From 0906a567e26a1b41fcdf1a217825e126872bda32 Mon Sep 17 00:00:00 2001 From: Mcu_sdk Ci Date: Wed, 22 May 2024 10:46:55 +0200 Subject: [PATCH] Apply MCUXpresso SDK 2.14.0 MCXN23X release update The update sources are from MCUXpresso SDK 2.14.0 MCXN23X release update --- SW-Content-Register.txt | 614 +- boards/frdmmcxn236/board.c | 181 + boards/frdmmcxn236/board.h | 179 + boards/frdmmcxn236/clock_config.c | 448 + boards/frdmmcxn236/clock_config.h | 177 + boards/frdmmcxn236/frdmmcxn236.png | Bin 0 -> 52000 bytes .../set_board_frdmmcxn236_fmstr.cmake | 2 + boards/frdmmcxn236/project_template/board.c | 181 + boards/frdmmcxn236/project_template/board.h | 179 + .../project_template/clock_config.c | 448 + .../project_template/clock_config.h | 177 + .../project_template/peripherals.c | 99 + .../project_template/peripherals.h | 39 + boards/frdmmcxn236/project_template/pin_mux.c | 382 + boards/frdmmcxn236/project_template/pin_mux.h | 134 + .../frdmmcxn236/set_board_frdmmcxn236.cmake | 31 + cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c | 10 +- cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.h | 6 +- cmsis_drivers/lpspi/fsl_lpspi_cmsis.c | 34 +- cmsis_drivers/lpspi/fsl_lpspi_cmsis.h | 4 +- cmsis_drivers/lpuart/fsl_lpuart_cmsis.c | 6 +- cmsis_drivers/lpuart/fsl_lpuart_cmsis.h | 6 +- components/audio/fsl_adapter_audio.h | 10 +- components/audio/fsl_adapter_sai.c | 96 +- components/button/fsl_component_button.c | 16 +- components/codec/da7212/fsl_dialog7212.c | 2 + components/codec/da7212/fsl_dialog7212.h | 19 +- components/codec/fsl_codec_common.h | 96 +- .../port/da7212/fsl_codec_da7212_adapter.c | 13 +- components/codec/port/fsl_codec_adapter.c | 132 +- components/codec/port/fsl_codec_adapter.h | 30 + .../port/sgtl5000/fsl_codec_sgtl_adapter.c | 23 +- .../port/wm8904/fsl_codec_wm8904_adapter.c | 51 +- .../port/wm8960/fsl_codec_wm8960_adapter.c | 52 +- .../port/wm8960/fsl_codec_wm8960_adapter.h | 4 +- components/codec/sgtl5000/fsl_sgtl5000.h | 8 +- components/codec/wm8904/fsl_wm8904.c | 26 +- components/codec/wm8904/fsl_wm8904.h | 12 +- components/codec/wm8960/fsl_wm8960.c | 4 +- components/codec/wm8960/fsl_wm8960.h | 4 +- components/els_pkc/LICENSE.htm | 3757 + components/els_pkc/ReleaseNotes.txt | 97 + components/els_pkc/doc/mcxn/html/a00002.html | 293 + components/els_pkc/doc/mcxn/html/a00002.js | 8 + components/els_pkc/doc/mcxn/html/a00005.html | 322 + components/els_pkc/doc/mcxn/html/a00005.js | 9 + components/els_pkc/doc/mcxn/html/a00008.html | 330 + components/els_pkc/doc/mcxn/html/a00008.js | 9 + components/els_pkc/doc/mcxn/html/a00011.html | 162 + components/els_pkc/doc/mcxn/html/a00011.js | 4 + components/els_pkc/doc/mcxn/html/a00014.html | 264 + components/els_pkc/doc/mcxn/html/a00014.js | 7 + components/els_pkc/doc/mcxn/html/a00017.html | 264 + components/els_pkc/doc/mcxn/html/a00017.js | 7 + components/els_pkc/doc/mcxn/html/a00020.html | 264 + components/els_pkc/doc/mcxn/html/a00020.js | 7 + components/els_pkc/doc/mcxn/html/a00023.html | 264 + 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.../els_pkc/doc/mcxn/html/a00359_source.html | 137 + components/els_pkc/doc/mcxn/html/a00362.html | 290 + components/els_pkc/doc/mcxn/html/a00362.js | 12 + .../els_pkc/doc/mcxn/html/a00362_source.html | 121 + components/els_pkc/doc/mcxn/html/a00365.html | 151 + components/els_pkc/doc/mcxn/html/a00365.js | 8 + .../els_pkc/doc/mcxn/html/a00365_source.html | 126 + .../els_pkc/doc/mcxn/html/a00368_source.html | 124 + components/els_pkc/doc/mcxn/html/a00371.html | 162 + components/els_pkc/doc/mcxn/html/a00371.js | 11 + .../els_pkc/doc/mcxn/html/a00371_source.html | 132 + components/els_pkc/doc/mcxn/html/a00374.html | 186 + components/els_pkc/doc/mcxn/html/a00374.js | 20 + .../els_pkc/doc/mcxn/html/a00374_source.html | 121 + .../els_pkc/doc/mcxn/html/a00377_source.html | 122 + components/els_pkc/doc/mcxn/html/a00380.html | 248 + components/els_pkc/doc/mcxn/html/a00380.js | 41 + .../els_pkc/doc/mcxn/html/a00380_source.html | 121 + .../els_pkc/doc/mcxn/html/a00383_source.html | 126 + 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components/els_pkc/doc/mcxn/html/a00428.html | 162 + components/els_pkc/doc/mcxn/html/a00428.js | 10 + .../els_pkc/doc/mcxn/html/a00428_source.html | 131 + .../els_pkc/doc/mcxn/html/a00431_source.html | 124 + components/els_pkc/doc/mcxn/html/a00434.html | 153 + components/els_pkc/doc/mcxn/html/a00434.js | 9 + .../els_pkc/doc/mcxn/html/a00434_source.html | 121 + components/els_pkc/doc/mcxn/html/a00437.html | 134 + .../els_pkc/doc/mcxn/html/a00437_source.html | 125 + components/els_pkc/doc/mcxn/html/a00440.html | 173 + components/els_pkc/doc/mcxn/html/a00440.js | 16 + .../els_pkc/doc/mcxn/html/a00440_source.html | 121 + .../els_pkc/doc/mcxn/html/a00443_source.html | 132 + components/els_pkc/doc/mcxn/html/a00446.html | 131 + .../els_pkc/doc/mcxn/html/a00446_source.html | 122 + components/els_pkc/doc/mcxn/html/a00449.html | 243 + components/els_pkc/doc/mcxn/html/a00449.js | 36 + .../els_pkc/doc/mcxn/html/a00449_source.html | 142 + .../els_pkc/doc/mcxn/html/a00452_source.html | 126 + components/els_pkc/doc/mcxn/html/a00455.html | 137 + .../els_pkc/doc/mcxn/html/a00455_source.html | 129 + components/els_pkc/doc/mcxn/html/a00458.html | 151 + components/els_pkc/doc/mcxn/html/a00458.js | 6 + .../els_pkc/doc/mcxn/html/a00458_source.html | 125 + components/els_pkc/doc/mcxn/html/a00461.html | 151 + components/els_pkc/doc/mcxn/html/a00461.js | 6 + .../els_pkc/doc/mcxn/html/a00461_source.html | 125 + components/els_pkc/doc/mcxn/html/a00464.html | 148 + components/els_pkc/doc/mcxn/html/a00464.js | 5 + .../els_pkc/doc/mcxn/html/a00464_source.html | 125 + components/els_pkc/doc/mcxn/html/a00467.html | 152 + components/els_pkc/doc/mcxn/html/a00467.js | 8 + .../els_pkc/doc/mcxn/html/a00467_source.html | 122 + components/els_pkc/doc/mcxn/html/a00470.html | 151 + components/els_pkc/doc/mcxn/html/a00470.js | 6 + .../els_pkc/doc/mcxn/html/a00470_source.html | 125 + components/els_pkc/doc/mcxn/html/a00473.html | 159 + components/els_pkc/doc/mcxn/html/a00473.js | 8 + .../els_pkc/doc/mcxn/html/a00473_source.html | 126 + components/els_pkc/doc/mcxn/html/a00476.html | 1032 + components/els_pkc/doc/mcxn/html/a00476.js | 302 + .../els_pkc/doc/mcxn/html/a00476_source.html | 121 + components/els_pkc/doc/mcxn/html/a00479.html | 162 + components/els_pkc/doc/mcxn/html/a00479.js | 10 + .../els_pkc/doc/mcxn/html/a00479_source.html | 125 + components/els_pkc/doc/mcxn/html/a00482.html | 185 + components/els_pkc/doc/mcxn/html/a00482.js | 9 + .../els_pkc/doc/mcxn/html/a00482_source.html | 123 + components/els_pkc/doc/mcxn/html/a00485.html | 183 + components/els_pkc/doc/mcxn/html/a00485.js | 6 + .../els_pkc/doc/mcxn/html/a00485_source.html | 126 + components/els_pkc/doc/mcxn/html/a00488.html | 131 + .../els_pkc/doc/mcxn/html/a00488_source.html | 123 + components/els_pkc/doc/mcxn/html/a00491.html | 241 + components/els_pkc/doc/mcxn/html/a00491.js | 32 + .../els_pkc/doc/mcxn/html/a00491_source.html | 128 + components/els_pkc/doc/mcxn/html/a00494.html | 179 + components/els_pkc/doc/mcxn/html/a00494.js | 6 + .../els_pkc/doc/mcxn/html/a00494_source.html | 123 + components/els_pkc/doc/mcxn/html/a00497.html | 132 + .../els_pkc/doc/mcxn/html/a00497_source.html | 124 + components/els_pkc/doc/mcxn/html/a00500.html | 130 + .../els_pkc/doc/mcxn/html/a00500_source.html | 124 + components/els_pkc/doc/mcxn/html/a00503.html | 137 + components/els_pkc/doc/mcxn/html/a00503.js | 4 + .../els_pkc/doc/mcxn/html/a00503_source.html | 121 + components/els_pkc/doc/mcxn/html/a00506.html | 167 + components/els_pkc/doc/mcxn/html/a00506.js | 14 + .../els_pkc/doc/mcxn/html/a00506_source.html | 121 + components/els_pkc/doc/mcxn/html/a00509.html | 132 + .../els_pkc/doc/mcxn/html/a00509_source.html | 125 + components/els_pkc/doc/mcxn/html/a00512.html | 147 + components/els_pkc/doc/mcxn/html/a00512.js | 7 + .../els_pkc/doc/mcxn/html/a00512_source.html | 121 + components/els_pkc/doc/mcxn/html/a00515.html | 139 + components/els_pkc/doc/mcxn/html/a00515.js | 4 + .../els_pkc/doc/mcxn/html/a00515_source.html | 122 + components/els_pkc/doc/mcxn/html/a00518.html | 131 + .../els_pkc/doc/mcxn/html/a00518_source.html | 123 + components/els_pkc/doc/mcxn/html/a00521.html | 214 + components/els_pkc/doc/mcxn/html/a00521.js | 23 + .../els_pkc/doc/mcxn/html/a00521_source.html | 144 + components/els_pkc/doc/mcxn/html/a00524.html | 169 + components/els_pkc/doc/mcxn/html/a00524.js | 12 + .../els_pkc/doc/mcxn/html/a00524_source.html | 126 + components/els_pkc/doc/mcxn/html/a00527.html | 132 + .../els_pkc/doc/mcxn/html/a00527_source.html | 124 + components/els_pkc/doc/mcxn/html/a00530.html | 150 + components/els_pkc/doc/mcxn/html/a00530.js | 8 + .../els_pkc/doc/mcxn/html/a00530_source.html | 121 + components/els_pkc/doc/mcxn/html/a00533.html | 161 + components/els_pkc/doc/mcxn/html/a00533.js | 11 + .../els_pkc/doc/mcxn/html/a00533_source.html | 137 + components/els_pkc/doc/mcxn/html/a00536.html | 161 + components/els_pkc/doc/mcxn/html/a00536.js | 9 + .../els_pkc/doc/mcxn/html/a00536_source.html | 129 + components/els_pkc/doc/mcxn/html/a00539.html | 132 + .../els_pkc/doc/mcxn/html/a00539_source.html | 123 + components/els_pkc/doc/mcxn/html/a00542.html | 142 + components/els_pkc/doc/mcxn/html/a00542.js | 5 + .../els_pkc/doc/mcxn/html/a00542_source.html | 125 + .../els_pkc/doc/mcxn/html/a00545_source.html | 129 + .../els_pkc/doc/mcxn/html/a00548_source.html | 128 + components/els_pkc/doc/mcxn/html/a00551.html | 170 + components/els_pkc/doc/mcxn/html/a00551.js | 15 + .../els_pkc/doc/mcxn/html/a00551_source.html | 121 + components/els_pkc/doc/mcxn/html/a00554.html | 134 + .../els_pkc/doc/mcxn/html/a00554_source.html | 125 + components/els_pkc/doc/mcxn/html/a00557.html | 189 + components/els_pkc/doc/mcxn/html/a00557.js | 21 + .../els_pkc/doc/mcxn/html/a00557_source.html | 140 + components/els_pkc/doc/mcxn/html/a00560.html | 153 + components/els_pkc/doc/mcxn/html/a00560.js | 7 + .../els_pkc/doc/mcxn/html/a00560_source.html | 141 + components/els_pkc/doc/mcxn/html/a00563.html | 353 + components/els_pkc/doc/mcxn/html/a00563.js | 76 + .../els_pkc/doc/mcxn/html/a00563_source.html | 121 + components/els_pkc/doc/mcxn/html/a00566.html | 224 + components/els_pkc/doc/mcxn/html/a00566.js | 26 + .../els_pkc/doc/mcxn/html/a00566_source.html | 142 + components/els_pkc/doc/mcxn/html/a00569.html | 131 + .../els_pkc/doc/mcxn/html/a00569_source.html | 123 + components/els_pkc/doc/mcxn/html/a00572.html | 150 + components/els_pkc/doc/mcxn/html/a00572.js | 7 + .../els_pkc/doc/mcxn/html/a00572_source.html | 135 + components/els_pkc/doc/mcxn/html/a00575.html | 128 + .../els_pkc/doc/mcxn/html/a00575_source.html | 121 + components/els_pkc/doc/mcxn/html/a00578.html | 193 + components/els_pkc/doc/mcxn/html/a00578.js | 16 + .../els_pkc/doc/mcxn/html/a00578_source.html | 145 + .../els_pkc/doc/mcxn/html/a00581_source.html | 121 + components/els_pkc/doc/mcxn/html/a00584.html | 326 + components/els_pkc/doc/mcxn/html/a00584.js | 67 + .../els_pkc/doc/mcxn/html/a00584_source.html | 121 + components/els_pkc/doc/mcxn/html/a00587.html | 160 + components/els_pkc/doc/mcxn/html/a00587.js | 11 + .../els_pkc/doc/mcxn/html/a00587_source.html | 123 + components/els_pkc/doc/mcxn/html/a00590.html | 140 + components/els_pkc/doc/mcxn/html/a00590.js | 5 + .../els_pkc/doc/mcxn/html/a00590_source.html | 121 + components/els_pkc/doc/mcxn/html/a00593.html | 130 + .../els_pkc/doc/mcxn/html/a00593_source.html | 123 + components/els_pkc/doc/mcxn/html/a00596.html | 155 + components/els_pkc/doc/mcxn/html/a00596.js | 10 + .../els_pkc/doc/mcxn/html/a00596_source.html | 121 + components/els_pkc/doc/mcxn/html/a00599.html | 246 + components/els_pkc/doc/mcxn/html/a00599.js | 40 + .../els_pkc/doc/mcxn/html/a00599_source.html | 122 + components/els_pkc/doc/mcxn/html/a00602.html | 143 + components/els_pkc/doc/mcxn/html/a00602.js | 6 + .../els_pkc/doc/mcxn/html/a00602_source.html | 121 + components/els_pkc/doc/mcxn/html/a00605.html | 438 + components/els_pkc/doc/mcxn/html/a00605.js | 104 + .../els_pkc/doc/mcxn/html/a00605_source.html | 121 + components/els_pkc/doc/mcxn/html/a00608.html | 132 + .../els_pkc/doc/mcxn/html/a00608_source.html | 125 + components/els_pkc/doc/mcxn/html/a00611.html | 386 + components/els_pkc/doc/mcxn/html/a00611.js | 73 + .../els_pkc/doc/mcxn/html/a00611_source.html | 123 + components/els_pkc/doc/mcxn/html/a00614.html | 236 + components/els_pkc/doc/mcxn/html/a00614.js | 26 + .../els_pkc/doc/mcxn/html/a00614_source.html | 123 + components/els_pkc/doc/mcxn/html/a00617.html | 133 + .../els_pkc/doc/mcxn/html/a00617_source.html | 126 + components/els_pkc/doc/mcxn/html/a00620.html | 142 + components/els_pkc/doc/mcxn/html/a00620.js | 4 + .../els_pkc/doc/mcxn/html/a00620_source.html | 129 + components/els_pkc/doc/mcxn/html/a00623.html | 141 + components/els_pkc/doc/mcxn/html/a00623.js | 4 + .../els_pkc/doc/mcxn/html/a00623_source.html | 129 + components/els_pkc/doc/mcxn/html/a00626.html | 137 + components/els_pkc/doc/mcxn/html/a00626.js | 4 + .../els_pkc/doc/mcxn/html/a00626_source.html | 126 + components/els_pkc/doc/mcxn/html/a00629.html | 142 + components/els_pkc/doc/mcxn/html/a00629.js | 4 + .../els_pkc/doc/mcxn/html/a00629_source.html | 129 + components/els_pkc/doc/mcxn/html/a00632.html | 163 + components/els_pkc/doc/mcxn/html/a00632.js | 11 + .../els_pkc/doc/mcxn/html/a00632_source.html | 122 + components/els_pkc/doc/mcxn/html/a00635.html | 174 + components/els_pkc/doc/mcxn/html/a00635.js | 10 + .../els_pkc/doc/mcxn/html/a00635_source.html | 129 + components/els_pkc/doc/mcxn/html/a00638.html | 186 + components/els_pkc/doc/mcxn/html/a00638.js | 20 + .../els_pkc/doc/mcxn/html/a00638_source.html | 122 + components/els_pkc/doc/mcxn/html/a00641.html | 161 + components/els_pkc/doc/mcxn/html/a00641.js | 12 + .../els_pkc/doc/mcxn/html/a00641_source.html | 121 + components/els_pkc/doc/mcxn/html/a00644.html | 130 + .../els_pkc/doc/mcxn/html/a00644_source.html | 124 + components/els_pkc/doc/mcxn/html/a00647.html | 191 + components/els_pkc/doc/mcxn/html/a00647.js | 22 + .../els_pkc/doc/mcxn/html/a00647_source.html | 121 + components/els_pkc/doc/mcxn/html/a00650.html | 194 + components/els_pkc/doc/mcxn/html/a00650.js | 23 + .../els_pkc/doc/mcxn/html/a00650_source.html | 121 + components/els_pkc/doc/mcxn/html/a00661.html | 152 + components/els_pkc/doc/mcxn/html/a00661.js | 8 + components/els_pkc/doc/mcxn/html/a00662.html | 134 + components/els_pkc/doc/mcxn/html/a00662.js | 4 + components/els_pkc/doc/mcxn/html/a00663.html | 143 + components/els_pkc/doc/mcxn/html/a00664.html | 268 + components/els_pkc/doc/mcxn/html/a00664.js | 5 + components/els_pkc/doc/mcxn/html/a00665.html | 478 + components/els_pkc/doc/mcxn/html/a00665.js | 8 + components/els_pkc/doc/mcxn/html/a00666.html | 252 + components/els_pkc/doc/mcxn/html/a00666.js | 9 + components/els_pkc/doc/mcxn/html/a00667.html | 203 + components/els_pkc/doc/mcxn/html/a00667.js | 4 + components/els_pkc/doc/mcxn/html/a00668.html | 124 + components/els_pkc/doc/mcxn/html/a00669.html | 286 + components/els_pkc/doc/mcxn/html/a00669.js | 11 + components/els_pkc/doc/mcxn/html/a00670.html | 272 + components/els_pkc/doc/mcxn/html/a00670.js | 9 + components/els_pkc/doc/mcxn/html/a00671.html | 152 + components/els_pkc/doc/mcxn/html/a00671.js | 8 + components/els_pkc/doc/mcxn/html/a00672.html | 158 + components/els_pkc/doc/mcxn/html/a00673.html | 154 + components/els_pkc/doc/mcxn/html/a00673.js | 12 + components/els_pkc/doc/mcxn/html/a00674.html | 124 + components/els_pkc/doc/mcxn/html/a00675.html | 124 + components/els_pkc/doc/mcxn/html/a00676.html | 252 + components/els_pkc/doc/mcxn/html/a00676.js | 9 + components/els_pkc/doc/mcxn/html/a00677.html | 638 + components/els_pkc/doc/mcxn/html/a00677.js | 25 + components/els_pkc/doc/mcxn/html/a00678.html | 170 + components/els_pkc/doc/mcxn/html/a00678.js | 5 + components/els_pkc/doc/mcxn/html/a00679.html | 155 + components/els_pkc/doc/mcxn/html/a00679.js | 11 + components/els_pkc/doc/mcxn/html/a00680.html | 252 + components/els_pkc/doc/mcxn/html/a00681.html | 910 + components/els_pkc/doc/mcxn/html/a00681.js | 14 + components/els_pkc/doc/mcxn/html/a00682.html | 2997 + components/els_pkc/doc/mcxn/html/a00682.js | 127 + components/els_pkc/doc/mcxn/html/a00683.html | 195 + components/els_pkc/doc/mcxn/html/a00683.js | 12 + components/els_pkc/doc/mcxn/html/a00684.html | 230 + components/els_pkc/doc/mcxn/html/a00684.js | 36 + components/els_pkc/doc/mcxn/html/a00685.html | 180 + components/els_pkc/doc/mcxn/html/a00685.js | 7 + components/els_pkc/doc/mcxn/html/a00686.html | 485 + components/els_pkc/doc/mcxn/html/a00686.js | 56 + components/els_pkc/doc/mcxn/html/a00687.html | 157 + components/els_pkc/doc/mcxn/html/a00687.js | 4 + components/els_pkc/doc/mcxn/html/a00688.html | 340 + components/els_pkc/doc/mcxn/html/a00688.js | 15 + components/els_pkc/doc/mcxn/html/a00689.html | 140 + components/els_pkc/doc/mcxn/html/a00689.js | 6 + components/els_pkc/doc/mcxn/html/a00690.html | 213 + components/els_pkc/doc/mcxn/html/a00690.js | 8 + components/els_pkc/doc/mcxn/html/a00691.html | 379 + components/els_pkc/doc/mcxn/html/a00691.js | 16 + components/els_pkc/doc/mcxn/html/a00692.html | 134 + components/els_pkc/doc/mcxn/html/a00692.js | 18 + components/els_pkc/doc/mcxn/html/a00693.html | 671 + components/els_pkc/doc/mcxn/html/a00693.js | 8 + components/els_pkc/doc/mcxn/html/a00694.html | 140 + components/els_pkc/doc/mcxn/html/a00694.js | 6 + components/els_pkc/doc/mcxn/html/a00695.html | 161 + components/els_pkc/doc/mcxn/html/a00695.js | 6 + components/els_pkc/doc/mcxn/html/a00696.html | 350 + components/els_pkc/doc/mcxn/html/a00696.js | 14 + components/els_pkc/doc/mcxn/html/a00697.html | 191 + components/els_pkc/doc/mcxn/html/a00697.js | 6 + components/els_pkc/doc/mcxn/html/a00698.html | 134 + components/els_pkc/doc/mcxn/html/a00698.js | 16 + components/els_pkc/doc/mcxn/html/a00699.html | 252 + components/els_pkc/doc/mcxn/html/a00699.js | 4 + components/els_pkc/doc/mcxn/html/a00700.html | 140 + components/els_pkc/doc/mcxn/html/a00700.js | 6 + components/els_pkc/doc/mcxn/html/a00701.html | 159 + components/els_pkc/doc/mcxn/html/a00701.js | 6 + components/els_pkc/doc/mcxn/html/a00702.html | 170 + components/els_pkc/doc/mcxn/html/a00702.js | 5 + components/els_pkc/doc/mcxn/html/a00703.html | 246 + components/els_pkc/doc/mcxn/html/a00703.js | 9 + components/els_pkc/doc/mcxn/html/a00704.html | 134 + components/els_pkc/doc/mcxn/html/a00704.js | 15 + components/els_pkc/doc/mcxn/html/a00705.html | 241 + components/els_pkc/doc/mcxn/html/a00705.js | 4 + components/els_pkc/doc/mcxn/html/a00706.html | 140 + components/els_pkc/doc/mcxn/html/a00706.js | 6 + components/els_pkc/doc/mcxn/html/a00707.html | 201 + components/els_pkc/doc/mcxn/html/a00707.js | 13 + components/els_pkc/doc/mcxn/html/a00708.html | 170 + components/els_pkc/doc/mcxn/html/a00708.js | 5 + components/els_pkc/doc/mcxn/html/a00709.html | 170 + components/els_pkc/doc/mcxn/html/a00709.js | 5 + components/els_pkc/doc/mcxn/html/a00710.html | 170 + components/els_pkc/doc/mcxn/html/a00710.js | 5 + components/els_pkc/doc/mcxn/html/a00711.html | 172 + components/els_pkc/doc/mcxn/html/a00711.js | 5 + components/els_pkc/doc/mcxn/html/a00712.html | 172 + components/els_pkc/doc/mcxn/html/a00712.js | 5 + components/els_pkc/doc/mcxn/html/a00713.html | 210 + components/els_pkc/doc/mcxn/html/a00713.js | 7 + components/els_pkc/doc/mcxn/html/a00714.html | 210 + components/els_pkc/doc/mcxn/html/a00714.js | 7 + components/els_pkc/doc/mcxn/html/a00715.html | 189 + components/els_pkc/doc/mcxn/html/a00715.js | 6 + components/els_pkc/doc/mcxn/html/a00716.html | 220 + components/els_pkc/doc/mcxn/html/a00716.js | 85 + components/els_pkc/doc/mcxn/html/a00717.html | 684 + components/els_pkc/doc/mcxn/html/a00717.js | 19 + components/els_pkc/doc/mcxn/html/a00718.html | 140 + components/els_pkc/doc/mcxn/html/a00718.js | 6 + components/els_pkc/doc/mcxn/html/a00719.html | 140 + components/els_pkc/doc/mcxn/html/a00719.js | 6 + components/els_pkc/doc/mcxn/html/a00720.html | 284 + components/els_pkc/doc/mcxn/html/a00720.js | 11 + components/els_pkc/doc/mcxn/html/a00721.html | 1009 + components/els_pkc/doc/mcxn/html/a00721.js | 35 + components/els_pkc/doc/mcxn/html/a00722.html | 569 + components/els_pkc/doc/mcxn/html/a00722.js | 26 + components/els_pkc/doc/mcxn/html/a00723.html | 134 + components/els_pkc/doc/mcxn/html/a00723.js | 11 + components/els_pkc/doc/mcxn/html/a00724.html | 285 + components/els_pkc/doc/mcxn/html/a00724.js | 7 + components/els_pkc/doc/mcxn/html/a00725.html | 140 + components/els_pkc/doc/mcxn/html/a00725.js | 6 + components/els_pkc/doc/mcxn/html/a00726.html | 149 + components/els_pkc/doc/mcxn/html/a00726.js | 9 + components/els_pkc/doc/mcxn/html/a00727.html | 208 + components/els_pkc/doc/mcxn/html/a00727.js | 7 + components/els_pkc/doc/mcxn/html/a00728.html | 303 + components/els_pkc/doc/mcxn/html/a00728.js | 12 + components/els_pkc/doc/mcxn/html/a00729.html | 210 + components/els_pkc/doc/mcxn/html/a00729.js | 7 + components/els_pkc/doc/mcxn/html/a00730.html | 334 + components/els_pkc/doc/mcxn/html/a00730.js | 13 + components/els_pkc/doc/mcxn/html/a00731.html | 170 + components/els_pkc/doc/mcxn/html/a00731.js | 5 + components/els_pkc/doc/mcxn/html/a00732.html | 195 + components/els_pkc/doc/mcxn/html/a00732.js | 6 + components/els_pkc/doc/mcxn/html/a00733.html | 168 + components/els_pkc/doc/mcxn/html/a00733.js | 45 + components/els_pkc/doc/mcxn/html/a00734.html | 492 + components/els_pkc/doc/mcxn/html/a00734.js | 7 + components/els_pkc/doc/mcxn/html/a00735.html | 140 + components/els_pkc/doc/mcxn/html/a00735.js | 6 + components/els_pkc/doc/mcxn/html/a00736.html | 161 + components/els_pkc/doc/mcxn/html/a00736.js | 8 + components/els_pkc/doc/mcxn/html/a00737.html | 486 + components/els_pkc/doc/mcxn/html/a00737.js | 21 + components/els_pkc/doc/mcxn/html/a00738.html | 216 + components/els_pkc/doc/mcxn/html/a00738.js | 7 + components/els_pkc/doc/mcxn/html/a00739.html | 216 + components/els_pkc/doc/mcxn/html/a00739.js | 7 + components/els_pkc/doc/mcxn/html/a00740.html | 216 + components/els_pkc/doc/mcxn/html/a00740.js | 7 + components/els_pkc/doc/mcxn/html/a00741.html | 134 + components/els_pkc/doc/mcxn/html/a00741.js | 16 + components/els_pkc/doc/mcxn/html/a00742.html | 221 + components/els_pkc/doc/mcxn/html/a00742.js | 4 + components/els_pkc/doc/mcxn/html/a00743.html | 140 + components/els_pkc/doc/mcxn/html/a00743.js | 6 + components/els_pkc/doc/mcxn/html/a00744.html | 175 + components/els_pkc/doc/mcxn/html/a00744.js | 6 + components/els_pkc/doc/mcxn/html/a00745.html | 170 + components/els_pkc/doc/mcxn/html/a00745.js | 5 + components/els_pkc/doc/mcxn/html/a00746.html | 134 + components/els_pkc/doc/mcxn/html/a00746.js | 11 + components/els_pkc/doc/mcxn/html/a00747.html | 233 + components/els_pkc/doc/mcxn/html/a00747.js | 4 + components/els_pkc/doc/mcxn/html/a00748.html | 137 + components/els_pkc/doc/mcxn/html/a00748.js | 5 + components/els_pkc/doc/mcxn/html/a00749.html | 137 + components/els_pkc/doc/mcxn/html/a00749.js | 5 + components/els_pkc/doc/mcxn/html/a00750.html | 402 + components/els_pkc/doc/mcxn/html/a00750.js | 17 + components/els_pkc/doc/mcxn/html/a00751.html | 140 + components/els_pkc/doc/mcxn/html/a00751.js | 27 + components/els_pkc/doc/mcxn/html/a00752.html | 458 + components/els_pkc/doc/mcxn/html/a00752.js | 8 + components/els_pkc/doc/mcxn/html/a00753.html | 140 + components/els_pkc/doc/mcxn/html/a00753.js | 6 + components/els_pkc/doc/mcxn/html/a00754.html | 140 + components/els_pkc/doc/mcxn/html/a00754.js | 6 + components/els_pkc/doc/mcxn/html/a00755.html | 189 + components/els_pkc/doc/mcxn/html/a00755.js | 6 + components/els_pkc/doc/mcxn/html/a00756.html | 210 + components/els_pkc/doc/mcxn/html/a00756.js | 7 + components/els_pkc/doc/mcxn/html/a00757.html | 170 + components/els_pkc/doc/mcxn/html/a00757.js | 5 + components/els_pkc/doc/mcxn/html/a00758.html | 134 + components/els_pkc/doc/mcxn/html/a00758.js | 13 + components/els_pkc/doc/mcxn/html/a00759.html | 380 + components/els_pkc/doc/mcxn/html/a00759.js | 7 + components/els_pkc/doc/mcxn/html/a00760.html | 137 + components/els_pkc/doc/mcxn/html/a00760.js | 5 + components/els_pkc/doc/mcxn/html/a00761.html | 303 + components/els_pkc/doc/mcxn/html/a00761.js | 12 + components/els_pkc/doc/mcxn/html/a00762.html | 605 + components/els_pkc/doc/mcxn/html/a00762.js | 12 + components/els_pkc/doc/mcxn/html/a00763.html | 137 + components/els_pkc/doc/mcxn/html/a00763.js | 5 + components/els_pkc/doc/mcxn/html/a00764.html | 210 + components/els_pkc/doc/mcxn/html/a00764.js | 9 + components/els_pkc/doc/mcxn/html/a00765.html | 664 + components/els_pkc/doc/mcxn/html/a00765.js | 31 + components/els_pkc/doc/mcxn/html/a00766.html | 1108 + components/els_pkc/doc/mcxn/html/a00766.js | 53 + components/els_pkc/doc/mcxn/html/a00767.html | 421 + components/els_pkc/doc/mcxn/html/a00767.js | 18 + components/els_pkc/doc/mcxn/html/a00768.html | 250 + components/els_pkc/doc/mcxn/html/a00768.js | 40 + components/els_pkc/doc/mcxn/html/a00769.html | 145 + components/els_pkc/doc/mcxn/html/a00769.js | 6 + components/els_pkc/doc/mcxn/html/a00770.html | 146 + components/els_pkc/doc/mcxn/html/a00770.js | 8 + components/els_pkc/doc/mcxn/html/a00771.html | 348 + components/els_pkc/doc/mcxn/html/a00771.js | 15 + components/els_pkc/doc/mcxn/html/a00772.html | 403 + components/els_pkc/doc/mcxn/html/a00772.js | 7 + components/els_pkc/doc/mcxn/html/a00773.html | 232 + components/els_pkc/doc/mcxn/html/a00773.js | 8 + components/els_pkc/doc/mcxn/html/a00774.html | 324 + components/els_pkc/doc/mcxn/html/a00774.js | 11 + components/els_pkc/doc/mcxn/html/a00775.html | 455 + components/els_pkc/doc/mcxn/html/a00775.js | 20 + components/els_pkc/doc/mcxn/html/a00776.html | 702 + components/els_pkc/doc/mcxn/html/a00776.js | 33 + components/els_pkc/doc/mcxn/html/a00777.html | 220 + components/els_pkc/doc/mcxn/html/a00777.js | 7 + components/els_pkc/doc/mcxn/html/a00778.html | 192 + components/els_pkc/doc/mcxn/html/a00778.js | 5 + components/els_pkc/doc/mcxn/html/a00779.html | 134 + components/els_pkc/doc/mcxn/html/a00779.js | 4 + components/els_pkc/doc/mcxn/html/a00780.html | 175 + components/els_pkc/doc/mcxn/html/a00780.js | 4 + components/els_pkc/doc/mcxn/html/a00781.html | 224 + components/els_pkc/doc/mcxn/html/a00781.js | 7 + components/els_pkc/doc/mcxn/html/a00782.html | 209 + components/els_pkc/doc/mcxn/html/a00782.js | 4 + components/els_pkc/doc/mcxn/html/a00783.html | 124 + components/els_pkc/doc/mcxn/html/a00784.html | 147 + components/els_pkc/doc/mcxn/html/a00784.js | 8 + components/els_pkc/doc/mcxn/html/a00785.html | 186 + components/els_pkc/doc/mcxn/html/a00785.js | 9 + components/els_pkc/doc/mcxn/html/a00786.html | 267 + components/els_pkc/doc/mcxn/html/a00786.js | 10 + components/els_pkc/doc/mcxn/html/a00787.html | 208 + components/els_pkc/doc/mcxn/html/a00787.js | 7 + components/els_pkc/doc/mcxn/html/a00788.html | 499 + components/els_pkc/doc/mcxn/html/a00788.js | 22 + components/els_pkc/doc/mcxn/html/a00789.html | 725 + components/els_pkc/doc/mcxn/html/a00789.js | 34 + components/els_pkc/doc/mcxn/html/a00790.html | 536 + components/els_pkc/doc/mcxn/html/a00790.js | 10 + components/els_pkc/doc/mcxn/html/a00791.html | 149 + components/els_pkc/doc/mcxn/html/a00792.html | 226 + components/els_pkc/doc/mcxn/html/a00792.js | 7 + components/els_pkc/doc/mcxn/html/a00793.html | 392 + components/els_pkc/doc/mcxn/html/a00793.js | 16 + components/els_pkc/doc/mcxn/html/a00794.html | 144 + components/els_pkc/doc/mcxn/html/a00794.js | 6 + components/els_pkc/doc/mcxn/html/a00795.html | 149 + components/els_pkc/doc/mcxn/html/a00796.html | 137 + components/els_pkc/doc/mcxn/html/a00796.js | 5 + components/els_pkc/doc/mcxn/html/a00797.html | 225 + components/els_pkc/doc/mcxn/html/a00797.js | 4 + components/els_pkc/doc/mcxn/html/a00798.html | 347 + components/els_pkc/doc/mcxn/html/a00798.js | 6 + components/els_pkc/doc/mcxn/html/a00799.html | 272 + components/els_pkc/doc/mcxn/html/a00799.js | 10 + components/els_pkc/doc/mcxn/html/a00800.html | 214 + components/els_pkc/doc/mcxn/html/a00800.js | 7 + components/els_pkc/doc/mcxn/html/a00801.html | 134 + components/els_pkc/doc/mcxn/html/a00801.js | 4 + components/els_pkc/doc/mcxn/html/a00802.html | 124 + components/els_pkc/doc/mcxn/html/a00803.html | 170 + components/els_pkc/doc/mcxn/html/a00804.html | 316 + components/els_pkc/doc/mcxn/html/a00804.js | 11 + components/els_pkc/doc/mcxn/html/a00805.html | 137 + components/els_pkc/doc/mcxn/html/a00805.js | 5 + components/els_pkc/doc/mcxn/html/a00806.html | 2169 + components/els_pkc/doc/mcxn/html/a00806.js | 36 + components/els_pkc/doc/mcxn/html/a00807.html | 265 + components/els_pkc/doc/mcxn/html/a00807.js | 10 + components/els_pkc/doc/mcxn/html/a00808.html | 150 + components/els_pkc/doc/mcxn/html/a00808.js | 9 + components/els_pkc/doc/mcxn/html/a00809.html | 257 + components/els_pkc/doc/mcxn/html/a00809.js | 6 + components/els_pkc/doc/mcxn/html/a00810.html | 279 + components/els_pkc/doc/mcxn/html/a00810.js | 6 + components/els_pkc/doc/mcxn/html/a00811.html | 231 + components/els_pkc/doc/mcxn/html/a00811.js | 5 + components/els_pkc/doc/mcxn/html/a00812.html | 302 + components/els_pkc/doc/mcxn/html/a00812.js | 8 + components/els_pkc/doc/mcxn/html/a00813.html | 278 + components/els_pkc/doc/mcxn/html/a00813.js | 6 + components/els_pkc/doc/mcxn/html/a00814.html | 178 + components/els_pkc/doc/mcxn/html/a00814.js | 6 + components/els_pkc/doc/mcxn/html/a00815.html | 177 + components/els_pkc/doc/mcxn/html/a00815.js | 6 + components/els_pkc/doc/mcxn/html/a00816.html | 151 + components/els_pkc/doc/mcxn/html/a00816.js | 4 + components/els_pkc/doc/mcxn/html/a00817.html | 134 + components/els_pkc/doc/mcxn/html/a00817.js | 4 + components/els_pkc/doc/mcxn/html/a00818.html | 266 + components/els_pkc/doc/mcxn/html/a00818.js | 9 + components/els_pkc/doc/mcxn/html/a00819.html | 129 + components/els_pkc/doc/mcxn/html/a00820.html | 124 + components/els_pkc/doc/mcxn/html/a00821.html | 151 + components/els_pkc/doc/mcxn/html/a00821.js | 4 + components/els_pkc/doc/mcxn/html/a00822.html | 284 + components/els_pkc/doc/mcxn/html/a00822.js | 11 + components/els_pkc/doc/mcxn/html/a00823.html | 173 + components/els_pkc/doc/mcxn/html/a00823.js | 5 + components/els_pkc/doc/mcxn/html/a00824.html | 209 + components/els_pkc/doc/mcxn/html/a00824.js | 7 + components/els_pkc/doc/mcxn/html/a00825.html | 152 + components/els_pkc/doc/mcxn/html/a00825.js | 4 + components/els_pkc/doc/mcxn/html/a00826.html | 137 + components/els_pkc/doc/mcxn/html/a00826.js | 5 + components/els_pkc/doc/mcxn/html/a00827.html | 143 + components/els_pkc/doc/mcxn/html/a00827.js | 7 + components/els_pkc/doc/mcxn/html/a00828.html | 137 + components/els_pkc/doc/mcxn/html/a00828.js | 5 + components/els_pkc/doc/mcxn/html/a00829.html | 152 + components/els_pkc/doc/mcxn/html/a00829.js | 10 + components/els_pkc/doc/mcxn/html/a00830.html | 134 + components/els_pkc/doc/mcxn/html/a00830.js | 4 + components/els_pkc/doc/mcxn/html/a00831.html | 469 + components/els_pkc/doc/mcxn/html/a00831.js | 11 + components/els_pkc/doc/mcxn/html/a00832.html | 261 + components/els_pkc/doc/mcxn/html/a00832.js | 13 + components/els_pkc/doc/mcxn/html/a00833.html | 155 + components/els_pkc/doc/mcxn/html/a00833.js | 4 + components/els_pkc/doc/mcxn/html/a00834.html | 124 + components/els_pkc/doc/mcxn/html/a00835.html | 124 + components/els_pkc/doc/mcxn/html/a00836.html | 124 + components/els_pkc/doc/mcxn/html/a00837.html | 124 + components/els_pkc/doc/mcxn/html/a00838.html | 167 + components/els_pkc/doc/mcxn/html/a00839.html | 162 + components/els_pkc/doc/mcxn/html/a00839.js | 7 + components/els_pkc/doc/mcxn/html/a00840.html | 137 + components/els_pkc/doc/mcxn/html/a00840.js | 5 + components/els_pkc/doc/mcxn/html/a00841.html | 307 + components/els_pkc/doc/mcxn/html/a00841.js | 12 + components/els_pkc/doc/mcxn/html/a00842.html | 307 + components/els_pkc/doc/mcxn/html/a00842.js | 12 + components/els_pkc/doc/mcxn/html/a00843.html | 675 + components/els_pkc/doc/mcxn/html/a00843.js | 7 + components/els_pkc/doc/mcxn/html/a00844.html | 932 + components/els_pkc/doc/mcxn/html/a00844.js | 43 + components/els_pkc/doc/mcxn/html/a00845.html | 294 + components/els_pkc/doc/mcxn/html/a00845.js | 11 + components/els_pkc/doc/mcxn/html/a00846.html | 292 + components/els_pkc/doc/mcxn/html/a00846.js | 11 + components/els_pkc/doc/mcxn/html/a00847.html | 292 + components/els_pkc/doc/mcxn/html/a00847.js | 11 + components/els_pkc/doc/mcxn/html/a00848.html | 303 + components/els_pkc/doc/mcxn/html/a00848.js | 12 + components/els_pkc/doc/mcxn/html/a00849.html | 155 + components/els_pkc/doc/mcxn/html/a00849.js | 11 + components/els_pkc/doc/mcxn/html/a00850.html | 328 + components/els_pkc/doc/mcxn/html/a00850.js | 13 + components/els_pkc/doc/mcxn/html/a00851.html | 212 + components/els_pkc/doc/mcxn/html/a00851.js | 7 + components/els_pkc/doc/mcxn/html/a00852.html | 191 + components/els_pkc/doc/mcxn/html/a00852.js | 6 + components/els_pkc/doc/mcxn/html/a00853.html | 256 + components/els_pkc/doc/mcxn/html/a00853.js | 22 + components/els_pkc/doc/mcxn/html/a00854.html | 163 + components/els_pkc/doc/mcxn/html/a00854.js | 6 + components/els_pkc/doc/mcxn/html/a00855.html | 326 + components/els_pkc/doc/mcxn/html/a00855.js | 7 + components/els_pkc/doc/mcxn/html/a00856.html | 135 + components/els_pkc/doc/mcxn/html/a00856.js | 5 + components/els_pkc/doc/mcxn/html/a00857.html | 187 + components/els_pkc/doc/mcxn/html/a00857.js | 6 + components/els_pkc/doc/mcxn/html/a00858.html | 166 + components/els_pkc/doc/mcxn/html/a00858.js | 5 + components/els_pkc/doc/mcxn/html/a00859.html | 297 + components/els_pkc/doc/mcxn/html/a00859.js | 26 + components/els_pkc/doc/mcxn/html/a00860.html | 142 + components/els_pkc/doc/mcxn/html/a00860.js | 8 + components/els_pkc/doc/mcxn/html/a00861.html | 137 + components/els_pkc/doc/mcxn/html/a00861.js | 5 + components/els_pkc/doc/mcxn/html/a00862.html | 270 + components/els_pkc/doc/mcxn/html/a00862.js | 9 + components/els_pkc/doc/mcxn/html/a00863.html | 212 + components/els_pkc/doc/mcxn/html/a00863.js | 5 + components/els_pkc/doc/mcxn/html/a00864.html | 136 + components/els_pkc/doc/mcxn/html/a00864.js | 6 + components/els_pkc/doc/mcxn/html/a00865.html | 170 + components/els_pkc/doc/mcxn/html/a00865.js | 5 + components/els_pkc/doc/mcxn/html/a00866.html | 139 + components/els_pkc/doc/mcxn/html/a00866.js | 7 + components/els_pkc/doc/mcxn/html/a00867.html | 137 + components/els_pkc/doc/mcxn/html/a00867.js | 5 + components/els_pkc/doc/mcxn/html/a00868.html | 251 + components/els_pkc/doc/mcxn/html/a00868.js | 8 + components/els_pkc/doc/mcxn/html/a00869.html | 212 + components/els_pkc/doc/mcxn/html/a00869.js | 5 + components/els_pkc/doc/mcxn/html/a00870.html | 149 + components/els_pkc/doc/mcxn/html/a00870.js | 9 + components/els_pkc/doc/mcxn/html/a00871.html | 127 + components/els_pkc/doc/mcxn/html/a00872.html | 911 + components/els_pkc/doc/mcxn/html/a00872.js | 24 + components/els_pkc/doc/mcxn/html/a00873.html | 250 + components/els_pkc/doc/mcxn/html/a00873.js | 6 + components/els_pkc/doc/mcxn/html/a00874.html | 328 + components/els_pkc/doc/mcxn/html/a00874.js | 8 + components/els_pkc/doc/mcxn/html/a00875.html | 326 + components/els_pkc/doc/mcxn/html/a00875.js | 8 + components/els_pkc/doc/mcxn/html/a00876.html | 267 + components/els_pkc/doc/mcxn/html/a00876.js | 6 + components/els_pkc/doc/mcxn/html/a00877.html | 189 + components/els_pkc/doc/mcxn/html/a00877.js | 6 + components/els_pkc/doc/mcxn/html/a00878.html | 149 + components/els_pkc/doc/mcxn/html/a00878.js | 9 + components/els_pkc/doc/mcxn/html/a00879.html | 281 + components/els_pkc/doc/mcxn/html/a00879.js | 7 + components/els_pkc/doc/mcxn/html/a00880.html | 273 + components/els_pkc/doc/mcxn/html/a00880.js | 8 + components/els_pkc/doc/mcxn/html/a00881.html | 1386 + components/els_pkc/doc/mcxn/html/a00881.js | 41 + components/els_pkc/doc/mcxn/html/a00882.html | 371 + components/els_pkc/doc/mcxn/html/a00882.js | 10 + components/els_pkc/doc/mcxn/html/a00883.html | 800 + components/els_pkc/doc/mcxn/html/a00883.js | 22 + components/els_pkc/doc/mcxn/html/a00884.html | 719 + components/els_pkc/doc/mcxn/html/a00884.js | 19 + components/els_pkc/doc/mcxn/html/a00885.html | 146 + components/els_pkc/doc/mcxn/html/a00885.js | 8 + components/els_pkc/doc/mcxn/html/a00886.html | 134 + components/els_pkc/doc/mcxn/html/a00886.js | 4 + components/els_pkc/doc/mcxn/html/a00887.html | 196 + components/els_pkc/doc/mcxn/html/a00887.js | 4 + components/els_pkc/doc/mcxn/html/a00888.html | 134 + components/els_pkc/doc/mcxn/html/a00888.js | 4 + components/els_pkc/doc/mcxn/html/a00889.html | 202 + components/els_pkc/doc/mcxn/html/a00889.js | 4 + components/els_pkc/doc/mcxn/html/a00890.html | 134 + components/els_pkc/doc/mcxn/html/a00890.js | 4 + components/els_pkc/doc/mcxn/html/a00891.html | 209 + components/els_pkc/doc/mcxn/html/a00891.js | 4 + components/els_pkc/doc/mcxn/html/a00892.html | 134 + components/els_pkc/doc/mcxn/html/a00892.js | 4 + components/els_pkc/doc/mcxn/html/a00893.html | 203 + components/els_pkc/doc/mcxn/html/a00893.js | 4 + components/els_pkc/doc/mcxn/html/a00894.html | 137 + components/els_pkc/doc/mcxn/html/a00894.js | 5 + components/els_pkc/doc/mcxn/html/a00895.html | 265 + components/els_pkc/doc/mcxn/html/a00895.js | 10 + components/els_pkc/doc/mcxn/html/a00896.html | 151 + components/els_pkc/doc/mcxn/html/a00896.js | 4 + components/els_pkc/doc/mcxn/html/a00897.html | 140 + components/els_pkc/doc/mcxn/html/a00897.js | 6 + components/els_pkc/doc/mcxn/html/a00898.html | 189 + components/els_pkc/doc/mcxn/html/a00898.js | 6 + components/els_pkc/doc/mcxn/html/a00899.html | 170 + components/els_pkc/doc/mcxn/html/a00899.js | 5 + components/els_pkc/doc/mcxn/html/a00900.html | 228 + components/els_pkc/doc/mcxn/html/a00900.js | 5 + components/els_pkc/doc/mcxn/html/a00901.html | 143 + components/els_pkc/doc/mcxn/html/a00901.js | 7 + components/els_pkc/doc/mcxn/html/a00902.html | 270 + components/els_pkc/doc/mcxn/html/a00902.js | 9 + components/els_pkc/doc/mcxn/html/a00903.html | 285 + components/els_pkc/doc/mcxn/html/a00903.js | 8 + components/els_pkc/doc/mcxn/html/a00904.html | 255 + components/els_pkc/doc/mcxn/html/a00904.js | 7 + components/els_pkc/doc/mcxn/html/a00905.html | 187 + components/els_pkc/doc/mcxn/html/a00905.js | 5 + components/els_pkc/doc/mcxn/html/a00906.html | 303 + components/els_pkc/doc/mcxn/html/a00906.js | 12 + components/els_pkc/doc/mcxn/html/a00907.html | 143 + components/els_pkc/doc/mcxn/html/a00907.js | 7 + components/els_pkc/doc/mcxn/html/a00908.html | 308 + components/els_pkc/doc/mcxn/html/a00908.js | 11 + components/els_pkc/doc/mcxn/html/a00909.html | 261 + components/els_pkc/doc/mcxn/html/a00909.js | 8 + components/els_pkc/doc/mcxn/html/a00910.html | 231 + components/els_pkc/doc/mcxn/html/a00910.js | 7 + components/els_pkc/doc/mcxn/html/a00911.html | 187 + components/els_pkc/doc/mcxn/html/a00911.js | 5 + components/els_pkc/doc/mcxn/html/a00912.html | 143 + components/els_pkc/doc/mcxn/html/a00912.js | 7 + components/els_pkc/doc/mcxn/html/a00913.html | 327 + components/els_pkc/doc/mcxn/html/a00913.js | 12 + components/els_pkc/doc/mcxn/html/a00914.html | 261 + components/els_pkc/doc/mcxn/html/a00914.js | 8 + components/els_pkc/doc/mcxn/html/a00915.html | 231 + components/els_pkc/doc/mcxn/html/a00915.js | 7 + components/els_pkc/doc/mcxn/html/a00916.html | 187 + components/els_pkc/doc/mcxn/html/a00916.js | 5 + components/els_pkc/doc/mcxn/html/a00917.html | 134 + components/els_pkc/doc/mcxn/html/a00917.js | 4 + components/els_pkc/doc/mcxn/html/a00918.html | 238 + components/els_pkc/doc/mcxn/html/a00918.js | 8 + components/els_pkc/doc/mcxn/html/a00919.html | 208 + components/els_pkc/doc/mcxn/html/a00919.js | 7 + components/els_pkc/doc/mcxn/html/a00920.html | 246 + components/els_pkc/doc/mcxn/html/a00920.js | 9 + components/els_pkc/doc/mcxn/html/a00921.html | 387 + components/els_pkc/doc/mcxn/html/a00921.js | 11 + components/els_pkc/doc/mcxn/html/a00922.html | 208 + components/els_pkc/doc/mcxn/html/a00922.js | 7 + components/els_pkc/doc/mcxn/html/a00923.html | 249 + components/els_pkc/doc/mcxn/html/a00923.js | 9 + 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components/els_pkc/doc/mcxn/html/a00941.html | 149 + components/els_pkc/doc/mcxn/html/a00942.html | 149 + components/els_pkc/doc/mcxn/html/a00943.html | 149 + components/els_pkc/doc/mcxn/html/a00944.html | 149 + components/els_pkc/doc/mcxn/html/a00945.html | 149 + components/els_pkc/doc/mcxn/html/a00946.html | 149 + components/els_pkc/doc/mcxn/html/a00947.html | 149 + components/els_pkc/doc/mcxn/html/a00948.html | 149 + components/els_pkc/doc/mcxn/html/a00949.html | 149 + components/els_pkc/doc/mcxn/html/a00950.html | 149 + components/els_pkc/doc/mcxn/html/a00951.html | 149 + components/els_pkc/doc/mcxn/html/a00952.html | 149 + components/els_pkc/doc/mcxn/html/a00953.html | 149 + components/els_pkc/doc/mcxn/html/a00954.html | 149 + components/els_pkc/doc/mcxn/html/a00955.html | 149 + components/els_pkc/doc/mcxn/html/a00956.html | 149 + components/els_pkc/doc/mcxn/html/a00957.html | 302 + components/els_pkc/doc/mcxn/html/a00957.js | 11 + components/els_pkc/doc/mcxn/html/a00958.html | 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components/els_pkc/doc/mcxn/html/a01009.js | 14 + components/els_pkc/doc/mcxn/html/a01021.html | 327 + components/els_pkc/doc/mcxn/html/a01021.js | 13 + components/els_pkc/doc/mcxn/html/a01033.html | 302 + components/els_pkc/doc/mcxn/html/a01033.js | 11 + components/els_pkc/doc/mcxn/html/a01045.html | 429 + components/els_pkc/doc/mcxn/html/a01045.js | 18 + components/els_pkc/doc/mcxn/html/a01057.html | 252 + components/els_pkc/doc/mcxn/html/a01057.js | 9 + components/els_pkc/doc/mcxn/html/a01069.html | 251 + components/els_pkc/doc/mcxn/html/a01069.js | 9 + components/els_pkc/doc/mcxn/html/a01081.html | 251 + components/els_pkc/doc/mcxn/html/a01081.js | 9 + components/els_pkc/doc/mcxn/html/a01093.html | 668 + components/els_pkc/doc/mcxn/html/a01093.js | 29 + components/els_pkc/doc/mcxn/html/a01105.html | 235 + components/els_pkc/doc/mcxn/html/a01105.js | 9 + components/els_pkc/doc/mcxn/html/a01117.html | 296 + components/els_pkc/doc/mcxn/html/a01117.js | 11 + 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components/els_pkc/doc/mcxn/html/a01237.js | 33 + components/els_pkc/doc/mcxn/html/a01249.html | 143 + components/els_pkc/doc/mcxn/html/a01249.js | 6 + components/els_pkc/doc/mcxn/html/a01253.html | 173 + components/els_pkc/doc/mcxn/html/a01253.js | 5 + components/els_pkc/doc/mcxn/html/a01257.html | 140 + components/els_pkc/doc/mcxn/html/a01257.js | 5 + components/els_pkc/doc/mcxn/html/a01261.html | 173 + components/els_pkc/doc/mcxn/html/a01261.js | 5 + components/els_pkc/doc/mcxn/html/a01265.html | 174 + components/els_pkc/doc/mcxn/html/a01265.js | 5 + components/els_pkc/doc/mcxn/html/a01269.html | 177 + components/els_pkc/doc/mcxn/html/a01269.js | 5 + components/els_pkc/doc/mcxn/html/a01273.html | 279 + components/els_pkc/doc/mcxn/html/a01273.js | 10 + components/els_pkc/doc/mcxn/html/a01277.html | 211 + components/els_pkc/doc/mcxn/html/a01277.js | 7 + components/els_pkc/doc/mcxn/html/a01281.html | 154 + components/els_pkc/doc/mcxn/html/a01281.js | 4 + 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+ components/els_pkc/doc/mcxn/html/a01303.html | 121 + components/els_pkc/doc/mcxn/html/a01304.html | 121 + components/els_pkc/doc/mcxn/html/a01305.html | 121 + components/els_pkc/doc/mcxn/html/a01307.html | 121 + components/els_pkc/doc/mcxn/html/a01308.html | 121 + components/els_pkc/doc/mcxn/html/a01309.html | 121 + components/els_pkc/doc/mcxn/html/a01310.html | 121 + components/els_pkc/doc/mcxn/html/a01311.html | 121 + components/els_pkc/doc/mcxn/html/a01312.html | 121 + components/els_pkc/doc/mcxn/html/a01313.html | 121 + components/els_pkc/doc/mcxn/html/a01314.html | 121 + components/els_pkc/doc/mcxn/html/a01315.html | 121 + components/els_pkc/doc/mcxn/html/a01316.html | 121 + components/els_pkc/doc/mcxn/html/a01317.html | 121 + components/els_pkc/doc/mcxn/html/a01318.html | 121 + components/els_pkc/doc/mcxn/html/a01319.html | 121 + components/els_pkc/doc/mcxn/html/a01320.html | 175 + components/els_pkc/doc/mcxn/html/a01321.html | 140 + .../els_pkc/doc/mcxn/html/annotated.html | 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.../dir_6bb1d262d2f1e2da7d1b3eb7f0841c25.html | 121 + .../dir_789b10fbea7cebd033e3b0362b1fecef.html | 125 + .../dir_789b10fbea7cebd033e3b0362b1fecef.js | 12 + .../dir_8794789cb36db87bacac0d738226e3a5.html | 134 + .../dir_8794789cb36db87bacac0d738226e3a5.js | 6 + .../dir_8a434646fc8236fed8545f11b359bd33.html | 158 + .../dir_8a434646fc8236fed8545f11b359bd33.js | 14 + .../dir_8cc4b1983882a70286ae35228f42fe3d.html | 137 + .../dir_8cc4b1983882a70286ae35228f42fe3d.js | 7 + .../dir_9213b388d9e49777ed89916a660dacc5.html | 149 + .../dir_9213b388d9e49777ed89916a660dacc5.js | 11 + .../dir_9f351d46ce3cc29445a41dc3a31e6919.html | 121 + .../dir_b19d4aa211bb6dbce6ab36de7af852a2.html | 128 + .../dir_b19d4aa211bb6dbce6ab36de7af852a2.js | 4 + .../dir_fd86ae10c2a65c079928a83f489ab440.html | 149 + .../dir_fd86ae10c2a65c079928a83f489ab440.js | 11 + components/els_pkc/doc/mcxn/html/doc.png | Bin 0 -> 746 bytes components/els_pkc/doc/mcxn/html/doxygen.css | 1764 + components/els_pkc/doc/mcxn/html/doxygen.png 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+ .../examples/mcuxClKey/mcuxClKey_example.c | 109 + ...s_cbc_mac_multipart_zero_padding_example.c | 204 + .../mcuxClMacModes_cbc_mac_oneshot_example.c | 167 + .../mcuxClMacModes_cmac_oneshot_example.c | 191 + .../mcuxClRandomModes_ELS_example.c | 169 + .../mcuxClRsa_sign_NoEncode_example.c | 233 + .../mcuxClRsa_sign_pss_sha2_256_example.c | 218 + .../mcuxClRsa_verify_NoVerify_example.c | 221 + ...xClRsa_verify_pssverify_sha2_256_example.c | 194 + .../inc/mcuxCsslExamples.h | 41 + .../mcuxCsslFlowProtection_example.c | 473 + .../data_invariant_memory_compare.c | 98 + .../data_invariant_memory_copy.c | 93 + .../inc/mcuxCsslMemory_Examples.h | 31 + .../mcuxCsslMemory_Clear_example.c | 50 + .../mcuxCsslMemory_Set_example.c | 80 + .../els_pkc/set_component_els_pkc.cmake | 1286 + .../els_pkc/softwareContentRegister.txt | 14 + .../els_pkc/src/compiler/mcuxClToolchain.h | 132 + .../inc/mcuxClOscca_FunctionIdentifiers.h | 324 + .../src/comps/common/inc/mcuxClOscca_Memory.h | 65 + .../common/inc/mcuxClOscca_PlatformTypes.h | 51 + .../src/comps/common/inc/mcuxClOscca_Types.h | 53 + .../common/src/mcuxClOscca_CommonOperations.c | 180 + .../inc/internal/mcuxClAead_Internal_Ctx.h | 31 + .../internal/mcuxClAead_Internal_Descriptor.h | 152 + .../src/comps/mcuxClAead/inc/mcuxClAead.h | 56 + .../mcuxClAead/inc/mcuxClAead_Constants.h | 47 + .../mcuxClAead/inc/mcuxClAead_Functions.h | 264 + .../comps/mcuxClAead/inc/mcuxClAead_Types.h | 118 + .../src/comps/mcuxClAead/src/mcuxClAead.c | 233 + .../mcuxClAeadModes_Common_Functions.h | 98 + .../internal/mcuxClAeadModes_Els_Algorithms.h | 33 + .../internal/mcuxClAeadModes_Els_Functions.h | 86 + .../inc/internal/mcuxClAeadModes_Els_Types.h | 140 + .../inc/internal/mcuxClAeadModes_Internal.h | 38 + .../mcuxClAeadModes_Internal_Constants.h | 37 + .../mcuxClAeadModes/inc/mcuxClAeadModes.h | 22 + .../inc/mcuxClAeadModes_MemoryConsumption.h | 65 + .../inc/mcuxClAeadModes_Modes.h | 93 + .../src/mcuxClAeadModes_Els_AesCcm.c | 677 + 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+ .../inc/mcuxCsslMemory_Compare.h | 80 + .../mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h | 77 + .../mcuxCsslMemory/inc/mcuxCsslMemory_Set.h | 82 + .../mcuxCsslMemory/inc/mcuxCsslMemory_Types.h | 74 + .../mcuxCsslMemory/src/mcuxCsslMemory_Clear.c | 54 + .../src/mcuxCsslMemory_Compare.c | 72 + .../mcuxCsslMemory/src/mcuxCsslMemory_Copy.c | 76 + ...uxCsslMemory_Internal_SecureCompare_Stub.c | 66 + .../mcuxCsslMemory/src/mcuxCsslMemory_Set.c | 135 + .../inc/mcuxCsslParamIntegrity.h | 116 + .../src/mcuxCsslParamIntegrity.c | 99 + .../inc/mcuxCsslSecureCounter.h | 304 + .../inc/mcuxCsslSecureCounter_Cfg.h | 103 + .../inc/mcuxCsslSecureCounter_Impl.h | 48 + .../inc/mcuxCsslSecureCounter_None.h | 274 + .../inc/mcuxCsslSecureCounter_SW_Local.h | 293 + .../els_pkc/src/inc/impl/mcuxCl_clns_impl.h | 31 + components/els_pkc/src/inc/mcuxCl_clns.h | 47 + .../src/platforms/mcxn/inc/ip_css_constants.h | 52 + .../mcxn/inc/ip_css_design_configuration.h | 402 + .../src/platforms/mcxn/inc/ip_platform.h | 89 + .../els_pkc/src/platforms/mcxn/mcuxClConfig.h | 778 + .../els_pkc/src/platforms/mcxn/mcux_els.c | 134 + .../els_pkc/src/platforms/mcxn/mcux_els.h | 61 + .../els_pkc/src/platforms/mcxn/mcux_pkc.c | 68 + .../els_pkc/src/platforms/mcxn/mcux_pkc.h | 64 + .../mcxn/platform_specific_headers.h | 27 + .../els_pkc/static_library/mcxn/libclns.a | Bin 0 -> 1856008 bytes .../static_library/mcxn/libclns.a.libsize | 3 + .../static_library/mcxn/libclns.a.objsize | 196 + .../static_library/mcxn/libclns.stripped.a | Bin 0 -> 628136 bytes components/flash/mflash/mcxnx4x/mflash_drv.c | 84 + components/flash/mflash/mcxnx4x/mflash_drv.h | 32 + .../flash/nor/lpspi/fsl_lpspi_nor_flash.c | 49 + .../flash/nor/lpspi/fsl_lpspi_nor_flash.h | 16 + components/ft5406_rt/fsl_ft5406_rt.c | 60 +- components/gpio/fsl_adapter_gpio.c | 54 +- components/i2c/fsl_adapter_i2c.h | 4 +- components/i2c/fsl_adapter_lpi2c.c | 31 +- components/i3c_bus/fsl_component_i3c.h | 12 +- .../i3c_bus/fsl_component_i3c_adapter.c | 88 +- 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.../wlan_txpwrlimit_cfg_murata_2DS_EU.h | 2 + .../wlan_txpwrlimit_cfg_murata_2DS_JP.h | 2 + .../wlan_txpwrlimit_cfg_murata_2DS_US.h | 2 + .../wlan_txpwrlimit_cfg_murata_2DS_WW.h | 11 +- ...txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h | 3136 + ...txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h | 3100 + ...txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h | 3118 + ...txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h | 3136 + .../wlan_txpwrlimit_cfg_murata_2EL_WW.h | 2993 + .../incl/wifi_bt_module_config.h | 352 + .../wlan_txpwrlimit_cfg_jody_w5_WW.h | 2993 + devices/MCXN235/MCXN235.h | 70325 +++++++++++++++ devices/MCXN235/MCXN235_features.h | 900 + devices/MCXN235/drivers/fsl_clock.c | 2695 + devices/MCXN235/drivers/fsl_clock.h | 1726 + devices/MCXN235/drivers/fsl_edma_soc.c | 289 + devices/MCXN235/drivers/fsl_edma_soc.h | 68 + .../drivers/fsl_inputmux_connections.h | 3664 + devices/MCXN235/drivers/fsl_reset.c | 102 + devices/MCXN235/drivers/fsl_reset.h | 224 + devices/MCXN235/fsl_device_registers.h | 33 + devices/MCXN235/gcc/MCXN235_flash.ld | 205 + devices/MCXN235/gcc/MCXN235_ram.ld | 205 + devices/MCXN235/gcc/startup_MCXN235.S | 1948 + devices/MCXN235/mcuxpresso/startup_mcxn235.c | 1409 + .../MCXN235/mcuxpresso/startup_mcxn235.cpp | 1409 + devices/MCXN235/project_template/board.c | 24 + devices/MCXN235/project_template/board.h | 36 + .../MCXN235/project_template/clock_config.c | 32 + .../MCXN235/project_template/clock_config.h | 31 + .../MCXN235/project_template/peripherals.c | 28 + .../MCXN235/project_template/peripherals.h | 31 + devices/MCXN235/project_template/pin_mux.c | 27 + devices/MCXN235/project_template/pin_mux.h | 33 + devices/MCXN235/set_device_MCXN235.cmake | 2 + devices/MCXN235/system_MCXN235.c | 128 + devices/MCXN235/system_MCXN235.h | 106 + devices/MCXN235/template/RTE_Device.h | 230 + devices/MCXN236/MCXN236.h | 70367 ++++++++++++++++ devices/MCXN236/MCXN236_features.h | 900 + devices/MCXN236/all_lib_device.cmake | 1104 + devices/MCXN236/drivers/fsl_clock.c | 2695 + devices/MCXN236/drivers/fsl_clock.h | 1726 + devices/MCXN236/drivers/fsl_edma_soc.c | 289 + devices/MCXN236/drivers/fsl_edma_soc.h | 68 + .../drivers/fsl_inputmux_connections.h | 3664 + devices/MCXN236/drivers/fsl_reset.c | 102 + devices/MCXN236/drivers/fsl_reset.h | 224 + devices/MCXN236/fsl_device_registers.h | 33 + devices/MCXN236/gcc/MCXN236_flash.ld | 205 + devices/MCXN236/gcc/MCXN236_ram.ld | 205 + devices/MCXN236/gcc/startup_MCXN236.S | 1948 + devices/MCXN236/mcuxpresso/startup_mcxn236.c | 1409 + .../MCXN236/mcuxpresso/startup_mcxn236.cpp | 1409 + devices/MCXN236/project_template/board.c | 59 + devices/MCXN236/project_template/board.h | 148 + .../MCXN236/project_template/clock_config.c | 447 + .../MCXN236/project_template/clock_config.h | 177 + .../MCXN236/project_template/peripherals.c | 99 + .../MCXN236/project_template/peripherals.h | 39 + devices/MCXN236/project_template/pin_mux.c | 61 + devices/MCXN236/project_template/pin_mux.h | 52 + devices/MCXN236/set_device_MCXN236.cmake | 4239 + devices/MCXN236/system_MCXN236.c | 128 + devices/MCXN236/system_MCXN236.h | 106 + devices/MCXN236/template/RTE_Device.h | 230 + .../cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c | 20 + .../cache/lpcac_n4a_mcxn/fsl_cache_lpcac.h | 184 + drivers/cdog/fsl_cdog.c | 19 + drivers/cdog/fsl_cdog.h | 6 +- drivers/common/fsl_common.h | 9 +- drivers/common/fsl_common_arm.c | 4 +- drivers/common/fsl_common_arm.h | 18 +- drivers/crc/fsl_crc.c | 49 + drivers/crc/fsl_crc.h | 15 +- drivers/ctimer/fsl_ctimer.h | 6 +- drivers/edma4/fsl_edma.c | 2224 + drivers/edma4/fsl_edma.h | 1593 + drivers/edma4/fsl_edma_core.h | 299 + drivers/eim/fsl_eim.c | 312 + drivers/eim/fsl_eim.h | 144 + drivers/erm/fsl_erm.c | 317 + drivers/erm/fsl_erm.h | 235 + drivers/evtg/fsl_evtg.c | 418 + drivers/evtg/fsl_evtg.h | 355 + drivers/ewm/fsl_ewm.h | 6 +- drivers/flexcan/fsl_flexcan.c | 37 +- drivers/flexcan/fsl_flexcan.h | 10 +- drivers/flexcan/fsl_flexcan_edma.c | 18 +- drivers/flexcan/fsl_flexcan_edma.h | 8 +- drivers/flexio/fsl_flexio.c | 15 + drivers/flexio/fsl_flexio.h | 9 +- drivers/flexio/i2c/fsl_flexio_i2c_master.h | 6 +- drivers/flexio/mculcd/fsl_flexio_mculcd.c | 12 +- drivers/flexio/mculcd/fsl_flexio_mculcd.h | 11 +- .../flexio/mculcd/fsl_flexio_mculcd_edma.c | 10 +- .../flexio/mculcd/fsl_flexio_mculcd_edma.h | 10 +- .../mculcd/fsl_flexio_mculcd_smartdma.c | 14 +- .../mculcd/fsl_flexio_mculcd_smartdma.h | 10 +- drivers/flexio/spi/fsl_flexio_spi.c | 8 +- drivers/flexio/spi/fsl_flexio_spi.h | 8 +- drivers/flexio/spi/fsl_flexio_spi_edma.h | 4 +- drivers/flexio/uart/fsl_flexio_uart.c | 14 + drivers/flexio/uart/fsl_flexio_uart.h | 15 +- drivers/flexio/uart/fsl_flexio_uart_edma.h | 6 +- drivers/gpio/fsl_gpio.c | 18 +- drivers/gpio/fsl_gpio.h | 8 +- drivers/i3c/fsl_i3c.c | 145 +- drivers/i3c/fsl_i3c.h | 25 +- drivers/i3c/fsl_i3c_edma.c | 1055 + drivers/i3c/fsl_i3c_edma.h | 279 + drivers/inputmux/fsl_inputmux.c | 63 +- drivers/inputmux/fsl_inputmux.h | 22 +- drivers/intm/fsl_intm.c | 86 + drivers/intm/fsl_intm.h | 207 + drivers/irtc/fsl_irtc.h | 22 +- drivers/itrc/fsl_itrc.c | 171 +- drivers/itrc/fsl_itrc.h | 168 +- drivers/lpadc/fsl_lpadc.c | 1822 +- drivers/lpadc/fsl_lpadc.h | 683 +- drivers/lpc_freqme/fsl_freqme.c | 38 +- drivers/lpc_freqme/fsl_freqme.h | 113 +- drivers/lpcmp/fsl_lpcmp.c | 130 +- drivers/lpcmp/fsl_lpcmp.h | 367 +- drivers/lpflexcomm/fsl_lpflexcomm.c | 380 + drivers/lpflexcomm/fsl_lpflexcomm.h | 88 + drivers/lpflexcomm/fsl_lpi2c_freertos.c | 122 + drivers/lpflexcomm/fsl_lpi2c_freertos.h | 107 + drivers/lpflexcomm/fsl_lpspi_freertos.c | 135 + drivers/lpflexcomm/fsl_lpspi_freertos.h | 103 + drivers/lpflexcomm/fsl_lpuart_freertos.c | 489 + drivers/lpflexcomm/fsl_lpuart_freertos.h | 192 + drivers/lpflexcomm/lpi2c/fsl_lpi2c.c | 2423 + drivers/lpflexcomm/lpi2c/fsl_lpi2c.h | 1342 + drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c | 636 + drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.h | 158 + drivers/lpflexcomm/lpspi/fsl_lpspi.c | 2297 + drivers/lpflexcomm/lpspi/fsl_lpspi.h | 1175 + drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c | 1118 + drivers/lpflexcomm/lpspi/fsl_lpspi_edma.h | 339 + drivers/lpflexcomm/lpuart/fsl_lpuart.c | 2129 + drivers/lpflexcomm/lpuart/fsl_lpuart.h | 1175 + drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c | 510 + drivers/lpflexcomm/lpuart/fsl_lpuart_edma.h | 189 + drivers/lptmr/fsl_lptmr.h | 6 +- drivers/mcx_cmc/fsl_cmc.c | 315 + drivers/mcx_cmc/fsl_cmc.h | 911 + drivers/mcx_romapi/flash/fsl_efuse.h | 112 + drivers/mcx_romapi/flash/fsl_flash.h | 591 + drivers/mcx_romapi/flash/fsl_flash_ffr.h | 591 + .../mcx_romapi/flash/fsl_flexspi_nor_flash.h | 721 + drivers/mcx_romapi/flash/src/fsl_flash.c | 567 + .../mem_interface/fsl_mem_interface.h | 379 + .../mcx_romapi/mem_interface/fsl_sbloader.h | 373 + .../mem_interface/fsl_sbloader_v3.h | 271 + .../mem_interface/src/fsl_mem_interface.c | 154 + drivers/mcx_romapi/nboot/fsl_nboot.h | 346 + drivers/mcx_romapi/nboot/fsl_nboot_hal.h | 231 + drivers/mcx_romapi/nboot/src/fsl_nboot.c | 212 + .../runbootloader/fsl_runbootloader.h | 72 + .../runbootloader/src/fsl_runbootloader.c | 52 + drivers/mcx_spc/fsl_spc.c | 1753 + drivers/mcx_spc/fsl_spc.h | 2223 + drivers/mcx_vbat/fsl_vbat.c | 498 + drivers/mcx_vbat/fsl_vbat.h | 1386 + drivers/mrt/fsl_mrt.h | 6 +- drivers/ostimer/fsl_ostimer.c | 13 + drivers/ostimer/fsl_ostimer.h | 8 +- drivers/pdm/fsl_pdm.c | 14 +- drivers/pdm/fsl_pdm.h | 86 +- drivers/pdm/fsl_pdm_edma.h | 4 +- drivers/pint/fsl_pint.c | 11 +- drivers/pint/fsl_pint.h | 11 +- drivers/port/fsl_port.h | 6 +- drivers/puf_v3/fsl_puf_v3.c | 137 +- drivers/puf_v3/fsl_puf_v3.h | 59 +- drivers/pwm/fsl_pwm.c | 441 +- drivers/pwm/fsl_pwm.h | 74 +- drivers/qdc/fsl_qdc.c | 645 + drivers/qdc/fsl_qdc.h | 585 + drivers/sai/fsl_sai.c | 719 +- drivers/sai/fsl_sai.h | 157 +- drivers/sai/fsl_sai_edma.c | 206 +- drivers/sai/fsl_sai_edma.h | 70 +- drivers/smartdma/fsl_smartdma.c | 833 +- drivers/smartdma/fsl_smartdma.h | 218 +- drivers/smartdma/fsl_smartdma_mcxn.c | 445 + drivers/smartdma/fsl_smartdma_mcxn.h | 136 + drivers/smartdma/fsl_smartdma_prv.h | 4 +- drivers/smartdma/fsl_smartdma_rt500.c | 2518 + drivers/smartdma/fsl_smartdma_rt500.h | 321 + drivers/syspm/fsl_syspm.c | 215 + drivers/syspm/fsl_syspm.h | 165 + drivers/tdet/fsl_tdet.c | 656 + drivers/tdet/fsl_tdet.h | 601 + drivers/utick/fsl_utick.h | 6 +- drivers/vref_1/fsl_vref.c | 118 +- drivers/vref_1/fsl_vref.h | 65 +- drivers/wuu/fsl_wuu.c | 292 + drivers/wuu/fsl_wuu.h | 286 + drivers/wwdt/fsl_wwdt.h | 6 +- manifests/FRDM-MCXN236_manifest_v3_13.xml | 9307 ++ tools/cmake_toolchain_files/mcux_config.cmake | 5 +- utilities/debug_console/fsl_debug_console.c | 4 +- .../debug_console_lite/fsl_debug_console.c | 12 +- utilities/str/fsl_str.c | 131 +- utilities/unity/gcov_support.c | 2 +- utilities/unity/linkscripts/main_text.ldt | 26 +- utilities/unity/unity.c | 138 + utilities/unity/unity.h | 15 +- west.yml | 20 +- 2407 files changed, 586411 insertions(+), 10606 deletions(-) create mode 100644 boards/frdmmcxn236/board.c create mode 100644 boards/frdmmcxn236/board.h create mode 100644 boards/frdmmcxn236/clock_config.c create mode 100644 boards/frdmmcxn236/clock_config.h create mode 100644 boards/frdmmcxn236/frdmmcxn236.png create mode 100644 boards/frdmmcxn236/freemaster_examples/set_board_frdmmcxn236_fmstr.cmake create mode 100644 boards/frdmmcxn236/project_template/board.c create mode 100644 boards/frdmmcxn236/project_template/board.h create mode 100644 boards/frdmmcxn236/project_template/clock_config.c create mode 100644 boards/frdmmcxn236/project_template/clock_config.h create mode 100644 boards/frdmmcxn236/project_template/peripherals.c create mode 100644 boards/frdmmcxn236/project_template/peripherals.h create mode 100644 boards/frdmmcxn236/project_template/pin_mux.c create mode 100644 boards/frdmmcxn236/project_template/pin_mux.h create mode 100644 boards/frdmmcxn236/set_board_frdmmcxn236.cmake create mode 100644 components/els_pkc/LICENSE.htm create mode 100644 components/els_pkc/ReleaseNotes.txt create mode 100644 components/els_pkc/doc/mcxn/html/a00002.html create mode 100644 components/els_pkc/doc/mcxn/html/a00002.js create mode 100644 components/els_pkc/doc/mcxn/html/a00005.html create mode 100644 components/els_pkc/doc/mcxn/html/a00005.js create mode 100644 components/els_pkc/doc/mcxn/html/a00008.html create mode 100644 components/els_pkc/doc/mcxn/html/a00008.js create mode 100644 components/els_pkc/doc/mcxn/html/a00011.html create mode 100644 components/els_pkc/doc/mcxn/html/a00011.js create mode 100644 components/els_pkc/doc/mcxn/html/a00014.html create mode 100644 components/els_pkc/doc/mcxn/html/a00014.js create mode 100644 components/els_pkc/doc/mcxn/html/a00017.html create mode 100644 components/els_pkc/doc/mcxn/html/a00017.js create mode 100644 components/els_pkc/doc/mcxn/html/a00020.html create mode 100644 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create mode 100644 components/els_pkc/doc/mcxn/html/a00278.html create mode 100644 components/els_pkc/doc/mcxn/html/a00278.js create mode 100644 components/els_pkc/doc/mcxn/html/a00278_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00281.html create mode 100644 components/els_pkc/doc/mcxn/html/a00281.js create mode 100644 components/els_pkc/doc/mcxn/html/a00281_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00284.html create mode 100644 components/els_pkc/doc/mcxn/html/a00284.js create mode 100644 components/els_pkc/doc/mcxn/html/a00284_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00287.html create mode 100644 components/els_pkc/doc/mcxn/html/a00287.js create mode 100644 components/els_pkc/doc/mcxn/html/a00287_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00290.html create mode 100644 components/els_pkc/doc/mcxn/html/a00290.js create mode 100644 components/els_pkc/doc/mcxn/html/a00290_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00293.html create mode 100644 components/els_pkc/doc/mcxn/html/a00293_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00296.html create mode 100644 components/els_pkc/doc/mcxn/html/a00296.js create mode 100644 components/els_pkc/doc/mcxn/html/a00296_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00299.html create mode 100644 components/els_pkc/doc/mcxn/html/a00299.js create mode 100644 components/els_pkc/doc/mcxn/html/a00299_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00302.html create mode 100644 components/els_pkc/doc/mcxn/html/a00302.js create mode 100644 components/els_pkc/doc/mcxn/html/a00302_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00305.html create mode 100644 components/els_pkc/doc/mcxn/html/a00305.js create mode 100644 components/els_pkc/doc/mcxn/html/a00305_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00308.html create mode 100644 components/els_pkc/doc/mcxn/html/a00308.js create mode 100644 components/els_pkc/doc/mcxn/html/a00308_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00311.html create mode 100644 components/els_pkc/doc/mcxn/html/a00311.js create mode 100644 components/els_pkc/doc/mcxn/html/a00311_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00314.html create mode 100644 components/els_pkc/doc/mcxn/html/a00314.js create mode 100644 components/els_pkc/doc/mcxn/html/a00314_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00317.html create mode 100644 components/els_pkc/doc/mcxn/html/a00317.js create mode 100644 components/els_pkc/doc/mcxn/html/a00317_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00320.html create mode 100644 components/els_pkc/doc/mcxn/html/a00320.js create mode 100644 components/els_pkc/doc/mcxn/html/a00320_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00323.html create mode 100644 components/els_pkc/doc/mcxn/html/a00323.js create mode 100644 components/els_pkc/doc/mcxn/html/a00323_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00326.html create mode 100644 components/els_pkc/doc/mcxn/html/a00326.js create mode 100644 components/els_pkc/doc/mcxn/html/a00326_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00329.html create mode 100644 components/els_pkc/doc/mcxn/html/a00329.js create mode 100644 components/els_pkc/doc/mcxn/html/a00329_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00332.html create mode 100644 components/els_pkc/doc/mcxn/html/a00332.js create mode 100644 components/els_pkc/doc/mcxn/html/a00332_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00335_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00338_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00341_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00344_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00347_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00350_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00353.html create mode 100644 components/els_pkc/doc/mcxn/html/a00353_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00356.html create mode 100644 components/els_pkc/doc/mcxn/html/a00356.js create mode 100644 components/els_pkc/doc/mcxn/html/a00356_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00359.html create mode 100644 components/els_pkc/doc/mcxn/html/a00359.js create mode 100644 components/els_pkc/doc/mcxn/html/a00359_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00362.html create mode 100644 components/els_pkc/doc/mcxn/html/a00362.js create mode 100644 components/els_pkc/doc/mcxn/html/a00362_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00365.html create mode 100644 components/els_pkc/doc/mcxn/html/a00365.js create mode 100644 components/els_pkc/doc/mcxn/html/a00365_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00368_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00371.html create mode 100644 components/els_pkc/doc/mcxn/html/a00371.js create mode 100644 components/els_pkc/doc/mcxn/html/a00371_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00374.html create mode 100644 components/els_pkc/doc/mcxn/html/a00374.js create mode 100644 components/els_pkc/doc/mcxn/html/a00374_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00377_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00380.html create mode 100644 components/els_pkc/doc/mcxn/html/a00380.js create mode 100644 components/els_pkc/doc/mcxn/html/a00380_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00383_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00386.html create mode 100644 components/els_pkc/doc/mcxn/html/a00386.js create mode 100644 components/els_pkc/doc/mcxn/html/a00386_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00389.html create mode 100644 components/els_pkc/doc/mcxn/html/a00389.js create mode 100644 components/els_pkc/doc/mcxn/html/a00389_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00392.html create mode 100644 components/els_pkc/doc/mcxn/html/a00392.js create mode 100644 components/els_pkc/doc/mcxn/html/a00392_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00395.html create mode 100644 components/els_pkc/doc/mcxn/html/a00395.js create mode 100644 components/els_pkc/doc/mcxn/html/a00395_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00398.html create mode 100644 components/els_pkc/doc/mcxn/html/a00398.js create mode 100644 components/els_pkc/doc/mcxn/html/a00398_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00401.html create mode 100644 components/els_pkc/doc/mcxn/html/a00401_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00404.html create mode 100644 components/els_pkc/doc/mcxn/html/a00404.js create mode 100644 components/els_pkc/doc/mcxn/html/a00404_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00407.html create mode 100644 components/els_pkc/doc/mcxn/html/a00407.js create mode 100644 components/els_pkc/doc/mcxn/html/a00407_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00410.html create mode 100644 components/els_pkc/doc/mcxn/html/a00410.js create mode 100644 components/els_pkc/doc/mcxn/html/a00410_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00413_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00416.html create mode 100644 components/els_pkc/doc/mcxn/html/a00416.js create mode 100644 components/els_pkc/doc/mcxn/html/a00416_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00419.html create mode 100644 components/els_pkc/doc/mcxn/html/a00419_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00422.html create mode 100644 components/els_pkc/doc/mcxn/html/a00422.js create mode 100644 components/els_pkc/doc/mcxn/html/a00422_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00425.html create mode 100644 components/els_pkc/doc/mcxn/html/a00425.js create mode 100644 components/els_pkc/doc/mcxn/html/a00425_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00428.html create mode 100644 components/els_pkc/doc/mcxn/html/a00428.js create mode 100644 components/els_pkc/doc/mcxn/html/a00428_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00431_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00434.html create mode 100644 components/els_pkc/doc/mcxn/html/a00434.js create mode 100644 components/els_pkc/doc/mcxn/html/a00434_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00437.html create mode 100644 components/els_pkc/doc/mcxn/html/a00437_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00440.html create mode 100644 components/els_pkc/doc/mcxn/html/a00440.js create mode 100644 components/els_pkc/doc/mcxn/html/a00440_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00443_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00446.html create mode 100644 components/els_pkc/doc/mcxn/html/a00446_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00449.html create mode 100644 components/els_pkc/doc/mcxn/html/a00449.js create mode 100644 components/els_pkc/doc/mcxn/html/a00449_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00452_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00455.html create mode 100644 components/els_pkc/doc/mcxn/html/a00455_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00458.html create mode 100644 components/els_pkc/doc/mcxn/html/a00458.js create mode 100644 components/els_pkc/doc/mcxn/html/a00458_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00461.html create mode 100644 components/els_pkc/doc/mcxn/html/a00461.js create mode 100644 components/els_pkc/doc/mcxn/html/a00461_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00464.html create mode 100644 components/els_pkc/doc/mcxn/html/a00464.js create mode 100644 components/els_pkc/doc/mcxn/html/a00464_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00467.html create mode 100644 components/els_pkc/doc/mcxn/html/a00467.js create mode 100644 components/els_pkc/doc/mcxn/html/a00467_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00470.html create mode 100644 components/els_pkc/doc/mcxn/html/a00470.js create mode 100644 components/els_pkc/doc/mcxn/html/a00470_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00473.html create mode 100644 components/els_pkc/doc/mcxn/html/a00473.js create mode 100644 components/els_pkc/doc/mcxn/html/a00473_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00476.html create mode 100644 components/els_pkc/doc/mcxn/html/a00476.js create mode 100644 components/els_pkc/doc/mcxn/html/a00476_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00479.html create mode 100644 components/els_pkc/doc/mcxn/html/a00479.js create mode 100644 components/els_pkc/doc/mcxn/html/a00479_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00482.html create mode 100644 components/els_pkc/doc/mcxn/html/a00482.js create mode 100644 components/els_pkc/doc/mcxn/html/a00482_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00485.html create mode 100644 components/els_pkc/doc/mcxn/html/a00485.js create mode 100644 components/els_pkc/doc/mcxn/html/a00485_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00488.html create mode 100644 components/els_pkc/doc/mcxn/html/a00488_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00491.html create mode 100644 components/els_pkc/doc/mcxn/html/a00491.js create mode 100644 components/els_pkc/doc/mcxn/html/a00491_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00494.html create mode 100644 components/els_pkc/doc/mcxn/html/a00494.js create mode 100644 components/els_pkc/doc/mcxn/html/a00494_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00497.html create mode 100644 components/els_pkc/doc/mcxn/html/a00497_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00500.html create mode 100644 components/els_pkc/doc/mcxn/html/a00500_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00503.html create mode 100644 components/els_pkc/doc/mcxn/html/a00503.js create mode 100644 components/els_pkc/doc/mcxn/html/a00503_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00506.html create mode 100644 components/els_pkc/doc/mcxn/html/a00506.js create mode 100644 components/els_pkc/doc/mcxn/html/a00506_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00509.html create mode 100644 components/els_pkc/doc/mcxn/html/a00509_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00512.html create mode 100644 components/els_pkc/doc/mcxn/html/a00512.js create mode 100644 components/els_pkc/doc/mcxn/html/a00512_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00515.html create mode 100644 components/els_pkc/doc/mcxn/html/a00515.js create mode 100644 components/els_pkc/doc/mcxn/html/a00515_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00518.html create mode 100644 components/els_pkc/doc/mcxn/html/a00518_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00521.html create mode 100644 components/els_pkc/doc/mcxn/html/a00521.js create mode 100644 components/els_pkc/doc/mcxn/html/a00521_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00524.html create mode 100644 components/els_pkc/doc/mcxn/html/a00524.js create mode 100644 components/els_pkc/doc/mcxn/html/a00524_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00527.html create mode 100644 components/els_pkc/doc/mcxn/html/a00527_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00530.html create mode 100644 components/els_pkc/doc/mcxn/html/a00530.js create mode 100644 components/els_pkc/doc/mcxn/html/a00530_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00533.html create mode 100644 components/els_pkc/doc/mcxn/html/a00533.js create mode 100644 components/els_pkc/doc/mcxn/html/a00533_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00536.html create mode 100644 components/els_pkc/doc/mcxn/html/a00536.js create mode 100644 components/els_pkc/doc/mcxn/html/a00536_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00539.html create mode 100644 components/els_pkc/doc/mcxn/html/a00539_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00542.html create mode 100644 components/els_pkc/doc/mcxn/html/a00542.js create mode 100644 components/els_pkc/doc/mcxn/html/a00542_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00545_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00548_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00551.html create mode 100644 components/els_pkc/doc/mcxn/html/a00551.js create mode 100644 components/els_pkc/doc/mcxn/html/a00551_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00554.html create mode 100644 components/els_pkc/doc/mcxn/html/a00554_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00557.html create mode 100644 components/els_pkc/doc/mcxn/html/a00557.js create mode 100644 components/els_pkc/doc/mcxn/html/a00557_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00560.html create mode 100644 components/els_pkc/doc/mcxn/html/a00560.js create mode 100644 components/els_pkc/doc/mcxn/html/a00560_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00563.html create mode 100644 components/els_pkc/doc/mcxn/html/a00563.js create mode 100644 components/els_pkc/doc/mcxn/html/a00563_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00566.html create mode 100644 components/els_pkc/doc/mcxn/html/a00566.js create mode 100644 components/els_pkc/doc/mcxn/html/a00566_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00569.html create mode 100644 components/els_pkc/doc/mcxn/html/a00569_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00572.html create mode 100644 components/els_pkc/doc/mcxn/html/a00572.js create mode 100644 components/els_pkc/doc/mcxn/html/a00572_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00575.html create mode 100644 components/els_pkc/doc/mcxn/html/a00575_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00578.html create mode 100644 components/els_pkc/doc/mcxn/html/a00578.js create mode 100644 components/els_pkc/doc/mcxn/html/a00578_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00581_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00584.html create mode 100644 components/els_pkc/doc/mcxn/html/a00584.js create mode 100644 components/els_pkc/doc/mcxn/html/a00584_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00587.html create mode 100644 components/els_pkc/doc/mcxn/html/a00587.js create mode 100644 components/els_pkc/doc/mcxn/html/a00587_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00590.html create mode 100644 components/els_pkc/doc/mcxn/html/a00590.js create mode 100644 components/els_pkc/doc/mcxn/html/a00590_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00593.html create mode 100644 components/els_pkc/doc/mcxn/html/a00593_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00596.html create mode 100644 components/els_pkc/doc/mcxn/html/a00596.js create mode 100644 components/els_pkc/doc/mcxn/html/a00596_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00599.html create mode 100644 components/els_pkc/doc/mcxn/html/a00599.js create mode 100644 components/els_pkc/doc/mcxn/html/a00599_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00602.html create mode 100644 components/els_pkc/doc/mcxn/html/a00602.js create mode 100644 components/els_pkc/doc/mcxn/html/a00602_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00605.html create mode 100644 components/els_pkc/doc/mcxn/html/a00605.js create mode 100644 components/els_pkc/doc/mcxn/html/a00605_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00608.html create mode 100644 components/els_pkc/doc/mcxn/html/a00608_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00611.html create mode 100644 components/els_pkc/doc/mcxn/html/a00611.js create mode 100644 components/els_pkc/doc/mcxn/html/a00611_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00614.html create mode 100644 components/els_pkc/doc/mcxn/html/a00614.js create mode 100644 components/els_pkc/doc/mcxn/html/a00614_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00617.html create mode 100644 components/els_pkc/doc/mcxn/html/a00617_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00620.html create mode 100644 components/els_pkc/doc/mcxn/html/a00620.js create mode 100644 components/els_pkc/doc/mcxn/html/a00620_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00623.html create mode 100644 components/els_pkc/doc/mcxn/html/a00623.js create mode 100644 components/els_pkc/doc/mcxn/html/a00623_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00626.html create mode 100644 components/els_pkc/doc/mcxn/html/a00626.js create mode 100644 components/els_pkc/doc/mcxn/html/a00626_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00629.html create mode 100644 components/els_pkc/doc/mcxn/html/a00629.js create mode 100644 components/els_pkc/doc/mcxn/html/a00629_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00632.html create mode 100644 components/els_pkc/doc/mcxn/html/a00632.js create mode 100644 components/els_pkc/doc/mcxn/html/a00632_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00635.html create mode 100644 components/els_pkc/doc/mcxn/html/a00635.js create mode 100644 components/els_pkc/doc/mcxn/html/a00635_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00638.html create mode 100644 components/els_pkc/doc/mcxn/html/a00638.js create mode 100644 components/els_pkc/doc/mcxn/html/a00638_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00641.html create mode 100644 components/els_pkc/doc/mcxn/html/a00641.js create mode 100644 components/els_pkc/doc/mcxn/html/a00641_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00644.html create mode 100644 components/els_pkc/doc/mcxn/html/a00644_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00647.html create mode 100644 components/els_pkc/doc/mcxn/html/a00647.js create mode 100644 components/els_pkc/doc/mcxn/html/a00647_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00650.html create mode 100644 components/els_pkc/doc/mcxn/html/a00650.js create mode 100644 components/els_pkc/doc/mcxn/html/a00650_source.html create mode 100644 components/els_pkc/doc/mcxn/html/a00661.html create mode 100644 components/els_pkc/doc/mcxn/html/a00661.js create mode 100644 components/els_pkc/doc/mcxn/html/a00662.html create mode 100644 components/els_pkc/doc/mcxn/html/a00662.js create mode 100644 components/els_pkc/doc/mcxn/html/a00663.html create mode 100644 components/els_pkc/doc/mcxn/html/a00664.html create mode 100644 components/els_pkc/doc/mcxn/html/a00664.js create mode 100644 components/els_pkc/doc/mcxn/html/a00665.html create mode 100644 components/els_pkc/doc/mcxn/html/a00665.js create mode 100644 components/els_pkc/doc/mcxn/html/a00666.html create mode 100644 components/els_pkc/doc/mcxn/html/a00666.js create mode 100644 components/els_pkc/doc/mcxn/html/a00667.html create mode 100644 components/els_pkc/doc/mcxn/html/a00667.js create mode 100644 components/els_pkc/doc/mcxn/html/a00668.html create mode 100644 components/els_pkc/doc/mcxn/html/a00669.html create mode 100644 components/els_pkc/doc/mcxn/html/a00669.js create mode 100644 components/els_pkc/doc/mcxn/html/a00670.html create mode 100644 components/els_pkc/doc/mcxn/html/a00670.js create mode 100644 components/els_pkc/doc/mcxn/html/a00671.html create mode 100644 components/els_pkc/doc/mcxn/html/a00671.js create mode 100644 components/els_pkc/doc/mcxn/html/a00672.html create mode 100644 components/els_pkc/doc/mcxn/html/a00673.html create mode 100644 components/els_pkc/doc/mcxn/html/a00673.js create mode 100644 components/els_pkc/doc/mcxn/html/a00674.html create mode 100644 components/els_pkc/doc/mcxn/html/a00675.html create mode 100644 components/els_pkc/doc/mcxn/html/a00676.html create mode 100644 components/els_pkc/doc/mcxn/html/a00676.js create mode 100644 components/els_pkc/doc/mcxn/html/a00677.html create mode 100644 components/els_pkc/doc/mcxn/html/a00677.js create mode 100644 components/els_pkc/doc/mcxn/html/a00678.html create mode 100644 components/els_pkc/doc/mcxn/html/a00678.js create mode 100644 components/els_pkc/doc/mcxn/html/a00679.html create mode 100644 components/els_pkc/doc/mcxn/html/a00679.js create mode 100644 components/els_pkc/doc/mcxn/html/a00680.html create mode 100644 components/els_pkc/doc/mcxn/html/a00681.html create mode 100644 components/els_pkc/doc/mcxn/html/a00681.js create mode 100644 components/els_pkc/doc/mcxn/html/a00682.html create mode 100644 components/els_pkc/doc/mcxn/html/a00682.js create mode 100644 components/els_pkc/doc/mcxn/html/a00683.html create mode 100644 components/els_pkc/doc/mcxn/html/a00683.js create mode 100644 components/els_pkc/doc/mcxn/html/a00684.html create mode 100644 components/els_pkc/doc/mcxn/html/a00684.js create mode 100644 components/els_pkc/doc/mcxn/html/a00685.html create mode 100644 components/els_pkc/doc/mcxn/html/a00685.js create mode 100644 components/els_pkc/doc/mcxn/html/a00686.html create mode 100644 components/els_pkc/doc/mcxn/html/a00686.js create mode 100644 components/els_pkc/doc/mcxn/html/a00687.html create mode 100644 components/els_pkc/doc/mcxn/html/a00687.js create mode 100644 components/els_pkc/doc/mcxn/html/a00688.html create mode 100644 components/els_pkc/doc/mcxn/html/a00688.js create mode 100644 components/els_pkc/doc/mcxn/html/a00689.html create mode 100644 components/els_pkc/doc/mcxn/html/a00689.js create mode 100644 components/els_pkc/doc/mcxn/html/a00690.html create mode 100644 components/els_pkc/doc/mcxn/html/a00690.js create mode 100644 components/els_pkc/doc/mcxn/html/a00691.html create mode 100644 components/els_pkc/doc/mcxn/html/a00691.js create mode 100644 components/els_pkc/doc/mcxn/html/a00692.html create mode 100644 components/els_pkc/doc/mcxn/html/a00692.js create mode 100644 components/els_pkc/doc/mcxn/html/a00693.html create mode 100644 components/els_pkc/doc/mcxn/html/a00693.js create mode 100644 components/els_pkc/doc/mcxn/html/a00694.html create mode 100644 components/els_pkc/doc/mcxn/html/a00694.js create mode 100644 components/els_pkc/doc/mcxn/html/a00695.html create mode 100644 components/els_pkc/doc/mcxn/html/a00695.js create mode 100644 components/els_pkc/doc/mcxn/html/a00696.html create mode 100644 components/els_pkc/doc/mcxn/html/a00696.js create mode 100644 components/els_pkc/doc/mcxn/html/a00697.html create mode 100644 components/els_pkc/doc/mcxn/html/a00697.js create mode 100644 components/els_pkc/doc/mcxn/html/a00698.html create mode 100644 components/els_pkc/doc/mcxn/html/a00698.js create mode 100644 components/els_pkc/doc/mcxn/html/a00699.html create mode 100644 components/els_pkc/doc/mcxn/html/a00699.js create mode 100644 components/els_pkc/doc/mcxn/html/a00700.html create mode 100644 components/els_pkc/doc/mcxn/html/a00700.js create mode 100644 components/els_pkc/doc/mcxn/html/a00701.html create mode 100644 components/els_pkc/doc/mcxn/html/a00701.js create mode 100644 components/els_pkc/doc/mcxn/html/a00702.html create mode 100644 components/els_pkc/doc/mcxn/html/a00702.js create mode 100644 components/els_pkc/doc/mcxn/html/a00703.html create mode 100644 components/els_pkc/doc/mcxn/html/a00703.js create mode 100644 components/els_pkc/doc/mcxn/html/a00704.html create mode 100644 components/els_pkc/doc/mcxn/html/a00704.js create mode 100644 components/els_pkc/doc/mcxn/html/a00705.html create mode 100644 components/els_pkc/doc/mcxn/html/a00705.js create mode 100644 components/els_pkc/doc/mcxn/html/a00706.html create mode 100644 components/els_pkc/doc/mcxn/html/a00706.js create mode 100644 components/els_pkc/doc/mcxn/html/a00707.html create mode 100644 components/els_pkc/doc/mcxn/html/a00707.js create mode 100644 components/els_pkc/doc/mcxn/html/a00708.html create mode 100644 components/els_pkc/doc/mcxn/html/a00708.js create mode 100644 components/els_pkc/doc/mcxn/html/a00709.html create mode 100644 components/els_pkc/doc/mcxn/html/a00709.js create mode 100644 components/els_pkc/doc/mcxn/html/a00710.html create mode 100644 components/els_pkc/doc/mcxn/html/a00710.js create mode 100644 components/els_pkc/doc/mcxn/html/a00711.html create mode 100644 components/els_pkc/doc/mcxn/html/a00711.js create mode 100644 components/els_pkc/doc/mcxn/html/a00712.html create mode 100644 components/els_pkc/doc/mcxn/html/a00712.js create mode 100644 components/els_pkc/doc/mcxn/html/a00713.html create mode 100644 components/els_pkc/doc/mcxn/html/a00713.js create mode 100644 components/els_pkc/doc/mcxn/html/a00714.html create mode 100644 components/els_pkc/doc/mcxn/html/a00714.js create mode 100644 components/els_pkc/doc/mcxn/html/a00715.html create mode 100644 components/els_pkc/doc/mcxn/html/a00715.js create mode 100644 components/els_pkc/doc/mcxn/html/a00716.html create mode 100644 components/els_pkc/doc/mcxn/html/a00716.js create mode 100644 components/els_pkc/doc/mcxn/html/a00717.html create mode 100644 components/els_pkc/doc/mcxn/html/a00717.js create mode 100644 components/els_pkc/doc/mcxn/html/a00718.html create mode 100644 components/els_pkc/doc/mcxn/html/a00718.js create mode 100644 components/els_pkc/doc/mcxn/html/a00719.html create mode 100644 components/els_pkc/doc/mcxn/html/a00719.js create mode 100644 components/els_pkc/doc/mcxn/html/a00720.html create mode 100644 components/els_pkc/doc/mcxn/html/a00720.js create mode 100644 components/els_pkc/doc/mcxn/html/a00721.html create mode 100644 components/els_pkc/doc/mcxn/html/a00721.js create mode 100644 components/els_pkc/doc/mcxn/html/a00722.html create mode 100644 components/els_pkc/doc/mcxn/html/a00722.js create mode 100644 components/els_pkc/doc/mcxn/html/a00723.html create mode 100644 components/els_pkc/doc/mcxn/html/a00723.js create mode 100644 components/els_pkc/doc/mcxn/html/a00724.html create mode 100644 components/els_pkc/doc/mcxn/html/a00724.js create mode 100644 components/els_pkc/doc/mcxn/html/a00725.html create mode 100644 components/els_pkc/doc/mcxn/html/a00725.js create mode 100644 components/els_pkc/doc/mcxn/html/a00726.html create mode 100644 components/els_pkc/doc/mcxn/html/a00726.js create mode 100644 components/els_pkc/doc/mcxn/html/a00727.html create mode 100644 components/els_pkc/doc/mcxn/html/a00727.js create mode 100644 components/els_pkc/doc/mcxn/html/a00728.html create mode 100644 components/els_pkc/doc/mcxn/html/a00728.js create mode 100644 components/els_pkc/doc/mcxn/html/a00729.html create mode 100644 components/els_pkc/doc/mcxn/html/a00729.js create mode 100644 components/els_pkc/doc/mcxn/html/a00730.html create mode 100644 components/els_pkc/doc/mcxn/html/a00730.js create mode 100644 components/els_pkc/doc/mcxn/html/a00731.html create mode 100644 components/els_pkc/doc/mcxn/html/a00731.js create mode 100644 components/els_pkc/doc/mcxn/html/a00732.html create mode 100644 components/els_pkc/doc/mcxn/html/a00732.js create mode 100644 components/els_pkc/doc/mcxn/html/a00733.html create mode 100644 components/els_pkc/doc/mcxn/html/a00733.js create mode 100644 components/els_pkc/doc/mcxn/html/a00734.html create mode 100644 components/els_pkc/doc/mcxn/html/a00734.js create mode 100644 components/els_pkc/doc/mcxn/html/a00735.html create mode 100644 components/els_pkc/doc/mcxn/html/a00735.js create mode 100644 components/els_pkc/doc/mcxn/html/a00736.html create mode 100644 components/els_pkc/doc/mcxn/html/a00736.js create mode 100644 components/els_pkc/doc/mcxn/html/a00737.html create mode 100644 components/els_pkc/doc/mcxn/html/a00737.js create mode 100644 components/els_pkc/doc/mcxn/html/a00738.html create mode 100644 components/els_pkc/doc/mcxn/html/a00738.js create mode 100644 components/els_pkc/doc/mcxn/html/a00739.html create mode 100644 components/els_pkc/doc/mcxn/html/a00739.js create mode 100644 components/els_pkc/doc/mcxn/html/a00740.html create mode 100644 components/els_pkc/doc/mcxn/html/a00740.js create mode 100644 components/els_pkc/doc/mcxn/html/a00741.html create mode 100644 components/els_pkc/doc/mcxn/html/a00741.js create mode 100644 components/els_pkc/doc/mcxn/html/a00742.html create mode 100644 components/els_pkc/doc/mcxn/html/a00742.js create mode 100644 components/els_pkc/doc/mcxn/html/a00743.html create mode 100644 components/els_pkc/doc/mcxn/html/a00743.js create mode 100644 components/els_pkc/doc/mcxn/html/a00744.html create mode 100644 components/els_pkc/doc/mcxn/html/a00744.js create mode 100644 components/els_pkc/doc/mcxn/html/a00745.html create mode 100644 components/els_pkc/doc/mcxn/html/a00745.js create mode 100644 components/els_pkc/doc/mcxn/html/a00746.html create mode 100644 components/els_pkc/doc/mcxn/html/a00746.js create mode 100644 components/els_pkc/doc/mcxn/html/a00747.html create mode 100644 components/els_pkc/doc/mcxn/html/a00747.js create mode 100644 components/els_pkc/doc/mcxn/html/a00748.html create mode 100644 components/els_pkc/doc/mcxn/html/a00748.js create mode 100644 components/els_pkc/doc/mcxn/html/a00749.html create mode 100644 components/els_pkc/doc/mcxn/html/a00749.js create mode 100644 components/els_pkc/doc/mcxn/html/a00750.html create mode 100644 components/els_pkc/doc/mcxn/html/a00750.js create mode 100644 components/els_pkc/doc/mcxn/html/a00751.html create mode 100644 components/els_pkc/doc/mcxn/html/a00751.js create mode 100644 components/els_pkc/doc/mcxn/html/a00752.html create mode 100644 components/els_pkc/doc/mcxn/html/a00752.js create mode 100644 components/els_pkc/doc/mcxn/html/a00753.html create mode 100644 components/els_pkc/doc/mcxn/html/a00753.js create mode 100644 components/els_pkc/doc/mcxn/html/a00754.html create mode 100644 components/els_pkc/doc/mcxn/html/a00754.js create mode 100644 components/els_pkc/doc/mcxn/html/a00755.html create mode 100644 components/els_pkc/doc/mcxn/html/a00755.js create mode 100644 components/els_pkc/doc/mcxn/html/a00756.html create mode 100644 components/els_pkc/doc/mcxn/html/a00756.js create mode 100644 components/els_pkc/doc/mcxn/html/a00757.html create mode 100644 components/els_pkc/doc/mcxn/html/a00757.js create mode 100644 components/els_pkc/doc/mcxn/html/a00758.html create mode 100644 components/els_pkc/doc/mcxn/html/a00758.js create mode 100644 components/els_pkc/doc/mcxn/html/a00759.html create mode 100644 components/els_pkc/doc/mcxn/html/a00759.js create mode 100644 components/els_pkc/doc/mcxn/html/a00760.html create mode 100644 components/els_pkc/doc/mcxn/html/a00760.js create mode 100644 components/els_pkc/doc/mcxn/html/a00761.html create mode 100644 components/els_pkc/doc/mcxn/html/a00761.js create mode 100644 components/els_pkc/doc/mcxn/html/a00762.html create mode 100644 components/els_pkc/doc/mcxn/html/a00762.js create mode 100644 components/els_pkc/doc/mcxn/html/a00763.html create mode 100644 components/els_pkc/doc/mcxn/html/a00763.js create mode 100644 components/els_pkc/doc/mcxn/html/a00764.html create mode 100644 components/els_pkc/doc/mcxn/html/a00764.js create mode 100644 components/els_pkc/doc/mcxn/html/a00765.html create mode 100644 components/els_pkc/doc/mcxn/html/a00765.js create mode 100644 components/els_pkc/doc/mcxn/html/a00766.html create mode 100644 components/els_pkc/doc/mcxn/html/a00766.js create mode 100644 components/els_pkc/doc/mcxn/html/a00767.html create mode 100644 components/els_pkc/doc/mcxn/html/a00767.js create mode 100644 components/els_pkc/doc/mcxn/html/a00768.html create mode 100644 components/els_pkc/doc/mcxn/html/a00768.js create mode 100644 components/els_pkc/doc/mcxn/html/a00769.html create mode 100644 components/els_pkc/doc/mcxn/html/a00769.js create mode 100644 components/els_pkc/doc/mcxn/html/a00770.html create mode 100644 components/els_pkc/doc/mcxn/html/a00770.js create mode 100644 components/els_pkc/doc/mcxn/html/a00771.html create mode 100644 components/els_pkc/doc/mcxn/html/a00771.js create mode 100644 components/els_pkc/doc/mcxn/html/a00772.html create mode 100644 components/els_pkc/doc/mcxn/html/a00772.js create mode 100644 components/els_pkc/doc/mcxn/html/a00773.html create mode 100644 components/els_pkc/doc/mcxn/html/a00773.js create mode 100644 components/els_pkc/doc/mcxn/html/a00774.html create mode 100644 components/els_pkc/doc/mcxn/html/a00774.js create mode 100644 components/els_pkc/doc/mcxn/html/a00775.html create mode 100644 components/els_pkc/doc/mcxn/html/a00775.js create mode 100644 components/els_pkc/doc/mcxn/html/a00776.html create mode 100644 components/els_pkc/doc/mcxn/html/a00776.js create mode 100644 components/els_pkc/doc/mcxn/html/a00777.html create mode 100644 components/els_pkc/doc/mcxn/html/a00777.js create mode 100644 components/els_pkc/doc/mcxn/html/a00778.html create mode 100644 components/els_pkc/doc/mcxn/html/a00778.js create mode 100644 components/els_pkc/doc/mcxn/html/a00779.html create mode 100644 components/els_pkc/doc/mcxn/html/a00779.js create mode 100644 components/els_pkc/doc/mcxn/html/a00780.html create mode 100644 components/els_pkc/doc/mcxn/html/a00780.js create mode 100644 components/els_pkc/doc/mcxn/html/a00781.html create mode 100644 components/els_pkc/doc/mcxn/html/a00781.js create mode 100644 components/els_pkc/doc/mcxn/html/a00782.html create mode 100644 components/els_pkc/doc/mcxn/html/a00782.js create mode 100644 components/els_pkc/doc/mcxn/html/a00783.html create mode 100644 components/els_pkc/doc/mcxn/html/a00784.html create mode 100644 components/els_pkc/doc/mcxn/html/a00784.js create mode 100644 components/els_pkc/doc/mcxn/html/a00785.html create mode 100644 components/els_pkc/doc/mcxn/html/a00785.js create mode 100644 components/els_pkc/doc/mcxn/html/a00786.html create mode 100644 components/els_pkc/doc/mcxn/html/a00786.js create mode 100644 components/els_pkc/doc/mcxn/html/a00787.html create mode 100644 components/els_pkc/doc/mcxn/html/a00787.js create mode 100644 components/els_pkc/doc/mcxn/html/a00788.html create mode 100644 components/els_pkc/doc/mcxn/html/a00788.js create mode 100644 components/els_pkc/doc/mcxn/html/a00789.html create mode 100644 components/els_pkc/doc/mcxn/html/a00789.js create mode 100644 components/els_pkc/doc/mcxn/html/a00790.html create mode 100644 components/els_pkc/doc/mcxn/html/a00790.js create mode 100644 components/els_pkc/doc/mcxn/html/a00791.html create mode 100644 components/els_pkc/doc/mcxn/html/a00792.html create mode 100644 components/els_pkc/doc/mcxn/html/a00792.js create mode 100644 components/els_pkc/doc/mcxn/html/a00793.html create mode 100644 components/els_pkc/doc/mcxn/html/a00793.js create mode 100644 components/els_pkc/doc/mcxn/html/a00794.html create mode 100644 components/els_pkc/doc/mcxn/html/a00794.js create mode 100644 components/els_pkc/doc/mcxn/html/a00795.html create mode 100644 components/els_pkc/doc/mcxn/html/a00796.html create mode 100644 components/els_pkc/doc/mcxn/html/a00796.js create mode 100644 components/els_pkc/doc/mcxn/html/a00797.html create mode 100644 components/els_pkc/doc/mcxn/html/a00797.js create mode 100644 components/els_pkc/doc/mcxn/html/a00798.html create mode 100644 components/els_pkc/doc/mcxn/html/a00798.js create mode 100644 components/els_pkc/doc/mcxn/html/a00799.html create mode 100644 components/els_pkc/doc/mcxn/html/a00799.js create mode 100644 components/els_pkc/doc/mcxn/html/a00800.html create mode 100644 components/els_pkc/doc/mcxn/html/a00800.js create mode 100644 components/els_pkc/doc/mcxn/html/a00801.html create mode 100644 components/els_pkc/doc/mcxn/html/a00801.js create mode 100644 components/els_pkc/doc/mcxn/html/a00802.html create mode 100644 components/els_pkc/doc/mcxn/html/a00803.html create mode 100644 components/els_pkc/doc/mcxn/html/a00804.html create mode 100644 components/els_pkc/doc/mcxn/html/a00804.js create mode 100644 components/els_pkc/doc/mcxn/html/a00805.html create mode 100644 components/els_pkc/doc/mcxn/html/a00805.js create mode 100644 components/els_pkc/doc/mcxn/html/a00806.html create mode 100644 components/els_pkc/doc/mcxn/html/a00806.js create mode 100644 components/els_pkc/doc/mcxn/html/a00807.html create mode 100644 components/els_pkc/doc/mcxn/html/a00807.js create mode 100644 components/els_pkc/doc/mcxn/html/a00808.html create mode 100644 components/els_pkc/doc/mcxn/html/a00808.js create mode 100644 components/els_pkc/doc/mcxn/html/a00809.html create mode 100644 components/els_pkc/doc/mcxn/html/a00809.js create mode 100644 components/els_pkc/doc/mcxn/html/a00810.html create mode 100644 components/els_pkc/doc/mcxn/html/a00810.js create mode 100644 components/els_pkc/doc/mcxn/html/a00811.html create mode 100644 components/els_pkc/doc/mcxn/html/a00811.js create mode 100644 components/els_pkc/doc/mcxn/html/a00812.html create mode 100644 components/els_pkc/doc/mcxn/html/a00812.js create mode 100644 components/els_pkc/doc/mcxn/html/a00813.html create mode 100644 components/els_pkc/doc/mcxn/html/a00813.js create mode 100644 components/els_pkc/doc/mcxn/html/a00814.html create mode 100644 components/els_pkc/doc/mcxn/html/a00814.js create mode 100644 components/els_pkc/doc/mcxn/html/a00815.html create mode 100644 components/els_pkc/doc/mcxn/html/a00815.js create mode 100644 components/els_pkc/doc/mcxn/html/a00816.html create mode 100644 components/els_pkc/doc/mcxn/html/a00816.js create mode 100644 components/els_pkc/doc/mcxn/html/a00817.html create mode 100644 components/els_pkc/doc/mcxn/html/a00817.js create mode 100644 components/els_pkc/doc/mcxn/html/a00818.html create mode 100644 components/els_pkc/doc/mcxn/html/a00818.js create mode 100644 components/els_pkc/doc/mcxn/html/a00819.html create mode 100644 components/els_pkc/doc/mcxn/html/a00820.html create mode 100644 components/els_pkc/doc/mcxn/html/a00821.html create mode 100644 components/els_pkc/doc/mcxn/html/a00821.js create mode 100644 components/els_pkc/doc/mcxn/html/a00822.html create mode 100644 components/els_pkc/doc/mcxn/html/a00822.js create mode 100644 components/els_pkc/doc/mcxn/html/a00823.html create mode 100644 components/els_pkc/doc/mcxn/html/a00823.js create mode 100644 components/els_pkc/doc/mcxn/html/a00824.html create mode 100644 components/els_pkc/doc/mcxn/html/a00824.js create mode 100644 components/els_pkc/doc/mcxn/html/a00825.html create mode 100644 components/els_pkc/doc/mcxn/html/a00825.js create mode 100644 components/els_pkc/doc/mcxn/html/a00826.html create mode 100644 components/els_pkc/doc/mcxn/html/a00826.js create mode 100644 components/els_pkc/doc/mcxn/html/a00827.html create mode 100644 components/els_pkc/doc/mcxn/html/a00827.js create mode 100644 components/els_pkc/doc/mcxn/html/a00828.html create mode 100644 components/els_pkc/doc/mcxn/html/a00828.js create mode 100644 components/els_pkc/doc/mcxn/html/a00829.html create mode 100644 components/els_pkc/doc/mcxn/html/a00829.js create mode 100644 components/els_pkc/doc/mcxn/html/a00830.html create mode 100644 components/els_pkc/doc/mcxn/html/a00830.js create mode 100644 components/els_pkc/doc/mcxn/html/a00831.html create mode 100644 components/els_pkc/doc/mcxn/html/a00831.js create mode 100644 components/els_pkc/doc/mcxn/html/a00832.html create mode 100644 components/els_pkc/doc/mcxn/html/a00832.js create mode 100644 components/els_pkc/doc/mcxn/html/a00833.html create mode 100644 components/els_pkc/doc/mcxn/html/a00833.js create mode 100644 components/els_pkc/doc/mcxn/html/a00834.html create mode 100644 components/els_pkc/doc/mcxn/html/a00835.html create mode 100644 components/els_pkc/doc/mcxn/html/a00836.html create mode 100644 components/els_pkc/doc/mcxn/html/a00837.html create mode 100644 components/els_pkc/doc/mcxn/html/a00838.html create mode 100644 components/els_pkc/doc/mcxn/html/a00839.html create mode 100644 components/els_pkc/doc/mcxn/html/a00839.js create mode 100644 components/els_pkc/doc/mcxn/html/a00840.html create mode 100644 components/els_pkc/doc/mcxn/html/a00840.js create mode 100644 components/els_pkc/doc/mcxn/html/a00841.html create mode 100644 components/els_pkc/doc/mcxn/html/a00841.js create mode 100644 components/els_pkc/doc/mcxn/html/a00842.html create mode 100644 components/els_pkc/doc/mcxn/html/a00842.js create mode 100644 components/els_pkc/doc/mcxn/html/a00843.html create mode 100644 components/els_pkc/doc/mcxn/html/a00843.js create mode 100644 components/els_pkc/doc/mcxn/html/a00844.html create mode 100644 components/els_pkc/doc/mcxn/html/a00844.js create mode 100644 components/els_pkc/doc/mcxn/html/a00845.html create mode 100644 components/els_pkc/doc/mcxn/html/a00845.js create mode 100644 components/els_pkc/doc/mcxn/html/a00846.html create mode 100644 components/els_pkc/doc/mcxn/html/a00846.js create mode 100644 components/els_pkc/doc/mcxn/html/a00847.html create mode 100644 components/els_pkc/doc/mcxn/html/a00847.js create mode 100644 components/els_pkc/doc/mcxn/html/a00848.html create mode 100644 components/els_pkc/doc/mcxn/html/a00848.js create mode 100644 components/els_pkc/doc/mcxn/html/a00849.html create mode 100644 components/els_pkc/doc/mcxn/html/a00849.js create mode 100644 components/els_pkc/doc/mcxn/html/a00850.html create mode 100644 components/els_pkc/doc/mcxn/html/a00850.js create mode 100644 components/els_pkc/doc/mcxn/html/a00851.html create mode 100644 components/els_pkc/doc/mcxn/html/a00851.js create mode 100644 components/els_pkc/doc/mcxn/html/a00852.html create mode 100644 components/els_pkc/doc/mcxn/html/a00852.js create mode 100644 components/els_pkc/doc/mcxn/html/a00853.html create mode 100644 components/els_pkc/doc/mcxn/html/a00853.js create mode 100644 components/els_pkc/doc/mcxn/html/a00854.html create mode 100644 components/els_pkc/doc/mcxn/html/a00854.js create mode 100644 components/els_pkc/doc/mcxn/html/a00855.html create mode 100644 components/els_pkc/doc/mcxn/html/a00855.js create mode 100644 components/els_pkc/doc/mcxn/html/a00856.html create mode 100644 components/els_pkc/doc/mcxn/html/a00856.js create mode 100644 components/els_pkc/doc/mcxn/html/a00857.html create mode 100644 components/els_pkc/doc/mcxn/html/a00857.js create mode 100644 components/els_pkc/doc/mcxn/html/a00858.html create mode 100644 components/els_pkc/doc/mcxn/html/a00858.js create mode 100644 components/els_pkc/doc/mcxn/html/a00859.html create mode 100644 components/els_pkc/doc/mcxn/html/a00859.js create mode 100644 components/els_pkc/doc/mcxn/html/a00860.html create mode 100644 components/els_pkc/doc/mcxn/html/a00860.js create mode 100644 components/els_pkc/doc/mcxn/html/a00861.html create mode 100644 components/els_pkc/doc/mcxn/html/a00861.js create mode 100644 components/els_pkc/doc/mcxn/html/a00862.html create mode 100644 components/els_pkc/doc/mcxn/html/a00862.js create mode 100644 components/els_pkc/doc/mcxn/html/a00863.html create mode 100644 components/els_pkc/doc/mcxn/html/a00863.js create mode 100644 components/els_pkc/doc/mcxn/html/a00864.html create mode 100644 components/els_pkc/doc/mcxn/html/a00864.js create mode 100644 components/els_pkc/doc/mcxn/html/a00865.html create mode 100644 components/els_pkc/doc/mcxn/html/a00865.js create mode 100644 components/els_pkc/doc/mcxn/html/a00866.html create mode 100644 components/els_pkc/doc/mcxn/html/a00866.js create mode 100644 components/els_pkc/doc/mcxn/html/a00867.html create mode 100644 components/els_pkc/doc/mcxn/html/a00867.js create mode 100644 components/els_pkc/doc/mcxn/html/a00868.html create mode 100644 components/els_pkc/doc/mcxn/html/a00868.js create mode 100644 components/els_pkc/doc/mcxn/html/a00869.html create mode 100644 components/els_pkc/doc/mcxn/html/a00869.js create mode 100644 components/els_pkc/doc/mcxn/html/a00870.html create mode 100644 components/els_pkc/doc/mcxn/html/a00870.js create mode 100644 components/els_pkc/doc/mcxn/html/a00871.html create mode 100644 components/els_pkc/doc/mcxn/html/a00872.html create mode 100644 components/els_pkc/doc/mcxn/html/a00872.js create mode 100644 components/els_pkc/doc/mcxn/html/a00873.html create mode 100644 components/els_pkc/doc/mcxn/html/a00873.js create mode 100644 components/els_pkc/doc/mcxn/html/a00874.html create mode 100644 components/els_pkc/doc/mcxn/html/a00874.js create mode 100644 components/els_pkc/doc/mcxn/html/a00875.html create mode 100644 components/els_pkc/doc/mcxn/html/a00875.js create mode 100644 components/els_pkc/doc/mcxn/html/a00876.html create mode 100644 components/els_pkc/doc/mcxn/html/a00876.js create mode 100644 components/els_pkc/doc/mcxn/html/a00877.html create mode 100644 components/els_pkc/doc/mcxn/html/a00877.js create mode 100644 components/els_pkc/doc/mcxn/html/a00878.html create mode 100644 components/els_pkc/doc/mcxn/html/a00878.js create mode 100644 components/els_pkc/doc/mcxn/html/a00879.html create mode 100644 components/els_pkc/doc/mcxn/html/a00879.js create mode 100644 components/els_pkc/doc/mcxn/html/a00880.html create mode 100644 components/els_pkc/doc/mcxn/html/a00880.js create mode 100644 components/els_pkc/doc/mcxn/html/a00881.html create mode 100644 components/els_pkc/doc/mcxn/html/a00881.js create mode 100644 components/els_pkc/doc/mcxn/html/a00882.html create mode 100644 components/els_pkc/doc/mcxn/html/a00882.js create mode 100644 components/els_pkc/doc/mcxn/html/a00883.html create mode 100644 components/els_pkc/doc/mcxn/html/a00883.js create mode 100644 components/els_pkc/doc/mcxn/html/a00884.html create mode 100644 components/els_pkc/doc/mcxn/html/a00884.js create mode 100644 components/els_pkc/doc/mcxn/html/a00885.html create mode 100644 components/els_pkc/doc/mcxn/html/a00885.js create mode 100644 components/els_pkc/doc/mcxn/html/a00886.html create mode 100644 components/els_pkc/doc/mcxn/html/a00886.js create mode 100644 components/els_pkc/doc/mcxn/html/a00887.html create mode 100644 components/els_pkc/doc/mcxn/html/a00887.js create mode 100644 components/els_pkc/doc/mcxn/html/a00888.html create mode 100644 components/els_pkc/doc/mcxn/html/a00888.js create mode 100644 components/els_pkc/doc/mcxn/html/a00889.html create mode 100644 components/els_pkc/doc/mcxn/html/a00889.js create mode 100644 components/els_pkc/doc/mcxn/html/a00890.html create mode 100644 components/els_pkc/doc/mcxn/html/a00890.js create mode 100644 components/els_pkc/doc/mcxn/html/a00891.html create mode 100644 components/els_pkc/doc/mcxn/html/a00891.js create mode 100644 components/els_pkc/doc/mcxn/html/a00892.html create mode 100644 components/els_pkc/doc/mcxn/html/a00892.js create mode 100644 components/els_pkc/doc/mcxn/html/a00893.html create mode 100644 components/els_pkc/doc/mcxn/html/a00893.js create mode 100644 components/els_pkc/doc/mcxn/html/a00894.html create mode 100644 components/els_pkc/doc/mcxn/html/a00894.js create mode 100644 components/els_pkc/doc/mcxn/html/a00895.html create mode 100644 components/els_pkc/doc/mcxn/html/a00895.js create mode 100644 components/els_pkc/doc/mcxn/html/a00896.html create mode 100644 components/els_pkc/doc/mcxn/html/a00896.js create mode 100644 components/els_pkc/doc/mcxn/html/a00897.html create mode 100644 components/els_pkc/doc/mcxn/html/a00897.js create mode 100644 components/els_pkc/doc/mcxn/html/a00898.html create mode 100644 components/els_pkc/doc/mcxn/html/a00898.js create mode 100644 components/els_pkc/doc/mcxn/html/a00899.html create mode 100644 components/els_pkc/doc/mcxn/html/a00899.js create mode 100644 components/els_pkc/doc/mcxn/html/a00900.html create mode 100644 components/els_pkc/doc/mcxn/html/a00900.js create mode 100644 components/els_pkc/doc/mcxn/html/a00901.html create mode 100644 components/els_pkc/doc/mcxn/html/a00901.js create mode 100644 components/els_pkc/doc/mcxn/html/a00902.html create mode 100644 components/els_pkc/doc/mcxn/html/a00902.js create mode 100644 components/els_pkc/doc/mcxn/html/a00903.html create mode 100644 components/els_pkc/doc/mcxn/html/a00903.js create mode 100644 components/els_pkc/doc/mcxn/html/a00904.html create mode 100644 components/els_pkc/doc/mcxn/html/a00904.js create mode 100644 components/els_pkc/doc/mcxn/html/a00905.html create mode 100644 components/els_pkc/doc/mcxn/html/a00905.js create mode 100644 components/els_pkc/doc/mcxn/html/a00906.html create mode 100644 components/els_pkc/doc/mcxn/html/a00906.js create mode 100644 components/els_pkc/doc/mcxn/html/a00907.html create mode 100644 components/els_pkc/doc/mcxn/html/a00907.js create mode 100644 components/els_pkc/doc/mcxn/html/a00908.html create mode 100644 components/els_pkc/doc/mcxn/html/a00908.js create mode 100644 components/els_pkc/doc/mcxn/html/a00909.html create mode 100644 components/els_pkc/doc/mcxn/html/a00909.js create mode 100644 components/els_pkc/doc/mcxn/html/a00910.html create mode 100644 components/els_pkc/doc/mcxn/html/a00910.js create mode 100644 components/els_pkc/doc/mcxn/html/a00911.html create mode 100644 components/els_pkc/doc/mcxn/html/a00911.js create mode 100644 components/els_pkc/doc/mcxn/html/a00912.html create mode 100644 components/els_pkc/doc/mcxn/html/a00912.js create mode 100644 components/els_pkc/doc/mcxn/html/a00913.html create mode 100644 components/els_pkc/doc/mcxn/html/a00913.js create mode 100644 components/els_pkc/doc/mcxn/html/a00914.html create mode 100644 components/els_pkc/doc/mcxn/html/a00914.js create mode 100644 components/els_pkc/doc/mcxn/html/a00915.html create mode 100644 components/els_pkc/doc/mcxn/html/a00915.js create mode 100644 components/els_pkc/doc/mcxn/html/a00916.html create mode 100644 components/els_pkc/doc/mcxn/html/a00916.js create mode 100644 components/els_pkc/doc/mcxn/html/a00917.html create mode 100644 components/els_pkc/doc/mcxn/html/a00917.js create mode 100644 components/els_pkc/doc/mcxn/html/a00918.html create mode 100644 components/els_pkc/doc/mcxn/html/a00918.js create mode 100644 components/els_pkc/doc/mcxn/html/a00919.html create mode 100644 components/els_pkc/doc/mcxn/html/a00919.js create mode 100644 components/els_pkc/doc/mcxn/html/a00920.html create mode 100644 components/els_pkc/doc/mcxn/html/a00920.js create mode 100644 components/els_pkc/doc/mcxn/html/a00921.html create mode 100644 components/els_pkc/doc/mcxn/html/a00921.js create mode 100644 components/els_pkc/doc/mcxn/html/a00922.html create mode 100644 components/els_pkc/doc/mcxn/html/a00922.js create mode 100644 components/els_pkc/doc/mcxn/html/a00923.html create mode 100644 components/els_pkc/doc/mcxn/html/a00923.js create mode 100644 components/els_pkc/doc/mcxn/html/a00924.html create mode 100644 components/els_pkc/doc/mcxn/html/a00924.js create mode 100644 components/els_pkc/doc/mcxn/html/a00925.html create mode 100644 components/els_pkc/doc/mcxn/html/a00925.js create mode 100644 components/els_pkc/doc/mcxn/html/a00926.html create mode 100644 components/els_pkc/doc/mcxn/html/a00927.html create mode 100644 components/els_pkc/doc/mcxn/html/a00928.html create mode 100644 components/els_pkc/doc/mcxn/html/a00929.html create mode 100644 components/els_pkc/doc/mcxn/html/a00930.html create mode 100644 components/els_pkc/doc/mcxn/html/a00931.html create mode 100644 components/els_pkc/doc/mcxn/html/a00932.html create mode 100644 components/els_pkc/doc/mcxn/html/a00933.html create mode 100644 components/els_pkc/doc/mcxn/html/a00934.html create mode 100644 components/els_pkc/doc/mcxn/html/a00935.html create mode 100644 components/els_pkc/doc/mcxn/html/a00936.html create mode 100644 components/els_pkc/doc/mcxn/html/a00937.html create mode 100644 components/els_pkc/doc/mcxn/html/a00938.html create mode 100644 components/els_pkc/doc/mcxn/html/a00939.html create mode 100644 components/els_pkc/doc/mcxn/html/a00940.html create mode 100644 components/els_pkc/doc/mcxn/html/a00941.html create mode 100644 components/els_pkc/doc/mcxn/html/a00942.html create mode 100644 components/els_pkc/doc/mcxn/html/a00943.html create mode 100644 components/els_pkc/doc/mcxn/html/a00944.html create mode 100644 components/els_pkc/doc/mcxn/html/a00945.html create mode 100644 components/els_pkc/doc/mcxn/html/a00946.html create mode 100644 components/els_pkc/doc/mcxn/html/a00947.html create mode 100644 components/els_pkc/doc/mcxn/html/a00948.html create mode 100644 components/els_pkc/doc/mcxn/html/a00949.html create mode 100644 components/els_pkc/doc/mcxn/html/a00950.html create mode 100644 components/els_pkc/doc/mcxn/html/a00951.html create mode 100644 components/els_pkc/doc/mcxn/html/a00952.html create mode 100644 components/els_pkc/doc/mcxn/html/a00953.html create mode 100644 components/els_pkc/doc/mcxn/html/a00954.html create mode 100644 components/els_pkc/doc/mcxn/html/a00955.html create mode 100644 components/els_pkc/doc/mcxn/html/a00956.html create mode 100644 components/els_pkc/doc/mcxn/html/a00957.html create mode 100644 components/els_pkc/doc/mcxn/html/a00957.js create mode 100644 components/els_pkc/doc/mcxn/html/a00958.html create mode 100644 components/els_pkc/doc/mcxn/html/a00958.js create mode 100644 components/els_pkc/doc/mcxn/html/a00959.html create mode 100644 components/els_pkc/doc/mcxn/html/a00959.js create mode 100644 components/els_pkc/doc/mcxn/html/a00960.html create mode 100644 components/els_pkc/doc/mcxn/html/a00960.js create mode 100644 components/els_pkc/doc/mcxn/html/a00961.html create mode 100644 components/els_pkc/doc/mcxn/html/a00961.js create mode 100644 components/els_pkc/doc/mcxn/html/a00962.html create mode 100644 components/els_pkc/doc/mcxn/html/a00962.js create mode 100644 components/els_pkc/doc/mcxn/html/a00963.html create mode 100644 components/els_pkc/doc/mcxn/html/a00963.js create mode 100644 components/els_pkc/doc/mcxn/html/a00964.html create mode 100644 components/els_pkc/doc/mcxn/html/a00964.js create mode 100644 components/els_pkc/doc/mcxn/html/a00965.html create mode 100644 components/els_pkc/doc/mcxn/html/a00965.js create mode 100644 components/els_pkc/doc/mcxn/html/a00966.html create mode 100644 components/els_pkc/doc/mcxn/html/a00966.js create mode 100644 components/els_pkc/doc/mcxn/html/a00967.html create mode 100644 components/els_pkc/doc/mcxn/html/a00967.js create mode 100644 components/els_pkc/doc/mcxn/html/a00968.html create mode 100644 components/els_pkc/doc/mcxn/html/a00968.js create mode 100644 components/els_pkc/doc/mcxn/html/a00969.html create mode 100644 components/els_pkc/doc/mcxn/html/a00969.js create mode 100644 components/els_pkc/doc/mcxn/html/a00973.html create mode 100644 components/els_pkc/doc/mcxn/html/a00973.js create mode 100644 components/els_pkc/doc/mcxn/html/a00977.html create mode 100644 components/els_pkc/doc/mcxn/html/a00977.js create mode 100644 components/els_pkc/doc/mcxn/html/a00981.html create mode 100644 components/els_pkc/doc/mcxn/html/a00981.js create mode 100644 components/els_pkc/doc/mcxn/html/a00985.html create mode 100644 components/els_pkc/doc/mcxn/html/a00985.js create mode 100644 components/els_pkc/doc/mcxn/html/a00989.html create mode 100644 components/els_pkc/doc/mcxn/html/a00989.js create mode 100644 components/els_pkc/doc/mcxn/html/a00993.html create mode 100644 components/els_pkc/doc/mcxn/html/a00993.js create mode 100644 components/els_pkc/doc/mcxn/html/a00997.html create mode 100644 components/els_pkc/doc/mcxn/html/a00997.js create mode 100644 components/els_pkc/doc/mcxn/html/a01009.html create mode 100644 components/els_pkc/doc/mcxn/html/a01009.js create mode 100644 components/els_pkc/doc/mcxn/html/a01021.html create mode 100644 components/els_pkc/doc/mcxn/html/a01021.js create mode 100644 components/els_pkc/doc/mcxn/html/a01033.html create mode 100644 components/els_pkc/doc/mcxn/html/a01033.js create mode 100644 components/els_pkc/doc/mcxn/html/a01045.html create mode 100644 components/els_pkc/doc/mcxn/html/a01045.js create mode 100644 components/els_pkc/doc/mcxn/html/a01057.html create mode 100644 components/els_pkc/doc/mcxn/html/a01057.js create mode 100644 components/els_pkc/doc/mcxn/html/a01069.html create mode 100644 components/els_pkc/doc/mcxn/html/a01069.js create mode 100644 components/els_pkc/doc/mcxn/html/a01081.html create mode 100644 components/els_pkc/doc/mcxn/html/a01081.js create mode 100644 components/els_pkc/doc/mcxn/html/a01093.html create mode 100644 components/els_pkc/doc/mcxn/html/a01093.js create mode 100644 components/els_pkc/doc/mcxn/html/a01105.html create mode 100644 components/els_pkc/doc/mcxn/html/a01105.js create mode 100644 components/els_pkc/doc/mcxn/html/a01117.html create mode 100644 components/els_pkc/doc/mcxn/html/a01117.js create mode 100644 components/els_pkc/doc/mcxn/html/a01129.html create mode 100644 components/els_pkc/doc/mcxn/html/a01129.js create mode 100644 components/els_pkc/doc/mcxn/html/a01141.html create mode 100644 components/els_pkc/doc/mcxn/html/a01141.js create mode 100644 components/els_pkc/doc/mcxn/html/a01153.html create mode 100644 components/els_pkc/doc/mcxn/html/a01153.js create mode 100644 components/els_pkc/doc/mcxn/html/a01165.html create mode 100644 components/els_pkc/doc/mcxn/html/a01165.js create mode 100644 components/els_pkc/doc/mcxn/html/a01177.html create mode 100644 components/els_pkc/doc/mcxn/html/a01177.js create mode 100644 components/els_pkc/doc/mcxn/html/a01189.html create mode 100644 components/els_pkc/doc/mcxn/html/a01189.js create mode 100644 components/els_pkc/doc/mcxn/html/a01201.html create mode 100644 components/els_pkc/doc/mcxn/html/a01201.js create mode 100644 components/els_pkc/doc/mcxn/html/a01213.html create mode 100644 components/els_pkc/doc/mcxn/html/a01213.js create mode 100644 components/els_pkc/doc/mcxn/html/a01225.html create mode 100644 components/els_pkc/doc/mcxn/html/a01225.js create mode 100644 components/els_pkc/doc/mcxn/html/a01237.html create mode 100644 components/els_pkc/doc/mcxn/html/a01237.js create mode 100644 components/els_pkc/doc/mcxn/html/a01249.html create mode 100644 components/els_pkc/doc/mcxn/html/a01249.js create mode 100644 components/els_pkc/doc/mcxn/html/a01253.html create mode 100644 components/els_pkc/doc/mcxn/html/a01253.js create mode 100644 components/els_pkc/doc/mcxn/html/a01257.html create mode 100644 components/els_pkc/doc/mcxn/html/a01257.js create mode 100644 components/els_pkc/doc/mcxn/html/a01261.html create mode 100644 components/els_pkc/doc/mcxn/html/a01261.js create mode 100644 components/els_pkc/doc/mcxn/html/a01265.html create mode 100644 components/els_pkc/doc/mcxn/html/a01265.js create mode 100644 components/els_pkc/doc/mcxn/html/a01269.html create mode 100644 components/els_pkc/doc/mcxn/html/a01269.js create mode 100644 components/els_pkc/doc/mcxn/html/a01273.html create mode 100644 components/els_pkc/doc/mcxn/html/a01273.js create mode 100644 components/els_pkc/doc/mcxn/html/a01277.html create mode 100644 components/els_pkc/doc/mcxn/html/a01277.js create mode 100644 components/els_pkc/doc/mcxn/html/a01281.html create mode 100644 components/els_pkc/doc/mcxn/html/a01281.js create mode 100644 components/els_pkc/doc/mcxn/html/a01285.html create mode 100644 components/els_pkc/doc/mcxn/html/a01285.js create mode 100644 components/els_pkc/doc/mcxn/html/a01286.html create mode 100644 components/els_pkc/doc/mcxn/html/a01287.html create mode 100644 components/els_pkc/doc/mcxn/html/a01288.html create mode 100644 components/els_pkc/doc/mcxn/html/a01289.html create mode 100644 components/els_pkc/doc/mcxn/html/a01290.html create mode 100644 components/els_pkc/doc/mcxn/html/a01291.html create mode 100644 components/els_pkc/doc/mcxn/html/a01292.html create mode 100644 components/els_pkc/doc/mcxn/html/a01293.html create mode 100644 components/els_pkc/doc/mcxn/html/a01294.html create mode 100644 components/els_pkc/doc/mcxn/html/a01295.html create mode 100644 components/els_pkc/doc/mcxn/html/a01296.html create mode 100644 components/els_pkc/doc/mcxn/html/a01297.html create mode 100644 components/els_pkc/doc/mcxn/html/a01298.html create mode 100644 components/els_pkc/doc/mcxn/html/a01299.html create mode 100644 components/els_pkc/doc/mcxn/html/a01300.html create mode 100644 components/els_pkc/doc/mcxn/html/a01301.html create mode 100644 components/els_pkc/doc/mcxn/html/a01302.html create mode 100644 components/els_pkc/doc/mcxn/html/a01303.html create mode 100644 components/els_pkc/doc/mcxn/html/a01304.html create mode 100644 components/els_pkc/doc/mcxn/html/a01305.html create mode 100644 components/els_pkc/doc/mcxn/html/a01307.html create mode 100644 components/els_pkc/doc/mcxn/html/a01308.html create mode 100644 components/els_pkc/doc/mcxn/html/a01309.html create mode 100644 components/els_pkc/doc/mcxn/html/a01310.html create mode 100644 components/els_pkc/doc/mcxn/html/a01311.html create mode 100644 components/els_pkc/doc/mcxn/html/a01312.html create mode 100644 components/els_pkc/doc/mcxn/html/a01313.html create mode 100644 components/els_pkc/doc/mcxn/html/a01314.html create mode 100644 components/els_pkc/doc/mcxn/html/a01315.html create mode 100644 components/els_pkc/doc/mcxn/html/a01316.html create mode 100644 components/els_pkc/doc/mcxn/html/a01317.html create mode 100644 components/els_pkc/doc/mcxn/html/a01318.html create mode 100644 components/els_pkc/doc/mcxn/html/a01319.html create mode 100644 components/els_pkc/doc/mcxn/html/a01320.html create mode 100644 components/els_pkc/doc/mcxn/html/a01321.html create mode 100644 components/els_pkc/doc/mcxn/html/annotated.html create mode 100644 components/els_pkc/doc/mcxn/html/annotated_dup.js create mode 100644 components/els_pkc/doc/mcxn/html/bc_s.png create mode 100644 components/els_pkc/doc/mcxn/html/bdwn.png create mode 100644 components/els_pkc/doc/mcxn/html/classes.html create mode 100644 components/els_pkc/doc/mcxn/html/closed.png create mode 100644 components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_1ef99d9f3941c1bb5bff22950fd24df0.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_26570dcca9ee0bc63023bb3cebfd7781.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_2c12341984063bfcf36407a836e9dc8b.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_2c12341984063bfcf36407a836e9dc8b.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_397074c11054ba9b56701968f508752f.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_397074c11054ba9b56701968f508752f.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_48667f1bea109c59ee8faafddd8eabef.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_48667f1bea109c59ee8faafddd8eabef.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_596401c3c8fefb49e213c913ed9c7192.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_596401c3c8fefb49e213c913ed9c7192.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_68d0113f5403700f3062397be9dd82ba.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_6bb1d262d2f1e2da7d1b3eb7f0841c25.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_789b10fbea7cebd033e3b0362b1fecef.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_789b10fbea7cebd033e3b0362b1fecef.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_9f351d46ce3cc29445a41dc3a31e6919.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.js create mode 100644 components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.html create mode 100644 components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.js create mode 100644 components/els_pkc/doc/mcxn/html/doc.png create mode 100644 components/els_pkc/doc/mcxn/html/doxygen.css create mode 100644 components/els_pkc/doc/mcxn/html/doxygen.png create mode 100644 components/els_pkc/doc/mcxn/html/dynsections.js create mode 100644 components/els_pkc/doc/mcxn/html/examples.html create mode 100644 components/els_pkc/doc/mcxn/html/examples.js create mode 100644 components/els_pkc/doc/mcxn/html/files.html create mode 100644 components/els_pkc/doc/mcxn/html/files_dup.js create mode 100644 components/els_pkc/doc/mcxn/html/folderclosed.png create mode 100644 components/els_pkc/doc/mcxn/html/folderopen.png create mode 100644 components/els_pkc/doc/mcxn/html/functions.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_a.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_b.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_c.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_d.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_dup.js create mode 100644 components/els_pkc/doc/mcxn/html/functions_e.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_f.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_g.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_h.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_i.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_k.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_l.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_m.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_o.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_p.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_r.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_s.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_t.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_u.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_v.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars.js create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_a.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_b.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_c.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_d.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_e.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_f.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_g.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_h.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_i.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_k.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_l.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_m.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_o.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_p.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_r.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_s.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_t.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_u.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_v.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_vars_w.html create mode 100644 components/els_pkc/doc/mcxn/html/functions_w.html create mode 100644 components/els_pkc/doc/mcxn/html/globals.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_a.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_d.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs.js create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs_e.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs_m.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs_r.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_defs_u.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_dup.js create mode 100644 components/els_pkc/doc/mcxn/html/globals_e.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_func.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_g.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_k.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_m.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_r.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_s.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_type.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_u.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars.js create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_d.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_e.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_g.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_k.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_m.html create mode 100644 components/els_pkc/doc/mcxn/html/globals_vars_s.html create mode 100644 components/els_pkc/doc/mcxn/html/index.html create mode 100644 components/els_pkc/doc/mcxn/html/jquery.js create mode 100644 components/els_pkc/doc/mcxn/html/modules.html create mode 100644 components/els_pkc/doc/mcxn/html/modules.js create mode 100644 components/els_pkc/doc/mcxn/html/nav_f.png create mode 100644 components/els_pkc/doc/mcxn/html/nav_g.png create mode 100644 components/els_pkc/doc/mcxn/html/nav_h.png create mode 100644 components/els_pkc/doc/mcxn/html/navtree.css create mode 100644 components/els_pkc/doc/mcxn/html/navtree.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreedata.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex0.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex1.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex10.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex11.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex12.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex13.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex14.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex15.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex16.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex17.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex18.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex19.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex2.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex20.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex21.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex22.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex23.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex24.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex25.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex26.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex27.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex28.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex29.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex3.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex30.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex31.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex32.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex33.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex34.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex35.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex36.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex37.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex38.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex39.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex4.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex40.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex41.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex42.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex43.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex44.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex5.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex6.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex7.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex8.js create mode 100644 components/els_pkc/doc/mcxn/html/navtreeindex9.js create mode 100644 components/els_pkc/doc/mcxn/html/open.png create mode 100644 components/els_pkc/doc/mcxn/html/pages.html create mode 100644 components/els_pkc/doc/mcxn/html/resize.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_0.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_0.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_1.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_1.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_10.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_10.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_11.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_11.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_12.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_12.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_13.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_13.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_14.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_14.js create mode 100644 components/els_pkc/doc/mcxn/html/search/all_2.html create mode 100644 components/els_pkc/doc/mcxn/html/search/all_2.js create mode 100644 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components/els_pkc/doc/mcxn/html/search/close.png create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_0.html create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_0.js create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_1.html create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_1.js create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_2.html create mode 100644 components/els_pkc/doc/mcxn/html/search/defines_2.js create mode 100644 components/els_pkc/doc/mcxn/html/search/files_0.html create mode 100644 components/els_pkc/doc/mcxn/html/search/files_0.js create mode 100644 components/els_pkc/doc/mcxn/html/search/files_1.html create mode 100644 components/els_pkc/doc/mcxn/html/search/files_1.js create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_0.html create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_0.js create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_1.html create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_1.js create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_2.html create mode 100644 components/els_pkc/doc/mcxn/html/search/functions_2.js create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_0.html create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_0.js create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_1.html create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_1.js create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_2.html create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_2.js create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_3.html create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_3.js create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_4.html create mode 100644 components/els_pkc/doc/mcxn/html/search/groups_4.js create mode 100644 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components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Els_Oneshot_External_Key_example.c create mode 100644 components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Sw_Oneshot_example.c create mode 100644 components/els_pkc/examples/mcuxClKey/mcuxClKey_example.c create mode 100644 components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_multipart_zero_padding_example.c create mode 100644 components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_oneshot_example.c create mode 100644 components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c create mode 100644 components/els_pkc/examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c create mode 100644 components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c create mode 100644 components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c create mode 100644 components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c create mode 100644 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create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Types.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_KeyTypes.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyAgreement.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyGeneration.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_DhSetupEnvironment.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c create mode 100644 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components/els_pkc/src/comps/mcuxClPrng/src/mcuxClPrng_ELS.c create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Memory.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Types.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Constants.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Functions.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Types.h create mode 100644 components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_DRBG.c create mode 100644 components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_PRNG.c create mode 100644 components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Internal_SizeDefinitions.h create mode 100644 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components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PrDisabled.c create mode 100644 components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_TestMode.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_ComputeD_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Functions.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Macros.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_MemoryConsumption.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcDefs.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcTypes.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Types.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_KeyGeneration_Crt_FUP.h create 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components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_KeyGeneration_Crt_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MemoryConsumption.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MillerRabinTest_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_PrivateCrt_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Public_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_RemoveBlinding_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPQDistance_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPrimeCandidate_FUP.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Types.h create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_GenerateProbablePrime.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Plain.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Mgf1.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ModInv.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoEncode.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoVerify.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Encode_sign.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Verify.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivatePlain.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssEncode.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssVerify.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Sign.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate_FUP.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Verify.c create mode 100644 components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_VerifyE.c create mode 100644 components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal.h create mode 100644 components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal_Functions.h create mode 100644 components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession.h create mode 100644 components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Functions.h create mode 100644 components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Types.h create mode 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components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h create mode 100644 components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h create mode 100644 components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h create mode 100644 components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h create mode 100644 components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h create mode 100644 components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c create mode 100644 components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c create mode 100644 components/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h create mode 100644 components/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c create mode 100644 components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h create mode 100644 components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h create mode 100644 components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h create mode 100644 components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h create mode 100644 components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h create mode 100644 components/els_pkc/src/inc/impl/mcuxCl_clns_impl.h create mode 100644 components/els_pkc/src/inc/mcuxCl_clns.h create mode 100644 components/els_pkc/src/platforms/mcxn/inc/ip_css_constants.h create mode 100644 components/els_pkc/src/platforms/mcxn/inc/ip_css_design_configuration.h create mode 100644 components/els_pkc/src/platforms/mcxn/inc/ip_platform.h create mode 100644 components/els_pkc/src/platforms/mcxn/mcuxClConfig.h create mode 100644 components/els_pkc/src/platforms/mcxn/mcux_els.c create mode 100644 components/els_pkc/src/platforms/mcxn/mcux_els.h create mode 100644 components/els_pkc/src/platforms/mcxn/mcux_pkc.c create mode 100644 components/els_pkc/src/platforms/mcxn/mcux_pkc.h create mode 100644 components/els_pkc/src/platforms/mcxn/platform_specific_headers.h create mode 100644 components/els_pkc/static_library/mcxn/libclns.a create mode 100644 components/els_pkc/static_library/mcxn/libclns.a.libsize create mode 100644 components/els_pkc/static_library/mcxn/libclns.a.objsize create mode 100644 components/els_pkc/static_library/mcxn/libclns.stripped.a create mode 100644 components/flash/mflash/mcxnx4x/mflash_drv.c create mode 100644 components/flash/mflash/mcxnx4x/mflash_drv.h create mode 100644 components/p3t1755/fsl_p3t1755.c create mode 100644 components/p3t1755/fsl_p3t1755.h create mode 100644 components/phy/device/phylan8741/fsl_phylan8741.c create mode 100644 components/phy/device/phylan8741/fsl_phylan8741.h create mode 100644 components/st7796s/fsl_st7796s.c create mode 100644 components/st7796s/fsl_st7796s.h create mode 100644 components/video/camera/device/ov7670/fsl_ov7670.c create mode 100644 components/video/camera/device/ov7670/fsl_ov7670.h create mode 100644 components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h create mode 100644 components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h create mode 100644 components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h create mode 100644 components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h create mode 100644 components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_WW.h create mode 100644 components/wifi_bt_module/incl/wifi_bt_module_config.h create mode 100644 components/wifi_bt_module/u-blox/tx_pwr_limits/wlan_txpwrlimit_cfg_jody_w5_WW.h create mode 100644 devices/MCXN235/MCXN235.h create mode 100644 devices/MCXN235/MCXN235_features.h create mode 100644 devices/MCXN235/drivers/fsl_clock.c create mode 100644 devices/MCXN235/drivers/fsl_clock.h create mode 100644 devices/MCXN235/drivers/fsl_edma_soc.c create mode 100644 devices/MCXN235/drivers/fsl_edma_soc.h create mode 100644 devices/MCXN235/drivers/fsl_inputmux_connections.h create mode 100644 devices/MCXN235/drivers/fsl_reset.c create mode 100644 devices/MCXN235/drivers/fsl_reset.h create mode 100644 devices/MCXN235/fsl_device_registers.h create mode 100644 devices/MCXN235/gcc/MCXN235_flash.ld create mode 100644 devices/MCXN235/gcc/MCXN235_ram.ld create mode 100644 devices/MCXN235/gcc/startup_MCXN235.S create mode 100644 devices/MCXN235/mcuxpresso/startup_mcxn235.c create mode 100644 devices/MCXN235/mcuxpresso/startup_mcxn235.cpp create mode 100644 devices/MCXN235/project_template/board.c create mode 100644 devices/MCXN235/project_template/board.h create mode 100644 devices/MCXN235/project_template/clock_config.c create mode 100644 devices/MCXN235/project_template/clock_config.h create mode 100644 devices/MCXN235/project_template/peripherals.c create mode 100644 devices/MCXN235/project_template/peripherals.h create mode 100644 devices/MCXN235/project_template/pin_mux.c create mode 100644 devices/MCXN235/project_template/pin_mux.h create mode 100644 devices/MCXN235/set_device_MCXN235.cmake create mode 100644 devices/MCXN235/system_MCXN235.c create mode 100644 devices/MCXN235/system_MCXN235.h create mode 100644 devices/MCXN235/template/RTE_Device.h create mode 100644 devices/MCXN236/MCXN236.h create mode 100644 devices/MCXN236/MCXN236_features.h create mode 100644 devices/MCXN236/all_lib_device.cmake create mode 100644 devices/MCXN236/drivers/fsl_clock.c create mode 100644 devices/MCXN236/drivers/fsl_clock.h create mode 100644 devices/MCXN236/drivers/fsl_edma_soc.c create mode 100644 devices/MCXN236/drivers/fsl_edma_soc.h create mode 100644 devices/MCXN236/drivers/fsl_inputmux_connections.h create mode 100644 devices/MCXN236/drivers/fsl_reset.c create mode 100644 devices/MCXN236/drivers/fsl_reset.h create mode 100644 devices/MCXN236/fsl_device_registers.h create mode 100644 devices/MCXN236/gcc/MCXN236_flash.ld create mode 100644 devices/MCXN236/gcc/MCXN236_ram.ld create mode 100644 devices/MCXN236/gcc/startup_MCXN236.S create mode 100644 devices/MCXN236/mcuxpresso/startup_mcxn236.c create mode 100644 devices/MCXN236/mcuxpresso/startup_mcxn236.cpp create mode 100644 devices/MCXN236/project_template/board.c create mode 100644 devices/MCXN236/project_template/board.h create mode 100644 devices/MCXN236/project_template/clock_config.c create mode 100644 devices/MCXN236/project_template/clock_config.h create mode 100644 devices/MCXN236/project_template/peripherals.c create mode 100644 devices/MCXN236/project_template/peripherals.h create mode 100644 devices/MCXN236/project_template/pin_mux.c create mode 100644 devices/MCXN236/project_template/pin_mux.h create mode 100644 devices/MCXN236/set_device_MCXN236.cmake create mode 100644 devices/MCXN236/system_MCXN236.c create mode 100644 devices/MCXN236/system_MCXN236.h create mode 100644 devices/MCXN236/template/RTE_Device.h create mode 100644 drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c create mode 100644 drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.h create mode 100644 drivers/edma4/fsl_edma.c create mode 100644 drivers/edma4/fsl_edma.h create mode 100644 drivers/edma4/fsl_edma_core.h create mode 100644 drivers/eim/fsl_eim.c create mode 100644 drivers/eim/fsl_eim.h create mode 100644 drivers/erm/fsl_erm.c create mode 100644 drivers/erm/fsl_erm.h create mode 100644 drivers/evtg/fsl_evtg.c create mode 100644 drivers/evtg/fsl_evtg.h create mode 100644 drivers/i3c/fsl_i3c_edma.c create mode 100644 drivers/i3c/fsl_i3c_edma.h create mode 100644 drivers/intm/fsl_intm.c create mode 100644 drivers/intm/fsl_intm.h create mode 100644 drivers/lpflexcomm/fsl_lpflexcomm.c create mode 100644 drivers/lpflexcomm/fsl_lpflexcomm.h create mode 100644 drivers/lpflexcomm/fsl_lpi2c_freertos.c create mode 100644 drivers/lpflexcomm/fsl_lpi2c_freertos.h create mode 100644 drivers/lpflexcomm/fsl_lpspi_freertos.c create mode 100644 drivers/lpflexcomm/fsl_lpspi_freertos.h create mode 100644 drivers/lpflexcomm/fsl_lpuart_freertos.c create mode 100644 drivers/lpflexcomm/fsl_lpuart_freertos.h create mode 100644 drivers/lpflexcomm/lpi2c/fsl_lpi2c.c create mode 100644 drivers/lpflexcomm/lpi2c/fsl_lpi2c.h create mode 100644 drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c create mode 100644 drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.h create mode 100644 drivers/lpflexcomm/lpspi/fsl_lpspi.c create mode 100644 drivers/lpflexcomm/lpspi/fsl_lpspi.h create mode 100644 drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c create mode 100644 drivers/lpflexcomm/lpspi/fsl_lpspi_edma.h create mode 100644 drivers/lpflexcomm/lpuart/fsl_lpuart.c create mode 100644 drivers/lpflexcomm/lpuart/fsl_lpuart.h create mode 100644 drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c create mode 100644 drivers/lpflexcomm/lpuart/fsl_lpuart_edma.h create mode 100644 drivers/mcx_cmc/fsl_cmc.c create mode 100644 drivers/mcx_cmc/fsl_cmc.h create mode 100644 drivers/mcx_romapi/flash/fsl_efuse.h create mode 100644 drivers/mcx_romapi/flash/fsl_flash.h create mode 100644 drivers/mcx_romapi/flash/fsl_flash_ffr.h create mode 100644 drivers/mcx_romapi/flash/fsl_flexspi_nor_flash.h create mode 100644 drivers/mcx_romapi/flash/src/fsl_flash.c create mode 100644 drivers/mcx_romapi/mem_interface/fsl_mem_interface.h create mode 100644 drivers/mcx_romapi/mem_interface/fsl_sbloader.h create mode 100644 drivers/mcx_romapi/mem_interface/fsl_sbloader_v3.h create mode 100644 drivers/mcx_romapi/mem_interface/src/fsl_mem_interface.c create mode 100644 drivers/mcx_romapi/nboot/fsl_nboot.h create mode 100644 drivers/mcx_romapi/nboot/fsl_nboot_hal.h create mode 100644 drivers/mcx_romapi/nboot/src/fsl_nboot.c create mode 100644 drivers/mcx_romapi/runbootloader/fsl_runbootloader.h create mode 100644 drivers/mcx_romapi/runbootloader/src/fsl_runbootloader.c create mode 100644 drivers/mcx_spc/fsl_spc.c create mode 100644 drivers/mcx_spc/fsl_spc.h create mode 100644 drivers/mcx_vbat/fsl_vbat.c create mode 100644 drivers/mcx_vbat/fsl_vbat.h create mode 100644 drivers/qdc/fsl_qdc.c create mode 100644 drivers/qdc/fsl_qdc.h create mode 100644 drivers/smartdma/fsl_smartdma_mcxn.c create mode 100644 drivers/smartdma/fsl_smartdma_mcxn.h create mode 100644 drivers/smartdma/fsl_smartdma_rt500.c create mode 100644 drivers/smartdma/fsl_smartdma_rt500.h create mode 100644 drivers/syspm/fsl_syspm.c create mode 100644 drivers/syspm/fsl_syspm.h create mode 100644 drivers/tdet/fsl_tdet.c create mode 100644 drivers/tdet/fsl_tdet.h create mode 100644 drivers/wuu/fsl_wuu.c create mode 100644 drivers/wuu/fsl_wuu.h create mode 100644 manifests/FRDM-MCXN236_manifest_v3_13.xml diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt index a8915ebb1..3a7baa8db 100644 --- a/SW-Content-Register.txt +++ b/SW-Content-Register.txt @@ -2,62 +2,6 @@ Release Name: MCUXpresso Software Development Kit (SDK) Release Version: 2.14.0 Package License: LA_OPT_NXP_Software_License.txt v45 May 2023- Additional Distribution License granted, license in Section 2.3 applies -SDK_Examples Name: SDK examples - Version: NA - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, binary, project files, linker - files - Description: SDK out of box examples to show how - to use peripheral drivers and integrate - middleware. - Location: boards// - Origin: NXP (BSD-3-Clause) - -segger_sysview Name: Segger SystemView Demo - Version: 3.30 - Outgoing License: BSD-1-Clause - License File: - boards//freertos_examples/visualization/fre - ertos_segger_sysview/LICENSE - Format: source code - Description: Segger SystemView demo - Location: - boards//freertos_examples/visualization/fre - ertos_segger_sysview - Origin: Segger (BSD-1-Clause) - Url: - https://www.segger.com/products/development-tools/ - systemview/ - -maestro_framework Name: Maestro Audio Framework - Version: 1.6.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Source - Description: Maestro MCU Audio Framework - Location: middleware/maestro - Origin: NXP (Proprietary) Flac (BSD 3-clause) Ogg - (BSD 3-clause) Opus (BSD 3-clause) Opusfile (BSD - 3-clause) - Url: https://github.com/xiph/flac - https://github.com/xiph/ogg - https://github.com/xiph/opus - https://github.com/xiph/opusfile - -wifi Name: NXP Wi-Fi driver - Version: 1.3.46 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, header files, firmware - binaries - Description: NXP Wi-Fi driver and networking - utilities - Location: middleware/wifi_nxp - Origin: NXP (BSD-3-Clause) - SDK_Peripheral_Driver Name: SDK Peripheral Driver Version: 2.x.x Outgoing License: BSD-3-Clause @@ -99,8 +43,9 @@ cmsis_drivers Name: SDK CMSIS Peripheral Drivers application reusable across a wide range of supported microcontroller devices. Location: devices//cmsis_drivers - Origin: NXP (Apache-2.0) - ARM (Apache-2.0) - https://github.com/ARM-software/CMSIS_5/releases/tag/5.8.0 + Origin: NXP (Apache-2.0) ARM (Apache-2.0) - + https://github.com/ARM-software/CMSIS_5/releases/t + ag/5.8.0 CMSIS Name: CMSIS Version: 5.8.0 @@ -112,29 +57,23 @@ CMSIS Name: CMSIS based on Arm Cortex processors, distributed by ARM. cores Location: CMSIS/ - Origin: ARM (Apache-2.0) - https://github.com/ARM-software/CMSIS_5/releases/tag/5.8.0 + Origin: ARM (Apache-2.0) - + https://github.com/ARM-software/CMSIS_5/releases/t + ag/5.8.0 -eap Name: EAP - Version: 3.0.12 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - XTENSA/ARMDS example application project - Description: essential audio processing library - EAP16 v3.0.12 for CM7, FusionF1, Hifi4 + EAP16 - windows lib for simulation EAP32 v1.0.1 for RT600 - + EAP32 v1.0.2 for CM7 + EAP32 windows lib for - simulation(v1.0.2) - Location: middleware/EAP - Origin: NXP (Proprietary) - Url: - https://www.youtube.com/watch?v=qZ1fhDc27UU&featur - e=youtu.be +mbedtls Name: Mbed TLS + Version: 2.28.5 + Outgoing License: Apache-2.0 + License File: middleware/mbedtls/LICENSE + Format: source code + Description: Cryptographic and SSL/TLS Library + Location: middleware/mbedtls + Origin: ARM(Apache-2.0) - + https://github.com/Mbed-TLS/mbedtls/releases/tag/v + 2.28.3 fatfs Name: FatFs - Version: 0.14b + Version: R0.15 Outgoing License: FatFs License Approved open source license: Yes License File: middleware/fatfs/LICENSE.txt @@ -146,20 +85,19 @@ fatfs Name: FatFs city, Japan (FatFs License) Url: http://elm-chan.org/fsw/ff/00index_e.html -freertos-kernel Name: FreeRTOS kernel - Version: 10.5.1 - Outgoing License: MIT - License File: - rtos/freertos/freertos-kernel/LICENSE.md +usb Name: USB + Version: 2.9.1 + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 Format: source code - Description: Open source RTOS kernel for small - devices - Location: rtos/freertos/freertos-kernel - Origin: Amazon (MIT) - Url: https://github.com/FreeRTOS/FreeRTOS-Kernel + Description: NXP USB stack. This is a version of + the USB stack that has been integrated with the + MCUXpresso SDK. + Location: middleware/usb + Origin: NXP (BSD-3-Clause) littlefs Name: LittleFS - Version: 2.5.0 + Version: 2.8.0 Outgoing License: BSD-3-Clause License File: middleware/littlefs/LICENSE.md Format: source code @@ -170,53 +108,37 @@ littlefs Name: LittleFS (https://github.com/geky/) Url: https://github.com/littlefs-project/littlefs -lwip Name: lwIP TCP/IP Stack - Version: lwIP git repository (2023-01-03, branch: - master, SHA-1: - 3fe8d2fc43a9b69f7ed28c63d44a7744f9c0def9) - Outgoing License: BSD-3-Clause - License File: middleware/lwip/COPYING - Format: source code - Description: A light-weight TCP/IP stack - Location: middleware/lwip - Origin: NXP (BSD-3-Clause) Swedish Institute of - Computer Science (BSD-3-Clause) - - http://savannah.nongnu.org/projects/lwip - -mcuboot Name: MCUBoot - Version: 1.9.0 - Outgoing License: Apache-2.0 +freertos-kernel Name: FreeRTOS kernel + Version: 10.5.1 + Outgoing License: MIT License File: - middleware/mcuboot_opensource/LICENSE - Format: source code - Description: MCUBoot - a bootloader for - microcontrollers - Location: middleware/mcuboot_opensource - Origin: MCUBoot https://www.mcuboot.com/ - Url: https://github.com/mcu-tools/mcuboot - -mmcau Name: mmCAU S/W Library - Version: 2.0.4 - Outgoing License: BSD-3-Clause - License File: middleware/mmcau/LICENSE + rtos/freertos/freertos-kernel/LICENSE.md Format: source code - Description: S/W library that works with the - memory-mapped cryptographic acceleration unit - present on some MCUXpresso SoCs - Location: middleware/mmcau - Origin: NXP (BSD-3-Clause) + Description: Open source RTOS kernel for small + devices + Location: rtos/freertos/freertos-kernel + Origin: Amazon (MIT) + Url: https://github.com/FreeRTOS/FreeRTOS-Kernel -multicore_mcmgr Name: MCMGR - Version: 4.1.4 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: Multicore manager - Location: middleware/multicore/mcmgr - Origin: NXP (BSD-3-Clause) +maestro_framework Name: Maestro Audio Framework + Version: 1.7.0 + Outgoing License: LA_OPT_NXP_Software_License.txt + v45 May 2023- Additional Distribution License + granted, license in Section 2.3 applies + License File: LA_OPT_NXP_Software_License.txt + Format: Source + Description: Maestro MCU Audio Framework + Location: middleware/maestro + Origin: NXP (Proprietary) Flac (BSD 3-clause) Ogg + (BSD 3-clause) Opus (BSD 3-clause) Opusfile (BSD + 3-clause) + Url: https://github.com/xiph/flac + https://github.com/xiph/ogg + https://github.com/xiph/opus + https://github.com/xiph/opusfile multicore Name: Multicore SDK - Version: 2.14.0 + Version: 2.15.0 Outgoing License: BSD-3-Clause License File: COPYING-BSD-3 Format: source code @@ -225,20 +147,8 @@ multicore Name: Multicore SDK Location: middleware/multicore Origin: NXP (BSD-3-Clause) -multicore_rpmsg_lite Name: RPMsg-Lite - Version: 5.1.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: Open Asymmetric Multi Processing - (OpenAMP) framework project - Location: middleware/multicore/rpmsg_lite - Origin: Mentor Graphics Corporation & community - contributors - Url: https://github.com/NXPmicro/rpmsg-lite - multicore_erpc Name: eRPC - Version: 1.11.0 + Version: 1.12.0 Outgoing License: BSD-3-Clause License File: middleware/multicore/erpc/LICENSE Format: source code @@ -290,98 +200,6 @@ arser Version: NA http://www.bradapp.com/ftp/src/libs/C++/Options.ht ml -mbedtls Name: Mbed TLS - Version: 2.28.3 - Outgoing License: Apache-2.0 - License File: middleware/mbedtls/LICENSE - Format: source code - Description: Cryptographic and SSL/TLS Library - Location: middleware/mbedtls - Origin: ARM(Apache-2.0) - - https://github.com/Mbed-TLS/mbedtls/releases/tag/v - 2.28.3 - -sdmmc Name: SD MMC SDIO Card middleware - Version: 2.2.7 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: A software component support SD card, - eMMC card, SDIO card. - Location: middleware/sdmmc - Origin: NXP (BSD-3-Clause) - -sdmmc_sdspi Name: SD Card middleware - Version: 2.1.4 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: A software component support access - SD card through spi. - Location: middleware/sdmmc/sdspi - Origin: NXP (BSD-3-Clause) - -usb Name: USB - Version: 2.9.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: NXP USB stack. This is a version of - the USB stack that has been integrated with the - MCUXpresso SDK. - Location: middleware/usb - Origin: NXP (BSD-3-Clause) - -vit Name: VIT_v4.8.1 - Version: 4.8.1 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: Voice Intelligent Technology library - Location: middleware/vit - Origin: NXP (Proprietary) - -voice_seeker Name: VoiceSeeker (no AEC) - Version: 0.6.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: VoiceSeeker is a multi-microphone - voice control audio front-end signal processing - solution. Acoustic Echo Cancellation (AEC) is not - enabled in this free version. - Location: middleware/voice_seeker - Origin: NXP (Proprietary) ARM (Apache-2.0) - Url: - https://www.nxp.com/design/software/embedded-softw - are/voiceseeker-audio-front-end:VOICESEEKER - https://github.com/ARM-software/CMSIS_5 - -VoiceSeeker_dsp Name: VoiceSeeker (no AEC) - Version: 0.6.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: Precompiled libraries, header files, - example application - Description: VoiceSeeker is a multi-microphone - voice control audio front-end signal processing - solution. Acoustic Echo Cancellation (AEC) is not - enabled in this free version. - Location: middleware/voice_seeker - Origin: NXP (Proprietary) Cadence Design Systems - (Proprietary) - Url: - https://www.nxp.com/design/software/embedded-softw - are/voiceseeker-audio-front-end:VOICESEEKER - osa Name: OSA Version: 1.0.0 Outgoing License: BSD-3-Clause @@ -403,312 +221,6 @@ wifi_tx_pwr_limits Name: Wi-Fi module Tx power limits Origin: Murata Manufacturing Co., Ltd. (BSD-3-Clause) -edgefast_bluetooth Name: EdgeFast Protocol Abstraction Layer - Version: 0.1.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, header files - Description: EdgeFast Bluetooth PAL - Location: middleware/edgefast_bluetooth - Origin: NXP (BSD-3-Clause) Zephyr BT/BLE Host - stack (Apache-2.0) - - https://github.com/zephyrproject-rtos/zephyr/tree/ - v2.6-branch/subsys/bluetooth - -eiq_tensorflow_lite Name: TensorFlow Lite for Microcontrollers - Version: 23-03-23 (commit 75f5290) - Outgoing License: Apache-2.0 - License File: - middleware/eiq/tensorflow-lite/LICENSE - Format: source code - Description: Software library for running machine - learning models on embedded devices - Location: middleware/eiq/tensorflow-lite - Origin: See middleware/eiq/tensorflow-lite/AUTHORS - Url: https://github.com/tensorflow/tensorflow - -eiq_FFT2D Name: FFT2D - Version: NA - Outgoing License: Public Domain - License File: - middleware/eiq/tensorflow-lite/third_party/fft2d/L - ICENSE - Format: source code - Description: FFT package in C - Location: - middleware/eiq/tensorflow-lite/third_party/fft2d - Origin: Takuya Ooura - Url: - http://www.kurims.kyoto-u.ac.jp/~ooura/fft.html - -eiq_FlatBuffers Name: FlatBuffers - Version: 2.0.6 (commit a66de58) - Outgoing License: Apache-2.0 - License File: - middleware/eiq/tensorflow-lite/third_party/flatbuf - fers/LICENSE.txt - Format: source code - Description: Cross platform serialization library - Location: - middleware/eiq/tensorflow-lite/third_party/flatbuf - fers - Origin: https://google.github.io/flatbuffers - Url: https://github.com/google/flatbuffers - -eiq_gemmlowp Name: gemmlowp - Version: NA (commit 719139c) - Outgoing License: Apache-2.0 - License File: - middleware/eiq/tensorflow-lite/third_party/gemmlow - p/LICENSE - Format: source code - Description: A small self-contained low-precision - GEMM library - Location: - middleware/eiq/tensorflow-lite/third_party/gemmlow - p - Origin: See - middleware/eiq/tensorflow-lite/third_party/gemmlow - p/AUTHORS - Url: https://github.com/google/gemmlowp - -eiq_KissFFT Name: Kiss FFT - Version: 1.3.0 - Outgoing License: BSD-3-Clause - License File: - middleware/eiq/tensorflow-lite/third_party/kissfft - /COPYING - Format: source code - Description: A mixed-radix Fast Fourier Transform - library - Location: - middleware/eiq/tensorflow-lite/third_party/kissfft - Origin: Mark Borgerding - Url: https://github.com/mborgerding/kissfft - -eiq_ruy Name: ruy - Version: NA (commit d371283) - Outgoing License: Apache-2.0 - License File: - middleware/eiq/tensorflow-lite/third_party/ruy/LIC - ENSE - Format: source code - Description: The ruy matrix multiplication library - Location: - middleware/eiq/tensorflow-lite/third_party/ruy - Origin: Google, Inc. - Url: https://github.com/google/ruy - -eiq_tensorflow_lite_micro_cName: CMSIS-NN library -msis_nn Version: 4.1.0 (commit d071e9f) - Outgoing License: Apache-2.0 - License File: - middleware/eiq/tensorflow-lite/third_party/cmsis/L - ICENSE.txt - Format: source code - Description: A neural network kernels library for - Cortex-M cores from ARM - Location: - middleware/eiq/tensorflow-lite/third_party/cmsis - Origin: ARM - Url: https://github.com/ARM-software/CMSIS-NN - -eiq_tensorflow_lite_micro_xName: Cadence HiFi4 Neural Network (NN) Library -tensa_nn Version: 2.9.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023 - Additional distribution license - granted - License in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: A neural network kernels library for - Xtensa cores from Cadence - Location: - middleware/eiq/tensorflow-lite/third_party/xa_nnli - b_hifi4, - middleware/eiq/tensorflow-lite/tensorflow/lite/mic - ro/kernels/xtensa_hifi - Origin: Cadence Design Systems, Inc. (proprietary) - Url: https://github.com/foss-xtensa/nnlib-hifi4 - -Glow_Utils Name: Glow Utils - Version: 1.0.0 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code, header files, python scripts - Description: Utilities and project examples for - Glow NN Compiler. - Location: middleware/eiq/glow - Origin: NXP (BSD-3-Clause) - -DeepviewRT_Library Name: DeepviewRT Library - Version: 2.4.20 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- No distribution permitted, license - in Section 2.2 applies. - License File: LA_OPT_NXP_Software_License.txt - Format: machine learning library and header file - Description: Au-Zone DeepViewRT and ModelRunner - License. - Location: middleware/eiq/deepviewrt/lib - Origin: Au-Zone (proprietary) - Url: https://embeddedml.com - -DeepviewRT_Sample Name: DeepviewRT Sample - Version: 1.0.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional distribution license - granted, license in Section 2.3 applies. - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: Utilities and project examples for - deepviewRT. - Location: middleware/eiq/deepviewrt - Origin: NXP (Proprietary)/Au-Zone (proprietary) - Url: https://embeddedml.com - -mpp Name: Multimedia Processing Pipelines (MPP) - Version: 2.0.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code, header files - Description: Library to build vision pipelines - Location: middleware/eiq/mpp - Origin: NXP - -azure_rtos_threadx Name: Azure RTOS ThreadX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: RTOS kernel for microcontrollers - Location: rtos/azure-rtos/threadx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -azure_rtos_filex Name: Azure RTOS FileX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: file system - Location: rtos/azure-rtos/filex - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -azure_rtos_levelx Name: Azure RTOS LevelX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: NAND and NOR flash wear leveling - facilities for embedded applications - Location: rtos/azure-rtos/levelx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -azure_rtos_netxduo Name: Azure RTOS NetX Duo - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: advanced, industrial-grade TCP/IP - network stack - Location: rtos/azure-rtos/netxduo - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -azure_rtos_guix Name: Azure RTOS GUIX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: advanced, industrial-grade GUI - solution - Location: rtos/azure-rtos/guix - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -azure_rtos_usbx Name: Azure RTOS USBX - Version: 6.2.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: A high-performance USB host and - device embedded stack - Location: rtos/azure-rtos/usbx - Origin: Microsoft - Url: - https://azure.microsoft.com/en-us/services/rtos/ - -issdk Name: ISSDK - Version: 1.7 - Outgoing License: BSD-3-Clause - License File: COPYING-BSD-3 - Format: source code - Description: NXP IoT Sensing SDK. It combines a - set of robust Sensor Drivers and algorithms along - with example applications. - Location: middleware/issdk - Origin: NXP (BSD-3-Clause) - -Pedometer_Library Name: Pedometer Library - Version: 1.0.0 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: binary library - Description: NXP issdk pedometer algorithm library - for Arm Cortex M0+ and M4 processors - Location: - middleware/issdk/algorithms/pedometer/lib - Origin: KEYnetik, Inc - -dsp_audio_streamer_frameworName: dsp_audio_framework -k Version: 3.2 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- Additional Distribution License - granted, license in Section 2.3 applies - License File: LA_OPT_NXP_Software_License.txt - Format: source code - Description: DSP Audio Streamer Framework based on - Xtensa Audio Framework from Cadence Design - Location: middleware/dsp/audio_framework - Origin: Cadence Design Systems, Inc. & NXP - -dsp_nn Name: Cadence HiFi4 Neural Network (NN) Library - Version: 2.4.1 - Outgoing License: LA_OPT_NXP_Software_License.txt - v45 May 2023- No distribution permitted, license - in Section 2.2 applies. - License File: LA_OPT_NXP_Software_License.txt - Format: source code, header files, binary files - Description: DSP Neural Networks Framework based - on Xtensa Neural Networks Library from Cadence - Design - Location: middleware/dsp/nn - Origin: Cadence Design Systems, Inc. & NXP - (proprietary) - segger_rtt Name: SEGGER Real Timer Transfer Version: 7.22 Outgoing License: LA_OPT_NXP_Software_License.txt @@ -720,12 +232,14 @@ segger_rtt Name: SEGGER Real Timer Transfer Location: components/rtt Origin: SEGGER Microcontroller (proprietary) -CRC32-GS Name: CRC32 code +SDK_Examples Name: SDK examples Version: NA - Outgoing License: Public domain - Format: source code - Description: CRC32 code written by Gary S. Brown - Location: - components/codec/tfa9xxx/vas_tfa_drv/tfa_container - _crc32.c - Origin: Gary S. Brown + Outgoing License: BSD-3-Clause + License File: COPYING-BSD-3 + Format: source code, binary, project files, linker + files + Description: SDK out of box examples to show how + to use peripheral drivers and integrate + middleware. + Location: boards// + Origin: NXP (BSD-3-Clause) diff --git a/boards/frdmmcxn236/board.c b/boards/frdmmcxn236/board.c new file mode 100644 index 000000000..237805671 --- /dev/null +++ b/boards/frdmmcxn236/board.c @@ -0,0 +1,181 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER +#include "fsl_lpflexcomm.h" +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ +#include "fsl_spc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* attach 12 MHz clock to FLEXCOMM4 (debug console) */ + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); + CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); + + RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST); + + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER + LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART); +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) +{ + lpi2c_master_config_t lpi2cConfig = {0}; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); +} + +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Read; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize); +} + +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t status; + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = NULL; + xfer.dataSize = 0; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + + if (kStatus_Success == status) + { + xfer.subaddressSize = 0; + xfer.direction = kLPI2C_Read; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + } + + return status; +} + +void BOARD_Codec_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); +} + +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); +} + +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* Update Active mode voltage for OverDrive mode. */ +void BOARD_PowerMode_OD(void) +{ + spc_active_mode_dcdc_option_t opt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); + + spc_sram_voltage_config_t cfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &cfg); +} diff --git a/boards/frdmmcxn236/board.h b/boards/frdmmcxn236/board.h new file mode 100644 index 000000000..bbe9874ae --- /dev/null +++ b/boards/frdmmcxn236/board.h @@ -0,0 +1,179 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "FRDM-MCXN236" + +/*! @brief The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART4 +#define BOARD_DEBUG_UART_INSTANCE 4U +#define BOARD_DEBUG_UART_CLK_FREQ 12000000U +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4 +#define BOARD_DEBUG_UART_RST kFC4_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC kCLOCK_FlexComm4 +#define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM4_IRQHandler +#define BOARD_UART_IRQ LP_FLEXCOMM4_IRQn + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#endif + +#define BOARD_CODEC_I2C_BASEADDR LPI2C2 +#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000 +#define BOARD_CODEC_I2C_INSTANCE 2 + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO4 +#endif +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 18U +#endif + +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO4 +#endif +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 17U +#endif + +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO4 +#endif +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 19U +#endif + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO0 +#endif +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 20U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW2_IRQ GPIO00_IRQn +#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO0 +#endif +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 6U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ GPIO00_IRQn +#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED_RED_INIT(output) \ + GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ + BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ +#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ +#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ +#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ + +#define LED_BLUE_INIT(output) \ + GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ + BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ +#define LED_BLUE_ON() GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ +#define LED_BLUE_OFF() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ +#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ + BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ +#define LED_GREEN_ON() GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ +#define LED_GREEN_OFF() GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ +#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ + + +/* ERPC LPSPI configuration */ +#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1) +#define ERPC_BOARD_LPSPI_BASEADDR LPSPI3 +#define ERPC_BOARD_LPSPI_BAUDRATE 500000U +#define ERPC_BOARD_LPSPI_CLKSRC kCLOCK_Flexcomm3 +#define ERPC_BOARD_LPSPI_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(1) +#define ERPC_BOARD_LPSPI_INT_GPIO GPIO0 +#define ERPC_BOARD_LPSPI_INT_PIN 16U +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ PIN_INT0_IRQn +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER PIN_INT0_IRQHandler + +/* ERPC LPI2C configuration */ +#define ERPC_BOARD_LPI2C_BASEADDR LPI2C0_BASE +#define ERPC_BOARD_LPI2C_BAUDRATE 100000U +#define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm0 +#define ERPC_BOARD_LPI2C_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(2) +#define ERPC_BOARD_LPI2C_INT_GPIO GPIO1 +#define ERPC_BOARD_LPI2C_INT_PIN 0U +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ PIN_INT1_IRQn +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz); +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); +void BOARD_Codec_I2C_Init(void); +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +void BOARD_PowerMode_OD(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/frdmmcxn236/clock_config.c b/boards/frdmmcxn236/clock_config.c new file mode 100644 index 000000000..97c812891 --- /dev/null +++ b/boards/frdmmcxn236/clock_config.c @@ -0,0 +1,448 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v12.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.3 +board: FRDM-MCXN236 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 12000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + /*!< Set up clock selectors */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 48000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF144M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 144 MHz} +- {id: MAIN_clock.outFreq, value: 144 MHz} +- {id: Slow_clock.outFreq, value: 36 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: RunPowerMode, value: OD} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.FIRC.outFreq, value: 144 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF144M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 144000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 150 MHz} +- {id: PLL0_CLK_clock.outFreq, value: 150 MHz} +- {id: Slow_clock.outFreq, value: 37.5 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: RunPowerMode, value: OD} +- {id: SCGMode, value: PLL0} +- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true} +- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M} +- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CLK_IN_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 100 MHz} +- {id: PLL1_CLK_clock.outFreq, value: 100 MHz} +- {id: Slow_clock.outFreq, value: 25 MHz} +- {id: System_clock.outFreq, value: 100 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: RunPowerMode, value: SD} +- {id: SCGMode, value: PLL1} +- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true} +- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true} +- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SCG_SOSCCSR_ERFES_SEL, value: CryOsc} +- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.1 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_NormalVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.1 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.1V voltage level and 100000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the 1.1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P1V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupExtClocking(24000000U); + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + /*!< Set up PLL1 */ + const pll_setup_t pll1Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U), + .pllndiv = SCG_SPLLNDIV_NDIV(6U), + .pllpdiv = SCG_SPLLPDIV_PDIV(2U), + .pllmdiv = SCG_SPLLMDIV_MDIV(100U), + .pllRate = 100000000U + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +} + diff --git a/boards/frdmmcxn236/clock_config.h b/boards/frdmmcxn236/clock_config.h new file mode 100644 index 000000000..eb259a85c --- /dev/null +++ b/boards/frdmmcxn236/clock_config.h @@ -0,0 +1,177 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ +#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ +#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF144M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ +#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ +#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/boards/frdmmcxn236/frdmmcxn236.png b/boards/frdmmcxn236/frdmmcxn236.png new file mode 100644 index 0000000000000000000000000000000000000000..8a7eb3cdfbd047e2c9939eb5168efe64f0b81ef6 GIT binary patch literal 52000 zcmXt9XEnKqNqeKg$6Ls|7qK)2r7rl4U8J!>qqIaTqgV9S6o#?$q`{w=e z{kU`QkNZ6H+;jHXd+oK>j#gEc!NwrNKte*omXigmBkse9%LMHW;x|R%qy=$9cb3(4 zLqfvo|L=O0#)3nRgakyA1B+{V{XY8jrNO|;`{W_pV|)&FV$fcu@Q3+xJxCvl*%YnB zVH`t~%E3eR1bOJL2gQ*t_l6@y@@!Z|Z&#eHIlGhC@p&BS*g1>#?U`vazyxX0}bG zDYEgATnw~X<@+ncNb2e=^vt=u38GP!?1{CK)XcHRPt6YJm7)q|TOqw16n-MqP#aZt zawKlYP$FoJ;eCsf^6jFbQPjPMJnzC54ccopre0tzJ`}KBNaN zQ!z%BKc@VL4pf|jw7Tv+y?!M6hM!Q>X%{ z^Y*4@As?y?mRWGHuxyh-BO9`^f7-41>OaDCJW+>SmOA|zr3XxHIF*Wj)|V9JHQf+T z!0Ra6U?896zC7j7VJv(=S9zcT?` zW$VD)pZj_r33k*`)h;x;N}~5i&_^vOmm{*W_^FUH6`}ULGTg~Pyu^1@?@R>J`Y*w| zd+9X}k=W#X^#QAICUTD%^Vv2qQCm)aOO8#9sj~k@K@Mng>_}Dx^JQO77{kiqK@2&U6`QBt4Ml$eXSKmn*N*@t9 zh)@5w-IS%$!NHtMYIKLd;rRH<-SZ=tFb0}+)+m%MJ6gIZN8pKU$v)3vxp{JaUYz|F z1#uYK{^?0<;N|Jlrj6poN&hHQn4DXM#eT>GW-HY@JP;G`xYXTaXr#E^`7uXUi+%-0 zE2_W?%efY)I?0Aym`GSH_n?TcBEQCtOI6^V`RIo7NapYFzaBkC=}Qzi35T-q62ySt z6SG-bSuK5;!yzLl<5v@aZ_l!}dpgkJp#j_81LSD)4NQG}P{&V;3bR|PzFLv%ltlkz z1~9*|6Cy~huLp0rK-FnW=!S>l-?D+n^ynlQDNbOhXu{wYJa#zoozq+8g zCc&FM$i*5nK${j5?2z3;1z@o_A9rdGZS$g4WhEYnpJ!kw-;7Q335JYF8?YKtU zmkd9uCx^bhy*#L3%*@vxth29by}@G}_s9{MOR&k}uNsTb#a2{So(bF_sKV?z&vv3A zyKs4K#N2kJ_dH&eauW_Y^d7F0;3t(n15hk8kfH%&kn{G`%QJ=pMAwtyBuv`wSTHb@ z-hQUrt((Ka^c=583@@L-jBHLouuU+7Dqk88Rd}JOv^4wXhPQBvqZJbTZ`ZQ$oM~K% zjdkq9mN#+?ZHjX7(l3+O_v(4O5z>l9A)siaep5C38nR5DYC(tXAh0kRpbIn>(yP+d&FXi~u~kbFhZp2g--1 zjF%*VP?3gQM)okg40)u6>-^pU4^K`5ZpZ*kRECnh z#p`A2&CO!DJl~7b#dvgNcaPa5J-K@RY;z}w`Pw{jo+p^Yq2=ASiOh#jPn5C)dMu6R&SyqDubhnI@r( z6oV8L4W*FhMzj92rEZ@Dt5A23-cT)tblIkWUp(eQtDir8g)-x3{VdTA4 zz*M-p`boEqi-#$bnWu-MMxQc*7ahilop68e9TJSx*ocnY1HAXcUv@cT!6-1sTc`}s zCi)YFW_o?8r7I2v{T3o~c1Q?@ykWx=<6{O!Yr2PuafHdBDrwa^ki##_ZS<~^#);4F zzr!wBl4A5^)?2cbCj$#xW@u@NuhQkD0py?;f8W0Gzwg+)9s0xm7U#s z+3|&oM?lU^;dObr^LjUxI*VLZ7CEP4N__lhAKx|?$Xi(5Sq1Z39Ej8}hQW(of>ucM zu~3y500nCX39Oez_M=)fj49^MPrR+YsDI1k@foRX4C6A^?P#f;a^X@(2U4iYG}G)r zXIIA-q)@B6Ug_k`;^e*Hbgm*wCWbK#nM>OI&~-s?>Ot=OYRI#83?mH^ZHKek9s7Z5 zXJr!On34$R=wLJ4Eajr(_W3X}IN>Rha=Yq7fNA>HqVH%Lg+hHO#ma%%?<~pKYhxx8 zb8%Rq?T_*ZizWW5$ilmGy8z8`72foLYhh+-RNZqm<}_VB zL+R?&bDIFo{5Q!#7J~hD1Ue;gL6L_oC{N;kF%dSTI!%2QA96NIvK_^=EO4k+;;IgZ zW8SpbFV(&3T2pELNr?4k|9HQoy`7|Qc8Z%CTHtoPQNf9wA`AMu#ecNakqvgh=HY2H zpMFn9X6t=f$wwFs#zz^pzL8gwYGq} zHFYhRZ9_GxxpRvlW`LsV*mRi+5l+)9vr$`mU^-6aUtI7sZATd>sxVv<@Xcvi&`%^S zElu$8RowMqd$hD97A}q&`ysdpzpWj`euySzga8d?vGW)sCLHT2{U7>U|1df=^)gUF zjXZC5NqcFwX(w2|K}RpIw5%)>tdwK!imuR{xQ*7>h>fT>DazH~$Ss;q7YDZ&QFdHk z$t6b(7A`{j)Lk?EL}cvj$O8g{miBER3sTASRf0A7n0pVpy1LS5Kmv?Sew;qZzV+6h zYc0WTZPL<=Q0x6aD0woA8OATqueVuVy-`rGmJV_ikm=N1zk_|KwSnnT-HqVEU{tHw zyrDo2o?P2Ul{w%}%pa;rz;S;x;gRkKmw&TNDikWO>W|u7=~fS$Kk|wwX;=v@7`O$! zj`XZMJbRFx$OHRKA){yg&MI@T@4dE%rq9eS@Tu$TM@B|kyhEV8s+Ep7d*-3(Uak;O zji&={gh^pKHmj8R>TmYVT8=g~OIOq68=m9-!%YAt{q7#r+QD{!*C6Xas&ERACt8o! z=}%adHeR9}Lkf!It1L1CrkI3{V0;t`L^1C%4)SAHDbqB!H_y3efz~Rf1P3d$G|4#l zWAj8eD#oi2V1=vtF^AMd3>2ect@gSq`uO-n_nSd}O(v*K*;qRkR@A5LY!gJ7)YR~+ zC}?0V*+Wfh!60>Pc1p_JoKL>Q&f<7wWtA4TJ|XUcaV7VE4cehf6nRfZ{jV<$PVt$6Q~&S6{_cDvA?Q} zxo+Q+;Gwh}bc+;jput6+Xcbr#+})cdm)rAdr`{X#yXH9acmMHkf5q>6Bb;aDcFpsU zWS+E<75C{uuSKS^_oF*k- z%yo$w`(6E=Ybz_sM81`~`PYFokcY?h-?oXnMQ%Dex}Ul;6B7o@IyyS$&dz9TsutSi znUzt@Fh%7tPF|64CYydUPRl*wR(G4I%zXjj1*rwLiM&rLFZbdADf;|z4q@)WvtblO z-4hR*N|G}a3QUT9dMz6hvW^ZpqTalNmC9PVl1B6t$A;#7no(iMWuS`V5^e9d+hcdR z*tXkt6*xFBvp-!PGY%9T86cufVv1)|XV2#5=9yVp`O0de$;{AW95sK#yLpb%=4g_M zLq1E;0cqUX=@XFb@uSOp{c3xo*OwB4T;Tx4H&|RmOA<-4_NECs%L9w zr+q9zM~0(O^%t!o>RV?C@j|0XTD%8@Ln&0gIBHKINX$VAdAxe#vJ44a#0k;`kzxe{ z3F3yB(mfvakQT1-@XpVMEoT-r3uLAE)TGe!e{Op5#v`>E_LjTAtn*lGh4&9tjV)21l1!+>54(Yv!BlLxV%* zrEVuRv9-@KD5#5^9;lieZ6z0AIs6_mN{4#Z2di<6(bhDg*;F~M@6O+;hkUKDe?6^(N41z2uk zN@uaoim=e~evk!$xsQfUZ_RXxV@fuVd&HvrXd>YxVl#f=qI26Yd~+-V87L7zZm|1% zNmH;GP>h50yCyS!?0jLFh+n|*#qWq-6ObGN=VHCq%+L1|iB!3)ByJP|>kd|_myuVKlgxsr+kI`rrLywoR<9!5vdp}Y=ISCDgTc~)(t>XV+~=2qG+$*z*T z_C`Ubk)TQATl1l8wa-)KkY!FYy^UvUS?2vlPHfR3%e}jo_1YKT93Ostck(4L$b!h( zJywxH3jQ10-QDwYnfe8k|58mo5E)dQmCC|En8JblzxsW@gxI4%m0EU%9qoRoTrfG`|x@&sPy& zfVo#6N>pcfLE}wGe;O=An=B63DYin8)r_~G9(Qv{Nr{NaTC8y)%!EL7xWE4V(a_jz zyo^(>LQjEJU&EnfAgt)-h6zQw@l8WKY>traiMnrxVq*xVXgy}p) z*(JxEJJ{rKF~Isz{RcHKZci>pz!#eJ8zr)872dxMGBY#7f{=mvuuy~}KH#|QZtu_i zlN$6uVK<}@o6~eg?cSK~2EwTYV)jDTgKOm>QH4RQWfY(OF^8K{eZD;r6+!`n(IIa^ zx)N$2F^OdJ(H)G!zu#;Egi%oN=Wji01Ge-)Y9>2J6W+A@&bs7jM^afCDg}H?XziI-V}?E=Vn|gp?bCxNEjn!}JV%O{ zUeLGQ=4b3j9?oz_p{V49j`k{JQ`4B89U_V$6D4gv%i`|GO|E37Z}+cf=lgYZ4aNB! z6lY3`%i>MTz=F90gebNIYQk_cd-ohwj;|nCm;~8~`I{k^_vtL)UK&j)P;O;O;7lDN zMPT7z%}g#1PjAv9YsGMrq8XDhK)1dP6BIHbs2LG0@nlpAT;YWQHwv)s8+>!Ms_ANE zrn(Ryx@-sn`nTl8mfXLG#$>c9g9rv(S^bhjKrE^9Qjft%F@*?Vz1V6-o`1KRa9Q=` zi8y303AXdX*IGR(Fx)YO>`Nm%wAKW^?rDl{Z>;BMH~+g1s6_OZr33HcC_wm&2I@3saI;6NWreH zs>MZpCMe?HoE{uSo`tBlM;P-4_b{Cgwxtei>2kb}xdX7dJxu@>Ew2QXn9jLsTesi~omh8UZiXmdC-v%Ma7_ zX3cB1X74N-Vij}VPaepC~9IjixYbwu^WpSCk&oKj_girrI0#NY4_Cw%gP>e-xpV0hS zyiiul{c-cfY=ZLH!i#ejq1D93Wjma8%+k@PXnR{*;%7tz!&wQQ6uQ(oO$${BlW`V< z(zVjBm)F#rJwsHMYgGoqck7{Hc0TB_7~V6e0%EQLp`o!xfU@lv?uIYGC}a_(BArp1 zDB8NszDqG^1-=YmU@l5Mj$Lc$2eZ}e990-dj$fH)nlvInVDwR#3_ZPQ^21Qb0pz7* zEtClZ4SD<0TkyBg-~EH_`@ICniFZ`RAOjk0db`ylq={Cwk`WIDERKXvF(jE>9?qco z5u3e56I1$+abQ)u4;#k1cY54MBleoh(c?P+wtu75W@lBpc$n6Zb1t8t({*%}nUUd; z5d`(LE``71RyRHx7zC6Liew#*62X_l!?$>+22k^7u4ARcKu%_&k>`pxE3hR)V8Kzu z6CKRZBhb0l-Ol3!7^^76hD-i-j%4mxFZXMPa zaPoYxrpmhOeRa<0{WodI+O}MZ4?CXHKhrADn@ablpo~iv0~u%Y;Ljb1NqgFU*$t^C zx?gfQS%!na^l;F_?)fU=RPXiI=OJsuB0vqLq=UU~DAUN-I4m_zR*>#GblK6;(FJ{q z$c5uag_A`e^ji4g4mo~jaR4DLMA5MD28_K%6|Fg z13#J=ZPGXOvdP)m{+d2azjHs9>5ZVu0qR%?e0VvDAv$v1GJWqI7m%o*kz8x=}TACX{kkBzd zH(PPy_cpzamx#k5uZFI>Jw~?c)_pRd*O=YAB*>w_Z$E6cCK;=HWxDjzoT7|%ah}D3 zVAyQw<*wZ>lOB}tOXp*CqRzjFjTyM4uy40rFR@TFGD{EUHHfBQ~~()HA}FDdOjEuR4XYM002B zuz&w7)ib4Tj68TU)4X^0NJz;>J6`=kbK)=!)?tljiUDAF+b>H4P$*!uWO1}HTEoTU zZ&+AZT7oPxw=Yqd(?&mx-NUS90Rt~Ph$Lg3HCUpQ&F^!?L`aw-eDk-ypB6tWiws{X z{5h87o{w9hy1v6Kmh2SAlL7R!v)_SO=+8R>PMuo43ls-3!I7CB!5PY^tWoqsU5T z>gpG!Xo=d#orH=${y}|MPE%gsfPAx|d9J1=(cHu_GycXBIrtmohxv;cE0ie;!48WU z0b4obocge4=yXrKZUgc}nuh6cMY;!-veCjrR=ifld7U5%t|l=Lfma+XnDy?bzvTtn z`#;^Tj6eLjeKqfXi}!V|-XA`|`Y?YkMqJrtKG{!IocT$S;_S*Ow;CyqA}k70qbhHQxKh zNa$AAG^CbqZZDYRFwuTK$17Czz>`bnP$Gou`+q|c@5-;M(r(lUiE_~EB8$aDJ~{Ax zczR_h;1be#ylib_XJP6`AoY2Y#ljsXac;vOFEvRGB#mCrAZ|Lu!$L*B>pNOm8X6vE zYL&q6T1zlWE32+7Dr*cSWK=6Jo2 z*7h$(BmLX_#S-zxEzs6*ROz>dTeqSQ4-L)DmtSuEFxf~=m9$Cfm}oHw($t|R*V%W! zwNFjluV`OM_0_Nfv=|Hthc1P=mFV(eTpZ5$fgE5afL{2-gzfk?5Q8g(i6CK!|4U~+ zOYSGY#XH&p;B}*m>%K1Y4sEM_yn3yKf&VATzEHoLt{42S+sp(y9h`C|8d+KbO!1nfaR!RY_y1wXCsiZ9dFtTm!DrrmeC}6twHN8e=>7!s%{%6GhC&?m3}xy5D2zdrA;&|pt>*{V)$Nzow(LMc4^65Q%fq@ z90N5s#-0w7s=%1YF)I1%9y+2oG}Ggck98zNp+i);Hw*;PiLf0G?9hmaH+A>I@rOV; z+A0=2jEKocve;PIT&K7jCL#dGOVzYB`nInC2qI#Zcb1b=WW@jWnXv1@H-EPz8%KjR zb*a;V#p(mZ*xWpMsm!Ly{;;T`A{%q>LrqnCtTnAPyS7Bq`lvzsJId_t(tDkZOa?&0 z%;I!^<9Qz-mOe|LOm22gZ9ykNl&r9+40VaR#8-*DWG@j8nDTfn6`PV}WV#AvzoGt> z)w;j>J(k#tS|G$x`>sDyv~NiCxfWKu6yJ$$|GO!>x#KB!=ISggAgHNn~?E0 zg<1&R(WxPCFikmU*t5s(c@M`Rd(9ER3Dq<+Dcf(R|15<%k^($Jb^76Bi=dFd$)jUj z0*$hEb{}C1u^A=eoKCcK>$s?#*n}h`Qx)?@xQreD_X1?(VK#cWunv_6WdEd#p?x++ z(%^faOq4(^M1_2nANn`Yih{qz;<$gi*LN%Wv)aO^-Or<}3?F~F7s@KF>QQ;0sezX) zJY6Foo|$mJiz0~sHO*tzIE&T4{e#th*Ahjm*j`E}(J|`PYa(6;JsDauvzfu`qouj= zFJ1TebyDHROwv|g_@cq75rcZ>a>Z`rKHzV)t?$G?FV+NnG&Ae_ilu}fg);dVKz5ML z;SdWh#1X$rMEUR37BUUjg@DSeE85tklGL=Qi(TJ!5q~Q(!!B`1n)vSWDd9`!ga2aF zL|dc7iXTkLerX!Ect?RCHumI#f)Jj789y)NyVqn{qRyFl0D9B~4>j|5D8X$JZ&+c{ zsUV7>KI-_hR(N1=Bl-OFLUUX}kNEF)L6=XsYDqsTs!KJiYRqmOaUlMQGSohaJO-Z- zIXt4n_cj@3x#T-1BG}$0;Bmvsb50g;D0#{Vh{4B*0zIuy-{LIXAEEts>);^kb z@~0z3hxMzC-f(%0iq_vFdpbixnJeSVl9N3upR3`!YLCQ2$CXY`ck}zzk+i}V&to5U z!%^3L_2|+(|L~2C*oLOY%ing4Hv08>JgehZp1d6V{M}14rHgeIbOnX{OEG`N`JF1GiB-t99!_O1>La=(cFzl`9*((Nyp)v>S z{zl4!tb~HNtvht}CrITaKod%!!?wnW+mHS79QhMM$_& zjEl9$dQ}~cqI6ptOs+w#BU?Jf?_$CQ@&Ybg%#Cs+*d^Ih%*?IH>bO$ z5b_^vMnyOngkBM2hc2atXv8 zM~JXmb`+ZYD5URqJL;u$UNa_FbrW%XzoMxFPK~_oHcDH$ zxx3}d#q9JyOv%2@Tj_6I7<@-T*?Wqs&P+UP;pWB9%4XI2Z#|oo>fN`*4+v92)6Tc- z#26f+<$jf*zd)E#nbKWKpkxV zqt#-)8{IXw5_c01mk4iTIXd#P=a0%tQ)>ghK;<88RE4bHw6Es23be9x0Vt4#K2HjS z9<0O`ceEUsc=G33QAOGL1vj9(Ha-3#_tY;E3{uo^!~8fiV-M*{a{gJ4R#lD2U_XsB zaacwG71RhS00?)^opfW<#OMVOk6m z*JZMuKr7|^@114XDw<5`7Yz*_(<{HlxQV6l>6xM9;g}@%^J{^GMVjK!o%{uoitVUE z%|ivq+Xs*0Fca6)u1CyrQ3=j`scSnx9ntd@rtjh}-cjnO1Qjl4lf<4WC()*2w>hnLujlc9DEsIRN_IYlP@mSK@}<*ywU`&$YF+ zg`o6p?Y6#R262#hxzJSLokui9RcxJa#LA=>!-CVPo_PU^7HG ziuAQ=FnV8%Fp^T_eK-FN354l$Qex^>76lroo<7~7Q5xhPt+b{?*kx)pd#}OJbnP0p zY`!&5p}mP5AX$ZprDeQdLC_XPMtpztmde!9)cE!l^0A$s_o?rnzK*r_bcAo`G+?vO zeCC~H2}A4ddcf}PuJ_5kRSiYt0{d0H*^uM!g@*s|CSiVw%K~*^CT8Ddi)-THpDSf( z`e(1B%oNsb&3}xFo!1Gs$%^Se><;KNN7bq_v|6^ky;>R?8tRfEWy$J!G9ZEiGbKWV zb;q9JOXiI`#oHNf^t;eS%f@B|9uU#m+AqyB_3=xkgMS*zJ$+yc_}Bd!Vbdcfflm5~ z92}7I|C?4r;6J(2WOMcR2Zsb<5^B$rC@PzNS>LW&q#(&7#Gf|6ge-xIUes!`x*J({sP-A0hF9Ba=RudklkF)O{ zQ37pzJYf`-Z)u8de%w`h95;Ft$iKfT<@easnr3-V6|ipde3QKfOdCB5edts&gP85* zg$m!_ZK1rTIb${Sz6R9lkis~ab}n*6zd%QlOr+niUpzf@B5W!J?WKej5YxZvqDpZH zbmfCuAM2*+p6kax{YSKKD_s_-<0PsbmYP{IpUwCW7`h#AS1)b&LzUfRqPtx zNhu^-qV9fE#Yh~-AtaZk%E~5VB8EX)ywK&6TXxSHg)gr@`rY6@vy_+sqcN7h z*zXNr!fQPaiGJOFI+Y+mb!|2+?9&I_g+7c}e*ATD zfG*fRZ=zj-Wc}p~e`K}R`82zLr~y0!>&4+Q;=M`K6=&R^wbpC!2y{hL0*>;fQ65BXXEJj9m1LjQ8b)H99BEZ?fGS#CTy(n zF2?M+f!YmJGF!7>UgqHnbeMmu5*+mBH5MkvnsW931|AEe@iy|XkxD0>`aLXT;l{Z< z_A4ORwJpVXtjiQ?(P4Sl=)n>nKM_$kHw8tNueD|ij`KI%iON=qV0>})sD3j|tjy(r zErx)Xnf%S2^aM_BuAaOOA!|FkLY*q-wcD;f{}&(8wSV(`a$wfZyL+MgiuO|z1CP4(gQjLh7DMmG6kg8Gj$6{cMjub=ivNn65HG<4?pXl&5(TQJCKlld zfk$SL+Kz;c9)+>-55_{gqL2Ft_ZR6eIbhm}xd+@Dy9G}iO2IL+1d*}5=jFhy>XXjw zq*@c+shYN5Fjn^SAC(t4qqo5Fo)UUTs-*w404_P>%x1 zdt$Di`pbj6O5{_RQm&cr){H4TNSYq%LAcPUG(t(~-^BwiOl9Hx)MM0UDUW~(kt`tHS1khvr*g?)Ku9y!JU-o=X zI!=Ap$yT1{o2RCKPwZ<{C&G!|Z^sB<%|treC*(hFzY6%bPWQ{*FJoIhLW!Jjv!FhQ z)tH|kDKUYi$)QxUEYZ-gpN06tZBNk@Q^#Q&DHWM`k{?QlnxOBz%fGZO#e{@jl zq7-bqh0CqCRNqa>K!r4{F!+^?B3s+Qg~f!L2O&#Kj$Yei;YAerx_}gC(o+l3rr^&FLk-d-h%XQ(`hd!-` zRifJ}&)cxYG}=pzkM@6lAuLO5Bj(AOneU#@E(5#MpSKf|w5XSxjCzU^K7}0$JofB~ z!pdf>qKD`ZPT|YA>QzanQ@s)^tH0KEjQQ{aCg#_nB#02Sgb`_f8>O|H=#q?? zcZ^+)ao6fZNk-z-|H|22tSv%`~qQg zgiFqa#pv2)c`}h4U}OiDBjTF}rXBkiclaZfb#TxsN=m}ry?IkWs>G@y&R!r_x8)(T zl*;BoTZl}%vU&ijbu zl$C$kr<-Mr0g7L~F!JztY+taLPt%)g(Gj4Blx{AV56V2)SljA5*+|(cv>Z`ilzbIS)9?8cO$@ul&?GSR zt^bROW6K6dWhKp^l>$@D*hmUvv^1TL530%a&-N{TL>pyULOcaykk=gGVBVgVDdo~ig-~IZAR)qQS$|EL zm8{PLqDPi>*Vleh_@z&pD&VdZ;VYrjfyV9mxPQ4;Wrg0YSiO*EF<;gX<(WIc-*kH3 zF5DHt{evt0^*LaIA+(5YPp93JjYUD>yS92%T@aIe4!=vXTXn95t10qAV`fg)Rv-00 zy!_|>(?s|#f}#cHv(?lkmp>!So}_B2`D+K4zh^2HR^5`3g#Uy@(13{+qe8RUAP7x2+>fS9Z2My z5pocPuPwHP5VOllUux6S;KLf$(99)J{YSHmCW*3){`v~V z#5HQM{=U+GvXwv20y%H;Ow`kCmQQpAN+$$fDWxRkeEjjP5NJA)u{HLCaQ4ffOR^cU zRIa!bDko+PP(YHfZC`8;LRl`T>9JGuxw0`3ur+pM7I^x6;6#}guLt)z+3T!6{M8Re zeow>2zb)z1IQ>Uttntw4TTy%FZY;@PYbVK49xje;dH_B?7*#SD1tTqQ7C@J-l-GL$ zZ+6-A5^$l3_|Z`3HRZ0z@LE?ufO~%4m^&M>#-4x5+c2#Z3^CiT#w&iN&sgL*YKg&8; zo^DfYP17(slp{ZW~!Wtg7ZWN@QLi?rcy4a8*K`Wfs@ew8(snd}8;!*D*v~~E0+mf? zgl{Z!|6PVXF_=@jn_LXA`RnoG@asE1#H5U#1dXU}IQ`#oUS0>E{6Ei*CoR{~riEd0 zrIJMpE|*G&YD@%ZF3~1%yj)6$k<)K;G%?6zmC!Iy!PI_KcpsS7q(P7}1V|7&m`q9C z7&H47OA`b2b*SVI9x{SLMUHjJY6Y_zxYA}aSQLPP7mIHHSUi$6b&T0YE#H z6A(Oc@$^Th3Hvr*U)4eeJe(x$#Bt-U$dw#cuDbgDc2MKU__%cSLUL}}2%*YYNd?{e zr_+NY%k$}bl-DMjwx|WFQ9+{J*9%5cAcCUO_H0KhKHm1|Vg-`TbFZ?>N;-mQF7Hh+ z0eWZmMJJ-z2q%9AkcDk&0t9_Lwl#)UX3!(X~-+t~xr`TyPtk(#A4i4aQ!^mj% z!p`RHP-MlEiAxT{vYPmOwsezVZSDB&$2YvniLqL`j;OjYCJedNboF~TK7~XJF;g!u z(qf5-u&_@9!5Mh_hi)l}V8y{e7S35yiO(=sz;}L(@MIlO%x9GaLQ^~%1|SB3 zj~T(Mci0cLdhYzof}~ey06=L6Zs(wgUpoh#g%B+~}x<8svR7T+)730-t^CVfkP z5N@8-)UW3E(`i^&xG5&hHHc}S$4(B0`ZR1@`)`kr0+x!ovB?}T5@m_pzgCCPTc-E9 zNDb4cC#K`q=_x7s;X`{n|Fj0aVV!R(tZC@G1=m{8sWQzW0#@xkc33Y>Zx2ms3_oIP zNw$D2UPmL0i}k*^DGW**DuIum3YjMNT(=zT!NFgpi|KjTa#I^Ld&Q}le|{y?l@AD@ zsdY}gxv_Muud^vHldk?)&2&b)J>k(*L_p@Iab^WNKcoGpmnjN z>C|YHxyk6rVhONNYnP7reN*bvHwz^SH}K?9zZaKI9Ut{OHc$PYm;UTY?DJkOaQ1)z zKt$xSWRX% zMwn^IdiIYBOUiexmd{?+==PWJ1M|L+#!2^XoWbFC+1p*0 zZf}Agv#fe8Xt4vM>+2kS!9d+iPhxh+*Cp%k?G=O-s}pyy-P(WUb}pV@YMuAzGREJd zapI@x-PfDyLoHCmf$V7Mzt0FJstm_0UpEox6KF1c3X-Nz$V8vUQAr^)1 z-r%u$9%Fs&17Ie-L5Y%#iZt%~qa@s`a~B!bt@DGz#RQli8Wp)EK%$*ZAw{IjQQOmzs+884^HO@!3FXe-Y-~ zYH%0P;n(TUB6{*?+$ryY(COFH`-usW&05ln8uBhHBr9!}_1^uXoyc5Y7f;+2ec?Ch z%R`+{jOX5cKN@X){`n+YpchMwEY_)^NrcQ^xvNi8G&DEW1w4&=eG1iKBL*-{+BTY( zlorjEPmz11LZROlnD_Vp8gFJmerMT|YCyWlojSuwRe)%6@Axp#b)l*ib3b@&X{She z+jFgHgVl?~i>7E5xI%!_3kwRqb}UKGVb0ux7KE^t=ie-96+FXr{S%bSQDKj)y1WTP z`Cd_00hj#P9$G8@%hz5JZ=z#q>p=Li7-5n$v`HL0Ln`Y>`#=h8Je=@-PeFVzextm& zo)0r~8bSSlqLKsK^>tiM^^fgizCW~NI2*TEbQqiPa`SYU(iH*d^%zE4uk``o-;PSPkb$bhNF}PPL4i)vzE zsR8U2$pPf=KvB{tv`J_^s%Y<2?YI#v>f;8GX;v0vF7QX5mb_fWe4<8TqS^_fOtbtXlQ9ulASjD-uje0ts3s(=W&_hxsRCL*R(TW&J! zLe>pueo~67>FMdwYr86ohrP9r!op+!$WO(JXI*cuyhA#H=U!poM6-^5eJ`a&Lq1Tb zyHIKVHN>}eVtn(}#jknmt!aR03d8Qq$~5XZl5}oNGXDMJ>{K+cUsg%U!g;c?jVi~BEa`av3#<~vQ_Og0mLLz%d4S7h-s*nXv9bZT|a7F zeZBK{{>ejZol4%e+1&I;p3lGjm=HvNSO52NJnGI*fv~9~z~Gxuoce*Uz`=dD_Pf8K znEpXy>~9)FpgXU4+^1jtF=G*Xnq2U!1cWfO3}K@httL8QQ$}F$H&P+i!XZG?myVBr0$)A_4v#f4 z&Dx@((?sOp$;ryuH0u?MRjP9c^GAu|(UD!HXeY*!CWuLh>ub=7o(RRx*$&vt$&@DT zAG=NKtPM_1a=d<`s&mDZm8JEJ4R!`8f+!dX-WmT3ldx1|F)c)iM{E@?d&i5 zE<78aOs_zy!5h(Ah>UT8(Xtc&aQ+Y};CBW*rc`e8UH!pL)|ShDz&@{Pv=H=VF;<=U z?4O_Lnv`S`hizKcP1AqtTz7fVayf5@7JJ6GEC9GFnmWu>>{odHzZXFC3(k0)!&rvE z>s;vs){&K$^*1<2LSP>sGOGzKH~8w8>E$^|5ZT_!{iTirvAZqXlnx^CA+}nwbP7Lq zfFq;9U8voq-QX|w8~e{6E7>Z+wDKSCDQ=~>I}~@<;7%!4+^x84akt=J5~R2lcM0y4;_mKF;q3q7 zTyc?$jIl$q)_moeKPe)DS4c=O>}Fi6f1I4S*=rFKHKch7tFP|6(C$;96cwhx2%IS; zB^C5oia;bql0ghKNMY~#X<0XgDRJX}s@ZbrR3bnqHJSYDa*Nf#c}YQkf9}s|8_}|{ zW!H#x&&{uj>&b9{X^b0)E}u;cODx%`#KKySh!ESL%o#knG2NdFkm$4Vi>7^Wm-36=&b~uKTPMEYvZNF?h9pi!OjS%SctrK<@BL zPajXdXKz88@Ny(@_d-A?#+P58+Hm0J)nKc^7f3Q{FuWiBq7TNZA+v;gN~s40+%gr9B} zry-LqQipswW?R%vj#$oMFlHy1wx0W0%kI3SArt!)4Gxy{I2Q;iZ%S8f4D3r*6^-xB z7;Y$c+-jP9i!1tEZ8~+@YtDfkFSA&0g-LwYmVe&)h!>}#_?S6M5Jz`%r`frFOU>Js zN~@UWbY#!+bq=2+s{%LGnvvK*avbJ^`1Bk#h;Ty$ua%uEbl#FMDfS#acH-vH;!W~> z96d+$i=s(YDnuA{-?lX>tPiMosn%VNdq$x;o9kNs`8Az^j#ua6^6*lxnknLnfl>*! zP}Fw1vwxq8KamX19L-RNHoMF*P2`KII!j=qE3;G>bVPP_U3r?i{MVq@lQI3#`d5|l zpRd|D(b7qOh@ztvGDNIU6jI-Ht;;Ik3M>h&5TMB%+1gFpDe-HN;HEBcWc&u+GPtww z?AS=$4LE2S=m>jLD;pSaQD(SEW0}Z$7O#0gk`ng3A0OYhys_45GV!1^AX-piAkl;p zfN7xZg`r=WQgQL|P1$uXpM)bXkpwFd`+-*=8gwEHNoq)yU&9Q`cc9~r7uh9&gU{z3 z1F<$AFAza>oU=NDRw%@Lf#X9n$SWRiZyWdF>WmiA3Np#xxN#~~`sT{3Ot*cjosHk@ z+VAR=%oNE#C|nl;*K7;p+W$Pwko>N1D_A&< z_1nalF4uIKvKLg;T%C&jq@<}DxF}++8W=SDuD-m&tOVSg$g8_6$Dz`Wuas= z>L3M%#E+bHGzC0F*bw#KMBiPkc}_~ac92A0_AN!%?>NF9!(Q%M_J`#rH^!URcSjvN zHztAm{=M)8QtI4S{Z3N>3+Uj~(qFIPXVSsbvyv9w(ewN_^wH|( zF!X!jd4Y zwlT+@Z>?9kX+1&(O0$8g#_RKL2uC(Pe{1RZueyf*0R1l|=EU$HZ4Q z;wHlq2?d%(co`^M`CK&2l9DJI3ncI@etE(6A`iWy@$K`6pwiA-j*}W+z zRWiRpegJLhBupNblro?`c5KHk$BUMY+l%AltAASJvG=*>L5z6Hi=gX2kFqtA*wv zKW-h)sT@mrmEQ1TG>YYf;g9LFjg?ZfLIE^D6lC`Sk!8PL68hxg<05@+vRpoc>;csraXmdIzEz(OZ2=3g-BE3)vlBwgi9A?cQB2F* z>$9%ss%<=pKxj(hMMN(@iH%oy#DV91z2Bn?jXb2FA?y_npR79F_pBuy|82iX`2J*8 z)9@GN1~CLuhe%mvHMHGh+f?tqjIYCt_qXDk;&*q_TlZ9oh~~#|VkeK^o0uN8R@$`l zMonp}A12tnk8rh&8p031>?NfdMZ%7ZSDKL{>%eQpa3I~i>q*b4+2s!kT%N1$^w;v5Di&TedVV%mfSvBjLS{gbM=($ z@u!BE#fE$C4}rf6W*BNSQ_;|WCpS5HuAY%limzL?(VK``nWQfKzC&KoZTX4E)in+aKX{u zqwhxa2?$k^Sz$KZqN6nQPZGx1zDiwhIcvhhWTv;P=(u(}L}-FSMsK1P4?yFT^g z{_Qa{J2%`%>|i=tQCe7-GBdrHu$mSftE8t#1eHy#^*v9BB^HV|lf}fw2!FI*wz|2w zt8=d|!vI+=JvSfXc!8hdwv6g+NPtfUO2wkiyg!_1A6X%VyU zyfFp07VzvoGsCs$bPn(LF#Y^;m+m>O=^Z~d?K(|Rk&=Qt^_O>uKEFLqtGw-x`wRvB zYZwohbu|M=?6Xg@n|~B?@<=2Ig5V$UQt+Q;ef+eU3>Lbqdg&`Prbz7_(?{rFns~1& z4bgyoW6f6d`@}>f1k+(17D^TN1Gq30`4skLSyRu#pBfBUAh?i;{$Dekhz4Y@cQbZM zIl^g^jj!U-QlstfW4vE6fpVmGnjC{lKNZJiolS*7J$T;e>GNdg1x|vPhuB9tW>9q# zI5|n;?Pq#d*CU~~z@nxWPhxuV=y$#`i{rb0ez*@<=f-T4BG(jRq>fbdf!vB|V?_;6 z^jszt9~JD!Fx?#sE5I}h6WpX{&Cuz3waN3j^Ir3|`uKd82WhEH?tC@Dxg;oO?aJ~0 zfI%V8(aV9&kw)=9CWsG~IXd+~v6&*aI@4S~j`QDD_84!}YalwFZp|#G?J5%Z*ysAP zo4|x7NU9eXUa>;rw`S5?!0r>0bRPH+JUAG=G@kBlAhEH5})q353zZ+eQ ztmgq9Wxli{ZvoH21tuDY-2@4se(CBFSkb@j+U!yOJXI;XR$D36U~z>M$;}12g$){U>Fdo@!D*mM+%cl zN!^96RZ2p6l1-byshRQ&B>k2%GqXbdLT?M{g9aB@`?`H5b=HGZ{TPY?$> z{y~Teg^x6SCn0D2=itJp-K(AKkL_s@hWN}r1ue);51kGgf3(CDPhuyTwpCdCY2(Cp zz(EoElb?K2obBHkE3N{IR7gl+anZ%zH{zD7=tZUML`jubevi{7DF&kbKf~0`KKcx) zIF;X(hZNp3VsIsh`JrkvXAa#kez`=C;2?-CEG}dZymV2J-NQjcaT91GAUo#y~)Jhm#y?>Ri-K zkOjp|aN&!My+hyetttBf2O&ClgWKlW`Jin*M2peZ;H<~-zdstn zD}hH&(lWwK#tln^L|0gG(#|@SpzUFkXvs8e1j0%~d77Nqdd?&F-}CncnxIISshmbm zK~KQmMCQnf0Q8r@7ZtOi$&9+%X2fu>N5?>EiXN7Ey-d$XshkMSK+Tbk7RxpdQrds1^Kb7`ZLC5ymq&UZpiI*_0#Rgw7Op!bGxw-MN44%}lqa_=@r|@}R zFDe0o?c@ov1LnLCExVc$eg+cV0k*tX()kK~nC$sm^1M-75a#P8T||6K^XXs4u`GT# z+^MMEx;9zMZNj*1_U0nYQOBQy|n_`lI0I6hukq89JPoliR(ay%S? zo6M#h?}a?iKvwLOpEqtwU4ZDB&G+-}?aR8iZnzttkH8n;!7l)Vgufe_AgZK1E*;#% zu409GdyCG1i(J+9irD%3L`)Ko3;2V{C6km`G0=G;p!2`Ittu*2pd`7Ta~kJY@Bew; zpe?JxPTO?{P>aSg6=?AG@0QQZkLmL%MqTPa*wP^R!je&#k)dDs)s5-(uE0dAZ2 z2GN1lOySNV8{Vb!cv;(n>9Sa9C4cX|kOxHL*98Xp#oup^>S{Xuv6-{e#L77gZ1g0N z8b-d@Vefi3u`Yj!v*S{%f_qfOP7CVmg;{^jAHR-{|I(t3ibDxQNgnR zmSv~8d$uW^1(|SQA;r9^f!yv|V9gW?NlrRE2ZVI2$PdDBh#&laxeFptD&#LKum8ks zTMb^!QgKxMAeF~%H8IbQn=(Z(rqAn+C=Gib%giWK!l5>gvwzy;!QnANHK3ByU28^9 zAjX;S!>G7naX74A_F`0E2XE(k!=HG;{{pZ}wCdaznaY?ZA)1F%M@k@S2>={PSN~of z`H+#Z{dSL7Q~N82?HGSysGOb_o#FX^yilC%#i597KG!oP0mDglbaWM!9AT+BnC0GB zPV73l*-0oe2mlXun(Txs8L5(6sghZY7TYa$R;CeGlTH@jckPa^8x7MhPe6E<7#Nf& zhNu^6uk8S_B>oS#f^59`)y^Ka8(sq zd=A6@!KN8^g9rP8%k|C|)vL(_vCXkeF2BpUbP}c-{Cak3%1Is(XTX>nCt9Y4=vLqT7DXmCZTj!g z&duWWO`C59hx-=oO{uv1oHVx&aa-U*&q|A{Zp)PdB4WpH_ut9s+TDQQ8403FNlmM@ zA4YrfX=^!ObMHss34FLVde|H!Cva)Q+IHrwyH@{v^E0@*YdLHnr}rW1%i*c}W%jzr z=zhMVbfw0}1Q-LMx&i|c9W`|}P*3D0y6q~>R-jb~BZ||LP$>J9JRKRlqYDG_VtIMd z!`70}S^bk^_dxWYhMuErc0to`MlQiZ=Q`fc(;vTn>;DxyXHA2PF}=1btKz`=8Go|h zcw&1bj4`LYf{waRQpJNQU6~0nHM}%=z?A3P!sWJug3QELIa{OiD2wOR(zK+VU7{I1 zpDE|k(8#DnwKfhugkg?}TQHMU=+5OW{96)^Go5nA4-Kt4`$s=kBhdsWVFg2sEg4ixqxKv3Z;vGGZrZrPvC*WR}gI%;eJTcO3$}_vP2FtkI_P)4WSO4Y?uFQW) z7CQ3>+oi=x;Jk42cyd|&W!8tmG&MEVTnnzO{?m6h!PBl*fgK^SS22Icg)1IoF@Lhi znYzUP*`%~3fbfmxpGJ~8W}|ImD(pR}uEGO+sSp8;#j3-LoFGBO$>i(YP4Y%JQC z40Vtil7t#$&Q?y|nVp?o+`)nMyz32fE%2Q5Mi3q*9Y#P}T9M0_R#73V(|HmQpU>a@ zF+n6s#j4w+o@2Xic!8M+<@%ca+xJjO?6WpUc+XY;56Udxl`^?g6GZ=IoOk_;=38Is zui+D?Iq5U!ri^sH5flNO1vRJF6X|yWnA+8y?{p~vi$ftmfOg+E;mBGb4RVrZuaYkuxn^$i+AEzS z>K+vB`ke+B2Rb;m6DIaA>I3;=w_;#mw)eFaREsGJ)~A#q946t(7EF_5+OUBMs>z!5 zdaji9x=E5H;IgEttTbTOYfWS!Zx6xY(U4TK{L*jwBUT0~trY3zV?Z&Ai@%$clo`T? zOBK`~_C&XHfCWrtoB=PIX-1tmxjsLZ9lOHnhDQ$%h2zrrfd`%=>`up6&qyZ!{p*>Q(wsNSX z2^yjZTs~%r?+EP8SR#H>f-I+beF)CWwN{wWeoh zCA9M+*u=b|f`?=H{Tp+TzZ73gnKilWpUSqJ7Z^F6&dobN-k9Ng|@#^K%&pUG$vEnLY0tCFVNN z%-I%o^vToEVWE7eT_&}@#Y6lMQfP&{;e4;5ml7vky$fz^UgBsT(DX)&r_WIh?58M$2NrTjWl$8OJq9hG2NI@?B=fWF08ZIbm?TnHN zTTD6~9OB8PO+) z92J@oN-c+sOhYJ-2aH-f7 zO*Q$Z2Hsyo%ynB7AG|pGXip zE0{gpTUk^nR?Z#%I$udgLSngB;hlnuZ_-Fmn>7w}LIiJoP^I!Dh={Y15X??ipFd&> z*986DqXW=lNoRSYcjO{LVho%XBbtJ(ZNEy(225*R<~uOi4?Hdh@yYhXEoRxjvD~2d z69`!{#VOzZN)@DG3^FV?gGJLeuShLaXqB;PnsO7WmA*=UO%l&U`+oZ<*}u)fZ21up zN>);zpd*ZeQnPGtu%GaK^>sifU;gd*U8bVS_Inc< zlEMXhtDa5jdc4VvjfRa5&!J_}C^=PdBa?a1W^)?y&S%!@F7^Z#axHKwqV%IBYj$E7 z71QP!s?+f}m)vm9$XzA58D}PTD8>D{r_iB|4KNa-Kw%T}Mgeg&v`%+!+ckR4=WEA9 zY|I;yU#U~~%K*P0vCA{Eu@U3y+SS`?R!HA>Rc}d84@}7kj_ffu9@>_Qq)nuKj|hbe zr0|n}f<7$f>|8%i6QdEtA-cG_WboM0!Kh`-xQT`)#|x^8LQr{5naQ(d8tI0Ph}rf_ z2lGnCc|a--a2U|&C@#E<1?YWZB92>wr_;>>gmjpqHao

U~=VnjfGN zzRTVH<(dqo12iAeNAu6*-xqriXRW}tLGoWR1-~<`pD)4ws&;O+tq$@Vs1GV1JIa++ z&!GTeh9MWu=iP_eZLjtab8{UVdwZEmE&4vAkMa(6DQZ8pq%19oJlfDh5qC4 z7R~cI`(!Q;QW&xa$|EAHl_#t9>4dXZ9L`Ic033lRHC#tnhMR~Ii=a5r_&-|PUiF~Y zAc-5F@gf90YG45E1stEs^5VL>Xy7ldQSwurnc3^Jb`N}zFMa>96LUYE4iZQ!{!lD8_070NI8T|+`o(2|+A zJZ?YmnRpW&^2*>TuL!M%#zut zK_MXZ*t3uM5hXn7M}u9pER@Tbjd=VLI!G}4X?OD6zMzI7AH8W^MJe&&?)V(bECiS) z;ywAko9<(ZaRl_@-XOwraP)*=IskfuNG!Rw%=*uWTC)+IPHWLe>XC&mYLIXNZo9+y z|7QXEEK?pv%d;6tzeZBiranFShzBVY?XD`HCu^%kN;q1)u7v&3&fNiIfV6DKuH4(!`K?LwpWUWHqyiVi9E~ow_BxPpy_cZ33859lDqe;lki)!lr;plz7#Kpg3KL0^Qm?e|{OI>@YE zhKM8U;UZySi4|6i;)$3Sk~*)k+UP^C^HaFrjs?EPyw2qEdApppugGJETPH=T&J z@w*)_5x(2#&^htYm_=1%qRAp=dxrwd`^NlT%7f$iSaAYF%ZZLmO-;{Q0Z|QWh=sVFWpB>knT;ZNNYG=9NCcsVypN zO%u4@pIMm+U3KVlP?bna^=c2mRrs_jvf6KoEH33EL&uQX4@Cx1>PDApqP)CPU?gWo z9}&Gi&38G?D)U`E;u~GWSml|*>S!M#{{2h=_`pSVM@WH>qxm(NzuPZXlKmRDDH`zY zGKD5p?L>)oRV@0J4m+#tf1)IHqeakL?fX>)W?Cbxu80uTM>49NY_oq)nCdc*xUY z?2&EjvcBobzUQp~e^)O!fNfXy?&|d$TbFL-9%_Ke2AtP{CH zuzq<9(Er?J9+q(y>xLyoO;}-&LeRThL)jsGNJj^J)3UUTmf-5DznhS6lr$6pUKG}? z_GXv2x$xF0UaYUhS=%;WKOjUR4gHFfK+i_;KHX*e4(iabc|MEBbFt&@j-;0BwE8hFi!P4M8=V$*7KBZ(;@4YE z8b9q&g@;2=79Kw;rm+H9Dv_UZ`ZEg$7tj9vW>f`EoIc~m>^L!@fS)!@P9C*=jbT#1 zjQl=0N9Y?Y$!xzyNP~lrMKeb%MuXsIQ~kSKy^z^Y6eY&o^VQ!5A4gD;kb{i76EvWf z`&A+@*W~Nhz4@IR+m-t@R#VB#Z zV?YZyYLIr!@-tCKQhTs)RqGQ`Jc&?jJ@ivzO~y?QibG3;86$jh0`Xm9~ZDhw8u zTXQRmFNOi(QnF0!85)aio?<}$Gvoutrd-3Uno(bBx{E>tyUUMkU-4R{2~=)Nj?Rv6&G=Bmi5 zn^3ZhS7uZUnE!(6efWhH>IDwg(Ug<&CzXC5CVaDTnj>r=AK-z9DSAV|n;kNML7uIu z>3qN1ba`b5#0k+0`NwE**!};a;nG;!otyXEEatrUknW<+Z`6p(IACNq2}@KNOh$$k z6&CS1o#+T8)#SUTrta+TL+7l2wW|#am8fDzmmVBDgXQE_Jgx;*@}d2#6*J(;;@MzBe|g(9oMO(Yi;u-Ao$f|JY^us ziVWnXg9|8Xb#hu21Sq!7^ghGE;}+3>PF7}f=-^6K$n%> zPv2`*>kd2S1;&qOH?a!~D|vtCL&*&zp0A>wH33y}Up(XI6?IlcvvsYgEUd?m7s9O7 zxHj%KuVok+hG>Z}Olz{8?gc2ZAzM2E1Gw4VcQ5k5a*+6!F>XtJUN}2FF(w0|4u1!P zhPd}JRRtCH+>@gB!t@E`R6<YJC(`Tv@!d0Da+Br#e9q$E8J(S? z3emEOshKJg0hIm@d?EkfcRrO+8(jT(`5b#_w5!F8BU||g4lboGD+mq~jNsEjR-~uQ z3^32$*jjaFt(0?{%^#0=^m608W75u9zW^V`|xCoz2JuQL@Gcn7mj!Rq~AwiDxhl1VBxMbS_%hxnTZL;L=RiQK(z18=#;iEGHvTf>F_F7e#lhsp0uF2`LL`3 zEdeHYODKkRS47&L)`^GEAtB+A0xhd2ISyxuO72F?q*zHwIgp6d+=9f?^s^HvdxZ-x z*lYdv5rI(XE4br03;H^>=rd@daNE+_#(|x<|JNwMi=jk%_xS!%_-U%|;KqkeDXTxo z|GBi>Zs+xxyZ~BB7C{{*1W>mLXB8H&XH9?}3z7_k*~l6F4b$ZOkxbkB?0bH>65C8{ zYlW#iE12az8a2aMiK_z<2|*G)RGb2NN1nob7A%eg2NpjdMQg0BjjMG|^>wV9^Ch)ZmnAP4tQGJN4vSdTze)5+clXq>Hf+VPIb4_#zG4t zym?$`4iEuMsm+H{OPTO+C&66nXbi}Yaa&647;t{Rl-^ve9?8jiV9G79f5v3hv+xTF zb&$#3sn|ewH~V0G{=gph7eg&%B;m)lb=RvuHlX3&%-Irtm-Z+i4KO>smQbbGe$}Kc zP~*t=#d2Z~h;~J1$-6%7aA1%wL=@Z5;Mh=I5^UQtSqskkdBkXw&izG(L^8{#Xs2oD zq(soqE6WUTT<&cQJDb&K)Dhx~T!SGmY@Ugz0X0sI%!=BtTRqDRyaZF`JcSOJ?s22@pqM5q&=R2;}iwS_I5FZQ8vJEAUVO z91cw~XZ(Ji57?YpQu*trrWGHNQYE77RRviqF|*I30_QK+IyJ_W4iO>f>lLs=H?syS z9`tDtNiq#rOJjUmyb3@&GG9>DwL#7T5^1{9IenYr>YO|HxLC-t*f4vSYTFYX94Mhn z`P@i>)Q87;V#kZQbfc?Rq4NSJlx#jnXn_fF332u`dSKF0>?Pn(M=cu#gS zTl9c8iflfIqLQ{4$G;Vjs>W#Yb!Yq{m?6{W^3t-3y=f!Sv9QsA?uA;~hY(6MQf4hK z-tteh$&zzC`X0nlDGD<3&X2T;nHBA4G)LgY0#mwcBr{z_3_=LcI^N_bavW#~ z2nHNHDHNz$)`Y>e2w?fbrZ)T-#?PCNe8GRF(3t-+Q&SMhCn^=Qqva|w*)3~uX4;2{ ze=$<{ETe=G>jq@79qc&MXrM8e}@v?ASplSiubdXM*%*y`M_gFUGUn0ps`wwd~!t zi(qMWwd_3Y>(!B6`(wiV!&7#yzGt6HqvK0r3|njTQ|Xt-gMatz!;1&z47f7$Uk4J% zWmO&7!mAR>mg*K$r$u>7BeTC6RZTH6;X(IDi@hWeBN$^aj35aNL{v`^XwSSzeaap|j?ER`5xY^+;2Jpyu`1NU( zDn|CJzM(#PrS>nme|TIqbGKjGEGQrB^;V?Ak=wfl2A<0&^6K6vrvX26Aq7dcgta+Akr1E#lfVoQaGzyfAmTFU!?Zy z6<;*U)q%ZOf6u>&U-^RR9nYAY2j^B!UPuW?Bn^$0>a70$@W5|7gaUFT2r;HmwA2{J zWt67IjW@1eF0E!TeLZ3P-IU);RsP^FYI?~J;FQs7t#KcsyIN0}yN(c3l(KFCvdT?w z48NN(+t)cBW+Bhvw?WB={QNoFZJ;8$)7=B_ce7}<;x((>{;;3^tCXm3-tMpK+p6am z0}UBRZ9X9n``zH{bgEIDw!4#F+gg((7O$)J=A5dNG#f+Fn2Ah93M|X(rekbrWN+@` zY?YEsJt4AkW(XtUSRFS}Fz19r*=x28L3AiG0z8m2(el4!6cAAH@qHrvqNSkdN?dO_ zwwKE%Heg$SeQdNo>6qsg-`nfA=Kt&t@aNRy&z2|JUDJLzIQ?@^*Dx?pW%|@(n{;q~ zzP+1nWV!Od1h83jc>}xBK~(bGL=xPZxI7^g8N==Z&V(vTbmVL=mv2802^$@RhW_TZ z5fWXPH1veruT2C=mHet=gf=z;M*rWdoxtzgWyg+`c^v9OzFeDL(WPGoXUTPxye+cM zf(VlF0=qN7l6S(l7yxDPT z{GrT>K006&Y&qPh$r8 ztsqLt9upTA*N44hRh_m&1lIK2x+~iX-pu4U<%JX0m6pef<>t)VuiO0IFSroni`#iS zHQY}nt11DV5nNVF{H{;jXs<_;}3gvkTiCOFA{9X_9LzZ|#h9UZGT z;9km+s2bv7f6)^R*R9{TxCBFx+g5{S4^4rrgPVuDF<1%h4s&W=NPITa^6q3!mMOQm z@E1bzV(%riEfTb?lxsNoY8Dq74)4|ei2EsZYI<5iL0MhwJDphIO}g;KM#qZJ=% z^>#u?DThC)EQ<-0j9k8|K$U80ZT(+4EPD0Obh0X!KgR*2OO>evHzmX_r@D?+tMhKy zo{}gEtj;s$!YfTb%88f#{w*?JlPPS@R*DY+C?MX8IAPk#!1ijAukIxWA)AUTJW)g{Vt%TQqbEN#gIQg``t<(<^Y z!y6OBgzo$(g&H;hJ+Mf_#UJ>@$vL+s5tkm@dk_^y& zbsDZ*pZwu7PPK@#i4G4OHtTk^)iw0Sas<9iy8}6|{iAX=D|4?%U>b!K0YWYr)g^y0 zrEz^mJ-0V)TyZ(H@a2u6=Z!RjGt+|E5;uK7qHX&hPsXd-kOAbvh+*nflbRyzuqQ_06s9!y~kdDig)^WXKs!6XRrkJZj(z z8s;P6MOdbo6%Ixlyg{SOSui1qs9Wqv9S#Z;y}FjxM0BcM2A40LQNZP=TvGp=TMSbq z-ZUdu(mH#~+mY&nV{%B>r0n-qP#L`nP;dSr-|*3Us}=~rda$_evzbrk!7q?{Jo)#H zW%Fgv8C9D|Dx=d%f8yrJ@5$cZ?erzv0S-)nAAl7zfW?z5_V)Nbo>XLFc%Ya$9VH3G z2~*~KOSES0fn2B8IIfH0vE|6uDx1yhFuvRkTY2w~^9|j4wfvjNzZh?I=jP?%a@}JV zY;6V5eM0d6LLLzPfVGk^a|pm*R3@J1@_c<4@b-t?Y2g(3$eBJf)ntt$g!}()YQVmF zCL|=G!9wF$SRS3~#;UdEKGu&NyzuEb2p1PjrJFy6baf@H3K3sC|694-&c8TXH>Ax~ z!a}2WY85%i>TX7E@VkTAj+7rQwB2K^JKAjQYQGLogm<(*?-AeJ-*WKpnBA78z8u_< zZw)t5M$^g2yvtDH#EU_%AC4Wj?Xl!ZlCzrPc{o;7bzSf9{CP+ffk9SO-jwjS_#?;^ zg*@PbGMR3U!^0H#^A-5bl(dP;u1)p+-GE--WI}9aM^|U(3BT^J(woMDj_@Ku67Pp| z`CnEUq?}1Z>qG4CK? z)7!Gj9O2mn7+vx)ql_d_<{vbk#2T;kce{K4a8v)a+4Z|$mj%~gJW02G!{z7)$E_<= zx>~nkv}hDXYhnNJA7UfGbE4To?AgRt;cEn*l+|jhV~ee>h*|VCd*Z|CIobYH!Rm_p zd;;O+?NxPP`*2dj>SLDg zR#*X^1mD((bDhsEpT6I8*bsQ^aCXqf#-Vp}qHnW?@>@l0b?F`u6{$zInOF z;rfIo97Z;gBPh>LVmgvi`m$TpHMO>+5*Wz#e1F!%$2}yj3a|x83BU-DANF7l1UTh+ z=iQx)i$2WS*Jb5?GiOZ$iv>POb!Wy*w{Vb5K~Y0U-UL}ZxyZmXx!;dsWD2?VrzU#j z58<^0&H?v-s=d!c*mRrjhyz}S*dk%uzkla!Mt`o_NM`EQL=#j(hF?NKGMB`g!GP@8pvX}@brj-xs+Kzz1V(zlw?nfqzflN-FGRh z@2rPXHVXYV86{#G$0Yo@b$Ga%4kvbskAR+yPi4DSyV;}QgD%qapL06gL(6H11uh=m z?A&q`|I*mdgs_tC&q!-y0vs?+PHsguizQC2+uuO2l4-r(G@#;y5D-xuAO&A&FlR*$ z3#L5D1S46F>Z&%_gD<^u7%~}pdMG+X;17Z$+J!#@w2KPJd~2^C z+>?tIivalZd@_*a1?Mpg9r;5rQ#!S+8&zbvkHqHa8RT-z-o z53eVS+J!^sj_9!ndNym~FepN; z#_vMc`;*%%VXgqlu$qyTX=p7Q9Zn*VJ+XG-RHu?NDz+DLjgNDK`B7DZE@|(4@+D?| zO|Q=a{}1G7TOBvod<3Ayn}C&vAjk%|b^p2bg%*E?`r-ULu^{bNr)`#DO6{@dOj0SC za!)en1omAuyXGQ6CA|(y?$_^R>v8!~aeb!%aIXENtxqa|k51@A41Lzl%ud&XzuHMf^)lOSp z@VCjfz;=s$DCU}#Q@^ZZHD>)Hh#eP(1qw$D*Lj3l-P|T%5ggK|D$OpgeaPymGFbn3 z^`SquJ%vQEj72OPB8~9U`m1QboP&$)Dykf0VQSYYm^|8#~Vn$hw~V zCP|aGb4edC_{Zi;RM>N-#;7Qa3XdK`7^a186bs-L+ZOI=lZsFk7L#n*kdfVOkleMOF#WbU_KQ{G? zb(KNVF(oy|Yx0Y44}YBBeZzcxu_! zZY?R#L1&PBFF6u+0^+nR9J&Hi9L;E?wJvumO^$RTlLDeVLiK#exFzh+#j;NmEN&t} zsb!aDOC8m#m?S4mXQh#~c!WDlqhXwuM2k(EDqg2E#KzF8Hv9XxdlCdbVpv=q-GxMe zp!7kPpw<{E)`x&2lLo|bY{pPs0V%giOc2$Rruv?keB8}S|En@r{4~_|k6W}W-k8~a zqq2VBY-MD)l9e`_P@_F+zMxDPnHbG3c2S_d@7FIwO9h#hBsrdEo$6CSy0ta+L zvsROqXT4!LT!C<69rr34nKUdc-TSnA0pdI|uJ>Im|YnAU8=|GS{6Lq88nG6aD0BlPYb1(DI{MGv}0WZnq zu3P=;WuIC190Prmz6IV;gNG4*UN4r|={%=yGZB}F?f z09-yvV}?DZMVwV;nr30HyEQFK-j|)N>T5@Cr|PfBfNQaK(uO2kS5FKFZ1;+!)qH(y zS_eRbZ(%U|-J3%?$sqo1x<7Sq)My3Mp zY&_*%CX2Aqp>g-C6IWGgO2FUF{~}zR=sKAz%YC$cN4^>iGlej);eY)ijs+;@3#VH4 zyvGMBsUW7xt>IBhHZlBqm}KUBuN~Vf&^4guZuqSs))H?d`a}@;vW@E392bTwkoNYqQfL4C-_WY%u}| zGoba2|7>W-JMPy*hN-6i{+-Bwd!Yv=vQ(Fz*6Vi$(Al?@+A!@auuN!~l;o-6N$;!&A1$Gu^Dt~KqJ~$vu zW7Z9wvxk(ICoe5U{mSYtd^!ZWyE7hpG(Fa_{t>9w#}^#@Q-eMJzS!KU@&GDArDEg% zXgaH)xVo-ezahch-QBHm2<|il3BldnJrLa8-63cKjk{Yzu;A_x+#UY?ovL$36Rs{@k8LS5a*?r@qaAB|o5G(BIPVeU;wcXL>^jZbHL=3hs2?*c-hj9qC zb4rYiS~EwJhcNKSS28gzUYu(FF?9KCpu(0_YmzkaARC4mYKNGrT*kmOb`WZrzcZuA zzVq++*N&m1dEqP`=lH||o5kI(U$sE1Ql>`l_M^J@bMhPxz7XNz@m3b|FLN3k%Z)

4QmTlS0_bMA%L;^k++3oLV*P5=sxOzPum8+^#4#oc}G9FgNW6$VI|C&00 z{Q>PvM_!nu$6_8qx)12EE324+I9rbAyHm*|K|0_;+%brjWrYy8#3Nz06N~u+&i9&gdb_ox|pX>2Sl`d62 zzOoZmj}88b;Y24*O4Yqh&q6viVo(C1NRBDfcoE;Sh#Ec+hb~%%i#LWSe$!2Egbo`I zBEim&Y z&$WqQbkTu!$AFlH(>^|~k%)j0DW*YR@@nIgMJ6WOq3hXv(cvIz*Qr#4D23}UJgJY# z(HZKrs-l*7kIIq6?AgN^!o;jyD2YZ0b3e3LWEgOIvyW*rm5dvgRcDy!AelLS=seg% zs%n}M)C+@>_v^Bt%-zf3fd1BlaY_=T*t`T7fbds+x?k;GJ=laAQtB{zIx>kauwmIhg#vqVX?Ik zBoA^MD)#OK>|vFQ{T1@xw!;=-PtTd{Mw|!w9dW%~A3RPzj{^?H-X{BJ#7{6IE*_N| zOVgoAe-wUPb$BcNtSP;GKx`8fvR2dOUt3kAATXL(IQF_4-Ke*Q`XgN-du=_YKf25z zl_}-+8X9=z&6g$fuR7c9n-pF0)5-T_rw^}r8mI&^P825Bkk}Df0OLe6s;FA)kutlw zvI-x({4CAMbs)g;0lhpIsARwG$s9^8OGaf@+BFn=|UC zQcDW?3O9}rCMT2nTS&=FjdI+A8&4qHYSx_;V%KNFd3o_GZ|4-9Z^vbS(+!_F!s!5$gWhKV#`PLzCET~_$|j=-pCJ%cPSvvW*hL4H+jM^yLw&eyB!=%og4?mRtu1CL%#za{pjUo zBF*oefq+6K<@xLtv7VujY3wjvnI>5^fhIF*Os#Fj*Qxzf_~Kf2soRr$R4J<_yK8XY zZO21!bYiryJRo6v+XSXx638=i>3mE{#lt`dQRN~GgM(*e8!s*SnII(`xVA5aMZ3?U z7a~exdS6Q_eEVGPz4z-^lID!x<>-djRr6&1xe?G@$Al?ct8(g#h{T|v0nhTEThWfp z$Kx0ac*;l#S45H)fSTZ8So4RbHp{oE5vY_zNaLCSGa$1lC8o#?av6ET zmGSk(WC(bE5U3>?V;-8>n4LHkZOw-MY6~N0(H~1Y?~>$-lq-sv-J-}4A5ry#Jn?7O~z4?8+L*@og8x&YZ>SQRv#BCm4wVk6{zd>k312J$9NTMY6U<4bo% zR$Qi>y7Fae4Gqnvb&CMFyU4~4wL&S%iYlz^=aN#S{Lq<`nKg4*Pwc`*$f(1??$#^t z!cejxrZr`%Th`O~8&lro&&Au046!Tw*%A@|`7I zZKVQngFN^Txg9UUOjS%jE7s-%&b6-YBFN+wg zKWzon!XLE-E>TfO!c|CxnQ_Hc+Af};QElI2<>W82IMXk0HAN zi!yVB!kdk&Kk~U+&I5bK4r0Wcjp2qXjw3&SwcAGOB`omJzZ54WotXY*N|uE;2xTDI zS<`QNz;*H^(DLp0UJ46tvkH!oE&0+sTl*Lxc{+wES#+Kri_3`;m zjjJrCzTN~y(sD1Ixqi}w7ZV(U5dx5?mv0EG4LXU^*JOnA299sHowO>5bmLfvLhLC4 zm#x4$Oqzauj!1j+^xS-C;V}>jwf%b~L&Otp!*RVw_q;2(%r*r-JwcOOiAXf_Zk|nI znt-ht89e&i_JEA7`yWwI|7W#Jezfe|W5<>(715`Nh6E|@3Sa;mi7lG}5Q?{~GQ6n7 zeRbi(3XJQuoZDA(1iT|G^ZetkCk=b%_}((EW?b01uM}*KhpxAL&w-Q9?|s5gYpTEr z`VK-jwHV+VF*Nk0g$B<^n?W+21S97x%Bvv3Qi7xRx=ozUFIsAK{ET4Bmj`E!ZyNRX zEB8MXzF9JVf0aC}l;9`YUxFt$0~U_J+Lhrql-&Wi~nid}Rc5eiPPv;U7&M1^P|voj;W2wqQPhZ z7b9}dw_Ss)YvdNI$GsElMR{3E{7_hL1URW8`Efktq=MPi)$u!0U4FocXkRmtBkZ5k zeio1rPVNIZ8dqYVdvtknF5A1#ak*9l*$0KCdnj3DkdwaX3?5&!0RJu6Ct!9ew2E?z z>U_8f47pd8-6!}BUZ7Bol$c&V5~KN50YJSqJv$e?WY=ratg0@OR<}pXU;|S%5!rvX znkdjeZ|aXaoluT{q};&)@{VgykJk6rk25LPZW+$y7`b;><97q$O6Suub{js}aC zEZ(?LCy^#GG4X%Q%l;`DOFpJRF%Q{sJKkbz!8c6NX)ToOi6|DuPcY(16*QG)CUqJ0 z>q8nAAVzEBkppVc4MkfhVNfqYq*;!(>jB3JGFG&7eJeUxmd7nBS^+Wi#j4F8?>QM2 zJPOoPc6iK*awytqVi4opayyv>tuYV--zjt3x z;cwWlyw8=9!hf@0_V&8XH}JEYFztSR2ERqxmRIn_BSUH{Em zjBj2Pz5>KZVDvSbM6TD<$fpOOVTnI)V0eUc3z?~Nciaqba7@k0uq0BEO=jsxgYW>h zH)y-xhAS~598=EuWzpZmai#A!J5Y2{rD{00*YNAHxpWwWg@uhkC#ffo2Wc`}|Al2c z9ke|@L2*9?`RlCcj4%)uZDGKpky@St8@`j?{5s2p&+A?X_G}$ig#D7#eov#rtM8Ef z>s9W_t7{-qjsVHHNoT3c6yAGX_^j&~4Q2~Ll;06?IF8hG`R3@;3pI$^zdsB4_YN4yU;zXY?QYAreX+X}U$%5{YC(e;m&YHIH0pG*h}fmyoJNbE z6JJ!Jp_#(%JEUYLUshH1any|Hbwj(A;RkdNroP4z<@b_Zu@84*Oc4bE3|ct0YKRs~ zAQ0<|gJV{w6ePx!DuDybg2!zE$+QCbcz`xt1OT3dl}?&c^6la=Llja_pj}d37Aueu z>!PpBrI58Vtm5?NMH-<#bN#G#8hcDkzLbH535fS8t`dZkX%gf@=@Cns$e=;Yo(=4G z5IR=%Y|rJ-#T&4@INsYzG}?V9%y^n(cf|8NJ!?G=7wxFM7%9ZQx%UKULKTFfvA*Z+ z$?1S+ObgUEo*5lMDM!bRg^@)T^FUOIC_cq<=Z!CWbv?E z*-XfeGu#tAzvm?t8o6);eR)Dxmjf_uxXj=j&-O$MmXyq~67D?$^qv0OH16)nM`vdx zoi)LyLY@?(Sh`IP(x6XnpX|_p1<_hdjxq==ivf&HK1lfpV1Zo>CCAur* zt0SxPO?uDu@n+&?rwN{gde3)CxMv^4aLHoYlphXOjK}fAA%A@q|G>2 zRC)fzD!CYkbRYEJi<(@fsI_GaGE|M2 z^Z)$v&BD@Sjljh<=jJg;_@!T4&vlC?s>Z)--48)lnT)h%B15J$i!468-Ju<`xnJtM z2LrYJ9=I3(N0My^@8-aA3t0B*vD8PZe16V2%TrD>^k?+FJA+oXRkbum`a+Qb;|0MZ z8GHF8h_k{0i=LR6k(G7Nv-?@}f7|A~XaAVt*r_9sKy! z@BpiXf`E+IXS4!lB!O0k+O8)X1x1C26Nrknqdh%YY?2b~G*7OZU?dB2MADBrn?E*C zz&ooo?$y!SlB;}mrH6xy$594izP{P@A>gYGtFPybAr{TM#2!}F)*cN(-1%8uUC`1J zQd#$P*Zb=CaCVKY=9>vpusY&a!VO-n0^L2+P5-o^D=jz&%6+qX@QXo95R^R5*I zj?Lk7;-a4oDRMMXm6cXm3g&|VL;Js|q8|_WT#89FQsQFjAh__b2wCjnL_N}tf_y11 zWva}Aj*gq#v%I$-7u}D)CUxs?7IQt<1>I+#CYPGuaTfHOW863Fq?4rCI(K1szjqTy z3-m^@ukW^_u6X@xMQ_<_YWI3gO()Rhj@wGaXkPOsUe6K!BrdC}R{dzhlU)86pn{0? zoXgH}cf6nJ+O6G@vVvJbCxQ|zc$CSiUe|_>E|Y8b7ypX!FZZ8JUv}HB9|p<4T| zW}O7b8;I!7YaI7xj_|^;@mx-j=%1vShLla-&vFlog%rKLy#W!5s-B))z&l1|mU||B za^#7JC6{y@G|nP}GX`|&g(Z)b$btuww%m{TpNFVUr`oD5XyS|}SLq^qn4A_vp~x2a z3x+KxdtAh0C`i6au>zC>xwRv+@ z-wG?2SR{a6-~Sx}Ej)RD9}kB%c6dh|^l6M)p>9c!!6qo|ROtQV;sqWiLd<{KQIDja z8_@Q5pO3)a0n11Z3m4ZM$c)Eh)#(ES{T~o^eULA_I^7!bdbiyY;|9e*lo?Ve((oeJ z8x%Q9*g!T4i-jw10j=5PuXjW{LhTkq1F|*!H7%C3_ujIxb!?4Kl47F_43$B(RV8YK zC}MLO3ek!Hl8K*0SwosSRk@&&sj`-u@{3kZ{DS&eqA5Iv+egUgfT7_t{dw0t88BX@ zB}3)9&vCW35tQa4Bi2{`JNY@BCMv@mx%bO|5bd&(mIz=U?YJ2K;|Gf(OZQC&W7WK0 zfZE%JL4p+1K(AzY-J;%uBxaM{TDT*>1PG6YKu4NC3z%tK-a*-CyvmS&K_$JH2R0J=u=4A;-t-8gjQk8&f5Wt~<)&X3Bit@rZtPg*-ZW4Mdtv)RGEeg1Okz zN&BaM>#&;PgdQc+V}l2d&W=hg^mx!eUvX4@tEJ41bKW3L|Lwc*p)Cv*n1_7`3W1vM zqyk*Ef8(ug9!)#9UIKob4C#i>xIEbZ_#H=E0TEMqMQP+qknnQ0itG9~Q%a1~fl-89 zpBNsP21|9uI&^GIL2Z;qL_~y!TTo_fq;2?J2yysWd;v%To?2LVe?QkEp9n_|663X? zEh1hz39GGeqf;B9%e3NmxigdgFM4k5#v1bI5A|ee{~c9|Z!q%YejGt-(((Kz1Smc% zUIu*D{ja}9MIjy8IZ`qLG91fCE$ui?ge1VK*<;aYLa?-?(KQ^+fc!}kb7(GQ4u-z; z{S=mwt*YZ2bRe4h5+kWlJtaSwLT)_cYdqg@XswM#+{8{CxxT!uEc%4VhZ)8|R$X2I zFFK5$|6Q!Vmi5L1Udw;b{AKIN5aK+`rj*n>`kK91_so!LYWpzw>kVCca8S?dQd(m{ zNebhWa=t+CfV_LPc4yjbE@jh+y(Dfm;J@$*GqGElRiY@OiiV5T$K*Y8usrUXKUp3t ziEL;x6A30IJq3cSXV=%mib@WNuVzJY`uMPDaH4?5mVo3$TK%ik2Ow;NOa+Zr8kVK| z4DJrdm8fI~(9T10v`Gwvs2fupjg8ouqP~I~j%z?RDJ00hKA{+rt6=QiC(80NMG{E9DYR za*T|%wSDogcI2wHFk=FM3FYs0yr;*}9X6crm-5Jcwb*q^ktmmgF8Y=M6Q4V0+g(;& z9kkZ&$;|BW z1@GeHs`GfT0ABsO3Ve?;zA?FPQiO=-kB@k?-J3M+mURa8tj&rv>LSe*!| ztYpZFn%x?(fYcfFQUM7=U=9qRIZ*v_NK1gQee1&kC0a1>LuwVljBCO z05TpIXj5_yCn`#j|F@-RofZlZ^B|l?g%xYen++k(Df+=+Cdrkl6xL8=(zrNMGJE6Z z4m7oGg^3aLQ|_^x=Cs1s&-saQZk)b4JlvL(!=hLvwf;=yZ;rm_q@@R6H=h0PW;foH z*|P}UwKeO^T1^R|L(;WQfuHOYu#!kn;Q3qWcSCR}FkmiwQ$p~15cLp@O!N?%dWSaY z6zj9*ss)LxWwMGY&O2_ceb1kVuN7#tkIA0b-QVSu7i}kIh-$vYuipw!u6N(D!rvFA z4sfsnBU*m{8w4OZ7lll8aO#qpWbqj#wN>EmL{y0&Y_Um_H{JYo8TpWy!033MRLWRx zGDx~wr<-hYLcM0bLj&A=+)ct=gfQgMwR%@%Eitr^3 z`>9B*WxMdjA({WvfTqXEGT7D^Id11_DxPd-@zOLzHND*_S|6 zNWN9iWOtkds%hBkxO(fMoJV5m;sZ13-1;(x>i07FrsDtb8csk&R8m|M3WOsN-AZW> za)HXjWEoNwS}ItW+4Uk#ea9!jvp|LhP$ssX)H4(26Z9*Vj#^y1c{Vwn@+`PqOi?W>!DLL);q|1IeE4u8H&f9Y>NI{<{2rFw{ukL-qKW`0>qnc8ur zLJ}&D^rbVx-#>oby|!OV!IUF98 zV77tb8!^j2Xqmx!z!mgYmWlmJ{hZhS602R?8yuS+Bu3)%VyUcZa;n_kp6PxR>m{&D!+FTd`ROGmMfVi#XUSlk})rVwVQ-;+{n zMitA(Q>RM&3@OrKOHWwt0U4i+Gycc6;RWwZu+_#JDv@VXs$4T;WK%nq-gN^`W7i$S z@4i?NzWtkAt+zh5akey>IW152H0>$QTp~xYrZ6N|vk0*i6>4@I2IIG0r@cvyUM1c7 zz5Bk)0g}h$ot=^n(3}lwzmg#LG7dr5U}2{azqd_Je5WUE)7(UUz#c#O<4*jxR!|K5 zUj5_`&!|RL*B93vmcDUQIq_Xt{y1NX7I@Ac1{nMawq-}fW|~-0X3czj;7V!Y-yc*>SVzpc060fV*Sb_g z;q-+yhzN*TlrTp44HmDNFHoy6MiTdx71CiYE3^C%YrJgt-T2$x*U+8+!v4f`J6?mo zd3t&_TwUe8{%@`&!hS9z^Z9xYN$0Vn!xw+=ilz4WD)>Ag9`%^r@@U4t>v1ArGfrq@ z>|*4Tq~!3!f$V!G_YU{TIwU(K-Qs2(x)yX ztv;qT*Lz)Jg{h#`?NtmDkP_}5SvFzHVj2_FTTFyvz@Y#+9BsG9hjyn%Ru7;B{qMNI zwV=4qgsZetB>b(c*pXI6xHCNWIqZn|@F4XSzT#^og0bt;*Kc2HQZlo1#XqXzP=n-X zAIH)~M_*n@)YTy@hIJuo-f?zpgFL@hdUlrtil!{htP=FwJ*F9Q_eLTiDf`S1T`Cx# zJ{79qghuLOw&(TEmbQ=k;`vPd@(Z>LMIbFvQ(LuZDUz{B}-b#;jmDOp^R7@rG}S2*if!fp8s{;ZCJ zs_@*YwwYv=b9yiJ@NQVmj<)wgRD*SBH#05$<*ohWRvfy6>B-&^W#jXJ7Ty21Pf)&Gx{r9c5wNuLh}xJs#L zp<~E+u7?-SK;A;%z^*m`Bksd!VJs&+MM3!#cZxa4nW>kh#~YdwMS&n!3Nho-W`Srj zr|umXxCi^ax!!jM4A0}YcfHm)a)aE0I(Iau2j$MIyv0*Y9|7>gb<&T&p!|`F>Z`akH(g z92+z9b0KmY4p4fPYGfHt#-%e%Oh8<2iO9ac95k?LjV~U8z8QSyN!Rlsv|Xq!4;X~q z74jL~jn;d7vK4R9YdsPyD=Tk(u5JI#8oU!6T;2L$!q(~c(U_st{hD|YFdJ=a0b2h5 zxVdLT#Kj6T{%W7*o;EZ$b8~a|2L=NPJYEQriyC9NDQZeeO0FgsIPmDCz0M+WXlV6D z;`kDL{H`8xU+BDRtg{$$0bZR2R)g;Higu$9X*gO(U!rMowGJd~G!n7NVMV!EbJ(3E z#7WM4RxbBHuCK`(1*vptNxJO!5%$6K&C(?z9|#6?zSvr^>1SKY=Wjleeh%cd4#Cq= zY*3@X;fnh?cMKeHQ=*%OCpS02m&N+BiHXqEW+IS6-GxG8* z-0YI_y2zCC3H!fbmMX+@sL9n33JQ$>{Y#KMoBYsKqLx|SDKahVZ#}GNr7cZ_Maeou zUp`_s^I$Az$vH`U?j_P>ez6Dyc^*&jas9Spv>Ym{&{VKWv^oi^vvEivC@IF zx9oka8xXv-WWD|}1b%txjdwlI??j!%b@TMt8paH5(u|86$9Te2^IG+~{wn;uYx%fJ ze^v-74`pUE1P1yII7lZe?dg1LU6GkvAIJa1K=vLFysTFgUk(%Dyy?~h&{4z7i4J-aC(hpp~Sqk2V=~<6iU*9=G(1kk9JY5 zF0nEMQ_C|*6LHXi2NoEFez?*{Z>ChHij?TRvgw|O0Z`Sv-q`v_`p3cOV5P~wR?Eb> z>Fa!1I_VgOv0Wt|c>E7pEl8kTqM z{#+14HGRU%m+9QOaj>k_r}q0l*Dvz|wVnG^OxNxSM99=j1riiWf$8$MI6lLo+usUsnkFl*{3WJcMuwfQ)tB^C5ds_=dQD;sxJ!Q9t(UQm zez~@_>mzOM_=#Z4jNB|UKffIOynwWsRg}Er1Z8tXN%9Ma4WG{OTU8Nd3^1tkacd08=5pzi;t# zfw)@NlhgLwFZm9MtW$%Ef-PADW3`&E)}Vh6{-+xA(14q->eZJ!@ml$>tDft=)1iuO zT!iAwuJYPhDLY$4xM<|W^f3|^mdp)}o?mJf4*wm}#ZX3k#ADGJjb^voB0cxRuds{C zf3t(nf9-1~%*`k+rJXE#BWto>8`|2D{7cNU&y0F^vf8h-w8d-~kkA#{Nx)>`Wfqg| z&>A^o7l|!d?sYb(pK|csuUnx4q=*yta#)!E+w{O6jht*(Xu~&xyBPaqO?0FyShmIJ z)<%r;Gp{m%27mpz`4pYu>odH7(EGT-_mo*sLsIZ=+V_f?1D zzt*_$d6-gA=?o~1((3qd09rywPF!wjM5%z#$8VPvXkit@*1pK~FI-cEJwN z&G2#akzf3U{NngrKW*z8Nrw>?7npHgSl|rd5cK=5}2AvD0U1`-A;T+1dH=+>f`H zgR{Bg`I@<7Hl1R}MYmF!0^~v7Sf>W_j5aNne|}A0yB&6Tp0bX4kMus5Cu?U^utI0z zPOWBndHSY)7<9Rm8Z`N3o}He~fBg7e(2&7~a%#b#Szb47>eSx5(`68AZEm`DWkuJ` zF(AKdcZT`)Dz(b3tF%BpuRNVazmogNEomTFxqMb|uXULtc_VrduhVS_3H1>6W3+p1 z=~v|8IR~cVP7Rp@7uZuD>sd|N|KqP)u zZf#A8VxQ5(%lgf?q5)2FC9Yh3;vjJn-@S0E5;+tv7x?M3;ol`agZ8qA^~cPKcNFPavGzbmHk&`1*$Z;k^xyRX6Z}Ut^5+PhPGV-)Q=+Vo52^B5zhvca^}>^h4Nd)Aus(9w zxiaTvwkE(}yO4NR-AL{iMy?sC<6YR^v)n_>zsdt~0S4N3- z*}5`d(@U{{p3N%#8LHNqAIdUkwc7}YN~|Lya~fUN%+W}+^o&XZEDA(he+YaQa5KwMTBbt?koFhEpPob|)781Q>)1!l5fB+qJILRgUvV_8 z)fmK~1Ly<8O{^s;kwK9dqry^e3gf-?SRY!o!Vb0kMI(wlJKCV9JvEo$Y{$Z8Nc7Q_ zwq3hirz-6f;gIZ@l|5hKhwlVsz>5%Dl0Gvxi#iTQg0W5sUVMBiG1zX+2V)j5hk#_S z)lhi2ZLiacQQntv`Ksn*#W$y73F*A!;M~gb)M#&6Q9#H)4eIMVx;OK3l>bi1YHz;_ zsj=(2MCE6U_vxp%`jo=#Ug;lOuqo)Up7vXGT35wZkva9zyG(KRlfP2URf|JGg17TcwvZq|F>}f9Uk6LhLs;}qRJtn3Og%i8>+_i!I=qF4NC@Z zmK&8s7CVfKvMm$IaA{EuLrM^UnJE2h#8{}~2$gTt9Ok9LXLtUcivktop${`T>+*(m zMeUtCX5T~?eKuY9K31sokF#ah9SwLt&cB+zH-wIuh2p8yAEzR&dpt{<&9b80#HgX^ z%g9W+yrUZ!-6oMxp{XiRgd}pvW{2^YS?7_9(OJ|2wryn=%7-Do?mu}V?MvO~^aNDF zHXdDn#Me{R4g$pJtNZv9HD=VP{lD&AR=Oq>7E0PY{@XBF!zE?WS%gZWzfjN4($=KN9MVyY}9*!m`f zUr@0*bUO`X7)Sj$&h=9n^+P4=clKd?$5+G5zloW+(h&NFniI|ZdQF+K4VGF!`0e}cqm zcm&OpYnhbid00bnQsqoDKkL96(RjB9iZdls{^W}&LSWzH6j3jyJy%6Xc@hLy;^wO- zQ-(D}z=R&@$eCkPYjt{25^r4KbveH;Ofyk^bJKF}<+?jrL(DMKMRL0><^S$N5HfN0 zO5L&527qnjsg#n{)p^o9h&7JM`sx=&_4e-H;^#;{YnuB2h3X^dqdui$ivwzWhZj3CtLy>tg&C%=gXtG< z_ucWLugRiYwJYZ(#pSUd!{c@`81wvXkndm8+dpWv`H+qzv}QWjw^EhI=TmLy(BxkI zOu_DLa1&H4HIPJ>_C5oN*lS}%Nhk)kW@0ri3&Vtx!^zb+*&!Q8(2$Fn5)z@rrX_fY zlxR*w`ov5T(Vt?-s;Z~W$P8f?qBx`A*bfZF&Q6rCet(XYbiex zr(#+e7hxXq4}ees(V<|{-=C`ExS2%RG$~P6dQuhwErS_;%G^_^t~~L@l63TRm1Zox ze%@g&HA6F{P<~F(_(4}|XzaIn0Y8}_++mMUEQxLlmtv}%|e zK2ChEoz{IEWoNQ>Yn&say__(t71F=2y@J2ft6c2Ct6+u7w`G&q!O$kt<4CKzk`*1E z9V_UpI?LIzm1TJR=2}~Idd_aOQq7B$$?AT7YECeoQnE$u@0Z0(Z z=6zbm@6qdLRe!{5JO0gVMhv2bzzPtP_k$>%m8rxe|Un2yw*6(?F7sg*@Go~#T~oO{;V8xD~ttm+Dk7Ek|gi8>t|} zn=K`Ku-dlBP4;SoGRRaAu$nd~Xu$SU^tdaPq&(aT`uEdc5L;DPKYUiO z^=WIbNQJhPnHA7a`0;F$Ix0K&>*^fp?bbUrP9&xB>iYA>@0Dg&GPn>%+prF~*?k#> zJ3TuRm*z~hNu8H~Q=d;%m|ZZwxS7YN?W;Fy&FTEbR0d+oh*AseIaVtW#u)TR`hfv zhmQjur{pbrKK5{i{eeSae3m1lYuwJ8yAp46rzDC9D>@_si>o_299?mOr&XtZFhc*< z?gfUTk1m25GRITx@HmT^aaC{OPJfBIfQ)RossgpCykP)wo#D>k3eK`J8$CZ`A;L)$ zleV~n%;$a%|6LyGgo+A6(=N3^XSH#q3AMbc?QkBY{vm6LyhgQ-Q~h%@2bZASb~F=W z)IOWY_<$Gn>aIhR_3J+?^6k73NV1zJZUv8xmqFOuTj+?E3Bt!xz)2{95dD}*NFr;r z$XhNm6qz~zqD&txYADmGNmTGYq*G_@wQSwJB5asRVg6dgK$kwTRchDAQ6wxHZ{KdF zMr2Gho<1g}Dp#jv^@q=-at{!$X5Mwo=g;OdjIq9`lq4U0u(P~agzd;V@}<9V)m zeK=<8%=m^zwpS&(I4a_3Fxpe^-*s6rxcUnJ-ZQ)&z^Yl9{`|(!AJFbd?78NH8LF4K zuG~92sfgq-P``&?-_k7hb?K&oh(*_%^7RxhxPMm9du>hl^*Z0_>E@G#x;bB3y#PEW zK$!~%FX&6+3^E{Q`XS3j8Vi=xladJe$GB9?G!*h)7Q-px-~Qey?Hoa9_(CGWJGRX8 zorDC30hjn!D_msIrXMEc_oQ)`9{snGA59rKF_CTWfegUTLsi z&kdW&DbAQ)Y6daNRGx&-X>H()FDlF5%>t%e`6fYZ?7vBO44O?DiqT#XbWG+x4w@*6 zRF^Dbii){^w?0J(=nOTH=6!~M!TjJnIgVD91e51I)?OFvW4VpS^67xbgcV8?M_YUR za(vG04-3l&o;Dk{E}{?{MZjSp98qV4mr_&zC2a*;)B0cO>_FW>1IT)^|4)X-YetS~ zL5lct{e^pyDYXe#Q;)U(f=i=94UQ`7V8cFG4@%2Hi-)C-fI=-bK&ghzlISE>U%^uI zJr|hD7zEsYB_Yczt{MDb($?M{X+zsb(JGn@F@GD*?+E|SZciQK-+TB#a^LYRL-u%? z{6m~=Vdx(%+A}(n#er>1+#i?Wp+Tj|<&;XyVKh=8mX_n@5t~UI2PCjBUaY+Nt&Sz| zzzYEvLzm5%z-TF9!mJ|IHc}wYoJz_CVW@8Cw-U=rX#(HxP8^tNP;!)^Zq#1Oo$vAO z&x54ss9klu_Pe}7F41^f#H&G=Ih&8AJm2&?BeQwCBV)7K%spzy&%k;1Ba2zW{9{YUKA^v`t=7_S670jUI2F}ULa%=An+D?S&amnXHVaq+_sb%TDS{ud7h28-NdCmkgx$a&t@G3B0l+b2?y zGM(a$Ix)f#I3_LUG0k ze~aam^U2D8HODSJGU>BMtvF~;)?p4_Txf@I+)Jw_nRNbxv$nN;{7wkpxnQ8VnRyWY z^BD>H33sqsuQ9_^vKSN;K^yJkjQX&R-!0atY5oprc2;$frrO&fCPz>kyu?tyW zXS1+8;OFM*y%-@RiY<7QXeWRRNt8l}HP8Gco?(ac!8m8+kmk!CoxK_pN`GIyU4xn& zF16ent4?7G4Z`*=k%h?(;UK3tL1E(%C%EMA02o$kr71EyB+FImjX^;PbbKqQ&|AO9 zoROVN7e{Rel_`n{#;C#7p}$JgIg--pmcJJnF5!L)&D`})?Jkq9JAaPk^2Xu0HBDwX ze>PVCJWPS$r%+17{G{{c8e*rHURtw8c^U@JQQaOa2g%_;)9;*)whPS&$C5o-sm#a@wSN&6CPc0UGJH)Fg z_I$iDVXz^Oku^L2{f87KFD0&lX?!v@H=P+V-zr`Ih$h%BG=h(0c3oqJ1gv2^fEewd zW1j&mEFyS2DT-clih~QM~kSC@tZlkn2he%jg@A5 z8gpO$F*=%vXwpZSa0mI*B4^ByNL}=&DVkGem@?MOj!V*bmQ!*$1AQIduPmW zz!gI-GTY`^`^K2-q{B`+yRgIO0l)1cZIl0`SNUFa4%B^miA8om^b4 zKMf6C`-)_NOKWGs_0Gc}0TBubWow<8UC8z+$CsGR;p8vQ7K%gXiia zvEFYN!u+=?6>9U5^7p6N-RL#HtI78m7k4U}uQ1l93zjaUfwr8lNWDODQVDPq6V zzs#8z+iGzO3yZHcWM3+^s&$f#y&4oSY-R|<*V@s3+fK^+-?KtnO~i96G7}VvN8;=! z6Gw4dPSdh4gMXC!Kk>sM8V`bCtdy+g)zfL1AZ-eD<tBov1r>aiQgwax0j1?`wN)lr@;X>yoN=bJR-mlhG#Vrx z5#DU{C%xPxoMY!zlHmTwk(n2eDvml6?al04mqAg%pMUP1<4UJeQ8;m#ZbvMi(o8WC z1M!edz+;Nj>!(y9v49m4{G)Y=u#bWwPSU1s0G&r%(sY>!J}_ND7?_*WoeGB3$z(+7 zfK@9G_j|zk-vs38{zj^F%Fs{Z;?ufA_<5(8S{ayZg+A?`7w2T*d>rxI@{zaCD zgXz+H>rbz5bFH%?6GDtBIDoHEV{B))!jwd$Dc^035&=i_WedHIC7a?W@9bm-gR%`i zNXj{cHVIT&-YjJ2c;LXrsCx^+|zo*e!1y>G#ku^7^A? zRFqtTq2Jswv9UXmCA2=5VTz+AGbf@gR+-i)C5DE~b`9M-M^l3W+R-pe2*99p0N^!oRGc60p zvdLt#OpcAAg^80Agi(ZPCaq(~F;G(f3!5*SD2&cW5&+wB@PiC*@|4WlcJ5AmfNwH+@>dBm$bkAeGLN%Xk#q z+sQZ+$XMce7PjdU1W8^G;CjjCaZQ74+J!jAPzEA0$(SylX_3zupd(7N0o76&g9z76 zlTLYKVd$4l8-+@EB$l1LxEP8k3^7czdD17RzU`Vx`yB(N68MKQWMd8_xjSGfBcK_zkN^3nV0t; zK`KyMHBUu@XP^2mANz}Y*}3-!rbsv=^=g$!3Z&HdejP96k3LH(M*hNKmDqleYCa6mL@* z-n0akVPaSbtUitfnvgJ%C>>)pabQl$R+bjzTk_FZoPh49<#C?!*Vea$W3%tVD;+Ck}Nmx$y$$0}&@wKXb^*m^Qz-dgmtXSYxNptU9c z)X}4-C-~oViP!R>fd!dwVr1`}nX7arR#J&lL@u8qiX~nu#qFD4N6_%Yr+=}ttWf1J z4C@jd8ip0ymc?zi+{lwZeF|SH;wU5zlhMA8C9dNVgaO*H&^p4jk`vf4ZG7LyG^}Q! z+ho}p*7>lmWQ-;W?WSd)cfC?g%PYea2?WG8QPRZFF+shagxW;wSn1>>QLP29-rwIh z=A`WBI@;Qwy5{ODCO-1f`{I9Z5A9oj`^f_%+a6uh#Su&k3}Itf0?QV}N@6)F0$(zD zw#=G~deB{h3IB#qzW0ys|MX(jy zL}O5{1@yG1iTp-**`-%p^@GQ@@A?|$o=m-Zie;q2L&qF)b?GDahC z9Rttx@G@!UN+p6Q;&*@h-A`O~$&z=x{oNlf{XboA<+5cPr%R<5ln_LI()}|H&{87K z4J?(SrI4emyXB+Xw(a}Wf0lb~{Q7nKkGH=5ogW<(ra57m0wH2d8-yVV!T_lymTBTS z4k_DV%L`k+^1s>~0PUTvs{p$_# zA9TrBj>J)nZrX*}mW|mY{UlIu(bRql)T>>~_1vm$TCwMOiH4MwaAOj^sKkFo(`+3p zUH|n4`StpDzdAZQ-h$SHg?z3YM|`>TDgzxv|OxR&^uA^2KPSN=;M{U7h! ic +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER +#include "fsl_lpflexcomm.h" +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ +#include "fsl_spc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* attach 12 MHz clock to FLEXCOMM4 (debug console) */ + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); + CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); + + RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST); + + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER + LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART); +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) +{ + lpi2c_master_config_t lpi2cConfig = {0}; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); +} + +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Read; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + return LPI2C_MasterTransferBlocking(base, &xfer); +} + +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize); +} + +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t status; + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = NULL; + xfer.dataSize = 0; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + + if (kStatus_Success == status) + { + xfer.subaddressSize = 0; + xfer.direction = kLPI2C_Read; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + status = LPI2C_MasterTransferBlocking(base, &xfer); + } + + return status; +} + +void BOARD_Codec_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); +} + +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); +} + +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* Update Active mode voltage for OverDrive mode. */ +void BOARD_PowerMode_OD(void) +{ + spc_active_mode_dcdc_option_t opt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); + + spc_sram_voltage_config_t cfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &cfg); +} diff --git a/boards/frdmmcxn236/project_template/board.h b/boards/frdmmcxn236/project_template/board.h new file mode 100644 index 000000000..bbe9874ae --- /dev/null +++ b/boards/frdmmcxn236/project_template/board.h @@ -0,0 +1,179 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "FRDM-MCXN236" + +/*! @brief The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART4 +#define BOARD_DEBUG_UART_INSTANCE 4U +#define BOARD_DEBUG_UART_CLK_FREQ 12000000U +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4 +#define BOARD_DEBUG_UART_RST kFC4_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC kCLOCK_FlexComm4 +#define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM4_IRQHandler +#define BOARD_UART_IRQ LP_FLEXCOMM4_IRQn + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#endif + +#define BOARD_CODEC_I2C_BASEADDR LPI2C2 +#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000 +#define BOARD_CODEC_I2C_INSTANCE 2 + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO4 +#endif +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 18U +#endif + +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO4 +#endif +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 17U +#endif + +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO4 +#endif +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 19U +#endif + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO0 +#endif +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 20U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW2_IRQ GPIO00_IRQn +#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO0 +#endif +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 6U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ GPIO00_IRQn +#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED_RED_INIT(output) \ + GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ + BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ +#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ +#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ +#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ + +#define LED_BLUE_INIT(output) \ + GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ + BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ +#define LED_BLUE_ON() GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ +#define LED_BLUE_OFF() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ +#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ + BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ +#define LED_GREEN_ON() GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ +#define LED_GREEN_OFF() GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ +#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ + + +/* ERPC LPSPI configuration */ +#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1) +#define ERPC_BOARD_LPSPI_BASEADDR LPSPI3 +#define ERPC_BOARD_LPSPI_BAUDRATE 500000U +#define ERPC_BOARD_LPSPI_CLKSRC kCLOCK_Flexcomm3 +#define ERPC_BOARD_LPSPI_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(1) +#define ERPC_BOARD_LPSPI_INT_GPIO GPIO0 +#define ERPC_BOARD_LPSPI_INT_PIN 16U +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ PIN_INT0_IRQn +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER PIN_INT0_IRQHandler + +/* ERPC LPI2C configuration */ +#define ERPC_BOARD_LPI2C_BASEADDR LPI2C0_BASE +#define ERPC_BOARD_LPI2C_BAUDRATE 100000U +#define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm0 +#define ERPC_BOARD_LPI2C_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(2) +#define ERPC_BOARD_LPI2C_INT_GPIO GPIO1 +#define ERPC_BOARD_LPI2C_INT_PIN 0U +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ PIN_INT1_IRQn +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz); +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); +void BOARD_Codec_I2C_Init(void); +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +void BOARD_PowerMode_OD(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/boards/frdmmcxn236/project_template/clock_config.c b/boards/frdmmcxn236/project_template/clock_config.c new file mode 100644 index 000000000..97c812891 --- /dev/null +++ b/boards/frdmmcxn236/project_template/clock_config.c @@ -0,0 +1,448 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v12.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.3 +board: FRDM-MCXN236 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 12000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + /*!< Set up clock selectors */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 48000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF144M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 144 MHz} +- {id: MAIN_clock.outFreq, value: 144 MHz} +- {id: Slow_clock.outFreq, value: 36 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: RunPowerMode, value: OD} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.FIRC.outFreq, value: 144 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF144M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 144000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 150 MHz} +- {id: PLL0_CLK_clock.outFreq, value: 150 MHz} +- {id: Slow_clock.outFreq, value: 37.5 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: RunPowerMode, value: OD} +- {id: SCGMode, value: PLL0} +- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true} +- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M} +- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CLK_IN_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 100 MHz} +- {id: PLL1_CLK_clock.outFreq, value: 100 MHz} +- {id: Slow_clock.outFreq, value: 25 MHz} +- {id: System_clock.outFreq, value: 100 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: RunPowerMode, value: SD} +- {id: SCGMode, value: PLL1} +- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true} +- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true} +- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SCG_SOSCCSR_ERFES_SEL, value: CryOsc} +- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.1 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_NormalVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.1 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.1V voltage level and 100000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the 1.1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P1V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupExtClocking(24000000U); + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + /*!< Set up PLL1 */ + const pll_setup_t pll1Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U), + .pllndiv = SCG_SPLLNDIV_NDIV(6U), + .pllpdiv = SCG_SPLLPDIV_PDIV(2U), + .pllmdiv = SCG_SPLLMDIV_MDIV(100U), + .pllRate = 100000000U + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +} + diff --git a/boards/frdmmcxn236/project_template/clock_config.h b/boards/frdmmcxn236/project_template/clock_config.h new file mode 100644 index 000000000..eb259a85c --- /dev/null +++ b/boards/frdmmcxn236/project_template/clock_config.h @@ -0,0 +1,177 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ +#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ +#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF144M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ +#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ +#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/boards/frdmmcxn236/project_template/peripherals.c b/boards/frdmmcxn236/project_template/peripherals.c new file mode 100644 index 000000000..75d5ffba1 --- /dev/null +++ b/boards/frdmmcxn236/project_template/peripherals.c @@ -0,0 +1,99 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v13.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.5 +functionalGroups: +- name: BOARD_InitPeripherals + UUID: fbea44e1-da40-4200-8454-ce9165488681 + called_from_default_init: true + selectedCore: cm33_core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ + /* Initialize components */ +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/boards/frdmmcxn236/project_template/peripherals.h b/boards/frdmmcxn236/project_template/peripherals.h new file mode 100644 index 000000000..ead2693b4 --- /dev/null +++ b/boards/frdmmcxn236/project_template/peripherals.h @@ -0,0 +1,39 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/boards/frdmmcxn236/project_template/pin_mux.c b/boards/frdmmcxn236/project_template/pin_mux.c new file mode 100644 index 000000000..eeea71d20 --- /dev/null +++ b/boards/frdmmcxn236/project_template/pin_mux.c @@ -0,0 +1,382 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v14.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.0 +board: FRDM-MCXN236 +external_user_signals: {} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: A1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/FLEXIO0_D16/I3C1_SDA/ADC1_A8, + slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable, + invert_input: normal} + - {pin_num: B1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/FLEXIO0_D17/I3C1_SCL/ADC1_A9, slew_rate: fast, + open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for PORT1: Enables clock */ + CLOCK_EnableClock(kCLOCK_Port1); + + const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as FC4_P0 */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT1_8 (pin A1) is configured as FC4_P0 */ + PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config); + + const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as FC4_P1 */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT1_9 (pin B1) is configured as FC4_P1 */ + PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: A16, peripheral: SWD, signal: SWCLK, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, + pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: A17, peripheral: SWD, signal: SWDIO, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, pull_select: up, + pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: B16, peripheral: SWD, signal: SWO, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, drive_strength: high, + pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for PORT0 controller: Enables clock */ + CLOCK_EnableClock(kCLOCK_Port0); + + const port_pin_config_t port0_0_pinA17_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* High drive strength is configured */ + kPORT_HighDriveStrength, + /* Pin is configured as SWDIO */ + kPORT_MuxAlt1, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_0 (pin A17) is configured as SWDIO */ + PORT_SetPinConfig(PORT0, 0U, &port0_0_pinA17_config); + + const port_pin_config_t port0_1_pinA16_config = {/* Internal pull-down resistor is enabled */ + kPORT_PullDown, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as SWCLK */ + kPORT_MuxAlt1, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_1 (pin A16) is configured as SWCLK */ + PORT_SetPinConfig(PORT0, 1U, &port0_1_pinA16_config); + + const port_pin_config_t port0_2_pinB16_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* High drive strength is configured */ + kPORT_HighDriveStrength, + /* Pin is configured as SWO */ + kPORT_MuxAlt1, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_2 (pin B16) is configured as SWO */ + PORT_SetPinConfig(PORT0, 2U, &port0_2_pinB16_config); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: R9, peripheral: GPIO4, signal: 'GPIO, 17', pin_signal: PIO4_17/TRIG_IN9/FC2_P3/USB1_OTG_OC/CT3_MAT1/FLEXIO0_D25/ADC0_B6, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: N10, peripheral: GPIO4, signal: 'GPIO, 18', pin_signal: PIO4_18/CT3_MAT2/FLEXIO0_D26, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, + pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: R10, peripheral: GPIO4, signal: 'GPIO, 19', pin_signal: PIO4_19/TRIG_OUT5/CT3_MAT3/FLEXIO0_D27/ADC0_B1/CMP1_IN4P, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for PORT4: Enables clock */ + CLOCK_EnableClock(kCLOCK_Port4); + + const port_pin_config_t port4_17_pinR9_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as PIO4_17 */ + kPORT_MuxAlt0, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT4_17 (pin R9) is configured as PIO4_17 */ + PORT_SetPinConfig(PORT4, 17U, &port4_17_pinR9_config); + + const port_pin_config_t port4_18_pinN10_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as PIO4_18 */ + kPORT_MuxAlt0, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT4_18 (pin N10) is configured as PIO4_18 */ + PORT_SetPinConfig(PORT4, 18U, &port4_18_pinN10_config); + + const port_pin_config_t port4_19_pinR10_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as PIO4_19 */ + kPORT_MuxAlt0, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT4_19 (pin R10) is configured as PIO4_19 */ + PORT_SetPinConfig(PORT4, 19U, &port4_19_pinR10_config); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: C14, peripheral: GPIO0, signal: 'GPIO, 6', pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/PDM0_DATA1/CLKOUT, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: C8, peripheral: GPIO0, signal: 'GPIO, 20', pin_signal: PIO0_20/WUU0_IN4/FC0_P4/FC1_P0/CT_INP0/FLEXIO0_D4/I3C0_SDA/ADC0_A12, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for PORT0 controller: Enables clock */ + CLOCK_EnableClock(kCLOCK_Port0); + + const port_pin_config_t port0_20_pinC8_config = {/* Internal pull-up/down resistor is disabled */ + kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as PIO0_20 */ + kPORT_MuxAlt0, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_20 (pin C8) is configured as PIO0_20 */ + PORT_SetPinConfig(PORT0, 20U, &port0_20_pinC8_config); + + const port_pin_config_t port0_6_pinC14_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Pin is configured as PIO0_6 */ + kPORT_MuxAlt0, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_6 (pin C14) is configured as PIO0_6 */ + PORT_SetPinConfig(PORT0, 6U, &port0_6_pinC14_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/frdmmcxn236/project_template/pin_mux.h b/boards/frdmmcxn236/project_template/pin_mux.h new file mode 100644 index 000000000..c2e55e6d9 --- /dev/null +++ b/boards/frdmmcxn236/project_template/pin_mux.h @@ -0,0 +1,134 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! @name FC4_P0 (coord A1), P1_8/J5[12] + @{ */ +/* @} */ + +/*! @name FC4_P1 (coord B1), P1_9/J5[11] + @{ */ +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/*! @name SWCLK (coord A16), P0_1/SWCLK/JP8[2] + @{ */ +/* @} */ + +/*! @name SWDIO (coord A17), P0_0/SWDIO + @{ */ +/* @} */ + +/*! @name SWO (coord B16), P0_2/SWO + @{ */ +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); + +/*! @name PIO4_17 (coord R9), P4_17/J4[8] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO4 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 17U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 17U) /*!<@brief GPIO pin mask */ +/* @} */ + +/*! @name PIO4_18 (coord N10), P4_18/J22[1] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO4 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 18U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +/* @} */ + +/*! @name PIO4_19 (coord R10), P4_19/J6[11] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO4 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 19U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); + +/*! @name PIO0_6 (coord C14), P0_6/J12[7] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 6U /*!<@brief GPIO pin number */ +#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */ +/* @} */ + +/*! @name PIO0_20 (coord C8), P0_20/J1[6]/J6[8] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 20U /*!<@brief GPIO pin number */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 20U) /*!<@brief GPIO pin mask */ +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/frdmmcxn236/set_board_frdmmcxn236.cmake b/boards/frdmmcxn236/set_board_frdmmcxn236.cmake new file mode 100644 index 000000000..2073bef7f --- /dev/null +++ b/boards/frdmmcxn236/set_board_frdmmcxn236.cmake @@ -0,0 +1,31 @@ +include_guard(GLOBAL) + + +if (CONFIG_USE_BOARD_Project_Template_frdmmcxn236) +# Add set(CONFIG_USE_BOARD_Project_Template_frdmmcxn236 true) in config.cmake to use this component + +message("BOARD_Project_Template_frdmmcxn236 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_lpuart_adapter AND CONFIG_USE_driver_lpuart AND CONFIG_USE_driver_lpi2c AND CONFIG_USE_driver_gpio AND CONFIG_USE_driver_reset AND CONFIG_USE_driver_clock AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_device_MCXN236_startup AND (CONFIG_BOARD STREQUAL frdmmcxn236) AND ((CONFIG_USE_utility_debug_console AND CONFIG_USE_component_serial_manager AND CONFIG_USE_driver_port))) + +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.h "" BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.c "" BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.c "" BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.c "" BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.h ${CMAKE_CURRENT_LIST_DIR}/project_template/. BOARD_Project_Template_frdmmcxn236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.c "" BOARD_Project_Template_frdmmcxn236) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/project_template/. +) + +else() + +message(SEND_ERROR "BOARD_Project_Template_frdmmcxn236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + diff --git a/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c b/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c index ace5738f0..a2c86fc87 100644 --- a/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c +++ b/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c @@ -25,7 +25,7 @@ (defined(RTE_I2C4) && RTE_I2C4 && defined(LPI2C4)) || (defined(RTE_I2C5) && RTE_I2C5 && defined(LPI2C5)) || \ (defined(RTE_I2C6) && RTE_I2C6 && defined(LPI2C6))) -#define ARM_LPI2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (2)) +#define ARM_LPI2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (4)) /* * ARMCC does not support split the data section automatically, so the driver @@ -70,11 +70,11 @@ typedef struct _cmsis_lpi2c_interrupt_driver_state #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) typedef const struct _cmsis_lpi2c_edma_resource { - DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for Tx. */ + void *txEdmaBase; /*!< EDMA peripheral base address for Tx. */ uint32_t txEdmaChannel; /*!< EDMA channel for Tx */ uint16_t txDmaRequest; /*!< Tx EDMA request source. */ - DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for Rx. */ + void *rxEdmaBase; /*!< EDMA peripheral base address for Rx. */ uint32_t rxEdmaChannel; /*!< EDMA channel for Rx */ uint16_t rxDmaRequest; /*!< Rx EDMA request source. */ #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) @@ -168,9 +168,9 @@ static int32_t LPI2C_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis #if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX EDMA_SetChannelMux(lpi2c->edmaResource->txEdmaBase, lpi2c->edmaResource->txEdmaChannel, - lpi2c->edmaResource->txDmaRequest); + (int32_t)lpi2c->edmaResource->txDmaRequest); EDMA_SetChannelMux(lpi2c->edmaResource->rxEdmaBase, lpi2c->edmaResource->rxEdmaChannel, - lpi2c->edmaResource->rxDmaRequest); + (int32_t)lpi2c->edmaResource->rxDmaRequest); #endif /* Create master_edma_handle */ LPI2C_MasterCreateEDMAHandle(lpi2c->resource->base, lpi2c->master_edma_handle, lpi2c->edmaRxHandle, diff --git a/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.h b/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.h index 385daa89a..baf9467e5 100644 --- a/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.h +++ b/cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.h @@ -18,8 +18,8 @@ * limitations under the License. */ -#ifndef _FSL_LPI2C_CMSIS_H_ -#define _FSL_LPI2C_CMSIS_H_ +#ifndef FSL_LPI2C_CMSIS_H_ +#define FSL_LPI2C_CMSIS_H_ #include "fsl_common.h" #include "Driver_I2C.h" @@ -68,4 +68,4 @@ extern ARM_DRIVER_I2C Driver_I2C6; #define I2C_FLAG_INIT (1UL << 0) #define I2C_FLAG_POWER (1UL << 1) -#endif /* _FSL_LPI2C_CMSIS_H_ */ +#endif /* FSL_LPI2C_CMSIS_H_ */ diff --git a/cmsis_drivers/lpspi/fsl_lpspi_cmsis.c b/cmsis_drivers/lpspi/fsl_lpspi_cmsis.c index 42c59448c..a4705910d 100644 --- a/cmsis_drivers/lpspi/fsl_lpspi_cmsis.c +++ b/cmsis_drivers/lpspi/fsl_lpspi_cmsis.c @@ -29,7 +29,7 @@ (defined(RTE_SPI2) && RTE_SPI2 && defined(LPSPI2)) || (defined(RTE_SPI3) && RTE_SPI3 && defined(LPSPI3)) || \ (defined(RTE_SPI4) && RTE_SPI4 && defined(LPSPI4)) || (defined(RTE_SPI5) && RTE_SPI5 && defined(LPSPI5))) -#define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (6)) /* driver version */ +#define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (9)) /* driver version */ /* * ARMCC does not support split the data section automatically, so the driver @@ -66,11 +66,11 @@ typedef struct _cmsis_lpspi_interrupt_driver_state #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) typedef const struct _cmsis_lpspi_edma_resource { - DMA_Type *txEdmaBase; + void *txEdmaBase; uint32_t txEdmaChannel; uint16_t txDmaRequest; - DMA_Type *rxEdmaBase; + void *rxEdmaBase; uint32_t rxEdmaChannel; uint16_t rxDmaRequest; @@ -565,8 +565,8 @@ static int32_t LPSPI_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpspi_edma_dr EDMA_CreateHandle(lpspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); EDMA_CreateHandle(lpspi->edmaTxDataToTxRegHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel); #if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX - EDMA_SetChannelMux(dmaResource->txEdmaBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest); - EDMA_SetChannelMux(dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); + EDMA_SetChannelMux(dmaResource->txEdmaBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest); + EDMA_SetChannelMux(dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest); #endif #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) @@ -1450,8 +1450,8 @@ static cmsis_lpspi_resource_t LPSPI1_Resource = {LPSPI1, 1, LPSPI1_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI1_EdmaResource = { - RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_PERI_SEL, - RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_PERI_SEL, + RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, (uint16_t)RTE_SPI1_DMA_TX_PERI_SEL, + RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, (uint16_t)RTE_SPI1_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_RX_DMAMUX_BASE, #endif @@ -1620,8 +1620,8 @@ static cmsis_lpspi_resource_t LPSPI2_Resource = {LPSPI2, 2, LPSPI2_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI2_EdmaResource = { - RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_PERI_SEL, - RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_PERI_SEL, + RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, (uint16_t)RTE_SPI2_DMA_TX_PERI_SEL, + RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, (uint16_t)RTE_SPI2_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI2_DMA_TX_DMAMUX_BASE, RTE_SPI2_DMA_RX_DMAMUX_BASE, #endif @@ -1790,8 +1790,8 @@ static cmsis_lpspi_resource_t LPSPI3_Resource = {LPSPI3, 3, LPSPI3_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI3_EdmaResource = { - RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_TX_PERI_SEL, - RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, RTE_SPI3_DMA_RX_PERI_SEL, + RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, (uint16_t)RTE_SPI3_DMA_TX_PERI_SEL, + RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, (uint16_t)RTE_SPI3_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI3_DMA_TX_DMAMUX_BASE, RTE_SPI3_DMA_RX_DMAMUX_BASE, #endif @@ -1960,8 +1960,8 @@ static cmsis_lpspi_resource_t LPSPI4_Resource = {LPSPI4, 4, LPSPI4_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI4_EdmaResource = { - RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, RTE_SPI4_DMA_TX_PERI_SEL, - RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH, RTE_SPI4_DMA_RX_PERI_SEL, + RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, (uint16_t)RTE_SPI4_DMA_TX_PERI_SEL, + RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH, (uint16_t)RTE_SPI4_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI4_DMA_TX_DMAMUX_BASE, RTE_SPI4_DMA_RX_DMAMUX_BASE, #endif @@ -2130,8 +2130,8 @@ static cmsis_lpspi_resource_t LPSPI5_Resource = {LPSPI5, 5, LPSPI5_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI5_EdmaResource = { - RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, RTE_SPI5_DMA_TX_PERI_SEL, - RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH, RTE_SPI5_DMA_RX_PERI_SEL, + RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, (uint16_t)RTE_SPI5_DMA_TX_PERI_SEL, + RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH, (uint16_t)RTE_SPI5_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI5_DMA_TX_DMAMUX_BASE, RTE_SPI5_DMA_RX_DMAMUX_BASE, #endif @@ -2300,8 +2300,8 @@ static cmsis_lpspi_resource_t LPSPI6_Resource = {LPSPI6, 6, LPSPI6_GetFreq}; #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) static cmsis_lpspi_edma_resource_t LPSPI6_EdmaResource = { - RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, RTE_SPI6_DMA_TX_PERI_SEL, - RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH, RTE_SPI6_DMA_RX_PERI_SEL, + RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, (uint16_t)RTE_SPI6_DMA_TX_PERI_SEL, + RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH, (uint16_t)RTE_SPI6_DMA_RX_PERI_SEL, #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) RTE_SPI6_DMA_TX_DMAMUX_BASE, RTE_SPI6_DMA_RX_DMAMUX_BASE, #endif diff --git a/cmsis_drivers/lpspi/fsl_lpspi_cmsis.h b/cmsis_drivers/lpspi/fsl_lpspi_cmsis.h index 534d39997..c2f0e1dad 100644 --- a/cmsis_drivers/lpspi/fsl_lpspi_cmsis.h +++ b/cmsis_drivers/lpspi/fsl_lpspi_cmsis.h @@ -18,8 +18,8 @@ * limitations under the License. */ -#ifndef _FSL_LPSPI_CMSISI_H_ -#define _FSL_LPSPI_CMSISI_H_ +#ifndef FSL_LPSPI_CMSISI_H_ +#define FSL_LPSPI_CMSISI_H_ #include "fsl_common.h" #include "RTE_Device.h" diff --git a/cmsis_drivers/lpuart/fsl_lpuart_cmsis.c b/cmsis_drivers/lpuart/fsl_lpuart_cmsis.c index 23bf1fc9d..c74b25156 100644 --- a/cmsis_drivers/lpuart/fsl_lpuart_cmsis.c +++ b/cmsis_drivers/lpuart/fsl_lpuart_cmsis.c @@ -204,7 +204,7 @@ (defined(RTE_USART5) && RTE_USART5 && defined(LPUART5)) || \ (defined(RTE_USART6) && RTE_USART6 && defined(LPUART6))) -#define ARM_LPUART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (4)) +#define ARM_LPUART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (5)) /* * ARMCC does not support split the data section automatically, so the driver @@ -265,11 +265,11 @@ typedef struct _cmsis_lpuart_dma_driver_state #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) typedef struct _cmsis_lpuart_edma_resource { - DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for TX. */ + void *txEdmaBase; /*!< EDMA peripheral base address for TX. */ uint32_t txEdmaChannel; /*!< EDMA channel for LPUART TX. */ uint32_t txDmaRequest; /*!< TX EDMA request source. */ - DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for RX. */ + void *rxEdmaBase; /*!< EDMA peripheral base address for RX. */ uint32_t rxEdmaChannel; /*!< EDMA channel for LPUART RX. */ uint32_t rxDmaRequest; /*!< RX EDMA request source. */ diff --git a/cmsis_drivers/lpuart/fsl_lpuart_cmsis.h b/cmsis_drivers/lpuart/fsl_lpuart_cmsis.h index 53a8d654f..71f383913 100644 --- a/cmsis_drivers/lpuart/fsl_lpuart_cmsis.h +++ b/cmsis_drivers/lpuart/fsl_lpuart_cmsis.h @@ -18,8 +18,8 @@ * limitations under the License. */ -#ifndef _FSL_LPUART_CMSIS_H_ -#define _FSL_LPUART_CMSIS_H_ +#ifndef FSL_LPUART_CMSIS_H_ +#define FSL_LPUART_CMSIS_H_ #include "fsl_common.h" #include "Driver_USART.h" @@ -105,4 +105,4 @@ extern ARM_DRIVER_USART Driver_USART5; #define USART_FLAG_POWER (1UL << 1) #define USART_FLAG_CONFIGURED (1UL << 2) -#endif /* _FSL_LPUART_CMSIS_H_ */ +#endif /* FSL_LPUART_CMSIS_H_ */ diff --git a/components/audio/fsl_adapter_audio.h b/components/audio/fsl_adapter_audio.h index b5a7af838..f37267370 100644 --- a/components/audio/fsl_adapter_audio.h +++ b/components/audio/fsl_adapter_audio.h @@ -326,8 +326,8 @@ typedef struct _hal_audio_config points to an entity defined by hal_audio_ip_config_t. If there is no specific feature configuration, it should be set to NULL. */ - uint32_t srcClock_Hz; /*!< Source clock */ - uint32_t sampleRate_Hz; /*!< Sample rate */ + uint32_t srcClock_Hz; /*!< Source clock */ + uint32_t sampleRate_Hz; /*!< Sample rate */ uint16_t frameLength; /*!< Only flexcomm_i2s uses this field. In most cases, frameLength is equal to bitWidth times lineChannels. In some cases, frameLength needs to be set to other value. For example, when the number of bit clock on the bus between two neighboring WS @@ -359,10 +359,10 @@ typedef struct _hal_audio_config on different mode. For example, for I2S classic mode, frameSyncWidth is equal to kHAL_AudioBeginAtFallingEdge. */ - hal_audio_channel_t lineChannels; /*!< Configure the number of channel on the data line. */ - hal_audio_data_format_t dataFormat; /*!< data format on bus */ + hal_audio_channel_t lineChannels; /*!< Configure the number of channel on the data line. */ + hal_audio_data_format_t dataFormat; /*!< data format on bus */ - uint8_t bitWidth; /*!< Bit Width */ + uint8_t bitWidth; /*!< Bit Width */ uint8_t instance; /*!< Instance (0 - I2S0/SAI0, 1 - I2S1/SAI1, ...), for detailed information please refer to the SOC corresponding RM. Invalid instance value will cause initialization failure. */ } hal_audio_config_t; diff --git a/components/audio/fsl_adapter_sai.c b/components/audio/fsl_adapter_sai.c index 4616ca1c9..27ca10146 100644 --- a/components/audio/fsl_adapter_sai.c +++ b/components/audio/fsl_adapter_sai.c @@ -7,8 +7,7 @@ */ #include "fsl_common.h" -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) #include "fsl_dmamux.h" #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ @@ -20,7 +19,7 @@ #include "fsl_sai.h" #include "fsl_sai_dma.h" #else -#endif /* FSL_FEATURE_SOC_EDMA_COUNT, FSL_FEATURE_SOC_DMA4_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ #include "fsl_adapter_audio.h" /******************************************************************************* @@ -32,8 +31,7 @@ typedef struct _hal_audio_state { hal_audio_transfer_callback_t callback; void *callbackParam; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) sai_edma_handle_t xferDmaHandle; edma_handle_t dmaHandle; #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) @@ -41,12 +39,11 @@ typedef struct _hal_audio_state dma_handle_t dmaHandle; #else #endif -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) uint8_t dmaMuxInstance; #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ -#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ uint8_t dmaInstance; uint8_t dmaChannel; uint8_t instance; @@ -68,13 +65,12 @@ static uint8_t s_i2sOccupied[ARRAY_SIZE(s_i2sBases)]; #if (defined(HAL_AUDIO_DMA_INIT_ENABLE) && (HAL_AUDIO_DMA_INIT_ENABLE > 0U)) /*! @brief Resource for each dma instance. */ static uint8_t s_dmaOccupied[ARRAY_SIZE((DMA_Type *[])DMA_BASE_PTRS)]; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) /*! @brief Resource for each dma mux instance. */ static uint8_t s_dmaMuxOccupied[ARRAY_SIZE((DMAMUX_Type *[])DMAMUX_BASE_PTRS)]; #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ -#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ #endif /* HAL_AUDIO_DMA_INIT_ENABLE */ /******************************************************************************* @@ -195,8 +191,7 @@ static hal_audio_status_t HAL_AudioGetStatus(status_t status) return returnStatus; } -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) static void HAL_AudioCallbackEDMA(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData) { hal_audio_state_t *audioHandle; @@ -235,20 +230,22 @@ static hal_audio_status_t HAL_AudioCommonInit(hal_audio_handle_t handle, sai_transceiver_t saiConfig; hal_audio_dma_config_t *dmaConfig; hal_audio_ip_config_t *featureConfig; -#if (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U) && \ + (defined(FSL_EDMA_SOC_IP_DMA3) && (FSL_EDMA_SOC_IP_DMA3 > 0) || \ + defined(FSL_EDMA_SOC_IP_DMA4) && (FSL_EDMA_SOC_IP_DMA4 > 0))) EDMA_Type *dmaBases[] = EDMA_BASE_PTRS; #else DMA_Type *dmaBases[] = DMA_BASE_PTRS; -#endif /* FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ IRQn_Type txIrqNumber[] = I2S_TX_IRQS; IRQn_Type rxIrqNumber[] = I2S_RX_IRQS; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) -#if (defined(FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL > 0U)) - IRQn_Type dmaIrqNumber[][FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL] = EDMA_CHN_IRQS; +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#if (defined(FSL_EDMA_SOC_IP_DMA3) && (FSL_EDMA_SOC_IP_DMA3 > 0) || \ + defined(FSL_EDMA_SOC_IP_DMA4) && (FSL_EDMA_SOC_IP_DMA4 > 0)) + IRQn_Type dmaIrqNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; #else IRQn_Type dmaIrqNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; -#endif /* FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL */ +#endif #if (defined(HAL_AUDIO_DMA_INIT_ENABLE) && (HAL_AUDIO_DMA_INIT_ENABLE > 0U)) edma_config_t audioDmaConfig; #endif /* HAL_AUDIO_DMA_INIT_ENABLE */ @@ -260,7 +257,7 @@ static hal_audio_status_t HAL_AudioCommonInit(hal_audio_handle_t handle, #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) IRQn_Type dmaIrqNumber[][FSL_FEATURE_DMA_MODULE_CHANNEL] = DMA_CHN_IRQS; #else -#endif /* FSL_FEATURE_SOC_EDMA_COUNT, FSL_FEATURE_SOC_DMA4_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ #if (defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE > 0U)) uint32_t u32Temp; @@ -447,8 +444,7 @@ static hal_audio_status_t HAL_AudioCommonInit(hal_audio_handle_t handle, } s_i2sOccupied[audioHandle->instance]++; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) assert(dmaConfig->dmaMuxConfig); @@ -498,10 +494,10 @@ static hal_audio_status_t HAL_AudioCommonInit(hal_audio_handle_t handle, EDMA_CreateHandle(&audioHandle->dmaHandle, dmaBases[dmaConfig->instance], dmaConfig->channel); #if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) - assert(dmaConfig->dmaChannelMuxConfig); - EDMA_SetChannelMux(dmaBases[dmaConfig->instance], dmaConfig->channel, - (dma_request_source_t)((hal_audio_dma_channel_mux_config_t *)dmaConfig->dmaChannelMuxConfig) - ->dmaChannelMuxConfig.dmaRequestSource); + assert(dmaConfig->dmaChannelMuxConfig); + EDMA_SetChannelMux(dmaBases[dmaConfig->instance], dmaConfig->channel, + (int32_t)((hal_audio_dma_channel_mux_config_t *)dmaConfig->dmaChannelMuxConfig) + ->dmaChannelMuxConfig.dmaRequestSource); #endif /* FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */ if ((uint8_t)kHAL_AudioDmaChannelPriorityDefault != (uint8_t)dmaConfig->priority) @@ -550,7 +546,7 @@ static hal_audio_status_t HAL_AudioCommonInit(hal_audio_handle_t handle, SAI_TransferRxSetConfigDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle, &saiConfig); } #else -#endif /* FSL_FEATURE_SOC_EDMA_COUNT, FSL_FEATURE_SOC_DMA4_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA_COUNT */ if (direction) { @@ -578,7 +574,9 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool { hal_audio_state_t *audioHandle; -#if (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U) && \ + (defined(FSL_EDMA_SOC_IP_DMA3) && (FSL_EDMA_SOC_IP_DMA3 > 0) || \ + defined(FSL_EDMA_SOC_IP_DMA4) && (FSL_EDMA_SOC_IP_DMA4 > 0))) #if (defined(HAL_AUDIO_DMA_INIT_ENABLE) && (HAL_AUDIO_DMA_INIT_ENABLE > 0U)) || \ (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) EDMA_Type *dmaBases[] = EDMA_BASE_PTRS; @@ -588,14 +586,13 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) DMA_Type *dmaBases[] = DMA_BASE_PTRS; #endif /* HAL_AUDIO_DMA_INIT_ENABLE or FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */ -#endif /* FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ #if (defined(HAL_AUDIO_DMA_INIT_ENABLE) && (HAL_AUDIO_DMA_INIT_ENABLE > 0U)) -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) DMAMUX_Type *dmaMuxBases[] = DMAMUX_BASE_PTRS; #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ -#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ #endif /* HAL_AUDIO_DMA_INIT_ENABLE */ assert(handle); @@ -627,12 +624,11 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool } } -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) - EDMA_SetChannelMux(dmaBases[audioHandle->dmaInstance], audioHandle->dmaChannel, kDmaRequestDisabled); + EDMA_SetChannelMux(dmaBases[audioHandle->dmaInstance], audioHandle->dmaChannel, 0); #endif /* FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */ -#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ #if (defined(HAL_AUDIO_DMA_INIT_ENABLE) && (HAL_AUDIO_DMA_INIT_ENABLE > 0U)) if (s_dmaOccupied[audioHandle->dmaInstance] != 0U) @@ -641,8 +637,7 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool if (s_dmaOccupied[audioHandle->dmaInstance] == 0U) { -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) EDMA_Deinit(dmaBases[audioHandle->dmaInstance]); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) DMA_Deinit(dmaBases[audioHandle->dmaInstance]); @@ -651,8 +646,7 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool } } -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) if (s_dmaMuxOccupied[audioHandle->dmaMuxInstance] != 0U) { @@ -664,7 +658,7 @@ static hal_audio_status_t HAL_AudioCommonDeinit(hal_audio_handle_t handle, bool } } #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ -#endif /* FSL_FEATURE_SOC_EDMA_COUNT or FSL_FEATURE_SOC_DMA4_COUNT */ +#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ #endif /* HAL_AUDIO_DMA_INIT_ENABLE */ return kStatus_HAL_AudioSuccess; @@ -734,8 +728,7 @@ hal_audio_status_t HAL_AudioTransferSendNonBlocking(hal_audio_handle_t handle, h transfer.data = (uint8_t *)xfer->data; transfer.dataSize = xfer->dataSize; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) return HAL_AudioGetStatus( SAI_TransferSendEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle, &transfer)); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) @@ -757,8 +750,7 @@ hal_audio_status_t HAL_AudioTransferReceiveNonBlocking(hal_audio_handle_t handle transfer.data = (uint8_t *)xfer->data; transfer.dataSize = xfer->dataSize; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) return HAL_AudioGetStatus( SAI_TransferReceiveEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle, &transfer)); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) @@ -776,8 +768,7 @@ hal_audio_status_t HAL_AudioTransferGetSendCount(hal_audio_handle_t handle, size audioHandle = (hal_audio_state_t *)handle; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) return HAL_AudioGetStatus( SAI_TransferGetSendCountEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle, count)); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) @@ -795,8 +786,7 @@ hal_audio_status_t HAL_AudioTransferGetReceiveCount(hal_audio_handle_t handle, s audioHandle = (hal_audio_state_t *)handle; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) return HAL_AudioGetStatus( SAI_TransferGetReceiveCountEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle, count)); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) @@ -814,8 +804,7 @@ hal_audio_status_t HAL_AudioTransferAbortSend(hal_audio_handle_t handle) audioHandle = (hal_audio_state_t *)handle; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) SAI_TransferTerminateSendEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) SAI_TransferAbortSendDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle); @@ -833,8 +822,7 @@ hal_audio_status_t HAL_AudioTransferAbortReceive(hal_audio_handle_t handle) audioHandle = (hal_audio_state_t *)handle; -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_DMA4_COUNT) && (FSL_FEATURE_SOC_DMA4_COUNT > 0U)) +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) SAI_TransferTerminateReceiveEDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle); #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) SAI_TransferAbortReceiveDMA(s_i2sBases[audioHandle->instance], &audioHandle->xferDmaHandle); diff --git a/components/button/fsl_component_button.c b/components/button/fsl_component_button.c index 77c35ac37..20d156a10 100644 --- a/components/button/fsl_component_button.c +++ b/components/button/fsl_component_button.c @@ -31,16 +31,10 @@ #if defined(OSA_USED) #include "fsl_os_abstraction.h" -#if (defined(USE_RTOS) && (USE_RTOS > 0U)) #define BUTTON_SR_ALLOC() OSA_SR_ALLOC() #define BUTTON_ENTER_CRITICAL() OSA_ENTER_CRITICAL(); #define BUTTON_EXIT_CRITICAL() OSA_EXIT_CRITICAL() #else -#define BUTTON_SR_ALLOC() -#define BUTTON_ENTER_CRITICAL() -#define BUTTON_EXIT_CRITICAL() -#endif -#else #define BUTTON_SR_ALLOC() uint32_t buttonPrimask; #define BUTTON_ENTER_CRITICAL() buttonPrimask = DisableGlobalIRQ(); #define BUTTON_EXIT_CRITICAL() EnableGlobalIRQ(buttonPrimask); @@ -158,7 +152,11 @@ static void BUTTON_Event(void *param) { (void)TM_Start(s_buttonList.timerHandle, (uint8_t)kTimerModeIntervalTimer, BUTTON_TIMER_INTERVAL); } - s_buttonList.activeButtonCount++; + + if (((uint8_t)kStatus_BUTTON_Pressed) == (buttonState->state.pressed)) + { + s_buttonList.activeButtonCount++; + } } } else @@ -515,8 +513,6 @@ button_status_t BUTTON_EnterLowpower(button_handle_t buttonHandle) assert(kStatus_HAL_GpioSuccess == status); (void)status; - BUTTON_CloseTimer(); - if ((button_handle_t)pLowpowerHandle != buttonHandle) { break; @@ -553,8 +549,6 @@ button_status_t BUTTON_ExitLowpower(button_handle_t buttonHandle) assert(kStatus_HAL_GpioSuccess == status); (void)status; - BUTTON_OpenTimer(); - BUTTON_Event(buttonState); if ((button_handle_t)pLowpowerHandle != buttonHandle) diff --git a/components/codec/da7212/fsl_dialog7212.c b/components/codec/da7212/fsl_dialog7212.c index bc4df20c4..d6b059858 100644 --- a/components/codec/da7212/fsl_dialog7212.c +++ b/components/codec/da7212/fsl_dialog7212.c @@ -404,6 +404,8 @@ status_t DA7212_Init(da7212_handle_t *handle, da7212_config_t *codecConfig) sysClock = (uint32_t)(codecConfig->pll->outputClock_HZ); } + + DA7212_ChangeInput(handle, codecConfig->inputSource); error = DA7212_ConfigAudioFormat(handle, sysClock, config->format.sampleRate, config->format.bitWidth); diff --git a/components/codec/da7212/fsl_dialog7212.h b/components/codec/da7212/fsl_dialog7212.h index ca2780b2c..d7989bb38 100644 --- a/components/codec/da7212/fsl_dialog7212.h +++ b/components/codec/da7212/fsl_dialog7212.h @@ -20,8 +20,8 @@ ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.3. */ -#define FSL_DA7212_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*! @brief CLOCK driver version 2.3.0. */ +#define FSL_DA7212_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ /*! @brief da7212 handle size */ @@ -156,7 +156,7 @@ #define DIALOG7212_DAC_NG_OFF_THRESH 0xB0 #define DIALOG7212_DAC_NG_ON_THRESH 0xB1 #define DIALOG7212_DAC_NG_CTRL 0xB2 -//#define DIALOG7212_DAC_NG_SPARE 0xB3 +// #define DIALOG7212_DAC_NG_SPARE 0xB3 /************Tone Generation & Beep Registers************/ #define DIALOG7212_TONE_GEN_CFG1 0xB4 #define DIALOG7212_TONE_GEN_CFG2 0xB5 @@ -1100,15 +1100,16 @@ typedef struct _da7212_audio_format /*! @brief DA7212 configure structure */ typedef struct da7212_config { - bool isMaster; /*!< If DA7212 is master, true means master, false means slave. */ - da7212_protocol_t protocol; /*!< Audio bus format, can be I2S, LJ, RJ or DSP mode. */ - da7212_dac_source_t dacSource; /*!< DA7212 data source. */ - da7212_audio_format_t format; /*!< audio format */ - uint8_t slaveAddress; /*!< device address */ - codec_i2c_config_t i2cConfig; /*!< i2c configuration */ + bool isMaster; /*!< If DA7212 is master, true means master, false means slave. */ + da7212_protocol_t protocol; /*!< Audio bus format, can be I2S, LJ, RJ or DSP mode. */ + da7212_dac_source_t dacSource; /*!< DA7212 data source. */ + da7212_audio_format_t format; /*!< audio format */ + uint8_t slaveAddress; /*!< device address */ + codec_i2c_config_t i2cConfig; /*!< i2c configuration */ da7212_sys_clk_source_t sysClkSource; /*!< system clock source */ da7212_pll_config_t *pll; /*!< pll configuration */ + da7212_Input_t inputSource; /*!< AD212 input source*/ } da7212_config_t; /*! @brief da7212 codec handler diff --git a/components/codec/fsl_codec_common.h b/components/codec/fsl_codec_common.h index bb10c5da1..797a58539 100644 --- a/components/codec/fsl_codec_common.h +++ b/components/codec/fsl_codec_common.h @@ -172,14 +172,14 @@ enum kCODEC_PlayChannelLineOutLeft = 16U, /*!< play channel lineout left */ kCODEC_PlayChannelLineOutRight = 32U, /*!< play channel lineout right */ - kCODEC_PlayChannelLeft0 = 1U, /*!< play channel left0 */ - kCODEC_PlayChannelRight0 = 2U, /*!< play channel right0 */ - kCODEC_PlayChannelLeft1 = 4U, /*!< play channel left1 */ - kCODEC_PlayChannelRight1 = 8U, /*!< play channel right1 */ - kCODEC_PlayChannelLeft2 = 16U, /*!< play channel left2 */ - kCODEC_PlayChannelRight2 = 32U, /*!< play channel right2 */ - kCODEC_PlayChannelLeft3 = 64U, /*!< play channel left3 */ - kCODEC_PlayChannelRight3 = 128U, /*!< play channel right3 */ + kCODEC_PlayChannelLeft0 = 1U, /*!< play channel left0 */ + kCODEC_PlayChannelRight0 = 2U, /*!< play channel right0 */ + kCODEC_PlayChannelLeft1 = 4U, /*!< play channel left1 */ + kCODEC_PlayChannelRight1 = 8U, /*!< play channel right1 */ + kCODEC_PlayChannelLeft2 = 16U, /*!< play channel left2 */ + kCODEC_PlayChannelRight2 = 32U, /*!< play channel right2 */ + kCODEC_PlayChannelLeft3 = 64U, /*!< play channel left3 */ + kCODEC_PlayChannelRight3 = 128U, /*!< play channel right3 */ }; /*! @brief codec volume setting @@ -194,16 +194,16 @@ enum kCODEC_VolumeLineOutLeft = 16U, /*!< lineout left volume */ kCODEC_VolumeLineOutRight = 32U, /*!< lineout right volume */ - kCODEC_VolumeLeft0 = 1UL << 0U, /*!< left0 volume */ - kCODEC_VolumeRight0 = 1UL << 1U, /*!< right0 volume */ - kCODEC_VolumeLeft1 = 1UL << 2U, /*!< left1 volume */ - kCODEC_VolumeRight1 = 1UL << 3U, /*!< right1 volume */ - kCODEC_VolumeLeft2 = 1UL << 4U, /*!< left2 volume */ - kCODEC_VolumeRight2 = 1UL << 5U, /*!< right2 volume */ - kCODEC_VolumeLeft3 = 1UL << 6U, /*!< left3 volume */ - kCODEC_VolumeRight3 = 1UL << 7U, /*!< right3 volume */ + kCODEC_VolumeLeft0 = 1UL << 0U, /*!< left0 volume */ + kCODEC_VolumeRight0 = 1UL << 1U, /*!< right0 volume */ + kCODEC_VolumeLeft1 = 1UL << 2U, /*!< left1 volume */ + kCODEC_VolumeRight1 = 1UL << 3U, /*!< right1 volume */ + kCODEC_VolumeLeft2 = 1UL << 4U, /*!< left2 volume */ + kCODEC_VolumeRight2 = 1UL << 5U, /*!< right2 volume */ + kCODEC_VolumeLeft3 = 1UL << 6U, /*!< left3 volume */ + kCODEC_VolumeRight3 = 1UL << 7U, /*!< right3 volume */ - kCODEC_VolumeDAC = 1UL << 8U, /*!< dac volume */ + kCODEC_VolumeDAC = 1UL << 8U, /*!< dac volume */ }; /*! @brief audio codec capability @@ -211,37 +211,37 @@ enum */ enum { - kCODEC_SupportModuleADC = 1U << 0U, /*!< codec capability of module ADC */ - kCODEC_SupportModuleDAC = 1U << 1U, /*!< codec capability of module DAC */ - kCODEC_SupportModulePGA = 1U << 2U, /*!< codec capability of module PGA */ - kCODEC_SupportModuleHeadphone = 1U << 3U, /*!< codec capability of module headphone */ - kCODEC_SupportModuleSpeaker = 1U << 4U, /*!< codec capability of module speaker */ - kCODEC_SupportModuleLinein = 1U << 5U, /*!< codec capability of module linein */ - kCODEC_SupportModuleLineout = 1U << 6U, /*!< codec capability of module lineout */ - kCODEC_SupportModuleVref = 1U << 7U, /*!< codec capability of module vref */ - kCODEC_SupportModuleMicbias = 1U << 8U, /*!< codec capability of module mic bias */ - kCODEC_SupportModuleMic = 1U << 9U, /*!< codec capability of module mic bias */ - kCODEC_SupportModuleI2SIn = 1U << 10U, /*!< codec capability of module I2S in */ - kCODEC_SupportModuleI2SOut = 1U << 11U, /*!< codec capability of module I2S out */ - kCODEC_SupportModuleMixer = 1U << 12U, /*!< codec capability of module mixer */ - kCODEC_SupportModuleI2SInSwitchInterface = 1U << 13U, /*!< codec capability of module I2S in switch interface */ - - kCODEC_SupportPlayChannelLeft0 = 1U << 0U, /*!< codec capability of play channel left 0 */ - kCODEC_SupportPlayChannelRight0 = 1U << 1U, /*!< codec capability of play channel right 0 */ - kCODEC_SupportPlayChannelLeft1 = 1U << 2U, /*!< codec capability of play channel left 1 */ - kCODEC_SupportPlayChannelRight1 = 1U << 3U, /*!< codec capability of play channel right 1 */ - kCODEC_SupportPlayChannelLeft2 = 1U << 4U, /*!< codec capability of play channel left 2 */ - kCODEC_SupportPlayChannelRight2 = 1U << 5U, /*!< codec capability of play channel right 2 */ - kCODEC_SupportPlayChannelLeft3 = 1U << 6U, /*!< codec capability of play channel left 3 */ - kCODEC_SupportPlayChannelRight3 = 1U << 7U, /*!< codec capability of play channel right 3 */ - - kCODEC_SupportPlaySourcePGA = 1U << 8U, /*!< codec capability of set playback source PGA */ - kCODEC_SupportPlaySourceInput = 1U << 9U, /*!< codec capability of set playback source INPUT */ - kCODEC_SupportPlaySourceDAC = 1U << 10U, /*!< codec capability of set playback source DAC */ - kCODEC_SupportPlaySourceMixerIn = 1U << 11U, /*!< codec capability of set play source Mixer in */ - kCODEC_SupportPlaySourceMixerInLeft = 1U << 12U, /*!< codec capability of set play source Mixer in left */ - kCODEC_SupportPlaySourceMixerInRight = 1U << 13U, /*!< codec capability of set play source Mixer in right */ - kCODEC_SupportPlaySourceAux = 1U << 14U, /*!< codec capability of set play source aux */ + kCODEC_SupportModuleADC = 1U << 0U, /*!< codec capability of module ADC */ + kCODEC_SupportModuleDAC = 1U << 1U, /*!< codec capability of module DAC */ + kCODEC_SupportModulePGA = 1U << 2U, /*!< codec capability of module PGA */ + kCODEC_SupportModuleHeadphone = 1U << 3U, /*!< codec capability of module headphone */ + kCODEC_SupportModuleSpeaker = 1U << 4U, /*!< codec capability of module speaker */ + kCODEC_SupportModuleLinein = 1U << 5U, /*!< codec capability of module linein */ + kCODEC_SupportModuleLineout = 1U << 6U, /*!< codec capability of module lineout */ + kCODEC_SupportModuleVref = 1U << 7U, /*!< codec capability of module vref */ + kCODEC_SupportModuleMicbias = 1U << 8U, /*!< codec capability of module mic bias */ + kCODEC_SupportModuleMic = 1U << 9U, /*!< codec capability of module mic bias */ + kCODEC_SupportModuleI2SIn = 1U << 10U, /*!< codec capability of module I2S in */ + kCODEC_SupportModuleI2SOut = 1U << 11U, /*!< codec capability of module I2S out */ + kCODEC_SupportModuleMixer = 1U << 12U, /*!< codec capability of module mixer */ + kCODEC_SupportModuleI2SInSwitchInterface = 1U << 13U, /*!< codec capability of module I2S in switch interface */ + + kCODEC_SupportPlayChannelLeft0 = 1U << 0U, /*!< codec capability of play channel left 0 */ + kCODEC_SupportPlayChannelRight0 = 1U << 1U, /*!< codec capability of play channel right 0 */ + kCODEC_SupportPlayChannelLeft1 = 1U << 2U, /*!< codec capability of play channel left 1 */ + kCODEC_SupportPlayChannelRight1 = 1U << 3U, /*!< codec capability of play channel right 1 */ + kCODEC_SupportPlayChannelLeft2 = 1U << 4U, /*!< codec capability of play channel left 2 */ + kCODEC_SupportPlayChannelRight2 = 1U << 5U, /*!< codec capability of play channel right 2 */ + kCODEC_SupportPlayChannelLeft3 = 1U << 6U, /*!< codec capability of play channel left 3 */ + kCODEC_SupportPlayChannelRight3 = 1U << 7U, /*!< codec capability of play channel right 3 */ + + kCODEC_SupportPlaySourcePGA = 1U << 8U, /*!< codec capability of set playback source PGA */ + kCODEC_SupportPlaySourceInput = 1U << 9U, /*!< codec capability of set playback source INPUT */ + kCODEC_SupportPlaySourceDAC = 1U << 10U, /*!< codec capability of set playback source DAC */ + kCODEC_SupportPlaySourceMixerIn = 1U << 11U, /*!< codec capability of set play source Mixer in */ + kCODEC_SupportPlaySourceMixerInLeft = 1U << 12U, /*!< codec capability of set play source Mixer in left */ + kCODEC_SupportPlaySourceMixerInRight = 1U << 13U, /*!< codec capability of set play source Mixer in right */ + kCODEC_SupportPlaySourceAux = 1U << 14U, /*!< codec capability of set play source aux */ kCODEC_SupportRecordSourceDifferentialLine = 1U << 0U, /*!< codec capability of record source differential line */ kCODEC_SupportRecordSourceLineInput = 1U << 1U, /*!< codec capability of record source line input */ diff --git a/components/codec/port/da7212/fsl_codec_da7212_adapter.c b/components/codec/port/da7212/fsl_codec_da7212_adapter.c index 0b94fc3fc..7f3dcd0f4 100644 --- a/components/codec/port/da7212/fsl_codec_da7212_adapter.c +++ b/components/codec/port/da7212/fsl_codec_da7212_adapter.c @@ -22,13 +22,12 @@ kCODEC_SupportRecordSourceSingleEndMic | kCODEC_SupportRecordSourceLineInput /*! @brief DA7212 map module */ -#define HAL_DA7212_MAP_PROTOCOL(protocol) \ - (protocol == kCODEC_BusI2S ? \ - kDA7212_BusI2S : \ - protocol == kCODEC_BusLeftJustified ? \ - kDA7212_BusLeftJustified : \ - protocol == kCODEC_BusRightJustified ? kDA7212_BusRightJustified : \ - protocol == kCODEC_BusPCMA ? kDA7212_BusDSPMode : kDA7212_BusI2S) +#define HAL_DA7212_MAP_PROTOCOL(protocol) \ + (protocol == kCODEC_BusI2S ? kDA7212_BusI2S : \ + protocol == kCODEC_BusLeftJustified ? kDA7212_BusLeftJustified : \ + protocol == kCODEC_BusRightJustified ? kDA7212_BusRightJustified : \ + protocol == kCODEC_BusPCMA ? kDA7212_BusDSPMode : \ + kDA7212_BusI2S) #define HAL_DA7212_VOLUME_CAPABILITY \ kCODEC_SupportPlayChannelLeft0 | kCODEC_SupportPlayChannelRight0 | kCODEC_SupportPlayChannelLeft1 | \ kCODEC_SupportPlayChannelRight1 diff --git a/components/codec/port/fsl_codec_adapter.c b/components/codec/port/fsl_codec_adapter.c index 5deb1b1c9..0d69820d3 100644 --- a/components/codec/port/fsl_codec_adapter.c +++ b/components/codec/port/fsl_codec_adapter.c @@ -1,6 +1,5 @@ /* - * Copyright 2019-2021 NXP - * All rights reserved. + * Copyright 2019-2023 NXP * * * SPDX-License-Identifier: BSD-3-Clause @@ -111,6 +110,19 @@ status_t HAL_CODEC_Init(void *handle, void *config) retVal = HAL_CODEC_TFA9896_Init(handle, config); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_Init(handle, config); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_Init(handle, config); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -197,6 +209,19 @@ status_t HAL_CODEC_Deinit(void *handle) retVal = HAL_CODEC_TFA9XXX_Deinit(handle); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_Deinit(handle); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_Deinit(handle); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -286,6 +311,19 @@ status_t HAL_CODEC_SetFormat(void *handle, uint32_t mclk, uint32_t sampleRate, u retVal = HAL_CODEC_TFA9XXX_SetFormat(handle, mclk, sampleRate, bitWidth); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetFormat(handle, mclk, sampleRate, bitWidth); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetFormat(handle, mclk, sampleRate, bitWidth); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -374,6 +412,19 @@ status_t HAL_CODEC_SetVolume(void *handle, uint32_t playChannel, uint32_t volume retVal = HAL_CODEC_TFA9XXX_SetVolume(handle, playChannel, volume); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetVolume(handle, playChannel, volume); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetVolume(handle, playChannel, volume); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -462,6 +513,19 @@ status_t HAL_CODEC_SetMute(void *handle, uint32_t playChannel, bool isMute) retVal = HAL_CODEC_TFA9XXX_SetMute(handle, playChannel, isMute); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetMute(handle, playChannel, isMute); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetMute(handle, playChannel, isMute); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -550,6 +614,19 @@ status_t HAL_CODEC_SetPower(void *handle, uint32_t module, bool powerOn) retVal = HAL_CODEC_TFA9XXX_SetPower(handle, module, powerOn); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetPower(handle, module, powerOn); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetPower(handle, module, powerOn); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -638,6 +715,19 @@ status_t HAL_CODEC_SetRecord(void *handle, uint32_t recordSource) retVal = HAL_CODEC_TFA9XXX_SetRecord(handle, recordSource); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetRecord(handle, recordSource); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetRecord(handle, recordSource); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -729,6 +819,19 @@ status_t HAL_CODEC_SetRecordChannel(void *handle, uint32_t leftRecordChannel, ui retVal = HAL_CODEC_TFA9XXX_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -817,6 +920,19 @@ status_t HAL_CODEC_SetPlay(void *handle, uint32_t playSource) retVal = HAL_CODEC_TFA9XXX_SetPlay(handle, playSource); break; #endif + +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_SetPlay(handle, playSource); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_SetPlay(handle, playSource); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; @@ -905,6 +1021,18 @@ status_t HAL_CODEC_ModuleControl(void *handle, uint32_t cmd, uint32_t data) break; #endif +#ifdef CODEC_PCM512X_ENABLE + case kCODEC_PCM512X: + retVal = HAL_CODEC_PCM512x_ModuleControl(handle, cmd, data); + break; +#endif + +#ifdef CODEC_PCM186X_ENABLE + case kCODEC_PCM186X: + retVal = HAL_CODEC_PCM186x_ModuleControl(handle, cmd, data); + break; +#endif + default: retVal = kStatus_InvalidArgument; break; diff --git a/components/codec/port/fsl_codec_adapter.h b/components/codec/port/fsl_codec_adapter.h index e984ceee2..4f9c44767 100644 --- a/components/codec/port/fsl_codec_adapter.h +++ b/components/codec/port/fsl_codec_adapter.h @@ -183,6 +183,34 @@ #endif /* CODEC_TFA9896_ENABLE */ +#ifdef CODEC_PCM512X_ENABLE +#include "fsl_codec_pcm512x_adapter.h" + +#if ((defined HAL_CODEC_HANDLER_SIZE) && (HAL_CODEC_HANDLER_SIZE < HAL_CODEC_PCM512X_HANDLER_SIZE)) +#undef HAL_CODEC_HANDLER_SIZE +#define HAL_CODEC_HANDLER_SIZE HAL_CODEC_PCM512X_HANDLER_SIZE +#endif + +#if (!(defined HAL_CODEC_HANDLER_SIZE)) +#define HAL_CODEC_HANDLER_SIZE HAL_CODEC_PCM512X_HANDLER_SIZE +#endif + +#endif /* CODEC_PCM512X_ENABLE */ + +#ifdef CODEC_PCM186X_ENABLE +#include "fsl_codec_pcm186x_adapter.h" + +#if ((defined HAL_CODEC_HANDLER_SIZE) && (HAL_CODEC_HANDLER_SIZE < HAL_CODEC_PCM186X_HANDLER_SIZE)) +#undef HAL_CODEC_HANDLER_SIZE +#define HAL_CODEC_HANDLER_SIZE HAL_CODEC_PCM186X_HANDLER_SIZE +#endif + +#if (!(defined HAL_CODEC_HANDLER_SIZE)) +#define HAL_CODEC_HANDLER_SIZE HAL_CODEC_PCM186X_HANDLER_SIZE +#endif + +#endif /* CODEC_PCM186X_ENABLE */ + #ifndef HAL_CODEC_HANDLER_SIZE #define HAL_CODEC_HANDLER_SIZE 128U #endif @@ -206,6 +234,8 @@ enum kCODEC_TFA9XXX, /*!< tfa9xxx */ kCODEC_TFA9896, /*!< tfa9896 */ kCODEC_WM8962, /*!< wm8962 */ + kCODEC_PCM512X, /*!< pcm512x */ + kCODEC_PCM186X, /*!< pcm186x */ }; /******************************************************************************* * API diff --git a/components/codec/port/sgtl5000/fsl_codec_sgtl_adapter.c b/components/codec/port/sgtl5000/fsl_codec_sgtl_adapter.c index a9446950d..667cbf01f 100644 --- a/components/codec/port/sgtl5000/fsl_codec_sgtl_adapter.c +++ b/components/codec/port/sgtl5000/fsl_codec_sgtl_adapter.c @@ -24,20 +24,15 @@ kCODEC_SupportPlayChannelLeft0 | kCODEC_SupportPlayChannelRight0 | kCODEC_SupportPlayChannelLeft1 | \ kCODEC_SupportPlayChannelRight1 | kCODEC_SupportPlayChannelLeft2 | kCODEC_SupportPlayChannelRight2 /*! @brief sgtl map module */ -#define HAL_SGTL_MAP_MODULE(module) \ - ((module) == (uint32_t)kCODEC_ModuleADC ? \ - kSGTL_ModuleADC : \ - (module) == (uint32_t)kCODEC_ModuleDAC ? \ - kSGTL_ModuleDAC : \ - (module) == (uint32_t)kCODEC_ModuleHeadphone ? \ - kSGTL_ModuleHP : \ - (module) == (uint32_t)kCODEC_ModuleI2SIn ? \ - kSGTL_ModuleI2SIN : \ - (module) == (uint32_t)kCODEC_ModuleI2SOut ? \ - kSGTL_ModuleI2SOUT : \ - (module) == (uint32_t)kCODEC_ModuleLinein ? \ - kSGTL_ModuleLineIn : \ - (module) == (uint32_t)kCODEC_ModuleLineout ? kSGTL_ModuleLineOut : kSGTL_ModuleMicin) +#define HAL_SGTL_MAP_MODULE(module) \ + ((module) == (uint32_t)kCODEC_ModuleADC ? kSGTL_ModuleADC : \ + (module) == (uint32_t)kCODEC_ModuleDAC ? kSGTL_ModuleDAC : \ + (module) == (uint32_t)kCODEC_ModuleHeadphone ? kSGTL_ModuleHP : \ + (module) == (uint32_t)kCODEC_ModuleI2SIn ? kSGTL_ModuleI2SIN : \ + (module) == (uint32_t)kCODEC_ModuleI2SOut ? kSGTL_ModuleI2SOUT : \ + (module) == (uint32_t)kCODEC_ModuleLinein ? kSGTL_ModuleLineIn : \ + (module) == (uint32_t)kCODEC_ModuleLineout ? kSGTL_ModuleLineOut : \ + kSGTL_ModuleMicin) /******************************************************************************* * Prototypes diff --git a/components/codec/port/wm8904/fsl_codec_wm8904_adapter.c b/components/codec/port/wm8904/fsl_codec_wm8904_adapter.c index 2a5ae8277..d809ba3ac 100644 --- a/components/codec/port/wm8904/fsl_codec_wm8904_adapter.c +++ b/components/codec/port/wm8904/fsl_codec_wm8904_adapter.c @@ -28,38 +28,31 @@ kCODEC_SupportRecordChannelRight1 | kCODEC_SupportRecordChannelRight2 | kCODEC_SupportRecordChannelRight3 /*! @brief wm8904 map protocol */ -#define HAL_WM8904_MAP_PROTOCOL(protocol) \ - ((protocol) == kCODEC_BusI2S ? \ - kWM8904_ProtocolI2S : \ - (protocol) == kCODEC_BusLeftJustified ? \ - kWM8904_ProtocolLeftJustified : \ - (protocol) == kCODEC_BusRightJustified ? \ - kWM8904_ProtocolRightJustified : \ - (protocol) == kCODEC_BusPCMA ? kWM8904_ProtocolPCMA : \ - (protocol) == kCODEC_BusPCMB ? kWM8904_ProtocolPCMB : kWM8904_ProtocolI2S) +#define HAL_WM8904_MAP_PROTOCOL(protocol) \ + ((protocol) == kCODEC_BusI2S ? kWM8904_ProtocolI2S : \ + (protocol) == kCODEC_BusLeftJustified ? kWM8904_ProtocolLeftJustified : \ + (protocol) == kCODEC_BusRightJustified ? kWM8904_ProtocolRightJustified : \ + (protocol) == kCODEC_BusPCMA ? kWM8904_ProtocolPCMA : \ + (protocol) == kCODEC_BusPCMB ? kWM8904_ProtocolPCMB : \ + kWM8904_ProtocolI2S) /*! @brief wm8904 map module */ -#define HAL_WM8904_MAP_MODULE(module) \ - ((module) == kCODEC_ModuleADC ? \ - kWM8904_ModuleADC : \ - (module) == kCODEC_ModuleDAC ? \ - kWM8904_ModuleDAC : \ - (module) == kCODEC_ModulePGA ? kWM8904_ModulePGA : \ - (module) == kCODEC_ModuleHeadphone ? \ - kWM8904_ModuleHeadphone : \ - (module) == kCODEC_ModuleLineout ? kWM8904_ModuleLineout : kWM8904_ModuleADC) +#define HAL_WM8904_MAP_MODULE(module) \ + ((module) == kCODEC_ModuleADC ? kWM8904_ModuleADC : \ + (module) == kCODEC_ModuleDAC ? kWM8904_ModuleDAC : \ + (module) == kCODEC_ModulePGA ? kWM8904_ModulePGA : \ + (module) == kCODEC_ModuleHeadphone ? kWM8904_ModuleHeadphone : \ + (module) == kCODEC_ModuleLineout ? kWM8904_ModuleLineout : \ + kWM8904_ModuleADC) /*! @brief wm8904 map protocol */ -#define HAL_WM8904_MAP_SAMPLERATE(sampleRATE) \ - ((sampleRATE) == kCODEC_AudioSampleRate8KHz ? \ - kWM8904_SampleRate8kHz : \ - (sampleRATE) == kCODEC_AudioSampleRate12KHz ? \ - kWM8904_SampleRate12kHz : \ - (sampleRATE) == kCODEC_AudioSampleRate16KHz ? \ - kWM8904_SampleRate16kHz : \ - (sampleRATE) == kCODEC_AudioSampleRate24KHz ? \ - kWM8904_SampleRate24kHz : \ - (sampleRATE) == kCODEC_AudioSampleRate32KHz ? kWM8904_SampleRate32kHz : kWM8904_SampleRate48kHz) +#define HAL_WM8904_MAP_SAMPLERATE(sampleRATE) \ + ((sampleRATE) == kCODEC_AudioSampleRate8KHz ? kWM8904_SampleRate8kHz : \ + (sampleRATE) == kCODEC_AudioSampleRate12KHz ? kWM8904_SampleRate12kHz : \ + (sampleRATE) == kCODEC_AudioSampleRate16KHz ? kWM8904_SampleRate16kHz : \ + (sampleRATE) == kCODEC_AudioSampleRate24KHz ? kWM8904_SampleRate24kHz : \ + (sampleRATE) == kCODEC_AudioSampleRate32KHz ? kWM8904_SampleRate32kHz : \ + kWM8904_SampleRate48kHz) /******************************************************************************* * Prototypes @@ -156,7 +149,7 @@ status_t HAL_CODEC_WM8904_SetVolume(void *handle, uint32_t playChannel, uint32_t { mappedVolume = (volume * (WM8904_DAC_MAX_VOLUME - 0U)) / 100U; ret = WM8904_SetDACVolume((wm8904_handle_t *)((uint32_t)(((codec_handle_t *)handle)->codecDevHandle)), - (uint8_t)mappedVolume); + (uint8_t)mappedVolume); if (ret != kStatus_Success) { return ret; diff --git a/components/codec/port/wm8960/fsl_codec_wm8960_adapter.c b/components/codec/port/wm8960/fsl_codec_wm8960_adapter.c index 84e12518a..0a84e5f66 100644 --- a/components/codec/port/wm8960/fsl_codec_wm8960_adapter.c +++ b/components/codec/port/wm8960/fsl_codec_wm8960_adapter.c @@ -1,7 +1,5 @@ /* - * Copyright 2021 NXP - * All rights reserved. - * + * Copyright 2021-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,37 +29,27 @@ kCODEC_SupportPlayChannelRight0 | kCODEC_SupportPlayChannelRight1 | kCODEC_SupportPlayChannelRight2) /*! @brief wm8960 map protocol */ -#define HAL_WM8960_MAP_PROTOCOL(protocol) \ - ((protocol) == kCODEC_BusI2S ? \ - kWM8960_BusI2S : \ - (protocol) == kCODEC_BusLeftJustified ? \ - kWM8960_BusLeftJustified : \ - (protocol) == kCODEC_BusRightJustified ? \ - kWM8960_BusRightJustified : \ - (protocol) == kCODEC_BusPCMA ? kWM8960_BusPCMA : \ - (protocol) == kCODEC_BusPCMB ? kWM8960_BusPCMB : kWM8960_BusI2S) +#define HAL_WM8960_MAP_PROTOCOL(protocol) \ + ((protocol) == kCODEC_BusI2S ? kWM8960_BusI2S : \ + (protocol) == kCODEC_BusLeftJustified ? kWM8960_BusLeftJustified : \ + (protocol) == kCODEC_BusRightJustified ? kWM8960_BusRightJustified : \ + (protocol) == kCODEC_BusPCMA ? kWM8960_BusPCMA : \ + (protocol) == kCODEC_BusPCMB ? kWM8960_BusPCMB : \ + kWM8960_BusI2S) /*! @brief wm8960 map module */ -#define HAL_WM8960_MAP_MODULE(module) \ - ((module) == (uint32_t)kCODEC_ModuleADC ? \ - kWM8960_ModuleADC : \ - (module) == (uint32_t)kCODEC_ModuleDAC ? \ - kWM8960_ModuleDAC : \ - (module) == (uint32_t)kCODEC_ModuleVref ? \ - kWM8960_ModuleVREF : \ - (module) == (uint32_t)kCODEC_ModuleHeadphone ? \ - kWM8960_ModuleHP : \ - (module) == (uint32_t)kCODEC_ModuleMicbias ? \ - kWM8960_ModuleMICB : \ - (module) == (uint32_t)kCODEC_ModuleMic ? \ - kWM8960_ModuleMIC : \ - (module) == (uint32_t)kCODEC_ModuleLinein ? \ - kWM8960_ModuleLineIn : \ - (module) == (uint32_t)kCODEC_ModuleSpeaker ? \ - kWM8960_ModuleSpeaker : \ - (module) == (uint32_t)kCODEC_ModuleMixer ? \ - kWM8960_ModuleOMIX : \ - (module) == (uint32_t)kCODEC_ModuleLineout ? kWM8960_ModuleLineOut : kWM8960_ModuleADC) +#define HAL_WM8960_MAP_MODULE(module) \ + ((module) == (uint32_t)kCODEC_ModuleADC ? kWM8960_ModuleADC : \ + (module) == (uint32_t)kCODEC_ModuleDAC ? kWM8960_ModuleDAC : \ + (module) == (uint32_t)kCODEC_ModuleVref ? kWM8960_ModuleVREF : \ + (module) == (uint32_t)kCODEC_ModuleHeadphone ? kWM8960_ModuleHP : \ + (module) == (uint32_t)kCODEC_ModuleMicbias ? kWM8960_ModuleMICB : \ + (module) == (uint32_t)kCODEC_ModuleMic ? kWM8960_ModuleMIC : \ + (module) == (uint32_t)kCODEC_ModuleLinein ? kWM8960_ModuleLineIn : \ + (module) == (uint32_t)kCODEC_ModuleSpeaker ? kWM8960_ModuleSpeaker : \ + (module) == (uint32_t)kCODEC_ModuleMixer ? kWM8960_ModuleOMIX : \ + (module) == (uint32_t)kCODEC_ModuleLineout ? kWM8960_ModuleLineOut : \ + kWM8960_ModuleADC) /******************************************************************************* * Prototypes diff --git a/components/codec/port/wm8960/fsl_codec_wm8960_adapter.h b/components/codec/port/wm8960/fsl_codec_wm8960_adapter.h index ce612560c..88a902564 100644 --- a/components/codec/port/wm8960/fsl_codec_wm8960_adapter.h +++ b/components/codec/port/wm8960/fsl_codec_wm8960_adapter.h @@ -1,7 +1,5 @@ /* - * Copyright 2021 NXP - * All rights reserved. - * + * Copyright 2021-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/components/codec/sgtl5000/fsl_sgtl5000.h b/components/codec/sgtl5000/fsl_sgtl5000.h index 44d9c432f..8d5ca81e9 100644 --- a/components/codec/sgtl5000/fsl_sgtl5000.h +++ b/components/codec/sgtl5000/fsl_sgtl5000.h @@ -847,10 +847,10 @@ typedef struct _sgtl_audio_format /*! @brief Initailize structure of sgtl5000 */ typedef struct _sgtl_config { - sgtl_route_t route; /*!< Audio data route.*/ - sgtl_protocol_t bus; /*!< Audio transfer protocol */ - bool master_slave; /*!< Master or slave. True means master, false means slave. */ - sgtl_audio_format_t format; /*!< audio format */ + sgtl_route_t route; /*!< Audio data route.*/ + sgtl_protocol_t bus; /*!< Audio transfer protocol */ + bool master_slave; /*!< Master or slave. True means master, false means slave. */ + sgtl_audio_format_t format; /*!< audio format */ uint8_t slaveAddress; /*!< code device slave address */ codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ diff --git a/components/codec/wm8904/fsl_wm8904.c b/components/codec/wm8904/fsl_wm8904.c index e089ca329..2507a6f21 100644 --- a/components/codec/wm8904/fsl_wm8904.c +++ b/components/codec/wm8904/fsl_wm8904.c @@ -14,21 +14,17 @@ * Definitions ******************************************************************************/ /*! @brief wm8904 volume mapping */ -#define WM8904_SWAP_UINT16_BYTE_SEQUENCE(x) ((((x) & 0x00ffU) << 8U) | (((x) & 0xff00U) >> 8U)) -#define WM8904_MAP_SAMPLERATE(x) \ - ((x) == kWM8904_SampleRate8kHz ? \ - 8000U : \ - (x) == kWM8904_SampleRate12kHz ? \ - 12000U : \ - (x) == kWM8904_SampleRate16kHz ? \ - 16000U : \ - (x) == kWM8904_SampleRate24kHz ? \ - 24000U : \ - (x) == kWM8904_SampleRate32kHz ? \ - 32000U : \ - (x) == kWM8904_SampleRate48kHz ? \ - 48000U : \ - (x) == kWM8904_SampleRate11025Hz ? 11025U : (x) == kWM8904_SampleRate22050Hz ? 22050U : 44100U) +#define WM8904_SWAP_UINT16_BYTE_SEQUENCE(x) ((((x)&0x00ffU) << 8U) | (((x)&0xff00U) >> 8U)) +#define WM8904_MAP_SAMPLERATE(x) \ + ((x) == kWM8904_SampleRate8kHz ? 8000U : \ + (x) == kWM8904_SampleRate12kHz ? 12000U : \ + (x) == kWM8904_SampleRate16kHz ? 16000U : \ + (x) == kWM8904_SampleRate24kHz ? 24000U : \ + (x) == kWM8904_SampleRate32kHz ? 32000U : \ + (x) == kWM8904_SampleRate48kHz ? 48000U : \ + (x) == kWM8904_SampleRate11025Hz ? 11025U : \ + (x) == kWM8904_SampleRate22050Hz ? 22050U : \ + 44100U) #define WM8904_MAP_BITWIDTH(x) \ ((x) == kWM8904_BitWidth16 ? 16 : (x) == kWM8904_BitWidth20 ? 20 : (x) == kWM8904_BitWidth24 ? 24 : 32) /******************************************************************************* diff --git a/components/codec/wm8904/fsl_wm8904.h b/components/codec/wm8904/fsl_wm8904.h index b8269f44a..50500d177 100644 --- a/components/codec/wm8904/fsl_wm8904.h +++ b/components/codec/wm8904/fsl_wm8904.h @@ -268,13 +268,13 @@ typedef struct _wm8904_config wm8904_audio_format_t format; /*!< Audio format */ uint32_t mclk_HZ; /*!< MCLK frequency value */ - uint16_t recordSource; /*!< record source */ - uint16_t recordChannelLeft; /*!< record channel */ - uint16_t recordChannelRight; /*!< record channel */ - uint16_t playSource; /*!< play source */ + uint16_t recordSource; /*!< record source */ + uint16_t recordChannelLeft; /*!< record channel */ + uint16_t recordChannelRight; /*!< record channel */ + uint16_t playSource; /*!< play source */ - uint8_t slaveAddress; /*!< code device slave address */ - codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ + uint8_t slaveAddress; /*!< code device slave address */ + codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ } wm8904_config_t; /*! @brief wm8904 codec handler diff --git a/components/codec/wm8960/fsl_wm8960.c b/components/codec/wm8960/fsl_wm8960.c index daed274a3..556810fdf 100644 --- a/components/codec/wm8960/fsl_wm8960.c +++ b/components/codec/wm8960/fsl_wm8960.c @@ -90,7 +90,8 @@ static status_t WM8960_SetInternalPllConfig( /* enable PLL power */ WM8960_CHECK_RET(WM8960_ModifyReg(handle, WM8960_POWER2, 1U, 1U), ret); - WM8960_CHECK_RET(WM8960_ModifyReg(handle, WM8960_CLOCK1, 7U, (uint16_t)(((sysclkDiv == 1U ? 0U : sysclkDiv) << 1U) | 1U)), ret); + WM8960_CHECK_RET( + WM8960_ModifyReg(handle, WM8960_CLOCK1, 7U, (uint16_t)(((sysclkDiv == 1U ? 0U : sysclkDiv) << 1U) | 1U)), ret); return ret; } @@ -269,7 +270,6 @@ status_t WM8960_Deinit(wm8960_handle_t *handle) WM8960_CHECK_RET(WM8960_SetModule(handle, kWM8960_ModuleLineIn, false), ret); WM8960_CHECK_RET(WM8960_SetModule(handle, kWM8960_ModuleLineOut, false), ret); WM8960_CHECK_RET(WM8960_SetModule(handle, kWM8960_ModuleSpeaker, false), ret); - WM8960_CHECK_RET(CODEC_I2C_Deinit(handle->i2cHandle), ret); return ret; } diff --git a/components/codec/wm8960/fsl_wm8960.h b/components/codec/wm8960/fsl_wm8960.h index c5d8bb614..4fa6593f7 100644 --- a/components/codec/wm8960/fsl_wm8960.h +++ b/components/codec/wm8960/fsl_wm8960.h @@ -23,8 +23,8 @@ ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.2.2 */ -#define FSL_WM8960_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @brief CLOCK driver version 2.2.4 */ +#define FSL_WM8960_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*@}*/ /*! @brief wm8960 handle size */ diff --git a/components/els_pkc/LICENSE.htm b/components/els_pkc/LICENSE.htm new file mode 100644 index 000000000..ad837cbd2 --- /dev/null +++ b/components/els_pkc/LICENSE.htm @@ -0,0 +1,3757 @@ + + + + + + + + + + + + + + + + + + +

+ +

LA_OPT_NXP_Software_License v48 +July 2023 

+ +

IMPORTANT.  Read +the following NXP Software License Agreement (“Agreement”) completely. By +selecting the “I Accept” button at the end of this page, or by downloading, installing, or using the Licensed Software, you indicate that you accept the terms of +the Agreement, and you acknowledge that you have the authority, +for yourself or on behalf of your company, to bind your company to these terms. +You may then download or install the file. In the event of a conflict between the +terms of this Agreement and any license terms and conditions for NXP’s proprietary software +embedded anywhere in the Licensed Software file, the terms of this Agreement +shall control.  If a separate license agreement for the Licensed Software +has been signed by you and NXP, then that agreement shall govern your use of +the Licensed Software and shall supersede this Agreement.

+ +

 

+ +

NXP SOFTWARE LICENSE AGREEMENT

+ +

This is a legal +agreement between your +employer, of which you are an authorized representative, or, if you have no +employer, you as an individual (“you” or “Licensee”), and NXP B.V. (“NXP”).  +It concerns your rights to use the software provided to you in binary or source +code form and any accompanying written materials (the “Licensed Software”). The +Licensed Software may include any updates or error corrections or documentation +relating to the Licensed Software provided to you by NXP under this Agreement. +In consideration for NXP allowing you to access the Licensed Software, you are +agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or +install the Licensed Software. If you change your mind later, stop using the +Licensed Software and delete all copies of the Licensed Software in your +possession or control. Any copies of the Licensed Software that you have +already distributed, where permitted, and do not destroy will continue to be +governed by this Agreement. Your prior use will also continue to be governed by +this Agreement.

+ +

1.       +DEFINITIONS

+ +

1.1.         +“Affiliate” means, with respect to a party, any corporation or other legal +entity that now or hereafter Controls, is Controlled by or is under common +Control with such party; where “Control” means the direct or indirect ownership +of greater than fifty percent (50%) of the shares or similar interests entitled +to vote for the election of directors or other persons performing similar +functions. An entity is considered an Affiliate only so long as such Control +exists.

+ +

1.2       “Authorized System” means either (i) Licensee’s hardware product which incorporates an NXP +Product or (ii) Licensee’s software program which is used exclusively in +connection with an NXP Product and with which the Licensed Software will be +integrated.      

+ +

1.3.      “Derivative Work” means a work based upon +one or more pre-existing works.  A work +consisting of editorial revisions, annotations, elaborations, or other +modifications which, as a whole, represent an original +work of authorship, is a Derivative +Work.        

+ +

1.4       “Intellectual Property Rights” means any and all rights under statute, common law or equity in +and under copyrights, trade secrets, and patents (including utility +models), and analogous rights throughout the world, including any +applications for and the right to apply for, any of the foregoing.

+ +

1.5       “NXP Product” means a hardware product (e.g. a +microprocessor, microcontroller, sensor or digital signal processor) and/or +services (e.g. cloud platform services) supplied directly or indirectly from +NXP or an NXP Affiliate, unless there is a product specified in the Software +Content Register, in which case this definition is limited to such product.

+ +

1.6      “Software Content Register” means the +documentation which may accompany the Licensed Software which identifies the +contents of the Licensed Software, including but not limited to identification of +any Third Party Software, if any, and may also contain other related +information as whether the license in 2.3 is applicable. 

+ +

1.7     “Third Party Software” means, any software +included in the Licensed Software that is not NXP +proprietary software, and is not open source software, and to which +different license terms may apply. 

+ +

2.       +LICENSE GRANT.  

+ +

2.1.         +If you are not expressly granted the distribution license in Section 2.3 in the +Software Content Register, then you are only granted the rights in Section 2.2 +and not in 2.3.  If you are expressly +granted the distribution license in Section 2.3 in the Software Content +Register, then you are granted the rights in both Section 2.2 and 2.3.

+ +

2.2.      Standard License.  Subject to the terms and conditions of this +Agreement, NXP grants you a worldwide, personal, non-transferable, +non-exclusive, non-sublicensable license, solely for +the development of an Authorized System:

+ +

(a)        to +use and reproduce the Licensed Software (and its Derivative Works prepared +under the license in Section 2.2(b)) +solely in combination +with a NXP Product; and

+ +

(b)        for +Licensed Software provided to you in source code form (human readable), to +prepare Derivative Works of the Licensed Software solely +for use in combination with a NXP Product.

+ +

You may not distribute +or sublicense the Licensed Software to others under the license granted in this +Section 2.2. 

+ +

You may demonstrate the Licensed Software to +your direct customers as part of an Authorized System so long as such +demonstration is directly controlled by you and without prior approval by NXP; +however, to all other third parties only if NXP has provided its advance, +written approval (e.g. email approval) of your +demonstrating the Licensed Software to specified third parties or at specified +event(s).  You may not leave the Licensed Software with a direct customer +or any other third party at any time. 

+ +

2.3.        Additional +Distribution License.  If expressly +authorized in the Software Content Register, subject to the terms and +conditions of this Agreement, NXP grants you a worldwide, +personal, non-transferable, non-exclusive, non-sublicensable license solely in connection +with your manufacturing and distribution of an Authorized System:

+ +

(a)            +to manufacture (or have +manufactured), distribute, and market the Licensed Software (and its Derivative +Works prepared under the license in 2.2(b)) in object code (machine readable +format) only as part of, or embedded within, Authorized Systems and not on a +standalone basis solely for use in combination with a NXP Product.  Notwithstanding the foregoing, those files +marked as .h files (“Header files”) may be distributed in source or object code +form, but only as part of, or embedded within Authorized Systems; and 

+ +

(b)            +to copy and distribute as needed, +solely in connection with an Authorized System and for use in combination with a NXP Product, +non-confidential NXP information provided as part of the Licensed Software for +the purpose of maintaining and supporting Authorized Systems with which the +Licensed Software is integrated.

+ +

2.4       Separate license grants to Third Party +Software, or other terms applicable to the Licensed Software if different from +those granted in this Section 2, are contained in Appendix A. The Licensed +Software may be accompanied by a Software Content Register which will identify +that portion of the Licensed Software, if any, that is subject to the different +terms in Appendix A. 

+ +

2.5.         +You may use subcontractors to exercise your rights under Section 2.2 and +Section 2.3, if any, so long as you have an agreement in place with the +subcontractor containing confidentiality restrictions no less stringent than +those contained in this Agreement. You will remain liable for your +subcontractors’ adherence to the terms of this Agreement and for any and all acts and omissions of such subcontractors with +respect to this Agreement and the Licensed Software.

+ +

3.       +LICENSE LIMITATIONS AND RESTRICTIONS.  

+ +

3.1.         +The licenses granted above in Section 2 only extend to NXP Intellectual +Property Rights that would be infringed by the unmodified Licensed Software +prior to your preparation of any Derivative Work.   

+ +

3.2.         +The Licensed Software is licensed to you, not sold. Title to Licensed Software +delivered hereunder remains vested in NXP or NXP’s licensor and cannot be +assigned or transferred. You are expressly forbidden from selling or otherwise +distributing the Licensed Software, or any portion thereof, except as expressly +permitted herein. This Agreement does not grant to you any implied rights under +any NXP or third party Intellectual Property Rights.

+ +

3.3.         +You may not translate, reverse engineer, decompile, or disassemble the Licensed +Software except to the extent applicable law specifically prohibits such +restriction. You must prohibit your subcontractors or customers (if +distribution is permitted) from translating, reverse engineering, decompiling, +or disassembling the Licensed Software except to the extent applicable law +specifically prohibits such restriction.

+ +

3.4.         +You must reproduce any and all of NXP’s (or its +third-party licensor’s) copyright notices and other proprietary legends on copies +of Licensed Software.  

+ +

3.5.         +If you distribute the Licensed Software to the United States Government, then +the Licensed Software is “restricted computer software” and is subject to FAR +52.227-19.   

+ +

3.6.         +You grant to NXP a non-exclusive, non-transferable, irrevocable, perpetual, +worldwide, royalty-free, sub-licensable license under your Intellectual +Property Rights to use without restriction and for any purpose any suggestion, +comment or other feedback related to the Licensed Software (including, but not +limited to, error corrections and bug fixes).

+ +

3.7.         +You will not take or fail to take any action that could subject the Licensed +Software to an Excluded License. An Excluded License means any license that +requires, as a condition of use, modification or +distribution of software subject to the Excluded License, that such software or +other software combined and/or distributed with the software be (i) disclosed or distributed in source code form; (ii) +licensed for the purpose of making Derivative Works; or (iii) redistributable +at no charge. 

+ +

3.8.         +You may not publish or distribute reports associated with the use of the +Licensed Software to anyone other than NXP.  +You may advise NXP of any results obtained from your use of the Licensed +Software, including any problems or suggested improvements thereof, and NXP +retains the right to use such results and related information in any manner it +deems appropriate.

+ +

4.       +OPEN SOURCE.         +Open source software included in the Licensed Software +is not licensed under the terms of this Agreement but is instead licensed under +the terms of the applicable open source license(s), such as the BSD License, +Apache License or the GNU Lesser General Public License. Your use of the open source software is subject to the terms of each +applicable license. You must agree to the terms of each applicable license, or +you cannot use the open source software.  

+ + + +

5.       +INTELLECTUAL PROPERTY RIGHTS.   

+ +

Upon request, you must +provide NXP the source code of any derivative of the Licensed Software.

+ +

Unless prohibited by +law, the following paragraph shall apply.  +Your modifications to the Licensed Software, and all intellectual +property rights associated with, and title thereto, will be the property of NXP.  You agree to assign all, and hereby do assign +all rights, title, and interest to any such modifications to the Licensed +Software to NXP and agree to provide all assistance reasonably requested by NXP +to establish, preserve or enforce such right.  Further, you agree to waive all moral rights +relating to your modifications to the Licensed Software, including, without +limitation, all rights of identification of authorship and all rights of +approval, restriction, or limitation on use or subsequent modification.  Notwithstanding the foregoing, you will have +the license rights granted in Section 2 hereto to any such modifications made +by you or your licensees.

+ +

Otherwise, you agree to +grant an irrevocable, worldwide, and perpetual license to NXP to make, have made, +use, sell, offer to sell, import, commercialize, sublicense +and reproduce your modifications or derivative works to the Licensed Software +without any payment to Licensee. You agree to provide all assistance reasonably +requested by NXP to establish, preserve or enforce +such right.

+ +

6.       +ESSENTIAL PATENTS.    NXP has no +obligation to identify or obtain any license to any Intellectual Property Right +of a third-party that may be necessary for use in connection with technology +that is incorporated into the Authorized System (whether or not as part of the Licensed Software).

+ +

7.       +TERM AND TERMINATION.   This Agreement will remain in effect +unless terminated as provided in this Section.

+ +

7.1.         +You may terminate this Agreement immediately upon written notice to NXP at the +address provided below.

+ +

7.2.         +Either party may terminate this Agreement if the other party is in default of +any of the terms and conditions of this Agreement, and termination is effective +if the defaulting party fails to correct such default within 30 days after +written notice thereof by the non-defaulting party to the defaulting party at +the address below.

+ +

7.3.         +Notwithstanding the foregoing, NXP may terminate this Agreement immediately +upon written notice if you: breach any of your confidentiality obligations or +the license restrictions under this Agreement;  become bankrupt, +insolvent, or file a petition for bankruptcy or insolvency; make an assignment +for the benefit of its creditors; enter proceedings for winding up or +dissolution; are dissolved; or are nationalized or become subject to the +expropriation of all or substantially all of your business or assets.

+ +

7.4.         +Upon termination of this Agreement, all licenses granted under Section 2 will +expire.

+ +

7.5.         +After termination of this Agreement by either party   you will destroy all parts of Licensed +Software and its Derivative Works (if any) and will provide to NXP a statement +certifying the same.

+ +

7.6.         +Notwithstanding the termination of this Agreement for any reason, the terms of +Sections 1 and 3 through 24 will survive.  

+ +

8. +       SUPPORT.  NXP is not obligated +to provide any support, upgrades or new releases of +the Licensed Software under this Agreement. If you wish, you may contact NXP +and report problems and provide suggestions regarding the Licensed Software. +NXP has no obligation to respond to such a problem report or suggestion. NXP +may make changes to the Licensed Software at any time, without any obligation +to notify or provide updated versions of the Licensed Software to you.

+ +

9.        +NO WARRANTY.  To the maximum extent permitted by law, NXP expressly +disclaims any warranty for the Licensed Software. The Licensed Software is +provided “AS IS”, without warranty of any kind, either express or implied, +including without limitation the implied warranties of merchantability, fitness +for a particular purpose, or non-infringement. You assume the entire risk +arising out of the use or performance of the licensed software, or any systems +you design using the licensed software (if any).

+ +

10. +       INDEMNITY. You agree to fully +defend and indemnify NXP from all claims, liabilities, and costs (including +reasonable attorney’s fees) related to (1) your use (including your +subcontractor’s or distributee’s use, if permitted) +of the Licensed Software or (2) your violation of the terms and conditions of +this Agreement.

+ +

11. +       LIMITATION OF LIABILITY.  +EXCLUDING LIABILITY FOR A BREACH OF SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS +AND RESTRICTIONS), SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER +SECTION 10 (INDEMNITY), IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN +CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL +OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF +USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR +REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP’S TOTAL +LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF +OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS +AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION +WITH THE LICENSED SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR +DAMAGES ARE CLAIMED.

+ +

12. +       EXPORT COMPLIANCE. Each party shall +comply with all applicable export and import control laws and regulations +including but not limited to the US Export Administration Regulation (including +restrictions on certain military end uses and military end users as specified +in Section 15 C.F.R. § 744.21 and prohibited party lists issued by other +federal governments), Catch-all regulations and all national and international +embargoes. Each party further agrees that it will not knowingly transfer, +divert, export or re-export, directly or indirectly, any product, software, +including software source code, or technology restricted by such regulations or +by other applicable national regulations, received from the other party under +this Agreement, or any direct product of such software or technical data to any +person, firm, entity, country or destination to which such transfer, diversion, +export or re-export is restricted or prohibited, without obtaining prior +written authorization from the applicable competent government authorities to +the extent required by those laws.

+ +

13.   GOVERNMENT +CONTRACT COMPLIANCE

+ +

13.1.      +If you sell Authorized Systems directly to any government or public entity, +including U.S., state, local, foreign or international governments or public +entities, or indirectly via a prime contractor or subcontractor of such +governments or entities, NXP makes no representations, certifications, or +warranties whatsoever about compliance with government or public entity +acquisition statutes or regulations, including, without limitation, statutes or +regulations that may relate to pricing, quality, origin or content.

+ +

13.2.      +The Licensed Software has been developed at private expense and is a “Commercial +Item” as defined in 48 C.F.R. Section 2.101, consisting of “Commercial Computer +Software”, and/or “Commercial Computer Software Documentation,” as such terms +are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as +applicable) and may only be licensed to or shared with U.S. Government end +users in object code form as part of, or embedded within, Authorized Systems. +Any agreement pursuant to which you share the Licensed Software will include a +provision that reiterates the limitations of this document and requires all +sub-agreements to similarly contain such limitations. 

+ +

14. +       CRITICAL APPLICATIONS.  In some cases, NXP +may promote certain software for use in the development of, or for +incorporation into, products or services (a) used in applications requiring +fail-safe performance or (b) in which failure could lead to death, personal +injury, or severe physical or environmental damage (these products and services +are referred to as “Critical Applications”). NXP’s goal is to educate customers +so that they can design their own end-product solutions to meet applicable +functional safety standards and requirements. Licensee makes the ultimate +design decisions regarding its products and is solely responsible for +compliance with all legal, regulatory, safety, and security related +requirements concerning its products, regardless of any information or support +that may be provided by NXP. As such, Licensee assumes all risk related to use +of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE +FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee +will indemnify and hold NXP harmless from any claims, liabilities, damages and +associated costs and expenses (including attorneys’ fees) that NXP may incur +related to Licensee’s incorporation of the Licensed Software in a Critical +Application.

+ +

15. +       CHOICE OF LAW; VENUE.  This Agreement will be governed by, construed, and enforced in +accordance with the laws of The Netherlands, without regard to conflicts of +laws principles, will apply to all matters relating to this Agreement or the +Licensed Software, and you agree that any litigation will be subject to the +exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United +Nations Convention on Contracts for the International Sale of Goods will not +apply to this document. 

+ +

16. +       CONFIDENTIAL INFORMATION.  Subject to the license grants and restrictions contained +herein, you must treat the Licensed Software as confidential information and +you agree to retain the Licensed Software in confidence perpetually. You may +not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and +employees, or subcontractors in accordance with Section 2.5, who have a need to +know of the Licensed Software and who have executed written agreements +obligating them to protect such Licensed Software to at least the same degree +of confidentiality as in this Agreement. You agree to use the same degree of +care, but no less than a reasonable degree of care, with the Licensed Software +as you do with your own confidential information. You may disclose Licensed +Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to +disclosure, which you only disclose the minimum of the required information, +and that you allow NXP the opportunity to object to such court or other legal +body requiring such disclosure.

+ +

17. +      TRADEMARKS.  You are not +authorized to use any NXP trademarks, brand names, or logos.

+ +

18. +       ENTIRE AGREEMENT.  This +Agreement constitutes the entire agreement between you and NXP regarding the +subject matter of this Agreement, and supersedes all prior communications, +negotiations, understandings, agreements or +representations, either written or oral, if any. This Agreement may only be +amended in written form, signed by you and NXP.

+ +

19. +       SEVERABILITY.  If any +provision of this Agreement is held for any reason to be invalid or +unenforceable, then the remaining provisions of this Agreement will be +unimpaired and, unless a modification or replacement of the invalid or +unenforceable provision is further held to deprive you or NXP of a material +benefit, in which case the Agreement will immediately terminate, the invalid or +unenforceable provision will be replaced with a provision that is valid and +enforceable and that comes closest to the intention underlying the invalid or +unenforceable provision.

+ +

20. +       NO WAIVER.  The waiver by NXP +of any breach of any provision of this Agreement will not operate or be +construed as a waiver of any other or a subsequent breach of the same or a +different provision.

+ +

21. +       AUDIT.  You will keep full, clear and accurate records with respect to your compliance +with the limited license rights granted under this Agreement for three years +following expiration or termination of this Agreement. NXP will have the right, +either itself or through an independent certified public accountant to examine +and audit, at NXP’s expense, not more than once a year, and during normal +business hours, all such records that may bear upon your compliance with the +limited license rights granted above. You must make prompt adjustment to +compensate for any errors and/or omissions disclosed by such examination or +audit.

+ +

22. +       NOTICES.             +All notices and communications under this Agreement will be made in +writing, and will be effective when received at the following addresses: 

+ +

NXP:    

+ +

NXP B.V.

+ +

High +Tech Campus 60

+ +

5656 +AG Eindhoven

+ +

The +Netherlands

+ +

ATTN: Legal Department

+ +

                    

+ +

You:    

+ +

The address provided at +registration will be used.

+ +

 

+ +

23. +       RELATIONSHIP OF THE PARTIES.     +The parties are independent contractors. Nothing in this Agreement will be +construed to create any partnership, joint venture, or similar relationship. +Neither party is authorized to bind the other to any obligations with third +parties.

+ +

24. +       SUCCESSION AND ASSIGNMENT.   +This Agreement will be binding upon and inure to the benefit of the parties and +their permitted successors and assigns.  You may not assign this +Agreement, or any part of this Agreement, without the prior written approval of +NXP, which approval will not be unreasonably withheld or delayed. NXP may +assign this Agreement, or any part of this Agreement, in its sole discretion.

+ +

25.       PRIVACY. By agreeing to this +Agreement and/or utilizing the Licensed Software, Licensee consents to use of +certain personal information, including but not limited to name, email address, +and location, for the purpose of NXP’s internal analysis regarding future software +offerings.  NXP’s complete Privacy +Statement can be found at: https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACTICES.

+ + + +

 

+ +

 

+ +

 

+ +

 

+ +
+ + +

 

+ +

APPENDIX A

+ +

Other License Grants and Restrictions:

+ +

 

+ +

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+ +
+ + + + diff --git a/components/els_pkc/ReleaseNotes.txt b/components/els_pkc/ReleaseNotes.txt new file mode 100644 index 000000000..44cea882d --- /dev/null +++ b/components/els_pkc/ReleaseNotes.txt @@ -0,0 +1,97 @@ +CLNS SDK (1.7.0) Release Notes + +- Release: RW61x_PRC +- Version: CLNS_SDK_1.7.0 +- Date: 2023-09-15 +- Link to Nexus RepositoryManager: https://nl-nxrm.sw.nxp.com/service/rest/repository/browse/cccs-releases-raw/ +- Link to Bitbucket: tags/sdk_v1.7.0_prc +- Compiler: ARMCLANG keilmdk 533 +--- Test Target: + - RW610 A0 Sample +--- CLNS memory consumption: static_library/RW61x/libclns.a + TEXT RO RW ZI TOTAL_CONSUMPTION + 83816 24421 0 0 108237 + +--- New Features + - MISRA C-2012 mandatory and required violations resolved + - mcuxClHash component reworked and split into mcuxClHash and (new) mcuxClHashModes components + - Fixed build system bug which caused that feature flag NXPCL_FEATURE_ELS_LINK_BASE_ADDRESS was not removed from file ip_platform.h + - Prevent compiler optimization in function mcuxClMemory_copy which changed byte access to (unaligned) word access + - mcuxClEls_Ecc_Keygen_Sign_Verify_example buffer alignment fixed + +--- Features: + - Components included: mcuxClAead, mcuxClAeadModes, mcuxClAes, mcuxClCipher, mcuxClCipherModes, mcuxClCore, + mcuxClEcc, mcuxClEls, mcuxClExample, mcuxClHash, mcuxClHashModes, mcuxClKey, mcuxClMac, mcuxClMacModes, mcuxClMath, mcuxClMemory, + mcuxClPadding, mcuxClPkc, mcuxClPrng, mcuxClPsaDriver, mcuxClRandom, mcuxClRandomModes, mcuxClRsa, mcuxClSession, + mcuxClTrng, mcuxCsslCPreProcessor, mcuxCsslDataIntegrity, mcuxCsslFlowProtection, mcuxCsslMemory, mcuxCsslParamIntegrity, mcuxCsslSecureCounter + +--- Known Issues Limitations: + - platform_specific_headers.h: + #include "fsl_device_registers.h" + // #include "RW610.h" + // #include "RW610_features.h" + // #include "system_RW610.h" + - Cert-C / Coverity static analysis violations to be cleaned up + - When MCUXCLECC_STATUS_RNG_ERROR or MCUXCLRSA_STATUS_RNG_ERROR is returned the security counter is not guaranteed to be balanced properly + +- Release: MCXN_PRC +- Version: CLNS_SDK_1.7.0 +- Date: 2023-09-15 +- Link to Nexus RepositoryManager: https://nl-nxrm.sw.nxp.com/service/rest/repository/browse/cccs-releases-raw/ +- Link to Bitbucket: tags/sdk_v1.7.0_prc +- Compiler: IAR Compiler v.8.40.1 +--- Test Target: + - MCXN sample +--- CLNS memory consumption: static_library/mcxn/libclns.a + TEXT RO RW ZI TOTAL_CONSUMPTION + 72506 19752 0 0 92258 + + +--- New Features: + - Maintenance release + - mcuxClHash component reworked and split into mcuxClHash and (new) mcuxClHashModes components + - Fixed build system bug which caused that feature flag NXPCL_FEATURE_ELS_LINK_BASE_ADDRESS was not removed from file ip_platform.h + - Prevent compiler optimization in function mcuxClMemory_copy which changed byte access to (unaligned) word access + - mcuxClEls_Ecc_Keygen_Sign_Verify_example buffer alignment fixed + +--- Features: + - Components included: mcuxClAead, mcuxClAeadModes, mcuxClAes, mcuxClCipher, mcuxClCipherModes, mcuxClCore, + mcuxClEcc, mcuxClEls, mcuxClExample, mcuxClHash, mcuxClHashModes, mcuxClKey, mcuxClMac, mcuxClMacModes, mcuxClMath, mcuxClMemory, + mcuxClOsccaPkc, mcuxClOsccaSm3, mcuxClPadding, mcuxClPkc, mcuxClPrng, mcuxClRandom, mcuxClRandomModes, mcuxClRsa, mcuxClSession, + mcuxClTrng, mcuxCsslCPreProcessor, mcuxCsslDataIntegrity, mcuxCsslFlowProtection, mcuxCsslMemory, mcuxCsslParamIntegrity, mcuxCsslSecureCounter + +--- Known Issues Limitations: + - par_els_semaphore_master tests failed due to test issues (reading MASTER ID SFR from ELS "secure" BASE in non-secure mode, missing exception/fault handling when exceptions/faults occur in non-secure) + - Cert-C / Coverity static analysis violations to be cleaned up + - When MCUXCLECC_STATUS_RNG_ERROR or MCUXCLRSA_STATUS_RNG_ERROR is returned the security counter is not guaranteed to be balanced + +- Release: LPC_PRC +- Version: CLNS_SDK_1.7.0 +- Date: 2023-09-15 +- Link to Nexus RepositoryManager: https://nl-nxrm.sw.nxp.com/service/rest/repository/browse/cccs-releases-raw/ +- Link to Bitbucket: tags/sdk_v1.7.0_prc +- Compiler: IAR Compiler v.8.40.1 +--- Test Target: + - LPC55S36_sample +--- CLNS memory consumption: static_library/lpc/libclns.a + TEXT RO RW ZI TOTAL_CONSUMPTION + 61878 19136 0 4 81018 + + +--- New Features: + - Maintenance release + - mcuxClHash component reworked and split into mcuxClHash and (new) mcuxClHashModes components + - Fixed build system bug which caused that feature flag NXPCL_FEATURE_ELS_LINK_BASE_ADDRESS was not removed from file ip_platform.h + - Prevent compiler optimization in function mcuxClMemory_copy which changed byte access to (unaligned) word access + - mcuxClEls_Ecc_Keygen_Sign_Verify_example buffer alignment fixed + +--- Features: + - Components included: mcuxClAead, mcuxClAeadModes, mcuxClAes, mcuxClCipher, mcuxClCipherModes, mcuxClCore, + mcuxClEcc, mcuxClEls, mcuxClExample, mcuxClHash, mcuxClHashModes, mcuxClKey, mcuxClMac, mcuxClMacModes, mcuxClMath, mcuxClMemory, + mcuxClPadding, mcuxClPkc, mcuxClPrng, mcuxClRandom, mcuxClRandomModes, mcuxClRsa, mcuxClSession, + mcuxCsslCPreProcessor, mcuxCsslDataIntegrity, mcuxCsslFlowProtection, mcuxCsslMemory, mcuxCsslParamIntegrity, mcuxCsslSecureCounter + +--- Known Issues Limitations: + - Negative tests which try to provoke an uninitialized PRNG error had to be disabled since ELS_ITERATIVE_SEEDING inherently always initalizes the PRNG (sim_random_ncGenerate_negative, par_ecc_pkc_keygen_rng_error, par_ecc_pkc_sign_rng_error) + - Cert-C / Coverity static analysis violations to be cleaned up + - When MCUXCLECC_STATUS_RNG_ERROR or MCUXCLRSA_STATUS_RNG_ERROR is returned the security counter is not guaranteed to be balanced \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00002.html b/components/els_pkc/doc/mcxn/html/a00002.html new file mode 100644 index 000000000..2d8bf0286 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00002.html @@ -0,0 +1,293 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c File Reference
+
+
+ +

Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example)
 Performs AES-128 ECB encryption using mcuxClEls functions. More...
 
+ + + + + + + + + + + + + +

+Variables

static uint8_t const aes128_input [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Plaintext input for the AES encryption. More...
 
static uint8_t const aes128_expected_output [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Expected ciphertext output of the AES encryption. More...
 
static uint32_t const aes128_key [MCUXCLELS_CIPHER_KEY_SIZE_AES_128/sizeof(uint32_t)]
 Key for the AES encryption. More...
 
static uint8_t aes128_output [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Destination buffer to receive the ciphertext output of the AES encryption. More...
 
+

Detailed Description

+

Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example )
+
+ +

Performs AES-128 ECB encryption using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ aes128_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Plaintext input for the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_expected_output

+ +
+
+ + + + + +
+ + + + +
uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Expected ciphertext output of the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_key

+ +
+
+ + + + + +
+ + + + +
uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128/sizeof(uint32_t)]
+ 		+static
+
+ +

Key for the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_output

+ +
+
+ + + + + +
+ + + + +
uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Destination buffer to receive the ciphertext output of the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00002.js b/components/els_pkc/doc/mcxn/html/a00002.js new file mode 100644 index 000000000..d41edef8f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00002.js @@ -0,0 +1,8 @@ +var a00002 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00002.html#a4557ce4897e01774148f2f764c833b3a", null ], + [ "aes128_input", "a00002.html#ad27e8e7cceb19331fe1611f2eeb66dc8", null ], + [ "aes128_expected_output", "a00002.html#a8f724484dd059cbe14851b0a799c0890", null ], + [ "aes128_key", "a00002.html#af381139a6e72029d4fa91365ecd128dc", null ], + [ "aes128_output", "a00002.html#aac664c77a3ccf9254ab1afd4ce762854", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00005.html b/components/els_pkc/doc/mcxn/html/a00005.html new file mode 100644 index 000000000..ce050124f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00005.html @@ -0,0 +1,322 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c File Reference
+
+
+ +

Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls. +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example)
 Performs AES-128 CBC encryption using mcuxClEls functions. More...
 
+ + + + + + + + + + + + + + + + +

+Variables

static uint8_t const aes128_input [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Plaintext input for the AES encryption. More...
 
static uint8_t aes128_iv [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 IV of the AES encryption. More...
 
static uint8_t const aes128_expected_output [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Expected ciphertext output of the AES encryption. More...
 
static uint32_t const aes128_key [MCUXCLELS_CIPHER_KEY_SIZE_AES_128/sizeof(uint32_t)]
 Key for the AES encryption. More...
 
static uint8_t aes128_output [MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
 Destination buffer to receive the ciphertext output of the AES encryption. More...
 
+

Detailed Description

+

Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example )
+
+ +

Performs AES-128 CBC encryption using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ aes128_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Plaintext input for the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_iv

+ +
+
+ + + + + +
+ + + + +
uint8_t aes128_iv[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

IV of the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_expected_output

+ +
+
+ + + + + +
+ + + + +
uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Expected ciphertext output of the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_key

+ +
+
+ + + + + +
+ + + + +
uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128/sizeof(uint32_t)]
+ 		+static
+
+ +

Key for the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+ +

◆ aes128_output

+ +
+
+ + + + + +
+ + + + +
uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]
+ 		+static
+
+ +

Destination buffer to receive the ciphertext output of the AES encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00005.js b/components/els_pkc/doc/mcxn/html/a00005.js new file mode 100644 index 000000000..48d3191e2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00005.js @@ -0,0 +1,9 @@ +var a00005 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00005.html#a771a0ec79a4dd825868d4be9bc76c6b7", null ], + [ "aes128_input", "a00005.html#ad27e8e7cceb19331fe1611f2eeb66dc8", null ], + [ "aes128_iv", "a00005.html#a8eef9cffb37af88e29a455967c68e7bc", null ], + [ "aes128_expected_output", "a00005.html#a8f724484dd059cbe14851b0a799c0890", null ], + [ "aes128_key", "a00005.html#af381139a6e72029d4fa91365ecd128dc", null ], + [ "aes128_output", "a00005.html#aac664c77a3ccf9254ab1afd4ce762854", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00008.html b/components/els_pkc/doc/mcxn/html/a00008.html new file mode 100644 index 000000000..98be7ffa3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00008.html @@ -0,0 +1,330 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Ecc_Keygen_Sign_Verify_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c File Reference
+
+
+ +

Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_ELS_Key_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Ecc_Keygen_Sign_Verify_example)
 Performs SHA2-256 hashing using mcuxClEls functions. More...
 
+ + + + + + + + + + + + + + + + +

+Variables

static uint32_t const ecc_digest [MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256/sizeof(uint32_t)]
 Pre-hashed data to be signed. More...
 
static uint32_t ecc_public_key [MCUXCLELS_ECC_PUBLICKEY_SIZE/sizeof(uint32_t)]
 Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation. More...
 
static uint32_t ecc_signature [MCUXCLELS_ECC_SIGNATURE_SIZE/sizeof(uint32_t)]
 Destination buffer to receive the signature of the mcuxClEls_EccSign_Async operation. More...
 
static uint32_t ecc_signature_r [MCUXCLELS_ECC_SIGNATURE_R_SIZE/sizeof(uint32_t)]
 Destination buffer to receive the signature part r of the VerifyOptions operation. More...
 
static uint32_t ecc_signature_and_public_key [(MCUXCLELS_ECC_SIGNATURE_SIZE+MCUXCLELS_ECC_PUBLICKEY_SIZE)/sizeof(uint32_t)]
 Concatenation of the ECC signature and public key, needed for the mcuxClEls_EccVerify_Async operation. More...
 
+

Detailed Description

+

Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Ecc_Keygen_Sign_Verify_example )
+
+ +

Performs SHA2-256 hashing using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

deleted keyIdx keySlot

+

Disable the ELS

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ ecc_digest

+ +
+
+ + + + + +
+ + + + +
uint32_t const ecc_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256/sizeof(uint32_t)]
+ 		+static
+
+ +

Pre-hashed data to be signed.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ ecc_public_key

+ +
+
+ + + + + +
+ + + + +
uint32_t ecc_public_key[MCUXCLELS_ECC_PUBLICKEY_SIZE/sizeof(uint32_t)]
+ 		+static
+
+ +

Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ ecc_signature

+ +
+
+ + + + + +
+ + + + +
uint32_t ecc_signature[MCUXCLELS_ECC_SIGNATURE_SIZE/sizeof(uint32_t)]
+ 		+static
+
+ +

Destination buffer to receive the signature of the mcuxClEls_EccSign_Async operation.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ ecc_signature_r

+ +
+
+ + + + + +
+ + + + + + + + +
static mcuxClEls_EccByte_t ecc_signature_r (uint32_t )
+ 		+static
+
+ +

Destination buffer to receive the signature part r of the VerifyOptions operation.

+

Output buffer for the signature part r of the mcuxClEls_KeyImportPuk_Async operation.

+

Must be word-aligned!

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ ecc_signature_and_public_key

+ +
+
+ + + + + +
+ + + + +
uint32_t ecc_signature_and_public_key[(MCUXCLELS_ECC_SIGNATURE_SIZE+MCUXCLELS_ECC_PUBLICKEY_SIZE)/sizeof(uint32_t)]
+ 		+static
+
+ +

Concatenation of the ECC signature and public key, needed for the mcuxClEls_EccVerify_Async operation.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00008.js b/components/els_pkc/doc/mcxn/html/a00008.js new file mode 100644 index 000000000..e91d89f7e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00008.js @@ -0,0 +1,9 @@ +var a00008 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00008.html#a7871444a5008d1d5409e35c7c1cbd1d3", null ], + [ "ecc_digest", "a00008.html#ae951d0a54ca7834571b2870fdee3ee9c", null ], + [ "ecc_public_key", "a00008.html#ae2a6bb3aae38a75b559936cb2a304daa", null ], + [ "ecc_signature", "a00008.html#a0c919da2c9c7078b5c7243da9fa76322", null ], + [ "ecc_signature_r", "a00008.html#a9723d2c5493f5403895e91d633105402", null ], + [ "ecc_signature_and_public_key", "a00008.html#a94d4ee9f78d77b0c9e977400ad498190", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00011.html b/components/els_pkc/doc/mcxn/html/a00011.html new file mode 100644 index 000000000..7a85fa0e7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00011.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Common_Get_Info_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Common_Get_Info_example.c File Reference
+
+
+ +

Example of version and configuration load functions. +More...

+
#include <mcuxCl_clns.h>
+#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Common_Get_Info_example)
 
+

Detailed Description

+

Example of version and configuration load functions.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Common_Get_Info_example )
+
+

Initialize ELS, Enable the ELS

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00011.js b/components/els_pkc/doc/mcxn/html/a00011.js new file mode 100644 index 000000000..2d37e7aeb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00011.js @@ -0,0 +1,4 @@ +var a00011 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00011.html#a2d5de980923b27edc61a1c9ffb521a1e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00014.html b/components/els_pkc/doc/mcxn/html/a00014.html new file mode 100644 index 000000000..02d002637 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00014.html @@ -0,0 +1,264 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Hash_Sha224_One_Block_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Hash_Sha224_One_Block_example.c File Reference
+
+
+ +

Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha224_One_Block_example)
 Performs SHA2-224 hashing using mcuxClEls functions. More...
 
+ + + + + + + + + + +

+Variables

static uint8_t const sha224_padded_input [MCUXCLELS_HASH_BLOCK_SIZE_SHA_224]
 Data input for SHA2-224 hashing. More...
 
static uint8_t sha224_reference_digest [MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224]
 Expected hash value. More...
 
static uint8_t sha2_224_digest [MCUXCLELS_HASH_STATE_SIZE_SHA_224]
 Destination buffer to receive the hash output of the SHA2-224 hashing. More...
 
+

Detailed Description

+

Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha224_One_Block_example )
+
+ +

Performs SHA2-224 hashing using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ sha224_padded_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const sha224_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_224]
+ 		+static
+
+ +

Data input for SHA2-224 hashing.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ sha224_reference_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha224_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224]
+ 		+static
+
+ +

Expected hash value.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ sha2_224_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha2_224_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_224]
+ 		+static
+
+ +

Destination buffer to receive the hash output of the SHA2-224 hashing.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00014.js b/components/els_pkc/doc/mcxn/html/a00014.js new file mode 100644 index 000000000..f02e63c35 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00014.js @@ -0,0 +1,7 @@ +var a00014 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00014.html#ab89d2312fc5c2fdc0298cc1ae1f278e3", null ], + [ "sha224_padded_input", "a00014.html#a3a90d0719630869e92e2a830633b3276", null ], + [ "sha224_reference_digest", "a00014.html#abf0bb6879a755eadc984fc84923cc0bf", null ], + [ "sha2_224_digest", "a00014.html#ad953a0e00811066696ef763b14c096f9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00017.html b/components/els_pkc/doc/mcxn/html/a00017.html new file mode 100644 index 000000000..a8abbb0aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00017.html @@ -0,0 +1,264 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Hash_Sha256_One_Block_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Hash_Sha256_One_Block_example.c File Reference
+
+
+ +

Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha256_One_Block_example)
 Performs SHA2-256 hashing using mcuxClEls functions. More...
 
+ + + + + + + + + + +

+Variables

static uint8_t const sha256_padded_input [MCUXCLELS_HASH_BLOCK_SIZE_SHA_256]
 Data input for SHA2-256 hashing. More...
 
static uint8_t sha256_reference_digest [MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256]
 Expected hash value. More...
 
static uint8_t sha2_256_digest [MCUXCLELS_HASH_STATE_SIZE_SHA_256]
 Destination buffer to receive the hash output of the SHA2-256 hashing. More...
 
+

Detailed Description

+

Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha256_One_Block_example )
+
+ +

Performs SHA2-256 hashing using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ sha256_padded_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const sha256_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_256]
+ 		+static
+
+ +

Data input for SHA2-256 hashing.

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ sha256_reference_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha256_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256]
+ 		+static
+
+ +

Expected hash value.

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ sha2_256_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha2_256_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_256]
+ 		+static
+
+ +

Destination buffer to receive the hash output of the SHA2-256 hashing.

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00017.js b/components/els_pkc/doc/mcxn/html/a00017.js new file mode 100644 index 000000000..cb168ef67 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00017.js @@ -0,0 +1,7 @@ +var a00017 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00017.html#ac6870823b93f74e0bc36a7d1d471bd9d", null ], + [ "sha256_padded_input", "a00017.html#a890aa9aa5c130271cfeb0c43324c4e51", null ], + [ "sha256_reference_digest", "a00017.html#ab00b3a897c4bba2fc29a541a23c4a0ea", null ], + [ "sha2_256_digest", "a00017.html#aff61e539755c5c8c4b21046c976abdfa", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00020.html b/components/els_pkc/doc/mcxn/html/a00020.html new file mode 100644 index 000000000..14377cf59 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00020.html @@ -0,0 +1,264 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Hash_Sha384_One_Block_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Hash_Sha384_One_Block_example.c File Reference
+
+
+ +

Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha384_One_Block_example)
 Performs SHA2-384 hashing using mcuxClEls functions. More...
 
+ + + + + + + + + + +

+Variables

static uint8_t const sha384_padded_input [MCUXCLELS_HASH_BLOCK_SIZE_SHA_384]
 Data input for SHA2-384 hashing. More...
 
static uint8_t sha384_reference_digest [MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384]
 Expected hash value. More...
 
static uint8_t sha2_384_digest [MCUXCLELS_HASH_STATE_SIZE_SHA_384]
 Destination buffer to receive the hash output of the SHA2-384 hashing. More...
 
+

Detailed Description

+

Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha384_One_Block_example )
+
+ +

Performs SHA2-384 hashing using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ sha384_padded_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const sha384_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_384]
+ 		+static
+
+ +

Data input for SHA2-384 hashing.

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ sha384_reference_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha384_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384]
+ 		+static
+
+ +

Expected hash value.

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ sha2_384_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha2_384_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_384]
+ 		+static
+
+ +

Destination buffer to receive the hash output of the SHA2-384 hashing.

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00020.js b/components/els_pkc/doc/mcxn/html/a00020.js new file mode 100644 index 000000000..8825e48c8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00020.js @@ -0,0 +1,7 @@ +var a00020 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00020.html#a5a28e0b6909b5d91b26a95077092fae7", null ], + [ "sha384_padded_input", "a00020.html#a157042750820e99bfa2441a0fcba481e", null ], + [ "sha384_reference_digest", "a00020.html#a031991d5ae2823da0e9b5bd7c854e9b3", null ], + [ "sha2_384_digest", "a00020.html#a4fdd7260badc8d686d79df408edb7c21", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00023.html b/components/els_pkc/doc/mcxn/html/a00023.html new file mode 100644 index 000000000..a325f18af --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00023.html @@ -0,0 +1,264 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Hash_Sha512_One_Block_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Hash_Sha512_One_Block_example.c File Reference
+
+
+ +

Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha512_One_Block_example)
 Performs SHA2-512 hashing using mcuxClEls functions. More...
 
+ + + + + + + + + + +

+Variables

static uint8_t const sha512_padded_input [MCUXCLELS_HASH_BLOCK_SIZE_SHA_512]
 Data input for SHA2-512 hashing. More...
 
static uint8_t sha512_reference_digest [MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512]
 Expected hash value. More...
 
static uint8_t sha2_512_digest [MCUXCLELS_HASH_STATE_SIZE_SHA_512]
 Destination buffer to receive the hash output of the SHA2-512 hashing. More...
 
+

Detailed Description

+

Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Hash_Sha512_One_Block_example )
+
+ +

Performs SHA2-512 hashing using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Disable the ELS

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ sha512_padded_input

+ +
+
+ + + + + +
+ + + + +
uint8_t const sha512_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_512]
+ 		+static
+
+ +

Data input for SHA2-512 hashing.

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ sha512_reference_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha512_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512]
+ 		+static
+
+ +

Expected hash value.

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ sha2_512_digest

+ +
+
+ + + + + +
+ + + + +
uint8_t sha2_512_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_512]
+ 		+static
+
+ +

Destination buffer to receive the hash output of the SHA2-512 hashing.

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00023.js b/components/els_pkc/doc/mcxn/html/a00023.js new file mode 100644 index 000000000..4fa03cda6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00023.js @@ -0,0 +1,7 @@ +var a00023 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00023.html#aca162de2f88b777e78145615790dde8d", null ], + [ "sha512_padded_input", "a00023.html#aa6ed8b927262ff98775b8726955ef8e0", null ], + [ "sha512_reference_digest", "a00023.html#a1e3cfc0c29a9863abf6ecd8c022d05ab", null ], + [ "sha2_512_digest", "a00023.html#a0d806e17a1cf2005916602c6ebd303f2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00026.html b/components/els_pkc/doc/mcxn/html/a00026.html new file mode 100644 index 000000000..cc8f8fc02 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00026.html @@ -0,0 +1,174 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Rng_Prng_Get_Random_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Rng_Prng_Get_Random_example.c File Reference
+
+
+ +

Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_ELS_Key_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Rng_Prng_Get_Random_example)
 Uses random number from PRNG of ELS. More...
 
+

Detailed Description

+

Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Rng_Prng_Get_Random_example )
+
+ +

Uses random number from PRNG of ELS.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

deleted 18 keySlot

+

Disable the ELS

+
Examples
mcuxClEls_Rng_Prng_Get_Random_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00026.js b/components/els_pkc/doc/mcxn/html/a00026.js new file mode 100644 index 000000000..35d203db5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00026.js @@ -0,0 +1,4 @@ +var a00026 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00026.html#a4533123497ea62887db3256587ae76ac", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00029.html b/components/els_pkc/doc/mcxn/html/a00029.html new file mode 100644 index 000000000..2ec0c2d79 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00029.html @@ -0,0 +1,234 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Tls_Master_Key_Session_Keys_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClEls_Tls_Master_Key_Session_Keys_example.c File Reference
+
+
+ +

TLS key derivation example. +More...

+
#include <mcuxClEls.h>
+#include <mcuxClMemory.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_ELS_Key_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Tls_Master_Key_Session_Keys_example)
 Performs key derivation for TLS protocol. More...
 
+ + + + + + + + + + + + + + + + +

+Variables

static mcuxClEls_EccByte_t ecc_public_key_client [MCUXCLELS_ECC_PUBLICKEY_SIZE]
 Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation. More...
 
+static mcuxClEls_EccByte_t ecc_public_key_server [MCUXCLELS_ECC_PUBLICKEY_SIZE]
 
+static uint8_t derivation_data [MCUXCLELS_TLS_DERIVATIONDATA_SIZE]
 
+static uint8_t client_random [MCUXCLELS_TLS_RANDOM_SIZE]
 
+static uint8_t server_random [MCUXCLELS_TLS_RANDOM_SIZE]
 
+static uint8_t master_key_string []
 
+static uint8_t key_expansion_string []
 
+

Detailed Description

+

TLS key derivation example.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Tls_Master_Key_Session_Keys_example )
+
+ +

Performs key derivation for TLS protocol.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

< [in] The TLS derivation data

+

< [in] Desired key properties. Only mcuxClEls_KeyProp_t::upprot_priv and mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.

+

< [in] The index of the TLS pre-master key, which is overwritten with the master key

+

< [in] The TLS derivation data

+

< [in] Desired key properties. Only mcuxClEls_KeyProp_t::upprot_priv and mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.

+

< [in] The index of the TLS master key, which is overwritten with one of the session keys.

+

deleted keyIdxPrivClient keySlot

+

deleted keyIdxPrivServer keySlot

+

deleted i keySlot

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ ecc_public_key_client

+ +
+
+ + + + + +
+ + + + +
mcuxClEls_EccByte_t ecc_public_key_client[MCUXCLELS_ECC_PUBLICKEY_SIZE]
+ 		+static
+
+ +

Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00029.js b/components/els_pkc/doc/mcxn/html/a00029.js new file mode 100644 index 000000000..ee8d31019 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00029.js @@ -0,0 +1,11 @@ +var a00029 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00029.html#afca899ba16d4b475a0e780589dbfc560", null ], + [ "ecc_public_key_client", "a00029.html#a0f8366d89d3959a37ba157fad828c3f5", null ], + [ "ecc_public_key_server", "a00029.html#ad46e921046ed161d25a77f77fafeb4e8", null ], + [ "derivation_data", "a00029.html#a41dc6b7ee183699c7c329f650ac0942b", null ], + [ "client_random", "a00029.html#a5dea7e556f3948d30c543999250e9209", null ], + [ "server_random", "a00029.html#a39c9969896b3113bb25fc2643a6ea41e", null ], + [ "master_key_string", "a00029.html#a433bc05dd30cd1802dbea7a904e77065", null ], + [ "key_expansion_string", "a00029.html#abfe9105525edfe55ab75c875f9d7a34a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00032.html b/components/els_pkc/doc/mcxn/html/a00032.html new file mode 100644 index 000000000..eb6474358 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00032.html @@ -0,0 +1,416 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls/mcuxClEls_Key_Import_Puk_DER_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions | +Variables
+
+
mcuxClEls_Key_Import_Puk_DER_example.c File Reference
+
+
+ +

Example of PuK import from a DER-encoded certificate using the ELS (CLNS component mcuxClEls) +More...

+
#include <mcuxClEls.h>
+#include <mcuxClMemory.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_ELS_Key_Helper.h>
+#include <mcuxClExample_RFC3394_Helper.h>
+
+ + + +

+Macros

+#define SHA256_BLOCK_SIZE
 
+ + + + + + + +

+Functions

static mcuxClEls_EccByte_t ecc_signature [MCUXCLELS_ECC_SIGNATURE_SIZE] __attribute__ ((aligned(4)))
 Output buffer for the signature of the mcuxClEls_EccSign_Async operation. More...
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Key_Import_Puk_DER_example)
 Example for PuK import from DER-encoded certificate using mcuxClEls functions. More...
 
+ + + + + + + + + + + + + + + + + + + + + +

+Variables

static uint8_t const der_certificate [450U]
 Key wrapping key. More...
 
static size_t der_certificate_offset_pbk
 Offset of the public key that we want to import within the certificate. More...
 
static size_t der_certificate_len_without_signature
 Total length of the certificate without signature. More...
 
static uint8_t key_rfc3394 [MCUXCLELS_RFC3394_CONTAINER_SIZE_P256]
 Output buffer for the wrapped ECC public root key. More...
 
static uint8_t der_certificate_import [sizeof(der_certificate)+SHA256_BLOCK_SIZE]
 Output buffer for the certificate and padding. More...
 
static mcuxClEls_EccByte_t ecc_root_public_key [MCUXCLELS_ECC_PUBLICKEY_SIZE]
 Output buffers for the public key of the mcuxClEls_EccKeyGen_Async operation. More...
 
+static mcuxClEls_EccByte_t ecc_root_public_key_switched [MCUXCLELS_ECC_PUBLICKEY_SIZE]
 
+

Detailed Description

+

Example of PuK import from a DER-encoded certificate using the ELS (CLNS component mcuxClEls)

+

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + +
+ + + + + + + + +
static mcuxClEls_EccByte_t ecc_signature [MCUXCLELS_ECC_SIGNATURE_SIZE] __attribute__ ((aligned(4)) )
+ 		+static
+
+ +

Output buffer for the signature of the mcuxClEls_EccSign_Async operation.

+

Output buffer for the signature part r of the mcuxClEls_KeyImportPuk_Async operation.

+

Must be word-aligned!

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEls_Key_Import_Puk_DER_example )
+
+ +

Example for PuK import from DER-encoded certificate using mcuxClEls functions.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+
    +
  1. Prepare certificate for import by copying certificate without signature and adding SHA-256 padding.
    2. +
  2. Generace ECC key pair and sign the prepared certificate.
    3. +
  3. Provision helper key and key wrapping key.
    4. +
  4. Convert the generated root public key and import it into keystore.
    5. +
+

function that performs RFC3394 key wrapping

+
    +
  1. Import the public key from the certificate into keystore.
    2. +
  2. Verify R and key properties.
    3. +
  3. Cleanup.
    4. +
+

deleted key_idx_helper_key keySlot

+

deleted key_idx_ecc_root_private_key keySlot

+

deleted key_idx_ecc_root_public_key keySlot

+

deleted key_idx_ecc_import_public_key keySlot

+

Disable the ELS

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+

Variable Documentation

+ +

◆ der_certificate

+ +
+
+ + + + + +
+ + + + +
uint8_t const der_certificate[450U]
+ 		+static
+
+ +

Key wrapping key.

+

Raw DER-encoded certificate.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ der_certificate_offset_pbk

+ +
+
+ + + + + +
+ + + + +
size_t der_certificate_offset_pbk
+ 		+static
+
+ +

Offset of the public key that we want to import within the certificate.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ der_certificate_len_without_signature

+ +
+
+ + + + + +
+ + + + +
size_t der_certificate_len_without_signature
+ 		+static
+
+ +

Total length of the certificate without signature.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ key_rfc3394

+ +
+
+ + + + + +
+ + + + +
uint8_t key_rfc3394[MCUXCLELS_RFC3394_CONTAINER_SIZE_P256]
+ 		+static
+
+ +

Output buffer for the wrapped ECC public root key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ der_certificate_import

+ +
+
+ + + + + +
+ + + + +
uint8_t der_certificate_import[sizeof(der_certificate)+SHA256_BLOCK_SIZE]
+ 		+static
+
+ +

Output buffer for the certificate and padding.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ ecc_root_public_key

+ +
+
+ + + + + +
+ + + + +
mcuxClEls_EccByte_t ecc_root_public_key[MCUXCLELS_ECC_PUBLICKEY_SIZE]
+ 		+static
+
+ +

Output buffers for the public key of the mcuxClEls_EccKeyGen_Async operation.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00032.js b/components/els_pkc/doc/mcxn/html/a00032.js new file mode 100644 index 000000000..5bb9fbe8e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00032.js @@ -0,0 +1,13 @@ +var a00032 = +[ + [ "SHA256_BLOCK_SIZE", "a00032.html#a9c1fe69ad43d4ca74b84303a0ed64f2f", null ], + [ "__attribute__", "a00032.html#a3e0329840494bde2557d01ee51c9aa52", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00032.html#afa131c8f7a3740ff4732892b4db16bec", null ], + [ "der_certificate", "a00032.html#a9aaa67299df29bf9b32ac94aa91dde50", null ], + [ "der_certificate_offset_pbk", "a00032.html#af049ea7eafe6bdbb70ce3dd48adca426", null ], + [ "der_certificate_len_without_signature", "a00032.html#a7edd27bd2edabd9a7a5c790b8605cd9a", null ], + [ "key_rfc3394", "a00032.html#adfc408cbf330d6e41a58a910f6a287d0", null ], + [ "der_certificate_import", "a00032.html#adf7528a77c2e6b48821cbed7c0337096", null ], + [ "ecc_root_public_key", "a00032.html#a961fa94f9b6e3852e50ad9417f7a6601", null ], + [ "ecc_root_public_key_switched", "a00032.html#ae8a9e11309b1e008ef85ce7e2fc6fc5b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00035.html b/components/els_pkc/doc/mcxn/html/a00035.html new file mode 100644 index 000000000..ac1b79fa7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00035.html @@ -0,0 +1,193 @@ + + + + + + + +MCUX CLNS: examples/mcuxClAeadModes/mcuxClAeadModes_Multipart_Els_Ccm_Example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClAeadModes_Multipart_Els_Ccm_Example.c File Reference
+
+
+ +

: Example Aead application +More...

+
#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_Key_Helper.h>
+#include <mcuxClEls.h>
+#include <mcuxClSession.h>
+#include <mcuxClKey.h>
+#include <mcuxClAes.h>
+#include <mcuxClAead.h>
+#include <mcuxClAeadModes.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <stdbool.h>
+#include <mcuxClExample_RNG_Helper.h>
+
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Multipart_Els_Ccm_Example)
 
+ + + + + + + + + + + + + +

+Variables

+static const uint8_t msg_plain [24]
 
+static const uint8_t msg_adata [20]
 
+static const uint8_t aes128_iv [12]
 
+static const uint8_t aes128_key [16]
 
+static const uint8_t msg_tag_expected [8]
 
+static const uint8_t msg_enc_expected [24]
 
+

Detailed Description

+

: Example Aead application

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Multipart_Els_Ccm_Example )
+
+

Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL

+

Destroy Session and cleanup Session

+

Disable the ELS

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00035.js b/components/els_pkc/doc/mcxn/html/a00035.js new file mode 100644 index 000000000..cb2b1dff2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00035.js @@ -0,0 +1,10 @@ +var a00035 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00035.html#a39688ef490286a2fed36617ad2c02795", null ], + [ "msg_plain", "a00035.html#a99de0c4caba7ecddb743f4d3b48b6256", null ], + [ "msg_adata", "a00035.html#a531f9f06a2213a464804b219389801fd", null ], + [ "aes128_iv", "a00035.html#a71586523cee0ec4d7cc47a6fa37498e9", null ], + [ "aes128_key", "a00035.html#a3235daa10df637f7ebc03e1fc6506514", null ], + [ "msg_tag_expected", "a00035.html#a077f6105a911bdc7c7e4495da9e07fab", null ], + [ "msg_enc_expected", "a00035.html#a3efbc79cff15a3b2bb3497cd2768062b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00038.html b/components/els_pkc/doc/mcxn/html/a00038.html new file mode 100644 index 000000000..4a42ec6c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00038.html @@ -0,0 +1,193 @@ + + + + + + + +MCUX CLNS: examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Ccm_Example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClAeadModes_Oneshot_Els_Ccm_Example.c File Reference
+
+
+ +

: Example Aead application +More...

+
#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_Key_Helper.h>
+#include <mcuxClEls.h>
+#include <mcuxClSession.h>
+#include <mcuxClKey.h>
+#include <mcuxClAes.h>
+#include <mcuxClAead.h>
+#include <mcuxClAeadModes.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <stdbool.h>
+#include <mcuxClExample_RNG_Helper.h>
+
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Oneshot_Els_Ccm_Example)
 
+ + + + + + + + + + + + + +

+Variables

+static const uint8_t msg_plain [16]
 
+static const uint8_t msg_adata [16]
 
+static const uint8_t aes128_iv [8]
 
+static const uint8_t aes128_key [16]
 
+static const uint8_t msg_tag_expected [6]
 
+static const uint8_t msg_enc_expected [16]
 
+

Detailed Description

+

: Example Aead application

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Oneshot_Els_Ccm_Example )
+
+

Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL

+

Destroy Session and cleanup Session

+

Disable the ELS

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00038.js b/components/els_pkc/doc/mcxn/html/a00038.js new file mode 100644 index 000000000..c15ab57aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00038.js @@ -0,0 +1,10 @@ +var a00038 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00038.html#a54de761e25b3fd9e3b4d7e5b90ebd7ca", null ], + [ "msg_plain", "a00038.html#afdebae21697b493d39c86b98dd7c52d3", null ], + [ "msg_adata", "a00038.html#a43716be4844a1dca0c29d716aa888900", null ], + [ "aes128_iv", "a00038.html#aed4067d92dd4142bd21dac1ce4a79be1", null ], + [ "aes128_key", "a00038.html#a3235daa10df637f7ebc03e1fc6506514", null ], + [ "msg_tag_expected", "a00038.html#a6f401b24b3ff505146c5bd11e6f871f8", null ], + [ "msg_enc_expected", "a00038.html#abe3e86ad1a649c7a4bbd03de069864da", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00041.html b/components/els_pkc/doc/mcxn/html/a00041.html new file mode 100644 index 000000000..3936bf5b9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00041.html @@ -0,0 +1,338 @@ + + + + + + + +MCUX CLNS: examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Gcm_Example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClAeadModes_Oneshot_Els_Gcm_Example.c File Reference
+
+
+ +

: Example Aead application +More...

+
#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_Key_Helper.h>
+#include <mcuxClEls.h>
+#include <mcuxClSession.h>
+#include <mcuxClKey.h>
+#include <mcuxClAes.h>
+#include <mcuxClAead.h>
+#include <mcuxClAeadModes.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <stdbool.h>
+#include <mcuxClExample_RNG_Helper.h>
+
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Oneshot_Els_Gcm_Example)
 
+ + + + + + + + + + + + + + + + + + + +

+Variables

static uint8_t aes128_key [16u]
 Key for the AES encryption. More...
 
static uint8_t aes128_iv [12u]
 IV of the AES encryption. More...
 
static uint8_t const msg_plain [16u]
 Plaintext input for the AES encryption. More...
 
static uint8_t const msg_adata [16u]
 Additional authenticated data. More...
 
static uint8_t const msg_enc_expected [16u]
 Expected ciphertext output of the AES-GCM encryption. More...
 
static uint8_t const msg_tag_expected [16u]
 Expected authentication tag output. More...
 
+

Detailed Description

+

: Example Aead application

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClAeadModes_Oneshot_Els_Gcm_Example )
+
+

Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL

+

Destroy Session and cleanup Session

+

Disable the ELS

+ +
+
+

Variable Documentation

+ +

◆ aes128_key

+ +
+
+ + + + + +
+ + + + +
uint8_t aes128_key[16u]
+ 		+static
+
+ +

Key for the AES encryption.

+ +
+
+ +

◆ aes128_iv

+ +
+
+ + + + + +
+ + + + +
uint8_t aes128_iv[12u]
+ 		+static
+
+ +

IV of the AES encryption.

+ +
+
+ +

◆ msg_plain

+ +
+
+ + + + + +
+ + + + +
uint8_t const msg_plain[16u]
+ 		+static
+
+ +

Plaintext input for the AES encryption.

+ +
+
+ +

◆ msg_adata

+ +
+
+ + + + + +
+ + + + +
uint8_t const msg_adata[16u]
+ 		+static
+
+ +

Additional authenticated data.

+ +
+
+ +

◆ msg_enc_expected

+ +
+
+ + + + + +
+ + + + +
uint8_t const msg_enc_expected[16u]
+ 		+static
+
+ +

Expected ciphertext output of the AES-GCM encryption.

+ +
+
+ +

◆ msg_tag_expected

+ +
+
+ + + + + +
+ + + + +
uint8_t const msg_tag_expected[16u]
+ 		+static
+
+ +

Expected authentication tag output.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00041.js b/components/els_pkc/doc/mcxn/html/a00041.js new file mode 100644 index 000000000..3090551d1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00041.js @@ -0,0 +1,10 @@ +var a00041 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00041.html#a92d351633686713a2dc9f051c5d63c12", null ], + [ "aes128_key", "a00041.html#afd0e33c5f8fc3670f63b637fb2febba4", null ], + [ "aes128_iv", "a00041.html#aef268ff45a3b41fd6678cfeaf409151e", null ], + [ "msg_plain", "a00041.html#ab5559a8546823f96b075fb6be010313e", null ], + [ "msg_adata", "a00041.html#a437ec5d6cef80672b16b267a9038fb3e", null ], + [ "msg_enc_expected", "a00041.html#a087137335e23969000b7aaee28cb398d", null ], + [ "msg_tag_expected", "a00041.html#abea9520607fe8679a77f6b7f902786af", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00074.html b/components/els_pkc/doc/mcxn/html/a00074.html new file mode 100644 index 000000000..9565c6faa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00074.html @@ -0,0 +1,182 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_Mont_Curve25519_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_Mont_Curve25519_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClRandomModes.h>
+#include <mcuxClRandom.h>
+#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+ + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_Mont_Curve25519_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_Mont_Curve25519_example )
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClEcc_Mont_Curve25519_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00074.js b/components/els_pkc/doc/mcxn/html/a00074.js new file mode 100644 index 000000000..be89c2234 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00074.js @@ -0,0 +1,7 @@ +var a00074 = +[ + [ "RAM_START_ADDRESS", "a00074.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00074.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00074.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00074.html#a75d0a2ced8164c38afbd0c95a1ff6686", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00077.html b/components/els_pkc/doc/mcxn/html/a00077.html new file mode 100644 index 000000000..15d2efc50 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00077.html @@ -0,0 +1,181 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_Mont_Curve448_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_Mont_Curve448_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClRandomModes.h>
+#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+ + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_Mont_Curve448_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_Mont_Curve448_example )
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClEcc_Mont_Curve448_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00077.js b/components/els_pkc/doc/mcxn/html/a00077.js new file mode 100644 index 000000000..806da621e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00077.js @@ -0,0 +1,7 @@ +var a00077 = +[ + [ "RAM_START_ADDRESS", "a00077.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00077.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00077.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00077.html#addf8fd48c03094abe17db5e808ed580c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00080.html b/components/els_pkc/doc/mcxn/html/a00080.html new file mode 100644 index 000000000..c0ebaee5e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00080.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions | +Variables
+
+
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClCore_Examples.h>
+#include <mcuxClSession.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClKey.h>
+#include <mcuxClEcc.h>
+#include <mcuxClEcc_WeierECC.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+
+ + + + + + + + + +

+Macros

+#define BN256_BYTE_LEN_P
 
+#define BN256_BYTE_LEN_N
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example)
 Performs an example key derivation using the mcuxClKey component. More...
 
+ + + + + + + + + + + +

+Variables

+static const uint8_t BN_P256_P [BN256_BYTE_LEN_P]
 
+static const uint8_t BN_P256_A [BN256_BYTE_LEN_P]
 
+static const uint8_t BN_P256_B [BN256_BYTE_LEN_P]
 
+static const uint8_t BN_P256_G [2u *BN256_BYTE_LEN_P]
 
+static const uint8_t BN_P256_N [BN256_BYTE_LEN_N]
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example )
+
+ +

Performs an example key derivation using the mcuxClKey component.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00080.js b/components/els_pkc/doc/mcxn/html/a00080.js new file mode 100644 index 000000000..89218fdd4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00080.js @@ -0,0 +1,13 @@ +var a00080 = +[ + [ "BN256_BYTE_LEN_P", "a00080.html#a7087f8ab68f1fe36f56211293f56d273", null ], + [ "BN256_BYTE_LEN_N", "a00080.html#acbc1657fa1c66004aa1e8d5eda1077c5", null ], + [ "MAX_CPUWA_SIZE", "a00080.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00080.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00080.html#a9e584bfb84b74adc18f23fb9774ff2e7", null ], + [ "BN_P256_P", "a00080.html#a9bdad68c86b0c0250f7cc749fc7fccf8", null ], + [ "BN_P256_A", "a00080.html#a29b851ce7ae361b1292e971e6c675138", null ], + [ "BN_P256_B", "a00080.html#a8040230a419f7be94d9ee6cbf4cf3f9f", null ], + [ "BN_P256_G", "a00080.html#a2f73dfd0364fa7290c6c4f6340b58d2f", null ], + [ "BN_P256_N", "a00080.html#a1f8bf4159aaaf487fc5f63c517e55c53", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00083.html b/components/els_pkc/doc/mcxn/html/a00083.html new file mode 100644 index 000000000..2fac24d18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00083.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ctx_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_EdDSA_Ed25519ctx_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClRandomModes.h>
+#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize)
 
+ + + + + +

+Functions

+static const uint8_t pMessage [] __attribute__ ((aligned(4)))
 
+ MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_EdDSA_Ed25519ctx_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00083.js b/components/els_pkc/doc/mcxn/html/a00083.js new file mode 100644 index 000000000..1b1abe161 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00083.js @@ -0,0 +1,9 @@ +var a00083 = +[ + [ "RAM_START_ADDRESS", "a00083.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00083.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00083.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "CPUALIGN_FROM_BYTES_TO_WORDSIZE", "a00083.html#a57c7a185581c58dff3e19bc745e8ed46", null ], + [ "__attribute__", "a00083.html#a9f458658069ce56366803ad5e06c35da", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00083.html#a1c4abe06d4daeb53d5ba1affb2a149c4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00086.html b/components/els_pkc/doc/mcxn/html/a00086.html new file mode 100644 index 000000000..00c04230d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00086.html @@ -0,0 +1,163 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ph_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_EdDSA_Ed25519ph_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClSession.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize)
 
+ + + + + +

+Functions

+static const uint8_t pMessage [] __attribute__ ((aligned(4)))
 
+ MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_EdDSA_Ed25519ph_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00086.js b/components/els_pkc/doc/mcxn/html/a00086.js new file mode 100644 index 000000000..60576e1d0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00086.js @@ -0,0 +1,9 @@ +var a00086 = +[ + [ "RAM_START_ADDRESS", "a00086.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00086.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00086.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "CPUALIGN_FROM_BYTES_TO_WORDSIZE", "a00086.html#a57c7a185581c58dff3e19bc745e8ed46", null ], + [ "__attribute__", "a00086.html#a9f458658069ce56366803ad5e06c35da", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00086.html#a1dcca9ead40bfbfe63355a2584ad4b83", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00089.html b/components/els_pkc/doc/mcxn/html/a00089.html new file mode 100644 index 000000000..9b4fd65e5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00089.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions | +Variables
+
+
mcuxClEcc_EdDSA_Ed25519_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + +

+Macros

+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + +

+Functions

+ MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_EdDSA_Ed25519_example)
 
+ + + +

+Variables

+static const uint8_t digest []
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00089.js b/components/els_pkc/doc/mcxn/html/a00089.js new file mode 100644 index 000000000..19a666631 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00089.js @@ -0,0 +1,7 @@ +var a00089 = +[ + [ "MAX_CPUWA_SIZE", "a00089.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00089.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00089.html#a62bdb5f26e6562bddf0d917057609404", null ], + [ "digest", "a00089.html#aff755c9c8469316315cb98b49477eef4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00092.html b/components/els_pkc/doc/mcxn/html/a00092.html new file mode 100644 index 000000000..1d5d499cc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00092.html @@ -0,0 +1,159 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + + + +

+Functions

+static const uint8_t pIn [] __attribute__ ((aligned(4)))
 
+ MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_EdDSA_VerifySignature_Ed25519_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00092.js b/components/els_pkc/doc/mcxn/html/a00092.js new file mode 100644 index 000000000..9d5d1d482 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00092.js @@ -0,0 +1,8 @@ +var a00092 = +[ + [ "RAM_START_ADDRESS", "a00092.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00092.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00092.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "__attribute__", "a00092.html#a76afd8e100a870ff884fb95bfc86e1a5", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00092.html#a87767682ee439267d095104e7bd1d75d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00095.html b/components/els_pkc/doc/mcxn/html/a00095.html new file mode 100644 index 000000000..1aeb93b8c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00095.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc/mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c File Reference
+
+
+ +

Example for the mcuxClEcc component. +More...

+
#include <mcuxClRandomModes.h>
+#include <mcuxClEcc.h>
+#include <mcuxClKey.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_RNG_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + +

+Macros

+#define RAM_START_ADDRESS
 
+#define MAX_CPUWA_SIZE
 
+#define MAX_PKCWA_SIZE
 
+ + + + + +

+Functions

+static const uint8_t pPrivKeyInput [MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__ ((aligned(4)))
 
+ MCUXCLEXAMPLE_FUNCTION (mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example)
 
+

Detailed Description

+

Example for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00095.js b/components/els_pkc/doc/mcxn/html/a00095.js new file mode 100644 index 000000000..c0c2b88d7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00095.js @@ -0,0 +1,8 @@ +var a00095 = +[ + [ "RAM_START_ADDRESS", "a00095.html#ae0248821388fe7ca46f47ce430d362f3", null ], + [ "MAX_CPUWA_SIZE", "a00095.html#ad43fc61273c08b0081fddb5f9f4cdd0b", null ], + [ "MAX_PKCWA_SIZE", "a00095.html#ac83e4873883f213b8ba03e33cfa954cd", null ], + [ "__attribute__", "a00095.html#ae9c827d8da99018b2d53224871c9bd3d", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00095.html#a46d540d0aa75e4590f9afa479ba7e00b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00116.html b/components/els_pkc/doc/mcxn/html/a00116.html new file mode 100644 index 000000000..84776cded --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00116.html @@ -0,0 +1,182 @@ + + + + + + + +MCUX CLNS: examples/mcuxClKey/mcuxClKey_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClKey_example.c File Reference
+
+
+ +

Example for the mcuxClKey component. +More...

+
#include <mcuxClKey.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Examples.h>
+#include <stdbool.h>
+#include <mcuxClAes.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_Key_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClKey_example)
 Performs an example initialization and cleanup of the mcuxClKey component. More...
 
+ + + +

+Variables

+static uint32_t aes128_key [MCUXCLAES_AES128_KEY_SIZE_IN_WORDS]
 
+

Detailed Description

+

Example for the mcuxClKey component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClKey_example )
+
+ +

Performs an example initialization and cleanup of the mcuxClKey component.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Destroy Session and cleanup Session

+
Examples
mcuxClKey_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00116.js b/components/els_pkc/doc/mcxn/html/a00116.js new file mode 100644 index 000000000..811864d98 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00116.js @@ -0,0 +1,5 @@ +var a00116 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00116.html#a4d4124fd2881a1d89bcb320735293fc7", null ], + [ "aes128_key", "a00116.html#a34b4612aa0a826c43b8167f23f225674", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00119.html b/components/els_pkc/doc/mcxn/html/a00119.html new file mode 100644 index 000000000..f27b83027 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00119.html @@ -0,0 +1,179 @@ + + + + + + + +MCUX CLNS: examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClMacModes_cmac_oneshot_example.c File Reference
+
+
+ +

Example CMAC computation using functions of the mcuxClKey and mcuxClMac component. +More...

+
#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClKey.h>
+#include <mcuxClAes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClMac.h>
+#include <mcuxClMacModes.h>
+#include <mcuxClExample_ELS_Helper.h>
+#include <mcuxClExample_Key_Helper.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClExample_RNG_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClMacModes_cmac_oneshot_example)
 Performs a CMAC computation using functions of the mcuxClKey component. More...
 
+

Detailed Description

+

Example CMAC computation using functions of the mcuxClKey and mcuxClMac component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClMacModes_cmac_oneshot_example )
+
+ +

Performs a CMAC computation using functions of the mcuxClKey component.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00119.js b/components/els_pkc/doc/mcxn/html/a00119.js new file mode 100644 index 000000000..63f0bf3d4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00119.js @@ -0,0 +1,4 @@ +var a00119 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00119.html#a71e50006ff7948794718e7aee5ca982a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00134.html b/components/els_pkc/doc/mcxn/html/a00134.html new file mode 100644 index 000000000..21be58d44 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00134.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_ELS_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with ELS mode. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_ELS_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with ELS mode.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00134.js b/components/els_pkc/doc/mcxn/html/a00134.js new file mode 100644 index 000000000..7305e6263 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00134.js @@ -0,0 +1,4 @@ +var a00134 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00134.html#a4fb93b93e2f83f913ca6d51af1f61e0a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00137.html b/components/els_pkc/doc/mcxn/html/a00137.html new file mode 100644 index 000000000..575bcbc52 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00137.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_ELS_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_ELS_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with ELS mode. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_ELS_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with ELS mode.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_ELS_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00137.js b/components/els_pkc/doc/mcxn/html/a00137.js new file mode 100644 index 000000000..98458744e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00137.js @@ -0,0 +1,4 @@ +var a00137 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00137.html#a91004e78f2323ae2750f3db18d7ed12f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00140.html b/components/els_pkc/doc/mcxn/html/a00140.html new file mode 100644 index 000000000..0e2991e3e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00140.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_DRG3_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_DRG3_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00140.js b/components/els_pkc/doc/mcxn/html/a00140.js new file mode 100644 index 000000000..3a8d72788 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00140.js @@ -0,0 +1,4 @@ +var a00140 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00140.html#a824a93e2c644f62de4ab1c413f3cdeaa", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00143.html b/components/els_pkc/doc/mcxn/html/a00143.html new file mode 100644 index 000000000..d1a5335b2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00143.html @@ -0,0 +1,178 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_Different_Sessions_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_Different_Sessions_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_Different_Sessions_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_Different_Sessions_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy session_0 and cleanup session_0

+

Destroy session_1 and cleanup session_1

+

Disable the ELS

+
Examples
mcuxClRandomModes_Different_Sessions_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00143.js b/components/els_pkc/doc/mcxn/html/a00143.js new file mode 100644 index 000000000..87b53165b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00143.js @@ -0,0 +1,4 @@ +var a00143 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00143.html#a9b0834b958b1450723fab20a00fcefe1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00146.html b/components/els_pkc/doc/mcxn/html/a00146.html new file mode 100644 index 000000000..d31aad0b2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00146.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_DRG4_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_CtrDrbg_AES256_DRG4_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00146.js b/components/els_pkc/doc/mcxn/html/a00146.js new file mode 100644 index 000000000..d33914cd3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00146.js @@ -0,0 +1,4 @@ +var a00146 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00146.html#a8cbc037b8fa449be72bf01c6b63ca7a7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00149.html b/components/els_pkc/doc/mcxn/html/a00149.html new file mode 100644 index 000000000..14c37989d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00149.html @@ -0,0 +1,230 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + +

+Functions

static mcuxClRandom_Status_t RNG_Patch_function (mcuxClSession_Handle_t session, mcuxClRandom_Context_t pCustomCtx, uint8_t *pOut, uint32_t outLength)
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with patch mode. More...
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ RNG_Patch_function()

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
static mcuxClRandom_Status_t RNG_Patch_function (mcuxClSession_Handle_t session,
mcuxClRandom_Context_t pCustomCtx,
uint8_t * pOut,
uint32_t outLength 
)
+ 		+static
+
+

Destroy Session and cleanup Session

+
Examples
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with patch mode.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00149.js b/components/els_pkc/doc/mcxn/html/a00149.js new file mode 100644 index 000000000..1a035ddd5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00149.js @@ -0,0 +1,5 @@ +var a00149 = +[ + [ "RNG_Patch_function", "a00149.html#af28f6bb34479e4b2fe6b40fa868ee71b", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00149.html#a7cbd851346a84954cad6892fe66c1d90", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00152.html b/components/els_pkc/doc/mcxn/html/a00152.html new file mode 100644 index 000000000..2ed60ed0c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00152.html @@ -0,0 +1,200 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions | +Variables
+
+
mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + +

+Macros

+#define OUT_BUFFER_SIZE
 
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with test mode. More...
 
+ + + + + + + + + +

+Variables

+static const uint32_t entropyInputInit [MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE, sizeof(uint32_t))]
 
+static const uint32_t entropyInputReseed [MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE, sizeof(uint32_t))]
 
+static const uint32_t entropyInputGenerate [MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE *2u, sizeof(uint32_t))]
 
+static const uint32_t refOutput [OUT_BUFFER_SIZE/sizeof(uint32_t)]
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with test mode.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00152.js b/components/els_pkc/doc/mcxn/html/a00152.js new file mode 100644 index 000000000..5b6ea6cd8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00152.js @@ -0,0 +1,9 @@ +var a00152 = +[ + [ "OUT_BUFFER_SIZE", "a00152.html#a02ef0a0a6d0c0187af0f7ffedb713f1d", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00152.html#a99ac8d5cb62fa1f7978221415653da14", null ], + [ "entropyInputInit", "a00152.html#aa1ba37a2bf1a1e92860cef4446515ae9", null ], + [ "entropyInputReseed", "a00152.html#a9184e03824f9aa085e06848ac2c09cc7", null ], + [ "entropyInputGenerate", "a00152.html#a9642cac087753e42c26b773207af3166", null ], + [ "refOutput", "a00152.html#ac1935ef11aa2e22e2d63eed1b5fb9000", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00155.html b/components/els_pkc/doc/mcxn/html/a00155.html new file mode 100644 index 000000000..a0dff2b0c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00155.html @@ -0,0 +1,190 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes/mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions | +Variables
+
+
mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c File Reference
+
+
+ +

Example for the mcuxClRandomModes component. +More...

+
#include <mcuxClRandom.h>
+#include <mcuxClRandomModes.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + +

+Functions

 MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example)
 Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with test mode. More...
 
+ + + + + + + +

+Variables

+static const uint32_t entropyInputInit [MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE, sizeof(uint32_t))]
 
+static const uint32_t entropyInputReseed [MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE, sizeof(uint32_t))]
 
+static const uint32_t refOutput [64u]
 
+

Detailed Description

+

Example for the mcuxClRandomModes component.

+

Function Documentation

+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example )
+
+ +

Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with test mode.

+
Return values
+ + + +
trueThe example code completed successfully
falseThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00155.js b/components/els_pkc/doc/mcxn/html/a00155.js new file mode 100644 index 000000000..bbb5deb42 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00155.js @@ -0,0 +1,7 @@ +var a00155 = +[ + [ "MCUXCLEXAMPLE_FUNCTION", "a00155.html#a986952eb07f2ec086c4f6ff46bbbc9a0", null ], + [ "entropyInputInit", "a00155.html#aa1ba37a2bf1a1e92860cef4446515ae9", null ], + [ "entropyInputReseed", "a00155.html#a9184e03824f9aa085e06848ac2c09cc7", null ], + [ "refOutput", "a00155.html#a0047b8f1e1384162c3481c14e81e3372", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00158.html b/components/els_pkc/doc/mcxn/html/a00158.html new file mode 100644 index 000000000..b5aed69de --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00158.html @@ -0,0 +1,322 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRsa/mcuxClRsa_verify_pssverify_sha2_256_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClRsa_verify_pssverify_sha2_256_example.c File Reference
+
+
+ +

Example of using function mcuxClRsa_verify to perform the RSA signature verification with EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2. +More...

+
#include <mcuxClSession.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClRandom.h>
+#include <mcuxClRsa.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + + + + + + + + + + +

+Macros

#define RSA_KEY_BIT_LENGTH
 The example uses a 2048-bit key. More...
 
#define RSA_KEY_BYTE_LENGTH
 Converting the key-bitlength to bytelength. More...
 
#define RSA_PUBLIC_EXP_BYTE_LENGTH
 The public exponent has a length of three bytes. More...
 
#define RSA_MESSAGE_DIGEST_LENGTH
 The example uses a Sha2-256 digest, which is 32 bytes long. More...
 
#define RSA_PSS_SALT_LENGTH
 The salt for the PSS padding is 32 bytes long. More...
 
+ + + + + + + +

+Functions

static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)))
 Example value for public RSA modulus N. More...
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_verify_pssverify_sha2_256_example)
 Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_Pss_Sha2_256; a session clean-up. More...
 
+

Detailed Description

+

Example of using function mcuxClRsa_verify to perform the RSA signature verification with EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2.

+

Macro Definition Documentation

+ +

◆ RSA_KEY_BIT_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BIT_LENGTH
+
+ +

The example uses a 2048-bit key.

+ +
+
+ +

◆ RSA_KEY_BYTE_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BYTE_LENGTH
+
+ +

Converting the key-bitlength to bytelength.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ RSA_PUBLIC_EXP_BYTE_LENGTH

+ +
+
+ + + + +
#define RSA_PUBLIC_EXP_BYTE_LENGTH
+
+ +

The public exponent has a length of three bytes.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ RSA_MESSAGE_DIGEST_LENGTH

+ +
+
+ + + + +
#define RSA_MESSAGE_DIGEST_LENGTH
+
+ +

The example uses a Sha2-256 digest, which is 32 bytes long.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ RSA_PSS_SALT_LENGTH

+ +
+
+ + + + +
#define RSA_PSS_SALT_LENGTH
+
+ +

The salt for the PSS padding is 32 bytes long.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + +
+ + + + + + + + +
static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)) )
+ 		+static
+
+ +

Example value for public RSA modulus N.

+

Example value for RSA signature s.

+

Example value for Sha2-256 message digest.

+

Example value for public RSA exponent e.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_verify_pssverify_sha2_256_example )
+
+ +

Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_Pss_Sha2_256; a session clean-up.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00158.js b/components/els_pkc/doc/mcxn/html/a00158.js new file mode 100644 index 000000000..12fd1f4f9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00158.js @@ -0,0 +1,10 @@ +var a00158 = +[ + [ "RSA_KEY_BIT_LENGTH", "a00158.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe", null ], + [ "RSA_KEY_BYTE_LENGTH", "a00158.html#a682e80cec7574ae978654511689ad090", null ], + [ "RSA_PUBLIC_EXP_BYTE_LENGTH", "a00158.html#a1318d0d378cd86d23dcf30d273a195a9", null ], + [ "RSA_MESSAGE_DIGEST_LENGTH", "a00158.html#a5621c168ff2d53aa21bf267fa5f5d88c", null ], + [ "RSA_PSS_SALT_LENGTH", "a00158.html#aa130e86f5b203dd9bcd2b0daf72cc2d5", null ], + [ "__attribute__", "a00158.html#ac653ec70e8637a68edb49fd66e7e3edc", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00158.html#a7299c7736f173efca4ade8d274e7d75b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00161.html b/components/els_pkc/doc/mcxn/html/a00161.html new file mode 100644 index 000000000..3faed908d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00161.html @@ -0,0 +1,300 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClRsa_sign_pss_sha2_256_example.c File Reference
+
+
+ +

Example of using function mcuxClRsa_sign to perform the RSA signature generation with EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2. +More...

+
#include <mcuxClSession.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClRandom.h>
+#include <mcuxClRsa.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + + + + + + + +

+Macros

#define RSA_KEY_BIT_LENGTH
 The example uses a 2048-bit key. More...
 
#define RSA_KEY_BYTE_LENGTH
 Converting the key-bitlength to bytelength. More...
 
#define RSA_MESSAGE_DIGEST_LENGTH
 The example uses a Sha2-256 digest, which is 32 bytes long. More...
 
#define RSA_PSS_SALT_LENGTH
 The salt length is set to 0 in this example. More...
 
+ + + + + + + +

+Functions

static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)))
 Example value for public RSA modulus N. More...
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_sign_pss_sha2_256_example)
 Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Sign_Pss_Sha2_256; a session clean-up. More...
 
+

Detailed Description

+

Example of using function mcuxClRsa_sign to perform the RSA signature generation with EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2.

+

Macro Definition Documentation

+ +

◆ RSA_KEY_BIT_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BIT_LENGTH
+
+ +

The example uses a 2048-bit key.

+ +
+
+ +

◆ RSA_KEY_BYTE_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BYTE_LENGTH
+
+ +

Converting the key-bitlength to bytelength.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ RSA_MESSAGE_DIGEST_LENGTH

+ +
+
+ + + + +
#define RSA_MESSAGE_DIGEST_LENGTH
+
+ +

The example uses a Sha2-256 digest, which is 32 bytes long.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ RSA_PSS_SALT_LENGTH

+ +
+
+ + + + +
#define RSA_PSS_SALT_LENGTH
+
+ +

The salt length is set to 0 in this example.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + +
+ + + + + + + + +
static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)) )
+ 		+static
+
+ +

Example value for public RSA modulus N.

+

Expected signature.

+

Example value for Sha2-256 message digest.

+

Example value for private RSA exponent d.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_sign_pss_sha2_256_example )
+
+ +

Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Sign_Pss_Sha2_256; a session clean-up.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00161.js b/components/els_pkc/doc/mcxn/html/a00161.js new file mode 100644 index 000000000..3947cc918 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00161.js @@ -0,0 +1,9 @@ +var a00161 = +[ + [ "RSA_KEY_BIT_LENGTH", "a00161.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe", null ], + [ "RSA_KEY_BYTE_LENGTH", "a00161.html#a682e80cec7574ae978654511689ad090", null ], + [ "RSA_MESSAGE_DIGEST_LENGTH", "a00161.html#a5621c168ff2d53aa21bf267fa5f5d88c", null ], + [ "RSA_PSS_SALT_LENGTH", "a00161.html#aa130e86f5b203dd9bcd2b0daf72cc2d5", null ], + [ "__attribute__", "a00161.html#ac653ec70e8637a68edb49fd66e7e3edc", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00161.html#a20789e8a17209cfcf845dd22d8a02462", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00164.html b/components/els_pkc/doc/mcxn/html/a00164.html new file mode 100644 index 000000000..7ef389fe2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00164.html @@ -0,0 +1,259 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClRsa_verify_NoVerify_example.c File Reference
+
+
+ +

Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 (public exponentiation and NO padding verification) according to PKCS #1 v2.2. +More...

+
#include <mcuxClSession.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClRandom.h>
+#include <mcuxClRsa.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + +

+Macros

#define RSA_KEY_BIT_LENGTH
 The example uses a 2048-bit key. More...
 
#define RSA_KEY_BYTE_LENGTH
 Converting the key-bitlength to bytelength. More...
 
+ + + + + + + +

+Functions

static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)))
 Example value for public RSA modulus N. More...
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_verify_NoVerify_example)
 Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up. More...
 
+

Detailed Description

+

Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 (public exponentiation and NO padding verification) according to PKCS #1 v2.2.

+

Macro Definition Documentation

+ +

◆ RSA_KEY_BIT_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BIT_LENGTH
+
+ +

The example uses a 2048-bit key.

+ +
+
+ +

◆ RSA_KEY_BYTE_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BYTE_LENGTH
+
+ +

Converting the key-bitlength to bytelength.

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + +
+ + + + + + + + +
static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)) )
+ 		+static
+
+ +

Example value for public RSA modulus N.

+

Reference output when calling mcuxClRsa_verify on signature s using the RSA public key pair (N,e) and choosing mode mcuxClRsa_Mode_Verify_NoVerify.

+

Example value for RSA signature s.

+

Example value for public RSA exponent e.

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_verify_NoVerify_example )
+
+ +

Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00164.js b/components/els_pkc/doc/mcxn/html/a00164.js new file mode 100644 index 000000000..212f50f43 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00164.js @@ -0,0 +1,7 @@ +var a00164 = +[ + [ "RSA_KEY_BIT_LENGTH", "a00164.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe", null ], + [ "RSA_KEY_BYTE_LENGTH", "a00164.html#a682e80cec7574ae978654511689ad090", null ], + [ "__attribute__", "a00164.html#ac653ec70e8637a68edb49fd66e7e3edc", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00164.html#ab0f06c91945e4c60608e1508e1a40fdf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00167.html b/components/els_pkc/doc/mcxn/html/a00167.html new file mode 100644 index 000000000..7b5bbf4d6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00167.html @@ -0,0 +1,259 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClRsa_sign_NoEncode_example.c File Reference
+
+
+ +

Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format. +More...

+
#include <mcuxClSession.h>
+#include <mcuxClExample_Session_Helper.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClRandom.h>
+#include <mcuxClRsa.h>
+#include <mcuxClToolchain.h>
+#include <mcuxClCore_Examples.h>
+#include <mcuxClEls.h>
+#include <mcuxClExample_ELS_Helper.h>
+
+ + + + + + + +

+Macros

#define RSA_KEY_BIT_LENGTH
 The example uses a 1024-bit key. More...
 
#define RSA_KEY_BYTE_LENGTH
 Converting the key-bitlength to bytelength. More...
 
+ + + + + + + +

+Functions

static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)))
 Example value for public RSA modulus N. More...
 
 MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_sign_NoEncode_example)
 Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up. More...
 
+

Detailed Description

+

Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format.

+

Macro Definition Documentation

+ +

◆ RSA_KEY_BIT_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BIT_LENGTH
+
+ +

The example uses a 1024-bit key.

+ +
+
+ +

◆ RSA_KEY_BYTE_LENGTH

+ +
+
+ + + + +
#define RSA_KEY_BYTE_LENGTH
+
+ +

Converting the key-bitlength to bytelength.

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
+
+ +
+
+

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + +
+ + + + + + + + +
static const uint8_t modulus [RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned(4)) )
+ 		+static
+
+ +

Example value for public RSA modulus N.

+

Expected signature.

+

Input message.

+

Example value for private RSA exponent d.

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
+
+ +
+
+ +

◆ MCUXCLEXAMPLE_FUNCTION()

+ +
+
+ + + + + + + + +
MCUXCLEXAMPLE_FUNCTION (mcuxClRsa_sign_NoEncode_example )
+
+ +

Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up.

+
Return values
+ + + +
MCUXCLEXAMPLE_STATUS_OKThe example code completed successfully
MCUXCLEXAMPLE_STATUS_ERRORThe example code failed
+
+
+

Initialize ELS, Enable the ELS

+

Destroy Session and cleanup Session

+

Disable the ELS

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00167.js b/components/els_pkc/doc/mcxn/html/a00167.js new file mode 100644 index 000000000..e99cc398c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00167.js @@ -0,0 +1,7 @@ +var a00167 = +[ + [ "RSA_KEY_BIT_LENGTH", "a00167.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe", null ], + [ "RSA_KEY_BYTE_LENGTH", "a00167.html#a682e80cec7574ae978654511689ad090", null ], + [ "__attribute__", "a00167.html#ac653ec70e8637a68edb49fd66e7e3edc", null ], + [ "MCUXCLEXAMPLE_FUNCTION", "a00167.html#a80d285764029b6fa279a51015d492960", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00173.html b/components/els_pkc/doc/mcxn/html/a00173.html new file mode 100644 index 000000000..a16191f87 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00173.html @@ -0,0 +1,185 @@ + + + + + + + +MCUX CLNS: examples/mcuxCsslMemory/data_invariant_memory_compare.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
data_invariant_memory_compare.c File Reference
+
+
+ +

Example constant-time memory compare (CSSL component mcuxCsslMemory) +More...

+
#include <stdbool.h>
+#include <stdint.h>
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslMemory_Examples.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+ + + + + + + +

+Macros

#define EXIT_CODE_ERROR
 example return code in case an error occurred More...
 
#define EXIT_CODE_OK
 example return code in case of successful operation More...
 
+ + + +

+Functions

+bool data_invariant_memory_compare (void)
 
+

Detailed Description

+

Example constant-time memory compare (CSSL component mcuxCsslMemory)

+

Macro Definition Documentation

+ +

◆ EXIT_CODE_ERROR

+ +
+
+ + + + +
#define EXIT_CODE_ERROR
+
+ +

example return code in case an error occurred

+ +
+
+ +

◆ EXIT_CODE_OK

+ +
+
+ + + + +
#define EXIT_CODE_OK
+
+ +

example return code in case of successful operation

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00173.js b/components/els_pkc/doc/mcxn/html/a00173.js new file mode 100644 index 000000000..5e00d7a01 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00173.js @@ -0,0 +1,6 @@ +var a00173 = +[ + [ "EXIT_CODE_ERROR", "a00173.html#a1feeb5aa091fe94feea015623eeb53b7", null ], + [ "EXIT_CODE_OK", "a00173.html#ae6032b4b9390cdf8886f3b02ab488383", null ], + [ "data_invariant_memory_compare", "a00173.html#a78e1836b2a203ba366d6930eca203e60", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00176.html b/components/els_pkc/doc/mcxn/html/a00176.html new file mode 100644 index 000000000..ceb0b99d2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00176.html @@ -0,0 +1,185 @@ + + + + + + + +MCUX CLNS: examples/mcuxCsslMemory/data_invariant_memory_copy.c File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
data_invariant_memory_copy.c File Reference
+
+
+ +

Example constant-time memory copy (CSSL component mcuxCsslMemory) +More...

+
#include <stdbool.h>
+#include <stdint.h>
+#include <mcuxCsslMemory.h>
+#include <mcuxCsslMemory_Examples.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+ + + + + + + +

+Macros

#define EXIT_CODE_ERROR
 example return code in case an error occurred More...
 
#define EXIT_CODE_OK
 example return code in case of successful operation More...
 
+ + + +

+Functions

+bool data_invariant_memory_copy (void)
 
+

Detailed Description

+

Example constant-time memory copy (CSSL component mcuxCsslMemory)

+

Macro Definition Documentation

+ +

◆ EXIT_CODE_ERROR

+ +
+
+ + + + +
#define EXIT_CODE_ERROR
+
+ +

example return code in case an error occurred

+ +
+
+ +

◆ EXIT_CODE_OK

+ +
+
+ + + + +
#define EXIT_CODE_OK
+
+ +

example return code in case of successful operation

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00176.js b/components/els_pkc/doc/mcxn/html/a00176.js new file mode 100644 index 000000000..f526227a6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00176.js @@ -0,0 +1,6 @@ +var a00176 = +[ + [ "EXIT_CODE_ERROR", "a00176.html#a1feeb5aa091fe94feea015623eeb53b7", null ], + [ "EXIT_CODE_OK", "a00176.html#ae6032b4b9390cdf8886f3b02ab488383", null ], + [ "data_invariant_memory_copy", "a00176.html#a814e4c2decdd93ed6c81273b350c66b3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00191_source.html b/components/els_pkc/doc/mcxn/html/a00191_source.html new file mode 100644 index 000000000..026594a20 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00191_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: examples/mcuxCsslFlowProtection/inc/mcuxCsslExamples.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslExamples.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUX_CSSL_EXAMPLES_H_
15 #define MCUX_CSSL_EXAMPLES_H_
16 
17 #include <stdint.h>
18 #include <stdbool.h>
19 #include <stddef.h>
20 
21 #define MCUX_CSSL_EX_FUNCTION(_name) bool _name(void)
22 
23 #define MCUX_CSSL_EX_OK true
24 #define MCUX_CSSL_EX_ERROR false
25 
26 static inline bool mcuxCsslExamples_assertEqual(const uint8_t * const x, const uint8_t * const y, uint32_t length)
27 {
28  for (uint32_t i = 0; i < length; ++i)
29  {
30  if (x[i] != y[i])
31  {
32  return false;
33  }
34  }
35 
36  return true;
37 }
38 
39 MCUX_CSSL_EX_FUNCTION(mcuxCsslFlowProtection_example);
40 
41 #endif /* MCUX_CSSL_EXAMPLES_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00194_source.html b/components/els_pkc/doc/mcxn/html/a00194_source.html new file mode 100644 index 000000000..c3b23156e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00194_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: examples/mcuxCsslMemory/inc/mcuxCsslMemory_Examples.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslMemory_Examples.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCSSLMEMORY_EXAMPLES_H_
15 #define MCUXCSSLMEMORY_EXAMPLES_H_
16 
17 #include <stdint.h>
18 #include <stdbool.h>
19 #include <stddef.h>
20 
21 #define MCUXCSSL_MEMORY_EX_FUNCTION(_name) bool _name(void)
22 
23 #define MCUXCSSLMEMORY_EX_OK true
24 #define MCUXCSSLMEMORY_EX_ERROR false
25 
26 bool data_invariant_memory_compare(void);
27 bool data_invariant_memory_copy(void);
28 MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Clear_example);
29 MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Set_example);
30 
31 #endif /* MCUXCSSLMEMORY_EXAMPLES_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00200.html b/components/els_pkc/doc/mcxn/html/a00200.html new file mode 100644 index 000000000..2f582c9aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00200.html @@ -0,0 +1,225 @@ + + + + + + + +MCUX CLNS: mcuxCl_clns.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxCl_clns.h File Reference
+
+
+ +

CLNS header for component-independent functionality. +More...

+
#include <mcuxClConfig.h>
+#include <impl/mcuxCl_clns_impl.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Macros

#define MCUXCL_API
 Marks a function as a public API function of the CLNS. More...
 
#define MCUXCL_VERSION_MAX_SIZE
 Maximum size of the CLNS version string, in bytes (including zero-terminator) More...
 
#define MCUXCL_VERSION
 String literal for the version string of CLNS release that this header is part of. More...
 
+ + + + +

+Functions

MCUXCL_API char const * mcuxCl_GetVersion (void)
 Gets the CLNS version string that uniquely identifies this release of the CLNS. More...
 
+

Detailed Description

+

CLNS header for component-independent functionality.

+

Macro Definition Documentation

+ +

◆ MCUXCL_API

+ +
+
+ + + + +
#define MCUXCL_API
+
+ +

Marks a function as a public API function of the CLNS.

+ +
+
+ +

◆ MCUXCL_VERSION_MAX_SIZE

+ +
+
+ + + + +
#define MCUXCL_VERSION_MAX_SIZE
+
+ +

Maximum size of the CLNS version string, in bytes (including zero-terminator)

+ +
+
+ +

◆ MCUXCL_VERSION

+ +
+
+ + + + +
#define MCUXCL_VERSION
+
+ +

String literal for the version string of CLNS release that this header is part of.

+ +
+
+

Function Documentation

+ +

◆ mcuxCl_GetVersion()

+ +
+
+ + + + + + + + +
MCUXCL_API char const* mcuxCl_GetVersion (void )
+
+ +

Gets the CLNS version string that uniquely identifies this release of the CLNS.

+
Returns
Zero-terminated ASCII string that identifies this release of the CLNS. Maximum size in bytes (including zero-terminator) is MCUXCL_VERSION_MAX_SIZE.
+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00200.js b/components/els_pkc/doc/mcxn/html/a00200.js new file mode 100644 index 000000000..be3bbdd64 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00200.js @@ -0,0 +1,7 @@ +var a00200 = +[ + [ "MCUXCL_API", "a00200.html#a3a2aa1bfb4cd2f30cd208b1f53fd3238", null ], + [ "MCUXCL_VERSION_MAX_SIZE", "a00200.html#aac49d4488517875c56358012b911da08", null ], + [ "MCUXCL_VERSION", "a00200.html#aaac021cf1e464db8ec89a2313860577b", null ], + [ "mcuxCl_GetVersion", "a00200.html#a41e47552892b4e05c396de4ab626aaa2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00200_source.html b/components/els_pkc/doc/mcxn/html/a00200_source.html new file mode 100644 index 000000000..dc5dc1571 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00200_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxCl_clns.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCl_clns.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCL_CLNS_H_
18 #define MCUXCL_CLNS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 
25 #define MCUXCL_API static inline
26 
27 /**********************************************
28  * CONSTANTS
29  **********************************************/
30 
31 #define MCUXCL_VERSION_MAX_SIZE ((size_t) 16U)
32 
33 #define MCUXCL_VERSION "SDK_1.7.0"
34 
35 /**********************************************
36  * FUNCTIONS
37  **********************************************/
38 
43 MCUXCL_API char const* mcuxCl_GetVersion(
44  void);
45 
46 #include <impl/mcuxCl_clns_impl.h> // Implementation header
47 #endif /* MCUXCL_CLNS_H_ */
MCUXCL_API
#define MCUXCL_API
Marks a function as a public API function of the CLNS.
Definition: mcuxCl_clns.h:25
+
mcuxCl_GetVersion
MCUXCL_API char const * mcuxCl_GetVersion(void)
Gets the CLNS version string that uniquely identifies this release of the CLNS.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00203.html b/components/els_pkc/doc/mcxn/html/a00203.html new file mode 100644 index 000000000..f1489848a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00203.html @@ -0,0 +1,133 @@ + + + + + + + +MCUX CLNS: mcuxClAead.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAead.h File Reference
+
+
+ +

Top-level include file for the mcuxClAead component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClAead_Types.h>
+#include <mcuxClAead_Functions.h>
+#include <mcuxClAead_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClAead component.

+

This includes headers for all of the functionality provided by the mcuxClAead component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00203_source.html b/components/els_pkc/doc/mcxn/html/a00203_source.html new file mode 100644 index 000000000..29a3276a9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00203_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClAead.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAead.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
46 #ifndef MCUXCLAEAD_H_
47 #define MCUXCLAEAD_H_
48 
49 #include <mcuxClConfig.h> // Exported features flags header
50 
51 #include <mcuxClAead_Types.h>
52 #include <mcuxClAead_Functions.h>
53 #include <mcuxClAead_Constants.h>
54 
55 
56 #endif /* MCUXCLAEAD_H_ */
mcuxClAead_Constants.h
Constants for use with the mcuxClAead component.
+
mcuxClAead_Functions.h
Top-level API of the mcuxClAead component.
+
mcuxClAead_Types.h
Type definitions for the mcuxClAead component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00206.html b/components/els_pkc/doc/mcxn/html/a00206.html new file mode 100644 index 000000000..39e24cc07 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00206.html @@ -0,0 +1,147 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClAead_Constants.h File Reference
+
+
+ +

Constants for use with the mcuxClAead component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + +

+Macros

+#define MCUXCLAEAD_STATUS_ERROR
 
+#define MCUXCLAEAD_STATUS_FAULT_ATTACK
 
+#define MCUXCLAEAD_STATUS_OK
 
+#define MCUXCLAEAD_STATUS_NOT_OK
 
+

Detailed Description

+

Constants for use with the mcuxClAead component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00206.js b/components/els_pkc/doc/mcxn/html/a00206.js new file mode 100644 index 000000000..f658955ce --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00206.js @@ -0,0 +1,7 @@ +var a00206 = +[ + [ "MCUXCLAEAD_STATUS_ERROR", "a00663.html#ga66d71fdbfe9e95ddd5af2f23466ba44a", null ], + [ "MCUXCLAEAD_STATUS_FAULT_ATTACK", "a00663.html#ga85ef5d5dd9baa2ab5001159f6c392d13", null ], + [ "MCUXCLAEAD_STATUS_OK", "a00663.html#ga6c761e767eb59aef9aa93a6e05661aa5", null ], + [ "MCUXCLAEAD_STATUS_NOT_OK", "a00663.html#ga4d19e62c6e89d496019c680ff7abf299", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00206_source.html b/components/els_pkc/doc/mcxn/html/a00206_source.html new file mode 100644 index 000000000..687c3314d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00206_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAead_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLAEAD_CONSTANTS_H_
18 #define MCUXCLAEAD_CONSTANTS_H_
19 
34 #include <mcuxClConfig.h> // Exported features flags header
35 
36 /* Error codes */
37 /* TODO CLNS-8684: Unionize and describe return codes */
38 #define MCUXCLAEAD_STATUS_ERROR ((mcuxClAead_Status_t) 0x01115330u)
39 #define MCUXCLAEAD_STATUS_FAULT_ATTACK ((mcuxClAead_Status_t) 0x0111F0F0u)
40 #define MCUXCLAEAD_STATUS_OK ((mcuxClAead_Status_t) 0x01112E03u)
41 #define MCUXCLAEAD_STATUS_NOT_OK ((mcuxClAead_Status_t) 0x011153FCu)
42 
47 #endif /* MCUXCLAEAD_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00209.html b/components/els_pkc/doc/mcxn/html/a00209.html new file mode 100644 index 000000000..4e4c2146f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00209.html @@ -0,0 +1,157 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
+ +
+
+Functions
+
+
mcuxClAead_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClAead component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClKey.h>
+#include <mcuxClAead_Types.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClAead_Status_t mcuxClAead_crypt (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag, uint32_t tagLength)
 One-shot authenticated encryption/decryption function. More...
 
mcuxClAead_Status_t mcuxClAead_init (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, uint32_t inLength, uint32_t adataLength, uint32_t tagLength)
 Multi-part authenticated encryption/decryption initialization function. More...
 
mcuxClAead_Status_t mcuxClAead_process (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part authenticated encryption/decryption processing function for the regular data (authenticated and encrypted) More...
 
mcuxClAead_Status_t mcuxClAead_process_adata (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength)
 Multi-part authenticated encryption/decryption processing function for the associated data (authenticated only) More...
 
mcuxClAead_Status_t mcuxClAead_finish (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag)
 Multi-part authenticated encryption/decryption finalization function. More...
 
mcuxClAead_Status_t mcuxClAead_verify (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pTag, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part authenticated decryption verification function. More...
 
+

Detailed Description

+

Top-level API of the mcuxClAead component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00209.js b/components/els_pkc/doc/mcxn/html/a00209.js new file mode 100644 index 000000000..1ef1dc121 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00209.js @@ -0,0 +1,9 @@ +var a00209 = +[ + [ "mcuxClAead_crypt", "a00664.html#gad0713168358588f9550468bf1ef7cfbb", null ], + [ "mcuxClAead_init", "a00665.html#gaeb2451aba7d135f7af05e94f9b095fae", null ], + [ "mcuxClAead_process", "a00665.html#gaa4af5201aaf549186bf80cbf4284f3d1", null ], + [ "mcuxClAead_process_adata", "a00665.html#ga40cbd731ba8874d971213fa03605736d", null ], + [ "mcuxClAead_finish", "a00665.html#ga2b18aa6585e4d229d7ccfdd34f3f9dba", null ], + [ "mcuxClAead_verify", "a00665.html#gafb82bc41120d69281d0fbb719fb35d9d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00209_source.html b/components/els_pkc/doc/mcxn/html/a00209_source.html new file mode 100644 index 000000000..0bb1edb7f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00209_source.html @@ -0,0 +1,139 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Functions.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
mcuxClAead_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLAEAD_FUNCTIONS_H_
18 #define MCUXCLAEAD_FUNCTIONS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 #include <mcuxClSession_Types.h>
22 #include <mcuxClKey.h>
23 #include <mcuxClAead_Types.h>
24 #include <mcuxClCore_Buffer.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
78 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_crypt)
79 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_crypt(
80  mcuxClSession_Handle_t session,
81  mcuxClKey_Handle_t key,
82  mcuxClAead_Mode_t mode,
83  mcuxCl_InputBuffer_t pNonce,
84  uint32_t nonceLength,
85  mcuxCl_InputBuffer_t pIn,
86  uint32_t inLength,
87  mcuxCl_InputBuffer_t pAdata,
88  uint32_t adataLength,
89  mcuxCl_Buffer_t pOut,
90  uint32_t * const pOutLength,
91  mcuxCl_Buffer_t pTag,
92  uint32_t tagLength
93 );
94 
124 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_init)
125 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_init(
126  mcuxClSession_Handle_t session,
127  mcuxClAead_Context_t * const pContext,
128  mcuxClKey_Handle_t key,
129  mcuxClAead_Mode_t mode,
130  mcuxCl_InputBuffer_t pNonce,
131  uint32_t nonceLength,
132  uint32_t inLength,
133  uint32_t adataLength,
134  uint32_t tagLength
135 ); /* init encrypt */
136 
159 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_process)
160 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process(
161  mcuxClSession_Handle_t session,
162  mcuxClAead_Context_t * const pContext,
163  mcuxCl_InputBuffer_t pIn,
164  uint32_t inLength,
165  mcuxCl_Buffer_t pOut,
166  uint32_t * const pOutLength
167 ); /* update */
168 
186 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_process_adata)
187 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process_adata(
188  mcuxClSession_Handle_t session,
189  mcuxClAead_Context_t * const pContext,
190  mcuxCl_InputBuffer_t pAdata,
191  uint32_t adataLength
192 ); /* update associated data */
193 
216 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_finish)
217 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_finish(
218  mcuxClSession_Handle_t session,
219  mcuxClAead_Context_t * const pContext,
220  mcuxCl_Buffer_t pOut,
221  uint32_t * const pOutLength,
222  mcuxCl_Buffer_t pTag
223 ); /* finalize encrypt/decrypt + output tag */
224 
249 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_verify)
250 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_verify(
251  mcuxClSession_Handle_t session,
252  mcuxClAead_Context_t * const pContext,
253  mcuxCl_InputBuffer_t pTag,
254  mcuxCl_Buffer_t pOut,
255  uint32_t * const pOutLength
256 ); /* finalize decrypt + compare tag */
257 
260 #ifdef __cplusplus
261 } /* extern "C" */
262 #endif
263 
264 #endif /* MCUXCLAEAD_FUNCTION_H_ */
mcuxClAead_finish
mcuxClAead_Status_t mcuxClAead_finish(mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag)
Multi-part authenticated encryption/decryption finalization function.
+
mcuxClAead_Status_t
uint32_t mcuxClAead_Status_t
AEAD status code.
Definition: mcuxClAead_Types.h:110
+
mcuxClAead_Context_t
struct mcuxClAead_Context mcuxClAead_Context_t
AEAD context type.
Definition: mcuxClAead_Types.h:102
+
mcuxClKey.h
Top-level include file for the mcuxClKey component.
+
mcuxClAead_process
mcuxClAead_Status_t mcuxClAead_process(mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
Multi-part authenticated encryption/decryption processing function for the regular data (authenticate...
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClAead_verify
mcuxClAead_Status_t mcuxClAead_verify(mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pTag, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
Multi-part authenticated decryption verification function.
+
mcuxClAead_crypt
mcuxClAead_Status_t mcuxClAead_crypt(mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag, uint32_t tagLength)
One-shot authenticated encryption/decryption function.
+
mcuxClAead_Types.h
Type definitions for the mcuxClAead component.
+
mcuxClAead_process_adata
mcuxClAead_Status_t mcuxClAead_process_adata(mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength)
Multi-part authenticated encryption/decryption processing function for the associated data (authentic...
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClAead_Mode_t
const mcuxClAead_ModeDescriptor_t *const mcuxClAead_Mode_t
AEAD mode/algorithm type.
Definition: mcuxClAead_Types.h:63
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClAead_init
mcuxClAead_Status_t mcuxClAead_init(mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, uint32_t inLength, uint32_t adataLength, uint32_t tagLength)
Multi-part authenticated encryption/decryption initialization function.
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00212.html b/components/els_pkc/doc/mcxn/html/a00212.html new file mode 100644 index 000000000..f6bf89b98 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00212.html @@ -0,0 +1,157 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Typedefs
+
+
mcuxClAead_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClAead component. +More...

+
#include <mcuxClConfig.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <mcuxClSession.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t
 AEAD mode/algorithm descriptor type. More...
 
typedef const mcuxClAead_ModeDescriptor_t *const mcuxClAead_Mode_t
 AEAD mode/algorithm type. More...
 
typedef struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t
 Aead selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClAead_TestDescriptor_t *const mcuxClAead_Test_t
 Aead selftest mode/algorithm type. More...
 
typedef struct mcuxClAead_Context mcuxClAead_Context_t
 AEAD context type. More...
 
typedef uint32_t mcuxClAead_Status_t
 AEAD status code. More...
 
+

Detailed Description

+

Type definitions for the mcuxClAead component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00212.js b/components/els_pkc/doc/mcxn/html/a00212.js new file mode 100644 index 000000000..567cc2e3f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00212.js @@ -0,0 +1,9 @@ +var a00212 = +[ + [ "mcuxClAead_ModeDescriptor_t", "a00666.html#ga8378bbf26468fde8248b08efca599481", null ], + [ "mcuxClAead_Mode_t", "a00666.html#ga8084949e97b9ab9cd35ac041b8bbea0a", null ], + [ "mcuxClAead_TestDescriptor_t", "a00666.html#gae182daa83ee8ec992f261f2b52b20adb", null ], + [ "mcuxClAead_Test_t", "a00666.html#gab0222b5a8fcc204e08515b0b558fb5fe", null ], + [ "mcuxClAead_Context_t", "a00666.html#gaf67b42507181f9793498bfaaab35a48a", null ], + [ "mcuxClAead_Status_t", "a00666.html#ga1497c344a218545c5980a407e7c9194d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00212_source.html b/components/els_pkc/doc/mcxn/html/a00212_source.html new file mode 100644 index 000000000..0ed196e25 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00212_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Types.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClAead_Types.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021,2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLAEAD_TYPES_H_
19 #define MCUXCLAEAD_TYPES_H_
20 
21 #include <mcuxClConfig.h> // Exported features flags header
22 
23 #include <stdint.h>
24 #include <stdbool.h>
25 #include <stddef.h>
26 
27 #include <mcuxClSession.h>
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 
47 struct mcuxClAead_ModeDescriptor;
48 
55 typedef struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t;
56 
57 
63 typedef const mcuxClAead_ModeDescriptor_t * const mcuxClAead_Mode_t;
64 
71 struct mcuxClAead_TestDescriptor;
72 
79 typedef struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t;
80 
86 typedef const mcuxClAead_TestDescriptor_t * const mcuxClAead_Test_t;
87 
94 struct mcuxClAead_Context;
95 
102 typedef struct mcuxClAead_Context mcuxClAead_Context_t;
103 
110 typedef uint32_t mcuxClAead_Status_t;
111 
114 #ifdef __cplusplus
115 } /* extern "C" */
116 #endif
117 
118 #endif /* MCUXCLAEAD_TYPES_H_ */
mcuxClAead_Status_t
uint32_t mcuxClAead_Status_t
AEAD status code.
Definition: mcuxClAead_Types.h:110
+
mcuxClAead_Context_t
struct mcuxClAead_Context mcuxClAead_Context_t
AEAD context type.
Definition: mcuxClAead_Types.h:102
+
mcuxClAead_Test_t
const mcuxClAead_TestDescriptor_t *const mcuxClAead_Test_t
Aead selftest mode/algorithm type.
Definition: mcuxClAead_Types.h:86
+
mcuxClAead_TestDescriptor_t
struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t
Aead selftest mode/algorithm descriptor type.
Definition: mcuxClAead_Types.h:79
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClAead_Mode_t
const mcuxClAead_ModeDescriptor_t *const mcuxClAead_Mode_t
AEAD mode/algorithm type.
Definition: mcuxClAead_Types.h:63
+
mcuxClAead_ModeDescriptor_t
struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t
AEAD mode/algorithm descriptor type.
Definition: mcuxClAead_Types.h:55
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00215_source.html b/components/els_pkc/doc/mcxn/html/a00215_source.html new file mode 100644 index 000000000..5d2b565f6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00215_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClAeadModes.h Source File + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClAeadModes.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLAEADMODES_H_
15 #define MCUXCLAEADMODES_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClAeadModes_Modes.h>
19 #include <mcuxClAeadModes_MemoryConsumption.h>
20 
21 
22 #endif /* MCUXCLAEADMODES_H_ */
mcuxClAeadModes_Modes.h
This file defines the modes for the mcuxClAeadModes component.
+
mcuxClAeadModes_MemoryConsumption.h
Defines the memory consumption for the clAeadModes component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00218.html b/components/els_pkc/doc/mcxn/html/a00218.html new file mode 100644 index 000000000..ca29ad771 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00218.html @@ -0,0 +1,188 @@ + + + + + + + +MCUX CLNS: mcuxClAeadModes_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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mcuxClAeadModes_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the clAeadModes component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLAEAD_SIZE_IN_CPUWORDS(size)
 
+#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_CONTEXT_SIZE
 
#define MCUXCLAEAD_WA_SIZE_MAX
 Define the max workarea size in bytes required for this component. More...
 
+#define MCUXCLAEAD_WA_SIZE_IN_WORDS_MAX
 
+

Detailed Description

+

Defines the memory consumption for the clAeadModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00218.js b/components/els_pkc/doc/mcxn/html/a00218.js new file mode 100644 index 000000000..349179570 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00218.js @@ -0,0 +1,21 @@ +var a00218 = +[ + [ "MCUXCLAEAD_SIZE_IN_CPUWORDS", "a00667.html#ga53e8c4dc830f50602ff699bf0b747495", null ], + [ "MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE", "a00667.html#ga0d28570552a4193d7077054cbda8e618", null ], + [ "MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#gaf205dbdf5c15f82012a737aff0c00a08", null ], + [ "MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE", "a00667.html#gae82e7089a8cecc5b45bd852ea297b0c1", null ], + [ "MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#gaa19dc3346683e79084c252cd00c9e8f1", null ], + [ "MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE", "a00667.html#ga9603396be29445bde86580ed7dbfad26", null ], + [ "MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#ga32478a7abada179f4de0de2e0ead4dc9", null ], + [ "MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE", "a00667.html#gac0c234139ddc3dacfb48774e34565140", null ], + [ "MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#gaaae9aecd6c4b7d34ec93ef74be250ca5", null ], + [ "MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE", "a00667.html#ga659891bea9bc39459ec08e63425ffd9c", null ], + [ "MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#ga50aed34b2310689b37909b6461ce1e4f", null ], + [ "MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE", "a00667.html#gadfc0bd4adcf283c13dd2c5411cd12b83", null ], + [ "MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#ga4d51597b8101e7236462bbdbc18b8d8a", null ], + [ "MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE", "a00667.html#gaa7c6348ab0e03e3c682368c4eec68a68", null ], + [ "MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00667.html#gac639e0e2b92fb940c4b22e0b264b6a44", null ], + [ "MCUXCLAEAD_CONTEXT_SIZE", "a00667.html#gace6ad3b0b19634794833b688437380ff", null ], + [ "MCUXCLAEAD_WA_SIZE_MAX", "a00667.html#gab4cc3939b235a6d122ce012c23d3e61a", null ], + [ "MCUXCLAEAD_WA_SIZE_IN_WORDS_MAX", "a00667.html#gaf71be8e9107754f330cd397794b12ab3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00218_source.html b/components/els_pkc/doc/mcxn/html/a00218_source.html new file mode 100644 index 000000000..9018c27fd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00218_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClAeadModes_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAeadModes_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLAEADMODES_MEMORYCONSUMPTION_H_
18 #define MCUXCLAEADMODES_MEMORYCONSUMPTION_H_
19 
27 /* Macro to calculate the WA size in the CPU wordsize */
28 #define MCUXCLAEAD_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t)))
29 
30 
31 #define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE (124u)
32 #define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE )
33 
34 #define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE (4u)
35 #define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE )
36 
37 
38 
39 
40 #define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE (4u)
41 #define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE )
42 #define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE (4u)
43 #define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE )
44 #define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE (4u)
45 #define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE )
46 #define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE (4u)
47 #define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE )
48 #define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE (124u)
49 #define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE )
50 
51 #define MCUXCLAEAD_CONTEXT_SIZE (124u)
52 
53 
58 #define MCUXCLAEAD_WA_SIZE_MAX (124u)
59 #define MCUXCLAEAD_WA_SIZE_IN_WORDS_MAX MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_WA_SIZE_MAX )
60  /* mcuxClAead_MemoryConsumption */
64 
65 #endif /* MCUXCLAEADMODES_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00221.html b/components/els_pkc/doc/mcxn/html/a00221.html new file mode 100644 index 000000000..d6a44c096 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00221.html @@ -0,0 +1,321 @@ + + + + + + + +MCUX CLNS: mcuxClAeadModes_Modes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClAeadModes_Modes.h File Reference
+
+
+ +

This file defines the modes for the mcuxClAeadModes component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClAead_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC
 AES CCM encrypt mode descriptor. More...
 
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_ENC
 AES CCM encrypt mode. More...
 
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC
 AES CCM decrypt mode descriptor. More...
 
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_DEC
 AES CCM decrypt mode. More...
 
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC
 AES GCM encrypt mode descriptor. More...
 
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_ENC
 AES GCM encrypt mode. More...
 
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC
 AES GCM decrypt mode descriptor. More...
 
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_DEC
 AES GCM decrypt mode. More...
 
+

Detailed Description

+

This file defines the modes for the mcuxClAeadModes component.

+

Variable Documentation

+ +

◆ mcuxClAead_ModeDescriptor_AES_CCM_ENC

+ +
+
+ + + + +
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC
+
+ +

AES CCM encrypt mode descriptor.

+ +
+
+ +

◆ mcuxClAead_Mode_AES_CCM_ENC

+ +
+
+ + + + + +
+ + + + +
mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_ENC
+ 		+static
+
+ +

AES CCM encrypt mode.

+ +
+
+ +

◆ mcuxClAead_ModeDescriptor_AES_CCM_DEC

+ +
+
+ + + + +
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC
+
+ +

AES CCM decrypt mode descriptor.

+ +
+
+ +

◆ mcuxClAead_Mode_AES_CCM_DEC

+ +
+
+ + + + + +
+ + + + +
mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_DEC
+ 		+static
+
+ +

AES CCM decrypt mode.

+ +
+
+ +

◆ mcuxClAead_ModeDescriptor_AES_GCM_ENC

+ +
+
+ + + + +
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC
+
+ +

AES GCM encrypt mode descriptor.

+ +
+
+ +

◆ mcuxClAead_Mode_AES_GCM_ENC

+ +
+
+ + + + + +
+ + + + +
mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_ENC
+ 		+static
+
+ +

AES GCM encrypt mode.

+ +
+
+ +

◆ mcuxClAead_ModeDescriptor_AES_GCM_DEC

+ +
+
+ + + + +
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC
+
+ +

AES GCM decrypt mode descriptor.

+ +
+
+ +

◆ mcuxClAead_Mode_AES_GCM_DEC

+ +
+
+ + + + + +
+ + + + +
mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_DEC
+ 		+static
+
+ +

AES GCM decrypt mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00221.js b/components/els_pkc/doc/mcxn/html/a00221.js new file mode 100644 index 000000000..327cd915b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00221.js @@ -0,0 +1,11 @@ +var a00221 = +[ + [ "mcuxClAead_ModeDescriptor_AES_CCM_ENC", "a00221.html#ac05fdd0d08e4c25390079671875363f3", null ], + [ "mcuxClAead_Mode_AES_CCM_ENC", "a00221.html#a2bcc801c8d408f932f10ef5834bd4dca", null ], + [ "mcuxClAead_ModeDescriptor_AES_CCM_DEC", "a00221.html#a6a1aa3e495a39a8c6d8e399e2195daf2", null ], + [ "mcuxClAead_Mode_AES_CCM_DEC", "a00221.html#a2200749ce58283a93c563c8ca588b266", null ], + [ "mcuxClAead_ModeDescriptor_AES_GCM_ENC", "a00221.html#a8874663e21c7e81e855ebcceacdd300a", null ], + [ "mcuxClAead_Mode_AES_GCM_ENC", "a00221.html#ac6b194ee963fcd02a46c187436486f3a", null ], + [ "mcuxClAead_ModeDescriptor_AES_GCM_DEC", "a00221.html#ac167912520d7408603f0b4115ea59150", null ], + [ "mcuxClAead_Mode_AES_GCM_DEC", "a00221.html#afec8f3f6510075056a56f46fcec29f0d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00221_source.html b/components/els_pkc/doc/mcxn/html/a00221_source.html new file mode 100644 index 000000000..8ae1952a5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00221_source.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClAeadModes_Modes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAeadModes_Modes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLAEADMODES_MODES_H_
18 #define MCUXCLAEADMODES_MODES_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 #include <mcuxClAead_Types.h>
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
46 extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC;
47 
51 static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_ENC =
52  &mcuxClAead_ModeDescriptor_AES_CCM_ENC;
53 
57 extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC;
58 
62 static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_DEC =
63  &mcuxClAead_ModeDescriptor_AES_CCM_DEC;
64 
68 extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC;
69 
73 static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_ENC =
74  &mcuxClAead_ModeDescriptor_AES_GCM_ENC;
75 
79 extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC;
80 
84 static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_DEC =
85  &mcuxClAead_ModeDescriptor_AES_GCM_DEC;
89 #ifdef __cplusplus
90 } /* extern "C" */
91 #endif
92 
93 #endif /* MCUXCLAEADMODES_MODES_H_ */
mcuxClAead_ModeDescriptor_AES_GCM_ENC
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC
AES GCM encrypt mode descriptor.
+
mcuxClAead_Mode_AES_CCM_ENC
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_ENC
AES CCM encrypt mode.
Definition: mcuxClAeadModes_Modes.h:51
+
mcuxClAead_ModeDescriptor_AES_GCM_DEC
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC
AES GCM decrypt mode descriptor.
+
mcuxClAead_Mode_AES_CCM_DEC
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_DEC
AES CCM decrypt mode.
Definition: mcuxClAeadModes_Modes.h:62
+
mcuxClAead_Mode_AES_GCM_DEC
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_DEC
AES GCM decrypt mode.
Definition: mcuxClAeadModes_Modes.h:84
+
mcuxClAead_Types.h
Type definitions for the mcuxClAead component.
+
mcuxClAead_ModeDescriptor_AES_CCM_DEC
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC
AES CCM decrypt mode descriptor.
+
mcuxClAead_Mode_AES_GCM_ENC
static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_ENC
AES GCM encrypt mode.
Definition: mcuxClAeadModes_Modes.h:73
+
mcuxClAead_Mode_t
const mcuxClAead_ModeDescriptor_t *const mcuxClAead_Mode_t
AEAD mode/algorithm type.
Definition: mcuxClAead_Types.h:63
+
mcuxClAead_ModeDescriptor_AES_CCM_ENC
const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC
AES CCM encrypt mode descriptor.
+
mcuxClAead_ModeDescriptor_t
struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t
AEAD mode/algorithm descriptor type.
Definition: mcuxClAead_Types.h:55
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00224.html b/components/els_pkc/doc/mcxn/html/a00224.html new file mode 100644 index 000000000..7cc2c5fcb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00224.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClAes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAes.h File Reference
+
+
+ +

Top-level interface header for the mcuxClAes component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClAes_Constants.h>
+#include <mcuxClAes_KeyTypes.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level interface header for the mcuxClAes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00224_source.html b/components/els_pkc/doc/mcxn/html/a00224_source.html new file mode 100644 index 000000000..64c1167a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00224_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClAes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLAES_H_
20 #define MCUXCLAES_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #include <mcuxClAes_Constants.h>
25 #include <mcuxClAes_KeyTypes.h>
26 #endif /* MCUXCLAES_H_ */
mcuxClAes_KeyTypes.h
Definition of supported key types in mcuxClAes component, see also mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00227_source.html b/components/els_pkc/doc/mcxn/html/a00227_source.html new file mode 100644 index 000000000..409e7331b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00227_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClAes_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAes_Constants.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLAES_CONSTANTS_H_
15 #define MCUXCLAES_CONSTANTS_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 
19 #include <mcuxClKey_Constants.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
32 /* Block size */
33 #define MCUXCLAES_BLOCK_SIZE (16u)
34 #define MCUXCLAES_BLOCK_SIZE_IN_WORDS (MCUXCLAES_BLOCK_SIZE / sizeof(uint32_t))
35 
36 /* Key sizes */
37 #define MCUXCLAES_AES128_KEY_SIZE (MCUXCLKEY_SIZE_128)
38 #define MCUXCLAES_AES128_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_128_IN_WORDS)
39 #define MCUXCLAES_AES192_KEY_SIZE (MCUXCLKEY_SIZE_192)
40 #define MCUXCLAES_AES192_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_192_IN_WORDS)
41 #define MCUXCLAES_AES256_KEY_SIZE (MCUXCLKEY_SIZE_256)
42 #define MCUXCLAES_AES256_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_256_IN_WORDS)
43 
44  /* mcuxClAes_Constants */
47 
48 #ifdef __cplusplus
49 } /* extern "C" */
50 #endif
51 
52 #endif /* MCUXCLAES_CONSTANTS_H_ */
mcuxClKey_Constants.h
Constants for the mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00230.html b/components/els_pkc/doc/mcxn/html/a00230.html new file mode 100644 index 000000000..aec26b637 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00230.html @@ -0,0 +1,156 @@ + + + + + + + +MCUX CLNS: mcuxClAes_KeyTypes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClAes_KeyTypes.h File Reference
+
+
+ +

Definition of supported key types in mcuxClAes component, see also mcuxClKey component. +More...

+
#include <mcuxClConfig.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <mcuxClKey_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128
 Key type structure for AES-128 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes128
 Key type pointer for AES-128 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192
 Key type structure for AES-192 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes192
 Key type pointer for AES-192 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256
 Key type structure for AES-256 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes256
 Key type pointer for AES-256 based keys. More...
 
+

Detailed Description

+

Definition of supported key types in mcuxClAes component, see also mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00230.js b/components/els_pkc/doc/mcxn/html/a00230.js new file mode 100644 index 000000000..155c08866 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00230.js @@ -0,0 +1,9 @@ +var a00230 = +[ + [ "mcuxClKey_TypeDescriptor_Aes128", "a00670.html#ga8f7fce2b87e12c68354d223b9a75dc37", null ], + [ "mcuxClKey_Type_Aes128", "a00670.html#ga8f0a74b8ec63f9bcfff2723f37602d0d", null ], + [ "mcuxClKey_TypeDescriptor_Aes192", "a00670.html#ga16e79ab35a7a7da20948688481fe15ad", null ], + [ "mcuxClKey_Type_Aes192", "a00670.html#gaaeae50366310367805cb6ae6d81d88b1", null ], + [ "mcuxClKey_TypeDescriptor_Aes256", "a00670.html#ga5a8d0b88ec6b1da1730d861ca6fb7f97", null ], + [ "mcuxClKey_Type_Aes256", "a00670.html#ga1249b014f089397821eceab3fd04ed5c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00230_source.html b/components/els_pkc/doc/mcxn/html/a00230_source.html new file mode 100644 index 000000000..c1478a6ba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00230_source.html @@ -0,0 +1,130 @@ + + + + + + + +MCUX CLNS: mcuxClAes_KeyTypes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClAes_KeyTypes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLAES_KEYTYPES_H_
20 #define MCUXCLAES_KEYTYPES_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 
27 #include <mcuxClKey_Types.h>
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ")
34 
35 
45 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128;
46 
50 static const mcuxClKey_Type_t mcuxClKey_Type_Aes128 = &mcuxClKey_TypeDescriptor_Aes128;
51 
56 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192;
57 
61 static const mcuxClKey_Type_t mcuxClKey_Type_Aes192 = &mcuxClKey_TypeDescriptor_Aes192;
62 
67 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256;
68 
72 static const mcuxClKey_Type_t mcuxClKey_Type_Aes256 = &mcuxClKey_TypeDescriptor_Aes256;
73  /* mcuxClAes_KeyTypes */
77 
78 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
79 
80 #ifdef __cplusplus
81 } /* extern "C" */
82 #endif
83 
84 #endif /* MCUXCLAES_KEYTYPES_H_ */
mcuxClKey_TypeDescriptor_Aes256
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256
Key type structure for AES-256 based keys.
+
mcuxClKey_Type_Aes128
static const mcuxClKey_Type_t mcuxClKey_Type_Aes128
Key type pointer for AES-128 based keys.
Definition: mcuxClAes_KeyTypes.h:50
+
mcuxClKey_TypeDescriptor_t
struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
Key type descriptor type.
Definition: mcuxClKey_Types.h:104
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey_Type_Aes192
static const mcuxClKey_Type_t mcuxClKey_Type_Aes192
Key type pointer for AES-192 based keys.
Definition: mcuxClAes_KeyTypes.h:61
+
mcuxClKey_Type_Aes256
static const mcuxClKey_Type_t mcuxClKey_Type_Aes256
Key type pointer for AES-256 based keys.
Definition: mcuxClAes_KeyTypes.h:72
+
mcuxClKey_TypeDescriptor_Aes192
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192
Key type structure for AES-192 based keys.
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxClKey_TypeDescriptor_Aes128
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128
Key type structure for AES-128 based keys.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00233.html b/components/els_pkc/doc/mcxn/html/a00233.html new file mode 100644 index 000000000..77070313c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00233.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClCipher.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipher.h File Reference
+
+
+ +

Top-level include file for the mcuxClCipher component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClCipher_Types.h>
+#include <mcuxClCipher_Functions.h>
+#include <mcuxClCipher_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClCipher component.

+

Top-level include file for the mcuxClCipherModes component.

+

This includes headers for all of the functionality provided by the mcuxClCipher component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00233_source.html b/components/els_pkc/doc/mcxn/html/a00233_source.html new file mode 100644 index 000000000..4d2113309 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00233_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClCipher.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipher.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCIPHER_H_
15 #define MCUXCLCIPHER_H_
16 
46 #include <mcuxClConfig.h> // Exported features flags header
47 #include <mcuxClCipher_Types.h>
48 #include <mcuxClCipher_Functions.h>
49 #include <mcuxClCipher_Constants.h>
50 #include <mcuxClCipher_Types.h>
51 
52 #endif /* MCUXCLCIPHER_H_ */
mcuxClCipher_Functions.h
Top-level API of the mcuxClCipher component.
+
mcuxClCipher_Types.h
Type definitions for the mcuxClCipher component.
+
mcuxClCipher_Constants.h
Constants for use with the mcuxClCipher component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00236.html b/components/els_pkc/doc/mcxn/html/a00236.html new file mode 100644 index 000000000..ac26f695a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00236.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClCipher_Constants.h File Reference
+
+
+ +

Constants for use with the mcuxClCipher component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLCIPHER_STATUS_ERROR
 
+#define MCUXCLCIPHER_STATUS_FAILURE
 
+#define MCUXCLCIPHER_STATUS_INVALID_INPUT
 
+#define MCUXCLCIPHER_STATUS_ERROR_MEMORY_ALLOCATION
 
+#define MCUXCLCIPHER_STATUS_FAULT_ATTACK
 
+#define MCUXCLCIPHER_STATUS_OK
 
+#define MCUXCLCIPHER_STATUS_JOB_STARTED
 
+#define MCUXCLCIPHER_STATUS_JOB_COMPLETED
 
+#define MCUXCLCIPHER_STATUS_JOB_UNAVAILABLE
 
+

Detailed Description

+

Constants for use with the mcuxClCipher component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00236.js b/components/els_pkc/doc/mcxn/html/a00236.js new file mode 100644 index 000000000..b465ee970 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00236.js @@ -0,0 +1,12 @@ +var a00236 = +[ + [ "MCUXCLCIPHER_STATUS_ERROR", "a00672.html#ga350c525bf22b1a9c0297a36fe10f10e7", null ], + [ "MCUXCLCIPHER_STATUS_FAILURE", "a00672.html#ga88dab6d131989e4cca5fbfe2a666b277", null ], + [ "MCUXCLCIPHER_STATUS_INVALID_INPUT", "a00672.html#ga3d713d890dd9e6c2830f1e71d60b10e3", null ], + [ "MCUXCLCIPHER_STATUS_ERROR_MEMORY_ALLOCATION", "a00672.html#ga3477f9802814956f0ad47cb7d96c8ea9", null ], + [ "MCUXCLCIPHER_STATUS_FAULT_ATTACK", "a00672.html#ga001d7e59d3c2904c0962f5ef013ed2f3", null ], + [ "MCUXCLCIPHER_STATUS_OK", "a00672.html#ga42278cd4637634ffa6d97b8e0e74c27c", null ], + [ "MCUXCLCIPHER_STATUS_JOB_STARTED", "a00672.html#ga2cc0714dead5d4fecff9cf576c0f4099", null ], + [ "MCUXCLCIPHER_STATUS_JOB_COMPLETED", "a00672.html#ga0e213ff812de409b99dd0a79a789c639", null ], + [ "MCUXCLCIPHER_STATUS_JOB_UNAVAILABLE", "a00672.html#ga076f7c37aa40f16ac8ac7ad804418f6f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00236_source.html b/components/els_pkc/doc/mcxn/html/a00236_source.html new file mode 100644 index 000000000..ab0b615a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00236_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
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+ +
+ +
+
+
mcuxClCipher_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLCIPHER_CONSTANTS_H_
18 #define MCUXCLCIPHER_CONSTANTS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 
29 /* Error codes */
30 /* TODO CLNS-8684: Unionize and describe return codes */
31 #define MCUXCLCIPHER_STATUS_ERROR ((mcuxClCipher_Status_t) 0x02225330u)
32 #define MCUXCLCIPHER_STATUS_FAILURE ((mcuxClCipher_Status_t) 0x02225334u)
33 #define MCUXCLCIPHER_STATUS_INVALID_INPUT ((mcuxClCipher_Status_t) 0x022253F8u)
34 #define MCUXCLCIPHER_STATUS_ERROR_MEMORY_ALLOCATION ((mcuxClCipher_Status_t) 0x0222533Cu) // memory allocation error
35 #define MCUXCLCIPHER_STATUS_FAULT_ATTACK ((mcuxClCipher_Status_t) 0x0222F0F0u)
36 #define MCUXCLCIPHER_STATUS_OK ((mcuxClCipher_Status_t) 0x02222E03u)
37 #define MCUXCLCIPHER_STATUS_JOB_STARTED ((mcuxClCipher_Status_t) 0x02222E47u)
38 #define MCUXCLCIPHER_STATUS_JOB_COMPLETED ((mcuxClCipher_Status_t) 0x02222E8Bu)
39 #define MCUXCLCIPHER_STATUS_JOB_UNAVAILABLE ((mcuxClCipher_Status_t) 0x022289BCu)
40 
42 #endif /* MCUXCLCIPHER_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00239.html b/components/els_pkc/doc/mcxn/html/a00239.html new file mode 100644 index 000000000..a87543190 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00239.html @@ -0,0 +1,436 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClCipher_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClCipher component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClKey_Types.h>
+#include <mcuxClCipher_Types.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Functions

mcuxClCipher_Status_t mcuxClCipher_crypt (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClCipher_Mode_t mode, mcuxCl_InputBuffer_t pIv, uint32_t ivLength, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 One-shot encryption/decryption function. More...
 
mcuxClCipher_Status_t mcuxClCipher_init (mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClCipher_Mode_t mode, mcuxCl_InputBuffer_t pIv, uint32_t ivLength)
 Multi-part encryption/decryption initialization function. More...
 
mcuxClCipher_Status_t mcuxClCipher_process (mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part encryption/decryption processing function. More...
 
mcuxClCipher_Status_t mcuxClCipher_finish (mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part encryption/decryption finalization function. More...
 
+

Detailed Description

+

Top-level API of the mcuxClCipher component.

+

Function Documentation

+ +

◆ mcuxClCipher_crypt()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClCipher_Status_t mcuxClCipher_crypt (mcuxClSession_Handle_t session,
mcuxClKey_Handle_t key,
mcuxClCipher_Mode_t mode,
mcuxCl_InputBuffer_t pIv,
uint32_t ivLength,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength 
)
+
+ +

One-shot encryption/decryption function.

+

This function performs an encryption/decryption operation in one shot. The algorithm to be used will be determined based on the mode that is provided.

+

For example, to perform an AES encryption/decryption operation with a 128-bit key in CBC mode on padded data, the following needs to be provided:

    +
  • AES128 key
    • +
  • CBC mode for encryption, without padding
    • +
  • IV, same size as the AES block size
    • +
  • Plain input data, size must be a multiple of the AES block size
    • +
  • Output data buffer, with the same size as the input data
    • +
  • Output size buffer, to store the amount of written bytes
    • +
+
Parameters
+ + + + + + + + + + +
sessionHandle for the current CL session.
keyKey to be used to encrypt the data.
modeCipher mode that should be used during the encryption/decryption operation.
[in]pIvPointer to the buffer that contains the IV, if needed for the chosen mode, otherwise ignored.
ivLengthNumber of bytes of data in the pIv buffer.
[in]pInPointer to the input buffer that contains the plain data that needs to be encrypted.
inLengthNumber of bytes of plain data in the pIn buffer.
[out]pOutPointer to the output buffer where the encrypted data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of encrypted data that have been written to the pOut buffer.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClCipher_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClCipher_Status_t mcuxClCipher_init (mcuxClSession_Handle_t session,
mcuxClCipher_Context_t *const pContext,
mcuxClKey_Handle_t key,
mcuxClCipher_Mode_t mode,
mcuxCl_InputBuffer_t pIv,
uint32_t ivLength 
)
+
+ +

Multi-part encryption/decryption initialization function.

+

This function performs the initialization for a multi part encryption/decryption operation. The algorithm to be used will be determined based on the mode that is provided.

+
Parameters
+ + + + + + + +
sessionHandle for the current CL session.
pContextCipher context which is used to maintain the state and store other relevant information about the operation.
keyKey to be used to encrypt the data.
modeCipher mode that should be used during the encryption/decryption operation.
[in]pIvPointer to the buffer that contains the IV, if needed for the chosen mode, otherwise ignored.
ivLengthNumber of bytes of data in the pIv buffer.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClCipher_process()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClCipher_Status_t mcuxClCipher_process (mcuxClSession_Handle_t session,
mcuxClCipher_Context_t *const pContext,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength 
)
+
+ +

Multi-part encryption/decryption processing function.

+

This function performs the processing of (a part of) a data stream for an encryption/decryption operation. The algorithm and key to be used will be determined based on the context that is provided. Data is processed in full blocks only. Remaining data is stored in the context to be handled in later process or finish calls.

+
Parameters
+ + + + + + + +
sessionHandle for the current CL session.
pContextCipher context which is used to maintain the state and store other relevant information about the operation.
[in]pInPointer to the input buffer that contains the data that needs to be processed.
inLengthNumber of bytes of data in the pIn buffer.
[out]pOutPointer to the output buffer where the processed data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of processed data that have been written to the pOut buffer.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClCipher_finish()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClCipher_Status_t mcuxClCipher_finish (mcuxClSession_Handle_t session,
mcuxClCipher_Context_t *const pContext,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength 
)
+
+ +

Multi-part encryption/decryption finalization function.

+

This function performs the finalization of an encryption or decryption operation. The algorithm and key to be used will be determined based on the context that is provided. No new data is accepted but remaining data in the context is processed.

+
Parameters
+ + + + + +
sessionHandle for the current CL session.
pContextCipher context which is used to maintain the state and store other relevant information about the operation.
[out]pOutPointer to the output buffer where the processed data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of processed data that have been written to the pOut buffer.
+
+
+
Returns
status
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00239.js b/components/els_pkc/doc/mcxn/html/a00239.js new file mode 100644 index 000000000..00af8dc50 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00239.js @@ -0,0 +1,7 @@ +var a00239 = +[ + [ "mcuxClCipher_crypt", "a00239.html#a3bc78aed20c4d8fcf8606d46dd27bf12", null ], + [ "mcuxClCipher_init", "a00239.html#a3d0ee9a87aa371edeac7f361344aeb27", null ], + [ "mcuxClCipher_process", "a00239.html#a1a5072096f7f82fbce313d414dbb438d", null ], + [ "mcuxClCipher_finish", "a00239.html#a90ac41c7d96f333de0708126b0bce4be", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00239_source.html b/components/els_pkc/doc/mcxn/html/a00239_source.html new file mode 100644 index 000000000..b94ac8a20 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00239_source.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipher_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLCIPHER_FUNCTIONS_H_
18 #define MCUXCLCIPHER_FUNCTIONS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 #include <mcuxClSession_Types.h>
22 #include <mcuxClKey_Types.h>
23 #include <mcuxClCipher_Types.h>
24 #include <mcuxClCore_Platform.h>
25 #include <mcuxClCore_Buffer.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 
79 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_crypt)
80 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_crypt(
81  mcuxClSession_Handle_t session,
82  mcuxClKey_Handle_t key,
83  mcuxClCipher_Mode_t mode,
84  mcuxCl_InputBuffer_t pIv,
85  uint32_t ivLength,
86  mcuxCl_InputBuffer_t pIn,
87  uint32_t inLength,
88  mcuxCl_Buffer_t pOut,
89  uint32_t * const pOutLength
90 );
91 
92 
93 
119 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_init)
120 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_init(
121  mcuxClSession_Handle_t session,
122  mcuxClCipher_Context_t * const pContext,
123  mcuxClKey_Handle_t key,
124  mcuxClCipher_Mode_t mode,
125  mcuxCl_InputBuffer_t pIv,
126  uint32_t ivLength
127 ); /* init */
128 
151 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_process)
152 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_process(
153  mcuxClSession_Handle_t session,
154  mcuxClCipher_Context_t * const pContext,
155  mcuxCl_InputBuffer_t pIn,
156  uint32_t inLength,
157  mcuxCl_Buffer_t pOut,
158  uint32_t * const pOutLength
159 ); /* update */
160 
179 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_finish)
180 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_finish(
181  mcuxClSession_Handle_t session,
182  mcuxClCipher_Context_t * const pContext,
183  mcuxCl_Buffer_t pOut,
184  uint32_t * const pOutLength
185 ); /* finalize */
186 
187 
188 
189 
190 
191 #ifdef __cplusplus
192 } /* extern "C" */
193 #endif
194 
195 #endif /* MCUXCLCIPHER_FUNCTIONS_H_ */
mcuxClCipher_Types.h
Type definitions for the mcuxClCipher component.
+
mcuxClCipher_finish
mcuxClCipher_Status_t mcuxClCipher_finish(mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
Multi-part encryption/decryption finalization function.
+
mcuxClCipher_Context_t
struct mcuxClCipher_Context mcuxClCipher_Context_t
Cipher context type.
Definition: mcuxClCipher_Types.h:100
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClCipher_Status_t
uint32_t mcuxClCipher_Status_t
Cipher status code.
Definition: mcuxClCipher_Types.h:108
+
mcuxClCipher_init
mcuxClCipher_Status_t mcuxClCipher_init(mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClCipher_Mode_t mode, mcuxCl_InputBuffer_t pIv, uint32_t ivLength)
Multi-part encryption/decryption initialization function.
+
mcuxClCipher_process
mcuxClCipher_Status_t mcuxClCipher_process(mcuxClSession_Handle_t session, mcuxClCipher_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
Multi-part encryption/decryption processing function.
+
mcuxClCipher_Mode_t
const mcuxClCipher_ModeDescriptor_t *const mcuxClCipher_Mode_t
Cipher mode/algorithm type.
Definition: mcuxClCipher_Types.h:61
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCipher_crypt
mcuxClCipher_Status_t mcuxClCipher_crypt(mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClCipher_Mode_t mode, mcuxCl_InputBuffer_t pIv, uint32_t ivLength, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
One-shot encryption/decryption function.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00242.html b/components/els_pkc/doc/mcxn/html/a00242.html new file mode 100644 index 000000000..dcc259e6f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00242.html @@ -0,0 +1,157 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClCipher_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClCipher component. +More...

+
#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t
 Cipher mode/algorithm descriptor type. More...
 
typedef const mcuxClCipher_ModeDescriptor_t *const mcuxClCipher_Mode_t
 Cipher mode/algorithm type. More...
 
typedef struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t
 Cipher selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClCipher_TestDescriptor_t *const mcuxClCipher_Test_t
 Cipher selftest mode/algorithm type. More...
 
typedef struct mcuxClCipher_Context mcuxClCipher_Context_t
 Cipher context type. More...
 
typedef uint32_t mcuxClCipher_Status_t
 Cipher status code. More...
 
+

Detailed Description

+

Type definitions for the mcuxClCipher component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00242.js b/components/els_pkc/doc/mcxn/html/a00242.js new file mode 100644 index 000000000..fc4518409 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00242.js @@ -0,0 +1,9 @@ +var a00242 = +[ + [ "mcuxClCipher_ModeDescriptor_t", "a00676.html#gaa9586d961025bb80660a563be606451e", null ], + [ "mcuxClCipher_Mode_t", "a00676.html#gacd434e81399ac5f9752f61d55ecfb305", null ], + [ "mcuxClCipher_TestDescriptor_t", "a00676.html#gae10b2dde7d4883d6992adb3e23d57714", null ], + [ "mcuxClCipher_Test_t", "a00676.html#ga2d2ad865d5d552ea37a471acb2c48a74", null ], + [ "mcuxClCipher_Context_t", "a00676.html#ga9faa78dbb34107f8f28344b36b91c93d", null ], + [ "mcuxClCipher_Status_t", "a00676.html#gadcf65a3850bca1bd4059213edf23df4f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00242_source.html b/components/els_pkc/doc/mcxn/html/a00242_source.html new file mode 100644 index 000000000..18c4f2446 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00242_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipher_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLCIPHER_TYPES_H_
19 #define MCUXCLCIPHER_TYPES_H_
20 
21 #include <stdint.h>
22 #include <stdbool.h>
23 #include <stddef.h>
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxClSession.h>
27 
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
46 struct mcuxClCipher_ModeDescriptor;
47 
54 typedef struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t;
55 
61 typedef const mcuxClCipher_ModeDescriptor_t * const mcuxClCipher_Mode_t;
62 
69 struct mcuxClCipher_TestDescriptor;
70 
77 typedef struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t;
78 
84 typedef const mcuxClCipher_TestDescriptor_t * const mcuxClCipher_Test_t;
85 
92 struct mcuxClCipher_Context;
93 
100 typedef struct mcuxClCipher_Context mcuxClCipher_Context_t;
101 
108 typedef uint32_t mcuxClCipher_Status_t;
109 
112 #ifdef __cplusplus
113 } /* extern "C" */
114 #endif
115 
116 #endif /* MCUXCLCIPHER_TYPES_H_ */
mcuxClCipher_Context_t
struct mcuxClCipher_Context mcuxClCipher_Context_t
Cipher context type.
Definition: mcuxClCipher_Types.h:100
+
mcuxClCipher_Test_t
const mcuxClCipher_TestDescriptor_t *const mcuxClCipher_Test_t
Cipher selftest mode/algorithm type.
Definition: mcuxClCipher_Types.h:84
+
mcuxClCipher_Status_t
uint32_t mcuxClCipher_Status_t
Cipher status code.
Definition: mcuxClCipher_Types.h:108
+
mcuxClCipher_TestDescriptor_t
struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t
Cipher selftest mode/algorithm descriptor type.
Definition: mcuxClCipher_Types.h:77
+
mcuxClCipher_Mode_t
const mcuxClCipher_ModeDescriptor_t *const mcuxClCipher_Mode_t
Cipher mode/algorithm type.
Definition: mcuxClCipher_Types.h:61
+
mcuxClCipher_ModeDescriptor_t
struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t
Cipher mode/algorithm descriptor type.
Definition: mcuxClCipher_Types.h:54
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00245_source.html b/components/els_pkc/doc/mcxn/html/a00245_source.html new file mode 100644 index 000000000..1f566e6ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00245_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClCipherModes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipherModes.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCIPHERMODES_H_
15 #define MCUXCLCIPHERMODES_H_
16 
21 #include <mcuxClConfig.h> // Exported features flags header
22 
23 #include <mcuxClCipherModes_MemoryConsumption.h>
24 #include <mcuxClCipherModes_Modes.h>
25 
26 #endif /* MCUXCLCIPHERMODES_H_ */
mcuxClCipherModes_Modes.h
Supported modes for the mcuxClCipher component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00248_source.html b/components/els_pkc/doc/mcxn/html/a00248_source.html new file mode 100644 index 000000000..b63ebd35d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00248_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClCipherModes_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
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+
+ +
+
+
+ +
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+
+ + +
+ +
+ +
+
+
mcuxClCipherModes_MemoryConsumption.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLCIPHER_MEMORYCONSUMPTION_H_
20 #define MCUXCLCIPHER_MEMORYCONSUMPTION_H_
21 
22 /* Macro to calculate the WA size in the CPU wordsize */
23 #define MCUXCLCIPHER_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t)))
24 
25 /* Workarea sizes */
26 #define MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE (48u)
27 #define MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE)
28 
29 #define MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE (4u)
30 #define MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE (4u)
31 #define MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE (4u)
32 #define MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE)
33 #define MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE)
34 #define MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE)
35 
36 #define MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE (MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE)
37 #define MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE_IN_WORDS (MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS)
38 
39 /* Context sizes */
40 #define MCUXCLCIPHER_AES_CONTEXT_SIZE (48u)
41 #define MCUXCLCIPHER_AES_CONTEXT_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_CONTEXT_SIZE)
42 
43 
44 #endif /* MCUXCLCIPHER_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00251.html b/components/els_pkc/doc/mcxn/html/a00251.html new file mode 100644 index 000000000..ae563a049 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00251.html @@ -0,0 +1,203 @@ + + + + + + + +MCUX CLNS: mcuxClCipherModes_Modes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClCipherModes_Modes.h File Reference
+
+
+ +

Supported modes for the mcuxClCipher component. +More...

+
#include <mcuxClCipher_Types.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding
 AES ECB Encryption mode descriptor without padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding
 AES ECB Encryption mode without padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1
 AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 1. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1
 AES ECB Encryption mode with ISO/IEC 9797-1 padding method 1. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2
 AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 2. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2
 AES ECB Encryption mode with ISO/IEC 9797-1 padding method 2. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7
 AES ECB Encryption mode descriptor with PKCS7 padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7
 AES ECB Encryption mode with PKCS7 padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec
 AES ECB Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding
 AES ECB Decryption mode. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding
 AES CBC Encryption mode descriptor without padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding
 AES CBC Encryption mode without padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1
 AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 1. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1
 AES CBC Encryption mode with ISO/IEC 9797-1 padding method 1. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2
 AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 2. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2
 AES CBC Encryption mode with ISO/IEC 9797-1 padding method 2. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7
 AES CBC Encryption mode descriptor with PKCS7 padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7
 AES CBC Encryption mode with PKCS7 padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec
 AES CBC Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding
 AES CBC Decryption mode. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR
 CTR Encryption/Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR
 CTR Encryption/Decryption mode. More...
 
+

Detailed Description

+

Supported modes for the mcuxClCipher component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00251.js b/components/els_pkc/doc/mcxn/html/a00251.js new file mode 100644 index 000000000..796081eda --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00251.js @@ -0,0 +1,25 @@ +var a00251 = +[ + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding", "a00677.html#ga6d4a742e7880955c34b446d8d7ac4b18", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_NoPadding", "a00677.html#gac5863201c397e8418c5284523119ea41", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1", "a00677.html#gae27dec2288073dac847fa49e1f3e9dd8", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1", "a00677.html#ga5c3dcb833ab559f75065e0e340b02886", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2", "a00677.html#ga887163d5d571468467116cf2017f00a9", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2", "a00677.html#gae741b5b27af200b377425049545f6779", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7", "a00677.html#gad0e87e50be9066b625215cda60152589", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7", "a00677.html#ga76508d5bd12946fbb9b52749dac9f528", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Dec", "a00677.html#ga4a86accbf3ed6f707bca9208464b0fe8", null ], + [ "mcuxClCipher_Mode_AES_ECB_Dec_NoPadding", "a00677.html#gade75d09ba133c93d3e46eb1c795bb451", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding", "a00677.html#ga2cf616ea2d030fbe13a8b1ce8a3a6fa8", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_NoPadding", "a00677.html#ga807a672d6329f9c7d3beaabca651d517", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1", "a00677.html#ga22e8dfabe8c99f091cd41beeade83b2c", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1", "a00677.html#ga20b89472f917ef5dcd1493e349a2851c", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2", "a00677.html#ga270643be668dfd110388711cae932bd6", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2", "a00677.html#ga3656eebb0f185f9bec04f0cb293c42db", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7", "a00677.html#gab68a0cefd449150330bc4882ca957396", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PKCS7", "a00677.html#gad8399b835f6d454f0fa15b2b0ca41ee4", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Dec", "a00677.html#ga4c8f02ead08c8c20259cf0c0120c8420", null ], + [ "mcuxClCipher_Mode_AES_CBC_Dec_NoPadding", "a00677.html#gafcea66751b4008e0b5c9f3d3b982a3a4", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CTR", "a00677.html#ga93287cc9cd970f5c9103f1cc597027e0", null ], + [ "mcuxClCipher_Mode_AES_CTR", "a00677.html#ga6f1b191b97196025c65851958eb2a700", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00251_source.html b/components/els_pkc/doc/mcxn/html/a00251_source.html new file mode 100644 index 000000000..bca17f7ac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00251_source.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: mcuxClCipherModes_Modes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCipherModes_Modes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLCIPHERMODES_MODES_H_
19 #define MCUXCLCIPHERMODES_MODES_H_
20 
21 #include <mcuxClCipher_Types.h>
22 
23 #include <mcuxCsslAnalysis.h>
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ")
39 
40 /*
41  * Crypt Modes using the ELS
42  */
46 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding;
47 
51 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding =
52  &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding;
53 
57 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1;
58 
62 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1 =
63  &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1;
64 
68 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2;
69 
73 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2 =
74  &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2;
75 
79 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7;
80 
84 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7 =
85  &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7;
86 
90 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec;
91 
95 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding =
96  &mcuxClCipher_ModeDescriptor_AES_ECB_Dec;
97 
101 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding;
102 
106 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding =
107  &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding;
108 
112 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1;
113 
117 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1 =
118  &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1;
119 
123 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2;
124 
128 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2 =
129  &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2;
130 
134 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7;
135 
139 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7 =
140  &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7;
141 
145 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec;
146 
150 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding =
151  &mcuxClCipher_ModeDescriptor_AES_CBC_Dec;
152 
156 extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR;
157 
161 static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR =
162  &mcuxClCipher_ModeDescriptor_AES_CTR;
163 
164 
165 
166 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
167 
170 #ifdef __cplusplus
171 } /* extern "C" */
172 #endif
173 
174 #endif /* MCUXCLCIPHERMODES_MODES_H_ */
175 
mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7
AES CBC Encryption mode descriptor with PKCS7 padding.
+
mcuxClCipher_ModeDescriptor_AES_ECB_Dec
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec
AES ECB Decryption mode descriptor.
+
mcuxClCipher_Types.h
Type definitions for the mcuxClCipher component.
+
mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1
AES ECB Encryption mode with ISO/IEC 9797-1 padding method 1.
Definition: mcuxClCipherModes_Modes.h:62
+
mcuxClCipher_Mode_AES_CTR
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR
CTR Encryption/Decryption mode.
Definition: mcuxClCipherModes_Modes.h:161
+
mcuxClCipher_Mode_AES_ECB_Dec_NoPadding
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding
AES ECB Decryption mode.
Definition: mcuxClCipherModes_Modes.h:95
+
mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1
AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 1.
+
mcuxClCipher_ModeDescriptor_AES_CTR
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR
CTR Encryption/Decryption mode descriptor.
+
mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7
AES ECB Encryption mode descriptor with PKCS7 padding.
+
mcuxClCipher_Mode_t
const mcuxClCipher_ModeDescriptor_t *const mcuxClCipher_Mode_t
Cipher mode/algorithm type.
Definition: mcuxClCipher_Types.h:61
+
mcuxClCipher_ModeDescriptor_t
struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t
Cipher mode/algorithm descriptor type.
Definition: mcuxClCipher_Types.h:54
+
mcuxClCipher_Mode_AES_ECB_Enc_NoPadding
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding
AES ECB Encryption mode without padding.
Definition: mcuxClCipherModes_Modes.h:51
+
mcuxClCipher_Mode_AES_CBC_Enc_PKCS7
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7
AES CBC Encryption mode with PKCS7 padding.
Definition: mcuxClCipherModes_Modes.h:139
+
mcuxClCipher_ModeDescriptor_AES_CBC_Dec
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec
AES CBC Decryption mode descriptor.
+
mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding
AES CBC Encryption mode descriptor without padding.
+
mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2
AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 2.
+
mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1
AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 1.
+
mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2
AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 2.
+
mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding
AES ECB Encryption mode descriptor without padding.
+
mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7
AES ECB Encryption mode with PKCS7 padding.
Definition: mcuxClCipherModes_Modes.h:84
+
mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2
AES CBC Encryption mode with ISO/IEC 9797-1 padding method 2.
Definition: mcuxClCipherModes_Modes.h:128
+
mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1
AES CBC Encryption mode with ISO/IEC 9797-1 padding method 1.
Definition: mcuxClCipherModes_Modes.h:117
+
mcuxClCipher_Mode_AES_CBC_Enc_NoPadding
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding
AES CBC Encryption mode without padding.
Definition: mcuxClCipherModes_Modes.h:106
+
mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2
AES ECB Encryption mode with ISO/IEC 9797-1 padding method 2.
Definition: mcuxClCipherModes_Modes.h:73
+
mcuxClCipher_Mode_AES_CBC_Dec_NoPadding
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding
AES CBC Decryption mode.
Definition: mcuxClCipherModes_Modes.h:150
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00254_source.html b/components/els_pkc/doc/mcxn/html/a00254_source.html new file mode 100644 index 000000000..8d50a5da7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00254_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClCore_Buffer.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCore_Buffer.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCORE_BUFFER_H_
15 #define MCUXCLCORE_BUFFER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 
42 typedef const uint8_t * const mcuxCl_InputBuffer_t;
43 
51 typedef uint8_t * const mcuxCl_Buffer_t;
52 
53 
54 #endif /* MCUXCLCORE_BUFFER_H_ */
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00257_source.html b/components/els_pkc/doc/mcxn/html/a00257_source.html new file mode 100644 index 000000000..f2b7a5f82 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00257_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClCore_Examples.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCore_Examples.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCORE_EXAMPLES_H_
15 #define MCUXCLCORE_EXAMPLES_H_
16 
17 #include <mcuxClCore_Platform.h>
18 #include <mcuxCsslFlowProtection.h>
19 
24 // TODO CLNS-3599: #define MCUXCLEXAMPLE_FUNCTION(_name) uint32_t _name(void)
25 #define MCUXCLEXAMPLE_FUNCTION(_name) bool _name(void)
26 
31 #define MCUXCLEXAMPLE_STATUS_OK true // TODO CLNS-3599: 0xC001C0DEu
32 
38 #define MCUXCLEXAMPLE_OK MCUXCLEXAMPLE_STATUS_OK
39 
44 #define MCUXCLEXAMPLE_STATUS_ERROR false // TODO CLNS-3599: 0xEEEEEEEEu
45 
51 #define MCUXCLEXAMPLE_ERROR MCUXCLEXAMPLE_STATUS_ERROR
52 
53 
58 #define MCUXCLEXAMPLE_STATUS_FAILURE false // TODO CLNS-3599: 0xFFFFFFFFu
59 
65 #define MCUXCLEXAMPLE_FAILURE MCUXCLEXAMPLE_STATUS_FAILURE
66 
70 #define MCUXCLEXAMPLE_MAX( x, y ) ( ( x ) > ( y ) ? ( x ) : ( y ) )
71 
75 #define MCUXCLEXAMPLE_CEILING(x,y) (((x) + (y) - 1U) / (y))
76 
80 MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCore_assertEqual)
81 static inline bool mcuxClCore_assertEqual(const uint8_t * const x, const uint8_t * const y, uint32_t length)
82 {
83  for (uint32_t i = 0; i < length; ++i)
84  {
85  if (x[i] != y[i])
86  {
87  return false;
88  }
89  }
90 
91  return true;
92 }
93 
94 #endif /* MCUXCLCORE_EXAMPLES_H_ */
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DEF
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
Definition of a flow protected function.
Definition: mcuxCsslFlowProtection.h:159
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00260.html b/components/els_pkc/doc/mcxn/html/a00260.html new file mode 100644 index 000000000..f3b012948 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00260.html @@ -0,0 +1,18077 @@ + + + + + + + +MCUX CLNS: mcuxClCore_FunctionIdentifiers.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClCore_FunctionIdentifiers.h File Reference
+
+
+ +

Definition of function identifiers for the flow protection mechanism. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwVersion
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwConfig
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwState
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Enable_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Reset_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Disable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntEnableFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetIntEnableFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetIntFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_WaitForOperation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_LimitedWaitForOperation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetErrorFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorCode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorLevel
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Enable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Disable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_ShaDirect
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cipher_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyGen_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchange_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchangeInt_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccSign_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerify_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerifyInt_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp_SqrMultAws
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Init_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_PartialInit_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateAad_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateData_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Finalize_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cmac_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_LoadConfig_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_Trim_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hmac_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Rfc5869_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp800108_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyDelete_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvision_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvisionRom_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImport_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImportPuk_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyExport_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_handleKeyExportError
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequest_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequestRaw_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoad_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_Reseed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_Init_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandomWord
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandom
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetKeyProperties
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_export_state
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHash_import_state
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Md5
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Md5
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Md5
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_finishAbsorb
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_squeeze
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_createShakeAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_MiyaguchiPreneel
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_MiyaguchiPreneel
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_MiyaguchiPreneel
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_dmaProtectionAddressReadback
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2_direct
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_md5
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_keccak
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha3_Keccak
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_generate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXof_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_generate_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_init_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_process_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_oneshot_sha3_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_finish_shake
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadCopro
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadMemory
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_flush
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setKeyproperties
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_LoadFuncPtr_t
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_FlushFuncPtr_t
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setProtection
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_createGmacMode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Update
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Finalize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Update
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Finalize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Sw
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Sw
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Sw
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Sw
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Els
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Els
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Els
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Els
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_prepareHMACKey
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_createHmacMode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_InitLocalUptrt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_LeadingZeros
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ShiftModulus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_NDash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QDash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QSquared
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModInv
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModExp_SqrMultL2R
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestInstantiate_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestExtract_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesEcb_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesCtr_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Initialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Deinitialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_GenerateUPTRT
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Calc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcConst
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcFup
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForFinish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForReady
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_allocateCpuBuffer
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_freeAllCpuBuffers
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRtf
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_cleanup
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_destroy
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setSecurityOptions
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRandom
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_sha512
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_aead
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p256
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p384
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hmac
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_eckxh
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_extract
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ctr
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ecb
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ckdf
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hkdf
 
+#define MCUX_CSSL_FP_FUNCID_nboot_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Extract_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Expand_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Sp80056c_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_keyProv
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_get_oem_cust_cert_dice_puk
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_eck_sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_enc_blk
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_key_gen
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_sb_store_key
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_rts_get_id_clns
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_gen_oem_master_share
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_set_oem_master_share
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_store_key
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_rfc3394_wrap_manual
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_ssf_insert_cert
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384
 
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_cmac
 
+#define MCUX_CSSL_FP_FUNCID_nboot_key_delete
 
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_export_key
 
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_is_loaded
 
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_init
 
+#define MCUX_CSSL_FP_FUNCID_nboot_key_store_generate_rom_key
 
+#define MCUX_CSSL_FP_FUNCID_nboot_cmac_authenticate_romapi
 
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_manifest
 
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_block
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockVerify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDecrypt_Start
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockEncrypt_Start
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockCrypt_Finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDeriveKey
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestImportPck
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestDeriveKdk
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_DeletePck
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Cleanup
 
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa
 
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_romapi
 
+#define MCUX_CSSL_FP_FUNCID_nboot_sb3_img_authenticate_ecdsa
 
+#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_internal
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_none
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_ckdf
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveTwoScalars
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble_NIST
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult_NIST
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR_NIST
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd_NIST
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SwitchEndianness_P384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_rts_insert_cert
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetRandomStartDelay
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetRandomStartDelay
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ReleaseLock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_IsLocked
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetMasterUnlock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ConfigureCommandCRC
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetCommandCRC
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_VerifyVsRefCRC
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_RespGen_Async
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportBigEndianToPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportBigEndianFromPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SwitchEndianness
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_RandomizeUPTRT
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ReRandomizeUPTRT
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SecurePointMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwVersion
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwState
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntEnableFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntEnableFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ResetIntFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Configuration
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Lock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ConfigEval
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Enroll
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reconstruct
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_KeyGeneration
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntFlags
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_img_authenticate_ecdsa
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_dev_set_wrap_data
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_mcux
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_oem
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_TrailingZeros
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ReduceModEven
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_KeyGen
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportBigEndianFromPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_CoreKeyGen
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_ResetEventCounter
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_GetEventCounter
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportBigEndianToPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_public
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privatePlain
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noVerify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivideOdd
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssVerify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_mgf1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privateCRT
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noEncode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssEncode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SetupEnvironment
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_SetupEnvironment
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_SecureScalarMult_XZMontLadder
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_X
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeScalar
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeCoordinate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_GenerateMultiplicativeBlinding
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLastDmaAddress
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_CompareDmaFinalOutputAddress
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyAgreement
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyGeneration
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivide
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_reseed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_uninit
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_checkSecurityStrength
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncInit
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncGenerate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPQDistance
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ModInv
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_MillerRabinTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ComputeD
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_VerifyE
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_GenerateProbablePrime
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Crt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_UpdateRefCRC
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPrimeCandidate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Plain
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportLittleEndianToPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportLittleEndianFromPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportLittleEndianToPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportLittleEndianFromPkc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_SetupEnvironment
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_crypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_None
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Random
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_PKCS7
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_None
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Default
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method1
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_PKCS7
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Stream
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesGcm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_crypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process_adata
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesCcm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesCcmEls
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesGcmEls
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_getEntropyInput
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_generate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_reseed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_generatePrHandler
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PTG3_selftestAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateOutput
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_UpdateState
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_bcc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_df
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_updateEntropyInput
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createTestFromNormalMode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_DRBG_AES_Internal_blockcipher
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PTG3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createPatchMode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_incV
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reset
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_EngineEls
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Decode_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_SetupEnvironment
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateCustomKeyType
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateDomainParams
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_MAC_ISO9797_1_Method2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepEncode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepDecode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_generate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RecodeAndReorderScalar
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_FixScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult25519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectComb
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd25519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd25519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectML
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_VarScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainVarScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PrecPointImportAndValidate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Ckdf
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_crypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process_adata
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateKeyPair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_generate_keypair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_GenerateKeyPair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_Public
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_UtilsAsym_ModularExponentiation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcInitialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcDeinitialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_BlindedScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_BlindedScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PointDecFct_SEC
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_S5xyStub
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_S5xyStub
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_SetupEnvironment
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetVersionAndConfig
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetStatus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SyncReset
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntEnable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetIntEnable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ClearIntStatus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntStatus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_Lock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsLocked
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsIndexLocked
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_StartEnable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ContinueEnable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_LockIndex
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ResetIndex
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_EndOperation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_CalcHashModN
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed25519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_InitPrivKeyInputMode
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setResource
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_configure_job
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_request
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_release
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_triggerUserCallback
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_handle_interrupt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_request
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_release
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_checkConfig
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_linkKeyPair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithmeticOperation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointAdd
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_RemoveBlinding
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_ScalarMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDH_KeyAgreement
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_encrypt_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_decrypt_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finish_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_selftest_VerifyArrays
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveScalar
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PrivateKeyValidation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PublicKeyValidation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateHashPrefix
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateProtocolDescriptor
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignatureModeDescriptor
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_PreHashMessage
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair_Core
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_Core
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_Core
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_GenerateSignature
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_VerifySignature
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointSub
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ISOIEC_18033_2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ISOIEC_18033_2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_56C
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_OneStep
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_TwoStep
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ANSI_X9_63
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ANSI_X9_63
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_HKDF
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_HKDF
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_Randombytes
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_XOF_Hash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Init_And_Absorb
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Absorb
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Squeeze
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_Verify_checkInputs
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_computeMu
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_performPolynomialArithmetic
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcInitialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcDeinitialize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_backup
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClResource_restore
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_resume
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClMac_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClAead_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC16
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC32
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_verifyContextCrc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_computeContextCrc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC32
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC16
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKem_encapsulate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKem_decapsulate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_KeyGen
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi_nonBlocking
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi_nonBlocking
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_setWa
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_getWa
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi_nonBlocking
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Multipart
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClLtc_BackupStatus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClLtc_RestoreStatus
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_569
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_570
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_571
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_572
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_573
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_574
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_575
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_576
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_577
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_578
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_579
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_580
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_581
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_582
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_583
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_584
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_585
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_586
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_587
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_588
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_589
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_590
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_591
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_592
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_593
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_594
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_595
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_596
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_597
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_598
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_599
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_600
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_601
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_602
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_603
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_604
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_605
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_606
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_607
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_608
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_609
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_610
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_611
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_612
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_613
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_614
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_615
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_616
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_617
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_618
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_619
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_620
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_621
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_622
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_623
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_624
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_625
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_626
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_627
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_628
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_629
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_630
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_631
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_632
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_633
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_634
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_635
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_636
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_637
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_638
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_639
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_640
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_641
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_642
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_643
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_644
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_645
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_646
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_647
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_648
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_649
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_650
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_651
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_652
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_653
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_654
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_655
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_656
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_657
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_658
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_659
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_660
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_661
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_662
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_663
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_664
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_665
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_666
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_667
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_668
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_669
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_670
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_671
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_672
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_673
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_674
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_675
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_676
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_677
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_678
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_679
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_680
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_681
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_682
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_683
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_684
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_685
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_686
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_687
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_688
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_689
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_690
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_691
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_692
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_693
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_694
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_695
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_696
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_697
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_698
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_699
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_700
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_701
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_702
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_703
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_704
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_705
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_706
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_707
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_708
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_709
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_710
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_711
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_712
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_713
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_714
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_715
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_716
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_717
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_718
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_719
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_720
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_721
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_722
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_723
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_724
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_725
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_726
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_727
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_728
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_729
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_730
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_731
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_732
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_733
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_734
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_735
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_736
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_737
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_738
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_739
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_740
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_741
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_742
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_743
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_744
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_745
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_746
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_747
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_748
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_749
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_750
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_751
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_752
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_753
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_754
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_755
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_756
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_757
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_758
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_759
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_760
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_761
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_762
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_763
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_764
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_765
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_766
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_767
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_768
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_769
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_770
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_771
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_772
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_773
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_774
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_775
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_776
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_777
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_778
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_779
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_780
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_781
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_782
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_783
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_784
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_785
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_786
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_787
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_788
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_789
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_790
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_791
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_792
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_793
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_794
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_795
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_796
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_797
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_798
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_799
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_800
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_801
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_802
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_803
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_804
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_805
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_806
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_807
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_808
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_809
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_810
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_811
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_812
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_813
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_814
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_815
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_816
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_817
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_818
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_819
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_820
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_821
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_822
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_823
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_824
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_825
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_826
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_827
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_828
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_829
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_830
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_831
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_832
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_833
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_834
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_835
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_836
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_837
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_838
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_839
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_840
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_841
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_842
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_843
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_844
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_845
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_846
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_847
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_848
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_849
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_850
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_851
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_852
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_853
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_854
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_855
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_856
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_857
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_858
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_859
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_860
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_861
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_862
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_863
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_864
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_865
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_866
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_867
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_868
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_869
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_870
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_871
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_872
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_873
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_874
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_875
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_876
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_877
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_878
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_879
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_880
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_881
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_882
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_883
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_884
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_885
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_886
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_887
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_888
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_889
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_890
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_891
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_892
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_893
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_894
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_895
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_896
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_897
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_898
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_899
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_900
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_901
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_902
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_903
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_904
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_905
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_906
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_907
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_908
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_909
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_910
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_911
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_912
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_913
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_914
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_915
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_916
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_917
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_918
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_919
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_920
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_921
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_922
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_923
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_924
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_925
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_926
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_927
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_928
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_929
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_930
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_931
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_932
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_933
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_934
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_935
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_936
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_937
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_938
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_939
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_940
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_941
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_942
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_943
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_944
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_945
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_946
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_947
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_948
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_949
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_950
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_951
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_952
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_953
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_954
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_955
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_956
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_957
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_958
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_959
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_960
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_961
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_962
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_963
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_964
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_965
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_966
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_967
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_968
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_969
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_970
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_971
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_972
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_973
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_974
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_975
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_976
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_977
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_978
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_979
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_980
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_981
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_982
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_983
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_984
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_985
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_986
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_987
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_988
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_989
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_990
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_991
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_992
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_993
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_994
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_995
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_996
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_997
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_998
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_999
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1000
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1001
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1002
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1003
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1004
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1005
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1006
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1007
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1008
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1009
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1010
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1011
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1012
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1013
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1014
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1015
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1016
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1017
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1018
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1019
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1020
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1021
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1022
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1023
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1024
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1025
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1026
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1027
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1028
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1029
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1030
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1031
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1032
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1033
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1034
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1035
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1036
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1037
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1038
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1039
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1040
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1041
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1042
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1043
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1044
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1045
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1046
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1047
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1048
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1049
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1050
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1051
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1052
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1053
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1054
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1055
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1056
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1057
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1058
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1059
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1060
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1061
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1062
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1063
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1064
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1065
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1066
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1067
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1068
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1069
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1070
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1071
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1072
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1073
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1074
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1075
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1076
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1077
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1078
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1079
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1080
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1081
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1082
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1083
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1084
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1085
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1086
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1087
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1088
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1089
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1090
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1091
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1092
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1093
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1094
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1095
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1096
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1097
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1098
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1099
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1165
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1166
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1167
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1168
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1169
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1170
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1171
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1172
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1173
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1174
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1175
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1176
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1177
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1178
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1179
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1569
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1570
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1571
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1572
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1573
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1574
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1575
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1576
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1577
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1578
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1579
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1580
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1581
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1582
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1583
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1584
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1585
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1586
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1587
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1588
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1589
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1590
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1591
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1592
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1593
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1594
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1595
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1596
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1597
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1598
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1599
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1600
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1601
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1602
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1603
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1604
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1605
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1606
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1607
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1608
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1609
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1610
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1611
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1612
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1613
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1614
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1615
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1616
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1617
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1618
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1619
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1620
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1621
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1622
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1623
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1624
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1625
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1626
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1627
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1628
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1629
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1630
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1631
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1632
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1633
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1634
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1635
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1636
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1637
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1638
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1639
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1640
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1641
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1642
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1643
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1644
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1645
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1646
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1647
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1648
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1649
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1650
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1651
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1652
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1653
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1654
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1655
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1656
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1657
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1658
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1659
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1660
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1661
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1662
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1663
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1664
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1665
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1666
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1667
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1668
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1669
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1670
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1671
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1672
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1673
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1674
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1675
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1676
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1677
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1678
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1679
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1680
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1681
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1682
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1683
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1684
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1685
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1686
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1687
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1688
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1689
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1690
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1691
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1692
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1693
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1694
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1695
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1696
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1697
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1698
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1699
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1700
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1701
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1702
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1703
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1704
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1705
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1706
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1707
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1708
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1709
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1710
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1711
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1712
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1713
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1714
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1715
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1716
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1717
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1718
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1719
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1720
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1721
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1722
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1723
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1724
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1725
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1726
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1727
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1728
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1729
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1730
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1731
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1732
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1733
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1734
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1735
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1736
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1737
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1738
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1739
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1740
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1741
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1742
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1743
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1744
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1745
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1746
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1747
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1748
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1749
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1750
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1751
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1752
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1753
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1754
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1755
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1756
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1757
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1758
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1759
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1760
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1761
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1762
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1763
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1764
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1765
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1766
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1767
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1768
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1769
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1770
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1771
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1772
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1773
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1774
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1775
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1776
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1777
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1778
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1779
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1780
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1781
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1782
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1783
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1784
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1785
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1786
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1787
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1788
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1789
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1790
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1791
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1792
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1793
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1794
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1795
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1796
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1797
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1798
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1799
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1800
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1801
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1802
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1803
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1804
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1805
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1806
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1807
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1808
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1809
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1810
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1811
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1812
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1813
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1814
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1815
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1816
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1817
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1818
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1819
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1820
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1821
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1822
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1823
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1824
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1825
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1826
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1827
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1828
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1829
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1830
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1831
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1832
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1833
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1834
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1835
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1836
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1837
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1838
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1839
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1840
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1841
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1842
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1843
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1844
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1845
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1846
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1847
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1848
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1849
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1850
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1851
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1852
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1853
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1854
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1855
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1856
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1857
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1858
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1859
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1860
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1861
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1862
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1863
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1864
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1865
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1866
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1867
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1868
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1869
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1870
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1871
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1872
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1873
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1874
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1875
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1876
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1877
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1878
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1879
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1880
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1881
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1882
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1883
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1884
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1885
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1886
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1887
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1888
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1889
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1890
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1891
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1892
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1893
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1894
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1895
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1896
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1897
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1898
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1899
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1900
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1901
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1902
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1903
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1904
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1905
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1906
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1907
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1908
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1909
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1910
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1911
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1912
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1913
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1914
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1915
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1916
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1917
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1918
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1919
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1920
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1921
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1922
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1923
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1924
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1925
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1926
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1927
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1928
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1929
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1930
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1931
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1932
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1933
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1934
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1935
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1936
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1937
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1938
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1939
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1940
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1941
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1942
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1943
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1944
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1945
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1946
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1947
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1948
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1949
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1950
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1951
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1952
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1953
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1954
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1955
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1956
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1957
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1958
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1959
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1960
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1961
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1962
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1963
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1964
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1965
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1966
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1967
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1968
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1969
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1970
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1971
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1972
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1973
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1974
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1975
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1976
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1977
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1978
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1979
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1980
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1981
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1982
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1983
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1984
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1985
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1986
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1987
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1988
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1989
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1990
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1991
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1992
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1993
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1994
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1995
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1996
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1997
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1998
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1999
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2000
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2001
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2002
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2003
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2004
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2005
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2006
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2007
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2008
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2009
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2010
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2011
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2012
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2013
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2014
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2015
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2016
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2017
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2018
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2019
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2020
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2021
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2022
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2023
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2024
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2025
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2026
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2027
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2028
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2029
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2030
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2031
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2032
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2033
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2034
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2035
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2036
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2037
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2038
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2039
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2040
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2041
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2042
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2043
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2044
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2045
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2046
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2047
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2048
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2049
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2050
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2051
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2052
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2053
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2054
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2055
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2056
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2057
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2058
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2059
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2060
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2061
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2062
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2063
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2064
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2065
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2066
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2067
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2068
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2069
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2070
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2071
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2072
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2073
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2074
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2075
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2076
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2077
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2078
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2079
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2080
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2081
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2082
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2083
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2084
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2085
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2086
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2087
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2088
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2089
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2090
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2091
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2092
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2093
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2094
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2095
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2096
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2097
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2098
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2099
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2165
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2166
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2167
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2168
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2169
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2170
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2171
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2172
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2173
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2174
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2175
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2176
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2177
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2178
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2179
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2569
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2570
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2571
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2572
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2573
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2574
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2575
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2576
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2577
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2578
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2579
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2580
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2581
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2582
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2583
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2584
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2585
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2586
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2587
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2588
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2589
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2590
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2591
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2592
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2593
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2594
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2595
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2596
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2597
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2598
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2599
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2600
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2601
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2602
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2603
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2604
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2605
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2606
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2607
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2608
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2609
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2610
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2611
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2612
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2613
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2614
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2615
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2616
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2617
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2618
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2619
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2620
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2621
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2622
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2623
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2624
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2625
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2626
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2627
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2628
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2629
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2630
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2631
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2632
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2633
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2634
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2635
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2636
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2637
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2638
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2639
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2640
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2641
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2642
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2643
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2644
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2645
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2646
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2647
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2648
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2649
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2650
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2651
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2652
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2653
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2654
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2655
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2656
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2657
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2658
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2659
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2660
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2661
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2662
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2663
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2664
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2665
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2666
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2667
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2668
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2669
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2670
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2671
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2672
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2673
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2674
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2675
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2676
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2677
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2678
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2679
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2680
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2681
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2682
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2683
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2684
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2685
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2686
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2687
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2688
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2689
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2690
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2691
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2692
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2693
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2694
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2695
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2696
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2697
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2698
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2699
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2700
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2701
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2702
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2703
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2704
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2705
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2706
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2707
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2708
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2709
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2710
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2711
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2712
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2713
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2714
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2715
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2716
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2717
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2718
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2719
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2720
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2721
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2722
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2723
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2724
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2725
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2726
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2727
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2728
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2729
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2730
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2731
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2732
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2733
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2734
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2735
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2736
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2737
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2738
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2739
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2740
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2741
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2742
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2743
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2744
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2745
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2746
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2747
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2748
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2749
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2750
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2751
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2752
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2753
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2754
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2755
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2756
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2757
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2758
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2759
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2760
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2761
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2762
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2763
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2764
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2765
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2766
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2767
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2768
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2769
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2770
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2771
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2772
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2773
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2774
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2775
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2776
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2777
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2778
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2779
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2780
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2781
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2782
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2783
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2784
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2785
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2786
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2787
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2788
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2789
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2790
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2791
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2792
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2793
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2794
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2795
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2796
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2797
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2798
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2799
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2800
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2801
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2802
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2803
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2804
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2805
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2806
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2807
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2808
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2809
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2810
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2811
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2812
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2813
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2814
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2815
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2816
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2817
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2818
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2819
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2820
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2821
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2822
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2823
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2824
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2825
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2826
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2827
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2828
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2829
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2830
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2831
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2832
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2833
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2834
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2835
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2836
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2837
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2838
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2839
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2840
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2841
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2842
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2843
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2844
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2845
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2846
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2847
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2848
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2849
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2850
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2851
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2852
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2853
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2854
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2855
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2856
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2857
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2858
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2859
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2860
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2861
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2862
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2863
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2864
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2865
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2866
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2867
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2868
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2869
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2870
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2871
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2872
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2873
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2874
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2875
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2876
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2877
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2878
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2879
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2880
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2881
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2882
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2883
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2884
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2885
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2886
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2887
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2888
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2889
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2890
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2891
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2892
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2893
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2894
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2895
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2896
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2897
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2898
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2899
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2900
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2901
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2902
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2903
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2904
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2905
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2906
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2907
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2908
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2909
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2910
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2911
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2912
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2913
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2914
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2915
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2916
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2917
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2918
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2919
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2920
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2921
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2922
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2923
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2924
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2925
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2926
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2927
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2928
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2929
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2930
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2931
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2932
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2933
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2934
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2935
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2936
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2937
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2938
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2939
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2940
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2941
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2942
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2943
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2944
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2945
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2946
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2947
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2948
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2949
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2950
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2951
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2952
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2953
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2954
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2955
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2956
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2957
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2958
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2959
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2960
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2961
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2962
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2963
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2964
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2965
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2966
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2967
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2968
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2969
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2970
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2971
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2972
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2973
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2974
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2975
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2976
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2977
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2978
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2979
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2980
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2981
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2982
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2983
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2984
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2985
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2986
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2987
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2988
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2989
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2990
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2991
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2992
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2993
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2994
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2995
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2996
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2997
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2998
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2999
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3000
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3001
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3002
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3003
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3004
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3005
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3006
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3007
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3008
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3009
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3010
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3011
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3012
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3013
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3014
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3015
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3016
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3017
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3018
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3019
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3020
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3021
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3022
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3023
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3024
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3025
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3026
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3027
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3028
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3029
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3030
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3031
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3032
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3033
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3034
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3035
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3036
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3037
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3038
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3039
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3040
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3041
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3042
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3043
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3044
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3045
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3046
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3047
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3048
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3049
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3050
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3051
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3052
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3053
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3054
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3055
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3056
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3057
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3058
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3059
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3060
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3061
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3062
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3063
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3064
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3065
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3066
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3067
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3068
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3069
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3070
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3071
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3072
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3073
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3074
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3075
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3076
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3077
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3078
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3079
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3080
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3081
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3082
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3083
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3084
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3085
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3086
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3087
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3088
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3089
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3090
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3091
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3092
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3093
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3094
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3095
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3096
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3097
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3098
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3099
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3165
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3166
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3167
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3168
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3169
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3170
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3171
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3172
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3173
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3174
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3175
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3176
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3177
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3178
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3179
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3569
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3570
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3571
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3572
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3573
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3574
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3575
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3576
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3577
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3578
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3579
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3580
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3581
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3582
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3583
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3584
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3585
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3586
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3587
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3588
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3589
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3590
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3591
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3592
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3593
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3594
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3595
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3596
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3597
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3598
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3599
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3600
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3601
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3602
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3603
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3604
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3605
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3606
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3607
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3608
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3609
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3610
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3611
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3612
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3613
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3614
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3615
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3616
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3617
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3618
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3619
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3620
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3621
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3622
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3623
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3624
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3625
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3626
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3627
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3628
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3629
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3630
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3631
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3632
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3633
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3634
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3635
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3636
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3637
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3638
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3639
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3640
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3641
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3642
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3643
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3644
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3645
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3646
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3647
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3648
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3649
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3650
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3651
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3652
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3653
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3654
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3655
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3656
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3657
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3658
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3659
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3660
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3661
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3662
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3663
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3664
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3665
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3666
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3667
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3668
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3669
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3670
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3671
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3672
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3673
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3674
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3675
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3676
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3677
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3678
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3679
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3680
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3681
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3682
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3683
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3684
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3685
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3686
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3687
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3688
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3689
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3690
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3691
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3692
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3693
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3694
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3695
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3696
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3697
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3698
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3699
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3700
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3701
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3702
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3703
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3704
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3705
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3706
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3707
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3708
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3709
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3710
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3711
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3712
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3713
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3714
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3715
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3716
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3717
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3718
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3719
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3720
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3721
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3722
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3723
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3724
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3725
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3726
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3727
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3728
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3729
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3730
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3731
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3732
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3733
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3734
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3735
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3736
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3737
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3738
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3739
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3740
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3741
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3742
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3743
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3744
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3745
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3746
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3747
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3748
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3749
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3750
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3751
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3752
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3753
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3754
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3755
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3756
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3757
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3758
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3759
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3760
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3761
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3762
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3763
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3764
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3765
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3766
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3767
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3768
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3769
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3770
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3771
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3772
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3773
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3774
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3775
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3776
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3777
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3778
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3779
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3780
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3781
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3782
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3783
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3784
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3785
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3786
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3787
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3788
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3789
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3790
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3791
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3792
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3793
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3794
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3795
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3796
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3797
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3798
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3799
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3800
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3801
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3802
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3803
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3804
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3805
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3806
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3807
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3808
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3809
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3810
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3811
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3812
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3813
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3814
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3815
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3816
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3817
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3818
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3819
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3820
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3821
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3822
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3823
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3824
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3825
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3826
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3827
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3828
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3829
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3830
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3831
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3832
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3833
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3834
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3835
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3836
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3837
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3838
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3839
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3840
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3841
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3842
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3843
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3844
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3845
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3846
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3847
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3848
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3849
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3850
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3851
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3852
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3853
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3854
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3855
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3856
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3857
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3858
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3859
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3860
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3861
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3862
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3863
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3864
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3865
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3866
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3867
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3868
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3869
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3870
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3871
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3872
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3873
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3874
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3875
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3876
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3877
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3878
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3879
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3880
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3881
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3882
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3883
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3884
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3885
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3886
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3887
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3888
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3889
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3890
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3891
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3892
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3893
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3894
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3895
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3896
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3897
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3898
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3899
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3900
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3901
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3902
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3903
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3904
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3905
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3906
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3907
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3908
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3909
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3910
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3911
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3912
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3913
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3914
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3915
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3916
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3917
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3918
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3919
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3920
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3921
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3922
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3923
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3924
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3925
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3926
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3927
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3928
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3929
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3930
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3931
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3932
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3933
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3934
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3935
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3936
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3937
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3938
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3939
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3940
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3941
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3942
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3943
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3944
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3945
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3946
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3947
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3948
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3949
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3950
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3951
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3952
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3953
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3954
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3955
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3956
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3957
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3958
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3959
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3960
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3961
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3962
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3963
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3964
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3965
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3966
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3967
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3968
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3969
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3970
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3971
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3972
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3973
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3974
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3975
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3976
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3977
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3978
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3979
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3980
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3981
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3982
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3983
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3984
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3985
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3986
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3987
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3988
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3989
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3990
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3991
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3992
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3993
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3994
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3995
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3996
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3997
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3998
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3999
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4000
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4001
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4002
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4003
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4004
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4005
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4006
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4007
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4008
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4009
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4010
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4011
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4012
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4013
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4014
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4015
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4016
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4017
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4018
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4019
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4020
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4021
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4022
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4023
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4024
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4025
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4026
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4027
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4028
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4029
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4030
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4031
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4032
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4033
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4034
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4035
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4036
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4037
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4038
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4039
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4040
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4041
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4042
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4043
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4044
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4045
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4046
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4047
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4048
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4049
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4050
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4051
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4052
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4053
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4054
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4055
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4056
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4057
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4058
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4059
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4060
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4061
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4062
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4063
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4064
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4065
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4066
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4067
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4068
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4069
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4070
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4071
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4072
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4073
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4074
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4075
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4076
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4077
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4078
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4079
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4080
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4081
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4082
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4083
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4084
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4085
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4086
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4087
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4088
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4089
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4090
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4091
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4092
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4093
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4094
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4095
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4096
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4097
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4098
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4099
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4165
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4166
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4167
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4168
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4169
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4170
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4171
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4172
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4173
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4174
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4175
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4176
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4177
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4178
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4179
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4569
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4570
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4571
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4572
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4573
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4574
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4575
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4576
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4577
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4578
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4579
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4580
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4581
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4582
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4583
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4584
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4585
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4586
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4587
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4588
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4589
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4590
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4591
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4592
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4593
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4594
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4595
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4596
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4597
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4598
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4599
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4600
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4601
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4602
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4603
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4604
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4605
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4606
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4607
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4608
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4609
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4610
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4611
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4612
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4613
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4614
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4615
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4616
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4617
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4618
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4619
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4620
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4621
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4622
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4623
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4624
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4625
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4626
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4627
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4628
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4629
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4630
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4631
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4632
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4633
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4634
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4635
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4636
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4637
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4638
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4639
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4640
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4641
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4642
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4643
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4644
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4645
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4646
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4647
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4648
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4649
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4650
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4651
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4652
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4653
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4654
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4655
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4656
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4657
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4658
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4659
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4660
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4661
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4662
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4663
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4664
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4665
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4666
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4667
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4668
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4669
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4670
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4671
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4672
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4673
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4674
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4675
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4676
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4677
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4678
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4679
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4680
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4681
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4682
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4683
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4684
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4685
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4686
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4687
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4688
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4689
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4690
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4691
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4692
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4693
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4694
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4695
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4696
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4697
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4698
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4699
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4700
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4701
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4702
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4703
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4704
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4705
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4706
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4707
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4708
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4709
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4710
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4711
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4712
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4713
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4714
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4715
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4716
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4717
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4718
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4719
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4720
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4721
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4722
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4723
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4724
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4725
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4726
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4727
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4728
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4729
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4730
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4731
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4732
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4733
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4734
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4735
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4736
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4737
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4738
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4739
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4740
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4741
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4742
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4743
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4744
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4745
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4746
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4747
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4748
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4749
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4750
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4751
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4752
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4753
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4754
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4755
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4756
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4757
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4758
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4759
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4760
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4761
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4762
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4763
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4764
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4765
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4766
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4767
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4768
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4769
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4770
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4771
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4772
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4773
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4774
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4775
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4776
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4777
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4778
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4779
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4780
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4781
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4782
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4783
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4784
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4785
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4786
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4787
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4788
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4789
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4790
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4791
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4792
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4793
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4794
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4795
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4796
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4797
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4798
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4799
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4800
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4801
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4802
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4803
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4804
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4805
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4806
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4807
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4808
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4809
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4810
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4811
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4812
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4813
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4814
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4815
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4816
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4817
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4818
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4819
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4820
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4821
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4822
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4823
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4824
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4825
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4826
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4827
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4828
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4829
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4830
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4831
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4832
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4833
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4834
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4835
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4836
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4837
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4838
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4839
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4840
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4841
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4842
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4843
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4844
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4845
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4846
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4847
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4848
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4849
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4850
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4851
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4852
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4853
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4854
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4855
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4856
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4857
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4858
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4859
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4860
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4861
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4862
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4863
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4864
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4865
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4866
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4867
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4868
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4869
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4870
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4871
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4872
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4873
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4874
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4875
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4876
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4877
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4878
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4879
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4880
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4881
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4882
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4883
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4884
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4885
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4886
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4887
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4888
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4889
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4890
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4891
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4892
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4893
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4894
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4895
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4896
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4897
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4898
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4899
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4900
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4901
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4902
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4903
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4904
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4905
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4906
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4907
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4908
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4909
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4910
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4911
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4912
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4913
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4914
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4915
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4916
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4917
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4918
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4919
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4920
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4921
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4922
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4923
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4924
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4925
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4926
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4927
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4928
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4929
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4930
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4931
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4932
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4933
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4934
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4935
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4936
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4937
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4938
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4939
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4940
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4941
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4942
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4943
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4944
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4945
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4946
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4947
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4948
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4949
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4950
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4951
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4952
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4953
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4954
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4955
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4956
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4957
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4958
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4959
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4960
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4961
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4962
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4963
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4964
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4965
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4966
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4967
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4968
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4969
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4970
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4971
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4972
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4973
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4974
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4975
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4976
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4977
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4978
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4979
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4980
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4981
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4982
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4983
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4984
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4985
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4986
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4987
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4988
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4989
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4990
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4991
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4992
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4993
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4994
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4995
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4996
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4997
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4998
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4999
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5000
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5001
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5002
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5003
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5004
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5005
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5006
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5007
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5008
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5009
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5010
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5011
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5012
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5013
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5014
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5015
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5016
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5017
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5018
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5019
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5020
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5021
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5022
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5023
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5024
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5025
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5026
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5027
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5028
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5029
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5030
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5031
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5032
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5033
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5034
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5035
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5036
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5037
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5038
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5039
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5040
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5041
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5042
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5043
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5044
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5045
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5046
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5047
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5048
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5049
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5050
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5051
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5052
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5053
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5054
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5055
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5056
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5057
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5058
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5059
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5060
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5061
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5062
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5063
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5064
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5065
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5066
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5067
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5068
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5069
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5070
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5071
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5072
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5073
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5074
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5075
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5076
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5077
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5078
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5079
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5080
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5081
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5082
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5083
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5084
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5085
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5086
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5087
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5088
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5089
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5090
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5091
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5092
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5093
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5094
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5095
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5096
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5097
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5098
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5099
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5165
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5166
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5167
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5168
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5169
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5170
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5171
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5172
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5173
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5174
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5175
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5176
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5177
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5178
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5179
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5180
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5181
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5182
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5183
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5184
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5185
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5186
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5187
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5188
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5189
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5190
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5191
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5192
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5193
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5194
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5195
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5196
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5197
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5198
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5199
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5200
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5201
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5202
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5203
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5204
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5205
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5206
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5207
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5208
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5209
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5210
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5211
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5212
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5213
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5214
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5215
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5216
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5217
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5218
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5219
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5220
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5221
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5222
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5223
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5224
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5225
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5226
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5227
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5228
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5229
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5230
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5231
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5232
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5233
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5234
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5235
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5236
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5237
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5238
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5239
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5240
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5241
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5242
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5243
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5244
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5245
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5246
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5247
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5248
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5249
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5250
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5251
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5252
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5253
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5254
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5255
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5256
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5257
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5258
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5259
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5260
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5261
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5262
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5263
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5264
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5265
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5266
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5267
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5268
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5269
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5270
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5271
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5272
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5273
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5274
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5275
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5276
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5277
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5278
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5279
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5280
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5281
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5282
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5283
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5284
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5285
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5286
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5287
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5288
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5289
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5290
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5291
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5292
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5293
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5294
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5295
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5296
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5297
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5298
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5299
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5300
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5301
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5302
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5303
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5304
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5305
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5306
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5307
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5308
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5309
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5310
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5311
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5312
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5313
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5314
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5315
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5316
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5317
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5318
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5319
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5320
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5321
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5322
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5323
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5324
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5325
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5326
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5327
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5328
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5329
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5330
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5331
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5332
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5333
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5334
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5335
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5336
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5337
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5338
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5339
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5340
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5341
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5342
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5343
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5344
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5345
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5346
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5347
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5348
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5349
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5350
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5351
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5352
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5353
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5354
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5355
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5356
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5357
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5358
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5359
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5360
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5361
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5362
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5363
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5364
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5365
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5366
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5367
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5368
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5369
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5370
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5371
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5372
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5373
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5374
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5375
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5376
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5377
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5378
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5379
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5380
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5381
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5382
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5383
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5384
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5385
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5386
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5387
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5388
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5389
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5390
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5391
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5392
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5393
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5394
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5395
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5396
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5397
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5398
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5399
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5400
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5401
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5402
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5403
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5404
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5405
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5406
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5407
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5408
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5409
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5410
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5411
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5412
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5413
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5414
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5415
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5416
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5417
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5418
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5419
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5420
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5421
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5422
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5423
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5424
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5425
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5426
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5427
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5428
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5429
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5430
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5431
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5432
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5433
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5434
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5435
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5436
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5437
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5438
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5439
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5440
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5441
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5442
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5443
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5444
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5445
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5446
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5447
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5448
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5449
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5450
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5451
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5452
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5453
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5454
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5455
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5456
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5457
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5458
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5459
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5460
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5461
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5462
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5463
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5464
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5465
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5466
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5467
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5468
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5469
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5470
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5471
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5472
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5473
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5474
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5475
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5476
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5477
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5478
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5479
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5480
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5481
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5482
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5483
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5484
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5485
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5486
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5487
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5488
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5489
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5490
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5491
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5492
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5493
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5494
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5495
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5496
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5497
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5498
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5499
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5500
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5501
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5502
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5503
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5504
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5505
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5506
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5507
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5508
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5509
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5510
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5511
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5512
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5513
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5514
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5515
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5516
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5517
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5518
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5519
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5520
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5521
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5522
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5523
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5524
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5525
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5526
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5527
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5528
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5529
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5530
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5531
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5532
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5533
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5534
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5535
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5536
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5537
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5538
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5539
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5540
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5541
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5542
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5543
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5544
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5545
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5546
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5547
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5548
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5549
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5550
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5551
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5552
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5553
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5554
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5555
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5556
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5557
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5558
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5559
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5560
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5561
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5562
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5563
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5564
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5565
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5566
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5567
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5568
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5569
 
+

Detailed Description

+

Definition of function identifiers for the flow protection mechanism.

+
Note
This file might be post-processed to update the identifier values to proper/secure values.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00260.js b/components/els_pkc/doc/mcxn/html/a00260.js new file mode 100644 index 000000000..b7d8820e2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00260.js @@ -0,0 +1,5983 @@ +var a00260 = +[ + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwVersion", "a00260.html#a54251be1e3ff464d71bae0f54c1f4dff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwConfig", "a00260.html#ace6a57a8bfc135468fd01eec43ef479c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwState", "a00260.html#a49f046b67eedbd6c4145cee500bdadfa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Enable_Async", "a00260.html#aff367aef716bc6720310daa342d02e51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Reset_Async", "a00260.html#a2e43e3b2a425fe58165e0d8520917641", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Disable", "a00260.html#af329979bd4e76db0dc2ef9a644707fda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntEnableFlags", "a00260.html#a4ac36aa8ed0f88578fd456fca5cb1c47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetIntEnableFlags", "a00260.html#a382eccde9cc0211390815555f4d08ffe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetIntFlags", "a00260.html#a093da74dd85a92d674eef1ff93faa345", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntFlags", "a00260.html#a5a6a7df0e800dea1d5416b9e4d153797", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_WaitForOperation", "a00260.html#a2389b2b71f8d4c629b66c249d0a15dd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_LimitedWaitForOperation", "a00260.html#aa25c88012c6f822260de7eee1a65980e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetErrorFlags", "a00260.html#aacfdd6bc6df9ee3b3bac1b4bdda2e390", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorCode", "a00260.html#a60115351f66ed76d9f8aca6367c1caed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorLevel", "a00260.html#a3838ab462f6fe0823f700b36e878c37a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_Async", "a00260.html#a508a8cbbd60bb6a6b34ac2343d74da96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Enable", "a00260.html#aac8f54a8dd3b37cb702a3b9b20ec0f3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Disable", "a00260.html#a2ba9c5f891c213e0d7a9b0ced3117324", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_ShaDirect", "a00260.html#a800076b43b634fb15bfbf912d5ea94ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Cipher_Async", "a00260.html#a02c6bec39beeeccc8f99a67c4b7ff1cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyGen_Async", "a00260.html#a763eed4a82b212791278b532fd4ed8d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchange_Async", "a00260.html#a4c1f4bf9079e5905500271b4ea3b1d42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchangeInt_Async", "a00260.html#a361d79e4b43a6faf2c33c66e96fb8dd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccSign_Async", "a00260.html#ac6e4955f02811739f79666d1dea5b03f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerify_Async", "a00260.html#ad041f0347db3ce41e599a968ced72a8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerifyInt_Async", "a00260.html#a2582af22fe517a527a42de3fe3595a74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp", "a00260.html#a47719ae6806027959c2e51d59bbd2981", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp_SqrMultAws", "a00260.html#a2628b96aaf23071444bc2b9310dcb2b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Init_Async", "a00260.html#afb2d2c841331db604b0e3409ff517c6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_PartialInit_Async", "a00260.html#a1aebd2ee65b10d15236721fd3697d519", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateAad_Async", "a00260.html#a67f9348cc615fa9383d23477902c8ede", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateData_Async", "a00260.html#a001aa082f75b9f2feea47d2f34e58236", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Finalize_Async", "a00260.html#a63bbdef5b8e3df219f2cdbb03a80ab28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Cmac_Async", "a00260.html#aa128a316b5265dfb839609fd6c468cec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_LoadConfig_Async", "a00260.html#a2101f16896f6da0b9e0cc2a3cb0cd79b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_Trim_Async", "a00260.html#adb5b494ddab851901456286d0c954eba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Hmac_Async", "a00260.html#ae6a03f17a67787681eb557b37014ac4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Rfc5869_Async", "a00260.html#ac9dde4cad92957370fac4af8412e9ac0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp800108_Async", "a00260.html#a1fe0a5c0860dd548aa1c76e62677a133", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async", "a00260.html#a7e6058559c8929dd0c63a69d7c2b9f56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async", "a00260.html#abfd15417d84dc1c3d262f750f3b6dda9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyDelete_Async", "a00260.html#a9d2e08d0aad680a5f7f259baacacc139", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvision_Async", "a00260.html#a7105f1cb65632ddb8252eabd2e27b556", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvisionRom_Async", "a00260.html#aab16b8bebfd189668a8d58d39d8431e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImport_Async", "a00260.html#adef31c5b8b970f9217e4993cbe62a20e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImportPuk_Async", "a00260.html#a77ffdedf0d0367947a4302cc1ab81d5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyExport_Async", "a00260.html#a2f288e8b85f2e0158fc8e9d6c753181b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_handleKeyExportError", "a00260.html#a4713ce7f81b87fe2bdb18df25aa31368", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequest_Async", "a00260.html#a0a006434d50abda464d776fcc47fbc08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequestRaw_Async", "a00260.html#a1785e14f6439c41d8ac801eb34026bbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoad_Async", "a00260.html#ae2f3fce063cbdff7adf0727f116a14cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async", "a00260.html#aa2fddae6464f690d8c98c4557780b69e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async", "a00260.html#ab72de9545202511fa021643764a69073", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_Reseed", "a00260.html#acf592cd5848046ccf414922291cd2ebb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_Init_Async", "a00260.html#aae5612633a1c356a268ad72a6dc18b2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandomWord", "a00260.html#abc20bb7c09080e3b2c79cd5d26184f9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandom", "a00260.html#a8e35e636b2bc5fd08d03db7afb630354", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetKeyProperties", "a00260.html#ac0051edd1b5bd9cd70785851f310d693", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_compute", "a00260.html#a60ed8198ee37d097eef5ef5d928a66a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_compare", "a00260.html#a6618ffa024a5904a24e8b7cd7e0a94ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_verify", "a00260.html#a8b7d3890858fa2d6e3cb31b3e3e4a685", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_init", "a00260.html#ad1b0c6655bb72499a217876bbc1631c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_process", "a00260.html#a2bf83b35e98c592953d2534b4bfa33d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_finish", "a00260.html#a1b4741071f1348e067710c6097a6d881", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_selftest", "a00260.html#a0d022db0ea2e7775d343d78f71170ec7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_export_state", "a00260.html#afd95578fe46253b97ba82a632c81df0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHash_import_state", "a00260.html#a4c6a3f8b588157f7af2e04a0855c3578", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Md5", "a00260.html#a114343e185fab2928c5a339197f40981", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Md5", "a00260.html#a232aab207faf1ffae0c416fea7819ee7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Md5", "a00260.html#a9c6984b96629888de1a7495d280694fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha1", "a00260.html#a750ddcf9d659a38dccf42c975f18dec5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha1", "a00260.html#ab47bbd2f627d715f560fd8e40aa15094", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha1", "a00260.html#acb7c7374ffcda4aa264d6d182f9d259a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha224", "a00260.html#a838b79715dec774acfab889effda7bdd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha224", "a00260.html#a9d4186f8b46794673840bf1f7c72771d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha224", "a00260.html#af4346891bdfcdf2e10aa96820da82947", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha256", "a00260.html#a13fdd5dde4398d8ae8fb5e8ebdd0676d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha256", "a00260.html#a71beb22116b206e5abe5c06c2ac787c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha256", "a00260.html#aae532267004751129d1d3caf93d374b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha384", "a00260.html#a3070e5083c950a22b82a99fcfa7fdd8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha384", "a00260.html#a0e46157e0a327548a56cc0eaf802f118", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha384", "a00260.html#a0d9661ec8a74c4adfc65824dee5da75e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha512", "a00260.html#afe443c2cf3aec995fd665e368abf9028", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha512", "a00260.html#a54cd5d038e86269a244c3122a0c7d706", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha512", "a00260.html#aec3d46442f3c07b2207e8cf17dbfdf45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3_shake", "a00260.html#a6d790205559c1438bf97a30f3be0bb4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3_shake", "a00260.html#a64d27e97927632228a38cf50337100bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3_shake", "a00260.html#a88899c5c9ae7aa1efe750b3931eea7a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3", "a00260.html#ae7098028f77013d43383662c9d78bcc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3", "a00260.html#a33cb351daf24425e4273834e396ecf18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3", "a00260.html#adeefcc89c78605fb1f59cc2d400601dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_finishAbsorb", "a00260.html#a6894d72671d8ce9b8f49064824504d94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_squeeze", "a00260.html#add817058cb7f134d6dfda03b8f69c413", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_createShakeAlgorithm", "a00260.html#aedb88501469f192c330bb95ff8dd1657", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_Sha2", "a00260.html#acabf9bc6d158d5a7054cefe4905a1f62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2", "a00260.html#aa4184b4bd41172e31430df0be63af065", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2", "a00260.html#aac87ee9c08fbac9e4640b60048b94352", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_MiyaguchiPreneel", "a00260.html#a0c9e040f76bd5f67fe69730c27c6d73f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_MiyaguchiPreneel", "a00260.html#a8409fb75aa020e47edc1e990af13bc19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_MiyaguchiPreneel", "a00260.html#aec950ef99b0817bcd6d376d7e386f09f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2", "a00260.html#a33a45e27b2065ec00ce616113daceb21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2", "a00260.html#a9274942027de1540c56f572088184b26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2", "a00260.html#a5a116a6f16eda8bc0d825bf9bf5f578b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_dmaProtectionAddressReadback", "a00260.html#a265345816ea529e7f75cec3aa2f1dd6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha256", "a00260.html#a0eb10fad01c83bf1056f18ff83050fae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha384", "a00260.html#acba0700eada7efcc3d2e5d325a531205", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2", "a00260.html#aef423e666691d799250944bdbddce738", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2_direct", "a00260.html#ad5a6931d1f2e91aca2402f8ffbba9a89", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_md5", "a00260.html#a4d2f9d74128e7b394cd8a8bee668a9e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha1", "a00260.html#a28ecc5bad555b33890e39709fd86f99e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha256", "a00260.html#a127a6124103476da07d6b0a6e7aaaa8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha512", "a00260.html#a27bc558af54c080ee2fff9956f0cf1b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_keccak", "a00260.html#a446e1258a9aa0c209137515d0b011b54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha3_Keccak", "a00260.html#a1d09167e450ee61a3c73acc86597a688", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha1", "a00260.html#ae5402516498395e81ea0846e15898516", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha256", "a00260.html#ae52e3382c6f730670e187f90370d7f61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha512", "a00260.html#a86e8cb901222ff8a270a9457417c06e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha", "a00260.html#a92926bd1679756adbce776e483c69d46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha", "a00260.html#a1bbbf6a7c6e2a3a230829cbb9671846d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha", "a00260.html#ac39a74e998c029123fe1298a439a222f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha3", "a00260.html#a993c22c55a8b5fb141ec41b55cd5b870", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha3", "a00260.html#a9ed60ee9c2c31e81c603bc6b3b0d11da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha3", "a00260.html#a9a2e60e076544cf1d511e474fd332b21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXof_compute", "a00260.html#a9a29719adb04939132fb60d47e0429df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXof_init", "a00260.html#a419714217a9a0697383af6aca4f8d5de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXof_process", "a00260.html#a1aafbac7525443429144248f3355f1ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXof_generate", "a00260.html#a337ead0b3fe35fa59e2522319b1fca17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXof_finish", "a00260.html#a7d03ca481b17f4b902fe8fb0420ac0da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_generate_shake", "a00260.html#a011e24d6df3bcfe98f261c5cb8532895", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_init_sha3_shake", "a00260.html#aed0906707df146399c1c3aab373c880a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_process_sha3_shake", "a00260.html#a273ad070d0669ec703b5281ac8158cbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_oneshot_sha3_shake", "a00260.html#af8ff1122ba9d9ae3ddbd327d645bd9cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_finish_shake", "a00260.html#a902aef1ab3868219850bc236daacd774", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_loadCopro", "a00260.html#acc0d42492beecf36a9a69f44b967cc61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_loadMemory", "a00260.html#adf2703b209d40603d4318f464606a8f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_flush", "a00260.html#afcfb04c2a5f414b091de2ecfe82fa69d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_setKeyproperties", "a00260.html#abb707c929513ec447c1cec5295a4f1eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_LoadFuncPtr_t", "a00260.html#a348af25a692b267ac80c56d92dfc048a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_FlushFuncPtr_t", "a00260.html#a17c3b8c7a254c5ce7b4208b3f4b2e3ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_init", "a00260.html#ace6bdfc6a0372f78696d1819cbeae8a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_setProtection", "a00260.html#a1f58f275ea3924fb056bd6669c866d64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement", "a00260.html#a8099054668f06a6df4b04c944aa99917", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_protect", "a00260.html#add13c03a70ec89831b6e64da064651df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_compute", "a00260.html#a3a33e737af9946468ae88921f1597e42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_compare", "a00260.html#a88d3913d7d0bbb2e533c275d6c5b4a88", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_init", "a00260.html#a6c8b477629227edba9020ebf3c3e31a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_process", "a00260.html#ab40c727382346077d65a43ae1587f515", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_finish", "a00260.html#a73465a0ed00f5da63f4edb5d1726a151", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_verify", "a00260.html#ac82c2eb31526acdf881682836296344d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compute", "a00260.html#a741b4d4a4a4f0e97f99cfebb497b9b79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compare", "a00260.html#ad73062980897b7ecde7911cecec2aae8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_init", "a00260.html#a4a2dbf841237a407d03a1e4aff3be748", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_process", "a00260.html#acfd7fb9143fecee5f3e9f4c4d201f968", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_finish", "a00260.html#abf85be23498ec95a8f2655c121ff8e25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_verify", "a00260.html#a9cc9a2d725f3a124d80e8abad33209e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_createGmacMode", "a00260.html#a841a73b266e21d30f3b1704ccc9d4afd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Oneshot", "a00260.html#a7bef3439063251ab0baf7ee482e3e948", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Init", "a00260.html#a5bfcd32457970a419e35f831026f782f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Update", "a00260.html#a389b3837cc3f275f190492c43bd95bb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Finalize", "a00260.html#a7a9afeb4276ee248847314177030413e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Oneshot", "a00260.html#a47858c53f2da64cdc3ea4a88293587a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Init", "a00260.html#a1fed6d61f818982b013dc1b3de17209c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Update", "a00260.html#a7b164bb67e8a2ebf06df540394106ed7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Finalize", "a00260.html#a6e18c43b2bbb3a8f8ac2bca3c3d6decd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Sw", "a00260.html#ac723692e3b2567e0f176c6ec2e4830f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Sw", "a00260.html#a10dbf83e21e5064957ff03107017bd18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Sw", "a00260.html#af0258cff8bfa8e04a4079aa6b212aeef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Sw", "a00260.html#a00d49773ca15d39e49479d1422b4afba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Els", "a00260.html#af20b14d7d0ba9c8fb36c7c03035ace64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Els", "a00260.html#abd6bdf3de874e0effcf7d0768b814ad3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Els", "a00260.html#a3371d5276ced0de014aaf49cbfa2798a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Els", "a00260.html#ab1a0fbc491835a295ccf08ceb31d1aa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_compute", "a00260.html#a4fd04b97d706b67bb4211fb6a870e58b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_init", "a00260.html#af09ef1c921261b7c8ae8e70f98b74c77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_process", "a00260.html#a0123435c90d7c243c6c32b8be9128133", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_finish", "a00260.html#ad633258bd16fa3c60deb984aa35f4f2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_prepareHMACKey", "a00260.html#a21f03c826bef0c905c00c331ce60216d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClHmac_createHmacMode", "a00260.html#ae7fe0dad2fb1d731766e00e9dd51ecb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_InitLocalUptrt", "a00260.html#acb291b7a54b67750014529e53292a7df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_LeadingZeros", "a00260.html#a6b084acb8f88b7fb17a3d7924e8ba3d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ShiftModulus", "a00260.html#a95fd7e88cf5cee584e1f9e6a443b9106", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_NDash", "a00260.html#a4de50c39073fb234caa6c1b543e4b3ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_QDash", "a00260.html#affd9093fc1d299d0137256e2017564bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_QSquared", "a00260.html#a145e7775de815b9bbd5d019e7713bc31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ModInv", "a00260.html#acfe3f470be4f440d12adf13f534ffd0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ModExp_SqrMultL2R", "a00260.html#af40317f30fb927b2b12e69f100c30488", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestInstantiate_Async", "a00260.html#a9798720bbdd77e2afab2e1cbbf454f8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestExtract_Async", "a00260.html#ab58bbe6a56fb88f3058c3e485edeabdc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesEcb_Async", "a00260.html#a01fdf94e0d4be71b8b0fcba856e5cdb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesCtr_Async", "a00260.html#a89edc24d65b36a741fc2766cbff6601f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear", "a00260.html#a7dd848e3cebfe70d7491d9bc42c69018", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy", "a00260.html#abc250c08a77a753d423526b87a71f444", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMemory_set", "a00260.html#aa0d954c0085b4933ebc846a482ef90de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_Initialize", "a00260.html#aa555e0d876290650906caceb6a7e0bd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_Deinitialize", "a00260.html#a78194772ab76e5c6537d8fec967d6140", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_GenerateUPTRT", "a00260.html#a312c9b1a892a8539c2f76b0478518680", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_Calc", "a00260.html#a65c149203de1f07c3a9406c8f4cebe0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcConst", "a00260.html#a4d07cd851c5b9e4292c6d26d92329493", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcFup", "a00260.html#ad00ef5d2ec8edc11572035da3715577e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForFinish", "a00260.html#aefb16decaef6f72c71374efd861309f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForReady", "a00260.html#a469e684b234a1236c5d1b626cfebbc28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_init", "a00260.html#a4d5cdd2baee9deea0efb9bdae7511614", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_allocateCpuBuffer", "a00260.html#af121a96e368cb239f3f96e56577e7fc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_freeAllCpuBuffers", "a00260.html#a5691bcb346624a6174d447e6bf553c71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_setRtf", "a00260.html#abd7b5d38003bbd60bc1752c267077745", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_cleanup", "a00260.html#ae2babe0652d54c5bf92fd8d118774917", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_destroy", "a00260.html#aa4d33507c8e2a9065b5851c9945b3a14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_setSecurityOptions", "a00260.html#ad1fed2f3048e76205c6d39fa2f93ae5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_setRandom", "a00260.html#a802effbd6d4a6059b6ad30b3dbf67e42", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_sha512", "a00260.html#a8e27b3d8e5c13381ea68e2b152b15ef1", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_aead", "a00260.html#a92116a3d39c16596ebb786af6d2bb9c2", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p256", "a00260.html#a76ce16355bd6b6c4b9b859cdbdab27a1", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p384", "a00260.html#a2da943f4401d94440f962eb2ee152dc7", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_hmac", "a00260.html#a95dfafc880cece512001551dd2041e2b", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_eckxh", "a00260.html#a5f711b6f0c9e9f26ff1afa33f305e6e7", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_extract", "a00260.html#a83952a5cf9bce2870256977b3bef00ca", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ctr", "a00260.html#ad7988f09a801e0e055c974b0db3aaf89", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ecb", "a00260.html#a44db6d88d62f4b422a306771b67bcf24", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_ckdf", "a00260.html#aa6be198ec2a96712e60bf1f1300425cc", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest_hkdf", "a00260.html#a51f5a2f1b6df843bb7b416bb230f6d59", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_selftest", "a00260.html#a318d6192b81e0c7cdc0f592d54a38672", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Extract_Async", "a00260.html#a29f69f6137489e09d121213b0315fe10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Expand_Async", "a00260.html#a02dcc2b028a282f6e5bdd40f84d19dee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Sp80056c_Async", "a00260.html#ab8941550409c674c50ab45a91983c4b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_keyProv", "a00260.html#aff2572392cb1624dab512b36b9bedf12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_get_oem_cust_cert_dice_puk", "a00260.html#ab3cb7d1f42110a6e948cd2e15572bb2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_eck_sign", "a00260.html#aaedd6af9a5fae48b2eb98fecab3e390d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_enc_blk", "a00260.html#a07e3bf33b223ce8f2a8a6b0ad7e79aef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_key_gen", "a00260.html#ae2a148c4df7ef6fde5a8358bf7fe4b78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_sb_store_key", "a00260.html#acea0e4932bd1d76e0a4bb36b95640770", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_rts_get_id_clns", "a00260.html#a69cbd953d2a2954d785a09b48375ae0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_gen_oem_master_share", "a00260.html#adafe042f4af644f21dacbe83192c6660", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_set_oem_master_share", "a00260.html#aaccf37f45c9cd40af40e99318e8c8753", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_store_key", "a00260.html#a6c0e9cd6cc31cac0301a391a6295146b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_rfc3394_wrap_manual", "a00260.html#ad10720d5f7592967dc8958b519437ef6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_ssf_insert_cert", "a00260.html#a9f49cb02c538120a133fc39ca5aee8b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384", "a00260.html#a8c41b0334ef435ebf11b0945b724cef4", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_cmac", "a00260.html#aac7a4a4353ba6355e279dcb5e7ceb426", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_key_delete", "a00260.html#a9a1f7d8e975f2a7fab92b5dc0f88601d", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_key_store_export_key", "a00260.html#a76ed75470f8be1d954614de2e768eb64", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_key_store_is_loaded", "a00260.html#ade9567dca14f0cf25873f12834e4b120", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_key_store_init", "a00260.html#aa7539aef06ffc0d8a3c6be30d84b6221", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_key_store_generate_rom_key", "a00260.html#a853bd5ec920e9d6c27b5deb0d4e0734a", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_cmac_authenticate_romapi", "a00260.html#aae07a3a8ccb23464746339aeb48bab43", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_sb3_load_manifest", "a00260.html#a133eddbb75cf2b23511c720bb130a019", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_sb3_load_block", "a00260.html#a2616b251621c36fdbadabfa5df11030d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockVerify", "a00260.html#a80162c6c3efebb02c1c23021f0318178", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDecrypt_Start", "a00260.html#a14914aeb67b783aec46005f68748213f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockEncrypt_Start", "a00260.html#a5c9ea72cd478eefbabed06f6296f615f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockCrypt_Finish", "a00260.html#ae4ed9b7423c6499825b89737455d4787", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDeriveKey", "a00260.html#a167f901c1e3375f6d6ab75afa88780df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestImportPck", "a00260.html#a3c668d9bedb31257fab3bf9262ad6a45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestDeriveKdk", "a00260.html#abe9eace2b47299461d5d63d195dff1c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_DeletePck", "a00260.html#af6feb900a01d1a021bc0a0041d499761", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_Cleanup", "a00260.html#aef8f383143ce7b6b25e5ee1f63583603", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa", "a00260.html#a4a817b3a4eac69941acafd2dc8e0c617", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_romapi", "a00260.html#a3c66e35e53548a0736d1996fff3533ac", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_sb3_img_authenticate_ecdsa", "a00260.html#a164fbcc2af923dd87327709f4ce945af", null ], + [ "MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_internal", "a00260.html#a367f9c0b0a81c98f4e3e381905f05847", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_none", "a00260.html#a4021021adadc2c4a638296c71aa9dee5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_ckdf", "a00260.html#a83287230af7e81c312a635c51da7cdda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveTwoScalars", "a00260.html#a0cb44be16d584b77657664bb1661d4fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble_NIST", "a00260.html#ad8eb1fc2d9384f9739849a8be0a43426", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult_NIST", "a00260.html#acc96df6401c4fa2628d3d051c2180046", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR_NIST", "a00260.html#ab717b9589592ed9faae6f85d237cf064", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd_NIST", "a00260.html#a2ca4ee7a3ad1fe1f472d7a5eadfe13cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_SwitchEndianness_P384", "a00260.html#afa3eafb7c67c49195c09647388199719", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_rts_insert_cert", "a00260.html#ae4d1876567c2f1875228690c397e2da1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_SetRandomStartDelay", "a00260.html#a38a7cd0423a7681ae7a54af360e9c2cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetRandomStartDelay", "a00260.html#aa95c106364db28378d5c1879bde4726e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLock", "a00260.html#aa8aadd44da9b2487fcee2fcf4b54dd6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ReleaseLock", "a00260.html#a939f3e6fb22bef246a36bb844dea4a62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_IsLocked", "a00260.html#ac699622130ac2693f601ae6865361d2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_SetMasterUnlock", "a00260.html#a99e120589d33e921c02215264035a7de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_ConfigureCommandCRC", "a00260.html#a1db562aeb7c0ecb2b4217219019846d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetCommandCRC", "a00260.html#a5575e774758c90d89e6c6fd3137c3f32", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_VerifyVsRefCRC", "a00260.html#a66f41936c56913930e60edbee226591b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_RespGen_Async", "a00260.html#ae85547875e266cada16e58f7a5a34656", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportBigEndianToPkc", "a00260.html#a9ee7e800b0c5563ee233261fc31d8e06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportBigEndianFromPkc", "a00260.html#ae07332dedaa9514f58059e1b39cea511", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify", "a00260.html#abb64b66ce2a9be3ec2ede635564e4afb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_SwitchEndianness", "a00260.html#a8229042cadfdc72da319fdf207ecf516", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR", "a00260.html#a76803691824c6045393c555e9c2cfedd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble", "a00260.html#a45c4d86eda1b2874eb9a3ec07de7adf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd", "a00260.html#adaf24ed72dfb35a0efcede710dadb00d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult", "a00260.html#a8d264f35290bace718cd3f71dd099511", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_RandomizeUPTRT", "a00260.html#ab95b4f1c1b6db3688e770b93d1a4b063", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_ReRandomizeUPTRT", "a00260.html#a28b1ba251f2120233490aa48804cf653", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_SecurePointMult", "a00260.html#a6b20a6c4c0fc8ef067a061e098dafb1a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwVersion", "a00260.html#a666cf78beaa4a2360b6568400276e0a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwState", "a00260.html#ab74997ac3071f05ab2d5a1351f0cf505", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntEnableFlags", "a00260.html#abe38cb1c08e484cf008b17630d153267", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntEnableFlags", "a00260.html#a5c9dc470c382de0499ab81a713d04aaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ResetIntFlags", "a00260.html#a4b41d5e356aca7f81b1a7d4ea39cb247", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntFlags", "a00260.html#ad692b6e33f73e5467dca0ed248ff28e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Configuration", "a00260.html#a1d9f2d6e6ce088efca853ea6bc37fc51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Lock", "a00260.html#abad115618bddf700dae8eb489d161609", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ConfigEval", "a00260.html#ad601821194f6055f36951ba35b58ef77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Enroll", "a00260.html#a0e4dfcb8881f3f9789ec56f8037bb475", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reconstruct", "a00260.html#addddeb14c0d2d30d03c039b8df90865c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_KeyGeneration", "a00260.html#ad694915258bb2da7701b2f8ea36d517b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntFlags", "a00260.html#a67df6552d80aa07bcb3e610543bb8bea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_img_authenticate_ecdsa", "a00260.html#ac279f67acd3d0db2ed2bb43f85d7f562", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_dev_set_wrap_data", "a00260.html#a61c670edf51f3dfb0acc729249b941a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge", "a00260.html#ab448ebb8612142c92c01b3ffb86a44be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_mcux", "a00260.html#a6cc392bbf6db11a6e33d92efd034c99d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_oem", "a00260.html#a17f8d435125005b075800d9660702b07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_TrailingZeros", "a00260.html#ab1caf3469b6f04c54fddcb22f08ebd65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ReduceModEven", "a00260.html#af2a8dc2d205d94ce7c7f50253b7b1577", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_KeyGen", "a00260.html#a8b0b174bf2d2e15b19c85005f8e79ce6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportBigEndianFromPkc", "a00260.html#a34d3ed96621342246fccc6523e7ca9b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_CoreKeyGen", "a00260.html#a7f4ea39324cbdaa93a5a9de297c0d85e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_ResetEventCounter", "a00260.html#aad850df4f62140fd303a451da7660b9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_GetEventCounter", "a00260.html#a041c1a4c35124edfd41795e6aa5ff86f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportBigEndianToPkc", "a00260.html#a376e0cdc3cc3544e6cb0f6847b129db2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Sign", "a00260.html#a0700e9e6f8aa890040b12e46d7fa2dbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointMult", "a00260.html#a11f265ce4bdb9105bde7b175cf6c7254", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_public", "a00260.html#a5389c64b6ae265463961d25c09baae84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_privatePlain", "a00260.html#acb13d37fa73626df9c21fcff9877705d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_verify", "a00260.html#afe66b6d6f56395648807aa3f235cb2f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_noVerify", "a00260.html#a0a7c2eefb62be2a8f722a990e597a783", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_sign", "a00260.html#a180c71cd1adb71c6ba0ebc0d9535cdf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Verify", "a00260.html#ab4c975945b4f2093048023f3988580a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivideOdd", "a00260.html#a488080d11896017a4afd199922d9eecc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssVerify", "a00260.html#a692b7a7550279424a71f1de928e3aa65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_mgf1", "a00260.html#a73f46afb846fd264b178eb5aaf326511", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_privateCRT", "a00260.html#a1ab08b458713684e5c18280829cf4366", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_sign", "a00260.html#a0ef35de05a43977cd967abb30903b769", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_noEncode", "a00260.html#aa1d48fb403ea2185a1166a5b896d7574", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssEncode", "a00260.html#a49fbba418f4216c94c9ef5d171786342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_SetupEnvironment", "a00260.html#ae1628ec25de1f0a95f95e41d9dd2de6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_SetupEnvironment", "a00260.html#af384afb2ef22f85a5492f1c516276c38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_SecureScalarMult_XZMontLadder", "a00260.html#ae50e5c20d393726ba654540c674b6f78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_X", "a00260.html#ad11d4546f59b2cb56b24d91c82ca1a87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeScalar", "a00260.html#ac55a95ea81df5ca4d62a0ea3e08d6d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeCoordinate", "a00260.html#ad1b7a1abdb182dae0f42267ac6c5d957", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_GenerateMultiplicativeBlinding", "a00260.html#a8450799cd8e9cd16e16e4468ef81d297", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLastDmaAddress", "a00260.html#aeaf139e1fa069ef8210bef54747dd9c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_CompareDmaFinalOutputAddress", "a00260.html#a9f57fe059305ab235a1b054a0cb34fdc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyAgreement", "a00260.html#a6aaf0d978261abd1898d98602b8cd1ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyGeneration", "a00260.html#aae493b45f455c97adc82c8ed4ddd0c77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivide", "a00260.html#ac30af4fdccc705042313ebc7a49ed4b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_init", "a00260.html#a7e9cacd6b80c038e511d627fe5cad4af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_reseed", "a00260.html#a7ef1c2264c646560c9640c869ea6b92a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate", "a00260.html#acef11966cdc167dc5e4625be7883976d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_uninit", "a00260.html#a311c5d90aba3b03b4fcc2a65d7ed53c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_selftest", "a00260.html#a506048cbe98f70822ab898e984dd5583", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_checkSecurityStrength", "a00260.html#afe78bd74ab770efa8ca5c2d554811b76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncInit", "a00260.html#a4601dd6c0cb34cf1c952a3b2a2505f8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncGenerate", "a00260.html#aeea416c5e79f21bf8b303414646c1767", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPQDistance", "a00260.html#abce0383fc350e839a4af9267d69dffb4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_ModInv", "a00260.html#a8e67129f5830f1b7ed0f6e1293e4d26d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_MillerRabinTest", "a00260.html#a3124151a6811d120b71434dbcd5ecb0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_ComputeD", "a00260.html#a0daeab74420c7b3fd16db6d3ca80faa7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_VerifyE", "a00260.html#acfa50091a3c66e1e51d9257a7460bcbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_GenerateProbablePrime", "a00260.html#a8594e6dfa94c170226354a7099c1f68c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Crt", "a00260.html#aab8be9f8d2bf73b7459556f6984cfdbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_UpdateRefCRC", "a00260.html#a479de268cbca07786217520ea5cc569f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPrimeCandidate", "a00260.html#a19985c8dc45e1ef747cd2d9139576e25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Plain", "a00260.html#a4c968e2bc6f286a21ff07df47ef2ddb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportLittleEndianToPkc", "a00260.html#a53ef23930b40fb33b230d8e2fc80bb4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportLittleEndianFromPkc", "a00260.html#a2a6275ac86fde089775876b902f10362", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportLittleEndianToPkc", "a00260.html#a65bb028b02764cdbb098934a5b1b242f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportLittleEndianFromPkc", "a00260.html#a17712e28ac81e4bacc9c8a2395ac353c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_SetupEnvironment", "a00260.html#a3bc7c294a3cb60e61eafe2488b947657", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes", "a00260.html#a17530b075755efc41ebd7ed7780e249b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_crypt", "a00260.html#ad3a2a82a4c6abeb3e8529b3a7346f13a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_init", "a00260.html#ac53513c5c4797e9cf6284e0674e8a1ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_process", "a00260.html#a52336818bd48ca5499740c7633233bfe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_finish", "a00260.html#add32d569dd12653c180477c297c2764c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_None", "a00260.html#a4332b076032f415b858ec0b3b0862db9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Random", "a00260.html#a76ad1392fdde52da0ca40c81d6cde53b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Decrypt", "a00260.html#a2984a16b17cfb4d952df956005f32602", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method1", "a00260.html#ab22af8138cba7ab7bdeeac51d6a9b7f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method2", "a00260.html#af67e612db7ab954b2e651b49f7ea8608", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_PKCS7", "a00260.html#ab300227e70ec3ce3b647a482287b17a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_None", "a00260.html#a4b2a16d37a69cc01b5933f7d7f3de209", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Default", "a00260.html#a120552f757a9eb3c4ffd65c129af11f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method1", "a00260.html#a08e35ab8dd35a8b9b6842c0b2721ee72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method2", "a00260.html#af0b0345f76515e2bf33cc5c2ba7e008f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_PKCS7", "a00260.html#a2dce0ba97d1afbfcbda505bc67a8fd10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Stream", "a00260.html#a101222db52b99b4b6e5b4c94f5eae9e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesGcm", "a00260.html#a7c914c410eda35b16c27a4edda52df5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_crypt", "a00260.html#a3e6326e1dc911c2192b8285d858a1384", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_init", "a00260.html#a99417ba0bb027bf5943df1eb4b49cc15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_process", "a00260.html#abb79c0b61ff2a771d64979ac4c42e3e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_process_adata", "a00260.html#aa297a5415ed2603d5e997340de1e281e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_finish", "a00260.html#a5e5030883828a1d16f4a9ba25f178f6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_verify", "a00260.html#a5ae609a8a46a4fdeb50fb33278db4f2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesCcm", "a00260.html#a1edf6f28f42be8d673b563c41600b075", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesCcmEls", "a00260.html#abd2f31c3a358cc79a6af9ff419086054", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesGcmEls", "a00260.html#a9774b58156551f9e020a679ed1822993", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_encrypt", "a00260.html#a9f7a8c9245757dec92d9162ae9cacbd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_decrypt", "a00260.html#a607c2a32fcb851ba83990023cac03c9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_init_encrypt", "a00260.html#ad2037006ce94109deae66a41449b7f5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_init_decrypt", "a00260.html#aa670eaabccc649b6a142899a66da89a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClTrng_getEntropyInput", "a00260.html#aba136d5ef1b92a2cfafd6ae452416041", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_generate", "a00260.html#aaa720148c8efd7066b66b15ce148d5f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_init", "a00260.html#a6c78f6863f98fb052f434a1fd39fceb4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_reseed", "a00260.html#ade2a60201861c26f951794e658d7c25e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_selftest", "a00260.html#a01a8e67ada5061372a372faf5db1bea9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm", "a00260.html#a526376ca09c3a14bb3df726ca5e72f91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm", "a00260.html#a26796a43098d031c8ae9c7dc91279316", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_generatePrHandler", "a00260.html#a1305b3a1b0148c66b8ea2b75af876ece", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm", "a00260.html#a3f8410620300ee13cb4d4244c9e4e2af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PTG3_selftestAlgorithm", "a00260.html#a0d2494b57c282cf65559fa2387d6f081", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateOutput", "a00260.html#a463c9b2fd7d157d4315d7f8cd97b6ade", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_UpdateState", "a00260.html#a65e0669692ee8d098f177edb7a5fc2fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_bcc", "a00260.html#ace776927b5dd3f8f61c63be439532c0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_df", "a00260.html#af9f1a5b7542636e816b599b5011ec189", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_updateEntropyInput", "a00260.html#a94782620c543e480541ea2456f75509e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction", "a00260.html#af1f2b4978ffdd4494b47baf340a27bfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction", "a00260.html#a08f3115d7997788d467dedf2d7e4fa16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createTestFromNormalMode", "a00260.html#a4d87a9635fef74fe6bc9ab59e1ce49e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction", "a00260.html#a49724a0828cbb4ae72935660d7f4e351", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction", "a00260.html#a11096e1b3918ee7ea9e4b9ed01d9de24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_DRBG_AES_Internal_blockcipher", "a00260.html#aa2dcda204f13fa37483fa83f3f1621bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled", "a00260.html#a2b0477fdcdcc90c02da2df6d42a6b7d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction", "a00260.html#aa3cd629553f347e0ed33068db9cb2894", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm", "a00260.html#adf3349c88e2988e2624a2cebf5ebf54a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PTG3", "a00260.html#a8b39773f9b2d0eda1184d80f9f5796a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction", "a00260.html#ae548273bbab95cfbf9077dc4ce89eb87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction", "a00260.html#a35cbcd36228541751573ef3f30baa577", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction", "a00260.html#a286f6e1964885974f2bf3bbf1373df30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction", "a00260.html#aef80c5b4335b02c2a5d9af180a6848e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createPatchMode", "a00260.html#a8623fda3117b10ebd2f547b3fb34d3d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_incV", "a00260.html#a35a6dcac3a481b8d2993c25d4c9f38e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction", "a00260.html#ae1de787a8b2c9dd07ba0db1be09cf765", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClTrng_Init", "a00260.html#a69a882e90f2a643edd8a14a9a88081ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reset", "a00260.html#ab89be83d3dce82f1748513c53cf66e20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_EngineEls", "a00260.html#acc2f6a345da2e973c7eec6f7e0b9d67f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair", "a00260.html#ab1bc9eca80a03d9227cb2b1e40659f92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature", "a00260.html#a074220ac4fb4d80271dfa5e5cd70c65d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature", "a00260.html#a3bdbe2a6f90417954c33716ad286a443", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_encrypt", "a00260.html#a027fd868e48b96db5ede9e4638338062", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Decode_decrypt", "a00260.html#a7d97d5c968854ddef4a5463772e2a2d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_SetupEnvironment", "a00260.html#ab727c5121c1cdb16db5d10c7b172e24a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateCustomKeyType", "a00260.html#ae05257f186b3cac6e8a013fd9a98d22c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateDomainParams", "a00260.html#a203474b371b03d350b1125855cf4c6fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_MAC_ISO9797_1_Method2", "a00260.html#a539760afe6f956430b073b81549d5d14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepEncode", "a00260.html#ad92a02499680aa970ffce73f54c85aca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepDecode", "a00260.html#a8fbc76e423f90ccf5d72f87a5b8d5c3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPrng_init", "a00260.html#aabfb11f2d6584acc70846a2c14897844", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClPrng_generate", "a00260.html#af1d17b75d4d50339184f1ea6c3a299bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_RecodeAndReorderScalar", "a00260.html#ad8c39537e2c18329fa28ed48ec457d3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_FixScalarMult", "a00260.html#a52b26bf8a6371cbce73906ef0a0c03e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult25519", "a00260.html#a2523ccd46d37508adda78ade1c150085", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectComb", "a00260.html#a7882b39a4ef458a4047c784010daeb3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd25519", "a00260.html#ab5d32a81237c6b9d36d6b90c719a37a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd25519", "a00260.html#a859d5473d2b58222be19f8c3854c77ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectML", "a00260.html#a81d4434144cc0e96e60ef490d8bf0897", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_VarScalarMult", "a00260.html#aafdb3aa472346da235dcfaebb72368c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainVarScalarMult", "a00260.html#ae2d43885b0ea69bd47fef0f4a34fec04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PrecPointImportAndValidate", "a00260.html#aa98551a5219fd4ab6b4c7b848149f166", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSb3_Ckdf", "a00260.html#afd682f08fd0bd47c95aa46daa855dc46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_verify", "a00260.html#a2c84f74f1edd3585808a02c90f7007bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_crypt", "a00260.html#a98798e2a22be5930dcc62a666c9e933f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_finish", "a00260.html#a73f48343220b7e2c3de344ac2014831c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process", "a00260.html#a31e845eeb83bf8bb7673608dc10f171b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_init", "a00260.html#ada7135b39373c2120e0165377e22a342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process_adata", "a00260.html#a39eb21f3598569bf21a76f233ef1b4a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateKeyPair", "a00260.html#ad28dc6bb8a9bfa0962b8672566ada0e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_generate_keypair", "a00260.html#a6089e952822854431c59bca84fc2f163", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_GenerateKeyPair", "a00260.html#a99a9ac06a8885b89882877fe28095f4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_Public", "a00260.html#a0e535bd1035f6869ea84ab2895c8d75d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_UtilsAsym_ModularExponentiation", "a00260.html#ad63a4e519574b2b96bfa9e6772fff027", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcInitialize", "a00260.html#a99371b03972572e756b08b44240b9414", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcDeinitialize", "a00260.html#a12a9a74c3742ebc798d78e4d91ab6003", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_BlindedScalarMult", "a00260.html#a91b6f166f14cdd107aa9ce05566b5138", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_BlindedScalarMult", "a00260.html#a99c1faa871e4ef826b301dda7860f7e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PointDecFct_SEC", "a00260.html#ac6126871423de820004e543ae550ef93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_S5xyStub", "a00260.html#a6dc4ccf9019ec3a52533fda9c0b8a834", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_S5xyStub", "a00260.html#aedeef9193fa78bc0ee3e3be29dbd394b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSignature_selftest", "a00260.html#ae90810dbb0f04ffa9ecee16935125165", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSignature_sign", "a00260.html#abc954548cc83964f1f6c548a9cb18517", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSignature_verify", "a00260.html#a0f479f4aa5fddd2913c689d36396fde5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSignature_init", "a00260.html#ae1559b7025113bf76c2e9abcd3ad4ab1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSignature_finish", "a00260.html#a9d6a1f806d94461a88050fe35c66b9f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_selftest", "a00260.html#a59f9b6b272c884a1c8d87df15bf5180c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_SetupEnvironment", "a00260.html#abb1cd8533639990bd5b15e9d416c86c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetVersionAndConfig", "a00260.html#a0b3e638a93e218f0a713e54069bbf815", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetStatus", "a00260.html#aa71c684e98ef4b804b8ca107403f04a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SyncReset", "a00260.html#a40785b841ec9b433e259862c25d01015", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntEnable", "a00260.html#a58259343f494ceedff94972ceeb19182", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetIntEnable", "a00260.html#ae8c458844961e446df94c755174c3369", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ClearIntStatus", "a00260.html#adc2a44869ec84384abd7cd14f8b2a8f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntStatus", "a00260.html#af6d680157d5ef5f4aceda8fb5fa3b825", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_Lock", "a00260.html#a679ed1ef49cc91c4270a66b12837d8d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsLocked", "a00260.html#a7b75510e666d595b8af0c2253ed8480f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsIndexLocked", "a00260.html#a7296b7f7386a20a46ce0e2e36337a565", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_StartEnable", "a00260.html#a1f0c1570ee39f7a4b48440d2f64e4f3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ContinueEnable", "a00260.html#a08e8f70d1693b5355caf4a0c0ab17926", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_LockIndex", "a00260.html#aa120ec6cf27d078b4771174945e3804b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ResetIndex", "a00260.html#ab0d0d891f1ef79798cce9e8b68e4412d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClGlikey_EndOperation", "a00260.html#a20a22755263aca2e730f033c089af3ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_CalcHashModN", "a00260.html#a5b633614d004b9f5d3c477e667ec212b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed25519", "a00260.html#a7b5fc7df992d5de08975a19429b06e01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed448", "a00260.html#a454b78891131ad464e7e94ed095cbda5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_InitPrivKeyInputMode", "a00260.html#ae0b29f87fcc86e09d49a3c2cc302f2fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_setResource", "a00260.html#a7d2732b5c9de9f8e9392b745c5799afe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_configure_job", "a00260.html#a5164fdc0d6a40e2be0e192193a401d9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_request", "a00260.html#af6148cce167b1632335b3b751f56af0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_release", "a00260.html#a85b16d54e77ff772f0cfa1f13ac89753", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_triggerUserCallback", "a00260.html#aa2e0eb5d9413ddb5009fb70424070d4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_init", "a00260.html#a7bf02d65854a0fdf77c68fb68ee70024", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_handle_interrupt", "a00260.html#ab6911debe705ad9be0d213ae4223c3d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_request", "a00260.html#a63aade8373fdaff9bc7eaa3759e3c696", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_release", "a00260.html#a63cf0224cc4066bcbbebf45c17eef86a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClTrng_checkConfig", "a00260.html#a0fad040974acfd091f8804306de61390", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_linkKeyPair", "a00260.html#af22bf8dc11d03a2f3222dc80e4dad48b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithmeticOperation", "a00260.html#aad62d20920e2d652bed625f8a0d03810", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointAdd", "a00260.html#a925a83f65f37e52b3890627af33537a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_RemoveBlinding", "a00260.html#aa0b969d02f50e04a3753f3e291dc952c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_ScalarMult", "a00260.html#ad049151a0a9e3576bc49119fa6c0b663", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement_selftest", "a00260.html#a21e44b3115cc2915c151bbc2f74afeb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDH_KeyAgreement", "a00260.html#a35d3f5f22b451ac77761998e9df2dece", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_encrypt", "a00260.html#abd966aa91469c9b78bb0dff871152eb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_decrypt", "a00260.html#a4c7b8855a38d96ffe57c999fdeef3242", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_encrypt", "a00260.html#a05c0cef2a08bdff756f5c9ef75a490bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_decrypt", "a00260.html#a0f541c8c03b600235a304ee36face953", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi", "a00260.html#adb5fd182e0db8fe92784229113f53eb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi", "a00260.html#a31a922f933fd5780a90d0199215d3505", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_encrypt_Sgi", "a00260.html#a90754258b3bba88aa6e0c9d753f61cd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_decrypt_Sgi", "a00260.html#a4daa82849cd4f64df4394725ebca90ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi", "a00260.html#a0bacfc834f9ffa4dc00e72ea98b3151f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finish_Sgi", "a00260.html#a86c992abd2c7d268c8fbb5a8d810533c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_selftest_VerifyArrays", "a00260.html#ad92900689bb5629b4a283b4688fb3f4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveScalar", "a00260.html#a11821bdafca63f77cd7b44be8e59b266", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PrivateKeyValidation", "a00260.html#abcb6c4fe2b1815de2666d87ad285250b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PublicKeyValidation", "a00260.html#a9dbe89f976288951924b2dfc7cdf4cbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateHashPrefix", "a00260.html#ac9bca4e0a63fe4916b3a30a0d53095e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateProtocolDescriptor", "a00260.html#aff0a41b435afedf0ae617ad3c4bc0741", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignatureModeDescriptor", "a00260.html#a1a09ebf21d57c6c10a8a5ec20f4bc2ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_PreHashMessage", "a00260.html#aa9e8cf7b3b2cfcf39906071aaf009f06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair_Core", "a00260.html#aa1ceabe489ce1a9b52c26ead1a14089e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_Core", "a00260.html#a4c78f220e914436d3295f6dcbab15343", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_Core", "a00260.html#a8f753db8fb674f40bbaaa176ef3fc406", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_GenerateSignature", "a00260.html#a3c8627a0cc37c015a41ed15ea0dd4f84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_VerifySignature", "a00260.html#accf2ce517a32630d67b7114597a8f024", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed", "a00260.html#a5aeb8b1418eb860f01d10092f21f608e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointSub", "a00260.html#aafcf4e3033beee0469a462b73a6e30c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation", "a00260.html#a5bfb2890b4b1d4ff3d9263064f3fada0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_108", "a00260.html#a4ec674fe4a02079dc7de268719954d09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_108", "a00260.html#ab01e75f0771e70718330896cdf1b6e7e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ISOIEC_18033_2", "a00260.html#afd753cdd5da7ec64836f8f6a711fda13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ISOIEC_18033_2", "a00260.html#a27add60580d69e2d01587753ee054c2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_56C", "a00260.html#a429213fc4d19531b360fbf0a4f1c87f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_OneStep", "a00260.html#af77fb1bfe1326b54ca64a685843f25d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_TwoStep", "a00260.html#a5934a45e22d61a5422bf450b6b3e76af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ANSI_X9_63", "a00260.html#ae07712a943569a8076b995bde76a7372", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ANSI_X9_63", "a00260.html#ae750da5622b46f06755e0ac680f5fbff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_HKDF", "a00260.html#a736f998538c5fef037d57a12f7724497", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_HKDF", "a00260.html#ad0d802794eb2bda421f7b1ec2b49cbc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_Randombytes", "a00260.html#a474afd177ac6a2673f80a27eaf834b1b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_XOF_Hash", "a00260.html#a08e142fd42a533aa5fec40c251193627", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Init_And_Absorb", "a00260.html#a500e168b78f48894758b5eb5b92951ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Absorb", "a00260.html#a911c3a800b714ea8964399ab67e25487", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Squeeze", "a00260.html#ae033ee89fe6f349e3d6eab12b92cf1a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair", "a00260.html#ab323c7023d15467546b87fb9342f4473", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Sign", "a00260.html#a15aae32a09b796b6043ce394cd93409f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Verify", "a00260.html#a5f33b13f392a9ac73ab851b4c592cfa9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_Verify_checkInputs", "a00260.html#a60cef52639b94e721542e46dac4c4b26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_computeMu", "a00260.html#a3cab0e517ef67190829a03935e2aaba5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_performPolynomialArithmetic", "a00260.html#a18cc03ad6d8c9c09c69df127942829c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed", "a00260.html#a09f5af6f26acc92e35402e13929260aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcInitialize", "a00260.html#a169c7e879b876d863657b5fb57bb0d71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcDeinitialize", "a00260.html#a38add2ff7e10ab1bbb2d33155fbf1636", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_backup", "a00260.html#a6dd38ae1a9f3af2b3e5882e92b0e5126", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClResource_restore", "a00260.html#a40656fb9db8425c50b63fadceb6a3ee2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_resume", "a00260.html#a88d15588a141641620b87f992e3ac62b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClMac_selftest", "a00260.html#ac4230222e08dc2c1a56c358d50e8a2f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClAead_selftest", "a00260.html#a3b30fd753efc850faea807cce97776d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC16", "a00260.html#af0c3d5f73516c0a328755f1008b744f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC32", "a00260.html#a2a01471d61a43fcb831142b435eed56c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_verifyContextCrc", "a00260.html#ac4042f8ab2cd072b31d10f57e608ba84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipher_computeContextCrc", "a00260.html#a9b1d48a4790c26307ca3a1b4b203a45c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC32", "a00260.html#ae709feed5238b8b64800a2b5b6c1ce51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC16", "a00260.html#a1751ce8714bb8bd35fd8cd78df4cb7a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKem_encapsulate", "a00260.html#a8f7e2db94337b6b1e0e6d6f0689c59f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKem_decapsulate", "a00260.html#a23048db516abda52f9b7d4697ef12d7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClKyber_KeyGen", "a00260.html#a7898889e83554cc4df4c060013c83abd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi_nonBlocking", "a00260.html#ae8e839754079c71d99bc80cb77c082cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi_nonBlocking", "a00260.html#ac063688cb3d83bf6c064cecc9f1690df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_job_setWa", "a00260.html#a840601f5692e37506ac32a95c6865268", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClSession_job_getWa", "a00260.html#a2341facb73619021f180ba498c73f2a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi_nonBlocking", "a00260.html#a8ab9c97aecda20f9c6681f5d88ab8bb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Multipart", "a00260.html#a813ae168f0eab8f03d9b4458c550ea4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Oneshot", "a00260.html#ab37730e2eb9c07f9e0d49a686b826142", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClLtc_BackupStatus", "a00260.html#ae0fb73b8e3b221aafb64a785dedd3b29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClLtc_RestoreStatus", "a00260.html#a89abe26987de3ac12e8c28c29b81bdf9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_180", "a00260.html#adb148d5b02402ddcf6ef323332b35268", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_181", "a00260.html#a32e4e05d724a2686b882f0045146e5be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_182", "a00260.html#a1651b2a5cd6c0e928384ccf8b2dab7d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_183", "a00260.html#a2d5d2c00bd1eabaea3330e278c52f93a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_184", "a00260.html#aa3f5668c1423388645725bbd60fee1fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_185", "a00260.html#a056dc2a557d2c36458aee10e296a60c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_186", "a00260.html#a8fbffd89538a2ca38a6b94f8bf9ffda2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_187", "a00260.html#a3a7cf326a1bec120711710e74fe02fdf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_188", "a00260.html#ac6ae0824a54e4925e48166d91c9da0ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_189", "a00260.html#aed1adaf48e6f24d625a5ae80f42f5f20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_190", "a00260.html#a17b122f94591f58776af105c1444fea6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_191", "a00260.html#a895c60ad347726a6acceba721a88b852", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_192", "a00260.html#a4742f16672de8fd741bbba5986c4af3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_193", "a00260.html#a41f65491dfa8ffbd0508ebaff0680725", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_194", "a00260.html#aaafe68a2e798ee1ad4d035543683fc02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_195", "a00260.html#a2148e65b0fabb89c6d0531ad7182ab59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_196", "a00260.html#ac25af75a6a21c152e916b421829e797a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_197", "a00260.html#abfa74d584655a5a22885ceccb09fac60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_198", "a00260.html#a086eb54dc02513b8d2cfbeab775e7bd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_199", "a00260.html#a32bf84509a7050dc0d6e7e542fd52a23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_200", "a00260.html#a091ce66c8c92fa6dd1676f482a4cee63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_201", "a00260.html#a57e960d0edcca1bdcc7151611f9f245a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_202", "a00260.html#acf66a62a7ad372c43cc39e441b50c268", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_203", "a00260.html#a02017b2548c950a48c155ed310bb38eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_204", "a00260.html#a50ec67117b3c498a94bad701adebcd49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_205", "a00260.html#a24270de2bf18b6595467c5cf78a6853a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_206", "a00260.html#a9f4c78057e539920e7ea81c3294032c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_207", "a00260.html#a591f6997a901a7387852a35abaf8415f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_208", "a00260.html#a58cbb97a55fe4655c8b4fce600134a2b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_209", "a00260.html#a5518b8a7505cd4f521cbe84851574e2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_210", "a00260.html#aebb0c1db8235aa5a3d0c327f1b61161d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_211", "a00260.html#abf8def46efcc719c549f3253d9fff406", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_212", "a00260.html#a2fc0bd2ed3d579f1630b5410e26c3037", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_213", "a00260.html#af0961568548816ea79ac7763c2dec244", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_214", "a00260.html#ad2a7af33d1d958954e386968df10589c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_215", "a00260.html#a5efdc77f8f773f43cf685ddcaaf96f82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_216", "a00260.html#acaf4feb2dc64f24e1e0bd57ef40bec5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_217", "a00260.html#ac0b4354c685e15584ac8d949c1fe276c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_218", "a00260.html#a5b7c4dba5b4187f96a38be309bf2413e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_219", "a00260.html#ad08fd44b18fd5c45b8d195c9a7e5c0cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_220", "a00260.html#a7fc6c833fad0b5824eef147fd7fd49d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_221", "a00260.html#a2c814e145f078fc7828067925017d168", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_222", "a00260.html#ac06872a94418ccbe76fc14f938588ccf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_223", "a00260.html#af6b0aebd03d9736aa1a1e28856ccd9cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_224", "a00260.html#a994c1380f3f9c3f40223b72cca813b67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_225", "a00260.html#aae467fd03893a0e80345b8280edc30f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_226", "a00260.html#a09c6b9785cc849b502d1fef9cb2cc657", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_227", "a00260.html#a11530589a7e9bfd6ebe54a041d934dd4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_228", "a00260.html#a8ba7117d79c6ef3afd2b89faf8c24887", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_229", "a00260.html#aee8335f6806568f5c4ec27c34e4e739b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_230", "a00260.html#a72561ca1df509f781f60ef77c43df005", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_231", "a00260.html#ae51060f231b3d4f1ebbc1caf366f4055", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_232", "a00260.html#a554fea763de009f8f4fff9b37326cb9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_233", "a00260.html#aa398973ef6b58017675b52ccf012df9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_234", "a00260.html#a4d4c50a2f9c182b917d30a0ecf80c31f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_235", "a00260.html#a09e9f51882f6d4284b0ac46223caea46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_236", "a00260.html#a63c6b1f5b07ccf70ca513c7a521258f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_237", "a00260.html#a4d66db35a883e54e9dcd0c38026c10ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_238", "a00260.html#adc0ad46f7212aa80ed3dcfe86ee48e22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_239", "a00260.html#af28913680f79a1691b19b5d5b50183f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_240", "a00260.html#ad4d9602d4427fe129a5f2ababe2c1d2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_241", "a00260.html#a999cbc6059cb805365fb994b0bcb6941", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_242", "a00260.html#a0c06d654f0858d16c671657768abaf44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_243", "a00260.html#a9f472b4f6df2134bd55bb3db2a896a1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_244", "a00260.html#a48dfb0fc0a6c3607edeb8fdc464969db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_245", "a00260.html#aab501654c978dd7a460bfe1eb95b620d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_246", "a00260.html#a0be0a4c5b160dece98a174887786c411", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_247", "a00260.html#a399032572a884e358c46c5aa917df6e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_248", "a00260.html#a7ed51d236fb012e87146c0e59b49a8b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_249", "a00260.html#a9c700e9483b0977252606e26a425b860", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_250", "a00260.html#ae1644a0bff0e8bf26e726bee638ab700", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_251", "a00260.html#a5abd3494ca8e955ee10731ddb8b14686", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_252", "a00260.html#a2b60cf7ef2a4e542f4a32ac1a3b5e74d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_253", "a00260.html#a2ed622ef416e3512cc88898dcd70c2f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_254", "a00260.html#a4bdfe03a448541ae330e41715c04b659", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_255", "a00260.html#af8f8cf4ecdba5547b24f34876b52487d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_256", "a00260.html#a6fb05cc38cbea940ef1f61a868992da7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_257", "a00260.html#ab7134b60935c4f21e9ac4dd35195830f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_258", "a00260.html#a2fcd6b9719944f7ab3e731a2a9f2db13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_259", "a00260.html#a7e08019cdf086ccafd0b97f2ca9ef4b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_260", "a00260.html#ae74412e95127168fccd23a9e2447271a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_261", "a00260.html#a067d19422e5ebdc5b81914d54b899289", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_262", "a00260.html#aa909b80381c91e55595e3ecf7fc49b76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_263", "a00260.html#a6975b22bc693337b290b6ab042ac23f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_264", "a00260.html#adbd5a5b7cfdd3cfeee94f4e4fa9c4367", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_265", "a00260.html#af56942916fdc3c5dc2d589133aebfdff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_266", "a00260.html#a032d47dc34e9f34b80320928a41b0d79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_267", "a00260.html#a42717db3c28fbe5894cfdbb6e0c150bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_268", "a00260.html#afdd487303db44eb950bde475023a1181", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_269", "a00260.html#a5211a1472e728426a9fc5c60db32d81e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_270", "a00260.html#ab6ea6ad133cfdeda49ffaa3464224e70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_271", "a00260.html#aff6d7300a28ffcdb004ba08ab9e78015", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_272", "a00260.html#a22ac32a3aa781ec8d8b3593e02225ebe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_273", "a00260.html#aa77cc17457699b047db83967465dfcdd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_274", "a00260.html#ab1fa3ce3b30f8b0ec365be2399b8358d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_275", "a00260.html#a4801713983dc20fb9cbf0653c9e23956", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_276", "a00260.html#af1cd5091f030b35b21538f5f954498be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_277", "a00260.html#addf0c54af14adb821abca253e7cc974a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_278", "a00260.html#addd5273c6371810a5abc75cc7f2d3255", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_279", "a00260.html#a635bb3dd57cfb78c617ec69597828ba1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_280", "a00260.html#adbe909dc38b59235a88d37a9d0cb2487", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_281", "a00260.html#a61dd3c9b6d67ec049565dd9e320baa34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_282", "a00260.html#abf522f1c6c68ee72362b729af5739af0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_283", "a00260.html#ad198f442a3458a124051f45267b39ad4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_284", "a00260.html#a88f89461c8655a32e3aa94474b98497a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_285", "a00260.html#a640a2d65c4e7d7601b3dc7d98e0941ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_286", "a00260.html#acfee7cd2f31ae84fe304357c4675b23c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_287", "a00260.html#a118c3d81bdb58b28e99bbe8e82b54c3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_288", "a00260.html#aba5a6dbd3ebd20df1749a76e4b2ca69b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_289", "a00260.html#ac3ee964c82d1b770142d45c20367585e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_290", "a00260.html#aaa98f2721468413312b32e97d17c9d35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_291", "a00260.html#a4ae81b4cd1d59aaee59fcd005c8f226f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_292", "a00260.html#af15fdb2ff6edde0c2dcc5511b38d4d7e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_293", "a00260.html#a820232607ab011ed885cc592e86e8995", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_294", "a00260.html#a0358bdcf27e2269e6d03dc822a8f80eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_295", "a00260.html#ad78d58be6d540427b34a115d69219798", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_296", "a00260.html#aa2a1c4b323410bb214bc9a2018159ada", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_297", "a00260.html#a06c3cdb18307fdf210bcde0cc8bdb088", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_298", "a00260.html#a334460b5e99906d32f54956961036593", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_299", "a00260.html#a0da54dbdc4e7cb77c1a973d57742742d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_300", "a00260.html#a6d725b02a8f20b776dfaefc84b09c2d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_301", "a00260.html#a7a01ee990d43a231f2618803c76ca954", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_302", "a00260.html#acb79c0c018a64bfeb06bab1c2b30a842", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_303", "a00260.html#ae431c9b6810b8e4355e34c08468663e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_304", "a00260.html#a4fa61a67ca2cbe7dad58ec0ce8cacb44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_305", "a00260.html#af73a5a621cc048ea8204f76fa747228c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_306", "a00260.html#a06637fd42259ddd31f151ac78ff8734d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_307", "a00260.html#adf595807f7d88cd861fa13693a6671b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_308", "a00260.html#a869e93c2982c65e1a58ed5e78c1701e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_309", "a00260.html#aa8d4101f65f46236f66654a7bb0fc0ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_310", "a00260.html#af1784db7f25b9fd94ad2edbafe9a3380", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_311", "a00260.html#a3d605e265369e74ae7eace769f5d9d2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_312", "a00260.html#a30f4ad58101db513e1d00b85cdd8c96a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_313", "a00260.html#a7c3e6e956b20608efa90e72276529910", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_314", "a00260.html#ace33ea1ab49fef307320415cd9cefdb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_315", "a00260.html#a0e81972ce1ba9f70965cebdffa1ff5ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_316", "a00260.html#ab3cb3266da1cafb93458b9bd05802653", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_317", "a00260.html#ad87d37a151c631c23990eb596670e13e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_318", "a00260.html#a1cbe639eb896474b716a3607a31ab9d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_319", "a00260.html#a7264ea53767be9420867f72753396e1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_320", "a00260.html#aa080708636c3e486faad24b7564cb1a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_321", "a00260.html#af8fb8dec368f81cb18bd3e6ffbd5e6db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_322", "a00260.html#a791d9df1939f506e7d27ecd9cd276a57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_323", "a00260.html#a189fc615d8f4658e8a2f542c0643de8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_324", "a00260.html#a7ba8c48dea70e5e9196c67e9bbf4460d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_325", "a00260.html#a68d5eca8aeb46166851d8733f82948e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_326", "a00260.html#a0e57cf24f132aefe82159706e3122170", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_327", "a00260.html#afeb387207b83ca6acdc838cfe132f043", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_328", "a00260.html#a86994991f573442f86e9fcdf926a3b91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_329", "a00260.html#a87f1cb11bbe3f3e4ef48ec752f863381", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_330", "a00260.html#a1e4447360bd1f09cdcd77738bf2ebbeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_331", "a00260.html#af8392597fbc248b3b1669ad4bbbaaa3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_332", "a00260.html#abccee0939e965476addac450209b1ffd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_333", "a00260.html#ad69f2a3a9fa73c1d175d6d818e05a178", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_334", "a00260.html#a792f4e6a68a3bc1cc51b293454977ca8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_335", "a00260.html#ad9c1e4fd5ad52f979ff1581ea5889c15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_336", "a00260.html#a123e70f603696a0a5f4df184a7213739", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_337", "a00260.html#a8c3f2669d06ba0e779894b2eb572ad64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_338", "a00260.html#a16487e7e4992841a1a061dedce063c26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_339", "a00260.html#a25b60d0aa06ff4830ca9b4526c16cdc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_340", "a00260.html#adedb766ba4a185965cb71ce83a648438", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_341", "a00260.html#a65dcbccf50a137252de27f798352eddc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_342", "a00260.html#ac2a7031d79c3c53522eac0ed7101c257", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_343", "a00260.html#a3b4eec9072202323546167b4e21334ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_344", "a00260.html#a3d7ee9d3c24ef5c0d039187526af52fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_345", "a00260.html#a1f9948cd7cc3dd24a1455df2fcf4f755", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_346", "a00260.html#aacf2aeaa43031d067cea371cede0bd49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_347", "a00260.html#a1ab0eeac285a2301948650009ac1dab6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_348", "a00260.html#a0aba2aa3a350c77e7cb0ab1922ea05ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_349", "a00260.html#a0da935db217ed43659894f9ecd6af4b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_350", "a00260.html#a4310553b80087facf37f7527c59030d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_351", "a00260.html#af36827c2271e52987103149bf2740ebe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_352", "a00260.html#ac332d1d92eaa83a9ec307e325152d8ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_353", "a00260.html#a0b5edf962311ebd5fa60c3f084e63dd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_354", "a00260.html#a3d061e79f0f4907c25832a63529515f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_355", "a00260.html#a1cca29f4c057e94246b6a523c480f23f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_356", "a00260.html#a4112d5ce9f5091ba3a75f4adfdb63502", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_357", "a00260.html#abd13ecc2ed68fdfa2743a6d36e41c54e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_358", "a00260.html#a56addf6c71d37cbb20119f244683913b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_359", "a00260.html#a381d9bb1f68a92a60b87561089717317", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_360", "a00260.html#ad68ed862fc98420c138892851f2977eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_361", "a00260.html#ac62543b12f711e9ea1f84f86d1f504d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_362", "a00260.html#a16702ed16824022cb1ddc6a01ad5753d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_363", "a00260.html#a013f92e56b3904104f4834b4357f81ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_364", "a00260.html#ab06700c210acfcad909b874ba6229754", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_365", "a00260.html#ab2d0e101dc0295614f1d72bd7d004097", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_366", "a00260.html#a73a4ed9559c8b43a5bc20adc8a894664", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_367", "a00260.html#afb43ccfcf7f19333eeb02e974eb898c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_368", "a00260.html#a520c80c8c475ca9873fba586f98b0f55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_369", "a00260.html#a283c3705fc83e4d9593e33c61488d63d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_370", "a00260.html#a8799e709792ede7759bbf0b7ea677fc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_371", "a00260.html#a916145c40531f70d3f8194b29ba8fb47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_372", "a00260.html#a353bb79d175a28f8f7895d0dbebf133f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_373", "a00260.html#a8cd23ada032432340fba84e5ad43c35f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_374", "a00260.html#a556ce63fce2414df72ae1a50c94f28d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_375", "a00260.html#ac875b683642f6cdb894900e98c50d43c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_376", "a00260.html#a79381eb81b6ec6fa0e51c668471a6359", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_377", "a00260.html#af5cc24a180cf99b2233aff0c78d580ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_378", "a00260.html#ac5728fffa820d85bb951aca849565ca3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_379", "a00260.html#ab0a6cf3b2c80451cc523b2ea359ce449", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_380", "a00260.html#a2cd6ef3a0bcbe7773d57ff280d05c5d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_381", "a00260.html#a04883fa7a501c66564bad7fa4e56b8b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_382", "a00260.html#aa04ffbe270cf340629c76d95d79fd04c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_383", "a00260.html#ae981fc12d58ed936418b023cdd58b464", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_384", "a00260.html#ad65d82295b036caa04de72f44f24ff7e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_385", "a00260.html#a67a7d588e444ecf1b014a2698cefb2b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_386", "a00260.html#ab7b02c6e7ea1c43a6edc3861d3ca0427", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_387", "a00260.html#a201093742407a46b06bb35ea858e2ffc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_388", "a00260.html#a79f6cafe2e9935909619c363a6c9b0ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_389", "a00260.html#abcf07089435af0c8c5bc00826cd1448a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_390", "a00260.html#afea27593ff6fbc7d2a8b6f91290d7ad8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_391", "a00260.html#afb7314239500c90e89bf18fbb98eb10a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_392", "a00260.html#a4e713108551f08b2e6db57deb49f2751", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_393", "a00260.html#a573a2f58a29e0bac186da709d73ed315", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_394", "a00260.html#ae164c5ed21b2d8d50c24ca303d985831", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_395", "a00260.html#afd377de25e314592abed0822bb1febaf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_396", "a00260.html#ae205eae0c8c3be24e2515dd701a7f7f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_397", "a00260.html#a165a7580a8c492f890d7ef83948d5b34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_398", "a00260.html#acad7e0e2a12694f04d90d6128eb3919f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_399", "a00260.html#a1283363cfddbd6a00d0572e9118e6633", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_400", "a00260.html#a8bd7c0420fcfefa61fdd40af78d3f3d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_401", "a00260.html#a9debfb443f35f225c096da4d59de143a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_402", "a00260.html#a6964cdf38d307b7d18af54c9425c1af8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_403", "a00260.html#a4ea4787c0ec82c9ef7ec7709ab083f97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_404", "a00260.html#a3ce4c207864a191c9b68270c36521f38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_405", "a00260.html#acb51409b2f20d7c9ebd2de54e2f769dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_406", "a00260.html#a3e0c852e38463a9ee8f40268b075c716", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_407", "a00260.html#aa1d4393d4aafafec3ad85cddc65056ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_408", "a00260.html#a7f636cb8a5ea8ee9ba63a1954e95eeb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_409", "a00260.html#a8add882bd8e599c901baadbe7a722485", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_410", "a00260.html#a44ecafc4bd3bee5998bdd6e7f64012d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_411", "a00260.html#a9f6d41fccc0b259c62cc56fe43e75cd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_412", "a00260.html#a2603d5277da38b38cdeba6101752b31e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_413", "a00260.html#a0d7103081264796a931d1c28cb1af7a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_414", "a00260.html#a82ad306e47433c5d78f15c48c5512af3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_415", "a00260.html#a0ca7b605582c81e6444184e8c9d65071", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_416", "a00260.html#a38f7763eb9a87ed5080dbde106594d4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_417", "a00260.html#a385119ecb9f5ff3bdd791cfac77d99db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_418", "a00260.html#a917b7b496d1f005bd35036bd9d6792de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_419", "a00260.html#a580777876e98cc4ac1bfe12e990bfb16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_420", "a00260.html#a2c8b4f6dd560c8967969a54bbef48683", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_421", "a00260.html#aed1bfd068cba9339e82e04852d0121f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_422", "a00260.html#ad3852d3c6f76c9e4be2709c73b052e7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_423", "a00260.html#a7b956d701049c2bb2ff69f6ac0fd0faf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_424", "a00260.html#a3c212fde6c3ab1d2e191109865b234c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_425", "a00260.html#a786db9f1e224ff7b043fc11c2245f4c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_426", "a00260.html#a287efa85fe5514db7b12b42c3739ed65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_427", "a00260.html#af0da5b9f4e6ada77136c08e5b3d923d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_428", "a00260.html#a5bb468e6622b4b15ef5bb71e7e565286", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_429", "a00260.html#abb294d502460c88d86e8988a71e374d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_430", "a00260.html#af4d0162729a2e1aee851093976e87d8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_431", "a00260.html#ac2a54e922bde1314728c3cf5d29025c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_432", "a00260.html#a50afa077cb720add21339e226c6f77bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_433", "a00260.html#ac3a09232b2e0f779244645f0db4d83b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_434", "a00260.html#afe064bdc3e068d298cf1d397e446d487", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_435", "a00260.html#ac392e96fa82e6e9ddcb33e8eec407cc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_436", "a00260.html#a8c95fde273e0dae2cbe61d0124a85a2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_437", "a00260.html#a84b5130376406c645537261a2c4578c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_438", "a00260.html#a346626ede543d815f395768751902ec4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_439", "a00260.html#a12a891ec3018fe3e54529bcb49d476f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_440", "a00260.html#a8ff68f31990c4acd576fe1765cd786a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_441", "a00260.html#a64346ea433eec2106bfbe5556ce57a6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_442", "a00260.html#a36589cded98caeabf9fb3a921297e94d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_443", "a00260.html#a4260ca6a3b1f3c069927f08f8bab6ef1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_444", "a00260.html#a095a55663e4ff4553d4f09a57761132d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_445", "a00260.html#a27b930a39da8496476b6c91fd8b58b58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_446", "a00260.html#a5c2e6120b1481823364c446e44b0a029", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_447", "a00260.html#a39dc45eb25c05b24980b31af1a799dd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_448", "a00260.html#a117955552d3787651e94bb532f0c031e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_449", "a00260.html#ac89d8fa31a5e03e6f3728d14c5efce57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_450", "a00260.html#af5e66fc7aeb08b99f853d0d1016f7db5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_451", "a00260.html#ae8a1a6e94bc209bed9e15c0ae36e2153", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_452", "a00260.html#ad1aed256c60ee64b92702e3902767bd2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_453", "a00260.html#abcd05419451d9054846babefc7a9afc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_454", "a00260.html#a253940ce259f47e3e0307bde5d0e9021", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_455", "a00260.html#ab1abecf4f1c3a71458113305bf1b5dea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_456", "a00260.html#a513001a89231bf25a2973a652cca4d91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_457", "a00260.html#a747717ac694efa42bef1c62a245c5192", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_458", "a00260.html#a7f42a821ce716f1adb8e90099c274913", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_459", "a00260.html#a0c3fd1fa1f26473859880500374cc98c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_460", "a00260.html#a655829e47fb9df3a69aacf28c90c1f9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_461", "a00260.html#a58dbdc70203ac2ca8791a380c8a83387", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_462", "a00260.html#a44903bad30d4f3e1dd296b657ae0e87e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_463", "a00260.html#a2b77480d9a710e62df7c18f98c491152", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_464", "a00260.html#adbe59a90d2ebad62a63bb573dd8f7d12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_465", "a00260.html#abb3692b9ba0de3c9c64a48b15a8e2cc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_466", "a00260.html#adfc1cf3165631e3a5b06867100085624", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_467", "a00260.html#a9f38277c8b7da88267d5dc46edd63b5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_468", "a00260.html#ac4f704b1fdb0015b8ea6a7ded2a189bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_469", "a00260.html#a001b524077d57d7a243546840aea5e07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_470", "a00260.html#a2c84eb9b6c2e457b4e1b0913c23b74a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_471", "a00260.html#ad9b627bf7ca5419ba255681e3c4cfb9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_472", "a00260.html#a378efffb57fc093f40af9a63e220df0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_473", "a00260.html#ae7f6e5acda4979bcbd654e9416aeb3e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_474", "a00260.html#a3e23a6e8d7a73f680dabef4b0cedbe99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_475", "a00260.html#afe90a0c02fca1426c0fbd99c960f6421", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_476", "a00260.html#a80953707926b4e79d64e6b9b414d19b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_477", "a00260.html#a12a916306cd60154860f422467d3c227", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_478", "a00260.html#a2a2467e88ba6fb02d3ac4302c18bf8dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_479", "a00260.html#ae6128b2d80861fe2f48756c5fd4e3064", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_480", "a00260.html#a61691280066963b6b7180254831c3591", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_481", "a00260.html#adbb1a8acd69c968a2235363b29e02882", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_482", "a00260.html#aacd2d578c0496833c7808476a0487697", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_483", "a00260.html#a6a815d76a44e9031e068c2d93e880e9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_484", "a00260.html#a446694bfe1c3efbf24072f97f642abbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_485", "a00260.html#aa5702c19243964e35ffc309a5a4babf7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_486", "a00260.html#a951b5e9697fcdfea69131aaa1a9e8c67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_487", "a00260.html#ae109827441124aa25c0f1eba8feca053", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_488", "a00260.html#af58a2119f1a6fc4e01bdd9cc517f5715", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_489", "a00260.html#ab82805fef2f301d6b25c498d55adbca0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_490", "a00260.html#a4b0f4bece7f22db317d2b73c592543d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_491", "a00260.html#a1cdd8d1adb648b25e0823602a4f7cdde", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_492", "a00260.html#ad40cf0ee6b1f7855261c8fd4a46ee248", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_493", "a00260.html#a1b461dd2d408625e47f30cad2dc58d1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_494", "a00260.html#a7424d2809c0bb4a97fd88ca152c14436", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_495", "a00260.html#a9eebe99216029b2f21656f50b4ed298d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_496", "a00260.html#ad738b744dae969df905544c07880440c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_497", "a00260.html#a30b05d5cf3c20e120539a71a86f4b248", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_498", "a00260.html#a62bc700ed9bd306f072dab338e5452e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_499", "a00260.html#a7db6f79e7d465de3baf951ea9482b87d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_500", "a00260.html#a9d7b6d6418c670dfbc48c35b4e0c9934", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_501", "a00260.html#a7d665cfe929665b3f3d918201482027b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_502", "a00260.html#a911eea0093cd3c22462ec0967c0664ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_503", "a00260.html#a68f99434d83b8d0d3020e98774ad4f99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_504", "a00260.html#aad041c0a61bbf70bdd7cd94f7bf7e196", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_505", "a00260.html#a3e222ffcf30bc7372bcf2a00aa3a5dff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_506", "a00260.html#a0da9aa446015e918d49193fc83fc6dab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_507", "a00260.html#a73306fd94e7940ae56ad77303e496c3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_508", "a00260.html#a31e1c389c374b373f7d5d7846ab6a1c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_509", "a00260.html#a082cc532269d883ea759f692eaee9e72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_510", "a00260.html#a81d17abe23abf5164f741123c6ad8777", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_511", "a00260.html#a32cb21d43eb7a0dd3a83627aaf45097b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_512", "a00260.html#ae08d368222c4a144d4f0f451ac72585c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_513", "a00260.html#ab18d37c7516c9410944ecf192eb7c385", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_514", "a00260.html#a465d0f003b6118a01fb12c8e65cbdf6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_515", "a00260.html#a2dd3eddfceea52dc605e2b6f9703bbc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_516", "a00260.html#af2dee6ad4e4583a92172078e6d87c4dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_517", "a00260.html#a967087aec26a681865775f3ca3839400", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_518", "a00260.html#acbc171db774ff4157d2318cc0f55b7e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_519", "a00260.html#a06b94e794700677eedfb1363b54c098d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_520", "a00260.html#a79402747e6d4c2b4024e3244f9565c46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_521", "a00260.html#a367c864a600ae59385bef23ddb837c9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_522", "a00260.html#a8fce2bed06f52b9f734ef64f84537e7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_523", "a00260.html#a7d64dbb57525a74daa596bee2f52048f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_524", "a00260.html#a9216843f444267b79b7cbf66765c193c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_525", "a00260.html#a94118340e15b2e809062b8ac74356740", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_526", "a00260.html#a3a125ac5f7a633450bab58965cce6ed8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_527", "a00260.html#afc586af7ef435b70174dc9fdddc8917a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_528", "a00260.html#add49cccbaea22810d185b1e8ebb160e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_529", "a00260.html#af8ec7d6c49c6c494d9dbc3f8cd3eb229", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_530", "a00260.html#a67c5e7f3255a588f73fc0e0cf574a42c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_531", "a00260.html#a45aec84add132ac5def0e6edb36808a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_532", "a00260.html#a11966d4277ffeb4457cb219ac7f974f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_533", "a00260.html#ad9cc2973a27ba67b8e7405ec30e79620", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_534", "a00260.html#a76a285f4ba159ec488518d5f7556adca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_535", "a00260.html#a932e11faae87e464f25ebe7aa77b31de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_536", "a00260.html#a2b280d3fa09a6df80f55d73308a33cce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_537", "a00260.html#a959eb619d5406b57c91ba6f6971accca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_538", "a00260.html#a963a9d75d7a54509d7f1acb76bb1ea30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_539", "a00260.html#aefa5e2a667c9c30d86489618003a9304", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_540", "a00260.html#a75926da4eb86f5591e075274fca125c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_541", "a00260.html#a12df4fe505c79eb9fa2d9ef1b429cfd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_542", "a00260.html#ab0d6ca2a980cb41bbcda2f0306b2586c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_543", "a00260.html#a78bbd354fcd51597e7e01957583da416", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_544", "a00260.html#a6d075fb95aee1bff379642c54efc3ca3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_545", "a00260.html#a985fab715d7fd9912412384f517ccf4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_546", "a00260.html#a911bb4f4ce71ab7339660ea0fc28bfcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_547", "a00260.html#a4dbf52d299d2906ded3506fde3445b6b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_548", "a00260.html#aee6344b171c260375da73a3c43602c8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_549", "a00260.html#a6d62fc70406b093367430a24acc1a69b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_550", "a00260.html#ad8540a6f4485fb3926d04ed795f89479", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_551", "a00260.html#a960b38030ef50c478dd0a3357be9bd54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_552", "a00260.html#a08a292004197a2c0f16d558a94d33440", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_553", "a00260.html#ac02f4c3dde2e622bc03bd611e7951ee3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_554", "a00260.html#a9f6da7f330b18821926fc1c4558f40e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_555", "a00260.html#ad39c661edb21a935ab0e92e33a0d4b92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_556", "a00260.html#aff475a2ee486fa9e9057397cf3f49d76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_557", "a00260.html#acca465a9fa1a3c2188dd956aa9896145", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_558", "a00260.html#aa73aca4c47bcad47109477ae8aee6bd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_559", "a00260.html#ae2f09d18e3a457a2cc9d1e5a50623dd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_560", "a00260.html#aafaa336e09f5865a67103146481e8660", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_561", "a00260.html#a191cb69b9f184161464faf515e259abc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_562", "a00260.html#ad38f87af37336c52f75625c5f8f06fe6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_563", "a00260.html#a716d1cbec8ee55977119bd6804625053", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_564", "a00260.html#a7aa3b099b2baa0c7d5e9f86020edc045", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_565", "a00260.html#ab675066189bdd418fdde4b87f77b116c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_566", "a00260.html#aa353e22b7a3ae45c5a71fb0c5ba387d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_567", "a00260.html#a99964a3f69218d542a620e8cfd630be6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_568", "a00260.html#a5d818c4ab2172f248cecb052ec88a28d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_569", "a00260.html#a4894f59a61add299ec53a0be29c30bdc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_570", "a00260.html#a8d442703f92252f76e316f9c8f16917b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_571", "a00260.html#a3db9f65a118ff0cbeaabe4c8a530f65c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_572", "a00260.html#ab144a570ed01e1c11c2e3ea10d239f62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_573", "a00260.html#afb4a19477bdce5576fb838b03483362c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_574", "a00260.html#a5daac24cbb723649ca79c119ee4c4b88", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_575", "a00260.html#a25f81de16ecbd5a1a3c9a28f29069403", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_576", "a00260.html#ac68568a2d1c580c26f0b373ec0fbcfab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_577", "a00260.html#ac1b9b738570cd9d1ce1087a7d35528c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_578", "a00260.html#a62c5874d83bda3357b02c0dde797a9d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_579", "a00260.html#a136f8056a6218f81b6f6e6a9dd6daada", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_580", "a00260.html#ab1fdb0f86361a3ea44bf047debf22f7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_581", "a00260.html#a4d31b9d992f28e1e66e8f5d5101e5415", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_582", "a00260.html#a65b1f98d84bd01d091d5de101ec68de0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_583", "a00260.html#aa2ad03bac340e2215aecb17f4d3cbd15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_584", "a00260.html#a9c8417330422b319b2478499910d97f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_585", "a00260.html#a4713796285dc3311517d98898ee0d7ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_586", "a00260.html#a02e5b7671bf4b3f2802310db5059a568", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_587", "a00260.html#aac65c8cdb50bc3fe0b4b59411726603a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_588", "a00260.html#a464903a65a8fe8be9ac51d7b1682a802", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_589", "a00260.html#a502cc5a1f9e5b73dfe22cb9230d0e6b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_590", "a00260.html#a9cc8c40dd7903a64a54fa0be9e176972", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_591", "a00260.html#acbbf63a0657b534e44d938e4a7d64e8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_592", "a00260.html#af18a507e5ac413f89d255ef3c5a2a62a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_593", "a00260.html#a71f85313af05155f67aded50a9d24d7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_594", "a00260.html#a664f5c3ed8dbcbbb955d11d68f1770b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_595", "a00260.html#aa130570187556cea630570e2ad86efb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_596", "a00260.html#a226bd093d43520f12a78399955ce1c3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_597", "a00260.html#a6d3bd687df0f3e1df4d87a0cec661a8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_598", "a00260.html#ab28ff1b12fb67c249694fe97eef421f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_599", "a00260.html#acb0965098f9dde484db23c4f6007ca4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_600", "a00260.html#aa17edd9bb3f923b284fa6301e57e144a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_601", "a00260.html#a41d8a497f1d6df32f19a77ca241380e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_602", "a00260.html#a8dba2b52bcd8133a7cc899e2bcac62df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_603", "a00260.html#a302d166bd09d4e993d1a5f5fefc10ef3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_604", "a00260.html#a38d693cd76a816e1b624f5d8e5880beb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_605", "a00260.html#ac7c9b2e5535150e036b3a6e848aed7cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_606", "a00260.html#aad0e271f602a633dc9273fd859e4c164", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_607", "a00260.html#ab3040a374a262b33793b9c605f27bb0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_608", "a00260.html#a8d78fab46e3a6d9aa29984ba0d71ad5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_609", "a00260.html#a319ab7f438ab4733a411a404742bc0d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_610", "a00260.html#af89326a73c5c26a4af0532ffb9a4e8c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_611", "a00260.html#a06fa1588b859483f18d3526f1577db5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_612", "a00260.html#a256ea6dcc7a9cc53844abb1f89fd5760", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_613", "a00260.html#a21de28c3c35ee580f17113ca3a6e9852", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_614", "a00260.html#a4995c95353609b02373a794d0411cc0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_615", "a00260.html#aa1312627dd5ab8453720ec527dd14d45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_616", "a00260.html#a28263d4f7cb1b9348a1f38202d520f55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_617", "a00260.html#a9c393276b7929a513f1c839d9952da8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_618", "a00260.html#ac37c10a32a73f06e3ecda639b5a5e28e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_619", "a00260.html#aed7e76c0880f531b1d70ddbd01604ffd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_620", "a00260.html#a7b1690f2a1461e62b977de852131c092", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_621", "a00260.html#a499019cc11156399e99fa89cf318072f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_622", "a00260.html#a5ee697144bc84c27b69f2589e48ad142", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_623", "a00260.html#a1a0abce75bc4677c3220f3bf46a9d7f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_624", "a00260.html#a9bb14644b556a37aeb8fafc0f2bf2fb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_625", "a00260.html#a0dcb02e071709217be2eecbe31a2c3d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_626", "a00260.html#a0ea2a1657b0a7c503a12bf0328259fda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_627", "a00260.html#a3ddca9e92c4a9f4068475fde60ba2c12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_628", "a00260.html#ae8b6747390905af6d655d1d9e628647d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_629", "a00260.html#addc95e4a613101caa166b7e2aa125978", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_630", "a00260.html#ab0d7b87d7466ce0f3150daf30a5d932d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_631", "a00260.html#a93a9901d54f8d49f468c34bea0bde455", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_632", "a00260.html#a1cd896ce6df5d185e8a854c98c0d9955", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_633", "a00260.html#ab00578f1c536676456f756cfbdd874f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_634", "a00260.html#a92dcee962fbafc17eb41a362467c3c2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_635", "a00260.html#ad16e09c1e41f80828945dd5674f1feeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_636", "a00260.html#a96222b7fc20d3a1f74f360c77316ccb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_637", "a00260.html#a2668ddd810749e0abe5dc80c1d8aa738", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_638", "a00260.html#a7e5e06fca356db40ca239c677afee86b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_639", "a00260.html#aa37154ebd4ec7b6ce46ab6627ca652dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_640", "a00260.html#abb749fa23c9db8962d45a5a9c2388b35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_641", "a00260.html#acd158908c9cf9e01f3aa57fe2f4df2bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_642", "a00260.html#a748d7fdefac3987b20ab8f5b4a5fec83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_643", "a00260.html#a46185ee26557f653e43a09fa11529cf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_644", "a00260.html#ad6c84c893dce04d5c91b995132ce26a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_645", "a00260.html#a0ba037043994dd8559bf5f74b9f266fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_646", "a00260.html#a20e378e41573730a171e971e27743f29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_647", "a00260.html#a1385fa63499d98cf6961a7bbcf80df9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_648", "a00260.html#a2aaf15a9bf4293a417c91276fe18f6d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_649", "a00260.html#aff7edb56638fc5f10581834f6cfb48ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_650", "a00260.html#aabe275d76702969c049c767445d2d8b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_651", "a00260.html#af3a74171636aa6ed586c9b23ea62b91a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_652", "a00260.html#a2f5c38aed2bab39994676dcb81dd1e45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_653", "a00260.html#aaad3b71a398dc9a4919b20cdebaf7a7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_654", "a00260.html#ae99b3a07135427012200ccb2e73fa2b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_655", "a00260.html#ab91dcd0bcb3b596871a534429179e5c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_656", "a00260.html#afdf3141c159babae678a528eb0bcdab2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_657", "a00260.html#ac77e14e11c23976e305bdc30ddfdea53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_658", "a00260.html#a617fc257cc962a465eb2fb6b9533e187", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_659", "a00260.html#a2af44edf962ee83df9f0b16733086fa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_660", "a00260.html#a5b625c9c0c90ae8d9135376bcb2eb393", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_661", "a00260.html#a148ca4b905c45c26854d166531452874", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_662", "a00260.html#ad52ee5c79066e0ad99d70629e3a0292e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_663", "a00260.html#a5cd473660daec32f81401ddf0db0f00c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_664", "a00260.html#a50b7fbbd7c0818c37fbb93a33b1247fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_665", "a00260.html#a7fb4f479ff8a9c022b8619c3453cd0db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_666", "a00260.html#a2b156f1c33eb60b222471fa5f6c11606", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_667", "a00260.html#ae6ad2df004c7ec9fa4835dd5fd9bdfef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_668", "a00260.html#abf7fd42963ac3deb7b861d65740c1959", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_669", "a00260.html#a7fc2303b75ea3b688c9a096f21877faf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_670", "a00260.html#a08ebe792061b528e072b9d47ece46932", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_671", "a00260.html#a4094a5628c25f0579bc9c48fa7b47361", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_672", "a00260.html#ac02b3f57c26433b9715d3048bf08b086", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_673", "a00260.html#ab6f35dd0bc14cc6f52860c8dc254489d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_674", "a00260.html#a688419400802f823f037229e89b3c35d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_675", "a00260.html#abad8ce66526205f6acbb0b689780e300", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_676", "a00260.html#af7eba549195c768d23d8478cb468e1aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_677", "a00260.html#abb925acd4e4002bdd2e7caa80870105f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_678", "a00260.html#a8c17a3df02e0984a0d13989529fa4380", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_679", "a00260.html#adcfaf978ac1b0557ff90f0e00328e03f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_680", "a00260.html#ad244ac562103d966c99aab4ca2a421c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_681", "a00260.html#a7c6c505cf47ab60863ddc496faee2783", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_682", "a00260.html#aba5afe6b86d57e49d56edb2f113e95d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_683", "a00260.html#a72462e064507d4c88104fc737cb69b39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_684", "a00260.html#a97215d0aaad49324270cbd752b5ed498", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_685", "a00260.html#a2670125de7fd9068c2a7af19dfc3f7ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_686", "a00260.html#a5ab41051433bef2ca298f80d4ad296b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_687", "a00260.html#afb85270811d28a512cd4df9b5bc12723", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_688", "a00260.html#a10325c590db07fa93d4755608ee98a92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_689", "a00260.html#a068bbd2f986f862fbc79124675644338", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_690", "a00260.html#ad2da3525d5c6b3d1481824b9c13e41e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_691", "a00260.html#aef841bbdc6f04cbb3ebb2202a0756ea0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_692", "a00260.html#aa6e6a8dfb5af09df7be305ab132cd81f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_693", "a00260.html#a78d61b1bd30a0fbc254a9349ce02420f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_694", "a00260.html#ac84f4ff4a3a2a0cea6552acf2c267e22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_695", "a00260.html#aa7484f41fb62387a359ebb3c5fc3582f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_696", "a00260.html#accd24fa3f31c9eb0d0efa3f763f419de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_697", "a00260.html#a9ef1ed75a52d1a3010476923fc3241f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_698", "a00260.html#acb915ced79e2db4916b214f58f503bad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_699", "a00260.html#a345173e93fdd723907998621d07d9dc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_700", "a00260.html#adcdd8eb739ec4cbeedcf9ea3c36d1253", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_701", "a00260.html#af3ae51bb9c6ced61c24e96cf14d2dbd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_702", "a00260.html#a9efbcc835cefceb729a17910adb6c95b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_703", "a00260.html#aea07e7b1fda809c344f97a7094289e45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_704", "a00260.html#ae4017c19ca0eb6d38a3054e7c26870e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_705", "a00260.html#aa3edbd8967cb4deec29026a081da55fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_706", "a00260.html#ac3793246a75dc8db28a47905078cb288", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_707", "a00260.html#af042da14d389574ba428b5840c80eb2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_708", "a00260.html#a52ddfda4bc42a2956ae125eda5b67f22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_709", "a00260.html#a18c140e178fafe2e5e9f1688742c42bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_710", "a00260.html#a56762776075d4f8cd9c6368ca87e5244", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_711", "a00260.html#a7b0538834dda2ec16e00cb22e463b10c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_712", "a00260.html#a45be8b69183b4291daa0d0bd89f79271", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_713", "a00260.html#a7f2cb7b9bab8c5215809f39363321f39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_714", "a00260.html#af2ba1093077011043d31d4e174407475", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_715", "a00260.html#aa0a2fdb3e3537ef9bc5dc3ef1f6059fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_716", "a00260.html#ae69bcb2d297dd8c993f83f65106cba01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_717", "a00260.html#aa6b39ac9598ce7cbabc62992504feac0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_718", "a00260.html#a04e6097c12df0fb948fb91b8c5551ee6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_719", "a00260.html#a6c682ce4443dccb129912192a9cf1fb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_720", "a00260.html#af7a24704d890f8ae667dfa639c49ee2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_721", "a00260.html#ab22d9daa94336697326f98b25e00d207", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_722", "a00260.html#a84a43bce5194eb778549fabe2c5b67b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_723", "a00260.html#a99857f6700619b95f89a6964e345e78d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_724", "a00260.html#a0c18a5ace1d36dff7b70f935cefae33f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_725", "a00260.html#a7c9e44fc29e18e2bae8ae3d104049d2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_726", "a00260.html#a3ebb945871c3c021ef4b0050b08c7e8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_727", "a00260.html#ad9100af6ab02dce0c2bbd260c774294f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_728", "a00260.html#a41e8e4545536ee46df2bc373a21695e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_729", "a00260.html#aa3fcd810fb4228b3848bbb1ac67fd7e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_730", "a00260.html#aed7afb005e99fdf10d6e73f6d3efb97a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_731", "a00260.html#ae182c68cdfc4e604fe21dd6bcaf9a45a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_732", "a00260.html#a879b22c1caa9bf7a3db94f2306d6f266", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_733", "a00260.html#aa21c1c8334d62ea5740bdb127c7ca867", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_734", "a00260.html#a61094845a28fb933aa8f0d2df6bb9e8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_735", "a00260.html#ac26ed4a87d943afbc5655f386a3694aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_736", "a00260.html#a58a9db09a4d68695eb0bb19384edc80d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_737", "a00260.html#a8ea89d9d481b493983305ceba88fac16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_738", "a00260.html#a11af699daf64f2402852d689634cdf79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_739", "a00260.html#a9c23a649dc1b00978bc001e25aac6a46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_740", "a00260.html#ab06d719c9fbca04a39e3be2e1e7b2285", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_741", "a00260.html#a6673473dc43e01631d1a0cb5ebfa1abb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_742", "a00260.html#affeb06e1baf76e5a7ebbbdb0de1044de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_743", "a00260.html#a460e7750a5c582232e0ee67f912a8ab7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_744", "a00260.html#a34ef6477470aec9c4703a85182b8ef6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_745", "a00260.html#a6732e35124830ef6b06fdacf07415790", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_746", "a00260.html#a40d74b3a09305e3712933a223bfe0809", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_747", "a00260.html#adaf20aae5826e33e38833e68dfbf788f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_748", "a00260.html#ab77966aaf394e95f745028c4102cab8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_749", "a00260.html#a16523933879f30b4d47462be7dbf90f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_750", "a00260.html#a6acd455b15a0573bcab1ccb306852ce8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_751", "a00260.html#a0c55fa9feb9f982b4f00a20d5e5949ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_752", "a00260.html#a2284ec2795bd9511e28151e2784338ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_753", "a00260.html#aaf73b3d846ac45b125c424d1a8bd22f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_754", "a00260.html#ad223df3263fc5c842b90dce1b795f149", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_755", "a00260.html#afcc827c907e4d44a3ced207b5499c146", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_756", "a00260.html#ac4787a08c0d5cddf452c33c40de9c165", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_757", "a00260.html#a142d8f0c3703ee886f9569808311b58f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_758", "a00260.html#adf179762be2cbf270c25cbdafe682961", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_759", "a00260.html#a83ac54a204cab717b6a892c5a9e93426", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_760", "a00260.html#a69066a48d2f025d4f918ddb4e082276e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_761", "a00260.html#a8ab0fb29517996c3e5932eb243f780ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_762", "a00260.html#aae4934fc6a2693aab38d73201e8e6837", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_763", "a00260.html#aac3cfa3b6af90aab722ed3d46c94b4df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_764", "a00260.html#a857db1673f69b84df7d26c1cc1a81c9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_765", "a00260.html#a9b07b6f8a30f6691982b0ea92a92a9e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_766", "a00260.html#ab704192f078b2f11d0f40194aba6004b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_767", "a00260.html#a890de397398121ca83c22e6c678d62a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_768", "a00260.html#a7aca4c5d96e5cf28b25688bbf97c8b75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_769", "a00260.html#ab5088b4776d5c36f7044733d2276e5a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_770", "a00260.html#a4d96407bdacc649c39f811fca571cdb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_771", "a00260.html#affc3f97816f60cd076c6e27353e3eefb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_772", "a00260.html#a30082cf9b40e18f7983c93358078ba62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_773", "a00260.html#ae3c0e67c576fc9e50154f53e54de5bd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_774", "a00260.html#a0d71fc197ed054647f9000300960493b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_775", "a00260.html#a4b4eb6d0ac51d56d48c8764a05499afd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_776", "a00260.html#a09d8c546cc3f08a3ea457f303021a134", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_777", "a00260.html#a576d5ade8a2ea30bb872c19d5c206c35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_778", "a00260.html#a823c7353bd5d500371891dded7aa7f40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_779", "a00260.html#af7f52d039be967c8293762cd324bbd22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_780", "a00260.html#afb18b141b369da82b9e3d4a1a9fa93cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_781", "a00260.html#a4013973cd8ad57cb1a894d122cfd8ff0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_782", "a00260.html#a7e201e58191d85b2b3d2decea28eed2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_783", "a00260.html#aea6a60b26416cfffaebb539555f9ebf2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_784", "a00260.html#a1e9bc88dbac2982f126a233abe8463e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_785", "a00260.html#ac14c05816a0fe62b7e1cf5242748b628", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_786", "a00260.html#a5fee16b691227895176b689af06113ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_787", "a00260.html#ad0e977a58a65ce13d69ebae95ae010b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_788", "a00260.html#abe502832c23142d9f0b13c1ea90a8dd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_789", "a00260.html#aecdcafeefbf67fa5d6faf3ed9954e79c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_790", "a00260.html#a4caeec0f89e97bbec5fa2b800487138c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_791", "a00260.html#a298ab8ba85f0c8aa52ec50d1ae80c7e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_792", "a00260.html#af267955c00544699c9d5071c95e6c0ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_793", "a00260.html#a53eb7e4b733ec24a8479d5d3a0b79336", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_794", "a00260.html#a44c0d4e85f85ddefd66e4ff27f86e0e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_795", "a00260.html#a31be32eaa86bd693c59c0d0ed54363c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_796", "a00260.html#a42ad4ab5c435f1e8b60964e1e760ad59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_797", "a00260.html#a9c793f4feb915f86c303bb67638515f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_798", "a00260.html#a7fafffe56f8812a62e3451a634f7534c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_799", "a00260.html#af3ae8c225b0f18b84a087a6c0321b0aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_800", "a00260.html#a73d5e742e7ea69a2e3c7679017206981", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_801", "a00260.html#a6bc53cac638736aac9be0bd53e3f49ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_802", "a00260.html#af5af603f833e30c8559007f05b832988", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_803", "a00260.html#a01106aff83db6bcc1e89922fb178d843", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_804", "a00260.html#a4c11ae4843bcfb42f4f843eec735b324", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_805", "a00260.html#ae668ab7128eb220de6d25e37115d3d21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_806", "a00260.html#add9faffccdff9e75f17d1254ef883f96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_807", "a00260.html#affa91289fd9640b1da071761c1f415ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_808", "a00260.html#a36d4440e2afa6533262d42995f68e576", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_809", "a00260.html#a77b3a15244ca5e6b27ba3bc34dc3d7ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_810", "a00260.html#a5498794e7cecf3e8bdd5d6b5455dd469", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_811", "a00260.html#a3492744b36dc61d4f7ee37e8f0bc3d84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_812", "a00260.html#a5d0d853ee706d3ec6f80f34b65dacfa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_813", "a00260.html#a7d11d784d4f71ceeb99ccfcca5b13d9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_814", "a00260.html#a21470e2a0d4065e58180b22a0e29a52d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_815", "a00260.html#a88f1e6f8b443dbd83af54e02bb2eaeb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_816", "a00260.html#aed0c868b082ee5a8daea132c32452cf4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_817", "a00260.html#a42081ca01fbfffd36afc5fe78702e079", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_818", "a00260.html#a2ecc94c17063e883cffa1077a4cf97fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_819", "a00260.html#a397c70bf5a7a4d9ce536c672b1c8cbec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_820", "a00260.html#a032625cc44af3719e6a0bd1db9dbad65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_821", "a00260.html#ad9616ce7006babee7ae033495d12161b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_822", "a00260.html#a9562173e59c802b48840826cb738fef6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_823", "a00260.html#a9d82ed9b313424545998cce52e08815d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_824", "a00260.html#aca1561090804d90503bbf72166b7856c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_825", "a00260.html#a03820f96264f439840a83b0bb89f3c7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_826", "a00260.html#a5790358c3b4de39093b43f4585bfe015", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_827", "a00260.html#a4de3e68a2626d882605fca2a4f83b727", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_828", "a00260.html#a30caa15e01349defbec9680f3ba5eca1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_829", "a00260.html#a9725551b8f9b8c99fffe82ed88cd432e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_830", "a00260.html#aedb7d1a0abe6babc4b7b9ca97730f3e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_831", "a00260.html#a1ecdc9bfb1a0e2e0e68ac72f7e5e2d42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_832", "a00260.html#aebc3dc2157aabb6b2d70f25f3275544d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_833", "a00260.html#a33a8767cf8c12ecb629fa236bd947e4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_834", "a00260.html#ae6ebb0031dcfafc173df5c17e6059cf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_835", "a00260.html#adca1c8d3c669c32bee656523eb1a7548", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_836", "a00260.html#ad5e72b606f83b2ffa799603663fcffd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_837", "a00260.html#a6de5220dc4555f7193a55ff8313e5c2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_838", "a00260.html#abf098f7ffb2b878a036babebdfe9f7e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_839", "a00260.html#aca219c50f0ba9925e215d5b683a90375", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_840", "a00260.html#a23a79cd28b7b4d2573af33c727362665", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_841", "a00260.html#abf7751f2821004d83e15e0b9e82eb415", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_842", "a00260.html#a0152bda1043a4b3e46eddb65f95c5970", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_843", "a00260.html#adbbaaed575ee6e97ef37fbfddd79c8b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_844", "a00260.html#a647a01c4c6e8a6a5976fc7bb6bd74431", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_845", "a00260.html#acbae77eb7b3df47df97e8c7c19ad8392", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_846", "a00260.html#a9ca6538e12e02b369e7ddf20cd0c33d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_847", "a00260.html#a32dd59e40c704c9f5557f3f5754e06a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_848", "a00260.html#a092f89e9a9c964e331b0ecca93e67cc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_849", "a00260.html#a0a2be237756ff308829f4485c551454b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_850", "a00260.html#ab90c3fb397ad65e7f2484c730db43154", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_851", "a00260.html#afee39d667c89ba7a9990d025c12947e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_852", "a00260.html#a80152b8a64b7f3f98d6915c72df1aa04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_853", "a00260.html#a960c1bef8ff337099989024f3beab2b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_854", "a00260.html#ac2fff99ccff9b296480bead3ebed3e10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_855", "a00260.html#a1b0dbbbae2752ffe09263a999213f9cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_856", "a00260.html#af7e8a6097fe27797f186b51678891431", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_857", "a00260.html#ad80533c6535cd80fab254af5ba8363d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_858", "a00260.html#a50b2a398ea894ce4c665f716d9727395", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_859", "a00260.html#ae52f0e35a97af277ebab58eb7f26dff0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_860", "a00260.html#a09eaea12deea681c3c65e9ebd4422ba8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_861", "a00260.html#a34b3d0e895de6e04c396b9273af23982", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_862", "a00260.html#ac36edb1be60fe2e451285454a0293521", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_863", "a00260.html#ae651ed45bbbc9ea9aee03a4a65433d84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_864", "a00260.html#aacc7e7be31369286c5fe68cad4d40c56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_865", "a00260.html#a775bdd5de847b034be7ae9907f008639", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_866", "a00260.html#afa619f8e442dfbe8664314bed4bbfaad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_867", "a00260.html#a7c145c920763fba16e7b1f29398b34d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_868", "a00260.html#a1ce1235a4e9060f3f4848478826d86ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_869", "a00260.html#a2df69070e5e628ec21ac05c02be1da9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_870", "a00260.html#ad517b45f98bbcb9bfa5d24a0b5f38f64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_871", "a00260.html#a768eb0a3e1b8f3aadf0f25609769f429", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_872", "a00260.html#adb5f7db1e0020dae1a083b197c70c35d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_873", "a00260.html#a3b79fd23c8464cc4bf1f66d5c336be4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_874", "a00260.html#af41af61edacc4b4debf897eb92371c9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_875", "a00260.html#a2938b2a8974212ce1a651e8f42487a93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_876", "a00260.html#a13aa8cb421920b795e75afc3c3cc7c93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_877", "a00260.html#a984d782fea597ab0fb8c728e5ae600bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_878", "a00260.html#a47be8cb04b19b226c37a4a8e1ac959ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_879", "a00260.html#ad844f57f4617ab733d555218f29234e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_880", "a00260.html#aa7f86b46f27637276d337a8de3b9c8f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_881", "a00260.html#a374e80f00712e5e05e8f66d8e5d09b79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_882", "a00260.html#add47f487f9111bc4545ef4ea72d85d9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_883", "a00260.html#aee9dfe58863c16746f47b06a6324d0e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_884", "a00260.html#afcfab02210a3d7be7572ceffa17b86ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_885", "a00260.html#a60d61a0cb2ddeb3e91a561bc2906880e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_886", "a00260.html#a24f57d5c38301096dcdfc0db025a2e07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_887", "a00260.html#abb89a3d75e3ce21067be52596b11632d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_888", "a00260.html#a1d0749524dd84839d75cecb66bbe5e16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_889", "a00260.html#a9330469bc8d2e3446679272bdbf1e23e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_890", "a00260.html#a198f89510263500ae4b926be978d00c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_891", "a00260.html#af0796cce0bf2d6834c479fc0511a1694", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_892", "a00260.html#a05b0cdb897389efe3f38fba0d1b36e5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_893", "a00260.html#aff431147317fcad60a8214308a2bb47f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_894", "a00260.html#a4e932c87437d53561498eb0fdc524506", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_895", "a00260.html#a7b2ba64d694c602958db98234a0520f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_896", "a00260.html#a6ddbe6f1951a562a8a1ac04e07f1beb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_897", "a00260.html#a58e82e355820ac635c1ee2f1c9616bc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_898", "a00260.html#a6003644cfd0cde3626f1e5649601b20e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_899", "a00260.html#a9ebf9234118dd7ddf5af92ac2ed9d11f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_900", "a00260.html#a8fe137e8efee22370e9bcbb0b8715e43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_901", "a00260.html#a98ddf39ffcc287701c172ed486ce1867", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_902", "a00260.html#a444b9993f687bf228d41e7332833aff2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_903", "a00260.html#aa1fac3e82d7d3b436926b9ede3892c51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_904", "a00260.html#a1505ed7f54639e96c06a8670148458cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_905", "a00260.html#a22508bf34af7e30f7f653394fa5fc99c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_906", "a00260.html#a96e436c370489a573450add6f166ea1a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_907", "a00260.html#a69f51fc53f31dc4ef283a7f70568ddb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_908", "a00260.html#abd12beac5878b139de2886dd897e9129", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_909", "a00260.html#a07b7a696d945f31c7b920ecea24267f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_910", "a00260.html#af2b98d3cf29ecf010f7236e2658d77f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_911", "a00260.html#a89e3f01ab0b4f028f16af39e74cc3ce8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_912", "a00260.html#a5d70c0b7e3872cafb9f05cb936357642", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_913", "a00260.html#af2ac9207e93be6a06a63c7e54d971763", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_914", "a00260.html#aa53906327d54c233c3e8e6b9c5577521", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_915", "a00260.html#aae3c3e832a8888927069fc328995a6ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_916", "a00260.html#ad7842833bf31290d873934b9119cbdd7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_917", "a00260.html#aa924a53b9093f418085d70d72a7a9ea0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_918", "a00260.html#a955c808defd25b5dfa433f0563e271f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_919", "a00260.html#a1c7a49641bda8b154e6654a7cf04faea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_920", "a00260.html#ad60b49d3f4e3ab9beda46eb8f5414790", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_921", "a00260.html#af83eec4115c9df98d6505c401ef70768", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_922", "a00260.html#ada3c89f01a4e42f5b92bdc77b541b372", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_923", "a00260.html#ae74ba135978cd0a5cfafd0fd892338cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_924", "a00260.html#a6dea854f359abd5ac850edcdf8f5fe3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_925", "a00260.html#a18b3cba9ce500db7d30bc4713f170d8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_926", "a00260.html#a7c0281c9e377105298c12c49a681e707", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_927", "a00260.html#a66373ea493a024c8e413d0015317ef29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_928", "a00260.html#af372beabbf429036c48369a467116e87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_929", "a00260.html#a3a997995fb177b7e36a9fd4bafebd950", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_930", "a00260.html#ae611f3feb02eb2a510c0c7e61878f212", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_931", "a00260.html#a942163ded737b0c08ff44b115280f35b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_932", "a00260.html#a9a9c6bcb0f4306e8b2f4f9bc13d4a1fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_933", "a00260.html#aa7e9e505ebbe3c119c48914a1d74b3ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_934", "a00260.html#a048df2af6c46cdef1909f2a12f876cb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_935", "a00260.html#a2a96d5b012a130190e76f4c508fd5798", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_936", "a00260.html#ad4b47c6bc3ac13f1fb6c5ee375e1c5cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_937", "a00260.html#aabdb47d83c6ae216d6ac74d0bfee9e39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_938", "a00260.html#a5e438c9e1dab708885daf20e1660294c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_939", "a00260.html#ae9c8b6385c9b48ff65b14ad76ab284f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_940", "a00260.html#ade3d641ce5f79999da89d99d30d2c0cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_941", "a00260.html#a6a84d7eec0ef4e377f78bfafb0c06250", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_942", "a00260.html#a64b4a21d72439f1f5a401b1d66659ba8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_943", "a00260.html#ad894372857d1fb6e27fa0643331abb16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_944", "a00260.html#ab93d7e162bac2afb0e7074b75fa7617e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_945", "a00260.html#a16de81aa1c46b81085b7d97e30dedee7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_946", "a00260.html#a01d067b6fea02d9a92cd32fe3fc7d6c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_947", "a00260.html#a80921b225911489376b42f7c48b25258", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_948", "a00260.html#affb47722f945085f094b5e0128ca2ff1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_949", "a00260.html#ab4b3a9dc89a2cb8c6d8fa370852ba61f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_950", "a00260.html#a14577f890f99c384de27570f2a260b49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_951", "a00260.html#a2fa0a0627fd3e293588ebfa953bf75f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_952", "a00260.html#ac7ab82fa0c88ca5aee9f35792eddcbc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_953", "a00260.html#a68b7bd585b24b5c84f83f70a9216bdb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_954", "a00260.html#a7e9d5bf1f5c19aca3855a93c3a466e5b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_955", "a00260.html#af1165301082f06a11d78a5e87507ff97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_956", "a00260.html#ac5f8f9a50148d2dc0c7969e952cae2a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_957", "a00260.html#a9d425da8b7a495aa5a683f8c2a0dfe27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_958", "a00260.html#a1d39ae841c7789fdcb1fd6eb9b20fccc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_959", "a00260.html#acc9a3624d1e8afce6d4291e5246c4129", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_960", "a00260.html#a4cb928b22f93510c440b94847a4c2fab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_961", "a00260.html#aa28093880f6d38d281bfbf909efe22f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_962", "a00260.html#acc61d30c6a0b5c4684c65ca69f52c924", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_963", "a00260.html#a8b43f39d7abc3f249ca91726287087e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_964", "a00260.html#af9da52ca344038de56dca5122e395724", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_965", "a00260.html#ae49048e1b08ee07730394b6ad8e619e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_966", "a00260.html#a6a553dbe579080572361f3e072a1f197", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_967", "a00260.html#a56e2fb8334bd2aada76188739b3abe11", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_968", "a00260.html#af8252dda2a4ddc54eded9b81d0de254e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_969", "a00260.html#a1825c4e856539963964d8eb953f42ebd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_970", "a00260.html#ad3cfda25fb759241ec4fef84b58701df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_971", "a00260.html#a41fd639642740353d44f72c576ed9522", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_972", "a00260.html#acf87978b1cba4427a6cc4f8d6f0f475d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_973", "a00260.html#a412412d88723897fc6e70eee4ded0edb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_974", "a00260.html#a97e379b7bd752516eacf2b20475a6d06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_975", "a00260.html#a17e4c5cf1ed201b2ceb50338d32377fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_976", "a00260.html#adb80d1178a8155a157e1e29f646f9524", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_977", "a00260.html#a6f5557fbed97ac36b5f584b6792b199d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_978", "a00260.html#aea4332e5e79955334002a4686d2faa31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_979", "a00260.html#afee9911aa22e52d27ec9fc56db6db5ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_980", "a00260.html#a7d3a187b2720fbb71c6097066aa66071", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_981", "a00260.html#af92389ae15f11b67b8da20bfcf6f8deb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_982", "a00260.html#a1f0990871a5b6f03eb46ff282a9dd1ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_983", "a00260.html#af79dfd0eb0ea98ca16b6e200067d0b15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_984", "a00260.html#afd2437aad34af6c32dcea328e7c23721", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_985", "a00260.html#a567ba59d31631112875700b19c09254a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_986", "a00260.html#afef3c4bba32cce5961b6e3434baf6ec2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_987", "a00260.html#a8fb26beacad253f7b93875227b6f6d5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_988", "a00260.html#a7719b8bbf1a4f800e420de51e152c4cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_989", "a00260.html#a508636a2dff459f9e669fb0f8709515b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_990", "a00260.html#a0b536cc818178ec7b30aff1f888e0115", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_991", "a00260.html#a08d422c4fbf77c95f205d1c1a06dd44e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_992", "a00260.html#a487c8c1ed7bc08bfcdd90b0bcc33129d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_993", "a00260.html#ac8df21cad80ed4cdcfab92d7656f8cb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_994", "a00260.html#a4a2284aa15485222938fea947f8378c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_995", "a00260.html#accd5f6c3bc3379093a2bd0db83e47692", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_996", "a00260.html#ac551eb5aaad88dd0381c700c0c8becf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_997", "a00260.html#ae5039366815f9d9436ab68d513d12e25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_998", "a00260.html#aa57b7835d0d9ef92a13f25b87683a30a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_999", "a00260.html#ad6735c1b707889635e4a0b4f46f6adad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1000", "a00260.html#a4951a476f7f71f1ced8f42da5aa09552", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1001", "a00260.html#a64834e75c4dabe86e25a9cc598a5b978", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1002", "a00260.html#af75f55cce9ee6b64f352162069cd0c24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1003", "a00260.html#a5875bdd93ae2c183e1a3e093cb0a68ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1004", "a00260.html#ac719179bc46e197921172081b3afcbf6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1005", "a00260.html#a2c7a2a64a58eb3f30a29b05eb5837da2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1006", "a00260.html#a9cf8caf66ef8e6c88b265fb27a4ee45e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1007", "a00260.html#a89ba93627a2c4e20ff589a7225eb59bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1008", "a00260.html#aea1b0499cd2edc79bb1f601eb67c9c4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1009", "a00260.html#a531e288985df6f5762d7a23c2c566cd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1010", "a00260.html#aa716649b622c9332c2ebd79057c3c62f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1011", "a00260.html#a40031ae0640dc1f5ff787a9feb3d2e0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1012", "a00260.html#a990c6bd73788e146ac3f20d803f19640", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1013", "a00260.html#a2e567f08392a1db675d7c479220aa1c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1014", "a00260.html#a89f868b46a3d2a2c04ef7f96fb945578", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1015", "a00260.html#a6f6849802dd670e78a47571f3e9493ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1016", "a00260.html#af28140a1adf40b708ac3141210509204", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1017", "a00260.html#a2ef1e2ec3a9cd77f93d71cb4d8d79878", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1018", "a00260.html#a0cf5dac7313d5dffb5373d8c53c96de5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1019", "a00260.html#ae3e95ffa6514914d0dc9b8735a023740", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1020", "a00260.html#a47ad04ffd618234909c6a2d5294beff0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1021", "a00260.html#a816f233ff9cb178486ca6f86197be5f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1022", "a00260.html#a304ac2e23767f03130c0a59a127316b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1023", "a00260.html#a8f12ba484f0a61495444d4ae4851d2e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1024", "a00260.html#a94dfe26924f6269cd9bf335f084ab748", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1025", "a00260.html#a89ffd876453b8b32f2e7d08a54870316", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1026", "a00260.html#aaf73770520b9a5099bb80a11b7fc654e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1027", "a00260.html#a7e394553cdf1e824f5fe7a6d6d8c917e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1028", "a00260.html#a6cfec1acad40d938c1ca6dd54c5b6b75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1029", "a00260.html#a2288c2893e7c532f2998feb1f314e957", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1030", "a00260.html#a7b942deefbe968dcac373c6e9a67da12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1031", "a00260.html#ada4af727d35c3bace9878d79c4f281e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1032", "a00260.html#a3601e7bdfb132d99d33f8f29590652ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1033", "a00260.html#affa7f2896dfd4ba9bc2e7eb528ce8f04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1034", "a00260.html#a3ee92b288a9dd68ac2912a9e0c17f3af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1035", "a00260.html#a63341660b3a12c69616d61680c0fed2b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1036", "a00260.html#a02fe6cf8cf523e0529d038e90a7ecbb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1037", "a00260.html#acc07d8933079a3092597633f403e8161", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1038", "a00260.html#a8fe68eb22d521ab940b5239752d16021", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1039", "a00260.html#a32336e181305b05f9ee2b977db1ded8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1040", "a00260.html#a1830a72c51e80af0e73a9a326af5340d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1041", "a00260.html#a9093703bcac9a1a77997b6b4776d45b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1042", "a00260.html#afb3bdc1f676912fd55ddf2b4ba194d18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1043", "a00260.html#a4c1c27b3938b46144ed21e3d89ab7667", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1044", "a00260.html#afa38046229c84403045e97dcd360915d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1045", "a00260.html#a77713794be22eeb229944ed22e0fe11a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1046", "a00260.html#a279c1ca93239da7d41162f7fe1d3ebb9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1047", "a00260.html#a0a76ba1394d6978db2881bec98a40da6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1048", "a00260.html#a619a48e5a999b0ec1213630a8bd7e53d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1049", "a00260.html#a8872bf1e1c4d8ed15e5d5879b4bad32b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1050", "a00260.html#aedfebd9e7f9cf4c0fe950bd401b65a5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1051", "a00260.html#a6509c324fb19a42420138409f925674c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1052", "a00260.html#ac101e64d06f0de26fa202d80aa464a28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1053", "a00260.html#acbaa4fd90960e75ff8e55149a9dffd84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1054", "a00260.html#ac85121b52d56e10d1fb8be9de98ffcbd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1055", "a00260.html#af2208abf806ecc866e9a2c88a834e969", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1056", "a00260.html#a61223020a3b750f4c291ef3ece34bed5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1057", "a00260.html#a44e84cea17595d524bad48497a91114e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1058", "a00260.html#a8bfe1017bc8dc059290433867e56608a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1059", "a00260.html#a2bbfb082a4dc6c6c58234c17604de343", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1060", "a00260.html#ac105e96524e22d6c68111213e75c8dc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1061", "a00260.html#a8eefcd154883fe332abb9a7792bf8414", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1062", "a00260.html#a8ca8fa888f1bfb15d189b008de5f2896", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1063", "a00260.html#af590bdef5c3afb73244964e18ca74ffa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1064", "a00260.html#a954b04904cb472a84549cc12d39c403c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1065", "a00260.html#a51400967c7029dd42a75565e9be92ff0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1066", "a00260.html#a12873cdf35f5b57d2830c164ce467e04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1067", "a00260.html#a81806234f8f6c24c0e1a280231b88ceb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1068", "a00260.html#a92031c2b82d31a887cf7660a6a319d4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1069", "a00260.html#adc7752a81d6d1db4d68ccf0ddd9d746e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1070", "a00260.html#a43d7bd07151c0ab094f36b695295b56f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1071", "a00260.html#a7bc5e348f80f2c356f339f484aa21207", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1072", "a00260.html#a9b6e6afb965ba2332f5dcfbc0135e55b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1073", "a00260.html#a8dd8e9040407d29f8f445949fae58881", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1074", "a00260.html#acf1666c9acce8a03727a34dc07ca4cd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1075", "a00260.html#a6d37a798e8731c855e5e148ed4cc3d6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1076", "a00260.html#afc64294b67a7fe456cc59c40366e3fa2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1077", "a00260.html#ae15bd7770d8655c18a541491daf72035", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1078", "a00260.html#a6fad269f0143eebb2814d2108cd112bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1079", "a00260.html#ad47487a4c948680af2e8d4792262ff5b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1080", "a00260.html#ae3609480d180e090887fd5b00b9fd8a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1081", "a00260.html#a6e7d3a457b0f9fa96172489fd07ec957", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1082", "a00260.html#a053ea547c81d404eb47205b11e119d4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1083", "a00260.html#aa4b15d7b53cfe642bd10124a89050c80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1084", "a00260.html#a8f88b7502953105e141172c4d5f01cf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1085", "a00260.html#a198d29c6ff2cc824929d720646c97731", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1086", "a00260.html#a830577e2b5b9971e534a4b7f7b65b901", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1087", "a00260.html#abe21153d7801bbf92964b591657487ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1088", "a00260.html#a318df6ee02f566992b6fef64535ee43c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1089", "a00260.html#a363a993f43560de356da82dbb589b5f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1090", "a00260.html#a26b757a18e5566d80eb61f923823fc1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1091", "a00260.html#aa86889a76f2b84b1341eb12a3d70e1e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1092", "a00260.html#a61d37221e534632fa29ccf5c9853d4f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1093", "a00260.html#a5ecb687141f3f4719dca1d5691068746", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1094", "a00260.html#ae0c8a3e56e920c95f0bf19454e211202", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1095", "a00260.html#ae0dac0dc2b37ec8c5322a9572ff4e41c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1096", "a00260.html#a05adc69b4873fd0c013f087636f92457", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1097", "a00260.html#afdef6c0cdfb100cdda1cc0db24664716", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1098", "a00260.html#a20620e14a0a3dea9b595b617e914fbb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1099", "a00260.html#ae28bf72e0c311caf897e78394414ebd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1100", "a00260.html#a800fe19336ae0951f3e6f7cd292ce338", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1101", "a00260.html#a3b35355e38fe13b4fbf63118c8acfd90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1102", "a00260.html#af19beee6dd67a0314194e00e1e79aa44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1103", "a00260.html#ad34259d0ff1d9b0cd8b4cecb1906bd34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1104", "a00260.html#ab2e49ad968d9b2a42dcd02c59066bb99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1105", "a00260.html#aa309144c3b1cb38171e16dd1be9c6513", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1106", "a00260.html#aa0630160df73c1ceff88a3a24f9c3ce3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1107", "a00260.html#a822a81551be1a3f0f2f2bfd1686dc7df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1108", "a00260.html#afde8589d14cd47e31f422d7e3473f06c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1109", "a00260.html#a639a6afbc50262377a91cfc0bfc1dc53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1110", "a00260.html#ae6f10254e0ac5a15b93d8741643c7633", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1111", "a00260.html#a30542ac0d6391f7726ece69806be4aa9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1112", "a00260.html#a89484f4b01d5fac77011c662cff2ca09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1113", "a00260.html#a80ee0def142dda7fa3498f50c04d65af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1114", "a00260.html#aac83cc54324b49e2447e2679349ff4d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1115", "a00260.html#a887a81f8ed5b7744cbab8d389edad819", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1116", "a00260.html#a55961962e81e4b2c38baeb50a968473e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1117", "a00260.html#aa82b51db56c01abcb6dc82091ce4ed20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1118", "a00260.html#ab00c1e8b807cede0134efecbb0fec384", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1119", "a00260.html#a927c549d52ee4b88f8c78d0c0d925620", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1120", "a00260.html#ace47234400647d3d1697da1f74cd11e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1121", "a00260.html#a6e1bfedef6e092010be4a4d007c4f2cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1122", "a00260.html#aae465ead64cdc5ff0cb918a59d5fdd30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1123", "a00260.html#a756dea10f376c3e3bb8f4334c0fde410", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1124", "a00260.html#a80fe57afda98055b2cf2f1df878a1500", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1125", "a00260.html#aaa5a39fcbdbcdc2a88af6e30f073e74c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1126", "a00260.html#aa3cdfcbbe3ec0956f66493b330f91621", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1127", "a00260.html#a56a1935fc3f06281b8a623393c1a6844", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1128", "a00260.html#a9255795e48d93ef49e94f97820b6046d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1129", "a00260.html#ab647ed1e684081b267dc2b45b6f09f49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1130", "a00260.html#a1822a1ab7088314deb916f2144bdf277", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1131", "a00260.html#a7bb7233e1e51c2725b037a2eddccc6f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1132", "a00260.html#abb59ac5a77990c95bcb148d45be8c91b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1133", "a00260.html#a1d4e83b4d83c737676b6336d5bb45d7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1134", "a00260.html#af4b29127dbbf9253a438baf48f5fcd97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1135", "a00260.html#adafe7154484e8dc1f842e698f8d8a50c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1136", "a00260.html#a611d067c3afa141913634d2f035aaeab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1137", "a00260.html#a6aeedb5daba2deb2e46f5ed394d950b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1138", "a00260.html#a9420ee6e57cb6abd8a420bb1d4f6c55a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1139", "a00260.html#a5a61a262eadb53d3b6774ba205a334d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1140", "a00260.html#a448eb7d3849b5e7ef8146c1ec90dccf2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1141", "a00260.html#a2c1bd49672eeb6c8f8ffc37c8b00457c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1142", "a00260.html#af61fc7c4eaa08af293822e5be0d7c572", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1143", "a00260.html#a948d1ec7f7b6e81f30c1df10cbb2afd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1144", "a00260.html#aa84135baf0fbd3048eb2a30a9b3b69d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1145", "a00260.html#ab0783c0d0cea05644807af0f0caf07ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1146", "a00260.html#a3fc01328f76e611f3934b0e045aac47c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1147", "a00260.html#a9469cb269fd0192e2ddc81a50c8c2fd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1148", "a00260.html#a6f615046c184c1050d42a4867013e976", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1149", "a00260.html#ac8913ba1954b5689fe7ba15ce3324491", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1150", "a00260.html#a7731af89d4873671d6b613533c819fa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1151", "a00260.html#a276b493e36210bacbe81c055e51cf822", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1152", "a00260.html#a41f9a448bc69a5b21eb22eeec121390b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1153", "a00260.html#ad3efbb3694f86352e8fd45eec28c6c29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1154", "a00260.html#ae228b2c6a71632eb5f12105688265ea0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1155", "a00260.html#a49e1659fc825deaa66d531b6c89b3961", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1156", "a00260.html#a1af0004bcab704f79c3f7de494ee34e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1157", "a00260.html#ac93634f6b2bfd6c60eca80e4ab9d5d48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1158", "a00260.html#a8a7cbb680154f4afabf3139213b31c72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1159", "a00260.html#a5718a917c9652922486c2a45a0c634d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1160", "a00260.html#a10c0910af2f2512afdb3cd638a33bef2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1161", "a00260.html#a89a0fab2b74dd296deca7b62e8ba344a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1162", "a00260.html#a582e327eb9303da014f444bae4c4b98a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1163", "a00260.html#ac6134c80a9ba11bf2d8a10b9d73ad6bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1164", "a00260.html#a1da17742b0dad46e0b61cd7aa6f8e9e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1165", "a00260.html#ae3b5bb292b5ebba0bb4b0873514022f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1166", "a00260.html#afa2252a75288503cf5d7fed80f696981", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1167", "a00260.html#aa6f2ee19a4199cd3e04794f47304adbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1168", "a00260.html#aa5bd9c71939a0976906df0b26a9eb593", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1169", "a00260.html#a8daf34e92e92556253771f7c242c47fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1170", "a00260.html#a4277fa4865b700a6dc142d029acfbe50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1171", "a00260.html#abb4e8c9418206cd577ebf5cba5deec72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1172", "a00260.html#a8f494bd9efe90d5fe7c3b87d6623cce9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1173", "a00260.html#a909d8890f37bbacbacf9f1400be6af02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1174", "a00260.html#aff6a14cb0d75e36f2f100e12b8494afa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1175", "a00260.html#a2d66dfb90dcae9a19ced00ad83a72640", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1176", "a00260.html#a5806d47d15711df26db05d581e3541c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1177", "a00260.html#a98de7b196eb595b5b176626892438f98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1178", "a00260.html#af9a7410afc1935b125b19029ae290812", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1179", "a00260.html#aecd1991570196682617c589ff4707c48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1180", "a00260.html#a26c772490e72cf76c3f217d98fa663e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1181", "a00260.html#afd5cf94250f30a8441e7c28199d6438d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1182", "a00260.html#ab2f71ec55bf3dd2e011d032911ea202a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1183", "a00260.html#ad792fb90186591479ba77adfd9c44767", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1184", "a00260.html#a588382f5052fd06e4c61fc856bb7fbc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1185", "a00260.html#a8a51bc5cd57732e33758ba9ca123e1a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1186", "a00260.html#a9fc567f056b0fc7c8f28c842933358eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1187", "a00260.html#aabd68ae4723dfe4617b572a429919df8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1188", "a00260.html#a3890f90b44ead112dc2a5d96f3352bfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1189", "a00260.html#accd82b3b1d82dce74fd5721c3fe0c037", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1190", "a00260.html#ad862935d7c35b56a96a13ab97fbc0334", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1191", "a00260.html#a523ef8a829e702f1abf931b4035978ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1192", "a00260.html#a06483cbd7510a8f7a7606d39afb81776", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1193", "a00260.html#aca2f10f19b45a08c3469bcc8a440c52e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1194", "a00260.html#a31e5cc6ba3688e69b0ce4fbacf85bbc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1195", "a00260.html#ad9ba9a02dc68f1b423628281df8dc3fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1196", "a00260.html#a7046dc27e894cb210d9b3664607da341", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1197", "a00260.html#a73d2e39ade08b8f6c2d8ee9502bbd1f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1198", "a00260.html#a99d64f02fcc15b40bdbf7c1ef9b14455", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1199", "a00260.html#a27e4dd4eecb9f19025379d3d0f98228c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1200", "a00260.html#af8a0a2c366b1db980b56743cbfbaf5dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1201", "a00260.html#a79a46d977c141b4720684151739d63dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1202", "a00260.html#ae780ebada80739fe5372f5f5e4a97aeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1203", "a00260.html#a9b0a721650294e6d58b6f41088ac3550", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1204", "a00260.html#a765c9c63a9dea427775cfa748123851b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1205", "a00260.html#a7ed857783b5141e620fb9b9ae9f1a6bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1206", "a00260.html#a4e470867b89dd0397268ccde34f31bcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1207", "a00260.html#a22833a1e7b4247e6afe5e74e24c93d85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1208", "a00260.html#a03f3260780666ce8f79c4ca5b6f79ca0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1209", "a00260.html#a7eb0a822b53061bccfe02c3536f19a8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1210", "a00260.html#a6267aa921e29e2f3758d6f1e6f5edaf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1211", "a00260.html#ae23be7d502a145cbf0d557473347954f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1212", "a00260.html#a67f5a123240ba366afd99fd0f05c8181", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1213", "a00260.html#a23b3e704539c420ead0fca0a1f40f8a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1214", "a00260.html#adaff15e58d81f1a064928da46c6e6887", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1215", "a00260.html#a54234585d54efe1063b24934a720bbed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1216", "a00260.html#a79e5f484bc452c471b1e39dc09589589", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1217", "a00260.html#ad7b2a8106ac8a8bcfad7f638d9928ae8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1218", "a00260.html#acd3e93e46bd0627f9931bf6ae5d0eb4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1219", "a00260.html#aba9adcd015bff43e05ff8a372ad88138", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1220", "a00260.html#ae0b9d242c6e1c4474ba84633b2bbd24b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1221", "a00260.html#a898080140196c699a6254eec5913b58a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1222", "a00260.html#ada49b3f93342bd92c925a53a21a57283", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1223", "a00260.html#a6a5f791b7329f933e05c5a172c9daee9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1224", "a00260.html#a966f7dd4dfcdceeaf644862478e24bd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1225", "a00260.html#a28be8f3d5486a1c5c7eb19c51adf6d53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1226", "a00260.html#ae4f31a85800d3165e5f7e2b00fb7f7a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1227", "a00260.html#adaee6a07a2c6c44aaa6023b2bddbcb2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1228", "a00260.html#aa23d7d432c8cfef45189fe0bdcfe52cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1229", "a00260.html#a5ee8d1720f75750dcd7d0ba58145f4a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1230", "a00260.html#a9a94bf8572a84bc479f30bf6050c92d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1231", "a00260.html#af37caa8bfcb8c83962f148626f762e53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1232", "a00260.html#a52767b66ca934d179ca5eda5e6f701a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1233", "a00260.html#af83fdd693571e79ca817d8ddf1dd9552", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1234", "a00260.html#a498d31243efe01d6ad715a5d0e2ec3d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1235", "a00260.html#ae06109f2cdb1bf841cce1bd8e53bd3dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1236", "a00260.html#aec3d449e14957e890bb935f83515d52f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1237", "a00260.html#ac722b257558208269ee9d69b08b1aa00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1238", "a00260.html#af2ec5670430d467b5e81756c8f34aa29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1239", "a00260.html#a37c762adfd02cb87d5265b0ad912f139", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1240", "a00260.html#a45877e8a8d7499db792704be9c8609a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1241", "a00260.html#acb0e44711de25fb7a984acf8fa4c2dc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1242", "a00260.html#a49c687cefc578e724cbba04dbc9891b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1243", "a00260.html#af18118645c3e710e3a60afc0ec644139", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1244", "a00260.html#a81662bedd8634bf6731905ed5123787f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1245", "a00260.html#ab44227917da0377158ba5c159af933b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1246", "a00260.html#a00f6994d49b7bff9f7e3fdf7fb757cd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1247", "a00260.html#a2fa7f0b81a589de4c8e4f361496d977b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1248", "a00260.html#a68898f07ddf698c89d55d6fae4149f97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1249", "a00260.html#a91fd868084d39fda7904791a81ac2da7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1250", "a00260.html#ae3463392669e9b780f0eedf4b1f1de29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1251", "a00260.html#a550f85111a097e5a74994e83d9e4139b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1252", "a00260.html#ae72c5655ae95f2189efc77dbc238448e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1253", "a00260.html#ad7de2153adb46b9bf575484e6a2832d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1254", "a00260.html#adcd5aa889400bdf90a4cddedb8dc917b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1255", "a00260.html#a00069954d539e262e90a5190517e1283", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1256", "a00260.html#a2dd0555a82cf80208e99ce2f22f79f2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1257", "a00260.html#a9a8bb6b46c9d67953c7151e28cc83e40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1258", "a00260.html#abe8cb617db7e481e9806c15fb9efafd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1259", "a00260.html#a9ad1bfc31d03e68743f539f8631aadbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1260", "a00260.html#aee0584f0ef8c8c18c50460fe86065b6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1261", "a00260.html#aad55e277794688ffc045d320270e0263", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1262", "a00260.html#a9106260dc5eb90d73e31937578234160", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1263", "a00260.html#aedf1c4e7886c16cb4919b9a11356f866", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1264", "a00260.html#a27a2a10aa678db6d5a2cb80f41aad43a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1265", "a00260.html#ab3194e1e627e14a6d78ed8765b60aac2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1266", "a00260.html#a28ec5f0b10447857f338deedbca61cc6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1267", "a00260.html#a0efcac7689f67e6be21f5b3c09784838", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1268", "a00260.html#ac350945979e7c59945cb100ef475241f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1269", "a00260.html#a5849703f63fab954c0bf0ad90ca2f6f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1270", "a00260.html#adabdca657faedf933bbd81e3b9d5ff4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1271", "a00260.html#a0d6ae135c4e14be6c43bb9c9ab908810", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1272", "a00260.html#aca5cc256eac1796849df512e5c772f4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1273", "a00260.html#a8b6ea081c2cc28fc79b7fb2202ec2c18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1274", "a00260.html#af6ae1c3d2f4d7fa7016c8c4b757f7159", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1275", "a00260.html#a7a88eb8fc0ae5144b009ea22d17e233d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1276", "a00260.html#a4ed5fbd0625ba9bcf7d7e9d5bb45d09b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1277", "a00260.html#a7fb5c9590488348de058f2c2b9f0c731", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1278", "a00260.html#a267108e3ce56dd5072a4bccc844117b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1279", "a00260.html#a0ef56b8566f1c8eef3b50719d9d20a09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1280", "a00260.html#a235dbe6f60fc10ed58ae179f50f968af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1281", "a00260.html#a8b406a7fc83a0ac3effa73b9f5c6ec00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1282", "a00260.html#a9257f59f86c856569cf07ae289f5d51f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1283", "a00260.html#a92e6a36160e23cf0871153a09a01682d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1284", "a00260.html#a191558375ad1ada1ca511fb5af1d6127", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1285", "a00260.html#a394fa4c0d511fe9f60e5122175f2a4c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1286", "a00260.html#ab4408295c2b76a3b55eca31580ada6ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1287", "a00260.html#aa191980d588277fab728fa4f83598c04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1288", "a00260.html#aae7c156f96b842e8d413e267b7a85665", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1289", "a00260.html#a8d2a84c39c49a29d9e1a976e6d0826e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1290", "a00260.html#aa5708f60fbb313f4f67e6bd4390dfe02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1291", "a00260.html#abc9be31408aeef8fbed2e7eadadf7d78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1292", "a00260.html#a9d5519b8dadf2c2a5422b7636e395b90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1293", "a00260.html#aba476d2e47bfdb6797f0dc05d34812b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1294", "a00260.html#a9f57cecc27c2e8a6d0f7dc0157a27fb4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1295", "a00260.html#a7d79069c393ed30c78f5e218a34e7ab8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1296", "a00260.html#a41c69e0026380386d09fe80a74e3e7fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1297", "a00260.html#a331bf4926bc449a1d3b758663919df44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1298", "a00260.html#a3a67e265c8bccf109a427f366095db4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1299", "a00260.html#a91ce65ff196a5c75d2151b73f2546a20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1300", "a00260.html#a75da5234d16626eed7aca11f1820ec41", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1301", "a00260.html#af527ead712b9502fe562be3d486ffb8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1302", "a00260.html#aa45e44ec311ba0fea515886490bcfba0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1303", "a00260.html#aca2efb40d652db916be675ae6a5c3e68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1304", "a00260.html#a9faeefa0a9516e5ba9e887d7587e17e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1305", "a00260.html#af5220413e70e964b13962218b46e4e42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1306", "a00260.html#aa8e3a6f8d61843d9867aec15b4a98598", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1307", "a00260.html#a2d6eb4afcbddb1e1f2b8e1de93a6bccb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1308", "a00260.html#aa002349be6d49a73c6a861ea19993fe7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1309", "a00260.html#a423b164bc3a525007951775afa5fbd5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1310", "a00260.html#aca44188bfa9a230463048dcd275eeb25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1311", "a00260.html#a2f524ba3848faa9b4fd2d3c6756a2ab3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1312", "a00260.html#afc7ddbd32a2183f80c4c85ca4b7b5820", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1313", "a00260.html#a7892506a9ae3625543ec168b9f2ad798", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1314", "a00260.html#aadd57dfc79918c45d947dbfb9b83a596", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1315", "a00260.html#a5b13fb8ad3ae31b39dbe7743b4d7c9f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1316", "a00260.html#acd462a7f9f3c555d2a576eb65b27dc82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1317", "a00260.html#a6170f7b9d89aca2cf83c839ea839a377", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1318", "a00260.html#a822eeadebe4eaf95500a87f115fb9b2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1319", "a00260.html#ae6155b14cada1238532e2959d2f40bce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1320", "a00260.html#a91150f824072a5b517af1ce83d0bbf10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1321", "a00260.html#a857158a0df849e112d64fe555d826f59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1322", "a00260.html#a5082d5fdb539f5f4078e6e1819204972", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1323", "a00260.html#a0162ccb374ac53ba7e95c0cf2d3b4f9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1324", "a00260.html#a4e958fdf381e789b9a6e9b3d60913d4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1325", "a00260.html#a45540f8db0de93b677222a49982ae8f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1326", "a00260.html#adc028ce219263d8720e37d8cfee5ad48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1327", "a00260.html#a6cc05e875bf16e3bc78e6466f77e0aa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1328", "a00260.html#a8c6e5589f3df9a67e143a2ad11489b44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1329", "a00260.html#a2b11c2ed9703020a02b2dddeeae68a8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1330", "a00260.html#afd3f0d85c64e1c5e070712e895069d85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1331", "a00260.html#a5107b795a731f66271b9413772205de2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1332", "a00260.html#a9709d613d4fad6999aeafdf8594859f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1333", "a00260.html#ac26376b8041f8b51fe467e81512d8421", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1334", "a00260.html#a6f363c46552d5cc7504506c8cc89a4f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1335", "a00260.html#a60a3a6d91bcb7ec9d9668a5a59b5324c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1336", "a00260.html#ad72d50c30e3ab3fae66d44197f13f811", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1337", "a00260.html#a057dc615efc77b4400ee63fd959c3900", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1338", "a00260.html#accd1a212a427bc6cc80d2e91881adfc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1339", "a00260.html#ab6e246b5699a804497d3a3796b7dbbe8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1340", "a00260.html#a222c028c0df7e20ce0e3b764452f04c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1341", "a00260.html#a553a437a01d2421efa904e228ff74fca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1342", "a00260.html#a399b16799c458d6c34a81d36f87543ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1343", "a00260.html#a2692d6e82338a85c15066e3f479b53fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1344", "a00260.html#ae319e6f4409432bcccf9b399aa266164", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1345", "a00260.html#a98a44d49211628ce7dc97dffb47c0984", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1346", "a00260.html#aa5b237d9d12763bc03536e20f96860cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1347", "a00260.html#aa270b762f7a8e0399fa321cc2158ca8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1348", "a00260.html#ae7d23b27471362baff96a569e2a55ad1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1349", "a00260.html#acdd024517c2c331c20449cb29860c4b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1350", "a00260.html#a50f28df9eb05d2db3f13a813f17b5eba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1351", "a00260.html#adb4009b69d5b220c87a954c69b832073", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1352", "a00260.html#a3b155cc53154897b23d317e6e76f89a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1353", "a00260.html#ae04b1218ea8efbe0b3e30267bb4b1ec7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1354", "a00260.html#a69d787aef7ac36a7e148c4829c7aa2c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1355", "a00260.html#a4c3db439dd954262156175347e6911cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1356", "a00260.html#a2411f4bd00b3548ee1bce6c092032b85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1357", "a00260.html#a14ed4526b0b058e34b5136c5b8e80ad1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1358", "a00260.html#ad3811ea63872a29f3d82b35b71c02bab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1359", "a00260.html#a564f5d374e509670488320b85d00abc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1360", "a00260.html#ad0437723532529d58e0412710f7f236a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1361", "a00260.html#a71be4da99988c16a9441e396cb860471", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1362", "a00260.html#a18df70d6dab5ecedece0f02e1d75c4ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1363", "a00260.html#af3d0cdde535941aeda06383998aefd12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1364", "a00260.html#ae2f52bec45b97b1d8d6e7919c407837d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1365", "a00260.html#a7e6bd69990f02334c73b602eb82f9b69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1366", "a00260.html#aa324143e3466e12725f70f77a4266290", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1367", "a00260.html#a4f4667e4ad2ff79353b81f0a10812ba8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1368", "a00260.html#a507ec11b5b146cf9d96b14128472e509", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1369", "a00260.html#a23fab464a3012fa016bb1414ba908d0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1370", "a00260.html#a95f6852f20b653744ad832823256966f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1371", "a00260.html#aa922a0f5b83ce25eb18ce64604642591", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1372", "a00260.html#a04727a657cbcd32ddbe28751397be186", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1373", "a00260.html#a19ea538b76e278c3a5d914f4d0ac1b03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1374", "a00260.html#a72c3fe7e4cc5703e418f482b9ec39eed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1375", "a00260.html#a43c7ea4c790dc908022ad4bb2aae1c66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1376", "a00260.html#ab4bb5a26bbd4c207c4b19ef6fe186340", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1377", "a00260.html#a4da94350652491d40fbf275861eaad57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1378", "a00260.html#a9c106a9ded499bca18e839568ec0f6ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1379", "a00260.html#aca4c36875cf66cee70a5a5d473479185", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1380", "a00260.html#acd1604188e210e2687707730aa85e099", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1381", "a00260.html#a4f447fa1b36566a8d468e5ada7f35d20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1382", "a00260.html#af1d635b1104e16ec59f87179229500ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1383", "a00260.html#a4966af2041d3a2bdb8c5adf7061d9df9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1384", "a00260.html#a5308c9aa0d8cd01d4c3344cf84858bd4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1385", "a00260.html#a83a517ca98a8ab6aec188d8853bb5d1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1386", "a00260.html#a0b829ef43c1022596c7417499dd0e132", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1387", "a00260.html#a1acc9c0ff197c7ea149cf3ab409793f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1388", "a00260.html#aa876b74a4ec05f3ba9bca5e039d25b80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1389", "a00260.html#aca943bedd308a9a2df3cabd767f5078d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1390", "a00260.html#a9d03f160f5e4aa8980282300cf8c0382", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1391", "a00260.html#a1de3d34807d70b74846ff95dad960350", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1392", "a00260.html#a4267c7041cefba6b75e14833370368a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1393", "a00260.html#a6c6ee211398a8a3e93bd1acb995151d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1394", "a00260.html#adc5f7b3293292087837db60c363e35e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1395", "a00260.html#a453c763892228dcb385500e133356e6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1396", "a00260.html#a3832c80ab590fdac947de8dd28edc281", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1397", "a00260.html#a76e0587da752f2b8dffef7049a9960ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1398", "a00260.html#a14c1c169217f2e489552eeecd13c40fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1399", "a00260.html#a770a75506f0bbb5f8988a15b0bf18359", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1400", "a00260.html#ad1e59124cfe7fd047eb813342bb8cad3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1401", "a00260.html#a503ba583327d4a6385def64f72f10b1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1402", "a00260.html#af45899f4f084e0657cf2df9d06a84ff8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1403", "a00260.html#afec92e9245f5feca1f6738823918e4fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1404", "a00260.html#af1c95b10b49606a0e71787501e614fce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1405", "a00260.html#a059349f99c70d3bb6968e18b4d4b70b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1406", "a00260.html#a0b9e4c875725efa97c5f394742ff1fb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1407", "a00260.html#afc7b9da7ead5f11914ff53a4f8180e61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1408", "a00260.html#adb737ea51900e61c304b7a52d9e9a7ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1409", "a00260.html#a585c7c453c8e5881c8e228f1acc3bc54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1410", "a00260.html#a0270ca482bcbd0749cc069a7ea842748", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1411", "a00260.html#a3447512d59afc44ecbf1e448e895c602", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1412", "a00260.html#ab153599ee09c71b35078b7e2893cb0d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1413", "a00260.html#a53cc96918c5b8a4606231018264bf220", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1414", "a00260.html#ad702af593127e6337c772f7dfb676430", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1415", "a00260.html#a8cf26f55cbd8e01fec27aec1c65df037", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1416", "a00260.html#ae577bbf24c5177062082d6d2a907394d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1417", "a00260.html#a50da5cabc8bda0f243d0f3b8de7e78d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1418", "a00260.html#a329f9d662a009368534a1ce7cd78b4bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1419", "a00260.html#a81e7f988ff6bee47663e8716e45958fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1420", "a00260.html#a5037cb55b4b7de1b5df863b480e28d30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1421", "a00260.html#a879e8b10d2ef809c467bdf596470c53f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1422", "a00260.html#adb61d2c3467c95b9cb94d3ff054c7c77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1423", "a00260.html#a2b1b59706c738979406e8171283c4240", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1424", "a00260.html#a1a21601efe20abab5245ce20c9bff40a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1425", "a00260.html#aea6087b44bb24f787c30c9eac2ce389f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1426", "a00260.html#a618d5a3d3c779fa85ed98e7b82ef8fbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1427", "a00260.html#aa07edfc0f18047c08941916f439a138e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1428", "a00260.html#a5c268e3c42a0cda7db0181c51329644f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1429", "a00260.html#a76a486895ed4cf0d75f5d01d81b4b431", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1430", "a00260.html#a14e230311b695d1e3e9ea15daea4a0b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1431", "a00260.html#ac5d7d31b9b35e472a8eb10e3e95fecce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1432", "a00260.html#af7b6bcfac92fd5b6d87b19f883dbce94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1433", "a00260.html#a0cf61b25beaeaf4d4eb792f346716b2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1434", "a00260.html#a36d125fa38eeb2d67638403d09ea211a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1435", "a00260.html#afc814ee545ea3abe0a5da47eec515a23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1436", "a00260.html#a8ab16570100410b6c0cfa7fdfe5784cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1437", "a00260.html#ad3a671886a0fdaa74a94f08494d5f559", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1438", "a00260.html#a5c751ff58f3640ed7d44c682abbaf391", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1439", "a00260.html#a7415024145e0954ab3e53c190a5e7c4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1440", "a00260.html#a5abadd48afff69ce76acbbcc22e34989", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1441", "a00260.html#a05a30667998f3e619a2c5bed29a239c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1442", "a00260.html#a2667693c867c8f43ab6c8812ce1c51bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1443", "a00260.html#aa89e49a708510750e50ddf9b57be9980", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1444", "a00260.html#ac280c50f50a793b9ba2647101fc8ba6b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1445", "a00260.html#aeb548bd28df33f92b223482aa0a34a69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1446", "a00260.html#a53f85b53b488b6591380ec39e2d55877", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1447", "a00260.html#af3e80f5cea7d9f8577f3833e59ba9162", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1448", "a00260.html#a34b09e0a6ade4911e3bdbcbbc5146830", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1449", "a00260.html#a583ea237d766eb626102d003cf77b035", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1450", "a00260.html#a946bcba827bbf7c4eb66b7e1bc53e9fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1451", "a00260.html#a8b2cac18ebbe0f02a066d4931131f2b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1452", "a00260.html#a6c346fc40a70cac316165a1966a7c562", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1453", "a00260.html#a1fa9c67e911b2442dca8ace2741390fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1454", "a00260.html#a509f49b87fef1890f99633411b2e9d50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1455", "a00260.html#ac486ba931eca7bf4047d70639d1acdcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1456", "a00260.html#a4147a1d3ace22e281e1fffe68a227e34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1457", "a00260.html#abae0384b85c8e3546465c13fee5b06f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1458", "a00260.html#ad7a43fbb3101defe7cbfd77391981cdc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1459", "a00260.html#a625bc1f8d65074e656b2bec4ef767729", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1460", "a00260.html#a208a3ce88964a2ba5e8f733d93a6ce2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1461", "a00260.html#a98c3771e750a4739757df7cd791e7e13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1462", "a00260.html#afa6d5037de9901449b3c098ec26fbb0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1463", "a00260.html#a75611e4f54d02ee6dd636e53059422d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1464", "a00260.html#aa02e39f637c1ee3332b3d81d32f152f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1465", "a00260.html#af3e687edd65b034fbd32ba7e4dd3d2a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1466", "a00260.html#a57e6c755f8757a5a0becb87269b01466", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1467", "a00260.html#a4825265c709ddd095bb52bd368afca63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1468", "a00260.html#abaf803e848f0a960b21c220e16217516", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1469", "a00260.html#a08888e252e0b98da6894115e0e2cf84e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1470", "a00260.html#a11022942345033aea2b7b9c34dbcd465", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1471", "a00260.html#a377ce81ae1d87142cb3cdad76b40d744", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1472", "a00260.html#a05f516710eea66cb5d533346883f004a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1473", "a00260.html#a12514b3ebd81843399c1b486f79ed121", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1474", "a00260.html#ae9f8c3db1a28c74ff2cb6fdf80841cd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1475", "a00260.html#af4212f55cf7405965e112605fdb412e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1476", "a00260.html#a63fc9e42b8580e45a87a47298d5a625e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1477", "a00260.html#a2c365cd7d7d049bfaef269c8abd2aff3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1478", "a00260.html#a99b3ef65abb6d46bc5fb87fdd4c51b29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1479", "a00260.html#acba5e4684e6a1c6e11387fab31e7d22d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1480", "a00260.html#a8360379c135ddac62186793a0d479745", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1481", "a00260.html#a33983ea96fd1ab34d9c2f893fb631a8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1482", "a00260.html#abf4c546e9d0ed466dde730ecd16e7e63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1483", "a00260.html#adbc6e832660a9463373c017f2f2f1c7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1484", "a00260.html#abf131033f03ecd43c73f2f2c50553c5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1485", "a00260.html#aee2fd50478273ad9e61c7a073f389db8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1486", "a00260.html#a0e2d8afbc208794e4604bee4fd090f84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1487", "a00260.html#a1d7f2d9de857c6b2e06611013b271bf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1488", "a00260.html#ab2a50352dcb15416b7ac23c0fe80e7a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1489", "a00260.html#a3b13083eb0bcaf366e5d74064b5fc4f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1490", "a00260.html#a0a6cd5ec9052ac9331df4517ae62a8cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1491", "a00260.html#ac891516880406b5b356bdbf0d5950dd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1492", "a00260.html#adf402c65e595d139d90447565a007fd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1493", "a00260.html#a4ec9bd6b4a705a6dd51fd8bbdcc5dab5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1494", "a00260.html#a167555b38f4b2bd3eda323e96719c867", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1495", "a00260.html#a8f79f2b2b9b72fb8fd7fe3eed012904b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1496", "a00260.html#a41c633e23c34ba2fce96c5b85cc8422a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1497", "a00260.html#a45c321cfd69dddb3b938bc9c290c3598", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1498", "a00260.html#af8c5e3308133f9dcecea941d6039ec38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1499", "a00260.html#a4ab5817900d364edac21beccb74f77c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1500", "a00260.html#a9d09a2c8be75c6db0f5ed5d484df7b1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1501", "a00260.html#aee242ac2c85dae6947ef444cee3e3647", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1502", "a00260.html#ad1e14cb556fcec6e0780d61eab1ef449", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1503", "a00260.html#a6bb632523a878ce2fca44cc43a39a53e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1504", "a00260.html#aef35fbb26a3fa73a4fdf6155aa45c530", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1505", "a00260.html#a73099610bdc528599bc4194a8a3e1a37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1506", "a00260.html#a0cb1eb7a4c19e9610d9dcb12ea1fa543", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1507", "a00260.html#af4d8a8d49ba0342bb03b5f05c8ee86d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1508", "a00260.html#a7692735577908196b1887708d0b255b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1509", "a00260.html#a320a1706d42ed47824d363e4f5d18a66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1510", "a00260.html#a1e476d7854d93179546158ce3126b1cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1511", "a00260.html#abe96f928967ae37b0357d297bf9c7141", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1512", "a00260.html#afbee7262cfdd983050d71276c2601c4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1513", "a00260.html#a2aa5a857efb43cca41ba1ff083dabf7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1514", "a00260.html#aa3e41632ba5055dec6b29921c04dde13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1515", "a00260.html#ab152cffd5eed4e2883d78ff49fa73e7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1516", "a00260.html#ac7e8261c48d03c4c396a5d252042af3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1517", "a00260.html#a55dc7dc0ee9a162e27630095fdca9dbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1518", "a00260.html#a44f0caa51e99405ec0941c20a13c25a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1519", "a00260.html#a7cf7336f3ff07528dafa74f270293b05", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1520", "a00260.html#a0c80243c1c45c258b4298259cf19e30e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1521", "a00260.html#a3b4f7315d322b07568e8fe74895e2d12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1522", "a00260.html#a41c4cf2d23edc8127b5c3f3c6aaaef4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1523", "a00260.html#a742e28b7f10af4894319673031237334", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1524", "a00260.html#a3c72d43c0847c4f8e2df32ca6610fff8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1525", "a00260.html#a229daa67672cd971d4724e326d37ea23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1526", "a00260.html#a831597ece4c302f4b4aeb93b90af0350", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1527", "a00260.html#ab8dd76b8ac2a23e425eea20f701b51f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1528", "a00260.html#a2a9132dbf991fd2ed27e929b815b8100", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1529", "a00260.html#ad47fd2c4190bf1efb1b103ad54f5eaa2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1530", "a00260.html#ac66ea8fd9a7dd37540cbaa972dd2a7e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1531", "a00260.html#a75867b1e32a053f2a0c95d20ac981e4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1532", "a00260.html#aeb434a4ca69636a32d1a79e214607342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1533", "a00260.html#a7c62289fa7f1236125d783be3446533a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1534", "a00260.html#a518081a5832e06443a061df4cf5b6815", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1535", "a00260.html#aefabde031310a9f5b6a19ca0ab7094c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1536", "a00260.html#a9df09b83f9dc9e08386643beeb089781", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1537", "a00260.html#a9ae86a7dfc64698fc85cf91fec44ce01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1538", "a00260.html#a8dab0a34c9564a3c785e85f5dd7197ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1539", "a00260.html#a6a7e3e70ca9c93761579f55d55c17698", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1540", "a00260.html#acdde03f9b8b3b845050e543cdc49d922", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1541", "a00260.html#a4342ac52e50694e659b29f6025201853", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1542", "a00260.html#a5832189d68df7b059187e37331fde12f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1543", "a00260.html#acccbe7ad29a831dd4f07ba2a7a722ae5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1544", "a00260.html#a31e60a24a0252b9a648ddb51b5f837b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1545", "a00260.html#ac632882b80e894c1e08b312cf38a459a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1546", "a00260.html#a80a455798f594d78adca271ec3969b57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1547", "a00260.html#a77ca5d95faa8219b636d01a2244b3aaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1548", "a00260.html#a74eeee4e63f308c8df2d60dda45c8d2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1549", "a00260.html#a5122de1562a545f592d8aa97383fbc48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1550", "a00260.html#adc9b7debde5be76920a2b937b4f403f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1551", "a00260.html#a30e85dac5f50485be1b05a2c69f871e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1552", "a00260.html#a4a1c4218afc347e4d251a76a283a0ab0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1553", "a00260.html#a233729be49b3f30f38ed373f4304e25a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1554", "a00260.html#a03533d615adb189fb43c3a584f724649", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1555", "a00260.html#a4dbb45c829865ce058b209614299b05b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1556", "a00260.html#a8cd1892536aa90d0aa660d09411bf1ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1557", "a00260.html#a4fd7b69059676dc778a8938a508c2262", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1558", "a00260.html#a91c6f3d5140a5c4bc680edc9b7e72e07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1559", "a00260.html#a6fa01512467d3af4be95be0d68a00ac9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1560", "a00260.html#a3f143dc33d2e980add3b762bf1b100a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1561", "a00260.html#aade18c697166f5234634e0dfcdb3b547", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1562", "a00260.html#a0dc5c5f451b4f59afa5fcd85aebb24e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1563", "a00260.html#a570e7199d8245701eaffe9510ee08764", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1564", "a00260.html#aebe7b2c50a0427c3a1c08428c4a97af8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1565", "a00260.html#a36123ef4679adb88866a0155694ee15a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1566", "a00260.html#ab6cd14fafd65603750e26c048e217a1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1567", "a00260.html#ad76553dc2d76c4568b446f28dcb808cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1568", "a00260.html#ab663920ea48955c675a61a4e49f42252", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1569", "a00260.html#af975ccdb8774b87be30c5f731ae0334d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1570", "a00260.html#aaa5335e471a507ee5a136288c642b092", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1571", "a00260.html#adbda3ce982a6f5afe8168a8c12b6fbfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1572", "a00260.html#aea7d61d4f159e0c1e3796c67202d69de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1573", "a00260.html#ae7383dddf3297da05d52cf3f6f8284a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1574", "a00260.html#aafe05f9b5f6f1ff2079ce843c1d56736", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1575", "a00260.html#a5f7318ed3e9b2ff5a1afe8b17b29e0de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1576", "a00260.html#aff57fddbdb68ff8e0b2682606674829d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1577", "a00260.html#abbcfec72914e2caf9cd3237c5148be2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1578", "a00260.html#a69a85cb1bc27e895f9039a65272f3762", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1579", "a00260.html#a79a36b58546a1863b579c2959f9b8bd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1580", "a00260.html#aec332b6c22e31d90502b551764f9d8ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1581", "a00260.html#adf5ca998dbe9074b6a7d338e287112ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1582", "a00260.html#af7c6ed4ba98c37c8848c8d34db9d8859", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1583", "a00260.html#af73171fb6dd266b2708b53860cf646e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1584", "a00260.html#af5e92c361b5e4e0d0bb4f1353fcfacc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1585", "a00260.html#ac346688e1bfc695934bf5222c408ee88", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1586", "a00260.html#a0bb151dd478f2bf528a0a1202f969fe3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1587", "a00260.html#a5cbfb8e27cdb9b5bbcd58eb28846641c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1588", "a00260.html#a3406feae27fca28ba258251f82589058", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1589", "a00260.html#ab899b5a3c5c142587fa5b23fc3f9172a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1590", "a00260.html#aca880fc615c75c66e1bfae2c8dc3e68a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1591", "a00260.html#add130bffe68686aa0dbbb67fd76658fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1592", "a00260.html#abb10d5ce07632560bca3bfcd3c68b7ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1593", "a00260.html#a8c877117fd662ceef23f35c24a83e7f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1594", "a00260.html#a34d69ddf7aeac437f5777232f6de9561", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1595", "a00260.html#ad90a2039b354e9aa6f45735ccc47e447", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1596", "a00260.html#ac4931dce37fd5ce4a26dd129f6132097", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1597", "a00260.html#aaaa7843d6995b7a5bc016c7c52d6c081", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1598", "a00260.html#ab4ad9438e49defd57936fb804b3d0703", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1599", "a00260.html#aa489574322f69af39286fa365619a6c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1600", "a00260.html#a96ae4b76338adbfb245118a9e1fd5b6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1601", "a00260.html#a93a6944627a270457fb2dd78abde381b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1602", "a00260.html#af5d22be76fcc36647154654c07bba01e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1603", "a00260.html#afccab70206ae08dac9d8a0780c70ecd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1604", "a00260.html#af9ddd94153c1c7b986eb793879f64c8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1605", "a00260.html#a33dc31ca963728abf1385f17031d6e73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1606", "a00260.html#a0bfc020fb9bf3ce5932e0bfdf14aa979", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1607", "a00260.html#ab57fbdefa910a449c334ac940f72cc25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1608", "a00260.html#a5e63ccfbd179bb0c84e9b03d65724f5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1609", "a00260.html#a05bcbbfb65b644aa796f6ce2f192ac97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1610", "a00260.html#aa9bd16a7dee48a90d2aa109c0b20b5f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1611", "a00260.html#a07e5913cfb54a3c648911ec5a128876d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1612", "a00260.html#a0a45fcc2a3d2ded38e9302a994582503", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1613", "a00260.html#acc4c8339950827f958fd0ec734e6de3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1614", "a00260.html#aeaf0e177b472d6a8567f03130081f8a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1615", "a00260.html#a61603804213a89b62fcf9cb5e482e858", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1616", "a00260.html#aa5fe3f7b8b3f341dc7978efef3785047", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1617", "a00260.html#ad1f691c95ba37488fd00a51097fd6ba1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1618", "a00260.html#a1c796606f8b4dab5206d1d641adf9ad2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1619", "a00260.html#a1488484c97260b02973378c7a34d14ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1620", "a00260.html#a0ac0de2ada1827340a3d71dd661f653d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1621", "a00260.html#a69a6000c1a52508fb4af215e11c270d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1622", "a00260.html#af12c31dc4852048dea4d9ed53b8eb40d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1623", "a00260.html#afa4c88e7cf81dbd713ecc05525038d10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1624", "a00260.html#a5a55b94016864e5f9a56550dc623e928", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1625", "a00260.html#a69f3a66429516c3e118d43c679a6ae82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1626", "a00260.html#a2ac2dca238065183100930de2269e123", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1627", "a00260.html#a63a74cccc75d12624adbd3b9ca1ead97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1628", "a00260.html#aa07905d3e1e9afe8e9e03c35ba2b26eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1629", "a00260.html#a829eacd5beb9ceabdec96502e5fdbe6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1630", "a00260.html#a493b7dac970a99719db7abc8605690c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1631", "a00260.html#a17e75a467b9aabb5c245989ffe895794", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1632", "a00260.html#a1042373faadc604bb5afeff1408774ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1633", "a00260.html#ac5ed1a55f56d25a45722776ea7e8e757", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1634", "a00260.html#ae8183a0d09912eac9b182a105de2938d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1635", "a00260.html#afe66428e84944db02be8dd8c2c797343", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1636", "a00260.html#a3ba8f166036d20f2ca90491ef963bb23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1637", "a00260.html#a8eb4fef95bb0ce74c21573335eae06e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1638", "a00260.html#ae3855d84c5fa2218ebd6b96afb47f4d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1639", "a00260.html#aaff30bffcf8640bb4999965ae0539449", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1640", "a00260.html#a94ebd3d796820f055e35bb17b1adb6f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1641", "a00260.html#a83f78c6bbb23f466c80ffc465e35151f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1642", "a00260.html#aeb245f7efec6a5590bf72ca76aa44574", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1643", "a00260.html#a9bc4f3a14d05e6040b5ab7926a096519", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1644", "a00260.html#afd6c75f5654e275e6c0216fbd026af8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1645", "a00260.html#aadfc4eb1f53cf0598ff1bb1eb39b2a31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1646", "a00260.html#ad2bade931c6a34360ea302a6c4e0f240", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1647", "a00260.html#a1696a5d598c8f45c32fd2b31ceddfba3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1648", "a00260.html#a7e1bb6a942847aa09fa87330fe68435b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1649", "a00260.html#a76cc4456a2c65f8d69f428eee24b23b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1650", "a00260.html#a6fc5d4b83dd3782276f575efba699e26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1651", "a00260.html#a49af29ee2a9b8429fefc894390f68a25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1652", "a00260.html#ad67b9d83588bd24a4082d2cb941060b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1653", "a00260.html#a9558969d534b35bd82bc8bfbde3a9949", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1654", "a00260.html#afad10c0f8e96f6a0c7e2d0bdcdac4a71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1655", "a00260.html#a7aa3a70a1ea13de244ebf48842edfc60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1656", "a00260.html#a70ba6765912741e7fa81acf8c6ebc917", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1657", "a00260.html#aa92646405dd4446b2c82cdf099388a6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1658", "a00260.html#ad5c64131711dce60fbfbfc6d9b75e651", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1659", "a00260.html#ae668eb01a25ae09e3d91db02a6ac0fce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1660", "a00260.html#aeb69f8e9fea0c6befa5713cc7f753c2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1661", "a00260.html#a3da20664d9776eb0a27c1c02b984d0b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1662", "a00260.html#a8902ca0a8170fc6dce8aa8de064fca20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1663", "a00260.html#a913c46f5ea81b5fbf99d6b6775ec3b24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1664", "a00260.html#ac9b8498e744328e4581f15b698f2015d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1665", "a00260.html#a7afb306a331d80d671a2bf5b6de81600", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1666", "a00260.html#a7bcef531633eb99c72a4cd2cdc739a8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1667", "a00260.html#aa217c85ec391b659481e81ca03b0d8c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1668", "a00260.html#a3153b7541df3eb4a780ca2b17f797a3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1669", "a00260.html#a7f161d823fcd81a23cfbfb8c0cadf01c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1670", "a00260.html#a8755822d147974abfd0fbe2fa3aacac7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1671", "a00260.html#a437c5db7340821f870d3ad2d863d34b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1672", "a00260.html#ada520523b1402c29eba487f358c2454a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1673", "a00260.html#a01f4c0d528e2e73ebdf8b047790b8135", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1674", "a00260.html#a3607de51816e6ce24cde984ad3730bbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1675", "a00260.html#aae327b576f767389f7854806cb1087dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1676", "a00260.html#accf09896c20c41d420ce94f030a85a09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1677", "a00260.html#ac5818b7b305df5a016f077d4b523ed74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1678", "a00260.html#ad8cdebf90a7383c7dd40ac3830485e9b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1679", "a00260.html#a7632a93302cacae1cf23a24a9ff7f932", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1680", "a00260.html#a01fdd2f9d26a697a9727e55303ad24dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1681", "a00260.html#aff6480cfa1bb653558586c4ad16b9e3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1682", "a00260.html#aba4dd6d8994a7a21a3022769b35e3cf5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1683", "a00260.html#a0597489cae3d5b7ed848b7426338ca8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1684", "a00260.html#a48394c9a1ee8a628c3f9f10e3f54d52b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1685", "a00260.html#ac8b89a64eadd6e8c7fe7539eb1f77b5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1686", "a00260.html#a8b05cbd8efd0302060bd68864e17684f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1687", "a00260.html#a489f2c23ad895a2391c61ac407b7e2fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1688", "a00260.html#a6539596d87face352f90b6d7ce849e7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1689", "a00260.html#a4fc28de52a03b9f81262ebec7383370c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1690", "a00260.html#a952c3cea73f639cb9adc9a2b0a5d22a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1691", "a00260.html#adb88abe46aac47c14e44541155b731da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1692", "a00260.html#a5620d3972c229f6107c0dffa74e07f98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1693", "a00260.html#aa459bca09e7e173b0d3d15db355c8853", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1694", "a00260.html#ab0615c97087a40ec14cf3d0e60877e5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1695", "a00260.html#aca11cab2dc25324ac02f3a7e2a4c95ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1696", "a00260.html#a892926f75d125e64616599d1b321a523", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1697", "a00260.html#a0a7d35de6ab55e5f47f6815639d0fd61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1698", "a00260.html#ab13e60e9abca1b9e16ecde58c2d16e79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1699", "a00260.html#a4fe80bf63299b584d3a08471a0ef2c6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1700", "a00260.html#a3d1805460087b8553ef5ff2492939835", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1701", "a00260.html#a5202db505f91fd30974a4f05fa4b7d30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1702", "a00260.html#a283dd60cea377c06379e5b6bb197d0a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1703", "a00260.html#a2455dbe775e580f7c01e668333fa0247", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1704", "a00260.html#a28ff108f7f1c90bd5485cc7abbe0fb03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1705", "a00260.html#afafd4c4c808be184b9f8285967dc3162", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1706", "a00260.html#a74ead5bfc91faaeca00fde43213fa26f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1707", "a00260.html#a1902fedff8f715ca578f3b758847dd53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1708", "a00260.html#ae1b28d18a192ab2494016082ff4ba7f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1709", "a00260.html#ac7961cb5ff3107fbf6883e580659d887", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1710", "a00260.html#af2ec407ad3cf8705f15b7349f569e4df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1711", "a00260.html#a55fff206f75ce4bb230bd69cdc2d1fe8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1712", "a00260.html#aa11aa4e9a4c719cf021d52daf1b36580", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1713", "a00260.html#a3003dff1a953fa5458f1f931c4724655", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1714", "a00260.html#af70ca4c10231f1e3b800d0e41a2c2451", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1715", "a00260.html#af6adab83af5df4001aae52e7f1299192", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1716", "a00260.html#a2bac74754d830f3aefca8673b6c03c09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1717", "a00260.html#a5ea71ba3ac4505580d7842034b1b61fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1718", "a00260.html#a75ed6775648a318a7a9a10366862fa6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1719", "a00260.html#ac08ea875b897fe80967ca7095eed9474", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1720", "a00260.html#a2bcd76a7887a770db6fe44fd4977abd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1721", "a00260.html#a1985348b3a780b8d8c772cd9a92a571c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1722", "a00260.html#a90deed34b7c7156e1e531333f6124610", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1723", "a00260.html#a8e7498b76d0374af7b29cb1a7eeb6348", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1724", "a00260.html#a9119a73a323892fc27daf9c8cb6d0dfb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1725", "a00260.html#a0d8de062d23589779edbb26481cde160", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1726", "a00260.html#a7cb2f96f0f29b7097ae1784a4170a4c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1727", "a00260.html#afe6fc255b13d678f2614f69523792385", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1728", "a00260.html#a62a0c738df7d02782faa0fb4b8fb7b7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1729", "a00260.html#a6240fd45e8c9bb67921c99564ed4a643", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1730", "a00260.html#a21f1dd0cc678343f37f962d9db8bd8e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1731", "a00260.html#ae82f83d1741dce5e1a36b47d0198c8a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1732", "a00260.html#abd6c3a475688fa492b42fb1979298bfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1733", "a00260.html#a07d89d24363825704447f94cc2dd23a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1734", "a00260.html#a81e20ec380a2c87c31d3d4cde65d8f20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1735", "a00260.html#ad2ceb9e86628a150effd01cd9269d6d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1736", "a00260.html#a8c7fdf53930ed0c5d2e720c9c8cbc187", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1737", "a00260.html#a43da72f6b3d876a6bb8f4c73bb40790d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1738", "a00260.html#abe301c0d1f3c21eaefc7d47c2fa91e07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1739", "a00260.html#a737144458b072ceb039e93cc2c822f01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1740", "a00260.html#ac06db3e8dbd5076c62855e2133bd1123", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1741", "a00260.html#ad3853476a7940965526607964591ec9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1742", "a00260.html#a62ad780dbecdd79a6d510ebd5966cae0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1743", "a00260.html#acdd7cd8dd7af1355e68bb481f9514865", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1744", "a00260.html#af3b048625547d6ecbe6a680e1fa2cb14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1745", "a00260.html#a6cf586fee151831fe71b211f88748061", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1746", "a00260.html#a44bdd26470b3d2a952f986c19ad90059", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1747", "a00260.html#a69d830d6d8108b0daa552da865186741", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1748", "a00260.html#a4e4af2888550604f31477774a4a605f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1749", "a00260.html#a498ebc383cfd87553e738c8fe65bb768", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1750", "a00260.html#ae4357499fd63f7b65231bdd2afed9996", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1751", "a00260.html#aa11506abf26acf229c104ebd9f11c789", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1752", "a00260.html#a158a77d43235a35beff6fb46f964a5ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1753", "a00260.html#a2f13dd3da1c70d07fa9b9fda4a7388a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1754", "a00260.html#a7e6a81b38abf5526e4e728b6caf64281", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1755", "a00260.html#a7ec128ba4cd42b10e63f892d460363d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1756", "a00260.html#ad366f2d4cb2c5658f571658e6a57361a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1757", "a00260.html#abd44b4761ff623928ebe052d8296d673", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1758", "a00260.html#ae40e43ce564f697b235711b577041373", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1759", "a00260.html#a2a84a3761c9c044d56f1a61a314d5b7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1760", "a00260.html#af89b8e7f5ac0dc71b814efa87075b118", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1761", "a00260.html#a4d54fe2e1b3d6c98ad89ebd70f54c41b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1762", "a00260.html#a304290d218f8b88ffe5e4b4fe7f7fb5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1763", "a00260.html#af78f435a9dc1f25bfd8fe8ed18a1f79b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1764", "a00260.html#a598f1fae08d533062e4b0d6b22a923b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1765", "a00260.html#a75bf7c4dd75be248974eb44484a4caa9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1766", "a00260.html#a039b71c15e000cdfaa24dc490dd6d696", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1767", "a00260.html#a307242cfe013fb91eaaf43e5e2b7c639", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1768", "a00260.html#a97dac13f32fc834a3c2b7a9a2c6c34ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1769", "a00260.html#a0f4c2edc06a5139bac6f534279029688", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1770", "a00260.html#a2e4c6e884ad2635da7e1f2af42dccbdb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1771", "a00260.html#a7c758fd622a086b537c5a33f95d7d31c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1772", "a00260.html#afbca0d82ae73cad8aacbbdf69f0d19ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1773", "a00260.html#aab1a44b5a22ec08ef4af31dcc3c68c00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1774", "a00260.html#a1f3a369d5ba26fcbd493302191f69457", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1775", "a00260.html#afbe9603e1c9036cc4674d26eccb04bb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1776", "a00260.html#a4a6e1d233f00954df5efcb7125fb7edb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1777", "a00260.html#aa71f16a049c4498da7d8e2e7124e52d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1778", "a00260.html#add27766c8d9583d494c9069eb861dcb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1779", "a00260.html#afdc7ca0b7f31ba009d3fd9697c53bea4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1780", "a00260.html#a98b3a5f9475fd08752edfc4ad85a6bf2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1781", "a00260.html#a8ed78d8d4377fceaedbf60b14f8c069c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1782", "a00260.html#a7d4b6bff8efa5753d83170a92add0884", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1783", "a00260.html#a59d00f4a57fb9ec39a602d17344302e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1784", "a00260.html#a405d66a69dcd7d83be22b940dab1f2ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1785", "a00260.html#ac9eab8d350f78ca2d2a9bb7640c73b2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1786", "a00260.html#a6efeef729ef6c1e489005df86b396ab9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1787", "a00260.html#ae11b22f6ddaac3c83eb5040eae80e976", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1788", "a00260.html#ae2d550cd4878110879f0406ac61a6115", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1789", "a00260.html#a336f48821bf46e1e968a9bc5239bfdaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1790", "a00260.html#ad62d03a7a828f645cb0677fbca830848", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1791", "a00260.html#ae6b13ee8330dc8deebc06ac4256049a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1792", "a00260.html#a50b8e1c307212cece6276c35f4ebbd22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1793", "a00260.html#a53e4b29ea1012ed7f886d2153c1d49f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1794", "a00260.html#aed049b791014fb40606c5f5de5dd019e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1795", "a00260.html#ac98c5ae1fe98b5596e90f1dd2b90ba9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1796", "a00260.html#adc1dd42f3f566da55afc891206d1b941", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1797", "a00260.html#ad7562ec117c7e8c14a36ca7cb0307504", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1798", "a00260.html#aebe7ea94ebcde6fa5f50f4c680a6ecd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1799", "a00260.html#acbee266fb215bb6986cca1594b068787", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1800", "a00260.html#aa3c67169892f51a2608436bdf0ebee2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1801", "a00260.html#ada14910bc0f77e35dc4a97044195a264", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1802", "a00260.html#a12604909ebeee360f998a23a730eefa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1803", "a00260.html#aaeae8e3ef890b6b03907d50fa5f63525", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1804", "a00260.html#ac3a5ccc877f6ba23457f4a1de2c0e24d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1805", "a00260.html#ad44389a782878ee23bf0ba3a008e6c43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1806", "a00260.html#ae465c9a01db45bf82a9ab8e4a569414a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1807", "a00260.html#acef5049af7acb45937d34a6d3d56a72c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1808", "a00260.html#a488a2e92ab61e26c4c6dc22fbb3561f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1809", "a00260.html#a0bf9e431278baa19ebd36dbcb26ac6b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1810", "a00260.html#a9c168fcda687114df2e616a4dd058163", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1811", "a00260.html#aa8b76cf481068c2199b4ae40d699ad47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1812", "a00260.html#aeb49c65256625cecd1c881fd798d97ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1813", "a00260.html#aa2cfcc7012c19cdd73a241fa9c6134c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1814", "a00260.html#a376fe1d9566608ac92e8a3cdba3b1440", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1815", "a00260.html#af3f00dbe7b4dd21a86daef16dbc72f44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1816", "a00260.html#a265b452e6c1a001d9d50fac66cda55a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1817", "a00260.html#a6c39f6d07b31de3f7c951e7d743b7807", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1818", "a00260.html#a5e6a7267742a28c522c5c0bb1a0886df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1819", "a00260.html#a13f0ec5e6e60c33fe2105da6c51735ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1820", "a00260.html#a51a7eadb774ad062a115d43fc5bd7bc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1821", "a00260.html#aaf44d11fab944d5d8aa4ae7732cfd788", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1822", "a00260.html#a2dab9057970e73a7325530892c422897", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1823", "a00260.html#a0a35add4062239efb603fe10c40348e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1824", "a00260.html#a654e6f2c2b086ce9ff3b25ad86268d9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1825", "a00260.html#ac1c7525ae67138ff9da7b5d5088c10e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1826", "a00260.html#aa9337912813e543e90e90c7432af6237", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1827", "a00260.html#af48a355ced303f47fd4ed3f46cdc0a05", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1828", "a00260.html#a5f44a1f530bdf5e70c680169381ca84e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1829", "a00260.html#a4b70f19757798e422645608b08ff11b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1830", "a00260.html#a3b171956da5b5ad584096e69fd7b4006", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1831", "a00260.html#aa8c05558aa2a21af82286b27c1c25023", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1832", "a00260.html#a25f0a9f4d01de004ce9ad957c655a146", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1833", "a00260.html#a765a9fb4724f3becaaa10806d413796c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1834", "a00260.html#a4ba2e830b0ebabf3a0860cd0ffeb275a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1835", "a00260.html#a3bcc979ff8ec74f88a82650d632361ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1836", "a00260.html#a5c9000c5c7ff6783955f8681efb750ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1837", "a00260.html#ac4ed63bf474e35294b09727cda784458", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1838", "a00260.html#a7fc86002294cd39da91853f40cfb84bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1839", "a00260.html#ad197d80b0699eb6592432182ab81fbfb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1840", "a00260.html#af3d7393c9f475c88e4d3ed10ffb1ec1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1841", "a00260.html#ad07d16638f0781c6edec6e7fb7155064", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1842", "a00260.html#a9a29a162ea9f7ea061037968e86c8421", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1843", "a00260.html#ae3a4f9a1efabb6d2380f1dcd633ffac2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1844", "a00260.html#ad1d9547da61e43472a2128be8a2a8f91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1845", "a00260.html#a32de40ef9ea29380eb69ac87438c42d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1846", "a00260.html#ab2965b9b71f2b466a7905e3df8201a56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1847", "a00260.html#aa29d580bcb005340bc76c8aad2dd2b9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1848", "a00260.html#ac86f6e7bea352477d70cd9e359ff67de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1849", "a00260.html#a89d9d1a1676c12ca76bf42f81eb04c7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1850", "a00260.html#a7025e4aa3ad776b6a1c53b73cda33a5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1851", "a00260.html#ac858b89d100fd877965ea8dc4b25b6f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1852", "a00260.html#a0826fd6a8e4ce3e7ee9d08246defefca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1853", "a00260.html#a3e361f3a39c3be5b5e09e708bc469e4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1854", "a00260.html#a8cc4e9a92763fc170abf6fa8b1597799", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1855", "a00260.html#a0d411d1d75e30df59e29bef8b3372abb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1856", "a00260.html#aa511ac97edc675b7d3d8b4b0851469db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1857", "a00260.html#a10dec68d0bd2b6d8a72fed4cd6766502", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1858", "a00260.html#a01fa21bc249c11b71706df7db5159386", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1859", "a00260.html#a035a0c73ba36a0de6704179ca98de091", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1860", "a00260.html#a2c358387654212e2fd0241f9810e20ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1861", "a00260.html#abaeb172990507a300b31e7f7e738e201", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1862", "a00260.html#a06922ecddd5318a3c70fdc2b3d089f68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1863", "a00260.html#ab23421c0463e2e538c26bb214f75d36a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1864", "a00260.html#a3b6297e56cd75a26471c4dbc4701c917", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1865", "a00260.html#a1cf5e68c3483662fe8d2d4dc5a0edfba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1866", "a00260.html#a0ca9daa51d2122090015070fc151c820", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1867", "a00260.html#a92569247f3c1ba8267258a2a15907588", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1868", "a00260.html#a9da6e8f783dd5e96c0219573b2534b3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1869", "a00260.html#a12677974374ceee1bbfa3e3d4923a40f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1870", "a00260.html#a4c08490b5c45f39f2f6dc962ef3293cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1871", "a00260.html#a252f382c11e311fb84c0d54c45515dfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1872", "a00260.html#a16eef8f731d98e361488566357299d94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1873", "a00260.html#a7aa4b4b64ac8a785158860d7dd3a360b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1874", "a00260.html#a83d2bc7b957493ef6dd8767cfe38f010", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1875", "a00260.html#a9aec102034615f4152593ff8acfe90c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1876", "a00260.html#aa00c3220f812c63b7840f33f07bce3df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1877", "a00260.html#a35e17fa00df4cdd991f1df78bbeaf163", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1878", "a00260.html#a676ec3706ee0ddbc6b2a4e3f24b22cb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1879", "a00260.html#af00ccedb8f4233c03920bc073cafb020", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1880", "a00260.html#a0094ceef398764e27ae6f02c676d7c63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1881", "a00260.html#a10453a91c85beaf9e880153560382d63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1882", "a00260.html#ad4d253375c9f7b89c4688a74a9836efa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1883", "a00260.html#a317d788f7d16e0c2f41607cd4ba1d2d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1884", "a00260.html#aadb32959cfe49b45749e68c44c327bc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1885", "a00260.html#ac3436309401c616cbaa1e5d32827d713", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1886", "a00260.html#afbaab4fafec9911c018abef27579be13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1887", "a00260.html#a64803c9dfb08bcf48e87e79f21f433ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1888", "a00260.html#a5a3b8aa4be80860b77bbf28c14528319", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1889", "a00260.html#ad05aeb1036c8da3c6a13ac1501b7f409", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1890", "a00260.html#a987d8fc1be7cbaa3bae8477a2bbdef91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1891", "a00260.html#ad436dc0eab979ca001fdfe9a1ebcb329", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1892", "a00260.html#aafc9ff6b03c0af38b076695a03f3cfb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1893", "a00260.html#ad505de03c4ae4715b2b24a9f4699b677", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1894", "a00260.html#a298199fba1888ab6fb7624c47d7b29af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1895", "a00260.html#aa2736122b6ca4d7ee12dbcc99a0bd442", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1896", "a00260.html#a1e462e4fa1a18040a974d08ef0a8833b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1897", "a00260.html#a3566fa3552bdbd338f0b2c0018104d6b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1898", "a00260.html#aac6991e7acaf86545a63ac86804db67c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1899", "a00260.html#a4375be32b4219d526e12979b616647f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1900", "a00260.html#acacbd7a1ea4aa314df9398aaa8eaa3b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1901", "a00260.html#a9ca4bcc643b778d121561dfcdc1d8dd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1902", "a00260.html#a2cfb22efb5e3751808d868deedcd809c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1903", "a00260.html#a76a039e0c693fca8069f897762d5d724", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1904", "a00260.html#a71484ae49b6c71b28177b05b95cc2f1a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1905", "a00260.html#add9d98529df3e10ff95f4b80f4ac6b27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1906", "a00260.html#a8ac551164c72116f38def3bf1a7d8fc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1907", "a00260.html#a72686ab78237349c2ac796447efe0bd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1908", "a00260.html#abbd9b8cc4a51dcd4bcb16a489e4c373b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1909", "a00260.html#a5413bc21caf8fc6ff6c8d31fd3ff38bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1910", "a00260.html#aafdca92138fa76d0d76be40ad62a1865", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1911", "a00260.html#abc966694873fc45740e1684b6d5b9131", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1912", "a00260.html#ab9a2e81976915ee4f2719f1f70f11ea4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1913", "a00260.html#af4c6f5e280f4672945e0bc1b39cbc42a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1914", "a00260.html#a07a619ea98c0fee7a29a02703c21d98c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1915", "a00260.html#aaecea748a7e13e6add1d2a9000a315b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1916", "a00260.html#ab168aff518eeb6700e43e541e315dc71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1917", "a00260.html#a53895a2be95c704605dde7cf9be11b25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1918", "a00260.html#a380c3cae1312afa0eebf30e84b6dda5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1919", "a00260.html#a7b3ad58a256d064b564d627a8c845b6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1920", "a00260.html#a49430b5ac568ca69406b752c39f00b43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1921", "a00260.html#a190524752e476b15955ddcd8f24c2050", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1922", "a00260.html#a90bbdb78136bab091634a31c944f2f16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1923", "a00260.html#a1fdea4a731516e0b63e89dbb8af6e203", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1924", "a00260.html#a51df160409ebdfda5f5210f7f1489ff6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1925", "a00260.html#a59359a6afd50f289323ffde12b3ce08c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1926", "a00260.html#aea8408d5acc30ab7dc9fdee845033438", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1927", "a00260.html#ae133798d387dd0f7021344717b2bae1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1928", "a00260.html#a5a0004f731fb030aee57fbbb1037f2db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1929", "a00260.html#ad447853c13995bacc60d178694409eca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1930", "a00260.html#a8f723b1525719cf8f8c6a7c63e913e0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1931", "a00260.html#a1de836f701a1aa5f7581d72c769388f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1932", "a00260.html#ad02a819c37cecc6a4f32ce45ec3939fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1933", "a00260.html#ac81223dd2ee4443f7fca0a3c0a068b93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1934", "a00260.html#a34149c56a0177334273cfb0eb0a31738", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1935", "a00260.html#a487e08ed0f68f23aa291e10323dde749", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1936", "a00260.html#a77295e8040dfa09e9ebbbdaddaaafff1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1937", "a00260.html#aaf94d2e2a409a278ab46810679bf0ce9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1938", "a00260.html#a9baf2abee336e0f16031625e5422cd62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1939", "a00260.html#a4d8983b2d6df6cd5b199062a4bbe7510", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1940", "a00260.html#ae4669dafabf8d543c59913d98d06958e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1941", "a00260.html#a34ecaf2c45a69537caa4fb3bd2df16a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1942", "a00260.html#aa18e024b13c0f4745a53553086b65726", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1943", "a00260.html#ac0646d17da081dc60cf372d8c04c0010", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1944", "a00260.html#acf4a1b529f92311a18790246bbb250ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1945", "a00260.html#a17447291ea76321919c99dc415e84ade", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1946", "a00260.html#a7a6bc3f061ae00ca89af3d3042776eea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1947", "a00260.html#afd60fc461fbfdee6daec582de4ffbb2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1948", "a00260.html#a5c28b7db4b87e274aa237d50fa708c8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1949", "a00260.html#ad3cb13c5ded97cc0258eac0cb1c38840", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1950", "a00260.html#af06de4522afef983ff38d6771b7d9694", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1951", "a00260.html#a70cca07d6a9bc33fdee05cc2a2f548e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1952", "a00260.html#ac876f07e2624403c167bd04c40ac476f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1953", "a00260.html#a419fe1dcf1034377aa1006ecba7c6093", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1954", "a00260.html#a8468cba93c38f632ab7262869a336837", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1955", "a00260.html#a166dd92a98fa2c3bea413632a3500b0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1956", "a00260.html#a5373c34ad5899166c0de06f611756aa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1957", "a00260.html#ac7e2b26d2c1390bfd7987544087ab245", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1958", "a00260.html#acc75bd161f78eb8015b3505ad0e7cf9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1959", "a00260.html#a832541ceda119f6a55a5b068912f638c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1960", "a00260.html#a62a77b15b4bdcef98818fadb68ff1b18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1961", "a00260.html#a0b76c66d7a164cfa55fae6b882d48c74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1962", "a00260.html#a8bf552c0748e42473a0f873ce227c01a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1963", "a00260.html#ae5a14e26e2648eda0f4fa0d0b24515b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1964", "a00260.html#a9335e7b63cb444abf290dbd605de97c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1965", "a00260.html#a16a7927458d005ab352404ed3d5e52b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1966", "a00260.html#af892b7d38c5fe016fc08f852eebc1db5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1967", "a00260.html#acbca2f20be8fc0c8b844b2aaa99dcd94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1968", "a00260.html#ae30b01aaec35c445b0de873c79ff5be9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1969", "a00260.html#a13df92ec226f95bef020be530095a207", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1970", "a00260.html#a511c95355208fd615c405e0873350217", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1971", "a00260.html#aab14b986b3e7876d22ea0d1082b84192", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1972", "a00260.html#adc67fb4b399a77700826a88b551f5a26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1973", "a00260.html#a01a5dbcd43306306286deedeb9744351", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1974", "a00260.html#a47fce93c88c06a41cd66897d5fcb6558", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1975", "a00260.html#ad1cbbcc9d3623a11c96e29b594ce603e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1976", "a00260.html#a8a0d6743534076451729c44a1abc45e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1977", "a00260.html#a89a707c4e6c9a54c8eb3d045496210ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1978", "a00260.html#a1cc85121e70a0455448154f3c1cb5c2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1979", "a00260.html#a666fbb2d79a058f69e22921da88e2619", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1980", "a00260.html#a677ddd0f0220a7e1caf2391fa8a7a9ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1981", "a00260.html#ab42fcbd05825011aeb17d5cd6c695481", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1982", "a00260.html#a64906d73879a05f0ef3003f9a63fd2f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1983", "a00260.html#ab51477a35c9f35df2345ed15679b9369", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1984", "a00260.html#abe4ac5f8e16b6736dc49ce17d19275cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1985", "a00260.html#a24c35f3885b5941bfe6b5b29fbdb6350", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1986", "a00260.html#a8aa2a3c276d9c6fbc282471f8f0bca23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1987", "a00260.html#a4a2a3fe6f9b27edb4d54e9b0cd95b35b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1988", "a00260.html#a8a20d44061caab5800bf5222a66c5d39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1989", "a00260.html#a7a33a2bcf9465dbbd969cfc2705a9df8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1990", "a00260.html#ac5a78e23e024260427b48014887b8a3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1991", "a00260.html#a24b4c37a2dec45feb8b3f860e40f932b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1992", "a00260.html#a9199da611ada01343a402adbefeacbbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1993", "a00260.html#a635ac820bd6c32c432858575d5357ccf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1994", "a00260.html#a6763edb369f007a8ddca1f9243bc614d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1995", "a00260.html#a98df9511eda539aaa0b83af71285dfd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1996", "a00260.html#a93f26135febdfc7b1a7849f1ac63957c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1997", "a00260.html#aa29de961bc964f9ac9aacb0d630a6b90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1998", "a00260.html#a205ba7725cd5091f798aceb8866a22a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1999", "a00260.html#ab3918d07772a616d421f1638e1d3a790", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2000", "a00260.html#a89059f41d6d55ff06953f8e87ba29f02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2001", "a00260.html#a3aeeedb7fac60813dd969fb96db585d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2002", "a00260.html#aa6290454da7d759ad206ce66decdaf99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2003", "a00260.html#a933da1ff0051778ecd19ed78fe0c413b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2004", "a00260.html#ae1fac6eb3a9f6dbb55dce5ccbe145d39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2005", "a00260.html#a1fab51b1600355e775adc0dd20b31aec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2006", "a00260.html#a3973490544205584f8a009244dc4f747", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2007", "a00260.html#aa6563de464126c97d8dc4c2929933768", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2008", "a00260.html#a29b58499557d10db497ff26f8cfd4467", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2009", "a00260.html#a15c4a750bd557d499752956503a8452a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2010", "a00260.html#a12e60210d0776e60c9265ece684550ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2011", "a00260.html#a4dee524d0d48101ce84dfc95c04206a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2012", "a00260.html#ac9023bbff6b64abf381c2dd94cbf6574", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2013", "a00260.html#a59bda03429e13bf0ec558f3a15858574", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2014", "a00260.html#ab213a685b36f5edfe91994426c36a2f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2015", "a00260.html#a84038ae568b163086a5dbc73e28c91a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2016", "a00260.html#ac07200193760634eef5e8fe995b7da93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2017", "a00260.html#a273fb3765c8f1bc565b162349d6a6233", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2018", "a00260.html#a37129aa1e4bbdb737a64780efbe46f8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2019", "a00260.html#ac21653d67c7b5364b76ebc10aad8a2f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2020", "a00260.html#ac6d0d8125028e4183dd7c5cda775d04a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2021", "a00260.html#a29a9a6ec39f0a1306db29d7cbbceab74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2022", "a00260.html#a9dff7dcef1afc9591376677ff73c23c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2023", "a00260.html#af4c2d52c981659e5f963c3ff399d97a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2024", "a00260.html#af975697c3d42eadc44c6dd13d8d2a8ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2025", "a00260.html#a8bb4d4a63892fec9633e8f4b7a5b437d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2026", "a00260.html#aef1436ca5bb705e9df3adc6fe70e5ed3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2027", "a00260.html#a61dd0fbbc6c36889f67bd7d6def182b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2028", "a00260.html#aaea0d0e003f951ed03584ccaa042ce50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2029", "a00260.html#a23ddbc359ec039fc3276750b89d82b99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2030", "a00260.html#afe4ff285816338481d91d147a861d0e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2031", "a00260.html#a3a8fe83ffc08e158401d8ff091370cdb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2032", "a00260.html#a470f188f541ecd0a819bccd74a93a8f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2033", "a00260.html#a1b88858082eb93abb94473d95bf49f65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2034", "a00260.html#a225199f377f224b9b9b4f5fa71c64646", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2035", "a00260.html#a574b59dd3527efa4319a0d92d894dc90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2036", "a00260.html#a0d544d1b7c305888f7bcde48ec2c697d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2037", "a00260.html#ae0569aec4a20ccfa057dc6702a59f200", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2038", "a00260.html#a4ba27a5e3d97baa5c8f5cdd1930637d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2039", "a00260.html#ac133af18a42083b579075de4c170c097", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2040", "a00260.html#abbf187b45bdc04119670e583669e5f04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2041", "a00260.html#a21c0d61dd29f46ffc68e7359ce82eff3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2042", "a00260.html#ae3c5e1a76c4461b8914a2dbf939a52b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2043", "a00260.html#a1513c9c69c0146d34934922d93ac3157", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2044", "a00260.html#a823c869a949bb85eadc0f5efd638f78d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2045", "a00260.html#ac0eb08e607e815301ec50d5513d938b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2046", "a00260.html#a549be6104a9933a1c7198c71e2586f0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2047", "a00260.html#aa96dbdd63186bcd8ffae14193dd8cdf4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2048", "a00260.html#adcf4544e61d903276ce6bfd608779fa5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2049", "a00260.html#aacbd8ee3272a0465254d6ac29d3e69fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2050", "a00260.html#ab70df0991b9755ccc2f01f55b595b3c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2051", "a00260.html#af81056461f8af149726d52f858b829a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2052", "a00260.html#ae93f05446a844305bf279030a90bcdf5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2053", "a00260.html#a3644022a9d11bdce0288400bfcc631e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2054", "a00260.html#a16b0f8a4ea3eed2d2ca8082fcc4112b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2055", "a00260.html#a1c9f09df0a3982fff8b300296a411b9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2056", "a00260.html#a5d337c2f595100a6e67820b1a37ccfa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2057", "a00260.html#a6acec104bb863f969d82266da72d180c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2058", "a00260.html#a6b75cbaa1e97e0d41376bcf56099831b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2059", "a00260.html#a463900ecb4854166c7477de0097d1c67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2060", "a00260.html#a7d7cb6f7a35cb2b06e88df85c3f543d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2061", "a00260.html#a182b3d1f14731fb1bca7ff8b2a0a19d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2062", "a00260.html#a9397c5541d9fea086fb36311e7dd6174", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2063", "a00260.html#abd0402d305a9a0932fe0c0dce5da5062", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2064", "a00260.html#a52e490a25d2acbe7f647218126274479", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2065", "a00260.html#a0f271879b5832604180a3655c186578b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2066", "a00260.html#a11ec3c07075260c110b351e961fb6b5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2067", "a00260.html#ab667b2fea8f70292eba971141aa687ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2068", "a00260.html#a72964c31e7fdc59d4754d283d8c40814", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2069", "a00260.html#ad87be7a6bf1f6f0d26b987660945524a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2070", "a00260.html#adde6308f35b7d888039ea657539467cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2071", "a00260.html#a2d149335147c6a115126d316b4175238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2072", "a00260.html#a8942cbb429bf1f8535d48d9b1431bcb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2073", "a00260.html#acc8a2515448b35f056d3ada326f44391", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2074", "a00260.html#abbe21eb0676d923daf7136a458532e06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2075", "a00260.html#aa24f0d2ad4478bd386f3547ab8a8eda1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2076", "a00260.html#a232337f21d5e88670c4675df17b21b40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2077", "a00260.html#ad51446d8c50b08ea1c62b480a479e6bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2078", "a00260.html#a592cb3cf4e1b0a7089436a1c776d88b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2079", "a00260.html#a6dd69c0cabad84808b32c7f1de9f1e7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2080", "a00260.html#a65345d5fe41d7d9ee6174f2457ce8cba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2081", "a00260.html#a5a212a71c424e8b13cd065303707deda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2082", "a00260.html#af666a09266b34ba45385d4392eca97d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2083", "a00260.html#a4754e79924a6dcd8764a3c81859b3b35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2084", "a00260.html#ab96a3c7a39b7d694826aaf42046f93e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2085", "a00260.html#ab6c42b37c0eec2d0fc8bf8cd05c7a99d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2086", "a00260.html#a901af7f008f5d24a83f89d6a8d43e989", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2087", "a00260.html#a23b95afe3d98d736035ea8752432baec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2088", "a00260.html#afe715baf6850f4fc62e0f698d0c4a7cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2089", "a00260.html#ab6003da0cc3e6671907b91f4cf7f7234", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2090", "a00260.html#af5876cc9bbf958913e1a593990a97496", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2091", "a00260.html#a10feed179b5119f4c6bd2b4ddbc34021", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2092", "a00260.html#a807ce5d5274dec2a6728c2f013cc4094", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2093", "a00260.html#ad8882466225b28128189bc16fc2f7ba2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2094", "a00260.html#ad4a79a85ee9dce54e645bca805c81bb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2095", "a00260.html#ae67386eb4cb2fea49db4af492802a232", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2096", "a00260.html#a74d54f09f297d2a7734515014b5b8eaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2097", "a00260.html#ac33bce99415029442a84c8bfdd72397e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2098", "a00260.html#acc3267a6bf87c5d2991ab0bbb94d3bd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2099", "a00260.html#a5875d4707bf664f3d458ca9b99d0ba75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2100", "a00260.html#aafb838beeb7bdbec2fe5a507f27b2591", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2101", "a00260.html#ab60dfba9271726c588703566fd7f2966", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2102", "a00260.html#acefa1aed996db5f0b91656b5e861ed36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2103", "a00260.html#a00ae297430ad7651f724227ed7dfbab5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2104", "a00260.html#a94de1d36751fd3132678629be88925d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2105", "a00260.html#affbc99869dcb344e03bb7fccf462911b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2106", "a00260.html#a4573ea740d77503d6631517b0df806b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2107", "a00260.html#ae01ef9145da363701e05fc65b36318ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2108", "a00260.html#a7cdac8e795fa3144bf3daaff1986b1f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2109", "a00260.html#a4a6f711908ec87cc256e848a56502b2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2110", "a00260.html#a6c5fadaa11140da8d53aa1ff224b444a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2111", "a00260.html#abfc6cff74b8a38833cebb15f4c5f89b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2112", "a00260.html#a5dc7227a31265917de2cb3297f00d015", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2113", "a00260.html#a7b79debaa6b9c957348f1b1d98189e25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2114", "a00260.html#a4fde9001c6d2c442bceb7df70f9fd735", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2115", "a00260.html#a62831aef8baa9c83e366cf39afeb0037", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2116", "a00260.html#af0a15eb2f63657cc78ae7adee64ec71c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2117", "a00260.html#a5373d7a73b59e4ae160747c9301555ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2118", "a00260.html#a9d3e178f197a052ad1ed3ad55025d219", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2119", "a00260.html#aa389b24df36298cdc210c1d636f9cc14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2120", "a00260.html#ae597fdc91650f5dc651fe0da2a15f2c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2121", "a00260.html#af1da0ccdc12bcae2396c2c6097d6b321", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2122", "a00260.html#ad60ae0842964605b31019ddcb4b1d6f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2123", "a00260.html#a3e98350d936dd36817ed6886729e5bf4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2124", "a00260.html#a13e36b514ca89da0b6a9d8b1e09feb62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2125", "a00260.html#ae95e3a714cda2f2fcb2e217d3179c5b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2126", "a00260.html#a4a1054c90406ac902709e0e12a744158", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2127", "a00260.html#a0be3beb715997c76a325076b5d2ae8dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2128", "a00260.html#a7fe0b35d080bf125486716c68f8e698e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2129", "a00260.html#ad5425be95188f65afa3ab9c3e57d5cba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2130", "a00260.html#a7c7a8a6a727de2dbbb1bf1cade016e80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2131", "a00260.html#ae65bcffbb57faea7a897676c69f10985", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2132", "a00260.html#a944a4215fb7e48738ab98bd81ac2ab69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2133", "a00260.html#a58ba22e32b31754e817054e80986444e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2134", "a00260.html#a13a8208067e0cef4f2d587c9c13b46c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2135", "a00260.html#a205a4541cbabee9a8684e678926e030a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2136", "a00260.html#a5e0e0bf119e3760800ed012111fc70c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2137", "a00260.html#a1fd83a8e009222b6ef4ceef2a5a29e2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2138", "a00260.html#ade1e606f93969b9261542173e317b36e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2139", "a00260.html#ab5b4db6f6c51c0f2370c27c8cd2e27ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2140", "a00260.html#aab92376e7b88c4b1a28ef0201aa2051d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2141", "a00260.html#a20f036f1a34a0806ddadaf652b132e5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2142", "a00260.html#ac1915da94a9749cfe906e9072465d9db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2143", "a00260.html#ae6ae6dac4768b905cd4fca4d29a10628", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2144", "a00260.html#a4a3d812de7db9b459cce6ed047da6839", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2145", "a00260.html#ac1d0a291e4fc006c80f5d0c11cd46883", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2146", "a00260.html#ab991064f24d54aa82d073bf42431570d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2147", "a00260.html#ae36052e7b6e16868672fe2459c7bbb3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2148", "a00260.html#ae2d48c7d62d75abdef9450b991cf400b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2149", "a00260.html#a5a8f9074c6564ead86db210d4f14f52e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2150", "a00260.html#aac8988e3b7d9632d4bc753b67d75e422", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2151", "a00260.html#a1825ba3c2ba4e3663c51413d9e74c776", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2152", "a00260.html#a98e1569c78a98a5c5739bf639cdb882b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2153", "a00260.html#a57b1178cb419e6d7398e584aeffcc511", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2154", "a00260.html#af876274f291a36c419661d4a886e8dbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2155", "a00260.html#aa5b5ff7f3d2bd652bf2d878ff4a89afa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2156", "a00260.html#af791a5115d5567649eb962ca41b4122a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2157", "a00260.html#ade706705917a415848262ce93ac37658", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2158", "a00260.html#afa56f26a52cc2e08688d3a65b684ee3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2159", "a00260.html#af1f7ab2dd6989a8f02bfe8358c9baa4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2160", "a00260.html#a4522a4808750e98a4d17a578365510a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2161", "a00260.html#a7316c88c0e587c340ec563782538d5be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2162", "a00260.html#abdc7357bc63529697bfb47762d1cffb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2163", "a00260.html#a4b95d20945cd06388cbfb72ef446b15c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2164", "a00260.html#acb1836687aca24175a7ec82e328db31c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2165", "a00260.html#a1e5b0ec6dd30fc455a0fac7d90e8441a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2166", "a00260.html#abd478ac1e2d6ed855602030175945fc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2167", "a00260.html#aa099c43a37c4db5cf141e7e3ae08b44e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2168", "a00260.html#a11b19d63c593ee65f823463232d3768b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2169", "a00260.html#ac40f21086e732ac85019ee96f5e6a7c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2170", "a00260.html#a7a67b11392b4cf8e83a654ce52b33cb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2171", "a00260.html#a10b7718d1ab805b11d90df9fa3adecff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2172", "a00260.html#a8e0daab3b1d8ef3030f247cab74e5b54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2173", "a00260.html#a66431f3f52e279af8bc20f7285b824cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2174", "a00260.html#af2b1ceaf78be5d20ecb5be7cf8629463", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2175", "a00260.html#a43a3b9921f073e3e1d2a1a1fc33494c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2176", "a00260.html#aed35ee2f5e3310c92ece15405faedd20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2177", "a00260.html#a1f05b0c19b77cd55ed215bcb63f4ea19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2178", "a00260.html#a1c11286fe1186b4841a396092c494c15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2179", "a00260.html#acee546c374f0e3753a806a66cd9a5fea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2180", "a00260.html#ad37318e2a9dc902e735f2f2743667d2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2181", "a00260.html#acab71618278406052d8059c770d0fde0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2182", "a00260.html#ae51a5f6036b99978fab43a3553f7d368", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2183", "a00260.html#a550111cb0417de6254729f7d31a97fb9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2184", "a00260.html#a564317883573a39861e5ce35f934e456", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2185", "a00260.html#a5d30b2a533b46d94347c45983963998c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2186", "a00260.html#ab5401c02f330d4c6357dc54a5bbdfb55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2187", "a00260.html#aae1e144995e05768f43ae49a3f553fed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2188", "a00260.html#ab4c2db22e702f56164c9459de00df0ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2189", "a00260.html#abcdc737a524bdaf40e4b150950b19212", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2190", "a00260.html#ace8bf59478fe29a30b6c4add40340431", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2191", "a00260.html#a95b80303d031c394efef0b85db93a285", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2192", "a00260.html#a7a2f440a8b8c3ac1e3df2f8a5585ed36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2193", "a00260.html#a0d4d7804f7b503dddbdfdcda06c65a12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2194", "a00260.html#acbfd5e9d122f82ddec8a2a9644422e20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2195", "a00260.html#af8cc0b64eb98deae4fbbd77c0294f2fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2196", "a00260.html#a0ddcf7e379d3494065287de53daa018e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2197", "a00260.html#aad2fd2bb1ace39b86b666f61f87fa7f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2198", "a00260.html#aedf736e081bf51e6cdca059f3a7955f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2199", "a00260.html#a0e1b183f2f98d72cc978339bb8d03af6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2200", "a00260.html#ac08e8919e5161c93d2bebe35131552eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2201", "a00260.html#aba7672a8ae6b04070feaa15bc4a9a126", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2202", "a00260.html#a769c620df775e20b43aa005db3bb324b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2203", "a00260.html#aa99a4d8fac955aca82a3d6a19b5873ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2204", "a00260.html#aed5afebd6d863b32ed1a91daafbbf6da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2205", "a00260.html#a0899d4e4b94b41febd839e1758365cde", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2206", "a00260.html#ae9a261d28f892d211ac9bc87100a8c12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2207", "a00260.html#ab8f8e2552370b501284740120577c7cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2208", "a00260.html#aff77a25912951a841bb9e0ee6d0a19fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2209", "a00260.html#ad7386f25bf017089c083dbeb10990e93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2210", "a00260.html#aa4e98a64456549bb59faef6bd880a394", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2211", "a00260.html#a193184f06fb541f286f22d25c758c9ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2212", "a00260.html#a6366bf81bc293a4a0e1e14a4d1519479", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2213", "a00260.html#aae7cc028b8181980a745b6299a6b433c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2214", "a00260.html#a22c3a201727a356305512b442e72112b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2215", "a00260.html#ad9dbc9220910ae5da44f7cdb77d054cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2216", "a00260.html#ad83bbccbe2943bed735e9e9a7c546117", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2217", "a00260.html#a543ee8b313bca6a01ccebb38e6c3ddcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2218", "a00260.html#ad7be69df45d9f93d354ab95609ad33e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2219", "a00260.html#af748602bf5bb85b6524919606aac9a1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2220", "a00260.html#a3b682f59c089640d8326fd4d9f5ebff4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2221", "a00260.html#ab55af87a1b1aec61d837e1f4b7b72ef4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2222", "a00260.html#a375b4221cfebb5e0a5a61491a1b24784", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2223", "a00260.html#a1f830fc43cf2e23360eaa5649c8b29ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2224", "a00260.html#a0a40204fafec6ea280c87ce59b50d56d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2225", "a00260.html#a7a6e82893f3379e65bc85a904e6f75e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2226", "a00260.html#af26048fe9b6be7fe251bc4d8f1c83827", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2227", "a00260.html#afb11ab0f4174f7e663b798f49fc88548", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2228", "a00260.html#a2a875bb63f3f6322f30f0ad0deb04d0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2229", "a00260.html#a9024bf2102981dcf0a950eacaa50075b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2230", "a00260.html#a63cc516d02fc681504c9065757d6c0e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2231", "a00260.html#aa36c67af44ba70d47a8ba5343e301579", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2232", "a00260.html#a203694d191052a7441dcfc76086f1f40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2233", "a00260.html#a13094a6e037d4198c37b4680b3702928", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2234", "a00260.html#a4c32a1e7c17375c32026b7e7c3f4ccad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2235", "a00260.html#a7e217324ba36d46fb0bc85ecdbaf1825", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2236", "a00260.html#a781601657e07376b40be4b60ec721c3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2237", "a00260.html#aea4729f9d91698e267bc2ffd5e5cd973", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2238", "a00260.html#aea25638240fcfe8b32b1da58b5d57822", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2239", "a00260.html#a5cc0bccd6caea6d97aeb06de6598a771", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2240", "a00260.html#ad986590f17146b16e399df1c57fe7fff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2241", "a00260.html#a7c13fa974f248f1a142b5ebb683f2a97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2242", "a00260.html#a3266c5f6c5496becd57ed09e7b277770", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2243", "a00260.html#a7af29aab17f101dd627643ef8055263c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2244", "a00260.html#a109f56263b7491817e6ae10fd6c5e2ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2245", "a00260.html#a90c8beb808680d758711ad4df4e07246", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2246", "a00260.html#a100b7decc3451ea9465bba049ace30f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2247", "a00260.html#ae9c3545c546093a48a7dc96cd094b247", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2248", "a00260.html#a5074dd32adca7a6ba1011c3ea6c07c75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2249", "a00260.html#aa5258162b85e9485826789f80d389d66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2250", "a00260.html#a728b633498504856be6fa8c519d298fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2251", "a00260.html#aa88c0193fdd6423bb4670d7ba2d28a35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2252", "a00260.html#a4f366b2d8a5d43ede1692d658a1f7219", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2253", "a00260.html#ad62738f0695a44089ad62e919a023d54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2254", "a00260.html#a38b589438f18bd486516c06d85757806", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2255", "a00260.html#a3083cf04219ebf750e648211f4551ae8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2256", "a00260.html#ad77ae0afe2d525dfa4b8ed0a07dd471b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2257", "a00260.html#a90fd646861b809b129c1b84c02081d53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2258", "a00260.html#ae0d3d485b9b147eaa9a2281626fa9185", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2259", "a00260.html#a6c18d934a2dc47b9333e27f3b30a542f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2260", "a00260.html#a17a74a109865bd8d9ff9aa515f324fb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2261", "a00260.html#a82350ee243d71e2a6132937de3d160a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2262", "a00260.html#a3289aeb3266e2ca624e736d520041ec5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2263", "a00260.html#a6e1b9512553388f54ed7f2b200c3cc76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2264", "a00260.html#a33ab13a2df9ab08fcb7b028cb8e9b505", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2265", "a00260.html#ae23ee8e7869acd0ccdbf200d76a7a776", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2266", "a00260.html#aaaa3089f193e35aa30dac293ecdfd7c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2267", "a00260.html#af9695dd3a7d94cb25291ee440ac5d7ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2268", "a00260.html#acbdc53c3091f53724e6447ad47a79d91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2269", "a00260.html#a24ffa59ed966c9b497108c0b7a998a45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2270", "a00260.html#a9791d233dce0f1b0049f6c4a756e48f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2271", "a00260.html#abaaa1ae2da1c2a99c4fe484ff11963df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2272", "a00260.html#a12e199f81996377c939c1108fb035732", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2273", "a00260.html#a32e5935df18e053276eb068ee35e63bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2274", "a00260.html#a4f7d3b571d0e02bb2fb4ed01ee0987b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2275", "a00260.html#a497bf5586fe2f4f465e5e992d461ae45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2276", "a00260.html#ae741b3ec23b171e6299d92ecf4ea40e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2277", "a00260.html#ac74e580a67d810da678c4326fb48a744", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2278", "a00260.html#a816a3ccdd039a8e6a7f05df746921218", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2279", "a00260.html#a2346a16cbeb850113f56dbee643ef939", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2280", "a00260.html#a4f5671442458bd0e0e4316e79516acd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2281", "a00260.html#a184abbee01b8da1e6046f1c712fa5cdf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2282", "a00260.html#a96426385b09a9c81d21df33867dafaed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2283", "a00260.html#a412955de22183cb127c83305fc4e6b0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2284", "a00260.html#a74ebe1af562ba99b547d56cca35fe109", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2285", "a00260.html#ad61f5dd386b6ddbeacab7ef0e048f523", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2286", "a00260.html#aee8fa6404b6af8c3578fa6ec3f709234", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2287", "a00260.html#ac389877501cb57d087e2964cae45e309", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2288", "a00260.html#aaccd8e75d784b68de8cc17b9ad037b80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2289", "a00260.html#a0b386b42924414000a77023a0248738c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2290", "a00260.html#ae6e9bfc7b699980dd50fd2ba701401f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2291", "a00260.html#a78867258ca278cf91c82bfe34e9e5a52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2292", "a00260.html#afea23c734b5138fa4b91a2a1f8ea7460", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2293", "a00260.html#afabfb147abf325a358c093f83e131501", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2294", "a00260.html#ae24da516b450886ce32692d6f3a66b92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2295", "a00260.html#af604642dee2f2eff6e69435debd56c14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2296", "a00260.html#a05ebcf7c45ae7430b0e7fb98ea035c52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2297", "a00260.html#a639d7309c57a64db6ab22e97f24c3e32", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2298", "a00260.html#ab0c4a6541d5dbc6c0f10c68d7d103ac8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2299", "a00260.html#ab337f768120416ede99381055bbaee0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2300", "a00260.html#a9745cdab807c963cbf491574c330cf36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2301", "a00260.html#ab2afc0fc6635cddd0460a79aab6940ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2302", "a00260.html#af972164748f1135df15624af4be9fae2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2303", "a00260.html#ad8cafbfceff5349b804425b148c02d5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2304", "a00260.html#af63491de9e9c3b5a97a6c90892452f07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2305", "a00260.html#af4a1daceb2be5b4d20598976db2216d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2306", "a00260.html#a0a21274509b5244e2bc18bc40c804d4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2307", "a00260.html#adbb7d2f42290a737a7d52a56e2b1fa64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2308", "a00260.html#aec68452414c847e1934152cd5a9b054e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2309", "a00260.html#aacc7b11788229f1222354c6c06e9ec74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2310", "a00260.html#a935f4bc6e8d880a1e4c4ea097f0f125a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2311", "a00260.html#a827f8ea088d7b4abf51f03ef6cd3344b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2312", "a00260.html#ae9470a3ef8cca99a877fd755bb3d7433", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2313", "a00260.html#a3ed30074c4604418630ea3343e4dd895", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2314", "a00260.html#a396717f864a6506623be5165efc49491", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2315", "a00260.html#a3631dd4e904cf109b73569bc6603e224", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2316", "a00260.html#aae65c2f6ed1133033b912e30ffe2fd17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2317", "a00260.html#a346413c4c95c2c0596207a5d41c8b176", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2318", "a00260.html#a5d46e3c0ee58db9fde476298b817f4df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2319", "a00260.html#a87e67b4db2f2b1c62dbbc7e2dc4cb230", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2320", "a00260.html#ac89eb588237da52f3097f58d2c9bd0c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2321", "a00260.html#ab74bcdc4fb6b0836d1210edbbd93b8ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2322", "a00260.html#a20037625931ee1ca3739da9c15b7c889", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2323", "a00260.html#abc4e57f1b7a7820418410171725ecd08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2324", "a00260.html#af23d88508e2c9c770fea94dd48bd2a26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2325", "a00260.html#a3a3c4d018800dae869a254a87b0b0cc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2326", "a00260.html#a3c49b5610ba727a977a80907ab086609", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2327", "a00260.html#a76f403e65227387fcf29dc77db948f7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2328", "a00260.html#a4d2be76c6a457b01383079457b5096b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2329", "a00260.html#ac5d69815d1eb881a38b7e02fa1a77e14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2330", "a00260.html#a7adb12081ea6366ee35968a1dcdeb9f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2331", "a00260.html#a69171e45eba7c81e12e0cbe0287bc1fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2332", "a00260.html#a4b3bebcc6ee8e87d83c0a0a8ec67673b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2333", "a00260.html#ab3745118311796fcaceb9028ed7b6073", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2334", "a00260.html#a0e6711a22bb7b2ed290f391067143ade", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2335", "a00260.html#a090d2b4ba32cffc7ce5a1be0c2feed37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2336", "a00260.html#a8bd624f5cf4dcab9c2da2c1da63baf26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2337", "a00260.html#a4f59dd0b856ea54a29c6d8bc777bf33f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2338", "a00260.html#a70844babad344e5771f02af8c1a1a9ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2339", "a00260.html#a116dec6dd815e5952ac73d617a064c1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2340", "a00260.html#af05b956ed75c849689b2906371deba97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2341", "a00260.html#acf0a24cf4734a45acafa2b1d8068894e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2342", "a00260.html#a927194e590061844f8e593cf3e4e484e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2343", "a00260.html#a0a8974fd1bfde4c0db7ca12f320f806a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2344", "a00260.html#a7e165e99a556462c709f42ec243dd729", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2345", "a00260.html#a5658d20f3e4988e6f1040250f091fcc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2346", "a00260.html#a4aa425aec390391f8aad48782b681f26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2347", "a00260.html#a7b40b820ce0d24f38f447b5341b4059a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2348", "a00260.html#ac48ae9b085dfbe2a8e75562873711325", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2349", "a00260.html#a9cf53a581f1dace8c314a135fca0e8fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2350", "a00260.html#a112777f4d9d9ec970dc0a9719dd185ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2351", "a00260.html#abdb1de984d15c7ea8fb3d6494ef912df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2352", "a00260.html#a87cf877874de8d9ef999e84a06dbf1b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2353", "a00260.html#ad0a9bca42a27bd155d61d3ce212fd88d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2354", "a00260.html#a3d7285bf8906cfad748b4d7103fd8f91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2355", "a00260.html#aedc328b65af9d02278ab83889b5944b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2356", "a00260.html#a685e5c3c0d4a8266b43d88abd7fbddbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2357", "a00260.html#ace9585762dcf260a8214445a7d94688f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2358", "a00260.html#a6bf45eb568ca3a5ea705a9de440236a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2359", "a00260.html#a3b28333a312edbf858646536b15668ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2360", "a00260.html#a2d418e730f206d50719488e08ef7dc57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2361", "a00260.html#a31ba74a16ebb5bffcd18365657a553ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2362", "a00260.html#abdd82fb109c13877635b228c12a1e667", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2363", "a00260.html#a31c5ad35240980b36288bd5010bf31b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2364", "a00260.html#a39623c76b6bef52580536466ebde717e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2365", "a00260.html#ae4410c716666d382bca401a0dfa62bca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2366", "a00260.html#a02c3276cca81fa45dd8c1c5f45a9138d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2367", "a00260.html#afacdb2dbaa3a89a023bc1143de749c92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2368", "a00260.html#ad67ce1f53fe92c540f7b080f9c8acaa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2369", "a00260.html#a6301ace1e7c27179a64a9aff882b8597", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2370", "a00260.html#ab5a66a694c3bea8799e2787c532d4738", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2371", "a00260.html#af5d6c04f95f77129e11cf08204d865f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2372", "a00260.html#a115542f863001fdc885e2672fce2a806", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2373", "a00260.html#a8d16f8672aa0d54780cc06331aef8097", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2374", "a00260.html#af8b62bfe64653ca8844508df76d8e9bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2375", "a00260.html#a130e944de9ef8992a8ba92d2a79df3fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2376", "a00260.html#a1ebe50a439a8c6a7c799d33fce927600", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2377", "a00260.html#abaf84b465337ad11df5d73c291b438da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2378", "a00260.html#a6d43bee9e7f697bea321ab0b4a158549", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2379", "a00260.html#a00b2de54f8c8b13c6f2b91e32b3fd486", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2380", "a00260.html#a6bf9a6c19dcd446ea9b5915b7a1bb51e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2381", "a00260.html#a7b8850ee8a31399bc14e8a41a7873c95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2382", "a00260.html#a5d138d19f9a9154dac183bf7077b8046", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2383", "a00260.html#a23b651c4ea12516011244a371e72dfb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2384", "a00260.html#ade743c73931a601f9b5d417275c4d2eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2385", "a00260.html#af6e127640586c6471c63d841314f1611", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2386", "a00260.html#ab43f9abf7afcd576435af45717d6d3d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2387", "a00260.html#afdc02f691a17aaef960c4891f133dbb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2388", "a00260.html#a4034452ba042798ed335d8c118bda7bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2389", "a00260.html#ac90643c46837e972056540c4cf5b900e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2390", "a00260.html#a185242ad52b8ad96ac1445e6d0e82c55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2391", "a00260.html#a778af641f78743b4b71e2820f9ba185d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2392", "a00260.html#a59fb9c99c9c7c311600635b0aa525e74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2393", "a00260.html#aaa174c36e53c62f4d12bb073d076ef13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2394", "a00260.html#afcde53631c744448fcab43c766d75711", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2395", "a00260.html#af81539fee9ed4406ab32dec9a94a85ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2396", "a00260.html#aac1c8ec82eaff424c6ffe0b2c977feef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2397", "a00260.html#a80af521e1d051b38a2335c3209af2591", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2398", "a00260.html#a777e4a4b025ff6112fd3a3aa76d6763f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2399", "a00260.html#a85bd0da6ab3eafea6df6c9f84b621144", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2400", "a00260.html#ad2a5ffb83072306a96f4c164c55d6bfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2401", "a00260.html#af71a05f3a8984952ed8067291595c240", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2402", "a00260.html#a364d1b13a8d63e08821c600b3a3ffeb9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2403", "a00260.html#a62a07a4ec004f0f90eedac68821f5285", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2404", "a00260.html#a1c6a58167f1ef6f37aa8c99a99f86a55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2405", "a00260.html#ae817404cca6217491fec35590f2acece", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2406", "a00260.html#a131d7ed1e58d683e102210326d309cc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2407", "a00260.html#a5c061af4c2fc68fd1fe7e22579c5db87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2408", "a00260.html#ab4836514605e8e5551fbfed33bbb38ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2409", "a00260.html#a15d83166a36da03948b9982bd26087f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2410", "a00260.html#a5f4c0ebb3008bc2c0b4323f9032cc680", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2411", "a00260.html#a576896c38620730893dde88f903d0907", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2412", "a00260.html#a372eae86a3622011024696c840401cee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2413", "a00260.html#aecf684e64e818818d1681bf50aa34a00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2414", "a00260.html#af6aa316d6b54354edd2ab1e0d73401ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2415", "a00260.html#ab96fb498ce6d847d218f5f5f557812d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2416", "a00260.html#a6abf2c12bbda24ab9bffa8244605955e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2417", "a00260.html#a5ea994789fc5fd8b94b57b495a070ca4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2418", "a00260.html#a1ae82b076f25f7e23428854c1bd0b075", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2419", "a00260.html#ac5f5c9cc273f78216f059e6767bda1ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2420", "a00260.html#a5453fa280fab4d0093143d7efd5bb1a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2421", "a00260.html#a42053cfd73ce348619bee8ead9bd8602", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2422", "a00260.html#a3ddcca5d6b895371440cfadb64cc6cec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2423", "a00260.html#a0fc37b9d46f1141a94b8f91a90fef2a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2424", "a00260.html#acb9624794b3f1df0ecde1a3f39a5a700", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2425", "a00260.html#a497f00a3c83f6613ff2fd1fa56c61dc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2426", "a00260.html#a3343dfb8b86db8ab41eff1c016b0f02d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2427", "a00260.html#ac2f5a987028e69c3d55983dc1eeb9346", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2428", "a00260.html#a806271ae5caee5537ec662214f785e37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2429", "a00260.html#a53641839d84e794aae4c1e73ffc99f5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2430", "a00260.html#adb3a74e4ff37a257a9f9941496643f11", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2431", "a00260.html#a05d08f4f42bc2854c6d679e87009418b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2432", "a00260.html#a3fa17929aad1494f52c241a6f3bd98c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2433", "a00260.html#ac2c0ed03ad1546775c91dd0cc91ddbd7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2434", "a00260.html#a69a846b631f6c9214a463ad05f3b2f91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2435", "a00260.html#a6420ff9ed4d1adc90a8a15d7f3b832b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2436", "a00260.html#af7666b1168de270fff8049fc6730b795", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2437", "a00260.html#a61bcc9d80fdd97852c4fc738e44821ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2438", "a00260.html#a9e5500888688266718f8f16f1800067f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2439", "a00260.html#ac8bf96ed010567775dad8d6d3ef6860e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2440", "a00260.html#a3d3c763c4e4ea79030e5db9ebda01719", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2441", "a00260.html#ad13a85cf178de11170265a74f135939c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2442", "a00260.html#adf408ebbe23d5ea37ed315dddc8f458e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2443", "a00260.html#a09cfa6081cfc5e8cb13dc4cdaf26f217", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2444", "a00260.html#a1229f06ba93b4d9f3eb1ba3bd976c128", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2445", "a00260.html#a003b5a0115505b04adee45dcbaab5035", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2446", "a00260.html#a71e87cce58540c6e2294adefb91d6c8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2447", "a00260.html#afc063f7b6a5125b709c9ad1dc53ef162", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2448", "a00260.html#aa0d0097b23ec7b0485f5a211f7c65fd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2449", "a00260.html#a5d628f235d4840df62c2930266baf0c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2450", "a00260.html#a47e06563d795659ff72507843d9d8e92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2451", "a00260.html#a503770037f1c403de89719b5a434969b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2452", "a00260.html#aa25963cb9c40a5a5e24085033f04f1bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2453", "a00260.html#a3164c43abeabd2263e6e7da6a6a4d82b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2454", "a00260.html#a1ab870cefdb03ebeac51e0ff661f4e75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2455", "a00260.html#a862a86a3108710aef3d9e8a6dfb7116c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2456", "a00260.html#ad24f35d968c28a631b23749e82d883c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2457", "a00260.html#ab972c1f1672a4cbf3f72268623f5b06e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2458", "a00260.html#ac9a453b413454aba099b431699ff84ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2459", "a00260.html#a1303bf3ad596b95acc208c47b6a3f9c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2460", "a00260.html#a4da328b788d12a9f1b59ad5cc74a3dc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2461", "a00260.html#aae6581e9563a74307035b001e429f78b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2462", "a00260.html#a074c3df28c1fbd7ab1819fa48cd654d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2463", "a00260.html#aad3a559e9991ae4b32c41053a7364318", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2464", "a00260.html#ab03257c876d97c2f0cfe6e82cb632dd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2465", "a00260.html#af3a7edc33af7b1542f655c9ef142e3ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2466", "a00260.html#a6a23d43f36fcdd9202162280e27bad65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2467", "a00260.html#accabd63687855faf9fe7676a1e7faff5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2468", "a00260.html#adac93ee467759a5faa72385017387dd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2469", "a00260.html#ac38fa75a0e971416dd56b5943b3b2ca8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2470", "a00260.html#aacd44ea452be30d7102fa37570fbbb1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2471", "a00260.html#a0ae8171238976e88feebfd77e5700b26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2472", "a00260.html#aea801585627febe7afdd46aacb69d003", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2473", "a00260.html#a606432b4e99ecb067fafeecda96fbc3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2474", "a00260.html#ac4969e9daf6a4a24f543cb8e81ad3419", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2475", "a00260.html#a662cc624755d34b8e86a069af2f6bc65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2476", "a00260.html#a67efb1381ceffbae702418e158a1150c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2477", "a00260.html#ac6a7ca4f7b4dedd8629e09010075c9d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2478", "a00260.html#a8e48817340c7ea765b65a5a537ca78cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2479", "a00260.html#ae0be37a80df923b847dbac5691a3b409", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2480", "a00260.html#acf9719c294effd394f8081c891e1c4d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2481", "a00260.html#ae902b6297e56716c80dacde607d7980c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2482", "a00260.html#a5c09a66458c8a1d763ec6666c613320f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2483", "a00260.html#a143f83748d1c0941fc0a6ac487ff5d09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2484", "a00260.html#a5b2178da3d5ff9b98ab08ba9c103ae59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2485", "a00260.html#ad3a0d1df546b3b69e10ab83752138dd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2486", "a00260.html#affc867d259362c5fffb9fcee9e210963", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2487", "a00260.html#aa4e230018cd4a3742cd33f57ee8a56f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2488", "a00260.html#a2532823c56592cb29284af788c596d41", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2489", "a00260.html#a17f33b81db64bccb4a25cce05d680299", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2490", "a00260.html#ab2d022c8ca7f6470c18c77bd410a3a07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2491", "a00260.html#a88e8217172e376c9c070982519f4c7f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2492", "a00260.html#af642a1351191354b016d51a195f8dc28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2493", "a00260.html#a6e29d7cf04e2d10962d88c3ca22dee6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2494", "a00260.html#a2a38350cb8d634e34152d97c1c3bd16c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2495", "a00260.html#a3d4737637f0e5080c8943bce05e72fea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2496", "a00260.html#a10a8fdb8b6f082e70373b2c789088dcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2497", "a00260.html#a34634c3f844966f8fae8472f729c249b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2498", "a00260.html#a0f56420888541d196b9d588b84439edd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2499", "a00260.html#a05076e814dd3e80a3e74ebcc59ed5963", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2500", "a00260.html#a1bc265e93b561baf89a52e4c6220987c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2501", "a00260.html#ac508cdb07d3b18451d8f70cd93802ef8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2502", "a00260.html#a8d1ab9c5f8676408f0fb5f7fdd15ad6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2503", "a00260.html#af559645219a6eda55378621ab33690af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2504", "a00260.html#a81256582f41df6855c799ac711186f62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2505", "a00260.html#a65b974b28c5602be30fa68f0ccd4649f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2506", "a00260.html#ace73d5bae3a50cf0d4c5df2021cf2f3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2507", "a00260.html#a1b9a69b48babddd011b2c8912b862dc8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2508", "a00260.html#aa542ecd2ef142fe2f6989ae508803c8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2509", "a00260.html#a990a7badde3e50659252dcbc8782036e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2510", "a00260.html#a75a3da3c3b423fb58470c9530748dcfa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2511", "a00260.html#aa118a675000c2319bc5066740bd3105c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2512", "a00260.html#a36673f8a9f834d7dd727ea5b53fc4402", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2513", "a00260.html#ada4fa2b625fa3b7c71f1a4e11036b0a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2514", "a00260.html#acde8e6b7a5d8e2475c414446baab9187", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2515", "a00260.html#a6c2ef846da586789fd21ab72677c7f10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2516", "a00260.html#a4c3c77e47a4621b61460a0fc89fe8508", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2517", "a00260.html#ab6ab4d12242c30ca899c8fa65f8c0d54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2518", "a00260.html#ad41849959c52bc3c411b3b98a8151ca0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2519", "a00260.html#aef260cb3dd25c115bd92c59ca9a7d631", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2520", "a00260.html#aaebb82a9c24f4f533137144305d73fe9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2521", "a00260.html#a5888ffbd9d8dc66425c5f607b1a7e065", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2522", "a00260.html#a23c1c4bc1f0a68cb8f135e172e3ca81c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2523", "a00260.html#a412bf2c581584b3f5fcfa64ba1e3f819", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2524", "a00260.html#af57a7098262d8b61136afef472cee9cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2525", "a00260.html#aaefd495a939565fe560c9e7a57a40226", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2526", "a00260.html#aeade7ec17d0f350fab2c9fbaa3b6927c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2527", "a00260.html#a4caa26315bf0266b89e46361abbdfc0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2528", "a00260.html#a43937eb2c00a44ed3dc191ac3831a1bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2529", "a00260.html#aaac89bb8e9da9e4d30b9ef290ced88cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2530", "a00260.html#a92872a6b6d6bff1f469ff4fb465ea90d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2531", "a00260.html#ab241bcf5cc3ecc55d86f243adc52a081", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2532", "a00260.html#acc022106df77821293c635d543d097f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2533", "a00260.html#aff7ef97ec73c4a098c03626c48a2902c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2534", "a00260.html#af043c5a460a1f4143c70b176c4bf5c77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2535", "a00260.html#ae52beddc69759d9b36c1f07b3888253e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2536", "a00260.html#abd3acab399e77f26b909bb35f1481c5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2537", "a00260.html#a13ca92d30aa7ecc5f08d48c12a953724", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2538", "a00260.html#a10bb5523165d6d46b98b0e2954b13c9b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2539", "a00260.html#a17fe1ab5f0547bbaa44913a66e6ee56f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2540", "a00260.html#a5d8e5a8be96f4e2b0fe8f3f25f928305", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2541", "a00260.html#a2dffdf9ceadd3d1a173c9cf9a13dd776", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2542", "a00260.html#a9615de35ebd6cdf4137c3534fb638741", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2543", "a00260.html#a4b2260763cabfb9dd38ce9b5ca420734", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2544", "a00260.html#af7933d50960270b09c40cba2e5fb6ee6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2545", "a00260.html#a06388d6f087ba98ff5de84521d0f872d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2546", "a00260.html#afab9e222b90a93fbeb5b1f9a54e27205", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2547", "a00260.html#a338aa2b731e2f35c8d8a13cc356c1909", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2548", "a00260.html#ac6ae8e14252b4ef6f47eaeef16459a2b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2549", "a00260.html#aaf4eab8bc18a180608f4686fa3e7b66c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2550", "a00260.html#aba844d5f4d9f057747e9d33181872950", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2551", "a00260.html#aa730325a4ffc0960a7d33cb6a380600c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2552", "a00260.html#ae176c8c6b4979e3fca15a13ae4b8e05e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2553", "a00260.html#a92ffe8b2cdf5ee8f5cb7aa99a10bd4fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2554", "a00260.html#adddd4baf09c3e64c7c9e2fc7fc6cf872", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2555", "a00260.html#ad5ebf313d04b5557f3b3a49d8acb051d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2556", "a00260.html#a566942880f0ac67d9d0322d32efedefd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2557", "a00260.html#a75d3f665350d4d1c290682437fa7784e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2558", "a00260.html#a69929e8b00938b3a1514f74c0290a338", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2559", "a00260.html#a5882031c905c6397d5bd402e7ef70d3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2560", "a00260.html#a33071ef459733b33c1e59e02e356594e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2561", "a00260.html#ac113b9f0e40b265bf24ead28f705fc93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2562", "a00260.html#ab04c6c40eb8d9c18dbae401eb961f224", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2563", "a00260.html#a18d7e61093026c43972b8a8934bc98b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2564", "a00260.html#a005bf0870c5f084b90934189896835fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2565", "a00260.html#a65ff37a266083c8082fa4dcbd7979451", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2566", "a00260.html#a713540cd20457af7986fd8d7dbe30d26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2567", "a00260.html#a2232a7baed11f92189e8019208b699ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2568", "a00260.html#a10173551a5006aa98479f6d4090940b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2569", "a00260.html#aed5e5696e303c29af792c18e12818e14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2570", "a00260.html#a4cadd901154a9fb882e9bfca4ae844e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2571", "a00260.html#afdedcf1680a48bfde986963848901379", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2572", "a00260.html#a8222e8f5be12b5a8b44a2b8949fd81e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2573", "a00260.html#a7ac535f1a3af94ebd5ec11f2eaa979a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2574", "a00260.html#adc2cf36b7e609c29640cd7c708f998f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2575", "a00260.html#a1be11fad66df4dac866970e6e44d0b3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2576", "a00260.html#aaafe609a0c3fa41a5996c56fade876de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2577", "a00260.html#a51531c77648338e3a76fca34003658ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2578", "a00260.html#a5aa2cad8b3eb404367cf9906f9d2fbb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2579", "a00260.html#ac222588138b3b4025b66749058f866ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2580", "a00260.html#a9ea3962a6b39e08481442cb0510f3393", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2581", "a00260.html#a39208df496a46630af778d776871cfb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2582", "a00260.html#a1a7eba4afdd99bcd40c82e4d82afd9da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2583", "a00260.html#a2508cb670b205ccf662dd6e4361ed310", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2584", "a00260.html#a337d043680c76a37afccdd52511c5938", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2585", "a00260.html#a9dfe72194e31011ef3b960cf6d789fd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2586", "a00260.html#acd28f117f19bbf70845e35bf2e6ff9ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2587", "a00260.html#aa9c568907615fd75bc9e965fa665a5e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2588", "a00260.html#ae51105bb9aaa27ddfabb3a8cd8b61666", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2589", "a00260.html#aaca1def76ab29cb46267149e085b0965", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2590", "a00260.html#a000ec835dbf5c338900503b2f0912887", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2591", "a00260.html#a2577f4222dac0869719e7bbd1ee68aa0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2592", "a00260.html#af6583ef854c72d5159e1da5ac3f76909", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2593", "a00260.html#ae2b164c836b5d3bd7a71d6d27a675318", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2594", "a00260.html#a511fc695596e27f4c560805f6de28ad2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2595", "a00260.html#a6d7cda699cb671848e58a048124cfa8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2596", "a00260.html#a4372cafaebb89d7994e1c472be12245c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2597", "a00260.html#a675fad626149009f2b08ba4e47bc713a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2598", "a00260.html#abf12ae74c7d1a36973a05f3528bc81c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2599", "a00260.html#a19e2745bd0fe12de02115ae437dd5dca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2600", "a00260.html#af8d6c27162ec7bbe6922aea774f2b1a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2601", "a00260.html#a2c9b68e8176122fd24c843ab7c9cc1e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2602", "a00260.html#a9d5aea264168b38e43cf849501058a82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2603", "a00260.html#a931bc8ae3abfade307d569eec1b55cfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2604", "a00260.html#add96ba331d171f1ef2988f4bcde91271", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2605", "a00260.html#a4427d7a482d44435810bf87ebaff80c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2606", "a00260.html#af86ce79423803e09c5bdcbca95a9dad4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2607", "a00260.html#a228968148ea09c544818ca0cca7b9291", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2608", "a00260.html#a5e3ae6f21de52986e9e6b2f68c1437f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2609", "a00260.html#a8e769076a70d545a62b7bfa04a5cc43c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2610", "a00260.html#ae972ce5c7da65d2536d8ce24536f0402", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2611", "a00260.html#a3faa107c2e3583f37734408a9fc8ab77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2612", "a00260.html#a33d4825e4a7929443476e146cc7fe351", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2613", "a00260.html#a6d1b144d251c5e1d1f31c0ac7b12fd03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2614", "a00260.html#a22f7aa2593539358fceb6065fb999e5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2615", "a00260.html#af9d9d31b5e135ec497369a72976a5cc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2616", "a00260.html#a1281d5fe84c8de5a7d04e9b59acb5f1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2617", "a00260.html#a6d3cbca83f3ca9323c963de27bf9ec07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2618", "a00260.html#a28c7a8e5b41f849a33ffba66657d71da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2619", "a00260.html#a4fc6bba3256470408736affe26eabb1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2620", "a00260.html#a6c71c0c4198c1d973065bf5924ac3d52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2621", "a00260.html#af73c7930df3f378466bb1f8c73f2e3c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2622", "a00260.html#a156781182bbe19bfed95fcab8d6ba3c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2623", "a00260.html#a3e8df1ee0529bf9e17a9975ed4886560", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2624", "a00260.html#a0065350707112246504dcc332532330c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2625", "a00260.html#a9c4270a8d2eb843b8d1082dc744aa9ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2626", "a00260.html#ad8916adb43a1d6fcb2880513aaec80f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2627", "a00260.html#adac117ebcded846ed2ed1ce3885329ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2628", "a00260.html#a6416f446b8f49bd81e13e43cf90cff0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2629", "a00260.html#a0d3d4ab560a12692bda4f89d62f5b7a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2630", "a00260.html#a0b9ea955ddc3f3421f71089e26ac9b85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2631", "a00260.html#a1ac4b5e8cdf7529636d79225ab912438", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2632", "a00260.html#ad58652bd34578b7c2bc7333c0ebfbbba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2633", "a00260.html#abc04fcbb82c1cd25e8bf7820cdb6617b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2634", "a00260.html#a7b0e4f88566cffee713dc6863b1c0d4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2635", "a00260.html#ac9d380da2c90d185534217b2d80cf84f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2636", "a00260.html#ae4671b9e6abadc0a0d1d658546970beb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2637", "a00260.html#a45470df9786d6640c1d61d857345bc95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2638", "a00260.html#a18bbadd898b9197570ee47d1c61a844e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2639", "a00260.html#a9f7acdd50b3cab835eb53a3925b1585e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2640", "a00260.html#aa24817e21268bfd2697da8a110a41b58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2641", "a00260.html#aa38ab5bd740bace6f4449bbc726b254f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2642", "a00260.html#a60df81fdee5680ae3ae05539588695ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2643", "a00260.html#a8c2b71994598f1f7ee3618d8bd1de07b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2644", "a00260.html#ac5f433f8332f443fb2d01e783a953597", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2645", "a00260.html#a59f6f890fbb89dbc69a977ac3654dd0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2646", "a00260.html#aaed5ae49415666cd6a97739fb28b4bc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2647", "a00260.html#aa531d8ea0faac50b3d727c5d6440a1ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2648", "a00260.html#afeff65908d54439e2240d2968f1c0ecb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2649", "a00260.html#a6ce713bab85eef4c3c06ce4119dc63d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2650", "a00260.html#a24ac0923b0992e7ca89c23a923d1dad4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2651", "a00260.html#a6de88f383d207d8b2be6e9620a5a54d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2652", "a00260.html#ad8c31669ae28f59bb62914d3327053cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2653", "a00260.html#a83749b63f80e012b68be03fed7c84028", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2654", "a00260.html#a1b76265e21f1c37b37aee43bf6d508d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2655", "a00260.html#a4dbc4bee435e1941942a0d4cf3437094", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2656", "a00260.html#a7d2d91bdb855f11ef9ddf92b2b91393c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2657", "a00260.html#aa516687da83efea498ca0bc93b6a0a4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2658", "a00260.html#a88e72194a57b3f52124912a989cf403b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2659", "a00260.html#a47db4b8fa43d35c3b5a0ad2ef2fd50d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2660", "a00260.html#a9ca7d73f9887fe19e0579f694cd62888", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2661", "a00260.html#a18c51bf3feb5a7860d2a87a0dfe3d6e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2662", "a00260.html#a1ac659a8f6e41d6d418274c77ad9d7a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2663", "a00260.html#a3df2d05bb3a32c4a9a72a882b748e79b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2664", "a00260.html#a59748497f26adb356af658d40bf3a343", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2665", "a00260.html#a7716766334a972dd0d46df3fe11e7557", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2666", "a00260.html#a1bdad4b0117b3a086ffccf444cdc6867", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2667", "a00260.html#aa4a37e5fad27caff0c828603d68dbcc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2668", "a00260.html#a32a54ed78948f5f90a0d82786128945f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2669", "a00260.html#a6ae38fb9da10f275c574e82652f4bfdb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2670", "a00260.html#a30bc6ef2c79fdab1cb2e6caf9d656424", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2671", "a00260.html#a40917d2ad52e13f8e11f4b2ec444f20e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2672", "a00260.html#a73593810279a95ca064a0c8ff2c1bad6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2673", "a00260.html#a53949079a8ec9e10cc630dac91f99f9b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2674", "a00260.html#a6a3f49e3238f936f964efd46a9b7d023", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2675", "a00260.html#ae783986ed2ee08eae91f48143a7f9210", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2676", "a00260.html#a42883d5fac708e8e8d56ba6f69364bf5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2677", "a00260.html#a2232fa183193bcc812b28fb64efa8f0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2678", "a00260.html#ae79feeea52dff2d39af4730411414974", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2679", "a00260.html#ab0700645cb9c39caf2b8319b46c7e025", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2680", "a00260.html#a177c9538caf8bc0722c629ff17b8c5ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2681", "a00260.html#a6f449d947aaf7b1cb34f795d33992942", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2682", "a00260.html#a883f64f66bc2c6a01a7e3427239f5bd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2683", "a00260.html#acf0cffdb59f49fad6d632c0b60eb1d0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2684", "a00260.html#adab8d2f3ea4f9a660ef461ec7830c9ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2685", "a00260.html#a7f3781d19c4295200583c7b76648bed7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2686", "a00260.html#a158568a96178efa1b597d056bdd62895", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2687", "a00260.html#ab460e67002d2355fa60b1c188cc31b96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2688", "a00260.html#ab9d1f5397c15ce4fad9b096cc6edc56e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2689", "a00260.html#a0e57799183631d34758a42deb12da5d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2690", "a00260.html#acd3552a38eb058e8d53cabb1d6082b2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2691", "a00260.html#ae3ce6a2aad54b3f116d3612a129053dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2692", "a00260.html#a622392fb2caf8edf8ae6ea00fdc16f6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2693", "a00260.html#a04aa2c4108e0e8aee0dc988e9cf0012a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2694", "a00260.html#a5539a6cf12ee2b99f1455155ee80d68f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2695", "a00260.html#aeb791405bda3a6d60ff000b078809d42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2696", "a00260.html#afaa48ebbb7dd8ff989be09a6ecc7c37c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2697", "a00260.html#a5639684fbae1dbddf9d0d7c6ebf14b39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2698", "a00260.html#ac924eb0c311f614e87631241fa8752cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2699", "a00260.html#ae210e173ad024e03fd6aba92fe3e2f2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2700", "a00260.html#ac712dddeb73f42f7ef84b5dcaf172805", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2701", "a00260.html#aa31dfdc4bc45b4cd9c444179da8a74ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2702", "a00260.html#ae7d26dce24af800ac1ad6f65b27319ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2703", "a00260.html#acc6075cc7d0e0258170e376a427be2f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2704", "a00260.html#adf1592332923eaac09ff3d92ef4ebb07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2705", "a00260.html#ad1c9b161bd2f2a448ebbbd966d4e0253", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2706", "a00260.html#a2b6514cb4a23645eb3a4b39b8c160eb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2707", "a00260.html#afa274189a63d37b7224934570c56fcd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2708", "a00260.html#acc6a1d3e469fe7087a84ac53696c386a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2709", "a00260.html#a96a936eb8233f983da1a07af34c22aab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2710", "a00260.html#a94dd4abf3fa4b8da8db655522157d717", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2711", "a00260.html#a70447362210c7342a3970c7064fef38a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2712", "a00260.html#a553273d3b39a4ee847d0dd592bf45e9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2713", "a00260.html#a75fa1f3d84f1fe4487cc1a10806afd08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2714", "a00260.html#a294898a7f2fc4c38d4af2c47e2f638db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2715", "a00260.html#adaf18b99e1e6df7049d4e24fbcd99d0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2716", "a00260.html#a46819a124421107bb31ebc013e4a12d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2717", "a00260.html#a444a9da7614968a91f82632fc15aed81", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2718", "a00260.html#a1ca62ac46bc6dd007c2a175c78133aa8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2719", "a00260.html#aa5cba1ae0a3da6b7e387a5a96bcf2b53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2720", "a00260.html#a53bf66c412dd287e81c6f9beb9f92932", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2721", "a00260.html#a755eea7854a2bf2d6d89b5219dd24172", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2722", "a00260.html#a7507b43063e990a135fb55981b7a2f27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2723", "a00260.html#a23d24e18ed6f816d5be883378d512051", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2724", "a00260.html#a4d4f4048494db50380de6d757e2f361f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2725", "a00260.html#a61de0e89001346a7c0aca1221b742f86", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2726", "a00260.html#a526f45024bb1107676d9b18a75f712bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2727", "a00260.html#a11382074ced8202a8676bbad7bff4531", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2728", "a00260.html#ac4411957fa95d84569f697f12490055a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2729", "a00260.html#ab9237a0bf3b861a4924fa651209dc452", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2730", "a00260.html#adfbbb841bdcc77fb64aec0468b2a2703", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2731", "a00260.html#a6a1b8d55a006e78b560400f67d72d3d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2732", "a00260.html#acfc8a56a908e5897d452fbe32f1284ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2733", "a00260.html#a87d4abfd86da7695711f638b1e063932", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2734", "a00260.html#aca8c6cae08ea075f55d013f073ea5871", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2735", "a00260.html#ae2857c3e8e54fbc13691552f97ebcc70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2736", "a00260.html#a692af9413dba15b09b2d202f8b1bcfe8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2737", "a00260.html#a234abc22545a99e3e3cc68e88ff9e5a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2738", "a00260.html#af6284ad7cbc570edc1c856ac6cbfbe64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2739", "a00260.html#a4f7f71bee90dca3e510d4e0e804e4ca3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2740", "a00260.html#a2d296fb69d551374e59f4262b361c3f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2741", "a00260.html#ae7f1132969861e4dec4a1226d6bd78c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2742", "a00260.html#a6714620d0a2b16be370f4b76cac13a3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2743", "a00260.html#a22110a57f7231ca59bc3c9bdfd3e785a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2744", "a00260.html#a42282a4955e02ee9c0a02e8fbf09d466", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2745", "a00260.html#a11684fd74cbf3e7a91b0e24c3b3d43c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2746", "a00260.html#a46af43ccaf94c16b786f36f58d47b9bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2747", "a00260.html#a01d1a7ad18ce8e772017a9f96628ec13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2748", "a00260.html#a2e231b4e950fdfa5f06dd294911d0d91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2749", "a00260.html#a322044bced4ae48e733ddcfa485ca762", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2750", "a00260.html#a0287813f6f7597845bbbfdc4438764a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2751", "a00260.html#a72555902859ba779956c0ff81ae9fe1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2752", "a00260.html#a938f3006e6cebddceb70c199c8e72a96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2753", "a00260.html#aedf07907312003119d5d18d392caff2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2754", "a00260.html#ac809588e54e3d7774b1d94ac74ab7a9b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2755", "a00260.html#aaae5a9e26328e8dd6d761283de43eaab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2756", "a00260.html#a948133abab354a01ff4540bdbc305c78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2757", "a00260.html#af5c86a2cd7c7d9fcd575cb90290db656", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2758", "a00260.html#a99ec1484a5ce3e6f48ee0a62cb535f3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2759", "a00260.html#a3186e4d66413f19bfe9bc4aa523d7899", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2760", "a00260.html#af87e72b2d119687b96f7e819116b659f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2761", "a00260.html#a705a27bbf7ec38ff1f739ab3510b2c2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2762", "a00260.html#ab461e35f17e5e87c0b1ec1447c3544e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2763", "a00260.html#ab34453ce0f9afc3e53ff255cff14c9f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2764", "a00260.html#a04415101a2a63e581c019ed976587a09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2765", "a00260.html#a90a734405ac71a1ddcbac2d520f5e5c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2766", "a00260.html#a55ff613675b4ac1881735ccf3fff44ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2767", "a00260.html#a05838b7c7f2c8f882c3646f9af70e57f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2768", "a00260.html#a96f1ce9dba7da8cd7aed373c929eb908", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2769", "a00260.html#a91f3d8e225488c6ac434614e58272e36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2770", "a00260.html#a061c6fffcd5bb5ec100765bb8c96d123", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2771", "a00260.html#a2b3dfb57ac1441e02e29f5aa95bd539f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2772", "a00260.html#a2ed128edb363d29ae440261f5cc4e17a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2773", "a00260.html#a00821087842daea620fc8af545f81dd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2774", "a00260.html#a2302deb26074dfb5595c76a1fe859892", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2775", "a00260.html#a4efb51769be140bcb084acbfd0ea0d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2776", "a00260.html#a730d8d6ae88df72401b063383d279771", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2777", "a00260.html#a2b98bf1a3a316d1badf43d1712731c23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2778", "a00260.html#ac603fc7d3df95fe15f7ccf784f4f5d49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2779", "a00260.html#ad9257b29f0d00662ad14aeb4792d5e5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2780", "a00260.html#a431a539f90f53ad5e5898f2c08a2e4a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2781", "a00260.html#a613ccba8b9064b30182b1a5b5c229fea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2782", "a00260.html#ade3fc7a00fa0bf59fe333751ad2698a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2783", "a00260.html#a39395bd51975d93564d626cb99d565df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2784", "a00260.html#a8f0af23beb47ddf247c27fc80e5c21ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2785", "a00260.html#a7a7901169103a6a84c39e423a983760f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2786", "a00260.html#a00e3a4b3c061c58d9da413c28248be8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2787", "a00260.html#adff9d71dd48927db7821dda465ec4553", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2788", "a00260.html#ad45ca35e679799994bd262788b871843", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2789", "a00260.html#acf94ad57e060cbf4069eb55df34131d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2790", "a00260.html#a9a1e94cda9110dc67175c2f689b797d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2791", "a00260.html#a2544dd6c83ba73ab19016d0f090cd4f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2792", "a00260.html#a7d5c7b4724e205c07edb395c58e103de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2793", "a00260.html#a1a7520d0055c096062d32fc6437e71cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2794", "a00260.html#a323383a121f91e441f792e93ffa40e99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2795", "a00260.html#a2701477d7e7d72dd33f6042354ace5db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2796", "a00260.html#a42039d2d43d34520912914f6d80f1424", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2797", "a00260.html#ab6851b5925dab7931c4c362250154ff7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2798", "a00260.html#ab701130dce8c8e99b9ce7f1f57837e91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2799", "a00260.html#a7797d50c59ddf9d64a7884ddf054e8bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2800", "a00260.html#a6694c4746424d1c701c59ad4c51acbf9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2801", "a00260.html#adba54f75f0cf4a8f1d00c82e46714f8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2802", "a00260.html#a93b8a2bc9fddfdd200a01c4a90f21cf2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2803", "a00260.html#a5f10f7ef96c2620f621845820eca03ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2804", "a00260.html#aabaf1100da85fac53f283d2c10eb5083", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2805", "a00260.html#a593b6fc16a367598e9b59068c2ff2918", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2806", "a00260.html#ab39ada62408a617a397378ca85523936", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2807", "a00260.html#a64b368e8366d040732665a4fec7ec1e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2808", "a00260.html#ac6fbee918f494808d9fec52db7c45df4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2809", "a00260.html#a049152b39317a49928c9fac306efff1b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2810", "a00260.html#a0e1345db854449cb0578b530f6be5f71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2811", "a00260.html#a4ba107be14eda85f3bc5820cc438cf4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2812", "a00260.html#a8e71881bc924a498b8f1b3dd20654065", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2813", "a00260.html#ae04a6f6f699b0afaeefef63b987e6aa9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2814", "a00260.html#aa71f145c75ffc1f23f55aea98d7709ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2815", "a00260.html#afff7f873bf6e8844f1cbcaf8b7c295ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2816", "a00260.html#a0d04f911da1cb6028c43a57c4af59882", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2817", "a00260.html#aa2e7e4d9781ae6c1b4f9ee3069f47b26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2818", "a00260.html#a9e80c33a06176e15b72b8b0705a9019d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2819", "a00260.html#a6b64ec3c849adb9344295deae41e9860", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2820", "a00260.html#a2f05d8a4125ec3827db7f3d1ac2a62d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2821", "a00260.html#aaa183e1351fb072e33e8e5c94a9a08e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2822", "a00260.html#afb075c0f23bc63080c23121e26286785", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2823", "a00260.html#a7125b59742c6a0ecd04dbe3350c923a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2824", "a00260.html#a9b40bc2605e3c2d939fd9185f45d6235", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2825", "a00260.html#a737cc1a3d4bad52901193948959265c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2826", "a00260.html#ac067c414a67c154ac07ee7af1cb68430", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2827", "a00260.html#a163cd8b345f7fda7fede591d75d06b25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2828", "a00260.html#a7ff96100dbe7cb93fd42c7cfac06cad8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2829", "a00260.html#a20c4f140df6f2cb5836457a921c29de5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2830", "a00260.html#a7eba0a3130aee6b366bd5186e720b8c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2831", "a00260.html#adb8cda7f052ffeee171629137e17aa8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2832", "a00260.html#ad4e752fb24f4e7bf7d4d9eae922f2008", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2833", "a00260.html#aaa9c01ab7a4e2d903dcccfc50166a487", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2834", "a00260.html#ad6b71701d01dacef6b01191e807bc2f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2835", "a00260.html#a2a9756a8a44b44d2ed1ee15e21594733", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2836", "a00260.html#a6551c42b18f9043d4ad922bf69cd35b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2837", "a00260.html#afa9695bcce858c620538d4f19f4d5a0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2838", "a00260.html#ac2453f3f46d775bcff4d2427950098eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2839", "a00260.html#ae404e0cc9777c149e2e718bf95db2602", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2840", "a00260.html#ace3ff9993fe29db217650e275ed9af31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2841", "a00260.html#a9529f2422684201fb4f486aa26aee890", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2842", "a00260.html#ac31da581559499810d8e81e6ad0dd7b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2843", "a00260.html#a32e54a2d8915f146ad233a14b54d5834", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2844", "a00260.html#a466f97b74bf2c948d6a0fcb867cb5ff7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2845", "a00260.html#a55be8fdfaed46cf9f5102d7b63ea5b95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2846", "a00260.html#aec435d1d136b80b6df56b66601c53408", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2847", "a00260.html#aa07413cdbd7db604f5cddbeec04ad016", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2848", "a00260.html#af54855beda0ee0151d4d7c2774063d03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2849", "a00260.html#ab65cd937313df7ef5552ce9b5edc0ce1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2850", "a00260.html#a41906a04a3c211e3569530b48084dd54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2851", "a00260.html#a78aa294482b1f20c7cb8a1e8e87be9c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2852", "a00260.html#a82b9208f53b687e0a5e169a7e5fbc101", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2853", "a00260.html#a3a2dc5997cdd20ac5058b248a3f87daa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2854", "a00260.html#aef5030c96fc61315abbebe8e6bc7c4bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2855", "a00260.html#a9f8482d841701c575630b2d829ccf910", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2856", "a00260.html#adf0ed174f6b03566d3e34e6fa8e3dbc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2857", "a00260.html#a2eb4b444dc997456efdebf781b43bfb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2858", "a00260.html#acb2971000d5fd8e19ab5d1f7dc75fd5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2859", "a00260.html#a4234a18cca13a7fcb2742ba882bd365f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2860", "a00260.html#abb0d1b172c7e68a8349275849aa0c7e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2861", "a00260.html#a6ee3c783ad58fbc65e134bc12e1a9b04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2862", "a00260.html#a29578c26bd6b93279fe1b15b77a8e5cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2863", "a00260.html#a84146f70c07cdd565ac83c65a853f9ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2864", "a00260.html#abc3a21e2f6316562cec0767349dc4a33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2865", "a00260.html#afedcd31c8654131a31669a360e2349b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2866", "a00260.html#acecad29d968ff52c78d636057aaa55cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2867", "a00260.html#a38e6b91a2b0270f19619c502b607804c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2868", "a00260.html#a7da117ac724a9a5da4a1ffb00a95251d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2869", "a00260.html#ab96ac8957c4e4a17958bced857495921", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2870", "a00260.html#a9ea2ceeee04a35dc96f488ab0500edc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2871", "a00260.html#ab681caa1d6f147b6c2076712d610a13e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2872", "a00260.html#aec863452d15782552ddf914013f624ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2873", "a00260.html#a9eb690b868a253ad5888d1741181017f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2874", "a00260.html#a13ff51b5a7c3d31769ca7c2b4e530431", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2875", "a00260.html#a5dde422b673e9c36378eee191328539d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2876", "a00260.html#a1bc6c16b553227940fb7759f87a9753a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2877", "a00260.html#ad5c0edbd2a8acc0079ebbf6194bb0104", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2878", "a00260.html#aa93c0bafd1a01b3aae96aad4ba2b5fdf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2879", "a00260.html#acf7c1c473da98eb29e34e9adc24bfa1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2880", "a00260.html#aee3312063c1bc03d795e38f9177fda40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2881", "a00260.html#a9e00578a6397e60d60de081a2aabe774", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2882", "a00260.html#a93cf6bf0ed604fa4d94911a6cb196dab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2883", "a00260.html#a504b198e0bccd106ec0fbbc0827e0f8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2884", "a00260.html#a9b042a74fcac544d18b64be31aa83c5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2885", "a00260.html#a1573bf9e23eee8183dd90d453288d36d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2886", "a00260.html#aa42e5136c8e098399edd8140bfff6a9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2887", "a00260.html#a36c4bc9e08ee24ada151dd1d9099e4da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2888", "a00260.html#aacf6dd5706a1d38db61b42a64a8179b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2889", "a00260.html#a51ca909e3cc2744e9e6bc2acd350f0a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2890", "a00260.html#ae44eb0b5f1b30ccec47fadd4cefe015d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2891", "a00260.html#ab95a6ac68bee2503485e7a13d721e413", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2892", "a00260.html#aaad46c49133a1ed0d431ad5433c05dc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2893", "a00260.html#a3027a2c7f1f402b9db99e84da1c3cb12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2894", "a00260.html#aff0104fe1bcbdf27e224d040e5949729", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2895", "a00260.html#acca45062478acc38f6c26aaa3fa78e22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2896", "a00260.html#a60dfb969be46a495b128c1d2846b62f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2897", "a00260.html#acf82a84bcf7fe4c4935fcec0affc59e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2898", "a00260.html#a512a8fe05e50a6182c58e1a458101820", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2899", "a00260.html#aae93501d531965af6ed9194835a9ac2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2900", "a00260.html#a276199cfb662a5071efbcc46232eb723", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2901", "a00260.html#a02ff9b7b1a483b75ca0b281cce3d5ef1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2902", "a00260.html#aeec41e2625ac3e39b551ce0e567e91ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2903", "a00260.html#a1ab56039bdac0640d93ff957f8d07ec8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2904", "a00260.html#ad18b6847450cad0718b98271eddc6e44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2905", "a00260.html#a30be41db8d7150b603306b6d78a6e69e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2906", "a00260.html#abd7970db06da01199e9b23621ec77cbd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2907", "a00260.html#a405afd3fb4fa3174090a3ca847db34d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2908", "a00260.html#ada422b7769a40ce2f39d91097d491143", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2909", "a00260.html#ac89e1fcdce6f702022738a32d4ec5a50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2910", "a00260.html#a6a95415f1d20454b69f26f719f48ef3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2911", "a00260.html#ad1e990c7dd2397e1ac84c77ac70a8cc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2912", "a00260.html#a3c055ab49f49a8a98cb717d5a5a3fbee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2913", "a00260.html#a25f42f5208e574041a1b79a66e38c810", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2914", "a00260.html#a781f0957d1fa95a8e7e2ad7b74da7e74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2915", "a00260.html#a5f210002b2b8f88f1e6b1383a98e7b12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2916", "a00260.html#a7aa466a819e74d70ada431346cd4d93b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2917", "a00260.html#aa9948f07e9f3cdd9087bf6ee9a8fafbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2918", "a00260.html#ad37d71b64f4f66960924bc17294fef1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2919", "a00260.html#ad3bc37e28d32db687b8a0559b2d5355f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2920", "a00260.html#af2cc45169409adf9b34983abb273beda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2921", "a00260.html#a833ffd504c61dfc10fa1d5baf244261f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2922", "a00260.html#a5fdaa466728f40b6f079536a2c6e4cd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2923", "a00260.html#a1486e7dd1f9fc132d941e4f51b124fcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2924", "a00260.html#ad5f4ea70b92fabd042a57e2434950b4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2925", "a00260.html#ac29bc567772ea5f1d7504678c75fcc7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2926", "a00260.html#a656e03985286f5366fdd303f34c24b5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2927", "a00260.html#ae4aa1fe9122310863d23075509e73f35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2928", "a00260.html#a81b37ff6fdcb4f35a2fd70ea1024366a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2929", "a00260.html#aff3c443f83f52779604ea2809d1ede07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2930", "a00260.html#af51214c42b86eed24b1b18c94f0e8c44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2931", "a00260.html#a889f1f577093df13d3de24b6248f1f57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2932", "a00260.html#ad499b8c9ae65d354c7ad05c1eb19e1f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2933", "a00260.html#ab1a2db257e19af81ecb0b110809ac03c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2934", "a00260.html#ab19f9a81095e9a84d168dccfc20820ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2935", "a00260.html#ad116594ae4438584ba3f1640cbbb78ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2936", "a00260.html#aae2427fbf8231130ca0ff4c22a0f0371", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2937", "a00260.html#a767a9bcfd6749a60ebe3e328f1c6cb2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2938", "a00260.html#a1441f5116cccffaea740c7ed60487d73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2939", "a00260.html#ab9354bd9f59bd0cd3df225241c4c3e03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2940", "a00260.html#a5b63a5f376fb627893e4f5e1ad02a270", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2941", "a00260.html#a4dfb7dbf9dee51fa672c977d5284ffd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2942", "a00260.html#a792d6769c96e3bcc8889fe4b6fd88f70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2943", "a00260.html#a219d777204cf0ad41f039fc8c5c9c4c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2944", "a00260.html#a47eba43ecd163a2b8df5c0698628fc08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2945", "a00260.html#a12216090ab5aa54e23018a511096cbda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2946", "a00260.html#a212e49b7746c43d7ec79533484e88785", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2947", "a00260.html#a833d42f433561c4e81f3f54e06d845bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2948", "a00260.html#ad737197fbe28b0b886074c8f3540039c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2949", "a00260.html#add744738f378f7d55851dc5778938308", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2950", "a00260.html#a9bd04a93da3d8d7bb7a58d41e5f5ca31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2951", "a00260.html#a999a231cc25b0d5ce633fe413c4576df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2952", "a00260.html#a56231d02af1478c424eb4236d2dd983b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2953", "a00260.html#a21bce1e9c064006476c75772d42a4367", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2954", "a00260.html#ac4c81ca8665cc639fc33433b73ed32f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2955", "a00260.html#af61dd152824bdeae0345ca3544b28335", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2956", "a00260.html#a06ea3feb808d5360be79d154a5f3ddfc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2957", "a00260.html#a32c590205dbb0eed92908541dd3026b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2958", "a00260.html#a67163fb874f66f0d3eb7964956b258eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2959", "a00260.html#ae72ffdd1244874f9c8f5069bc3413150", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2960", "a00260.html#a4c200efff05d666cee7821a58debe3e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2961", "a00260.html#ab1f791f5a442a90546d3c63923e44a23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2962", "a00260.html#a81bb1fa7944f0b0685c4709805d02b92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2963", "a00260.html#a96903eb239d888cd97a1022e44fd3631", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2964", "a00260.html#a57cb9912ea2974266cdb20a6c6bcd9db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2965", "a00260.html#a625619683dccac922d72ccca789ddb3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2966", "a00260.html#ae7b2228f46ce687e05b0468fd97a8b3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2967", "a00260.html#a4aa8c88b31c56516c19fd4765881ae16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2968", "a00260.html#a398fcd9554e3f092bb155b88ba9ea983", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2969", "a00260.html#a6a7f39940e64ac7ecbafdbe709eef489", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2970", "a00260.html#a6bddb2983171345fce55b49cf2d28c7e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2971", "a00260.html#af21b528d0cdcf9304f413e922446ede5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2972", "a00260.html#aafa7e3a1d16f7cc9f0951314fb81aef5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2973", "a00260.html#aff0cbf40ffb7b96b0c6d6b90898d6467", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2974", "a00260.html#a707598e77d358e265c0eceae1914b295", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2975", "a00260.html#acf5f81a866f85ca0eb6aa1d99d410160", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2976", "a00260.html#ac13f0bddd5044672d0a3c16986ac9b30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2977", "a00260.html#afa58bfd3513648ff7c56ce49cd62ecbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2978", "a00260.html#ad10c99b97de87b2f3fa820360a2ec392", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2979", "a00260.html#a8845b1d0c0000f26d76b855f375c7c60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2980", "a00260.html#a243856cc65b8479c9bb8cbbc2936e3e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2981", "a00260.html#a264f95ffd3bd933172f0e68e5e122868", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2982", "a00260.html#ab79d21fdeb904a3bb249a39ed5b19543", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2983", "a00260.html#ad78ddf3b3a813d262857267fa0ec6d37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2984", "a00260.html#a98176cfc54ef68fe507bb44d01c8ac04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2985", "a00260.html#a7df39a7f90c436f312202b97faeb6b2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2986", "a00260.html#a29a16846b4db81db2edb7d3b66087d43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2987", "a00260.html#a894eeb95e20856f0d1b3f2571ba0d5d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2988", "a00260.html#a027d89dd31efff2576635cb69c6086da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2989", "a00260.html#a56185f76eb84ff5d3efc9954242d6b37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2990", "a00260.html#a4e7aa05df5195c07bc5ee93a2289b769", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2991", "a00260.html#a1820979442ca569cd813937ed6c21bba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2992", "a00260.html#a531ce56095d517ee43cd484673ac1120", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2993", "a00260.html#acda153e62e96613eb83ee78cfbf9f35b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2994", "a00260.html#a9994f6cf9fd7ce647c33720f31ac4f1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2995", "a00260.html#a2eb1a895439fb0f010b11354c5e96e74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2996", "a00260.html#aeaf2ef58fd07995afd5babdd75789581", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2997", "a00260.html#a32ced4f857485640fd68b310ab9a9eb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2998", "a00260.html#abd9fa98f27bf911d2e5e9d6e992bcd5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2999", "a00260.html#ad427fbf63d740f026b677ab1fc053b75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3000", "a00260.html#ab084e70b09920e1dd066759968e5450a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3001", "a00260.html#aa52a0273ce653fb1d46195ebd37abfb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3002", "a00260.html#ab0259905d3a30715e33bfb48cc5e5c30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3003", "a00260.html#a6eee7017085109b7b590e969aaf5415d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3004", "a00260.html#aed20a532b8f48e7728c4988ceaaa9c8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3005", "a00260.html#a59ca408f52a6fc48d0adcb9b27435357", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3006", "a00260.html#a7d972fd1c86bbb8ef3221f14248eca3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3007", "a00260.html#a0b631b71a2ee235a9c7d93ff74ae7a04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3008", "a00260.html#acc3dca48263cc4d369314af9ea71830b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3009", "a00260.html#acb887070cdef18223e85f30a166b50f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3010", "a00260.html#a107cc48f0da892f51d5c6eeae8a1521b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3011", "a00260.html#ad75e9b14898f5e6aedbd0f11ba188d47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3012", "a00260.html#ac8b2e388bc29bb6c6c0120d8638e98ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3013", "a00260.html#aecf24ca68b011a2e9b30d88d715c2507", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3014", "a00260.html#ac9e588c8440b05a7b63d781dcd82684a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3015", "a00260.html#ae5148592fc7b1aa49d634be9c80bf9e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3016", "a00260.html#af7f2def8756d41f70a8be4d900c105bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3017", "a00260.html#a31d3d31d2d6fb916aa569c03835ecd2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3018", "a00260.html#a7db88f627e9e8292977e0dfefbc19248", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3019", "a00260.html#aaec16fb668a3b60470ecfd09b9f9e33c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3020", "a00260.html#a1c463bbd0f7b7e80857d8d58c339c3ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3021", "a00260.html#ad9671dbcee6480cb4980096ab31d6f8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3022", "a00260.html#acaddd21d6a132cbbe19f4928429a119b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3023", "a00260.html#ad5ff52d9dfe2822ee97120294e04ed8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3024", "a00260.html#a604a8ea8fc5ef2578bef0da1d3152b47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3025", "a00260.html#aeeb4cf004f18dc50c629f0f677374a62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3026", "a00260.html#aab0ee27891050e4bdd4a75f7b8703ba4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3027", "a00260.html#a37037e9435ae115ea6f84d3b7217ee40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3028", "a00260.html#aa4b23a3193ced810e046d30b96b37fa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3029", "a00260.html#afaa748d750445fff80c2975ed6b18a13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3030", "a00260.html#a07a2f0ecb7692089320906a907d6b8ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3031", "a00260.html#a4eaa1edd8c0376c9b75e2b368a3b8e46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3032", "a00260.html#a7f9620bf881b1eb2d858d1cdb649e35e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3033", "a00260.html#ab431682d6d7942cbd0b632c1edf96863", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3034", "a00260.html#a10187f06418a5e90e6c2c57fff0d4c99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3035", "a00260.html#af0a01605c392c937121c472fdd974571", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3036", "a00260.html#a79073f1628ec97be6f562695afddf105", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3037", "a00260.html#a0f5cf17be8b2fc9627ad9bd883997635", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3038", "a00260.html#ad51bb1ffce492e29d4b7185c6fd1c249", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3039", "a00260.html#aea4255024d894fcffa6a15b44a6ac521", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3040", "a00260.html#a930e4fbc3c19b448e45193d9638df95e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3041", "a00260.html#a188b151f7191deb5d87c631b182d7290", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3042", "a00260.html#a533e9bb8f42d01f3ecca1d37200a1c5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3043", "a00260.html#a18a13ceee7c6118269e805ba6a42f0e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3044", "a00260.html#a633b7b0b6fb19668abbfa89946044d6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3045", "a00260.html#ac9f86c3e5937d32ae79c68846ada0105", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3046", "a00260.html#a4319454664b96843983ab1d0993f9af7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3047", "a00260.html#ab77f832e8024ffe628c8f4634f25d114", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3048", "a00260.html#a70f6e995bdeaef8d162d585d2c29b9be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3049", "a00260.html#ac17d8b2074ac5972d452a1a9b4d5fc96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3050", "a00260.html#ad15c6aa58baacb617bc1bfbc7671db0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3051", "a00260.html#ae48c32320cd43736ccae8d016cc184d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3052", "a00260.html#ace1d0364b5773f32733b875fb6ee9a61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3053", "a00260.html#a2049bdef0004e22c41856185daeb59ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3054", "a00260.html#a7766720e12a19783cc5ac9cd3a87a434", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3055", "a00260.html#a32e212d22be247e385b90315f6a1e903", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3056", "a00260.html#a7643542eb7e7b85a46f2d51527940a90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3057", "a00260.html#a770ec6fbf03a8ee73b516ead7ad7122f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3058", "a00260.html#a31e5f2ca39f12f0833665ce7adbc98be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3059", "a00260.html#a89b40ba0a400f5825945eac720215790", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3060", "a00260.html#a5a56cd8b3ce517ed4b862bb6aac764e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3061", "a00260.html#a914447503cd9ed4c13da73a64c3127f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3062", "a00260.html#aa419f50f427a8621e7e793b575f4bbf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3063", "a00260.html#aa5b3d7ae023b06e0790938ec0ef5fc02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3064", "a00260.html#a1689a62b0ce0299e9f27602ab55bb555", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3065", "a00260.html#ab806ce325c70a016f5af44f4afbeb16a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3066", "a00260.html#ab7162e1a395ff58d9704cd6f6bbab130", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3067", "a00260.html#afbdf20191adbbca695193f6912e7adca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3068", "a00260.html#ad0ceebaa620e6eb036baed351c045b1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3069", "a00260.html#ab37b8d157672f9fd43cd2273bc0856a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3070", "a00260.html#a02dd022b2482fa9d4f6a523cf9d3b28e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3071", "a00260.html#ac62fd1b06b6c2c9a715a8fac7ff661af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3072", "a00260.html#ae062a77dbd18f5c5e69f7ac8f626c68d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3073", "a00260.html#a6a7270664f7ed72e22bef64053af4a5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3074", "a00260.html#a63ab18c0ba610dcc0f08bdd09749af20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3075", "a00260.html#a20333d4adf354632676beba0b4bbe35a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3076", "a00260.html#a94a4d32986e7f2f06781f065f41cee47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3077", "a00260.html#a05b90d4da85c7a5353dabcaeb6961c06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3078", "a00260.html#a23ed5434d78f09352c5fe445317622b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3079", "a00260.html#a1d6d860b28bd12e5ce773be931622238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3080", "a00260.html#a56a440fa0b723413e2981a696ae3e52f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3081", "a00260.html#ac50897d46aca1ebc2d592defb5f6c3a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3082", "a00260.html#abee52f629839bdd5e66375774957cf6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3083", "a00260.html#aa25fb0dfdf5b0fc054435c607078273d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3084", "a00260.html#a6f63cb81bd97fbd7bf1106789dded34d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3085", "a00260.html#a2128047cdddf030501b2123515714f29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3086", "a00260.html#a0950e896fbbe19301609c518169c3a1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3087", "a00260.html#ab8c992d49197047418909344e9ded95f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3088", "a00260.html#ae4c1dc4f99545449015322c716dd52f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3089", "a00260.html#aa66e65a096ba51342e9be40cf3515424", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3090", "a00260.html#ae1321d7a4f5ab031f19f4f87a6ab4978", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3091", "a00260.html#a53141696dd2e51fb6198f2d6f432d5ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3092", "a00260.html#aa8fe4ef08755bd2a3a376ff0f08ca9a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3093", "a00260.html#ae3a4f0a937441c262fba11fb5aaa1405", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3094", "a00260.html#a4a25080f6b330d057c370dff2787d26e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3095", "a00260.html#acbb59c524221f07df3b8daaab1a8a238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3096", "a00260.html#a2975cce041c06520bcc836f815c690a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3097", "a00260.html#a7a3389a233bb5460d23db7272e4d25cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3098", "a00260.html#aea27180c5cbec14a051a6b741018e7a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3099", "a00260.html#ab240b935aaa308b710b7fe683703fa1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3100", "a00260.html#aa74ef4d68e68cf0553bcb75b48564d09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3101", "a00260.html#a802c77dca31fe617ebea9ba735f0a25f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3102", "a00260.html#a20e148644c005b41021a8843327ddcfb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3103", "a00260.html#a8453ef58b7515f108076368eaa8c66bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3104", "a00260.html#abb291ac98fbf016076c47073ab98feae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3105", "a00260.html#a3d4654721715e427a18682caa5847e4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3106", "a00260.html#a44ebba87919f7e8741307d372faa7b54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3107", "a00260.html#a503a533315634aac50917f6e53662e2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3108", "a00260.html#ad9edb6742ef22afe7143a33c411a53fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3109", "a00260.html#a1402ca842a8b732ecf438032e68e02d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3110", "a00260.html#ad16e754f86dbb5b52cad70f21220ba78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3111", "a00260.html#a5e4d6887f73f92fb5f06364409f0da23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3112", "a00260.html#aa65dfbad70b13040933b690b0a2f0528", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3113", "a00260.html#a7a9cea91d7c8786c74483c28f311a367", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3114", "a00260.html#a054e8353fb240b4cbac2e7f24aae4a8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3115", "a00260.html#a640e0569ab3e8adef4677bb0df01eff9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3116", "a00260.html#a2679dfb61848dc4f6030ff45f7721f97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3117", "a00260.html#a8b3daef3267178abd22e87ff4200bce5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3118", "a00260.html#a35cd920e814d57592087f957899ebc0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3119", "a00260.html#ae0158cec802bbc95dcb55ae1c552d93f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3120", "a00260.html#a0f24d93a0275700d5b36d5e2059d2a9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3121", "a00260.html#a28b5185d105b090575b4d45815f7ed92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3122", "a00260.html#adee8bc57d582a532a1fb0fca09ccd97c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3123", "a00260.html#ac818266a7d97260666d4ccd7afcfb6c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3124", "a00260.html#ab093c445a756c77ea42c000ec3e3de0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3125", "a00260.html#a716d544a9e4e441f0aec3a95c5dfd96b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3126", "a00260.html#a3fd471abcc0ac8a4d4c574b878785147", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3127", "a00260.html#a5cf9b977c0c8d6441cbd796596aff402", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3128", "a00260.html#a6a235265c7ca9aabcb69c18dd006b6ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3129", "a00260.html#a34646bae1843cd4f8b486b62291be1ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3130", "a00260.html#ad3a3d664f15308015d7909f66669e045", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3131", "a00260.html#a55b3ab0f0f614b75ad958295ff9c3ce0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3132", "a00260.html#a5516f39523eaa796b3f5c3a97279ab1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3133", "a00260.html#a3b1ddac1b788d03618aa937ce16f0832", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3134", "a00260.html#a76cfd8d4aba18cdf7dbbe0320a08235c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3135", "a00260.html#a0beed1b6505aa1dc804b3e989bfaed7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3136", "a00260.html#ad61fd5e619a8feb54c623d3985c24fb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3137", "a00260.html#af64961adbf9544a13a528ef7a0457585", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3138", "a00260.html#aa859242706787bf49c37cc015b12c7ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3139", "a00260.html#a1e6d251524fd930ecd949201f5995775", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3140", "a00260.html#ac85b8481e32135e154be4b08c2eaabe2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3141", "a00260.html#a099f03d9f4dee8ad63a50449eed03314", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3142", "a00260.html#a6d7b67f71eca7d93b8d9608d29824a0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3143", "a00260.html#a985c63aa3eb8acff30dc52c91bb9c3f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3144", "a00260.html#ab32f62c72a66776d7a05546af3df497e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3145", "a00260.html#a75c720548046e1a8789514c6f6b0fca8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3146", "a00260.html#a1dd8f892c17d89f0cc74b78f6fb34855", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3147", "a00260.html#a4b8417f8103cc59dbdf90a03b6d1098a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3148", "a00260.html#acec4dbe01d677efed7b6ef3abaefcaff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3149", "a00260.html#a356655f643662d14b9dadb0218b15f3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3150", "a00260.html#a5a9a2616bb8acb7463652282d2cc44bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3151", "a00260.html#a44da5cb9b82065c85a84ab1992142793", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3152", "a00260.html#a0fcea0ce0924b95fa090f8beaf8821d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3153", "a00260.html#af5941b576542f2563d1019979ab16f03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3154", "a00260.html#a84165c79d8e65257c9984ce88c6545c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3155", "a00260.html#a80945d0003748bdf68a7010c83a39a97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3156", "a00260.html#a25bce5ebb35d2456f0720e3d831a1d75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3157", "a00260.html#ac339aa3588e5adcc5394f3a68df17939", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3158", "a00260.html#adf9c0816ae51fe03836b785485b42854", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3159", "a00260.html#ae5b097a7a426165ac027533cb9ee1522", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3160", "a00260.html#af76b4d4163b74ceef567f552eb6649bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3161", "a00260.html#a483e36f1af40bf8ae2dcdbcac358b59a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3162", "a00260.html#a2a10b86bf94dfd1a58eba3e0fcfb57c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3163", "a00260.html#a357fec9e7c2cf8d80ab24dd69b77b915", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3164", "a00260.html#a6aec3ee1a1c2489ef6a845cef7951b4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3165", "a00260.html#a491379518973083c20566bd17b848173", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3166", "a00260.html#a375d8113803697632a28a90a25caea3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3167", "a00260.html#ab7861cf0ab0141a6f0c0948934a4a6f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3168", "a00260.html#a90f222fb1f9df70f2acbed15e35b7bc8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3169", "a00260.html#a92c675d73cfdecc280a0ac3529470e33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3170", "a00260.html#adb85d276585f6b3e85e9fed0bd700642", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3171", "a00260.html#a461b2fd4fff003fbd4d6cd300cfcb54b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3172", "a00260.html#a2bcceb0a087caf486dbf1c6d3e54e1c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3173", "a00260.html#a3ac60358f6c4868e23885d330777a47d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3174", "a00260.html#aa3c0f09b3514384770231f12f01c4493", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3175", "a00260.html#ac5d38856ba2f97f6549a3c2baa27d687", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3176", "a00260.html#a4c9794092a2dedbf986ea8dbc0e6c6bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3177", "a00260.html#a7d2b6e5a0696a5ed945350e751e38604", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3178", "a00260.html#a52592d4b42c749cabfa4a5566c463690", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3179", "a00260.html#a3e93553adcdcff5fe059b161ce165605", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3180", "a00260.html#a64b8b4be17536d6689a1eeb492027f24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3181", "a00260.html#a621fc6ef14b4201509643078f05aaea0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3182", "a00260.html#a6b4675b62ad2ed75218897ae59d20476", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3183", "a00260.html#a70afad7dd29f9b90136dc483a945c3a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3184", "a00260.html#a849f0a30cb59734effbf3a72acc1ed83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3185", "a00260.html#a9a12ffa6e807a140654ec272d63b2c5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3186", "a00260.html#a2465e185d2b28d3f788fecbb32027a8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3187", "a00260.html#a0af464c82759997a80d74234f1836d36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3188", "a00260.html#ab89c5d14ed79cf5092589e319253987a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3189", "a00260.html#a8939214c121c59df1d387b7086f70c03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3190", "a00260.html#abfbba491bdeee07f85d87bbe78c7e6eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3191", "a00260.html#a5a3ddc2c171b8c2f2e07c3e8ff082167", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3192", "a00260.html#add6c3a7cec63897599de877590da64cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3193", "a00260.html#a4df698ed1e0a89cb730fe33ce2636465", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3194", "a00260.html#aff02950e5d5a100d1e437e0b759eac61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3195", "a00260.html#ad6301e2bd5c9d348a4c4b6c0ae1302f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3196", "a00260.html#a3e6c242d37eaa4cfc3bc931703e2338b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3197", "a00260.html#a086b032349cfc9d4f87ae4965f9f4ac9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3198", "a00260.html#a01aaaac55f5b5bfcdead7821683520c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3199", "a00260.html#afde34ea118b0827cfe58221ae9206ca6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3200", "a00260.html#a99c61b8760e64ce845a23b353f92dfe9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3201", "a00260.html#aa4b4441b3b787d0ba34b300640ed570e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3202", "a00260.html#a7f8d935765d2c70a7aff38ea406ad1e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3203", "a00260.html#ac23c76d08a806049064c2a479e3d37c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3204", "a00260.html#a49d1a370974375f104f0311b3e8a07a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3205", "a00260.html#a58f09b32fd10b080fefde8bed49ff9f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3206", "a00260.html#a40f619080f1cfe6c3cfdcaea6d2c1ec6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3207", "a00260.html#adeaf55c414c2a651d20e47087cbc053f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3208", "a00260.html#aff20c3b8e4394db4ecb84ec2915a08bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3209", "a00260.html#a5191835a73d496b6d5e94ef7f61282be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3210", "a00260.html#a6661a8f85cce8bb17029e55733229636", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3211", "a00260.html#a9a3104e741736798820a3bf51e74507f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3212", "a00260.html#a8a08870659adb091efec38cb5e8908e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3213", "a00260.html#a619b4daae519fcd81a6047a689a1f15d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3214", "a00260.html#a1db264038bf885492204c302c4bc4ff6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3215", "a00260.html#a08f0d3752266cdb780f732ad4dfb0d12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3216", "a00260.html#af5ea1b59babf0b26da548336da8b1657", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3217", "a00260.html#a0c2dd9e57b686bc8ec06ff25f6f2940c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3218", "a00260.html#a7f46e4c985b16d274b614ec5b7c732e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3219", "a00260.html#a84c3333743ce9b8678006d3fc40da348", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3220", "a00260.html#aa00b9ea302d6f5e93be9e17975580ad6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3221", "a00260.html#a715b39bed144d94b966d53aa39bcdcdf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3222", "a00260.html#a729829007ce70ffcb51abc9d1eb5a94f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3223", "a00260.html#a4f9c284beb79d3bf1bd3750bd072596b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3224", "a00260.html#a318726235a0506e84b349b737714f43f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3225", "a00260.html#af2076294087b8142d4b7a08a3dd5fe8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3226", "a00260.html#a039b95b85e461b13ad6615698b4b6a97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3227", "a00260.html#a0e9782cc74e152c997a96146d12e1a92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3228", "a00260.html#afa31088eba952055c8240ff8c691e552", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3229", "a00260.html#a1931dea673278bb422504e6f720f8ad2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3230", "a00260.html#ae014b4c7f16f33a129c24b63de206a0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3231", "a00260.html#af5bdf5b1b7fcc07e2dee714ef2fca157", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3232", "a00260.html#a72f91fa06699a11ddf55a8290bcc63a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3233", "a00260.html#a3a56acb3f5c62d806fd81d250aab89bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3234", "a00260.html#a7658ce9f826fc764244d33e463e951f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3235", "a00260.html#a4903f3b841742f403ac7c90cf2772be4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3236", "a00260.html#a219494c321fa0e6f7bbd6d366c00167a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3237", "a00260.html#a039f4b604d49da738b900d2e6525cc21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3238", "a00260.html#aec15265cd9905ce07bbb867779070081", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3239", "a00260.html#a87e94daaf10e9b1ed9d2b0a19f47a837", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3240", "a00260.html#aa65c3c5654dd5dad90f72f64cafe9576", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3241", "a00260.html#ad0980dcc682ba46350166c87a92b0062", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3242", "a00260.html#a4ca5729981963b207c41bc562a50374d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3243", "a00260.html#a77eb7054be3315fb704f0441cf304996", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3244", "a00260.html#a50d141bf86138c01e7abaf02439d5de6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3245", "a00260.html#a542cee6e7db19c21d921a3834118fc86", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3246", "a00260.html#a8c7c620f318d07bb23cef1bea60f79e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3247", "a00260.html#a55bed3806d3a3a1e09c22145255b8950", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3248", "a00260.html#a138891804f1a3ad68b0de3f72e901776", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3249", "a00260.html#a589561067e06a37d2cfb8a67dacfd50d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3250", "a00260.html#a3d20da9bc3e854ed98b2e5406c80b37c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3251", "a00260.html#aa9347f3d6bf04667f2cc731275a46d58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3252", "a00260.html#a7c60f0dce81c60730c7368f7d783c4ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3253", "a00260.html#a1df0f5ea7f97c15b605916d39b0716d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3254", "a00260.html#aa7452c78f8b6c660440e4220527a9bbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3255", "a00260.html#a87e041953d18b7dd849c77b2f5209cd2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3256", "a00260.html#ae398451a0ef460893b1f9502b8ac4277", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3257", "a00260.html#a4fc1ca9ca720c133bd4d6d6734f2f163", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3258", "a00260.html#a80cf357a100a3b240cb14c5172501fb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3259", "a00260.html#ab9ea04260d0f948a3d496d0b219534c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3260", "a00260.html#af72feae0408349c8a74580ece78dc131", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3261", "a00260.html#a6ec72558dfd114b41f36ee6a5073f0ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3262", "a00260.html#ae58df89a39a620da127a8b7791fe3201", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3263", "a00260.html#a8a5efe4024abc4e252a22e5500b31b15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3264", "a00260.html#a9369f6deb1992bff09e9d1b354c97d83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3265", "a00260.html#a96a00f792ca534196ac20cbdc01d6d31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3266", "a00260.html#a62ca860c9dad84db397fd781ca2148f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3267", "a00260.html#ab46b16f96995f5409dbac22b098f39d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3268", "a00260.html#aa5477fce2949ec75b33258906c0ae022", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3269", "a00260.html#a5ce1baf48b106c6ad0951dc32e6aea29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3270", "a00260.html#afbfa086c62be6bb91f47d5b5813bc4c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3271", "a00260.html#a5caaf12489b09001b998b45b732383df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3272", "a00260.html#af52c0084105e3d24848c26e18f1bfe46", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3273", "a00260.html#ad3c47d2285a0c195547471247b2cbe67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3274", "a00260.html#a32df756efd558ce65bc4c7ebc22573fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3275", "a00260.html#a86d07eea75e490222610d3b8b2ace531", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3276", "a00260.html#a55b44876ae5bef79c57b4d9bb07111c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3277", "a00260.html#aa5e007fd3b9937843dcbe5d5052b9906", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3278", "a00260.html#a7a82d10e583568da50a7affee75ec507", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3279", "a00260.html#a8f9d13dee86bdb629539ef8891d087ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3280", "a00260.html#a89b2caa3fc88d219dd128f13fef94cb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3281", "a00260.html#adf8dfbd6c579c007c40545ab3c76fe6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3282", "a00260.html#a5d541de5dfd02b79319c5235d218972f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3283", "a00260.html#a3c56c16e020dfa5f548a714cee955545", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3284", "a00260.html#ad6386a3b6457c07a1e98afb84b7f1d53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3285", "a00260.html#abe2d38d42788962ad41decf202f57bed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3286", "a00260.html#a75fccf6412f013e22123358979673b01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3287", "a00260.html#ae94c9f558e5fb0a738ea5fd185a1d6f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3288", "a00260.html#a52733c8fc05274b64f54b4273a68611b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3289", "a00260.html#a3d5d66dbd76963e670cae50f79b329c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3290", "a00260.html#a2c924203e352090a4a78055a1b507985", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3291", "a00260.html#a1aba87d6d9777196f88d6283ace8116a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3292", "a00260.html#a9ae8b378a34a1e676b804e0895456844", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3293", "a00260.html#ab4f80e5bf4aed2de19bbf1d1893f81b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3294", "a00260.html#a1415df3df8036e6f9ea24217918622f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3295", "a00260.html#a6e52be005088e581b1427ed720ecb919", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3296", "a00260.html#a0688fead2a7ae6f7e212ae17c9537461", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3297", "a00260.html#a0a0fa6152a8619d88056ed9516390607", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3298", "a00260.html#a1381c0c3657936c22ae68f374df3d2e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3299", "a00260.html#a9d4becc7e9dc3bba75d87ca3c544a9a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3300", "a00260.html#a550f948fec640b0ddbb5b07b8bb7bffc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3301", "a00260.html#aac360ce179e868cae924036cf0c5d5b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3302", "a00260.html#ae3f392bdf17dd7ca4e565e52d23e8b93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3303", "a00260.html#a82b4781bbdab7b5d33a79c029c738952", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3304", "a00260.html#aec35b3851cb749190dcf2f0973738601", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3305", "a00260.html#a0a91d20fe06a8f0b9d55c351179abc8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3306", "a00260.html#a063dbe6768b484c21803064ecca35bbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3307", "a00260.html#a5e5a16a3e27e3ab8a9811ad063c0155c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3308", "a00260.html#a3997ff69832bd8dfb6968c85ed37888d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3309", "a00260.html#afdec1376f897b662b739f631f48a8d14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3310", "a00260.html#aa5f828724547eafd69bf3dabdf65e7b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3311", "a00260.html#a27fadea725fb542e9bad734a151f252a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3312", "a00260.html#ad647c3f3aaff0424ff82dcd9c7feb0d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3313", "a00260.html#a416ee0bbb227f62cb402b6684fd94795", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3314", "a00260.html#ac61be14a3ad41ff09741051b21f7aa30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3315", "a00260.html#a6ace6f57c2d1bfed6c6d30f88c4aec7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3316", "a00260.html#aad5b6d1c315c02c18aba1ce9bc32b4c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3317", "a00260.html#a988f9b094c4c67f096d52dee2b7b4217", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3318", "a00260.html#a5e8ff7dde97dc46a8fb3cb2623e4e9db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3319", "a00260.html#a573c9c731a49bf2d141c5e3e7683b80e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3320", "a00260.html#a44addfdab3be9c18b72045b6a8fe3485", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3321", "a00260.html#a25275a7b5aaf6eb1342026c26dc879b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3322", "a00260.html#a21d12c04047a216fd424d35bce600744", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3323", "a00260.html#a9e3f434cf23164d2f2af22ed496269c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3324", "a00260.html#ac4e006402532a471857cf657e66e2238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3325", "a00260.html#a29fe79486221a1819fd33aa6bda2b8f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3326", "a00260.html#adc22a0c06498f1163fa64ec00301902e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3327", "a00260.html#a344889f2fd0daf50a4d0456f1314f08c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3328", "a00260.html#a7a011e95f7abb761f4c4462781a286f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3329", "a00260.html#a8aa9e4400973d452cbccd3469a1dfaf9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3330", "a00260.html#ada9d86066402c85af22f76e90acb8f10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3331", "a00260.html#a7ed1f660bf37076942b8e7f52a800bf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3332", "a00260.html#a6efd67ef20206df5802972b24ee6638f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3333", "a00260.html#abf83047144dc9ce50a4554ba7ade347c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3334", "a00260.html#a9790c936b9960497f4ea122428a223f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3335", "a00260.html#a9eea5696e7b92c99c5a06688d42ceb4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3336", "a00260.html#ae9cb2759408f8b21139e02e8101c5303", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3337", "a00260.html#a1397b36248ca0347f57a8af2117df6cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3338", "a00260.html#a1c878170de8093474d58ab82860818be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3339", "a00260.html#ad755a638ffb79fd0b98ad80c9f400a23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3340", "a00260.html#a4df9078bf1a2c77a86b792cc59311194", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3341", "a00260.html#a801a9c8a9a9eae85b6c3be67f2cef008", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3342", "a00260.html#a66b0149ac308dc0e3acba2fee165c1e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3343", "a00260.html#a6cc3e719abbeefb1303a870fd6865b25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3344", "a00260.html#ad4fe939995324cf3f4aad738d7a86901", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3345", "a00260.html#a58701bb6d9ace74b481cb7608e97eabd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3346", "a00260.html#a88a295ece88dcf9c0dd6648ccc3b1f00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3347", "a00260.html#a6e5aa586cf01b007e81146e8f9e88d9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3348", "a00260.html#aeeb31e3ae914e14d3df9bb5e6a94125b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3349", "a00260.html#a3482898acf90264c69777e23c58b3ec9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3350", "a00260.html#a67c2cdc3c203b3af1939a015d1bb416b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3351", "a00260.html#a62cd4d1a9b1f583a727befa45eb26fbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3352", "a00260.html#ae9ad0cf8a3976759b32378a440c87846", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3353", "a00260.html#aef82f4ac8fb5f5f14366141b6dab802c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3354", "a00260.html#a5536e5a59d5174ab9ebb0a60e0897b49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3355", "a00260.html#a9fc17748d015d29eaf11a52febefadb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3356", "a00260.html#afc28bbb1018d0c4a98a4566fd3e6c2c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3357", "a00260.html#ae80cf37456fddc3853242cf668b1daa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3358", "a00260.html#ace822de858afb45b0b239b231ba19848", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3359", "a00260.html#a2ab562311ace48c18c595c591befd45f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3360", "a00260.html#a308358521324cc12983c18cfd9694cad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3361", "a00260.html#acda2ab3535a4234c14904294faac4315", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3362", "a00260.html#a726350254e5dbfc2b093314d593b631b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3363", "a00260.html#a76b7845007ef8b5366d8f6682b68dd34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3364", "a00260.html#a1c254f04da02404f8147034a490660ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3365", "a00260.html#aa147d8402412b4fbab503167b44c22f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3366", "a00260.html#a2d3950031c1804d55c5d8092cf530886", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3367", "a00260.html#a198ab643856878e585833272988caa97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3368", "a00260.html#ad905675fde6defe236b1d04411d700da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3369", "a00260.html#aadfc1890b2b377e0668736dfc63572b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3370", "a00260.html#ac08d8cc404a926bbf3fb88df3271f5fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3371", "a00260.html#af14836b4d4df5714cc4bb2d720ac00bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3372", "a00260.html#a96f364475b1a18399b7b3e561a61c0ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3373", "a00260.html#af981c345c0ef88fcf1c31403889b8d4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3374", "a00260.html#ad78e62f8af5ef95530e61b0896bf66d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3375", "a00260.html#a67f96465cb42f955200275689a8d4630", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3376", "a00260.html#a95adae74d35bb7afeb74338b2f6681a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3377", "a00260.html#a6dbd7fe5f2bae0492fe2e97f1db3495d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3378", "a00260.html#a27e2aa130b75c53538391227aced40eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3379", "a00260.html#a5d73cb2a2c07569cb56514979ee5abd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3380", "a00260.html#a6e458b855126c27577049f77b90a192c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3381", "a00260.html#aad08f122b4032224f9a3acbec389717b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3382", "a00260.html#ab9153c366ecb5920c7b4c5ba34129795", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3383", "a00260.html#abf5e004eacb6ab72fd5de86bdb1a5d80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3384", "a00260.html#a24d71e05f33ee8723ca039c89196ea3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3385", "a00260.html#ae2a968dd23a9b2ea7fdc6b4b111188ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3386", "a00260.html#ad6ec192ec32c64f2f5fb062f5bffb05f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3387", "a00260.html#adb5c87d1c0b5f610dfc148723b79b3d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3388", "a00260.html#a946e61682c1c0424f077f706f3aeb6a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3389", "a00260.html#a0246ee8a06d0e860447ab28d4b94c43c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3390", "a00260.html#a4776339b84133cf9ac223bb8a9d1af79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3391", "a00260.html#a76be34c91867bffeb9f4637aa93f64f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3392", "a00260.html#ae854638e44df57ba35ba53a25a01f298", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3393", "a00260.html#a08b7198f86b6b4a7dd065350cdd7598a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3394", "a00260.html#a8d644c8201eed2ab882d6fc3a42b96f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3395", "a00260.html#aade0559241489759821fd161f2a8cf0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3396", "a00260.html#ab5d09380f1622edaaf51b6ad7cef4e69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3397", "a00260.html#aaa1e5d9ce1eb50cd755806bc43f65d89", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3398", "a00260.html#a66a7df25888e3d5878d43c1143b53434", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3399", "a00260.html#a376c2445b32352f41e9a51a96f13c834", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3400", "a00260.html#ac17469fe304b12ef82055887f98ae52e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3401", "a00260.html#a28cb287c2ef85efe7d6ebb4af59c6f24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3402", "a00260.html#abf9c89c5b9ba38a5e4c5dd3264544541", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3403", "a00260.html#a0ac87a8d6bb31517ae63e1f085084eb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3404", "a00260.html#a2d8181e5041507adafba644804676eb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3405", "a00260.html#ad47d54a69f8666fa4585c83504162671", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3406", "a00260.html#a38f56b000615b6c7c8be5159ee94877b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3407", "a00260.html#ac3df9a3dac26431837dae147ce30e515", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3408", "a00260.html#a329b9ac6159ff8fbfc9aa299be98f9e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3409", "a00260.html#aa1953f493e8ea605c8a4fe8a24508e1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3410", "a00260.html#a30b1c233614fb7f49f59625bf9e8de04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3411", "a00260.html#abcd55890ef442b2d4cb1d91a62fcbb3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3412", "a00260.html#a610b2888ab4bc1a6710063b0c2076287", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3413", "a00260.html#a6566fcd4078d395768f1b98718cbc71f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3414", "a00260.html#a2788d4a30d611efac96ef01bd5759265", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3415", "a00260.html#a7d52f528e8715c47977e575be416d804", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3416", "a00260.html#a9f384893b854eaaedb5dd70b0a1d84ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3417", "a00260.html#a025725925d237746889b76ae1dd357dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3418", "a00260.html#a8130f8070b183798e84a47c263574d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3419", "a00260.html#ac7c9f66515affa21493d653ff3831fcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3420", "a00260.html#aae664bb6c3c2b608283938f310c748dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3421", "a00260.html#a443b47a35d779f34ab74b8fedc632d6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3422", "a00260.html#ab5342079f892b609c66882a9400e44e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3423", "a00260.html#a8e80d8cb732a5b91ce29e226bd35c422", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3424", "a00260.html#a107b05294c7ead1ffa5c05cbb782d955", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3425", "a00260.html#a7ed51490a39812a8e6dfffc28d82822c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3426", "a00260.html#a56090e4a52d04fdc2e9bf16cf9f3b7d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3427", "a00260.html#a3675ad74b06ce188a61b24e3050a241c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3428", "a00260.html#aab76efdc361065a38af10b298292bf23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3429", "a00260.html#ac534191229a11132b0b14d3cb431dd39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3430", "a00260.html#a408327f094bb04977bb2b7abb36c2546", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3431", "a00260.html#ad00760ee39b65c109673d3c8dfedd905", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3432", "a00260.html#a3627aa2bae2e776ed517d92577ae0d8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3433", "a00260.html#acb6a4aa37700edfb2e5cce44bf12e1e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3434", "a00260.html#a1b529f6728ddb1e624767b1ecc063f66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3435", "a00260.html#a57a86f0019f8a907a498d96d2da9c2e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3436", "a00260.html#a6378692ab03711e06233fb893216ca4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3437", "a00260.html#a9012cb48b7bbef8542535a2738a06f2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3438", "a00260.html#a33761c154a272ee49423fe358d63a0ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3439", "a00260.html#ae34092f1a3a46bb77a2f760de769ed82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3440", "a00260.html#aee034f2f7511d37c9768ecd5082145bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3441", "a00260.html#ac30cec0fd8f4981337a00222bf1a5f0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3442", "a00260.html#ad7bec3b9e0ecb247781f7e084e208bc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3443", "a00260.html#aa5a023ba2784076838b1499fac4c7e66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3444", "a00260.html#a9cd618d9d62e431b5d444f2dab6c63d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3445", "a00260.html#a1bfff6f0304a1fbd58c07235ccb86ed2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3446", "a00260.html#a8a976b6aea86f9783f97d298bd60843a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3447", "a00260.html#a6376c8d5037e0f4c726e9abf02527f22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3448", "a00260.html#a114bb0712b560d1003595e3eb0310546", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3449", "a00260.html#ab4a792fc0ead722d98f7389a62e907c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3450", "a00260.html#a8e4908603d4464979d20b337e3a3c467", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3451", "a00260.html#a5692808ea075b6f1252c7c092c54ced3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3452", "a00260.html#a43c472e92d8bcf7ce801ed27b14d9703", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3453", "a00260.html#a5c5d25a7734c55a22d0c348d0e1a97b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3454", "a00260.html#a6969ec779badb63c9063eafb49a90599", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3455", "a00260.html#a2301327d4eea9ea570d0d8f72c9b1ed1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3456", "a00260.html#a2b4cca318069ecfd1065d5668630892a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3457", "a00260.html#ab84f030ef6595db43dbaa3f30b1e477f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3458", "a00260.html#a1bacd385a945ac974b1457c601cc4faa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3459", "a00260.html#ac3631d68a5917cc2c654316bcb7d7352", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3460", "a00260.html#a759b4e6b8b44f282211bebb4ddabcdf8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3461", "a00260.html#a8851e9749a8167196c0525b87ffe566b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3462", "a00260.html#a20fec514213fd4afe55f2283d9998072", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3463", "a00260.html#acf06baddb8c8e535f743423e6a2aa913", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3464", "a00260.html#abe6a2264343a160b21690a3f2afecaa0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3465", "a00260.html#a870db5d47e768053ba47daf2a500534c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3466", "a00260.html#a296db28d55333576763d34549a512bcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3467", "a00260.html#af2cdfefd14c2723cd0118b1892c2657d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3468", "a00260.html#a74c0b6eaba02352b46c70c257dc19112", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3469", "a00260.html#add7aaf37bdca78700c7e34bb0bcca7ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3470", "a00260.html#a5578b59c551b9f46ce22750cf49ff2e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3471", "a00260.html#aed5b3c943654533405f78b00694864ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3472", "a00260.html#abb0eb4ef0c1a3731ca09a32fc325e853", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3473", "a00260.html#a364f1a19fe8daaf2ff2334ad62d3b7c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3474", "a00260.html#ad5566edca965be5b0cbec9a78db46515", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3475", "a00260.html#a0bcc427842533732b5a82f1c9115a0ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3476", "a00260.html#a303e2f40cf221becbcadc97e7d5c3fbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3477", "a00260.html#a1eb7ddc1e73b3fa798f1f3d7a75a5960", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3478", "a00260.html#a2eb469a2e871e892f35b5701dc8d8a8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3479", "a00260.html#a59b56bc4b63399914e29cdc4bd7313aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3480", "a00260.html#a6a8ec643309857178062d5b104bd739b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3481", "a00260.html#a7cfd6ffb25637cf63c188d853c76c874", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3482", "a00260.html#acde4c2037f3181112de3e019e60d46d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3483", "a00260.html#aa6500ac6ae975bb24adf5a2c2c24c171", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3484", "a00260.html#a7fa4a9ec4f66cec806f4a7a9e4c64298", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3485", "a00260.html#a38850bdcc6882c7c27821c257c424fe2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3486", "a00260.html#a9ebf3c93de68cbb9bb2ea8b882f38b37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3487", "a00260.html#a2a01c782a122611490cb507453e1ee9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3488", "a00260.html#a5c17a16dc256409f3600bade6bcce324", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3489", "a00260.html#a13ba38b37c094e2746a0e76cd043e84e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3490", "a00260.html#abecd54acee07dececf852c59142c1454", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3491", "a00260.html#a2cb486e29f0edb0c2532f26bab234123", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3492", "a00260.html#a33e26e6bc2e5e6cb99b7f76d25def739", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3493", "a00260.html#a6e26e1638a69b071edbb1447b0b4a8fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3494", "a00260.html#a7cc7b991e7c7b9b27f960c1f3e6a6cc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3495", "a00260.html#a00177c7a0040b95c0a543fb55d526a09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3496", "a00260.html#a14139811ca4f86e9ad724aec68731136", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3497", "a00260.html#a6ebe1b0562f00629697cb18ac5c4f93c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3498", "a00260.html#a31deae2f83d57698fa8997efa2a6b584", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3499", "a00260.html#a85c18501ceab180df5ab973ee2cb984c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3500", "a00260.html#a252a65d97297b35d66463b43016d4ff4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3501", "a00260.html#a6be7048a15b21d5cb2ac042a005851f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3502", "a00260.html#a0fbd6a466ea19440da94a4504b889de0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3503", "a00260.html#ab43df4fc57f45deb04093e8bfdd9b606", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3504", "a00260.html#a7971021a6442e19fa3fefaecf152a904", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3505", "a00260.html#afc67ad52b7d3043b8b9be09a1eb05d34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3506", "a00260.html#ae2db70c760ef252293ce5c5e653de3db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3507", "a00260.html#a5114cb9f9d24fc05b870b12a07ef52c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3508", "a00260.html#a46f3b9e761821ac26afd8079f1bb88d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3509", "a00260.html#a9b5ea7feb0498d0422509f24b9988d49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3510", "a00260.html#a75f411ae2f00b3092c4a249ddd7b60b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3511", "a00260.html#a531957f4cbc86e55610202b807561947", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3512", "a00260.html#a931de96d7132127141963893f875a7ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3513", "a00260.html#abab3430723f429b1998f42b2236e8a02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3514", "a00260.html#a5a6921b1b91373b77f7ef8eb4ec287a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3515", "a00260.html#ad3568d91bac441f8ebb05030a50fb9b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3516", "a00260.html#a04c82608e68ef4d23819bb46dcba13f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3517", "a00260.html#af647e583928d6992e90aade9e193f865", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3518", "a00260.html#a5baf88b17ab6f29a230a43ca57510659", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3519", "a00260.html#ad67283f76caa9a7bd071c8f207d115c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3520", "a00260.html#aeaf5090d1ae855a062ba0db7da44f7b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3521", "a00260.html#af6958348e2688d5a3d697ae08ab6760f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3522", "a00260.html#ad1060b4504482b8ff309627f21d52be3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3523", "a00260.html#afcb11018e72d1cfb50e99fe8cd055a55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3524", "a00260.html#ac4dbeff0d397ffea2f54f304fa3e0d65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3525", "a00260.html#a0f2621f3c2245c3c4f1292b12bf77614", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3526", "a00260.html#a841cc56b9c461620f9fd55917f980a5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3527", "a00260.html#a93df01cf7cb384fd18ef13792134fe73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3528", "a00260.html#a3f7d63c046cbac17fa57bf96ecaa1dcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3529", "a00260.html#ae6921c868c978e725f1fea7839d13dcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3530", "a00260.html#a6953e5d29242e8caa0cd60ddb67be19a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3531", "a00260.html#a91ad8a56c174b357ab911ed3a79688f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3532", "a00260.html#addc382e575966a757a8840d288644222", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3533", "a00260.html#ab16311796b57d0abf76329a56f77584a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3534", "a00260.html#a02d5c89ff8b6a8cedb2f64b962d4499e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3535", "a00260.html#a4356f416287bd62e1a7ddc5e06cb1765", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3536", "a00260.html#acb8220ebe3d58d1f5fd789652550cc93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3537", "a00260.html#a5e466f673bdd1dea6fd9a4dfacb12acd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3538", "a00260.html#a59cfc8736ad0c796f5d2f5a91bb97cda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3539", "a00260.html#a0c69e9d83b7ed56d793e1ca09f1d7e02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3540", "a00260.html#a825069942d15cdc08887aeb899bf7b98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3541", "a00260.html#a473eca54efc8785de41a52c21a7ee213", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3542", "a00260.html#a5c9ae7e96c917d9d393f074becc15b31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3543", "a00260.html#a5cc10457045720b0529ffcf53fb48bd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3544", "a00260.html#ae381aa88323dac03dc1b9dde6b09001b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3545", "a00260.html#a7bfbec07b2fda67b9f8cf4cb0894d39b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3546", "a00260.html#aca3530f519792d94fc952a8f4f1b27ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3547", "a00260.html#a2f65c76a52bfc9993c6f69771c05eb56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3548", "a00260.html#a16898c8307d78b3c2957e8ec8cd11217", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3549", "a00260.html#a9e770f3b3080bf53f2391d90f111ca4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3550", "a00260.html#adc5affa1713d906119ebd402e72fb7bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3551", "a00260.html#a9d9bcbffb4c1dd22bddcd2c6dae1041a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3552", "a00260.html#a93ca79c07c2c98ace6f1a0f3e02f8e58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3553", "a00260.html#a0d5be563934f9813403bf3ac136954b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3554", "a00260.html#ae19b90d4d1cc27f67709f31f08211550", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3555", "a00260.html#aa657cf6a50a47511201702ddcdaece28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3556", "a00260.html#ac7c5c8c97273d4e00ae1282f643fa2b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3557", "a00260.html#a0a1e9b6c9c751c4176c835951f7b2972", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3558", "a00260.html#a4b4ae0b71a0e5cb37d3aece724b11012", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3559", "a00260.html#ae2e4c6def61939eb4ea3312a8e7b0d9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3560", "a00260.html#a53b439a8f74db457871617c339f82ef8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3561", "a00260.html#a68d91460c1805c095be4ace58084808e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3562", "a00260.html#ac574e6a868d61942320b93895349d502", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3563", "a00260.html#a3ee696d93f9dfe5f8835fbd5ef880a56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3564", "a00260.html#ae6766dc24382ea052496966ff25de25f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3565", "a00260.html#a51fc6310c02e0b2b3a3836bd648a1aae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3566", "a00260.html#ad71298343669c6806cf0ab43dd7fd3ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3567", "a00260.html#a78feeaffe0bb997bc88b5f051064d655", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3568", "a00260.html#aa808430a32af5f97efbb53864973fbf9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3569", "a00260.html#a98a45c231d7019df41e9c2c096d0c5cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3570", "a00260.html#a8cd5a0736a4a321e6d193b4d29b17b81", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3571", "a00260.html#aaad1c793701299c7fe7a9f42c5d10158", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3572", "a00260.html#a0e0d2467107e9f9cd0c68fb2999335e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3573", "a00260.html#a8c5663c60b45678a0610938ba62d7faa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3574", "a00260.html#ac063165a7e2445785a2941e95c268004", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3575", "a00260.html#a44c836335a4b7fb9f9e448658e333994", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3576", "a00260.html#aa64dd80967fe4ab2216b64c36260d62e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3577", "a00260.html#abb82e864948665031f64bfc79de67e3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3578", "a00260.html#a1104c5b62b6997007f1ef61a7a3441b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3579", "a00260.html#a524e8a808df10960baab85bed5e1c823", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3580", "a00260.html#a2548536c170a723a45bc22a2515249ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3581", "a00260.html#a05eb7f7d5c14bebb720d9a7c5fb177af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3582", "a00260.html#a114c805a84b6707201ce9fa9732c7eec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3583", "a00260.html#afacc4aa9cd404e90c151e01a12912a68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3584", "a00260.html#a68a967909fe9f325d68f78c948944cab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3585", "a00260.html#ab3d1912c2999f5e0522b671b12a82807", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3586", "a00260.html#a0ec7ebbc006059fea2e7e7659600d2e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3587", "a00260.html#a9ab05df85b6ecd8d153f7246fb456225", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3588", "a00260.html#a75a252e9813651beeed391d14d753e70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3589", "a00260.html#a6466d71aeb5a049c3d2bda96e7a1dc7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3590", "a00260.html#a55a1f71cbd65c39780b555183a6f2f6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3591", "a00260.html#ae534e1260c799f4b2a5358bccf03dd10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3592", "a00260.html#a1e5fc6cec1d2233628f1e0eb7bc42391", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3593", "a00260.html#ac5ea194c17ec8d70c34055caa37dbe63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3594", "a00260.html#a6a2c2c22f643651262be51240748c069", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3595", "a00260.html#abb93c221853dfd8445083452c22d0e55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3596", "a00260.html#a553750859d3bab02aa979ad875e8cf9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3597", "a00260.html#a70a6cf4ec143310e8ce4913f69818d20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3598", "a00260.html#ae16b208516c9ede0eaec2039becb0f7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3599", "a00260.html#a642886d13c6980ed79effa3945956803", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3600", "a00260.html#a966c6b69b4218fa492d5a508499ddf9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3601", "a00260.html#ad0dec57db697a81f01283f590b409857", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3602", "a00260.html#a961b87a180a47977c10348b9248f2464", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3603", "a00260.html#ad5bec37abfe5d8701ba2f01fef7386da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3604", "a00260.html#a7b286e22e579d72532ef6695730e6338", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3605", "a00260.html#a2af0c0e15672b3cfaa05b62a825ec7b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3606", "a00260.html#a324bed8c5d93975b258e97b58e5b887f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3607", "a00260.html#a88374da7eca888bda09380390f8b58bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3608", "a00260.html#a1c0a9e766bab8efcd087426a46bc676b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3609", "a00260.html#a1623aa8e2c4b8056e72a1e3d6d67b363", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3610", "a00260.html#a9081e8546bae3b7e5023625a1da295c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3611", "a00260.html#a130a132e74a1271abcdd2824fec4a116", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3612", "a00260.html#a69ad9f1f675718a8a66eaa52342c72f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3613", "a00260.html#a36e02490b4d1ef4e846fb687ea229eaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3614", "a00260.html#a798c95ed2a0f7156e5ab2b7f579a65d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3615", "a00260.html#abe79e1c7bebc3f6e18222f3f8003c883", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3616", "a00260.html#a66fa755091c2d709629c958b3f1965b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3617", "a00260.html#a59d8b44d94f61ff3ad77df4dad5721f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3618", "a00260.html#a82982a6ce7952be953995223e60e746f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3619", "a00260.html#a07243716f286e722fa4f99e3654596f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3620", "a00260.html#a4bfa5060fdf6c5b0f8f6a46a5e0faef4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3621", "a00260.html#aa0ce591bb21a7fe2457cfaa41bc6df72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3622", "a00260.html#ab839626714bd254c72e73b2179fc069a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3623", "a00260.html#af3082b1a64126fcf5f92d94a6a36920c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3624", "a00260.html#a7e9ed63c7109ce4bae9990042ab57d4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3625", "a00260.html#a50a1366c726de7e25e7779c76f652c40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3626", "a00260.html#a025ecf5f13eaaa417b7191f7ad08fc9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3627", "a00260.html#a7a9dda8bba111b13a55504467b6b0370", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3628", "a00260.html#a2239b44ab098650f105594640590acc6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3629", "a00260.html#a895610496722e2d12e0f138e18a631c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3630", "a00260.html#a513f6d92d4f5742bd951e7040903e520", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3631", "a00260.html#aa4390d0c0508403b7ef44cc2e659fcf6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3632", "a00260.html#af70479b655dee7fd58d4c81839e17897", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3633", "a00260.html#abc10ff445d11cc1682f3f7597eb39d36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3634", "a00260.html#a039cefca76f89aab777a424d6a8f32bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3635", "a00260.html#abadec87ddd3b4df09cf77e3332249f6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3636", "a00260.html#a7dc5e916643a6f23c20340132f712634", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3637", "a00260.html#a831474a03c5dbc9c4cdea8bbc8439342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3638", "a00260.html#a3249839ebb4615b021983c09cc88e69f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3639", "a00260.html#ad1590a1afce062cb8f7720e18b24e755", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3640", "a00260.html#a3cbc48d437ba8438858ccd0feb5e99df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3641", "a00260.html#ac88a9aba55ca9e5df4e347c003acda7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3642", "a00260.html#a668eba3a5072b0476262e9b65e8f1ba4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3643", "a00260.html#afa31a1c4a5b30f58a09a2ef16b311951", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3644", "a00260.html#a66ce7c15cb05cc6dd0e278e671ce3ea3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3645", "a00260.html#a78407d028c525e32170977c564eebae2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3646", "a00260.html#aa36d86ce525d1a632595ab68a928954c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3647", "a00260.html#a56088a4b6afa8859d90b9a7c26d3379c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3648", "a00260.html#a665fd4619be147049f5d9f63dafb578b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3649", "a00260.html#a200494ab36077b96f4e3751c47ae6660", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3650", "a00260.html#a43e97b1f02efab12e7c6e94598c17394", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3651", "a00260.html#a59f6cc6ee2c243a8bf094ad98ebddfc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3652", "a00260.html#a0bfc08254b585657e1eb6d2e2a75505c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3653", "a00260.html#a6c5b9de69ab81d7d55b74b774b0a52cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3654", "a00260.html#a36ab3b789a8bddccf11b0459c702fc73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3655", "a00260.html#ac5bf5abf4348d921d3ed43fc886de79f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3656", "a00260.html#a92aa7f6aed32ba8b64cdf57702a5fae3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3657", "a00260.html#aa686470408ebc039204b0893a3888014", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3658", "a00260.html#a732f96d712ef92c3e81d47cd5850b206", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3659", "a00260.html#aa90fbdda745d21e120c8ae8e5cb7d5ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3660", "a00260.html#a0bf06c67eebe24955b0b70aacc34ae0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3661", "a00260.html#a21af6a1f3b159fa37d207827507b1527", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3662", "a00260.html#adada84b69957be6becbd6b6fd8e43628", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3663", "a00260.html#a4221db1f11d9c81bf37a27b6dffba1bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3664", "a00260.html#af1cc31d0519864d5ed086f96b024bbbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3665", "a00260.html#a51604cab27a02ba2c4183d1472a7276e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3666", "a00260.html#a77877955784a63df71c57c158d4089f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3667", "a00260.html#a9818ae7bc8af2c3d46d4fe9164aedc0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3668", "a00260.html#afde2c6d344bd0c7523e2de212a78016d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3669", "a00260.html#a0a88ccc466fd81f3a209367354683af8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3670", "a00260.html#a319cfc54118055d6076359ba62873223", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3671", "a00260.html#a81bb9c312c4c3bcc6f7bd259e60b49c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3672", "a00260.html#a723bca9ea15c44ce9c193d99f093ee9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3673", "a00260.html#a5965bce3c1852e9c780f2f54b04e99b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3674", "a00260.html#aba02051ecec0cfb0455adcfc3be9d257", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3675", "a00260.html#ad1ed177665b31f25e342285bed972266", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3676", "a00260.html#a598d78870b1df6d9f6061dda584ee580", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3677", "a00260.html#aa1a32e6be1f740fb5af91d7384c02cae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3678", "a00260.html#a00f0254fe4fda2f214dac128c5593b48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3679", "a00260.html#ac930a8f0f9287530e1bf3d76d2e05d2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3680", "a00260.html#a379c32325385dba38a7e53bd04115c33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3681", "a00260.html#a4be684a5d023d0ca3efda8164b224ccb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3682", "a00260.html#a1d92d6a0b42dd2c1bd1611042f240578", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3683", "a00260.html#abf304e243dad884c68b684d38977f123", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3684", "a00260.html#a8ebd8694c562d5d71894f6b5a3458ef0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3685", "a00260.html#a94345f6e6176da67f24849a72b7969b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3686", "a00260.html#a000c16e4d69d9fba52b233ae17086af2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3687", "a00260.html#a19fa1c1d308a5e01f579a6dbcb8083bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3688", "a00260.html#a560f0af5954237947318255aa9567e93", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3689", "a00260.html#a735d352d851152a38ab8618221635c2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3690", "a00260.html#a57a251f66f32c39238f8a9b2ca160c8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3691", "a00260.html#ae9d809fe1b83fa3af0cbee3974ce5b33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3692", "a00260.html#a223c237b3a7442ccfd4defd1500cb094", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3693", "a00260.html#afa3fe0c0bc1e41ea71b68cb2f3e44b5b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3694", "a00260.html#a8ac5391728ee2b820e56f9f801b07c4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3695", "a00260.html#a78dfac36b22baaf0c35ddda2a5b2f3a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3696", "a00260.html#a9b0da7a1bde919650113a6ccda88b316", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3697", "a00260.html#a99033f8c1730d14773727e007397c8a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3698", "a00260.html#a9062d6e27bf3dd1924a4099ea7aba108", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3699", "a00260.html#a545b9ca0532fc7d17961f2d085b13ba5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3700", "a00260.html#a5809d3d96e82ecabe8055d55ba3947ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3701", "a00260.html#adc1929ec8641fe83ed396d56738bf65b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3702", "a00260.html#a42b668965734334412703e1026624648", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3703", "a00260.html#a5a5531d1708994f2c1d1df55c3ae92fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3704", "a00260.html#a87f6f90f79bf6db10877d3143dd02480", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3705", "a00260.html#acad757cd8e56a0e89aaea31b1bc2c914", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3706", "a00260.html#a42c08f89513b2c993d8b53ee0307e824", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3707", "a00260.html#a378eba2f936b7996e2448526ff3f6e17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3708", "a00260.html#a0ee98c78421ac8c6b97c470bd34d7b9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3709", "a00260.html#ae1696de1e0673dde2669a9463865988b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3710", "a00260.html#a1c987bfc88da65f1cbe1bfa7c0e06005", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3711", "a00260.html#a5c1386e3aa3c05b1ad49df5ff065755a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3712", "a00260.html#a954556104f5453192140eba426883dcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3713", "a00260.html#aa45c88170389f51cf548eeae076f81c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3714", "a00260.html#a34dc7459ff5085606f5c859deb92d5ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3715", "a00260.html#a499e5b01fc4227fc8d9d2d07da16e36a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3716", "a00260.html#a9c9d669c1fa4d550ad7b735502856e2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3717", "a00260.html#a32b57dc36730e8659d81bd59dd307c0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3718", "a00260.html#ac4d8de6ddfd0a83dac14184376cd3374", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3719", "a00260.html#aa7c81242694d9ca1750238711981abc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3720", "a00260.html#a6ffd0b3825993fd43e6cd4d0014ff8e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3721", "a00260.html#a37a817d752685a930afafaad1bb613a0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3722", "a00260.html#a146e1657f9b7b93b07bd8cd71b7e1995", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3723", "a00260.html#a70f568c56ab48023ec4938cc3c528084", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3724", "a00260.html#ac9dfa15cb2c5c915662a19b02ceaeafc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3725", "a00260.html#a9b2bb9794880974d6896d57bdbedd78c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3726", "a00260.html#a3c5de8cf444acbbd076c2b1993764057", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3727", "a00260.html#ae958af605d226fc26a9173520f523110", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3728", "a00260.html#ade2629fec0e9ea5edbe7055833b2bd2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3729", "a00260.html#a75146d118e41f81d5c8916d6894678ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3730", "a00260.html#ae98d73b64a88e6a98e9295072fa90325", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3731", "a00260.html#a83274bdc0356e8cd76337163b758018e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3732", "a00260.html#a2cd1236e850c053e69d9ccd16919cb55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3733", "a00260.html#a492253829cf1df0248ea7bc93694ae66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3734", "a00260.html#a4c0225d6c725c5cd5f5912e7fa3b32d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3735", "a00260.html#a705cb134e0e845e929890a46c8807c3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3736", "a00260.html#a14164f8816fe281d392490f8952aab78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3737", "a00260.html#acaccb6efa39a661783195947d3ed19db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3738", "a00260.html#a3b77edbea3317291366c0c1beace51f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3739", "a00260.html#a51516210055b332823ec3bfe7594d09c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3740", "a00260.html#a01dbc7ab0922692c2902379feeb71253", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3741", "a00260.html#aae2d953feade3a2f9f38f4edae6a408d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3742", "a00260.html#a5aa34713f36b9d2ae6ee00ddafbb461c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3743", "a00260.html#a540a1365bcafda4748c673d843b15a6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3744", "a00260.html#a24d47ca3d7b1a4de0ae953b2663a9a42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3745", "a00260.html#a07ae173914d0f389e7dd0e380738f351", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3746", "a00260.html#ab84c45e2acc9816509c33b80302cdcd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3747", "a00260.html#a0cfdecc220ee85f7ce2ea6e5c18e5a32", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3748", "a00260.html#ac5f97951d4d31c3343d76e13b1800503", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3749", "a00260.html#abf3e8a68cceda6111d00e24557c84a6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3750", "a00260.html#ac85bf00f24d7437897eacee8183ac932", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3751", "a00260.html#a0137e36b97ffc2ebfa1db01f70961b77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3752", "a00260.html#ad3990c24d22001b88036fbed5d31a3f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3753", "a00260.html#ad8b9cd77f39f9e1ca23121ea43ce029d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3754", "a00260.html#a6e2c119050128f1dc7b675cdb02670ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3755", "a00260.html#a2abd05528951d4860f30fb65381b0ef2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3756", "a00260.html#a6c9d0129de954ddc36b8e2806582fcd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3757", "a00260.html#aa57c20e3f3cc0f36d795b66fb1986813", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3758", "a00260.html#a3bf110a4517410e6b97d616c3d3eb7be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3759", "a00260.html#abdff55f3b28e8893877c8d4c2e4d8f74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3760", "a00260.html#a8e02d103deeb9ec75c420e464599071d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3761", "a00260.html#a4404546d17a5585c997c47f88b7989ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3762", "a00260.html#a1cc794177df8aedd622b01e3c1c69a99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3763", "a00260.html#a79bc21cf9f8fab4b77a94a7dc25fa39f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3764", "a00260.html#a02165424d2f8def2ea84b9a12542ddb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3765", "a00260.html#a2fc001b812a13c6609dc2def68dee9bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3766", "a00260.html#a4fef1c416ddde0f1d0d52916372ecca0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3767", "a00260.html#ab4a7cb69ffcaf5f3b3998be0b33c6ed0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3768", "a00260.html#a8eafb24a497900d3744562f1e02b3a3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3769", "a00260.html#ad6fe048987dc1ac08ad88d0257445a9b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3770", "a00260.html#a070bb0cc6d11aaa6fd2fe1d9928cc3b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3771", "a00260.html#a50a9cf3f6da0cf6bc6a3a0f642b7d060", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3772", "a00260.html#a72c262ba7487de876eb2e7d625f4fd67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3773", "a00260.html#a2bd22e3a5b16f78f534d828abdcaa138", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3774", "a00260.html#a21747353bde77ff7f92ba90167a33df3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3775", "a00260.html#a006bca2ec5ca74a666731a1b82a3dbc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3776", "a00260.html#ae18ea4a8a9514ed501195d5c277bd237", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3777", "a00260.html#aaba1d91c6a432aa6bd084b9bcbfc9bdd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3778", "a00260.html#aa9cd7e5bffd231ac189122096578a13f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3779", "a00260.html#a856243405af9cd1cb289278690f3161c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3780", "a00260.html#af420aef0b30e976a16e7571b67ad40a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3781", "a00260.html#ab44e16c04e51b364dd4701a186b117be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3782", "a00260.html#af48493f7a8a82180319d36219ae3b104", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3783", "a00260.html#a12b40b48b9ad1fa68d75fbe3847cddf4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3784", "a00260.html#a500982c009e0ef5ae4c31ff2ccd46919", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3785", "a00260.html#a9c57d63bc1c91d6e1f40f4527f357150", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3786", "a00260.html#a9fdeee152dc510c5839d32c81d89e872", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3787", "a00260.html#a636fe39fc93ad66732bdad870d9c3ef5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3788", "a00260.html#a36ca5ab434c0a3be6a0aa1eb576bb233", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3789", "a00260.html#aca742c91f27b0d9c5e524b91abc57830", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3790", "a00260.html#ae378ddb92075eed4883b0fac4d56db8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3791", "a00260.html#a3cf7f8708444c5532cb8b79be572c882", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3792", "a00260.html#a3cd7c47c3fc8f2e979a8f800715732e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3793", "a00260.html#ae580a5131494bb3b28b0c220218ffa2d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3794", "a00260.html#a96e76f2a04ba53a71d001d52c0c0e143", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3795", "a00260.html#a3367e3833cb94b344c7e1f03088f46f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3796", "a00260.html#a02500c15e9f2ea20047c66ddd8c96674", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3797", "a00260.html#a2f57a079a12036af0d36392238f72b61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3798", "a00260.html#ae6c977d5e6155468e05e5e157f4337ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3799", "a00260.html#a9404b89c824d88a8959ca4f23c5159e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3800", "a00260.html#ac15def7dfeb2172fd71deb4ab9433741", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3801", "a00260.html#a8523b9187c528f4132e49a2402865e1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3802", "a00260.html#ab2daed55c5233b59990c81d4ee047253", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3803", "a00260.html#a2976324542c75103a0c1502717c63929", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3804", "a00260.html#a98efa443d325d63ceddf793f3001bcc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3805", "a00260.html#a16869b19d67c20823601b4addaf3043d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3806", "a00260.html#a2aa7a1be690eefb308353d08f2f6d4e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3807", "a00260.html#ad8858259eb1a3829f2cc634c3438bf4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3808", "a00260.html#a3c7104697b547ba846669323e27270f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3809", "a00260.html#ad1e7447c2ab967428154489ec6f843d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3810", "a00260.html#a343af03c7a81b9433fd29ecc6c445085", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3811", "a00260.html#a9adede9728f66854bf491273a2a8dcbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3812", "a00260.html#ac1b3ec63383c0fb071ffe30b125cbb85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3813", "a00260.html#aee422e0ea820a58c6c05d85f112aed19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3814", "a00260.html#a7d8ff853ee12854de2935d69f8f29b63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3815", "a00260.html#a0156599cde71fa094f52ba50a7e39d9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3816", "a00260.html#ab90a4622392e233e4846547e95d15693", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3817", "a00260.html#a58b7b4033f89aa0ff9779bf576b50e29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3818", "a00260.html#ae6909d2ac31fa524e78a3422b0636ea0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3819", "a00260.html#ae36ab80f3e312061f05d0e2324e8e7ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3820", "a00260.html#afed34acdb1549a0c3d13f7fcc273d322", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3821", "a00260.html#a2a54d3eb121231c0c7e0480091b81f55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3822", "a00260.html#a21510fe55119ecfb3839ed78ba57ab6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3823", "a00260.html#aa8acb803214c40bafc28c569a3d3c583", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3824", "a00260.html#acf48637c891675e1b9b9ca03559a7835", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3825", "a00260.html#a5d815ca68883d51b823df4fe66a93a84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3826", "a00260.html#a109e0ec29214fb3df9ddb3b1c7818bc7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3827", "a00260.html#a5edc000d04f24efcb47ed9dcebdd9a2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3828", "a00260.html#a85660434829daf7605d4560555360d5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3829", "a00260.html#a898f7419eb333b46b1585b44e2549b30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3830", "a00260.html#a07ee3c5de5efff94f3b6e17a0136a307", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3831", "a00260.html#ae7701118ab0651b15ea2ec6de13a7cc6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3832", "a00260.html#a7959ca0c4b38dd5d0ee39444f1457d5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3833", "a00260.html#a7b90ef21a3fdd1281521ed9097a7d53f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3834", "a00260.html#a61084d6a93206ddda7eda5a4a6bdc1d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3835", "a00260.html#a641569408421056e0114c0207b43b151", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3836", "a00260.html#a385f9c6e601f0a65342d2f2cb222a95e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3837", "a00260.html#ad983ff7ac8fd0baab4b7659c97f573b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3838", "a00260.html#a152b7279f06e9044578ccd184a50a911", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3839", "a00260.html#a724d79af9ea1f401dff37d428d17b778", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3840", "a00260.html#ad0993e2d1ae196357ae6a6e08d8e4898", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3841", "a00260.html#a723bd5e3372ffdb60bd74ad70247a24f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3842", "a00260.html#a12e9ae3afbc6194023dd6a200b8d59b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3843", "a00260.html#a05c354a7de5f0a496edd0a37712ab9e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3844", "a00260.html#a5a305283385e6117665ea3d593cbdde5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3845", "a00260.html#a429ee3abee4b5df7d8ffc6b4018def83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3846", "a00260.html#acb5bbd5165f55336e2e24365e4c0c062", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3847", "a00260.html#a1f95185c188c87f9d2f25e12adb1ad88", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3848", "a00260.html#a43adc638e647c13f69f6a7b9c5f9687d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3849", "a00260.html#a4e88996a80f9f943b33cafdff7a5ad9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3850", "a00260.html#a7b05ec66dc08c55e58ab413a7c8b4926", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3851", "a00260.html#aab7124de89f7ba6d75e3b6c5412efe07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3852", "a00260.html#ae49c96180299bc164e1e2cf08af8ea7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3853", "a00260.html#aeb46bcf90551321d240c677057d3d56c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3854", "a00260.html#a639fbca00962d43af8aba170c74e8133", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3855", "a00260.html#a43f7d82b92524ad5df596123bfbea9a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3856", "a00260.html#a0df83755a4c4c4f75a0e545a7c27d43b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3857", "a00260.html#aa329fae4cbd0d5474edf14ddfd960215", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3858", "a00260.html#a6101491aa0dfe5cec050a0d00cbc0f70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3859", "a00260.html#a46010c26c3e5a04be305961ba4e8ee4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3860", "a00260.html#a20bf6027af019ad755986e75d4eac73c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3861", "a00260.html#a2e6de0b960275543cbe4a15c999013fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3862", "a00260.html#aa75f7493b92a0ad4b6553235ff5f9a7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3863", "a00260.html#afe069e8710c144d581c116d1ac8c9b9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3864", "a00260.html#aeca9119f0c2d20a03bac31a6a1b86981", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3865", "a00260.html#a7f1de8a6417c5e8ddc18e0b7f5cf361f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3866", "a00260.html#a3f43e33325bbddc33d6c9ec78d525c06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3867", "a00260.html#a5b80b5df0156b604b67b549e7b0c5b3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3868", "a00260.html#a0711a4953ba1d915d5b2ec777a70bb7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3869", "a00260.html#a5d81b19afe36aacf147a118dc9c1836a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3870", "a00260.html#a09d36dfbc5911297d7c82fd0d0679962", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3871", "a00260.html#a6e483d465d224cf4043c2204ab6c77c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3872", "a00260.html#a7a4889ad4fe231283d3c5b3081d11940", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3873", "a00260.html#aac79115c7a65ae8fc4276bb2ea925801", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3874", "a00260.html#ac4d014d88bd27aa8897bc25d96fcd2e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3875", "a00260.html#a9f3fa36f55aa7d0e985150182d501cc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3876", "a00260.html#a050f89da61a19b2f0e11d5eb59804616", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3877", "a00260.html#a89b5d6c0cbd968676b5892b8a6f52af7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3878", "a00260.html#ace827446bda37bd102d98f64544861db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3879", "a00260.html#a848f4b975f3752d978231ba7eed23aa0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3880", "a00260.html#ab0afae7ce076802246abf93aa7cb191f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3881", "a00260.html#ac0ea38f53f9263f5d1983c62bf83f774", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3882", "a00260.html#a74db7f4a93edbe4178d2fcf177351a62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3883", "a00260.html#adf38173d1df4e31de9f8870d82628663", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3884", "a00260.html#a269805342940b94ab3b616ac98aa2d0c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3885", "a00260.html#a86ac6be9e0868b2ed9f4e7745e97495c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3886", "a00260.html#a208940033a360da9ef5b71a35036eaf9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3887", "a00260.html#a5358c853faa8129d04928fbed83f69b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3888", "a00260.html#ab515d06f15582bd0169bd069a449e48e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3889", "a00260.html#a43ba067467b48559202c14f03bde1339", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3890", "a00260.html#a2718dee70a7d9baee2a77ab9b08f7ca3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3891", "a00260.html#aef7b443cd4790ce3431c1b8b8ea1bedb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3892", "a00260.html#ae535c32a6a4fb71bfe79014ddc2df21b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3893", "a00260.html#a45e79755ad9f60620d49e42d3804319a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3894", "a00260.html#a9890ff4941063b1c71b90f61d8fe5c4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3895", "a00260.html#aa647fe0a844b42c96f935002dc3ddd9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3896", "a00260.html#add2bbd3e385dcd0a0a9ac5a5905b7ad5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3897", "a00260.html#aac2e10bc9bcd7a3834f535dd6cac19e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3898", "a00260.html#a64c2ee9e305ed7bbb77411b5913c8111", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3899", "a00260.html#a7b0e0aa3777001dd0dca87c619f3e404", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3900", "a00260.html#adb38e9a085536e7d05f9858ba84a5a56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3901", "a00260.html#aebd0ae1a3841ce33f1f934397fb4fa4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3902", "a00260.html#afb2061dab8849c8b788207f26fc14d99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3903", "a00260.html#a6d66ac4309be6a3b23222712048cf800", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3904", "a00260.html#ae429c19000c1365db74995cda1867e18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3905", "a00260.html#add1be236b0eb6a59b3052c4c5b220553", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3906", "a00260.html#a153fea48b1c80baa73070ff53f526d5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3907", "a00260.html#af9dc39a6522bc20c442222fc6b872c6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3908", "a00260.html#a1346f7762bcdad21750f20611cdb1373", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3909", "a00260.html#a767a7ea1a3f77b4ac8b0d3f3e873898b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3910", "a00260.html#a49dc6e19ae45874be88eca8ecc866b49", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3911", "a00260.html#aaf37078329fc0a7e90347b5e3ee83c82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3912", "a00260.html#ac1abb2c11c9d75da7ecee68444850bec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3913", "a00260.html#ab0e659b65a5294c4b102450d56d2e5c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3914", "a00260.html#a183656bede1d847d61d43f21cdbb9947", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3915", "a00260.html#a0874857ab0809d5d93c249c07b10bd68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3916", "a00260.html#ac15e17285eeb5b0e2a9d6c463a80215d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3917", "a00260.html#ad033eabce549d1458a67590091b1a31b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3918", "a00260.html#a438e3c2a9742b9c343e08d4732729c41", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3919", "a00260.html#a9c2f9aca4650d3cfaab00637037a8ec1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3920", "a00260.html#a634e3b8d75ee2a83abcdd2dbd8f21553", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3921", "a00260.html#abb8d10a2dde0af0fd90265dce452d68f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3922", "a00260.html#aa4a43de5f82f06a34e18a0961c294f38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3923", "a00260.html#a9576a21fb883dca83e6d789244bc769f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3924", "a00260.html#ac3ce8b71361179be53617ad274bbf9be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3925", "a00260.html#ac3af6479b06e4e201e33cca538902a36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3926", "a00260.html#ad25ae4f8253c6b6067aaac6b4bf8857d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3927", "a00260.html#af11c52767aed2e47fefecd57b6f1f454", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3928", "a00260.html#ad694e5e8b697542b5e33f648821dca27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3929", "a00260.html#a4a318b53eefb11d4a20d833cf1fa5400", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3930", "a00260.html#ac74da7d3cffea2020bada08f52325670", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3931", "a00260.html#ae28ec2d0d55927b3b29cadfa1a1b17c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3932", "a00260.html#a683adc421c8c2001bdf5d0492824e27f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3933", "a00260.html#a30e7f59aee97f60985dce5383b5b662b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3934", "a00260.html#a77a549e5d6056212689090c27be14860", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3935", "a00260.html#a26284e85a1f107326eb563b77cfaeddb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3936", "a00260.html#ad4173b395fb4a711d66770265d644880", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3937", "a00260.html#a5ea7cf2468731599b24b2e048247e055", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3938", "a00260.html#aea6150afa4ab3a79884d1a9047fa541b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3939", "a00260.html#a10bc38d023be3d7d97727d94337f1a7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3940", "a00260.html#afcf4269f4e58058afbf99340e2c24775", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3941", "a00260.html#a54f1ad0e90a27156b171ee3b5e3ce62f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3942", "a00260.html#a885dccb9eb8016bae284b9410ac42d50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3943", "a00260.html#a9487ff958f9b07c9ead37bd2f508d11d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3944", "a00260.html#af6e225bfeb83047003d58a8efe7999bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3945", "a00260.html#afa3360891d442673d86842670058ef3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3946", "a00260.html#ad4e3d1be0e6c048a71bbca2c7aef20e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3947", "a00260.html#ac230de62f26330382a4c82aeffef4e6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3948", "a00260.html#a0da307d0f93463ed5be0f17cff2938ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3949", "a00260.html#aca2df3e5ac2b99f2fdba41ebb41d88fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3950", "a00260.html#ad24fba74c4bf37acc739d5a873bd99f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3951", "a00260.html#a616cbef45cc7b2b759218c7e1f16a0c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3952", "a00260.html#aa136dfb90cece33e315d09e824e086a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3953", "a00260.html#a878f1bb19239a55e33a098d3703efa5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3954", "a00260.html#a0c9b6be414657eed284a5aef7af6ba4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3955", "a00260.html#aafcf9b83cf8e334ba8b522f63db6d7d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3956", "a00260.html#a54c64385b68c53567b3db9f6916f0cb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3957", "a00260.html#aaac537b90aef45548a5f7bdb00a6f80c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3958", "a00260.html#aba0c42c77114ff323f5fd8651a62b25d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3959", "a00260.html#a76fdbbe10ba480728a0ad4350663780a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3960", "a00260.html#abd0eb5a592ec10daee5c5774c071c7c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3961", "a00260.html#afaa3acf34d6848882d1e03c0d439c6df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3962", "a00260.html#abac276d03b96fa48d4cdabf5155736f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3963", "a00260.html#acc0ce360546f181149a6e64d917deaeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3964", "a00260.html#a2d175b39877cf6da6a008de468e9cc68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3965", "a00260.html#a10776f667d46c17568d266709a84803d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3966", "a00260.html#a084babe86116f576eb154d80a5ff0070", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3967", "a00260.html#ad8de3fe1a7c24d4d625580cd3c5dbe57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3968", "a00260.html#a2e99597b72af39f1e46b6e080f145852", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3969", "a00260.html#a7a2cd99aada3eb36629ab2ac64825d76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3970", "a00260.html#a0dc9968043628a2c5f162c4faff47898", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3971", "a00260.html#acf607299d6c430f030ab1dcb35d60a88", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3972", "a00260.html#a8398f18f3d9d361f5c54b681911f00bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3973", "a00260.html#a5cda267a47cecacf052a097efbae6023", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3974", "a00260.html#ac9cf94ec3c12a3d39797f23e462e7b55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3975", "a00260.html#abca39d7c6fa74b749c1763ab35beaf9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3976", "a00260.html#aa715b706b2092d9b9fe26365bc40f2c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3977", "a00260.html#acf6376bcc78dc00c6753731a4509808d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3978", "a00260.html#a28463816a27694b49bc6ca240370a216", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3979", "a00260.html#aff5010d792670462d6e524ffeb4bc7f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3980", "a00260.html#a57958acbc355734eea644b27d52aab3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3981", "a00260.html#a60ab307dbf55a9ee1be2f7e6b73c6809", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3982", "a00260.html#a3b9a96334d7ec84bc7b08510f509453a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3983", "a00260.html#a2cd9c08ef9ae61ae6b604ebf5d14a5bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3984", "a00260.html#a4ed41d579f29416124c01b3cdfec124c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3985", "a00260.html#a1fba6eb471ba17e89a7bb1e4a0003627", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3986", "a00260.html#a4d8fa8174001447fe4f15772e0ee8050", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3987", "a00260.html#a3ba01e2d8a436e17889ed0cca297c6b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3988", "a00260.html#ab80e261f6a1a807220ad17a5744ef514", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3989", "a00260.html#a066e48203f9ee1a94219b51b531b34fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3990", "a00260.html#a2db981312e1279520fe9a5834797dd2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3991", "a00260.html#a92f51c934f313b61b6159314a6f56b6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3992", "a00260.html#a49464e7bb8f1d4f0bb77c20a9e643e63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3993", "a00260.html#ae312764e66169502472d86215298e595", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3994", "a00260.html#a53656c693ab39105f65505fee717773d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3995", "a00260.html#a58ffb19a6b483a775bc1d5edb16f0e07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3996", "a00260.html#a5b724a330246ae0a3e0bc1abcd3102e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3997", "a00260.html#a1775876a1b0145f6d2a53d6becd99c2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3998", "a00260.html#a7a765b831a12092007436b5c4283707a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3999", "a00260.html#a6724ed78e3960d2acc25ae8d4dbff81e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4000", "a00260.html#a48539e2f48ccf88bab60a9cad39aaed0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4001", "a00260.html#abf2578176e1db2ab4fced2b2673c9203", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4002", "a00260.html#a68028bf1f731a07a4c2165707e3928c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4003", "a00260.html#acf45b6496638901a4f5aa64b5c4da6f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4004", "a00260.html#a3839599889ffb99b8b6b5b7b2344302e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4005", "a00260.html#a9dd1c8ababd4cdcfd59dbe14847ba9e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4006", "a00260.html#a651db45748b45c954f089adce42dfbac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4007", "a00260.html#acf00f939ebf75581f9dcd8695b7a4f65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4008", "a00260.html#a296c4505e35d3edd6357a949a2aebfb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4009", "a00260.html#ac87d0c5a9c2e99ea7d9c481264972f5b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4010", "a00260.html#a64c2e8eabc6efd9327422a613ba4d46c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4011", "a00260.html#a4dc1b0697737514a37f74cb26a40a61e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4012", "a00260.html#a6e5d2d320add413282222fd48188b780", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4013", "a00260.html#a6ef2c3a3a9b16197c6ac57e6c7ef74c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4014", "a00260.html#a85da155dec89c5183d0457ed863a04a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4015", "a00260.html#a443bb9b87743d6aa8c5692adcc5d184e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4016", "a00260.html#a2f669a09a25f6c181f9ae558476b5e7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4017", "a00260.html#a15f5ce279587aae9bbdf2690012252e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4018", "a00260.html#a7b25c69a6e7840c975ac8fb78c9abf1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4019", "a00260.html#a069e56a80c7860fc90993c51525b7da3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4020", "a00260.html#a4cfb63597c06789cab7c58a1673a53ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4021", "a00260.html#af236d8535ec0a7a64bde37765b3febd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4022", "a00260.html#ae70d572a9e4f233051c50ab30612d97d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4023", "a00260.html#ade52f5de862265761f58b2f8be5b0166", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4024", "a00260.html#aedd5e02b1a2c72da04cef8e4c230644b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4025", "a00260.html#a37462dbb63f9215d8cdee159296ecac6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4026", "a00260.html#aa67a2bddb9861033171f9857faf6b42b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4027", "a00260.html#a4aa4548f9af5bd1a0597861b2bf596be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4028", "a00260.html#a245a5e215763974ec5a8063ebd3cbd84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4029", "a00260.html#a39153c11c796fb7c410446acef2a7947", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4030", "a00260.html#a4f942460d17ec0a40e886f277c9f025c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4031", "a00260.html#a26354914b5fe14f92f76aaacef65cc6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4032", "a00260.html#aa05eafa7ede1d21040f6ca54fbb4b285", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4033", "a00260.html#a6077332790568ec9b05c2a9df1cc95e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4034", "a00260.html#afdeac58d8ff633c1ea019835ff3b0fa0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4035", "a00260.html#a307aa5663630b417c534df42c883ba05", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4036", "a00260.html#a4e60702acff5814c511ab4431b015ec5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4037", "a00260.html#a644c365021e5b38af970a94e7b41304d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4038", "a00260.html#a7a54ad456e0502a3924b4995e12b1dd0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4039", "a00260.html#a0cd70d3c242422dd99771d6954183072", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4040", "a00260.html#a10e0565e8f2b609e831b08430bdbb0f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4041", "a00260.html#a0074950e3dfeb98d3e364ace00b262a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4042", "a00260.html#aac1325ff9bf70db04ecdb2049a913b26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4043", "a00260.html#a2bd7c1743299f0893800b6bb8e46e130", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4044", "a00260.html#ad4c98d1b9bf51d4d75a4672213839cca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4045", "a00260.html#af388fa6d002690b64ef1f01ff0f1a779", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4046", "a00260.html#a715f47a362604da70042e6aa97517dc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4047", "a00260.html#a99c61fc1219440f6c1d88e2daf8f582c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4048", "a00260.html#af1e139185b4352d62d6f5cca96ad5b7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4049", "a00260.html#a300a7d33d6665f4ef6ae887c0c1e0a08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4050", "a00260.html#a14200fa7ec5c46d32fc47f4ffcd6dcb4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4051", "a00260.html#a2bc6a395e6260cad448afe439f74e3fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4052", "a00260.html#af31e8e0a75e471f28b38f6351a7603bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4053", "a00260.html#ad4881a0d828d869b4e169dad16842a65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4054", "a00260.html#af1188c23b62697e86cbd056a5ad9ced3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4055", "a00260.html#a10f8ee268265e941d6663af67a564f81", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4056", "a00260.html#a1850b41812c1cb0091f0a495124816b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4057", "a00260.html#a738abbce72c34d0b6a2ae1538fa0c816", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4058", "a00260.html#a867283c6e634a6f0c494272089bae068", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4059", "a00260.html#ae0286361a681c538f8754600f97b548a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4060", "a00260.html#a82165c1c2a66612a4d436a4d561edfcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4061", "a00260.html#a734c97715ab0a2deac5e8926def21ff4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4062", "a00260.html#a808290c4d680f07af387213b3d197bb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4063", "a00260.html#ad65f569be4e1dcbbd499e738a56362f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4064", "a00260.html#a9c21ad8acd758ca9bafcabe7d2ece74f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4065", "a00260.html#adc9a788fda7ea07f52634612c186535f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4066", "a00260.html#a58e409328e5f9a773fbf8c0e9be564b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4067", "a00260.html#ade69e2b06bfb5b081b0890c3b874094b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4068", "a00260.html#ac4854aac89610032fc16e1f2843c110e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4069", "a00260.html#a18f7f81dcb6a13d4c6346c39f467ebf1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4070", "a00260.html#abbfa318d91a43bb47f5ca87a89e13dd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4071", "a00260.html#af68c5b2777d19b7e59d00a466f863934", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4072", "a00260.html#a29304e8ff758a58dcaa9df8a59dbb5c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4073", "a00260.html#aaa59c76a41504555181e3b683eff02ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4074", "a00260.html#a416766010931ade8eb0910053e0435f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4075", "a00260.html#ab628f3095f4e079e0e12bd365d07f620", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4076", "a00260.html#ab41272c21a7a8b2bdcb1ca49a7b6503e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4077", "a00260.html#a8c360fb09ad62cf024e692be20dc3a6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4078", "a00260.html#adfb686fe65c2a3cb2b65ada1cdeeb8cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4079", "a00260.html#afec8ba8d1289a79cc15869e923f4e676", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4080", "a00260.html#a0f33178574bf6ae810e46ce48a95fa8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4081", "a00260.html#ac11d11bbaa58984ba47998c8660f7e23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4082", "a00260.html#aef6c83c6e6fc3dc9222fbfd541740e08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4083", "a00260.html#ad54244af563f60a8fc4871fa1ff427aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4084", "a00260.html#a08918d122ddf71771fa9a50f86ecf49a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4085", "a00260.html#a5e1bdb9b07ceab392f725d1eb4a865d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4086", "a00260.html#a5f4ef33e13ae8709dfcb7cb9ed89469e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4087", "a00260.html#a32f04fb518c06a1765455c9004998804", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4088", "a00260.html#a365152d4b1f79145a5f9ddfdae2b52fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4089", "a00260.html#aeaf9f7d60ffffc9448e0b1128844a42d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4090", "a00260.html#afdd053becdd885fddf3fc6088d3494ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4091", "a00260.html#a7d0d64300a5b6f7ac74ff71454fa65fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4092", "a00260.html#a21f457b1c30009db7c58fe31f459ac4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4093", "a00260.html#a969243af1b59abe971fc6d24a6759b27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4094", "a00260.html#a22c8da66aa575d4f5916d7b20aaf03ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4095", "a00260.html#ab44cce6fe82cb911bb63e3d9252f84eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4096", "a00260.html#ac8108cb16c6dbe57985e00c4c841a0cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4097", "a00260.html#a4fbf8a5a592fdb94c73afe38e61ea3ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4098", "a00260.html#adf939d7248a8cdb1fc7f579d1e4c92a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4099", "a00260.html#ab3c10e88b649e363b02e91240cc13f0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4100", "a00260.html#a7be2e6a96399f27192ce48555d9fc9ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4101", "a00260.html#a929f950b4f62e17a040bdd47f22c97f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4102", "a00260.html#ae4a7d2e8dad7deb196313d1529137beb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4103", "a00260.html#a03e990bcf8560c27fa452702d9d4accf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4104", "a00260.html#a576b2495103f839612bbd07d5042ee7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4105", "a00260.html#adb6e5ae080535be694e4ed3caebabc30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4106", "a00260.html#a04e072d7965ba630aa5028f699e2411a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4107", "a00260.html#a162f393682c5dfa3855519ca40f64d72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4108", "a00260.html#a1c8ddd5a8241e13ff141e653217dc1fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4109", "a00260.html#ad9ee5d2127ee41663848bd0350b52434", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4110", "a00260.html#ac4e9956708fb79dc2bda5fc9b8163080", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4111", "a00260.html#adefe8941ca495e29f98ff3810f48d964", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4112", "a00260.html#ad3aa6ad36261afbdfadd5768748594bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4113", "a00260.html#ae182dd10cbfdbddc042187deda8e0cd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4114", "a00260.html#a2a26d8443bc2fd42368047b8a888a6a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4115", "a00260.html#a3abc4d159e380cb2526a37d5c9d00f69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4116", "a00260.html#a8253da6e9f175ca97b49cce1df4662b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4117", "a00260.html#aac4ac7d08863f1f24ecb0cb3bbbeb6b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4118", "a00260.html#ada1cb5f32a420170deb9c85123ace884", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4119", "a00260.html#a65afa90ca49b3567064d2e2d43dfa289", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4120", "a00260.html#a3a170df0145f8605be0b5aeba562f249", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4121", "a00260.html#a44461d6add69883ca8fb8c3c669b8986", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4122", "a00260.html#a1c9bf01ff413d4ce4dbf66ec4947bd0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4123", "a00260.html#a82e7731666d735c002228d953b3cc09a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4124", "a00260.html#a22e6f83a547ddad2fc129dbe9a79928e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4125", "a00260.html#aa790cabda6bd5629677579e132181628", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4126", "a00260.html#af6b382710f20f0f8cb682c2fa9005924", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4127", "a00260.html#ae2bb89c0c7224fafa5a621f09b23a41c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4128", "a00260.html#a9d0ccd555acbfd14a45e0df9b8ef939d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4129", "a00260.html#affb302052de97a1a85e62000b692d096", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4130", "a00260.html#a602b3d8ecb93c0913402b7759ca7ccbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4131", "a00260.html#ae4311c2914d65992fe97af0400ababa5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4132", "a00260.html#a0b4eb8508e49a1988a5cd4a11555b584", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4133", "a00260.html#acf6c98bd97736d87bfbc47cde54b4582", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4134", "a00260.html#af874a644fefa32e8ac33f28415286cd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4135", "a00260.html#a433695a613c3e81395fbf4fffba53cfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4136", "a00260.html#af7019ab174b3510d845fc63c2f36a6d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4137", "a00260.html#a880c96b60d369ebcb12780ca5acad437", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4138", "a00260.html#a03feff49783b0da5c5894038b949d6d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4139", "a00260.html#a843fc48cc53d0a1dfe2cace177661137", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4140", "a00260.html#ac2cd8dda8e2a35a6433342b9e1c04ed4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4141", "a00260.html#a2f3e977ec058a855e4de9070c904689e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4142", "a00260.html#a15e2986e79b8fcebc935bd3e1dacf87a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4143", "a00260.html#a1309ce8f9c94273c0f5edad130c5f340", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4144", "a00260.html#a5514084b2742e4ffa931bb6963bbd1ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4145", "a00260.html#a19a7a6dae421b8076a2c35260666f7ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4146", "a00260.html#ad960a1b2bacef23f3c929ef3ad97178c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4147", "a00260.html#a5c16a5727242c2db4bc2d62c47128cdb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4148", "a00260.html#a27f1494b787ea03cd76e802550768d5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4149", "a00260.html#ae2617e465ff39016387d95597486ecf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4150", "a00260.html#af867897c31f6c86bc81ad8ab97e37484", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4151", "a00260.html#a2722cf16efb55432872b113e76959748", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4152", "a00260.html#a8a10006027fae7b63933e4c583694229", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4153", "a00260.html#ad168e0819006cd0c8771321fd5d69c53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4154", "a00260.html#ab2a9d4aa5c8c24709b8a9f899ddf41ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4155", "a00260.html#a76e3a9623f11e1e921fdcaccdfecd9e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4156", "a00260.html#a54657ea130d465812ce2f5d62cf43e6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4157", "a00260.html#a53fd77d204ac48919114f92d0aa62ff6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4158", "a00260.html#a8b4426f36cad8d591e329a7032e8baf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4159", "a00260.html#a11e4b09cde96e2e3b20b6ff21ec37927", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4160", "a00260.html#a00ba8cdf253d5183d4886eeab942c0c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4161", "a00260.html#a0f5a203be2d4247fd7a0503f6b1ed3d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4162", "a00260.html#a35005b788ca45ff59192abbc6e5872c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4163", "a00260.html#a5d94df3490ccad9bdaa3f577c9871d54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4164", "a00260.html#aab2b994ed575cfb8e3e0523a896f421f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4165", "a00260.html#ae7839fab4f55176c48330f826de7a905", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4166", "a00260.html#a64b6f6452d89bf5f2505a062992afc6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4167", "a00260.html#aeb2ee47ebcedc6f788aec95cb909dcc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4168", "a00260.html#a6f22e6bf43313023e066ad658d380710", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4169", "a00260.html#a40abbe8211992f8af668497af99edc25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4170", "a00260.html#a1ce86694b78ab8e6ee1612eb4663fa2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4171", "a00260.html#a08893b595b65ccce565118ece28aa481", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4172", "a00260.html#a82a3d690458f8b55876c1ae6a1bb0357", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4173", "a00260.html#ade712bfd90c2e813703690aa76582cb9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4174", "a00260.html#a182d5c4f78cf991a8efbfe81154b417d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4175", "a00260.html#a7b4c37cf5487f6e18e6905e3c563fa0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4176", "a00260.html#aff594de6e3d90a56ced337f8175f71d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4177", "a00260.html#a7dea8e6a7e2f950cfc1b6ed171552d84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4178", "a00260.html#a392cd40292fec73dd072e25e0426ec27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4179", "a00260.html#a90a6e2b4e0f739ca02c83564a308fcb9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4180", "a00260.html#a21f41a08558551f875ee29b7bd6daabd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4181", "a00260.html#ad5ba7a1b3a7842c6025f3ed9e3a4b6ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4182", "a00260.html#adaf4c2f8a49d42fb8c2d90a18c8ad1b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4183", "a00260.html#afde0ddffd8e58794acf0e89491ff39e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4184", "a00260.html#ac6f9fba8cafafd5436ea98c86e59c939", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4185", "a00260.html#acbd4fbae172f7bd6f89b263e800e32b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4186", "a00260.html#aed9a5756744c3aa5076c295af5df9f63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4187", "a00260.html#aafb4f73ad0f672912ef398a5dc2392e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4188", "a00260.html#a1ef8601f2eb6c61ab535d87bd0af1f4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4189", "a00260.html#abccdd79c01772f8c2b22b63e11ab76b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4190", "a00260.html#a608f0a7e33be9d650c12d31f60eeffb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4191", "a00260.html#ade92e48ce1ea1818a042d15cba53db66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4192", "a00260.html#a416d473ed447e1795f2b735f63175700", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4193", "a00260.html#a535bd60e427978342f79d8c63e347254", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4194", "a00260.html#a831523b07d9abe688bc8daa38c00f9e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4195", "a00260.html#a773e5f3e071a279cd97c2f7181b0ae35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4196", "a00260.html#a29be065d2fdc0780889fb28f705c13c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4197", "a00260.html#a7a0e570907714b81f8505e63725317e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4198", "a00260.html#a3a3d06f1bfeb8153d92d3abe26c02dd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4199", "a00260.html#aaba3957e40d531aa9451cb2cf19f0eec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4200", "a00260.html#a7f49bca2e6cd7c9a2b9d93e3e7a9fb40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4201", "a00260.html#add00873a24fa9799d2b6b1caffe4a4e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4202", "a00260.html#a2ffe3547ddbe9df200316173b1320175", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4203", "a00260.html#aaec0697385cc61e6644bb1bf8753a15c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4204", "a00260.html#acf945a01deffd90b64cf85cf12eef46c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4205", "a00260.html#a3bb1240b11c49502bb44ce06797ca0f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4206", "a00260.html#aa1222c16e54ddada3d8ecf6dac911917", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4207", "a00260.html#a2b00061189166d1430abfc07d0302a7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4208", "a00260.html#aad200fa5ce48558e55e7afb84d0412ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4209", "a00260.html#ab6bc00db95961753a7acd0deea4124a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4210", "a00260.html#a44ba89ea251395ddfd1f63d9b1bf1dd3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4211", "a00260.html#a3b2188dc9430e70599463a8313d667d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4212", "a00260.html#a69cc0002a03e1e55c4e3c556b712c426", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4213", "a00260.html#adffb77fb0076a7d712db26594212acb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4214", "a00260.html#a01a06581f89624b288fd793fdf2c1569", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4215", "a00260.html#a327bef746ede178f7d71919545b33b2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4216", "a00260.html#a3b25a877742facd73b70d972441b5d2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4217", "a00260.html#a491edc51bba9e9855416b9e0fc0c52ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4218", "a00260.html#af87d92f492e5a36681c435ef087732b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4219", "a00260.html#a8e773f44f33dd6eebd08ac906d365ab7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4220", "a00260.html#aa3f4c78c8db44dd7ac3a2ac6c54f18c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4221", "a00260.html#a6a995191019439c0cd116d3a876b0b35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4222", "a00260.html#ac9cc3fd830b894b73fac10559ad975e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4223", "a00260.html#aef075974873aa71abbb41567039f05b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4224", "a00260.html#aec4a965c1fbd66e3be844381314e2e25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4225", "a00260.html#a12793e0fa81ebd75348815c90f984523", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4226", "a00260.html#a2f049c0d5bd66a1bc322f7b3f458c600", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4227", "a00260.html#a288592a0a8deca4dc809ec8969697864", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4228", "a00260.html#a23b096a2199c11146d4548cad59aac39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4229", "a00260.html#a271dabf2d74d35bd40053d7d0156515a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4230", "a00260.html#ae39d36bf009402d312896ad2c41746ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4231", "a00260.html#a65d33ce6ad8660d2d8d0411eafaebc37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4232", "a00260.html#a6ed28f1044e05ccd21f9b37e06c028eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4233", "a00260.html#ac28bd0f99e260954f3c101a28aaa26c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4234", "a00260.html#a350420b39f164b3c067513c0fbaeb351", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4235", "a00260.html#a173fa7edb9640f29c732ce6238611440", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4236", "a00260.html#a99ee331a7c911733222aa6c257d03973", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4237", "a00260.html#a80f3f1c1ac28480eb67479c7d1356d91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4238", "a00260.html#ad51105476845d41673f8cc0ad234faf8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4239", "a00260.html#a36a1679ba2b1014a18fd3346ca5f0653", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4240", "a00260.html#a4d03889447c0438f2bc880f0dcd6fc87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4241", "a00260.html#a30aa172686cd5b8cdd9fb54961b7db5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4242", "a00260.html#a686ce4390f49d360fcdf3e4ffa45ae03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4243", "a00260.html#a8ac58e1821261d5383108425ab384032", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4244", "a00260.html#afe79bf6249459e6e5c45f3d840a42a48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4245", "a00260.html#a2d795fa5f6b1d585dab4d881f646f375", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4246", "a00260.html#aeaf8eee3bc5903259a13cc24c7391a2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4247", "a00260.html#a9ee74e657920c1317e842eade6b02c9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4248", "a00260.html#af3b361a24202c5e3190b6bef6122069f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4249", "a00260.html#ac319c073cfbbef75347d0c23e6daa0f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4250", "a00260.html#a66be1f62af4f122be4defff211b4462d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4251", "a00260.html#a9ae621d74cc6e643da698b49befab784", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4252", "a00260.html#a8b9838c48083e7a7056cbf7c3950442d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4253", "a00260.html#ad7d6a47e25a09fe4ed16a74500d2bd1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4254", "a00260.html#a5a7449ed3c6e2b53f3966d83d5d5f41e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4255", "a00260.html#a3c7bd95fb6c273283dca0cf7a03c0866", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4256", "a00260.html#a2c0e0afd810e1f2bb5050d25089586f1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4257", "a00260.html#afe77cda404002abda87bae0e31fc2796", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4258", "a00260.html#a6bc77412b31673b6b73ddb26c8b146ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4259", "a00260.html#a745569a56b873144e08b1ed62b0a40b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4260", "a00260.html#a66eb66b6960c2b28da9a341a08a0253f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4261", "a00260.html#ac443200954a5278528627fe7f8380a7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4262", "a00260.html#ad306543ffe76a073da70e27e78a7fb50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4263", "a00260.html#a97849919436884343233b7e3436f8840", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4264", "a00260.html#a7fd62052cd38486b3a0ab40f6c7b6322", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4265", "a00260.html#a2fdc25f20ba451b2c515b00934dfc7c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4266", "a00260.html#a301c6933c7f93e0bd4309d0b51ee8d3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4267", "a00260.html#a8bd6ac46827362bf2d7a52810b975a96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4268", "a00260.html#aaf83f6b389ad9f2e7062a6e3756c8691", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4269", "a00260.html#af845cd0eef159603cbf019f6de4e19f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4270", "a00260.html#a48defc1208729000085f499c4a5340b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4271", "a00260.html#a42e7b560ea87b9db7bbde94f449df48e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4272", "a00260.html#a18b210adc155241550c7aaa89ab4454a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4273", "a00260.html#ae728f65ecd808bf50a56c22b0dd609eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4274", "a00260.html#afb95e66c111c3a16541a2895e66aef23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4275", "a00260.html#a6b4b8f56cfad9af8f394901bc9151677", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4276", "a00260.html#a66d522ba80b292fc7dc5530fc1d503d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4277", "a00260.html#ab926b5ce2ac8db0cd7787cba6a84283b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4278", "a00260.html#a028591c37d00611cfa0bf94812348d04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4279", "a00260.html#a5f42a543c71cf66317b36556f5f69cab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4280", "a00260.html#aaaf0e7b75d24e2c1a86a025f9e7e927f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4281", "a00260.html#afd972b54cc0785de435b44e6cc5cd097", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4282", "a00260.html#a91ea33ab5f749c418a525b6324c2f333", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4283", "a00260.html#ac605a6d83008e29d28d53499ee36e1b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4284", "a00260.html#ad47279eaa3edadbead52e552ca31b1c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4285", "a00260.html#a2a069954de19fdfebbabe76367b1d4ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4286", "a00260.html#a5052dfe56e58ca2c9e33742ad0a4357f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4287", "a00260.html#a13d5f3a645f22de8c59a02a1213a7ebd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4288", "a00260.html#abc9590ae6f56d613c5c9394a528ba61c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4289", "a00260.html#a1fc9ee10f3a9aa1339129b71e5bbda00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4290", "a00260.html#af51cf8837d98653b73ecb793e01a8d3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4291", "a00260.html#a5100729f032e7d768fe8eb1c540cf502", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4292", "a00260.html#a9a586e4f3519168c561733ce2c83710c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4293", "a00260.html#a3af8f856961a8ac0e46cdc580d7cab1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4294", "a00260.html#a9527fb94833b4bea31d3ccdb668ed0bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4295", "a00260.html#a2f1f7b2df1b7bde170ffe88e566e16c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4296", "a00260.html#a617907a2f0146b7ae33985c1dd756344", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4297", "a00260.html#a8e043437d8172efbb56892871991fce6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4298", "a00260.html#a7536f0cb3c2dc5bea6a33eda2fd0c0c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4299", "a00260.html#a2a14619fa410116f2e6275261b02295c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4300", "a00260.html#a979c6814fba9da7df70cbd69e8e67b43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4301", "a00260.html#aae296df7269272c7b6af672745c6d724", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4302", "a00260.html#afa637f3d4e23a327c661519000edc44c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4303", "a00260.html#aa500a8179aaf2210260553c59d9f4ca2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4304", "a00260.html#a611d96402a34f190ba736fa735d038b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4305", "a00260.html#a7b9bb159e859881759de2528b02d67ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4306", "a00260.html#a430e577eacaccef252704b6dcd91dc9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4307", "a00260.html#a6f51877dae546d998183dfd64b7fd34a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4308", "a00260.html#ae6c4b58883176ed32d5afc533953838d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4309", "a00260.html#a5908c14f0c8654b8c064facc0924b7cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4310", "a00260.html#add109ac91761c2e23beea5b01fa4f87a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4311", "a00260.html#ae0e3f24c527a9f6820e57dd908ec2643", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4312", "a00260.html#a9f4e4d7049688a94d4242a90c40d6dfe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4313", "a00260.html#ae161b842641659dbe72cca1eed7ecbbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4314", "a00260.html#af5a8f5746d438e46b86d3e6d8193e3e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4315", "a00260.html#a00176870eac9afe161c92834de1c1342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4316", "a00260.html#a2ab75f65a506155e0eb9bddfb1cd24e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4317", "a00260.html#ad0d37e37fcadb19159d47a52cedcc512", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4318", "a00260.html#a53dd9439f395cad38aa76f1bd83e22cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4319", "a00260.html#a12d96c271d613dbb8210fcd4f3d4e12f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4320", "a00260.html#aa129e0af6f5134f4c7905fbb1afb7fef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4321", "a00260.html#ae5ae9d926a2c09ffa079ff34e51871da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4322", "a00260.html#af34d373f67b99e03f4d7b1716abe76fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4323", "a00260.html#a0e856b8356aadb8c3adfec604bb78598", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4324", "a00260.html#a346a24f719da985f480cab002b4b9474", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4325", "a00260.html#a181ade22019ca16cab7b657d1c6a3f71", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4326", "a00260.html#a3446c7d40d6d6b8e3a5efd2c6d524d34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4327", "a00260.html#ac3640af3b201ad0d49e9b3647552dfc3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4328", "a00260.html#a5453523c2d484f9ef81e1e7d7bf31454", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4329", "a00260.html#a303d2d326be5ecb88bfe0b3ab10e7c92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4330", "a00260.html#a8d4d0910f56101034ab5d0c110ccdea6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4331", "a00260.html#acaf1734d6942169b1a8266ae44b9275c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4332", "a00260.html#a58c4044366cc66f03cd00b8d3af50d39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4333", "a00260.html#a67fbd3dbfdb72a5b5ca1f5e9cca63167", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4334", "a00260.html#a532cfe8b0706cfdd4e2e044df7318d4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4335", "a00260.html#a55411b03d1e0a548424a0c6b9630f5d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4336", "a00260.html#a05b4a4118f9abe10246af41abe2e9528", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4337", "a00260.html#a264ee63272dc904589d926c029e5ff3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4338", "a00260.html#a614f9196cf1d73405d1bfc9be23b6671", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4339", "a00260.html#a998a50d0c480bb64bb0f633262c130ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4340", "a00260.html#a38e84344edb43fdc4b75790bcd4dbbb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4341", "a00260.html#a97ae42fbba136d502650199e2f9d4077", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4342", "a00260.html#a3e7090b5677fcade23f610ee4eb7a19e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4343", "a00260.html#afb51ac1bbe48d7ff6c5b1f36c15cbe08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4344", "a00260.html#acaefa04623063f86a1520599bddbc738", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4345", "a00260.html#a2fc68ae403c4ba89c8c2971842dc5109", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4346", "a00260.html#a595f1e6dc9bf674732d9f49933da5c80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4347", "a00260.html#a5ac944a936c7e94effa2d71e9b645b23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4348", "a00260.html#a596466e563d19f4807c048a08cf85a73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4349", "a00260.html#a173e758b12f602ec31c63788b74d8b64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4350", "a00260.html#abf36e40c402ed118b0d114a52b667020", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4351", "a00260.html#ae43ed185b0937f99992c8cc0ec90c6ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4352", "a00260.html#a0e7c548f15b1dc7538be974a4078cf7e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4353", "a00260.html#a3a654c78df9c92ebbb4628f509d75bb0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4354", "a00260.html#a9bfb9813b0b5e49e04e30a7ab5bb861d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4355", "a00260.html#a2002c5889e700c8f17272e6c23cefa0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4356", "a00260.html#a8b7627c0e2ce7b24a17a429929f18c6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4357", "a00260.html#a4aebcb20072170d6d7543940e79a2f13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4358", "a00260.html#a1f063d6eed67059264cebf738c85a68e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4359", "a00260.html#a06d88b95005e4fa415f1b92fd43b7e2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4360", "a00260.html#a04db1c8f1d434f138758e12495d3a521", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4361", "a00260.html#a031fecbfb8f92a260b96f531ca0e3eec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4362", "a00260.html#a11e0f24fdc2c3195fd83c248fa8e06b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4363", "a00260.html#abcfc45ff44f3972798797ef8bb841581", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4364", "a00260.html#ad71c79bbc330882811862fc7f31f6c1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4365", "a00260.html#adbf49e3645b5b5871f5856bf6707f0b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4366", "a00260.html#a3a7675941c38efd4721f553466a869e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4367", "a00260.html#a4b3969238b67ced2fb3a5baeab198d76", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4368", "a00260.html#a2ece09ee19435fac18ec12ecb56c4c0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4369", "a00260.html#a8a6822757a32d0bfedc592e87febf10b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4370", "a00260.html#a8c7dfbaef67872b329c4be8b46d49891", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4371", "a00260.html#a332723e20e759076f05e051cbef81fc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4372", "a00260.html#aac0365e437c034f6a104b34c861d157e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4373", "a00260.html#a5c7e4f83ffedc02f0915b28213143238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4374", "a00260.html#a08cd236e492f9df8b760905e09778675", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4375", "a00260.html#a769efa3d1ccf477493c96d5266c8dddb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4376", "a00260.html#a3b77df070e8e2cb7e3abb3334f5df864", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4377", "a00260.html#a2a840458476a44dc8fbd2a9879a6682e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4378", "a00260.html#a17e949e9f0b5b3b0ae80436deb54041b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4379", "a00260.html#af37f45c36b42eb33baf8918cc7261bbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4380", "a00260.html#a2de46a4e91991f043803c6ccfa444b36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4381", "a00260.html#a9bb97fc10945749c3d385a55a582ee21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4382", "a00260.html#addee487508676fc7539cb6b1a18f37e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4383", "a00260.html#a5415230d14d251817520b2a4024fa9e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4384", "a00260.html#a39f3be78e2b926d2c3bb4172700dc618", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4385", "a00260.html#a929334187f8f862c7be2546ee4b42cf2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4386", "a00260.html#aa2252e84fddf4ce204338a0b809dbfa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4387", "a00260.html#af54e12c0065968d8427032a21159529c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4388", "a00260.html#a65c9ecd369edc08c2800ab970372c8f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4389", "a00260.html#ad481bbc5cb99c51dce0bda36b40916ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4390", "a00260.html#a80d3c8bb2b5de569e5af4e7b529373bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4391", "a00260.html#a5ffa079a5c5a1e6fb97c1906f7a8eddb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4392", "a00260.html#a35fee50d1ae6d9039428efa8eb31c718", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4393", "a00260.html#a338813d0f2ea1b048542245b9971d9f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4394", "a00260.html#a080856a45d44a9e68816c27cc940a407", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4395", "a00260.html#ac3408c6aeba85a972a7094ea1e5cd952", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4396", "a00260.html#a45167d5b3f8402ea24a4e31b1b4a5c14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4397", "a00260.html#a435f52ddf33be3bfe915d848a2f1ed7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4398", "a00260.html#ac58b10cac961b9117933482230380ad5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4399", "a00260.html#a46cd5b352f171c4a74e51fa77db330b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4400", "a00260.html#a537db2c66a2701891635b48ce9a5260b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4401", "a00260.html#a4c8dee154aec74872657f98d023c2080", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4402", "a00260.html#a2f5c04d80f3e37e04081643256014416", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4403", "a00260.html#a592482ba2f171b3487d90397125bb530", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4404", "a00260.html#a23867a52a2259b0c0adf8f8d1150ea14", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4405", "a00260.html#a49950a97dbe074b4e942a89c9749e6ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4406", "a00260.html#ab57d501a2320bea4d0eba2235178701d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4407", "a00260.html#a50a38e4e7ceaf56dc6291e7176bd5ac5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4408", "a00260.html#a0d86e5d7589a76cc942312d6135f66b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4409", "a00260.html#a036bb951effb7bcc449797566eaf9e91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4410", "a00260.html#a879c75d747d8c0143074bbbc01b865f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4411", "a00260.html#a917680d9f4f2ddc6cc098536eeb5a9b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4412", "a00260.html#af747976ab73d8a3feac8d98f27f91054", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4413", "a00260.html#a96d12a2d65c231217259e6884cc19ae3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4414", "a00260.html#a9b9ccfdf6fdd51bce5dd5971c69321b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4415", "a00260.html#a68c0b633f60a3b603210d2446cf64b1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4416", "a00260.html#aec6b7d58cfc94258bc5a9dd344f60e24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4417", "a00260.html#a8038ec120219b7cc672eaec9848c82a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4418", "a00260.html#a3704a6f1b271e67daf4a0ee24105c66e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4419", "a00260.html#aae5ec126c3d544851a3830feb385616a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4420", "a00260.html#a621355a5edaab0c87e5f42102a8396c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4421", "a00260.html#a5872035c9ae6bf8052b40636cf524f02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4422", "a00260.html#af71469993d10f2e7c4a1f1db24ddcf1a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4423", "a00260.html#a1c2dd78699f67f3f51a3ecda6afe7242", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4424", "a00260.html#a7ddc498e2ee048459e657b15d7e114af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4425", "a00260.html#a734a89f3b20e2cc584f1737840e19cf7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4426", "a00260.html#a71989b90a3d0d648b3e1e57811ed55db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4427", "a00260.html#aaaf149c78416325223b598de058553be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4428", "a00260.html#a34228b406cb1138169bcfbee031a71f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4429", "a00260.html#ad4dd4176cf4f3aeceb6e59e50f2653f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4430", "a00260.html#ad9f834097ae0cb359460f1221ec53072", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4431", "a00260.html#a3dac0bd5833265ec0fd1550677909912", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4432", "a00260.html#a23bc37f051fd5f0a7e7e5e75a26c4ab7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4433", "a00260.html#a2a268c6735767d6ea8f04ffbb2e8ee87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4434", "a00260.html#afbaecefc9d455de4689ecb5f45e38126", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4435", "a00260.html#a43a63d65222b1f5bf56872092e385d64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4436", "a00260.html#a12e41ccbae947217e0bc16273fd7db19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4437", "a00260.html#a6781a15d944ca136ce6d8c0733809ca5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4438", "a00260.html#a233044954d3daf224c665ff1effc17d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4439", "a00260.html#a722aea983d5969d38a5d2bd4879a41e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4440", "a00260.html#a34387e03e5a5f36ad1cce6107793e7b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4441", "a00260.html#ad840bc91f45b928331383b4311c2fa29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4442", "a00260.html#a020f2f26edb8e4b8e29d57dc9e996e78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4443", "a00260.html#a4119dc289ad9dc23bb803640e02800e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4444", "a00260.html#a2ea1a53bd10fc147bbd8b25360d2984d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4445", "a00260.html#a83ec73277e12f335867f90b6e01117f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4446", "a00260.html#a06a8541233a5dcdac8cfaa4651427a1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4447", "a00260.html#a16bcf89032ab68f0c5487ccaed6c37d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4448", "a00260.html#ab7ec8b04fc5fc352bb392cc3027cb6e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4449", "a00260.html#ab344dcf23f6041d99bc46ef0623ddb33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4450", "a00260.html#a95d74685f8caa63dbb7c4635ef92265b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4451", "a00260.html#a1303c512fee9830f5d722d1a45e987fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4452", "a00260.html#aedb5ebd2cd1ed79961dd9d0111eb837b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4453", "a00260.html#a96eb5d3519f10886e6f30a179471556b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4454", "a00260.html#aecb63cddc6c4018dd853d91a94820368", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4455", "a00260.html#a6c63eb434f22230be746ae93a5cd7d34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4456", "a00260.html#a4a6ca7c3cefe5f6d41284b8fa0c2a0d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4457", "a00260.html#a011ab11e93efdacf8310133b62f9ef4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4458", "a00260.html#ac8b8ac89ac8fc9ff8c6feb33b0ab6449", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4459", "a00260.html#a329664bcbe86b89e96fc125584919587", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4460", "a00260.html#a7cadab0feb4866191c13c579e290b54b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4461", "a00260.html#a66398bbad84a70f725a9e5d24068e613", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4462", "a00260.html#ad5bbd29189f50f733be483d6a747bcd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4463", "a00260.html#a134f6b78dfd62a938d5379dd9007d5f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4464", "a00260.html#a2ef3e996b7bc2c1451d1f004b6f703b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4465", "a00260.html#a3126bcdb1c5cee84c0a8599b91574e0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4466", "a00260.html#ae70b15b6ec2f10f3b23c8fd262e98eac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4467", "a00260.html#a250997dca9e8e1818b30222a7f0db662", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4468", "a00260.html#a1b72c5dbb8395bafac6a93703ea97dc6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4469", "a00260.html#a7c22979996ef00a2c376d468b8978442", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4470", "a00260.html#a09b545b8a67b95aa242587e011a7da91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4471", "a00260.html#a0ac2b73314fb21652117f0c0c05259f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4472", "a00260.html#a92b9609bbd7b304bc8a2bf4519becafe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4473", "a00260.html#a5deac391e0d2797b96f174e092628a7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4474", "a00260.html#a0a7fa1f885c36b78bbfd1f496e7d7ff2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4475", "a00260.html#a86e13b9148c89bb3f0c47cb717577447", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4476", "a00260.html#abba4cac2ebb4abcacf65f33dfbf40537", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4477", "a00260.html#a8aa613f0e8ca80c11ab776255e84a941", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4478", "a00260.html#a76252364396e21dc4a13d814b5fcd178", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4479", "a00260.html#a7cf17c0a3daeda70a3800041f1d23465", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4480", "a00260.html#a3a095118f9804d643cf4a4d8e54f0b5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4481", "a00260.html#a465db64237418e19498d14fa53a8b878", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4482", "a00260.html#a92846ec399e8b4291ead7ec280ec2134", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4483", "a00260.html#a92c1586bc7c6aeb4aec2bdadd0313c7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4484", "a00260.html#a01e47e0a76ed4276c42813296c4c3fe9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4485", "a00260.html#ac2724e41d6fd58d712857a6a507eefa3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4486", "a00260.html#af895013809ad756d7c85e1c3a87c5e69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4487", "a00260.html#adea7db9522eea617d79d2ade96e498da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4488", "a00260.html#a3f7176ece1e7a41d9e4c18616b4b9836", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4489", "a00260.html#a8a0f649156e29d2dc8a40fafda57c59e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4490", "a00260.html#a5fdd1be576471f359d6f393e4e3b10f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4491", "a00260.html#a6fb5086ba5145a9ba89f319decf5cdbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4492", "a00260.html#a6eb7838d52c16118bd20417da0b8f6a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4493", "a00260.html#ad3ded9a98180f23acdfd4d0836322eaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4494", "a00260.html#a40863e5ded46e869dbf4fa1abb13dcc8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4495", "a00260.html#a4bb5206e4c76ac294d74dc7f9e331f5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4496", "a00260.html#ac56c8ea14e19993e411c2b7f5e46091e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4497", "a00260.html#a997c1379dc9d9fd89236320889d59c52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4498", "a00260.html#a391001da499d1f2833a013d03080f12c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4499", "a00260.html#afbeb92ee849f79f6279bcaf6cabb7f04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4500", "a00260.html#aa69ba9f6ac79b558dd5a841512941ff0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4501", "a00260.html#add4161bb0b28e7c2ef4223ebf5ff7eda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4502", "a00260.html#a36797bbdfecdad6f3281102be10db9c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4503", "a00260.html#a9d04dfb3df8cdfbbd22f4a6929bc10e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4504", "a00260.html#a23c42e1d716078a209279e219b17a46b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4505", "a00260.html#a8ecbe7d076787dc252e9906c1212a6e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4506", "a00260.html#a2b781b1f3c7445c53698b55ab4a59a83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4507", "a00260.html#a0727f12a6df7a00c6490111047526033", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4508", "a00260.html#a0cfd883760f2e939c606128d993da975", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4509", "a00260.html#ac3c3f3d2096afce5dd4c2fcb1b94e823", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4510", "a00260.html#a27377ea69a6140f2ab76b09323077b55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4511", "a00260.html#adaf9599468ad762621c634c69be9dcc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4512", "a00260.html#a10b218da52fe7c3e8c297b1329c567c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4513", "a00260.html#a1226302fcd25406ddcad4532f083e765", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4514", "a00260.html#aac522a09d94752d7c7c322d5fc5adb4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4515", "a00260.html#a7cd48bb1d21ee88537a14ea38212b947", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4516", "a00260.html#a991e826854b09a3c15d58151430a2c95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4517", "a00260.html#a3608ab73b75bda0e2632fa6a45d80bdc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4518", "a00260.html#ab78bcc260d918e0e9332d96d0b2e2c3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4519", "a00260.html#a14b003c5483fa1576bfb47300dfb3b92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4520", "a00260.html#ac89ef958f3321adee3f2f38a1e807188", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4521", "a00260.html#a84ddeae88d5914f507ae399077442e6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4522", "a00260.html#a78e6de265ad432f6dd8f51415a6c7a47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4523", "a00260.html#a9988b45c9f3d57c0c56cdaa947eca2f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4524", "a00260.html#a931b2b2385c415cbaa2131b68b8fb2cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4525", "a00260.html#a5ddd1eb72971633fcf107e58a1fa9af4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4526", "a00260.html#aa72e1cd2fb3e7f26040e43a1a89835b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4527", "a00260.html#aaec4ddd9c2cf97d794ebe55f9b7df982", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4528", "a00260.html#ab66d63875ceedcd4269c54fa0c27c97c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4529", "a00260.html#ab121c4de8f1ce985bebdb18e033fc98b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4530", "a00260.html#a8b923d4c75b2b891a5acf722ed3e9f6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4531", "a00260.html#a9805e57fe59eae01c2bc9e0f0d2677e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4532", "a00260.html#ade248896a140a178ae316a828a30c2f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4533", "a00260.html#a774a5d69f7b92cb4c3aa4aa202cc725c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4534", "a00260.html#afea30180af3419619088401c88945eae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4535", "a00260.html#a513f3a65aca43e3548df43a5aa5adbee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4536", "a00260.html#a8f423459dcf25d2e0cdffa0cef8f6d33", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4537", "a00260.html#a49ac0df87a0be50e4585ec8dcef89934", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4538", "a00260.html#ad54090fc36c375661536938572fc2a3e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4539", "a00260.html#a90026d1bad9d809f60b692ab59f3998b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4540", "a00260.html#a37f807f77c42fd8cc3d48ac9afd159db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4541", "a00260.html#ae5529a9f82d811d0bc17781815e07419", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4542", "a00260.html#a2f437660dfc8895620fb146e31f92708", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4543", "a00260.html#a0ebafc7865d22e7287a8abcaffc9f7bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4544", "a00260.html#ab3359a27d3ed28ee36a38a4bf9ab0f3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4545", "a00260.html#a5a6f6c6ba57a3abf6e86ddce2e45ea69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4546", "a00260.html#ace324caa28d486c09c812721f57fc2d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4547", "a00260.html#a6e7e9bedeed34f2704904607b5718e8e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4548", "a00260.html#a76f6cf37c37a284ec1956cda5383b6de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4549", "a00260.html#af7d0b7e8383a5e39ab1ed222a710a1f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4550", "a00260.html#a6f9bd0b3432bc0112e5dcebb9a80a0d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4551", "a00260.html#a1ba3181a9433661a0480d4fbfbdd5e0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4552", "a00260.html#ad71a906646ebfc6d55a84615f9619d28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4553", "a00260.html#ae19626e089f05c6b951948956563b4f8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4554", "a00260.html#a6e62421d29b709f0fd4c317f4c1c2396", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4555", "a00260.html#ad2c790419251cf987df2d0558577ab05", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4556", "a00260.html#a0b883c9121484fac31a3c5f17c7a0104", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4557", "a00260.html#a4a8c189f1448efa42e9179af3ff19fb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4558", "a00260.html#a8cb539a9301d9635fca48ed2ce6149c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4559", "a00260.html#a13f383b8a164c31d168434ecce7c0032", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4560", "a00260.html#aac2a4bb6e080bf9c4b67d02e6d8c7c10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4561", "a00260.html#a7e15f1980cd0bdfd8d163ac4fa88136b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4562", "a00260.html#aa6bef9e2591ffdf6da15c940b165b5d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4563", "a00260.html#ac633210b0e14a590b8121c24bbea26ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4564", "a00260.html#a066d7b82405a1252f9c90b78bbd8dd74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4565", "a00260.html#a96234126a96949b977ca192163b2beeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4566", "a00260.html#a5110d1b853840061182c4f2d77bee9eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4567", "a00260.html#a4630be721c4e2b1b916c20b7daad9448", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4568", "a00260.html#abe89672932b1551aa61723fab07a64c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4569", "a00260.html#a1b5c7c674b6591ee924972eed6350711", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4570", "a00260.html#a47e14681e09235396d92d8988e930296", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4571", "a00260.html#aff41cc2e14f42701fdb030d62ba39a57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4572", "a00260.html#a5a091d3ce160720d7bf32f746d82e9a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4573", "a00260.html#ad0eac064422611458a4313cf468970dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4574", "a00260.html#ab73f78da529f4a3168e268e0008527c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4575", "a00260.html#a79b7193e49950ed7cf2e6378e7af420e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4576", "a00260.html#ac503651859ec84e919b07901be532528", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4577", "a00260.html#a421d79d23436d92a7844546ddf7e6ba6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4578", "a00260.html#a9e6b0f725acb2e658512514c9e7b2be8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4579", "a00260.html#aff227a431d87a1b20f844305c8dc67c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4580", "a00260.html#a4cb66bece525c5d1d6aa695f7734ac45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4581", "a00260.html#a202606567ae50e42590737e5f4b21945", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4582", "a00260.html#af637a8c06f546ca902418fb8ea613a02", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4583", "a00260.html#ab414be9a484002d4f045d6ab95b29fe1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4584", "a00260.html#a8049ea4085015b1ec87725783d740414", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4585", "a00260.html#a7de1559794381f2494e4fe6db68bedee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4586", "a00260.html#a1016e21832647ceee95f5c941ba977d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4587", "a00260.html#a6dc8e02235d15128cbedef0057efe521", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4588", "a00260.html#a41ab52cbfc6af8a5944f29b504c8218c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4589", "a00260.html#aba044dd909318da038f046cdc40b943e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4590", "a00260.html#ae055fe8b81ea0f9e9e1335f20230eb38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4591", "a00260.html#aae92f6befd7c2cb90477079ceda79e22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4592", "a00260.html#a9977d71cd936e3edf7a926bc84372f12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4593", "a00260.html#a8681ab8eff57ebb4f2bbb88ea3190a57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4594", "a00260.html#a81dbdec8a7af1f55d1a2bacff7dccc13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4595", "a00260.html#ab6c169067be5e1b31ae545c5ddf28c7d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4596", "a00260.html#af9803d0dadcb766d5c00fa84a31522bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4597", "a00260.html#a64b864a9e6247750946da7ffd6637d6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4598", "a00260.html#ae49a1d2fafb4de41809bfef1dab95d96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4599", "a00260.html#a8ac1b763631cdc76b03a86a20767ba7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4600", "a00260.html#ad732ec8c205d98ec17f1a18b3a43c23d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4601", "a00260.html#a44bd8e08e7c4269ec581881c8f91c796", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4602", "a00260.html#a62f64ba13b767a8baeb48dfad48a6deb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4603", "a00260.html#abd4e525222a944f7ba37c70fcf7350b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4604", "a00260.html#a9477ec4b90a165bb065eb4169697e39c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4605", "a00260.html#ae99f9830546af90993a3ab7c0c19260b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4606", "a00260.html#a7cbef1e9058f59ae40b54cc07a73b939", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4607", "a00260.html#aff169ef8a2713c0f28565d3909731501", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4608", "a00260.html#a0fe3b6cc26e546e1f7021348d6f3c430", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4609", "a00260.html#ab03f13eaaffa8bc0ecb4a455919f8139", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4610", "a00260.html#afb83a7b9482e27332bacd479153d6035", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4611", "a00260.html#aca2539e509ad4a72dd6b561721620883", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4612", "a00260.html#a3e378a45e3fa7c9d5a613ce46be070fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4613", "a00260.html#acc05a086cbefee8cda64e0a91ee1380f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4614", "a00260.html#ae4c5d5791f286b6936f0547f844241db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4615", "a00260.html#a57239a87ccf8fb566601e746ec6bd4c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4616", "a00260.html#aa68e3120b67a989b2c432b5d23fbbe3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4617", "a00260.html#af12189f7e211fa49dd619cddf2874e62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4618", "a00260.html#aa2a629ada55bf658fa1df7627168530c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4619", "a00260.html#af4ed39125c9ef020f63621b2efa9d600", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4620", "a00260.html#a1c9a263810cd323cc6970814b0e231c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4621", "a00260.html#ab60150bc12fa3c93b1162fd8419ba1a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4622", "a00260.html#a4dad622dc0452ff72b7113a56c7b4697", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4623", "a00260.html#ad2dfecd768d5ed24accd05a3a006c704", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4624", "a00260.html#a953dfeb4b26accab6fdf93735da89131", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4625", "a00260.html#adec907e42689984e84ad608488966c4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4626", "a00260.html#a2827336b4d2a543f3aa43852bc2cf218", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4627", "a00260.html#af42e1dba91525eda055d53e81681c721", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4628", "a00260.html#a98012129dbd9b3fecf24ea608305771f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4629", "a00260.html#a5dc0895d5b76b70ac0e7bd29b9a92c28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4630", "a00260.html#a3e780043cbfe24298c5a150b8e03a10b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4631", "a00260.html#aaa010adf72004e8c5043b5bbd2c89933", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4632", "a00260.html#abb8c1d9411fbfeae962ff9f43a2d42aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4633", "a00260.html#a2b9a4b33624af64bdccb0e9301c0a424", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4634", "a00260.html#a47f3efbcc2c2277ea578dc461d7724bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4635", "a00260.html#a1e639f447b919b76920f1ec46f2ea81b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4636", "a00260.html#a7679ae442f477598de5b5143847edf20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4637", "a00260.html#a0b6780c46632cb090859a8613cf37192", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4638", "a00260.html#aacbb78233c98ea9c8876b1fefa23b934", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4639", "a00260.html#af3fc631c38af5909e63eef1f39c8040c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4640", "a00260.html#a050ee4d3aff2dedab8f4800e09d86d22", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4641", "a00260.html#a8ecea86c10b280da9453de3167e905c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4642", "a00260.html#a8a96dcbfc121586398e2388e62572442", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4643", "a00260.html#aa99a8c354b8089152a741adfb2cc46cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4644", "a00260.html#ac4207e6b616b40a3d3439e106a42efcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4645", "a00260.html#a5b4b1ed4b3b9c68761fd89a592f8fd60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4646", "a00260.html#a789e18f62560494807f890d49af0fe7b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4647", "a00260.html#a27fd1b0a71cd8023383ecd69434ceb1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4648", "a00260.html#a2d8483a07d5e8697f1bc634d4eab007e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4649", "a00260.html#aafc1f7b97011e0c1f7e3a7dcf48c2877", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4650", "a00260.html#a4aefebc21e51ea72d616e6429900930d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4651", "a00260.html#af034561d4b5d76b90529667ff142074d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4652", "a00260.html#affe9bec6b135cf5e1758ffb9f546d3de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4653", "a00260.html#a79352aceb16be058fdf04fe4261dedaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4654", "a00260.html#a882248ca7ee842e31b410514972dbdc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4655", "a00260.html#a80b96ede27ba9f426235e54b616e63e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4656", "a00260.html#abe1c0dd65104a410bca66f911eb8927e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4657", "a00260.html#a3f032de5fac8f4f968400e7b68df8c42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4658", "a00260.html#a57982fa612a9383228a50e650a880e2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4659", "a00260.html#a4c65ab9dbd9e1d3630466f3e4869cd70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4660", "a00260.html#adac9d03742e455792e2775fa009bd3dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4661", "a00260.html#a723373d48cde3e72ec5f8a3da8033e6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4662", "a00260.html#a8c4610508428f17c057589e958f0e703", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4663", "a00260.html#a093fff655bb2b665fd2c591eb4770bf8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4664", "a00260.html#aacd2348ffe2c2b57d4a81f4329fdb347", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4665", "a00260.html#ae1503291cbf2fbea560506c500358a03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4666", "a00260.html#a1a4770888611d1cdb7d2257fc6942ebc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4667", "a00260.html#adc0c935df3f1d6744049b416dea6aae2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4668", "a00260.html#a3e93ab3df76fd7d11d66f8e91b68dded", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4669", "a00260.html#ae2c835250c5f3a8bba7a6a4bd09f0c65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4670", "a00260.html#a71bcd667d3cc8cf31cb249a9c7ec3040", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4671", "a00260.html#a87ce17e2dc624c84b180256e0322816b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4672", "a00260.html#a773e9849274587ca681e42731f58b4ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4673", "a00260.html#a057bb63911143dfe47ce00cdab8d94c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4674", "a00260.html#a7a5cb39aa21cf57dba097a4f84614ce3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4675", "a00260.html#a4e27d95f47ece1fe392c2c78f06caa59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4676", "a00260.html#a4476f190a133d2cfadd6c57b963f71c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4677", "a00260.html#abf89104fa6cd3e3225be1b4d09ebda7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4678", "a00260.html#abd8e25794132644341e1f9551cc53ba3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4679", "a00260.html#a440584a15bb6fca83175e41157bce770", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4680", "a00260.html#ae6657eecd81afe98bd75a542f537f1c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4681", "a00260.html#a77747f8b73918e6a1d5ccd60cd859006", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4682", "a00260.html#ac4dd33b80ec5d082d5421e1f30c365b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4683", "a00260.html#a8759c97b8e3706d2bfe6882e329ded92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4684", "a00260.html#ac4e79baf3963b605810002862cdf5f40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4685", "a00260.html#a4b48a13bb9e9ae7c7f068bf1df90f413", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4686", "a00260.html#a03cf334e83dfc5da2f39e5375463542b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4687", "a00260.html#affaf0419f5238571201683ef3f690bcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4688", "a00260.html#adf5bf8198245abfc22be286e57b6a20f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4689", "a00260.html#a63b1fe54e4894d3a0f5d7fbaa6842ac2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4690", "a00260.html#a9f1c0c011fab5374f7ba24b4a5409b96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4691", "a00260.html#a18aaea1f0415b92ad71b7ae5888b6af4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4692", "a00260.html#a279bbdd4d75e1e22f7f029008e609409", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4693", "a00260.html#a4640acb3204de75648031bb26a50f47c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4694", "a00260.html#a14759b275ea4e03481be3d73828eb41a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4695", "a00260.html#a8ee2b72297f01ed1b18e55e60448405a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4696", "a00260.html#a736a46d3cde58ffcb59a58ef459e4514", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4697", "a00260.html#ae8c51fc8ca267813ac93ebb6faa6b3e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4698", "a00260.html#a3a6624c15ff9aabe7dcb9385c6fe9deb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4699", "a00260.html#ae2eaaeb7cf6ac6a345e3c5fa2ab8a3fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4700", "a00260.html#a75098fef55253d1424d7196121a371bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4701", "a00260.html#a313d81a215f7168c15c554165b120e60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4702", "a00260.html#a2a9b1f5cee84a386d648d515b270f4fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4703", "a00260.html#a369ea5e260a8ee8da078b3c62a1ed4de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4704", "a00260.html#aea695df5b040331d3df987e6092aa1a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4705", "a00260.html#a75739d7e1b3f4bfb6676766a4b6933e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4706", "a00260.html#ae452aea62e72c6531737fa003b26f570", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4707", "a00260.html#ac4dbcea4fa8765fad7fde9078adc1dcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4708", "a00260.html#a4cc8429e5ec70e35099150a4896617cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4709", "a00260.html#a807c539f9e0cf26ed15b90d4ab9080f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4710", "a00260.html#a3fceabbbfd3af0433e28605fab3b56e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4711", "a00260.html#aadca20d2d912913cd4288e19c7808a51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4712", "a00260.html#a1b6990329a2bb2388ef3502d3ab28ada", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4713", "a00260.html#a1f2dbcc467a45c06c3e6fdc2850b7635", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4714", "a00260.html#aacdd4f487247b028d1dafba8afb37fbc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4715", "a00260.html#a7342646456abb65b57c2c4ad1e9b4662", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4716", "a00260.html#ae4225f6551f702292820b10f3dc2c145", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4717", "a00260.html#a64efe77716b7b069f92604090a534010", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4718", "a00260.html#af85c1e051c72524504a21025064b25bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4719", "a00260.html#a21fc9e7aa5a71ab99c406375e6b0c954", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4720", "a00260.html#a8f683658e47c293f8d4c09ebdabaee94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4721", "a00260.html#a5d1275cb857f1a3ef8f2794eab435305", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4722", "a00260.html#ab6ead6e2d9a3e49fddd09bcc25ac20cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4723", "a00260.html#af1d4e4596b012a675fc15b35bd202e54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4724", "a00260.html#a34b286e32f58a3933dbe284d574d766c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4725", "a00260.html#a55ca4bc1613480b793e9e95a8e1da71c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4726", "a00260.html#ad62a41fabccffdcb58ba8c0c7c3fcd62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4727", "a00260.html#a044026730e53a6be71bc9940fcfd00a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4728", "a00260.html#a85d07825f8144aa919739e7385c04577", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4729", "a00260.html#a3072b18090b11200af39161624dc4907", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4730", "a00260.html#a9be11ba496781fa70af296caa2a3873a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4731", "a00260.html#a1fc022261af692e749f3b2e4e2110760", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4732", "a00260.html#abfed757d09c21d0014b4f2509565047e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4733", "a00260.html#af496cfb67c1e8c3de7a2a02a23a9e53b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4734", "a00260.html#a33c1fe4c9c77ef146965405361997a91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4735", "a00260.html#a43b77c1d7938386e92bca352d8e82578", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4736", "a00260.html#ae88d0cb4f30e7df3c53abb3fda46d36a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4737", "a00260.html#a99b8e0143ff6e6ad4d4a6c594a0d4c6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4738", "a00260.html#a9b95e7be89be88f1527e36e8a2e39f1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4739", "a00260.html#a4d0a02e2a102b824f643dc780bf18c42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4740", "a00260.html#aafa11b0143cdd0fd594f4b2df7eabd39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4741", "a00260.html#a4fc4ff441be5a6666bf4d7db63439e53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4742", "a00260.html#aef50aab025c3a7167cb6d76c17b0b567", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4743", "a00260.html#a7078b348119433873dc7f9c7b95bd21c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4744", "a00260.html#a178362e96cb250e6b6217d3a14984c61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4745", "a00260.html#a4dfcf5482031cd678a12a404dabb1328", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4746", "a00260.html#a0a77a4341eb51b25cd39e657a7dbfcc6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4747", "a00260.html#a36ac8f0bbfc11489ffea72d674c73731", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4748", "a00260.html#ac3dcdcbbfd342b5c031c3d05c6463a38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4749", "a00260.html#adf18ca7551cb2da24b8d9f94cf2601de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4750", "a00260.html#a2415f8609fe789d0571adc7d477b032a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4751", "a00260.html#a9d19cba5df6d475bc45462d47328e7b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4752", "a00260.html#a6fa9473e859f91408061d0d57f73bbe1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4753", "a00260.html#acb25972f4025cd8ede86c0527cc30982", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4754", "a00260.html#a79686a4b481bdc8d699e35359f7a0600", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4755", "a00260.html#a1b1a55d9974c46a8dd647035049bf28e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4756", "a00260.html#abf78202ab3aafd89d7443fb31a7f4a23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4757", "a00260.html#ab948fc5cdf0fa57fbef3db24bb3054a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4758", "a00260.html#aa7165941dde867d26e9551a9b32d5659", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4759", "a00260.html#aa61ded80b5b56201185d326b04bb5b0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4760", "a00260.html#a6394b36f5a0e3d0d10bbcb139bbc0aa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4761", "a00260.html#ac91c02d1794d2b23a8d2e3c017e06bc1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4762", "a00260.html#af6171a93e12e243714ea80fd3e71acf6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4763", "a00260.html#a0ff6e8ae303b1d1d9b38a9b8fa9cc127", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4764", "a00260.html#a0252aac11437406aaef7b8522d6826a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4765", "a00260.html#ae05faec41758b1000c7f805b71dfb97e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4766", "a00260.html#a00ba7a46af79a95b4c8f5b85d41b357b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4767", "a00260.html#ae8cfbc09860ff8e96dd5a56a30274eef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4768", "a00260.html#ac6066822d8166135b05d50972653b1ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4769", "a00260.html#abe584b8c7a41a61337a6c6cd722c0143", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4770", "a00260.html#aa22829b3e273b781a8e925819c9f6d00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4771", "a00260.html#a9967edf7d9bd09175230fb2cf0840e19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4772", "a00260.html#a4f649af829251fbc1a53de82d4ce5d0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4773", "a00260.html#a92d260b784ba56d9a10d7257ba8770f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4774", "a00260.html#a351b5a6f88acd84a678538648f2b2bff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4775", "a00260.html#aabe9d95554157a280ba0a04c198e94ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4776", "a00260.html#a63bd8baed532c9080c93851710ec5f2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4777", "a00260.html#aa24fb114d64809c9edbcb45514f13320", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4778", "a00260.html#a4353182db072d1b9ec1d3edb0f741772", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4779", "a00260.html#a4953cfe4e91c48bd591193fa561408ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4780", "a00260.html#a2581a65957422722fbd89040d86dc633", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4781", "a00260.html#a5595a2d84811cbe9d5af65249c11ac60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4782", "a00260.html#a66a02aac60944a2581e10506ec6a38f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4783", "a00260.html#a1c1b377101c81a123af49bfb19dccae7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4784", "a00260.html#ae1b2553e814053dc5f40050a89326e91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4785", "a00260.html#a60c1f8920b4f429522ca22a2fc89f148", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4786", "a00260.html#acbfb14353f6ecef0528478efa9bd67fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4787", "a00260.html#a247c991ac3c07703816536587e10cf98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4788", "a00260.html#ad6532e3a6e30fc6e56b31d0898aa89f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4789", "a00260.html#aba9df7ff5f9f1df653204f30c93918b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4790", "a00260.html#a0552921589b7085e1b66bdec010f6839", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4791", "a00260.html#a21e48619e994038c0d0314f31fc44214", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4792", "a00260.html#ae89a595230c319407f6330b45a7cc8c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4793", "a00260.html#a20960dd73a1943a1fba06b55825b41e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4794", "a00260.html#ad5a53bf1f25f202c9ef8106e1a28492c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4795", "a00260.html#abac9d170c8a2ea281d7c1c63350c305d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4796", "a00260.html#a8d0929c8af531682355a7df30e1219c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4797", "a00260.html#a098fc9a55353abcab184ac52050d0c37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4798", "a00260.html#a77ec22493f445e19ce09c7d7fb035017", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4799", "a00260.html#ace978b7b5056601976c8f2d05e06773a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4800", "a00260.html#a6994e221b626f05adca65af2184f22ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4801", "a00260.html#a2dd7ff4b6103ced2d837dca45edc47be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4802", "a00260.html#a85ce0c52ec421365db3de9481fd1b1a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4803", "a00260.html#adf48c74fc8db3ec7718cb5094a476f95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4804", "a00260.html#af9738b7cd9b27e743829126aeff232ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4805", "a00260.html#a80d9e44c59f1eeddeb06448efeeef3ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4806", "a00260.html#ae0153ae28a81d81c2e4b81de85abda9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4807", "a00260.html#a105435e97253f45067e630746f825ffc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4808", "a00260.html#a6d4ba81f4d65eac24e184298c0f2707f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4809", "a00260.html#a19d01ec460febf7d435724773ff887a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4810", "a00260.html#ae9aff85fcb0d828749b297fbb7244d9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4811", "a00260.html#aa8f65941845fd2dc0b876063448635a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4812", "a00260.html#adcd40c4afa28346c67af4b77fd931c36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4813", "a00260.html#a946ffe61bad232c023237f901651b17c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4814", "a00260.html#a5e786db97d4660caea1a3530a3a18f09", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4815", "a00260.html#ab4aece40d40e3e5959cee869c32301c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4816", "a00260.html#aa5d32ec1ada5d05e8fea4fde5e42ccfa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4817", "a00260.html#acf99c46eb65cc28aafb7bdccfdd9072e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4818", "a00260.html#ab814c618c7600cce6d98f85c4541381c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4819", "a00260.html#afddf09e20c259ac5acfb10fa995b44dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4820", "a00260.html#ae325dcd8f7546de41c755493adc4f327", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4821", "a00260.html#a1fbe95ff7c8f8cec698a528ff5d8a97b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4822", "a00260.html#abcecc2fac15b73aef29f42d95b2312cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4823", "a00260.html#a91641e42ef6bb1c5c6e12516dc3887d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4824", "a00260.html#a40d9fa295094e850a23297a792782244", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4825", "a00260.html#a6e58cefe6bb6ba14cdc3b2d2784228e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4826", "a00260.html#a6cc4de51b5e58a4fdbefba1f41aa9ac2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4827", "a00260.html#a3a33ada7b0ea58bdd974707f90182608", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4828", "a00260.html#a7a7f28297fc7ffd26e61f2c90e0787b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4829", "a00260.html#aa55c1d7a21aa2aebe1eea685854545a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4830", "a00260.html#ae6d89002d213eb5eda166cfde3f2fab4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4831", "a00260.html#af0bee9396d29027b74d67f0154b9cd55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4832", "a00260.html#a294332afc6a73e984e137c4d8a8c6e58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4833", "a00260.html#acaa15460e7c214454a8a223429a798a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4834", "a00260.html#ad9d6c79d1eac30594ca418138d7877d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4835", "a00260.html#a88cfb8e20fda18f8485b74684fa40ae6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4836", "a00260.html#a4f5f0c541719571251a98c08c8c00976", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4837", "a00260.html#a8c7a70d2c5dcb021ab634bd51e0e910d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4838", "a00260.html#a78b31b7a44afb7a9ec12cac96733f9f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4839", "a00260.html#a046d88a0c3ae4a782538651fedbc8201", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4840", "a00260.html#a4b367bf2548f7ee66fb6d347f509e5f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4841", "a00260.html#ac827afd0e85a5313bf578fabc75fe65e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4842", "a00260.html#a6a6f09eec1cd598ad43f09f55152d3da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4843", "a00260.html#aa99dcd083109c17a374b8c54600783e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4844", "a00260.html#a91d2e799ae05699230ba1f4db91087b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4845", "a00260.html#a3b540b27b40dca87292426ed7842d033", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4846", "a00260.html#ab995a5ffe028f79e1e8fda0578cdfd38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4847", "a00260.html#a3991dbbec6cdc02c3cd7e87d20bba98e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4848", "a00260.html#ac3bc5a7ab5007cfc8ddba5f4c1c1e6c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4849", "a00260.html#a6cf8616e898957e4d8a7193bc7a5f3a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4850", "a00260.html#a21b04153bdc5cbf6d70d3c6c01c9d6c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4851", "a00260.html#aa676a2fff03c87de1042117cacb9a31f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4852", "a00260.html#aedeeb5928c24bdd23f8f48ee19b22f37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4853", "a00260.html#adb4deac97718295472ced6c7ed36182f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4854", "a00260.html#ad421fa26680321307da514076624599b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4855", "a00260.html#aca056c14eb87c0698642c831408b4a8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4856", "a00260.html#a10000e096ab9efef8d7276a4f6019b34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4857", "a00260.html#a65ca10d446833e94f2916d0a1ff9018c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4858", "a00260.html#a8fe1016564d0d2dfa6e5c344b8980c43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4859", "a00260.html#a9bec35c9e6ef4689e31f560666fa110d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4860", "a00260.html#ac17fe1498681c26fcbc8c1e685b8e08d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4861", "a00260.html#a38dca21717913ac7933de5326622a7c5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4862", "a00260.html#ac88a737da4f00a2904d42d6792416c42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4863", "a00260.html#abb19b916976911ac320f090779af4e8d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4864", "a00260.html#a9f2f618b85205f32d5848c4a053c1bc0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4865", "a00260.html#a4a8fa9782f7ed4ad50e13997adb50e83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4866", "a00260.html#a38b2fc450b4bba81ca3a9e67e2979ece", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4867", "a00260.html#a02a17aedacdef13a7ede05adc9c6dde3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4868", "a00260.html#a6867600207b245097509332882607e53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4869", "a00260.html#ab27b7aa7282ae915dd8262ef1b88ab78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4870", "a00260.html#a6cdb7231ba8e87279bbe415ccd9f6ae1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4871", "a00260.html#a0eeb3e8bfb2ac823597e122dd9000885", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4872", "a00260.html#aef92af1cf8c91b0026c0c2cf887fa007", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4873", "a00260.html#a8ad25e6eb092b91e53508e5866307c44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4874", "a00260.html#ae01437f631c9a5c5398b90e71c78090e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4875", "a00260.html#a45c4b6067da29dbd2684f04c5297007f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4876", "a00260.html#ac9d1b80200faa02430e53e7913751d7c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4877", "a00260.html#a82b104a7b89f9304d1a8023d00fc46bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4878", "a00260.html#aa04348d0aaa03d234415b4895c86e25a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4879", "a00260.html#a3c2819144a0f2e28315806da51b63d31", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4880", "a00260.html#ad6b8448b374956d757bddb67863aaba3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4881", "a00260.html#a1270995f213bc92c49e7f9a2a76c6124", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4882", "a00260.html#a4dbb921e97a2e863fc6cc77cd11fab78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4883", "a00260.html#a7bea760371b100e6ff4b4fe63eab3bb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4884", "a00260.html#a41c74ac0aa6ee0ffb693a4013378b314", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4885", "a00260.html#a393ab72e663346f968cc0d940bba4e64", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4886", "a00260.html#aba0b4b108b257b0c62620d508464f626", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4887", "a00260.html#a0afd7456449e002104473f92fd732d85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4888", "a00260.html#a233479cb6a137e7076299c9d78a62d2f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4889", "a00260.html#a8a302d7e61baa5f455fcd00ce2912cd8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4890", "a00260.html#acfbe032ea243fde532c394bd19f5fffd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4891", "a00260.html#af8d81365de6aeb3ea4894c17d679a88d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4892", "a00260.html#ad6d0a976de258b4bd3e19dcd72628d59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4893", "a00260.html#a16d820be0a06ce9b33e530a2dea3bd94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4894", "a00260.html#ac5214b0f14faee0b4fac14a29e397c10", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4895", "a00260.html#aa0b49a29c1681f9c6e3f57ffba82f99a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4896", "a00260.html#a891a22131e968e90f651d0a767083b90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4897", "a00260.html#a80222d5ec5a86b6951f9c6c3c8b1a9ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4898", "a00260.html#a3e94cc2ed2594fcafe1e6eb09c347c40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4899", "a00260.html#a662654ffc9140fbc5ba94b63ecc9b5a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4900", "a00260.html#aa67ec092a20c90833a4283f17c793caa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4901", "a00260.html#a4abbc5f8b21b64a3d2209eae7d4555fc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4902", "a00260.html#a2cb05402c10cb3b427617e770da596da", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4903", "a00260.html#afe3011def7c81c42f5f4cbeaf7c04f84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4904", "a00260.html#afcad8aa6fc94bc7cbd3e46b8c525bf78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4905", "a00260.html#a895f5c7b0bdfa52bf93ef84f2f4a128e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4906", "a00260.html#a47571c8821b0fbf57e01c8fd14dc69e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4907", "a00260.html#a2393421b5864d4a92ab43aa5e4d827d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4908", "a00260.html#a3d55bfc45ce29357acd77d1e42327959", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4909", "a00260.html#a29693f19030e43d5166bbc0f099e5d5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4910", "a00260.html#ac8f3b2b9222b7cbcb51ccee364a2e36d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4911", "a00260.html#a9aa500590d6677d04166f8bdb53e714b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4912", "a00260.html#a662295e3fc8277625ef30e9346090d28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4913", "a00260.html#ac9f41e13f85c026b45cad2ba481e89d6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4914", "a00260.html#a8fcd4626219e0143dcd3a35327bef255", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4915", "a00260.html#a4c68b5892e442129619b7f1843168b0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4916", "a00260.html#adba22d42b732df695d10420b1b4128b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4917", "a00260.html#a4f5ab9b8ba1a5d68568ca7e76c7e6ef9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4918", "a00260.html#ae727ae14542dc6e1fd42f3c85f1ca0b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4919", "a00260.html#a4ae23251ce866cf1f3691dd0fcbe23fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4920", "a00260.html#af3c0f110f4efce0bfc50d54224631876", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4921", "a00260.html#a81cd4a58c5e0401e7e94e67753a76181", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4922", "a00260.html#a32fd0c5b7704d41199827df4b1b6b609", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4923", "a00260.html#acbd29ba842d6301a8b8b0c2cc4b494eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4924", "a00260.html#a38d9403c6ec444d8fb00976cedba0970", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4925", "a00260.html#a501a887a71b77471d354f938446d43c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4926", "a00260.html#aa623720117866828b9ababf291047698", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4927", "a00260.html#ad35f2c0a687a9e0f6b35a11a25a7d89a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4928", "a00260.html#a817ad74d4442787b44ac6230c4ed8622", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4929", "a00260.html#aa63cacba382b9119c69d1de37747b379", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4930", "a00260.html#a758ff3decca3e950d5447b44856a5672", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4931", "a00260.html#a1201e32a9b4dd5776691c9daa1e2e2b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4932", "a00260.html#ae43c676635aacdbd34d9b86ade0db6db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4933", "a00260.html#a3533571025c2be0557d07ed3ca7f9aff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4934", "a00260.html#a0c2f62b1ee9ffa224c6c8b6dcad62814", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4935", "a00260.html#a4e5c904240e7c37522153592fd71d702", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4936", "a00260.html#a2c91e7d17e67f394b4ae5ff03fca73e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4937", "a00260.html#a53dfd2d013ac24e0fcc432e43fb977c2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4938", "a00260.html#a32c935cbcdc33fb312a2f85e38ae0415", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4939", "a00260.html#ac265c6ced3ac13233ce3e8c0e327848d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4940", "a00260.html#a5cdf331d782e366a2b1376b83aa93a07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4941", "a00260.html#a46de9615241979ba03b4e12bd780275a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4942", "a00260.html#a8743e3545ccfbf192d3d6f75884d1806", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4943", "a00260.html#acb203cf0a57cf219d67d80da90a385bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4944", "a00260.html#a534a34febad02052aeb69a067b0f8a08", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4945", "a00260.html#a991376be846059c53446267a9a4448ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4946", "a00260.html#aa729a687aa4cacbaf8e636f41494bca2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4947", "a00260.html#ad019624ad1af9164031abbcdf296ba5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4948", "a00260.html#a3551de6e85e44c94b36cc4119717a992", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4949", "a00260.html#a1664553ab04a446f2ddc1dbd4abe2d29", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4950", "a00260.html#a0e16ab3cc729155a8fc74e40552ad1fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4951", "a00260.html#a850afc179d91272b4fd3cbc7c403fe90", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4952", "a00260.html#ab7238a372ad315ff08adfa2756cb4bc8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4953", "a00260.html#a2ef187fb51cbb4507e77b26ff003b403", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4954", "a00260.html#a7bbb705218ab4b6d5d30c5e063f0f70d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4955", "a00260.html#a481e319dd922a853738fa0b0253a5664", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4956", "a00260.html#a0f40ca5c02fc971e8f8fd4a222b7fde3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4957", "a00260.html#ad4257f76ae2f3af4fecff3fe61ab4ba8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4958", "a00260.html#a7ee6b6d7c3c7445d76bfb9e2d1f34a17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4959", "a00260.html#a7d07e3a9c3bb4b57d4f773ac55ef9469", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4960", "a00260.html#a7ad3174978e04af2851e1cdb83a9a026", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4961", "a00260.html#a8bf80bb4136ff0fea274cb04832cd887", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4962", "a00260.html#a271ef9edf88fb11ae5e06b825e622cb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4963", "a00260.html#a6dd6abcee4f3c630b302aa52e4c27c67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4964", "a00260.html#a4599bd2a829c400533acbb96451effd5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4965", "a00260.html#a6db936e5827255115be561db6c93abaa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4966", "a00260.html#afde4ddf6090d10823f5bd818a8576fb1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4967", "a00260.html#a72a4061c5a2cca60ded1c8b07b79d59b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4968", "a00260.html#aeab897f5a7b779541fc386ddba6d8120", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4969", "a00260.html#ac467643f044efba00da4757df37a5f8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4970", "a00260.html#a5d2190f47dd6ca0a8489dde90f6158c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4971", "a00260.html#a9dfe6ca9a015bc7417082e86ce9e34b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4972", "a00260.html#a5b10d74e06137dffabf8a8428d36b856", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4973", "a00260.html#aad8b54ac6678f3c3946d6e9e93cd20c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4974", "a00260.html#a42bf412a7f07340206fdffc40f61f9fb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4975", "a00260.html#a8993b17ac9acabea41a7719e71b51e6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4976", "a00260.html#a5aff0619e07a1526e7c495d6a15f00bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4977", "a00260.html#a26d6e36608594c82906d0276895520cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4978", "a00260.html#a8ca7e3b837e79174f40fbb85b990784c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4979", "a00260.html#a359215389fd85fed1a79c5f8d61bb345", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4980", "a00260.html#a355c3599e60330b366b3e542481d99ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4981", "a00260.html#a69b061faa2b792980137f105fb571508", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4982", "a00260.html#a053e475f17ba0c12af4d84e0daf70612", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4983", "a00260.html#aeddc62daf029ad91614dd0b8f3228f01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4984", "a00260.html#a2c7300fe6474268ac8cfda1e1bf5fb47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4985", "a00260.html#a5c7fd5d95bb04dbc14a4ff02b6243e9c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4986", "a00260.html#aee9c971c20c66bbddcc200df732a32c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4987", "a00260.html#a3d57a386a0d67fdd890a7c547e1b4c07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4988", "a00260.html#a8cc448cc54d87d0d363c4a43f6ef24f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4989", "a00260.html#a952467fc852ef0dd3b4958f4481b58fa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4990", "a00260.html#a5f148b2635b2b6ade62dc18bd0a92509", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4991", "a00260.html#a27698893d38a8b3742650e23f7810c83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4992", "a00260.html#aa47de9527ab83513250e499c1b006067", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4993", "a00260.html#a02954d14c39a12328263f7090d7efb38", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4994", "a00260.html#afd22057723cfefd08fc8cec149a4b9d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4995", "a00260.html#a8f5671739e61d214cbcd798ff039d7ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4996", "a00260.html#aeaafdd151ad10e98a014ff0ae0e27fb8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4997", "a00260.html#a500875a14c6b803693583e2d9e6c959e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4998", "a00260.html#a01b65cebccb158ad1d1b1556f8c1573a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4999", "a00260.html#ae832fb8b5f51e70d814d494f0e37cccc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5000", "a00260.html#acc26404d7fb42a65fe159161e0c2289e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5001", "a00260.html#a2f1eb504ecc1a7415879c1e8a17341af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5002", "a00260.html#adf0db24c2861aaa962038486b40ead37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5003", "a00260.html#a1a394c2296ca27dec7e5d70f05e96aa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5004", "a00260.html#afb1a26f047fcc559f1df81da5b4ecaad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5005", "a00260.html#a84d4f654d3458fcd071e1cdfea803537", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5006", "a00260.html#a3acd9d973e67329107bbca2077a32976", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5007", "a00260.html#aa929a46dc1243e59dd299da2365da075", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5008", "a00260.html#a03049131742862fb53c956e4ab54c1d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5009", "a00260.html#a6443744e5edba9b79458f742b1e1c2e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5010", "a00260.html#a0e27275174bd06b42f7102e9f06abb80", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5011", "a00260.html#af77aa2ad22f811bf4c5bc4f88e061ce8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5012", "a00260.html#a6a58a190fdfe0257909b6ebd79f017dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5013", "a00260.html#aa72bbb733edf4a22d13874802f3e4bf0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5014", "a00260.html#a033b97e496c57d1f246120b26b43c874", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5015", "a00260.html#a9e93bd8812a61a50a3832e9761f938e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5016", "a00260.html#a9fe9ffaa061c6852b57a2354d7bfd252", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5017", "a00260.html#a10017d7efc7621f2d0ac663c001dfdf7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5018", "a00260.html#ab78a6ca148100af595a22760edf37b01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5019", "a00260.html#a218ef73ceb60246c32fdb70436005c98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5020", "a00260.html#a59d340dd1d881726a298294664e41381", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5021", "a00260.html#a93c1d12304a719aaab0906dcc548491c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5022", "a00260.html#a914bd99ab70d332c0bf3f95415b74e67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5023", "a00260.html#a05e16cd32cf65225cdd237b0edd32c2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5024", "a00260.html#af912c6d35cffe41829a5793747961053", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5025", "a00260.html#a9b7e9cf6493c7da2f0503d19f2ae36e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5026", "a00260.html#a9961821d0e249be6399084b7460bf489", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5027", "a00260.html#ae2202133045a8d85dfc66292b50f0876", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5028", "a00260.html#a96d71387fb300afcc1634607b6130b13", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5029", "a00260.html#a2546c6343d1c227e1f4241b8f0f1cf47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5030", "a00260.html#a0555a3c4c3f76c527346e84b4e66e328", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5031", "a00260.html#adbd68eed2947cb0fe8986d731816b535", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5032", "a00260.html#a6881b47333ac211df29594b08ed7fd9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5033", "a00260.html#a1cb88ea8d97e909d20982ffa2a38e7b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5034", "a00260.html#a7328a2a37edea715d73d8f109f972134", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5035", "a00260.html#a094219733f40ca7944cd45ddc1b25997", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5036", "a00260.html#ae03ca3a29faa4ea293e43f6e998b4e28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5037", "a00260.html#a82a3d6bfd520c93540cf6bbbbf9635d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5038", "a00260.html#ab0ef9281ba80df8293ce4bc2fd72a61e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5039", "a00260.html#acdbfa935501dc3304590ccf0be20fc4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5040", "a00260.html#ab85fd343e340363c76b64b4016ae3931", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5041", "a00260.html#a9ea20d8478e2b679e6781e721bb3f1b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5042", "a00260.html#a86ebb277f7eab7febc40c1af686c85ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5043", "a00260.html#a304d011030edc40e01e275904cf99b73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5044", "a00260.html#a4579bef402dd52afcedfa50096277f92", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5045", "a00260.html#a5bf9595cad7cd1160d81fc6c98012434", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5046", "a00260.html#a957e6f0d4d9287730e154780081fa5fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5047", "a00260.html#ac8ff4b6bc079e17793cfe4873b682066", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5048", "a00260.html#a4e610b530aa444e2ee17cb73d8f1acf0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5049", "a00260.html#a891eccb213fb4c004ffbd5ea03db30c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5050", "a00260.html#a5fdf48a7d2cc9574576557c3c506f768", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5051", "a00260.html#a422ea6328731038ad999c7f1ee18c3b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5052", "a00260.html#a8699b13c9618203470fe899e6d2b0951", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5053", "a00260.html#abf6ea122348ef6db427ab817cd58241e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5054", "a00260.html#acb62c366f1f9326c3000a9a7e59721ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5055", "a00260.html#ad31ad432b76c85ea28eed74292870069", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5056", "a00260.html#a22aa8682202049024c929a94dd958ffc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5057", "a00260.html#a8be3ee7962965bd3f9e2584b834d54e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5058", "a00260.html#ab660a25099327e0c0ffa544e0757cd72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5059", "a00260.html#ae1ac99eaea8db370d1dd5475df493467", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5060", "a00260.html#ab955c74508033cdb33978bea1fbca453", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5061", "a00260.html#a36639418646845efbbba63fe88c013c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5062", "a00260.html#a7af8c76a7d740e7d868c974a3e178ac4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5063", "a00260.html#acbfa5d10c37bc2f4ea3756ace3fbad56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5064", "a00260.html#af37c68706d587d96cee1d99494cc84b1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5065", "a00260.html#af71b28a9eff614ed83990d713d9c2e59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5066", "a00260.html#a8499488f6c1dd7e7711b7e7fd24b0ce8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5067", "a00260.html#a6946f09878a820202a70a147866e469d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5068", "a00260.html#ac21d0e1efe0c7455e306db8958919400", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5069", "a00260.html#ac930e88e58392cb2c616a564513e40fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5070", "a00260.html#a1feb1a4c399f18f5ca463304e9c3d2b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5071", "a00260.html#a57331a5c40750e39ca04b488ac4ac507", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5072", "a00260.html#ae0b6be4c2cce053691f3106750dfae20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5073", "a00260.html#adb5cea44df09945c5ec597024ab63119", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5074", "a00260.html#a28e74a33af37bcc8eed3d2bc5ab0e439", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5075", "a00260.html#a936c9f0e485b9919b1d52c544d1c7af7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5076", "a00260.html#a4c0684a0aa52efeade1f3885e761be9f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5077", "a00260.html#af58321598c02017bdaf5ae969abade04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5078", "a00260.html#ae35d189725e8fb16d2c2ee12ad59c889", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5079", "a00260.html#a763a6e349ceb4110c2164ea4f021aaf7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5080", "a00260.html#a15d420a6075d34f7565f2656740ab8be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5081", "a00260.html#ae57a7c4e21c10314dc05097ec95918df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5082", "a00260.html#afbb1d52303cb42a9e370c5b192622f23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5083", "a00260.html#aa418272c650f58e799b4daf65c7f04cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5084", "a00260.html#a0d346870ec9c7f06d73453ee079f2e6f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5085", "a00260.html#a04bfdacc615951024baa04cd97fa25d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5086", "a00260.html#a3ceaa13f3994e49536275186b600ac21", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5087", "a00260.html#ab597279aa7c7253a8dcfa934627c898d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5088", "a00260.html#a6df5133ef527d79af78ea05b9bf40af5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5089", "a00260.html#a09cbb966cfb71b2cfdc1d9bc98a5383a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5090", "a00260.html#a8cf124143923b152fe0e80ede065a367", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5091", "a00260.html#a56098b32dc7a2e17fe8b31597ba3e857", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5092", "a00260.html#a1a45555cef42240ce44adb655d4dd97d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5093", "a00260.html#a292d7935d8b5feb76afe46985414b7c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5094", "a00260.html#ad124b132a6deaf3fadfb58103fecabe4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5095", "a00260.html#aa05448628662463abb147af42c5d36ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5096", "a00260.html#a3cec746091569148e4e50d78355e99a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5097", "a00260.html#abb4333bb01f3e65880a4a9adb16274c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5098", "a00260.html#ac5887586a74d8fec383cb38edf9bac40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5099", "a00260.html#a66c50e08556a4d6acdac895d9e6304bc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5100", "a00260.html#af097ff6ac042066ca1c6e47b14c0bceb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5101", "a00260.html#aa21b33b1fb6ff069707ea5f82b3cd868", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5102", "a00260.html#a9aad5be3936960f07aaaf3ea98cee979", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5103", "a00260.html#aa9409211439c10d22052f523d961f0ca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5104", "a00260.html#a74dea8529190ee0ca389d93ff44e7836", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5105", "a00260.html#a642adca31e0ddf2bfc31405ab096ccc4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5106", "a00260.html#aa340a9fc8c680368db46b878173df823", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5107", "a00260.html#abfe67914d3c6f58a64698af04462df3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5108", "a00260.html#a5e38a612abd4d9ce42d1a4ce6398bf6a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5109", "a00260.html#afe27e42e909531ad001bf6a5430ae669", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5110", "a00260.html#a26b7028222db5d2c9656f82c4b87a840", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5111", "a00260.html#ac04285cfe339efad774f4ec120267d15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5112", "a00260.html#a770d82ad476c4bca21f674301e993262", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5113", "a00260.html#a4ad56aed23cda52168e96821e749b645", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5114", "a00260.html#aa7172ad7cd01bc5d0f68c10a69373bc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5115", "a00260.html#a75abf5810bdcaab7068a4c82e515792c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5116", "a00260.html#a3fa491dcadb224fa31af2a3d8988e7af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5117", "a00260.html#a53423cf496d4e3c3e3b2ebd4414e226f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5118", "a00260.html#a9199e51907feaf880628a3c6281c01eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5119", "a00260.html#ab59d0e9d695e5d3460cd1f0940fb27df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5120", "a00260.html#a47f354e71d8c2307e97244f6d5626e5c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5121", "a00260.html#a7acb9d9459036aff0f2c11d573e8fe19", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5122", "a00260.html#ad496ce38dfae0e204ba178efbda382f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5123", "a00260.html#a3ab2b98487ec8c9ec3256da5e263fd57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5124", "a00260.html#a5a0edd7297978f9720fe2024d76fa773", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5125", "a00260.html#af329da13208c2a1bc982c78f78c32908", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5126", "a00260.html#a2c5021f28a97076520323b2360c2fc0d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5127", "a00260.html#a4fd2adbe8aec4dd8d38d82ebc677d467", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5128", "a00260.html#a4f1fa47331e53970b493c970d9083fcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5129", "a00260.html#a98c1ba7df58a9b5ecb123da620c3bd00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5130", "a00260.html#a83b799b40901ee9573839412528c8b1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5131", "a00260.html#ae5dd02069e70e231d6024c1d323e335f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5132", "a00260.html#add257b7605f7951a856c511067fd79b0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5133", "a00260.html#a2cbe4ac9b907276398cd64e50a8df594", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5134", "a00260.html#ac3e8c7d2700acdbe798171583702192d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5135", "a00260.html#a188696ccf48304376cf339bb31479c3f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5136", "a00260.html#aeea6d13f1a4892def52c8917f95360c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5137", "a00260.html#aa88fd9cc63d0f042853af152b4cb8a1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5138", "a00260.html#ac2211a289f0c7a64f6be8555011f1823", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5139", "a00260.html#a8da8f99b3ebd8212ea268b1c4573b20a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5140", "a00260.html#a576053ed685421265f07368446d58cd7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5141", "a00260.html#ab8d0c94c83098407e4dc90ed9f39052b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5142", "a00260.html#a53f84326a464ca1a70b24e8be5630304", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5143", "a00260.html#ae069ea84e6d174146df63430620eb818", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5144", "a00260.html#ab997ec48519d1d67b775d2cf87f05a75", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5145", "a00260.html#ac363335d8dd8626824362069a92e7b65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5146", "a00260.html#a837783c08b4daed321735a91415614d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5147", "a00260.html#a708199ad3211e21b753ae7d1bbafaef5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5148", "a00260.html#a95908601856053bdd5ba0e294fb6d099", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5149", "a00260.html#a70e67d81028f1bdb8feaed7b69ae7fd4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5150", "a00260.html#ab0a47eaf6ed149e28d24d78f74c8f5b7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5151", "a00260.html#a3048d884033166479b9e74e7f7ab3faf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5152", "a00260.html#a1745e87b5ecf84fd175d4c917689c121", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5153", "a00260.html#ad1ba9e62833904278dff08c1ee70bbf0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5154", "a00260.html#afd770f30a2e6d6ceec3b8acc97b12af3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5155", "a00260.html#a610fd0d07ef18abaea8daa3d87845fe5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5156", "a00260.html#a6b93e355e2e44aef73179ee9a2181dc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5157", "a00260.html#a64b4bd5f3a927e3dff11a2e3af0a13ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5158", "a00260.html#a637bcd4fa24a9ea651748b228b414e59", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5159", "a00260.html#a0793bb0e4e2e757856e486d00be025b9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5160", "a00260.html#a973f6ac9d24b85ceca6d4792b3910fe2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5161", "a00260.html#a677d2de7c9b43e3e151a6b8cd4856ad6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5162", "a00260.html#a33073649db6b306f6132fd7ccb6e5723", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5163", "a00260.html#a5e185de59b09435915b238aa5bc024a2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5164", "a00260.html#acd8b7a3a8a15075530e4ecf89c6ffcf5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5165", "a00260.html#a2d539e9b6e96d9f6e7ff9e5c644e5568", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5166", "a00260.html#a3550d30ae8b9d0edc821a6464af9c24b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5167", "a00260.html#abf366fcab3986bed20e607d70c6c26aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5168", "a00260.html#ad1feb35bcf493d7575af865d7861ede7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5169", "a00260.html#a29dddec3a8d5d4ffe25cda482524fe4f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5170", "a00260.html#ae7ecbac28c22aec0a9b004ee7abc5b9e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5171", "a00260.html#aea23360a9fb2d72c9f7e85f430b0fc27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5172", "a00260.html#aa50237e6d29f4f35f1321ffbf4e79a57", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5173", "a00260.html#a2b898318b367a7e68fb8ef0df20a7382", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5174", "a00260.html#a9345c6320b629f46133384b403374aea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5175", "a00260.html#a74e7b3b55093eac3d6dda5dfb3e429e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5176", "a00260.html#afcc94d58c78fa886e1b1d6820d6dcca1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5177", "a00260.html#ab276e0adf9fbc2c5cd93a156c200d01b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5178", "a00260.html#a91dad461e9460c426814a76f2c049645", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5179", "a00260.html#a0ee0376509bb6af9db8a5eff0efe71cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5180", "a00260.html#a76dda6ca3b949e81ac4cc47e862ad8e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5181", "a00260.html#a4141ac2cb223442fa607f342c8cf679e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5182", "a00260.html#a0147cb5e09b6fecce08b7df0a45d0484", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5183", "a00260.html#a974ef8a93bc83747d687a87d05100238", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5184", "a00260.html#a48b67cfd1920455dcb123c4152824160", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5185", "a00260.html#a639581bd8024a0823a6e6fe2509839c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5186", "a00260.html#a41ee841c716811c621a718f446516a8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5187", "a00260.html#afa527533d4c80f52e2c8afee7506335a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5188", "a00260.html#a1b7a4a6b984c3083b13f57f995b9625f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5189", "a00260.html#af19d664440dc50803b269c536a0360c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5190", "a00260.html#abe4b9a826bab259daf5b9c828bd6b42a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5191", "a00260.html#a9358adcf4cd2f6a88fb30a868f820e1e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5192", "a00260.html#a0e7f78b9780e356aa0e3210324ac5e00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5193", "a00260.html#abaaa926e7b77528685156b6e0fc7f415", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5194", "a00260.html#ad5165fe8428f6fa2d98b524275d1cf2b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5195", "a00260.html#a974ce9fb0afd3b7d85507196c1ce8634", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5196", "a00260.html#ac97af212bb60bf162563d2c850a0142e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5197", "a00260.html#af4f51b4bd364d3f5c2988564bb5fa749", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5198", "a00260.html#a9b6baaa30a3b85ff1e06f4424f91ea51", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5199", "a00260.html#ae6ee2adf3e731e4ea01ce993684d661b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5200", "a00260.html#aed8fa84b2fa05312f74662386fc2f287", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5201", "a00260.html#ae412281c0970169558566b5c148d51d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5202", "a00260.html#a3725f5ac1684e42a78a3cd62675c9c68", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5203", "a00260.html#a17f8f37e1b42aa69f9fc360233966e4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5204", "a00260.html#a20daaaad2943a6a1002c9b1c99ec8a34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5205", "a00260.html#a8e3926b78bf626a9dc040ed9c9b7ca87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5206", "a00260.html#a8e8ee523f5cae298a5b25c7beb3b77c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5207", "a00260.html#a1d14cd781913465cec63db357d277b00", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5208", "a00260.html#adfc6a4a21031d797f411d8521507bf78", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5209", "a00260.html#a552bb7707bb6c1cacb8adeb9e2d59bce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5210", "a00260.html#aeaf825611533607c00684ae6658b188e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5211", "a00260.html#a0ab30c3be037e4a00efe39d78d2ffdb6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5212", "a00260.html#a18b917c9fe9fd6f391465e6e330da8f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5213", "a00260.html#a899e12566906522e2276fdb02d356862", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5214", "a00260.html#ac701e816ae729a9977fd5a3428bb0338", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5215", "a00260.html#a8bcfcd7ac7d53aa92622731d05492288", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5216", "a00260.html#a8e4d4e3efb35dacdeb297fb81e9c6867", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5217", "a00260.html#abe75a10948f935e69b38c4d1958b12f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5218", "a00260.html#a5cfce7d0c7e55e6200fd4ff32837d4e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5219", "a00260.html#a3220f8324f9fd7165b3c477425371d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5220", "a00260.html#a75ef81f4cc0e8ba9be84e52a0ffab1af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5221", "a00260.html#a0de1cd4d49596bbb26949ce6f093d423", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5222", "a00260.html#ace43cfe95d8a527a6cb2e2767e13383b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5223", "a00260.html#a923a6e07ef072536fa2574493dbf404a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5224", "a00260.html#a0ebf77dffa277be07886dccbc5da02a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5225", "a00260.html#ad64251f56c63be18d559e4316332b206", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5226", "a00260.html#a5745c9144b9062b5d0dbf68ca5975f91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5227", "a00260.html#a32d9e05fe3eca3ba78a3f6d9b7a83153", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5228", "a00260.html#a43f16f09540d84a1e245efb5faf85106", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5229", "a00260.html#aed9ff446874f0aa7ffe2a0b72907e79d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5230", "a00260.html#a914464634210bd54ddd95114b2f83387", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5231", "a00260.html#a821f8ba225e0095a3d30d302269142ae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5232", "a00260.html#ae0648ae8061388983b905f8ab6c35fc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5233", "a00260.html#afa49a092548783183d09f2360862327c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5234", "a00260.html#a47b78ffbe203d111c1d0223a492511d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5235", "a00260.html#ad96aef710906141d341c0631a6a2b4c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5236", "a00260.html#a227c542a43f7810ded809fc210aa1c12", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5237", "a00260.html#affd4837826ca9db0d7fe48fbf213659a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5238", "a00260.html#aec55b231e3c820fe30302f6dfa25a0ea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5239", "a00260.html#a088c2431c0b0448bece6c5d1377ad220", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5240", "a00260.html#a7d5b7479db838f9105920c332503279f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5241", "a00260.html#a637e04fbe1c735fa70fff7c956d8a97a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5242", "a00260.html#a14ff89e3aaadfa64caef3887abebdcfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5243", "a00260.html#a9c4068f20da65bed79eb11ceb72b6da5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5244", "a00260.html#ac9c38fdb5853523fda76cf0ecc2d6e70", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5245", "a00260.html#a65ad92d20769da730c3472da0c3b34e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5246", "a00260.html#a6420099f5a32bcc79ddc4f6b613ac3dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5247", "a00260.html#a4ca34b01c12bd7d5a3a2ef2b5c1a53db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5248", "a00260.html#a5a9b099d404f142b9260c049655e11d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5249", "a00260.html#ad53be0ee67fa840f9bab273cc1f59a73", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5250", "a00260.html#aea00a66fd5d3d00afe3da62b5af0943c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5251", "a00260.html#a9b5efa46571cd09acff42bdd21e0bca1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5252", "a00260.html#a94170b234ca12494ec33b7c1eaf7a228", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5253", "a00260.html#a6599c8cf88f1785568082abad325b5b5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5254", "a00260.html#a2819fa1474a52aa517e061063d0fb5dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5255", "a00260.html#a2d4e9a64b526449059e93eeb0a2b5007", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5256", "a00260.html#add9a257ee329c1dfdf168d98f9f66995", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5257", "a00260.html#a5098ff60fdc7e7b39349cd9595c88a0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5258", "a00260.html#a312846b9d47cd6205b49904e7c279446", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5259", "a00260.html#a0c21d87f6c0022c08d500a2a2796c98a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5260", "a00260.html#aeda4f699d15470b33112bb7c21fd8c62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5261", "a00260.html#a7bbbd4d8acc1460caa34228443d2ed27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5262", "a00260.html#ae20f417843bcebb506b7e5534b3226c1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5263", "a00260.html#a41f4c0b0869f9f124014c8230af3079b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5264", "a00260.html#ac826e6891559a9e64d22afc357ffe210", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5265", "a00260.html#a56947f393448192a22f01aa80882ba8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5266", "a00260.html#a874e50d7357ecf266001b8ccc70be42c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5267", "a00260.html#af160ffd3b33ccc6122f9cdd3c08d3542", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5268", "a00260.html#aba4e8dffaddecd297068b0f1c9f3ebfe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5269", "a00260.html#a204ecb5d9f4ff8c067ee3641ec271ab8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5270", "a00260.html#a6547b611b47e3f94d2fb3cfbadff4854", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5271", "a00260.html#a8e4f27ff54e9d1b2acd86465352ba2a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5272", "a00260.html#a7707f2f8cfc69670d16dadc0243e7742", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5273", "a00260.html#a5136a6626538e5aae6e353c8f27544f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5274", "a00260.html#a83d8d20575488bf29dd922816771efac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5275", "a00260.html#a23fc7d5a20fd575039b3e01280c150b2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5276", "a00260.html#ab6e77d6e15004802f88637446c65f3fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5277", "a00260.html#a0cb37fd55aab0cbed5d943cee04e1060", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5278", "a00260.html#a4e7c940decfc74b783610d0f0e88cf5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5279", "a00260.html#a09c7a574faec1401133137cb25689bb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5280", "a00260.html#a82cfda07a232a0278a6d74a88a15b5f3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5281", "a00260.html#af43236e5c0896c1b8c3efb7d6df96342", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5282", "a00260.html#a27e956d995170d7b70e90c55d8b36b8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5283", "a00260.html#aed11b5aa78ec427797a6e5c2972cc457", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5284", "a00260.html#afd7248580c107b83e66905d1732845ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5285", "a00260.html#a8993cba754067247ba1e05fdae400c3a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5286", "a00260.html#a4205a540fe302c879244be9b94a3e3a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5287", "a00260.html#a0cefd82a12e46c3f98c09e6e473071a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5288", "a00260.html#a1bde190684a9472a76e05ae6693b8e2e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5289", "a00260.html#a2e82c79569ba6f3cd3083625474bfa52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5290", "a00260.html#a6123f97c54a9486ab44ab22f596be3cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5291", "a00260.html#ac7b9eef9c39cfdba67157af31067e26c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5292", "a00260.html#ae92fe37e965bfc31eafd74e8c58d7018", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5293", "a00260.html#aced0c2e22f0e7f15c45d2c3ce68d863a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5294", "a00260.html#a7fb988b70300c5bb4939a3cbea9a054d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5295", "a00260.html#a74fa1f5fccd43102c56631bc0e4bc28c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5296", "a00260.html#a7420a8af2e1267ece84c7e9018484fae", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5297", "a00260.html#a523bc6da931dbf36285514c2940f51eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5298", "a00260.html#a51141301adcd927bf7de129eacdbf356", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5299", "a00260.html#a5c5b3bcc32dab0372d87699ad216252e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5300", "a00260.html#adf3f1308e7f9059380a56c1193582e48", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5301", "a00260.html#a2273c91104493e63e78d3fbd3cde40e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5302", "a00260.html#a934e7f5cff1d83740514e5deab7bfd66", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5303", "a00260.html#a167e84745f805ff5a21a3111d15e296c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5304", "a00260.html#ac2d48018faf3596f34c24881ef3f5b72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5305", "a00260.html#ae788563b7cd4ab427bdb5bdce72d9322", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5306", "a00260.html#a76e7576a96f6985717f7545bf6df4983", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5307", "a00260.html#afe0bb5ac7b041cb09d0b11bf11182094", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5308", "a00260.html#a9a9ead17849cb294f799ae1d49839b25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5309", "a00260.html#ad9d71437f082bb1f09236b4a9673bec5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5310", "a00260.html#a91644e3702c359646e4ec398ae5e0fe3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5311", "a00260.html#aabb54e48941d953763997c47acee0861", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5312", "a00260.html#a004d293875ae4c1e4d7114aa31ff81ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5313", "a00260.html#a23d7ec62270bdde82123061d10ddc2b8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5314", "a00260.html#ae2ab0a952685152376a00203ceae136a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5315", "a00260.html#af137333f7819a5b52367e56905da277a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5316", "a00260.html#a98a6a94cd9a95e66df23246e9c9fede9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5317", "a00260.html#a3050e8aac70a5f3a8b9d0e4224e2626f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5318", "a00260.html#a50120c6b1e6e32aa004dc746d1c0a63a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5319", "a00260.html#a6c78572b918215fc35d88e3ed1a00b2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5320", "a00260.html#a2bc34b8d244569d57df49b19919b7fb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5321", "a00260.html#a61c2c33a5dfdba4e24db24b6cfec3371", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5322", "a00260.html#a34466748103b428d0bc50f8031679b20", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5323", "a00260.html#aa45595e8e870dc09c43732b7440c4c06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5324", "a00260.html#a8314d82e673438a1a705c2b04ae67499", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5325", "a00260.html#a631b2be43dab763e983244f3bd0a9145", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5326", "a00260.html#a6b589b6da922d9215271bb0cb6bfdb52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5327", "a00260.html#aabd602111748aa0e045a8287a4211c8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5328", "a00260.html#a2ffa45e9879425581140803bec209c79", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5329", "a00260.html#a34a509e91edcbfb3c11b5d76e405943c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5330", "a00260.html#a2b6123d968c3a1790e46d75a6d29a944", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5331", "a00260.html#a3331b2d2f23150cbcab4ccb54c907162", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5332", "a00260.html#aa5774b0b0b21f15a015646968d165135", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5333", "a00260.html#af61da196b41c172c27fba9f8ca7d8f53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5334", "a00260.html#ac74cc7703ef919993b03b794b30cb83e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5335", "a00260.html#a079425f062eaa0814ae6178ace769803", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5336", "a00260.html#abee0a7a4ba2cc83b3fe7284c1c0c2d8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5337", "a00260.html#ac12b4f0f966c4b468b05cf7bd6534df5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5338", "a00260.html#a9679f84f9c9b6d55ed86a634cace61bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5339", "a00260.html#a2cf335f2f971aa554ce86dfb71ad3af6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5340", "a00260.html#a27efb932a665bb1b45992d151958786a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5341", "a00260.html#a373510c2f40e37203705142b2a933597", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5342", "a00260.html#abd2a74ac21291b36e6ea5c82f05e805c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5343", "a00260.html#ad11e673195a806d4a38f0c5419c16327", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5344", "a00260.html#a3bb71e663744c9b5ee7a86768ead8dd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5345", "a00260.html#aaf4e323b93db57f1537455952d06406c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5346", "a00260.html#aae99d59d3962aa12684e427da8fad5c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5347", "a00260.html#ae79d9196b1d067d1be6672beee931814", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5348", "a00260.html#a72bcc85b1ed9e6fc1f767706bab7c81a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5349", "a00260.html#a07c4178c2a30322178cf6711101d15db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5350", "a00260.html#a940a852588e0286ce6f3652275a97fed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5351", "a00260.html#a52a4f1ae4dc1af60f29dc5785ac65d04", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5352", "a00260.html#aa0a619ec4265a2b8df4ccf61db8ba216", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5353", "a00260.html#a60d6cf128811d34dea903764974f2381", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5354", "a00260.html#ad7adf693e32c530c9d35228713e229d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5355", "a00260.html#ae8724eaa9e37c5f0571e967bb93bb165", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5356", "a00260.html#ac162eaeda4b12a936b0968e2c28bde0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5357", "a00260.html#a042882a9548770dbe3672bd67b4659a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5358", "a00260.html#a600b969d0c444adfcaedd3881e2c5453", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5359", "a00260.html#ac6883645a84b5cf132d523152695ca5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5360", "a00260.html#a75d707cbb516f0c1221b812f1f53fdca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5361", "a00260.html#ad72d8a506b1ba326f6e930b86e1fdde8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5362", "a00260.html#a5c977e4b821a7a47fef08cae96aef651", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5363", "a00260.html#a52f6882c8a85df9f5aa8862caf3b47d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5364", "a00260.html#a44c27e66938007a99fa1efc49a5c32be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5365", "a00260.html#a1cf56d67924eedcc8f5c5b692edb6706", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5366", "a00260.html#a6b1d6ba3d25449acc24ed10ce0f25229", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5367", "a00260.html#ae1161162a93fbc90e7c1779aeb876713", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5368", "a00260.html#a3c0c62fe2ac5e26aba54facf56c9e8f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5369", "a00260.html#a2a8b809111caf5bf54444b4a3d41e274", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5370", "a00260.html#af947ab313fc23606545461c741c7a534", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5371", "a00260.html#ae79ae64cd8c88f56e8c4ed46de02086e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5372", "a00260.html#a4883df597815a00bbb864c4fbbc981ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5373", "a00260.html#afe7c119b9f13c611df0a35f93c798f94", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5374", "a00260.html#ac616e9a94fe0f9aa8e6c321987a356cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5375", "a00260.html#ab35462c63f22a7cc2637dc23be33a949", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5376", "a00260.html#a9809038c59290bf4011cc4b9cad15ffa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5377", "a00260.html#a448d1d57f27f9ad8c1a2a161b92054c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5378", "a00260.html#a4ae3b9ef81d3e0c23c72ceeb3b45b1f9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5379", "a00260.html#a9154c8d4e59bc6e4e57408c7669150e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5380", "a00260.html#a4fd5e9eea4147997ec40d32a068a5379", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5381", "a00260.html#aa2faee475d4104da25884d3167ecad85", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5382", "a00260.html#a2ce844805806f27652abeeb097cdd2c0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5383", "a00260.html#afdbf2102dee0efdfa0938ee8ea72880d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5384", "a00260.html#a574a87c9dad2ae7f40ea24635d8c680d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5385", "a00260.html#a3a9825367fff9221b641833f7079fcd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5386", "a00260.html#a7ff263c7d59ccee4ff3f291e55613265", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5387", "a00260.html#a1af82298c2691a399f944c6c99a63078", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5388", "a00260.html#a5f4bf290889943f21ff92349ad58ca53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5389", "a00260.html#a208251500ef1fdf7bd56cc37af85597d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5390", "a00260.html#abeef2baf1f25ccacc5fd9e4283323f54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5391", "a00260.html#a6b7365f7323d7b1352ba695c97d5bcbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5392", "a00260.html#a2e6f2490257739e8907f26bde44d7d87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5393", "a00260.html#ae883731b57fc868ea6af4b9997b709de", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5394", "a00260.html#a577d7c226a89bbf163292bff28e87d5f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5395", "a00260.html#a70286ad50a36e99067e406f5f40d832e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5396", "a00260.html#a6026dcee158a335269ac5d1e5315469a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5397", "a00260.html#a3375a4ffcca16357d3b9d43ad9ecff62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5398", "a00260.html#ad16571e2e85620fad9870e975b0a7027", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5399", "a00260.html#a543a1bed8f6ef0749a92c32ca6670ac2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5400", "a00260.html#a58aaebd828763aad371752adab414040", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5401", "a00260.html#a6dbda6b16cd774340e8825c5307a5ca8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5402", "a00260.html#a2f35c1d5abe9cca4f3ce8ccb752d5c56", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5403", "a00260.html#a43ea7e3cc5d162d3dde87a9d7264ff5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5404", "a00260.html#ad9e6a921889bdc70a6dcf8997e08a011", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5405", "a00260.html#a724fa498e31b40037d880d7055f320c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5406", "a00260.html#a3b2e5ec86869867c6eb47490acad4fcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5407", "a00260.html#a6e32507e9a18e678e4ce555a25cacb3d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5408", "a00260.html#aa6c57bff8839ae164522de0cb85f09dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5409", "a00260.html#ab8980298362766909dc3a0ad82f8ffea", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5410", "a00260.html#a2b3ef1fda07308d032189ee15cbcba1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5411", "a00260.html#a53fef96769eee37ef9445183f3908d36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5412", "a00260.html#ace0d61537d9b510a3cf609750bb0c80c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5413", "a00260.html#a3f4a398838df7e0e0a35867e82620a77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5414", "a00260.html#a5c03e02468fbce57936270fe41efe9bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5415", "a00260.html#aa99c97433154a1beffd6d18999e5d4ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5416", "a00260.html#af1ddca701d1dad2d7d692a31644a59ac", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5417", "a00260.html#a83793f273c9a7bec0841eb828d204bdb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5418", "a00260.html#a03c75a4369bb42a4ec10674e9031b055", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5419", "a00260.html#aed09a5527876392876da530628ffc36b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5420", "a00260.html#a6a766b19e974e89ecd18c461c93a4bf0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5421", "a00260.html#a235fd26f88919e7b21018146033527f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5422", "a00260.html#aecb45c8e11e0d9ba8d046729222c4dcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5423", "a00260.html#acb3b26741474486a72bab850a84eb4ba", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5424", "a00260.html#a4c28dd41cb4e7b322a057b8b809a0277", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5425", "a00260.html#a0e1cccce7d7780a51c6857db2c83f826", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5426", "a00260.html#abb277f7cabc43c2fe6aea9a57e9abe8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5427", "a00260.html#a7bb20989e5e382b80413f2bb3a2c6a43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5428", "a00260.html#ab53ea1f579e7aec691adf7d0a8e6a04b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5429", "a00260.html#a999329c5e6567d71afb3521e49233320", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5430", "a00260.html#ac88b1aa9a5d78cb16cebc4fa8083dbc5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5431", "a00260.html#ae730a122b720206cea939c60ff72a7c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5432", "a00260.html#a5e51c247a6feaf35e2a482a2ba3b7a69", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5433", "a00260.html#aeea6bdce8305556bb269a978c4f8bc1f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5434", "a00260.html#a338774ebe607ad109b3dd7319595cbd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5435", "a00260.html#a0d2685bb82494f8e4a7c07dcd07b8a97", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5436", "a00260.html#af3303938aabaac54b86ef8d8848790c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5437", "a00260.html#add5268dd69459d437bd9650294a190e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5438", "a00260.html#a079cd57c333ca3078035549eecc3c8e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5439", "a00260.html#a5ec741f6931c795fe3169aed4165b9b3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5440", "a00260.html#ad7d0ce50baa57bcc99f38ebb291fbf39", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5441", "a00260.html#aab5cf9e10fe87be7a7b1e720f6e4ed0e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5442", "a00260.html#abd64d903d57810ed0ca679eee4129a4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5443", "a00260.html#ad6024ea77fd0cc1c28befc0b3f9e6061", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5444", "a00260.html#afc7ce29878e7ed65be4c546960059aa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5445", "a00260.html#ac6884c6125ffdd99ac7aa09fc2c8ec24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5446", "a00260.html#a78e37e5482db1447ab8e003802199eeb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5447", "a00260.html#aabad3c7d846a788569773d48282a8b25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5448", "a00260.html#a0f94eea6b5c1712a9efb0505e90cc458", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5449", "a00260.html#ab81b1345390c895dae1b74218851e304", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5450", "a00260.html#a143c411a65b8f8948d670db645b62063", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5451", "a00260.html#a7275ae98b30baf13d9be87634b66a6d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5452", "a00260.html#ad942b24b3bf2f192574b0bbf1ebf1ec8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5453", "a00260.html#a9b6a82e9e4457e141bdc4174b7de55eb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5454", "a00260.html#a27101fdf42d789151b44e034b291e442", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5455", "a00260.html#aeadb2ef0de0a79cd21e195fc86e6e18a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5456", "a00260.html#a790ca9714fc7d6fc95b5164244c3b6c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5457", "a00260.html#a22c7414bdf800e60ecb5a403a1c67df1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5458", "a00260.html#a8ccc379c1b879caabde3e960437cc363", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5459", "a00260.html#af9d3dc47b29aa5d9fdc136abe5b9380c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5460", "a00260.html#a52353afe443d98eb6768e8e8cac819ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5461", "a00260.html#a8327ef62cc86fa979b974098f01a329e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5462", "a00260.html#ab064f963e241999f360dc3bcc7fa1440", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5463", "a00260.html#a45f71975d08b12a863e82abb338fc2f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5464", "a00260.html#a4b725453795f722ef372b56c9f3cbf55", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5465", "a00260.html#aed6bde22dc0d8f735ff1e02d8fe94e5a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5466", "a00260.html#a45280e1057e3ba86544da526bc380b99", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5467", "a00260.html#aed07a52ece1a23c099ad2e32e108e79a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5468", "a00260.html#a22241684b3c8c3c6f1912797b8ce0726", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5469", "a00260.html#ada4b2882250c06d609b529eee24008db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5470", "a00260.html#a6921278ef5ae04ca6b4089ca511a94fe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5471", "a00260.html#ad3f3ed46409bc996634da3b6abc4c1e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5472", "a00260.html#abba5a6bfd67a79b56f9f18e970c93cf6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5473", "a00260.html#a2e5e1117860e108549f5489b046fc1ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5474", "a00260.html#a135e2350528000639f3921411ac94034", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5475", "a00260.html#aeb90774f76ff0b4c610e1447d5ada89a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5476", "a00260.html#a8c7e39a70a168ed8f2b6ebc6976576a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5477", "a00260.html#a574f13bd302766e5829a0d26b89ccc36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5478", "a00260.html#a2e177015586874fc2326330677ff09c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5479", "a00260.html#a81d2168bd4c4ab1b944e7d6d97aad807", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5480", "a00260.html#a0147e06c2c01b56c00666cc820265dbb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5481", "a00260.html#ae6da40968b5d8de6090c6734670d7a1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5482", "a00260.html#a40526452fe42e84cf6d3dca21f3989c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5483", "a00260.html#a4949bae06e29417c6dca34a8b347f0c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5484", "a00260.html#a70ffc93e0b036c74f026902f3b8c38cd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5485", "a00260.html#a0de114ea390d5dfc6a1a1cd498d52fed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5486", "a00260.html#a5d0cfc45932a7b3b6572cbd80d6474bf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5487", "a00260.html#ae2afad275ffd11e4ceb9381707786eec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5488", "a00260.html#a4590a3557b95218e57f3c002e87be1e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5489", "a00260.html#a9115dd7840baba1e0ed6f045c5d8024c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5490", "a00260.html#a9224c99cdf3ce963b3f21c74da49bbc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5491", "a00260.html#ac1468625764118f0c8768e11cd0402d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5492", "a00260.html#ab6d5501f9fba89c3aa52c02547a48986", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5493", "a00260.html#a9b45abf2e6d4133cd20b290e44d51a1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5494", "a00260.html#aa8c282ac0568f9407de391910e342d2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5495", "a00260.html#aba9ce635ea4633630c55aa3fabde18d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5496", "a00260.html#a33981515f9d98b8d7462fb97e1b598a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5497", "a00260.html#abc7a0a1c335a63093234c53a11486bef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5498", "a00260.html#add1e44a08f309738c638cf3518266678", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5499", "a00260.html#acf098baa2c0db53832fd9a93f6971188", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5500", "a00260.html#ae462b3f9a26f8ba2b372f69c041a5c63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5501", "a00260.html#a678737de72844a85bc41861987fd9d15", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5502", "a00260.html#a317e4799840539a9afdc7f8cee3674bd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5503", "a00260.html#af30cd41f0111950762504e4a9f1df506", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5504", "a00260.html#a8263429a1800775bb1b85d6a40411153", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5505", "a00260.html#a7e49cc734bc0b6e1169aef7b70be61a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5506", "a00260.html#a0f359bc8bacf35ce451e472079fbb17f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5507", "a00260.html#ada90ccd725736be5c7dad194ef08a1c3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5508", "a00260.html#a9f614cd521ae032467d2bea1cc068fbf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5509", "a00260.html#ae2c7cc00adb32acda6244ad9398805fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5510", "a00260.html#a3f58583c98fb82de5ff2238635e4c327", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5511", "a00260.html#ab057ec1803f8b7c828a103ddd148b8c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5512", "a00260.html#a4ca79e2ac9fc8415fe734f73ae2205b4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5513", "a00260.html#a959022e5cbaa369bda26de03d31dc37d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5514", "a00260.html#a4854abbd62ac053de5f19c48ea86d038", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5515", "a00260.html#ac72b4dddc835bfc10027cda3ad2c4ff5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5516", "a00260.html#afe85a2e8c845af11831f06cac9c5ec9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5517", "a00260.html#a73cf7bade79dcc237f72247cde0094c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5518", "a00260.html#a890ac0d18c45a49dce7e613596790b52", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5519", "a00260.html#a466cd352eab306b0b33db9c961810fcf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5520", "a00260.html#af651524ec6341aef282265aea33db2e6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5521", "a00260.html#aff4b269437b3f154f1c6e687b3b475ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5522", "a00260.html#a4c0f9709085290f4aecde2691f64a483", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5523", "a00260.html#a4055ba1bd8f00ed6650f6a5a42023626", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5524", "a00260.html#afd97a4bcb7137c0571d039419856bc05", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5525", "a00260.html#a6c3914f7eef70ee1b8048cc89b6fff0a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5526", "a00260.html#a8aeb69f33dbe08ed4d1085fd2cac6a6e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5527", "a00260.html#a0b74750ac5e6904032df39a61887a05b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5528", "a00260.html#a4f5c45918c2af0669848e716474a335d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5529", "a00260.html#a75dda7f19637feca332a9791ea9e8915", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5530", "a00260.html#a7c441caca1af65189af7bf5b294eb7e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5531", "a00260.html#aea2a17cd632de9b113477fc7568b95bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5532", "a00260.html#a7c4d8ef1e69f88a3cf58aa641be00a74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5533", "a00260.html#a8356f68cd534178b27e9d64e2a31e14b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5534", "a00260.html#ad208a7bd34ab67c852766b32fa943950", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5535", "a00260.html#a69d5950dac05c91ace332e7f93af0ea5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5536", "a00260.html#a5a863d85a2d1b8d214edaaf649a40bb4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5537", "a00260.html#abb33ef1449992da2474e86cf557de5f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5538", "a00260.html#ab8eb76a57e3a82a120d1239bc0cf0ee2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5539", "a00260.html#a267b044cf03561228d6e60a6d381b36b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5540", "a00260.html#ad76010fa0ad04cd7dbceabd641db5120", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5541", "a00260.html#a3da105c68f18bb1b995830efceb232d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5542", "a00260.html#ad7d161b94da789234cbc34b6a0ae0d4e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5543", "a00260.html#adf747876ac8fbbd7aa441faf622fbc43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5544", "a00260.html#a514f73502a47b89ac26865aa76c4b1db", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5545", "a00260.html#acde6d1e46d28545a803d45be76c113ec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5546", "a00260.html#a579692b6f2d7f0167aaada964143b325", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5547", "a00260.html#adc91aeabd576171d8d17f7b5c7ffbc2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5548", "a00260.html#a89a925ef0d485143bee67b471f3eaba0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5549", "a00260.html#a0ba522bd9cbc869e152201fda46c89f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5550", "a00260.html#a5047036f46b2a1de95af0d44e32be276", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5551", "a00260.html#aac4c121f41aef6023a7da61a60f04378", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5552", "a00260.html#a3104ff7b12a42b4b5841e401e705a870", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5553", "a00260.html#ac226094628ea0d93704295c37b7a565a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5554", "a00260.html#aafb8a4c68e0e68d745e33b90d6936846", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5555", "a00260.html#a0c0e9fdd3aa38ec37d4d2e6e9385994e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5556", "a00260.html#ae4f028b19912ae20aef5db341712e42a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5557", "a00260.html#a4e021d4266d681bb39ff7642340ddb7f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5558", "a00260.html#ababf510e92d5a47218c41c52df1372cf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5559", "a00260.html#ae1c9c8ecff1aefc15ab1db6cc082bf28", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5560", "a00260.html#a07cdff54d248096658dfaeaf0e35d9dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5561", "a00260.html#a6470f187f3ada82e4b7fa4a2b0bcb221", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5562", "a00260.html#a34cf63f8512517f054a327f6fc5f356e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5563", "a00260.html#a89a4af095ed660906a6a7939e723aa72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5564", "a00260.html#a22dac74029f50102fec1cb47399e3f98", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5565", "a00260.html#a962e54a1ba8210b24a7b0c853952bcf4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5566", "a00260.html#a6d06934f83a4e60deb79d2bace86f705", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5567", "a00260.html#ad934a9ec8176efb4166c711fdb4a8289", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5568", "a00260.html#abc4a6d7f4f61c9f24f6ab253d900b721", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5569", "a00260.html#ad50999bc7fdb0f507ad10b0027cf877a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00260_source.html b/components/els_pkc/doc/mcxn/html/a00260_source.html new file mode 100644 index 000000000..291c4715b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00260_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClCore_FunctionIdentifiers.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClCore_FunctionIdentifiers.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
23 #define MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 
27 #include <mcuxCsslAnalysis.h>
28 
29 MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER()
30 
31 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwVersion (0x6366u)
32 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwConfig (0x4C37u)
33 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwState (0x7907u)
34 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Enable_Async (0x44DDu)
35 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Reset_Async (0x5457u)
36 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Disable (0x466Eu)
37 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntEnableFlags (0x0DB6u)
38 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetIntEnableFlags (0x4E2Eu)
39 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetIntFlags (0x0FB2u)
40 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntFlags (0x55CCu)
41 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_WaitForOperation (0x34B9u)
42 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_LimitedWaitForOperation (0x6CE4u)
43 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetErrorFlags (0x710Fu)
44 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorCode (0x7456u)
45 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorLevel (0x59D2u)
46 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_Async (0x59D8u)
47 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Enable (0x496Bu)
48 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Disable (0x23CBu)
49 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_ShaDirect (0x7C29u)
50 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cipher_Async (0x13D5u)
51 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyGen_Async (0x2E95u)
52 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchange_Async (0x5762u)
53 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchangeInt_Async (0x555Cu)
54 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccSign_Async (0x3C36u)
55 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerify_Async (0x5B0Bu)
56 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerifyInt_Async (0x62ADu)
57 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp (0x5578u)
58 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp_SqrMultAws (0x067Bu)
59 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Init_Async (0x607Eu)
60 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_PartialInit_Async (0x035Fu)
61 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateAad_Async (0x0F59u)
62 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateData_Async (0x2E9Cu)
63 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Finalize_Async (0x2DA9u)
64 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cmac_Async (0x1793u)
65 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_LoadConfig_Async (0x693Cu)
66 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_Trim_Async (0x09BEu)
67 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hmac_Async (0x4BE1u)
68 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Rfc5869_Async (0x5B92u)
69 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp800108_Async (0x27A5u)
70 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async (0x3F84u)
71 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async (0x7545u)
72 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyDelete_Async (0x58F2u)
73 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvision_Async (0x5ED0u)
74 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvisionRom_Async (0x64B3u)
75 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImport_Async (0x1397u)
76 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImportPuk_Async (0x2CAEu)
77 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyExport_Async (0x258Fu)
78 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_handleKeyExportError (0x46B3u)
79 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequest_Async (0x4D9Cu)
80 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequestRaw_Async (0x62D9u)
81 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoad_Async (0x2756u)
82 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async (0x42F5u)
83 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async (0x62E9u)
84 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_Reseed (0x5939u)
85 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_Init_Async (0x3BC4u)
86 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandomWord (0x3AC6u)
87 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandom (0x49D3u)
88 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetKeyProperties (0x7E14u)
89 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_compute (0x2DAAu)
90 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_compare (0x42DDu)
91 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_verify (0x3D45u)
92 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_init (0x416Fu)
93 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_process (0x5873u)
94 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_finish (0x17D8u)
95 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_selftest (0x68F2u)
96 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_export_state (0x7871u)
97 #define MCUX_CSSL_FP_FUNCID_mcuxClHash_import_state (0x79C4u)
98 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Md5 (0x25CBu)
99 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Md5 (0x29F8u)
100 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Md5 (0x396Cu)
101 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha1 (0x61B6u)
102 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha1 (0x7196u)
103 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha1 (0x52D3u)
104 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha224 (0x7958u)
105 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha224 (0x6B19u)
106 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha224 (0x1A76u)
107 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha256 (0x5AC3u)
108 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha256 (0x4F1Au)
109 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha256 (0x39C5u)
110 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha384 (0x4E5Cu)
111 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha384 (0x115Fu)
112 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha384 (0x512Fu)
113 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha512 (0x28E7u)
114 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha512 (0x15E5u)
115 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha512 (0x54CEu)
116 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3_shake (0x4D1Eu)
117 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3_shake (0x1B8Bu)
118 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3_shake (0x1EC9u)
119 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3 (0x7326u)
120 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3 (0x3B94u)
121 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3 (0x2F49u)
122 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_finishAbsorb (0x25F4u)
123 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_squeeze (0x2D4Bu)
124 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_createShakeAlgorithm (0x5B23u)
125 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_Sha2 (0x784Bu)
126 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2 (0x076Du)
127 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2 (0x23B5u)
128 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_MiyaguchiPreneel (0x45F8u)
129 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_MiyaguchiPreneel (0x5C1Du)
130 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_MiyaguchiPreneel (0x166Bu)
131 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2 (0x36C5u)
132 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2 (0x73B0u)
133 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2 (0x4E33u)
134 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_dmaProtectionAddressReadback (0x5C71u)
135 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha256 (0x718Du)
136 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha384 (0x3B0Du)
137 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2 (0x195Du)
138 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2_direct (0x4EACu)
139 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_md5 (0x2CE5u)
140 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha1 (0x70B5u)
141 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha256 (0x72C3u)
142 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha512 (0x7B82u)
143 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_keccak (0x54DAu)
144 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha3_Keccak (0x3627u)
145 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha1 (0x33C5u)
146 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha256 (0x1A76u)
147 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha512 (0x3E16u)
148 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha (0x4E5Cu)
149 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha (0x115Fu)
150 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha (0x33ACu)
151 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha3 (0x0FE4u)
152 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha3 (0x2AF1u)
153 #define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha3 (0x4771u)
154 #define MCUX_CSSL_FP_FUNCID_mcuxClXof_compute (0x41AFu)
155 #define MCUX_CSSL_FP_FUNCID_mcuxClXof_init (0x6A72u)
156 #define MCUX_CSSL_FP_FUNCID_mcuxClXof_process (0x5396u)
157 #define MCUX_CSSL_FP_FUNCID_mcuxClXof_generate (0x1A6Bu)
158 #define MCUX_CSSL_FP_FUNCID_mcuxClXof_finish (0x6B0Eu)
159 #define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_generate_shake (0x271Bu)
160 #define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_init_sha3_shake (0x22EBu)
161 #define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_process_sha3_shake (0x2A37u)
162 #define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_oneshot_sha3_shake (0x0E7Cu)
163 #define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_finish_shake (0x3572u)
164 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadCopro (0x2579u)
165 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadMemory (0x7962u)
166 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_flush (0x26ECu)
167 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_setKeyproperties (0x3879u)
168 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_LoadFuncPtr_t (0x55C9u)
169 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_FlushFuncPtr_t (0x476Cu)
170 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_init (0x3635u)
171 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_setProtection (0x6C3Cu)
172 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement (0x7A19u)
173 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect (0x33A9u)
174 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_compute (0x22F9u)
175 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_compare (0x7686u)
176 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_init (0x16EAu)
177 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_process (0x5CB1u)
178 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_finish (0x4D59u)
179 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_verify (0x29F1u)
180 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compute (0x36ACu)
181 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compare (0x316Bu)
182 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_init (0x6B1Cu)
183 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_process (0x29CDu)
184 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_finish (0x70DCu)
185 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_verify (0x3077u)
186 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_createGmacMode (0x7CB0u)
187 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Oneshot (0x6783u)
188 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Init (0x528Fu)
189 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Update (0x475Cu)
190 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Finalize (0x7295u)
191 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Oneshot (0x2C9Eu)
192 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Init (0x5F41u)
193 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Update (0x5786u)
194 #define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Finalize (0x6734u)
195 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Sw (0x17D4u)
196 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Sw (0x1D4Bu)
197 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Sw (0x47C9u)
198 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Sw (0x323Eu)
199 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Els (0x2B6Au)
200 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Els (0x34D9u)
201 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Els (0x66A6u)
202 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Els (0x4D2Du)
203 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_compute (0x453Du)
204 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_init (0x43BCu)
205 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_process (0x4BA5u)
206 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_finish (0x7623u)
207 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_prepareHMACKey (0x46E6u)
208 #define MCUX_CSSL_FP_FUNCID_mcuxClHmac_createHmacMode (0x634Du)
209 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_InitLocalUptrt (0x6762u)
210 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_LeadingZeros (0x0DE5u)
211 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ShiftModulus (0x63E2u)
212 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_NDash (0x236Du)
213 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_QDash (0x60BBu)
214 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_QSquared (0x197Au)
215 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModInv (0x48DDu)
216 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModExp_SqrMultL2R (0x791Cu)
217 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestInstantiate_Async (0x5C27u)
218 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestExtract_Async (0x2E9Au)
219 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesEcb_Async (0x0B97u)
220 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesCtr_Async (0x743Au)
221 #define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear (0x6BC8u)
222 #define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy (0x126Fu)
223 #define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set (0x6AA6u)
224 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Initialize (0x7319u)
225 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Deinitialize (0x7315u)
226 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_GenerateUPTRT (0x1C5Bu)
227 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Calc (0x152Fu)
228 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcConst (0x6693u)
229 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcFup (0x2B71u)
230 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForFinish (0x255Bu)
231 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForReady (0x05AFu)
232 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_init (0x58B5u)
233 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_allocateCpuBuffer (0x6F09u)
234 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_freeAllCpuBuffers (0x58AEu)
235 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRtf (0x057Bu)
236 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_cleanup (0x2CD3u)
237 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_destroy (0x6A4Bu)
238 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_setSecurityOptions (0x0F63u)
239 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRandom (0x78B4u)
240 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_sha512 (0x6E2Cu)
241 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_aead (0x4D4Du)
242 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p256 (0x1769u)
243 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p384 (0x7526u)
244 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_hmac (0x7067u)
245 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_eckxh (0x2D36u)
246 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_extract (0x61ABu)
247 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ctr (0x3E64u)
248 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ecb (0x415Fu)
249 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_ckdf (0x3E83u)
250 #define MCUX_CSSL_FP_FUNCID_nboot_selftest_hkdf (0x4E2Du)
251 #define MCUX_CSSL_FP_FUNCID_nboot_selftest (0x4F58u)
252 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Extract_Async (0x1F23u)
253 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Expand_Async (0x7427u)
254 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Sp80056c_Async (0x307Du)
255 #define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_keyProv (0x59AAu)
256 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_get_oem_cust_cert_dice_puk (0x436Eu)
257 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_eck_sign (0x1F89u)
258 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_enc_blk (0x7C43u)
259 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_key_gen (0x653Cu)
260 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_sb_store_key (0x75E0u)
261 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_rts_get_id_clns (0x5935u)
262 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_gen_oem_master_share (0x5D83u)
263 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_set_oem_master_share (0x7D50u)
264 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_store_key (0x1AADu)
265 #define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_rfc3394_wrap_manual (0x6B70u)
266 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_ssf_insert_cert (0x15E6u)
267 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384 (0x155Du)
268 #define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_cmac (0x3E34u)
269 #define MCUX_CSSL_FP_FUNCID_nboot_key_delete (0x29DAu)
270 #define MCUX_CSSL_FP_FUNCID_nboot_key_store_export_key (0x6A4Eu)
271 #define MCUX_CSSL_FP_FUNCID_nboot_key_store_is_loaded (0x7744u)
272 #define MCUX_CSSL_FP_FUNCID_nboot_key_store_init (0x32BCu)
273 #define MCUX_CSSL_FP_FUNCID_nboot_key_store_generate_rom_key (0x259Du)
274 #define MCUX_CSSL_FP_FUNCID_nboot_cmac_authenticate_romapi (0x4CB5u)
275 #define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_manifest (0x76C4u)
276 #define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_block (0x36E4u)
277 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockVerify (0x1BA9u)
278 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDecrypt_Start (0x238Fu)
279 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockEncrypt_Start (0x785Au)
280 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockCrypt_Finish (0x478Bu)
281 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDeriveKey (0x54EAu)
282 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestImportPck (0x437Au)
283 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestDeriveKdk (0x732Cu)
284 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_DeletePck (0x5A5Au)
285 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Cleanup (0x4ED8u)
286 #define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa (0x6E62u)
287 #define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_romapi (0x2D99u)
288 #define MCUX_CSSL_FP_FUNCID_nboot_sb3_img_authenticate_ecdsa (0x5AC6u)
289 #define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_internal (0x4E65u)
290 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_none (0x5A4Bu)
291 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_ckdf (0x588Fu)
292 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveTwoScalars (0x28DEu)
293 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble_NIST (0x4EB4u)
294 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult_NIST (0x3672u)
295 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR_NIST (0x05E7u)
296 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd_NIST (0x629Bu)
297 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SwitchEndianness_P384 (0x7C8Au)
298 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_rts_insert_cert (0x0EBAu)
299 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetRandomStartDelay (0x134Fu)
300 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetRandomStartDelay (0x51C7u)
301 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLock (0x4AE6u)
302 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ReleaseLock (0x61D3u)
303 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_IsLocked (0x646Eu)
304 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetMasterUnlock (0x30B7u)
305 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_ConfigureCommandCRC (0x4CF1u)
306 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetCommandCRC (0x0B9Bu)
307 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_VerifyVsRefCRC (0x5C17u)
308 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_RespGen_Async (0x7256u)
309 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportBigEndianToPkc (0x5F30u)
310 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportBigEndianFromPkc (0x3D1Cu)
311 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify (0x5CA5u)
312 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SwitchEndianness (0x36A9u)
313 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR (0x65ACu)
314 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble (0x7986u)
315 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd (0x10FEu)
316 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult (0x59B4u)
317 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_RandomizeUPTRT (0x1D87u)
318 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ReRandomizeUPTRT (0x5E54u)
319 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SecurePointMult (0x03BDu)
320 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwVersion (0x0CCFu)
321 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwState (0x0B57u)
322 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntEnableFlags (0x176Au)
323 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntEnableFlags (0x346Bu)
324 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ResetIntFlags (0x3E29u)
325 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntFlags (0x5D2Au)
326 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Configuration (0x4EE2u)
327 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Lock (0x1177u)
328 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ConfigEval (0x28EEu)
329 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Enroll (0x31B6u)
330 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reconstruct (0x3C9Au)
331 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_KeyGeneration (0x3EC8u)
332 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntFlags (0x6AD4u)
333 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_img_authenticate_ecdsa (0x788Bu)
334 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_dev_set_wrap_data (0x5369u)
335 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge (0x4A6Du)
336 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_mcux (0x48D7u)
337 #define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_oem (0x12FCu)
338 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_TrailingZeros (0x037Eu)
339 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ReduceModEven (0x235Eu)
340 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_KeyGen (0x6726u)
341 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportBigEndianFromPkc (0x19E6u)
342 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_CoreKeyGen (0x5C87u)
343 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_ResetEventCounter (0x14EBu)
344 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_GetEventCounter (0x2D72u)
345 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportBigEndianToPkc (0x271Du)
346 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Sign (0x59A3u)
347 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointMult (0x5AD2u)
348 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_public (0x7469u)
349 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privatePlain (0x0E7Au)
350 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_verify (0x2D78u)
351 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noVerify (0x689Eu)
352 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_sign (0x50DBu)
353 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Verify (0x270Fu)
354 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivideOdd (0x509Fu)
355 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssVerify (0x69B2u)
356 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_mgf1 (0x7878u)
357 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privateCRT (0x69D2u)
358 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_sign (0x1C7Cu)
359 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noEncode (0x758Cu)
360 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssEncode (0x3C66u)
361 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SetupEnvironment (0x318Fu)
362 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_SetupEnvironment (0x6A39u)
363 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_SecureScalarMult_XZMontLadder (0x4D55u)
364 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_X (0x147Du)
365 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeScalar (0x5197u)
366 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeCoordinate (0x44F5u)
367 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_GenerateMultiplicativeBlinding (0x03BEu)
368 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLastDmaAddress (0x3E51u)
369 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_CompareDmaFinalOutputAddress (0x6A3Cu)
370 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyAgreement (0x6933u)
371 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyGeneration (0x097Eu)
372 #define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivide (0x3CE4u)
373 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_init (0x456Eu)
374 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_reseed (0x4CE9u)
375 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate (0x7D28u)
376 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_uninit (0x41FCu)
377 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_selftest (0x51E5u)
378 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_checkSecurityStrength (0x3B13u)
379 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncInit (0x4E8Bu)
380 #define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncGenerate (0x20DFu)
381 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPQDistance (0x345Bu)
382 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ModInv (0x178Eu)
383 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_MillerRabinTest (0x5F42u)
384 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ComputeD (0x6A36u)
385 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_VerifyE (0x53F0u)
386 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_GenerateProbablePrime (0x1ACEu)
387 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Crt (0x5F12u)
388 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_UpdateRefCRC (0x05BEu)
389 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPrimeCandidate (0x10EFu)
390 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Plain (0x58B6u)
391 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportLittleEndianToPkc (0x275Cu)
392 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportLittleEndianFromPkc (0x0BDAu)
393 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportLittleEndianToPkc (0x64F8u)
394 #define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportLittleEndianFromPkc (0x16E6u)
395 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_SetupEnvironment (0x54B3u)
396 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes (0x05B7u)
397 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_crypt (0x1BB2u)
398 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init (0x7683u)
399 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_process (0x61E6u)
400 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_finish (0x60EEu)
401 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_None (0x529Eu)
402 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Random (0x1B9Au)
403 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Decrypt (0x368Du)
404 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method1 (0x33C9u)
405 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method2 (0x15BAu)
406 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_PKCS7 (0x3974u)
407 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_None (0x5AA9u)
408 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Default (0x075Bu)
409 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method1 (0x61B9u)
410 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method2 (0x6D1Au)
411 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_PKCS7 (0x7923u)
412 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Stream (0x3C6Au)
413 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesGcm (0x6731u)
414 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_crypt (0x68BAu)
415 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_init (0x6EA1u)
416 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_process (0x3E89u)
417 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_process_adata (0x19D6u)
418 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_finish (0x21BEu)
419 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_verify (0x6D0Eu)
420 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesCcm (0x5633u)
421 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesCcmEls (0x25A7u)
422 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesGcmEls (0x3BA8u)
423 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_encrypt (0x5C65u)
424 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_decrypt (0x137Au)
425 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_encrypt (0x3B89u)
426 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_decrypt (0x2F0Eu)
427 #define MCUX_CSSL_FP_FUNCID_mcuxClTrng_getEntropyInput (0x34E5u)
428 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_generate (0x246Fu)
429 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_init (0x5A1Eu)
430 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_reseed (0x41E7u)
431 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_selftest (0x14DBu)
432 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm (0x517Cu)
433 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm (0x42FAu)
434 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_generatePrHandler (0x447Bu)
435 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm (0x54BAu)
436 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PTG3_selftestAlgorithm (0x435Du)
437 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateOutput (0x6D8Cu)
438 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_UpdateState (0x35A9u)
439 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_bcc (0x5B54u)
440 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_df (0x13E5u)
441 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_updateEntropyInput (0x525Eu)
442 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction (0x70DAu)
443 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction (0x5CCAu)
444 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createTestFromNormalMode (0x72C6u)
445 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction (0x327Au)
446 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction (0x3C33u)
447 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_DRBG_AES_Internal_blockcipher (0x5E98u)
448 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled (0x541Fu)
449 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction (0x4755u)
450 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm (0x22F5u)
451 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PTG3 (0x72A6u)
452 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction (0x6E2Au)
453 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction (0x20FEu)
454 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction (0x72A9u)
455 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction (0x6939u)
456 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createPatchMode (0x642Fu)
457 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_incV (0x09AFu)
458 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction (0x4BB2u)
459 #define MCUX_CSSL_FP_FUNCID_mcuxClTrng_Init (0x73D0u)
460 #define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reset (0x334Eu)
461 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_EngineEls (0x3B46u)
462 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair (0x2D6Au)
463 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature (0x43F4u)
464 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature (0x15DAu)
465 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_encrypt (0x3B70u)
466 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Decode_decrypt (0x56CCu)
467 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_SetupEnvironment (0x31CBu)
468 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateCustomKeyType (0x4D6Au)
469 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateDomainParams (0x321Fu)
470 #define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_MAC_ISO9797_1_Method2 (0x5857u)
471 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepEncode (0x6A27u)
472 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepDecode (0x2DC5u)
473 #define MCUX_CSSL_FP_FUNCID_mcuxClPrng_init (0x7346u)
474 #define MCUX_CSSL_FP_FUNCID_mcuxClPrng_generate (0x44F3u)
475 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RecodeAndReorderScalar (0x39E4u)
476 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_FixScalarMult (0x08EFu)
477 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult25519 (0x612Fu)
478 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectComb (0x0EAEu)
479 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd25519 (0x3E43u)
480 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd25519 (0x13EAu)
481 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectML (0x4D99u)
482 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_VarScalarMult (0x05BDu)
483 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainVarScalarMult (0x7C54u)
484 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PrecPointImportAndValidate (0x7323u)
485 #define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Ckdf (0x19E3u)
486 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_verify (0x72B8u)
487 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_crypt (0x0F78u)
488 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_finish (0x0E8Fu)
489 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process (0x1375u)
490 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_init (0x2A5Eu)
491 #define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process_adata (0x18D7u)
492 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateKeyPair (0x19D3u)
493 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_generate_keypair (0x5BC8u)
494 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_GenerateKeyPair (0x47A3u)
495 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_Public (0x195Bu)
496 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_UtilsAsym_ModularExponentiation (0x47F0u)
497 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcInitialize (0x294Fu)
498 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcDeinitialize (0x69C5u)
499 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_BlindedScalarMult (0x2AD9u)
500 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_BlindedScalarMult (0x76A8u)
501 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PointDecFct_SEC (0x3674u)
502 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_S5xyStub (0x0F96u)
503 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_S5xyStub (0x05F5u)
504 #define MCUX_CSSL_FP_FUNCID_mcuxClSignature_selftest (0x05F9u)
505 #define MCUX_CSSL_FP_FUNCID_mcuxClSignature_sign (0x08FEu)
506 #define MCUX_CSSL_FP_FUNCID_mcuxClSignature_verify (0x46DCu)
507 #define MCUX_CSSL_FP_FUNCID_mcuxClSignature_init (0x169Bu)
508 #define MCUX_CSSL_FP_FUNCID_mcuxClSignature_finish (0x61DCu)
509 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_selftest (0x3571u)
510 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_SetupEnvironment (0x132Fu)
511 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetVersionAndConfig (0x694Du)
512 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetStatus (0x346Du)
513 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SyncReset (0x3DC8u)
514 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntEnable (0x0F2Du)
515 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetIntEnable (0x683Bu)
516 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ClearIntStatus (0x6D94u)
517 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntStatus (0x15E9u)
518 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_Lock (0x68B5u)
519 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsLocked (0x5653u)
520 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsIndexLocked (0x3B19u)
521 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_StartEnable (0x725Au)
522 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ContinueEnable (0x0B5Bu)
523 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_LockIndex (0x30BBu)
524 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ResetIndex (0x1F19u)
525 #define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_EndOperation (0x17C9u)
526 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_CalcHashModN (0x1A79u)
527 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed25519 (0x6CA6u)
528 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed448 (0x58DAu)
529 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_InitPrivKeyInputMode (0x536Au)
530 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_setResource (0x3785u)
531 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_configure_job (0x761Cu)
532 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_request (0x559Au)
533 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_release (0x48EEu)
534 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_triggerUserCallback (0x1D36u)
535 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_init (0x7968u)
536 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_handle_interrupt (0x7634u)
537 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_request (0x23D5u)
538 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_release (0x78CCu)
539 #define MCUX_CSSL_FP_FUNCID_mcuxClTrng_checkConfig (0x471Du)
540 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_linkKeyPair (0x50F5u)
541 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithmeticOperation (0x61A7u)
542 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointAdd (0x0797u)
543 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_RemoveBlinding (0x6CE8u)
544 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_ScalarMult (0x599Cu)
545 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement_selftest (0x5939u)
546 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDH_KeyAgreement (0x10F7u)
547 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_encrypt (0x6279u)
548 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_decrypt (0x1F1Cu)
549 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_encrypt (0x5659u)
550 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_decrypt (0x119Fu)
551 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi (0x6C3Au)
552 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi (0x1DB8u)
553 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_encrypt_Sgi (0x4DD2u)
554 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_decrypt_Sgi (0x5EE0u)
555 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi (0x3374u)
556 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finish_Sgi (0x51ADu)
557 #define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_selftest_VerifyArrays (0x5D13u)
558 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveScalar (0x1FA2u)
559 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PrivateKeyValidation (0x0DEAu)
560 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PublicKeyValidation (0x2F32u)
561 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateHashPrefix (0x4957u)
562 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateProtocolDescriptor (0x19CEu)
563 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignatureModeDescriptor (0x5BC4u)
564 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_PreHashMessage (0x396Au)
565 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair_Core (0x436Bu)
566 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_Core (0x47E8u)
567 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_Core (0x57A1u)
568 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_GenerateSignature (0x3CCAu)
569 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_VerifySignature (0x5574u)
570 #define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed (0x37D0u)
571 #define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointSub (0x395Cu)
572 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation (0x3B2Au)
573 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_108 (0x784Eu)
574 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_108 (0x3D38u)
575 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ISOIEC_18033_2 (0x1A3Bu)
576 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ISOIEC_18033_2 (0x15CEu)
577 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_56C (0x45E3u)
578 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_OneStep (0x7E84u)
579 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_TwoStep (0x4CDAu)
580 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ANSI_X9_63 (0x4E5Cu)
581 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ANSI_X9_63 (0x115Fu)
582 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_HKDF (0x6786u)
583 #define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_HKDF (0x54B6u)
584 #define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_Randombytes (0x2D1Eu)
585 #define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_XOF_Hash (0x78D1u)
586 #define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Init_And_Absorb (0x2CCBu)
587 #define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Absorb (0x64F4u)
588 #define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Squeeze (0x6C1Eu)
589 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair (0x307Bu)
590 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Sign (0x6DE0u)
591 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Verify (0x24EDu)
592 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_Verify_checkInputs (0x6786u)
593 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_computeMu (0x54B6u)
594 #define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_performPolynomialArithmetic (0x58DAu)
595 #define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed (0x7B41u)
596 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcInitialize (0x3DA2u)
597 #define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcDeinitialize (0x1CB5u)
598 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_backup (0x23E9u)
599 #define MCUX_CSSL_FP_FUNCID_mcuxClResource_restore (0x652Du)
600 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_resume (0x3AB4u)
601 #define MCUX_CSSL_FP_FUNCID_mcuxClMac_selftest (0x42AFu)
602 #define MCUX_CSSL_FP_FUNCID_mcuxClAead_selftest (0x24AFu)
603 #define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC16 (0x425Fu)
604 #define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC32 (0x4B39u)
605 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_verifyContextCrc (0x2C7Cu)
606 #define MCUX_CSSL_FP_FUNCID_mcuxClCipher_computeContextCrc (0x325Eu)
607 #define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC32 (0x4EE1u)
608 #define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC16 (0x706Eu)
609 #define MCUX_CSSL_FP_FUNCID_mcuxClKem_encapsulate (0x15D3u)
610 #define MCUX_CSSL_FP_FUNCID_mcuxClKem_decapsulate (0x05DEu)
611 #define MCUX_CSSL_FP_FUNCID_mcuxClKyber_KeyGen (0x1B99u)
612 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi_nonBlocking (0x474Eu)
613 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi_nonBlocking (0x4BC9u)
614 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_setWa (0x2CD5u)
615 #define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_getWa (0x18F5u)
616 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi_nonBlocking (0x7790u)
617 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Multipart (0x1A6Eu)
618 #define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Oneshot (0x75C1u)
619 #define MCUX_CSSL_FP_FUNCID_mcuxClLtc_BackupStatus (0x1697u)
620 #define MCUX_CSSL_FP_FUNCID_mcuxClLtc_RestoreStatus (0x135Eu)
621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_180 (0x4FA4u)
622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_181 (0x243Fu)
623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_182 (0x1F16u)
624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_183 (0x683Eu)
625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_184 (0x6E31u)
626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_185 (0x623Eu)
627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_186 (0x47E1u)
628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_187 (0x53C9u)
629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_188 (0x6535u)
630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_189 (0x2697u)
631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_190 (0x07E9u)
632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_191 (0x599Au)
633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_192 (0x2B93u)
634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_193 (0x4AF1u)
635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_194 (0x2C5Eu)
636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_195 (0x518Fu)
637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_196 (0x738Au)
638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_197 (0x49E3u)
639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_198 (0x43BAu)
640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_199 (0x296Eu)
641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_200 (0x54F2u)
642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_201 (0x2B36u)
643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_202 (0x58C7u)
644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_203 (0x7632u)
645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_204 (0x2B78u)
646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_205 (0x5CF0u)
647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_206 (0x1C75u)
648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_207 (0x39A3u)
649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_208 (0x5E2Au)
650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_209 (0x728Du)
651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_210 (0x5D2Cu)
652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_211 (0x6399u)
653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_212 (0x724Bu)
654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_213 (0x53A3u)
655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_214 (0x1D2Bu)
656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_215 (0x5726u)
657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_216 (0x03B7u)
658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_217 (0x0D37u)
659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_218 (0x362Du)
660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_219 (0x4AE3u)
661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_220 (0x4BD8u)
662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_221 (0x7945u)
663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_222 (0x5B34u)
664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_223 (0x749Cu)
665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_224 (0x4D56u)
666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_225 (0x1D53u)
667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_226 (0x1573u)
668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_227 (0x78C6u)
669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_228 (0x4C6Eu)
670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_229 (0x65D2u)
671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_230 (0x5599u)
672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_231 (0x4EE8u)
673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_232 (0x256Eu)
674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_233 (0x2CB6u)
675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_234 (0x4753u)
676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_235 (0x0E6Bu)
677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_236 (0x52DAu)
678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_237 (0x2F70u)
679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_238 (0x1877u)
680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_239 (0x5CAAu)
681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_240 (0x325Du)
682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_241 (0x11AFu)
683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_242 (0x63B2u)
684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_243 (0x5917u)
685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_244 (0x2D95u)
686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_245 (0x1EC5u)
687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_246 (0x27ACu)
688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_247 (0x1CBCu)
689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_248 (0x037Du)
690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_249 (0x4BC5u)
691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_250 (0x4A6Bu)
692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_251 (0x7856u)
693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_252 (0x5BA4u)
694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_253 (0x6B92u)
695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_254 (0x32E6u)
696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_255 (0x2F1Au)
697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_256 (0x136Eu)
698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_257 (0x2C6Eu)
699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_258 (0x356Cu)
700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_259 (0x46ADu)
701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_260 (0x319Eu)
702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_261 (0x5B2Au)
703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_262 (0x1BCCu)
704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_263 (0x33A6u)
705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_264 (0x2B59u)
706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_265 (0x6E07u)
707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_266 (0x529Du)
708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_267 (0x1B95u)
709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_268 (0x78CAu)
710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_269 (0x21F9u)
711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_270 (0x549Eu)
712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_271 (0x0BF8u)
713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_272 (0x6CA3u)
714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_273 (0x4575u)
715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_274 (0x06FCu)
716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_275 (0x1B33u)
717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_276 (0x4CB9u)
718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_277 (0x3D70u)
719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_278 (0x632Bu)
720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_279 (0x2C4Fu)
721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_280 (0x51B6u)
722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_281 (0x459Du)
723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_282 (0x6AAAu)
724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_283 (0x19ECu)
725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_284 (0x7B84u)
726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_285 (0x53ACu)
727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_286 (0x3B25u)
728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_287 (0x2D33u)
729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_288 (0x3A66u)
730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_289 (0x5D86u)
731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_290 (0x3A0Fu)
732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_291 (0x6F12u)
733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_292 (0x6633u)
734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_293 (0x5E0Du)
735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_294 (0x253Eu)
736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_295 (0x1D39u)
737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_296 (0x06CFu)
738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_297 (0x3A4Du)
739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_298 (0x7C0Bu)
740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_299 (0x7172u)
741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_300 (0x2B56u)
742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_301 (0x24DEu)
743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_302 (0x46F1u)
744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_303 (0x3C9Cu)
745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_304 (0x731Cu)
746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_305 (0x5A2Du)
747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_306 (0x117Du)
748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_307 (0x6785u)
749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_308 (0x53E8u)
750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_309 (0x3596u)
751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_310 (0x03BBu)
752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_311 (0x3CE1u)
753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_312 (0x54D3u)
754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_313 (0x362Bu)
755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_314 (0x530Fu)
756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_315 (0x7A32u)
757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_316 (0x3475u)
758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_317 (0x61CEu)
759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_318 (0x668Bu)
760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_319 (0x5876u)
761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_320 (0x549Bu)
762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_321 (0x721Eu)
763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_322 (0x3578u)
764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_323 (0x2A3Eu)
765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_324 (0x63C5u)
766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_325 (0x4ED4u)
767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_326 (0x2ABCu)
768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_327 (0x231Fu)
769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_328 (0x1EE2u)
770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_329 (0x0E73u)
771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_330 (0x29DCu)
772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_331 (0x5A2Bu)
773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_332 (0x48FCu)
774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_333 (0x35AAu)
775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_334 (0x2D74u)
776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_335 (0x3B8Au)
777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_336 (0x0577u)
778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_337 (0x6D58u)
779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_338 (0x7929u)
780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_339 (0x6E0Bu)
781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_340 (0x47D1u)
782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_341 (0x4E4Bu)
783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_342 (0x6F0Cu)
784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_343 (0x4F15u)
785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_344 (0x7D60u)
786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_345 (0x32C7u)
787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_346 (0x685Eu)
788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_347 (0x1ED4u)
789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_348 (0x4EA6u)
790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_349 (0x27B4u)
791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_350 (0x1C9Eu)
792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_351 (0x45CDu)
793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_352 (0x38CDu)
794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_353 (0x3A55u)
795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_354 (0x5536u)
796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_355 (0x5E29u)
797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_356 (0x427Eu)
798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_357 (0x5D52u)
799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_358 (0x272Bu)
800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_359 (0x05EDu)
801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_360 (0x2D8Bu)
802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_361 (0x3F28u)
803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_362 (0x32F2u)
804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_363 (0x70ECu)
805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_364 (0x28BDu)
806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_365 (0x74C3u)
807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_366 (0x3663u)
808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_367 (0x266Bu)
809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_368 (0x1EB2u)
810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_369 (0x395Au)
811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_370 (0x6A96u)
812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_371 (0x08FBu)
813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_372 (0x0CDEu)
814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_373 (0x4F0Bu)
815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_374 (0x2FA8u)
816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_375 (0x4D27u)
817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_376 (0x2B47u)
818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_377 (0x2CC7u)
819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_378 (0x507Bu)
820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_379 (0x6A56u)
821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_380 (0x7DA0u)
822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_381 (0x25DAu)
823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_382 (0x371Au)
824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_383 (0x5E86u)
825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_384 (0x1EE4u)
826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_385 (0x52B3u)
827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_386 (0x17D2u)
828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_387 (0x370Du)
829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_388 (0x5AB8u)
830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_389 (0x11FCu)
831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_390 (0x6C2Eu)
832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_391 (0x28F9u)
833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_392 (0x6C8Eu)
834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_393 (0x71CAu)
835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_394 (0x12BEu)
836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_395 (0x529Bu)
837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_396 (0x07ABu)
838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_397 (0x5336u)
839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_398 (0x40DFu)
840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_399 (0x59B2u)
841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_400 (0x7784u)
842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_401 (0x5966u)
843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_402 (0x2973u)
844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_403 (0x15ECu)
845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_404 (0x36AAu)
846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_405 (0x0ADBu)
847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_406 (0x173Cu)
848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_407 (0x3999u)
849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_408 (0x5A95u)
850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_409 (0x4B2Du)
851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_410 (0x46D3u)
852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_411 (0x519Bu)
853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_412 (0x646Du)
854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_413 (0x0F1Bu)
855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_414 (0x0ABBu)
856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_415 (0x571Cu)
857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_416 (0x59C5u)
858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_417 (0x334Du)
859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_418 (0x7827u)
860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_419 (0x29B5u)
861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_420 (0x2CCDu)
862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_421 (0x37C2u)
863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_422 (0x0DBCu)
864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_423 (0x7435u)
865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_424 (0x66E1u)
866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_425 (0x49F2u)
867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_426 (0x7926u)
868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_427 (0x5C96u)
869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_428 (0x45AEu)
870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_429 (0x185Fu)
871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_430 (0x38CEu)
872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_431 (0x619Bu)
873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_432 (0x3927u)
874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_433 (0x38D3u)
875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_434 (0x67C8u)
876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_435 (0x5E1Cu)
877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_436 (0x73A4u)
878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_437 (0x71F0u)
879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_438 (0x435Eu)
880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_439 (0x651Eu)
881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_440 (0x7B24u)
882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_441 (0x625Bu)
883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_442 (0x53AAu)
884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_443 (0x11D7u)
885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_444 (0x5789u)
886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_445 (0x3E62u)
887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_446 (0x623Du)
888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_447 (0x7895u)
889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_448 (0x7370u)
890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_449 (0x2D71u)
891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_450 (0x1C2Fu)
892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_451 (0x5D1Au)
893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_452 (0x5F22u)
894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_453 (0x46F4u)
895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_454 (0x1CD5u)
896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_455 (0x4CADu)
897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_456 (0x558Du)
898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_457 (0x153Bu)
899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_458 (0x26E3u)
900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_459 (0x1DC3u)
901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_460 (0x307Eu)
902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_461 (0x2537u)
903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_462 (0x3AA3u)
904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_463 (0x6D86u)
905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_464 (0x67A2u)
906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_465 (0x52F4u)
907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_466 (0x09F3u)
908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_467 (0x6DC8u)
909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_468 (0x5E1Au)
910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_469 (0x7A86u)
911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_470 (0x2D47u)
912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_471 (0x09EBu)
913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_472 (0x1D27u)
914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_473 (0x68EAu)
915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_474 (0x29D6u)
916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_475 (0x66B1u)
917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_476 (0x1537u)
918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_477 (0x6F05u)
919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_478 (0x4CF4u)
920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_479 (0x1D3Cu)
921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_480 (0x15D6u)
922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_481 (0x6173u)
923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_482 (0x04BFu)
924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_483 (0x4B47u)
925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_484 (0x07B6u)
926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_485 (0x3AD2u)
927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_486 (0x638Du)
928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_487 (0x3953u)
929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_488 (0x7135u)
930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_489 (0x585Eu)
931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_490 (0x43CDu)
932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_491 (0x2B74u)
933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_492 (0x6569u)
934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_493 (0x4C6Du)
935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_494 (0x0737u)
936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_495 (0x7916u)
937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_496 (0x28BEu)
938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_497 (0x2557u)
939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_498 (0x609Fu)
940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_499 (0x691Du)
941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_500 (0x31E9u)
942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_501 (0x3A53u)
943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_502 (0x7658u)
944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_503 (0x5C59u)
945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_504 (0x6725u)
946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_505 (0x7A38u)
947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_506 (0x3356u)
948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_507 (0x6696u)
949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_508 (0x52ECu)
950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_509 (0x4F49u)
951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_510 (0x2799u)
952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_511 (0x2E17u)
953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_512 (0x2AD6u)
954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_513 (0x524Fu)
955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_514 (0x7561u)
956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_515 (0x4D8Bu)
957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_516 (0x0CF6u)
958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_517 (0x39B1u)
959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_518 (0x45BCu)
960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_519 (0x5665u)
961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_520 (0x70E3u)
962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_521 (0x2EB2u)
963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_522 (0x06D7u)
964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_523 (0x5E45u)
965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_524 (0x72D1u)
966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_525 (0x129Fu)
967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_526 (0x21BBu)
968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_527 (0x0D5Bu)
969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_528 (0x0F3Au)
970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_529 (0x131Fu)
971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_530 (0x539Cu)
972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_531 (0x7D06u)
973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_532 (0x47D4u)
974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_533 (0x25D5u)
975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_534 (0x13F8u)
976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_535 (0x14F3u)
977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_536 (0x2759u)
978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_537 (0x7994u)
979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_538 (0x45B6u)
980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_539 (0x38C7u)
981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_540 (0x52DCu)
982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_541 (0x29ADu)
983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_542 (0x6B29u)
984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_543 (0x5476u)
985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_544 (0x467Au)
986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_545 (0x49BCu)
987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_546 (0x40EFu)
988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_547 (0x6B8Cu)
989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_548 (0x28EDu)
990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_549 (0x11F9u)
991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_550 (0x5C1Eu)
992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_551 (0x7998u)
993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_552 (0x7887u)
994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_553 (0x30BDu)
995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_554 (0x0DF8u)
996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_555 (0x3257u)
997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_556 (0x6D2Au)
998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_557 (0x670Du)
999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_558 (0x04FEu)
1000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_559 (0x6E25u)
1001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_560 (0x52B5u)
1002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_561 (0x1F34u)
1003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_562 (0x1AB5u)
1004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_563 (0x4E56u)
1005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_564 (0x53D4u)
1006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_565 (0x70ABu)
1007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_566 (0x3B4Cu)
1008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_567 (0x5176u)
1009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_568 (0x4DF0u)
1010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_569 (0x29AEu)
1011 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_570 (0x3955u)
1012 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_571 (0x7A1Cu)
1013 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_572 (0x1C6Eu)
1014 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_573 (0x053Fu)
1015 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_574 (0x499Bu)
1016 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_575 (0x23B9u)
1017 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_576 (0x6A35u)
1018 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_577 (0x4F16u)
1019 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_578 (0x0BC7u)
1020 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_579 (0x13ADu)
1021 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_580 (0x5437u)
1022 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_581 (0x51DCu)
1023 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_582 (0x27E1u)
1024 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_583 (0x3D29u)
1025 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_584 (0x6137u)
1026 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_585 (0x64CEu)
1027 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_586 (0x4C8Fu)
1028 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_587 (0x45F1u)
1029 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_588 (0x07D5u)
1030 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_589 (0x551Bu)
1031 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_590 (0x3AD1u)
1032 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_591 (0x5EC2u)
1033 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_592 (0x63B8u)
1034 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_593 (0x4B2Eu)
1035 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_594 (0x1E1Bu)
1036 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_595 (0x53A6u)
1037 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_596 (0x34DAu)
1038 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_597 (0x11FAu)
1039 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_598 (0x3A95u)
1040 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_599 (0x6D51u)
1041 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_600 (0x56C3u)
1042 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_601 (0x64D5u)
1043 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_602 (0x633Au)
1044 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_603 (0x2B1Bu)
1045 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_604 (0x255Du)
1046 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_605 (0x764Cu)
1047 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_606 (0x0B6Du)
1048 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_607 (0x63ACu)
1049 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_608 (0x7F02u)
1050 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_609 (0x0F35u)
1051 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_610 (0x1B2Du)
1052 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_611 (0x0ABEu)
1053 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_612 (0x4CCBu)
1054 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_613 (0x7554u)
1055 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_614 (0x5639u)
1056 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_615 (0x6758u)
1057 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_616 (0x30F9u)
1058 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_617 (0x0FB1u)
1059 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_618 (0x30EBu)
1060 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_619 (0x4C5Du)
1061 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_620 (0x61D9u)
1062 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_621 (0x5C9Au)
1063 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_622 (0x7D11u)
1064 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_623 (0x6F81u)
1065 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_624 (0x3A59u)
1066 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_625 (0x383Eu)
1067 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_626 (0x3B4Au)
1068 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_627 (0x3AB1u)
1069 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_628 (0x1CE9u)
1070 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_629 (0x372Au)
1071 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_630 (0x3745u)
1072 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_631 (0x7938u)
1073 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_632 (0x55D4u)
1074 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_633 (0x21F3u)
1075 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_634 (0x1B65u)
1076 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_635 (0x4D6Cu)
1077 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_636 (0x54B5u)
1078 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_637 (0x7136u)
1079 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_638 (0x5DA2u)
1080 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_639 (0x52BCu)
1081 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_640 (0x3D92u)
1082 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_641 (0x20FDu)
1083 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_642 (0x43CEu)
1084 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_643 (0x4C75u)
1085 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_644 (0x2B33u)
1086 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_645 (0x0EADu)
1087 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_646 (0x1ED1u)
1088 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_647 (0x34BAu)
1089 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_648 (0x4DE2u)
1090 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_649 (0x13F2u)
1091 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_650 (0x6D43u)
1092 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_651 (0x60F9u)
1093 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_652 (0x519Eu)
1094 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_653 (0x0DBAu)
1095 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_654 (0x43DAu)
1096 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_655 (0x03AFu)
1097 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_656 (0x6E61u)
1098 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_657 (0x64B9u)
1099 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_658 (0x2A9Eu)
1100 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_659 (0x3659u)
1101 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_660 (0x6CD4u)
1102 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_661 (0x17B8u)
1103 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_662 (0x0E2Fu)
1104 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_663 (0x6179u)
1105 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_664 (0x14FCu)
1106 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_665 (0x1D5Cu)
1107 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_666 (0x5CC5u)
1108 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_667 (0x4EA3u)
1109 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_668 (0x097Bu)
1110 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_669 (0x33E2u)
1111 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_670 (0x68F4u)
1112 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_671 (0x5B25u)
1113 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_672 (0x6473u)
1114 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_673 (0x5479u)
1115 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_674 (0x2771u)
1116 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_675 (0x0A7Du)
1117 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_676 (0x61AEu)
1118 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_677 (0x3D4Cu)
1119 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_678 (0x13CEu)
1120 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_679 (0x0C5Fu)
1121 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_680 (0x35E8u)
1122 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_681 (0x19F4u)
1123 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_682 (0x7A54u)
1124 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_683 (0x760Bu)
1125 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_684 (0x1FA8u)
1126 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_685 (0x1F64u)
1127 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_686 (0x36B2u)
1128 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_687 (0x0A9Fu)
1129 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_688 (0x54E9u)
1130 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_689 (0x6CC3u)
1131 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_690 (0x3792u)
1132 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_691 (0x4766u)
1133 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_692 (0x69B4u)
1134 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_693 (0x48B7u)
1135 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_694 (0x3719u)
1136 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_695 (0x3F06u)
1137 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_696 (0x715Cu)
1138 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_697 (0x12DEu)
1139 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_698 (0x721Du)
1140 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_699 (0x1D65u)
1141 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_700 (0x2736u)
1142 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_701 (0x29D3u)
1143 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_702 (0x1CDCu)
1144 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_703 (0x1D1Eu)
1145 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_704 (0x29D9u)
1146 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_705 (0x5D64u)
1147 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_706 (0x30FCu)
1148 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_707 (0x63B1u)
1149 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_708 (0x2FC1u)
1150 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_709 (0x1F29u)
1151 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_710 (0x4D65u)
1152 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_711 (0x7AC4u)
1153 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_712 (0x0DDAu)
1154 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_713 (0x38ECu)
1155 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_714 (0x56A6u)
1156 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_715 (0x1CE3u)
1157 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_716 (0x0DE9u)
1158 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_717 (0x5553u)
1159 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_718 (0x7E24u)
1160 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_719 (0x3B32u)
1161 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_720 (0x7C62u)
1162 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_721 (0x61C7u)
1163 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_722 (0x3D8Cu)
1164 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_723 (0x4FC4u)
1165 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_724 (0x61EAu)
1166 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_725 (0x3B86u)
1167 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_726 (0x19BCu)
1168 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_727 (0x43B3u)
1169 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_728 (0x1D8Du)
1170 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_729 (0x4E35u)
1171 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_730 (0x7C23u)
1172 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_731 (0x734Au)
1173 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_732 (0x3327u)
1174 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_733 (0x6716u)
1175 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_734 (0x707Au)
1176 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_735 (0x3897u)
1177 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_736 (0x4F43u)
1178 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_737 (0x3723u)
1179 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_738 (0x5A36u)
1180 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_739 (0x333Au)
1181 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_740 (0x6C99u)
1182 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_741 (0x15ABu)
1183 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_742 (0x1DCCu)
1184 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_743 (0x538Du)
1185 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_744 (0x6C5Au)
1186 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_745 (0x53D1u)
1187 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_746 (0x5E46u)
1188 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_747 (0x5E0Eu)
1189 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_748 (0x233Bu)
1190 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_749 (0x686Eu)
1191 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_750 (0x1B3Cu)
1192 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_751 (0x691Eu)
1193 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_752 (0x50BDu)
1194 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_753 (0x46D9u)
1195 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_754 (0x2DB8u)
1196 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_755 (0x154Fu)
1197 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_756 (0x6BC2u)
1198 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_757 (0x0FB8u)
1199 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_758 (0x3DC4u)
1200 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_759 (0x44D7u)
1201 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_760 (0x3DE0u)
1202 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_761 (0x7463u)
1203 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_762 (0x39CCu)
1204 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_763 (0x643Eu)
1205 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_764 (0x4AB6u)
1206 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_765 (0x495Du)
1207 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_766 (0x5CD2u)
1208 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_767 (0x6C65u)
1209 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_768 (0x34B5u)
1210 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_769 (0x781Eu)
1211 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_770 (0x67C2u)
1212 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_771 (0x7259u)
1213 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_772 (0x5C93u)
1214 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_773 (0x1AB6u)
1215 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_774 (0x2DD4u)
1216 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_775 (0x076Eu)
1217 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_776 (0x19E9u)
1218 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_777 (0x47D2u)
1219 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_778 (0x5672u)
1220 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_779 (0x476Au)
1221 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_780 (0x15B5u)
1222 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_781 (0x1B69u)
1223 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_782 (0x53B2u)
1224 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_783 (0x29E9u)
1225 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_784 (0x5B62u)
1226 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_785 (0x316Eu)
1227 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_786 (0x5897u)
1228 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_787 (0x6ACAu)
1229 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_788 (0x235Bu)
1230 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_789 (0x1F0Bu)
1231 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_790 (0x618Fu)
1232 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_791 (0x0DADu)
1233 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_792 (0x7A94u)
1234 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_793 (0x78D2u)
1235 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_794 (0x7949u)
1236 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_795 (0x5B51u)
1237 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_796 (0x1B2Eu)
1238 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_797 (0x116Fu)
1239 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_798 (0x386Eu)
1240 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_799 (0x5BE0u)
1241 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_800 (0x4EC9u)
1242 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_801 (0x505Fu)
1243 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_802 (0x4675u)
1244 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_803 (0x305Fu)
1245 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_804 (0x7E90u)
1246 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_805 (0x5969u)
1247 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_806 (0x7AA2u)
1248 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_807 (0x4BC6u)
1249 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_808 (0x2379u)
1250 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_809 (0x23B3u)
1251 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_810 (0x7CC2u)
1252 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_811 (0x715Au)
1253 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_812 (0x2B53u)
1254 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_813 (0x1579u)
1255 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_814 (0x4657u)
1256 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_815 (0x6AC6u)
1257 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_816 (0x4E1Bu)
1258 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_817 (0x7724u)
1259 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_818 (0x52CBu)
1260 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_819 (0x495Eu)
1261 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_820 (0x1B5Cu)
1262 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_821 (0x682Fu)
1263 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_822 (0x32DAu)
1264 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_823 (0x133Bu)
1265 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_824 (0x0EF1u)
1266 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_825 (0x5B89u)
1267 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_826 (0x0FA3u)
1268 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_827 (0x4CD9u)
1269 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_828 (0x479Cu)
1270 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_829 (0x6363u)
1271 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_830 (0x4D74u)
1272 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_831 (0x18EDu)
1273 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_832 (0x748Eu)
1274 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_833 (0x3A3Cu)
1275 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_834 (0x5D49u)
1276 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_835 (0x198Fu)
1277 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_836 (0x762Au)
1278 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_837 (0x0BD6u)
1279 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_838 (0x2F34u)
1280 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_839 (0x75D0u)
1281 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_840 (0x1D78u)
1282 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_841 (0x62A7u)
1283 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_842 (0x4F68u)
1284 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_843 (0x5791u)
1285 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_844 (0x39D8u)
1286 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_845 (0x285Fu)
1287 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_846 (0x6E86u)
1288 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_847 (0x05EBu)
1289 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_848 (0x59C3u)
1290 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_849 (0x5BC2u)
1291 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_850 (0x740Fu)
1292 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_851 (0x0E76u)
1293 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_852 (0x157Cu)
1294 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_853 (0x6B0Du)
1295 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_854 (0x6A47u)
1296 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_855 (0x0E3Eu)
1297 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_856 (0x7638u)
1298 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_857 (0x24E7u)
1299 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_858 (0x0D6Du)
1300 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_859 (0x5517u)
1301 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_860 (0x30D7u)
1302 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_861 (0x1D59u)
1303 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_862 (0x57E0u)
1304 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_863 (0x745Cu)
1305 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_864 (0x43D5u)
1306 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_865 (0x3B58u)
1307 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_866 (0x730Du)
1308 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_867 (0x75C8u)
1309 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_868 (0x278Eu)
1310 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_869 (0x54ADu)
1311 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_870 (0x0AEDu)
1312 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_871 (0x46CBu)
1313 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_872 (0x56D4u)
1314 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_873 (0x5CB8u)
1315 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_874 (0x317Au)
1316 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_875 (0x73C8u)
1317 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_876 (0x2BB4u)
1318 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_877 (0x079Eu)
1319 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_878 (0x31CEu)
1320 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_879 (0x47CAu)
1321 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_880 (0x2AB3u)
1322 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_881 (0x52E9u)
1323 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_882 (0x5CA6u)
1324 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_883 (0x16F1u)
1325 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_884 (0x5713u)
1326 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_885 (0x6B86u)
1327 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_886 (0x5A93u)
1328 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_887 (0x66E4u)
1329 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_888 (0x5257u)
1330 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_889 (0x3B34u)
1331 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_890 (0x0CB7u)
1332 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_891 (0x6335u)
1333 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_892 (0x1D93u)
1334 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_893 (0x38B3u)
1335 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_894 (0x4F8Au)
1336 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_895 (0x2E2Du)
1337 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_896 (0x7A51u)
1338 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_897 (0x56AAu)
1339 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_898 (0x1BD2u)
1340 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_899 (0x1AF8u)
1341 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_900 (0x1975u)
1342 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_901 (0x2CB5u)
1343 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_902 (0x11BEu)
1344 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_903 (0x681Fu)
1345 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_904 (0x5E23u)
1346 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_905 (0x7AB0u)
1347 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_906 (0x7534u)
1348 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_907 (0x3DC1u)
1349 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_908 (0x655Cu)
1350 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_909 (0x4B1Bu)
1351 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_910 (0x70CBu)
1352 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_911 (0x1E66u)
1353 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_912 (0x556Cu)
1354 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_913 (0x5B07u)
1355 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_914 (0x390Fu)
1356 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_915 (0x4DCCu)
1357 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_916 (0x596Cu)
1358 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_917 (0x1AECu)
1359 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_918 (0x41DBu)
1360 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_919 (0x5617u)
1361 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_920 (0x5C4Du)
1362 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_921 (0x4F23u)
1363 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_922 (0x662Du)
1364 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_923 (0x24FAu)
1365 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_924 (0x0E4Fu)
1366 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_925 (0x62F4u)
1367 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_926 (0x35CCu)
1368 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_927 (0x68E9u)
1369 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_928 (0x7D81u)
1370 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_929 (0x58E3u)
1371 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_930 (0x1C97u)
1372 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_931 (0x25B9u)
1373 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_932 (0x0AD7u)
1374 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_933 (0x39C9u)
1375 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_934 (0x3C27u)
1376 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_935 (0x28F3u)
1377 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_936 (0x175Cu)
1378 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_937 (0x39A6u)
1379 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_938 (0x2375u)
1380 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_939 (0x3699u)
1381 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_940 (0x3D43u)
1382 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_941 (0x70B3u)
1383 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_942 (0x34E9u)
1384 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_943 (0x4FC8u)
1385 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_944 (0x03FAu)
1386 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_945 (0x5AACu)
1387 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_946 (0x46EAu)
1388 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_947 (0x065Fu)
1389 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_948 (0x49CBu)
1390 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_949 (0x64C7u)
1391 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_950 (0x6393u)
1392 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_951 (0x392Eu)
1393 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_952 (0x16DCu)
1394 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_953 (0x0BB3u)
1395 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_954 (0x591Du)
1396 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_955 (0x4C6Bu)
1397 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_956 (0x4C7Cu)
1398 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_957 (0x1E99u)
1399 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_958 (0x14E7u)
1400 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_959 (0x3479u)
1401 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_960 (0x5CB2u)
1402 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_961 (0x0ECBu)
1403 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_962 (0x748Du)
1404 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_963 (0x23F1u)
1405 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_964 (0x5B68u)
1406 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_965 (0x6CD2u)
1407 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_966 (0x4B93u)
1408 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_967 (0x712Bu)
1409 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_968 (0x19DAu)
1410 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_969 (0x4C76u)
1411 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_970 (0x6356u)
1412 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_971 (0x41F9u)
1413 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_972 (0x30FAu)
1414 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_973 (0x6B4Au)
1415 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_974 (0x55D8u)
1416 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_975 (0x2C2Fu)
1417 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_976 (0x5A9Au)
1418 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_977 (0x5CD4u)
1419 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_978 (0x23E5u)
1420 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_979 (0x6C17u)
1421 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_980 (0x5C8Bu)
1422 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_981 (0x7934u)
1423 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_982 (0x526Bu)
1424 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_983 (0x1B59u)
1425 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_984 (0x694Bu)
1426 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_985 (0x1E55u)
1427 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_986 (0x163Bu)
1428 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_987 (0x6F41u)
1429 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_988 (0x06DBu)
1430 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_989 (0x5D94u)
1431 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_990 (0x2A9Du)
1432 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_991 (0x6636u)
1433 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_992 (0x5C6Cu)
1434 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_993 (0x4AB9u)
1435 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_994 (0x0DCBu)
1436 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_995 (0x7A25u)
1437 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_996 (0x3E52u)
1438 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_997 (0x7361u)
1439 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_998 (0x4576u)
1440 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_999 (0x25E6u)
1441 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1000 (0x60CFu)
1442 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1001 (0x5B31u)
1443 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1002 (0x16AEu)
1444 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1003 (0x1AC7u)
1445 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1004 (0x3AA6u)
1446 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1005 (0x6C95u)
1447 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1006 (0x7159u)
1448 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1007 (0x7C4Au)
1449 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1008 (0x4733u)
1450 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1009 (0x4567u)
1451 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1010 (0x38B6u)
1452 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1011 (0x24F6u)
1453 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1012 (0x724Du)
1454 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1013 (0x6AB4u)
1455 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1014 (0x5A69u)
1456 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1015 (0x72AAu)
1457 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1016 (0x7643u)
1458 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1017 (0x2C6Bu)
1459 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1018 (0x25C7u)
1460 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1019 (0x3A87u)
1461 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1020 (0x225Fu)
1462 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1021 (0x6D16u)
1463 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1022 (0x35ACu)
1464 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1023 (0x3E91u)
1465 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1024 (0x789Au)
1466 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1025 (0x7B0Au)
1467 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1026 (0x12F3u)
1468 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1027 (0x34F1u)
1469 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1028 (0x7C86u)
1470 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1029 (0x56E4u)
1471 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1030 (0x569Cu)
1472 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1031 (0x3AC3u)
1473 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1032 (0x3339u)
1474 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1033 (0x1957u)
1475 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1034 (0x5563u)
1476 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1035 (0x6A71u)
1477 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1036 (0x55B8u)
1478 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1037 (0x1DD2u)
1479 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1038 (0x499Du)
1480 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1039 (0x3359u)
1481 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1040 (0x2AD3u)
1482 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1041 (0x592Du)
1483 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1042 (0x5E4Au)
1484 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1043 (0x0F8Eu)
1485 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1044 (0x6D49u)
1486 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1045 (0x6B58u)
1487 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1046 (0x34D6u)
1488 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1047 (0x16F2u)
1489 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1048 (0x2D6Cu)
1490 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1049 (0x239Du)
1491 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1050 (0x16D3u)
1492 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1051 (0x58BCu)
1493 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1052 (0x44FAu)
1494 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1053 (0x359Au)
1495 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1054 (0x6D91u)
1496 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1055 (0x4D2Bu)
1497 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1056 (0x1E4Bu)
1498 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1057 (0x33B2u)
1499 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1058 (0x1CBAu)
1500 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1059 (0x7278u)
1501 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1060 (0x3B29u)
1502 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1061 (0x7447u)
1503 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1062 (0x4E99u)
1504 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1063 (0x78E1u)
1505 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1064 (0x58F1u)
1506 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1065 (0x750Du)
1507 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1066 (0x7E09u)
1508 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1067 (0x14CFu)
1509 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1068 (0x1DB2u)
1510 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1069 (0x615Du)
1511 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1070 (0x3B8Cu)
1512 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1071 (0x58F8u)
1513 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1072 (0x2AB6u)
1514 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1073 (0x6B25u)
1515 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1074 (0x0C77u)
1516 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1075 (0x5972u)
1517 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1076 (0x13AEu)
1518 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1077 (0x12F6u)
1519 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1078 (0x38ADu)
1520 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1079 (0x5CD1u)
1521 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1080 (0x26CBu)
1522 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1081 (0x2ECAu)
1523 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1082 (0x37C8u)
1524 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1083 (0x5A3Au)
1525 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1084 (0x38E6u)
1526 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1085 (0x4F19u)
1527 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1086 (0x2795u)
1528 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1087 (0x768Au)
1529 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1088 (0x393Cu)
1530 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1089 (0x417Bu)
1531 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1090 (0x5A66u)
1532 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1091 (0x35B1u)
1533 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1092 (0x65D1u)
1534 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1093 (0x6956u)
1535 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1094 (0x2F45u)
1536 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1095 (0x4ED2u)
1537 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1096 (0x586Eu)
1538 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1097 (0x6371u)
1539 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1098 (0x52A7u)
1540 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1099 (0x27D8u)
1541 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1100 (0x5D16u)
1542 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1101 (0x36B4u)
1543 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1102 (0x5A17u)
1544 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1103 (0x295Bu)
1545 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1104 (0x13ABu)
1546 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1105 (0x0ED3u)
1547 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1106 (0x5B26u)
1548 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1107 (0x61DAu)
1549 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1108 (0x3C56u)
1550 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1109 (0x660Fu)
1551 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1110 (0x6365u)
1552 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1111 (0x5A0Fu)
1553 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1112 (0x3743u)
1554 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1113 (0x06F9u)
1555 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1114 (0x4CAEu)
1556 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1115 (0x5974u)
1557 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1116 (0x17E8u)
1558 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1117 (0x1A67u)
1559 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1118 (0x7C49u)
1560 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1119 (0x14D7u)
1561 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1120 (0x2B17u)
1562 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1121 (0x741Eu)
1563 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1122 (0x5745u)
1564 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1123 (0x7C1Cu)
1565 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1124 (0x2B2Eu)
1566 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1125 (0x6C1Bu)
1567 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1126 (0x35CAu)
1568 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1127 (0x05F6u)
1569 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1128 (0x2C9Bu)
1570 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1129 (0x71A6u)
1571 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1130 (0x123Fu)
1572 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1131 (0x069Fu)
1573 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1132 (0x136Bu)
1574 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1133 (0x6857u)
1575 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1134 (0x4E0Fu)
1576 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1135 (0x193Eu)
1577 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1136 (0x15F8u)
1578 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1137 (0x127Bu)
1579 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1138 (0x668Du)
1580 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1139 (0x34ADu)
1581 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1140 (0x7AA8u)
1582 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1141 (0x3E25u)
1583 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1142 (0x3365u)
1584 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1143 (0x4C5Eu)
1585 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1144 (0x2E1Eu)
1586 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1145 (0x2B55u)
1587 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1146 (0x64EAu)
1588 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1147 (0x36D1u)
1589 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1148 (0x70E6u)
1590 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1149 (0x3794u)
1591 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1150 (0x5167u)
1592 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1151 (0x1A6Du)
1593 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1152 (0x6A66u)
1594 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1153 (0x311Fu)
1595 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1154 (0x62F2u)
1596 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1155 (0x6A6Au)
1597 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1156 (0x13BCu)
1598 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1157 (0x274Du)
1599 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1158 (0x6AA5u)
1600 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1159 (0x22F3u)
1601 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1160 (0x2755u)
1602 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1161 (0x5E26u)
1603 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1162 (0x726Au)
1604 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1163 (0x5AC5u)
1605 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1164 (0x51D6u)
1606 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1165 (0x04DFu)
1607 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1166 (0x4DA5u)
1608 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1167 (0x49DAu)
1609 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1168 (0x7439u)
1610 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1169 (0x645Bu)
1611 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1170 (0x6C96u)
1612 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1171 (0x236Eu)
1613 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1172 (0x2AADu)
1614 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1173 (0x5BA8u)
1615 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1174 (0x2673u)
1616 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1175 (0x41EDu)
1617 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1176 (0x18E7u)
1618 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1177 (0x705Du)
1619 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1178 (0x1C3Bu)
1620 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1179 (0x7607u)
1621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1180 (0x0E97u)
1622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1181 (0x4A9Du)
1623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1182 (0x1759u)
1624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1183 (0x3A47u)
1625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1184 (0x5A27u)
1626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1185 (0x4A6Eu)
1627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1186 (0x6267u)
1628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1187 (0x4B59u)
1629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1188 (0x2ACBu)
1630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1189 (0x16CDu)
1631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1190 (0x6CF0u)
1632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1191 (0x7D42u)
1633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1192 (0x432Fu)
1634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1193 (0x25F1u)
1635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1194 (0x546Du)
1636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1195 (0x69E2u)
1637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1196 (0x7C91u)
1638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1197 (0x232Fu)
1639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1198 (0x2337u)
1640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1199 (0x6E1Cu)
1641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1200 (0x5E85u)
1642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1201 (0x1A73u)
1643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1202 (0x29F4u)
1644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1203 (0x5738u)
1645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1204 (0x1DCAu)
1646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1205 (0x21EDu)
1647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1206 (0x3B0Eu)
1648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1207 (0x25EAu)
1649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1208 (0x0DB5u)
1650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1209 (0x7543u)
1651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1210 (0x4735u)
1652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1211 (0x11EDu)
1653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1212 (0x458Fu)
1654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1213 (0x6C2Bu)
1655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1214 (0x15B9u)
1656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1215 (0x3C3Au)
1657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1216 (0x5C5Au)
1658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1217 (0x53A5u)
1659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1218 (0x635Cu)
1660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1219 (0x638Eu)
1661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1220 (0x70AEu)
1662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1221 (0x1DD8u)
1663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1222 (0x34BCu)
1664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1223 (0x491Fu)
1665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1224 (0x0DD5u)
1666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1225 (0x2BC5u)
1667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1226 (0x6536u)
1668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1227 (0x63D1u)
1669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1228 (0x75A1u)
1670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1229 (0x1357u)
1671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1230 (0x4F98u)
1672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1231 (0x2FC8u)
1673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1232 (0x139Du)
1674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1233 (0x64ADu)
1675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1234 (0x13CBu)
1676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1235 (0x332Bu)
1677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1236 (0x6663u)
1678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1237 (0x4FC2u)
1679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1238 (0x65A5u)
1680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1239 (0x67C4u)
1681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1240 (0x487Bu)
1682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1241 (0x6B0Bu)
1683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1242 (0x516Du)
1684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1243 (0x0FC9u)
1685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1244 (0x3E46u)
1686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1245 (0x627Cu)
1687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1246 (0x4A5Bu)
1688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1247 (0x2DD8u)
1689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1248 (0x6A65u)
1690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1249 (0x7760u)
1691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1250 (0x7750u)
1692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1251 (0x5879u)
1693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1252 (0x3D64u)
1694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1253 (0x06F6u)
1695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1254 (0x4787u)
1696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1255 (0x1CF8u)
1697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1256 (0x70E5u)
1698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1257 (0x41B7u)
1699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1258 (0x12BDu)
1700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1259 (0x146Fu)
1701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1260 (0x5497u)
1702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1261 (0x633Cu)
1703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1262 (0x48F5u)
1704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1263 (0x1BC9u)
1705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1264 (0x545Bu)
1706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1265 (0x616Du)
1707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1266 (0x51BAu)
1708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1267 (0x728Eu)
1709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1268 (0x3965u)
1710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1269 (0x47A5u)
1711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1270 (0x74CAu)
1712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1271 (0x0CBEu)
1713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1272 (0x3C6Cu)
1714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1273 (0x50EEu)
1715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1274 (0x45F4u)
1716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1275 (0x30DDu)
1717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1276 (0x6DA4u)
1718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1277 (0x68ECu)
1719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1278 (0x0CFCu)
1720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1279 (0x273Au)
1721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1280 (0x51B5u)
1722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1281 (0x1B4Du)
1723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1282 (0x35F0u)
1724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1283 (0x0D57u)
1725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1284 (0x02EFu)
1726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1285 (0x4A67u)
1727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1286 (0x457Au)
1728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1287 (0x54E5u)
1729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1288 (0x2AF8u)
1730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1289 (0x746Au)
1731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1290 (0x6A74u)
1732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1291 (0x099Fu)
1733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1292 (0x654Bu)
1734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1293 (0x3C5Au)
1735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1294 (0x18BBu)
1736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1295 (0x617Cu)
1737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1296 (0x2E5Au)
1738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1297 (0x6E68u)
1739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1298 (0x713Au)
1740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1299 (0x26F1u)
1741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1300 (0x6257u)
1742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1301 (0x786Cu)
1743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1302 (0x16D5u)
1744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1303 (0x1C67u)
1745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1304 (0x64CBu)
1746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1305 (0x62B6u)
1747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1306 (0x47C3u)
1748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1307 (0x78A9u)
1749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1308 (0x2ED8u)
1750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1309 (0x3B07u)
1751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1310 (0x5B1Au)
1752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1311 (0x1E47u)
1753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1312 (0x39B4u)
1754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1313 (0x30E7u)
1755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1314 (0x41EEu)
1756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1315 (0x5547u)
1757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1316 (0x4B4Bu)
1758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1317 (0x2E1Du)
1759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1318 (0x5A3Cu)
1760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1319 (0x7558u)
1761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1320 (0x32F4u)
1762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1321 (0x4727u)
1763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1322 (0x3ACCu)
1764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1323 (0x3655u)
1765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1324 (0x1F49u)
1766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1325 (0x3B1Cu)
1767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1326 (0x6077u)
1768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1327 (0x4EB8u)
1769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1328 (0x056Fu)
1770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1329 (0x7C58u)
1771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1330 (0x45D3u)
1772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1331 (0x3FA0u)
1773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1332 (0x63D4u)
1774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1333 (0x76C8u)
1775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1334 (0x4D95u)
1776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1335 (0x370Bu)
1777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1336 (0x1F8Au)
1778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1337 (0x4CDCu)
1779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1338 (0x3539u)
1780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1339 (0x24CFu)
1781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1340 (0x1D99u)
1782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1341 (0x451Fu)
1783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1342 (0x15B6u)
1784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1343 (0x5CC3u)
1785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1344 (0x3CC3u)
1786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1345 (0x6C56u)
1787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1346 (0x04F7u)
1788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1347 (0x7D84u)
1789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1348 (0x25BCu)
1790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1349 (0x2CD6u)
1791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1350 (0x391Eu)
1792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1351 (0x075Du)
1793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1352 (0x67A4u)
1794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1353 (0x195Eu)
1795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1354 (0x478Eu)
1796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1355 (0x47E2u)
1797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1356 (0x52C7u)
1798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1357 (0x18BEu)
1799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1358 (0x3473u)
1800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1359 (0x798Au)
1801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1360 (0x3378u)
1802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1361 (0x72D2u)
1803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1362 (0x7163u)
1804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1363 (0x18DEu)
1805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1364 (0x22FCu)
1806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1365 (0x2BCCu)
1807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1366 (0x0E6Eu)
1808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1367 (0x2CF4u)
1809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1368 (0x5D4Cu)
1810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1369 (0x3527u)
1811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1370 (0x3353u)
1812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1371 (0x1CCEu)
1813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1372 (0x4BD1u)
1814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1373 (0x1E8Bu)
1815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1374 (0x7D24u)
1816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1375 (0x4E47u)
1817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1376 (0x5955u)
1818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1377 (0x72A3u)
1819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1378 (0x1E33u)
1820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1379 (0x5AD4u)
1821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1380 (0x247Du)
1822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1381 (0x67E0u)
1823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1382 (0x4BA6u)
1824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1383 (0x594Bu)
1825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1384 (0x454Fu)
1826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1385 (0x58EAu)
1827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1386 (0x4DD8u)
1828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1387 (0x7364u)
1829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1388 (0x0B3Bu)
1830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1389 (0x1E53u)
1831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1390 (0x5EC1u)
1832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1391 (0x31F4u)
1833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1392 (0x7495u)
1834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1393 (0x439Eu)
1835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1394 (0x344Fu)
1836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1395 (0x5A1Bu)
1837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1396 (0x3963u)
1838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1397 (0x46ECu)
1839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1398 (0x1DAAu)
1840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1399 (0x326Eu)
1841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1400 (0x522Fu)
1842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1401 (0x73C2u)
1843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1402 (0x1DB1u)
1844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1403 (0x14F6u)
1845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1404 (0x26F2u)
1846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1405 (0x32D6u)
1847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1406 (0x6B15u)
1848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1407 (0x19AEu)
1849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1408 (0x0D5Du)
1850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1409 (0x7899u)
1851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1410 (0x5587u)
1852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1411 (0x674Cu)
1853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1412 (0x2C73u)
1854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1413 (0x2B1Du)
1855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1414 (0x12AFu)
1856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1415 (0x78B2u)
1857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1416 (0x3731u)
1858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1417 (0x4D35u)
1859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1418 (0x23D9u)
1860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1419 (0x4B65u)
1861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1420 (0x29F2u)
1862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1421 (0x7394u)
1863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1422 (0x65D8u)
1864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1423 (0x386Bu)
1865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1424 (0x6C0Fu)
1866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1425 (0x6C4Du)
1867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1426 (0x2BA9u)
1868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1427 (0x2F46u)
1869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1428 (0x3D26u)
1870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1429 (0x7A15u)
1871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1430 (0x7398u)
1872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1431 (0x73C4u)
1873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1432 (0x32DCu)
1874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1433 (0x21F6u)
1875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1434 (0x162Fu)
1876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1435 (0x1E2Du)
1877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1436 (0x22DEu)
1878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1437 (0x593Au)
1879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1438 (0x173Au)
1880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1439 (0x66D2u)
1881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1440 (0x217Du)
1882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1441 (0x44EDu)
1883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1442 (0x3617u)
1884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1443 (0x09DBu)
1885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1444 (0x51CBu)
1886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1445 (0x591Bu)
1887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1446 (0x45ECu)
1888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1447 (0x19ADu)
1889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1448 (0x7649u)
1890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1449 (0x3653u)
1891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1450 (0x6574u)
1892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1451 (0x7C16u)
1893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1452 (0x7932u)
1894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1453 (0x364Du)
1895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1454 (0x790Eu)
1896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1455 (0x323Du)
1897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1456 (0x586Bu)
1898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1457 (0x1B35u)
1899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1458 (0x78E2u)
1900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1459 (0x6F06u)
1901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1460 (0x0BF2u)
1902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1461 (0x14DDu)
1903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1462 (0x5959u)
1904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1463 (0x3CAAu)
1905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1464 (0x5734u)
1906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1465 (0x46E9u)
1907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1466 (0x2ABAu)
1908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1467 (0x0AEBu)
1909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1468 (0x46CDu)
1910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1469 (0x6273u)
1911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1470 (0x32AEu)
1912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1471 (0x4E93u)
1913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1472 (0x369Au)
1914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1473 (0x4DB1u)
1915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1474 (0x23F2u)
1916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1475 (0x3AB2u)
1917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1476 (0x744Du)
1918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1477 (0x26D9u)
1919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1478 (0x5953u)
1920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1479 (0x558Eu)
1921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1480 (0x5D45u)
1922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1481 (0x2B35u)
1923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1482 (0x32D3u)
1924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1483 (0x7943u)
1925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1484 (0x0AAFu)
1926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1485 (0x2F91u)
1927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1486 (0x68F8u)
1928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1487 (0x3D54u)
1929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1488 (0x1BF0u)
1930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1489 (0x2AABu)
1931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1490 (0x1C4Fu)
1932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1491 (0x0D67u)
1933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1492 (0x159Bu)
1934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1493 (0x1E59u)
1935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1494 (0x6A2Eu)
1936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1495 (0x18FCu)
1937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1496 (0x39C6u)
1938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1497 (0x6F28u)
1939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1498 (0x219Fu)
1940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1499 (0x1976u)
1941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1500 (0x24DDu)
1942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1501 (0x51ECu)
1943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1502 (0x7217u)
1944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1503 (0x5137u)
1945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1504 (0x2F43u)
1946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1505 (0x14BEu)
1947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1506 (0x5297u)
1948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1507 (0x40FEu)
1949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1508 (0x2A79u)
1950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1509 (0x117Bu)
1951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1510 (0x269Du)
1952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1511 (0x66C9u)
1953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1512 (0x42EBu)
1954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1513 (0x153Du)
1955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1514 (0x55A5u)
1956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1515 (0x7615u)
1957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1516 (0x43F1u)
1958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1517 (0x1BE4u)
1959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1518 (0x3C1Du)
1960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1519 (0x33D1u)
1961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1520 (0x607Bu)
1962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1521 (0x6475u)
1963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1522 (0x3C8Eu)
1964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1523 (0x1799u)
1965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1524 (0x5EA4u)
1966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1525 (0x7459u)
1967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1526 (0x2735u)
1968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1527 (0x6476u)
1969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1528 (0x6C27u)
1970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1529 (0x2B1Eu)
1971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1530 (0x61BAu)
1972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1531 (0x3B16u)
1973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1532 (0x2AB9u)
1974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1533 (0x644Fu)
1975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1534 (0x2ED1u)
1976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1535 (0x1F68u)
1977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1536 (0x1557u)
1978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1537 (0x3D07u)
1979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1538 (0x1A5Eu)
1980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1539 (0x55E4u)
1981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1540 (0x3995u)
1982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1541 (0x5E70u)
1983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1542 (0x71D2u)
1984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1543 (0x3E0Bu)
1985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1544 (0x2F07u)
1986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1545 (0x163Du)
1987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1546 (0x4B33u)
1988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1547 (0x3D85u)
1989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1548 (0x297Cu)
1990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1549 (0x0EDCu)
1991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1550 (0x4A2Fu)
1992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1551 (0x5E43u)
1993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1552 (0x4F32u)
1994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1553 (0x1AB3u)
1995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1554 (0x64B5u)
1996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1555 (0x4EC5u)
1997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1556 (0x6E19u)
1998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1557 (0x42BDu)
1999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1558 (0x3B92u)
2000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1559 (0x5A56u)
2001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1560 (0x6587u)
2002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1561 (0x66A3u)
2003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1562 (0x19B3u)
2004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1563 (0x21D7u)
2005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1564 (0x4376u)
2006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1565 (0x32A7u)
2007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1566 (0x7951u)
2008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1567 (0x1B2Bu)
2009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1568 (0x5754u)
2010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1569 (0x0D8Fu)
2011 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1570 (0x1D3Au)
2012 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1571 (0x3E86u)
2013 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1572 (0x43CBu)
2014 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1573 (0x1739u)
2015 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1574 (0x7985u)
2016 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1575 (0x7472u)
2017 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1576 (0x196Eu)
2018 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1577 (0x2DE8u)
2019 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1578 (0x6A78u)
2020 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1579 (0x38BCu)
2021 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1580 (0x1F51u)
2022 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1581 (0x0F6Au)
2023 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1582 (0x70B9u)
2024 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1583 (0x34D5u)
2025 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1584 (0x64E9u)
2026 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1585 (0x352Du)
2027 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1586 (0x6764u)
2028 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1587 (0x3555u)
2029 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1588 (0x378Cu)
2030 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1589 (0x1D35u)
2031 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1590 (0x515Du)
2032 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1591 (0x292Fu)
2033 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1592 (0x4C3Du)
2034 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1593 (0x1733u)
2035 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1594 (0x5BA1u)
2036 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1595 (0x59E4u)
2037 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1596 (0x7313u)
2038 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1597 (0x48BBu)
2039 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1598 (0x7075u)
2040 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1599 (0x11BBu)
2041 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1600 (0x5D43u)
2042 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1601 (0x3876u)
2043 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1602 (0x1B6Cu)
2044 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1603 (0x1BCAu)
2045 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1604 (0x18F9u)
2046 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1605 (0x559Cu)
2047 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1606 (0x19BAu)
2048 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1607 (0x382Fu)
2049 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1608 (0x3751u)
2050 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1609 (0x5768u)
2051 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1610 (0x1BC6u)
2052 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1611 (0x7E60u)
2053 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1612 (0x27C6u)
2054 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1613 (0x33C6u)
2055 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1614 (0x2B87u)
2056 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1615 (0x2E74u)
2057 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1616 (0x7B05u)
2058 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1617 (0x59B8u)
2059 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1618 (0x465Du)
2060 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1619 (0x3D15u)
2061 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1620 (0x0F8Du)
2062 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1621 (0x38D9u)
2063 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1622 (0x659Au)
2064 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1623 (0x295Du)
2065 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1624 (0x265Bu)
2066 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1625 (0x7626u)
2067 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1626 (0x27B2u)
2068 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1627 (0x55B4u)
2069 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1628 (0x64E6u)
2070 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1629 (0x315Bu)
2071 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1630 (0x299Eu)
2072 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1631 (0x6C59u)
2073 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1632 (0x169Du)
2074 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1633 (0x3639u)
2075 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1634 (0x0F6Cu)
2076 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1635 (0x4ACDu)
2077 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1636 (0x3D1Au)
2078 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1637 (0x2397u)
2079 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1638 (0x664Bu)
2080 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1639 (0x5731u)
2081 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1640 (0x2E66u)
2082 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1641 (0x1BE8u)
2083 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1642 (0x5B2Cu)
2084 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1643 (0x27B8u)
2085 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1644 (0x4BC3u)
2086 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1645 (0x433Du)
2087 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1646 (0x2F83u)
2088 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1647 (0x1657u)
2089 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1648 (0x2B65u)
2090 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1649 (0x2BD8u)
2091 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1650 (0x561Eu)
2092 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1651 (0x4375u)
2093 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1652 (0x1AAEu)
2094 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1653 (0x39F0u)
2095 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1654 (0x668Eu)
2096 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1655 (0x4C9Bu)
2097 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1656 (0x6EA8u)
2098 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1657 (0x1667u)
2099 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1658 (0x0AEEu)
2100 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1659 (0x075Eu)
2101 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1660 (0x2A2Fu)
2102 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1661 (0x643Du)
2103 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1662 (0x564Bu)
2104 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1663 (0x33CCu)
2105 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1664 (0x63A5u)
2106 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1665 (0x56B8u)
2107 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1666 (0x53CCu)
2108 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1667 (0x7299u)
2109 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1668 (0x0DE3u)
2110 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1669 (0x47A9u)
2111 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1670 (0x632Eu)
2112 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1671 (0x7307u)
2113 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1672 (0x3917u)
2114 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1673 (0x719Au)
2115 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1674 (0x3B31u)
2116 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1675 (0x658Du)
2117 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1676 (0x3C59u)
2118 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1677 (0x744Eu)
2119 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1678 (0x63CAu)
2120 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1679 (0x0677u)
2121 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1680 (0x74CCu)
2122 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1681 (0x1B39u)
2123 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1682 (0x4BCCu)
2124 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1683 (0x45D6u)
2125 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1684 (0x2CABu)
2126 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1685 (0x456Bu)
2127 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1686 (0x0F9Au)
2128 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1687 (0x1CB6u)
2129 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1688 (0x327Cu)
2130 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1689 (0x0E6Du)
2131 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1690 (0x23DCu)
2132 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1691 (0x55E1u)
2133 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1692 (0x69D8u)
2134 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1693 (0x5B16u)
2135 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1694 (0x78B8u)
2136 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1695 (0x69CAu)
2137 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1696 (0x385Du)
2138 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1697 (0x4937u)
2139 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1698 (0x6CA9u)
2140 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1699 (0x263Bu)
2141 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1700 (0x709Bu)
2142 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1701 (0x513Du)
2143 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1702 (0x496Du)
2144 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1703 (0x6E0Eu)
2145 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1704 (0x57C4u)
2146 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1705 (0x3F41u)
2147 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1706 (0x2B3Cu)
2148 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1707 (0x7A0Du)
2149 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1708 (0x7931u)
2150 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1709 (0x63C6u)
2151 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1710 (0x783Au)
2152 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1711 (0x5B70u)
2153 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1712 (0x65B4u)
2154 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1713 (0x49B9u)
2155 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1714 (0x65A9u)
2156 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1715 (0x6996u)
2157 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1716 (0x2F86u)
2158 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1717 (0x574Cu)
2159 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1718 (0x423Fu)
2160 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1719 (0x564Du)
2161 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1720 (0x3636u)
2162 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1721 (0x0D1Fu)
2163 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1722 (0x782Eu)
2164 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1723 (0x2AA7u)
2165 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1724 (0x5D91u)
2166 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1725 (0x1277u)
2167 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1726 (0x265Eu)
2168 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1727 (0x0F1Du)
2169 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1728 (0x606Fu)
2170 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1729 (0x5C9Cu)
2171 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1730 (0x5353u)
2172 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1731 (0x191Fu)
2173 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1732 (0x330Fu)
2174 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1733 (0x5E25u)
2175 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1734 (0x08FDu)
2176 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1735 (0x5175u)
2177 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1736 (0x6CAAu)
2178 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1737 (0x5333u)
2179 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1738 (0x1ACBu)
2180 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1739 (0x6672u)
2181 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1740 (0x39D1u)
2182 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1741 (0x3BB0u)
2183 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1742 (0x7A52u)
2184 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1743 (0x5794u)
2185 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1744 (0x5D23u)
2186 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1745 (0x6D1Cu)
2187 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1746 (0x72E8u)
2188 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1747 (0x5F82u)
2189 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1748 (0x650Fu)
2190 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1749 (0x0D9Eu)
2191 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1750 (0x1B3Au)
2192 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1751 (0x36D8u)
2193 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1752 (0x0B75u)
2194 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1753 (0x583Du)
2195 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1754 (0x2EE8u)
2196 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1755 (0x41DDu)
2197 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1756 (0x159Eu)
2198 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1757 (0x6F44u)
2199 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1758 (0x7B30u)
2200 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1759 (0x46BAu)
2201 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1760 (0x0B6Bu)
2202 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1761 (0x3CD8u)
2203 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1762 (0x06DEu)
2204 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1763 (0x69B1u)
2205 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1764 (0x216Fu)
2206 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1765 (0x3F90u)
2207 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1766 (0x166Du)
2208 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1767 (0x1D96u)
2209 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1768 (0x32E5u)
2210 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1769 (0x32D5u)
2211 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1770 (0x17A6u)
2212 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1771 (0x5A8Du)
2213 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1772 (0x2373u)
2214 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1773 (0x2DC3u)
2215 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1774 (0x51F8u)
2216 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1775 (0x6E91u)
2217 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1776 (0x4F92u)
2218 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1777 (0x7325u)
2219 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1778 (0x31B5u)
2220 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1779 (0x495Bu)
2221 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1780 (0x1ABAu)
2222 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1781 (0x75B0u)
2223 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1782 (0x56C6u)
2224 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1783 (0x26DCu)
2225 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1784 (0x5387u)
2226 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1785 (0x64E5u)
2227 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1786 (0x11DEu)
2228 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1787 (0x591Eu)
2229 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1788 (0x23CEu)
2230 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1789 (0x7358u)
2231 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1790 (0x6317u)
2232 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1791 (0x4F34u)
2233 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1792 (0x49B6u)
2234 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1793 (0x27E8u)
2235 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1794 (0x6593u)
2236 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1795 (0x44EEu)
2237 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1796 (0x6C1Du)
2238 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1797 (0x26BAu)
2239 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1798 (0x30EDu)
2240 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1799 (0x276Au)
2241 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1800 (0x47C6u)
2242 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1801 (0x5173u)
2243 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1802 (0x07D9u)
2244 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1803 (0x714Du)
2245 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1804 (0x3D8Au)
2246 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1805 (0x0D4Fu)
2247 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1806 (0x6533u)
2248 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1807 (0x2778u)
2249 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1808 (0x1ECCu)
2250 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1809 (0x7A23u)
2251 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1810 (0x49F8u)
2252 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1811 (0x3F0Au)
2253 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1812 (0x1B1Eu)
2254 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1813 (0x0D76u)
2255 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1814 (0x24BEu)
2256 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1815 (0x07CBu)
2257 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1816 (0x2DCCu)
2258 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1817 (0x7952u)
2259 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1818 (0x5D0Du)
2260 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1819 (0x55E2u)
2261 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1820 (0x672Au)
2262 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1821 (0x549Du)
2263 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1822 (0x1B53u)
2264 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1823 (0x0DC7u)
2265 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1824 (0x1E5Au)
2266 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1825 (0x6B64u)
2267 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1826 (0x0DA7u)
2268 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1827 (0x289Fu)
2269 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1828 (0x7B42u)
2270 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1829 (0x59E8u)
2271 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1830 (0x07F4u)
2272 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1831 (0x3CA9u)
2273 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1832 (0x1F4Au)
2274 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1833 (0x2DACu)
2275 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1834 (0x39D4u)
2276 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1835 (0x0B3Eu)
2277 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1836 (0x751Cu)
2278 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1837 (0x1C9Bu)
2279 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1838 (0x55A3u)
2280 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1839 (0x7568u)
2281 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1840 (0x46AEu)
2282 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1841 (0x70D5u)
2283 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1842 (0x5AA5u)
2284 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1843 (0x3D68u)
2285 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1844 (0x570Eu)
2286 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1845 (0x0BB6u)
2287 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1846 (0x641Fu)
2288 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1847 (0x3E58u)
2289 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1848 (0x62C7u)
2290 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1849 (0x6B46u)
2291 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1850 (0x57D0u)
2292 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1851 (0x7E30u)
2293 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1852 (0x6789u)
2294 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1853 (0x12F5u)
2295 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1854 (0x12BBu)
2296 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1855 (0x7654u)
2297 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1856 (0x15A7u)
2298 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1857 (0x2AECu)
2299 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1858 (0x6CACu)
2300 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1859 (0x236Bu)
2301 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1860 (0x5F48u)
2302 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1861 (0x269Bu)
2303 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1862 (0x6B26u)
2304 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1863 (0x578Au)
2305 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1864 (0x532Du)
2306 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1865 (0x18CFu)
2307 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1866 (0x5B38u)
2308 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1867 (0x2AE9u)
2309 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1868 (0x0977u)
2310 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1869 (0x6A8Eu)
2311 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1870 (0x3A56u)
2312 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1871 (0x6947u)
2313 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1872 (0x1A2Fu)
2314 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1873 (0x655Au)
2315 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1874 (0x3D52u)
2316 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1875 (0x2B4Eu)
2317 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1876 (0x26F8u)
2318 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1877 (0x2E71u)
2319 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1878 (0x35D1u)
2320 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1879 (0x1EB8u)
2321 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1880 (0x1CB9u)
2322 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1881 (0x171Du)
2323 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1882 (0x5DC1u)
2324 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1883 (0x4D1Bu)
2325 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1884 (0x3A5Cu)
2326 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1885 (0x6D89u)
2327 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1886 (0x36D2u)
2328 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1887 (0x3D89u)
2329 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1888 (0x0EBCu)
2330 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1889 (0x4759u)
2331 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1890 (0x7AC8u)
2332 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1891 (0x4F29u)
2333 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1892 (0x2D2Eu)
2334 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1893 (0x2F31u)
2335 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1894 (0x3E13u)
2336 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1895 (0x62CEu)
2337 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1896 (0x3E26u)
2338 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1897 (0x06BDu)
2339 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1898 (0x662Bu)
2340 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1899 (0x0EDAu)
2341 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1900 (0x54CDu)
2342 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1901 (0x0BDCu)
2343 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1902 (0x11EEu)
2344 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1903 (0x54D5u)
2345 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1904 (0x51D9u)
2346 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1905 (0x1F2Cu)
2347 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1906 (0x0BD3u)
2348 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1907 (0x324Fu)
2349 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1908 (0x4D53u)
2350 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1909 (0x4DE1u)
2351 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1910 (0x3EC4u)
2352 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1911 (0x34B6u)
2353 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1912 (0x7564u)
2354 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1913 (0x03F5u)
2355 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1914 (0x155Bu)
2356 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1915 (0x0D7Cu)
2357 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1916 (0x6547u)
2358 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1917 (0x3D31u)
2359 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1918 (0x3C65u)
2360 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1919 (0x3395u)
2361 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1920 (0x16ADu)
2362 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1921 (0x66A5u)
2363 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1922 (0x33B8u)
2364 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1923 (0x7C92u)
2365 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1924 (0x4E17u)
2366 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1925 (0x745Au)
2367 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1926 (0x2BC3u)
2368 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1927 (0x26B6u)
2369 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1928 (0x5EA2u)
2370 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1929 (0x3396u)
2371 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1930 (0x0F27u)
2372 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1931 (0x4B53u)
2373 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1932 (0x3C2Bu)
2374 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1933 (0x349Eu)
2375 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1934 (0x5378u)
2376 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1935 (0x722Bu)
2377 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1936 (0x2B6Cu)
2378 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1937 (0x6EB0u)
2379 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1938 (0x6D64u)
2380 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1939 (0x2E72u)
2381 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1940 (0x4DE8u)
2382 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1941 (0x3738u)
2383 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1942 (0x4BAAu)
2384 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1943 (0x7271u)
2385 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1944 (0x3497u)
2386 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1945 (0x4DC6u)
2387 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1946 (0x2EB4u)
2388 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1947 (0x7A2Cu)
2389 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1948 (0x0FCAu)
2390 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1949 (0x3734u)
2391 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1950 (0x748Bu)
2392 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1951 (0x690Fu)
2393 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1952 (0x6E83u)
2394 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1953 (0x7F08u)
2395 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1954 (0x5276u)
2396 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1955 (0x41BDu)
2397 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1956 (0x43ADu)
2398 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1957 (0x34D3u)
2399 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1958 (0x7097u)
2400 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1959 (0x237Au)
2401 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1960 (0x6745u)
2402 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1961 (0x3B54u)
2403 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1962 (0x4E1Eu)
2404 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1963 (0x3D34u)
2405 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1964 (0x0E5Eu)
2406 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1965 (0x3AF0u)
2407 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1966 (0x723Au)
2408 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1967 (0x671Cu)
2409 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1968 (0x30F3u)
2410 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1969 (0x5723u)
2411 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1970 (0x6F18u)
2412 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1971 (0x3E4Au)
2413 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1972 (0x55A9u)
2414 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1973 (0x08DFu)
2415 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1974 (0x26CDu)
2416 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1975 (0x1D5Au)
2417 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1976 (0x2C97u)
2418 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1977 (0x3BA4u)
2419 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1978 (0x7A46u)
2420 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1979 (0x44EBu)
2421 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1980 (0x1DC5u)
2422 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1981 (0x41FAu)
2423 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1982 (0x5E94u)
2424 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1983 (0x76A1u)
2425 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1984 (0x295Eu)
2426 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1985 (0x629Eu)
2427 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1986 (0x3E0Eu)
2428 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1987 (0x464Fu)
2429 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1988 (0x2F51u)
2430 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1989 (0x6761u)
2431 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1990 (0x0ACFu)
2432 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1991 (0x3D58u)
2433 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1992 (0x257Au)
2434 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1993 (0x44F6u)
2435 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1994 (0x62EAu)
2436 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1995 (0x4CB6u)
2437 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1996 (0x659Cu)
2438 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1997 (0x7A07u)
2439 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1998 (0x5C33u)
2440 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1999 (0x2BA5u)
2441 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2000 (0x703Bu)
2442 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2001 (0x5D58u)
2443 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2002 (0x7139u)
2444 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2003 (0x3656u)
2445 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2004 (0x4EB2u)
2446 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2005 (0x7E81u)
2447 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2006 (0x33E8u)
2448 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2007 (0x2CADu)
2449 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2008 (0x59CAu)
2450 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2009 (0x1EB1u)
2451 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2010 (0x3764u)
2452 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2011 (0x23D6u)
2453 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2012 (0x4537u)
2454 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2013 (0x7651u)
2455 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2014 (0x7591u)
2456 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2015 (0x4E6Cu)
2457 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2016 (0x1679u)
2458 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2017 (0x259Eu)
2459 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2018 (0x389Eu)
2460 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2019 (0x1FB0u)
2461 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2020 (0x3F09u)
2462 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2021 (0x227Eu)
2463 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2022 (0x74C6u)
2464 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2023 (0x70F4u)
2465 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2024 (0x14DEu)
2466 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2025 (0x61B5u)
2467 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2026 (0x336Cu)
2468 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2027 (0x619Eu)
2469 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2028 (0x266Eu)
2470 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2029 (0x4C2Fu)
2471 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2030 (0x6F22u)
2472 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2031 (0x58E5u)
2473 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2032 (0x26EAu)
2474 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2033 (0x3E8Cu)
2475 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2034 (0x28DBu)
2476 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2035 (0x72D8u)
2477 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2036 (0x1F54u)
2478 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2037 (0x07ECu)
2479 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2038 (0x0BCBu)
2480 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2039 (0x7709u)
2481 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2040 (0x4A5Eu)
2482 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2041 (0x3CD2u)
2483 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2042 (0x0F17u)
2484 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2043 (0x24EEu)
2485 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2044 (0x3C4Eu)
2486 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2045 (0x0ED9u)
2487 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2046 (0x7865u)
2488 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2047 (0x4477u)
2489 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2048 (0x6738u)
2490 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2049 (0x2E96u)
2491 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2050 (0x6A63u)
2492 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2051 (0x7D48u)
2493 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2052 (0x419Fu)
2494 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2053 (0x58D6u)
2495 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2054 (0x6EC8u)
2496 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2055 (0x427Bu)
2497 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2056 (0x52D6u)
2498 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2057 (0x13D9u)
2499 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2058 (0x5C78u)
2500 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2059 (0x63A9u)
2501 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2060 (0x3E1Cu)
2502 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2061 (0x6B8Au)
2503 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2062 (0x31DAu)
2504 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2063 (0x6B32u)
2505 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2064 (0x74D4u)
2506 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2065 (0x374Cu)
2507 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2066 (0x6666u)
2508 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2067 (0x4C97u)
2509 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2068 (0x269Eu)
2510 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2069 (0x41CFu)
2511 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2070 (0x1A9Bu)
2512 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2071 (0x4DB8u)
2513 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2072 (0x31EAu)
2514 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2073 (0x1E74u)
2515 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2074 (0x762Cu)
2516 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2075 (0x70D9u)
2517 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2076 (0x0B4Fu)
2518 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2077 (0x653Au)
2519 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2078 (0x7C31u)
2520 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2079 (0x4ED1u)
2521 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2080 (0x30F6u)
2522 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2081 (0x11B7u)
2523 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2082 (0x48DEu)
2524 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2083 (0x0767u)
2525 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2084 (0x125Fu)
2526 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2085 (0x3CB1u)
2527 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2086 (0x7586u)
2528 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2087 (0x0FE8u)
2529 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2088 (0x62AEu)
2530 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2089 (0x3536u)
2531 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2090 (0x7117u)
2532 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2091 (0x6D15u)
2533 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2092 (0x0FD4u)
2534 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2093 (0x3A1Du)
2535 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2094 (0x5D1Cu)
2536 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2095 (0x0A7Eu)
2537 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2096 (0x0A5Fu)
2538 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2097 (0x4CCDu)
2539 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2098 (0x314Fu)
2540 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2099 (0x3A9Cu)
2541 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2100 (0x670Eu)
2542 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2101 (0x523Du)
2543 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2102 (0x58BAu)
2544 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2103 (0x3157u)
2545 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2104 (0x3770u)
2546 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2105 (0x3972u)
2547 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2106 (0x2ACDu)
2548 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2107 (0x71C6u)
2549 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2108 (0x4F51u)
2550 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2109 (0x1A97u)
2551 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2110 (0x34CBu)
2552 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2111 (0x622Fu)
2553 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2112 (0x514Fu)
2554 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2113 (0x1736u)
2555 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2114 (0x23CDu)
2556 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2115 (0x72B2u)
2557 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2116 (0x7552u)
2558 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2117 (0x1B1Du)
2559 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2118 (0x6175u)
2560 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2119 (0x3AE1u)
2561 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2120 (0x32EAu)
2562 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2121 (0x2727u)
2563 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2122 (0x66C5u)
2564 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2123 (0x4EC6u)
2565 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2124 (0x16BCu)
2566 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2125 (0x4717u)
2567 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2126 (0x558Bu)
2568 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2127 (0x7C98u)
2569 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2128 (0x734Cu)
2570 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2129 (0x2EA3u)
2571 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2130 (0x358Du)
2572 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2131 (0x54D6u)
2573 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2132 (0x12EEu)
2574 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2133 (0x7E50u)
2575 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2134 (0x523Eu)
2576 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2135 (0x6BA4u)
2577 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2136 (0x0CF3u)
2578 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2137 (0x78A6u)
2579 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2138 (0x5716u)
2580 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2139 (0x351Du)
2581 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2140 (0x157Au)
2582 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2141 (0x2997u)
2583 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2142 (0x718Eu)
2584 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2143 (0x7992u)
2585 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2144 (0x5A9Cu)
2586 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2145 (0x2BB2u)
2587 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2146 (0x455Eu)
2588 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2147 (0x569Au)
2589 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2148 (0x3CA3u)
2590 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2149 (0x2B2Du)
2591 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2150 (0x6837u)
2592 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2151 (0x58D5u)
2593 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2152 (0x2E87u)
2594 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2153 (0x1FD0u)
2595 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2154 (0x58ABu)
2596 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2155 (0x786Au)
2597 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2156 (0x5F18u)
2598 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2157 (0x5A8Bu)
2599 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2158 (0x4D9Au)
2600 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2159 (0x453Eu)
2601 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2160 (0x2F2Au)
2602 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2161 (0x11CFu)
2603 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2162 (0x0F4Bu)
2604 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2163 (0x48EBu)
2605 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2164 (0x2EC6u)
2606 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2165 (0x2B27u)
2607 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2166 (0x31DCu)
2608 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2167 (0x66D4u)
2609 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2168 (0x1E6Cu)
2610 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2169 (0x7CC4u)
2611 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2170 (0x0AF6u)
2612 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2171 (0x52AEu)
2613 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2172 (0x48FAu)
2614 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2173 (0x2AC7u)
2615 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2174 (0x69E8u)
2616 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2175 (0x1C37u)
2617 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2176 (0x3ACAu)
2618 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2177 (0x174Bu)
2619 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2178 (0x68B6u)
2620 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2179 (0x17F0u)
2621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2180 (0x1C3Eu)
2622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2181 (0x59A9u)
2623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2182 (0x2C57u)
2624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2183 (0x5F14u)
2625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2184 (0x3EA2u)
2626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2185 (0x43E3u)
2627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2186 (0x4D39u)
2628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2187 (0x32CDu)
2629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2188 (0x2597u)
2630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2189 (0x4F8Cu)
2631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2190 (0x11F6u)
2632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2191 (0x15D9u)
2633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2192 (0x351Eu)
2634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2193 (0x4AB3u)
2635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2194 (0x7073u)
2636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2195 (0x331Du)
2637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2196 (0x3A8Du)
2638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2197 (0x39B8u)
2639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2198 (0x341Fu)
2640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2199 (0x62F1u)
2641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2200 (0x43B5u)
2642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2201 (0x4DA6u)
2643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2202 (0x4ADAu)
2644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2203 (0x546Bu)
2645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2204 (0x4FA1u)
2646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2205 (0x6647u)
2647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2206 (0x654Eu)
2648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2207 (0x17D1u)
2649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2208 (0x05FAu)
2650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2209 (0x4AAEu)
2651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2210 (0x7239u)
2652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2211 (0x0F74u)
2653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2212 (0x02BFu)
2654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2213 (0x4E63u)
2655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2214 (0x7076u)
2656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2215 (0x0EABu)
2657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2216 (0x6C71u)
2658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2217 (0x21B7u)
2659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2218 (0x49C7u)
2660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2219 (0x754Au)
2661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2220 (0x58E6u)
2662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2221 (0x6867u)
2663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2222 (0x5E61u)
2664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2223 (0x398Du)
2665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2224 (0x7685u)
2666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2225 (0x366Au)
2667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2226 (0x6A5Cu)
2668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2227 (0x03EDu)
2669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2228 (0x5C4Eu)
2670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2229 (0x171Eu)
2671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2230 (0x45D5u)
2672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2231 (0x649Bu)
2673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2232 (0x261Fu)
2674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2233 (0x137Cu)
2675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2234 (0x596Au)
2676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2235 (0x3C72u)
2677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2236 (0x4AD3u)
2678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2237 (0x2B9Cu)
2679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2238 (0x56F0u)
2680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2239 (0x2DCAu)
2681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2240 (0x578Cu)
2682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2241 (0x3467u)
2683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2242 (0x36B8u)
2684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2243 (0x22DBu)
2685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2244 (0x339Cu)
2686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2245 (0x07DAu)
2687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2246 (0x07B5u)
2688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2247 (0x1597u)
2689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2248 (0x47B4u)
2690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2249 (0x6D19u)
2691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2250 (0x2667u)
2692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2251 (0x6D25u)
2693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2252 (0x09DEu)
2694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2253 (0x33A5u)
2695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2254 (0x1D9Au)
2696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2255 (0x6CD8u)
2697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2256 (0x1CA7u)
2698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2257 (0x43F8u)
2699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2258 (0x2F68u)
2700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2259 (0x227Du)
2701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2260 (0x4F46u)
2702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2261 (0x3E92u)
2703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2262 (0x698Du)
2704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2263 (0x359Cu)
2705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2264 (0x6A9Au)
2706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2265 (0x7714u)
2707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2266 (0x6347u)
2708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2267 (0x16B9u)
2709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2268 (0x3DD0u)
2710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2269 (0x66F0u)
2711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2270 (0x6873u)
2712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2271 (0x589Bu)
2713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2272 (0x621Fu)
2714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2273 (0x61BCu)
2715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2274 (0x23ABu)
2716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2275 (0x1F32u)
2717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2276 (0x6E0Du)
2718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2277 (0x78A5u)
2719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2278 (0x6E32u)
2720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2279 (0x6AD1u)
2721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2280 (0x0DECu)
2722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2281 (0x51B9u)
2723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2282 (0x2ED4u)
2724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2283 (0x3837u)
2725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2284 (0x0FB4u)
2726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2285 (0x22BBu)
2727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2286 (0x2FD0u)
2728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2287 (0x695Cu)
2729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2288 (0x4E36u)
2730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2289 (0x2E8Bu)
2731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2290 (0x553Au)
2732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2291 (0x4975u)
2733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2292 (0x25CDu)
2734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2293 (0x43D9u)
2735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2294 (0x6359u)
2736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2295 (0x6751u)
2737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2296 (0x0B6Eu)
2738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2297 (0x729Au)
2739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2298 (0x217Eu)
2740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2299 (0x598Bu)
2741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2300 (0x4E4Eu)
2742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2301 (0x49ECu)
2743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2302 (0x746Cu)
2744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2303 (0x3D0Bu)
2745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2304 (0x25B5u)
2746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2305 (0x1A9Eu)
2747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2306 (0x21EEu)
2748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2307 (0x5E68u)
2749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2308 (0x7A43u)
2750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2309 (0x1A3Eu)
2751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2310 (0x5D0Eu)
2752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2311 (0x4795u)
2753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2312 (0x0F8Bu)
2754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2313 (0x5C5Cu)
2755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2314 (0x7523u)
2756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2315 (0x251Fu)
2757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2316 (0x7915u)
2758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2317 (0x493Eu)
2759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2318 (0x2ADAu)
2760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2319 (0x3C4Bu)
2761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2320 (0x7E11u)
2762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2321 (0x1D2Eu)
2763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2322 (0x3A63u)
2764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2323 (0x0F5Au)
2765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2324 (0x5C99u)
2766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2325 (0x5AE8u)
2767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2326 (0x17A5u)
2768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2327 (0x0BB9u)
2769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2328 (0x07B3u)
2770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2329 (0x1F0Du)
2771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2330 (0x6E70u)
2772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2331 (0x389Bu)
2773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2332 (0x631Du)
2774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2333 (0x45CBu)
2775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2334 (0x4B9Cu)
2776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2335 (0x2877u)
2777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2336 (0x32ADu)
2778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2337 (0x5C56u)
2779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2338 (0x3E8Au)
2780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2339 (0x6DD0u)
2781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2340 (0x6927u)
2782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2341 (0x5C3Cu)
2783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2342 (0x6BC4u)
2784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2343 (0x5D46u)
2785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2344 (0x6E51u)
2786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2345 (0x742Eu)
2787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2346 (0x536Cu)
2788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2347 (0x543Du)
2789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2348 (0x3987u)
2790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2349 (0x2AF4u)
2791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2350 (0x3A17u)
2792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2351 (0x62D6u)
2793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2352 (0x2B4Du)
2794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2353 (0x60AFu)
2795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2354 (0x19CDu)
2796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2355 (0x4CE6u)
2797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2356 (0x5467u)
2798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2357 (0x52CEu)
2799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2358 (0x5C6Au)
2800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2359 (0x561Du)
2801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2360 (0x06FAu)
2802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2361 (0x616Eu)
2803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2362 (0x68D6u)
2804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2363 (0x3E45u)
2805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2364 (0x274Bu)
2806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2365 (0x1E39u)
2807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2366 (0x60FAu)
2808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2367 (0x728Bu)
2809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2368 (0x76C1u)
2810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2369 (0x3EA8u)
2811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2370 (0x178Du)
2812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2371 (0x7964u)
2813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2372 (0x6DA1u)
2814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2373 (0x61D5u)
2815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2374 (0x14BDu)
2816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2375 (0x613Du)
2817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2376 (0x58E9u)
2818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2377 (0x3AA5u)
2819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2378 (0x712Du)
2820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2379 (0x44CFu)
2821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2380 (0x7171u)
2822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2381 (0x783Cu)
2823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2382 (0x6E85u)
2824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2383 (0x44BDu)
2825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2384 (0x5DC4u)
2826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2385 (0x76A4u)
2827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2386 (0x6969u)
2828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2387 (0x328Fu)
2829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2388 (0x3372u)
2830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2389 (0x1E5Cu)
2831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2390 (0x68E6u)
2832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2391 (0x615Bu)
2833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2392 (0x6CB1u)
2834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2393 (0x1BB1u)
2835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2394 (0x13C7u)
2836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2395 (0x2F52u)
2837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2396 (0x24DBu)
2838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2397 (0x7A83u)
2839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2398 (0x7CA4u)
2840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2399 (0x2A8Fu)
2841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2400 (0x79A4u)
2842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2401 (0x0F53u)
2843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2402 (0x58B3u)
2844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2403 (0x3C69u)
2845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2404 (0x03DDu)
2846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2405 (0x648Fu)
2847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2406 (0x49B5u)
2848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2407 (0x4A3Du)
2849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2408 (0x7B60u)
2850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2409 (0x67A8u)
2851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2410 (0x25BAu)
2852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2411 (0x34CDu)
2853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2412 (0x192Fu)
2854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2413 (0x7C2Cu)
2855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2414 (0x07CEu)
2856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2415 (0x4AEAu)
2857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2416 (0x78C3u)
2858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2417 (0x7853u)
2859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2418 (0x19B5u)
2860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2419 (0x686Bu)
2861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2420 (0x34E3u)
2862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2421 (0x1CADu)
2863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2422 (0x7913u)
2864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2423 (0x2DB1u)
2865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2424 (0x32D9u)
2866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2425 (0x6AA3u)
2867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2426 (0x554Bu)
2868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2427 (0x74A6u)
2869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2428 (0x355Au)
2870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2429 (0x5BC1u)
2871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2430 (0x199Bu)
2872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2431 (0x7147u)
2873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2432 (0x672Cu)
2874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2433 (0x4F52u)
2875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2434 (0x5356u)
2876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2435 (0x7E44u)
2877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2436 (0x2567u)
2878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2437 (0x447Du)
2879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2438 (0x13A7u)
2880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2439 (0x744Bu)
2881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2440 (0x057Du)
2882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2441 (0x2357u)
2883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2442 (0x5393u)
2884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2443 (0x614Fu)
2885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2444 (0x055Fu)
2886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2445 (0x7227u)
2887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2446 (0x57C2u)
2888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2447 (0x7961u)
2889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2448 (0x3A33u)
2890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2449 (0x18AFu)
2891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2450 (0x658Bu)
2892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2451 (0x1F91u)
2893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2452 (0x3BD0u)
2894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2453 (0x3F44u)
2895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2454 (0x4D72u)
2896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2455 (0x54D9u)
2897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2456 (0x2DE1u)
2898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2457 (0x4772u)
2899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2458 (0x26B5u)
2900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2459 (0x36C3u)
2901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2460 (0x1FC4u)
2902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2461 (0x05DDu)
2903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2462 (0x0BE3u)
2904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2463 (0x4AF8u)
2905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2464 (0x2B2Bu)
2906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2465 (0x07E5u)
2907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2466 (0x245Fu)
2908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2467 (0x3D25u)
2909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2468 (0x5EC4u)
2910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2469 (0x69D1u)
2911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2470 (0x174Du)
2912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2471 (0x3563u)
2913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2472 (0x07EAu)
2914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2473 (0x32ABu)
2915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2474 (0x25D3u)
2916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2475 (0x35D8u)
2917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2476 (0x3275u)
2918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2477 (0x3647u)
2919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2478 (0x6E4Au)
2920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2479 (0x27D4u)
2921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2480 (0x6D70u)
2922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2481 (0x6752u)
2923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2482 (0x7C52u)
2924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2483 (0x343Eu)
2925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2484 (0x272Eu)
2926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2485 (0x7AE0u)
2927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2486 (0x1BA6u)
2928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2487 (0x51D3u)
2929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2488 (0x2EAAu)
2930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2489 (0x20FBu)
2931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2490 (0x2E65u)
2932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2491 (0x4CC7u)
2933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2492 (0x2CF8u)
2934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2493 (0x66E2u)
2935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2494 (0x353Au)
2936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2495 (0x2F15u)
2937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2496 (0x3A96u)
2938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2497 (0x24F5u)
2939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2498 (0x2A7Cu)
2940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2499 (0x4277u)
2941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2500 (0x58D9u)
2942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2501 (0x1DC6u)
2943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2502 (0x4ACEu)
2944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2503 (0x0377u)
2945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2504 (0x358Eu)
2946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2505 (0x4B8Du)
2947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2506 (0x6E15u)
2948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2507 (0x0ECDu)
2949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2508 (0x7C8Cu)
2950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2509 (0x4CD5u)
2951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2510 (0x6699u)
2952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2511 (0x64F1u)
2953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2512 (0x75C4u)
2954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2513 (0x665Au)
2955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2514 (0x5A47u)
2956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2515 (0x51DAu)
2957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2516 (0x7A45u)
2958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2517 (0x6B07u)
2959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2518 (0x312Fu)
2960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2519 (0x338Du)
2961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2520 (0x17C3u)
2962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2521 (0x7A68u)
2963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2522 (0x44FCu)
2964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2523 (0x532Bu)
2965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2524 (0x30DEu)
2966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2525 (0x5798u)
2967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2526 (0x31CDu)
2968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2527 (0x3A72u)
2969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2528 (0x5DC8u)
2970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2529 (0x5CC9u)
2971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2530 (0x5770u)
2972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2531 (0x2765u)
2973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2532 (0x5D8Au)
2974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2533 (0x1AE3u)
2975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2534 (0x1B56u)
2976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2535 (0x5339u)
2977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2536 (0x7925u)
2978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2537 (0x5947u)
2979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2538 (0x6AC9u)
2980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2539 (0x4679u)
2981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2540 (0x570Bu)
2982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2541 (0x66D8u)
2983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2542 (0x18F3u)
2984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2543 (0x652Bu)
2985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2544 (0x5758u)
2986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2545 (0x568Eu)
2987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2546 (0x692Bu)
2988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2547 (0x479Au)
2989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2548 (0x1CE6u)
2990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2549 (0x2ADCu)
2991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2550 (0x7748u)
2992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2551 (0x346Eu)
2993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2552 (0x754Cu)
2994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2553 (0x720Fu)
2995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2554 (0x1AE9u)
2996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2555 (0x14F5u)
2997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2556 (0x5A2Eu)
2998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2557 (0x56A5u)
2999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2558 (0x2F0Du)
3000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2559 (0x2D1Bu)
3001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2560 (0x0EE9u)
3002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2561 (0x11F5u)
3003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2562 (0x28F6u)
3004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2563 (0x22FAu)
3005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2564 (0x3F48u)
3006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2565 (0x0E79u)
3007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2566 (0x6DC2u)
3008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2567 (0x64D6u)
3009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2568 (0x7236u)
3010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2569 (0x4B3Au)
3011 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2570 (0x7316u)
3012 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2571 (0x36CAu)
3013 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2572 (0x61F1u)
3014 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2573 (0x439Du)
3015 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2574 (0x7991u)
3016 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2575 (0x14EEu)
3017 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2576 (0x65D4u)
3018 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2577 (0x2A5Du)
3019 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2578 (0x19DCu)
3020 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2579 (0x55C6u)
3021 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2580 (0x1BD8u)
3022 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2581 (0x69C9u)
3023 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2582 (0x6974u)
3024 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2583 (0x6E89u)
3025 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2584 (0x561Bu)
3026 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2585 (0x69F0u)
3027 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2586 (0x43ECu)
3028 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2587 (0x3D83u)
3029 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2588 (0x366Cu)
3030 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2589 (0x47B1u)
3031 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2590 (0x68CBu)
3032 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2591 (0x7538u)
3033 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2592 (0x6AB2u)
3034 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2593 (0x3335u)
3035 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2594 (0x56A9u)
3036 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2595 (0x58D3u)
3037 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2596 (0x74D8u)
3038 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2597 (0x0FCCu)
3039 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2598 (0x3C1Eu)
3040 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2599 (0x0B9Du)
3041 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2600 (0x6E34u)
3042 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2601 (0x4CA7u)
3043 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2602 (0x1B87u)
3044 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2603 (0x34F8u)
3045 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2604 (0x1C3Du)
3046 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2605 (0x60BDu)
3047 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2606 (0x38D5u)
3048 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2607 (0x4B66u)
3049 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2608 (0x345Eu)
3050 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2609 (0x1771u)
3051 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2610 (0x688Fu)
3052 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2611 (0x3CCCu)
3053 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2612 (0x6E54u)
3054 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2613 (0x6A99u)
3055 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2614 (0x58A7u)
3056 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2615 (0x0F47u)
3057 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2616 (0x2CEAu)
3058 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2617 (0x24BBu)
3059 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2618 (0x2F58u)
3060 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2619 (0x1B36u)
3061 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2620 (0x66B4u)
3062 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2621 (0x50E7u)
3063 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2622 (0x0D97u)
3064 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2623 (0x5655u)
3065 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2624 (0x1F4Cu)
3066 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2625 (0x1373u)
3067 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2626 (0x590Fu)
3068 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2627 (0x71A5u)
3069 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2628 (0x2B63u)
3070 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2629 (0x784Du)
3071 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2630 (0x46D6u)
3072 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2631 (0x39E1u)
3073 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2632 (0x2D65u)
3074 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2633 (0x6A17u)
3075 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2634 (0x33E1u)
3076 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2635 (0x342Fu)
3077 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2636 (0x0A6Fu)
3078 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2637 (0x2A76u)
3079 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2638 (0x4673u)
3080 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2639 (0x5E34u)
3081 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2640 (0x5372u)
3082 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2641 (0x2C3Du)
3083 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2642 (0x0EEAu)
3084 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2643 (0x5D70u)
3085 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2644 (0x4F4Au)
3086 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2645 (0x361Eu)
3087 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2646 (0x33AAu)
3088 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2647 (0x3EB0u)
3089 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2648 (0x0DCDu)
3090 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2649 (0x4E8Du)
3091 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2650 (0x2F2Cu)
3092 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2651 (0x365Au)
3093 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2652 (0x5A4Du)
3094 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2653 (0x5A74u)
3095 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2654 (0x61ECu)
3096 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2655 (0x1D72u)
3097 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2656 (0x7A26u)
3098 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2657 (0x53B8u)
3099 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2658 (0x78F0u)
3100 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2659 (0x23E6u)
3101 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2660 (0x56D2u)
3102 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2661 (0x2CDAu)
3103 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2662 (0x3A1Bu)
3104 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2663 (0x159Du)
3105 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2664 (0x18FAu)
3106 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2665 (0x7C94u)
3107 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2666 (0x25E9u)
3108 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2667 (0x1BB8u)
3109 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2668 (0x25F8u)
3110 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2669 (0x3C17u)
3111 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2670 (0x2FB0u)
3112 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2671 (0x65A3u)
3113 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2672 (0x634Eu)
3114 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2673 (0x0CEDu)
3115 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2674 (0x05D7u)
3116 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2675 (0x6D62u)
3117 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2676 (0x65C3u)
3118 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2677 (0x55E8u)
3119 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2678 (0x199Eu)
3120 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2679 (0x65C6u)
3121 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2680 (0x6E8Cu)
3122 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2681 (0x42FCu)
3123 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2682 (0x1DE1u)
3124 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2683 (0x4C4Fu)
3125 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2684 (0x40F7u)
3126 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2685 (0x7EC0u)
3127 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2686 (0x0B7Au)
3128 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2687 (0x7A91u)
3129 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2688 (0x6D52u)
3130 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2689 (0x4E8Eu)
3131 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2690 (0x492Fu)
3132 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2691 (0x3A93u)
3133 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2692 (0x35C5u)
3134 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2693 (0x6CE1u)
3135 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2694 (0x33D8u)
3136 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2695 (0x0CF5u)
3137 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2696 (0x66CCu)
3138 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2697 (0x716Cu)
3139 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2698 (0x16E3u)
3140 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2699 (0x42F6u)
3141 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2700 (0x593Cu)
3142 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2701 (0x3F18u)
3143 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2702 (0x264Fu)
3144 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2703 (0x1755u)
3145 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2704 (0x6E64u)
3146 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2705 (0x55F0u)
3147 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2706 (0x5B43u)
3148 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2707 (0x4AE5u)
3149 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2708 (0x74E2u)
3150 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2709 (0x4763u)
3151 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2710 (0x59A5u)
3152 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2711 (0x252Fu)
3153 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2712 (0x6AACu)
3154 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2713 (0x4D96u)
3155 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2714 (0x2C7Au)
3156 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2715 (0x4B2Bu)
3157 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2716 (0x21AFu)
3158 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2717 (0x4E9Au)
3159 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2718 (0x1D95u)
3160 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2719 (0x391Du)
3161 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2720 (0x7782u)
3162 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2721 (0x2BC6u)
3163 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2722 (0x23EAu)
3164 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2723 (0x69A6u)
3165 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2724 (0x354Eu)
3166 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2725 (0x2EB8u)
3167 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2726 (0x1D55u)
3168 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2727 (0x2DC9u)
3169 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2728 (0x652Eu)
3170 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2729 (0x5C4Bu)
3171 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2730 (0x6C55u)
3172 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2731 (0x167Au)
3173 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2732 (0x2BE8u)
3174 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2733 (0x15AEu)
3175 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2734 (0x6E52u)
3176 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2735 (0x7193u)
3177 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2736 (0x25ECu)
3178 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2737 (0x4D33u)
3179 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2738 (0x215Fu)
3180 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2739 (0x613Eu)
3181 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2740 (0x22DDu)
3182 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2741 (0x6665u)
3183 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2742 (0x7195u)
3184 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2743 (0x7A0Bu)
3185 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2744 (0x7362u)
3186 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2745 (0x6EA4u)
3187 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2746 (0x0DCEu)
3188 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2747 (0x7661u)
3189 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2748 (0x63D8u)
3190 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2749 (0x4979u)
3191 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2750 (0x25CEu)
3192 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2751 (0x5F28u)
3193 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2752 (0x5327u)
3194 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2753 (0x0F72u)
3195 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2754 (0x0A3Fu)
3196 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2755 (0x0CD7u)
3197 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2756 (0x48E7u)
3198 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2757 (0x63CCu)
3199 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2758 (0x2E99u)
3200 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2759 (0x117Eu)
3201 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2760 (0x2A6Bu)
3202 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2761 (0x4CEAu)
3203 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2762 (0x4BB8u)
3204 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2763 (0x1ED2u)
3205 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2764 (0x2EC9u)
3206 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2765 (0x385Bu)
3207 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2766 (0x16B6u)
3208 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2767 (0x32F8u)
3209 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2768 (0x69CCu)
3210 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2769 (0x433Bu)
3211 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2770 (0x35B2u)
3212 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2771 (0x1E87u)
3213 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2772 (0x6E45u)
3214 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2773 (0x61F8u)
3215 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2774 (0x7525u)
3216 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2775 (0x547Cu)
3217 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2776 (0x63AAu)
3218 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2777 (0x1717u)
3219 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2778 (0x1C76u)
3220 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2779 (0x7F40u)
3221 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2780 (0x3A69u)
3222 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2781 (0x4C3Bu)
3223 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2782 (0x497Cu)
3224 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2783 (0x6F30u)
3225 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2784 (0x29D5u)
3226 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2785 (0x55D2u)
3227 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2786 (0x5473u)
3228 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2787 (0x70F8u)
3229 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2788 (0x2C76u)
3230 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2789 (0x02F7u)
3231 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2790 (0x3A71u)
3232 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2791 (0x0E3Bu)
3233 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2792 (0x03F6u)
3234 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2793 (0x33B4u)
3235 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2794 (0x542Fu)
3236 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2795 (0x6E29u)
3237 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2796 (0x515Bu)
3238 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2797 (0x11EBu)
3239 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2798 (0x7255u)
3240 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2799 (0x663Cu)
3241 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2800 (0x0EE5u)
3242 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2801 (0x7718u)
3243 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2802 (0x50F3u)
3244 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2803 (0x1B93u)
3245 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2804 (0x729Cu)
3246 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2805 (0x5AB4u)
3247 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2806 (0x319Du)
3248 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2807 (0x6C36u)
3249 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2808 (0x48BDu)
3250 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2809 (0x3693u)
3251 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2810 (0x2A57u)
3252 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2811 (0x5D0Bu)
3253 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2812 (0x1B55u)
3254 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2813 (0x790Bu)
3255 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2814 (0x42BEu)
3256 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2815 (0x13B5u)
3257 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2816 (0x2CCEu)
3258 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2817 (0x23F8u)
3259 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2818 (0x7B90u)
3260 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2819 (0x1937u)
3261 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2820 (0x543Bu)
3262 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2821 (0x5D92u)
3263 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2822 (0x256Bu)
3264 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2823 (0x6F88u)
3265 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2824 (0x139Bu)
3266 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2825 (0x5F0Cu)
3267 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2826 (0x7343u)
3268 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2827 (0x096Fu)
3269 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2828 (0x4F64u)
3270 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2829 (0x7235u)
3271 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2830 (0x68D9u)
3272 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2831 (0x7DC0u)
3273 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2832 (0x38E9u)
3274 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2833 (0x3C93u)
3275 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2834 (0x385Eu)
3276 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2835 (0x38E5u)
3277 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2836 (0x19EAu)
3278 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2837 (0x2C75u)
3279 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2838 (0x6CA5u)
3280 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2839 (0x7338u)
3281 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2840 (0x2CBCu)
3282 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2841 (0x3935u)
3283 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2842 (0x506Fu)
3284 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2843 (0x5D85u)
3285 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2844 (0x15ADu)
3286 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2845 (0x53B4u)
3287 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2846 (0x731Au)
3288 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2847 (0x3559u)
3289 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2848 (0x24F9u)
3290 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2849 (0x68E5u)
3291 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2850 (0x3B38u)
3292 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2851 (0x4BE4u)
3293 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2852 (0x299Du)
3294 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2853 (0x59E1u)
3295 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2854 (0x3B83u)
3296 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2855 (0x2AE5u)
3297 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2856 (0x07D6u)
3298 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2857 (0x52B9u)
3299 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2858 (0x6635u)
3300 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2859 (0x1F25u)
3301 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2860 (0x7391u)
3302 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2861 (0x37C1u)
3303 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2862 (0x06F3u)
3304 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2863 (0x19F8u)
3305 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2864 (0x4EB1u)
3306 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2865 (0x1E72u)
3307 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2866 (0x4B4Du)
3308 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2867 (0x31F1u)
3309 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2868 (0x3978u)
3310 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2869 (0x6A55u)
3311 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2870 (0x0EECu)
3312 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2871 (0x5E92u)
3313 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2872 (0x685Du)
3314 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2873 (0x2DA5u)
3315 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2874 (0x3DA1u)
3316 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2875 (0x439Bu)
3317 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2876 (0x7570u)
3318 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2877 (0x48CFu)
3319 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2878 (0x595Au)
3320 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2879 (0x513Eu)
3321 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2880 (0x0BABu)
3322 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2881 (0x61CDu)
3323 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2882 (0x60F3u)
3324 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2883 (0x50B7u)
3325 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2884 (0x1B47u)
3326 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2885 (0x1B74u)
3327 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2886 (0x5BB0u)
3328 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2887 (0x31F8u)
3329 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2888 (0x13B9u)
3330 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2889 (0x6F0Au)
3331 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2890 (0x3167u)
3332 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2891 (0x60FCu)
3333 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2892 (0x7989u)
3334 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2893 (0x3695u)
3335 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2894 (0x4B3Cu)
3336 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2895 (0x7A4Cu)
3337 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2896 (0x5B52u)
3338 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2897 (0x4AD5u)
3339 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2898 (0x68DAu)
3340 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2899 (0x15E3u)
3341 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2900 (0x572Cu)
3342 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2901 (0x730Eu)
3343 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2902 (0x369Cu)
3344 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2903 (0x5A39u)
3345 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2904 (0x4ECAu)
3346 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2905 (0x5DE0u)
3347 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2906 (0x7728u)
3348 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2907 (0x6F48u)
3349 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2908 (0x077Au)
3350 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2909 (0x69E4u)
3351 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2910 (0x2739u)
3352 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2911 (0x19B9u)
3353 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2912 (0x6497u)
3354 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2913 (0x2C8Fu)
3355 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2914 (0x1637u)
3356 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2915 (0x316Du)
3357 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2916 (0x3F24u)
3358 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2917 (0x0B67u)
3359 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2918 (0x3AACu)
3360 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2919 (0x227Bu)
3361 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2920 (0x15CBu)
3362 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2921 (0x658Eu)
3363 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2922 (0x3D16u)
3364 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2923 (0x6E92u)
3365 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2924 (0x2E0Fu)
3366 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2925 (0x494Fu)
3367 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2926 (0x2B66u)
3368 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2927 (0x2C67u)
3369 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2928 (0x7896u)
3370 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2929 (0x31E5u)
3371 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2930 (0x4579u)
3372 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2931 (0x1B8Eu)
3373 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2932 (0x2576u)
3374 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2933 (0x3437u)
3375 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2934 (0x3AE4u)
3376 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2935 (0x73A8u)
3377 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2936 (0x74AAu)
3378 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2937 (0x5C35u)
3379 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2938 (0x0CE7u)
3380 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2939 (0x7619u)
3381 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2940 (0x79B0u)
3382 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2941 (0x1EA5u)
3383 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2942 (0x623Bu)
3384 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2943 (0x547Au)
3385 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2944 (0x12CFu)
3386 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2945 (0x4CBCu)
3387 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2946 (0x2AD5u)
3388 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2947 (0x2CD9u)
3389 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2948 (0x1DA3u)
3390 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2949 (0x691Bu)
3391 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2950 (0x7A85u)
3392 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2951 (0x4796u)
3393 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2952 (0x66C6u)
3394 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2953 (0x4D8Eu)
3395 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2954 (0x535Au)
3396 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2955 (0x3D4Au)
3397 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2956 (0x23BCu)
3398 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2957 (0x6E8Au)
3399 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2958 (0x48BEu)
3400 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2959 (0x5867u)
3401 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2960 (0x41F3u)
3402 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2961 (0x5CE8u)
3403 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2962 (0x1CE5u)
3404 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2963 (0x5CD8u)
3405 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2964 (0x3A39u)
3406 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2965 (0x3678u)
3407 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2966 (0x35D2u)
3408 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2967 (0x5956u)
3409 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2968 (0x7E82u)
3410 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2969 (0x0FAAu)
3411 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2970 (0x2ECCu)
3412 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2971 (0x63D2u)
3413 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2972 (0x5B85u)
3414 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2973 (0x617Au)
3415 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2974 (0x7562u)
3416 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2975 (0x2A67u)
3417 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2976 (0x368Bu)
3418 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2977 (0x79E0u)
3419 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2978 (0x4F45u)
3420 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2979 (0x3197u)
3421 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2980 (0x5C53u)
3422 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2981 (0x0CBDu)
3423 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2982 (0x2E59u)
3424 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2983 (0x527Cu)
3425 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2984 (0x770Cu)
3426 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2985 (0x2A5Bu)
3427 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2986 (0x2BD4u)
3428 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2987 (0x2E5Cu)
3429 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2988 (0x42BBu)
3430 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2989 (0x76C2u)
3431 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2990 (0x6BD0u)
3432 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2991 (0x3E54u)
3433 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2992 (0x6F14u)
3434 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2993 (0x6966u)
3435 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2994 (0x2CE6u)
3436 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2995 (0x664Du)
3437 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2996 (0x62DCu)
3438 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2997 (0x31A7u)
3439 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2998 (0x2F19u)
3440 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2999 (0x6A33u)
3441 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3000 (0x2BCAu)
3442 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3001 (0x4EC3u)
3443 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3002 (0x6AE1u)
3444 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3003 (0x2F0Bu)
3445 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3004 (0x2F38u)
3446 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3005 (0x493Du)
3447 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3006 (0x15D5u)
3448 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3007 (0x1A7Cu)
3449 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3008 (0x3DA8u)
3450 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3009 (0x5EC8u)
3451 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3010 (0x12E7u)
3452 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3011 (0x7629u)
3453 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3012 (0x62B5u)
3454 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3013 (0x6669u)
3455 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3014 (0x7D0Cu)
3456 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3015 (0x187Bu)
3457 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3016 (0x4BE8u)
3458 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3017 (0x3399u)
3459 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3018 (0x332Eu)
3460 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3019 (0x0B9Eu)
3461 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3020 (0x68F1u)
3462 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3021 (0x70CEu)
3463 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3022 (0x69A5u)
3464 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3023 (0x4AD9u)
3465 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3024 (0x2CE9u)
3466 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3025 (0x4367u)
3467 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3026 (0x28F5u)
3468 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3027 (0x3AE8u)
3469 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3028 (0x19C7u)
3470 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3029 (0x0DD3u)
3471 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3030 (0x1787u)
3472 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3031 (0x3BC2u)
3473 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3032 (0x1DE2u)
3474 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3033 (0x6599u)
3475 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3034 (0x7079u)
3476 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3035 (0x4DAAu)
3477 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3036 (0x5317u)
3478 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3037 (0x4F2Cu)
3479 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3038 (0x7D09u)
3480 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3039 (0x18F6u)
3481 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3040 (0x17A9u)
3482 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3041 (0x706Du)
3483 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3042 (0x02DFu)
3484 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3043 (0x3666u)
3485 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3044 (0x64DCu)
3486 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3045 (0x5635u)
3487 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3046 (0x03DEu)
3488 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3047 (0x1DE4u)
3489 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3048 (0x7CC1u)
3490 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3049 (0x48DBu)
3491 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3050 (0x6CB2u)
3492 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3051 (0x68CDu)
3493 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3052 (0x2979u)
3494 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3053 (0x52F1u)
3495 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3054 (0x26C7u)
3496 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3055 (0x2BD2u)
3497 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3056 (0x5347u)
3498 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3057 (0x372Cu)
3499 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3058 (0x41EBu)
3500 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3059 (0x0E9Du)
3501 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3060 (0x0B5Eu)
3502 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3061 (0x07E6u)
3503 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3062 (0x1B96u)
3504 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3063 (0x5A78u)
3505 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3064 (0x09EEu)
3506 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3065 (0x45ABu)
3507 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3066 (0x37A2u)
3508 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3067 (0x0FD2u)
3509 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3068 (0x45BAu)
3510 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3069 (0x15F1u)
3511 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3070 (0x515Eu)
3512 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3071 (0x7272u)
3513 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3072 (0x388Fu)
3514 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3073 (0x1F2Au)
3515 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3074 (0x287Eu)
3516 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3075 (0x7A0Eu)
3517 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3076 (0x72CAu)
3518 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3077 (0x1E2Bu)
3519 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3078 (0x25D6u)
3520 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3079 (0x2D56u)
3521 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3080 (0x478Du)
3522 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3081 (0x1BAAu)
3523 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3082 (0x79C8u)
3524 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3083 (0x6A0Fu)
3525 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3084 (0x6A8Du)
3526 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3085 (0x0BCEu)
3527 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3086 (0x67B0u)
3528 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3087 (0x2D17u)
3529 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3088 (0x394Bu)
3530 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3089 (0x70ADu)
3531 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3090 (0x26ABu)
3532 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3091 (0x1BACu)
3533 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3092 (0x49D6u)
3534 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3093 (0x4CCEu)
3535 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3094 (0x5875u)
3536 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3095 (0x7037u)
3537 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3096 (0x543Eu)
3538 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3097 (0x714Eu)
3539 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3098 (0x7293u)
3540 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3099 (0x6B34u)
3541 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3100 (0x7781u)
3542 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3101 (0x4BB1u)
3543 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3102 (0x4D47u)
3544 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3103 (0x71C5u)
3545 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3104 (0x1C79u)
3546 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3105 (0x1477u)
3547 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3106 (0x661Eu)
3548 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3107 (0x26AEu)
3549 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3108 (0x0ED6u)
3550 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3109 (0x68B9u)
3551 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3110 (0x374Au)
3552 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3111 (0x5267u)
3553 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3112 (0x636Au)
3554 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3113 (0x69C6u)
3555 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3114 (0x7668u)
3556 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3115 (0x417Eu)
3557 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3116 (0x4E96u)
3558 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3117 (0x147Bu)
3559 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3118 (0x378Au)
3560 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3119 (0x14BBu)
3561 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3120 (0x17E4u)
3562 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3121 (0x483Fu)
3563 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3122 (0x63E4u)
3564 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3123 (0x78D4u)
3565 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3124 (0x7133u)
3566 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3125 (0x0B8Fu)
3567 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3126 (0x7D41u)
3568 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3127 (0x1D69u)
3569 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3128 (0x6AE2u)
3570 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3129 (0x4676u)
3571 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3130 (0x698Bu)
3572 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3131 (0x790Du)
3573 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3132 (0x7169u)
3574 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3133 (0x4573u)
3575 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3134 (0x6457u)
3576 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3135 (0x27B1u)
3577 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3136 (0x09BBu)
3578 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3137 (0x3A78u)
3579 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3138 (0x1D17u)
3580 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3139 (0x15C7u)
3581 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3140 (0x1CECu)
3582 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3141 (0x6CCAu)
3583 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3142 (0x656Cu)
3584 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3143 (0x5E51u)
3585 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3144 (0x2D4Du)
3586 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3145 (0x3457u)
3587 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3146 (0x2975u)
3588 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3147 (0x05FCu)
3589 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3148 (0x5D26u)
3590 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3149 (0x7385u)
3591 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3150 (0x51E6u)
3592 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3151 (0x2679u)
3593 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3152 (0x2E3Au)
3594 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3153 (0x35B8u)
3595 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3154 (0x3F0Cu)
3596 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3155 (0x095Fu)
3597 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3156 (0x587Au)
3598 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3157 (0x7C70u)
3599 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3158 (0x463Bu)
3600 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3159 (0x696Au)
3601 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3160 (0x3A74u)
3602 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3161 (0x03EEu)
3603 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3162 (0x47A6u)
3604 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3163 (0x61D6u)
3605 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3164 (0x267Au)
3606 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3165 (0x791Au)
3607 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3166 (0x79A8u)
3608 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3167 (0x7664u)
3609 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3168 (0x6369u)
3610 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3169 (0x36D4u)
3611 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3170 (0x6955u)
3612 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3171 (0x7705u)
3613 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3172 (0x36CCu)
3614 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3173 (0x07B9u)
3615 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3174 (0x711Eu)
3616 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3175 (0x5F09u)
3617 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3176 (0x565Cu)
3618 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3177 (0x71E2u)
3619 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3178 (0x07BCu)
3620 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3179 (0x6F03u)
3621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3180 (0x741Bu)
3622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3181 (0x5A55u)
3623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3182 (0x16D6u)
3624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3183 (0x326Bu)
3625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3184 (0x7AA4u)
3626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3185 (0x1CD6u)
3627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3186 (0x453Bu)
3628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3187 (0x05CFu)
3629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3188 (0x097Du)
3630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3189 (0x6639u)
3631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3190 (0x4A8Fu)
3632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3191 (0x2D55u)
3633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3192 (0x511Fu)
3634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3193 (0x175Au)
3635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3194 (0x5EA1u)
3636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3195 (0x1F45u)
3637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3196 (0x436Du)
3638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3197 (0x66D1u)
3639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3198 (0x563Au)
3640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3199 (0x0DD9u)
3641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3200 (0x4D93u)
3642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3201 (0x5719u)
3643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3202 (0x3AE2u)
3644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3203 (0x1E3Cu)
3645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3204 (0x335Cu)
3646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3205 (0x2BC9u)
3647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3206 (0x3E70u)
3648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3207 (0x0F66u)
3649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3208 (0x55CAu)
3650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3209 (0x70BCu)
3651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3210 (0x45DCu)
3652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3211 (0x2DB2u)
3653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3212 (0x338Bu)
3654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3213 (0x34A7u)
3655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3214 (0x06EDu)
3656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3215 (0x6D32u)
3657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3216 (0x7C13u)
3658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3217 (0x634Bu)
3659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3218 (0x0BE6u)
3660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3219 (0x4D5Cu)
3661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3220 (0x4F94u)
3662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3221 (0x716Au)
3663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3222 (0x3971u)
3664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3223 (0x705Bu)
3665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3224 (0x5D61u)
3666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3225 (0x7872u)
3667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3226 (0x723Cu)
3668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3227 (0x394Eu)
3669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3228 (0x3363u)
3670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3229 (0x6396u)
3671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3230 (0x34EAu)
3672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3231 (0x0D75u)
3673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3232 (0x6723u)
3674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3233 (0x325Bu)
3675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3234 (0x58ADu)
3676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3235 (0x5D89u)
3677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3236 (0x296Bu)
3678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3237 (0x0DDCu)
3679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3238 (0x1F58u)
3680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3239 (0x7B06u)
3681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3240 (0x74C5u)
3682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3241 (0x0A77u)
3683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3242 (0x7B22u)
3684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3243 (0x352Bu)
3685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3244 (0x3A4Eu)
3686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3245 (0x1EB4u)
3687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3246 (0x6C66u)
3688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3247 (0x545Eu)
3689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3248 (0x54F1u)
3690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3249 (0x585Du)
3691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3250 (0x5C2Du)
3692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3251 (0x2CECu)
3693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3252 (0x7847u)
3694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3253 (0x036Fu)
3695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3254 (0x7698u)
3696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3255 (0x72C9u)
3697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3256 (0x1FC2u)
3698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3257 (0x4A73u)
3699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3258 (0x7499u)
3700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3259 (0x78C5u)
3701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3260 (0x03EBu)
3702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3261 (0x4C1Fu)
3703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3262 (0x31C7u)
3704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3263 (0x5A63u)
3705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3264 (0x5C3Au)
3706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3265 (0x63E1u)
3707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3266 (0x7389u)
3708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3267 (0x5695u)
3709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3268 (0x6AF0u)
3710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3269 (0x23C7u)
3711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3270 (0x607Du)
3712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3271 (0x66CAu)
3713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3272 (0x631Bu)
3714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3273 (0x057Eu)
3715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3274 (0x568Du)
3716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3275 (0x2E33u)
3717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3276 (0x3179u)
3718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3277 (0x5A99u)
3719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3278 (0x7592u)
3720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3279 (0x6372u)
3721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3280 (0x794Au)
3722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3281 (0x0F69u)
3723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3282 (0x5C72u)
3724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3283 (0x4A3Eu)
3725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3284 (0x49F4u)
3726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3285 (0x7253u)
3727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3286 (0x507Du)
3728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3287 (0x615Eu)
3729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3288 (0x4CABu)
3730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3289 (0x5D98u)
3731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3290 (0x1756u)
3732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3291 (0x53CAu)
3733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3292 (0x4EAAu)
3734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3293 (0x7383u)
3735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3294 (0x0D9Bu)
3736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3295 (0x139Eu)
3737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3296 (0x5E07u)
3738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3297 (0x0F56u)
3739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3298 (0x34F2u)
3740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3299 (0x7B11u)
3741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3300 (0x3875u)
3742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3301 (0x0DE6u)
3743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3302 (0x04FDu)
3744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3303 (0x43B6u)
3745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3304 (0x3857u)
3746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3305 (0x1ECAu)
3747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3306 (0x18DDu)
3748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3307 (0x1A1Fu)
3749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3308 (0x13DAu)
3750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3309 (0x4FB0u)
3751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3310 (0x6B43u)
3752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3311 (0x54B9u)
3753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3312 (0x5AB2u)
3754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3313 (0x3783u)
3755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3314 (0x4E3Au)
3756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3315 (0x3959u)
3757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3316 (0x0AF9u)
3758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3317 (0x463Du)
3759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3318 (0x7546u)
3760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3319 (0x4E27u)
3761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3320 (0x730Bu)
3762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3321 (0x4B1Eu)
3763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3322 (0x1753u)
3764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3323 (0x1F26u)
3765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3324 (0x343Du)
3766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3325 (0x7B21u)
3767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3326 (0x43ABu)
3768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3327 (0x4EA5u)
3769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3328 (0x38F2u)
3770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3329 (0x1F70u)
3771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3330 (0x0757u)
3772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3331 (0x4D3Cu)
3773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3332 (0x279Cu)
3774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3333 (0x74B1u)
3775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3334 (0x1F98u)
3776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3335 (0x1673u)
3777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3336 (0x313Eu)
3778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3337 (0x2D53u)
3779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3338 (0x0BBAu)
3780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3339 (0x0B7Cu)
3781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3340 (0x59D1u)
3782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3341 (0x69D4u)
3783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3342 (0x02FDu)
3784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3343 (0x5663u)
3785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3344 (0x0B76u)
3786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3345 (0x165Bu)
3787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3346 (0x7F20u)
3788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3347 (0x647Au)
3789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3348 (0x4756u)
3790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3349 (0x71B2u)
3791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3350 (0x7A8Au)
3792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3351 (0x2763u)
3793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3352 (0x2FA2u)
3794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3353 (0x353Cu)
3795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3354 (0x4BCAu)
3796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3355 (0x17E2u)
3797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3356 (0x3669u)
3798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3357 (0x067Du)
3799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3358 (0x27CAu)
3800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3359 (0x651Bu)
3801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3360 (0x0EF4u)
3802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3361 (0x0BADu)
3803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3362 (0x38A7u)
3804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3363 (0x7A2Au)
3805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3364 (0x6D4Au)
3806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3365 (0x49BAu)
3807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3366 (0x7334u)
3808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3367 (0x64ABu)
3809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3368 (0x709Eu)
3810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3369 (0x59C6u)
3811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3370 (0x768Cu)
3812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3371 (0x645Du)
3813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3372 (0x31BCu)
3814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3373 (0x4778u)
3815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3374 (0x1AF2u)
3816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3375 (0x14AFu)
3817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3376 (0x4BF0u)
3818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3377 (0x3671u)
3819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3378 (0x0D3Du)
3820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3379 (0x3B2Cu)
3821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3380 (0x7EA0u)
3822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3381 (0x5978u)
3823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3382 (0x7E88u)
3824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3383 (0x3C2Eu)
3825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3384 (0x2DD1u)
3826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3385 (0x361Bu)
3827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3386 (0x18BDu)
3828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3387 (0x429Fu)
3829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3388 (0x3C35u)
3830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3389 (0x239Bu)
3831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3390 (0x6D8Au)
3832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3391 (0x1EA6u)
3833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3392 (0x23F4u)
3834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3393 (0x1F38u)
3835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3394 (0x5C69u)
3836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3395 (0x28FCu)
3837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3396 (0x4F07u)
3838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3397 (0x7A16u)
3839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3398 (0x535Cu)
3840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3399 (0x0FA9u)
3841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3400 (0x45DAu)
3842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3401 (0x5B29u)
3843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3402 (0x0C7Bu)
3844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3403 (0x4F31u)
3845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3404 (0x4736u)
3846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3405 (0x1EC6u)
3847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3406 (0x6B4Cu)
3848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3407 (0x68A7u)
3849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3408 (0x798Cu)
3850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3409 (0x319Bu)
3851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3410 (0x25E5u)
3852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3411 (0x62B3u)
3853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3412 (0x237Cu)
3854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3413 (0x19A7u)
3855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3414 (0x13E6u)
3856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3415 (0x2EA6u)
3857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3416 (0x2F54u)
3858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3417 (0x329Du)
3859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3418 (0x69A9u)
3860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3419 (0x26F4u)
3861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3420 (0x443Fu)
3862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3421 (0x5569u)
3863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3422 (0x4C79u)
3864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3423 (0x2E3Cu)
3865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3424 (0x46BCu)
3866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3425 (0x263Du)
3867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3426 (0x6527u)
3868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3427 (0x6B61u)
3869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3428 (0x3297u)
3870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3429 (0x62D5u)
3871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3430 (0x3996u)
3872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3431 (0x138Fu)
3873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3432 (0x0D73u)
3874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3433 (0x794Cu)
3875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3434 (0x69A3u)
3876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3435 (0x39AAu)
3877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3436 (0x2D96u)
3878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3437 (0x4337u)
3879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3438 (0x78C9u)
3880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3439 (0x5D54u)
3881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3440 (0x459Eu)
3882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3441 (0x2D27u)
3883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3442 (0x5E0Bu)
3884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3443 (0x1C57u)
3885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3444 (0x6C4Eu)
3886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3445 (0x32B9u)
3887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3446 (0x2676u)
3888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3447 (0x6999u)
3889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3448 (0x348Fu)
3890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3449 (0x5A71u)
3891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3450 (0x516Bu)
3892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3451 (0x6395u)
3893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3452 (0x293Eu)
3894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3453 (0x26ADu)
3895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3454 (0x7A92u)
3896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3455 (0x259Bu)
3897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3456 (0x1675u)
3898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3457 (0x7516u)
3899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3458 (0x229Fu)
3900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3459 (0x4EE4u)
3901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3460 (0x332Du)
3902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3461 (0x3371u)
3903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3462 (0x5F03u)
3904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3463 (0x4A7Cu)
3905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3464 (0x0CEBu)
3906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3465 (0x4CF8u)
3907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3466 (0x788Du)
3908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3467 (0x44AFu)
3909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3468 (0x03DBu)
3910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3469 (0x5D19u)
3911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3470 (0x3939u)
3912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3471 (0x551Du)
3913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3472 (0x41DEu)
3914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3473 (0x493Bu)
3915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3474 (0x7839u)
3916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3475 (0x5F88u)
3917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3476 (0x56ACu)
3918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3477 (0x2F4Au)
3919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3478 (0x3A5Au)
3920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3479 (0x649Eu)
3921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3480 (0x6B49u)
3922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3481 (0x5A96u)
3923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3482 (0x1D1Bu)
3924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3483 (0x3CB4u)
3925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3484 (0x4AC7u)
3926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3485 (0x46F2u)
3927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3486 (0x4F70u)
3928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3487 (0x30F5u)
3929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3488 (0x11DDu)
3930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3489 (0x692Du)
3931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3490 (0x147Eu)
3932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3491 (0x2E6Cu)
3933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3492 (0x3CC6u)
3934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3493 (0x56B1u)
3935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3494 (0x34AEu)
3936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3495 (0x4DD1u)
3937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3496 (0x33F0u)
3938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3497 (0x3E23u)
3939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3498 (0x3F42u)
3940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3499 (0x6791u)
3941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3500 (0x2DE4u)
3942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3501 (0x663Au)
3943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3502 (0x54ECu)
3944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3503 (0x3CACu)
3945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3504 (0x3716u)
3946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3505 (0x2E1Bu)
3947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3506 (0x7C45u)
3948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3507 (0x707Cu)
3949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3508 (0x71A9u)
3950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3509 (0x57A8u)
3951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3510 (0x073Bu)
3952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3511 (0x705Eu)
3953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3512 (0x6D0Bu)
3954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3513 (0x65E1u)
3955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3514 (0x74D1u)
3956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3515 (0x6D07u)
3957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3516 (0x661Bu)
3958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3517 (0x74B4u)
3959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3518 (0x0EB6u)
3960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3519 (0x16F4u)
3961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3520 (0x5E58u)
3962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3521 (0x3732u)
3963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3522 (0x5A35u)
3964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3523 (0x2477u)
3965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3524 (0x30CFu)
3966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3525 (0x3EC1u)
3967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3526 (0x0DF4u)
3968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3527 (0x71D8u)
3969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3528 (0x178Bu)
3970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3529 (0x22B7u)
3971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3530 (0x35D4u)
3972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3531 (0x37A1u)
3973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3532 (0x5707u)
3974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3533 (0x702Fu)
3975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3534 (0x6B45u)
3976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3535 (0x4B6Au)
3977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3536 (0x17C6u)
3978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3537 (0x2B96u)
3979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3538 (0x6743u)
3980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3539 (0x6D98u)
3981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3540 (0x7C83u)
3982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3541 (0x71D4u)
3983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3542 (0x15DCu)
3984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3543 (0x3633u)
3985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3544 (0x64BCu)
3986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3545 (0x55A6u)
3987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3546 (0x1B0Fu)
3988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3547 (0x4E95u)
3989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3548 (0x368Eu)
3990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3549 (0x5355u)
3991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3550 (0x5C95u)
3992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3551 (0x0ED5u)
3993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3552 (0x472Bu)
3994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3553 (0x6D4Cu)
3995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3554 (0x6653u)
3996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3555 (0x32B3u)
3997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3556 (0x467Cu)
3998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3557 (0x2F26u)
3999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3558 (0x3A9Au)
4000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3559 (0x470Fu)
4001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3560 (0x554Eu)
4002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3561 (0x6D0Du)
4003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3562 (0x0BEAu)
4004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3563 (0x64AEu)
4005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3564 (0x4ACBu)
4006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3565 (0x1676u)
4007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3566 (0x6993u)
4008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3567 (0x2CF1u)
4009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3568 (0x170Fu)
4010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3569 (0x72CCu)
4011 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3570 (0x595Cu)
4012 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3571 (0x4B17u)
4013 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3572 (0x2BAAu)
4014 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3573 (0x2D5Cu)
4015 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3574 (0x785Cu)
4016 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3575 (0x13DCu)
4017 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3576 (0x3D0Du)
4018 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3577 (0x6CC6u)
4019 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3578 (0x66AAu)
4020 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3579 (0x4CECu)
4021 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3580 (0x16D9u)
4022 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3581 (0x6467u)
4023 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3582 (0x15CDu)
4024 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3583 (0x5A65u)
4025 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3584 (0x43AEu)
4026 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3585 (0x3798u)
4027 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3586 (0x60F5u)
4028 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3587 (0x455Du)
4029 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3588 (0x4F38u)
4030 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3589 (0x64A7u)
4031 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3590 (0x7616u)
4032 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3591 (0x2F89u)
4033 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3592 (0x4E4Du)
4034 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3593 (0x15F2u)
4035 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3594 (0x36C6u)
4036 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3595 (0x6355u)
4037 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3596 (0x544Fu)
4038 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3597 (0x7D22u)
4039 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3598 (0x39A5u)
4040 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3599 (0x5A8Eu)
4041 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3600 (0x2D87u)
4042 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3601 (0x465Eu)
4043 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3602 (0x761Au)
4044 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3603 (0x65F0u)
4045 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3604 (0x093Fu)
4046 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3605 (0x50DEu)
4047 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3606 (0x2F29u)
4048 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3607 (0x05BBu)
4049 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3608 (0x7722u)
4050 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3609 (0x709Du)
4051 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3610 (0x4E59u)
4052 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3611 (0x2B8Bu)
4053 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3612 (0x1F15u)
4054 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3613 (0x5DB0u)
4055 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3614 (0x6770u)
4056 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3615 (0x2F92u)
4057 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3616 (0x44BBu)
4058 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3617 (0x6B31u)
4059 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3618 (0x1967u)
4060 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3619 (0x626Bu)
4061 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3620 (0x3E49u)
4062 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3621 (0x62DAu)
4063 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3622 (0x76B0u)
4064 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3623 (0x40BFu)
4065 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3624 (0x625Du)
4066 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3625 (0x63E8u)
4067 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3626 (0x6FA0u)
4068 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3627 (0x1973u)
4069 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3628 (0x6875u)
4070 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3629 (0x56C9u)
4071 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3630 (0x3DA4u)
4072 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3631 (0x51E3u)
4073 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3632 (0x5AC9u)
4074 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3633 (0x4373u)
4075 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3634 (0x12DBu)
4076 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3635 (0x721Bu)
4077 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3636 (0x067Eu)
4078 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3637 (0x166Eu)
4079 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3638 (0x41F5u)
4080 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3639 (0x247Eu)
4081 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3640 (0x0AB7u)
4082 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3641 (0x4E6Au)
4083 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3642 (0x2573u)
4084 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3643 (0x3393u)
4085 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3644 (0x07AEu)
4086 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3645 (0x6595u)
4087 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3646 (0x5565u)
4088 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3647 (0x1EE8u)
4089 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3648 (0x3DC2u)
4090 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3649 (0x74A3u)
4091 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3650 (0x3CB2u)
4092 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3651 (0x6978u)
4093 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3652 (0x07CDu)
4094 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3653 (0x47B8u)
4095 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3654 (0x3D61u)
4096 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3655 (0x1F0Eu)
4097 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3656 (0x626Eu)
4098 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3657 (0x54A7u)
4099 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3658 (0x685Bu)
4100 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3659 (0x572Au)
4101 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3660 (0x358Bu)
4102 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3661 (0x4BD2u)
4103 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3662 (0x31D6u)
4104 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3663 (0x56E8u)
4105 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3664 (0x6EC2u)
4106 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3665 (0x38F1u)
4107 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3666 (0x7C34u)
4108 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3667 (0x664Eu)
4109 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3668 (0x1CABu)
4110 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3669 (0x6565u)
4111 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3670 (0x0A7Bu)
4112 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3671 (0x7199u)
4113 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3672 (0x19B6u)
4114 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3673 (0x48EDu)
4115 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3674 (0x07DCu)
4116 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3675 (0x08F7u)
4117 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3676 (0x6B98u)
4118 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3677 (0x329Eu)
4119 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3678 (0x74D2u)
4120 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3679 (0x71E8u)
4121 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3680 (0x0F65u)
4122 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3681 (0x5E83u)
4123 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3682 (0x2D35u)
4124 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3683 (0x3336u)
4125 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3684 (0x38DAu)
4126 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3685 (0x58DCu)
4127 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3686 (0x7B0Cu)
4128 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3687 (0x4CB3u)
4129 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3688 (0x61B3u)
4130 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3689 (0x4E2Bu)
4131 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3690 (0x26BCu)
4132 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3691 (0x55B2u)
4133 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3692 (0x3867u)
4134 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3693 (0x47CCu)
4135 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3694 (0x7C0Eu)
4136 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3695 (0x61ADu)
4137 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3696 (0x163Eu)
4138 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3697 (0x0D5Eu)
4139 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3698 (0x16E5u)
4140 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3699 (0x10DFu)
4141 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3700 (0x5F90u)
4142 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3701 (0x58CDu)
4143 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3702 (0x35C6u)
4144 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3703 (0x072Fu)
4145 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3704 (0x687Au)
4146 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3705 (0x1CB3u)
4147 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3706 (0x4E66u)
4148 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3707 (0x19F2u)
4149 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3708 (0x4AB5u)
4150 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3709 (0x55C5u)
4151 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3710 (0x589Eu)
4152 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3711 (0x5363u)
4153 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3712 (0x4D3Au)
4154 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3713 (0x169Eu)
4155 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3714 (0x197Cu)
4156 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3715 (0x6C39u)
4157 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3716 (0x6F11u)
4158 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3717 (0x1BD1u)
4159 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3718 (0x2B0Fu)
4160 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3719 (0x1F92u)
4161 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3720 (0x44DEu)
4162 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3721 (0x7692u)
4163 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3722 (0x7E48u)
4164 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3723 (0x4B63u)
4165 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3724 (0x52F2u)
4166 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3725 (0x6D68u)
4167 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3726 (0x2FE0u)
4168 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3727 (0x2657u)
4169 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3728 (0x5A6Au)
4170 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3729 (0x71C9u)
4171 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3730 (0x4B1Du)
4172 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3731 (0x27A3u)
4173 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3732 (0x6AE8u)
4174 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3733 (0x51ABu)
4175 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3734 (0x21DBu)
4176 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3735 (0x1E9Au)
4177 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3736 (0x7417u)
4178 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3737 (0x35A6u)
4179 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3738 (0x2ACEu)
4180 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3739 (0x3F05u)
4181 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3740 (0x6C47u)
4182 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3741 (0x2E2Eu)
4183 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3742 (0x12DDu)
4184 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3743 (0x1765u)
4185 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3744 (0x2B99u)
4186 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3745 (0x24F3u)
4187 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3746 (0x1AF4u)
4188 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3747 (0x4A9Bu)
4189 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3748 (0x0F4Eu)
4190 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3749 (0x562Du)
4191 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3750 (0x7E05u)
4192 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3751 (0x6713u)
4193 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3752 (0x1B17u)
4194 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3753 (0x32B6u)
4195 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3754 (0x6695u)
4196 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3755 (0x59CCu)
4197 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3756 (0x7127u)
4198 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3757 (0x0CFAu)
4199 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3758 (0x7513u)
4200 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3759 (0x71E1u)
4201 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3760 (0x78ACu)
4202 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3761 (0x5475u)
4203 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3762 (0x59C9u)
4204 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3763 (0x585Bu)
4205 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3764 (0x32BAu)
4206 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3765 (0x75C2u)
4207 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3766 (0x167Cu)
4208 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3767 (0x5E32u)
4209 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3768 (0x5993u)
4210 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3769 (0x233Eu)
4211 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3770 (0x4BACu)
4212 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3771 (0x3C63u)
4213 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3772 (0x4877u)
4214 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3773 (0x3B23u)
4215 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3774 (0x1A8Fu)
4216 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3775 (0x213Fu)
4217 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3776 (0x7589u)
4218 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3777 (0x5B32u)
4219 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3778 (0x1BC3u)
4220 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3779 (0x6AC3u)
4221 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3780 (0x438Fu)
4222 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3781 (0x61E5u)
4223 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3782 (0x70EAu)
4224 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3783 (0x30EEu)
4225 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3784 (0x5AD1u)
4226 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3785 (0x0ECEu)
4227 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3786 (0x5FC0u)
4228 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3787 (0x273Cu)
4229 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3788 (0x1E27u)
4230 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3789 (0x5CACu)
4231 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3790 (0x3ED0u)
4232 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3791 (0x6C72u)
4233 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3792 (0x7F04u)
4234 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3793 (0x70BAu)
4235 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3794 (0x19F1u)
4236 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3795 (0x6D31u)
4237 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3796 (0x7156u)
4238 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3797 (0x7712u)
4239 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3798 (0x12B7u)
4240 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3799 (0x598Du)
4241 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3800 (0x689Du)
4242 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3801 (0x5DA8u)
4243 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3802 (0x5556u)
4244 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3803 (0x172Eu)
4245 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3804 (0x7352u)
4246 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3805 (0x71B4u)
4247 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3806 (0x26E9u)
4248 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3807 (0x17A3u)
4249 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3808 (0x0CBBu)
4250 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3809 (0x669Cu)
4251 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3810 (0x5F50u)
4252 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3811 (0x687Cu)
4253 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3812 (0x2A73u)
4254 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3813 (0x3C53u)
4255 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3814 (0x360Fu)
4256 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3815 (0x594Du)
4257 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3816 (0x7392u)
4258 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3817 (0x4B8Eu)
4259 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3818 (0x38CBu)
4260 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3819 (0x7835u)
4261 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3820 (0x33C3u)
4262 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3821 (0x598Eu)
4263 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3822 (0x2D69u)
4264 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3823 (0x2DD2u)
4265 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3824 (0x7E21u)
4266 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3825 (0x71B1u)
4267 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3826 (0x4739u)
4268 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3827 (0x3C39u)
4269 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3828 (0x5593u)
4270 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3829 (0x42F3u)
4271 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3830 (0x4E3Cu)
4272 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3831 (0x0F39u)
4273 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3832 (0x7742u)
4274 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3833 (0x3E98u)
4275 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3834 (0x0F3Cu)
4276 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3835 (0x384Fu)
4277 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3836 (0x5D29u)
4278 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3837 (0x4CE3u)
4279 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3838 (0x6C8Bu)
4280 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3839 (0x6387u)
4281 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3840 (0x674Au)
4282 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3841 (0x586Du)
4283 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3842 (0x693Au)
4284 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3843 (0x63C3u)
4285 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3844 (0x54ABu)
4286 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3845 (0x1AABu)
4287 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3846 (0x333Cu)
4288 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3847 (0x7BA0u)
4289 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3848 (0x41BBu)
4290 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3849 (0x4B35u)
4291 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3850 (0x09F9u)
4292 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3851 (0x50AFu)
4293 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3852 (0x329Bu)
4294 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3853 (0x2A7Au)
4295 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3854 (0x7E0Cu)
4296 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3855 (0x05DBu)
4297 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3856 (0x59F0u)
4298 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3857 (0x72ACu)
4299 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3858 (0x3B85u)
4300 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3859 (0x2B5Au)
4301 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3860 (0x4FD0u)
4302 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3861 (0x249Fu)
4303 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3862 (0x13E3u)
4304 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3863 (0x68E3u)
4305 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3864 (0x62E6u)
4306 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3865 (0x2774u)
4307 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3866 (0x28FAu)
4308 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3867 (0x5D51u)
4309 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3868 (0x60DBu)
4310 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3869 (0x1DA5u)
4311 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3870 (0x6553u)
4312 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3871 (0x5A59u)
4313 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3872 (0x71D1u)
4314 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3873 (0x6ACCu)
4315 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3874 (0x40FDu)
4316 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3875 (0x59E2u)
4317 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3876 (0x50CFu)
4318 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3877 (0x770Au)
4319 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3878 (0x4F61u)
4320 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3879 (0x4B69u)
4321 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3880 (0x534Eu)
4322 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3881 (0x0EF2u)
4323 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3882 (0x45CEu)
4324 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3883 (0x2733u)
4325 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3884 (0x5157u)
4326 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3885 (0x29C7u)
4327 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3886 (0x09B7u)
4328 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3887 (0x6B68u)
4329 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3888 (0x45E6u)
4330 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3889 (0x2DC6u)
4331 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3890 (0x6A6Cu)
4332 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3891 (0x23D3u)
4333 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3892 (0x4177u)
4334 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3893 (0x54AEu)
4335 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3894 (0x56D8u)
4336 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3895 (0x73A2u)
4337 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3896 (0x27CCu)
4338 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3897 (0x5B91u)
4339 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3898 (0x2F1Cu)
4340 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3899 (0x3F12u)
4341 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3900 (0x0E5Du)
4342 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3901 (0x271Eu)
4343 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3902 (0x671Au)
4344 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3903 (0x4BE2u)
4345 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3904 (0x4976u)
4346 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3905 (0x5A1Du)
4347 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3906 (0x3F30u)
4348 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3907 (0x725Cu)
4349 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3908 (0x12D7u)
4350 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3909 (0x29E6u)
4351 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3910 (0x3749u)
4352 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3911 (0x49D5u)
4353 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3912 (0x466Du)
4354 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3913 (0x254Fu)
4355 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3914 (0x2A1Fu)
4356 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3915 (0x3786u)
4357 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3916 (0x7A62u)
4358 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3917 (0x79A1u)
4359 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3918 (0x7A1Au)
4360 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3919 (0x7D12u)
4361 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3920 (0x3E61u)
4362 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3921 (0x4F2Au)
4363 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3922 (0x2E63u)
4364 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3923 (0x3C87u)
4365 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3924 (0x09CFu)
4366 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3925 (0x68C7u)
4367 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3926 (0x5715u)
4368 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3927 (0x67A1u)
4369 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3928 (0x2EACu)
4370 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3929 (0x79C1u)
4371 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3930 (0x3267u)
4372 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3931 (0x4B36u)
4373 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3932 (0x5571u)
4374 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3933 (0x16B5u)
4375 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3934 (0x077Cu)
4376 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3935 (0x14FAu)
4377 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3936 (0x1D1Du)
4378 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3937 (0x5179u)
4379 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3938 (0x5AAAu)
4380 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3939 (0x4B99u)
4381 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3940 (0x1ABCu)
4382 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3941 (0x0E5Bu)
4383 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3942 (0x64D3u)
4384 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3943 (0x28B7u)
4385 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3944 (0x5C8Du)
4386 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3945 (0x4F0Eu)
4387 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3946 (0x7266u)
4388 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3947 (0x5527u)
4389 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3948 (0x1E65u)
4390 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3949 (0x626Du)
4391 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3950 (0x1CCDu)
4392 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3951 (0x51BCu)
4393 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3952 (0x11DBu)
4394 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3953 (0x6176u)
4395 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3954 (0x35A5u)
4396 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3955 (0x5DD0u)
4397 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3956 (0x2747u)
4398 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3957 (0x7583u)
4399 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3958 (0x3746u)
4400 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3959 (0x2575u)
4401 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3960 (0x33E4u)
4402 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3961 (0x1E36u)
4403 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3962 (0x2F8Cu)
4404 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3963 (0x3CE8u)
4405 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3964 (0x22EEu)
4406 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3965 (0x2E35u)
4407 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3966 (0x4AABu)
4408 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3967 (0x4D2Eu)
4409 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3968 (0x07BAu)
4410 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3969 (0x758Au)
4411 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3970 (0x631Eu)
4412 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3971 (0x3599u)
4413 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3972 (0x7551u)
4414 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3973 (0x6768u)
4415 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3974 (0x4BB4u)
4416 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3975 (0x7B09u)
4417 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3976 (0x74ACu)
4418 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3977 (0x26B3u)
4419 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3978 (0x72B1u)
4420 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3979 (0x7B81u)
4421 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3980 (0x56B4u)
4422 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3981 (0x2E56u)
4423 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3982 (0x474Bu)
4424 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3983 (0x445Fu)
4425 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3984 (0x43DCu)
4426 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3985 (0x7519u)
4427 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3986 (0x1D63u)
4428 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3987 (0x2BE4u)
4429 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3988 (0x265Du)
4430 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3989 (0x4CF2u)
4431 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3990 (0x5D07u)
4432 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3991 (0x0FC6u)
4433 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3992 (0x5999u)
4434 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3993 (0x27F0u)
4435 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3994 (0x6C69u)
4436 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3995 (0x1A37u)
4437 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3996 (0x627Au)
4438 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3997 (0x6687u)
4439 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3998 (0x24BDu)
4440 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3999 (0x5D38u)
4441 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4000 (0x0FACu)
4442 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4001 (0x3754u)
4443 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4002 (0x7351u)
4444 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4003 (0x0BD9u)
4445 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4004 (0x7919u)
4446 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4005 (0x28BBu)
4447 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4006 (0x3B15u)
4448 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4007 (0x34B3u)
4449 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4008 (0x3B62u)
4450 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4009 (0x2EA9u)
4451 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4010 (0x7694u)
4452 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4011 (0x54E3u)
4453 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4012 (0x6D61u)
4454 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4013 (0x5399u)
4455 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4014 (0x718Bu)
4456 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4015 (0x3B64u)
4457 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4016 (0x6333u)
4458 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4017 (0x1D47u)
4459 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4018 (0x31D3u)
4460 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4019 (0x5539u)
4461 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4020 (0x68ABu)
4462 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4021 (0x4E5Au)
4463 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4022 (0x3BC1u)
4464 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4023 (0x0EC7u)
4465 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4024 (0x74E1u)
4466 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4025 (0x193Du)
4467 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4026 (0x7332u)
4468 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4027 (0x287Bu)
4469 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4028 (0x13D6u)
4470 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4029 (0x43D6u)
4471 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4030 (0x38EAu)
4472 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4031 (0x3F22u)
4473 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4032 (0x6EC1u)
4474 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4033 (0x45A7u)
4475 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4034 (0x7B18u)
4476 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4035 (0x5E31u)
4477 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4036 (0x73C1u)
4478 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4037 (0x74E8u)
4479 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4038 (0x6C9Cu)
4480 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4039 (0x6ED0u)
4481 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4040 (0x1CAEu)
4482 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4041 (0x389Du)
4483 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4042 (0x5751u)
4484 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4043 (0x36C9u)
4485 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4044 (0x45C7u)
4486 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4045 (0x36A3u)
4487 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4046 (0x1575u)
4488 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4047 (0x7836u)
4489 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4048 (0x42F9u)
4490 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4049 (0x3A6Cu)
4491 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4050 (0x3347u)
4492 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4051 (0x2B4Bu)
4493 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4052 (0x27C9u)
4494 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4053 (0x15EAu)
4495 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4054 (0x48F6u)
4496 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4055 (0x6A95u)
4497 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4056 (0x3B1Au)
4498 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4057 (0x4B6Cu)
4499 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4058 (0x29A7u)
4500 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4059 (0x0EE3u)
4501 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4060 (0x4B56u)
4502 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4061 (0x5E15u)
4503 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4062 (0x22EDu)
4504 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4063 (0x43C7u)
4505 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4064 (0x1F1Au)
4506 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4065 (0x71E4u)
4507 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4066 (0x28EBu)
4508 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4067 (0x36E1u)
4509 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4068 (0x247Bu)
4510 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4069 (0x4F26u)
4511 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4070 (0x7D82u)
4512 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4071 (0x6674u)
4513 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4072 (0x04FBu)
4514 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4073 (0x531Bu)
4515 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4074 (0x5761u)
4516 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4075 (0x49D9u)
4517 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4076 (0x7B50u)
4518 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4077 (0x5732u)
4519 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4078 (0x2675u)
4520 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4079 (0x7478u)
4521 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4080 (0x3CA5u)
4522 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4081 (0x4B5Au)
4523 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4082 (0x4C57u)
4524 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4083 (0x6BE0u)
4525 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4084 (0x2C79u)
4526 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4085 (0x1B66u)
4527 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4086 (0x74B2u)
4528 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4087 (0x6E23u)
4529 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4088 (0x6C2Du)
4530 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4089 (0x03D7u)
4531 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4090 (0x5A33u)
4532 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4091 (0x3EC2u)
4533 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4092 (0x55D1u)
4534 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4093 (0x719Cu)
4535 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4094 (0x639Cu)
4536 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4095 (0x7349u)
4537 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4096 (0x4B27u)
4538 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4097 (0x1CD9u)
4539 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4098 (0x584Fu)
4540 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4099 (0x33D2u)
4541 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4100 (0x2FC2u)
4542 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4101 (0x545Du)
4543 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4102 (0x7CA1u)
4544 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4103 (0x3D2Cu)
4545 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4104 (0x1CEAu)
4546 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4105 (0x4DA9u)
4547 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4106 (0x65CCu)
4548 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4107 (0x4ECCu)
4549 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4108 (0x4B95u)
4550 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4109 (0x7817u)
4551 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4110 (0x6D83u)
4552 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4111 (0x6A1Du)
4553 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4112 (0x29B6u)
4554 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4113 (0x6DB0u)
4555 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4114 (0x135Du)
4556 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4115 (0x3791u)
4557 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4116 (0x16ECu)
4558 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4117 (0x1DD1u)
4559 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4118 (0x5792u)
4560 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4119 (0x4F91u)
4561 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4120 (0x4FC1u)
4562 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4121 (0x471Bu)
4563 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4122 (0x1763u)
4564 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4123 (0x6C78u)
4565 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4124 (0x6B94u)
4566 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4125 (0x133Eu)
4567 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4126 (0x581Fu)
4568 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4127 (0x5F60u)
4569 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4128 (0x7E42u)
4570 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4129 (0x6F84u)
4571 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4130 (0x1BA5u)
4572 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4131 (0x62BCu)
4573 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4132 (0x26D5u)
4574 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4133 (0x751Au)
4575 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4134 (0x34ECu)
4576 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4135 (0x0776u)
4577 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4136 (0x2B95u)
4578 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4137 (0x7855u)
4579 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4138 (0x60D7u)
4580 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4139 (0x13E9u)
4581 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4140 (0x5971u)
4582 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4141 (0x45E5u)
4583 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4142 (0x447Eu)
4584 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4143 (0x4A57u)
4585 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4144 (0x23ADu)
4586 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4145 (0x3B68u)
4587 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4146 (0x3595u)
4588 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4147 (0x06AFu)
4589 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4148 (0x65C5u)
4590 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4149 (0x31ADu)
4591 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4150 (0x1F46u)
4592 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4151 (0x750Eu)
4593 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4152 (0x323Bu)
4594 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4153 (0x62ABu)
4595 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4154 (0x6378u)
4596 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4155 (0x5F21u)
4597 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4156 (0x24EBu)
4598 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4157 (0x26B9u)
4599 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4158 (0x2CDCu)
4600 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4159 (0x7A34u)
4601 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4160 (0x355Cu)
4602 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4161 (0x1ADAu)
4603 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4162 (0x5666u)
4604 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4163 (0x5CE1u)
4605 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4164 (0x21DDu)
4606 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4165 (0x3D98u)
4607 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4166 (0x19D5u)
4608 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4167 (0x64E3u)
4609 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4168 (0x6A53u)
4610 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4169 (0x145Fu)
4611 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4170 (0x23A7u)
4612 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4171 (0x3725u)
4613 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4172 (0x782Bu)
4614 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4173 (0x6539u)
4615 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4174 (0x2B72u)
4616 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4175 (0x54F8u)
4617 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4176 (0x462Fu)
4618 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4177 (0x63A6u)
4619 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4178 (0x6617u)
4620 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4179 (0x16E9u)
4621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4180 (0x6B23u)
4622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4181 (0x3933u)
4623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4182 (0x52B6u)
4624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4183 (0x3A3Au)
4625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4184 (0x5B4Cu)
4626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4185 (0x636Cu)
4627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4186 (0x706Bu)
4628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4187 (0x0F1Eu)
4629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4188 (0x0EB5u)
4630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4189 (0x46B6u)
4631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4190 (0x5837u)
4632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4191 (0x0AE7u)
4633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4192 (0x7689u)
4634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4193 (0x3993u)
4635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4194 (0x68B3u)
4636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4195 (0x4A4Fu)
4637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4196 (0x3789u)
4638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4197 (0x2E55u)
4639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4198 (0x5678u)
4640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4199 (0x7532u)
4641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4200 (0x4F85u)
4642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4201 (0x6BA8u)
4643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4202 (0x61F2u)
4644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4203 (0x0ADEu)
4645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4204 (0x678Cu)
4646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4205 (0x2F25u)
4647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4206 (0x13F4u)
4648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4207 (0x4D78u)
4649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4208 (0x67C1u)
4650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4209 (0x1AD3u)
4651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4210 (0x647Cu)
4652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4211 (0x3B52u)
4653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4212 (0x43B9u)
4654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4213 (0x4D36u)
4655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4214 (0x611Fu)
4656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4215 (0x6D34u)
4657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4216 (0x7296u)
4658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4217 (0x1A5Du)
4659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4218 (0x7C51u)
4660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4219 (0x3F82u)
4661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4220 (0x0DF1u)
4662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4221 (0x760Du)
4663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4222 (0x07D3u)
4664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4223 (0x1F85u)
4665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4224 (0x568Bu)
4666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4225 (0x6197u)
4667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4226 (0x499Eu)
4668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4227 (0x6B51u)
4669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4228 (0x2637u)
4670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4229 (0x12FAu)
4671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4230 (0x49AEu)
4672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4231 (0x1D0Fu)
4673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4232 (0x3AA9u)
4674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4233 (0x0FC5u)
4675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4234 (0x2D93u)
4676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4235 (0x5E13u)
4677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4236 (0x331Bu)
4678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4237 (0x73A1u)
4679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4238 (0x3E2Cu)
4680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4239 (0x5A53u)
4681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4240 (0x6746u)
4682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4241 (0x371Cu)
4683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4242 (0x70D3u)
4684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4243 (0x51F1u)
4685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4244 (0x4774u)
4686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4245 (0x4C9Eu)
4687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4246 (0x3665u)
4688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4247 (0x531Du)
4689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4248 (0x473Au)
4690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4249 (0x1C6Du)
4691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4250 (0x16A7u)
4692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4251 (0x44DBu)
4693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4252 (0x1E6Au)
4694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4253 (0x3175u)
4695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4254 (0x5743u)
4696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4255 (0x6B1Au)
4697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4256 (0x55C3u)
4698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4257 (0x2A3Bu)
4699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4258 (0x5729u)
4700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4259 (0x336Au)
4701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4260 (0x4E87u)
4702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4261 (0x4CBAu)
4703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4262 (0x1D66u)
4704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4263 (0x33A3u)
4705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4264 (0x17B2u)
4706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4265 (0x6B91u)
4707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4266 (0x43EAu)
4708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4267 (0x61F4u)
4709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4268 (0x0ABDu)
4710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4269 (0x5647u)
4711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4270 (0x4B78u)
4712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4271 (0x02FBu)
4713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4272 (0x53C5u)
4714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4273 (0x68D5u)
4715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4274 (0x742Bu)
4716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4275 (0x7AC2u)
4717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4276 (0x3768u)
4718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4277 (0x1E8Du)
4719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4278 (0x7263u)
4720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4279 (0x0B1Fu)
4721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4280 (0x2D9Au)
4722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4281 (0x7CA2u)
4723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4282 (0x46B9u)
4724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4283 (0x526Du)
4725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4284 (0x7869u)
4726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4285 (0x7E0Au)
4727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4286 (0x268Fu)
4728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4287 (0x57A2u)
4729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4288 (0x6276u)
4730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4289 (0x0DD6u)
4731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4290 (0x16C7u)
4732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4291 (0x35C9u)
4733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4292 (0x7433u)
4734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4293 (0x2B3Au)
4735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4294 (0x5963u)
4736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4295 (0x30AFu)
4737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4296 (0x0F93u)
4738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4297 (0x1E35u)
4739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4298 (0x5237u)
4740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4299 (0x6297u)
4741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4300 (0x34F4u)
4742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4301 (0x399Au)
4743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4302 (0x6374u)
4744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4303 (0x2EC3u)
4745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4304 (0x3E31u)
4746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4305 (0x27C3u)
4747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4306 (0x565Au)
4748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4307 (0x27A6u)
4749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4308 (0x475Au)
4750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4309 (0x738Cu)
4751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4310 (0x53B1u)
4752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4311 (0x7057u)
4753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4312 (0x66ACu)
4754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4313 (0x7D18u)
4755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4314 (0x38F8u)
4756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4315 (0x3CC9u)
4757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4316 (0x6754u)
4758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4317 (0x26CEu)
4759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4318 (0x7C1Au)
4760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4319 (0x42CFu)
4761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4320 (0x562Eu)
4762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4321 (0x6A93u)
4763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4322 (0x54E6u)
4764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4323 (0x2B8Du)
4765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4324 (0x6D92u)
4766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4325 (0x5B94u)
4767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4326 (0x7703u)
4768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4327 (0x552Eu)
4769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4328 (0x6A9Cu)
4770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4329 (0x5B46u)
4771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4330 (0x1A3Du)
4772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4331 (0x53E2u)
4773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4332 (0x136Du)
4774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4333 (0x7645u)
4775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4334 (0x0BAEu)
4776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4335 (0x72B4u)
4777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4336 (0x3355u)
4778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4337 (0x7155u)
4779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4338 (0x64BAu)
4780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4339 (0x683Du)
4781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4340 (0x7B12u)
4782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4341 (0x526Eu)
4783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4342 (0x3E1Au)
4784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4343 (0x2717u)
4785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4344 (0x2F13u)
4786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4345 (0x05F3u)
4787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4346 (0x656Au)
4788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4347 (0x624Fu)
4789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4348 (0x1FA1u)
4790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4349 (0x507Eu)
4791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4350 (0x3C1Bu)
4792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4351 (0x742Du)
4793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4352 (0x1DC9u)
4794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4353 (0x6E94u)
4795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4354 (0x53E1u)
4796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4355 (0x1F52u)
4797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4356 (0x073Eu)
4798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4357 (0x4F4Cu)
4799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4358 (0x7C25u)
4800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4359 (0x38AEu)
4801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4360 (0x13B6u)
4802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4361 (0x0EB3u)
4803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4362 (0x3C5Cu)
4804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4363 (0x127Eu)
4805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4364 (0x6555u)
4806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4365 (0x158Fu)
4807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4366 (0x3D19u)
4808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4367 (0x1997u)
4809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4368 (0x2D8Eu)
4810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4369 (0x0C7Eu)
4811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4370 (0x3BC8u)
4812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4371 (0x7386u)
4813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4372 (0x7A4Au)
4814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4373 (0x5AD8u)
4815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4374 (0x0BCDu)
4816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4375 (0x2F98u)
4817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4376 (0x06B7u)
4818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4377 (0x7368u)
4819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4378 (0x1D33u)
4820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4379 (0x33D4u)
4821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4380 (0x363Au)
4822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4381 (0x3AB8u)
4823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4382 (0x7507u)
4824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4383 (0x7721u)
4825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4384 (0x2E27u)
4826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4385 (0x4C3Eu)
4827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4386 (0x5DC2u)
4828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4387 (0x5B13u)
4829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4388 (0x69B8u)
4830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4389 (0x3A1Eu)
4831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4390 (0x452Fu)
4832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4391 (0x2A6Eu)
4833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4392 (0x5371u)
4834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4393 (0x4D87u)
4835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4394 (0x7C15u)
4836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4395 (0x6E4Cu)
4837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4396 (0x58CEu)
4838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4397 (0x276Cu)
4839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4398 (0x70D6u)
4840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4399 (0x68BCu)
4841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4400 (0x4769u)
4842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4401 (0x2AEAu)
4843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4402 (0x527Au)
4844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4403 (0x2E6Au)
4845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4404 (0x781Du)
4846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4405 (0x5AA3u)
4847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4406 (0x2D3Au)
4848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4407 (0x764Au)
4849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4408 (0x592Eu)
4850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4409 (0x7C61u)
4851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4410 (0x2B9Au)
4852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4411 (0x463Eu)
4853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4412 (0x3726u)
4854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4413 (0x62CDu)
4855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4414 (0x665Cu)
4856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4415 (0x4F13u)
4857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4416 (0x20EFu)
4858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4417 (0x1979u)
4859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4418 (0x0FD1u)
4860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4419 (0x29CEu)
4861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4420 (0x1B27u)
4862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4421 (0x666Cu)
4863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4422 (0x70F1u)
4864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4423 (0x6C6Au)
4865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4424 (0x193Bu)
4866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4425 (0x3A36u)
4867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4426 (0x43F2u)
4868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4427 (0x37E0u)
4869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4428 (0x06EEu)
4870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4429 (0x1C8Fu)
4871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4430 (0x74F0u)
4872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4431 (0x4765u)
4873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4432 (0x6E43u)
4874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4433 (0x29E3u)
4875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4434 (0x5D32u)
4876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4435 (0x1ACDu)
4877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4436 (0x0CAFu)
4878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4437 (0x2772u)
4879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4438 (0x5E89u)
4880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4439 (0x6C53u)
4881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4440 (0x1E78u)
4882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4441 (0x5B49u)
4883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4442 (0x552Du)
4884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4443 (0x0CDBu)
4885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4444 (0x2AE6u)
4886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4445 (0x654Du)
4887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4446 (0x0F2Eu)
4888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4447 (0x6B13u)
4889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4448 (0x299Bu)
4890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4449 (0x65E2u)
4891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4450 (0x4FE0u)
4892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4451 (0x0D3Eu)
4893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4452 (0x44BEu)
4894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4453 (0x287Du)
4895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4454 (0x75A8u)
4896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4455 (0x639Au)
4897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4456 (0x1E1Eu)
4898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4457 (0x1B1Bu)
4899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4458 (0x3533u)
4900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4459 (0x1E17u)
4901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4460 (0x465Bu)
4902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4461 (0x2EE1u)
4903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4462 (0x335Au)
4904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4463 (0x54DCu)
4905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4464 (0x497Au)
4906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4465 (0x4597u)
4907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4466 (0x6CC5u)
4908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4467 (0x34C7u)
4909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4468 (0x538Bu)
4910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4469 (0x3476u)
4911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4470 (0x5D8Cu)
4912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4471 (0x15B3u)
4913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4472 (0x2DF0u)
4914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4473 (0x3AC5u)
4915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4474 (0x274Eu)
4916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4475 (0x5B0Eu)
4917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4476 (0x43E5u)
4918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4477 (0x3AD4u)
4919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4478 (0x6897u)
4920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4479 (0x37A4u)
4921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4480 (0x69AAu)
4922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4481 (0x6DA8u)
4923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4482 (0x5AE2u)
4924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4483 (0x1E9Cu)
4925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4484 (0x1E93u)
4926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4485 (0x6D2Cu)
4927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4486 (0x5CB4u)
4928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4487 (0x4DACu)
4929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4488 (0x0DB9u)
4930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4489 (0x17CAu)
4931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4490 (0x7C46u)
4932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4491 (0x194Fu)
4933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4492 (0x0F71u)
4934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4493 (0x4799u)
4935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4494 (0x6559u)
4936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4495 (0x4E1Du)
4937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4496 (0x23E3u)
4938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4497 (0x28DDu)
4939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4498 (0x7C19u)
4940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4499 (0x6AE4u)
4941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4500 (0x6959u)
4942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4501 (0x6556u)
4943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4502 (0x52E3u)
4944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4503 (0x43D3u)
4945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4504 (0x7866u)
4946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4505 (0x2769u)
4947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4506 (0x30DBu)
4948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4507 (0x1FC8u)
4949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4508 (0x45E9u)
4950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4509 (0x6792u)
4951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4510 (0x5F11u)
4952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4511 (0x073Du)
4953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4512 (0x309Fu)
4954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4513 (0x24FCu)
4955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4514 (0x4637u)
4956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4515 (0x29EAu)
4957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4516 (0x22BEu)
4958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4517 (0x2B39u)
4959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4518 (0x469Du)
4960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4519 (0x3B51u)
4961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4520 (0x1AD5u)
4962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4521 (0x58ECu)
4963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4522 (0x649Du)
4964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4523 (0x31BAu)
4965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4524 (0x25B3u)
4966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4525 (0x2D1Du)
4967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4526 (0x7174u)
4968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4527 (0x4E78u)
4969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4528 (0x0F33u)
4970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4529 (0x5693u)
4971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4530 (0x27D2u)
4972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4531 (0x6BC1u)
4973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4532 (0x5936u)
4974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4533 (0x09F5u)
4975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4534 (0x64B6u)
4976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4535 (0x29E5u)
4977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4536 (0x3EE0u)
4978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4537 (0x5CCCu)
4979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4538 (0x0BECu)
4980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4539 (0x7153u)
4981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4540 (0x4B4Eu)
4982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4541 (0x6C4Bu)
4983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4542 (0x165Eu)
4984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4543 (0x3758u)
4985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4544 (0x2BA6u)
4986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4545 (0x3CA6u)
4987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4546 (0x1E2Eu)
4988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4547 (0x49F1u)
4989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4548 (0x262Fu)
4990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4549 (0x44B7u)
4991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4550 (0x33CAu)
4992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4551 (0x13BAu)
4993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4552 (0x172Bu)
4994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4553 (0x4ADCu)
4995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4554 (0x7646u)
4996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4555 (0x09EDu)
4997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4556 (0x326Du)
4998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4557 (0x0DABu)
4999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4558 (0x7CA8u)
5000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4559 (0x4EF0u)
5001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4560 (0x51E9u)
5002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4561 (0x5CE4u)
5003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4562 (0x6571u)
5004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4563 (0x2EF0u)
5005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4564 (0x74A5u)
5006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4565 (0x1F61u)
5007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4566 (0x25AEu)
5008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4567 (0x5E52u)
5009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4568 (0x461Fu)
5010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4569 (0x61E9u)
5011 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4570 (0x605Fu)
5012 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4571 (0x3E15u)
5013 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4572 (0x571Au)
5014 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4573 (0x27A9u)
5015 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4574 (0x2EA5u)
5016 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4575 (0x283Fu)
5017 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4576 (0x392Du)
5018 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4577 (0x49E6u)
5019 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4578 (0x5B8Au)
5020 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4579 (0x3C8Du)
5021 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4580 (0x383Bu)
5022 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4581 (0x6E98u)
5023 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4582 (0x47C5u)
5024 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4583 (0x45ADu)
5025 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4584 (0x678Au)
5026 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4585 (0x18B7u)
5027 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4586 (0x1376u)
5028 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4587 (0x1337u)
5029 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4588 (0x62B9u)
5030 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4589 (0x39D2u)
5031 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4590 (0x037Bu)
5032 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4591 (0x296Du)
5033 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4592 (0x31D5u)
5034 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4593 (0x3936u)
5035 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4594 (0x076Bu)
5036 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4595 (0x3D86u)
5037 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4596 (0x29CBu)
5038 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4597 (0x78E8u)
5039 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4598 (0x5366u)
5040 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4599 (0x49EAu)
5041 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4600 (0x760Eu)
5042 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4601 (0x2B8Eu)
5043 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4602 (0x4CD3u)
5044 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4603 (0x7B88u)
5045 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4604 (0x4DC9u)
5046 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4605 (0x3956u)
5047 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4606 (0x51A7u)
5048 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4607 (0x293Bu)
5049 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4608 (0x267Cu)
5050 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4609 (0x0E37u)
5051 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4610 (0x2E39u)
5052 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4611 (0x7B48u)
5053 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4612 (0x7178u)
5054 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4613 (0x6C5Cu)
5055 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4614 (0x51EAu)
5056 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4615 (0x7970u)
5057 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4616 (0x2A3Du)
5058 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4617 (0x2C5Du)
5059 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4618 (0x6729u)
5060 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4619 (0x3707u)
5061 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4620 (0x4DCAu)
5062 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4621 (0x2957u)
5063 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4622 (0x266Du)
5064 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4623 (0x4ABCu)
5065 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4624 (0x4967u)
5066 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4625 (0x199Du)
5067 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4626 (0x5725u)
5068 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4627 (0x0F99u)
5069 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4628 (0x42E7u)
5070 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4629 (0x5365u)
5071 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4630 (0x2376u)
5072 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4631 (0x275Au)
5073 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4632 (0x3C47u)
5074 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4633 (0x22E7u)
5075 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4634 (0x4F86u)
5076 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4635 (0x0FE2u)
5077 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4636 (0x5D25u)
5078 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4637 (0x6D46u)
5079 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4638 (0x555Au)
5080 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4639 (0x18EBu)
5081 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4640 (0x5D4Au)
5082 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4641 (0x487Du)
5083 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4642 (0x71ACu)
5084 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4643 (0x354Bu)
5085 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4644 (0x4F0Du)
5086 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4645 (0x0DF2u)
5087 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4646 (0x3C74u)
5088 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4647 (0x0AF5u)
5089 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4648 (0x32CBu)
5090 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4649 (0x298Fu)
5091 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4650 (0x42DEu)
5092 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4651 (0x186Fu)
5093 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4652 (0x3C2Du)
5094 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4653 (0x72A5u)
5095 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4654 (0x1B4Eu)
5096 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4655 (0x1E4Eu)
5097 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4656 (0x7863u)
5098 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4657 (0x7C2Au)
5099 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4658 (0x646Bu)
5100 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4659 (0x4B5Cu)
5101 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4660 (0x583Bu)
5102 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4661 (0x3387u)
5103 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4662 (0x1BA3u)
5104 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4663 (0x53C6u)
5105 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4664 (0x2FA4u)
5106 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4665 (0x16BAu)
5107 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4666 (0x7893u)
5108 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4667 (0x31E3u)
5109 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4668 (0x3276u)
5110 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4669 (0x45D9u)
5111 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4670 (0x25B6u)
5112 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4671 (0x468Fu)
5113 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4672 (0x1E96u)
5114 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4673 (0x079Du)
5115 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4674 (0x45EAu)
5116 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4675 (0x361Du)
5117 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4676 (0x54BCu)
5118 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4677 (0x3566u)
5119 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4678 (0x0AF3u)
5120 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4679 (0x7CC8u)
5121 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4680 (0x5B61u)
5122 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4681 (0x6A8Bu)
5123 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4682 (0x398Bu)
5124 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4683 (0x789Cu)
5125 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4684 (0x50BEu)
5126 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4685 (0x1EA3u)
5127 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4686 (0x3715u)
5128 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4687 (0x5783u)
5129 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4688 (0x750Bu)
5130 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4689 (0x75A2u)
5131 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4690 (0x059Fu)
5132 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4691 (0x1EAAu)
5133 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4692 (0x0CEEu)
5134 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4693 (0x6719u)
5135 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4694 (0x3E32u)
5136 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4695 (0x2B69u)
5137 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4696 (0x156Bu)
5138 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4697 (0x57C8u)
5139 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4698 (0x60BEu)
5140 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4699 (0x5C1Bu)
5141 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4700 (0x5C39u)
5142 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4701 (0x19CBu)
5143 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4702 (0x7D90u)
5144 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4703 (0x315Du)
5145 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4704 (0x272Du)
5146 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4705 (0x66B8u)
5147 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4706 (0x6E1Au)
5148 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4707 (0x6C6Cu)
5149 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4708 (0x4A3Bu)
5150 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4709 (0x23B6u)
5151 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4710 (0x560Fu)
5152 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4711 (0x6FC0u)
5153 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4712 (0x3C4Du)
5154 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4713 (0x1AD9u)
5155 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4714 (0x5DA1u)
5156 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4715 (0x5E38u)
5157 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4716 (0x26E6u)
5158 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4717 (0x517Au)
5159 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4718 (0x2C3Eu)
5160 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4719 (0x3273u)
5161 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4720 (0x6953u)
5162 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4721 (0x50EDu)
5163 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4722 (0x5275u)
5164 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4723 (0x3AD8u)
5165 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4724 (0x592Bu)
5166 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4725 (0x51AEu)
5167 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4726 (0x6A59u)
5168 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4727 (0x5699u)
5169 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4728 (0x31F2u)
5170 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4729 (0x3C8Bu)
5171 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4730 (0x7487u)
5172 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4731 (0x427Du)
5173 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4732 (0x1F86u)
5174 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4733 (0x5E49u)
5175 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4734 (0x5F05u)
5176 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4735 (0x1D56u)
5177 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4736 (0x1CF4u)
5178 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4737 (0x3752u)
5179 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4738 (0x35B4u)
5180 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4739 (0x670Bu)
5181 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4740 (0x64D9u)
5182 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4741 (0x2F4Cu)
5183 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4742 (0x5D34u)
5184 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4743 (0x0DB3u)
5185 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4744 (0x6F90u)
5186 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4745 (0x306Fu)
5187 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4746 (0x466Bu)
5188 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4747 (0x6C9Au)
5189 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4748 (0x1367u)
5190 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4749 (0x69ACu)
5191 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4750 (0x513Bu)
5192 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4751 (0x3D62u)
5193 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4752 (0x313Bu)
5194 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4753 (0x2D8Du)
5195 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4754 (0x3B98u)
5196 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4755 (0x53E4u)
5197 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4756 (0x3569u)
5198 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4757 (0x6353u)
5199 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4758 (0x1F31u)
5200 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4759 (0x1D6Cu)
5201 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4760 (0x5687u)
5202 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4761 (0x7515u)
5203 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4762 (0x5BD0u)
5204 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4763 (0x1772u)
5205 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4764 (0x43E6u)
5206 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4765 (0x36E8u)
5207 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4766 (0x5B0Du)
5208 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4767 (0x72E2u)
5209 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4768 (0x349Du)
5210 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4769 (0x06BEu)
5211 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4770 (0x5669u)
5212 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4771 (0x5B8Cu)
5213 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4772 (0x498Fu)
5214 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4773 (0x3535u)
5215 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4774 (0x1D2Du)
5216 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4775 (0x6B85u)
5217 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4776 (0x703Eu)
5218 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4777 (0x7269u)
5219 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4778 (0x50D7u)
5220 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4779 (0x68CEu)
5221 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4780 (0x69E1u)
5222 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4781 (0x72E4u)
5223 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4782 (0x752Au)
5224 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4783 (0x5749u)
5225 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4784 (0x364Bu)
5226 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4785 (0x1B9Cu)
5227 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4786 (0x5B86u)
5228 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4787 (0x7C0Du)
5229 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4788 (0x3F21u)
5230 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4789 (0x694Eu)
5231 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4790 (0x5C2Eu)
5232 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4791 (0x6A3Au)
5233 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4792 (0x2E2Bu)
5234 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4793 (0x38B5u)
5235 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4794 (0x4ABAu)
5236 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4795 (0x52ADu)
5237 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4796 (0x53D2u)
5238 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4797 (0x47ACu)
5239 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4798 (0x187Du)
5240 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4799 (0x449Fu)
5241 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4800 (0x25E3u)
5242 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4801 (0x7354u)
5243 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4802 (0x60B7u)
5244 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4803 (0x1CDAu)
5245 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4804 (0x5395u)
5246 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4805 (0x257Cu)
5247 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4806 (0x471Eu)
5248 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4807 (0x62E3u)
5249 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4808 (0x331Eu)
5250 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4809 (0x46C7u)
5251 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4810 (0x7D88u)
5252 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4811 (0x3AC9u)
5253 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4812 (0x2367u)
5254 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4813 (0x7598u)
5255 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4814 (0x47B2u)
5256 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4815 (0x7613u)
5257 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4816 (0x58F4u)
5258 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4817 (0x6C63u)
5259 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4818 (0x6A4Du)
5260 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4819 (0x6F24u)
5261 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4820 (0x5987u)
5262 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4821 (0x234Fu)
5263 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4822 (0x42DBu)
5264 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4823 (0x638Bu)
5265 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4824 (0x4A37u)
5266 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4825 (0x2FC4u)
5267 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4826 (0x7A49u)
5268 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4827 (0x417Du)
5269 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4828 (0x7C89u)
5270 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4829 (0x68ADu)
5271 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4830 (0x51D5u)
5272 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4831 (0x253Du)
5273 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4832 (0x6B83u)
5274 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4833 (0x1BB4u)
5275 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4834 (0x1778u)
5276 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4835 (0x3237u)
5277 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4836 (0x74E4u)
5278 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4837 (0x63C9u)
5279 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4838 (0x1C6Bu)
5280 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4839 (0x31AEu)
5281 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4840 (0x1ADCu)
5282 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4841 (0x5636u)
5283 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4842 (0x2AF2u)
5284 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4843 (0x64CDu)
5285 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4844 (0x55ACu)
5286 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4845 (0x1B72u)
5287 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4846 (0x6AD8u)
5288 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4847 (0x40FBu)
5289 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4848 (0x52CDu)
5290 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4849 (0x343Bu)
5291 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4850 (0x6935u)
5292 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4851 (0x6578u)
5293 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4852 (0x7466u)
5294 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4853 (0x6BA2u)
5295 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4854 (0x5AE1u)
5296 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4855 (0x5596u)
5297 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4856 (0x7529u)
5298 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4857 (0x566Cu)
5299 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4858 (0x4B9Au)
5300 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4859 (0x6A1Bu)
5301 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4860 (0x174Eu)
5302 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4861 (0x0AFCu)
5303 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4862 (0x1A7Au)
5304 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4863 (0x394Du)
5305 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4864 (0x7A29u)
5306 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4865 (0x2E69u)
5307 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4866 (0x7C38u)
5308 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4867 (0x3BA1u)
5309 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4868 (0x32ECu)
5310 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4869 (0x5E64u)
5311 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4870 (0x179Au)
5312 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4871 (0x26DAu)
5313 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4872 (0x32E3u)
5314 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4873 (0x315Eu)
5315 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4874 (0x7730u)
5316 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4875 (0x2793u)
5317 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4876 (0x24D7u)
5318 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4877 (0x5F06u)
5319 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4878 (0x3D2Au)
5320 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4879 (0x5B45u)
5321 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4880 (0x4FA8u)
5322 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4881 (0x3173u)
5323 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4882 (0x628Fu)
5324 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4883 (0x4BA9u)
5325 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4884 (0x6AA9u)
5326 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4885 (0x4D4Bu)
5327 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4886 (0x5752u)
5328 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4887 (0x62F8u)
5329 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4888 (0x50EBu)
5330 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4889 (0x63A3u)
5331 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4890 (0x6566u)
5332 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4891 (0x55B1u)
5333 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4892 (0x62E5u)
5334 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4893 (0x666Au)
5335 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4894 (0x5359u)
5336 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4895 (0x5B15u)
5337 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4896 (0x5B98u)
5338 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4897 (0x35C3u)
5339 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4898 (0x1A75u)
5340 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4899 (0x28D7u)
5341 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4900 (0x4397u)
5342 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4901 (0x3D32u)
5343 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4902 (0x426Fu)
5344 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4903 (0x5374u)
5345 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4904 (0x13D3u)
5346 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4905 (0x749Au)
5347 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4906 (0x196Bu)
5348 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4907 (0x2753u)
5349 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4908 (0x64ECu)
5350 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4909 (0x6A2Bu)
5351 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4910 (0x6336u)
5352 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4911 (0x39E8u)
5353 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4912 (0x1EA9u)
5354 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4913 (0x7A70u)
5355 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4914 (0x2177u)
5356 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4915 (0x5559u)
5357 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4916 (0x223Fu)
5358 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4917 (0x5FA0u)
5359 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4918 (0x4697u)
5360 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4919 (0x1DE8u)
5361 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4920 (0x50F9u)
5362 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4921 (0x2ED2u)
5363 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4922 (0x3C71u)
5364 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4923 (0x3317u)
5365 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4924 (0x0E75u)
5366 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4925 (0x2DA6u)
5367 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4926 (0x534Du)
5368 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4927 (0x09D7u)
5369 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4928 (0x703Du)
5370 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4929 (0x6BA1u)
5371 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4930 (0x31D9u)
5372 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4931 (0x6EE0u)
5373 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4932 (0x46CEu)
5374 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4933 (0x1B78u)
5375 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4934 (0x6879u)
5376 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4935 (0x5C8Eu)
5377 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4936 (0x5C66u)
5378 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4937 (0x50F6u)
5379 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4938 (0x25ABu)
5380 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4939 (0x6563u)
5381 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4940 (0x726Cu)
5382 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4941 (0x135Bu)
5383 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4942 (0x7D03u)
5384 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4943 (0x25ADu)
5385 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4944 (0x3D91u)
5386 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4945 (0x26D3u)
5387 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4946 (0x2D66u)
5388 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4947 (0x587Cu)
5389 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4948 (0x4357u)
5390 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4949 (0x09DDu)
5391 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4950 (0x51F4u)
5392 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4951 (0x5A72u)
5393 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4952 (0x7453u)
5394 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4953 (0x171Bu)
5395 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4954 (0x351Bu)
5396 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4955 (0x1AE5u)
5397 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4956 (0x699Au)
5398 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4957 (0x0FA6u)
5399 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4958 (0x3729u)
5400 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4959 (0x21EBu)
5401 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4960 (0x6B16u)
5402 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4961 (0x3F60u)
5403 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4962 (0x539Au)
5404 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4963 (0x3E68u)
5405 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4964 (0x1D74u)
5406 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4965 (0x732Au)
5407 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4966 (0x10FBu)
5408 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4967 (0x1AE6u)
5409 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4968 (0x538Eu)
5410 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4969 (0x0B79u)
5411 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4970 (0x1CD3u)
5412 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4971 (0x42EDu)
5413 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4972 (0x5555u)
5414 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4973 (0x2D59u)
5415 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4974 (0x594Eu)
5416 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4975 (0x34E6u)
5417 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4976 (0x60DEu)
5418 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4977 (0x533Au)
5419 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4978 (0x71A3u)
5420 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4979 (0x516Eu)
5421 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4980 (0x07F2u)
5422 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4981 (0x6971u)
5423 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4982 (0x546Eu)
5424 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4983 (0x551Eu)
5425 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4984 (0x2796u)
5426 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4985 (0x0F55u)
5427 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4986 (0x72F0u)
5428 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4987 (0x1DD4u)
5429 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4988 (0x15F4u)
5430 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4989 (0x5E19u)
5431 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4990 (0x39A9u)
5432 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4991 (0x3574u)
5433 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4992 (0x73E0u)
5434 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4993 (0x6D23u)
5435 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4994 (0x4DD4u)
5436 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4995 (0x564Eu)
5437 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4996 (0x46ABu)
5438 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4997 (0x36F0u)
5439 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4998 (0x2E53u)
5440 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4999 (0x523Bu)
5441 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5000 (0x566Au)
5442 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5001 (0x0B37u)
5443 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5002 (0x49ABu)
5444 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5003 (0x52E6u)
5445 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5004 (0x7AC1u)
5446 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5005 (0x5DA4u)
5447 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5006 (0x1B63u)
5448 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5007 (0x5E2Cu)
5449 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5008 (0x23ECu)
5450 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5009 (0x350Fu)
5451 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5010 (0x6DA2u)
5452 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5011 (0x07ADu)
5453 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5012 (0x76E0u)
5454 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5013 (0x27E4u)
5455 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5014 (0x6AB8u)
5456 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5015 (0x53A9u)
5457 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5016 (0x62CBu)
5458 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5017 (0x11F3u)
5459 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5018 (0x41BEu)
5460 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5019 (0x7187u)
5461 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5020 (0x4379u)
5462 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5021 (0x7631u)
5463 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5022 (0x32F1u)
5464 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5023 (0x356Au)
5465 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5024 (0x1C7Au)
5466 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5025 (0x2F85u)
5467 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5026 (0x49CDu)
5468 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5027 (0x27C5u)
5469 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5028 (0x52D5u)
5470 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5029 (0x13CDu)
5471 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5030 (0x1DACu)
5472 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5031 (0x78E4u)
5473 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5032 (0x3C96u)
5474 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5033 (0x3C3Cu)
5475 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5034 (0x5ACCu)
5476 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5035 (0x1E69u)
5477 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5036 (0x7331u)
5478 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5037 (0x3CB8u)
5479 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5038 (0x56A3u)
5480 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5039 (0x345Du)
5481 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5040 (0x6D38u)
5482 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5041 (0x149Fu)
5483 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5042 (0x23AEu)
5484 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5043 (0x32B5u)
5485 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5044 (0x66E8u)
5486 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5045 (0x3D46u)
5487 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5046 (0x630Fu)
5488 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5047 (0x38E3u)
5489 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5048 (0x07A7u)
5490 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5049 (0x6339u)
5491 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5050 (0x6CD1u)
5492 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5051 (0x3C95u)
5493 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5052 (0x6F50u)
5494 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5053 (0x1D4Eu)
5495 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5054 (0x56B2u)
5496 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5055 (0x7A8Cu)
5497 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5056 (0x45B3u)
5498 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5057 (0x1B5Au)
5499 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5058 (0x2976u)
5500 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5059 (0x6678u)
5501 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5060 (0x6972u)
5502 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5061 (0x2BE1u)
5503 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5062 (0x066Fu)
5504 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5063 (0x7455u)
5505 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5064 (0x2D39u)
5506 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5065 (0x32E9u)
5507 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5066 (0x7D14u)
5508 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5067 (0x21E7u)
5509 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5068 (0x29B9u)
5510 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5069 (0x46B5u)
5511 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5070 (0x3547u)
5512 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5071 (0x534Bu)
5513 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5072 (0x7A13u)
5514 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5073 (0x19E5u)
5515 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5074 (0x32CEu)
5516 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5075 (0x1CCBu)
5517 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5076 (0x349Bu)
5518 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5077 (0x2D9Cu)
5519 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5078 (0x7C4Cu)
5520 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5079 (0x5EA8u)
5521 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5080 (0x5C2Bu)
5522 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5081 (0x1795u)
5523 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5082 (0x434Fu)
5524 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5083 (0x3556u)
5525 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5084 (0x473Cu)
5526 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5085 (0x6A69u)
5527 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5086 (0x5B4Au)
5528 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5087 (0x7662u)
5529 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5088 (0x1727u)
5530 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5089 (0x2F61u)
5531 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5090 (0x2DB4u)
5532 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5091 (0x49A7u)
5533 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5092 (0x46E5u)
5534 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5093 (0x6479u)
5535 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5094 (0x792Au)
5536 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5095 (0x34ABu)
5537 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5096 (0x0EA7u)
5538 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5097 (0x6627u)
5539 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5098 (0x3696u)
5540 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5099 (0x3593u)
5541 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5100 (0x02FEu)
5542 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5101 (0x47AAu)
5543 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5102 (0x57A4u)
5544 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5103 (0x686Du)
5545 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5104 (0x256Du)
5546 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5105 (0x6917u)
5547 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5106 (0x5C47u)
5548 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5107 (0x5CC6u)
5549 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5108 (0x5E4Cu)
5550 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5109 (0x17ACu)
5551 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5110 (0x2F23u)
5552 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5111 (0x6936u)
5553 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5112 (0x2AB5u)
5554 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5113 (0x2CB3u)
5555 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5114 (0x5C74u)
5556 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5115 (0x286Fu)
5557 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5116 (0x06DDu)
5558 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5117 (0x6C74u)
5559 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5118 (0x3587u)
5560 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5119 (0x3EA4u)
5561 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5120 (0x2D4Eu)
5562 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5121 (0x2EE2u)
5563 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5122 (0x6572u)
5564 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5123 (0x4D1Du)
5565 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5124 (0x44E7u)
5566 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5125 (0x74A9u)
5567 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5126 (0x4AADu)
5568 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5127 (0x0BE5u)
5569 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5128 (0x4F62u)
5570 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5129 (0x35E1u)
5571 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5130 (0x4E69u)
5572 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5131 (0x4F54u)
5573 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5132 (0x4667u)
5574 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5133 (0x49E5u)
5575 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5134 (0x7287u)
5576 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5135 (0x1F62u)
5577 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5136 (0x7233u)
5578 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5137 (0x71CCu)
5579 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5138 (0x3369u)
5580 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5139 (0x46E3u)
5581 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5140 (0x2E4Du)
5582 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5141 (0x3D23u)
5583 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5142 (0x334Bu)
5584 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5143 (0x56E2u)
5585 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5144 (0x71AAu)
5586 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5145 (0x38B9u)
5587 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5146 (0x3B45u)
5588 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5147 (0x0BF4u)
5589 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5148 (0x365Cu)
5590 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5149 (0x1567u)
5591 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5150 (0x635Au)
5592 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5151 (0x23DAu)
5593 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5152 (0x2766u)
5594 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5153 (0x6CE2u)
5595 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5154 (0x1CF2u)
5596 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5155 (0x1379u)
5597 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5156 (0x4D69u)
5598 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5157 (0x0D79u)
5599 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5158 (0x22F6u)
5600 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5159 (0x7F10u)
5601 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5160 (0x50FCu)
5602 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5161 (0x4E9Cu)
5603 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5162 (0x347Cu)
5604 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5163 (0x399Cu)
5605 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5164 (0x39B2u)
5606 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5165 (0x6C33u)
5607 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5166 (0x6E26u)
5608 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5167 (0x5CE2u)
5609 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5168 (0x4AE9u)
5610 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5169 (0x548Fu)
5611 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5170 (0x33B1u)
5612 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5171 (0x226Fu)
5613 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5172 (0x3969u)
5614 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5173 (0x56D1u)
5615 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5174 (0x692Eu)
5616 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5175 (0x7531u)
5617 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5176 (0x2F94u)
5618 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5177 (0x1DA6u)
5619 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5178 (0x1EE1u)
5620 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5179 (0x165Du)
5621 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5180 (0x46D5u)
5622 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5181 (0x55AAu)
5623 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5182 (0x38BAu)
5624 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5183 (0x6CC9u)
5625 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5184 (0x36E2u)
5626 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5185 (0x156Eu)
5627 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5186 (0x68D3u)
5628 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5187 (0x26D6u)
5629 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5188 (0x1C9Du)
5630 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5189 (0x7329u)
5631 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5190 (0x752Cu)
5632 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5191 (0x28AFu)
5633 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5192 (0x1F13u)
5634 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5193 (0x7954u)
5635 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5194 (0x79D0u)
5636 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5195 (0x21FCu)
5637 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5196 (0x54F4u)
5638 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5197 (0x7C32u)
5639 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5198 (0x6C87u)
5640 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5199 (0x5279u)
5641 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5200 (0x4D5Au)
5642 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5201 (0x5AA6u)
5643 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5202 (0x4A75u)
5644 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5203 (0x669Au)
5645 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5204 (0x3A35u)
5646 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5205 (0x552Bu)
5647 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5206 (0x4DE4u)
5648 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5207 (0x41D7u)
5649 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5208 (0x455Bu)
5650 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5209 (0x0BB5u)
5651 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5210 (0x1CF1u)
5652 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5211 (0x6157u)
5653 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5212 (0x1B6Au)
5654 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5213 (0x2C6Du)
5655 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5214 (0x4DB2u)
5656 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5215 (0x22CFu)
5657 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5216 (0x2F8Au)
5658 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5217 (0x6656u)
5659 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5218 (0x7A58u)
5660 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5219 (0x3A8Bu)
5661 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5220 (0x5533u)
5662 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5221 (0x1DA9u)
5663 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5222 (0x7A98u)
5664 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5223 (0x27D1u)
5665 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5224 (0x1DB4u)
5666 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5225 (0x0F5Cu)
5667 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5226 (0x6E13u)
5668 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5227 (0x65B2u)
5669 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5228 (0x3D49u)
5670 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5229 (0x36B1u)
5671 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5230 (0x3B0Bu)
5672 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5231 (0x0C9Fu)
5673 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5232 (0x143Fu)
5674 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5233 (0x17AAu)
5675 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5234 (0x5995u)
5676 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5235 (0x5785u)
5677 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5236 (0x176Cu)
5678 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5237 (0x51B3u)
5679 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5238 (0x386Du)
5680 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5239 (0x7652u)
5681 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5240 (0x7E41u)
5682 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5241 (0x37A8u)
5683 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5242 (0x619Du)
5684 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5243 (0x6AD2u)
5685 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5244 (0x3E4Cu)
5686 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5245 (0x7471u)
5687 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5246 (0x503Fu)
5688 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5247 (0x66B2u)
5689 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5248 (0x4DC3u)
5690 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5249 (0x2CF2u)
5691 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5250 (0x6B54u)
5692 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5251 (0x65B1u)
5693 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5252 (0x7874u)
5694 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5253 (0x42B7u)
5695 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5254 (0x1F94u)
5696 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5255 (0x1D4Du)
5697 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5256 (0x5F84u)
5698 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5257 (0x6987u)
5699 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5258 (0x31B3u)
5700 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5259 (0x347Au)
5701 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5260 (0x16CBu)
5702 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5261 (0x4A9Eu)
5703 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5262 (0x0D6Bu)
5704 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5263 (0x3F50u)
5705 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5264 (0x2F64u)
5706 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5265 (0x3687u)
5707 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5266 (0x0ADDu)
5708 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5267 (0x0BF1u)
5709 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5268 (0x3C99u)
5710 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5269 (0x1C5Eu)
5711 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5270 (0x20F7u)
5712 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5271 (0x09FAu)
5713 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5272 (0x3CF0u)
5714 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5273 (0x456Du)
5715 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5274 (0x18EEu)
5716 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5275 (0x782Du)
5717 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5276 (0x0FD8u)
5718 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5277 (0x69C3u)
5719 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5278 (0x2E4Eu)
5720 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5279 (0x7A64u)
5721 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5280 (0x1AF1u)
5722 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5281 (0x1AB9u)
5723 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5282 (0x48F3u)
5724 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5283 (0x1FA4u)
5725 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5284 (0x12F9u)
5726 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5285 (0x485Fu)
5727 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5286 (0x7B44u)
5728 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5287 (0x645Eu)
5729 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5288 (0x5746u)
5730 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5289 (0x7C85u)
5731 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5290 (0x0773u)
5732 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5291 (0x4997u)
5733 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5292 (0x5F0Au)
5734 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5293 (0x2A4Fu)
5735 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5294 (0x317Cu)
5736 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5295 (0x722Du)
5737 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5296 (0x7C64u)
5738 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5297 (0x459Bu)
5739 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5298 (0x525Bu)
5740 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5299 (0x7493u)
5741 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5300 (0x708Fu)
5742 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5301 (0x15BCu)
5743 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5302 (0x7AD0u)
5744 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5303 (0x3B49u)
5745 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5304 (0x6EC4u)
5746 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5305 (0x3E2Au)
5747 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5306 (0x278Du)
5748 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5307 (0x3D13u)
5749 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5308 (0x70CDu)
5750 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5309 (0x4A1Fu)
5751 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5310 (0x3CE2u)
5752 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5311 (0x17B4u)
5753 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5312 (0x17E1u)
5754 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5313 (0x49ADu)
5755 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5314 (0x6AC5u)
5756 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5315 (0x6D29u)
5757 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5316 (0x0EB9u)
5758 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5317 (0x6D13u)
5759 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5318 (0x172Du)
5760 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5319 (0x77A0u)
5761 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5320 (0x10FDu)
5762 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5321 (0x0BA7u)
5763 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5322 (0x3966u)
5764 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5323 (0x38F4u)
5765 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5324 (0x20BFu)
5766 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5325 (0x31ECu)
5767 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5326 (0x1E3Au)
5768 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5327 (0x5ACAu)
5769 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5328 (0x5D68u)
5770 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5329 (0x322Fu)
5771 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5330 (0x2FA1u)
5772 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5331 (0x079Bu)
5773 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5332 (0x6965u)
5774 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5333 (0x4A76u)
5775 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5334 (0x712Eu)
5776 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5335 (0x7D30u)
5777 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5336 (0x5B19u)
5778 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5337 (0x0EE6u)
5779 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5338 (0x0F95u)
5780 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5339 (0x68DCu)
5781 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5340 (0x2BF0u)
5782 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5341 (0x2EE4u)
5783 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5342 (0x632Du)
5784 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5343 (0x3C78u)
5785 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5344 (0x7CD0u)
5786 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5345 (0x74B8u)
5787 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5346 (0x189Fu)
5788 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5347 (0x08BFu)
5789 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5348 (0x0BE9u)
5790 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5349 (0x0CDDu)
5791 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5350 (0x60EBu)
5792 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5351 (0x550Fu)
5793 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5352 (0x17B1u)
5794 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5353 (0x4DB4u)
5795 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5354 (0x76A2u)
5796 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5355 (0x1D71u)
5797 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5356 (0x2DA3u)
5798 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5357 (0x17CCu)
5799 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5358 (0x3F88u)
5800 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5359 (0x65E8u)
5801 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5360 (0x788Eu)
5802 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5361 (0x7706u)
5803 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5362 (0x7983u)
5804 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5363 (0x3A6Au)
5805 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5364 (0x5996u)
5806 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5365 (0x1735u)
5807 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5366 (0x25D9u)
5808 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5367 (0x37B0u)
5809 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5368 (0x2BB8u)
5810 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5369 (0x5E91u)
5811 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5370 (0x5D31u)
5812 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5371 (0x4D63u)
5813 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5372 (0x7E12u)
5814 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5373 (0x5A4Eu)
5815 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5374 (0x7465u)
5816 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5375 (0x39C3u)
5817 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5376 (0x6237u)
5818 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5377 (0x7A61u)
5819 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5378 (0x2A75u)
5820 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5379 (0x2967u)
5821 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5380 (0x6749u)
5822 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5381 (0x1ED8u)
5823 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5382 (0x3CC5u)
5824 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5383 (0x34CEu)
5825 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5384 (0x4B0Fu)
5826 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5385 (0x6CB8u)
5827 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5386 (0x54CBu)
5828 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5387 (0x253Bu)
5829 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5388 (0x313Du)
5830 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5389 (0x4AF4u)
5831 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5390 (0x2B5Cu)
5832 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5391 (0x5B64u)
5833 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5392 (0x570Du)
5834 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5393 (0x5F81u)
5835 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5394 (0x6327u)
5836 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5395 (0x556Au)
5837 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5396 (0x3A4Bu)
5838 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5397 (0x6659u)
5839 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5398 (0x3A99u)
5840 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5399 (0x62ECu)
5841 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5400 (0x0C7Du)
5842 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5401 (0x625Eu)
5843 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5402 (0x487Eu)
5844 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5403 (0x2E8Du)
5845 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5404 (0x66A9u)
5846 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5405 (0x486Fu)
5847 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5406 (0x05EEu)
5848 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5407 (0x1E1Du)
5849 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5408 (0x6596u)
5850 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5409 (0x59D4u)
5851 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5410 (0x2CB9u)
5852 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5411 (0x74C9u)
5853 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5412 (0x291Fu)
5854 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5413 (0x472Eu)
5855 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5414 (0x279Au)
5856 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5415 (0x113Fu)
5857 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5416 (0x474Du)
5858 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5417 (0x5965u)
5859 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5418 (0x0EF8u)
5860 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5419 (0x35E2u)
5861 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5420 (0x0F9Cu)
5862 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5421 (0x5535u)
5863 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5422 (0x352Eu)
5864 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5423 (0x6DC1u)
5865 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5424 (0x6C8Du)
5866 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5425 (0x29ECu)
5867 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5426 (0x22BDu)
5868 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5427 (0x6963u)
5869 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5428 (0x363Cu)
5870 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5429 (0x3CD1u)
5871 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5430 (0x196Du)
5872 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5431 (0x64DAu)
5873 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5432 (0x5696u)
5874 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5433 (0x1E71u)
5875 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5434 (0x6B89u)
5876 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5435 (0x3176u)
5877 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5436 (0x6275u)
5878 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5437 (0x39CAu)
5879 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5438 (0x4B96u)
5880 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5439 (0x76D0u)
5881 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5440 (0x13ECu)
5882 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5441 (0x698Eu)
5883 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5442 (0x3E19u)
5884 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5443 (0x65B8u)
5885 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5444 (0x741Du)
5886 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5445 (0x4FA2u)
5887 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5446 (0x7A31u)
5888 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5447 (0x695Au)
5889 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5448 (0x2D2Du)
5890 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5449 (0x4D8Du)
5891 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5450 (0x4747u)
5892 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5451 (0x26E5u)
5893 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5452 (0x4CD6u)
5894 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5453 (0x71C3u)
5895 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5454 (0x4E53u)
5896 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5455 (0x2AAEu)
5897 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5456 (0x3517u)
5898 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5457 (0x1D6Au)
5899 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5458 (0x10BFu)
5900 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5459 (0x531Eu)
5901 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5460 (0x0E67u)
5902 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5461 (0x62D3u)
5903 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5462 (0x3553u)
5904 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5463 (0x4BA3u)
5905 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5464 (0x613Bu)
5906 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5465 (0x7166u)
5907 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5466 (0x3137u)
5908 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5467 (0x2D5Au)
5909 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5468 (0x0AFAu)
5910 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5469 (0x446Fu)
5911 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5470 (0x0BBCu)
5912 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5471 (0x6CB4u)
5913 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5472 (0x699Cu)
5914 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5473 (0x1C73u)
5915 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5474 (0x28CFu)
5916 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5475 (0x3A27u)
5917 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5476 (0x7D05u)
5918 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5477 (0x6995u)
5919 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5478 (0x1AD6u)
5920 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5479 (0x1A5Bu)
5921 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5480 (0x1F8Cu)
5922 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5481 (0x79A2u)
5923 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5482 (0x70E9u)
5924 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5483 (0x5F44u)
5925 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5484 (0x6B62u)
5926 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5485 (0x3AAAu)
5927 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5486 (0x5AB1u)
5928 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5487 (0x6CCCu)
5929 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5488 (0x47E4u)
5930 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5489 (0x0E3Du)
5931 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5490 (0x6D26u)
5932 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5491 (0x2BE2u)
5933 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5492 (0x47D8u)
5934 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5493 (0x66C3u)
5935 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5494 (0x437Cu)
5936 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5495 (0x06BBu)
5937 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5496 (0x4B8Bu)
5938 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5497 (0x4B72u)
5939 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5498 (0x1E95u)
5940 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5499 (0x1A4Fu)
5941 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5500 (0x16CEu)
5942 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5501 (0x7788u)
5943 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5502 (0x6BB0u)
5944 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5503 (0x71B8u)
5945 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5504 (0x4E55u)
5946 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5505 (0x7C68u)
5947 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5506 (0x42EEu)
5948 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5507 (0x6C93u)
5949 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5508 (0x2DE2u)
5950 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5509 (0x338Eu)
5951 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5510 (0x1EC3u)
5952 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5511 (0x64F2u)
5953 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5512 (0x56C5u)
5954 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5513 (0x1EF0u)
5955 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5514 (0x52BAu)
5956 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5515 (0x72D4u)
5957 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5516 (0x4C9Du)
5958 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5517 (0x6B38u)
5959 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5518 (0x3E0Du)
5960 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5519 (0x391Bu)
5961 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5520 (0x56E1u)
5962 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5521 (0x7625u)
5963 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5522 (0x4AECu)
5964 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5523 (0x074Fu)
5965 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5524 (0x0CF9u)
5966 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5525 (0x263Eu)
5967 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5526 (0x3E38u)
5968 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5527 (0x7946u)
5969 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5528 (0x1BC5u)
5970 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5529 (0x2D2Bu)
5971 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5530 (0x38ABu)
5972 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5531 (0x370Eu)
5973 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5532 (0x3A2Eu)
5974 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5533 (0x3279u)
5975 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5534 (0x711Bu)
5976 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5535 (0x72E1u)
5977 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5536 (0x57B0u)
5978 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5537 (0x65E4u)
5979 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5538 (0x643Bu)
5980 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5539 (0x49E9u)
5981 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5540 (0x387Au)
5982 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5541 (0x7B03u)
5983 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5542 (0x4CE5u)
5984 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5543 (0x582Fu)
5985 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5544 (0x6A1Eu)
5986 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5545 (0x0779u)
5987 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5546 (0x1E56u)
5988 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5547 (0x58CBu)
5989 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5548 (0x713Cu)
5990 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5549 (0x4F89u)
5991 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5550 (0x7436u)
5992 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5551 (0x7594u)
5993 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5552 (0x1A9Du)
5994 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5553 (0x6E16u)
5995 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5554 (0x48AFu)
5996 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5555 (0x49B3u)
5997 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5556 (0x2D3Cu)
5998 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5557 (0x7165u)
5999 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5558 (0x0775u)
6000 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5559 (0x4E72u)
6001 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5560 (0x65A6u)
6002 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5561 (0x04EFu)
6003 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5562 (0x616Bu)
6004 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5563 (0x2E36u)
6005 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5564 (0x704Fu)
6006 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5565 (0x35A3u)
6007 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5566 (0x4C67u)
6008 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5567 (0x72C5u)
6009 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5568 (0x7711u)
6010 #define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5569 (0x4AD6u)
6011 
6012 MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER()
6013 
6014 #endif /* MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00263_source.html b/components/els_pkc/doc/mcxn/html/a00263_source.html new file mode 100644 index 000000000..64c6eee4e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00263_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClCore_Platform.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCore_Platform.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCORE_PLATFORM_H_
15 #define MCUXCLCORE_PLATFORM_H_
16 
17 #include <stddef.h>
18 #include <stdint.h>
19 #include <stdbool.h>
20 
21 #include <mcuxClConfig.h> // Exported features flags header
22 
23 #endif /* MCUXCLCORE_PLATFORM_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00266_source.html b/components/els_pkc/doc/mcxn/html/a00266_source.html new file mode 100644 index 000000000..632016dd8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00266_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClCore_Toolchain.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClCore_Toolchain.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLCORE_TOOLCHAIN_H_
15 #define MCUXCLCORE_TOOLCHAIN_H_
16 
17 #include <mcuxClCore_Platform.h>
18 #include <mcuxCsslFlowProtection.h>
19 
20 MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap64)
21 static inline uint64_t mcuxCl_Core_Swap64(uint64_t value)
22 {
23  return __builtin_bswap64(value);
24 }
25 
26 MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap32)
27 static inline uint32_t mcuxCl_Core_Swap32(uint32_t value)
28 {
29  return __builtin_bswap32(value);
30 }
31 
32 
33 #endif /* MCUXCLCORE_TOOLCHAIN_H_ */
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DEF
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
Definition of a flow protected function.
Definition: mcuxCsslFlowProtection.h:159
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00269.html b/components/els_pkc/doc/mcxn/html/a00269.html new file mode 100644 index 000000000..91839b126 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00269.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClEcc.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
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+
+ + +
+ +
+ +
+
+
mcuxClEcc.h File Reference
+
+
+ +

Top level header of mcuxClEcc component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEcc_Types.h>
+#include <mcuxClEcc_Functions.h>
+#include <mcuxClEcc_MemoryConsumption.h>
+#include <mcuxClEcc_Constants.h>
+#include <mcuxClEcc_ParameterSizes.h>
+#include <mcuxClEcc_KeyMechanisms.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00269_source.html b/components/els_pkc/doc/mcxn/html/a00269_source.html new file mode 100644 index 000000000..cee696869 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00269_source.html @@ -0,0 +1,127 @@ + + + + + + + +MCUX CLNS: mcuxClEcc.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
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+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
23 #ifndef MCUXCLECC_H_
24 #define MCUXCLECC_H_
25 
26 #include <mcuxClConfig.h> // Exported features flags header
27 #include <mcuxClEcc_Types.h>
28 #include <mcuxClEcc_Functions.h>
29 #include <mcuxClEcc_MemoryConsumption.h>
30 #include <mcuxClEcc_Constants.h>
31 #include <mcuxClEcc_ParameterSizes.h>
32 #include <mcuxClEcc_KeyMechanisms.h>
33 
34 
35 
36 #endif /* MCUXCLECC_H_ */
mcuxClEcc_ParameterSizes.h
Definitions of ECC domain parameter, key and signature sizes.
+
mcuxClEcc_Types.h
Type definitions of mcuxClEcc component.
+
mcuxClEcc_Functions.h
Top level APIs of mcuxClEcc component.
+
mcuxClEcc_MemoryConsumption.h
Defines the memory consumption for the mcuxClEcc component.
+
mcuxClEcc_KeyMechanisms.h
ECC related definitions to be used for key handling mechanisms of the mcuxClKey component.
+
mcuxClEcc_Constants.h
Constants definition for domain parameters of supported curves.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00272.html b/components/els_pkc/doc/mcxn/html/a00272.html new file mode 100644 index 000000000..becd065f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00272.html @@ -0,0 +1,257 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ +
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+ + +
+ +
+ +
+
+Macros | +Variables
+
+
mcuxClEcc_Constants.h File Reference
+
+
+ +

Constants definition for domain parameters of supported curves. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEcc_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define mcuxClEcc_Weier_DomainParams_NIST_P192
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p192r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P224
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p224r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P256
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p256r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P384
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p384r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P521
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p521r1
 
+#define MCUXCLECC_EDDSA_PHFLAG_ZERO
 
+#define MCUXCLECC_EDDSA_PHFLAG_ONE
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve25519
 
+const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve448
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp160k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp384r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp521r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512t1
 
+const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed25519
 
+const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed448
 
+

Detailed Description

+

Constants definition for domain parameters of supported curves.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00272.js b/components/els_pkc/doc/mcxn/html/a00272.js new file mode 100644 index 000000000..0a7dba78a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00272.js @@ -0,0 +1,42 @@ +var a00272 = +[ + [ "mcuxClEcc_Weier_DomainParams_NIST_P192", "a00680.html#gabe95df8265e4d7295f57a78e5f5ed97b", null ], + [ "mcuxClEcc_Weier_DomainParams_ansix9p192r1", "a00680.html#ga2f517597a50ff98d33fa5578297965ff", null ], + [ "mcuxClEcc_Weier_DomainParams_NIST_P224", "a00680.html#ga915b5e2b7610fa471163dbaabbc7f05e", null ], + [ "mcuxClEcc_Weier_DomainParams_ansix9p224r1", "a00680.html#gae62b906fe7cf8f6f03e7db723e1e03f9", null ], + [ "mcuxClEcc_Weier_DomainParams_NIST_P256", "a00680.html#ga13b24b605539761b3dbf567c6a836188", null ], + [ "mcuxClEcc_Weier_DomainParams_ansix9p256r1", "a00680.html#ga51137f47fa6da6863aff3986fb6777b3", null ], + [ "mcuxClEcc_Weier_DomainParams_NIST_P384", "a00680.html#ga8e7697891b0bb90edfe86c54fe30c869", null ], + [ "mcuxClEcc_Weier_DomainParams_ansix9p384r1", "a00680.html#ga59f49a94c99e0dafb74d50af68d26c95", null ], + [ "mcuxClEcc_Weier_DomainParams_NIST_P521", "a00680.html#ga245bc63cdc97b931d33814f0786aa2d7", null ], + [ "mcuxClEcc_Weier_DomainParams_ansix9p521r1", "a00680.html#ga099d34a166b431c2d9233c6c8bf0c976", null ], + [ "MCUXCLECC_EDDSA_PHFLAG_ZERO", "a00680.html#gaf1be797d5a17411e0259ed8885dc1d17", null ], + [ "MCUXCLECC_EDDSA_PHFLAG_ONE", "a00680.html#ga834b59a03ee5e206312030a46844598a", null ], + [ "mcuxClEcc_MontDH_DomainParams_Curve25519", "a00680.html#ga0a4b1c3036d360b7a5954b6763edcd4d", null ], + [ "mcuxClEcc_MontDH_DomainParams_Curve448", "a00680.html#ga41c84ad3d583df9a60c756afab58cbbf", null ], + [ "mcuxClEcc_Weier_DomainParams_secp160k1", "a00680.html#ga598afef59bd9f6448224a9df05d4ff71", null ], + [ "mcuxClEcc_Weier_DomainParams_secp192k1", "a00680.html#ga7e827ee1bf34d1af6dfbde1b855c9be9", null ], + [ "mcuxClEcc_Weier_DomainParams_secp224k1", "a00680.html#gad446197691360de63d4b645ac7e2897d", null ], + [ "mcuxClEcc_Weier_DomainParams_secp256k1", "a00680.html#gaee71310d7a77c8bf985137be03a14ada", null ], + [ "mcuxClEcc_Weier_DomainParams_secp192r1", "a00680.html#gac40968fdc1cb7351e102c0bba5e29e0b", null ], + [ "mcuxClEcc_Weier_DomainParams_secp224r1", "a00680.html#ga126369b0016bed6188fb502df38bffb0", null ], + [ "mcuxClEcc_Weier_DomainParams_secp256r1", "a00680.html#gaf1296b696fcfd63ce97e91fb52d0e36c", null ], + [ "mcuxClEcc_Weier_DomainParams_secp384r1", "a00680.html#ga8765b672d80547274f0620470ce71b16", null ], + [ "mcuxClEcc_Weier_DomainParams_secp521r1", "a00680.html#gaf9393efb042a2268e6ab55f964238e90", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP160r1", "a00680.html#ga4dcf91bc5ba21ad8c1d67240cc0e5bae", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP192r1", "a00680.html#ga33e51ff79d9343b35a953d4394994df0", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP224r1", "a00680.html#gab8981620e671ac98b4140cfc5c75216d", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP256r1", "a00680.html#gac5235482a5b38f32502c60de1512dca8", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP320r1", "a00680.html#ga3e7fd1cae4cebdf5c293e0c8d4882b68", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP384r1", "a00680.html#gaae38ee9014acd39b266978e16e2428ac", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP512r1", "a00680.html#gad1ff7f8a3a24e40c9c621bc704bab5e7", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP160t1", "a00680.html#ga4c1962dd1de1cd509fb04fd5016aa9b2", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP192t1", "a00680.html#ga1474ba3c37506a0ba9d2c1b7e748bcde", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP224t1", "a00680.html#gac23c3d43571efa1145db6ffae9184653", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP256t1", "a00680.html#ga458fd129751ae0cca77e8e0e8a7f4769", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP320t1", "a00680.html#ga20897f773d6002975c81e6179d79e342", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP384t1", "a00680.html#ga67d56b0bca2655301baf1ca656c42f41", null ], + [ "mcuxClEcc_Weier_DomainParams_brainpoolP512t1", "a00680.html#gab06e470839d66dc13573623fd365375b", null ], + [ "mcuxClEcc_EdDSA_DomainParams_Ed25519", "a00680.html#gae4378399b889f8e1cfa3d59bac99b26a", null ], + [ "mcuxClEcc_EdDSA_DomainParams_Ed448", "a00680.html#ga7e9a5c7412b123fe9cc8d5e52e88410f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00272_source.html b/components/els_pkc/doc/mcxn/html/a00272_source.html new file mode 100644 index 000000000..c703b1789 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00272_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 /* TODO: domain parameters are not verified, and will be verified in CLNS-5817 */
20 
21 #ifndef MCUXCLECC_CONSTANTS_H_
22 #define MCUXCLECC_CONSTANTS_H_
23 
24 #include <mcuxClConfig.h> // Exported features flags header
25 #include <mcuxClEcc_Types.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
39 /* Curve25519 domain parameters */
40 extern const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve25519;
41 
42 /* Curve448 domain parameters */
43 extern const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve448;
44 
45 /* secp160k1 domain parameters */
46 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp160k1;
47 
48 /* secp192k1 domain parameters */
49 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192k1;
50 
51 /* sec224k1 domain parameters */
52 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224k1;
53 
54 /* secp256k1 domain parameters */
55 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256k1;
56 
57 /* secp192r1 (nistp192r1, ansix9p192r1) domain parameters */
58 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192r1;
59 #define mcuxClEcc_Weier_DomainParams_NIST_P192 mcuxClEcc_Weier_DomainParams_secp192r1
60 #define mcuxClEcc_Weier_DomainParams_ansix9p192r1 mcuxClEcc_Weier_DomainParams_secp192r1
61 
62 /* secp224r1 (nistp224r1, ansix9p224r1) domain parameters */
63 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224r1;
64 #define mcuxClEcc_Weier_DomainParams_NIST_P224 mcuxClEcc_Weier_DomainParams_secp224r1
65 #define mcuxClEcc_Weier_DomainParams_ansix9p224r1 mcuxClEcc_Weier_DomainParams_secp224r1
66 
67 /* secp256r1 (nistp256r1, ansix9p256r1) domain parameters */
68 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256r1;
69 #define mcuxClEcc_Weier_DomainParams_NIST_P256 mcuxClEcc_Weier_DomainParams_secp256r1
70 #define mcuxClEcc_Weier_DomainParams_ansix9p256r1 mcuxClEcc_Weier_DomainParams_secp256r1
71 
72 /* secp384r1 (nistp384r1, ansix9p384r1) domain parameters */
73 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp384r1;
74 #define mcuxClEcc_Weier_DomainParams_NIST_P384 mcuxClEcc_Weier_DomainParams_secp384r1
75 #define mcuxClEcc_Weier_DomainParams_ansix9p384r1 mcuxClEcc_Weier_DomainParams_secp384r1
76 
77 /* secp521r1 (nistp521r1, ansix9p521r1) domain parameters */
78 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp521r1;
79 #define mcuxClEcc_Weier_DomainParams_NIST_P521 mcuxClEcc_Weier_DomainParams_secp521r1
80 #define mcuxClEcc_Weier_DomainParams_ansix9p521r1 mcuxClEcc_Weier_DomainParams_secp521r1
81 
82 /* brainpoolP160r1 domain parameters */
83 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160r1;
84 
85 /* brainpoolP192r1 domain parameters */
86 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192r1;
87 
88 /* brainpoolP224r1 domain parameters */
89 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224r1;
90 
91 /* brainpoolP256r1 domain parameters */
92 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256r1;
93 
94 /* brainpoolP320r1 domain parameters */
95 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320r1;
96 
97 /* brainpoolP384r1 domain parameters */
98 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384r1;
99 
100 /* brainpoolP512r1 domain parameters */
101 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512r1;
102 
103 /* brainpoolP160t1 domain parameters */
104 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160t1;
105 
106 /* brainpoolP192t1 domain parameters */
107 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192t1;
108 
109 /* brainpoolP224t1 domain parameters */
110 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224t1;
111 
112 /* brainpoolP256t1 domain parameters */
113 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256t1;
114 
115 /* brainpoolP320t1 domain parameters */
116 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320t1;
117 
118 /* brainpoolP384t1 domain parameters */
119 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384t1;
120 
121 /* brainpoolP512t1 domain parameters */
122 extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512t1;
123 
124 
125 /* Ed25519 domain parameters */
126 extern const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed25519;
127 
128 /* Ed448 domain parameters */
129 extern const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed448;
130 
131 /* phflag values for EdDSA */
132 #define MCUXCLECC_EDDSA_PHFLAG_ZERO 0u
133 #define MCUXCLECC_EDDSA_PHFLAG_ONE 1u
134  /* mcuxClEcc_Constants */
138 
139 #ifdef __cplusplus
140 } /* extern "C" */
141 #endif
142 
143 #endif /* MCUXCLECC_CONSTANTS_H_ */
mcuxClEcc_Types.h
Type definitions of mcuxClEcc component.
+
mcuxClEcc_EdDSA_DomainParams_t
struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
Type for EdDSA domain parameters.
Definition: mcuxClEcc_Types.h:96
+
mcuxClEcc_Weier_DomainParams_t
struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
Type for Weierstrass ECC domain parameters.
Definition: mcuxClEcc_Types.h:120
+
mcuxClEcc_MontDH_DomainParams_t
struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t
Type for MontDH domain parameters.
Definition: mcuxClEcc_Types.h:92
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00275.html b/components/els_pkc/doc/mcxn/html/a00275.html new file mode 100644 index 000000000..3cd01c45b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00275.html @@ -0,0 +1,175 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Functions
+
+
mcuxClEcc_Functions.h File Reference
+
+
+ +

Top level APIs of mcuxClEcc component. +More...

+
#include <stdint.h>
+#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxClEcc_Types.h>
+#include <mcuxClKey.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClEcc_Status_t mcuxClEcc_KeyGen (mcuxClSession_Handle_t pSession, const mcuxClEcc_KeyGen_Param_t *pParam)
 implements ECDSA key generation. More...
 
mcuxClEcc_Status_t mcuxClEcc_Sign (mcuxClSession_Handle_t pSession, const mcuxClEcc_Sign_Param_t *pParam)
 implements ECDSA signature generation. More...
 
mcuxClEcc_Status_t mcuxClEcc_Verify (mcuxClSession_Handle_t pSession, const mcuxClEcc_Verify_Param_t *pParam)
 implements ECDSA signature verification. More...
 
mcuxClEcc_Status_t mcuxClEcc_PointMult (mcuxClSession_Handle_t pSession, const mcuxClEcc_PointMult_Param_t *pParam)
 implements ECC point multiplication. More...
 
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyGeneration (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 implements ECC key pair generation step for a MontDh key agreement according to rfc7748. More...
 
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyAgreement (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Handle_t otherKey, uint8_t *pOut, uint32_t *const pOutLength)
 implements ECC key agreement according to rfc7748. More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateKeyPair (mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
 This function implements the EdDSA key pair generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.5 and 5.2.5 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateSignature (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, uint8_t *pSignature, uint32_t *const pSignatureSize)
 This function implements the EdDSA signature generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.6 and 5.2.6 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_VerifySignature (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, const uint8_t *pSignature, uint32_t signatureSize)
 This function implements the EdDSA signature verification for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.7 and 5.2.7 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_InitPrivKeyInputMode (mcuxClSession_Handle_t pSession, mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, const uint8_t *pPrivKey)
 This function initializes an EdDSA mode descriptor for EdDSA key pair generation with private key input. More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateProtocolDescriptor (mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor, uint32_t phflag, mcuxCl_InputBuffer_t pContext, uint32_t contextLen)
 This function implements the protocol descriptor generation for Ed25519ctx, Ed25519ph, Ed448 and Ed448ph. More...
 
+

Detailed Description

+

Top level APIs of mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00275.js b/components/els_pkc/doc/mcxn/html/a00275.js new file mode 100644 index 000000000..ad4a0c9b9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00275.js @@ -0,0 +1,14 @@ +var a00275 = +[ + [ "mcuxClEcc_KeyGen", "a00681.html#gabc728b0278908265f9923535391005dc", null ], + [ "mcuxClEcc_Sign", "a00681.html#ga105ec4e9dc29573334f52979381686de", null ], + [ "mcuxClEcc_Verify", "a00681.html#ga80f15538ec3cb2d3bfa8dc2f2da86366", null ], + [ "mcuxClEcc_PointMult", "a00681.html#gab199a221c61f252a0c755ab8d8a6a77c", null ], + [ "mcuxClEcc_Mont_DhKeyGeneration", "a00681.html#ga71406ab7d35c51f12c01efcb73305196", null ], + [ "mcuxClEcc_Mont_DhKeyAgreement", "a00681.html#gaef77a1a80276b44da54c66a8d606f20d", null ], + [ "mcuxClEcc_EdDSA_GenerateKeyPair", "a00681.html#ga0ac2814cb9c8f4b8718a95d8c2ae2b85", null ], + [ "mcuxClEcc_EdDSA_GenerateSignature", "a00681.html#ga0b9ad0b0aa3afccae32a14aeddf9d8fe", null ], + [ "mcuxClEcc_EdDSA_VerifySignature", "a00681.html#ga514b29374472b14ad00e0e5ef3469c7f", null ], + [ "mcuxClEcc_EdDSA_InitPrivKeyInputMode", "a00681.html#ga78eaff72d9c8202b51c61c6668b9c3aa", null ], + [ "mcuxClEcc_EdDSA_GenerateProtocolDescriptor", "a00681.html#ga54e3517cb9729321cdb4017b0fdc4485", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00275_source.html b/components/els_pkc/doc/mcxn/html/a00275_source.html new file mode 100644 index 000000000..9532958ea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00275_source.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClEcc_Functions.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLECC_FUNCTIONS_H_
21 #define MCUXCLECC_FUNCTIONS_H_
22 
23 
24 #include <stdint.h>
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxClSession.h>
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClCore_FunctionIdentifiers.h>
29 #include <mcuxCsslAnalysis.h>
30 
31 #include <mcuxClEcc_Types.h>
32 
33 #include <mcuxClKey.h>
34 
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /**********************************************************/
41 /* Public APIs of mcuxClEcc */
42 /**********************************************************/
43 
58 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_KeyGen)
59 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_KeyGen(
60  mcuxClSession_Handle_t pSession,
61  const mcuxClEcc_KeyGen_Param_t * pParam
62  );
63 
71 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Sign)
72 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Sign(
73  mcuxClSession_Handle_t pSession,
74  const mcuxClEcc_Sign_Param_t * pParam
75  );
76 
77 
84 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Verify)
85 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Verify(
86  mcuxClSession_Handle_t pSession,
87  const mcuxClEcc_Verify_Param_t * pParam
88  );
89 
118 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_PointMult)
119 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointMult(
120  mcuxClSession_Handle_t pSession,
121  const mcuxClEcc_PointMult_Param_t * pParam
122  );
123 
124 
151 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Mont_DhKeyGeneration)
152 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyGeneration(
153  mcuxClSession_Handle_t pSession,
154  mcuxClKey_Type_t type,
155  mcuxClKey_Protection_t protection,
156  mcuxClKey_Handle_t privKey,
157  uint8_t * pPrivData,
158  uint32_t * const pPrivDataLength,
159  mcuxClKey_Handle_t pubKey,
160  uint8_t * pPubData,
161  uint32_t * const pPubDataLength
162  );
163 
188 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Mont_DhKeyAgreement)
189 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyAgreement(
190  mcuxClSession_Handle_t pSession,
191  mcuxClKey_Handle_t key,
192  mcuxClKey_Handle_t otherKey,
193  uint8_t * pOut,
194  uint32_t * const pOutLength
195  );
196 
197 
198 MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.")
223 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS()
224 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateKeyPair)
225 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateKeyPair(
226  mcuxClSession_Handle_t pSession,
227  const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode,
228  mcuxClKey_Handle_t privKey,
229  mcuxClKey_Handle_t pubKey
230  );
231 
232 MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.")
263 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS()
264 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateSignature)
265 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateSignature(
266  mcuxClSession_Handle_t pSession,
267  mcuxClKey_Handle_t key,
268  const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode,
269  const uint8_t *pIn,
270  uint32_t inSize,
271  uint8_t *pSignature,
272  uint32_t * const pSignatureSize
273  );
274 
275 MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.")
305 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS()
306 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_VerifySignature)
307 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_VerifySignature(
308  mcuxClSession_Handle_t session,
309  mcuxClKey_Handle_t key,
310  const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode,
311  const uint8_t *pIn,
312  uint32_t inSize,
313  const uint8_t *pSignature,
314  uint32_t signatureSize
315  );
316 
328 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_InitPrivKeyInputMode)
329 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_InitPrivKeyInputMode(
330  mcuxClSession_Handle_t pSession,
331  mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode,
332  const uint8_t *pPrivKey
333  );
334 
349 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateProtocolDescriptor)
350 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateProtocolDescriptor(
351  mcuxClSession_Handle_t pSession,
352  const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams,
353  mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor,
354  uint32_t phflag,
355  mcuxCl_InputBuffer_t pContext,
356  uint32_t contextLen);
357 
358 
359 
360 
361  /* mcuxClEcc_Functions */
365 
366 #ifdef __cplusplus
367 } /* extern "C" */
368 #endif
369 
370 #endif /* MCUXCLECC_FUNCTIONS_H_ */
mcuxClEcc_Mont_DhKeyAgreement
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyAgreement(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Handle_t otherKey, uint8_t *pOut, uint32_t *const pOutLength)
implements ECC key agreement according to rfc7748.
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey.h
Top-level include file for the mcuxClKey component.
+
mcuxClEcc_Verify
mcuxClEcc_Status_t mcuxClEcc_Verify(mcuxClSession_Handle_t pSession, const mcuxClEcc_Verify_Param_t *pParam)
implements ECDSA signature verification.
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
EdDSA GenerateKeyPair variant descriptor type.
Definition: mcuxClEcc_Types.h:106
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClEcc_Types.h
Type definitions of mcuxClEcc component.
+
mcuxClEcc_EdDSA_VerifySignature
mcuxClEcc_Status_t mcuxClEcc_EdDSA_VerifySignature(mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, const uint8_t *pSignature, uint32_t signatureSize)
This function implements the EdDSA signature verification for Ed25519 and Ed448 as specified in rfc80...
+
mcuxClEcc_Sign_Param_t
Parameter structure for function mcuxClEcc_Sign.
Definition: mcuxClEcc_Types.h:164
+
mcuxClEcc_PointMult
mcuxClEcc_Status_t mcuxClEcc_PointMult(mcuxClSession_Handle_t pSession, const mcuxClEcc_PointMult_Param_t *pParam)
implements ECC point multiplication.
+
mcuxClEcc_KeyGen
mcuxClEcc_Status_t mcuxClEcc_KeyGen(mcuxClSession_Handle_t pSession, const mcuxClEcc_KeyGen_Param_t *pParam)
implements ECDSA key generation.
+
mcuxClEcc_EdDSA_DomainParams_t
struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
Type for EdDSA domain parameters.
Definition: mcuxClEcc_Types.h:96
+
mcuxClKey_Protection_t
const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
Key protection mechanism type.
Definition: mcuxClKey_Types.h:141
+
mcuxClEcc_EdDSA_GenerateKeyPair
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateKeyPair(mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
This function implements the EdDSA key pair generation for Ed25519 and Ed448 as specified in rfc8032 ...
+
mcuxClEcc_Mont_DhKeyGeneration
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyGeneration(mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
implements ECC key pair generation step for a MontDh key agreement according to rfc7748.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClEcc_Sign
mcuxClEcc_Status_t mcuxClEcc_Sign(mcuxClSession_Handle_t pSession, const mcuxClEcc_Sign_Param_t *pParam)
implements ECDSA signature generation.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClEcc_EdDSA_GenerateSignature
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateSignature(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, uint8_t *pSignature, uint32_t *const pSignatureSize)
This function implements the EdDSA signature generation for Ed25519 and Ed448 as specified in rfc8032...
+
mcuxClEcc_PointMult_Param_t
Parameter structure for function mcuxClEcc_PointMult.
Definition: mcuxClEcc_Types.h:205
+
mcuxClEcc_KeyGen_Param_t
Parameter structure for function mcuxClEcc_KeyGen.
Definition: mcuxClEcc_Types.h:152
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEcc_EdDSA_InitPrivKeyInputMode
mcuxClEcc_Status_t mcuxClEcc_EdDSA_InitPrivKeyInputMode(mcuxClSession_Handle_t pSession, mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, const uint8_t *pPrivKey)
This function initializes an EdDSA mode descriptor for EdDSA key pair generation with private key inp...
+
mcuxClEcc_Status_t
uint32_t mcuxClEcc_Status_t
Type for mcuxClEcc component return codes.
Definition: mcuxClEcc_Types.h:48
+
mcuxClEcc_Verify_Param_t
Parameter structure for function mcuxClEcc_Verify.
Definition: mcuxClEcc_Types.h:183
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
mcuxClEcc_EdDSA_GenerateProtocolDescriptor
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateProtocolDescriptor(mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor, uint32_t phflag, mcuxCl_InputBuffer_t pContext, uint32_t contextLen)
This function implements the protocol descriptor generation for Ed25519ctx, Ed25519ph,...
+
mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
EdDSA SignatureProtocol variant descriptor type.
Definition: mcuxClEcc_Types.h:116
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00278.html b/components/els_pkc/doc/mcxn/html/a00278.html new file mode 100644 index 000000000..dca4a4878 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00278.html @@ -0,0 +1,513 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_KeyMechanisms.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Macros | +Variables
+
+
mcuxClEcc_KeyMechanisms.h File Reference
+
+
+ +

ECC related definitions to be used for key handling mechanisms of the mcuxClKey component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEcc_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-192. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-192. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-224. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-224. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-256. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-256. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-384. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-384. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-521. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-521. More...
 
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+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp160k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp160k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp160k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp160k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp192k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp192k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp192k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp224k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp224k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp224k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp256k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp256k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp256k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp521r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-192. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-224. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-224. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-384. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-384. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-521. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-521. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP160r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP160r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP160r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP320r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP320r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP320r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP512r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP512r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP512r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP160t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP160t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP160t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP192t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP192t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP192t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP224t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP224t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP224t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP256t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP256t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP256t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP320t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP320t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP320t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP384t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP384t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP384t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP512t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP512t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP512t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv
 Key type structure for ECC EdDSA Ed25519 private keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv
 Key type pointer for ECC EdDSA Ed25519 private keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub
 Key type structure for ECC EdDSA Ed25519 public keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub
 Key type pointer for ECC EdDSA Ed25519 public keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv
 Key type structure for ECC EdDSA Ed448 private keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv
 Key type pointer for ECC EdDSA Ed448 private keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub
 Key type structure for ECC EdDSA Ed448 public keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub
 Key type pointer for ECC EdDSA Ed448 public keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair
 Key type structure for ECC MontDH Curve25519 Key pairs. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair
 Key type pointer for ECC MontDH Curve25519 Key pairs. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair
 Key type structure for ECC MontDH Curve448 Key pairs. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair
 Key type pointer for ECC MontDH Curve448 Key pairs. More...
 
+

Detailed Description

+

ECC related definitions to be used for key handling mechanisms of the mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00278.js b/components/els_pkc/doc/mcxn/html/a00278.js new file mode 100644 index 000000000..68db617e1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00278.js @@ -0,0 +1,127 @@ +var a00278 = +[ + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub", "a00682.html#ga697b811095baa95d968a6710b78dda40", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv", "a00682.html#gaf0d412d5ea6506c4afa947ef3d17646c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub", "a00682.html#ga40820475ba5218c1746f3de54035367f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv", "a00682.html#gaf049264c890164b02d97139deb8c1471", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub", "a00682.html#ga66bb90651426a91d158794a3c79df29f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv", "a00682.html#gab13c07ea082e362aefed4814123ff724", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub", "a00682.html#gadad85b76aaf6f7c99a0264392a31a5a1", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv", "a00682.html#ga5177e841e9f5754aded42239c95b4263", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub", "a00682.html#ga34397e23e613e3662aabe96baeb7dd99", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv", "a00682.html#gac4ff88aeb6544eee998bbe565e870856", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub", "a00682.html#ga45f80b52c3713407e5ea8d874fcab224", null ], + [ "mcuxClKey_Type_WeierECC_secp160k1_Pub", "a00682.html#ga4345462d03a5a61641bfbbd3a2d5b86e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv", "a00682.html#ga5be9d578c7e89fb9ddeb24ce1dd87705", null ], + [ "mcuxClKey_Type_WeierECC_secp160k1_Priv", "a00682.html#ga919b93483d11e303265fc8db41c4c03f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub", "a00682.html#gae82b0b8a866aa021d9be12d673ea44cb", null ], + [ "mcuxClKey_Type_WeierECC_secp192k1_Pub", "a00682.html#gaade00cdba0ae71d0ead7474186e8b9fa", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv", "a00682.html#ga4464ec90b697f37d0c77f371ffd25f73", null ], + [ "mcuxClKey_Type_WeierECC_secp192k1_Priv", "a00682.html#ga1bbeb45dc0f37b64ddf7d54890d1d5da", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub", "a00682.html#ga72e156ee2a9ac1c0808fb54be1c37854", null ], + [ "mcuxClKey_Type_WeierECC_secp224k1_Pub", "a00682.html#ga75e6fbe876aa640a0fade7940ed23c3b", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv", "a00682.html#gaacbea5c086db4ecfa1e481d64e64c034", null ], + [ "mcuxClKey_Type_WeierECC_secp224k1_Priv", "a00682.html#ga8754b1ec3ded884876adbb0145d1e054", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub", "a00682.html#gafb9d141d04c292a77577c8593f379dae", null ], + [ "mcuxClKey_Type_WeierECC_secp256k1_Pub", "a00682.html#ga41cecc27d7f37dfc1bca1158fa42af05", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv", "a00682.html#ga39040d5c10a5245ba45acb94304704f5", null ], + [ "mcuxClKey_Type_WeierECC_secp256k1_Priv", "a00682.html#ga9e922253404f7608e004929b2e994d7d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub", "a00682.html#gad6f5289ef5ca2a8675ab7086b35522df", null ], + [ "mcuxClKey_Type_WeierECC_secp192r1_Pub", "a00682.html#gaf003efa3e8861d0651ce6616abf5d919", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv", "a00682.html#ga9696729f938dcffb197bb7ec7cf68ab7", null ], + [ "mcuxClKey_Type_WeierECC_secp192r1_Priv", "a00682.html#ga000d450d23f8c6980674668531ad4727", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub", "a00682.html#ga243160a6bd14bfcfae0feab8cfec4444", null ], + [ "mcuxClKey_Type_WeierECC_secp224r1_Pub", "a00682.html#ga3b602493fe22f22f91da3f6159ebe79c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv", "a00682.html#ga9d9727c76f81c36e06c5202eced2d73b", null ], + [ "mcuxClKey_Type_WeierECC_secp224r1_Priv", "a00682.html#gabaef750bcfea399f7cf7e397d1b637e6", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub", "a00682.html#ga82bfa972e94322b417a5ddf43932a2ec", null ], + [ "mcuxClKey_Type_WeierECC_secp256r1_Pub", "a00682.html#gafc846d07facc686d0d6fcf7a46e7eb67", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv", "a00682.html#gaddbf6d8826069565a1e79fb24d8cb3b2", null ], + [ "mcuxClKey_Type_WeierECC_secp256r1_Priv", "a00682.html#gac945c22c4932453b64a0369e168aa05a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub", "a00682.html#ga21b1d68989a19b915dd5106075e29cb3", null ], + [ "mcuxClKey_Type_WeierECC_secp384r1_Pub", "a00682.html#ga5e8db8f1f69ba0886f3a568e3eef3777", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv", "a00682.html#gac745b76bab619fff5fe1146fb7d71a50", null ], + [ "mcuxClKey_Type_WeierECC_secp384r1_Priv", "a00682.html#ga4456ec80ccaa45cf7a715719acb9195d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub", "a00682.html#ga6269f061cab69e82df4cd7b9656c8a2c", null ], + [ "mcuxClKey_Type_WeierECC_secp521r1_Pub", "a00682.html#ga4922658a5dbdafb18e9a26aa62d047d9", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv", "a00682.html#ga06483f379dc8873d7cc30c300610e327", null ], + [ "mcuxClKey_Type_WeierECC_secp521r1_Priv", "a00682.html#ga8898847c8409dd00985474ce2bfd9e7b", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P192_Pub", "a00682.html#ga06b92e495eab87142fc07c469fac5526", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P192_Priv", "a00682.html#gab3bd456d3e79c18bb52852012a785a7c", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P224_Pub", "a00682.html#ga0a61957ec8619856fe03204d56bd7a14", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P224_Priv", "a00682.html#ga8449862f98fdfc750c8990a06e561bc7", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P256_Pub", "a00682.html#ga7f344daa7b996e30a163c9053f05ac5f", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P256_Priv", "a00682.html#gacc7e8ff2ac5a8a3d894d7a9da0a80341", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P384_Pub", "a00682.html#ga2ee917bf64caddab241b566099acf669", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P384_Priv", "a00682.html#ga690fd09dedd835e6d9e99e6de82f3ba0", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P521_Pub", "a00682.html#ga4fa543596682506a51f4078409dc3731", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P521_Priv", "a00682.html#ga0b3881b7f5ef6077eaca0d37395a320e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub", "a00682.html#ga62389be1de20d8cf7dfdf9416766ce59", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub", "a00682.html#ga953ce0f67b3ba06382f7ca22eec53b3e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv", "a00682.html#gafee54bf1b90cab43955656fdf688e6b9", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv", "a00682.html#gadee38fd7f3c37112e45316828a1b421d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub", "a00682.html#ga55895a7c4d7dbde9cb53e27ce4aadc36", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub", "a00682.html#ga6f2fdb757ee68215625ffb9d32bab892", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv", "a00682.html#gaf7713f17a5c6504d79a4cc19a619d1bf", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv", "a00682.html#ga58315a40eb971b7d1ae90d906eb30319", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub", "a00682.html#ga71ccfd1a0541def6aa05b24db3059b10", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub", "a00682.html#ga78e896c33933303cacce198571f1d525", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv", "a00682.html#ga2eefdf975f757f135792dedcc500c9f5", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv", "a00682.html#ga67db10ea32d18c91b828214d9d38ac8b", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub", "a00682.html#ga81ed0e23c5cb230eaf68b43e2d037dde", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub", "a00682.html#ga37b4c94b2e841b2f3eb2331083b76f5f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv", "a00682.html#ga1c0248997a1ae57f004b96d063240fc7", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv", "a00682.html#ga9de0651cd7e19b5a7d5b3e782a8cdb78", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub", "a00682.html#ga3578f443c84fa6e97c7fa21bd5765461", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub", "a00682.html#ga91e507098e21780ba47f892d18197b26", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv", "a00682.html#ga3eb4a76b7cd7e5b04b69f1af7d430a24", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv", "a00682.html#ga073b9c815509c8321bdeb396d8f377d5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub", "a00682.html#ga72edef6223f86b15d63f282c0a9119bc", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub", "a00682.html#gade346aa31f4479a953d693d24be3005c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv", "a00682.html#ga4c70e1c0c3dec2ae4b89fd544987724b", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv", "a00682.html#ga8a996e206f32bd964d23537c41f27b25", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub", "a00682.html#gace90d3010bf72d3289a1f5ab249c07a2", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub", "a00682.html#ga90516c497fc468872c20797ea042d7d6", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv", "a00682.html#gac15a4416fa5fa537f67a456e68b9e81a", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv", "a00682.html#ga0973ccb9a10dba4e034096093ea24b22", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub", "a00682.html#gabe551efbcc35efcba391ee767b7f7ff0", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub", "a00682.html#ga8f69f4a645709620e99b354c8d28c57a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv", "a00682.html#ga3e834a29c37352e20f69567334a19ecb", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv", "a00682.html#ga84b46e442f069d514c5061a03c4e9190", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub", "a00682.html#ga5a4502575819fa65e4afad99ce4c1d77", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub", "a00682.html#gaee8f56b3741cb2d385321184ecc3112a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv", "a00682.html#gaec947c583361285beabd1515b85ffa05", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv", "a00682.html#ga9c3d2aedc7cdee77f194a281a79d1b38", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub", "a00682.html#ga0532b3419b3886694736007f0b8e7944", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub", "a00682.html#gaa70ef1ac082befbd2bcb06a1990cf8ca", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv", "a00682.html#ga8b497f39e491a6301f7e27edf74a1d94", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv", "a00682.html#ga6965a5067cf306af93fa18b0d7c40bf5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub", "a00682.html#ga649b579900b6ff23d3009026fa4a7a3a", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub", "a00682.html#ga5d9afd44cd025fbb0b3fc05c0b207597", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv", "a00682.html#ga900bbb5cd092246e2bb83336df1af27e", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv", "a00682.html#ga5d0109f06ed0017ab64a625c290f84a0", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub", "a00682.html#ga45b70649d277b865e410beef5e815198", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub", "a00682.html#ga660a4eedac67861ac691f8e6cce31a2e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv", "a00682.html#ga055bfc9d1fa07fcd80911a4483ee8989", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv", "a00682.html#ga9fd102f8a9a37098e7fbaccd56ccb66c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub", "a00682.html#ga7cd3157e70c933ce8f646c6277d832b6", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub", "a00682.html#ga9efe52ae3219c7c1401dcd2be13b5bd0", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv", "a00682.html#gab5dc15b01d9c0d9dbf847026af187802", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv", "a00682.html#gaa83b67499981c694cc35d63173b908e5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub", "a00682.html#gaa585fea86a1de6d3eee179053ff71396", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub", "a00682.html#ga1346153805fc80794dcd54135e18ded9", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv", "a00682.html#ga980f0af6070d632d144d38c34ca26d0e", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv", "a00682.html#ga6c0ef669e99f161073f329a5e08c7d10", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv", "a00682.html#gab98021bcb61d1707d87106ddae87439c", null ], + [ "mcuxClKey_Type_EdDSA_Ed25519_Priv", "a00682.html#ga4f21b03709a5cac0b713f4e930102af8", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub", "a00682.html#ga3adea0c5fb26beb91e9d5cc798b167fd", null ], + [ "mcuxClKey_Type_EdDSA_Ed25519_Pub", "a00682.html#gab1d91d013e28a086fd4e13175252c049", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv", "a00682.html#gab28b18fd50c1ec6bc4a05c56d1663046", null ], + [ "mcuxClKey_Type_EdDSA_Ed448_Priv", "a00682.html#ga5deb01671f213897a9d54c0e5b5b2ebe", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub", "a00682.html#gae06f9c4d573b51d538a42dfd2cbc4699", null ], + [ "mcuxClKey_Type_EdDSA_Ed448_Pub", "a00682.html#gab35aa6e48e5bd8eda0a1b27c897f81a2", null ], + [ "mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair", "a00682.html#gadfd782e0581049bb1fe40049295807f6", null ], + [ "mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair", "a00682.html#gadcf4ca8f2a1626610da5b9bea5be3d89", null ], + [ "mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair", "a00682.html#ga033a43f0faf219f0e18ced032e1ad694", null ], + [ "mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair", "a00682.html#gae9116a45b5bfb237470625ae7d0fb29b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00278_source.html b/components/els_pkc/doc/mcxn/html/a00278_source.html new file mode 100644 index 000000000..42881a36f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00278_source.html @@ -0,0 +1,248 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_KeyMechanisms.h Source File + + + + + + + + + + + + + + + + +
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+ + +
+ +
+ +
+
+
mcuxClEcc_KeyMechanisms.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLECC_KEYMECHANISMS_H_
21 #define MCUXCLECC_KEYMECHANISMS_H_
22 
23 #include <mcuxClConfig.h> // Exported features flags header
24 #include <mcuxClEcc_Types.h>
25 #include <mcuxCsslAnalysis.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /***********************************************/
39 /* Key types for secp160k1 */
40 /***********************************************/
41 
46 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub;
47 
52 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
53 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub;
54 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
55 
60 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv;
61 
66 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
67 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv;
68 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
69 
70 
71 /***********************************************/
72 /* Key types for secp192k1 */
73 /***********************************************/
74 
79 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub;
80 
85 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
86 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub;
87 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
88 
93 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv;
94 
99 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
100 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv;
101 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
102 
103 
104 /***********************************************/
105 /* Key types for secp224k1 */
106 /***********************************************/
107 
112 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub;
113 
118 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
119 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub;
120 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
121 
126 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv;
127 
132 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
133 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv;
134 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
135 
136 
137 /***********************************************/
138 /* Key types for secp256k1 */
139 /***********************************************/
140 
145 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub;
146 
151 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
152 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub;
153 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
154 
159 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv;
160 
165 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
166 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv;
167 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
168 
169 
170 /***********************************************/
171 /* Key types for secp192r1 */
172 /***********************************************/
173 
178 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub;
179 
184 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
185 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub;
186 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
187 
192 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv;
193 
198 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
199 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv;
200 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
201 
202 
203 /***********************************************/
204 /* Key types for secp224r1 */
205 /***********************************************/
206 
211 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub;
212 
217 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
218 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub;
219 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
220 
225 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv;
226 
231 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
232 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv;
233 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
234 
235 
236 /***********************************************/
237 /* Key types for secp256r1 */
238 /***********************************************/
239 
244 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub;
245 
250 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
251 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub;
252 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
253 
258 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv;
259 
264 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
265 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv;
266 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
267 
268 
269 /***********************************************/
270 /* Key types for secp384r1 */
271 /***********************************************/
272 
277 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub;
278 
283 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
284 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub;
285 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
286 
291 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv;
292 
297 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
298 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv;
299 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
300 
301 
302 /***********************************************/
303 /* Key types for secp521r1 */
304 /***********************************************/
305 
310 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub;
311 
316 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
317 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub;
318 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
319 
324 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv;
325 
330 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
331 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv;
332 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
333 
334 
335 /***********************************************/
336 /* Key types for NIST P-192 */
337 /***********************************************/
338 
343 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
344 
349 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
350 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub;
351 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
352 
357 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
358 
363 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
364 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv;
365 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
366 
367 
368 /***********************************************/
369 /* Key types for NIST P-224 */
370 /***********************************************/
371 
376 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
377 
382 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
383 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub;
384 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
385 
390 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
391 
396 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
397 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv;
398 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
399 
400 
401 /***********************************************/
402 /* Key types for NIST P-256 */
403 /***********************************************/
404 
409 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
410 
415 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
416 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub;
417 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
418 
423 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
424 
429 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
430 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv;
431 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
432 
433 
434 /***********************************************/
435 /* Key types for NIST P-384 */
436 /***********************************************/
437 
442 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
443 
448 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
449 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub;
450 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
451 
456 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
457 
462 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
463 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv;
464 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
465 
466 
467 /***********************************************/
468 /* Key types for NIST P-521 */
469 /***********************************************/
470 
475 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
476 
481 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
482 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub;
483 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
484 
489 #define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
490 
495 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
496 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv;
497 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
498 
499 
500 /***********************************************/
501 /* Key types for brainpoolP160r1 */
502 /***********************************************/
503 
508 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub;
509 
514 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
515 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub;
516 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
517 
522 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv;
523 
528 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
529 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv;
530 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
531 
532 
533 /***********************************************/
534 /* Key types for brainpoolP192r1 */
535 /***********************************************/
536 
541 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub;
542 
547 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
548 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub;
549 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
550 
555 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv;
556 
561 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
562 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv;
563 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
564 
565 
566 /***********************************************/
567 /* Key types for brainpoolP224r1 */
568 /***********************************************/
569 
574 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub;
575 
580 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
581 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub;
582 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
583 
588 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv;
589 
594 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
595 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv;
596 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
597 
598 
599 /***********************************************/
600 /* Key types for brainpoolP256r1 */
601 /***********************************************/
602 
607 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub;
608 
613 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
614 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub;
615 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
616 
621 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv;
622 
627 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
628 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv;
629 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
630 
631 
632 /***********************************************/
633 /* Key types for brainpoolP320r1 */
634 /***********************************************/
635 
640 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub;
641 
646 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
647 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub;
648 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
649 
654 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv;
655 
660 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
661 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv;
662 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
663 
664 
665 /***********************************************/
666 /* Key types for brainpoolP384r1 */
667 /***********************************************/
668 
673 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub;
674 
679 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
680 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub;
681 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
682 
687 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv;
688 
693 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
694 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv;
695 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
696 
697 
698 /***********************************************/
699 /* Key types for brainpoolP512r1 */
700 /***********************************************/
701 
706 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub;
707 
712 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
713 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub;
714 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
715 
720 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv;
721 
726 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
727 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv;
728 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
729 
730 
731 /***********************************************/
732 /* Key types for brainpoolP160t1 */
733 /***********************************************/
734 
739 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub;
740 
745 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
746 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub;
747 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
748 
753 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv;
754 
759 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
760 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv;
761 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
762 
763 
764 /***********************************************/
765 /* Key types for brainpoolP192t1 */
766 /***********************************************/
767 
772 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub;
773 
778 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
779 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub;
780 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
781 
786 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv;
787 
792 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
793 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv;
794 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
795 
796 
797 /***********************************************/
798 /* Key types for brainpoolP224t1 */
799 /***********************************************/
800 
805 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub;
806 
811 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
812 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub;
813 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
814 
819 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv;
820 
825 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
826 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv;
827 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
828 
829 
830 /***********************************************/
831 /* Key types for brainpoolP256t1 */
832 /***********************************************/
833 
838 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub;
839 
844 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
845 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub;
846 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
847 
852 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv;
853 
858 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
859 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv;
860 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
861 
862 
863 /***********************************************/
864 /* Key types for brainpoolP320t1 */
865 /***********************************************/
866 
871 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub;
872 
877 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
878 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub;
879 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
880 
885 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv;
886 
891 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
892 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv;
893 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
894 
895 
896 /***********************************************/
897 /* Key types for brainpoolP384t1 */
898 /***********************************************/
899 
904 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub;
905 
910 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
911 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub;
912 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
913 
918 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv;
919 
924 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
925 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv;
926 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
927 
928 
929 /***********************************************/
930 /* Key types for brainpoolP512t1 */
931 /***********************************************/
932 
937 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub;
938 
943 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
944 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub;
945 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
946 
951 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv;
952 
957 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
958 static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv;
959 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
960 
961 
962 
963 /***********************************************/
964 /* Key types for Ed25519 */
965 /***********************************************/
966 
971 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv;
972 
977 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
978 static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv = &mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv;
979 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
980 
985 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub;
986 
991 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
992 static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub = &mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub;
993 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
994 
995 /***********************************************/
996 /* Key types for Ed448 */
997 /***********************************************/
998 
1003 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv;
1004 
1009 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
1010 static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv = &mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv;
1011 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
1012 
1017 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub;
1018 
1023 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
1024 static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub = &mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub;
1025 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
1026 
1027 
1028 /***********************************************/
1029 /* Key types for Curve25519 */
1030 /***********************************************/
1031 
1036 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair;
1037 
1042 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
1043 static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair = &mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair;
1044 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
1045 
1046 
1047 /***********************************************/
1048 /* Key types for Curve448 */
1049 /***********************************************/
1050 
1055 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair;
1056 
1061 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.")
1062 static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair = &mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair;
1063 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() /* mcuxClEcc_KeyTypeDescriptors */
1067 
1068 
1069 
1070 
1071 
1072 
1073 #ifdef __cplusplus
1074 } /* extern "C" */
1075 #endif
1076 
1077 #endif /* MCUXCLECC_KEYMECHANISMS_H_ */
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP160r1.
+
mcuxClKey_Type_WeierECC_secp256r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256r1.
Definition: mcuxClEcc_KeyMechanisms.h:251
+
mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair
Key type pointer for ECC MontDH Curve25519 Key pairs.
Definition: mcuxClEcc_KeyMechanisms.h:1043
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub
Key type structure for public ECC keys for Weierstrass curve NIST P-192.
Definition: mcuxClEcc_KeyMechanisms.h:343
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP256t1.
+
mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv
Key type structure for ECC EdDSA Ed448 private keys.
+
mcuxClKey_Type_WeierECC_secp160k1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp160k1.
Definition: mcuxClEcc_KeyMechanisms.h:53
+
mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP512t1.
Definition: mcuxClEcc_KeyMechanisms.h:958
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv
Key type structure for private ECC keys for Weierstrass curve NIST P-384.
Definition: mcuxClEcc_KeyMechanisms.h:456
+
mcuxClKey_Type_WeierECC_secp224r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224r1.
Definition: mcuxClEcc_KeyMechanisms.h:218
+
mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub
Key type structure for public ECC keys for Weierstrass curve secp256k1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP320t1.
+
mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384t1.
Definition: mcuxClEcc_KeyMechanisms.h:911
+
mcuxClKey_Type_WeierECC_NIST_P192_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv
Key type pointer for private ECC keys for Weierstrass curve NIST P-256.
Definition: mcuxClEcc_KeyMechanisms.h:364
+
mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv
Key type structure for private ECC keys for Weierstrass curve secp256k1.
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub
Key type structure for public ECC keys for Weierstrass curve NIST P-256.
Definition: mcuxClEcc_KeyMechanisms.h:409
+
mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP160t1.
Definition: mcuxClEcc_KeyMechanisms.h:760
+
mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
Key type structure for private ECC keys for Weierstrass curve secp521r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP256r1.
+
mcuxClKey_TypeDescriptor_t
struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
Key type descriptor type.
Definition: mcuxClKey_Types.h:104
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv
Key type structure for private ECC keys for Weierstrass curve NIST P-521.
Definition: mcuxClEcc_KeyMechanisms.h:489
+
mcuxClKey_Type_WeierECC_NIST_P521_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-521.
Definition: mcuxClEcc_KeyMechanisms.h:482
+
mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256t1.
Definition: mcuxClEcc_KeyMechanisms.h:845
+
mcuxClKey_Type_WeierECC_secp256k1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp256k1.
Definition: mcuxClEcc_KeyMechanisms.h:166
+
mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192r1.
Definition: mcuxClEcc_KeyMechanisms.h:548
+
mcuxClKey_Type_WeierECC_NIST_P256_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv
Key type pointer for private ECC keys for Weierstrass curve NIST P-256.
Definition: mcuxClEcc_KeyMechanisms.h:430
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub
Key type structure for public ECC keys for Weierstrass curve NIST P-224.
Definition: mcuxClEcc_KeyMechanisms.h:376
+
mcuxClKey_Type_WeierECC_secp192r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp192r1.
Definition: mcuxClEcc_KeyMechanisms.h:199
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP384r1.
+
mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP512r1.
Definition: mcuxClEcc_KeyMechanisms.h:727
+
mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub
Key type structure for ECC EdDSA Ed25519 public keys.
+
mcuxClKey_Type_WeierECC_secp160k1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp160k1.
Definition: mcuxClEcc_KeyMechanisms.h:67
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP384r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP512t1.
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub
Key type structure for public ECC keys for Weierstrass curve NIST P-384.
Definition: mcuxClEcc_KeyMechanisms.h:442
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP192r1.
+
mcuxClKey_Type_WeierECC_NIST_P384_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv
Key type pointer for private ECC keys for Weierstrass curve NIST P-384.
Definition: mcuxClEcc_KeyMechanisms.h:463
+
mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
Key type structure for public ECC keys for Weierstrass curve secp384r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP320t1.
+
mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
Key type structure for public ECC keys for Weierstrass curve secp256r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP224t1.
+
mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP256t1.
Definition: mcuxClEcc_KeyMechanisms.h:859
+
mcuxClKey_Type_WeierECC_secp384r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp384r1.
Definition: mcuxClEcc_KeyMechanisms.h:298
+
mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
Key type structure for private ECC keys for Weierstrass curve secp256r1.
+
mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP224r1.
Definition: mcuxClEcc_KeyMechanisms.h:595
+
mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP224t1.
Definition: mcuxClEcc_KeyMechanisms.h:826
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP384t1.
+
mcuxClKey_Type_WeierECC_secp224r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp224r1.
Definition: mcuxClEcc_KeyMechanisms.h:232
+
mcuxClKey_Type_WeierECC_secp521r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp521r1.
Definition: mcuxClEcc_KeyMechanisms.h:317
+
mcuxClEcc_Types.h
Type definitions of mcuxClEcc component.
+
mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub
Key type structure for public ECC keys for Weierstrass curve secp224k1.
+
mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub
Key type structure for public ECC keys for Weierstrass curve secp192k1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP160t1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP256r1.
+
mcuxClKey_Type_WeierECC_NIST_P256_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-256.
Definition: mcuxClEcc_KeyMechanisms.h:416
+
mcuxClKey_Type_WeierECC_secp192r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192r1.
Definition: mcuxClEcc_KeyMechanisms.h:185
+
mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv
Key type structure for private ECC keys for Weierstrass curve secp192k1.
+
mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv
Key type structure for private ECC keys for Weierstrass curve secp160k1.
+
mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP384t1.
Definition: mcuxClEcc_KeyMechanisms.h:925
+
mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub
Key type structure for public ECC keys for Weierstrass curve secp160k1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP192t1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP224t1.
+
mcuxClKey_Type_WeierECC_secp521r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp521r1.
Definition: mcuxClEcc_KeyMechanisms.h:331
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv
Key type structure for private ECC keys for Weierstrass curve NIST P-224.
Definition: mcuxClEcc_KeyMechanisms.h:390
+
mcuxClKey_Type_WeierECC_secp256r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp256r1.
Definition: mcuxClEcc_KeyMechanisms.h:265
+
mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
Key type structure for private ECC keys for Weierstrass curve secp224r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP384t1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP512r1.
+
mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512t1.
Definition: mcuxClEcc_KeyMechanisms.h:944
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP320r1.
+
mcuxClKey_Type_WeierECC_secp224k1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224k1.
Definition: mcuxClEcc_KeyMechanisms.h:119
+
mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair
Key type structure for ECC MontDH Curve448 Key pairs.
+
mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv
Key type structure for ECC EdDSA Ed25519 private keys.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP512t1.
+
mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192t1.
Definition: mcuxClEcc_KeyMechanisms.h:779
+
mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP192t1.
Definition: mcuxClEcc_KeyMechanisms.h:793
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP160t1.
+
mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub
Key type structure for ECC EdDSA Ed448 public keys.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP224r1.
+
mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224t1.
Definition: mcuxClEcc_KeyMechanisms.h:812
+
mcuxClKey_Type_WeierECC_secp192k1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp192k1.
Definition: mcuxClEcc_KeyMechanisms.h:100
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP512r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP320r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP224r1.
+
mcuxClKey_Type_WeierECC_secp224k1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv
Key type pointer for private ECC keys for Weierstrass curve secp224k1.
Definition: mcuxClEcc_KeyMechanisms.h:133
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub
Key type structure for public ECC keys for Weierstrass curve brainpoolP192t1.
+
mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
Key type structure for public ECC keys for Weierstrass curve secp224r1.
+
mcuxClKey_Type_WeierECC_secp384r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp384r1.
Definition: mcuxClEcc_KeyMechanisms.h:284
+
mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224r1.
Definition: mcuxClEcc_KeyMechanisms.h:581
+
mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv
Key type structure for private ECC keys for Weierstrass curve secp224k1.
+
mcuxClKey_Type_WeierECC_NIST_P384_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-384.
Definition: mcuxClEcc_KeyMechanisms.h:449
+
mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
Key type structure for public ECC keys for Weierstrass curve secp521r1.
+
mcuxClKey_Type_WeierECC_NIST_P224_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-224.
Definition: mcuxClEcc_KeyMechanisms.h:383
+
mcuxClKey_Type_WeierECC_secp256k1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256k1.
Definition: mcuxClEcc_KeyMechanisms.h:152
+
mcuxClKey_Type_EdDSA_Ed448_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub
Key type pointer for ECC EdDSA Ed448 public keys.
Definition: mcuxClEcc_KeyMechanisms.h:1024
+
mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256r1.
Definition: mcuxClEcc_KeyMechanisms.h:614
+
mcuxClKey_Type_EdDSA_Ed25519_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub
Key type pointer for ECC EdDSA Ed25519 public keys.
Definition: mcuxClEcc_KeyMechanisms.h:992
+
mcuxClKey_Type_EdDSA_Ed25519_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv
Key type pointer for ECC EdDSA Ed25519 private keys.
Definition: mcuxClEcc_KeyMechanisms.h:978
+
mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair
Key type pointer for ECC MontDH Curve448 Key pairs.
Definition: mcuxClEcc_KeyMechanisms.h:1062
+
mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP256r1.
Definition: mcuxClEcc_KeyMechanisms.h:628
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv
Key type structure for private ECC keys for Weierstrass curve NIST P-256.
Definition: mcuxClEcc_KeyMechanisms.h:423
+
mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP192r1.
Definition: mcuxClEcc_KeyMechanisms.h:562
+
mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
Key type structure for private ECC keys for Weierstrass curve secp192r1.
+
mcuxClKey_Type_WeierECC_NIST_P224_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv
Key type pointer for private ECC keys for Weierstrass curve NIST P-224.
Definition: mcuxClEcc_KeyMechanisms.h:397
+
mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320t1.
Definition: mcuxClEcc_KeyMechanisms.h:878
+
mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
Key type structure for public ECC keys for Weierstrass curve secp192r1.
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP256t1.
+
mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP384r1.
Definition: mcuxClEcc_KeyMechanisms.h:694
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub
Key type structure for public ECC keys for Weierstrass curve NIST P-521.
Definition: mcuxClEcc_KeyMechanisms.h:475
+
mcuxClKey_Type_EdDSA_Ed448_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv
Key type pointer for ECC EdDSA Ed448 private keys.
Definition: mcuxClEcc_KeyMechanisms.h:1010
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP192r1.
+
mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair
Key type structure for ECC MontDH Curve25519 Key pairs.
+
mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320r1.
Definition: mcuxClEcc_KeyMechanisms.h:647
+
mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
Key type structure for private ECC keys for Weierstrass curve secp384r1.
+
mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP320r1.
Definition: mcuxClEcc_KeyMechanisms.h:661
+
mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP320t1.
Definition: mcuxClEcc_KeyMechanisms.h:892
+
mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv
Key type structure for private ECC keys for Weierstrass curve brainpoolP160r1.
+
mcuxClKey_Type_WeierECC_NIST_P521_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv
Key type pointer for private ECC keys for Weierstrass curve NIST P-521.
Definition: mcuxClEcc_KeyMechanisms.h:496
+
mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160t1.
Definition: mcuxClEcc_KeyMechanisms.h:746
+
mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512r1.
Definition: mcuxClEcc_KeyMechanisms.h:713
+
mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv
Key type structure for private ECC keys for Weierstrass curve NIST P-192.
Definition: mcuxClEcc_KeyMechanisms.h:357
+
mcuxClKey_Type_WeierECC_secp192k1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192k1.
Definition: mcuxClEcc_KeyMechanisms.h:86
+
mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384r1.
Definition: mcuxClEcc_KeyMechanisms.h:680
+
mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv
Key type pointer for private ECC keys for Weierstrass curve brainpoolP160r1.
Definition: mcuxClEcc_KeyMechanisms.h:529
+
mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160r1.
Definition: mcuxClEcc_KeyMechanisms.h:515
+
mcuxClKey_Type_WeierECC_NIST_P192_Pub
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub
Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-192.
Definition: mcuxClEcc_KeyMechanisms.h:350
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00281.html b/components/els_pkc/doc/mcxn/html/a00281.html new file mode 100644 index 000000000..85be1b65e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00281.html @@ -0,0 +1,260 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClEcc_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClEcc component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_ALIGN_SIZE_CPU(byteLen)
 
#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN)
 CPU workarea size (in bytes) for mcuxClEcc_KeyGen. Parameter byteLenN is just to keep the API consistent. More...
 
#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN)
 CPU workarea size (in bytes) for mcuxClEcc_Sign. Parameter byteLenN is just to keep the API consistent. More...
 
#define MCUXCLECC_VERIFY_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Verify. More...
 
#define MCUXCLECC_POINTMULT_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_PointMult. More...
 
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams. More...
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration. More...
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed25519. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed25519. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448. More...
 
#define MCUXCLECC_PKC_WORDSIZE
 PKC wordsize in ECC component. More...
 
#define MCUXCLECC_MAX(value0, value1)
 Helper macro to get the maximum of two given constants. More...
 
#define MCUXCLECC_ALIGN_SIZE_PKC(size)
 Helper macro to calculate size aligned to PKC word. More...
 
#define MCUXCLECC_KEYGEN_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_KeyGen for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_SIGN_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_Sign for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_VERIFY_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_Verify for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_POINTMULT_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_PointMult for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams for arbitrary lengths of p and n. More...
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_128
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_256
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_384
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_512
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_640
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve25519. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve25519. More...
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve448. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve448. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448. More...
 
#define MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(byteLenP, byteLenN)
 Define for the buffer size (in bytes) for optimized custom ECC Weierstrass domain parameters. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE
 EdDSA key pair generation descriptor size. More...
 
#define MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE
 EdDSA signature generation descriptor size. More...
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00281.js b/components/els_pkc/doc/mcxn/html/a00281.js new file mode 100644 index 000000000..5386cb813 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00281.js @@ -0,0 +1,45 @@ +var a00281 = +[ + [ "MCUXCLECC_ALIGN_SIZE_CPU", "a00918.html#ga060c9729b406c2295fffad1f87a39a41", null ], + [ "MCUXCLECC_KEYGEN_WACPU_SIZE", "a00918.html#ga0fdfb866390f13e869a59e859da3866e", null ], + [ "MCUXCLECC_SIGN_WACPU_SIZE", "a00918.html#gabe6907845de629a54b0eae63da78d099", null ], + [ "MCUXCLECC_VERIFY_WACPU_SIZE", "a00918.html#ga77a772614cead92da188f20009bc24b5", null ], + [ "MCUXCLECC_POINTMULT_WACPU_SIZE", "a00918.html#ga46349810877e3b79a8d899648e1b2e06", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE", "a00918.html#ga29e85a389cf38d61196691fc4f3a35f1", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE", "a00919.html#ga89090994d784943f6c0ff6858600a5c8", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE", "a00919.html#gaf968453d3c749fe1e2a79b10877e8c9b", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE", "a00919.html#gaaf4bad03752e8903fc972548c27b40a3", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE", "a00919.html#ga8051604c81692c541171eb8693eb0ebe", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE", "a00920.html#ga647bd322f94b65acba45b872cacf5ba8", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE", "a00920.html#gad7ee128279d1230a6f0dee32093e4dc0", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE", "a00920.html#ga9ec654b676b4d3e3ccdda604ba55e5ed", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE", "a00920.html#ga86d2a91a15fd9c10989b363bcd9ab6af", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE", "a00920.html#gaf1baa23b5fa695897dade1e24bd60881", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE", "a00920.html#gaeb4fa934c84d576b93c321b436af5ccd", null ], + [ "MCUXCLECC_PKC_WORDSIZE", "a00921.html#ga636a89c09b2210ea78da464825e4bf99", null ], + [ "MCUXCLECC_MAX", "a00921.html#gaf74ecb9246e198a6078c55c48ddf479e", null ], + [ "MCUXCLECC_ALIGN_SIZE_PKC", "a00921.html#gac836b17e161566b045beb35f53828d1b", null ], + [ "MCUXCLECC_KEYGEN_WAPKC_SIZE", "a00921.html#ga7e26bba72c6eefd7f91907d0df33f17b", null ], + [ "MCUXCLECC_SIGN_WAPKC_SIZE", "a00921.html#ga3574ac0f7b7b9b6d17003263fc47c6c0", null ], + [ "MCUXCLECC_VERIFY_WAPKC_SIZE", "a00921.html#gab4cdcbfb78c215dbee9ff06dc2955034", null ], + [ "MCUXCLECC_POINTMULT_WAPKC_SIZE", "a00921.html#ga36cab670f924640163fc1b02bb753792", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE", "a00921.html#gad8881999c0f76cfb55a70d953fb979da", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_128", "a00921.html#ga69f2048dc8c0b4e7a171629db9625930", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_256", "a00921.html#gaac9a7761a7383add169e9ac24a0da0a3", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_384", "a00921.html#gadd45741f1d583af4e0fc7087d8eb84ad", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_512", "a00921.html#ga2de3745f78b2d6571bab0a6e4ebd0c2c", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_640", "a00921.html#ga7a35cbaaaf25c64dfbd72dd51c20b0b0", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE", "a00922.html#gae36dff0de90c37f30b946bf2788b8c50", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE", "a00922.html#gab8a50884589fb6a8e9c3a27176a98f17", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE", "a00922.html#ga10eb15479cf16f2bbe6834d0dce7480b", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE", "a00922.html#ga42aed746692f49fa0a4e27f5b3f5d743", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE", "a00923.html#ga6584fe2b7bc2e31a739cfb453fd2a9e6", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE", "a00923.html#ga4dd4582e5d6cdec3e4537a3447281348", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE", "a00923.html#ga0e082808f23a46021d65be49224fef54", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE", "a00923.html#gaca347a8466c7addee0aa63eb112fcb72", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE", "a00923.html#ga1a0b00eab2150578dc7afc98f8e82f2a", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE", "a00923.html#gad04926b8f100205fb4726200c825e1f6", null ], + [ "MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE", "a00683.html#gac8895d8165cf3c84b10ac986a30c37e4", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE", "a00924.html#ga435b584a2a74e53c5987727a938aa65d", null ], + [ "MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE", "a00925.html#ga045352e805adba9dfc25b087371872a6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00281_source.html b/components/els_pkc/doc/mcxn/html/a00281_source.html new file mode 100644 index 000000000..534c7d1c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00281_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLECC_MEMORYCONSUMPTION_H_
20 #define MCUXCLECC_MEMORYCONSUMPTION_H_
21 
22 
35 #define MCUXCLECC_ALIGN_SIZE_CPU(byteLen) ((((byteLen) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t))) * (sizeof(uint32_t)))
36 
37 #ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND
38 #define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) (416u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u))
39 #define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) (416u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u))
40 #else /* ! MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */
41 #define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) 416u
42 #define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) 416u
43 #endif /* MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */
44 
45 #define MCUXCLECC_VERIFY_WACPU_SIZE 424u
46 #define MCUXCLECC_POINTMULT_WACPU_SIZE 416u
47 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE 88u
48 
49  /* MCUXCLECC_WACPU_ */
53 
59 #define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE 444u
60 #define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE 468u
61 
62 #define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE 88u
63 #define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE 88u
64  /* MCUXCLECC_MONTDH_WACPU_ */
67 
73 #define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE 680u
74 #define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE 516u
75 
76 #define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE 540u
77 #define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE 132u
78 
79 #define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE 540u
80 #define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE 132u
81 
82  /* MCUXCLECC_EDDSA_WACPU_ */
85 
86 
96 #define MCUXCLECC_PKC_WORDSIZE 8u
97 
101 #define MCUXCLECC_MAX(value0, value1) (((value0) > (value1)) ? (value0) : (value1))
102 
106 #define MCUXCLECC_ALIGN_SIZE_PKC(size) ((((size) + MCUXCLECC_PKC_WORDSIZE - 1u) / MCUXCLECC_PKC_WORDSIZE) * MCUXCLECC_PKC_WORDSIZE)
107 
111 #define MCUXCLECC_KEYGEN_WAPKC_SIZE(pByteLen,nByteLen) \
112  (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE))
113 
114 
118 #define MCUXCLECC_SIGN_WAPKC_SIZE(pByteLen,nByteLen) \
119  (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE))
120 
121 
126 #define MCUXCLECC_VERIFY_WAPKC_SIZE(pByteLen,nByteLen) \
127  (28u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE))
128 
129 
133 #define MCUXCLECC_POINTMULT_WAPKC_SIZE(pByteLen,nByteLen) \
134  (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE))
135 
136 
140 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(pByteLen,nByteLen) \
141  (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE))
142 
143 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_128 (528u )
144 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_256 (880u )
145 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_384 (1232u )
146 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_512 (1584u )
147 #define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_640 (1936u )
148 
149 
150 
151  /* MCUXCLECC_WAPKC_ */
155 
156 
166 #define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE 880u
167 
171 #define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE 880u
172 
176 #define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE 1408u
177 
181 #define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE 1408u
182  /* MCUXCLECC_MONTDH_WAPKC_ */
186 
196 #define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE 1760u
197 #define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE 2816u
198 
199 
202 #define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE 1760u
203 #define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE 2816u
204 
205 
208 #define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE 1760u
209 #define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE 2816u
210 
211  /* MCUXCLECC_EDDSA_WAPKC_ */
214 
218 #define MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(byteLenP, byteLenN) \
219  MCUXCLECC_ALIGN_SIZE_CPU(76u \
220  + 8u * (byteLenP) \
221  + 2u * (byteLenN) )
222 
228 #define MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE 8u
229  /* MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_ */
232 
238 #define MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE 20u
239  /* MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_ */
242 
243 
244  /* mcuxClEcc_MemoryConsumption */
248 
249 #endif /* MCUXCLECC_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00284.html b/components/els_pkc/doc/mcxn/html/a00284.html new file mode 100644 index 000000000..dbbc07268 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00284.html @@ -0,0 +1,729 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_ParameterSizes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClEcc_ParameterSizes.h File Reference
+
+
+ +

Definitions of ECC domain parameter, key and signature sizes. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SIGNATURE
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_SIGNATURE
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP
 Byte length of the underlying prime p used in Ed25519. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER
 Byte length of the base point order n used in Ed25519. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY
 Byte length of an Ed25519 private key. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA
 Byte length of an Ed25519 private key handle data buffer. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY
 Byte length of an Ed25519 public key. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE
 Byte length of an Ed25519 signature. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen)
 Byte length of an Ed25519 prefix. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(contextLen)
 Byte length of an Ed25519 signature protocol descriptor. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP
 Byte length of the underlying prime p used in Ed448. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER
 Byte length of the base point order n used in Ed448. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY
 Byte length of an Ed448 private key. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA
 Byte length of an Ed448 private key handle data buffer. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY
 Byte length of an Ed448 public key. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE
 Byte length of an Ed448 signature. More...
 
+

Detailed Description

+

Definitions of ECC domain parameter, key and signature sizes.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00284.js b/components/els_pkc/doc/mcxn/html/a00284.js new file mode 100644 index 000000000..eef26ba3e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00284.js @@ -0,0 +1,201 @@ +var a00284 = +[ + [ "MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP", "a00926.html#ga3bca9028f9d698f1ed15c1a514b2e06c", null ], + [ "MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER", "a00926.html#ga1f47a7227582d04c228bb8b5d83b5ee9", null ], + [ "MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY", "a00926.html#ga512a7c862daef2ea238bb72ffd81fa7c", null ], + [ "MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY", "a00926.html#gac015167be9a74c6df948b30ee8b6e09f", null ], + [ "MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET", "a00926.html#ga0ef39e57a2f11b7f7f73110ca20c3197", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP", "a00927.html#gaf9580a49a92c6ed2918527e987f8c984", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER", "a00927.html#ga42c17dc5334d05f1aa6a482c32769f57", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY", "a00927.html#ga7c345468f9a5f6bd1fa9781bbe6ca377", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY", "a00927.html#ga1775c3331371392ead11c2add9cfdfd0", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET", "a00927.html#ga119c05b619b28cfd9b827c8fc3234d18", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP", "a00928.html#ga28e4bb7afa082b5aeec9b6081172b0b5", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER", "a00928.html#ga6e36bfa692483410753d3fc0df05c580", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY", "a00928.html#ga19af7820e42a44058173afac32a9c16d", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY", "a00928.html#gaa1614138c27ba75a1918f8d29076a578", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_SHAREDSECRET", "a00928.html#ga64043193d3a40ba543c7dc2c6c28660a", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_SIGNATURE", "a00928.html#gae207d4c272218473c543176c8cd3f2cb", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP", "a00929.html#ga402412a5c54ea3909218981dea204890", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER", "a00929.html#gadfabfd04272186731b11dd8f56aa4827", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY", "a00929.html#ga68f50564fa822462e325b477541685dc", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY", "a00929.html#gaa295fdca6bab37a60352516922dbb6fc", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_SHAREDSECRET", "a00929.html#ga0f5ae1ebd15a5b8bf3c9e6b4e69808e8", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_SIGNATURE", "a00929.html#ga657ddaf1d1ce192fa042762dfbedfb50", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP", "a00930.html#gabc8a3172a5339aa1b3d30591ee6360b3", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER", "a00930.html#ga350845dc45783342b504858c78ce2ef2", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY", "a00930.html#ga8ea8d0cf94b6bed41000240c3511f91f", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY", "a00930.html#gaad2e9937bcccb1604954d2e00675cbbb", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_SHAREDSECRET", "a00930.html#ga7db652e88413d25efaf80c5a072dcf9c", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_SIGNATURE", "a00930.html#gae743cd8b404f11ec1f075417501f1c3d", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP", "a00931.html#ga479adcdc74d2a161e130c6549e72fb40", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER", "a00931.html#ga79a08043fa20086731a99e55c29c9f4e", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY", "a00931.html#ga5435f0e07f059e414e04dc91f2498443", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY", "a00931.html#ga877e8a301a6c8925ad374f67cecb1731", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_SHAREDSECRET", "a00931.html#ga3f14dc34b760c7fe109a7f1a7449ff57", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_SIGNATURE", "a00931.html#ga80ad64fcc874eb428f99e6bc4ae848c6", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP", "a00932.html#gabb92392d31be1a0da2a7f3bbbb4aba13", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER", "a00932.html#ga4e1cf7bab303d3667e7af6f8954dca4d", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY", "a00932.html#ga36d1e7d4ec4d462354d00b88c8cf3582", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY", "a00932.html#ga34ce64a62c5e82acd2a86567451a07bb", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET", "a00932.html#ga970d8235bff47a48078cc55ad3b8c624", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE", "a00932.html#ga76b44dd6ef634152bc27d9ea724a352a", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP", "a00933.html#ga68c72ca50f7f6cb10c4c80ca7f4bcffe", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER", "a00933.html#ga044677f511b81107fbe707eaebf84b2c", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY", "a00933.html#ga89944dac2d2b8a709f64800dfb363c7f", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY", "a00933.html#ga93a441ca8983c98b8507e13f0de08319", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET", "a00933.html#gaa4f91c8a3c53c2ccb723a8937effa152", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE", "a00933.html#ga0654465d99b8468ec17fa6355a81445c", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP", "a00934.html#gaa7e45fc6ca8b57f4b7ae9568fea7053a", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER", "a00934.html#ga5f66c6fb66c0b99f896e6a86f007e2a4", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY", "a00934.html#ga402a1726d764c75ad2f7afaa068c0610", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY", "a00934.html#ga4fbe8c2df6a36805a0d496ee30fb1b84", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET", "a00934.html#ga32e70368eee58182b074aa946e608d28", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE", "a00934.html#ga56a2fe6f41b5cb217bea6bd420ab16bf", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP", "a00935.html#ga1c80e4ec32c4eccff6f18ca4899d8cb1", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER", "a00935.html#ga22063da285c3dd1772f04c42af03a012", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY", "a00935.html#ga7a175030f4f636023ed3f249802692c4", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY", "a00935.html#ga2f4300c15d8abc809033c1e109dc5637", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET", "a00935.html#ga26698857f8af46c61abe0133aa36438b", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE", "a00935.html#gae9a1d1a90bb82dab5080bfa763b9caf2", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP", "a00936.html#gad19952d6ecdfcdd29e2e2391f8e35b30", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER", "a00936.html#ga873ad34336cabcfdbaf80346de840efe", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY", "a00936.html#ga087c1fd0bdad7988fa0d83fb12ff0686", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY", "a00936.html#ga88e46b2a1b3abbbf5c1e9ecfc09a5bbb", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET", "a00936.html#gabb820fc7cb4df389e2556131097583af", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE", "a00936.html#gabfb1fd97b8ff000d6bb7a25ed142a03f", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIMEP", "a00937.html#ga6a1e5f15f31e2e5c1973f1b16815bf5a", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_BASEPOINTORDER", "a00937.html#gaf98fd2699492d41641811074d107efb2", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIVATEKEY", "a00937.html#ga73d7ccf303168577a0af45e50b0d7b54", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_PUBLICKEY", "a00937.html#ga28ae2e17531d7264a04374c47b22e30d", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_SHAREDSECRET", "a00937.html#ga81c60eb78dbbd4f67028dc8ac25992a4", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_SIGNATURE", "a00937.html#gac00f674b3c0c8216c0b047f5213b86f5", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIMEP", "a00938.html#gac2abdc8d40d2b2968842a835f723b596", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_BASEPOINTORDER", "a00938.html#gaadfea79bf9c9c425dc1a88e673713b75", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIVATEKEY", "a00938.html#gaf9dbc5aa798901b7ca03bba4ed10064a", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_PUBLICKEY", "a00938.html#ga791f2a50e6cc964a8f8bd2d9dcdf4e57", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_SHAREDSECRET", "a00938.html#gae08cef37c533c5da90d44f0a8080d380", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_SIGNATURE", "a00938.html#gaad47f7bd68a52f156dbb32affd434775", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIMEP", "a00939.html#ga858ea348c06fe856e79bda0d982b83e3", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_BASEPOINTORDER", "a00939.html#gaf1dcecf0e8005e7d2ce6150c936cc87a", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIVATEKEY", "a00939.html#ga61a295049d0ec8c67db7712c4ec03c7f", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY", "a00939.html#gae790b50fd58924cf38403197bfcfd913", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_SHAREDSECRET", "a00939.html#ga17d542ceeb453e5ea16375443c475cc2", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_SIGNATURE", "a00939.html#gabcc2b84fcc017b015f256a629d302065", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIMEP", "a00940.html#gac65ceecde99aa5db0a5770bc59512e35", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_BASEPOINTORDER", "a00940.html#ga22234e8606fa67ceabc49baabb352561", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIVATEKEY", "a00940.html#ga256fe4e3199e5c8ce20cf0684ff4b0c8", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_PUBLICKEY", "a00940.html#gafdfa971ab0ccac15ddc0b41bacfe79f7", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_SHAREDSECRET", "a00940.html#ga01abc3bafc96b45c398eac99e03fcca0", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_SIGNATURE", "a00940.html#ga1968b738479d39ee748cd6fa68b57b21", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIMEP", "a00941.html#ga480093eabf4d155ca413b74c19283232", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_BASEPOINTORDER", "a00941.html#ga9a22c8961e50ad75362e6a6623fef3aa", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIVATEKEY", "a00941.html#ga28a1b9618bfb3d3457dd594e5b1729f0", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_PUBLICKEY", "a00941.html#ga235a3ef333eb9befaffff160277d106b", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_SHAREDSECRET", "a00941.html#ga45a80ee215dca5187e30ed3ec06da650", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_SIGNATURE", "a00941.html#ga4c05eb063afd9d4f49d60b59d57f6247", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP", "a00942.html#ga29064d2948a7d12d938703e19ea6e8e2", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER", "a00942.html#ga60f1824ed6020a082a91a6885521508c", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY", "a00942.html#ga587b8cb032d81e7997a31116ee2e6ee6", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY", "a00942.html#gabde96388fd2aad0224cb991952c9ccb8", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SHAREDSECRET", "a00942.html#ga15b1327463a6054b9582c30dc5f91ce1", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SIGNATURE", "a00942.html#gaf95c3f37cbe1c7e66c57e39400f94590", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP", "a00943.html#ga8eea52017a08668a5bb707e17b185b80", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER", "a00943.html#ga97d9bc33fc60b060b682f7fc170efb93", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY", "a00943.html#gafdb5f18e4a93e4d41d0569a90fbe8ee2", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY", "a00943.html#ga9f8a7f077d42c2e745dc1a9a548e2a5f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SHAREDSECRET", "a00943.html#gae270f5ea105640cf6edbc055fc6b6d56", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SIGNATURE", "a00943.html#gadf4b398d18eb3ef6e935561ff14950ad", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP", "a00944.html#ga6fc6b225b896f7f3a4532d541360214e", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER", "a00944.html#gacafca680cb636c4a03b7703dde3d2e29", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY", "a00944.html#gadbba84943ad2ad6946e1cec42848961a", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY", "a00944.html#ga19b80e475cb295a73d8ebb1761ec3546", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SHAREDSECRET", "a00944.html#ga61961bf3720308b0c2ebd000398d6d0d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SIGNATURE", "a00944.html#ga5b818df653e85c8769dcc7af267c2158", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP", "a00945.html#ga8185b90c41b37c25830dba8d48c8762b", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER", "a00945.html#ga59996f5a8c7431e5449005358a65ca61", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY", "a00945.html#ga875aeb34b6dbe1c9e1e2c36d5a3329ac", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY", "a00945.html#ga9980496a153c2adf526d4ca4e33fb4d2", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SHAREDSECRET", "a00945.html#ga3ee900d646eb0ccb46436c8cba8ec81e", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SIGNATURE", "a00945.html#ga6bf8477ef868c13359ab8b54c7861d9f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP", "a00946.html#gafcc40268b5a4cb1d220acc2605232173", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER", "a00946.html#gaacfdb466238098bbcb47f27021d53881", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY", "a00946.html#ga5a5a09eb5da406c41254987894267be5", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY", "a00946.html#ga906ac373bea8684bea0f673afb57fbe3", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SHAREDSECRET", "a00946.html#ga343afcdd8ac82975174f4a951dbcbdef", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SIGNATURE", "a00946.html#ga71f45ca2b1cbf8a99f707adfbd16dc0c", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP", "a00947.html#gaa6fae1be34cb51f33af0699a2d76e149", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER", "a00947.html#ga57c7dbb0ce08c72cde1320abc438f134", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY", "a00947.html#ga23206411bdefde9e1ea63a9628d058ec", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY", "a00947.html#ga218818b77a0a3a82e78347aec40eefc7", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SHAREDSECRET", "a00947.html#gaf730516bd41728d9670df803df55d712", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SIGNATURE", "a00947.html#ga315230f65100ec17e9b289ec01560b0a", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP", "a00948.html#gac911b12f358a598368de8008565a7965", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER", "a00948.html#ga30420814ab3d68bdea47d2bb68cb9075", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY", "a00948.html#gab39ba3438dd2d92cb43717fe90142e98", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY", "a00948.html#ga5f3e79ac5e4188e45a4360b82766efac", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SHAREDSECRET", "a00948.html#ga3153d7c9178e4f6ee3b22c58272fe991", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SIGNATURE", "a00948.html#ga7f6870016e09396fc95cff113588e0d9", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP", "a00949.html#ga8e41ce1275f9099653655d5db355b2fc", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER", "a00949.html#ga86a04274ad793470f1ef95349645c2a9", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY", "a00949.html#gacd6353b6d01e1c07d1ab01221f1d6ea0", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY", "a00949.html#ga76ce85bf2b5967fc4606bc36ac0445d8", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SHAREDSECRET", "a00949.html#ga08d03f76f12766858a93c7f0333854bd", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SIGNATURE", "a00949.html#ga7fc74ebae337f2fbc6296bd7c2b9af84", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP", "a00950.html#ga2e93b7bf76e1af575045cd8bdaa65c1d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER", "a00950.html#gaabf0391797bcc7a209831507bc02f16d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY", "a00950.html#gafc766769815a56c9e199a12c8c2d34ac", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY", "a00950.html#ga8c3ecd312e39682fd890045ee937e743", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SHAREDSECRET", "a00950.html#ga133038807a4e1623866b3b2538b8aa44", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SIGNATURE", "a00950.html#ga08accb350e9d3d6deb131f88ece17c8f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP", "a00951.html#ga3bfe87ceb97334e081a5176fc71a5d81", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER", "a00951.html#ga80c4b2efb69d76af0af8f85b9fbc0b31", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY", "a00951.html#ga69a011c4cd6308c2f9024c097aef4714", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY", "a00951.html#ga01748d2eda57325ce2b9ef463416a54b", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SHAREDSECRET", "a00951.html#gae847e5f5a8516748b48544b7f1dc83e7", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SIGNATURE", "a00951.html#ga4488b9f539a27064b8dbefe1db019847", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP", "a00952.html#ga5bb8e51a52d641df6a2d4cfb5dbea41b", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER", "a00952.html#gacb973f68128e18f3d5c116694b175d18", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY", "a00952.html#gaf94e83f0a6d7951ea870e01e1b0adc6b", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY", "a00952.html#ga435c02a0a53c943524ee7eb1ba9e53d1", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SHAREDSECRET", "a00952.html#ga78d31fa57c3f2b48f1e5c27460a90ba9", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SIGNATURE", "a00952.html#ga749a51c1c738f1844a3a0c5250050335", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP", "a00953.html#gaebc46ddfd33f5866183f67232c0a819f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER", "a00953.html#gad2d1b81b83f4fe841796ffe569f5587d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY", "a00953.html#ga9cac03f68781406a94a4017dc82b38fb", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY", "a00953.html#ga435e53871ff7e723f6258b70b75a8c0f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SHAREDSECRET", "a00953.html#gaeb545ffd5944f000a98918e515bde802", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SIGNATURE", "a00953.html#gabad591ce0a76b70ee8966423652b9d9e", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP", "a00954.html#ga09fe1dc2e6c110146f84c0169726fb24", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER", "a00954.html#gaf1d60056cca6462da2c1a04c09b42c0c", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY", "a00954.html#gadb506ed797dd61ac13408393dd9f4c6d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY", "a00954.html#ga866e84f0f45d9205786ef5cd33b39243", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SHAREDSECRET", "a00954.html#gafdfaff86fce87aacc85e0acde1734dd3", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SIGNATURE", "a00954.html#gae745fa5b7559a675140e44b47d500f4f", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP", "a00955.html#gaf6dbfcea787862deada291d2dc1d8e1c", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER", "a00955.html#gad169fc8fca8df374ff4d13d7b3b572db", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY", "a00955.html#ga1f38851700c73f633eae946430ff303d", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY", "a00955.html#gaff406a4217a997b6c177b996b4482896", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SHAREDSECRET", "a00955.html#gad65cf192e18d2e42da7e85ce76f73878", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SIGNATURE", "a00955.html#ga5aebc9d13e27a5d8858eb37f04fbb61e", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP", "a00956.html#ga1133b6fe2138d934b9f0471476f0a7e6", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER", "a00956.html#gaca66ff9c186fea80c603a2d2069a9630", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_PRIVATEKEY", "a00956.html#gaf115516a57075c4e105c7b805a0cafac", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_PUBLICKEY", "a00956.html#ga0cd50a5cde6dc18b32f528c3f76441d9", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_SHAREDSECRET", "a00956.html#ga43125d3e1985a499ac11cdbe552c0a84", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE_SIGNATURE", "a00956.html#gaaabaa4d486311510289753e5b4ac30fa", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP", "a00957.html#gac14b636a63b6ad2a4ba8edb45d213aea", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER", "a00957.html#gab9dd06ce9086a33b19e20eba3aed8a7c", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY", "a00957.html#gab2c2539baf2994a0baae71d5d5c8f9fe", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA", "a00957.html#ga550f1830c8403002664123225e0f594f", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY", "a00957.html#gaf6cce889f1dc2b213479126d850af09c", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE", "a00957.html#gafd15d3ce72046f505d9763687d1614df", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX", "a00957.html#gae7f1a0f58d5d7690b379a651edda99ef", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR", "a00957.html#ga506d1f24af8a6f12335d65ddb6be97fb", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP", "a00958.html#ga574cb628611266d5182378f52676024b", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER", "a00958.html#ga2fff3270c5870bb95a69c8f283d91ee4", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY", "a00958.html#ga37d97fd46dcc20e7f93a5e06017ff967", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA", "a00958.html#gae310bda6e4756493489df624280503ef", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY", "a00958.html#ga51affb40be89a5c0b1eb0d17a135786c", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE", "a00958.html#gae3ae89f1d488c9444e0f8c3813b9753a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00284_source.html b/components/els_pkc/doc/mcxn/html/a00284_source.html new file mode 100644 index 000000000..33de3401a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00284_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_ParameterSizes.h Source File + + + + + + + + + + + + + + + + +
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+ +
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+ +
+ +
+
+
mcuxClEcc_ParameterSizes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLECC_PARAMETERSIZES_H_
21 #define MCUXCLECC_PARAMETERSIZES_H_
22 
23 #include <mcuxClConfig.h> // Exported features flags header
24 
38 #define MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP (32U)
39 #define MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER (32U)
40 #define MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY (MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER)
41 #define MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY (MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP)
42 #define MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET (MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP)
43  /* MCUXCLECC_MONT_CURVE25519_SIZE_ */
44 
49 #define MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP (56U)
50 #define MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER (56U)
51 #define MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY (MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER)
52 #define MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY (MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP)
53 #define MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET (MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP)
54  /* MCUXCLECC_MONT_CURVE448_SIZE_ */
55 
56 
61 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP (20U)
62 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER (21U)
63 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER)
64 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP)
65 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP)
66 #define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER)
67  /* MCUXCLECC_WEIERECC_SECP160K1_SIZE_ */
68 
73 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP (24U)
74 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER (24U)
75 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER)
76 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP)
77 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP)
78 #define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER)
79  /* MCUXCLECC_WEIERECC_SECP192K1_SIZE_ */
80 
85 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP (28U)
86 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER (29U)
87 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER)
88 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP)
89 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP)
90 #define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER)
91  /* MCUXCLECC_WEIERECC_SECP224K1_SIZE_ */
92 
97 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP (32U)
98 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER (32U)
99 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER)
100 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP)
101 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP)
102 #define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER)
103  /* MCUXCLECC_WEIERECC_SECP256K1_SIZE_ */
104 
109 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP (24U)
110 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER (24U)
111 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER)
112 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP)
113 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP)
114 #define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER)
115  /* MCUXCLECC_WEIERECC_SECP192R1_SIZE_ */
116 
121 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP (28U)
122 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER (28U)
123 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER)
124 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP)
125 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP)
126 #define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER)
127  /* MCUXCLECC_WEIERECC_SECP224R1_SIZE_ */
128 
133 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP (32U)
134 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER (32U)
135 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER)
136 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP)
137 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP)
138 #define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER)
139  /* MCUXCLECC_WEIERECC_SECP256R1_SIZE_ */
140 
145 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP (48U)
146 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER (48U)
147 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER)
148 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP)
149 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP)
150 #define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER)
151  /* MCUXCLECC_WEIERECC_SECP384R1_SIZE_ */
152 
157 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP (66U)
158 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER (66U)
159 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER)
160 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP)
161 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP)
162 #define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER)
163  /* MCUXCLECC_WEIERECC_SECP521R1_SIZE_ */
164 
169 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP)
170 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER)
171 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY)
172 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY)
173 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET)
174 #define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE)
175  /* MCUXCLECC_WEIERECC_NIST_P192_SIZE_ */
176 
181 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP)
182 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER)
183 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY)
184 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY)
185 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET)
186 #define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE)
187  /* MCUXCLECC_WEIERECC_NIST_P224_SIZE_ */
188 
193 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP)
194 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER)
195 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY)
196 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY)
197 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET)
198 #define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE)
199  /* MCUXCLECC_WEIERECC_NIST_P256_SIZE_ */
200 
205 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP)
206 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER)
207 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY)
208 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY)
209 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET)
210 #define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE)
211  /* MCUXCLECC_WEIERECC_NIST_P384_SIZE_ */
212 
217 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP)
218 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER)
219 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY)
220 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY)
221 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET)
222 #define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE)
223  /* MCUXCLECC_WEIERECC_NIST_P521_SIZE_ */
224 
229 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP (20U)
230 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER (20U)
231 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER)
232 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP)
233 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP)
234 #define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER)
235  /* MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_ */
236 
241 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP (24U)
242 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER (24U)
243 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER)
244 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP)
245 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP)
246 #define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER)
247  /* MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_ */
248 
253 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP (28U)
254 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER (28U)
255 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER)
256 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP)
257 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP)
258 #define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER)
259  /* MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_ */
260 
265 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP (32U)
266 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER (32U)
267 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER)
268 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP)
269 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP)
270 #define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER)
271  /* MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_ */
272 
277 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP (40U)
278 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER (40U)
279 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER)
280 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP)
281 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP)
282 #define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER)
283  /* MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_ */
284 
289 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP (48U)
290 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER (48U)
291 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER)
292 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP)
293 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP)
294 #define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER)
295  /* MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_ */
296 
301 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP (64U)
302 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER (64U)
303 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER)
304 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP)
305 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP)
306 #define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER)
307  /* MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_ */
308 
313 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP (20U)
314 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER (20U)
315 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER)
316 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP)
317 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP)
318 #define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER)
319  /* MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_ */
320 
325 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP (24U)
326 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER (24U)
327 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER)
328 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP)
329 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP)
330 #define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER)
331  /* MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_ */
332 
337 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP (28U)
338 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER (28U)
339 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER)
340 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP)
341 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP)
342 #define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER)
343  /* MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_ */
344 
349 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP (32U)
350 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER (32U)
351 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER)
352 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP)
353 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP)
354 #define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER)
355  /* MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_ */
356 
361 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP (40U)
362 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER (40U)
363 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER)
364 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP)
365 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP)
366 #define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER)
367  /* MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_ */
368 
373 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP (48U)
374 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER (48U)
375 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER)
376 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP)
377 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP)
378 #define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER)
379  /* MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_ */
380 
385 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP (64U)
386 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER (64U)
387 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER)
388 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP)
389 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP)
390 #define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER)
391  /* MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_ */
392 
396 #define MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP (80U)
397 #define MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER (80U)
398 #define MCUXCLECC_WEIERECC_MAX_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER)
399 #define MCUXCLECC_WEIERECC_MAX_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP)
400 #define MCUXCLECC_WEIERECC_MAX_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP)
401 #define MCUXCLECC_WEIERECC_MAX_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER)
402  /* MCUXCLECC_WEIERECC_MAX_SIZE */
403 
407 #define MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP (32u)
408 #define MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER (32u)
409 #define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY (32u)
410 #define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA (96u)
411 #define MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY (32u)
412 #define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE (64u)
413 #define MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen) (34u + (contextLen))
414 #define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(contextLen) \
415  (MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE + MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen))
416 
417  /* MCUXCLECC_EDDSA_ED25519_SIZE_ */
418 
422 #define MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP (56u)
423 #define MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER (56u)
424 #define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY (57u)
425 #define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA (171u)
426 #define MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY (57u)
427 #define MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE (114u)
428  /* MCUXCLECC_EDDSA_ED448_SIZE_ */
429  /* mcuxClEcc_ParameterSizes */
432 
433 #endif /* MCUXCLECC_PARAMETERSIZES_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00287.html b/components/els_pkc/doc/mcxn/html/a00287.html new file mode 100644 index 000000000..2a1968f0d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00287.html @@ -0,0 +1,250 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Variables
+
+
mcuxClEcc_Types.h File Reference
+
+
+ +

Type definitions of mcuxClEcc component. +More...

+
#include <stdint.h>
+#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClEcc_ParameterSizes.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Data Structures

struct  mcuxClEcc_DomainParam_t
 Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p. More...
 
struct  mcuxClEcc_KeyGen_Param_t
 Parameter structure for function mcuxClEcc_KeyGen. More...
 
struct  mcuxClEcc_Sign_Param_t
 Parameter structure for function mcuxClEcc_Sign. More...
 
struct  mcuxClEcc_Verify_Param_t
 Parameter structure for function mcuxClEcc_Verify. More...
 
struct  mcuxClEcc_PointMult_Param_t
 Parameter structure for function mcuxClEcc_PointMult. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_STATUS_OK
 Operation was successful. More...
 
#define MCUXCLECC_STATUS_INVALID_PARAMS
 Parameters are invalid. More...
 
#define MCUXCLECC_STATUS_RNG_ERROR
 Random number (DRBG / PRNG) error (unexpected behavior). More...
 
#define MCUXCLECC_STATUS_INVALID_SIGNATURE
 ECDSA Signature is invalid. More...
 
#define MCUXCLECC_STATUS_NEUTRAL_POINT
 The result of the point operation is the neutral point. More...
 
#define MCUXCLECC_STATUS_FAULT_ATTACK
 Fault attack (unexpected behavior) is detected. More...
 
#define MCUXCLECC_STATUS_NOT_SUPPORTED
 Functionality is not supported. More...
 
#define MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP
 MONTDH public key lies in small subgroup. More...
 
#define mcuxClEcc_DomainParam_misc_Pack(byteLenN, byteLenP)
 mcuxClEcc macros and defines to pack or access components of misc parameter of mcuxClEcc_DomainParam_t More...
 
#define mcuxClEcc_DomainParam_misc_byteLenP_offset
 Offset of byteLenP in packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenP_mask
 Mask to extract byteLenP from packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenN_offset
 Offset of byteLenN in packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenN_mask
 Mask to extract byteLenN from packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_Sign_Param_optLen_Pack(byteLenHash)
 mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Sign_Param_t More...
 
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_offset
 Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Sign_Param_t. More...
 
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_mask
 Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Sign_Param_t. More...
 
#define mcuxClEcc_Verify_Param_optLen_Pack(byteLenHash)
 mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Verify_Param_t More...
 
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_offset
 Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Verify_Param_t. More...
 
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_mask
 Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Verify_Param_t. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClEcc_Status_t
 Type for mcuxClEcc component return codes. More...
 
typedef mcuxClEcc_Status_t mcuxClEcc_Status_Protected_t
 Deprecated type for mcuxClEcc component return codes. More...
 
typedef struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t
 Type for MontDH domain parameters. More...
 
typedef struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
 Type for EdDSA domain parameters. More...
 
typedef struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
 EdDSA GenerateKeyPair variant descriptor type. More...
 
typedef struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
 EdDSA SignatureProtocol variant descriptor type. More...
 
typedef struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
 Type for Weierstrass ECC domain parameters. More...
 
+ + + + + + +

+Variables

+const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor
 
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor
 Ed25519 signature protocol descriptor. More...
 
+

Detailed Description

+

Type definitions of mcuxClEcc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00287.js b/components/els_pkc/doc/mcxn/html/a00287.js new file mode 100644 index 000000000..aa4ee1ce0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00287.js @@ -0,0 +1,31 @@ +var a00287 = +[ + [ "MCUXCLECC_STATUS_OK", "a00959.html#gafed6866e44c300e1946713be81aefb9c", null ], + [ "MCUXCLECC_STATUS_INVALID_PARAMS", "a00959.html#ga7eec856d4a1438ff6e603ee42aaa9aae", null ], + [ "MCUXCLECC_STATUS_RNG_ERROR", "a00959.html#ga80ff10536e9cd063f733449d74b1c878", null ], + [ "MCUXCLECC_STATUS_INVALID_SIGNATURE", "a00959.html#gae739e1f3f62d1a66e2a862e40d5a0f37", null ], + [ "MCUXCLECC_STATUS_NEUTRAL_POINT", "a00959.html#gaad0d3ea3572cc175fe1608bca3ddac35", null ], + [ "MCUXCLECC_STATUS_FAULT_ATTACK", "a00959.html#ga9d53aaec17a413449e5cb6b73702c2c3", null ], + [ "MCUXCLECC_STATUS_NOT_SUPPORTED", "a00959.html#ga7f2a86f80fcda4760372af6cdbc11c1b", null ], + [ "MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP", "a00960.html#gaf70d3732e96746a174562deb076669f6", null ], + [ "mcuxClEcc_DomainParam_misc_Pack", "a00686.html#ga811c5fef9abbdfc1548b007e0d31c69f", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenP_offset", "a00686.html#ga62009de56f8d1fbbd2024072229a75fa", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenP_mask", "a00686.html#ga6b450065c08ab2e1adf93c1015c2fe87", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenN_offset", "a00686.html#ga2470875307a9264ff6e12046fd4a57eb", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenN_mask", "a00686.html#ga26e4695e9a47f6a7c7d36af8e8432fa0", null ], + [ "mcuxClEcc_Sign_Param_optLen_Pack", "a00686.html#ga05dbf2e2404af42bb6aaca0d0eaada8f", null ], + [ "mcuxClEcc_Sign_Param_optLen_byteLenHash_offset", "a00686.html#ga25bfc46880eb604440c1facc7e55fc3d", null ], + [ "mcuxClEcc_Sign_Param_optLen_byteLenHash_mask", "a00686.html#ga4a74c55c76d977b39d1b387b75bbeebb", null ], + [ "mcuxClEcc_Verify_Param_optLen_Pack", "a00686.html#ga329b8cd689c64177a46e68b4f3a6a158", null ], + [ "mcuxClEcc_Verify_Param_optLen_byteLenHash_offset", "a00686.html#ga9e4f2aa470eda485d1ca012222e37070", null ], + [ "mcuxClEcc_Verify_Param_optLen_byteLenHash_mask", "a00686.html#gafeb4e3230717ac80d469d421918a8607", null ], + [ "mcuxClEcc_Status_t", "a00685.html#gaf044f4a5eeeecc4ec5b01aed19f2fe41", null ], + [ "mcuxClEcc_Status_Protected_t", "a00685.html#ga3900d9bdb95a061d26b71f300318b6a1", null ], + [ "mcuxClEcc_MontDH_DomainParams_t", "a00686.html#ga52205a42d2027ba1c3ec49589f9f0b8c", null ], + [ "mcuxClEcc_EdDSA_DomainParams_t", "a00686.html#ga365359e63f156889e46845381455b321", null ], + [ "mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t", "a00686.html#gadee46209e43c63814a86e882b3927b27", null ], + [ "mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t", "a00686.html#gaec003d78ecf36673f595fcc87f11b82c", null ], + [ "mcuxClEcc_Weier_DomainParams_t", "a00686.html#gafe84edad82c8934ef1634e9f29effa55", null ], + [ "mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor", "a00687.html#ga86ce358d9af15d943c4a254ac4156363", null ], + [ "mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor", "a00687.html#ga41770640b3d964f8add4ad005c6d81e6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00287_source.html b/components/els_pkc/doc/mcxn/html/a00287_source.html new file mode 100644 index 000000000..7efd43859 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00287_source.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLECC_TYPES_H_
21 #define MCUXCLECC_TYPES_H_
22 
23 
24 #include <stdint.h>
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxCsslFlowProtection.h>
27 #include <mcuxClEcc_ParameterSizes.h>
28 #include <mcuxCsslAnalysis.h>
29 
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /**********************************************************/
36 /* Return codes of mcuxClEcc */
37 /**********************************************************/
48 typedef uint32_t mcuxClEcc_Status_t;
49 
53 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Status_Protected_t;
54 
55 
60 #define MCUXCLECC_STATUS_OK ((mcuxClEcc_Status_t) 0x04442E03u)
61 #define MCUXCLECC_STATUS_INVALID_PARAMS ((mcuxClEcc_Status_t) 0x044453F8u)
62 #define MCUXCLECC_STATUS_RNG_ERROR ((mcuxClEcc_Status_t) 0x04445334u)
63 #define MCUXCLECC_STATUS_INVALID_SIGNATURE ((mcuxClEcc_Status_t) 0x04448930u)
64 #define MCUXCLECC_STATUS_NEUTRAL_POINT ((mcuxClEcc_Status_t) 0x04448934u)
65 #define MCUXCLECC_STATUS_FAULT_ATTACK ((mcuxClEcc_Status_t) 0x0444F0F0u)
66 #define MCUXCLECC_STATUS_NOT_SUPPORTED ((mcuxClEcc_Status_t) 0x04445370u)
67 
73 #define MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP ((mcuxClEcc_Status_t) 0x04445374u)
74  /* MCUXCLECC_MONTDH_STATUS_ */
75  /* mcuxClEcc_Macros */
78 
79 
80 /**********************************************************/
81 /* Parameter structure of mcuxClEcc APIs */
82 /**********************************************************/
92 typedef struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t;
93 
94 
96 typedef struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t;
97 
101 struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor;
102 
106 typedef struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t;
107 
111 struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor;
112 
116 typedef struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t;
117 
118 
120 typedef struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t;
121 
127 typedef struct
128 {
129  const uint8_t *pA;
130  const uint8_t *pB;
131  const uint8_t *pP;
132  const uint8_t *pG;
134  const uint8_t *pN;
136  uint32_t misc;
138 } mcuxClEcc_DomainParam_t;
142 
144 #define mcuxClEcc_DomainParam_misc_Pack(byteLenN, byteLenP) MCUXCLPKC_PACKARGS4(0u, 0u, (uint8_t) byteLenN, (uint8_t) byteLenP)
145 #define mcuxClEcc_DomainParam_misc_byteLenP_offset 0
146 #define mcuxClEcc_DomainParam_misc_byteLenP_mask ((uint32_t) 0x000000FFu)
147 #define mcuxClEcc_DomainParam_misc_byteLenN_offset 8
148 #define mcuxClEcc_DomainParam_misc_byteLenN_mask ((uint32_t) 0x0000FF00u)
149 
150 
152 typedef struct
153 {
154  mcuxClEcc_DomainParam_t curveParam;
155  uint8_t * pPrivateKey;
156  uint8_t * pPublicKey;
158  uint32_t optLen;
160 } mcuxClEcc_KeyGen_Param_t;
162 
164 typedef struct
165 {
166  mcuxClEcc_DomainParam_t curveParam;
167  const uint8_t * pHash;
168  const uint8_t * pPrivateKey;
169  uint8_t * pSignature;
170  uint32_t optLen;
173 } mcuxClEcc_Sign_Param_t;
176 
178 #define mcuxClEcc_Sign_Param_optLen_Pack(byteLenHash) ((uint32_t) (byteLenHash) & 0xFFu)
179 #define mcuxClEcc_Sign_Param_optLen_byteLenHash_offset 0
180 #define mcuxClEcc_Sign_Param_optLen_byteLenHash_mask ((uint32_t) 0x000000FFu)
181 
182 
183 typedef struct
184 {
185  mcuxClEcc_DomainParam_t curveParam;
186  const uint8_t * pPrecG;
187  const uint8_t * pHash;
189  const uint8_t * pSignature;
190  const uint8_t * pPublicKey;
192  uint8_t * pOutputR;
193  uint32_t optLen;
195 } mcuxClEcc_Verify_Param_t;
198 
200 #define mcuxClEcc_Verify_Param_optLen_Pack(byteLenHash) ((uint32_t) (byteLenHash) & 0xFFu)
201 #define mcuxClEcc_Verify_Param_optLen_byteLenHash_offset 0
202 #define mcuxClEcc_Verify_Param_optLen_byteLenHash_mask ((uint32_t) 0x000000FFu)
203 
204 
205 typedef struct
206 {
207  mcuxClEcc_DomainParam_t curveParam;
208  const uint8_t * pScalar;
209  const uint8_t * pPoint;
210  uint8_t * pResult;
211  uint32_t optLen;
213 } mcuxClEcc_PointMult_Param_t; /* mcuxClEcc_Types */
218 
219 /**********************************************************/
220 /* Descriptors of mcuxClEcc APIs */
221 /**********************************************************/
229 /**********************************************************/
230 /* Key pair generation descriptors */
231 /**********************************************************/
232 
233 /* EdDSA key pair generation descriptor to be used when the private key shall be generated by the
234  * EdDSA key pair generation function */
235 extern const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor;
236 
237 
238 /**********************************************************/
239 /* Signature ProtocolDescriptors and ModeDescriptors */
240 /**********************************************************/
241 
251 extern const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor;
252 
253 
254 
255  /* mcuxClEcc_Descriptors */
259 
260 #ifdef __cplusplus
261 } /* extern "C" */
262 #endif
263 
264 #endif /* MCUXCLECC_TYPES_H_ */
mcuxClEcc_Status_Protected_t
mcuxClEcc_Status_t mcuxClEcc_Status_Protected_t
Deprecated type for mcuxClEcc component return codes.
Definition: mcuxClEcc_Types.h:53
+
mcuxClEcc_DomainParam_t::pB
const uint8_t * pB
[in] pointer to octet string of curve parameter b (< p), of which the length is byteLenP.
Definition: mcuxClEcc_Types.h:130
+
mcuxClEcc_Verify_Param_t::pOutputR
uint8_t * pOutputR
[out] pointer to memory area in which signature R calculated by verify function will be exported if s...
Definition: mcuxClEcc_Types.h:192
+
mcuxClEcc_PointMult_Param_t::pPoint
const uint8_t * pPoint
[in] pointer to octet string of EC point Q, which is of the same format as base point G.
Definition: mcuxClEcc_Types.h:209
+
mcuxClEcc_PointMult_Param_t::pResult
uint8_t * pResult
[out] pointer to memory area, where the result R = dQ will be exported if PointMult is executed succe...
Definition: mcuxClEcc_Types.h:210
+
mcuxClEcc_ParameterSizes.h
Definitions of ECC domain parameter, key and signature sizes.
+
mcuxClEcc_Verify_Param_t::pPrecG
const uint8_t * pPrecG
[in] pointer to octet string of pre-computed point of base point G, which is of the same format as ba...
Definition: mcuxClEcc_Types.h:186
+
mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
EdDSA GenerateKeyPair variant descriptor type.
Definition: mcuxClEcc_Types.h:106
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClEcc_Verify_Param_t::pSignature
const uint8_t * pSignature
[in] pointer to octet string of signature R and S.
Definition: mcuxClEcc_Types.h:189
+
mcuxClEcc_DomainParam_t::pA
const uint8_t * pA
[in] pointer to octet string of curve parameter a (< p), of which the length is byteLenP.
Definition: mcuxClEcc_Types.h:129
+
mcuxClEcc_DomainParam_t::pP
const uint8_t * pP
[in] pointer to octet string of prime modulus p, of which the length is byteLenP.
Definition: mcuxClEcc_Types.h:131
+
mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor
Ed25519 signature protocol descriptor.
+
mcuxClEcc_Sign_Param_t
Parameter structure for function mcuxClEcc_Sign.
Definition: mcuxClEcc_Types.h:164
+
mcuxClEcc_EdDSA_DomainParams_t
struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
Type for EdDSA domain parameters.
Definition: mcuxClEcc_Types.h:96
+
mcuxClEcc_Sign_Param_t::pSignature
uint8_t * pSignature
[out] pointer to memory area in which signature R and S will be exported if signature is generated su...
Definition: mcuxClEcc_Types.h:169
+
mcuxClEcc_PointMult_Param_t::pScalar
const uint8_t * pScalar
[in] pointer to octet string of scalar d, which is of the same format as base point order n.
Definition: mcuxClEcc_Types.h:208
+
mcuxClEcc_KeyGen_Param_t::pPrivateKey
uint8_t * pPrivateKey
[out] pointer to memory area, where the private key will be exported if KeyGen is executed successful...
Definition: mcuxClEcc_Types.h:155
+
mcuxClEcc_KeyGen_Param_t::curveParam
mcuxClEcc_DomainParam_t curveParam
[in] structure of pointers to curve parameters and length of parameters.
Definition: mcuxClEcc_Types.h:154
+
mcuxClEcc_Sign_Param_t::pPrivateKey
const uint8_t * pPrivateKey
[in] pointer to octet string of private key, which is of the same format as base point order n.
Definition: mcuxClEcc_Types.h:168
+
mcuxClEcc_Sign_Param_t::curveParam
mcuxClEcc_DomainParam_t curveParam
[in] structure of pointers to curve parameters and length of parameters.
Definition: mcuxClEcc_Types.h:166
+
mcuxClEcc_PointMult_Param_t::curveParam
mcuxClEcc_DomainParam_t curveParam
[in] structure of pointers to curve parameters and length of parameters.
Definition: mcuxClEcc_Types.h:207
+
mcuxClEcc_PointMult_Param_t
Parameter structure for function mcuxClEcc_PointMult.
Definition: mcuxClEcc_Types.h:205
+
mcuxClEcc_KeyGen_Param_t
Parameter structure for function mcuxClEcc_KeyGen.
Definition: mcuxClEcc_Types.h:152
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEcc_Sign_Param_t::pHash
const uint8_t * pHash
[in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen).
Definition: mcuxClEcc_Types.h:167
+
mcuxClEcc_Weier_DomainParams_t
struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
Type for Weierstrass ECC domain parameters.
Definition: mcuxClEcc_Types.h:120
+
mcuxClEcc_Status_t
uint32_t mcuxClEcc_Status_t
Type for mcuxClEcc component return codes.
Definition: mcuxClEcc_Types.h:48
+
mcuxClEcc_Verify_Param_t::curveParam
mcuxClEcc_DomainParam_t curveParam
[in] structure of pointers to curve parameters and length of parameters.
Definition: mcuxClEcc_Types.h:185
+
mcuxClEcc_Verify_Param_t
Parameter structure for function mcuxClEcc_Verify.
Definition: mcuxClEcc_Types.h:183
+
mcuxClEcc_MontDH_DomainParams_t
struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t
Type for MontDH domain parameters.
Definition: mcuxClEcc_Types.h:92
+
mcuxClEcc_DomainParam_t
Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p.
Definition: mcuxClEcc_Types.h:127
+
mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
EdDSA SignatureProtocol variant descriptor type.
Definition: mcuxClEcc_Types.h:116
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00290.html b/components/els_pkc/doc/mcxn/html/a00290.html new file mode 100644 index 000000000..8c8ddef5d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00290.html @@ -0,0 +1,311 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_WeierECC.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEcc_WeierECC.h File Reference
+
+
+ +

header of mcuxClEcc functionalities related to ECC protocols based on (short) Weierstrass curves +More...

+
#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClSession.h>
+#include <mcuxClKey.h>
+#include <mcuxClEcc_Types.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClEcc_Weier_BasicDomainParams_t
 Structure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1. More...
 
+ + + + + + + + + +

+Macros

+#define MCUXCLECC_OPTION_GENERATEPRECPOINT_YES
 
+#define MCUXCLECC_OPTION_GENERATEPRECPOINT_NO
 
+#define MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK
 
+#define MCUXCLECC_OPTION_GENERATEPRECPOINT_OFFSET
 
+ + + + + + + +

+Functions

mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateDomainParams (mcuxClSession_Handle_t pSession, mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams, mcuxClEcc_Weier_BasicDomainParams_t *pEccWeierBasicDomainParams, uint32_t options)
 ECC Weierstrass custom domain parameter generation function. More...
 
mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateCustomKeyType (mcuxClKey_CustomType_t customType, mcuxClKey_AlgorithmId_t algoId, mcuxClKey_Size_t size, void *pCustomParams)
 Key type constructor. More...
 
+

Detailed Description

+

header of mcuxClEcc functionalities related to ECC protocols based on (short) Weierstrass curves

+

Function Documentation

+ +

◆ mcuxClEcc_WeierECC_GenerateDomainParams()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateDomainParams (mcuxClSession_Handle_t pSession,
mcuxClEcc_Weier_DomainParams_t * pEccWeierDomainParams,
mcuxClEcc_Weier_BasicDomainParams_t * pEccWeierBasicDomainParams,
uint32_t options 
)
+
+ +

ECC Weierstrass custom domain parameter generation function.

+

Given pointers and lengths specifying domain parameters of a custom (short) Weierstrass curve with cofactor 1, this function generates a corresponding optimized custom domain parameter struct.

+
Parameters
+ + + + + +
pSessionHandle for the current CL session.
[out]pEccWeierDomainParamsPointer to memory area in which the optimized domain parameters shall be stored.
[in]pEccWeierBasicDomainParamsPointer to struct containing pointers and lengths specifying the custom domain parameters.
[in]optionsParameter specifying whether or not the pre-computed point (2 ^ (byteLenN * 4)) * G corresponding to the base point G shall be calculated or not, If set to
    +
  • MCUXCLECC_OPTION_GENERATEPRECPOINT_YES, the pre-computed point will be calculated
    • +
  • MCUXCLECC_OPTION_GENERATEPRECPOINT_NO, the pre-computed point will not be calculated
    • +
+
+
+
+
Attention
the generated optimized domain parameter cannot be copied or moved, but shall be used in the original memory address where it is generated.
+
Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
+
Return values
+ + + + +
MCUXCLECC_STATUS_OKif optimized domain parameters are generated successfully;
MCUXCLECC_STATUS_INVALID_PARAMSif parameters are invalid;
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
+
+
+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ mcuxClEcc_WeierECC_GenerateCustomKeyType()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateCustomKeyType (mcuxClKey_CustomType_t customType,
mcuxClKey_AlgorithmId_t algoId,
mcuxClKey_Size_t size,
void * pCustomParams 
)
+
+ +

Key type constructor.

+

This function allows to generate custom key types according to the passed algoId.

+
Parameters
+ + + + + +
[out]customTypeHandle for the custom key type.
[in]algoIdAlgorithm identifier specifying the key type descriptor to be generated. The supported algoIds are
    +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_KEY_PAIR
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_KEY_PAIR All other values will trigger an error.
    • +
+
[in]sizeAlgorithm based key size.
[in]pCustomParamsPointer to algorithm based custom parameters. If algoId & MCUXCLKEY_ALGO_ID_ALGO_MASK equals
    +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM, a pointer to an mcuxClEcc_Weier_BasicDomainParams_t struct specifying custom ECC Weierstrass domain parameters
    • +
  • MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM, a pointer to an mcuxClEcc_Weier_DomainParams_t struct specifying optimized custom ECC Weierstrass domain parameters In all other cases, the pointer shall be set to NULL
    • +
+
+
+
+
Returns
status
+
Return values
+ + + + +
MCUXCLECC_STATUS_OKif custom key type is generated successfully;
MCUXCLECC_STATUS_INVALID_PARAMSif Parameters are invalid.
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
+
+
+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00290.js b/components/els_pkc/doc/mcxn/html/a00290.js new file mode 100644 index 000000000..2de28bee1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00290.js @@ -0,0 +1,10 @@ +var a00290 = +[ + [ "mcuxClEcc_Weier_BasicDomainParams_t", "a00993.html", "a00993" ], + [ "MCUXCLECC_OPTION_GENERATEPRECPOINT_YES", "a00290.html#a4e9b583c3b1411f1e637077f94830923", null ], + [ "MCUXCLECC_OPTION_GENERATEPRECPOINT_NO", "a00290.html#ab9477bfbda79aa92959c0d5d932a90b7", null ], + [ "MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK", "a00290.html#a7ad5ff52b9bccfda2081787268a5bf12", null ], + [ "MCUXCLECC_OPTION_GENERATEPRECPOINT_OFFSET", "a00290.html#a96a9c5f434cfc48c4abece918f779b0b", null ], + [ "mcuxClEcc_WeierECC_GenerateDomainParams", "a00290.html#a1deb22c96b88674a4513e56cdd2dfe3a", null ], + [ "mcuxClEcc_WeierECC_GenerateCustomKeyType", "a00290.html#abd1f9ebda4a913d82eefe752ca54923b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00290_source.html b/components/els_pkc/doc/mcxn/html/a00290_source.html new file mode 100644 index 000000000..4d5a63303 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00290_source.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_WeierECC.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_WeierECC.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLECC_WEIERECC_H_
21 #define MCUXCLECC_WEIERECC_H_
22 
23 
24 #include <mcuxClCore_FunctionIdentifiers.h>
25 #include <mcuxClSession.h>
26 #include <mcuxClKey.h>
27 #include <mcuxClEcc_Types.h>
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
36 typedef struct {
37  const uint8_t *pP;
38  uint32_t pLen;
39  const uint8_t *pA;
40  const uint8_t *pB;
41  const uint8_t *pG;
42  const uint8_t *pN;
43  uint32_t nLen;
44 } mcuxClEcc_Weier_BasicDomainParams_t;
45 
46 
69 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_GenerateDomainParams)
70 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateDomainParams(
71  mcuxClSession_Handle_t pSession,
72  mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams,
73  mcuxClEcc_Weier_BasicDomainParams_t *pEccWeierBasicDomainParams,
74  uint32_t options
75  );
76 
77 #define MCUXCLECC_OPTION_GENERATEPRECPOINT_YES (0x00000001u)
78 #define MCUXCLECC_OPTION_GENERATEPRECPOINT_NO (0x00000002u)
79 #define MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK (MCUXCLECC_OPTION_GENERATEPRECPOINT_YES | MCUXCLECC_OPTION_GENERATEPRECPOINT_NO)
80 #define MCUXCLECC_OPTION_GENERATEPRECPOINT_OFFSET 0u
81 
82 
110 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_GenerateCustomKeyType)
111 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateCustomKeyType(
112  mcuxClKey_CustomType_t customType,
113  mcuxClKey_AlgorithmId_t algoId,
114  mcuxClKey_Size_t size,
115  void *pCustomParams
116  );
117 
118 
119 
120 #ifdef __cplusplus
121 } /* extern "C" */
122 #endif
123 
124 #endif /* MCUXCLECC_WEIERECC_H_ */
mcuxClEcc_Weier_BasicDomainParams_t
Structure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1.
Definition: mcuxClEcc_WeierECC.h:36
+
mcuxClKey.h
Top-level include file for the mcuxClKey component.
+
mcuxClKey_AlgorithmId_t
uint16_t mcuxClKey_AlgorithmId_t
Type for algorithm based key id.
Definition: mcuxClKey_Types.h:52
+
mcuxClEcc_WeierECC_GenerateDomainParams
mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateDomainParams(mcuxClSession_Handle_t pSession, mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams, mcuxClEcc_Weier_BasicDomainParams_t *pEccWeierBasicDomainParams, uint32_t options)
ECC Weierstrass custom domain parameter generation function.
+
mcuxClEcc_WeierECC_GenerateCustomKeyType
mcuxClEcc_Status_t mcuxClEcc_WeierECC_GenerateCustomKeyType(mcuxClKey_CustomType_t customType, mcuxClKey_AlgorithmId_t algoId, mcuxClKey_Size_t size, void *pCustomParams)
Key type constructor.
+
mcuxClKey_CustomType_t
mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t
Custom key type handle type.
Definition: mcuxClKey_Types.h:118
+
mcuxClEcc_Types.h
Type definitions of mcuxClEcc component.
+
mcuxClKey_Size_t
uint32_t mcuxClKey_Size_t
Type for algorithm based key size.
Definition: mcuxClKey_Types.h:57
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEcc_Weier_DomainParams_t
struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
Type for Weierstrass ECC domain parameters.
Definition: mcuxClEcc_Types.h:120
+
mcuxClEcc_Status_t
uint32_t mcuxClEcc_Status_t
Type for mcuxClEcc component return codes.
Definition: mcuxClEcc_Types.h:48
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00293.html b/components/els_pkc/doc/mcxn/html/a00293.html new file mode 100644 index 000000000..84eeeecd6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00293.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxClEls.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls.h File Reference
+
+
+ +

Top-level include file for the ELS driver. +More...

+
#include <mcuxClConfig.h>
+#include <platform_specific_headers.h>
+#include <mcuxClEls_Types.h>
+#include <mcuxClEls_Common.h>
+#include <mcuxClEls_Hash.h>
+#include <mcuxClEls_Hmac.h>
+#include <mcuxClEls_Cmac.h>
+#include <mcuxClEls_Cipher.h>
+#include <mcuxClEls_Aead.h>
+#include <mcuxClEls_KeyManagement.h>
+#include <mcuxClEls_Rng.h>
+#include <mcuxClEls_Ecc.h>
+#include <mcuxClEls_Kdf.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the ELS driver.

+

This includes headers for all of the functionality provided by the ELS IP.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00293_source.html b/components/els_pkc/doc/mcxn/html/a00293_source.html new file mode 100644 index 000000000..32978e8f3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00293_source.html @@ -0,0 +1,133 @@ + + + + + + + +MCUX CLNS: mcuxClEls.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020, 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
233 #ifndef MCUXCLELS_H_
234 #define MCUXCLELS_H_
235 
236 #include <mcuxClConfig.h> // Exported features flags header
237 #include <platform_specific_headers.h>
238 
239 #include <mcuxClEls_Types.h>
240 #include <mcuxClEls_Common.h>
241 #ifdef MCUXCL_FEATURE_ELS_CMD_CRC
242 #include <mcuxClEls_Crc.h>
243 #endif /* MCUXCL_FEATURE_ELS_CMD_CRC */
244 #include <mcuxClEls_Hash.h>
245 #include <mcuxClEls_Hmac.h>
246 #include <mcuxClEls_Cmac.h>
247 #include <mcuxClEls_Cipher.h>
248 #include <mcuxClEls_Aead.h>
249 #include <mcuxClEls_KeyManagement.h>
250 #include <mcuxClEls_Rng.h>
251 #include <mcuxClEls_Ecc.h>
252 #include <mcuxClEls_Kdf.h>
253 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
254 #include <mcuxClEls_GlitchDetector.h>
255 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
256 
257 #endif /* MCUXCLELS_H_ */
mcuxClEls_KeyManagement.h
ELS header for key management.
+
mcuxClEls_Aead.h
ELS header for Authenticated Encryption with Associated Data (AEAD).
+
mcuxClEls_Cipher.h
ELS header for symmetric ciphers.
+
mcuxClEls_Hash.h
ELS header for hashing.
+
mcuxClEls_Rng.h
ELS header for random number generation.
+
mcuxClEls_Hmac.h
ELS header for HMAC support.
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_Types.h
ELS type header.
+
mcuxClEls_Kdf.h
ELS header for key derivation.
+
mcuxClEls_Ecc.h
ELS header for elliptic curve cryptography This header exposes functions that enable using the ELS fo...
+
mcuxClEls_Crc.h
ELS header for Command CRC functionality.
+
mcuxClEls_Cmac.h
ELS header for CMAC support.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00296.html b/components/els_pkc/doc/mcxn/html/a00296.html new file mode 100644 index 000000000..5eada2b06 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00296.html @@ -0,0 +1,213 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Aead.h File Reference
+
+
+ +

ELS header for Authenticated Encryption with Associated Data (AEAD). +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_AeadOption_t
 Command option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async, mcuxClEls_Aead_UpdateData_Async and mcuxClEls_Aead_Finalize_Async. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_AEAD_ENCRYPT
 Set mcuxClEls_AeadOption_t.dcrpt to this value to encrypt data. More...
 
#define MCUXCLELS_AEAD_DECRYPT
 Set mcuxClEls_AeadOption_t.dcrpt to this value to decrypt data. More...
 
#define MCUXCLELS_AEAD_STATE_IN_DISABLE
 Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from ELS. More...
 
#define MCUXCLELS_AEAD_STATE_IN_ENABLE
 Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from the context. More...
 
#define MCUXCLELS_AEAD_LASTINIT_TRUE
 Set mcuxClEls_AeadOption_t.lastinit to this value if this is the last call to init. More...
 
#define MCUXCLELS_AEAD_LASTINIT_FALSE
 Set mcuxClEls_AeadOption_t.lastinit to this value if this is not the last call to init. More...
 
#define MCUXCLELS_AEAD_EXTERN_KEY
 Set mcuxClEls_AeadOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_AEAD_INTERN_KEY
 Set mcuxClEls_AeadOption_t.extkey to this value to use a key from the ELS keystore. More...
 
#define MCUXCLELS_AEAD_ACPMOD_INIT
 Set mcuxClEls_AeadOption_t.acpmod to this value for Init mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_AADPROC
 Set mcuxClEls_AeadOption_t.acpmod to this value for Process Additional Authenticated Data mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_MSGPROC
 Set mcuxClEls_AeadOption_t.acpmod to this value for Process Message mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_FINAL
 Set mcuxClEls_AeadOption_t.acpmod to this value for Finalize mode. For internal use. More...
 
#define MCUXCLELS_AEAD_STATE_OUT_ENABLE
 Set mcuxClEls_AeadOption_t.acpsoe to this value to save the state to the context. For internal use. More...
 
#define MCUXCLELS_AEAD_IV_BLOCK_SIZE
 
#define MCUXCLELS_AEAD_AAD_BLOCK_SIZE
 AES-GCM AAD Granularity: 128 bit (16 bytes) More...
 
#define MCUXCLELS_AEAD_TAG_SIZE
 tag size: Tag generation supports only a 128 bit wide tag (16 bytes) More...
 
#define MCUXCLELS_AEAD_CONTEXT_SIZE
 context size: 512 bit (64 bytes) + 16 bytes for finalize More...
 
+ + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Init_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
 AES-GCM initialization. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_PartialInit_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
 AES-GCM partial initialization. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateAad_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pAad, size_t aadLength, uint8_t *pAeadCtx)
 AES-GCM update of the Additional Authenticated Data (AAD) More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateData_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput, uint8_t *pAeadCtx)
 AES-GCM update of the encrypted data. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Finalize_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, size_t aadLength, size_t dataLength, uint8_t *pTag, uint8_t *pAeadCtx)
 AES-GCM final encryption/decryption. More...
 
+

Detailed Description

+

ELS header for Authenticated Encryption with Associated Data (AEAD).

+

This header exposes functions that enable using the ELS for Authenticated Encryption with Associated Data (AEAD). The AEAD algorithm supported by ELS is AES in Galois/Counter Mode (GCM), as described in NIST Special Publication 800-38D.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00296.js b/components/els_pkc/doc/mcxn/html/a00296.js new file mode 100644 index 000000000..bdca12eba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00296.js @@ -0,0 +1,25 @@ +var a00296 = +[ + [ "MCUXCLELS_AEAD_ENCRYPT", "a00691.html#ga3bc61d00867e4344af9c7605a47028cf", null ], + [ "MCUXCLELS_AEAD_DECRYPT", "a00691.html#gaaf35b04563d926ceaa1782d82741d7b7", null ], + [ "MCUXCLELS_AEAD_STATE_IN_DISABLE", "a00691.html#ga445707b186d86232b626330863532c15", null ], + [ "MCUXCLELS_AEAD_STATE_IN_ENABLE", "a00691.html#ga19f5684ee7ffea323b56bab96f7c059b", null ], + [ "MCUXCLELS_AEAD_LASTINIT_TRUE", "a00691.html#ga7af98652f0dba78d1c665b2c9dfd0e29", null ], + [ "MCUXCLELS_AEAD_LASTINIT_FALSE", "a00691.html#ga7f97e1488141405752147029eee6a818", null ], + [ "MCUXCLELS_AEAD_EXTERN_KEY", "a00691.html#ga5b1a905706af4ecad1473f5e3ac8a710", null ], + [ "MCUXCLELS_AEAD_INTERN_KEY", "a00691.html#gaa7d58cf548b411d9aaea17af1539203a", null ], + [ "MCUXCLELS_AEAD_ACPMOD_INIT", "a00691.html#ga6c775ee90e7ea1e3db4840a2037d303c", null ], + [ "MCUXCLELS_AEAD_ACPMOD_AADPROC", "a00691.html#ga536e8fa026cae719c095b47fbb0fd099", null ], + [ "MCUXCLELS_AEAD_ACPMOD_MSGPROC", "a00691.html#ga05e3ebc05c195d1f62ff6a40a98b8d3c", null ], + [ "MCUXCLELS_AEAD_ACPMOD_FINAL", "a00691.html#ga1d5a6d584b299721149ff9bdbeaee517", null ], + [ "MCUXCLELS_AEAD_STATE_OUT_ENABLE", "a00691.html#ga944f3b21904cdbc22385fcfab1c1236b", null ], + [ "MCUXCLELS_AEAD_IV_BLOCK_SIZE", "a00690.html#gacc54b347065e037fd7d5814334b82826", null ], + [ "MCUXCLELS_AEAD_AAD_BLOCK_SIZE", "a00690.html#ga8a1dab00c208f1b7dc1cf8a2a30a3991", null ], + [ "MCUXCLELS_AEAD_TAG_SIZE", "a00690.html#ga61d8f500ac3ed42fff023025b54692f2", null ], + [ "MCUXCLELS_AEAD_CONTEXT_SIZE", "a00690.html#ga191963434b3271e31bdffc12943745e2", null ], + [ "mcuxClEls_Aead_Init_Async", "a00693.html#ga86bbde5d55c2e44102158ef7b802b819", null ], + [ "mcuxClEls_Aead_PartialInit_Async", "a00693.html#ga817b12c984eb2afcaad9aa3c2b75040c", null ], + [ "mcuxClEls_Aead_UpdateAad_Async", "a00693.html#gaa34534b5e5196e07cbcef7c858cc0ea9", null ], + [ "mcuxClEls_Aead_UpdateData_Async", "a00693.html#ga7d5f1b08fbbcda07f881c274b0100c8b", null ], + [ "mcuxClEls_Aead_Finalize_Async", "a00693.html#gab2f0d1f82ce7537c78967ea2989a2054", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00296_source.html b/components/els_pkc/doc/mcxn/html/a00296_source.html new file mode 100644 index 000000000..be85e1621 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00296_source.html @@ -0,0 +1,141 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Aead.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
29 #ifndef MCUXCLELS_AEAD_H_
30 #define MCUXCLELS_AEAD_H_
31 
32 #include <mcuxClConfig.h> // Exported features flags header
33 #include <mcuxClEls_Common.h> // Common functionality
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /**********************************************
40  * CONSTANTS
41  **********************************************/
54 #define MCUXCLELS_AEAD_ENCRYPT (0x00U)
55 #define MCUXCLELS_AEAD_DECRYPT (0x01U)
56 
57 #define MCUXCLELS_AEAD_STATE_IN_DISABLE (0x00U)
58 #define MCUXCLELS_AEAD_STATE_IN_ENABLE (0x01U)
59 
60 #define MCUXCLELS_AEAD_LASTINIT_TRUE (0x01U)
61 #define MCUXCLELS_AEAD_LASTINIT_FALSE (0x00U)
62 
63 #define MCUXCLELS_AEAD_EXTERN_KEY (0x01U)
64 #define MCUXCLELS_AEAD_INTERN_KEY (0x00U)
65 
66 #define MCUXCLELS_AEAD_ACPMOD_INIT (0x00U)
67 #define MCUXCLELS_AEAD_ACPMOD_AADPROC (0x01U)
68 #define MCUXCLELS_AEAD_ACPMOD_MSGPROC (0x02U)
69 #define MCUXCLELS_AEAD_ACPMOD_FINAL (0x03U)
70 
71 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
72 #define MCUXCLELS_AEAD_STATE_OUT_ENABLE (0x01U)
73 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
74 
78 #define MCUXCLELS_AEAD_IV_BLOCK_SIZE 16U
79 #define MCUXCLELS_AEAD_AAD_BLOCK_SIZE 16U
80 #define MCUXCLELS_AEAD_TAG_SIZE 16U
81 #define MCUXCLELS_AEAD_CONTEXT_SIZE 80U
82 
86 /**********************************************
87  * TYPEDEFS
88  **********************************************/
89 
98 typedef union
99 {
100  struct
101  {
102  uint32_t value;
103  } word;
104  struct
105  {
106  uint32_t :1;
107  uint32_t dcrpt :1;
108  uint32_t acpmod :2;
109 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
110  uint32_t acpsoe :1;
111 #else
112  uint32_t :1;
113 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
114  uint32_t acpsie :1;
115  uint32_t msgendw :4;
116  uint32_t lastinit :1;
117  uint32_t :2;
118  uint32_t extkey :1;
119  uint32_t :18;
120  } bits;
121 } mcuxClEls_AeadOption_t;
126 /**********************************************
127  * FUNCTIONS
128  **********************************************/
182 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Init_Async)
183 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Init_Async(
184  mcuxClEls_AeadOption_t options,
185  mcuxClEls_KeyIndex_t keyIdx,
186  uint8_t const * pKey,
187  size_t keyLength,
188  uint8_t const * pIV,
189  size_t ivLength,
190  uint8_t * pAeadCtx
191  );
192 
242 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_PartialInit_Async)
243 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_PartialInit_Async(
244  mcuxClEls_AeadOption_t options,
245  mcuxClEls_KeyIndex_t keyIdx,
246  uint8_t const * pKey,
247  size_t keyLength,
248  uint8_t const * pIV,
249  size_t ivLength,
250  uint8_t * pAeadCtx
251  );
252 
304 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateAad_Async)
305 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateAad_Async(
306  mcuxClEls_AeadOption_t options,
307  mcuxClEls_KeyIndex_t keyIdx,
308  uint8_t const * pKey,
309  size_t keyLength,
310  uint8_t const * pAad,
311  size_t aadLength,
312  uint8_t * pAeadCtx
313  );
314 
369 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateData_Async)
370 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateData_Async(
371  mcuxClEls_AeadOption_t options,
372  mcuxClEls_KeyIndex_t keyIdx,
373  uint8_t const * pKey,
374  size_t keyLength,
375  uint8_t const * pInput,
376  size_t inputLength,
377  uint8_t * pOutput,
378  uint8_t * pAeadCtx
379  );
380 
435 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Finalize_Async)
436 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Finalize_Async(
437  mcuxClEls_AeadOption_t options,
438  mcuxClEls_KeyIndex_t keyIdx,
439  uint8_t const * pKey,
440  size_t keyLength,
441  size_t aadLength,
442  size_t dataLength,
443  uint8_t * pTag,
444  uint8_t * pAeadCtx
445  );
446 
447 #ifdef __cplusplus
448 } /* extern "C" */
449 #endif
450 
451 #endif /* MCUXCLELS_AEAD_H_ */
452 
mcuxClEls_AeadOption_t::dcrpt
uint32_t dcrpt
Defines if encryption or decryption shall be performed.
Definition: mcuxClEls_Aead.h:107
+
mcuxClEls_AeadOption_t::acpsoe
uint32_t acpsoe
This field is managed internally.
Definition: mcuxClEls_Aead.h:110
+
mcuxClEls_Aead_UpdateAad_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateAad_Async(mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pAad, size_t aadLength, uint8_t *pAeadCtx)
AES-GCM update of the Additional Authenticated Data (AAD)
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_AeadOption_t::lastinit
uint32_t lastinit
Defines whether this is the last call to init.
Definition: mcuxClEls_Aead.h:116
+
mcuxClEls_AeadOption_t::acpsie
uint32_t acpsie
This field is managed internally.
Definition: mcuxClEls_Aead.h:114
+
mcuxClEls_Aead_Init_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Init_Async(mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
AES-GCM initialization.
+
mcuxClEls_AeadOption_t::acpmod
uint32_t acpmod
This field is managed internally.
Definition: mcuxClEls_Aead.h:108
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_AeadOption_t::msgendw
uint32_t msgendw
The size of the last data block (plain/cipher text) in bytes, without padding.
Definition: mcuxClEls_Aead.h:115
+
mcuxClEls_Aead_PartialInit_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_PartialInit_Async(mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
AES-GCM partial initialization.
+
mcuxClEls_AeadOption_t::extkey
uint32_t extkey
Defines whether an external key shall be used.
Definition: mcuxClEls_Aead.h:118
+
mcuxClEls_Common.h
ELS header for common functionality.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_Aead_Finalize_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Finalize_Async(mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, size_t aadLength, size_t dataLength, uint8_t *pTag, uint8_t *pAeadCtx)
AES-GCM final encryption/decryption.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_AeadOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Aead.h:102
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_Aead_UpdateData_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateData_Async(mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput, uint8_t *pAeadCtx)
AES-GCM update of the encrypted data.
+
mcuxClEls_AeadOption_t
Command option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async,...
Definition: mcuxClEls_Aead.h:98
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00299.html b/components/els_pkc/doc/mcxn/html/a00299.html new file mode 100644 index 000000000..6e8ad1ffb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00299.html @@ -0,0 +1,199 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Cipher.h File Reference
+
+
+ +

ELS header for symmetric ciphers. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_CipherOption_t
 Command option bit field for mcuxClEls_Cipher_Async. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CIPHER_ENCRYPT
 Set this option at mcuxClEls_CipherOption_t.dcrpt to perform an encryption. More...
 
#define MCUXCLELS_CIPHER_DECRYPT
 Set this option at mcuxClEls_CipherOption_t.dcrpt to perform a decryption. More...
 
#define MCUXCLELS_CIPHER_STATE_OUT_ENABLE
 Set this option at mcuxClEls_CipherOption_t.cphsoe to export the internal ELS state to pIV. More...
 
#define MCUXCLELS_CIPHER_STATE_OUT_DISABLE
 Set this option at mcuxClEls_CipherOption_t.cphsoe to not export the internal ELS state. More...
 
#define MCUXCLELS_CIPHER_STATE_IN_ENABLE
 Set this option at mcuxClEls_CipherOption_t.cphsie to import an external ELS state from pIV. More...
 
#define MCUXCLELS_CIPHER_STATE_IN_DISABLE
 Set this option at mcuxClEls_CipherOption_t.cphsie to not import an external ELS state. More...
 
#define MCUXCLELS_CIPHER_EXTERNAL_KEY
 Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by pKey. More...
 
#define MCUXCLELS_CIPHER_INTERNAL_KEY
 Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by keyIdx. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mode. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Cipher Block Chaining (CBC) mode. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Counter (CTR) mode. More...
 
#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES
 
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128
 Size of an AES128 key: 128 bit (16 bytes) More...
 
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_192
 Size of an AES192 key: 192 bit (24 bytes) More...
 
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256
 Size of an AES192 key: 256 bit (32 bytes) More...
 
+ + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cipher_Async (mcuxClEls_CipherOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pIV, uint8_t *pOutput)
 Performs AES encryption/decryption. More...
 
+

Detailed Description

+

ELS header for symmetric ciphers.

+

This header exposes functions that enable using the ELS for symmetric encryption/decryption. The cipher algorithm supported by ELS is AES in the following modes:

    +
  • Electronic Code Book (ECB) mode,
    • +
  • Cipher Block Chaining (CBC) mode, and
    • +
  • Counter (CTR) mode. Supported key sizes are 128, 192, and 256 bits.
    • +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00299.js b/components/els_pkc/doc/mcxn/html/a00299.js new file mode 100644 index 000000000..cbc556358 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00299.js @@ -0,0 +1,19 @@ +var a00299 = +[ + [ "MCUXCLELS_CIPHER_ENCRYPT", "a00696.html#ga9840411e958cd2b7312c7e62e5dc06d0", null ], + [ "MCUXCLELS_CIPHER_DECRYPT", "a00696.html#ga15e29141f6a5eef67438d6db62cbaa72", null ], + [ "MCUXCLELS_CIPHER_STATE_OUT_ENABLE", "a00696.html#gabb9d9bd0dc215ef17a7ffbabd0f714c7", null ], + [ "MCUXCLELS_CIPHER_STATE_OUT_DISABLE", "a00696.html#ga3eb172e440a7290240fca36a6bf82fa0", null ], + [ "MCUXCLELS_CIPHER_STATE_IN_ENABLE", "a00696.html#gab55a588688b790dd342dfc24f720a7aa", null ], + [ "MCUXCLELS_CIPHER_STATE_IN_DISABLE", "a00696.html#gafc74b6823a43a2b50a27b4ec891ce9ef", null ], + [ "MCUXCLELS_CIPHER_EXTERNAL_KEY", "a00696.html#ga9feef12c93a57ed798263258e74cba73", null ], + [ "MCUXCLELS_CIPHER_INTERNAL_KEY", "a00696.html#gad090b7cf60eb9468ae5fabf55672ab9d", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB", "a00696.html#ga6f585946c286cebc74b291c520eaaec9", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC", "a00696.html#ga22151bc71de63404ddcb4dec66a3d99f", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR", "a00696.html#ga4df5eca54609eed0ff0bf00152c87ccf", null ], + [ "MCUXCLELS_CIPHER_BLOCK_SIZE_AES", "a00695.html#ga36ebb8ab2b019997c6cf2c9d15b944b0", null ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_128", "a00697.html#ga68ee2f7110cd9f2dbce9af07b7c64f0f", null ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_192", "a00697.html#ga40b6da61509c272916be81c25780eeff", null ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_256", "a00697.html#ga474b8fd0f1e5832a4ba327ba7aee3520", null ], + [ "mcuxClEls_Cipher_Async", "a00699.html#gad8b0506b0510f7dc6ef20fd488ee004b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00299_source.html b/components/els_pkc/doc/mcxn/html/a00299_source.html new file mode 100644 index 000000000..38eb33ea8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00299_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Cipher.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
33 #ifndef MCUXCLELS_CIPHER_H_
34 #define MCUXCLELS_CIPHER_H_
35 
36 #include <mcuxClConfig.h> // Exported features flags header
37 #include <mcuxClEls_Common.h> // Common functionality
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 /**********************************************
44  * CONSTANTS
45  **********************************************/
62 #define MCUXCLELS_CIPHER_ENCRYPT 0U
63 #define MCUXCLELS_CIPHER_DECRYPT 1U
64 
65 #define MCUXCLELS_CIPHER_STATE_OUT_ENABLE 1U
66 #define MCUXCLELS_CIPHER_STATE_OUT_DISABLE 0U
67 
68 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
69 #define MCUXCLELS_CIPHER_STATE_IN_ENABLE 1U
70 #define MCUXCLELS_CIPHER_STATE_IN_DISABLE 0U
71 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
72 
73 #define MCUXCLELS_CIPHER_EXTERNAL_KEY 1U
74 #define MCUXCLELS_CIPHER_INTERNAL_KEY 0U
75 
76 #define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB 0x00U
77 #define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC 0x01U
78 #define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR 0x02U
79 
87 #define MCUXCLELS_CIPHER_BLOCK_SIZE_AES ((size_t) 16U)
88 
89 
96 #define MCUXCLELS_CIPHER_KEY_SIZE_AES_128 ((size_t) 16U)
97 #define MCUXCLELS_CIPHER_KEY_SIZE_AES_192 ((size_t) 24U)
98 #define MCUXCLELS_CIPHER_KEY_SIZE_AES_256 ((size_t) 32U)
99 
105 /**********************************************
106  * TYPEDEFS
107  **********************************************/
108 
120 typedef union
121 {
122  struct
123  {
124  uint32_t value;
125  } word;
126  struct
127  {
128  uint32_t :1;
129  uint32_t dcrpt :1;
130  uint32_t cphmde :2;
131  uint32_t cphsoe :1;
132 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
133  uint32_t cphsie :1;
134  uint32_t :7;
135 #else
136  uint32_t :8;
137 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
138  uint32_t extkey :1;
139  uint32_t :18;
140  } bits;
141 } mcuxClEls_CipherOption_t;
146 /**********************************************
147  * FUNCTIONS
148  **********************************************/
215 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cipher_Async)
216 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cipher_Async(
217  mcuxClEls_CipherOption_t options,
218  mcuxClEls_KeyIndex_t keyIdx,
219  uint8_t const * pKey,
220  size_t keyLength,
221  uint8_t const * pInput,
222  size_t inputLength,
223  uint8_t * pIV,
224  uint8_t * pOutput
225  );
226 
231 #ifdef __cplusplus
232 } /* extern "C" */
233 #endif
234 
235 #endif /* MCUXCLELS_CIPHER_H_ */
236 
mcuxClEls_CipherOption_t::cphmde
uint32_t cphmde
Define cipher mode.
Definition: mcuxClEls_Cipher.h:130
+
mcuxClEls_CipherOption_t::extkey
uint32_t extkey
Define whether an external key from memory or ELS internal key should be used.
Definition: mcuxClEls_Cipher.h:138
+
mcuxClEls_Cipher_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cipher_Async(mcuxClEls_CipherOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pIV, uint8_t *pOutput)
Performs AES encryption/decryption.
+
mcuxClEls_CipherOption_t::cphsoe
uint32_t cphsoe
Define whether the ELS internal cipher state should be extracted to external memory or kept internall...
Definition: mcuxClEls_Cipher.h:131
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_CipherOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Cipher.h:124
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_CipherOption_t
Command option bit field for mcuxClEls_Cipher_Async.
Definition: mcuxClEls_Cipher.h:120
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_CipherOption_t::dcrpt
uint32_t dcrpt
Define operation mode.
Definition: mcuxClEls_Cipher.h:129
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_CipherOption_t::cphsie
uint32_t cphsie
Define whether an external provided cipher state should be imported from external memory.
Definition: mcuxClEls_Cipher.h:133
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00302.html b/components/els_pkc/doc/mcxn/html/a00302.html new file mode 100644 index 000000000..eef21781f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00302.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Cmac.h File Reference
+
+
+ +

ELS header for CMAC support. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_CmacOption_t
 Command option bit field for mcuxClEls_Cmac_Async. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMAC_KEY_SIZE_128
 Size of 128 bit CMAC key (16 bytes) More...
 
#define MCUXCLELS_CMAC_KEY_SIZE_256
 Size of 256 bit CMAC key (32 bytes) More...
 
#define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
 Set mcuxClEls_CmacOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
 Set mcuxClEls_CmacOption_t.extkey to this value to use a key from the ELS keystore. More...
 
#define MCUXCLELS_CMAC_INITIALIZE_DISABLE
 Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk does not include the first block of the message. More...
 
#define MCUXCLELS_CMAC_INITIALIZE_ENABLE
 Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk includes the first block of the message. More...
 
#define MCUXCLELS_CMAC_FINALIZE_DISABLE
 Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk does not include the last block of the message. More...
 
#define MCUXCLELS_CMAC_FINALIZE_ENABLE
 Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk includes the last block of the message. More...
 
#define MCUXCLELS_CMAC_OUT_SIZE
 
+ + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cmac_Async (mcuxClEls_CmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pMac)
 Performs CMAC with AES-128 or AES-256. More...
 
+

Detailed Description

+

ELS header for CMAC support.

+

This header exposes functions that enable using the ELS for the generation of cipher-based message authentication codes (CMAC). The supported cipher algorithm is AES-128 and AES-256.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00302.js b/components/els_pkc/doc/mcxn/html/a00302.js new file mode 100644 index 000000000..7dfaeb7cb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00302.js @@ -0,0 +1,13 @@ +var a00302 = +[ + [ "MCUXCLELS_CMAC_KEY_SIZE_128", "a00702.html#ga62fa42c9462e49ed1e357287492a64e8", null ], + [ "MCUXCLELS_CMAC_KEY_SIZE_256", "a00702.html#gab62855422ff04c5fb61bdcd555282931", null ], + [ "MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE", "a00703.html#ga0b115dc62b80bece0cfbb37d8d6be71c", null ], + [ "MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE", "a00703.html#gaf8cc08552ae462283ee61cd55a1e6e6d", null ], + [ "MCUXCLELS_CMAC_INITIALIZE_DISABLE", "a00703.html#ga21b0dadab5a6ff16fa81b41a8bf8d190", null ], + [ "MCUXCLELS_CMAC_INITIALIZE_ENABLE", "a00703.html#ga556198894993c42af47bb004ddde6f8e", null ], + [ "MCUXCLELS_CMAC_FINALIZE_DISABLE", "a00703.html#ga5a7186be485cefe12529107214dd872b", null ], + [ "MCUXCLELS_CMAC_FINALIZE_ENABLE", "a00703.html#ga923398d224ee92df39da7b5a27982850", null ], + [ "MCUXCLELS_CMAC_OUT_SIZE", "a00701.html#ga5e153a25264389155e68014c29ddf815", null ], + [ "mcuxClEls_Cmac_Async", "a00705.html#ga0cc7e60d184ae44edd8ac6376ecf2387", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00302_source.html b/components/els_pkc/doc/mcxn/html/a00302_source.html new file mode 100644 index 000000000..c33f82e9e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00302_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
+
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+ +
+ +
+
+
mcuxClEls_Cmac.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
29 #ifndef MCUXCLELS_CMAC_H_
30 #define MCUXCLELS_CMAC_H_
31 
32 #include <mcuxClConfig.h> // Exported features flags header
33 #include <mcuxClEls_Common.h> // Common functionality
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /**********************************************
40  * MACROS
41  **********************************************/
54 #define MCUXCLELS_CMAC_KEY_SIZE_128 ((size_t) 16U)
55 #define MCUXCLELS_CMAC_KEY_SIZE_256 ((size_t) 32U)
56 
63 #define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE 1U
64 #define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE 0U
65 #define MCUXCLELS_CMAC_INITIALIZE_DISABLE 0U
66 #define MCUXCLELS_CMAC_INITIALIZE_ENABLE 1U
67 #define MCUXCLELS_CMAC_FINALIZE_DISABLE 0U
68 #define MCUXCLELS_CMAC_FINALIZE_ENABLE 1U
69 
73 #define MCUXCLELS_CMAC_OUT_SIZE ((size_t) 16U)
74 
75 
79 /**********************************************
80  * TYPEDEFS
81  **********************************************/
91 typedef union
92 {
93  struct
94  {
95  uint32_t value;
96  } word;
97  struct
98  {
99  uint32_t initialize : 1;
100  uint32_t finalize : 1;
101  uint32_t soe : 1;
102  uint32_t sie : 1;
103  uint32_t :9;
104  uint32_t extkey :1;
105  uint32_t :18;
106  } bits;
107 } mcuxClEls_CmacOption_t;
112 /**********************************************
113  * FUNCTIONS
114  **********************************************/
170 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cmac_Async)
171 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cmac_Async(
172  mcuxClEls_CmacOption_t options,
173  mcuxClEls_KeyIndex_t keyIdx,
174  uint8_t const * pKey,
175  size_t keyLength,
176  uint8_t const * pInput,
177  size_t inputLength,
178  uint8_t * pMac
179  );
180 
181 #ifdef __cplusplus
182 } /* extern "C" */
183 #endif
184 
185 #endif /* MCUXCLELS_CMAC_H_ */
186 
mcuxClEls_CmacOption_t::extkey
uint32_t extkey
An external key should be used.
Definition: mcuxClEls_Cmac.h:104
+
mcuxClEls_CmacOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Cmac.h:95
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_Cmac_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cmac_Async(mcuxClEls_CmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pMac)
Performs CMAC with AES-128 or AES-256.
+
mcuxClEls_CmacOption_t::finalize
uint32_t finalize
Request final processing for the last block of the message.
Definition: mcuxClEls_Cmac.h:100
+
mcuxClEls_CmacOption_t
Command option bit field for mcuxClEls_Cmac_Async.
Definition: mcuxClEls_Cmac.h:91
+
mcuxClEls_CmacOption_t::soe
uint32_t soe
This field is managed internally.
Definition: mcuxClEls_Cmac.h:101
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_CmacOption_t::sie
uint32_t sie
This field is managed internally.
Definition: mcuxClEls_Cmac.h:102
+
mcuxClEls_Common.h
ELS header for common functionality.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_CmacOption_t::initialize
uint32_t initialize
Request initial processing for the first block of the message.
Definition: mcuxClEls_Cmac.h:99
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00305.html b/components/els_pkc/doc/mcxn/html/a00305.html new file mode 100644 index 000000000..a913568ee --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00305.html @@ -0,0 +1,299 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+Data Structures | +Macros | +Typedefs | +Functions
+
+
mcuxClEls_Common.h File Reference
+
+
+ +

ELS header for common functionality. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <platform_specific_headers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Data Structures

union  mcuxClEls_HwVersion_t
 Result type of mcuxClEls_GetHwVersion. More...
 
union  mcuxClEls_HwState_t
 Result type of mcuxClEls_GetHwState. More...
 
union  mcuxClEls_InterruptOptionEn_t
 Command option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags. More...
 
union  mcuxClEls_InterruptOptionRst_t
 Type to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags. More...
 
union  mcuxClEls_InterruptOptionSet_t
 Type to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags. More...
 
union  mcuxClEls_HwConfig_t
 Result type of #mcuxClEls_GetHwConfig. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_API
 Marks a function as a public API function of the mcuxClEls component. More...
 
#define MCUXCLELS_HW_VERSION
 Compatible ELS hardware IP version for the CLNS release that this header is part of. More...
 
+#define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN
 
#define MCUXCLELS_ELS_INTERRUPT_ENABLE
 Set this option at mcuxClEls_InterruptOptionEn_t.elsint to allow ELS to trigger an interrupt. More...
 
#define MCUXCLELS_ELS_INTERRUPT_DISABLE
 Set this option at mcuxClEls_InterruptOptionEn_t.elsint to prevent ELS from triggering an interrupt. More...
 
#define MCUXCLELS_ELS_RESET_CLEAR
 Set this option at mcuxClEls_InterruptOptionRst_t.elsint to reset the ELS interrupt flag. More...
 
#define MCUXCLELS_ELS_RESET_KEEP
 Set this option at mcuxClEls_InterruptOptionRst_t.elsint to keep the ELS interrupt flag. More...
 
#define MCUXCLELS_ELS_INTERRUPT_SET
 Set this option at mcuxClEls_InterruptOptionSet_t.elsint to set the ELS interrupt flag. More...
 
#define MCUXCLELS_ELS_INTERRUPT_KEEP
 Set this option at mcuxClEls_InterruptOptionSet_t.elsint to leave the ELS interrupt flag unchanged. More...
 
#define MCUXCLELS_ERROR_FLAGS_KEEP
 Set this option at mcuxClEls_ErrorHandling_t to not clear any error flags. More...
 
#define MCUXCLELS_ERROR_FLAGS_CLEAR
 Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags. More...
 
#define MCUXCLELS_RESET_DO_NOT_CANCEL
 Set this option at mcuxClEls_ResetOption_t to abort the requested command if another ELS operation is still running. More...
 
#define MCUXCLELS_RESET_CANCEL
 Set this option at mcuxClEls_ResetOption_t to execute the requested command even if another ELS operation is still running. More...
 
#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged non-secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged non-secure mode. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_NORUN
 This value of mcuxClEls_HwState_t.ecdsavfy means that no ECDSA verify operation has been executed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_FAIL
 This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification failed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_OK
 This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification passed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_ERROR
 This value of mcuxClEls_HwState_t.ecdsavfy means that an error has occurred. More...
 
#define MCUXCLELS_STATUS_DRBGENTLVL_NONE
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG is not running. More...
 
#define MCUXCLELS_STATUS_DRBGENTLVL_LOW
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with a low security strength (sufficient for commands with a low DRBG security strength requirement, see the function description to check which level is required) More...
 
#define MCUXCLELS_STATUS_DRBGENTLVL_HIGH
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with 128 bits of security strength (sufficient for commands with a high DRBG security strength requirement, see the function description to check which level is required) More...
 
#define drbgreqsub
 Deprecated name for mcuxClEls_HwConfig_t.drbgreqsup. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClEls_ErrorHandling_t
 Type to handle ELS error clearing options. More...
 
typedef uint32_t mcuxClEls_ResetOption_t
 Type to handle ELS reset options. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwVersion (mcuxClEls_HwVersion_t *result)
 Determines the version of the underlying ELS hardware IP. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwState (mcuxClEls_HwState_t *result)
 Determines the current state of the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Enable_Async (void)
 Enables the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async (mcuxClEls_ResetOption_t options)
 Perform a synchronous reset of the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Disable (void)
 Disable the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntEnableFlags (mcuxClEls_InterruptOptionEn_t options)
 Set interrupt enable flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetIntEnableFlags (mcuxClEls_InterruptOptionEn_t *result)
 Get interrupt enable flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetIntFlags (mcuxClEls_InterruptOptionRst_t options)
 Clear the interrupt status register. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntFlags (mcuxClEls_InterruptOptionSet_t options)
 Set the interrupt status register, for debug and testing purposes. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation (mcuxClEls_ErrorHandling_t errorHandling)
 Wait for an ELS operation and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_LimitedWaitForOperation (uint32_t counterLimit, mcuxClEls_ErrorHandling_t errorHandling)
 Await the completion of an ELS operation for a limited amount of time and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetErrorFlags (void)
 Resets all error flags that have been set by a previous operation. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorCode (mcuxClEls_ErrorHandling_t errorHandling)
 Get the last ELS error code and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorLevel (mcuxClEls_ErrorHandling_t errorHandling, uint32_t *errorLevel)
 Get the last ELS error code and level and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetRandomStartDelay (uint32_t delay)
 Set the random start delay for AES based operations. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetRandomStartDelay (uint32_t *delay)
 Get the random start delay for AES based operations. More...
 
+

Detailed Description

+

ELS header for common functionality.

+

This header exposes functions that support hardware state management for other ELS commands.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00305.js b/components/els_pkc/doc/mcxn/html/a00305.js new file mode 100644 index 000000000..3ef850725 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00305.js @@ -0,0 +1,46 @@ +var a00305 = +[ + [ "MCUXCLELS_API", "a00707.html#ga5f87370c0e52126f57afb5b13c283d73", null ], + [ "MCUXCLELS_HW_VERSION", "a00707.html#gac06d5de9fa68404bc11b426ed3cdd8f6", null ], + [ "MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN", "a00707.html#ga4a47260edd9499c9dd629e1e5bc62235", null ], + [ "MCUXCLELS_ELS_INTERRUPT_ENABLE", "a00708.html#ga845d16f6376f2c28864f1855ddbde61c", null ], + [ "MCUXCLELS_ELS_INTERRUPT_DISABLE", "a00708.html#ga2427d922e877e78bac483cf68f6c5892", null ], + [ "MCUXCLELS_ELS_RESET_CLEAR", "a00709.html#ga1a702565c0bfd8fa6b28db41f61ba3be", null ], + [ "MCUXCLELS_ELS_RESET_KEEP", "a00709.html#gac963d24ca31b1b3e89d31efb7ccf6abf", null ], + [ "MCUXCLELS_ELS_INTERRUPT_SET", "a00710.html#ga08923159f1ba8aff0b1b06a547db7ff6", null ], + [ "MCUXCLELS_ELS_INTERRUPT_KEEP", "a00710.html#gab3911a79259043879d2446269741ac19", null ], + [ "MCUXCLELS_ERROR_FLAGS_KEEP", "a00711.html#gab2b0ee14cae59a5f5f4f2563d7189854", null ], + [ "MCUXCLELS_ERROR_FLAGS_CLEAR", "a00711.html#ga3528b1fa2b3c39524898299a3a90a753", null ], + [ "MCUXCLELS_RESET_DO_NOT_CANCEL", "a00712.html#gac02fc8694aa89061b1eb47bad8fca21d", null ], + [ "MCUXCLELS_RESET_CANCEL", "a00712.html#ga1f4338ba7f7d0ddd5b84236bc4545ee3", null ], + [ "MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE", "a00713.html#gaa8bbf4768eed46d69b6a9077f51c1481", null ], + [ "MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE", "a00713.html#ga11ba151ce5c794f3f433b1261c95f68c", null ], + [ "MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE", "a00713.html#gab95d873091d5a836bc3e37079766fb2e", null ], + [ "MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE", "a00713.html#ga9fd4449827c0ff5467277eca65c9d647", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_NORUN", "a00714.html#ga47e2750982e2b0db292e2a9944c1f635", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_FAIL", "a00714.html#ga647b29383be891aba96ede66ae327401", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_OK", "a00714.html#ga893b34cd2238053fb44a50ebe33bb5e3", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_ERROR", "a00714.html#ga9472855457417ea944570647a61c2b47", null ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_NONE", "a00715.html#ga5fe71d0b1d8e1c52794c24a98b6e2645", null ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_LOW", "a00715.html#ga1276cd61f68f743f631cdae25662b310", null ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_HIGH", "a00715.html#ga9e70aa4c959f092c77fc154327bc4bdb", null ], + [ "drbgreqsub", "a00716.html#ga58d0f81d7d9c40f22d85d048150bbc72", null ], + [ "mcuxClEls_ErrorHandling_t", "a00716.html#ga3411a9581b6770690eba6acc6b69c278", null ], + [ "mcuxClEls_ResetOption_t", "a00716.html#gab1ed08db7ad22b92ac714d17566d2fff", null ], + [ "mcuxClEls_GetHwVersion", "a00717.html#gaade966640da314f17e6024ada7df6219", null ], + [ "mcuxClEls_GetHwState", "a00717.html#gadb25761b4c1a0de90f1420f459093bd5", null ], + [ "mcuxClEls_Enable_Async", "a00717.html#ga6dbf394b38add1c6967dab368435b657", null ], + [ "mcuxClEls_Reset_Async", "a00717.html#ga988b48898347ef4de0912cae0f631764", null ], + [ "mcuxClEls_Disable", "a00717.html#gacbf878536100314ce61081c54ea5ef9e", null ], + [ "mcuxClEls_SetIntEnableFlags", "a00717.html#ga1cfec63993fa918d3b590b41b3558d84", null ], + [ "mcuxClEls_GetIntEnableFlags", "a00717.html#ga3de0def8758ec5320102a0beb521da37", null ], + [ "mcuxClEls_ResetIntFlags", "a00717.html#ga02f29ce399968793e6091505ddd9fa5e", null ], + [ "mcuxClEls_SetIntFlags", "a00717.html#ga90b8060544476c2e7278157833410c97", null ], + [ "mcuxClEls_WaitForOperation", "a00717.html#gaee73cb4825b7722d9e085565170eb18e", null ], + [ "mcuxClEls_LimitedWaitForOperation", "a00717.html#ga396f130363332586a56b9667cf46fe7e", null ], + [ "mcuxClEls_ResetErrorFlags", "a00717.html#gaf5485491a0851bc3c475e50690219d74", null ], + [ "mcuxClEls_GetErrorCode", "a00717.html#gaeb4fc2a3a1115489dcb9912f7160cb7f", null ], + [ "mcuxClEls_GetErrorLevel", "a00717.html#ga896309eafc0aedbb5514ec4111b4d750", null ], + [ "mcuxClEls_SetRandomStartDelay", "a00717.html#gabe9a2fe0df05c3e99fcd4a7a9138a2c8", null ], + [ "mcuxClEls_GetRandomStartDelay", "a00717.html#ga1269f369af68e23e9ee8d282dc37c42b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00305_source.html b/components/els_pkc/doc/mcxn/html/a00305_source.html new file mode 100644 index 000000000..8af5809e6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00305_source.html @@ -0,0 +1,195 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Common.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
27 #ifndef MCUXCLELS_COMMON_H_
28 #define MCUXCLELS_COMMON_H_
29 
30 #include <mcuxClConfig.h> // Exported features flags header
31 #include <mcuxClEls_Types.h> // Common types
32 #include <mcuxCsslFlowProtection.h>
33 #include <mcuxClCore_FunctionIdentifiers.h>
34 #include <platform_specific_headers.h>
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
47 #define MCUXCLELS_API
48 
49 /**********************************************
50  * CONSTANTS
51  **********************************************/
52 
57 #ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION
58 #define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \
59  .bits = { \
60  .revision = (uint32_t) ELS_HW_VERSION_REVISION, \
61  .minor = (uint32_t) ELS_HW_VERSION_MINOR, \
62  .major = (uint32_t) ELS_HW_VERSION_MAJOR, \
63  .level = (uint32_t) ELS_HW_VERSION_LEVEL \
64  } \
65  })
66 #else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
67 #define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \
68  .bits = { \
69  .revision = (uint32_t) ELS_HW_VERSION_REVISION, \
70  .minor = (uint32_t) ELS_HW_VERSION_MINOR, \
71  .major = (uint32_t) ELS_HW_VERSION_MAJOR, \
72  .fw_revision = (uint32_t) ELS_HW_VERSION_FW_REVISION, \
73  .fw_minor = (uint32_t) ELS_HW_VERSION_FW_MINOR, \
74  .fw_major = (uint32_t) ELS_HW_VERSION_FW_MAJOR \
75  } \
76  })
77 #endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
78 
79 #ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
80  #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_CompareDmaFinalOutputAddress)
81 #else
82  #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN (0u)
83 #endif
84 
85 
92 #define MCUXCLELS_ELS_INTERRUPT_ENABLE (0x01U)
93 #define MCUXCLELS_ELS_INTERRUPT_DISABLE (0x00U)
94 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
95 #define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE ((uint32_t) 1U)
96 #define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE ((uint32_t) 0U)
97 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
98 
106 #define MCUXCLELS_ELS_RESET_CLEAR (0x01U)
107 #define MCUXCLELS_ELS_RESET_KEEP (0x00U)
108 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
109 #define MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR ((uint32_t) 1U)
110 #define MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP ((uint32_t) 0U)
111 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
112 
120 #define MCUXCLELS_ELS_INTERRUPT_SET (0x01U)
121 #define MCUXCLELS_ELS_INTERRUPT_KEEP (0x00U)
122 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
123 #define MCUXCLELS_GLITCH_DETECTOR_NEG_SET (0x01U)
124 #define MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP (0x00U)
125 #define MCUXCLELS_GLITCH_DETECTOR_POS_SET (0x01U)
126 #define MCUXCLELS_GLITCH_DETECTOR_POS_KEEP (0x00U)
127 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
128 
136 #define MCUXCLELS_ERROR_FLAGS_KEEP ((mcuxClEls_ErrorHandling_t) 0x0u)
137 #define MCUXCLELS_ERROR_FLAGS_CLEAR ((mcuxClEls_ErrorHandling_t) 0x1u)
138 
146 #define MCUXCLELS_RESET_DO_NOT_CANCEL ((mcuxClEls_ResetOption_t) 0x0u)
147 #define MCUXCLELS_RESET_CANCEL ((mcuxClEls_ResetOption_t) 0x1u)
148 
161 #define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE ((uint32_t) 0x0u)
162 #define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE ((uint32_t) 0x1u)
163 #define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE ((uint32_t) 0x2u)
164 #define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE ((uint32_t) 0x3u)
165 
173 #define MCUXCLELS_STATUS_ECDSAVFY_NORUN ((uint32_t) 0x0u)
174 #define MCUXCLELS_STATUS_ECDSAVFY_FAIL ((uint32_t) 0x1u)
175 #define MCUXCLELS_STATUS_ECDSAVFY_OK ((uint32_t) 0x2u)
176 #define MCUXCLELS_STATUS_ECDSAVFY_ERROR ((uint32_t) 0x3u)
177 
184 #define MCUXCLELS_STATUS_DRBGENTLVL_NONE ((uint32_t) 0x0u)
185 #define MCUXCLELS_STATUS_DRBGENTLVL_LOW ((uint32_t) 0x1u)
186 #define MCUXCLELS_STATUS_DRBGENTLVL_HIGH ((uint32_t) 0x2u)
187 
189 #ifdef MCUXCL_FEATURE_ELS_LOCKING
190 
195 #define MCUXCLELS_MASTER_UNLOCK_ANY ((uint32_t) 0x1Fu)
196 
197 #endif /* MCUXCL_FEATURE_ELS_LOCKING */
198 
199 
200 
205 /**********************************************
206  * TYPEDEFS
207  **********************************************/
208 
221 typedef union
222 {
223  struct
224  {
225  uint32_t value;
226  } word;
227  struct
228  {
229  uint32_t revision :4;
230  uint32_t minor :8;
231  uint32_t major :4;
232 #ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION
233  uint32_t level :4;
234  uint32_t :12;
235 #else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
236  uint32_t fw_revision :4;
237  uint32_t fw_minor :8;
238  uint32_t fw_major :4;
239 #endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */
240  } bits;
241 } mcuxClEls_HwVersion_t;
242 
248 typedef union
249 {
250  struct
251  {
252  uint32_t value;
253  } word;
254  struct
255  {
256  uint32_t busy :1;
257  uint32_t irq :1;
258  uint32_t err :1;
259  uint32_t prngready :1;
260  uint32_t ecdsavfy :2;
261  uint32_t pprot :2;
262  uint32_t drbgentlvl :2;
263  uint32_t dtrng_busy: 1;
264 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
265  uint32_t gdet_pos :1;
266  uint32_t gdet_neg :1;
267 #else
268  uint32_t :2;
269 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
270  uint32_t :3;
271 #ifdef MCUXCL_FEATURE_ELS_LOCKING
272  uint32_t els_locked :1;
273 #else
274  uint32_t :1;
275 #endif /* MCUXCL_FEATURE_ELS_LOCKING */
276  uint32_t :15;
277  } bits;
278 } mcuxClEls_HwState_t;
279 
285 typedef uint32_t mcuxClEls_ErrorHandling_t;
286 
292 typedef uint32_t mcuxClEls_ResetOption_t;
293 
299 typedef union
300 {
301  struct
302  {
303  uint32_t value;
304  } word;
305  struct
306  {
307  uint32_t elsint :1;
308 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
309  uint32_t gdetint :1;
310 #else
311  uint32_t :1;
312 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
313  uint32_t :30;
314  } bits;
315 } mcuxClEls_InterruptOptionEn_t;
316 
320 typedef union
321 {
322  struct
323  {
324  uint32_t value;
325  } word;
326  struct
327  {
328  uint32_t elsint :1;
329 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
330  uint32_t gdetint :1;
331 #else
332  uint32_t :1;
333 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
334  uint32_t :30;
335  } bits;
336 } mcuxClEls_InterruptOptionRst_t;
337 
341 typedef union
342 {
343  struct
344  {
345  uint32_t value;
346  } word;
347  struct
348  {
349  uint32_t elsint :1;
350 #ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR
351  uint32_t gdetint_neg :1;
352  uint32_t gdetint_pos :1;
353 #else
354  uint32_t :2;
355 #endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */
356  uint32_t :29;
357  } bits;
358 } mcuxClEls_InterruptOptionSet_t;
359 
365 typedef union
366 {
367  struct
368  {
369  uint32_t value;
370  } word;
371  struct
372  {
373  uint32_t ciphersup :1;
374  uint32_t authciphersup :1;
375  uint32_t ecsignsup :1;
376  uint32_t ecvfysup :1;
377  uint32_t eckxchsup :1;
378  uint32_t keygensup :1;
379  uint32_t keyinsup :1;
380  uint32_t keyoutsup :1;
381  uint32_t kdeletesup :1;
382  uint32_t keyprovsup :1;
383  uint32_t ckdfsup :1;
384  uint32_t hkdfsup :1;
385  uint32_t tlsinitsup :1;
386  uint32_t hashsup :1;
387  uint32_t hmacsup :1;
388  uint32_t cmacsup :1;
389  uint32_t drbgreqsup :1;
390  uint32_t drbgtestsup :1;
391  uint32_t dtrgncfgloadsup :1;
392  uint32_t dtrngevalsup :1;
393  uint32_t gdetcfgloadsup :1;
394  uint32_t gdettrimsup :1;
395  uint32_t :10;
396  } bits;
397 } mcuxClEls_HwConfig_t;
398 
399 #define drbgreqsub drbgreqsup
400 
401 
406 /**********************************************
407  * FUNCTIONS
408  **********************************************/
428 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwVersion)
429 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwVersion(
430  mcuxClEls_HwVersion_t * result
431  );
432 
433 #ifdef MCUXCL_FEATURE_ELS_HWCONFIG
434 
445 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwConfig)
446 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwConfig(
447  mcuxClEls_HwConfig_t * result
448  );
449 #endif /* MCUXCL_FEATURE_ELS_HWCONFIG */
450 
462 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwState)
463 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwState(
464  mcuxClEls_HwState_t * result
465  );
466 
478 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Enable_Async)
479 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Enable_Async(
480  void
481  );
482 
507 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Reset_Async)
508 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Reset_Async(
509  mcuxClEls_ResetOption_t options
510  );
511 
523 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Disable)
524 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Disable(
525  void
526 );
527 
539 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntEnableFlags)
540 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntEnableFlags(
541  mcuxClEls_InterruptOptionEn_t options
542  );
543 
555 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetIntEnableFlags)
556 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetIntEnableFlags(
557  mcuxClEls_InterruptOptionEn_t * result
558  );
559 
571 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetIntFlags)
572 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetIntFlags(
573  mcuxClEls_InterruptOptionRst_t options
574  );
575 
587 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntFlags)
588 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntFlags(
589  mcuxClEls_InterruptOptionSet_t options
590  );
591 
609 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_WaitForOperation)
610 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_WaitForOperation(
611  mcuxClEls_ErrorHandling_t errorHandling
612  );
613 
635 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_LimitedWaitForOperation)
636 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_LimitedWaitForOperation(
637  uint32_t counterLimit,
638  mcuxClEls_ErrorHandling_t errorHandling
639  );
640 
650 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetErrorFlags)
651 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetErrorFlags(
652  void);
653 
667 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorCode)
668 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorCode(
669  mcuxClEls_ErrorHandling_t errorHandling
670  );
671 
687 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorLevel)
688 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorLevel(
689  mcuxClEls_ErrorHandling_t errorHandling,
690  uint32_t *errorLevel
691  );
692 
706 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetRandomStartDelay)
707 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetRandomStartDelay(
708  uint32_t delay
709  );
710 
724 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetRandomStartDelay)
725 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetRandomStartDelay(
726  uint32_t * delay
727  );
728 
729 #ifdef MCUXCL_FEATURE_ELS_LOCKING
730 
753 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLock)
754 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLock(
755  uint32_t * pSessionId
756  );
757 
777 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ReleaseLock)
778 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ReleaseLock(
779  uint32_t sessionId
780  );
781 
796 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_IsLocked)
797 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_IsLocked(void);
798 
815 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetMasterUnlock)
816 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetMasterUnlock(
817  uint32_t masterId
818  );
819 
820 #endif /* MCUXCL_FEATURE_ELS_LOCKING */
821 
822 
823 #ifdef MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK
824 
835 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLastDmaAddress)
836 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLastDmaAddress(
837  uint32_t* pLastAddress
838  );
839 #endif /* MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK */
840 
841 #ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK
842 
859 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_CompareDmaFinalOutputAddress)
860 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_CompareDmaFinalOutputAddress(
861  uint8_t *outputStartAddress,
862  size_t expectedLength
863  );
864 #endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */
865 
866 #ifdef __cplusplus
867 } /* extern "C" */
868 #endif
869 
870 #endif /* MCUXCLELS_COMMON_H_ */
871 
mcuxClEls_SetIntEnableFlags
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntEnableFlags(mcuxClEls_InterruptOptionEn_t options)
Set interrupt enable flags.
+
mcuxClEls_HwConfig_t::drbgreqsup
uint32_t drbgreqsup
Indicates whether the drbg_req command is supported.
Definition: mcuxClEls_Common.h:389
+
mcuxClEls_HwState_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:252
+
mcuxClEls_HwConfig_t::gdettrimsup
uint32_t gdettrimsup
Indicates whether the gdet_trim command is supported.
Definition: mcuxClEls_Common.h:394
+
mcuxClEls_HwConfig_t::ciphersup
uint32_t ciphersup
Indicates whether the cipher command is supported.
Definition: mcuxClEls_Common.h:373
+
mcuxClEls_InterruptOptionRst_t::elsint
uint32_t elsint
Whether ELS interrupt should be reset. (For possible values of this field, see mcuxClEls_InterruptOpt...
Definition: mcuxClEls_Common.h:328
+
mcuxClEls_SetIntFlags
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntFlags(mcuxClEls_InterruptOptionSet_t options)
Set the interrupt status register, for debug and testing purposes.
+
mcuxClEls_HwConfig_t::keyinsup
uint32_t keyinsup
Indicates whether the keyin command is supported.
Definition: mcuxClEls_Common.h:379
+
mcuxClEls_HwState_t::drbgentlvl
uint32_t drbgentlvl
Entropy quality of the current DRBG instance (For possible values of this field, see MCUXCLELS_STATUS...
Definition: mcuxClEls_Common.h:262
+
mcuxClEls_HwConfig_t::eckxchsup
uint32_t eckxchsup
Indicates whether the dhkey_xch command is supported.
Definition: mcuxClEls_Common.h:377
+
mcuxClEls_HwConfig_t::dtrgncfgloadsup
uint32_t dtrgncfgloadsup
Indicates whether the dtrng_cfg_load command is is supported.
Definition: mcuxClEls_Common.h:391
+
mcuxClEls_HwConfig_t::gdetcfgloadsup
uint32_t gdetcfgloadsup
Indicates whether the gdet_cfg_load command is supported.
Definition: mcuxClEls_Common.h:393
+
mcuxClEls_HwVersion_t::minor
uint32_t minor
Minor version.
Definition: mcuxClEls_Common.h:230
+
mcuxClEls_HwConfig_t
Result type of #mcuxClEls_GetHwConfig.
Definition: mcuxClEls_Common.h:365
+
mcuxClEls_InterruptOptionSet_t::elsint
uint32_t elsint
Whether ELS interrupt should be set. (For possible values of this field, see mcuxClEls_InterruptOptio...
Definition: mcuxClEls_Common.h:349
+
mcuxClEls_HwVersion_t::major
uint32_t major
Major version.
Definition: mcuxClEls_Common.h:231
+
mcuxClEls_HwConfig_t::hashsup
uint32_t hashsup
Indicates whether the hash command is supported.
Definition: mcuxClEls_Common.h:386
+
mcuxClEls_LimitedWaitForOperation
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_LimitedWaitForOperation(uint32_t counterLimit, mcuxClEls_ErrorHandling_t errorHandling)
Await the completion of an ELS operation for a limited amount of time and optionally clear the error ...
+
mcuxClEls_HwConfig_t::kdeletesup
uint32_t kdeletesup
Indicates whether the kdelete command is supported.
Definition: mcuxClEls_Common.h:381
+
mcuxClEls_HwConfig_t::keygensup
uint32_t keygensup
Indicates whether the keygen command is supported.
Definition: mcuxClEls_Common.h:378
+
mcuxClEls_HwConfig_t::keyprovsup
uint32_t keyprovsup
Indicates whether the keyprov command is supported.
Definition: mcuxClEls_Common.h:382
+
mcuxClEls_Disable
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Disable(void)
Disable the ELS.
+
mcuxClEls_HwConfig_t::hkdfsup
uint32_t hkdfsup
Indicates whether the hkdf command is supported.
Definition: mcuxClEls_Common.h:384
+
mcuxClEls_HwConfig_t::authciphersup
uint32_t authciphersup
Indicates whether the auth_cipher command is supported.
Definition: mcuxClEls_Common.h:374
+
mcuxClEls_HwConfig_t::keyoutsup
uint32_t keyoutsup
Indicates whether the keyout command is supported.
Definition: mcuxClEls_Common.h:380
+
mcuxClEls_HwState_t::pprot
uint32_t pprot
The privilege/security level of the most recently started ELS command (For possible values of this fi...
Definition: mcuxClEls_Common.h:261
+
mcuxClEls_GetRandomStartDelay
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetRandomStartDelay(uint32_t *delay)
Get the random start delay for AES based operations.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClEls_HwState_t::err
uint32_t err
ELS is in error state.
Definition: mcuxClEls_Common.h:258
+
mcuxClEls_ResetIntFlags
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetIntFlags(mcuxClEls_InterruptOptionRst_t options)
Clear the interrupt status register.
+
mcuxClEls_HwConfig_t::cmacsup
uint32_t cmacsup
Indicates whether the cmac command is supported.
Definition: mcuxClEls_Common.h:388
+
mcuxClEls_HwConfig_t::hmacsup
uint32_t hmacsup
Indicates whether the hmac command is supported.
Definition: mcuxClEls_Common.h:387
+
mcuxClEls_HwState_t::irq
uint32_t irq
ELS interrupt activated.
Definition: mcuxClEls_Common.h:257
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_WaitForOperation
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation(mcuxClEls_ErrorHandling_t errorHandling)
Wait for an ELS operation and optionally clear the error status.
+
mcuxClEls_InterruptOptionRst_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:324
+
mcuxClEls_HwConfig_t::ecsignsup
uint32_t ecsignsup
Indicates whether the ecsign command is supported.
Definition: mcuxClEls_Common.h:375
+
mcuxClEls_HwConfig_t::drbgtestsup
uint32_t drbgtestsup
Indicates whether the drbg_test command is supported.
Definition: mcuxClEls_Common.h:390
+
mcuxClEls_HwConfig_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:369
+
mcuxClEls_HwState_t::ecdsavfy
uint32_t ecdsavfy
ECDSA verify operation state (For possible values of this field, see MCUXCLELS_STATUS_ECDSAVFY_)
Definition: mcuxClEls_Common.h:260
+
mcuxClEls_Types.h
ELS type header.
+
mcuxClEls_HwVersion_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:225
+
mcuxClEls_HwConfig_t::tlsinitsup
uint32_t tlsinitsup
Indicates whether the tls_init command is supported.
Definition: mcuxClEls_Common.h:385
+
mcuxClEls_GetErrorLevel
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorLevel(mcuxClEls_ErrorHandling_t errorHandling, uint32_t *errorLevel)
Get the last ELS error code and level and optionally clear the error status.
+
mcuxClEls_HwState_t::prngready
uint32_t prngready
ELS PRNG is seeded and ready to use.
Definition: mcuxClEls_Common.h:259
+
mcuxClEls_SetRandomStartDelay
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetRandomStartDelay(uint32_t delay)
Set the random start delay for AES based operations.
+
mcuxClEls_InterruptOptionSet_t
Type to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags.
Definition: mcuxClEls_Common.h:341
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_InterruptOptionSet_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:345
+
mcuxClEls_Enable_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Enable_Async(void)
Enables the ELS.
+
mcuxClEls_HwConfig_t::ckdfsup
uint32_t ckdfsup
Indicates whether the ckdf command is supported.
Definition: mcuxClEls_Common.h:383
+
mcuxClEls_GetHwState
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwState(mcuxClEls_HwState_t *result)
Determines the current state of the ELS.
+
mcuxClEls_ResetOption_t
uint32_t mcuxClEls_ResetOption_t
Type to handle ELS reset options.
Definition: mcuxClEls_Common.h:292
+
mcuxClEls_HwState_t::dtrng_busy
uint32_t dtrng_busy
Indicates the DTRNG is gathering entropy.
Definition: mcuxClEls_Common.h:263
+
mcuxClEls_HwVersion_t::revision
uint32_t revision
Revision number.
Definition: mcuxClEls_Common.h:229
+
mcuxClEls_ResetErrorFlags
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetErrorFlags(void)
Resets all error flags that have been set by a previous operation.
+
mcuxClEls_GetHwVersion
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwVersion(mcuxClEls_HwVersion_t *result)
Determines the version of the underlying ELS hardware IP.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClEls_GetErrorCode
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorCode(mcuxClEls_ErrorHandling_t errorHandling)
Get the last ELS error code and optionally clear the error status.
+
mcuxClEls_HwConfig_t::ecvfysup
uint32_t ecvfysup
Indicates whether the ecvfy command is supported.
Definition: mcuxClEls_Common.h:376
+
mcuxClEls_ErrorHandling_t
uint32_t mcuxClEls_ErrorHandling_t
Type to handle ELS error clearing options.
Definition: mcuxClEls_Common.h:285
+
mcuxClEls_HwVersion_t::level
uint32_t level
Release level version.
Definition: mcuxClEls_Common.h:233
+
mcuxClEls_InterruptOptionRst_t
Type to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags.
Definition: mcuxClEls_Common.h:320
+
mcuxClEls_Reset_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async(mcuxClEls_ResetOption_t options)
Perform a synchronous reset of the ELS.
+
mcuxClEls_InterruptOptionEn_t
Command option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags.
Definition: mcuxClEls_Common.h:299
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_InterruptOptionEn_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Common.h:303
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_HwState_t
Result type of mcuxClEls_GetHwState.
Definition: mcuxClEls_Common.h:248
+
mcuxClEls_HwVersion_t
Result type of mcuxClEls_GetHwVersion.
Definition: mcuxClEls_Common.h:221
+
mcuxClEls_HwState_t::busy
uint32_t busy
ELS is busy.
Definition: mcuxClEls_Common.h:256
+
mcuxClEls_HwConfig_t::dtrngevalsup
uint32_t dtrngevalsup
Indicates whether the dtrng_eval command is supported.
Definition: mcuxClEls_Common.h:392
+
mcuxClEls_GetIntEnableFlags
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetIntEnableFlags(mcuxClEls_InterruptOptionEn_t *result)
Get interrupt enable flags.
+
mcuxClEls_InterruptOptionEn_t::elsint
uint32_t elsint
Whether ELS interrupt should be used. (For possible values of this field, see mcuxClEls_InterruptOpti...
Definition: mcuxClEls_Common.h:307
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00308.html b/components/els_pkc/doc/mcxn/html/a00308.html new file mode 100644 index 000000000..5d79a9fac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00308.html @@ -0,0 +1,351 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Crc.h File Reference
+
+
+ +

ELS header for Command CRC functionality. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_CommandCrcConfig_t
 Type to control ELS Command CRC. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMD_CRC_VALUE_RESET
 Reset the Command CRC to initial value. More...
 
#define MCUXCLELS_CMD_CRC_VALUE_ENABLE
 Enable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_VALUE_DISABLE
 Disable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_RESET
 Reset the Command CRC to initial value. More...
 
#define MCUXCLELS_CMD_CRC_ENABLE
 Enable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_DISABLE
 Disable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_POLYNOMIAL
 CRC polynomial for the Command CRC. More...
 
#define MCUXCLELS_CMD_CRC_INITIAL_VALUE
 Initial value for the Command CRC. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_INIT(crc)
 Initializes a reference CRC variable with the command CRC initial value. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_RESET(crc)
 Resets the given reference CRC variable to the command CRC initial value. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_Init_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_PartialInit_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_UpdateAad_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_UpdateData_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_Finalize_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER(crc, options)
 Updates given reference command CRC with command mcuxClEls_Cipher_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC(crc, options)
 Updates given reference command CRC with command mcuxClEls_Cmac_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccKeyGen_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc)
 Updates given reference command CRC with command mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccVerify_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG(crc)
 Updates given reference command CRC with command mcuxClEls_GlitchDetector_LoadConfig_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM(crc)
 Updates given reference command CRC with command mcuxClEls_GlitchDetector_Trim_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hash_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hmac_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108(crc)
 Updates given reference command CRC with command mcuxClEls_Ckdf_Sp800108_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hkdf_Rfc5869_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C(crc)
 Updates given reference command CRC with command mcuxClEls_Hkdf_Sp80056c_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY(crc)
 Updates given reference command CRC with command mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY(crc)
 Updates given reference command CRC with command mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc)
 Updates given reference command CRC with command mcuxClEls_KeyDelete_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, options)
 Updates given reference command CRC with command mcuxClEls_KeyImport_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT(crc)
 Updates given reference command CRC with command mcuxClEls_KeyExport_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgRequest_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestInstantiate_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesEcb_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesCtr_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigLoad_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER
 ELS Command ID for CIPHER command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER
 ELS Command ID for AUTH_CIPHER command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
 ELS Command ID for CHAL_RESP_GEN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN
 ELS Command ID for ECSIGN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY
 ELS Command ID for ECVFY command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH
 ELS Command ID for ECKXH command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN
 ELS Command ID for KEYGEN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN
 ELS Command ID for KEYIN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT
 ELS Command ID for KEYOUT command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE
 ELS Command ID for KDELETE command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV
 ELS Command ID for KEYPROV command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CKDF
 ELS Command ID for CKDF command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HKDF
 ELS Command ID for HKDF command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_TLS
 ELS Command ID for TLS command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HASH
 ELS Command ID for HASH command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HMAC
 ELS Command ID for HMAC command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CMAC
 ELS Command ID for CMAC command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ
 ELS Command ID for RND_REQ command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST
 ELS Command ID for DRBG_TEST command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
 ELS Command ID for DTRNG_CFG_LOAD command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL
 ELS Command ID for DTRNG_EVAL command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
 ELS Command ID for GDET_CFG_LOAD command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM
 ELS Command ID for GDET_TRIM command. More...
 
+ + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ConfigureCommandCRC (mcuxClEls_CommandCrcConfig_t options)
 Set command CRC flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetCommandCRC (uint32_t *commandCrc)
 Get the current command CRC value. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_VerifyVsRefCRC (uint32_t refCrc)
 Verifies a reference CRC against the computed ELS command CRC. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_UpdateRefCRC (uint8_t command, uint32_t options, uint32_t *refCrc)
 Updates a reference CRC with the parameters of an ELS command. More...
 
+

Detailed Description

+

ELS header for Command CRC functionality.

+

This header exposes functions that support the usage of the Command CRC feature for ELS.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00308.js b/components/els_pkc/doc/mcxn/html/a00308.js new file mode 100644 index 000000000..8de31f201 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00308.js @@ -0,0 +1,70 @@ +var a00308 = +[ + [ "MCUXCLELS_CMD_CRC_VALUE_RESET", "a00720.html#ga4ea6f474882d3641c24d667d3e27705e", null ], + [ "MCUXCLELS_CMD_CRC_VALUE_ENABLE", "a00720.html#ga72aafc14f6c0d2d5566095da8da12836", null ], + [ "MCUXCLELS_CMD_CRC_VALUE_DISABLE", "a00720.html#ga989391a1c889ba01d0324f71e22d9cdb", null ], + [ "MCUXCLELS_CMD_CRC_RESET", "a00720.html#ga223c08e1768387247f660f6ab9b2abd0", null ], + [ "MCUXCLELS_CMD_CRC_ENABLE", "a00720.html#ga30485738143113e3a857d505076c0407", null ], + [ "MCUXCLELS_CMD_CRC_DISABLE", "a00720.html#ga7dd3297a886e126c5c8c461e962b7c1e", null ], + [ "MCUXCLELS_CMD_CRC_POLYNOMIAL", "a00720.html#ga3ae77f6de5efb615e2f9bfe25d65eac5", null ], + [ "MCUXCLELS_CMD_CRC_INITIAL_VALUE", "a00720.html#ga2c5d32e550c9abea8ccc363d1fdb4a46", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_INIT", "a00721.html#ga2e1db01b3d5c51fd02a1e83060732e8c", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_RESET", "a00721.html#ga9ce01bd5d4ea16985fa7b85cc15f2693", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT", "a00721.html#gae6ab0207e4403dcf5c2dcfde753cf655", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT", "a00721.html#gaefec8bc08ee26c21e77b5805ce9b7e60", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD", "a00721.html#ga245c09816fabe02aaaac29346c15be21", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA", "a00721.html#ga54d72bcb4788676fa1abfddfeb0b0500", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE", "a00721.html#gada728bb209a10e78365aaa4165fb1526", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER", "a00721.html#ga1bb77cbf1f29cfac9ca2db5f7b1a0450", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC", "a00721.html#ga064eac834320f9002cbfe9981b4e416f", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN", "a00721.html#gae92dbeb4c44c99edccfe08ebce63d7e7", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE", "a00721.html#ga1e25c3e7350320526b8a46705d9eff7d", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN", "a00721.html#ga625ee41cf33f31eafc17ccc527feeb08", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY", "a00721.html#gab78f59c3466a002a40e3492054725c2c", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG", "a00721.html#ga7ad4439beeb293ebc81605aff8080f06", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM", "a00721.html#ga93bffd65f1138c80e00562ce7c37456a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH", "a00721.html#ga895449214513abfa3882c67be4cae8c1", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC", "a00721.html#gae38cd842c0f20823078a071e4efe6b91", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108", "a00721.html#ga47b490f3b6d5e627188d3130f475afbe", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869", "a00721.html#ga99f07b82231a11b71b66664e9a6cd632", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C", "a00721.html#gaf4580ba34e94564c4f608a55d120ea7b", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY", "a00721.html#gabf4ea11b932e2c372554a38d2b46af10", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY", "a00721.html#ga4767023f07bf0519f9ced9c08931b2db", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE", "a00721.html#ga78802e76c0a21709beb16b4764f395e4", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT", "a00721.html#gafda5328d88ce7cb623fbffe67f3f881a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT", "a00721.html#ga28cfed7894b7923478c183f52020ceec", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST", "a00721.html#gaa579d89877e771f69c92fbd0b3ed5752", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE", "a00721.html#ga57115088afcd2e11f0742426df26c31a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT", "a00721.html#ga26fc4efbe3d744309300fdc73f6a507b", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB", "a00721.html#ga931581b96f1c816a9b4f09ac6d219a68", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR", "a00721.html#ga1aa20023a8871dcf226865cfdc4846b8", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD", "a00721.html#gaabeccb19cfd99a1a83954d7676e792b4", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE", "a00721.html#ga1fef6315409433815a4e64abfb23159f", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CIPHER", "a00722.html#ga2a3c7f74fe04bdbcce0856868ecf44ad", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER", "a00722.html#ga409e1dae95e89fd8ffb127c4f7ed88d2", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN", "a00722.html#ga2fdefdf18f7cb37b74ef2f49daeb7549", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN", "a00722.html#gaeb55615316d2f67abc77976c752a4533", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECVFY", "a00722.html#ga7cd6375c813a4de7d0ec9c9d4209c03a", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECKXH", "a00722.html#ga04f3aa01819a18d5dbcedd795fddbc81", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN", "a00722.html#ga303a52799f5c842e761ae2c8527fb2f3", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYIN", "a00722.html#ga0d49dc33b50bd7db6ca58cb84db936e3", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT", "a00722.html#ga2fccccaeea8e4fb0e31bfa368caf39f7", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KDELETE", "a00722.html#gaf9eadae3c47cdd4df67b150f91d6b30b", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV", "a00722.html#gabaa8a08498f70bcccea59ee5472fe942", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CKDF", "a00722.html#gacc64012f05a991897dc401f526fcc78b", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HKDF", "a00722.html#ga3945648ed569844869fd7eb997e99df9", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_TLS", "a00722.html#gad86358f79337962338035ed5c49cb7ac", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HASH", "a00722.html#ga56f581e908a8889c11d0b916b6d69657", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HMAC", "a00722.html#gab2cc703ff096c3b830019510855001a6", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CMAC", "a00722.html#ga9716ab821ee894a4cd64d0553311da2a", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ", "a00722.html#ga72ff352c60a48b971c0ac0a772180fee", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST", "a00722.html#ga4852767cbb713b107cf8e261fdbe5c17", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD", "a00722.html#ga33f246b5a6c663fd854726fbde6b260d", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL", "a00722.html#gaac8b6cfd8f9bf0bea117371edc80b974", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD", "a00722.html#ga1dfda813fd0917ff50688736159435db", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM", "a00722.html#gab752a820b7f5957518912f67576f3ea8", null ], + [ "mcuxClEls_ConfigureCommandCRC", "a00724.html#ga4aaabd203c6c81a042bc4f3739ae8408", null ], + [ "mcuxClEls_GetCommandCRC", "a00724.html#gaf91caa2b1230676e9beedaa0eba442eb", null ], + [ "mcuxClEls_VerifyVsRefCRC", "a00724.html#ga5ebf64e6470c7a08c56ee44d9afe3990", null ], + [ "mcuxClEls_UpdateRefCRC", "a00724.html#gae04ed3290d9cb48f42f4f9aed4b1a825", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00308_source.html b/components/els_pkc/doc/mcxn/html/a00308_source.html new file mode 100644 index 000000000..9456ea896 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00308_source.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Crc.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLELS_CRC_H_
27 #define MCUXCLELS_CRC_H_
28 
29 #include <mcuxClConfig.h> // Exported features flags header
30 #include <mcuxClEls_Types.h> // Common types
31 #include <mcuxCsslFlowProtection.h>
32 #include <mcuxClCore_FunctionIdentifiers.h>
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /**********************************************
39  * CONSTANTS
40  **********************************************/
53 #define MCUXCLELS_CMD_CRC_VALUE_RESET ((uint32_t) 0x1u)
54 #define MCUXCLELS_CMD_CRC_VALUE_ENABLE ((uint32_t) 0x2u)
55 #define MCUXCLELS_CMD_CRC_VALUE_DISABLE ((uint32_t) 0x0u)
56 
57 #define MCUXCLELS_CMD_CRC_RESET ((uint32_t) 0x1u)
58 #define MCUXCLELS_CMD_CRC_ENABLE ((uint32_t) 0x1u)
59 #define MCUXCLELS_CMD_CRC_DISABLE ((uint32_t) 0x0u)
60 
61 #define MCUXCLELS_CMD_CRC_POLYNOMIAL ((uint32_t) 0x04C11DB7u)
62 #define MCUXCLELS_CMD_CRC_INITIAL_VALUE ((uint32_t) 0xA5A5A5A5u)
63 
76 #define MCUXCLELS_CMD_CRC_REFERENCE_INIT(crc) \
77  uint32_t (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE
78 
82 #define MCUXCLELS_CMD_CRC_REFERENCE_RESET(crc) \
83  (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE
84 
88 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
89 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options) \
90  ({ \
91  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \
92  (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE; \
93  (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE; \
94  (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \
95  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
96  (retVal); \
97  })
98 #else
99 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options) \
100  ({ \
101  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \
102  (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE; \
103  (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE; \
104  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
105  (retVal); \
106  })
107 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
108 
112 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
113 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options) \
114  ({ \
115  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \
116  (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \
117  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
118  (retVal); \
119  })
120 #else
121 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options) \
122  ({ \
123  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \
124  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
125  (retVal); \
126  })
127 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
128 
132 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
133 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options) \
134  ({ \
135  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC \
136  (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \
137  (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \
138  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
139  (retVal); \
140  })
141 #else
142 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options) \
143  ({ \
144  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC; \
145  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
146  (retVal); \
147  })
148 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
149 
153 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
154 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options) \
155  ({ \
156  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC \
157  (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \
158  (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \
159  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
160  (retVal); \
161  })
162 #else
163 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options) \
164  ({ \
165  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC; \
166  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
167  (retVal); \
168  })
169 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
170 
174 #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS
175 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options) \
176  ({ \
177  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL \
178  (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \
179  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
180  (retVal); \
181  })
182 #else
183 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options) \
184  ({ \
185  (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL; \
186  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \
187  (retVal); \
188  })
189 #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */
190 
194 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER(crc, options) \
195  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CIPHER, (options).word.value, &(crc))
196 
200 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC(crc, options) \
201  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CMAC, (options).word.value, &(crc))
202 
203 
207 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN(crc, options) \
208  ({ \
209  (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
210  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN, (options).word.value, &(crc)); \
211  (retVal); \
212  })
213 
217 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
218 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc) \
219  ({ \
220  mcuxClEls_EccKeyExchOption_t options = {0u}; \
221  options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
222  options.bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; \
223  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \
224  (retVal); \
225  })
226 #else
227 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc) \
228  ({ \
229  mcuxClEls_EccKeyExchOption_t options = {0u}; \
230  options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
231  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \
232  (retVal); \
233  })
234 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
235 
236 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
237 
240 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT(crc) \
241  ({ \
242  mcuxClEls_EccKeyExchOption_t options = {0u}; \
243  options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
244  options.bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; \
245  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \
246  (retVal); \
247  })
248 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
249 
253 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN(crc, options) \
254  ({ \
255  (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
256  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN, (options).word.value, &(crc)); \
257  (retVal); \
258  })
259 
263 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
264 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options) \
265  ({ \
266  (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
267  (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; \
268  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
269  (retVal); \
270  })
271 #else
272 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options) \
273  ({ \
274  (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
275  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
276  (retVal); \
277  })
278 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
279 
280 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
281 
284 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT(crc, options) \
285  ({ \
286  (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \
287  (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; \
288  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \
289  (retVal); \
290  })
291 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
292 
296 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG(crc) \
297  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD, 0u, &(crc))
298 
302 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM(crc) \
303  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM, 0u, &(crc))
304 
308 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH(crc, options) \
309  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HASH, (options).word.value, &(crc))
310 
314 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC(crc, options) \
315  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HMAC, (options).word.value, &(crc))
316 
320 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108(crc) \
321  ({ \
322  mcuxClEls_CkdfOption_t options = {0u}; \
323  options.bits.ckdf_algo = MCUXCLELS_CKDF_ALGO_SP800108; \
324  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CKDF, options.word.value, &(crc)); \
325  (retVal); \
326  })
327 
328 
332 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869(crc, options) \
333  ({ \
334  (options).bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_RFC5869; \
335  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, (options).word.value, &(crc)); \
336  (retVal); \
337  })
338 
342 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C(crc) \
343  ({ \
344  mcuxClEls_HkdfOption_t options = {0u}; \
345  options.bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_SP80056C; \
346  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, options.word.value, &(crc)); \
347  (retVal); \
348  })
349 
353 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY(crc) \
354  ({ \
355  mcuxClEls_TlsOption_t options = {0u}; \
356  options.bits.mode = MCUXCLELS_TLS_INIT; \
357  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc)); \
358  (retVal); \
359  })
360 
364 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY(crc) \
365  ({ \
366  mcuxClEls_TlsOption_t options = {0u}; \
367  options.bits.mode = MCUXCLELS_TLS_FINALIZE; \
368  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc)); \
369  (retVal); \
370  })
371 
375 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc) \
376  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KDELETE, 0u, &(crc))
377 
378 
379 
383 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, options) \
384  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, (options).word.value, &(crc))
385 
386 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
387 
390 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK(crc) \
391  ({ \
392  mcuxClEls_KeyImportOption_t options = {0u}; \
393  options.bits.revf = MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE; \
394  options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_PBK; \
395  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, options.word.value, &(crc)); \
396  (retVal); \
397  })
398 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
399 
403 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT(crc) \
404  ({ \
405  mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT, 0u, &(crc)); \
406  mcuxClEls_KeyImportOption_t import_options = {0u}; \
407  import_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394; \
408  retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc); \
409  retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, import_options); \
410  (retVal); \
411  })
412 
416 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST(crc) \
417  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, 0u, &(crc))
418 
419 #ifdef MCUXCL_FEATURE_ELS_RND_RAW
420 
423 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW(crc) \
424  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_RND_RAW, &(crc))
425 #endif /* MCUXCL_FEATURE_ELS_RND_RAW */
426 
430 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE(crc) \
431  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE, &(crc))
432 
436 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT(crc) \
437  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT, &(crc))
438 
442 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB(crc) \
443  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB, &(crc))
444 
448 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR(crc) \
449  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR, &(crc))
450 
454 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD(crc) \
455  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD, 0u, &(crc))
456 
460 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE(crc) \
461  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL, 0u, &(crc))
462 
463 #ifdef MCUXCL_FEATURE_ELS_PRND_INIT
464 
467 #define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT(crc) \
468  mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_PRND_INIT, &(crc))
469 #endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
470 
480 #define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER 0
481 #define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER 1
482 #define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN 3
483 #define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN 4
484 #define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY 5
485 #define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH 6
486 #define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN 8
487 #define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN 9
488 #define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT 10
489 #define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE 11
490 #define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV 12
491 #define MCUXCLELS_CMD_CRC_CMD_ID_CKDF 16
492 #define MCUXCLELS_CMD_CRC_CMD_ID_HKDF 17
493 #define MCUXCLELS_CMD_CRC_CMD_ID_TLS 18
494 #define MCUXCLELS_CMD_CRC_CMD_ID_HASH 20
495 #define MCUXCLELS_CMD_CRC_CMD_ID_HMAC 21
496 #define MCUXCLELS_CMD_CRC_CMD_ID_CMAC 22
497 #define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ 24
498 #define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST 25
499 #define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD 28
500 #define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL 29
501 #define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD 30
502 #define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM 31
503 
509 /**********************************************
510  * TYPEDEFS
511  **********************************************/
512 
522 typedef union
523 {
524  struct
525  {
526  uint32_t value;
527  } word;
528  struct
529  {
530  uint32_t reset :1;
531  uint32_t enable :1;
532  uint32_t : 30;
533  } bits;
534 } mcuxClEls_CommandCrcConfig_t;
535 
540 /**********************************************
541  * FUNCTIONS
542  **********************************************/
561 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ConfigureCommandCRC)
562 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ConfigureCommandCRC(
563  mcuxClEls_CommandCrcConfig_t options
564  );
565 
581 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetCommandCRC)
582 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetCommandCRC(
583  uint32_t* commandCrc
584  );
585 
597 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_VerifyVsRefCRC)
598 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_VerifyVsRefCRC(
599  uint32_t refCrc
600  );
601 
620 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_UpdateRefCRC)
621 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_UpdateRefCRC(
622  uint8_t command,
623  uint32_t options,
624  uint32_t* refCrc
625  );
626 
627 #ifdef __cplusplus
628 } /* extern "C" */
629 #endif
630 
631 #endif /* MCUXCLELS_CRC_H_ */
632 
mcuxClEls_ConfigureCommandCRC
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ConfigureCommandCRC(mcuxClEls_CommandCrcConfig_t options)
Set command CRC flags.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClEls_CommandCrcConfig_t::enable
uint32_t enable
Enable/Disable update of Command CRC value by executing commands, set with MCUXCLELS_CMD_CRC_ENABLE /...
Definition: mcuxClEls_Crc.h:531
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_UpdateRefCRC
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_UpdateRefCRC(uint8_t command, uint32_t options, uint32_t *refCrc)
Updates a reference CRC with the parameters of an ELS command.
+
mcuxClEls_Types.h
ELS type header.
+
mcuxClEls_CommandCrcConfig_t::reset
uint32_t reset
Reset the Command CRC to initial value, set by MCUXCLELS_CMD_CRC_RESET.
Definition: mcuxClEls_Crc.h:530
+
mcuxClEls_CommandCrcConfig_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Crc.h:526
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_CommandCrcConfig_t
Type to control ELS Command CRC.
Definition: mcuxClEls_Crc.h:522
+
mcuxClEls_VerifyVsRefCRC
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_VerifyVsRefCRC(uint32_t refCrc)
Verifies a reference CRC against the computed ELS command CRC.
+
mcuxClEls_GetCommandCRC
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetCommandCRC(uint32_t *commandCrc)
Get the current command CRC value.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00311.html b/components/els_pkc/doc/mcxn/html/a00311.html new file mode 100644 index 000000000..f6688f14e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00311.html @@ -0,0 +1,276 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc.h File Reference + + + + + + + + + + + + + + + + +
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Data Structures | +Macros | +Typedefs | +Functions
+
+
mcuxClEls_Ecc.h File Reference
+
+
+ +

ELS header for elliptic curve cryptography This header exposes functions that enable using the ELS for elliptic curve cryptography. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Data Structures

union  mcuxClEls_EccSignOption_t
 Command option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async. More...
 
union  mcuxClEls_EccVerifyOption_t
 Command option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOption_t. More...
 
union  mcuxClEls_EccKeyGenOption_t
 Command option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOption_t. More...
 
union  mcuxClEls_EccKeyExchOption_t
 Command option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only. More...
 
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+Macros

#define MCUXCLELS_ECC_VALUE_HASHED
 Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the hash of the message. More...
 
#define MCUXCLELS_ECC_VALUE_NOT_HASHED
 Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the plain message. More...
 
#define MCUXCLELS_ECC_VALUE_RTF
 Set this option at mcuxClEls_EccSignOption_t.value to include the RTF in the signature, only for mcuxClEls_EccSignOption_t. More...
 
#define MCUXCLELS_ECC_VALUE_NO_RTF
 Set this option at mcuxClEls_EccSignOption_t.value to not include the RTF in the signature, only for mcuxClEls_EccSignOption_t. More...
 
#define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to sign the public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a signing key usable by mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is deterministic. More...
 
#define MCUXCLELS_KEYGEN_VALUE_RANDOM
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is random. More...
 
#define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to generate a public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to not generate a public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.value to not use random data for signing the public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.value to use random data for signing the public key. More...
 
#define MCUXCLELS_ECC_HASHED
 Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the hash of the message. More...
 
#define MCUXCLELS_ECC_NOT_HASHED
 Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the plain message. More...
 
#define MCUXCLELS_ECC_RTF
 Set this option at mcuxClEls_EccSignOption_t.signrtf to include the RTF in the signature. More...
 
#define MCUXCLELS_ECC_NO_RTF
 Set this option at mcuxClEls_EccSignOption_t.signrtf to not include the RTF in the signature. More...
 
#define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to sign the public key (signature will be concatenated to the output public key) More...
 
#define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to not sign the public key. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_SIGN
 Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a signing key usable by mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is deterministic. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_RANDOM
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is random. More...
 
#define MCUXCLELS_ECC_GEN_PUBLIC_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to generate a public key. More...
 
#define MCUXCLELS_ECC_SKIP_PUBLIC_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to not generate a public key. More...
 
#define MCUXCLELS_ECC_NO_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to not include user provided random data for the signature. More...
 
#define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to include user provided random data for the signature. More...
 
#define MCUXCLELS_ECC_REVERSEFETCH_ENABLE
 Reverse Fetch enabled. For internal use. More...
 
#define MCUXCLELS_ECC_REVERSEFETCH_DISABLE
 Reverse Fetch disabled. For internal use. More...
 
#define MCUXCLELS_ECC_PUBLICKEY_SIZE
 Size of the public key. More...
 
#define MCUXCLELS_ECC_SIGNATURE_SIZE
 Size of the signature. More...
 
#define MCUXCLELS_ECC_SIGNATURE_R_SIZE
 Size of the signature part r. More...
 
+ + + + +

+Typedefs

typedef uint8_t mcuxClEls_EccByte_t
 Data type for ECC parameters in ELS format. More...
 
+ + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyGen_Async (mcuxClEls_EccKeyGenOption_t options, mcuxClEls_KeyIndex_t signingKeyIdx, mcuxClEls_KeyIndex_t privateKeyIdx, mcuxClEls_KeyProp_t generatedKeyProperties, uint8_t const *pRandomData, uint8_t *pPublicKey)
 Generates an ECC key pair on the NIST P-256 curve. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyExchange_Async (mcuxClEls_KeyIndex_t privateKeyIdx, uint8_t const *pPublicKey, mcuxClEls_KeyIndex_t sharedSecretIdx, mcuxClEls_KeyProp_t sharedSecretProperties)
 Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public key. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccSign_Async (mcuxClEls_EccSignOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t *pOutput)
 Generates an ECDSA signature of a given message. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccVerify_Async (mcuxClEls_EccVerifyOption_t options, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t const *pSignatureAndPubKey, uint8_t *pOutput)
 Verifies an ECDSA signature of a given message. More...
 
+

Detailed Description

+

ELS header for elliptic curve cryptography This header exposes functions that enable using the ELS for elliptic curve cryptography.

+

All functions operate on the NIST P-256 curve. The ECC operations supported are:

    +
  • ECC key generation
    • +
  • ECC Diffie-Hellman key exchange
    • +
  • ECDSA signature generation/verification
    • +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00311.js b/components/els_pkc/doc/mcxn/html/a00311.js new file mode 100644 index 000000000..9bf12400b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00311.js @@ -0,0 +1,40 @@ +var a00311 = +[ + [ "MCUXCLELS_ECC_VALUE_HASHED", "a00727.html#gac3be2289b4247767251a8d85014652bb", null ], + [ "MCUXCLELS_ECC_VALUE_NOT_HASHED", "a00727.html#ga90e38c2c9caeb976594c32d92bbc5d05", null ], + [ "MCUXCLELS_ECC_VALUE_RTF", "a00727.html#ga48a69913a0b9d082ea72b81f56ac1fdc", null ], + [ "MCUXCLELS_ECC_VALUE_NO_RTF", "a00727.html#ga66a8fbee1f549d2ad1819c0e08780e13", null ], + [ "MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY", "a00728.html#ga916703c91887cb429f5fc3c9f3f039c9", null ], + [ "MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN", "a00728.html#ga7bf099956f1b0d5e9b24a654023f28b7", null ], + [ "MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE", "a00728.html#ga9263040a043abb0bfaf51fb16ba270e5", null ], + [ "MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC", "a00728.html#gabbd15e28f3e551acbc9b786a52bfd238", null ], + [ "MCUXCLELS_KEYGEN_VALUE_RANDOM", "a00728.html#ga8bc95eb09238ba6e3716109472fe6c86", null ], + [ "MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY", "a00728.html#ga4a2e708b9f9c46037356e2f4c6ab662b", null ], + [ "MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY", "a00728.html#gaa98c6e65867abd8ae959c9771eefcbe6", null ], + [ "MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA", "a00728.html#ga73dea3b73d48e7b74ba484bb8278e110", null ], + [ "MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA", "a00728.html#gaf9df52529671dea7267c60318bcfc3ec", null ], + [ "MCUXCLELS_ECC_HASHED", "a00729.html#gafad38c505a64137b0283ad96c144c503", null ], + [ "MCUXCLELS_ECC_NOT_HASHED", "a00729.html#ga871f176b3998d9b5dd709d5a6e2585bd", null ], + [ "MCUXCLELS_ECC_RTF", "a00729.html#ga04c77ad43887a66b1b8df87cb9258981", null ], + [ "MCUXCLELS_ECC_NO_RTF", "a00729.html#gae7ffc3999117e1796727bd7700d88745", null ], + [ "MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE", "a00730.html#ga9b6bd96ac94ff7bd763b9b9d057d139f", null ], + [ "MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE", "a00730.html#gaf73a03883462465c3cabb2257981fc5f", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_SIGN", "a00730.html#gacff4169a4b48ee6c6e8ac13e2ea025ab", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE", "a00730.html#gabc39d5811bcaba4278e1f9c4874527ae", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC", "a00730.html#ga8cdc8f5c722207aaef7fef9fd0cc3837", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_RANDOM", "a00730.html#ga67348b1833c0bfaccbe334c2cb68b448", null ], + [ "MCUXCLELS_ECC_GEN_PUBLIC_KEY", "a00730.html#gac67abe2d5052f753cc5f5aca24663066", null ], + [ "MCUXCLELS_ECC_SKIP_PUBLIC_KEY", "a00730.html#gacbb5ce65a2ad59ec7a6709059f94426f", null ], + [ "MCUXCLELS_ECC_NO_RANDOM_DATA", "a00730.html#ga10f155f1020130f0b9c952f6df52c784", null ], + [ "MCUXCLELS_ECC_INCLUDE_RANDOM_DATA", "a00730.html#gadcb581867b97e3c3988125eddc5f24e3", null ], + [ "MCUXCLELS_ECC_REVERSEFETCH_ENABLE", "a00731.html#ga0536723a417500b946e92b6432d0a4fd", null ], + [ "MCUXCLELS_ECC_REVERSEFETCH_DISABLE", "a00731.html#ga92e6bbdd8cdd2d0ed90e6073e94924df", null ], + [ "MCUXCLELS_ECC_PUBLICKEY_SIZE", "a00732.html#ga7298491d4e2d679496d0bacab6f351f8", null ], + [ "MCUXCLELS_ECC_SIGNATURE_SIZE", "a00732.html#ga922fa06cbacda443d50f2b3c29fdea8c", null ], + [ "MCUXCLELS_ECC_SIGNATURE_R_SIZE", "a00732.html#ga18a35b4e98dac7862895339b720d667a", null ], + [ "mcuxClEls_EccByte_t", "a00733.html#gaaca57cf87336b1e866852443c47a019f", null ], + [ "mcuxClEls_EccKeyGen_Async", "a00734.html#ga060362493427031ef51110b7c381a986", null ], + [ "mcuxClEls_EccKeyExchange_Async", "a00734.html#ga39d6102bd9c792eb5a2e33af1f1830c3", null ], + [ "mcuxClEls_EccSign_Async", "a00734.html#ga96b17fadb9ee18906bb719e222908209", null ], + [ "mcuxClEls_EccVerify_Async", "a00734.html#ga019a066eda05dab4955ed76e83d39b77", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00311_source.html b/components/els_pkc/doc/mcxn/html/a00311_source.html new file mode 100644 index 000000000..530382c7a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00311_source.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Ecc.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLELS_ECC_H_
27 #define MCUXCLELS_ECC_H_
28 
29 #include <mcuxClConfig.h> // Exported features flags header
30 #include <mcuxClEls_Common.h> // Common types & functionality
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
44 /**********************************************
45  * CONSTANTS
46  **********************************************/
60 #define MCUXCLELS_ECC_VALUE_HASHED ((uint32_t) 0u<< 0u)
61 #define MCUXCLELS_ECC_VALUE_NOT_HASHED ((uint32_t) 1u<< 0u)
62 #define MCUXCLELS_ECC_VALUE_RTF ((uint32_t) 1u<< 1u)
63 #define MCUXCLELS_ECC_VALUE_NO_RTF ((uint32_t) 0u<< 1u)
64 
74 #define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY ((uint32_t) 1u<< 0u)
75 #define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN ((uint32_t) 0u<< 1u)
76 #define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE ((uint32_t) 1u<< 1u)
77 #define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC ((uint32_t) 0u<< 2u)
78 #define MCUXCLELS_KEYGEN_VALUE_RANDOM ((uint32_t) 1u<< 2u)
79 #define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY ((uint32_t) 0u<< 3u)
80 #define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY ((uint32_t) 1u<< 3u)
81 #define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA ((uint32_t) 0u<< 5u)
82 #define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA ((uint32_t) 1u<< 5u)
83 
93 #define MCUXCLELS_ECC_HASHED ((uint32_t) 0U)
94 #define MCUXCLELS_ECC_NOT_HASHED ((uint32_t) 1U)
95 
96 #define MCUXCLELS_ECC_RTF ((uint32_t) 1U)
97 #define MCUXCLELS_ECC_NO_RTF ((uint32_t) 0U)
98 
108 #define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE 1U
109 #define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE 0U
110 
111 #define MCUXCLELS_ECC_OUTPUTKEY_SIGN 0U
112 #define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE 1U
113 
114 #define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC 0U
115 #define MCUXCLELS_ECC_OUTPUTKEY_RANDOM 1U
116 
117 #define MCUXCLELS_ECC_GEN_PUBLIC_KEY 0U
118 #define MCUXCLELS_ECC_SKIP_PUBLIC_KEY 1U
119 
121 #define MCUXCLELS_ECC_NO_RANDOM_DATA 0U
122 #define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA 1U
123 
134 #define MCUXCLELS_ECC_REVERSEFETCH_ENABLE (0x01U)
135 #define MCUXCLELS_ECC_REVERSEFETCH_DISABLE (0x00U)
136 
137 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
138 #define MCUXCLELS_ECC_EXTKEY_EXTERNAL (0x01U)
139 #define MCUXCLELS_ECC_EXTKEY_INTERNAL (0x00U)
140 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
141 
151 #define MCUXCLELS_ECC_PUBLICKEY_SIZE ((size_t) 64U)
152 #define MCUXCLELS_ECC_SIGNATURE_SIZE ((size_t) 64U)
153 #define MCUXCLELS_ECC_SIGNATURE_R_SIZE ((size_t) 32U)
154  /* mcuxClEls_Ecc_Macros */
161 
162 
163 /**********************************************
164  * TYPEDEFS
165  **********************************************/
177 typedef uint8_t mcuxClEls_EccByte_t;
178 
183 typedef union
184 {
185  struct
186  {
187  uint32_t value;
188  } word;
189  struct
190  {
191  uint32_t echashchl :1;
192  uint32_t signrtf :1;
193  uint32_t :2;
194  uint32_t revf :1;
195  uint32_t :27;
196  } bits;
197 } mcuxClEls_EccSignOption_t;
198 
203 typedef union
204 {
205  struct
206  {
207  uint32_t value;
208  } word;
209  struct
210  {
211  uint32_t echashchl :1;
212  uint32_t :3;
213  uint32_t revf :1;
214 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT
215  uint32_t :8;
216  uint32_t extkey :1;
217  uint32_t :18;
218 #else
219  uint32_t :27;
220 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */
221  } bits;
222 } mcuxClEls_EccVerifyOption_t;
223 
228 typedef union
229 {
230  struct
231  {
232  uint32_t value;
233  } word;
234  struct
235  {
236  uint32_t kgsign :1;
237  uint32_t kgtypedh :1;
238  uint32_t kgsrc :1;
239  uint32_t skip_pbk :1;
240  uint32_t revf :1;
241  uint32_t kgsign_rnd :1;
242  uint32_t :26;
243  } bits;
244 } mcuxClEls_EccKeyGenOption_t;
245 
250 typedef union
251 {
252  struct
253  {
254  uint32_t value;
255  } word;
256  struct
257  {
258  uint32_t :4;
259  uint32_t revf :1;
260  uint32_t :8;
261  uint32_t extkey :1;
262  uint32_t :18;
263  } bits;
264 } mcuxClEls_EccKeyExchOption_t;
265  /* mcuxClEls_Ecc_Types */
269 
270 
271 /**********************************************
272  * FUNCTIONS
273  **********************************************/
319 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyGen_Async)
320 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyGen_Async(
321  mcuxClEls_EccKeyGenOption_t options,
322  mcuxClEls_KeyIndex_t signingKeyIdx,
323  mcuxClEls_KeyIndex_t privateKeyIdx,
324  mcuxClEls_KeyProp_t generatedKeyProperties,
325  uint8_t const * pRandomData,
326  uint8_t * pPublicKey
327  );
328 
360 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchange_Async)
361 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchange_Async(
362  mcuxClEls_KeyIndex_t privateKeyIdx,
363  uint8_t const * pPublicKey,
364  mcuxClEls_KeyIndex_t sharedSecretIdx,
365  mcuxClEls_KeyProp_t sharedSecretProperties
366  );
367 
368 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
369 
390 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchangeInt_Async)
391 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchangeInt_Async(
392  mcuxClEls_KeyIndex_t privateKeyIdx,
393  mcuxClEls_KeyIndex_t publicKeyIdx,
394  mcuxClEls_KeyIndex_t sharedSecretIdx,
395  mcuxClEls_KeyProp_t sharedSecretProperties
396  );
397 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
398 
443 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccSign_Async)
444 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccSign_Async(
445  mcuxClEls_EccSignOption_t options,
446  mcuxClEls_KeyIndex_t keyIdx,
447  uint8_t const * pInputHash,
448  uint8_t const * pInputMessage,
449  size_t inputMessageLength,
450  uint8_t * pOutput
451  );
452 
505 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerify_Async)
506 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerify_Async(
507  mcuxClEls_EccVerifyOption_t options,
508  uint8_t const * pInputHash,
509  uint8_t const * pInputMessage,
510  size_t inputMessageLength,
511  uint8_t const * pSignatureAndPubKey,
512  uint8_t * pOutput
513  );
514 
515 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
516 
568 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerifyInt_Async)
569 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerifyInt_Async(
570  mcuxClEls_EccVerifyOption_t options,
571  mcuxClEls_KeyIndex_t publicKeyIdx,
572  uint8_t const * pInputHash,
573  uint8_t const * pInputMessage,
574  size_t inputMessageLength,
575  uint8_t const * pSignature,
576  uint8_t * pOutput
577  );
578 
579 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
580  /* mcuxClEls_Ecc_Functions */
584  /* mcuxClEls_Ecc */
588 
589 #ifdef __cplusplus
590 } /* extern "C" */
591 #endif
592 
593 #endif /* MCUXCLELS_ECC_H_ */
mcuxClEls_EccKeyExchOption_t
Command option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only.
Definition: mcuxClEls_Ecc.h:250
+
mcuxClEls_EccSignOption_t::value
uint32_t value
Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (S...
Definition: mcuxClEls_Ecc.h:187
+
mcuxClEls_EccSignOption_t::signrtf
uint32_t signrtf
Define if signing the Run-Time Fingerprint.
Definition: mcuxClEls_Ecc.h:192
+
mcuxClEls_EccKeyGenOption_t::kgsign_rnd
uint32_t kgsign_rnd
Define if using user provided random data for the signature.
Definition: mcuxClEls_Ecc.h:241
+
mcuxClEls_EccKeyGenOption_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYG...
Definition: mcuxClEls_Ecc.h:232
+
mcuxClEls_EccKeyGen_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyGen_Async(mcuxClEls_EccKeyGenOption_t options, mcuxClEls_KeyIndex_t signingKeyIdx, mcuxClEls_KeyIndex_t privateKeyIdx, mcuxClEls_KeyProp_t generatedKeyProperties, uint8_t const *pRandomData, uint8_t *pPublicKey)
Generates an ECC key pair on the NIST P-256 curve.
+
mcuxClEls_EccKeyGenOption_t::kgtypedh
uint32_t kgtypedh
Define the usage of the output key.
Definition: mcuxClEls_Ecc.h:237
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_EccKeyExchange_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyExchange_Async(mcuxClEls_KeyIndex_t privateKeyIdx, uint8_t const *pPublicKey, mcuxClEls_KeyIndex_t sharedSecretIdx, mcuxClEls_KeyProp_t sharedSecretProperties)
Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public ke...
+
mcuxClEls_EccKeyExchOption_t::extkey
uint32_t extkey
This field is managed internally.
Definition: mcuxClEls_Ecc.h:261
+
mcuxClEls_EccKeyGenOption_t::revf
uint32_t revf
This field is managed internally.
Definition: mcuxClEls_Ecc.h:240
+
mcuxClEls_EccKeyGenOption_t::skip_pbk
uint32_t skip_pbk
Define if generating a public key.
Definition: mcuxClEls_Ecc.h:239
+
mcuxClEls_EccSign_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccSign_Async(mcuxClEls_EccSignOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t *pOutput)
Generates an ECDSA signature of a given message.
+
mcuxClEls_EccKeyGenOption_t
Command option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOpti...
Definition: mcuxClEls_Ecc.h:228
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_EccKeyExchOption_t::revf
uint32_t revf
This field is managed internally.
Definition: mcuxClEls_Ecc.h:259
+
mcuxClEls_EccKeyExchOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Ecc.h:254
+
mcuxClEls_EccKeyGenOption_t::kgsign
uint32_t kgsign
Define if signing the output public key.
Definition: mcuxClEls_Ecc.h:236
+
mcuxClEls_EccVerifyOption_t::revf
uint32_t revf
This field is managed internally.
Definition: mcuxClEls_Ecc.h:213
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_EccVerifyOption_t::echashchl
uint32_t echashchl
Define type of input, plain message or hash of message.
Definition: mcuxClEls_Ecc.h:211
+
mcuxClEls_EccVerifyOption_t::value
uint32_t value
Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (S...
Definition: mcuxClEls_Ecc.h:207
+
mcuxClEls_EccByte_t
uint8_t mcuxClEls_EccByte_t
Data type for ECC parameters in ELS format.
Definition: mcuxClEls_Ecc.h:177
+
mcuxClEls_EccVerifyOption_t
Command option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOpti...
Definition: mcuxClEls_Ecc.h:203
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_EccSignOption_t
Command option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async.
Definition: mcuxClEls_Ecc.h:183
+
mcuxClEls_EccKeyGenOption_t::kgsrc
uint32_t kgsrc
Define if the output key is deterministic or random.
Definition: mcuxClEls_Ecc.h:238
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClEls_EccVerify_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccVerify_Async(mcuxClEls_EccVerifyOption_t options, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t const *pSignatureAndPubKey, uint8_t *pOutput)
Verifies an ECDSA signature of a given message.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_EccSignOption_t::echashchl
uint32_t echashchl
Define type of input, plain message or hash of message.
Definition: mcuxClEls_Ecc.h:191
+
mcuxClEls_EccSignOption_t::revf
uint32_t revf
This field is managed internally.
Definition: mcuxClEls_Ecc.h:194
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00314.html b/components/els_pkc/doc/mcxn/html/a00314.html new file mode 100644 index 000000000..24a2d652d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00314.html @@ -0,0 +1,244 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
+ +
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+
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+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Hash.h File Reference
+
+
+ +

ELS header for hashing. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_HashOption_t
 Command option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_HASH_INIT_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashini to initialize the hash. More...
 
#define MCUXCLELS_HASH_INIT_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashini to continue the hash. More...
 
#define MCUXCLELS_HASH_LOAD_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashld to load the hash state from pDigest. More...
 
#define MCUXCLELS_HASH_LOAD_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashld to not load the hash state. More...
 
#define MCUXCLELS_HASH_OUTPUT_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashoe to output the hash to pDigest. More...
 
#define MCUXCLELS_HASH_OUTPUT_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashoe to not output the hash. More...
 
#define MCUXCLELS_HASH_RTF_UPDATE_ENABLE
 Set this option at mcuxClEls_HashOption_t.rtfupd to update the run-time fingerprint (only supported by mcuxClEls_Hash_Async) More...
 
#define MCUXCLELS_HASH_RTF_UPDATE_DISABLE
 Set this option at mcuxClEls_HashOption_t.rtfupd to not update the run-time fingerprint. More...
 
#define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE
 Set this option at mcuxClEls_HashOption_t.rtfoe to output the run-time fingerprint (only supported by mcuxClEls_Hash_Async) More...
 
#define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE
 Set this option at mcuxClEls_HashOption_t.rtfoe to not output the run-time fingerprint. More...
 
#define MCUXCLELS_HASH_MODE_SHA_224
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-224. More...
 
#define MCUXCLELS_HASH_MODE_SHA_256
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-256. More...
 
#define MCUXCLELS_HASH_MODE_SHA_384
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-384. More...
 
#define MCUXCLELS_HASH_MODE_SHA_512
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-512. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_224
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-224. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_256
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-256. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_384
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-384. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_512
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-512. More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224
 SHA-224 output size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256
 SHA-256 output size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384
 SHA-384 output size: 1024 bit (128 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512
 SHA-512 output size: 1024 bit (128 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_224
 SHA-224 state size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_256
 SHA-256 state size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_384
 SHA-384 state size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_512
 SHA-512 state size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224
 SHA-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256
 SHA-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384
 SHA-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512
 SHA-512 output size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_RTF_OUTPUT_SIZE
 
+ + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hash_Async (mcuxClEls_HashOption_t options, uint8_t const *pInput, size_t inputLength, uint8_t *pDigest)
 Computes the hash of a message. More...
 
+

Detailed Description

+

ELS header for hashing.

+

This header exposes functions that enable using the ELS for hashing. There are two modes to hash a message: The asynchronous way as an ELS command, and the SHA-Direct mode which feeds data to the internal registers of the ELS and is synchronous (blocking). The SHA-Direct mode is meant to be used when another command should be executed in parallel on the ELS while the hash operation is still ongoing. For this, use the DMA callback option in #mcuxClEls_Hash_ShaDirect.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00314.js b/components/els_pkc/doc/mcxn/html/a00314.js new file mode 100644 index 000000000..1bf79c3ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00314.js @@ -0,0 +1,35 @@ +var a00314 = +[ + [ "MCUXCLELS_HASH_INIT_ENABLE", "a00737.html#ga77bb4f8fa18f9e15f8a062c996aaa8b7", null ], + [ "MCUXCLELS_HASH_INIT_DISABLE", "a00737.html#gae4ee87c1b75f1f1b0499c55e32362314", null ], + [ "MCUXCLELS_HASH_LOAD_ENABLE", "a00737.html#gae826483f63146be0fcf0c06c132096ec", null ], + [ "MCUXCLELS_HASH_LOAD_DISABLE", "a00737.html#ga149c6d67f2f81c94d931660a041ea02a", null ], + [ "MCUXCLELS_HASH_OUTPUT_ENABLE", "a00737.html#gaba86f7cd657db104d355d74840eb4d42", null ], + [ "MCUXCLELS_HASH_OUTPUT_DISABLE", "a00737.html#gaedcd4ce245169a7375f96e7fb68c6bb8", null ], + [ "MCUXCLELS_HASH_RTF_UPDATE_ENABLE", "a00737.html#ga1aeb9d00c3be6bbbdb6421655f3b0c78", null ], + [ "MCUXCLELS_HASH_RTF_UPDATE_DISABLE", "a00737.html#ga403f2e98211fbc346b618654f9cbfaf2", null ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_ENABLE", "a00737.html#ga5a22b37440c5513f49344f7fabb8537b", null ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_DISABLE", "a00737.html#gad1029c2f42df24f540d1d5ff7b3eaa2d", null ], + [ "MCUXCLELS_HASH_MODE_SHA_224", "a00737.html#gaf65949fa7e4326a043629a163a7b49d1", null ], + [ "MCUXCLELS_HASH_MODE_SHA_256", "a00737.html#gadc8c733440eb2908d653e3647f650072", null ], + [ "MCUXCLELS_HASH_MODE_SHA_384", "a00737.html#gaff4d85496f5f770b803a8b4643665d5e", null ], + [ "MCUXCLELS_HASH_MODE_SHA_512", "a00737.html#gaff0fe735de78d7fb9bb090b82167e47e", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_224", "a00737.html#ga55483aa09654820ae31a84aae32e1b37", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_256", "a00737.html#ga3a02725bdd6679e1354b9dec7e12c22c", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_384", "a00737.html#gaa55acf6e0c6b46a2ae67c260819a3621", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_512", "a00737.html#ga9c10275675c3d6e4cccd6ebdfa229cc3", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_224", "a00738.html#ga675b25b13fc541b6caf4ede098e62a3a", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_256", "a00738.html#gaa8a671b476a7428d5a63addc98c196ce", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_384", "a00738.html#ga3f675b49bbe27893e553c19279260be3", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_512", "a00738.html#ga9488afdc7a3f5faf48e796ca3b2117dc", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_224", "a00739.html#ga3fd16f21d04553be99f6c4bade526fcb", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_256", "a00739.html#ga9a24ee94d01d6b1b8cb33c7af84f8d9e", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_384", "a00739.html#ga2d78f8155107a52c3e618bab9bb52f85", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_512", "a00739.html#gaf9f4da1c0d09797adb02f2af0bf4b429", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224", "a00740.html#ga5cc6964abb7966c445feb2abf14f8067", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256", "a00740.html#gaaa520442bedd60dec1b7e4b10ac57fe3", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384", "a00740.html#gab961aed69bd7828bf783f318a9dde671", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512", "a00740.html#gab75499823ecacb60bc8c9fdc8d541e95", null ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_SIZE", "a00736.html#ga0441e5ea8ef5538062269e9da3be7b6f", null ], + [ "mcuxClEls_Hash_Async", "a00742.html#ga086eeafba9afb8ea16550414fd33a3b3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00314_source.html b/components/els_pkc/doc/mcxn/html/a00314_source.html new file mode 100644 index 000000000..293fc4c68 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00314_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Hash.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
32 #ifndef MCUXCLELS_HASH_H_
33 #define MCUXCLELS_HASH_H_
34 
35 #include <mcuxClConfig.h> // Exported features flags header
36 #include <mcuxClEls_Common.h> // Common functionality
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 /**********************************************
43  * CONSTANTS
44  **********************************************/
45 
60 #define MCUXCLELS_HASH_INIT_ENABLE 1U
61 #define MCUXCLELS_HASH_INIT_DISABLE 0U
62 
63 #define MCUXCLELS_HASH_LOAD_ENABLE 1U
64 #define MCUXCLELS_HASH_LOAD_DISABLE 0U
65 
66 #define MCUXCLELS_HASH_OUTPUT_ENABLE 1U
67 #define MCUXCLELS_HASH_OUTPUT_DISABLE 0U
68 
69 #define MCUXCLELS_HASH_RTF_UPDATE_ENABLE 1U
70 #define MCUXCLELS_HASH_RTF_UPDATE_DISABLE 0U
71 
72 #define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE 1U
73 #define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE 0U
74 
75 #define MCUXCLELS_HASH_MODE_SHA_224 1U
76 #define MCUXCLELS_HASH_MODE_SHA_256 0U
77 #define MCUXCLELS_HASH_MODE_SHA_384 2U
78 #define MCUXCLELS_HASH_MODE_SHA_512 3U
79 
80 
81 #define MCUXCLELS_HASH_VALUE_MODE_SHA_224 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_224 << 4)
82 #define MCUXCLELS_HASH_VALUE_MODE_SHA_256 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_256 << 4)
83 #define MCUXCLELS_HASH_VALUE_MODE_SHA_384 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_384 << 4)
84 #define MCUXCLELS_HASH_VALUE_MODE_SHA_512 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_512 << 4)
85 
86 
97 #define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224 64U
98 #define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256 64U
99 #define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384 128U
100 #define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512 128U
101 
111 #define MCUXCLELS_HASH_STATE_SIZE_SHA_224 32U
112 #define MCUXCLELS_HASH_STATE_SIZE_SHA_256 32U
113 #define MCUXCLELS_HASH_STATE_SIZE_SHA_384 64U
114 #define MCUXCLELS_HASH_STATE_SIZE_SHA_512 64U
115 
125 #define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224 28U
126 #define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 32U
127 #define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384 48U
128 #define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 64U
129 
137 #define MCUXCLELS_HASH_RTF_OUTPUT_SIZE ((size_t)32U)
138 
144 /**********************************************
145  * TYPEDEFS
146  **********************************************/
147 
160 typedef union
161 {
162  struct
163  {
164  uint32_t value;
165  } word;
166  struct
167  {
168  uint32_t :2;
169  uint32_t hashini :1;
170  uint32_t hashld :1;
171  uint32_t hashmd :2;
172  uint32_t hashoe :1;
173  uint32_t rtfupd :1;
174  uint32_t rtfoe :1;
175  uint32_t :23;
176  } bits;
177 } mcuxClEls_HashOption_t;
178 
183 /**********************************************
184  * FUNCTIONS
185  **********************************************/
186 
237 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hash_Async)
238 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hash_Async(
239  mcuxClEls_HashOption_t options,
240  uint8_t const * pInput,
241  size_t inputLength,
242  uint8_t * pDigest
243  );
244 
245 
246 #ifdef __cplusplus
247 } /* extern "C" */
248 #endif
249 
250 #endif /* MCUXCLELS_HASH_H_ */
251 
mcuxClEls_HashOption_t::hashld
uint32_t hashld
Defines if the hash engine shall be initialized with an externally provided digest.
Definition: mcuxClEls_Hash.h:170
+
mcuxClEls_HashOption_t::hashoe
uint32_t hashoe
Defines if the hash digest shall be moved to the output buffer.
Definition: mcuxClEls_Hash.h:172
+
mcuxClEls_HashOption_t::rtfupd
uint32_t rtfupd
RTF (Runtime Fingerprint) Update.
Definition: mcuxClEls_Hash.h:173
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_HashOption_t::hashini
uint32_t hashini
Defines if the hash engine shall be initialized.
Definition: mcuxClEls_Hash.h:169
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_HashOption_t::hashmd
uint32_t hashmd
Defines which hash algorithm shall be used.
Definition: mcuxClEls_Hash.h:171
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_HashOption_t::rtfoe
uint32_t rtfoe
RTF (Runtime Fingerprint) Output Enabled.
Definition: mcuxClEls_Hash.h:174
+
mcuxClEls_Hash_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hash_Async(mcuxClEls_HashOption_t options, uint8_t const *pInput, size_t inputLength, uint8_t *pDigest)
Computes the hash of a message.
+
mcuxClEls_HashOption_t
Command option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect.
Definition: mcuxClEls_Hash.h:160
+
mcuxClEls_HashOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Hash.h:164
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00317.html b/components/els_pkc/doc/mcxn/html/a00317.html new file mode 100644 index 000000000..34afc6160 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00317.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Hmac.h File Reference
+
+
+ +

ELS header for HMAC support. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_HmacOption_t
 Command option bit field for mcuxClEls_Hmac_Async. More...
 
+ + + + + + + + + + + + +

+Macros

#define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
 Set mcuxClEls_HmacOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
 Set mcuxClEls_HmacOption_t.extkey to this value to use a key from the ELS keystore. More...
 
#define MCUXCLELS_HMAC_PADDED_KEY_SIZE
 
#define MCUXCLELS_HMAC_OUTPUT_SIZE
 HMAC Output size: 32 bytes. More...
 
+ + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hmac_Async (mcuxClEls_HmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pPaddedKey, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput)
 Performs HMAC with SHA-256. More...
 
+

Detailed Description

+

ELS header for HMAC support.

+

This header exposes functions that enable using the ELS for the generation of hashed-key message authentication codes (HMAC). The supported hash algorithm is SHA2-256.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00317.js b/components/els_pkc/doc/mcxn/html/a00317.js new file mode 100644 index 000000000..11c8c6eff --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00317.js @@ -0,0 +1,8 @@ +var a00317 = +[ + [ "MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE", "a00745.html#ga19feebc17331ebe966c67a9bfed79e33", null ], + [ "MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE", "a00745.html#ga876370de65e0c65b54c39b34921a4444", null ], + [ "MCUXCLELS_HMAC_PADDED_KEY_SIZE", "a00744.html#ga039409b9bba04a61be14b175117fb932", null ], + [ "MCUXCLELS_HMAC_OUTPUT_SIZE", "a00744.html#ga80d89c1569e578566088cad0ea9127f4", null ], + [ "mcuxClEls_Hmac_Async", "a00747.html#gafc82ce850568a1e0c9f44f9e59d6fbbf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00317_source.html b/components/els_pkc/doc/mcxn/html/a00317_source.html new file mode 100644 index 000000000..56385acb6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00317_source.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
+
+
mcuxClEls_Hmac.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
29 #ifndef MCUXCLELS_HMAC_H_
30 #define MCUXCLELS_HMAC_H_
31 
32 #include <mcuxClConfig.h> // Exported features flags header
33 #include <mcuxClEls_Common.h> // Common functionality
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /**********************************************
40  * MACROS
41  **********************************************/
54 #define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE 1U
55 #define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE 0U
56 
60 #define MCUXCLELS_HMAC_PADDED_KEY_SIZE ((size_t) 64U)
61 #define MCUXCLELS_HMAC_OUTPUT_SIZE ((size_t) 32U)
62 
66 /**********************************************
67  * TYPEDEFS
68  **********************************************/
69 
80 typedef union
81 {
82  struct
83  {
84  uint32_t value;
85  } word;
86  struct
87  {
88  uint32_t :13;
89  uint32_t extkey :1;
90  uint32_t :18;
91  } bits;
92 } mcuxClEls_HmacOption_t;
97 /**********************************************
98  * FUNCTIONS
99  **********************************************/
151 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hmac_Async)
152 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hmac_Async(
153  mcuxClEls_HmacOption_t options,
154  mcuxClEls_KeyIndex_t keyIdx,
155  uint8_t const * pPaddedKey,
156  uint8_t const * pInput,
157  size_t inputLength,
158  uint8_t * pOutput
159  );
160 
161 #ifdef __cplusplus
162 } /* extern "C" */
163 #endif
164 
165 #endif /* MCUXCLELS_HMAC_H_ */
166 
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_HmacOption_t::extkey
uint32_t extkey
Whether an external key should be used.
Definition: mcuxClEls_Hmac.h:89
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_Common.h
ELS header for common functionality.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_HmacOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Hmac.h:84
+
mcuxClEls_Hmac_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hmac_Async(mcuxClEls_HmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pPaddedKey, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput)
Performs HMAC with SHA-256.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_HmacOption_t
Command option bit field for mcuxClEls_Hmac_Async.
Definition: mcuxClEls_Hmac.h:80
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00320.html b/components/els_pkc/doc/mcxn/html/a00320.html new file mode 100644 index 000000000..f38c04856 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00320.html @@ -0,0 +1,211 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Data Structures | +Macros | +Functions
+
+
mcuxClEls_Kdf.h File Reference
+
+
+ +

ELS header for key derivation. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Data Structures

union  mcuxClEls_CkdfOption_t
 Internal command option bit field for CKDF functions. More...
 
union  mcuxClEls_HkdfOption_t
 Command option bit field for mcuxClEls_Hkdf_Rfc5869_Async. More...
 
union  mcuxClEls_TlsOption_t
 Internal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE
 Size of CKDF SP800-108 derivation data. More...
 
#define MCUXCLELS_CKDF_ALGO_SP800108
 Use SP800-108 algorithm. More...
 
#define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE
 Size of HKDF derivation data. More...
 
#define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE
 Size of HKDF SP800-56C derived key. More...
 
#define MCUXCLELS_HKDF_VALUE_RTF_DERIV
 Use RTF as derivation input. More...
 
#define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV
 Use derivation input from system memory. More...
 
#define MCUXCLELS_HKDF_ALGO_RFC5869
 Use RFC5869 algorithm. More...
 
#define MCUXCLELS_HKDF_ALGO_SP80056C
 Use SP800-56C algorithm. More...
 
#define MCUXCLELS_HKDF_RTF_DERIV
 Use RTF as derivation input. More...
 
#define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV
 Use derivation input from system memory. More...
 
#define MCUXCLELS_TLS_DERIVATIONDATA_SIZE
 Size of TLS derivation data. More...
 
#define MCUXCLELS_TLS_RANDOM_SIZE
 Size of random bytes for TLS. More...
 
#define MCUXCLELS_TLS_INIT
 Perform master key generation. More...
 
#define MCUXCLELS_TLS_FINALIZE
 Perform session key generation. More...
 
+ + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Rfc5869_Async (mcuxClEls_HkdfOption_t options, mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
 Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Sp80056c_Async (mcuxClEls_KeyIndex_t derivationKeyIdx, uint8_t *pTagetKey, uint8_t const *pDerivationData, size_t derivationDataLength)
 Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step approach with Sha2-256. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Ckdf_Sp800108_Async (mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
 Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async (uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
 Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1.2 specification. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async (uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
 Generates TLS session keys based on a master key and derivation data, according to the TLS 1.2 specification. More...
 
+

Detailed Description

+

ELS header for key derivation.

+

This header exposes functions that enable using the ELS for various key derivation commands. The supported key derivation algorithms are CKDF, HKDF, TLS

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00320.js b/components/els_pkc/doc/mcxn/html/a00320.js new file mode 100644 index 000000000..1ce03944f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00320.js @@ -0,0 +1,22 @@ +var a00320 = +[ + [ "MCUXCLELS_CKDF_DERIVATIONDATA_SIZE", "a00750.html#gae0e48994f0652e42fec3acca8c4469bb", null ], + [ "MCUXCLELS_CKDF_ALGO_SP800108", "a00750.html#gacb24894c500384a885842b542053b60f", null ], + [ "MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE", "a00750.html#ga7b1d08f458ed93ea2a17bdb8f8ecee40", null ], + [ "MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE", "a00750.html#gaf62127ae68ef3ec5815f3a7c3907d66f", null ], + [ "MCUXCLELS_HKDF_VALUE_RTF_DERIV", "a00750.html#ga9590681d68b6ef92ba29e53ecd556213", null ], + [ "MCUXCLELS_HKDF_VALUE_MEMORY_DERIV", "a00750.html#ga1af84f58a0ee007153d5e7dc65b43c2b", null ], + [ "MCUXCLELS_HKDF_ALGO_RFC5869", "a00750.html#ga3e905f07b3198e2853b8b099d68dc5d1", null ], + [ "MCUXCLELS_HKDF_ALGO_SP80056C", "a00750.html#ga41a071a8d47d42ec8350dd2db4f37867", null ], + [ "MCUXCLELS_HKDF_RTF_DERIV", "a00750.html#ga9eb01402c540d2f07a66cb1a26a12b1d", null ], + [ "MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV", "a00750.html#ga5b9747f125d34747a4707a5a08a572b2", null ], + [ "MCUXCLELS_TLS_DERIVATIONDATA_SIZE", "a00750.html#ga542a08e762e187464b77a707973eff65", null ], + [ "MCUXCLELS_TLS_RANDOM_SIZE", "a00750.html#gaf6beb56c924bf4d0bcea3a6fa31803be", null ], + [ "MCUXCLELS_TLS_INIT", "a00750.html#gaecd87e8690f333b6747f9e29848dfd08", null ], + [ "MCUXCLELS_TLS_FINALIZE", "a00750.html#gac9f01f30577af236ba91f31c78c428d2", null ], + [ "mcuxClEls_Hkdf_Rfc5869_Async", "a00752.html#gaad9187ee88fcb4efae7fd9469b51dc81", null ], + [ "mcuxClEls_Hkdf_Sp80056c_Async", "a00752.html#ga8d44c8b880565afe51d941057570361b", null ], + [ "mcuxClEls_Ckdf_Sp800108_Async", "a00752.html#ga4cf223def750c39f5c955fdfbe12bc8d", null ], + [ "mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async", "a00752.html#gac8b832b6cfa9c2b15b51be04ab349ae6", null ], + [ "mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async", "a00752.html#ga50b0d0753ed6a370b187904db49826ff", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00320_source.html b/components/els_pkc/doc/mcxn/html/a00320_source.html new file mode 100644 index 000000000..1b7994434 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00320_source.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf.h Source File + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClEls_Kdf.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
37 #ifndef MCUXCLELS_KDF_H_
38 #define MCUXCLELS_KDF_H_
39 
40 #include <mcuxClConfig.h> // Exported features flags header
41 
42 
43 
44 
45 
46 #include <mcuxClEls_Common.h> // Common functionality
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
52 /**********************************************
53  * CONSTANTS
54  **********************************************/
55 
64 #define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE 12u
65 #define MCUXCLELS_CKDF_ALGO_SP800108 0x0u
66 
67 
68 
69 
70 #define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE 32u
71 #define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE 32u
72 
73 #define MCUXCLELS_HKDF_VALUE_RTF_DERIV ((uint32_t) 1u<< 0u)
74 #define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV ((uint32_t) 0u<< 0u)
75 
76 #define MCUXCLELS_HKDF_ALGO_RFC5869 0x0u
77 #define MCUXCLELS_HKDF_ALGO_SP80056C 0x1u
78 
79 #define MCUXCLELS_HKDF_RTF_DERIV 1U
80 #define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV 0U
81 
82 #define MCUXCLELS_TLS_DERIVATIONDATA_SIZE ((size_t) 80u)
83 #define MCUXCLELS_TLS_RANDOM_SIZE ((size_t) 32u)
84 
85 #define MCUXCLELS_TLS_INIT 0u
86 #define MCUXCLELS_TLS_FINALIZE 1u
87 
88  /* mcuxClEls_Kdf_Define */
91 
92 /**********************************************
93  * TYPEDEFS
94  **********************************************/
95 
104 typedef union
105 {
106  struct
107  {
108  uint32_t value;
109  } word;
110  struct
111  {
112  uint32_t :12;
113  uint32_t ckdf_algo :2;
114  uint32_t :18;
116  } bits;
117 } mcuxClEls_CkdfOption_t;
118 
120 typedef union
121 {
122  struct
123  {
124  uint32_t value;
125  } word;
126  struct
127  {
128  uint32_t rtfdrvdat :1;
129  uint32_t hkdf_algo :1;
130  uint32_t :30;
133  } bits;
134 } mcuxClEls_HkdfOption_t;
135 
137 typedef union
138 {
139  struct
140  {
141  uint32_t value;
142  } word;
143  struct
144  {
145  uint32_t :10;
146  uint32_t mode :1;
147  uint32_t :21;
150  } bits;
151 } mcuxClEls_TlsOption_t;
152  /* mcuxClEls_Kdf_Types */
156  /* mcuxClEls_Kdf_Macros */
160 
161 
162 /**********************************************
163  * FUNCTIONS
164  **********************************************/
195 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Rfc5869_Async)
196 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Rfc5869_Async(
197  mcuxClEls_HkdfOption_t options,
198  mcuxClEls_KeyIndex_t derivationKeyIdx,
199  mcuxClEls_KeyIndex_t targetKeyIdx,
200  mcuxClEls_KeyProp_t targetKeyProperties,
201  uint8_t const * pDerivationData
202  );
203 
224 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Sp80056c_Async)
225 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Sp80056c_Async(
226  mcuxClEls_KeyIndex_t derivationKeyIdx,
227  uint8_t * pTagetKey,
228  uint8_t const * pDerivationData,
229  size_t derivationDataLength
230  );
231 
232 
254 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Ckdf_Sp800108_Async)
255 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Ckdf_Sp800108_Async(
256  mcuxClEls_KeyIndex_t derivationKeyIdx,
257  mcuxClEls_KeyIndex_t targetKeyIdx,
258  mcuxClEls_KeyProp_t targetKeyProperties,
259  uint8_t const * pDerivationData
260  );
261 
262 
263 
284 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async)
285 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async(
286  uint8_t const * pDerivationData,
287  mcuxClEls_KeyProp_t keyProperties,
288  mcuxClEls_KeyIndex_t keyIdx
289  );
290 
319 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async)
320 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async(
321  uint8_t const * pDerivationData,
322  mcuxClEls_KeyProp_t keyProperties,
323  mcuxClEls_KeyIndex_t keyIdx
324  );
325  /* mcuxClEls_Kdf_Functions */
329  /* mcuxClEls_Kdf */
333 
334 #ifdef __cplusplus
335 } /* extern "C" */
336 #endif
337 
338 #endif /* MCUXCLELS_KDF_H_ */
mcuxClEls_HkdfOption_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF...
Definition: mcuxClEls_Kdf.h:124
+
mcuxClEls_TlsOption_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF...
Definition: mcuxClEls_Kdf.h:141
+
mcuxClEls_TlsOption_t::mode
uint32_t mode
Defines which phase of the key generation is performed.
Definition: mcuxClEls_Kdf.h:146
+
mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async(uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1....
+
mcuxClEls_Hkdf_Sp80056c_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Sp80056c_Async(mcuxClEls_KeyIndex_t derivationKeyIdx, uint8_t *pTagetKey, uint8_t const *pDerivationData, size_t derivationDataLength)
Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step app...
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_HkdfOption_t
Command option bit field for mcuxClEls_Hkdf_Rfc5869_Async.
Definition: mcuxClEls_Kdf.h:120
+
mcuxClEls_HkdfOption_t::hkdf_algo
uint32_t hkdf_algo
Defines which algorithm shall be used.
Definition: mcuxClEls_Kdf.h:129
+
mcuxClEls_CkdfOption_t::ckdf_algo
uint32_t ckdf_algo
Defines which algorithm and mode shall be used.
Definition: mcuxClEls_Kdf.h:113
+
mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async(uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
Generates TLS session keys based on a master key and derivation data, according to the TLS 1....
+
mcuxClEls_Hkdf_Rfc5869_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Rfc5869_Async(mcuxClEls_HkdfOption_t options, mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869.
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_HkdfOption_t::rtfdrvdat
uint32_t rtfdrvdat
MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV=use derivation input from system memory, MCUXCLELS_HKDF_RTF_DERIV=...
Definition: mcuxClEls_Kdf.h:128
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClEls_TlsOption_t
Internal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async,...
Definition: mcuxClEls_Kdf.h:137
+
mcuxClEls_Ckdf_Sp800108_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Ckdf_Sp800108_Async(mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_CkdfOption_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF...
Definition: mcuxClEls_Kdf.h:108
+
mcuxClEls_CkdfOption_t
Internal command option bit field for CKDF functions.
Definition: mcuxClEls_Kdf.h:104
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00323.html b/components/els_pkc/doc/mcxn/html/a00323.html new file mode 100644 index 000000000..6c29320b6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00323.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Data Structures | +Macros | +Functions
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mcuxClEls_KeyManagement.h File Reference
+
+
+ +

ELS header for key management. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_KeyImportOption_t
 Command option bit field for mcuxClEls_KeyImport_Async. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF
 Key format UDF with shares in RTL or memory. More...
 
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394
 Key format RFC3394 with shares in memory. More...
 
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF
 Key from PUF. More...
 
#define MCUXCLELS_KEYIMPORT_KFMT_UDF
 Key format UDF with shares in RTL or memory. More...
 
#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394
 Key format RFC3394 with shares in memory. More...
 
#define MCUXCLELS_KEYIMPORT_KFMT_PUF
 Key from PUF. More...
 
#define MCUXCLELS_RFC3394_OVERHEAD
 Overhead between RFC3394 blob and key size. More...
 
#define MCUXCLELS_RFC3394_CONTAINER_SIZE_128
 Size of RFC3394 container for 128 bit key. More...
 
#define MCUXCLELS_RFC3394_CONTAINER_SIZE_256
 Size of RFC3394 container for 256 bit key. More...
 
+ + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyDelete_Async (mcuxClEls_KeyIndex_t keyIdx)
 Deletes a key from keystore at the given index. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyImport_Async (mcuxClEls_KeyImportOption_t options, uint8_t const *pImportKey, size_t importKeyLength, mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx)
 Imports a key from external storage to an internal key register. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyExport_Async (mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t exportKeyIdx, uint8_t *pOutput)
 Exports a key from an internal key register to external storage, using a wrapping key. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetKeyProperties (mcuxClEls_KeyIndex_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp)
 Exports the properties of the keys stored in the ELS internal keystore. More...
 
+

Detailed Description

+

ELS header for key management.

+

This header exposes functions that can be used to manage the keystore of ELS. This includes:

    +
  • Importing keys
    • +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00323.js b/components/els_pkc/doc/mcxn/html/a00323.js new file mode 100644 index 000000000..61fdd057a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00323.js @@ -0,0 +1,16 @@ +var a00323 = +[ + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF", "a00755.html#ga984d35cad96543f5cb269a9ee771834b", null ], + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394", "a00755.html#ga8ae5e78cfde658034967faafbbc84c97", null ], + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF", "a00755.html#gabf3d81b763b4402dd1a4716ca7b10a56", null ], + [ "MCUXCLELS_KEYIMPORT_KFMT_UDF", "a00756.html#ga1935d246d89a89d4d04c393b40161429", null ], + [ "MCUXCLELS_KEYIMPORT_KFMT_RFC3394", "a00756.html#gaa3f8c4e99d3c233eeaa2685d9e0d4b67", null ], + [ "MCUXCLELS_KEYIMPORT_KFMT_PUF", "a00756.html#ga757baa3bf038e4f16c63e356a2a590a6", null ], + [ "MCUXCLELS_RFC3394_OVERHEAD", "a00756.html#ga9c38ef72ae48380b864e6e5fb950ee17", null ], + [ "MCUXCLELS_RFC3394_CONTAINER_SIZE_128", "a00757.html#ga4d0fa5e5255eb1fa89b0cf6a30a452fb", null ], + [ "MCUXCLELS_RFC3394_CONTAINER_SIZE_256", "a00757.html#ga46c8e56ff10c6a6ecb28c511cd32178c", null ], + [ "mcuxClEls_KeyDelete_Async", "a00759.html#ga035d072c033f988194110973581c6303", null ], + [ "mcuxClEls_KeyImport_Async", "a00759.html#ga867d4be563b347273af25a559abd7f87", null ], + [ "mcuxClEls_KeyExport_Async", "a00759.html#ga698ad21f0b3576d2b9f4b7b3ef83134f", null ], + [ "mcuxClEls_GetKeyProperties", "a00759.html#ga524d99bbf9aae0d299fbb52d2a121c4f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00323_source.html b/components/els_pkc/doc/mcxn/html/a00323_source.html new file mode 100644 index 000000000..abf672063 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00323_source.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEls_KeyManagement.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
36 #ifndef MCUXCLELS_KEYMANAGEMENT_H_
37 #define MCUXCLELS_KEYMANAGEMENT_H_
38 
39 #include <mcuxClConfig.h> // Exported features flags header
40 #include <mcuxClEls_Common.h> // Common functionality
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /**********************************************
47  * CONSTANTS
48  **********************************************/
64 #define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF ((uint32_t) 0u<< 6u)
65 #define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394 ((uint32_t) 1u<< 6u)
66 #define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF ((uint32_t) 2u<< 6u)
67 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
68 #define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK ((uint32_t) 3u<< 6u)
69 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
70 
82 #define MCUXCLELS_KEYIMPORT_KFMT_UDF (0x00u)
83 #define MCUXCLELS_KEYIMPORT_KFMT_RFC3394 (0x01u)
84 #define MCUXCLELS_KEYIMPORT_KFMT_PUF (0x02u)
85 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
86 #define MCUXCLELS_KEYIMPORT_KFMT_PBK (0x03u)
87 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
88 
89 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
90 #define MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE (0x01U)
91 #define MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE (0x00U)
92 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
93 
94 #define MCUXCLELS_RFC3394_OVERHEAD ((size_t) 16u)
95 
106 #define MCUXCLELS_RFC3394_CONTAINER_SIZE_128 ((size_t) 256u/8u)
107 #define MCUXCLELS_RFC3394_CONTAINER_SIZE_256 ((size_t) 384u/8u)
108 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
109 #define MCUXCLELS_RFC3394_CONTAINER_SIZE_P256 ((size_t) 640u/8u)
110 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
111 
119 /**********************************************
120  * TYPEDEFS
121  **********************************************/
136 typedef union
137 {
138  struct
139  {
140  uint32_t value;
141  } word;
142  struct
143  {
144  uint32_t :4;
145  uint32_t revf :1;
146  uint32_t :1;
147  uint32_t kfmt :2;
148  uint32_t :24;
149  } bits;
150 } mcuxClEls_KeyImportOption_t;
151 
156 /**********************************************
157  * FUNCTIONS
158  **********************************************/
184 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyDelete_Async)
185 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyDelete_Async(
186  mcuxClEls_KeyIndex_t keyIdx
187 );
188 
189 
190 
227 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImport_Async)
228 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImport_Async(
229  mcuxClEls_KeyImportOption_t options,
230  uint8_t const * pImportKey,
231  size_t importKeyLength,
232  mcuxClEls_KeyIndex_t wrappingKeyIdx,
233  mcuxClEls_KeyIndex_t targetKeyIdx
234  );
235 
236 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
237 
260 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImportPuk_Async)
261 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImportPuk_Async(
262  uint8_t const * pCertificate,
263  size_t certificateLength,
264  size_t publicKeyOffset,
265  uint8_t const * pSignature,
266  mcuxClEls_KeyIndex_t verifyingKeyIdx,
267  mcuxClEls_KeyProp_t keyProperties,
268  mcuxClEls_KeyIndex_t targetKeyIdx,
269  uint8_t * pOutput
270  );
271 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
272 
293 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyExport_Async)
294 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyExport_Async(
295  mcuxClEls_KeyIndex_t wrappingKeyIdx,
296  mcuxClEls_KeyIndex_t exportKeyIdx,
297  uint8_t * pOutput
298  );
299 
314 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetKeyProperties)
315 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetKeyProperties(
316  mcuxClEls_KeyIndex_t keyIdx,
317  mcuxClEls_KeyProp_t * pKeyProp
318  );
319 
324 #ifdef __cplusplus
325 } /* extern "C" */
326 #endif
327 
328 #endif /* MCUXCLELS_KEYMANAGEMENT_H_ */
329 
mcuxClEls_KeyImportOption_t::revf
uint32_t revf
This field is managed internally.
Definition: mcuxClEls_KeyManagement.h:145
+
mcuxClEls_KeyImport_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyImport_Async(mcuxClEls_KeyImportOption_t options, uint8_t const *pImportKey, size_t importKeyLength, mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx)
Imports a key from external storage to an internal key register.
+
mcuxClEls_KeyImportOption_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYI...
Definition: mcuxClEls_KeyManagement.h:140
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
mcuxClEls_GetKeyProperties
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetKeyProperties(mcuxClEls_KeyIndex_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp)
Exports the properties of the keys stored in the ELS internal keystore.
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_KeyDelete_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyDelete_Async(mcuxClEls_KeyIndex_t keyIdx)
Deletes a key from keystore at the given index.
+
mcuxClEls_KeyImportOption_t::kfmt
uint32_t kfmt
Defines the key import format, one of MCUXCLELS_KEYIMPORT_KFMT_.
Definition: mcuxClEls_KeyManagement.h:147
+
mcuxClEls_Common.h
ELS header for common functionality.
+
mcuxClEls_KeyExport_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyExport_Async(mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t exportKeyIdx, uint8_t *pOutput)
Exports a key from an internal key register to external storage, using a wrapping key.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClEls_KeyImportOption_t
Command option bit field for mcuxClEls_KeyImport_Async.
Definition: mcuxClEls_KeyManagement.h:136
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00326.html b/components/els_pkc/doc/mcxn/html/a00326.html new file mode 100644 index 000000000..abe0d9bf4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00326.html @@ -0,0 +1,1639 @@ + + + + + + + +MCUX CLNS: mcuxClEls_mapping.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEls_mapping.h File Reference
+
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Header providing mapping for legacy function/definition names (with CSS) +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLCSS_API
 MCUXCLCSS_CSS_((?:INTERRUPT_DISABLE|INTERRUPT_ENABLE|INTERRUPT_KEEP|INTERRUPT_SET|RESET_CLEAR|RESET_KEEP))(?!\w) --> MCUXCLELS_ELS_\1. More...
 
+#define MCUXCLCSS_AEAD_AAD_BLOCK_SIZE
 
+#define MCUXCLCSS_AEAD_ACPMOD_AADPROC
 
+#define MCUXCLCSS_AEAD_ACPMOD_FINAL
 
+#define MCUXCLCSS_AEAD_ACPMOD_INIT
 
+#define MCUXCLCSS_AEAD_ACPMOD_MSGPROC
 
+#define MCUXCLCSS_AEAD_CONTEXT_SIZE
 
+#define MCUXCLCSS_AEAD_DECRYPT
 
+#define MCUXCLCSS_AEAD_ENCRYPT
 
+#define MCUXCLCSS_AEAD_EXTERN_KEY
 
+#define MCUXCLCSS_AEAD_INTERN_KEY
 
+#define MCUXCLCSS_AEAD_IV_BLOCK_SIZE
 
+#define MCUXCLCSS_AEAD_LASTINIT_FALSE
 
+#define MCUXCLCSS_AEAD_LASTINIT_TRUE
 
+#define MCUXCLCSS_AEAD_STATE_IN_DISABLE
 
+#define MCUXCLCSS_AEAD_STATE_IN_ENABLE
 
+#define MCUXCLCSS_AEAD_STATE_OUT_ENABLE
 
+#define MCUXCLCSS_AEAD_TAG_SIZE
 
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CBC
 
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CTR
 
+#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB
 
+#define MCUXCLCSS_CIPHER_BLOCK_SIZE_AES
 
+#define MCUXCLCSS_CIPHER_DECRYPT
 
+#define MCUXCLCSS_CIPHER_ENCRYPT
 
+#define MCUXCLCSS_CIPHER_EXTERNAL_KEY
 
+#define MCUXCLCSS_CIPHER_INTERNAL_KEY
 
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_128
 
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_192
 
+#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_256
 
+#define MCUXCLCSS_CIPHER_STATE_IN_DISABLE
 
+#define MCUXCLCSS_CIPHER_STATE_IN_ENABLE
 
+#define MCUXCLCSS_CIPHER_STATE_OUT_DISABLE
 
+#define MCUXCLCSS_CIPHER_STATE_OUT_ENABLE
 
+#define MCUXCLCSS_CKDF_ALGO_SP800108
 
+#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXPAND
 
+#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXTRACT
 
+#define MCUXCLCSS_CKDF_DERIVATIONDATA_SIZE
 
+#define MCUXCLCSS_HKDF_RTF_DERIV
 
+#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16
 
+#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32
 
+#define MCUXCLCSS_HKDF_SYSTEM_MEMORY_DERIV
 
+#define MCUXCLCSS_CMAC_EXTERNAL_KEY_DISABLE
 
+#define MCUXCLCSS_CMAC_EXTERNAL_KEY_ENABLE
 
+#define MCUXCLCSS_CMAC_FINALIZE_DISABLE
 
+#define MCUXCLCSS_CMAC_FINALIZE_ENABLE
 
+#define MCUXCLCSS_CMAC_INITIALIZE_DISABLE
 
+#define MCUXCLCSS_CMAC_INITIALIZE_ENABLE
 
+#define MCUXCLCSS_CMAC_KEY_SIZE_128
 
+#define MCUXCLCSS_CMAC_KEY_SIZE_256
 
+#define MCUXCLCSS_CMAC_OUT_SIZE
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_AUTH_CIPHER
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CIPHER
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CKDF
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_CMAC
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DRBG_TEST
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_EVAL
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECKXH
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECSIGN
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_ECVFY
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_TRIM
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HASH
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HKDF
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_HMAC
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KDELETE
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYGEN
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYIN
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYOUT
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYPROV
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_RND_REQ
 
+#define MCUXCLCSS_CMD_CRC_CMD_ID_TLS
 
+#define MCUXCLCSS_CMD_CRC_DISABLE
 
+#define MCUXCLCSS_CMD_CRC_ENABLE
 
+#define MCUXCLCSS_CMD_CRC_INITIAL_VALUE
 
+#define MCUXCLCSS_CMD_CRC_POLYNOMIAL
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_INIT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_RESET
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CIPHER
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CMAC
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HASH
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HMAC
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RESPGEN
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY
 
+#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY
 
+#define MCUXCLCSS_CMD_CRC_RESET
 
+#define MCUXCLCSS_CMD_CRC_VALUE_DISABLE
 
+#define MCUXCLCSS_CMD_CRC_VALUE_ENABLE
 
+#define MCUXCLCSS_CMD_CRC_VALUE_RESET
 
+#define MCUXCLCSS_CSS_INTERRUPT_DISABLE
 
+#define MCUXCLCSS_CSS_INTERRUPT_ENABLE
 
+#define MCUXCLCSS_CSS_INTERRUPT_KEEP
 
+#define MCUXCLCSS_CSS_INTERRUPT_SET
 
+#define MCUXCLCSS_CSS_RESET_CLEAR
 
+#define MCUXCLCSS_CSS_RESET_KEEP
 
+#define MCUXCLCSS_DMA_READBACK_PROTECTION_TOKEN
 
+#define MCUXCLCSS_ECC_EXTKEY_EXTERNAL
 
+#define MCUXCLCSS_ECC_EXTKEY_INTERNAL
 
+#define MCUXCLCSS_ECC_GEN_PUBLIC_KEY
 
+#define MCUXCLCSS_ECC_HASHED
 
+#define MCUXCLCSS_ECC_INCLUDE_RANDOM_DATA
 
+#define MCUXCLCSS_ECC_NOT_HASHED
 
+#define MCUXCLCSS_ECC_NO_RANDOM_DATA
 
+#define MCUXCLCSS_ECC_NO_RTF
 
+#define MCUXCLCSS_ECC_OUTPUTKEY_DETERMINISTIC
 
+#define MCUXCLCSS_ECC_OUTPUTKEY_KEYEXCHANGE
 
+#define MCUXCLCSS_ECC_OUTPUTKEY_RANDOM
 
+#define MCUXCLCSS_ECC_OUTPUTKEY_SIGN
 
+#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_DISABLE
 
+#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_ENABLE
 
+#define MCUXCLCSS_ECC_PUBLICKEY_SIZE
 
+#define MCUXCLCSS_ECC_REVERSEFETCH_DISABLE
 
+#define MCUXCLCSS_ECC_REVERSEFETCH_ENABLE
 
+#define MCUXCLCSS_ECC_RTF
 
+#define MCUXCLCSS_ECC_SIGNATURE_R_SIZE
 
+#define MCUXCLCSS_ECC_SIGNATURE_SIZE
 
+#define MCUXCLCSS_ECC_SKIP_PUBLIC_KEY
 
+#define MCUXCLCSS_ECC_VALUE_HASHED
 
+#define MCUXCLCSS_ECC_VALUE_NOT_HASHED
 
+#define MCUXCLCSS_ECC_VALUE_NO_RTF
 
+#define MCUXCLCSS_ECC_VALUE_RTF
 
+#define MCUXCLCSS_ERROR_FLAGS_CLEAR
 
+#define MCUXCLCSS_ERROR_FLAGS_KEEP
 
+#define MCUXCLCSS_GLITCHDETECTOR_CFG_SIZE
 
+#define MCUXCLCSS_GLITCHDETECTOR_TRIM_SIZE
 
+#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_DISABLE
 
+#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_ENABLE
 
+#define MCUXCLCSS_GLITCH_DETECTOR_NEG_KEEP
 
+#define MCUXCLCSS_GLITCH_DETECTOR_NEG_SET
 
+#define MCUXCLCSS_GLITCH_DETECTOR_POS_KEEP
 
+#define MCUXCLCSS_GLITCH_DETECTOR_POS_SET
 
+#define MCUXCLCSS_GLITCH_DETECTOR_RESET_CLEAR
 
+#define MCUXCLCSS_GLITCH_DETECTOR_RESET_KEEP
 
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_224
 
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_256
 
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_384
 
+#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_512
 
+#define MCUXCLCSS_HASH_INIT_DISABLE
 
+#define MCUXCLCSS_HASH_INIT_ENABLE
 
+#define MCUXCLCSS_HASH_LOAD_DISABLE
 
+#define MCUXCLCSS_HASH_LOAD_ENABLE
 
+#define MCUXCLCSS_HASH_MODE_SHA_224
 
+#define MCUXCLCSS_HASH_MODE_SHA_256
 
+#define MCUXCLCSS_HASH_MODE_SHA_384
 
+#define MCUXCLCSS_HASH_MODE_SHA_512
 
+#define MCUXCLCSS_HASH_OUTPUT_DISABLE
 
+#define MCUXCLCSS_HASH_OUTPUT_ENABLE
 
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_224
 
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_256
 
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_384
 
+#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_512
 
+#define MCUXCLCSS_HASH_RTF_OUTPUT_DISABLE
 
+#define MCUXCLCSS_HASH_RTF_OUTPUT_ENABLE
 
+#define MCUXCLCSS_HASH_RTF_OUTPUT_SIZE
 
+#define MCUXCLCSS_HASH_RTF_UPDATE_DISABLE
 
+#define MCUXCLCSS_HASH_RTF_UPDATE_ENABLE
 
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_224
 
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_256
 
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_384
 
+#define MCUXCLCSS_HASH_STATE_SIZE_SHA_512
 
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_224
 
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_256
 
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_384
 
+#define MCUXCLCSS_HASH_VALUE_MODE_SHA_512
 
+#define MCUXCLCSS_HKDF_ALGO_RFC5869
 
+#define MCUXCLCSS_HKDF_ALGO_SP80056C
 
+#define MCUXCLCSS_HKDF_RFC5869_DERIVATIONDATA_SIZE
 
+#define MCUXCLCSS_HKDF_SP80056C_TARGETKEY_SIZE
 
+#define MCUXCLCSS_HKDF_VALUE_MEMORY_DERIV
 
+#define MCUXCLCSS_HKDF_VALUE_RTF_DERIV
 
+#define MCUXCLCSS_HMAC_EXTERNAL_KEY_DISABLE
 
+#define MCUXCLCSS_HMAC_EXTERNAL_KEY_ENABLE
 
+#define MCUXCLCSS_HMAC_OUTPUT_SIZE
 
+#define MCUXCLCSS_HMAC_PADDED_KEY_SIZE
 
+#define MCUXCLCSS_HW_VERSION
 
+#define MCUXCLCSS_KEYGEN_VALUE_DETERMINISTIC
 
+#define MCUXCLCSS_KEYGEN_VALUE_GEN_PUB_KEY
 
+#define MCUXCLCSS_KEYGEN_VALUE_NO_PUB_KEY
 
+#define MCUXCLCSS_KEYGEN_VALUE_NO_RANDOM_DATA
 
+#define MCUXCLCSS_KEYGEN_VALUE_RANDOM
 
+#define MCUXCLCSS_KEYGEN_VALUE_SIGN_PUBLICKEY
 
+#define MCUXCLCSS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
 
+#define MCUXCLCSS_KEYGEN_VALUE_TYPE_SIGN
 
+#define MCUXCLCSS_KEYGEN_VALUE_USE_RANDOM_DATA
 
+#define MCUXCLCSS_KEYIMPORT_KFMT_PBK
 
+#define MCUXCLCSS_KEYIMPORT_KFMT_PUF
 
+#define MCUXCLCSS_KEYIMPORT_KFMT_RFC3394
 
+#define MCUXCLCSS_KEYIMPORT_KFMT_UDF
 
+#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_DISABLE
 
+#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_ENABLE
 
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PBK
 
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PUF
 
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_RFC3394
 
+#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_UDF
 
+#define MCUXCLCSS_KEYPROPERTY_ACTIVE_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_ACTIVE_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_AES_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_AES_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_BASE_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_CKDF_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_CKDF_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_CMAC_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_CMAC_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_ECC_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_ECC_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_HKDF_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_HKDF_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_HMAC_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_HMAC_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_HW_OUT_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_128
 
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_256
 
+#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_512
 
+#define MCUXCLCSS_KEYPROPERTY_KSK_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_KSK_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_KUOK_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_KUOK_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_KWK_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_KWK_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_PUK_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_PUK_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_RTF_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_RTF_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_SECOND_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_SECURE_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_SECURE_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_TECDH_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_TECDH_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ACTIVE
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_AES
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_BASE_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_CKDF
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_CMAC
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_DUK
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ECDH
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_ECSGN
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HKDF
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HMAC
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_128
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_256
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_512
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KGSRC
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KSK
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KUOK
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_KWK
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTPRIVILEGED
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTSECURE
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_PRIVILEGED
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_PUK
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_RETENTION_SLOT
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_RTF
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_SECURE
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TECDH
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
 
+#define MCUXCLCSS_KEYPROPERTY_VALUE_WRPOK
 
+#define MCUXCLCSS_KEYPROPERTY_WRAP_FALSE
 
+#define MCUXCLCSS_KEYPROPERTY_WRAP_TRUE
 
+#define MCUXCLCSS_KEYPROV_DUK_UPDATE_DISABLE
 
+#define MCUXCLCSS_KEYPROV_DUK_UPDATE_ENABLE
 
+#define MCUXCLCSS_KEYPROV_KEYSHARE_TABLE_SIZE
 
+#define MCUXCLCSS_KEYPROV_KEY_PART_1_SIZE
 
+#define MCUXCLCSS_KEYPROV_NOIC_DISABLE
 
+#define MCUXCLCSS_KEYPROV_NOIC_ENABLE
 
+#define MCUXCLCSS_KEYPROV_TESTERSHARE_SIZE
 
+#define MCUXCLCSS_KEYPROV_VALUE_NOIC
 
+#define MCUXCLCSS_KEY_SLOTS
 
+#define MCUXCLCSS_MASTER_UNLOCK_ANY
 
+#define MCUXCLCSS_RESET_CANCEL
 
+#define MCUXCLCSS_RESET_DO_NOT_CANCEL
 
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_0
 
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_1
 
+#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_2
 
+#define MCUXCLCSS_RESP_GEN_SLOTS
 
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_128
 
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_256
 
+#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_P256
 
+#define MCUXCLCSS_RFC3394_OVERHEAD
 
+#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
 
+#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
 
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_CTR
 
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_ECB
 
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_EXTRACT
 
+#define MCUXCLCSS_RNG_DRBG_TEST_MODE_INSTANTIATE
 
+#define MCUXCLCSS_RNG_DTRNG_CONFIG_SIZE
 
+#define MCUXCLCSS_RNG_DTRNG_EVAL_CONFIG_SIZE
 
+#define MCUXCLCSS_RNG_DTRNG_EVAL_RESULT_SIZE
 
+#define MCUXCLCSS_RNG_RAW_ENTROPY_SIZE
 
+#define MCUXCLCSS_RNG_RND_REQ_PRND_INIT
 
+#define MCUXCLCSS_RNG_RND_REQ_RND_RAW
 
+#define MCUXCLCSS_STATUS_DRBGENTLVL_HIGH
 
+#define MCUXCLCSS_STATUS_DRBGENTLVL_LOW
 
+#define MCUXCLCSS_STATUS_DRBGENTLVL_NONE
 
+#define MCUXCLCSS_STATUS_ECDSAVFY_ERROR
 
+#define MCUXCLCSS_STATUS_ECDSAVFY_FAIL
 
+#define MCUXCLCSS_STATUS_ECDSAVFY_NORUN
 
+#define MCUXCLCSS_STATUS_ECDSAVFY_OK
 
+#define MCUXCLCSS_STATUS_HW_ALGORITHM
 
+#define MCUXCLCSS_STATUS_HW_BUS
 
+#define MCUXCLCSS_STATUS_HW_DTRNG
 
+#define MCUXCLCSS_STATUS_HW_FAULT
 
+#define MCUXCLCSS_STATUS_HW_INTEGRITY
 
+#define MCUXCLCSS_STATUS_HW_OPERATIONAL
 
+#define MCUXCLCSS_STATUS_HW_PRNG
 
+#define MCUXCLCSS_STATUS_IS_HW_ERROR
 
+#define MCUXCLCSS_STATUS_IS_SW_ERROR
 
+#define MCUXCLCSS_STATUS_OK
 
+#define MCUXCLCSS_STATUS_OK_WAIT
 
+#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_NONSECURE
 
+#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_SECURE
 
+#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
 
+#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_SECURE
 
+#define MCUXCLCSS_STATUS_SW_CANNOT_INTERRUPT
 
+#define MCUXCLCSS_STATUS_SW_COMPARISON_FAILED
 
+#define MCUXCLCSS_STATUS_SW_COUNTER_EXPIRED
 
+#define MCUXCLCSS_STATUS_SW_FAULT
 
+#define MCUXCLCSS_STATUS_SW_INVALID_PARAM
 
+#define MCUXCLCSS_STATUS_SW_INVALID_STATE
 
+#define MCUXCLCSS_STATUS_SW_LOCKING_FAILED
 
+#define MCUXCLCSS_STATUS_SW_STATUS_LOCKED
 
+#define MCUXCLCSS_TLS_DERIVATIONDATA_SIZE
 
+#define MCUXCLCSS_TLS_FINALIZE
 
+#define MCUXCLCSS_TLS_INIT
 
+#define MCUXCLCSS_TLS_RANDOM_SIZE
 
#define mcuxClCss_AeadOption_t
 mcuxClCss_((?:AeadOption_t|CipherOption_t|CkdfOption_t|CmacOption_t|CommandCrcConfig_t|EccByte_t|EccKeyExchOption_t|EccKeyGenOption_t|EccSignOption_t|EccVerifyOption_t|ErrorHandling_t|HashOption_t|HkdfOption_t|HmacOption_t|HwConfig_t|HwState_t|HwVersion_t|InterruptOptionEn_t|InterruptOptionRst_t|InterruptOptionSet_t|KeyImportOption_t|KeyIndex_t|KeyProp_t|KeyProvisionOption_t|ResetOption_t|Status_Protected_t|Status_t|TlsOption_t|TransferToRegisterFunction_t))(?!\w) --> mcuxClEls_\1 More...
 
+#define mcuxClCss_CipherOption_t
 
+#define mcuxClCss_CkdfOption_t
 
+#define mcuxClCss_CmacOption_t
 
+#define mcuxClCss_CommandCrcConfig_t
 
+#define mcuxClCss_EccByte_t
 
+#define mcuxClCss_EccKeyExchOption_t
 
+#define mcuxClCss_EccKeyGenOption_t
 
+#define mcuxClCss_EccSignOption_t
 
+#define mcuxClCss_EccVerifyOption_t
 
+#define mcuxClCss_ErrorHandling_t
 
+#define mcuxClCss_HashOption_t
 
+#define mcuxClCss_HkdfOption_t
 
+#define mcuxClCss_HmacOption_t
 
+#define mcuxClCss_HwConfig_t
 
+#define mcuxClCss_HwState_t
 
+#define mcuxClCss_HwVersion_t
 
+#define mcuxClCss_InterruptOptionEn_t
 
+#define mcuxClCss_InterruptOptionRst_t
 
+#define mcuxClCss_InterruptOptionSet_t
 
+#define mcuxClCss_KeyImportOption_t
 
+#define mcuxClCss_KeyIndex_t
 
+#define mcuxClCss_KeyProp_t
 
+#define mcuxClCss_KeyProvisionOption_t
 
+#define mcuxClCss_ResetOption_t
 
+#define mcuxClCss_Status_Protected_t
 
+#define mcuxClCss_Status_t
 
+#define mcuxClCss_TlsOption_t
 
+#define mcuxClCss_TransferToRegisterFunction_t
 
#define mcuxClCss_Aead_Finalize_Async
 mcuxClCss_((?:Aead_Finalize_Async|Aead_Init_Async|Aead_PartialInit_Async|Aead_UpdateAad_Async|Aead_UpdateData_Async|Cipher_Async|Ckdf_Sp800108_Async|Ckdf_Sp80056c_Expand_Async|Ckdf_Sp80056c_Extract_Async|Cmac_Async|CompareDmaFinalOutputAddress|ConfigureCommandCRC|Disable|EccKeyExchangeInt_Async|EccKeyExchange_Async|EccKeyGen_Async|EccSign_Async|EccVerifyInt_Async|EccVerify_Async|Enable_Async|GetCommandCRC|GetErrorCode|GetErrorLevel|GetHwConfig|GetHwState|GetHwVersion|GetIntEnableFlags|GetKeyProperties|GetLastDmaAddress|GetLock|GetRandomStartDelay|GlitchDetector_GetEventCounter|GlitchDetector_LoadConfig_Async|GlitchDetector_ResetEventCounter|GlitchDetector_Trim_Async|Hash_Async|Hash_ShaDirect|Hkdf_Rfc5869_Async|Hkdf_Sp80056c_Async|Hmac_Async|IsLocked|KeyDelete_Async|KeyExport_Async|KeyImportPuk_Async|KeyImport_Async|KeyProvisionRom_Async|KeyProvision_Async|LimitedWaitForOperation|Prng_GetRandom|Prng_GetRandomWord|Prng_Init_Async|ReleaseLock|ResetErrorFlags|ResetIntFlags|Reset_Async|RespGen_Async|Rng_DrbgRequestRaw_Async|Rng_DrbgRequest_Async|Rng_DrbgTestAesCtr_Async|Rng_DrbgTestAesEcb_Async|Rng_DrbgTestExtract_Async|Rng_DrbgTestInstantiate_Async|Rng_Dtrng_ConfigEvaluate_Async|Rng_Dtrng_ConfigLoadPrv_Async|Rng_Dtrng_ConfigLoad_Async|SetIntEnableFlags|SetIntFlags|SetMasterUnlock|SetRandomStartDelay|ShaDirect_Disable|ShaDirect_Enable|TlsGenerateMasterKeyFromPreMasterKey_Async|TlsGenerateSessionKeysFromMasterKey_Async|UpdateRefCRC|VerifyVsRefCRC|WaitForOperation))(?!\w) --> mcuxClEls_\1 More...
 
+#define mcuxClCss_Aead_Init_Async
 
+#define mcuxClCss_Aead_PartialInit_Async
 
+#define mcuxClCss_Aead_UpdateAad_Async
 
+#define mcuxClCss_Aead_UpdateData_Async
 
+#define mcuxClCss_Cipher_Async
 
+#define mcuxClCss_Ckdf_Sp800108_Async
 
+#define mcuxClCss_Ckdf_Sp80056c_Expand_Async
 
+#define mcuxClCss_Ckdf_Sp80056c_Extract_Async
 
+#define mcuxClCss_Cmac_Async
 
+#define mcuxClCss_CompareDmaFinalOutputAddress
 
+#define mcuxClCss_ConfigureCommandCRC
 
+#define mcuxClCss_Disable
 
+#define mcuxClCss_EccKeyExchangeInt_Async
 
+#define mcuxClCss_EccKeyExchange_Async
 
+#define mcuxClCss_EccKeyGen_Async
 
+#define mcuxClCss_EccSign_Async
 
+#define mcuxClCss_EccVerifyInt_Async
 
+#define mcuxClCss_EccVerify_Async
 
+#define mcuxClCss_Enable_Async
 
+#define mcuxClCss_GetCommandCRC
 
+#define mcuxClCss_GetErrorCode
 
+#define mcuxClCss_GetErrorLevel
 
+#define mcuxClCss_GetHwConfig
 
+#define mcuxClCss_GetHwState
 
+#define mcuxClCss_GetHwVersion
 
+#define mcuxClCss_GetIntEnableFlags
 
+#define mcuxClCss_GetKeyProperties
 
+#define mcuxClCss_GetLastDmaAddress
 
+#define mcuxClCss_GetLock
 
+#define mcuxClCss_GetRandomStartDelay
 
+#define mcuxClCss_GlitchDetector_GetEventCounter
 
+#define mcuxClCss_GlitchDetector_LoadConfig_Async
 
+#define mcuxClCss_GlitchDetector_ResetEventCounter
 
+#define mcuxClCss_GlitchDetector_Trim_Async
 
+#define mcuxClCss_Hash_Async
 
+#define mcuxClCss_Hash_ShaDirect
 
+#define mcuxClCss_Hkdf_Rfc5869_Async
 
+#define mcuxClCss_Hkdf_Sp80056c_Async
 
+#define mcuxClCss_Hmac_Async
 
+#define mcuxClCss_IsLocked
 
+#define mcuxClCss_KeyDelete_Async
 
+#define mcuxClCss_KeyExport_Async
 
+#define mcuxClCss_KeyImportPuk_Async
 
+#define mcuxClCss_KeyImport_Async
 
+#define mcuxClCss_KeyProvisionRom_Async
 
+#define mcuxClCss_KeyProvision_Async
 
+#define mcuxClCss_LimitedWaitForOperation
 
+#define mcuxClCss_Prng_GetRandom
 
+#define mcuxClCss_Prng_GetRandomWord
 
+#define mcuxClCss_Prng_Init_Async
 
+#define mcuxClCss_ReleaseLock
 
+#define mcuxClCss_ResetErrorFlags
 
+#define mcuxClCss_ResetIntFlags
 
+#define mcuxClCss_Reset_Async
 
+#define mcuxClCss_RespGen_Async
 
+#define mcuxClCss_Rng_DrbgRequestRaw_Async
 
+#define mcuxClCss_Rng_DrbgRequest_Async
 
+#define mcuxClCss_Rng_DrbgTestAesCtr_Async
 
+#define mcuxClCss_Rng_DrbgTestAesEcb_Async
 
+#define mcuxClCss_Rng_DrbgTestExtract_Async
 
+#define mcuxClCss_Rng_DrbgTestInstantiate_Async
 
+#define mcuxClCss_Rng_Dtrng_ConfigEvaluate_Async
 
+#define mcuxClCss_Rng_Dtrng_ConfigLoadPrv_Async
 
+#define mcuxClCss_Rng_Dtrng_ConfigLoad_Async
 
+#define mcuxClCss_SetIntEnableFlags
 
+#define mcuxClCss_SetIntFlags
 
+#define mcuxClCss_SetMasterUnlock
 
+#define mcuxClCss_SetRandomStartDelay
 
+#define mcuxClCss_ShaDirect_Disable
 
+#define mcuxClCss_ShaDirect_Enable
 
+#define mcuxClCss_TlsGenerateMasterKeyFromPreMasterKey_Async
 
+#define mcuxClCss_TlsGenerateSessionKeysFromMasterKey_Async
 
+#define mcuxClCss_UpdateRefCRC
 
+#define mcuxClCss_VerifyVsRefCRC
 
+#define mcuxClCss_WaitForOperation
 
+

Detailed Description

+

Header providing mapping for legacy function/definition names (with CSS)

+

Macro Definition Documentation

+ +

◆ MCUXCLCSS_API

+ +
+
+ + + + +
#define MCUXCLCSS_API
+
+ +

MCUXCLCSS_CSS_((?:INTERRUPT_DISABLE|INTERRUPT_ENABLE|INTERRUPT_KEEP|INTERRUPT_SET|RESET_CLEAR|RESET_KEEP))(?!\w) --> MCUXCLELS_ELS_\1.

+

MCUXCLCSS_((?:API|AEAD_AAD_BLOCK_SIZE|AEAD_ACPMOD_AADPROC|AEAD_ACPMOD_FINAL|AEAD_ACPMOD_INIT|AEAD_ACPMOD_MSGPROC|AEAD_CONTEXT_SIZE|AEAD_DECRYPT|AEAD_ENCRYPT|AEAD_EXTERN_KEY|AEAD_INTERN_KEY|AEAD_IV_BLOCK_SIZE|AEAD_LASTINIT_FALSE|AEAD_LASTINIT_TRUE|AEAD_STATE_IN_DISABLE|AEAD_STATE_IN_ENABLE|AEAD_STATE_OUT_ENABLE|AEAD_TAG_SIZE|CIPHERPARAM_ALGORITHM_AES_CBC|CIPHERPARAM_ALGORITHM_AES_CTR|CIPHERPARAM_ALGORITHM_AES_ECB|CIPHER_BLOCK_SIZE_AES|CIPHER_DECRYPT|CIPHER_ENCRYPT|CIPHER_EXTERNAL_KEY|CIPHER_INTERNAL_KEY|CIPHER_KEY_SIZE_AES_128|CIPHER_KEY_SIZE_AES_192|CIPHER_KEY_SIZE_AES_256|CIPHER_STATE_IN_DISABLE|CIPHER_STATE_IN_ENABLE|CIPHER_STATE_OUT_DISABLE|CIPHER_STATE_OUT_ENABLE|CKDF_ALGO_SP800108|CKDF_ALGO_SP80056C_EXPAND|CKDF_ALGO_SP80056C_EXTRACT|CKDF_DERIVATIONDATA_SIZE|CKDF_RTF_DERIV|CKDF_SP80056C_DERIVATIONDATA_SIZE_16|CKDF_SP80056C_DERIVATIONDATA_SIZE_32|CKDF_SYSTEM_MEMORY_DERIV|CMAC_EXTERNAL_KEY_DISABLE|CMAC_EXTERNAL_KEY_ENABLE|CMAC_FINALIZE_DISABLE|CMAC_FINALIZE_ENABLE|CMAC_INITIALIZE_DISABLE|CMAC_INITIALIZE_ENABLE|CMAC_KEY_SIZE_128|CMAC_KEY_SIZE_256|CMAC_OUT_SIZE))(?!\w) MCUXCLCSS_((?:CMD_CRC_CMD_ID_AUTH_CIPHER|CMD_CRC_CMD_ID_CHAL_RESP_GEN|CMD_CRC_CMD_ID_CIPHER|CMD_CRC_CMD_ID_CKDF|CMD_CRC_CMD_ID_CMAC|CMD_CRC_CMD_ID_DRBG_TEST|CMD_CRC_CMD_ID_DTRNG_CFG_LOAD|CMD_CRC_CMD_ID_DTRNG_EVAL|CMD_CRC_CMD_ID_ECKXH|CMD_CRC_CMD_ID_ECSIGN|CMD_CRC_CMD_ID_ECVFY|CMD_CRC_CMD_ID_GDET_CFG_LOAD|CMD_CRC_CMD_ID_GDET_TRIM|CMD_CRC_CMD_ID_HASH|CMD_CRC_CMD_ID_HKDF|CMD_CRC_CMD_ID_HMAC|CMD_CRC_CMD_ID_KDELETE|CMD_CRC_CMD_ID_KEYGEN|CMD_CRC_CMD_ID_KEYIN|CMD_CRC_CMD_ID_KEYOUT|CMD_CRC_CMD_ID_KEYPROV|CMD_CRC_CMD_ID_RND_REQ|CMD_CRC_CMD_ID_TLS|CMD_CRC_DISABLE|CMD_CRC_ENABLE|CMD_CRC_INITIAL_VALUE|CMD_CRC_POLYNOMIAL|CMD_CRC_REFERENCE_INIT|CMD_CRC_REFERENCE_RESET|CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE|CMD_CRC_REFERENCE_UPDATE_AEAD_INIT|CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA|CMD_CRC_REFERENCE_UPDATE_CIPHER|CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT|CMD_CRC_REFERENCE_UPDATE_CMAC))(?!\w) MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE|CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT|CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN|CMD_CRC_REFERENCE_UPDATE_ECCSIGN|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM|CMD_CRC_REFERENCE_UPDATE_HASH|CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869|CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C|CMD_CRC_REFERENCE_UPDATE_HMAC|CMD_CRC_REFERENCE_UPDATE_KEYDELETE|CMD_CRC_REFERENCE_UPDATE_KEYEXPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK|CMD_CRC_REFERENCE_UPDATE_KEYPROVISION|CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM|CMD_CRC_REFERENCE_UPDATE_PRNG_INIT|CMD_CRC_REFERENCE_UPDATE_RESPGEN|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE|CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE))(?!\w) MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD|CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY|CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY|CMD_CRC_RESET|CMD_CRC_VALUE_DISABLE|CMD_CRC_VALUE_ENABLE|CMD_CRC_VALUE_RESET|DMA_READBACK_PROTECTION_TOKEN|ECC_EXTKEY_EXTERNAL|ECC_EXTKEY_INTERNAL|ECC_GEN_PUBLIC_KEY|ECC_HASHED|ECC_INCLUDE_RANDOM_DATA|ECC_NOT_HASHED|ECC_NO_RANDOM_DATA|ECC_NO_RTF|ECC_OUTPUTKEY_DETERMINISTIC|ECC_OUTPUTKEY_KEYEXCHANGE|ECC_OUTPUTKEY_RANDOM|ECC_OUTPUTKEY_SIGN|ECC_PUBLICKEY_SIGN_DISABLE|ECC_PUBLICKEY_SIGN_ENABLE|ECC_PUBLICKEY_SIZE|ECC_REVERSEFETCH_DISABLE|ECC_REVERSEFETCH_ENABLE|ECC_RTF|ECC_SIGNATURE_R_SIZE|ECC_SIGNATURE_SIZE|ECC_SKIP_PUBLIC_KEY|ECC_VALUE_HASHED|ECC_VALUE_NOT_HASHED|ECC_VALUE_NO_RTF|ECC_VALUE_RTF|ERROR_FLAGS_CLEAR|ERROR_FLAGS_KEEP|GLITCHDETECTOR_CFG_SIZE|GLITCHDETECTOR_TRIM_SIZE|GLITCH_DETECTOR_INTERRUPT_DISABLE|GLITCH_DETECTOR_INTERRUPT_ENABLE|GLITCH_DETECTOR_NEG_KEEP))(?!\w) MCUXCLCSS_((?:GLITCH_DETECTOR_NEG_SET|GLITCH_DETECTOR_POS_KEEP|GLITCH_DETECTOR_POS_SET|GLITCH_DETECTOR_RESET_CLEAR|GLITCH_DETECTOR_RESET_KEEP|HASH_BLOCK_SIZE_SHA_224|HASH_BLOCK_SIZE_SHA_256|HASH_BLOCK_SIZE_SHA_384|HASH_BLOCK_SIZE_SHA_512|HASH_INIT_DISABLE|HASH_INIT_ENABLE|HASH_LOAD_DISABLE|HASH_LOAD_ENABLE|HASH_MODE_SHA_224|HASH_MODE_SHA_256|HASH_MODE_SHA_384|HASH_MODE_SHA_512|HASH_OUTPUT_DISABLE|HASH_OUTPUT_ENABLE|HASH_OUTPUT_SIZE_SHA_224|HASH_OUTPUT_SIZE_SHA_256|HASH_OUTPUT_SIZE_SHA_384|HASH_OUTPUT_SIZE_SHA_512|HASH_RTF_OUTPUT_DISABLE|HASH_RTF_OUTPUT_ENABLE|HASH_RTF_OUTPUT_SIZE|HASH_RTF_UPDATE_DISABLE|HASH_RTF_UPDATE_ENABLE|HASH_STATE_SIZE_SHA_224|HASH_STATE_SIZE_SHA_256|HASH_STATE_SIZE_SHA_384|HASH_STATE_SIZE_SHA_512|HASH_VALUE_MODE_SHA_224|HASH_VALUE_MODE_SHA_256|HASH_VALUE_MODE_SHA_384|HASH_VALUE_MODE_SHA_512|HKDF_ALGO_RFC5869|HKDF_ALGO_SP80056C|HKDF_RFC5869_DERIVATIONDATA_SIZE|HKDF_SP80056C_TARGETKEY_SIZE|HKDF_VALUE_MEMORY_DERIV|HKDF_VALUE_RTF_DERIV|HMAC_EXTERNAL_KEY_DISABLE|HMAC_EXTERNAL_KEY_ENABLE|HMAC_OUTPUT_SIZE|HMAC_PADDED_KEY_SIZE|HW_VERSION))(?!\w) MCUXCLCSS_((?:KEYGEN_VALUE_DETERMINISTIC|KEYGEN_VALUE_GEN_PUB_KEY|KEYGEN_VALUE_NO_PUB_KEY|KEYGEN_VALUE_NO_RANDOM_DATA|KEYGEN_VALUE_RANDOM|KEYGEN_VALUE_SIGN_PUBLICKEY|KEYGEN_VALUE_TYPE_KEYEXCHANGE|KEYGEN_VALUE_TYPE_SIGN|KEYGEN_VALUE_USE_RANDOM_DATA|KEYIMPORT_KFMT_PBK|KEYIMPORT_KFMT_PUF|KEYIMPORT_KFMT_RFC3394|KEYIMPORT_KFMT_UDF|KEYIMPORT_REVERSEFETCH_DISABLE|KEYIMPORT_REVERSEFETCH_ENABLE|KEYIMPORT_VALUE_KFMT_PBK|KEYIMPORT_VALUE_KFMT_PUF|KEYIMPORT_VALUE_KFMT_RFC3394|KEYIMPORT_VALUE_KFMT_UDF|KEYPROPERTY_ACTIVE_FALSE|KEYPROPERTY_ACTIVE_TRUE|KEYPROPERTY_AES_FALSE|KEYPROPERTY_AES_TRUE|KEYPROPERTY_BASE_SLOT|KEYPROPERTY_CKDF_FALSE|KEYPROPERTY_CKDF_TRUE|KEYPROPERTY_CMAC_FALSE|KEYPROPERTY_CMAC_TRUE|KEYPROPERTY_DEVICE_UNIQUE_FALSE|KEYPROPERTY_DEVICE_UNIQUE_TRUE|KEYPROPERTY_ECC_DH_PRIVATE_FALSE|KEYPROPERTY_ECC_DH_PRIVATE_TRUE|KEYPROPERTY_ECC_FALSE|KEYPROPERTY_ECC_TRUE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE|KEYPROPERTY_HKDF_FALSE|KEYPROPERTY_HKDF_TRUE|KEYPROPERTY_HMAC_FALSE|KEYPROPERTY_HMAC_TRUE|KEYPROPERTY_HW_OUT_FALSE|KEYPROPERTY_HW_OUT_SLOT_FALSE))(?!\w) MCUXCLCSS_((?:KEYPROPERTY_HW_OUT_SLOT_TRUE|KEYPROPERTY_HW_OUT_TRUE|KEYPROPERTY_INPUT_FOR_ECC_FALSE|KEYPROPERTY_INPUT_FOR_ECC_TRUE|KEYPROPERTY_KEY_SIZE_128|KEYPROPERTY_KEY_SIZE_256|KEYPROPERTY_KEY_SIZE_512|KEYPROPERTY_KSK_FALSE|KEYPROPERTY_KSK_TRUE|KEYPROPERTY_KUOK_FALSE|KEYPROPERTY_KUOK_TRUE|KEYPROPERTY_KWK_FALSE|KEYPROPERTY_KWK_TRUE|KEYPROPERTY_PRIVILEGED_FALSE|KEYPROPERTY_PRIVILEGED_TRUE|KEYPROPERTY_PUK_FALSE|KEYPROPERTY_PUK_TRUE|KEYPROPERTY_RETENTION_SLOT_FALSE|KEYPROPERTY_RETENTION_SLOT_TRUE|KEYPROPERTY_RTF_FALSE|KEYPROPERTY_RTF_TRUE|KEYPROPERTY_SECOND_SLOT|KEYPROPERTY_SECURE_FALSE|KEYPROPERTY_SECURE_TRUE|KEYPROPERTY_TECDH_FALSE|KEYPROPERTY_TECDH_TRUE|KEYPROPERTY_TLS_MASTER_SECRET_FALSE|KEYPROPERTY_TLS_MASTER_SECRET_TRUE|KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE|KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE|KEYPROPERTY_VALUE_ACTIVE|KEYPROPERTY_VALUE_AES|KEYPROPERTY_VALUE_BASE_SLOT|KEYPROPERTY_VALUE_CKDF|KEYPROPERTY_VALUE_CMAC|KEYPROPERTY_VALUE_DUK|KEYPROPERTY_VALUE_ECDH|KEYPROPERTY_VALUE_ECSGN|KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT|KEYPROPERTY_VALUE_HKDF|KEYPROPERTY_VALUE_HMAC))(?!\w) MCUXCLCSS_((?:KEYPROPERTY_VALUE_HW_OUT|KEYPROPERTY_VALUE_HW_OUT_SLOT|KEYPROPERTY_VALUE_KEY_SIZE_128|KEYPROPERTY_VALUE_KEY_SIZE_256|KEYPROPERTY_VALUE_KEY_SIZE_512|KEYPROPERTY_VALUE_KGSRC|KEYPROPERTY_VALUE_KSK|KEYPROPERTY_VALUE_KUOK|KEYPROPERTY_VALUE_KWK|KEYPROPERTY_VALUE_NOTPRIVILEGED|KEYPROPERTY_VALUE_NOTSECURE|KEYPROPERTY_VALUE_PRIVILEGED|KEYPROPERTY_VALUE_PUK|KEYPROPERTY_VALUE_RETENTION_SLOT|KEYPROPERTY_VALUE_RTF|KEYPROPERTY_VALUE_SECURE|KEYPROPERTY_VALUE_TECDH|KEYPROPERTY_VALUE_TLS_MASTER_SECRET|KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET|KEYPROPERTY_VALUE_WRPOK|KEYPROPERTY_WRAP_FALSE|KEYPROPERTY_WRAP_TRUE|KEYPROV_DUK_UPDATE_DISABLE|KEYPROV_DUK_UPDATE_ENABLE|KEYPROV_KEYSHARE_TABLE_SIZE|KEYPROV_KEY_PART_1_SIZE|KEYPROV_NOIC_DISABLE|KEYPROV_NOIC_ENABLE|KEYPROV_TESTERSHARE_SIZE|KEYPROV_VALUE_NOIC|KEY_SLOTS|MASTER_UNLOCK_ANY|RESET_CANCEL|RESET_DO_NOT_CANCEL|RESP_GEN_AVAILABLE_SLOT_0|RESP_GEN_AVAILABLE_SLOT_1|RESP_GEN_AVAILABLE_SLOT_2|RESP_GEN_SLOTS|RFC3394_CONTAINER_SIZE_128|RFC3394_CONTAINER_SIZE_256|RFC3394_CONTAINER_SIZE_P256|RFC3394_OVERHEAD|RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE))(?!\w) MCUXCLCSS_((?:RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE|RNG_DRBG_TEST_MODE_AES_CTR|RNG_DRBG_TEST_MODE_AES_ECB|RNG_DRBG_TEST_MODE_EXTRACT|RNG_DRBG_TEST_MODE_INSTANTIATE|RNG_DTRNG_CONFIG_SIZE|RNG_DTRNG_EVAL_CONFIG_SIZE|RNG_DTRNG_EVAL_RESULT_SIZE|RNG_RAW_ENTROPY_SIZE|RNG_RND_REQ_PRND_INIT|RNG_RND_REQ_RND_RAW|STATUS_DRBGENTLVL_HIGH|STATUS_DRBGENTLVL_LOW|STATUS_DRBGENTLVL_NONE|STATUS_ECDSAVFY_ERROR|STATUS_ECDSAVFY_FAIL|STATUS_ECDSAVFY_NORUN|STATUS_ECDSAVFY_OK|STATUS_HW_ALGORITHM|STATUS_HW_BUS|STATUS_HW_DTRNG|STATUS_HW_FAULT|STATUS_HW_INTEGRITY|STATUS_HW_OPERATIONAL|STATUS_HW_PRNG|STATUS_IS_HW_ERROR|STATUS_IS_SW_ERROR|STATUS_OK|STATUS_OK_WAIT|STATUS_PPROT_PRIVILEGED_NONSECURE|STATUS_PPROT_PRIVILEGED_SECURE|STATUS_PPROT_UNPRIVILEGED_NONSECURE|STATUS_PPROT_UNPRIVILEGED_SECURE|STATUS_SW_CANNOT_INTERRUPT|STATUS_SW_COMPARISON_FAILED|STATUS_SW_COUNTER_EXPIRED|STATUS_SW_FAULT|STATUS_SW_INVALID_PARAM|STATUS_SW_INVALID_STATE|STATUS_SW_LOCKING_FAILED|STATUS_SW_STATUS_LOCKED|TLS_DERIVATIONDATA_SIZE|TLS_FINALIZE|TLS_INIT|TLS_RANDOM_SIZE))(?!\w) --> MCUXCLELS_\1

+ +
+
+ +

◆ mcuxClCss_AeadOption_t

+ +
+
+ + + + +
#define mcuxClCss_AeadOption_t
+
+ +

mcuxClCss_((?:AeadOption_t|CipherOption_t|CkdfOption_t|CmacOption_t|CommandCrcConfig_t|EccByte_t|EccKeyExchOption_t|EccKeyGenOption_t|EccSignOption_t|EccVerifyOption_t|ErrorHandling_t|HashOption_t|HkdfOption_t|HmacOption_t|HwConfig_t|HwState_t|HwVersion_t|InterruptOptionEn_t|InterruptOptionRst_t|InterruptOptionSet_t|KeyImportOption_t|KeyIndex_t|KeyProp_t|KeyProvisionOption_t|ResetOption_t|Status_Protected_t|Status_t|TlsOption_t|TransferToRegisterFunction_t))(?!\w) --> mcuxClEls_\1

+ +
+
+ +

◆ mcuxClCss_Aead_Finalize_Async

+ +
+
+ + + + +
#define mcuxClCss_Aead_Finalize_Async
+
+ +

mcuxClCss_((?:Aead_Finalize_Async|Aead_Init_Async|Aead_PartialInit_Async|Aead_UpdateAad_Async|Aead_UpdateData_Async|Cipher_Async|Ckdf_Sp800108_Async|Ckdf_Sp80056c_Expand_Async|Ckdf_Sp80056c_Extract_Async|Cmac_Async|CompareDmaFinalOutputAddress|ConfigureCommandCRC|Disable|EccKeyExchangeInt_Async|EccKeyExchange_Async|EccKeyGen_Async|EccSign_Async|EccVerifyInt_Async|EccVerify_Async|Enable_Async|GetCommandCRC|GetErrorCode|GetErrorLevel|GetHwConfig|GetHwState|GetHwVersion|GetIntEnableFlags|GetKeyProperties|GetLastDmaAddress|GetLock|GetRandomStartDelay|GlitchDetector_GetEventCounter|GlitchDetector_LoadConfig_Async|GlitchDetector_ResetEventCounter|GlitchDetector_Trim_Async|Hash_Async|Hash_ShaDirect|Hkdf_Rfc5869_Async|Hkdf_Sp80056c_Async|Hmac_Async|IsLocked|KeyDelete_Async|KeyExport_Async|KeyImportPuk_Async|KeyImport_Async|KeyProvisionRom_Async|KeyProvision_Async|LimitedWaitForOperation|Prng_GetRandom|Prng_GetRandomWord|Prng_Init_Async|ReleaseLock|ResetErrorFlags|ResetIntFlags|Reset_Async|RespGen_Async|Rng_DrbgRequestRaw_Async|Rng_DrbgRequest_Async|Rng_DrbgTestAesCtr_Async|Rng_DrbgTestAesEcb_Async|Rng_DrbgTestExtract_Async|Rng_DrbgTestInstantiate_Async|Rng_Dtrng_ConfigEvaluate_Async|Rng_Dtrng_ConfigLoadPrv_Async|Rng_Dtrng_ConfigLoad_Async|SetIntEnableFlags|SetIntFlags|SetMasterUnlock|SetRandomStartDelay|ShaDirect_Disable|ShaDirect_Enable|TlsGenerateMasterKeyFromPreMasterKey_Async|TlsGenerateSessionKeysFromMasterKey_Async|UpdateRefCRC|VerifyVsRefCRC|WaitForOperation))(?!\w) --> mcuxClEls_\1

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00326.js b/components/els_pkc/doc/mcxn/html/a00326.js new file mode 100644 index 000000000..b96369177 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00326.js @@ -0,0 +1,488 @@ +var a00326 = +[ + [ "MCUXCLCSS_API", "a00326.html#a943265c1ad7bb3d4163f108994aa7958", null ], + [ "MCUXCLCSS_AEAD_AAD_BLOCK_SIZE", "a00326.html#ac07990407d0cbe0747651212c50e291e", null ], + [ "MCUXCLCSS_AEAD_ACPMOD_AADPROC", "a00326.html#a49af3d4b982be6ef34865a334a827ce2", null ], + [ "MCUXCLCSS_AEAD_ACPMOD_FINAL", "a00326.html#a175a96e2a33dd4715d0d8cba36b4a98d", null ], + [ "MCUXCLCSS_AEAD_ACPMOD_INIT", "a00326.html#aef9ac0ea919f3d7cae276e7c4c185395", null ], + [ "MCUXCLCSS_AEAD_ACPMOD_MSGPROC", "a00326.html#a87215048ff470b9181bcae493543c56a", null ], + [ "MCUXCLCSS_AEAD_CONTEXT_SIZE", "a00326.html#ac865f4bef955cb6f180c48023005b394", null ], + [ "MCUXCLCSS_AEAD_DECRYPT", "a00326.html#a6fa54f09aa5a8ab7a7035d801192e134", null ], + [ "MCUXCLCSS_AEAD_ENCRYPT", "a00326.html#ae6a5dd43d303ed82ba164b77f7c72fcd", null ], + [ "MCUXCLCSS_AEAD_EXTERN_KEY", "a00326.html#af7487d1da09472a338c6c2dc2837d44e", null ], + [ "MCUXCLCSS_AEAD_INTERN_KEY", "a00326.html#a808c6b23b3ec90ab9332dfbe02355022", null ], + [ "MCUXCLCSS_AEAD_IV_BLOCK_SIZE", "a00326.html#af1cd65ede10c597d80ccd53e568613c8", null ], + [ "MCUXCLCSS_AEAD_LASTINIT_FALSE", "a00326.html#aac5500d7132902a34d7b93945019aec3", null ], + [ "MCUXCLCSS_AEAD_LASTINIT_TRUE", "a00326.html#a5bdda1c54a413cdf08174cb6c01a8ee6", null ], + [ "MCUXCLCSS_AEAD_STATE_IN_DISABLE", "a00326.html#adffcee7e129d4d4a7aa73ff41336493f", null ], + [ "MCUXCLCSS_AEAD_STATE_IN_ENABLE", "a00326.html#aed4093ec6b9149c8171b8b0d41120fcb", null ], + [ "MCUXCLCSS_AEAD_STATE_OUT_ENABLE", "a00326.html#a39c8b1642274423044c21b1a5ed49f8b", null ], + [ "MCUXCLCSS_AEAD_TAG_SIZE", "a00326.html#a3e045e77a1c636d5a8730732b78719e3", null ], + [ "MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CBC", "a00326.html#adac26b2772748ef907252d6927fdf0d3", null ], + [ "MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CTR", "a00326.html#ac864ddc8a0beae89337673dac8d795de", null ], + [ "MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB", "a00326.html#a9f8e04d6c8bbbf37653b9cb255bde9a4", null ], + [ "MCUXCLCSS_CIPHER_BLOCK_SIZE_AES", "a00326.html#a197b36d7f9dbb6dade5f56f37190de1a", null ], + [ "MCUXCLCSS_CIPHER_DECRYPT", "a00326.html#a1331ccf646df70f20b261a7a79deb82e", null ], + [ "MCUXCLCSS_CIPHER_ENCRYPT", "a00326.html#aeac4a6baaf2e90924b3bc6dce8292fb7", null ], + [ "MCUXCLCSS_CIPHER_EXTERNAL_KEY", "a00326.html#aecf1cf5a727b0e877f517b5f4512ff0c", null ], + [ "MCUXCLCSS_CIPHER_INTERNAL_KEY", "a00326.html#a75f847396e290215ff3326c3c8d6868f", null ], + [ "MCUXCLCSS_CIPHER_KEY_SIZE_AES_128", "a00326.html#a1699d287480c4f9dd826b32438f4a165", null ], + [ "MCUXCLCSS_CIPHER_KEY_SIZE_AES_192", "a00326.html#a96c0f92563ed9d3bab268451570ff45f", null ], + [ "MCUXCLCSS_CIPHER_KEY_SIZE_AES_256", "a00326.html#aabf1cf32c4cdafa8475c0f275d96a184", null ], + [ "MCUXCLCSS_CIPHER_STATE_IN_DISABLE", "a00326.html#af2ffbb11b59ce50bfc4c3bda31908813", null ], + [ "MCUXCLCSS_CIPHER_STATE_IN_ENABLE", "a00326.html#a38294183b4f9f66dd24a4c9bf0743816", null ], + [ "MCUXCLCSS_CIPHER_STATE_OUT_DISABLE", "a00326.html#a6cd2df3fdedc0f43a3f9d815d9ce3343", null ], + [ "MCUXCLCSS_CIPHER_STATE_OUT_ENABLE", "a00326.html#a57af57a11ede8cf2abab5111a4c02f8c", null ], + [ "MCUXCLCSS_CKDF_ALGO_SP800108", "a00326.html#a9defd7abe573bb2080e752b0648b8a5b", null ], + [ "MCUXCLCSS_CKDF_ALGO_SP80056C_EXPAND", "a00326.html#ae51c706fbf07d6ff45f4ef0b2bfc9b7b", null ], + [ "MCUXCLCSS_CKDF_ALGO_SP80056C_EXTRACT", "a00326.html#a4be4f08a2b2f4bde868bb1b9d6a2d709", null ], + [ "MCUXCLCSS_CKDF_DERIVATIONDATA_SIZE", "a00326.html#a64b843ed1bb8df2599a8bbe58761b700", null ], + [ "MCUXCLCSS_HKDF_RTF_DERIV", "a00326.html#a3eb012d3c256c5d541b2e13fb14e837f", null ], + [ "MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16", "a00326.html#a55c01a52bae710d5230789efc3470550", null ], + [ "MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32", "a00326.html#a64d6aa6e9bcd47621e27668f7c25623e", null ], + [ "MCUXCLCSS_HKDF_SYSTEM_MEMORY_DERIV", "a00326.html#ad7859d622d9fbf78234ba74d4f6353ab", null ], + [ "MCUXCLCSS_CMAC_EXTERNAL_KEY_DISABLE", "a00326.html#aa463d6b0f259e56d029ea2141085a754", null ], + [ "MCUXCLCSS_CMAC_EXTERNAL_KEY_ENABLE", "a00326.html#abd05adb49b59d1d6ae7a4dec8b749345", null ], + [ "MCUXCLCSS_CMAC_FINALIZE_DISABLE", "a00326.html#a32e238cc83184f43849da1d6e1781e2f", null ], + [ "MCUXCLCSS_CMAC_FINALIZE_ENABLE", "a00326.html#a38075a52c17aa3f57cf1f6aaaa255e79", null ], + [ "MCUXCLCSS_CMAC_INITIALIZE_DISABLE", "a00326.html#a4464e301220c18d5e078eb2ef1293d40", null ], + [ "MCUXCLCSS_CMAC_INITIALIZE_ENABLE", "a00326.html#a7a6d826fccaffd1e1fa0d7496b29971e", null ], + [ "MCUXCLCSS_CMAC_KEY_SIZE_128", "a00326.html#a37cee6fbcb9fc11d1663df5e10c9e9d4", null ], + [ "MCUXCLCSS_CMAC_KEY_SIZE_256", "a00326.html#a25764b96504304f4c75d5d5b636c0268", null ], + [ "MCUXCLCSS_CMAC_OUT_SIZE", "a00326.html#a4aca1c01b0dffee12ecb8a8fdf6996bf", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_AUTH_CIPHER", "a00326.html#a92945eb20ffa979b4add4e2c5703d3ec", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_CHAL_RESP_GEN", "a00326.html#a9e72923d3c37a731129ea449b07ffe14", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_CIPHER", "a00326.html#acb3456cf3f36c86635831deb4cfc4c16", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_CKDF", "a00326.html#a10f67b5e8757cb162f8f5851412eb73f", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_CMAC", "a00326.html#a79c27bbc3a54ea0871b6357b5766a9ac", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_DRBG_TEST", "a00326.html#a8f3a42f1a882cd3c84bc367d18ce41e8", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD", "a00326.html#ab9b331b429dfdea801567604f32546e2", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_EVAL", "a00326.html#ab7de362cb7e961f98a111497eaacaaba", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_ECKXH", "a00326.html#ad6f79743b63736084d06efcaf5bc714f", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_ECSIGN", "a00326.html#a906544d1264eb7373e1e668fe532d0b7", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_ECVFY", "a00326.html#ac5eeb71d7beed73e66777eac6ecd35df", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_GDET_CFG_LOAD", "a00326.html#a063fa78dba82ed5b4bffd0c0f7b9ef51", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_GDET_TRIM", "a00326.html#ab6c67a69e6e0975b076a6ab378f39ca2", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_HASH", "a00326.html#a04c16ea4ea9977fd2f14cfce718bc603", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_HKDF", "a00326.html#a0bd29ea962972bb246075c5e8dd3e1b1", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_HMAC", "a00326.html#acba86cb3d3a12a7ef7ca485f6aae9e3a", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_KDELETE", "a00326.html#a0c54107b84a2b9db6e397752616ccf66", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_KEYGEN", "a00326.html#a6f2290bbf15922574254082b730bca3c", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_KEYIN", "a00326.html#afdf7c60a4546c3e6382455d0cbf0e63f", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_KEYOUT", "a00326.html#a429b3b960bf2137c38dd535f72da6376", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_KEYPROV", "a00326.html#a950ca4312b536591bccadb111089a624", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_RND_REQ", "a00326.html#a3f02b09e85f8b2d6bdaaba249daf15eb", null ], + [ "MCUXCLCSS_CMD_CRC_CMD_ID_TLS", "a00326.html#a16f37615af1be9ac653fd0928a8fe8af", null ], + [ "MCUXCLCSS_CMD_CRC_DISABLE", "a00326.html#a30153cb9f088cb7b94855a0f97c99ad2", null ], + [ "MCUXCLCSS_CMD_CRC_ENABLE", "a00326.html#a902716b4eed29414ad8fd50cd3778964", null ], + [ "MCUXCLCSS_CMD_CRC_INITIAL_VALUE", "a00326.html#addd5cef5b27a2cf0e1a120e7f3d107f3", null ], + [ "MCUXCLCSS_CMD_CRC_POLYNOMIAL", "a00326.html#a5fecb350b5e9b30c314880fb3222111f", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_INIT", "a00326.html#a19a1c6e119f115213f0b20d8faafed6f", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_RESET", "a00326.html#a8522978a86cd8e0c57d3d26eb5cd2309", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE", "a00326.html#a2adedfd411f2dd7756c2dc3476e48b50", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT", "a00326.html#abb4ac34c5307a264ebc246e29e0fe8a5", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT", "a00326.html#af0d8875ed3933c317e2bf56c67fffdcc", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD", "a00326.html#ae238c67a71a763b72d3f3ddf9896db2b", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA", "a00326.html#ae770b9a4d3c6fc940b2de39d96367c82", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CIPHER", "a00326.html#a829b6c07cf88178dd4b97a8bd2f1f5f5", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108", "a00326.html#af897ab87d04892bc9006e7315d18e8c6", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND", "a00326.html#acccce4f96b7e397e28af9af8e5197513", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT", "a00326.html#a006b9eb5ca4fe0c12c666eb97903f821", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CMAC", "a00326.html#a9759b344d8a297cccf66fc194aee7dad", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE", "a00326.html#a8da18bcb0d7107ac7faa994052e98f72", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT", "a00326.html#a4817af52844ee9aba99a989e80bb3af5", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN", "a00326.html#a65540a0f1a40938916e96114ea2ad96f", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN", "a00326.html#abfdd4810f95ec35f2c35ea8188ee0852", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY", "a00326.html#a6ec60b1ea7624a3380af5b0315a188ab", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT", "a00326.html#acbb3576a5fdf286f30c4ab3d0be4741c", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG", "a00326.html#ab3f32b317590ac4152c1b1bc4a7e4e36", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM", "a00326.html#a7c01764061a3c24a1a64f55e9a0bd86b", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HASH", "a00326.html#ac839e1f20aff714878567e9b7638f6e8", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869", "a00326.html#a76eeb8d06839ea9c9c865e9bbd4e8921", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C", "a00326.html#aa773ced01ed66ba72eb7c53f049d3bed", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HMAC", "a00326.html#acc510c528a7a2ef5c9bebfe15dca3ac2", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE", "a00326.html#a5f6c3eaabe56459ccf33c7fb04dc13b6", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT", "a00326.html#aed84f9ccc8f525bfda652fd0f8b07842", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT", "a00326.html#a4160b08a1ab7a6b90ead5e0b86a68ac2", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK", "a00326.html#ae55c0a9bced435734ba7a06102ba1020", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION", "a00326.html#adcfe336be49923d52bd0f4af270d8043", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM", "a00326.html#a9c7ac6b700196bfd4ff0a21707f442b1", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT", "a00326.html#a2cd317b68ed977c7be7caa72c4bab3b5", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RESPGEN", "a00326.html#acef73de6e75ed0b861b966dca01f9bce", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST", "a00326.html#af6410c80aaa4e891e707f92a83404608", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW", "a00326.html#ae00792f86dc056dbeae70d16a9b1212f", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR", "a00326.html#af27cecc30fc9f6997e27e95645500880", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB", "a00326.html#a505f45de7d143278e6f44c4314522851", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT", "a00326.html#a6cd6081f63fd0d403fa93c4733cc3c20", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE", "a00326.html#a59a084122f90d26b15be2f9f76ca5e72", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE", "a00326.html#a570df95accad08acf62406bc8b5710fa", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD", "a00326.html#ac1878916b5f284cc27608a886e9ebc88", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY", "a00326.html#ad06bf5b037f25c1b82c60d7533a2dfbd", null ], + [ "MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY", "a00326.html#a04a5e5fcd0182522f392f0b0dab8103d", null ], + [ "MCUXCLCSS_CMD_CRC_RESET", "a00326.html#a716778f02882130dfd1b4c8f974f706e", null ], + [ "MCUXCLCSS_CMD_CRC_VALUE_DISABLE", "a00326.html#aafc6264eee6f651000a2ea2dab7a0219", null ], + [ "MCUXCLCSS_CMD_CRC_VALUE_ENABLE", "a00326.html#a8603d875caf53b87f9acfeedd89303a1", null ], + [ "MCUXCLCSS_CMD_CRC_VALUE_RESET", "a00326.html#a3f92ff6da9e5d4a3e3ec1af11c93a538", null ], + [ "MCUXCLCSS_CSS_INTERRUPT_DISABLE", "a00326.html#a255fdc21832cbb7b6b0d7c03f736165c", null ], + [ "MCUXCLCSS_CSS_INTERRUPT_ENABLE", "a00326.html#a2f2f54ba5272bef759dc485e4bc4a358", null ], + [ "MCUXCLCSS_CSS_INTERRUPT_KEEP", "a00326.html#ad00b1bae49c5ffa130a5873279ecdb2b", null ], + [ "MCUXCLCSS_CSS_INTERRUPT_SET", "a00326.html#aa5e94fd0213a8b7de68b0f6c5e1f8f2c", null ], + [ "MCUXCLCSS_CSS_RESET_CLEAR", "a00326.html#a33e132ea9a8fa4dd4c2caff33f1aa044", null ], + [ "MCUXCLCSS_CSS_RESET_KEEP", "a00326.html#aa4865b18dd46cbf4c4f809aba1d42464", null ], + [ "MCUXCLCSS_DMA_READBACK_PROTECTION_TOKEN", "a00326.html#acfb8228d7cc0a56c4fe0d0965c459b56", null ], + [ "MCUXCLCSS_ECC_EXTKEY_EXTERNAL", "a00326.html#a9ab0b9c5b2e539cca085dbcc47c94e75", null ], + [ "MCUXCLCSS_ECC_EXTKEY_INTERNAL", "a00326.html#a23dd445952ea18d05ab2c67dc5b916b5", null ], + [ "MCUXCLCSS_ECC_GEN_PUBLIC_KEY", "a00326.html#a0a39b27819589188ec5c0b399773df52", null ], + [ "MCUXCLCSS_ECC_HASHED", "a00326.html#a0bca97238cd68e1ca7b82781db17f02d", null ], + [ "MCUXCLCSS_ECC_INCLUDE_RANDOM_DATA", "a00326.html#ad306a4a317a11381736b41a87f72fd61", null ], + [ "MCUXCLCSS_ECC_NOT_HASHED", "a00326.html#aab22f0230352f12b79e5c89adb6c7b86", null ], + [ "MCUXCLCSS_ECC_NO_RANDOM_DATA", "a00326.html#a46a73bfafb4a28b4c3fc895b31e2227a", null ], + [ "MCUXCLCSS_ECC_NO_RTF", "a00326.html#a0c9f0c2945a6f3d607982ccf82ec64bd", null ], + [ "MCUXCLCSS_ECC_OUTPUTKEY_DETERMINISTIC", "a00326.html#a95c03b98675d5a680237a50aef73a963", null ], + [ "MCUXCLCSS_ECC_OUTPUTKEY_KEYEXCHANGE", "a00326.html#abce101ba79a9c03476a715b10fd3cfcb", null ], + [ "MCUXCLCSS_ECC_OUTPUTKEY_RANDOM", "a00326.html#a3477340cdfdf8081e74f042ab44b6dc5", null ], + [ "MCUXCLCSS_ECC_OUTPUTKEY_SIGN", "a00326.html#a8070d52b9e1de24eb80be43426300799", null ], + [ "MCUXCLCSS_ECC_PUBLICKEY_SIGN_DISABLE", "a00326.html#ad00a38fffb3eb59746f5d75fef0e60ec", null ], + [ "MCUXCLCSS_ECC_PUBLICKEY_SIGN_ENABLE", "a00326.html#a1382599ee4dd5c957759f3229f088126", null ], + [ "MCUXCLCSS_ECC_PUBLICKEY_SIZE", "a00326.html#ad108c2eda1500c7e436cbf833dd29dd4", null ], + [ "MCUXCLCSS_ECC_REVERSEFETCH_DISABLE", "a00326.html#a8de5756db01aaebfe8ada436492012ac", null ], + [ "MCUXCLCSS_ECC_REVERSEFETCH_ENABLE", "a00326.html#aad664519a25760d0f3225a772a3d1b59", null ], + [ "MCUXCLCSS_ECC_RTF", "a00326.html#ad69d63febc4b18b4841138ef0b605467", null ], + [ "MCUXCLCSS_ECC_SIGNATURE_R_SIZE", "a00326.html#aa7134516dc01477ac820a0d085614815", null ], + [ "MCUXCLCSS_ECC_SIGNATURE_SIZE", "a00326.html#a80478c2d8d6c3610b0f50957032afb7e", null ], + [ "MCUXCLCSS_ECC_SKIP_PUBLIC_KEY", "a00326.html#aa16f425deb9ee1609111f60836efdc56", null ], + [ "MCUXCLCSS_ECC_VALUE_HASHED", "a00326.html#a2182c8f712c4efdc8ab2f6cee7807ade", null ], + [ "MCUXCLCSS_ECC_VALUE_NOT_HASHED", "a00326.html#aedc258f70b2395c77c51275ffc17d149", null ], + [ "MCUXCLCSS_ECC_VALUE_NO_RTF", "a00326.html#a95036871d36cf68feb7a82efff7ea331", null ], + [ "MCUXCLCSS_ECC_VALUE_RTF", "a00326.html#afc86a1ccab6ba6db1bd8833cd1cb59cd", null ], + [ "MCUXCLCSS_ERROR_FLAGS_CLEAR", "a00326.html#abbb24a67f696bccd837f1d7c65845432", null ], + [ "MCUXCLCSS_ERROR_FLAGS_KEEP", "a00326.html#a961b05e6468dc49dd7aed1054512adbd", null ], + [ "MCUXCLCSS_GLITCHDETECTOR_CFG_SIZE", "a00326.html#ab1b153a467f3ae53a293446cfdf50393", null ], + [ "MCUXCLCSS_GLITCHDETECTOR_TRIM_SIZE", "a00326.html#a30d41dcb47943983dd3330cd28d5eb92", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_DISABLE", "a00326.html#acd717b20ede0f78f32ebdb9fd7e668b3", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_ENABLE", "a00326.html#a0e2a88207e41cd0d258608884baaf423", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_NEG_KEEP", "a00326.html#a4c05dc3a8973f6feafcc4bfc227ec230", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_NEG_SET", "a00326.html#a6ef269efee2350e2610d0de4a2589f81", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_POS_KEEP", "a00326.html#aa9a84584328c3a1056b979fbc23a7eb5", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_POS_SET", "a00326.html#a1a6bad1a0eed21e8d26c060a6bf730f4", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_RESET_CLEAR", "a00326.html#a7577e5d1115aa9ccb600109cce39744b", null ], + [ "MCUXCLCSS_GLITCH_DETECTOR_RESET_KEEP", "a00326.html#aa5b02a8ceb76f98f05333af1cf7e3970", null ], + [ "MCUXCLCSS_HASH_BLOCK_SIZE_SHA_224", "a00326.html#a4d3e6c483d80cb0275724553ec0c19f5", null ], + [ "MCUXCLCSS_HASH_BLOCK_SIZE_SHA_256", "a00326.html#a8b685c238e55aa0a078b9a69c503b08b", null ], + [ "MCUXCLCSS_HASH_BLOCK_SIZE_SHA_384", "a00326.html#a4d18ada36b64cff315ae82bbabb5212d", null ], + [ "MCUXCLCSS_HASH_BLOCK_SIZE_SHA_512", "a00326.html#a3f3835fc2c6b362d7bcfd94106c3734d", null ], + [ "MCUXCLCSS_HASH_INIT_DISABLE", "a00326.html#a4f37bc91be2e6af69f6988f6ed723660", null ], + [ "MCUXCLCSS_HASH_INIT_ENABLE", "a00326.html#afd75c3ec3d52e0ee2e13c014520fba98", null ], + [ "MCUXCLCSS_HASH_LOAD_DISABLE", "a00326.html#a6c5a802ab6b21960339cc8663cc88bff", null ], + [ "MCUXCLCSS_HASH_LOAD_ENABLE", "a00326.html#a25138f0efb4784ff32ac1b24c02e58f7", null ], + [ "MCUXCLCSS_HASH_MODE_SHA_224", "a00326.html#ade92d000538d2bc7120e8f6f79a27b79", null ], + [ "MCUXCLCSS_HASH_MODE_SHA_256", "a00326.html#a159f860f32e58ca87d7d5a66cac99d53", null ], + [ "MCUXCLCSS_HASH_MODE_SHA_384", "a00326.html#acdc9e0f80a183fa38f9fae82372ce332", null ], + [ "MCUXCLCSS_HASH_MODE_SHA_512", "a00326.html#a46e24b4e9ff6eb8b4c5537017d7b7a21", null ], + [ "MCUXCLCSS_HASH_OUTPUT_DISABLE", "a00326.html#a86aeaf74e904cdfab7b841b2b369b986", null ], + [ "MCUXCLCSS_HASH_OUTPUT_ENABLE", "a00326.html#af9a30c97004c2048dbfce054edb9985a", null ], + [ "MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_224", "a00326.html#a17d6eaa1f3f707f0deb415f94b73ee65", null ], + [ "MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_256", "a00326.html#a783695a49f9c67cd2a8546d86e4b5a86", null ], + [ "MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_384", "a00326.html#a2c3834219fb85d6eaba34de77be104b0", null ], + [ "MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_512", "a00326.html#a4a073160b4c743a138afee249f1a1842", null ], + [ "MCUXCLCSS_HASH_RTF_OUTPUT_DISABLE", "a00326.html#a2a82dbb17ea5a53534d6b7aba91e3a2e", null ], + [ "MCUXCLCSS_HASH_RTF_OUTPUT_ENABLE", "a00326.html#a0ad926213ad5fa0a0c8d7926641fe641", null ], + [ "MCUXCLCSS_HASH_RTF_OUTPUT_SIZE", "a00326.html#ac664d7ccc2e665ffa595d353f885c726", null ], + [ "MCUXCLCSS_HASH_RTF_UPDATE_DISABLE", "a00326.html#aabc417a63c1e014c00be577b7e47d49e", null ], + [ "MCUXCLCSS_HASH_RTF_UPDATE_ENABLE", "a00326.html#a1048327e3ee71b6bf7f1a58e4d720814", null ], + [ "MCUXCLCSS_HASH_STATE_SIZE_SHA_224", "a00326.html#a67d00c615049e7cc27def9a50198a6bd", null ], + [ "MCUXCLCSS_HASH_STATE_SIZE_SHA_256", "a00326.html#af3e1374b19bc1537ae2c4d457a91a985", null ], + [ "MCUXCLCSS_HASH_STATE_SIZE_SHA_384", "a00326.html#a9ed18ed27e1e13a59cf4a60fd80cdffb", null ], + [ "MCUXCLCSS_HASH_STATE_SIZE_SHA_512", "a00326.html#aca0aadf883642c14d844051c18c05734", null ], + [ "MCUXCLCSS_HASH_VALUE_MODE_SHA_224", "a00326.html#a973f4a525ab84014c916c4fa3342e5ac", null ], + [ "MCUXCLCSS_HASH_VALUE_MODE_SHA_256", "a00326.html#aa601ebec121f959d2947a7f877c99e7b", null ], + [ "MCUXCLCSS_HASH_VALUE_MODE_SHA_384", "a00326.html#ad62303288ebf3d264e7480beef314eba", null ], + [ "MCUXCLCSS_HASH_VALUE_MODE_SHA_512", "a00326.html#a538038c51c46a7ee8e18bdb355a0fa41", null ], + [ "MCUXCLCSS_HKDF_ALGO_RFC5869", "a00326.html#a91399fc471cb4c4a495001e22b08b722", null ], + [ "MCUXCLCSS_HKDF_ALGO_SP80056C", "a00326.html#a8b242833b8c78810e8733614cfc934bf", null ], + [ "MCUXCLCSS_HKDF_RFC5869_DERIVATIONDATA_SIZE", "a00326.html#a2cbe31021080edae81628e35e491a8d7", null ], + [ "MCUXCLCSS_HKDF_SP80056C_TARGETKEY_SIZE", "a00326.html#a31496a291591d99b3a1935fbee85e630", null ], + [ "MCUXCLCSS_HKDF_VALUE_MEMORY_DERIV", "a00326.html#a9e65aa426cfbcd5eb2662300eada9a38", null ], + [ "MCUXCLCSS_HKDF_VALUE_RTF_DERIV", "a00326.html#a770fccc94f9f7ba601a047562bb681fa", null ], + [ "MCUXCLCSS_HMAC_EXTERNAL_KEY_DISABLE", "a00326.html#a5fff9a5b18e44d471dc00766fe8a42d9", null ], + [ "MCUXCLCSS_HMAC_EXTERNAL_KEY_ENABLE", "a00326.html#abd180a5ef21f2f56e357f3ee1337ff3c", null ], + [ "MCUXCLCSS_HMAC_OUTPUT_SIZE", "a00326.html#ae1cdfabfa0b10b698bce00a75af4f0f7", null ], + [ "MCUXCLCSS_HMAC_PADDED_KEY_SIZE", "a00326.html#a6fb6271ad70e2a4e2138c202c2651018", null ], + [ "MCUXCLCSS_HW_VERSION", "a00326.html#ab8ec8531d5bfe6991efb244b92616c57", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_DETERMINISTIC", "a00326.html#a622cc96422d438cf61c8b9eb924b2df5", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_GEN_PUB_KEY", "a00326.html#aa7dc9da1e1ee723bd6bd1dee80a18df6", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_NO_PUB_KEY", "a00326.html#ab6706bad78abac9c6e7c72ec8cf34b17", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_NO_RANDOM_DATA", "a00326.html#a93ba2f6d2ad0e75aeb5be0f196354387", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_RANDOM", "a00326.html#ab48d1755d76ff44418d4e2b4c3b21b05", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_SIGN_PUBLICKEY", "a00326.html#ab15f1a80b43924c18dbdd01d7e43d6aa", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_TYPE_KEYEXCHANGE", "a00326.html#a36e78663fef3d372cf8cba67970caf07", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_TYPE_SIGN", "a00326.html#a2e2aeb4497642b5dc777000896baefe3", null ], + [ "MCUXCLCSS_KEYGEN_VALUE_USE_RANDOM_DATA", "a00326.html#ac8e7ba0124d408a1f1cea4e8756ac38e", null ], + [ "MCUXCLCSS_KEYIMPORT_KFMT_PBK", "a00326.html#a550ab61bff707fef9a78a7c613fa872c", null ], + [ "MCUXCLCSS_KEYIMPORT_KFMT_PUF", "a00326.html#af66db7f2a85d31d0734af958f3c1ec54", null ], + [ "MCUXCLCSS_KEYIMPORT_KFMT_RFC3394", "a00326.html#a99f9ef0742012604e75276dba003bc90", null ], + [ "MCUXCLCSS_KEYIMPORT_KFMT_UDF", "a00326.html#af5f639b2398e305a43d5fbc6ea065340", null ], + [ "MCUXCLCSS_KEYIMPORT_REVERSEFETCH_DISABLE", "a00326.html#ae3e8889bc9ee605c4c498d85fc1caaed", null ], + [ "MCUXCLCSS_KEYIMPORT_REVERSEFETCH_ENABLE", "a00326.html#a4dda6129074237f58bd183ae470e7243", null ], + [ "MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PBK", "a00326.html#ab317fc6018419a37c4982fc012ed1b1a", null ], + [ "MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PUF", "a00326.html#a19620fe9890be50696d247b0fea655c2", null ], + [ "MCUXCLCSS_KEYIMPORT_VALUE_KFMT_RFC3394", "a00326.html#a00fe1b492488d2d7a851dc34d66d6255", null ], + [ "MCUXCLCSS_KEYIMPORT_VALUE_KFMT_UDF", "a00326.html#ac448b57291666268614ba870239af580", null ], + [ "MCUXCLCSS_KEYPROPERTY_ACTIVE_FALSE", "a00326.html#a0d17aaec7af64fcd8f30a1e2e30d4ca5", null ], + [ "MCUXCLCSS_KEYPROPERTY_ACTIVE_TRUE", "a00326.html#a4f232753817cca8ad89d63964cf2f048", null ], + [ "MCUXCLCSS_KEYPROPERTY_AES_FALSE", "a00326.html#aa4cbb439cbd5a0d8a668dc8979a199ae", null ], + [ "MCUXCLCSS_KEYPROPERTY_AES_TRUE", "a00326.html#a7a6fbe75bb67500e05a5d0eaf2a2af6f", null ], + [ "MCUXCLCSS_KEYPROPERTY_BASE_SLOT", "a00326.html#a9f7e39018bff2e1fbf982a17c5e2cdbf", null ], + [ "MCUXCLCSS_KEYPROPERTY_CKDF_FALSE", "a00326.html#a744722dd16eb339df40e0587e519b2a9", null ], + [ "MCUXCLCSS_KEYPROPERTY_CKDF_TRUE", "a00326.html#a2072f4a5fade095ab80e3dbd83de6ac4", null ], + [ "MCUXCLCSS_KEYPROPERTY_CMAC_FALSE", "a00326.html#af7993cf4a1d1774b31f35d09bc5d2d24", null ], + [ "MCUXCLCSS_KEYPROPERTY_CMAC_TRUE", "a00326.html#a63463c7af1b3005a7d152a4a3dd6df46", null ], + [ "MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_FALSE", "a00326.html#abe36792489a0192b0cb54099aaf6bace", null ], + [ "MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_TRUE", "a00326.html#a37f353d6f9692534376d73a8ad558fab", null ], + [ "MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE", "a00326.html#add4e040440adf1f4f16935b3615a8a46", null ], + [ "MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE", "a00326.html#a97045d1840740b7032bba33b42a39b77", null ], + [ "MCUXCLCSS_KEYPROPERTY_ECC_FALSE", "a00326.html#a75e2ba045e29b9de5e548269873b3f01", null ], + [ "MCUXCLCSS_KEYPROPERTY_ECC_TRUE", "a00326.html#a9fe603074f056994e079453aefe1cc5d", null ], + [ "MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE", "a00326.html#a64bde9546ea127d215da7a643ed924aa", null ], + [ "MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE", "a00326.html#ad8fc9da088866e358712015447c6a205", null ], + [ "MCUXCLCSS_KEYPROPERTY_HKDF_FALSE", "a00326.html#a96732cf34df4c865f1e2c7c6c9851b08", null ], + [ "MCUXCLCSS_KEYPROPERTY_HKDF_TRUE", "a00326.html#a3943123a5fea3966bcaa46d7740d0e72", null ], + [ "MCUXCLCSS_KEYPROPERTY_HMAC_FALSE", "a00326.html#ae10e89b31c0843d31f838aee0e95ebf9", null ], + [ "MCUXCLCSS_KEYPROPERTY_HMAC_TRUE", "a00326.html#a2c15be7b609b703dbcbfb977db9bfbd0", null ], + [ "MCUXCLCSS_KEYPROPERTY_HW_OUT_FALSE", "a00326.html#ace207da98260f877ec4e90852f870645", null ], + [ "MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_FALSE", "a00326.html#a85a4adff48ef9a69886c6a59e384be93", null ], + [ "MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_TRUE", "a00326.html#ac55dc35f11c3758978d2fba58806534c", null ], + [ "MCUXCLCSS_KEYPROPERTY_HW_OUT_TRUE", "a00326.html#ae7ae66946020b73e81e162a178ea401d", null ], + [ "MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_FALSE", "a00326.html#ad3f72b9782882d043bfaeb734a0e604e", null ], + [ "MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_TRUE", "a00326.html#ad66e15365d1a792a1f0e6c547abc466c", null ], + [ "MCUXCLCSS_KEYPROPERTY_KEY_SIZE_128", "a00326.html#a5da48131f42f3c84ca6f0bb541f0e577", null ], + [ "MCUXCLCSS_KEYPROPERTY_KEY_SIZE_256", "a00326.html#a8f07304adae521a03ab5d00c19a19704", null ], + [ "MCUXCLCSS_KEYPROPERTY_KEY_SIZE_512", "a00326.html#ad22eb742032a361f7f66dfac36c947f4", null ], + [ "MCUXCLCSS_KEYPROPERTY_KSK_FALSE", "a00326.html#a95d5ee92b7c45cd23ff913a6fe7535d5", null ], + [ "MCUXCLCSS_KEYPROPERTY_KSK_TRUE", "a00326.html#a607e884fd84d2af746790b0ae4df0930", null ], + [ "MCUXCLCSS_KEYPROPERTY_KUOK_FALSE", "a00326.html#acf7e0fe86a025ecce6d68ae63cc7e863", null ], + [ "MCUXCLCSS_KEYPROPERTY_KUOK_TRUE", "a00326.html#a7a335c83717683dd2f1865b276687ad2", null ], + [ "MCUXCLCSS_KEYPROPERTY_KWK_FALSE", "a00326.html#af3caa4709bf3506da000ff729519a449", null ], + [ "MCUXCLCSS_KEYPROPERTY_KWK_TRUE", "a00326.html#a71330599a88564ba2643b01602fb2c4e", null ], + [ "MCUXCLCSS_KEYPROPERTY_PRIVILEGED_FALSE", "a00326.html#ae5f6c29a2c93ccf6125663d93c09cbe3", null ], + [ "MCUXCLCSS_KEYPROPERTY_PRIVILEGED_TRUE", "a00326.html#a21ce522549d570bec044b8ae0c64673d", null ], + [ "MCUXCLCSS_KEYPROPERTY_PUK_FALSE", "a00326.html#a19d56dd68a28340d144123c497aaa1d3", null ], + [ "MCUXCLCSS_KEYPROPERTY_PUK_TRUE", "a00326.html#a6aba5043d8c61450680fb984152618f5", null ], + [ "MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_FALSE", "a00326.html#af9a45278780bb7ca17d861c3ff8b5432", null ], + [ "MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_TRUE", "a00326.html#a28549ca174f46969c11f87504c4af102", null ], + [ "MCUXCLCSS_KEYPROPERTY_RTF_FALSE", "a00326.html#a15fae42046dcbf80e8f2bd92b17993b7", null ], + [ "MCUXCLCSS_KEYPROPERTY_RTF_TRUE", "a00326.html#a4be8a0d9400e7815fa628fd9f9874678", null ], + [ "MCUXCLCSS_KEYPROPERTY_SECOND_SLOT", "a00326.html#a9464ffee50cd3c7ebb6e833d3166a419", null ], + [ "MCUXCLCSS_KEYPROPERTY_SECURE_FALSE", "a00326.html#a8d5684f5f6f8d08349f8ecd2d58d8c02", null ], + [ "MCUXCLCSS_KEYPROPERTY_SECURE_TRUE", "a00326.html#ac97aee1951814ef6517ecfb8722f6b6d", null ], + [ "MCUXCLCSS_KEYPROPERTY_TECDH_FALSE", "a00326.html#aa1a0904e5c508e93cf9e53f0f31e07b1", null ], + [ "MCUXCLCSS_KEYPROPERTY_TECDH_TRUE", "a00326.html#aaa9918fb9e4ea660b46164b2ff89070f", null ], + [ "MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE", "a00326.html#a71997579592aa3a0c220436a2818fc1a", null ], + [ "MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE", "a00326.html#a033b5bd3c836ea31583f7782d8592b7c", null ], + [ "MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE", "a00326.html#a2c24a471e7acd9cd53cb0fe0845b3790", null ], + [ "MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE", "a00326.html#a70a43d7321dfb191b4da362f25b5a878", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_ACTIVE", "a00326.html#a9f3651d3e306f2e330fff730d5784696", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_AES", "a00326.html#a612babf48a690b487e9cd0408f55e78a", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_BASE_SLOT", "a00326.html#acaf383969b8bb7162deac8218aae8c41", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_CKDF", "a00326.html#aa7833a46d5030368c21616f8e907183b", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_CMAC", "a00326.html#ad628b83a2bbf047c0a93143b75ae4caf", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_DUK", "a00326.html#a3579cb33a0cef2e84319f20c3d63b02e", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_ECDH", "a00326.html#aa33e608b60b4059cb3a7ebd4ff82752a", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_ECSGN", "a00326.html#a1870ee6b44e549ef08f2266f62dd7517", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT", "a00326.html#abf862876fffbf522b1a2f19a2d0bdaf6", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_HKDF", "a00326.html#a8363c6c21cf992fa6b83a188e52825c0", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_HMAC", "a00326.html#a7ca5c21a37d6b6ee4e3fbe008ab130aa", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT", "a00326.html#a12958c6761b6c31a52243894bb42cf41", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT_SLOT", "a00326.html#af98b7c79f7aa0204d4d349d1f9460bc8", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_128", "a00326.html#aad9a92f43d7279dec83ced1ba6a02dcb", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_256", "a00326.html#ab279ae92063286b8e702163c74f1850d", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_512", "a00326.html#a737101d0a2dd8f78fdb3bc6023c4b71a", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KGSRC", "a00326.html#a99d1e8243a4531340679ce3f3c5f4f51", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KSK", "a00326.html#a57e79ad7ff29b3f4d70c47a02c89d9d6", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KUOK", "a00326.html#a4e016be69b64c0ada6199d0b7592c6a9", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_KWK", "a00326.html#a1f3c732a3a9b90f976c4476e9768f4c3", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_NOTPRIVILEGED", "a00326.html#a8c77c6c4dce048b52cfc167b53e3c662", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_NOTSECURE", "a00326.html#ab3704505990cae730180c3d3f50cf552", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_PRIVILEGED", "a00326.html#abb01e30f9875ea8fc833510bea75cbc4", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_PUK", "a00326.html#a7f998548987a940a7344726faa56fea1", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_RETENTION_SLOT", "a00326.html#a8a76a8f2bc63d344a3acf270cd3acae8", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_RTF", "a00326.html#a722a3a8146211e69dfad6f73bb5fb935", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_SECURE", "a00326.html#a341d2f47688ba34de5aae495774954c9", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_TECDH", "a00326.html#aaea1e1f1c45fce6e64bc7b2e0b9667bf", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET", "a00326.html#a3ad39cca5e9286c33af3d69ca7dbbc75", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET", "a00326.html#aabc1fe269ca3cbbe77ef2c78488cca53", null ], + [ "MCUXCLCSS_KEYPROPERTY_VALUE_WRPOK", "a00326.html#afe2fc088bcc641a22347a0050cab7d2d", null ], + [ "MCUXCLCSS_KEYPROPERTY_WRAP_FALSE", "a00326.html#afe6fedcf0c36967caf067587fa8cb5f5", null ], + [ "MCUXCLCSS_KEYPROPERTY_WRAP_TRUE", "a00326.html#a9f2303274e87ac487d7982e170fb1d88", null ], + [ "MCUXCLCSS_KEYPROV_DUK_UPDATE_DISABLE", "a00326.html#a11c37096278e29adbec73c1930388dbb", null ], + [ "MCUXCLCSS_KEYPROV_DUK_UPDATE_ENABLE", "a00326.html#aaa24e7e93d8afde954a0807a167f901b", null ], + [ "MCUXCLCSS_KEYPROV_KEYSHARE_TABLE_SIZE", "a00326.html#ab69f1bb287c9dbb099f102384b09d6e3", null ], + [ "MCUXCLCSS_KEYPROV_KEY_PART_1_SIZE", "a00326.html#ac083c0bd3bcb55e84e7a96b69bcc8949", null ], + [ "MCUXCLCSS_KEYPROV_NOIC_DISABLE", "a00326.html#a36cc163b24366b81ae62e1f5953a28fc", null ], + [ "MCUXCLCSS_KEYPROV_NOIC_ENABLE", "a00326.html#a53d9b9f10f35ae12d42d8f7d83fc1f46", null ], + [ "MCUXCLCSS_KEYPROV_TESTERSHARE_SIZE", "a00326.html#a324d9f5156eb71dcec85ceac23e0c430", null ], + [ "MCUXCLCSS_KEYPROV_VALUE_NOIC", "a00326.html#ae4f269b95269486420cdb5d6972c7e22", null ], + [ "MCUXCLCSS_KEY_SLOTS", "a00326.html#ad3a228cc6266ea9c1f81e38bc0be7284", null ], + [ "MCUXCLCSS_MASTER_UNLOCK_ANY", "a00326.html#a254b56f8535d9b0ee57ff096583d8797", null ], + [ "MCUXCLCSS_RESET_CANCEL", "a00326.html#a8406f9dfe9b26aa856fc322039599148", null ], + [ "MCUXCLCSS_RESET_DO_NOT_CANCEL", "a00326.html#a350fe58f3bb17019073adc91d57fbd89", null ], + [ "MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_0", "a00326.html#a1d62b12fd59aea38c424f911009a9e25", null ], + [ "MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_1", "a00326.html#a035d6f264a04b56f5933331742a6ccc6", null ], + [ "MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_2", "a00326.html#ade2f7d124dfdbe7b27b3be8604ceebdb", null ], + [ "MCUXCLCSS_RESP_GEN_SLOTS", "a00326.html#adf4f7f554b4183281ec4dbc32b7b98d7", null ], + [ "MCUXCLCSS_RFC3394_CONTAINER_SIZE_128", "a00326.html#a1a874de5d9eaa584e1f8b5f6f7c5d7d0", null ], + [ "MCUXCLCSS_RFC3394_CONTAINER_SIZE_256", "a00326.html#a8cf48a7bb2432243e171d904cb3890a3", null ], + [ "MCUXCLCSS_RFC3394_CONTAINER_SIZE_P256", "a00326.html#af2784f566afff9e25b368394ad008696", null ], + [ "MCUXCLCSS_RFC3394_OVERHEAD", "a00326.html#a6962fe4cad4a4a1c5b0a9fd5d12f3328", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE", "a00326.html#a8eff269e0b0202c32591b3be69dcc673", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE", "a00326.html#a3ea8f055bdf31fe558db537e62d4dd33", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_CTR", "a00326.html#ae4474a1dd2f642f3744af353e37568a5", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_ECB", "a00326.html#aff13410c28106829a32a244a6225783e", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_MODE_EXTRACT", "a00326.html#a371f897c9fc431f16bc363fae953c797", null ], + [ "MCUXCLCSS_RNG_DRBG_TEST_MODE_INSTANTIATE", "a00326.html#a85e0d2049c234685e629aecab9bfb401", null ], + [ "MCUXCLCSS_RNG_DTRNG_CONFIG_SIZE", "a00326.html#abda85ee68fd3a733626fd5010392a056", null ], + [ "MCUXCLCSS_RNG_DTRNG_EVAL_CONFIG_SIZE", "a00326.html#ae06f893c67d58049913a4b2bdeae966f", null ], + [ "MCUXCLCSS_RNG_DTRNG_EVAL_RESULT_SIZE", "a00326.html#ad7047da255cc862e68a310719bd28127", null ], + [ "MCUXCLCSS_RNG_RAW_ENTROPY_SIZE", "a00326.html#aeca6160e4e96476690c57ad1b35826f6", null ], + [ "MCUXCLCSS_RNG_RND_REQ_PRND_INIT", "a00326.html#a9f58c1a730ae8fbc1242de761e1dc14d", null ], + [ "MCUXCLCSS_RNG_RND_REQ_RND_RAW", "a00326.html#a54425235a764981403e589978cdedeca", null ], + [ "MCUXCLCSS_STATUS_DRBGENTLVL_HIGH", "a00326.html#ace8aac7d208417d5da45b01b5896aa3c", null ], + [ "MCUXCLCSS_STATUS_DRBGENTLVL_LOW", "a00326.html#ae37dede8fbd2c0314bd27d7b67b07200", null ], + [ "MCUXCLCSS_STATUS_DRBGENTLVL_NONE", "a00326.html#a66655c971e77afa090accf2878072879", null ], + [ "MCUXCLCSS_STATUS_ECDSAVFY_ERROR", "a00326.html#a10d6936773329b47c8c79319338b6b88", null ], + [ "MCUXCLCSS_STATUS_ECDSAVFY_FAIL", "a00326.html#af22023f36ac442cf64f8501a7294bab4", null ], + [ "MCUXCLCSS_STATUS_ECDSAVFY_NORUN", "a00326.html#a78d5d494499de79087cfc76eac95c68f", null ], + [ "MCUXCLCSS_STATUS_ECDSAVFY_OK", "a00326.html#a8b583babde0119fa01ba2033290f26c7", null ], + [ "MCUXCLCSS_STATUS_HW_ALGORITHM", "a00326.html#addefde9d75633c1625522ac908770f54", null ], + [ "MCUXCLCSS_STATUS_HW_BUS", "a00326.html#a53d9cb59969fee38fba63244736ab440", null ], + [ "MCUXCLCSS_STATUS_HW_DTRNG", "a00326.html#ae8b1830c3a293f669763dcd976b3f686", null ], + [ "MCUXCLCSS_STATUS_HW_FAULT", "a00326.html#ad0536fa6242769cb2600dbce80306dbd", null ], + [ "MCUXCLCSS_STATUS_HW_INTEGRITY", "a00326.html#a1f3df27eb14036c8b9206d32459e30e2", null ], + [ "MCUXCLCSS_STATUS_HW_OPERATIONAL", "a00326.html#a6b0831ccc016832d2018c69c253f8091", null ], + [ "MCUXCLCSS_STATUS_HW_PRNG", "a00326.html#a18bd25061f38f2ceb06b2631403efe35", null ], + [ "MCUXCLCSS_STATUS_IS_HW_ERROR", "a00326.html#ada2d34b0486f21cdc6a342decf87631a", null ], + [ "MCUXCLCSS_STATUS_IS_SW_ERROR", "a00326.html#a0a53f6ac67401158cf5cd67b53be0edb", null ], + [ "MCUXCLCSS_STATUS_OK", "a00326.html#a634955e46e8fa7b765009e6cdb8afd51", null ], + [ "MCUXCLCSS_STATUS_OK_WAIT", "a00326.html#a297513afc3d4e6d0f94064a59a2e23b6", null ], + [ "MCUXCLCSS_STATUS_PPROT_PRIVILEGED_NONSECURE", "a00326.html#af26118e1a16954e5ab4f8282eecb66d4", null ], + [ "MCUXCLCSS_STATUS_PPROT_PRIVILEGED_SECURE", "a00326.html#a4f3043b7e899d5df2bf1a9e29efced21", null ], + [ "MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_NONSECURE", "a00326.html#a8ea2c69b1786dd633654ce4750d54410", null ], + [ "MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_SECURE", "a00326.html#a7cbd0f3a376ddaddef1f9dc9828f555a", null ], + [ "MCUXCLCSS_STATUS_SW_CANNOT_INTERRUPT", "a00326.html#a73ff3a7a0a8431e73c5642eb27d4c264", null ], + [ "MCUXCLCSS_STATUS_SW_COMPARISON_FAILED", "a00326.html#abf883262c74f544cfa0d58797cf17ed1", null ], + [ "MCUXCLCSS_STATUS_SW_COUNTER_EXPIRED", "a00326.html#aae93f0b585ffc529f3f7fea0efb5d7d2", null ], + [ "MCUXCLCSS_STATUS_SW_FAULT", "a00326.html#a2e1e05de4dd1609e6838eab40f69bd47", null ], + [ "MCUXCLCSS_STATUS_SW_INVALID_PARAM", "a00326.html#a8ec9a41988bdc9decef481ed60401b55", null ], + [ "MCUXCLCSS_STATUS_SW_INVALID_STATE", "a00326.html#abe6aa3792ea27a7597b0d0799b760561", null ], + [ "MCUXCLCSS_STATUS_SW_LOCKING_FAILED", "a00326.html#ab72822002068bc4586a95bf0a1394547", null ], + [ "MCUXCLCSS_STATUS_SW_STATUS_LOCKED", "a00326.html#a5cb83c8d2e06a10f270b6594cd641fc2", null ], + [ "MCUXCLCSS_TLS_DERIVATIONDATA_SIZE", "a00326.html#a790a04ed31f864e9a8ee6c58e215f71b", null ], + [ "MCUXCLCSS_TLS_FINALIZE", "a00326.html#aff974ef54b82c3587652be8a9623fe7a", null ], + [ "MCUXCLCSS_TLS_INIT", "a00326.html#aeb7b93199178bc480621befd97179966", null ], + [ "MCUXCLCSS_TLS_RANDOM_SIZE", "a00326.html#a8f7f9783f6e3387647c01d883f7905a9", null ], + [ "mcuxClCss_AeadOption_t", "a00326.html#adbc7825ddeb3a5325134b21ba92d895c", null ], + [ "mcuxClCss_CipherOption_t", "a00326.html#af437cab3c523aaa70f7eb0890760873a", null ], + [ "mcuxClCss_CkdfOption_t", "a00326.html#a295198ccf946545f427df3e7681b85b5", null ], + [ "mcuxClCss_CmacOption_t", "a00326.html#a8a90f7a951bf7a6af73a6aedd75211f2", null ], + [ "mcuxClCss_CommandCrcConfig_t", "a00326.html#a783623df272024a312bd2c4c22124956", null ], + [ "mcuxClCss_EccByte_t", "a00326.html#a3f045f11abb7a1100aae44d1d9f7a459", null ], + [ "mcuxClCss_EccKeyExchOption_t", "a00326.html#a49389bbfb8a4f0cb9c86494b2c31e64f", null ], + [ "mcuxClCss_EccKeyGenOption_t", "a00326.html#a69b5a998209a427ab60181f9c5496df5", null ], + [ "mcuxClCss_EccSignOption_t", "a00326.html#aa20e1b5508c3c6d21f9101bd035ec668", null ], + [ "mcuxClCss_EccVerifyOption_t", "a00326.html#a2a16a12a7ad5f08dd77a764a5a754fe9", null ], + [ "mcuxClCss_ErrorHandling_t", "a00326.html#ac9c41c0c63595a8bf4b6b5c65a61f3bc", null ], + [ "mcuxClCss_HashOption_t", "a00326.html#adf0523c70f94f504012891f9d081c74d", null ], + [ "mcuxClCss_HkdfOption_t", "a00326.html#abdddaf7af74f674a7b3a265ff534a66b", null ], + [ "mcuxClCss_HmacOption_t", "a00326.html#a7ad6d8a8baf267577a1a5639d0aee9df", null ], + [ "mcuxClCss_HwConfig_t", "a00326.html#ac1d1a413bb5f3374805d824ed13f32fc", null ], + [ "mcuxClCss_HwState_t", "a00326.html#aa6b28ff73d531c9e1e626a1070d5e936", null ], + [ "mcuxClCss_HwVersion_t", "a00326.html#aabfb75c002eaee7378317c4eb97d78f2", null ], + [ "mcuxClCss_InterruptOptionEn_t", "a00326.html#a7d381ef703cb41428c6e5936f99deb2f", null ], + [ "mcuxClCss_InterruptOptionRst_t", "a00326.html#a72165e9a307dbcce2963248e2cac779a", null ], + [ "mcuxClCss_InterruptOptionSet_t", "a00326.html#a51bb09787ce6b4a127b569813389578d", null ], + [ "mcuxClCss_KeyImportOption_t", "a00326.html#a7982cec7fe093a87973128e14aed50d4", null ], + [ "mcuxClCss_KeyIndex_t", "a00326.html#ac08e733fef66a44fcbac0a48ac74e01f", null ], + [ "mcuxClCss_KeyProp_t", "a00326.html#af39f42d9b466e57de01d178f29103772", null ], + [ "mcuxClCss_KeyProvisionOption_t", "a00326.html#ab12e742eb52157cc68fff6a68478921d", null ], + [ "mcuxClCss_ResetOption_t", "a00326.html#a2fda566281e4266c05812c44b05cf58e", null ], + [ "mcuxClCss_Status_Protected_t", "a00326.html#aa71f80e16ea66c8a045be97763cc4899", null ], + [ "mcuxClCss_Status_t", "a00326.html#a416096f815d6bbe0cde9b91d2191d16e", null ], + [ "mcuxClCss_TlsOption_t", "a00326.html#a8c6a729e067510eea690ff39cfcdc583", null ], + [ "mcuxClCss_TransferToRegisterFunction_t", "a00326.html#ab3b7deed7a8e59a4a11c579fd82764e0", null ], + [ "mcuxClCss_Aead_Finalize_Async", "a00326.html#acd4f33dfe8b92796f5d88070e2cb45ec", null ], + [ "mcuxClCss_Aead_Init_Async", "a00326.html#a197c20d27b5c59924900d47ebf4e40c3", null ], + [ "mcuxClCss_Aead_PartialInit_Async", "a00326.html#a228e941a21f75fb150530bf8afd5e020", null ], + [ "mcuxClCss_Aead_UpdateAad_Async", "a00326.html#ad28a73da8e828ee755e574fe46ed3bbf", null ], + [ "mcuxClCss_Aead_UpdateData_Async", "a00326.html#adb6df74a4c9af9de8de6bbfc45edc057", null ], + [ "mcuxClCss_Cipher_Async", "a00326.html#a797007ded485bc407e1ff436a038ac04", null ], + [ "mcuxClCss_Ckdf_Sp800108_Async", "a00326.html#a62747f67cd21e996149ced9d8dd7ee3d", null ], + [ "mcuxClCss_Ckdf_Sp80056c_Expand_Async", "a00326.html#a17abdf05d778acf2f9d71bf0b6e07203", null ], + [ "mcuxClCss_Ckdf_Sp80056c_Extract_Async", "a00326.html#a1c1099284de0e1cd7ae5d5b8ae05a0a9", null ], + [ "mcuxClCss_Cmac_Async", "a00326.html#a337f6bcb101a59301f19d726500cf2fb", null ], + [ "mcuxClCss_CompareDmaFinalOutputAddress", "a00326.html#a540d6f5605034403c9ef2588f2aceda6", null ], + [ "mcuxClCss_ConfigureCommandCRC", "a00326.html#a56cfad9f617abf6c055bc26eded38353", null ], + [ "mcuxClCss_Disable", "a00326.html#a545710a6a86eb497fe95ed08a397b39e", null ], + [ "mcuxClCss_EccKeyExchangeInt_Async", "a00326.html#a7b8c3e3cb0e85758638dc75789f8a367", null ], + [ "mcuxClCss_EccKeyExchange_Async", "a00326.html#aac8fcc47cceebf9ec25c8e2b47071a50", null ], + [ "mcuxClCss_EccKeyGen_Async", "a00326.html#aff19d1400f4441effb1adf8180a59f23", null ], + [ "mcuxClCss_EccSign_Async", "a00326.html#a0798c49605391ae7744eb153e955cb06", null ], + [ "mcuxClCss_EccVerifyInt_Async", "a00326.html#a79f65beb6384271b968a677578f1a11a", null ], + [ "mcuxClCss_EccVerify_Async", "a00326.html#a8ea4438f2f8069aab105ea0f996eb8dc", null ], + [ "mcuxClCss_Enable_Async", "a00326.html#a6f293e6b077cac6a1e5f38f91f6735a3", null ], + [ "mcuxClCss_GetCommandCRC", "a00326.html#a09d390018be871cc4e59605c1ea31d01", null ], + [ "mcuxClCss_GetErrorCode", "a00326.html#ac6c4ce2cef6c191ab058fd3fc3050232", null ], + [ "mcuxClCss_GetErrorLevel", "a00326.html#a1a349fc5551e293d479e4906621931ad", null ], + [ "mcuxClCss_GetHwConfig", "a00326.html#a003a52805a66e90b405588555ba5cc8a", null ], + [ "mcuxClCss_GetHwState", "a00326.html#ae8d8712af3dcddec8f013188704497b5", null ], + [ "mcuxClCss_GetHwVersion", "a00326.html#a54f0f4dfe5c6d6420363e6df449efc0b", null ], + [ "mcuxClCss_GetIntEnableFlags", "a00326.html#a4483aee11836ffb073eceb550a1cb82d", null ], + [ "mcuxClCss_GetKeyProperties", "a00326.html#a025de361915b08f166565a91838115ec", null ], + [ "mcuxClCss_GetLastDmaAddress", "a00326.html#a3294f9ba970f26b7905d184a95d2eb7a", null ], + [ "mcuxClCss_GetLock", "a00326.html#a0d4b7f58bcb6dd7a1f7aaaa288cb94ab", null ], + [ "mcuxClCss_GetRandomStartDelay", "a00326.html#a615b28f42a37da0ce8f94688033181d9", null ], + [ "mcuxClCss_GlitchDetector_GetEventCounter", "a00326.html#a05c7b9c63b9a78139de1470ac24d050a", null ], + [ "mcuxClCss_GlitchDetector_LoadConfig_Async", "a00326.html#a622a148155ebdab3b593c5aa773d0f52", null ], + [ "mcuxClCss_GlitchDetector_ResetEventCounter", "a00326.html#a7fb66578cd676462868c23f07982bf4b", null ], + [ "mcuxClCss_GlitchDetector_Trim_Async", "a00326.html#a65e51d75311943095b000be78b654f9f", null ], + [ "mcuxClCss_Hash_Async", "a00326.html#abc7accd724d4a7f75c93390f9023cff4", null ], + [ "mcuxClCss_Hash_ShaDirect", "a00326.html#a2f817a61d1501cc5f92e2794f1410adf", null ], + [ "mcuxClCss_Hkdf_Rfc5869_Async", "a00326.html#a43a83da60db5c56af400456692625e13", null ], + [ "mcuxClCss_Hkdf_Sp80056c_Async", "a00326.html#a9fd0b807c45e9b416d96bf966093a01c", null ], + [ "mcuxClCss_Hmac_Async", "a00326.html#a9122a99e2edd76a4446cdd876142276a", null ], + [ "mcuxClCss_IsLocked", "a00326.html#a1f0bb1024e28f9d94d0dc9898b06793d", null ], + [ "mcuxClCss_KeyDelete_Async", "a00326.html#a5bf5db0d8cdd030277f6d08e34398364", null ], + [ "mcuxClCss_KeyExport_Async", "a00326.html#a8ae381ab2b03107dc728450e21ec0b34", null ], + [ "mcuxClCss_KeyImportPuk_Async", "a00326.html#a9b685054c327532e5e8bc8a549860d91", null ], + [ "mcuxClCss_KeyImport_Async", "a00326.html#ab1009a386f6b907e37ba56c8d969e8d3", null ], + [ "mcuxClCss_KeyProvisionRom_Async", "a00326.html#a54f147e682b21be900a4171ee71d2d60", null ], + [ "mcuxClCss_KeyProvision_Async", "a00326.html#a8de7c996ce9366d031325ed6a576086a", null ], + [ "mcuxClCss_LimitedWaitForOperation", "a00326.html#a9483a369d9a5da7ad4dd470b888a987d", null ], + [ "mcuxClCss_Prng_GetRandom", "a00326.html#ad4b388e5bd58a3d6dd9995946e524683", null ], + [ "mcuxClCss_Prng_GetRandomWord", "a00326.html#a44e20a279fdc982716d64644882a48db", null ], + [ "mcuxClCss_Prng_Init_Async", "a00326.html#a3d7d8454153f67cc652c0ced97c0faaf", null ], + [ "mcuxClCss_ReleaseLock", "a00326.html#a3b0ea9a5ee53048c9f75b3de0fb76f0c", null ], + [ "mcuxClCss_ResetErrorFlags", "a00326.html#a0383b675d82d05fa1a76affc7c8ec259", null ], + [ "mcuxClCss_ResetIntFlags", "a00326.html#a39754fdffd353b78e94b14eedeacdc26", null ], + [ "mcuxClCss_Reset_Async", "a00326.html#a4cab5f290fddec7260b05ac2161fc1f9", null ], + [ "mcuxClCss_RespGen_Async", "a00326.html#ab91bb185ea2967b0d2ebbddbca334627", null ], + [ "mcuxClCss_Rng_DrbgRequestRaw_Async", "a00326.html#a39cc1de9838f907dfd488adfa3708cc8", null ], + [ "mcuxClCss_Rng_DrbgRequest_Async", "a00326.html#af28eec2f67bc92ea75f7f9e34da7df76", null ], + [ "mcuxClCss_Rng_DrbgTestAesCtr_Async", "a00326.html#a6345b0fa9905bade69880419710c5b63", null ], + [ "mcuxClCss_Rng_DrbgTestAesEcb_Async", "a00326.html#a3758231b6b62ff158aeeed86dd6239c1", null ], + [ "mcuxClCss_Rng_DrbgTestExtract_Async", "a00326.html#a21303c555b879786c969a371538883f8", null ], + [ "mcuxClCss_Rng_DrbgTestInstantiate_Async", "a00326.html#af2e2ffaf16e1b337950dd59fc5f94bbc", null ], + [ "mcuxClCss_Rng_Dtrng_ConfigEvaluate_Async", "a00326.html#aed7e70c1a0f9ef2879a2141d2ae7ca83", null ], + [ "mcuxClCss_Rng_Dtrng_ConfigLoadPrv_Async", "a00326.html#ad406a85e6342b029eb127d7410c708ed", null ], + [ "mcuxClCss_Rng_Dtrng_ConfigLoad_Async", "a00326.html#ae7d06766bd1f4774295f6504496577d6", null ], + [ "mcuxClCss_SetIntEnableFlags", "a00326.html#a1afbc95754f4ad0c8031537ae1ea15bf", null ], + [ "mcuxClCss_SetIntFlags", "a00326.html#ab7a97b7f0a3482f88488c2f10b3568aa", null ], + [ "mcuxClCss_SetMasterUnlock", "a00326.html#af27b84e8ea5f5022fe735ac690686f67", null ], + [ "mcuxClCss_SetRandomStartDelay", "a00326.html#a88e6dca779d851a941bb49ed7e884c0a", null ], + [ "mcuxClCss_ShaDirect_Disable", "a00326.html#a0e04f10ca4ceada02682e2c93e4b15b9", null ], + [ "mcuxClCss_ShaDirect_Enable", "a00326.html#aa08dec4457d7a9d7de73eee348e3ac4c", null ], + [ "mcuxClCss_TlsGenerateMasterKeyFromPreMasterKey_Async", "a00326.html#aeb497b64cb74701afcbc374c8cd48d4a", null ], + [ "mcuxClCss_TlsGenerateSessionKeysFromMasterKey_Async", "a00326.html#a454844f45c14004191ff6dc283bf0d66", null ], + [ "mcuxClCss_UpdateRefCRC", "a00326.html#a93bc83703c37a678b6e0fc9fbe22cadc", null ], + [ "mcuxClCss_VerifyVsRefCRC", "a00326.html#a371ced4184af49df18e20201ea8f2bba", null ], + [ "mcuxClCss_WaitForOperation", "a00326.html#a1802e6e968c8f327363d8193e6908ba3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00326_source.html b/components/els_pkc/doc/mcxn/html/a00326_source.html new file mode 100644 index 000000000..337585708 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00326_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_mapping.h Source File + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_mapping.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLELS_MAPPING_H_
21 #define MCUXCLELS_MAPPING_H_
22 
23 /* Public definitions */
41 #define MCUXCLCSS_API MCUXCLELS_API
42 #define MCUXCLCSS_AEAD_AAD_BLOCK_SIZE MCUXCLELS_AEAD_AAD_BLOCK_SIZE
43 #define MCUXCLCSS_AEAD_ACPMOD_AADPROC MCUXCLELS_AEAD_ACPMOD_AADPROC
44 #define MCUXCLCSS_AEAD_ACPMOD_FINAL MCUXCLELS_AEAD_ACPMOD_FINAL
45 #define MCUXCLCSS_AEAD_ACPMOD_INIT MCUXCLELS_AEAD_ACPMOD_INIT
46 #define MCUXCLCSS_AEAD_ACPMOD_MSGPROC MCUXCLELS_AEAD_ACPMOD_MSGPROC
47 #define MCUXCLCSS_AEAD_CONTEXT_SIZE MCUXCLELS_AEAD_CONTEXT_SIZE
48 #define MCUXCLCSS_AEAD_DECRYPT MCUXCLELS_AEAD_DECRYPT
49 #define MCUXCLCSS_AEAD_ENCRYPT MCUXCLELS_AEAD_ENCRYPT
50 #define MCUXCLCSS_AEAD_EXTERN_KEY MCUXCLELS_AEAD_EXTERN_KEY
51 #define MCUXCLCSS_AEAD_INTERN_KEY MCUXCLELS_AEAD_INTERN_KEY
52 #define MCUXCLCSS_AEAD_IV_BLOCK_SIZE MCUXCLELS_AEAD_IV_BLOCK_SIZE
53 #define MCUXCLCSS_AEAD_LASTINIT_FALSE MCUXCLELS_AEAD_LASTINIT_FALSE
54 #define MCUXCLCSS_AEAD_LASTINIT_TRUE MCUXCLELS_AEAD_LASTINIT_TRUE
55 #define MCUXCLCSS_AEAD_STATE_IN_DISABLE MCUXCLELS_AEAD_STATE_IN_DISABLE
56 #define MCUXCLCSS_AEAD_STATE_IN_ENABLE MCUXCLELS_AEAD_STATE_IN_ENABLE
57 #define MCUXCLCSS_AEAD_STATE_OUT_ENABLE MCUXCLELS_AEAD_STATE_OUT_ENABLE
58 #define MCUXCLCSS_AEAD_TAG_SIZE MCUXCLELS_AEAD_TAG_SIZE
59 #define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CBC MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
60 #define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CTR MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
61 #define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
62 #define MCUXCLCSS_CIPHER_BLOCK_SIZE_AES MCUXCLELS_CIPHER_BLOCK_SIZE_AES
63 #define MCUXCLCSS_CIPHER_DECRYPT MCUXCLELS_CIPHER_DECRYPT
64 #define MCUXCLCSS_CIPHER_ENCRYPT MCUXCLELS_CIPHER_ENCRYPT
65 #define MCUXCLCSS_CIPHER_EXTERNAL_KEY MCUXCLELS_CIPHER_EXTERNAL_KEY
66 #define MCUXCLCSS_CIPHER_INTERNAL_KEY MCUXCLELS_CIPHER_INTERNAL_KEY
67 #define MCUXCLCSS_CIPHER_KEY_SIZE_AES_128 MCUXCLELS_CIPHER_KEY_SIZE_AES_128
68 #define MCUXCLCSS_CIPHER_KEY_SIZE_AES_192 MCUXCLELS_CIPHER_KEY_SIZE_AES_192
69 #define MCUXCLCSS_CIPHER_KEY_SIZE_AES_256 MCUXCLELS_CIPHER_KEY_SIZE_AES_256
70 #define MCUXCLCSS_CIPHER_STATE_IN_DISABLE MCUXCLELS_CIPHER_STATE_IN_DISABLE
71 #define MCUXCLCSS_CIPHER_STATE_IN_ENABLE MCUXCLELS_CIPHER_STATE_IN_ENABLE
72 #define MCUXCLCSS_CIPHER_STATE_OUT_DISABLE MCUXCLELS_CIPHER_STATE_OUT_DISABLE
73 #define MCUXCLCSS_CIPHER_STATE_OUT_ENABLE MCUXCLELS_CIPHER_STATE_OUT_ENABLE
74 #define MCUXCLCSS_CKDF_ALGO_SP800108 MCUXCLELS_CKDF_ALGO_SP800108
75 #define MCUXCLCSS_CKDF_ALGO_SP80056C_EXPAND MCUXCLELS_CKDF_ALGO_SP80056C_EXPAND
76 #define MCUXCLCSS_CKDF_ALGO_SP80056C_EXTRACT MCUXCLELS_CKDF_ALGO_SP80056C_EXTRACT
77 #define MCUXCLCSS_CKDF_DERIVATIONDATA_SIZE MCUXCLELS_CKDF_DERIVATIONDATA_SIZE
78 #define MCUXCLCSS_HKDF_RTF_DERIV MCUXCLELS_HKDF_RTF_DERIV
79 #define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16 MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16
80 #define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32 MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32
81 #define MCUXCLCSS_HKDF_SYSTEM_MEMORY_DERIV MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV
82 #define MCUXCLCSS_CMAC_EXTERNAL_KEY_DISABLE MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
83 #define MCUXCLCSS_CMAC_EXTERNAL_KEY_ENABLE MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
84 #define MCUXCLCSS_CMAC_FINALIZE_DISABLE MCUXCLELS_CMAC_FINALIZE_DISABLE
85 #define MCUXCLCSS_CMAC_FINALIZE_ENABLE MCUXCLELS_CMAC_FINALIZE_ENABLE
86 #define MCUXCLCSS_CMAC_INITIALIZE_DISABLE MCUXCLELS_CMAC_INITIALIZE_DISABLE
87 #define MCUXCLCSS_CMAC_INITIALIZE_ENABLE MCUXCLELS_CMAC_INITIALIZE_ENABLE
88 #define MCUXCLCSS_CMAC_KEY_SIZE_128 MCUXCLELS_CMAC_KEY_SIZE_128
89 #define MCUXCLCSS_CMAC_KEY_SIZE_256 MCUXCLELS_CMAC_KEY_SIZE_256
90 #define MCUXCLCSS_CMAC_OUT_SIZE MCUXCLELS_CMAC_OUT_SIZE
91 #define MCUXCLCSS_CMD_CRC_CMD_ID_AUTH_CIPHER MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER
92 #define MCUXCLCSS_CMD_CRC_CMD_ID_CHAL_RESP_GEN MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
93 #define MCUXCLCSS_CMD_CRC_CMD_ID_CIPHER MCUXCLELS_CMD_CRC_CMD_ID_CIPHER
94 #define MCUXCLCSS_CMD_CRC_CMD_ID_CKDF MCUXCLELS_CMD_CRC_CMD_ID_CKDF
95 #define MCUXCLCSS_CMD_CRC_CMD_ID_CMAC MCUXCLELS_CMD_CRC_CMD_ID_CMAC
96 #define MCUXCLCSS_CMD_CRC_CMD_ID_DRBG_TEST MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST
97 #define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
98 #define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_EVAL MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL
99 #define MCUXCLCSS_CMD_CRC_CMD_ID_ECKXH MCUXCLELS_CMD_CRC_CMD_ID_ECKXH
100 #define MCUXCLCSS_CMD_CRC_CMD_ID_ECSIGN MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN
101 #define MCUXCLCSS_CMD_CRC_CMD_ID_ECVFY MCUXCLELS_CMD_CRC_CMD_ID_ECVFY
102 #define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_CFG_LOAD MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
103 #define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_TRIM MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM
104 #define MCUXCLCSS_CMD_CRC_CMD_ID_HASH MCUXCLELS_CMD_CRC_CMD_ID_HASH
105 #define MCUXCLCSS_CMD_CRC_CMD_ID_HKDF MCUXCLELS_CMD_CRC_CMD_ID_HKDF
106 #define MCUXCLCSS_CMD_CRC_CMD_ID_HMAC MCUXCLELS_CMD_CRC_CMD_ID_HMAC
107 #define MCUXCLCSS_CMD_CRC_CMD_ID_KDELETE MCUXCLELS_CMD_CRC_CMD_ID_KDELETE
108 #define MCUXCLCSS_CMD_CRC_CMD_ID_KEYGEN MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN
109 #define MCUXCLCSS_CMD_CRC_CMD_ID_KEYIN MCUXCLELS_CMD_CRC_CMD_ID_KEYIN
110 #define MCUXCLCSS_CMD_CRC_CMD_ID_KEYOUT MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT
111 #define MCUXCLCSS_CMD_CRC_CMD_ID_KEYPROV MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV
112 #define MCUXCLCSS_CMD_CRC_CMD_ID_RND_REQ MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ
113 #define MCUXCLCSS_CMD_CRC_CMD_ID_TLS MCUXCLELS_CMD_CRC_CMD_ID_TLS
114 #define MCUXCLCSS_CMD_CRC_DISABLE MCUXCLELS_CMD_CRC_DISABLE
115 #define MCUXCLCSS_CMD_CRC_ENABLE MCUXCLELS_CMD_CRC_ENABLE
116 #define MCUXCLCSS_CMD_CRC_INITIAL_VALUE MCUXCLELS_CMD_CRC_INITIAL_VALUE
117 #define MCUXCLCSS_CMD_CRC_POLYNOMIAL MCUXCLELS_CMD_CRC_POLYNOMIAL
118 #define MCUXCLCSS_CMD_CRC_REFERENCE_INIT MCUXCLELS_CMD_CRC_REFERENCE_INIT
119 #define MCUXCLCSS_CMD_CRC_REFERENCE_RESET MCUXCLELS_CMD_CRC_REFERENCE_RESET
120 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE
121 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT
122 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT
123 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD
124 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA
125 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CIPHER MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER
126 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108 MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108
127 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND
128 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT
129 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CMAC MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC
130 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE
131 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT
132 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN
133 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN
134 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY
135 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT
136 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG
137 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM
138 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HASH MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH
139 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869 MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869
140 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C
141 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HMAC MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC
142 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE
143 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT
144 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT
145 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK
146 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION
147 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM
148 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT
149 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RESPGEN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RESPGEN
150 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST
151 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW
152 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR
153 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB
154 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT
155 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE
156 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE
157 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD
158 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY
159 #define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY
160 #define MCUXCLCSS_CMD_CRC_RESET MCUXCLELS_CMD_CRC_RESET
161 #define MCUXCLCSS_CMD_CRC_VALUE_DISABLE MCUXCLELS_CMD_CRC_VALUE_DISABLE
162 #define MCUXCLCSS_CMD_CRC_VALUE_ENABLE MCUXCLELS_CMD_CRC_VALUE_ENABLE
163 #define MCUXCLCSS_CMD_CRC_VALUE_RESET MCUXCLELS_CMD_CRC_VALUE_RESET
164 #define MCUXCLCSS_CSS_INTERRUPT_DISABLE MCUXCLELS_ELS_INTERRUPT_DISABLE
165 #define MCUXCLCSS_CSS_INTERRUPT_ENABLE MCUXCLELS_ELS_INTERRUPT_ENABLE
166 #define MCUXCLCSS_CSS_INTERRUPT_KEEP MCUXCLELS_ELS_INTERRUPT_KEEP
167 #define MCUXCLCSS_CSS_INTERRUPT_SET MCUXCLELS_ELS_INTERRUPT_SET
168 #define MCUXCLCSS_CSS_RESET_CLEAR MCUXCLELS_ELS_RESET_CLEAR
169 #define MCUXCLCSS_CSS_RESET_KEEP MCUXCLELS_ELS_RESET_KEEP
170 #define MCUXCLCSS_DMA_READBACK_PROTECTION_TOKEN MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN
171 #define MCUXCLCSS_ECC_EXTKEY_EXTERNAL MCUXCLELS_ECC_EXTKEY_EXTERNAL
172 #define MCUXCLCSS_ECC_EXTKEY_INTERNAL MCUXCLELS_ECC_EXTKEY_INTERNAL
173 #define MCUXCLCSS_ECC_GEN_PUBLIC_KEY MCUXCLELS_ECC_GEN_PUBLIC_KEY
174 #define MCUXCLCSS_ECC_HASHED MCUXCLELS_ECC_HASHED
175 #define MCUXCLCSS_ECC_INCLUDE_RANDOM_DATA MCUXCLELS_ECC_INCLUDE_RANDOM_DATA
176 #define MCUXCLCSS_ECC_NOT_HASHED MCUXCLELS_ECC_NOT_HASHED
177 #define MCUXCLCSS_ECC_NO_RANDOM_DATA MCUXCLELS_ECC_NO_RANDOM_DATA
178 #define MCUXCLCSS_ECC_NO_RTF MCUXCLELS_ECC_NO_RTF
179 #define MCUXCLCSS_ECC_OUTPUTKEY_DETERMINISTIC MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
180 #define MCUXCLCSS_ECC_OUTPUTKEY_KEYEXCHANGE MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE
181 #define MCUXCLCSS_ECC_OUTPUTKEY_RANDOM MCUXCLELS_ECC_OUTPUTKEY_RANDOM
182 #define MCUXCLCSS_ECC_OUTPUTKEY_SIGN MCUXCLELS_ECC_OUTPUTKEY_SIGN
183 #define MCUXCLCSS_ECC_PUBLICKEY_SIGN_DISABLE MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
184 #define MCUXCLCSS_ECC_PUBLICKEY_SIGN_ENABLE MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE
185 #define MCUXCLCSS_ECC_PUBLICKEY_SIZE MCUXCLELS_ECC_PUBLICKEY_SIZE
186 #define MCUXCLCSS_ECC_REVERSEFETCH_DISABLE MCUXCLELS_ECC_REVERSEFETCH_DISABLE
187 #define MCUXCLCSS_ECC_REVERSEFETCH_ENABLE MCUXCLELS_ECC_REVERSEFETCH_ENABLE
188 #define MCUXCLCSS_ECC_RTF MCUXCLELS_ECC_RTF
189 #define MCUXCLCSS_ECC_SIGNATURE_R_SIZE MCUXCLELS_ECC_SIGNATURE_R_SIZE
190 #define MCUXCLCSS_ECC_SIGNATURE_SIZE MCUXCLELS_ECC_SIGNATURE_SIZE
191 #define MCUXCLCSS_ECC_SKIP_PUBLIC_KEY MCUXCLELS_ECC_SKIP_PUBLIC_KEY
192 #define MCUXCLCSS_ECC_VALUE_HASHED MCUXCLELS_ECC_VALUE_HASHED
193 #define MCUXCLCSS_ECC_VALUE_NOT_HASHED MCUXCLELS_ECC_VALUE_NOT_HASHED
194 #define MCUXCLCSS_ECC_VALUE_NO_RTF MCUXCLELS_ECC_VALUE_NO_RTF
195 #define MCUXCLCSS_ECC_VALUE_RTF MCUXCLELS_ECC_VALUE_RTF
196 #define MCUXCLCSS_ERROR_FLAGS_CLEAR MCUXCLELS_ERROR_FLAGS_CLEAR
197 #define MCUXCLCSS_ERROR_FLAGS_KEEP MCUXCLELS_ERROR_FLAGS_KEEP
198 #define MCUXCLCSS_GLITCHDETECTOR_CFG_SIZE MCUXCLELS_GLITCHDETECTOR_CFG_SIZE
199 #define MCUXCLCSS_GLITCHDETECTOR_TRIM_SIZE MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE
200 #define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_DISABLE MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE
201 #define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_ENABLE MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE
202 #define MCUXCLCSS_GLITCH_DETECTOR_NEG_KEEP MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP
203 #define MCUXCLCSS_GLITCH_DETECTOR_NEG_SET MCUXCLELS_GLITCH_DETECTOR_NEG_SET
204 #define MCUXCLCSS_GLITCH_DETECTOR_POS_KEEP MCUXCLELS_GLITCH_DETECTOR_POS_KEEP
205 #define MCUXCLCSS_GLITCH_DETECTOR_POS_SET MCUXCLELS_GLITCH_DETECTOR_POS_SET
206 #define MCUXCLCSS_GLITCH_DETECTOR_RESET_CLEAR MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR
207 #define MCUXCLCSS_GLITCH_DETECTOR_RESET_KEEP MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP
208 #define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_224 MCUXCLELS_HASH_BLOCK_SIZE_SHA_224
209 #define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_256 MCUXCLELS_HASH_BLOCK_SIZE_SHA_256
210 #define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_384 MCUXCLELS_HASH_BLOCK_SIZE_SHA_384
211 #define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_512 MCUXCLELS_HASH_BLOCK_SIZE_SHA_512
212 #define MCUXCLCSS_HASH_INIT_DISABLE MCUXCLELS_HASH_INIT_DISABLE
213 #define MCUXCLCSS_HASH_INIT_ENABLE MCUXCLELS_HASH_INIT_ENABLE
214 #define MCUXCLCSS_HASH_LOAD_DISABLE MCUXCLELS_HASH_LOAD_DISABLE
215 #define MCUXCLCSS_HASH_LOAD_ENABLE MCUXCLELS_HASH_LOAD_ENABLE
216 #define MCUXCLCSS_HASH_MODE_SHA_224 MCUXCLELS_HASH_MODE_SHA_224
217 #define MCUXCLCSS_HASH_MODE_SHA_256 MCUXCLELS_HASH_MODE_SHA_256
218 #define MCUXCLCSS_HASH_MODE_SHA_384 MCUXCLELS_HASH_MODE_SHA_384
219 #define MCUXCLCSS_HASH_MODE_SHA_512 MCUXCLELS_HASH_MODE_SHA_512
220 #define MCUXCLCSS_HASH_OUTPUT_DISABLE MCUXCLELS_HASH_OUTPUT_DISABLE
221 #define MCUXCLCSS_HASH_OUTPUT_ENABLE MCUXCLELS_HASH_OUTPUT_ENABLE
222 #define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_224 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224
223 #define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_256 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256
224 #define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_384 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384
225 #define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_512 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512
226 #define MCUXCLCSS_HASH_RTF_OUTPUT_DISABLE MCUXCLELS_HASH_RTF_OUTPUT_DISABLE
227 #define MCUXCLCSS_HASH_RTF_OUTPUT_ENABLE MCUXCLELS_HASH_RTF_OUTPUT_ENABLE
228 #define MCUXCLCSS_HASH_RTF_OUTPUT_SIZE MCUXCLELS_HASH_RTF_OUTPUT_SIZE
229 #define MCUXCLCSS_HASH_RTF_UPDATE_DISABLE MCUXCLELS_HASH_RTF_UPDATE_DISABLE
230 #define MCUXCLCSS_HASH_RTF_UPDATE_ENABLE MCUXCLELS_HASH_RTF_UPDATE_ENABLE
231 #define MCUXCLCSS_HASH_STATE_SIZE_SHA_224 MCUXCLELS_HASH_STATE_SIZE_SHA_224
232 #define MCUXCLCSS_HASH_STATE_SIZE_SHA_256 MCUXCLELS_HASH_STATE_SIZE_SHA_256
233 #define MCUXCLCSS_HASH_STATE_SIZE_SHA_384 MCUXCLELS_HASH_STATE_SIZE_SHA_384
234 #define MCUXCLCSS_HASH_STATE_SIZE_SHA_512 MCUXCLELS_HASH_STATE_SIZE_SHA_512
235 #define MCUXCLCSS_HASH_VALUE_MODE_SHA_224 MCUXCLELS_HASH_VALUE_MODE_SHA_224
236 #define MCUXCLCSS_HASH_VALUE_MODE_SHA_256 MCUXCLELS_HASH_VALUE_MODE_SHA_256
237 #define MCUXCLCSS_HASH_VALUE_MODE_SHA_384 MCUXCLELS_HASH_VALUE_MODE_SHA_384
238 #define MCUXCLCSS_HASH_VALUE_MODE_SHA_512 MCUXCLELS_HASH_VALUE_MODE_SHA_512
239 #define MCUXCLCSS_HKDF_ALGO_RFC5869 MCUXCLELS_HKDF_ALGO_RFC5869
240 #define MCUXCLCSS_HKDF_ALGO_SP80056C MCUXCLELS_HKDF_ALGO_SP80056C
241 #define MCUXCLCSS_HKDF_RFC5869_DERIVATIONDATA_SIZE MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE
242 #define MCUXCLCSS_HKDF_SP80056C_TARGETKEY_SIZE MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE
243 #define MCUXCLCSS_HKDF_VALUE_MEMORY_DERIV MCUXCLELS_HKDF_VALUE_MEMORY_DERIV
244 #define MCUXCLCSS_HKDF_VALUE_RTF_DERIV MCUXCLELS_HKDF_VALUE_RTF_DERIV
245 #define MCUXCLCSS_HMAC_EXTERNAL_KEY_DISABLE MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
246 #define MCUXCLCSS_HMAC_EXTERNAL_KEY_ENABLE MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
247 #define MCUXCLCSS_HMAC_OUTPUT_SIZE MCUXCLELS_HMAC_OUTPUT_SIZE
248 #define MCUXCLCSS_HMAC_PADDED_KEY_SIZE MCUXCLELS_HMAC_PADDED_KEY_SIZE
249 #define MCUXCLCSS_HW_VERSION MCUXCLELS_HW_VERSION
250 #define MCUXCLCSS_KEYGEN_VALUE_DETERMINISTIC MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC
251 #define MCUXCLCSS_KEYGEN_VALUE_GEN_PUB_KEY MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY
252 #define MCUXCLCSS_KEYGEN_VALUE_NO_PUB_KEY MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY
253 #define MCUXCLCSS_KEYGEN_VALUE_NO_RANDOM_DATA MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA
254 #define MCUXCLCSS_KEYGEN_VALUE_RANDOM MCUXCLELS_KEYGEN_VALUE_RANDOM
255 #define MCUXCLCSS_KEYGEN_VALUE_SIGN_PUBLICKEY MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY
256 #define MCUXCLCSS_KEYGEN_VALUE_TYPE_KEYEXCHANGE MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
257 #define MCUXCLCSS_KEYGEN_VALUE_TYPE_SIGN MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN
258 #define MCUXCLCSS_KEYGEN_VALUE_USE_RANDOM_DATA MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA
259 #define MCUXCLCSS_KEYIMPORT_KFMT_PBK MCUXCLELS_KEYIMPORT_KFMT_PBK
260 #define MCUXCLCSS_KEYIMPORT_KFMT_PUF MCUXCLELS_KEYIMPORT_KFMT_PUF
261 #define MCUXCLCSS_KEYIMPORT_KFMT_RFC3394 MCUXCLELS_KEYIMPORT_KFMT_RFC3394
262 #define MCUXCLCSS_KEYIMPORT_KFMT_UDF MCUXCLELS_KEYIMPORT_KFMT_UDF
263 #define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_DISABLE MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE
264 #define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_ENABLE MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE
265 #define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PBK MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK
266 #define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PUF MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF
267 #define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_RFC3394 MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394
268 #define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_UDF MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF
269 #define MCUXCLCSS_KEYPROPERTY_ACTIVE_FALSE MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE
270 #define MCUXCLCSS_KEYPROPERTY_ACTIVE_TRUE MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
271 #define MCUXCLCSS_KEYPROPERTY_AES_FALSE MCUXCLELS_KEYPROPERTY_AES_FALSE
272 #define MCUXCLCSS_KEYPROPERTY_AES_TRUE MCUXCLELS_KEYPROPERTY_AES_TRUE
273 #define MCUXCLCSS_KEYPROPERTY_BASE_SLOT MCUXCLELS_KEYPROPERTY_BASE_SLOT
274 #define MCUXCLCSS_KEYPROPERTY_CKDF_FALSE MCUXCLELS_KEYPROPERTY_CKDF_FALSE
275 #define MCUXCLCSS_KEYPROPERTY_CKDF_TRUE MCUXCLELS_KEYPROPERTY_CKDF_TRUE
276 #define MCUXCLCSS_KEYPROPERTY_CMAC_FALSE MCUXCLELS_KEYPROPERTY_CMAC_FALSE
277 #define MCUXCLCSS_KEYPROPERTY_CMAC_TRUE MCUXCLELS_KEYPROPERTY_CMAC_TRUE
278 #define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_FALSE MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
279 #define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_TRUE MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
280 #define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
281 #define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
282 #define MCUXCLCSS_KEYPROPERTY_ECC_FALSE MCUXCLELS_KEYPROPERTY_ECC_FALSE
283 #define MCUXCLCSS_KEYPROPERTY_ECC_TRUE MCUXCLELS_KEYPROPERTY_ECC_TRUE
284 #define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
285 #define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
286 #define MCUXCLCSS_KEYPROPERTY_HKDF_FALSE MCUXCLELS_KEYPROPERTY_HKDF_FALSE
287 #define MCUXCLCSS_KEYPROPERTY_HKDF_TRUE MCUXCLELS_KEYPROPERTY_HKDF_TRUE
288 #define MCUXCLCSS_KEYPROPERTY_HMAC_FALSE MCUXCLELS_KEYPROPERTY_HMAC_FALSE
289 #define MCUXCLCSS_KEYPROPERTY_HMAC_TRUE MCUXCLELS_KEYPROPERTY_HMAC_TRUE
290 #define MCUXCLCSS_KEYPROPERTY_HW_OUT_FALSE MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE
291 #define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_FALSE MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE
292 #define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_TRUE MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE
293 #define MCUXCLCSS_KEYPROPERTY_HW_OUT_TRUE MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE
294 #define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_FALSE MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
295 #define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_TRUE MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
296 #define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_128 MCUXCLELS_KEYPROPERTY_KEY_SIZE_128
297 #define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_256 MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
298 #define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_512 MCUXCLELS_KEYPROPERTY_KEY_SIZE_512
299 #define MCUXCLCSS_KEYPROPERTY_KSK_FALSE MCUXCLELS_KEYPROPERTY_KSK_FALSE
300 #define MCUXCLCSS_KEYPROPERTY_KSK_TRUE MCUXCLELS_KEYPROPERTY_KSK_TRUE
301 #define MCUXCLCSS_KEYPROPERTY_KUOK_FALSE MCUXCLELS_KEYPROPERTY_KUOK_FALSE
302 #define MCUXCLCSS_KEYPROPERTY_KUOK_TRUE MCUXCLELS_KEYPROPERTY_KUOK_TRUE
303 #define MCUXCLCSS_KEYPROPERTY_KWK_FALSE MCUXCLELS_KEYPROPERTY_KWK_FALSE
304 #define MCUXCLCSS_KEYPROPERTY_KWK_TRUE MCUXCLELS_KEYPROPERTY_KWK_TRUE
305 #define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_FALSE MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE
306 #define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_TRUE MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
307 #define MCUXCLCSS_KEYPROPERTY_PUK_FALSE MCUXCLELS_KEYPROPERTY_PUK_FALSE
308 #define MCUXCLCSS_KEYPROPERTY_PUK_TRUE MCUXCLELS_KEYPROPERTY_PUK_TRUE
309 #define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_FALSE MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE
310 #define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_TRUE MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE
311 #define MCUXCLCSS_KEYPROPERTY_RTF_FALSE MCUXCLELS_KEYPROPERTY_RTF_FALSE
312 #define MCUXCLCSS_KEYPROPERTY_RTF_TRUE MCUXCLELS_KEYPROPERTY_RTF_TRUE
313 #define MCUXCLCSS_KEYPROPERTY_SECOND_SLOT MCUXCLELS_KEYPROPERTY_SECOND_SLOT
314 #define MCUXCLCSS_KEYPROPERTY_SECURE_FALSE MCUXCLELS_KEYPROPERTY_SECURE_FALSE
315 #define MCUXCLCSS_KEYPROPERTY_SECURE_TRUE MCUXCLELS_KEYPROPERTY_SECURE_TRUE
316 #define MCUXCLCSS_KEYPROPERTY_TECDH_FALSE MCUXCLELS_KEYPROPERTY_TECDH_FALSE
317 #define MCUXCLCSS_KEYPROPERTY_TECDH_TRUE MCUXCLELS_KEYPROPERTY_TECDH_TRUE
318 #define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
319 #define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
320 #define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
321 #define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
322 #define MCUXCLCSS_KEYPROPERTY_VALUE_ACTIVE MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE
323 #define MCUXCLCSS_KEYPROPERTY_VALUE_AES MCUXCLELS_KEYPROPERTY_VALUE_AES
324 #define MCUXCLCSS_KEYPROPERTY_VALUE_BASE_SLOT MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT
325 #define MCUXCLCSS_KEYPROPERTY_VALUE_CKDF MCUXCLELS_KEYPROPERTY_VALUE_CKDF
326 #define MCUXCLCSS_KEYPROPERTY_VALUE_CMAC MCUXCLELS_KEYPROPERTY_VALUE_CMAC
327 #define MCUXCLCSS_KEYPROPERTY_VALUE_DUK MCUXCLELS_KEYPROPERTY_VALUE_DUK
328 #define MCUXCLCSS_KEYPROPERTY_VALUE_ECDH MCUXCLELS_KEYPROPERTY_VALUE_ECDH
329 #define MCUXCLCSS_KEYPROPERTY_VALUE_ECSGN MCUXCLELS_KEYPROPERTY_VALUE_ECSGN
330 #define MCUXCLCSS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
331 #define MCUXCLCSS_KEYPROPERTY_VALUE_HKDF MCUXCLELS_KEYPROPERTY_VALUE_HKDF
332 #define MCUXCLCSS_KEYPROPERTY_VALUE_HMAC MCUXCLELS_KEYPROPERTY_VALUE_HMAC
333 #define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT
334 #define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT_SLOT MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT
335 #define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_128 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128
336 #define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_256 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256
337 #define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_512 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512
338 #define MCUXCLCSS_KEYPROPERTY_VALUE_KGSRC MCUXCLELS_KEYPROPERTY_VALUE_KGSRC
339 #define MCUXCLCSS_KEYPROPERTY_VALUE_KSK MCUXCLELS_KEYPROPERTY_VALUE_KSK
340 #define MCUXCLCSS_KEYPROPERTY_VALUE_KUOK MCUXCLELS_KEYPROPERTY_VALUE_KUOK
341 #define MCUXCLCSS_KEYPROPERTY_VALUE_KWK MCUXCLELS_KEYPROPERTY_VALUE_KWK
342 #define MCUXCLCSS_KEYPROPERTY_VALUE_NOTPRIVILEGED MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED
343 #define MCUXCLCSS_KEYPROPERTY_VALUE_NOTSECURE MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE
344 #define MCUXCLCSS_KEYPROPERTY_VALUE_PRIVILEGED MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED
345 #define MCUXCLCSS_KEYPROPERTY_VALUE_PUK MCUXCLELS_KEYPROPERTY_VALUE_PUK
346 #define MCUXCLCSS_KEYPROPERTY_VALUE_RETENTION_SLOT MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT
347 #define MCUXCLCSS_KEYPROPERTY_VALUE_RTF MCUXCLELS_KEYPROPERTY_VALUE_RTF
348 #define MCUXCLCSS_KEYPROPERTY_VALUE_SECURE MCUXCLELS_KEYPROPERTY_VALUE_SECURE
349 #define MCUXCLCSS_KEYPROPERTY_VALUE_TECDH MCUXCLELS_KEYPROPERTY_VALUE_TECDH
350 #define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
351 #define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
352 #define MCUXCLCSS_KEYPROPERTY_VALUE_WRPOK MCUXCLELS_KEYPROPERTY_VALUE_WRPOK
353 #define MCUXCLCSS_KEYPROPERTY_WRAP_FALSE MCUXCLELS_KEYPROPERTY_WRAP_FALSE
354 #define MCUXCLCSS_KEYPROPERTY_WRAP_TRUE MCUXCLELS_KEYPROPERTY_WRAP_TRUE
355 #define MCUXCLCSS_KEYPROV_DUK_UPDATE_DISABLE MCUXCLELS_KEYPROV_DUK_UPDATE_DISABLE
356 #define MCUXCLCSS_KEYPROV_DUK_UPDATE_ENABLE MCUXCLELS_KEYPROV_DUK_UPDATE_ENABLE
357 #define MCUXCLCSS_KEYPROV_KEYSHARE_TABLE_SIZE MCUXCLELS_KEYPROV_KEYSHARE_TABLE_SIZE
358 #define MCUXCLCSS_KEYPROV_KEY_PART_1_SIZE MCUXCLELS_KEYPROV_KEY_PART_1_SIZE
359 #define MCUXCLCSS_KEYPROV_NOIC_DISABLE MCUXCLELS_KEYPROV_NOIC_DISABLE
360 #define MCUXCLCSS_KEYPROV_NOIC_ENABLE MCUXCLELS_KEYPROV_NOIC_ENABLE
361 #define MCUXCLCSS_KEYPROV_TESTERSHARE_SIZE MCUXCLELS_KEYPROV_TESTERSHARE_SIZE
362 #define MCUXCLCSS_KEYPROV_VALUE_NOIC MCUXCLELS_KEYPROV_VALUE_NOIC
363 #define MCUXCLCSS_KEY_SLOTS MCUXCLELS_KEY_SLOTS
364 #define MCUXCLCSS_MASTER_UNLOCK_ANY MCUXCLELS_MASTER_UNLOCK_ANY
365 #define MCUXCLCSS_RESET_CANCEL MCUXCLELS_RESET_CANCEL
366 #define MCUXCLCSS_RESET_DO_NOT_CANCEL MCUXCLELS_RESET_DO_NOT_CANCEL
367 #define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_0 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_0
368 #define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_1 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_1
369 #define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_2 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_2
370 #define MCUXCLCSS_RESP_GEN_SLOTS MCUXCLELS_RESP_GEN_SLOTS
371 #define MCUXCLCSS_RFC3394_CONTAINER_SIZE_128 MCUXCLELS_RFC3394_CONTAINER_SIZE_128
372 #define MCUXCLCSS_RFC3394_CONTAINER_SIZE_256 MCUXCLELS_RFC3394_CONTAINER_SIZE_256
373 #define MCUXCLCSS_RFC3394_CONTAINER_SIZE_P256 MCUXCLELS_RFC3394_CONTAINER_SIZE_P256
374 #define MCUXCLCSS_RFC3394_OVERHEAD MCUXCLELS_RFC3394_OVERHEAD
375 #define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
376 #define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
377 #define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_CTR MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR
378 #define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_ECB MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB
379 #define MCUXCLCSS_RNG_DRBG_TEST_MODE_EXTRACT MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT
380 #define MCUXCLCSS_RNG_DRBG_TEST_MODE_INSTANTIATE MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE
381 #define MCUXCLCSS_RNG_DTRNG_CONFIG_SIZE MCUXCLELS_RNG_DTRNG_CONFIG_SIZE
382 #define MCUXCLCSS_RNG_DTRNG_EVAL_CONFIG_SIZE MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE
383 #define MCUXCLCSS_RNG_DTRNG_EVAL_RESULT_SIZE MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE
384 #define MCUXCLCSS_RNG_RAW_ENTROPY_SIZE MCUXCLELS_RNG_RAW_ENTROPY_SIZE
385 #define MCUXCLCSS_RNG_RND_REQ_PRND_INIT MCUXCLELS_RNG_RND_REQ_PRND_INIT
386 #define MCUXCLCSS_RNG_RND_REQ_RND_RAW MCUXCLELS_RNG_RND_REQ_RND_RAW
387 #define MCUXCLCSS_STATUS_DRBGENTLVL_HIGH MCUXCLELS_STATUS_DRBGENTLVL_HIGH
388 #define MCUXCLCSS_STATUS_DRBGENTLVL_LOW MCUXCLELS_STATUS_DRBGENTLVL_LOW
389 #define MCUXCLCSS_STATUS_DRBGENTLVL_NONE MCUXCLELS_STATUS_DRBGENTLVL_NONE
390 #define MCUXCLCSS_STATUS_ECDSAVFY_ERROR MCUXCLELS_STATUS_ECDSAVFY_ERROR
391 #define MCUXCLCSS_STATUS_ECDSAVFY_FAIL MCUXCLELS_STATUS_ECDSAVFY_FAIL
392 #define MCUXCLCSS_STATUS_ECDSAVFY_NORUN MCUXCLELS_STATUS_ECDSAVFY_NORUN
393 #define MCUXCLCSS_STATUS_ECDSAVFY_OK MCUXCLELS_STATUS_ECDSAVFY_OK
394 #define MCUXCLCSS_STATUS_HW_ALGORITHM MCUXCLELS_STATUS_HW_ALGORITHM
395 #define MCUXCLCSS_STATUS_HW_BUS MCUXCLELS_STATUS_HW_BUS
396 #define MCUXCLCSS_STATUS_HW_DTRNG MCUXCLELS_STATUS_HW_DTRNG
397 #define MCUXCLCSS_STATUS_HW_FAULT MCUXCLELS_STATUS_HW_FAULT
398 #define MCUXCLCSS_STATUS_HW_INTEGRITY MCUXCLELS_STATUS_HW_INTEGRITY
399 #define MCUXCLCSS_STATUS_HW_OPERATIONAL MCUXCLELS_STATUS_HW_OPERATIONAL
400 #define MCUXCLCSS_STATUS_HW_PRNG MCUXCLELS_STATUS_HW_PRNG
401 #define MCUXCLCSS_STATUS_IS_HW_ERROR MCUXCLELS_STATUS_IS_HW_ERROR
402 #define MCUXCLCSS_STATUS_IS_SW_ERROR MCUXCLELS_STATUS_IS_SW_ERROR
403 #define MCUXCLCSS_STATUS_OK MCUXCLELS_STATUS_OK
404 #define MCUXCLCSS_STATUS_OK_WAIT MCUXCLELS_STATUS_OK_WAIT
405 #define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_NONSECURE MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE
406 #define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_SECURE MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE
407 #define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_NONSECURE MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
408 #define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_SECURE MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE
409 #define MCUXCLCSS_STATUS_SW_CANNOT_INTERRUPT MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT
410 #define MCUXCLCSS_STATUS_SW_COMPARISON_FAILED MCUXCLELS_STATUS_SW_COMPARISON_FAILED
411 #define MCUXCLCSS_STATUS_SW_COUNTER_EXPIRED MCUXCLELS_STATUS_SW_COUNTER_EXPIRED
412 #define MCUXCLCSS_STATUS_SW_FAULT MCUXCLELS_STATUS_SW_FAULT
413 #define MCUXCLCSS_STATUS_SW_INVALID_PARAM MCUXCLELS_STATUS_SW_INVALID_PARAM
414 #define MCUXCLCSS_STATUS_SW_INVALID_STATE MCUXCLELS_STATUS_SW_INVALID_STATE
415 #define MCUXCLCSS_STATUS_SW_LOCKING_FAILED MCUXCLELS_STATUS_SW_LOCKING_FAILED
416 #define MCUXCLCSS_STATUS_SW_STATUS_LOCKED MCUXCLELS_STATUS_SW_STATUS_LOCKED
417 #define MCUXCLCSS_TLS_DERIVATIONDATA_SIZE MCUXCLELS_TLS_DERIVATIONDATA_SIZE
418 #define MCUXCLCSS_TLS_FINALIZE MCUXCLELS_TLS_FINALIZE
419 #define MCUXCLCSS_TLS_INIT MCUXCLELS_TLS_INIT
420 #define MCUXCLCSS_TLS_RANDOM_SIZE MCUXCLELS_TLS_RANDOM_SIZE
421 
422 
423 /* Public types */
429 #define mcuxClCss_AeadOption_t mcuxClEls_AeadOption_t
430 #define mcuxClCss_CipherOption_t mcuxClEls_CipherOption_t
431 #define mcuxClCss_CkdfOption_t mcuxClEls_CkdfOption_t
432 #define mcuxClCss_CmacOption_t mcuxClEls_CmacOption_t
433 #define mcuxClCss_CommandCrcConfig_t mcuxClEls_CommandCrcConfig_t
434 #define mcuxClCss_EccByte_t mcuxClEls_EccByte_t
435 #define mcuxClCss_EccKeyExchOption_t mcuxClEls_EccKeyExchOption_t
436 #define mcuxClCss_EccKeyGenOption_t mcuxClEls_EccKeyGenOption_t
437 #define mcuxClCss_EccSignOption_t mcuxClEls_EccSignOption_t
438 #define mcuxClCss_EccVerifyOption_t mcuxClEls_EccVerifyOption_t
439 #define mcuxClCss_ErrorHandling_t mcuxClEls_ErrorHandling_t
440 #define mcuxClCss_HashOption_t mcuxClEls_HashOption_t
441 #define mcuxClCss_HkdfOption_t mcuxClEls_HkdfOption_t
442 #define mcuxClCss_HmacOption_t mcuxClEls_HmacOption_t
443 #define mcuxClCss_HwConfig_t mcuxClEls_HwConfig_t
444 #define mcuxClCss_HwState_t mcuxClEls_HwState_t
445 #define mcuxClCss_HwVersion_t mcuxClEls_HwVersion_t
446 #define mcuxClCss_InterruptOptionEn_t mcuxClEls_InterruptOptionEn_t
447 #define mcuxClCss_InterruptOptionRst_t mcuxClEls_InterruptOptionRst_t
448 #define mcuxClCss_InterruptOptionSet_t mcuxClEls_InterruptOptionSet_t
449 #define mcuxClCss_KeyImportOption_t mcuxClEls_KeyImportOption_t
450 #define mcuxClCss_KeyIndex_t mcuxClEls_KeyIndex_t
451 #define mcuxClCss_KeyProp_t mcuxClEls_KeyProp_t
452 #define mcuxClCss_KeyProvisionOption_t mcuxClEls_KeyProvisionOption_t
453 #define mcuxClCss_ResetOption_t mcuxClEls_ResetOption_t
454 #define mcuxClCss_Status_Protected_t mcuxClEls_Status_Protected_t
455 #define mcuxClCss_Status_t mcuxClEls_Status_t
456 #define mcuxClCss_TlsOption_t mcuxClEls_TlsOption_t
457 #define mcuxClCss_TransferToRegisterFunction_t mcuxClEls_TransferToRegisterFunction_t
458 
459 
460 /* Public functions */
466 #define mcuxClCss_Aead_Finalize_Async mcuxClEls_Aead_Finalize_Async
467 #define mcuxClCss_Aead_Init_Async mcuxClEls_Aead_Init_Async
468 #define mcuxClCss_Aead_PartialInit_Async mcuxClEls_Aead_PartialInit_Async
469 #define mcuxClCss_Aead_UpdateAad_Async mcuxClEls_Aead_UpdateAad_Async
470 #define mcuxClCss_Aead_UpdateData_Async mcuxClEls_Aead_UpdateData_Async
471 #define mcuxClCss_Cipher_Async mcuxClEls_Cipher_Async
472 #define mcuxClCss_Ckdf_Sp800108_Async mcuxClEls_Ckdf_Sp800108_Async
473 #define mcuxClCss_Ckdf_Sp80056c_Expand_Async mcuxClEls_Ckdf_Sp80056c_Expand_Async
474 #define mcuxClCss_Ckdf_Sp80056c_Extract_Async mcuxClEls_Ckdf_Sp80056c_Extract_Async
475 #define mcuxClCss_Cmac_Async mcuxClEls_Cmac_Async
476 #define mcuxClCss_CompareDmaFinalOutputAddress mcuxClEls_CompareDmaFinalOutputAddress
477 #define mcuxClCss_ConfigureCommandCRC mcuxClEls_ConfigureCommandCRC
478 #define mcuxClCss_Disable mcuxClEls_Disable
479 #define mcuxClCss_EccKeyExchangeInt_Async mcuxClEls_EccKeyExchangeInt_Async
480 #define mcuxClCss_EccKeyExchange_Async mcuxClEls_EccKeyExchange_Async
481 #define mcuxClCss_EccKeyGen_Async mcuxClEls_EccKeyGen_Async
482 #define mcuxClCss_EccSign_Async mcuxClEls_EccSign_Async
483 #define mcuxClCss_EccVerifyInt_Async mcuxClEls_EccVerifyInt_Async
484 #define mcuxClCss_EccVerify_Async mcuxClEls_EccVerify_Async
485 #define mcuxClCss_Enable_Async mcuxClEls_Enable_Async
486 #define mcuxClCss_GetCommandCRC mcuxClEls_GetCommandCRC
487 #define mcuxClCss_GetErrorCode mcuxClEls_GetErrorCode
488 #define mcuxClCss_GetErrorLevel mcuxClEls_GetErrorLevel
489 #define mcuxClCss_GetHwConfig mcuxClEls_GetHwConfig
490 #define mcuxClCss_GetHwState mcuxClEls_GetHwState
491 #define mcuxClCss_GetHwVersion mcuxClEls_GetHwVersion
492 #define mcuxClCss_GetIntEnableFlags mcuxClEls_GetIntEnableFlags
493 #define mcuxClCss_GetKeyProperties mcuxClEls_GetKeyProperties
494 #define mcuxClCss_GetLastDmaAddress mcuxClEls_GetLastDmaAddress
495 #define mcuxClCss_GetLock mcuxClEls_GetLock
496 #define mcuxClCss_GetRandomStartDelay mcuxClEls_GetRandomStartDelay
497 #define mcuxClCss_GlitchDetector_GetEventCounter mcuxClEls_GlitchDetector_GetEventCounter
498 #define mcuxClCss_GlitchDetector_LoadConfig_Async mcuxClEls_GlitchDetector_LoadConfig_Async
499 #define mcuxClCss_GlitchDetector_ResetEventCounter mcuxClEls_GlitchDetector_ResetEventCounter
500 #define mcuxClCss_GlitchDetector_Trim_Async mcuxClEls_GlitchDetector_Trim_Async
501 #define mcuxClCss_Hash_Async mcuxClEls_Hash_Async
502 #define mcuxClCss_Hash_ShaDirect mcuxClEls_Hash_ShaDirect
503 #define mcuxClCss_Hkdf_Rfc5869_Async mcuxClEls_Hkdf_Rfc5869_Async
504 #define mcuxClCss_Hkdf_Sp80056c_Async mcuxClEls_Hkdf_Sp80056c_Async
505 #define mcuxClCss_Hmac_Async mcuxClEls_Hmac_Async
506 #define mcuxClCss_IsLocked mcuxClEls_IsLocked
507 #define mcuxClCss_KeyDelete_Async mcuxClEls_KeyDelete_Async
508 #define mcuxClCss_KeyExport_Async mcuxClEls_KeyExport_Async
509 #define mcuxClCss_KeyImportPuk_Async mcuxClEls_KeyImportPuk_Async
510 #define mcuxClCss_KeyImport_Async mcuxClEls_KeyImport_Async
511 #define mcuxClCss_KeyProvisionRom_Async mcuxClEls_KeyProvisionRom_Async
512 #define mcuxClCss_KeyProvision_Async mcuxClEls_KeyProvision_Async
513 #define mcuxClCss_LimitedWaitForOperation mcuxClEls_LimitedWaitForOperation
514 #define mcuxClCss_Prng_GetRandom mcuxClEls_Prng_GetRandom
515 #define mcuxClCss_Prng_GetRandomWord mcuxClEls_Prng_GetRandomWord
516 #define mcuxClCss_Prng_Init_Async mcuxClEls_Prng_Init_Async
517 #define mcuxClCss_ReleaseLock mcuxClEls_ReleaseLock
518 #define mcuxClCss_ResetErrorFlags mcuxClEls_ResetErrorFlags
519 #define mcuxClCss_ResetIntFlags mcuxClEls_ResetIntFlags
520 #define mcuxClCss_Reset_Async mcuxClEls_Reset_Async
521 #define mcuxClCss_RespGen_Async mcuxClEls_RespGen_Async
522 #define mcuxClCss_Rng_DrbgRequestRaw_Async mcuxClEls_Rng_DrbgRequestRaw_Async
523 #define mcuxClCss_Rng_DrbgRequest_Async mcuxClEls_Rng_DrbgRequest_Async
524 #define mcuxClCss_Rng_DrbgTestAesCtr_Async mcuxClEls_Rng_DrbgTestAesCtr_Async
525 #define mcuxClCss_Rng_DrbgTestAesEcb_Async mcuxClEls_Rng_DrbgTestAesEcb_Async
526 #define mcuxClCss_Rng_DrbgTestExtract_Async mcuxClEls_Rng_DrbgTestExtract_Async
527 #define mcuxClCss_Rng_DrbgTestInstantiate_Async mcuxClEls_Rng_DrbgTestInstantiate_Async
528 #define mcuxClCss_Rng_Dtrng_ConfigEvaluate_Async mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async
529 #define mcuxClCss_Rng_Dtrng_ConfigLoadPrv_Async mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async
530 #define mcuxClCss_Rng_Dtrng_ConfigLoad_Async mcuxClEls_Rng_Dtrng_ConfigLoad_Async
531 #define mcuxClCss_SetIntEnableFlags mcuxClEls_SetIntEnableFlags
532 #define mcuxClCss_SetIntFlags mcuxClEls_SetIntFlags
533 #define mcuxClCss_SetMasterUnlock mcuxClEls_SetMasterUnlock
534 #define mcuxClCss_SetRandomStartDelay mcuxClEls_SetRandomStartDelay
535 #define mcuxClCss_ShaDirect_Disable mcuxClEls_ShaDirect_Disable
536 #define mcuxClCss_ShaDirect_Enable mcuxClEls_ShaDirect_Enable
537 #define mcuxClCss_TlsGenerateMasterKeyFromPreMasterKey_Async mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
538 #define mcuxClCss_TlsGenerateSessionKeysFromMasterKey_Async mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async
539 #define mcuxClCss_UpdateRefCRC mcuxClEls_UpdateRefCRC
540 #define mcuxClCss_VerifyVsRefCRC mcuxClEls_VerifyVsRefCRC
541 #define mcuxClCss_WaitForOperation mcuxClEls_WaitForOperation
542 
549 #endif /* MCUXCLELS_MAPPING_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00329.html b/components/els_pkc/doc/mcxn/html/a00329.html new file mode 100644 index 000000000..6ad90f758 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00329.html @@ -0,0 +1,195 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros | +Functions
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+
mcuxClEls_Rng.h File Reference
+
+
+ +

ELS header for random number generation. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClEls_Common.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE
 Size of DTRNG configuration. More...
 
#define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE
 Size of DTRNG characterization data. More...
 
#define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE
 Size of DTRNG characterization result. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
 Minimum output size of mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
 Maximum output size of mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE
 Command options value for DRBG Test Instantiate command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT
 Command options value for DRBG Test Extract command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB
 Command options value for DRBG Test AES-ECB command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR
 Command options value for DRBG Test AES-CTR command. For internal use. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgRequest_Async (uint8_t *pOutput, size_t outputLength)
 Writes random data from the ELS DRBG to the given buffer. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestInstantiate_Async (uint8_t const *pEntropy)
 Instantiates the DRBG in test mode. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestExtract_Async (uint8_t *pOutput, size_t outputLength)
 Performs a DRBG extraction. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesEcb_Async (uint8_t const *pDataKey, uint8_t *pOutput)
 Encrypts data using the AES-ECB engine of the DRBG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesCtr_Async (uint8_t const *pData, size_t dataLength, uint8_t const *pIvKey, uint8_t *pOutput)
 Encrypts data using the AES-CTR engine of the DRBG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigLoad_Async (uint8_t const *pInput)
 Loads a configuration of the ELS DTRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async (uint8_t const *pInput, uint8_t *pOutput)
 Performs characterization of the ELS DTRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandomWord (uint32_t *pWord)
 Returns one random word from the ELS PRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandom (uint8_t *pOutput, size_t outputLength)
 Writes random data from the ELS PRNG to the given buffer. More...
 
+

Detailed Description

+

ELS header for random number generation.

+

This header exposes functions to configure the ELS RNGs (DRBG and DTRNG) and to generate random data.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00329.js b/components/els_pkc/doc/mcxn/html/a00329.js new file mode 100644 index 000000000..138bf88db --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00329.js @@ -0,0 +1,21 @@ +var a00329 = +[ + [ "MCUXCLELS_RNG_DTRNG_CONFIG_SIZE", "a00761.html#ga62287bdc5d7f577d4196b409fa9e27c2", null ], + [ "MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE", "a00761.html#ga05b362ef8faa883390e693f6f0499261", null ], + [ "MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE", "a00761.html#ga612e743bb2a36fec076fbf45bb9fb871", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE", "a00761.html#ga4e1cd62dea9fd027f68c6e95f887a052", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE", "a00761.html#ga28815696e8ff825c435f97fd74a63682", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE", "a00761.html#gaefdcd27bd482d26a59b449860c7c07e6", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT", "a00761.html#ga6e8e503cbc286ca4082b3f8f757e43b8", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB", "a00761.html#gac1504aed0077bef23daf988d3630b089", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR", "a00761.html#gafe0506d5703701493637b44873e80f9c", null ], + [ "mcuxClEls_Rng_DrbgRequest_Async", "a00762.html#gac48eddfc58d2fc6aebe0dd373baf4360", null ], + [ "mcuxClEls_Rng_DrbgTestInstantiate_Async", "a00762.html#ga17e52c0038540a032faf460033df35e6", null ], + [ "mcuxClEls_Rng_DrbgTestExtract_Async", "a00762.html#ga89b800a51c4046c7c7736d545595e097", null ], + [ "mcuxClEls_Rng_DrbgTestAesEcb_Async", "a00762.html#gaa356b6cafdb26f78c90fc9a24dd7dcd8", null ], + [ "mcuxClEls_Rng_DrbgTestAesCtr_Async", "a00762.html#gada018f6414175632aa2328ffd2ed02bf", null ], + [ "mcuxClEls_Rng_Dtrng_ConfigLoad_Async", "a00762.html#ga254ab1259a0688701233e1cf3636b244", null ], + [ "mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async", "a00762.html#gac7fb747c02024315df352977d8269535", null ], + [ "mcuxClEls_Prng_GetRandomWord", "a00762.html#ga10ee7783feeef4fbe5d5309c61f358a1", null ], + [ "mcuxClEls_Prng_GetRandom", "a00762.html#ga222cf598c85ceb0483297169255688b0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00329_source.html b/components/els_pkc/doc/mcxn/html/a00329_source.html new file mode 100644 index 000000000..f0802785e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00329_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEls_Rng.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLELS_RNG_H_
21 #define MCUXCLELS_RNG_H_
22 
23 #include <mcuxClConfig.h> // Exported features flags header
24 #include <mcuxClEls_Common.h> // Common functionality
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
38 /**********************************************
39  * CONSTANTS
40  **********************************************/
47 #define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE ((uint8_t) 84)
48 #define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE ((uint8_t) 52)
49 #define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE ((uint8_t) 188)
50 
51 #define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE 4U
52 #define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE ((uint32_t) 1U << 16U)
53 
54 #define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE ((uint32_t) 0U)
55 #define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT ((uint32_t) 1U)
56 #define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB ((uint32_t) 3U)
57 #define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR ((uint32_t) 2U)
58 
59 #ifdef MCUXCL_FEATURE_ELS_RND_RAW
60 #define MCUXCLELS_RNG_RND_REQ_RND_RAW ((uint32_t) 1U << 1)
61 #define MCUXCLELS_RNG_RAW_ENTROPY_SIZE ((uint32_t) 32U)
62 #endif /* MCUXCL_FEATURE_ELS_RND_RAW */
63 #ifdef MCUXCL_FEATURE_ELS_PRND_INIT
64 #define MCUXCLELS_RNG_RND_REQ_PRND_INIT ((uint32_t) 1U << 0)
65 #endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
66 
71 /**********************************************
72  * FUNCTIONS
73  **********************************************/
118 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequest_Async)
119 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequest_Async(
120  uint8_t * pOutput,
121  size_t outputLength
122  );
123 
124 #ifdef MCUXCL_FEATURE_ELS_RND_RAW
125 
142 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequestRaw_Async)
143 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequestRaw_Async(
144  uint8_t * pOutput
145  );
146 #endif /* MCUXCL_FEATURE_ELS_RND_RAW */
147 
166 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestInstantiate_Async)
167 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestInstantiate_Async(
168  uint8_t const * pEntropy
169  );
170 
201 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestExtract_Async)
202 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestExtract_Async(
203  uint8_t * pOutput,
204  size_t outputLength
205  );
206 
227 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesEcb_Async)
228 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesEcb_Async(
229  uint8_t const * pDataKey,
230  uint8_t * pOutput
231  );
232 
255 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesCtr_Async)
256 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesCtr_Async(
257  uint8_t const * pData,
258  size_t dataLength,
259  uint8_t const * pIvKey,
260  uint8_t * pOutput
261  );
262 
292 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigLoad_Async)
293 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigLoad_Async(
294  uint8_t const * pInput
295  );
296 
297 
327 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async)
328 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async(
329  uint8_t const * pInput,
330  uint8_t * pOutput
331  );
332 
333 #ifdef MCUXCL_FEATURE_ELS_PRND_INIT
334 
349 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_Init_Async)
350 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_Init_Async(void);
351 #endif /* MCUXCL_FEATURE_ELS_PRND_INIT */
352 
370 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandomWord)
371 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandomWord(
372  uint32_t * pWord
373  );
374 
393 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandom)
394 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandom(
395  uint8_t * pOutput,
396  size_t outputLength
397  );
398 
399 #ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING
400 
418 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed)
419 MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed(const uint8_t *pDtrngConfig);
420 #endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */
421  /* mcuxClEls_Rng_Functions */
425 
426  /* mcuxClEls_Rng */
430 
431 #ifdef __cplusplus
432 } /* extern "C" */
433 #endif
434 
435 #endif /* MCUXCLELS_RNG_H_ */
mcuxClEls_Rng_DrbgTestAesCtr_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesCtr_Async(uint8_t const *pData, size_t dataLength, uint8_t const *pIvKey, uint8_t *pOutput)
Encrypts data using the AES-CTR engine of the DRBG.
+
mcuxClEls_Prng_GetRandom
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandom(uint8_t *pOutput, size_t outputLength)
Writes random data from the ELS PRNG to the given buffer.
+
mcuxClEls_Prng_GetRandomWord
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandomWord(uint32_t *pWord)
Returns one random word from the ELS PRNG.
+
mcuxClEls_Rng_DrbgTestExtract_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestExtract_Async(uint8_t *pOutput, size_t outputLength)
Performs a DRBG extraction.
+
MCUXCLELS_API
#define MCUXCLELS_API
Marks a function as a public API function of the mcuxClEls component.
Definition: mcuxClEls_Common.h:47
+
mcuxClEls_Rng_DrbgRequest_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgRequest_Async(uint8_t *pOutput, size_t outputLength)
Writes random data from the ELS DRBG to the given buffer.
+
mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async(uint8_t const *pInput, uint8_t *pOutput)
Performs characterization of the ELS DTRNG.
+
mcuxClEls_Rng_Dtrng_ConfigLoad_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigLoad_Async(uint8_t const *pInput)
Loads a configuration of the ELS DTRNG.
+
mcuxClEls_Common.h
ELS header for common functionality.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClEls_Rng_DrbgTestAesEcb_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesEcb_Async(uint8_t const *pDataKey, uint8_t *pOutput)
Encrypts data using the AES-ECB engine of the DRBG.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
+
mcuxClEls_Rng_DrbgTestInstantiate_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestInstantiate_Async(uint8_t const *pEntropy)
Instantiates the DRBG in test mode.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00332.html b/components/els_pkc/doc/mcxn/html/a00332.html new file mode 100644 index 000000000..6daba65f4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00332.html @@ -0,0 +1,454 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs
+
+
mcuxClEls_Types.h File Reference
+
+
+ +

ELS type header. +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClEls_mapping.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

union  mcuxClEls_KeyProp_t
 Type for ELS key store key properties. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEY_SLOTS
 Number of key slots in the ELS key store. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128
 128-bit key More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256
 256-bit key More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE
 Key is active (loaded) More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT
 First part of multi-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
 General purpose key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT
 Retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT
 Hardware output key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_CMAC
 CMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KSK
 Key signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_RTF
 RTF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_CKDF
 CKDF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HKDF
 HKDF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN
 ECC signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ECDH
 ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_AES
 AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HMAC
 HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KWK
 Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KUOK
 Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
 TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
 TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC
 Can provide key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT
 A key to be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK
 The key can be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_DUK
 Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED
 Caller must be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED
 Caller does not have to be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_SECURE
 Caller must be in secure mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE
 Caller does not have to be in secure mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128
 This value of mcuxClEls_KeyProp_t.ksize indicates a 128 bit key. More...
 
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
 This value of mcuxClEls_KeyProp_t.ksize indicates a 256 bit key. More...
 
#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
 This value of mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key. More...
 
#define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE
 This value of mcuxClEls_KeyProp_t.kactv indicates that the slot does not contain active key. More...
 
#define MCUXCLELS_KEYPROPERTY_BASE_SLOT
 This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECOND_SLOT
 This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the second slot of a 2-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a retention key slot or a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a neither retention key slot nor hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is a retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is not a retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is not a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_CMAC_TRUE
 This value of mcuxClEls_KeyProp_t.ucmac indicates that the key can be used for CMAC. More...
 
#define MCUXCLELS_KEYPROPERTY_CMAC_FALSE
 This value of mcuxClEls_KeyProp_t.ucmac indicates that the key cannot be used for CMAC. More...
 
#define MCUXCLELS_KEYPROPERTY_KSK_TRUE
 This value of mcuxClEls_KeyProp_t.uksk indicates that the key can be used for key signing. More...
 
#define MCUXCLELS_KEYPROPERTY_KSK_FALSE
 This value of mcuxClEls_KeyProp_t.uksk indicates that the key cannot be used for key signing. More...
 
#define MCUXCLELS_KEYPROPERTY_RTF_TRUE
 This value of mcuxClEls_KeyProp_t.urtf indicates that the key can be used for RTF signing. More...
 
#define MCUXCLELS_KEYPROPERTY_RTF_FALSE
 This value of mcuxClEls_KeyProp_t.urtf indicates that the key cannot be used for RTF signing. More...
 
#define MCUXCLELS_KEYPROPERTY_CKDF_TRUE
 This value of mcuxClEls_KeyProp_t.uckdf indicates that the key can be used for CKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_CKDF_FALSE
 This value of mcuxClEls_KeyProp_t.uckdf indicates that the key cannot be used for CKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_HKDF_TRUE
 This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key can be used for HKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_HKDF_FALSE
 This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key cannot be used for HKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_TRUE
 This value of mcuxClEls_KeyProp_t.uecsg indicates that the key can be used for ECC signing. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_FALSE
 This value of mcuxClEls_KeyProp_t.uecsg indicates that the key cannot be used for ECC signing. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
 This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is a ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
 This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is not an ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_AES_TRUE
 This value of mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_AES_FALSE
 This value of mcuxClEls_KeyProp_t.uaes indicates that the key is not an AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_HMAC_TRUE
 This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is an HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_HMAC_FALSE
 This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is not an HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_KWK_TRUE
 This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KWK_FALSE
 This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is not a Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KUOK_TRUE
 This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is a Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KUOK_FALSE
 This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is not a Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
 This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is a TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
 This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is not a TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
 This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is a TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
 This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is not a TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
 This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key can be used as key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
 This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key cannot be used as key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE
 This value of mcuxClEls_KeyProp_t.uhwo indicates that the key can be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE
 This value of mcuxClEls_KeyProp_t.uhwo indicates that the key cannot be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_WRAP_TRUE
 This value of mcuxClEls_KeyProp_t.wrpok indicates that the key can be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_WRAP_FALSE
 This value of mcuxClEls_KeyProp_t.wrpok indicates that the key cannot be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
 This value of mcuxClEls_KeyProp_t.duk indicates that the key is a Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
 This value of mcuxClEls_KeyProp_t.duk indicates that the key is not a Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
 This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE
 This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller does not need to be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE
 This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECURE_FALSE
 This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller does not need to be in secure mode to use the key. More...
 
#define MCUXCLELS_STATUS_OK
 No error occurred. More...
 
#define MCUXCLELS_STATUS_OK_WAIT
 An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete it. More...
 
#define MCUXCLELS_STATUS_HW_FAULT
 ELS hardware detected a fault. More...
 
#define MCUXCLELS_STATUS_HW_ALGORITHM
 An algorithm failed in hardware. More...
 
#define MCUXCLELS_STATUS_HW_OPERATIONAL
 ELS was operated incorrectly. More...
 
#define MCUXCLELS_STATUS_HW_BUS
 A bus access failed. More...
 
#define MCUXCLELS_STATUS_HW_INTEGRITY
 An integrity check failed in hardware. More...
 
#define MCUXCLELS_STATUS_HW_PRNG
 Read access to PRNG output while PRNG is not in ready state. More...
 
#define MCUXCLELS_STATUS_HW_DTRNG
 Unable to get entropy from dTRNG with current configuration. More...
 
#define MCUXCLELS_STATUS_SW_FAULT
 Software detected a fault. More...
 
#define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT
 an ELS command was started while the ELS was still busy, or a SHA-Direct command was started while the SHA kernel was still busy More...
 
#define MCUXCLELS_STATUS_SW_INVALID_PARAM
 Incorrect parameters were supplied. More...
 
#define MCUXCLELS_STATUS_SW_INVALID_STATE
 This can happen when ELS is in a wrong state for the requested ELS command. More...
 
#define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED
 A software counter expired while waiting for an ELS operation to finish. More...
 
#define MCUXCLELS_STATUS_SW_COMPARISON_FAILED
 A comparison between an ELS flag and its expected value failed. More...
 
#define MCUXCLELS_STATUS_IS_HW_ERROR(x)
 Checks whether an error code is a hardware error. Indicates that an error was reported by ELS hardware. More...
 
#define MCUXCLELS_STATUS_IS_SW_ERROR(x)
 Checks whether an error code is a software error. Indicates that the error was detected by the driver software and not by ELS hardware. More...
 
#define utlpsms
 Deprecated name for mcuxClEls_KeyProp_t.utlspms. More...
 
+ + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClEls_Status_t
 Type for ELS driver status codes. More...
 
typedef mcuxClEls_Status_t mcuxClEls_Status_Protected_t
 Deprecated type for ELS driver protected status codes. More...
 
typedef uint32_t mcuxClEls_KeyIndex_t
 Type for ELS keystore indices. More...
 
typedef mcuxClEls_Status_t(* mcuxClEls_TransferToRegisterFunction_t) (uint32_t volatile *pDestRegister, uint8_t const *pSource, size_t sourceLength, void *pCallerData)
 Function type for transfer of data to a memory-mapped register. More...
 
+

Detailed Description

+

ELS type header.

+

This header defines types that are used by other mcuxClEls headers.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00332.js b/components/els_pkc/doc/mcxn/html/a00332.js new file mode 100644 index 000000000..eca194d9f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00332.js @@ -0,0 +1,104 @@ +var a00332 = +[ + [ "MCUXCLELS_KEY_SLOTS", "a00764.html#ga68a354e8f8ccdcf5ea6b44458894e11c", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128", "a00765.html#ga20705a3a067d321f364a1c5b278a32d8", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256", "a00765.html#gaa605da5172899ce79cb55909ed4a3464", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE", "a00765.html#ga38ccbdbdaade2b7880d64982044e8035", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT", "a00765.html#gabbdb03610e94b456d47ad12d7a12140e", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT", "a00765.html#gad18d55603e3e1563ea9da2edafc26315", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT", "a00765.html#gaacc968f77f54b1b66903aecb8fbb1e1c", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT", "a00765.html#ga7f07dfb893d2d9cd087f63c931f2ca29", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_CMAC", "a00765.html#gae181bcf54a9e911574ac80f47e9478b0", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KSK", "a00765.html#ga6dc65c24d84015a37cc697a1f8ebfa94", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_RTF", "a00765.html#ga0a33beb3623a2c3d1bdd1d3194419b51", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_CKDF", "a00765.html#ga005bacc1cb8c881365bdf22cc3264af5", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HKDF", "a00765.html#gaa4e7e020109bb4a83c8f05f17fb860bb", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ECSGN", "a00765.html#ga3a77d34b3cdb470dbe9cbac0c6383488", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ECDH", "a00765.html#gaa50202ab187ade63e84c8b589a08ce58", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_AES", "a00765.html#gac45ebca89b1aa9788366cb5d1bbc92f8", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HMAC", "a00765.html#ga64d0aa24d8057d5c96b8bc1a6f5d8711", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KWK", "a00765.html#ga518248d788f4fe3746c9ca910d70f38b", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KUOK", "a00765.html#ga40d6978ccb822e1dccd7701cc635ffc9", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET", "a00765.html#gadc12177ca1a434524bf41e3e646bea4c", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET", "a00765.html#gac71ffc243f1c14fea51a8cfe0a5bb7da", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KGSRC", "a00765.html#ga70889526167cbf5e75912e430372a993", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT", "a00765.html#ga7388b2da16ebf2291f6b4a682240f073", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_WRPOK", "a00765.html#gadf248e85c19983b971956e30471b5b68", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_DUK", "a00765.html#ga5333f4f5fd6978a1c4bd9e6cae7a4955", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED", "a00765.html#ga714925236ac3417792b5b51054c5f479", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED", "a00765.html#ga193c53f3465e549c04bffb48c614b976", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_SECURE", "a00765.html#ga938259096a964f99992874407cb75b5b", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE", "a00765.html#gaee9d5c2f7654dab8449372339f6eb857", null ], + [ "MCUXCLELS_KEYPROPERTY_KEY_SIZE_128", "a00766.html#ga4cacf5225b1aa96c74f05b111cfd0298", null ], + [ "MCUXCLELS_KEYPROPERTY_KEY_SIZE_256", "a00766.html#ga755a270fd53677522cafd0e56a6be66f", null ], + [ "MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE", "a00766.html#ga80e7d70c48a472dba6067d6b8e97bb68", null ], + [ "MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE", "a00766.html#gadba88640610efd722fd6cb31131476ac", null ], + [ "MCUXCLELS_KEYPROPERTY_BASE_SLOT", "a00766.html#ga8a549e38eaccd502bd48a82e95ff20f2", null ], + [ "MCUXCLELS_KEYPROPERTY_SECOND_SLOT", "a00766.html#ga2a587ef5925801237ed4289ba7124bc1", null ], + [ "MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE", "a00766.html#ga7db639faa4a274e77743882b7057c537", null ], + [ "MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE", "a00766.html#gae3b99cfb55454bdc413aace5afd71890", null ], + [ "MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE", "a00766.html#ga9f77c7afd0e967dbde5dfd67b8d41257", null ], + [ "MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE", "a00766.html#ga69b01ec32c2541c387b1bab005e4b03e", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE", "a00766.html#ga644cefc65b923481fdf6013ffad6a664", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE", "a00766.html#ga289019e9ef73c7f796ab0b69d2d5223f", null ], + [ "MCUXCLELS_KEYPROPERTY_CMAC_TRUE", "a00766.html#ga2f6b74eae56797b769e35fb9d1d5465e", null ], + [ "MCUXCLELS_KEYPROPERTY_CMAC_FALSE", "a00766.html#ga362b93220be9faf000985a3b28380ad0", null ], + [ "MCUXCLELS_KEYPROPERTY_KSK_TRUE", "a00766.html#ga00953660d09e3ed62645b167851b9cc9", null ], + [ "MCUXCLELS_KEYPROPERTY_KSK_FALSE", "a00766.html#ga432995f0ef41d5b333e9b3829122bc42", null ], + [ "MCUXCLELS_KEYPROPERTY_RTF_TRUE", "a00766.html#gad03052755431d2adfeaa30277e418f04", null ], + [ "MCUXCLELS_KEYPROPERTY_RTF_FALSE", "a00766.html#ga8a942c5fc98bc8ffdc5f009ba3bfa29c", null ], + [ "MCUXCLELS_KEYPROPERTY_CKDF_TRUE", "a00766.html#ga8d6171d58db58d9ba6e15e7f9cb0c057", null ], + [ "MCUXCLELS_KEYPROPERTY_CKDF_FALSE", "a00766.html#ga960f82984c81287e968904ffd41be70c", null ], + [ "MCUXCLELS_KEYPROPERTY_HKDF_TRUE", "a00766.html#gac0b2f4e4b25b10f1674d8baa8d38286e", null ], + [ "MCUXCLELS_KEYPROPERTY_HKDF_FALSE", "a00766.html#gaa80640a904308caeb41895739ef281d1", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_TRUE", "a00766.html#gab457f8b10780aad731269d29445a2333", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_FALSE", "a00766.html#ga3f8380fec95cb01265199fd2a9e7c5a7", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE", "a00766.html#gaec7f78155e96050db23eaf4a623ea5a7", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE", "a00766.html#gaec997cabe18f4c4188a602c39890aadf", null ], + [ "MCUXCLELS_KEYPROPERTY_AES_TRUE", "a00766.html#gae292b4575efaa152a6a2704c05e079c7", null ], + [ "MCUXCLELS_KEYPROPERTY_AES_FALSE", "a00766.html#ga9960540d8489d2022ee67e60e77858bf", null ], + [ "MCUXCLELS_KEYPROPERTY_HMAC_TRUE", "a00766.html#ga0174e78e6f43bf25603e6ac5791d6031", null ], + [ "MCUXCLELS_KEYPROPERTY_HMAC_FALSE", "a00766.html#gabaace8fb57f6d821d042639dd83024b4", null ], + [ "MCUXCLELS_KEYPROPERTY_KWK_TRUE", "a00766.html#ga8f78e035c0c348d9c95250cbb5c06bdc", null ], + [ "MCUXCLELS_KEYPROPERTY_KWK_FALSE", "a00766.html#ga456e3e1f4c7dbfedb45b81407b55619b", null ], + [ "MCUXCLELS_KEYPROPERTY_KUOK_TRUE", "a00766.html#ga116b9a68bec502c77b49b95189cdd51c", null ], + [ "MCUXCLELS_KEYPROPERTY_KUOK_FALSE", "a00766.html#gaed363ebd3822cf20b7b6eb97477e4683", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE", "a00766.html#gafb78c8a3541eb87092a513461fd77b16", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE", "a00766.html#gab55f1e3817acebe4ac54babddac0ae54", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE", "a00766.html#ga821ec254e0847c27f58345e3be802768", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE", "a00766.html#ga4723acef377d8337e76cf3a24b0e32df", null ], + [ "MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE", "a00766.html#ga65bc587af872d79766a1990b644d65ad", null ], + [ "MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE", "a00766.html#ga6bb1e8b818ab13bec2351784f459c815", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE", "a00766.html#ga0504273f3b2e50c2574b8a8d83475afb", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE", "a00766.html#gadade800ab03e3b7693f8a68005205a34", null ], + [ "MCUXCLELS_KEYPROPERTY_WRAP_TRUE", "a00766.html#gaf07168a64eb99d5788e096d735871c3f", null ], + [ "MCUXCLELS_KEYPROPERTY_WRAP_FALSE", "a00766.html#ga1b9c490f4f9556731df00636c902c76a", null ], + [ "MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE", "a00766.html#ga265cc12998ae7e8bb54e4f61ae2c21db", null ], + [ "MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE", "a00766.html#ga1ee99e7d2dcd7dd025bd9dbebfe31c2e", null ], + [ "MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE", "a00766.html#ga45d5d7ba7da1060c55a4bac5279841cc", null ], + [ "MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE", "a00766.html#gaa613ab074bf3fc6b9f90a69f505d2e28", null ], + [ "MCUXCLELS_KEYPROPERTY_SECURE_TRUE", "a00766.html#ga2088d83e8ab366a72075f52e3ca352ad", null ], + [ "MCUXCLELS_KEYPROPERTY_SECURE_FALSE", "a00766.html#gae85a65c3e6ae36cc74de69fa6a562a7a", null ], + [ "MCUXCLELS_STATUS_OK", "a00767.html#ga022996920a649ed71428ed73e53eae8a", null ], + [ "MCUXCLELS_STATUS_OK_WAIT", "a00767.html#ga0c69ecf4e48929c38549c8b430dae4b2", null ], + [ "MCUXCLELS_STATUS_HW_FAULT", "a00767.html#ga5903a9bf2687c19a6a4c89a0486f2ccb", null ], + [ "MCUXCLELS_STATUS_HW_ALGORITHM", "a00767.html#gacf60910b71f03c324d53f8b6563baf4c", null ], + [ "MCUXCLELS_STATUS_HW_OPERATIONAL", "a00767.html#ga6f70e740d4b57dc50083fd6f052ad434", null ], + [ "MCUXCLELS_STATUS_HW_BUS", "a00767.html#ga84e18c7cc39ffd66abc53f7353269a84", null ], + [ "MCUXCLELS_STATUS_HW_INTEGRITY", "a00767.html#gac58ea9f6e1103f32cd5cac0b2c45549c", null ], + [ "MCUXCLELS_STATUS_HW_PRNG", "a00767.html#ga1ba84ebe125bbe9dc402d9089bc46164", null ], + [ "MCUXCLELS_STATUS_HW_DTRNG", "a00767.html#ga1dc849dc5b6501b5f1c9e68f89f07881", null ], + [ "MCUXCLELS_STATUS_SW_FAULT", "a00767.html#gad3b3fde6156b816225f119a525c7f0b4", null ], + [ "MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT", "a00767.html#ga20ac618d5c0b386df110135322b94ed6", null ], + [ "MCUXCLELS_STATUS_SW_INVALID_PARAM", "a00767.html#ga96347d1bd07cc9ee18688f1973219878", null ], + [ "MCUXCLELS_STATUS_SW_INVALID_STATE", "a00767.html#gac167d607babe9a7f93950b581c08bdef", null ], + [ "MCUXCLELS_STATUS_SW_COUNTER_EXPIRED", "a00767.html#gaf10c1ef8b7689807ed2d163fe71c4b89", null ], + [ "MCUXCLELS_STATUS_SW_COMPARISON_FAILED", "a00767.html#gaddad780e0aef6a33d31b800ecb8673cd", null ], + [ "MCUXCLELS_STATUS_IS_HW_ERROR", "a00764.html#gae333a22199f8899e33304329a5ea3a3e", null ], + [ "MCUXCLELS_STATUS_IS_SW_ERROR", "a00764.html#ga1787a44ce530639142f3a63e5c38f1b5", null ], + [ "utlpsms", "a00768.html#ga0056d58adc14ddca2f9eee45575393a8", null ], + [ "mcuxClEls_Status_t", "a00768.html#ga734d7200290fe0eda6ef3347f52177f3", null ], + [ "mcuxClEls_Status_Protected_t", "a00768.html#ga9d1e537d1dc0c3eda9c26ba9e82e0596", null ], + [ "mcuxClEls_KeyIndex_t", "a00768.html#ga769227492b28ef0d58a94b202113cee8", null ], + [ "mcuxClEls_TransferToRegisterFunction_t", "a00768.html#gacb342d252ea80b11e90b781c5e1aa331", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00332_source.html b/components/els_pkc/doc/mcxn/html/a00332_source.html new file mode 100644 index 000000000..76f071ab5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00332_source.html @@ -0,0 +1,155 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLELS_TYPES_H_
27 #define MCUXCLELS_TYPES_H_
28 
29 #include <stdint.h>
30 #include <stddef.h>
31 #include <mcuxClConfig.h> // Exported features flags header
32 #include <mcuxCsslFlowProtection.h>
33 
34 #include <mcuxClEls_mapping.h>
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /**********************************************
41  * MACROS
42  **********************************************/
50 #define MCUXCLELS_KEY_SLOTS (20U)
51 
52 
57 #define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128 ((uint32_t) 0u<< 0u)
58 #define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256 ((uint32_t) 1u<< 0u)
59 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
60 #define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512 ((uint32_t) 3u<< 0u)
61 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
62 #define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE ((uint32_t) 1u<< 5u)
63 #define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT ((uint32_t) 1u<< 6u)
64 #define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT ((uint32_t) 1u<< 7u)
65 #define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT ((uint32_t) 1u<< 8u)
66 #define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT ((uint32_t) 1u<< 9u)
67 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
68 #define MCUXCLELS_KEYPROPERTY_VALUE_PUK ((uint32_t) 1u<<11u)
69 #define MCUXCLELS_KEYPROPERTY_VALUE_TECDH ((uint32_t) 1u<<12u)
70 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
71 #define MCUXCLELS_KEYPROPERTY_VALUE_CMAC ((uint32_t) 1u<<13u)
72 #define MCUXCLELS_KEYPROPERTY_VALUE_KSK ((uint32_t) 1u<<14u)
73 #define MCUXCLELS_KEYPROPERTY_VALUE_RTF ((uint32_t) 1u<<15u)
74 #define MCUXCLELS_KEYPROPERTY_VALUE_CKDF ((uint32_t) 1u<<16u)
75 #define MCUXCLELS_KEYPROPERTY_VALUE_HKDF ((uint32_t) 1u<<17u)
76 #define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN ((uint32_t) 1u<<18u)
77 #define MCUXCLELS_KEYPROPERTY_VALUE_ECDH ((uint32_t) 1u<<19u)
78 #define MCUXCLELS_KEYPROPERTY_VALUE_AES ((uint32_t) 1u<<20u)
79 #define MCUXCLELS_KEYPROPERTY_VALUE_HMAC ((uint32_t) 1u<<21u)
80 #define MCUXCLELS_KEYPROPERTY_VALUE_KWK ((uint32_t) 1u<<22u)
81 #define MCUXCLELS_KEYPROPERTY_VALUE_KUOK ((uint32_t) 1u<<23u)
82 #define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET ((uint32_t) 1u<<24u)
83 #define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET ((uint32_t) 1u<<25u)
84 #define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC ((uint32_t) 1u<<26u)
85 #define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT ((uint32_t) 1u<<27u)
86 #define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK ((uint32_t) 1u<<28u)
87 #define MCUXCLELS_KEYPROPERTY_VALUE_DUK ((uint32_t) 1u<<29u)
88 #define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED ((uint32_t) 1u<<30u)
89 #define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED ((uint32_t) 0u<<30u)
90 #define MCUXCLELS_KEYPROPERTY_VALUE_SECURE ((uint32_t) 0u<<31u)
91 #define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE ((uint32_t) 1u<<31u)
92 
101 #define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128 0U
102 #define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256 1U
103 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
104 #define MCUXCLELS_KEYPROPERTY_KEY_SIZE_512 3U
105 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
106 #define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE 1U
107 #define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE 0U
108 #define MCUXCLELS_KEYPROPERTY_BASE_SLOT 1U
109 #define MCUXCLELS_KEYPROPERTY_SECOND_SLOT 0U
110 #define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE 1U
111 #define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE 0U
112 #define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE 1U
113 #define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE 0U
114 #define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE 1U
115 #define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE 0U
116 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
117 #define MCUXCLELS_KEYPROPERTY_PUK_TRUE 1U
118 #define MCUXCLELS_KEYPROPERTY_PUK_FALSE 0U
119 #define MCUXCLELS_KEYPROPERTY_TECDH_TRUE 1U
120 #define MCUXCLELS_KEYPROPERTY_TECDH_FALSE 0U
121 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
122 #define MCUXCLELS_KEYPROPERTY_CMAC_TRUE 1U
123 #define MCUXCLELS_KEYPROPERTY_CMAC_FALSE 0U
124 #define MCUXCLELS_KEYPROPERTY_KSK_TRUE 1U
125 #define MCUXCLELS_KEYPROPERTY_KSK_FALSE 0U
126 #define MCUXCLELS_KEYPROPERTY_RTF_TRUE 1U
127 #define MCUXCLELS_KEYPROPERTY_RTF_FALSE 0U
128 #define MCUXCLELS_KEYPROPERTY_CKDF_TRUE 1U
129 #define MCUXCLELS_KEYPROPERTY_CKDF_FALSE 0U
130 #define MCUXCLELS_KEYPROPERTY_HKDF_TRUE 1U
131 #define MCUXCLELS_KEYPROPERTY_HKDF_FALSE 0U
132 #define MCUXCLELS_KEYPROPERTY_ECC_TRUE 1U
133 #define MCUXCLELS_KEYPROPERTY_ECC_FALSE 0U
134 #define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE 1U
135 #define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE 0U
136 #define MCUXCLELS_KEYPROPERTY_AES_TRUE 1U
137 #define MCUXCLELS_KEYPROPERTY_AES_FALSE 0U
138 #define MCUXCLELS_KEYPROPERTY_HMAC_TRUE 1U
139 #define MCUXCLELS_KEYPROPERTY_HMAC_FALSE 0U
140 #define MCUXCLELS_KEYPROPERTY_KWK_TRUE 1U
141 #define MCUXCLELS_KEYPROPERTY_KWK_FALSE 0U
142 #define MCUXCLELS_KEYPROPERTY_KUOK_TRUE 1U
143 #define MCUXCLELS_KEYPROPERTY_KUOK_FALSE 0U
144 #define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE 1U
145 #define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE 0U
146 #define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE 1U
147 #define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE 0U
148 #define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE 1U
149 #define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE 0U
150 #define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE 1U
151 #define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE 0U
152 #define MCUXCLELS_KEYPROPERTY_WRAP_TRUE 1U
153 #define MCUXCLELS_KEYPROPERTY_WRAP_FALSE 0U
154 #define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE 1U
155 #define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE 0U
156 #define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE 1U
157 #define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE 0U
158 #define MCUXCLELS_KEYPROPERTY_SECURE_TRUE 0U
159 #define MCUXCLELS_KEYPROPERTY_SECURE_FALSE 1U
160 
170 #define MCUXCLELS_STATUS_OK ((mcuxClEls_Status_t) 0x05552E03u)
171 #define MCUXCLELS_STATUS_OK_WAIT ((mcuxClEls_Status_t) 0x05552E07u)
172 #define MCUXCLELS_STATUS_HW_FAULT ((mcuxClEls_Status_t) 0x05555330u)
173 #define MCUXCLELS_STATUS_HW_ALGORITHM ((mcuxClEls_Status_t) 0x05555334u)
174 #define MCUXCLELS_STATUS_HW_OPERATIONAL ((mcuxClEls_Status_t) 0x05555338u)
175 #define MCUXCLELS_STATUS_HW_BUS ((mcuxClEls_Status_t) 0x0555533Cu)
176 #define MCUXCLELS_STATUS_HW_INTEGRITY ((mcuxClEls_Status_t) 0x05555370u)
177 #define MCUXCLELS_STATUS_HW_PRNG ((mcuxClEls_Status_t) 0x05555374u)
178 #define MCUXCLELS_STATUS_HW_DTRNG ((mcuxClEls_Status_t) 0x05555378u)
179 #define MCUXCLELS_STATUS_SW_FAULT ((mcuxClEls_Status_t) 0x0555F0F0u)
180 #define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT ((mcuxClEls_Status_t) 0x055553B0u)
181 #define MCUXCLELS_STATUS_SW_INVALID_PARAM ((mcuxClEls_Status_t) 0x055553F8u)
182 #define MCUXCLELS_STATUS_SW_INVALID_STATE ((mcuxClEls_Status_t) 0x055553B8u)
183 #define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED ((mcuxClEls_Status_t) 0x055553BCu)
184 #define MCUXCLELS_STATUS_SW_COMPARISON_FAILED ((mcuxClEls_Status_t) 0x05558930u)
185 #ifdef MCUXCL_FEATURE_ELS_LOCKING
186 #define MCUXCLELS_STATUS_SW_LOCKING_FAILED ((mcuxClEls_Status_t) 0x055553F4u)
187 #define MCUXCLELS_STATUS_SW_STATUS_LOCKED ((mcuxClEls_Status_t) 0x05552E0Bu)
188 #endif /* MCUXCL_FEATURE_ELS_LOCKING */
189 
191 #define MCUXCLELS_STATUS_IS_HW_ERROR(x) ((((mcuxClEls_Status_t) (x)) & 0x0000FF00U) == 0x0000E100U)
192 
193 #define MCUXCLELS_STATUS_IS_SW_ERROR(x) ((((mcuxClEls_Status_t) (x)) & 0x0000FF00U) == 0x0000F000U)
194 
195 
199 /**********************************************
200  * TYPEDEFS
201  **********************************************/
211 typedef uint32_t mcuxClEls_Status_t;
212 
216 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Status_Protected_t;
217 
221 typedef uint32_t mcuxClEls_KeyIndex_t;
222 
224 typedef union
225 {
226  struct
227  {
228  uint32_t value;
229  } word;
230  struct
231  {
232 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
233  uint32_t ksize :2;
234  uint32_t :3;
235 #else
236  uint32_t ksize :1;
237  uint32_t :4;
238 #endif
239  uint32_t kactv :1;
240  uint32_t kbase :1;
241  uint32_t fgp :1;
242  uint32_t frtn :1;
243  uint32_t fhwo :1;
244 #ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL
245  uint32_t :1;
246  uint32_t upuk :1;
247  uint32_t utecdh :1;
248 #else
249  uint32_t :3;
250 #endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */
251  uint32_t ucmac :1;
252  uint32_t uksk :1;
253  uint32_t urtf :1;
254  uint32_t uckdf :1;
255  uint32_t uhkdf :1;
256  uint32_t uecsg :1;
257  uint32_t uecdh :1;
258  uint32_t uaes :1;
259  uint32_t uhmac :1;
260  uint32_t ukwk :1;
261  uint32_t ukuok :1;
262  uint32_t utlspms :1;
263  uint32_t utlsms :1;
264  uint32_t ukgsrc :1;
265  uint32_t uhwo :1;
266  uint32_t wrpok :1;
267  uint32_t duk :1;
268  uint32_t upprot_priv :1;
269  uint32_t upprot_sec :1;
270  } bits;
271 } mcuxClEls_KeyProp_t;
272 
273 
274 #define utlpsms utlspms
275 
276 
289 typedef mcuxClEls_Status_t (*mcuxClEls_TransferToRegisterFunction_t)(
290  uint32_t volatile * pDestRegister,
291  uint8_t const * pSource,
292  size_t sourceLength,
293  void * pCallerData);
294 
295 #ifdef __cplusplus
296 } /* extern "C" */
297 #endif
298 
299 #endif /* MCUXCLELS_TYPES_H_ */
300 
mcuxClEls_KeyProp_t::uhkdf
uint32_t uhkdf
Usage permission for HKDF.
Definition: mcuxClEls_Types.h:255
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mcuxClEls_KeyProp_t::uckdf
uint32_t uckdf
Usage permission for CKDF.
Definition: mcuxClEls_Types.h:254
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mcuxClEls_KeyProp_t::uecsg
uint32_t uecsg
Usage permission for ECDSA signing.
Definition: mcuxClEls_Types.h:256
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mcuxClEls_KeyProp_t::fgp
uint32_t fgp
Hardware feature flag: General purpose key slot.
Definition: mcuxClEls_Types.h:241
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mcuxClEls_KeyProp_t::ucmac
uint32_t ucmac
Usage permission for CMAC.
Definition: mcuxClEls_Types.h:251
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mcuxClEls_KeyProp_t::kbase
uint32_t kbase
Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key.
Definition: mcuxClEls_Types.h:240
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mcuxClEls_KeyProp_t::uhmac
uint32_t uhmac
Usage permission for HMAC.
Definition: mcuxClEls_Types.h:259
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mcuxClEls_KeyProp_t::upprot_sec
uint32_t upprot_sec
Access restriction to TrustZone secure mode.
Definition: mcuxClEls_Types.h:269
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mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
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mcuxClEls_KeyProp_t::ukgsrc
uint32_t ukgsrc
Usage permission as input for ECC key generation.
Definition: mcuxClEls_Types.h:264
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mcuxClEls_KeyProp_t::fhwo
uint32_t fhwo
Hardware feature flag: Hardware-out key slot.
Definition: mcuxClEls_Types.h:243
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mcuxClEls_KeyProp_t::kactv
uint32_t kactv
Status flag to indicate whether the key slot contains an active key or not.
Definition: mcuxClEls_Types.h:239
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mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
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mcuxClEls_KeyProp_t::ukuok
uint32_t ukuok
Usage permission for key unwrapping, but not for key wrapping.
Definition: mcuxClEls_Types.h:261
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mcuxClEls_mapping.h
Header providing mapping for legacy function/definition names (with CSS)
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mcuxClEls_KeyProp_t::uksk
uint32_t uksk
Usage permission for key signing.
Definition: mcuxClEls_Types.h:252
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mcuxClEls_KeyProp_t::uhwo
uint32_t uhwo
Usage permission in a hardware-out key slot.
Definition: mcuxClEls_Types.h:265
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mcuxClEls_KeyProp_t::duk
uint32_t duk
Device-unique key flag.
Definition: mcuxClEls_Types.h:267
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mcuxClEls_KeyProp_t::wrpok
uint32_t wrpok
Usage permission to wrap.
Definition: mcuxClEls_Types.h:266
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mcuxClEls_KeyProp_t::utlspms
uint32_t utlspms
Usage permission as a TLS premaster secret.
Definition: mcuxClEls_Types.h:262
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mcuxClEls_KeyProp_t::ksize
uint32_t ksize
Key size.
Definition: mcuxClEls_Types.h:236
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mcuxClEls_KeyProp_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYP...
Definition: mcuxClEls_Types.h:228
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mcuxClEls_TransferToRegisterFunction_t
mcuxClEls_Status_t(* mcuxClEls_TransferToRegisterFunction_t)(uint32_t volatile *pDestRegister, uint8_t const *pSource, size_t sourceLength, void *pCallerData)
Function type for transfer of data to a memory-mapped register.
Definition: mcuxClEls_Types.h:289
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mcuxClEls_KeyProp_t::uaes
uint32_t uaes
Usage permission for AES.
Definition: mcuxClEls_Types.h:258
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mcuxClEls_KeyProp_t::ukwk
uint32_t ukwk
Usage permission for key wrapping.
Definition: mcuxClEls_Types.h:260
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mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
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mcuxClEls_KeyProp_t::urtf
uint32_t urtf
Usage permission for RTF signing.
Definition: mcuxClEls_Types.h:253
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mcuxClEls_Status_Protected_t
mcuxClEls_Status_t mcuxClEls_Status_Protected_t
Deprecated type for ELS driver protected status codes.
Definition: mcuxClEls_Types.h:216
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mcuxClEls_KeyProp_t::frtn
uint32_t frtn
Hardware feature flag: Retention key slot.
Definition: mcuxClEls_Types.h:242
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MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
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mcuxClEls_Status_t
uint32_t mcuxClEls_Status_t
Type for ELS driver status codes.
Definition: mcuxClEls_Types.h:211
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mcuxClEls_KeyProp_t::uecdh
uint32_t uecdh
Usage permission for Elliptic Curve Diffie-Hellman.
Definition: mcuxClEls_Types.h:257
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mcuxClEls_KeyProp_t::utlsms
uint32_t utlsms
Usage permission as a TLS master secret.
Definition: mcuxClEls_Types.h:263
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mcuxClEls_KeyProp_t::upprot_priv
uint32_t upprot_priv
Access restriction to privileged mode.
Definition: mcuxClEls_Types.h:268
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00335_source.html b/components/els_pkc/doc/mcxn/html/a00335_source.html new file mode 100644 index 000000000..e6ff4573a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00335_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClExample_ELS_Helper.h Source File + + + + + + + + + + + + + + + + +
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MCUX Crypto Library Normal Secure
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mcuxClExample_ELS_Helper.h
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_ELS_HELPER_H_
15 #define MCUXCLEXAMPLE_ELS_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClEls.h>
20 #include <mcuxCsslFlowProtection.h>
21 #include <mcuxClCore_FunctionIdentifiers.h>
22 
28 static inline bool mcuxClExample_Els_Init(mcuxClEls_ResetOption_t options)
29 {
30  /* Enable ELS */
31  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Enable_Async()); // Enable the ELS.
32  // mcuxClEls_Enable_Async is a flow-protected function: Check the protection token and the return value
33  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Enable_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
34  {
35  return false;
36  }
37  MCUX_CSSL_FP_FUNCTION_CALL_END();
38 
39  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete.
40  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
41  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
42  {
43  return false;
44  }
45  MCUX_CSSL_FP_FUNCTION_CALL_END();
46 
47  /* Reset ELS */
48  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Reset_Async(options));
49  // mcuxClEls_Reset_Async is a flow-protected function: Check the protection token and the return value
50  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Reset_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
51  {
52  return false;
53  }
54  MCUX_CSSL_FP_FUNCTION_CALL_END();
55 
56  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Reset_Async operation to complete.
57  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
58  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
59  {
60  return false;
61  }
62  MCUX_CSSL_FP_FUNCTION_CALL_END();
63  return true;
64 }
65 
69 static inline bool mcuxClExample_Els_Disable(void)
70 {
71  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Disable()); // Disable the ELS.
72  // mcuxClEls_Disable is a flow-protected function: Check the protection token and the return value
73  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Disable) != token) || (MCUXCLELS_STATUS_OK != result))
74  {
75  return false;
76  }
77  MCUX_CSSL_FP_FUNCTION_CALL_END();
78  return true;
79 }
80 
81 #endif /* MCUXCLEXAMPLE_ELS_HELPER_H_ */
mcuxClEls.h
Top-level include file for the ELS driver.
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mcuxClEls_Disable
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Disable(void)
Disable the ELS.
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MCUX_CSSL_FP_FUNCTION_CALLED
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
Expectation of a called function.
Definition: mcuxCsslFlowProtection.h:730
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mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
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mcuxClEls_WaitForOperation
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation(mcuxClEls_ErrorHandling_t errorHandling)
Wait for an ELS operation and optionally clear the error status.
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MCUXCLELS_STATUS_OK
#define MCUXCLELS_STATUS_OK
No error occurred.
Definition: mcuxClEls_Types.h:170
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mcuxClEls_Enable_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Enable_Async(void)
Enables the ELS.
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MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
Call a flow protected function and check the protection token.
Definition: mcuxCsslFlowProtection.h:576
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mcuxClEls_ResetOption_t
uint32_t mcuxClEls_ResetOption_t
Type to handle ELS reset options.
Definition: mcuxClEls_Common.h:292
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mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
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MCUXCLELS_STATUS_OK_WAIT
#define MCUXCLELS_STATUS_OK_WAIT
An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete i...
Definition: mcuxClEls_Types.h:171
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MCUXCLELS_ERROR_FLAGS_CLEAR
#define MCUXCLELS_ERROR_FLAGS_CLEAR
Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags.
Definition: mcuxClEls_Common.h:137
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mcuxClEls_Reset_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async(mcuxClEls_ResetOption_t options)
Perform a synchronous reset of the ELS.
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MCUX_CSSL_FP_FUNCTION_CALL_END
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
Definition: mcuxCsslFlowProtection.h:611
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mcuxClExample_ELS_Key_Helper.h
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_ELS_KEY_HELPER_H_
15 #define MCUXCLEXAMPLE_ELS_KEY_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClEls.h>
20 #include <mcuxClExample_RFC3394_Helper.h>
21 #include <mcuxCsslFlowProtection.h>
22 #include <mcuxClCore_FunctionIdentifiers.h>
23 
28 static inline bool mcuxClExample_Els_KeyDelete(mcuxClEls_KeyIndex_t keyIdx)
29 {
30  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyDelete_Async(keyIdx));
31  // mcuxClEls_KeyDelete_Async is a flow-protected function: Check the protection token and the return value
32  if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
33  {
34  return false; // Expect that no error occurred, meaning that the mcuxClEls_KeyDelete_Async operation was started.
35  }
36  MCUX_CSSL_FP_FUNCTION_CALL_END();
37 
38  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_KeyDelete_Async operation to complete.
39  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
40  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
41  {
42  return false;
43  }
44  MCUX_CSSL_FP_FUNCTION_CALL_END();
45  return true;
46 }
47 
51 static inline bool mcuxClExample_Els_KeyDeleteAll(void)
52 {
53  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Reset_Async(0U));
54  // mcuxClEls_Reset_Async is a flow-protected function: Check the protection token and the return value
55  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Reset_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
56  {
57  return false;
58  }
59  MCUX_CSSL_FP_FUNCTION_CALL_END();
60 
61  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Reset_Async operation to complete.
62  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
63  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
64  {
65  return false;
66  }
67  MCUX_CSSL_FP_FUNCTION_CALL_END();
68  return true;
69 }
70 
71 
72 /*
73  * Check only if the mcuxClEls_KeyDelete_Async is defined "because mcuxClEls_KeyProvision_Async will be always defined"
74  * via CL library or via the TEST OS
75  * Function that loads a known key into the ELS key store
76  * [in] helperKeyIdx: The index of the helper key
77  * [in] targetKeyIdx: The key index at which the target key shall be loaded
78  * [in] targetKeyProperties: The target properties of the key
79  * [in] pKey: Pointer to the key to be loaded
80 */
81 #define ELS_RFC_PADDING_LENGTH 16U
82 
83 static bool mcuxClExample_load_els_key(
84  mcuxClEls_KeyIndex_t helperKeyIdx,
85  mcuxClEls_KeyIndex_t targetKeyIdx,
86  mcuxClEls_KeyProp_t properties,
87  const uint8_t* pKey
88 )
89 {
90  size_t key_size = ((MCUXCLELS_KEYPROPERTY_KEY_SIZE_256 == properties.bits.ksize) ? MCUXCLELS_CIPHER_KEY_SIZE_AES_256 : MCUXCLELS_CIPHER_KEY_SIZE_AES_128);
91  uint8_t wrapped_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_256 + ELS_RFC_PADDING_LENGTH];
92 
96  mcuxClEls_KeyProp_t key_properties_targeted;
97  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetKeyProperties(targetKeyIdx, &key_properties_targeted));
98  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties) != token) || (MCUXCLELS_STATUS_OK != result))
99  {
100  return false;
101  }
102  MCUX_CSSL_FP_FUNCTION_CALL_END();
103  if (MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE == key_properties_targeted.bits.kactv)
104  {
105  return true;
106  }
107 
111  mcuxClEls_KeyProp_t AesHelperKeyProp = {0};
112  AesHelperKeyProp.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_256;
113  AesHelperKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE;
114  AesHelperKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE;
115  AesHelperKeyProp.bits.uaes = MCUXCLELS_KEYPROPERTY_AES_TRUE;
116  AesHelperKeyProp.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
117  AesHelperKeyProp.bits.kbase = MCUXCLELS_KEYPROPERTY_BASE_SLOT;
118 
119  if(true != mcuxClExample_provision_key(helperKeyIdx, AesHelperKeyProp))
120  {
121  return false;
122  }
123 
127  mcuxClExample_rfc3394_wrap(pKey, key_size, NULL, helperKeyIdx, MCUXCLELS_CIPHER_INTERNAL_KEY, MCUXCLELS_CIPHER_KEY_SIZE_AES_256, wrapped_key, properties);
128 
132  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyDelete_Async(helperKeyIdx));
133  // mcuxClEls_KeyDelete_Async is a flow-protected function: Check the protection token and the return value
134  if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
135  {
136  return false; // Expect that no error occurred, meaning that the mcuxClEls_KeyDelete_Async operation was started.
137  }
138  MCUX_CSSL_FP_FUNCTION_CALL_END();
139 
140  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_KeyDelete_Async operation to complete.
141  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
142  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
143  {
144  return false;
145  }
146  MCUX_CSSL_FP_FUNCTION_CALL_END();
147 
151  mcuxClEls_KeyProp_t kwkHelperKeyProp = {0};
152  kwkHelperKeyProp.bits.ukwk = MCUXCLELS_KEYPROPERTY_KWK_TRUE;
153  kwkHelperKeyProp.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_256;
154  kwkHelperKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE;
155  kwkHelperKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE;
156  kwkHelperKeyProp.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
157  kwkHelperKeyProp.bits.kbase = MCUXCLELS_KEYPROPERTY_BASE_SLOT;
158 
159  if(true != mcuxClExample_provision_key(helperKeyIdx, kwkHelperKeyProp))
160  {
161  return false;
162  }
163 
164  mcuxClEls_KeyImportOption_t wrapped_key_options = {0};
165  wrapped_key_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394;
166 
167  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyImport_Async(wrapped_key_options, wrapped_key, key_size + ELS_RFC_PADDING_LENGTH, helperKeyIdx, targetKeyIdx));
168  // mcuxClEls_KeyImport_Async is a flow-protected function: Check the protection token and the return value
169  if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyImport_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
170  {
171  return false; // Expect that no error occurred, meaning that the mcuxClEls_KeyDelete_Async operation was started.
172  }
173  MCUX_CSSL_FP_FUNCTION_CALL_END();
174 
175  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_KeyDelete_Async operation to complete.
176  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
177  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
178  {
179  return false;
180  }
181  MCUX_CSSL_FP_FUNCTION_CALL_END();
182 
186  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyDelete_Async(helperKeyIdx));
187  // mcuxClEls_KeyDelete_Async is a flow-protected function: Check the protection token and the return value
188  if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
189  {
190  return false; // Expect that no error occurred, meaning that the mcuxClEls_KeyDelete_Async operation was started.
191  }
192  MCUX_CSSL_FP_FUNCTION_CALL_END();
193 
194  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_KeyDelete_Async operation to complete.
195  // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
196  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
197  {
198  return false;
199  }
200  MCUX_CSSL_FP_FUNCTION_CALL_END();
201  return true;
202 }
203 
204 #endif /* MCUXCLEXAMPLE_ELS_KEY_HELPER_H_ */
mcuxClEls.h
Top-level include file for the ELS driver.
+
mcuxClEls_KeyImport_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyImport_Async(mcuxClEls_KeyImportOption_t options, uint8_t const *pImportKey, size_t importKeyLength, mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx)
Imports a key from external storage to an internal key register.
+
MCUXCLELS_KEYPROPERTY_SECURE_TRUE
#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE
This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use ...
Definition: mcuxClEls_Types.h:158
+
MCUXCLELS_KEYPROPERTY_AES_TRUE
#define MCUXCLELS_KEYPROPERTY_AES_TRUE
This value of mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key.
Definition: mcuxClEls_Types.h:136
+
MCUXCLELS_KEYPROPERTY_KWK_TRUE
#define MCUXCLELS_KEYPROPERTY_KWK_TRUE
This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key.
Definition: mcuxClEls_Types.h:140
+
mcuxClEls_KeyProp_t::kbase
uint32_t kbase
Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key.
Definition: mcuxClEls_Types.h:240
+
mcuxClEls_KeyProp_t::upprot_sec
uint32_t upprot_sec
Access restriction to TrustZone secure mode.
Definition: mcuxClEls_Types.h:269
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
MCUX_CSSL_FP_FUNCTION_CALLED
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
Expectation of a called function.
Definition: mcuxCsslFlowProtection.h:730
+
mcuxClEls_KeyProp_t::kactv
uint32_t kactv
Status flag to indicate whether the key slot contains an active key or not.
Definition: mcuxClEls_Types.h:239
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUXCLELS_CIPHER_KEY_SIZE_AES_128
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128
Size of an AES128 key: 128 bit (16 bytes)
Definition: mcuxClEls_Cipher.h:96
+
mcuxClEls_GetKeyProperties
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetKeyProperties(mcuxClEls_KeyIndex_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp)
Exports the properties of the keys stored in the ELS internal keystore.
+
mcuxClEls_KeyDelete_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyDelete_Async(mcuxClEls_KeyIndex_t keyIdx)
Deletes a key from keystore at the given index.
+
mcuxClEls_WaitForOperation
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation(mcuxClEls_ErrorHandling_t errorHandling)
Wait for an ELS operation and optionally clear the error status.
+
MCUXCLELS_KEYIMPORT_KFMT_RFC3394
#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394
Key format RFC3394 with shares in memory.
Definition: mcuxClEls_KeyManagement.h:83
+
mcuxClEls_KeyImportOption_t::kfmt
uint32_t kfmt
Defines the key import format, one of MCUXCLELS_KEYIMPORT_KFMT_.
Definition: mcuxClEls_KeyManagement.h:147
+
MCUXCLELS_KEYPROPERTY_BASE_SLOT
#define MCUXCLELS_KEYPROPERTY_BASE_SLOT
This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key.
Definition: mcuxClEls_Types.h:108
+
MCUXCLELS_STATUS_OK
#define MCUXCLELS_STATUS_OK
No error occurred.
Definition: mcuxClEls_Types.h:170
+
mcuxClEls_KeyProp_t::ksize
uint32_t ksize
Key size.
Definition: mcuxClEls_Types.h:236
+
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
Call a flow protected function and check the protection token.
Definition: mcuxCsslFlowProtection.h:576
+
mcuxClEls_KeyProp_t::uaes
uint32_t uaes
Usage permission for AES.
Definition: mcuxClEls_Types.h:258
+
mcuxClEls_KeyProp_t::ukwk
uint32_t ukwk
Usage permission for key wrapping.
Definition: mcuxClEls_Types.h:260
+
MCUXCLELS_CIPHER_KEY_SIZE_AES_256
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256
Size of an AES192 key: 256 bit (32 bytes)
Definition: mcuxClEls_Cipher.h:98
+
mcuxClEls_KeyProp_t::bits
struct mcuxClEls_KeyProp_t::@41 bits
Access mcuxClEls_KeyProp_t bit-wise.
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClEls_KeyImportOption_t
Command option bit field for mcuxClEls_KeyImport_Async.
Definition: mcuxClEls_KeyManagement.h:136
+
MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
This value of mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key.
Definition: mcuxClEls_Types.h:106
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClEls_KeyImportOption_t::bits
struct mcuxClEls_KeyImportOption_t::@39 bits
Access mcuxClEls_KeyImportOption_t bit-wise.
+
MCUXCLELS_STATUS_OK_WAIT
#define MCUXCLELS_STATUS_OK_WAIT
An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete i...
Definition: mcuxClEls_Types.h:171
+
MCUXCLELS_CIPHER_INTERNAL_KEY
#define MCUXCLELS_CIPHER_INTERNAL_KEY
Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by ke...
Definition: mcuxClEls_Cipher.h:74
+
MCUXCLELS_ERROR_FLAGS_CLEAR
#define MCUXCLELS_ERROR_FLAGS_CLEAR
Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags.
Definition: mcuxClEls_Common.h:137
+
MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
This value of mcuxClEls_KeyProp_t.ksize indicates a 256 bit key.
Definition: mcuxClEls_Types.h:102
+
mcuxClEls_Reset_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async(mcuxClEls_ResetOption_t options)
Perform a synchronous reset of the ELS.
+
MCUX_CSSL_FP_FUNCTION_CALL_END
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
Definition: mcuxCsslFlowProtection.h:611
+
MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to...
Definition: mcuxClEls_Types.h:156
+
mcuxClEls_KeyProp_t::upprot_priv
uint32_t upprot_priv
Access restriction to privileged mode.
Definition: mcuxClEls_Types.h:268
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00341_source.html b/components/els_pkc/doc/mcxn/html/a00341_source.html new file mode 100644 index 000000000..f06ee43df --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00341_source.html @@ -0,0 +1,139 @@ + + + + + + + +MCUX CLNS: mcuxClExample_Key_Helper.h Source File + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
mcuxClExample_Key_Helper.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_KEY_HELPER_H_
15 #define MCUXCLEXAMPLE_KEY_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClCore_Buffer.h>
20 #include <mcuxClKey.h>
21 #include <mcuxClSession.h>
22 #include <mcuxCsslFlowProtection.h>
23 #include <mcuxClCore_FunctionIdentifiers.h>
24 
36 #define MCUXCLEXAMPLE_CONST_EXTERNAL_KEY 0U
37 #define MCUXCLEXAMPLE_CONST_INTERNAL_KEY 1U
38 MCUX_CSSL_FP_FUNCTION_DEF(mcuxClExample_Key_Init_And_Load)
39 static inline bool mcuxClExample_Key_Init_And_Load(mcuxClSession_Handle_t pSession,
40  mcuxClKey_Handle_t pKey,
41  mcuxClKey_Type_t type,
42  mcuxCl_Buffer_t pData,
43  uint32_t keyDataLength,
44  mcuxClEls_KeyProp_t * key_properties,
45  uint32_t * dst,
46  uint8_t key_loading_option)
47 {
48  /* Init the key. */
49  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_init(pSession,
50  pKey,
51  type,
52  pData,
53  keyDataLength));
54 
55  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != token) || (MCUXCLKEY_STATUS_OK != result))
56  {
57  return false;
58  }
59  MCUX_CSSL_FP_FUNCTION_CALL_END();
60 
61  /* Set the key properties. */
62  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_setKeyproperties(pKey,
63  key_properties));
64 
65  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_setKeyproperties) != token) || (MCUXCLKEY_STATUS_OK != result))
66  {
67  return false;
68  }
69  MCUX_CSSL_FP_FUNCTION_CALL_END();
70 
71  if(MCUXCLEXAMPLE_CONST_EXTERNAL_KEY == key_loading_option)
72  {
73  /* load key into destination memory buffer */
74  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_loadMemory(
75  /* mcuxClSession_Handle_t pSession: */ pSession,
76  /* mcuxClKey_Handle_t key: */ pKey,
77  /* uint32_t * dstData: */ dst));
78 
79  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadMemory) != token) || (MCUXCLKEY_STATUS_OK != result))
80  {
81  return false;
82  }
83  MCUX_CSSL_FP_FUNCTION_CALL_END();
84  }
85  else
86  {
87  /* load key into destination key slot of coprocessor (key_slot = '*dst') */
88  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_loadCopro(
89  /* mcuxClSession_Handle_t pSession: */ pSession,
90  /* mcuxClKey_Handle_t key: */ pKey,
91  /* uint32_t dstSlot: */ *dst));
92 
93  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadCopro) != token) || (MCUXCLKEY_STATUS_OK != result))
94  {
95  return false;
96  }
97  MCUX_CSSL_FP_FUNCTION_CALL_END();
98  }
99  return true;
100 }
101 
102 #endif /* MCUXCLEXAMPLE_KEY_HELPER_H_ */
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
MCUXCLKEY_STATUS_OK
#define MCUXCLKEY_STATUS_OK
Key operation successful.
Definition: mcuxClKey_Constants.h:39
+
mcuxClKey.h
Top-level include file for the mcuxClKey component.
+
MCUX_CSSL_FP_FUNCTION_CALLED
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
Expectation of a called function.
Definition: mcuxCsslFlowProtection.h:730
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClKey_setKeyproperties
mcuxClKey_Status_t mcuxClKey_setKeyproperties(mcuxClKey_Handle_t key, mcuxClEls_KeyProp_t *key_properties)
Set the requested key properties of the destination key.
+
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
Call a flow protected function and check the protection token.
Definition: mcuxCsslFlowProtection.h:576
+
MCUX_CSSL_FP_FUNCTION_DEF
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
Definition of a flow protected function.
Definition: mcuxCsslFlowProtection.h:159
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClKey_loadMemory
mcuxClKey_Status_t mcuxClKey_loadMemory(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t *dstData)
Load key into destination memory buffer.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClKey_loadCopro
mcuxClKey_Status_t mcuxClKey_loadCopro(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t dstSlot)
Load key into destination key slot of a coprocessor.
+
mcuxClKey_init
mcuxClKey_Status_t mcuxClKey_init(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Type_t type, mcuxCl_InputBuffer_t pKeyData, uint32_t keyDataLength)
Initializes a key handle.
+
MCUX_CSSL_FP_FUNCTION_CALL_END
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
Definition: mcuxCsslFlowProtection.h:611
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00344_source.html b/components/els_pkc/doc/mcxn/html/a00344_source.html new file mode 100644 index 000000000..e85a659ba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00344_source.html @@ -0,0 +1,153 @@ + + + + + + + +MCUX CLNS: mcuxClExample_RFC3394_Helper.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClExample_RFC3394_Helper.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_RFC3394_HELPER_H_
15 #define MCUXCLEXAMPLE_RFC3394_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClEls.h>
20 #include <mcuxCsslFlowProtection.h>
21 #include <mcuxClCore_FunctionIdentifiers.h>
22 #include <mcuxClMemory_Copy.h>
23 
28 static inline bool mcuxClExample_rfc3394_wrap(
29  const uint8_t * pInput, //< pointer to key to be wrapped
30  size_t inputLength, //< length of key to be wrapped in bytes
31  const uint8_t * pKek_in, //< pointer to key wrapping key
32  mcuxClEls_KeyIndex_t keyIdx, //< keyslot index of key wrapping key
33  uint8_t extkey, //< 0-use key stored internally at keyIdx as wrapping key, 1-use external pKek_in as wrapping key
34  size_t kekLength, //< length of key wrapping key in bytes
35  uint8_t * pOutput, //< pointer to output buffer, size has to be inputLength + 16 bytes
36  mcuxClEls_KeyProp_t properties //< properties of the key to be wrapped
37 )
38 {
39  uint32_t concat[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u };
40 
41  uint32_t input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u };
42  uint8_t pKek[MCUXCLELS_CIPHER_KEY_SIZE_AES_256] = { 0u };
43 
44  if (extkey == MCUXCLELS_CIPHER_EXTERNAL_KEY)
45  {
46  MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy (pKek,
47  pKek_in,
48  kekLength,
49  kekLength));
50 
51  if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
52  {
53  return false;
54  }
55 
56  MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
57  }
58 
59  // Intermediate state is stored in pOutput as it is large enough
60 
61  // initialize buffer
62  concat[0] = 0xA6A6A6A6u; // first half of concat is the A from the standard, initialized to RFC3394 IV
63  concat[1] = 0xA6A6A6A6u;
64  concat[2] = properties.word.value; // second half of concat is R(input)/B(output), first R consists of properties...
65  concat[3] = 0x00000000u; // ... and ELS padding (zeros)
66  concat[2] = (concat[2] << 24u) | (concat[2] >> 24u) | ((concat[2] & 0x0000ff00u) << 8u) | ((concat[2] >> 8u) & 0x0000ff00u); // swap endianness
67 
68  // initialize ELS encryption parameters
69  mcuxClEls_CipherOption_t cipher_options;
70  cipher_options.word.value = 0;
71  cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB;
72  cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT;
73  cipher_options.bits.extkey = extkey;
74 
75  // input has to be multiple of 64 bits
76  if (inputLength % sizeof(uint64_t) != 0u)
77  {
78  return false;
79  }
80 
81  uint32_t *pSource = (uint32_t*) pInput;
82  uint32_t *pDest = (uint32_t*) pOutput;
83  uint32_t std_n = inputLength/sizeof(uint64_t) + 1; // n value from standard
84  for(size_t jdx = 0u; jdx < 6u; jdx++)
85  {
86  for(size_t idx = 0u; idx < std_n; idx++)
87  {
88  input[0]=concat[0];
89  input[1]=concat[1];
90  input[2]=concat[2];
91  input[3]=concat[3];
92 
93  // Encrypt concatenated A and chunk to be processed
94  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async(
95  cipher_options,
96  keyIdx,
97  pKek,
98  kekLength,
99  (uint8_t*) input,
100  MCUXCLELS_CIPHER_BLOCK_SIZE_AES,
101  NULL,
102  (uint8_t*) concat));
103  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
104  {
105  return false;
106  }
107  MCUX_CSSL_FP_FUNCTION_CALL_END();
108 
109  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR));
110  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
111  {
112  return false;
113  }
114  MCUX_CSSL_FP_FUNCTION_CALL_END();
115 
116  // Write out processed key chunk
117  pDest[2u*idx + 2u] = concat[2u];
118  pDest[2u*idx + 3u] = concat[3u];
119 
120  if( idx == std_n - 1u)
121  {
122  // Load next key chunk
123  concat[2u] = pDest[2u];
124  concat[3u] = pDest[3u];
125  pSource = pDest + 4;
126  }
127  else
128  {
129  // Load next key chunk
130  concat[2u] = pSource[2u*idx + 0u];
131  concat[3u] = pSource[2u*idx + 1u];
132  }
133 
134  // XOR round constant into A
135  uint32_t gdx = std_n * jdx + (idx+1); // all values should fit into a uint32_t
136  gdx = (gdx << 24u) | (gdx >> 24u) | ((gdx & 0x0000ff00u) << 8u) | ((gdx >> 8u) & 0x0000ff00u); // swap endianness
137  concat[1u] ^= gdx;
138  }
139  }
140  // Write out processed key chunk
141  pDest[0u] = concat[0u];
142  pDest[1u] = concat[1u];
143 
144  return true;
145 }
146 
151 static inline bool mcuxClExample_rfc3394_unwrap(
152  const uint8_t * pInput, //< pointer to rfc3394 blob to be wrapped
153  size_t inputLength, //< length of key the rfc3394 blob in bytes
154  const uint8_t * pKek_in, //< pointer to key wrapping key
155  mcuxClEls_KeyIndex_t keyIdx, //< keyslot index of key wrapping key
156  uint8_t extkey, //< 0-use key stored internally at keyIdx as wrapping key, 1-use external pKek_in as wrapping key
157  size_t kekLength, //< length of key wrapping key in bytes
158  uint8_t * pOutput //< pointer to output buffer, size has to inputLength - 8 bytes, contents will be properties|zeros|key
159 )
160 {
161  uint32_t concat[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u };
162 
163  uint32_t input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u };
164  uint8_t pKek[MCUXCLELS_CIPHER_KEY_SIZE_AES_256] = { 0u };
165 
166  if (extkey == MCUXCLELS_CIPHER_EXTERNAL_KEY)
167  {
168  MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy (pKek,
169  pKek_in,
170  kekLength,
171  kekLength));
172 
173  if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
174  {
175  return false;
176  }
177 
178  MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
179  }
180 
181  // initialize buffer
182  concat[0] = ((uint32_t*) pInput)[0]; // first half of concat is the A from the standard, to first chunk of input
183  concat[1] = ((uint32_t*) pInput)[1];
184 
185  // initialize ELS encryption parameters
186  mcuxClEls_CipherOption_t cipher_options;
187  cipher_options.word.value = 0;
188  cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB;
189  cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_DECRYPT;
190  cipher_options.bits.extkey = extkey;
191 
192  // input has to be multiple of 64 bits
193  if (inputLength % sizeof(uint64_t) != 0u)
194  {
195  return false;
196  }
197 
198 
199  uint32_t std_n = inputLength/sizeof(uint64_t) - 1; // n value from standard
200  uint32_t *pSource = ((uint32_t*) pInput ) + 2u; // skip first 64 bits
201  uint32_t *pDest = ((uint32_t*) pOutput) + 0u;
202  for(size_t jdx = 6u; jdx > 0u; jdx--)
203  {
204  for(size_t idx = std_n; idx > 0u; idx--)
205  {
206  // Load next key chunk
207  concat[2u] = pSource[2u*(idx-1) + 0u];
208  concat[3u] = pSource[2u*(idx-1) + 1u];
209 
210  // XOR round constant into A
211  uint32_t gdx = std_n * (jdx-1u) + idx; // all values should fit into a uint32_t
212  gdx = (gdx << 24u) | (gdx >> 24u) | ((gdx & 0x0000ff00u) << 8u) | ((gdx >> 8u) & 0x0000ff00u); // swap endianness
213  concat[1u] ^= gdx;
214 
215  input[0]=concat[0];
216  input[1]=concat[1];
217  input[2]=concat[2];
218  input[3]=concat[3];
219 
220  // Decrypt concatenated A and chunk to be processed
221  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async(
222  cipher_options,
223  keyIdx,
224  pKek,
225  kekLength,
226  (uint8_t*) input,
227  MCUXCLELS_CIPHER_BLOCK_SIZE_AES,
228  NULL,
229  (uint8_t*) concat));
230  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
231  {
232  return false;
233  }
234  MCUX_CSSL_FP_FUNCTION_CALL_END();
235 
236  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR));
237  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
238  {
239  return false;
240  }
241  MCUX_CSSL_FP_FUNCTION_CALL_END();
242 
243  // Write out processed key chunk
244  pDest[2u*(idx-1) + 0u] = concat[2u];
245  pDest[2u*(idx-1) + 1u] = concat[3u];
246  }
247  pSource = pDest;
248  }
249  pDest[0] = (pDest[0] << 24u) | (pDest[0] >> 24u) | ((pDest[0] & 0x0000ff00u) << 8u) | ((pDest[0] >> 8u) & 0x0000ff00u); // swap endianness
250  // Check padding
251  if((concat[0u] != 0xA6A6A6A6u) || (concat[1u] != 0xA6A6A6A6u))
252  {
253  return false;
254  }
255  return true;
256 }
257 
258 #endif /* MCUXCLEXAMPLE_RFC3394_HELPER_H_ */
mcuxClEls_CipherOption_t::cphmde
uint32_t cphmde
Define cipher mode.
Definition: mcuxClEls_Cipher.h:130
+
mcuxClEls_CipherOption_t::extkey
uint32_t extkey
Define whether an external key from memory or ELS internal key should be used.
Definition: mcuxClEls_Cipher.h:138
+
mcuxClEls.h
Top-level include file for the ELS driver.
+
mcuxClEls_Cipher_Async
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cipher_Async(mcuxClEls_CipherOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pIV, uint8_t *pOutput)
Performs AES encryption/decryption.
+
MCUXCLELS_CIPHER_EXTERNAL_KEY
#define MCUXCLELS_CIPHER_EXTERNAL_KEY
Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by pKe...
Definition: mcuxClEls_Cipher.h:73
+
mcuxClEls_KeyIndex_t
uint32_t mcuxClEls_KeyIndex_t
Type for ELS keystore indices.
Definition: mcuxClEls_Types.h:221
+
MCUXCLELS_CIPHER_DECRYPT
#define MCUXCLELS_CIPHER_DECRYPT
Set this option at mcuxClEls_CipherOption_t.dcrpt to perform a decryption.
Definition: mcuxClEls_Cipher.h:63
+
mcuxClEls_CipherOption_t::word
struct mcuxClEls_CipherOption_t::@2 word
Access mcuxClEls_CipherOption_t word-wise.
+
MCUX_CSSL_FP_FUNCTION_CALLED
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
Expectation of a called function.
Definition: mcuxCsslFlowProtection.h:730
+
mcuxClMemory_copy
void mcuxClMemory_copy(uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
Copies a memory buffer to another location.
+
mcuxClEls_CipherOption_t::value
uint32_t value
Accesses the bit field as a full word.
Definition: mcuxClEls_Cipher.h:124
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mo...
Definition: mcuxClEls_Cipher.h:76
+
mcuxClMemory_Copy.h
Memory header for copy functions.
+
mcuxClEls_WaitForOperation
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation(mcuxClEls_ErrorHandling_t errorHandling)
Wait for an ELS operation and optionally clear the error status.
+
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...)
End a void function call section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN.
Definition: mcuxCsslFlowProtection.h:678
+
mcuxClEls_CipherOption_t
Command option bit field for mcuxClEls_Cipher_Async.
Definition: mcuxClEls_Cipher.h:120
+
MCUXCLELS_STATUS_OK
#define MCUXCLELS_STATUS_OK
No error occurred.
Definition: mcuxClEls_Types.h:170
+
MCUXCLELS_CIPHER_ENCRYPT
#define MCUXCLELS_CIPHER_ENCRYPT
Set this option at mcuxClEls_CipherOption_t.dcrpt to perform an encryption.
Definition: mcuxClEls_Cipher.h:62
+
mcuxClEls_KeyProp_t::value
uint32_t value
Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYP...
Definition: mcuxClEls_Types.h:228
+
mcuxClEls_CipherOption_t::dcrpt
uint32_t dcrpt
Define operation mode.
Definition: mcuxClEls_Cipher.h:129
+
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
Call a flow protected function and check the protection token.
Definition: mcuxCsslFlowProtection.h:576
+
MCUXCLELS_CIPHER_KEY_SIZE_AES_256
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256
Size of an AES192 key: 256 bit (32 bytes)
Definition: mcuxClEls_Cipher.h:98
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...)
Call a flow protected void function and check the protection token.
Definition: mcuxCsslFlowProtection.h:647
+
mcuxClEls_KeyProp_t::word
struct mcuxClEls_KeyProp_t::@40 word
Access mcuxClEls_KeyProp_t word-wise.
+
MCUXCLELS_STATUS_OK_WAIT
#define MCUXCLELS_STATUS_OK_WAIT
An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete i...
Definition: mcuxClEls_Types.h:171
+
MCUXCLELS_ERROR_FLAGS_CLEAR
#define MCUXCLELS_ERROR_FLAGS_CLEAR
Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags.
Definition: mcuxClEls_Common.h:137
+
MCUXCLELS_CIPHER_BLOCK_SIZE_AES
#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES
Definition: mcuxClEls_Cipher.h:87
+
mcuxClEls_CipherOption_t::bits
struct mcuxClEls_CipherOption_t::@3 bits
Access mcuxClEls_CipherOption_t bit-wise.
+
MCUX_CSSL_FP_FUNCTION_CALL_END
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
Definition: mcuxCsslFlowProtection.h:611
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00347_source.html b/components/els_pkc/doc/mcxn/html/a00347_source.html new file mode 100644 index 000000000..ec5304596 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00347_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClExample_RNG_Helper.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClExample_RNG_Helper.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_RNG_HELPER_H_
15 #define MCUXCLEXAMPLE_RNG_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClRandom.h>
20 #include <mcuxClRandomModes.h>
21 #include <mcuxCsslFlowProtection.h>
22 #include <mcuxClCore_FunctionIdentifiers.h>
23 
24 // always allocate a minimum size buffer to avoid issues
25 // The size is given in bytes and allocated in words
26 #define MCUXCLEXAMPLE_ALLOCATE_RNG_CTXT(rngCtxLength) (rngCtxLength?((rngCtxLength + sizeof(uint32_t) - 1u) / sizeof(uint32_t)):1u)
27 
28 
36 #define MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(pSession, rngCtxLength, mode) \
37  uint32_t context[MCUXCLEXAMPLE_ALLOCATE_RNG_CTXT(rngCtxLength)] = {0}; \
38  mcuxClRandom_Context_t pRng_ctx = (mcuxClRandom_Context_t)context; \
39  \
40  /* Initialize the RNG context */ \
41  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomInit_result, randomInit_token, mcuxClRandom_init(pSession, \
42  pRng_ctx, \
43  mode)); \
44  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != randomInit_token) || (MCUXCLRANDOM_STATUS_OK != randomInit_result)) \
45  { \
46  return MCUXCLEXAMPLE_STATUS_ERROR; \
47  } \
48  MCUX_CSSL_FP_FUNCTION_CALL_END(); \
49  /* Initialize the PRNG */ \
50  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(pSession)); \
51  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) \
52  { \
53  return MCUXCLEXAMPLE_STATUS_ERROR; \
54  } \
55  MCUX_CSSL_FP_FUNCTION_CALL_END();
56 
57 #define MCUXCLEXAMPLE_INITIALIZE_PRNG(session) \
58  /* Initialize the PRNG */ \
59  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); \
60  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) \
61  { \
62  return MCUXCLEXAMPLE_STATUS_ERROR; \
63  } \
64  MCUX_CSSL_FP_FUNCTION_CALL_END();
65 
66 #endif /* MCUXCLEXAMPLE_RNG_HELPER_H_ */
mcuxClRandomModes.h
Top level header of mcuxClRandomModes component.
+
mcuxClRandom.h
Top level header of mcuxClRandom component.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00350_source.html b/components/els_pkc/doc/mcxn/html/a00350_source.html new file mode 100644 index 000000000..0a96f306e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00350_source.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClExample_Session_Helper.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClExample_Session_Helper.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLEXAMPLE_SESSION_HELPER_H_
15 #define MCUXCLEXAMPLE_SESSION_HELPER_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxClSession.h>
20 #include <mcuxCsslFlowProtection.h>
21 #include <mcuxClCore_FunctionIdentifiers.h>
22 #include <platform_specific_headers.h>
23 
31 /* TODO: CLNS-5886 [DEV][Session][Example] enable size checking when allocating buffers and update example macros */
32 #if 0
33 #define MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength) ((cpuWaLength?cpuWaLength:(sizeof(uint32_t))) / (sizeof(uint32_t))) // always allocate a minimum size buffer to avoid issues
34 #define MCUXCLEXAMPLE_ALLOCATE_PKCWA(pkcWaLength) ((pkcWaLength?pkcWaLength:(sizeof(uint32_t))) / (sizeof(uint32_t))) // always allocate a minimum size buffer to avoid issues
35 #else
36 #define MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength) (cpuWaLength?cpuWaLength:1u) // always allocate a minimum size buffer to avoid issues
37 #define MCUXCLEXAMPLE_ALLOCATE_PKCWA(pkcWaLength) (pkcWaLength?pkcWaLength:1u) // always allocate a minimum size buffer to avoid issues
38 #endif
39 
40 #define MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(pSession, cpuWaLength, pkcWaLength) \
41  uint32_t cpuWaBuffer[MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength)]; \
42  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(si_status, token, mcuxClSession_init( \
43  /* mcuxClSession_Handle_t session: */ pSession, \
44  /* uint32_t * const cpuWaBuffer: */ cpuWaBuffer, \
45  /* uint32_t cpuWaSize: */ cpuWaLength, \
46  /* uint32_t * const pkcWaBuffer: */ (uint32_t *) PKC_RAM_ADDR, \
47  /* uint32_t pkcWaSize: */ pkcWaLength \
48  )); \
49  /* mcuxClSession_init is a flow-protected function: Check the protection token and the return value */ \
50  if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_init) != token) || (MCUXCLSESSION_STATUS_OK != si_status)) \
51  { \
52  return false; \
53  } \
54  MCUX_CSSL_FP_FUNCTION_CALL_END();
55 
60 MCUX_CSSL_FP_FUNCTION_DEF(mcuxClExample_Session_Clean)
61 static inline bool mcuxClExample_Session_Clean(mcuxClSession_Handle_t pSession)
62 {
63  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cleanup_result, cleanup_token, mcuxClSession_cleanup(pSession));
64 
65  if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_cleanup) != cleanup_token || MCUXCLSESSION_STATUS_OK != cleanup_result)
66  {
67  return false;
68  }
69 
70  MCUX_CSSL_FP_FUNCTION_CALL_END();
71 
72  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(destroy_result, destroy_token, mcuxClSession_destroy(pSession));
73 
74  if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_destroy) != destroy_token || MCUXCLSESSION_STATUS_OK != destroy_result)
75  {
76  return false;
77  }
78 
79  MCUX_CSSL_FP_FUNCTION_CALL_END();
80  return true;
81 }
82 
83 #endif /* MCUXCLEXAMPLE_SESSION_HELPER_H_ */
MCUX_CSSL_FP_FUNCTION_CALLED
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
Expectation of a called function.
Definition: mcuxCsslFlowProtection.h:730
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClSession_cleanup
mcuxClSession_Status_t mcuxClSession_cleanup(mcuxClSession_Handle_t pSession)
Clean up a Crypto Library session.
+
MCUXCLSESSION_STATUS_OK
#define MCUXCLSESSION_STATUS_OK
Session operation successful.
Definition: mcuxClSession_Types.h:44
+
mcuxClSession_destroy
mcuxClSession_Status_t mcuxClSession_destroy(mcuxClSession_Handle_t pSession)
Destroy a Crypto Library session.
+
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
Call a flow protected function and check the protection token.
Definition: mcuxCsslFlowProtection.h:576
+
MCUX_CSSL_FP_FUNCTION_DEF
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
Definition of a flow protected function.
Definition: mcuxCsslFlowProtection.h:159
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_CALL_END
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.
Definition: mcuxCsslFlowProtection.h:611
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00353.html b/components/els_pkc/doc/mcxn/html/a00353.html new file mode 100644 index 000000000..619a7c7b5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00353.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClHash.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+ +
+ +
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+ + +
+ +
+ +
+
+
mcuxClHash.h File Reference
+
+
+ +

Top-level include file for the mcuxClHash component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClHash_Types.h>
+#include <mcuxClHash_Functions.h>
+#include <mcuxClHash_MemoryConsumption.h>
+#include <mcuxClHash_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClHash component.

+

This includes headers for all of the functionality provided by the mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00353_source.html b/components/els_pkc/doc/mcxn/html/a00353_source.html new file mode 100644 index 000000000..08612c582 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00353_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClHash.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ +
+ +
+
+
mcuxClHash.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
43 #ifndef MCUXCLHASH_H_
44 #define MCUXCLHASH_H_
45 
46 #include <mcuxClConfig.h> // Exported features flags header
47 #include <mcuxClHash_Types.h>
48 #include <mcuxClHash_Functions.h>
49 #include <mcuxClHash_MemoryConsumption.h>
50 #include <mcuxClHash_Constants.h>
51 
52 #endif /* MCUXCLHASH_H_ */
mcuxClHash_Constants.h
Constants for use with the mcuxClHash component.
+
mcuxClHash_Functions.h
Top-level API of the mcuxClHash component.
+
mcuxClHash_MemoryConsumption.h
Defines the memory consumption for the mcuxClHash component.
+
mcuxClHash_Types.h
Type definitions for the mcuxClHash component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00356.html b/components/els_pkc/doc/mcxn/html/a00356.html new file mode 100644 index 000000000..558e63246 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00356.html @@ -0,0 +1,167 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHash_Constants.h File Reference
+
+
+ +

Constants for use with the mcuxClHash component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_STATUS_OK
 Hash operation successful. More...
 
#define MCUXCLHASH_STATUS_COMPARE_EQUAL
 Hash operation and comparison of result successful. More...
 
#define MCUXCLHASH_COMPARE_EQUAL
 
#define MCUXCLHASH_STATUS_FAILURE
 Hash operation failed. More...
 
#define MCUXCLHASH_FAILURE
 
#define MCUXCLHASH_STATUS_INVALID_PARAMS
 Hash function called with invalid parameters. More...
 
#define MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
 Export on state, for which a NON-multiple of the blocksize has been hashed. More...
 
#define MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
 
#define MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL
 Hash operation succeeded, but comparison of result failed. More...
 
#define MCUXCLHASH_COMPARE_NOT_EQUAL
 
#define MCUXCLHASH_STATUS_FULL
 Hash operation failed because the total input size exceeds the upper limit. More...
 
#define MCUXCLHASH_STATUS_FAULT_ATTACK
 Fault attack (unexpected behavior) detected. More...
 
+

Detailed Description

+

Constants for use with the mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00356.js b/components/els_pkc/doc/mcxn/html/a00356.js new file mode 100644 index 000000000..80e21f0c6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00356.js @@ -0,0 +1,15 @@ +var a00356 = +[ + [ "MCUXCLHASH_STATUS_OK", "a00771.html#gadf29410b02d95357d48a3ba443558da4", null ], + [ "MCUXCLHASH_STATUS_COMPARE_EQUAL", "a00771.html#gaaf06d7932b91cce6e94312a534f61934", null ], + [ "MCUXCLHASH_COMPARE_EQUAL", "a00771.html#ga05eaccf399e17f323499f31e764d5173", null ], + [ "MCUXCLHASH_STATUS_FAILURE", "a00771.html#ga377eaddc82740c4c4590688c754f78a0", null ], + [ "MCUXCLHASH_FAILURE", "a00771.html#gaaef282127a4c3c3e8f9a034cba1b70e0", null ], + [ "MCUXCLHASH_STATUS_INVALID_PARAMS", "a00771.html#ga6cd095f16a5ff26877cc877cecbd0e2b", null ], + [ "MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK", "a00771.html#gabeb9fdba3834bd6d1b62b53d0b981bb9", null ], + [ "MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK", "a00771.html#ga5cb4d265e6848270e5a3e38b5e57e84a", null ], + [ "MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL", "a00771.html#gad39c265fd8728f3287eeef999cfeb599", null ], + [ "MCUXCLHASH_COMPARE_NOT_EQUAL", "a00771.html#ga647cd722111188a5d028d1f3ab4eb795", null ], + [ "MCUXCLHASH_STATUS_FULL", "a00771.html#ga9abcd3d90166d6f4fd532d8b7c24931f", null ], + [ "MCUXCLHASH_STATUS_FAULT_ATTACK", "a00771.html#gaca3624d074b137e5587052f6ffb1b6f6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00356_source.html b/components/els_pkc/doc/mcxn/html/a00356_source.html new file mode 100644 index 000000000..305e80bfa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00356_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+
+
mcuxClHash_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLHASH_CONSTANTS_H_
18 #define MCUXCLHASH_CONSTANTS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 
35 #define MCUXCLHASH_STATUS_OK ((mcuxClHash_Status_t) 0x06662E03u)
36 #define MCUXCLHASH_STATUS_COMPARE_EQUAL ((mcuxClHash_Status_t) 0x06662E07u)
37 #define MCUXCLHASH_COMPARE_EQUAL MCUXCLHASH_STATUS_COMPARE_EQUAL
38 #define MCUXCLHASH_STATUS_FAILURE ((mcuxClHash_Status_t) 0x06665330u)
39 #define MCUXCLHASH_FAILURE MCUXCLHASH_STATUS_FAILURE
40 #define MCUXCLHASH_STATUS_INVALID_PARAMS ((mcuxClHash_Status_t) 0x066653F8u)
41 #define MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK ((mcuxClHash_Status_t) 0x06665338u)
42 #define MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
43 #define MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL ((mcuxClHash_Status_t) 0x06668930u)
44 #define MCUXCLHASH_COMPARE_NOT_EQUAL ((mcuxClHash_Status_t) 0x06668930u)
45 #define MCUXCLHASH_STATUS_FULL ((mcuxClHash_Status_t) 0x0666538Eu)
46 #define MCUXCLHASH_STATUS_FAULT_ATTACK ((mcuxClHash_Status_t) 0x0666F0F0u)
47 
51 #endif /* MCUXCLHASH_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00359.html b/components/els_pkc/doc/mcxn/html/a00359.html new file mode 100644 index 000000000..4951aacb4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00359.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClHash_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClHash component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClHash_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Functions

mcuxClHash_Status_t mcuxClHash_compute (mcuxClSession_Handle_t session, mcuxClHash_Algo_t algorithm, mcuxCl_InputBuffer_t pIn, uint32_t inSize, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
 One-shot Hash computation function. More...
 
mcuxClHash_Status_t mcuxClHash_init (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxClHash_Algo_t algorithm)
 Multi-part Hash initialization function. More...
 
mcuxClHash_Status_t mcuxClHash_process (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_InputBuffer_t pIn, uint32_t inSize)
 Multi-part Hash processing function. More...
 
mcuxClHash_Status_t mcuxClHash_finish (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
 Multi-part Hash computation finalization function. More...
 
+

Detailed Description

+

Top-level API of the mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00359.js b/components/els_pkc/doc/mcxn/html/a00359.js new file mode 100644 index 000000000..4c4d1950c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00359.js @@ -0,0 +1,7 @@ +var a00359 = +[ + [ "mcuxClHash_compute", "a00772.html#ga7beb1bb4063eae682eca700efeba93db", null ], + [ "mcuxClHash_init", "a00772.html#ga68263436904cf849bfbe8c9b1f6542d4", null ], + [ "mcuxClHash_process", "a00772.html#ga49bdf3dca9746328fe58e6d5859e92eb", null ], + [ "mcuxClHash_finish", "a00772.html#gad55cc3a702b915f84d9cd2e94c2b7f6b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00359_source.html b/components/els_pkc/doc/mcxn/html/a00359_source.html new file mode 100644 index 000000000..e1b63b7ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00359_source.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHash_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLHASH_FUNCTIONS_H_
18 #define MCUXCLHASH_FUNCTIONS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 #include <mcuxClSession_Types.h>
22 #include <mcuxClHash_Types.h>
23 #include <mcuxCsslFlowProtection.h>
24 #include <mcuxClCore_FunctionIdentifiers.h>
25 #include <mcuxClCore_Buffer.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /**********************************************************************/
39 /* ONE-SHOT */
40 /**********************************************************************/
41 
80 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_compute)
81 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_compute(
82  mcuxClSession_Handle_t session,
83  mcuxClHash_Algo_t algorithm,
84  mcuxCl_InputBuffer_t pIn,
85  uint32_t inSize,
86  mcuxCl_Buffer_t pOut,
87  uint32_t *const pOutSize
88 ); /* oneshot compute */
89 
90 
91 
92 /**********************************************************************/
93 /* MULTIPART */
94 /**********************************************************************/
95 
113 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_init)
114 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_init(
115  mcuxClSession_Handle_t session,
116  mcuxClHash_Context_t pContext,
117  mcuxClHash_Algo_t algorithm
118 ); /* init */
119 
142 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_process)
143 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_process(
144  mcuxClSession_Handle_t session,
145  mcuxClHash_Context_t pContext,
146  mcuxCl_InputBuffer_t pIn,
147  uint32_t inSize
148 ); /* update */
149 
173 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_finish)
174 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_finish(
175  mcuxClSession_Handle_t session,
176  mcuxClHash_Context_t pContext,
177  mcuxCl_Buffer_t pOut,
178  uint32_t *const pOutSize
179 ); /* finalize compute */
180 
181 
182  /* mcuxClHash_Functions */
186 
187 #ifdef __cplusplus
188 } /* extern "C" */
189 #endif
190 
191 #endif /* MCUXCLHASH_FUNCTIONS_H_ */
192 
mcuxClHash_Algo_t
const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
Hash mode/algorithm type.
Definition: mcuxClHash_Types.h:50
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClHash_Status_t
uint32_t mcuxClHash_Status_t
Hash Status type.
Definition: mcuxClHash_Types.h:78
+
mcuxClHash_finish
mcuxClHash_Status_t mcuxClHash_finish(mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
Multi-part Hash computation finalization function.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClHash_compute
mcuxClHash_Status_t mcuxClHash_compute(mcuxClSession_Handle_t session, mcuxClHash_Algo_t algorithm, mcuxCl_InputBuffer_t pIn, uint32_t inSize, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
One-shot Hash computation function.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClHash_init
mcuxClHash_Status_t mcuxClHash_init(mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxClHash_Algo_t algorithm)
Multi-part Hash initialization function.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClHash_Context_t
mcuxClHash_ContextDescriptor_t *const mcuxClHash_Context_t
Hash Context type.
Definition: mcuxClHash_Types.h:70
+
mcuxClHash_process
mcuxClHash_Status_t mcuxClHash_process(mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_InputBuffer_t pIn, uint32_t inSize)
Multi-part Hash processing function.
+
mcuxClHash_Types.h
Type definitions for the mcuxClHash component.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00362.html b/components/els_pkc/doc/mcxn/html/a00362.html new file mode 100644 index 000000000..1aa33072d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00362.html @@ -0,0 +1,290 @@ + + + + + + + +MCUX CLNS: mcuxClHash_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHash_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClHash component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClHash_compute. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClHash_compare. More...
 
#define MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required for mcuxClHash_init. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClHash_process. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClHash_finish. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClHash_verify. More...
 
#define MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required for this component. More...
 
#define MCUXCLHASH_CONTEXT_SIZE
 Defines the maximum size a context might need. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClHash component.

+

Macro Definition Documentation

+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClHash_compute.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClHash_compare.

+ +
+
+ +

◆ MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE

+ +
+
+ + + + +
#define MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE
+
+ +

Defines the max workarea size required for mcuxClHash_init.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClHash_process.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClHash_finish.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClHash_verify.

+ +
+
+ +

◆ MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE

+ +
+
+ + + + +
#define MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE
+
+ +

Defines the max workarea size required for this component.

+ +
+
+ +

◆ MCUXCLHASH_CONTEXT_SIZE

+ +
+
+ + + + +
#define MCUXCLHASH_CONTEXT_SIZE
+
+ +

Defines the maximum size a context might need.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00362.js b/components/els_pkc/doc/mcxn/html/a00362.js new file mode 100644 index 000000000..6af8f139f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00362.js @@ -0,0 +1,12 @@ +var a00362 = +[ + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX", "a00362.html#a8b3af117f171a613124593df58ada62a", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX", "a00362.html#a8e985e955759e3f5f6fb1d11c3901e2c", null ], + [ "MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE", "a00362.html#a8434a263faa18d7d5f1db037eca3a130", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX", "a00362.html#ac7007695fab49af24194295d81f80b56", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX", "a00362.html#a63da111398b07963ed1a77da6c97a64d", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX", "a00362.html#a59a048780405bb5b38b256cf689bdf80", null ], + [ "MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE", "a00362.html#a8c70073fba8e9b6bdd946ca99e3dfcf4", null ], + [ "MCUXCLHASH_CONTEXT_SIZE", "a00362.html#a42253ef03c357fbdcc8a0c502f34c4f3", null ], + [ "MCUXCLHASH_CONTEXT_SIZE_IN_WORDS", "a00362.html#a7f64d7a91943132c5f4be29307f70059", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00362_source.html b/components/els_pkc/doc/mcxn/html/a00362_source.html new file mode 100644 index 000000000..7bafd2470 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00362_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClHash_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHash_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLHASH_MEMORYCONSUMPTION_H_
18 #define MCUXCLHASH_MEMORYCONSUMPTION_H_
19 
20 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX (192u)
21 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
22 #define MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE (4u)
23 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX (4u)
24 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX (192u)
25 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX
26 
27 #define MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE (192u)
28 
29 
30 /****************************************************************************/
31 /* Definitions of context sizes for the mcuxClHash multi-part functions. */
32 /****************************************************************************/
33 
34 #define MCUXCLHASH_CONTEXT_SIZE (392u)
35 #define MCUXCLHASH_CONTEXT_SIZE_IN_WORDS (392u / sizeof(uint32_t))
36 
37 
38 #endif /* MCUXCLHASH_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00365.html b/components/els_pkc/doc/mcxn/html/a00365.html new file mode 100644 index 000000000..16abd5e6b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00365.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClHash_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClHash component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClCore_Platform.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
 Hash mode/algorithm descriptor type. More...
 
typedef const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
 Hash mode/algorithm type. More...
 
typedef struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t
 Hash Context buffer type. More...
 
typedef mcuxClHash_ContextDescriptor_t *const mcuxClHash_Context_t
 Hash Context type. More...
 
typedef uint32_t mcuxClHash_Status_t
 Hash Status type. More...
 
+

Detailed Description

+

Type definitions for the mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00365.js b/components/els_pkc/doc/mcxn/html/a00365.js new file mode 100644 index 000000000..c61d3b633 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00365.js @@ -0,0 +1,8 @@ +var a00365 = +[ + [ "mcuxClHash_AlgorithmDescriptor_t", "a00773.html#gacccec0a811d221d2cb0fd8416da271d8", null ], + [ "mcuxClHash_Algo_t", "a00773.html#ga0ffeeb89c76da6470176e7621713e1b2", null ], + [ "mcuxClHash_ContextDescriptor_t", "a00773.html#ga90ff7c4f43e59b80eca542e35722124c", null ], + [ "mcuxClHash_Context_t", "a00773.html#ga84c437ceb6b43a992b75866f793d0956", null ], + [ "mcuxClHash_Status_t", "a00773.html#gacdfd7a833fcd06684a73c22364e89b7c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00365_source.html b/components/els_pkc/doc/mcxn/html/a00365_source.html new file mode 100644 index 000000000..6bd7e737f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00365_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHash_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLHASH_TYPES_H_
19 #define MCUXCLHASH_TYPES_H_
20 
21 #include <mcuxClConfig.h> // Exported features flags header
22 #include <mcuxClCore_Platform.h>
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
42 typedef struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t;
43 
50 typedef const mcuxClHash_AlgorithmDescriptor_t * const mcuxClHash_Algo_t;
51 
52 
53 
61 typedef struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t;
62 
70 typedef mcuxClHash_ContextDescriptor_t * const mcuxClHash_Context_t;
71 
78 typedef uint32_t mcuxClHash_Status_t;
79 
82 #ifdef __cplusplus
83 } /* extern "C" */
84 #endif
85 
86 #endif /* MCUXCLHASH_TYPES_H_ */
mcuxClHash_Algo_t
const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
Hash mode/algorithm type.
Definition: mcuxClHash_Types.h:50
+
mcuxClHash_Status_t
uint32_t mcuxClHash_Status_t
Hash Status type.
Definition: mcuxClHash_Types.h:78
+
mcuxClHash_ContextDescriptor_t
struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t
Hash Context buffer type.
Definition: mcuxClHash_Types.h:61
+
mcuxClHash_Context_t
mcuxClHash_ContextDescriptor_t *const mcuxClHash_Context_t
Hash Context type.
Definition: mcuxClHash_Types.h:70
+
mcuxClHash_AlgorithmDescriptor_t
struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
Hash mode/algorithm descriptor type.
Definition: mcuxClHash_Types.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00368_source.html b/components/els_pkc/doc/mcxn/html/a00368_source.html new file mode 100644 index 000000000..821fbfb87 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00368_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHashModes.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLHASHMODES_H_
15 #define MCUXCLHASHMODES_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClHashModes_Algorithms.h>
19 #include <mcuxClHashModes_Constants.h>
20 #include <mcuxClHashModes_Functions.h>
21 #include <mcuxClHashModes_MemoryConsumption.h>
22 
23 #endif /* MCUXCLHASHMODES_H_ */
mcuxClHashModes_Constants.h
Constants for use with the mcuxClHashModes component.
+
mcuxClHashModes_MemoryConsumption.h
Defines the memory consumption for the mcuxClHash component.
+
mcuxClHashModes_Algorithms.h
Algorithm/mode definitions for the mcuxClHashModes component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00371.html b/components/els_pkc/doc/mcxn/html/a00371.html new file mode 100644 index 000000000..bf79eceaa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00371.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Algorithms.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClHashModes_Algorithms.h File Reference
+
+
+ +

Algorithm/mode definitions for the mcuxClHashModes component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxClHash_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224
 Sha-224 algorithm descriptor Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224
 Sha-224 algorithm Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256
 Sha-256 algorithm descriptor Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256
 Sha-256 algorithm Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384
 Sha-384 algorithm descriptor Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384
 Sha-384 algorithm Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512
 Sha-512 algorithm descriptor Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512
 Sha-512 algorithm Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
+

Detailed Description

+

Algorithm/mode definitions for the mcuxClHashModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00371.js b/components/els_pkc/doc/mcxn/html/a00371.js new file mode 100644 index 000000000..4e019d9fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00371.js @@ -0,0 +1,11 @@ +var a00371 = +[ + [ "mcuxClHash_AlgorithmDescriptor_Sha224", "a00774.html#ga56d71cf5a53a9e64a648c4d9776efa8e", null ], + [ "mcuxClHash_Algorithm_Sha224", "a00774.html#ga4de6a5917dc46d3aae22f93df66fc228", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha256", "a00774.html#ga0332b3c0540cd1761dfaa17b33f02f02", null ], + [ "mcuxClHash_Algorithm_Sha256", "a00774.html#ga672407195f718d55fcee73d1dfb7c623", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha384", "a00774.html#ga18de1261f5761dfc43ef89a102fda259", null ], + [ "mcuxClHash_Algorithm_Sha384", "a00774.html#gaa7389b8db9ec5c97b44db899e2b9f8db", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha512", "a00774.html#ga50a5ce5101cf1175127bdf1ea7bfb0e1", null ], + [ "mcuxClHash_Algorithm_Sha512", "a00774.html#gae0687309bef869b41302594c6c934d9a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00371_source.html b/components/els_pkc/doc/mcxn/html/a00371_source.html new file mode 100644 index 000000000..f02c0fcdd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00371_source.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Algorithms.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHashModes_Algorithms.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLHASHMODES_ALGORITHMS_H_
19 #define MCUXCLHASHMODES_ALGORITHMS_H_
20 
21 #include <mcuxClConfig.h> // Exported features flags header
22 #include <mcuxClCore_Platform.h>
23 #include <mcuxCsslAnalysis.h>
24 #include <mcuxClHash_Types.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
38 MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER()
39 
40 
41 
42 
43 
44 
45 
46 
47 
48 
49 
55 extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224;
56 
62 static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224 = &mcuxClHash_AlgorithmDescriptor_Sha224;
63 
64 
70 extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256;
71 
77 static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256 = &mcuxClHash_AlgorithmDescriptor_Sha256;
78 
79 
85 extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384;
86 
92 static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384 = &mcuxClHash_AlgorithmDescriptor_Sha384;
93 
94 
100 extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512;
101 
107 static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512 = &mcuxClHash_AlgorithmDescriptor_Sha512;
108 
109 
110 
111 
112 
113 
114 
115 
116 
117 
118 
119 
120 
121 
122 
123 
124 
125 
126 
127 
128 
129 
130 
131 
132 
133 
134 
135 
136 MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER()
137 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
138 
141 #ifdef __cplusplus
142 } /* extern "C" */
143 #endif
144 
145 #endif /* MCUXCLHASHMODES_ALGORITHMS_H_ */
mcuxClHash_Algorithm_Sha512
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512
Sha-512 algorithm Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF.
Definition: mcuxClHashModes_Algorithms.h:107
+
mcuxClHash_AlgorithmDescriptor_Sha256
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256
Sha-256 algorithm descriptor Sha-256 hash calculation using the Hash functionality of ELS,...
+
mcuxClHash_AlgorithmDescriptor_Sha224
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224
Sha-224 algorithm descriptor Sha-224 hash calculation using the Hash functionality of ELS,...
+
mcuxClHash_Algo_t
const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
Hash mode/algorithm type.
Definition: mcuxClHash_Types.h:50
+
mcuxClHash_Algorithm_Sha256
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256
Sha-256 algorithm Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF.
Definition: mcuxClHashModes_Algorithms.h:77
+
mcuxClHash_Algorithm_Sha224
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224
Sha-224 algorithm Sha-224 hash calculation using the Hash functionality of ELS, it does not support R...
Definition: mcuxClHashModes_Algorithms.h:62
+
mcuxClHash_AlgorithmDescriptor_Sha384
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384
Sha-384 algorithm descriptor Sha-384 hash calculation using the Hash functionality of ELS,...
+
mcuxClHash_AlgorithmDescriptor_Sha512
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512
Sha-512 algorithm descriptor Sha-512 hash calculation using the Hash functionality of ELS,...
+
mcuxClHash_Algorithm_Sha384
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384
Sha-384 algorithm Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF.
Definition: mcuxClHashModes_Algorithms.h:92
+
mcuxClHash_Types.h
Type definitions for the mcuxClHash component.
+
mcuxClHash_AlgorithmDescriptor_t
struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
Hash mode/algorithm descriptor type.
Definition: mcuxClHash_Types.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00374.html b/components/els_pkc/doc/mcxn/html/a00374.html new file mode 100644 index 000000000..c196c2bfe --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00374.html @@ -0,0 +1,186 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHashModes_Constants.h File Reference
+
+
+ +

Constants for use with the mcuxClHashModes component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_OUTPUT_SIZE_MD5
 MD5 output size: 128 bit (16 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_1
 SHA-1 output size: 160 bit (20 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_224
 SHA-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_256
 SHA-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_384
 SHA-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512
 SHA-512 output size: 512 bit (64 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_224
 SHA-512/224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_256
 SHA-512/256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_224
 SHA3-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_256
 SHA3-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_384
 SHA3-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_512
 SHA3-512 output size: 512 bit (64 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128
 SHA3-SHAKE 128 output size: 1344 bit (168 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256
 SHA3-SHAKE 256 output size: 1088 bit (136 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128
 SHA3-CSHAKE 128 output size: 1344 bit (168 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256
 SHA3-CSHAKE 256 output size: 1088 bit (136 bytes) More...
 
#define MCUXCLHASH_MAX_OUTPUT_SIZE
 Maximum output size. More...
 
+

Detailed Description

+

Constants for use with the mcuxClHashModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00374.js b/components/els_pkc/doc/mcxn/html/a00374.js new file mode 100644 index 000000000..aacd6fe12 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00374.js @@ -0,0 +1,20 @@ +var a00374 = +[ + [ "MCUXCLHASH_OUTPUT_SIZE_MD5", "a00775.html#gafe7e3fec63db293d11223cf996b0f933", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_1", "a00775.html#ga8e6f2196aa9cc22514327290e9c6d265", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_224", "a00775.html#ga4f3a086ffb19f8127e04dd2e9c458a48", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_256", "a00775.html#gaf4d4bd473c10a1c0e474dfa6ebad83d3", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_384", "a00775.html#gad9f68a357e04e78a8930ae8575d2fb95", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512", "a00775.html#gab3854625bf1807c8be0d0eda40c9b15c", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512_224", "a00775.html#ga2b26c1ca0f30feb3c3e12f97ca433935", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512_256", "a00775.html#ga106037a11d7e73694703696f1cbd9b8a", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_224", "a00775.html#ga9b455baf1195244a5a21f95d24d1bb78", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_256", "a00775.html#ga2d4ce7c5407c45486781710968933d59", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_384", "a00775.html#ga9ba519f3947e62fe3c33ba89912415f2", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_512", "a00775.html#ga98c0f235847458f6e0785ce7e1fa4de1", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128", "a00775.html#gaf92c4c2afd86cf0276655d833fc92946", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256", "a00775.html#ga6208318273d199569492d2df54285bfb", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128", "a00775.html#gabee2279c4070bb6e490acc465d19f7b1", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256", "a00775.html#ga1310682860222f35228b9b69e9110b7b", null ], + [ "MCUXCLHASH_MAX_OUTPUT_SIZE", "a00775.html#ga1be4781928bd9fa5aa9ea9fc9140320b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00374_source.html b/components/els_pkc/doc/mcxn/html/a00374_source.html new file mode 100644 index 000000000..9d21af642 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00374_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHashModes_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLHASHMODES_CONSTANTS_H_
18 #define MCUXCLHASHMODES_CONSTANTS_H_
19 
20 #include <mcuxClConfig.h> // Exported features flags header
21 
35 #define MCUXCLHASH_OUTPUT_SIZE_MD5 (16U)
36 #define MCUXCLHASH_OUTPUT_SIZE_SHA_1 (20U)
37 #define MCUXCLHASH_OUTPUT_SIZE_SHA_224 (28U)
38 #define MCUXCLHASH_OUTPUT_SIZE_SHA_256 (32U)
39 #define MCUXCLHASH_OUTPUT_SIZE_SHA_384 (48U)
40 #define MCUXCLHASH_OUTPUT_SIZE_SHA_512 (64U)
41 #define MCUXCLHASH_OUTPUT_SIZE_SHA_512_224 (28U)
42 #define MCUXCLHASH_OUTPUT_SIZE_SHA_512_256 (32U)
43 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_224 (28uL)
44 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_256 (32uL)
45 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_384 (48uL)
46 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_512 (64uL)
47 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128 (168uL)
48 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256 (136uL)
49 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128 (168uL)
50 #define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256 (136uL)
51 #define MCUXCLHASH_MAX_OUTPUT_SIZE (MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128)
52 
59 #endif /* MCUXCLHASHMODES_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00377_source.html b/components/els_pkc/doc/mcxn/html/a00377_source.html new file mode 100644 index 000000000..2abc1e794 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00377_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHashModes_Functions.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLHASHMODES_FUNCTIONS_H_
15 #define MCUXCLHASHMODES_FUNCTIONS_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClHash.h>
19 
20 
21 #endif /* MCUXCLHASHMODES_FUNCTIONS_H_ */
mcuxClHash.h
Top-level include file for the mcuxClHash component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00380.html b/components/els_pkc/doc/mcxn/html/a00380.html new file mode 100644 index 000000000..aaa0657fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00380.html @@ -0,0 +1,248 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHashModes_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClHash component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_compute on SHA2-224. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_compare on SHA2-224. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_process on SHA2-224. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_finish on SHA2-224. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_verify on SHA2-224. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_compute on SHA2-256. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_compare on SHA2-256. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_process on SHA2-256. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_finish on SHA2-256. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_verify on SHA2-256. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_compute on SHA2-384. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_compare on SHA2-384. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_process on SHA2-384. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_finish on SHA2-384. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_verify on SHA2-384. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_compute on SHA2-512. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_compute on SHA2-512/224. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_compute on SHA2-512/256. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_compare on SHA2-512. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_compare on SHA2-512/224. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_compare on SHA2-512/256. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_process on SHA2-512. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_process on SHA2-512/224. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_process on SHA2-512/256. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_finish on SHA2-512. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_finish on SHA2-512/224. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_finish on SHA2-512/256. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_verify on SHA2-512. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_verify on SHA2-512/224. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_verify on SHA2-512/256. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_224_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224
 Defines the state size required for SHA2-224. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256
 Defines the state size required for SHA2-256. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_384_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384
 Defines the state size required for SHA2-384. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_512_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512
 Defines the state size required for SHA2-512. More...
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00380.js b/components/els_pkc/doc/mcxn/html/a00380.js new file mode 100644 index 000000000..b348cb7a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00380.js @@ -0,0 +1,41 @@ +var a00380 = +[ + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga40b9eff6f42215fc5c98c0513fbd2c79", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga8ff96915814df592db3d68d925408a98", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga2ff77f524496774f46c5294dfc7619bf", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#gae23cdd9e00a486600ee5b90949f3842f", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#gabf598385358401cea01d065d9d421d87", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga0ebf52b4105a30badc619e7ba70193b3", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#gaa98512fd1ef5f7d8310a811035811fbb", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga6a38dced70e095517b706930b2c164c4", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga7e0a2938cc503a204da719c7b8aab627", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#gaf0e29b1e66d6d5a8af6b4c20ec5bb85e", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga55b9dabdce9439ad6fec034dc86ead8c", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#gaa4c0e341d16ed5fe2be37691f582e326", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#gaeca1828134728d6d1d7da343711934e6", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga64ac4667e73071d261d273b72abc70d9", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga2dc773fc49bfd2c5dd1fc298a3dadb35", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#gaa7b677e561a919060c8c1eae1c5f2455", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#gaa1ea090ae23f0e04f553cdfbeb2573a9", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#gac7c04d4fd538f29eb200ae68a076853e", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga762efcb01b7aaf95266adfb3c9b174b0", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga6dbc0f41ec9388bbc8aeb99e2ee37230", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga3e3ada3faaecda7fbef060e2c3e835f8", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#gac571e29844bf3dc2cd052c28e40dc90e", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#gab081523fa0e85169ed405bd514f0e318", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#gac38cbbdbd0ae6c935f09f75ba51bf8de", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga0b23abb47f314adac81fa08cabded273", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga1d3671a1c73c8ef559ac12b3206ab952", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga95fcec323ebd8dbfddc56a99e6f49900", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga50e9da09a4a92534775a94da69c17b48", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga9e3c10d8b549eba86ff96332417ecbdb", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga000d10c6a9b9475289a7ff08cb283394", null ], + [ "MCUXCLHASH_CONTEXT_SIZE_SHA2_224_IN_WORDS", "a00777.html#ga2c04d0cffab682e5b9b6952d4a528f98", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224", "a00777.html#ga64ea4a6c44d5714d06cde9c858ca963f", null ], + [ "MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS", "a00777.html#gab93330a244ea077e8d0bd011e11338d4", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256", "a00777.html#gac40907ce6e09e87b7931823ad48a50c3", null ], + [ "MCUXCLHASH_CONTEXT_SIZE_SHA2_384_IN_WORDS", "a00777.html#gaafc7a84f853c89c470675cad975b7bb7", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384", "a00777.html#ga09b5656067c3ab3e89c3d0aaa9f2e5ad", null ], + [ "MCUXCLHASH_CONTEXT_SIZE_SHA2_512_IN_WORDS", "a00777.html#ga53faec405d34f4f97a20e0db6d63c20d", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512", "a00777.html#gad09b3d78d2a33f965308f2e4c34ea0cf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00380_source.html b/components/els_pkc/doc/mcxn/html/a00380_source.html new file mode 100644 index 000000000..4687034dd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00380_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHashModes_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLHASHMODES_MEMORYCONSUMPTION_H_
18 #define MCUXCLHASHMODES_MEMORYCONSUMPTION_H_
19 
27 /****************************************************************************/
28 /* Definitions of workarea buffer sizes for the mcuxClHashModes functions. */
29 /****************************************************************************/
30 
31 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224 (96u)
32 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224
33 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224 (4u)
34 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224 (96u)
35 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224
36 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256 (96u)
37 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256
38 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256 (4u)
39 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256 (96u)
40 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256
41 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384 (192u)
42 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384
43 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384 (4u)
44 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384 (192u)
45 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384
46 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512 (192u)
47 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224 (192u)
48 #define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256 (192u)
49 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512
50 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224
51 #define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256
52 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512 (4u)
53 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224 (4u)
54 #define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256 (4u)
55 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512 (192u)
56 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224 (192u)
57 #define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256 (192u)
58 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512
59 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224
60 #define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256
61 
71 /**************************************************************************************************************/
72 /* Definitions of context sizes and state buffer sizes for mcuxClHash_export_state and mcuxClHash_import_state */
73 /**************************************************************************************************************/
74 
75 #define MCUXCLHASH_CONTEXT_SIZE_SHA2_224_IN_WORDS (120u / sizeof(uint32_t))
76 #define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224 (40u)
77 #define MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS (120u / sizeof(uint32_t))
78 #define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256 (40u)
79 #define MCUXCLHASH_CONTEXT_SIZE_SHA2_384_IN_WORDS (216u / sizeof(uint32_t))
80 #define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384 (80u)
81 #define MCUXCLHASH_CONTEXT_SIZE_SHA2_512_IN_WORDS (216u / sizeof(uint32_t))
82 #define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512 (80u)
83 
86 #endif /* MCUXCLHASHMODES_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00383_source.html b/components/els_pkc/doc/mcxn/html/a00383_source.html new file mode 100644 index 000000000..9946438ab --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00383_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClHmac.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
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+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHmac.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLHMAC_H_
15 #define MCUXCLHMAC_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClHmac_Constants.h>
19 #include <mcuxClHmac_Functions.h>
20 #include <mcuxClHmac_MemoryConsumption.h>
21 #include <mcuxClHmac_Modes.h>
22 #include <mcuxClHmac_KeyTypes.h>
23 #endif /* MCUXCLHMAC_H_ */
mcuxClHmac_MemoryConsumption.h
Defines the memory consumption for the mcuxClHmac component All work area sizes in bytes are a multip...
+
mcuxClHmac_Modes.h
Mode descriptors for the mcuxClHmac component.
+
mcuxClHmac_Constants.h
Constants for the mcuxClHmac component.
+
mcuxClHmac_Functions.h
Functions for the mcuxClHmac component.
+
mcuxClHmac_KeyTypes.h
Definition of supported key types in mcuxClHmac component, see also mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00386.html b/components/els_pkc/doc/mcxn/html/a00386.html new file mode 100644 index 000000000..8ac68286b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00386.html @@ -0,0 +1,160 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHmac_Constants.h File Reference
+
+
+ +

Constants for the mcuxClHmac component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClHashModes_Constants.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLHMAC_ELS_OUTPUT_SIZE
 
+#define MCUXCLHMAC_ELS_OUTPUT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_MAX_OUTPUT_SIZE
 
+#define MCUXCLHMAC_MAX_OUTPUT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_ELS_BLOCK_SIZE
 
+#define MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD
 
#define MCUXCLHMAC_ELS_MIN_PADDING_LENGTH
 Size of minimum HMAC padding length. More...
 
#define MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH(dataLength)
 Formula to calculate input buffer size for HMAC with SHA-256. More...
 
+

Detailed Description

+

Constants for the mcuxClHmac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00386.js b/components/els_pkc/doc/mcxn/html/a00386.js new file mode 100644 index 000000000..d61d63229 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00386.js @@ -0,0 +1,11 @@ +var a00386 = +[ + [ "MCUXCLHMAC_ELS_OUTPUT_SIZE", "a00778.html#gab2c0a4b35c88ad7030723c7c08589973", null ], + [ "MCUXCLHMAC_ELS_OUTPUT_SIZE_IN_WORDS", "a00778.html#ga834fe8d5cb9bd67d7546fb65b1ce0a3d", null ], + [ "MCUXCLHMAC_MAX_OUTPUT_SIZE", "a00778.html#ga805cc0a6fd67f42bd457b3580e74d1f3", null ], + [ "MCUXCLHMAC_MAX_OUTPUT_SIZE_IN_WORDS", "a00778.html#gaad0284f5ab76848289067aff908176bd", null ], + [ "MCUXCLHMAC_ELS_BLOCK_SIZE", "a00778.html#ga3a88f703f1237941c22789183be3ddc2", null ], + [ "MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD", "a00778.html#ga38f449fb5de294a9f398b33a37b96708", null ], + [ "MCUXCLHMAC_ELS_MIN_PADDING_LENGTH", "a00778.html#gaeea21ec876a193348d5f78b5014da165", null ], + [ "MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH", "a00778.html#gac9e4d270e79fa637dfac0c4919bf5eda", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00386_source.html b/components/els_pkc/doc/mcxn/html/a00386_source.html new file mode 100644 index 000000000..41787b763 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00386_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
mcuxClHmac_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLHMAC_CONSTANTS_H_
20 #define MCUXCLHMAC_CONSTANTS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 #include <mcuxClHashModes_Constants.h>
24 
32 /* Output sizes */
33 
34 #define MCUXCLHMAC_ELS_OUTPUT_SIZE (32u) /* Size of HMAC SHA-256 output in bytes: 256 bits (32 bytes) */
35 #define MCUXCLHMAC_ELS_OUTPUT_SIZE_IN_WORDS (MCUXCLHMAC_ELS_OUTPUT_SIZE / sizeof(uint32_t))
36 
37 #define MCUXCLHMAC_MAX_OUTPUT_SIZE (MCUXCLHASH_MAX_OUTPUT_SIZE)
38 #define MCUXCLHMAC_MAX_OUTPUT_SIZE_IN_WORDS (MCUXCLHMAC_MAX_OUTPUT_SIZE / sizeof(uint32_t))
39 
40 /* Helper macros and constants for HMAC buffer sizes, assuming HMAC on ELS with SHA-256 is used */
41 #define MCUXCLHMAC_ELS_BLOCK_SIZE (64u)
42 #define MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD (8u)
43 #define MCUXCLHMAC_ELS_MIN_PADDING_LENGTH (MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD + 1u)
44 #define MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH(dataLength) \
45  ((((dataLength) + MCUXCLHMAC_ELS_MIN_PADDING_LENGTH) + (MCUXCLHMAC_ELS_BLOCK_SIZE) - 1) / (MCUXCLHMAC_ELS_BLOCK_SIZE)) * MCUXCLHMAC_ELS_BLOCK_SIZE
46 
47 
49 #endif /* MCUXCLHMAC_CONSTANTS_H_ */
mcuxClHashModes_Constants.h
Constants for use with the mcuxClHashModes component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00389.html b/components/els_pkc/doc/mcxn/html/a00389.html new file mode 100644 index 000000000..cb91aa932 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00389.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClHmac_Functions.h File Reference
+
+
+ +

Functions for the mcuxClHmac component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClMac_Types.h>
+#include <mcuxClHash_Types.h>
+
+

Go to the source code of this file.

+ + + + + +

+Functions

mcuxClMac_Status_t mcuxClHmac_createHmacMode (mcuxClMac_CustomMode_t mode, mcuxClHash_Algo_t hashAlgorithm)
 This function creates a HMAC mode descriptor for software implementations of HMAC. More...
 
+

Detailed Description

+

Functions for the mcuxClHmac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00389.js b/components/els_pkc/doc/mcxn/html/a00389.js new file mode 100644 index 000000000..9716af796 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00389.js @@ -0,0 +1,4 @@ +var a00389 = +[ + [ "mcuxClHmac_createHmacMode", "a00780.html#ga43f6d98b6b3b6a6e62263130e2c95a68", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00389_source.html b/components/els_pkc/doc/mcxn/html/a00389_source.html new file mode 100644 index 000000000..8cd5520e7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00389_source.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHmac_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLHMAC_FUNCTIONS_H_
20 #define MCUXCLHMAC_FUNCTIONS_H_
21 
22 #include <mcuxClCore_Platform.h>
23 #include <mcuxCsslFlowProtection.h>
24 #include <mcuxClSession_Types.h>
25 #include <mcuxClMac_Types.h>
26 #include <mcuxClHash_Types.h>
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
60 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_createHmacMode)
61 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_createHmacMode(
62  mcuxClMac_CustomMode_t mode,
63  mcuxClHash_Algo_t hashAlgorithm
64 );
65  /* mcuxClHmac_Constructors */
69  /* mcuxClHmac_Functions */
73 
74 #ifdef __cplusplus
75 } /* extern "C" */
76 #endif
77 
78 #endif /* MCUXCLHMAC_FUNCTIONS_H_ */
mcuxClMac_CustomMode_t
mcuxClMac_ModeDescriptor_t *const mcuxClMac_CustomMode_t
MAC custom mode/algorithm type.
Definition: mcuxClMac_Types.h:75
+
mcuxClHmac_createHmacMode
mcuxClMac_Status_t mcuxClHmac_createHmacMode(mcuxClMac_CustomMode_t mode, mcuxClHash_Algo_t hashAlgorithm)
This function creates a HMAC mode descriptor for software implementations of HMAC.
+
mcuxClHash_Algo_t
const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
Hash mode/algorithm type.
Definition: mcuxClHash_Types.h:50
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClHash_Types.h
Type definitions for the mcuxClHash component.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
mcuxClMac_Status_t
uint32_t mcuxClMac_Status_t
Type for Mac component error codes.
Definition: mcuxClMac_Types.h:44
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00392.html b/components/els_pkc/doc/mcxn/html/a00392.html new file mode 100644 index 000000000..4988b09c5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00392.html @@ -0,0 +1,148 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_KeyTypes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+Variables
+
+
mcuxClHmac_KeyTypes.h File Reference
+
+
+ +

Definition of supported key types in mcuxClHmac component, see also mcuxClKey component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClKey_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256
 Key type structure for HMAC-SHA256 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256
 Key type pointer for HMAC-SHA256 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength
 Key type structure for Sw-HMAC based keys with variable length. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength
 Key type pointer for HMAC-SHA256 based keys with variable length. More...
 
+

Detailed Description

+

Definition of supported key types in mcuxClHmac component, see also mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00392.js b/components/els_pkc/doc/mcxn/html/a00392.js new file mode 100644 index 000000000..b26ecda74 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00392.js @@ -0,0 +1,7 @@ +var a00392 = +[ + [ "mcuxClKey_TypeDescriptor_HmacSha256", "a00781.html#gaa7829411660f435c478e54884f9dc235", null ], + [ "mcuxClKey_Type_HmacSha256", "a00781.html#ga6d1ebb714b890c9b193a68edb3038720", null ], + [ "mcuxClKey_TypeDescriptor_Hmac_variableLength", "a00781.html#gae7b0c9b1b7b2c69b0d8c9ac6decdcf1f", null ], + [ "mcuxClKey_Type_Hmac_variableLength", "a00781.html#ga42eb018ca876c87b3d4539532ab2154d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00392_source.html b/components/els_pkc/doc/mcxn/html/a00392_source.html new file mode 100644 index 000000000..cfc2e8518 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00392_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_KeyTypes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+
+
mcuxClHmac_KeyTypes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLHMAC_KEYTYPES_H_
20 #define MCUXCLHMAC_KEYTYPES_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #include <mcuxClKey_Types.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
36 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ")
41 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256;
42 
46 static const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256 = &mcuxClKey_TypeDescriptor_HmacSha256;
47 
52 extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength;
53 
57 static const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength = &mcuxClKey_TypeDescriptor_Hmac_variableLength;
58 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
59  /* mcuxClHmac_KeyTypes */
63 
64 #ifdef __cplusplus
65 } /* extern "C" */
66 #endif
67 
68 #endif /* MCUXCLHMAC_KEYTYPES_H_ */
mcuxClKey_TypeDescriptor_t
struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
Key type descriptor type.
Definition: mcuxClKey_Types.h:104
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey_Type_HmacSha256
static const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256
Key type pointer for HMAC-SHA256 based keys.
Definition: mcuxClHmac_KeyTypes.h:46
+
mcuxClKey_TypeDescriptor_HmacSha256
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256
Key type structure for HMAC-SHA256 based keys.
+
mcuxClKey_TypeDescriptor_Hmac_variableLength
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength
Key type structure for Sw-HMAC based keys with variable length.
+
mcuxClKey_Type_Hmac_variableLength
static const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength
Key type pointer for HMAC-SHA256 based keys with variable length.
Definition: mcuxClHmac_KeyTypes.h:57
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00395.html b/components/els_pkc/doc/mcxn/html/a00395.html new file mode 100644 index 000000000..fa617a381 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00395.html @@ -0,0 +1,191 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHmac_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClHmac component All work area sizes in bytes are a multiple of CPU wordsize. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHMAC_SIZE_IN_CPUWORDS(size)
 Helper macro to calculate size aligned to CPU word. More...
 
+#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_SW
 
+#define MCUXCLHMAC_CONTEXT_SIZE_SW_IN_WORDS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_ELS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_ELS_IN_WORDS
 
+#define MCUXCLHMAC_MAX_CONTEXT_SIZE
 
+#define MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE
 
+#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClHmac component All work area sizes in bytes are a multiple of CPU wordsize.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00395.js b/components/els_pkc/doc/mcxn/html/a00395.js new file mode 100644 index 000000000..bbd0facda --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00395.js @@ -0,0 +1,22 @@ +var a00395 = +[ + [ "MCUXCLHMAC_SIZE_IN_CPUWORDS", "a00782.html#ga7ebd777bda72a587fe816238ee14106c", null ], + [ "MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE", "a00782.html#gafa4c1919e1b7a450b573c635488f8be5", null ], + [ "MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00782.html#gad2b69f64e83b40bda46be831f4062da5", null ], + [ "MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE", "a00782.html#ga01e22cdce0b2a5c08859a4a2b54dbbaa", null ], + [ "MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00782.html#ga6301069f46a847b4328bb40c9bc1ce05", null ], + [ "MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE", "a00782.html#gad32487e6264e582b7f49a561cce85650", null ], + [ "MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00782.html#ga9f609a47a9855e913e6618067630e79f", null ], + [ "MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE", "a00782.html#ga91c9ac6a5ad4b40f506fe571c68c34de", null ], + [ "MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00782.html#ga3dafad1d1b9f291435c67c403e4c13b5", null ], + [ "MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE", "a00782.html#gadd36023bc355c5b378f7e2437e163a48", null ], + [ "MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00782.html#gab4440c0475cc08afa1769fa0e800a231", null ], + [ "MCUXCLHMAC_CONTEXT_SIZE_SW", "a00782.html#ga14a7e14d5595d74efaadd2e02182d681", null ], + [ "MCUXCLHMAC_CONTEXT_SIZE_SW_IN_WORDS", "a00782.html#ga361d774a54d813f81e554cca45c13326", null ], + [ "MCUXCLHMAC_CONTEXT_SIZE_ELS", "a00782.html#gafada1dbe049cd70862e1de0e53f26c71", null ], + [ "MCUXCLHMAC_CONTEXT_SIZE_ELS_IN_WORDS", "a00782.html#ga663b075450a0f5fdb41b2b7fe96fcd8e", null ], + [ "MCUXCLHMAC_MAX_CONTEXT_SIZE", "a00782.html#gacd9993ae04818b78e0ad3930ceaeb8bd", null ], + [ "MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS", "a00782.html#gaaddc32b2f69d37d2e2a60a96c826aa5e", null ], + [ "MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE", "a00782.html#ga3ed5d2cb469346c2bc7c4e5c185cd3ce", null ], + [ "MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE_IN_WORDS", "a00782.html#gaf4eac2a7dedcf27bc4bf13e3396268df", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00395_source.html b/components/els_pkc/doc/mcxn/html/a00395_source.html new file mode 100644 index 000000000..73321c67b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00395_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHmac_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLHMAC_MEMORYCONSUMPTION_H_
20 #define MCUXCLHMAC_MEMORYCONSUMPTION_H_
21 
32 #define MCUXCLHMAC_SIZE_IN_CPUWORDS(size) ((((size) + sizeof(uint32_t) - 1u) / sizeof(uint32_t)))
33 
34 /* Workarea sizes */
35 #define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE (360u)
36 #define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE)
37 #define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE (360u)
38 #define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE)
39 #define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE (4u)
40 #define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE)
41 #define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE (168u)
42 #define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE)
43 
44 #define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE (360u)
45 #define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE)
46 
47 /* Context sizes */
48 #define MCUXCLHMAC_CONTEXT_SIZE_SW (572u)
49 #define MCUXCLHMAC_CONTEXT_SIZE_SW_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_CONTEXT_SIZE_SW)
50 #define MCUXCLHMAC_CONTEXT_SIZE_ELS (72u)
51 #define MCUXCLHMAC_CONTEXT_SIZE_ELS_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_CONTEXT_SIZE_ELS)
52 #define MCUXCLHMAC_MAX_CONTEXT_SIZE (572u)
53 #define MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_MAX_CONTEXT_SIZE)
54 
55 /* Mode descriptor sizes */
56 #define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE (48u)
57 #define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE)
58  /* mcuxClMac_MemoryConsumption */
62 
63 #endif /* MCUXCLHMAC_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00398.html b/components/els_pkc/doc/mcxn/html/a00398.html new file mode 100644 index 000000000..f800d9043 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00398.html @@ -0,0 +1,187 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Modes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClHmac_Modes.h File Reference
+
+
+ +

Mode descriptors for the mcuxClHmac component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxClMac_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + +

+Variables

const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS
 HMAC-SHA2-256 mode descriptor using ELS HW. More...
 
static mcuxClMac_Mode_t mcuxClMac_Mode_HMAC_SHA2_256_ELS
 HMAC-SHA2-256 mode using ELS HW. More...
 
+

Detailed Description

+

Mode descriptors for the mcuxClHmac component.

+

Variable Documentation

+ +

◆ mcuxClHmac_ModeDescriptor_SHA2_256_ELS

+ +
+
+ + + + +
const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS
+
+ +

HMAC-SHA2-256 mode descriptor using ELS HW.

+ +
+
+ +

◆ mcuxClMac_Mode_HMAC_SHA2_256_ELS

+ +
+
+ + + + + +
+ + + + +
mcuxClMac_Mode_t mcuxClMac_Mode_HMAC_SHA2_256_ELS
+ 		+static
+
+ +

HMAC-SHA2-256 mode using ELS HW.

+

The input buffer in will be modified by applying padding to it. The caller must ensure that the input buffer is large enough to hold this padding. The total buffer size including padding can be calculated using the macro MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH on the data size inLength.

+

Also note that mcuxClMac_Mode_HMAC_SHA2_256_ELS only works with keys loaded into coprocessor (see mcuxClKey for details).

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00398.js b/components/els_pkc/doc/mcxn/html/a00398.js new file mode 100644 index 000000000..1b99cea55 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00398.js @@ -0,0 +1,5 @@ +var a00398 = +[ + [ "mcuxClHmac_ModeDescriptor_SHA2_256_ELS", "a00398.html#a06144963f16c396f82dcab7f0a3bb0db", null ], + [ "mcuxClMac_Mode_HMAC_SHA2_256_ELS", "a00398.html#ad6bd4a8254a45bfc3f319c4177fd8d80", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00398_source.html b/components/els_pkc/doc/mcxn/html/a00398_source.html new file mode 100644 index 000000000..504c2d4f5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00398_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_Modes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClHmac_Modes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLHMAC_MODES_H_
20 #define MCUXCLHMAC_MODES_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 #include <mcuxClCore_Platform.h>
24 #include <mcuxCsslAnalysis.h>
25 #include <mcuxClMac_Types.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
48 extern const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS;
49 
62 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
63 static mcuxClMac_Mode_t mcuxClMac_Mode_HMAC_SHA2_256_ELS =
64  &mcuxClHmac_ModeDescriptor_SHA2_256_ELS;
65 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
66 
67 
68 #ifdef __cplusplus
69 } /* extern "C" */
70 #endif
71 
72 #endif /* MCUXCLHMAC_MODES_H_ */
mcuxClMac_Mode_t
const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
MAC mode/algorithm type.
Definition: mcuxClMac_Types.h:67
+
mcuxClMac_Mode_HMAC_SHA2_256_ELS
static mcuxClMac_Mode_t mcuxClMac_Mode_HMAC_SHA2_256_ELS
HMAC-SHA2-256 mode using ELS HW.
Definition: mcuxClHmac_Modes.h:63
+
mcuxClHmac_ModeDescriptor_SHA2_256_ELS
const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS
HMAC-SHA2-256 mode descriptor using ELS HW.
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
mcuxClMac_ModeDescriptor_t
struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
MAC mode/algorithm descriptor type.
Definition: mcuxClMac_Types.h:60
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00401.html b/components/els_pkc/doc/mcxn/html/a00401.html new file mode 100644 index 000000000..58f9370cb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00401.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClKey.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey.h File Reference
+
+
+ +

Top-level include file for the mcuxClKey component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClKey_Types.h>
+#include <mcuxClKey_Functions.h>
+#include <mcuxClKey_Constants.h>
+#include <mcuxClKey_MemoryConsumption.h>
+#include <mcuxClKey_ProtectionMechanisms.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00401_source.html b/components/els_pkc/doc/mcxn/html/a00401_source.html new file mode 100644 index 000000000..d3b55637b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00401_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClKey.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUXCLKEY_H_
23 #define MCUXCLKEY_H_
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxClKey_Types.h>
27 #include <mcuxClKey_Functions.h>
28 #include <mcuxClKey_Constants.h>
29 #include <mcuxClKey_MemoryConsumption.h>
30 #include <mcuxClKey_ProtectionMechanisms.h>
31 
32 #endif /* MCUXCLKEY_H_ */
mcuxClKey_MemoryConsumption.h
Defines the memory consumption for the mcuxClKey component All work area sizes in bytes are a multipl...
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxClKey_Constants.h
Constants for the mcuxClKey component.
+
mcuxClKey_Functions.h
Top-level API of the mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00404.html b/components/els_pkc/doc/mcxn/html/a00404.html new file mode 100644 index 000000000..29ee12a5d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00404.html @@ -0,0 +1,325 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClKey_Constants.h File Reference
+
+
+ +

Constants for the mcuxClKey component. +More...

+
#include <mcuxCsslAnalysis.h>
+#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLKEY_STATUS_OK
 Key operation successful. More...
 
#define MCUXCLKEY_STATUS_ERROR
 Error occured during Key operation. More...
 
#define MCUXCLKEY_STATUS_FAILURE
 Failure during execution. More...
 
#define MCUXCLKEY_STATUS_INVALID_INPUT
 Invalid input. More...
 
#define MCUXCLKEY_STATUS_FAULT_ATTACK
 Fault attack detected. More...
 
#define MCUXCLKEY_STATUS_CRC_NOT_OK
 CRC verification failed. More...
 
#define MCUXCLKEY_STATUS_NOT_SUPPORTED
 Functionality not supported. More...
 
#define MCUXCLKEY_LOADSTATUS_NOTLOADED
 Key not loaded. More...
 
#define MCUXCLKEY_LOADSTATUS_MEMORY
 Key is loaded to memory. More...
 
#define MCUXCLKEY_LOADSTATUS_COPRO
 Key is loaded to HW IP slot. More...
 
#define MCUXCLKEY_LOADSTATUS_KEEPLOADED
 Do not flush the key after the operation (for Symmetric keys only) More...
 
#define MCUXCLKEY_ALGO_ID_AES
 AES key. More...
 
#define MCUXCLKEY_ALGO_ID_RSA
 RSA key. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP
 ECC key using Short Weierstrass Curve over GF(p) More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M
 ECC key using Short Weierstrass Curve over GF(2^m) More...
 
#define MCUXCLKEY_ALGO_ID_ECC_MONTDH
 ECC key for MontDH key exchange scheme. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_EDDSA
 ECC key for EdDSA signature scheme. More...
 
#define MCUXCLKEY_ALGO_ID_HMAC
 HMAC key. More...
 
#define MCUXCLKEY_ALGO_ID_SM4
 SM4 key. More...
 
#define MCUXCLKEY_ALGO_ID_SM2
 SM2 key. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM
 ECC key using Short Weierstrass Curve over GF(p) with ephemeral custom domain parameters. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM
 ECC key using Short Weierstrass Curve over GF(p) with static custom domain parameters. More...
 
#define MCUXCLKEY_ALGO_ID_ALGO_MASK
 Mask for Algorithm. More...
 
#define MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY
 Symmetric key. More...
 
#define MCUXCLKEY_ALGO_ID_PUBLIC_KEY
 Public key. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY
 Private key. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT
 Private RSA key in CRT format. More...
 
#define MCUXCLKEY_ALGO_ID_KEY_PAIR
 Key pair. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA
 RSA key pair, with the private part in CRT format. More...
 
#define MCUXCLKEY_ALGO_ID_USAGE_MASK
 Mask for Key Usage. More...
 
#define MCUXCLKEY_SIZE_NOTUSED
 key length field is not used (e.g. ECC keys) More...
 
#define MCUXCLKEY_SIZE_128
 128 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_160
 160 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_192
 192 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_224
 224 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_256
 256 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_320
 320 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_384
 348 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_512
 512 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_521
 521 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_1024
 1024 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_2048
 2048 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_3072
 3072 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_4096
 4096 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_6144
 6144 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_8192
 8192 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_128_IN_WORDS
 128 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_160_IN_WORDS
 160 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_192_IN_WORDS
 192 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_224_IN_WORDS
 224 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_256_IN_WORDS
 256 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_320_IN_WORDS
 320 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_384_IN_WORDS
 348 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_512_IN_WORDS
 512 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_521_IN_WORDS
 521 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_1024_IN_WORDS
 1024 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_2048_IN_WORDS
 2048 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_3072_IN_WORDS
 3072 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_4096_IN_WORDS
 4096 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_6144_IN_WORDS
 6144 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_8192_IN_WORDS
 8192 bit key, size in words More...
 
#define MCUXCLKEY_WA_SIZE_MAX
 Define the max workarea size required for this component. More...
 
#define MCUXCLKEY_INVALID_KEYSLOT
 Define the value for an invalid key slot. More...
 
+

Detailed Description

+

Constants for the mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00404.js b/components/els_pkc/doc/mcxn/html/a00404.js new file mode 100644 index 000000000..da4b9fdf2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00404.js @@ -0,0 +1,66 @@ +var a00404 = +[ + [ "MCUXCLKEY_STATUS_OK", "a00786.html#ga3cac3b08cb53d2949698e19319010c49", null ], + [ "MCUXCLKEY_STATUS_ERROR", "a00786.html#gaad298a05e6e023bc251b91ad5173ac59", null ], + [ "MCUXCLKEY_STATUS_FAILURE", "a00786.html#gabcc2c3ef67df555b363b5bb51f71d83b", null ], + [ "MCUXCLKEY_STATUS_INVALID_INPUT", "a00786.html#gaf5c8b802949e1a7920cfdd65ec3fe42b", null ], + [ "MCUXCLKEY_STATUS_FAULT_ATTACK", "a00786.html#ga7be083c8ca459a7290b5cf7784c75469", null ], + [ "MCUXCLKEY_STATUS_CRC_NOT_OK", "a00786.html#gaa1223f9f839075cd078103d4129b5218", null ], + [ "MCUXCLKEY_STATUS_NOT_SUPPORTED", "a00786.html#gacb7a3820f23f7cc17d33498ab12e3b3c", null ], + [ "MCUXCLKEY_LOADSTATUS_NOTLOADED", "a00787.html#ga8ce719dd938dbdc0cf859fbb1e602a0e", null ], + [ "MCUXCLKEY_LOADSTATUS_MEMORY", "a00787.html#ga50a509b8aa4abb9219470b45a385c794", null ], + [ "MCUXCLKEY_LOADSTATUS_COPRO", "a00787.html#ga3ab5a0669a60ff9b617bad0aeac71d72", null ], + [ "MCUXCLKEY_LOADSTATUS_KEEPLOADED", "a00787.html#gafd80ca5f40ff2e3898358c26cdd2caab", null ], + [ "MCUXCLKEY_ALGO_ID_AES", "a00788.html#gaf342031191b667161f2db471ddbc1724", null ], + [ "MCUXCLKEY_ALGO_ID_RSA", "a00788.html#ga728c97658536b4430e2b0e2c7373f141", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP", "a00788.html#ga2270daa12f0592b07c5a657d3cc1ae87", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M", "a00788.html#ga77f445482782348f049443d35a21662e", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_MONTDH", "a00788.html#gaace809498ccbffd63bc29f2b6d3a8db3", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_EDDSA", "a00788.html#gacbfa2e595e1fb1c6152cb4587ea01346", null ], + [ "MCUXCLKEY_ALGO_ID_HMAC", "a00788.html#gadb9ccdf41fc6a4868a0db982a601e226", null ], + [ "MCUXCLKEY_ALGO_ID_SM4", "a00788.html#ga8edc6b9dbe321d4e8a7f0681c4109111", null ], + [ "MCUXCLKEY_ALGO_ID_SM2", "a00788.html#gad4879e15a76d3c52e08855d993ba252e", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM", "a00788.html#gad51657624280512bd92719790363d763", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM", "a00788.html#ga8de9456ab126f7227b1077462fbca3b4", null ], + [ "MCUXCLKEY_ALGO_ID_ALGO_MASK", "a00788.html#gaf933f3469276e89b07aa395f90e2d180", null ], + [ "MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY", "a00788.html#gaa4fb66afe4c13047acc47ebf6d69e16e", null ], + [ "MCUXCLKEY_ALGO_ID_PUBLIC_KEY", "a00788.html#ga59fde148cf2683ed4371524df7ae3f06", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY", "a00788.html#ga18dcc408cf88d59a8d55fcfd3efd3b75", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT", "a00788.html#gacc27c79457fc64101a84a110014f92e1", null ], + [ "MCUXCLKEY_ALGO_ID_KEY_PAIR", "a00788.html#ga73033441ba95ee2e3dd88a2d14f30bd5", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA", "a00788.html#gabe8f17c80217f51dd7833e97ca169eee", null ], + [ "MCUXCLKEY_ALGO_ID_USAGE_MASK", "a00788.html#gadb73c82af33ca9b97d8465c36defdd6a", null ], + [ "MCUXCLKEY_SIZE_NOTUSED", "a00789.html#gaba60c5f0fa5e1bfb5299f1e6814c919f", null ], + [ "MCUXCLKEY_SIZE_128", "a00789.html#gab0cb72bbcdd5736790b183a6e49f8eb8", null ], + [ "MCUXCLKEY_SIZE_160", "a00789.html#gac82b7eaeeb5f153630b71bbd59a7e515", null ], + [ "MCUXCLKEY_SIZE_192", "a00789.html#ga9871dfc831af8af21381f0f08007efe8", null ], + [ "MCUXCLKEY_SIZE_224", "a00789.html#gaaeee050febe3515ef1369c27a77d8a79", null ], + [ "MCUXCLKEY_SIZE_256", "a00789.html#ga16f615ca2af0dcc6dad9930cbfc21b89", null ], + [ "MCUXCLKEY_SIZE_320", "a00789.html#gad3a6f649d8e9b10a97bc0c04bc353718", null ], + [ "MCUXCLKEY_SIZE_384", "a00789.html#ga0d300ed35264eccec76e71201613f065", null ], + [ "MCUXCLKEY_SIZE_512", "a00789.html#ga7dd4afbbc02c2612af98796af352b875", null ], + [ "MCUXCLKEY_SIZE_521", "a00789.html#ga704db03c84c8e46314089d8b052ba030", null ], + [ "MCUXCLKEY_SIZE_1024", "a00789.html#gadd198add7df214eed81dbe316b150d3d", null ], + [ "MCUXCLKEY_SIZE_2048", "a00789.html#gacaf2b0cf43dc21e81e653d58be8320f6", null ], + [ "MCUXCLKEY_SIZE_3072", "a00789.html#gacdbba9c49cef3b7a47dc9570bdc72115", null ], + [ "MCUXCLKEY_SIZE_4096", "a00789.html#ga44cf02ee5c2944fa72ec10c3be54642a", null ], + [ "MCUXCLKEY_SIZE_6144", "a00789.html#gaf8c45542e3fe919a3dddc532b44cecd2", null ], + [ "MCUXCLKEY_SIZE_8192", "a00789.html#gaaee55d800a45f767592c0071e5fca0d8", null ], + [ "MCUXCLKEY_SIZE_128_IN_WORDS", "a00789.html#ga46a4709b4a513ab6676ee24944d4d2f0", null ], + [ "MCUXCLKEY_SIZE_160_IN_WORDS", "a00789.html#ga468b330bc005b81ccfe88e11171f391f", null ], + [ "MCUXCLKEY_SIZE_192_IN_WORDS", "a00789.html#gaeab881403cb2a9ade4906fda695a086e", null ], + [ "MCUXCLKEY_SIZE_224_IN_WORDS", "a00789.html#gaeb7c6bde09543bd3a45fc33c8e5beb3a", null ], + [ "MCUXCLKEY_SIZE_256_IN_WORDS", "a00789.html#ga6bea535c9b507d50ff14aa2dfb1ddf5b", null ], + [ "MCUXCLKEY_SIZE_320_IN_WORDS", "a00789.html#ga979dec395bea975d81634d14026159e4", null ], + [ "MCUXCLKEY_SIZE_384_IN_WORDS", "a00789.html#ga3ad1e0304140bdf547a93d45cbd7a5ff", null ], + [ "MCUXCLKEY_SIZE_512_IN_WORDS", "a00789.html#gacfa3ec1113e89c824bc9d3aaad76d04e", null ], + [ "MCUXCLKEY_SIZE_521_IN_WORDS", "a00789.html#gadaea316eb7a4a8b0b59e9f1879cae923", null ], + [ "MCUXCLKEY_SIZE_1024_IN_WORDS", "a00789.html#ga0c357e26537083ca9164aab3820b4ca7", null ], + [ "MCUXCLKEY_SIZE_2048_IN_WORDS", "a00789.html#gae48b497b883fa63ef84465fcb4fb3ced", null ], + [ "MCUXCLKEY_SIZE_3072_IN_WORDS", "a00789.html#gabbd3d5e04feb2c2f43a94d238cfca369", null ], + [ "MCUXCLKEY_SIZE_4096_IN_WORDS", "a00789.html#gada1e24d3f9d8207287333085df1712dd", null ], + [ "MCUXCLKEY_SIZE_6144_IN_WORDS", "a00789.html#ga4de61cf46c4577ba0019f92814cbf804", null ], + [ "MCUXCLKEY_SIZE_8192_IN_WORDS", "a00789.html#ga6c05f57184c5dd0da0cbb44ba28ce0f8", null ], + [ "MCUXCLKEY_WA_SIZE_MAX", "a00785.html#ga617470bb5f7da932c271545154fe31b7", null ], + [ "MCUXCLKEY_INVALID_KEYSLOT", "a00785.html#ga016a12d0d9ac976c44d4cf1f8a493763", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00404_source.html b/components/els_pkc/doc/mcxn/html/a00404_source.html new file mode 100644 index 000000000..c517d244e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00404_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLKEY_CONSTANTS_H_
20 #define MCUXCLKEY_CONSTANTS_H_
21 
22 #include <mcuxCsslAnalysis.h>
23 #include <mcuxClConfig.h> // Exported features flags header
24 
25 /**********************************************
26  * CONSTANTS
27  **********************************************/
39 #define MCUXCLKEY_STATUS_OK ((mcuxClKey_Status_t) 0x07772E03u)
40 #define MCUXCLKEY_STATUS_ERROR ((mcuxClKey_Status_t) 0x07775330u)
41 #define MCUXCLKEY_STATUS_FAILURE ((mcuxClKey_Status_t) 0x07775334u)
42 #define MCUXCLKEY_STATUS_INVALID_INPUT ((mcuxClKey_Status_t) 0x07775338u)
43 #define MCUXCLKEY_STATUS_FAULT_ATTACK ((mcuxClKey_Status_t) 0x0777F0F0u)
44 #define MCUXCLKEY_STATUS_CRC_NOT_OK ((mcuxClKey_Status_t) 0x077753FCu)
45 #define MCUXCLKEY_STATUS_NOT_SUPPORTED ((mcuxClKey_Status_t) 0x07775370u)
46 
53 #define MCUXCLKEY_LOADSTATUS_NOTLOADED 0x0000u
54 #define MCUXCLKEY_LOADSTATUS_MEMORY 0x0001u
55 #define MCUXCLKEY_LOADSTATUS_COPRO 0x0002u
56 #define MCUXCLKEY_LOADSTATUS_KEEPLOADED 0x8000u
57 
60 /* Define algorithm IDs */
61 
67 #define MCUXCLKEY_ALGO_ID_AES 0x0F01u
68 #define MCUXCLKEY_ALGO_ID_RSA 0x0E02u
69 #define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP 0x0D03u
70 #define MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M 0x0C04u
71 #define MCUXCLKEY_ALGO_ID_ECC_MONTDH 0x0B05u
72 #define MCUXCLKEY_ALGO_ID_ECC_EDDSA 0x0A06u
73 #define MCUXCLKEY_ALGO_ID_HMAC 0x0907u
74 #define MCUXCLKEY_ALGO_ID_SM4 0x0808u
75 #define MCUXCLKEY_ALGO_ID_SM2 0x0809u
76 #define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM 0x0709u
77 #define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM 0x060Au
78 #define MCUXCLKEY_ALGO_ID_ALGO_MASK 0x0FFFu
79 
80 #define MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY 0x0000u
81 #define MCUXCLKEY_ALGO_ID_PUBLIC_KEY 0x8000u
82 #define MCUXCLKEY_ALGO_ID_PRIVATE_KEY 0x4000u
83 #define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT 0x6000u
84 #define MCUXCLKEY_ALGO_ID_KEY_PAIR 0xC000u
85 #define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA 0xE000u
86 
87 #define MCUXCLKEY_ALGO_ID_USAGE_MASK 0xF000u
88 
90 /* Define key sizes */
91 
97 #define MCUXCLKEY_SIZE_NOTUSED 0u
98 #define MCUXCLKEY_SIZE_128 16u
99 #define MCUXCLKEY_SIZE_160 20u
100 #define MCUXCLKEY_SIZE_192 24u
101 #define MCUXCLKEY_SIZE_224 28u
102 #define MCUXCLKEY_SIZE_256 32u
103 #define MCUXCLKEY_SIZE_320 40u
104 #define MCUXCLKEY_SIZE_384 48u
105 #define MCUXCLKEY_SIZE_512 64u
106 #define MCUXCLKEY_SIZE_521 66u
107 #define MCUXCLKEY_SIZE_1024 1024u
108 #define MCUXCLKEY_SIZE_2048 2048u
109 #define MCUXCLKEY_SIZE_3072 3072u
110 #define MCUXCLKEY_SIZE_4096 4096u
111 #define MCUXCLKEY_SIZE_6144 6144u
112 #define MCUXCLKEY_SIZE_8192 8192u
113 
114 // TODO CLNS-6135: replace these divides by a macro that ensures rounding up
115 #define MCUXCLKEY_SIZE_128_IN_WORDS (MCUXCLKEY_SIZE_128 / sizeof(uint32_t))
116 #define MCUXCLKEY_SIZE_160_IN_WORDS (MCUXCLKEY_SIZE_160 / sizeof(uint32_t))
117 #define MCUXCLKEY_SIZE_192_IN_WORDS (MCUXCLKEY_SIZE_192 / sizeof(uint32_t))
118 #define MCUXCLKEY_SIZE_224_IN_WORDS (MCUXCLKEY_SIZE_224 / sizeof(uint32_t))
119 #define MCUXCLKEY_SIZE_256_IN_WORDS (MCUXCLKEY_SIZE_256 / sizeof(uint32_t))
120 #define MCUXCLKEY_SIZE_320_IN_WORDS (MCUXCLKEY_SIZE_320 / sizeof(uint32_t))
121 #define MCUXCLKEY_SIZE_384_IN_WORDS (MCUXCLKEY_SIZE_384 / sizeof(uint32_t))
122 #define MCUXCLKEY_SIZE_512_IN_WORDS (MCUXCLKEY_SIZE_512 / sizeof(uint32_t))
123 #define MCUXCLKEY_SIZE_521_IN_WORDS ((MCUXCLKEY_SIZE_521 + sizeof(uint32_t) - 1u) / sizeof(uint32_t))
124 #define MCUXCLKEY_SIZE_1024_IN_WORDS (MCUXCLKEY_SIZE_1024 / (sizeof(uint32_t) * 8u))
125 #define MCUXCLKEY_SIZE_2048_IN_WORDS (MCUXCLKEY_SIZE_2048 / (sizeof(uint32_t) * 8u))
126 #define MCUXCLKEY_SIZE_3072_IN_WORDS (MCUXCLKEY_SIZE_3072 / (sizeof(uint32_t) * 8u))
127 #define MCUXCLKEY_SIZE_4096_IN_WORDS (MCUXCLKEY_SIZE_4096 / (sizeof(uint32_t) * 8u))
128 #define MCUXCLKEY_SIZE_6144_IN_WORDS (MCUXCLKEY_SIZE_6144 / (sizeof(uint32_t) * 8u))
129 #define MCUXCLKEY_SIZE_8192_IN_WORDS (MCUXCLKEY_SIZE_8192 / (sizeof(uint32_t) * 8u))
130 
138 #define MCUXCLKEY_WA_SIZE_MAX 0U
139 
144 #define MCUXCLKEY_INVALID_KEYSLOT 0xFFu
145 
146 #endif /* MCUXCLKEY_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00407.html b/components/els_pkc/doc/mcxn/html/a00407.html new file mode 100644 index 000000000..f4ce2d3f8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00407.html @@ -0,0 +1,164 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClKey_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClKey component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClKey_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Buffer.h>
+#include <mcuxClEls.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClKey_Status_t mcuxClKey_init (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Type_t type, mcuxCl_InputBuffer_t pKeyData, uint32_t keyDataLength)
 Initializes a key handle. More...
 
mcuxClKey_Status_t mcuxClKey_linkKeyPair (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
 Establishes a key pair link between a private and public key handle. More...
 
mcuxClKey_Status_t mcuxClKey_setProtection (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Protection_t protection, mcuxCl_Buffer_t pAuxData, mcuxClKey_Handle_t parentKey)
 Configures they protection mechanism for to the given key handle. More...
 
mcuxClKey_Status_t mcuxClKey_loadCopro (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t dstSlot)
 Load key into destination key slot of a coprocessor. More...
 
mcuxClKey_Status_t mcuxClKey_loadMemory (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t *dstData)
 Load key into destination memory buffer. More...
 
mcuxClKey_Status_t mcuxClKey_flush (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key)
 Flush key from destination which can be a key slot of coprocessor or memory buffer. More...
 
mcuxClKey_Status_t mcuxClKey_setKeyproperties (mcuxClKey_Handle_t key, mcuxClEls_KeyProp_t *key_properties)
 Set the requested key properties of the destination key. More...
 
+

Detailed Description

+

Top-level API of the mcuxClKey component.

+

It is capable to load and flush keys into memory locations or coprocessors.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00407.js b/components/els_pkc/doc/mcxn/html/a00407.js new file mode 100644 index 000000000..e1ae12223 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00407.js @@ -0,0 +1,10 @@ +var a00407 = +[ + [ "mcuxClKey_init", "a00790.html#ga8c6e891b1f7f973dbdccfe0f2a713142", null ], + [ "mcuxClKey_linkKeyPair", "a00790.html#gadac5d6a29e1a0dba2b418b98e4ccd0ee", null ], + [ "mcuxClKey_setProtection", "a00790.html#ga761180099785b36b6d5a6014cae54bb8", null ], + [ "mcuxClKey_loadCopro", "a00790.html#ga616ead4a2aaab2d0ae5502ba52315fca", null ], + [ "mcuxClKey_loadMemory", "a00790.html#gac4ec3d39748fc018dfb50316d2c51490", null ], + [ "mcuxClKey_flush", "a00790.html#ga60a86766cba40477651948cfa55eb7cd", null ], + [ "mcuxClKey_setKeyproperties", "a00790.html#gab1586a462e51711691901aa099f8b556", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00407_source.html b/components/els_pkc/doc/mcxn/html/a00407_source.html new file mode 100644 index 000000000..8e372ca7c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00407_source.html @@ -0,0 +1,144 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLKEY_FUNCTIONS_H_
21 #define MCUXCLKEY_FUNCTIONS_H_
22 
23 #include <mcuxClConfig.h> // Exported features flags header
24 #include <mcuxClSession.h>
25 #include <mcuxClSession_Types.h>
26 
27 #include <mcuxClKey_Types.h>
28 
29 #include <mcuxCsslFlowProtection.h>
30 #include <mcuxClCore_FunctionIdentifiers.h>
31 #include <mcuxClCore_Buffer.h>
32 #include <mcuxClEls.h>
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /**********************************************
39  * FUNCTIONS
40  **********************************************/
41 
77 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_init)
78 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_init(
79  mcuxClSession_Handle_t pSession,
80  mcuxClKey_Handle_t key,
81  mcuxClKey_Type_t type,
82  mcuxCl_InputBuffer_t pKeyData,
83  uint32_t keyDataLength
84 );
85 
102 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_linkKeyPair)
103 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_linkKeyPair(
104  mcuxClSession_Handle_t pSession,
105  mcuxClKey_Handle_t privKey,
106  mcuxClKey_Handle_t pubKey
107 );
108 
127 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_setProtection)
128 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setProtection(
129  mcuxClSession_Handle_t pSession,
130  mcuxClKey_Handle_t key,
131  mcuxClKey_Protection_t protection,
132  mcuxCl_Buffer_t pAuxData,
133  mcuxClKey_Handle_t parentKey
134 );
135 
152 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_loadCopro)
153 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadCopro(
154  mcuxClSession_Handle_t pSession,
155  mcuxClKey_Handle_t key,
156  uint32_t dstSlot
157 );
158 
175 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_loadMemory)
176 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadMemory(
177  mcuxClSession_Handle_t pSession,
178  mcuxClKey_Handle_t key,
179  uint32_t * dstData
180 );
181 
197 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_flush)
198 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_flush(
199  mcuxClSession_Handle_t pSession,
200  mcuxClKey_Handle_t key
201 );
202 
203 
204 
220 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_setKeyproperties)
221 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setKeyproperties(
222  mcuxClKey_Handle_t key,
223  mcuxClEls_KeyProp_t * key_properties
224 );
225 
226 
227 
228 
229 
230  /* mcuxClKey_Functions */
234 
235 #ifdef __cplusplus
236 } /* extern "C" */
237 #endif
238 
239 #endif /* MCUXCLKEY_FUNCTIONS_H_ */
mcuxClEls.h
Top-level include file for the ELS driver.
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClKey_Status_t
uint32_t mcuxClKey_Status_t
Type for Key component error codes.
Definition: mcuxClKey_Types.h:47
+
mcuxClKey_setProtection
mcuxClKey_Status_t mcuxClKey_setProtection(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Protection_t protection, mcuxCl_Buffer_t pAuxData, mcuxClKey_Handle_t parentKey)
Configures they protection mechanism for to the given key handle.
+
mcuxClKey_setKeyproperties
mcuxClKey_Status_t mcuxClKey_setKeyproperties(mcuxClKey_Handle_t key, mcuxClEls_KeyProp_t *key_properties)
Set the requested key properties of the destination key.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
mcuxClKey_Protection_t
const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
Key protection mechanism type.
Definition: mcuxClKey_Types.h:141
+
mcuxClKey_flush
mcuxClKey_Status_t mcuxClKey_flush(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key)
Flush key from destination which can be a key slot of coprocessor or memory buffer.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClEls_KeyProp_t
Type for ELS key store key properties.
Definition: mcuxClEls_Types.h:224
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClKey_loadMemory
mcuxClKey_Status_t mcuxClKey_loadMemory(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t *dstData)
Load key into destination memory buffer.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClKey_loadCopro
mcuxClKey_Status_t mcuxClKey_loadCopro(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t dstSlot)
Load key into destination key slot of a coprocessor.
+
mcuxClKey_linkKeyPair
mcuxClKey_Status_t mcuxClKey_linkKeyPair(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
Establishes a key pair link between a private and public key handle.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxClKey_init
mcuxClKey_Status_t mcuxClKey_init(mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Type_t type, mcuxCl_InputBuffer_t pKeyData, uint32_t keyDataLength)
Initializes a key handle.
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00410.html b/components/els_pkc/doc/mcxn/html/a00410.html new file mode 100644 index 000000000..c3a0d1f50 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00410.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClKey_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClKey_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClKey component All work area sizes in bytes are a multiple of CPU wordsize. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLKEY_DESCRIPTOR_SIZE
 
+#define MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS
 
+#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE
 
+#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE_IN_WORDS
 
+#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE
 
+#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClKey component All work area sizes in bytes are a multiple of CPU wordsize.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00410.js b/components/els_pkc/doc/mcxn/html/a00410.js new file mode 100644 index 000000000..197a60af5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00410.js @@ -0,0 +1,9 @@ +var a00410 = +[ + [ "MCUXCLKEY_DESCRIPTOR_SIZE", "a00791.html#ga2b9695046f1c43593266896742ce3e8f", null ], + [ "MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS", "a00791.html#ga738fd85c6dc17cc4209d08e940d57775", null ], + [ "MCUXCLKEY_TYPEDESCRIPTOR_SIZE", "a00791.html#gafa477e27c0893deffea7f8f71ddb8925", null ], + [ "MCUXCLKEY_TYPEDESCRIPTOR_SIZE_IN_WORDS", "a00791.html#ga879c5be1d91cd1c7816fe5b5cefb6549", null ], + [ "MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE", "a00791.html#gaef10bc9f41b3b52769460161840fb082", null ], + [ "MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS", "a00791.html#ga0cc0a564e13bd274c94afa281ed495b7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00410_source.html b/components/els_pkc/doc/mcxn/html/a00410_source.html new file mode 100644 index 000000000..84867a909 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00410_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClKey_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLKEY_MEMORYCONSUMPTION_H_
20 #define MCUXCLKEY_MEMORYCONSUMPTION_H_
21 
29 #define MCUXCLKEY_DESCRIPTOR_SIZE (56u)
30 #define MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_DESCRIPTOR_SIZE / sizeof(uint32_t))
31 
32 #define MCUXCLKEY_TYPEDESCRIPTOR_SIZE (12u)
33 #define MCUXCLKEY_TYPEDESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_TYPEDESCRIPTOR_SIZE / sizeof(uint32_t))
34 
35 #define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE (12u)
36 #define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE / sizeof(uint32_t))
37 
38  /* mcuxClKey_MemoryConsumption */
42 
43 #endif /* MCUXCLKEY_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00413_source.html b/components/els_pkc/doc/mcxn/html/a00413_source.html new file mode 100644 index 000000000..df81d748a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00413_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClKey_ProtectionMechanisms.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_ProtectionMechanisms.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLKEY_PROTECTIONMECHANISMS_H_
20 #define MCUXCLKEY_PROTECTIONMECHANISMS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 #include <mcuxClKey_Types.h>
24 #include <mcuxCsslAnalysis.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ")
31 
32 
50 extern const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None;
51 
55 static const mcuxClKey_Protection_t mcuxClKey_Protection_None =
56  &mcuxClKey_ProtectionDescriptor_None;
57 
62 extern const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf;
63 
67 static const mcuxClKey_Protection_t mcuxClKey_Protection_Ckdf =
68  &mcuxClKey_ProtectionDescriptor_Ckdf;
69 
70 
71 
72 
75 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
76 
77 #ifdef __cplusplus
78 } /* extern "C" */
79 #endif
80 
81 #endif /* MCUXCLKEY_PROTECTIONMECHANISMS_H_ */
82 
mcuxClKey_ProtectionDescriptor_Ckdf
const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf
Key protection descriptor for using CKDF based key protection This protection mechanism cannot be use...
+
mcuxClKey_Protection_Ckdf
static const mcuxClKey_Protection_t mcuxClKey_Protection_Ckdf
CKDF key protection.
Definition: mcuxClKey_ProtectionMechanisms.h:67
+
mcuxClKey_ProtectionDescriptor_None
const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None
Key protection descriptor for using no key protection.
+
mcuxClKey_Protection_None
static const mcuxClKey_Protection_t mcuxClKey_Protection_None
No key protection.
Definition: mcuxClKey_ProtectionMechanisms.h:55
+
mcuxClKey_Protection_t
const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
Key protection mechanism type.
Definition: mcuxClKey_Types.h:141
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxClKey_ProtectionDescriptor_t
struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t
Key protection mechanism descriptor type.
Definition: mcuxClKey_Types.h:134
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00416.html b/components/els_pkc/doc/mcxn/html/a00416.html new file mode 100644 index 000000000..bf1de8da0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00416.html @@ -0,0 +1,180 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
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+
+ +
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+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClKey_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClKey component. +More...

+
#include <stdint.h>
+#include <stdbool.h>
+#include <mcuxClConfig.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClKey_Status_t
 Type for Key component error codes. More...
 
typedef uint16_t mcuxClKey_AlgorithmId_t
 Type for algorithm based key id. More...
 
typedef uint32_t mcuxClKey_Size_t
 Type for algorithm based key size. More...
 
typedef mcuxClKey_Status_t mcuxClKey_Status_Protected_t
 Deprecated type for Key component error codes, returned by functions with code-flow protection. More...
 
typedef struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t
 Key descriptor type. More...
 
typedef mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
 Key handle type. More...
 
typedef struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
 Key type descriptor type. More...
 
typedef const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
 Key type handle type. More...
 
typedef mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t
 Custom key type handle type. More...
 
typedef struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t
 Key protection mechanism descriptor type. More...
 
typedef const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
 Key protection mechanism type. More...
 
typedef struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t
 Key generation descriptor type. More...
 
typedef const mcuxClKey_GenerationDescriptor_t *const mcuxClKey_Generation_t
 Key generation type. More...
 
+

Detailed Description

+

Type definitions for the mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00416.js b/components/els_pkc/doc/mcxn/html/a00416.js new file mode 100644 index 000000000..584e59c9e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00416.js @@ -0,0 +1,16 @@ +var a00416 = +[ + [ "mcuxClKey_Status_t", "a00793.html#gaa19905c3963849a56ee26a9b0e5013f5", null ], + [ "mcuxClKey_AlgorithmId_t", "a00793.html#ga322cbacb57f10aa6cb6731d64d4e64e3", null ], + [ "mcuxClKey_Size_t", "a00793.html#ga90c030f08081016123496c56021b9bab", null ], + [ "mcuxClKey_Status_Protected_t", "a00793.html#ga9886ee2d82f96093ad0a39385452cdfb", null ], + [ "mcuxClKey_Descriptor_t", "a00793.html#ga1b7557c7a8892e65d43b90f8d6226d6a", null ], + [ "mcuxClKey_Handle_t", "a00793.html#gafe84fa2aa66094f542164e0627a54c5d", null ], + [ "mcuxClKey_TypeDescriptor_t", "a00793.html#gae9a4d21e5a5239fd0ef48978a3774a89", null ], + [ "mcuxClKey_Type_t", "a00793.html#ga9ea75aa8fe6ddb914d91b170bb5d8be5", null ], + [ "mcuxClKey_CustomType_t", "a00793.html#ga4249d6ccc1dab6d15b46270da3c3d6d4", null ], + [ "mcuxClKey_ProtectionDescriptor_t", "a00793.html#ga1c51acf51723d52dbcdc1a0f80f98572", null ], + [ "mcuxClKey_Protection_t", "a00793.html#gab16fa58359f9994921f5d4a58c597c66", null ], + [ "mcuxClKey_GenerationDescriptor_t", "a00793.html#gaad2bc2272e961dd28dba4697d9287a14", null ], + [ "mcuxClKey_Generation_t", "a00793.html#gabb1e565ab474265cf8b53be6d9a1f758", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00416_source.html b/components/els_pkc/doc/mcxn/html/a00416_source.html new file mode 100644 index 000000000..04985f934 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00416_source.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLKEY_TYPES_H_
20 #define MCUXCLKEY_TYPES_H_
21 
22 #include <stdint.h>
23 #include <stdbool.h>
24 #include <mcuxClConfig.h> // Exported features flags header
25 #include <mcuxCsslAnalysis.h>
26 #include <mcuxCsslFlowProtection.h>
27 #include <mcuxClCore_FunctionIdentifiers.h>
28 #include <mcuxClCore_Buffer.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 /**********************************************
35  * TYPEDEFS
36  **********************************************/
47 typedef uint32_t mcuxClKey_Status_t;
48 
52 typedef uint16_t mcuxClKey_AlgorithmId_t;
53 
57 typedef uint32_t mcuxClKey_Size_t;
58 
62 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_Status_Protected_t;
63 
64 /* Forward declaration */
65 struct mcuxClKey_Protection;
66 
73 struct mcuxClKey_Descriptor;
74 
81 typedef struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t;
82 
88 typedef mcuxClKey_Descriptor_t * const mcuxClKey_Handle_t;
89 
96 struct mcuxClKey_TypeDescriptor;
97 
104 typedef struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t;
105 
111 typedef const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t;
112 
118 typedef mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t;
119 
126 struct mcuxClKey_ProtectionDescriptor;
127 
134 typedef struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t;
135 
141 typedef const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t;
142 
143 
150 struct mcuxClKey_GenerationDescriptor;
151 
158 typedef struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t;
159 
165 typedef const mcuxClKey_GenerationDescriptor_t * const mcuxClKey_Generation_t;
166 
167 
168 
169  /* mcuxClKey_Types */
173 
174 #ifdef __cplusplus
175 } /* extern "C" */
176 #endif
177 
178 #endif /* MCUXCLKEY_TYPES_H_ */
mcuxClKey_Status_Protected_t
mcuxClKey_Status_t mcuxClKey_Status_Protected_t
Deprecated type for Key component error codes, returned by functions with code-flow protection.
Definition: mcuxClKey_Types.h:62
+
mcuxClKey_TypeDescriptor_t
struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
Key type descriptor type.
Definition: mcuxClKey_Types.h:104
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey_AlgorithmId_t
uint16_t mcuxClKey_AlgorithmId_t
Type for algorithm based key id.
Definition: mcuxClKey_Types.h:52
+
mcuxClKey_GenerationDescriptor_t
struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t
Key generation descriptor type.
Definition: mcuxClKey_Types.h:158
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClKey_Descriptor_t
struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t
Key descriptor type.
Definition: mcuxClKey_Types.h:81
+
mcuxClKey_CustomType_t
mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t
Custom key type handle type.
Definition: mcuxClKey_Types.h:118
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClKey_Status_t
uint32_t mcuxClKey_Status_t
Type for Key component error codes.
Definition: mcuxClKey_Types.h:47
+
mcuxClKey_Generation_t
const mcuxClKey_GenerationDescriptor_t *const mcuxClKey_Generation_t
Key generation type.
Definition: mcuxClKey_Types.h:165
+
mcuxClKey_Size_t
uint32_t mcuxClKey_Size_t
Type for algorithm based key size.
Definition: mcuxClKey_Types.h:57
+
mcuxClKey_Protection_t
const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
Key protection mechanism type.
Definition: mcuxClKey_Types.h:141
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClKey_ProtectionDescriptor_t
struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t
Key protection mechanism descriptor type.
Definition: mcuxClKey_Types.h:134
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00419.html b/components/els_pkc/doc/mcxn/html/a00419.html new file mode 100644 index 000000000..d5b22b5df --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00419.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClMac.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac.h File Reference
+
+
+ +

Top-level include file for the mcuxClMac component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClMac_Types.h>
+#include <mcuxClMac_Functions.h>
+#include <mcuxClMac_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClMac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00419_source.html b/components/els_pkc/doc/mcxn/html/a00419_source.html new file mode 100644 index 000000000..5cd802fc9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00419_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClMac.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020, 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
38 #ifndef MCUXCLMAC_H_
39 #define MCUXCLMAC_H_
40 
41 #include <mcuxClConfig.h> // Exported features flags header
42 #include <mcuxClMac_Types.h>
43 #include <mcuxClMac_Functions.h>
44 #include <mcuxClMac_Constants.h>
45 
46 #endif /* MCUXCLMAC_H_ */
mcuxClMac_Constants.h
Constants and status codes for the mcuxClMac component.
+
mcuxClMac_Functions.h
Top-level API of the mcuxClMac component.
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00422.html b/components/els_pkc/doc/mcxn/html/a00422.html new file mode 100644 index 000000000..62d13ebe9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00422.html @@ -0,0 +1,153 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMac_Constants.h File Reference
+
+
+ +

Constants and status codes for the mcuxClMac component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLMAC_STATUS_ERROR
 
+#define MCUXCLMAC_STATUS_FAILURE
 
+#define MCUXCLMAC_STATUS_INVALID_PARAM
 
+#define MCUXCLMAC_STATUS_FAULT_ATTACK
 
+#define MCUXCLMAC_STATUS_OK
 
+#define MCUXCLMAC_STATUS_COMPARE_NOK
 
+

Detailed Description

+

Constants and status codes for the mcuxClMac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00422.js b/components/els_pkc/doc/mcxn/html/a00422.js new file mode 100644 index 000000000..c82bf3cfb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00422.js @@ -0,0 +1,9 @@ +var a00422 = +[ + [ "MCUXCLMAC_STATUS_ERROR", "a00795.html#ga29a0556d236921ec9e6680cd049f784b", null ], + [ "MCUXCLMAC_STATUS_FAILURE", "a00795.html#gaeee9d7aded8807ac014d1030847457a2", null ], + [ "MCUXCLMAC_STATUS_INVALID_PARAM", "a00795.html#ga8eb86baa218d3f14c65c4cf1fd4a9a6b", null ], + [ "MCUXCLMAC_STATUS_FAULT_ATTACK", "a00795.html#ga025cf49de0fa3225a6d15fd972bf3c64", null ], + [ "MCUXCLMAC_STATUS_OK", "a00795.html#ga7df50ebdaad50cfe8661c930df6c43df", null ], + [ "MCUXCLMAC_STATUS_COMPARE_NOK", "a00795.html#ga322f2ecd934013fbc12b609d7f92b49f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00422_source.html b/components/els_pkc/doc/mcxn/html/a00422_source.html new file mode 100644 index 000000000..e1b5819ff --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00422_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLMAC_CONSTANTS_H_
20 #define MCUXCLMAC_CONSTANTS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
30 /* TODO CLNS-8684: Unionize and describe return codes */
31 #define MCUXCLMAC_STATUS_ERROR ((mcuxClMac_Status_t) 0x08885330u)
32 #define MCUXCLMAC_STATUS_FAILURE ((mcuxClMac_Status_t) 0x08885334u)
33 #define MCUXCLMAC_STATUS_INVALID_PARAM ((mcuxClMac_Status_t) 0x088853F8u)
34 #define MCUXCLMAC_STATUS_FAULT_ATTACK ((mcuxClMac_Status_t) 0x0888F0F0u)
35 #define MCUXCLMAC_STATUS_OK ((mcuxClMac_Status_t) 0x08882E03u)
36 #define MCUXCLMAC_STATUS_COMPARE_NOK ((mcuxClMac_Status_t) 0x088853FCu)
37 
39 #endif /* MCUXCLMAC_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00425.html b/components/els_pkc/doc/mcxn/html/a00425.html new file mode 100644 index 000000000..3a2ec5353 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00425.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClMac_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClMac component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClKey_Types.h>
+#include <mcuxClMac_Types.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Functions

mcuxClMac_Status_t mcuxClMac_compute (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
 One-shot message authentication code (MAC) computation function. More...
 
mcuxClMac_Status_t mcuxClMac_init (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode)
 Initialization for a multipart MAC computation. More...
 
mcuxClMac_Status_t mcuxClMac_process (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength)
 Data processing for a multipart MAC computation. More...
 
mcuxClMac_Status_t mcuxClMac_finish (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
 Finalize a MAC generation for a multipart MAC computation. More...
 
+

Detailed Description

+

Top-level API of the mcuxClMac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00425.js b/components/els_pkc/doc/mcxn/html/a00425.js new file mode 100644 index 000000000..aacc28bed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00425.js @@ -0,0 +1,7 @@ +var a00425 = +[ + [ "mcuxClMac_compute", "a00797.html#gad2fe8b5e17f2b468fbe8a61f8fee5400", null ], + [ "mcuxClMac_init", "a00798.html#ga803bd7822372bdca8dfd0c81b5db96eb", null ], + [ "mcuxClMac_process", "a00798.html#ga2749e40209d4308f21ebe761485d4d56", null ], + [ "mcuxClMac_finish", "a00798.html#ga9d66c6e242ff75b6ff4826fdcb784e08", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00425_source.html b/components/els_pkc/doc/mcxn/html/a00425_source.html new file mode 100644 index 000000000..d9f8d44de --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00425_source.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLMAC_FUNCTIONS_H_
20 #define MCUXCLMAC_FUNCTIONS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 #include <mcuxClSession_Types.h>
24 #include <mcuxClKey_Types.h>
25 #include <mcuxClMac_Types.h>
26 #include <mcuxClCore_Platform.h>
27 #include <mcuxClCore_Buffer.h>
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
40 /****************************************************************************/
41 /* ONESHOT */
42 /****************************************************************************/
43 
84 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_compute)
85 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_compute(
86  mcuxClSession_Handle_t session,
87  mcuxClKey_Handle_t key,
88  mcuxClMac_Mode_t mode,
89  mcuxCl_InputBuffer_t pIn,
90  uint32_t inLength,
91  mcuxCl_Buffer_t pMac,
92  uint32_t * const pMacLength
93 );
94  /* mcuxClMac_OneShot */
98 
99 
100 /****************************************************************************/
101 /* MULTIPART */
102 /****************************************************************************/
103 
141 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_init)
142 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_init(
143  mcuxClSession_Handle_t session,
144  mcuxClMac_Context_t * const pContext,
145  mcuxClKey_Handle_t key,
146  mcuxClMac_Mode_t mode
147 ); /* init */
148 
180 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_process)
181 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_process(
182  mcuxClSession_Handle_t session,
183  mcuxClMac_Context_t * const pContext,
184  mcuxCl_InputBuffer_t pIn,
185  uint32_t inLength
186 ); /* update */
187 
221 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_finish)
222 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_finish(
223  mcuxClSession_Handle_t session,
224  mcuxClMac_Context_t * const pContext,
225  mcuxCl_Buffer_t pMac,
226  uint32_t * const pMacLength
227 ); /* finalize compute */
228  /* mcuxClMac_MultiPart */
232  /* mcuxClMac_Functions */
236 
237 #ifdef __cplusplus
238 } /* extern "C" */
239 #endif
240 
241 #endif /* MCUXCLMAC_FUNCTIONS_H_ */
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClMac_finish
mcuxClMac_Status_t mcuxClMac_finish(mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
Finalize a MAC generation for a multipart MAC computation.
+
mcuxClMac_Mode_t
const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
MAC mode/algorithm type.
Definition: mcuxClMac_Types.h:67
+
mcuxClMac_init
mcuxClMac_Status_t mcuxClMac_init(mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode)
Initialization for a multipart MAC computation.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClMac_compute
mcuxClMac_Status_t mcuxClMac_compute(mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
One-shot message authentication code (MAC) computation function.
+
mcuxClMac_process
mcuxClMac_Status_t mcuxClMac_process(mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength)
Data processing for a multipart MAC computation.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
mcuxClMac_Context_t
struct mcuxClMac_Context mcuxClMac_Context_t
Mac context type.
Definition: mcuxClMac_Types.h:118
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
mcuxClMac_Status_t
uint32_t mcuxClMac_Status_t
Type for Mac component error codes.
Definition: mcuxClMac_Types.h:44
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00428.html b/components/els_pkc/doc/mcxn/html/a00428.html new file mode 100644 index 000000000..391813c90 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00428.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClMac_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClMac component. +More...

+
#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClMac_Status_t
 Type for Mac component error codes. More...
 
typedef struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
 MAC mode/algorithm descriptor type. More...
 
typedef const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
 MAC mode/algorithm type. More...
 
typedef mcuxClMac_ModeDescriptor_t *const mcuxClMac_CustomMode_t
 MAC custom mode/algorithm type. More...
 
typedef struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t
 Mac selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClMac_TestDescriptor_t *const mcuxClMac_Test_t
 Mac selftest mode/algorithm type. More...
 
typedef struct mcuxClMac_Context mcuxClMac_Context_t
 Mac context type. More...
 
+

Detailed Description

+

Type definitions for the mcuxClMac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00428.js b/components/els_pkc/doc/mcxn/html/a00428.js new file mode 100644 index 000000000..500780d9c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00428.js @@ -0,0 +1,10 @@ +var a00428 = +[ + [ "mcuxClMac_Status_t", "a00799.html#gaca63aa917056a18f99a911f329f3971b", null ], + [ "mcuxClMac_ModeDescriptor_t", "a00799.html#gaad5e6326d43f28d324ef2d98ac3ad2cc", null ], + [ "mcuxClMac_Mode_t", "a00799.html#ga8e9aa3b88af43aaf819650568abc471f", null ], + [ "mcuxClMac_CustomMode_t", "a00799.html#ga55e9279a13efd1dd87affcc88f3eb34a", null ], + [ "mcuxClMac_TestDescriptor_t", "a00799.html#ga05358be86e9c9b69f46225171d63f406", null ], + [ "mcuxClMac_Test_t", "a00799.html#ga0af47561198575f7792301a2a5135e75", null ], + [ "mcuxClMac_Context_t", "a00799.html#gaf804dbff6e0d68d2d877b21995ed5c34", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00428_source.html b/components/els_pkc/doc/mcxn/html/a00428_source.html new file mode 100644 index 000000000..3d180ed52 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00428_source.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLMAC_TYPES_H_
19 #define MCUXCLMAC_TYPES_H_
20 
21 #include <stdint.h>
22 #include <stdbool.h>
23 #include <stddef.h>
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxClSession_Types.h>
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClCore_FunctionIdentifiers.h>
29 
37 /**********************************************
38  * TYPEDEFS
39  **********************************************/
40 
44 typedef uint32_t mcuxClMac_Status_t;
45 
52 struct mcuxClMac_ModeDescriptor;
53 
60 typedef struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t;
61 
67 typedef const mcuxClMac_ModeDescriptor_t * const mcuxClMac_Mode_t;
68 
75 typedef mcuxClMac_ModeDescriptor_t * const mcuxClMac_CustomMode_t;
76 
83 struct mcuxClMac_TestDescriptor;
84 
91 typedef struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t;
92 
98 typedef const mcuxClMac_TestDescriptor_t * const mcuxClMac_Test_t;
99 
106 struct mcuxClMac_Context;
107 
118 typedef struct mcuxClMac_Context mcuxClMac_Context_t;
119  /* mcuxClMac_Types */
123 
124 #endif /* MCUXCLMAC_TYPES_H_ */
mcuxClMac_CustomMode_t
mcuxClMac_ModeDescriptor_t *const mcuxClMac_CustomMode_t
MAC custom mode/algorithm type.
Definition: mcuxClMac_Types.h:75
+
mcuxClMac_Mode_t
const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
MAC mode/algorithm type.
Definition: mcuxClMac_Types.h:67
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClMac_TestDescriptor_t
struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t
Mac selftest mode/algorithm descriptor type.
Definition: mcuxClMac_Types.h:91
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
mcuxClMac_Test_t
const mcuxClMac_TestDescriptor_t *const mcuxClMac_Test_t
Mac selftest mode/algorithm type.
Definition: mcuxClMac_Types.h:98
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClMac_Context_t
struct mcuxClMac_Context mcuxClMac_Context_t
Mac context type.
Definition: mcuxClMac_Types.h:118
+
mcuxClMac_Status_t
uint32_t mcuxClMac_Status_t
Type for Mac component error codes.
Definition: mcuxClMac_Types.h:44
+
mcuxClMac_ModeDescriptor_t
struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
MAC mode/algorithm descriptor type.
Definition: mcuxClMac_Types.h:60
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00431_source.html b/components/els_pkc/doc/mcxn/html/a00431_source.html new file mode 100644 index 000000000..4a6d06b21 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00431_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMacModes.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLMACMODES_H_
15 #define MCUXCLMACMODES_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClMacModes_Modes.h>
19 #include <mcuxClMacModes_Functions.h>
20 #include <mcuxClMacModes_MemoryConsumption.h>
21 #include <mcuxClMacModes_Constants.h>
22 
23 #endif /* MCUXCLMACMODES_H_ */
mcuxClMacModes_Constants.h
Constants for the mcuxClMacModes component.
+
mcuxClMacModes_Functions.h
Functions for the mcuxClMacModes component.
+
mcuxClMacModes_MemoryConsumption.h
Defines the memory consumption for the mcuxClMacModes component All work area sizes in bytes are a mu...
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00434.html b/components/els_pkc/doc/mcxn/html/a00434.html new file mode 100644 index 000000000..ada8eb8a6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00434.html @@ -0,0 +1,153 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMacModes_Constants.h File Reference
+
+
+ +

Constants for the mcuxClMacModes component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE
 Size of CBCMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS
 Size of CBCMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CMAC_OUTPUT_SIZE
 Size of CMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS
 Size of CMAC output in bytes: 128 bits (16 bytes) More...
 
+#define MCUXCLMACMODES_MAX_OUTPUT_SIZE
 
+#define MCUXCLMACMODES_MAX_OUTPUT_SIZE_IN_WORDS
 
+

Detailed Description

+

Constants for the mcuxClMacModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00434.js b/components/els_pkc/doc/mcxn/html/a00434.js new file mode 100644 index 000000000..17839e07d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00434.js @@ -0,0 +1,9 @@ +var a00434 = +[ + [ "MCUXCLMAC_CBCMAC_OUTPUT_SIZE", "a00800.html#gae3fbb2da7d5fef73ea388eb30cb0e8a4", null ], + [ "MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS", "a00800.html#ga071c1074dbc84e227e6bb7de4355d9e4", null ], + [ "MCUXCLMAC_CMAC_OUTPUT_SIZE", "a00800.html#ga19fabc0fcc4bb740d3ae3f5af0801932", null ], + [ "MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS", "a00800.html#ga6c92dadeb46681334a49ccd369639ca3", null ], + [ "MCUXCLMACMODES_MAX_OUTPUT_SIZE", "a00800.html#ga0ef0a7fc1fb078d453b8f662d1b35538", null ], + [ "MCUXCLMACMODES_MAX_OUTPUT_SIZE_IN_WORDS", "a00800.html#ga9d79d99b39bcb663b8f5f43db2b90105", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00434_source.html b/components/els_pkc/doc/mcxn/html/a00434_source.html new file mode 100644 index 000000000..7df11d47c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00434_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMacModes_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLMACMODES_CONSTANTS_H_
20 #define MCUXCLMACMODES_CONSTANTS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
31 /* Output sizes */
32 #define MCUXCLMAC_CBCMAC_OUTPUT_SIZE (16u)
33 #define MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS (MCUXCLMAC_CBCMAC_OUTPUT_SIZE / sizeof(uint32_t))
34 #define MCUXCLMAC_CMAC_OUTPUT_SIZE (16u)
35 #define MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS (MCUXCLMAC_CMAC_OUTPUT_SIZE / sizeof(uint32_t))
36 
37 #define MCUXCLMACMODES_MAX_OUTPUT_SIZE (16u)
38 
39 #define MCUXCLMACMODES_MAX_OUTPUT_SIZE_IN_WORDS (MCUXCLMACMODES_MAX_OUTPUT_SIZE / sizeof(uint32_t))
40 
43 #endif /* MCUXCLMACMODES_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00437.html b/components/els_pkc/doc/mcxn/html/a00437.html new file mode 100644 index 000000000..35fe43e78 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00437.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMacModes_Functions.h File Reference
+
+
+ +

Functions for the mcuxClMacModes component. +More...

+
#include <mcuxCsslFlowProtection.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClKey_Types.h>
+#include <mcuxClMac_Types.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Functions for the mcuxClMacModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00437_source.html b/components/els_pkc/doc/mcxn/html/a00437_source.html new file mode 100644 index 000000000..709608f35 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00437_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMacModes_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLMACMODES_FUNCTIONS_H_
20 #define MCUXCLMACMODES_FUNCTIONS_H_
21 
22 #include <mcuxCsslFlowProtection.h>
23 #include <mcuxClSession_Types.h>
24 #include <mcuxClKey_Types.h>
25 #include <mcuxClMac_Types.h>
26 #include <mcuxClCore_Platform.h>
27 #include <mcuxClCore_Buffer.h>
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32  /* mcuxClMacModes_Constructors */
51  /* mcuxClMacModes_Functions */
55 
56 #ifdef __cplusplus
57 } /* extern "C" */
58 #endif
59 
60 #endif /* MCUXCLMACMODES_FUNCTIONS_H_ */
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
mcuxClKey_Types.h
Type definitions for the mcuxClKey component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00440.html b/components/els_pkc/doc/mcxn/html/a00440.html new file mode 100644 index 000000000..583743ff1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00440.html @@ -0,0 +1,173 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMacModes_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClMacModes component All work area sizes in bytes are a multiple of CPU wordsize. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(size)
 
+#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_CONTEXT_SIZE
 
+#define MCUXCLMAC_CONTEXT_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClMacModes component All work area sizes in bytes are a multiple of CPU wordsize.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00440.js b/components/els_pkc/doc/mcxn/html/a00440.js new file mode 100644 index 000000000..97ea64dd6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00440.js @@ -0,0 +1,16 @@ +var a00440 = +[ + [ "MCUXCLMAC_MAX_SIZE_IN_CPUWORDS", "a00803.html#ga84842218ae711915efb61e0367612a1a", null ], + [ "MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE", "a00803.html#gadda00ba9831fbe307d2e351ffd68e881", null ], + [ "MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00803.html#ga1b01f0c494353c88edd45e9db5ed645c", null ], + [ "MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE", "a00803.html#ga714b7602c4434bdb9de3d0490fe86933", null ], + [ "MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00803.html#ga185deb298f4e4ec0c52d1d8268f5eaaa", null ], + [ "MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE", "a00803.html#ga76f5246882165b0c2686ef7b829cd792", null ], + [ "MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00803.html#ga5bbb8825cf62bc8d9cece88079a6c230", null ], + [ "MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE", "a00803.html#ga74efbfc67317a7e98173ff1e168c0a1d", null ], + [ "MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00803.html#ga2afda137b04670ff1433367446720e76", null ], + [ "MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE", "a00803.html#gaf4b9285d00220f9797d3912c06fb5ced", null ], + [ "MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS", "a00803.html#ga801ae8228e57d64f40752f67878d2fb8", null ], + [ "MCUXCLMAC_CONTEXT_SIZE", "a00803.html#gaecd5a4a9d2cb95f881e289793ba56c41", null ], + [ "MCUXCLMAC_CONTEXT_SIZE_IN_WORDS", "a00803.html#ga924f3e3033b2d83dabdccd56915221fa", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00440_source.html b/components/els_pkc/doc/mcxn/html/a00440_source.html new file mode 100644 index 000000000..3b8feb2a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00440_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
mcuxClMacModes_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLMACMODES_MEMORYCONSUMPTION_H_
20 #define MCUXCLMACMODES_MEMORYCONSUMPTION_H_
21 
29 #define MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t)))
30 
31 /* Workarea sizes */
32 #define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE (16u)
33 #define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE)
34 
35 #define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE (16u)
36 #define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE)
37 #define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE (sizeof(uint32_t))
38 #define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE)
39 #define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE (sizeof(uint32_t))
40 #define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE)
41 #define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE (16u)
42 #define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE)
43 
44 /* Context sizes */
45 #define MCUXCLMAC_CONTEXT_SIZE (52u)
46 #define MCUXCLMAC_CONTEXT_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_CONTEXT_SIZE)
47 
48 /* Mode descriptor sizes */
49  /* mcuxClMac_MemoryConsumption */
53 
54 #endif /* MCUXCLMACMODES_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00443_source.html b/components/els_pkc/doc/mcxn/html/a00443_source.html new file mode 100644 index 000000000..12dcc9c12 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00443_source.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_Modes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+
mcuxClMacModes_Modes.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLMACMODES_MODES_H_
15 #define MCUXCLMACMODES_MODES_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 #include <mcuxClCore_Platform.h>
19 #include <mcuxCsslAnalysis.h>
20 #include <mcuxClMac_Types.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
45 extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC;
46 
51 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
52 static mcuxClMac_Mode_t mcuxClMac_Mode_CMAC =
53  &mcuxClMac_ModeDescriptor_CMAC;
54 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
55 
56 
57 
62 extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding;
63 
68 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
69 static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_NoPadding =
70  &mcuxClMac_ModeDescriptor_CBCMAC_NoPadding;
71 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
72 
77 extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1;
78 
83 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
84 static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1 =
85  &mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1;
86 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
87 
92 extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2;
93 
98 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
99 static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2 =
100  &mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2;
101 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
102 
106 extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_Padding_PKCS7;
107 
111 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API")
112 static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_Padding_PKCS7 =
113  &mcuxClMac_ModeDescriptor_CBCMAC_Padding_PKCS7;
114 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
115 
116 
117 #ifdef __cplusplus
118 } /* extern "C" */
119 #endif
120 
121 #endif /* MCUXCLMACMODES_MODES_H_ */
mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2
CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 2.
+
mcuxClMac_ModeDescriptor_CMAC
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC
CMAC mode descriptor.
+
mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2
CBC-MAC mode with ISO/IEC 9797-1 padding method 2.
Definition: mcuxClMacModes_Modes.h:99
+
mcuxClMac_ModeDescriptor_CBCMAC_NoPadding
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding
CBC-MAC mode descriptor without padding.
+
mcuxClMac_Mode_t
const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
MAC mode/algorithm type.
Definition: mcuxClMac_Types.h:67
+
mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1
CBC-MAC mode with ISO/IEC 9797-1 padding method 1.
Definition: mcuxClMacModes_Modes.h:84
+
mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1
CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 1.
+
mcuxClMac_Types.h
Type definitions for the mcuxClMac component.
+
mcuxClMac_ModeDescriptor_t
struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
MAC mode/algorithm descriptor type.
Definition: mcuxClMac_Types.h:60
+
mcuxClMac_Mode_CMAC
static mcuxClMac_Mode_t mcuxClMac_Mode_CMAC
CMAC mode.
Definition: mcuxClMacModes_Modes.h:52
+
mcuxClMac_Mode_CBCMAC_NoPadding
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_NoPadding
CBC-MAC mode without padding.
Definition: mcuxClMacModes_Modes.h:69
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00446.html b/components/els_pkc/doc/mcxn/html/a00446.html new file mode 100644 index 000000000..d83a48946 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00446.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClMath.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMath.h File Reference
+
+
+ +

Top level header of mcuxClMath component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClMath_Types.h>
+#include <mcuxClMath_Functions.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClMath component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00446_source.html b/components/els_pkc/doc/mcxn/html/a00446_source.html new file mode 100644 index 000000000..47ff3e091 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00446_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClMath.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClMath.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
23 #ifndef MCUXCLMATH_H_
24 #define MCUXCLMATH_H_
25 
26 #include <mcuxClCore_Platform.h>
27 #include <mcuxClMath_Types.h>
28 #include <mcuxClMath_Functions.h>
29 
30 
31 #endif /* MCUXCLMATH_H_ */
mcuxClMath_Functions.h
APIs of mcuxClMath component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00449.html b/components/els_pkc/doc/mcxn/html/a00449.html new file mode 100644 index 000000000..0ac0b9b63 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00449.html @@ -0,0 +1,243 @@ + + + + + + + +MCUX CLNS: mcuxClMath_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
+Macros | +Functions
+
+
mcuxClMath_Functions.h File Reference
+
+
+ +

APIs of mcuxClMath component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClPkc.h>
+#include <mcuxClSession.h>
+#include <mcuxClMath_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLMATH_SHIFTMODULUS(iNShifted, iN)
 Helper macro for mcuxClMath_ShiftModulus. More...
 
#define MCUXCLMATH_FP_SHIFTMODULUS(iNShifted, iN)
 Helper macro for mcuxClMath_ShiftModulus with flow protection. More...
 
#define MCUXCLMATH_NDASH(iN, iT)
 Helper macro for mcuxClMath_NDash. More...
 
#define MCUXCLMATH_FP_NDASH(iN, iT)
 Helper macro for mcuxClMath_NDash with flow protection. More...
 
#define MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len)
 Helper macro for mcuxClMath_QDash. More...
 
#define MCUXCLMATH_FP_QDASH(iQDash, iNShifted, iN, iT, len)
 Helper macro for mcuxClMath_QDash with flow protection. More...
 
#define MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT)
 Helper macro for mcuxClMath_QSquared. More...
 
#define MCUXCLMATH_FP_QSQUARED(iQSqr, iNShifted, iN, iT)
 Helper macro for mcuxClMath_QSquared with flow protection. More...
 
#define MCUXCLMATH_MODINV(iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModInv. More...
 
#define MCUXCLMATH_FP_MODINV(iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModInv with flow protection. More...
 
#define MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_ReduceModEven. More...
 
#define MCUXCLMATH_FP_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_ReduceModEven with flow protection. More...
 
#define MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModExp_SqrMultL2R. More...
 
#define MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModExp_SqrMultL2R with flow protection. More...
 
#define MCUXCLMATH_SECMODEXP(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_SecModExp. More...
 
#define MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_SecModExp with disabled operand re-randomization. More...
 
#define MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivideOdd. More...
 
#define MCUXCLMATH_FP_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivideOdd with flow protection. More...
 
#define MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivide. More...
 
#define MCUXCLMATH_FP_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivide with flow protection. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void mcuxClMath_InitLocalUptrt (uint32_t i3_i2_i1_i0, uint32_t i7_i6_i5_i4, uint16_t *localPtrUptrt, uint8_t noOfIndices, const uint16_t **oldPtrUptrt)
 Initializes and uses the new UPTRT and returns the address of original UPTRT. More...
 
void mcuxClMath_LeadingZeros (uint8_t iX, uint32_t *pNumLeadingZeros)
 Counts number of leading zero bits of a PKC operand. More...
 
uint32_t mcuxClMath_TrailingZeros (uint8_t iX)
 Counts number of trailing zero bits of a PKC operand. More...
 
void mcuxClMath_ShiftModulus (uint16_t iNShifted_iN)
 Prepares shifted modulus. More...
 
void mcuxClMath_NDash (uint16_t iN_iT)
 Prepares modulus (calculates NDash) for PKC modular multiplication. More...
 
void mcuxClMath_QDash (uint32_t iQDash_iNShifted_iN_iT, uint16_t length)
 Calculates QDash = Q * Q' mod n, where Q = 256^(operandSize) mod n, and Q' = 256^length mod n. More...
 
void mcuxClMath_QSquared (uint32_t iQSqr_iNShifted_iN_iT)
 Calculates QSquared = Q^2 mod n, where Q = 256^(operandSize) mod n. More...
 
void mcuxClMath_ModInv (uint32_t iR_iX_iN_iT)
 Calculates modular inversion, with odd modulus. More...
 
void mcuxClMath_ReduceModEven (uint32_t iR_iX_iN_iT0, uint32_t iT1_iT2_iT3)
 Calculates modular reduction with even modulus. More...
 
void mcuxClMath_ModExp_SqrMultL2R (const uint8_t *pExp, uint32_t expByteLength, uint32_t iR_iX_iN_iT)
 Calculates modular exponentiation. More...
 
mcuxClMath_Status_t mcuxClMath_SecModExp (mcuxClSession_Handle_t session, const uint8_t *pExp, uint32_t *pExpTemp, uint32_t expByteLength, uint32_t iT3_iX_iT2_iT1, uint32_t iN_iTE_iT0_iR, uint32_t secOption)
 Securely calculates modular exponentiation. More...
 
void mcuxClMath_ExactDivideOdd (uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
 Calculates exact division with odd divisor. More...
 
void mcuxClMath_ExactDivide (uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
 Calculates exact division (supporting even divisor). More...
 
+

Detailed Description

+

APIs of mcuxClMath component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00449.js b/components/els_pkc/doc/mcxn/html/a00449.js new file mode 100644 index 000000000..982877ae4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00449.js @@ -0,0 +1,36 @@ +var a00449 = +[ + [ "MCUXCLMATH_SHIFTMODULUS", "a00806.html#gaadd4485b0f1db32b6da6e6b7a2e6cc11", null ], + [ "MCUXCLMATH_FP_SHIFTMODULUS", "a00806.html#ga35df7cdad4c81c5e276f373c70c571d0", null ], + [ "MCUXCLMATH_NDASH", "a00806.html#gab588855e23f750a4c9f7533b54a11325", null ], + [ "MCUXCLMATH_FP_NDASH", "a00806.html#gafa0d390f4eb5728edfd764936aeee313", null ], + [ "MCUXCLMATH_QDASH", "a00806.html#ga666d3347d6f96a09b791355e596de46d", null ], + [ "MCUXCLMATH_FP_QDASH", "a00806.html#ga7703703d552c5446acdf38d82cd81971", null ], + [ "MCUXCLMATH_QSQUARED", "a00806.html#ga4ee6d9b078ecc35a081a3a8cdbec0968", null ], + [ "MCUXCLMATH_FP_QSQUARED", "a00806.html#gadcd348426e9998703dc6f93194a62f80", null ], + [ "MCUXCLMATH_MODINV", "a00806.html#gaa59866fd485a59868a2a594a5858f1de", null ], + [ "MCUXCLMATH_FP_MODINV", "a00806.html#gab456571414ef2f49a91b61f0c91009ba", null ], + [ "MCUXCLMATH_REDUCEMODEVEN", "a00806.html#ga3ee39987ba7de0e36abc848d77b4eaa3", null ], + [ "MCUXCLMATH_FP_REDUCEMODEVEN", "a00806.html#gaed2b24ff10b916eb07a842a2a05ad341", null ], + [ "MCUXCLMATH_MODEXP_SQRMULTL2R", "a00806.html#ga82842f4b45c0d86e4c2d6d29e23c259b", null ], + [ "MCUXCLMATH_FP_MODEXP_SQRMULTL2R", "a00806.html#ga9f0c8d67f0c192341fbf9ac436f02173", null ], + [ "MCUXCLMATH_SECMODEXP", "a00806.html#ga3e0168ff93f7bffd7d56ce509ba29c59", null ], + [ "MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION", "a00806.html#ga32eaa55458996d636a82ac9bda34e3e0", null ], + [ "MCUXCLMATH_EXACTDIVIDEODD", "a00806.html#gae807c4ed789f67aa150addbae31de180", null ], + [ "MCUXCLMATH_FP_EXACTDIVIDEODD", "a00806.html#gaf1d62616daa224745d2ed40fdfa4d724", null ], + [ "MCUXCLMATH_EXACTDIVIDE", "a00806.html#gae99e5e55dda4387e4384e974a112a760", null ], + [ "MCUXCLMATH_FP_EXACTDIVIDE", "a00806.html#ga4dd21ea08b92f104bd3d9bff5ce7efe7", null ], + [ "mcuxClMath_InitLocalUptrt", "a00806.html#ga716b9990024e2ea5e5984ca960a5e861", null ], + [ "mcuxClMath_LeadingZeros", "a00806.html#ga91e4885b266c16938e04aa036eae6977", null ], + [ "mcuxClMath_TrailingZeros", "a00806.html#ga0203db0be2a5c09157c0db697cc2685f", null ], + [ "mcuxClMath_ShiftModulus", "a00806.html#ga65003277bfc2c6eb64be0f23261cadd7", null ], + [ "mcuxClMath_NDash", "a00806.html#ga47ca58caa097e65c0925aa488f287a1e", null ], + [ "mcuxClMath_QDash", "a00806.html#ga61ef022af097c89154560df0f81b3caa", null ], + [ "mcuxClMath_QSquared", "a00806.html#gae2ad68ea7641a23751583c27ed1d77a7", null ], + [ "mcuxClMath_ModInv", "a00806.html#ga9c01f0090ea0220a735ea6992515cf7a", null ], + [ "mcuxClMath_ReduceModEven", "a00806.html#gadcf87738f49ecf4c39ee725fa6cb88f9", null ], + [ "mcuxClMath_ModExp_SqrMultL2R", "a00806.html#gabdd7a91f84faca1e208c143a25e318f8", null ], + [ "mcuxClMath_SecModExp", "a00806.html#ga5f0ebd971dee31e271c27ae02479ff55", null ], + [ "mcuxClMath_ExactDivideOdd", "a00806.html#ga7aa33c63d602fdb151d3e342284b2171", null ], + [ "mcuxClMath_ExactDivide", "a00806.html#ga9416369d37627425ecac95580d1c3ee4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00449_source.html b/components/els_pkc/doc/mcxn/html/a00449_source.html new file mode 100644 index 000000000..69b7e90bd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00449_source.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxClMath_Functions.h Source File + + + + + + + + + + + + + + + + +
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+ + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
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+ + +
+ +
+ +
+
+
mcuxClMath_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLMATH_FUNCTIONS_H_
21 #define MCUXCLMATH_FUNCTIONS_H_
22 
23 
24 #include <mcuxClCore_Platform.h>
25 #include <mcuxClCore_FunctionIdentifiers.h>
26 #include <mcuxCsslFlowProtection.h>
27 
28 #include <mcuxClPkc.h>
29 #include <mcuxClSession.h>
30 
31 #include <mcuxClMath_Types.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
92 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_InitLocalUptrt)
93 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_InitLocalUptrt(
94  uint32_t i3_i2_i1_i0,
95  uint32_t i7_i6_i5_i4,
96  uint16_t *localPtrUptrt,
97  uint8_t noOfIndices,
98  const uint16_t **oldPtrUptrt
99  );
100 
101 
132 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_LeadingZeros)
133 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_LeadingZeros(
134  uint8_t iX,
135  uint32_t *pNumLeadingZeros
136  );
137 
138 
171 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_TrailingZeros)
172 MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClMath_TrailingZeros(
173  uint8_t iX
174  );
175 
176 
210 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ShiftModulus)
211 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ShiftModulus(
212  uint16_t iNShifted_iN
213  );
215 #define MCUXCLMATH_SHIFTMODULUS(iNShifted, iN) \
216  mcuxClMath_ShiftModulus(MCUXCLPKC_PACKARGS2(iNShifted, iN))
217 
218 #define MCUXCLMATH_FP_SHIFTMODULUS(iNShifted, iN) \
219  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_SHIFTMODULUS(iNShifted, iN))
220 
221 
257 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_NDash)
258 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_NDash(
259  uint16_t iN_iT
260  );
262 #define MCUXCLMATH_NDASH(iN, iT) \
263  mcuxClMath_NDash(MCUXCLPKC_PACKARGS2(iN, iT))
264 
265 #define MCUXCLMATH_FP_NDASH(iN, iT) \
266  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_NDASH(iN, iT))
267 
268 
309 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_QDash)
310 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QDash(
311  uint32_t iQDash_iNShifted_iN_iT,
312  uint16_t length
313  );
315 #define MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len) \
316  mcuxClMath_QDash(MCUXCLPKC_PACKARGS4(iQDash, iNShifted, iN, iT), len)
317 
318 #define MCUXCLMATH_FP_QDASH(iQDash, iNShifted, iN, iT, len) \
319  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len))
320 
321 
359 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_QSquared)
360 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QSquared(
361  uint32_t iQSqr_iNShifted_iN_iT
362  );
364 #define MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT) \
365  mcuxClMath_QSquared(MCUXCLPKC_PACKARGS4(iQSqr, iNShifted, iN, iT))
366 
367 #define MCUXCLMATH_FP_QSQUARED(iQSqr, iNShifted, iN, iT) \
368  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT))
369 
370 
411 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ModInv)
412 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModInv(
413  uint32_t iR_iX_iN_iT
414  );
416 #define MCUXCLMATH_MODINV(iR, iX, iN, iT) \
417  mcuxClMath_ModInv(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT))
418 
419 #define MCUXCLMATH_FP_MODINV(iR, iX, iN, iT) \
420  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_MODINV(iR, iX, iN, iT))
421 
422 
471 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ReduceModEven)
472 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ReduceModEven(
473  uint32_t iR_iX_iN_iT0,
474  uint32_t iT1_iT2_iT3
475  );
477 #define MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3) \
478  mcuxClMath_ReduceModEven(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT0), MCUXCLPKC_PACKARGS4(0u, iT1, iT2, iT3))
479 
480 #define MCUXCLMATH_FP_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3) \
481  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3))
482 
483 
523 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ModExp_SqrMultL2R)
524 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModExp_SqrMultL2R(
525  const uint8_t *pExp,
526  uint32_t expByteLength,
527  uint32_t iR_iX_iN_iT
528  );
530 #define MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT) \
531  mcuxClMath_ModExp_SqrMultL2R(pExp, byteLenExp, MCUXCLPKC_PACKARGS4(iR, iX, iN, iT))
532 
533 #define MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT) \
534  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT))
535 
536 
611 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_SecModExp)
612 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) mcuxClMath_SecModExp(
613  mcuxClSession_Handle_t session,
614  const uint8_t *pExp,
615  uint32_t *pExpTemp,
616  uint32_t expByteLength,
617  uint32_t iT3_iX_iT2_iT1,
618  uint32_t iN_iTE_iT0_iR,
619  uint32_t secOption
620  );
622 #define MCUXCLMATH_SECMODEXP(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3) \
623  mcuxClMath_SecModExp(session, pExp, pExpTemp, byteLenExp, MCUXCLPKC_PACKARGS4(iT3, iX, iT2, iT1), MCUXCLPKC_PACKARGS4(iN, iTE, iT0, iR), 0u)
624 
626 #define MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3) \
627  mcuxClMath_SecModExp(session, pExp, pExpTemp, byteLenExp, MCUXCLPKC_PACKARGS4(iT3, iX, iT2, iT1), MCUXCLPKC_PACKARGS4(iN, iTE, iT0, iR), MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND)
628 
629 
680 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ExactDivideOdd)
681 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivideOdd(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength);
683 #define MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \
684  mcuxClMath_ExactDivideOdd(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT), xPkcByteLen, yPkcByteLen)
685 
686 #define MCUXCLMATH_FP_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \
687  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen))
688 
689 
749 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ExactDivide)
750 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivide(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength);
752 #define MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \
753  mcuxClMath_ExactDivide(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT), xPkcByteLen, yPkcByteLen)
754 
756 #define MCUXCLMATH_FP_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \
757  MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen))
758 
759  /* mcuxClMath_Functions */
763 
764 #ifdef __cplusplus
765 } /* extern "C" */
766 #endif
767 
768 #endif /* MCUXCLMATH_FUNCTIONS_H_ */
mcuxClMath_InitLocalUptrt
void mcuxClMath_InitLocalUptrt(uint32_t i3_i2_i1_i0, uint32_t i7_i6_i5_i4, uint16_t *localPtrUptrt, uint8_t noOfIndices, const uint16_t **oldPtrUptrt)
Initializes and uses the new UPTRT and returns the address of original UPTRT.
+
mcuxClMath_ExactDivide
void mcuxClMath_ExactDivide(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
Calculates exact division (supporting even divisor).
+
mcuxClMath_QSquared
void mcuxClMath_QSquared(uint32_t iQSqr_iNShifted_iN_iT)
Calculates QSquared = Q^2 mod n, where Q = 256^(operandSize) mod n.
+
mcuxClMath_NDash
void mcuxClMath_NDash(uint16_t iN_iT)
Prepares modulus (calculates NDash) for PKC modular multiplication.
+
mcuxClMath_ExactDivideOdd
void mcuxClMath_ExactDivideOdd(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
Calculates exact division with odd divisor.
+
mcuxClMath_ModInv
void mcuxClMath_ModInv(uint32_t iR_iX_iN_iT)
Calculates modular inversion, with odd modulus.
+
mcuxClPkc.h
Top level header of mcuxClPkc component (PKC hardware driver)
+
mcuxClMath_ReduceModEven
void mcuxClMath_ReduceModEven(uint32_t iR_iX_iN_iT0, uint32_t iT1_iT2_iT3)
Calculates modular reduction with even modulus.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClMath_ShiftModulus
void mcuxClMath_ShiftModulus(uint16_t iNShifted_iN)
Prepares shifted modulus.
+
mcuxClMath_QDash
void mcuxClMath_QDash(uint32_t iQDash_iNShifted_iN_iT, uint16_t length)
Calculates QDash = Q * Q' mod n, where Q = 256^(operandSize) mod n, and Q' = 256^length mod n.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClMath_ModExp_SqrMultL2R
void mcuxClMath_ModExp_SqrMultL2R(const uint8_t *pExp, uint32_t expByteLength, uint32_t iR_iX_iN_iT)
Calculates modular exponentiation.
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClMath_TrailingZeros
uint32_t mcuxClMath_TrailingZeros(uint8_t iX)
Counts number of trailing zero bits of a PKC operand.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClMath_LeadingZeros
void mcuxClMath_LeadingZeros(uint8_t iX, uint32_t *pNumLeadingZeros)
Counts number of leading zero bits of a PKC operand.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClMath_Status_t
uint32_t mcuxClMath_Status_t
Type for error codes used by Math component functions.
Definition: mcuxClMath_Types.h:46
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMath_SecModExp
mcuxClMath_Status_t mcuxClMath_SecModExp(mcuxClSession_Handle_t session, const uint8_t *pExp, uint32_t *pExpTemp, uint32_t expByteLength, uint32_t iT3_iX_iT2_iT1, uint32_t iN_iTE_iT0_iR, uint32_t secOption)
Securely calculates modular exponentiation.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00452_source.html b/components/els_pkc/doc/mcxn/html/a00452_source.html new file mode 100644 index 000000000..18bc8bc4c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00452_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClMath_Types.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
+ +
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+ + +
+ +
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+
mcuxClMath_Types.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLMATH_TYPES_H_
21 #define MCUXCLMATH_TYPES_H_
22 
23 #include <mcuxClCore_Platform.h>
24 #include <mcuxClCore_FunctionIdentifiers.h>
25 #include <mcuxCsslFlowProtection.h>
26 
27 
28 /**********************************************
29  * CONSTANTS
30  **********************************************/
31 /* None */
32 
33 /**********************************************
34  * TYPEDEFS
35  **********************************************/
46 typedef uint32_t mcuxClMath_Status_t;
47 
51 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) mcuxClMath_Status_Protected_t;
52 
53 #define MCUXCLMATH_STATUS_OK ((mcuxClMath_Status_t) 0x0FF32E03u)
54 #define MCUXCLMATH_ERRORCODE_OK MCUXCLMATH_STATUS_OK
55 #define MCUXCLMATH_STATUS_ERROR ((mcuxClMath_Status_t) 0x0FF35330u)
56 #define MCUXCLMATH_ERRORCODE_ERROR MCUXCLMATH_STATUS_ERROR
57 
58 
62 #define MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND (0xA5A5A5A5u)
63  /* mcuxClMath_Macros */
67 
68 
69 #endif /* MCUXCLMATH_TYPES_H_ */
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClMath_Status_t
uint32_t mcuxClMath_Status_t
Type for error codes used by Math component functions.
Definition: mcuxClMath_Types.h:46
+
mcuxClMath_Status_Protected_t
mcuxClMath_Status_t mcuxClMath_Status_Protected_t
Deprecated type for error codes used by code-flow protected Math component functions.
Definition: mcuxClMath_Types.h:51
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00455.html b/components/els_pkc/doc/mcxn/html/a00455.html new file mode 100644 index 000000000..861f9d2b0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00455.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClMemory.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClMemory.h File Reference
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+
+ +

Top-level include file for the memory operations. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxClMemory_Endianness.h>
+#include <mcuxClMemory_Clear.h>
+#include <mcuxClMemory_Copy.h>
+#include <mcuxClMemory_Copy_Reversed.h>
+#include <mcuxClMemory_Set.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the memory operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00455_source.html b/components/els_pkc/doc/mcxn/html/a00455_source.html new file mode 100644 index 000000000..3be88caf0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00455_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxClMemory.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClMemory.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLMEMORY_H
27 #define MCUXCLMEMORY_H
28 
29 #include <mcuxClConfig.h> // Exported features flags header
30 #include <mcuxCsslFlowProtection.h>
31 #include <mcuxClCore_FunctionIdentifiers.h>
32 #include <mcuxClMemory_Types.h>
33 #include <mcuxClMemory_Endianness.h>
34 #include <mcuxClMemory_Clear.h>
35 #include <mcuxClMemory_Copy.h>
36 #include <mcuxClMemory_Copy_Reversed.h>
37 #include <mcuxClMemory_Set.h>
38 
42 #endif
mcuxClMemory_Copy_Reversed.h
Memory header for reversed copy functions.
+
mcuxClMemory_Endianness.h
Memory header for endianness support functions.
+
mcuxClMemory_Set.h
Memory header for set function.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClMemory_Copy.h
Memory header for copy functions.
+
mcuxClMemory_Clear.h
Memory header for clear functions.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00458.html b/components/els_pkc/doc/mcxn/html/a00458.html new file mode 100644 index 000000000..2bccf6b03 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00458.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Clear.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros | +Functions
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mcuxClMemory_Clear.h File Reference
+
+
+ +

Memory header for clear functions. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, byteLen)
 Helper macro to call mcuxClMemory_clear with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF(pTarget, byteLen, buffLen)
 Helper macro to call mcuxClMemory_clear with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength)
 Overwrites a memory buffer with null bytes. More...
 
+

Detailed Description

+

Memory header for clear functions.

+

This header exposes functions that enable using memory clear function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00458.js b/components/els_pkc/doc/mcxn/html/a00458.js new file mode 100644 index 000000000..a60fceeb0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00458.js @@ -0,0 +1,6 @@ +var a00458 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_CLEAR", "a00809.html#ga2dc0fdbb602c3777fffb8515f944d736", null ], + [ "MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF", "a00809.html#ga76dcce466859684502b4725d51d5de4f", null ], + [ "mcuxClMemory_clear", "a00809.html#ga1ac6e8a4335f620d41360c090ee5ce73", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00458_source.html b/components/els_pkc/doc/mcxn/html/a00458_source.html new file mode 100644 index 000000000..4eb9ab782 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00458_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Clear.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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mcuxClMemory_Clear.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
28 #ifndef MCUXCLMEMORY_CLEAR_H_
29 #define MCUXCLMEMORY_CLEAR_H_
30 
31 #include <mcuxClConfig.h> // Exported features flags header
32 
33 #include <mcuxClMemory_Types.h>
34 #include <mcuxCsslAnalysis.h>
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /**********************************************
41  * FUNCTIONS
42  **********************************************/
43 
55 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_clear)
56 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength);
57 
58 
59 /**********************************************
60  * MACROS
61  **********************************************/
62 
64 #define MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, byteLen) \
65  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, byteLen))
66 
68 #define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF(pTarget, byteLen, buffLen) \
69  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, buffLen))
70 
71 
72 #ifdef __cplusplus
73 } /* extern "C" */
74 #endif
75 
76 #endif /* MCUXCLMEMORY_CLEAR_H_ */
77 
mcuxClMemory_clear
void mcuxClMemory_clear(uint8_t *pDst, size_t length, size_t bufLength)
Overwrites a memory buffer with null bytes.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00461.html b/components/els_pkc/doc/mcxn/html/a00461.html new file mode 100644 index 000000000..866cb54c7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00461.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros | +Functions
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mcuxClMemory_Copy.h File Reference
+
+
+ +

Memory header for copy functions. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, byteLen)
 Helper macro to call mcuxClMemory_copy with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pTarget, pSource, byteLen, buffLen)
 Helper macro to call mcuxClMemory_copy with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
 Copies a memory buffer to another location. More...
 
+

Detailed Description

+

Memory header for copy functions.

+

This header exposes functions that enable using memory copy function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00461.js b/components/els_pkc/doc/mcxn/html/a00461.js new file mode 100644 index 000000000..c4522a185 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00461.js @@ -0,0 +1,6 @@ +var a00461 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_COPY", "a00810.html#ga5d16560ac24ef6ba2dae129206e70208", null ], + [ "MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF", "a00810.html#gaab249829be1231ec5f08f90093943a40", null ], + [ "mcuxClMemory_copy", "a00810.html#gab564183ab5f02cf11b66b6244ba2112a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00461_source.html b/components/els_pkc/doc/mcxn/html/a00461_source.html new file mode 100644 index 000000000..a524ae195 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00461_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClMemory_Copy.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLMEMORY_COPY_H_
27 #define MCUXCLMEMORY_COPY_H_
28 
29 #include <mcuxClConfig.h> // Exported features flags header
30 
31 #include <mcuxClMemory_Types.h>
32 #include <mcuxCsslAnalysis.h>
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /**********************************************
39  * FUNCTIONS
40  **********************************************/
41 
57 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy)
58 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength);
59 
60 
61 /**********************************************
62  * MACROS
63  **********************************************/
64 
66 #define MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, byteLen) \
67  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen))
68 
70 #define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pTarget, pSource, byteLen, buffLen) \
71  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, buffLen))
72 
73 
74 #ifdef __cplusplus
75 } /* extern "C" */
76 #endif
77 
78 #endif /* MCUXCLMEMORY_COPY_H_ */
79 
mcuxClMemory_copy
void mcuxClMemory_copy(uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
Copies a memory buffer to another location.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00464.html b/components/els_pkc/doc/mcxn/html/a00464.html new file mode 100644 index 000000000..72a431c46 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00464.html @@ -0,0 +1,148 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy_Reversed.h File Reference + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros | +Functions
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mcuxClMemory_Copy_Reversed.h File Reference
+
+
+ +

Memory header for reversed copy functions. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pTarget, pSource, byteLen)
 Helper macro to call mcuxClMemory_copy_reversed with flow protection. More...
 
+ + + + +

+Functions

void mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
 Copies a memory buffer to another location reversely. More...
 
+

Detailed Description

+

Memory header for reversed copy functions.

+

This header exposes functions that enable using memory reversed copy function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00464.js b/components/els_pkc/doc/mcxn/html/a00464.js new file mode 100644 index 000000000..a12bc5118 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00464.js @@ -0,0 +1,5 @@ +var a00464 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED", "a00811.html#ga34f4a48eda22ae64759db5d7893d0c36", null ], + [ "mcuxClMemory_copy_reversed", "a00811.html#gafc918d181009c3af7638604e5e4b9281", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00464_source.html b/components/els_pkc/doc/mcxn/html/a00464_source.html new file mode 100644 index 000000000..77ddf2901 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00464_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy_Reversed.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClMemory_Copy_Reversed.h
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLMEMORY_COPY_REVERSED_H_
27 #define MCUXCLMEMORY_COPY_REVERSED_H_
28 
29 #include <mcuxClCore_Platform.h>
30 #include <mcuxClMemory_Types.h>
31 #include <mcuxCsslAnalysis.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /**********************************************
38  * FUNCTIONS
39  **********************************************/
40 
54 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy_reversed)
55 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength);
56 
57 
58 /**********************************************
59  * MACROS
60  **********************************************/
61 
63 #define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pTarget, pSource, byteLen) \
64  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy_reversed((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen))
65 
66 #ifdef __cplusplus
67 } /* extern "C" */
68 #endif
69 
70 #endif /* MCUXCLMEMORY_COPY_REVERSED_H_ */
71 
mcuxClMemory_copy_reversed
void mcuxClMemory_copy_reversed(uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
Copies a memory buffer to another location reversely.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00467.html b/components/els_pkc/doc/mcxn/html/a00467.html new file mode 100644 index 000000000..d9489bd61 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00467.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Endianness.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+Macros
+
+
mcuxClMemory_Endianness.h File Reference
+
+
+ +

Memory header for endianness support functions. +More...

+
#include <mcuxClMemory_Types.h>
+#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Macros

#define mcuxClMemory_StoreLittleEndian32(destination, value)
 Converts a 32-bit unsigned integer to a little-endian order uint8_t array . More...
 
#define mcuxClMemory_StoreBigEndian32(destination, value)
 Converts a 32-bit unsigned integer to a big-endian order uint8_t array. More...
 
#define mcuxClMemory_LoadLittleEndian32(source)
 Converts a little-endian order uint8_t array to a 32-bit unsigned integer. More...
 
#define mcuxClMemory_LoadBigEndian32(source)
 Converts a big-endian order uint8_t array to a 32-bit unsigned integer. More...
 
#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input)
 MACRO that switches byte endianness of given CPU word. More...
 
+

Detailed Description

+

Memory header for endianness support functions.

+

This header exposes macros that enable using endianness support functions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00467.js b/components/els_pkc/doc/mcxn/html/a00467.js new file mode 100644 index 000000000..60aa5913f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00467.js @@ -0,0 +1,8 @@ +var a00467 = +[ + [ "mcuxClMemory_StoreLittleEndian32", "a00812.html#gaef4886d199c2539b209458a8c62378cd", null ], + [ "mcuxClMemory_StoreBigEndian32", "a00812.html#ga84f8097975ebea39deaea4ab9306d2ce", null ], + [ "mcuxClMemory_LoadLittleEndian32", "a00812.html#gaa3eba98f422623a6a02f15898449c874", null ], + [ "mcuxClMemory_LoadBigEndian32", "a00812.html#gabd3fd1c7ee32c2cd202a67bce5036778", null ], + [ "MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS", "a00812.html#gac426a079f1808ff0183d2851ead720c5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00467_source.html b/components/els_pkc/doc/mcxn/html/a00467_source.html new file mode 100644 index 000000000..e21f5f96b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00467_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Endianness.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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mcuxClMemory_Endianness.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLMEMORY_ENDIANNESS_H_
27 #define MCUXCLMEMORY_ENDIANNESS_H_
28 
29 #include <mcuxClMemory_Types.h>
30 #include <mcuxClConfig.h> // Exported features flags header
31 
32 
33 /**********************************************
34  * MACROS
35  **********************************************/
36 
46 #define mcuxClMemory_StoreLittleEndian32( destination, value ) \
47 do \
48 { \
49  (destination)[0] = (uint8_t) (((value) & 0x000000FFU) >> 0u); \
50  (destination)[1] = (uint8_t) (((value) & 0x0000FF00U) >> 8u); \
51  (destination)[2] = (uint8_t) (((value) & 0x00FF0000U) >> 16u); \
52  (destination)[3] = (uint8_t) (((value) & 0xFF000000U) >> 24u); \
53 } while (false)
54 
63 #define mcuxClMemory_StoreBigEndian32( destination, value ) \
64 do \
65 { \
66  (destination)[0] = (uint8_t) (((value) & 0xFF000000U) >> 24u); \
67  (destination)[1] = (uint8_t) (((value) & 0x00FF0000U) >> 16u); \
68  (destination)[2] = (uint8_t) (((value) & 0x0000FF00U) >> 8u); \
69  (destination)[3] = (uint8_t) (((value) & 0x000000FFU) >> 0u); \
70 } while (false)
71 
80 #define mcuxClMemory_LoadLittleEndian32( source ) \
81  ( (((uint32_t) (source)[0]) << 0u) | \
82  (((uint32_t) (source)[1]) << 8u) | \
83  (((uint32_t) (source)[2]) << 16u) | \
84  (((uint32_t) (source)[3]) << 24u) )
85 
86 
94 #define mcuxClMemory_LoadBigEndian32( source ) \
95  ( (((uint32_t) (source)[0]) << 24u) | \
96  (((uint32_t) (source)[1]) << 16u) | \
97  (((uint32_t) (source)[2]) << 8u) | \
98  (((uint32_t) (source)[3]) << 0u) )
99 
107 #ifdef __REV
108 #define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input) __REV(input)
109 #else
110 #define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input) ((((input) & 0xffu) << 24u) | (((input) & 0xff00u) << 8u) | (((input) & 0xff0000u) >> 8u) | (((input) & 0xff000000u) >> 24u))
111 #endif
112 
113 #endif /* MCUXCLMEMORY_ENDIANNESS_H_ */
114 
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00470.html b/components/els_pkc/doc/mcxn/html/a00470.html new file mode 100644 index 000000000..65ed618a5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00470.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Set.h File Reference + + + + + + + + + + + + + + + + +
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mcuxClMemory_Set.h File Reference
+
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+ +

Memory header for set function. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClMemory_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_SET(pTarget, val, byteLen)
 Helper macro to call mcuxClMemory_set with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pTarget, val, byteLen, buffLen)
 Helper macro to call mcuxClMemory_set with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength)
 Sets all bytes of a memory buffer to a specified value. More...
 
+

Detailed Description

+

Memory header for set function.

+

This header exposes functions that enable using memory set functions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00470.js b/components/els_pkc/doc/mcxn/html/a00470.js new file mode 100644 index 000000000..4c4d6fff1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00470.js @@ -0,0 +1,6 @@ +var a00470 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_SET", "a00813.html#ga039e0b482faab4d1aabe2dd5c79d3eb5", null ], + [ "MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF", "a00813.html#gad65a5023a0b0263462b6cfcd6761b904", null ], + [ "mcuxClMemory_set", "a00813.html#ga5d86af41c30044c28809914e2901884d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00470_source.html b/components/els_pkc/doc/mcxn/html/a00470_source.html new file mode 100644 index 000000000..f1d5d183a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00470_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Set.h Source File + + + + + + + + + + + + + + + + +
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
26 #ifndef MCUXCLMEMORY_SET_H_
27 #define MCUXCLMEMORY_SET_H_
28 
29 #include <mcuxClConfig.h> // Exported features flags header
30 
31 #include <mcuxClMemory_Types.h>
32 #include <mcuxCsslAnalysis.h>
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /**********************************************
39  * FUNCTIONS
40  **********************************************/
53 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_set)
54 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength);
55 
56 /**********************************************
57  * MACROS
58  **********************************************/
59 
61 #define MCUXCLMEMORY_FP_MEMORY_SET(pTarget, val, byteLen) \
62  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, byteLen))
63 
65 #define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pTarget, val, byteLen, buffLen) \
66  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, buffLen))
67 
68 
69 #ifdef __cplusplus
70 } /* extern "C" */
71 #endif
72 
73 #endif /* MCUXCLMEMORY_SET_H_ */
74 
mcuxClMemory_set
void mcuxClMemory_set(uint8_t *pDst, uint8_t val, size_t length, size_t bufLength)
Sets all bytes of a memory buffer to a specified value.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMemory_Types.h
Memory type header.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00473.html b/components/els_pkc/doc/mcxn/html/a00473.html new file mode 100644 index 000000000..59dd4017e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00473.html @@ -0,0 +1,159 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Types.h File Reference + + + + + + + + + + + + + + + + +
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mcuxClMemory_Types.h File Reference
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Memory type header. +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Macros

#define MCUXCLMEMORY_API
 Marks a function as a public API function of the mcuxClMemory component. More...
 
#define MCUXCLMEMORY_STATUS_OK
 Memory operation successful. More...
 
#define MCUXCLMEMORY_ERRORCODE_OK
 Memory operation successful. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClMemory_Status_t
 Type for error codes of mcuxClMemory component functions. More...
 
typedef mcuxClMemory_Status_t mcuxClMemory_Status_Protected_t
 Deprecated type for error codes used by code-flow protected mcuxClMemory component functions. More...
 
+

Detailed Description

+

Memory type header.

+

This header exposes types used by the mcuxClMemory functions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00473.js b/components/els_pkc/doc/mcxn/html/a00473.js new file mode 100644 index 000000000..6ce93983b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00473.js @@ -0,0 +1,8 @@ +var a00473 = +[ + [ "MCUXCLMEMORY_API", "a00815.html#ga2469abde1e59b6b478ba8c393dc3e95a", null ], + [ "MCUXCLMEMORY_STATUS_OK", "a00816.html#ga0a6eff5e1bb27d6c237a16f7d60b9eb9", null ], + [ "MCUXCLMEMORY_ERRORCODE_OK", "a00815.html#ga0e92b528eed7533fedddfc3172c60fa8", null ], + [ "mcuxClMemory_Status_t", "a00814.html#gad25887c99517f13c547e1d2bf027ccd1", null ], + [ "mcuxClMemory_Status_Protected_t", "a00814.html#ga57c9ba76c62b4ad9bd565df4a98c19ba", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00473_source.html b/components/els_pkc/doc/mcxn/html/a00473_source.html new file mode 100644 index 000000000..4b44bff3f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00473_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Types.h Source File + + + + + + + + + + + + + + + + +
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mcuxClMemory_Types.h
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
25 #ifndef MCUXCLMEMORY_TYPES_H
26 #define MCUXCLMEMORY_TYPES_H
27 
28 #include <stdint.h>
29 #include <stddef.h>
30 #include <mcuxClConfig.h> // Exported features flags header
31 #include <mcuxCsslFlowProtection.h>
32 #include <mcuxClCore_FunctionIdentifiers.h>
33 
34 /**********************************************
35  * MACROS
36  **********************************************/
43 #define MCUXCLMEMORY_API extern
44 
45 
52 #define MCUXCLMEMORY_STATUS_OK ((mcuxClMemory_Status_t) 0x09992E03u)
53 
54 
58 #define MCUXCLMEMORY_ERRORCODE_OK MCUXCLMEMORY_STATUS_OK
59 
61 
65 /**********************************************
66  * TYPEDEFS
67  **********************************************/
73 typedef uint32_t mcuxClMemory_Status_t;
74 
78 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_Status_Protected_t;
79 
80 #endif /* #MCUXCLMEMORY_TYPES_H */
81 
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClMemory_Status_Protected_t
mcuxClMemory_Status_t mcuxClMemory_Status_Protected_t
Deprecated type for error codes used by code-flow protected mcuxClMemory component functions.
Definition: mcuxClMemory_Types.h:78
+
mcuxClMemory_Status_t
uint32_t mcuxClMemory_Status_t
Type for error codes of mcuxClMemory component functions.
Definition: mcuxClMemory_Types.h:73
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00476.html b/components/els_pkc/doc/mcxn/html/a00476.html new file mode 100644 index 000000000..5c00b6ce1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00476.html @@ -0,0 +1,1032 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_FunctionIdentifiers.h File Reference + + + + + + + + + + + + + + + + +
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mcuxClOscca_FunctionIdentifiers.h File Reference
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Definition of function identifiers for the flow protection mechanism. +More...

+ +

Go to the source code of this file.

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+Macros

+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_encrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_decrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_OnlyVerify_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_SignVerify_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_EncDec_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compute
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_SM4_Gen_K1K2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Finalize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Finalize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Update
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Update
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_reseed
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_process_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_decrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_encrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_decrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_encrypt_Sm4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_FastSecureXor
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_switch_endianness
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_finish_sm3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_process_sm3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_oneShotSkeleton_sm3
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_finishSkeleton
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_processSkeleton
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_oneShotSkeleton
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PowerOnTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_DeliverySimpleTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PokerTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_generate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SkeletonCcm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CalcMontInverse
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_EngineCcm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_Internal_Ctr
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeModInv
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_LeadingZeros
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_MultipleShiftRotate_Index
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GeneratePointerTable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeQSquared
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeNDash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_StartFupProgram
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Op
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetFupTable
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_WaitforFinish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GetWordSize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetWordSize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Reset
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process_adata
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_crypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_prepareHMACKey
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tprime
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Lprime
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_T
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_L
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Finalize
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Oneshot
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tau
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Update
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_SkeletonSM2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSM2_GenerateKeyPair
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_PreLoad
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Auto
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Norm
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_ProcessMessageBlock_Sgi
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareToZero
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareBoolean
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SignVerify_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ComputePrehash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_InvertPrivateKey
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Sign
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Export
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Import
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointCheckCoordinate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAddOrDouble
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccTransAffinePoint2Jac
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenRandomBytes
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultMontgomery
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAdd
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointDouble
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointConvert2Affine
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccJacPointCheck
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointYNegNoInit
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointWithInit
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenerateZ
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPrepareParameters
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccInit
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_WrapHash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccExitClear
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ValidateEncDecCtx
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_UpdatePhase
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecondPartOfInitPhase
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KDF
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SetParamCrcValue
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_CheckParamCrc
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_decrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_encrypt
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleSM4Key
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_EngineSM4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_SkeletonSM4
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_key_agreement
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_verify
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PreHash
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyAgreement_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PrepareDigest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_IncCounter
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CountLeadingZerosWord
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_core_sm3_processMessageBlock
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Engine
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleKey
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccSecurePointMult
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultSplitScalar
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureExport
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureImport
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Ecb_EncDec_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Cbc_EncDec_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4Cmac_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4CbcMac_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Sm4Ccm_EncDec_SelfTest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_selftest
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Init
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_ProcessAad
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Process
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Finish
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_25
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_26
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_27
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_28
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_29
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_30
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_31
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_32
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_33
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_34
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_35
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_36
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_37
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_38
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_39
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_40
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_41
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_42
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_43
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_44
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_45
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_46
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_47
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_48
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_49
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_50
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_51
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_52
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_53
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_54
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_55
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_56
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_57
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_58
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_59
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_60
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_61
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_62
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_63
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_64
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_65
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_66
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_67
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_68
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_69
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_70
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_71
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_72
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_73
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_74
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_75
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_76
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_77
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_78
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_79
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_80
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_81
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_82
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_83
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_84
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_85
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_86
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_87
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_88
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_89
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_90
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_91
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_92
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_93
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_94
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_95
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_96
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_97
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_98
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_99
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_100
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_101
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_102
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_103
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_104
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_105
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_106
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_107
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_108
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_109
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_110
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_111
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_112
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_113
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_114
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_115
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_116
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_117
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_118
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_119
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_120
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_121
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_122
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_123
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_124
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_125
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_126
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_127
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_128
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_129
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_130
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_131
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_132
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_133
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_134
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_135
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_136
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_137
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_138
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_139
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_140
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_141
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_142
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_143
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_144
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_145
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_146
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_147
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_148
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_149
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_150
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_151
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_152
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_153
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_154
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_155
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_156
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_157
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_158
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_159
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_160
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_161
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_162
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_163
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_164
 
+#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_165
 
+

Detailed Description

+

Definition of function identifiers for the flow protection mechanism.

+
Note
This file might be post-processed to update the identifier values to proper/secure values.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00476.js b/components/els_pkc/doc/mcxn/html/a00476.js new file mode 100644 index 000000000..629797ea7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00476.js @@ -0,0 +1,302 @@ +var a00476 = +[ + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_encrypt", "a00476.html#a4dcf0e2d02e61349dbae6b5b17201a91", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_encrypt_Sm4", "a00476.html#a3462f5eab34342bb68164cbdeb46365d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_decrypt_Sm4", "a00476.html#a33f961caa97807193545ee312d2cf221", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_OnlyVerify_SelfTest", "a00476.html#a776117ff675e8778880ad4bb0b89a429", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_SignVerify_SelfTest", "a00476.html#afce3ec27b7b155c2958a586e89bc5ffc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_EncDec_selftest", "a00476.html#a9d1986fc3b6b5efd021143fff7d63dd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange_SelfTest", "a00476.html#ae7e1dc19c9a80eb0d229c52f1cf6b71d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_finish", "a00476.html#a55d6c22eabffbb7915632260d0a183f2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_process", "a00476.html#a1d73d3ad98975dae3f4871ebd8d6b7f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compute", "a00476.html#ab0c443839b1821d438cc411ae731deb7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_init", "a00476.html#a6d683b8408692d235d203d9f150f4c25", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_SM4_Gen_K1K2", "a00476.html#a30e870afd5fa07c10bfb98909d957d9a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Finalize", "a00476.html#a0af02ab635b8fc082914d13a8f5bd811", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Finalize", "a00476.html#a7bebcb297b767d40b9eac3a0aff0770b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Update", "a00476.html#af6e538673c201bf463848f74f481b0e1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Update", "a00476.html#af952256ec85de06ebaf81ab7ac37f3e8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Init", "a00476.html#a36bbd84f89ad96dc5967adbb85a6f21a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Init", "a00476.html#ab95ab1c6542f5e6187c16a4b49084da7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Oneshot", "a00476.html#a754292edf9d870817bac764baea6cb77", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Oneshot", "a00476.html#a55799c481f0605f1741fdcce751ad6b6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_reseed", "a00476.html#a8a167f214bf2fedf36a792f637026339", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_Sm4", "a00476.html#a5fc25d42fc8a90a24d71b66f4d95e128", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_process_Sm4", "a00476.html#a6f9381f8be6de2f7a072cbe824e24a42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_decrypt_Sm4", "a00476.html#a7ff8d05fdf4763ac4ed3c2fa41ccd8a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_encrypt_Sm4", "a00476.html#ae991986457d406907094e1436d022d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_decrypt_Sm4", "a00476.html#a25e8d6c8ad3d15245857071657dc7a86", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_encrypt_Sm4", "a00476.html#a05505c25cfdb41ea71e4f7bf40ed42ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_FastSecureXor", "a00476.html#a9d49dcce9752d3ad74432dcd110bb17c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_switch_endianness", "a00476.html#a98525f572a0bb58532e166e77d389d30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_finish_sm3", "a00476.html#a598b88fbc9e3813e797fb421d01e00d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_process_sm3", "a00476.html#aab449a16dd17d5271a235e13ba225cd9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_oneShotSkeleton_sm3", "a00476.html#a47260b40f0524d0a3136c4022c6723f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_finishSkeleton", "a00476.html#ae2657447e2ed926b53715b61788820d7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_processSkeleton", "a00476.html#a5ea62e3f65f7a10b1b03e370ac31d0a1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_oneShotSkeleton", "a00476.html#ade206605bd481408991a32fdb9016118", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_selftest", "a00476.html#af434646886f6779492a15d2d77d01c8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PowerOnTest", "a00476.html#a2a5ede61f36a0c69a96945af5cb7e3cc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_DeliverySimpleTest", "a00476.html#ab80630723e49b9ec46df5d32f0049bb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PokerTest", "a00476.html#a156e462d6206600f33bdf0c4ba3c2cf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_generate", "a00476.html#a8197f735c538a4cb8f2e876b0f332a8f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_init", "a00476.html#a0de5e45dd7e660a39632f242d1013ba6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SkeletonCcm", "a00476.html#a43631e5f9ab0fc76822977854df9246a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CalcMontInverse", "a00476.html#adc197cd776847e0491d0ffff4f774770", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_EngineCcm", "a00476.html#a975302bfabb97094d3f8dc700649da30", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_Internal_Ctr", "a00476.html#abd1894256483d6e2e05c4029b8e5aa53", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeModInv", "a00476.html#a01691d552290a7fd3f8c1ff8c3523616", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_LeadingZeros", "a00476.html#a42da81b9b866a1b95409778d7dd5516d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_MultipleShiftRotate_Index", "a00476.html#ad0fadc8029481422fdcf8beaa0b61c74", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GeneratePointerTable", "a00476.html#ad32df448b36cf109601d85922741e0a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeQSquared", "a00476.html#ab1898fdd78a96da681fe381b0ba00013", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeNDash", "a00476.html#abecc600fdfdc789c4bb68c5367e2673b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_StartFupProgram", "a00476.html#a9f1b653350ba8a9d7582b015cd1d6c6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Op", "a00476.html#a42256acedfd06e8d427f9b07e3d35d06", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetFupTable", "a00476.html#a90b6771e8f887b750c3d9e67d203ae23", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_WaitforFinish", "a00476.html#a53c6a8e79d0979b5a77eacd586ded5e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GetWordSize", "a00476.html#ab9333ec280d78dd1a5ac5c37e347629f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetWordSize", "a00476.html#a85e7c7ec62971a3d3ad611a8577bc8ee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Init", "a00476.html#abc924bd0c21ecd95c6319794a09c1c58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Reset", "a00476.html#a80ce01391a3911badea61e9e30916757", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init", "a00476.html#aa26ead35069de24085a48abab95dd6df", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_encrypt", "a00476.html#a17f02f9edf46c1e9e27998a971b65504", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_decrypt", "a00476.html#a97cc6214ab57fb77ba3af3f9a2248d42", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process", "a00476.html#adbaf9664a527df26d05d4aea3ddd2f26", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process_adata", "a00476.html#a58ab4ca5e92651a137d45ef4aceaec72", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_finish", "a00476.html#ad2e841776f2cb80ed2219f9413e770f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_verify", "a00476.html#abb2c3939599a6a2827d81d6367d78752", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_crypt", "a00476.html#a79251668ca7923c4b100072b8b36056f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_encrypt", "a00476.html#ad194345afc555898461a0faf7a32dfcc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_decrypt", "a00476.html#a6b829a093a2fd61d27d79805d399eabb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_prepareHMACKey", "a00476.html#aa93ad7f30b7e5244f9d6a8867d93d8f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Init", "a00476.html#a3fdec65dc2e3f184482a5c154485ac43", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tprime", "a00476.html#a25b3334cd0de70a0edc68a5dc512705d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Lprime", "a00476.html#a1810492f18e43afe11af97fa5380029e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_T", "a00476.html#aa1052cf741074a7381996a983a2b97af", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_L", "a00476.html#a60b11dcd8719cd91d38f59c824cd6586", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Finalize", "a00476.html#ad546d4caf80bb7972b6ec1f6724eb06a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Oneshot", "a00476.html#ac2e6371038ff061a7e9afc1c68ca92d8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tau", "a00476.html#a26f3889e037d04cf179854ecc5626aa4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Update", "a00476.html#a9b72e70cfdcfe565c8137c247c391cad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_SkeletonSM2", "a00476.html#ac6cb45adf8e2159cb4940731fda75d5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_finish", "a00476.html#af1b254ffb3ff6c302a49a7cea506761c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_process", "a00476.html#aafe41f6e0fdaf06415ab18041dc14ce0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_decrypt", "a00476.html#a744a15b342e5755cf65c23ae7abc794f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSM2_GenerateKeyPair", "a00476.html#a33953369f42b2fbe2cc03fffcfeb3a18", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_PreLoad", "a00476.html#a6d4c09e474fb14dd57238182b2bd0405", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Auto", "a00476.html#a52304a022625c41532e36dc9cc412e01", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Norm", "a00476.html#af954096516f4b0a064aaab61242bcf60", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi", "a00476.html#af25528ca047be9cd17f25915ba511fbe", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_ProcessMessageBlock_Sgi", "a00476.html#aa54519b160697f8a3a3d9d2774804e2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareToZero", "a00476.html#a570331403841e58b06818ad3eb4a9254", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareBoolean", "a00476.html#a6ae336742d65883774fcc156bac70f17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SignVerify_SelfTest", "a00476.html#a40d0bba28881aa415cec9c2f17cef6d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_SelfTest", "a00476.html#a926f10b0d6cf79fd223ac719661af0aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange", "a00476.html#a27b1195d097534edbd656b453ae41665", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Decrypt", "a00476.html#adce0a159f0195bfd3b3202c14d443772", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Encrypt", "a00476.html#a6b9064a343e90df555c01a69840b4ade", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ComputePrehash", "a00476.html#a46858757f0448881bfb5b976362e598c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_InvertPrivateKey", "a00476.html#a5ffb3c9d2b19f41ddad4f4c7bc1367d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Verify", "a00476.html#a85e6bbb0eb7f8882c2e1fcfd3630afa2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Sign", "a00476.html#a7c05592d624ea400ebfd4186b424ab96", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Export", "a00476.html#a5944005c62cf519298a0233f1040f5e7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Import", "a00476.html#a46957116f014006246cf5b6c5eb990a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointCheckCoordinate", "a00476.html#a78deb2ff982b6c1f661875cc96bca7d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAddOrDouble", "a00476.html#a319d9f9c233ad3216d78bdee40d85d44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccTransAffinePoint2Jac", "a00476.html#a20e09f68fee183a0a72383003978280e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenRandomBytes", "a00476.html#a1194af79934e4b10df1ecc1f3410d0be", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultMontgomery", "a00476.html#a9ee22e5d67d6420c5c97ca3325be95aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAdd", "a00476.html#a58a4e9b21f0282d1bbf331074086730e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointDouble", "a00476.html#add33dfaaf5dc1524fb80de713736cc58", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointConvert2Affine", "a00476.html#ad62e0604dbf8c6a11f8ae4aa9873c86e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccJacPointCheck", "a00476.html#af3525312cc53083eef904fe4116def83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointYNegNoInit", "a00476.html#a373b5e2e688256cf1a902a0251f9b93d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointWithInit", "a00476.html#a1a2318ebdf08dc9424e7849876f06e95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenerateZ", "a00476.html#aaa982bab3e2bca4944745a2ab73fdf63", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPrepareParameters", "a00476.html#a40407a78c03b756f1473b132b84ebf1c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccInit", "a00476.html#a5d4490b97d48f052cc5ae8e0b9b19c07", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_WrapHash", "a00476.html#a24e071304c79da164d0b2a9de2da7e17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccExitClear", "a00476.html#a1afe992130bd71473c5fe05cc331aafb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ValidateEncDecCtx", "a00476.html#a87cf506f751e9954c708dbc90a9d7816", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_UpdatePhase", "a00476.html#acfad55b72b266e939120285083f9e14f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecondPartOfInitPhase", "a00476.html#ae6f507a80191c77d69e7386518ae6972", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KDF", "a00476.html#a6568c7358966f164eee23cb43285346a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SetParamCrcValue", "a00476.html#a828994ad0f804e617a7e07bca102189c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_CheckParamCrc", "a00476.html#a7094367213755e5f28abcd5d8fcb81bb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_decrypt", "a00476.html#a021c10b424313f22ca727412c8232032", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_encrypt", "a00476.html#af9b305d02e6172426b78a713948c2c6c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleSM4Key", "a00476.html#a42ad76dea482e463f439c205bf961f54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_EngineSM4", "a00476.html#a1c84f94a01696a6acaba15cee18d4eb2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_SkeletonSM4", "a00476.html#accf7f3771c76c7a38b54833eb27b1890", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_key_agreement", "a00476.html#a23784a74d65494d0ce160820ccec2fcd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compare", "a00476.html#a97561ab6d84e5c61481c58875d381120", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_verify", "a00476.html#a3d28c31bb15392dfc0b220a2f751bf95", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Init", "a00476.html#a8529a63e7bf8c12120bb16d20412565e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Finish", "a00476.html#abafb1cad10fa72effeb8f8b3e9c13245", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PreHash", "a00476.html#a386fb4d2fe541064fde23698d990ac16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyAgreement_SelfTest", "a00476.html#aecccccccaba2bb4c218d883f689cdfa5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PrepareDigest", "a00476.html#af512e5b6851ab3bef9c6292cb4147e4a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_IncCounter", "a00476.html#a84fd147db2260bcd42b7ed322d4a3bd6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CountLeadingZerosWord", "a00476.html#a7e016043608c36083e9d0268cacb119f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_core_sm3_processMessageBlock", "a00476.html#a38d6caa672a703f3c1ece2ec83211aa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Engine", "a00476.html#a9bc8bafecbcf188eae62f89958f5af17", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleKey", "a00476.html#a54efc44e7803651f925fc83d45fd506c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccSecurePointMult", "a00476.html#abc49ef29a5241f8c219ef3e6771b02d0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultSplitScalar", "a00476.html#a3212d23f0256b037518bebad2fe49bb3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureExport", "a00476.html#a005b9ee1f6d7dd8f99ba787bc4e2b83c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureImport", "a00476.html#a054e472e8223ed151a92d468dc99b636", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Init", "a00476.html#a7735d68f5627ae89933af4a62c865474", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Finish", "a00476.html#ab213ec033ac03170051612f83cdc47e2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Ecb_EncDec_SelfTest", "a00476.html#a7bc28afd17d3be32a7d059b4a7488176", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Cbc_EncDec_SelfTest", "a00476.html#a02ab1dcebc2ed7f11b561aa501993752", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4Cmac_SelfTest", "a00476.html#a64a2425954c4c2847092d6c53ea275d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4CbcMac_SelfTest", "a00476.html#a2662471ad940cbf77a556afe060784a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Sm4Ccm_EncDec_SelfTest", "a00476.html#a5d16c7422bd44925bba53b33eb08a2c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_selftest", "a00476.html#a2b1d107aac529562f8283fe34c8a6d65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Init", "a00476.html#a168203877393cebcd8e419b7bac801a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_ProcessAad", "a00476.html#a593b8a032cd92f31fa28aa18d84d06ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Process", "a00476.html#a0507fcd6ea83160ed8ed6a638245c66e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Finish", "a00476.html#ad86a1df5f64b0584fea44d3eb7d8983d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_25", "a00476.html#a8132482524ba80cc20a2160c8706b51f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_26", "a00476.html#a530bedbf8f9b03af523d241ceba66fe5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_27", "a00476.html#a2d3d88d5ae13c49a3d2d5a78b181fd3c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_28", "a00476.html#a882291c08439feb48cfffc6e68279d24", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_29", "a00476.html#af9fe2ffcaec7c4c1bd35d12a1b74e82a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_30", "a00476.html#af933d924bebf402a702d642f351c5cce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_31", "a00476.html#ad39f438654d11098036c0df99962f64b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_32", "a00476.html#aee1938976403a5c79eca0bb8dd5faebd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_33", "a00476.html#a8a93c3f0c14d9f8521c2dd5e5fc30dfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_34", "a00476.html#a9c984c3fb25d7529423213c93d9f8f9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_35", "a00476.html#af0393aa4b210323a4bdd3a77465f9fd1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_36", "a00476.html#a71103760495f69814a275488d0b7f84e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_37", "a00476.html#adfff181704087908b57ccf29d1daf0d5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_38", "a00476.html#a3d61b27650154f5e9845ecbe4b8d98ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_39", "a00476.html#a958c0b734fce117612a844c2f5fab129", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_40", "a00476.html#aa7f65159fc5286f64f31291fdd7747c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_41", "a00476.html#aa2706b1659d4a57cbb6e73c80d6c9820", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_42", "a00476.html#a12cdd297b66541b02e158ca48acf8a44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_43", "a00476.html#a4d2c60eb3ac828d85994d15b5c930445", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_44", "a00476.html#a902ae13948f297215b11753ac81a37ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_45", "a00476.html#ad952fc07649b5764c2509dd2ae6b2295", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_46", "a00476.html#a540a95056ab5adb9e96b5e186c23846c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_47", "a00476.html#a3cf9d7e6a769b2f8a551d793387b69a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_48", "a00476.html#ac68423aaf8ac6fc407456855e9a39ffb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_49", "a00476.html#aa0bd8851a9a3b052cad9a7e799d2ae8b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_50", "a00476.html#afe7beda4441de86bbe7841c0204aaaa9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_51", "a00476.html#a03d8371794c127d6fc2143b4986e29c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_52", "a00476.html#ad2a88b0dc67d1879407fc23cc7548e61", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_53", "a00476.html#a4d558cf4eaccd41db51b352f23050c1d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_54", "a00476.html#ad4c4e7ff3431115e94667eec4b06528c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_55", "a00476.html#af9895806bb9c417cb05dfe2780d55dc9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_56", "a00476.html#a4ac96d218a8ad4ac499d410ba22b9134", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_57", "a00476.html#adbcdf80b07a864dec9f8b644998fa572", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_58", "a00476.html#af95051abd168021201b41263afc27997", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_59", "a00476.html#a6aa7971328aa479c0da2833df856cf4c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_60", "a00476.html#a50651fb277286eff3acc0d06d72697c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_61", "a00476.html#a012cfd918798d1326072c1726fe01093", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_62", "a00476.html#a256ea0723330572e7d9c061faa1e6c37", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_63", "a00476.html#ad66c39bd2950369c3af0e0f8932dabf3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_64", "a00476.html#a5577baef628bcca70dc207aca1c2a35c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_65", "a00476.html#a1d45288deb2f9a222790897b65c04537", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_66", "a00476.html#afa7d406f7dba2b26c32794b5fa1f16f0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_67", "a00476.html#abc47f32a8f1b751fac5ab19a0c9d9ab9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_68", "a00476.html#a186b67fb5cc9f5ec270f19ca5a730d41", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_69", "a00476.html#a2c934879af585954f51a526c3a064ca3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_70", "a00476.html#a964abddb0ba8ffb7c6e1a0692ea2d36d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_71", "a00476.html#af802bae8bfe9b17f73374615aba02389", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_72", "a00476.html#a30a4784ceff8a70fb9b6c376e0003fa1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_73", "a00476.html#ac17b9377899c77eb33204e0994942fed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_74", "a00476.html#ad05edb3b4695e306d769b165f4133086", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_75", "a00476.html#a0d1f2aefe17d0c5b0b15e9c04a9dc4e3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_76", "a00476.html#ad65dbb9c0e08ce6b1c47ed2b5f618eb5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_77", "a00476.html#a51a4080c75137a693a26e8f6059a8d44", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_78", "a00476.html#aab2f8a50f2cd877bdb462ed20a5741d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_79", "a00476.html#a791156b617efbc9bd3b8bc6d8a9b9d6d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_80", "a00476.html#a21e371a9cfb7fffd3a824d78d93dbeaf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_81", "a00476.html#a0dbe012a5502caf7bec7086c584f950e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_82", "a00476.html#ace9408a72baccb1fd2d534efd0491b2b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_83", "a00476.html#a00ced9ef329037b9d8c2f2af5f1d2573", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_84", "a00476.html#ab3f400854d374b642a339dc57ee9262c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_85", "a00476.html#a503a62cdf31814a0cf8633c96661d0a7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_86", "a00476.html#a5eddea8b14e3dc22fbeaf3c485360c03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_87", "a00476.html#a431c5ebb14f7ee617619a114bf2edaf6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_88", "a00476.html#a09b3eb131847014f10793b8678f7229f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_89", "a00476.html#aa67c7137e3389554e09d8ac09b8bacca", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_90", "a00476.html#a1cb36cba20ab0aeb9fdd6b6b2f6cd0a9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_91", "a00476.html#a643b8947c38e3cf6302b1bd368056623", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_92", "a00476.html#a4984f9271caa382baa71f74db1baf56b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_93", "a00476.html#ae084fbc68f55489618dec3b7d30e2fa6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_94", "a00476.html#ab7279a6affb10ba7944f08261737efdf", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_95", "a00476.html#a8c707c439559ed5a7866453e2e40888b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_96", "a00476.html#a1b25807134a5dec839c20aa94c021f62", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_97", "a00476.html#a68d817a1bd042dca613894ac5520c07a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_98", "a00476.html#a03da12aa15775e843f28f84ec003133b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_99", "a00476.html#a9fc964aa7898a5baf9d748496163bbfd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_100", "a00476.html#a14d84a609fe4c77c504c0a7a6700123c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_101", "a00476.html#a10af01339cf9462a4326dad972419f4d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_102", "a00476.html#afe1446bdb2c61dd7aa2e5f50e8e4ffed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_103", "a00476.html#a35c36d346f17a2e1426f70263fff1421", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_104", "a00476.html#a08a77fbdbf4cb966f72a03c34a6e0e35", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_105", "a00476.html#a083722d626e4fc47bf5bd8205f71431d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_106", "a00476.html#aeaa5e9bcdaa402d4436ba0b3ea5c7f86", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_107", "a00476.html#a1eb71b036d2e2d85f60e144a71f9945d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_108", "a00476.html#a7dd76ed937744d3b38b64bee29edb31f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_109", "a00476.html#a322696ed29f1f51ccc9c920f0c0cbec1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_110", "a00476.html#a46e4c3a8221e8505a8706c839ec553ab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_111", "a00476.html#a2a7f576b1cb04bf4b9ec08445bf1919a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_112", "a00476.html#a97f66ea16d30e392c38dad31eb17db2a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_113", "a00476.html#ae704bd5b450ed08faf915d53209dd00d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_114", "a00476.html#a9948395b93b34599900eab5c4282a499", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_115", "a00476.html#a13c7aba51ad41a94d6f52cd5fdd5aa40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_116", "a00476.html#a1853974f007c4b2982a99890a727fec5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_117", "a00476.html#a777ce2e18860c83860e671e9b838bbd4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_118", "a00476.html#a7a7be4446f323aa45110851047ae5aec", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_119", "a00476.html#ab29cba72162bfe13f133609d6b5e5cda", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_120", "a00476.html#a173b0d22fad6ff07509acb65189bc75d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_121", "a00476.html#a2168c5a4849b9a0fa721a614a53b7752", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_122", "a00476.html#a9e44e7b6b6ee455ed82b0e38e99218f6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_123", "a00476.html#a67316183e4d1b75c3eb7078feb74b659", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_124", "a00476.html#ab2058227baf2e27ca53e66f467d49f34", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_125", "a00476.html#a81d884b59662f4f79a27e7089db993aa", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_126", "a00476.html#ae52eba8c5d685c7063c615a1ffb7d44e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_127", "a00476.html#a3f850985dd25d904f90dd0d2252f32e9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_128", "a00476.html#ad12bd5c787102e401c6c68760aae6c8c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_129", "a00476.html#abcee8e363771297d16d1b0743128fa27", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_130", "a00476.html#a6b41d78632db799fc7b98c384ab71513", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_131", "a00476.html#a9ef3f2d628c7b7a17fe163814c40d91a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_132", "a00476.html#ab454da2e09673f21b8f3edf9fcf2251b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_133", "a00476.html#af6e34a6f2bb33fa8b712e5f047ad1c83", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_134", "a00476.html#aca28827966526b65572dd3cf33b7ac7a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_135", "a00476.html#a7e9d735295e15445481f129d92c20353", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_136", "a00476.html#a7216a34d7493a4bf857429ff84102379", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_137", "a00476.html#ad2f6061dc8af889e554c54c136107f0b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_138", "a00476.html#a1cde41f81bf2d10ea1de9d8665e2fa84", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_139", "a00476.html#ad90a21b37338a17a8558e2d11df0d362", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_140", "a00476.html#a00b6d861255f0a5b665212400489f4dd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_141", "a00476.html#af9e37f2c9a10b4835537e12813435b16", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_142", "a00476.html#addd1cab76ca5fea1715e1b8091e6a572", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_143", "a00476.html#a4d65335fcbc27a2c44bdbb6d7161208d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_144", "a00476.html#a720795ec1914e4917603d82585d9675b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_145", "a00476.html#ac9639762937ec1ab7ef8e4a62f5d41e4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_146", "a00476.html#a688b263e0b057ff692ade6a0a85b9def", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_147", "a00476.html#a65ed55a0d71e99565de5d1e226b0f476", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_148", "a00476.html#a00a0418146594112517159354f75a2fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_149", "a00476.html#a4c7feef0ae396521eaf8e812db02bde7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_150", "a00476.html#a5bee8a216fdf30c298ed13530f1b316e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_151", "a00476.html#a5fcf03271858ae4f624c277e7a46d689", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_152", "a00476.html#a4d3bb138e5a19046efed96f510e539ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_153", "a00476.html#a63e9695dacc67089260c9c3bfd789cde", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_154", "a00476.html#a72982f5578ad51f8210e74ef66b5e421", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_155", "a00476.html#a95257920ae6f738aedca6138291d3041", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_156", "a00476.html#a6dbf145945b52eed2829ed907407cfc2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_157", "a00476.html#a0680b2ba6f8684f99f8800dc22c14c54", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_158", "a00476.html#abef7648dd0fdaf97f657251ccaa0e8d3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_159", "a00476.html#ad467b3a5d3f6526b9aa5a666764625a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_160", "a00476.html#a760cf1a65810400d71680b85c6901e8a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_161", "a00476.html#a210eb7fc23cb8c8e48dcf91e4d44174c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_162", "a00476.html#a05147c117e760306175b6214cd817d41", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_163", "a00476.html#ad6ff1088da896ab9426582d93d6313c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_164", "a00476.html#ae5c988cd6cd0c901ef0c1acdc89748ad", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxClOscca_165", "a00476.html#a2b64fa2c4de582bb8a58566ea0ac5ce2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00476_source.html b/components/els_pkc/doc/mcxn/html/a00476_source.html new file mode 100644 index 000000000..c412e2a1c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00476_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_FunctionIdentifiers.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClOscca_FunctionIdentifiers.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
23 #define MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
24 
25 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_encrypt (0x1766u)
26 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_encrypt_Sm4 (0x5AE4u)
27 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_decrypt_Sm4 (0x7C26u)
28 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_OnlyVerify_SelfTest (0x1F43u)
29 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_SignVerify_SelfTest (0x3BE0u)
30 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_EncDec_selftest (0x3A2Bu)
31 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange_SelfTest (0x3A8Eu)
32 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_finish (0x1E63u)
33 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_process (0x1B8Du)
34 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compute (0x5A87u)
35 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_init (0x2E4Bu)
36 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_SM4_Gen_K1K2 (0x413Fu)
37 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Finalize (0x52D9u)
38 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Finalize (0x14EDu)
39 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Update (0x7247u)
40 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Update (0x14B7u)
41 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Init (0x06F5u)
42 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Init (0x489Fu)
43 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Oneshot (0x3BA2u)
44 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Oneshot (0x11BDu)
45 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_reseed (0x49DCu)
46 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_Sm4 (0x724Eu)
47 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_process_Sm4 (0x68AEu)
48 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_decrypt_Sm4 (0x7D0Au)
49 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_encrypt_Sm4 (0x54C7u)
50 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_decrypt_Sm4 (0x39ACu)
51 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_encrypt_Sm4 (0x21DEu)
52 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_FastSecureXor (0x6C35u)
53 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_switch_endianness (0x2C1Fu)
54 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_finish_sm3 (0x60EDu)
55 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_process_sm3 (0x519Du)
56 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_oneShotSkeleton_sm3 (0x5572u)
57 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_finishSkeleton (0x70A7u)
58 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_processSkeleton (0x06EBu)
59 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_oneShotSkeleton (0x574Au)
60 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_selftest (0x5335u)
61 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PowerOnTest (0x155Eu)
62 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_DeliverySimpleTest (0x6E49u)
63 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PokerTest (0x31ABu)
64 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_generate (0x563Cu)
65 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_init (0x7BC0u)
66 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SkeletonCcm (0x30BEu)
67 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CalcMontInverse (0x6B2Cu)
68 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_EngineCcm (0x2E47u)
69 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_Internal_Ctr (0x457Cu)
70 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeModInv (0x2BB1u)
71 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_LeadingZeros (0x496Eu)
72 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_MultipleShiftRotate_Index (0x52F8u)
73 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GeneratePointerTable (0x6D54u)
74 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeQSquared (0x1A57u)
75 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeNDash (0x3B61u)
76 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_StartFupProgram (0x161Fu)
77 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Op (0x5A6Cu)
78 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetFupTable (0x339Au)
79 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_WaitforFinish (0x156Du)
80 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GetWordSize (0x1E4Du)
81 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetWordSize (0x6798u)
82 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Init (0x16ABu)
83 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Reset (0x4C73u)
84 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init (0x61CBu)
85 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_encrypt (0x168Fu)
86 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_decrypt (0x6F82u)
87 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process (0x2BD1u)
88 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process_adata (0x0B2Fu)
89 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_finish (0x1D8Bu)
90 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_verify (0x4B87u)
91 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_crypt (0x4BD4u)
92 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_encrypt (0x5CA9u)
93 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_decrypt (0x6A5Au)
94 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_prepareHMACKey (0x469Bu)
95 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Init (0x2787u)
96 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tprime (0x3B43u)
97 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Lprime (0x2CBAu)
98 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_T (0x6D45u)
99 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_L (0x743Cu)
100 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Finalize (0x45B5u)
101 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Oneshot (0x2BA3u)
102 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tau (0x383Du)
103 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Update (0x5C0Fu)
104 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_SkeletonSM2 (0x41F6u)
105 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_finish (0x3F11u)
106 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_process (0x5A5Cu)
107 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_decrypt (0x1C5Du)
108 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSM2_GenerateKeyPair (0x392Bu)
109 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_PreLoad (0x0DAEu)
110 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Auto (0x1CC7u)
111 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Norm (0x39E2u)
112 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi (0x5F24u)
113 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_ProcessMessageBlock_Sgi (0x4D17u)
114 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareToZero (0x50FAu)
115 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareBoolean (0x5D62u)
116 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SignVerify_SelfTest (0x6437u)
117 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_SelfTest (0x21CFu)
118 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange (0x52ABu)
119 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Decrypt (0x6E38u)
120 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Encrypt (0x4D0Fu)
121 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ComputePrehash (0x60F6u)
122 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_InvertPrivateKey (0x5EB0u)
123 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Verify (0x48F9u)
124 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Sign (0x3947u)
125 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Export (0x5933u)
126 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Import (0x1B4Bu)
127 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointCheckCoordinate (0x4B71u)
128 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAddOrDouble (0x4A7Au)
129 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccTransAffinePoint2Jac (0x09E7u)
130 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenRandomBytes (0x5E62u)
131 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultMontgomery (0x5C63u)
132 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAdd (0x0D6Eu)
133 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointDouble (0x0D9Du)
134 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointConvert2Affine (0x4973u)
135 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccJacPointCheck (0x2A97u)
136 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointYNegNoInit (0x2E78u)
137 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointWithInit (0x2F62u)
138 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenerateZ (0x4B55u)
139 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPrepareParameters (0x722Eu)
140 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccInit (0x11E7u)
141 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_WrapHash (0x6E58u)
142 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccExitClear (0x7E06u)
143 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ValidateEncDecCtx (0x7496u)
144 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_UpdatePhase (0x7345u)
145 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecondPartOfInitPhase (0x7670u)
146 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KDF (0x63B4u)
147 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SetParamCrcValue (0x4793u)
148 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_CheckParamCrc (0x4A79u)
149 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_decrypt (0x16B3u)
150 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_encrypt (0x293Du)
151 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleSM4Key (0x58B9u)
152 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_EngineSM4 (0x4E74u)
153 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_SkeletonSM4 (0x65CAu)
154 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_key_agreement (0x362Eu)
155 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compare (0x3D94u)
156 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_verify (0x532Eu)
157 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Init (0x43A7u)
158 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Finish (0x387Cu)
159 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PreHash (0x22D7u)
160 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyAgreement_SelfTest (0x70F2u)
161 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PrepareDigest (0x1DF0u)
162 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_IncCounter (0x2BACu)
163 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CountLeadingZerosWord (0x7741u)
164 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_core_sm3_processMessageBlock (0x4B74u)
165 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Engine (0x153Eu)
166 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleKey (0x1774u)
167 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccSecurePointMult (0x398Eu)
168 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultSplitScalar (0x70C7u)
169 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureExport (0x3D51u)
170 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureImport (0x09FCu)
171 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Init (0x31B9u)
172 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Finish (0x25DCu)
173 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Ecb_EncDec_SelfTest (0x1747u)
174 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Cbc_EncDec_SelfTest (0x06E7u)
175 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4Cmac_SelfTest (0x29BAu)
176 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4CbcMac_SelfTest (0x53D8u)
177 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Sm4Ccm_EncDec_SelfTest (0x2D0Fu)
178 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_selftest (0x7474u)
179 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Init (0x13F1u)
180 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_ProcessAad (0x5D15u)
181 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Process (0x3DB0u)
182 #define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Finish (0x472Du)
183 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_25 (0x7E18u)
184 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_26 (0x1576u)
185 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_27 (0x5C36u)
186 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_28 (0x3A65u)
187 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_29 (0x0B73u)
188 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_30 (0x29ABu)
189 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_31 (0x6D85u)
190 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_32 (0x4F83u)
191 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_33 (0x09BDu)
192 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_34 (0x6167u)
193 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_35 (0x6A2Du)
194 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_36 (0x1BD4u)
195 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_37 (0x554Du)
196 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_38 (0x6F60u)
197 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_39 (0x46A7u)
198 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_40 (0x1BE1u)
199 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_41 (0x4EA9u)
200 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_42 (0x59ACu)
201 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_43 (0x7A89u)
202 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_44 (0x7691u)
203 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_45 (0x2277u)
204 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_46 (0x6EA2u)
205 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_47 (0x3F14u)
206 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_48 (0x164Fu)
207 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_49 (0x3D0Eu)
208 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_50 (0x0D7Au)
209 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_51 (0x13B3u)
210 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_52 (0x60E7u)
211 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_53 (0x6794u)
212 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_54 (0x127Du)
213 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_55 (0x255Eu)
214 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_56 (0x583Eu)
215 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_57 (0x235Du)
216 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_58 (0x2CA7u)
217 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_59 (0x65AAu)
218 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_60 (0x553Cu)
219 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_61 (0x4DA3u)
220 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_62 (0x179Cu)
221 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_63 (0x36A6u)
222 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_64 (0x16DAu)
223 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_65 (0x661Du)
224 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_66 (0x0FA5u)
225 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_67 (0x49CEu)
226 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_68 (0x0B3Du)
227 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_69 (0x7E22u)
228 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_70 (0x52E5u)
229 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_71 (0x133Du)
230 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_72 (0x3B91u)
231 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_73 (0x5C55u)
232 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_74 (0x2C5Bu)
233 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_75 (0x31E6u)
234 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_76 (0x16F8u)
235 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_77 (0x21F5u)
236 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_78 (0x7B14u)
237 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_79 (0x6F42u)
238 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_80 (0x36A5u)
239 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_81 (0x3565u)
240 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_82 (0x6715u)
241 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_83 (0x4D4Eu)
242 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_84 (0x21FAu)
243 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_85 (0x1D8Eu)
244 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_86 (0x0E9Eu)
245 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_87 (0x4E39u)
246 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_88 (0x12EBu)
247 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_89 (0x431Fu)
248 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_90 (0x12EDu)
249 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_91 (0x3333u)
250 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_92 (0x5E8Cu)
251 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_93 (0x56CAu)
252 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_94 (0x5566u)
253 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_95 (0x151Fu)
254 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_96 (0x5BA2u)
255 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_97 (0x4F25u)
256 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_98 (0x5077u)
257 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_99 (0x59A6u)
258 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_100 (0x354Du)
259 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_101 (0x2EB1u)
260 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_102 (0x3762u)
261 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_103 (0x5764u)
262 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_104 (0x651Du)
263 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_105 (0x0F2Bu)
264 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_106 (0x23BAu)
265 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_107 (0x65C9u)
266 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_108 (0x393Au)
267 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_109 (0x5273u)
268 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_110 (0x239Eu)
269 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_111 (0x6876u)
270 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_112 (0x37C4u)
271 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_113 (0x5CA3u)
272 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_114 (0x792Cu)
273 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_115 (0x4C5Bu)
274 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_116 (0x5E8Au)
275 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_117 (0x27E2u)
276 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_118 (0x3EA1u)
277 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_119 (0x6DC4u)
278 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_120 (0x09F6u)
279 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_121 (0x5656u)
280 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_122 (0x59B1u)
281 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_123 (0x4D71u)
282 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_124 (0x7265u)
283 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_125 (0x78D8u)
284 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_126 (0x0E57u)
285 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_127 (0x217Bu)
286 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_128 (0x525Du)
287 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_129 (0x3873u)
288 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_130 (0x4C7Au)
289 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_131 (0x0F4Du)
290 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_132 (0x364Eu)
291 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_133 (0x1AEAu)
292 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_134 (0x3E85u)
293 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_135 (0x2C37u)
294 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_136 (0x2A6Du)
295 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_137 (0x38D6u)
296 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_138 (0x6707u)
297 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_139 (0x51CDu)
298 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_140 (0x7859u)
299 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_141 (0x3713u)
300 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_142 (0x45F2u)
301 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_143 (0x29B3u)
302 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_144 (0x51F2u)
303 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_145 (0x5671u)
304 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_146 (0x435Bu)
305 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_147 (0x18DBu)
306 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_148 (0x1B71u)
307 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_149 (0x45B9u)
308 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_150 (0x46DAu)
309 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_151 (0x233Du)
310 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_152 (0x689Bu)
311 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_153 (0x2E8Eu)
312 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_154 (0x2E93u)
313 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_155 (0x7B28u)
314 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_156 (0x469Eu)
315 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_157 (0x3A2Du)
316 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_158 (0x714Bu)
317 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_159 (0x7AA1u)
318 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_160 (0x2C9Du)
319 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_161 (0x19D9u)
320 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_162 (0x5E16u)
321 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_163 (0x0BD5u)
322 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_164 (0x6517u)
323 #define MCUX_CSSL_FP_FUNCID_mcuxClOscca_165 (0x433Eu)
324 #endif /* MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00479.html b/components/els_pkc/doc/mcxn/html/a00479.html new file mode 100644 index 000000000..dee9f6187 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00479.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_Memory.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros | +Functions
+
+
mcuxClOscca_Memory.h File Reference
+
+
+ +

: Macros for alignment memory +More...

+
#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClOscca_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + +

+Macros

+#define MCUXCLOSCCA_SIZE_ALIGN_OFFSET
 
+#define mcuxClOscca_alignAddress(address)
 
+#define mcuxClOscca_alignSize(size)
 
+#define mcuxClOscca_alignAddressWithOffset(address, offset)
 
+#define mcuxClOscca_alignAddressToBoundary(address, boundary)
 
+ + + + + +

+Functions

+void mcuxClOscca_FastSecureXor (void *pTgt, void *pSrc1, void *pSrc2, uint32_t length)
 
+void mcuxClOscca_switch_endianness (uint32_t *ptr, uint32_t length)
 
+

Detailed Description

+

: Macros for alignment memory

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00479.js b/components/els_pkc/doc/mcxn/html/a00479.js new file mode 100644 index 000000000..f5808f51a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00479.js @@ -0,0 +1,10 @@ +var a00479 = +[ + [ "MCUXCLOSCCA_SIZE_ALIGN_OFFSET", "a00479.html#aa3a71a50c5a16ac11d40fca22e0e8e6a", null ], + [ "mcuxClOscca_alignAddress", "a00479.html#a4d7d960d5c32329501e917a5ec57bbfc", null ], + [ "mcuxClOscca_alignSize", "a00479.html#abed72009d14359c88321efd18d77d518", null ], + [ "mcuxClOscca_alignAddressWithOffset", "a00479.html#a568d2c25122791e10569de52d2257d0a", null ], + [ "mcuxClOscca_alignAddressToBoundary", "a00479.html#adecf327b9cbf358250b83b0adf2484b9", null ], + [ "mcuxClOscca_FastSecureXor", "a00479.html#abd4377e6f133173e8dcef7e841659c5c", null ], + [ "mcuxClOscca_switch_endianness", "a00479.html#af3ac8e537c7ce9fc0ea5f22bb33192e8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00479_source.html b/components/els_pkc/doc/mcxn/html/a00479_source.html new file mode 100644 index 000000000..bf62f1536 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00479_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_Memory.h Source File + + + + + + + + + + + + + + + + +
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+
mcuxClOscca_Memory.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2016, 2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 /* Security Classification: Company Confidential */
14 /*--------------------------------------------------------------------------*/
15 
23 #ifndef MCUXCLOSCCA_MEMORY_H_
24 #define MCUXCLOSCCA_MEMORY_H_
25 
26 #include <mcuxClConfig.h> // Exported features flags header
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClOscca_FunctionIdentifiers.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 #define MCUXCLOSCCA_SIZE_ALIGN_OFFSET (sizeof(size_t) - 1U)
35 
36 #define mcuxClOscca_alignAddress(address) \
37  ((void*)( (((size_t)(address)) + (sizeof(size_t) - 1U)) \
38  & ((size_t)(~(sizeof(size_t) - 1U))) ))
39 
40 #define mcuxClOscca_alignSize(size) \
41  ((size_t)(((size_t)(size)) + (sizeof(size_t) - 1U)) \
42  & ((size_t)(~(sizeof(size_t) - 1U))) )
43 
44 #define mcuxClOscca_alignAddressWithOffset(address, offset) \
45  ((void*)( (((size_t)(address) + (size_t)(offset)) + (sizeof(size_t) - 1U)) \
46  & ((size_t)(~(sizeof(size_t) - 1U))) ))
47 
48 #define mcuxClOscca_alignAddressToBoundary(address, boundary) \
49  ((void*)( (((size_t)(address)) + (boundary - 1U)) \
50  & ((size_t)(~(boundary - 1U))) ))
51 
52 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOscca_FastSecureXor)
53 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_FastSecureXor(void *pTgt,
54  void *pSrc1,
55  void *pSrc2,
56  uint32_t length);
57 
58 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOscca_switch_endianness)
59 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_switch_endianness(uint32_t *ptr, uint32_t length);
60 
61 #ifdef __cplusplus
62 } /* extern "C" */
63 #endif
64 
65 #endif /* MCUXCLOSCCA_MEMORY_H_ */
mcuxClOscca_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00482.html b/components/els_pkc/doc/mcxn/html/a00482.html new file mode 100644 index 000000000..5fb455bf5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00482.html @@ -0,0 +1,185 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_PlatformTypes.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Data Structures | +Macros | +Typedefs | +Variables
+
+
mcuxClOscca_PlatformTypes.h File Reference
+
+
+ +

: Platform type definitions +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <platform_specific_headers.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClOscca_ScratchPad_t
 global scratch pad structure definition More...
 
+ + + +

+Macros

+#define MCUX_CLOSCCA_SCRATCHPAD_SECTION
 
+ + + + + + + +

+Typedefs

+typedef uint32_t mcuxClOscca_Size_t
 
+typedef uint32_t mcuxClOscca_Uint_t
 
+typedef int32_t mcuxClOscca_Int_t
 
+ + + + +

+Variables

mcuxClOscca_ScratchPad_t MCUX_CLOSCCA_SCRATCHPAD_SECTION gmcuxClOscca_ScratchPad
 global scratch pad object More...
 
+

Detailed Description

+

: Platform type definitions

+

Variable Documentation

+ +

◆ gmcuxClOscca_ScratchPad

+ +
+
+ + + + +
mcuxClOscca_ScratchPad_t MCUX_CLOSCCA_SCRATCHPAD_SECTION gmcuxClOscca_ScratchPad
+
+ +

global scratch pad object

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00482.js b/components/els_pkc/doc/mcxn/html/a00482.js new file mode 100644 index 000000000..2e48c4969 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00482.js @@ -0,0 +1,9 @@ +var a00482 = +[ + [ "mcuxClOscca_ScratchPad_t", "a01249.html", "a01249" ], + [ "MCUX_CLOSCCA_SCRATCHPAD_SECTION", "a00482.html#ac438f82df94a0dea75e654d301de3ee7", null ], + [ "mcuxClOscca_Size_t", "a00482.html#a2e3f534011a27f600fd71444c8aa4b7e", null ], + [ "mcuxClOscca_Uint_t", "a00482.html#a1221f25b4eada35e16ead85a3587dba2", null ], + [ "mcuxClOscca_Int_t", "a00482.html#aec73edcb9b0dc6107be06f7bd0a97caa", null ], + [ "gmcuxClOscca_ScratchPad", "a00482.html#ac37c24690a87ce8d10e039d46b426a2c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00482_source.html b/components/els_pkc/doc/mcxn/html/a00482_source.html new file mode 100644 index 000000000..b76488a5a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00482_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_PlatformTypes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOscca_PlatformTypes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2016, 2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 /* Security Classification: Company Confidential */
14 /*--------------------------------------------------------------------------*/
15 
22 #ifndef MCUXCLOSCCA_PLATFORMTYPES_H_
23 #define MCUXCLOSCCA_PLATFORMTYPES_H_
24 
25 #include <stdint.h>
26 #include <stddef.h>
27 #include <stdbool.h>
28 #include <platform_specific_headers.h>
29 
30 typedef uint32_t mcuxClOscca_Size_t;
31 typedef uint32_t mcuxClOscca_Uint_t;
32 typedef int32_t mcuxClOscca_Int_t;
33 
37 typedef struct
38 {
39  volatile uint16_t securityCounter;
40  volatile uint16_t stackPointerBackup;
41  uint32_t generalPurposeValue;
42 } mcuxClOscca_ScratchPad_t;
43 
44 #define MCUX_CLOSCCA_SCRATCHPAD_SECTION __attribute__((section(".data.gmcuxClOscca_ScratchPad")))
45 
49 extern mcuxClOscca_ScratchPad_t MCUX_CLOSCCA_SCRATCHPAD_SECTION gmcuxClOscca_ScratchPad;
50 
51 #endif /* MCUXCLOSCCA_PLATFORMTYPES_H_ */
gmcuxClOscca_ScratchPad
mcuxClOscca_ScratchPad_t MCUX_CLOSCCA_SCRATCHPAD_SECTION gmcuxClOscca_ScratchPad
global scratch pad object
+
mcuxClOscca_ScratchPad_t
global scratch pad structure definition
Definition: mcuxClOscca_PlatformTypes.h:37
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00485.html b/components/els_pkc/doc/mcxn/html/a00485.html new file mode 100644 index 000000000..0bf49f363 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00485.html @@ -0,0 +1,183 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ +
+
+Data Structures | +Typedefs
+
+
mcuxClOscca_Types.h File Reference
+
+
+ +

: Global type definitions +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClOscca_MPInt_t
 Structure for multi-precision integer used in asymetric cryptography. More...
 
+ + + + + + + +

+Typedefs

typedef struct mcuxClOscca_Rng_Ctx_t mcuxClOscca_Rng_Ctx_t
 The RNG context forward declaration. More...
 
typedef struct mcuxClOscca_MPInt_t mcuxClOscca_MPInt_t
 Structure for multi-precision integer used in asymetric cryptography. More...
 
+

Detailed Description

+

: Global type definitions

+

Typedef Documentation

+ +

◆ mcuxClOscca_Rng_Ctx_t

+ +
+
+ + + + +
typedef struct mcuxClOscca_Rng_Ctx_t mcuxClOscca_Rng_Ctx_t
+
+ +

The RNG context forward declaration.

+ +
+
+ +

◆ mcuxClOscca_MPInt_t

+ +
+
+ + + + +
typedef struct mcuxClOscca_MPInt_t mcuxClOscca_MPInt_t
+
+ +

Structure for multi-precision integer used in asymetric cryptography.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00485.js b/components/els_pkc/doc/mcxn/html/a00485.js new file mode 100644 index 000000000..5a6da8fe0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00485.js @@ -0,0 +1,6 @@ +var a00485 = +[ + [ "mcuxClOscca_MPInt_t", "a01253.html", "a01253" ], + [ "mcuxClOscca_Rng_Ctx_t", "a00485.html#ab3464aacd01247830fe9a57570620d23", null ], + [ "mcuxClOscca_MPInt_t", "a00485.html#a167ac5bec44e63a398cce013bd85476f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00485_source.html b/components/els_pkc/doc/mcxn/html/a00485_source.html new file mode 100644 index 000000000..bc39e3373 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00485_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+ +
+
+
mcuxClOscca_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2016, 2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 /* Security Classification: Company Confidential */
14 /*--------------------------------------------------------------------------*/
15 
23 #ifndef MCUXCLOSCCA_TYPES_H_
24 #define MCUXCLOSCCA_TYPES_H_
25 
26 #include <stdint.h>
27 #include <stddef.h>
28 #include <stdbool.h>
29 
30 #ifdef __cplusplus
31 extern "C"
32 {
33 #endif
34 
35 #ifndef __RNG_TYPES_DEFINED_
36 
39 typedef struct mcuxClOscca_Rng_Ctx_t mcuxClOscca_Rng_Ctx_t;
40 #endif
41 
43 typedef struct mcuxClOscca_MPInt_t
44 {
45  uint8_t const *pMPInt;
46  uint16_t wNumBytes;
47 } mcuxClOscca_MPInt_t;
48 
49 #ifdef __cplusplus
50 } /* extern "C" */
51 #endif
52 
53 #endif /* MCUXCLOSCCA_TYPES_H_ */
mcuxClOscca_MPInt_t
Structure for multi-precision integer used in asymetric cryptography.
Definition: mcuxClOscca_Types.h:43
+
mcuxClOscca_MPInt_t
struct mcuxClOscca_MPInt_t mcuxClOscca_MPInt_t
Structure for multi-precision integer used in asymetric cryptography.
+
mcuxClOscca_Rng_Ctx_t
struct mcuxClOscca_Rng_Ctx_t mcuxClOscca_Rng_Ctx_t
The RNG context forward declaration.
Definition: mcuxClOscca_Types.h:39
+
mcuxClOscca_MPInt_t::pMPInt
uint8_t const * pMPInt
Pointer to the multi precision integer.
Definition: mcuxClOscca_Types.h:45
+
mcuxClOscca_MPInt_t::wNumBytes
uint16_t wNumBytes
Length in bytes of multi precision integer.
Definition: mcuxClOscca_Types.h:46
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00488.html b/components/els_pkc/doc/mcxn/html/a00488.html new file mode 100644 index 000000000..18f8d3c54 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00488.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOsccaPkc.h File Reference
+
+
+ +

Top level header of mcuxClOsccaPkc component (PKC hardware driver) +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClOsccaPkc_Types.h>
+#include <mcuxClOsccaPkc_Functions.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClOsccaPkc component (PKC hardware driver)

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00488_source.html b/components/els_pkc/doc/mcxn/html/a00488_source.html new file mode 100644 index 000000000..11cf816bd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00488_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOsccaPkc.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
23 #ifndef MCUXCLOSCCAPKC_H_
24 #define MCUXCLOSCCAPKC_H_
25 
26 #include <mcuxClConfig.h> // Exported features flags header
27 #include <mcuxClOsccaPkc_Types.h>
28 #include <mcuxClOsccaPkc_Functions.h>
29 
30 
31 #endif /* MCUXCLOSCCAPKC_H_ */
mcuxClOsccaPkc_Functions.h
APIs of mcuxClOsccaPkc component.
+
mcuxClOsccaPkc_Types.h
Type definitions of mcuxClOsccaPkc component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00491.html b/components/els_pkc/doc/mcxn/html/a00491.html new file mode 100644 index 000000000..2249c4500 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00491.html @@ -0,0 +1,241 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs | +Functions | +Variables
+
+
mcuxClOsccaPkc_Functions.h File Reference
+
+
+ +

APIs of mcuxClOsccaPkc component. +More...

+
#include <stdint.h>
+#include <stdbool.h>
+#include <mcuxClConfig.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClOscca_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClOsccaPkc_State_t
 Structure of PKC state backup. More...
 
+ + + + + + + +

+Typedefs

typedef struct mcuxClOsccaPkc_State_t mcuxClOsccaPkc_State_t
 Structure of PKC state backup. More...
 
typedef const struct mcuxClOsccaPkc_FUPEntry * mcuxClOsccaPkc_PtrFUPEntry_t
 type of FUP program address. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Reset) void mcuxClOsccaPkc_Reset(mcuxClOsccaPkc_State_t *state)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Init) void mcuxClOsccaPkc_Init(mcuxClOsccaPkc_State_t *state)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_SetWordSize) void mcuxClOsccaPkc_SetWordSize(uint32_t redmul)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_GetWordSize) uint32_t mcuxClOsccaPkc_GetWordSize(void)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_WaitforFinish) void mcuxClOsccaPkc_WaitforFinish(void)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_SetFupTable) void mcuxClOsccaPkc_SetFupTable(void *pUPTRT)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Op) void mcuxClOsccaPkc_Op(uint32_t mode
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_StartFupProgram) void mcuxClOsccaPkc_StartFupProgram(mcuxClOsccaPkc_PtrFUPEntry_t fupProgram
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeNDash) void mcuxClOsccaPkc_ComputeNDash(uint32_t iNiTiXiX)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeQSquared) void mcuxClOsccaPkc_ComputeQSquared(uint32_t iQiMiTiX
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_GeneratePointerTable) void mcuxClOsccaPkc_GeneratePointerTable(uint16_t *pOperandsBase
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_MultipleShiftRotate_Index) void mcuxClOsccaPkc_MultipleShiftRotate_Index(uint32_t iModuluss
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_LeadingZeros) uint32_t mcuxClOsccaPkc_LeadingZeros(uint8_t *pNum
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeModInv) void mcuxClOsccaPkc_ComputeModInv(uint32_t iRiIiNiT
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_CalcMontInverse) void mcuxClOsccaPkc_CalcMontInverse(uint32_t iIiRiNiT
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+uint32_t iRiXiYiZ
 
+uint32_t fupProgramSize
 
+uint16_t iMs
 
+uint8_t * pBufferBase
 
+uint8_t uint32_t bufferSize
 
+uint8_t uint32_t uint32_t bufferNums
 
+uint32_t iModulus
 
+uint32_t uint32_t leadingZeroBits
 
+uint32_t uint32_t _Bool shiftLeft
 
+uint32_t numLen
 
+uint32_t iT2
 
+uint32_t R2
 
+

Detailed Description

+

APIs of mcuxClOsccaPkc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00491.js b/components/els_pkc/doc/mcxn/html/a00491.js new file mode 100644 index 000000000..2bddb8a6b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00491.js @@ -0,0 +1,32 @@ +var a00491 = +[ + [ "mcuxClOsccaPkc_State_t", "a00818.html#ga83f8544bc01ae0f871addbfe5600e706", null ], + [ "mcuxClOsccaPkc_PtrFUPEntry_t", "a00818.html#gae42a19bfc4e7aaa16fdea5ef1e6bc6c4", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gabd5b473ffa78d054abea238ec8a9d9fe", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga0646235b9bbfcec83360eb5802c06426", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga78c5eea2450cb2351c5d65dad3d84238", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gafad9a8bee8d9259bb38053ace2ff9ca8", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga91ea1418d58d66d4ed04400bc7680ac0", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gaf3336b8b4829aa28b897724242f7f17b", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gabf067124152cc864fe727a7977822cc4", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gae52a6763bb9ba879df92b745c7febc17", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga86def3f8950ebe3553ed175be877044e", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gad82d3f934c597b0dc8a44800a9ad0310", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga3069ecca4548922141318eddb11a4697", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga69d772f883f91d43f43f2162a13e38f1", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gac5f2f559428918f93d8215fa2eb55c8a", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#gad8f90d299d8a7a011f105de82915388d", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00818.html#ga73bfc9d815a08347fb0a78f14b533831", null ], + [ "iRiXiYiZ", "a00818.html#ga1fd59ad49f1211f8749136417e7edf2a", null ], + [ "fupProgramSize", "a00818.html#ga200bf53d30b8c8616a27614242d1cd7e", null ], + [ "iMs", "a00818.html#ga3e7923f50d3e4770adebe37b36d1aa9f", null ], + [ "pBufferBase", "a00818.html#ga719901c51eebba77522676c9a3262d6f", null ], + [ "bufferSize", "a00818.html#ga299ed7375fbbea443d7a275a7e7dd355", null ], + [ "bufferNums", "a00818.html#ga524183a528789bfe86492899f52c7a7f", null ], + [ "iModulus", "a00818.html#ga318684b691571e6ed271ee3fe4687f30", null ], + [ "leadingZeroBits", "a00818.html#ga33e538094808aa5ec50e181c9b2fc48a", null ], + [ "shiftLeft", "a00818.html#ga9a026ac6dbc0ffb86bdb50069cc59171", null ], + [ "numLen", "a00818.html#ga4e4c25b41efa2605867f0458ae031d48", null ], + [ "iT2", "a00818.html#ga45937a49364d4cb58eadc6beb0432f2d", null ], + [ "R2", "a00818.html#ga5d193f7a0912b76f2101cc5388c7b71b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00491_source.html b/components/els_pkc/doc/mcxn/html/a00491_source.html new file mode 100644 index 000000000..5a612bc1b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00491_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOsccaPkc_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2018-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLOSCCAPKC_FUNCTIONS_H_
21 #define MCUXCLOSCCAPKC_FUNCTIONS_H_
22 
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 #include <mcuxClConfig.h> // Exported features flags header
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClOscca_FunctionIdentifiers.h>
29 
40 typedef struct mcuxClOsccaPkc_State_t
41 {
42  uint32_t cfg;
43  uint32_t ctrl;
44 }mcuxClOsccaPkc_State_t;
45 
47 typedef const struct mcuxClOsccaPkc_FUPEntry * mcuxClOsccaPkc_PtrFUPEntry_t;
48 
49 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Reset) /* No semicolon */
50 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Reset(mcuxClOsccaPkc_State_t *state) ;
51 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Init) /* No semicolon */
52 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Init(mcuxClOsccaPkc_State_t *state) ;
53 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_SetWordSize) /* No semicolon */
54 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetWordSize(uint32_t redmul) ;
55 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_GetWordSize) /* No semicolon */
56 MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_GetWordSize(void) ;
57 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_WaitforFinish) /* No semicolon */
58 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_WaitforFinish(void) ;
59 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_SetFupTable) /* No semicolon */
60 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetFupTable(void *pUPTRT) ;
61 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Op) /* No semicolon */
62 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Op(uint32_t mode, uint32_t iRiXiYiZ) ;
63 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_StartFupProgram) /* No semicolon */
64 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_StartFupProgram(mcuxClOsccaPkc_PtrFUPEntry_t fupProgram, uint32_t fupProgramSize);
65 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeNDash) /* No semicolon */
66 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeNDash(uint32_t iNiTiXiX);
67 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeQSquared) /* No semicolon */
68 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeQSquared(uint32_t iQiMiTiX, uint16_t iMs);
69 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_GeneratePointerTable) /* No semicolon */
70 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_GeneratePointerTable(uint16_t *pOperandsBase, uint8_t *pBufferBase, uint32_t bufferSize, uint32_t bufferNums);
71 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_MultipleShiftRotate_Index) /* No semicolon */
72 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_MultipleShiftRotate_Index(uint32_t iModuluss, uint32_t iModulus, uint32_t leadingZeroBits, _Bool shiftLeft);
73 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_LeadingZeros) /* No semicolon */
74 MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_LeadingZeros(uint8_t *pNum, uint32_t numLen);
75 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeModInv) /* No semicolon */
76 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeModInv(uint32_t iRiIiNiT, uint32_t iT2);
77 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_CalcMontInverse) /* No semicolon */
78 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_CalcMontInverse(uint32_t iIiRiNiT, uint32_t R2);
79 
80  /* mcuxClOsccaPkc_Functions */
84 
85 #endif /*MCUXCLOSCCAPKC_FUNCTIONS_H_*/
mcuxClOsccaPkc_State_t
struct mcuxClOsccaPkc_State_t mcuxClOsccaPkc_State_t
Structure of PKC state backup.
+
mcuxClOscca_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClOsccaPkc_PtrFUPEntry_t
const struct mcuxClOsccaPkc_FUPEntry * mcuxClOsccaPkc_PtrFUPEntry_t
type of FUP program address.
Definition: mcuxClOsccaPkc_Functions.h:47
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClOsccaPkc_State_t
Structure of PKC state backup.
Definition: mcuxClOsccaPkc_Functions.h:40
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00494.html b/components/els_pkc/doc/mcxn/html/a00494.html new file mode 100644 index 000000000..ea954864f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00494.html @@ -0,0 +1,179 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxClOsccaPkc_Types.h File Reference
+
+
+ +

Type definitions of mcuxClOsccaPkc component. +More...

+
#include <stdint.h>
+#include <mcuxClConfig.h>
+#include <platform_specific_headers.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClOscca_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + +

+Macros

#define MCUXCLOSCCAPKC_PKCPACKARGS2(hi8, lo8)
 Macros for packing 2 8-bit parameters. More...
 
+#define MCUXCLOSCCAPKC_PKC_RAM_BASEADDR
 
+#define MCUXCLOSCCAPKC_WORD_SIZE
 
+

Detailed Description

+

Type definitions of mcuxClOsccaPkc component.

+

Macro Definition Documentation

+ +

◆ MCUXCLOSCCAPKC_PKCPACKARGS2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLOSCCAPKC_PKCPACKARGS2( hi8,
 lo8 
)
+
+ +

Macros for packing 2 8-bit parameters.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00494.js b/components/els_pkc/doc/mcxn/html/a00494.js new file mode 100644 index 000000000..df6038cb4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00494.js @@ -0,0 +1,6 @@ +var a00494 = +[ + [ "MCUXCLOSCCAPKC_PKCPACKARGS2", "a00494.html#aba1b2e7258d3f4a2080b728cc7f91eaf", null ], + [ "MCUXCLOSCCAPKC_PKC_RAM_BASEADDR", "a00494.html#abf92a6a0dd052e3ae6ca7a9929ebb7a7", null ], + [ "MCUXCLOSCCAPKC_WORD_SIZE", "a00494.html#a33bcea3ff2387d7065f0565f17c9038e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00494_source.html b/components/els_pkc/doc/mcxn/html/a00494_source.html new file mode 100644 index 000000000..fcd21e30e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00494_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
mcuxClOsccaPkc_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2018-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLOSCCAPKC_TYPES_H
21 #define MCUXCLOSCCAPKC_TYPES_H
22 
23 
24 #include <stdint.h>
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <platform_specific_headers.h>
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClOscca_FunctionIdentifiers.h>
29 
30 /**********************************************************/
31 /* Helper macros */
32 /**********************************************************/
34 #define MCUXCLOSCCAPKC_PKCPACKARGS2(hi8, lo8) \
35  ( ((uint16_t) (hi8) << 8u) | ((uint16_t) (lo8)) )
36 
37 
38 /**********************************************************/
39 /* PKC information */
40 /**********************************************************/
41 #define MCUXCLOSCCAPKC_PKC_RAM_BASEADDR ((uint32_t)PKC_RAM_ADDR)
42 #define MCUXCLOSCCAPKC_WORD_SIZE (PKC_WORD_SIZE)
43  /* mcuxClOsccaPkc_Types */
47 
48 #endif /* #MCUXCLOSCCAPKC_TYPES_H */
mcuxClOscca_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00497.html b/components/els_pkc/doc/mcxn/html/a00497.html new file mode 100644 index 000000000..23c897692 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00497.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
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+
+
mcuxClOsccaSm3.h File Reference
+
+
+ +

Top-level include file for the mcuxClOsccaSm3 component. +More...

+
#include <mcuxClOsccaSm3_Algorithms.h>
+#include <mcuxClOsccaSm3_Constants.h>
+#include <mcuxClOsccaSm3_MemoryConsumption.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClOsccaSm3 component.

+

This includes headers for all of the functionality provided by the mcuxClOsccaSm3 component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00497_source.html b/components/els_pkc/doc/mcxn/html/a00497_source.html new file mode 100644 index 000000000..64fefd303 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00497_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3.h Source File + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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mcuxClOsccaSm3.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
43 #ifndef MCUXCLOSCCASM3_H_
44 #define MCUXCLOSCCASM3_H_
45 
46 #include <mcuxClOsccaSm3_Algorithms.h>
47 #include <mcuxClOsccaSm3_Constants.h>
48 #include <mcuxClOsccaSm3_MemoryConsumption.h>
49 
50 #endif /* MCUXCLOSCCASM3_H_ */
mcuxClOsccaSm3_Constants.h
Constants for use with the mcuxClOsccaSm3 component.
+
mcuxClOsccaSm3_MemoryConsumption.h
Defines the memory consumption for the mcuxClOsccaSm3 component.
+
mcuxClOsccaSm3_Algorithms.h
Algorithm/mode definitions for the mcuxClOsccaSm3 component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00500.html b/components/els_pkc/doc/mcxn/html/a00500.html new file mode 100644 index 000000000..e1f7c4fc5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00500.html @@ -0,0 +1,130 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_Algorithms.h File Reference + + + + + + + + + + + + + + + + +
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+
mcuxClOsccaSm3_Algorithms.h File Reference
+
+
+ +

Algorithm/mode definitions for the mcuxClOsccaSm3 component. +More...

+
#include <mcuxClHash_Types.h>
+#include <mcuxCsslAnalysis.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Algorithm/mode definitions for the mcuxClOsccaSm3 component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00500_source.html b/components/els_pkc/doc/mcxn/html/a00500_source.html new file mode 100644 index 000000000..2c1743b76 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00500_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_Algorithms.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+
+
mcuxClOsccaSm3_Algorithms.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLOSCCASM3_ALGORITHMS_H_
19 #define MCUXCLOSCCASM3_ALGORITHMS_H_
20 
21 #include <mcuxClHash_Types.h>
22 #include <mcuxCsslAnalysis.h>
23 
31 MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ")
32 
33 #if defined(MCUXCL_FEATURE_HASH_HW_SM3)
34 
38 extern const mcuxClHash_AlgorithmDescriptor_t mcuxClOsccaSm3_AlgorithmDescriptor_Sm3;
39 
44 static mcuxClHash_Algo_t mcuxClOsccaSm3_Algorithm_Sm3 = &mcuxClOsccaSm3_AlgorithmDescriptor_Sm3;
45 
46 #endif /* MCUXCL_FEATURE_HASH_HW_SM3 */
47 
48 MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
49 
50 
52 #endif /* MCUXCLOSCCASM3_ALGORITHMS_H_ */
mcuxClHash_Algo_t
const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
Hash mode/algorithm type.
Definition: mcuxClHash_Types.h:50
+
mcuxClHash_Types.h
Type definitions for the mcuxClHash component.
+
mcuxClHash_AlgorithmDescriptor_t
struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
Hash mode/algorithm descriptor type.
Definition: mcuxClHash_Types.h:42
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00503.html b/components/els_pkc/doc/mcxn/html/a00503.html new file mode 100644 index 000000000..a28788d5a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00503.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
+Macros
+
+
mcuxClOsccaSm3_Constants.h File Reference
+
+
+ +

Constants for use with the mcuxClOsccaSm3 component. +More...

+ +

Go to the source code of this file.

+ + + + + +

+Macros

#define MCUXCLOSCCASM3_OUTPUT_SIZE_SM3
 SM3 output size: 256 bit (32 bytes) More...
 
+

Detailed Description

+

Constants for use with the mcuxClOsccaSm3 component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00503.js b/components/els_pkc/doc/mcxn/html/a00503.js new file mode 100644 index 000000000..758686269 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00503.js @@ -0,0 +1,4 @@ +var a00503 = +[ + [ "MCUXCLOSCCASM3_OUTPUT_SIZE_SM3", "a00821.html#ga12a91530ea05a544a80b18d4f436d51f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00503_source.html b/components/els_pkc/doc/mcxn/html/a00503_source.html new file mode 100644 index 000000000..42545442e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00503_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
+ +
+
+
mcuxClOsccaSm3_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
17 #ifndef MCUXCLOSCCASM3_CONSTANTS_H_
18 #define MCUXCLOSCCASM3_CONSTANTS_H_
19 
26 #define MCUXCLOSCCASM3_OUTPUT_SIZE_SM3 (32U)
27 
31 #endif /* MCUXCLOSCCASM3_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00506.html b/components/els_pkc/doc/mcxn/html/a00506.html new file mode 100644 index 000000000..794aa0330 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00506.html @@ -0,0 +1,167 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
+
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+Macros
+
+
mcuxClOsccaSm3_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClOsccaSm3 component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_compute on SM3. More...
 
#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_compute. More...
 
#define MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required for mcuxClOsccaSm3_init. More...
 
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_process on SM3. More...
 
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_process. More...
 
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_finish on SM3. More...
 
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_finish. More...
 
#define MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required this component. More...
 
+#define MCUXCLOSCCASM3_CONTEXT_SIZE
 
#define MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS
 Defines the context size for streaming hashing interfaces. More...
 
#define MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE
 Defines the state size required for SM3. More...
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClOsccaSm3 component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00506.js b/components/els_pkc/doc/mcxn/html/a00506.js new file mode 100644 index 000000000..0d1970bcc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00506.js @@ -0,0 +1,14 @@ +var a00506 = +[ + [ "MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#ga69194394354130bb74c3a659c6a6382a", null ], + [ "MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#gaac9381a82113d329dd25ab934c95dfd5", null ], + [ "MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE", "a00822.html#gab8638606efbce3f6c35b1584e2edf157", null ], + [ "MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#ga44f1d4fbc45ff4047678df48c2673868", null ], + [ "MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#ga7fc2a9c206d05b1b56fdb4a50964e8aa", null ], + [ "MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#gac8ba7076a5518d52ce295d48099d4ae3", null ], + [ "MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#ga53ef6d92e75dc64d5cdf0bf5cf9c4231", null ], + [ "MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE", "a00822.html#ga92c12b7d0bcd8ebcaf3ffa9bcac45b6b", null ], + [ "MCUXCLOSCCASM3_CONTEXT_SIZE", "a00823.html#ga1ac92cebbc8b9f549fd7c7eddc563134", null ], + [ "MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS", "a00823.html#ga60a96727f7daf1d9762c0c54544e0ca8", null ], + [ "MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE", "a00823.html#ga55b2857bb7c8aec7fb22e3ebab7ebf77", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00506_source.html b/components/els_pkc/doc/mcxn/html/a00506_source.html new file mode 100644 index 000000000..642c5329d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00506_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+
+
mcuxClOsccaSm3_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_
20 #define MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_
21 
29 /****************************************************************************/
30 /* Definitions of workarea buffer sizes for the mcuxClOsccaSm3 functions. */
31 /****************************************************************************/
32 #define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3 (160u)
33 #define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX (160u)
34 
35 
36 #define MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE (0u)
37 
38 #define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3 (32u)
39 #define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX (32u)
40 
41 #define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3 (64u)
42 #define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX (64u)
43 
44 #define MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE (160u)
45 
46 
55 /****************************************************************************/
56 /* Definitions of context sizes for the mcuxClOsccaSm3 multi-part functions. */
57 /****************************************************************************/
58 
59 #define MCUXCLOSCCASM3_CONTEXT_SIZE (120u)
60 #define MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS (120u / sizeof(uint32_t))
61 
62 /********************************************************************************************/
63 /* Definitions of state buffer sizes for mcuxClHash_export_state and mcuxClHash_import_state */
64 /********************************************************************************************/
65 
66 #define MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE (40u)
67 
68  /* mcuxClOsccaSm3_MemoryConsumption */
71 
72 #endif /* MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00509.html b/components/els_pkc/doc/mcxn/html/a00509.html new file mode 100644 index 000000000..7677e6b97 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00509.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClPadding.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ + +
+ +
+ +
+
+
mcuxClPadding.h File Reference
+
+
+ +

Top-level include file for the padding component. +More...

+
#include <mcuxClPadding_Types.h>
+#include <mcuxClPadding_Constants.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the padding component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00509_source.html b/components/els_pkc/doc/mcxn/html/a00509_source.html new file mode 100644 index 000000000..209b8b201 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00509_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClPadding.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClPadding.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLPADDING_H
20 #define MCUXCLPADDING_H
21 
22 #include <mcuxClPadding_Types.h>
23 #include <mcuxClPadding_Constants.h>
24 
25 #include <mcuxCsslFlowProtection.h>
26 #include <mcuxClCore_FunctionIdentifiers.h>
27 
28 #endif /* MCUXCLPADDING_H */
29 
mcuxClPadding_Types.h
Type definitions for the mcuxClPadding component.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClPadding_Constants.h
Constants definitions for the mcuxClPadding component.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00512.html b/components/els_pkc/doc/mcxn/html/a00512.html new file mode 100644 index 000000000..ef6f55fb1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00512.html @@ -0,0 +1,147 @@ + + + + + + + +MCUX CLNS: mcuxClPadding_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
+ +
+
+Macros
+
+
mcuxClPadding_Constants.h File Reference
+
+
+ +

Constants definitions for the mcuxClPadding component. +More...

+
#include <stdint.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLPADDING_STATUS_OK
 Return codes. More...
 
#define MCUXCLPADDING_STATUS_NOT_OK
 Incorrect padding. More...
 
#define MCUXCLPADDING_STATUS_ERROR
 Error occurred during Padding operation. More...
 
#define MCUXCLPADDING_STATUS_FAULT_ATTACK
 Fault attack (unexpected behaviour) detected. More...
 
+

Detailed Description

+

Constants definitions for the mcuxClPadding component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00512.js b/components/els_pkc/doc/mcxn/html/a00512.js new file mode 100644 index 000000000..c7f200887 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00512.js @@ -0,0 +1,7 @@ +var a00512 = +[ + [ "MCUXCLPADDING_STATUS_OK", "a00824.html#gad64734c94edeab85fc1d8e05c4134f52", null ], + [ "MCUXCLPADDING_STATUS_NOT_OK", "a00824.html#ga6393900f48c3b32dd379a6ea30bc730a", null ], + [ "MCUXCLPADDING_STATUS_ERROR", "a00824.html#ga27d0fc33860c93a2241e1d6b37a92d94", null ], + [ "MCUXCLPADDING_STATUS_FAULT_ATTACK", "a00824.html#ga4dff5913bd142d42c0a8825ce553bc3c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00512_source.html b/components/els_pkc/doc/mcxn/html/a00512_source.html new file mode 100644 index 000000000..280115749 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00512_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClPadding_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
+
+
mcuxClPadding_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
18 #ifndef MCUXCLPADDING_CONSTANTS_H_
19 #define MCUXCLPADDING_CONSTANTS_H_
20 
21 #include <stdint.h>
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
34 /**********************************************
35  * CONSTANTS
36  **********************************************/
37 
41 #define MCUXCLPADDING_STATUS_OK ((mcuxClPadding_Status_t) 0x0FF42E03u)
42 #define MCUXCLPADDING_STATUS_NOT_OK ((mcuxClPadding_Status_t) 0x0FF453FCu)
43 #define MCUXCLPADDING_STATUS_ERROR ((mcuxClPadding_Status_t) 0x0FF45330u)
44 #define MCUXCLPADDING_STATUS_FAULT_ATTACK ((mcuxClPadding_Status_t) 0x0FF4F0F0u)
45 
46 
48 #ifdef __cplusplus
49 } /* extern "C" */
50 #endif
51 
52 #endif /* MCUXCLPADDING_CONSTANTS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00515.html b/components/els_pkc/doc/mcxn/html/a00515.html new file mode 100644 index 000000000..24993536d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00515.html @@ -0,0 +1,139 @@ + + + + + + + +MCUX CLNS: mcuxClPadding_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClPadding_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClPadding component. +More...

+
#include <stdint.h>
+#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + +

+Typedefs

typedef uint32_t mcuxClPadding_Status_t
 Padding status code. More...
 
+

Detailed Description

+

Type definitions for the mcuxClPadding component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00515.js b/components/els_pkc/doc/mcxn/html/a00515.js new file mode 100644 index 000000000..8a3e006af --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00515.js @@ -0,0 +1,4 @@ +var a00515 = +[ + [ "mcuxClPadding_Status_t", "a00825.html#ga965eb15986e53917365f3f3b769e0968", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00515_source.html b/components/els_pkc/doc/mcxn/html/a00515_source.html new file mode 100644 index 000000000..6cf9b715e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00515_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxClPadding_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClPadding_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLPADDING_TYPES_H_
21 #define MCUXCLPADDING_TYPES_H_
22 
23 #include <stdint.h>
24 #include <mcuxClConfig.h> // Exported features flags header
25 
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
45 typedef uint32_t mcuxClPadding_Status_t;
46 
49 #ifdef __cplusplus
50 } /* extern "C" */
51 #endif
52 
53 #endif /* MCUXCLPADDING_TYPES_H_ */
mcuxClPadding_Status_t
uint32_t mcuxClPadding_Status_t
Padding status code.
Definition: mcuxClPadding_Types.h:45
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00518.html b/components/els_pkc/doc/mcxn/html/a00518.html new file mode 100644 index 000000000..8e4d0e1e2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00518.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClPkc.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
mcuxClPkc.h File Reference
+
+
+ +

Top level header of mcuxClPkc component (PKC hardware driver) +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClPkc_Types.h>
+#include <mcuxClPkc_Functions.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClPkc component (PKC hardware driver)

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00518_source.html b/components/els_pkc/doc/mcxn/html/a00518_source.html new file mode 100644 index 000000000..6426901da --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00518_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClPkc.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClPkc.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
23 #ifndef MCUXCLPKC_H_
24 #define MCUXCLPKC_H_
25 
26 #include <mcuxClCore_Platform.h>
27 #include <mcuxClPkc_Types.h>
28 #include <mcuxClPkc_Functions.h>
29 
30 
31 #endif /* MCUXCLPKC_H_ */
mcuxClPkc_Types.h
Type definitions of mcuxClPkc component.
+
mcuxClPkc_Functions.h
APIs of mcuxClPkc component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00521.html b/components/els_pkc/doc/mcxn/html/a00521.html new file mode 100644 index 000000000..56c955afc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00521.html @@ -0,0 +1,214 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs | +Functions
+
+
mcuxClPkc_Functions.h File Reference
+
+
+ +

APIs of mcuxClPkc component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClSession.h>
+#include <mcuxClPkc_Types.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClPkc_State_t
 Structure of PKC state backup. More...
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLPKC_FP_INITIALIZE(pState)
 Helper macro to call mcuxClPkc_Initialize with flow protection. More...
 
#define MCUXCLPKC_FP_DEINITIALIZE(pState)
 Helper macro to call mcuxClPkc_Deinitialize with flow protection. More...
 
#define MCUXCLPKC_FP_GENERATEUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer)
 Helper macro to call mcuxClPkc_GenerateUPTRT with flow protection. More...
 
#define MCUXCLPKC_FP_CALCFUP(pUPTR, ulen)
 Helper macro to call mcuxClPkc_CalcFup with flow protection. More...
 
#define MCUXCLPKC_FP_CALCFUP_OFFSET(pUPTR, skipLen, ulen)
 Helper macro to call mcuxClPkc_CalcFup (skipping first skipLen calculation(s)) with flow protection. More...
 
#define MCUXCLPKC_FP_WAITFORFINISH()
 Helper macro to call mcuxClPkc_WaitForFinish with flow protection. More...
 
#define MCUXCLPKC_FP_WAITFORREADY()
 Helper macro to call mcuxClPkc_WaitForReady with flow protection. More...
 
+ + + + +

+Typedefs

typedef const struct mcuxClPkc_FUPEntry * mcuxClPkc_PtrFUPEntry_t
 type of FUP program address. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

 MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcInitializeEngine_t, typedef void(*mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState))
 Function type for PKC initialization engine. More...
 
 MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcDeInitializeEngine_t, typedef void(*mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState))
 Function type for PKC deinitialization engine. More...
 
void mcuxClPkc_Initialize (mcuxClPkc_State_t *pState)
 initialize PKC hardware More...
 
void mcuxClPkc_Deinitialize (const mcuxClPkc_State_t *pState)
 deinitialize PKC hardware More...
 
void mcuxClPkc_GenerateUPTRT (uint16_t *pUPTRT, const uint8_t *pBaseBuffer, uint16_t bufferLength, uint8_t noOfBuffer)
 Initialize UPTR table. More...
 
mcuxClPkc_Status_t mcuxClPkc_RandomizeUPTRT (mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint8_t noOfBuffer)
 Randomize UPTR table. More...
 
mcuxClPkc_Status_t mcuxClPkc_ReRandomizeUPTRT (mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint16_t bufferLength, uint8_t noOfBuffer)
 Randomize UPTR table and operands in PKC workarea. More...
 
void mcuxClPkc_Calc (uint16_t param_mode, uint32_t iR_iX_iY_iZ)
 Start a PKC calculation. More...
 
void mcuxClPkc_CalcConst (uint16_t param_mode, uint32_t iR_iX_iY_C)
 Start a PKC calculation with one constant parameter. More...
 
void mcuxClPkc_CalcFup (mcuxClPkc_PtrFUPEntry_t pUPTR, uint8_t uLength)
 Start a PKC FUP program calculation. More...
 
void mcuxClPkc_WaitForFinish (void)
 Wait until PKC finishes calculations. More...
 
void mcuxClPkc_WaitForReady (void)
 Wait until PKC is ready to accept new calculation. More...
 
+

Detailed Description

+

APIs of mcuxClPkc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00521.js b/components/els_pkc/doc/mcxn/html/a00521.js new file mode 100644 index 000000000..6da363c28 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00521.js @@ -0,0 +1,23 @@ +var a00521 = +[ + [ "MCUXCLPKC_FP_INITIALIZE", "a00963.html#ga3a95e35addbaf26fa41f8e9cf27950f6", null ], + [ "MCUXCLPKC_FP_DEINITIALIZE", "a00963.html#gaf47041e2fee71acba1d37b89f7825e02", null ], + [ "MCUXCLPKC_FP_GENERATEUPTRT", "a00964.html#ga26921e5d9a66bd8247a277794b04b42c", null ], + [ "MCUXCLPKC_FP_CALCFUP", "a00965.html#ga75385d0295607d89d375f6b8706f4299", null ], + [ "MCUXCLPKC_FP_CALCFUP_OFFSET", "a00965.html#gac16f7fd691d8868968cc643feed97846", null ], + [ "MCUXCLPKC_FP_WAITFORFINISH", "a00966.html#gac1f65eb00620f5683ffd7965a084a977", null ], + [ "MCUXCLPKC_FP_WAITFORREADY", "a00966.html#ga1733f3b346a3bd00ffdd8b3f7df0c3fc", null ], + [ "mcuxClPkc_PtrFUPEntry_t", "a00965.html#ga9c5b69d5d2b5e9b7551de9cbe163050f", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00963.html#gaf821ec5ad694746ba28321b2bb802236", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00963.html#ga4ad3a9a17b2090a8d761fcd9c9c86218", null ], + [ "mcuxClPkc_Initialize", "a00963.html#ga338ddc55800355531bd20236fa3710b8", null ], + [ "mcuxClPkc_Deinitialize", "a00963.html#ga0d09260a20ca358d02264f16a74369c1", null ], + [ "mcuxClPkc_GenerateUPTRT", "a00964.html#gae14e20fe9fd56e0ca8125773bc88f822", null ], + [ "mcuxClPkc_RandomizeUPTRT", "a00964.html#gaf961165a01be833d3200563399a2c9aa", null ], + [ "mcuxClPkc_ReRandomizeUPTRT", "a00964.html#ga195c78d51f2084c693257bc52c725c1f", null ], + [ "mcuxClPkc_Calc", "a00965.html#ga1fe435f5e72d9347692a7ac8fa2ba67f", null ], + [ "mcuxClPkc_CalcConst", "a00965.html#ga2d214326104dc2ced79098286852ae03", null ], + [ "mcuxClPkc_CalcFup", "a00965.html#gaec0a3e70eb593b9bd49edf9e7aba298e", null ], + [ "mcuxClPkc_WaitForFinish", "a00966.html#ga7d26efcc91094390f7c55fbd870692cd", null ], + [ "mcuxClPkc_WaitForReady", "a00966.html#ga963b13a65f2ae869947cbbebf2f9a823", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00521_source.html b/components/els_pkc/doc/mcxn/html/a00521_source.html new file mode 100644 index 000000000..b3da31a63 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00521_source.html @@ -0,0 +1,144 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClPkc_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLPKC_FUNCTIONS_H_
21 #define MCUXCLPKC_FUNCTIONS_H_
22 
23 
24 #include <mcuxClCore_Platform.h>
25 #include <mcuxClCore_FunctionIdentifiers.h>
26 #include <mcuxCsslFlowProtection.h>
27 #include <mcuxClSession.h>
28 #include <mcuxClPkc_Types.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
42 /**********************************************************/
43 /* PKC initialization and deinitialization */
44 /**********************************************************/
54 typedef struct
55 {
56  uint16_t ctrl;
57  uint16_t cfg;
58 } mcuxClPkc_State_t;
59 
60 
68 MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcInitializeEngine_t,
69 typedef MCUX_CSSL_FP_PROTECTED_TYPE(void) (* mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState));
70 
78 MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcDeInitializeEngine_t,
79 typedef MCUX_CSSL_FP_PROTECTED_TYPE(void) (* mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState));
80 
89 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Initialize, mcuxClPkc_PkcInitializeEngine_t)
90 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Initialize(
91  mcuxClPkc_State_t *pState
92  );
94 #define MCUXCLPKC_FP_INITIALIZE(pState) \
95  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Initialize(pState))
96 
105 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Deinitialize, mcuxClPkc_PkcDeInitializeEngine_t)
106 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Deinitialize(
107  const mcuxClPkc_State_t *pState
108  );
110 #define MCUXCLPKC_FP_DEINITIALIZE(pState) \
111  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Deinitialize(pState))
112 
113  /* mcuxClPkc_Functions_Init */
117 
118 
119 /**********************************************************/
120 /* UPTR table */
121 /**********************************************************/
153 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_GenerateUPTRT)
154 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_GenerateUPTRT(
155  uint16_t *pUPTRT,
156  const uint8_t *pBaseBuffer,
157  uint16_t bufferLength,
158  uint8_t noOfBuffer
159  );
161 #define MCUXCLPKC_FP_GENERATEUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer) \
162  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_GenerateUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer))
163 
194 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_RandomizeUPTRT)
195 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_RandomizeUPTRT(
196  mcuxClSession_Handle_t pSession,
197  uint16_t *pUPTRT,
198  uint8_t noOfBuffer
199  );
200 
234 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_ReRandomizeUPTRT)
235 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_ReRandomizeUPTRT(
236  mcuxClSession_Handle_t pSession,
237  uint16_t *pUPTRT,
238  uint16_t bufferLength,
239  uint8_t noOfBuffer
240  );
241  /* mcuxClPkc_Functions_UPTRT */
245 
246 
247 /**********************************************************/
248 /* PKC calculation */
249 /**********************************************************/
268 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Calc)
269 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Calc(
270  uint16_t param_mode,
271  uint32_t iR_iX_iY_iZ
272  );
273 
288 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_CalcConst)
289 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcConst(
290  uint16_t param_mode,
291  uint32_t iR_iX_iY_C
292  );
293 
295 typedef const struct mcuxClPkc_FUPEntry * mcuxClPkc_PtrFUPEntry_t;
296 
307 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_CalcFup)
308 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcFup(
309  mcuxClPkc_PtrFUPEntry_t pUPTR,
310  uint8_t uLength
311  );
313 #define MCUXCLPKC_FP_CALCFUP(pUPTR, ulen) \
314  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcFup(pUPTR, ulen))
315 
317 #define MCUXCLPKC_FP_CALCFUP_OFFSET(pUPTR, skipLen, ulen) \
318  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcFup(&((mcuxClPkc_PtrFUPEntry_t) (pUPTR))[(skipLen)], ulen))
319  /* mcuxClPkc_Functions_Calculation */
323 
324 
325 /**********************************************************/
326 /* PKC wait functions */
327 /**********************************************************/
340 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_WaitForFinish)
341 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForFinish(void);
343 #define MCUXCLPKC_FP_WAITFORFINISH() \
344  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_WaitForFinish())
345 
351 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_WaitForReady)
352 MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForReady(void);
354 #define MCUXCLPKC_FP_WAITFORREADY() \
355  MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_WaitForReady())
356 
357  /* mcuxClPkc_Functions_Wait */
361  /* mcuxClPkc_Functions */
365 
366 #ifdef __cplusplus
367 } /* extern "C" */
368 #endif
369 
370 #endif /* MCUXCLPKC_FUNCTIONS_H_ */
mcuxClPkc_Deinitialize
void mcuxClPkc_Deinitialize(const mcuxClPkc_State_t *pState)
deinitialize PKC hardware
+
mcuxClPkc_Types.h
Type definitions of mcuxClPkc component.
+
MCUX_CSSL_FP_FUNCTION_POINTER
MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcInitializeEngine_t, typedef void(*mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState))
Function type for PKC initialization engine.
+
mcuxClPkc_Status_t
uint32_t mcuxClPkc_Status_t
Type for error codes used by PKC component functions.
Definition: mcuxClPkc_Types.h:55
+
mcuxClPkc_RandomizeUPTRT
mcuxClPkc_Status_t mcuxClPkc_RandomizeUPTRT(mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint8_t noOfBuffer)
Randomize UPTR table.
+
mcuxClPkc_State_t::ctrl
uint16_t ctrl
backup of PKC CTRL bits
Definition: mcuxClPkc_Functions.h:56
+
mcuxClPkc_Calc
void mcuxClPkc_Calc(uint16_t param_mode, uint32_t iR_iX_iY_iZ)
Start a PKC calculation.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClPkc_Initialize
void mcuxClPkc_Initialize(mcuxClPkc_State_t *pState)
initialize PKC hardware
+
mcuxClPkc_CalcConst
void mcuxClPkc_CalcConst(uint16_t param_mode, uint32_t iR_iX_iY_C)
Start a PKC calculation with one constant parameter.
+
mcuxClPkc_State_t
Structure of PKC state backup.
Definition: mcuxClPkc_Functions.h:54
+
mcuxClPkc_PtrFUPEntry_t
const struct mcuxClPkc_FUPEntry * mcuxClPkc_PtrFUPEntry_t
type of FUP program address.
Definition: mcuxClPkc_Functions.h:295
+
mcuxClPkc_State_t::cfg
uint16_t cfg
backup of PKC CFG bits
Definition: mcuxClPkc_Functions.h:57
+
mcuxClPkc_ReRandomizeUPTRT
mcuxClPkc_Status_t mcuxClPkc_ReRandomizeUPTRT(mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint16_t bufferLength, uint8_t noOfBuffer)
Randomize UPTR table and operands in PKC workarea.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClPkc_WaitForReady
void mcuxClPkc_WaitForReady(void)
Wait until PKC is ready to accept new calculation.
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClPkc_WaitForFinish
void mcuxClPkc_WaitForFinish(void)
Wait until PKC finishes calculations.
+
mcuxClPkc_GenerateUPTRT
void mcuxClPkc_GenerateUPTRT(uint16_t *pUPTRT, const uint8_t *pBaseBuffer, uint16_t bufferLength, uint8_t noOfBuffer)
Initialize UPTR table.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClPkc_CalcFup
void mcuxClPkc_CalcFup(mcuxClPkc_PtrFUPEntry_t pUPTR, uint8_t uLength)
Start a PKC FUP program calculation.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00524.html b/components/els_pkc/doc/mcxn/html/a00524.html new file mode 100644 index 000000000..4a22aff16 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00524.html @@ -0,0 +1,169 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Typedefs
+
+
mcuxClPkc_Types.h File Reference
+
+
+ +

Type definitions of mcuxClPkc component. +More...

+
#include <platform_specific_headers.h>
+#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslFlowProtection.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLPKC_STATUS_OK
 PKC operation successful. More...
 
#define MCUXCLPKC_STATUS_NOK
 PKC operation not successful. More...
 
#define MCUXCLPKC_ROUNDUP_SIZE(byteLen)
 Round-up a length to a multiple of PKC wordsize. More...
 
#define MCUXCLPKC_PACKARGS4(byte3_MSByte, byte2, byte1, byte0_LSByte)
 Macros for packing 4 8-bit parameters. More...
 
#define MCUXCLPKC_PACKARGS2(hi8, lo8)
 Macros for packing 2 8-bit parameters. More...
 
#define MCUXCLPKC_RAM_START_ADDRESS
 PKC workarea address. More...
 
#define MCUXCLPKC_WORDSIZE
 PKC wordsize in byte. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClPkc_Status_t
 Type for error codes used by PKC component functions. More...
 
typedef mcuxClPkc_Status_t mcuxClPkc_Status_Protected_t
 Deprecated type for error codes used by code-flow protected PKC component functions. More...
 
+

Detailed Description

+

Type definitions of mcuxClPkc component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00524.js b/components/els_pkc/doc/mcxn/html/a00524.js new file mode 100644 index 000000000..2627f6983 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00524.js @@ -0,0 +1,12 @@ +var a00524 = +[ + [ "MCUXCLPKC_STATUS_OK", "a00967.html#ga12385077399c226411e29ef427246669", null ], + [ "MCUXCLPKC_STATUS_NOK", "a00967.html#gab1f0a5295736463652b7a8c1ba887991", null ], + [ "MCUXCLPKC_ROUNDUP_SIZE", "a00968.html#ga5d67b3705403f3a0cab0d71316df929b", null ], + [ "MCUXCLPKC_PACKARGS4", "a00968.html#gac13331e9f328b7a4446314837be58138", null ], + [ "MCUXCLPKC_PACKARGS2", "a00968.html#ga5040d930ab47ec9246a95cf32b8f5fed", null ], + [ "MCUXCLPKC_RAM_START_ADDRESS", "a00968.html#ga0de371abb530f10283d7f8ba4bf8dd76", null ], + [ "MCUXCLPKC_WORDSIZE", "a00968.html#ga275596959934aecdbc4dc35cefb1c6ba", null ], + [ "mcuxClPkc_Status_t", "a00967.html#ga9382ab1c4689794b50a3b75ad39a350c", null ], + [ "mcuxClPkc_Status_Protected_t", "a00967.html#gaaee98013327cc5777f68c6b9fdb1ef6d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00524_source.html b/components/els_pkc/doc/mcxn/html/a00524_source.html new file mode 100644 index 000000000..4a3d9ee52 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00524_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
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+
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+ +
+ +
+
+
mcuxClPkc_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLPKC_TYPES_H
21 #define MCUXCLPKC_TYPES_H
22 
23 
24 #include <platform_specific_headers.h>
25 #include <mcuxClCore_Platform.h>
26 #include <mcuxClCore_FunctionIdentifiers.h>
27 #include <mcuxCsslFlowProtection.h>
28 
29 
38 /**********************************************
39  * CONSTANTS
40  **********************************************/
41 /* None */
42 
43 
44 /**********************************************
45  * TYPEDEFS
46  **********************************************/
55 typedef uint32_t mcuxClPkc_Status_t;
56 
60 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_Status_Protected_t;
61 
62 #define MCUXCLPKC_STATUS_OK ((mcuxClPkc_Status_t) 0x0AAA2E03u)
63 #define MCUXCLPKC_STATUS_NOK ((mcuxClPkc_Status_t) 0x0AAA53FCu)
64  /* MCUXCLPKC_STATUS_ */
67 
68 
69 /**********************************************************/
70 /* Helper macros */
71 /**********************************************************/
78 #define MCUXCLPKC_ROUNDUP_SIZE(byteLen) \
79  (((uint32_t) (byteLen) + (uint32_t)MCUXCLPKC_WORDSIZE - (uint32_t)1u) & (~((uint32_t) MCUXCLPKC_WORDSIZE - (uint32_t)1u)))
80 
82 #define MCUXCLPKC_PACKARGS4(byte3_MSByte, byte2, byte1, byte0_LSByte) \
83  ( ((uint32_t) (byte3_MSByte) << 24) | ((uint32_t) (byte2) << 16) \
84  | ((uint32_t) (byte1) << 8) | ((uint32_t) (byte0_LSByte)) )
85 
87 #define MCUXCLPKC_PACKARGS2(hi8, lo8) \
88  ( ((uint16_t) (hi8) << 8) | ((uint16_t) (lo8)) )
89 
90 
91 /**********************************************************/
92 /* PKC information */
93 /**********************************************************/
94 #define MCUXCLPKC_RAM_START_ADDRESS PKC_RAM_ADDR
95 #define MCUXCLPKC_WORDSIZE 8u
96 
97  /* MCUXCLPKC_MISC_ */
101  /* mcuxClEcc_Macros */
105 
106 #endif /* #MCUXCLPKC_TYPES_H */
mcuxClPkc_Status_t
uint32_t mcuxClPkc_Status_t
Type for error codes used by PKC component functions.
Definition: mcuxClPkc_Types.h:55
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClPkc_Status_Protected_t
mcuxClPkc_Status_t mcuxClPkc_Status_Protected_t
Deprecated type for error codes used by code-flow protected PKC component functions.
Definition: mcuxClPkc_Types.h:60
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00527.html b/components/els_pkc/doc/mcxn/html/a00527.html new file mode 100644 index 000000000..3e884d208 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00527.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClRandom.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
+
mcuxClRandom.h File Reference
+
+
+ +

Top level header of mcuxClRandom component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClRandom_Types.h>
+#include <mcuxClRandom_Functions.h>
+#include <mcuxClRandom_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00527_source.html b/components/els_pkc/doc/mcxn/html/a00527_source.html new file mode 100644 index 000000000..43222acc0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00527_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClRandom.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
+ + + +
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+ +
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+
+
mcuxClRandom.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUXCLRANDOM_H_
23 #define MCUXCLRANDOM_H_
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 
27 #include <mcuxClRandom_Types.h>
28 #include <mcuxClRandom_Functions.h>
29 #include <mcuxClRandom_Constants.h>
30 
31 #endif /* MCUXCLRANDOM_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClRandom_Constants.h
Constant definitions of mcuxClRandom component.
+
mcuxClRandom_Functions.h
Top level APIs of mcuxClRandom component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00530.html b/components/els_pkc/doc/mcxn/html/a00530.html new file mode 100644 index 000000000..c0a21645c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00530.html @@ -0,0 +1,150 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
+
+
mcuxClRandom_Constants.h File Reference
+
+
+ +

Constant definitions of mcuxClRandom component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRANDOM_STATUS_ERROR
 Random function returned error. More...
 
#define MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH
 Security strength of given RNG lower than requested. More...
 
#define MCUXCLRANDOM_STATUS_INVALID_PARAM
 Random function parameter invalid. More...
 
#define MCUXCLRANDOM_STATUS_OK
 Random function returned successfully. More...
 
#define MCUXCLRANDOM_STATUS_FAULT_ATTACK
 Random function returned fault attack. More...
 
+

Detailed Description

+

Constant definitions of mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00530.js b/components/els_pkc/doc/mcxn/html/a00530.js new file mode 100644 index 000000000..63998bce2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00530.js @@ -0,0 +1,8 @@ +var a00530 = +[ + [ "MCUXCLRANDOM_STATUS_ERROR", "a00969.html#ga1b55e6564466854e9bd070d5bf20c46c", null ], + [ "MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH", "a00969.html#ga1318606347b0aa4a477b68572a862552", null ], + [ "MCUXCLRANDOM_STATUS_INVALID_PARAM", "a00969.html#ga9b0f869c046d3055dcc6f994c9aa0191", null ], + [ "MCUXCLRANDOM_STATUS_OK", "a00969.html#ga951990ff5179cd6fce7310de16002b20", null ], + [ "MCUXCLRANDOM_STATUS_FAULT_ATTACK", "a00969.html#ga6d4a0c17c9ec70556936f749305dace8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00530_source.html b/components/els_pkc/doc/mcxn/html/a00530_source.html new file mode 100644 index 000000000..293acad46 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00530_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Constants.h Source File + + + + + + + + + + + + + + + + +
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClRandom_Constants.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLRANDOM_CONSTANTS_H_
21 #define MCUXCLRANDOM_CONSTANTS_H_
22 
23 
24 #include <mcuxClConfig.h> // Exported features flags header
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 /**********************************************************/
31 /* Constants of mcuxClRandom */
32 /**********************************************************/
43 #define MCUXCLRANDOM_STATUS_ERROR 0x0BBB5330u
44 #define MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH 0x0BBB5334u
45 #define MCUXCLRANDOM_STATUS_INVALID_PARAM 0x0BBB53F8u
46 #define MCUXCLRANDOM_STATUS_OK 0x0BBB2E03u
47 #define MCUXCLRANDOM_STATUS_FAULT_ATTACK 0x0BBBF0F0u
48  /* mcuxClRandom_Constants */
53 
54 #ifdef __cplusplus
55 } /* extern "C" */
56 #endif
57 
58 #endif /* MCUXCLRANDOM_TYPES_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00533.html b/components/els_pkc/doc/mcxn/html/a00533.html new file mode 100644 index 000000000..2fc8c9fbd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00533.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+
+ +
+ +
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+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandom_Functions.h File Reference
+
+
+ +

Top level APIs of mcuxClRandom component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+#include <mcuxClRandom_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClRandom_Status_t mcuxClRandom_init (mcuxClSession_Handle_t pSession, mcuxClRandom_Context_t pContext, mcuxClRandom_Mode_t mode)
 Random data generator initialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_reseed (mcuxClSession_Handle_t pSession)
 Random data generator reseed function. More...
 
mcuxClRandom_Status_t mcuxClRandom_generate (mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
 Random data generation function. More...
 
mcuxClRandom_Status_t mcuxClRandom_uninit (mcuxClSession_Handle_t pSession)
 Random data generator uninitialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_selftest (mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode)
 Random data generator self-test function. More...
 
mcuxClRandom_Status_t mcuxClRandom_checkSecurityStrength (mcuxClSession_Handle_t pSession, uint32_t securityStrength)
 Random data generator security strength check. More...
 
mcuxClRandom_Status_t mcuxClRandom_ncInit (mcuxClSession_Handle_t pSession)
 Non-cryptographic PRNG initialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_ncGenerate (mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
 Non-cryptographic PRNG data generation function. More...
 
+

Detailed Description

+

Top level APIs of mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00533.js b/components/els_pkc/doc/mcxn/html/a00533.js new file mode 100644 index 000000000..d7b235c07 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00533.js @@ -0,0 +1,11 @@ +var a00533 = +[ + [ "mcuxClRandom_init", "a00831.html#ga989cf9033b30c383d1548037f2ec8bc9", null ], + [ "mcuxClRandom_reseed", "a00831.html#ga89fe90a4ca175d03b4a821cf2fa2004f", null ], + [ "mcuxClRandom_generate", "a00831.html#gadb7d7b6ff820450be3533014cb47f279", null ], + [ "mcuxClRandom_uninit", "a00831.html#ga92889d1e06ba33656278bd2a4110be99", null ], + [ "mcuxClRandom_selftest", "a00831.html#ga4c882c0d6b1e1bba418934c44acc873c", null ], + [ "mcuxClRandom_checkSecurityStrength", "a00831.html#ga6e48c6007ea1d6cfa2ec329152072fc0", null ], + [ "mcuxClRandom_ncInit", "a00831.html#ga4522b9cfa28cb224b653003d481d7100", null ], + [ "mcuxClRandom_ncGenerate", "a00831.html#ga942c035e4c1971f3e4da8cf252b6cdf6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00533_source.html b/components/els_pkc/doc/mcxn/html/a00533_source.html new file mode 100644 index 000000000..3ac562fbf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00533_source.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClRandom_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRANDOM_FUNCTIONS_H_
20 #define MCUXCLRANDOM_FUNCTIONS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #include <mcuxClSession.h>
25 #include <mcuxClRandom_Types.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 /**********************************************************/
32 /* Public APIs of mcuxClRandom */
33 /**********************************************************/
54 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_init)
55 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_init(
56  mcuxClSession_Handle_t pSession,
57  mcuxClRandom_Context_t pContext,
58  mcuxClRandom_Mode_t mode
59 ); /* init */
60 
72 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_reseed)
73 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_reseed(
74  mcuxClSession_Handle_t pSession
75 ); /* reseed */
76 
91 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_generate)
92 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_generate(
93  mcuxClSession_Handle_t pSession,
94  uint8_t * pOut,
95  uint32_t outLength
96 ); /* generate */
97 
108 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_uninit)
109 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_uninit(
110  mcuxClSession_Handle_t pSession
111 ); /* uninit */
112 
124 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_selftest)
125 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_selftest(
126  mcuxClSession_Handle_t pSession,
127  mcuxClRandom_Mode_t mode
128 ); /* health test */
129 
141 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_checkSecurityStrength)
142 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_checkSecurityStrength(
143  mcuxClSession_Handle_t pSession,
144  uint32_t securityStrength
145 ); /* security strength check */
146 
157 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_ncInit)
158 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncInit(
159  mcuxClSession_Handle_t pSession
160 ); /* LE init */
161 
175 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_ncGenerate)
176 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncGenerate(
177  mcuxClSession_Handle_t pSession,
178  uint8_t * pOut,
179  uint32_t outLength
180 ); /* LE generate */
181 
182 #ifdef __cplusplus
183 } /* extern "C" */
184 #endif
185  /* mcuxClRandom_Functions */
189 
190 #endif /* MCUXCLRANDOM_FUNCTIONS_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClRandom_Context_t
mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
Random context type.
Definition: mcuxClRandom_Types.h:70
+
mcuxClRandom_checkSecurityStrength
mcuxClRandom_Status_t mcuxClRandom_checkSecurityStrength(mcuxClSession_Handle_t pSession, uint32_t securityStrength)
Random data generator security strength check.
+
mcuxClRandom_ncGenerate
mcuxClRandom_Status_t mcuxClRandom_ncGenerate(mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
Non-cryptographic PRNG data generation function.
+
mcuxClRandom_init
mcuxClRandom_Status_t mcuxClRandom_init(mcuxClSession_Handle_t pSession, mcuxClRandom_Context_t pContext, mcuxClRandom_Mode_t mode)
Random data generator initialization function.
+
mcuxClRandom_ncInit
mcuxClRandom_Status_t mcuxClRandom_ncInit(mcuxClSession_Handle_t pSession)
Non-cryptographic PRNG initialization function.
+
mcuxClRandom_selftest
mcuxClRandom_Status_t mcuxClRandom_selftest(mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode)
Random data generator self-test function.
+
mcuxClRandom_Status_t
uint32_t mcuxClRandom_Status_t
Type for status codes of mcuxClRandom component functions.
Definition: mcuxClRandom_Types.h:47
+
mcuxClRandom_reseed
mcuxClRandom_Status_t mcuxClRandom_reseed(mcuxClSession_Handle_t pSession)
Random data generator reseed function.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClRandom_uninit
mcuxClRandom_Status_t mcuxClRandom_uninit(mcuxClSession_Handle_t pSession)
Random data generator uninitialization function.
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClRandom_Mode_t
const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
Random data generation mode/algorithm type.
Definition: mcuxClRandom_Types.h:93
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClRandom_generate
mcuxClRandom_Status_t mcuxClRandom_generate(mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
Random data generation function.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00536.html b/components/els_pkc/doc/mcxn/html/a00536.html new file mode 100644 index 000000000..81bea3611 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00536.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Types.h File Reference + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Data Structures | +Typedefs
+
+
mcuxClRandom_Types.h File Reference
+
+
+ +

Type definitions of mcuxClRandom component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClCore_Platform.h>
+
+

Go to the source code of this file.

+ + + + + +

+Data Structures

struct  mcuxClRandom_Config
 Random config structure. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClRandom_Status_t
 Type for status codes of mcuxClRandom component functions. More...
 
typedef struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t
 Random context type. More...
 
typedef mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
 Random context type. More...
 
typedef struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
 Random data generation mode/algorithm descriptor type. More...
 
typedef const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
 Random data generation mode/algorithm type. More...
 
typedef struct mcuxClRandom_Config mcuxClRandom_Config_t
 Random config type. More...
 
+

Detailed Description

+

Type definitions of mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00536.js b/components/els_pkc/doc/mcxn/html/a00536.js new file mode 100644 index 000000000..e94fa6b9f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00536.js @@ -0,0 +1,9 @@ +var a00536 = +[ + [ "mcuxClRandom_Status_t", "a00832.html#ga768ea9930242003d2a68991684a1e948", null ], + [ "mcuxClRandom_ContextDescriptor_t", "a00832.html#gab409cd7b1e5a4da822bf9ae43d00c79c", null ], + [ "mcuxClRandom_Context_t", "a00832.html#gac2ce3a52788240794afde522cfad65c5", null ], + [ "mcuxClRandom_ModeDescriptor_t", "a00832.html#gadcfae984a95f3e98617ca5fb9767f5cd", null ], + [ "mcuxClRandom_Mode_t", "a00832.html#ga2998181a66cbdc063aa08d76e5fdef9d", null ], + [ "mcuxClRandom_Config_t", "a00832.html#gaf1284eaa96ef47c06697f95e74ffc3ee", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00536_source.html b/components/els_pkc/doc/mcxn/html/a00536_source.html new file mode 100644 index 000000000..5e8fc9856 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00536_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+
mcuxClRandom_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCLRANDOM_TYPES_H_
21 #define MCUXCLRANDOM_TYPES_H_
22 
23 #include <mcuxClConfig.h> // Exported features flags header
24 
25 #include <mcuxClCore_Platform.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 /**********************************************************/
32 /* Types of mcuxClRandom */
33 /**********************************************************/
47 typedef uint32_t mcuxClRandom_Status_t;
48 
55 struct mcuxClRandom_Context;
56 
63 typedef struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t;
64 
70 typedef mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t;
71 
78 struct mcuxClRandom_ModeDescriptor;
79 
86 typedef struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t;
87 
93 typedef const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t;
94 
100 struct mcuxClRandom_Config {
101  mcuxClRandom_Mode_t mode;
102  mcuxClRandom_Context_t ctx;
103 };
104 
110 typedef struct mcuxClRandom_Config mcuxClRandom_Config_t;
111  /* mcuxClRandom_Types */
115 
116 #ifdef __cplusplus
117 } /* extern "C" */
118 #endif
119 
120 #endif /* MCUXCLRANDOM_TYPES_H_ */
mcuxClRandom_Context_t
mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
Random context type.
Definition: mcuxClRandom_Types.h:70
+
mcuxClRandom_ModeDescriptor_t
struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
Random data generation mode/algorithm descriptor type.
Definition: mcuxClRandom_Types.h:86
+
mcuxClRandom_ContextDescriptor_t
struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t
Random context type.
Definition: mcuxClRandom_Types.h:63
+
mcuxClRandom_Status_t
uint32_t mcuxClRandom_Status_t
Type for status codes of mcuxClRandom component functions.
Definition: mcuxClRandom_Types.h:47
+
mcuxClRandom_Config::ctx
mcuxClRandom_Context_t ctx
Context for the Rng.
Definition: mcuxClRandom_Types.h:102
+
mcuxClRandom_Mode_t
const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
Random data generation mode/algorithm type.
Definition: mcuxClRandom_Types.h:93
+
mcuxClRandom_Config::mode
mcuxClRandom_Mode_t mode
Random data generation mode/algorithm.
Definition: mcuxClRandom_Types.h:101
+
mcuxClRandom_Config
Random config structure.
Definition: mcuxClRandom_Types.h:100
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00539.html b/components/els_pkc/doc/mcxn/html/a00539.html new file mode 100644 index 000000000..69f53af9d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00539.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes.h File Reference
+
+
+ +

Top level header of mcuxClRandomModes component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClRandomModes_Functions_PatchMode.h>
+#include <mcuxClRandomModes_MemoryConsumption.h>
+#include <mcuxClRandomModes_Constants.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top level header of mcuxClRandomModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00539_source.html b/components/els_pkc/doc/mcxn/html/a00539_source.html new file mode 100644 index 000000000..7d838af48 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00539_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUXCLRANDOMMODES_H_
23 #define MCUXCLRANDOMMODES_H_
24 
25 #include <mcuxClConfig.h> // Exported features flags header
26 #ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE
27 #include <mcuxClRandomModes_Functions_TestMode.h>
28 #endif /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */
29 #include <mcuxClRandomModes_Functions_PatchMode.h>
30 #include <mcuxClRandomModes_MemoryConsumption.h>
31 #include <mcuxClRandomModes_Constants.h>
32 
33 #endif /* MCUXCLRANDOMMODES_H_ */
mcuxClRandomModes_Constants.h
Mode definitions of mcuxClRandomModes component.
+
mcuxClRandomModes_MemoryConsumption.h
Defines the memory consumption for the mcuxClRandom component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00542.html b/components/els_pkc/doc/mcxn/html/a00542.html new file mode 100644 index 000000000..d6bbe7080 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00542.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClRandomModes_Constants.h File Reference
+
+
+ +

Mode definitions of mcuxClRandomModes component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClRandom_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + +

+Variables

const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg
 Mode for a DRBG implemented by the ELS. More...
 
+static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_ELS_Drbg
 
+

Detailed Description

+

Mode definitions of mcuxClRandomModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00542.js b/components/els_pkc/doc/mcxn/html/a00542.js new file mode 100644 index 000000000..08f3bd5fd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00542.js @@ -0,0 +1,5 @@ +var a00542 = +[ + [ "mcuxClRandomModes_mdELS_Drbg", "a00833.html#ga33a2ec75a1ffddc069c679de7c34b8fc", null ], + [ "mcuxClRandomModes_Mode_ELS_Drbg", "a00833.html#gaf311101fffad7349aa55d1fc33a29f84", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00542_source.html b/components/els_pkc/doc/mcxn/html/a00542_source.html new file mode 100644 index 000000000..8e82e1a8b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00542_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRANDOMMODES_CONSTANTS_H_
20 #define MCUXCLRANDOMMODES_CONSTANTS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #include <mcuxClRandom_Types.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 /**********************************************************/
31 /* Values for reseeds */
32 /**********************************************************/
33 
34 
35 /**********************************************************/
36 /* Types of mcuxClRandom */
37 /**********************************************************/
52 extern const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg;
53 static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_ELS_Drbg =
54  &mcuxClRandomModes_mdELS_Drbg;
55 
56 
57 #if defined(MCUXCL_FEATURE_RANDOMMODES_NORMALMODE) && defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG)
58 
59 #ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED
60 
61 
62 
63 #ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
64 
72 extern const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdCtrDrbg_AES256_DRG3;
73 static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 =
74  &mcuxClRandomModes_mdCtrDrbg_AES256_DRG3;
75 
86 #define mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG4 mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3
87 
97 #define mcuxClRandomModes_Mode_CtrDrbg_AES256 mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3
98 
99 #endif /* MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 */
100 
101 #endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */
102 
103 
104 
105 #endif /* defined(MCUXCL_FEATURE_RANDOMMODES_NORMALMODE) && defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) */
106  /* mcuxClRandom_Types */
110 
111 #ifdef __cplusplus
112 } /* extern "C" */
113 #endif
114 
115 #endif /* MCUXCLRANDOMMODES_CONSTANTS_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClRandom_ModeDescriptor_t
struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
Random data generation mode/algorithm descriptor type.
Definition: mcuxClRandom_Types.h:86
+
mcuxClRandomModes_mdELS_Drbg
const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg
Mode for a DRBG implemented by the ELS.
+
mcuxClRandom_Mode_t
const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
Random data generation mode/algorithm type.
Definition: mcuxClRandom_Types.h:93
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00545_source.html b/components/els_pkc/doc/mcxn/html/a00545_source.html new file mode 100644 index 000000000..620e74252 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00545_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_Functions_PatchMode.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+ + + +
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_Functions_PatchMode.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_
15 #define MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 
19 #include <mcuxClSession.h>
20 #include <mcuxClRandom_Types.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
40 /* Interface definition for a custom RNG function */
41 typedef mcuxClRandom_Status_t (* mcuxClRandomModes_CustomGenerateAlgorithm_t)(
42  mcuxClSession_Handle_t session,
43  mcuxClRandom_Context_t pCustomCtx,
44  uint8_t *pOut,
45  uint32_t outLength
46 );
47 
66 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_createPatchMode)
67 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createPatchMode(
68  mcuxClRandom_ModeDescriptor_t * patchMode,
69  mcuxClRandomModes_CustomGenerateAlgorithm_t customGenerateAlgorithm,
70  mcuxClRandom_Context_t pCustomCtx,
71  uint32_t securityStrength
72 );
73 
74 
75 #ifdef __cplusplus
76 } /* extern "C" */
77 #endif
78 
79 #endif /* MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClRandom_Context_t
mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
Random context type.
Definition: mcuxClRandom_Types.h:70
+
mcuxClRandom_ModeDescriptor_t
struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
Random data generation mode/algorithm descriptor type.
Definition: mcuxClRandom_Types.h:86
+
mcuxClRandom_Status_t
uint32_t mcuxClRandom_Status_t
Type for status codes of mcuxClRandom component functions.
Definition: mcuxClRandom_Types.h:47
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00548_source.html b/components/els_pkc/doc/mcxn/html/a00548_source.html new file mode 100644 index 000000000..1040ad51d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00548_source.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_Functions_TestMode.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_Functions_TestMode.h
+
+
+
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_
15 #define MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_
16 
17 #include <mcuxClConfig.h> // Exported features flags header
18 
19 #include <mcuxClSession.h>
20 #include <mcuxClRandom_Types.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
55 // TODO: Create defines for entropy input sizes using object size filler
56 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_createTestFromNormalMode)
57 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createTestFromNormalMode(
58  mcuxClRandom_ModeDescriptor_t *pTestMode,
59  mcuxClRandom_Mode_t normalMode,
60  const uint32_t * const pEntropyInput
61 );
62 
72 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_updateEntropyInput)
73 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_updateEntropyInput(
74  mcuxClRandom_ModeDescriptor_t *pTestMode,
75  const uint32_t * const pEntropyInput
76 );
77 
78 #ifdef __cplusplus
79 } /* extern "C" */
80 #endif
81 
82 #endif /* MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClRandom_ModeDescriptor_t
struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
Random data generation mode/algorithm descriptor type.
Definition: mcuxClRandom_Types.h:86
+
mcuxClRandom_Status_t
uint32_t mcuxClRandom_Status_t
Type for status codes of mcuxClRandom component functions.
Definition: mcuxClRandom_Types.h:47
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClRandom_Mode_t
const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
Random data generation mode/algorithm type.
Definition: mcuxClRandom_Types.h:93
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00551.html b/components/els_pkc/doc/mcxn/html/a00551.html new file mode 100644 index 000000000..09ca7ea23 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00551.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClRandomModes_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClRandom component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE
 
+#define MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLRANDOMMODES_INIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00551.js b/components/els_pkc/doc/mcxn/html/a00551.js new file mode 100644 index 000000000..c91a34a95 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00551.js @@ -0,0 +1,15 @@ +var a00551 = +[ + [ "MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE", "a00838.html#ga2e6179f023e993cea2e6d14807f05f50", null ], + [ "MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE", "a00838.html#ga59fbf5778ef6a709439a803f25e01588", null ], + [ "MCUXCLRANDOMMODES_INIT_WACPU_SIZE", "a00838.html#gaec7b900425ae4a868bc28f07f244e012", null ], + [ "MCUXCLRANDOMMODES_RESEED_WACPU_SIZE", "a00838.html#ga50a8e0a649ba1eb61230eb08aad49d92", null ], + [ "MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE", "a00838.html#gaacaa5035a96e553110c4f3b6597a89a0", null ], + [ "MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE", "a00838.html#ga92890503eaf94411a6eceede4bc0804c", null ], + [ "MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE", "a00838.html#ga8ce34613a3418be522d9420f2ab49656", null ], + [ "MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE", "a00838.html#ga641f79548f72b067cebdca4eff78dd76", null ], + [ "MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE", "a00838.html#ga02a8fc4426640dc23d863cdef5afbc61", null ], + [ "MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE", "a00838.html#ga36727c29c2050920e3e68b692dc76aca", null ], + [ "MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE", "a00838.html#gaa2fb0e4c6985e63daae5e11e4031b2a8", null ], + [ "MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE", "a00838.html#ga34185164de955a9bcda1e71bb3bf281e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00551_source.html b/components/els_pkc/doc/mcxn/html/a00551_source.html new file mode 100644 index 000000000..185617efa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00551_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_
20 #define MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_
21 
29 #define MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE (20u)
30 
31 #ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE
32 #define MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE (20u)
33 #endif
34 
35 #define MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE (324u)
36 
37 #define MCUXCLRANDOMMODES_INIT_WACPU_SIZE (312u)
38 #define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE (280u)
39 #define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE (280u)
40 #define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE (324u)
41 #define MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE (0u)
42 #define MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE (0u)
43 #define MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE (0u)
44 #define MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE (0u)
45 #define MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE (0u)
46 #define MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE (0u)
47 
48 #ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG
49 
50 
51 
52 #ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
53 #define MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE (64u)
54 #define MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS ((MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE + sizeof(uint32_t) - 1u) / sizeof(uint32_t))
55 #endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
56 
57 
58 
59 #ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
60 #define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE (72u)
61 #define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE (56u)
62 #endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256
63 
64 #endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */
65 
66  /* mcuxClRandomModes_MemoryConsumption */
70 
71 #endif /* MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00554.html b/components/els_pkc/doc/mcxn/html/a00554.html new file mode 100644 index 000000000..908a886cf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00554.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClRsa.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
+
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+ + +
+ +
+ +
+
+
mcuxClRsa.h File Reference
+
+
+ +

Top-level include file for the mcuxClRsa component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClRsa_Functions.h>
+#include <mcuxClRsa_MemoryConsumption.h>
+#include <mcuxClRsa_Constants.h>
+#include <mcuxClRsa_Types.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClRsa component.

+

This includes headers for all of the functionality provided by the mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00554_source.html b/components/els_pkc/doc/mcxn/html/a00554_source.html new file mode 100644 index 000000000..12e776ef4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00554_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxClRsa.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClRsa.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
58 #ifndef MCUXCLRSA_H_
59 #define MCUXCLRSA_H_
60 
61 #include <mcuxClConfig.h> // Exported features flags header
62 #include <mcuxClRsa_Functions.h>
63 #include <mcuxClRsa_MemoryConsumption.h>
64 #include <mcuxClRsa_Constants.h>
65 #include <mcuxClRsa_Types.h>
66 #endif /* MCUXCLRSA_H_ */
mcuxClRsa_MemoryConsumption.h
Defines the memory consumption for the mcuxClRsa component.
+
mcuxClRsa_Types.h
Type definitions for the mcuxClRsa component.
+
mcuxClRsa_Constants.h
Constant definitions for the mcuxClRsa component.
+
mcuxClRsa_Functions.h
Top-level API of the mcuxClRsa component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00557.html b/components/els_pkc/doc/mcxn/html/a00557.html new file mode 100644 index 000000000..8882d691d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00557.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Constants.h File Reference + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Variables
+
+
mcuxClRsa_Constants.h File Reference
+
+
+ +

Constant definitions for the mcuxClRsa component. +More...

+
#include <mcuxClConfig.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode
 Mode definition for RSASP1. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/512. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224
 Mode definition for RSASSA-PSS-SIGN using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256
 Mode definition for RSASSA-PSS-SIGN using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384
 Mode definition for RSASSA-PSS-SIGN using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512
 Mode definition for RSASSA-PSS-SIGN using SHA-2/512. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify
 Mode definition for RSAVP1. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/512. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/512. More...
 
+

Detailed Description

+

Constant definitions for the mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00557.js b/components/els_pkc/doc/mcxn/html/a00557.js new file mode 100644 index 000000000..ac6375960 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00557.js @@ -0,0 +1,21 @@ +var a00557 = +[ + [ "mcuxClRsa_Mode_Sign_NoEncode", "a00841.html#ga4459d773156bf4ac906a1416dd4ed4f4", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224", "a00841.html#gac7cfd526cb16ba49a48ea0881c12e778", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256", "a00841.html#ga1845c307f6b2897cf563c1ad97523840", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384", "a00841.html#ga2e630f5e6e06e0b5adc2d5f63268b77f", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512", "a00841.html#ga61cdf384d5eb7774a35bec2dd28b67c8", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_224", "a00841.html#ga6544c3cc75077dde34304c5c45999edf", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_256", "a00841.html#gaf88819f8def0ed1dc626168103856a25", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_384", "a00841.html#ga884749f4e133157dcdc3b85d15b98ada", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_512", "a00841.html#gab71896db47c552effcdad152a574e5a1", null ], + [ "mcuxClRsa_Mode_Verify_NoVerify", "a00842.html#ga9274985a905326fe0bcbe3ab23123e75", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224", "a00842.html#gafaa7d91b00e9a3e5edbcc8ea8d0d2320", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256", "a00842.html#gaebc33a997f28ae34f977899c4da4f117", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384", "a00842.html#ga6e5c11f4096af091859db6a5f3009c43", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512", "a00842.html#gafc855e8c67d58fc5b0e79e89eac6d976", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_224", "a00842.html#gaba34c04545877c67789942d9a2c9134a", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_256", "a00842.html#gab80d7f48edeb8b4c401221180572e4f2", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_384", "a00842.html#ga74c434306a9d393e51b4997152381b8e", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_512", "a00842.html#ga4214b439b403de8eda53043cdf71ca83", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00557_source.html b/components/els_pkc/doc/mcxn/html/a00557_source.html new file mode 100644 index 000000000..892993f18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00557_source.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Constants.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRsa_Constants.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRSA_CONSTANTS_H_
20 #define MCUXCLRSA_CONSTANTS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* TODO:
29  * Using defines for SGI Hashes is a workaround to enable testing of internal padding functions. This should not be in the CL, as mode constructors are used for S5xy.
30  * CL artifact to remove this workaround: CLNS-6116
31  * TT artifact to adapt the tests: CLNS-6117
32  */
33 
51 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode;
52 
56 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224;
57 
61 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256;
62 
66 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384;
67 
71 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512;
72 
76 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224;
77 
81 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256;
82 
86 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384;
87 
91 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512;
92 
107 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify;
108 
112 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224;
113 
117 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256;
118 
122 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384;
123 
127 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512;
128 
132 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224;
133 
137 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256;
138 
142 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384;
143 
147 extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512;
148 
154 #ifdef __cplusplus
155 } /* extern "C" */
156 #endif
157 
158 #endif /* MCUXCLRSA_CONSTANTS_H_ */
mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224
Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/224.
+
mcuxClRsa_Mode_Verify_Pss_Sha2_384
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384
Mode definition for RSASSA-PSS-VERIFY using SHA-2/384.
+
mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384
Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/384.
+
mcuxClRsa_Mode_Verify_NoVerify
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify
Mode definition for RSAVP1.
+
mcuxClRsa_Mode_Verify_Pss_Sha2_224
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224
Mode definition for RSASSA-PSS-VERIFY using SHA-2/224.
+
mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384
Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/384.
+
mcuxClRsa_Mode_Sign_Pss_Sha2_512
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512
Mode definition for RSASSA-PSS-SIGN using SHA-2/512.
+
mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256
Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/256.
+
mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512
Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/512.
+
mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256
Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/256.
+
mcuxClRsa_Mode_Verify_Pss_Sha2_256
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256
Mode definition for RSASSA-PSS-VERIFY using SHA-2/256.
+
mcuxClRsa_Mode_Sign_Pss_Sha2_384
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384
Mode definition for RSASSA-PSS-SIGN using SHA-2/384.
+
mcuxClRsa_Mode_Sign_Pss_Sha2_256
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256
Mode definition for RSASSA-PSS-SIGN using SHA-2/256.
+
mcuxClRsa_SignVerifyMode_t
struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t
Forward declaration of Sign/Verify mode struct.
Definition: mcuxClRsa_Types.h:179
+
mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512
Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/512.
+
mcuxClRsa_Mode_Sign_NoEncode
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode
Mode definition for RSASP1.
+
mcuxClRsa_Mode_Sign_Pss_Sha2_224
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224
Mode definition for RSASSA-PSS-SIGN using SHA-2/224.
+
mcuxClRsa_Mode_Verify_Pss_Sha2_512
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512
Mode definition for RSASSA-PSS-VERIFY using SHA-2/512.
+
mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224
Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/224.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00560.html b/components/els_pkc/doc/mcxn/html/a00560.html new file mode 100644 index 000000000..2aa3e2ab4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00560.html @@ -0,0 +1,153 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRsa_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClRsa component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxClKey.h>
+#include <mcuxClRsa_Types.h>
+#include <mcuxClCore_Buffer.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Functions

mcuxClRsa_Status_t mcuxClRsa_sign (mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, const mcuxClRsa_SignVerifyMode pPaddingMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pSignature)
 RSA sign operation. More...
 
mcuxClRsa_Status_t mcuxClRsa_verify (mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, mcuxCl_Buffer_t pSignature, const mcuxClRsa_SignVerifyMode pVerifyMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pOutput)
 RSA verify operation. More...
 
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Crt (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 Generates an RSA key in CRT format. More...
 
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Plain (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 RSA key generation of private plain key operation. More...
 
+

Detailed Description

+

Top-level API of the mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00560.js b/components/els_pkc/doc/mcxn/html/a00560.js new file mode 100644 index 000000000..d157e8866 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00560.js @@ -0,0 +1,7 @@ +var a00560 = +[ + [ "mcuxClRsa_sign", "a00843.html#gaea19a43d7a52c159675d93d8e7d6ec51", null ], + [ "mcuxClRsa_verify", "a00843.html#ga21bf92b81f28be1b6b6fc7d3bdc69098", null ], + [ "mcuxClRsa_KeyGeneration_Crt", "a00843.html#gaa099449b2290a333aac2dcf090a2740c", null ], + [ "mcuxClRsa_KeyGeneration_Plain", "a00843.html#ga08dff8d41898b3f372ceab1038205b51", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00560_source.html b/components/els_pkc/doc/mcxn/html/a00560_source.html new file mode 100644 index 000000000..43cf1dc3f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00560_source.html @@ -0,0 +1,141 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Functions.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxClRsa_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRSA_FUNCTIONS_H_
20 #define MCUXCLRSA_FUNCTIONS_H_
21 
22 #include <mcuxClConfig.h> // Exported features flags header
23 #include <mcuxClSession.h>
24 #include <mcuxCsslFlowProtection.h>
25 #include <mcuxClCore_FunctionIdentifiers.h>
26 #include <mcuxClKey.h>
27 #include <mcuxClRsa_Types.h>
28 #include <mcuxClCore_Buffer.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
118 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_sign)
119 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_sign(
120  mcuxClSession_Handle_t pSession,
121  const mcuxClRsa_Key * const pKey,
122  mcuxCl_InputBuffer_t pMessageOrDigest,
123  const uint32_t messageLength,
124  const mcuxClRsa_SignVerifyMode pPaddingMode,
125  const uint32_t saltLength,
126  const uint32_t options,
127  mcuxCl_Buffer_t pSignature
128 );
129 
201 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_verify)
202 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_verify(
203  mcuxClSession_Handle_t pSession,
204  const mcuxClRsa_Key * const pKey,
205  mcuxCl_InputBuffer_t pMessageOrDigest,
206  const uint32_t messageLength,
207  mcuxCl_Buffer_t pSignature,
208  const mcuxClRsa_SignVerifyMode pVerifyMode,
209  const uint32_t saltLength,
210  const uint32_t options,
211  mcuxCl_Buffer_t pOutput
212 );
213 
214 
215 
216 
284 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_KeyGeneration_Crt)
285 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Crt(
286  mcuxClSession_Handle_t pSession,
287  mcuxClKey_Type_t type,
288  mcuxClKey_Protection_t protection,
289  mcuxClKey_Handle_t privKey,
290  uint8_t * pPrivData,
291  uint32_t * const pPrivDataLength,
292  mcuxClKey_Handle_t pubKey,
293  uint8_t * pPubData,
294  uint32_t * const pPubDataLength
295  );
296 
297 
365 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_KeyGeneration_Plain)
366 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Plain(
367  mcuxClSession_Handle_t pSession,
368  mcuxClKey_Type_t type,
369  mcuxClKey_Protection_t protection,
370  mcuxClKey_Handle_t privKey,
371  uint8_t * pPrivData,
372  uint32_t * const pPrivDataLength,
373  mcuxClKey_Handle_t pubKey,
374  uint8_t * pPubData,
375  uint32_t * const pPubDataLength
376  );
377 
378  /* mcuxClRsa_Functions */
382 
383 #ifdef __cplusplus
384 } /* extern "C" */
385 #endif
386 
387 #endif /* MCUXCLRSA_FUNCTIONS_H_ */
388 
mcuxClRsa_Status_t
uint32_t mcuxClRsa_Status_t
Type for RSA status codes.
Definition: mcuxClRsa_Types.h:115
+
mcuxClRsa_Key
Structure type for Rsa key, specifying key type and key entries.
Definition: mcuxClRsa_Types.h:143
+
mcuxClKey_Type_t
const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
Key type handle type.
Definition: mcuxClKey_Types.h:111
+
mcuxClKey.h
Top-level include file for the mcuxClKey component.
+
mcuxClRsa_KeyGeneration_Crt
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Crt(mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
Generates an RSA key in CRT format.
+
mcuxClKey_Handle_t
mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
Key handle type.
Definition: mcuxClKey_Types.h:88
+
mcuxClRsa_SignVerifyMode
mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode
Pointer type to Sign/Verify mode.
Definition: mcuxClRsa_Types.h:184
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClKey_Protection_t
const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
Key protection mechanism type.
Definition: mcuxClKey_Types.h:141
+
mcuxClRsa_Types.h
Type definitions for the mcuxClRsa component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClRsa_verify
mcuxClRsa_Status_t mcuxClRsa_verify(mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, mcuxCl_Buffer_t pSignature, const mcuxClRsa_SignVerifyMode pVerifyMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pOutput)
RSA verify operation.
+
mcuxClRsa_KeyGeneration_Plain
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Plain(mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
RSA key generation of private plain key operation.
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCl_Buffer_t
uint8_t *const mcuxCl_Buffer_t
Generic buffer typeThis type provides a pointer to the memory location that can be used for both read...
Definition: mcuxClCore_Buffer.h:51
+
mcuxCl_InputBuffer_t
const uint8_t *const mcuxCl_InputBuffer_t
Input buffer typeThis type provides a pointer to the memory location that should be used to read inpu...
Definition: mcuxClCore_Buffer.h:42
+
mcuxClRsa_sign
mcuxClRsa_Status_t mcuxClRsa_sign(mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, const mcuxClRsa_SignVerifyMode pPaddingMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pSignature)
RSA sign operation.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00563.html b/components/els_pkc/doc/mcxn/html/a00563.html new file mode 100644 index 000000000..0445f9a79 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00563.html @@ -0,0 +1,353 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
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+
mcuxClRsa_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClRsa component. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_NoVerify. More...
 
#define MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PssVerify. More...
 
#define MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_VERIFY_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 1024-bit keys. More...
 
#define MCUXCLRSA_VERIFY_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 2048-bit keys. More...
 
#define MCUXCLRSA_VERIFY_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 3072-bit keys. More...
 
#define MCUXCLRSA_VERIFY_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 4096-bit keys. More...
 
#define MCUXCLRSA_VERIFY_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size (in bytes) for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size (in bytes) for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the public key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the public key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the public key data for 4096-bit keys. More...
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00563.js b/components/els_pkc/doc/mcxn/html/a00563.js new file mode 100644 index 000000000..28aa715bf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00563.js @@ -0,0 +1,76 @@ +var a00563 = +[ + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE", "a00844.html#ga62affe57ed8b934c432d1e4957ca2b96", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE", "a00844.html#ga0771ad370b59155e8fee261c84e51531", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE", "a00844.html#gae3e6841f0361a7df7d5308d663b114c6", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE", "a00844.html#ga34b88e6a0e6b4168b989aa9d6bf9c569", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE", "a00844.html#gaa605aa3b59dcc107147ddeb6fcb7e8c0", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE", "a00844.html#ga4312eb8909ce30ba6362af6aaa03f69e", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE", "a00844.html#gaf455d79389af05675935d6d53d7ade7c", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE", "a00844.html#ga164cca6715f5d4ad090ccc4ab882dd68", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE", "a00844.html#ga773066aea6da7ba38442305ad2bf6af2", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE", "a00844.html#ga1dea31cb3edffff3b19d105f7374aa81", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE", "a00844.html#ga25a8fb0b64b30957a85d6cc8ccff3694", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE", "a00844.html#ga6c85361c450a7a291e4a21ba5ad8c829", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE", "a00844.html#gaa0b8b7e5e999f0f647b157570879ab70", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE", "a00844.html#ga48f0eed84fa89303aab8926a5af140e0", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE", "a00844.html#gab630a43086137a34a22d379d99d4979e", null ], + [ "MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE", "a00844.html#ga48b4346142911ddd75ac4bb4575b4a44", null ], + [ "MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE", "a00844.html#ga5b2d3626004c26e5935658c75faed0fe", null ], + [ "MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE", "a00844.html#ga87f2af5e231ca701d6c241260f6632c8", null ], + [ "MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE", "a00844.html#gac51d995815daa1270660faa6c941556b", null ], + [ "MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE", "a00844.html#gab592bb2afe239d110b69019bbcfbf39a", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE", "a00844.html#ga08af4d804d4c5dd22c246fe4ee55afd1", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE", "a00844.html#gada60205f871f7cbdff86547038599ec8", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE", "a00844.html#gaa9fbd44b2d8b333ef36b98aa36d8ce91", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE", "a00844.html#ga9afbf286d2d7eda637ba13f19bbf727f", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE", "a00844.html#ga97d05e715e7d13e8eccdaad372e7d50a", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE", "a00844.html#ga94c5de50e6e2c146a56ca41fe875b1ae", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE", "a00844.html#gaffa8f7a22bc5dc5f0102e6a7d58aae22", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE", "a00844.html#ga622d0a8ac987bd0a74fbf3a6aafb0622", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE", "a00844.html#ga56c7e14b62345bd224a7dd133c9cf47e", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE", "a00844.html#gaae863be535c94424a53999e430f94345", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE", "a00844.html#gaf8a8d4ef6856d0325171771a38ed2b3f", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE", "a00844.html#ga13a37dc2bf4e9369d0f97257eedbb240", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE", "a00844.html#gaf1c40d9d43240fca324f6bddb7ba22b2", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE", "a00844.html#ga85c6c2f1faf8413022119493161d08eb", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE", "a00844.html#ga437b8eb62b4f1c455f0fcf9185dee790", null ], + [ "MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE", "a00844.html#gaace82904ad5b20b810d80d9561e6277b", null ], + [ "MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE", "a00844.html#gaab6efa4449159180daf2c0ad4452283c", null ], + [ "MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE", "a00844.html#ga7844b694581a8cb752edd86444a10812", null ], + [ "MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE", "a00844.html#ga56f2ed2760ce4db4e8246d96f768e23e", null ], + [ "MCUXCLRSA_SIGN_CRT_WAPKC_SIZE", "a00844.html#gae92072e416a0f52664b7720d33b1fd91", null ], + [ "MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE", "a00845.html#gac0a79e3e30fbf6610c95ad399bb55165", null ], + [ "MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE", "a00845.html#gaf4bcc54a8a49029c2454d0afdca0a18e", null ], + [ "MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE", "a00845.html#gab9dc9df4db1e42592e9f23b90abf7432", null ], + [ "MCUXCLRSA_VERIFY_1024_WAPKC_SIZE", "a00845.html#gaf6485ca0f6a219994ba327e9f35dbb94", null ], + [ "MCUXCLRSA_VERIFY_2048_WAPKC_SIZE", "a00845.html#ga347b86aaa2ec9e1c6b42d53b8b550139", null ], + [ "MCUXCLRSA_VERIFY_3072_WAPKC_SIZE", "a00845.html#gaf370a2aea81eaa53070ecd49de1291fb", null ], + [ "MCUXCLRSA_VERIFY_4096_WAPKC_SIZE", "a00845.html#ga8472e567acdaf653ea64617586e69dd5", null ], + [ "MCUXCLRSA_VERIFY_WAPKC_SIZE", "a00845.html#ga1890b9a82cba6144b533121da365baeb", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE", "a00846.html#gad96d63918b029c58379a519458e0fe5e", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE", "a00846.html#ga4f7ea947e335da713b995b3dd5756726", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE", "a00846.html#ga7cd47280b5c29ab35fe15afdb1aff9b5", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE", "a00846.html#gab62b9607b6acf175174f192227482782", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE", "a00846.html#ga50df60e5ac10a4d18d91793b9975f931", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE", "a00846.html#ga9cddbdf9c06180c1ad4f1004c013a3b0", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE", "a00846.html#ga046e2a5713b8ad6d69f9882d2fde5b3f", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE", "a00846.html#ga398705431e601a6309bcf59a65f72328", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE", "a00847.html#ga8bfbe68f2ddf833c65badc56832310ff", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE", "a00847.html#ga499a98e9b3b5f98b43d41bace11d6d2a", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE", "a00847.html#gacfaaad0cd3da9dd167a4068a2a2fda7f", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE", "a00847.html#gab0c5e4df4d6371815ec7b1d962053507", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE", "a00847.html#gaeaf97fe967de3e01d06b80d4aecf62ba", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE", "a00847.html#ga76dbc936b3c90bf4e66824697b16be80", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE", "a00847.html#ga2e6c1c9053ca24c4101e348c9f8d2588", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE", "a00847.html#ga989c3c758b19a6f32cb0ac16dc698bc2", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE", "a00848.html#gaad6be857cb7e5a3e95f09e0122f2e94a", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE", "a00848.html#gab391bd614cb01e50e382c9dd20c17666", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE", "a00848.html#gaa60cf674b45656cf7500cd50749d8088", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE", "a00848.html#ga726a733c6b7203ed8ffb1fcc542d3947", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE", "a00848.html#ga42819dfa5d08299cd05b1589d354aea8", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE", "a00848.html#ga9326e34e5b0cae6bba738466a089b523", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE", "a00848.html#gae34fdb8022b5b8b2d62794b19ed310cf", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE", "a00848.html#ga78776bc5abbc55e6ebe24450dac788f3", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE", "a00848.html#ga0cb2520b3056a154c1d551b2a677dd12", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00563_source.html b/components/els_pkc/doc/mcxn/html/a00563_source.html new file mode 100644 index 000000000..2f5f967c0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00563_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRsa_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRSA_MEMORYCONSUMPTION_H_
20 #define MCUXCLRSA_MEMORYCONSUMPTION_H_
21 
22 
23 /****************************************************************************/
24 /* Definitions of workarea sizes for the mcuxClRsa Sign */
25 /****************************************************************************/
26 
33 #define MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE (152u)
34 #define MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE (280u)
35 #define MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE (408u)
36 #define MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE (536u)
37 
38 #define MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE(keyBitLength) \
39  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE : \
40  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE : \
41  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE : \
42  MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE)))
43 
44 #define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE (196u)
45 #define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE (280u)
46 #define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE (408u)
47 #define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE (536u)
48 #define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE(keyBitLength) \
49  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE : \
50  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE : \
51  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE : \
52  MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE)))
53 
54 #define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE (196u)
55 #define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE (280u)
56 #define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE (408u)
57 #define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE (536u)
58 #define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength) \
59  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE : \
60  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE : \
61  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE : \
62  MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE)))
63 
64 #define MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE (1064u)
65 #define MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE (1960u)
66 #define MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE (2856u)
67 #define MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE (3752u)
68 #define MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE(keyBitLength) \
69  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE : \
70  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE : \
71  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE : \
72  MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE)))
73 
74 #define MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE (104u)
75 #define MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE (168u)
76 #define MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE (232u)
77 #define MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE (296u)
78 
79 #define MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE(keyBitLength) \
80  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE : \
81  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE : \
82  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE : \
83  MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE)))
84 
85 #define MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE (196u)
86 #define MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE (196u)
87 #define MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE (232u)
88 #define MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE (296u)
89 #define MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE(keyBitLength) \
90  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE : \
91  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE : \
92  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE : \
93  MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE)))
94 
95 #define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE (196u)
96 #define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE (196u)
97 #define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE (232u)
98 #define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE (296u)
99 #define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength) \
100  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE : \
101  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE : \
102  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE : \
103  MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE)))
104 
105 #define MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE (968u)
106 #define MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE (1864u)
107 #define MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE (2760u)
108 #define MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE (3656u)
109 #define MCUXCLRSA_SIGN_CRT_WAPKC_SIZE(keyBitLength) \
110  ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE : \
111  ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE : \
112  ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE : \
113  MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE)))
114 
115 
117 /****************************************************************************/
118 /* Definitions of workarea sizes for the mcuxClRsa Verify */
119 /****************************************************************************/
128 #define MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE (16u)
129 #define MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE (196u)
130 #define MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE (196u)
131 
132 #define MCUXCLRSA_VERIFY_1024_WAPKC_SIZE (800u)
133 #define MCUXCLRSA_VERIFY_2048_WAPKC_SIZE (1568u)
134 #define MCUXCLRSA_VERIFY_3072_WAPKC_SIZE (2336u)
135 #define MCUXCLRSA_VERIFY_4096_WAPKC_SIZE (3104u)
136 #define MCUXCLRSA_VERIFY_WAPKC_SIZE(keyBitLength) \
137  ((3072u < (keyBitLength)) ? MCUXCLRSA_VERIFY_4096_WAPKC_SIZE : \
138  ((2048u < (keyBitLength)) ? MCUXCLRSA_VERIFY_3072_WAPKC_SIZE : \
139  ((1024u < (keyBitLength)) ? MCUXCLRSA_VERIFY_2048_WAPKC_SIZE : \
140  MCUXCLRSA_VERIFY_1024_WAPKC_SIZE)))
141 
142 
143 
147 /**********************************************************************************/
148 /* Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function. */
149 /**********************************************************************************/
156 #define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE (632u)
157 #define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE (760u)
158 #define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE (888u)
159 #define MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE(keyBitLength) \
160  ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE : \
161  ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE : \
162  MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE))
163 
164 #define MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE (1656u)
165 #define MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE (2424u)
166 #define MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE (3192u)
167 #define MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE(keyBitLength) \
168  ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE : \
169  ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE : \
170  MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE))
171 
172 
174 /********************************************************************************/
175 /* Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function. */
176 /********************************************************************************/
183 #define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE (620u)
184 #define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE (748u)
185 #define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE (876u)
186 #define MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE(keyBitLength) \
187  ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE : \
188  ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE : \
189  MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE))
190 
191 #define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE (1832u)
192 #define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE (2728u)
193 #define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE (3624u)
194 #define MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE(keyBitLength) \
195  ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE : \
196  ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE : \
197  MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE))
198 
199 
201 /*************************************************************************************************************************/
202 /* Definitions of generated key data size for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. */
203 /*************************************************************************************************************************/
210 #define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE (556u)
211 #define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE (812u)
212 #define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE (1068u)
213 
214 #define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE (708u)
215 #define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE (1028u)
216 #define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE (1348u)
217 
218 #define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE (556u)
219 #define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE (812u)
220 #define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE (1068u)
221 
222 
225 #endif /* MCUXCLRSA_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00566.html b/components/els_pkc/doc/mcxn/html/a00566.html new file mode 100644 index 000000000..b2c988c9d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00566.html @@ -0,0 +1,224 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Data Structures | +Macros | +Typedefs
+
+
mcuxClRsa_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClRsa component. +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <mcuxClConfig.h>
+#include <mcuxClSession.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + +

+Data Structures

struct  mcuxClRsa_KeyEntry_t
 Structure type for Rsa key entries, specifying key entry length and data. More...
 
struct  mcuxClRsa_Key
 Structure type for Rsa key, specifying key type and key entries. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_STATUS_SIGN_OK
 RSA sign operation successful. More...
 
#define MCUXCLRSA_STATUS_VERIFY_OK
 RSA verify operation successful. More...
 
#define MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK
 RSA verify primitive operation (RSAVP1) successful. More...
 
#define MCUXCLRSA_STATUS_ERROR
 Error occurred during RSA operation. More...
 
#define MCUXCLRSA_STATUS_INVALID_INPUT
 Input data cannot be processed. More...
 
#define MCUXCLRSA_STATUS_VERIFY_FAILED
 Signature verification failed. More...
 
#define MCUXCLRSA_STATUS_FAULT_ATTACK
 Fault attack detected. More...
 
#define MCUXCLRSA_STATUS_KEYGENERATION_OK
 RSA key generation operation executed successfully. More...
 
#define MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED
 RSA key generation exceeds the limit of iterations to generate a prime. More...
 
#define MCUXCLRSA_STATUS_RNG_ERROR
 Random number (DRBG / PRNG) error (unexpected behavior) More...
 
#define MCUXCLRSA_KEY_PUBLIC
 RSA key type public. More...
 
#define MCUXCLRSA_KEY_PRIVATEPLAIN
 RSA key type private plain. More...
 
#define MCUXCLRSA_KEY_PRIVATECRT
 RSA key type private CRT. More...
 
#define MCUXCLRSA_KEY_PRIVATECRT_DFA
 RSA key type private CRT, with which a fault-protected CRT operation is executed. More...
 
#define MCUXCLRSA_OPTION_MESSAGE_PLAIN
 Option passing a plain message as input to the sign or verify operation. More...
 
#define MCUXCLRSA_OPTION_MESSAGE_DIGEST
 Option passing a message digest as input to the sign or verify operation. More...
 
#define MCUXCLRSA_OPTION_MESSAGE_MASK
 Mask to set option MESSAGE_PLAIN or MESSAGE_DIGEST. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClRsa_Status_t
 Type for RSA status codes. More...
 
typedef mcuxClRsa_Status_t mcuxClRsa_Status_Protected_t
 Deprecated type for RSA protected status codes. More...
 
typedef mcuxClRsa_KeyEntry_t * mcuxClRsa_KeyEntry
 Pointer type to Rsa key entries. More...
 
typedef struct mcuxClRsa_Key mcuxClRsa_Key
 Structure type for Rsa key, specifying key type and key entries. More...
 
typedef struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t
 Forward declaration of Sign/Verify mode struct. More...
 
typedef mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode
 Pointer type to Sign/Verify mode. More...
 
+

Detailed Description

+

Type definitions for the mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00566.js b/components/els_pkc/doc/mcxn/html/a00566.js new file mode 100644 index 000000000..ccde08154 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00566.js @@ -0,0 +1,26 @@ +var a00566 = +[ + [ "MCUXCLRSA_STATUS_SIGN_OK", "a00850.html#gac7719ba5cbecc181bef2b21dca99fdf3", null ], + [ "MCUXCLRSA_STATUS_VERIFY_OK", "a00850.html#ga2dbb489ad7452a487a5d49df5a979d69", null ], + [ "MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK", "a00850.html#gadabda4063a5cfe9766a7201d271d8f0a", null ], + [ "MCUXCLRSA_STATUS_ERROR", "a00850.html#gac062bb04172f071a8595aa39bef80edc", null ], + [ "MCUXCLRSA_STATUS_INVALID_INPUT", "a00850.html#ga14e28c4e4b6a325ddd1f038b5274ccec", null ], + [ "MCUXCLRSA_STATUS_VERIFY_FAILED", "a00850.html#ga05d091562f747706d7aecfb99b5a735c", null ], + [ "MCUXCLRSA_STATUS_FAULT_ATTACK", "a00850.html#gaf886957f4dc2794dd12839a690ae05d0", null ], + [ "MCUXCLRSA_STATUS_KEYGENERATION_OK", "a00850.html#gab08354492e4b0feceab7a3615abee1f0", null ], + [ "MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED", "a00850.html#ga90072cc31c18394f5e5d3a2e63e014fa", null ], + [ "MCUXCLRSA_STATUS_RNG_ERROR", "a00850.html#gadd600ddd2a4c8c2fc79f427e438f81f4", null ], + [ "MCUXCLRSA_KEY_PUBLIC", "a00851.html#ga4c194e24352de4ab02294292f35f24d9", null ], + [ "MCUXCLRSA_KEY_PRIVATEPLAIN", "a00851.html#ga16c4298a66c8a1a7c2e18aca938442a6", null ], + [ "MCUXCLRSA_KEY_PRIVATECRT", "a00851.html#gade33615f2bc73e552ca020a1e43a41c3", null ], + [ "MCUXCLRSA_KEY_PRIVATECRT_DFA", "a00851.html#gac5562ce31d1bc26cf93b647a17e38814", null ], + [ "MCUXCLRSA_OPTION_MESSAGE_PLAIN", "a00852.html#ga60de22c98680641aaef3331fbd5bb0f1", null ], + [ "MCUXCLRSA_OPTION_MESSAGE_DIGEST", "a00852.html#gaae780b6c51aa31e7e9f20cb2afddf9c6", null ], + [ "MCUXCLRSA_OPTION_MESSAGE_MASK", "a00852.html#gac091ddc4844c510873c4492061ce7a5f", null ], + [ "mcuxClRsa_Status_t", "a00853.html#gab654093108d59a4690e464f314356e69", null ], + [ "mcuxClRsa_Status_Protected_t", "a00853.html#ga60189e258e6739b78e900b025be0ab34", null ], + [ "mcuxClRsa_KeyEntry", "a00853.html#ga45ab9e1108bb7a629af14c74d8392622", null ], + [ "mcuxClRsa_Key", "a00853.html#gaa10abda6e87540ddd4db42c84aa5f8f5", null ], + [ "mcuxClRsa_SignVerifyMode_t", "a00853.html#gabe334b37ac763b3943364b26e130d0df", null ], + [ "mcuxClRsa_SignVerifyMode", "a00853.html#ga9135a8d95f26a1b90c7a251886bce7e5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00566_source.html b/components/els_pkc/doc/mcxn/html/a00566_source.html new file mode 100644 index 000000000..cf73159bd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00566_source.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Types.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
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+ +
+ +
+
+
mcuxClRsa_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLRSA_TYPES_H_
20 #define MCUXCLRSA_TYPES_H_
21 
22 #include <stdint.h>
23 #include <stddef.h>
24 #include <stdbool.h>
25 #include <mcuxClConfig.h> // Exported features flags header
26 #include <mcuxClSession.h>
27 #include <mcuxCsslFlowProtection.h>
28 #include <mcuxClCore_FunctionIdentifiers.h>
29 
30 /***********************************************************
31  * MACROS
32  **********************************************************/
33 
41 /***********************************************************
42  * MACROS RELATED TO FUNCTION STATUS
43  **********************************************************/
44 
51 #define MCUXCLRSA_STATUS_SIGN_OK ((mcuxClRsa_Status_t) 0x0FF62E03u )
52 #define MCUXCLRSA_STATUS_VERIFY_OK ((mcuxClRsa_Status_t) 0x0FF62E07u )
53 #define MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK ((mcuxClRsa_Status_t) 0x0FF62E0Bu )
54 #define MCUXCLRSA_STATUS_ERROR ((mcuxClRsa_Status_t) 0x0FF65330u )
55 #define MCUXCLRSA_STATUS_INVALID_INPUT ((mcuxClRsa_Status_t) 0x0FF653F8u )
56 #define MCUXCLRSA_STATUS_VERIFY_FAILED ((mcuxClRsa_Status_t) 0x0FF68930u )
57 #define MCUXCLRSA_STATUS_FAULT_ATTACK ((mcuxClRsa_Status_t) 0x0FF6F0F0u )
58 #define MCUXCLRSA_STATUS_KEYGENERATION_OK ((mcuxClRsa_Status_t) 0x0FF62E0Fu )
59 #define MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED ((mcuxClRsa_Status_t) 0x0FF68934u )
60 #define MCUXCLRSA_STATUS_RNG_ERROR ((mcuxClRsa_Status_t) 0x0FF65338u )
61 
62 
65 /***********************************************************
66  * MACROS RELATED TO RSA KEY
67  **********************************************************/
74 #define MCUXCLRSA_KEY_PUBLIC (0xA5A5A5A5U)
75 #define MCUXCLRSA_KEY_PRIVATEPLAIN (0x5A5A5A5AU)
76 #define MCUXCLRSA_KEY_PRIVATECRT (0xB4B4B4B4U)
77 #define MCUXCLRSA_KEY_PRIVATECRT_DFA (0x4B4B4B4BU)
78 
81 /***********************************************************
82  * MACROS RELATED TO PUBLIC FUNCTIONS' OPTIONS
83  **********************************************************/
84 
90 #define MCUXCLRSA_OPTION_MESSAGE_PLAIN (0XA5U)
91 #define MCUXCLRSA_OPTION_MESSAGE_DIGEST (0X5AU)
92 #define MCUXCLRSA_OPTION_MESSAGE_MASK (MCUXCLRSA_OPTION_MESSAGE_PLAIN | MCUXCLRSA_OPTION_MESSAGE_DIGEST)
93 
98 /**********************************************
99  * TYPEDEFS
100  **********************************************/
101 
108 /***********************************************************
109  * TYPES RELATED TO FUNCTION STATUS
110  **********************************************************/
111 
115 typedef uint32_t mcuxClRsa_Status_t;
116 
120 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_Status_Protected_t;
121 
122 /***********************************************************
123  * TYPES RELATED TO RSA KEY
124  **********************************************************/
128 typedef struct
129 {
130  uint8_t* pKeyEntryData;
131  uint32_t keyEntryLength;
132 }mcuxClRsa_KeyEntry_t;
133 
137 // TODO CLNS-6135: replace all occurrences of "mcuxClRsa_KeyEntry" by "mcuxClRsa_KeyEntry_t *", which is more explicit for a type
138 typedef mcuxClRsa_KeyEntry_t * mcuxClRsa_KeyEntry;
139 
143 typedef struct mcuxClRsa_Key
144 {
145  uint32_t keytype;
146  mcuxClRsa_KeyEntry_t * pMod1;
151  mcuxClRsa_KeyEntry_t * pMod2;
154  mcuxClRsa_KeyEntry_t * pQInv;
157  mcuxClRsa_KeyEntry_t * pExp1;
160  mcuxClRsa_KeyEntry_t * pExp2;
164  mcuxClRsa_KeyEntry_t * pExp3;
167 } mcuxClRsa_Key;
170 
171 
172 /***********************************************************
173  * TYPES RELATED TO SIGN / VERIFY FUNCTIONALITY
174  **********************************************************/
175 
179 typedef struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t;
180 
184 typedef mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode;
185 
191 #endif /* MCUXCLRSA_TYPES_H_ */
192 
mcuxClRsa_Key::pQInv
mcuxClRsa_KeyEntry_t * pQInv
Pointer to third key entry:
Definition: mcuxClRsa_Types.h:156
+
mcuxClRsa_Status_t
uint32_t mcuxClRsa_Status_t
Type for RSA status codes.
Definition: mcuxClRsa_Types.h:115
+
mcuxClRsa_Key::keytype
uint32_t keytype
Key type specifier:
Definition: mcuxClRsa_Types.h:145
+
mcuxClRsa_Key
Structure type for Rsa key, specifying key type and key entries.
Definition: mcuxClRsa_Types.h:143
+
mcuxClRsa_Key::pExp2
mcuxClRsa_KeyEntry_t * pExp2
Pointer to fifth key entry:
Definition: mcuxClRsa_Types.h:163
+
mcuxClRsa_KeyEntry_t::keyEntryLength
uint32_t keyEntryLength
Byte-length of the buffer pointed to by pKeyEntryData.
Definition: mcuxClRsa_Types.h:131
+
mcuxClRsa_SignVerifyMode
mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode
Pointer type to Sign/Verify mode.
Definition: mcuxClRsa_Types.h:184
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClRsa_KeyEntry_t::pKeyEntryData
uint8_t * pKeyEntryData
Pointer to buffer containing the key entry data in big-endian byte order.
Definition: mcuxClRsa_Types.h:130
+
mcuxClRsa_Key::pExp3
mcuxClRsa_KeyEntry_t * pExp3
Pointer to sixth key entry:
Definition: mcuxClRsa_Types.h:166
+
mcuxClRsa_Key::pMod2
mcuxClRsa_KeyEntry_t * pMod2
Pointer to second key entry:
Definition: mcuxClRsa_Types.h:153
+
mcuxClRsa_SignVerifyMode_t
struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t
Forward declaration of Sign/Verify mode struct.
Definition: mcuxClRsa_Types.h:179
+
mcuxClRsa_Key::pMod1
mcuxClRsa_KeyEntry_t * pMod1
Pointer to first key entry:
Definition: mcuxClRsa_Types.h:150
+
mcuxClRsa_Key::pExp1
mcuxClRsa_KeyEntry_t * pExp1
Pointer to fourth key entry:
Definition: mcuxClRsa_Types.h:159
+
mcuxClSession.h
Top-level include file for the mcuxClSession component.
+
mcuxClRsa_Key
struct mcuxClRsa_Key mcuxClRsa_Key
Structure type for Rsa key, specifying key type and key entries.
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxClRsa_KeyEntry_t
Structure type for Rsa key entries, specifying key entry length and data.
Definition: mcuxClRsa_Types.h:128
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClRsa_Status_Protected_t
mcuxClRsa_Status_t mcuxClRsa_Status_Protected_t
Deprecated type for RSA protected status codes.
Definition: mcuxClRsa_Types.h:120
+
mcuxClRsa_KeyEntry
mcuxClRsa_KeyEntry_t * mcuxClRsa_KeyEntry
Pointer type to Rsa key entries.
Definition: mcuxClRsa_Types.h:138
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00569.html b/components/els_pkc/doc/mcxn/html/a00569.html new file mode 100644 index 000000000..dfff8fa20 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00569.html @@ -0,0 +1,131 @@ + + + + + + + +MCUX CLNS: mcuxClSession.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+ +
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+
+ + +
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+ +
+
+
mcuxClSession.h File Reference
+
+
+ +

Top-level include file for the mcuxClSession component. +More...

+
#include <mcuxClConfig.h>
+#include <mcuxClSession_Types.h>
+#include <mcuxClSession_Functions.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the mcuxClSession component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00569_source.html b/components/els_pkc/doc/mcxn/html/a00569_source.html new file mode 100644 index 000000000..a90327930 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00569_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxClSession.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
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+
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+ +
+ +
+
+
mcuxClSession.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
35 #ifndef MCUXCLSESSION_H_
36 #define MCUXCLSESSION_H_
37 
38 #include <mcuxClConfig.h> // Exported features flags header
39 #include <mcuxClSession_Types.h>
40 #include <mcuxClSession_Functions.h>
41 
42 #endif /* MCUXCLSESSION_H_ */
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
mcuxClSession_Functions.h
Top-level API of the mcuxClSession component.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00572.html b/components/els_pkc/doc/mcxn/html/a00572.html new file mode 100644 index 000000000..dc0dca456 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00572.html @@ -0,0 +1,150 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Functions.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+Functions
+
+
mcuxClSession_Functions.h File Reference
+
+
+ +

Top-level API of the mcuxClSession component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxClSession_Types.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Functions

mcuxClSession_Status_t mcuxClSession_init (mcuxClSession_Handle_t pSession, uint32_t *const pCpuWaBuffer, uint32_t cpuWaLength, uint32_t *const pPkcWaBuffer, uint32_t pkcWaLength)
 Initialize a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_setRtf (mcuxClSession_Handle_t pSession, uint8_t *const pRtf, mcuxClSession_Rtf_t RtfOptions)
 Set the RTF option in a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_cleanup (mcuxClSession_Handle_t pSession)
 Clean up a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_destroy (mcuxClSession_Handle_t pSession)
 Destroy a Crypto Library session. More...
 
+

Detailed Description

+

Top-level API of the mcuxClSession component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00572.js b/components/els_pkc/doc/mcxn/html/a00572.js new file mode 100644 index 000000000..3c8510308 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00572.js @@ -0,0 +1,7 @@ +var a00572 = +[ + [ "mcuxClSession_init", "a00855.html#gaf1b8776b0d519136df17f6dd632442cf", null ], + [ "mcuxClSession_setRtf", "a00855.html#ga159bff529d405fd6da2930590a69ac06", null ], + [ "mcuxClSession_cleanup", "a00855.html#ga1ba3d2c6e561c86e1da8fcc0abfd046c", null ], + [ "mcuxClSession_destroy", "a00855.html#gaad324fd8f8eeefa29521c4297ac75fd2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00572_source.html b/components/els_pkc/doc/mcxn/html/a00572_source.html new file mode 100644 index 000000000..ed672d479 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00572_source.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Functions.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClSession_Functions.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLSESSION_FUNCTIONS_H_
20 #define MCUXCLSESSION_FUNCTIONS_H_
21 
22 #include <mcuxClCore_Platform.h>
23 #include <mcuxClCore_FunctionIdentifiers.h>
24 #include <mcuxCsslFlowProtection.h>
25 #include <mcuxClSession_Types.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 /**********************************************
32  * FUNCTIONS
33  **********************************************/
58 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_init)
59 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_init(
60  mcuxClSession_Handle_t pSession,
61  uint32_t * const pCpuWaBuffer,
62  uint32_t cpuWaLength,
63  uint32_t * const pPkcWaBuffer,
64  uint32_t pkcWaLength
65  /* TBD: sclRandom_Context_t * const rngCtx */
66 );
67 
77 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_setRtf)
78 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRtf(
79  mcuxClSession_Handle_t pSession,
80  uint8_t * const pRtf,
81  mcuxClSession_Rtf_t RtfOptions
82 );
83 
84 
85 
86 
87 
88 
89 
100 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_cleanup)
101 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_cleanup(
102  mcuxClSession_Handle_t pSession
103 );
104 
117 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_destroy)
118 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_destroy(
119  mcuxClSession_Handle_t pSession
120 );
121 
122 #ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM
123 
132 MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_setRandom)
133 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRandom(
134  mcuxClSession_Handle_t session,
135  mcuxClRandom_Mode_t randomMode,
136  mcuxClRandom_Context_t randomCtx
137 );
138 #endif // MCUXCL_FEATURE_SESSION_HAS_RANDOM
139  /* mcuxClSession_Functions */
143 
144 
145 #ifdef __cplusplus
146 } /* extern "C" */
147 #endif
148 
149 #endif /* MCUXCLSESSION_FUNCTIONS_H_ */
mcuxClRandom_Context_t
mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
Random context type.
Definition: mcuxClRandom_Types.h:70
+
mcuxClSession_Rtf_t
uint32_t mcuxClSession_Rtf_t
Type for mcuxClSession RTF configuration flags.
Definition: mcuxClSession_Types.h:88
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClSession_cleanup
mcuxClSession_Status_t mcuxClSession_cleanup(mcuxClSession_Handle_t pSession)
Clean up a Crypto Library session.
+
mcuxClSession_setRtf
mcuxClSession_Status_t mcuxClSession_setRtf(mcuxClSession_Handle_t pSession, uint8_t *const pRtf, mcuxClSession_Rtf_t RtfOptions)
Set the RTF option in a Crypto Library session.
+
mcuxClSession_Types.h
Type definitions for the mcuxClSession component.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxClSession_destroy
mcuxClSession_Status_t mcuxClSession_destroy(mcuxClSession_Handle_t pSession)
Destroy a Crypto Library session.
+
mcuxClRandom_Mode_t
const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
Random data generation mode/algorithm type.
Definition: mcuxClRandom_Types.h:93
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxClSession_Status_t
uint32_t mcuxClSession_Status_t
Type for mcuxClSession status codes.
Definition: mcuxClSession_Types.h:78
+
mcuxClSession_init
mcuxClSession_Status_t mcuxClSession_init(mcuxClSession_Handle_t pSession, uint32_t *const pCpuWaBuffer, uint32_t cpuWaLength, uint32_t *const pPkcWaBuffer, uint32_t pkcWaLength)
Initialize a Crypto Library session.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00575.html b/components/els_pkc/doc/mcxn/html/a00575.html new file mode 100644 index 000000000..bb46c3cde --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00575.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: mcuxClSession_MemoryConsumption.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
mcuxClSession_MemoryConsumption.h File Reference
+
+
+ +

Defines the memory consumption for the mcuxClSession component. +More...

+ +

Go to the source code of this file.

+

Detailed Description

+

Defines the memory consumption for the mcuxClSession component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00575_source.html b/components/els_pkc/doc/mcxn/html/a00575_source.html new file mode 100644 index 000000000..8d6c2dd1f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00575_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClSession_MemoryConsumption.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+
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+ +
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+
+ + +
+ +
+ +
+
+
mcuxClSession_MemoryConsumption.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLSESSION_MEMORYCONSUMPTION_H_
20 #define MCUXCLSESSION_MEMORYCONSUMPTION_H_
21 
22 
23 #endif /* MCUXCLSESSION_MEMORYCONSUMPTION_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00578.html b/components/els_pkc/doc/mcxn/html/a00578.html new file mode 100644 index 000000000..21678c745 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00578.html @@ -0,0 +1,193 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs
+
+
mcuxClSession_Types.h File Reference
+
+
+ +

Type definitions for the mcuxClSession component. +More...

+
#include <mcuxClCore_Platform.h>
+#include <mcuxClCore_FunctionIdentifiers.h>
+#include <mcuxCsslFlowProtection.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Data Structures

struct  mcuxClSession_WorkArea
 Type for mcuxClSession workareas flags. More...
 
struct  mcuxClSession_SecurityContext
 Type for mcuxClSession security context. More...
 
struct  mcuxClSession_Descriptor
 Type for mcuxClSession Descriptor. More...
 
+ + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLSESSION_STATUS_OK
 Session operation successful. More...
 
#define MCUXCLSESSION_STATUS_ERROR
 Error occurred during Session operation. More...
 
#define MCUXCLSESSION_STATUS_HW_UNAVAILABLE
 Required HW is unavailable. More...
 
#define MCUXCLSESSION_RTF_UPDATE_TRUE
 RTF will be updated. More...
 
#define MCUXCLSESSION_RTF_UPDATE_FALSE
 RTF will not be updated. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClSession_Status_t
 Type for mcuxClSession status codes. More...
 
typedef mcuxClSession_Status_t mcuxClSession_Status_Protected_t
 Deprecated type for mcuxClSession protected status codes. More...
 
typedef uint32_t mcuxClSession_Rtf_t
 Type for mcuxClSession RTF configuration flags. More...
 
typedef struct mcuxClSession_WorkArea mcuxClSession_WorkArea_t
 Type for mcuxClSession workareas flags. More...
 
typedef struct mcuxClSession_SecurityContext mcuxClSession_SecurityContext_t
 Type for mcuxClSession security context. More...
 
typedef uint32_t mcuxClSession_SecurityOptions_t
 Type for Session security options. More...
 
typedef struct mcuxClSession_Descriptor mcuxClSession_Descriptor_t
 Type for mcuxClSession Descriptor. More...
 
typedef mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
 Type for mcuxClSession Handle. More...
 
+

Detailed Description

+

Type definitions for the mcuxClSession component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00578.js b/components/els_pkc/doc/mcxn/html/a00578.js new file mode 100644 index 000000000..ac32fcfb9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00578.js @@ -0,0 +1,16 @@ +var a00578 = +[ + [ "MCUXCLSESSION_STATUS_OK", "a00857.html#ga3f63cf17e4f26ba5ee4d92152fca1eb6", null ], + [ "MCUXCLSESSION_STATUS_ERROR", "a00857.html#ga547425b7379de3ee1fb96c79140fd68e", null ], + [ "MCUXCLSESSION_STATUS_HW_UNAVAILABLE", "a00857.html#gaa3a0727f4c8a2658cb607d45cd28229e", null ], + [ "MCUXCLSESSION_RTF_UPDATE_TRUE", "a00858.html#ga17963249b8a091124c5442ca642a55d8", null ], + [ "MCUXCLSESSION_RTF_UPDATE_FALSE", "a00858.html#ga922a60abc33fb57bb5b4587324f2d73c", null ], + [ "mcuxClSession_Status_t", "a00859.html#ga9f2ec672d5a5fe92159f0e6159e04e4e", null ], + [ "mcuxClSession_Status_Protected_t", "a00859.html#ga09bbfe382aac167ec94e8e6e3d2b10f6", null ], + [ "mcuxClSession_Rtf_t", "a00859.html#gac635eeca4268dbd500e45806ee37f685", null ], + [ "mcuxClSession_WorkArea_t", "a00859.html#ga13a1a61b81f8b8bdc5272d33b44a2dac", null ], + [ "mcuxClSession_SecurityContext_t", "a00859.html#gac2866aae4d5a869b0fa55c82190d0c93", null ], + [ "mcuxClSession_SecurityOptions_t", "a00859.html#gabd24855c86970aaa97d3c6975a8ca53c", null ], + [ "mcuxClSession_Descriptor_t", "a00859.html#gafe6e209ab6b552af2011043383473f18", null ], + [ "mcuxClSession_Handle_t", "a00859.html#ga17fd337618b05459b4a343393e099b56", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00578_source.html b/components/els_pkc/doc/mcxn/html/a00578_source.html new file mode 100644 index 000000000..94a2a1ecc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00578_source.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Types.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxClSession_Types.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCLSESSION_TYPES_H_
20 #define MCUXCLSESSION_TYPES_H_
21 
22 #include <mcuxClCore_Platform.h>
23 #include <mcuxClCore_FunctionIdentifiers.h>
24 #include <mcuxCsslFlowProtection.h>
25 
26 #ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM
27 #include <mcuxClRandom_Types.h>
28 #endif /* MCUXCL_FEATURE_SESSION_HAS_RANDOM */
29 
30 /**********************************************
31  * CONSTANTS
32  **********************************************/
44 #define MCUXCLSESSION_STATUS_OK ((mcuxClSession_Status_t) 0x0EEE2E03u)
45 #define MCUXCLSESSION_STATUS_ERROR ((mcuxClSession_Status_t) 0x0EEE5330u)
46 #define MCUXCLSESSION_STATUS_HW_UNAVAILABLE ((mcuxClSession_Status_t) 0x0EEE5334u)
47 
53 #define MCUXCLSESSION_RTF_UPDATE_TRUE ((mcuxClSession_Rtf_t) 0xF0F00F0Fu )
54 #define MCUXCLSESSION_RTF_UPDATE_FALSE ((mcuxClSession_Rtf_t) 0x0F0F0F0Fu )
55 
63 /* mcuxClSession_Constants */
64 
65 /**********************************************
66  * TYPEDEFS
67  **********************************************/
78 typedef uint32_t mcuxClSession_Status_t;
79 
83 typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_Status_Protected_t;
84 
88 typedef uint32_t mcuxClSession_Rtf_t;
89 
93 typedef struct mcuxClSession_WorkArea
94 {
95  uint32_t * buffer;
96  uint32_t size;
97  uint32_t used;
98  uint32_t dirty;
99 } mcuxClSession_WorkArea_t;
100 
104 typedef struct mcuxClSession_SecurityContext
105 {
106  uint32_t securityCounter;
107 } mcuxClSession_SecurityContext_t;
108 
112 typedef uint32_t mcuxClSession_SecurityOptions_t;
113 
114 
115 
119 typedef struct mcuxClSession_Descriptor
120 {
121  mcuxClSession_WorkArea_t cpuWa;
122  mcuxClSession_WorkArea_t pkcWa;
123 #ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM
124  mcuxClRandom_Config_t randomCfg;
125 #endif /* MCUXCL_FEATURE_SESSION_HAS_RANDOM */
126  mcuxClSession_Rtf_t rtf;
127  uint8_t *pRtf;
128 } mcuxClSession_Descriptor_t;
129 
133 typedef mcuxClSession_Descriptor_t * const mcuxClSession_Handle_t;
134 
135  /* mcuxClSession_Types */
139 
140 #endif /* MCUXCLSESSION_TYPES_H_ */
mcuxClRandom_Types.h
Type definitions of mcuxClRandom component.
+
mcuxClSession_Rtf_t
uint32_t mcuxClSession_Rtf_t
Type for mcuxClSession RTF configuration flags.
Definition: mcuxClSession_Types.h:88
+
mcuxClSession_Descriptor::cpuWa
mcuxClSession_WorkArea_t cpuWa
Workarea for the CPU.
Definition: mcuxClSession_Types.h:121
+
mcuxClSession_Descriptor
Type for mcuxClSession Descriptor.
Definition: mcuxClSession_Types.h:119
+
mcuxClSession_Descriptor::pkcWa
mcuxClSession_WorkArea_t pkcWa
Workarea for the PKC.
Definition: mcuxClSession_Types.h:122
+
mcuxClSession_SecurityOptions_t
uint32_t mcuxClSession_SecurityOptions_t
Type for Session security options.
Definition: mcuxClSession_Types.h:112
+
mcuxClSession_Status_Protected_t
mcuxClSession_Status_t mcuxClSession_Status_Protected_t
Deprecated type for mcuxClSession protected status codes.
Definition: mcuxClSession_Types.h:83
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxClSession_SecurityContext::securityCounter
uint32_t securityCounter
Security counter.
Definition: mcuxClSession_Types.h:106
+
mcuxClSession_SecurityContext_t
struct mcuxClSession_SecurityContext mcuxClSession_SecurityContext_t
Type for mcuxClSession security context.
+
mcuxClSession_WorkArea::dirty
uint32_t dirty
Maximum used portion of the workarea buffer in words (uint32_t)
Definition: mcuxClSession_Types.h:98
+
mcuxClSession_Descriptor::rtf
mcuxClSession_Rtf_t rtf
Configuration of the RTF.
Definition: mcuxClSession_Types.h:126
+
mcuxClSession_WorkArea::size
uint32_t size
Size of the workarea buffer in words (uint32_t)
Definition: mcuxClSession_Types.h:96
+
mcuxClSession_WorkArea_t
struct mcuxClSession_WorkArea mcuxClSession_WorkArea_t
Type for mcuxClSession workareas flags.
+
mcuxClSession_SecurityContext
Type for mcuxClSession security context.
Definition: mcuxClSession_Types.h:104
+
mcuxClSession_WorkArea::buffer
uint32_t * buffer
Pointer to the starting address of the workarea buffer.
Definition: mcuxClSession_Types.h:95
+
mcuxClSession_WorkArea::used
uint32_t used
Used portion of the workarea buffer in words (uint32_t)
Definition: mcuxClSession_Types.h:97
+
mcuxClSession_Handle_t
mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
Type for mcuxClSession Handle.
Definition: mcuxClSession_Types.h:133
+
mcuxClCore_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
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mcuxClSession_Status_t
uint32_t mcuxClSession_Status_t
Type for mcuxClSession status codes.
Definition: mcuxClSession_Types.h:78
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mcuxClSession_Descriptor_t
struct mcuxClSession_Descriptor mcuxClSession_Descriptor_t
Type for mcuxClSession Descriptor.
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mcuxClSession_WorkArea
Type for mcuxClSession workareas flags.
Definition: mcuxClSession_Types.h:93
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mcuxClRandom_Config
Random config structure.
Definition: mcuxClRandom_Types.h:100
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslAnalysis.h
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1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2022-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUX_CSSL_ANALYSIS_H_
15 #define MCUX_CSSL_ANALYSIS_H_
16 
17 #define MCUX_CSSL_ANALYSIS_STR(a) #a
18 #define MCUX_CSSL_ANALYSIS_EMPTY()
19 #define MCUX_CSSL_ANALYSIS_DEFER(id) id MCUX_CSSL_ANALYSIS_EMPTY()
20 #define MCUX_CSSL_ANALYSIS_EXPAND(...) __VA_ARGS__
21 
22 #define MCUX_CSSL_ANALYSIS_PRAGMA(x) _Pragma(#x)
23 
24 /* Compiler defines TODO: decide proper placement for those */
25 #if defined ( __CC_ARM )
26 /* Arm Compiler 4/5 */
27 #define MCUX_CSSL_COMPILER_ARMCC
28 #define MCUX_CSSL_COMPILER_ARM_COMPILER
29 
30 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
31 /* Arm Compiler 6.6 LTM (armclang) */
32 #define MCUX_CSSL_COMPILER_ARMCLANG_LTM
33 #define MCUX_CSSL_COMPILER_ARM_COMPILER
34 
35 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
36 /* Arm Compiler above 6.10.1 (armclang) */
37 #define MCUX_CSSL_COMPILER_ARMCLANG
38 #define MCUX_CSSL_COMPILER_ARM_COMPILER
39 
40 #elif defined (_clang_)
41 #define MCUX_CSSL_COMPILER_ARM_COMPILER /* i.e. Version 6.01 build 0019 */
42 #endif // defined ( __CC_ARM )
43 
44 /* Example of common patterns, with either just predefined rationale, or a combination of discards. */
45 #define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_READ() \
46  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Read from a HW peripheral")
47 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_READ() \
48  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE()
49 
50 #define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_WRITE() \
51  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Write to a HW peripheral")
52  /*MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_TO_OBJECT("Write to a HW peripheral")*/
53 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_WRITE() \
54  /*MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_TO_OBJECT()*/ \
55  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE()
56 
57 #define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_API_DECLARATIONS() \
58  MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user, it is declared but never referenced. ")
59 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_API_DECLARATIONS() \
60  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED()
61 
62 #define MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() \
63  MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER("Identifiers longer than 31 characters are allowed for more descriptive naming")
64 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() \
65  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER()
66 
67 #define MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() \
68  MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("explicit pointer casts reinterpreting opaque types of workarea-like buffer objects are allowed.")
69 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() \
70  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY()
71 /* Rule 11.3: applies to casts between ctx structs
72 * e.g. cast from Aead_Context_t to more specific type AeadModes_Context_t
73 */
74 #define MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() \
75  MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Cast to a more specific type is allowed")
76 #define MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() \
77  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY()
78 
79 #define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_HEADER() \
80  MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION("External header outside our control") \
81  MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE("External header outside our control") \
82  MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER("External header outside our control") \
83  MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY("External header outside our control")
84 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_HEADER() \
85  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \
86  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \
87  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \
88  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION()
89 
90 #define MCUX_CSSL_ANALYSIS_START_PATTERN_OBJ_SIZES() \
91  MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE("Variables used to determine object sizes") \
92  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("Variables used to determine object sizes")
93 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_OBJ_SIZES() \
94  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \
95  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE()
96 
97 #define MCUX_CSSL_ANALYSIS_START_PATTERN_FUP() \
98  MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("External declarations are generated by the FUP processing tool")
99 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP() \
100  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION()
101 
102 #define MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
103  MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for security counter variables per design")
104 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() \
105  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
106 
107 #define MCUX_CSSL_ANALYSIS_START_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \
108  MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED("Return instead of break statement as terminator is allowed")
109 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \
110  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED()
111 
112 #define MCUX_CSSL_ANALYSIS_START_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \
113  MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("Invariant expression is allowed in workarea calculation macros")
114 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \
115  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT()
116 
117 #define MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \
118  MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS("Address in SFR is for internal use only and does not escape")
119 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \
120  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS()
121 
122 
123 #define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_INTEGER_OVERFLOW() \
124  MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for DI variables per design")
125 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_INTEGER_OVERFLOW() \
126  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW()
127 
128 #define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_CAST_POINTERS() \
129  MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast pointer to integer for DI record/expunge") \
130  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_6, "Typecast pointer (void *) to integer for DI record/expunge")
131 #define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_CAST_POINTERS() \
132  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_6) \
133  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
134 
135 /* Example of basic violation suppression */
136 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DEAD_CODE(rationale) \
137  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_1, rationale)
138 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DEAD_CODE() \
139  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_1)
140 
141 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS(rationale) \
142  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_3_1, rationale)
143 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() \
144  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_3_1)
145 
146 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING(rationale) \
147  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \
148  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP36_C, rationale) \
149  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
150 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() \
151  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \
152  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP36_C) \
153  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
154 
155 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE(rationale) \
156  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \
157  MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \
158  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale)
159 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE() \
160  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \
161  MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \
162  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual)
163 
164 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_OUT_OF_BOUNDS_ACCESS(rationale) \
165  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_1, rationale)
166 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OUT_OF_BOUNDS_ACCESS() \
167  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_1) \
168 
169 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST(rationale) \
170  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \
171  MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \
172  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale)
173 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST() \
174  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \
175  MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \
176  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual)
177 
178 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER(rationale) \
179  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale)
180 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() \
181  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8)
182 
183 
184 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT(rationale) \
185  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_9, rationale)
186 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() \
187  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_9)
188 
189 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES(rationale) \
190  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale)
191 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() \
192  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
193 
194 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY(rationale) \
195  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \
196  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
197 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() \
198  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \
199  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3)
200 
201 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ARRAY_OUT_OF_BOUNDS(rationale) \
202  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_ARR30_C, rationale)
203 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ARRAY_OUT_OF_BOUNDS() \
204  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_ARR30_C)
205 
206 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale) \
207  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, rationale) \
208  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT36_C, rationale) \
209  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_MSC15_C, rationale)
210 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() \
211  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_MSC15_C) \
212  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT36_C) \
213  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4)
214 
215 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER(rationale) \
216  MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale)
217 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \
218  MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER()
219 
220 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER(rationale) \
221  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_1, rationale) \
222  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_4, rationale)
223 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER() \
224  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_1) \
225  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_4)
226 
227 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_STRUCT(rationale) \
228  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_1, rationale)
229 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_STRUCT() \
230  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_1)
231 
232 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED(rationale) \
233  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_2, rationale)
234 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() \
235  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_2)
236 
237 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW(rationale) \
238  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(INTEGER_OVERFLOW, rationale) \
239  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \
240  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale) \
241  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_12_4, rationale)
242 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() \
243  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_12_4) \
244  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \
245  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C) \
246  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(INTEGER_OVERFLOW)
247 
248 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_WRAP(rationale) \
249  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \
250  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale)
251 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_WRAP() \
252  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \
253  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C)
254 
255 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_INCOMPATIBLE(rationale) \
256  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale)
257 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_INCOMPATIBLE() \
258  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C)
259 
260 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED(rationale) \
261  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_1, rationale) \
262  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_3, rationale) \
263  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_6, rationale)
264 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED() \
265  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_1) \
266  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_3) \
267  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_6)
268 
269 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT(rationale) \
270  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, rationale)
271 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \
272  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3)
273 
274 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS(rationale) \
275  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_6, rationale)
276 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS() \
277  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_6)
278 
279 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \
280  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "Conditional expression does have a boolean type.")
281 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \
282  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4)
283 
284 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION(rationale) \
285  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wc11-extensions, rationale)
286 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION() \
287  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wc11-extensions)
288 
289 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE(rationale) \
290  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wundef, rationale)
291 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \
292  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wundef)
293 
294 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_IDENTIFIER(rationale) \
295  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-identifier, rationale)
296 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_IDENTIFIER() \
297  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-identifier)
298 
299 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER(rationale) \
300  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-macro-identifier, rationale)
301 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \
302  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-macro-identifier)
303 
304 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION(rationale) \
305  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wmissing-variable-declarations, rationale) \
306  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_4, rationale)
307 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \
308  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_4) \
309  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wmissing-variable-declarations)
310 
311 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION(rationale) \
312  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_8, rationale)
313 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION() \
314  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_8)
315 
316 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE(rationale) \
317  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wunused-variable, rationale)
318 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE() \
319  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wunused-variable)
320 
321 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY(rationale) \
322  MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wpadded, rationale)
323 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \
324  MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wpadded)
325 
326 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS(rationale) \
327  MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(-Warray-bounds, rationale)
328 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() \
329  MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(-Warray-bounds)
330 
331 #define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TAINTED_EXPRESSION(rationale) \
332  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Directive_4_14, rationale)
333 #define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TAINTED_EXPRESSION() \
334  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Directive_4_14)
335 
336 /* Tool specific handling: Coverity checkers */
337 #if defined(__COVERITY__)
338 
339 #define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale) \
340  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block deviate checker_identifier rationale))
341 #define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier) \
342  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier))
343 
344 #define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale) \
345  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block fp checker_identifier rationale))
346 #define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier) \
347  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier))
348 
349 #else
350 #define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale)
351 #define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier)
352 
353 #define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale)
354 #define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier)
355 #endif
356 
357 /* Tool specific handling: Clang warnings */
358 #if defined(__clang__)
359 #define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) \
360  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \
361  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
362 #define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier) \
363  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop))
364 #else
365 #define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale)
366 #define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier)
367 #endif
368 
369 /* Tool specific handling: GHS warnings */
370 #if defined(__ghs__)
371 #define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale) \
372  _Pragma("ghs nowarning " ## warning_identifier)
373 #define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier) \
374  _Pragma("ghs endnowarning")
375 #else
376 #define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale)
377 #define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier)
378 #endif
379 
380 /* Tool specific handling: GCC warnings */
381 #if defined(__GNUC__)
382 #define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale) \
383  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic push)) \
384  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
385 #define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier) \
386  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic pop))
387 #else
388 #define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale)
389 #define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier)
390 #endif
391 
392 /* Arm Compiler 4/5 */
393 #if defined(MCUX_CSSL_COMPILER_ARMCC)
394 #define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale) \
395  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(push)) \
396  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(diag_suppress MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
397 #define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier) \
398  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(pop))
399 #else
400 #define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale)
401 #define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier)
402 #endif
403 
404 /* Arm Compiler 6 / Arm Compiler for Embedded 6 */
405 #if defined(MCUX_CSSL_COMPILER_ARMCLANG) || defined(MCUX_CSSL_COMPILER_ARMCLANG_LTM)
406 #define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) \
407  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \
408  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier)))
409 #define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier) \
410  MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop))
411 #else
412 #define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale)
413 #define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier)
414 #endif
415 
416 #endif /* MCUX_CSSL_ANALYSIS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00584.html b/components/els_pkc/doc/mcxn/html/a00584.html new file mode 100644 index 000000000..ee17f7783 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00584.html @@ -0,0 +1,326 @@ + + + + + + + +MCUX CLNS: mcuxCsslCPreProcessor.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslCPreProcessor.h File Reference
+
+
+ +

The default implementation is based on standard C preprocessor functionality. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUX_CSSL_CPP_STR(a)
 
+#define MCUX_CSSL_CPP_ADD(a)
 
+#define MCUX_CSSL_CPP_CAT_IMPL(a, b)
 
+#define MCUX_CSSL_CPP_CAT(a, b)
 
+#define MCUX_CSSL_CPP_CAT3(a, b, c)
 
+#define MCUX_CSSL_CPP_CAT4(a, b, c, d)
 
+#define MCUX_CSSL_CPP_CAT6(a, b, c, d, e, f)
 
+#define MCUX_CSSL_CPP_SEQUENCE_32TO0()
 
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0()
 
+#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0()
 
+#define MCUX_CSSL_CPP_ARG_N(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, N, ...)
 
+#define MCUX_CSSL_CPP_ARGCOUNT_IMPL(...)
 
+#define MCUX_CSSL_CPP_ARGCOUNT(...)
 
+#define MCUX_CSSL_CPP_ARGCOUNT_2N(...)
 
+#define MCUX_CSSL_CPP_ARGCOUNT_3N(...)
 
+#define MCUX_CSSL_CPP_OVERLOADED_IMPL(name, n)
 
+#define MCUX_CSSL_CPP_OVERLOADED(name, ...)
 
+#define MCUX_CSSL_CPP_OVERLOADED1(name, ...)
 
+#define MCUX_CSSL_CPP_OVERLOADED2(name, ...)
 
+#define MCUX_CSSL_CPP_OVERLOADED3(name, ...)
 
+#define MCUX_CSSL_CPP_MAP(__macro, ...)
 
+#define MCUX_CSSL_CPP_EVAL(...)
 
+#define MCUX_CSSL_CPP_EVAL1024(...)
 
+#define MCUX_CSSL_CPP_EVAL512(...)
 
+#define MCUX_CSSL_CPP_EVAL256(...)
 
+#define MCUX_CSSL_CPP_EVAL128(...)
 
+#define MCUX_CSSL_CPP_EVAL64(...)
 
+#define MCUX_CSSL_CPP_EVAL32(...)
 
+#define MCUX_CSSL_CPP_EVAL16(...)
 
+#define MCUX_CSSL_CPP_EVAL8(...)
 
+#define MCUX_CSSL_CPP_EVAL4(...)
 
+#define MCUX_CSSL_CPP_EVAL2(...)
 
+#define MCUX_CSSL_CPP_EVAL1(...)
 
+#define MCUX_CSSL_CPP_MAP_IMPL(__macro, ...)
 
+#define MCUX_CSSL_CPP_MAP_IMPL_()
 
+#define MCUX_CSSL_CPP_FIRST(a, ...)
 
+#define MCUX_CSSL_CPP_SECOND(a, b, ...)
 
+#define MCUX_CSSL_CPP_THIRD(a, b, c, ...)
 
+#define MCUX_CSSL_CPP_FOURTH(a, b, c, d, ...)
 
+#define MCUX_CSSL_CPP_NEXT(...)
 
+#define MCUX_CSSL_CPP_NEXT_()
 
+#define MCUX_CSSL_CPP_NEXT__(x, ...)
 
+#define MCUX_CSSL_CPP_HAS_MORE_ARGS(...)
 
+#define MCUX_CSSL_CPP_HAS_ONE_ARG(...)
 
+#define MCUX_CSSL_CPP_HAS_TWO_ARGS(...)
 
+#define MCUX_CSSL_CPP_HAS_THREE_ARGS(...)
 
+#define MCUX_CSSL_CPP_IS_MARKER(...)
 
+#define MCUX_CSSL_CPP_MARKER()
 
+#define MCUX_CSSL_CPP_BOOL(x)
 
+#define MCUX_CSSL_CPP_NOT(x)
 
+#define MCUX_CSSL_CPP_NOT_BOOL_0
 
+#define MCUX_CSSL_CPP_IF(condition)
 
+#define MCUX_CSSL_CPP_IF_(condition)
 
+#define MCUX_CSSL_CPP_IF_BOOL_0(...)
 
+#define MCUX_CSSL_CPP_IF_BOOL_1(...)
 
+#define MCUX_CSSL_CPP_IF_ELSE(condition)
 
+#define MCUX_CSSL_CPP_IF_ELSE_IMPL(condition)
 
+#define MCUX_CSSL_CPP_IFE_BOOL_0(...)
 
+#define MCUX_CSSL_CPP_IFE_BOOL_0_ELSE(...)
 
+#define MCUX_CSSL_CPP_IFE_BOOL_1(...)
 
+#define MCUX_CSSL_CPP_IFE_BOOL_1_ELSE(...)
 
+#define MCUX_CSSL_CPP_EMPTY()
 
+#define MCUX_CSSL_CPP_DEFER1(macro)
 
+#define MCUX_CSSL_CPP_DEFER2(macro)
 
+

Detailed Description

+

The default implementation is based on standard C preprocessor functionality.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00584.js b/components/els_pkc/doc/mcxn/html/a00584.js new file mode 100644 index 000000000..89def2672 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00584.js @@ -0,0 +1,67 @@ +var a00584 = +[ + [ "MCUX_CSSL_CPP_STR", "a00584.html#a0213e8d1a575acd58777b509d8fddc04", null ], + [ "MCUX_CSSL_CPP_ADD", "a00584.html#a9db36bbb5b7ff261403f89377520731a", null ], + [ "MCUX_CSSL_CPP_CAT_IMPL", "a00584.html#a42e265c7d656f0d40494ecf8ce52084f", null ], + [ "MCUX_CSSL_CPP_CAT", "a00584.html#a4c9cb13da1e5971a5f499b6cd1cfb6b2", null ], + [ "MCUX_CSSL_CPP_CAT3", "a00584.html#aaf29e16bb9757a9504e4c0ee9e14de74", null ], + [ "MCUX_CSSL_CPP_CAT4", "a00584.html#aeadf3ee9f17b1f124e99d4472f58c07d", null ], + [ "MCUX_CSSL_CPP_CAT6", "a00584.html#aa59cf21060354e1cd10fa6eec4460009", null ], + [ "MCUX_CSSL_CPP_SEQUENCE_32TO0", "a00584.html#a9860187a5033174e092d8432a8c573e0", null ], + [ "MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0", "a00584.html#a6bb5b9ae101dd3c05f0c574bfd42ede1", null ], + [ "MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0", "a00584.html#ad831654b9d2f022003390fa0d5fe07e0", null ], + [ "MCUX_CSSL_CPP_ARG_N", "a00584.html#ad54c795ba13a9edcff5fd090ae0bfecc", null ], + [ "MCUX_CSSL_CPP_ARGCOUNT_IMPL", "a00584.html#aa554ae4d6144dbad01e3f5fabc85ff3d", null ], + [ "MCUX_CSSL_CPP_ARGCOUNT", "a00584.html#ad4a0affd323b09487c9f5697931752ff", null ], + [ "MCUX_CSSL_CPP_ARGCOUNT_2N", "a00584.html#a2498f2d757cd656f8d7279005431ed24", null ], + [ "MCUX_CSSL_CPP_ARGCOUNT_3N", "a00584.html#a5efec784320d074d1e2bb5dcefd6f3e0", null ], + [ "MCUX_CSSL_CPP_OVERLOADED_IMPL", "a00584.html#a1445c9090608d2b87aa3b06add415667", null ], + [ "MCUX_CSSL_CPP_OVERLOADED", "a00584.html#ad98010e26571ff83d966269b2c231694", null ], + [ "MCUX_CSSL_CPP_OVERLOADED1", "a00584.html#aa15b14a8de4c84de61da64ed9d195065", null ], + [ "MCUX_CSSL_CPP_OVERLOADED2", "a00584.html#ae1f44f293a3ea3bd164b520e8aa69ccf", null ], + [ "MCUX_CSSL_CPP_OVERLOADED3", "a00584.html#aeef537ba43080ab8ffbda202b13a05e1", null ], + [ "MCUX_CSSL_CPP_MAP", "a00584.html#a2bce80a07a5a57f83695e0050c63b4df", null ], + [ "MCUX_CSSL_CPP_EVAL", "a00584.html#ae7a50db23c0377417f7986b211cb2aff", null ], + [ "MCUX_CSSL_CPP_EVAL1024", "a00584.html#a097e5b5bb7a45dd32d324fc4da3902b4", null ], + [ "MCUX_CSSL_CPP_EVAL512", "a00584.html#a1f61fd0ec2f72e0479ce65d5aee7e6a7", null ], + [ "MCUX_CSSL_CPP_EVAL256", "a00584.html#a2222be97e96fa2bc7aaa13e0482e7f09", null ], + [ "MCUX_CSSL_CPP_EVAL128", "a00584.html#a9111e40668fd08585a60e26068e4248a", null ], + [ "MCUX_CSSL_CPP_EVAL64", "a00584.html#ac6db6b4bfab1ce131a184efba4f5f5e1", null ], + [ "MCUX_CSSL_CPP_EVAL32", "a00584.html#ac2666230a0eafbf0a4cc2ab11b720ec7", null ], + [ "MCUX_CSSL_CPP_EVAL16", "a00584.html#a838e92fe704842b56d054f38b086211f", null ], + [ "MCUX_CSSL_CPP_EVAL8", "a00584.html#aab558a37fb914ce8ef2689ac39157510", null ], + [ "MCUX_CSSL_CPP_EVAL4", "a00584.html#ad888df9bd9085c7fa99d0f28f6ede602", null ], + [ "MCUX_CSSL_CPP_EVAL2", "a00584.html#a7778918f379e4b6e853081caa2a65641", null ], + [ "MCUX_CSSL_CPP_EVAL1", "a00584.html#acc8b865a62f12ff6a38c3b9b0c44130f", null ], + [ "MCUX_CSSL_CPP_MAP_IMPL", "a00584.html#ab41cf01262864a8aef2416175eec8358", null ], + [ "MCUX_CSSL_CPP_MAP_IMPL_", "a00584.html#a4d5d0f5270ace7e0e72625ba4d7dee8e", null ], + [ "MCUX_CSSL_CPP_FIRST", "a00584.html#a86494d2e402ff8f41684ee0f467ff6b2", null ], + [ "MCUX_CSSL_CPP_SECOND", "a00584.html#a6313691748cc2e7bcea3add8d9d23318", null ], + [ "MCUX_CSSL_CPP_THIRD", "a00584.html#a5a3d65c2c8c9caeeff088264aa257384", null ], + [ "MCUX_CSSL_CPP_FOURTH", "a00584.html#a4f7ca972630be7e56055ee8ae30fb501", null ], + [ "MCUX_CSSL_CPP_NEXT", "a00584.html#ab53fcc654090f0756c50ec0b2dacebd4", null ], + [ "MCUX_CSSL_CPP_NEXT_", "a00584.html#a89c3115c37ad9c29b1dec6b65d25799c", null ], + [ "MCUX_CSSL_CPP_NEXT__", "a00584.html#ae7b74733ce05b4fc5e54665ddeb13fbd", null ], + [ "MCUX_CSSL_CPP_HAS_MORE_ARGS", "a00584.html#a93ba7d67bf2d037072e995f2500dee2d", null ], + [ "MCUX_CSSL_CPP_HAS_ONE_ARG", "a00584.html#aa4867806fd41a62be88fa85a17b0f724", null ], + [ "MCUX_CSSL_CPP_HAS_TWO_ARGS", "a00584.html#a2c12dd284c632cd09ab1a80299b5c027", null ], + [ "MCUX_CSSL_CPP_HAS_THREE_ARGS", "a00584.html#a70359ac985775379acf48566d62c9c16", null ], + [ "MCUX_CSSL_CPP_IS_MARKER", "a00584.html#a1473968f98b13b52c221269504c3a960", null ], + [ "MCUX_CSSL_CPP_MARKER", "a00584.html#a87522ae1205332bdeeacfaf55a33f7b8", null ], + [ "MCUX_CSSL_CPP_BOOL", "a00584.html#a8da08e9d14819e99ee7b6b7a2bb90197", null ], + [ "MCUX_CSSL_CPP_NOT", "a00584.html#acabd7fb4d62961dcacb2c9faa1273748", null ], + [ "MCUX_CSSL_CPP_NOT_BOOL_0", "a00584.html#ae42f7b703e240e57ffdd65255d0af170", null ], + [ "MCUX_CSSL_CPP_IF", "a00584.html#aef996ff2207e156799c7f8eacd58b197", null ], + [ "MCUX_CSSL_CPP_IF_", "a00584.html#a35ed63e9f8ed083f0c273f8dd4661006", null ], + [ "MCUX_CSSL_CPP_IF_BOOL_0", "a00584.html#af89ec57641bd5425d156f1bada689607", null ], + [ "MCUX_CSSL_CPP_IF_BOOL_1", "a00584.html#a9da3e8ee0cf36b73e5703d986b6b135a", null ], + [ "MCUX_CSSL_CPP_IF_ELSE", "a00584.html#a06a4cd1dbe6c2c697e00d7024580f31f", null ], + [ "MCUX_CSSL_CPP_IF_ELSE_IMPL", "a00584.html#a4b6888e813d96560eaba93fde97f7733", null ], + [ "MCUX_CSSL_CPP_IFE_BOOL_0", "a00584.html#a85e13d973cc1069024f304d248f55589", null ], + [ "MCUX_CSSL_CPP_IFE_BOOL_0_ELSE", "a00584.html#a17c691bd33b1c7f8066a1a984ea06f9d", null ], + [ "MCUX_CSSL_CPP_IFE_BOOL_1", "a00584.html#a5f98f3afb725de9118db61162c2dfd85", null ], + [ "MCUX_CSSL_CPP_IFE_BOOL_1_ELSE", "a00584.html#a128df47cacd988995d08c7fb9b5b2ea5", null ], + [ "MCUX_CSSL_CPP_EMPTY", "a00584.html#a44dbbd48edeb66f4b3c6fbc20424f470", null ], + [ "MCUX_CSSL_CPP_DEFER1", "a00584.html#ad475cd85d6abbc47d7ae7a2dc8ca1671", null ], + [ "MCUX_CSSL_CPP_DEFER2", "a00584.html#a2667b3ce8585bb3adb3c58e7e5c0ce1b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00584_source.html b/components/els_pkc/doc/mcxn/html/a00584_source.html new file mode 100644 index 000000000..efd4c2dd2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00584_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslCPreProcessor.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslCPreProcessor.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2019-2020 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
14 #ifndef MCUX_CSSL_C_PRE_PROCESSOR_H_
15 #define MCUX_CSSL_C_PRE_PROCESSOR_H_
16 
23 #define MCUX_CSSL_CPP_STR(a) #a
24 
25 #define MCUX_CSSL_CPP_ADD(a) + (a)
26 
27 #define MCUX_CSSL_CPP_CAT_IMPL(a, b) a##b
28 
29 #define MCUX_CSSL_CPP_CAT(a, b) \
30  MCUX_CSSL_CPP_CAT_IMPL(a, b)
31 
32 #define MCUX_CSSL_CPP_CAT3(a, b, c) \
33  MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), c)
34 
35 #define MCUX_CSSL_CPP_CAT4(a, b, c, d) \
36  MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), MCUX_CSSL_CPP_CAT(c, d))
37 
38 #define MCUX_CSSL_CPP_CAT6(a, b, c, d, e, f) \
39  MCUX_CSSL_CPP_CAT3( \
40  MCUX_CSSL_CPP_CAT(a, b), \
41  MCUX_CSSL_CPP_CAT(c, d), \
42  MCUX_CSSL_CPP_CAT(e, f))
43 
44 #define MCUX_CSSL_CPP_SEQUENCE_32TO0() \
45  32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, \
46  16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
47 
48 #define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0() \
49  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
50  n, n, n, n, n, n, n, n, n, n, n, n, n, 3, 2, 1, 0
51 
52 #define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0() \
53  n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \
54  n, n, n, n, n, n, n, n, n, n, n, n, n, n, 2, 1, 0
55 
56 #define MCUX_CSSL_CPP_ARG_N( \
57  _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, \
58  _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, \
59  N, ...) \
60  N
61 
62 #define MCUX_CSSL_CPP_ARGCOUNT_IMPL(...) \
63  MCUX_CSSL_CPP_ARG_N(__VA_ARGS__)
64 
65 #define MCUX_CSSL_CPP_ARGCOUNT(...) \
66  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_32TO0())
67 
68 #define MCUX_CSSL_CPP_ARGCOUNT_2N(...) \
69  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0())
70 
71 #define MCUX_CSSL_CPP_ARGCOUNT_3N(...) \
72  MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0())
73 
74 #define MCUX_CSSL_CPP_OVERLOADED_IMPL(name, n) MCUX_CSSL_CPP_CAT_IMPL(name, n)
75 
76 #define MCUX_CSSL_CPP_OVERLOADED(name, ...) \
77  MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_OVERLOADED_IMPL)()(name, MCUX_CSSL_CPP_ARGCOUNT(__VA_ARGS__))
78 
79 #define MCUX_CSSL_CPP_OVERLOADED1(name, ...) \
80  MCUX_CSSL_CPP_IF_ELSE(MCUX_CSSL_CPP_HAS_ONE_ARG(__VA_ARGS__))( \
81  /* If only one arg, use the 1 version */ \
82  MCUX_CSSL_CPP_CAT(name,1)(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure extra argument: */ 0)) \
83  )( \
84  /* Otherwise the n version */ \
85  MCUX_CSSL_CPP_CAT(name,n)(__VA_ARGS__) \
86  )
87 
88 #define MCUX_CSSL_CPP_OVERLOADED2(name, ...) \
89  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_2N(__VA_ARGS__))(__VA_ARGS__)
90 
91 #define MCUX_CSSL_CPP_OVERLOADED3(name, ...) \
92  MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_3N(__VA_ARGS__))(__VA_ARGS__)
93 
94 
95 
96 /*****************************************************************************
97  * Helper macros *
98  *****************************************************************************/
99 
100 /* Apply a macro to all arguments */
101 #define MCUX_CSSL_CPP_MAP(__macro, ...) \
102  MCUX_CSSL_CPP_EVAL(MCUX_CSSL_CPP_MAP_IMPL(__macro, __VA_ARGS__))
103 
104 /* Evaluate a complex macro (which needs multiple expansions to be processed) */
105 #define MCUX_CSSL_CPP_EVAL(...) MCUX_CSSL_CPP_EVAL1024(__VA_ARGS__)
106 #define MCUX_CSSL_CPP_EVAL1024(...) MCUX_CSSL_CPP_EVAL512(MCUX_CSSL_CPP_EVAL512(__VA_ARGS__))
107 #define MCUX_CSSL_CPP_EVAL512(...) MCUX_CSSL_CPP_EVAL256(MCUX_CSSL_CPP_EVAL256(__VA_ARGS__))
108 #define MCUX_CSSL_CPP_EVAL256(...) MCUX_CSSL_CPP_EVAL128(MCUX_CSSL_CPP_EVAL128(__VA_ARGS__))
109 #define MCUX_CSSL_CPP_EVAL128(...) MCUX_CSSL_CPP_EVAL64( MCUX_CSSL_CPP_EVAL64( __VA_ARGS__))
110 #define MCUX_CSSL_CPP_EVAL64(...) MCUX_CSSL_CPP_EVAL32( MCUX_CSSL_CPP_EVAL32( __VA_ARGS__))
111 #define MCUX_CSSL_CPP_EVAL32(...) MCUX_CSSL_CPP_EVAL16( MCUX_CSSL_CPP_EVAL16( __VA_ARGS__))
112 #define MCUX_CSSL_CPP_EVAL16(...) MCUX_CSSL_CPP_EVAL8( MCUX_CSSL_CPP_EVAL8( __VA_ARGS__))
113 #define MCUX_CSSL_CPP_EVAL8(...) MCUX_CSSL_CPP_EVAL4( MCUX_CSSL_CPP_EVAL4( __VA_ARGS__))
114 #define MCUX_CSSL_CPP_EVAL4(...) MCUX_CSSL_CPP_EVAL2( MCUX_CSSL_CPP_EVAL2( __VA_ARGS__))
115 #define MCUX_CSSL_CPP_EVAL2(...) MCUX_CSSL_CPP_EVAL1( MCUX_CSSL_CPP_EVAL1( __VA_ARGS__))
116 #define MCUX_CSSL_CPP_EVAL1(...) __VA_ARGS__
117 
118 /* Recursive definition of map macro, assumes at least one argument */
119 #define MCUX_CSSL_CPP_MAP_IMPL(__macro, ...) \
120  /* Apply the macro to the first argument from the list */\
121  __macro(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure second argument: */ 0)) \
122  /* Only proceed if there are additional arguments */\
123  MCUX_CSSL_CPP_IF(MCUX_CSSL_CPP_HAS_MORE_ARGS(__VA_ARGS__))( \
124  /* Recursive call for remaining arguments */\
125  MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_MAP_IMPL_)()(__macro, \
126  MCUX_CSSL_CPP_NEXT(__VA_ARGS__)) \
127  )
128 #define MCUX_CSSL_CPP_MAP_IMPL_() MCUX_CSSL_CPP_MAP_IMPL
129 
130 /* Extract first argument (requires at least two arguments to be present) */
131 #define MCUX_CSSL_CPP_FIRST(a, ...) a
132 /* Extract second argument (requires at least three arguments to be present) */
133 #define MCUX_CSSL_CPP_SECOND(a, b, ...) b
134 /* Extract second argument (requires at least four arguments to be present) */
135 #define MCUX_CSSL_CPP_THIRD(a, b, c, ...) c
136 /* Extract second argument (requires at least five arguments to be present) */
137 #define MCUX_CSSL_CPP_FOURTH(a, b, c, d, ...) d
138 /* Remove the first argument from the list (requires at least two arguments to be present) */
139 #define MCUX_CSSL_CPP_NEXT(...) MCUX_CSSL_CPP_NEXT_()(__VA_ARGS__)
140 #define MCUX_CSSL_CPP_NEXT_() MCUX_CSSL_CPP_NEXT__
141 #define MCUX_CSSL_CPP_NEXT__(x, ...) __VA_ARGS__
142 
143 /* Check whether there is more then one argument */
144 #define MCUX_CSSL_CPP_HAS_MORE_ARGS(...) \
145  MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER())))
146 
147 #define MCUX_CSSL_CPP_HAS_ONE_ARG(...) \
148  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
149 
150 #define MCUX_CSSL_CPP_HAS_TWO_ARGS(...) \
151  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_THIRD(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
152 
153 #define MCUX_CSSL_CPP_HAS_THREE_ARGS(...) \
154  MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_FOURTH(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))
155 
156 
157 /* Check whether the argument is MCUX_CSSL_CPP_MARKER(), return 1 if it is */
158 #define MCUX_CSSL_CPP_IS_MARKER(...) \
159  MCUX_CSSL_CPP_SECOND(__VA_ARGS__, 0, 0)
160 #define MCUX_CSSL_CPP_MARKER() \
161  ~, 1
162 
163 /* Convert any argument into a bool (either 0 or 1), by double negation */
164 #define MCUX_CSSL_CPP_BOOL(x) MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_NOT(x))
165 
166 /* Boolean negation (map value 0 to the marker, and check if we have the marker) */
167 #define MCUX_CSSL_CPP_NOT(x) MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_NOT_BOOL_, x))
168 #define MCUX_CSSL_CPP_NOT_BOOL_0 MCUX_CSSL_CPP_MARKER()
169 
170 /* Convert condition to bool */
171 #define MCUX_CSSL_CPP_IF(condition) MCUX_CSSL_CPP_IF_(MCUX_CSSL_CPP_BOOL(condition))
172 /* Convert bool to decision defines */
173 #define MCUX_CSSL_CPP_IF_(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IF_BOOL_, condition)
174 /* If 0, do nothing*/
175 #define MCUX_CSSL_CPP_IF_BOOL_0(...)
176 /* If 1, perform action */
177 #define MCUX_CSSL_CPP_IF_BOOL_1(...) __VA_ARGS__
178 
179 /* Convert condition to bool */
180 #define MCUX_CSSL_CPP_IF_ELSE(condition) MCUX_CSSL_CPP_IF_ELSE_IMPL(MCUX_CSSL_CPP_BOOL(condition))
181 /* Convert bool to decision defines */
182 #define MCUX_CSSL_CPP_IF_ELSE_IMPL(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IFE_BOOL_, condition)
183 /* If 0, ignore action */
184 #define MCUX_CSSL_CPP_IFE_BOOL_0(...) MCUX_CSSL_CPP_IFE_BOOL_0_ELSE
185 /* Else 0, perform action */
186 #define MCUX_CSSL_CPP_IFE_BOOL_0_ELSE(...) __VA_ARGS__
187 /* If 1, perform action */
188 #define MCUX_CSSL_CPP_IFE_BOOL_1(...) __VA_ARGS__ MCUX_CSSL_CPP_IFE_BOOL_1_ELSE
189 /* Else 1, ignore action */
190 
191 #define MCUX_CSSL_CPP_IFE_BOOL_1_ELSE(...)
192 
193 /* Defer macro expansion */
194 #define MCUX_CSSL_CPP_EMPTY()
195 #define MCUX_CSSL_CPP_DEFER1(macro) macro MCUX_CSSL_CPP_EMPTY()
196 #define MCUX_CSSL_CPP_DEFER2(macro) macro MCUX_CSSL_CPP_EMPTY MCUX_CSSL_CPP_EMPTY()()
197 
198 #endif /* MCUX_CSSL_C_PRE_PROCESSOR_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00587.html b/components/els_pkc/doc/mcxn/html/a00587.html new file mode 100644 index 000000000..ba37e21c9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00587.html @@ -0,0 +1,160 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslDataIntegrity.h File Reference
+
+
+ +

Provides the API for the CSSL data integrity mechanism. +More...

+
#include <mcuxCsslDataIntegrity_Impl.h>
+#include <mcuxCsslSecureCounter.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_DI_CHECK_PASSED
 Positive comparison result value. More...
 
#define MCUX_CSSL_DI_CHECK_FAILED
 Negative comparison result value. More...
 
#define MCUX_CSSL_DI_INIT_DEFAULT_VALUE
 Default value use for the initialization of the data integrity mechanism. More...
 
#define MCUX_CSSL_DI_ALLOC()
 Allocation operation for the data integrity register. More...
 
#define MCUX_CSSL_DI_INIT(value)
 Initialization operation for the data integrity mechanism. More...
 
#define MCUX_CSSL_DI_CHECK(reference)
 Comparison operation for the data integrity. More...
 
#define MCUX_CSSL_DI_RECORD(identifier, value)
 Record the value for data integrity checking. More...
 
#define MCUX_CSSL_DI_EXPUNGE(identifier, value)
 Expunge the record for value. More...
 
+

Detailed Description

+

Provides the API for the CSSL data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00587.js b/components/els_pkc/doc/mcxn/html/a00587.js new file mode 100644 index 000000000..86d1e8e37 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00587.js @@ -0,0 +1,11 @@ +var a00587 = +[ + [ "MCUX_CSSL_DI_CHECK_PASSED", "a00862.html#gaf795c9830ecd5c53d21ae5efb05716c0", null ], + [ "MCUX_CSSL_DI_CHECK_FAILED", "a00862.html#ga836c5e13eae4d1fdcfe33a41051c26b5", null ], + [ "MCUX_CSSL_DI_INIT_DEFAULT_VALUE", "a00862.html#ga43f4285ae50273c0c9ddd7bb4afa123d", null ], + [ "MCUX_CSSL_DI_ALLOC", "a00862.html#ga7f64db7a5134579f6225fc87a04c9e10", null ], + [ "MCUX_CSSL_DI_INIT", "a00862.html#ga8e9f35be6109155f823f827707af31fb", null ], + [ "MCUX_CSSL_DI_CHECK", "a00862.html#ga86a850875eca35952e2c3a8312364896", null ], + [ "MCUX_CSSL_DI_RECORD", "a00863.html#ga885885837b7340002b9782ffc41e4842", null ], + [ "MCUX_CSSL_DI_EXPUNGE", "a00863.html#ga3e10066c4efffa9040982cde10a52076", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00587_source.html b/components/els_pkc/doc/mcxn/html/a00587_source.html new file mode 100644 index 000000000..328123ecd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00587_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslDataIntegrity.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLDATAINTEGRITY_H_
20 #define MCUXCSSLDATAINTEGRITY_H_
21 
22 /* Include the actual implementation of the data integrity mechanism. */
23 #include <mcuxCsslDataIntegrity_Impl.h>
24 
25 /* Include the Secure Counter definitions */
26 #include <mcuxCsslSecureCounter.h>
27 
43 /****************************************************************************/
44 /* Constants */
45 /****************************************************************************/
46 
53 #define MCUX_CSSL_DI_CHECK_PASSED \
54  MCUX_CSSL_DI_CHECK_PASSED_IMPL
55 
62 #define MCUX_CSSL_DI_CHECK_FAILED \
63  MCUX_CSSL_DI_CHECK_FAILED_IMPL
64 
71 #define MCUX_CSSL_DI_INIT_DEFAULT_VALUE \
72  (0x96969696u)
73 
74 /****************************************************************************/
75 /* Initialization */
76 /****************************************************************************/
77 
84 #define MCUX_CSSL_DI_ALLOC() \
85  MCUX_CSSL_DI_ALLOC_IMPL()
86 
95 #define MCUX_CSSL_DI_INIT(value) \
96  MCUX_CSSL_DI_INIT_IMPL(value)
97 
98 /****************************************************************************/
99 /* Check */
100 /****************************************************************************/
101 
112 #define MCUX_CSSL_DI_CHECK(reference) \
113  MCUX_CSSL_DI_CHECK_IMPL(reference)
114 
115 /****************************************************************************/
116 /* Updates */
117 /****************************************************************************/
118 
134 #define MCUX_CSSL_DI_RECORD(identifier, value) \
135  MCUX_CSSL_DI_RECORD_IMPL(identifier, value)
136 
146 #define MCUX_CSSL_DI_EXPUNGE(identifier, value) \
147  MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value)
148 
149 #endif /* MCUXCSSLDATAINTEGRITY_H_ */
mcuxCsslDataIntegrity_Impl.h
Selection of the implementation for the data integrity mechanism.
+
mcuxCsslSecureCounter.h
Provides the API for the CSSL secure counter mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00590.html b/components/els_pkc/doc/mcxn/html/a00590.html new file mode 100644 index 000000000..d9adf9779 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00590.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_Cfg.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslDataIntegrity_Cfg.h File Reference
+
+
+ +

Configuration of the implementation for the data integrity mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + +

+Macros

#define MCUX_CSSL_DI_USE_SECURE_COUNTER
 If set to 1, use the data integrity mechanism implementation based on the CSSL secure counter mechanism. More...
 
#define MCUX_CSSL_DI_USE_NONE
 If set to 1, do not use the data integrity mechanism. More...
 
+

Detailed Description

+

Configuration of the implementation for the data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00590.js b/components/els_pkc/doc/mcxn/html/a00590.js new file mode 100644 index 000000000..1c1f193e1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00590.js @@ -0,0 +1,5 @@ +var a00590 = +[ + [ "MCUX_CSSL_DI_USE_SECURE_COUNTER", "a00865.html#gad14940e758b00b26f2e699b4fc0144bb", null ], + [ "MCUX_CSSL_DI_USE_NONE", "a00865.html#ga4f0cea555852c5171e55303b6cb062be", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00590_source.html b/components/els_pkc/doc/mcxn/html/a00590_source.html new file mode 100644 index 000000000..4fb9ccd3d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00590_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_Cfg.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
+
+
mcuxCsslDataIntegrity_Cfg.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLDATAINTEGRITY_CFG_H_
20 #define MCUXCSSLDATAINTEGRITY_CFG_H_
21 
36  #define MCUX_CSSL_DI_USE_SECURE_COUNTER 0
37 
43  #define MCUX_CSSL_DI_USE_NONE 1
44 
45 /* Basic configuration sanity check */
46 
47 #endif /* MCUXCSSLDATAINTEGRITY_CFG_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00593.html b/components/els_pkc/doc/mcxn/html/a00593.html new file mode 100644 index 000000000..0a79614b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00593.html @@ -0,0 +1,130 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_Impl.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ + +
+ +
+ +
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+
mcuxCsslDataIntegrity_Impl.h File Reference
+
+
+ +

Selection of the implementation for the data integrity mechanism. +More...

+
#include <mcuxCsslDataIntegrity_Cfg.h>
+#include <mcuxCsslDataIntegrity_None.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Selection of the implementation for the data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00593_source.html b/components/els_pkc/doc/mcxn/html/a00593_source.html new file mode 100644 index 000000000..efaf0a6ef --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00593_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_Impl.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslDataIntegrity_Impl.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLDATAINTEGRITY_IMPL_H_
20 #define MCUXCSSLDATAINTEGRITY_IMPL_H_
21 
22 /* Include the configuration for the data integrity mechanism. */
23 #include <mcuxCsslDataIntegrity_Cfg.h>
24 
25 /* Include the selected implementation of the data integrity mechanism. */
26 #if defined(MCUX_CSSL_DI_USE_SECURE_COUNTER) && (1 == MCUX_CSSL_DI_USE_SECURE_COUNTER)
27 # include <mcuxCsslDataIntegrity_SecureCounter.h>
28 #elif defined(MCUX_CSSL_DI_USE_NONE) && (1 == MCUX_CSSL_DI_USE_NONE)
29 # include <mcuxCsslDataIntegrity_None.h>
30 #else
31 # error "No data integrity implementation found/configured."
32 #endif
33 
34 #endif /* MCUXCSSLDATAINTEGRITY_IMPL_H_ */
mcuxCsslDataIntegrity_None.h
Implementation that disables the CSSL data integrity mechanism.
+
mcuxCsslDataIntegrity_Cfg.h
Configuration of the implementation for the data integrity mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00596.html b/components/els_pkc/doc/mcxn/html/a00596.html new file mode 100644 index 000000000..96988e3fa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00596.html @@ -0,0 +1,155 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_None.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+Macros
+
+
mcuxCsslDataIntegrity_None.h File Reference
+
+
+ +

Implementation that disables the CSSL data integrity mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_DI_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_DI_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_DI_ALLOC_IMPL()
 Allocation operation implementation for the data integrity. More...
 
#define MCUX_CSSL_DI_INIT_IMPL(value)
 Initialization operation implementation for the data integrity. More...
 
#define MCUX_CSSL_DI_CHECK_IMPL(reference)
 Comparison operation implementation for the data integrity. More...
 
#define MCUX_CSSL_DI_RECORD_IMPL(identifier, value)
 Implementation: Record the value for data integrity checking. More...
 
#define MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value)
 Implementation: Expunge the record for value. More...
 
+

Detailed Description

+

Implementation that disables the CSSL data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00596.js b/components/els_pkc/doc/mcxn/html/a00596.js new file mode 100644 index 000000000..250ef034b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00596.js @@ -0,0 +1,10 @@ +var a00596 = +[ + [ "MCUX_CSSL_DI_CHECK_PASSED_IMPL", "a00868.html#ga4deb1836544c454f189e5aefe3a16b90", null ], + [ "MCUX_CSSL_DI_CHECK_FAILED_IMPL", "a00868.html#ga381a9c96de77bfc8d099d9ebcc54f71b", null ], + [ "MCUX_CSSL_DI_ALLOC_IMPL", "a00868.html#ga923d5186da2eecf410950262961e03c5", null ], + [ "MCUX_CSSL_DI_INIT_IMPL", "a00868.html#gadc0c4c5c446999ac332e799edbe04249", null ], + [ "MCUX_CSSL_DI_CHECK_IMPL", "a00868.html#gac19903f4bcc14df44ce3779e82eeec8b", null ], + [ "MCUX_CSSL_DI_RECORD_IMPL", "a00869.html#ga528d28a827727ba460795460a30cccfd", null ], + [ "MCUX_CSSL_DI_EXPUNGE_IMPL", "a00869.html#gaac8a8ea1888347d41f58f27f11c9caab", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00596_source.html b/components/els_pkc/doc/mcxn/html/a00596_source.html new file mode 100644 index 000000000..32b7bc2e4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00596_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslDataIntegrity_None.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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mcuxCsslDataIntegrity_None.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLDATAINTEGRITY_NONE_H_
20 #define MCUXCSSLDATAINTEGRITY_NONE_H_
21 
37 /****************************************************************************/
38 /* Constants */
39 /****************************************************************************/
40 
46 #define MCUX_CSSL_DI_CHECK_PASSED_IMPL (MCUX_CSSL_SC_CHECK_PASSED)
47 
53 #define MCUX_CSSL_DI_CHECK_FAILED_IMPL (MCUX_CSSL_SC_CHECK_FAILED)
54 
55 /****************************************************************************/
56 /* Initialization */
57 /****************************************************************************/
58 
64 #define MCUX_CSSL_DI_ALLOC_IMPL() \
65  /* intentionally empty */
66 
74 #define MCUX_CSSL_DI_INIT_IMPL(value) \
75  /* intentionally empty */
76 
77 /****************************************************************************/
78 /* Check */
79 /****************************************************************************/
80 
89 #define MCUX_CSSL_DI_CHECK_IMPL(reference) \
90  (MCUX_CSSL_DI_CHECK_PASSED_IMPL)
91 
92 /****************************************************************************/
93 /* Updates */
94 /****************************************************************************/
95 
110 #define MCUX_CSSL_DI_RECORD_IMPL(identifier, value) \
111  /* intentionally empty */
112 
121 #define MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value) \
122  /* intentionally empty */
123 
124 
125 #endif /* MCUXCSSLDATAINTEGRITY_NONE_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00599.html b/components/els_pkc/doc/mcxn/html/a00599.html new file mode 100644 index 000000000..f9818fcec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00599.html @@ -0,0 +1,246 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection.h File Reference + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
+
+
mcuxCsslFlowProtection.h File Reference
+
+
+ +

Provides the API for the CSSL flow protection mechanism. +More...

+
#include <mcuxCsslFlowProtection_Impl.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
 Based on a given base type, builds a return type with flow protection. More...
 
#define MCUX_CSSL_FP_COUNTER_STMT(statement)
 A statement which is only evaluated if a secure counter is used. More...
 
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
 Declaration of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
 Definition of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_POINTER(type, definition)
 Definition of a flow protected function pointer. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY(...)
 Flow protection handler for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT(...)
 Flow protection handler for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(...)
 Flow protection handler for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID(...)
 Flow protection handler for the exit point of functions with the return type void. More...
 
#define MCUX_CSSL_FP_RESULT(return)
 Extract the result value from a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN(return)
 Extract the protection token value from a protected return value. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL(...)
 Call a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID(...)
 Call a flow protected void function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(...)
 Call a flow protected function from unprotected code. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED(...)
 Call a flow protected void function from unprotected code. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
 Call a flow protected function and check the protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
 End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...)
 Call a flow protected void function and check the protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...)
 End a void function call section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
 Expectation of a called function. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTERED(id)
 Expectation implementation of an entered (but not exited) function. More...
 
#define MCUX_CSSL_FP_LOOP_DECL(id)
 Declaration of a flow protected loop. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION(...)
 Perform a loop iteration. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATIONS(id, count)
 Expected number of loop iterations. More...
 
#define MCUX_CSSL_FP_BRANCH_DECL(id)
 Declaration of a flow protected branch. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE(...)
 Positive scenario for a branch is executed. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE(...)
 Negative scenario of a branch is executed. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(...)
 Expectation that positive branch has been taken. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(...)
 Expectation that negative branch has been taken. More...
 
#define MCUX_CSSL_FP_SWITCH_DECL(id)
 Declaration of a flow protected switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN(...)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(...)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_EXPECT(...)
 Declaration(s) of expected code flow behavior. More...
 
#define MCUX_CSSL_FP_CONDITIONAL(condition, ...)
 Handling of conditionally expected code flow behavior. More...
 
#define MCUX_CSSL_FP_ASSERT(...)
 Assert an expected state of the code flow. More...
 
+

Detailed Description

+

Provides the API for the CSSL flow protection mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00599.js b/components/els_pkc/doc/mcxn/html/a00599.js new file mode 100644 index 000000000..566ab0093 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00599.js @@ -0,0 +1,40 @@ +var a00599 = +[ + [ "MCUX_CSSL_FP_PROTECTED_TYPE", "a00872.html#ga6cb5dab960bed02a02ad907bd2a54a4b", null ], + [ "MCUX_CSSL_FP_COUNTER_STMT", "a00872.html#gacb5d4268cc93c95b8e69da19d74de79f", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00872.html#ga21e1a3f12fd2772ca92216b888b3bdff", null ], + [ "MCUX_CSSL_FP_FUNCTION_DEF", "a00872.html#ga7c1d29e4d644c86f11e337e30dd2b210", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00872.html#gab9bdb43ee02202c53d729847dea78ccc", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY", "a00872.html#ga2fda8e2a0e7d862b113b28bcc1b4d9bb", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT", "a00872.html#ga9d9934b6d02da9505dd20ac36236b61d", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK", "a00872.html#ga7c4b79e79eecb68ef4e4fb4fb9fbc1b8", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID", "a00872.html#ga4c6863806f0054719824891271a5f598", null ], + [ "MCUX_CSSL_FP_RESULT", "a00872.html#ga3919086f41a5a26003dd28b528aa473f", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN", "a00872.html#ga8d5c6d7d0c0aba35d4a841e964d5d607", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL", "a00872.html#ga9517fd35bea64a62f1cd3bf58a6218ef", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID", "a00872.html#ga8d8dfc8f87971ee861d0bc77118a97cb", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED", "a00872.html#gac861d63fbf4a985b570845c02c5e412f", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED", "a00872.html#ga5544a5ce0e2478832eb1eacf339b4475", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_BEGIN", "a00872.html#ga8a9b1ebbc02c8195618a339aa8e0003d", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_END", "a00872.html#gac4362de43d0e67ba6fac0057eb38008d", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN", "a00872.html#ga268f9c22cb59586556e0cbb21ac3320e", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_END", "a00872.html#ga30de6960e0ce17187bce680980617f38", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALLED", "a00872.html#gac16ad6597579a02a30ada37f86f216d5", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTERED", "a00872.html#ga9f7aa860f353079a6da5188bd18b977c", null ], + [ "MCUX_CSSL_FP_LOOP_DECL", "a00873.html#ga96df84766aff763718a84dd44246af38", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION", "a00873.html#gae7942657c4fac73115908f05c382cc86", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATIONS", "a00873.html#gae5aabc3339a46a799d1fefd1095a4898", null ], + [ "MCUX_CSSL_FP_BRANCH_DECL", "a00874.html#ga1406430491edf42797f1fbb6fec6d400", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE", "a00874.html#ga9aaebd3ae72dfb08a7a286c9cf02898c", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE", "a00874.html#ga67a87d7f006f7f4fc09f1a0b93d21043", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE", "a00874.html#ga99db0902665c118dbfeacd73dd8c8672", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE", "a00874.html#ga7ca1b74234f560a110647fbc24fec3f9", null ], + [ "MCUX_CSSL_FP_SWITCH_DECL", "a00875.html#gafc01be288246642c1b2779b69188adad", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE", "a00875.html#gab3a2723c9a344c245ff6b596aaee5414", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT", "a00875.html#gaebd999394afa94e2c3e3b64f68d85e2a", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN", "a00875.html#gaa620180722a4eaa8e7370a92d2bd18d9", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT", "a00875.html#gac011e972fff0f38d704edfeadce256cd", null ], + [ "MCUX_CSSL_FP_EXPECT", "a00876.html#ga83db474d65df2b52abea45293f9684d0", null ], + [ "MCUX_CSSL_FP_CONDITIONAL", "a00876.html#ga24a55fecde25d3aa0a227814345b9714", null ], + [ "MCUX_CSSL_FP_ASSERT", "a00876.html#ga301b8f23ac6981e62649c8f571a6c6eb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00599_source.html b/components/els_pkc/doc/mcxn/html/a00599_source.html new file mode 100644 index 000000000..baf2713fe --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00599_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUX_CSSL_FLOW_PROTECTION_H_
20 #define MCUX_CSSL_FLOW_PROTECTION_H_
21 
22 /* Include the actual implementation of the flow protection mechanism. */
23 #include <mcuxCsslFlowProtection_Impl.h>
24 
58 #ifdef __COVERITY__
59 #pragma coverity compliance block deviate MISRA_C_2012_Rule_3_1 "Comments outline example sequences. For more readability, additional inner comments might be added."
60 #endif
61 
81 #define MCUX_CSSL_FP_PROTECTED_TYPE(resultType) \
82  MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType)
83 
96 #define MCUX_CSSL_FP_COUNTER_STMT(statement) \
97  MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement)
98 
99 
125 #define MCUX_CSSL_FP_FUNCTION_DECL(...) \
126  MCUX_CSSL_FP_FUNCTION_DECL_IMPL(__VA_ARGS__)
127 
159 #define MCUX_CSSL_FP_FUNCTION_DEF(...) \
160  MCUX_CSSL_FP_FUNCTION_DEF_IMPL(__VA_ARGS__)
161 
195 #define MCUX_CSSL_FP_FUNCTION_POINTER(type, definition) \
196  MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition)
197 
244 #define MCUX_CSSL_FP_FUNCTION_ENTRY(...) \
245  MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
246 
286 #define MCUX_CSSL_FP_FUNCTION_EXIT(...) \
287  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
288 
325 #define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(...) \
326  MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
327 
365 #define MCUX_CSSL_FP_FUNCTION_EXIT_VOID(...) \
366  MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
367 
375 #define MCUX_CSSL_FP_RESULT(return) \
376  MCUX_CSSL_FP_RESULT_IMPL(return)
377 
388 #define MCUX_CSSL_FP_PROTECTION_TOKEN(return) \
389  MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return)
390 
427 #define MCUX_CSSL_FP_FUNCTION_CALL(...) \
428  MCUX_CSSL_FP_FUNCTION_CALL_IMPL(__VA_ARGS__)
429 
462 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID(...) \
463  MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(__VA_ARGS__)
464 
500 #define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(...) \
501  MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(__VA_ARGS__)
502 
536 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED(...) \
537  MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(__VA_ARGS__)
538 
576 #define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...) \
577  MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(__VA_ARGS__)
578 
611 #define MCUX_CSSL_FP_FUNCTION_CALL_END(...) \
612  MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL(__VA_ARGS__)
613 
647 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...) \
648  MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(__VA_ARGS__)
649 
678 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...) \
679  MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL(__VA_ARGS__)
680 
730 #define MCUX_CSSL_FP_FUNCTION_CALLED(...) \
731  MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(__VA_ARGS__)
732 
733 
765 #define MCUX_CSSL_FP_FUNCTION_ENTERED(id) \
766  MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id)
767 
768 
805 #define MCUX_CSSL_FP_LOOP_DECL(id) \
806  MCUX_CSSL_FP_LOOP_DECL_IMPL(id)
807 
833 #define MCUX_CSSL_FP_LOOP_ITERATION(...) \
834  MCUX_CSSL_FP_LOOP_ITERATION_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
835 
868 #define MCUX_CSSL_FP_LOOP_ITERATIONS(id, count) \
869  MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count)
870 
871 
872 
914 #define MCUX_CSSL_FP_BRANCH_DECL(id) \
915  MCUX_CSSL_FP_BRANCH_DECL_IMPL(id)
916 
953 #define MCUX_CSSL_FP_BRANCH_POSITIVE(...) \
954  MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
955 
992 #define MCUX_CSSL_FP_BRANCH_NEGATIVE(...) \
993  MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
994 
1035 #define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(...) \
1036  MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(__VA_ARGS__)
1037 
1080 #define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(...) \
1081  MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(__VA_ARGS__)
1082 
1083 
1084 
1137 #define MCUX_CSSL_FP_SWITCH_DECL(id) \
1138  MCUX_CSSL_FP_SWITCH_DECL_IMPL(id)
1139 
1186 #define MCUX_CSSL_FP_SWITCH_CASE(...) \
1187  MCUX_CSSL_FP_SWITCH_CASE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
1188 
1234 #define MCUX_CSSL_FP_SWITCH_DEFAULT(...) \
1235  MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
1236 
1288 #define MCUX_CSSL_FP_SWITCH_TAKEN(...) \
1289  MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(__VA_ARGS__)
1290 
1340 #define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(...) \
1341  MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(__VA_ARGS__)
1342 
1343 
1344 
1377 #define MCUX_CSSL_FP_EXPECT(...) \
1378  MCUX_CSSL_FP_EXPECT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
1379 
1400 #define MCUX_CSSL_FP_CONDITIONAL(condition, ...) \
1401  MCUX_CSSL_FP_CONDITIONAL_IMPL((condition), __VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL())
1402 
1403 #ifdef __COVERITY__
1404 #pragma coverity compliance end_block MISRA_C_2012_Rule_3_1
1405 #endif
1406 
1432 #define MCUX_CSSL_FP_ASSERT(...) \
1433  MCUX_CSSL_FP_ASSERT_IMPL(__VA_ARGS__)
1434 
1435 #endif /* MCUX_CSSL_FLOW_PROTECTION_H_ */
1436 
mcuxCsslFlowProtection_Impl.h
Selection of the implementation for the flow protection mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00602.html b/components/els_pkc/doc/mcxn/html/a00602.html new file mode 100644 index 000000000..560cee8e6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00602.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_Cfg.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslFlowProtection_Cfg.h File Reference
+
+
+ +

Configuration of the implementation for the flow protection mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_USE_CODE_SIGNATURE
 If set to 1, use the flow protection mechanism implementation based on the Zen-V code signature HW mechanism. More...
 
#define MCUX_CSSL_FP_USE_SECURE_COUNTER
 If set to 1, use the flow protection mechanism implementation based on the CSSL secure counter mechanism. More...
 
#define MCUX_CSSL_FP_USE_NONE
 If set to 1, do not use the flow protection mechanism. More...
 
+

Detailed Description

+

Configuration of the implementation for the flow protection mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00602.js b/components/els_pkc/doc/mcxn/html/a00602.js new file mode 100644 index 000000000..8ff353626 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00602.js @@ -0,0 +1,6 @@ +var a00602 = +[ + [ "MCUX_CSSL_FP_USE_CODE_SIGNATURE", "a00877.html#gaeaecd08382d1bf7542d523e67c15b90b", null ], + [ "MCUX_CSSL_FP_USE_SECURE_COUNTER", "a00877.html#ga645fafaa87e927ec807c9679dfa6d74e", null ], + [ "MCUX_CSSL_FP_USE_NONE", "a00877.html#ga8fcbc78b6821d4cd6ea67bdc3d4e3ba7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00602_source.html b/components/els_pkc/doc/mcxn/html/a00602_source.html new file mode 100644 index 000000000..61d8a315c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00602_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_Cfg.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_Cfg.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUX_CSSL_FLOW_PROTECTION_CFG_H_
20 #define MCUX_CSSL_FLOW_PROTECTION_CFG_H_
21 
36  #define MCUX_CSSL_FP_USE_CODE_SIGNATURE 0
37 
44  #define MCUX_CSSL_FP_USE_SECURE_COUNTER 1
45 
51  #define MCUX_CSSL_FP_USE_NONE 0
52 
53 /* Basic configuration sanity check */
54 
55 #endif /* MCUX_CSSL_FLOW_PROTECTION_CFG_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00605.html b/components/els_pkc/doc/mcxn/html/a00605.html new file mode 100644 index 000000000..dfd46b4ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00605.html @@ -0,0 +1,438 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_FunctionIdentifiers.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+Macros
+
+
mcuxCsslFlowProtection_FunctionIdentifiers.h File Reference
+
+
+ +

Definition of function identifiers for the flow protection mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUX_CSSL_FP_FUNCID_functionOnly0
 
+#define MCUX_CSSL_FP_FUNCID_functionOnly1
 
+#define MCUX_CSSL_FP_FUNCID_functionOnly2
 
+#define MCUX_CSSL_FP_FUNCID_functionCall
 
+#define MCUX_CSSL_FP_FUNCID_functionCalls
 
+#define MCUX_CSSL_FP_FUNCID_functionLoop
 
+#define MCUX_CSSL_FP_FUNCID_functionBranch
 
+#define MCUX_CSSL_FP_FUNCID_functionSwitch
 
+#define MCUX_CSSL_FP_FUNCID_functionComplex
 
+#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_compare
 
+#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_copy
 
+#define MCUX_CSSL_FP_FUNCID_functionAssert
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslParamIntegrity_Validate
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Compare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Copy
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Clear
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Set
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureClear
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCopy
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureSet
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCompare
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyPow2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecCopyPow2
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecComp
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecClear
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecSet
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXOR
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXORWithConst
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_11
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_12
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_13
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_14
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_15
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_16
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_17
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_18
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_19
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_20
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_21
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_22
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_23
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_24
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_25
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_26
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_27
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_28
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_29
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_30
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_31
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_32
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_33
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_34
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_35
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_36
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_37
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_38
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_39
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_40
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_41
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_42
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_43
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_44
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_45
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_46
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_47
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_48
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_49
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_50
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_51
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_52
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_53
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_54
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_55
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_56
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_57
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_58
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_59
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_60
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_61
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_62
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_63
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_64
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_65
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_66
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_67
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_68
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_69
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_70
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_71
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_72
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_73
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_74
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_75
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_76
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_77
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_78
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_79
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_80
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_81
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_82
 
+#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_83
 
+

Detailed Description

+

Definition of function identifiers for the flow protection mechanism.

+
Note
This file might be post-processed to update the identifier values to proper/secure values.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00605.js b/components/els_pkc/doc/mcxn/html/a00605.js new file mode 100644 index 000000000..58e7d7e9f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00605.js @@ -0,0 +1,104 @@ +var a00605 = +[ + [ "MCUX_CSSL_FP_FUNCID_functionOnly0", "a00605.html#a73d5b591cc03f0aaef5e630048b71351", null ], + [ "MCUX_CSSL_FP_FUNCID_functionOnly1", "a00605.html#af35d8b3fceb113024ff726237c82786d", null ], + [ "MCUX_CSSL_FP_FUNCID_functionOnly2", "a00605.html#a186a446bbb7e2c6ce6d076f42ef5bda6", null ], + [ "MCUX_CSSL_FP_FUNCID_functionCall", "a00605.html#a5f88410408cb24d11228c7a8ab872f50", null ], + [ "MCUX_CSSL_FP_FUNCID_functionCalls", "a00605.html#a769946b750e110d641c53a9009dac0ab", null ], + [ "MCUX_CSSL_FP_FUNCID_functionLoop", "a00605.html#a65fa3052cfd9a72fa9f465c9b53ba344", null ], + [ "MCUX_CSSL_FP_FUNCID_functionBranch", "a00605.html#acc5243088d9d1b90a06d7c78488669d7", null ], + [ "MCUX_CSSL_FP_FUNCID_functionSwitch", "a00605.html#ae2e3c1ed18022f8b882911e0ebe2a3d0", null ], + [ "MCUX_CSSL_FP_FUNCID_functionComplex", "a00605.html#a244d7b1e90c69363d7b443fb919060dc", null ], + [ "MCUX_CSSL_FP_FUNCID_data_invariant_memory_compare", "a00605.html#a798c43865074c3298c8d4aa96724a12c", null ], + [ "MCUX_CSSL_FP_FUNCID_data_invariant_memory_copy", "a00605.html#ae74e417044a5f4fd688273d6685e9304", null ], + [ "MCUX_CSSL_FP_FUNCID_functionAssert", "a00605.html#a18d54e79ec0c7693e56e0b0801dd073b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslParamIntegrity_Validate", "a00605.html#a6926c8a1d4e7a5d94af65219fcec3907", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Compare", "a00605.html#a572d3c3edb4523a9b61d51d380fec14f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Copy", "a00605.html#a9d1401173a738706316d732e155fedee", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Clear", "a00605.html#a4a1dc58fb1af7540f6fee3db57917119", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Set", "a00605.html#a3f013e297d7e468bf9f61ec6e2d8c3ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureClear", "a00605.html#a633a4edc3b77048801856344d2c1c08a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCopy", "a00605.html#a622a9a2e0bc03662e11c973929c3800f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureSet", "a00605.html#ad3a61394c9427717d5681ab03edaba36", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCompare", "a00605.html#ab46262b2781b85eaf09a6c5608d4a8e5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyPow2", "a00605.html#a91308182612f39611183a6611c86d1cb", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecCopyPow2", "a00605.html#a3ef5d09ba6f7251f7d383ae01e7b44a4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecComp", "a00605.html#ae7bae7048e925801548153ac324893f7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecClear", "a00605.html#a8e7dc0e6552354790d073a4716fca695", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecSet", "a00605.html#ae22d40208a05c1dd403df5ca1fb38265", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXOR", "a00605.html#a372818f4dba1e7afceec9a9d156bc02e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXORWithConst", "a00605.html#a73f82fa603a9c198b1a90b7d6bc52d47", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_11", "a00605.html#a6d346a27fcd225ca998142e2cb26d755", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_12", "a00605.html#a48facd4013f791976da8c7708c1089f5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_13", "a00605.html#ab6cc4d8d9c2fb0d732096ad13978da4b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_14", "a00605.html#a05709fa4b5758017fcc1c9415d2a12ce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_15", "a00605.html#a0f1b0dd7a596f72e6cddc3fb393af831", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_16", "a00605.html#ac25c207da04d5e341d63a33fe3ed8c3b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_17", "a00605.html#a21bd2a8daff698ebc16c4f28d46918d2", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_18", "a00605.html#a4313cff83e0c1abd035988b94d3cb6a6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_19", "a00605.html#aa70acdb1be2464237dee6ff516e2902a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_20", "a00605.html#a33055e73bbf6f2a5ecd561d8dd5ecc87", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_21", "a00605.html#ae0555b87cd208e2532647ed761434f40", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_22", "a00605.html#a1f0eb9428199885ed292b5b740d989ff", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_23", "a00605.html#a0f63015b6889cf38823c643103b1fad3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_24", "a00605.html#ab7214869c13a772a24806c0d5d05b709", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_25", "a00605.html#a6099d983c4bd6562944d47dfe62ef92a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_26", "a00605.html#ae6e5f78d141bcff5daec80d8f2772726", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_27", "a00605.html#af95d126316a3e06966dc255babcec95c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_28", "a00605.html#a384fc546cd8f78f89cd9c7e1524262d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_29", "a00605.html#a351ce9420276d32a53ac27f39396b1e0", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_30", "a00605.html#ab6028a86273eb08016dd9a677d2d20a5", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_31", "a00605.html#aead08d80f2bdf845be6a9aa61c92ff2c", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_32", "a00605.html#a8ba7a676a07b864f896aaec914c55c65", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_33", "a00605.html#a7dcb01f46124061ff324768819af286a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_34", "a00605.html#a06b72bcd066f0915795535fa53ca144d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_35", "a00605.html#a4febd885e5d28e932715b88f30d4639f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_36", "a00605.html#a03f2ebf2f300ce2fdf7216bf6bcd3a5d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_37", "a00605.html#a8536e5f190b1b1dae7ea302c79b803a8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_38", "a00605.html#a5c8b7c2959161f53169ff293224498d4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_39", "a00605.html#a1d28a078ba079027977bda978fa269d1", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_40", "a00605.html#ae80c9226ca7f08d5caebfbc51ae47c45", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_41", "a00605.html#af330fdfd5e079f6dba1396a4e0194963", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_42", "a00605.html#aed656fccdf616a83dab6e7ab71590e50", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_43", "a00605.html#ac2286721c8b7140be58d8e5a77cb12a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_44", "a00605.html#aa30d0c3e57c3d3697d92e39515cdb9c8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_45", "a00605.html#affee8d86b90c8813567dc28a671cbce8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_46", "a00605.html#aa0cd1b80a9532f5ff1bab60c85780f82", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_47", "a00605.html#ad3e29c1f4893b323d8dea33b62f7da89", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_48", "a00605.html#a50c94d7dfe2458e43b8c466343b6a28a", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_49", "a00605.html#aeb939a9c02f643d609be3239b6c8d955", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_50", "a00605.html#aaaee3787a273912b9bfc85a11154b461", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_51", "a00605.html#ad25422cbea2cd0d2255abbe4d4d436c7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_52", "a00605.html#a26767f6c1590580119a2ab2ddfebef1b", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_53", "a00605.html#a0b92b7d2bdd2f48646a74ce8c050bf0f", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_54", "a00605.html#ad354a1edea62d1ff6eff234bbb7b54ef", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_55", "a00605.html#a1e98484ff52ae04a872e88bf3bb329c6", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_56", "a00605.html#a16bb26514dcb425b1d383014b08224dc", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_57", "a00605.html#a4c2aa2eb2b90f3afdd41503ef4d8b9ed", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_58", "a00605.html#aaf07750d941c8f581ef5e4de395bc910", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_59", "a00605.html#a0486b1285651e66ea8c8c3153ed11fce", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_60", "a00605.html#af9829a2c70077731675384381c0eb69d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_61", "a00605.html#a80a6b82ff8129714926333d753ca455d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_62", "a00605.html#afe37b36d5a08d782d132917d2d1f29c4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_63", "a00605.html#adfb2da6c20c0b09f4874ac50f3c9cf5e", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_64", "a00605.html#a8f875f281e9d47d00f1f04c60a07cbf7", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_65", "a00605.html#ac4b063369ba537a57e6e1f77d6837fe8", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_66", "a00605.html#a9e43e06753b390c7d90c454a9a15e8c9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_67", "a00605.html#a7a21e7c10dcc0246a847ac895b6d7f67", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_68", "a00605.html#a65be1019c75d825571cec35359ed7725", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_69", "a00605.html#a1533d17ac427e6475e93fbb9445bf640", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_70", "a00605.html#a516b0e50c2065455e340108e78683919", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_71", "a00605.html#ae563c4d1da81d9840ed20711f172d190", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_72", "a00605.html#aa510f4de2248f97654860e6d2f6b8a03", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_73", "a00605.html#a7af6c17abaa5900f2dbaaac10b6951f4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_74", "a00605.html#a7aedc2d4d0a3454c360531bf4bc0fbab", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_75", "a00605.html#a54694fbdbea5e4992735222068460ec4", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_76", "a00605.html#a4952990542ce93ff89c2ce6976a26b9d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_77", "a00605.html#a3b0958239d9c369b4d0ead499dfeb747", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_78", "a00605.html#a00256092fa2c26bd8c30cbc1ce4377a3", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_79", "a00605.html#a97345b5c4157a7f099418497c96227fd", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_80", "a00605.html#adb100ccbe9834b9aa03841a16ad3d8d9", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_81", "a00605.html#aafd973b5d14410b769c278aebd37e61d", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_82", "a00605.html#aaa998f227bb8f5555c94c1542bc31355", null ], + [ "MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_83", "a00605.html#a03a49c3f5b512556159f4a8726e392c6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00605_source.html b/components/els_pkc/doc/mcxn/html/a00605_source.html new file mode 100644 index 000000000..455049fb4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00605_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_FunctionIdentifiers.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_FunctionIdentifiers.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 #ifndef MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
23 #define MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_
24 
25 /* Flow Protection example values: */
26 #define MCUX_CSSL_FP_FUNCID_functionOnly0 (0x50DDu)
27 #define MCUX_CSSL_FP_FUNCID_functionOnly1 (0x5595u)
28 #define MCUX_CSSL_FP_FUNCID_functionOnly2 (0x6B52u)
29 #define MCUX_CSSL_FP_FUNCID_functionCall (0x50BBu)
30 #define MCUX_CSSL_FP_FUNCID_functionCalls (0x4E71u)
31 #define MCUX_CSSL_FP_FUNCID_functionLoop (0x4AF2u)
32 #define MCUX_CSSL_FP_FUNCID_functionBranch (0x0D3Bu)
33 #define MCUX_CSSL_FP_FUNCID_functionSwitch (0x22AFu)
34 #define MCUX_CSSL_FP_FUNCID_functionComplex (0x781Bu)
35 #define MCUX_CSSL_FP_FUNCID_data_invariant_memory_compare (0x562Bu)
36 #define MCUX_CSSL_FP_FUNCID_data_invariant_memory_copy (0x4AA7u)
37 #define MCUX_CSSL_FP_FUNCID_functionAssert (0x21DEu)
38 /* Values for production use: */
39 #define MCUX_CSSL_FP_FUNCID_mcuxCsslParamIntegrity_Validate (0x1AA7u)
40 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Compare (0x696Cu)
41 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Copy (0x7D21u)
42 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Clear (0x42D7u)
43 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Set (0x44F9u)
44 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureClear (0x29BCu)
45 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCopy (0x27AAu)
46 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureSet (0x5B58u)
47 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCompare (0x79C2u)
48 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyPow2 (0x3761u)
49 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecCopyPow2 (0x4A5Du)
50 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecComp (0x187Eu)
51 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecClear (0x2C3Bu)
52 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecSet (0x6655u)
53 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXOR (0x3366u)
54 #define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXORWithConst (0x4A97u)
55 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_11 (0x629Du)
56 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_12 (0x5AF0u)
57 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_13 (0x53C3u)
58 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_14 (0x17C5u)
59 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_15 (0x1E8Eu)
60 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_16 (0x26A7u)
61 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_17 (0x14F9u)
62 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_18 (0x43E9u)
63 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_19 (0x533Cu)
64 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_20 (0x2EC5u)
65 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_21 (0x7D44u)
66 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_22 (0x2AE3u)
67 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_23 (0x7274u)
68 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_24 (0x7CE0u)
69 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_25 (0x4DC5u)
70 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_26 (0x3E94u)
71 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_27 (0x75A4u)
72 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_28 (0x35E4u)
73 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_29 (0x63F0u)
74 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_30 (0x62BAu)
75 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_31 (0x7549u)
76 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_32 (0x77C0u)
77 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_33 (0x662Eu)
78 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_34 (0x521Fu)
79 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_35 (0x6671u)
80 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_36 (0x711Du)
81 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_37 (0x684Fu)
82 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_38 (0x52EAu)
83 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_39 (0x1EACu)
84 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_40 (0x4D66u)
85 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_41 (0x4557u)
86 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_42 (0x25F2u)
87 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_43 (0x278Bu)
88 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_44 (0x3C55u)
89 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_45 (0x1796u)
90 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_46 (0x6732u)
91 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_47 (0x67D0u)
92 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_48 (0x5627u)
93 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_49 (0x6AB1u)
94 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_50 (0x5927u)
95 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_51 (0x51CEu)
96 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_52 (0x7585u)
97 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_53 (0x78B1u)
98 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_54 (0x0B5Du)
99 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_55 (0x6A87u)
100 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_56 (0x19ABu)
101 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_57 (0x57C1u)
102 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_58 (0x589Du)
103 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_59 (0x61E3u)
104 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_60 (0x0D2Fu)
105 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_61 (0x5B1Cu)
106 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_62 (0x3CD4u)
107 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_63 (0x0C6Fu)
108 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_64 (0x21BDu)
109 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_65 (0x1D9Cu)
110 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_66 (0x5674u)
111 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_67 (0x60DDu)
112 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_68 (0x78AAu)
113 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_69 (0x0F36u)
114 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_70 (0x6B2Au)
115 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_71 (0x2D63u)
116 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_72 (0x2F16u)
117 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_73 (0x4F1Cu)
118 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_74 (0x5B83u)
119 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_75 (0x7833u)
120 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_76 (0x3B26u)
121 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_77 (0x34DCu)
122 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_78 (0x6E46u)
123 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_79 (0x6F21u)
124 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_80 (0x2937u)
125 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_81 (0x1BE2u)
126 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_82 (0x2A9Bu)
127 #define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_83 (0x78A3u)
128 
129 #endif /* MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00608.html b/components/els_pkc/doc/mcxn/html/a00608.html new file mode 100644 index 000000000..3f5f0b856 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00608.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_Impl.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_Impl.h File Reference
+
+
+ +

Selection of the implementation for the flow protection mechanism. +More...

+
#include <mcuxCsslFlowProtection_Cfg.h>
+#include <mcuxCsslSecureCounter_Cfg.h>
+#include <mcuxCsslFlowProtection_SecureCounter_Common.h>
+#include <mcuxCsslFlowProtection_SecureCounter_Global.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Selection of the implementation for the flow protection mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00608_source.html b/components/els_pkc/doc/mcxn/html/a00608_source.html new file mode 100644 index 000000000..dbade18de --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00608_source.html @@ -0,0 +1,125 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_Impl.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_Impl.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUX_CSSL_FLOW_PROTECTION_IMPL_H_
20 #define MCUX_CSSL_FLOW_PROTECTION_IMPL_H_
21 
22 /* Include the configuration for the flow protection mechanism. */
23 #include <mcuxCsslFlowProtection_Cfg.h>
24 
25 /* Include the selected implementation of the flow protection mechanism. */
26 #if defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && (1 == MCUX_CSSL_FP_USE_CODE_SIGNATURE)
27 # include <mcuxCsslFlowProtection_CodeSignature.h>
28 #elif defined(MCUX_CSSL_FP_USE_SECURE_COUNTER) \
29  && (1 == MCUX_CSSL_FP_USE_SECURE_COUNTER)
30 # include <mcuxCsslSecureCounter_Cfg.h>
31 # include <mcuxCsslFlowProtection_SecureCounter_Common.h>
32 # if defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL)
33 # include <mcuxCsslFlowProtection_SecureCounter_Local.h>
34 # else
35 # include <mcuxCsslFlowProtection_SecureCounter_Global.h>
36 # endif
37 #elif defined(MCUX_CSSL_FP_USE_NONE) && (1 == MCUX_CSSL_FP_USE_NONE)
38 # include <mcuxCsslFlowProtection_None.h>
39 #else
40 # error "No flow protection implementation found/configured."
41 #endif
42 
43 #endif /* MCUX_CSSL_FLOW_PROTECTION_IMPL_H_ */
mcuxCsslSecureCounter_Cfg.h
Configuration of the implementation for the secure counter mechanism.
+
mcuxCsslFlowProtection_SecureCounter_Local.h
Counter based implementation for the flow protection mechanism, for a local security counter.
+
mcuxCsslFlowProtection_SecureCounter_Common.h
Counter based implementation for the flow protection mechanism, for a local security counter.
+
mcuxCsslFlowProtection_Cfg.h
Configuration of the implementation for the flow protection mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00611.html b/components/els_pkc/doc/mcxn/html/a00611.html new file mode 100644 index 000000000..dd43da1fa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00611.html @@ -0,0 +1,386 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_SecureCounter_Common.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslFlowProtection_SecureCounter_Common.h File Reference
+
+
+ +

Counter based implementation for the flow protection mechanism, for a local security counter. +More...

+
#include <mcuxCsslCPreProcessor.h>
+#include <mcuxCsslAnalysis.h>
+#include <mcuxCsslSecureCounter.h>
+#include <stdint.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_DECL_NAME(type, id)
 Construct a name based on type and id. More...
 
#define MCUX_CSSL_FP_DECL_IMPL(type, id)
 Generic flow protected entity declaration implementation. More...
 
#define MCUX_CSSL_FP_ID_IMPL()
 Generic identifier generator based on current line number. More...
 
#define MCUX_CSSL_FP_EXPECTATIONS(...)
 Expectation aggregation. More...
 
+#define MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement)
 
#define MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, ...)
 Conditional expectation aggregation. More...
 
#define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()
 Implementation of expectation of nothingThis expectation macro indicates to the flow protection mechanism that nothing is expected to happen. More...
 
#define MCUX_CSSL_FP_EXPECT_IMPL(...)
 Declaration(s) of expected code flow behavior. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID(id)
 Generator for function identifiers. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK
 Mask to be used to derive entry part from a function identifier. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id)
 Part of the function identifier to be used at function entry. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id)
 Part of the function identifier to be used at function exit. More...
 
#define MCUX_CSSL_FP_FUNCTION_DECL_IMPL(...)
 Declaration implementation of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_VALUE(id)
 Macro to get the value for a given function. More...
 
#define MCUX_CSSL_FP_FUNCTION_DEF_IMPL(...)
 Definition implementation of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition)
 Definition implementation of a flow protected function pointer. More...
 
#define MCUX_CSSL_FP_RESULT_OFFSET
 Offset of the result in the return value. More...
 
#define MCUX_CSSL_FP_RESULT_MASK
 Bitmask of the result in the return value. More...
 
#define MCUX_CSSL_FP_RESULT_VALUE(result)
 Encode a result value for a protected return value. More...
 
#define MCUX_CSSL_FP_RESULT_IMPL(return)
 Extract the result value from a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_OFFSET
 Offset of the protection token in the return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_MASK
 Bitmask of the protection token in the return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(token)
 Encode a protection token for a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return)
 Extract the protection token value from a protected return value. More...
 
#define MCUX_CSSL_FP_COUNTER_COMPRESSED()
 Compressed version of the secure counter that can be used as a protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(id)
 Expectation implementation of a called function. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id)
 Expectation implementation of an entered (but not exited) function. More...
 
#define MCUX_CSSL_FP_LOOP_ID(id)
 Generator for loop identifiers. More...
 
#define MCUX_CSSL_FP_LOOP_DECL_IMPL(id)
 Declaration implementation of a flow protected loop. More...
 
#define MCUX_CSSL_FP_LOOP_VALUE(id)
 Macro to get the value for a given loop. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, ...)
 Event implementation of a loop iteration (with expectations). More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1(id)
 Event implementation of a loop iteration (without expectations). More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL(...)
 Event implementation of a loop iteration. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count)
 Expectation implementation of a number of loop iterations. More...
 
#define MCUX_CSSL_FP_BRANCH_ID(id)
 Generator for branch identifiers. More...
 
#define MCUX_CSSL_FP_BRANCH_DECL_IMPL(id)
 Declaration implementation of a flow protected branch. More...
 
#define MCUX_CSSL_FP_BRANCH_VALUE(id)
 Macro to get the value for a given branch. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE
 Value to use for the positive scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE
 Value to use for the negative scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, scenario, ...)
 Event implementation for the execution of a specified branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn(id, ...)
 Event implementation for the execution of a positive branch scenario (with expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1(id)
 Event implementation for the execution of a positive branch scenario (without expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(...)
 Event implementation for the execution of a positive branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn(id, ...)
 Event implementation for the execution of a negative branch scenario (with expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1(id)
 Event implementation for the execution of a negative branch scenario (without expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(...)
 Event implementation for the execution of a negative branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, scenario, condition)
 Expectation implementation of an executed specified branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2(id, condition)
 Expectation implementation of an executed positive branch (with condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1(id)
 Expectation implementation of an executed positive branch (without condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(...)
 Expectation implementation of an executed positive branch. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2(id, condition)
 Expectation implementation of an executed negative branch (with condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1(id)
 Expectation implementation of an executed negative branch (without condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(...)
 Expectation implementation of an executed negative branch. More...
 
#define MCUX_CSSL_FP_SWITCH_ID(id)
 Generator for switch identifiers. More...
 
#define MCUX_CSSL_FP_SWITCH_DECL_IMPL(id)
 Declaration implementation of a flow protected switch. More...
 
#define MCUX_CSSL_FP_SWITCH_VALUE(id)
 Macro to get the value for a given switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, ...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL2(id, case)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE
 Value to use for default case. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, ...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1(id)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, condition)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2(id, case)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(...)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, condition)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1(id)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(...)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_ASSERT_CALLBACK()
 Fallback assert callback implementation. More...
 
+

Detailed Description

+

Counter based implementation for the flow protection mechanism, for a local security counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_FUNCTION_POINTER_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_POINTER_IMPL( type,
 definition 
)
+
+ +

Definition implementation of a flow protected function pointer.

+
Parameters
+ + + +
typeIdentifier for the function pointer type that is flow protected.
definitionActual type definition of the function pointer type.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00611.js b/components/els_pkc/doc/mcxn/html/a00611.js new file mode 100644 index 000000000..2c85c0fe0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00611.js @@ -0,0 +1,73 @@ +var a00611 = +[ + [ "MCUX_CSSL_FP_DECL_NAME", "a00879.html#ga116350fa9fa1a37d3fca3d3a15f010f3", null ], + [ "MCUX_CSSL_FP_DECL_IMPL", "a00879.html#gab0919c85280cbf0aa51daaec18cb524a", null ], + [ "MCUX_CSSL_FP_ID_IMPL", "a00879.html#ga6bc8b7f3f35325ca98c1b5d0f7658061", null ], + [ "MCUX_CSSL_FP_EXPECTATIONS", "a00880.html#ga173c3887e1d02b5cace9e622d0a3225b", null ], + [ "MCUX_CSSL_FP_COUNTER_STMT_IMPL", "a00611.html#a206162408638fe12dc1d021fa3cb8ad5", null ], + [ "MCUX_CSSL_FP_CONDITIONAL_IMPL", "a00879.html#ga643cc00e2fecb3e73de572797618ad35", null ], + [ "MCUX_CSSL_FP_VOID_EXPECTATION_IMPL", "a00880.html#ga4ea20ab3d4d080887fdfc12f6c7f6bab", null ], + [ "MCUX_CSSL_FP_EXPECT_IMPL", "a00880.html#ga7be0ed334bcf634f81d5d4b93a4c1657", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID", "a00881.html#ga479eda7e7852481c11efbc1959aee5ab", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK", "a00881.html#gaaee8a28145962c5b60693126fb43f577", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART", "a00881.html#gafee5e352ad736687d3b51475705cb7e3", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART", "a00881.html#ga0b9936d950500136323df9b790a53cbf", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL_IMPL", "a00881.html#gad18deaf144ed415268a00f1634552e22", null ], + [ "MCUX_CSSL_FP_FUNCTION_VALUE", "a00881.html#gad9e9dfa4b8b661a90fca8a8348d85797", null ], + [ "MCUX_CSSL_FP_FUNCTION_DEF_IMPL", "a00881.html#gae834db0dba75df2b3f18e773b6f054b8", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER_IMPL", "a00611.html#a7d3ca21c8f547090d91d2d2b77607f45", null ], + [ "MCUX_CSSL_FP_RESULT_OFFSET", "a00881.html#ga7ec1aab92504892fe1f18c2890298b21", null ], + [ "MCUX_CSSL_FP_RESULT_MASK", "a00881.html#ga841d36aa501a694ec13c5f1cc0c55d18", null ], + [ "MCUX_CSSL_FP_RESULT_VALUE", "a00881.html#ga8fa4f755ce171f2497d143b627478aa8", null ], + [ "MCUX_CSSL_FP_RESULT_IMPL", "a00881.html#ga2464ae5055d514ca07dfd0a912d66233", null ], + [ "MCUX_CSSL_FP_PROTECTION_OFFSET", "a00881.html#ga4e64bd8d03d3e33458ee8a7fccb37c45", null ], + [ "MCUX_CSSL_FP_PROTECTION_MASK", "a00881.html#ga8778012875929ec230fcfdf10ff9500f", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE", "a00881.html#gaeba1f8f690177515b77e499d9d99b4e3", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL", "a00881.html#ga5da930d2d73279d4361af98b96771185", null ], + [ "MCUX_CSSL_FP_COUNTER_COMPRESSED", "a00881.html#ga2aa4e71591c9e48638a5733885a77972", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALLED_IMPL", "a00881.html#ga387940e23bd51390165c5cdffe5b2e6e", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL", "a00881.html#gaaf3937045ab2420f95b209d63d380b0e", null ], + [ "MCUX_CSSL_FP_LOOP_ID", "a00882.html#ga995fa3b11e4cc00e87135ada7aef8d5e", null ], + [ "MCUX_CSSL_FP_LOOP_DECL_IMPL", "a00882.html#gaf96c3a513125fcf430cbf3b5fe595e4f", null ], + [ "MCUX_CSSL_FP_LOOP_VALUE", "a00882.html#ga7eef9d81d7343fd127b4b05c14944d1c", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPLn", "a00882.html#ga60705dcec1d1ad92e356e66725d3bf3e", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPL1", "a00882.html#ga4c1cfe8ca5990c4c17f5193bcfe0df7e", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPL", "a00882.html#ga5d124a3ac8175c17ef669fde72edb64f", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL", "a00882.html#gaae28d69224446d35fe5e09fcde65a16b", null ], + [ "MCUX_CSSL_FP_BRANCH_ID", "a00883.html#ga0cd46ecad6c5ab6ef4ba6ff18a79b1eb", null ], + [ "MCUX_CSSL_FP_BRANCH_DECL_IMPL", "a00883.html#gaf4e4c76c10150fa1b5e8944f33720c44", null ], + [ "MCUX_CSSL_FP_BRANCH_VALUE", "a00883.html#ga24770b08dbac22e0ca123f737f9710b3", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE", "a00883.html#gafd8b6619c2105004d85eee8581c4969c", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE", "a00883.html#ga82df96ef3fb0b8718bff46f3f4cd9a5c", null ], + [ "MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL", "a00883.html#gab65273365a2139c4e6693664c8dc7e36", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn", "a00883.html#ga3232cfdb56c441fe5c6a914e38528494", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1", "a00883.html#ga54981abcad9da3f0d9a347ec3d0d2953", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL", "a00883.html#gadff057603f2018ef9440b0e981353a48", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn", "a00883.html#ga49e07e6c9d6faf768cd464d4cdb4a881", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1", "a00883.html#ga8547d895809dfb59bf0709fbc49e5483", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL", "a00883.html#gaf7f462f39963033ea44c0f7c7f41a76f", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_IMPL", "a00883.html#ga640bbb8417eb2e2fd975431d15a9364d", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2", "a00883.html#ga8a3b0d047ea142e74e5bef729508f683", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1", "a00883.html#ga29b42c7c0d701dc98159e7e04aafcd93", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL", "a00883.html#gaae07d1c658effb2daa3df7a75214b0f1", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2", "a00883.html#gae5068ae5b0a47a9d366e832f255e9ce9", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1", "a00883.html#gaff88c9879207f5f1d7ab643fdd9c278f", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL", "a00883.html#ga2142ecf918cf320bf1b15b8d8cfe5253", null ], + [ "MCUX_CSSL_FP_SWITCH_ID", "a00884.html#gaf1c0885504f90cfa3da18399d96b1319", null ], + [ "MCUX_CSSL_FP_SWITCH_DECL_IMPL", "a00884.html#ga685b8b131aa17d9a2fbb215cf282e47e", null ], + [ "MCUX_CSSL_FP_SWITCH_VALUE", "a00884.html#ga60aebfce23f0dc04ef9035404526a049", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPLn", "a00884.html#ga5f9c86c89dde886bc8a4d0685c193b35", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPL2", "a00884.html#ga7228ed734302bc58312a7f120f437ea4", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPL", "a00884.html#ga4fac747213aeed1e92363a2bdd68406b", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE", "a00884.html#ga3c29758b5fe14aacedaebdf5a77a2a24", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn", "a00884.html#gac3dcce63f39b86956e2535b5277781e7", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1", "a00884.html#gaf7458c44a5c0237192b047645b9fef44", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL", "a00884.html#gade7e9242949c3b56a6c26d4f9baa4184", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3", "a00884.html#gae6c4eb02ea889928868e6eae6d4fac9e", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2", "a00884.html#ga74061d2cc9faf009465c92cf7fa2806f", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL", "a00884.html#ga2cea4b8acd163c7b4877267c4221a9d4", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2", "a00884.html#gaf4a47979ed6e58b347658038ed393210", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1", "a00884.html#gaef7299bb6aa7dc7a367edae023cc2a41", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL", "a00884.html#gadd39e2b4cb02e9c849a289302465a8ff", null ], + [ "MCUX_CSSL_FP_ASSERT_CALLBACK", "a00880.html#ga0c29c395a9104c6d918091b12f63ca74", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00611_source.html b/components/els_pkc/doc/mcxn/html/a00611_source.html new file mode 100644 index 000000000..fa0201fcf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00611_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_SecureCounter_Common.h Source File + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_SecureCounter_Common.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_
20 #define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_
21 
22 /* Include the CSSL C pre-processor support functionality. */
23 #include <mcuxCsslCPreProcessor.h>
24 #include <mcuxCsslAnalysis.h>
25 
26 /* Include the CSSL secure counter mechanism as basic building block. */
27 #include <mcuxCsslSecureCounter.h>
28 
29 /* Include the C99 standard integer types. */
30 #include <stdint.h>
31 
63 #define MCUX_CSSL_FP_DECL_NAME(type, id) \
64  MCUX_CSSL_CPP_CAT4(mcuxCsslFlowProtection_, type, _, id)
65 
75 #define MCUX_CSSL_FP_DECL_IMPL(type, id) \
76  MCUX_CSSL_SC_VALUE_TYPE MCUX_CSSL_FP_DECL_NAME(type, id) = \
77  MCUX_CSSL_CPP_CAT3(MCUX_CSSL_FP_, type, _ID)(id)
78 
86 #define MCUX_CSSL_FP_ID_IMPL() \
87  MCUX_CSSL_CPP_CAT(__LINE__, u)
88 
89 
90 
106 #define MCUX_CSSL_FP_EXPECTATIONS(...) \
107  ((uint32_t) 0u + (MCUX_CSSL_CPP_MAP(MCUX_CSSL_CPP_ADD, __VA_ARGS__)))
108 
121 #define MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement) \
122  statement
123 
135 #define MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, ...) \
136  (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) & ((condition) ? ((uint32_t) UINT32_MAX) : ((uint32_t) 0)))
137 
148 #define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL() \
149  (0u)
150 
164 #define MCUX_CSSL_FP_EXPECT_IMPL(...) \
165  MCUX_CSSL_SC_SUB( \
166  MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
167  )
168 
169 
170 
188 #define MCUX_CSSL_FP_FUNCTION_ID(id) \
189  MCUX_CSSL_CPP_CAT(MCUX_CSSL_FP_FUNCID_, id)
190 
196 #define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK \
197  (0x5A5A5A5Au)
198 
206 #define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id) \
207  (MCUX_CSSL_FP_FUNCTION_VALUE(id) & MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK)
208 
216 #define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
217  (MCUX_CSSL_FP_FUNCTION_VALUE(id) - MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id))
218 
230 #define MCUX_CSSL_FP_FUNCTION_DECL_IMPL(...) \
231  /* Intentionally empty */
232 
241 #define MCUX_CSSL_FP_FUNCTION_VALUE(id) \
242  ((uint32_t) MCUX_CSSL_FP_FUNCTION_ID(id))
243 
254 #define MCUX_CSSL_FP_FUNCTION_DEF_IMPL(...) \
255  /* Intentionally empty. */
256 
265 #define MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition) \
266  definition
267 
273 #define MCUX_CSSL_FP_RESULT_OFFSET \
274  (0u)
275 
281 #define MCUX_CSSL_FP_RESULT_MASK \
282  (0xFFFFFFFFuLL)
283 
291 #define MCUX_CSSL_FP_RESULT_VALUE(result) \
292  (((uint64_t)(result) & MCUX_CSSL_FP_RESULT_MASK) << MCUX_CSSL_FP_RESULT_OFFSET)
293 
301 #define MCUX_CSSL_FP_RESULT_IMPL(return) \
302  (uint32_t)(((return) >> MCUX_CSSL_FP_RESULT_OFFSET) & MCUX_CSSL_FP_RESULT_MASK)
303 
309 #define MCUX_CSSL_FP_PROTECTION_OFFSET \
310  (32u)
311 
317 #define MCUX_CSSL_FP_PROTECTION_MASK \
318  ((uint64_t) 0xFFFFFFFFuLL)
319 
330 #define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(token) \
331  ((((uint64_t)(token) & MCUX_CSSL_FP_PROTECTION_MASK)) << MCUX_CSSL_FP_PROTECTION_OFFSET)
332 
343 #define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return) \
344  (uint32_t)(((return) >> MCUX_CSSL_FP_PROTECTION_OFFSET) & MCUX_CSSL_FP_PROTECTION_MASK)
345 
352 #define MCUX_CSSL_FP_COUNTER_COMPRESSED() \
353  MCUX_CSSL_SC_VALUE()
354 
355 
369 #define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(id) \
370  MCUX_CSSL_FP_FUNCTION_VALUE(id)
371 
372 
386 #define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id) \
387  MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id)
388 
389 
408 #define MCUX_CSSL_FP_LOOP_ID(id) \
409  MCUX_CSSL_FP_ID_IMPL()
410 
418 #define MCUX_CSSL_FP_LOOP_DECL_IMPL(id) \
419  MCUX_CSSL_FP_DECL_IMPL(LOOP, id)
420 
429 #define MCUX_CSSL_FP_LOOP_VALUE(id) \
430  MCUX_CSSL_FP_DECL_NAME(LOOP, id)
431 
443 #define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, ...) \
444  MCUX_CSSL_SC_ADD( \
445  MCUX_CSSL_FP_LOOP_VALUE(id) \
446  - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
447  )
448 
459 #define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1(id) \
460  MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, 0u)
461 
476 #define MCUX_CSSL_FP_LOOP_ITERATION_IMPL(...) \
477  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_LOOP_ITERATION_IMPL, __VA_ARGS__)
478 
487 #define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count) \
488  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
489  ((count) * MCUX_CSSL_FP_LOOP_VALUE(id)) \
490  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
491 
492 
493 
512 #define MCUX_CSSL_FP_BRANCH_ID(id) \
513  MCUX_CSSL_FP_ID_IMPL()
514 
522 #define MCUX_CSSL_FP_BRANCH_DECL_IMPL(id) \
523  MCUX_CSSL_FP_DECL_IMPL(BRANCH, id)
524 
533 #define MCUX_CSSL_FP_BRANCH_VALUE(id) \
534  MCUX_CSSL_FP_DECL_NAME(BRANCH, id)
535 
541 #define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE 0x5u
542 
548 #define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE 0xAu
549 
564 #define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, scenario, ...) \
565  MCUX_CSSL_SC_ADD( \
566  (MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \
567  - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
568  )
569 
584 #define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn(id, ...) \
585  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, \
586  __VA_ARGS__)
587 
600 #define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1(id) \
601  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, 0u)
602 
618 #define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(...) \
619  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL, __VA_ARGS__)
620 
635 #define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn(id, ...) \
636  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, \
637  __VA_ARGS__)
638 
651 #define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1(id) \
652  MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, 0u)
653 
669 #define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(...) \
670  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL, __VA_ARGS__)
671 
684 #define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, scenario, condition) \
685  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
686  MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \
687  MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \
688  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
689 
702 #define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2(id, condition) \
703  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, condition)
704 
716 #define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1(id) \
717  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
718  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
719  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, true) \
720  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
721  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
722 
736 #define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(...) \
737  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL, __VA_ARGS__)
738 
751 #define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2(id, condition) \
752  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, condition)
753 
765 #define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1(id) \
766  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
767  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
768  MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, true) \
769  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
770  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
771 
785 #define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(...) \
786  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL, __VA_ARGS__)
787 
788 
789 
808 #define MCUX_CSSL_FP_SWITCH_ID(id) \
809  MCUX_CSSL_FP_ID_IMPL()
810 
818 #define MCUX_CSSL_FP_SWITCH_DECL_IMPL(id) \
819  MCUX_CSSL_FP_DECL_IMPL(SWITCH, id)
820 
829 #define MCUX_CSSL_FP_SWITCH_VALUE(id) \
830  MCUX_CSSL_FP_DECL_NAME(SWITCH, id)
831 
845 #define MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, ...) \
846  MCUX_CSSL_SC_ADD( \
847  (MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \
848  - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
849  )
850 
862 #define MCUX_CSSL_FP_SWITCH_CASE_IMPL2(id, case) \
863  MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, 0u)
864 
880 #define MCUX_CSSL_FP_SWITCH_CASE_IMPL(...) \
881  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_CASE_IMPL, __VA_ARGS__)
882 
888 #define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE \
889  (0xDEFAu)
890 
903 #define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, ...) \
904  MCUX_CSSL_FP_SWITCH_CASE_IMPLn( \
905  id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, __VA_ARGS__)
906 
917 #define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1(id) \
918  MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, 0u) \
919 
920 
934 #define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(...) \
935  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL, __VA_ARGS__)
936 
950 #define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, condition) \
951  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
952  MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \
953  MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \
954  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
955 
967 #define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2(id, case) \
968  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
969  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
970  MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, true) \
971  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
972  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
973 
989 #define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(...) \
990  MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_SWITCH_TAKEN_IMPL, __VA_ARGS__)
991 
1003 #define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, condition) \
1004  MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, condition)
1005 
1016 #define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1(id) \
1017  MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \
1018  MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \
1019  MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, true) \
1020  MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \
1021  MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8)
1022 
1036 #define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(...) \
1037  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL, __VA_ARGS__)
1038 
1056 #ifndef MCUX_CSSL_FP_ASSERT_CALLBACK
1057  #define MCUX_CSSL_FP_ASSERT_CALLBACK() \
1058  return 1/0 /* Fallback ASSERT callback is used, please provide your own. */
1059 #endif
1060 
1061 #endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_ */
mcuxCsslCPreProcessor.h
The default implementation is based on standard C preprocessor functionality.
+
mcuxCsslSecureCounter.h
Provides the API for the CSSL secure counter mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00614.html b/components/els_pkc/doc/mcxn/html/a00614.html new file mode 100644 index 000000000..750b22083 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00614.html @@ -0,0 +1,236 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_SecureCounter_Local.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+ +
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+
+ +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslFlowProtection_SecureCounter_Local.h File Reference
+
+
+ +

Counter based implementation for the flow protection mechanism, for a local security counter. +More...

+
#include <mcuxCsslCPreProcessor.h>
+#include <mcuxCsslSecureCounter.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType)
 Based on a given base type, builds a return type with flow protection. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, ...)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1(function)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(...)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, ...)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1(id)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2(id, result)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(...)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, ...)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3(id, pass, fail)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(...)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1(id)
 Flow protection handler for the exit point of functions with the return type void. More...
 
+#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPLn(id, ...)
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(...)
 Flow protection handler for the exit point of functions with the return type void. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL(result, call)
 Event implementation of a flow protected function call. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(call)
 Event implementation of a flow protected void function call. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call)
 Implementation of a flow protected function call meant to be used from within an unprotected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call)
 Implementation of a flow protected void function call meant to be used from within an unprotected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(result, token, call)
 Implementation of a flow protected function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL()
 Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(token, call)
 Implementation of a flow protected void function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL()
 Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL. More...
 
#define MCUX_CSSL_FP_ASSERT_IMPL(...)
 Assert an expected state of the code flow. More...
 
+

Detailed Description

+

Counter based implementation for the flow protection mechanism, for a local security counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL( call)
+
+ +

Event implementation of a flow protected void function call.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+
Parameters
+ + +
callThe (protected) function call that must be performed.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00614.js b/components/els_pkc/doc/mcxn/html/a00614.js new file mode 100644 index 000000000..6ab83fcac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00614.js @@ -0,0 +1,26 @@ +var a00614 = +[ + [ "MCUX_CSSL_FP_PROTECTED_TYPE_IMPL", "a00881.html#ga8c5845ea3e1b932b969db83484b26ecf", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn", "a00881.html#ga1a8ea6cc710859bcadb79a488dd8db25", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1", "a00881.html#gab4ce00a3b45306924fe9b0b6664bde0a", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL", "a00881.html#gade96ac1fafaf20164fda6e40ec29b111", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn", "a00881.html#gadff771aa8e6ddffa0943c1e05d143d3b", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1", "a00881.html#gafbffa86482e7c82632c29b7b47268cc0", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2", "a00881.html#ga9c6252af0f1985853ed349c5d1ae1788", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL", "a00881.html#gaa04b0a2008a71b07057236083492ff59", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn", "a00881.html#ga98f3eec493dd7bf7b26f064c31302c73", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3", "a00881.html#gad1f605647ff376aba41b2362d8d02def", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL", "a00881.html#ga03a6226c405fe4012598d538b751d8e0", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1", "a00881.html#ga7d4f6f29ec46da78d39c6835c2353c43", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPLn", "a00614.html#a383ad2c7cc236f1956892a325bce1c06", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL", "a00881.html#gada3bd3043e47a7155cbd6f48a19d8a7b", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_IMPL", "a00881.html#ga6dea11ddfc9ee7a58fd4c002bd2aa298", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL", "a00614.html#aac90557cb39d20ea0c0fda3985497b45", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL", "a00881.html#gacf0993520e666067ce074749c90e3d84", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL", "a00881.html#gadc1544cfd424c8ea5e09a97a6b48defa", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL", "a00881.html#gab0ff0e165d943faba9241de4f57c2d75", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL", "a00881.html#ga260f6caaf5d3f526e664835f6889fec5", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL", "a00881.html#ga8f9fbedb24cf72ef01632cc7a2df1f91", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL", "a00881.html#gae44806e59bfa6e136c7df9c641809621", null ], + [ "MCUX_CSSL_FP_ASSERT_IMPL", "a00880.html#ga391e0f29868a1dd17bd0d23a4737c129", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00614_source.html b/components/els_pkc/doc/mcxn/html/a00614_source.html new file mode 100644 index 000000000..6599f9c1a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00614_source.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: mcuxCsslFlowProtection_SecureCounter_Local.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslFlowProtection_SecureCounter_Local.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_
20 #define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_
21 
22 /* Include the CSSL C pre-processor support functionality. */
23 #include <mcuxCsslCPreProcessor.h>
24 
25 /* Include the CSSL secure counter mechanism as basic building block. */
26 #include <mcuxCsslSecureCounter.h>
27 
28 /* Include the C99 standard integer types. */
29 #include <stdint.h>
30 
31 /* Include standard boolean types */
32 #include <stdbool.h>
33 
34 
45 #define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType) \
46  uint64_t
47 
62 #define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, ...) \
63  MCUX_CSSL_SC_INIT( \
64  MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(function) \
65  - (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__)) \
66  )
67 
80 #define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1(function) \
81  MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, 0u)
82 
100 #define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(...) \
101  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL, __VA_ARGS__)
102 
103 
122 #define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, ...) \
123  MCUX_CSSL_SC_ADD( \
124  MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
125  - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
126  ); \
127  return (MCUX_CSSL_FP_RESULT_VALUE(result) \
128  | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED()))
129 
144 #define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1(id) \
145  MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, 0u, 0u)
146 
163 #define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2(id, result) \
164  MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, 0u)
165 
188 #define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(...) \
189  MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_FUNCTION_EXIT_IMPL, __VA_ARGS__)
190 
216 #define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, ...) \
217  MCUX_CSSL_SC_ADD( \
218  MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \
219  - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \
220  ); \
221  return (MCUX_CSSL_FP_RESULT_VALUE( \
222  (MCUX_CSSL_SC_CHECK_PASSED == \
223  MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_FUNCTION_VALUE(id))) \
224  ? pass : fail) \
225  | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED()))
226 
248 #define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3(id, pass, fail) \
249  MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, 0u)
250 
278 #define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(...) \
279  MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL, __VA_ARGS__)
280 
290 #define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1(id) \
291  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U)
292 
304 #define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPLn(id, ...) \
305  MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U, __VA_ARGS__)
306 
318 #define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(...) \
319  MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL, __VA_ARGS__)
320 
333 #define MCUX_CSSL_FP_FUNCTION_CALL_IMPL(result, call) \
334  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
335  MCUX_CSSL_SC_ADD_ON_CALL( \
336  MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \
337  const uint32_t result = MCUX_CSSL_FP_RESULT( \
338  MCUX_CSSL_CPP_CAT(result, _protected))
339 
350 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(call) \
351  { \
352  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
353  MCUX_CSSL_SC_ADD_ON_CALL( \
354  MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \
355  }
356 
368 #define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call) \
369  const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \
370  const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \
371  MCUX_CSSL_CPP_CAT(result, _protected)); \
372  const uint32_t result = MCUX_CSSL_FP_RESULT( \
373  MCUX_CSSL_CPP_CAT(result, _protected))
374 
385 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call) \
386  const uint64_t MCUX_CSSL_CPP_CAT(token, _protected) = (call); \
387  const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \
388  MCUX_CSSL_CPP_CAT(token, _protected));
389 
402 #define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(result, token, call) \
403 do \
404 { \
405  MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call)
406 
413 #define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL() \
414 } while (false)
415 
427 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(token, call) \
428 do \
429 { \
430  MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call)
431 
438 #define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL() \
439 } while (false)
440 
461 #define MCUX_CSSL_FP_ASSERT_IMPL(...) \
462  if (MCUX_CSSL_SC_CHECK_PASSED != \
463  MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \
464  { \
465  MCUX_CSSL_FP_ASSERT_CALLBACK(); \
466  } \
467  else if (MCUX_CSSL_SC_CHECK_PASSED != \
468  MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \
469  { \
470  MCUX_CSSL_FP_ASSERT_CALLBACK(); \
471  } \
472  else {/*empty*/}
473 
474 #endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_ */
mcuxCsslCPreProcessor.h
The default implementation is based on standard C preprocessor functionality.
+
mcuxCsslSecureCounter.h
Provides the API for the CSSL secure counter mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00617.html b/components/els_pkc/doc/mcxn/html/a00617.html new file mode 100644 index 000000000..6c07165fa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00617.html @@ -0,0 +1,133 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslMemory.h File Reference
+
+
+ +

Top-level include file for the CSSL memory functions. +More...

+
#include <mcuxCsslMemory_Types.h>
+#include <mcuxCsslMemory_Compare.h>
+#include <mcuxCsslMemory_Clear.h>
+#include <mcuxCsslMemory_Copy.h>
+#include <mcuxCsslMemory_Set.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Top-level include file for the CSSL memory functions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00617_source.html b/components/els_pkc/doc/mcxn/html/a00617_source.html new file mode 100644 index 000000000..841c755b7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00617_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslMemory.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLMEMORY_H
20 #define MCUXCSSLMEMORY_H
21 
28 #include <mcuxCsslMemory_Types.h>
29 
30 
31 #include <mcuxCsslMemory_Compare.h>
32 
33 #include <mcuxCsslMemory_Clear.h>
34 
35 #include <mcuxCsslMemory_Copy.h>
36 
37 #include <mcuxCsslMemory_Set.h>
38 
39 
40 #endif
mcuxCsslMemory_Compare.h
Include file for constant time memory compare function.
+
mcuxCsslMemory_Copy.h
Include file for memory copy function.
+
mcuxCsslMemory_Set.h
header file of memory set function
+
mcuxCsslMemory_Types.h
Type definitions for the mcuxCsslMemory component.
+
mcuxCsslMemory_Clear.h
header file of memory clear function
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00620.html b/components/els_pkc/doc/mcxn/html/a00620.html new file mode 100644 index 000000000..4090b7164 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00620.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Clear.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Functions
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+
mcuxCsslMemory_Clear.h File Reference
+
+
+ +

header file of memory clear function +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+

Go to the source code of this file.

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Clear (mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, size_t dstLength, size_t length)
 Clear length bytes of data at pDst. More...
 
+

Detailed Description

+

header file of memory clear function

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00620.js b/components/els_pkc/doc/mcxn/html/a00620.js new file mode 100644 index 000000000..c361f5a90 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00620.js @@ -0,0 +1,4 @@ +var a00620 = +[ + [ "mcuxCsslMemory_Clear", "a00887.html#gaea7d5f3c8d216e752f153827689e88c3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00620_source.html b/components/els_pkc/doc/mcxn/html/a00620_source.html new file mode 100644 index 000000000..f03378988 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00620_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Clear.h Source File + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
mcuxCsslMemory_Clear.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCSSLMEMORY_CLEAR_H_
21 #define MCUXCSSLMEMORY_CLEAR_H_
22 
23 #include <stdint.h>
24 #include <stddef.h>
25 #include <mcuxCsslFlowProtection.h>
26 #include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
27 #include <mcuxCsslParamIntegrity.h>
28 
63 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Clear)
64 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Clear
65 (
66  mcuxCsslParamIntegrity_Checksum_t chk,
67  void * pDst,
68  size_t dstLength,
69  size_t length
70 );
71 
80 #endif /* MCUXCSSLMEMORY_CLEAR_H_ */
mcuxCsslParamIntegrity.h
Top-level include file for the parameter integrity protection mechanism.
+
mcuxCsslMemory_Clear
mcuxCsslMemory_Status_t mcuxCsslMemory_Clear(mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, size_t dstLength, size_t length)
Clear length bytes of data at pDst.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxCsslParamIntegrity_Checksum_t
uint32_t mcuxCsslParamIntegrity_Checksum_t
Type of a parameter checksum.
Definition: mcuxCsslParamIntegrity.h:72
+
mcuxCsslFlowProtection_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCsslMemory_Status_t
uint32_t mcuxCsslMemory_Status_t
Type for CSSL Memory status codes.
Definition: mcuxCsslMemory_Types.h:67
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00623.html b/components/els_pkc/doc/mcxn/html/a00623.html new file mode 100644 index 000000000..bc0fc267c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00623.html @@ -0,0 +1,141 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Compare.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Functions
+
+
mcuxCsslMemory_Compare.h File Reference
+
+
+ +

Include file for constant time memory compare function. +More...

+
#include <stdint.h>
+#include <mcuxCsslParamIntegrity.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Compare (mcuxCsslParamIntegrity_Checksum_t chk, void const *pLhs, void const *pRhs, size_t length)
 Compares the two memory regions lhs and rhs. More...
 
+

Detailed Description

+

Include file for constant time memory compare function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00623.js b/components/els_pkc/doc/mcxn/html/a00623.js new file mode 100644 index 000000000..2fd89a070 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00623.js @@ -0,0 +1,4 @@ +var a00623 = +[ + [ "mcuxCsslMemory_Compare", "a00889.html#ga0a6695838853535250234994d7e4d5b1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00623_source.html b/components/els_pkc/doc/mcxn/html/a00623_source.html new file mode 100644 index 000000000..79a33d0ab --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00623_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Compare.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+ +
+
+
mcuxCsslMemory_Compare.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2022 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLMEMORY_COMPARE_H
20 #define MCUXCSSLMEMORY_COMPARE_H
21 
22 #include <stdint.h>
23 #include <mcuxCsslParamIntegrity.h>
24 #include <mcuxCsslFlowProtection.h>
25 #include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
26 
63 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Compare)
64 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Compare
65 (
66  mcuxCsslParamIntegrity_Checksum_t chk,
67  void const * pLhs,
68  void const * pRhs,
69  size_t length
70 );
71 
80 #endif
mcuxCsslMemory_Compare
mcuxCsslMemory_Status_t mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Checksum_t chk, void const *pLhs, void const *pRhs, size_t length)
Compares the two memory regions lhs and rhs.
+
mcuxCsslParamIntegrity.h
Top-level include file for the parameter integrity protection mechanism.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxCsslParamIntegrity_Checksum_t
uint32_t mcuxCsslParamIntegrity_Checksum_t
Type of a parameter checksum.
Definition: mcuxCsslParamIntegrity.h:72
+
mcuxCsslFlowProtection_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCsslMemory_Status_t
uint32_t mcuxCsslMemory_Status_t
Type for CSSL Memory status codes.
Definition: mcuxCsslMemory_Types.h:67
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00626.html b/components/els_pkc/doc/mcxn/html/a00626.html new file mode 100644 index 000000000..7afa677bc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00626.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Copy.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Functions
+
+
mcuxCsslMemory_Copy.h File Reference
+
+
+ +

Include file for memory copy function. +More...

+ +

Go to the source code of this file.

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Copy (mcuxCsslParamIntegrity_Checksum_t chk, void const *pSrc, void *pDst, size_t dstLength, size_t length)
 Copies length bytes of data from pSrc to pDst. More...
 
+

Detailed Description

+

Include file for memory copy function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00626.js b/components/els_pkc/doc/mcxn/html/a00626.js new file mode 100644 index 000000000..6a9a675ad --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00626.js @@ -0,0 +1,4 @@ +var a00626 = +[ + [ "mcuxCsslMemory_Copy", "a00891.html#gaa29b7e8d23c8d95ce248fc8e0a4b37c8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00626_source.html b/components/els_pkc/doc/mcxn/html/a00626_source.html new file mode 100644 index 000000000..ecee42626 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00626_source.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Copy.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxCsslMemory_Copy.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLMEMORY_COPY_H_
20 #define MCUXCSSLMEMORY_COPY_H_
21 
59 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Copy)
60 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Copy
61 (
62  mcuxCsslParamIntegrity_Checksum_t chk,
63  void const * pSrc,
64  void * pDst,
65  size_t dstLength,
66  size_t length
67 );
68 
77 #endif /* MCUXCSSLMEMORY_COPY_H_ */
mcuxCsslMemory_Copy
mcuxCsslMemory_Status_t mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Checksum_t chk, void const *pSrc, void *pDst, size_t dstLength, size_t length)
Copies length bytes of data from pSrc to pDst.
+
mcuxCsslParamIntegrity_Checksum_t
uint32_t mcuxCsslParamIntegrity_Checksum_t
Type of a parameter checksum.
Definition: mcuxCsslParamIntegrity.h:72
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCsslMemory_Status_t
uint32_t mcuxCsslMemory_Status_t
Type for CSSL Memory status codes.
Definition: mcuxCsslMemory_Types.h:67
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00629.html b/components/els_pkc/doc/mcxn/html/a00629.html new file mode 100644 index 000000000..48ff17b0f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00629.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Set.h File Reference + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Functions
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+
mcuxCsslMemory_Set.h File Reference
+
+
+ +

header file of memory set function +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+#include <mcuxCsslParamIntegrity.h>
+
+

Go to the source code of this file.

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Set (mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, uint8_t val, size_t length, size_t bufLength)
 Set length bytes of data at pDst. More...
 
+

Detailed Description

+

header file of memory set function

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00629.js b/components/els_pkc/doc/mcxn/html/a00629.js new file mode 100644 index 000000000..66df266d2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00629.js @@ -0,0 +1,4 @@ +var a00629 = +[ + [ "mcuxCsslMemory_Set", "a00893.html#ga0a0ed6d55e0cb4d633ba19a32aca64c6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00629_source.html b/components/els_pkc/doc/mcxn/html/a00629_source.html new file mode 100644 index 000000000..83b9d7e5c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00629_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Set.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
mcuxCsslMemory_Set.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021, 2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCSSLMEMORY_SET_H_
21 #define MCUXCSSLMEMORY_SET_H_
22 
23 #include <stdint.h>
24 #include <stddef.h>
25 #include <mcuxCsslFlowProtection.h>
26 #include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
27 #include <mcuxCsslParamIntegrity.h>
28 
64 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Set)
65 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Set
66 (
67  mcuxCsslParamIntegrity_Checksum_t chk,
68  void * pDst,
69  uint8_t val,
70  size_t length,
71  size_t bufLength
72 );
73 
82 #endif /* MCUXCSSLMEMORY_SET_H_ */
mcuxCsslParamIntegrity.h
Top-level include file for the parameter integrity protection mechanism.
+
mcuxCsslMemory_Set
mcuxCsslMemory_Status_t mcuxCsslMemory_Set(mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, uint8_t val, size_t length, size_t bufLength)
Set length bytes of data at pDst.
+
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxCsslParamIntegrity_Checksum_t
uint32_t mcuxCsslParamIntegrity_Checksum_t
Type of a parameter checksum.
Definition: mcuxCsslParamIntegrity.h:72
+
mcuxCsslFlowProtection_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
mcuxCsslMemory_Status_t
uint32_t mcuxCsslMemory_Status_t
Type for CSSL Memory status codes.
Definition: mcuxCsslMemory_Types.h:67
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00632.html b/components/els_pkc/doc/mcxn/html/a00632.html new file mode 100644 index 000000000..9d4086a6b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00632.html @@ -0,0 +1,163 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Types.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+Macros | +Typedefs
+
+
mcuxCsslMemory_Types.h File Reference
+
+
+ +

Type definitions for the mcuxCsslMemory component. +More...

+
#include <stdint.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCSSLMEMORY_STATUS_OK
 The operation was successful. More...
 
#define MCUXCSSLMEMORY_STATUS_EQUAL
 The two contents of the Memory Compare are equal. More...
 
#define MCUXCSSLMEMORY_STATUS_NOT_EQUAL
 The two contents of the Memory Compare are not equal. More...
 
#define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER
 A parameter was invalid. More...
 
#define MCUXCSSLMEMORY_STATUS_FAULT
 A fault occurred in the execution. More...
 
#define MCUXCSSLMEMORY_KEEP_ORDER
 Data storing in destination buffer in original order. More...
 
#define MCUXCSSLMEMORY_REVERSE_ORDER
 Data storing in destination buffer with reversed order. More...
 
+ + + + +

+Typedefs

typedef uint32_t mcuxCsslMemory_Status_t
 Type for CSSL Memory status codes. More...
 
+

Detailed Description

+

Type definitions for the mcuxCsslMemory component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00632.js b/components/els_pkc/doc/mcxn/html/a00632.js new file mode 100644 index 000000000..d1774b178 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00632.js @@ -0,0 +1,11 @@ +var a00632 = +[ + [ "MCUXCSSLMEMORY_STATUS_OK", "a00895.html#gab2993c75e7ef98fed36f03946630e41c", null ], + [ "MCUXCSSLMEMORY_STATUS_EQUAL", "a00895.html#gafaad4a560714fdff8064ba9a50f7d572", null ], + [ "MCUXCSSLMEMORY_STATUS_NOT_EQUAL", "a00895.html#ga2b5d2b24036bee244a9e7310160b3035", null ], + [ "MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER", "a00895.html#ga0e60adf6203cb3acb2bdb3ddec166766", null ], + [ "MCUXCSSLMEMORY_STATUS_FAULT", "a00895.html#gaf0923b98a5db9fd23732989986d72f4d", null ], + [ "MCUXCSSLMEMORY_KEEP_ORDER", "a00895.html#ga0072c925d0ab8c5b0b071abd1d5218af", null ], + [ "MCUXCSSLMEMORY_REVERSE_ORDER", "a00895.html#ga9c4cf10d8106eca9894d9e3b131b52f9", null ], + [ "mcuxCsslMemory_Status_t", "a00896.html#ga19c7a1367cb21d7bcb720607f495d86c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00632_source.html b/components/els_pkc/doc/mcxn/html/a00632_source.html new file mode 100644 index 000000000..16990213e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00632_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Types.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
mcuxCsslMemory_Types.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2021-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLMEMORY_TYPES_H
20 #define MCUXCSSLMEMORY_TYPES_H
21 
22 #include <stdint.h>
23 
31 /**********************************************
32  * CONSTANTS
33  **********************************************/
40 #define MCUXCSSLMEMORY_STATUS_OK ((mcuxCsslMemory_Status_t) 0xE1E11E1Eu)
41 #define MCUXCSSLMEMORY_STATUS_EQUAL ((mcuxCsslMemory_Status_t) 0xE1E1E1E1u)
42 #define MCUXCSSLMEMORY_STATUS_NOT_EQUAL ((mcuxCsslMemory_Status_t) 0x1E1E1E1Eu)
43 #define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER ((mcuxCsslMemory_Status_t) 0x69696969u)
44 #define MCUXCSSLMEMORY_STATUS_FAULT ((mcuxCsslMemory_Status_t) 0x96969696u)
45 
46 #define MCUXCSSLMEMORY_KEEP_ORDER ((uint32_t) 0xE1E139A5u)
47 #define MCUXCSSLMEMORY_REVERSE_ORDER ((uint32_t) 0xE1E1395Au)
48 
53 /**********************************************
54  * TYPEDEFS
55  **********************************************/
56 
67 typedef uint32_t mcuxCsslMemory_Status_t;
74 #endif /* MCUXCSSLMEMORY_TYPES_H */
mcuxCsslMemory_Status_t
uint32_t mcuxCsslMemory_Status_t
Type for CSSL Memory status codes.
Definition: mcuxCsslMemory_Types.h:67
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00635.html b/components/els_pkc/doc/mcxn/html/a00635.html new file mode 100644 index 000000000..52c0c1ec4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00635.html @@ -0,0 +1,174 @@ + + + + + + + +MCUX CLNS: mcuxCsslParamIntegrity.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros | +Typedefs | +Functions
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+
mcuxCsslParamIntegrity.h File Reference
+
+
+ +

Top-level include file for the parameter integrity protection mechanism. +More...

+
#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <mcuxCsslFlowProtection.h>
+#include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Macros

#define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM
 First eight hex digits of Eulers number. More...
 
#define MCUXCSSLPARAMINTEGRITY_CHECK_VALID
 Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was correct. More...
 
#define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID
 Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was incorrect. More...
 
+ + + + + + + +

+Typedefs

typedef void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u==sizeof(size_t)) ?(+1) :(-1)]
 Build time assertion to ensure CPU word size of 32 bit. More...
 
typedef uint32_t mcuxCsslParamIntegrity_Checksum_t
 Type of a parameter checksum. More...
 
+ + + + + + + +

+Functions

mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect (size_t nargs,...)
 Calculates a parameter checksum. More...
 
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Validate (mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs,...)
 Verifies the correctness of a parameter checksum. More...
 
+

Detailed Description

+

Top-level include file for the parameter integrity protection mechanism.

+

The library exposes the following functions:

    +
  1. +Generation of parameter checksums: mcuxCsslParamIntegrity_Protect
    2. +
  2. +Validation of parameter checksums: mcuxCsslParamIntegrity_Validate
    3. +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00635.js b/components/els_pkc/doc/mcxn/html/a00635.js new file mode 100644 index 000000000..77c28e864 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00635.js @@ -0,0 +1,10 @@ +var a00635 = +[ + [ "MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM", "a00898.html#ga53aac27cab05b855d2ae62f2b1d3d7d0", null ], + [ "MCUXCSSLPARAMINTEGRITY_CHECK_VALID", "a00898.html#gad7a460092fbe39b438614ba1d159bb16", null ], + [ "MCUXCSSLPARAMINTEGRITY_CHECK_INVALID", "a00898.html#ga889eda2d841537edae8f0f7d80dde8b0", null ], + [ "mcuxCsslParamIntegrity_AssertionCpuWordSize_t", "a00899.html#gaf2a8a66e39dd0d33d085d3d412cafb96", null ], + [ "mcuxCsslParamIntegrity_Checksum_t", "a00899.html#ga6a229130320b395fbb8a8a76a361bd1e", null ], + [ "mcuxCsslParamIntegrity_Protect", "a00900.html#gaaa2a9f40eb61dbe8ccce1b3b2dc824bb", null ], + [ "mcuxCsslParamIntegrity_Validate", "a00900.html#gaface23af4c626fe4adf70518056f2f33", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00635_source.html b/components/els_pkc/doc/mcxn/html/a00635_source.html new file mode 100644 index 000000000..4cc39f249 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00635_source.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxCsslParamIntegrity.h Source File + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslParamIntegrity.h
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2021 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
22 
23 #ifndef MCUXCSSLPARAMINTEGRITY_H
24 #define MCUXCSSLPARAMINTEGRITY_H
25 
26 #include <stdint.h>
27 #include <stddef.h>
28 #include <stdbool.h>
29 #include <mcuxCsslFlowProtection.h>
30 #include <mcuxCsslFlowProtection_FunctionIdentifiers.h>
31 
47 #define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM ((mcuxCsslParamIntegrity_Checksum_t)0xb7151628u)
48 
49 #define MCUXCSSLPARAMINTEGRITY_CHECK_VALID ((mcuxCsslParamIntegrity_Checksum_t)0x6969u)
50 
51 #define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID ((mcuxCsslParamIntegrity_Checksum_t)0x9696u)
52 
53 
67 typedef void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u == sizeof(size_t)) ? (+1) : (-1)];
68 
72 typedef uint32_t mcuxCsslParamIntegrity_Checksum_t;
73 
92 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Protect)
93 mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect(size_t nargs, ...);
94 
105 MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Validate)
106 MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslParamIntegrity_Checksum_t) mcuxCsslParamIntegrity_Validate(mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs, ...);
107 
116 #endif
mcuxCsslFlowProtection.h
Provides the API for the CSSL flow protection mechanism.
+
mcuxCsslParamIntegrity_Checksum_t
uint32_t mcuxCsslParamIntegrity_Checksum_t
Type of a parameter checksum.
Definition: mcuxCsslParamIntegrity.h:72
+
mcuxCsslParamIntegrity_Validate
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Validate(mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs,...)
Verifies the correctness of a parameter checksum.
+
mcuxCsslFlowProtection_FunctionIdentifiers.h
Definition of function identifiers for the flow protection mechanism.
+
mcuxCsslParamIntegrity_AssertionCpuWordSize_t
void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u==sizeof(size_t)) ?(+1) :(-1)]
Build time assertion to ensure CPU word size of 32 bit.
Definition: mcuxCsslParamIntegrity.h:67
+
MCUX_CSSL_FP_FUNCTION_DECL
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
Declaration of a flow protected function.
Definition: mcuxCsslFlowProtection.h:125
+
mcuxCsslParamIntegrity_Protect
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect(size_t nargs,...)
Calculates a parameter checksum.
+
MCUX_CSSL_FP_PROTECTED_TYPE
#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
Based on a given base type, builds a return type with flow protection.
Definition: mcuxCsslFlowProtection.h:81
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00638.html b/components/els_pkc/doc/mcxn/html/a00638.html new file mode 100644 index 000000000..7db776466 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00638.html @@ -0,0 +1,186 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter.h File Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
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+
mcuxCsslSecureCounter.h File Reference
+
+
+ +

Provides the API for the CSSL secure counter mechanism. +More...

+
#include <mcuxCsslSecureCounter_Impl.h>
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_CHECK_PASSED
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_ALLOC()
 Allocation operation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT(value)
 Initialization operation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK(reference)
 Comparison operation for the secure counter. More...
 
#define MCUX_CSSL_SC_ADD(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0x1()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0x10()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0x100()
 Increment the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_SUB(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0x1()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0x10()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0x100()
 Decrement the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_VALUE()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

Provides the API for the CSSL secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00638.js b/components/els_pkc/doc/mcxn/html/a00638.js new file mode 100644 index 000000000..15213058b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00638.js @@ -0,0 +1,20 @@ +var a00638 = +[ + [ "MCUX_CSSL_SC_CHECK_PASSED", "a00902.html#ga1f0a9fc2ca02b221c00acb56c1e93b9e", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED", "a00902.html#ga9c4c267ec8ea4df79b0f5affe471ee7b", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE", "a00902.html#ga614b8a54453d52240162efb2118db47f", null ], + [ "MCUX_CSSL_SC_ALLOC", "a00902.html#gae251628d245da18aa3c7aff92dbc8731", null ], + [ "MCUX_CSSL_SC_INIT", "a00902.html#ga25e2c92db2dee1b0cd339d3a8ca4112a", null ], + [ "MCUX_CSSL_SC_CHECK", "a00902.html#ga09971b594be3d77043145756712bd1bb", null ], + [ "MCUX_CSSL_SC_ADD", "a00903.html#gaebd375f1bd8786078a00d2d8326c23aa", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL", "a00903.html#ga4103d92fd5d240d12ace815c84d9d6f1", null ], + [ "MCUX_CSSL_SC_ADD_0x1", "a00903.html#gaca21d031efe80f6dd488932f0e335842", null ], + [ "MCUX_CSSL_SC_ADD_0x10", "a00903.html#gab6aafbee4e72e020907dc9f382ac6b65", null ], + [ "MCUX_CSSL_SC_ADD_0x100", "a00903.html#gaa7340bed15dc7026e9d2a0a9a1464cbf", null ], + [ "MCUX_CSSL_SC_SUB", "a00904.html#ga270e4467ff02a10df72b1da177385858", null ], + [ "MCUX_CSSL_SC_SUB_0x1", "a00904.html#ga7df8a7a4e7798142da2e668ca21f3a5e", null ], + [ "MCUX_CSSL_SC_SUB_0x10", "a00904.html#gabb6f649421ad8405aa47812615301933", null ], + [ "MCUX_CSSL_SC_SUB_0x100", "a00904.html#gacf7c177e9dbd78d8c5a81fe3b9b4b5cb", null ], + [ "MCUX_CSSL_SC_VALUE", "a00905.html#ga2b674477b2a4111ad89fd95598c36e69", null ], + [ "MCUX_CSSL_SC_ASSIGN", "a00905.html#ga019087e1fe72c9ef7b1e5f9e19aa7493", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00638_source.html b/components/els_pkc/doc/mcxn/html/a00638_source.html new file mode 100644 index 000000000..2762116d6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00638_source.html @@ -0,0 +1,122 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter.h Source File + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslSecureCounter.h
+
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+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLSECURECOUNTER_H_
20 #define MCUXCSSLSECURECOUNTER_H_
21 
22 /* Include the actual implementation of the secure counter mechanism. */
23 #include <mcuxCsslSecureCounter_Impl.h>
24 
42 /****************************************************************************/
43 /* Constants */
44 /****************************************************************************/
45 
52 #define MCUX_CSSL_SC_CHECK_PASSED \
53  MCUX_CSSL_SC_CHECK_PASSED_IMPL
54 
61 #define MCUX_CSSL_SC_CHECK_FAILED \
62  MCUX_CSSL_SC_CHECK_FAILED_IMPL
63 
70 #define MCUX_CSSL_SC_VALUE_TYPE \
71  MCUX_CSSL_SC_VALUE_TYPE_IMPL
72 
73 /****************************************************************************/
74 /* Initialization */
75 /****************************************************************************/
76 
83 #define MCUX_CSSL_SC_ALLOC() \
84  MCUX_CSSL_SC_ALLOC_IMPL()
85 
94 #define MCUX_CSSL_SC_INIT(value) \
95  MCUX_CSSL_SC_INIT_IMPL(value)
96 
97 /****************************************************************************/
98 /* Check */
99 /****************************************************************************/
100 
111 #define MCUX_CSSL_SC_CHECK(reference) \
112  MCUX_CSSL_SC_CHECK_IMPL(reference)
113 
114 /****************************************************************************/
115 /* Counter increment */
116 /****************************************************************************/
136 #define MCUX_CSSL_SC_ADD(value) \
137  MCUX_CSSL_SC_ADD_IMPL(value)
138 
149 #define MCUX_CSSL_SC_ADD_ON_CALL(value) \
150  MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
151 
163 #define MCUX_CSSL_SC_ADD_0x1() \
164  MCUX_CSSL_SC_ADD_0x1_IMPL()
165 
177 #define MCUX_CSSL_SC_ADD_0x10() \
178  MCUX_CSSL_SC_ADD_0x10_IMPL()
179 
191 #define MCUX_CSSL_SC_ADD_0x100() \
192  MCUX_CSSL_SC_ADD_0x100_IMPL()
193 
194 /****************************************************************************/
195 /* Counter decrement */
196 /****************************************************************************/
216 #define MCUX_CSSL_SC_SUB(value) \
217  MCUX_CSSL_SC_SUB_IMPL(value)
218 
230 #define MCUX_CSSL_SC_SUB_0x1() \
231  MCUX_CSSL_SC_SUB_0x1_IMPL()
232 
244 #define MCUX_CSSL_SC_SUB_0x10() \
245  MCUX_CSSL_SC_SUB_0x10_IMPL()
246 
258 #define MCUX_CSSL_SC_SUB_0x100() \
259  MCUX_CSSL_SC_SUB_0x100_IMPL()
260 
261 /****************************************************************************/
262 /* Direct access (optional) */
263 /****************************************************************************/
285 #define MCUX_CSSL_SC_VALUE() \
286  MCUX_CSSL_SC_VALUE_IMPL()
287 
301 #define MCUX_CSSL_SC_ASSIGN(value) \
302  MCUX_CSSL_SC_ASSIGN_IMPL(value)
303 
304 #endif /* MCUXCSSLSECURECOUNTER_H_ */
mcuxCsslSecureCounter_Impl.h
Selection of the implementation for the secure counter mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00641.html b/components/els_pkc/doc/mcxn/html/a00641.html new file mode 100644 index 000000000..b7974b5cb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00641.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_Cfg.h File Reference + + + + + + + + + + + + + + + + +
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MCUX Crypto Library Normal Secure
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+Macros
+
+
mcuxCsslSecureCounter_Cfg.h File Reference
+
+
+ +

Configuration of the implementation for the secure counter mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG
 If set to 1, use the hybrid secure counter mechanism implementation based on a SW counter stored in a local variable and the code watchdog (CDOG) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_CDOG
 If set to 1, use the secure counter mechanism implementation based on the code watchdog (CDOG) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_SCM
 If set to 1, use the secure counter mechanism implementation based on the subsystem control module (SCM) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_S3SCM
 If set to 1, use the secure counter mechanism implementation based on the subsystem control module (S3SCM) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_SW_LOCAL
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a local variable. More...
 
#define MCUX_CSSL_SC_USE_SW_CONTEXT
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a context structure. More...
 
#define MCUX_CSSL_SC_USE_SW_CALLBACK
 If set to 1, use the secure counter mechanism implementation based on a SW counter pointed to through a callback function. More...
 
#define MCUX_CSSL_SC_USE_SW_GLOBAL
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a global variable. More...
 
#define MCUX_CSSL_SC_USE_NONE
 If set to 1, do not use the secure counter mechanism. More...
 
+

Detailed Description

+

Configuration of the implementation for the secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00641.js b/components/els_pkc/doc/mcxn/html/a00641.js new file mode 100644 index 000000000..6a7e8e1ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00641.js @@ -0,0 +1,12 @@ +var a00641 = +[ + [ "MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG", "a00906.html#gab32cca78e592e73eb1d15d06be994839", null ], + [ "MCUX_CSSL_SC_USE_HW_CDOG", "a00906.html#gaa488aa67a604f34f36c1a99b07a6ab71", null ], + [ "MCUX_CSSL_SC_USE_HW_SCM", "a00906.html#gae5b47bf9fecd4e15c34cb859cad286a4", null ], + [ "MCUX_CSSL_SC_USE_HW_S3SCM", "a00906.html#gaf65f19a392d0dda41627f1e4ef3f2291", null ], + [ "MCUX_CSSL_SC_USE_SW_LOCAL", "a00906.html#ga841fe66e0a59b9c720854ff0ee2c4678", null ], + [ "MCUX_CSSL_SC_USE_SW_CONTEXT", "a00906.html#gaff2c61772a19bdf2e5038b674ea04128", null ], + [ "MCUX_CSSL_SC_USE_SW_CALLBACK", "a00906.html#ga788677fbf1a036b432007aa84a2879ad", null ], + [ "MCUX_CSSL_SC_USE_SW_GLOBAL", "a00906.html#ga8743f66cbadb2592671510ed3160dc09", null ], + [ "MCUX_CSSL_SC_USE_NONE", "a00906.html#ga8141a2d6da07d7137207fb35505a6cb0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00641_source.html b/components/els_pkc/doc/mcxn/html/a00641_source.html new file mode 100644 index 000000000..f1c53c43e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00641_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_Cfg.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslSecureCounter_Cfg.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLSECURECOUNTER_CFG_H_
20 #define MCUXCSSLSECURECOUNTER_CFG_H_
21 
36  #define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG 0
37 
44  #define MCUX_CSSL_SC_USE_HW_CDOG 0
45 
52  #define MCUX_CSSL_SC_USE_HW_SCM 0
53 
60  #define MCUX_CSSL_SC_USE_HW_S3SCM 0
61 
68  #define MCUX_CSSL_SC_USE_SW_LOCAL 1
69 
76  #define MCUX_CSSL_SC_USE_SW_CONTEXT 0
77 
84  #define MCUX_CSSL_SC_USE_SW_CALLBACK 0
85 
92  #define MCUX_CSSL_SC_USE_SW_GLOBAL 0
93 
99  #define MCUX_CSSL_SC_USE_NONE 0
100 
101 /* Basic configuration sanity check */
102 
103 #endif /* MCUXCSSLSECURECOUNTER_CFG_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00644.html b/components/els_pkc/doc/mcxn/html/a00644.html new file mode 100644 index 000000000..2e03a4605 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00644.html @@ -0,0 +1,130 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_Impl.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslSecureCounter_Impl.h File Reference
+
+
+ +

Selection of the implementation for the secure counter mechanism. +More...

+
#include <mcuxCsslSecureCounter_Cfg.h>
+#include <mcuxCsslSecureCounter_SW_Local.h>
+
+

Go to the source code of this file.

+

Detailed Description

+

Selection of the implementation for the secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00644_source.html b/components/els_pkc/doc/mcxn/html/a00644_source.html new file mode 100644 index 000000000..b02963927 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00644_source.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_Impl.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslSecureCounter_Impl.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLSECURECOUNTER_IMPL_H_
20 #define MCUXCSSLSECURECOUNTER_IMPL_H_
21 
22 /* Include the configuration for the secure counter mechanism. */
23 #include <mcuxCsslSecureCounter_Cfg.h>
24 
25 /* Include the selected implementation of the secure counter mechanism. */
26 #if defined(MCUX_CSSL_SC_USE_HW_CDOG) && (1 == MCUX_CSSL_SC_USE_HW_CDOG)
27 # include <mcuxCsslSecureCounter_HW_CDOG.h>
28 #elif defined(MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG) && (1 == MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG)
29 # include <mcuxCsslSecureCounter_Hybrid_LocalCDOG.h>
30 #elif defined(MCUX_CSSL_SC_USE_HW_S3SCM) && (1 == MCUX_CSSL_SC_USE_HW_S3SCM)
31 # include <mcuxCsslSecureCounter_HW_S3SCM.h>
32 #elif defined(MCUX_CSSL_SC_USE_HW_SCM) && (1 == MCUX_CSSL_SC_USE_HW_SCM)
33 # include <mcuxCsslSecureCounter_HW_SCM.h>
34 #elif defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL)
35 # include <mcuxCsslSecureCounter_SW_Local.h>
36 #elif defined(MCUX_CSSL_SC_USE_SW_CONTEXT) && (1 == MCUX_CSSL_SC_USE_SW_CONTEXT)
37 # include <mcuxCsslSecureCounter_SW_Context.h>
38 #elif defined(MCUX_CSSL_SC_USE_SW_CALLBACK) && (1 == MCUX_CSSL_SC_USE_SW_CALLBACK)
39 # include <mcuxCsslSecureCounter_SW_Callback.h>
40 #elif defined(MCUX_CSSL_SC_USE_SW_GLOBAL) && (1 == MCUX_CSSL_SC_USE_SW_GLOBAL)
41 # include <mcuxCsslSecureCounter_SW_Global.h>
42 #elif defined(MCUX_CSSL_SC_USE_NONE) && (1 == MCUX_CSSL_SC_USE_NONE)
43 # include <mcuxCsslSecureCounter_None.h>
44 #else
45 # error "No secure counter implementation found/configured."
46 #endif
47 
48 #endif /* MCUXCSSLSECURECOUNTER_IMPL_H_ */
mcuxCsslSecureCounter_None.h
Implementation that disables the CSSL secure counter mechanism.
+
mcuxCsslSecureCounter_SW_Local.h
SW implementation of the CSSL secure counter mechanism (using a local variable).
+
mcuxCsslSecureCounter_Cfg.h
Configuration of the implementation for the secure counter mechanism.
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00647.html b/components/els_pkc/doc/mcxn/html/a00647.html new file mode 100644 index 000000000..e5b68d3ee --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00647.html @@ -0,0 +1,191 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_None.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslSecureCounter_None.h File Reference
+
+
+ +

Implementation that disables the CSSL secure counter mechanism. +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
 Data type used for the secure counter. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
 Data type used for properly casting the secure counter balancing values. More...
 
#define MCUX_CSSL_SC_ALLOC_IMPL()
 Allocation operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT_IMPL(value)
 Initialization operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK_IMPL(value)
 Comparison operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_ADD_IMPL(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
 Increment the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_SUB_IMPL(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
 Decrement the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_VALUE_IMPL()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN_IMPL(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

Implementation that disables the CSSL secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00647.js b/components/els_pkc/doc/mcxn/html/a00647.js new file mode 100644 index 000000000..a4b78784c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00647.js @@ -0,0 +1,22 @@ +var a00647 = +[ + [ "MCUX_CSSL_SC_CHECK_PASSED_IMPL", "a00908.html#ga417202932e9a8a880e23e8a3321309ac", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED_IMPL", "a00908.html#gac1d032d150bd774f86bbb50fdfa0ee19", null ], + [ "MCUX_CSSL_SC_COUNTER_TYPE_IMPL", "a00908.html#gaafa4d13a4e311121551b8e49662c3470", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE_IMPL", "a00908.html#gaf84485a6eb6bbcd39933ff1abcb3ee61", null ], + [ "MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL", "a00908.html#ga919150430f3033eb5d6c8025216548b3", null ], + [ "MCUX_CSSL_SC_ALLOC_IMPL", "a00908.html#gad413de64b4cc420be30b5278fd5083d0", null ], + [ "MCUX_CSSL_SC_INIT_IMPL", "a00908.html#gaf8d9ebeb36322ea86fc8766afa84bc3f", null ], + [ "MCUX_CSSL_SC_CHECK_IMPL", "a00908.html#gaf15120a3e9f4edf59cb5b42860fe86dd", null ], + [ "MCUX_CSSL_SC_ADD_IMPL", "a00909.html#gaa4a21360f6c3d08fc777879e4f4551ed", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL_IMPL", "a00909.html#ga9c0484fdff900c04462d668a0870bf33", null ], + [ "MCUX_CSSL_SC_ADD_0X1_IMPL", "a00909.html#ga45a909bcf29531036b1aad68ac8b0afb", null ], + [ "MCUX_CSSL_SC_ADD_0X10_IMPL", "a00909.html#gaac716380d3c29a995745053bb6915044", null ], + [ "MCUX_CSSL_SC_ADD_0X100_IMPL", "a00909.html#gafb5fa6d42145120126b00ab3707711be", null ], + [ "MCUX_CSSL_SC_SUB_IMPL", "a00910.html#gaca0635e01e8eef97f9a06a50b24d0941", null ], + [ "MCUX_CSSL_SC_SUB_0X1_IMPL", "a00910.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8", null ], + [ "MCUX_CSSL_SC_SUB_0X10_IMPL", "a00910.html#gafa9701e3c0f7e757573c4bfcdae22959", null ], + [ "MCUX_CSSL_SC_SUB_0X100_IMPL", "a00910.html#gaa4a6dba75f476d29637e005dc8272083", null ], + [ "MCUX_CSSL_SC_VALUE_IMPL", "a00911.html#ga5ebadc1cc4cc3e849527adcf3da5c258", null ], + [ "MCUX_CSSL_SC_ASSIGN_IMPL", "a00911.html#ga87e741e67b757bf719409530176e56b9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00647_source.html b/components/els_pkc/doc/mcxn/html/a00647_source.html new file mode 100644 index 000000000..2a0045873 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00647_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_None.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxCsslSecureCounter_None.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
19 #ifndef MCUXCSSLSECURECOUNTER_NONE_H_
20 #define MCUXCSSLSECURECOUNTER_NONE_H_
21 
39 /****************************************************************************/
40 /* Constants */
41 /****************************************************************************/
42 
48 #define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u)
49 
55 #define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL)
56 
62 #define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \
63  uint32_t
64 
70 #define MCUX_CSSL_SC_VALUE_TYPE_IMPL \
71  static const uint32_t
72 
78 #define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \
79  uint32_t
80 
81 /****************************************************************************/
82 /* Initialization */
83 /****************************************************************************/
84 
90 #define MCUX_CSSL_SC_ALLOC_IMPL() \
91  /* intentionally empty */
92 
100 #define MCUX_CSSL_SC_INIT_IMPL(value) \
101  /* intentionally empty */
102 
103 /****************************************************************************/
104 /* Check */
105 /****************************************************************************/
106 
115 #define MCUX_CSSL_SC_CHECK_IMPL(value) \
116  (MCUX_CSSL_SC_CHECK_PASSED_IMPL)
117 
118 /****************************************************************************/
119 /* Counter increment */
120 /****************************************************************************/
136 #define MCUX_CSSL_SC_ADD_IMPL(value) \
137  /* intentionally empty */
138 
148 #define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \
149  /* intentionally empty */
150 
158 #define MCUX_CSSL_SC_ADD_0X1_IMPL() \
159  /* intentionally empty */
160 
168 #define MCUX_CSSL_SC_ADD_0X10_IMPL() \
169  /* intentionally empty */
170 
178 #define MCUX_CSSL_SC_ADD_0X100_IMPL() \
179  /* intentionally empty */
180 
181 /****************************************************************************/
182 /* Counter decrement */
183 /****************************************************************************/
199 #define MCUX_CSSL_SC_SUB_IMPL(value) \
200  /* intentionally empty */
201 
209 #define MCUX_CSSL_SC_SUB_0X1_IMPL() \
210  /* intentionally empty */
211 
219 #define MCUX_CSSL_SC_SUB_0X10_IMPL() \
220  /* intentionally empty */
221 
229 #define MCUX_CSSL_SC_SUB_0X100_IMPL() \
230  /* intentionally empty */
231 
232 /****************************************************************************/
233 /* Direct access (optional) */
234 /****************************************************************************/
255 #define MCUX_CSSL_SC_VALUE_IMPL() \
256  1/0 /* not supported */
257 
270 #define MCUX_CSSL_SC_ASSIGN_IMPL(value) \
271  /* intentionally empty */
272 
273 
274 #endif /* MCUXCSSLSECURECOUNTER_NONE_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00650.html b/components/els_pkc/doc/mcxn/html/a00650.html new file mode 100644 index 000000000..9bcc1a169 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00650.html @@ -0,0 +1,194 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_SW_Local.h File Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslSecureCounter_SW_Local.h File Reference
+
+
+ +

SW implementation of the CSSL secure counter mechanism (using a local variable). +More...

+ +

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_COUNTER_NAME
 Variable name to use for storing the secure counter value. More...
 
#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
 Data type used for the secure counter. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
 Data type used for properly casting the secure counter balancing values. More...
 
#define MCUX_CSSL_SC_ALLOC_IMPL()
 Allocation operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT_IMPL(value)
 Initialization operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK_IMPL(value)
 Comparison operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_ADD_IMPL(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
 Increment the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_SUB_IMPL(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
 Decrement the secure counter with 0x100. More...
 
#define MCUX_CSSL_SC_VALUE_IMPL()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN_IMPL(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

SW implementation of the CSSL secure counter mechanism (using a local variable).

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00650.js b/components/els_pkc/doc/mcxn/html/a00650.js new file mode 100644 index 000000000..102b2e318 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00650.js @@ -0,0 +1,23 @@ +var a00650 = +[ + [ "MCUX_CSSL_SC_COUNTER_NAME", "a00913.html#ga7cf637fa768fe3fe088dbf367ad46b8a", null ], + [ "MCUX_CSSL_SC_CHECK_PASSED_IMPL", "a00913.html#ga417202932e9a8a880e23e8a3321309ac", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED_IMPL", "a00913.html#gac1d032d150bd774f86bbb50fdfa0ee19", null ], + [ "MCUX_CSSL_SC_COUNTER_TYPE_IMPL", "a00913.html#gaafa4d13a4e311121551b8e49662c3470", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE_IMPL", "a00913.html#gaf84485a6eb6bbcd39933ff1abcb3ee61", null ], + [ "MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL", "a00913.html#ga919150430f3033eb5d6c8025216548b3", null ], + [ "MCUX_CSSL_SC_ALLOC_IMPL", "a00913.html#gad413de64b4cc420be30b5278fd5083d0", null ], + [ "MCUX_CSSL_SC_INIT_IMPL", "a00913.html#gaf8d9ebeb36322ea86fc8766afa84bc3f", null ], + [ "MCUX_CSSL_SC_CHECK_IMPL", "a00913.html#gaf15120a3e9f4edf59cb5b42860fe86dd", null ], + [ "MCUX_CSSL_SC_ADD_IMPL", "a00914.html#gaa4a21360f6c3d08fc777879e4f4551ed", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL_IMPL", "a00914.html#ga9c0484fdff900c04462d668a0870bf33", null ], + [ "MCUX_CSSL_SC_ADD_0X1_IMPL", "a00914.html#ga45a909bcf29531036b1aad68ac8b0afb", null ], + [ "MCUX_CSSL_SC_ADD_0X10_IMPL", "a00914.html#gaac716380d3c29a995745053bb6915044", null ], + [ "MCUX_CSSL_SC_ADD_0X100_IMPL", "a00914.html#gafb5fa6d42145120126b00ab3707711be", null ], + [ "MCUX_CSSL_SC_SUB_IMPL", "a00915.html#gaca0635e01e8eef97f9a06a50b24d0941", null ], + [ "MCUX_CSSL_SC_SUB_0X1_IMPL", "a00915.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8", null ], + [ "MCUX_CSSL_SC_SUB_0X10_IMPL", "a00915.html#gafa9701e3c0f7e757573c4bfcdae22959", null ], + [ "MCUX_CSSL_SC_SUB_0X100_IMPL", "a00915.html#gaa4a6dba75f476d29637e005dc8272083", null ], + [ "MCUX_CSSL_SC_VALUE_IMPL", "a00916.html#ga5ebadc1cc4cc3e849527adcf3da5c258", null ], + [ "MCUX_CSSL_SC_ASSIGN_IMPL", "a00916.html#ga87e741e67b757bf719409530176e56b9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00650_source.html b/components/els_pkc/doc/mcxn/html/a00650_source.html new file mode 100644 index 000000000..bdccea5a7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00650_source.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxCsslSecureCounter_SW_Local.h Source File + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+
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+
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+
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+ +
+
+ + +
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+
+
mcuxCsslSecureCounter_SW_Local.h
+
+
+Go to the documentation of this file.
1 /*--------------------------------------------------------------------------*/
2 /* Copyright 2020-2023 NXP */
3 /* */
4 /* NXP Confidential. This software is owned or controlled by NXP and may */
5 /* only be used strictly in accordance with the applicable license terms. */
6 /* By expressly accepting such terms or by downloading, installing, */
7 /* activating and/or otherwise using the software, you are agreeing that */
8 /* you have read, and that you agree to comply with and are bound by, such */
9 /* license terms. If you do not agree to be bound by the applicable license */
10 /* terms, then you may not retain, install, activate or otherwise use the */
11 /* software. */
12 /*--------------------------------------------------------------------------*/
13 
20 #ifndef MCUXCSSLSECURECOUNTER_SW_LOCAL_H_
21 #define MCUXCSSLSECURECOUNTER_SW_LOCAL_H_
22 
45 #define MCUX_CSSL_SC_COUNTER_NAME \
46  mcuxCsslSecureCounter
47 
48 /****************************************************************************/
49 /* Constants */
50 /****************************************************************************/
51 
57 #define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u)
58 
64 #define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL)
65 
71 #define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \
72  uint32_t
73 
79 #define MCUX_CSSL_SC_VALUE_TYPE_IMPL \
80  static const uint32_t
81 
87 #define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \
88  uint32_t
89 
90 /****************************************************************************/
91 /* Initialization */
92 /****************************************************************************/
93 
99 #define MCUX_CSSL_SC_ALLOC_IMPL() \
100  MCUX_CSSL_SC_COUNTER_TYPE_IMPL MCUX_CSSL_SC_COUNTER_NAME
101 
109 #define MCUX_CSSL_SC_INIT_IMPL(value) \
110  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
111  MCUX_CSSL_SC_ALLOC_IMPL() = ((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) \
112  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
113 
114 /****************************************************************************/
115 /* Check */
116 /****************************************************************************/
117 
127 #define MCUX_CSSL_SC_CHECK_IMPL(value) \
128  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
129  (MCUX_CSSL_SC_CHECK_FAILED_IMPL ^ (MCUX_CSSL_SC_COUNTER_NAME - (((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) + 1u))) \
130  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
131 
132 /****************************************************************************/
133 /* Counter increment */
134 /****************************************************************************/
150 #define MCUX_CSSL_SC_ADD_IMPL(value) \
151  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
152  MCUX_CSSL_SC_COUNTER_NAME += (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
153  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
154 
164 #define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \
165  MCUX_CSSL_SC_ADD_IMPL(value)
166 
174 #define MCUX_CSSL_SC_ADD_0X1_IMPL() \
175  MCUX_CSSL_SC_ADD_IMPL(0x1u)
176 
184 #define MCUX_CSSL_SC_ADD_0X10_IMPL() \
185  MCUX_CSSL_SC_ADD_IMPL(0x10u)
186 
194 #define MCUX_CSSL_SC_ADD_0X100_IMPL() \
195  MCUX_CSSL_SC_ADD_IMPL(0x100u)
196 
197 /****************************************************************************/
198 /* Counter decrement */
199 /****************************************************************************/
215 #define MCUX_CSSL_SC_SUB_IMPL(value) \
216  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
217  MCUX_CSSL_SC_COUNTER_NAME -= (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
218  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
219 
227 #define MCUX_CSSL_SC_SUB_0X1_IMPL() \
228  MCUX_CSSL_SC_SUB_IMPL(0x1u)
229 
237 #define MCUX_CSSL_SC_SUB_0X10_IMPL() \
238  MCUX_CSSL_SC_SUB_IMPL(0x10u)
239 
247 #define MCUX_CSSL_SC_SUB_0X100_IMPL() \
248  MCUX_CSSL_SC_SUB_IMPL(0x100u)
249 
250 /****************************************************************************/
251 /* Direct access (optional) */
252 /****************************************************************************/
273 #define MCUX_CSSL_SC_VALUE_IMPL() \
274  MCUX_CSSL_SC_COUNTER_NAME
275 
288 #define MCUX_CSSL_SC_ASSIGN_IMPL(value) \
289  MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \
290  MCUX_CSSL_SC_COUNTER_NAME = (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \
291  MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW()
292 
293 #endif /* MCUXCSSLSECURECOUNTER_SW_LOCAL_H_ */
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00661.html b/components/els_pkc/doc/mcxn/html/a00661.html new file mode 100644 index 000000000..690891092 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00661.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClAead + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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mcuxClAead
MCUX CL &ndash; API
+
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Hash component. +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 mcuxClAead_Constants
 Constants of mcuxClAead component.
 
 One-shot AEAD interfaces
 Interfaces to perform AEAD operations in one shot.
 
 AEAD type definitions
 Types used by the AEAD operations.
 
 mcuxClAead_MemoryConsumption
 Defines the memory consumption for the mcuxClAead component All work area sizes in bytes are a multiple of CPU wordsize.
 
 AEAD mode definitions
 Modes used by the AEAD operations.
 
+

Detailed Description

+

Hash component.

+

Authenticated Encryption with Associated Data (AEAD) operations.

+

The mcuxClAead component implements the Authenticated Encryption with Associated Data (AEAD) operations supported by CLNS.

+

An example of how to use the mcuxClAead component can be found in /mcuxClAead/ex.

+

The component uses the ELS hardware. The ELS hardware has to be initialized, prior to calling any function of the mcuxClAead component.

+

The mcuxClAead component supports interfaces to either authenticate and encrypt or verify and decrypt a message in one shot (mcuxClAead_crypt) or to either authenticate and encrypt or verify and decrypt it in parts (mcuxClAead_init, mcuxClAead_process, mcuxClAead_process_adata and mcuxClAead_finish). In case of processing a message in parts, first an initialization has to be performed (mcuxClAead_init), followed by zero, one or multiple updates (mcuxClAead_process_adata and mcuxClAead_process), followed by a finalization or verification (mcuxClAead_finish/mcuxClAead_verify). The finalization generates the output tag and destroys the context. The verification generates and compares the output tag and destroys the context. After the finalization/verification step, no further updates are possible.

+

The targeted AEAD algorithm is selected by passing one of the offered algorithm mode descriptors (mcuxClAead_Modes), which are listed in file mcuxClAead_Modes.h

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00661.js b/components/els_pkc/doc/mcxn/html/a00661.js new file mode 100644 index 000000000..328410526 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00661.js @@ -0,0 +1,8 @@ +var a00661 = +[ + [ "mcuxClAead_Constants", "a00662.html", "a00662" ], + [ "One-shot AEAD interfaces", "a00664.html", "a00664" ], + [ "AEAD type definitions", "a00666.html", "a00666" ], + [ "mcuxClAead_MemoryConsumption", "a00667.html", "a00667" ], + [ "AEAD mode definitions", "a00668.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00662.html b/components/els_pkc/doc/mcxn/html/a00662.html new file mode 100644 index 000000000..8022e59a1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00662.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClAead_Constants + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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mcuxClAead_Constants
MCUX CL &ndash; API » mcuxClAead
+
+
+ +

Constants of mcuxClAead component. +More...

+ + + + + +

+Modules

 MCUXCLAEAD_STATUS_
 Return code definitions.
 
+

Detailed Description

+

Constants of mcuxClAead component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00662.js b/components/els_pkc/doc/mcxn/html/a00662.js new file mode 100644 index 000000000..02d90a60e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00662.js @@ -0,0 +1,4 @@ +var a00662 = +[ + [ "MCUXCLAEAD_STATUS_", "a00663.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00663.html b/components/els_pkc/doc/mcxn/html/a00663.html new file mode 100644 index 000000000..0cb3d69da --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00663.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: MCUXCLAEAD_STATUS_ + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros
+
+
MCUXCLAEAD_STATUS_
MCUX CL &ndash; API » mcuxClAead » mcuxClAead_Constants
+
+
+ +

Return code definitions. +More...

+ + + + + + + + + + +

+Macros

+#define MCUXCLAEAD_STATUS_ERROR
 
+#define MCUXCLAEAD_STATUS_FAULT_ATTACK
 
+#define MCUXCLAEAD_STATUS_OK
 
+#define MCUXCLAEAD_STATUS_NOT_OK
 
+

Detailed Description

+

Return code definitions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00664.html b/components/els_pkc/doc/mcxn/html/a00664.html new file mode 100644 index 000000000..d2e263411 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00664.html @@ -0,0 +1,268 @@ + + + + + + + +MCUX CLNS: One-shot AEAD interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Modules | +Functions
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+
One-shot AEAD interfaces
MCUX CL &ndash; API » mcuxClAead
+
+
+ +

Interfaces to perform AEAD operations in one shot. +More...

+ + + + + +

+Modules

 Multi-part AEAD interfaces
 Interfaces to perform AEAD operations in multiple parts.
 
+ + + + +

+Functions

mcuxClAead_Status_t mcuxClAead_crypt (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag, uint32_t tagLength)
 One-shot authenticated encryption/decryption function. More...
 
+

Detailed Description

+

Interfaces to perform AEAD operations in one shot.

+

Function Documentation

+ +

◆ mcuxClAead_crypt()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_crypt (mcuxClSession_Handle_t session,
mcuxClKey_Handle_t key,
mcuxClAead_Mode_t mode,
mcuxCl_InputBuffer_t pNonce,
uint32_t nonceLength,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength,
mcuxCl_InputBuffer_t pAdata,
uint32_t adataLength,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength,
mcuxCl_Buffer_t pTag,
uint32_t tagLength 
)
+
+ +

One-shot authenticated encryption/decryption function.

+

This function performs an authenticated encryption/decryption operation in one shot. The algorithm to be used will be determined based on the mode that is provided.

+

For example, to perform an AES authenticated encryption operation with a 128-bit key in GCM mode on padded data, the following needs to be provided:

    +
  • AES128 key
    • +
  • AES GCM encryption mode
    • +
  • Nonce
    • +
  • Plain input data
    • +
  • Associated data
    • +
  • Output data buffer
    • +
  • Output length buffer, to store the amount of written bytes
    • +
  • Tag buffer, to store the authentication tag
    • +
+
Parameters
+ + + + + + + + + + + + + + +
sessionHandle for the current CL session.
keyKey to be used to encrypt the data.
modeAEAD mode that should be used during the encryption operation.
[in]pNoncePointer to the buffer that contains the nonce.
nonceLengthNumber of bytes of nonce data in the nonce buffer.
[in]pInPointer to the input buffer that contains the plain data that need to be authenticated and encrypted.
inLengthNumber of bytes of plain data in the in buffer.
[in]pAdataAssociated data for the authenticated encryption operation. Data format depends on the chosen mode.
adataLengthNumber of bytes of associated data in the adata buffer.
[out]pOutPointer to the output buffer where the authenticated encrypted data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of authenticated encrypted data that have been written to the out buffer.
[out]pTagPointer to the output buffer where the tag needs to be written.
tagLengthNumber of bytes of tag data that will be written to the tag buffer.
+
+
+
Returns
status
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00664.js b/components/els_pkc/doc/mcxn/html/a00664.js new file mode 100644 index 000000000..a3e3c7ab5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00664.js @@ -0,0 +1,5 @@ +var a00664 = +[ + [ "Multi-part AEAD interfaces", "a00665.html", "a00665" ], + [ "mcuxClAead_crypt", "a00664.html#gad0713168358588f9550468bf1ef7cfbb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00665.html b/components/els_pkc/doc/mcxn/html/a00665.html new file mode 100644 index 000000000..a5b7299e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00665.html @@ -0,0 +1,478 @@ + + + + + + + +MCUX CLNS: Multi-part AEAD interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Functions
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Multi-part AEAD interfaces
MCUX CL &ndash; API » mcuxClAead » One-shot AEAD interfaces
+
+
+ +

Interfaces to perform AEAD operations in multiple parts. +More...

+ + + + + + + + + + + + + + + + + +

+Functions

mcuxClAead_Status_t mcuxClAead_init (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClAead_Mode_t mode, mcuxCl_InputBuffer_t pNonce, uint32_t nonceLength, uint32_t inLength, uint32_t adataLength, uint32_t tagLength)
 Multi-part authenticated encryption/decryption initialization function. More...
 
mcuxClAead_Status_t mcuxClAead_process (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part authenticated encryption/decryption processing function for the regular data (authenticated and encrypted) More...
 
mcuxClAead_Status_t mcuxClAead_process_adata (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pAdata, uint32_t adataLength)
 Multi-part authenticated encryption/decryption processing function for the associated data (authenticated only) More...
 
mcuxClAead_Status_t mcuxClAead_finish (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength, mcuxCl_Buffer_t pTag)
 Multi-part authenticated encryption/decryption finalization function. More...
 
mcuxClAead_Status_t mcuxClAead_verify (mcuxClSession_Handle_t session, mcuxClAead_Context_t *const pContext, mcuxCl_InputBuffer_t pTag, mcuxCl_Buffer_t pOut, uint32_t *const pOutLength)
 Multi-part authenticated decryption verification function. More...
 
+

Detailed Description

+

Interfaces to perform AEAD operations in multiple parts.

+

Function Documentation

+ +

◆ mcuxClAead_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_init (mcuxClSession_Handle_t session,
mcuxClAead_Context_t *const pContext,
mcuxClKey_Handle_t key,
mcuxClAead_Mode_t mode,
mcuxCl_InputBuffer_t pNonce,
uint32_t nonceLength,
uint32_t inLength,
uint32_t adataLength,
uint32_t tagLength 
)
+
+ +

Multi-part authenticated encryption/decryption initialization function.

+

This function performs the initialization for a multi part authenticated encryption/decryption operation. The algorithm to be used will be determined based on the key and mode that are provided.

+
Parameters
+ + + + + + + + + + +
sessionHandle for the current CL session.
pContextAEAD context which is used to maintain the state and store other relevant information about the operation.
keyKey to be used to encrypt the data.
modeAEAD mode that should be used during the encryption/decryption operation.
[in]pNoncePointer to the buffer that contains the nonce.
nonceLengthNumber of bytes of nonce data in the nonce buffer.
inLengthNumber of bytes of plain data that will be processed.
adataLengthNumber of bytes of associated data that will be processed.
tagLengthNumber of bytes to be used for the authentication tag.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClAead_process()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_process (mcuxClSession_Handle_t session,
mcuxClAead_Context_t *const pContext,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength 
)
+
+ +

Multi-part authenticated encryption/decryption processing function for the regular data (authenticated and encrypted)

+

This function performs the processing of (a part of) a data stream for an authenticated encryption/decryption operation. The algorithm and key to be used will be determined based on the context that is provided.

+
Parameters
+ + + + + + + +
sessionHandle for the current CL session.
pContextAEAD context which is used to maintain the state and store other relevant information about the operation.
[in]pInPointer to the input buffer that contains the data that needs to be processed.
inLengthNumber of bytes of data in the in buffer.
[out]pOutPointer to the output buffer where the processed data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of processed data that have been written to the out buffer.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClAead_process_adata()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_process_adata (mcuxClSession_Handle_t session,
mcuxClAead_Context_t *const pContext,
mcuxCl_InputBuffer_t pAdata,
uint32_t adataLength 
)
+
+ +

Multi-part authenticated encryption/decryption processing function for the associated data (authenticated only)

+

This function performs the processing of (a part of) an associated data stream for an authenticated encryption/decryption operation. The algorithm and key to be used will be determined based on the context that is provided.

+
Parameters
+ + + + + +
sessionHandle for the current CL session.
pContextAEAD context which is used to maintain the state and store other relevant information about the operation.
[in]pAdataAssociated data that needs to be proccessed.
adataLengthNumber of bytes of associated data in the adata buffer.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClAead_finish()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_finish (mcuxClSession_Handle_t session,
mcuxClAead_Context_t *const pContext,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength,
mcuxCl_Buffer_t pTag 
)
+
+ +

Multi-part authenticated encryption/decryption finalization function.

+

This function performs the finalization of an authenticated encryption or decryption operation and produces the authentication tag. The algorithm and key to be used will be determined based on the context that is provided.

+

Note: the taglength is already specified when the INIT function is called.

+
Parameters
+ + + + + + +
sessionHandle for the current CL session.
pContextAEAD context which is used to maintain the state and store other relevant information about the operation.
[out]pOutPointer to the output buffer where the processed data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of processed data that have been written to the out buffer.
[out]pTagPointer to the output buffer where the tag needs to be written.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClAead_verify()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClAead_Status_t mcuxClAead_verify (mcuxClSession_Handle_t session,
mcuxClAead_Context_t *const pContext,
mcuxCl_InputBuffer_t pTag,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutLength 
)
+
+ +

Multi-part authenticated decryption verification function.

+

This function performs the finalization of an authenticated decryption operation and verifies the authentication tag. The algorithm and key to be used will be determined based on the context that is provided.

+

This function can be used as an alternative for mcuxClAead_finish when one also wants to perform the tag verification step.

+

Note: the taglength is already specified when the INIT function is called.

+
Parameters
+ + + + + + +
sessionHandle for the current CL session.
pContextAEAD context which is used to maintain the state and store other relevant information about the operation.
[in]pTagPointer to the buffer that contains the tag.
[out]pOutPointer to the output buffer where the authenticated decrypted data needs to be written.
[out]pOutLengthWill be incremented by the number of bytes of authenticated decrypted data that have been written to the out buffer.
+
+
+
Returns
status
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00665.js b/components/els_pkc/doc/mcxn/html/a00665.js new file mode 100644 index 000000000..d80f46832 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00665.js @@ -0,0 +1,8 @@ +var a00665 = +[ + [ "mcuxClAead_init", "a00665.html#gaeb2451aba7d135f7af05e94f9b095fae", null ], + [ "mcuxClAead_process", "a00665.html#gaa4af5201aaf549186bf80cbf4284f3d1", null ], + [ "mcuxClAead_process_adata", "a00665.html#ga40cbd731ba8874d971213fa03605736d", null ], + [ "mcuxClAead_finish", "a00665.html#ga2b18aa6585e4d229d7ccfdd34f3f9dba", null ], + [ "mcuxClAead_verify", "a00665.html#gafb82bc41120d69281d0fbb719fb35d9d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00666.html b/components/els_pkc/doc/mcxn/html/a00666.html new file mode 100644 index 000000000..deb862f08 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00666.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: AEAD type definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
AEAD type definitions
MCUX CL &ndash; API » mcuxClAead
+
+
+ +

Types used by the AEAD operations. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t
 AEAD mode/algorithm descriptor type. More...
 
typedef const mcuxClAead_ModeDescriptor_t *const mcuxClAead_Mode_t
 AEAD mode/algorithm type. More...
 
typedef struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t
 Aead selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClAead_TestDescriptor_t *const mcuxClAead_Test_t
 Aead selftest mode/algorithm type. More...
 
typedef struct mcuxClAead_Context mcuxClAead_Context_t
 AEAD context type. More...
 
typedef uint32_t mcuxClAead_Status_t
 AEAD status code. More...
 
+

Detailed Description

+

Types used by the AEAD operations.

+

Typedef Documentation

+ +

◆ mcuxClAead_ModeDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t
+
+ +

AEAD mode/algorithm descriptor type.

+

This type captures all the information that the AEAD interfaces need to know about a particular AEAD mode/algorithm.

+ +
+
+ +

◆ mcuxClAead_Mode_t

+ +
+
+ + + + +
typedef const mcuxClAead_ModeDescriptor_t* const mcuxClAead_Mode_t
+
+ +

AEAD mode/algorithm type.

+

This type is used to refer to an AEAD mode/algorithm.

+ +
+
+ +

◆ mcuxClAead_TestDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t
+
+ +

Aead selftest mode/algorithm descriptor type.

+

This type captures all the information that the Aead selftest interfaces need to know about a particular Aead selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClAead_Test_t

+ +
+
+ + + + +
typedef const mcuxClAead_TestDescriptor_t* const mcuxClAead_Test_t
+
+ +

Aead selftest mode/algorithm type.

+

This type is used to refer to a Aead selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClAead_Context_t

+ +
+
+ + + + +
typedef struct mcuxClAead_Context mcuxClAead_Context_t
+
+ +

AEAD context type.

+

This type is used in the multi-part interfaces to store the information about the current operation and the relevant internal state.

+ +
+
+ +

◆ mcuxClAead_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClAead_Status_t
+
+ +

AEAD status code.

+

This type provides information about the status of the AEAD operation that has been performed.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00666.js b/components/els_pkc/doc/mcxn/html/a00666.js new file mode 100644 index 000000000..d8aeeaf7e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00666.js @@ -0,0 +1,9 @@ +var a00666 = +[ + [ "mcuxClAead_ModeDescriptor_t", "a00666.html#ga8378bbf26468fde8248b08efca599481", null ], + [ "mcuxClAead_Mode_t", "a00666.html#ga8084949e97b9ab9cd35ac041b8bbea0a", null ], + [ "mcuxClAead_TestDescriptor_t", "a00666.html#gae182daa83ee8ec992f261f2b52b20adb", null ], + [ "mcuxClAead_Test_t", "a00666.html#gab0222b5a8fcc204e08515b0b558fb5fe", null ], + [ "mcuxClAead_Context_t", "a00666.html#gaf67b42507181f9793498bfaaab35a48a", null ], + [ "mcuxClAead_Status_t", "a00666.html#ga1497c344a218545c5980a407e7c9194d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00667.html b/components/els_pkc/doc/mcxn/html/a00667.html new file mode 100644 index 000000000..aa6a85f19 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00667.html @@ -0,0 +1,203 @@ + + + + + + + +MCUX CLNS: mcuxClAead_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClAead_MemoryConsumption
MCUX CL &ndash; API » mcuxClAead
+
+
+ +

Defines the memory consumption for the mcuxClAead component All work area sizes in bytes are a multiple of CPU wordsize. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLAEAD_SIZE_IN_CPUWORDS(size)
 
+#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLAEAD_CONTEXT_SIZE
 
#define MCUXCLAEAD_WA_SIZE_MAX
 Define the max workarea size in bytes required for this component. More...
 
+#define MCUXCLAEAD_WA_SIZE_IN_WORDS_MAX
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClAead component All work area sizes in bytes are a multiple of CPU wordsize.

+

Macro Definition Documentation

+ +

◆ MCUXCLAEAD_WA_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLAEAD_WA_SIZE_MAX
+
+ +

Define the max workarea size in bytes required for this component.

+

Work area sizes in bytes are a multiple of CPU wordsize.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00667.js b/components/els_pkc/doc/mcxn/html/a00667.js new file mode 100644 index 000000000..d72d339b5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00667.js @@ -0,0 +1,4 @@ +var a00667 = +[ + [ "MCUXCLAEAD_WA_SIZE_MAX", "a00667.html#gab4cc3939b235a6d122ce012c23d3e61a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00668.html b/components/els_pkc/doc/mcxn/html/a00668.html new file mode 100644 index 000000000..b7f5ee4e3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00668.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: AEAD mode definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
AEAD mode definitions
MCUX CL &ndash; API » mcuxClAead
+
+
+ +

Modes used by the AEAD operations. +More...

+

Modes used by the AEAD operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00669.html b/components/els_pkc/doc/mcxn/html/a00669.html new file mode 100644 index 000000000..87418a15c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00669.html @@ -0,0 +1,286 @@ + + + + + + + +MCUX CLNS: mcuxClAes_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClAes_Constants
+
+
+ +

Defines of constants associated with mcuxClAes. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLAES_BLOCK_SIZE
 AES block size in bytes. More...
 
#define MCUXCLAES_BLOCK_SIZE_IN_WORDS
 AES block size in words. More...
 
#define MCUXCLAES_AES128_KEY_SIZE
 AES-128 key size in bytes. More...
 
#define MCUXCLAES_AES128_KEY_SIZE_IN_WORDS
 AES-128 key size in words. More...
 
#define MCUXCLAES_AES192_KEY_SIZE
 AES-192 key size in bytes. More...
 
#define MCUXCLAES_AES192_KEY_SIZE_IN_WORDS
 AES-192 key size in words. More...
 
#define MCUXCLAES_AES256_KEY_SIZE
 AES-256 key size in bytes. More...
 
#define MCUXCLAES_AES256_KEY_SIZE_IN_WORDS
 AES-256 key size in words. More...
 
+

Detailed Description

+

Defines of constants associated with mcuxClAes.

+

Macro Definition Documentation

+ +

◆ MCUXCLAES_BLOCK_SIZE

+ +
+
+ + + + +
#define MCUXCLAES_BLOCK_SIZE
+
+ +

AES block size in bytes.

+ +
+
+ +

◆ MCUXCLAES_BLOCK_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLAES_BLOCK_SIZE_IN_WORDS
+
+ +

AES block size in words.

+ +
+
+ +

◆ MCUXCLAES_AES128_KEY_SIZE

+ +
+
+ + + + +
#define MCUXCLAES_AES128_KEY_SIZE
+
+ +

AES-128 key size in bytes.

+ +
+
+ +

◆ MCUXCLAES_AES128_KEY_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLAES_AES128_KEY_SIZE_IN_WORDS
+
+ +

AES-128 key size in words.

+
Examples
mcuxClKey_example.c.
+
+ +
+
+ +

◆ MCUXCLAES_AES192_KEY_SIZE

+ +
+
+ + + + +
#define MCUXCLAES_AES192_KEY_SIZE
+
+ +

AES-192 key size in bytes.

+ +
+
+ +

◆ MCUXCLAES_AES192_KEY_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLAES_AES192_KEY_SIZE_IN_WORDS
+
+ +

AES-192 key size in words.

+ +
+
+ +

◆ MCUXCLAES_AES256_KEY_SIZE

+ +
+
+ + + + +
#define MCUXCLAES_AES256_KEY_SIZE
+
+ +

AES-256 key size in bytes.

+ +
+
+ +

◆ MCUXCLAES_AES256_KEY_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLAES_AES256_KEY_SIZE_IN_WORDS
+
+ +

AES-256 key size in words.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00669.js b/components/els_pkc/doc/mcxn/html/a00669.js new file mode 100644 index 000000000..5ecbc6111 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00669.js @@ -0,0 +1,11 @@ +var a00669 = +[ + [ "MCUXCLAES_BLOCK_SIZE", "a00669.html#gaa988298f03dda2718fd7d6a893d84b6a", null ], + [ "MCUXCLAES_BLOCK_SIZE_IN_WORDS", "a00669.html#ga70310305440fe83e2f18e79341de4830", null ], + [ "MCUXCLAES_AES128_KEY_SIZE", "a00669.html#gaf7377746dc3a4ea714c79c17f9ddbdde", null ], + [ "MCUXCLAES_AES128_KEY_SIZE_IN_WORDS", "a00669.html#ga82f8be599a040e7a44d1c4a78513b643", null ], + [ "MCUXCLAES_AES192_KEY_SIZE", "a00669.html#ga10c60a14d43acdf3a32074b6104c00b4", null ], + [ "MCUXCLAES_AES192_KEY_SIZE_IN_WORDS", "a00669.html#ga68bc6c94d74d3ddde085798e06c5968a", null ], + [ "MCUXCLAES_AES256_KEY_SIZE", "a00669.html#gaf85d02f88b56069ada0d2e6eaf184af8", null ], + [ "MCUXCLAES_AES256_KEY_SIZE_IN_WORDS", "a00669.html#ga59948f7fc4145e5dc383387f01dc439b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00670.html b/components/els_pkc/doc/mcxn/html/a00670.html new file mode 100644 index 000000000..ec37793da --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00670.html @@ -0,0 +1,272 @@ + + + + + + + +MCUX CLNS: mcuxClAes_KeyTypes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClAes_KeyTypes
+
+
+ +

Defines of supported key types of mcuxClAes, see mcuxClKey. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128
 Key type structure for AES-128 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes128
 Key type pointer for AES-128 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192
 Key type structure for AES-192 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes192
 Key type pointer for AES-192 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256
 Key type structure for AES-256 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Aes256
 Key type pointer for AES-256 based keys. More...
 
+

Detailed Description

+

Defines of supported key types of mcuxClAes, see mcuxClKey.

+

Variable Documentation

+ +

◆ mcuxClKey_TypeDescriptor_Aes128

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128
+
+ +

Key type structure for AES-128 based keys.

+ +
+
+ +

◆ mcuxClKey_Type_Aes128

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Aes128
+ 		+static
+
+ +

Key type pointer for AES-128 based keys.

+
Examples
mcuxClKey_example.c.
+
+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_Aes192

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192
+
+ +

Key type structure for AES-192 based keys.

+ +
+
+ +

◆ mcuxClKey_Type_Aes192

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Aes192
+ 		+static
+
+ +

Key type pointer for AES-192 based keys.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_Aes256

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256
+
+ +

Key type structure for AES-256 based keys.

+ +
+
+ +

◆ mcuxClKey_Type_Aes256

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Aes256
+ 		+static
+
+ +

Key type pointer for AES-256 based keys.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00670.js b/components/els_pkc/doc/mcxn/html/a00670.js new file mode 100644 index 000000000..ac230dc42 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00670.js @@ -0,0 +1,9 @@ +var a00670 = +[ + [ "mcuxClKey_TypeDescriptor_Aes128", "a00670.html#ga8f7fce2b87e12c68354d223b9a75dc37", null ], + [ "mcuxClKey_Type_Aes128", "a00670.html#ga8f0a74b8ec63f9bcfff2723f37602d0d", null ], + [ "mcuxClKey_TypeDescriptor_Aes192", "a00670.html#ga16e79ab35a7a7da20948688481fe15ad", null ], + [ "mcuxClKey_Type_Aes192", "a00670.html#gaaeae50366310367805cb6ae6d81d88b1", null ], + [ "mcuxClKey_TypeDescriptor_Aes256", "a00670.html#ga5a8d0b88ec6b1da1730d861ca6fb7f97", null ], + [ "mcuxClKey_Type_Aes256", "a00670.html#ga1249b014f089397821eceab3fd04ed5c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00671.html b/components/els_pkc/doc/mcxn/html/a00671.html new file mode 100644 index 000000000..122bfe9bc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00671.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClCipher + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClCipher
MCUX CL &ndash; API
+
+
+ +

Cipher component. +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 mcuxClCipher_Constants
 Constants of mcuxClCipher component.
 
 One-shot Cipher interfaces
 Interfaces to perform Cipher operations in one shot.
 
 Multi-part Cipher interfaces
 Interfaces to perform Cipher operations in multiple parts.
 
 Cipher type definitions
 Types used by the Cipher operations.
 
 Cipher mode definitions
 Modes used by the Cipher operations.
 
+

Detailed Description

+

Cipher component.

+

Cipher operations.

+

The mcuxClCipher component implements the Encryption and Decryption functionality supported by CLNS. It supports Symmetric encryption algorithms.

+

An example of how to use the mcuxClCipher component can be found in /mcuxClCipher/ex.

+

The component uses the ELS hardware. The ELS hardware has to be initialized, prior to calling any function of the mcuxClCipher component.

+

The mcuxClCipher component supports interfaces to either encrypt/decrypt a message in one shot (mcuxClCipher_crypt) or to encrypt/decrypt it in parts (mcuxClCipher_init, mcuxClCipher_process, and mcuxClCipher_finish). In case of encrypting/decrypting a message in parts, first an initialization has to be performed (mcuxClCipher_init), followed by zero, one or multiple updates (mcuxClCipher_process), followed by a finalization (mcuxClCipher_finish). The finalization generates the encrypted/decrypted output data and destroys the context. After the finalization step, no further updates are possible.

+

The targeted encryption algorithm is selected by passing one of the offered algorithm mode descriptors, which are available in the mcuxClCipherModes components.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00671.js b/components/els_pkc/doc/mcxn/html/a00671.js new file mode 100644 index 000000000..2a0560ba2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00671.js @@ -0,0 +1,8 @@ +var a00671 = +[ + [ "mcuxClCipher_Constants", "a00672.html", null ], + [ "One-shot Cipher interfaces", "a00674.html", null ], + [ "Multi-part Cipher interfaces", "a00675.html", null ], + [ "Cipher type definitions", "a00676.html", "a00676" ], + [ "Cipher mode definitions", "a00677.html", "a00677" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00672.html b/components/els_pkc/doc/mcxn/html/a00672.html new file mode 100644 index 000000000..db665921c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00672.html @@ -0,0 +1,158 @@ + + + + + + + +MCUX CLNS: mcuxClCipher_Constants + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClCipher_Constants
MCUX CL &ndash; API » mcuxClCipher
+
+
+ +

Constants of mcuxClCipher component. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLCIPHER_STATUS_ERROR
 
+#define MCUXCLCIPHER_STATUS_FAILURE
 
+#define MCUXCLCIPHER_STATUS_INVALID_INPUT
 
+#define MCUXCLCIPHER_STATUS_ERROR_MEMORY_ALLOCATION
 
+#define MCUXCLCIPHER_STATUS_FAULT_ATTACK
 
+#define MCUXCLCIPHER_STATUS_OK
 
+#define MCUXCLCIPHER_STATUS_JOB_STARTED
 
+#define MCUXCLCIPHER_STATUS_JOB_COMPLETED
 
+#define MCUXCLCIPHER_STATUS_JOB_UNAVAILABLE
 
+

Detailed Description

+

Constants of mcuxClCipher component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00673.html b/components/els_pkc/doc/mcxn/html/a00673.html new file mode 100644 index 000000000..ad4797530 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00673.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: MCUX CL – API + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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MCUX CL – API
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+Modules

 mcuxClCipher
 Cipher component.
 
 mcuxClKey
 mcuxClKey component
 
 mcuxClMac
 Message Authentication Code (MAC) componentThe mcuxClMac component implements Message Authentication Code (MAC) calculation, based on either HMAC or CMAC.
 
 Random PATCH_MODE API
 Random operations in PATCH_MODE.
 
 Random TEST_MODE API
 Random operations in TEST_MODE.
 
 mcuxClAead
 Hash component.
 
 Core API
 Essential types and functionality.
 
 HMAC Modes API
 HMAC mode operations.
 
 MAC Modes API
 Message Authentication Code (MAC) mode operations.
 
+

Detailed Description

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00673.js b/components/els_pkc/doc/mcxn/html/a00673.js new file mode 100644 index 000000000..a245f5b62 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00673.js @@ -0,0 +1,12 @@ +var a00673 = +[ + [ "mcuxClCipher", "a00671.html", "a00671" ], + [ "mcuxClKey", "a00784.html", "a00784" ], + [ "mcuxClMac", "a00794.html", "a00794" ], + [ "Random PATCH_MODE API", "a00834.html", null ], + [ "Random TEST_MODE API", "a00836.html", null ], + [ "mcuxClAead", "a00661.html", "a00661" ], + [ "Core API", "a00917.html", "a00917" ], + [ "HMAC Modes API", "a00961.html", "a00961" ], + [ "MAC Modes API", "a00962.html", "a00962" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00674.html b/components/els_pkc/doc/mcxn/html/a00674.html new file mode 100644 index 000000000..464be8c9c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00674.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: One-shot Cipher interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ + +
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+
+
One-shot Cipher interfaces
MCUX CL &ndash; API » mcuxClCipher
+
+
+ +

Interfaces to perform Cipher operations in one shot. +More...

+

Interfaces to perform Cipher operations in one shot.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00675.html b/components/els_pkc/doc/mcxn/html/a00675.html new file mode 100644 index 000000000..545916f6c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00675.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: Multi-part Cipher interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Multi-part Cipher interfaces
MCUX CL &ndash; API » mcuxClCipher
+
+
+ +

Interfaces to perform Cipher operations in multiple parts. +More...

+

Interfaces to perform Cipher operations in multiple parts.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00676.html b/components/els_pkc/doc/mcxn/html/a00676.html new file mode 100644 index 000000000..f7c49da4f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00676.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: Cipher type definitions + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Typedefs
+
+
Cipher type definitions
MCUX CL &ndash; API » mcuxClCipher
+
+
+ +

Types used by the Cipher operations. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t
 Cipher mode/algorithm descriptor type. More...
 
typedef const mcuxClCipher_ModeDescriptor_t *const mcuxClCipher_Mode_t
 Cipher mode/algorithm type. More...
 
typedef struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t
 Cipher selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClCipher_TestDescriptor_t *const mcuxClCipher_Test_t
 Cipher selftest mode/algorithm type. More...
 
typedef struct mcuxClCipher_Context mcuxClCipher_Context_t
 Cipher context type. More...
 
typedef uint32_t mcuxClCipher_Status_t
 Cipher status code. More...
 
+

Detailed Description

+

Types used by the Cipher operations.

+

Typedef Documentation

+ +

◆ mcuxClCipher_ModeDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t
+
+ +

Cipher mode/algorithm descriptor type.

+

This type captures all the information that the Cipher interfaces need to know about a particular Cipher mode/algorithm.

+ +
+
+ +

◆ mcuxClCipher_Mode_t

+ +
+
+ + + + +
typedef const mcuxClCipher_ModeDescriptor_t* const mcuxClCipher_Mode_t
+
+ +

Cipher mode/algorithm type.

+

This type is used to refer to a Cipher mode/algorithm.

+ +
+
+ +

◆ mcuxClCipher_TestDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t
+
+ +

Cipher selftest mode/algorithm descriptor type.

+

This type captures all the information that the Cipher selftest interfaces need to know about a particular Cipher selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClCipher_Test_t

+ +
+
+ + + + +
typedef const mcuxClCipher_TestDescriptor_t* const mcuxClCipher_Test_t
+
+ +

Cipher selftest mode/algorithm type.

+

This type is used to refer to a Cipher selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClCipher_Context_t

+ +
+
+ + + + +
typedef struct mcuxClCipher_Context mcuxClCipher_Context_t
+
+ +

Cipher context type.

+

This type is used in the multi-part interfaces to store the information about the current operation and the relevant internal state.

+ +
+
+ +

◆ mcuxClCipher_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClCipher_Status_t
+
+ +

Cipher status code.

+

This type provides information about the status of the Cipher operation that has been performed.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00676.js b/components/els_pkc/doc/mcxn/html/a00676.js new file mode 100644 index 000000000..fc7ed9ac2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00676.js @@ -0,0 +1,9 @@ +var a00676 = +[ + [ "mcuxClCipher_ModeDescriptor_t", "a00676.html#gaa9586d961025bb80660a563be606451e", null ], + [ "mcuxClCipher_Mode_t", "a00676.html#gacd434e81399ac5f9752f61d55ecfb305", null ], + [ "mcuxClCipher_TestDescriptor_t", "a00676.html#gae10b2dde7d4883d6992adb3e23d57714", null ], + [ "mcuxClCipher_Test_t", "a00676.html#ga2d2ad865d5d552ea37a471acb2c48a74", null ], + [ "mcuxClCipher_Context_t", "a00676.html#ga9faa78dbb34107f8f28344b36b91c93d", null ], + [ "mcuxClCipher_Status_t", "a00676.html#gadcf65a3850bca1bd4059213edf23df4f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00677.html b/components/els_pkc/doc/mcxn/html/a00677.html new file mode 100644 index 000000000..b4021a390 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00677.html @@ -0,0 +1,638 @@ + + + + + + + +MCUX CLNS: Cipher mode definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Variables
+
+
Cipher mode definitions
MCUX CL &ndash; API » mcuxClCipher
+
+
+ +

Modes used by the Cipher operations. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding
 AES ECB Encryption mode descriptor without padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding
 AES ECB Encryption mode without padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1
 AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 1. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1
 AES ECB Encryption mode with ISO/IEC 9797-1 padding method 1. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2
 AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 2. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2
 AES ECB Encryption mode with ISO/IEC 9797-1 padding method 2. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7
 AES ECB Encryption mode descriptor with PKCS7 padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7
 AES ECB Encryption mode with PKCS7 padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec
 AES ECB Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding
 AES ECB Decryption mode. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding
 AES CBC Encryption mode descriptor without padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding
 AES CBC Encryption mode without padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1
 AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 1. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1
 AES CBC Encryption mode with ISO/IEC 9797-1 padding method 1. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2
 AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 2. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2
 AES CBC Encryption mode with ISO/IEC 9797-1 padding method 2. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7
 AES CBC Encryption mode descriptor with PKCS7 padding. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7
 AES CBC Encryption mode with PKCS7 padding. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec
 AES CBC Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding
 AES CBC Decryption mode. More...
 
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR
 CTR Encryption/Decryption mode descriptor. More...
 
static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR
 CTR Encryption/Decryption mode. More...
 
+

Detailed Description

+

Modes used by the Cipher operations.

+

Variable Documentation

+ +

◆ mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding
+
+ +

AES ECB Encryption mode descriptor without padding.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_ECB_Enc_NoPadding

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding
+ 		+static
+
+ +

AES ECB Encryption mode without padding.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1
+
+ +

AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1
+ 		+static
+
+ +

AES ECB Encryption mode with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2
+
+ +

AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 2.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2
+ 		+static
+
+ +

AES ECB Encryption mode with ISO/IEC 9797-1 padding method 2.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7
+
+ +

AES ECB Encryption mode descriptor with PKCS7 padding.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7
+ 		+static
+
+ +

AES ECB Encryption mode with PKCS7 padding.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_ECB_Dec

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec
+
+ +

AES ECB Decryption mode descriptor.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_ECB_Dec_NoPadding

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding
+ 		+static
+
+ +

AES ECB Decryption mode.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding
+
+ +

AES CBC Encryption mode descriptor without padding.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CBC_Enc_NoPadding

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding
+ 		+static
+
+ +

AES CBC Encryption mode without padding.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1
+
+ +

AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1
+ 		+static
+
+ +

AES CBC Encryption mode with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2
+
+ +

AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 2.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2
+ 		+static
+
+ +

AES CBC Encryption mode with ISO/IEC 9797-1 padding method 2.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7
+
+ +

AES CBC Encryption mode descriptor with PKCS7 padding.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CBC_Enc_PKCS7

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7
+ 		+static
+
+ +

AES CBC Encryption mode with PKCS7 padding.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CBC_Dec

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec
+
+ +

AES CBC Decryption mode descriptor.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CBC_Dec_NoPadding

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding
+ 		+static
+
+ +

AES CBC Decryption mode.

+ +
+
+ +

◆ mcuxClCipher_ModeDescriptor_AES_CTR

+ +
+
+ + + + +
const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR
+
+ +

CTR Encryption/Decryption mode descriptor.

+ +
+
+ +

◆ mcuxClCipher_Mode_AES_CTR

+ +
+
+ + + + + +
+ + + + +
mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR
+ 		+static
+
+ +

CTR Encryption/Decryption mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00677.js b/components/els_pkc/doc/mcxn/html/a00677.js new file mode 100644 index 000000000..d73545458 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00677.js @@ -0,0 +1,25 @@ +var a00677 = +[ + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding", "a00677.html#ga6d4a742e7880955c34b446d8d7ac4b18", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_NoPadding", "a00677.html#gac5863201c397e8418c5284523119ea41", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1", "a00677.html#gae27dec2288073dac847fa49e1f3e9dd8", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1", "a00677.html#ga5c3dcb833ab559f75065e0e340b02886", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2", "a00677.html#ga887163d5d571468467116cf2017f00a9", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2", "a00677.html#gae741b5b27af200b377425049545f6779", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7", "a00677.html#gad0e87e50be9066b625215cda60152589", null ], + [ "mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7", "a00677.html#ga76508d5bd12946fbb9b52749dac9f528", null ], + [ "mcuxClCipher_ModeDescriptor_AES_ECB_Dec", "a00677.html#ga4a86accbf3ed6f707bca9208464b0fe8", null ], + [ "mcuxClCipher_Mode_AES_ECB_Dec_NoPadding", "a00677.html#gade75d09ba133c93d3e46eb1c795bb451", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding", "a00677.html#ga2cf616ea2d030fbe13a8b1ce8a3a6fa8", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_NoPadding", "a00677.html#ga807a672d6329f9c7d3beaabca651d517", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1", "a00677.html#ga22e8dfabe8c99f091cd41beeade83b2c", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1", "a00677.html#ga20b89472f917ef5dcd1493e349a2851c", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2", "a00677.html#ga270643be668dfd110388711cae932bd6", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2", "a00677.html#ga3656eebb0f185f9bec04f0cb293c42db", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7", "a00677.html#gab68a0cefd449150330bc4882ca957396", null ], + [ "mcuxClCipher_Mode_AES_CBC_Enc_PKCS7", "a00677.html#gad8399b835f6d454f0fa15b2b0ca41ee4", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CBC_Dec", "a00677.html#ga4c8f02ead08c8c20259cf0c0120c8420", null ], + [ "mcuxClCipher_Mode_AES_CBC_Dec_NoPadding", "a00677.html#gafcea66751b4008e0b5c9f3d3b982a3a4", null ], + [ "mcuxClCipher_ModeDescriptor_AES_CTR", "a00677.html#ga93287cc9cd970f5c9103f1cc597027e0", null ], + [ "mcuxClCipher_Mode_AES_CTR", "a00677.html#ga6f1b191b97196025c65851958eb2a700", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00678.html b/components/els_pkc/doc/mcxn/html/a00678.html new file mode 100644 index 000000000..7f8d54264 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00678.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: Core type definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
Core type definitions
MCUX CL &ndash; API » Core API
+
+
+ +

Types used by basically all operations. +More...

+ + + + + + + + +

+Typedefs

typedef const uint8_t *const mcuxCl_InputBuffer_t
 Input buffer typeThis type provides a pointer to the memory location that should be used to read input data from. More...
 
typedef uint8_t *const mcuxCl_Buffer_t
 Generic buffer typeThis type provides a pointer to the memory location that can be used for both reading input data and writing output data. More...
 
+

Detailed Description

+

Types used by basically all operations.

+

Typedef Documentation

+ +

◆ mcuxCl_InputBuffer_t

+ +
+
+ + + + +
typedef const uint8_t* const mcuxCl_InputBuffer_t
+
+ +

Input buffer typeThis type provides a pointer to the memory location that should be used to read input data from.

+ +
+
+ +

◆ mcuxCl_Buffer_t

+ +
+
+ + + + +
typedef uint8_t* const mcuxCl_Buffer_t
+
+ +

Generic buffer typeThis type provides a pointer to the memory location that can be used for both reading input data and writing output data.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00678.js b/components/els_pkc/doc/mcxn/html/a00678.js new file mode 100644 index 000000000..2f6e62605 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00678.js @@ -0,0 +1,5 @@ +var a00678 = +[ + [ "mcuxCl_InputBuffer_t", "a00678.html#gae1ad733bc1a05d9dc6e9fb8b0e9b436d", null ], + [ "mcuxCl_Buffer_t", "a00678.html#gaa29a7ef1a28440e75f2c0d007011ae2b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00679.html b/components/els_pkc/doc/mcxn/html/a00679.html new file mode 100644 index 000000000..a60f9061d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00679.html @@ -0,0 +1,155 @@ + + + + + + + +MCUX CLNS: mcuxClEcc + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEcc
+
+
+ +

Elliptic Curve Cryptography component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 mcuxClEcc_Constants
 Defines constants of mcuxClEcc.
 
 mcuxClEcc_Functions
 Defines all functions of mcuxClEcc.
 
 mcuxClEcc_KeyTypeDescriptors
 Definitions of ECC related key type descriptors.
 
 mcuxClEcc_MemoryConsumption
 Defines the memory consumption for the mcuxClEcc component.
 
 mcuxClEcc_ParameterSizes
 Defines domain parameter, key and signature sizes of mcuxClEcc.
 
 mcuxClEcc_Macros
 Defines all macros of mcuxClEcc.
 
 mcuxClEcc_Types
 Defines all types of mcuxClEcc.
 
 mcuxClEcc_Descriptors
 Defines descriptors of mcuxClEcc.
 
+

Detailed Description

+

Elliptic Curve Cryptography component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00679.js b/components/els_pkc/doc/mcxn/html/a00679.js new file mode 100644 index 000000000..59cc76d79 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00679.js @@ -0,0 +1,11 @@ +var a00679 = +[ + [ "mcuxClEcc_Constants", "a00680.html", null ], + [ "mcuxClEcc_Functions", "a00681.html", "a00681" ], + [ "mcuxClEcc_KeyTypeDescriptors", "a00682.html", "a00682" ], + [ "mcuxClEcc_MemoryConsumption", "a00683.html", "a00683" ], + [ "mcuxClEcc_ParameterSizes", "a00684.html", "a00684" ], + [ "mcuxClEcc_Macros", "a00685.html", "a00685" ], + [ "mcuxClEcc_Types", "a00686.html", "a00686" ], + [ "mcuxClEcc_Descriptors", "a00687.html", "a00687" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00680.html b/components/els_pkc/doc/mcxn/html/a00680.html new file mode 100644 index 000000000..213f8aae6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00680.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Variables
+
+
mcuxClEcc_Constants
mcuxClEcc
+
+
+ +

Defines constants of mcuxClEcc. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define mcuxClEcc_Weier_DomainParams_NIST_P192
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p192r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P224
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p224r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P256
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p256r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P384
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p384r1
 
+#define mcuxClEcc_Weier_DomainParams_NIST_P521
 
+#define mcuxClEcc_Weier_DomainParams_ansix9p521r1
 
+#define MCUXCLECC_EDDSA_PHFLAG_ZERO
 
+#define MCUXCLECC_EDDSA_PHFLAG_ONE
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve25519
 
+const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve448
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp160k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256k1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp384r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp521r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512r1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384t1
 
+const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512t1
 
+const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed25519
 
+const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed448
 
+

Detailed Description

+

Defines constants of mcuxClEcc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00681.html b/components/els_pkc/doc/mcxn/html/a00681.html new file mode 100644 index 000000000..78fee1be8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00681.html @@ -0,0 +1,910 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEcc_Functions
mcuxClEcc
+
+
+ +

Defines all functions of mcuxClEcc. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClEcc_Status_t mcuxClEcc_KeyGen (mcuxClSession_Handle_t pSession, const mcuxClEcc_KeyGen_Param_t *pParam)
 implements ECDSA key generation. More...
 
mcuxClEcc_Status_t mcuxClEcc_Sign (mcuxClSession_Handle_t pSession, const mcuxClEcc_Sign_Param_t *pParam)
 implements ECDSA signature generation. More...
 
mcuxClEcc_Status_t mcuxClEcc_Verify (mcuxClSession_Handle_t pSession, const mcuxClEcc_Verify_Param_t *pParam)
 implements ECDSA signature verification. More...
 
mcuxClEcc_Status_t mcuxClEcc_PointMult (mcuxClSession_Handle_t pSession, const mcuxClEcc_PointMult_Param_t *pParam)
 implements ECC point multiplication. More...
 
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyGeneration (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 implements ECC key pair generation step for a MontDh key agreement according to rfc7748. More...
 
mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyAgreement (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Handle_t otherKey, uint8_t *pOut, uint32_t *const pOutLength)
 implements ECC key agreement according to rfc7748. More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateKeyPair (mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
 This function implements the EdDSA key pair generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.5 and 5.2.5 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateSignature (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, uint8_t *pSignature, uint32_t *const pSignatureSize)
 This function implements the EdDSA signature generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.6 and 5.2.6 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_VerifySignature (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, const uint8_t *pIn, uint32_t inSize, const uint8_t *pSignature, uint32_t signatureSize)
 This function implements the EdDSA signature verification for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.7 and 5.2.7 of https://datatracker.ietf.org/doc/html/rfc8032). More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_InitPrivKeyInputMode (mcuxClSession_Handle_t pSession, mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, const uint8_t *pPrivKey)
 This function initializes an EdDSA mode descriptor for EdDSA key pair generation with private key input. More...
 
mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateProtocolDescriptor (mcuxClSession_Handle_t pSession, const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor, uint32_t phflag, mcuxCl_InputBuffer_t pContext, uint32_t contextLen)
 This function implements the protocol descriptor generation for Ed25519ctx, Ed25519ph, Ed448 and Ed448ph. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEcc.

+

Function Documentation

+ +

◆ mcuxClEcc_KeyGen()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_KeyGen (mcuxClSession_Handle_t pSession,
const mcuxClEcc_KeyGen_Param_t * pParam 
)
+
+ +

implements ECDSA key generation.

+
Return values
+ + + + + +
MCUXCLECC_STATUS_OKif private key and public key are generated successfully;
MCUXCLECC_STATUS_INVALID_PARAMSif parameters are invalid;
MCUXCLECC_STATUS_RNG_ERRORif random number (DRBG / PRNG) error (unexpected behavior);
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
+
+
+
Attention
This function uses DRBG and PRNG. Caller needs to check if DRBG and PRNG are ready.
+
Parameters
+ + + +
[in]pSessionpointer to mcuxClSession_Descriptor.
[in]pParampointer to ECDSA Key Generation parameter structure.
+
+
+ +
+
+ +

◆ mcuxClEcc_Sign()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_Sign (mcuxClSession_Handle_t pSession,
const mcuxClEcc_Sign_Param_t * pParam 
)
+
+ +

implements ECDSA signature generation.

+
Return values
+ + + + + +
MCUXCLECC_STATUS_OKif signature is generated successfully;
MCUXCLECC_STATUS_INVALID_PARAMSif parameters are invalid;
MCUXCLECC_STATUS_RNG_ERRORif random number (DRBG / PRNG) error (unexpected behavior);
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
+
+
+
Attention
This function uses DRBG and PRNG. Caller needs to check if DRBG and PRNG are ready.
+
Parameters
+ + + +
[in]pSessionpointer to mcuxClSession_Descriptor.
[in]pParampointer to ECDSA Sign parameter structure.
+
+
+ +
+
+ +

◆ mcuxClEcc_Verify()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_Verify (mcuxClSession_Handle_t pSession,
const mcuxClEcc_Verify_Param_t * pParam 
)
+
+ +

implements ECDSA signature verification.

+
Return values
+ + + + + +
MCUXCLECC_STATUS_OKif ECDSA Signature is valid;
MCUXCLECC_STATUS_INVALID_SIGNATUREif ECDSA Signature is invalid;
MCUXCLECC_STATUS_INVALID_PARAMSif parameters are invalid;
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
+
+
+
Parameters
+ + + +
[in]pSessionpointer to mcuxClSession_Descriptor.
[in]pParampointer to ECDSA Verify parameter structure.
+
+
+ +
+
+ +

◆ mcuxClEcc_PointMult()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClEcc_Status_t mcuxClEcc_PointMult (mcuxClSession_Handle_t pSession,
const mcuxClEcc_PointMult_Param_t * pParam 
)
+
+ +

implements ECC point multiplication.

+

This API performs elliptic curve point multiplication on the given elliptic curve in short Weierstrass form. This API does not check if the curve parameters and the given point are valid or not. Invalid curve parameters or point might cause the return of MCUXCLECC_STATUS_INVALID_PARAMS, invalid result, and unexpected behavior (e.g., the return of MCUXCLECC_STATUS_FAULT_ATTACK).

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Parameters
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[in]pSessionpointer to mcuxClSession_Descriptor.
[in]pParampointer to ECC point multiplication parameter structure.
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+
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Parameter properties
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pParam.curveParam.pG
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the base point is not used in this API. This pointer can be left unspecified.
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKif point multiplication is calculated successfully, and the result is not the neutral point;
MCUXCLECC_STATUS_INVALID_PARAMSif parameters are invalid;
MCUXCLECC_STATUS_NEUTRAL_POINTif result is the neutral point;
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
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Attention
This function uses PRNG. Caller needs to check if PRNG is ready.
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◆ mcuxClEcc_Mont_DhKeyGeneration()

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mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyGeneration (mcuxClSession_Handle_t pSession,
mcuxClKey_Type_t type,
mcuxClKey_Protection_t protection,
mcuxClKey_Handle_t privKey,
uint8_t * pPrivData,
uint32_t *const pPrivDataLength,
mcuxClKey_Handle_t pubKey,
uint8_t * pPubData,
uint32_t *const pPubDataLength 
)
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+ +

implements ECC key pair generation step for a MontDh key agreement according to rfc7748.

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This API performs elliptic curve key generation of the private key and calculates corresponding public key for MontDh key agreement This API does not check if the curve parameters are correct. This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK.

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Parameters
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[in]pSessionmcuxClSession_Descriptor structure
[in]typetype structure specifying requested key type to be generated. Also contains domain parameters
[in]protection#mcuxClKey_Protection structure
[out]privKeyprivate key handling structure
[out]pPrivDatabuffer for private key of the MCUXCLECC_MONT_CURVE25519/448_SIZE_PRIVATEKEY length
[out]pPrivDataLengthprivate key length
[out]pubKeypublic key handling structure
[out]pPubDatabuffer for public key x-coordinate of MCUXCLECC_MONT_CURVE25519/448_SIZE_PUBLICKEY length
[out]pPubDataLengthpublic key x-coordinate length
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+
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_ and MCUXCLECC_MONTDH_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKif key generation correctly calculate private and public keys, public key does not belong to the small subgroup.
MCUXCLECC_STATUS_RNG_ERRORif RNG return an error.
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
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Attention
This function uses PRNG. Caller needs to check if PRNG is ready.
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Examples
mcuxClEcc_Mont_Curve25519_example.c, and mcuxClEcc_Mont_Curve448_example.c.
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◆ mcuxClEcc_Mont_DhKeyAgreement()

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mcuxClEcc_Status_t mcuxClEcc_Mont_DhKeyAgreement (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
mcuxClKey_Handle_t otherKey,
uint8_t * pOut,
uint32_t *const pOutLength 
)
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+ +

implements ECC key agreement according to rfc7748.

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This API performs elliptic curve key agreement to compute shared secret between two parties using the function X25519 This API does not check if the curve parameters are correct. This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way This API might return MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP if generated public key lies in the small subgroup Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK.

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Parameters
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[in]pSessionpointer to mcuxClSession_Descriptor.
[in]keyprivate key handling structure
[in]otherKeypublic key handling structure
[out]pOutbuffer for shared secret of length MCUXCLECC_MONT_CURVE25519/448_SIZE_SHAREDSECRET
[out]pOutLengthshared secret length
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_ and MCUXCLECC_MONTDH_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKif key generation correctly calculate private and public keys, public key does not belong to the small subgroup.
MCUXCLECC_STATUS_RNG_ERRORif RNG return an error.
MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUPif calculated public key lies in small subgroup.
MCUXCLECC_STATUS_FAULT_ATTACKif fault attack (unexpected behavior) is detected.
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Attention
This function uses PRNG. Caller needs to check if PRNG is ready.
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Examples
mcuxClEcc_Mont_Curve25519_example.c, and mcuxClEcc_Mont_Curve448_example.c.
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◆ mcuxClEcc_EdDSA_GenerateKeyPair()

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mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateKeyPair (mcuxClSession_Handle_t pSession,
const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t * mode,
mcuxClKey_Handle_t privKey,
mcuxClKey_Handle_t pubKey 
)
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+ +

This function implements the EdDSA key pair generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.5 and 5.2.5 of https://datatracker.ietf.org/doc/html/rfc8032).

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For an M byte private key d, which is either generated internally at random or passed as input, this function calculates the private key hash H(d)=(h0,...,h{2b-1}) and deduces and returns

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  • the secret integer s
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  • the second half (hb,...,h{2b-1}) of the private key hash
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  • the public key Qenc=(s*G)enc where G is the base point.
    • +
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This API does not check if the curve parameters are correct. This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK.

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Parameters
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[in]pSessionHandle for the current CL session
[in]modeMode descriptor specifying the EdDSA GenerateKeyPair variant
[in/out]privKey Key handle for the private key.
[in/out]pubKey Key handle for the public key.
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKprivate key data and public key have been generated successfully
MCUXCLECC_STATUS_RNG_ERRORrandom number generation (DRBG / PRNG) error (unexpected behavior)
MCUXCLECC_STATUS_FAULT_ATTACKfault attack (unexpected behavior) is detected
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Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
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◆ mcuxClEcc_EdDSA_GenerateSignature()

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mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateSignature (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * mode,
const uint8_t * pIn,
uint32_t inSize,
uint8_t * pSignature,
uint32_t *const pSignatureSize 
)
+
+ +

This function implements the EdDSA signature generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.6 and 5.2.6 of https://datatracker.ietf.org/doc/html/rfc8032).

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For given hash prefix prefix (either dom2(x, y) or dom4(x, y) according to the chosen EdDSA variant; see Sections 5.1 and 5.2 of https://datatracker.ietf.org/doc/html/rfc8032), a message digest m', i.e. either the message itself for PureEdDSA or the message hash for HashEdDSA (see Section 4 of https://datatracker.ietf.org/doc/html/rfc8032), the signing keys s and (hb,...,h{2b-1}) derived from the private key d (see mcuxClEcc_EdDSA_GenerateKeyPair) and a public key Qenc, this function calculates an EdDSA signature (Renc,S), where Renc and S are given by 

- Renc = (r*G)enc
+- S = r+H(prefix||Renc||Qenc||m')*s mod n
+

where the secret scalar r is given by r=H(prefix||(hb,...,h{2b-1})||m') and G is the base point.

+

This API does not check if the curve parameters are correct. This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK.

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Parameters
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[in]pSessionHandle for the current CL session
[in]keyKey handle for private key related data which a.o. references the secret signing keys s and (hb,...,h{2b-1}) as well as the public key Qenc.
[in]modeMode descriptor specifying the EdDSA variant
[in]pInPointer to message digest m'
[in]inSizeSize of message digest m'
[out]pSignaturePointer to buffer where the signature (Renc,S) will be stored
[out]pSignatureSizeWill be set to the number of bytes of data that have been written to the pSignature buffer
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKsignature generation was successful
MCUXCLECC_STATUS_RNG_ERRORrandom number generation (DRBG / PRNG) error (unexpected behavior)
MCUXCLECC_STATUS_FAULT_ATTACKfault attack (unexpected behavior) is detected
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Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
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◆ mcuxClEcc_EdDSA_VerifySignature()

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mcuxClEcc_Status_t mcuxClEcc_EdDSA_VerifySignature (mcuxClSession_Handle_t session,
mcuxClKey_Handle_t key,
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * mode,
const uint8_t * pIn,
uint32_t inSize,
const uint8_t * pSignature,
uint32_t signatureSize 
)
+
+ +

This function implements the EdDSA signature verification for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.7 and 5.2.7 of https://datatracker.ietf.org/doc/html/rfc8032).

+

For given hash prefix prefix (either dom2(x, y) or dom4(x, y) according to the chosen EdDSA variant; see Sections 5.1 and 5.2 of https://datatracker.ietf.org/doc/html/rfc8032), a message digest m', i.e. either the message itself for PureEdDSA or the message hash for HashEdDSA (see Section 4 of https://datatracker.ietf.org/doc/html/rfc8032), and a public key Qenc, this function:

    +
  • verifies the public key Qenc
    • +
  • verifies that the signature component S satisfies S in [0,n-1]
    • +
  • verifies if the following signature equation holds:
      +
    • h*S*G=h*R+h*H(prefix||Renc||Qenc||m')*Q
      • +
    +
    • +
+

This API does not check if the curve parameters are correct. This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK.

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Parameters
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[in]sessionHandle for the current CL session
[in]keyKey handle for public key Qenc
[in]modeMode descriptor specifying the EdDSA variant
[in]pInPointer to message digest m'
[in]inSizeSize of message digest m'
[in]pSignaturePointer to buffer containing the signature (Renc,S)
[in]signatureSizeNumber of bytes of data in the pSignature buffer
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+
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Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
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Return values
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MCUXCLECC_STATUS_OKsignature verification passed
MCUXCLECC_STATUS_INVALID_SIGNATUREEdDSA signature is invalid
MCUXCLECC_STATUS_INVALID_PARAMSinput parameters are invalid
MCUXCLECC_STATUS_FAULT_ATTACKfault attack (unexpected behavior) is detected
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+
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Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, and mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c.
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◆ mcuxClEcc_EdDSA_InitPrivKeyInputMode()

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mcuxClEcc_Status_t mcuxClEcc_EdDSA_InitPrivKeyInputMode (mcuxClSession_Handle_t pSession,
mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t * mode,
const uint8_t * pPrivKey 
)
+
+ +

This function initializes an EdDSA mode descriptor for EdDSA key pair generation with private key input.

+
Parameters
+ + + + +
[in]pSessionHandle for the current CL session
[in/out]mode Pointer to mode descriptor to be initialized for EdDSA key pair generation with private key input
[in]pPrivKeyPointer to private key input
+
+
+
Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
+
Return values
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MCUXCLECC_STATUS_OKEdDSA mode descriptor has been initialized successfully
MCUXCLECC_STATUS_FAULT_ATTACKfault attack (unexpected behavior) is detected
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+
+
Examples
mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
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◆ mcuxClEcc_EdDSA_GenerateProtocolDescriptor()

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mcuxClEcc_Status_t mcuxClEcc_EdDSA_GenerateProtocolDescriptor (mcuxClSession_Handle_t pSession,
const mcuxClEcc_EdDSA_DomainParams_t * pDomainParams,
mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * pProtocolDescriptor,
uint32_t phflag,
mcuxCl_InputBuffer_t pContext,
uint32_t contextLen 
)
+
+ +

This function implements the protocol descriptor generation for Ed25519ctx, Ed25519ph, Ed448 and Ed448ph.

+
Parameters
+ + + + + + + +
[in]pSessionpointer to mcuxClSession_Descriptor
[in]pDomainParamsPointer to domain parameters of the used curve
[in]pProtocolDescriptorProtocol descriptor specifying the EdDSA variant
[in]phflagOption whether pre-hashing is enabled
[in]pContextUser input context for the hash prefix
[in]contextLenLength of the context
+
+
+
Returns
A code-flow protected error code (see MCUXCLECC_STATUS_)
+
Return values
+ + + +
MCUXCLECC_STATUS_OKsignature verification passed
MCUXCLECC_STATUS_FAULT_ATTACKfault attack (unexpected behavior) is detected
+
+
+
Examples
mcuxClEcc_EdDSA_Ed25519ctx_example.c, and mcuxClEcc_EdDSA_Ed25519ph_example.c.
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00681.js b/components/els_pkc/doc/mcxn/html/a00681.js new file mode 100644 index 000000000..b143c8900 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00681.js @@ -0,0 +1,14 @@ +var a00681 = +[ + [ "mcuxClEcc_KeyGen", "a00681.html#gabc728b0278908265f9923535391005dc", null ], + [ "mcuxClEcc_Sign", "a00681.html#ga105ec4e9dc29573334f52979381686de", null ], + [ "mcuxClEcc_Verify", "a00681.html#ga80f15538ec3cb2d3bfa8dc2f2da86366", null ], + [ "mcuxClEcc_PointMult", "a00681.html#gab199a221c61f252a0c755ab8d8a6a77c", null ], + [ "mcuxClEcc_Mont_DhKeyGeneration", "a00681.html#ga71406ab7d35c51f12c01efcb73305196", null ], + [ "mcuxClEcc_Mont_DhKeyAgreement", "a00681.html#gaef77a1a80276b44da54c66a8d606f20d", null ], + [ "mcuxClEcc_EdDSA_GenerateKeyPair", "a00681.html#ga0ac2814cb9c8f4b8718a95d8c2ae2b85", null ], + [ "mcuxClEcc_EdDSA_GenerateSignature", "a00681.html#ga0b9ad0b0aa3afccae32a14aeddf9d8fe", null ], + [ "mcuxClEcc_EdDSA_VerifySignature", "a00681.html#ga514b29374472b14ad00e0e5ef3469c7f", null ], + [ "mcuxClEcc_EdDSA_InitPrivKeyInputMode", "a00681.html#ga78eaff72d9c8202b51c61c6668b9c3aa", null ], + [ "mcuxClEcc_EdDSA_GenerateProtocolDescriptor", "a00681.html#ga54e3517cb9729321cdb4017b0fdc4485", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00682.html b/components/els_pkc/doc/mcxn/html/a00682.html new file mode 100644 index 000000000..19d9dbce1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00682.html @@ -0,0 +1,2997 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_KeyTypeDescriptors + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros | +Variables
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mcuxClEcc_KeyTypeDescriptors
mcuxClEcc
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Definitions of ECC related key type descriptors. +More...

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+Macros

#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-192. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-192. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-224. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-224. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-256. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-256. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-384. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-384. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub
 Key type structure for public ECC keys for Weierstrass curve NIST P-521. More...
 
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv
 Key type structure for private ECC keys for Weierstrass curve NIST P-521. More...
 
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+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp160k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp160k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp160k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp160k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp192k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp192k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp192k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp224k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp224k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp224k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp256k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp256k1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp256k1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
 Key type structure for public ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp521r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
 Key type structure for private ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve secp521r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-192. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-224. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-224. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-256. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-384. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-384. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-521. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv
 Key type pointer for private ECC keys for Weierstrass curve NIST P-521. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP160r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP160r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP160r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP192r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP192r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP224r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP224r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP256r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP256r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP320r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP320r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP320r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP384r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP384r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP512r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP512r1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP512r1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP160t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP160t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP160t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP192t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP192t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP192t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP224t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP224t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP224t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP256t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP256t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP256t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP320t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP320t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP320t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP384t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP384t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP384t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub
 Key type structure for public ECC keys for Weierstrass curve brainpoolP512t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub
 Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv
 Key type structure for private ECC keys for Weierstrass curve brainpoolP512t1. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv
 Key type pointer for private ECC keys for Weierstrass curve brainpoolP512t1. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv
 Key type structure for ECC EdDSA Ed25519 private keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv
 Key type pointer for ECC EdDSA Ed25519 private keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub
 Key type structure for ECC EdDSA Ed25519 public keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub
 Key type pointer for ECC EdDSA Ed25519 public keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv
 Key type structure for ECC EdDSA Ed448 private keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv
 Key type pointer for ECC EdDSA Ed448 private keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub
 Key type structure for ECC EdDSA Ed448 public keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub
 Key type pointer for ECC EdDSA Ed448 public keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair
 Key type structure for ECC MontDH Curve25519 Key pairs. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair
 Key type pointer for ECC MontDH Curve25519 Key pairs. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair
 Key type structure for ECC MontDH Curve448 Key pairs. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair
 Key type pointer for ECC MontDH Curve448 Key pairs. More...
 
+

Detailed Description

+

Definitions of ECC related key type descriptors.

+

Macro Definition Documentation

+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve NIST P-192.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve NIST P-192.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve NIST P-224.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve NIST P-224.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve NIST P-256.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve NIST P-256.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve NIST P-384.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve NIST P-384.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve NIST P-521.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv

+ +
+
+ + + + +
#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve NIST P-521.

+ +
+
+

Variable Documentation

+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp160k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp160k1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp160k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp160k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp160k1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp160k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp192k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp192k1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp192k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp192k1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp192k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp224k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp224k1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp224k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp224k1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp224k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp256k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp256k1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp256k1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp256k1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp256k1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp192r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp192r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp192r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp192r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp192r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp224r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp224r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp224r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp224r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp224r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp256r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp256r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp256r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp256r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp256r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp384r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp384r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp384r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp384r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp384r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp384r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve secp521r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp521r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp521r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve secp521r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_secp521r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve secp521r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P192_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-192.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P192_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve NIST P-256.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P224_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-224.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P224_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve NIST P-224.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P256_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-256.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P256_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve NIST P-256.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P384_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-384.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P384_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve NIST P-384.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P521_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-521.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_NIST_P521_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve NIST P-521.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP160r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP160r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP160r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP192r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP192r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP192r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP224r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP224r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP224r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP256r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP256r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP256r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP320r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP320r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP320r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP384r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP384r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP384r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP512r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP512r1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP512r1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP160t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP160t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP160t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP192t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP192t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP192t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP224t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP224t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP224t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP256t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP256t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP256t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP320t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP320t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP320t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP384t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP384t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP384t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub
+
+ +

Key type structure for public ECC keys for Weierstrass curve brainpoolP512t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub
+ 		+static
+
+ +

Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv
+
+ +

Key type structure for private ECC keys for Weierstrass curve brainpoolP512t1.

+ +
+
+ +

◆ mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv
+ 		+static
+
+ +

Key type pointer for private ECC keys for Weierstrass curve brainpoolP512t1.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv
+
+ +

Key type structure for ECC EdDSA Ed25519 private keys.

+ +
+
+ +

◆ mcuxClKey_Type_EdDSA_Ed25519_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv
+ 		+static
+
+ +

Key type pointer for ECC EdDSA Ed25519 private keys.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
+
+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub
+
+ +

Key type structure for ECC EdDSA Ed25519 public keys.

+ +
+
+ +

◆ mcuxClKey_Type_EdDSA_Ed25519_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub
+ 		+static
+
+ +

Key type pointer for ECC EdDSA Ed25519 public keys.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, and mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c.
+
+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv
+
+ +

Key type structure for ECC EdDSA Ed448 private keys.

+ +
+
+ +

◆ mcuxClKey_Type_EdDSA_Ed448_Priv

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv
+ 		+static
+
+ +

Key type pointer for ECC EdDSA Ed448 private keys.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub
+
+ +

Key type structure for ECC EdDSA Ed448 public keys.

+ +
+
+ +

◆ mcuxClKey_Type_EdDSA_Ed448_Pub

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub
+ 		+static
+
+ +

Key type pointer for ECC EdDSA Ed448 public keys.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair
+
+ +

Key type structure for ECC MontDH Curve25519 Key pairs.

+ +
+
+ +

◆ mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair
+ 		+static
+
+ +

Key type pointer for ECC MontDH Curve25519 Key pairs.

+
Examples
mcuxClEcc_Mont_Curve25519_example.c.
+
+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair
+
+ +

Key type structure for ECC MontDH Curve448 Key pairs.

+ +
+
+ +

◆ mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair
+ 		+static
+
+ +

Key type pointer for ECC MontDH Curve448 Key pairs.

+
Examples
mcuxClEcc_Mont_Curve448_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00682.js b/components/els_pkc/doc/mcxn/html/a00682.js new file mode 100644 index 000000000..6fdbd750f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00682.js @@ -0,0 +1,127 @@ +var a00682 = +[ + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub", "a00682.html#ga697b811095baa95d968a6710b78dda40", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv", "a00682.html#gaf0d412d5ea6506c4afa947ef3d17646c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub", "a00682.html#ga40820475ba5218c1746f3de54035367f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv", "a00682.html#gaf049264c890164b02d97139deb8c1471", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub", "a00682.html#ga66bb90651426a91d158794a3c79df29f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv", "a00682.html#gab13c07ea082e362aefed4814123ff724", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub", "a00682.html#gadad85b76aaf6f7c99a0264392a31a5a1", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv", "a00682.html#ga5177e841e9f5754aded42239c95b4263", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub", "a00682.html#ga34397e23e613e3662aabe96baeb7dd99", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv", "a00682.html#gac4ff88aeb6544eee998bbe565e870856", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub", "a00682.html#ga45f80b52c3713407e5ea8d874fcab224", null ], + [ "mcuxClKey_Type_WeierECC_secp160k1_Pub", "a00682.html#ga4345462d03a5a61641bfbbd3a2d5b86e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv", "a00682.html#ga5be9d578c7e89fb9ddeb24ce1dd87705", null ], + [ "mcuxClKey_Type_WeierECC_secp160k1_Priv", "a00682.html#ga919b93483d11e303265fc8db41c4c03f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub", "a00682.html#gae82b0b8a866aa021d9be12d673ea44cb", null ], + [ "mcuxClKey_Type_WeierECC_secp192k1_Pub", "a00682.html#gaade00cdba0ae71d0ead7474186e8b9fa", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv", "a00682.html#ga4464ec90b697f37d0c77f371ffd25f73", null ], + [ "mcuxClKey_Type_WeierECC_secp192k1_Priv", "a00682.html#ga1bbeb45dc0f37b64ddf7d54890d1d5da", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub", "a00682.html#ga72e156ee2a9ac1c0808fb54be1c37854", null ], + [ "mcuxClKey_Type_WeierECC_secp224k1_Pub", "a00682.html#ga75e6fbe876aa640a0fade7940ed23c3b", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv", "a00682.html#gaacbea5c086db4ecfa1e481d64e64c034", null ], + [ "mcuxClKey_Type_WeierECC_secp224k1_Priv", "a00682.html#ga8754b1ec3ded884876adbb0145d1e054", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub", "a00682.html#gafb9d141d04c292a77577c8593f379dae", null ], + [ "mcuxClKey_Type_WeierECC_secp256k1_Pub", "a00682.html#ga41cecc27d7f37dfc1bca1158fa42af05", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv", "a00682.html#ga39040d5c10a5245ba45acb94304704f5", null ], + [ "mcuxClKey_Type_WeierECC_secp256k1_Priv", "a00682.html#ga9e922253404f7608e004929b2e994d7d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub", "a00682.html#gad6f5289ef5ca2a8675ab7086b35522df", null ], + [ "mcuxClKey_Type_WeierECC_secp192r1_Pub", "a00682.html#gaf003efa3e8861d0651ce6616abf5d919", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv", "a00682.html#ga9696729f938dcffb197bb7ec7cf68ab7", null ], + [ "mcuxClKey_Type_WeierECC_secp192r1_Priv", "a00682.html#ga000d450d23f8c6980674668531ad4727", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub", "a00682.html#ga243160a6bd14bfcfae0feab8cfec4444", null ], + [ "mcuxClKey_Type_WeierECC_secp224r1_Pub", "a00682.html#ga3b602493fe22f22f91da3f6159ebe79c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv", "a00682.html#ga9d9727c76f81c36e06c5202eced2d73b", null ], + [ "mcuxClKey_Type_WeierECC_secp224r1_Priv", "a00682.html#gabaef750bcfea399f7cf7e397d1b637e6", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub", "a00682.html#ga82bfa972e94322b417a5ddf43932a2ec", null ], + [ "mcuxClKey_Type_WeierECC_secp256r1_Pub", "a00682.html#gafc846d07facc686d0d6fcf7a46e7eb67", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv", "a00682.html#gaddbf6d8826069565a1e79fb24d8cb3b2", null ], + [ "mcuxClKey_Type_WeierECC_secp256r1_Priv", "a00682.html#gac945c22c4932453b64a0369e168aa05a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub", "a00682.html#ga21b1d68989a19b915dd5106075e29cb3", null ], + [ "mcuxClKey_Type_WeierECC_secp384r1_Pub", "a00682.html#ga5e8db8f1f69ba0886f3a568e3eef3777", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv", "a00682.html#gac745b76bab619fff5fe1146fb7d71a50", null ], + [ "mcuxClKey_Type_WeierECC_secp384r1_Priv", "a00682.html#ga4456ec80ccaa45cf7a715719acb9195d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub", "a00682.html#ga6269f061cab69e82df4cd7b9656c8a2c", null ], + [ "mcuxClKey_Type_WeierECC_secp521r1_Pub", "a00682.html#ga4922658a5dbdafb18e9a26aa62d047d9", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv", "a00682.html#ga06483f379dc8873d7cc30c300610e327", null ], + [ "mcuxClKey_Type_WeierECC_secp521r1_Priv", "a00682.html#ga8898847c8409dd00985474ce2bfd9e7b", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P192_Pub", "a00682.html#ga06b92e495eab87142fc07c469fac5526", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P192_Priv", "a00682.html#gab3bd456d3e79c18bb52852012a785a7c", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P224_Pub", "a00682.html#ga0a61957ec8619856fe03204d56bd7a14", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P224_Priv", "a00682.html#ga8449862f98fdfc750c8990a06e561bc7", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P256_Pub", "a00682.html#ga7f344daa7b996e30a163c9053f05ac5f", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P256_Priv", "a00682.html#gacc7e8ff2ac5a8a3d894d7a9da0a80341", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P384_Pub", "a00682.html#ga2ee917bf64caddab241b566099acf669", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P384_Priv", "a00682.html#ga690fd09dedd835e6d9e99e6de82f3ba0", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P521_Pub", "a00682.html#ga4fa543596682506a51f4078409dc3731", null ], + [ "mcuxClKey_Type_WeierECC_NIST_P521_Priv", "a00682.html#ga0b3881b7f5ef6077eaca0d37395a320e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub", "a00682.html#ga62389be1de20d8cf7dfdf9416766ce59", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub", "a00682.html#ga953ce0f67b3ba06382f7ca22eec53b3e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv", "a00682.html#gafee54bf1b90cab43955656fdf688e6b9", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv", "a00682.html#gadee38fd7f3c37112e45316828a1b421d", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub", "a00682.html#ga55895a7c4d7dbde9cb53e27ce4aadc36", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub", "a00682.html#ga6f2fdb757ee68215625ffb9d32bab892", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv", "a00682.html#gaf7713f17a5c6504d79a4cc19a619d1bf", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv", "a00682.html#ga58315a40eb971b7d1ae90d906eb30319", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub", "a00682.html#ga71ccfd1a0541def6aa05b24db3059b10", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub", "a00682.html#ga78e896c33933303cacce198571f1d525", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv", "a00682.html#ga2eefdf975f757f135792dedcc500c9f5", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv", "a00682.html#ga67db10ea32d18c91b828214d9d38ac8b", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub", "a00682.html#ga81ed0e23c5cb230eaf68b43e2d037dde", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub", "a00682.html#ga37b4c94b2e841b2f3eb2331083b76f5f", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv", "a00682.html#ga1c0248997a1ae57f004b96d063240fc7", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv", "a00682.html#ga9de0651cd7e19b5a7d5b3e782a8cdb78", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub", "a00682.html#ga3578f443c84fa6e97c7fa21bd5765461", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub", "a00682.html#ga91e507098e21780ba47f892d18197b26", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv", "a00682.html#ga3eb4a76b7cd7e5b04b69f1af7d430a24", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv", "a00682.html#ga073b9c815509c8321bdeb396d8f377d5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub", "a00682.html#ga72edef6223f86b15d63f282c0a9119bc", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub", "a00682.html#gade346aa31f4479a953d693d24be3005c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv", "a00682.html#ga4c70e1c0c3dec2ae4b89fd544987724b", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv", "a00682.html#ga8a996e206f32bd964d23537c41f27b25", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub", "a00682.html#gace90d3010bf72d3289a1f5ab249c07a2", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub", "a00682.html#ga90516c497fc468872c20797ea042d7d6", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv", "a00682.html#gac15a4416fa5fa537f67a456e68b9e81a", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv", "a00682.html#ga0973ccb9a10dba4e034096093ea24b22", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub", "a00682.html#gabe551efbcc35efcba391ee767b7f7ff0", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub", "a00682.html#ga8f69f4a645709620e99b354c8d28c57a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv", "a00682.html#ga3e834a29c37352e20f69567334a19ecb", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv", "a00682.html#ga84b46e442f069d514c5061a03c4e9190", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub", "a00682.html#ga5a4502575819fa65e4afad99ce4c1d77", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub", "a00682.html#gaee8f56b3741cb2d385321184ecc3112a", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv", "a00682.html#gaec947c583361285beabd1515b85ffa05", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv", "a00682.html#ga9c3d2aedc7cdee77f194a281a79d1b38", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub", "a00682.html#ga0532b3419b3886694736007f0b8e7944", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub", "a00682.html#gaa70ef1ac082befbd2bcb06a1990cf8ca", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv", "a00682.html#ga8b497f39e491a6301f7e27edf74a1d94", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv", "a00682.html#ga6965a5067cf306af93fa18b0d7c40bf5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub", "a00682.html#ga649b579900b6ff23d3009026fa4a7a3a", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub", "a00682.html#ga5d9afd44cd025fbb0b3fc05c0b207597", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv", "a00682.html#ga900bbb5cd092246e2bb83336df1af27e", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv", "a00682.html#ga5d0109f06ed0017ab64a625c290f84a0", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub", "a00682.html#ga45b70649d277b865e410beef5e815198", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub", "a00682.html#ga660a4eedac67861ac691f8e6cce31a2e", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv", "a00682.html#ga055bfc9d1fa07fcd80911a4483ee8989", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv", "a00682.html#ga9fd102f8a9a37098e7fbaccd56ccb66c", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub", "a00682.html#ga7cd3157e70c933ce8f646c6277d832b6", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub", "a00682.html#ga9efe52ae3219c7c1401dcd2be13b5bd0", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv", "a00682.html#gab5dc15b01d9c0d9dbf847026af187802", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv", "a00682.html#gaa83b67499981c694cc35d63173b908e5", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub", "a00682.html#gaa585fea86a1de6d3eee179053ff71396", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub", "a00682.html#ga1346153805fc80794dcd54135e18ded9", null ], + [ "mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv", "a00682.html#ga980f0af6070d632d144d38c34ca26d0e", null ], + [ "mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv", "a00682.html#ga6c0ef669e99f161073f329a5e08c7d10", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv", "a00682.html#gab98021bcb61d1707d87106ddae87439c", null ], + [ "mcuxClKey_Type_EdDSA_Ed25519_Priv", "a00682.html#ga4f21b03709a5cac0b713f4e930102af8", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub", "a00682.html#ga3adea0c5fb26beb91e9d5cc798b167fd", null ], + [ "mcuxClKey_Type_EdDSA_Ed25519_Pub", "a00682.html#gab1d91d013e28a086fd4e13175252c049", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv", "a00682.html#gab28b18fd50c1ec6bc4a05c56d1663046", null ], + [ "mcuxClKey_Type_EdDSA_Ed448_Priv", "a00682.html#ga5deb01671f213897a9d54c0e5b5b2ebe", null ], + [ "mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub", "a00682.html#gae06f9c4d573b51d538a42dfd2cbc4699", null ], + [ "mcuxClKey_Type_EdDSA_Ed448_Pub", "a00682.html#gab35aa6e48e5bd8eda0a1b27c897f81a2", null ], + [ "mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair", "a00682.html#gadfd782e0581049bb1fe40049295807f6", null ], + [ "mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair", "a00682.html#gadcf4ca8f2a1626610da5b9bea5be3d89", null ], + [ "mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair", "a00682.html#ga033a43f0faf219f0e18ced032e1ad694", null ], + [ "mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair", "a00682.html#gae9116a45b5bfb237470625ae7d0fb29b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00683.html b/components/els_pkc/doc/mcxn/html/a00683.html new file mode 100644 index 000000000..4c6ba9f33 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00683.html @@ -0,0 +1,195 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
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+Modules | +Macros
+
+
mcuxClEcc_MemoryConsumption
mcuxClEcc
+
+
+ +

Defines the memory consumption for the mcuxClEcc component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 MCUXCLECC_WACPU_
 Define the CPU workarea size required by mcuxClEcc APIs.
 
 MCUXCLECC_MONTDH_WACPU_
 Define the CPU workarea size required by mcuxClEcc MontDH APIs.
 
 MCUXCLECC_EDDSA_WACPU_
 Define the CPU workarea size required by mcuxClEcc EdDSA APIs.
 
 MCUXCLECC_WAPKC_
 Define the PKC workarea size required by mcuxClEcc APIs.
 
 MCUXCLECC_MONTDH_WAPKC_
 Define the PKC workarea size required by mcuxClEcc_Mont APIs.
 
 MCUXCLECC_EDDSA_WAPKC_
 Define the PKC workarea size required by mcuxClEcc EdDSA APIs.
 
 MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_
 Define for the EdDSA key pair generation descriptor size.
 
 MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_
 Define for the EdDSA signature protocol descriptor size.
 
+ + + + +

+Macros

#define MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(byteLenP, byteLenN)
 Define for the buffer size (in bytes) for optimized custom ECC Weierstrass domain parameters. More...
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClEcc component.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE( byteLenP,
 byteLenN 
)
+
+ +

Define for the buffer size (in bytes) for optimized custom ECC Weierstrass domain parameters.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00683.js b/components/els_pkc/doc/mcxn/html/a00683.js new file mode 100644 index 000000000..56ef363c6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00683.js @@ -0,0 +1,12 @@ +var a00683 = +[ + [ "MCUXCLECC_WACPU_", "a00918.html", "a00918" ], + [ "MCUXCLECC_MONTDH_WACPU_", "a00919.html", "a00919" ], + [ "MCUXCLECC_EDDSA_WACPU_", "a00920.html", "a00920" ], + [ "MCUXCLECC_WAPKC_", "a00921.html", "a00921" ], + [ "MCUXCLECC_MONTDH_WAPKC_", "a00922.html", "a00922" ], + [ "MCUXCLECC_EDDSA_WAPKC_", "a00923.html", "a00923" ], + [ "MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_", "a00924.html", "a00924" ], + [ "MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_", "a00925.html", "a00925" ], + [ "MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE", "a00683.html#gac8895d8165cf3c84b10ac986a30c37e4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00684.html b/components/els_pkc/doc/mcxn/html/a00684.html new file mode 100644 index 000000000..912a8044f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00684.html @@ -0,0 +1,230 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_ParameterSizes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Modules
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mcuxClEcc_ParameterSizes
mcuxClEcc
+
+
+ +

Defines domain parameter, key and signature sizes of mcuxClEcc. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 MCUXCLECC_MONT_CURVE25519_SIZE_
 MontDH parameter size definitions for Curve25519.
 
 MCUXCLECC_MONT_CURVE448_SIZE_
 MontDH parameter size definitions for Curve448.
 
 MCUXCLECC_WEIERECC_SECP160K1_SIZE_
 WeierECC parameter size definitions for secp160k1.
 
 MCUXCLECC_WEIERECC_SECP192K1_SIZE_
 WeierECC parameter size definitions for secp192k1.
 
 MCUXCLECC_WEIERECC_SECP224K1_SIZE_
 WeierECC parameter size definitions for secp224k1.
 
 MCUXCLECC_WEIERECC_SECP256K1_SIZE_
 WeierECC parameter size definitions for secp256k1.
 
 MCUXCLECC_WEIERECC_SECP192R1_SIZE_
 WeierECC parameter size definitions for secp192r1.
 
 MCUXCLECC_WEIERECC_SECP224R1_SIZE_
 WeierECC parameter size definitions for secp224r1.
 
 MCUXCLECC_WEIERECC_SECP256R1_SIZE_
 WeierECC parameter size definitions for secp256r1.
 
 MCUXCLECC_WEIERECC_SECP384R1_SIZE_
 WeierECC parameter size definitions for secp384r1.
 
 MCUXCLECC_WEIERECC_SECP521R1_SIZE_
 WeierECC parameter size definitions for secp521r1.
 
 MCUXCLECC_WEIERECC_NIST_P192_SIZE_
 WeierECC parameter size definitions for NIST P-192.
 
 MCUXCLECC_WEIERECC_NIST_P224_SIZE_
 WeierECC parameter size definitions for NIST P-224.
 
 MCUXCLECC_WEIERECC_NIST_P256_SIZE_
 WeierECC parameter size definitions for NIST P-256.
 
 MCUXCLECC_WEIERECC_NIST_P384_SIZE_
 WeierECC parameter size definitions for NIST P-384.
 
 MCUXCLECC_WEIERECC_NIST_P521_SIZE_
 WeierECC parameter size definitions for NIST P-521.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_
 WeierECC parameter size definitions for brainpoolP160r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_
 WeierECC parameter size definitions for brainpoolP192r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_
 WeierECC parameter size definitions for brainpoolP224r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_
 WeierECC parameter size definitions for brainpoolP256r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_
 WeierECC parameter size definitions for brainpoolP320r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_
 WeierECC parameter size definitions for brainpoolP384r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_
 WeierECC parameter size definitions for brainpoolP512r1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_
 WeierECC parameter size definitions for brainpoolP160t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_
 WeierECC parameter size definitions for brainpoolP192t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_
 WeierECC parameter size definitions for brainpoolP224t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_
 WeierECC parameter size definitions for brainpoolP256t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_
 WeierECC parameter size definitions for brainpoolP320t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_
 WeierECC parameter size definitions for brainpoolP384t1.
 
 MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_
 WeierECC parameter size definitions for brainpoolP512t1.
 
 MCUXCLECC_WEIERECC_MAX_SIZE
 Maximum size definitions for WeierECC parameters (ECC component officially supports up to 640 bit Weierstrass curves)
 
 MCUXCLECC_EDDSA_ED25519_SIZE_
 EdDSA parameter size definitions for Ed25519.
 
 MCUXCLECC_EDDSA_ED448_SIZE_
 EdDSA parameter size definitions for Ed448.
 
+

Detailed Description

+

Defines domain parameter, key and signature sizes of mcuxClEcc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00684.js b/components/els_pkc/doc/mcxn/html/a00684.js new file mode 100644 index 000000000..73226e110 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00684.js @@ -0,0 +1,36 @@ +var a00684 = +[ + [ "MCUXCLECC_MONT_CURVE25519_SIZE_", "a00926.html", null ], + [ "MCUXCLECC_MONT_CURVE448_SIZE_", "a00927.html", null ], + [ "MCUXCLECC_WEIERECC_SECP160K1_SIZE_", "a00928.html", null ], + [ "MCUXCLECC_WEIERECC_SECP192K1_SIZE_", "a00929.html", null ], + [ "MCUXCLECC_WEIERECC_SECP224K1_SIZE_", "a00930.html", null ], + [ "MCUXCLECC_WEIERECC_SECP256K1_SIZE_", "a00931.html", null ], + [ "MCUXCLECC_WEIERECC_SECP192R1_SIZE_", "a00932.html", null ], + [ "MCUXCLECC_WEIERECC_SECP224R1_SIZE_", "a00933.html", null ], + [ "MCUXCLECC_WEIERECC_SECP256R1_SIZE_", "a00934.html", null ], + [ "MCUXCLECC_WEIERECC_SECP384R1_SIZE_", "a00935.html", null ], + [ "MCUXCLECC_WEIERECC_SECP521R1_SIZE_", "a00936.html", null ], + [ "MCUXCLECC_WEIERECC_NIST_P192_SIZE_", "a00937.html", null ], + [ "MCUXCLECC_WEIERECC_NIST_P224_SIZE_", "a00938.html", null ], + [ "MCUXCLECC_WEIERECC_NIST_P256_SIZE_", "a00939.html", null ], + [ "MCUXCLECC_WEIERECC_NIST_P384_SIZE_", "a00940.html", null ], + [ "MCUXCLECC_WEIERECC_NIST_P521_SIZE_", "a00941.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_", "a00942.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_", "a00943.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_", "a00944.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_", "a00945.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_", "a00946.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_", "a00947.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_", "a00948.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_", "a00949.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_", "a00950.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_", "a00951.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_", "a00952.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_", "a00953.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_", "a00954.html", null ], + [ "MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_", "a00955.html", null ], + [ "MCUXCLECC_WEIERECC_MAX_SIZE", "a00956.html", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_", "a00957.html", "a00957" ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_", "a00958.html", "a00958" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00685.html b/components/els_pkc/doc/mcxn/html/a00685.html new file mode 100644 index 000000000..3b677059c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00685.html @@ -0,0 +1,180 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Typedefs
+
+
mcuxClEcc_Macros
mcuxClEcc
+
+
+ +

Defines all macros of mcuxClEcc. +More...

+ + + + + + + + +

+Modules

 MCUXCLECC_STATUS_
 mcuxClEcc return code definitions
 
 MCUXCLECC_MONTDH_STATUS_
 mcuxClEcc_Mont return code definitions
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClEcc_Status_t
 Type for mcuxClEcc component return codes. More...
 
typedef mcuxClEcc_Status_t mcuxClEcc_Status_Protected_t
 Deprecated type for mcuxClEcc component return codes. More...
 
+

Detailed Description

+

Defines all macros of mcuxClEcc.

+

Typedef Documentation

+ +

◆ mcuxClEcc_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClEcc_Status_t
+
+ +

Type for mcuxClEcc component return codes.

+ +
+
+ +

◆ mcuxClEcc_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClEcc_Status_t mcuxClEcc_Status_Protected_t
+
+ +

Deprecated type for mcuxClEcc component return codes.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00685.js b/components/els_pkc/doc/mcxn/html/a00685.js new file mode 100644 index 000000000..05adf136c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00685.js @@ -0,0 +1,7 @@ +var a00685 = +[ + [ "MCUXCLECC_STATUS_", "a00959.html", "a00959" ], + [ "MCUXCLECC_MONTDH_STATUS_", "a00960.html", "a00960" ], + [ "mcuxClEcc_Status_t", "a00685.html#gaf044f4a5eeeecc4ec5b01aed19f2fe41", null ], + [ "mcuxClEcc_Status_Protected_t", "a00685.html#ga3900d9bdb95a061d26b71f300318b6a1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00686.html b/components/els_pkc/doc/mcxn/html/a00686.html new file mode 100644 index 000000000..380b57eb8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00686.html @@ -0,0 +1,485 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs
+
+
mcuxClEcc_Types
mcuxClEcc
+
+
+ +

Defines all types of mcuxClEcc. +More...

+ + + + + + + + + + + + + + + + + +

+Data Structures

struct  mcuxClEcc_DomainParam_t
 Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p. More...
 
struct  mcuxClEcc_KeyGen_Param_t
 Parameter structure for function mcuxClEcc_KeyGen. More...
 
struct  mcuxClEcc_Sign_Param_t
 Parameter structure for function mcuxClEcc_Sign. More...
 
struct  mcuxClEcc_Verify_Param_t
 Parameter structure for function mcuxClEcc_Verify. More...
 
struct  mcuxClEcc_PointMult_Param_t
 Parameter structure for function mcuxClEcc_PointMult. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define mcuxClEcc_DomainParam_misc_Pack(byteLenN, byteLenP)
 mcuxClEcc macros and defines to pack or access components of misc parameter of mcuxClEcc_DomainParam_t More...
 
#define mcuxClEcc_DomainParam_misc_byteLenP_offset
 Offset of byteLenP in packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenP_mask
 Mask to extract byteLenP from packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenN_offset
 Offset of byteLenN in packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_DomainParam_misc_byteLenN_mask
 Mask to extract byteLenN from packed misc parameter of mcuxClEcc_DomainParam_t. More...
 
#define mcuxClEcc_Sign_Param_optLen_Pack(byteLenHash)
 mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Sign_Param_t More...
 
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_offset
 Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Sign_Param_t. More...
 
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_mask
 Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Sign_Param_t. More...
 
#define mcuxClEcc_Verify_Param_optLen_Pack(byteLenHash)
 mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Verify_Param_t More...
 
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_offset
 Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Verify_Param_t. More...
 
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_mask
 Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Verify_Param_t. More...
 
+ + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t
 Type for MontDH domain parameters. More...
 
typedef struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
 Type for EdDSA domain parameters. More...
 
typedef struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
 EdDSA GenerateKeyPair variant descriptor type. More...
 
typedef struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
 EdDSA SignatureProtocol variant descriptor type. More...
 
typedef struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
 Type for Weierstrass ECC domain parameters. More...
 
+

Detailed Description

+

Defines all types of mcuxClEcc.

+

Macro Definition Documentation

+ +

◆ mcuxClEcc_DomainParam_misc_Pack

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define mcuxClEcc_DomainParam_misc_Pack( byteLenN,
 byteLenP 
)
+
+ +

mcuxClEcc macros and defines to pack or access components of misc parameter of mcuxClEcc_DomainParam_t

+

Helper macro to pack misc parameter of mcuxClEcc_DomainParam_t

+ +
+
+ +

◆ mcuxClEcc_DomainParam_misc_byteLenP_offset

+ +
+
+ + + + +
#define mcuxClEcc_DomainParam_misc_byteLenP_offset
+
+ +

Offset of byteLenP in packed misc parameter of mcuxClEcc_DomainParam_t.

+ +
+
+ +

◆ mcuxClEcc_DomainParam_misc_byteLenP_mask

+ +
+
+ + + + +
#define mcuxClEcc_DomainParam_misc_byteLenP_mask
+
+ +

Mask to extract byteLenP from packed misc parameter of mcuxClEcc_DomainParam_t.

+ +
+
+ +

◆ mcuxClEcc_DomainParam_misc_byteLenN_offset

+ +
+
+ + + + +
#define mcuxClEcc_DomainParam_misc_byteLenN_offset
+
+ +

Offset of byteLenN in packed misc parameter of mcuxClEcc_DomainParam_t.

+ +
+
+ +

◆ mcuxClEcc_DomainParam_misc_byteLenN_mask

+ +
+
+ + + + +
#define mcuxClEcc_DomainParam_misc_byteLenN_mask
+
+ +

Mask to extract byteLenN from packed misc parameter of mcuxClEcc_DomainParam_t.

+ +
+
+ +

◆ mcuxClEcc_Sign_Param_optLen_Pack

+ +
+
+ + + + + + + + +
#define mcuxClEcc_Sign_Param_optLen_Pack( byteLenHash)
+
+ +

mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Sign_Param_t

+

Helper macro to pack optLen parameter of mcuxClEcc_Sign_Param_t

+ +
+
+ +

◆ mcuxClEcc_Sign_Param_optLen_byteLenHash_offset

+ +
+
+ + + + +
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_offset
+
+ +

Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Sign_Param_t.

+ +
+
+ +

◆ mcuxClEcc_Sign_Param_optLen_byteLenHash_mask

+ +
+
+ + + + +
#define mcuxClEcc_Sign_Param_optLen_byteLenHash_mask
+
+ +

Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Sign_Param_t.

+ +
+
+ +

◆ mcuxClEcc_Verify_Param_optLen_Pack

+ +
+
+ + + + + + + + +
#define mcuxClEcc_Verify_Param_optLen_Pack( byteLenHash)
+
+ +

mcuxClEcc macros and defines to pack or access components of optLen parameter of mcuxClEcc_Verify_Param_t

+

Helper macro to pack optLen parameter of mcuxClEcc_Verify_Param_t

+ +
+
+ +

◆ mcuxClEcc_Verify_Param_optLen_byteLenHash_offset

+ +
+
+ + + + +
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_offset
+
+ +

Offset of byteLenHash in packed optLen parameter of mcuxClEcc_Verify_Param_t.

+ +
+
+ +

◆ mcuxClEcc_Verify_Param_optLen_byteLenHash_mask

+ +
+
+ + + + +
#define mcuxClEcc_Verify_Param_optLen_byteLenHash_mask
+
+ +

Mask to extract byteLenHash from packed optLen parameter of mcuxClEcc_Verify_Param_t.

+ +
+
+

Typedef Documentation

+ +

◆ mcuxClEcc_MontDH_DomainParams_t

+ +
+
+ + + + +
typedef struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t
+
+ +

Type for MontDH domain parameters.

+ +
+
+ +

◆ mcuxClEcc_EdDSA_DomainParams_t

+ +
+
+ + + + +
typedef struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t
+
+ +

Type for EdDSA domain parameters.

+ +
+
+ +

◆ mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t
+
+ +

EdDSA GenerateKeyPair variant descriptor type.

+ +
+
+ +

◆ mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t
+
+ +

EdDSA SignatureProtocol variant descriptor type.

+ +
+
+ +

◆ mcuxClEcc_Weier_DomainParams_t

+ +
+
+ + + + +
typedef struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t
+
+ +

Type for Weierstrass ECC domain parameters.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00686.js b/components/els_pkc/doc/mcxn/html/a00686.js new file mode 100644 index 000000000..40109af41 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00686.js @@ -0,0 +1,56 @@ +var a00686 = +[ + [ "mcuxClEcc_DomainParam_t", "a00973.html", [ + [ "pA", "a00973.html#a5916c96212c7f76a61ddc0c8aa957ef5", null ], + [ "pB", "a00973.html#abcaf03eba7dd8f697e3e582de2aa1eef", null ], + [ "pP", "a00973.html#adbfda4ce0ba171e1aa6f52e6b564d1e4", null ], + [ "pG", "a00973.html#a63d99844f35b075f23980f9c405d034b", null ], + [ "pN", "a00973.html#a484854783a458fd3d3ab50bfd38afcf3", null ], + [ "misc", "a00973.html#a90f3bfeae254eaa0eb7f5d97f2123906", null ] + ] ], + [ "mcuxClEcc_KeyGen_Param_t", "a00977.html", [ + [ "curveParam", "a00977.html#a0396802978ddd78f753922c8dadadb18", null ], + [ "pPrivateKey", "a00977.html#a48dad4664822a37f78c78eca1e660a26", null ], + [ "pPublicKey", "a00977.html#a96680cb90b6901598b686b38edac1264", null ], + [ "optLen", "a00977.html#a6d0e636ce4f30294af6bcfe0ae717a01", null ] + ] ], + [ "mcuxClEcc_Sign_Param_t", "a00981.html", [ + [ "curveParam", "a00981.html#a9af6c185c258baa0a6a4b0080b35b1aa", null ], + [ "pHash", "a00981.html#aeccbb72505744e1f627b67b1f51508ef", null ], + [ "pPrivateKey", "a00981.html#a0e61b674ac7f46c4157397535d97ce81", null ], + [ "pSignature", "a00981.html#ae25d26ef489ff1614a0a6ab6abe9fc97", null ], + [ "optLen", "a00981.html#af5376d1c58c5cfaf33ae6156572700ff", null ] + ] ], + [ "mcuxClEcc_Verify_Param_t", "a00985.html", [ + [ "curveParam", "a00985.html#a58660c912b751cbea8360e214c482b42", null ], + [ "pPrecG", "a00985.html#ae5ba73e49b3346a860000f13d05bfbf0", null ], + [ "pHash", "a00985.html#adb5823e73ed5542ddd0b4a7103e62f1f", null ], + [ "pSignature", "a00985.html#ac9477410362aebdb892fdf382864342c", null ], + [ "pPublicKey", "a00985.html#a2db1a83966c659495b7bca80d7b5ab25", null ], + [ "pOutputR", "a00985.html#a6b6eb3da4f84de13269bb74d79583b51", null ], + [ "optLen", "a00985.html#afa16cb1249abe8848bfe2beeb909c4f3", null ] + ] ], + [ "mcuxClEcc_PointMult_Param_t", "a00989.html", [ + [ "curveParam", "a00989.html#a264c295859d39a968b32efbc4f03942a", null ], + [ "pScalar", "a00989.html#a661018eb3da69cf8aa41f08690abc10a", null ], + [ "pPoint", "a00989.html#aa8a74b645f7f8b9c611afa1df8c6b523", null ], + [ "pResult", "a00989.html#a6bf3d35fa5651ee8eacd77d9ce1d97bf", null ], + [ "optLen", "a00989.html#a037bdeafd85441ec7c9a5edde80ed772", null ] + ] ], + [ "mcuxClEcc_DomainParam_misc_Pack", "a00686.html#ga811c5fef9abbdfc1548b007e0d31c69f", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenP_offset", "a00686.html#ga62009de56f8d1fbbd2024072229a75fa", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenP_mask", "a00686.html#ga6b450065c08ab2e1adf93c1015c2fe87", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenN_offset", "a00686.html#ga2470875307a9264ff6e12046fd4a57eb", null ], + [ "mcuxClEcc_DomainParam_misc_byteLenN_mask", "a00686.html#ga26e4695e9a47f6a7c7d36af8e8432fa0", null ], + [ "mcuxClEcc_Sign_Param_optLen_Pack", "a00686.html#ga05dbf2e2404af42bb6aaca0d0eaada8f", null ], + [ "mcuxClEcc_Sign_Param_optLen_byteLenHash_offset", "a00686.html#ga25bfc46880eb604440c1facc7e55fc3d", null ], + [ "mcuxClEcc_Sign_Param_optLen_byteLenHash_mask", "a00686.html#ga4a74c55c76d977b39d1b387b75bbeebb", null ], + [ "mcuxClEcc_Verify_Param_optLen_Pack", "a00686.html#ga329b8cd689c64177a46e68b4f3a6a158", null ], + [ "mcuxClEcc_Verify_Param_optLen_byteLenHash_offset", "a00686.html#ga9e4f2aa470eda485d1ca012222e37070", null ], + [ "mcuxClEcc_Verify_Param_optLen_byteLenHash_mask", "a00686.html#gafeb4e3230717ac80d469d421918a8607", null ], + [ "mcuxClEcc_MontDH_DomainParams_t", "a00686.html#ga52205a42d2027ba1c3ec49589f9f0b8c", null ], + [ "mcuxClEcc_EdDSA_DomainParams_t", "a00686.html#ga365359e63f156889e46845381455b321", null ], + [ "mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t", "a00686.html#gadee46209e43c63814a86e882b3927b27", null ], + [ "mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t", "a00686.html#gaec003d78ecf36673f595fcc87f11b82c", null ], + [ "mcuxClEcc_Weier_DomainParams_t", "a00686.html#gafe84edad82c8934ef1634e9f29effa55", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00687.html b/components/els_pkc/doc/mcxn/html/a00687.html new file mode 100644 index 000000000..84ff6cde0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00687.html @@ -0,0 +1,157 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Descriptors + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClEcc_Descriptors
mcuxClEcc
+
+
+ +

Defines descriptors of mcuxClEcc. +More...

+ + + + + + + +

+Variables

+const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor
 
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor
 Ed25519 signature protocol descriptor. More...
 
+

Detailed Description

+

Defines descriptors of mcuxClEcc.

+

Variable Documentation

+ +

◆ mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor

+ +
+
+ + + + +
const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor
+
+ +

Ed25519 signature protocol descriptor.

+

NOTE: To be able to perform an Ed25519 signature generation using this mode, the private key handle must be properly linked to a key handle for the associated public key using the function mcuxClKey_linkKeyPair. This is necessary to make the public key accessible during an Ed25519 signature generation. If this is not satisfied the Ed25519 signature generation will fail. If the key pair has been generated using the mcuxClKey_generate_keypair function, this linking step is already performed by mcuxClKey_generate_keypair.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, and mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00687.js b/components/els_pkc/doc/mcxn/html/a00687.js new file mode 100644 index 000000000..9f2d4e6db --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00687.js @@ -0,0 +1,4 @@ +var a00687 = +[ + [ "mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor", "a00687.html#ga41770640b3d964f8add4ad005c6d81e6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00688.html b/components/els_pkc/doc/mcxn/html/a00688.html new file mode 100644 index 000000000..6c6583d7c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00688.html @@ -0,0 +1,340 @@ + + + + + + + +MCUX CLNS: mcuxClEls + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls
+
+
+ +

ELS driver. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 mcuxClEls_Aead
 This part of the mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD).
 
 mcuxClEls_Cipher
 This part of the mcuxClEls driver supports functionality for symmetric ciphers.
 
 mcuxClEls_Cmac
 This part of the mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC).
 
 mcuxClEls_Common
 This part of the mcuxClEls driver supports common functionality.
 
 mcuxClEls_Crc
 This part of the mcuxClEls driver defines the Command CRC functionality.
 
 mcuxClEls_Ecc
 This part of the mcuxClEls driver supports functionality for elliptic curve cryptography.
 
 mcuxClEls_Hash
 This part of the mcuxClEls driver supports hashing.
 
 mcuxClEls_Hmac
 This part of the mcuxClEls driver supports functionality for hashed-key message authentication codes.
 
 mcuxClEls_Kdf
 This part of the mcuxClEls driver supports functionality for key derivation.
 
 mcuxClEls_KeyManagement
 This part of the mcuxClEls driver supports functionality for keys management.
 
 mcuxClEls_Rng
 This part of the mcuxClEls driver supports functionality for random number generation.
 
 mcuxClEls_Types
 This part of the mcuxClEls driver defines common types.
 
+

Detailed Description

+

ELS driver.

+

This component abstracts the hardware access to the ELS IP. The library exposes the following hardware functionality:

    +
  1. +COMMON +
    2. +
  2. +CRC +
    3. +
  3. +HASH +
    4. +
  4. +CIPHER (Symmetric Encryption) +
    5. +
  5. +KEY MANAGEMENT +
    6. +
  6. +ECC (Elliptic Curve Cryptography) +
    7. +
  7. +KEY DERIVATION
      +
    • +Key derivation
        +
      • +
        • +
      +
      • +
    +
    8. +
+

After each call to a function ending in _Async, one of the waiting functions mcuxClEls_WaitForOperation or mcuxClEls_LimitedWaitForOperation must be called to ensure completion. The waiting functions may fail, e.g., when the ELS enters an error state.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00688.js b/components/els_pkc/doc/mcxn/html/a00688.js new file mode 100644 index 000000000..fd61b7cd8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00688.js @@ -0,0 +1,15 @@ +var a00688 = +[ + [ "mcuxClEls_Aead", "a00689.html", "a00689" ], + [ "mcuxClEls_Cipher", "a00694.html", "a00694" ], + [ "mcuxClEls_Cmac", "a00700.html", "a00700" ], + [ "mcuxClEls_Common", "a00706.html", "a00706" ], + [ "mcuxClEls_Crc", "a00718.html", "a00718" ], + [ "mcuxClEls_Ecc", "a00725.html", "a00725" ], + [ "mcuxClEls_Hash", "a00735.html", "a00735" ], + [ "mcuxClEls_Hmac", "a00743.html", "a00743" ], + [ "mcuxClEls_Kdf", "a00748.html", "a00748" ], + [ "mcuxClEls_KeyManagement", "a00753.html", "a00753" ], + [ "mcuxClEls_Rng", "a00760.html", "a00760" ], + [ "mcuxClEls_Types", "a00763.html", "a00763" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00689.html b/components/els_pkc/doc/mcxn/html/a00689.html new file mode 100644 index 000000000..7aee86995 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00689.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Aead
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD). +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Aead_Macros
 Defines all macros of mcuxClEls_Aead.
 
 mcuxClEls_Aead_Types
 Defines all types of mcuxClEls_Aead.
 
 mcuxClEls_Aead_Functions
 Defines all functions of mcuxClEls_Aead.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD).

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00689.js b/components/els_pkc/doc/mcxn/html/a00689.js new file mode 100644 index 000000000..a618d15d5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00689.js @@ -0,0 +1,6 @@ +var a00689 = +[ + [ "mcuxClEls_Aead_Macros", "a00690.html", "a00690" ], + [ "mcuxClEls_Aead_Types", "a00692.html", "a00692" ], + [ "mcuxClEls_Aead_Functions", "a00693.html", "a00693" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00690.html b/components/els_pkc/doc/mcxn/html/a00690.html new file mode 100644 index 000000000..e40fa59ea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00690.html @@ -0,0 +1,213 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClEls_Aead_Macros
mcuxClEls » mcuxClEls_Aead
+
+
+ +

Defines all macros of mcuxClEls_Aead. +More...

+ + + + + +

+Modules

 MCUXCLELS_AEAD_
 Defines macros used to initialize mcuxClEls_AeadOption_t.
 
+ + + + + + + + + + + + +

+Macros

#define MCUXCLELS_AEAD_IV_BLOCK_SIZE
 
#define MCUXCLELS_AEAD_AAD_BLOCK_SIZE
 AES-GCM AAD Granularity: 128 bit (16 bytes) More...
 
#define MCUXCLELS_AEAD_TAG_SIZE
 tag size: Tag generation supports only a 128 bit wide tag (16 bytes) More...
 
#define MCUXCLELS_AEAD_CONTEXT_SIZE
 context size: 512 bit (64 bytes) + 16 bytes for finalize More...
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Aead.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_AEAD_IV_BLOCK_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_IV_BLOCK_SIZE
+
+

AES-GCM IV Granularity: 128 bit (16 bytes)

+ +
+
+ +

◆ MCUXCLELS_AEAD_AAD_BLOCK_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_AAD_BLOCK_SIZE
+
+ +

AES-GCM AAD Granularity: 128 bit (16 bytes)

+ +
+
+ +

◆ MCUXCLELS_AEAD_TAG_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_TAG_SIZE
+
+ +

tag size: Tag generation supports only a 128 bit wide tag (16 bytes)

+ +
+
+ +

◆ MCUXCLELS_AEAD_CONTEXT_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_CONTEXT_SIZE
+
+ +

context size: 512 bit (64 bytes) + 16 bytes for finalize

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00690.js b/components/els_pkc/doc/mcxn/html/a00690.js new file mode 100644 index 000000000..e806237df --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00690.js @@ -0,0 +1,8 @@ +var a00690 = +[ + [ "MCUXCLELS_AEAD_", "a00691.html", "a00691" ], + [ "MCUXCLELS_AEAD_IV_BLOCK_SIZE", "a00690.html#gacc54b347065e037fd7d5814334b82826", null ], + [ "MCUXCLELS_AEAD_AAD_BLOCK_SIZE", "a00690.html#ga8a1dab00c208f1b7dc1cf8a2a30a3991", null ], + [ "MCUXCLELS_AEAD_TAG_SIZE", "a00690.html#ga61d8f500ac3ed42fff023025b54692f2", null ], + [ "MCUXCLELS_AEAD_CONTEXT_SIZE", "a00690.html#ga191963434b3271e31bdffc12943745e2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00691.html b/components/els_pkc/doc/mcxn/html/a00691.html new file mode 100644 index 000000000..95f298282 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00691.html @@ -0,0 +1,379 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_AEAD_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_AEAD_
mcuxClEls » mcuxClEls_Aead » mcuxClEls_Aead_Macros
+
+
+ +

Defines macros used to initialize mcuxClEls_AeadOption_t. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_AEAD_ENCRYPT
 Set mcuxClEls_AeadOption_t.dcrpt to this value to encrypt data. More...
 
#define MCUXCLELS_AEAD_DECRYPT
 Set mcuxClEls_AeadOption_t.dcrpt to this value to decrypt data. More...
 
#define MCUXCLELS_AEAD_STATE_IN_DISABLE
 Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from ELS. More...
 
#define MCUXCLELS_AEAD_STATE_IN_ENABLE
 Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from the context. More...
 
#define MCUXCLELS_AEAD_LASTINIT_TRUE
 Set mcuxClEls_AeadOption_t.lastinit to this value if this is the last call to init. More...
 
#define MCUXCLELS_AEAD_LASTINIT_FALSE
 Set mcuxClEls_AeadOption_t.lastinit to this value if this is not the last call to init. More...
 
#define MCUXCLELS_AEAD_EXTERN_KEY
 Set mcuxClEls_AeadOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_AEAD_INTERN_KEY
 Set mcuxClEls_AeadOption_t.extkey to this value to use a key from the ELS keystore. More...
 
#define MCUXCLELS_AEAD_ACPMOD_INIT
 Set mcuxClEls_AeadOption_t.acpmod to this value for Init mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_AADPROC
 Set mcuxClEls_AeadOption_t.acpmod to this value for Process Additional Authenticated Data mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_MSGPROC
 Set mcuxClEls_AeadOption_t.acpmod to this value for Process Message mode. For internal use. More...
 
#define MCUXCLELS_AEAD_ACPMOD_FINAL
 Set mcuxClEls_AeadOption_t.acpmod to this value for Finalize mode. For internal use. More...
 
#define MCUXCLELS_AEAD_STATE_OUT_ENABLE
 Set mcuxClEls_AeadOption_t.acpsoe to this value to save the state to the context. For internal use. More...
 
+

Detailed Description

+

Defines macros used to initialize mcuxClEls_AeadOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_AEAD_ENCRYPT

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_ENCRYPT
+
+ +

Set mcuxClEls_AeadOption_t.dcrpt to this value to encrypt data.

+ +
+
+ +

◆ MCUXCLELS_AEAD_DECRYPT

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_DECRYPT
+
+ +

Set mcuxClEls_AeadOption_t.dcrpt to this value to decrypt data.

+ +
+
+ +

◆ MCUXCLELS_AEAD_STATE_IN_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_STATE_IN_DISABLE
+
+ +

Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from ELS.

+ +
+
+ +

◆ MCUXCLELS_AEAD_STATE_IN_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_STATE_IN_ENABLE
+
+ +

Set mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from the context.

+ +
+
+ +

◆ MCUXCLELS_AEAD_LASTINIT_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_LASTINIT_TRUE
+
+ +

Set mcuxClEls_AeadOption_t.lastinit to this value if this is the last call to init.

+ +
+
+ +

◆ MCUXCLELS_AEAD_LASTINIT_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_LASTINIT_FALSE
+
+ +

Set mcuxClEls_AeadOption_t.lastinit to this value if this is not the last call to init.

+ +
+
+ +

◆ MCUXCLELS_AEAD_EXTERN_KEY

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_EXTERN_KEY
+
+ +

Set mcuxClEls_AeadOption_t.extkey to this value to use an external key.

+ +
+
+ +

◆ MCUXCLELS_AEAD_INTERN_KEY

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_INTERN_KEY
+
+ +

Set mcuxClEls_AeadOption_t.extkey to this value to use a key from the ELS keystore.

+ +
+
+ +

◆ MCUXCLELS_AEAD_ACPMOD_INIT

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_ACPMOD_INIT
+
+ +

Set mcuxClEls_AeadOption_t.acpmod to this value for Init mode. For internal use.

+ +
+
+ +

◆ MCUXCLELS_AEAD_ACPMOD_AADPROC

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_ACPMOD_AADPROC
+
+ +

Set mcuxClEls_AeadOption_t.acpmod to this value for Process Additional Authenticated Data mode. For internal use.

+ +
+
+ +

◆ MCUXCLELS_AEAD_ACPMOD_MSGPROC

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_ACPMOD_MSGPROC
+
+ +

Set mcuxClEls_AeadOption_t.acpmod to this value for Process Message mode. For internal use.

+ +
+
+ +

◆ MCUXCLELS_AEAD_ACPMOD_FINAL

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_ACPMOD_FINAL
+
+ +

Set mcuxClEls_AeadOption_t.acpmod to this value for Finalize mode. For internal use.

+ +
+
+ +

◆ MCUXCLELS_AEAD_STATE_OUT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_AEAD_STATE_OUT_ENABLE
+
+ +

Set mcuxClEls_AeadOption_t.acpsoe to this value to save the state to the context. For internal use.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00691.js b/components/els_pkc/doc/mcxn/html/a00691.js new file mode 100644 index 000000000..e9b548c17 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00691.js @@ -0,0 +1,16 @@ +var a00691 = +[ + [ "MCUXCLELS_AEAD_ENCRYPT", "a00691.html#ga3bc61d00867e4344af9c7605a47028cf", null ], + [ "MCUXCLELS_AEAD_DECRYPT", "a00691.html#gaaf35b04563d926ceaa1782d82741d7b7", null ], + [ "MCUXCLELS_AEAD_STATE_IN_DISABLE", "a00691.html#ga445707b186d86232b626330863532c15", null ], + [ "MCUXCLELS_AEAD_STATE_IN_ENABLE", "a00691.html#ga19f5684ee7ffea323b56bab96f7c059b", null ], + [ "MCUXCLELS_AEAD_LASTINIT_TRUE", "a00691.html#ga7af98652f0dba78d1c665b2c9dfd0e29", null ], + [ "MCUXCLELS_AEAD_LASTINIT_FALSE", "a00691.html#ga7f97e1488141405752147029eee6a818", null ], + [ "MCUXCLELS_AEAD_EXTERN_KEY", "a00691.html#ga5b1a905706af4ecad1473f5e3ac8a710", null ], + [ "MCUXCLELS_AEAD_INTERN_KEY", "a00691.html#gaa7d58cf548b411d9aaea17af1539203a", null ], + [ "MCUXCLELS_AEAD_ACPMOD_INIT", "a00691.html#ga6c775ee90e7ea1e3db4840a2037d303c", null ], + [ "MCUXCLELS_AEAD_ACPMOD_AADPROC", "a00691.html#ga536e8fa026cae719c095b47fbb0fd099", null ], + [ "MCUXCLELS_AEAD_ACPMOD_MSGPROC", "a00691.html#ga05e3ebc05c195d1f62ff6a40a98b8d3c", null ], + [ "MCUXCLELS_AEAD_ACPMOD_FINAL", "a00691.html#ga1d5a6d584b299721149ff9bdbeaee517", null ], + [ "MCUXCLELS_AEAD_STATE_OUT_ENABLE", "a00691.html#ga944f3b21904cdbc22385fcfab1c1236b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00692.html b/components/els_pkc/doc/mcxn/html/a00692.html new file mode 100644 index 000000000..48e50925b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00692.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Aead_Types
mcuxClEls » mcuxClEls_Aead
+
+
+ +

Defines all types of mcuxClEls_Aead. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_AeadOption_t
 Command option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async, mcuxClEls_Aead_UpdateData_Async and mcuxClEls_Aead_Finalize_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Aead.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00692.js b/components/els_pkc/doc/mcxn/html/a00692.js new file mode 100644 index 000000000..325998f52 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00692.js @@ -0,0 +1,18 @@ +var a00692 = +[ + [ "mcuxClEls_AeadOption_t", "a00997.html", [ + [ "value", "a00997.html#ac8b3278eb96cd5ca0e15b9b2318305a7", null ], + [ "word", "a00997.html#a6a1cf6dca7babcb5b673312d79c3db9e", null ], + [ "__pad0__", "a00997.html#a55a86ab29b1e20072f48c56470568824", null ], + [ "dcrpt", "a00997.html#aabfd8fc5389ae7bfa2dea92c42441555", null ], + [ "acpmod", "a00997.html#a2504aa4fde601569a6c27276e76802f3", null ], + [ "acpsoe", "a00997.html#a77636eb7e553de47143580de37585920", null ], + [ "acpsie", "a00997.html#a5fafad6f592dfb928316273b5ccbec12", null ], + [ "msgendw", "a00997.html#a6e7b66230e97b647ba209b8f5eb68d2f", null ], + [ "lastinit", "a00997.html#a70ab6c857c7ae2e10b2f0580e4ea3669", null ], + [ "__pad1__", "a00997.html#a6b276f4a8ddbf8c2f337ad23c52d6963", null ], + [ "extkey", "a00997.html#a6e8a89cd7914a8f587ae7d2888a1e7cd", null ], + [ "__pad2__", "a00997.html#ae06263ba435ff9824be1f20c8f20b96c", null ], + [ "bits", "a00997.html#a2d11453f5716e58c8b34e92d434edd1b", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00693.html b/components/els_pkc/doc/mcxn/html/a00693.html new file mode 100644 index 000000000..3449c55f8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00693.html @@ -0,0 +1,671 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Aead_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Aead_Functions
mcuxClEls » mcuxClEls_Aead
+
+
+ +

Defines all functions of mcuxClEls_Aead. +More...

+ + + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Init_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
 AES-GCM initialization. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_PartialInit_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pIV, size_t ivLength, uint8_t *pAeadCtx)
 AES-GCM partial initialization. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateAad_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pAad, size_t aadLength, uint8_t *pAeadCtx)
 AES-GCM update of the Additional Authenticated Data (AAD) More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateData_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput, uint8_t *pAeadCtx)
 AES-GCM update of the encrypted data. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Finalize_Async (mcuxClEls_AeadOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, size_t aadLength, size_t dataLength, uint8_t *pTag, uint8_t *pAeadCtx)
 AES-GCM final encryption/decryption. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Aead.

+

Function Documentation

+ +

◆ mcuxClEls_Aead_Init_Async()

+ +
+
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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Init_Async (mcuxClEls_AeadOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pIV,
size_t ivLength,
uint8_t * pAeadCtx 
)
+
+ +

AES-GCM initialization.

+

This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV pIV and the key (pKey or keyIdx).

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + +
[in]optionsThe AEAD command options. For more information, see mcuxClEls_AeadOption_t.
[in]keyIdxIndex of the key inside the ELS keystore
[in]pKeyPointer to the key
[in]keyLengthSize of pKey in bytes
[in]pIVPointer to memory area that contains the IV
[in]ivLengthSize of pIV in bytes, with padding
[out]pAeadCtxPointer to the memory area that receives the AEAD context structure. Must be at least MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_AEAD_EXTERN_KEY
+

keyIdx is ignored.

+

pKey must be a valid AES key and keyLength a valid AES key size (see MCUXCLELS_CIPHER_KEY_SIZE_AES_).

+

+
+
options.extkey == MCUXCLELS_AEAD_INTERN_KEY
+

keyIdx must be a valid key index with the correct usage rights.

+

pKey and keyLength are ignored.

+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Aead_PartialInit_Async()

+ +
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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_PartialInit_Async (mcuxClEls_AeadOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pIV,
size_t ivLength,
uint8_t * pAeadCtx 
)
+
+ +

AES-GCM partial initialization.

+

This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV pIV and the key (pKey or keyIdx).

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + +
[in]optionsThe AEAD command options. For more information, see mcuxClEls_AeadOption_t.
[in]keyIdxIndex of the key inside the ELS keystore
[in]pKeyPointer to the key
[in]keyLengthSize of pKey in bytes
[in]pIVPointer to memory area that contains the IV
[in]ivLengthSize of pIV in bytes, with padding
[out]pAeadCtxPointer to the memory area that receives the AEAD context structure. Must be at least MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_AEAD_EXTERN_KEY
+

keyIdx is ignored.

+

pKey must be a valid AES key and keyLength a valid AES key size (see MCUXCLELS_CIPHER_KEY_SIZE_AES_).

+

+
+
options.extkey == MCUXCLELS_AEAD_INTERN_KEY
+

keyIdx must be a valid key index with the correct usage rights.

+

pKey and keyLength are ignored.

+

+
+
options.msgendw
+
This field is ignored
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Aead_UpdateAad_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateAad_Async (mcuxClEls_AeadOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pAad,
size_t aadLength,
uint8_t * pAeadCtx 
)
+
+ +

AES-GCM update of the Additional Authenticated Data (AAD)

+

This is the second stage of AEAD encryption/decryption. This updates the internal authentication tag with the AAD.

+

mcuxClEls_Aead_Init_Async must have been called before calling this function.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + +
[in]optionsThe AEAD command options. For more information, see mcuxClEls_AeadOption_t.
[in]keyIdxIndex of the key inside the ELS keystore
[in]pKeyPointer to the key
[in]keyLengthSize of pKey in bytes
[in]pAadMemory area that contains the AAD
[in]aadLengthLength of the pAad in bytes with padding
[in,out]pAeadCtxPointer to the AEAD context structure. Must be at least MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_AEAD_EXTERN_KEY
+

keyIdx is ignored.

+

pKey must be a valid AES key and keyLength a valid AES key size (see MCUXCLELS_CIPHER_KEY_SIZE_AES_).

+

+
+
options.extkey == MCUXCLELS_AEAD_INTERN_KEY
+

keyIdx must be a valid key index with the correct usage rights.

+

pKey and keyLength are ignored.

+

+
+
options.msgendw
+
This field is ignored
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Aead_UpdateData_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_UpdateData_Async (mcuxClEls_AeadOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pInput,
size_t inputLength,
uint8_t * pOutput,
uint8_t * pAeadCtx 
)
+
+ +

AES-GCM update of the encrypted data.

+

This is the third stage of AEAD encryption/decryption. This processes the given plaintext (in case of encryption) or ciphertext (in case of decryption) and outputs the ciphertext (in case of encryption) or plaintext (in case of decryption).

+

mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async must have been called before calling this function.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + + +
[in]optionsThe AEAD command options. For more information, see mcuxClEls_AeadOption_t.
[in]keyIdxIndex of the key inside the ELS keystore
[in]pKeyPointer to the key
[in]keyLengthSize of pKey in bytes
[in]pInputPointer to the memory location of the data to be processed
[in]inputLengthSize of pInput in bytes with padding
[out]pOutputPointer to the processed data memory location
[in,out]pAeadCtxPointer to the AEAD context structure. Must be at least MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_AEAD_EXTERN_KEY
+

keyIdx is ignored.

+

pKey must be a valid AES key and keyLength a valid AES key size (see MCUXCLELS_CIPHER_KEY_SIZE_AES_).

+

+
+
options.extkey == MCUXCLELS_AEAD_INTERN_KEY
+

keyIdx must be a valid key index with the correct usage rights.

+

pKey and keyLength are ignored.

+

+
+
options.msgendw
+
This field has to be set to the size of the last data block (plain/cipher text) in bytes, without padding. In case the last block is a full block, this field has to be set to 0.
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Aead_Finalize_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Aead_Finalize_Async (mcuxClEls_AeadOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
size_t aadLength,
size_t dataLength,
uint8_t * pTag,
uint8_t * pAeadCtx 
)
+
+ +

AES-GCM final encryption/decryption.

+

This is the fourth stage of AEAD encryption/decryption. This updates the authentication tag with the final data length block and outputs the tag at the desired location.

+

mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async and mcuxClEls_Aead_UpdateData_Async must have been called before calling this function.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + + +
[in]optionsThe AEAD command options. For more information, see mcuxClEls_AeadOption_t.
[in]keyIdxIndex of the key inside the ELS keystore
[in]pKeyPointer to the key
[in]keyLengthSize of pKey in bytes
[in]aadLengthLength of the complete Additional Authenticated Data (AAD) in bytes, without padding.
[in]dataLengthLength of the complete plaintext/ciphertext in bytes, without padding.
[out]pTagPointer where the resulting tag will be stored
[in]pAeadCtxPointer to the AEAD context structure. Must be at least MCUXCLELS_AEAD_CONTEXT_SIZE bytes long.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_AEAD_EXTERN_KEY
+

keyIdx is ignored.

+

pKey must be a valid AES key and keyLength a valid AES key size (see MCUXCLELS_CIPHER_KEY_SIZE_AES_).

+

+
+
options.extkey == MCUXCLELS_AEAD_INTERN_KEY
+

keyIdx must be a valid key index with the correct usage rights.

+

pKey and keyLength are ignored.

+

+
+
options.msgendw
+
This field is ignored
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00693.js b/components/els_pkc/doc/mcxn/html/a00693.js new file mode 100644 index 000000000..5d3d99640 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00693.js @@ -0,0 +1,8 @@ +var a00693 = +[ + [ "mcuxClEls_Aead_Init_Async", "a00693.html#ga86bbde5d55c2e44102158ef7b802b819", null ], + [ "mcuxClEls_Aead_PartialInit_Async", "a00693.html#ga817b12c984eb2afcaad9aa3c2b75040c", null ], + [ "mcuxClEls_Aead_UpdateAad_Async", "a00693.html#gaa34534b5e5196e07cbcef7c858cc0ea9", null ], + [ "mcuxClEls_Aead_UpdateData_Async", "a00693.html#ga7d5f1b08fbbcda07f881c274b0100c8b", null ], + [ "mcuxClEls_Aead_Finalize_Async", "a00693.html#gab2f0d1f82ce7537c78967ea2989a2054", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00694.html b/components/els_pkc/doc/mcxn/html/a00694.html new file mode 100644 index 000000000..3ef780995 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00694.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Cipher
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for symmetric ciphers. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Cipher_Macros
 Defines all macros of mcuxClEls_Cipher.
 
 mcuxClEls_Cipher_Types
 Defines all types of mcuxClEls_Cipher.
 
 mcuxClEls_Cipher_Functions
 Defines all functions of mcuxClEls_Cipher.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for symmetric ciphers.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00694.js b/components/els_pkc/doc/mcxn/html/a00694.js new file mode 100644 index 000000000..4cf80ed40 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00694.js @@ -0,0 +1,6 @@ +var a00694 = +[ + [ "mcuxClEls_Cipher_Macros", "a00695.html", "a00695" ], + [ "mcuxClEls_Cipher_Types", "a00698.html", "a00698" ], + [ "mcuxClEls_Cipher_Functions", "a00699.html", "a00699" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00695.html b/components/els_pkc/doc/mcxn/html/a00695.html new file mode 100644 index 000000000..a63b8007d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00695.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
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+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClEls_Cipher_Macros
mcuxClEls » mcuxClEls_Cipher
+
+
+ +

Defines all macros of mcuxClEls_Cipher. +More...

+ + + + + + + + +

+Modules

 MCUXCLELS_CIPHER_
 Defines valid options to be used by mcuxClEls_CipherOption_tValid AES key sizes in bytes.
 
 MCUXCLELS_CIPHER_KEY_SIZE_AES_
 Defines valid AES key sizes in bytes.
 
+ + + +

+Macros

#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Cipher.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CIPHER_BLOCK_SIZE_AES

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES
+
+

Size of an AES input block: 128 bit (16 bytes)

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00695.js b/components/els_pkc/doc/mcxn/html/a00695.js new file mode 100644 index 000000000..f0826ec9b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00695.js @@ -0,0 +1,6 @@ +var a00695 = +[ + [ "MCUXCLELS_CIPHER_", "a00696.html", "a00696" ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_", "a00697.html", "a00697" ], + [ "MCUXCLELS_CIPHER_BLOCK_SIZE_AES", "a00695.html#ga36ebb8ab2b019997c6cf2c9d15b944b0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00696.html b/components/els_pkc/doc/mcxn/html/a00696.html new file mode 100644 index 000000000..3deded557 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00696.html @@ -0,0 +1,350 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CIPHER_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
MCUXCLELS_CIPHER_
mcuxClEls » mcuxClEls_Cipher » mcuxClEls_Cipher_Macros
+
+
+ +

Defines valid options to be used by mcuxClEls_CipherOption_tValid AES key sizes in bytes. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CIPHER_ENCRYPT
 Set this option at mcuxClEls_CipherOption_t.dcrpt to perform an encryption. More...
 
#define MCUXCLELS_CIPHER_DECRYPT
 Set this option at mcuxClEls_CipherOption_t.dcrpt to perform a decryption. More...
 
#define MCUXCLELS_CIPHER_STATE_OUT_ENABLE
 Set this option at mcuxClEls_CipherOption_t.cphsoe to export the internal ELS state to pIV. More...
 
#define MCUXCLELS_CIPHER_STATE_OUT_DISABLE
 Set this option at mcuxClEls_CipherOption_t.cphsoe to not export the internal ELS state. More...
 
#define MCUXCLELS_CIPHER_STATE_IN_ENABLE
 Set this option at mcuxClEls_CipherOption_t.cphsie to import an external ELS state from pIV. More...
 
#define MCUXCLELS_CIPHER_STATE_IN_DISABLE
 Set this option at mcuxClEls_CipherOption_t.cphsie to not import an external ELS state. More...
 
#define MCUXCLELS_CIPHER_EXTERNAL_KEY
 Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by pKey. More...
 
#define MCUXCLELS_CIPHER_INTERNAL_KEY
 Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by keyIdx. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mode. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Cipher Block Chaining (CBC) mode. More...
 
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
 Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Counter (CTR) mode. More...
 
+

Detailed Description

+

Defines valid options to be used by mcuxClEls_CipherOption_t

+

Valid AES key sizes in bytes.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CIPHER_ENCRYPT

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_ENCRYPT
+
+ +

Set this option at mcuxClEls_CipherOption_t.dcrpt to perform an encryption.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_CIPHER_DECRYPT

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_DECRYPT
+
+ +

Set this option at mcuxClEls_CipherOption_t.dcrpt to perform a decryption.

+ +
+
+ +

◆ MCUXCLELS_CIPHER_STATE_OUT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_STATE_OUT_ENABLE
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphsoe to export the internal ELS state to pIV.

+ +
+
+ +

◆ MCUXCLELS_CIPHER_STATE_OUT_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_STATE_OUT_DISABLE
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphsoe to not export the internal ELS state.

+ +
+
+ +

◆ MCUXCLELS_CIPHER_STATE_IN_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_STATE_IN_ENABLE
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphsie to import an external ELS state from pIV.

+ +
+
+ +

◆ MCUXCLELS_CIPHER_STATE_IN_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_STATE_IN_DISABLE
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphsie to not import an external ELS state.

+ +
+
+ +

◆ MCUXCLELS_CIPHER_EXTERNAL_KEY

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_EXTERNAL_KEY
+
+ +

Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by pKey.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_CIPHER_INTERNAL_KEY

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_INTERNAL_KEY
+
+ +

Set this option at mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by keyIdx.

+ +
+
+ +

◆ MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB

+ +
+
+ + + + +
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mode.

+
Examples
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC

+ +
+
+ + + + +
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Cipher Block Chaining (CBC) mode.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR

+ +
+
+ + + + +
#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
+
+ +

Set this option at mcuxClEls_CipherOption_t.cphmde to use AES engine in Counter (CTR) mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00696.js b/components/els_pkc/doc/mcxn/html/a00696.js new file mode 100644 index 000000000..6f49d629e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00696.js @@ -0,0 +1,14 @@ +var a00696 = +[ + [ "MCUXCLELS_CIPHER_ENCRYPT", "a00696.html#ga9840411e958cd2b7312c7e62e5dc06d0", null ], + [ "MCUXCLELS_CIPHER_DECRYPT", "a00696.html#ga15e29141f6a5eef67438d6db62cbaa72", null ], + [ "MCUXCLELS_CIPHER_STATE_OUT_ENABLE", "a00696.html#gabb9d9bd0dc215ef17a7ffbabd0f714c7", null ], + [ "MCUXCLELS_CIPHER_STATE_OUT_DISABLE", "a00696.html#ga3eb172e440a7290240fca36a6bf82fa0", null ], + [ "MCUXCLELS_CIPHER_STATE_IN_ENABLE", "a00696.html#gab55a588688b790dd342dfc24f720a7aa", null ], + [ "MCUXCLELS_CIPHER_STATE_IN_DISABLE", "a00696.html#gafc74b6823a43a2b50a27b4ec891ce9ef", null ], + [ "MCUXCLELS_CIPHER_EXTERNAL_KEY", "a00696.html#ga9feef12c93a57ed798263258e74cba73", null ], + [ "MCUXCLELS_CIPHER_INTERNAL_KEY", "a00696.html#gad090b7cf60eb9468ae5fabf55672ab9d", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB", "a00696.html#ga6f585946c286cebc74b291c520eaaec9", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC", "a00696.html#ga22151bc71de63404ddcb4dec66a3d99f", null ], + [ "MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR", "a00696.html#ga4df5eca54609eed0ff0bf00152c87ccf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00697.html b/components/els_pkc/doc/mcxn/html/a00697.html new file mode 100644 index 000000000..9d4455c9c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00697.html @@ -0,0 +1,191 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CIPHER_KEY_SIZE_AES_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_CIPHER_KEY_SIZE_AES_
mcuxClEls » mcuxClEls_Cipher » mcuxClEls_Cipher_Macros
+
+
+ +

Defines valid AES key sizes in bytes. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128
 Size of an AES128 key: 128 bit (16 bytes) More...
 
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_192
 Size of an AES192 key: 192 bit (24 bytes) More...
 
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256
 Size of an AES192 key: 256 bit (32 bytes) More...
 
+

Detailed Description

+

Defines valid AES key sizes in bytes.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CIPHER_KEY_SIZE_AES_128

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128
+
+ +

Size of an AES128 key: 128 bit (16 bytes)

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_CIPHER_KEY_SIZE_AES_192

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_192
+
+ +

Size of an AES192 key: 192 bit (24 bytes)

+ +
+
+ +

◆ MCUXCLELS_CIPHER_KEY_SIZE_AES_256

+ +
+
+ + + + +
#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256
+
+ +

Size of an AES192 key: 256 bit (32 bytes)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00697.js b/components/els_pkc/doc/mcxn/html/a00697.js new file mode 100644 index 000000000..2aa551035 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00697.js @@ -0,0 +1,6 @@ +var a00697 = +[ + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_128", "a00697.html#ga68ee2f7110cd9f2dbce9af07b7c64f0f", null ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_192", "a00697.html#ga40b6da61509c272916be81c25780eeff", null ], + [ "MCUXCLELS_CIPHER_KEY_SIZE_AES_256", "a00697.html#ga474b8fd0f1e5832a4ba327ba7aee3520", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00698.html b/components/els_pkc/doc/mcxn/html/a00698.html new file mode 100644 index 000000000..04cf28e44 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00698.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Cipher_Types
mcuxClEls » mcuxClEls_Cipher
+
+
+ +

Defines all types of mcuxClEls_Cipher. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_CipherOption_t
 Command option bit field for mcuxClEls_Cipher_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Cipher.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00698.js b/components/els_pkc/doc/mcxn/html/a00698.js new file mode 100644 index 000000000..335cf150c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00698.js @@ -0,0 +1,16 @@ +var a00698 = +[ + [ "mcuxClEls_CipherOption_t", "a01009.html", [ + [ "value", "a01009.html#a1c724d7ce478fcbb4cdd0ccb5c1fd899", null ], + [ "word", "a01009.html#afd7050544cd985c2dda66061e0f0c44f", null ], + [ "__pad0__", "a01009.html#abb6ec00ab841f6edcc37f6f51fb35975", null ], + [ "dcrpt", "a01009.html#ada47dbd9ac0d8ed1b171e4742ed5d73a", null ], + [ "cphmde", "a01009.html#a2e1e4a5d815c2559f0ef02e4fd0e5523", null ], + [ "cphsoe", "a01009.html#aa37b413e9a8ffa66655bc529aadaadbc", null ], + [ "cphsie", "a01009.html#af8735651384f21746fcea24b5c935a1d", null ], + [ "__pad1__", "a01009.html#a8b8096d5f06a8f303976697a0fa369aa", null ], + [ "extkey", "a01009.html#a833ce63bdab590215c35b82767479eee", null ], + [ "__pad2__", "a01009.html#a568f1ef7bba7f45209bf0cf43bb66b45", null ], + [ "bits", "a01009.html#af61168dc7998ed7862a56c85b64871c0", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00699.html b/components/els_pkc/doc/mcxn/html/a00699.html new file mode 100644 index 000000000..916510970 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00699.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Cipher_Functions
mcuxClEls » mcuxClEls_Cipher
+
+
+ +

Defines all functions of mcuxClEls_Cipher. +More...

+ + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cipher_Async (mcuxClEls_CipherOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pIV, uint8_t *pOutput)
 Performs AES encryption/decryption. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Cipher.

+

Function Documentation

+ +

◆ mcuxClEls_Cipher_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cipher_Async (mcuxClEls_CipherOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pInput,
size_t inputLength,
uint8_t * pIV,
uint8_t * pOutput 
)
+
+ +

Performs AES encryption/decryption.

+

Performs an AES encryption/decryption. Call mcuxClEls_WaitForOperation to complete the operation.

Parameters
+ + + + + + + + + +
[in]optionsEncryption/decryption command options. For detailed information, see mcuxClEls_CipherOption_t.
[in]keyIdxIndex of the key inside the ELS keystore. See parameter properties section in function description.
[in]pKeyMemory area that contains the key. See parameter properties section in function description.
[in]keyLengthSize of pKey in bytes. Must be a valid key size of MCUXCLELS_CIPHER_KEY_SIZE_AES_. See parameter properties section in function description.
[in]pInputPointer to the input data to be encrypted/decrypted. Padding must be already applied.
[in]inputLengthSize of pInput in bytes, must be a multiple of the block size.
[in,out]pIVA pointer to the memory location which contains/receives the IV/state of cipher. See parameter properties section in function description.
[out]pOutputPointer to the output buffer to store encrypted/decrypted data.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.cphmde == MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
+

pIV is ignored.

+

+
+
options.cphmde == MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
+

pIV must be set to the IV (when encrypting the first block) or to the last block of the ciphertext of the previous operation. ELS will always read and write to this location.

+

options.cphsie is ignored. 

     @p options.cphsoe is ignored.</dd>
+
+ <dt>@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR</dt>
+     <dd>@p pIV must be set to the IV (when encrypting the first block) or to the state output of the previous
+     encryption/decryption operation. ELS will write to this location if @p options.cphsoe == #MCUXCLELS_CIPHER_STATE_OUT_ENABLE.</dd>
+
+ <dt>@p options.extkey == #MCUXCLELS_CIPHER_EXTERNAL_KEY</dt>
+     <dd>@p keyIdx is ignored.</dd>
+
+ <dt>@p options.extkey == #MCUXCLELS_CIPHER_INTERNAL_KEY</dt>
+     <dd>@p pKey is ignored.
+
+     @p keyLength is ignored.</dd>
+

+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00699.js b/components/els_pkc/doc/mcxn/html/a00699.js new file mode 100644 index 000000000..c14dd3fd0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00699.js @@ -0,0 +1,4 @@ +var a00699 = +[ + [ "mcuxClEls_Cipher_Async", "a00699.html#gad8b0506b0510f7dc6ef20fd488ee004b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00700.html b/components/els_pkc/doc/mcxn/html/a00700.html new file mode 100644 index 000000000..cf14534f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00700.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Cmac
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC). +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Cmac_Macros
 Defines all macros of mcuxClEls_Cmac.
 
 mcuxClEls_Cmac_Types
 Defines all types of mcuxClEls_Cmac.
 
 mcuxClEls_Cmac_Functions
 Defines all functions of mcuxClEls_Cmac.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC).

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00700.js b/components/els_pkc/doc/mcxn/html/a00700.js new file mode 100644 index 000000000..86e54ae48 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00700.js @@ -0,0 +1,6 @@ +var a00700 = +[ + [ "mcuxClEls_Cmac_Macros", "a00701.html", "a00701" ], + [ "mcuxClEls_Cmac_Types", "a00704.html", "a00704" ], + [ "mcuxClEls_Cmac_Functions", "a00705.html", "a00705" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00701.html b/components/els_pkc/doc/mcxn/html/a00701.html new file mode 100644 index 000000000..3157abc73 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00701.html @@ -0,0 +1,159 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClEls_Cmac_Macros
mcuxClEls » mcuxClEls_Cmac
+
+
+ +

Defines all macros of mcuxClEls_Cmac. +More...

+ + + + + + + + +

+Modules

 MCUXCLELS_CMAC_KEY_SIZE_
 Valid CMAC key sizes in bytes.
 
 MCUXCLELS_CMAC_
 Option values for mcuxClEls_CmacOption_t.
 
+ + + +

+Macros

#define MCUXCLELS_CMAC_OUT_SIZE
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Cmac.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMAC_OUT_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_OUT_SIZE
+
+

Size of CMAC output: 128 bit (16 bytes)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00701.js b/components/els_pkc/doc/mcxn/html/a00701.js new file mode 100644 index 000000000..11385cc9b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00701.js @@ -0,0 +1,6 @@ +var a00701 = +[ + [ "MCUXCLELS_CMAC_KEY_SIZE_", "a00702.html", "a00702" ], + [ "MCUXCLELS_CMAC_", "a00703.html", "a00703" ], + [ "MCUXCLELS_CMAC_OUT_SIZE", "a00701.html#ga5e153a25264389155e68014c29ddf815", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00702.html b/components/els_pkc/doc/mcxn/html/a00702.html new file mode 100644 index 000000000..153648568 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00702.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CMAC_KEY_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
+
+
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+Macros
+
+
MCUXCLELS_CMAC_KEY_SIZE_
mcuxClEls » mcuxClEls_Cmac » mcuxClEls_Cmac_Macros
+
+
+ +

Valid CMAC key sizes in bytes. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_CMAC_KEY_SIZE_128
 Size of 128 bit CMAC key (16 bytes) More...
 
#define MCUXCLELS_CMAC_KEY_SIZE_256
 Size of 256 bit CMAC key (32 bytes) More...
 
+

Detailed Description

+

Valid CMAC key sizes in bytes.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMAC_KEY_SIZE_128

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_KEY_SIZE_128
+
+ +

Size of 128 bit CMAC key (16 bytes)

+ +
+
+ +

◆ MCUXCLELS_CMAC_KEY_SIZE_256

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_KEY_SIZE_256
+
+ +

Size of 256 bit CMAC key (32 bytes)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00702.js b/components/els_pkc/doc/mcxn/html/a00702.js new file mode 100644 index 000000000..ea48e2c48 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00702.js @@ -0,0 +1,5 @@ +var a00702 = +[ + [ "MCUXCLELS_CMAC_KEY_SIZE_128", "a00702.html#ga62fa42c9462e49ed1e357287492a64e8", null ], + [ "MCUXCLELS_CMAC_KEY_SIZE_256", "a00702.html#gab62855422ff04c5fb61bdcd555282931", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00703.html b/components/els_pkc/doc/mcxn/html/a00703.html new file mode 100644 index 000000000..803f76e98 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00703.html @@ -0,0 +1,246 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CMAC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_CMAC_
mcuxClEls » mcuxClEls_Cmac » mcuxClEls_Cmac_Macros
+
+
+ +

Option values for mcuxClEls_CmacOption_t. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
 Set mcuxClEls_CmacOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
 Set mcuxClEls_CmacOption_t.extkey to this value to use a key from the ELS keystore. More...
 
#define MCUXCLELS_CMAC_INITIALIZE_DISABLE
 Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk does not include the first block of the message. More...
 
#define MCUXCLELS_CMAC_INITIALIZE_ENABLE
 Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk includes the first block of the message. More...
 
#define MCUXCLELS_CMAC_FINALIZE_DISABLE
 Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk does not include the last block of the message. More...
 
#define MCUXCLELS_CMAC_FINALIZE_ENABLE
 Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk includes the last block of the message. More...
 
+

Detailed Description

+

Option values for mcuxClEls_CmacOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
+
+ +

Set mcuxClEls_CmacOption_t.extkey to this value to use an external key.

+ +
+
+ +

◆ MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
+
+ +

Set mcuxClEls_CmacOption_t.extkey to this value to use a key from the ELS keystore.

+ +
+
+ +

◆ MCUXCLELS_CMAC_INITIALIZE_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_INITIALIZE_DISABLE
+
+ +

Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk does not include the first block of the message.

+ +
+
+ +

◆ MCUXCLELS_CMAC_INITIALIZE_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_INITIALIZE_ENABLE
+
+ +

Set mcuxClEls_CmacOption_t.initialize to this value if the message chunk includes the first block of the message.

+ +
+
+ +

◆ MCUXCLELS_CMAC_FINALIZE_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_FINALIZE_DISABLE
+
+ +

Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk does not include the last block of the message.

+ +
+
+ +

◆ MCUXCLELS_CMAC_FINALIZE_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMAC_FINALIZE_ENABLE
+
+ +

Set mcuxClEls_CmacOption_t.finalize to this value if the message chunk includes the last block of the message.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00703.js b/components/els_pkc/doc/mcxn/html/a00703.js new file mode 100644 index 000000000..cab544e29 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00703.js @@ -0,0 +1,9 @@ +var a00703 = +[ + [ "MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE", "a00703.html#ga0b115dc62b80bece0cfbb37d8d6be71c", null ], + [ "MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE", "a00703.html#gaf8cc08552ae462283ee61cd55a1e6e6d", null ], + [ "MCUXCLELS_CMAC_INITIALIZE_DISABLE", "a00703.html#ga21b0dadab5a6ff16fa81b41a8bf8d190", null ], + [ "MCUXCLELS_CMAC_INITIALIZE_ENABLE", "a00703.html#ga556198894993c42af47bb004ddde6f8e", null ], + [ "MCUXCLELS_CMAC_FINALIZE_DISABLE", "a00703.html#ga5a7186be485cefe12529107214dd872b", null ], + [ "MCUXCLELS_CMAC_FINALIZE_ENABLE", "a00703.html#ga923398d224ee92df39da7b5a27982850", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00704.html b/components/els_pkc/doc/mcxn/html/a00704.html new file mode 100644 index 000000000..bfb0f2117 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00704.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Cmac_Types
mcuxClEls » mcuxClEls_Cmac
+
+
+ +

Defines all types of mcuxClEls_Cmac. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_CmacOption_t
 Command option bit field for mcuxClEls_Cmac_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Cmac.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00704.js b/components/els_pkc/doc/mcxn/html/a00704.js new file mode 100644 index 000000000..736611e93 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00704.js @@ -0,0 +1,15 @@ +var a00704 = +[ + [ "mcuxClEls_CmacOption_t", "a01021.html", [ + [ "value", "a01021.html#ab326f666bbbcabd39dc0bd26a83fa5c0", null ], + [ "word", "a01021.html#aa34c3bf115a202c3c96b967bc6114498", null ], + [ "initialize", "a01021.html#a90660bb1c9ee7d9f1d53209ab53dba4b", null ], + [ "finalize", "a01021.html#aabd3ce3a952bdd2279b7f4d0a2e22da8", null ], + [ "soe", "a01021.html#a69e48d5d1edf8300761b237872e4192f", null ], + [ "sie", "a01021.html#ab165c41c5cf41abf2b463ab742fa0c1b", null ], + [ "__pad0__", "a01021.html#add5bf1feb8f2a41a0f46c1bb06f15db0", null ], + [ "extkey", "a01021.html#a1d6db09e93aaf0c0d428e719dbff29fe", null ], + [ "__pad1__", "a01021.html#ace1fa4ccaa7741b93563ac6ace23989d", null ], + [ "bits", "a01021.html#a6cb17fd040a2db25cdaafe3e042b0831", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00705.html b/components/els_pkc/doc/mcxn/html/a00705.html new file mode 100644 index 000000000..e8f1d777e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00705.html @@ -0,0 +1,241 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cmac_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Cmac_Functions
mcuxClEls » mcuxClEls_Cmac
+
+
+ +

Defines all functions of mcuxClEls_Cmac. +More...

+ + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cmac_Async (mcuxClEls_CmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pKey, size_t keyLength, uint8_t const *pInput, size_t inputLength, uint8_t *pMac)
 Performs CMAC with AES-128 or AES-256. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Cmac.

+

Function Documentation

+ +

◆ mcuxClEls_Cmac_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Cmac_Async (mcuxClEls_CmacOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pKey,
size_t keyLength,
uint8_t const * pInput,
size_t inputLength,
uint8_t * pMac 
)
+
+ +

Performs CMAC with AES-128 or AES-256.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_CmacOption_t.
[in]keyIdxThe CMAC key index
[in]pKeyPointer to the padded CMAC key
[in]keyLengthSize of pKey in bytes. Must be a valid CMAC key size. See the parameter properties section in the function description.
[in]pInputPointer to a memory location which contains the data, padded via SP 800-38b standard, to be authenticated
[in]inputLengthSize of pInput in bytes before padding
[in,out]pMacPointer to the CMAC command state input/output. See the parameter properties section in the function description.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
+

keyIdx is ignored.

+

+
+
options.extkey == MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
+

pKey is ignored.

+

keyLength is ignored.

+

+
+
(options.finalize == MCUXCLELS_CMAC_FINALIZE_DISABLE)
+

The intermediate state is written to pMac.

+

+
+
options.finalize == MCUXCLELS_CMAC_FINALIZE_ENABLE
+

The resulting MAC is written to pMac.

+

options.soe is ignored.

+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif an invalid parameter was specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00705.js b/components/els_pkc/doc/mcxn/html/a00705.js new file mode 100644 index 000000000..33061fe85 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00705.js @@ -0,0 +1,4 @@ +var a00705 = +[ + [ "mcuxClEls_Cmac_Async", "a00705.html#ga0cc7e60d184ae44edd8ac6376ecf2387", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00706.html b/components/els_pkc/doc/mcxn/html/a00706.html new file mode 100644 index 000000000..d4115e3e9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00706.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Common
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports common functionality. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Common_Macros
 Defines all macros of mcuxClEls_Common.
 
 mcuxClEls_Common_Types
 Defines all types of mcuxClEls_Common.
 
 mcuxClEls_Common_Functions
 Defines all functions of mcuxClEls_Common.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports common functionality.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00706.js b/components/els_pkc/doc/mcxn/html/a00706.js new file mode 100644 index 000000000..96051732b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00706.js @@ -0,0 +1,6 @@ +var a00706 = +[ + [ "mcuxClEls_Common_Macros", "a00707.html", "a00707" ], + [ "mcuxClEls_Common_Types", "a00716.html", "a00716" ], + [ "mcuxClEls_Common_Functions", "a00717.html", "a00717" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00707.html b/components/els_pkc/doc/mcxn/html/a00707.html new file mode 100644 index 000000000..198c69099 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00707.html @@ -0,0 +1,201 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClEls_Common_Macros
mcuxClEls » mcuxClEls_Common
+
+
+ +

Defines all macros of mcuxClEls_Common. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 mcuxClEls_InterruptOptionEn_t
 Defines interrupt enable option values.
 
 mcuxClEls_InterruptOptionRst_t
 Defines interrupt reset option values.
 
 mcuxClEls_InterruptOptionSet_t
 Defines interrupt set option values.
 
 MCUXCLELS_ERROR_FLAGS_
 Options for error flag clearing.
 
 MCUXCLELS_RESET_
 Options for reset handling.
 
 MCUXCLELS_STATUS_PPROT_
 Values for the privilege/security level of ELS commands.
 
 MCUXCLELS_STATUS_ECDSAVFY_
 ECDSA verify check values.
 
 MCUXCLELS_STATUS_DRBGENTLVL_
 Constants for Entropy quality of the current DRBG instance.
 
+ + + + + + + + + +

+Macros

#define MCUXCLELS_API
 Marks a function as a public API function of the mcuxClEls component. More...
 
#define MCUXCLELS_HW_VERSION
 Compatible ELS hardware IP version for the CLNS release that this header is part of. More...
 
+#define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Common.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_API

+ +
+
+ + + + +
#define MCUXCLELS_API
+
+ +

Marks a function as a public API function of the mcuxClEls component.

+ +
+
+ +

◆ MCUXCLELS_HW_VERSION

+ +
+
+ + + + +
#define MCUXCLELS_HW_VERSION
+
+ +

Compatible ELS hardware IP version for the CLNS release that this header is part of.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00707.js b/components/els_pkc/doc/mcxn/html/a00707.js new file mode 100644 index 000000000..417e083c1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00707.js @@ -0,0 +1,13 @@ +var a00707 = +[ + [ "mcuxClEls_InterruptOptionEn_t", "a00708.html", "a00708" ], + [ "mcuxClEls_InterruptOptionRst_t", "a00709.html", "a00709" ], + [ "mcuxClEls_InterruptOptionSet_t", "a00710.html", "a00710" ], + [ "MCUXCLELS_ERROR_FLAGS_", "a00711.html", "a00711" ], + [ "MCUXCLELS_RESET_", "a00712.html", "a00712" ], + [ "MCUXCLELS_STATUS_PPROT_", "a00713.html", "a00713" ], + [ "MCUXCLELS_STATUS_ECDSAVFY_", "a00714.html", "a00714" ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_", "a00715.html", "a00715" ], + [ "MCUXCLELS_API", "a00707.html#ga5f87370c0e52126f57afb5b13c283d73", null ], + [ "MCUXCLELS_HW_VERSION", "a00707.html#gac06d5de9fa68404bc11b426ed3cdd8f6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00708.html b/components/els_pkc/doc/mcxn/html/a00708.html new file mode 100644 index 000000000..aa4260c1e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00708.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionEn_t + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
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+
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+
+Macros
+
+
mcuxClEls_InterruptOptionEn_t
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Defines interrupt enable option values. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_ELS_INTERRUPT_ENABLE
 Set this option at mcuxClEls_InterruptOptionEn_t.elsint to allow ELS to trigger an interrupt. More...
 
#define MCUXCLELS_ELS_INTERRUPT_DISABLE
 Set this option at mcuxClEls_InterruptOptionEn_t.elsint to prevent ELS from triggering an interrupt. More...
 
+

Detailed Description

+

Defines interrupt enable option values.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ELS_INTERRUPT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_ELS_INTERRUPT_ENABLE
+
+ +

Set this option at mcuxClEls_InterruptOptionEn_t.elsint to allow ELS to trigger an interrupt.

+ +
+
+ +

◆ MCUXCLELS_ELS_INTERRUPT_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_ELS_INTERRUPT_DISABLE
+
+ +

Set this option at mcuxClEls_InterruptOptionEn_t.elsint to prevent ELS from triggering an interrupt.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00708.js b/components/els_pkc/doc/mcxn/html/a00708.js new file mode 100644 index 000000000..17d18ee73 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00708.js @@ -0,0 +1,5 @@ +var a00708 = +[ + [ "MCUXCLELS_ELS_INTERRUPT_ENABLE", "a00708.html#ga845d16f6376f2c28864f1855ddbde61c", null ], + [ "MCUXCLELS_ELS_INTERRUPT_DISABLE", "a00708.html#ga2427d922e877e78bac483cf68f6c5892", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00709.html b/components/els_pkc/doc/mcxn/html/a00709.html new file mode 100644 index 000000000..411b14713 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00709.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionRst_t + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+Macros
+
+
mcuxClEls_InterruptOptionRst_t
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Defines interrupt reset option values. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_ELS_RESET_CLEAR
 Set this option at mcuxClEls_InterruptOptionRst_t.elsint to reset the ELS interrupt flag. More...
 
#define MCUXCLELS_ELS_RESET_KEEP
 Set this option at mcuxClEls_InterruptOptionRst_t.elsint to keep the ELS interrupt flag. More...
 
+

Detailed Description

+

Defines interrupt reset option values.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ELS_RESET_CLEAR

+ +
+
+ + + + +
#define MCUXCLELS_ELS_RESET_CLEAR
+
+ +

Set this option at mcuxClEls_InterruptOptionRst_t.elsint to reset the ELS interrupt flag.

+ +
+
+ +

◆ MCUXCLELS_ELS_RESET_KEEP

+ +
+
+ + + + +
#define MCUXCLELS_ELS_RESET_KEEP
+
+ +

Set this option at mcuxClEls_InterruptOptionRst_t.elsint to keep the ELS interrupt flag.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00709.js b/components/els_pkc/doc/mcxn/html/a00709.js new file mode 100644 index 000000000..1954a5da5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00709.js @@ -0,0 +1,5 @@ +var a00709 = +[ + [ "MCUXCLELS_ELS_RESET_CLEAR", "a00709.html#ga1a702565c0bfd8fa6b28db41f61ba3be", null ], + [ "MCUXCLELS_ELS_RESET_KEEP", "a00709.html#gac963d24ca31b1b3e89d31efb7ccf6abf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00710.html b/components/els_pkc/doc/mcxn/html/a00710.html new file mode 100644 index 000000000..2b2e22578 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00710.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionSet_t + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
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+
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+Macros
+
+
mcuxClEls_InterruptOptionSet_t
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Defines interrupt set option values. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_ELS_INTERRUPT_SET
 Set this option at mcuxClEls_InterruptOptionSet_t.elsint to set the ELS interrupt flag. More...
 
#define MCUXCLELS_ELS_INTERRUPT_KEEP
 Set this option at mcuxClEls_InterruptOptionSet_t.elsint to leave the ELS interrupt flag unchanged. More...
 
+

Detailed Description

+

Defines interrupt set option values.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ELS_INTERRUPT_SET

+ +
+
+ + + + +
#define MCUXCLELS_ELS_INTERRUPT_SET
+
+ +

Set this option at mcuxClEls_InterruptOptionSet_t.elsint to set the ELS interrupt flag.

+ +
+
+ +

◆ MCUXCLELS_ELS_INTERRUPT_KEEP

+ +
+
+ + + + +
#define MCUXCLELS_ELS_INTERRUPT_KEEP
+
+ +

Set this option at mcuxClEls_InterruptOptionSet_t.elsint to leave the ELS interrupt flag unchanged.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00710.js b/components/els_pkc/doc/mcxn/html/a00710.js new file mode 100644 index 000000000..b56a5b59d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00710.js @@ -0,0 +1,5 @@ +var a00710 = +[ + [ "MCUXCLELS_ELS_INTERRUPT_SET", "a00710.html#ga08923159f1ba8aff0b1b06a547db7ff6", null ], + [ "MCUXCLELS_ELS_INTERRUPT_KEEP", "a00710.html#gab3911a79259043879d2446269741ac19", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00711.html b/components/els_pkc/doc/mcxn/html/a00711.html new file mode 100644 index 000000000..f452f6e8b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00711.html @@ -0,0 +1,172 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_ERROR_FLAGS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_ERROR_FLAGS_
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Options for error flag clearing. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_ERROR_FLAGS_KEEP
 Set this option at mcuxClEls_ErrorHandling_t to not clear any error flags. More...
 
#define MCUXCLELS_ERROR_FLAGS_CLEAR
 Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags. More...
 
+

Detailed Description

+

Options for error flag clearing.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ERROR_FLAGS_KEEP

+ +
+
+ + + + +
#define MCUXCLELS_ERROR_FLAGS_KEEP
+
+ +

Set this option at mcuxClEls_ErrorHandling_t to not clear any error flags.

+ +
+
+ +

◆ MCUXCLELS_ERROR_FLAGS_CLEAR

+ +
+
+ + + + +
#define MCUXCLELS_ERROR_FLAGS_CLEAR
+
+ +

Set this option at mcuxClEls_ErrorHandling_t to clear all ELS error flags.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00711.js b/components/els_pkc/doc/mcxn/html/a00711.js new file mode 100644 index 000000000..8821d16c4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00711.js @@ -0,0 +1,5 @@ +var a00711 = +[ + [ "MCUXCLELS_ERROR_FLAGS_KEEP", "a00711.html#gab2b0ee14cae59a5f5f4f2563d7189854", null ], + [ "MCUXCLELS_ERROR_FLAGS_CLEAR", "a00711.html#ga3528b1fa2b3c39524898299a3a90a753", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00712.html b/components/els_pkc/doc/mcxn/html/a00712.html new file mode 100644 index 000000000..f2e209a01 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00712.html @@ -0,0 +1,172 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_RESET_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_RESET_
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Options for reset handling. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_RESET_DO_NOT_CANCEL
 Set this option at mcuxClEls_ResetOption_t to abort the requested command if another ELS operation is still running. More...
 
#define MCUXCLELS_RESET_CANCEL
 Set this option at mcuxClEls_ResetOption_t to execute the requested command even if another ELS operation is still running. More...
 
+

Detailed Description

+

Options for reset handling.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_RESET_DO_NOT_CANCEL

+ +
+
+ + + + +
#define MCUXCLELS_RESET_DO_NOT_CANCEL
+
+ +

Set this option at mcuxClEls_ResetOption_t to abort the requested command if another ELS operation is still running.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Common_Get_Info_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Rng_Prng_Get_Random_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_RESET_CANCEL

+ +
+
+ + + + +
#define MCUXCLELS_RESET_CANCEL
+
+ +

Set this option at mcuxClEls_ResetOption_t to execute the requested command even if another ELS operation is still running.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00712.js b/components/els_pkc/doc/mcxn/html/a00712.js new file mode 100644 index 000000000..e7901723a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00712.js @@ -0,0 +1,5 @@ +var a00712 = +[ + [ "MCUXCLELS_RESET_DO_NOT_CANCEL", "a00712.html#gac02fc8694aa89061b1eb47bad8fca21d", null ], + [ "MCUXCLELS_RESET_CANCEL", "a00712.html#ga1f4338ba7f7d0ddd5b84236bc4545ee3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00713.html b/components/els_pkc/doc/mcxn/html/a00713.html new file mode 100644 index 000000000..2243388f8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00713.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_STATUS_PPROT_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_STATUS_PPROT_
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Values for the privilege/security level of ELS commands. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged non-secure mode. More...
 
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE
 This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged non-secure mode. More...
 
+

Detailed Description

+

Values for the privilege/security level of ELS commands.

+

Note that some keys and memory areas may only be accessible when ELS is on a certain privilege/security level.

+

The default value, before any command has been executed, is MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE
+
+ +

This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged secure mode.

+ +
+
+ +

◆ MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE
+
+ +

This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged secure mode.

+ +
+
+ +

◆ MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE
+
+ +

This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged non-secure mode.

+ +
+
+ +

◆ MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE
+
+ +

This value of mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged non-secure mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00713.js b/components/els_pkc/doc/mcxn/html/a00713.js new file mode 100644 index 000000000..951c9fec4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00713.js @@ -0,0 +1,7 @@ +var a00713 = +[ + [ "MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE", "a00713.html#gaa8bbf4768eed46d69b6a9077f51c1481", null ], + [ "MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE", "a00713.html#ga11ba151ce5c794f3f433b1261c95f68c", null ], + [ "MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE", "a00713.html#gab95d873091d5a836bc3e37079766fb2e", null ], + [ "MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE", "a00713.html#ga9fd4449827c0ff5467277eca65c9d647", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00714.html b/components/els_pkc/doc/mcxn/html/a00714.html new file mode 100644 index 000000000..acd94647a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00714.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_STATUS_ECDSAVFY_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_STATUS_ECDSAVFY_
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

ECDSA verify check values. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_STATUS_ECDSAVFY_NORUN
 This value of mcuxClEls_HwState_t.ecdsavfy means that no ECDSA verify operation has been executed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_FAIL
 This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification failed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_OK
 This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification passed. More...
 
#define MCUXCLELS_STATUS_ECDSAVFY_ERROR
 This value of mcuxClEls_HwState_t.ecdsavfy means that an error has occurred. More...
 
+

Detailed Description

+

ECDSA verify check values.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_STATUS_ECDSAVFY_NORUN

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_ECDSAVFY_NORUN
+
+ +

This value of mcuxClEls_HwState_t.ecdsavfy means that no ECDSA verify operation has been executed.

+ +
+
+ +

◆ MCUXCLELS_STATUS_ECDSAVFY_FAIL

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_ECDSAVFY_FAIL
+
+ +

This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification failed.

+ +
+
+ +

◆ MCUXCLELS_STATUS_ECDSAVFY_OK

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_ECDSAVFY_OK
+
+ +

This value of mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification passed.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_STATUS_ECDSAVFY_ERROR

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_ECDSAVFY_ERROR
+
+ +

This value of mcuxClEls_HwState_t.ecdsavfy means that an error has occurred.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00714.js b/components/els_pkc/doc/mcxn/html/a00714.js new file mode 100644 index 000000000..e2daf74b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00714.js @@ -0,0 +1,7 @@ +var a00714 = +[ + [ "MCUXCLELS_STATUS_ECDSAVFY_NORUN", "a00714.html#ga47e2750982e2b0db292e2a9944c1f635", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_FAIL", "a00714.html#ga647b29383be891aba96ede66ae327401", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_OK", "a00714.html#ga893b34cd2238053fb44a50ebe33bb5e3", null ], + [ "MCUXCLELS_STATUS_ECDSAVFY_ERROR", "a00714.html#ga9472855457417ea944570647a61c2b47", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00715.html b/components/els_pkc/doc/mcxn/html/a00715.html new file mode 100644 index 000000000..a02a74681 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00715.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_STATUS_DRBGENTLVL_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_STATUS_DRBGENTLVL_
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Macros
+
+
+ +

Constants for Entropy quality of the current DRBG instance. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCLELS_STATUS_DRBGENTLVL_NONE
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG is not running. More...
 
#define MCUXCLELS_STATUS_DRBGENTLVL_LOW
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with a low security strength (sufficient for commands with a low DRBG security strength requirement, see the function description to check which level is required) More...
 
#define MCUXCLELS_STATUS_DRBGENTLVL_HIGH
 This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with 128 bits of security strength (sufficient for commands with a high DRBG security strength requirement, see the function description to check which level is required) More...
 
+

Detailed Description

+

Constants for Entropy quality of the current DRBG instance.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_STATUS_DRBGENTLVL_NONE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_DRBGENTLVL_NONE
+
+ +

This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG is not running.

+ +
+
+ +

◆ MCUXCLELS_STATUS_DRBGENTLVL_LOW

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_DRBGENTLVL_LOW
+
+ +

This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with a low security strength (sufficient for commands with a low DRBG security strength requirement, see the function description to check which level is required)

+ +
+
+ +

◆ MCUXCLELS_STATUS_DRBGENTLVL_HIGH

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_DRBGENTLVL_HIGH
+
+ +

This value of mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with 128 bits of security strength (sufficient for commands with a high DRBG security strength requirement, see the function description to check which level is required)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00715.js b/components/els_pkc/doc/mcxn/html/a00715.js new file mode 100644 index 000000000..3b292a14d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00715.js @@ -0,0 +1,6 @@ +var a00715 = +[ + [ "MCUXCLELS_STATUS_DRBGENTLVL_NONE", "a00715.html#ga5fe71d0b1d8e1c52794c24a98b6e2645", null ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_LOW", "a00715.html#ga1276cd61f68f743f631cdae25662b310", null ], + [ "MCUXCLELS_STATUS_DRBGENTLVL_HIGH", "a00715.html#ga9e70aa4c959f092c77fc154327bc4bdb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00716.html b/components/els_pkc/doc/mcxn/html/a00716.html new file mode 100644 index 000000000..5c33f8d7e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00716.html @@ -0,0 +1,220 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Macros | +Typedefs
+
+
mcuxClEls_Common_Types
mcuxClEls » mcuxClEls_Common
+
+
+ +

Defines all types of mcuxClEls_Common. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Data Structures

union  mcuxClEls_HwVersion_t
 Result type of mcuxClEls_GetHwVersion. More...
 
union  mcuxClEls_HwState_t
 Result type of mcuxClEls_GetHwState. More...
 
union  mcuxClEls_InterruptOptionEn_t
 Command option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags. More...
 
union  mcuxClEls_InterruptOptionRst_t
 Type to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags. More...
 
union  mcuxClEls_InterruptOptionSet_t
 Type to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags. More...
 
union  mcuxClEls_HwConfig_t
 Result type of #mcuxClEls_GetHwConfig. More...
 
+ + + + +

+Macros

#define drbgreqsub
 Deprecated name for mcuxClEls_HwConfig_t.drbgreqsup. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClEls_ErrorHandling_t
 Type to handle ELS error clearing options. More...
 
typedef uint32_t mcuxClEls_ResetOption_t
 Type to handle ELS reset options. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Common.

+

Macro Definition Documentation

+ +

◆ drbgreqsub

+ +
+
+ + + + +
#define drbgreqsub
+
+ +

Deprecated name for mcuxClEls_HwConfig_t.drbgreqsup.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+

Typedef Documentation

+ +

◆ mcuxClEls_ErrorHandling_t

+ +
+
+ + + + +
typedef uint32_t mcuxClEls_ErrorHandling_t
+
+ +

Type to handle ELS error clearing options.

+

For possible values, see MCUXCLELS_ERROR_FLAGS_.

+ +
+
+ +

◆ mcuxClEls_ResetOption_t

+ +
+
+ + + + +
typedef uint32_t mcuxClEls_ResetOption_t
+
+ +

Type to handle ELS reset options.

+

For possible values, see MCUXCLELS_RESET_.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00716.js b/components/els_pkc/doc/mcxn/html/a00716.js new file mode 100644 index 000000000..b525ce262 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00716.js @@ -0,0 +1,85 @@ +var a00716 = +[ + [ "mcuxClEls_HwVersion_t", "a01033.html", [ + [ "value", "a01033.html#a5e9b7103d2b419e9d860c04eb142d6e2", null ], + [ "word", "a01033.html#a87650934fb456d15383c0e0de64f93b2", null ], + [ "revision", "a01033.html#a11c1bba1b577058ea774f9fb51dfd449", null ], + [ "minor", "a01033.html#a648e4b690824c4652c70d707e00b6ffe", null ], + [ "major", "a01033.html#a0c4765f9784a475579e0fd433a753011", null ], + [ "level", "a01033.html#a362c318252fad3db6e55fde7dac2572f", null ], + [ "__pad0__", "a01033.html#a3f71ee0da1f604f06bce53faaee88549", null ], + [ "bits", "a01033.html#a107c920f079a09f0078dd0791faa2110", null ] + ] ], + [ "mcuxClEls_HwState_t", "a01045.html", [ + [ "value", "a01045.html#a9e0ca3d1f7797c407e594e55411549b0", null ], + [ "word", "a01045.html#a8318bd94bd3469bac07874ba2921d0cf", null ], + [ "busy", "a01045.html#a453ae753658b4809ea3141fffd5641c8", null ], + [ "irq", "a01045.html#afaa797f8db7f6252bf4ae54eb875c7fd", null ], + [ "err", "a01045.html#a5513d9d58397ac4701044421f2c8fd28", null ], + [ "prngready", "a01045.html#afbd164dd41b80e5a24310b6dac33cf79", null ], + [ "ecdsavfy", "a01045.html#a41492f22ac15d4cc4feebd517faa75ba", null ], + [ "pprot", "a01045.html#ac5b11ab2a0744e13303e920bee052f5b", null ], + [ "drbgentlvl", "a01045.html#a87b6c5ce545619bb478efcc020f862ff", null ], + [ "dtrng_busy", "a01045.html#a05b012990a92e9deaada4a5d87ac380a", null ], + [ "__pad0__", "a01045.html#ae4d9f2540dc7380b776ff6de6325c22f", null ], + [ "__pad1__", "a01045.html#aacebdfe99f0d29f126adc2a9d42a4b22", null ], + [ "__pad2__", "a01045.html#a68593765ff0c58861d600be91ee332a3", null ], + [ "__pad3__", "a01045.html#a240bdaa5a99cd057983b3cbe28e33fb1", null ], + [ "bits", "a01045.html#a3a7dbe3fd3f4e92c059cb39a04ac863e", null ] + ] ], + [ "mcuxClEls_InterruptOptionEn_t", "a01057.html", [ + [ "value", "a01057.html#a24184dcdf86670224ea536fc20a0e4d8", null ], + [ "word", "a01057.html#ad7e19b6dde1c236ad751eb9208e942db", null ], + [ "elsint", "a01057.html#a1ceef382dbc3fbafdff1d553658c7ea9", null ], + [ "__pad0__", "a01057.html#a71d456bef9a7a21d8ff55bc711a6a3bc", null ], + [ "__pad1__", "a01057.html#a502fdb51eeb304aabfd1ed4550ac3258", null ], + [ "bits", "a01057.html#ad3bc5d3ed1f3a1e38687c1742d3cf8f3", null ] + ] ], + [ "mcuxClEls_InterruptOptionRst_t", "a01069.html", [ + [ "value", "a01069.html#afe633f619c2da24bd5a99cf97782924b", null ], + [ "word", "a01069.html#ad45dfa4c603c021060fc0b4fdf0f769d", null ], + [ "elsint", "a01069.html#a8123125e41c363c03e6a671e94543d3d", null ], + [ "__pad0__", "a01069.html#ad560c85d9ea7975330ec5a2e207b30c0", null ], + [ "__pad1__", "a01069.html#a188253366e073fdcbdccbaa41ccbe915", null ], + [ "bits", "a01069.html#a38fff411deb5bfd137a206a35305d3e9", null ] + ] ], + [ "mcuxClEls_InterruptOptionSet_t", "a01081.html", [ + [ "value", "a01081.html#a58934a4a256905327206ee08d8c5931f", null ], + [ "word", "a01081.html#ac3c1022b8a8d5034511fd6ffcb76625d", null ], + [ "elsint", "a01081.html#a694dd46e51d111832674fdd7827ba7a2", null ], + [ "__pad0__", "a01081.html#a6f7f7fb21a47e0ba886c9c5ebdaae7bf", null ], + [ "__pad1__", "a01081.html#a3a1d6b3eaa5f8be52531ddb20f3e85c8", null ], + [ "bits", "a01081.html#ac8b9b47932507184288a99d01ee45b39", null ] + ] ], + [ "mcuxClEls_HwConfig_t", "a01093.html", [ + [ "value", "a01093.html#a2cf565902d36ad357eaaa793eb4be8d5", null ], + [ "word", "a01093.html#a57cd499ae60ad1bb19fc54517d9ff580", null ], + [ "ciphersup", "a01093.html#ac0db95aaf62ac50581111452e89de3ba", null ], + [ "authciphersup", "a01093.html#acd5dabf360244a33333e3063010ad26d", null ], + [ "ecsignsup", "a01093.html#ab5a3a301e2fa7ed724b1a10db46a4dc1", null ], + [ "ecvfysup", "a01093.html#a082dbc1af5f81f7d76e32c01e35a6c81", null ], + [ "eckxchsup", "a01093.html#ac9e323809993203e0867e37641f7d9e0", null ], + [ "keygensup", "a01093.html#add6853a64d3322d8400c601277d42afb", null ], + [ "keyinsup", "a01093.html#a10e2de8c251bc00183a2d578fb778661", null ], + [ "keyoutsup", "a01093.html#a6bbf59e55899238b17d7a1266d6a063a", null ], + [ "kdeletesup", "a01093.html#aff9488c467cfca4942ba41b51c4225b7", null ], + [ "keyprovsup", "a01093.html#a55ac97e5d1105cd9f5ac217d05a8e0c2", null ], + [ "ckdfsup", "a01093.html#a05b73ed0395351b9504c35f54ac50495", null ], + [ "hkdfsup", "a01093.html#af443a864be5d2d0ab3c6a2f007fe9afe", null ], + [ "tlsinitsup", "a01093.html#a9dc24a8f88688b9d4cc5c305acbf46e5", null ], + [ "hashsup", "a01093.html#ac5fc6ff1883c09e1ed72412f53514b13", null ], + [ "hmacsup", "a01093.html#a4cf06c58477f35949dc0089a3a3184ce", null ], + [ "cmacsup", "a01093.html#ad30966f27a451f027aed32c036289515", null ], + [ "drbgreqsup", "a01093.html#a1519b8980b5d2615c96ac1c788014e6d", null ], + [ "drbgtestsup", "a01093.html#ae70916d8e053e37a7de79db3c873cdd5", null ], + [ "dtrgncfgloadsup", "a01093.html#a1655b1afaf9b84514817f11e71f21232", null ], + [ "dtrngevalsup", "a01093.html#a7ab5fc2fd5378fbf9044f6eb47b74602", null ], + [ "gdetcfgloadsup", "a01093.html#a83e2de492b29950e62bdc159629a7e87", null ], + [ "gdettrimsup", "a01093.html#a546385b574e49302ba2e748303fa91a4", null ], + [ "__pad0__", "a01093.html#aa06967699abb851f567edb7ae687a0d2", null ], + [ "bits", "a01093.html#a95b4684aa6203efcdf26303743fdfcd5", null ] + ] ], + [ "drbgreqsub", "a00716.html#ga58d0f81d7d9c40f22d85d048150bbc72", null ], + [ "mcuxClEls_ErrorHandling_t", "a00716.html#ga3411a9581b6770690eba6acc6b69c278", null ], + [ "mcuxClEls_ResetOption_t", "a00716.html#gab1ed08db7ad22b92ac714d17566d2fff", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00717.html b/components/els_pkc/doc/mcxn/html/a00717.html new file mode 100644 index 000000000..34883918b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00717.html @@ -0,0 +1,684 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common_Functions + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Functions
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mcuxClEls_Common_Functions
mcuxClEls » mcuxClEls_Common
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+ +

Defines all functions of mcuxClEls_Common. +More...

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+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwVersion (mcuxClEls_HwVersion_t *result)
 Determines the version of the underlying ELS hardware IP. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwState (mcuxClEls_HwState_t *result)
 Determines the current state of the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Enable_Async (void)
 Enables the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async (mcuxClEls_ResetOption_t options)
 Perform a synchronous reset of the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Disable (void)
 Disable the ELS. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntEnableFlags (mcuxClEls_InterruptOptionEn_t options)
 Set interrupt enable flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetIntEnableFlags (mcuxClEls_InterruptOptionEn_t *result)
 Get interrupt enable flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetIntFlags (mcuxClEls_InterruptOptionRst_t options)
 Clear the interrupt status register. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntFlags (mcuxClEls_InterruptOptionSet_t options)
 Set the interrupt status register, for debug and testing purposes. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation (mcuxClEls_ErrorHandling_t errorHandling)
 Wait for an ELS operation and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_LimitedWaitForOperation (uint32_t counterLimit, mcuxClEls_ErrorHandling_t errorHandling)
 Await the completion of an ELS operation for a limited amount of time and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetErrorFlags (void)
 Resets all error flags that have been set by a previous operation. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorCode (mcuxClEls_ErrorHandling_t errorHandling)
 Get the last ELS error code and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorLevel (mcuxClEls_ErrorHandling_t errorHandling, uint32_t *errorLevel)
 Get the last ELS error code and level and optionally clear the error status. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetRandomStartDelay (uint32_t delay)
 Set the random start delay for AES based operations. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetRandomStartDelay (uint32_t *delay)
 Get the random start delay for AES based operations. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Common.

+

Function Documentation

+ +

◆ mcuxClEls_GetHwVersion()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwVersion (mcuxClEls_HwVersion_t * result)
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+ +

Determines the version of the underlying ELS hardware IP.

+
Attention
This header was delivered as part of a CLNS release which is compatible with a specific ELS hardware IP version, which is defined by the macro MCUXCLELS_HW_VERSION.
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Parameters
+ + +
[out]resultPointer which will be filled with the ELS hardware version
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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Examples
mcuxClEls_Common_Get_Info_example.c.
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◆ mcuxClEls_GetHwState()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetHwState (mcuxClEls_HwState_t * result)
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Determines the current state of the ELS.

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Parameters
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[out]resultPointer which will be filled with the ELS status information
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
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◆ mcuxClEls_Enable_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Enable_Async (void )
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+ +

Enables the ELS.

+

Call mcuxClEls_WaitForOperation to complete the operation.

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Returns
An error code that is always MCUXCLELS_STATUS_OK_WAIT
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◆ mcuxClEls_Reset_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Reset_Async (mcuxClEls_ResetOption_t options)
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Perform a synchronous reset of the ELS.

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This means that:

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  • any running ELS command will be stopped,
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  • all errors will be cleared,
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  • all keys will be deleted,
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  • any RNG entropy will be discarded,
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  • the glitch detector will be reset and
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  • the run-time fingerprint will be restored to its default value.
    • +
+

Call mcuxClEls_WaitForOperation to complete the operation.

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Parameters
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[in]optionsA value indicating whether any running ELS operations shall be canceled
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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Return values
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MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the reset
MCUXCLELS_STATUS_OK_WAITon successful request
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◆ mcuxClEls_Disable()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Disable (void )
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Disable the ELS.

+

This is useful as a power saving mechanism.

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Returns
An error code that is always MCUXCLELS_STATUS_OK
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+ +

◆ mcuxClEls_SetIntEnableFlags()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntEnableFlags (mcuxClEls_InterruptOptionEn_t options)
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Set interrupt enable flags.

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Parameters
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[in]optionsThe command options, determining which interrupts should be enabled or disabled. For more information, see mcuxClEls_InterruptOptionEn_t.
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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◆ mcuxClEls_GetIntEnableFlags()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetIntEnableFlags (mcuxClEls_InterruptOptionEn_t * result)
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Get interrupt enable flags.

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Parameters
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[out]resultPointer which is filled with the configuration of the interrupts enable register.
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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◆ mcuxClEls_ResetIntFlags()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetIntFlags (mcuxClEls_InterruptOptionRst_t options)
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Clear the interrupt status register.

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Parameters
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[in]optionsThe command options, determining which interrupt status bits should be cleared. For more information, see mcuxClEls_InterruptOptionRst_t.
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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◆ mcuxClEls_SetIntFlags()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetIntFlags (mcuxClEls_InterruptOptionSet_t options)
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Set the interrupt status register, for debug and testing purposes.

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Parameters
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[in]optionsThe command options, determining which interrupt status bits should be set. For more information, see mcuxClEls_InterruptOptionSet_t.
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Returns
An error code that is always MCUXCLELS_STATUS_OK
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◆ mcuxClEls_WaitForOperation()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_WaitForOperation (mcuxClEls_ErrorHandling_t errorHandling)
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Wait for an ELS operation and optionally clear the error status.

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If an ELS operation is active, this function waits for completion of that operation. For this, the busy flag of ELS is polled. Additionally, this function checks and returns any applicable error indication. If no operation is active, the function returns immediately.

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Parameters
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[in]errorHandlingDefine if error flags shall be cleared.
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Return values
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MCUXCLELS_STATUS_OKif the last operation was successful, or no operation was active
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
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◆ mcuxClEls_LimitedWaitForOperation()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_LimitedWaitForOperation (uint32_t counterLimit,
mcuxClEls_ErrorHandling_t errorHandling 
)
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+ +

Await the completion of an ELS operation for a limited amount of time and optionally clear the error status.

+

If an ELS operation is active, this function waits for completion of that operation until a counter expires. For this, the busy flag of ELS is polled. The counting mechanism behaves like a simple for-loop from counterLimit to one. This counter does not have a well-defined relationship to real-world time. Additionally, this function checks and returns any applicable error indication. If no operation is active, the function returns immediately.

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Parameters
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[in]counterLimitThe limit of the wait counter.
[in]errorHandlingDefine if error flags shall be cleared.
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Return values
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MCUXCLELS_STATUS_OKif the last operation was successful, or no operation was active
MCUXCLELS_STATUS_SW_COUNTER_EXPIREDif the counter expired while waiting for the operation to complete
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
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◆ mcuxClEls_ResetErrorFlags()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ResetErrorFlags (void )
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Resets all error flags that have been set by a previous operation.

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Returns
An error code that is always MCUXCLELS_STATUS_OK
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◆ mcuxClEls_GetErrorCode()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorCode (mcuxClEls_ErrorHandling_t errorHandling)
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Get the last ELS error code and optionally clear the error status.

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Parameters
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[in]errorHandlingDefine if error flags shall be cleared.
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Return values
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MCUXCLELS_STATUS_OKif the last operation was successful or no operation was active
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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◆ mcuxClEls_GetErrorLevel()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetErrorLevel (mcuxClEls_ErrorHandling_t errorHandling,
uint32_t * errorLevel 
)
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+ +

Get the last ELS error code and level and optionally clear the error status.

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Parameters
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[in]errorHandlingDefine if error flags shall be cleared.
[out]errorLevelPointer to the location that will receive the value of the error level.
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Return values
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MCUXCLELS_STATUS_OKif the last operation was successful or no operation was active
#MCUXCLELS_STATUS_if the last operation resulted in an error
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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◆ mcuxClEls_SetRandomStartDelay()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_SetRandomStartDelay (uint32_t delay)
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+ +

Set the random start delay for AES based operations.

+

This impacts mcuxClEls_Aead_*, mcuxClEls_Cipher_*, mcuxClEls_Cmac_*, ncpClEls_Ckdf_*, mcuxClEls_KeyImport_Async, mcuxClEls_KeyExport_Async

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Parameters
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[in]delayDefine the max random start delay. Acceptable values are a power of 2 minus one, starting from 0 to 1023 (0, 1, 3, 7, ..., 1023).
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Return values
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MCUXCLELS_STATUS_OKif the operation was successful
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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◆ mcuxClEls_GetRandomStartDelay()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetRandomStartDelay (uint32_t * delay)
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Get the random start delay for AES based operations.

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Parameters
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[out]delayPointer to store random start delay configuration.
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Return values
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MCUXCLELS_STATUS_OKif the operation was successful
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
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+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00717.js b/components/els_pkc/doc/mcxn/html/a00717.js new file mode 100644 index 000000000..40e04c729 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00717.js @@ -0,0 +1,19 @@ +var a00717 = +[ + [ "mcuxClEls_GetHwVersion", "a00717.html#gaade966640da314f17e6024ada7df6219", null ], + [ "mcuxClEls_GetHwState", "a00717.html#gadb25761b4c1a0de90f1420f459093bd5", null ], + [ "mcuxClEls_Enable_Async", "a00717.html#ga6dbf394b38add1c6967dab368435b657", null ], + [ "mcuxClEls_Reset_Async", "a00717.html#ga988b48898347ef4de0912cae0f631764", null ], + [ "mcuxClEls_Disable", "a00717.html#gacbf878536100314ce61081c54ea5ef9e", null ], + [ "mcuxClEls_SetIntEnableFlags", "a00717.html#ga1cfec63993fa918d3b590b41b3558d84", null ], + [ "mcuxClEls_GetIntEnableFlags", "a00717.html#ga3de0def8758ec5320102a0beb521da37", null ], + [ "mcuxClEls_ResetIntFlags", "a00717.html#ga02f29ce399968793e6091505ddd9fa5e", null ], + [ "mcuxClEls_SetIntFlags", "a00717.html#ga90b8060544476c2e7278157833410c97", null ], + [ "mcuxClEls_WaitForOperation", "a00717.html#gaee73cb4825b7722d9e085565170eb18e", null ], + [ "mcuxClEls_LimitedWaitForOperation", "a00717.html#ga396f130363332586a56b9667cf46fe7e", null ], + [ "mcuxClEls_ResetErrorFlags", "a00717.html#gaf5485491a0851bc3c475e50690219d74", null ], + [ "mcuxClEls_GetErrorCode", "a00717.html#gaeb4fc2a3a1115489dcb9912f7160cb7f", null ], + [ "mcuxClEls_GetErrorLevel", "a00717.html#ga896309eafc0aedbb5514ec4111b4d750", null ], + [ "mcuxClEls_SetRandomStartDelay", "a00717.html#gabe9a2fe0df05c3e99fcd4a7a9138a2c8", null ], + [ "mcuxClEls_GetRandomStartDelay", "a00717.html#ga1269f369af68e23e9ee8d282dc37c42b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00718.html b/components/els_pkc/doc/mcxn/html/a00718.html new file mode 100644 index 000000000..e17248317 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00718.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Crc
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver defines the Command CRC functionality. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Crc_Macros
 Defines all macros of mcuxClEls_Crc.
 
 mcuxClEls_Crc_Types
 Defines all types of mcuxClEls_Crc.
 
 mcuxClEls_Crc_Functions
 Defines all functions of mcuxClEls_Crc.
 
+

Detailed Description

+

This part of the mcuxClEls driver defines the Command CRC functionality.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00718.js b/components/els_pkc/doc/mcxn/html/a00718.js new file mode 100644 index 000000000..270733db8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00718.js @@ -0,0 +1,6 @@ +var a00718 = +[ + [ "mcuxClEls_Crc_Macros", "a00719.html", "a00719" ], + [ "mcuxClEls_Crc_Types", "a00723.html", "a00723" ], + [ "mcuxClEls_Crc_Functions", "a00724.html", "a00724" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00719.html b/components/els_pkc/doc/mcxn/html/a00719.html new file mode 100644 index 000000000..2b1e6548f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00719.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Crc_Macros
mcuxClEls » mcuxClEls_Crc
+
+
+ +

Defines all macros of mcuxClEls_Crc. +More...

+ + + + + + + + + + + +

+Modules

 MCUXCLELS_CMD_CRC_
 Constants for ELS Command CRC.
 
 MCUXCLELS_CMD_CRC_REFERENCE_
 Macros for reference ELS Command CRC.
 
 MCUXCLELS_CMD_CRC_CMD_ID_
 Constants for ELS Command IDs.
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Crc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00719.js b/components/els_pkc/doc/mcxn/html/a00719.js new file mode 100644 index 000000000..0d19b1c59 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00719.js @@ -0,0 +1,6 @@ +var a00719 = +[ + [ "MCUXCLELS_CMD_CRC_", "a00720.html", "a00720" ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_", "a00721.html", "a00721" ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_", "a00722.html", "a00722" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00720.html b/components/els_pkc/doc/mcxn/html/a00720.html new file mode 100644 index 000000000..118954d41 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00720.html @@ -0,0 +1,284 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CMD_CRC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_CMD_CRC_
mcuxClEls » mcuxClEls_Crc » mcuxClEls_Crc_Macros
+
+
+ +

Constants for ELS Command CRC. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMD_CRC_VALUE_RESET
 Reset the Command CRC to initial value. More...
 
#define MCUXCLELS_CMD_CRC_VALUE_ENABLE
 Enable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_VALUE_DISABLE
 Disable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_RESET
 Reset the Command CRC to initial value. More...
 
#define MCUXCLELS_CMD_CRC_ENABLE
 Enable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_DISABLE
 Disable update of Command CRC value by executing commands. More...
 
#define MCUXCLELS_CMD_CRC_POLYNOMIAL
 CRC polynomial for the Command CRC. More...
 
#define MCUXCLELS_CMD_CRC_INITIAL_VALUE
 Initial value for the Command CRC. More...
 
+

Detailed Description

+

Constants for ELS Command CRC.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMD_CRC_VALUE_RESET

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_VALUE_RESET
+
+ +

Reset the Command CRC to initial value.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_VALUE_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_VALUE_ENABLE
+
+ +

Enable update of Command CRC value by executing commands.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_VALUE_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_VALUE_DISABLE
+
+ +

Disable update of Command CRC value by executing commands.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_RESET

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_RESET
+
+ +

Reset the Command CRC to initial value.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_ENABLE
+
+ +

Enable update of Command CRC value by executing commands.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_DISABLE
+
+ +

Disable update of Command CRC value by executing commands.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_POLYNOMIAL

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_POLYNOMIAL
+
+ +

CRC polynomial for the Command CRC.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_INITIAL_VALUE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_INITIAL_VALUE
+
+ +

Initial value for the Command CRC.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00720.js b/components/els_pkc/doc/mcxn/html/a00720.js new file mode 100644 index 000000000..ea093af00 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00720.js @@ -0,0 +1,11 @@ +var a00720 = +[ + [ "MCUXCLELS_CMD_CRC_VALUE_RESET", "a00720.html#ga4ea6f474882d3641c24d667d3e27705e", null ], + [ "MCUXCLELS_CMD_CRC_VALUE_ENABLE", "a00720.html#ga72aafc14f6c0d2d5566095da8da12836", null ], + [ "MCUXCLELS_CMD_CRC_VALUE_DISABLE", "a00720.html#ga989391a1c889ba01d0324f71e22d9cdb", null ], + [ "MCUXCLELS_CMD_CRC_RESET", "a00720.html#ga223c08e1768387247f660f6ab9b2abd0", null ], + [ "MCUXCLELS_CMD_CRC_ENABLE", "a00720.html#ga30485738143113e3a857d505076c0407", null ], + [ "MCUXCLELS_CMD_CRC_DISABLE", "a00720.html#ga7dd3297a886e126c5c8c461e962b7c1e", null ], + [ "MCUXCLELS_CMD_CRC_POLYNOMIAL", "a00720.html#ga3ae77f6de5efb615e2f9bfe25d65eac5", null ], + [ "MCUXCLELS_CMD_CRC_INITIAL_VALUE", "a00720.html#ga2c5d32e550c9abea8ccc363d1fdb4a46", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00721.html b/components/els_pkc/doc/mcxn/html/a00721.html new file mode 100644 index 000000000..513ae4680 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00721.html @@ -0,0 +1,1009 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CMD_CRC_REFERENCE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_CMD_CRC_REFERENCE_
mcuxClEls » mcuxClEls_Crc » mcuxClEls_Crc_Macros
+
+
+ +

Macros for reference ELS Command CRC. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMD_CRC_REFERENCE_INIT(crc)
 Initializes a reference CRC variable with the command CRC initial value. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_RESET(crc)
 Resets the given reference CRC variable to the command CRC initial value. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_Init_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_PartialInit_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_UpdateAad_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_UpdateData_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options)
 Updates given reference command CRC with command mcuxClEls_Aead_Finalize_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER(crc, options)
 Updates given reference command CRC with command mcuxClEls_Cipher_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC(crc, options)
 Updates given reference command CRC with command mcuxClEls_Cmac_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccKeyGen_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc)
 Updates given reference command CRC with command mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options)
 Updates given reference command CRC with command mcuxClEls_EccVerify_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG(crc)
 Updates given reference command CRC with command mcuxClEls_GlitchDetector_LoadConfig_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM(crc)
 Updates given reference command CRC with command mcuxClEls_GlitchDetector_Trim_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hash_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hmac_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108(crc)
 Updates given reference command CRC with command mcuxClEls_Ckdf_Sp800108_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869(crc, options)
 Updates given reference command CRC with command mcuxClEls_Hkdf_Rfc5869_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C(crc)
 Updates given reference command CRC with command mcuxClEls_Hkdf_Sp80056c_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY(crc)
 Updates given reference command CRC with command mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY(crc)
 Updates given reference command CRC with command mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc)
 Updates given reference command CRC with command mcuxClEls_KeyDelete_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, options)
 Updates given reference command CRC with command mcuxClEls_KeyImport_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT(crc)
 Updates given reference command CRC with command mcuxClEls_KeyExport_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgRequest_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestInstantiate_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesEcb_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesCtr_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigLoad_Async. More...
 
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE(crc)
 Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async. More...
 
+

Detailed Description

+

Macros for reference ELS Command CRC.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_INIT

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_INIT( crc)
+
+ +

Initializes a reference CRC variable with the command CRC initial value.

+

The new variable has the given name.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_RESET

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_RESET( crc)
+
+ +

Resets the given reference CRC variable to the command CRC initial value.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Aead_Init_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Aead_PartialInit_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Aead_UpdateAad_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Aead_UpdateData_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Aead_Finalize_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Cipher_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Cmac_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_EccKeyGen_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_EccKeyExchange_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_EccSign_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_EccVerify_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_GlitchDetector_LoadConfig_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_GlitchDetector_Trim_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Hash_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Hmac_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Ckdf_Sp800108_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_Hkdf_Rfc5869_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Hkdf_Sp80056c_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_KeyDelete_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT( crc,
 options 
)
+
+ +

Updates given reference command CRC with command mcuxClEls_KeyImport_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_KeyExport_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_DrbgRequest_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestInstantiate_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestExtract_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesEcb_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_DrbgTestAesCtr_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigLoad_Async.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE

+ +
+
+ + + + + + + + +
#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE( crc)
+
+ +

Updates given reference command CRC with command mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00721.js b/components/els_pkc/doc/mcxn/html/a00721.js new file mode 100644 index 000000000..9b72bbd7d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00721.js @@ -0,0 +1,35 @@ +var a00721 = +[ + [ "MCUXCLELS_CMD_CRC_REFERENCE_INIT", "a00721.html#ga2e1db01b3d5c51fd02a1e83060732e8c", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_RESET", "a00721.html#ga9ce01bd5d4ea16985fa7b85cc15f2693", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT", "a00721.html#gae6ab0207e4403dcf5c2dcfde753cf655", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT", "a00721.html#gaefec8bc08ee26c21e77b5805ce9b7e60", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD", "a00721.html#ga245c09816fabe02aaaac29346c15be21", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA", "a00721.html#ga54d72bcb4788676fa1abfddfeb0b0500", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE", "a00721.html#gada728bb209a10e78365aaa4165fb1526", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER", "a00721.html#ga1bb77cbf1f29cfac9ca2db5f7b1a0450", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC", "a00721.html#ga064eac834320f9002cbfe9981b4e416f", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN", "a00721.html#gae92dbeb4c44c99edccfe08ebce63d7e7", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE", "a00721.html#ga1e25c3e7350320526b8a46705d9eff7d", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN", "a00721.html#ga625ee41cf33f31eafc17ccc527feeb08", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY", "a00721.html#gab78f59c3466a002a40e3492054725c2c", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG", "a00721.html#ga7ad4439beeb293ebc81605aff8080f06", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM", "a00721.html#ga93bffd65f1138c80e00562ce7c37456a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH", "a00721.html#ga895449214513abfa3882c67be4cae8c1", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC", "a00721.html#gae38cd842c0f20823078a071e4efe6b91", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108", "a00721.html#ga47b490f3b6d5e627188d3130f475afbe", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869", "a00721.html#ga99f07b82231a11b71b66664e9a6cd632", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C", "a00721.html#gaf4580ba34e94564c4f608a55d120ea7b", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY", "a00721.html#gabf4ea11b932e2c372554a38d2b46af10", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY", "a00721.html#ga4767023f07bf0519f9ced9c08931b2db", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE", "a00721.html#ga78802e76c0a21709beb16b4764f395e4", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT", "a00721.html#gafda5328d88ce7cb623fbffe67f3f881a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT", "a00721.html#ga28cfed7894b7923478c183f52020ceec", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST", "a00721.html#gaa579d89877e771f69c92fbd0b3ed5752", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE", "a00721.html#ga57115088afcd2e11f0742426df26c31a", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT", "a00721.html#ga26fc4efbe3d744309300fdc73f6a507b", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB", "a00721.html#ga931581b96f1c816a9b4f09ac6d219a68", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR", "a00721.html#ga1aa20023a8871dcf226865cfdc4846b8", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD", "a00721.html#gaabeccb19cfd99a1a83954d7676e792b4", null ], + [ "MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE", "a00721.html#ga1fef6315409433815a4e64abfb23159f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00722.html b/components/els_pkc/doc/mcxn/html/a00722.html new file mode 100644 index 000000000..62c09ea43 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00722.html @@ -0,0 +1,569 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_CMD_CRC_CMD_ID_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_CMD_CRC_CMD_ID_
mcuxClEls » mcuxClEls_Crc » mcuxClEls_Crc_Macros
+
+
+ +

Constants for ELS Command IDs. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER
 ELS Command ID for CIPHER command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER
 ELS Command ID for AUTH_CIPHER command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
 ELS Command ID for CHAL_RESP_GEN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN
 ELS Command ID for ECSIGN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY
 ELS Command ID for ECVFY command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH
 ELS Command ID for ECKXH command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN
 ELS Command ID for KEYGEN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN
 ELS Command ID for KEYIN command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT
 ELS Command ID for KEYOUT command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE
 ELS Command ID for KDELETE command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV
 ELS Command ID for KEYPROV command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CKDF
 ELS Command ID for CKDF command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HKDF
 ELS Command ID for HKDF command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_TLS
 ELS Command ID for TLS command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HASH
 ELS Command ID for HASH command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_HMAC
 ELS Command ID for HMAC command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_CMAC
 ELS Command ID for CMAC command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ
 ELS Command ID for RND_REQ command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST
 ELS Command ID for DRBG_TEST command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
 ELS Command ID for DTRNG_CFG_LOAD command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL
 ELS Command ID for DTRNG_EVAL command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
 ELS Command ID for GDET_CFG_LOAD command. More...
 
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM
 ELS Command ID for GDET_TRIM command. More...
 
+

Detailed Description

+

Constants for ELS Command IDs.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_CIPHER

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER
+
+ +

ELS Command ID for CIPHER command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER
+
+ +

ELS Command ID for AUTH_CIPHER command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN
+
+ +

ELS Command ID for CHAL_RESP_GEN command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN
+
+ +

ELS Command ID for ECSIGN command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_ECVFY

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY
+
+ +

ELS Command ID for ECVFY command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_ECKXH

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH
+
+ +

ELS Command ID for ECKXH command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN
+
+ +

ELS Command ID for KEYGEN command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_KEYIN

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN
+
+ +

ELS Command ID for KEYIN command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT
+
+ +

ELS Command ID for KEYOUT command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_KDELETE

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE
+
+ +

ELS Command ID for KDELETE command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV
+
+ +

ELS Command ID for KEYPROV command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_CKDF

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_CKDF
+
+ +

ELS Command ID for CKDF command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_HKDF

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_HKDF
+
+ +

ELS Command ID for HKDF command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_TLS

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_TLS
+
+ +

ELS Command ID for TLS command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_HASH

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_HASH
+
+ +

ELS Command ID for HASH command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_HMAC

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_HMAC
+
+ +

ELS Command ID for HMAC command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_CMAC

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_CMAC
+
+ +

ELS Command ID for CMAC command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ
+
+ +

ELS Command ID for RND_REQ command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST
+
+ +

ELS Command ID for DRBG_TEST command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD
+
+ +

ELS Command ID for DTRNG_CFG_LOAD command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL
+
+ +

ELS Command ID for DTRNG_EVAL command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD
+
+ +

ELS Command ID for GDET_CFG_LOAD command.

+ +
+
+ +

◆ MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM

+ +
+
+ + + + +
#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM
+
+ +

ELS Command ID for GDET_TRIM command.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00722.js b/components/els_pkc/doc/mcxn/html/a00722.js new file mode 100644 index 000000000..8a9f270f4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00722.js @@ -0,0 +1,26 @@ +var a00722 = +[ + [ "MCUXCLELS_CMD_CRC_CMD_ID_CIPHER", "a00722.html#ga2a3c7f74fe04bdbcce0856868ecf44ad", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER", "a00722.html#ga409e1dae95e89fd8ffb127c4f7ed88d2", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN", "a00722.html#ga2fdefdf18f7cb37b74ef2f49daeb7549", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN", "a00722.html#gaeb55615316d2f67abc77976c752a4533", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECVFY", "a00722.html#ga7cd6375c813a4de7d0ec9c9d4209c03a", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_ECKXH", "a00722.html#ga04f3aa01819a18d5dbcedd795fddbc81", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN", "a00722.html#ga303a52799f5c842e761ae2c8527fb2f3", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYIN", "a00722.html#ga0d49dc33b50bd7db6ca58cb84db936e3", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT", "a00722.html#ga2fccccaeea8e4fb0e31bfa368caf39f7", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KDELETE", "a00722.html#gaf9eadae3c47cdd4df67b150f91d6b30b", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV", "a00722.html#gabaa8a08498f70bcccea59ee5472fe942", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CKDF", "a00722.html#gacc64012f05a991897dc401f526fcc78b", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HKDF", "a00722.html#ga3945648ed569844869fd7eb997e99df9", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_TLS", "a00722.html#gad86358f79337962338035ed5c49cb7ac", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HASH", "a00722.html#ga56f581e908a8889c11d0b916b6d69657", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_HMAC", "a00722.html#gab2cc703ff096c3b830019510855001a6", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_CMAC", "a00722.html#ga9716ab821ee894a4cd64d0553311da2a", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ", "a00722.html#ga72ff352c60a48b971c0ac0a772180fee", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST", "a00722.html#ga4852767cbb713b107cf8e261fdbe5c17", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD", "a00722.html#ga33f246b5a6c663fd854726fbde6b260d", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL", "a00722.html#gaac8b6cfd8f9bf0bea117371edc80b974", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD", "a00722.html#ga1dfda813fd0917ff50688736159435db", null ], + [ "MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM", "a00722.html#gab752a820b7f5957518912f67576f3ea8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00723.html b/components/els_pkc/doc/mcxn/html/a00723.html new file mode 100644 index 000000000..45cc23e39 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00723.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Crc_Types
mcuxClEls » mcuxClEls_Crc
+
+
+ +

Defines all types of mcuxClEls_Crc. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_CommandCrcConfig_t
 Type to control ELS Command CRC. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Crc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00723.js b/components/els_pkc/doc/mcxn/html/a00723.js new file mode 100644 index 000000000..48c2385be --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00723.js @@ -0,0 +1,11 @@ +var a00723 = +[ + [ "mcuxClEls_CommandCrcConfig_t", "a01105.html", [ + [ "value", "a01105.html#a4dc44ca29e9ef4bcea0b6469a5966f6d", null ], + [ "word", "a01105.html#aa9b1c3ce855f539fb39a251dc5fe0744", null ], + [ "reset", "a01105.html#ae72c778e615b7e6aa4e73eb242beb354", null ], + [ "enable", "a01105.html#a60c0c05eb7acf852589b6f5b7a7c9dd3", null ], + [ "__pad0__", "a01105.html#a49e0d7b8ada89de5bd766ac9cf2c3e27", null ], + [ "bits", "a01105.html#ac18d751428d40b3e3127a0779abc1cec", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00724.html b/components/els_pkc/doc/mcxn/html/a00724.html new file mode 100644 index 000000000..b9f9adaea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00724.html @@ -0,0 +1,285 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Crc_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Crc_Functions
mcuxClEls » mcuxClEls_Crc
+
+
+ +

Defines all functions of mcuxClEls_Crc. +More...

+ + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ConfigureCommandCRC (mcuxClEls_CommandCrcConfig_t options)
 Set command CRC flags. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetCommandCRC (uint32_t *commandCrc)
 Get the current command CRC value. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_VerifyVsRefCRC (uint32_t refCrc)
 Verifies a reference CRC against the computed ELS command CRC. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_UpdateRefCRC (uint8_t command, uint32_t options, uint32_t *refCrc)
 Updates a reference CRC with the parameters of an ELS command. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Crc.

+

Function Documentation

+ +

◆ mcuxClEls_ConfigureCommandCRC()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_ConfigureCommandCRC (mcuxClEls_CommandCrcConfig_t options)
+
+ +

Set command CRC flags.

+
Parameters
+ + +
[in]optionsThe command CRC options. For more information, see mcuxClEls_CommandCrcConfig_t.
+
+
+
Returns
An error code that is always MCUXCLELS_STATUS_OK
+ +
+
+ +

◆ mcuxClEls_GetCommandCRC()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetCommandCRC (uint32_t * commandCrc)
+
+ +

Get the current command CRC value.

+
Parameters
+ + +
[out]commandCrcThe command CRC value.
+
+
+
Returns
An error code
+
Return values
+ + + +
MCUXCLELS_STATUS_OKOperation successful
MCUXCLELS_STATUS_SW_INVALID_PARAMParameter commandCRC points to NULL
+
+
+ +
+
+ +

◆ mcuxClEls_VerifyVsRefCRC()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_VerifyVsRefCRC (uint32_t refCrc)
+
+ +

Verifies a reference CRC against the computed ELS command CRC.

+
Parameters
+ + +
[in]refCrcThe reference CRC value.
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+ +
+
+ +

◆ mcuxClEls_UpdateRefCRC()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_UpdateRefCRC (uint8_t command,
uint32_t options,
uint32_t * refCrc 
)
+
+ +

Updates a reference CRC with the parameters of an ELS command.

+

This can be used to verify against the ELS command CRC.

+
Parameters
+ + + + +
[in]commandThe ELS command ID.
[in]optionsThe command options for the given ELS command.
[in,out]refCrcThe current reference CRC value to update.
+
+
+
Returns
An error code
+
Return values
+ + + +
MCUXCLELS_STATUS_OKOperation successful
MCUXCLELS_STATUS_SW_INVALID_PARAMParameter crc points to NULL
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00724.js b/components/els_pkc/doc/mcxn/html/a00724.js new file mode 100644 index 000000000..d2e640442 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00724.js @@ -0,0 +1,7 @@ +var a00724 = +[ + [ "mcuxClEls_ConfigureCommandCRC", "a00724.html#ga4aaabd203c6c81a042bc4f3739ae8408", null ], + [ "mcuxClEls_GetCommandCRC", "a00724.html#gaf91caa2b1230676e9beedaa0eba442eb", null ], + [ "mcuxClEls_VerifyVsRefCRC", "a00724.html#ga5ebf64e6470c7a08c56ee44d9afe3990", null ], + [ "mcuxClEls_UpdateRefCRC", "a00724.html#gae04ed3290d9cb48f42f4f9aed4b1a825", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00725.html b/components/els_pkc/doc/mcxn/html/a00725.html new file mode 100644 index 000000000..4e656cdd0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00725.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Ecc
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for elliptic curve cryptography. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Ecc_Macros
 Defines all macros of mcuxClEls_Ecc.
 
 mcuxClEls_Ecc_Types
 Defines all types of mcuxClEls_Ecc.
 
 mcuxClEls_Ecc_Functions
 Defines all functions of mcuxClEls_Ecc.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for elliptic curve cryptography.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00725.js b/components/els_pkc/doc/mcxn/html/a00725.js new file mode 100644 index 000000000..d31abc686 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00725.js @@ -0,0 +1,6 @@ +var a00725 = +[ + [ "mcuxClEls_Ecc_Macros", "a00726.html", "a00726" ], + [ "mcuxClEls_Ecc_Types", "a00733.html", "a00733" ], + [ "mcuxClEls_Ecc_Functions", "a00734.html", "a00734" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00726.html b/components/els_pkc/doc/mcxn/html/a00726.html new file mode 100644 index 000000000..3b4e850a0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00726.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Ecc_Macros
mcuxClEls » mcuxClEls_Ecc
+
+
+ +

Defines all macros of mcuxClEls_Ecc. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Modules

 MCUXCLELS_ECC (Sign and Verify) option word values
 Constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t.
 
 MCUXCLELS_KEYGEN option word values
 Constants for mcuxClEls_EccKeyGenOption_t.
 
 MCUXCLELS_ECC (Sign and Verify) option bit field values
 Bit field constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t.
 
 MCUXCLELS_KEYGEN option bit field values
 Bit field constants for mcuxClEls_EccKeyGenOption_t.
 
 Option bit field values that are needed for internal use only
 Internal bit field constants for several option types.
 
 MCUXCLELS_ECC_SIZE
 Defines size of public key and signature in bytes.
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Ecc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00726.js b/components/els_pkc/doc/mcxn/html/a00726.js new file mode 100644 index 000000000..84b91f21d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00726.js @@ -0,0 +1,9 @@ +var a00726 = +[ + [ "MCUXCLELS_ECC (Sign and Verify) option word values", "a00727.html", "a00727" ], + [ "MCUXCLELS_KEYGEN option word values", "a00728.html", "a00728" ], + [ "MCUXCLELS_ECC (Sign and Verify) option bit field values", "a00729.html", "a00729" ], + [ "MCUXCLELS_KEYGEN option bit field values", "a00730.html", "a00730" ], + [ "Option bit field values that are needed for internal use only", "a00731.html", "a00731" ], + [ "MCUXCLELS_ECC_SIZE", "a00732.html", "a00732" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00727.html b/components/els_pkc/doc/mcxn/html/a00727.html new file mode 100644 index 000000000..0f2f6f995 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00727.html @@ -0,0 +1,208 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_ECC (Sign and Verify) option word values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_ECC (Sign and Verify) option word values
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_ECC_VALUE_HASHED
 Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the hash of the message. More...
 
#define MCUXCLELS_ECC_VALUE_NOT_HASHED
 Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the plain message. More...
 
#define MCUXCLELS_ECC_VALUE_RTF
 Set this option at mcuxClEls_EccSignOption_t.value to include the RTF in the signature, only for mcuxClEls_EccSignOption_t. More...
 
#define MCUXCLELS_ECC_VALUE_NO_RTF
 Set this option at mcuxClEls_EccSignOption_t.value to not include the RTF in the signature, only for mcuxClEls_EccSignOption_t. More...
 
+

Detailed Description

+

Constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ECC_VALUE_HASHED

+ +
+
+ + + + +
#define MCUXCLELS_ECC_VALUE_HASHED
+
+ +

Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the hash of the message.

+ +
+
+ +

◆ MCUXCLELS_ECC_VALUE_NOT_HASHED

+ +
+
+ + + + +
#define MCUXCLELS_ECC_VALUE_NOT_HASHED
+
+ +

Set this option at mcuxClEls_EccSignOption_t.value or mcuxClEls_EccVerifyOption_t.value to specify input is the plain message.

+ +
+
+ +

◆ MCUXCLELS_ECC_VALUE_RTF

+ +
+
+ + + + +
#define MCUXCLELS_ECC_VALUE_RTF
+
+ +

Set this option at mcuxClEls_EccSignOption_t.value to include the RTF in the signature, only for mcuxClEls_EccSignOption_t.

+ +
+
+ +

◆ MCUXCLELS_ECC_VALUE_NO_RTF

+ +
+
+ + + + +
#define MCUXCLELS_ECC_VALUE_NO_RTF
+
+ +

Set this option at mcuxClEls_EccSignOption_t.value to not include the RTF in the signature, only for mcuxClEls_EccSignOption_t.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00727.js b/components/els_pkc/doc/mcxn/html/a00727.js new file mode 100644 index 000000000..745a6724a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00727.js @@ -0,0 +1,7 @@ +var a00727 = +[ + [ "MCUXCLELS_ECC_VALUE_HASHED", "a00727.html#gac3be2289b4247767251a8d85014652bb", null ], + [ "MCUXCLELS_ECC_VALUE_NOT_HASHED", "a00727.html#ga90e38c2c9caeb976594c32d92bbc5d05", null ], + [ "MCUXCLELS_ECC_VALUE_RTF", "a00727.html#ga48a69913a0b9d082ea72b81f56ac1fdc", null ], + [ "MCUXCLELS_ECC_VALUE_NO_RTF", "a00727.html#ga66a8fbee1f549d2ad1819c0e08780e13", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00728.html b/components/els_pkc/doc/mcxn/html/a00728.html new file mode 100644 index 000000000..5717350f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00728.html @@ -0,0 +1,303 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYGEN option word values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_KEYGEN option word values
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Constants for mcuxClEls_EccKeyGenOption_t. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to sign the public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a signing key usable by mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is deterministic. More...
 
#define MCUXCLELS_KEYGEN_VALUE_RANDOM
 Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is random. More...
 
#define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to generate a public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.value to not generate a public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.value to not use random data for signing the public key. More...
 
#define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.value to use random data for signing the public key. More...
 
+

Detailed Description

+

Constants for mcuxClEls_EccKeyGenOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to sign the public key.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a signing key usable by mcuxClEls_EccSign_Async.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is deterministic.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_RANDOM

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_RANDOM
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to specify output key is random.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to generate a public key.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to not generate a public key.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to not use random data for signing the public key.

+ +
+
+ +

◆ MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA

+ +
+
+ + + + +
#define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.value to use random data for signing the public key.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00728.js b/components/els_pkc/doc/mcxn/html/a00728.js new file mode 100644 index 000000000..ca8eb308e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00728.js @@ -0,0 +1,12 @@ +var a00728 = +[ + [ "MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY", "a00728.html#ga916703c91887cb429f5fc3c9f3f039c9", null ], + [ "MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN", "a00728.html#ga7bf099956f1b0d5e9b24a654023f28b7", null ], + [ "MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE", "a00728.html#ga9263040a043abb0bfaf51fb16ba270e5", null ], + [ "MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC", "a00728.html#gabbd15e28f3e551acbc9b786a52bfd238", null ], + [ "MCUXCLELS_KEYGEN_VALUE_RANDOM", "a00728.html#ga8bc95eb09238ba6e3716109472fe6c86", null ], + [ "MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY", "a00728.html#ga4a2e708b9f9c46037356e2f4c6ab662b", null ], + [ "MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY", "a00728.html#gaa98c6e65867abd8ae959c9771eefcbe6", null ], + [ "MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA", "a00728.html#ga73dea3b73d48e7b74ba484bb8278e110", null ], + [ "MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA", "a00728.html#gaf9df52529671dea7267c60318bcfc3ec", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00729.html b/components/els_pkc/doc/mcxn/html/a00729.html new file mode 100644 index 000000000..b343cf8ed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00729.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_ECC (Sign and Verify) option bit field values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_ECC (Sign and Verify) option bit field values
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Bit field constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_ECC_HASHED
 Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the hash of the message. More...
 
#define MCUXCLELS_ECC_NOT_HASHED
 Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the plain message. More...
 
#define MCUXCLELS_ECC_RTF
 Set this option at mcuxClEls_EccSignOption_t.signrtf to include the RTF in the signature. More...
 
#define MCUXCLELS_ECC_NO_RTF
 Set this option at mcuxClEls_EccSignOption_t.signrtf to not include the RTF in the signature. More...
 
+

Detailed Description

+

Bit field constants for mcuxClEls_EccSignOption_t and mcuxClEls_EccVerifyOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ECC_HASHED

+ +
+
+ + + + +
#define MCUXCLELS_ECC_HASHED
+
+ +

Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the hash of the message.

+ +
+
+ +

◆ MCUXCLELS_ECC_NOT_HASHED

+ +
+
+ + + + +
#define MCUXCLELS_ECC_NOT_HASHED
+
+ +

Set this option at mcuxClEls_EccSignOption_t.echashchl or mcuxClEls_EccVerifyOption_t.echashchl to specify input is the plain message.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_RTF

+ +
+
+ + + + +
#define MCUXCLELS_ECC_RTF
+
+ +

Set this option at mcuxClEls_EccSignOption_t.signrtf to include the RTF in the signature.

+ +
+
+ +

◆ MCUXCLELS_ECC_NO_RTF

+ +
+
+ + + + +
#define MCUXCLELS_ECC_NO_RTF
+
+ +

Set this option at mcuxClEls_EccSignOption_t.signrtf to not include the RTF in the signature.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00729.js b/components/els_pkc/doc/mcxn/html/a00729.js new file mode 100644 index 000000000..1fa48122b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00729.js @@ -0,0 +1,7 @@ +var a00729 = +[ + [ "MCUXCLELS_ECC_HASHED", "a00729.html#gafad38c505a64137b0283ad96c144c503", null ], + [ "MCUXCLELS_ECC_NOT_HASHED", "a00729.html#ga871f176b3998d9b5dd709d5a6e2585bd", null ], + [ "MCUXCLELS_ECC_RTF", "a00729.html#ga04c77ad43887a66b1b8df87cb9258981", null ], + [ "MCUXCLELS_ECC_NO_RTF", "a00729.html#gae7ffc3999117e1796727bd7700d88745", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00730.html b/components/els_pkc/doc/mcxn/html/a00730.html new file mode 100644 index 000000000..0de962d2e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00730.html @@ -0,0 +1,334 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYGEN option bit field values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_KEYGEN option bit field values
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Bit field constants for mcuxClEls_EccKeyGenOption_t. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to sign the public key (signature will be concatenated to the output public key) More...
 
#define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to not sign the public key. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_SIGN
 Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a signing key usable by mcuxClEls_EccSign_Async. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE
 Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is deterministic. More...
 
#define MCUXCLELS_ECC_OUTPUTKEY_RANDOM
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is random. More...
 
#define MCUXCLELS_ECC_GEN_PUBLIC_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to generate a public key. More...
 
#define MCUXCLELS_ECC_SKIP_PUBLIC_KEY
 Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to not generate a public key. More...
 
#define MCUXCLELS_ECC_NO_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to not include user provided random data for the signature. More...
 
#define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA
 Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to include user provided random data for the signature. More...
 
+

Detailed Description

+

Bit field constants for mcuxClEls_EccKeyGenOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to sign the public key (signature will be concatenated to the output public key)

+ +
+
+ +

◆ MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsign to not sign the public key.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_OUTPUTKEY_SIGN

+ +
+
+ + + + +
#define MCUXCLELS_ECC_OUTPUTKEY_SIGN
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a signing key usable by mcuxClEls_EccSign_Async.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a Diffie Helman key usable by mcuxClEls_EccKeyExchange_Async.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC

+ +
+
+ + + + +
#define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is deterministic.

+ +
+
+ +

◆ MCUXCLELS_ECC_OUTPUTKEY_RANDOM

+ +
+
+ + + + +
#define MCUXCLELS_ECC_OUTPUTKEY_RANDOM
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is random.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_GEN_PUBLIC_KEY

+ +
+
+ + + + +
#define MCUXCLELS_ECC_GEN_PUBLIC_KEY
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to generate a public key.

+ +
+
+ +

◆ MCUXCLELS_ECC_SKIP_PUBLIC_KEY

+ +
+
+ + + + +
#define MCUXCLELS_ECC_SKIP_PUBLIC_KEY
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.skip_pbk to not generate a public key.

+

If MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE set, this option will be ignored and a public key will be generated.

+ +
+
+ +

◆ MCUXCLELS_ECC_NO_RANDOM_DATA

+ +
+
+ + + + +
#define MCUXCLELS_ECC_NO_RANDOM_DATA
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to not include user provided random data for the signature.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_INCLUDE_RANDOM_DATA

+ +
+
+ + + + +
#define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA
+
+ +

Set this option at mcuxClEls_EccKeyGenOption_t.kgsign_rnd to include user provided random data for the signature.

+

MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE must be set in this case.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00730.js b/components/els_pkc/doc/mcxn/html/a00730.js new file mode 100644 index 000000000..bf1b017d5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00730.js @@ -0,0 +1,13 @@ +var a00730 = +[ + [ "MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE", "a00730.html#ga9b6bd96ac94ff7bd763b9b9d057d139f", null ], + [ "MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE", "a00730.html#gaf73a03883462465c3cabb2257981fc5f", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_SIGN", "a00730.html#gacff4169a4b48ee6c6e8ac13e2ea025ab", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE", "a00730.html#gabc39d5811bcaba4278e1f9c4874527ae", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC", "a00730.html#ga8cdc8f5c722207aaef7fef9fd0cc3837", null ], + [ "MCUXCLELS_ECC_OUTPUTKEY_RANDOM", "a00730.html#ga67348b1833c0bfaccbe334c2cb68b448", null ], + [ "MCUXCLELS_ECC_GEN_PUBLIC_KEY", "a00730.html#gac67abe2d5052f753cc5f5aca24663066", null ], + [ "MCUXCLELS_ECC_SKIP_PUBLIC_KEY", "a00730.html#gacbb5ce65a2ad59ec7a6709059f94426f", null ], + [ "MCUXCLELS_ECC_NO_RANDOM_DATA", "a00730.html#ga10f155f1020130f0b9c952f6df52c784", null ], + [ "MCUXCLELS_ECC_INCLUDE_RANDOM_DATA", "a00730.html#gadcb581867b97e3c3988125eddc5f24e3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00731.html b/components/els_pkc/doc/mcxn/html/a00731.html new file mode 100644 index 000000000..614d245d6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00731.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: Option bit field values that are needed for internal use only + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Option bit field values that are needed for internal use only
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Internal bit field constants for several option types. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_ECC_REVERSEFETCH_ENABLE
 Reverse Fetch enabled. For internal use. More...
 
#define MCUXCLELS_ECC_REVERSEFETCH_DISABLE
 Reverse Fetch disabled. For internal use. More...
 
+

Detailed Description

+

Internal bit field constants for several option types.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ECC_REVERSEFETCH_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_REVERSEFETCH_ENABLE
+
+ +

Reverse Fetch enabled. For internal use.

+ +
+
+ +

◆ MCUXCLELS_ECC_REVERSEFETCH_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_REVERSEFETCH_DISABLE
+
+ +

Reverse Fetch disabled. For internal use.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00731.js b/components/els_pkc/doc/mcxn/html/a00731.js new file mode 100644 index 000000000..094f6f97d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00731.js @@ -0,0 +1,5 @@ +var a00731 = +[ + [ "MCUXCLELS_ECC_REVERSEFETCH_ENABLE", "a00731.html#ga0536723a417500b946e92b6432d0a4fd", null ], + [ "MCUXCLELS_ECC_REVERSEFETCH_DISABLE", "a00731.html#ga92e6bbdd8cdd2d0ed90e6073e94924df", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00732.html b/components/els_pkc/doc/mcxn/html/a00732.html new file mode 100644 index 000000000..557e48bfa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00732.html @@ -0,0 +1,195 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_ECC_SIZE + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_ECC_SIZE
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Macros
+
+
+ +

Defines size of public key and signature in bytes. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCLELS_ECC_PUBLICKEY_SIZE
 Size of the public key. More...
 
#define MCUXCLELS_ECC_SIGNATURE_SIZE
 Size of the signature. More...
 
#define MCUXCLELS_ECC_SIGNATURE_R_SIZE
 Size of the signature part r. More...
 
+

Detailed Description

+

Defines size of public key and signature in bytes.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_ECC_PUBLICKEY_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_PUBLICKEY_SIZE
+
+ +

Size of the public key.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_SIGNATURE_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_SIGNATURE_SIZE
+
+ +

Size of the signature.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_ECC_SIGNATURE_R_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_ECC_SIGNATURE_R_SIZE
+
+ +

Size of the signature part r.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00732.js b/components/els_pkc/doc/mcxn/html/a00732.js new file mode 100644 index 000000000..61dcf8efa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00732.js @@ -0,0 +1,6 @@ +var a00732 = +[ + [ "MCUXCLELS_ECC_PUBLICKEY_SIZE", "a00732.html#ga7298491d4e2d679496d0bacab6f351f8", null ], + [ "MCUXCLELS_ECC_SIGNATURE_SIZE", "a00732.html#ga922fa06cbacda443d50f2b3c29fdea8c", null ], + [ "MCUXCLELS_ECC_SIGNATURE_R_SIZE", "a00732.html#ga18a35b4e98dac7862895339b720d667a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00733.html b/components/els_pkc/doc/mcxn/html/a00733.html new file mode 100644 index 000000000..173e642e0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00733.html @@ -0,0 +1,168 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs
+
+
mcuxClEls_Ecc_Types
mcuxClEls » mcuxClEls_Ecc
+
+
+ +

Defines all types of mcuxClEls_Ecc. +More...

+ + + + + + + + + + + + + + +

+Data Structures

union  mcuxClEls_EccSignOption_t
 Command option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async. More...
 
union  mcuxClEls_EccVerifyOption_t
 Command option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOption_t. More...
 
union  mcuxClEls_EccKeyGenOption_t
 Command option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOption_t. More...
 
union  mcuxClEls_EccKeyExchOption_t
 Command option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only. More...
 
+ + + + +

+Typedefs

typedef uint8_t mcuxClEls_EccByte_t
 Data type for ECC parameters in ELS format. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Ecc.

+

Typedef Documentation

+ +

◆ mcuxClEls_EccByte_t

+ +
+
+ + + + +
typedef uint8_t mcuxClEls_EccByte_t
+
+ +

Data type for ECC parameters in ELS format.

+

This type will be removed soon.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00733.js b/components/els_pkc/doc/mcxn/html/a00733.js new file mode 100644 index 000000000..678e5915e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00733.js @@ -0,0 +1,45 @@ +var a00733 = +[ + [ "mcuxClEls_EccSignOption_t", "a01117.html", [ + [ "value", "a01117.html#a7e32d20de26a1ca2d7eee8fe2fd95456", null ], + [ "word", "a01117.html#a6f703afe07655c05795fd6061b321dc3", null ], + [ "echashchl", "a01117.html#ab825e88899ff7627304d25fbcc1adffd", null ], + [ "signrtf", "a01117.html#aa4bcc3f1aaf9e991e62cdc22ffd7500e", null ], + [ "__pad0__", "a01117.html#a0e9a4b194d887a2b2c4c2297c2cbd868", null ], + [ "revf", "a01117.html#aa75bf5c0b29ee02a16ca1b31e3300b0f", null ], + [ "__pad1__", "a01117.html#a5527caf737b06f5053f89c60354dbe65", null ], + [ "bits", "a01117.html#accf6312c26ce770b5647c4e45b00f7b5", null ] + ] ], + [ "mcuxClEls_EccVerifyOption_t", "a01129.html", [ + [ "value", "a01129.html#a73b0b8e42d753a97bb03cb053799e33a", null ], + [ "word", "a01129.html#a1d1416b8e584c34840183572e7b2df3d", null ], + [ "echashchl", "a01129.html#a2642a5936ec9f5c7394704161c984598", null ], + [ "__pad0__", "a01129.html#a7dffb127ef2f32236227c9023af7e5cd", null ], + [ "revf", "a01129.html#afbf76f7ebcfc43ca99708cd1064a651a", null ], + [ "__pad1__", "a01129.html#ad2bdfda87da142b43bfd1e64ee8bb072", null ], + [ "bits", "a01129.html#aa5f2cce580390956b07603eb64fe6fc7", null ] + ] ], + [ "mcuxClEls_EccKeyGenOption_t", "a01141.html", [ + [ "value", "a01141.html#a2c377cdae550923ee7e1234735e08b40", null ], + [ "word", "a01141.html#ab5dac27ccbb4062c42c971d44e504519", null ], + [ "kgsign", "a01141.html#aa20a2dd1242cfa9c945d09332db760e1", null ], + [ "kgtypedh", "a01141.html#ade3f3190f07c3a1b8a5948988d3b85d5", null ], + [ "kgsrc", "a01141.html#aa60e98c0d7570daa80ab5536ebf71d94", null ], + [ "skip_pbk", "a01141.html#afa4cb29e6c55e30a30185180de2f8e49", null ], + [ "revf", "a01141.html#a7e2c0f35b5f6904c1a232f3552cb185f", null ], + [ "kgsign_rnd", "a01141.html#ab2d02455b74fc4f2999c8b579bd87c8d", null ], + [ "__pad0__", "a01141.html#ab6d97c184d6c34f0d6c1bc8e0a77057c", null ], + [ "bits", "a01141.html#afc19db0547800dd35ed3d3294831344b", null ] + ] ], + [ "mcuxClEls_EccKeyExchOption_t", "a01153.html", [ + [ "value", "a01153.html#aaa4e256f25f9c74123c28c5926d21ba2", null ], + [ "word", "a01153.html#a17969e2f10fec362e68869232cb1099b", null ], + [ "__pad0__", "a01153.html#a98a12e39b9f189c172f6b951c2ae781c", null ], + [ "revf", "a01153.html#a2a46aaff0c4f6f2cfa19b302ba713b43", null ], + [ "__pad1__", "a01153.html#a06d0377a60794946f8788a7fad8af177", null ], + [ "extkey", "a01153.html#ab28493ba971ceb64a4fa0f741e98358d", null ], + [ "__pad2__", "a01153.html#a82f1e57ea7fcdfd607a3954396e6ec84", null ], + [ "bits", "a01153.html#aa620a69ff6945f317f2df59bdf4284cd", null ] + ] ], + [ "mcuxClEls_EccByte_t", "a00733.html#gaaca57cf87336b1e866852443c47a019f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00734.html b/components/els_pkc/doc/mcxn/html/a00734.html new file mode 100644 index 000000000..6ef901810 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00734.html @@ -0,0 +1,492 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc_Functions + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Functions
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+
mcuxClEls_Ecc_Functions
mcuxClEls » mcuxClEls_Ecc
+
+
+ +

Defines all functions of mcuxClEls_Ecc. +More...

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+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyGen_Async (mcuxClEls_EccKeyGenOption_t options, mcuxClEls_KeyIndex_t signingKeyIdx, mcuxClEls_KeyIndex_t privateKeyIdx, mcuxClEls_KeyProp_t generatedKeyProperties, uint8_t const *pRandomData, uint8_t *pPublicKey)
 Generates an ECC key pair on the NIST P-256 curve. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyExchange_Async (mcuxClEls_KeyIndex_t privateKeyIdx, uint8_t const *pPublicKey, mcuxClEls_KeyIndex_t sharedSecretIdx, mcuxClEls_KeyProp_t sharedSecretProperties)
 Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public key. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccSign_Async (mcuxClEls_EccSignOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t *pOutput)
 Generates an ECDSA signature of a given message. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccVerify_Async (mcuxClEls_EccVerifyOption_t options, uint8_t const *pInputHash, uint8_t const *pInputMessage, size_t inputMessageLength, uint8_t const *pSignatureAndPubKey, uint8_t *pOutput)
 Verifies an ECDSA signature of a given message. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Ecc.

+

Function Documentation

+ +

◆ mcuxClEls_EccKeyGen_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyGen_Async (mcuxClEls_EccKeyGenOption_t options,
mcuxClEls_KeyIndex_t signingKeyIdx,
mcuxClEls_KeyIndex_t privateKeyIdx,
mcuxClEls_KeyProp_t generatedKeyProperties,
uint8_t const * pRandomData,
uint8_t * pPublicKey 
)
+
+ +

Generates an ECC key pair on the NIST P-256 curve.

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

Call mcuxClEls_WaitForOperation to complete the operation. The public key will be stored in the standard ANSI X9.62 byte order (big-endian).

+
Parameters
+ + + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_EccKeyGenOption_t.
[in]signingKeyIdxThe index of the key to sign the generated public key.
[in]privateKeyIdxOutput key index.
[in]generatedKeyPropertiesThe desired key properties of the generated key.
[in]pRandomDataRandom data provided by the user.
[out]pPublicKeyPointer to the memory area which receives the public key and optionally the key signature.
+
+
+
+
Parameter properties
+
+
options.kgsign == MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
+
signingKeyIdx is ignored.
+
options.kgsrc == MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
+
privateKeyIdx also defines the key index of the source key material. The source key material will be overwritten by the output public key.
+
options.kgsign_rnd == MCUXCLELS_ECC_NO_RANDOM_DATA
+
pRandomData is ignored.
+
pPublicKey must be aligned on a 4-byte boundary.
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+
+
+
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ mcuxClEls_EccKeyExchange_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccKeyExchange_Async (mcuxClEls_KeyIndex_t privateKeyIdx,
uint8_t const * pPublicKey,
mcuxClEls_KeyIndex_t sharedSecretIdx,
mcuxClEls_KeyProp_t sharedSecretProperties 
)
+
+ +

Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public key.

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

Call mcuxClEls_WaitForOperation to complete the operation. The public key must be stored in the standard ANSI X9.62 byte order (big-endian).

+
Parameters
+ + + + + +
[in]privateKeyIdxThe private key index.
[in]pPublicKeyPointer to the public key of a third party.
[in]sharedSecretIdxThe index in the ELS keystore that receives the shared secret that is generated by the ECDH operation.
[in]sharedSecretPropertiesThe desired key properties of the shared secret.
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+
Parameter properties
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pPublicKey
+
The public key consists of the 256-bit X coordinate and the 256-bit Y coordinate. The point must lie on the NIST P-256 curve, be encoded in X9.62 format and aligned on a 4-byte boundary.
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+
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+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
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+ +
+
+ +

◆ mcuxClEls_EccSign_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccSign_Async (mcuxClEls_EccSignOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pInputHash,
uint8_t const * pInputMessage,
size_t inputMessageLength,
uint8_t * pOutput 
)
+
+ +

Generates an ECDSA signature of a given message.

+

The curve is NIST P-256. The message hash, must be stored in the standard ANSI X9.62 format. If the message is provided in plain, no prior conversion is necessary. The signature will be stored in the standard ANSI X9.62 byte order (big-endian).

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_EccSignOption_t.
[in]keyIdxThe private key index.
[in]pInputHashThe hash of the message to sign in X9.62 format.
[in]pInputMessageThe message to sign.
[in]inputMessageLengthSize of pInputMessage in bytes.
[out]pOutputPointer to the memory area which receives the generated signature in X9.62 format. (64 bytes)
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+
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Parameter properties
+
+
options.echashchl == MCUXCLELS_ECC_HASHED
+
pInputHash is used, and it must be aligned on a 4-byte boundary. pInputMessage is ignored.
+
options.echashchl == MCUXCLELS_ECC_NOT_HASHED
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pInputHash is ignored. pInputMessage and inputMessageLength are used.
+
pOptput must be aligned on a 4-byte boundary.
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
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+
+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
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+ +

◆ mcuxClEls_EccVerify_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_EccVerify_Async (mcuxClEls_EccVerifyOption_t options,
uint8_t const * pInputHash,
uint8_t const * pInputMessage,
size_t inputMessageLength,
uint8_t const * pSignatureAndPubKey,
uint8_t * pOutput 
)
+
+ +

Verifies an ECDSA signature of a given message.

+

The curve is NIST P-256. The message hash, must be stored in the standard ANSI X9.62 format. If the message is provided in plain, no prior conversion is necessary. The signature and public key must be stored in the standard ANSI X9.62 byte order (big-endian).

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_EccVerifyOption_t.
[in]pInputHashThe hash of the signed message in X9.62 format.
[in]pInputMessageThe message to sign.
[in]inputMessageLengthSize of pInputMessage in bytes.
[in]pSignatureAndPubKeyPointer to the memory area which contains the concatenation of the signature and the public key.
[out]pOutputPointer to the memory area which will receive the recalculated value of the R component in case of a successful signature verification.
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Parameter properties
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options.echashchl == MCUXCLELS_ECC_HASHED
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pInputHash is used, and it must be aligned on a 4-byte boundary. pInputMessage is ignored.
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options.echashchl == MCUXCLELS_ECC_NOT_HASHED
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pInputHash is ignored. pInputMessage and inputMessageLength are used.
+
pSignatureAndPubKey
+
It must be aligned on a 4-byte boundary. The signature to be verified consists of the 256-bit R component and the 256-bit S component. The public key is the one for verification. (Uncompressed, X and Y components) The signature and the public key are in X9.62 format.
+
pOutput
+
It must be aligned on a 4-byte boundary. The output shall be compared to the first 32 bytes stored at pSignatureAndPublicKey.
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Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00734.js b/components/els_pkc/doc/mcxn/html/a00734.js new file mode 100644 index 000000000..6b37f4b39 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00734.js @@ -0,0 +1,7 @@ +var a00734 = +[ + [ "mcuxClEls_EccKeyGen_Async", "a00734.html#ga060362493427031ef51110b7c381a986", null ], + [ "mcuxClEls_EccKeyExchange_Async", "a00734.html#ga39d6102bd9c792eb5a2e33af1f1830c3", null ], + [ "mcuxClEls_EccSign_Async", "a00734.html#ga96b17fadb9ee18906bb719e222908209", null ], + [ "mcuxClEls_EccVerify_Async", "a00734.html#ga019a066eda05dab4955ed76e83d39b77", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00735.html b/components/els_pkc/doc/mcxn/html/a00735.html new file mode 100644 index 000000000..be82556c0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00735.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Modules
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mcuxClEls_Hash
mcuxClEls
+
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+ +

This part of the mcuxClEls driver supports hashing. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Hash_Macros
 Defines all macros of mcuxClEls_Hash.
 
 mcuxClEls_Hash_Types
 Defines all types of mcuxClEls_Hash.
 
 mcuxClEls_Hash_Functions
 Defines all functions of mcuxClEls_Hash.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports hashing.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00735.js b/components/els_pkc/doc/mcxn/html/a00735.js new file mode 100644 index 000000000..936395a0d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00735.js @@ -0,0 +1,6 @@ +var a00735 = +[ + [ "mcuxClEls_Hash_Macros", "a00736.html", "a00736" ], + [ "mcuxClEls_Hash_Types", "a00741.html", "a00741" ], + [ "mcuxClEls_Hash_Functions", "a00742.html", "a00742" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00736.html b/components/els_pkc/doc/mcxn/html/a00736.html new file mode 100644 index 000000000..6760b1ede --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00736.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Macros + + + + + + + + + + + + + + + + +
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+ + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Modules
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mcuxClEls_Hash_Macros
mcuxClEls » mcuxClEls_Hash
+
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+ +

Defines all macros of mcuxClEls_Hash. +More...

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+Modules

 MCUXCLELS_HASH_
 Defines valid options to be used by mcuxClEls_HashOption_t.
 
 MCUXCLELS_HASH_BLOCK_SIZE_
 Defines block sizes used by the supported hash algorithms.
 
 MCUXCLELS_HASH_STATE_SIZE_
 Defines the intermediate state sizes of the supported hash algorithms.
 
 MCUXCLELS_HASH_OUTPUT_SIZE_
 Defines the output sizes of the supported hash algorithms (do not use for allocation)
 
#define MCUXCLELS_HASH_RTF_OUTPUT_SIZE
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Hash.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HASH_RTF_OUTPUT_SIZE

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+
+ + + + +
#define MCUXCLELS_HASH_RTF_OUTPUT_SIZE
+
+

Size of run-time fingerprint appended to the hash in pDigest in bytes, if MCUXCLELS_HASH_RTF_OUTPUT_ENABLE was specified

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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00736.js b/components/els_pkc/doc/mcxn/html/a00736.js new file mode 100644 index 000000000..4b9fc2bd5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00736.js @@ -0,0 +1,8 @@ +var a00736 = +[ + [ "MCUXCLELS_HASH_", "a00737.html", "a00737" ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_", "a00738.html", "a00738" ], + [ "MCUXCLELS_HASH_STATE_SIZE_", "a00739.html", "a00739" ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_", "a00740.html", "a00740" ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_SIZE", "a00736.html#ga0441e5ea8ef5538062269e9da3be7b6f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00737.html b/components/els_pkc/doc/mcxn/html/a00737.html new file mode 100644 index 000000000..f98956063 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00737.html @@ -0,0 +1,486 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_HASH_ + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
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MCUXCLELS_HASH_
mcuxClEls » mcuxClEls_Hash » mcuxClEls_Hash_Macros
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+ +

Defines valid options to be used by mcuxClEls_HashOption_t. +More...

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+Macros

#define MCUXCLELS_HASH_INIT_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashini to initialize the hash. More...
 
#define MCUXCLELS_HASH_INIT_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashini to continue the hash. More...
 
#define MCUXCLELS_HASH_LOAD_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashld to load the hash state from pDigest. More...
 
#define MCUXCLELS_HASH_LOAD_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashld to not load the hash state. More...
 
#define MCUXCLELS_HASH_OUTPUT_ENABLE
 Set this option at mcuxClEls_HashOption_t.hashoe to output the hash to pDigest. More...
 
#define MCUXCLELS_HASH_OUTPUT_DISABLE
 Set this option at mcuxClEls_HashOption_t.hashoe to not output the hash. More...
 
#define MCUXCLELS_HASH_RTF_UPDATE_ENABLE
 Set this option at mcuxClEls_HashOption_t.rtfupd to update the run-time fingerprint (only supported by mcuxClEls_Hash_Async) More...
 
#define MCUXCLELS_HASH_RTF_UPDATE_DISABLE
 Set this option at mcuxClEls_HashOption_t.rtfupd to not update the run-time fingerprint. More...
 
#define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE
 Set this option at mcuxClEls_HashOption_t.rtfoe to output the run-time fingerprint (only supported by mcuxClEls_Hash_Async) More...
 
#define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE
 Set this option at mcuxClEls_HashOption_t.rtfoe to not output the run-time fingerprint. More...
 
#define MCUXCLELS_HASH_MODE_SHA_224
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-224. More...
 
#define MCUXCLELS_HASH_MODE_SHA_256
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-256. More...
 
#define MCUXCLELS_HASH_MODE_SHA_384
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-384. More...
 
#define MCUXCLELS_HASH_MODE_SHA_512
 Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-512. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_224
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-224. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_256
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-256. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_384
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-384. More...
 
#define MCUXCLELS_HASH_VALUE_MODE_SHA_512
 Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-512. More...
 
+

Detailed Description

+

Defines valid options to be used by mcuxClEls_HashOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HASH_INIT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_INIT_ENABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashini to initialize the hash.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_INIT_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_INIT_DISABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashini to continue the hash.

+ +
+
+ +

◆ MCUXCLELS_HASH_LOAD_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_LOAD_ENABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashld to load the hash state from pDigest.

+ +
+
+ +

◆ MCUXCLELS_HASH_LOAD_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_LOAD_DISABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashld to not load the hash state.

+ +
+
+ +

◆ MCUXCLELS_HASH_OUTPUT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_ENABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashoe to output the hash to pDigest.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_OUTPUT_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_DISABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.hashoe to not output the hash.

+ +
+
+ +

◆ MCUXCLELS_HASH_RTF_UPDATE_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_RTF_UPDATE_ENABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.rtfupd to update the run-time fingerprint (only supported by mcuxClEls_Hash_Async)

+ +
+
+ +

◆ MCUXCLELS_HASH_RTF_UPDATE_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_RTF_UPDATE_DISABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.rtfupd to not update the run-time fingerprint.

+ +
+
+ +

◆ MCUXCLELS_HASH_RTF_OUTPUT_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.rtfoe to output the run-time fingerprint (only supported by mcuxClEls_Hash_Async)

+ +
+
+ +

◆ MCUXCLELS_HASH_RTF_OUTPUT_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE
+
+ +

Set this option at mcuxClEls_HashOption_t.rtfoe to not output the run-time fingerprint.

+ +
+
+ +

◆ MCUXCLELS_HASH_MODE_SHA_224

+ +
+
+ + + + +
#define MCUXCLELS_HASH_MODE_SHA_224
+
+ +

Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-224.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_MODE_SHA_256

+ +
+
+ + + + +
#define MCUXCLELS_HASH_MODE_SHA_256
+
+ +

Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-256.

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_MODE_SHA_384

+ +
+
+ + + + +
#define MCUXCLELS_HASH_MODE_SHA_384
+
+ +

Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-384.

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_MODE_SHA_512

+ +
+
+ + + + +
#define MCUXCLELS_HASH_MODE_SHA_512
+
+ +

Set this option at mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-512.

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_VALUE_MODE_SHA_224

+ +
+
+ + + + +
#define MCUXCLELS_HASH_VALUE_MODE_SHA_224
+
+ +

Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-224.

+ +
+
+ +

◆ MCUXCLELS_HASH_VALUE_MODE_SHA_256

+ +
+
+ + + + +
#define MCUXCLELS_HASH_VALUE_MODE_SHA_256
+
+ +

Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-256.

+ +
+
+ +

◆ MCUXCLELS_HASH_VALUE_MODE_SHA_384

+ +
+
+ + + + +
#define MCUXCLELS_HASH_VALUE_MODE_SHA_384
+
+ +

Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-384.

+ +
+
+ +

◆ MCUXCLELS_HASH_VALUE_MODE_SHA_512

+ +
+
+ + + + +
#define MCUXCLELS_HASH_VALUE_MODE_SHA_512
+
+ +

Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-512.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00737.js b/components/els_pkc/doc/mcxn/html/a00737.js new file mode 100644 index 000000000..62a415b2b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00737.js @@ -0,0 +1,21 @@ +var a00737 = +[ + [ "MCUXCLELS_HASH_INIT_ENABLE", "a00737.html#ga77bb4f8fa18f9e15f8a062c996aaa8b7", null ], + [ "MCUXCLELS_HASH_INIT_DISABLE", "a00737.html#gae4ee87c1b75f1f1b0499c55e32362314", null ], + [ "MCUXCLELS_HASH_LOAD_ENABLE", "a00737.html#gae826483f63146be0fcf0c06c132096ec", null ], + [ "MCUXCLELS_HASH_LOAD_DISABLE", "a00737.html#ga149c6d67f2f81c94d931660a041ea02a", null ], + [ "MCUXCLELS_HASH_OUTPUT_ENABLE", "a00737.html#gaba86f7cd657db104d355d74840eb4d42", null ], + [ "MCUXCLELS_HASH_OUTPUT_DISABLE", "a00737.html#gaedcd4ce245169a7375f96e7fb68c6bb8", null ], + [ "MCUXCLELS_HASH_RTF_UPDATE_ENABLE", "a00737.html#ga1aeb9d00c3be6bbbdb6421655f3b0c78", null ], + [ "MCUXCLELS_HASH_RTF_UPDATE_DISABLE", "a00737.html#ga403f2e98211fbc346b618654f9cbfaf2", null ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_ENABLE", "a00737.html#ga5a22b37440c5513f49344f7fabb8537b", null ], + [ "MCUXCLELS_HASH_RTF_OUTPUT_DISABLE", "a00737.html#gad1029c2f42df24f540d1d5ff7b3eaa2d", null ], + [ "MCUXCLELS_HASH_MODE_SHA_224", "a00737.html#gaf65949fa7e4326a043629a163a7b49d1", null ], + [ "MCUXCLELS_HASH_MODE_SHA_256", "a00737.html#gadc8c733440eb2908d653e3647f650072", null ], + [ "MCUXCLELS_HASH_MODE_SHA_384", "a00737.html#gaff4d85496f5f770b803a8b4643665d5e", null ], + [ "MCUXCLELS_HASH_MODE_SHA_512", "a00737.html#gaff0fe735de78d7fb9bb090b82167e47e", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_224", "a00737.html#ga55483aa09654820ae31a84aae32e1b37", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_256", "a00737.html#ga3a02725bdd6679e1354b9dec7e12c22c", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_384", "a00737.html#gaa55acf6e0c6b46a2ae67c260819a3621", null ], + [ "MCUXCLELS_HASH_VALUE_MODE_SHA_512", "a00737.html#ga9c10275675c3d6e4cccd6ebdfa229cc3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00738.html b/components/els_pkc/doc/mcxn/html/a00738.html new file mode 100644 index 000000000..e4ab64c74 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00738.html @@ -0,0 +1,216 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_HASH_BLOCK_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_HASH_BLOCK_SIZE_
mcuxClEls » mcuxClEls_Hash » mcuxClEls_Hash_Macros
+
+
+ +

Defines block sizes used by the supported hash algorithms. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224
 SHA-224 output size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256
 SHA-256 output size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384
 SHA-384 output size: 1024 bit (128 bytes) More...
 
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512
 SHA-512 output size: 1024 bit (128 bytes) More...
 
+

Detailed Description

+

Defines block sizes used by the supported hash algorithms.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HASH_BLOCK_SIZE_SHA_224

+ +
+
+ + + + +
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224
+
+ +

SHA-224 output size: 512 bit (64 bytes)

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_BLOCK_SIZE_SHA_256

+ +
+
+ + + + +
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256
+
+ +

SHA-256 output size: 512 bit (64 bytes)

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_BLOCK_SIZE_SHA_384

+ +
+
+ + + + +
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384
+
+ +

SHA-384 output size: 1024 bit (128 bytes)

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_BLOCK_SIZE_SHA_512

+ +
+
+ + + + +
#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512
+
+ +

SHA-512 output size: 1024 bit (128 bytes)

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00738.js b/components/els_pkc/doc/mcxn/html/a00738.js new file mode 100644 index 000000000..1ac45eef7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00738.js @@ -0,0 +1,7 @@ +var a00738 = +[ + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_224", "a00738.html#ga675b25b13fc541b6caf4ede098e62a3a", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_256", "a00738.html#gaa8a671b476a7428d5a63addc98c196ce", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_384", "a00738.html#ga3f675b49bbe27893e553c19279260be3", null ], + [ "MCUXCLELS_HASH_BLOCK_SIZE_SHA_512", "a00738.html#ga9488afdc7a3f5faf48e796ca3b2117dc", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00739.html b/components/els_pkc/doc/mcxn/html/a00739.html new file mode 100644 index 000000000..a58fc67cc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00739.html @@ -0,0 +1,216 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_HASH_STATE_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_HASH_STATE_SIZE_
mcuxClEls » mcuxClEls_Hash » mcuxClEls_Hash_Macros
+
+
+ +

Defines the intermediate state sizes of the supported hash algorithms. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_HASH_STATE_SIZE_SHA_224
 SHA-224 state size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_256
 SHA-256 state size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_384
 SHA-384 state size: 512 bit (64 bytes) More...
 
#define MCUXCLELS_HASH_STATE_SIZE_SHA_512
 SHA-512 state size: 512 bit (64 bytes) More...
 
+

Detailed Description

+

Defines the intermediate state sizes of the supported hash algorithms.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HASH_STATE_SIZE_SHA_224

+ +
+
+ + + + +
#define MCUXCLELS_HASH_STATE_SIZE_SHA_224
+
+ +

SHA-224 state size: 256 bit (32 bytes)

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_STATE_SIZE_SHA_256

+ +
+
+ + + + +
#define MCUXCLELS_HASH_STATE_SIZE_SHA_256
+
+ +

SHA-256 state size: 256 bit (32 bytes)

+
Examples
mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_STATE_SIZE_SHA_384

+ +
+
+ + + + +
#define MCUXCLELS_HASH_STATE_SIZE_SHA_384
+
+ +

SHA-384 state size: 512 bit (64 bytes)

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_STATE_SIZE_SHA_512

+ +
+
+ + + + +
#define MCUXCLELS_HASH_STATE_SIZE_SHA_512
+
+ +

SHA-512 state size: 512 bit (64 bytes)

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00739.js b/components/els_pkc/doc/mcxn/html/a00739.js new file mode 100644 index 000000000..62b87acf2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00739.js @@ -0,0 +1,7 @@ +var a00739 = +[ + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_224", "a00739.html#ga3fd16f21d04553be99f6c4bade526fcb", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_256", "a00739.html#ga9a24ee94d01d6b1b8cb33c7af84f8d9e", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_384", "a00739.html#ga2d78f8155107a52c3e618bab9bb52f85", null ], + [ "MCUXCLELS_HASH_STATE_SIZE_SHA_512", "a00739.html#gaf9f4da1c0d09797adb02f2af0bf4b429", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00740.html b/components/els_pkc/doc/mcxn/html/a00740.html new file mode 100644 index 000000000..a909f94fd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00740.html @@ -0,0 +1,216 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_HASH_OUTPUT_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_HASH_OUTPUT_SIZE_
mcuxClEls » mcuxClEls_Hash » mcuxClEls_Hash_Macros
+
+
+ +

Defines the output sizes of the supported hash algorithms (do not use for allocation) +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224
 SHA-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256
 SHA-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384
 SHA-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512
 SHA-512 output size: 512 bit (64 bytes) More...
 
+

Detailed Description

+

Defines the output sizes of the supported hash algorithms (do not use for allocation)

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224
+
+ +

SHA-224 output size: 224 bit (28 bytes)

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256
+
+ +

SHA-256 output size: 256 bit (32 bytes)

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Hash_Sha256_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384
+
+ +

SHA-384 output size: 384 bit (48 bytes)

+
Examples
mcuxClEls_Hash_Sha384_One_Block_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512

+ +
+
+ + + + +
#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512
+
+ +

SHA-512 output size: 512 bit (64 bytes)

+
Examples
mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00740.js b/components/els_pkc/doc/mcxn/html/a00740.js new file mode 100644 index 000000000..8c0d7236f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00740.js @@ -0,0 +1,7 @@ +var a00740 = +[ + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224", "a00740.html#ga5cc6964abb7966c445feb2abf14f8067", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256", "a00740.html#gaaa520442bedd60dec1b7e4b10ac57fe3", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384", "a00740.html#gab961aed69bd7828bf783f318a9dde671", null ], + [ "MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512", "a00740.html#gab75499823ecacb60bc8c9fdc8d541e95", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00741.html b/components/els_pkc/doc/mcxn/html/a00741.html new file mode 100644 index 000000000..17a7ef19e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00741.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Hash_Types
mcuxClEls » mcuxClEls_Hash
+
+
+ +

Defines all types of mcuxClEls_Hash. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_HashOption_t
 Command option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Hash.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00741.js b/components/els_pkc/doc/mcxn/html/a00741.js new file mode 100644 index 000000000..3d5878ca3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00741.js @@ -0,0 +1,16 @@ +var a00741 = +[ + [ "mcuxClEls_HashOption_t", "a01165.html", [ + [ "value", "a01165.html#a71c7896e79c292ac111d85992a16c78d", null ], + [ "word", "a01165.html#a4addaf59a3d2ab2743fd4c622c0e97ac", null ], + [ "__pad0__", "a01165.html#aae0a2c87c57c974e9cb7a55126f95ca9", null ], + [ "hashini", "a01165.html#ac9b592abc979189fad34fde3ec0c163c", null ], + [ "hashld", "a01165.html#a4a982ed0c424187a716adba9c0c99996", null ], + [ "hashmd", "a01165.html#a91c25618e98d1a9db1b1b13cfe52495f", null ], + [ "hashoe", "a01165.html#a2a87b3f8cde5a5cfdbea784ca4c6a58a", null ], + [ "rtfupd", "a01165.html#a1d91adca6cd4e274287063d2ff8d1884", null ], + [ "rtfoe", "a01165.html#a8c09f754695c9adc3ffe482375fc5f36", null ], + [ "__pad1__", "a01165.html#a97d346a2d66df4edd1ab677769a7b648", null ], + [ "bits", "a01165.html#aacda3c97994f6b172c7fd69c89d275dc", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00742.html b/components/els_pkc/doc/mcxn/html/a00742.html new file mode 100644 index 000000000..134c9631a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00742.html @@ -0,0 +1,221 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Hash_Functions
mcuxClEls » mcuxClEls_Hash
+
+
+ +

Defines all functions of mcuxClEls_Hash. +More...

+ + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hash_Async (mcuxClEls_HashOption_t options, uint8_t const *pInput, size_t inputLength, uint8_t *pDigest)
 Computes the hash of a message. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Hash.

+

Function Documentation

+ +

◆ mcuxClEls_Hash_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hash_Async (mcuxClEls_HashOption_t options,
uint8_t const * pInput,
size_t inputLength,
uint8_t * pDigest 
)
+
+ +

Computes the hash of a message.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_HashOption_t.
[in]pInputPadded input data to be hashed
[in]inputLengthSize of pInput in bytes. Since the input is padded, the length must be a multiple of the block size, see MCUXCLELS_HASH_BLOCK_SIZE_.
[in,out]pDigestPointer to the memory area that contains/receives the (intermediate) hash digest, allocated by the caller, see MCUXCLELS_HASH_STATE_SIZE_.
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.hashini == MCUXCLELS_HASH_INIT_ENABLE
+

options.hashld has no effect and shall be MCUXCLELS_HASH_LOAD_DISABLE. No data is read from pDigest.

+

+
+
options.hashld == MCUXCLELS_HASH_LOAD_DISABLE
+

pDigest is not expected to contain an initial state. No data is read from pDigest.

+

+
+
options.rtfoe == MCUXCLELS_HASH_RTF_UPDATE_ENABLE
+

When this option is used the current runtime fingerprint (RTF) value will be appended to the output pDigest; an additional MCUXCLELS_HASH_RTF_OUTPUT_SIZE bytes has to be allocated for pDigest.

+

+
+
options.hashoe == MCUXCLELS_HASH_OUTPUT_ENABLE
+

The hash state is written to pDigest. The size varies depending on the choice of options.hashmd, for more information see MCUXCLELS_HASH_STATE_SIZE_ . In cases where the state size and output size differ - see MCUXCLELS_HASH_OUTPUT_SIZE_ -, the state must be truncated by the caller to obtain the final hash value.

+

+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00742.js b/components/els_pkc/doc/mcxn/html/a00742.js new file mode 100644 index 000000000..517143e54 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00742.js @@ -0,0 +1,4 @@ +var a00742 = +[ + [ "mcuxClEls_Hash_Async", "a00742.html#ga086eeafba9afb8ea16550414fd33a3b3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00743.html b/components/els_pkc/doc/mcxn/html/a00743.html new file mode 100644 index 000000000..2db2c9665 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00743.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Hmac
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for hashed-key message authentication codes. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_Hmac_Macros
 Defines all macros of mcuxClEls_Hmac.
 
 mcuxClEls_Hmac_Types
 Defines all types of mcuxClEls_Hmac.
 
 mcuxClEls_Hmac_Functions
 Defines all functions of mcuxClEls_Hmac.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for hashed-key message authentication codes.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00743.js b/components/els_pkc/doc/mcxn/html/a00743.js new file mode 100644 index 000000000..ed1a11454 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00743.js @@ -0,0 +1,6 @@ +var a00743 = +[ + [ "mcuxClEls_Hmac_Macros", "a00744.html", "a00744" ], + [ "mcuxClEls_Hmac_Types", "a00746.html", "a00746" ], + [ "mcuxClEls_Hmac_Functions", "a00747.html", "a00747" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00744.html b/components/els_pkc/doc/mcxn/html/a00744.html new file mode 100644 index 000000000..cf38d0658 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00744.html @@ -0,0 +1,175 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClEls_Hmac_Macros
mcuxClEls » mcuxClEls_Hmac
+
+
+ +

Defines all macros of mcuxClEls_Hmac. +More...

+ + + + + +

+Modules

 MCUXCLELS_HMAC_EXTERNAL_KEY_
 Defines valid options to be used by mcuxClEls_HmacOption_t.
 
+ + + + + + +

+Macros

#define MCUXCLELS_HMAC_PADDED_KEY_SIZE
 
#define MCUXCLELS_HMAC_OUTPUT_SIZE
 HMAC Output size: 32 bytes. More...
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Hmac.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HMAC_PADDED_KEY_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_HMAC_PADDED_KEY_SIZE
+
+

HMAC Key size: 64 bytes

+ +
+
+ +

◆ MCUXCLELS_HMAC_OUTPUT_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_HMAC_OUTPUT_SIZE
+
+ +

HMAC Output size: 32 bytes.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00744.js b/components/els_pkc/doc/mcxn/html/a00744.js new file mode 100644 index 000000000..1d7327811 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00744.js @@ -0,0 +1,6 @@ +var a00744 = +[ + [ "MCUXCLELS_HMAC_EXTERNAL_KEY_", "a00745.html", "a00745" ], + [ "MCUXCLELS_HMAC_PADDED_KEY_SIZE", "a00744.html#ga039409b9bba04a61be14b175117fb932", null ], + [ "MCUXCLELS_HMAC_OUTPUT_SIZE", "a00744.html#ga80d89c1569e578566088cad0ea9127f4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00745.html b/components/els_pkc/doc/mcxn/html/a00745.html new file mode 100644 index 000000000..1fb84f67a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00745.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_HMAC_EXTERNAL_KEY_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_HMAC_EXTERNAL_KEY_
mcuxClEls » mcuxClEls_Hmac » mcuxClEls_Hmac_Macros
+
+
+ +

Defines valid options to be used by mcuxClEls_HmacOption_t. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
 Set mcuxClEls_HmacOption_t.extkey to this value to use an external key. More...
 
#define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
 Set mcuxClEls_HmacOption_t.extkey to this value to use a key from the ELS keystore. More...
 
+

Detailed Description

+

Defines valid options to be used by mcuxClEls_HmacOption_t.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE

+ +
+
+ + + + +
#define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
+
+ +

Set mcuxClEls_HmacOption_t.extkey to this value to use an external key.

+ +
+
+ +

◆ MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE

+ +
+
+ + + + +
#define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
+
+ +

Set mcuxClEls_HmacOption_t.extkey to this value to use a key from the ELS keystore.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00745.js b/components/els_pkc/doc/mcxn/html/a00745.js new file mode 100644 index 000000000..82dd2665d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00745.js @@ -0,0 +1,5 @@ +var a00745 = +[ + [ "MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE", "a00745.html#ga19feebc17331ebe966c67a9bfed79e33", null ], + [ "MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE", "a00745.html#ga876370de65e0c65b54c39b34921a4444", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00746.html b/components/els_pkc/doc/mcxn/html/a00746.html new file mode 100644 index 000000000..62d3de34e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00746.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_Hmac_Types
mcuxClEls » mcuxClEls_Hmac
+
+
+ +

Defines all types of mcuxClEls_Hmac. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_HmacOption_t
 Command option bit field for mcuxClEls_Hmac_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Hmac.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00746.js b/components/els_pkc/doc/mcxn/html/a00746.js new file mode 100644 index 000000000..3c693381a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00746.js @@ -0,0 +1,11 @@ +var a00746 = +[ + [ "mcuxClEls_HmacOption_t", "a01177.html", [ + [ "value", "a01177.html#a577065f77e409f612e5a2fc2072b971d", null ], + [ "word", "a01177.html#a5f797c75232df146cecc9c76dd04d463", null ], + [ "__pad0__", "a01177.html#a590b1d47d31c598e6df237437a015b8e", null ], + [ "extkey", "a01177.html#a4e16fabb042914665cabe00f5d6a6795", null ], + [ "__pad1__", "a01177.html#afa33782e670b9a44a28f71cb097ad830", null ], + [ "bits", "a01177.html#ae06ed09126b22cf0131a97bff34cc166", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00747.html b/components/els_pkc/doc/mcxn/html/a00747.html new file mode 100644 index 000000000..e9232cca0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00747.html @@ -0,0 +1,233 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hmac_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_Hmac_Functions
mcuxClEls » mcuxClEls_Hmac
+
+
+ +

Defines all functions of mcuxClEls_Hmac. +More...

+ + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hmac_Async (mcuxClEls_HmacOption_t options, mcuxClEls_KeyIndex_t keyIdx, uint8_t const *pPaddedKey, uint8_t const *pInput, size_t inputLength, uint8_t *pOutput)
 Performs HMAC with SHA-256. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Hmac.

+

Function Documentation

+ +

◆ mcuxClEls_Hmac_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hmac_Async (mcuxClEls_HmacOption_t options,
mcuxClEls_KeyIndex_t keyIdx,
uint8_t const * pPaddedKey,
uint8_t const * pInput,
size_t inputLength,
uint8_t * pOutput 
)
+
+ +

Performs HMAC with SHA-256.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_HmacOption_t.
[in]keyIdxThe HMAC key index, if an internal key shall be used
[in]pPaddedKeyPointer to a memory location containing the padded HMAC key
[in]pInputPointer to a memory location which contains the data to be authenticated
[in]inputLengthSize of pInput in bytes
[out]pOutputThe output message authentication code
+
+
+

The properties of some parameters change with respect to selected options.

+
+
Parameter properties
+
+
options.extkey == MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
+

keyIdx is ignored.

+

pPaddedKey must contain the padded HMAC key, which can mean one of two things depending on the length of the original HMAC key, LkHMAC:

+

+
+
options.extkey == MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
+

keyIdx must be a valid key index with the correct usage rights for HMAC.

+

pPaddedKey is ignored.

+

+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00747.js b/components/els_pkc/doc/mcxn/html/a00747.js new file mode 100644 index 000000000..a25a750aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00747.js @@ -0,0 +1,4 @@ +var a00747 = +[ + [ "mcuxClEls_Hmac_Async", "a00747.html#gafc82ce850568a1e0c9f44f9e59d6fbbf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00748.html b/components/els_pkc/doc/mcxn/html/a00748.html new file mode 100644 index 000000000..aa4a5b9c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00748.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Kdf
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for key derivation. +More...

+ + + + + + + + +

+Modules

 mcuxClEls_Kdf_Macros
 Defines all macros of mcuxClEls_Kdf.
 
 mcuxClEls_Kdf_Functions
 Defines all functions of mcuxClEls_Kdf.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for key derivation.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00748.js b/components/els_pkc/doc/mcxn/html/a00748.js new file mode 100644 index 000000000..a29559598 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00748.js @@ -0,0 +1,5 @@ +var a00748 = +[ + [ "mcuxClEls_Kdf_Macros", "a00749.html", "a00749" ], + [ "mcuxClEls_Kdf_Functions", "a00752.html", "a00752" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00749.html b/components/els_pkc/doc/mcxn/html/a00749.html new file mode 100644 index 000000000..56972ae55 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00749.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+Modules
+
+
mcuxClEls_Kdf_Macros
mcuxClEls » mcuxClEls_Kdf
+
+
+ +

Defines all macros of mcuxClEls_Kdf. +More...

+ + + + + + + + +

+Modules

 mcuxClEls_Kdf_Define
 constants
 
 mcuxClEls_Kdf_Types
 Defines all types of mcuxClEls_Kdf.
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Kdf.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00749.js b/components/els_pkc/doc/mcxn/html/a00749.js new file mode 100644 index 000000000..0825836b3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00749.js @@ -0,0 +1,5 @@ +var a00749 = +[ + [ "mcuxClEls_Kdf_Define", "a00750.html", "a00750" ], + [ "mcuxClEls_Kdf_Types", "a00751.html", "a00751" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00750.html b/components/els_pkc/doc/mcxn/html/a00750.html new file mode 100644 index 000000000..c61774939 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00750.html @@ -0,0 +1,402 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf_Define + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxClEls_Kdf_Define
mcuxClEls » mcuxClEls_Kdf » mcuxClEls_Kdf_Macros
+
+
+ +

constants +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE
 Size of CKDF SP800-108 derivation data. More...
 
#define MCUXCLELS_CKDF_ALGO_SP800108
 Use SP800-108 algorithm. More...
 
#define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE
 Size of HKDF derivation data. More...
 
#define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE
 Size of HKDF SP800-56C derived key. More...
 
#define MCUXCLELS_HKDF_VALUE_RTF_DERIV
 Use RTF as derivation input. More...
 
#define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV
 Use derivation input from system memory. More...
 
#define MCUXCLELS_HKDF_ALGO_RFC5869
 Use RFC5869 algorithm. More...
 
#define MCUXCLELS_HKDF_ALGO_SP80056C
 Use SP800-56C algorithm. More...
 
#define MCUXCLELS_HKDF_RTF_DERIV
 Use RTF as derivation input. More...
 
#define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV
 Use derivation input from system memory. More...
 
#define MCUXCLELS_TLS_DERIVATIONDATA_SIZE
 Size of TLS derivation data. More...
 
#define MCUXCLELS_TLS_RANDOM_SIZE
 Size of random bytes for TLS. More...
 
#define MCUXCLELS_TLS_INIT
 Perform master key generation. More...
 
#define MCUXCLELS_TLS_FINALIZE
 Perform session key generation. More...
 
+

Detailed Description

+

constants

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_CKDF_DERIVATIONDATA_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE
+
+ +

Size of CKDF SP800-108 derivation data.

+ +
+
+ +

◆ MCUXCLELS_CKDF_ALGO_SP800108

+ +
+
+ + + + +
#define MCUXCLELS_CKDF_ALGO_SP800108
+
+ +

Use SP800-108 algorithm.

+ +
+
+ +

◆ MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE
+
+ +

Size of HKDF derivation data.

+ +
+
+ +

◆ MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE
+
+ +

Size of HKDF SP800-56C derived key.

+ +
+
+ +

◆ MCUXCLELS_HKDF_VALUE_RTF_DERIV

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_VALUE_RTF_DERIV
+
+ +

Use RTF as derivation input.

+ +
+
+ +

◆ MCUXCLELS_HKDF_VALUE_MEMORY_DERIV

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV
+
+ +

Use derivation input from system memory.

+ +
+
+ +

◆ MCUXCLELS_HKDF_ALGO_RFC5869

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_ALGO_RFC5869
+
+ +

Use RFC5869 algorithm.

+ +
+
+ +

◆ MCUXCLELS_HKDF_ALGO_SP80056C

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_ALGO_SP80056C
+
+ +

Use SP800-56C algorithm.

+ +
+
+ +

◆ MCUXCLELS_HKDF_RTF_DERIV

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_RTF_DERIV
+
+ +

Use RTF as derivation input.

+ +
+
+ +

◆ MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV

+ +
+
+ + + + +
#define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV
+
+ +

Use derivation input from system memory.

+ +
+
+ +

◆ MCUXCLELS_TLS_DERIVATIONDATA_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_TLS_DERIVATIONDATA_SIZE
+
+ +

Size of TLS derivation data.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_TLS_RANDOM_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_TLS_RANDOM_SIZE
+
+ +

Size of random bytes for TLS.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_TLS_INIT

+ +
+
+ + + + +
#define MCUXCLELS_TLS_INIT
+
+ +

Perform master key generation.

+ +
+
+ +

◆ MCUXCLELS_TLS_FINALIZE

+ +
+
+ + + + +
#define MCUXCLELS_TLS_FINALIZE
+
+ +

Perform session key generation.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00750.js b/components/els_pkc/doc/mcxn/html/a00750.js new file mode 100644 index 000000000..459213a4d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00750.js @@ -0,0 +1,17 @@ +var a00750 = +[ + [ "MCUXCLELS_CKDF_DERIVATIONDATA_SIZE", "a00750.html#gae0e48994f0652e42fec3acca8c4469bb", null ], + [ "MCUXCLELS_CKDF_ALGO_SP800108", "a00750.html#gacb24894c500384a885842b542053b60f", null ], + [ "MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE", "a00750.html#ga7b1d08f458ed93ea2a17bdb8f8ecee40", null ], + [ "MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE", "a00750.html#gaf62127ae68ef3ec5815f3a7c3907d66f", null ], + [ "MCUXCLELS_HKDF_VALUE_RTF_DERIV", "a00750.html#ga9590681d68b6ef92ba29e53ecd556213", null ], + [ "MCUXCLELS_HKDF_VALUE_MEMORY_DERIV", "a00750.html#ga1af84f58a0ee007153d5e7dc65b43c2b", null ], + [ "MCUXCLELS_HKDF_ALGO_RFC5869", "a00750.html#ga3e905f07b3198e2853b8b099d68dc5d1", null ], + [ "MCUXCLELS_HKDF_ALGO_SP80056C", "a00750.html#ga41a071a8d47d42ec8350dd2db4f37867", null ], + [ "MCUXCLELS_HKDF_RTF_DERIV", "a00750.html#ga9eb01402c540d2f07a66cb1a26a12b1d", null ], + [ "MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV", "a00750.html#ga5b9747f125d34747a4707a5a08a572b2", null ], + [ "MCUXCLELS_TLS_DERIVATIONDATA_SIZE", "a00750.html#ga542a08e762e187464b77a707973eff65", null ], + [ "MCUXCLELS_TLS_RANDOM_SIZE", "a00750.html#gaf6beb56c924bf4d0bcea3a6fa31803be", null ], + [ "MCUXCLELS_TLS_INIT", "a00750.html#gaecd87e8690f333b6747f9e29848dfd08", null ], + [ "MCUXCLELS_TLS_FINALIZE", "a00750.html#gac9f01f30577af236ba91f31c78c428d2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00751.html b/components/els_pkc/doc/mcxn/html/a00751.html new file mode 100644 index 000000000..8ae8b9ba5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00751.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf_Types + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Data Structures
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mcuxClEls_Kdf_Types
mcuxClEls » mcuxClEls_Kdf » mcuxClEls_Kdf_Macros
+
+
+ +

Defines all types of mcuxClEls_Kdf. +More...

+ + + + + + + + + + + +

+Data Structures

union  mcuxClEls_CkdfOption_t
 Internal command option bit field for CKDF functions. More...
 
union  mcuxClEls_HkdfOption_t
 Command option bit field for mcuxClEls_Hkdf_Rfc5869_Async. More...
 
union  mcuxClEls_TlsOption_t
 Internal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Kdf.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00751.js b/components/els_pkc/doc/mcxn/html/a00751.js new file mode 100644 index 000000000..60c9012e5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00751.js @@ -0,0 +1,27 @@ +var a00751 = +[ + [ "mcuxClEls_CkdfOption_t", "a01189.html", [ + [ "value", "a01189.html#a00abd43e6b7c9816562f2aa1d93c0b9e", null ], + [ "word", "a01189.html#a240aaf0efe5383f3f6c8cd250b31800d", null ], + [ "__pad0__", "a01189.html#a3d042b5093efe84ebc959168e0d4a5cc", null ], + [ "ckdf_algo", "a01189.html#afc52662f6e41b83e0c731d77c616506c", null ], + [ "__pad1__", "a01189.html#a00e88c3d9213e40f64c614df04a7735e", null ], + [ "bits", "a01189.html#a6e776ad52679cfa22fa4ca287c37d84c", null ] + ] ], + [ "mcuxClEls_HkdfOption_t", "a01201.html", [ + [ "value", "a01201.html#aa39e185af4b2cfd758c0b7b7d3bea8db", null ], + [ "word", "a01201.html#a9f4a89742369066ab393e9389f8a01f4", null ], + [ "rtfdrvdat", "a01201.html#a7830e4ca489dcbca0e0b535e0979f5cc", null ], + [ "hkdf_algo", "a01201.html#ab385e81dfad37e2cdd8faaa1521ac405", null ], + [ "__pad0__", "a01201.html#aa8d2970a725074eb3ee5b9baed362eb3", null ], + [ "bits", "a01201.html#a09d3e6cb3ae38a2e55b7c9a3e8c80555", null ] + ] ], + [ "mcuxClEls_TlsOption_t", "a01213.html", [ + [ "value", "a01213.html#acfe68053c7558c29e085ca434cf432cd", null ], + [ "word", "a01213.html#a90ee1034a9ee1809c079014fa19ed2ee", null ], + [ "__pad0__", "a01213.html#acff6fecdc2046f7299e575ff0b7177e4", null ], + [ "mode", "a01213.html#a3f8fbc06563e97492965d16d9f7a4ed1", null ], + [ "__pad1__", "a01213.html#a9d609161f300e9d3a67c2144079a17d3", null ], + [ "bits", "a01213.html#a06a84c2cb4e3b2e3f227995fa6c70dec", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00752.html b/components/els_pkc/doc/mcxn/html/a00752.html new file mode 100644 index 000000000..6e34b225d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00752.html @@ -0,0 +1,458 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Kdf_Functions + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Functions
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+
mcuxClEls_Kdf_Functions
mcuxClEls » mcuxClEls_Kdf
+
+
+ +

Defines all functions of mcuxClEls_Kdf. +More...

+ + + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Rfc5869_Async (mcuxClEls_HkdfOption_t options, mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
 Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Sp80056c_Async (mcuxClEls_KeyIndex_t derivationKeyIdx, uint8_t *pTagetKey, uint8_t const *pDerivationData, size_t derivationDataLength)
 Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step approach with Sha2-256. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Ckdf_Sp800108_Async (mcuxClEls_KeyIndex_t derivationKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx, mcuxClEls_KeyProp_t targetKeyProperties, uint8_t const *pDerivationData)
 Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async (uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
 Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1.2 specification. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async (uint8_t const *pDerivationData, mcuxClEls_KeyProp_t keyProperties, mcuxClEls_KeyIndex_t keyIdx)
 Generates TLS session keys based on a master key and derivation data, according to the TLS 1.2 specification. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Kdf.

+

Function Documentation

+ +

◆ mcuxClEls_Hkdf_Rfc5869_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Rfc5869_Async (mcuxClEls_HkdfOption_t options,
mcuxClEls_KeyIndex_t derivationKeyIdx,
mcuxClEls_KeyIndex_t targetKeyIdx,
mcuxClEls_KeyProp_t targetKeyProperties,
uint8_t const * pDerivationData 
)
+
+ +

Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869.

+

Call mcuxClEls_WaitForOperation to complete the operation.

Parameters
+ + + + + + +
[in]optionsThe command options. For more information, see mcuxClEls_HkdfOption_t.
[in]derivationKeyIdxKey index used for derivation. Must be a 256-bit key with HKDF property bit set to 1.
[in]targetKeyIdxKey bank number of the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key.
[in]targetKeyPropertiesRequested properties for the derived key. The ksize field will be ignored.
[in]pDerivationDataThe algorithm-specific derivation data, the length is MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE bytes
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Hkdf_Sp80056c_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Hkdf_Sp80056c_Async (mcuxClEls_KeyIndex_t derivationKeyIdx,
uint8_t * pTagetKey,
uint8_t const * pDerivationData,
size_t derivationDataLength 
)
+
+ +

Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step approach with Sha2-256.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + +
[in]derivationKeyIdxKey index used for derivation. Must be a 256-bit key with HKDF property bit set to 1.
[out]pTagetKeyMemory area to store the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key.
[in]pDerivationDataThe algorithm-specific derivation data
[in]derivationDataLengthLength of the derivation data
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Ckdf_Sp800108_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Ckdf_Sp800108_Async (mcuxClEls_KeyIndex_t derivationKeyIdx,
mcuxClEls_KeyIndex_t targetKeyIdx,
mcuxClEls_KeyProp_t targetKeyProperties,
uint8_t const * pDerivationData 
)
+
+ +

Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + +
[in]derivationKeyIdxKey index used for derivation
[in]targetKeyIdxKey bank number of the derived key
[in]targetKeyPropertiesRequested properties for the derived key. Only set usage bits.
[in]pDerivationDataThe algorithm-specific derivation data, the length is MCUXCLELS_CKDF_DERIVATIONDATA_SIZE bytes
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async (uint8_t const * pDerivationData,
mcuxClEls_KeyProp_t keyProperties,
mcuxClEls_KeyIndex_t keyIdx 
)
+
+ +

Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1.2 specification.

+

The pre-master key is overwritten in this operation. Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + +
[in]pDerivationDataThe TLS derivation data, consisting of Label, Client Random and Server Random from the TLS 1.2 specification. Note: The order is different from mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async.
[in]keyPropertiesDesired key properties. Only mcuxClEls_KeyProp_t::upprot_priv and mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.
[in]keyIdxThe index of the TLS pre-master key, which is overwritten with the master key
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async (uint8_t const * pDerivationData,
mcuxClEls_KeyProp_t keyProperties,
mcuxClEls_KeyIndex_t keyIdx 
)
+
+ +

Generates TLS session keys based on a master key and derivation data, according to the TLS 1.2 specification.

+

The master key and the following five key indices are overwritten in this operation. The keys are written in the following order:

    +
  1. +Client Encryption Key
    2. +
  2. +Client Message Authentication Key
    3. +
  3. +Server Encryption Key
    4. +
  4. +Server Message Authentication Key
    5. +
+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + +
[in]pDerivationDataThe TLS derivation data, consisting of Label, Server Random and Client Random from the TLS 1.2 specification. Note: The order is different from mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async.
[in]keyPropertiesDesired key properties. Only mcuxClEls_KeyProp_t::upprot_priv and mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored.
[in]keyIdxThe index of the TLS master key, which is overwritten with one of the session keys. There must be three further consecutive unoccupied key indices following this index.
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00752.js b/components/els_pkc/doc/mcxn/html/a00752.js new file mode 100644 index 000000000..0c2d7bcd8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00752.js @@ -0,0 +1,8 @@ +var a00752 = +[ + [ "mcuxClEls_Hkdf_Rfc5869_Async", "a00752.html#gaad9187ee88fcb4efae7fd9469b51dc81", null ], + [ "mcuxClEls_Hkdf_Sp80056c_Async", "a00752.html#ga8d44c8b880565afe51d941057570361b", null ], + [ "mcuxClEls_Ckdf_Sp800108_Async", "a00752.html#ga4cf223def750c39f5c955fdfbe12bc8d", null ], + [ "mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async", "a00752.html#gac8b832b6cfa9c2b15b51be04ab349ae6", null ], + [ "mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async", "a00752.html#ga50b0d0753ed6a370b187904db49826ff", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00753.html b/components/els_pkc/doc/mcxn/html/a00753.html new file mode 100644 index 000000000..6a8863a69 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00753.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEls_KeyManagement
mcuxClEls
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+
+ +

This part of the mcuxClEls driver supports functionality for keys management. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClEls_KeyManagement_Macros
 Defines all macros of mcuxClEls_KeyManagement.
 
 mcuxClEls_KeyManagement_Types
 Defines all types of mcuxClEls_KeyManagement.
 
 mcuxClEls_KeyManagement_Functions
 Defines all functions of mcuxClEls_KeyManagement.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for keys management.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00753.js b/components/els_pkc/doc/mcxn/html/a00753.js new file mode 100644 index 000000000..ed5e69583 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00753.js @@ -0,0 +1,6 @@ +var a00753 = +[ + [ "mcuxClEls_KeyManagement_Macros", "a00754.html", "a00754" ], + [ "mcuxClEls_KeyManagement_Types", "a00758.html", "a00758" ], + [ "mcuxClEls_KeyManagement_Functions", "a00759.html", "a00759" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00754.html b/components/els_pkc/doc/mcxn/html/a00754.html new file mode 100644 index 000000000..c7f58f7fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00754.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_KeyManagement_Macros
mcuxClEls » mcuxClEls_KeyManagement
+
+
+ +

Defines all macros of mcuxClEls_KeyManagement. +More...

+ + + + + + + + + + + +

+Modules

 MCUXCLELS_KEYIMPORT_VALUE_KFMT_
 Defines valid options (word value) to be used by mcuxClEls_KeyImport_Async.
 
 MCUXCLELS_KEYIMPORT_KFMT_
 Defines valid options (bit values) to be used by mcuxClEls_KeyImport_Async.
 
 MCUXCLELS_RFC3394_
 Defines specifying the length of RFC3394 containers.
 
+

Detailed Description

+

Defines all macros of mcuxClEls_KeyManagement.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00754.js b/components/els_pkc/doc/mcxn/html/a00754.js new file mode 100644 index 000000000..01fdcc75b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00754.js @@ -0,0 +1,6 @@ +var a00754 = +[ + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_", "a00755.html", "a00755" ], + [ "MCUXCLELS_KEYIMPORT_KFMT_", "a00756.html", "a00756" ], + [ "MCUXCLELS_RFC3394_", "a00757.html", "a00757" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00755.html b/components/els_pkc/doc/mcxn/html/a00755.html new file mode 100644 index 000000000..2c257514a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00755.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYIMPORT_VALUE_KFMT_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_KEYIMPORT_VALUE_KFMT_
mcuxClEls » mcuxClEls_KeyManagement » mcuxClEls_KeyManagement_Macros
+
+
+ +

Defines valid options (word value) to be used by mcuxClEls_KeyImport_Async. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF
 Key format UDF with shares in RTL or memory. More...
 
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394
 Key format RFC3394 with shares in memory. More...
 
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF
 Key from PUF. More...
 
+

Detailed Description

+

Defines valid options (word value) to be used by mcuxClEls_KeyImport_Async.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF
+
+ +

Key format UDF with shares in RTL or memory.

+ +
+
+ +

◆ MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394
+
+ +

Key format RFC3394 with shares in memory.

+ +
+
+ +

◆ MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF
+
+ +

Key from PUF.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00755.js b/components/els_pkc/doc/mcxn/html/a00755.js new file mode 100644 index 000000000..1b6f93741 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00755.js @@ -0,0 +1,6 @@ +var a00755 = +[ + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF", "a00755.html#ga984d35cad96543f5cb269a9ee771834b", null ], + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394", "a00755.html#ga8ae5e78cfde658034967faafbbc84c97", null ], + [ "MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF", "a00755.html#gabf3d81b763b4402dd1a4716ca7b10a56", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00756.html b/components/els_pkc/doc/mcxn/html/a00756.html new file mode 100644 index 000000000..71c4ebaa7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00756.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYIMPORT_KFMT_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_KEYIMPORT_KFMT_
mcuxClEls » mcuxClEls_KeyManagement » mcuxClEls_KeyManagement_Macros
+
+
+ +

Defines valid options (bit values) to be used by mcuxClEls_KeyImport_Async. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYIMPORT_KFMT_UDF
 Key format UDF with shares in RTL or memory. More...
 
#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394
 Key format RFC3394 with shares in memory. More...
 
#define MCUXCLELS_KEYIMPORT_KFMT_PUF
 Key from PUF. More...
 
#define MCUXCLELS_RFC3394_OVERHEAD
 Overhead between RFC3394 blob and key size. More...
 
+

Detailed Description

+

Defines valid options (bit values) to be used by mcuxClEls_KeyImport_Async.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEYIMPORT_KFMT_UDF

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_KFMT_UDF
+
+ +

Key format UDF with shares in RTL or memory.

+ +
+
+ +

◆ MCUXCLELS_KEYIMPORT_KFMT_RFC3394

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394
+
+ +

Key format RFC3394 with shares in memory.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYIMPORT_KFMT_PUF

+ +
+
+ + + + +
#define MCUXCLELS_KEYIMPORT_KFMT_PUF
+
+ +

Key from PUF.

+ +
+
+ +

◆ MCUXCLELS_RFC3394_OVERHEAD

+ +
+
+ + + + +
#define MCUXCLELS_RFC3394_OVERHEAD
+
+ +

Overhead between RFC3394 blob and key size.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00756.js b/components/els_pkc/doc/mcxn/html/a00756.js new file mode 100644 index 000000000..f5899f3f1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00756.js @@ -0,0 +1,7 @@ +var a00756 = +[ + [ "MCUXCLELS_KEYIMPORT_KFMT_UDF", "a00756.html#ga1935d246d89a89d4d04c393b40161429", null ], + [ "MCUXCLELS_KEYIMPORT_KFMT_RFC3394", "a00756.html#gaa3f8c4e99d3c233eeaa2685d9e0d4b67", null ], + [ "MCUXCLELS_KEYIMPORT_KFMT_PUF", "a00756.html#ga757baa3bf038e4f16c63e356a2a590a6", null ], + [ "MCUXCLELS_RFC3394_OVERHEAD", "a00756.html#ga9c38ef72ae48380b864e6e5fb950ee17", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00757.html b/components/els_pkc/doc/mcxn/html/a00757.html new file mode 100644 index 000000000..b3b098d1c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00757.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_RFC3394_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLELS_RFC3394_
mcuxClEls » mcuxClEls_KeyManagement » mcuxClEls_KeyManagement_Macros
+
+
+ +

Defines specifying the length of RFC3394 containers. +More...

+ + + + + + + + +

+Macros

#define MCUXCLELS_RFC3394_CONTAINER_SIZE_128
 Size of RFC3394 container for 128 bit key. More...
 
#define MCUXCLELS_RFC3394_CONTAINER_SIZE_256
 Size of RFC3394 container for 256 bit key. More...
 
+

Detailed Description

+

Defines specifying the length of RFC3394 containers.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_RFC3394_CONTAINER_SIZE_128

+ +
+
+ + + + +
#define MCUXCLELS_RFC3394_CONTAINER_SIZE_128
+
+ +

Size of RFC3394 container for 128 bit key.

+ +
+
+ +

◆ MCUXCLELS_RFC3394_CONTAINER_SIZE_256

+ +
+
+ + + + +
#define MCUXCLELS_RFC3394_CONTAINER_SIZE_256
+
+ +

Size of RFC3394 container for 256 bit key.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00757.js b/components/els_pkc/doc/mcxn/html/a00757.js new file mode 100644 index 000000000..4c58c73c2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00757.js @@ -0,0 +1,5 @@ +var a00757 = +[ + [ "MCUXCLELS_RFC3394_CONTAINER_SIZE_128", "a00757.html#ga4d0fa5e5255eb1fa89b0cf6a30a452fb", null ], + [ "MCUXCLELS_RFC3394_CONTAINER_SIZE_256", "a00757.html#ga46c8e56ff10c6a6ecb28c511cd32178c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00758.html b/components/els_pkc/doc/mcxn/html/a00758.html new file mode 100644 index 000000000..88e2f34bd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00758.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures
+
+
mcuxClEls_KeyManagement_Types
mcuxClEls » mcuxClEls_KeyManagement
+
+
+ +

Defines all types of mcuxClEls_KeyManagement. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_KeyImportOption_t
 Command option bit field for mcuxClEls_KeyImport_Async. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_KeyManagement.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00758.js b/components/els_pkc/doc/mcxn/html/a00758.js new file mode 100644 index 000000000..e236b465e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00758.js @@ -0,0 +1,13 @@ +var a00758 = +[ + [ "mcuxClEls_KeyImportOption_t", "a01225.html", [ + [ "value", "a01225.html#ad5bfabd7e1e04a95627e0cbc144afdcb", null ], + [ "word", "a01225.html#a9a03426cf6b706ee292473b3d695ebe0", null ], + [ "__pad0__", "a01225.html#a2dfcb81e1476a07a6ab67f8c090b4ab5", null ], + [ "revf", "a01225.html#aa699b2cfb2fc82dcbc25d833e09d442e", null ], + [ "__pad1__", "a01225.html#ad67985d38d1563a926768316825e1944", null ], + [ "kfmt", "a01225.html#ae3892b035704c00a855dd43d96a21b2c", null ], + [ "__pad2__", "a01225.html#a05660839da43298f12f96572bf538330", null ], + [ "bits", "a01225.html#ad0fc563d3f708b06c986ec2ae604d69e", null ] + ] ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00759.html b/components/els_pkc/doc/mcxn/html/a00759.html new file mode 100644 index 000000000..ab372dc1e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00759.html @@ -0,0 +1,380 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyManagement_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClEls_KeyManagement_Functions
mcuxClEls » mcuxClEls_KeyManagement
+
+
+ +

Defines all functions of mcuxClEls_KeyManagement. +More...

+ + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyDelete_Async (mcuxClEls_KeyIndex_t keyIdx)
 Deletes a key from keystore at the given index. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyImport_Async (mcuxClEls_KeyImportOption_t options, uint8_t const *pImportKey, size_t importKeyLength, mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t targetKeyIdx)
 Imports a key from external storage to an internal key register. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyExport_Async (mcuxClEls_KeyIndex_t wrappingKeyIdx, mcuxClEls_KeyIndex_t exportKeyIdx, uint8_t *pOutput)
 Exports a key from an internal key register to external storage, using a wrapping key. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetKeyProperties (mcuxClEls_KeyIndex_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp)
 Exports the properties of the keys stored in the ELS internal keystore. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_KeyManagement.

+

Function Documentation

+ +

◆ mcuxClEls_KeyDelete_Async()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyDelete_Async (mcuxClEls_KeyIndex_t keyIdx)
+
+ +

Deletes a key from keystore at the given index.

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + +
[in]keyIdxThe index of the key to be deleted
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_SW_FAULTif a failure occurred
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_KeyImport_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyImport_Async (mcuxClEls_KeyImportOption_t options,
uint8_t const * pImportKey,
size_t importKeyLength,
mcuxClEls_KeyIndex_t wrappingKeyIdx,
mcuxClEls_KeyIndex_t targetKeyIdx 
)
+
+ +

Imports a key from external storage to an internal key register.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + + + +
[in]optionsOne of MCUXCLELS_KEYIMPORT_KFMT_
[in]pImportKeyPointer to the RFC3394 container of the key to be imported
[in]importKeyLengthLength of the RFC3394 container of the key to be imported
[in]wrappingKeyIdxIndex of the key wrapping key, if importing RFC3394 format
[in]targetKeyIdxThe desired key index of the imported key
+
+
+
+
Parameter properties
+
+
options.kfmt != MCUXCLELS_KEYIMPORT_KFMT_RFC3394
+
    +
  • +pImportKey is ignored.
    • +
  • +importKeyLength is ignored.
    • +
  • +wrappingKeyIdx is ignored.
    • +
  • +targetKeyIdx is ignored. The unpacked key is automatically stored in key slots 0, 1.
    • +
+
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ mcuxClEls_KeyExport_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_KeyExport_Async (mcuxClEls_KeyIndex_t wrappingKeyIdx,
mcuxClEls_KeyIndex_t exportKeyIdx,
uint8_t * pOutput 
)
+
+ +

Exports a key from an internal key register to external storage, using a wrapping key.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + + +
[in]wrappingKeyIdxThe key used for key wrapping
[in]exportKeyIdxThe key to export
[out]pOutputThe memory address of the exported key
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_INVALID_PARAMif invalid parameters were specified
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+
Parameters
+ + + + +
[in]wrappingKeyIdxThe key used for key wrapping
[in]exportKeyIdxThe key to export
[out]pOutputThe memory address of the exported key
+
+
+ +
+
+ +

◆ mcuxClEls_GetKeyProperties()

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_GetKeyProperties (mcuxClEls_KeyIndex_t keyIdx,
mcuxClEls_KeyProp_t * pKeyProp 
)
+
+ +

Exports the properties of the keys stored in the ELS internal keystore.

+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + +
[in]keyIdxRequest key properties of the index defined here
[out]pKeyPropKey properties of the index provided
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OKon successful request
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00759.js b/components/els_pkc/doc/mcxn/html/a00759.js new file mode 100644 index 000000000..7f66edea7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00759.js @@ -0,0 +1,7 @@ +var a00759 = +[ + [ "mcuxClEls_KeyDelete_Async", "a00759.html#ga035d072c033f988194110973581c6303", null ], + [ "mcuxClEls_KeyImport_Async", "a00759.html#ga867d4be563b347273af25a559abd7f87", null ], + [ "mcuxClEls_KeyExport_Async", "a00759.html#ga698ad21f0b3576d2b9f4b7b3ef83134f", null ], + [ "mcuxClEls_GetKeyProperties", "a00759.html#ga524d99bbf9aae0d299fbb52d2a121c4f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00760.html b/components/els_pkc/doc/mcxn/html/a00760.html new file mode 100644 index 000000000..364a0b4b6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00760.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClEls_Rng
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver supports functionality for random number generation. +More...

+ + + + + + + + +

+Modules

 mcuxClEls_Rng_Macros
 Defines all macros of mcuxClEls_Rng.
 
 mcuxClEls_Rng_Functions
 Defines all functions of mcuxClEls_Rng.
 
+

Detailed Description

+

This part of the mcuxClEls driver supports functionality for random number generation.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00760.js b/components/els_pkc/doc/mcxn/html/a00760.js new file mode 100644 index 000000000..11f80aee5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00760.js @@ -0,0 +1,5 @@ +var a00760 = +[ + [ "mcuxClEls_Rng_Macros", "a00761.html", "a00761" ], + [ "mcuxClEls_Rng_Functions", "a00762.html", "a00762" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00761.html b/components/els_pkc/doc/mcxn/html/a00761.html new file mode 100644 index 000000000..54b03b6b9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00761.html @@ -0,0 +1,303 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ +
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+ +
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+Macros
+
+
mcuxClEls_Rng_Macros
mcuxClEls » mcuxClEls_Rng
+
+
+ +

Defines all macros of mcuxClEls_Rng. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE
 Size of DTRNG configuration. More...
 
#define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE
 Size of DTRNG characterization data. More...
 
#define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE
 Size of DTRNG characterization result. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
 Minimum output size of mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
 Maximum output size of mcuxClEls_Rng_DrbgTestExtract_Async. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE
 Command options value for DRBG Test Instantiate command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT
 Command options value for DRBG Test Extract command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB
 Command options value for DRBG Test AES-ECB command. For internal use. More...
 
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR
 Command options value for DRBG Test AES-CTR command. For internal use. More...
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Rng.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_RNG_DTRNG_CONFIG_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE
+
+ +

Size of DTRNG configuration.

+ +
+
+ +

◆ MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE
+
+ +

Size of DTRNG characterization data.

+ +
+
+ +

◆ MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE
+
+ +

Size of DTRNG characterization result.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE
+
+ +

Minimum output size of mcuxClEls_Rng_DrbgTestExtract_Async.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE
+
+ +

Maximum output size of mcuxClEls_Rng_DrbgTestExtract_Async.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE
+
+ +

Command options value for DRBG Test Instantiate command. For internal use.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT
+
+ +

Command options value for DRBG Test Extract command. For internal use.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB
+
+ +

Command options value for DRBG Test AES-ECB command. For internal use.

+ +
+
+ +

◆ MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR

+ +
+
+ + + + +
#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR
+
+ +

Command options value for DRBG Test AES-CTR command. For internal use.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00761.js b/components/els_pkc/doc/mcxn/html/a00761.js new file mode 100644 index 000000000..638ce144c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00761.js @@ -0,0 +1,12 @@ +var a00761 = +[ + [ "MCUXCLELS_RNG_DTRNG_CONFIG_SIZE", "a00761.html#ga62287bdc5d7f577d4196b409fa9e27c2", null ], + [ "MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE", "a00761.html#ga05b362ef8faa883390e693f6f0499261", null ], + [ "MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE", "a00761.html#ga612e743bb2a36fec076fbf45bb9fb871", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE", "a00761.html#ga4e1cd62dea9fd027f68c6e95f887a052", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE", "a00761.html#ga28815696e8ff825c435f97fd74a63682", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE", "a00761.html#gaefdcd27bd482d26a59b449860c7c07e6", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT", "a00761.html#ga6e8e503cbc286ca4082b3f8f757e43b8", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB", "a00761.html#gac1504aed0077bef23daf988d3630b089", null ], + [ "MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR", "a00761.html#gafe0506d5703701493637b44873e80f9c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00762.html b/components/els_pkc/doc/mcxn/html/a00762.html new file mode 100644 index 000000000..4279c3663 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00762.html @@ -0,0 +1,605 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Functions
+
+
mcuxClEls_Rng_Functions
mcuxClEls » mcuxClEls_Rng
+
+
+ +

Defines all functions of mcuxClEls_Rng. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgRequest_Async (uint8_t *pOutput, size_t outputLength)
 Writes random data from the ELS DRBG to the given buffer. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestInstantiate_Async (uint8_t const *pEntropy)
 Instantiates the DRBG in test mode. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestExtract_Async (uint8_t *pOutput, size_t outputLength)
 Performs a DRBG extraction. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesEcb_Async (uint8_t const *pDataKey, uint8_t *pOutput)
 Encrypts data using the AES-ECB engine of the DRBG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesCtr_Async (uint8_t const *pData, size_t dataLength, uint8_t const *pIvKey, uint8_t *pOutput)
 Encrypts data using the AES-CTR engine of the DRBG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigLoad_Async (uint8_t const *pInput)
 Loads a configuration of the ELS DTRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async (uint8_t const *pInput, uint8_t *pOutput)
 Performs characterization of the ELS DTRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandomWord (uint32_t *pWord)
 Returns one random word from the ELS PRNG. More...
 
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandom (uint8_t *pOutput, size_t outputLength)
 Writes random data from the ELS PRNG to the given buffer. More...
 
+

Detailed Description

+

Defines all functions of mcuxClEls_Rng.

+

Function Documentation

+ +

◆ mcuxClEls_Rng_DrbgRequest_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgRequest_Async (uint8_t * pOutput,
size_t outputLength 
)
+
+ +

Writes random data from the ELS DRBG to the given buffer.

+

This function fills a buffer with random values from the DRBG. The DRBG provides 128 bits of security strength.

+

Before execution, ELS will wait until mcuxClEls_HwState_t.drbgentlvl == MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call.

+

If the random values from the DRBG are later used as a cryptographic key, the security strength of the cryptographic operation using the generated key should not exceed that of the DRBG.

+

To name a few examples, this means (as per NIST SP 800-57 Part 1 Rev. 5):

    +
  • AES-192 or AES-256 keys generated with this function will provide only 128 bits of security strength
    • +
  • RSA keys longer than 3072 bits will provide only 128 bits of security strength
    • +
  • ECC keys longer than 383 bits will provide only 128 bits of security strength
    • +
+

Call mcuxClEls_WaitForOperation to complete the operation.

+
Parameters
+ + + +
[out]pOutputPointer to the beginning of the memory area to fill with random data
[in]outputLengthNumber of requested random bytes
+
+
+
+
Parameter properties
+
+
outputLength
+
supported values are MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_SW_FAULTin case of an internal error
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_DrbgTestInstantiate_Async()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestInstantiate_Async (uint8_t const * pEntropy)
+
+ +

Instantiates the DRBG in test mode.

+

This function is a support function for FIPS CAVP testing. This function turns the ELS internal DRBG in test mode by loading known entropy from system memory. Call mcuxClEls_WaitForOperation to complete the operation. Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.

+
Parameters
+ + +
[in]pEntropyPointer to the input entropy data
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_DrbgTestExtract_Async()

+ +
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+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestExtract_Async (uint8_t * pOutput,
size_t outputLength 
)
+
+ +

Performs a DRBG extraction.

+

This function is a support function for FIPS CAVP testing. This function mimics the behavior of mcuxClEls_Rng_DrbgRequest_Async and fills a buffer with random data when DRBG is in test mode. Call mcuxClEls_WaitForOperation to complete the operation. Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.

+
Attention
mcuxClEls_Rng_DrbgTestInstantiate_Async must be called prior to this function.
+
Parameters
+ + + +
[out]pOutputPointer to the output random number
[in]outputLengthLength of the random number
+
+
+
+
Parameter properties
+
+
outputLength
+
supported values are MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.
+
+
+
+
Returns
An error code (see MCUXCLELS_STATUS_)
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_DrbgTestAesEcb_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesEcb_Async (uint8_t const * pDataKey,
uint8_t * pOutput 
)
+
+ +

Encrypts data using the AES-ECB engine of the DRBG.

+

This function is a support function for FIPS CAVP testing. This function performs an AES-ECB encryption on system data to evaluate the encryption engine of the DRBG. Call mcuxClEls_WaitForOperation to complete the operation. Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.

+
Parameters
+ + + +
[in]pDataKeyPointer to the data and key
[out]pOutputPointer to the encrypted output
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_DrbgTestAesCtr_Async()

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MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_DrbgTestAesCtr_Async (uint8_t const * pData,
size_t dataLength,
uint8_t const * pIvKey,
uint8_t * pOutput 
)
+
+ +

Encrypts data using the AES-CTR engine of the DRBG.

+

This function is a support function for FIPS CAVP testing. This function performs an AES-CTR encryption on system data to evaluate the encryption engine of the DRBG in test mode. Call mcuxClEls_WaitForOperation to complete the operation. Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. The update process is majorly impacted by the time the TRNG needs to provide fresh entropy.

+
Parameters
+ + + + + +
[in]pDataPointer to the data to be encrypted
[in]dataLengthLength of the data to be encrypted
[in]pIvKeyPointer to the IV and key
[out]pOutputPointer to the encrypted output
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_Dtrng_ConfigLoad_Async()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigLoad_Async (uint8_t const * pInput)
+
+ +

Loads a configuration of the ELS DTRNG.

+

This function overwrites the default DTRNG configuration in order to optimize or fine tune the DTRNG entropy gathering process. Call mcuxClEls_WaitForOperation to complete the operation. Note that the TRNG configuration set by this function is non-persistent and any reset of the ELS (e.g. a power-cycle or calling mcuxClEls_Reset_Async) will resets the DTRNG configuration to its default value.

+
Parameters
+ + +
[in]pInputThe pointer to DTRNG initialization data
+
+
+
+
Parameter properties
+
+
pInput
+
The size is MCUXCLELS_RNG_DTRNG_CONFIG_SIZE bytes.
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async()

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async (uint8_t const * pInput,
uint8_t * pOutput 
)
+
+ +

Performs characterization of the ELS DTRNG.

+

This function evaluates a DTRNG configuration for device specific characterization. The configuration used for characterization has to be placed in system memory. Call mcuxClEls_WaitForOperation to complete the operation.

+
Attention
If this function is called once, all other ELS commands except mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async are blocked until any reset of the ELS (e.g. a power-cycle or calling mcuxClEls_Reset_Async) is triggered.
+
Parameters
+ + + +
[in]pInputThe pointer to DTRNG initialization data
[out]pOutputThe pointer to the evaluation result
+
+
+
+
Parameter properties
+
+
pInput
+
The size is MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE bytes.
+
pOutput
+
The size is MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE bytes.
+
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_SW_CANNOT_INTERRUPTif a running operation prevented the request
MCUXCLELS_STATUS_OK_WAITon successful request
+
+
+ +
+
+ +

◆ mcuxClEls_Prng_GetRandomWord()

+ +
+
+ + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandomWord (uint32_t * pWord)
+
+ +

Returns one random word from the ELS PRNG.

+

This function returns one low-quality random CPU word gathered from the PRNG.

+
Attention
PRNG has to be initialized prior to the first time calling this function.
+
Parameters
+ + +
[out]pWordThe pointer to the random word
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_OKon successful request
MCUXCLELS_STATUS_HW_PRNGin case of insufficient entropy
+
+
+
Examples
mcuxClEls_Rng_Prng_Get_Random_example.c.
+
+ +
+
+ +

◆ mcuxClEls_Prng_GetRandom()

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUXCLELS_API mcuxClEls_Status_t mcuxClEls_Prng_GetRandom (uint8_t * pOutput,
size_t outputLength 
)
+
+ +

Writes random data from the ELS PRNG to the given buffer.

+

This function fills a buffer with low-quality random values gathered from the PRNG.

+
Attention
PRNG has to be initialized prior to the first time calling this function.
+
Parameters
+ + + +
[out]pOutputPointer to the beginning of the memory area to fill with random data from PRNG
[in]outputLengthSize of pOutput in bytes
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLELS_STATUS_OKon successful request
MCUXCLELS_STATUS_HW_PRNGin case of insufficient entropy
+
+
+
Examples
mcuxClEls_Rng_Prng_Get_Random_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00762.js b/components/els_pkc/doc/mcxn/html/a00762.js new file mode 100644 index 000000000..a56cd500d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00762.js @@ -0,0 +1,12 @@ +var a00762 = +[ + [ "mcuxClEls_Rng_DrbgRequest_Async", "a00762.html#gac48eddfc58d2fc6aebe0dd373baf4360", null ], + [ "mcuxClEls_Rng_DrbgTestInstantiate_Async", "a00762.html#ga17e52c0038540a032faf460033df35e6", null ], + [ "mcuxClEls_Rng_DrbgTestExtract_Async", "a00762.html#ga89b800a51c4046c7c7736d545595e097", null ], + [ "mcuxClEls_Rng_DrbgTestAesEcb_Async", "a00762.html#gaa356b6cafdb26f78c90fc9a24dd7dcd8", null ], + [ "mcuxClEls_Rng_DrbgTestAesCtr_Async", "a00762.html#gada018f6414175632aa2328ffd2ed02bf", null ], + [ "mcuxClEls_Rng_Dtrng_ConfigLoad_Async", "a00762.html#ga254ab1259a0688701233e1cf3636b244", null ], + [ "mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async", "a00762.html#gac7fb747c02024315df352977d8269535", null ], + [ "mcuxClEls_Prng_GetRandomWord", "a00762.html#ga10ee7783feeef4fbe5d5309c61f358a1", null ], + [ "mcuxClEls_Prng_GetRandom", "a00762.html#ga222cf598c85ceb0483297169255688b0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00763.html b/components/els_pkc/doc/mcxn/html/a00763.html new file mode 100644 index 000000000..3d244ab65 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00763.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Modules
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mcuxClEls_Types
mcuxClEls
+
+
+ +

This part of the mcuxClEls driver defines common types. +More...

+ + + + + + + + +

+Modules

 mcuxClEls_Types_Macros
 Defines all macros of mcuxClEls_Types.
 
 mcuxClEls_Types_Types
 Defines all types of mcuxClEls_Types.
 
+

Detailed Description

+

This part of the mcuxClEls driver defines common types.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00763.js b/components/els_pkc/doc/mcxn/html/a00763.js new file mode 100644 index 000000000..39d7ca7d3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00763.js @@ -0,0 +1,5 @@ +var a00763 = +[ + [ "mcuxClEls_Types_Macros", "a00764.html", "a00764" ], + [ "mcuxClEls_Types_Types", "a00768.html", "a00768" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00764.html b/components/els_pkc/doc/mcxn/html/a00764.html new file mode 100644 index 000000000..2bb2167cf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00764.html @@ -0,0 +1,210 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Types_Macros + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Modules | +Macros
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mcuxClEls_Types_Macros
mcuxClEls » mcuxClEls_Types
+
+
+ +

Defines all macros of mcuxClEls_Types. +More...

+ + + + + + + + + + + +

+Modules

 MCUXCLELS_KEYPROPERTY_VALUE_
 Constants for initalizing mcuxClEls_KeyProp_t.word.
 
 MCUXCLELS_KEYPROPERTY_
 Constants for initalizing mcuxClEls_KeyProp_t.bits.
 
 MCUXCLELS_STATUS_
 Return code definitions.
 
+ + + + + + + + + + +

+Macros

#define MCUXCLELS_KEY_SLOTS
 Number of key slots in the ELS key store. More...
 
#define MCUXCLELS_STATUS_IS_HW_ERROR(x)
 Checks whether an error code is a hardware error. Indicates that an error was reported by ELS hardware. More...
 
#define MCUXCLELS_STATUS_IS_SW_ERROR(x)
 Checks whether an error code is a software error. Indicates that the error was detected by the driver software and not by ELS hardware. More...
 
+

Detailed Description

+

Defines all macros of mcuxClEls_Types.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEY_SLOTS

+ +
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+ + + + +
#define MCUXCLELS_KEY_SLOTS
+
+ +

Number of key slots in the ELS key store.

+ +
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+ +

◆ MCUXCLELS_STATUS_IS_HW_ERROR

+ +
+
+ + + + + + + + +
#define MCUXCLELS_STATUS_IS_HW_ERROR( x)
+
+ +

Checks whether an error code is a hardware error. Indicates that an error was reported by ELS hardware.

+ +
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+ +

◆ MCUXCLELS_STATUS_IS_SW_ERROR

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+ + + + + + + + +
#define MCUXCLELS_STATUS_IS_SW_ERROR( x)
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+ +

Checks whether an error code is a software error. Indicates that the error was detected by the driver software and not by ELS hardware.

+ +
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00764.js b/components/els_pkc/doc/mcxn/html/a00764.js new file mode 100644 index 000000000..3147bb87e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00764.js @@ -0,0 +1,9 @@ +var a00764 = +[ + [ "MCUXCLELS_KEYPROPERTY_VALUE_", "a00765.html", "a00765" ], + [ "MCUXCLELS_KEYPROPERTY_", "a00766.html", "a00766" ], + [ "MCUXCLELS_STATUS_", "a00767.html", "a00767" ], + [ "MCUXCLELS_KEY_SLOTS", "a00764.html#ga68a354e8f8ccdcf5ea6b44458894e11c", null ], + [ "MCUXCLELS_STATUS_IS_HW_ERROR", "a00764.html#gae333a22199f8899e33304329a5ea3a3e", null ], + [ "MCUXCLELS_STATUS_IS_SW_ERROR", "a00764.html#ga1787a44ce530639142f3a63e5c38f1b5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00765.html b/components/els_pkc/doc/mcxn/html/a00765.html new file mode 100644 index 000000000..07a7adb06 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00765.html @@ -0,0 +1,664 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYPROPERTY_VALUE_ + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
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MCUXCLELS_KEYPROPERTY_VALUE_
mcuxClEls » mcuxClEls_Types » mcuxClEls_Types_Macros
+
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+ +

Constants for initalizing mcuxClEls_KeyProp_t.word. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128
 128-bit key More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256
 256-bit key More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE
 Key is active (loaded) More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT
 First part of multi-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
 General purpose key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT
 Retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT
 Hardware output key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_CMAC
 CMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KSK
 Key signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_RTF
 RTF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_CKDF
 CKDF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HKDF
 HKDF signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN
 ECC signing key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_ECDH
 ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_AES
 AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HMAC
 HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KWK
 Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KUOK
 Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
 TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
 TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC
 Can provide key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT
 A key to be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK
 The key can be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_DUK
 Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED
 Caller must be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED
 Caller does not have to be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_SECURE
 Caller must be in secure mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE
 Caller does not have to be in secure mode to use the key. More...
 
+

Detailed Description

+

Constants for initalizing mcuxClEls_KeyProp_t.word.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128
+
+ +

128-bit key

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256
+
+ +

256-bit key

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE

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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE
+
+ +

Key is active (loaded)

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT
+
+ +

First part of multi-slot key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT

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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT
+
+ +

General purpose key slot.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT

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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT
+
+ +

Retention key slot.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT

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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT
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+ +

Hardware output key slot.

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◆ MCUXCLELS_KEYPROPERTY_VALUE_CMAC

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#define MCUXCLELS_KEYPROPERTY_VALUE_CMAC
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+ +

CMAC key.

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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KSK

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#define MCUXCLELS_KEYPROPERTY_VALUE_KSK
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+ +

Key signing key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_RTF

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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_RTF
+
+ +

RTF signing key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_CKDF

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_CKDF
+
+ +

CKDF signing key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_HKDF

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_HKDF
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+ +

HKDF signing key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_ECSGN

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN
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+ +

ECC signing key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_ECDH

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_ECDH
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+ +

ECC Diffie Hellman private key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_AES

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#define MCUXCLELS_KEYPROPERTY_VALUE_AES
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+ +

AES key.

+ +
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+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_HMAC

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_HMAC
+
+ +

HMAC key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KWK

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_KWK
+
+ +

Key Wrapping Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KUOK

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_KUOK
+
+ +

Key Unwrapping Only Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET
+
+ +

TLS Premaster Secret.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET
+
+ +

TLS Master Secret.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_KGSRC

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC
+
+ +

Can provide key material input for ECC key generation.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT

+ +
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+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT
+
+ +

A key to be used in a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_WRPOK

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK
+
+ +

The key can be wrapped.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_DUK

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_DUK
+
+ +

Device Unique Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED
+
+ +

Caller must be in privileged mode to use the key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED
+
+ +

Caller does not have to be in privileged mode to use the key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_SECURE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_SECURE
+
+ +

Caller must be in secure mode to use the key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE
+
+ +

Caller does not have to be in secure mode to use the key.

+ +
+
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00765.js b/components/els_pkc/doc/mcxn/html/a00765.js new file mode 100644 index 000000000..9d97630fb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00765.js @@ -0,0 +1,31 @@ +var a00765 = +[ + [ "MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128", "a00765.html#ga20705a3a067d321f364a1c5b278a32d8", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256", "a00765.html#gaa605da5172899ce79cb55909ed4a3464", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE", "a00765.html#ga38ccbdbdaade2b7880d64982044e8035", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT", "a00765.html#gabbdb03610e94b456d47ad12d7a12140e", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT", "a00765.html#gad18d55603e3e1563ea9da2edafc26315", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT", "a00765.html#gaacc968f77f54b1b66903aecb8fbb1e1c", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT", "a00765.html#ga7f07dfb893d2d9cd087f63c931f2ca29", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_CMAC", "a00765.html#gae181bcf54a9e911574ac80f47e9478b0", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KSK", "a00765.html#ga6dc65c24d84015a37cc697a1f8ebfa94", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_RTF", "a00765.html#ga0a33beb3623a2c3d1bdd1d3194419b51", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_CKDF", "a00765.html#ga005bacc1cb8c881365bdf22cc3264af5", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HKDF", "a00765.html#gaa4e7e020109bb4a83c8f05f17fb860bb", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ECSGN", "a00765.html#ga3a77d34b3cdb470dbe9cbac0c6383488", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_ECDH", "a00765.html#gaa50202ab187ade63e84c8b589a08ce58", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_AES", "a00765.html#gac45ebca89b1aa9788366cb5d1bbc92f8", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HMAC", "a00765.html#ga64d0aa24d8057d5c96b8bc1a6f5d8711", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KWK", "a00765.html#ga518248d788f4fe3746c9ca910d70f38b", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KUOK", "a00765.html#ga40d6978ccb822e1dccd7701cc635ffc9", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET", "a00765.html#gadc12177ca1a434524bf41e3e646bea4c", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET", "a00765.html#gac71ffc243f1c14fea51a8cfe0a5bb7da", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_KGSRC", "a00765.html#ga70889526167cbf5e75912e430372a993", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT", "a00765.html#ga7388b2da16ebf2291f6b4a682240f073", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_WRPOK", "a00765.html#gadf248e85c19983b971956e30471b5b68", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_DUK", "a00765.html#ga5333f4f5fd6978a1c4bd9e6cae7a4955", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED", "a00765.html#ga714925236ac3417792b5b51054c5f479", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED", "a00765.html#ga193c53f3465e549c04bffb48c614b976", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_SECURE", "a00765.html#ga938259096a964f99992874407cb75b5b", null ], + [ "MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE", "a00765.html#gaee9d5c2f7654dab8449372339f6eb857", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00766.html b/components/els_pkc/doc/mcxn/html/a00766.html new file mode 100644 index 000000000..7e1d7669c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00766.html @@ -0,0 +1,1108 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_KEYPROPERTY_ + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros
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MCUXCLELS_KEYPROPERTY_
mcuxClEls » mcuxClEls_Types » mcuxClEls_Types_Macros
+
+
+ +

Constants for initalizing mcuxClEls_KeyProp_t.bits. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128
 This value of mcuxClEls_KeyProp_t.ksize indicates a 128 bit key. More...
 
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
 This value of mcuxClEls_KeyProp_t.ksize indicates a 256 bit key. More...
 
#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
 This value of mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key. More...
 
#define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE
 This value of mcuxClEls_KeyProp_t.kactv indicates that the slot does not contain active key. More...
 
#define MCUXCLELS_KEYPROPERTY_BASE_SLOT
 This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECOND_SLOT
 This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the second slot of a 2-slot key. More...
 
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a retention key slot or a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a neither retention key slot nor hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is a retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is not a retention key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE
 This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE
 This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is not a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_CMAC_TRUE
 This value of mcuxClEls_KeyProp_t.ucmac indicates that the key can be used for CMAC. More...
 
#define MCUXCLELS_KEYPROPERTY_CMAC_FALSE
 This value of mcuxClEls_KeyProp_t.ucmac indicates that the key cannot be used for CMAC. More...
 
#define MCUXCLELS_KEYPROPERTY_KSK_TRUE
 This value of mcuxClEls_KeyProp_t.uksk indicates that the key can be used for key signing. More...
 
#define MCUXCLELS_KEYPROPERTY_KSK_FALSE
 This value of mcuxClEls_KeyProp_t.uksk indicates that the key cannot be used for key signing. More...
 
#define MCUXCLELS_KEYPROPERTY_RTF_TRUE
 This value of mcuxClEls_KeyProp_t.urtf indicates that the key can be used for RTF signing. More...
 
#define MCUXCLELS_KEYPROPERTY_RTF_FALSE
 This value of mcuxClEls_KeyProp_t.urtf indicates that the key cannot be used for RTF signing. More...
 
#define MCUXCLELS_KEYPROPERTY_CKDF_TRUE
 This value of mcuxClEls_KeyProp_t.uckdf indicates that the key can be used for CKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_CKDF_FALSE
 This value of mcuxClEls_KeyProp_t.uckdf indicates that the key cannot be used for CKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_HKDF_TRUE
 This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key can be used for HKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_HKDF_FALSE
 This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key cannot be used for HKDF. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_TRUE
 This value of mcuxClEls_KeyProp_t.uecsg indicates that the key can be used for ECC signing. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_FALSE
 This value of mcuxClEls_KeyProp_t.uecsg indicates that the key cannot be used for ECC signing. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
 This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is a ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
 This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is not an ECC Diffie Hellman private key. More...
 
#define MCUXCLELS_KEYPROPERTY_AES_TRUE
 This value of mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_AES_FALSE
 This value of mcuxClEls_KeyProp_t.uaes indicates that the key is not an AES key. More...
 
#define MCUXCLELS_KEYPROPERTY_HMAC_TRUE
 This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is an HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_HMAC_FALSE
 This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is not an HMAC key. More...
 
#define MCUXCLELS_KEYPROPERTY_KWK_TRUE
 This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KWK_FALSE
 This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is not a Key Wrapping Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KUOK_TRUE
 This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is a Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_KUOK_FALSE
 This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is not a Key Unwrapping Only Key. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
 This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is a TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
 This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is not a TLS Premaster Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
 This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is a TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
 This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is not a TLS Master Secret. More...
 
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
 This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key can be used as key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
 This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key cannot be used as key material input for ECC key generation. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE
 This value of mcuxClEls_KeyProp_t.uhwo indicates that the key can be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE
 This value of mcuxClEls_KeyProp_t.uhwo indicates that the key cannot be used in a hardware out key slot. More...
 
#define MCUXCLELS_KEYPROPERTY_WRAP_TRUE
 This value of mcuxClEls_KeyProp_t.wrpok indicates that the key can be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_WRAP_FALSE
 This value of mcuxClEls_KeyProp_t.wrpok indicates that the key cannot be wrapped. More...
 
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
 This value of mcuxClEls_KeyProp_t.duk indicates that the key is a Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
 This value of mcuxClEls_KeyProp_t.duk indicates that the key is not a Device Unique Key. More...
 
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
 This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE
 This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller does not need to be in privileged mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE
 This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use the key. More...
 
#define MCUXCLELS_KEYPROPERTY_SECURE_FALSE
 This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller does not need to be in secure mode to use the key. More...
 
+

Detailed Description

+

Constants for initalizing mcuxClEls_KeyProp_t.bits.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_KEYPROPERTY_KEY_SIZE_128

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128
+
+ +

This value of mcuxClEls_KeyProp_t.ksize indicates a 128 bit key.

+
Examples
mcuxClKey_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KEY_SIZE_256

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256
+
+ +

This value of mcuxClEls_KeyProp_t.ksize indicates a 256 bit key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.kactv indicates that the slot does not contain active key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_BASE_SLOT

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_BASE_SLOT
+
+ +

This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_SECOND_SLOT

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_SECOND_SLOT
+
+ +

This value of mcuxClEls_KeyProp_t.kbase indicates that the slot is the second slot of a 2-slot key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a retention key slot or a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.fgp indicates that the slot is a neither retention key slot nor hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is a retention key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.frtn indicates that the slot is not a retention key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.fhwo indicates that the slot is not a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_CMAC_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_CMAC_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.ucmac indicates that the key can be used for CMAC.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_CMAC_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_CMAC_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.ucmac indicates that the key cannot be used for CMAC.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KSK_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KSK_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uksk indicates that the key can be used for key signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KSK_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KSK_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uksk indicates that the key cannot be used for key signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_RTF_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_RTF_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.urtf indicates that the key can be used for RTF signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_RTF_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_RTF_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.urtf indicates that the key cannot be used for RTF signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_CKDF_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_CKDF_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uckdf indicates that the key can be used for CKDF.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_CKDF_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_CKDF_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uckdf indicates that the key cannot be used for CKDF.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HKDF_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HKDF_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key can be used for HKDF.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HKDF_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HKDF_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uhkdf indicates that the key cannot be used for HKDF.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ECC_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ECC_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uecsg indicates that the key can be used for ECC signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ECC_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ECC_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uecsg indicates that the key cannot be used for ECC signing.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is a ECC Diffie Hellman private key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uecdh indicates that the key is not an ECC Diffie Hellman private key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_AES_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_AES_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_AES_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_AES_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uaes indicates that the key is not an AES key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HMAC_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HMAC_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is an HMAC key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HMAC_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HMAC_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uhmac indicates that the key is not an HMAC key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KWK_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KWK_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KWK_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KWK_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.ukwk indicates that the key is not a Key Wrapping Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KUOK_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KUOK_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is a Key Unwrapping Only Key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_KUOK_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_KUOK_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.ukuok indicates that the key is not a Key Unwrapping Only Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is a TLS Premaster Secret.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.utlspms indicates that the key is not a TLS Premaster Secret.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is a TLS Master Secret.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.utlsms indicates that the key is not a TLS Master Secret.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key can be used as key material input for ECC key generation.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.ukgsrc indicates that the key cannot be used as key material input for ECC key generation.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.uhwo indicates that the key can be used in a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.uhwo indicates that the key cannot be used in a hardware out key slot.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_WRAP_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_WRAP_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.wrpok indicates that the key can be wrapped.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_WRAP_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_WRAP_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.wrpok indicates that the key cannot be wrapped.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.duk indicates that the key is a Device Unique Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.duk indicates that the key is not a Device Unique Key.

+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to use the key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.upprot_priv indicates that the caller does not need to be in privileged mode to use the key.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_SECURE_TRUE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE
+
+ +

This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use the key.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_KEYPROPERTY_SECURE_FALSE

+ +
+
+ + + + +
#define MCUXCLELS_KEYPROPERTY_SECURE_FALSE
+
+ +

This value of mcuxClEls_KeyProp_t.upprot_sec indicates that the caller does not need to be in secure mode to use the key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00766.js b/components/els_pkc/doc/mcxn/html/a00766.js new file mode 100644 index 000000000..72cd7adf1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00766.js @@ -0,0 +1,53 @@ +var a00766 = +[ + [ "MCUXCLELS_KEYPROPERTY_KEY_SIZE_128", "a00766.html#ga4cacf5225b1aa96c74f05b111cfd0298", null ], + [ "MCUXCLELS_KEYPROPERTY_KEY_SIZE_256", "a00766.html#ga755a270fd53677522cafd0e56a6be66f", null ], + [ "MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE", "a00766.html#ga80e7d70c48a472dba6067d6b8e97bb68", null ], + [ "MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE", "a00766.html#gadba88640610efd722fd6cb31131476ac", null ], + [ "MCUXCLELS_KEYPROPERTY_BASE_SLOT", "a00766.html#ga8a549e38eaccd502bd48a82e95ff20f2", null ], + [ "MCUXCLELS_KEYPROPERTY_SECOND_SLOT", "a00766.html#ga2a587ef5925801237ed4289ba7124bc1", null ], + [ "MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE", "a00766.html#ga7db639faa4a274e77743882b7057c537", null ], + [ "MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE", "a00766.html#gae3b99cfb55454bdc413aace5afd71890", null ], + [ "MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE", "a00766.html#ga9f77c7afd0e967dbde5dfd67b8d41257", null ], + [ "MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE", "a00766.html#ga69b01ec32c2541c387b1bab005e4b03e", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE", "a00766.html#ga644cefc65b923481fdf6013ffad6a664", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE", "a00766.html#ga289019e9ef73c7f796ab0b69d2d5223f", null ], + [ "MCUXCLELS_KEYPROPERTY_CMAC_TRUE", "a00766.html#ga2f6b74eae56797b769e35fb9d1d5465e", null ], + [ "MCUXCLELS_KEYPROPERTY_CMAC_FALSE", "a00766.html#ga362b93220be9faf000985a3b28380ad0", null ], + [ "MCUXCLELS_KEYPROPERTY_KSK_TRUE", "a00766.html#ga00953660d09e3ed62645b167851b9cc9", null ], + [ "MCUXCLELS_KEYPROPERTY_KSK_FALSE", "a00766.html#ga432995f0ef41d5b333e9b3829122bc42", null ], + [ "MCUXCLELS_KEYPROPERTY_RTF_TRUE", "a00766.html#gad03052755431d2adfeaa30277e418f04", null ], + [ "MCUXCLELS_KEYPROPERTY_RTF_FALSE", "a00766.html#ga8a942c5fc98bc8ffdc5f009ba3bfa29c", null ], + [ "MCUXCLELS_KEYPROPERTY_CKDF_TRUE", "a00766.html#ga8d6171d58db58d9ba6e15e7f9cb0c057", null ], + [ "MCUXCLELS_KEYPROPERTY_CKDF_FALSE", "a00766.html#ga960f82984c81287e968904ffd41be70c", null ], + [ "MCUXCLELS_KEYPROPERTY_HKDF_TRUE", "a00766.html#gac0b2f4e4b25b10f1674d8baa8d38286e", null ], + [ "MCUXCLELS_KEYPROPERTY_HKDF_FALSE", "a00766.html#gaa80640a904308caeb41895739ef281d1", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_TRUE", "a00766.html#gab457f8b10780aad731269d29445a2333", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_FALSE", "a00766.html#ga3f8380fec95cb01265199fd2a9e7c5a7", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE", "a00766.html#gaec7f78155e96050db23eaf4a623ea5a7", null ], + [ "MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE", "a00766.html#gaec997cabe18f4c4188a602c39890aadf", null ], + [ "MCUXCLELS_KEYPROPERTY_AES_TRUE", "a00766.html#gae292b4575efaa152a6a2704c05e079c7", null ], + [ "MCUXCLELS_KEYPROPERTY_AES_FALSE", "a00766.html#ga9960540d8489d2022ee67e60e77858bf", null ], + [ "MCUXCLELS_KEYPROPERTY_HMAC_TRUE", "a00766.html#ga0174e78e6f43bf25603e6ac5791d6031", null ], + [ "MCUXCLELS_KEYPROPERTY_HMAC_FALSE", "a00766.html#gabaace8fb57f6d821d042639dd83024b4", null ], + [ "MCUXCLELS_KEYPROPERTY_KWK_TRUE", "a00766.html#ga8f78e035c0c348d9c95250cbb5c06bdc", null ], + [ "MCUXCLELS_KEYPROPERTY_KWK_FALSE", "a00766.html#ga456e3e1f4c7dbfedb45b81407b55619b", null ], + [ "MCUXCLELS_KEYPROPERTY_KUOK_TRUE", "a00766.html#ga116b9a68bec502c77b49b95189cdd51c", null ], + [ "MCUXCLELS_KEYPROPERTY_KUOK_FALSE", "a00766.html#gaed363ebd3822cf20b7b6eb97477e4683", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE", "a00766.html#gafb78c8a3541eb87092a513461fd77b16", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE", "a00766.html#gab55f1e3817acebe4ac54babddac0ae54", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE", "a00766.html#ga821ec254e0847c27f58345e3be802768", null ], + [ "MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE", "a00766.html#ga4723acef377d8337e76cf3a24b0e32df", null ], + [ "MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE", "a00766.html#ga65bc587af872d79766a1990b644d65ad", null ], + [ "MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE", "a00766.html#ga6bb1e8b818ab13bec2351784f459c815", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE", "a00766.html#ga0504273f3b2e50c2574b8a8d83475afb", null ], + [ "MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE", "a00766.html#gadade800ab03e3b7693f8a68005205a34", null ], + [ "MCUXCLELS_KEYPROPERTY_WRAP_TRUE", "a00766.html#gaf07168a64eb99d5788e096d735871c3f", null ], + [ "MCUXCLELS_KEYPROPERTY_WRAP_FALSE", "a00766.html#ga1b9c490f4f9556731df00636c902c76a", null ], + [ "MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE", "a00766.html#ga265cc12998ae7e8bb54e4f61ae2c21db", null ], + [ "MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE", "a00766.html#ga1ee99e7d2dcd7dd025bd9dbebfe31c2e", null ], + [ "MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE", "a00766.html#ga45d5d7ba7da1060c55a4bac5279841cc", null ], + [ "MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE", "a00766.html#gaa613ab074bf3fc6b9f90a69f505d2e28", null ], + [ "MCUXCLELS_KEYPROPERTY_SECURE_TRUE", "a00766.html#ga2088d83e8ab366a72075f52e3ca352ad", null ], + [ "MCUXCLELS_KEYPROPERTY_SECURE_FALSE", "a00766.html#gae85a65c3e6ae36cc74de69fa6a562a7a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00767.html b/components/els_pkc/doc/mcxn/html/a00767.html new file mode 100644 index 000000000..b819dd284 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00767.html @@ -0,0 +1,421 @@ + + + + + + + +MCUX CLNS: MCUXCLELS_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros
+
+
MCUXCLELS_STATUS_
mcuxClEls » mcuxClEls_Types » mcuxClEls_Types_Macros
+
+
+ +

Return code definitions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLELS_STATUS_OK
 No error occurred. More...
 
#define MCUXCLELS_STATUS_OK_WAIT
 An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete it. More...
 
#define MCUXCLELS_STATUS_HW_FAULT
 ELS hardware detected a fault. More...
 
#define MCUXCLELS_STATUS_HW_ALGORITHM
 An algorithm failed in hardware. More...
 
#define MCUXCLELS_STATUS_HW_OPERATIONAL
 ELS was operated incorrectly. More...
 
#define MCUXCLELS_STATUS_HW_BUS
 A bus access failed. More...
 
#define MCUXCLELS_STATUS_HW_INTEGRITY
 An integrity check failed in hardware. More...
 
#define MCUXCLELS_STATUS_HW_PRNG
 Read access to PRNG output while PRNG is not in ready state. More...
 
#define MCUXCLELS_STATUS_HW_DTRNG
 Unable to get entropy from dTRNG with current configuration. More...
 
#define MCUXCLELS_STATUS_SW_FAULT
 Software detected a fault. More...
 
#define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT
 an ELS command was started while the ELS was still busy, or a SHA-Direct command was started while the SHA kernel was still busy More...
 
#define MCUXCLELS_STATUS_SW_INVALID_PARAM
 Incorrect parameters were supplied. More...
 
#define MCUXCLELS_STATUS_SW_INVALID_STATE
 This can happen when ELS is in a wrong state for the requested ELS command. More...
 
#define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED
 A software counter expired while waiting for an ELS operation to finish. More...
 
#define MCUXCLELS_STATUS_SW_COMPARISON_FAILED
 A comparison between an ELS flag and its expected value failed. More...
 
+

Detailed Description

+

Return code definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLELS_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_OK
+
+ +

No error occurred.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Common_Get_Info_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Rng_Prng_Get_Random_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUXCLELS_STATUS_OK_WAIT

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_OK_WAIT
+
+ +

An _Async function successfully started an ELS command. Call mcuxClEls_WaitForOperation to complete it.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
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+ +

◆ MCUXCLELS_STATUS_HW_FAULT

+ +
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+ + + + +
#define MCUXCLELS_STATUS_HW_FAULT
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+ +

ELS hardware detected a fault.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_ALGORITHM

+ +
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+ + + + +
#define MCUXCLELS_STATUS_HW_ALGORITHM
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+ +

An algorithm failed in hardware.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_OPERATIONAL

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_HW_OPERATIONAL
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+ +

ELS was operated incorrectly.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_BUS

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_HW_BUS
+
+ +

A bus access failed.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_INTEGRITY

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_HW_INTEGRITY
+
+ +

An integrity check failed in hardware.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_PRNG

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_HW_PRNG
+
+ +

Read access to PRNG output while PRNG is not in ready state.

+ +
+
+ +

◆ MCUXCLELS_STATUS_HW_DTRNG

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_HW_DTRNG
+
+ +

Unable to get entropy from dTRNG with current configuration.

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_FAULT

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_SW_FAULT
+
+ +

Software detected a fault.

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT

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+
+ + + + +
#define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT
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+ +

an ELS command was started while the ELS was still busy, or a SHA-Direct command was started while the SHA kernel was still busy

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_INVALID_PARAM

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_SW_INVALID_PARAM
+
+ +

Incorrect parameters were supplied.

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_INVALID_STATE

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_SW_INVALID_STATE
+
+ +

This can happen when ELS is in a wrong state for the requested ELS command.

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_COUNTER_EXPIRED

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED
+
+ +

A software counter expired while waiting for an ELS operation to finish.

+ +
+
+ +

◆ MCUXCLELS_STATUS_SW_COMPARISON_FAILED

+ +
+
+ + + + +
#define MCUXCLELS_STATUS_SW_COMPARISON_FAILED
+
+ +

A comparison between an ELS flag and its expected value failed.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00767.js b/components/els_pkc/doc/mcxn/html/a00767.js new file mode 100644 index 000000000..e2829c89e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00767.js @@ -0,0 +1,18 @@ +var a00767 = +[ + [ "MCUXCLELS_STATUS_OK", "a00767.html#ga022996920a649ed71428ed73e53eae8a", null ], + [ "MCUXCLELS_STATUS_OK_WAIT", "a00767.html#ga0c69ecf4e48929c38549c8b430dae4b2", null ], + [ "MCUXCLELS_STATUS_HW_FAULT", "a00767.html#ga5903a9bf2687c19a6a4c89a0486f2ccb", null ], + [ "MCUXCLELS_STATUS_HW_ALGORITHM", "a00767.html#gacf60910b71f03c324d53f8b6563baf4c", null ], + [ "MCUXCLELS_STATUS_HW_OPERATIONAL", "a00767.html#ga6f70e740d4b57dc50083fd6f052ad434", null ], + [ "MCUXCLELS_STATUS_HW_BUS", "a00767.html#ga84e18c7cc39ffd66abc53f7353269a84", null ], + [ "MCUXCLELS_STATUS_HW_INTEGRITY", "a00767.html#gac58ea9f6e1103f32cd5cac0b2c45549c", null ], + [ "MCUXCLELS_STATUS_HW_PRNG", "a00767.html#ga1ba84ebe125bbe9dc402d9089bc46164", null ], + [ "MCUXCLELS_STATUS_HW_DTRNG", "a00767.html#ga1dc849dc5b6501b5f1c9e68f89f07881", null ], + [ "MCUXCLELS_STATUS_SW_FAULT", "a00767.html#gad3b3fde6156b816225f119a525c7f0b4", null ], + [ "MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT", "a00767.html#ga20ac618d5c0b386df110135322b94ed6", null ], + [ "MCUXCLELS_STATUS_SW_INVALID_PARAM", "a00767.html#ga96347d1bd07cc9ee18688f1973219878", null ], + [ "MCUXCLELS_STATUS_SW_INVALID_STATE", "a00767.html#gac167d607babe9a7f93950b581c08bdef", null ], + [ "MCUXCLELS_STATUS_SW_COUNTER_EXPIRED", "a00767.html#gaf10c1ef8b7689807ed2d163fe71c4b89", null ], + [ "MCUXCLELS_STATUS_SW_COMPARISON_FAILED", "a00767.html#gaddad780e0aef6a33d31b800ecb8673cd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00768.html b/components/els_pkc/doc/mcxn/html/a00768.html new file mode 100644 index 000000000..db4ac2bdd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00768.html @@ -0,0 +1,250 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Types_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
+ +
+
+Data Structures | +Macros | +Typedefs
+
+
mcuxClEls_Types_Types
mcuxClEls » mcuxClEls_Types
+
+
+ +

Defines all types of mcuxClEls_Types. +More...

+ + + + + +

+Data Structures

union  mcuxClEls_KeyProp_t
 Type for ELS key store key properties. More...
 
+ + + + +

+Macros

#define utlpsms
 Deprecated name for mcuxClEls_KeyProp_t.utlspms. More...
 
+ + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClEls_Status_t
 Type for ELS driver status codes. More...
 
typedef mcuxClEls_Status_t mcuxClEls_Status_Protected_t
 Deprecated type for ELS driver protected status codes. More...
 
typedef uint32_t mcuxClEls_KeyIndex_t
 Type for ELS keystore indices. More...
 
typedef mcuxClEls_Status_t(* mcuxClEls_TransferToRegisterFunction_t) (uint32_t volatile *pDestRegister, uint8_t const *pSource, size_t sourceLength, void *pCallerData)
 Function type for transfer of data to a memory-mapped register. More...
 
+

Detailed Description

+

Defines all types of mcuxClEls_Types.

+

Macro Definition Documentation

+ +

◆ utlpsms

+ +
+
+ + + + +
#define utlpsms
+
+ +

Deprecated name for mcuxClEls_KeyProp_t.utlspms.

+ +
+
+

Typedef Documentation

+ +

◆ mcuxClEls_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClEls_Status_t
+
+ +

Type for ELS driver status codes.

+ +
+
+ +

◆ mcuxClEls_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClEls_Status_t mcuxClEls_Status_Protected_t
+
+ +

Deprecated type for ELS driver protected status codes.

+ +
+
+ +

◆ mcuxClEls_KeyIndex_t

+ +
+
+ + + + +
typedef uint32_t mcuxClEls_KeyIndex_t
+
+ +

Type for ELS keystore indices.

+ +
+
+ +

◆ mcuxClEls_TransferToRegisterFunction_t

+ +
+
+ + + + +
typedef mcuxClEls_Status_t(* mcuxClEls_TransferToRegisterFunction_t) (uint32_t volatile *pDestRegister, uint8_t const *pSource, size_t sourceLength, void *pCallerData)
+
+ +

Function type for transfer of data to a memory-mapped register.

+

This function type is used as a callback for handling data transfer from memory to a memory-mapped register. Such a function shall read data from the uint8_t array source, and write data via a sequence of writes to destRegister. Further specification of this function's behavior can be found in the documentation of the function that accepts this function as a callback parameter.

+
Parameters
+ + + + + +
[out]pDestRegisterMemory-mapped register that the output data shall be written to
[in]pSourceArray containing the input data
[in]sourceLengthSize of source in bytes
[in,out]pCallerDataCustom pointer that is provided by the caller and forwarded to the callback function by the operation
+
+
+
Returns
An error code that can be any error code in MCUXCLELS_STATUS_, see individual documentation for more information
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00768.js b/components/els_pkc/doc/mcxn/html/a00768.js new file mode 100644 index 000000000..429b436d0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00768.js @@ -0,0 +1,40 @@ +var a00768 = +[ + [ "mcuxClEls_KeyProp_t", "a01237.html", [ + [ "value", "a01237.html#af184a952f255348629f27f24c0fd0bd9", null ], + [ "word", "a01237.html#a270029567d10cf5d46c68f3fd5762394", null ], + [ "ksize", "a01237.html#a49806c0136f41b701675799cb69d34d5", null ], + [ "__pad0__", "a01237.html#aef07ed5cdd67e69b2862d98fa9ce2bf2", null ], + [ "kactv", "a01237.html#ad0617bc9eea63043b1faf5fe9814ba97", null ], + [ "kbase", "a01237.html#ac8a7a5dac0515241438c5086d60ffcd2", null ], + [ "fgp", "a01237.html#af8743c57bd6d9dd9f329b5cafa3f5c0c", null ], + [ "frtn", "a01237.html#a6e2122f7d4c2706f56ec7fba67042206", null ], + [ "fhwo", "a01237.html#a0c56a02caf693cda953b333b89a51389", null ], + [ "__pad1__", "a01237.html#aba08650854846dd1ef4788c1a8ef0c58", null ], + [ "ucmac", "a01237.html#acceecb25ef42cd4017edfc9095272b3d", null ], + [ "uksk", "a01237.html#a1c20ef8f869a090cc90472821adba513", null ], + [ "urtf", "a01237.html#a32ac519b2729fc88babaaf23ecfb6523", null ], + [ "uckdf", "a01237.html#a3bdb1b36f76fe81225b14896d3429147", null ], + [ "uhkdf", "a01237.html#a983d6a05d50a4e6eeb929ecfab1c5ca0", null ], + [ "uecsg", "a01237.html#adb18f3c09ac78e8d74f2ff9563da084b", null ], + [ "uecdh", "a01237.html#af513bad0dfe63b94b601adae2590ef17", null ], + [ "uaes", "a01237.html#a18d3c3d356100d7bd01a9950c1f7b81e", null ], + [ "uhmac", "a01237.html#ae8e6215c6390b64024f5bb71d09013a6", null ], + [ "ukwk", "a01237.html#a006a40e53f4859e41e4b4ec5424c6c26", null ], + [ "ukuok", "a01237.html#ab0fe394151ed388fa03198d5710bc0d1", null ], + [ "utlspms", "a01237.html#a30f2161747c56e0de99561d38885be7e", null ], + [ "utlsms", "a01237.html#a5f7b5dc8e882536c83ff87ac246ca6ed", null ], + [ "ukgsrc", "a01237.html#ac4fbcd8af04b845353857e27ae6e90b8", null ], + [ "uhwo", "a01237.html#a08b731503e03ee90d1904cbb88e9c37c", null ], + [ "wrpok", "a01237.html#a8b01f95eb9069953fe7a48b6ec85e479", null ], + [ "duk", "a01237.html#ab8a152b213978003ebb149be0c0ae5a7", null ], + [ "upprot_priv", "a01237.html#a50d3bbaabf919fab908e2ae83fe5a5ab", null ], + [ "upprot_sec", "a01237.html#a0d130be83d337e7a5d9ef56f4a92f3a0", null ], + [ "bits", "a01237.html#abcae2eaaf0826e5548f0b416ecfff0b4", null ] + ] ], + [ "utlpsms", "a00768.html#ga0056d58adc14ddca2f9eee45575393a8", null ], + [ "mcuxClEls_Status_t", "a00768.html#ga734d7200290fe0eda6ef3347f52177f3", null ], + [ "mcuxClEls_Status_Protected_t", "a00768.html#ga9d1e537d1dc0c3eda9c26ba9e82e0596", null ], + [ "mcuxClEls_KeyIndex_t", "a00768.html#ga769227492b28ef0d58a94b202113cee8", null ], + [ "mcuxClEls_TransferToRegisterFunction_t", "a00768.html#gacb342d252ea80b11e90b781c5e1aa331", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00769.html b/components/els_pkc/doc/mcxn/html/a00769.html new file mode 100644 index 000000000..6aee32ff6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00769.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: mcuxClHash + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClHash
+
+
+ +

Hash component. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClHash_Constants
 Constants of mcuxClHash component.
 
 mcuxClHash_Functions
 Defines all functions of mcuxClHash.
 
 mcuxClHash_Types
 Defines all types of the mcuxClHash component.
 
+

Detailed Description

+

Hash component.

+

The mcuxClHash component implements the Hash functionality supported by CLNS.

+

An example of how to use the mcuxClHash component can be found in /mcuxClHash/ex.

+

The mcuxClHash component supports interfaces to either hash a message in one shot (mcuxClHash_compute) or to hash it in parts (mcuxClHash_init, mcuxClHash_process, and mcuxClHash_finish). In case of hashing a message in parts, first an initialization has to be performed (mcuxClHash_init), followed by zero, one, or multiple updates (mcuxClHash_process), followed by a finalization (mcuxClHash_finish). The finalization generates the output data (digest) and destroys the context. After the finalization step, no further updates are possible.

+

The targeted hash algorithm is selected by passing one of the offered algorithm mode descriptors (mcuxClHash_Modes), which are listed in file mcuxClHash_Algorithms.h

+

Note: In case the hashing functionality is based on a hardware co-processor, it might be necessary to initialize the co-processor, before it's use in the mcuxClHash component. Please refer to the example for further information on this.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00769.js b/components/els_pkc/doc/mcxn/html/a00769.js new file mode 100644 index 000000000..9a652edf7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00769.js @@ -0,0 +1,6 @@ +var a00769 = +[ + [ "mcuxClHash_Constants", "a00770.html", "a00770" ], + [ "mcuxClHash_Functions", "a00772.html", "a00772" ], + [ "mcuxClHash_Types", "a00773.html", "a00773" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00770.html b/components/els_pkc/doc/mcxn/html/a00770.html new file mode 100644 index 000000000..7ac587e9d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00770.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClHash_Constants
mcuxClHash
+
+
+ +

Constants of mcuxClHash component. +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 MCUXCLHASH_STATUS_
 Return code definitions.
 
 mcuxClHashModes_Algorithms
 Hashing algorithms of the mcuxClHashModes component.
 
 MCUXCLHASH_OUTPUT_SIZE_
 Defines for digest sizes.
 
 mcuxClHashModes_WoarkareaConsumption
 Definitions of workarea sizes for the mcuxClHashModes functions.
 
 mcuxClHashModes_ContextSize
 Definitions of context sizes and state sizes for extraction of states of a hash operation.
 
+

Detailed Description

+

Constants of mcuxClHash component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00770.js b/components/els_pkc/doc/mcxn/html/a00770.js new file mode 100644 index 000000000..644a14445 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00770.js @@ -0,0 +1,8 @@ +var a00770 = +[ + [ "MCUXCLHASH_STATUS_", "a00771.html", "a00771" ], + [ "mcuxClHashModes_Algorithms", "a00774.html", "a00774" ], + [ "MCUXCLHASH_OUTPUT_SIZE_", "a00775.html", "a00775" ], + [ "mcuxClHashModes_WoarkareaConsumption", "a00776.html", "a00776" ], + [ "mcuxClHashModes_ContextSize", "a00777.html", "a00777" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00771.html b/components/els_pkc/doc/mcxn/html/a00771.html new file mode 100644 index 000000000..17abe24f4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00771.html @@ -0,0 +1,348 @@ + + + + + + + +MCUX CLNS: MCUXCLHASH_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLHASH_STATUS_
mcuxClHash » mcuxClHash_Constants
+
+
+ +

Return code definitions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_STATUS_OK
 Hash operation successful. More...
 
#define MCUXCLHASH_STATUS_COMPARE_EQUAL
 Hash operation and comparison of result successful. More...
 
#define MCUXCLHASH_COMPARE_EQUAL
 
#define MCUXCLHASH_STATUS_FAILURE
 Hash operation failed. More...
 
#define MCUXCLHASH_FAILURE
 
#define MCUXCLHASH_STATUS_INVALID_PARAMS
 Hash function called with invalid parameters. More...
 
#define MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
 Export on state, for which a NON-multiple of the blocksize has been hashed. More...
 
#define MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
 
#define MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL
 Hash operation succeeded, but comparison of result failed. More...
 
#define MCUXCLHASH_COMPARE_NOT_EQUAL
 
#define MCUXCLHASH_STATUS_FULL
 Hash operation failed because the total input size exceeds the upper limit. More...
 
#define MCUXCLHASH_STATUS_FAULT_ATTACK
 Fault attack (unexpected behavior) detected. More...
 
+

Detailed Description

+

Return code definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLHASH_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_OK
+
+ +

Hash operation successful.

+ +
+
+ +

◆ MCUXCLHASH_STATUS_COMPARE_EQUAL

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_COMPARE_EQUAL
+
+ +

Hash operation and comparison of result successful.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_EQUAL

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_EQUAL
+
+ +
+
+ +

◆ MCUXCLHASH_STATUS_FAILURE

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_FAILURE
+
+ +

Hash operation failed.

+ +
+
+ +

◆ MCUXCLHASH_FAILURE

+ +
+
+ + + + +
#define MCUXCLHASH_FAILURE
+
+ +
+
+ +

◆ MCUXCLHASH_STATUS_INVALID_PARAMS

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_INVALID_PARAMS
+
+ +

Hash function called with invalid parameters.

+ +
+
+ +

◆ MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
+
+ +

Export on state, for which a NON-multiple of the blocksize has been hashed.

+ +
+
+ +

◆ MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK

+ +
+
+ + + + +
#define MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK
+
+ +
+
+ +

◆ MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL
+
+ +

Hash operation succeeded, but comparison of result failed.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_NOT_EQUAL

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_NOT_EQUAL
+
+ +
+
+ +

◆ MCUXCLHASH_STATUS_FULL

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_FULL
+
+ +

Hash operation failed because the total input size exceeds the upper limit.

+ +
+
+ +

◆ MCUXCLHASH_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLHASH_STATUS_FAULT_ATTACK
+
+ +

Fault attack (unexpected behavior) detected.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00771.js b/components/els_pkc/doc/mcxn/html/a00771.js new file mode 100644 index 000000000..4ce125915 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00771.js @@ -0,0 +1,15 @@ +var a00771 = +[ + [ "MCUXCLHASH_STATUS_OK", "a00771.html#gadf29410b02d95357d48a3ba443558da4", null ], + [ "MCUXCLHASH_STATUS_COMPARE_EQUAL", "a00771.html#gaaf06d7932b91cce6e94312a534f61934", null ], + [ "MCUXCLHASH_COMPARE_EQUAL", "a00771.html#ga05eaccf399e17f323499f31e764d5173", null ], + [ "MCUXCLHASH_STATUS_FAILURE", "a00771.html#ga377eaddc82740c4c4590688c754f78a0", null ], + [ "MCUXCLHASH_FAILURE", "a00771.html#gaaef282127a4c3c3e8f9a034cba1b70e0", null ], + [ "MCUXCLHASH_STATUS_INVALID_PARAMS", "a00771.html#ga6cd095f16a5ff26877cc877cecbd0e2b", null ], + [ "MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK", "a00771.html#gabeb9fdba3834bd6d1b62b53d0b981bb9", null ], + [ "MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK", "a00771.html#ga5cb4d265e6848270e5a3e38b5e57e84a", null ], + [ "MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL", "a00771.html#gad39c265fd8728f3287eeef999cfeb599", null ], + [ "MCUXCLHASH_COMPARE_NOT_EQUAL", "a00771.html#ga647cd722111188a5d028d1f3ab4eb795", null ], + [ "MCUXCLHASH_STATUS_FULL", "a00771.html#ga9abcd3d90166d6f4fd532d8b7c24931f", null ], + [ "MCUXCLHASH_STATUS_FAULT_ATTACK", "a00771.html#gaca3624d074b137e5587052f6ffb1b6f6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00772.html b/components/els_pkc/doc/mcxn/html/a00772.html new file mode 100644 index 000000000..dc15a4228 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00772.html @@ -0,0 +1,403 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClHash_Functions
mcuxClHash
+
+
+ +

Defines all functions of mcuxClHash. +More...

+ + + + + + + + + + + + + + +

+Functions

mcuxClHash_Status_t mcuxClHash_compute (mcuxClSession_Handle_t session, mcuxClHash_Algo_t algorithm, mcuxCl_InputBuffer_t pIn, uint32_t inSize, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
 One-shot Hash computation function. More...
 
mcuxClHash_Status_t mcuxClHash_init (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxClHash_Algo_t algorithm)
 Multi-part Hash initialization function. More...
 
mcuxClHash_Status_t mcuxClHash_process (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_InputBuffer_t pIn, uint32_t inSize)
 Multi-part Hash processing function. More...
 
mcuxClHash_Status_t mcuxClHash_finish (mcuxClSession_Handle_t session, mcuxClHash_Context_t pContext, mcuxCl_Buffer_t pOut, uint32_t *const pOutSize)
 Multi-part Hash computation finalization function. More...
 
+

Detailed Description

+

Defines all functions of mcuxClHash.

+

Function Documentation

+ +

◆ mcuxClHash_compute()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClHash_Status_t mcuxClHash_compute (mcuxClSession_Handle_t session,
mcuxClHash_Algo_t algorithm,
mcuxCl_InputBuffer_t pIn,
uint32_t inSize,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutSize 
)
+
+ +

One-shot Hash computation function.

+

This function performs a hash computation over the input message pIn, using the hash function provided by the algorithm input parameter, in one shot. Up to 2^32 bytes of data can be hashed with this function.

+

For example, to perform a SHA256 computation, the following needs to be provided:

    +
  • SHA256 algorithm
    • +
  • Input data
    • +
  • Output hash buffer
    • +
+

The input parameter session has to be initialized by the function mcuxClSession_init prior to calling this function. (MCUXCL_FEATURE_SESSION_HAS_RTF)

+
Parameters
+ + + + + + + +
[in/out]session Handle for the current CL session.
[in]algorithmHash algorithm that should be used during the computation.
[in]pInPointer to the input buffer that contains the data that needs to be hashed.
[in]inSizeNumber of bytes of data in the pIn buffer.
[out]pOutPointer to the output buffer where the computed hash value is written.
[out]pOutSizeWill be incremented by the number of bytes of data that have been written to the pOut buffer.
+
+
+
Returns
status
+
Return values
+ + + + + +
MCUXCLHASH_STATUS_OKHash operation successful
MCUXCLHASH_STATUS_FAILUREError occured during Hash operation
MCUXCLHASH_STATUS_INVALID_PARAMSThe provided function parameters do not fulfill requirements
MCUXCLHASH_STATUS_FAULT_ATTACKA fault attack was detected
+
+
+ +
+
+ +

◆ mcuxClHash_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClHash_Status_t mcuxClHash_init (mcuxClSession_Handle_t session,
mcuxClHash_Context_t pContext,
mcuxClHash_Algo_t algorithm 
)
+
+ +

Multi-part Hash initialization function.

+

This function performs the initialization for a multi-part hash operation.

+
Parameters
+ + + + +
[in/out]session Handle for the current CL session.
[out]pContextHash context which is used to maintain the state and store other relevant information about the operation.
[in]algorithmHash algorithm that should be used during the computation operation.
+
+
+
Returns
status
+
Return values
+ + + +
MCUXCLHASH_STATUS_OKInitialization successful
MCUXCLHASH_STATUS_FAILUREError occurred during initialization function
+
+
+ +
+
+ +

◆ mcuxClHash_process()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClHash_Status_t mcuxClHash_process (mcuxClSession_Handle_t session,
mcuxClHash_Context_t pContext,
mcuxCl_InputBuffer_t pIn,
uint32_t inSize 
)
+
+ +

Multi-part Hash processing function.

+

This function performs the processing of (a part of) a data stream for a Hash operation. The algorithm to be used will be determined based on the context that is provided.

+
Parameters
+ + + + + +
[in/out]session Handle for the current CL session.
[in/out]pContext Hash context which is used to maintain the state and store other relevant information about the operation.
[in]pInPointer to the input buffer that contains the data that needs to be processed.
[in]inSizeNumber of bytes of data in the pIn buffer.
+
+
+
Returns
status
+
Return values
+ + + + + +
MCUXCLHASH_STATUS_OKHash operation successful
MCUXCLHASH_STATUS_FAILUREError occurred during Hash operation
MCUXCLHASH_STATUS_INVALID_PARAMSThe provided function parameters do not fulfill requirements
MCUXCLHASH_STATUS_FAULT_ATTACKA fault attack was detected
+
+
+ +
+
+ +

◆ mcuxClHash_finish()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClHash_Status_t mcuxClHash_finish (mcuxClSession_Handle_t session,
mcuxClHash_Context_t pContext,
mcuxCl_Buffer_t pOut,
uint32_t *const pOutSize 
)
+
+ +

Multi-part Hash computation finalization function.

+

This function performs the finalization of a Hash computation operation. The algorithm to be used will be determined based on the context that is provided

+
Parameters
+ + + + + +
[in/out]session Handle for the current CL session.
[in/out]pContext Hash context which is used to maintain the state and store other relevant information about the operation.
[out]pOutPointer to the output buffer where the computed hash value needs to be written.
[out]pOutSizeWill be incremented by the number of bytes of data that have been written to the pOut buffer.
+
+
+
Returns
status
+
Return values
+ + + + + +
MCUXCLHASH_STATUS_OKHash operation successful
MCUXCLHASH_STATUS_FAILUREError occurred during Hash operation
MCUXCLHASH_STATUS_INVALID_PARAMSThe provided function parameters do not fulfill requirements
MCUXCLHASH_STATUS_FAULT_ATTACKA fault attack was detected
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00772.js b/components/els_pkc/doc/mcxn/html/a00772.js new file mode 100644 index 000000000..2d9cf918b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00772.js @@ -0,0 +1,7 @@ +var a00772 = +[ + [ "mcuxClHash_compute", "a00772.html#ga7beb1bb4063eae682eca700efeba93db", null ], + [ "mcuxClHash_init", "a00772.html#ga68263436904cf849bfbe8c9b1f6542d4", null ], + [ "mcuxClHash_process", "a00772.html#ga49bdf3dca9746328fe58e6d5859e92eb", null ], + [ "mcuxClHash_finish", "a00772.html#gad55cc3a702b915f84d9cd2e94c2b7f6b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00773.html b/components/els_pkc/doc/mcxn/html/a00773.html new file mode 100644 index 000000000..c1b14a946 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00773.html @@ -0,0 +1,232 @@ + + + + + + + +MCUX CLNS: mcuxClHash_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClHash_Types
mcuxClHash
+
+
+ +

Defines all types of the mcuxClHash component. +More...

+ + + + + + + + + + + + + + + + + +

+Typedefs

typedef struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
 Hash mode/algorithm descriptor type. More...
 
typedef const mcuxClHash_AlgorithmDescriptor_t *const mcuxClHash_Algo_t
 Hash mode/algorithm type. More...
 
typedef struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t
 Hash Context buffer type. More...
 
typedef mcuxClHash_ContextDescriptor_t *const mcuxClHash_Context_t
 Hash Context type. More...
 
typedef uint32_t mcuxClHash_Status_t
 Hash Status type. More...
 
+

Detailed Description

+

Defines all types of the mcuxClHash component.

+

Typedef Documentation

+ +

◆ mcuxClHash_AlgorithmDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t
+
+ +

Hash mode/algorithm descriptor type.

+

This type captures all the information that the Hash interfaces need to know about a particular Hash mode/algorithm.

+ +
+
+ +

◆ mcuxClHash_Algo_t

+ +
+
+ + + + +
typedef const mcuxClHash_AlgorithmDescriptor_t* const mcuxClHash_Algo_t
+
+ +

Hash mode/algorithm type.

+

This type is used to refer to a Hash mode/algorithm.

+ +
+
+ +

◆ mcuxClHash_ContextDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t
+
+ +

Hash Context buffer type.

+

This type is used in the streaming interfaces to store the information about the current operation and the relevant internal state.

+ +
+
+ +

◆ mcuxClHash_Context_t

+ +
+
+ + + + +
typedef mcuxClHash_ContextDescriptor_t* const mcuxClHash_Context_t
+
+ +

Hash Context type.

+

This type is used to refer to the Hash context. It needs to be placed at a 64 Bit-aligned address.

+ +
+
+ +

◆ mcuxClHash_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClHash_Status_t
+
+ +

Hash Status type.

+

This type is used for hash return values: mcuxClHashStatusValues

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00773.js b/components/els_pkc/doc/mcxn/html/a00773.js new file mode 100644 index 000000000..b9c6d9e99 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00773.js @@ -0,0 +1,8 @@ +var a00773 = +[ + [ "mcuxClHash_AlgorithmDescriptor_t", "a00773.html#gacccec0a811d221d2cb0fd8416da271d8", null ], + [ "mcuxClHash_Algo_t", "a00773.html#ga0ffeeb89c76da6470176e7621713e1b2", null ], + [ "mcuxClHash_ContextDescriptor_t", "a00773.html#ga90ff7c4f43e59b80eca542e35722124c", null ], + [ "mcuxClHash_Context_t", "a00773.html#ga84c437ceb6b43a992b75866f793d0956", null ], + [ "mcuxClHash_Status_t", "a00773.html#gacdfd7a833fcd06684a73c22364e89b7c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00774.html b/components/els_pkc/doc/mcxn/html/a00774.html new file mode 100644 index 000000000..4ab16f907 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00774.html @@ -0,0 +1,324 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_Algorithms + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
mcuxClHashModes_Algorithms
mcuxClHash » mcuxClHash_Constants
+
+
+ +

Hashing algorithms of the mcuxClHashModes component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224
 Sha-224 algorithm descriptor Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224
 Sha-224 algorithm Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256
 Sha-256 algorithm descriptor Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256
 Sha-256 algorithm Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384
 Sha-384 algorithm descriptor Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384
 Sha-384 algorithm Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512
 Sha-512 algorithm descriptor Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512
 Sha-512 algorithm Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. More...
 
+

Detailed Description

+

Hashing algorithms of the mcuxClHashModes component.

+

Variable Documentation

+ +

◆ mcuxClHash_AlgorithmDescriptor_Sha224

+ +
+
+ + + + +
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224
+
+ +

Sha-224 algorithm descriptor Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_Algorithm_Sha224

+ +
+
+ + + + + +
+ + + + +
mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224
+ 		+static
+
+ +

Sha-224 algorithm Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_AlgorithmDescriptor_Sha256

+ +
+
+ + + + +
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256
+
+ +

Sha-256 algorithm descriptor Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_Algorithm_Sha256

+ +
+
+ + + + + +
+ + + + +
mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256
+ 		+static
+
+ +

Sha-256 algorithm Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_AlgorithmDescriptor_Sha384

+ +
+
+ + + + +
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384
+
+ +

Sha-384 algorithm descriptor Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_Algorithm_Sha384

+ +
+
+ + + + + +
+ + + + +
mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384
+ 		+static
+
+ +

Sha-384 algorithm Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_AlgorithmDescriptor_Sha512

+ +
+
+ + + + +
const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512
+
+ +

Sha-512 algorithm descriptor Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+ +

◆ mcuxClHash_Algorithm_Sha512

+ +
+
+ + + + + +
+ + + + +
mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512
+ 		+static
+
+ +

Sha-512 algorithm Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF.

+

SHA-direct mode has to be disabled prior to using this algorithm

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00774.js b/components/els_pkc/doc/mcxn/html/a00774.js new file mode 100644 index 000000000..91031ae80 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00774.js @@ -0,0 +1,11 @@ +var a00774 = +[ + [ "mcuxClHash_AlgorithmDescriptor_Sha224", "a00774.html#ga56d71cf5a53a9e64a648c4d9776efa8e", null ], + [ "mcuxClHash_Algorithm_Sha224", "a00774.html#ga4de6a5917dc46d3aae22f93df66fc228", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha256", "a00774.html#ga0332b3c0540cd1761dfaa17b33f02f02", null ], + [ "mcuxClHash_Algorithm_Sha256", "a00774.html#ga672407195f718d55fcee73d1dfb7c623", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha384", "a00774.html#ga18de1261f5761dfc43ef89a102fda259", null ], + [ "mcuxClHash_Algorithm_Sha384", "a00774.html#gaa7389b8db9ec5c97b44db899e2b9f8db", null ], + [ "mcuxClHash_AlgorithmDescriptor_Sha512", "a00774.html#ga50a5ce5101cf1175127bdf1ea7bfb0e1", null ], + [ "mcuxClHash_Algorithm_Sha512", "a00774.html#gae0687309bef869b41302594c6c934d9a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00775.html b/components/els_pkc/doc/mcxn/html/a00775.html new file mode 100644 index 000000000..7923ceea3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00775.html @@ -0,0 +1,455 @@ + + + + + + + +MCUX CLNS: MCUXCLHASH_OUTPUT_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLHASH_OUTPUT_SIZE_
mcuxClHash » mcuxClHash_Constants
+
+
+ +

Defines for digest sizes. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_OUTPUT_SIZE_MD5
 MD5 output size: 128 bit (16 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_1
 SHA-1 output size: 160 bit (20 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_224
 SHA-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_256
 SHA-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_384
 SHA-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512
 SHA-512 output size: 512 bit (64 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_224
 SHA-512/224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_256
 SHA-512/256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_224
 SHA3-224 output size: 224 bit (28 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_256
 SHA3-256 output size: 256 bit (32 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_384
 SHA3-384 output size: 384 bit (48 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_512
 SHA3-512 output size: 512 bit (64 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128
 SHA3-SHAKE 128 output size: 1344 bit (168 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256
 SHA3-SHAKE 256 output size: 1088 bit (136 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128
 SHA3-CSHAKE 128 output size: 1344 bit (168 bytes) More...
 
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256
 SHA3-CSHAKE 256 output size: 1088 bit (136 bytes) More...
 
#define MCUXCLHASH_MAX_OUTPUT_SIZE
 Maximum output size. More...
 
+

Detailed Description

+

Defines for digest sizes.

+

Macro Definition Documentation

+ +

◆ MCUXCLHASH_OUTPUT_SIZE_MD5

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_MD5
+
+ +

MD5 output size: 128 bit (16 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_1

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_1
+
+ +

SHA-1 output size: 160 bit (20 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_224

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_224
+
+ +

SHA-224 output size: 224 bit (28 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_256

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_256
+
+ +

SHA-256 output size: 256 bit (32 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_384

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_384
+
+ +

SHA-384 output size: 384 bit (48 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_512

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512
+
+ +

SHA-512 output size: 512 bit (64 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_224
+
+ +

SHA-512/224 output size: 224 bit (28 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_256
+
+ +

SHA-512/256 output size: 256 bit (32 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_224

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_224
+
+ +

SHA3-224 output size: 224 bit (28 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_256

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_256
+
+ +

SHA3-256 output size: 256 bit (32 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_384

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_384
+
+ +

SHA3-384 output size: 384 bit (48 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_512

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_512
+
+ +

SHA3-512 output size: 512 bit (64 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128
+
+ +

SHA3-SHAKE 128 output size: 1344 bit (168 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256
+
+ +

SHA3-SHAKE 256 output size: 1088 bit (136 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128
+
+ +

SHA3-CSHAKE 128 output size: 1344 bit (168 bytes)

+ +
+
+ +

◆ MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256

+ +
+
+ + + + +
#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256
+
+ +

SHA3-CSHAKE 256 output size: 1088 bit (136 bytes)

+ +
+
+ +

◆ MCUXCLHASH_MAX_OUTPUT_SIZE

+ +
+
+ + + + +
#define MCUXCLHASH_MAX_OUTPUT_SIZE
+
+ +

Maximum output size.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00775.js b/components/els_pkc/doc/mcxn/html/a00775.js new file mode 100644 index 000000000..bd1c8330e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00775.js @@ -0,0 +1,20 @@ +var a00775 = +[ + [ "MCUXCLHASH_OUTPUT_SIZE_MD5", "a00775.html#gafe7e3fec63db293d11223cf996b0f933", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_1", "a00775.html#ga8e6f2196aa9cc22514327290e9c6d265", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_224", "a00775.html#ga4f3a086ffb19f8127e04dd2e9c458a48", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_256", "a00775.html#gaf4d4bd473c10a1c0e474dfa6ebad83d3", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_384", "a00775.html#gad9f68a357e04e78a8930ae8575d2fb95", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512", "a00775.html#gab3854625bf1807c8be0d0eda40c9b15c", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512_224", "a00775.html#ga2b26c1ca0f30feb3c3e12f97ca433935", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA_512_256", "a00775.html#ga106037a11d7e73694703696f1cbd9b8a", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_224", "a00775.html#ga9b455baf1195244a5a21f95d24d1bb78", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_256", "a00775.html#ga2d4ce7c5407c45486781710968933d59", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_384", "a00775.html#ga9ba519f3947e62fe3c33ba89912415f2", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_512", "a00775.html#ga98c0f235847458f6e0785ce7e1fa4de1", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128", "a00775.html#gaf92c4c2afd86cf0276655d833fc92946", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256", "a00775.html#ga6208318273d199569492d2df54285bfb", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128", "a00775.html#gabee2279c4070bb6e490acc465d19f7b1", null ], + [ "MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256", "a00775.html#ga1310682860222f35228b9b69e9110b7b", null ], + [ "MCUXCLHASH_MAX_OUTPUT_SIZE", "a00775.html#ga1be4781928bd9fa5aa9ea9fc9140320b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00776.html b/components/els_pkc/doc/mcxn/html/a00776.html new file mode 100644 index 000000000..452cfb073 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00776.html @@ -0,0 +1,702 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_WoarkareaConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHashModes_WoarkareaConsumption
mcuxClHash » mcuxClHash_Constants
+
+
+ +

Definitions of workarea sizes for the mcuxClHashModes functions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_compute on SHA2-224. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_compare on SHA2-224. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_process on SHA2-224. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_finish on SHA2-224. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224
 Defines the workarea size required for mcuxClHash_verify on SHA2-224. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_compute on SHA2-256. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_compare on SHA2-256. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_process on SHA2-256. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_finish on SHA2-256. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256
 Defines the workarea size required for mcuxClHash_verify on SHA2-256. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_compute on SHA2-384. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_compare on SHA2-384. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_process on SHA2-384. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_finish on SHA2-384. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384
 Defines the workarea size required for mcuxClHash_verify on SHA2-384. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_compute on SHA2-512. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_compute on SHA2-512/224. More...
 
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_compute on SHA2-512/256. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_compare on SHA2-512. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_compare on SHA2-512/224. More...
 
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_compare on SHA2-512/256. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_process on SHA2-512. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_process on SHA2-512/224. More...
 
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_process on SHA2-512/256. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_finish on SHA2-512. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_finish on SHA2-512/224. More...
 
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_finish on SHA2-512/256. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512
 Defines the workarea size required for mcuxClHash_verify on SHA2-512. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224
 Defines the workarea size required for mcuxClHash_verify on SHA2-512/224. More...
 
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256
 Defines the workarea size required for mcuxClHash_verify on SHA2-512/256. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClHashModes functions.

+

Macro Definition Documentation

+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-512.

+ +
+
+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-512/224.

+ +
+
+ +

◆ MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256
+
+ +

Defines the workarea size required for mcuxClHash_compute on SHA2-512/256.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-512.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-512/224.

+ +
+
+ +

◆ MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256
+
+ +

Defines the workarea size required for mcuxClHash_compare on SHA2-512/256.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-512.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-512/224.

+ +
+
+ +

◆ MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256
+
+ +

Defines the workarea size required for mcuxClHash_process on SHA2-512/256.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-512.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-512/224.

+ +
+
+ +

◆ MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256
+
+ +

Defines the workarea size required for mcuxClHash_finish on SHA2-512/256.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-512.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-512/224.

+ +
+
+ +

◆ MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256

+ +
+
+ + + + +
#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256
+
+ +

Defines the workarea size required for mcuxClHash_verify on SHA2-512/256.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00776.js b/components/els_pkc/doc/mcxn/html/a00776.js new file mode 100644 index 000000000..5cf028054 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00776.js @@ -0,0 +1,33 @@ +var a00776 = +[ + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga40b9eff6f42215fc5c98c0513fbd2c79", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga8ff96915814df592db3d68d925408a98", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#ga2ff77f524496774f46c5294dfc7619bf", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#gae23cdd9e00a486600ee5b90949f3842f", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224", "a00776.html#gabf598385358401cea01d065d9d421d87", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga0ebf52b4105a30badc619e7ba70193b3", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#gaa98512fd1ef5f7d8310a811035811fbb", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga6a38dced70e095517b706930b2c164c4", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#ga7e0a2938cc503a204da719c7b8aab627", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256", "a00776.html#gaf0e29b1e66d6d5a8af6b4c20ec5bb85e", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga55b9dabdce9439ad6fec034dc86ead8c", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#gaa4c0e341d16ed5fe2be37691f582e326", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#gaeca1828134728d6d1d7da343711934e6", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga64ac4667e73071d261d273b72abc70d9", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384", "a00776.html#ga2dc773fc49bfd2c5dd1fc298a3dadb35", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#gaa7b677e561a919060c8c1eae1c5f2455", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#gaa1ea090ae23f0e04f553cdfbeb2573a9", null ], + [ "MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#gac7c04d4fd538f29eb200ae68a076853e", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga762efcb01b7aaf95266adfb3c9b174b0", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga6dbc0f41ec9388bbc8aeb99e2ee37230", null ], + [ "MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga3e3ada3faaecda7fbef060e2c3e835f8", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#gac571e29844bf3dc2cd052c28e40dc90e", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#gab081523fa0e85169ed405bd514f0e318", null ], + [ "MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#gac38cbbdbd0ae6c935f09f75ba51bf8de", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga0b23abb47f314adac81fa08cabded273", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga1d3671a1c73c8ef559ac12b3206ab952", null ], + [ "MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga95fcec323ebd8dbfddc56a99e6f49900", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512", "a00776.html#ga50e9da09a4a92534775a94da69c17b48", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224", "a00776.html#ga9e3c10d8b549eba86ff96332417ecbdb", null ], + [ "MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256", "a00776.html#ga000d10c6a9b9475289a7ff08cb283394", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00777.html b/components/els_pkc/doc/mcxn/html/a00777.html new file mode 100644 index 000000000..83376e944 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00777.html @@ -0,0 +1,220 @@ + + + + + + + +MCUX CLNS: mcuxClHashModes_ContextSize + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHashModes_ContextSize
mcuxClHash » mcuxClHash_Constants
+
+
+ +

Definitions of context sizes and state sizes for extraction of states of a hash operation. +More...

+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_224_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224
 Defines the state size required for SHA2-224. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256
 Defines the state size required for SHA2-256. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_384_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384
 Defines the state size required for SHA2-384. More...
 
+#define MCUXCLHASH_CONTEXT_SIZE_SHA2_512_IN_WORDS
 
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512
 Defines the state size required for SHA2-512. More...
 
+

Detailed Description

+

Definitions of context sizes and state sizes for extraction of states of a hash operation.

+

Macro Definition Documentation

+ +

◆ MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224

+ +
+
+ + + + +
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224
+
+ +

Defines the state size required for SHA2-224.

+ +
+
+ +

◆ MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256

+ +
+
+ + + + +
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256
+
+ +

Defines the state size required for SHA2-256.

+ +
+
+ +

◆ MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384

+ +
+
+ + + + +
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384
+
+ +

Defines the state size required for SHA2-384.

+ +
+
+ +

◆ MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512

+ +
+
+ + + + +
#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512
+
+ +

Defines the state size required for SHA2-512.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00777.js b/components/els_pkc/doc/mcxn/html/a00777.js new file mode 100644 index 000000000..e3f0ab4f9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00777.js @@ -0,0 +1,7 @@ +var a00777 = +[ + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224", "a00777.html#ga64ea4a6c44d5714d06cde9c858ca963f", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256", "a00777.html#gac40907ce6e09e87b7931823ad48a50c3", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384", "a00777.html#ga09b5656067c3ab3e89c3d0aaa9f2e5ad", null ], + [ "MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512", "a00777.html#gad09b3d78d2a33f965308f2e4c34ea0cf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00778.html b/components/els_pkc/doc/mcxn/html/a00778.html new file mode 100644 index 000000000..d2fee5fb8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00778.html @@ -0,0 +1,192 @@ + + + + + + + +MCUX CLNS: mcuxClHmac Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClHmac Constants
MCUX CL &ndash; API » HMAC Modes API
+
+
+ +

Constants of HMAC Modes API component. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLHMAC_ELS_OUTPUT_SIZE
 
+#define MCUXCLHMAC_ELS_OUTPUT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_MAX_OUTPUT_SIZE
 
+#define MCUXCLHMAC_MAX_OUTPUT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_ELS_BLOCK_SIZE
 
+#define MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD
 
#define MCUXCLHMAC_ELS_MIN_PADDING_LENGTH
 Size of minimum HMAC padding length. More...
 
#define MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH(dataLength)
 Formula to calculate input buffer size for HMAC with SHA-256. More...
 
+

Detailed Description

+

Constants of HMAC Modes API component.

+

Macro Definition Documentation

+ +

◆ MCUXCLHMAC_ELS_MIN_PADDING_LENGTH

+ +
+
+ + + + +
#define MCUXCLHMAC_ELS_MIN_PADDING_LENGTH
+
+ +

Size of minimum HMAC padding length.

+ +
+
+ +

◆ MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH

+ +
+
+ + + + + + + + +
#define MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH( dataLength)
+
+ +

Formula to calculate input buffer size for HMAC with SHA-256.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00778.js b/components/els_pkc/doc/mcxn/html/a00778.js new file mode 100644 index 000000000..36f05a1cf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00778.js @@ -0,0 +1,5 @@ +var a00778 = +[ + [ "MCUXCLHMAC_ELS_MIN_PADDING_LENGTH", "a00778.html#gaeea21ec876a193348d5f78b5014da165", null ], + [ "MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH", "a00778.html#gac9e4d270e79fa637dfac0c4919bf5eda", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00779.html b/components/els_pkc/doc/mcxn/html/a00779.html new file mode 100644 index 000000000..151a68dfa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00779.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClHmac Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+Modules
+
+
mcuxClHmac Functions
MCUX CL &ndash; API » HMAC Modes API
+
+
+ +

Defines all functions of HMAC Modes API. +More...

+ + + + + +

+Modules

 APIs to construct HMAC modes
 Interfaces to construct HMAC modes of operation.
 
+

Detailed Description

+

Defines all functions of HMAC Modes API.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00779.js b/components/els_pkc/doc/mcxn/html/a00779.js new file mode 100644 index 000000000..07ca05df1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00779.js @@ -0,0 +1,4 @@ +var a00779 = +[ + [ "APIs to construct HMAC modes", "a00780.html", "a00780" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00780.html b/components/els_pkc/doc/mcxn/html/a00780.html new file mode 100644 index 000000000..edc0ec5a9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00780.html @@ -0,0 +1,175 @@ + + + + + + + +MCUX CLNS: APIs to construct HMAC modes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+ +
+ +
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+ +
+ +
+
+Functions
+
+
APIs to construct HMAC modes
MCUX CL &ndash; API » HMAC Modes API » mcuxClHmac Functions
+
+
+ +

Interfaces to construct HMAC modes of operation. +More...

+ + + + + +

+Functions

mcuxClMac_Status_t mcuxClHmac_createHmacMode (mcuxClMac_CustomMode_t mode, mcuxClHash_Algo_t hashAlgorithm)
 This function creates a HMAC mode descriptor for software implementations of HMAC. More...
 
+

Detailed Description

+

Interfaces to construct HMAC modes of operation.

+

Function Documentation

+ +

◆ mcuxClHmac_createHmacMode()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClMac_Status_t mcuxClHmac_createHmacMode (mcuxClMac_CustomMode_t mode,
mcuxClHash_Algo_t hashAlgorithm 
)
+
+ +

This function creates a HMAC mode descriptor for software implementations of HMAC.

+

The SW-HMAC modes of operation require additional input, hence a mode descriptor has to be constructed with this function. The resulting descriptor will be written to mode.

+

This function must be called before any SW-HMAC operation is performed.

+
Parameters
+ + + +
mode[out]Pointer to HMAC custom mode to be initialized.
mcuxClHash_Algo_t[in]Pointer to the Hash algorithm descriptor to be used. SecSha algorithm descriptors are not supported.
+
+
+
Returns
status
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00780.js b/components/els_pkc/doc/mcxn/html/a00780.js new file mode 100644 index 000000000..b088734bb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00780.js @@ -0,0 +1,4 @@ +var a00780 = +[ + [ "mcuxClHmac_createHmacMode", "a00780.html#ga43f6d98b6b3b6a6e62263130e2c95a68", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00781.html b/components/els_pkc/doc/mcxn/html/a00781.html new file mode 100644 index 000000000..16ac9f7e3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00781.html @@ -0,0 +1,224 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_KeyTypes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Variables
+
+
mcuxClHmac_KeyTypes
MCUX CL &ndash; API » HMAC Modes API
+
+
+ +

Defines of supported key types of HMAC Modes API, see mcuxClKey. +More...

+ + + + + + + + + + + + + + +

+Variables

const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256
 Key type structure for HMAC-SHA256 based keys. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256
 Key type pointer for HMAC-SHA256 based keys. More...
 
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength
 Key type structure for Sw-HMAC based keys with variable length. More...
 
static const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength
 Key type pointer for HMAC-SHA256 based keys with variable length. More...
 
+

Detailed Description

+

Defines of supported key types of HMAC Modes API, see mcuxClKey.

+

Variable Documentation

+ +

◆ mcuxClKey_TypeDescriptor_HmacSha256

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256
+
+ +

Key type structure for HMAC-SHA256 based keys.

+ +
+
+ +

◆ mcuxClKey_Type_HmacSha256

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256
+ 		+static
+
+ +

Key type pointer for HMAC-SHA256 based keys.

+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_Hmac_variableLength

+ +
+
+ + + + +
const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength
+
+ +

Key type structure for Sw-HMAC based keys with variable length.

+ +
+
+ +

◆ mcuxClKey_Type_Hmac_variableLength

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength
+ 		+static
+
+ +

Key type pointer for HMAC-SHA256 based keys with variable length.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00781.js b/components/els_pkc/doc/mcxn/html/a00781.js new file mode 100644 index 000000000..f2fd82fb7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00781.js @@ -0,0 +1,7 @@ +var a00781 = +[ + [ "mcuxClKey_TypeDescriptor_HmacSha256", "a00781.html#gaa7829411660f435c478e54884f9dc235", null ], + [ "mcuxClKey_Type_HmacSha256", "a00781.html#ga6d1ebb714b890c9b193a68edb3038720", null ], + [ "mcuxClKey_TypeDescriptor_Hmac_variableLength", "a00781.html#gae7b0c9b1b7b2c69b0d8c9ac6decdcf1f", null ], + [ "mcuxClKey_Type_Hmac_variableLength", "a00781.html#ga42eb018ca876c87b3d4539532ab2154d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00782.html b/components/els_pkc/doc/mcxn/html/a00782.html new file mode 100644 index 000000000..2f3d731c5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00782.html @@ -0,0 +1,209 @@ + + + + + + + +MCUX CLNS: mcuxClHmac_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros
+
+
mcuxClHmac_MemoryConsumption
MCUX CL &ndash; API » HMAC Modes API
+
+
+ +

Defines the memory consumption for the mcuxClHmac component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLHMAC_SIZE_IN_CPUWORDS(size)
 Helper macro to calculate size aligned to CPU word. More...
 
+#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_SW
 
+#define MCUXCLHMAC_CONTEXT_SIZE_SW_IN_WORDS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_ELS
 
+#define MCUXCLHMAC_CONTEXT_SIZE_ELS_IN_WORDS
 
+#define MCUXCLHMAC_MAX_CONTEXT_SIZE
 
+#define MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS
 
+#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE
 
+#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClHmac component.

+

Macro Definition Documentation

+ +

◆ MCUXCLHMAC_SIZE_IN_CPUWORDS

+ +
+
+ + + + + + + + +
#define MCUXCLHMAC_SIZE_IN_CPUWORDS( size)
+
+ +

Helper macro to calculate size aligned to CPU word.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00782.js b/components/els_pkc/doc/mcxn/html/a00782.js new file mode 100644 index 000000000..5974dd459 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00782.js @@ -0,0 +1,4 @@ +var a00782 = +[ + [ "MCUXCLHMAC_SIZE_IN_CPUWORDS", "a00782.html#ga7ebd777bda72a587fe816238ee14106c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00783.html b/components/els_pkc/doc/mcxn/html/a00783.html new file mode 100644 index 000000000..5ae1a4438 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00783.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: HMAC mode definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
HMAC mode definitions
MCUX CL &ndash; API » HMAC Modes API
+
+
+ +

Modes used by the HMAC operations. +More...

+

Modes used by the HMAC operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00784.html b/components/els_pkc/doc/mcxn/html/a00784.html new file mode 100644 index 000000000..b19fae474 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00784.html @@ -0,0 +1,147 @@ + + + + + + + +MCUX CLNS: mcuxClKey + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Modules
+
+
mcuxClKey
MCUX CL &ndash; API
+
+
+ +

mcuxClKey component +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 mcuxClKey_Macros
 Defines all macros of mcuxClKey.
 
 mcuxClKey_Functions
 Defines all functions of mcuxClKey.
 
 mcuxClKey_MemoryConsumption
 Defines the memory consumption for the mcuxClKey component.
 
 Key protection mechanism definitions
 Mechanisms used by the Key operations.
 
 mcuxClKey_Types
 Defines all types of mcuxClKey.
 
+

Detailed Description

+

mcuxClKey component

+

Key handling operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00784.js b/components/els_pkc/doc/mcxn/html/a00784.js new file mode 100644 index 000000000..f96a449b6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00784.js @@ -0,0 +1,8 @@ +var a00784 = +[ + [ "mcuxClKey_Macros", "a00785.html", "a00785" ], + [ "mcuxClKey_Functions", "a00790.html", "a00790" ], + [ "mcuxClKey_MemoryConsumption", "a00791.html", null ], + [ "Key protection mechanism definitions", "a00792.html", "a00792" ], + [ "mcuxClKey_Types", "a00793.html", "a00793" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00785.html b/components/els_pkc/doc/mcxn/html/a00785.html new file mode 100644 index 000000000..2f662a8a6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00785.html @@ -0,0 +1,186 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+ +
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+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClKey_Macros
MCUX CL &ndash; API » mcuxClKey
+
+
+ +

Defines all macros of mcuxClKey. +More...

+ + + + + + + + + + + + + + +

+Modules

 MCUXCLKEY_STATUS_
 Return code definitions.
 
 MCUXCLKEY_LOADSTATUS_
 Load location options.
 
 mcuxClKey_KeyTypes
 Defines all key types of mcuxClKey.
 
 mcuxClKey_KeySize
 Defines all key sizes of mcuxClKey.
 
+ + + + + + + +

+Macros

#define MCUXCLKEY_WA_SIZE_MAX
 Define the max workarea size required for this component. More...
 
#define MCUXCLKEY_INVALID_KEYSLOT
 Define the value for an invalid key slot. More...
 
+

Detailed Description

+

Defines all macros of mcuxClKey.

+

Macro Definition Documentation

+ +

◆ MCUXCLKEY_WA_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLKEY_WA_SIZE_MAX
+
+ +

Define the max workarea size required for this component.

+ +
+
+ +

◆ MCUXCLKEY_INVALID_KEYSLOT

+ +
+
+ + + + +
#define MCUXCLKEY_INVALID_KEYSLOT
+
+ +

Define the value for an invalid key slot.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00785.js b/components/els_pkc/doc/mcxn/html/a00785.js new file mode 100644 index 000000000..b16f62367 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00785.js @@ -0,0 +1,9 @@ +var a00785 = +[ + [ "MCUXCLKEY_STATUS_", "a00786.html", "a00786" ], + [ "MCUXCLKEY_LOADSTATUS_", "a00787.html", "a00787" ], + [ "mcuxClKey_KeyTypes", "a00788.html", "a00788" ], + [ "mcuxClKey_KeySize", "a00789.html", "a00789" ], + [ "MCUXCLKEY_WA_SIZE_MAX", "a00785.html#ga617470bb5f7da932c271545154fe31b7", null ], + [ "MCUXCLKEY_INVALID_KEYSLOT", "a00785.html#ga016a12d0d9ac976c44d4cf1f8a493763", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00786.html b/components/els_pkc/doc/mcxn/html/a00786.html new file mode 100644 index 000000000..1fbceb179 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00786.html @@ -0,0 +1,267 @@ + + + + + + + +MCUX CLNS: MCUXCLKEY_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Macros
+
+
MCUXCLKEY_STATUS_
MCUX CL &ndash; API » mcuxClKey » mcuxClKey_Macros
+
+
+ +

Return code definitions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLKEY_STATUS_OK
 Key operation successful. More...
 
#define MCUXCLKEY_STATUS_ERROR
 Error occured during Key operation. More...
 
#define MCUXCLKEY_STATUS_FAILURE
 Failure during execution. More...
 
#define MCUXCLKEY_STATUS_INVALID_INPUT
 Invalid input. More...
 
#define MCUXCLKEY_STATUS_FAULT_ATTACK
 Fault attack detected. More...
 
#define MCUXCLKEY_STATUS_CRC_NOT_OK
 CRC verification failed. More...
 
#define MCUXCLKEY_STATUS_NOT_SUPPORTED
 Functionality not supported. More...
 
+

Detailed Description

+

Return code definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLKEY_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_OK
+
+ +

Key operation successful.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_ERROR
+
+ +

Error occured during Key operation.

+ +
+
+ +

◆ MCUXCLKEY_STATUS_FAILURE

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_FAILURE
+
+ +

Failure during execution.

+ +
+
+ +

◆ MCUXCLKEY_STATUS_INVALID_INPUT

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_INVALID_INPUT
+
+ +

Invalid input.

+ +
+
+ +

◆ MCUXCLKEY_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_FAULT_ATTACK
+
+ +

Fault attack detected.

+ +
+
+ +

◆ MCUXCLKEY_STATUS_CRC_NOT_OK

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_CRC_NOT_OK
+
+ +

CRC verification failed.

+ +
+
+ +

◆ MCUXCLKEY_STATUS_NOT_SUPPORTED

+ +
+
+ + + + +
#define MCUXCLKEY_STATUS_NOT_SUPPORTED
+
+ +

Functionality not supported.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00786.js b/components/els_pkc/doc/mcxn/html/a00786.js new file mode 100644 index 000000000..ff078b18b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00786.js @@ -0,0 +1,10 @@ +var a00786 = +[ + [ "MCUXCLKEY_STATUS_OK", "a00786.html#ga3cac3b08cb53d2949698e19319010c49", null ], + [ "MCUXCLKEY_STATUS_ERROR", "a00786.html#gaad298a05e6e023bc251b91ad5173ac59", null ], + [ "MCUXCLKEY_STATUS_FAILURE", "a00786.html#gabcc2c3ef67df555b363b5bb51f71d83b", null ], + [ "MCUXCLKEY_STATUS_INVALID_INPUT", "a00786.html#gaf5c8b802949e1a7920cfdd65ec3fe42b", null ], + [ "MCUXCLKEY_STATUS_FAULT_ATTACK", "a00786.html#ga7be083c8ca459a7290b5cf7784c75469", null ], + [ "MCUXCLKEY_STATUS_CRC_NOT_OK", "a00786.html#gaa1223f9f839075cd078103d4129b5218", null ], + [ "MCUXCLKEY_STATUS_NOT_SUPPORTED", "a00786.html#gacb7a3820f23f7cc17d33498ab12e3b3c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00787.html b/components/els_pkc/doc/mcxn/html/a00787.html new file mode 100644 index 000000000..1f33d5e8b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00787.html @@ -0,0 +1,208 @@ + + + + + + + +MCUX CLNS: MCUXCLKEY_LOADSTATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+Macros
+
+
MCUXCLKEY_LOADSTATUS_
MCUX CL &ndash; API » mcuxClKey » mcuxClKey_Macros
+
+
+ +

Load location options. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLKEY_LOADSTATUS_NOTLOADED
 Key not loaded. More...
 
#define MCUXCLKEY_LOADSTATUS_MEMORY
 Key is loaded to memory. More...
 
#define MCUXCLKEY_LOADSTATUS_COPRO
 Key is loaded to HW IP slot. More...
 
#define MCUXCLKEY_LOADSTATUS_KEEPLOADED
 Do not flush the key after the operation (for Symmetric keys only) More...
 
+

Detailed Description

+

Load location options.

+

Macro Definition Documentation

+ +

◆ MCUXCLKEY_LOADSTATUS_NOTLOADED

+ +
+
+ + + + +
#define MCUXCLKEY_LOADSTATUS_NOTLOADED
+
+ +

Key not loaded.

+ +
+
+ +

◆ MCUXCLKEY_LOADSTATUS_MEMORY

+ +
+
+ + + + +
#define MCUXCLKEY_LOADSTATUS_MEMORY
+
+ +

Key is loaded to memory.

+ +
+
+ +

◆ MCUXCLKEY_LOADSTATUS_COPRO

+ +
+
+ + + + +
#define MCUXCLKEY_LOADSTATUS_COPRO
+
+ +

Key is loaded to HW IP slot.

+ +
+
+ +

◆ MCUXCLKEY_LOADSTATUS_KEEPLOADED

+ +
+
+ + + + +
#define MCUXCLKEY_LOADSTATUS_KEEPLOADED
+
+ +

Do not flush the key after the operation (for Symmetric keys only)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00787.js b/components/els_pkc/doc/mcxn/html/a00787.js new file mode 100644 index 000000000..ea0a521f1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00787.js @@ -0,0 +1,7 @@ +var a00787 = +[ + [ "MCUXCLKEY_LOADSTATUS_NOTLOADED", "a00787.html#ga8ce719dd938dbdc0cf859fbb1e602a0e", null ], + [ "MCUXCLKEY_LOADSTATUS_MEMORY", "a00787.html#ga50a509b8aa4abb9219470b45a385c794", null ], + [ "MCUXCLKEY_LOADSTATUS_COPRO", "a00787.html#ga3ab5a0669a60ff9b617bad0aeac71d72", null ], + [ "MCUXCLKEY_LOADSTATUS_KEEPLOADED", "a00787.html#gafd80ca5f40ff2e3898358c26cdd2caab", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00788.html b/components/els_pkc/doc/mcxn/html/a00788.html new file mode 100644 index 000000000..aad630238 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00788.html @@ -0,0 +1,499 @@ + + + + + + + +MCUX CLNS: mcuxClKey_KeyTypes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClKey_KeyTypes
MCUX CL &ndash; API » mcuxClKey » mcuxClKey_Macros
+
+
+ +

Defines all key types of mcuxClKey. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLKEY_ALGO_ID_AES
 AES key. More...
 
#define MCUXCLKEY_ALGO_ID_RSA
 RSA key. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP
 ECC key using Short Weierstrass Curve over GF(p) More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M
 ECC key using Short Weierstrass Curve over GF(2^m) More...
 
#define MCUXCLKEY_ALGO_ID_ECC_MONTDH
 ECC key for MontDH key exchange scheme. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_EDDSA
 ECC key for EdDSA signature scheme. More...
 
#define MCUXCLKEY_ALGO_ID_HMAC
 HMAC key. More...
 
#define MCUXCLKEY_ALGO_ID_SM4
 SM4 key. More...
 
#define MCUXCLKEY_ALGO_ID_SM2
 SM2 key. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM
 ECC key using Short Weierstrass Curve over GF(p) with ephemeral custom domain parameters. More...
 
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM
 ECC key using Short Weierstrass Curve over GF(p) with static custom domain parameters. More...
 
#define MCUXCLKEY_ALGO_ID_ALGO_MASK
 Mask for Algorithm. More...
 
#define MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY
 Symmetric key. More...
 
#define MCUXCLKEY_ALGO_ID_PUBLIC_KEY
 Public key. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY
 Private key. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT
 Private RSA key in CRT format. More...
 
#define MCUXCLKEY_ALGO_ID_KEY_PAIR
 Key pair. More...
 
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA
 RSA key pair, with the private part in CRT format. More...
 
#define MCUXCLKEY_ALGO_ID_USAGE_MASK
 Mask for Key Usage. More...
 
+

Detailed Description

+

Defines all key types of mcuxClKey.

+

Macro Definition Documentation

+ +

◆ MCUXCLKEY_ALGO_ID_AES

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_AES
+
+ +

AES key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_RSA

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_RSA
+
+ +

RSA key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP
+
+ +

ECC key using Short Weierstrass Curve over GF(p)

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M
+
+ +

ECC key using Short Weierstrass Curve over GF(2^m)

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_MONTDH

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_MONTDH
+
+ +

ECC key for MontDH key exchange scheme.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_EDDSA

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_EDDSA
+
+ +

ECC key for EdDSA signature scheme.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_HMAC

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_HMAC
+
+ +

HMAC key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_SM4

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_SM4
+
+ +

SM4 key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_SM2

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_SM2
+
+ +

SM2 key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM
+
+ +

ECC key using Short Weierstrass Curve over GF(p) with ephemeral custom domain parameters.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM
+
+ +

ECC key using Short Weierstrass Curve over GF(p) with static custom domain parameters.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_ALGO_MASK

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_ALGO_MASK
+
+ +

Mask for Algorithm.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY
+
+ +

Symmetric key.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_PUBLIC_KEY

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_PUBLIC_KEY
+
+ +

Public key.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_PRIVATE_KEY

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY
+
+ +

Private key.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT
+
+ +

Private RSA key in CRT format.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_KEY_PAIR

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_KEY_PAIR
+
+ +

Key pair.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA
+
+ +

RSA key pair, with the private part in CRT format.

+ +
+
+ +

◆ MCUXCLKEY_ALGO_ID_USAGE_MASK

+ +
+
+ + + + +
#define MCUXCLKEY_ALGO_ID_USAGE_MASK
+
+ +

Mask for Key Usage.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00788.js b/components/els_pkc/doc/mcxn/html/a00788.js new file mode 100644 index 000000000..73c2aba0e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00788.js @@ -0,0 +1,22 @@ +var a00788 = +[ + [ "MCUXCLKEY_ALGO_ID_AES", "a00788.html#gaf342031191b667161f2db471ddbc1724", null ], + [ "MCUXCLKEY_ALGO_ID_RSA", "a00788.html#ga728c97658536b4430e2b0e2c7373f141", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP", "a00788.html#ga2270daa12f0592b07c5a657d3cc1ae87", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M", "a00788.html#ga77f445482782348f049443d35a21662e", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_MONTDH", "a00788.html#gaace809498ccbffd63bc29f2b6d3a8db3", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_EDDSA", "a00788.html#gacbfa2e595e1fb1c6152cb4587ea01346", null ], + [ "MCUXCLKEY_ALGO_ID_HMAC", "a00788.html#gadb9ccdf41fc6a4868a0db982a601e226", null ], + [ "MCUXCLKEY_ALGO_ID_SM4", "a00788.html#ga8edc6b9dbe321d4e8a7f0681c4109111", null ], + [ "MCUXCLKEY_ALGO_ID_SM2", "a00788.html#gad4879e15a76d3c52e08855d993ba252e", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM", "a00788.html#gad51657624280512bd92719790363d763", null ], + [ "MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM", "a00788.html#ga8de9456ab126f7227b1077462fbca3b4", null ], + [ "MCUXCLKEY_ALGO_ID_ALGO_MASK", "a00788.html#gaf933f3469276e89b07aa395f90e2d180", null ], + [ "MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY", "a00788.html#gaa4fb66afe4c13047acc47ebf6d69e16e", null ], + [ "MCUXCLKEY_ALGO_ID_PUBLIC_KEY", "a00788.html#ga59fde148cf2683ed4371524df7ae3f06", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY", "a00788.html#ga18dcc408cf88d59a8d55fcfd3efd3b75", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT", "a00788.html#gacc27c79457fc64101a84a110014f92e1", null ], + [ "MCUXCLKEY_ALGO_ID_KEY_PAIR", "a00788.html#ga73033441ba95ee2e3dd88a2d14f30bd5", null ], + [ "MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA", "a00788.html#gabe8f17c80217f51dd7833e97ca169eee", null ], + [ "MCUXCLKEY_ALGO_ID_USAGE_MASK", "a00788.html#gadb73c82af33ca9b97d8465c36defdd6a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00789.html b/components/els_pkc/doc/mcxn/html/a00789.html new file mode 100644 index 000000000..9071005c1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00789.html @@ -0,0 +1,725 @@ + + + + + + + +MCUX CLNS: mcuxClKey_KeySize + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClKey_KeySize
MCUX CL &ndash; API » mcuxClKey » mcuxClKey_Macros
+
+
+ +

Defines all key sizes of mcuxClKey. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLKEY_SIZE_NOTUSED
 key length field is not used (e.g. ECC keys) More...
 
#define MCUXCLKEY_SIZE_128
 128 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_160
 160 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_192
 192 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_224
 224 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_256
 256 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_320
 320 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_384
 348 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_512
 512 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_521
 521 bit key, size in bytes More...
 
#define MCUXCLKEY_SIZE_1024
 1024 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_2048
 2048 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_3072
 3072 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_4096
 4096 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_6144
 6144 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_8192
 8192 bit key, size in bits More...
 
#define MCUXCLKEY_SIZE_128_IN_WORDS
 128 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_160_IN_WORDS
 160 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_192_IN_WORDS
 192 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_224_IN_WORDS
 224 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_256_IN_WORDS
 256 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_320_IN_WORDS
 320 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_384_IN_WORDS
 348 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_512_IN_WORDS
 512 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_521_IN_WORDS
 521 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_1024_IN_WORDS
 1024 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_2048_IN_WORDS
 2048 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_3072_IN_WORDS
 3072 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_4096_IN_WORDS
 4096 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_6144_IN_WORDS
 6144 bit key, size in words More...
 
#define MCUXCLKEY_SIZE_8192_IN_WORDS
 8192 bit key, size in words More...
 
+

Detailed Description

+

Defines all key sizes of mcuxClKey.

+

Macro Definition Documentation

+ +

◆ MCUXCLKEY_SIZE_NOTUSED

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_NOTUSED
+
+ +

key length field is not used (e.g. ECC keys)

+ +
+
+ +

◆ MCUXCLKEY_SIZE_128

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_128
+
+ +

128 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_160

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_160
+
+ +

160 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_192

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_192
+
+ +

192 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_224

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_224
+
+ +

224 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_256

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_256
+
+ +

256 bit key, size in bytes

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_SIZE_320

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_320
+
+ +

320 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_384

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_384
+
+ +

348 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_512

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_512
+
+ +

512 bit key, size in bytes

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLKEY_SIZE_521

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_521
+
+ +

521 bit key, size in bytes

+ +
+
+ +

◆ MCUXCLKEY_SIZE_1024

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_1024
+
+ +

1024 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_2048

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_2048
+
+ +

2048 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_3072

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_3072
+
+ +

3072 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_4096

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_4096
+
+ +

4096 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_6144

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_6144
+
+ +

6144 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_8192

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_8192
+
+ +

8192 bit key, size in bits

+ +
+
+ +

◆ MCUXCLKEY_SIZE_128_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_128_IN_WORDS
+
+ +

128 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_160_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_160_IN_WORDS
+
+ +

160 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_192_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_192_IN_WORDS
+
+ +

192 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_224_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_224_IN_WORDS
+
+ +

224 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_256_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_256_IN_WORDS
+
+ +

256 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_320_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_320_IN_WORDS
+
+ +

320 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_384_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_384_IN_WORDS
+
+ +

348 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_512_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_512_IN_WORDS
+
+ +

512 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_521_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_521_IN_WORDS
+
+ +

521 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_1024_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_1024_IN_WORDS
+
+ +

1024 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_2048_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_2048_IN_WORDS
+
+ +

2048 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_3072_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_3072_IN_WORDS
+
+ +

3072 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_4096_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_4096_IN_WORDS
+
+ +

4096 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_6144_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_6144_IN_WORDS
+
+ +

6144 bit key, size in words

+ +
+
+ +

◆ MCUXCLKEY_SIZE_8192_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLKEY_SIZE_8192_IN_WORDS
+
+ +

8192 bit key, size in words

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00789.js b/components/els_pkc/doc/mcxn/html/a00789.js new file mode 100644 index 000000000..f8f2b2130 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00789.js @@ -0,0 +1,34 @@ +var a00789 = +[ + [ "MCUXCLKEY_SIZE_NOTUSED", "a00789.html#gaba60c5f0fa5e1bfb5299f1e6814c919f", null ], + [ "MCUXCLKEY_SIZE_128", "a00789.html#gab0cb72bbcdd5736790b183a6e49f8eb8", null ], + [ "MCUXCLKEY_SIZE_160", "a00789.html#gac82b7eaeeb5f153630b71bbd59a7e515", null ], + [ "MCUXCLKEY_SIZE_192", "a00789.html#ga9871dfc831af8af21381f0f08007efe8", null ], + [ "MCUXCLKEY_SIZE_224", "a00789.html#gaaeee050febe3515ef1369c27a77d8a79", null ], + [ "MCUXCLKEY_SIZE_256", "a00789.html#ga16f615ca2af0dcc6dad9930cbfc21b89", null ], + [ "MCUXCLKEY_SIZE_320", "a00789.html#gad3a6f649d8e9b10a97bc0c04bc353718", null ], + [ "MCUXCLKEY_SIZE_384", "a00789.html#ga0d300ed35264eccec76e71201613f065", null ], + [ "MCUXCLKEY_SIZE_512", "a00789.html#ga7dd4afbbc02c2612af98796af352b875", null ], + [ "MCUXCLKEY_SIZE_521", "a00789.html#ga704db03c84c8e46314089d8b052ba030", null ], + [ "MCUXCLKEY_SIZE_1024", "a00789.html#gadd198add7df214eed81dbe316b150d3d", null ], + [ "MCUXCLKEY_SIZE_2048", "a00789.html#gacaf2b0cf43dc21e81e653d58be8320f6", null ], + [ "MCUXCLKEY_SIZE_3072", "a00789.html#gacdbba9c49cef3b7a47dc9570bdc72115", null ], + [ "MCUXCLKEY_SIZE_4096", "a00789.html#ga44cf02ee5c2944fa72ec10c3be54642a", null ], + [ "MCUXCLKEY_SIZE_6144", "a00789.html#gaf8c45542e3fe919a3dddc532b44cecd2", null ], + [ "MCUXCLKEY_SIZE_8192", "a00789.html#gaaee55d800a45f767592c0071e5fca0d8", null ], + [ "MCUXCLKEY_SIZE_128_IN_WORDS", "a00789.html#ga46a4709b4a513ab6676ee24944d4d2f0", null ], + [ "MCUXCLKEY_SIZE_160_IN_WORDS", "a00789.html#ga468b330bc005b81ccfe88e11171f391f", null ], + [ "MCUXCLKEY_SIZE_192_IN_WORDS", "a00789.html#gaeab881403cb2a9ade4906fda695a086e", null ], + [ "MCUXCLKEY_SIZE_224_IN_WORDS", "a00789.html#gaeb7c6bde09543bd3a45fc33c8e5beb3a", null ], + [ "MCUXCLKEY_SIZE_256_IN_WORDS", "a00789.html#ga6bea535c9b507d50ff14aa2dfb1ddf5b", null ], + [ "MCUXCLKEY_SIZE_320_IN_WORDS", "a00789.html#ga979dec395bea975d81634d14026159e4", null ], + [ "MCUXCLKEY_SIZE_384_IN_WORDS", "a00789.html#ga3ad1e0304140bdf547a93d45cbd7a5ff", null ], + [ "MCUXCLKEY_SIZE_512_IN_WORDS", "a00789.html#gacfa3ec1113e89c824bc9d3aaad76d04e", null ], + [ "MCUXCLKEY_SIZE_521_IN_WORDS", "a00789.html#gadaea316eb7a4a8b0b59e9f1879cae923", null ], + [ "MCUXCLKEY_SIZE_1024_IN_WORDS", "a00789.html#ga0c357e26537083ca9164aab3820b4ca7", null ], + [ "MCUXCLKEY_SIZE_2048_IN_WORDS", "a00789.html#gae48b497b883fa63ef84465fcb4fb3ced", null ], + [ "MCUXCLKEY_SIZE_3072_IN_WORDS", "a00789.html#gabbd3d5e04feb2c2f43a94d238cfca369", null ], + [ "MCUXCLKEY_SIZE_4096_IN_WORDS", "a00789.html#gada1e24d3f9d8207287333085df1712dd", null ], + [ "MCUXCLKEY_SIZE_6144_IN_WORDS", "a00789.html#ga4de61cf46c4577ba0019f92814cbf804", null ], + [ "MCUXCLKEY_SIZE_8192_IN_WORDS", "a00789.html#ga6c05f57184c5dd0da0cbb44ba28ce0f8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00790.html b/components/els_pkc/doc/mcxn/html/a00790.html new file mode 100644 index 000000000..047ca4aae --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00790.html @@ -0,0 +1,536 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ + +
+ +
+ +
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+Functions
+
+
mcuxClKey_Functions
MCUX CL &ndash; API » mcuxClKey
+
+
+ +

Defines all functions of mcuxClKey. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClKey_Status_t mcuxClKey_init (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Type_t type, mcuxCl_InputBuffer_t pKeyData, uint32_t keyDataLength)
 Initializes a key handle. More...
 
mcuxClKey_Status_t mcuxClKey_linkKeyPair (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t privKey, mcuxClKey_Handle_t pubKey)
 Establishes a key pair link between a private and public key handle. More...
 
mcuxClKey_Status_t mcuxClKey_setProtection (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, mcuxClKey_Protection_t protection, mcuxCl_Buffer_t pAuxData, mcuxClKey_Handle_t parentKey)
 Configures they protection mechanism for to the given key handle. More...
 
mcuxClKey_Status_t mcuxClKey_loadCopro (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t dstSlot)
 Load key into destination key slot of a coprocessor. More...
 
mcuxClKey_Status_t mcuxClKey_loadMemory (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key, uint32_t *dstData)
 Load key into destination memory buffer. More...
 
mcuxClKey_Status_t mcuxClKey_flush (mcuxClSession_Handle_t pSession, mcuxClKey_Handle_t key)
 Flush key from destination which can be a key slot of coprocessor or memory buffer. More...
 
mcuxClKey_Status_t mcuxClKey_setKeyproperties (mcuxClKey_Handle_t key, mcuxClEls_KeyProp_t *key_properties)
 Set the requested key properties of the destination key. More...
 
+

Detailed Description

+

Defines all functions of mcuxClKey.

+

Function Documentation

+ +

◆ mcuxClKey_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_init (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
mcuxClKey_Type_t type,
mcuxCl_InputBuffer_t pKeyData,
uint32_t keyDataLength 
)
+
+ +

Initializes a key handle.

+

Initializes a key handle with default protection values.

+
Parameters
+ + + + + + +
[in]pSessionSession handle to provide session dependent information
[in,out]keyKey handle that will be initialized
[in]typeDefine which key type shall be initialized
[in]pKeyDataProvide pointer to source data of the key. This can be a pointer to a plain key buffer, a share, or a key blob. The protection function defines the purpose of this parameter
[in]keyDataLengthLength of the provided key data pKeyData
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, and mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ mcuxClKey_linkKeyPair()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_linkKeyPair (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t privKey,
mcuxClKey_Handle_t pubKey 
)
+
+ +

Establishes a key pair link between a private and public key handle.

+
Parameters
+ + + + +
[in]pSessionSession handle to provide session dependent information
[in,out]privKeyKey handle of private key
[in,out]pubKeyKey handle of public key
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+ +
+
+ +

◆ mcuxClKey_setProtection()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_setProtection (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
mcuxClKey_Protection_t protection,
mcuxCl_Buffer_t pAuxData,
mcuxClKey_Handle_t parentKey 
)
+
+ +

Configures they protection mechanism for to the given key handle.

+
Parameters
+ + + + + + +
[in]pSessionSession handle to provide session dependent information
[in,out]keyKey handle that will be configured
[in]protectionDefine the protection and flush mechanism that shall be used with this key
[in]pAuxDataProvide pointer to additional data the protection function may use
[in]parentKeyProvide parent key information in case it exists. The protection function defines the purpose of this parameter
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+ +
+
+ +

◆ mcuxClKey_loadCopro()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_loadCopro (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
uint32_t dstSlot 
)
+
+ +

Load key into destination key slot of a coprocessor.

+
Parameters
+ + + + +
[in]pSessionSession handle to provide session dependent information
[in]keyKey handle that provides information to load the key
[out]dstSlotProvide destination key slot in case the key has to loaded to a key slot. The protection function defines the purpose of this parameter
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+ +
+
+ +

◆ mcuxClKey_loadMemory()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_loadMemory (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key,
uint32_t * dstData 
)
+
+ +

Load key into destination memory buffer.

+
Parameters
+ + + + +
[in]pSessionSession handle to provide session dependent information
[in]keyKey handle that provides information to load the key
[out]dstDataProvide pointer to destination key memory in case the key has to be loaded to memory. The protection function defines the purpose of this parameter
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+ +
+
+ +

◆ mcuxClKey_flush()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_flush (mcuxClSession_Handle_t pSession,
mcuxClKey_Handle_t key 
)
+
+ +

Flush key from destination which can be a key slot of coprocessor or memory buffer.

+
Parameters
+ + + +
[in]pSessionSession handle to provide session dependent information
[in]keyKey handle that provides information to flush the key
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+
Examples
mcuxClKey_example.c.
+
+ +
+
+ +

◆ mcuxClKey_setKeyproperties()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClKey_Status_t mcuxClKey_setKeyproperties (mcuxClKey_Handle_t key,
mcuxClEls_KeyProp_t * key_properties 
)
+
+ +

Set the requested key properties of the destination key.

+
Parameters
+ + + +
[in,out]keykey handle that provides information to flush the key
[in]key_propertiesPointer to the requested key properties of the destination key. Will be set in key->container.pAuxData
+
+
+
Returns
An error code that can be any error code in MCUXCLKEY_STATUS_, see individual documentation for more information
+
Return values
+ + + +
MCUXCLKEY_STATUS_ERRORon unsuccessful operation
MCUXCLKEY_STATUS_OKon successful operation
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00790.js b/components/els_pkc/doc/mcxn/html/a00790.js new file mode 100644 index 000000000..64083e139 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00790.js @@ -0,0 +1,10 @@ +var a00790 = +[ + [ "mcuxClKey_init", "a00790.html#ga8c6e891b1f7f973dbdccfe0f2a713142", null ], + [ "mcuxClKey_linkKeyPair", "a00790.html#gadac5d6a29e1a0dba2b418b98e4ccd0ee", null ], + [ "mcuxClKey_setProtection", "a00790.html#ga761180099785b36b6d5a6014cae54bb8", null ], + [ "mcuxClKey_loadCopro", "a00790.html#ga616ead4a2aaab2d0ae5502ba52315fca", null ], + [ "mcuxClKey_loadMemory", "a00790.html#gac4ec3d39748fc018dfb50316d2c51490", null ], + [ "mcuxClKey_flush", "a00790.html#ga60a86766cba40477651948cfa55eb7cd", null ], + [ "mcuxClKey_setKeyproperties", "a00790.html#gab1586a462e51711691901aa099f8b556", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00791.html b/components/els_pkc/doc/mcxn/html/a00791.html new file mode 100644 index 000000000..74eab75ec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00791.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: mcuxClKey_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ +
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+ + +
+ +
+ +
+
+Macros
+
+
mcuxClKey_MemoryConsumption
MCUX CL &ndash; API » mcuxClKey
+
+
+ +

Defines the memory consumption for the mcuxClKey component. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLKEY_DESCRIPTOR_SIZE
 
+#define MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS
 
+#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE
 
+#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE_IN_WORDS
 
+#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE
 
+#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClKey component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00792.html b/components/els_pkc/doc/mcxn/html/a00792.html new file mode 100644 index 000000000..9f222caec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00792.html @@ -0,0 +1,226 @@ + + + + + + + +MCUX CLNS: Key protection mechanism definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+ + + +
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+ +
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+ +
+ +
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+ + +
+ +
+ +
+
+Variables
+
+
Key protection mechanism definitions
MCUX CL &ndash; API » mcuxClKey
+
+
+ +

Mechanisms used by the Key operations. +More...

+ + + + + + + + + + + + + + +

+Variables

const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None
 Key protection descriptor for using no key protection. More...
 
static const mcuxClKey_Protection_t mcuxClKey_Protection_None
 No key protection. More...
 
const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf
 Key protection descriptor for using CKDF based key protection This protection mechanism cannot be used for mcuxClKey_loadMemory. More...
 
static const mcuxClKey_Protection_t mcuxClKey_Protection_Ckdf
 CKDF key protection. More...
 
+

Detailed Description

+

Mechanisms used by the Key operations.

+

Variable Documentation

+ +

◆ mcuxClKey_ProtectionDescriptor_None

+ +
+
+ + + + +
const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None
+
+ +

Key protection descriptor for using no key protection.

+ +
+
+ +

◆ mcuxClKey_Protection_None

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Protection_t mcuxClKey_Protection_None
+ 		+static
+
+ +

No key protection.

+
Examples
mcuxClEcc_Mont_Curve25519_example.c, and mcuxClEcc_Mont_Curve448_example.c.
+
+ +
+
+ +

◆ mcuxClKey_ProtectionDescriptor_Ckdf

+ +
+
+ + + + +
const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf
+
+ +

Key protection descriptor for using CKDF based key protection This protection mechanism cannot be used for mcuxClKey_loadMemory.

+ +
+
+ +

◆ mcuxClKey_Protection_Ckdf

+ +
+
+ + + + + +
+ + + + +
const mcuxClKey_Protection_t mcuxClKey_Protection_Ckdf
+ 		+static
+
+ +

CKDF key protection.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00792.js b/components/els_pkc/doc/mcxn/html/a00792.js new file mode 100644 index 000000000..7e0f749a4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00792.js @@ -0,0 +1,7 @@ +var a00792 = +[ + [ "mcuxClKey_ProtectionDescriptor_None", "a00792.html#gaa4fc9e15d78b127eaab9ec4c273d64b1", null ], + [ "mcuxClKey_Protection_None", "a00792.html#gabf61ad39ecaba937f41b73721ce80b6a", null ], + [ "mcuxClKey_ProtectionDescriptor_Ckdf", "a00792.html#ga11724513bd08cb490212fa5d70c7c5b0", null ], + [ "mcuxClKey_Protection_Ckdf", "a00792.html#ga46912713307ab64e4f20075064224838", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00793.html b/components/els_pkc/doc/mcxn/html/a00793.html new file mode 100644 index 000000000..48f9eb81e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00793.html @@ -0,0 +1,392 @@ + + + + + + + +MCUX CLNS: mcuxClKey_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClKey_Types
MCUX CL &ndash; API » mcuxClKey
+
+
+ +

Defines all types of mcuxClKey. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClKey_Status_t
 Type for Key component error codes. More...
 
typedef uint16_t mcuxClKey_AlgorithmId_t
 Type for algorithm based key id. More...
 
typedef uint32_t mcuxClKey_Size_t
 Type for algorithm based key size. More...
 
typedef mcuxClKey_Status_t mcuxClKey_Status_Protected_t
 Deprecated type for Key component error codes, returned by functions with code-flow protection. More...
 
typedef struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t
 Key descriptor type. More...
 
typedef mcuxClKey_Descriptor_t *const mcuxClKey_Handle_t
 Key handle type. More...
 
typedef struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
 Key type descriptor type. More...
 
typedef const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t
 Key type handle type. More...
 
typedef mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t
 Custom key type handle type. More...
 
typedef struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t
 Key protection mechanism descriptor type. More...
 
typedef const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t
 Key protection mechanism type. More...
 
typedef struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t
 Key generation descriptor type. More...
 
typedef const mcuxClKey_GenerationDescriptor_t *const mcuxClKey_Generation_t
 Key generation type. More...
 
+

Detailed Description

+

Defines all types of mcuxClKey.

+

Typedef Documentation

+ +

◆ mcuxClKey_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClKey_Status_t
+
+ +

Type for Key component error codes.

+ +
+
+ +

◆ mcuxClKey_AlgorithmId_t

+ +
+
+ + + + +
typedef uint16_t mcuxClKey_AlgorithmId_t
+
+ +

Type for algorithm based key id.

+ +
+
+ +

◆ mcuxClKey_Size_t

+ +
+
+ + + + +
typedef uint32_t mcuxClKey_Size_t
+
+ +

Type for algorithm based key size.

+ +
+
+ +

◆ mcuxClKey_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClKey_Status_t mcuxClKey_Status_Protected_t
+
+ +

Deprecated type for Key component error codes, returned by functions with code-flow protection.

+ +
+
+ +

◆ mcuxClKey_Descriptor_t

+ +
+
+ + + + +
typedef struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t
+
+ +

Key descriptor type.

+

This type captures all the information that the Key interfaces need to know about a particular Key.

+ +
+
+ +

◆ mcuxClKey_Handle_t

+ +
+
+ + + + +
typedef mcuxClKey_Descriptor_t* const mcuxClKey_Handle_t
+
+ +

Key handle type.

+

This type is used to refer to the opaque key descriptor.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ mcuxClKey_TypeDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t
+
+ +

Key type descriptor type.

+

This type captures all the information that the Key interfaces need to know about a particular Key type.

+ +
+
+ +

◆ mcuxClKey_Type_t

+ +
+
+ + + + +
typedef const mcuxClKey_TypeDescriptor_t* mcuxClKey_Type_t
+
+ +

Key type handle type.

+

This type is used to refer to a key type descriptor.

+ +
+
+ +

◆ mcuxClKey_CustomType_t

+ +
+
+ + + + +
typedef mcuxClKey_TypeDescriptor_t* mcuxClKey_CustomType_t
+
+ +

Custom key type handle type.

+

This type is used to refer to a custom key type descriptor.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ mcuxClKey_ProtectionDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t
+
+ +

Key protection mechanism descriptor type.

+

This type captures all the information that the Key interfaces need to know about a particular Key protection mechanism.

+ +
+
+ +

◆ mcuxClKey_Protection_t

+ +
+
+ + + + +
typedef const mcuxClKey_ProtectionDescriptor_t* mcuxClKey_Protection_t
+
+ +

Key protection mechanism type.

+

This type is used to refer to a Key protection mechanism.

+ +
+
+ +

◆ mcuxClKey_GenerationDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t
+
+ +

Key generation descriptor type.

+

This type captures all the information that the Key interfaces need to know about a particular Key generation algorithm.

+ +
+
+ +

◆ mcuxClKey_Generation_t

+ +
+
+ + + + +
typedef const mcuxClKey_GenerationDescriptor_t* const mcuxClKey_Generation_t
+
+ +

Key generation type.

+

This type is used to refer to a Key generation algorithm.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00793.js b/components/els_pkc/doc/mcxn/html/a00793.js new file mode 100644 index 000000000..f64741360 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00793.js @@ -0,0 +1,16 @@ +var a00793 = +[ + [ "mcuxClKey_Status_t", "a00793.html#gaa19905c3963849a56ee26a9b0e5013f5", null ], + [ "mcuxClKey_AlgorithmId_t", "a00793.html#ga322cbacb57f10aa6cb6731d64d4e64e3", null ], + [ "mcuxClKey_Size_t", "a00793.html#ga90c030f08081016123496c56021b9bab", null ], + [ "mcuxClKey_Status_Protected_t", "a00793.html#ga9886ee2d82f96093ad0a39385452cdfb", null ], + [ "mcuxClKey_Descriptor_t", "a00793.html#ga1b7557c7a8892e65d43b90f8d6226d6a", null ], + [ "mcuxClKey_Handle_t", "a00793.html#gafe84fa2aa66094f542164e0627a54c5d", null ], + [ "mcuxClKey_TypeDescriptor_t", "a00793.html#gae9a4d21e5a5239fd0ef48978a3774a89", null ], + [ "mcuxClKey_Type_t", "a00793.html#ga9ea75aa8fe6ddb914d91b170bb5d8be5", null ], + [ "mcuxClKey_CustomType_t", "a00793.html#ga4249d6ccc1dab6d15b46270da3c3d6d4", null ], + [ "mcuxClKey_ProtectionDescriptor_t", "a00793.html#ga1c51acf51723d52dbcdc1a0f80f98572", null ], + [ "mcuxClKey_Protection_t", "a00793.html#gab16fa58359f9994921f5d4a58c597c66", null ], + [ "mcuxClKey_GenerationDescriptor_t", "a00793.html#gaad2bc2272e961dd28dba4697d9287a14", null ], + [ "mcuxClKey_Generation_t", "a00793.html#gabb1e565ab474265cf8b53be6d9a1f758", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00794.html b/components/els_pkc/doc/mcxn/html/a00794.html new file mode 100644 index 000000000..25037dd51 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00794.html @@ -0,0 +1,144 @@ + + + + + + + +MCUX CLNS: mcuxClMac + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClMac
MCUX CL &ndash; API
+
+
+ +

Message Authentication Code (MAC) componentThe mcuxClMac component implements Message Authentication Code (MAC) calculation, based on either HMAC or CMAC. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClMac_Constants
 Constants of mcuxClMac component.
 
 mcuxClMac Functions
 Defines all functions of mcuxClMac.
 
 mcuxClMac_Types
 Defines all types of the mcuxClMac component.
 
+

Detailed Description

+

Message Authentication Code (MAC) component

+

The mcuxClMac component implements Message Authentication Code (MAC) calculation, based on either HMAC or CMAC.

+

An example of how to use the mcuxClMac component can be found in /mcuxClMac/ex.

+

The MAC can either be computed in one shot, using the mcuxClMac_compute function, or the input can be split into multiple parts. In that case, an initialization has to be performed first by calling the mcuxClMac_init function. Now zero, one, or more messages can be added for authentication by calling mcuxClMac_process. Finally, the MAC is generated when the mcuxClMac_finish function is called.

+

The mode to be used, HMAC or CMAC, is defined by passing the corresponding mode descriptor (mcuxClMac_Mode_t) to mcuxClMac_compute or mcuxClMac_init.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00794.js b/components/els_pkc/doc/mcxn/html/a00794.js new file mode 100644 index 000000000..63f2b906e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00794.js @@ -0,0 +1,6 @@ +var a00794 = +[ + [ "mcuxClMac_Constants", "a00795.html", null ], + [ "mcuxClMac Functions", "a00796.html", "a00796" ], + [ "mcuxClMac_Types", "a00799.html", "a00799" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00795.html b/components/els_pkc/doc/mcxn/html/a00795.html new file mode 100644 index 000000000..47342038a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00795.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMac_Constants
MCUX CL &ndash; API » mcuxClMac
+
+
+ +

Constants of mcuxClMac component. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLMAC_STATUS_ERROR
 
+#define MCUXCLMAC_STATUS_FAILURE
 
+#define MCUXCLMAC_STATUS_INVALID_PARAM
 
+#define MCUXCLMAC_STATUS_FAULT_ATTACK
 
+#define MCUXCLMAC_STATUS_OK
 
+#define MCUXCLMAC_STATUS_COMPARE_NOK
 
+

Detailed Description

+

Constants of mcuxClMac component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00796.html b/components/els_pkc/doc/mcxn/html/a00796.html new file mode 100644 index 000000000..7f37574f3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00796.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClMac Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClMac Functions
MCUX CL &ndash; API » mcuxClMac
+
+
+ +

Defines all functions of mcuxClMac. +More...

+ + + + + + + + +

+Modules

 One-shot MAC interfaces
 Interfaces to perform MAC operations in one shot.
 
 Multi part MAC interfaces
 Interfaces to perform MAC operations in multi part.
 
+

Detailed Description

+

Defines all functions of mcuxClMac.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00796.js b/components/els_pkc/doc/mcxn/html/a00796.js new file mode 100644 index 000000000..c7e7fa804 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00796.js @@ -0,0 +1,5 @@ +var a00796 = +[ + [ "One-shot MAC interfaces", "a00797.html", "a00797" ], + [ "Multi part MAC interfaces", "a00798.html", "a00798" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00797.html b/components/els_pkc/doc/mcxn/html/a00797.html new file mode 100644 index 000000000..bf3e8ba64 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00797.html @@ -0,0 +1,225 @@ + + + + + + + +MCUX CLNS: One-shot MAC interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
One-shot MAC interfaces
MCUX CL &ndash; API » mcuxClMac » mcuxClMac Functions
+
+
+ +

Interfaces to perform MAC operations in one shot. +More...

+ + + + + +

+Functions

mcuxClMac_Status_t mcuxClMac_compute (mcuxClSession_Handle_t session, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode, mcuxCl_InputBuffer_t pIn, uint32_t inLength, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
 One-shot message authentication code (MAC) computation function. More...
 
+

Detailed Description

+

Interfaces to perform MAC operations in one shot.

+

Function Documentation

+ +

◆ mcuxClMac_compute()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClMac_Status_t mcuxClMac_compute (mcuxClSession_Handle_t session,
mcuxClKey_Handle_t key,
mcuxClMac_Mode_t mode,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength,
mcuxCl_Buffer_t pMac,
uint32_t *const pMacLength 
)
+
+ +

One-shot message authentication code (MAC) computation function.

+

This function performs a MAC computation in one shot. The algorithm to be used will be determined based on the key that is provided.

+

For example, to perform an AES MAC computation with a 128-bit key in CMAC mode on padded data, the following needs to be provided:

    +
  • AES128 key
    • +
  • CMAC mode
    • +
  • Input data
    • +
  • Output data buffer, at least the size of a single AES block
    • +
+
Attention
In some cases restrictions may apply, e.g. the input buffer must be prepared for padding. Please refer to mcuxClMac_Modes.h to find further details and restrictions for each specific mode.
+
Parameters
+ + + + + + + + +
[in]sessionHandle for the current CL session.
[in]keyKey to be used to authenticate the data.
[in]modeMode that should be used during the MAC operation.
[in]pInPointer to the input buffer that contains the data that needs to be authenticated.
[in]inLengthNumber of bytes of data in the pIn buffer.
[out]pMacPointer to the output buffer where the MAC needs to be written.
[out]pMacLengthWill be incremented by the number of bytes of data that have been written to the pMac buffer.
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + + + + +
MCUXCLMAC_STATUS_OKMac operation successful
MCUXCLMAC_STATUS_ERRORError occurred during Mac operation
MCUXCLMAC_STATUS_INVALID_PARAMAn invalid parameter was given to the function
MCUXCLMAC_STATUS_FAULT_ATTACKFault attack detected
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00797.js b/components/els_pkc/doc/mcxn/html/a00797.js new file mode 100644 index 000000000..6b6bcda2b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00797.js @@ -0,0 +1,4 @@ +var a00797 = +[ + [ "mcuxClMac_compute", "a00797.html#gad2fe8b5e17f2b468fbe8a61f8fee5400", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00798.html b/components/els_pkc/doc/mcxn/html/a00798.html new file mode 100644 index 000000000..41e430eb7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00798.html @@ -0,0 +1,347 @@ + + + + + + + +MCUX CLNS: Multi part MAC interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Multi part MAC interfaces
MCUX CL &ndash; API » mcuxClMac » mcuxClMac Functions
+
+
+ +

Interfaces to perform MAC operations in multi part. +More...

+ + + + + + + + + + + +

+Functions

mcuxClMac_Status_t mcuxClMac_init (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxClKey_Handle_t key, mcuxClMac_Mode_t mode)
 Initialization for a multipart MAC computation. More...
 
mcuxClMac_Status_t mcuxClMac_process (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_InputBuffer_t pIn, uint32_t inLength)
 Data processing for a multipart MAC computation. More...
 
mcuxClMac_Status_t mcuxClMac_finish (mcuxClSession_Handle_t session, mcuxClMac_Context_t *const pContext, mcuxCl_Buffer_t pMac, uint32_t *const pMacLength)
 Finalize a MAC generation for a multipart MAC computation. More...
 
+

Detailed Description

+

Interfaces to perform MAC operations in multi part.

+

Function Documentation

+ +

◆ mcuxClMac_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClMac_Status_t mcuxClMac_init (mcuxClSession_Handle_t session,
mcuxClMac_Context_t *const pContext,
mcuxClKey_Handle_t key,
mcuxClMac_Mode_t mode 
)
+
+ +

Initialization for a multipart MAC computation.

+

This function performs the initialization of a context for a multipart MAC computation. The algorithm to be used will be determined based on the key that is provided.

+

This function should only be called once, as the first step for a multipart computation.

+

For example, to perform a multipart AES MAC computation with a 128-bit key in CMAC mode on padded data, the following needs to be provided in this step:

    +
  • AES128 key
    • +
  • CMAC mode
    • +
+

The size of the context depends on the mode used (see mcuxClMac_MemoryConsumption).

+
Parameters
+ + + + + +
[in]sessionHandle for the current CL session.
[in]pContextMAC context which is used to maintain the state and store other relevant information about the operation.
[in]keyKey to be used to MAC the data.
[in]modeMode that should be used during the MAC operation.
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + + + + +
MCUXCLMAC_STATUS_OKMac operation successful
MCUXCLMAC_STATUS_ERRORError occurred during Mac operation
MCUXCLMAC_STATUS_INVALID_PARAMAn invalid parameter was given to the function
MCUXCLMAC_STATUS_FAULT_ATTACKFault attack detected
+
+
+ +
+
+ +

◆ mcuxClMac_process()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClMac_Status_t mcuxClMac_process (mcuxClSession_Handle_t session,
mcuxClMac_Context_t *const pContext,
mcuxCl_InputBuffer_t pIn,
uint32_t inLength 
)
+
+ +

Data processing for a multipart MAC computation.

+

This function performs the data processing for a multipart MAC computation. The algorithm and key to be used will be determined based on the context that is provided.

+

This function can be called multiple times, after the multipart context initialization.

+

For example, to perform a multipart AES MAC computation with a 128-bit key in CMAC mode on padded data, the following needs to be provided in this step:

    +
  • Input data
    • +
+

The size of the context depends on the mode used (see mcuxClMac_MemoryConsumption).

+
See also
mcuxClMac_init
+
Parameters
+ + + + + +
sessionHandle for the current CL session.
[in]pContextMAC context which is used to maintain the state and store other relevant information about the operation.
[in]pInPointer to the input buffer that contains the data that need to be processed.
[in]inLengthNumber of bytes of data in the in buffer.
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + + + + +
MCUXCLMAC_STATUS_OKMac operation successful
MCUXCLMAC_STATUS_ERRORError occurred during Mac operation
MCUXCLMAC_STATUS_INVALID_PARAMAn invalid parameter was given to the function
MCUXCLMAC_STATUS_FAULT_ATTACKFault attack detected
+
+
+ +
+
+ +

◆ mcuxClMac_finish()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClMac_Status_t mcuxClMac_finish (mcuxClSession_Handle_t session,
mcuxClMac_Context_t *const pContext,
mcuxCl_Buffer_t pMac,
uint32_t *const pMacLength 
)
+
+ +

Finalize a MAC generation for a multipart MAC computation.

+

This function performs the final MAC generation step for a multipart MAC computation. The algorithm and key to be used will be determined based on the context that is provided.

+

This function should only be called once, as the last step for a multipart computation.

+

For example, to perform a multipart AES MAC computation with a 128-bit key in CMAC mode on padded data, the following needs to be provided in this step:

    +
  • Output data buffer, at least the size of a single AES block
    • +
+

The size of the context depends on the mode used (see mcuxClMac_MemoryConsumption).

+
See also
mcuxClMac_init
+
+mcuxClMac_process
+
Parameters
+ + + + + +
[in]sessionHandle for the current CL session.
[in]pContextMAC context which is used to maintain the state and store other relevant information about the operation.
[out]pMacPointer to the output buffer where the MAC needs to be written.
[out]pMacLengthWill be incremented by the number of bytes of data that have been written to the pMac buffer.
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + + + + +
MCUXCLMAC_STATUS_OKMac operation successful
MCUXCLMAC_STATUS_ERRORError occurred during Mac operation
MCUXCLMAC_STATUS_INVALID_PARAMAn invalid parameter was given to the function
MCUXCLMAC_STATUS_FAULT_ATTACKFault attack detected
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00798.js b/components/els_pkc/doc/mcxn/html/a00798.js new file mode 100644 index 000000000..5d00998e0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00798.js @@ -0,0 +1,6 @@ +var a00798 = +[ + [ "mcuxClMac_init", "a00798.html#ga803bd7822372bdca8dfd0c81b5db96eb", null ], + [ "mcuxClMac_process", "a00798.html#ga2749e40209d4308f21ebe761485d4d56", null ], + [ "mcuxClMac_finish", "a00798.html#ga9d66c6e242ff75b6ff4826fdcb784e08", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00799.html b/components/els_pkc/doc/mcxn/html/a00799.html new file mode 100644 index 000000000..19d4fba45 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00799.html @@ -0,0 +1,272 @@ + + + + + + + +MCUX CLNS: mcuxClMac_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxClMac_Types
MCUX CL &ndash; API » mcuxClMac
+
+
+ +

Defines all types of the mcuxClMac component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClMac_Status_t
 Type for Mac component error codes. More...
 
typedef struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
 MAC mode/algorithm descriptor type. More...
 
typedef const mcuxClMac_ModeDescriptor_t *const mcuxClMac_Mode_t
 MAC mode/algorithm type. More...
 
typedef mcuxClMac_ModeDescriptor_t *const mcuxClMac_CustomMode_t
 MAC custom mode/algorithm type. More...
 
typedef struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t
 Mac selftest mode/algorithm descriptor type. More...
 
typedef const mcuxClMac_TestDescriptor_t *const mcuxClMac_Test_t
 Mac selftest mode/algorithm type. More...
 
typedef struct mcuxClMac_Context mcuxClMac_Context_t
 Mac context type. More...
 
+

Detailed Description

+

Defines all types of the mcuxClMac component.

+

Typedef Documentation

+ +

◆ mcuxClMac_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClMac_Status_t
+
+ +

Type for Mac component error codes.

+ +
+
+ +

◆ mcuxClMac_ModeDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t
+
+ +

MAC mode/algorithm descriptor type.

+

This type captures all the information that the MAC interfaces need to know about a particular MAC mode/algorithm.

+ +
+
+ +

◆ mcuxClMac_Mode_t

+ +
+
+ + + + +
typedef const mcuxClMac_ModeDescriptor_t* const mcuxClMac_Mode_t
+
+ +

MAC mode/algorithm type.

+

This type is used to refer to a MAC mode/algorithm.

+ +
+
+ +

◆ mcuxClMac_CustomMode_t

+ +
+
+ + + + +
typedef mcuxClMac_ModeDescriptor_t* const mcuxClMac_CustomMode_t
+
+ +

MAC custom mode/algorithm type.

+

This type is used to refer to a custom MAC mode/algorithm that can be created via a provided constructor.

+ +
+
+ +

◆ mcuxClMac_TestDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t
+
+ +

Mac selftest mode/algorithm descriptor type.

+

This type captures all the information that the Mac selftest interfaces need to know about a particular Mac selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClMac_Test_t

+ +
+
+ + + + +
typedef const mcuxClMac_TestDescriptor_t* const mcuxClMac_Test_t
+
+ +

Mac selftest mode/algorithm type.

+

This type is used to refer to a Mac selftest mode/algorithm.

+ +
+
+ +

◆ mcuxClMac_Context_t

+ +
+
+ + + + +
typedef struct mcuxClMac_Context mcuxClMac_Context_t
+
+ +

Mac context type.

+

This type captures all the information that the Mac interface needs to know for a particular Mac mode/algorithm to work.

+

The size of the context depends on the mode used (see mcuxClMac_MemoryConsumption).

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00799.js b/components/els_pkc/doc/mcxn/html/a00799.js new file mode 100644 index 000000000..14eb95aaf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00799.js @@ -0,0 +1,10 @@ +var a00799 = +[ + [ "mcuxClMac_Status_t", "a00799.html#gaca63aa917056a18f99a911f329f3971b", null ], + [ "mcuxClMac_ModeDescriptor_t", "a00799.html#gaad5e6326d43f28d324ef2d98ac3ad2cc", null ], + [ "mcuxClMac_Mode_t", "a00799.html#ga8e9aa3b88af43aaf819650568abc471f", null ], + [ "mcuxClMac_CustomMode_t", "a00799.html#ga55e9279a13efd1dd87affcc88f3eb34a", null ], + [ "mcuxClMac_TestDescriptor_t", "a00799.html#ga05358be86e9c9b69f46225171d63f406", null ], + [ "mcuxClMac_Test_t", "a00799.html#ga0af47561198575f7792301a2a5135e75", null ], + [ "mcuxClMac_Context_t", "a00799.html#gaf804dbff6e0d68d2d877b21995ed5c34", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00800.html b/components/els_pkc/doc/mcxn/html/a00800.html new file mode 100644 index 000000000..d04d12cf9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00800.html @@ -0,0 +1,214 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMacModes Constants
MCUX CL &ndash; API » MAC Modes API
+
+
+ +

Constants of MAC Modes API component. +More...

+ + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE
 Size of CBCMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS
 Size of CBCMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CMAC_OUTPUT_SIZE
 Size of CMAC output in bytes: 128 bits (16 bytes) More...
 
#define MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS
 Size of CMAC output in bytes: 128 bits (16 bytes) More...
 
+#define MCUXCLMACMODES_MAX_OUTPUT_SIZE
 
+#define MCUXCLMACMODES_MAX_OUTPUT_SIZE_IN_WORDS
 
+

Detailed Description

+

Constants of MAC Modes API component.

+

Macro Definition Documentation

+ +

◆ MCUXCLMAC_CBCMAC_OUTPUT_SIZE

+ +
+
+ + + + +
#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE
+
+ +

Size of CBCMAC output in bytes: 128 bits (16 bytes)

+ +
+
+ +

◆ MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS
+
+ +

Size of CBCMAC output in bytes: 128 bits (16 bytes)

+ +
+
+ +

◆ MCUXCLMAC_CMAC_OUTPUT_SIZE

+ +
+
+ + + + +
#define MCUXCLMAC_CMAC_OUTPUT_SIZE
+
+ +

Size of CMAC output in bytes: 128 bits (16 bytes)

+ +
+
+ +

◆ MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS
+
+ +

Size of CMAC output in bytes: 128 bits (16 bytes)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00800.js b/components/els_pkc/doc/mcxn/html/a00800.js new file mode 100644 index 000000000..6a6e176ed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00800.js @@ -0,0 +1,7 @@ +var a00800 = +[ + [ "MCUXCLMAC_CBCMAC_OUTPUT_SIZE", "a00800.html#gae3fbb2da7d5fef73ea388eb30cb0e8a4", null ], + [ "MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS", "a00800.html#ga071c1074dbc84e227e6bb7de4355d9e4", null ], + [ "MCUXCLMAC_CMAC_OUTPUT_SIZE", "a00800.html#ga19fabc0fcc4bb740d3ae3f5af0801932", null ], + [ "MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS", "a00800.html#ga6c92dadeb46681334a49ccd369639ca3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00801.html b/components/els_pkc/doc/mcxn/html/a00801.html new file mode 100644 index 000000000..0c5e5d0d7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00801.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClMacModes Functions
MCUX CL &ndash; API » MAC Modes API
+
+
+ +

Defines all functions of MAC Modes API. +More...

+ + + + + +

+Modules

 APIs to construct Mac modes
 Interfaces to construct Mac modes of operation.
 
+

Detailed Description

+

Defines all functions of MAC Modes API.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00801.js b/components/els_pkc/doc/mcxn/html/a00801.js new file mode 100644 index 000000000..67a7f8fa2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00801.js @@ -0,0 +1,4 @@ +var a00801 = +[ + [ "APIs to construct Mac modes", "a00802.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00802.html b/components/els_pkc/doc/mcxn/html/a00802.html new file mode 100644 index 000000000..c51b402d0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00802.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: APIs to construct Mac modes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
APIs to construct Mac modes
MCUX CL &ndash; API » MAC Modes API » mcuxClMacModes Functions
+
+
+ +

Interfaces to construct Mac modes of operation. +More...

+

Interfaces to construct Mac modes of operation.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00803.html b/components/els_pkc/doc/mcxn/html/a00803.html new file mode 100644 index 000000000..e81c61291 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00803.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxClMacModes_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMacModes_MemoryConsumption
MCUX CL &ndash; API » MAC Modes API
+
+
+ +

Defines the memory consumption for the mcuxClMacModes component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(size)
 
+#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS
 
+#define MCUXCLMAC_CONTEXT_SIZE
 
+#define MCUXCLMAC_CONTEXT_SIZE_IN_WORDS
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClMacModes component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00804.html b/components/els_pkc/doc/mcxn/html/a00804.html new file mode 100644 index 000000000..b071a8649 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00804.html @@ -0,0 +1,316 @@ + + + + + + + +MCUX CLNS: MAC mode definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
MAC mode definitions
MCUX CL &ndash; API » MAC Modes API
+
+
+ +

Modes used by the MAC operations. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC
 CMAC mode descriptor. More...
 
static mcuxClMac_Mode_t mcuxClMac_Mode_CMAC
 CMAC mode. More...
 
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding
 CBC-MAC mode descriptor without padding. More...
 
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_NoPadding
 CBC-MAC mode without padding. More...
 
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1
 CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 1. More...
 
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1
 CBC-MAC mode with ISO/IEC 9797-1 padding method 1. More...
 
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2
 CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 2. More...
 
static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2
 CBC-MAC mode with ISO/IEC 9797-1 padding method 2. More...
 
+

Detailed Description

+

Modes used by the MAC operations.

+

Variable Documentation

+ +

◆ mcuxClMac_ModeDescriptor_CMAC

+ +
+
+ + + + +
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC
+
+ +

CMAC mode descriptor.

+ +
+
+ +

◆ mcuxClMac_Mode_CMAC

+ +
+
+ + + + + +
+ + + + +
mcuxClMac_Mode_t mcuxClMac_Mode_CMAC
+ 		+static
+
+ +

CMAC mode.

+ +
+
+ +

◆ mcuxClMac_ModeDescriptor_CBCMAC_NoPadding

+ +
+
+ + + + +
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding
+
+ +

CBC-MAC mode descriptor without padding.

+ +
+
+ +

◆ mcuxClMac_Mode_CBCMAC_NoPadding

+ +
+
+ + + + + +
+ + + + +
mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_NoPadding
+ 		+static
+
+ +

CBC-MAC mode without padding.

+ +
+
+ +

◆ mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1

+ +
+
+ + + + +
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1
+
+ +

CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1

+ +
+
+ + + + + +
+ + + + +
mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1
+ 		+static
+
+ +

CBC-MAC mode with ISO/IEC 9797-1 padding method 1.

+ +
+
+ +

◆ mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2

+ +
+
+ + + + +
const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2
+
+ +

CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 2.

+ +
+
+ +

◆ mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2

+ +
+
+ + + + + +
+ + + + +
mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2
+ 		+static
+
+ +

CBC-MAC mode with ISO/IEC 9797-1 padding method 2.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00804.js b/components/els_pkc/doc/mcxn/html/a00804.js new file mode 100644 index 000000000..41c0eab5f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00804.js @@ -0,0 +1,11 @@ +var a00804 = +[ + [ "mcuxClMac_ModeDescriptor_CMAC", "a00804.html#ga7df28da412f427562a5ffcb2b3ab8c35", null ], + [ "mcuxClMac_Mode_CMAC", "a00804.html#gab5f61e17bb7b7d97f69745700f107bc6", null ], + [ "mcuxClMac_ModeDescriptor_CBCMAC_NoPadding", "a00804.html#gab8171ca5a2cad3f74f26cade42abb4fa", null ], + [ "mcuxClMac_Mode_CBCMAC_NoPadding", "a00804.html#ga0edfb9edb1c66eba797754851e463a20", null ], + [ "mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1", "a00804.html#gacf3978d54625d231254d9b42bcbf349c", null ], + [ "mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1", "a00804.html#ga39e525bf4e237be5933966afa1eafd02", null ], + [ "mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2", "a00804.html#gaacbabbb60934ae05725b5cb2889c7bce", null ], + [ "mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2", "a00804.html#ga6727ecd0ad3c728bb1ba822f7fd6f485", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00805.html b/components/els_pkc/doc/mcxn/html/a00805.html new file mode 100644 index 000000000..8023546a1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00805.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClMath + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+Modules
+
+
mcuxClMath
+
+
+ +

component of mathematics functions +More...

+ + + + + + + + +

+Modules

 mcuxClMath_Functions
 Defines all functions of mcuxClMath.
 
 mcuxClMath_Macros
 Defines all macros of mcuxClMath.
 
+

Detailed Description

+

component of mathematics functions

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00805.js b/components/els_pkc/doc/mcxn/html/a00805.js new file mode 100644 index 000000000..9a993851e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00805.js @@ -0,0 +1,5 @@ +var a00805 = +[ + [ "mcuxClMath_Functions", "a00806.html", "a00806" ], + [ "mcuxClMath_Macros", "a00807.html", "a00807" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00806.html b/components/els_pkc/doc/mcxn/html/a00806.html new file mode 100644 index 000000000..79c1c261b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00806.html @@ -0,0 +1,2169 @@ + + + + + + + +MCUX CLNS: mcuxClMath_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
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+
+ +
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+ + +
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+ +
+
+Macros | +Functions
+
+
mcuxClMath_Functions
mcuxClMath
+
+
+ +

Defines all functions of mcuxClMath. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLMATH_SHIFTMODULUS(iNShifted, iN)
 Helper macro for mcuxClMath_ShiftModulus. More...
 
#define MCUXCLMATH_FP_SHIFTMODULUS(iNShifted, iN)
 Helper macro for mcuxClMath_ShiftModulus with flow protection. More...
 
#define MCUXCLMATH_NDASH(iN, iT)
 Helper macro for mcuxClMath_NDash. More...
 
#define MCUXCLMATH_FP_NDASH(iN, iT)
 Helper macro for mcuxClMath_NDash with flow protection. More...
 
#define MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len)
 Helper macro for mcuxClMath_QDash. More...
 
#define MCUXCLMATH_FP_QDASH(iQDash, iNShifted, iN, iT, len)
 Helper macro for mcuxClMath_QDash with flow protection. More...
 
#define MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT)
 Helper macro for mcuxClMath_QSquared. More...
 
#define MCUXCLMATH_FP_QSQUARED(iQSqr, iNShifted, iN, iT)
 Helper macro for mcuxClMath_QSquared with flow protection. More...
 
#define MCUXCLMATH_MODINV(iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModInv. More...
 
#define MCUXCLMATH_FP_MODINV(iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModInv with flow protection. More...
 
#define MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_ReduceModEven. More...
 
#define MCUXCLMATH_FP_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_ReduceModEven with flow protection. More...
 
#define MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModExp_SqrMultL2R. More...
 
#define MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT)
 Helper macro for mcuxClMath_ModExp_SqrMultL2R with flow protection. More...
 
#define MCUXCLMATH_SECMODEXP(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_SecModExp. More...
 
#define MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3)
 Helper macro for mcuxClMath_SecModExp with disabled operand re-randomization. More...
 
#define MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivideOdd. More...
 
#define MCUXCLMATH_FP_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivideOdd with flow protection. More...
 
#define MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivide. More...
 
#define MCUXCLMATH_FP_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)
 Helper macro for mcuxClMath_ExactDivide with flow protection. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void mcuxClMath_InitLocalUptrt (uint32_t i3_i2_i1_i0, uint32_t i7_i6_i5_i4, uint16_t *localPtrUptrt, uint8_t noOfIndices, const uint16_t **oldPtrUptrt)
 Initializes and uses the new UPTRT and returns the address of original UPTRT. More...
 
void mcuxClMath_LeadingZeros (uint8_t iX, uint32_t *pNumLeadingZeros)
 Counts number of leading zero bits of a PKC operand. More...
 
uint32_t mcuxClMath_TrailingZeros (uint8_t iX)
 Counts number of trailing zero bits of a PKC operand. More...
 
void mcuxClMath_ShiftModulus (uint16_t iNShifted_iN)
 Prepares shifted modulus. More...
 
void mcuxClMath_NDash (uint16_t iN_iT)
 Prepares modulus (calculates NDash) for PKC modular multiplication. More...
 
void mcuxClMath_QDash (uint32_t iQDash_iNShifted_iN_iT, uint16_t length)
 Calculates QDash = Q * Q' mod n, where Q = 256^(operandSize) mod n, and Q' = 256^length mod n. More...
 
void mcuxClMath_QSquared (uint32_t iQSqr_iNShifted_iN_iT)
 Calculates QSquared = Q^2 mod n, where Q = 256^(operandSize) mod n. More...
 
void mcuxClMath_ModInv (uint32_t iR_iX_iN_iT)
 Calculates modular inversion, with odd modulus. More...
 
void mcuxClMath_ReduceModEven (uint32_t iR_iX_iN_iT0, uint32_t iT1_iT2_iT3)
 Calculates modular reduction with even modulus. More...
 
void mcuxClMath_ModExp_SqrMultL2R (const uint8_t *pExp, uint32_t expByteLength, uint32_t iR_iX_iN_iT)
 Calculates modular exponentiation. More...
 
mcuxClMath_Status_t mcuxClMath_SecModExp (mcuxClSession_Handle_t session, const uint8_t *pExp, uint32_t *pExpTemp, uint32_t expByteLength, uint32_t iT3_iX_iT2_iT1, uint32_t iN_iTE_iT0_iR, uint32_t secOption)
 Securely calculates modular exponentiation. More...
 
void mcuxClMath_ExactDivideOdd (uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
 Calculates exact division with odd divisor. More...
 
void mcuxClMath_ExactDivide (uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength)
 Calculates exact division (supporting even divisor). More...
 
+

Detailed Description

+

Defines all functions of mcuxClMath.

+

Macro Definition Documentation

+ +

◆ MCUXCLMATH_SHIFTMODULUS

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_SHIFTMODULUS( iNShifted,
 iN 
)
+
+ +

Helper macro for mcuxClMath_ShiftModulus.

+ +
+
+ +

◆ MCUXCLMATH_FP_SHIFTMODULUS

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_SHIFTMODULUS( iNShifted,
 iN 
)
+
+ +

Helper macro for mcuxClMath_ShiftModulus with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_NDASH

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_NDASH( iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_NDash.

+ +
+
+ +

◆ MCUXCLMATH_FP_NDASH

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_NDASH( iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_NDash with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_QDASH

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_QDASH( iQDash,
 iNShifted,
 iN,
 iT,
 len 
)
+
+ +

Helper macro for mcuxClMath_QDash.

+ +
+
+ +

◆ MCUXCLMATH_FP_QDASH

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_QDASH( iQDash,
 iNShifted,
 iN,
 iT,
 len 
)
+
+ +

Helper macro for mcuxClMath_QDash with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_QSQUARED

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_QSQUARED( iQSqr,
 iNShifted,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_QSquared.

+ +
+
+ +

◆ MCUXCLMATH_FP_QSQUARED

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_QSQUARED( iQSqr,
 iNShifted,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_QSquared with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_MODINV

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_MODINV( iR,
 iX,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_ModInv.

+ +
+
+ +

◆ MCUXCLMATH_FP_MODINV

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_MODINV( iR,
 iX,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_ModInv with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_REDUCEMODEVEN

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_REDUCEMODEVEN( iR,
 iX,
 iN,
 iT0,
 iT1,
 iT2,
 iT3 
)
+
+ +

Helper macro for mcuxClMath_ReduceModEven.

+ +
+
+ +

◆ MCUXCLMATH_FP_REDUCEMODEVEN

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_REDUCEMODEVEN( iR,
 iX,
 iN,
 iT0,
 iT1,
 iT2,
 iT3 
)
+
+ +

Helper macro for mcuxClMath_ReduceModEven with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_MODEXP_SQRMULTL2R

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_MODEXP_SQRMULTL2R( pExp,
 byteLenExp,
 iR,
 iX,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_ModExp_SqrMultL2R.

+ +
+
+ +

◆ MCUXCLMATH_FP_MODEXP_SQRMULTL2R

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_MODEXP_SQRMULTL2R( pExp,
 byteLenExp,
 iR,
 iX,
 iN,
 iT 
)
+
+ +

Helper macro for mcuxClMath_ModExp_SqrMultL2R with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_SECMODEXP

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_SECMODEXP( session,
 pExp,
 pExpTemp,
 byteLenExp,
 iR,
 iX,
 iN,
 iTE,
 iT0,
 iT1,
 iT2,
 iT3 
)
+
+ +

Helper macro for mcuxClMath_SecModExp.

+ +
+
+ +

◆ MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION( session,
 pExp,
 pExpTemp,
 byteLenExp,
 iR,
 iX,
 iN,
 iTE,
 iT0,
 iT1,
 iT2,
 iT3 
)
+
+ +

Helper macro for mcuxClMath_SecModExp with disabled operand re-randomization.

+

TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption to always re-randomize

+ +
+
+ +

◆ MCUXCLMATH_EXACTDIVIDEODD

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_EXACTDIVIDEODD( iR,
 iX,
 iN,
 iT,
 xPkcByteLen,
 yPkcByteLen 
)
+
+ +

Helper macro for mcuxClMath_ExactDivideOdd.

+ +
+
+ +

◆ MCUXCLMATH_FP_EXACTDIVIDEODD

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_EXACTDIVIDEODD( iR,
 iX,
 iN,
 iT,
 xPkcByteLen,
 yPkcByteLen 
)
+
+ +

Helper macro for mcuxClMath_ExactDivideOdd with flow protection.

+ +
+
+ +

◆ MCUXCLMATH_EXACTDIVIDE

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_EXACTDIVIDE( iR,
 iX,
 iN,
 iT,
 xPkcByteLen,
 yPkcByteLen 
)
+
+ +

Helper macro for mcuxClMath_ExactDivide.

+ +
+
+ +

◆ MCUXCLMATH_FP_EXACTDIVIDE

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMATH_FP_EXACTDIVIDE( iR,
 iX,
 iN,
 iT,
 xPkcByteLen,
 yPkcByteLen 
)
+
+ +

Helper macro for mcuxClMath_ExactDivide with flow protection.

+ +
+
+

Function Documentation

+ +

◆ mcuxClMath_InitLocalUptrt()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMath_InitLocalUptrt (uint32_t i3_i2_i1_i0,
uint32_t i7_i6_i5_i4,
uint16_t * localPtrUptrt,
uint8_t noOfIndices,
const uint16_t ** oldPtrUptrt 
)
+
+ +

Initializes and uses the new UPTRT and returns the address of original UPTRT.

+

This function copies up to 8 offsets of PKC operands from current UPTRT to the new UPTRT, sets PKC to use the new UPTRT, and returns the address of original UPTRT.

+
Parameters
+ + + + + + +
[in]i3_i2_i1_i0the first 4 indices of offsets to be copied
[in]i7_i6_i5_i4the second 4 indices of offsets to be copied
[in,out]localPtrUptrtaddress of the new UPTRT to be filled
[in]noOfIndicesnumber of offsets to be copied from original UPTRT to new UPTRT
[out]oldPtrUptrtpointer to where receives the original UPTRT address
+
+
+
+
Parameter properties
+
+
i3_i2_i1_i0
+
i0 (bits 0~7): originalUptrt[i0] will be copied to localPtrUptrt[0], if noOfIndices >= 1.
+i1 (bits 8~15): originalUptrt[i1] will be copied to localPtrUptrt[1], if noOfIndices >= 2.
+i2 (bits 16~23): originalUptrt[i2] will be copied to localPtrUptrt[2], if noOfIndices >= 3.
+i3 (bits 24~31): originalUptrt[i3] will be copied to localPtrUptrt[3], if noOfIndices >= 4.
+
i7_i6_i5_i4
+
i4 (bits 0~7): originalUptrt[i4] will be copied to localPtrUptrt[4], if noOfIndices >= 5.
+i5 (bits 8~15): originalUptrt[i5] will be copied to localPtrUptrt[5], if noOfIndices >= 6.
+i6 (bits 16~23): originalUptrt[i6] will be copied to localPtrUptrt[6], if noOfIndices >= 7.
+i7 (bits 24~31): originalUptrt[i7] will be copied to localPtrUptrt[7], if noOfIndices >= 8.
+
localPtrUptrt
+
This address shall be 2-byte aligned.
+Caller shall allocate at least noOfIndices 2-byte entries in this table.
+
+
+
+
+
PKC properties
+
+
UPTRT
+
This function will retrieve the original UPTRT address and return it to caller via oldPtrUptrt.
+This function will overwrite this address by localPtrUptrt.
+
PS1 lengths
+
Unused.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
This function shall not be called during a running FUP program (i.e., GOANY bit is set). Caller shall call mcuxClPkc_WaitForReady before calling this function, if a FUP program has been called.
+
+
+
+ +
+
+ +

◆ mcuxClMath_LeadingZeros()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClMath_LeadingZeros (uint8_t iX,
uint32_t * pNumLeadingZeros 
)
+
+ +

Counts number of leading zero bits of a PKC operand.

+

This function counts the number of leading zero bits of a PKC operand at offset UPTRT[iX] and of size PS1 OPLEN.

+
Parameters
+ + + +
[in]iXindex of PKC operand
[out]pNumLeadingZerospointer to where the number of leading zero bits will be stored
+
+
+
+
Parameter properties
+
+
iX
+
index of X (PKC operand), size = operandSize.
+The offset (UPTRT[iX]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
This function will not use PKC, and assumes PKC will not modify the operand iX simultaneously.
+
+
+
+ +
+
+ +

◆ mcuxClMath_TrailingZeros()

+ +
+
+ + + + + + + + +
uint32_t mcuxClMath_TrailingZeros (uint8_t iX)
+
+ +

Counts number of trailing zero bits of a PKC operand.

+

This function counts the number of trailing zero bits of a PKC operand at offset UPTRT[iX] and of size PS1 OPLEN.

+
Parameters
+ + +
[in]iXindex of PKC operand
+
+
+
+
Parameter properties
+
+
iX
+
index of X (PKC operand), size = operandSize.
+The offset (UPTRT[iX]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
This function will not use PKC, and assumes PKC will not modify the operand iX simultaneously.
+
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + +
#numTrailingZeroesNumber of trailing zeroes
+
+
+ +
+
+ +

◆ mcuxClMath_ShiftModulus()

+ +
+
+ + + + + + + + +
void mcuxClMath_ShiftModulus (uint16_t iNShifted_iN)
+
+ +

Prepares shifted modulus.

+

This function left shifts modulus (PKC operand iN) until there is no leading zero and stores the result in PKC operand iNShifted.

+
Parameters
+ + +
[in]iNShifted_iNindices of PKC operands
+
+
+
+
Parameter properties
+
+
iNShifted_iN
+
iN (bits 0~7): index of modulus (PKC operand), size = operandSize.
+The modulus shall be non-zero.
+The offset (UPTRT[iN]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+iNShifted (bits 8~15): index of shifted modulus (PKC operand), size = operandSize.
+This function supports in-place operation, i.e., iNShifted = iN.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_NDash()

+ +
+
+ + + + + + + + +
void mcuxClMath_NDash (uint16_t iN_iT)
+
+ +

Prepares modulus (calculates NDash) for PKC modular multiplication.

+

This function calculates NDash = (-modulus)^(-1) mod 256^(MCUXCLPKC_WORDSIZE) and stores NDash in the PKC word in front of the PKC operand of modulus (iN).

+
Parameters
+ + +
[in]iN_iTindices of PKC operands
+
+
+
+
Parameter properties
+
+
iN_iT
+
iT (bits 0~7): index of temp (PKC operand).
+The size of temp shall be at least (2 * MCUXCLPKC_WORDSIZE).
+iN (bits 8~15): index of modulus (PKC operand).
+The modulus shall be an odd number.
+The result NDash will be stored in the PKC word before modulus, i.e., at the offset, (UPTRT[iN] - MCUXCLPKC_WORDSIZE).
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
Unused.
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_QDash()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClMath_QDash (uint32_t iQDash_iNShifted_iN_iT,
uint16_t length 
)
+
+ +

Calculates QDash = Q * Q' mod n, where Q = 256^(operandSize) mod n, and Q' = 256^length mod n.

+

This function computes QDash which can be used to convert a PKC operand (of the size length) to its Montgomery representation (of the size operandSize).

+
Parameters
+ + + +
[in]iQDash_iNShifted_iN_iTindices of PKC operands
[in]lengthspecify Q' = 256^length mod n
+
+
+
+
Parameter properties
+
+
iQDash_iNShifted_iN_iT
+
iT (bits 0~7): index of temp (PKC operand).
+The size of temp shall be at least (operandSize + MCUXCLPKC_WORDSIZE).
+iN (bits 8~15): index of modulus (PKC operand), size = operandSize.
+NDash of modulus shall be stored in the PKC word before modulus.
+iNShifted (bits 16~23): index of shifted modulus (PKC operand), size = operandSize.
+If there is no leading zero in the PKC operand modulus, it can be iN.
+iQDash (bits 24~31): index of result QDash (PKC operand), size = operandSize.
+QDash might be greater than modulus.
+
length
+
It shall be nonzero. A zero length will cause undefined behavior.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN = MCLEN defines operandSize.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_QSquared()

+ +
+
+ + + + + + + + +
void mcuxClMath_QSquared (uint32_t iQSqr_iNShifted_iN_iT)
+
+ +

Calculates QSquared = Q^2 mod n, where Q = 256^(operandSize) mod n.

+

This function computes QSquared which can be used to convert a PKC operand to its Montgomery representation (both are of the size operandSize).

+
Parameters
+ + +
[in]iQSqr_iNShifted_iN_iTindices of PKC operands
+
+
+
+
Parameter properties
+
+
iQSqr_iNShifted_iN_iT
+
iT (bits 0~7): index of temp (PKC operand).
+The size of temp shall be at least (operandSize + MCUXCLPKC_WORDSIZE).
+iN (bits 8~15): index of modulus (PKC operand), size = operandSize.
+NDash of modulus shall be stored in the PKC word before modulus.
+iNShifted (bits 16~23): index of shifted modulus (PKC operand), size = operandSize.
+If there is no leading zero in the PKC operand modulus, it can be iN.
+iQSqr (bits 24~31): index of result QSquared (PKC operand), size = operandSize.
+QSquared might be greater than modulus.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN = MCLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_ModInv()

+ +
+
+ + + + + + + + +
void mcuxClMath_ModInv (uint32_t iR_iX_iN_iT)
+
+ +

Calculates modular inversion, with odd modulus.

+

This function calculates modular inversion, result = X^(-1) mod n.

+
Parameters
+ + +
[in]iR_iX_iN_iTindices of PKC operands
+
+
+
+
Parameter properties
+
+
iR_iX_iN_iT
+
iT (bits 0~7): index of temp (PKC operand).
+Its size shall be at least (operandSize + MCUXCLPKC_WORDSIZE).
+The offset (UPTRT[iT]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+iN (bits 8~15): index of modulus (PKC operand), size = operandSize.
+NDash of modulus shall be stored in the PKC word before modulus.
+iX (bits 16~23): index of X (PKC operand), size = operandSize.
+X will be destroyed by this function.
+X and the modulus shall be coprime, otherwise the result will be incorrect.
+iR (bits 24~31): index of result (PKC operand).
+Its size shall be at least (operandSize + MCUXCLPKC_WORDSIZE).
+The offset (UPTRT[iR]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+The result fits in operandSize, but might be greater than modulus.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN = MCLEN defines operandSize.
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_ReduceModEven()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClMath_ReduceModEven (uint32_t iR_iX_iN_iT0,
uint32_t iT1_iT2_iT3 
)
+
+ +

Calculates modular reduction with even modulus.

+

This function calculates modular reduction result = X mod n, where the modulus n is even.

+
Parameters
+ + + +
[in]iR_iX_iN_iT0indices of PKC operands
[in]iT1_iT2_iT3indices of PKC operands
+
+
+
+
Parameter properties
+
+
iR_iX_iN_iT0
+
iT0 (bits 0~7): index of temp0 (PKC operand).
+Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+The operand of modulus can be used as temp0 (i.e., iT0 = iN), but the modulus will be destroyed.
+iN (bits 8~15): index of modulus (PKC operand), size = lenN.
+The offset (UPTRT[iN]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+iX (bits 16~23): index of X (PKC operand).
+Its size shall be at least (lenX + MCUXCLPKC_WORDSIZE).
+iR (bits 24~31): index of result (PKC operand).
+Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+
iT1_iT2_iT3
+
iT3 (bits 0~7): index of temp3 (PKC operand).
+Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+iT2 (bits 8~15): index of temp2 (PKC operand).
+Its size shall be at least lenN.
+iT1 (bits 16~23): index of temp1 (PKC operand).
+Its size shall be at least lenN.
+The operand of result can be used as temp1 (i.e., iT1 = iR). TODO: always use R (any reason not using R?)
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN defines lenN (length of modulus n), and MCLEN defines lenX (length of X).
+Both OPLEN and MCLEN shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_ModExp_SqrMultL2R()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMath_ModExp_SqrMultL2R (const uint8_t * pExp,
uint32_t expByteLength,
uint32_t iR_iX_iN_iT 
)
+
+ +

Calculates modular exponentiation.

+

This function calculates modular exponentiation with left-to-right binary square-and-multiply algorithm.

+
Parameters
+ + + + +
[in]pExppointer to exponent
[in]expByteLengthbyte length of exponent
[in]iR_iX_iN_iTindices of PKC operands
+
+
+
+
Parameter properties
+
+
pExp
+
the exponent is a big-endian octet string and shall be non-zero.
+
iR_iX_iN_iT
+
iT (bits 0~7): index of temp operand (PKC operand).
+Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+iN (bits 8~15): index of modulus (PKC operand), size = operandSize.
+NDash of modulus shall be stored in the PKC word before modulus.
+iX (bits 16~23): index of base number (PKC operand), size = operandSize. iR (bits 24~31): index of result (PKC operand).
+Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN = MCLEN defines operandSize.
+
PS2 lengths
+
Unused.
+
ACTIV/GOANY
+
The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_SecModExp()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClMath_Status_t mcuxClMath_SecModExp (mcuxClSession_Handle_t session,
const uint8_t * pExp,
uint32_t * pExpTemp,
uint32_t expByteLength,
uint32_t iT3_iX_iT2_iT1,
uint32_t iN_iTE_iT0_iR,
uint32_t secOption 
)
+
+ +

Securely calculates modular exponentiation.

+

This function calculates modular exponentiation in a secure manner. It randomizes the computation by Euclidean splitting: exponent = b * q + r, where b is a 64-bit odd random number (with both MSbit and LSbit set), and r = exponent % b. The exponentiation is calculated by two steps: (1) m0 = m^q mod n; and (2) result = m0^b * m^r mod n. In addition, base operands are re-randomized, by adding random multiples of the modulus to them before performing modular multiplications.

+
Parameters
+ + + + + + + + +
[in]pSessionhandle for the current CL session.
[in]pExppointer to exponent
[in]pExpTemppointer to temporary buffer
[in]expByteLengthbyte length of exponent
[in]iT3_iX_iT2_iT1indices of PKC operands
[in]iN_iTE_iT0_iRindices of PKC operands
[in]secOptionoption to disable the operand re-randomization
+
+
+
+
Parameter properties
+
+
session:
+
The session pointed to by pSession has to be initialized prior to a call to this function.
+
pExp
+
the exponent is a big-endian octet string and shall be non-zero.
+
pExpTemp
+
the temporary buffer can be in either CPU or PKC workarea.
+It shall be CPU word aligned, and its length shall be a multiple of CPU word and greater than expByteLength.
+It can share the space with exponent (i.e., pExpTemp = pExp), but the exponent will be overwritten.
+
iT3_iX_iT2_iT1
+
iT1 (bits 0~7): index of temp1 (PKC operand).
+Its size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE).
+iT2 (bits 8~15): index of temp2 (PKC operand).
+Its size shall be at least max(lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE).
+iX (bits 16~23): index of base number (PKC operand), size = operandSize + MCUXCLPKC_WORDSIZE (= lenN + MCUXCLPKC_WORDSIZE).
+It will be overwritten.
+iT3 (bits 24~31): index of temp3 (PKC operand).
+Its size shall be at least max(lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE).
+
iN_iTE_iT0_iR
+
iR (bits 0~7): index of result (PKC operand).
+The size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE).
+iT0 (bits 8~15): index of temp0 (PKC operand).
+The size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE).
+iTE (bits 16~23): index of temp4 (PKC operand).
+The size shall be at least (6 * MCUXCLPKC_WORDSIZE).
+iN (bits 24~31): index of modulus (PKC operand), size = operandSize (= lenN).
+The upper 32 bits of N shall be null, which can be obtained for instance by applying 32-bit modulus blinding, or by artificially increasing PS1 lengths and all buffer sizes by 1 PKC word.
+NDash of modulus shall be stored in the PKC word before modulus.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
PS1 OPLEN = MCLEN defines operandSize = MCUXCLPKC_ROUNDUP_SIZE(lenN), where lenN is the length of modulus n. As the upper 32 bits of N should be null, operandSize >= lenN + 4 bytes.
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller. The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+
Returns
A code-flow protected error code (see Flow Protection API)
+
Return values
+ + + +
MCUXCLMATH_STATUS_OKfunction executed successfully
MCUXCLMATH_STATUS_ERRORerror occurred during operation
+
+
+
Attention
This function uses PRNG which has to be initialized prior to calling the function.
+ +
+
+ +

◆ mcuxClMath_ExactDivideOdd()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMath_ExactDivideOdd (uint32_t iR_iX_iY_iT,
uint32_t xPkcByteLength,
uint32_t yPkcByteLength 
)
+
+ +

Calculates exact division with odd divisor.

+

This function calculates exact division R = X/Y, where divisor Y is odd and dividend X shall be exactly a multiple of Y. If X is not a multiple of Y, result will be incorrect.

+
Parameters
+ + + + +
[in]iR_iX_iY_iTindices of PKC operands
[in]xPkcByteLengthlength of X
[in]yPkcByteLengthlength of Y
+
+
+
+
Parameter properties
+
+
iR_iX_iY_iT
+
iT (bits 0~7): index of temp (PKC operand).
+Its size shall be at least (3 * MCUXCLPKC_WORDSIZE).
+The offset (UPTRT[iT]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+iY (bits 8~15): index of divisor Y (PKC operand), size = yPkcByteLength.
+The most significant PKC word of Y shall be nonzero.
+iX (bits 16~23): index of dividend X (PKC operand), size = xPkcByteLength.
+X will be destroyed by this function.
+CAUTION: if xPkcByteLength = MCUXCLPKC_WORDSIZE, this function will access to (read) one extra PKC word of X, i.e., X[MCUXCLPKC_WORDSIZE ~ 2*MCUXCLPKC_WORDSIZE - 1]. The value of this PKC word will not affect correctness of the result, but caller shall ensure that this PKC word is accessible by PKC.
+iR (bits 24~31): index of result R (PKC operand), size = (xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE).
+
xPkcByteLength
+
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+
yPkcByteLength
+
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
Unused (modified and restored in the function).
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+ +

◆ mcuxClMath_ExactDivide()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMath_ExactDivide (uint32_t iR_iX_iY_iT,
uint32_t xPkcByteLength,
uint32_t yPkcByteLength 
)
+
+ +

Calculates exact division (supporting even divisor).

+

This function calculates exact division R = X/Y, where dividend X shall be exactly a multiple of divisor Y. If X is not a multiple of Y, result will be incorrect.

+

This function trims trailing zero bits of Y and gets Y' = Y >> trailingZeros(Y), and X' = X >> ((trailingZeros(Y) / 8*MCUXCLPKC_WORDSIZE) * 8*MCUXCLPKC_WORDSIZE). It relies on mcuxClMath_ExactDivideOdd to calculate R' = X'/Y', and then calculates R = R' >> (trailingZeros(Y) % (8*MCUXCLPKC_WORDSIZE)).

+
Parameters
+ + + + +
[in]iR_iX_iY_iTPointer table indices of parameters
[in]xPkcByteLengthlength of X
[in]yPkcByteLengthlength of Y
+
+
+
+
Parameter properties
+
+
iR_iX_iY_iT
+
iT (bits 0~7): index of temp (PKC operand).
+Its size shall be at least (3 * MCUXCLPKC_WORDSIZE).
+iY (bits 8~15): index of divisor Y (PKC operand), size = yPkcByteLength.
+The most significant PKC word of Y shall be nonzero.
+The offset (UPTRT[iY]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+iX (bits 16~23): index of dividend X (PKC operand), size = xPkcByteLength.
+X will be destroyed by this function.
+CAUTION: if the length of trimmed X' is MCUXCLPKC_WORDSIZE, this function will access to (read) one extra PKC word of X, i.e., X[xPkcByteLength ~ xPkcByteLength + MCUXCLPKC_WORDSIZE - 1]. The value of this PKC word will not affect correctness of the result, but caller shall ensure that this PKC word is accessible by PKC. If caller cannot guarantee the length of trimmed X' greater than MCUXCLPKC_WORDSIZE, X shall be stored in buffer of the size, xPkcByteLength + MCUXCLPKC_WORDSIZE.
+iR (bits 24~31): index of result R (PKC operand). Its buffer size shall be at least (xPkcByteLength - yPkcByteLength + 2*MCUXCLPKC_WORDSIZE). The result fits in size = (xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE).
+
xPkcByteLength
+
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+
yPkcByteLength
+
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+
+
PKC properties
+
+
PS1 lengths
+
Unused (modified and restored in the function).
+
PS2 lengths
+
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+
ACTIV/GOANY
+
mcuxClPkc_WaitForReady will be called before returning to caller.
+The PKC calculation might be still on-going, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00806.js b/components/els_pkc/doc/mcxn/html/a00806.js new file mode 100644 index 000000000..8f3c403c5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00806.js @@ -0,0 +1,36 @@ +var a00806 = +[ + [ "MCUXCLMATH_SHIFTMODULUS", "a00806.html#gaadd4485b0f1db32b6da6e6b7a2e6cc11", null ], + [ "MCUXCLMATH_FP_SHIFTMODULUS", "a00806.html#ga35df7cdad4c81c5e276f373c70c571d0", null ], + [ "MCUXCLMATH_NDASH", "a00806.html#gab588855e23f750a4c9f7533b54a11325", null ], + [ "MCUXCLMATH_FP_NDASH", "a00806.html#gafa0d390f4eb5728edfd764936aeee313", null ], + [ "MCUXCLMATH_QDASH", "a00806.html#ga666d3347d6f96a09b791355e596de46d", null ], + [ "MCUXCLMATH_FP_QDASH", "a00806.html#ga7703703d552c5446acdf38d82cd81971", null ], + [ "MCUXCLMATH_QSQUARED", "a00806.html#ga4ee6d9b078ecc35a081a3a8cdbec0968", null ], + [ "MCUXCLMATH_FP_QSQUARED", "a00806.html#gadcd348426e9998703dc6f93194a62f80", null ], + [ "MCUXCLMATH_MODINV", "a00806.html#gaa59866fd485a59868a2a594a5858f1de", null ], + [ "MCUXCLMATH_FP_MODINV", "a00806.html#gab456571414ef2f49a91b61f0c91009ba", null ], + [ "MCUXCLMATH_REDUCEMODEVEN", "a00806.html#ga3ee39987ba7de0e36abc848d77b4eaa3", null ], + [ "MCUXCLMATH_FP_REDUCEMODEVEN", "a00806.html#gaed2b24ff10b916eb07a842a2a05ad341", null ], + [ "MCUXCLMATH_MODEXP_SQRMULTL2R", "a00806.html#ga82842f4b45c0d86e4c2d6d29e23c259b", null ], + [ "MCUXCLMATH_FP_MODEXP_SQRMULTL2R", "a00806.html#ga9f0c8d67f0c192341fbf9ac436f02173", null ], + [ "MCUXCLMATH_SECMODEXP", "a00806.html#ga3e0168ff93f7bffd7d56ce509ba29c59", null ], + [ "MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION", "a00806.html#ga32eaa55458996d636a82ac9bda34e3e0", null ], + [ "MCUXCLMATH_EXACTDIVIDEODD", "a00806.html#gae807c4ed789f67aa150addbae31de180", null ], + [ "MCUXCLMATH_FP_EXACTDIVIDEODD", "a00806.html#gaf1d62616daa224745d2ed40fdfa4d724", null ], + [ "MCUXCLMATH_EXACTDIVIDE", "a00806.html#gae99e5e55dda4387e4384e974a112a760", null ], + [ "MCUXCLMATH_FP_EXACTDIVIDE", "a00806.html#ga4dd21ea08b92f104bd3d9bff5ce7efe7", null ], + [ "mcuxClMath_InitLocalUptrt", "a00806.html#ga716b9990024e2ea5e5984ca960a5e861", null ], + [ "mcuxClMath_LeadingZeros", "a00806.html#ga91e4885b266c16938e04aa036eae6977", null ], + [ "mcuxClMath_TrailingZeros", "a00806.html#ga0203db0be2a5c09157c0db697cc2685f", null ], + [ "mcuxClMath_ShiftModulus", "a00806.html#ga65003277bfc2c6eb64be0f23261cadd7", null ], + [ "mcuxClMath_NDash", "a00806.html#ga47ca58caa097e65c0925aa488f287a1e", null ], + [ "mcuxClMath_QDash", "a00806.html#ga61ef022af097c89154560df0f81b3caa", null ], + [ "mcuxClMath_QSquared", "a00806.html#gae2ad68ea7641a23751583c27ed1d77a7", null ], + [ "mcuxClMath_ModInv", "a00806.html#ga9c01f0090ea0220a735ea6992515cf7a", null ], + [ "mcuxClMath_ReduceModEven", "a00806.html#gadcf87738f49ecf4c39ee725fa6cb88f9", null ], + [ "mcuxClMath_ModExp_SqrMultL2R", "a00806.html#gabdd7a91f84faca1e208c143a25e318f8", null ], + [ "mcuxClMath_SecModExp", "a00806.html#ga5f0ebd971dee31e271c27ae02479ff55", null ], + [ "mcuxClMath_ExactDivideOdd", "a00806.html#ga7aa33c63d602fdb151d3e342284b2171", null ], + [ "mcuxClMath_ExactDivide", "a00806.html#ga9416369d37627425ecac95580d1c3ee4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00807.html b/components/els_pkc/doc/mcxn/html/a00807.html new file mode 100644 index 000000000..57e8df4c8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00807.html @@ -0,0 +1,265 @@ + + + + + + + +MCUX CLNS: mcuxClMath_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Typedefs
+
+
mcuxClMath_Macros
mcuxClMath
+
+
+ +

Defines all macros of mcuxClMath. +More...

+ + + + + + + + + + + + + + + +

+Macros

#define MCUXCLMATH_STATUS_OK
 Math operation successful. More...
 
#define MCUXCLMATH_ERRORCODE_OK
 
#define MCUXCLMATH_STATUS_ERROR
 Error occurred during Math operation. More...
 
#define MCUXCLMATH_ERRORCODE_ERROR
 
#define MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND
 Option to disable the operand re-randomization in the secure modular exponentiation. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClMath_Status_t
 Type for error codes used by Math component functions. More...
 
typedef mcuxClMath_Status_t mcuxClMath_Status_Protected_t
 Deprecated type for error codes used by code-flow protected Math component functions. More...
 
+

Detailed Description

+

Defines all macros of mcuxClMath.

+

Macro Definition Documentation

+ +

◆ MCUXCLMATH_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLMATH_STATUS_OK
+
+ +

Math operation successful.

+ +
+
+ +

◆ MCUXCLMATH_ERRORCODE_OK

+ +
+
+ + + + +
#define MCUXCLMATH_ERRORCODE_OK
+
+ +
+
+ +

◆ MCUXCLMATH_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLMATH_STATUS_ERROR
+
+ +

Error occurred during Math operation.

+ +
+
+ +

◆ MCUXCLMATH_ERRORCODE_ERROR

+ +
+
+ + + + +
#define MCUXCLMATH_ERRORCODE_ERROR
+
+ +
+
+ +

◆ MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND

+ +
+
+ + + + +
#define MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND
+
+ +

Option to disable the operand re-randomization in the secure modular exponentiation.

+

TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption to always re-randomize

+ +
+
+

Typedef Documentation

+ +

◆ mcuxClMath_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClMath_Status_t
+
+ +

Type for error codes used by Math component functions.

+ +
+
+ +

◆ mcuxClMath_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClMath_Status_t mcuxClMath_Status_Protected_t
+
+ +

Deprecated type for error codes used by code-flow protected Math component functions.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00807.js b/components/els_pkc/doc/mcxn/html/a00807.js new file mode 100644 index 000000000..c56c10eca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00807.js @@ -0,0 +1,10 @@ +var a00807 = +[ + [ "MCUXCLMATH_STATUS_OK", "a00807.html#ga745dd2a8966d1760f3475089b2f7aa47", null ], + [ "MCUXCLMATH_ERRORCODE_OK", "a00807.html#gacc4f37c95272b523a0ca1eca8d2e3735", null ], + [ "MCUXCLMATH_STATUS_ERROR", "a00807.html#ga6e43ca61303440dc7e9a83fbe9cce4d3", null ], + [ "MCUXCLMATH_ERRORCODE_ERROR", "a00807.html#ga1427ab8cd82a164dee226ae554894772", null ], + [ "MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND", "a00807.html#ga81bd9ab98d67ca3c7e944ad922d1d353", null ], + [ "mcuxClMath_Status_t", "a00807.html#gaf541274a57cf9f823c029f73ff733ae0", null ], + [ "mcuxClMath_Status_Protected_t", "a00807.html#ga0560097c958abffba7b41198a7af6c8b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00808.html b/components/els_pkc/doc/mcxn/html/a00808.html new file mode 100644 index 000000000..691d4dcb0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00808.html @@ -0,0 +1,150 @@ + + + + + + + +MCUX CLNS: mcuxClMemory + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClMemory
+
+
+ +

Basic memory operations. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Modules

 mcuxClMemory_Clear
 This function clears a memory region.
 
 mcuxClMemory_Copy
 This function copies a memory region from src to dst.
 
 mcuxClMemory_Copy_Reversed
 This function copies a memory region from src to dst reversely.
 
 mcuxClMemory_Endianness
 These macros implement endianess management on integers.
 
 mcuxClMemory_Set
 This function sets all bytes in a memory region to a specified value.
 
 mcuxClMemory_Types
 Defines all types used by the mcuxClMemory functions.
 
+

Detailed Description

+

Basic memory operations.

+

This component provides memory functions similar to the ones found in the C standard library.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00808.js b/components/els_pkc/doc/mcxn/html/a00808.js new file mode 100644 index 000000000..6f3560d2f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00808.js @@ -0,0 +1,9 @@ +var a00808 = +[ + [ "mcuxClMemory_Clear", "a00809.html", "a00809" ], + [ "mcuxClMemory_Copy", "a00810.html", "a00810" ], + [ "mcuxClMemory_Copy_Reversed", "a00811.html", "a00811" ], + [ "mcuxClMemory_Endianness", "a00812.html", "a00812" ], + [ "mcuxClMemory_Set", "a00813.html", "a00813" ], + [ "mcuxClMemory_Types", "a00814.html", "a00814" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00809.html b/components/els_pkc/doc/mcxn/html/a00809.html new file mode 100644 index 000000000..5281f19eb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00809.html @@ -0,0 +1,257 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Clear + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClMemory_Clear
mcuxClMemory
+
+
+ +

This function clears a memory region. +More...

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, byteLen)
 Helper macro to call mcuxClMemory_clear with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF(pTarget, byteLen, buffLen)
 Helper macro to call mcuxClMemory_clear with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength)
 Overwrites a memory buffer with null bytes. More...
 
+

Detailed Description

+

This function clears a memory region.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_FP_MEMORY_CLEAR

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_CLEAR( pTarget,
 byteLen 
)
+
+ +

Helper macro to call mcuxClMemory_clear with flow protection.

+ +
+
+ +

◆ MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF( pTarget,
 byteLen,
 buffLen 
)
+
+ +

Helper macro to call mcuxClMemory_clear with flow protection with buffer.

+ +
+
+

Function Documentation

+ +

◆ mcuxClMemory_clear()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMemory_clear (uint8_t * pDst,
size_t length,
size_t bufLength 
)
+
+ +

Overwrites a memory buffer with null bytes.

+

If the destination buffer is too small, i.e. if bufLength < length, (length-bufLength) is added to the Flow Protection token (see Flow Protection API).

+
Parameters
+ + + + +
[out]pDstPointer to the buffer to be cleared.
[in]lengthsize (in bytes) to be cleared.
[in]bufLengthbuffer size (if bufLength < length, only bufLength bytes are cleared).
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00809.js b/components/els_pkc/doc/mcxn/html/a00809.js new file mode 100644 index 000000000..ae43429bf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00809.js @@ -0,0 +1,6 @@ +var a00809 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_CLEAR", "a00809.html#ga2dc0fdbb602c3777fffb8515f944d736", null ], + [ "MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF", "a00809.html#ga76dcce466859684502b4725d51d5de4f", null ], + [ "mcuxClMemory_clear", "a00809.html#ga1ac6e8a4335f620d41360c090ee5ce73", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00810.html b/components/els_pkc/doc/mcxn/html/a00810.html new file mode 100644 index 000000000..e6a3c7fa5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00810.html @@ -0,0 +1,279 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClMemory_Copy
mcuxClMemory
+
+
+ +

This function copies a memory region from src to dst. +More...

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, byteLen)
 Helper macro to call mcuxClMemory_copy with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pTarget, pSource, byteLen, buffLen)
 Helper macro to call mcuxClMemory_copy with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
 Copies a memory buffer to another location. More...
 
+

Detailed Description

+

This function copies a memory region from src to dst.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_FP_MEMORY_COPY

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_COPY( pTarget,
 pSource,
 byteLen 
)
+
+ +

Helper macro to call mcuxClMemory_copy with flow protection.

+ +
+
+ +

◆ MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF( pTarget,
 pSource,
 byteLen,
 buffLen 
)
+
+ +

Helper macro to call mcuxClMemory_copy with flow protection with buffer.

+ +
+
+

Function Documentation

+ +

◆ mcuxClMemory_copy()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMemory_copy (uint8_t * pDst,
uint8_t const * pSrc,
size_t length,
size_t bufLength 
)
+
+ +

Copies a memory buffer to another location.

+

The two buffers must not overlap.

+

If the destination buffer is too small, i.e. if bufLength < length, (length-bufLength) is added to the Flow Protection token (see Flow Protection API).

+
Parameters
+ + + + + +
[out]pDstpointer to the buffer to be copied to.
[in]pSrcpointer to the buffer to copy.
[in]lengthsize (in bytes) to be copied.
[in]bufLengthbuffer size (if bufLength < length, only bufLength bytes are copied).
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00810.js b/components/els_pkc/doc/mcxn/html/a00810.js new file mode 100644 index 000000000..a427bd530 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00810.js @@ -0,0 +1,6 @@ +var a00810 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_COPY", "a00810.html#ga5d16560ac24ef6ba2dae129206e70208", null ], + [ "MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF", "a00810.html#gaab249829be1231ec5f08f90093943a40", null ], + [ "mcuxClMemory_copy", "a00810.html#gab564183ab5f02cf11b66b6244ba2112a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00811.html b/components/els_pkc/doc/mcxn/html/a00811.html new file mode 100644 index 000000000..6d3fe68b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00811.html @@ -0,0 +1,231 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Copy_Reversed + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClMemory_Copy_Reversed
mcuxClMemory
+
+
+ +

This function copies a memory region from src to dst reversely. +More...

+ + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pTarget, pSource, byteLen)
 Helper macro to call mcuxClMemory_copy_reversed with flow protection. More...
 
+ + + + +

+Functions

void mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength)
 Copies a memory buffer to another location reversely. More...
 
+

Detailed Description

+

This function copies a memory region from src to dst reversely.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED( pTarget,
 pSource,
 byteLen 
)
+
+ +

Helper macro to call mcuxClMemory_copy_reversed with flow protection.

+ +
+
+

Function Documentation

+ +

◆ mcuxClMemory_copy_reversed()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMemory_copy_reversed (uint8_t * pDst,
uint8_t const * pSrc,
size_t length,
size_t bufLength 
)
+
+ +

Copies a memory buffer to another location reversely.

+

If the destination buffer is too small, i.e. if bufLength < length, then only bufLength bytes are copied reversely.

+
Parameters
+ + + + + +
[out]pDstpointer to the buffer to be copied to.
[in]pSrcpointer to the buffer to copy.
[in]lengthsize (in bytes) to be copied.
[in]bufLengthbuffer size (if bufLength < length, only bufLength bytes are copied reversely).
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00811.js b/components/els_pkc/doc/mcxn/html/a00811.js new file mode 100644 index 000000000..bf89d577b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00811.js @@ -0,0 +1,5 @@ +var a00811 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED", "a00811.html#ga34f4a48eda22ae64759db5d7893d0c36", null ], + [ "mcuxClMemory_copy_reversed", "a00811.html#gafc918d181009c3af7638604e5e4b9281", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00812.html b/components/els_pkc/doc/mcxn/html/a00812.html new file mode 100644 index 000000000..a2d6aa7d5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00812.html @@ -0,0 +1,302 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Endianness + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClMemory_Endianness
mcuxClMemory
+
+
+ +

These macros implement endianess management on integers. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define mcuxClMemory_StoreLittleEndian32(destination, value)
 Converts a 32-bit unsigned integer to a little-endian order uint8_t array . More...
 
#define mcuxClMemory_StoreBigEndian32(destination, value)
 Converts a 32-bit unsigned integer to a big-endian order uint8_t array. More...
 
#define mcuxClMemory_LoadLittleEndian32(source)
 Converts a little-endian order uint8_t array to a 32-bit unsigned integer. More...
 
#define mcuxClMemory_LoadBigEndian32(source)
 Converts a big-endian order uint8_t array to a 32-bit unsigned integer. More...
 
#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input)
 MACRO that switches byte endianness of given CPU word. More...
 
+

Detailed Description

+

These macros implement endianess management on integers.

+

Macro Definition Documentation

+ +

◆ mcuxClMemory_StoreLittleEndian32

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define mcuxClMemory_StoreLittleEndian32( destination,
 value 
)
+
+ +

Converts a 32-bit unsigned integer to a little-endian order uint8_t array .

+
Note
Implementation is platform independent.
+
Parameters
+ + + +
[out]destinationpointer to a 4 byte buffer were 32-bit integer in little-endian will be encoded.
[in]valuepointer to the 32-bit integer to be encoded.
+
+
+ +
+
+ +

◆ mcuxClMemory_StoreBigEndian32

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define mcuxClMemory_StoreBigEndian32( destination,
 value 
)
+
+ +

Converts a 32-bit unsigned integer to a big-endian order uint8_t array.

+
Note
Implementation is platform independent.
+
Parameters
+ + +
[in]sourcepointer to a 4 byte big-endian order uint8_t buffer that will be converted to an unsigned integer
+
+
+ +
+
+ +

◆ mcuxClMemory_LoadLittleEndian32

+ +
+
+ + + + + + + + +
#define mcuxClMemory_LoadLittleEndian32( source)
+
+ +

Converts a little-endian order uint8_t array to a 32-bit unsigned integer.

+
Note
Implementation is platform independent.
+
Parameters
+ + +
[in]sourcepointer to a 4 byte little-endian order uint8_t buffer that will be converted to an unsigned integer
+
+
+ +
+
+ +

◆ mcuxClMemory_LoadBigEndian32

+ +
+
+ + + + + + + + +
#define mcuxClMemory_LoadBigEndian32( source)
+
+ +

Converts a big-endian order uint8_t array to a 32-bit unsigned integer.

+
Parameters
+ + +
[in]destinationpointer to a 4 byte buffer were 32-bit integer in big-endian will be decoded.
+
+
+
Returns
a 32-bit unsigned integer
+ +
+
+ +

◆ MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS

+ +
+
+ + + + + + + + +
#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS( input)
+
+ +

MACRO that switches byte endianness of given CPU word.

+
Parameters
+ + +
[in]inputa 32-bit unsigned integer whose endianness will be reversed.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00812.js b/components/els_pkc/doc/mcxn/html/a00812.js new file mode 100644 index 000000000..8c8127398 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00812.js @@ -0,0 +1,8 @@ +var a00812 = +[ + [ "mcuxClMemory_StoreLittleEndian32", "a00812.html#gaef4886d199c2539b209458a8c62378cd", null ], + [ "mcuxClMemory_StoreBigEndian32", "a00812.html#ga84f8097975ebea39deaea4ab9306d2ce", null ], + [ "mcuxClMemory_LoadLittleEndian32", "a00812.html#gaa3eba98f422623a6a02f15898449c874", null ], + [ "mcuxClMemory_LoadBigEndian32", "a00812.html#gabd3fd1c7ee32c2cd202a67bce5036778", null ], + [ "MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS", "a00812.html#gac426a079f1808ff0183d2851ead720c5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00813.html b/components/els_pkc/doc/mcxn/html/a00813.html new file mode 100644 index 000000000..46772f71b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00813.html @@ -0,0 +1,278 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Set + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
mcuxClMemory_Set
mcuxClMemory
+
+
+ +

This function sets all bytes in a memory region to a specified value. +More...

+ + + + + + + + +

+Macros

#define MCUXCLMEMORY_FP_MEMORY_SET(pTarget, val, byteLen)
 Helper macro to call mcuxClMemory_set with flow protection. More...
 
#define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pTarget, val, byteLen, buffLen)
 Helper macro to call mcuxClMemory_set with flow protection with buffer. More...
 
+ + + + +

+Functions

void mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength)
 Sets all bytes of a memory buffer to a specified value. More...
 
+

Detailed Description

+

This function sets all bytes in a memory region to a specified value.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_FP_MEMORY_SET

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_SET( pTarget,
 val,
 byteLen 
)
+
+ +

Helper macro to call mcuxClMemory_set with flow protection.

+ +
+
+ +

◆ MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF( pTarget,
 val,
 byteLen,
 buffLen 
)
+
+ +

Helper macro to call mcuxClMemory_set with flow protection with buffer.

+ +
+
+

Function Documentation

+ +

◆ mcuxClMemory_set()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClMemory_set (uint8_t * pDst,
uint8_t val,
size_t length,
size_t bufLength 
)
+
+ +

Sets all bytes of a memory buffer to a specified value.

+

If the destination buffer is too small, i.e. if bufLength < length, (length-bufLength) is added to the Flow Protection token (see Flow Protection API).

+
Parameters
+ + + + + +
[out]pDstpointer to the buffer to be set.
[in]valbyte value to be set.
[in]lengthsize (in bytes) to be set.
[in]bufLengthbuffer size (if bufLength < length, only bufLength bytes are set).
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00813.js b/components/els_pkc/doc/mcxn/html/a00813.js new file mode 100644 index 000000000..96f3248c4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00813.js @@ -0,0 +1,6 @@ +var a00813 = +[ + [ "MCUXCLMEMORY_FP_MEMORY_SET", "a00813.html#ga039e0b482faab4d1aabe2dd5c79d3eb5", null ], + [ "MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF", "a00813.html#gad65a5023a0b0263462b6cfcd6761b904", null ], + [ "mcuxClMemory_set", "a00813.html#ga5d86af41c30044c28809914e2901884d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00814.html b/components/els_pkc/doc/mcxn/html/a00814.html new file mode 100644 index 000000000..e9a912ed6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00814.html @@ -0,0 +1,178 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Typedefs
+
+
mcuxClMemory_Types
mcuxClMemory
+
+
+ +

Defines all types used by the mcuxClMemory functions. +More...

+ + + + + +

+Modules

 mcuxClMemory_Types_Macros
 Defines all macros of mcuxClMemory_Types.
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClMemory_Status_t
 Type for error codes of mcuxClMemory component functions. More...
 
typedef mcuxClMemory_Status_t mcuxClMemory_Status_Protected_t
 Deprecated type for error codes used by code-flow protected mcuxClMemory component functions. More...
 
+

Detailed Description

+

Defines all types used by the mcuxClMemory functions.

+

Typedef Documentation

+ +

◆ mcuxClMemory_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClMemory_Status_t
+
+ +

Type for error codes of mcuxClMemory component functions.

+

Type returned by mcuxClMemory functions. See MCUXCLMEMORY_STATUS_ for possible options.

+ +
+
+ +

◆ mcuxClMemory_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClMemory_Status_t mcuxClMemory_Status_Protected_t
+
+ +

Deprecated type for error codes used by code-flow protected mcuxClMemory component functions.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00814.js b/components/els_pkc/doc/mcxn/html/a00814.js new file mode 100644 index 000000000..6f16cb0de --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00814.js @@ -0,0 +1,6 @@ +var a00814 = +[ + [ "mcuxClMemory_Types_Macros", "a00815.html", "a00815" ], + [ "mcuxClMemory_Status_t", "a00814.html#gad25887c99517f13c547e1d2bf027ccd1", null ], + [ "mcuxClMemory_Status_Protected_t", "a00814.html#ga57c9ba76c62b4ad9bd565df4a98c19ba", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00815.html b/components/els_pkc/doc/mcxn/html/a00815.html new file mode 100644 index 000000000..7ae575e56 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00815.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: mcuxClMemory_Types_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
mcuxClMemory_Types_Macros
mcuxClMemory » mcuxClMemory_Types
+
+
+ +

Defines all macros of mcuxClMemory_Types. +More...

+ + + + + +

+Modules

 MCUXCLMEMORY_STATUS_
 Defines valid mcuxClMemory function return codes.
 
+ + + + + + + +

+Macros

#define MCUXCLMEMORY_API
 Marks a function as a public API function of the mcuxClMemory component. More...
 
#define MCUXCLMEMORY_ERRORCODE_OK
 Memory operation successful. More...
 
+

Detailed Description

+

Defines all macros of mcuxClMemory_Types.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_API

+ +
+
+ + + + +
#define MCUXCLMEMORY_API
+
+ +

Marks a function as a public API function of the mcuxClMemory component.

+ +
+
+ +

◆ MCUXCLMEMORY_ERRORCODE_OK

+ +
+
+ + + + +
#define MCUXCLMEMORY_ERRORCODE_OK
+
+ +

Memory operation successful.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00815.js b/components/els_pkc/doc/mcxn/html/a00815.js new file mode 100644 index 000000000..66c9b249b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00815.js @@ -0,0 +1,6 @@ +var a00815 = +[ + [ "MCUXCLMEMORY_STATUS_", "a00816.html", "a00816" ], + [ "MCUXCLMEMORY_API", "a00815.html#ga2469abde1e59b6b478ba8c393dc3e95a", null ], + [ "MCUXCLMEMORY_ERRORCODE_OK", "a00815.html#ga0e92b528eed7533fedddfc3172c60fa8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00816.html b/components/els_pkc/doc/mcxn/html/a00816.html new file mode 100644 index 000000000..8b748f0e5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00816.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: MCUXCLMEMORY_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLMEMORY_STATUS_
mcuxClMemory » mcuxClMemory_Types » mcuxClMemory_Types_Macros
+
+
+ +

Defines valid mcuxClMemory function return codes. +More...

+ + + + + +

+Macros

#define MCUXCLMEMORY_STATUS_OK
 Memory operation successful. More...
 
+

Detailed Description

+

Defines valid mcuxClMemory function return codes.

+

Macro Definition Documentation

+ +

◆ MCUXCLMEMORY_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLMEMORY_STATUS_OK
+
+ +

Memory operation successful.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00816.js b/components/els_pkc/doc/mcxn/html/a00816.js new file mode 100644 index 000000000..b44da60c7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00816.js @@ -0,0 +1,4 @@ +var a00816 = +[ + [ "MCUXCLMEMORY_STATUS_OK", "a00816.html#ga0a6eff5e1bb27d6c237a16f7d60b9eb9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00817.html b/components/els_pkc/doc/mcxn/html/a00817.html new file mode 100644 index 000000000..ae7af79e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00817.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClOsccaPkc
+
+
+ +

component of PKC hardware driver +More...

+ + + + + +

+Modules

 mcuxClOsccaPkc_Functions
 Defines all functions of mcuxClOsccaPkc.
 
+

Detailed Description

+

component of PKC hardware driver

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00817.js b/components/els_pkc/doc/mcxn/html/a00817.js new file mode 100644 index 000000000..03d516220 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00817.js @@ -0,0 +1,4 @@ +var a00817 = +[ + [ "mcuxClOsccaPkc_Functions", "a00818.html", "a00818" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00818.html b/components/els_pkc/doc/mcxn/html/a00818.html new file mode 100644 index 000000000..805d2505f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00818.html @@ -0,0 +1,266 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs | +Functions | +Variables
+
+
mcuxClOsccaPkc_Functions
mcuxClOsccaPkc
+
+
+ +

Defines all functions of mcuxClOsccaPkc. +More...

+ + + + + +

+Data Structures

struct  mcuxClOsccaPkc_State_t
 Structure of PKC state backup. More...
 
+ + + + + + + +

+Typedefs

typedef struct mcuxClOsccaPkc_State_t mcuxClOsccaPkc_State_t
 Structure of PKC state backup. More...
 
typedef const struct mcuxClOsccaPkc_FUPEntry * mcuxClOsccaPkc_PtrFUPEntry_t
 type of FUP program address. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Reset) void mcuxClOsccaPkc_Reset(mcuxClOsccaPkc_State_t *state)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Init) void mcuxClOsccaPkc_Init(mcuxClOsccaPkc_State_t *state)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_SetWordSize) void mcuxClOsccaPkc_SetWordSize(uint32_t redmul)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_GetWordSize) uint32_t mcuxClOsccaPkc_GetWordSize(void)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_WaitforFinish) void mcuxClOsccaPkc_WaitforFinish(void)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_SetFupTable) void mcuxClOsccaPkc_SetFupTable(void *pUPTRT)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_Op) void mcuxClOsccaPkc_Op(uint32_t mode
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_StartFupProgram) void mcuxClOsccaPkc_StartFupProgram(mcuxClOsccaPkc_PtrFUPEntry_t fupProgram
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeNDash) void mcuxClOsccaPkc_ComputeNDash(uint32_t iNiTiXiX)
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeQSquared) void mcuxClOsccaPkc_ComputeQSquared(uint32_t iQiMiTiX
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_GeneratePointerTable) void mcuxClOsccaPkc_GeneratePointerTable(uint16_t *pOperandsBase
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_MultipleShiftRotate_Index) void mcuxClOsccaPkc_MultipleShiftRotate_Index(uint32_t iModuluss
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_LeadingZeros) uint32_t mcuxClOsccaPkc_LeadingZeros(uint8_t *pNum
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_ComputeModInv) void mcuxClOsccaPkc_ComputeModInv(uint32_t iRiIiNiT
 
+ MCUX_CSSL_FP_FUNCTION_DECL (mcuxClOsccaPkc_CalcMontInverse) void mcuxClOsccaPkc_CalcMontInverse(uint32_t iIiRiNiT
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+uint32_t iRiXiYiZ
 
+uint32_t fupProgramSize
 
+uint16_t iMs
 
+uint8_t * pBufferBase
 
+uint8_t uint32_t bufferSize
 
+uint8_t uint32_t uint32_t bufferNums
 
+uint32_t iModulus
 
+uint32_t uint32_t leadingZeroBits
 
+uint32_t uint32_t _Bool shiftLeft
 
+uint32_t numLen
 
+uint32_t iT2
 
+uint32_t R2
 
+

Detailed Description

+

Defines all functions of mcuxClOsccaPkc.

+

Typedef Documentation

+ +

◆ mcuxClOsccaPkc_State_t

+ +
+
+ + + + +
typedef struct mcuxClOsccaPkc_State_t mcuxClOsccaPkc_State_t
+
+ +

Structure of PKC state backup.

+ +
+
+ +

◆ mcuxClOsccaPkc_PtrFUPEntry_t

+ +
+
+ + + + +
typedef const struct mcuxClOsccaPkc_FUPEntry* mcuxClOsccaPkc_PtrFUPEntry_t
+
+ +

type of FUP program address.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00818.js b/components/els_pkc/doc/mcxn/html/a00818.js new file mode 100644 index 000000000..53469e119 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00818.js @@ -0,0 +1,9 @@ +var a00818 = +[ + [ "mcuxClOsccaPkc_State_t", "a01257.html", [ + [ "cfg", "a01257.html#ad7810f1fb9ad33435dd7d916974106c7", null ], + [ "ctrl", "a01257.html#a51cc91fc838fe096cdd99b0fa45184b7", null ] + ] ], + [ "mcuxClOsccaPkc_State_t", "a00818.html#ga83f8544bc01ae0f871addbfe5600e706", null ], + [ "mcuxClOsccaPkc_PtrFUPEntry_t", "a00818.html#gae42a19bfc4e7aaa16fdea5ef1e6bc6c4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00819.html b/components/els_pkc/doc/mcxn/html/a00819.html new file mode 100644 index 000000000..3a12fa83c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00819.html @@ -0,0 +1,129 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3 + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOsccaSm3
+
+
+ +

Hash component. +More...

+

Hash component.

+

The mcuxClOsccaSm3 component implements the Hash functionality supported by CLNS.

+

An example of how to use the mcuxClOsccaSm3 component can be found in /mcuxClOsccaSm3/ex.

+

The mcuxClOsccaSm3 component supports interfaces to either hash a message in one shot (mcuxClOsccaSm3_compute) or to hash it in parts (mcuxClOsccaSm3_init, mcuxClOsccaSm3_process, and mcuxClOsccaSm3_finish). In case of hashing a message in parts, first an initialization has to be performed (mcuxClOsccaSm3_init), followed by zero, one, or multiple updates (mcuxClOsccaSm3_process), followed by a finalization (mcuxClOsccaSm3_finish). The finalization generates the output data (digest) and destroys the context. After the finalization step, no further updates are possible.

+

The targeted hash algorithm is selected by passing one of the offered algorithm mode descriptors (mcuxClOsccaSm3_Modes), which are listed in file mcuxClOsccaSm3_Algorithms.h

+

Note: In case the hashing functionality is based on a hardware co-processor, it might be necessary to initialize the co-processor, before it's use in the mcuxClOsccaSm3 component. Please refer to the example for further information on this.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00820.html b/components/els_pkc/doc/mcxn/html/a00820.html new file mode 100644 index 000000000..901ca0602 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00820.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaSm3_Modes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClOsccaSm3_Modes
+
+
+ +

Hashing modes of the mcuxClOsccaSm3 component. +More...

+

Hashing modes of the mcuxClOsccaSm3 component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00821.html b/components/els_pkc/doc/mcxn/html/a00821.html new file mode 100644 index 000000000..ed40e49e3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00821.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: MCUXCLOSCCASM3_OUTPUT_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLOSCCASM3_OUTPUT_SIZE_
+
+
+ +

Defines for digest sizes. +More...

+ + + + + +

+Macros

#define MCUXCLOSCCASM3_OUTPUT_SIZE_SM3
 SM3 output size: 256 bit (32 bytes) More...
 
+

Detailed Description

+

Defines for digest sizes.

+

Macro Definition Documentation

+ +

◆ MCUXCLOSCCASM3_OUTPUT_SIZE_SM3

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_OUTPUT_SIZE_SM3
+
+ +

SM3 output size: 256 bit (32 bytes)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00821.js b/components/els_pkc/doc/mcxn/html/a00821.js new file mode 100644 index 000000000..9022d848b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00821.js @@ -0,0 +1,4 @@ +var a00821 = +[ + [ "MCUXCLOSCCASM3_OUTPUT_SIZE_SM3", "a00821.html#ga12a91530ea05a544a80b18d4f436d51f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00822.html b/components/els_pkc/doc/mcxn/html/a00822.html new file mode 100644 index 000000000..dc6465337 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00822.html @@ -0,0 +1,284 @@ + + + + + + + +MCUX CLNS: MCUXCLOSCCASM3_WA + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLOSCCASM3_WA
+
+
+ +

Definitions of workarea sizes for the mcuxClOsccaSm3 functions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_compute on SM3. More...
 
#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_compute. More...
 
#define MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required for mcuxClOsccaSm3_init. More...
 
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_process on SM3. More...
 
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_process. More...
 
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3
 Defines the workarea size required for mcuxClOsccaSm3_finish on SM3. More...
 
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX
 Defines the max workarea size required for mcuxClOsccaSm3_finish. More...
 
#define MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE
 Defines the max workarea size required this component. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClOsccaSm3 functions.

+

Macro Definition Documentation

+ +

◆ MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3
+
+ +

Defines the workarea size required for mcuxClOsccaSm3_compute on SM3.

+ +
+
+ +

◆ MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClOsccaSm3_compute.

+ +
+
+ +

◆ MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE
+
+ +

Defines the max workarea size required for mcuxClOsccaSm3_init.

+ +
+
+ +

◆ MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3
+
+ +

Defines the workarea size required for mcuxClOsccaSm3_process on SM3.

+ +
+
+ +

◆ MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClOsccaSm3_process.

+ +
+
+ +

◆ MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3
+
+ +

Defines the workarea size required for mcuxClOsccaSm3_finish on SM3.

+ +
+
+ +

◆ MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX
+
+ +

Defines the max workarea size required for mcuxClOsccaSm3_finish.

+ +
+
+ +

◆ MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE
+
+ +

Defines the max workarea size required this component.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00822.js b/components/els_pkc/doc/mcxn/html/a00822.js new file mode 100644 index 000000000..313dd0e82 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00822.js @@ -0,0 +1,11 @@ +var a00822 = +[ + [ "MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#ga69194394354130bb74c3a659c6a6382a", null ], + [ "MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#gaac9381a82113d329dd25ab934c95dfd5", null ], + [ "MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE", "a00822.html#gab8638606efbce3f6c35b1584e2edf157", null ], + [ "MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#ga44f1d4fbc45ff4047678df48c2673868", null ], + [ "MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#ga7fc2a9c206d05b1b56fdb4a50964e8aa", null ], + [ "MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3", "a00822.html#gac8ba7076a5518d52ce295d48099d4ae3", null ], + [ "MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX", "a00822.html#ga53ef6d92e75dc64d5cdf0bf5cf9c4231", null ], + [ "MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE", "a00822.html#ga92c12b7d0bcd8ebcaf3ffa9bcac45b6b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00823.html b/components/els_pkc/doc/mcxn/html/a00823.html new file mode 100644 index 000000000..8dc19b7e9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00823.html @@ -0,0 +1,173 @@ + + + + + + + +MCUX CLNS: MCUXCLOSCCASM3_CONTEXT + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLOSCCASM3_CONTEXT
+
+
+ +

Definitions of context sizes for the mcuxClOsccaSm3 multi-part functions. +More...

+ + + + + + + + + + +

+Macros

+#define MCUXCLOSCCASM3_CONTEXT_SIZE
 
#define MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS
 Defines the context size for streaming hashing interfaces. More...
 
#define MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE
 Defines the state size required for SM3. More...
 
+

Detailed Description

+

Definitions of context sizes for the mcuxClOsccaSm3 multi-part functions.

+

Macro Definition Documentation

+ +

◆ MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS
+
+ +

Defines the context size for streaming hashing interfaces.

+ +
+
+ +

◆ MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE

+ +
+
+ + + + +
#define MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE
+
+ +

Defines the state size required for SM3.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00823.js b/components/els_pkc/doc/mcxn/html/a00823.js new file mode 100644 index 000000000..4a3467f0d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00823.js @@ -0,0 +1,5 @@ +var a00823 = +[ + [ "MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS", "a00823.html#ga60a96727f7daf1d9762c0c54544e0ca8", null ], + [ "MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE", "a00823.html#ga55b2857bb7c8aec7fb22e3ebab7ebf77", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00824.html b/components/els_pkc/doc/mcxn/html/a00824.html new file mode 100644 index 000000000..56512c52f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00824.html @@ -0,0 +1,209 @@ + + + + + + + +MCUX CLNS: Constants definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Constants definitions
+
+
+ +

Constants used by the Padding component. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLPADDING_STATUS_OK
 Return codes. More...
 
#define MCUXCLPADDING_STATUS_NOT_OK
 Incorrect padding. More...
 
#define MCUXCLPADDING_STATUS_ERROR
 Error occurred during Padding operation. More...
 
#define MCUXCLPADDING_STATUS_FAULT_ATTACK
 Fault attack (unexpected behaviour) detected. More...
 
+

Detailed Description

+

Constants used by the Padding component.

+

Macro Definition Documentation

+ +

◆ MCUXCLPADDING_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLPADDING_STATUS_OK
+
+ +

Return codes.

+

Padding operation successful

+ +
+
+ +

◆ MCUXCLPADDING_STATUS_NOT_OK

+ +
+
+ + + + +
#define MCUXCLPADDING_STATUS_NOT_OK
+
+ +

Incorrect padding.

+ +
+
+ +

◆ MCUXCLPADDING_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLPADDING_STATUS_ERROR
+
+ +

Error occurred during Padding operation.

+ +
+
+ +

◆ MCUXCLPADDING_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLPADDING_STATUS_FAULT_ATTACK
+
+ +

Fault attack (unexpected behaviour) detected.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00824.js b/components/els_pkc/doc/mcxn/html/a00824.js new file mode 100644 index 000000000..e971cbd93 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00824.js @@ -0,0 +1,7 @@ +var a00824 = +[ + [ "MCUXCLPADDING_STATUS_OK", "a00824.html#gad64734c94edeab85fc1d8e05c4134f52", null ], + [ "MCUXCLPADDING_STATUS_NOT_OK", "a00824.html#ga6393900f48c3b32dd379a6ea30bc730a", null ], + [ "MCUXCLPADDING_STATUS_ERROR", "a00824.html#ga27d0fc33860c93a2241e1d6b37a92d94", null ], + [ "MCUXCLPADDING_STATUS_FAULT_ATTACK", "a00824.html#ga4dff5913bd142d42c0a8825ce553bc3c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00825.html b/components/els_pkc/doc/mcxn/html/a00825.html new file mode 100644 index 000000000..06d8b2403 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00825.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: Padding type definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
Padding type definitions
+
+
+ +

Types used by the Padding component. +More...

+ + + + + +

+Typedefs

typedef uint32_t mcuxClPadding_Status_t
 Padding status code. More...
 
+

Detailed Description

+

Types used by the Padding component.

+

Typedef Documentation

+ +

◆ mcuxClPadding_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClPadding_Status_t
+
+ +

Padding status code.

+

This type provides information about the status of the Padding operation that has been performed.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00825.js b/components/els_pkc/doc/mcxn/html/a00825.js new file mode 100644 index 000000000..ea671ab4b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00825.js @@ -0,0 +1,4 @@ +var a00825 = +[ + [ "mcuxClPadding_Status_t", "a00825.html#ga965eb15986e53917365f3f3b769e0968", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00826.html b/components/els_pkc/doc/mcxn/html/a00826.html new file mode 100644 index 000000000..70a53a247 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00826.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClPkc + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClPkc
+
+
+ +

component of PKC hardware driver +More...

+ + + + + + + + +

+Modules

 mcuxClPkc_Functions
 Defines all functions of mcuxClPkc.
 
 mcuxClPkc_Macros
 Defines all macros of mcuxClPkc.
 
+

Detailed Description

+

component of PKC hardware driver

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00826.js b/components/els_pkc/doc/mcxn/html/a00826.js new file mode 100644 index 000000000..f3e0759eb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00826.js @@ -0,0 +1,5 @@ +var a00826 = +[ + [ "mcuxClPkc_Functions", "a00827.html", "a00827" ], + [ "mcuxClPkc_Macros", "a00828.html", "a00828" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00827.html b/components/els_pkc/doc/mcxn/html/a00827.html new file mode 100644 index 000000000..5e49ffa88 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00827.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClPkc_Functions
mcuxClPkc
+
+
+ +

Defines all functions of mcuxClPkc. +More...

+ + + + + + + + + + + + + + +

+Modules

 McuxClPkc_Functions_Init
 mcuxClPkc functions of PKC initialization and deinitialization
 
 McuxClPkc_Functions_UPTRT
 mcuxClPkc functions of PKC UPTR table setup
 
 McuxClPkc_Functions_Calculation
 mcuxClPkc functions of PKC calculation
 
 McuxClPkc_Functions_Wait
 mcuxClPkc functions for waiting PKC computation
 
+

Detailed Description

+

Defines all functions of mcuxClPkc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00827.js b/components/els_pkc/doc/mcxn/html/a00827.js new file mode 100644 index 000000000..003a3bcbc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00827.js @@ -0,0 +1,7 @@ +var a00827 = +[ + [ "McuxClPkc_Functions_Init", "a00963.html", "a00963" ], + [ "McuxClPkc_Functions_UPTRT", "a00964.html", "a00964" ], + [ "McuxClPkc_Functions_Calculation", "a00965.html", "a00965" ], + [ "McuxClPkc_Functions_Wait", "a00966.html", "a00966" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00828.html b/components/els_pkc/doc/mcxn/html/a00828.html new file mode 100644 index 000000000..a9f5e5c4c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00828.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClPkc_Macros
mcuxClPkc
+
+
+ +

Defines all macros of mcuxClPkc. +More...

+ + + + + + + + +

+Modules

 MCUXCLPKC_STATUS_
 mcuxClPkc return code definitions
 
 MCUXCLPKC_MISC_
 mcuxClPkc misc macros and definitions
 
+

Detailed Description

+

Defines all macros of mcuxClPkc.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00828.js b/components/els_pkc/doc/mcxn/html/a00828.js new file mode 100644 index 000000000..b828fbac8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00828.js @@ -0,0 +1,5 @@ +var a00828 = +[ + [ "MCUXCLPKC_STATUS_", "a00967.html", "a00967" ], + [ "MCUXCLPKC_MISC_", "a00968.html", "a00968" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00829.html b/components/els_pkc/doc/mcxn/html/a00829.html new file mode 100644 index 000000000..b4f351ccd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00829.html @@ -0,0 +1,152 @@ + + + + + + + +MCUX CLNS: mcuxClRandom + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClRandom
+
+
+ +

component of random number generation +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 mcuxClRandom_Constants
 Defines all contstants of mcuxClRandom.
 
 mcuxClRandom_Functions
 Defines all functions of mcuxClRandom.
 
 mcuxClRandom_Types
 Defines all types of mcuxClRandom.
 
 mcuxClRandom_Constants
 Defines all modes of mcuxClRandomModes.
 
 Random interfaces
 Interfaces to perform Random handling operations.
 
 Random interfaces
 Interfaces to perform Random handling operations.
 
 mcuxClRandomModes_MemoryConsumption
 Defines the memory consumption for the mcuxClRandom component.
 
+

Detailed Description

+

component of random number generation

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00829.js b/components/els_pkc/doc/mcxn/html/a00829.js new file mode 100644 index 000000000..e53a1b3a8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00829.js @@ -0,0 +1,10 @@ +var a00829 = +[ + [ "mcuxClRandom_Constants", "a00830.html", "a00830" ], + [ "mcuxClRandom_Functions", "a00831.html", "a00831" ], + [ "mcuxClRandom_Types", "a00832.html", "a00832" ], + [ "mcuxClRandom_Constants", "a00833.html", "a00833" ], + [ "Random interfaces", "a00835.html", null ], + [ "Random interfaces", "a00837.html", null ], + [ "mcuxClRandomModes_MemoryConsumption", "a00838.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00830.html b/components/els_pkc/doc/mcxn/html/a00830.html new file mode 100644 index 000000000..e2909613c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00830.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClRandom_Constants
mcuxClRandom
+
+
+ +

Defines all contstants of mcuxClRandom. +More...

+ + + + + +

+Modules

 MCUXCLRANDOM_STATUS_
 mcuxClRandom return code definitions
 
+

Detailed Description

+

Defines all contstants of mcuxClRandom.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00830.js b/components/els_pkc/doc/mcxn/html/a00830.js new file mode 100644 index 000000000..a3d99f8f8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00830.js @@ -0,0 +1,4 @@ +var a00830 = +[ + [ "MCUXCLRANDOM_STATUS_", "a00969.html", "a00969" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00831.html b/components/els_pkc/doc/mcxn/html/a00831.html new file mode 100644 index 000000000..416310044 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00831.html @@ -0,0 +1,469 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClRandom_Functions
mcuxClRandom
+
+
+ +

Defines all functions of mcuxClRandom. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

mcuxClRandom_Status_t mcuxClRandom_init (mcuxClSession_Handle_t pSession, mcuxClRandom_Context_t pContext, mcuxClRandom_Mode_t mode)
 Random data generator initialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_reseed (mcuxClSession_Handle_t pSession)
 Random data generator reseed function. More...
 
mcuxClRandom_Status_t mcuxClRandom_generate (mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
 Random data generation function. More...
 
mcuxClRandom_Status_t mcuxClRandom_uninit (mcuxClSession_Handle_t pSession)
 Random data generator uninitialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_selftest (mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode)
 Random data generator self-test function. More...
 
mcuxClRandom_Status_t mcuxClRandom_checkSecurityStrength (mcuxClSession_Handle_t pSession, uint32_t securityStrength)
 Random data generator security strength check. More...
 
mcuxClRandom_Status_t mcuxClRandom_ncInit (mcuxClSession_Handle_t pSession)
 Non-cryptographic PRNG initialization function. More...
 
mcuxClRandom_Status_t mcuxClRandom_ncGenerate (mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength)
 Non-cryptographic PRNG data generation function. More...
 
+

Detailed Description

+

Defines all functions of mcuxClRandom.

+

Function Documentation

+ +

◆ mcuxClRandom_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_init (mcuxClSession_Handle_t pSession,
mcuxClRandom_Context_t pContext,
mcuxClRandom_Mode_t mode 
)
+
+ +

Random data generator initialization function.

+

This function performs the initialization of a random data generator. This operation initializes the Random context referenced in the session handle.

+
Parameters
+ + + + +
[in]pSessionHandle for the current CL session.
[in]pContextPointer to a Random data context buffer large enough to hold the context for the selected mode
[in]modeMode of operation for random data generator.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, and mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_reseed()

+ +
+
+ + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_reseed (mcuxClSession_Handle_t pSession)
+
+ +

Random data generator reseed function.

+

This function performs the reseeding of a random data generator. This operation fetches a fresh seed from a TRNG and updates the state in the Random context referenced in the session handle.

+
Parameters
+ + +
[in]pSessionHandle for the current CL session.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, and mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_generate()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_generate (mcuxClSession_Handle_t pSession,
uint8_t * pOut,
uint32_t outLength 
)
+
+ +

Random data generation function.

+

This function generates random data based on the information contained in the Random context referenced in the session handle.

+
Parameters
+ + + + +
[in]pSessionHandle for the current CL session.
[out]pOutBuffer in which the generated random data must be written.
[in]outLengthNumber of random data bytes that must be written in the pOut buffer.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, and mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_uninit()

+ +
+
+ + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_uninit (mcuxClSession_Handle_t pSession)
+
+ +

Random data generator uninitialization function.

+

This function performs the cleanup of a random data generator. This operation cleans up the Random context referenced in the session handle.

+
Parameters
+ + +
[in]pSessionHandle for the current CL session.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, and mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_selftest()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_selftest (mcuxClSession_Handle_t pSession,
mcuxClRandom_Mode_t mode 
)
+
+ +

Random data generator self-test function.

+

This function performs a series of selft-tests on the random data generator. These tests are performed on the random data generator defined by Random context referenced in the session handle.

+
Parameters
+ + +
[in]pSessionHandle for the current CL session.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, and mcuxClRandomModes_Different_Sessions_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_checkSecurityStrength()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_checkSecurityStrength (mcuxClSession_Handle_t pSession,
uint32_t securityStrength 
)
+
+ +

Random data generator security strength check.

+

This function reports whether the the random data generator can provide the requested security strength.

+
Parameters
+ + + +
[in]pSessionHandle for the current CL session.
[in]securityStrengthRequested security strength in bits.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClRandom_ncInit()

+ +
+
+ + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_ncInit (mcuxClSession_Handle_t pSession)
+
+ +

Non-cryptographic PRNG initialization function.

+

This function performs the initialization of the non-cryptographic random number generator.

+
Parameters
+ + +
[in]pSessionHandle for the current CL session.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_ELS_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_ncGenerate()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClRandom_Status_t mcuxClRandom_ncGenerate (mcuxClSession_Handle_t pSession,
uint8_t * pOut,
uint32_t outLength 
)
+
+ +

Non-cryptographic PRNG data generation function.

+

This function generates non-cryptographic random data

+
Parameters
+ + + + +
[in]pSessionHandle for the current CL session.
[out]pOutBuffer in which the generated random data must be written.
[in]outLengthNumber of random data bytes that must be written in the pOut buffer.
+
+
+
Returns
status
+
Examples
mcuxClRandomModes_ELS_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00831.js b/components/els_pkc/doc/mcxn/html/a00831.js new file mode 100644 index 000000000..84b9e78db --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00831.js @@ -0,0 +1,11 @@ +var a00831 = +[ + [ "mcuxClRandom_init", "a00831.html#ga989cf9033b30c383d1548037f2ec8bc9", null ], + [ "mcuxClRandom_reseed", "a00831.html#ga89fe90a4ca175d03b4a821cf2fa2004f", null ], + [ "mcuxClRandom_generate", "a00831.html#gadb7d7b6ff820450be3533014cb47f279", null ], + [ "mcuxClRandom_uninit", "a00831.html#ga92889d1e06ba33656278bd2a4110be99", null ], + [ "mcuxClRandom_selftest", "a00831.html#ga4c882c0d6b1e1bba418934c44acc873c", null ], + [ "mcuxClRandom_checkSecurityStrength", "a00831.html#ga6e48c6007ea1d6cfa2ec329152072fc0", null ], + [ "mcuxClRandom_ncInit", "a00831.html#ga4522b9cfa28cb224b653003d481d7100", null ], + [ "mcuxClRandom_ncGenerate", "a00831.html#ga942c035e4c1971f3e4da8cf252b6cdf6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00832.html b/components/els_pkc/doc/mcxn/html/a00832.html new file mode 100644 index 000000000..699767b12 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00832.html @@ -0,0 +1,261 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
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+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs
+
+
mcuxClRandom_Types
mcuxClRandom
+
+
+ +

Defines all types of mcuxClRandom. +More...

+ + + + + +

+Data Structures

struct  mcuxClRandom_Config
 Random config structure. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClRandom_Status_t
 Type for status codes of mcuxClRandom component functions. More...
 
typedef struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t
 Random context type. More...
 
typedef mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t
 Random context type. More...
 
typedef struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
 Random data generation mode/algorithm descriptor type. More...
 
typedef const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t
 Random data generation mode/algorithm type. More...
 
typedef struct mcuxClRandom_Config mcuxClRandom_Config_t
 Random config type. More...
 
+

Detailed Description

+

Defines all types of mcuxClRandom.

+

Typedef Documentation

+ +

◆ mcuxClRandom_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClRandom_Status_t
+
+ +

Type for status codes of mcuxClRandom component functions.

+

This type provides information about the status of the Random operation that has been performed.

+ +
+
+ +

◆ mcuxClRandom_ContextDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t
+
+ +

Random context type.

+

This type is used to store the information about the current random data generator and the relevant internal state.

+ +
+
+ +

◆ mcuxClRandom_Context_t

+ +
+
+ + + + +
typedef mcuxClRandom_ContextDescriptor_t* mcuxClRandom_Context_t
+
+ +

Random context type.

+

This type is used to refer to a Random context.

+
Examples
mcuxClRandomModes_Different_Sessions_example.c.
+
+ +
+
+ +

◆ mcuxClRandom_ModeDescriptor_t

+ +
+
+ + + + +
typedef struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t
+
+ +

Random data generation mode/algorithm descriptor type.

+

This type captures all the information that the Random interfaces need to know about a particular Random data generation mode/algorithm.

+ +
+
+ +

◆ mcuxClRandom_Mode_t

+ +
+
+ + + + +
typedef const mcuxClRandom_ModeDescriptor_t* mcuxClRandom_Mode_t
+
+ +

Random data generation mode/algorithm type.

+

This type is used to refer to a Random data generation mode/algorithm.

+ +
+
+ +

◆ mcuxClRandom_Config_t

+ +
+
+ + + + +
typedef struct mcuxClRandom_Config mcuxClRandom_Config_t
+
+ +

Random config type.

+

This type is used to store context and mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00832.js b/components/els_pkc/doc/mcxn/html/a00832.js new file mode 100644 index 000000000..2f039e0fa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00832.js @@ -0,0 +1,13 @@ +var a00832 = +[ + [ "mcuxClRandom_Config", "a01265.html", [ + [ "mode", "a01265.html#ad723b63c438689b0d5c978fceb289506", null ], + [ "ctx", "a01265.html#a2869dc5912686dc81c5076587bb83327", null ] + ] ], + [ "mcuxClRandom_Status_t", "a00832.html#ga768ea9930242003d2a68991684a1e948", null ], + [ "mcuxClRandom_ContextDescriptor_t", "a00832.html#gab409cd7b1e5a4da822bf9ae43d00c79c", null ], + [ "mcuxClRandom_Context_t", "a00832.html#gac2ce3a52788240794afde522cfad65c5", null ], + [ "mcuxClRandom_ModeDescriptor_t", "a00832.html#gadcfae984a95f3e98617ca5fb9767f5cd", null ], + [ "mcuxClRandom_Mode_t", "a00832.html#ga2998181a66cbdc063aa08d76e5fdef9d", null ], + [ "mcuxClRandom_Config_t", "a00832.html#gaf1284eaa96ef47c06697f95e74ffc3ee", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00833.html b/components/els_pkc/doc/mcxn/html/a00833.html new file mode 100644 index 000000000..ffef82a0e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00833.html @@ -0,0 +1,155 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+ + +
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+ +
+
+Variables
+
+
mcuxClRandom_Constants
mcuxClRandom
+
+
+ +

Defines all modes of mcuxClRandomModes. +More...

+ + + + + + + +

+Variables

const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg
 Mode for a DRBG implemented by the ELS. More...
 
+static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_ELS_Drbg
 
+

Detailed Description

+

Defines all modes of mcuxClRandomModes.

+

Variable Documentation

+ +

◆ mcuxClRandomModes_mdELS_Drbg

+ +
+
+ + + + +
const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg
+
+ +

Mode for a DRBG implemented by the ELS.

+

This mode provides a function to get random values from a DRBG implemented by the ELS. The provided security strength is HW dependent and can be determined using the function mcuxClRandom_checkSecurityStrength

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00833.js b/components/els_pkc/doc/mcxn/html/a00833.js new file mode 100644 index 000000000..342c47594 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00833.js @@ -0,0 +1,4 @@ +var a00833 = +[ + [ "mcuxClRandomModes_mdELS_Drbg", "a00833.html#ga33a2ec75a1ffddc069c679de7c34b8fc", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00834.html b/components/els_pkc/doc/mcxn/html/a00834.html new file mode 100644 index 000000000..990617a8a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00834.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: Random PATCH_MODE API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Random PATCH_MODE API
MCUX CL &ndash; API
+
+
+ +

Random operations in PATCH_MODE. +More...

+

Random operations in PATCH_MODE.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00835.html b/components/els_pkc/doc/mcxn/html/a00835.html new file mode 100644 index 000000000..73cc990b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00835.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: Random interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+
+ +
+
+
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+
+ + +
+ +
+ +
+
+
Random interfaces
mcuxClRandom
+
+
+ +

Interfaces to perform Random handling operations. +More...

+

Interfaces to perform Random handling operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00836.html b/components/els_pkc/doc/mcxn/html/a00836.html new file mode 100644 index 000000000..29f666cf5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00836.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: Random TEST_MODE API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Random TEST_MODE API
MCUX CL &ndash; API
+
+
+ +

Random operations in TEST_MODE. +More...

+

Random operations in TEST_MODE.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00837.html b/components/els_pkc/doc/mcxn/html/a00837.html new file mode 100644 index 000000000..c557a9635 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00837.html @@ -0,0 +1,124 @@ + + + + + + + +MCUX CLNS: Random interfaces + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Random interfaces
mcuxClRandom
+
+
+ +

Interfaces to perform Random handling operations. +More...

+

Interfaces to perform Random handling operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00838.html b/components/els_pkc/doc/mcxn/html/a00838.html new file mode 100644 index 000000000..a7e9de7b3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00838.html @@ -0,0 +1,167 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_MemoryConsumption + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxClRandomModes_MemoryConsumption
mcuxClRandom
+
+
+ +

Defines the memory consumption for the mcuxClRandom component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE
 
+#define MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE
 
+#define MCUXCLRANDOMMODES_INIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE
 
+#define MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE
 
+

Detailed Description

+

Defines the memory consumption for the mcuxClRandom component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00839.html b/components/els_pkc/doc/mcxn/html/a00839.html new file mode 100644 index 000000000..43f321830 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00839.html @@ -0,0 +1,162 @@ + + + + + + + +MCUX CLNS: mcuxClRsa + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ + + + + + +
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+Modules
+
+
mcuxClRsa
+
+
+ +

RSA component. +More...

+ + + + + + + + + + + + + + +

+Modules

 mcuxClRsa_Constants
 Constants of mcuxClRsa component.
 
 mcuxClRsa_Functions
 Defines all functions of mcuxClRsa.
 
 mcuxClRsa_Macros
 Defines all macros of mcuxClRsa.
 
 mcuxClRsa_Types
 Defines all types of the mcuxClRsa component.
 
+

Detailed Description

+

RSA component.

+

The mcuxClRsa component implements the RSA functionality supported by CLNS. This includes RSA signature generation and verification according to PKCS#1 v2.2. The RSA component relies on the mcuxClMath component for modular arithmetic operations as well as the secure and non-secure exponentiation. It further relies on the mcuxHash component for the execution of hashing operations. The component offers the following functionality:

    +
  • RSA signature generation and verification:
      +
    1. +RSA signature generation using RSA keys in private plain or private CRT format together with the PKCS#1 v1.5 padding or PSS padding functionality, according to to RSASSA-PSS-SIGN or RSASSA-PKCS1-v1_5-SIGN of PKCS #1 v2.2.
      2. +
    2. +RSA signature verification using RSA keys public format together with the PKCS#1 v1.5 padding or PSS verification functionality, according to to RSASSA-PSS-VERIFY or RSASSA-PKCS1-v1_5-VERIFY of PKCS #1 v2.2.
      3. +
    3. +RSA signature generation primitive RSASP1 (exponentiation with public exponent) according to PKCS #1 v2.2.
      4. +
    4. +RSA signature verification primitive RSAVP1 (exponentiation with RSA keys in private plain or private CRT format) according to PKCS #1 v2.2.
      5. +
    5. +The bit-length of the modulus can vary from 512 bits to 4096 bits in multiples of 8.
      6. +
    6. +The bit-length of the public exponent is limited to: of 2 <= e < N.
      7. +
    7. +The bit-length of the private exponent is limited to: d < N.
      8. +
    +
    • +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00839.js b/components/els_pkc/doc/mcxn/html/a00839.js new file mode 100644 index 000000000..e137cb3c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00839.js @@ -0,0 +1,7 @@ +var a00839 = +[ + [ "mcuxClRsa_Constants", "a00840.html", "a00840" ], + [ "mcuxClRsa_Functions", "a00843.html", "a00843" ], + [ "mcuxClRsa_Macros", "a00849.html", "a00849" ], + [ "mcuxClRsa_Types", "a00853.html", "a00853" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00840.html b/components/els_pkc/doc/mcxn/html/a00840.html new file mode 100644 index 000000000..226f749b6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00840.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Modules
+
+
mcuxClRsa_Constants
mcuxClRsa
+
+
+ +

Constants of mcuxClRsa component. +More...

+ + + + + + + + +

+Modules

 mcuxClRsa_Sign_Modes
 Signing modes of the mcuxClRsa component.
 
 mcuxClRsa_Verify_Modes
 Verify modes of the mcuxClRsa component.
 
+

Detailed Description

+

Constants of mcuxClRsa component.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00840.js b/components/els_pkc/doc/mcxn/html/a00840.js new file mode 100644 index 000000000..9634e7c5c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00840.js @@ -0,0 +1,5 @@ +var a00840 = +[ + [ "mcuxClRsa_Sign_Modes", "a00841.html", "a00841" ], + [ "mcuxClRsa_Verify_Modes", "a00842.html", "a00842" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00841.html b/components/els_pkc/doc/mcxn/html/a00841.html new file mode 100644 index 000000000..2404cc1e7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00841.html @@ -0,0 +1,307 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Sign_Modes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ + + +
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+
+Variables
+
+
mcuxClRsa_Sign_Modes
mcuxClRsa » mcuxClRsa_Constants
+
+
+ +

Signing modes of the mcuxClRsa component. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode
 Mode definition for RSASP1. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512
 Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/512. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224
 Mode definition for RSASSA-PSS-SIGN using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256
 Mode definition for RSASSA-PSS-SIGN using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384
 Mode definition for RSASSA-PSS-SIGN using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512
 Mode definition for RSASSA-PSS-SIGN using SHA-2/512. More...
 
+

Detailed Description

+

Signing modes of the mcuxClRsa component.

+

Variable Documentation

+ +

◆ mcuxClRsa_Mode_Sign_NoEncode

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode
+
+ +

Mode definition for RSASP1.

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/224.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/256.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/384.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/512.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_Pss_Sha2_224

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224
+
+ +

Mode definition for RSASSA-PSS-SIGN using SHA-2/224.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_Pss_Sha2_256

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256
+
+ +

Mode definition for RSASSA-PSS-SIGN using SHA-2/256.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_Pss_Sha2_384

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384
+
+ +

Mode definition for RSASSA-PSS-SIGN using SHA-2/384.

+ +
+
+ +

◆ mcuxClRsa_Mode_Sign_Pss_Sha2_512

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512
+
+ +

Mode definition for RSASSA-PSS-SIGN using SHA-2/512.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00841.js b/components/els_pkc/doc/mcxn/html/a00841.js new file mode 100644 index 000000000..53d770a77 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00841.js @@ -0,0 +1,12 @@ +var a00841 = +[ + [ "mcuxClRsa_Mode_Sign_NoEncode", "a00841.html#ga4459d773156bf4ac906a1416dd4ed4f4", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224", "a00841.html#gac7cfd526cb16ba49a48ea0881c12e778", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256", "a00841.html#ga1845c307f6b2897cf563c1ad97523840", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384", "a00841.html#ga2e630f5e6e06e0b5adc2d5f63268b77f", null ], + [ "mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512", "a00841.html#ga61cdf384d5eb7774a35bec2dd28b67c8", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_224", "a00841.html#ga6544c3cc75077dde34304c5c45999edf", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_256", "a00841.html#gaf88819f8def0ed1dc626168103856a25", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_384", "a00841.html#ga884749f4e133157dcdc3b85d15b98ada", null ], + [ "mcuxClRsa_Mode_Sign_Pss_Sha2_512", "a00841.html#gab71896db47c552effcdad152a574e5a1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00842.html b/components/els_pkc/doc/mcxn/html/a00842.html new file mode 100644 index 000000000..90433df35 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00842.html @@ -0,0 +1,307 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Verify_Modes + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
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+ +
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+ + +
+ +
+ +
+
+Variables
+
+
mcuxClRsa_Verify_Modes
mcuxClRsa » mcuxClRsa_Constants
+
+
+ +

Verify modes of the mcuxClRsa component. +More...

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+Variables

const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify
 Mode definition for RSAVP1. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512
 Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/512. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/224. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/256. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/384. More...
 
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512
 Mode definition for RSASSA-PSS-VERIFY using SHA-2/512. More...
 
+

Detailed Description

+

Verify modes of the mcuxClRsa component.

+

Variable Documentation

+ +

◆ mcuxClRsa_Mode_Verify_NoVerify

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify
+
+ +

Mode definition for RSAVP1.

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/224.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/256.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/384.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512
+
+ +

Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/512.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_Pss_Sha2_224

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224
+
+ +

Mode definition for RSASSA-PSS-VERIFY using SHA-2/224.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_Pss_Sha2_256

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256
+
+ +

Mode definition for RSASSA-PSS-VERIFY using SHA-2/256.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_Pss_Sha2_384

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384
+
+ +

Mode definition for RSASSA-PSS-VERIFY using SHA-2/384.

+ +
+
+ +

◆ mcuxClRsa_Mode_Verify_Pss_Sha2_512

+ +
+
+ + + + +
const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512
+
+ +

Mode definition for RSASSA-PSS-VERIFY using SHA-2/512.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00842.js b/components/els_pkc/doc/mcxn/html/a00842.js new file mode 100644 index 000000000..f345daf24 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00842.js @@ -0,0 +1,12 @@ +var a00842 = +[ + [ "mcuxClRsa_Mode_Verify_NoVerify", "a00842.html#ga9274985a905326fe0bcbe3ab23123e75", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224", "a00842.html#gafaa7d91b00e9a3e5edbcc8ea8d0d2320", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256", "a00842.html#gaebc33a997f28ae34f977899c4da4f117", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384", "a00842.html#ga6e5c11f4096af091859db6a5f3009c43", null ], + [ "mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512", "a00842.html#gafc855e8c67d58fc5b0e79e89eac6d976", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_224", "a00842.html#gaba34c04545877c67789942d9a2c9134a", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_256", "a00842.html#gab80d7f48edeb8b4c401221180572e4f2", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_384", "a00842.html#ga74c434306a9d393e51b4997152381b8e", null ], + [ "mcuxClRsa_Mode_Verify_Pss_Sha2_512", "a00842.html#ga4214b439b403de8eda53043cdf71ca83", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00843.html b/components/els_pkc/doc/mcxn/html/a00843.html new file mode 100644 index 000000000..1023449fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00843.html @@ -0,0 +1,675 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Functions + + + + + + + + + + + + + + + + +
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+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+ +
+
+Functions
+
+
mcuxClRsa_Functions
mcuxClRsa
+
+
+ +

Defines all functions of mcuxClRsa. +More...

+ + + + + + + + + + + + + + +

+Functions

mcuxClRsa_Status_t mcuxClRsa_sign (mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, const mcuxClRsa_SignVerifyMode pPaddingMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pSignature)
 RSA sign operation. More...
 
mcuxClRsa_Status_t mcuxClRsa_verify (mcuxClSession_Handle_t pSession, const mcuxClRsa_Key *const pKey, mcuxCl_InputBuffer_t pMessageOrDigest, const uint32_t messageLength, mcuxCl_Buffer_t pSignature, const mcuxClRsa_SignVerifyMode pVerifyMode, const uint32_t saltLength, const uint32_t options, mcuxCl_Buffer_t pOutput)
 RSA verify operation. More...
 
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Crt (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 Generates an RSA key in CRT format. More...
 
mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Plain (mcuxClSession_Handle_t pSession, mcuxClKey_Type_t type, mcuxClKey_Protection_t protection, mcuxClKey_Handle_t privKey, uint8_t *pPrivData, uint32_t *const pPrivDataLength, mcuxClKey_Handle_t pubKey, uint8_t *pPubData, uint32_t *const pPubDataLength)
 RSA key generation of private plain key operation. More...
 
+

Detailed Description

+

Defines all functions of mcuxClRsa.

+

Function Documentation

+ +

◆ mcuxClRsa_sign()

+ +
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mcuxClRsa_Status_t mcuxClRsa_sign (mcuxClSession_Handle_t pSession,
const mcuxClRsa_Key *const pKey,
mcuxCl_InputBuffer_t pMessageOrDigest,
const uint32_t messageLength,
const mcuxClRsa_SignVerifyMode pPaddingMode,
const uint32_t saltLength,
const uint32_t options,
mcuxCl_Buffer_t pSignature 
)
+
+ +

RSA sign operation.

+

This function performs an RSA signature generation according to RSASP1, RSASSA-PSS-SIGN or RSASSA-PKCS1-v1_5-SIGN of PKCS #1 v2.2. Based on the passed key type, it is selected, whether to perform this operation using a private plain, a private CRT key, or whether to use a private CRT key and protect the operation against perturbation attacks. Based on the selection of the padding mode, it is determined, whether to perform no padding, or whether to perform one of the supported paddings based on one of the supported hash functions. The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8. The private exponent is limited to d < n.

+
Parameters
+ + + + + + + + + +
[in]pSessionPointer to mcuxClSession_Descriptor
[in]pKeyPointer to key structure of type mcuxClRsa_Key
[in]pMessageOrDigestPointer to buffer, which contains the input to the sign operation
[in]messageLengthByte-length of MessageOrDigest
[in]pPaddingModePointer to signing mode of type mcuxClRsa_SignVerifyMode_t
[in]saltLengthByte-length of salt
[in]optionsOptions field
[out]pSignaturePointer to buffer, which contains the result (signature)
+
+
+
+
Parameter properties
+
+
pSession:
+
The session pointed to by pSession has to be initialized prior to a call to this function.
+
pKey:
+
The key entries must meet the following conditions: +
+
pMessageOrDigest:
+
The input must meet the following conditions: +
+
messageLength:
+
This value is only regarded in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, or mode RSASP1, please set to zero.
+
pPaddingMode:
+
The mode specifies the targeted padding and hashing algorithms. Please set to one of mcuxClRsa_Sign_Modes.
+
saltLength:
+
This value is only regarded in case of performing a RSASSA-PSS-SIGN operation. Otherwise, please set to zero.
+
options:
+
This field is used to select options of the sign operation: +
+
pSignature:
+
The output is returned in in big-endian byte order.
+
+
+
+
Returns
Status of the mcuxClRsa_sign operation (see MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t))
+
Return values
+ + + + +
MCUXCLRSA_STATUS_SIGN_OKSign operation executed successfully.
MCUXCLRSA_STATUS_INVALID_INPUTThe input parameters are not valid.
MCUXCLRSA_STATUS_ERRORAn error occurred during the execution. In that case, expectations for the flow protection are not balanced.
+
+
+
Attention
This function uses PRNG which has to be initialized prior to calling the function.
+
Examples
mcuxClRsa_sign_NoEncode_example.c, and mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_verify()

+ +
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mcuxClRsa_Status_t mcuxClRsa_verify (mcuxClSession_Handle_t pSession,
const mcuxClRsa_Key *const pKey,
mcuxCl_InputBuffer_t pMessageOrDigest,
const uint32_t messageLength,
mcuxCl_Buffer_t pSignature,
const mcuxClRsa_SignVerifyMode pVerifyMode,
const uint32_t saltLength,
const uint32_t options,
mcuxCl_Buffer_t pOutput 
)
+
+ +

RSA verify operation.

+

This function performs an RSA signature verification according to RSAVP1, RSASSA-PSS-VERIFY or RSASSA-PKCS1-v1_5-VERIFY of PKCS #1 v2.2. Based on the selection of the padding mode, it is determined, whether to perform no padding verification, or whether to perform one of the supported padding verifications based on one of the supported hash functions. The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8. The public exponent is limited to 2 <= e < N.

+
Parameters
+ + + + + + + + + + +
[in]pSessionPointer to mcuxClSession_Descriptor
[in]pKeyPointer to key structure of type mcuxClRsa_Key
[in]pMessageOrDigestPointer to buffer, which contains the input to the verify operation
[in]messageLengthByte-length of MessageOrDigest
[in]pSignaturePointer to buffer, which contains the signature
[in]pVerifyModePointer to verification mode of type mcuxClRsa_SignVerifyMode_t
[in]saltLengthByte-length of salt
[in]optionsOptions field
[out]pOutputPointer to output buffer
+
+
+
+
Parameter properties
+
+
pSession:
+
The session pointed to by pSession has to be initialized prior to a call to this function.
+
pKey:
+
The key entries must meet the following conditions:
    +
  • Entry keytype must be set to MCUXCLRSA_KEY_PUBLIC. In case of passing another key type, the function returns MCUXCLRSA_STATUS_INVALID_INPUT. The functions checks, internally, whether the required key entries are not set to NULL. If so, the function returns MCUXCLRSA_STATUS_INVALID_INPUT;
    • +
  • The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8;
    • +
  • It is required that e is greater or equal to 2 and smaller than n.
    • +
+
+
pMessageOrDigest:
+
The input must meet the following conditions:
    +
  • It must be provided in big-endian byte order;
    • +
  • In case of mode RSAVP1, please set to NULL.
    • +
+
+
messageLength:
+
This value is only regarded in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, or mode RSAVP1, please set to zero.
+
pSignature:
+
The signature must meet the following conditions:
    +
  • It must be given in big-endian byte order;
    • +
  • The signature length is determined by the modulus length (bytelength(n));
    • +
  • The signature value must be smaller than n. If it is bigger the function returns MCUXCLRSA_STATUS_INVALID_INPUT.
    • +
+
+
pVerifyMode:
+
The mode specifies the targeted padding verification and hashing algorithms. Please set to one of mcuxClRsa_Verify_Modes.
+
saltLength:
+
This value is only regarded in case of performing a RSASSA-PSS-VERIFY operation. Otherwise, please set to zero.
+
options:
+
This field is used to select options of the sign operation: +
+
pOutput:
+
In case of mode RSAVP1 this pointer points to the buffer, where the result will be stored in big-endian byte order. This buffer must have the same byte-length as the modulus. In case of modes RSASSA-PSS-VERIFY and RSASSA-PKCS1-v1_5-VERIFY please set to NULL.
+
+
+
+
Returns
Status of the mcuxClRsa_verify operation (see MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t))
+
Return values
+ + + + + + +
MCUXCLRSA_STATUS_VERIFY_OKVerify operation executed successfully.
MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OKVerification primitive operation executed successfully.
MCUXCLRSA_STATUS_INVALID_INPUTThe input parameters are not valid.
MCUXCLRSA_STATUS_VERIFY_FAILEDThe signature verification failed.
MCUXCLRSA_STATUS_ERRORAn error occurred during the execution. In that case, expectations for the flow protection are not balanced.
+
+
+
Attention
This function uses PRNG which has to be initialized prior to calling the function.
+
Examples
mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ mcuxClRsa_KeyGeneration_Crt()

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mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Crt (mcuxClSession_Handle_t pSession,
mcuxClKey_Type_t type,
mcuxClKey_Protection_t protection,
mcuxClKey_Handle_t privKey,
uint8_t * pPrivData,
uint32_t *const pPrivDataLength,
mcuxClKey_Handle_t pubKey,
uint8_t * pPubData,
uint32_t *const pPubDataLength 
)
+
+ +

Generates an RSA key in CRT format.

+

This function for given public exponent and key size generates an RSA private key in CRT representation (p, q, dp, dq, qInv) and computes the modulus n.

+

Primes p and q are generated based on the method specified in the FIPS 186-4, Appendix B.3.3 using probabilistic primality test with the probability of not being prime less than 2^(-125). The public exponent is restricted to (FIPS compliant) odd values in the range 2^16 < e < 2^256 (i.e. including 0x10001). The bit-length of the key size is limited to 2048, 3072 and 4096. The keys generated by this function are FIPS 186-4 compliant provided their length is either 2048 or 3072 bits and the exponent value is an odd integer between 2^16 and 2^256.

+

The two key handles are linked with each other using mcuxClKey_linkKeyPair.

+
Parameters
+ + + + + + + + + + +
[in]pSessionPointer to mcuxClSession_Descriptor
[in]typeType of the key
[in]protectionProtection and flush mechanism that must be applied to the generated key.
[out]privKeyKey handle for the generated private key
[out]pPrivDataPointer to the buffer where the generated private CRT key data needs to be written
[out]pPrivDataLengthWill be set by the number of bytes of data that have been written to the pPrivData buffer
[out]pubKeyKey handle for the generated public key
[out]pPubDataPointer to the buffer where the generated public key data needs to be written
[out]pPubDataLengthWill be set by the number of bytes of data that have been written to the pPubData buffer
+
+
+
+
Parameter properties
+
+
pSession:
+
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized with the entropy level (security strength) in accordance with the value of type.size, as specified in SP 800-57, Part 1.
+
type:
+
Type of the key. It contains information about the input parameters:
    +
  • type.size - length of the generated key
    • +
  • type.info - pointer to key entry i.e. public exponent. It points to data type mcuxClRsa_KeyEntry_t* (i.e. pointer to buffer containing the public exponent data and byte-length of the public exponent).
    • +
+
+
protection :
+
Protection and flush mechanism that must be applied to the generated key.
+
privKey:
+
Key handle for the generated private key.
+
pPrivData:
+
Pointer to the buffer where the generated private CRT key (p, q, qInv, dp, dq) data needs to be written. This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: p, q, qInv, dp, dq. Buffer is allocated by the caller.
+
pPrivDataLength:
+
Number of bytes of data that have been written to the pPrivData buffer.
+
pubKey:
+
Key handle for the generated public key.
+
pPubData:
+
Pointer to the buffer where the generated public key (n, e) data needs to be written. This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, e. Buffer is allocated by the caller.
+
pPubDataLength:
+
Number of bytes of data that have been written to the pPubData buffer.
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Returns
Status of the mcuxClRsa_KeyGeneration_Crt operation (see MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t))
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Return values
+ + + + + +
MCUXCLRSA_STATUS_KEYGENERATION_OKRSA key generation operation executed successfully.
MCUXCLRSA_STATUS_INVALID_INPUTThe input parameters are not valid.
MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDEDRSA key generation exceeds the limit of iterations to generate a prime.
MCUXCLRSA_STATUS_ERRORAn error occurred during the execution. In that case, expectations for the flow protection are not balanced.
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Attention
This function uses DRBG and PRNG which have to be initialized prior to calling the function.
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◆ mcuxClRsa_KeyGeneration_Plain()

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mcuxClRsa_Status_t mcuxClRsa_KeyGeneration_Plain (mcuxClSession_Handle_t pSession,
mcuxClKey_Type_t type,
mcuxClKey_Protection_t protection,
mcuxClKey_Handle_t privKey,
uint8_t * pPrivData,
uint32_t *const pPrivDataLength,
mcuxClKey_Handle_t pubKey,
uint8_t * pPubData,
uint32_t *const pPubDataLength 
)
+
+ +

RSA key generation of private plain key operation.

+

This function for given public exponent and key size generates RSA private key in in plain from (d, n).

+

Private exponent d is computed with the requirements specified in the FIPS 186-4, Appendix B.3.1. Primes p and q are generated based on the method specified in the FIPS 186-4, Appendix B.3.3 using probabilistic primality test with the probability of not being prime less than 2^(-125). The public exponent is restricted to (FIPS compliant) odd values in the range 2^16 < e < 2^256 (i.e. including 0x10001). The bit-length of the key size is limited to 2048, 3072 and 4096. The keys generated by this function are FIPS 186-4 compliant provided their length is either 2048 or 3072 bits and the exponent value is an odd integer between 2^16 and 2^256.

+

The two key handles are linked with each other using mcuxClKey_linkKeyPair.

+
Parameters
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[in]pSessionPointer to mcuxClSession_Descriptor
[in]typeType of the key
[in]protectionProtection and flush mechanism that must be applied to the generated key
[out]privKeyKey handle for the generated private key
[out]pPrivDataPointer to the buffer where the generated private plain key data needs to be written
[out]pPrivDataLengthWill be set by the number of bytes of data that have been written to the pPrivData buffer
[out]pubKeyKey handle for the generated public key
[out]pPubDataPointer to the buffer where the generated public key data needs to be written
[out]pPubDataLengthWill be set by the number of bytes of data that have been written to the pPubData buffer
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Parameter properties
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pSession:
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The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized with the entropy level (security strength) in accordance with the value of type.size, as specified in SP 800-57, Part 1.
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type:
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Type of the key. It contains information about the input parameters:
    +
  • type.size - length of the generated key
    • +
  • type.info - pointer to key entry i.e. public exponent. It points to data type mcuxClRsa_KeyEntry_t*(i.e. pointer to buffer containing the public exponent data and byte-length of the public exponent).
    • +
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protection :
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Protection and flush mechanism that must be applied to the generated key.
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privKey:
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Key handle for the generated private key.
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pPrivData:
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Pointer to the buffer where the generated private plain key (n, d) data needs to be written. This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, d. Buffer is allocated by the caller.
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pPrivDataLength:
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Number of bytes of data that have been written to the pPrivData buffer.
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pubKey:
+
Key handle for the generated public key.
+
pPubData:
+
Pointer to the buffer where the generated public key (n, e) data needs to be written. This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, e. Buffer is allocated by the caller.
+
pPubDataLength:
+
Number of bytes of data that have been written to the pPubData buffer.
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+
+
+
Returns
Status of the mcuxClRsa_KeyGeneration_Plain operation (see MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t))
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Return values
+ + + + + +
MCUXCLRSA_STATUS_KEYGENERATION_OKRSA key generation operation executed successfully.
MCUXCLRSA_STATUS_INVALID_INPUTThe input parameters are not valid.
MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDEDRSA key generation exceeds the limit of iterations to generate a prime.
MCUXCLRSA_STATUS_ERRORAn error occurred during the execution. In that case, expectations for the flow protection are not balanced.
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+
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Attention
This function uses DRBG and PRNG which have to be initialized prior to calling the function.
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00843.js b/components/els_pkc/doc/mcxn/html/a00843.js new file mode 100644 index 000000000..664cbb50d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00843.js @@ -0,0 +1,7 @@ +var a00843 = +[ + [ "mcuxClRsa_sign", "a00843.html#gaea19a43d7a52c159675d93d8e7d6ec51", null ], + [ "mcuxClRsa_verify", "a00843.html#ga21bf92b81f28be1b6b6fc7d3bdc69098", null ], + [ "mcuxClRsa_KeyGeneration_Crt", "a00843.html#gaa099449b2290a333aac2dcf090a2740c", null ], + [ "mcuxClRsa_KeyGeneration_Plain", "a00843.html#ga08dff8d41898b3f372ceab1038205b51", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00844.html b/components/els_pkc/doc/mcxn/html/a00844.html new file mode 100644 index 000000000..28efebbd7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00844.html @@ -0,0 +1,932 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_SIGN_WA + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+Macros
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MCUXCLRSA_SIGN_WA
mcuxClRsa » mcuxClRsa_Macros
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Definitions of workarea sizes for the mcuxClRsa Sign. +More...

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+Macros

#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. More...
 
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys. More...
 
#define MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
#define MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private CRT keys. More...
 
#define MCUXCLRSA_SIGN_CRT_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClRsa Sign.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE

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+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode.

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
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+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE

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+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode.

+ +
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+ +

◆ MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE

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#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE
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+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode.

+ +
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+ +

◆ MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE

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#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode.

+ +
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+ +

◆ MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE

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+ + + + + + + + +
#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys.

+
Examples
mcuxClRsa_sign_NoEncode_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE( keyBitLength)
+
+ +

Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE

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+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 1024-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 2048-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 3072-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 4096-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 1024-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 2048-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 3072-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 4096-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 1024-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 2048-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 3072-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 4096-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private CRT keys.

+ +
+
+ +

◆ MCUXCLRSA_SIGN_CRT_WAPKC_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_SIGN_CRT_WAPKC_SIZE( keyBitLength)
+
+ +

Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00844.js b/components/els_pkc/doc/mcxn/html/a00844.js new file mode 100644 index 000000000..eae5506b0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00844.js @@ -0,0 +1,43 @@ +var a00844 = +[ + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE", "a00844.html#ga62affe57ed8b934c432d1e4957ca2b96", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE", "a00844.html#ga0771ad370b59155e8fee261c84e51531", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE", "a00844.html#gae3e6841f0361a7df7d5308d663b114c6", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE", "a00844.html#ga34b88e6a0e6b4168b989aa9d6bf9c569", null ], + [ "MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE", "a00844.html#gaa605aa3b59dcc107147ddeb6fcb7e8c0", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE", "a00844.html#ga4312eb8909ce30ba6362af6aaa03f69e", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE", "a00844.html#gaf455d79389af05675935d6d53d7ade7c", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE", "a00844.html#ga164cca6715f5d4ad090ccc4ab882dd68", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE", "a00844.html#ga773066aea6da7ba38442305ad2bf6af2", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE", "a00844.html#ga1dea31cb3edffff3b19d105f7374aa81", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE", "a00844.html#ga25a8fb0b64b30957a85d6cc8ccff3694", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE", "a00844.html#ga6c85361c450a7a291e4a21ba5ad8c829", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE", "a00844.html#gaa0b8b7e5e999f0f647b157570879ab70", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE", "a00844.html#ga48f0eed84fa89303aab8926a5af140e0", null ], + [ "MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE", "a00844.html#gab630a43086137a34a22d379d99d4979e", null ], + [ "MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE", "a00844.html#ga48b4346142911ddd75ac4bb4575b4a44", null ], + [ "MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE", "a00844.html#ga5b2d3626004c26e5935658c75faed0fe", null ], + [ "MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE", "a00844.html#ga87f2af5e231ca701d6c241260f6632c8", null ], + [ "MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE", "a00844.html#gac51d995815daa1270660faa6c941556b", null ], + [ "MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE", "a00844.html#gab592bb2afe239d110b69019bbcfbf39a", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE", "a00844.html#ga08af4d804d4c5dd22c246fe4ee55afd1", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE", "a00844.html#gada60205f871f7cbdff86547038599ec8", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE", "a00844.html#gaa9fbd44b2d8b333ef36b98aa36d8ce91", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE", "a00844.html#ga9afbf286d2d7eda637ba13f19bbf727f", null ], + [ "MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE", "a00844.html#ga97d05e715e7d13e8eccdaad372e7d50a", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE", "a00844.html#ga94c5de50e6e2c146a56ca41fe875b1ae", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE", "a00844.html#gaffa8f7a22bc5dc5f0102e6a7d58aae22", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE", "a00844.html#ga622d0a8ac987bd0a74fbf3a6aafb0622", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE", "a00844.html#ga56c7e14b62345bd224a7dd133c9cf47e", null ], + [ "MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE", "a00844.html#gaae863be535c94424a53999e430f94345", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE", "a00844.html#gaf8a8d4ef6856d0325171771a38ed2b3f", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE", "a00844.html#ga13a37dc2bf4e9369d0f97257eedbb240", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE", "a00844.html#gaf1c40d9d43240fca324f6bddb7ba22b2", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE", "a00844.html#ga85c6c2f1faf8413022119493161d08eb", null ], + [ "MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE", "a00844.html#ga437b8eb62b4f1c455f0fcf9185dee790", null ], + [ "MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE", "a00844.html#gaace82904ad5b20b810d80d9561e6277b", null ], + [ "MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE", "a00844.html#gaab6efa4449159180daf2c0ad4452283c", null ], + [ "MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE", "a00844.html#ga7844b694581a8cb752edd86444a10812", null ], + [ "MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE", "a00844.html#ga56f2ed2760ce4db4e8246d96f768e23e", null ], + [ "MCUXCLRSA_SIGN_CRT_WAPKC_SIZE", "a00844.html#gae92072e416a0f52664b7720d33b1fd91", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00845.html b/components/els_pkc/doc/mcxn/html/a00845.html new file mode 100644 index 000000000..f4aa5eda6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00845.html @@ -0,0 +1,294 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_VERIFY_WA + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLRSA_VERIFY_WA
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Definitions of workarea sizes for the mcuxClRsa Verify. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_NoVerify. More...
 
#define MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PssVerify. More...
 
#define MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE
 Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_*. More...
 
#define MCUXCLRSA_VERIFY_1024_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 1024-bit keys. More...
 
#define MCUXCLRSA_VERIFY_2048_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 2048-bit keys. More...
 
#define MCUXCLRSA_VERIFY_3072_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 3072-bit keys. More...
 
#define MCUXCLRSA_VERIFY_4096_WAPKC_SIZE
 Definition of PKC workarea size for the mcuxClRsa_verify function for 4096-bit keys. More...
 
#define MCUXCLRSA_VERIFY_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size to be used with a non-standard key length. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClRsa Verify.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_NoVerify.

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PssVerify.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE
+
+ +

Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_*.

+ +
+
+ +

◆ MCUXCLRSA_VERIFY_1024_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_1024_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_verify function for 1024-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_VERIFY_2048_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_2048_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_verify function for 2048-bit keys.

+
Examples
mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_VERIFY_3072_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_3072_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_verify function for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_VERIFY_4096_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_VERIFY_4096_WAPKC_SIZE
+
+ +

Definition of PKC workarea size for the mcuxClRsa_verify function for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_VERIFY_WAPKC_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_VERIFY_WAPKC_SIZE( keyBitLength)
+
+ +

Macro to extract PKC workarea size to be used with a non-standard key length.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00845.js b/components/els_pkc/doc/mcxn/html/a00845.js new file mode 100644 index 000000000..6bb4b71ab --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00845.js @@ -0,0 +1,11 @@ +var a00845 = +[ + [ "MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE", "a00845.html#gac0a79e3e30fbf6610c95ad399bb55165", null ], + [ "MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE", "a00845.html#gaf4bcc54a8a49029c2454d0afdca0a18e", null ], + [ "MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE", "a00845.html#gab9dc9df4db1e42592e9f23b90abf7432", null ], + [ "MCUXCLRSA_VERIFY_1024_WAPKC_SIZE", "a00845.html#gaf6485ca0f6a219994ba327e9f35dbb94", null ], + [ "MCUXCLRSA_VERIFY_2048_WAPKC_SIZE", "a00845.html#ga347b86aaa2ec9e1c6b42d53b8b550139", null ], + [ "MCUXCLRSA_VERIFY_3072_WAPKC_SIZE", "a00845.html#gaf370a2aea81eaa53070ecd49de1291fb", null ], + [ "MCUXCLRSA_VERIFY_4096_WAPKC_SIZE", "a00845.html#ga8472e567acdaf653ea64617586e69dd5", null ], + [ "MCUXCLRSA_VERIFY_WAPKC_SIZE", "a00845.html#ga1890b9a82cba6144b533121da365baeb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00846.html b/components/els_pkc/doc/mcxn/html/a00846.html new file mode 100644 index 000000000..882edd316 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00846.html @@ -0,0 +1,292 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_KEYGENERATION_CRT_WA + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLRSA_KEYGENERATION_CRT_WA
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size (in bytes) for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size (in bytes) for the given key length. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size (in bytes) for the given key length.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE( keyBitLength)
+
+ +

Macro to extract PKC workarea size (in bytes) for the given key length.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00846.js b/components/els_pkc/doc/mcxn/html/a00846.js new file mode 100644 index 000000000..2d4606796 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00846.js @@ -0,0 +1,11 @@ +var a00846 = +[ + [ "MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE", "a00846.html#gad96d63918b029c58379a519458e0fe5e", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE", "a00846.html#ga4f7ea947e335da713b995b3dd5756726", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE", "a00846.html#ga7cd47280b5c29ab35fe15afdb1aff9b5", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE", "a00846.html#gab62b9607b6acf175174f192227482782", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE", "a00846.html#ga50df60e5ac10a4d18d91793b9975f931", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE", "a00846.html#ga9cddbdf9c06180c1ad4f1004c013a3b0", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE", "a00846.html#ga046e2a5713b8ad6d69f9882d2fde5b3f", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE", "a00846.html#ga398705431e601a6309bcf59a65f72328", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00847.html b/components/els_pkc/doc/mcxn/html/a00847.html new file mode 100644 index 000000000..8904d6889 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00847.html @@ -0,0 +1,292 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_KEYGENERATION_PLAIN_WA + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
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+ +
+ +
+
+Macros
+
+
MCUXCLRSA_KEYGENERATION_PLAIN_WA
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE
 Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE(keyBitLength)
 Macro to extract CPU workarea size for the given key length. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE
 Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE(keyBitLength)
 Macro to extract PKC workarea size for the given key length. More...
 
+

Detailed Description

+

Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE
+
+ +

Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE( keyBitLength)
+
+ +

Macro to extract CPU workarea size for the given key length.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE
+
+ +

Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE( keyBitLength)
+
+ +

Macro to extract PKC workarea size for the given key length.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00847.js b/components/els_pkc/doc/mcxn/html/a00847.js new file mode 100644 index 000000000..4d9ff4104 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00847.js @@ -0,0 +1,11 @@ +var a00847 = +[ + [ "MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE", "a00847.html#ga8bfbe68f2ddf833c65badc56832310ff", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE", "a00847.html#ga499a98e9b3b5f98b43d41bace11d6d2a", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE", "a00847.html#gacfaaad0cd3da9dd167a4068a2a2fda7f", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE", "a00847.html#gab0c5e4df4d6371815ec7b1d962053507", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE", "a00847.html#gaeaf97fe967de3e01d06b80d4aecf62ba", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE", "a00847.html#ga76dbc936b3c90bf4e66824697b16be80", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE", "a00847.html#ga2e6c1c9053ca24c4101e348c9f8d2588", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE", "a00847.html#ga989c3c758b19a6f32cb0ac16dc698bc2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00848.html b/components/els_pkc/doc/mcxn/html/a00848.html new file mode 100644 index 000000000..8db1dcf4f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00848.html @@ -0,0 +1,303 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Definitions of bufer sizes for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the private plain key data for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the private CRT key data for 4096-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE
 Definition of bufer size (in bytes) for the public key data for 2048-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE
 Definition of bufer size (in bytes) for the public key data for 3072-bit keys. More...
 
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE
 Definition of bufer size (in bytes) for the public key data for 4096-bit keys. More...
 
+

Detailed Description

+

Definitions of bufer sizes for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE
+
+ +

Definition of bufer size (in bytes) for the private plain key data for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE
+
+ +

Definition of bufer size (in bytes) for the private plain key data for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE
+
+ +

Definition of bufer size (in bytes) for the private plain key data for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE
+
+ +

Definition of bufer size (in bytes) for the private CRT key data for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE
+
+ +

Definition of bufer size (in bytes) for the private CRT key data for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE
+
+ +

Definition of bufer size (in bytes) for the private CRT key data for 4096-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE
+
+ +

Definition of bufer size (in bytes) for the public key data for 2048-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE
+
+ +

Definition of bufer size (in bytes) for the public key data for 3072-bit keys.

+ +
+
+ +

◆ MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE

+ +
+
+ + + + +
#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE
+
+ +

Definition of bufer size (in bytes) for the public key data for 4096-bit keys.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00848.js b/components/els_pkc/doc/mcxn/html/a00848.js new file mode 100644 index 000000000..83f914d4e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00848.js @@ -0,0 +1,12 @@ +var a00848 = +[ + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE", "a00848.html#gaad6be857cb7e5a3e95f09e0122f2e94a", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE", "a00848.html#gab391bd614cb01e50e382c9dd20c17666", null ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE", "a00848.html#gaa60cf674b45656cf7500cd50749d8088", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE", "a00848.html#ga726a733c6b7203ed8ffb1fcc542d3947", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE", "a00848.html#ga42819dfa5d08299cd05b1589d354aea8", null ], + [ "MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE", "a00848.html#ga9326e34e5b0cae6bba738466a089b523", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE", "a00848.html#gae34fdb8022b5b8b2d62794b19ed310cf", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE", "a00848.html#ga78776bc5abbc55e6ebe24450dac788f3", null ], + [ "MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE", "a00848.html#ga0cb2520b3056a154c1d551b2a677dd12", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00849.html b/components/els_pkc/doc/mcxn/html/a00849.html new file mode 100644 index 000000000..5dae17de7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00849.html @@ -0,0 +1,155 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Macros + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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mcuxClRsa_Macros
mcuxClRsa
+
+
+ +

Defines all macros of mcuxClRsa. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 MCUXCLRSA_SIGN_WA
 Definitions of workarea sizes for the mcuxClRsa Sign.
 
 MCUXCLRSA_VERIFY_WA
 Definitions of workarea sizes for the mcuxClRsa Verify.
 
 MCUXCLRSA_KEYGENERATION_CRT_WA
 Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function.
 
 MCUXCLRSA_KEYGENERATION_PLAIN_WA
 Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function.
 
 MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE
 Definitions of bufer sizes for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions.
 
 MCUXCLRSA_STATUS_
 Return code definitions.
 
 MCUXCLRSA_KEY_
 Key type definitions.
 
 MCUXCLRSA_OPTION_
 Function options definitions.
 
+

Detailed Description

+

Defines all macros of mcuxClRsa.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00849.js b/components/els_pkc/doc/mcxn/html/a00849.js new file mode 100644 index 000000000..76b7aaae1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00849.js @@ -0,0 +1,11 @@ +var a00849 = +[ + [ "MCUXCLRSA_SIGN_WA", "a00844.html", "a00844" ], + [ "MCUXCLRSA_VERIFY_WA", "a00845.html", "a00845" ], + [ "MCUXCLRSA_KEYGENERATION_CRT_WA", "a00846.html", "a00846" ], + [ "MCUXCLRSA_KEYGENERATION_PLAIN_WA", "a00847.html", "a00847" ], + [ "MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE", "a00848.html", "a00848" ], + [ "MCUXCLRSA_STATUS_", "a00850.html", "a00850" ], + [ "MCUXCLRSA_KEY_", "a00851.html", "a00851" ], + [ "MCUXCLRSA_OPTION_", "a00852.html", "a00852" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00850.html b/components/els_pkc/doc/mcxn/html/a00850.html new file mode 100644 index 000000000..07cb38aa9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00850.html @@ -0,0 +1,328 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
+
MCUXCLRSA_STATUS_
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Return code definitions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_STATUS_SIGN_OK
 RSA sign operation successful. More...
 
#define MCUXCLRSA_STATUS_VERIFY_OK
 RSA verify operation successful. More...
 
#define MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK
 RSA verify primitive operation (RSAVP1) successful. More...
 
#define MCUXCLRSA_STATUS_ERROR
 Error occurred during RSA operation. More...
 
#define MCUXCLRSA_STATUS_INVALID_INPUT
 Input data cannot be processed. More...
 
#define MCUXCLRSA_STATUS_VERIFY_FAILED
 Signature verification failed. More...
 
#define MCUXCLRSA_STATUS_FAULT_ATTACK
 Fault attack detected. More...
 
#define MCUXCLRSA_STATUS_KEYGENERATION_OK
 RSA key generation operation executed successfully. More...
 
#define MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED
 RSA key generation exceeds the limit of iterations to generate a prime. More...
 
#define MCUXCLRSA_STATUS_RNG_ERROR
 Random number (DRBG / PRNG) error (unexpected behavior) More...
 
+

Detailed Description

+

Return code definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_STATUS_SIGN_OK

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_SIGN_OK
+
+ +

RSA sign operation successful.

+
Examples
mcuxClRsa_sign_NoEncode_example.c, and mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_STATUS_VERIFY_OK

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_VERIFY_OK
+
+ +

RSA verify operation successful.

+
Examples
mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK
+
+ +

RSA verify primitive operation (RSAVP1) successful.

+
Examples
mcuxClRsa_verify_NoVerify_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_ERROR
+
+ +

Error occurred during RSA operation.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_INVALID_INPUT

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_INVALID_INPUT
+
+ +

Input data cannot be processed.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_VERIFY_FAILED

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_VERIFY_FAILED
+
+ +

Signature verification failed.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_FAULT_ATTACK
+
+ +

Fault attack detected.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_KEYGENERATION_OK

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_KEYGENERATION_OK
+
+ +

RSA key generation operation executed successfully.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED
+
+ +

RSA key generation exceeds the limit of iterations to generate a prime.

+ +
+
+ +

◆ MCUXCLRSA_STATUS_RNG_ERROR

+ +
+
+ + + + +
#define MCUXCLRSA_STATUS_RNG_ERROR
+
+ +

Random number (DRBG / PRNG) error (unexpected behavior)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00850.js b/components/els_pkc/doc/mcxn/html/a00850.js new file mode 100644 index 000000000..1ad8d2331 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00850.js @@ -0,0 +1,13 @@ +var a00850 = +[ + [ "MCUXCLRSA_STATUS_SIGN_OK", "a00850.html#gac7719ba5cbecc181bef2b21dca99fdf3", null ], + [ "MCUXCLRSA_STATUS_VERIFY_OK", "a00850.html#ga2dbb489ad7452a487a5d49df5a979d69", null ], + [ "MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK", "a00850.html#gadabda4063a5cfe9766a7201d271d8f0a", null ], + [ "MCUXCLRSA_STATUS_ERROR", "a00850.html#gac062bb04172f071a8595aa39bef80edc", null ], + [ "MCUXCLRSA_STATUS_INVALID_INPUT", "a00850.html#ga14e28c4e4b6a325ddd1f038b5274ccec", null ], + [ "MCUXCLRSA_STATUS_VERIFY_FAILED", "a00850.html#ga05d091562f747706d7aecfb99b5a735c", null ], + [ "MCUXCLRSA_STATUS_FAULT_ATTACK", "a00850.html#gaf886957f4dc2794dd12839a690ae05d0", null ], + [ "MCUXCLRSA_STATUS_KEYGENERATION_OK", "a00850.html#gab08354492e4b0feceab7a3615abee1f0", null ], + [ "MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED", "a00850.html#ga90072cc31c18394f5e5d3a2e63e014fa", null ], + [ "MCUXCLRSA_STATUS_RNG_ERROR", "a00850.html#gadd600ddd2a4c8c2fc79f427e438f81f4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00851.html b/components/els_pkc/doc/mcxn/html/a00851.html new file mode 100644 index 000000000..dacd27e50 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00851.html @@ -0,0 +1,212 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_KEY_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLRSA_KEY_
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Key type definitions. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLRSA_KEY_PUBLIC
 RSA key type public. More...
 
#define MCUXCLRSA_KEY_PRIVATEPLAIN
 RSA key type private plain. More...
 
#define MCUXCLRSA_KEY_PRIVATECRT
 RSA key type private CRT. More...
 
#define MCUXCLRSA_KEY_PRIVATECRT_DFA
 RSA key type private CRT, with which a fault-protected CRT operation is executed. More...
 
+

Detailed Description

+

Key type definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_KEY_PUBLIC

+ +
+
+ + + + +
#define MCUXCLRSA_KEY_PUBLIC
+
+ +

RSA key type public.

+
Examples
mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_KEY_PRIVATEPLAIN

+ +
+
+ + + + +
#define MCUXCLRSA_KEY_PRIVATEPLAIN
+
+ +

RSA key type private plain.

+
Examples
mcuxClRsa_sign_NoEncode_example.c, and mcuxClRsa_sign_pss_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_KEY_PRIVATECRT

+ +
+
+ + + + +
#define MCUXCLRSA_KEY_PRIVATECRT
+
+ +

RSA key type private CRT.

+ +
+
+ +

◆ MCUXCLRSA_KEY_PRIVATECRT_DFA

+ +
+
+ + + + +
#define MCUXCLRSA_KEY_PRIVATECRT_DFA
+
+ +

RSA key type private CRT, with which a fault-protected CRT operation is executed.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00851.js b/components/els_pkc/doc/mcxn/html/a00851.js new file mode 100644 index 000000000..b598d5902 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00851.js @@ -0,0 +1,7 @@ +var a00851 = +[ + [ "MCUXCLRSA_KEY_PUBLIC", "a00851.html#ga4c194e24352de4ab02294292f35f24d9", null ], + [ "MCUXCLRSA_KEY_PRIVATEPLAIN", "a00851.html#ga16c4298a66c8a1a7c2e18aca938442a6", null ], + [ "MCUXCLRSA_KEY_PRIVATECRT", "a00851.html#gade33615f2bc73e552ca020a1e43a41c3", null ], + [ "MCUXCLRSA_KEY_PRIVATECRT_DFA", "a00851.html#gac5562ce31d1bc26cf93b647a17e38814", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00852.html b/components/els_pkc/doc/mcxn/html/a00852.html new file mode 100644 index 000000000..ea0d4ebe9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00852.html @@ -0,0 +1,191 @@ + + + + + + + +MCUX CLNS: MCUXCLRSA_OPTION_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLRSA_OPTION_
mcuxClRsa » mcuxClRsa_Macros
+
+
+ +

Function options definitions. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCLRSA_OPTION_MESSAGE_PLAIN
 Option passing a plain message as input to the sign or verify operation. More...
 
#define MCUXCLRSA_OPTION_MESSAGE_DIGEST
 Option passing a message digest as input to the sign or verify operation. More...
 
#define MCUXCLRSA_OPTION_MESSAGE_MASK
 Mask to set option MESSAGE_PLAIN or MESSAGE_DIGEST. More...
 
+

Detailed Description

+

Function options definitions.

+

Macro Definition Documentation

+ +

◆ MCUXCLRSA_OPTION_MESSAGE_PLAIN

+ +
+
+ + + + +
#define MCUXCLRSA_OPTION_MESSAGE_PLAIN
+
+ +

Option passing a plain message as input to the sign or verify operation.

+ +
+
+ +

◆ MCUXCLRSA_OPTION_MESSAGE_DIGEST

+ +
+
+ + + + +
#define MCUXCLRSA_OPTION_MESSAGE_DIGEST
+
+ +

Option passing a message digest as input to the sign or verify operation.

+
Examples
mcuxClRsa_sign_pss_sha2_256_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRSA_OPTION_MESSAGE_MASK

+ +
+
+ + + + +
#define MCUXCLRSA_OPTION_MESSAGE_MASK
+
+ +

Mask to set option MESSAGE_PLAIN or MESSAGE_DIGEST.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00852.js b/components/els_pkc/doc/mcxn/html/a00852.js new file mode 100644 index 000000000..b84d92926 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00852.js @@ -0,0 +1,6 @@ +var a00852 = +[ + [ "MCUXCLRSA_OPTION_MESSAGE_PLAIN", "a00852.html#ga60de22c98680641aaef3331fbd5bb0f1", null ], + [ "MCUXCLRSA_OPTION_MESSAGE_DIGEST", "a00852.html#gaae780b6c51aa31e7e9f20cb2afddf9c6", null ], + [ "MCUXCLRSA_OPTION_MESSAGE_MASK", "a00852.html#gac091ddc4844c510873c4492061ce7a5f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00853.html b/components/els_pkc/doc/mcxn/html/a00853.html new file mode 100644 index 000000000..3f83fd9f6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00853.html @@ -0,0 +1,256 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs
+
+
mcuxClRsa_Types
mcuxClRsa
+
+
+ +

Defines all types of the mcuxClRsa component. +More...

+ + + + + + + + +

+Data Structures

struct  mcuxClRsa_KeyEntry_t
 Structure type for Rsa key entries, specifying key entry length and data. More...
 
struct  mcuxClRsa_Key
 Structure type for Rsa key, specifying key type and key entries. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClRsa_Status_t
 Type for RSA status codes. More...
 
typedef mcuxClRsa_Status_t mcuxClRsa_Status_Protected_t
 Deprecated type for RSA protected status codes. More...
 
typedef mcuxClRsa_KeyEntry_t * mcuxClRsa_KeyEntry
 Pointer type to Rsa key entries. More...
 
typedef struct mcuxClRsa_Key mcuxClRsa_Key
 Structure type for Rsa key, specifying key type and key entries. More...
 
typedef struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t
 Forward declaration of Sign/Verify mode struct. More...
 
typedef mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode
 Pointer type to Sign/Verify mode. More...
 
+

Detailed Description

+

Defines all types of the mcuxClRsa component.

+

Typedef Documentation

+ +

◆ mcuxClRsa_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClRsa_Status_t
+
+ +

Type for RSA status codes.

+ +
+
+ +

◆ mcuxClRsa_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClRsa_Status_t mcuxClRsa_Status_Protected_t
+
+ +

Deprecated type for RSA protected status codes.

+ +
+
+ +

◆ mcuxClRsa_KeyEntry

+ +
+
+ + + + +
typedef mcuxClRsa_KeyEntry_t* mcuxClRsa_KeyEntry
+
+ +

Pointer type to Rsa key entries.

+ +
+
+ +

◆ mcuxClRsa_Key

+ +
+
+ + + + +
typedef struct mcuxClRsa_Key mcuxClRsa_Key
+
+ +

Structure type for Rsa key, specifying key type and key entries.

+ +
+
+ +

◆ mcuxClRsa_SignVerifyMode_t

+ +
+
+ + + + +
typedef struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t
+
+ +

Forward declaration of Sign/Verify mode struct.

+ +
+
+ +

◆ mcuxClRsa_SignVerifyMode

+ +
+
+ + + + +
typedef mcuxClRsa_SignVerifyMode_t* mcuxClRsa_SignVerifyMode
+
+ +

Pointer type to Sign/Verify mode.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00853.js b/components/els_pkc/doc/mcxn/html/a00853.js new file mode 100644 index 000000000..dbfd2d922 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00853.js @@ -0,0 +1,22 @@ +var a00853 = +[ + [ "mcuxClRsa_KeyEntry_t", "a01269.html", [ + [ "pKeyEntryData", "a01269.html#a1f5a90f95105b9abaf31a7997a2fb24e", null ], + [ "keyEntryLength", "a01269.html#a441763378fea50af88f8cdf75648a0e6", null ] + ] ], + [ "mcuxClRsa_Key", "a01273.html", [ + [ "keytype", "a01273.html#a8d0791ef8960a4316931f55f5848c3fa", null ], + [ "pMod1", "a01273.html#ab53f60022abcb2c60300022907c460ce", null ], + [ "pMod2", "a01273.html#ab1b71c75486149a0b722dfe36d3ca6cd", null ], + [ "pQInv", "a01273.html#aa9188b106fa0b275218f8dc04fd9fa79", null ], + [ "pExp1", "a01273.html#a28deb463bb016edacb1938dc272deb8a", null ], + [ "pExp2", "a01273.html#accac28790b11f7574dd84f6da9877a2c", null ], + [ "pExp3", "a01273.html#a0846b30142dc6cb42d05b5c30afd71cc", null ] + ] ], + [ "mcuxClRsa_Status_t", "a00853.html#gab654093108d59a4690e464f314356e69", null ], + [ "mcuxClRsa_Status_Protected_t", "a00853.html#ga60189e258e6739b78e900b025be0ab34", null ], + [ "mcuxClRsa_KeyEntry", "a00853.html#ga45ab9e1108bb7a629af14c74d8392622", null ], + [ "mcuxClRsa_Key", "a00853.html#gaa10abda6e87540ddd4db42c84aa5f8f5", null ], + [ "mcuxClRsa_SignVerifyMode_t", "a00853.html#gabe334b37ac763b3943364b26e130d0df", null ], + [ "mcuxClRsa_SignVerifyMode", "a00853.html#ga9135a8d95f26a1b90c7a251886bce7e5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00854.html b/components/els_pkc/doc/mcxn/html/a00854.html new file mode 100644 index 000000000..03c682f19 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00854.html @@ -0,0 +1,163 @@ + + + + + + + +MCUX CLNS: mcuxClSession + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClSession
+
+
+ +

This component provides functions for managing a session. +More...

+ + + + + + + + + + + +

+Modules

 mcuxClSession_Functions
 Defines all functions of mcuxClSession.
 
 mcuxClSession_Constants
 Defines all constants of mcuxClSession.
 
 mcuxClSession_Types
 Defines all types of mcuxClSession.
 
+

Detailed Description

+

This component provides functions for managing a session.

+

A session groups references to all the resources that a function to perform its operation needs into one structure. It contains references to buffers for working memory, random number generation, configuration data (e.g. for security features), etc...

+

The library exposes the following functionality:

    +
  1. +Initialization, cleanup and destruction + + +
    2. +
  2. +Configuration +
    3. +
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00854.js b/components/els_pkc/doc/mcxn/html/a00854.js new file mode 100644 index 000000000..3f49886ad --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00854.js @@ -0,0 +1,6 @@ +var a00854 = +[ + [ "mcuxClSession_Functions", "a00855.html", "a00855" ], + [ "mcuxClSession_Constants", "a00856.html", "a00856" ], + [ "mcuxClSession_Types", "a00859.html", "a00859" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00855.html b/components/els_pkc/doc/mcxn/html/a00855.html new file mode 100644 index 000000000..f6bcca39f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00855.html @@ -0,0 +1,326 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Functions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxClSession_Functions
mcuxClSession
+
+
+ +

Defines all functions of mcuxClSession. +More...

+ + + + + + + + + + + + + + +

+Functions

mcuxClSession_Status_t mcuxClSession_init (mcuxClSession_Handle_t pSession, uint32_t *const pCpuWaBuffer, uint32_t cpuWaLength, uint32_t *const pPkcWaBuffer, uint32_t pkcWaLength)
 Initialize a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_setRtf (mcuxClSession_Handle_t pSession, uint8_t *const pRtf, mcuxClSession_Rtf_t RtfOptions)
 Set the RTF option in a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_cleanup (mcuxClSession_Handle_t pSession)
 Clean up a Crypto Library session. More...
 
mcuxClSession_Status_t mcuxClSession_destroy (mcuxClSession_Handle_t pSession)
 Destroy a Crypto Library session. More...
 
+

Detailed Description

+

Defines all functions of mcuxClSession.

+

Function Documentation

+ +

◆ mcuxClSession_init()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClSession_Status_t mcuxClSession_init (mcuxClSession_Handle_t pSession,
uint32_t *const pCpuWaBuffer,
uint32_t cpuWaLength,
uint32_t *const pPkcWaBuffer,
uint32_t pkcWaLength 
)
+
+ +

Initialize a Crypto Library session.

+
Parameters
+ + + + + + +
pSessionSession to be initialized.
pCpuWaBufferPointer to buffer to be used as workarea for CPU operations. This pointer shall be CPU-word aligned.
cpuWaLengthSize (in bytes) of the workarea for CPU operations. The size shall be a multiple of CPU wordsize.
pPkcWaBufferPointer to buffer to be used as workarea for PKC operations. This pointer shall be PKC-word aligned.
pkcWaLengthSize (in bytes) of the workarea for PKC operations. The size shall be a multiple of CPU wordsize.
+
+
+
Returns
status
+
Return values
+ + + +
MCUXCLSESSION_STATUS_OKSession has been initialized successfully
MCUXCLSESSION_STATUS_ERRORError occurred during session initializing.
+
+
+
Examples
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+ +

◆ mcuxClSession_setRtf()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClSession_Status_t mcuxClSession_setRtf (mcuxClSession_Handle_t pSession,
uint8_t *const pRtf,
mcuxClSession_Rtf_t RtfOptions 
)
+
+ +

Set the RTF option in a Crypto Library session.

+
Parameters
+ + + + +
pSessionSession to be initialized.
pRtfbuffer to store the rtf result.
RtfOptionsOptions to define RTF processing.
+
+
+
Returns
status
+ +
+
+ +

◆ mcuxClSession_cleanup()

+ +
+
+ + + + + + + + +
mcuxClSession_Status_t mcuxClSession_cleanup (mcuxClSession_Handle_t pSession)
+
+ +

Clean up a Crypto Library session.

+

This function will (securely) cleanup the session, which will still be usable afterwards.

+
Parameters
+ + +
pSessionSession to be cleaned.
+
+
+
Returns
status
+
Return values
+ + +
MCUXCLSESSION_STATUS_OKSession operation successful
+
+
+ +
+
+ +

◆ mcuxClSession_destroy()

+ +
+
+ + + + + + + + +
mcuxClSession_Status_t mcuxClSession_destroy (mcuxClSession_Handle_t pSession)
+
+ +

Destroy a Crypto Library session.

+

This function will (securely) cleanup the session, including uninitialization etc. The session will no longer be usable afterwards.

+
Parameters
+ + +
pSessionSession to be destroyed.
+
+
+
Returns
status
+
Return values
+ + + +
MCUXCLSESSION_STATUS_OKSession operation successful
MCUXCLSESSION_STATUS_ERRORError occurred during Session operation
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00855.js b/components/els_pkc/doc/mcxn/html/a00855.js new file mode 100644 index 000000000..2791b5465 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00855.js @@ -0,0 +1,7 @@ +var a00855 = +[ + [ "mcuxClSession_init", "a00855.html#gaf1b8776b0d519136df17f6dd632442cf", null ], + [ "mcuxClSession_setRtf", "a00855.html#ga159bff529d405fd6da2930590a69ac06", null ], + [ "mcuxClSession_cleanup", "a00855.html#ga1ba3d2c6e561c86e1da8fcc0abfd046c", null ], + [ "mcuxClSession_destroy", "a00855.html#gaad324fd8f8eeefa29521c4297ac75fd2", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00856.html b/components/els_pkc/doc/mcxn/html/a00856.html new file mode 100644 index 000000000..9eb21bbe9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00856.html @@ -0,0 +1,135 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Constants + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxClSession_Constants
mcuxClSession
+
+
+ +

Defines all constants of mcuxClSession. +More...

+ + + + + + +

+Modules

 Session Status values
 
 Session RTF configuration values
 
+

Detailed Description

+

Defines all constants of mcuxClSession.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00856.js b/components/els_pkc/doc/mcxn/html/a00856.js new file mode 100644 index 000000000..d164d2bea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00856.js @@ -0,0 +1,5 @@ +var a00856 = +[ + [ "Session Status values", "a00857.html", "a00857" ], + [ "Session RTF configuration values", "a00858.html", "a00858" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00857.html b/components/els_pkc/doc/mcxn/html/a00857.html new file mode 100644 index 000000000..487dbc8c6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00857.html @@ -0,0 +1,187 @@ + + + + + + + +MCUX CLNS: Session Status values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Session Status values
mcuxClSession » mcuxClSession_Constants
+
+
+ + + + + + + + + + + +

+Macros

#define MCUXCLSESSION_STATUS_OK
 Session operation successful. More...
 
#define MCUXCLSESSION_STATUS_ERROR
 Error occurred during Session operation. More...
 
#define MCUXCLSESSION_STATUS_HW_UNAVAILABLE
 Required HW is unavailable. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +

◆ MCUXCLSESSION_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLSESSION_STATUS_OK
+
+ +

Session operation successful.

+
Examples
mcuxClRandomModes_Different_Sessions_example.c, and mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+ +

◆ MCUXCLSESSION_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLSESSION_STATUS_ERROR
+
+ +

Error occurred during Session operation.

+ +
+
+ +

◆ MCUXCLSESSION_STATUS_HW_UNAVAILABLE

+ +
+
+ + + + +
#define MCUXCLSESSION_STATUS_HW_UNAVAILABLE
+
+ +

Required HW is unavailable.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00857.js b/components/els_pkc/doc/mcxn/html/a00857.js new file mode 100644 index 000000000..a1c95459e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00857.js @@ -0,0 +1,6 @@ +var a00857 = +[ + [ "MCUXCLSESSION_STATUS_OK", "a00857.html#ga3f63cf17e4f26ba5ee4d92152fca1eb6", null ], + [ "MCUXCLSESSION_STATUS_ERROR", "a00857.html#ga547425b7379de3ee1fb96c79140fd68e", null ], + [ "MCUXCLSESSION_STATUS_HW_UNAVAILABLE", "a00857.html#gaa3a0727f4c8a2658cb607d45cd28229e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00858.html b/components/els_pkc/doc/mcxn/html/a00858.html new file mode 100644 index 000000000..b0676b362 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00858.html @@ -0,0 +1,166 @@ + + + + + + + +MCUX CLNS: Session RTF configuration values + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Session RTF configuration values
mcuxClSession » mcuxClSession_Constants
+
+
+ + + + + + + + +

+Macros

#define MCUXCLSESSION_RTF_UPDATE_TRUE
 RTF will be updated. More...
 
#define MCUXCLSESSION_RTF_UPDATE_FALSE
 RTF will not be updated. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +

◆ MCUXCLSESSION_RTF_UPDATE_TRUE

+ +
+
+ + + + +
#define MCUXCLSESSION_RTF_UPDATE_TRUE
+
+ +

RTF will be updated.

+ +
+
+ +

◆ MCUXCLSESSION_RTF_UPDATE_FALSE

+ +
+
+ + + + +
#define MCUXCLSESSION_RTF_UPDATE_FALSE
+
+ +

RTF will not be updated.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00858.js b/components/els_pkc/doc/mcxn/html/a00858.js new file mode 100644 index 000000000..5cc40962f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00858.js @@ -0,0 +1,5 @@ +var a00858 = +[ + [ "MCUXCLSESSION_RTF_UPDATE_TRUE", "a00858.html#ga17963249b8a091124c5442ca642a55d8", null ], + [ "MCUXCLSESSION_RTF_UPDATE_FALSE", "a00858.html#ga922a60abc33fb57bb5b4587324f2d73c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00859.html b/components/els_pkc/doc/mcxn/html/a00859.html new file mode 100644 index 000000000..78f0b6f80 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00859.html @@ -0,0 +1,297 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Structures | +Typedefs
+
+
mcuxClSession_Types
mcuxClSession
+
+
+ +

Defines all types of mcuxClSession. +More...

+ + + + + + + + + + + +

+Data Structures

struct  mcuxClSession_WorkArea
 Type for mcuxClSession workareas flags. More...
 
struct  mcuxClSession_SecurityContext
 Type for mcuxClSession security context. More...
 
struct  mcuxClSession_Descriptor
 Type for mcuxClSession Descriptor. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef uint32_t mcuxClSession_Status_t
 Type for mcuxClSession status codes. More...
 
typedef mcuxClSession_Status_t mcuxClSession_Status_Protected_t
 Deprecated type for mcuxClSession protected status codes. More...
 
typedef uint32_t mcuxClSession_Rtf_t
 Type for mcuxClSession RTF configuration flags. More...
 
typedef struct mcuxClSession_WorkArea mcuxClSession_WorkArea_t
 Type for mcuxClSession workareas flags. More...
 
typedef struct mcuxClSession_SecurityContext mcuxClSession_SecurityContext_t
 Type for mcuxClSession security context. More...
 
typedef uint32_t mcuxClSession_SecurityOptions_t
 Type for Session security options. More...
 
typedef struct mcuxClSession_Descriptor mcuxClSession_Descriptor_t
 Type for mcuxClSession Descriptor. More...
 
typedef mcuxClSession_Descriptor_t *const mcuxClSession_Handle_t
 Type for mcuxClSession Handle. More...
 
+

Detailed Description

+

Defines all types of mcuxClSession.

+

Typedef Documentation

+ +

◆ mcuxClSession_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClSession_Status_t
+
+ +

Type for mcuxClSession status codes.

+ +
+
+ +

◆ mcuxClSession_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClSession_Status_t mcuxClSession_Status_Protected_t
+
+ +

Deprecated type for mcuxClSession protected status codes.

+ +
+
+ +

◆ mcuxClSession_Rtf_t

+ +
+
+ + + + +
typedef uint32_t mcuxClSession_Rtf_t
+
+ +

Type for mcuxClSession RTF configuration flags.

+ +
+
+ +

◆ mcuxClSession_WorkArea_t

+ +
+
+ + + + +
typedef struct mcuxClSession_WorkArea mcuxClSession_WorkArea_t
+
+ +

Type for mcuxClSession workareas flags.

+ +
+
+ +

◆ mcuxClSession_SecurityContext_t

+ +
+
+ + + + +
typedef struct mcuxClSession_SecurityContext mcuxClSession_SecurityContext_t
+
+ +

Type for mcuxClSession security context.

+ +
+
+ +

◆ mcuxClSession_SecurityOptions_t

+ +
+
+ + + + +
typedef uint32_t mcuxClSession_SecurityOptions_t
+
+ +

Type for Session security options.

+ +
+
+ +

◆ mcuxClSession_Descriptor_t

+ +
+
+ + + + +
typedef struct mcuxClSession_Descriptor mcuxClSession_Descriptor_t
+
+ +

Type for mcuxClSession Descriptor.

+ +
+
+ +

◆ mcuxClSession_Handle_t

+ +
+
+ + + + +
typedef mcuxClSession_Descriptor_t* const mcuxClSession_Handle_t
+
+ +

Type for mcuxClSession Handle.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00859.js b/components/els_pkc/doc/mcxn/html/a00859.js new file mode 100644 index 000000000..8eeabf035 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00859.js @@ -0,0 +1,26 @@ +var a00859 = +[ + [ "mcuxClSession_WorkArea", "a01277.html", [ + [ "buffer", "a01277.html#acd3913d2b4adf01d7d95c687c578c752", null ], + [ "size", "a01277.html#a372ca932239a945030d51a23913c36e0", null ], + [ "used", "a01277.html#ab3280a7d27aa7837287e2fa4376492fb", null ], + [ "dirty", "a01277.html#a500aa3a1084704dbd9622a247458b9b1", null ] + ] ], + [ "mcuxClSession_SecurityContext", "a01281.html", [ + [ "securityCounter", "a01281.html#a3bca2e1ffbfa74a0afd525444dee8f16", null ] + ] ], + [ "mcuxClSession_Descriptor", "a01285.html", [ + [ "cpuWa", "a01285.html#a8e3448a94cee26e27929d48656dcacb8", null ], + [ "pkcWa", "a01285.html#a394996570a6810808bd59d2f9672c76a", null ], + [ "rtf", "a01285.html#ab1b8f498d45832cba336165e6761ce0d", null ], + [ "pRtf", "a01285.html#a2c4ebdaa00f8277aa174313ced71a4b6", null ] + ] ], + [ "mcuxClSession_Status_t", "a00859.html#ga9f2ec672d5a5fe92159f0e6159e04e4e", null ], + [ "mcuxClSession_Status_Protected_t", "a00859.html#ga09bbfe382aac167ec94e8e6e3d2b10f6", null ], + [ "mcuxClSession_Rtf_t", "a00859.html#gac635eeca4268dbd500e45806ee37f685", null ], + [ "mcuxClSession_WorkArea_t", "a00859.html#ga13a1a61b81f8b8bdc5272d33b44a2dac", null ], + [ "mcuxClSession_SecurityContext_t", "a00859.html#gac2866aae4d5a869b0fa55c82190d0c93", null ], + [ "mcuxClSession_SecurityOptions_t", "a00859.html#gabd24855c86970aaa97d3c6975a8ca53c", null ], + [ "mcuxClSession_Descriptor_t", "a00859.html#gafe6e209ab6b552af2011043383473f18", null ], + [ "mcuxClSession_Handle_t", "a00859.html#ga17fd337618b05459b4a343393e099b56", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00860.html b/components/els_pkc/doc/mcxn/html/a00860.html new file mode 100644 index 000000000..c8f1702d5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00860.html @@ -0,0 +1,142 @@ + + + + + + + +MCUX CLNS: MCUX CSSL – API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
MCUX CSSL – API
+
+
+ + + + + + + + + + + + + + + + + +

+Modules

 Data Integrity API
 Data integrity mechanism.
 
 Flow Protection API
 Flow protection mechanism.
 
 mcuxCssl Memory API
 Control Flow Protected Memory Functions.
 
 Parameter Integrity API
 Functionality to ensure parameter integrity during function calls.
 
 Secure Counter API
 Secure counter mechanism.
 
+

Detailed Description

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00860.js b/components/els_pkc/doc/mcxn/html/a00860.js new file mode 100644 index 000000000..085189d4d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00860.js @@ -0,0 +1,8 @@ +var a00860 = +[ + [ "Data Integrity API", "a00861.html", "a00861" ], + [ "Flow Protection API", "a00870.html", "a00870" ], + [ "mcuxCssl Memory API", "a00885.html", "a00885" ], + [ "Parameter Integrity API", "a00897.html", "a00897" ], + [ "Secure Counter API", "a00901.html", "a00901" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00861.html b/components/els_pkc/doc/mcxn/html/a00861.html new file mode 100644 index 000000000..f447cbf0c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00861.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: Data Integrity API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Data Integrity API
MCUX CSSL &ndash; API
+
+
+ +

Data integrity mechanism. +More...

+ + + + + + + + +

+Modules

 Data integrity core functionality
 Data integrity handling core functionality.
 
 Data integrity record
 Support for recording a value in the data integrity register.
 
+

Detailed Description

+

Data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00861.js b/components/els_pkc/doc/mcxn/html/a00861.js new file mode 100644 index 000000000..05af8a597 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00861.js @@ -0,0 +1,5 @@ +var a00861 = +[ + [ "Data integrity core functionality", "a00862.html", "a00862" ], + [ "Data integrity record", "a00863.html", "a00863" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00862.html b/components/els_pkc/doc/mcxn/html/a00862.html new file mode 100644 index 000000000..ece236c15 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00862.html @@ -0,0 +1,270 @@ + + + + + + + +MCUX CLNS: Data integrity core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data integrity core functionality
MCUX CSSL &ndash; API » Data Integrity API
+
+
+ +

Data integrity handling core functionality. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_DI_CHECK_PASSED
 Positive comparison result value. More...
 
#define MCUX_CSSL_DI_CHECK_FAILED
 Negative comparison result value. More...
 
#define MCUX_CSSL_DI_INIT_DEFAULT_VALUE
 Default value use for the initialization of the data integrity mechanism. More...
 
#define MCUX_CSSL_DI_ALLOC()
 Allocation operation for the data integrity register. More...
 
#define MCUX_CSSL_DI_INIT(value)
 Initialization operation for the data integrity mechanism. More...
 
#define MCUX_CSSL_DI_CHECK(reference)
 Comparison operation for the data integrity. More...
 
+

Detailed Description

+

Data integrity handling core functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_DI_CHECK_PASSED

+ +
+
+ + + + +
#define MCUX_CSSL_DI_CHECK_PASSED
+
+ +

Positive comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_DI_CHECK_FAILED

+ +
+
+ + + + +
#define MCUX_CSSL_DI_CHECK_FAILED
+
+ +

Negative comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_DI_INIT_DEFAULT_VALUE

+ +
+
+ + + + +
#define MCUX_CSSL_DI_INIT_DEFAULT_VALUE
+
+ +

Default value use for the initialization of the data integrity mechanism.

+ +
+
+ +

◆ MCUX_CSSL_DI_ALLOC

+ +
+
+ + + + + + + +
#define MCUX_CSSL_DI_ALLOC()
+
+ +

Allocation operation for the data integrity register.

+ +
+
+ +

◆ MCUX_CSSL_DI_INIT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_DI_INIT( value)
+
+ +

Initialization operation for the data integrity mechanism.

+
Parameters
+ + +
valueValue with which the data integrity register must be initialized.
+
+
+ +
+
+ +

◆ MCUX_CSSL_DI_CHECK

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_DI_CHECK( reference)
+
+ +

Comparison operation for the data integrity.

+
Parameters
+ + +
referenceReference value to compare the data integrity value against.
+
+
+
Returns
Either MCUX_CSSL_DI_CHECK_PASSED, if the value matches, or MCUX_CSSL_DI_CHECK_FAILED if the value is different.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00862.js b/components/els_pkc/doc/mcxn/html/a00862.js new file mode 100644 index 000000000..a40db7750 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00862.js @@ -0,0 +1,9 @@ +var a00862 = +[ + [ "MCUX_CSSL_DI_CHECK_PASSED", "a00862.html#gaf795c9830ecd5c53d21ae5efb05716c0", null ], + [ "MCUX_CSSL_DI_CHECK_FAILED", "a00862.html#ga836c5e13eae4d1fdcfe33a41051c26b5", null ], + [ "MCUX_CSSL_DI_INIT_DEFAULT_VALUE", "a00862.html#ga43f4285ae50273c0c9ddd7bb4afa123d", null ], + [ "MCUX_CSSL_DI_ALLOC", "a00862.html#ga7f64db7a5134579f6225fc87a04c9e10", null ], + [ "MCUX_CSSL_DI_INIT", "a00862.html#ga8e9f35be6109155f823f827707af31fb", null ], + [ "MCUX_CSSL_DI_CHECK", "a00862.html#ga86a850875eca35952e2c3a8312364896", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00863.html b/components/els_pkc/doc/mcxn/html/a00863.html new file mode 100644 index 000000000..7aca8bce8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00863.html @@ -0,0 +1,212 @@ + + + + + + + +MCUX CLNS: Data integrity record + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data integrity record
MCUX CSSL &ndash; API » Data Integrity API
+
+
+ +

Support for recording a value in the data integrity register. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_DI_RECORD(identifier, value)
 Record the value for data integrity checking. More...
 
#define MCUX_CSSL_DI_EXPUNGE(identifier, value)
 Expunge the record for value. More...
 
+

Detailed Description

+

Support for recording a value in the data integrity register.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_DI_RECORD

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_DI_RECORD( identifier,
 value 
)
+
+ +

Record the value for data integrity checking.

+
Parameters
+ + + +
identifierIdentifier for the value that will be recorded.
valueValue which needs to be recorded for the given identifier.
+
+
+ +
+
+ +

◆ MCUX_CSSL_DI_EXPUNGE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_DI_EXPUNGE( identifier,
 value 
)
+
+ +

Expunge the record for value.

+
Parameters
+ + + +
identifierIdentifier for the value that will be expunged.
valueExpected value that was recorded for the given identifier.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00863.js b/components/els_pkc/doc/mcxn/html/a00863.js new file mode 100644 index 000000000..f78554c56 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00863.js @@ -0,0 +1,5 @@ +var a00863 = +[ + [ "MCUX_CSSL_DI_RECORD", "a00863.html#ga885885837b7340002b9782ffc41e4842", null ], + [ "MCUX_CSSL_DI_EXPUNGE", "a00863.html#ga3e10066c4efffa9040982cde10a52076", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00864.html b/components/els_pkc/doc/mcxn/html/a00864.html new file mode 100644 index 000000000..e07165d8b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00864.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: MCUX CSSL – Configurations + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
MCUX CSSL – Configurations
+
+
+ + + + + + + + + + + +

+Modules

 Data Integrity Configuration
 Configuration options for the data integrity mechanism.
 
 Flow Protection Configuration
 Configuration options for the flow protection mechanism.
 
 Secure Counter Configuration
 Configuration options for the secure counter mechanism.
 
+

Detailed Description

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00864.js b/components/els_pkc/doc/mcxn/html/a00864.js new file mode 100644 index 000000000..b95e636f5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00864.js @@ -0,0 +1,6 @@ +var a00864 = +[ + [ "Data Integrity Configuration", "a00865.html", "a00865" ], + [ "Flow Protection Configuration", "a00877.html", "a00877" ], + [ "Secure Counter Configuration", "a00906.html", "a00906" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00865.html b/components/els_pkc/doc/mcxn/html/a00865.html new file mode 100644 index 000000000..ec9d72db7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00865.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: Data Integrity Configuration + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data Integrity Configuration
MCUX CSSL &ndash; Configurations
+
+
+ +

Configuration options for the data integrity mechanism. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_DI_USE_SECURE_COUNTER
 If set to 1, use the data integrity mechanism implementation based on the CSSL secure counter mechanism. More...
 
#define MCUX_CSSL_DI_USE_NONE
 If set to 1, do not use the data integrity mechanism. More...
 
+

Detailed Description

+

Configuration options for the data integrity mechanism.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_DI_USE_SECURE_COUNTER

+ +
+
+ + + + +
#define MCUX_CSSL_DI_USE_SECURE_COUNTER
+
+ +

If set to 1, use the data integrity mechanism implementation based on the CSSL secure counter mechanism.

+ +
+
+ +

◆ MCUX_CSSL_DI_USE_NONE

+ +
+
+ + + + +
#define MCUX_CSSL_DI_USE_NONE
+
+ +

If set to 1, do not use the data integrity mechanism.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00865.js b/components/els_pkc/doc/mcxn/html/a00865.js new file mode 100644 index 000000000..eb69b8110 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00865.js @@ -0,0 +1,5 @@ +var a00865 = +[ + [ "MCUX_CSSL_DI_USE_SECURE_COUNTER", "a00865.html#gad14940e758b00b26f2e699b4fc0144bb", null ], + [ "MCUX_CSSL_DI_USE_NONE", "a00865.html#ga4f0cea555852c5171e55303b6cb062be", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00866.html b/components/els_pkc/doc/mcxn/html/a00866.html new file mode 100644 index 000000000..8b73275ce --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00866.html @@ -0,0 +1,139 @@ + + + + + + + +MCUX CLNS: MCUX CSSL – Implementations + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
MCUX CSSL – Implementations
+
+
+ + + + + + + + + + + + + + +

+Modules

 Data Integrity: Disabled
 Disable the data integrity mechanism.
 
 Flow Protection: Secure Counter
 Secure counter based implementation for the flow protection mechanism.
 
 Secure Counter: Disabled
 Disable the secure counter mechanism.
 
 Secure Counter: SW Local
 Secure counter mechanism implementation using a local variable.
 
+

Detailed Description

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00866.js b/components/els_pkc/doc/mcxn/html/a00866.js new file mode 100644 index 000000000..6be53187e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00866.js @@ -0,0 +1,7 @@ +var a00866 = +[ + [ "Data Integrity: Disabled", "a00867.html", "a00867" ], + [ "Flow Protection: Secure Counter", "a00878.html", "a00878" ], + [ "Secure Counter: Disabled", "a00907.html", "a00907" ], + [ "Secure Counter: SW Local", "a00912.html", "a00912" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00867.html b/components/els_pkc/doc/mcxn/html/a00867.html new file mode 100644 index 000000000..9ff58cab3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00867.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: Data Integrity: Disabled + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Data Integrity: Disabled
MCUX CSSL &ndash; Implementations
+
+
+ +

Disable the data integrity mechanism. +More...

+ + + + + + + + +

+Modules

 Data integrity core functionality
 Data integrity handling core functionality, when data integrity is disabled.
 
 Data integrity record
 Support for recording a value in the data integrity register, when data integrity is disabled.
 
+

Detailed Description

+

Disable the data integrity mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00867.js b/components/els_pkc/doc/mcxn/html/a00867.js new file mode 100644 index 000000000..7ecce5f1b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00867.js @@ -0,0 +1,5 @@ +var a00867 = +[ + [ "Data integrity core functionality", "a00868.html", "a00868" ], + [ "Data integrity record", "a00869.html", "a00869" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00868.html b/components/els_pkc/doc/mcxn/html/a00868.html new file mode 100644 index 000000000..fc8ff748e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00868.html @@ -0,0 +1,251 @@ + + + + + + + +MCUX CLNS: Data integrity core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data integrity core functionality
MCUX CSSL &ndash; Implementations » Data Integrity: Disabled
+
+
+ +

Data integrity handling core functionality, when data integrity is disabled. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_DI_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_DI_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_DI_ALLOC_IMPL()
 Allocation operation implementation for the data integrity. More...
 
#define MCUX_CSSL_DI_INIT_IMPL(value)
 Initialization operation implementation for the data integrity. More...
 
#define MCUX_CSSL_DI_CHECK_IMPL(reference)
 Comparison operation implementation for the data integrity. More...
 
+

Detailed Description

+

Data integrity handling core functionality, when data integrity is disabled.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_DI_CHECK_PASSED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_DI_CHECK_PASSED_IMPL
+
+ +

Positive comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_DI_CHECK_FAILED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_DI_CHECK_FAILED_IMPL
+
+ +

Negative comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_DI_ALLOC_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_DI_ALLOC_IMPL()
+
+ +

Allocation operation implementation for the data integrity.

+ +
+
+ +

◆ MCUX_CSSL_DI_INIT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_DI_INIT_IMPL( value)
+
+ +

Initialization operation implementation for the data integrity.

+
Parameters
+ + +
valueValue with which the data integrity must be initialized.
+
+
+ +
+
+ +

◆ MCUX_CSSL_DI_CHECK_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_DI_CHECK_IMPL( reference)
+
+ +

Comparison operation implementation for the data integrity.

+
Parameters
+ + +
referenceReference value to compare the data integrity value against.
+
+
+
Returns
Always MCUX_CSSL_DI_CHECK_PASSED.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00868.js b/components/els_pkc/doc/mcxn/html/a00868.js new file mode 100644 index 000000000..cacefce75 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00868.js @@ -0,0 +1,8 @@ +var a00868 = +[ + [ "MCUX_CSSL_DI_CHECK_PASSED_IMPL", "a00868.html#ga4deb1836544c454f189e5aefe3a16b90", null ], + [ "MCUX_CSSL_DI_CHECK_FAILED_IMPL", "a00868.html#ga381a9c96de77bfc8d099d9ebcc54f71b", null ], + [ "MCUX_CSSL_DI_ALLOC_IMPL", "a00868.html#ga923d5186da2eecf410950262961e03c5", null ], + [ "MCUX_CSSL_DI_INIT_IMPL", "a00868.html#gadc0c4c5c446999ac332e799edbe04249", null ], + [ "MCUX_CSSL_DI_CHECK_IMPL", "a00868.html#gac19903f4bcc14df44ce3779e82eeec8b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00869.html b/components/els_pkc/doc/mcxn/html/a00869.html new file mode 100644 index 000000000..3979f34ea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00869.html @@ -0,0 +1,212 @@ + + + + + + + +MCUX CLNS: Data integrity record + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data integrity record
MCUX CSSL &ndash; Implementations » Data Integrity: Disabled
+
+
+ +

Support for recording a value in the data integrity register, when data integrity is disabled. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_DI_RECORD_IMPL(identifier, value)
 Implementation: Record the value for data integrity checking. More...
 
#define MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value)
 Implementation: Expunge the record for value. More...
 
+

Detailed Description

+

Support for recording a value in the data integrity register, when data integrity is disabled.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_DI_RECORD_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_DI_RECORD_IMPL( identifier,
 value 
)
+
+ +

Implementation: Record the value for data integrity checking.

+
Parameters
+ + + +
identifierIdentifier for the value that will be recorded.
valueValue which needs to be recorded for the given identifier.
+
+
+ +
+
+ +

◆ MCUX_CSSL_DI_EXPUNGE_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_DI_EXPUNGE_IMPL( identifier,
 value 
)
+
+ +

Implementation: Expunge the record for value.

+
Parameters
+ + + +
identifierIdentifier for the value that will be expunged.
valueExpected value that was recorded for the given identifier.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00869.js b/components/els_pkc/doc/mcxn/html/a00869.js new file mode 100644 index 000000000..f938250ac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00869.js @@ -0,0 +1,5 @@ +var a00869 = +[ + [ "MCUX_CSSL_DI_RECORD_IMPL", "a00869.html#ga528d28a827727ba460795460a30cccfd", null ], + [ "MCUX_CSSL_DI_EXPUNGE_IMPL", "a00869.html#gaac8a8ea1888347d41f58f27f11c9caab", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00870.html b/components/els_pkc/doc/mcxn/html/a00870.html new file mode 100644 index 000000000..9b83d6b97 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00870.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: Flow Protection API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Flow Protection API
MCUX CSSL &ndash; API
+
+
+ +

Flow protection mechanism. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Modules

 Flow protection core functionality
 Flow protection handling core functionality.
 
 Function calling flow protection
 Support for flow protected functions.
 
 Looping flow protection
 Support for flow protected loops.
 
 Branching flow protection
 Support for flow protected branches.
 
 Switching flow protection
 Support for flow protected switches.
 
 Expectation handling
 Expectation handling support functionality.
 
+

Detailed Description

+

Flow protection mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00870.js b/components/els_pkc/doc/mcxn/html/a00870.js new file mode 100644 index 000000000..e86aef678 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00870.js @@ -0,0 +1,9 @@ +var a00870 = +[ + [ "Flow protection core functionality", "a00871.html", null ], + [ "Function calling flow protection", "a00872.html", "a00872" ], + [ "Looping flow protection", "a00873.html", "a00873" ], + [ "Branching flow protection", "a00874.html", "a00874" ], + [ "Switching flow protection", "a00875.html", "a00875" ], + [ "Expectation handling", "a00876.html", "a00876" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00871.html b/components/els_pkc/doc/mcxn/html/a00871.html new file mode 100644 index 000000000..dbd03f0d1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00871.html @@ -0,0 +1,127 @@ + + + + + + + +MCUX CLNS: Flow protection core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Flow protection core functionality
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Flow protection handling core functionality. +More...

+

Flow protection handling core functionality.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00872.html b/components/els_pkc/doc/mcxn/html/a00872.html new file mode 100644 index 000000000..6e8f0f544 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00872.html @@ -0,0 +1,911 @@ + + + + + + + +MCUX CLNS: Function calling flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Function calling flow protection
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Support for flow protected functions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType)
 Based on a given base type, builds a return type with flow protection. More...
 
#define MCUX_CSSL_FP_COUNTER_STMT(statement)
 A statement which is only evaluated if a secure counter is used. More...
 
#define MCUX_CSSL_FP_FUNCTION_DECL(...)
 Declaration of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_DEF(...)
 Definition of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_POINTER(type, definition)
 Definition of a flow protected function pointer. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY(...)
 Flow protection handler for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT(...)
 Flow protection handler for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(...)
 Flow protection handler for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID(...)
 Flow protection handler for the exit point of functions with the return type void. More...
 
#define MCUX_CSSL_FP_RESULT(return)
 Extract the result value from a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN(return)
 Extract the protection token value from a protected return value. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL(...)
 Call a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID(...)
 Call a flow protected void function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(...)
 Call a flow protected function from unprotected code. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED(...)
 Call a flow protected void function from unprotected code. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...)
 Call a flow protected function and check the protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_END(...)
 End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...)
 Call a flow protected void function and check the protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...)
 End a void function call section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALLED(...)
 Expectation of a called function. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTERED(id)
 Expectation implementation of an entered (but not exited) function. More...
 
+

Detailed Description

+

Support for flow protected functions.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_PROTECTED_TYPE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_PROTECTED_TYPE( resultType)
+
+ +

Based on a given base type, builds a return type with flow protection.

+

This macro must be used to wrap the function return type. For example:

MCUX_CSSL_FP_FUNCTION_DECL(someFunction)
MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) someFunction(void);

Note that depending on the selected flow protection mechanism, the width of the result type may be limited to 32 bits or less to allow encoding a protection token in the other half of a 64-bit return value.

+
See also
MCUX_CSSL_FP_FUNCTION_DEF
+
Parameters
+ + +
resultTypeThe type to be converted into a protected type.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_COUNTER_STMT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_COUNTER_STMT( statement)
+
+ +

A statement which is only evaluated if a secure counter is used.

+

This macro can be used to create counting variables that are only present if the active configuration uses a secure counter, to avoid warnings about unused variables.

+
Parameters
+ + +
statementThe statement to be conditionally included.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_DECL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_DECL( ...)
+
+ +

Declaration of a flow protected function.

+

This declaration must be placed just in front of the actual function declaration. For example:

MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here
uint32_t someFunction(void);
Event
MCUX_CSSL_FP_FUNCTION_CALL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED
+
See also
MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_POINTER
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
Parameters
+ + + +
idIdentifier for the function that is flow protected.
ptrTypeOptional, pointer type matching this function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_DEF

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_DEF( ...)
+
+ +

Definition of a flow protected function.

+

This definition macro must be placed just in front of the actual function definition, that has been previously declared as flow protected using MCUX_CSSL_FP_FUNCTION_DECL. For example:

// someHeader.h
MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here
uint32_t someFunction(void);
// someFile.c
MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
// some function body
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_POINTER
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
Parameters
+ + + +
idIdentifier for the function that is flow protected.
ptrTypeOptional, pointer type matching this function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_POINTER

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_POINTER( type,
 definition 
)
+
+ +

Definition of a flow protected function pointer.

+

This definition macro must be placed around a function pointer definition. For example:

// someHeader.h
MCUX_CSSL_FP_FUNCTION_POINTER(ptrType,
typedef void (*ptrType)(void));
MCUX_CSSL_FP_FUNCTION_DECL(someFunction, ptrType) // Note: no semicolon here
uint32_t someFunction(void);
// someFile.c
MCUX_CSSL_FP_FUNCTION_DEF(someFunction, ptrType) // Note: no semicolon here
uint32_t someFunction(void)
{
// some function body
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
Parameters
+ + + +
typeIdentifier for the function pointer type that is flow protected.
definitionActual type definition of the function pointer type.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTRY

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTRY( ...)
+
+ +

Flow protection handler for the function entry point.

+

This entry macro should be placed at the start of the function body that needs to be protected. The function must have been declared before as flow protected using MCUX_CSSL_FP_FUNCTION_DECL. For example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// remainder of the function body
}

The only statements that should be placed before this one, are declarations for flow protected operations that are already used as expectations in this macro. For example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(uint32_t count)
{
MCUX_CSSL_FP_LOOP_DECL(someLoop);
MCUX_CSSL_FP_LOOP_DECL(otherLoop);
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction,
MCUX_CSSL_FP_LOOP_ITERATIONS(someLoop, count),
MCUX_CSSL_FP_LOOP_ITERATIONS(otherLoop, 2u * count)
);
// Remainder of the function body, where someLoop makes count iterations,
// and otherLoop 2*count iterations.
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the function that has just been entered.
    +
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT( ...)
+
+ +

Flow protection handler for the function exit point.

+

This exit macro must replace the regular return statements of a protected function. Given the following unprotected example:

uint32_t someFunction(void)
{
// some function body
return 0;
}

The protected version would become:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// remainder of the function body
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0);
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the function from which we will exit.
    • +
  • result: Result that should be encoded in the return value.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+
Returns
A value in which both result and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK( ...)
+
+ +

Flow protection handler for the function exit point which includes an actual check of the code flow.

+

This exit macro must replace the regular return statements of a protected function. In addition to MCUX_CSSL_FP_FUNCTION_EXIT it also checks the flow protection, and selects the return value accordingly. For example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// remainder of the function body
MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(someFunction, 0, 0xFAu);
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the function from which we will exit.
    • +
  • pass: Result that should be encoded in the return value if the flow protection check passed.
    • +
  • fail: Result that should be encoded in the return value if the flow protection check failed.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+
Returns
A value in which both the result (either pass or fail) and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_VOID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID( ...)
+
+ +

Flow protection handler for the exit point of functions with the return type void.

+

This exit macro must replace the regular return statements of a protected void function. Given the following unprotected example:

void someFunction(void)
{
// some function body
return 0;
}

The protected version would become:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
void someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// remainder of the function body
MCUX_CSSL_FP_FUNCTION_EXIT_VOID(someFunction);
}
See also
MCUX_CSSL_FP_FUNCTION_DECL
+
+MCUX_CSSL_FP_FUNCTION_DEF
+
+MCUX_CSSL_FP_FUNCTION_ENTRY
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the function from which we will exit.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+
Returns
A protected return value of type void.
+ +
+
+ +

◆ MCUX_CSSL_FP_RESULT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_RESULT( return)
+
+ +

Extract the result value from a protected return value.

+
Parameters
+ + +
returnThe protected return value which contains the result.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTION_TOKEN

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_PROTECTION_TOKEN( return)
+
+ +

Extract the protection token value from a protected return value.

+

Note that this macro is only used with a local security counter, e.g. for configuration CSSL_SC_USE_SW_LOCAL

+
Parameters
+ + +
returnThe protected return value which contains the protection token.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL( ...)
+
+ +

Call a flow protected function.

+

This function call macro encapsulates the flow protection handling needed for calling a function. In particular it takes care of extracting the flow protection token from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and incorporating that in the flow protection of the current function. For example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// ...
MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
);
}

For functions returning void, the macro MCUX_CSSL_FP_FUNCTION_CALL_VOID exists.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • result: Fresh variable name to store the result of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID( ...)
+
+ +

Call a flow protected void function.

+

This function call macro encapsulates the flow protection handling needed for calling a void function. In particular it takes care of extracting the flow protection token from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and incorporating that in the flow protection of the current function. For example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// ...
MCUX_CSSL_FP_FUNCTION_CALL_VOID(otherFunction());
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
);
}
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • call: The (protected) void function call that must be performed.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED( ...)
+
+ +

Call a flow protected function from unprotected code.

+

This function call macro encapsulates the flow protection handling needed for calling a function from within a function which does not have local flow protection, or which uses a different flow protection mechanism than the one provided by CSSL. In particular it takes care of extracting the protection token and result from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). For example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(
result,
token,
otherFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
// ... The following code may use result as a variable ...
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • result: Fresh variable name to store the result of call.
    • +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED( ...)
+
+ +

Call a flow protected void function from unprotected code.

+

This function call macro encapsulates the flow protection handling needed for calling a void function from within a function which does not have flow protection, or which uses a different flow protection mechanism than the one provided by CSSL. In particular it takes care of extracting the protection token and result from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). For example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(
token,
protectedVoidFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
// ...
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_BEGIN

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( ...)
+
+ +

Call a flow protected function and check the protection token.

+

This function call macro encapsulates the flow protection handling needed for calling a function from within a function which does not have local flow protection, or which uses a different flow protection mechanism than the one provided by CSSL. In particular it takes care of extracting the protection token and result from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). For example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(
result,
token,
otherFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
// ... The following code may use result as a variable ...
MCUX_CSSL_FP_FUNCTION_CALL_END();
// ... result is invalid here ...
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • result: Fresh variable name to store the result of call.
    • +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Common_Get_Info_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Rng_Prng_Get_Random_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, mcuxClKey_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_END

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_END( ...)
+
+ +

End a function call section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN.

+

Example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(
result,
token,
otherFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
// ... The following code may use result as a variable ...
MCUX_CSSL_FP_FUNCTION_CALL_END();
// ... result is invalid here ...
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • result: Fresh variable name to store the result of call.
    • +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Common_Get_Info_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Rng_Prng_Get_Random_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, mcuxClKey_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN( ...)
+
+ +

Call a flow protected void function and check the protection token.

+

This function call macro encapsulates the flow protection handling needed for calling a void function from within a function which does not have local flow protection, or which uses a different flow protection mechanism than the one provided by CSSL. In particular it takes care of extracting the protection token from the return value (which has been inserted by MCUX_CSSL_FP_FUNCTION_EXIT or MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). For example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(
token,
otherFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_END

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END( ...)
+
+ +

End a void function call section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN.

+

Example:

uint32_t someUnprotectedFunction(void)
{
// ...
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(
token,
otherFunction());
// Check the protection token
if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token)
{
return FAULT;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
}
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • token: Fresh variable name to store the protection token of call.
    • +
  • call: The (protected) function call that must be performed.
    • +
+
+
+
+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALLED

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALLED( ...)
+
+ +

Expectation of a called function.

+

This expectation macro indicates to the flow protection mechanism that a function call is expected to happen (if placed before the actual call), for example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction,
MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
);
// ...
MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0);
}

Or that a function call has happened (if placed after the actual call), for example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// ...
MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction());
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction)
);
}
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated): -id: Identifier of the function that is expected to be called.
+
+
+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c, mcuxClEls_Common_Get_Info_example.c, mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, mcuxClEls_Hash_Sha512_One_Block_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Rng_Prng_Get_Random_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, mcuxClKey_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTERED

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTERED( id)
+
+ +

Expectation implementation of an entered (but not exited) function.

+

This expectation macro indicates to the flow protection mechanism that a function entry has happened, for example:

MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here
uint32_t someFunction(void)
{
MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction);
// ...
MCUX_CSSL_FP_ASSERT(MCUX_CSSL_FP_FUNCTION_ENTERED(someFunction);
// ...
}
Declaration
MCUX_CSSL_FP_FUNCTION_DECL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
+MCUX_CSSL_FP_FUNCTION_CALLED
+
+MCUX_CSSL_FP_ASSERT
+
Parameters
+ + +
idIdentifier of the function that is expected to be entered.
+
+
+
Returns
Counter value for the given function.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00872.js b/components/els_pkc/doc/mcxn/html/a00872.js new file mode 100644 index 000000000..486de0f5f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00872.js @@ -0,0 +1,24 @@ +var a00872 = +[ + [ "MCUX_CSSL_FP_PROTECTED_TYPE", "a00872.html#ga6cb5dab960bed02a02ad907bd2a54a4b", null ], + [ "MCUX_CSSL_FP_COUNTER_STMT", "a00872.html#gacb5d4268cc93c95b8e69da19d74de79f", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL", "a00872.html#ga21e1a3f12fd2772ca92216b888b3bdff", null ], + [ "MCUX_CSSL_FP_FUNCTION_DEF", "a00872.html#ga7c1d29e4d644c86f11e337e30dd2b210", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00872.html#gab9bdb43ee02202c53d729847dea78ccc", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY", "a00872.html#ga2fda8e2a0e7d862b113b28bcc1b4d9bb", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT", "a00872.html#ga9d9934b6d02da9505dd20ac36236b61d", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK", "a00872.html#ga7c4b79e79eecb68ef4e4fb4fb9fbc1b8", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID", "a00872.html#ga4c6863806f0054719824891271a5f598", null ], + [ "MCUX_CSSL_FP_RESULT", "a00872.html#ga3919086f41a5a26003dd28b528aa473f", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN", "a00872.html#ga8d5c6d7d0c0aba35d4a841e964d5d607", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL", "a00872.html#ga9517fd35bea64a62f1cd3bf58a6218ef", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID", "a00872.html#ga8d8dfc8f87971ee861d0bc77118a97cb", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED", "a00872.html#gac861d63fbf4a985b570845c02c5e412f", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED", "a00872.html#ga5544a5ce0e2478832eb1eacf339b4475", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_BEGIN", "a00872.html#ga8a9b1ebbc02c8195618a339aa8e0003d", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_END", "a00872.html#gac4362de43d0e67ba6fac0057eb38008d", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN", "a00872.html#ga268f9c22cb59586556e0cbb21ac3320e", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_END", "a00872.html#ga30de6960e0ce17187bce680980617f38", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALLED", "a00872.html#gac16ad6597579a02a30ada37f86f216d5", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTERED", "a00872.html#ga9f7aa860f353079a6da5188bd18b977c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00873.html b/components/els_pkc/doc/mcxn/html/a00873.html new file mode 100644 index 000000000..0cb57e3ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00873.html @@ -0,0 +1,250 @@ + + + + + + + +MCUX CLNS: Looping flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Looping flow protection
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Support for flow protected loops. +More...

+ + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_LOOP_DECL(id)
 Declaration of a flow protected loop. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION(...)
 Perform a loop iteration. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATIONS(id, count)
 Expected number of loop iterations. More...
 
+

Detailed Description

+

Support for flow protected loops.

+
Declaration
MCUX_CSSL_FP_LOOP_DECL
+
Event
MCUX_CSSL_FP_LOOP_ITERATION
+
Expectation
MCUX_CSSL_FP_LOOP_ITERATIONS
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_LOOP_DECL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_DECL( id)
+
+ +

Declaration of a flow protected loop.

+

To inform the flow protection mechanism about a loop that needs to be protected, a loop identifier needs to be declared. This identifier can then be used in the event and expectation macros. For example:

MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
for (uint32_t i = 0; i < 8; ++i)
{
MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8)
);
Event
MCUX_CSSL_FP_LOOP_ITERATION
+
Expectation
MCUX_CSSL_FP_LOOP_ITERATIONS
+
Parameters
+ + +
idIdentifier for the loop that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATION

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATION( ...)
+
+ +

Perform a loop iteration.

+

This loop iteration macro informs the flow mechanism that an iteration event is performed for the loop declared by MCUX_CSSL_FP_LOOP_DECL with the given id. For example:

MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
for (uint32_t i = 0; i < 8; ++i)
{
MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
}
Declaration
MCUX_CSSL_FP_LOOP_DECL
+
Expectation
MCUX_CSSL_FP_LOOP_ITERATIONS
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier for the loop that is flow protected.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior related to this event.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATIONS

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATIONS( id,
 count 
)
+
+ +

Expected number of loop iterations.

+

This expectation macro indicates to the flow protection mechanism that the loop declared by MCUX_CSSL_FP_LOOP_DECL with the given id has made count iterations. For example:

MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier);
for (uint32_t i = 0; i < 8; ++i)
{
MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8)
);
Declaration
MCUX_CSSL_FP_LOOP_DECL
+
Event
MCUX_CSSL_FP_LOOP_ITERATION
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
Parameters
+ + + +
idIdentifier of the flow protected loop.
countNumber of expected iterations.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00873.js b/components/els_pkc/doc/mcxn/html/a00873.js new file mode 100644 index 000000000..4ca88e986 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00873.js @@ -0,0 +1,6 @@ +var a00873 = +[ + [ "MCUX_CSSL_FP_LOOP_DECL", "a00873.html#ga96df84766aff763718a84dd44246af38", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION", "a00873.html#gae7942657c4fac73115908f05c382cc86", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATIONS", "a00873.html#gae5aabc3339a46a799d1fefd1095a4898", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00874.html b/components/els_pkc/doc/mcxn/html/a00874.html new file mode 100644 index 000000000..341ebc3c7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00874.html @@ -0,0 +1,328 @@ + + + + + + + +MCUX CLNS: Branching flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Branching flow protection
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Support for flow protected branches. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_BRANCH_DECL(id)
 Declaration of a flow protected branch. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE(...)
 Positive scenario for a branch is executed. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE(...)
 Negative scenario of a branch is executed. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(...)
 Expectation that positive branch has been taken. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(...)
 Expectation that negative branch has been taken. More...
 
+

Detailed Description

+

Support for flow protected branches.

+
Declaration
MCUX_CSSL_FP_BRANCH_DECL
+
Events
MCUX_CSSL_FP_BRANCH_POSITIVE
+MCUX_CSSL_FP_BRANCH_NEGATIVE
+
Expectations
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_BRANCH_DECL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_DECL( id)
+
+ +

Declaration of a flow protected branch.

+

To inform the flow protection mechanism about a branch that needs to be protected, a branch identifier needs to be declared. This identifier can then be used in the events and expectation macros. For example:

MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
if (condition)
{
MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
}
else
{
MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_BRANCH_TAKEN(someBranchIdentifier,
MCUX_CSSL_FP_BRANCH_POSITIVE_SCENARIO, condition)
);
Events
MCUX_CSSL_FP_BRANCH_POSITIVE
+MCUX_CSSL_FP_BRANCH_NEGATIVE
+
Expectations
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+
Parameters
+ + +
idIdentifier for the branch that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_POSITIVE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_POSITIVE( ...)
+
+ +

Positive scenario for a branch is executed.

+

This branch event macro informs the flow mechanism that the positive scenario of the branch is executed for the branch declared by MCUX_CSSL_FP_BRANCH_DECL with the given id. For example:

MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
if (condition)
{
MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
}
else
{
MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition,
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_BRANCH_DECL
+
Expectation
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier for the branch for which the positive scenario is executed.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior related to this event.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_NEGATIVE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_NEGATIVE( ...)
+
+ +

Negative scenario of a branch is executed.

+

This branch event macro informs the flow mechanism that the positive scenario of the branch is executed for the branch declared by MCUX_CSSL_FP_BRANCH_DECL with the given id. For example:

MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
if (condition)
{
MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
}
else
{
MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition,
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_BRANCH_DECL
+
Expectation
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier for the branch for which the negative scenario is executed.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior related to this event.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE( ...)
+
+ +

Expectation that positive branch has been taken.

+

This expectation macro indicates to the flow protection mechanism that the branch declared by MCUX_CSSL_FP_BRANCH_DECL with the given id has executed the positive scenario (under the given condition). For example:

MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
if (condition)
{
MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
}
else
{
MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
// Providing the condition as part of the branch expectation.
// Alternatively, the expectation can be placed in a conditional block.
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier, condition)
);
Declaration
MCUX_CSSL_FP_BRANCH_DECL
+
Event
MCUX_CSSL_FP_BRANCH_POSITIVE
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
+MCUX_CSSL_FP_CONDITIONAL
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected branch.
    • +
  • condition: Optional, condition under which this branch is taken.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE( ...)
+
+ +

Expectation that negative branch has been taken.

+

This expectation macro indicates to the flow protection mechanism that the branch declared by MCUX_CSSL_FP_BRANCH_DECL with the given id has executed the negative scenario (under the given condition). For example:

MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier);
if (condition)
{
MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier);
}
else
{
MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier);
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0,
// Providing the branch expectation as part of a conditional block.
// Alternatively, the condition can be provided in the branch expectation.
MCUX_CSSL_FP_CONDITIONAL(!condition,
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_BRANCH_DECL
+
Event
MCUX_CSSL_FP_BRANCH_NEGATIVE
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
+MCUX_CSSL_FP_CONDITIONAL
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected branch.
    • +
  • condition: Optional, condition under which this branch is taken.
    • +
+
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00874.js b/components/els_pkc/doc/mcxn/html/a00874.js new file mode 100644 index 000000000..b2a6430ba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00874.js @@ -0,0 +1,8 @@ +var a00874 = +[ + [ "MCUX_CSSL_FP_BRANCH_DECL", "a00874.html#ga1406430491edf42797f1fbb6fec6d400", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE", "a00874.html#ga9aaebd3ae72dfb08a7a286c9cf02898c", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE", "a00874.html#ga67a87d7f006f7f4fc09f1a0b93d21043", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE", "a00874.html#ga99db0902665c118dbfeacd73dd8c8672", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE", "a00874.html#ga7ca1b74234f560a110647fbc24fec3f9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00875.html b/components/els_pkc/doc/mcxn/html/a00875.html new file mode 100644 index 000000000..0c8aba19b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00875.html @@ -0,0 +1,326 @@ + + + + + + + +MCUX CLNS: Switching flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Switching flow protection
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Support for flow protected switches. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_SWITCH_DECL(id)
 Declaration of a flow protected switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN(...)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(...)
 Expected that default case is handled from a switch. More...
 
+

Detailed Description

+

Support for flow protected switches.

+
Declaration
MCUX_CSSL_FP_SWITCH_DECL
+
Events
MCUX_CSSL_FP_SWITCH_CASE
+MCUX_CSSL_FP_SWITCH_DEFAULT
+
Expectations
MCUX_CSSL_FP_SWITCH_TAKEN
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_SWITCH_DECL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DECL( id)
+
+ +

Declaration of a flow protected switch.

+

To inform the flow protection mechanism about a switch that needs to be protected, a switch identifier needs to be declared. This identifier can then be used in the events and expectation macros. For example:

MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
switch (arg)
{
case 0xC0DEu:
{
result = 0xC0DEu;
MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
break;
}
default:
{
result = 0;
MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
break;
}
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
// Option 1: provide the condition as part of the switch expectation.
MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg),
// Option 2: place the switch expectation in a conditional block.
MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
)
);
Events
MCUX_CSSL_FP_SWITCH_CASE
+MCUX_CSSL_FP_SWITCH_DEFAULT
+
Expectations
MCUX_CSSL_FP_SWITCH_TAKEN
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT
+
Parameters
+ + +
idIdentifier for the switch that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_CASE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_CASE( ...)
+
+ +

Case that is being handled from a switch.

+

This switch event macro informs the flow mechanism that the given case of the switch is executed for the switch declared by MCUX_CSSL_FP_SWITCH_DECL with the given id. For example:

MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
switch (arg)
{
case 0xC0DEu:
{
result = 0xC0DEu;
MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
break;
}
default:
{
result = 0;
MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
break;
}
}
// ...
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
// Option 1: provide the condition as part of the switch expectation.
MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg),
// Option 2: place the switch expectation in a conditional block.
MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_SWITCH_DECL
+
Expectation
MCUX_CSSL_FP_SWITCH_TAKEN
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected switch.
    • +
  • case: Case value that is chosen in the switch.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior related to this event.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DEFAULT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DEFAULT( ...)
+
+ +

Case that is being handled from a switch.

+

This switch event macro informs the flow mechanism that the default case of the switch is executed for the switch declared by MCUX_CSSL_FP_SWITCH_DECL with the given id. For example:

MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
switch (arg)
{
case 0xC0DEu:
{
result = 0xC0DEu;
MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
break;
}
default:
{
result = 0;
MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
break;
}
}
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
// Option 1: provide the condition as part of the switch expectation.
MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
// Option 2: place the switch expectation in a conditional block.
MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_SWITCH_DECL
+
Expectation
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected switch.
    • +
  • expect: Zero or more (comma separated) declarations of expected code flow behavior related to this event.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN( ...)
+
+ +

Expected that a specific case is handled from a switch.

+

This expectation macro indicates to the flow protection mechanism that the switch declared by MCUX_CSSL_FP_SWITCH_DECL with the given id has executed the case (under the given condition). For example:

MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
switch (arg)
{
case 0xC0DEu:
{
result = 0xC0DEu;
MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
break;
}
default:
{
result = 0;
MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
break;
}
}
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
// Option 1: provide the condition as part of the switch expectation.
MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
// Option 2: place the switch expectation in a conditional block.
MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_SWITCH_DECL
+
Event
MCUX_CSSL_FP_SWITCH_CASE
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected switch.
    • +
  • case: Value of the case that is expected to be chosen in the switch.
    • +
  • condition: Optional, condition under which the case is taken.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT( ...)
+
+ +

Expected that default case is handled from a switch.

+

This expectation macro indicates to the flow protection mechanism that the switch declared by MCUX_CSSL_FP_SWITCH_DECL with the given id has executed the default case (under the given condition). For example:

MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier);
switch (arg)
{
case 0xC0DEu:
{
result = 0xC0DEu;
MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu);
break;
}
default:
{
result = 0;
MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier);
break;
}
}
MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result,
// Option 1: provide the condition as part of the switch expectation.
MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg),
// Option 2: place the switch expectation in a conditional block.
MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg),
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier)
)
);
Declaration
MCUX_CSSL_FP_SWITCH_DECL
+
Event
MCUX_CSSL_FP_SWITCH_DEFAULT
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • id: Identifier of the flow protected switch.
    • +
  • condition: Optional, condition under which the default case is taken.
    • +
+
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00875.js b/components/els_pkc/doc/mcxn/html/a00875.js new file mode 100644 index 000000000..000cd3bee --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00875.js @@ -0,0 +1,8 @@ +var a00875 = +[ + [ "MCUX_CSSL_FP_SWITCH_DECL", "a00875.html#gafc01be288246642c1b2779b69188adad", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE", "a00875.html#gab3a2723c9a344c245ff6b596aaee5414", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT", "a00875.html#gaebd999394afa94e2c3e3b64f68d85e2a", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN", "a00875.html#gaa620180722a4eaa8e7370a92d2bd18d9", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT", "a00875.html#gac011e972fff0f38d704edfeadce256cd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00876.html b/components/els_pkc/doc/mcxn/html/a00876.html new file mode 100644 index 000000000..4fa6d29fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00876.html @@ -0,0 +1,267 @@ + + + + + + + +MCUX CLNS: Expectation handling + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Expectation handling
MCUX CSSL &ndash; API » Flow Protection API
+
+
+ +

Expectation handling support functionality. +More...

+ + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_EXPECT(...)
 Declaration(s) of expected code flow behavior. More...
 
#define MCUX_CSSL_FP_CONDITIONAL(condition, ...)
 Handling of conditionally expected code flow behavior. More...
 
#define MCUX_CSSL_FP_ASSERT(...)
 Assert an expected state of the code flow. More...
 
+

Detailed Description

+

Expectation handling support functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_EXPECT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_EXPECT( ...)
+
+ +

Declaration(s) of expected code flow behavior.

+

This macro can be used to indicate expectations in the function body at another location than the function entry or exit.

+
Note
In general the use of this macro is discouraged, to avoid a potential security and/or code-size impact. However, it may be usefull for complex code, where an intermediate update can actually save code, since conditions for expectations can than be locallized.
+
Expectations
MCUX_CSSL_FP_FUNCTION_CALLED
+MCUX_CSSL_FP_LOOP_ITERATIONS
+MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+MCUX_CSSL_FP_SWITCH_TAKEN
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_CONDITIONAL
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • expect: One or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_CONDITIONAL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_CONDITIONAL( condition,
 ... 
)
+
+ +

Handling of conditionally expected code flow behavior.

+

This macro can be used to indicate expectations that are only true under a given condition.

+
Expectations
MCUX_CSSL_FP_FUNCTION_CALLED
+MCUX_CSSL_FP_LOOP_ITERATIONS
+MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE
+MCUX_CSSL_FP_SWITCH_TAKEN
+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY
+
+MCUX_CSSL_FP_FUNCTION_EXIT
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK
+
+MCUX_CSSL_FP_EXPECT
+
Parameters
+ + + +
conditionCondition under which the given expectations apply.
...One or more (comma separated) declarations of expected code flow behavior.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_ASSERT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_ASSERT( ...)
+
+ +

Assert an expected state of the code flow.

+

This macro can be used to check whether the code flow up to this point matches the expected state. Unlike the MCUX_CSSL_FP_EXPECT macro, it will not update the expectations, but merely perform a check on the recorded events against the already recorded expectations plus the ones provided as parameters.

+

If the check fails, the code defined in MCUX_CSSL_FP_ASSERT_CALLBACK() will be executed.

+
Note
MCUX_CSSL_FP_ASSERT_CALLBACK() must be defined before including the CSSL flow protection headers, otherwise a default implementation could be used.
+
See also
MCUX_CSSL_FP_EXPECT
+
Parameters
+ + +
...The following parameters need to be passed (comma separated):
    +
  • expect: One or more (comma separated) declarations of expected code flow behavior.
    • +
+
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00876.js b/components/els_pkc/doc/mcxn/html/a00876.js new file mode 100644 index 000000000..fbda534a4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00876.js @@ -0,0 +1,6 @@ +var a00876 = +[ + [ "MCUX_CSSL_FP_EXPECT", "a00876.html#ga83db474d65df2b52abea45293f9684d0", null ], + [ "MCUX_CSSL_FP_CONDITIONAL", "a00876.html#ga24a55fecde25d3aa0a227814345b9714", null ], + [ "MCUX_CSSL_FP_ASSERT", "a00876.html#ga301b8f23ac6981e62649c8f571a6c6eb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00877.html b/components/els_pkc/doc/mcxn/html/a00877.html new file mode 100644 index 000000000..de9d80342 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00877.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: Flow Protection Configuration + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Flow Protection Configuration
MCUX CSSL &ndash; Configurations
+
+
+ +

Configuration options for the flow protection mechanism. +More...

+ + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_USE_CODE_SIGNATURE
 If set to 1, use the flow protection mechanism implementation based on the Zen-V code signature HW mechanism. More...
 
#define MCUX_CSSL_FP_USE_SECURE_COUNTER
 If set to 1, use the flow protection mechanism implementation based on the CSSL secure counter mechanism. More...
 
#define MCUX_CSSL_FP_USE_NONE
 If set to 1, do not use the flow protection mechanism. More...
 
+

Detailed Description

+

Configuration options for the flow protection mechanism.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_USE_CODE_SIGNATURE

+ +
+
+ + + + +
#define MCUX_CSSL_FP_USE_CODE_SIGNATURE
+
+ +

If set to 1, use the flow protection mechanism implementation based on the Zen-V code signature HW mechanism.

+ +
+
+ +

◆ MCUX_CSSL_FP_USE_SECURE_COUNTER

+ +
+
+ + + + +
#define MCUX_CSSL_FP_USE_SECURE_COUNTER
+
+ +

If set to 1, use the flow protection mechanism implementation based on the CSSL secure counter mechanism.

+ +
+
+ +

◆ MCUX_CSSL_FP_USE_NONE

+ +
+
+ + + + +
#define MCUX_CSSL_FP_USE_NONE
+
+ +

If set to 1, do not use the flow protection mechanism.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00877.js b/components/els_pkc/doc/mcxn/html/a00877.js new file mode 100644 index 000000000..6d8d3b820 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00877.js @@ -0,0 +1,6 @@ +var a00877 = +[ + [ "MCUX_CSSL_FP_USE_CODE_SIGNATURE", "a00877.html#gaeaecd08382d1bf7542d523e67c15b90b", null ], + [ "MCUX_CSSL_FP_USE_SECURE_COUNTER", "a00877.html#ga645fafaa87e927ec807c9679dfa6d74e", null ], + [ "MCUX_CSSL_FP_USE_NONE", "a00877.html#ga8fcbc78b6821d4cd6ea67bdc3d4e3ba7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00878.html b/components/els_pkc/doc/mcxn/html/a00878.html new file mode 100644 index 000000000..25fb9a6de --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00878.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: Flow Protection: Secure Counter + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Flow Protection: Secure Counter
MCUX CSSL &ndash; Implementations
+
+
+ +

Secure counter based implementation for the flow protection mechanism. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Modules

 Flow protection core functionality
 Flow protection handling core functionality.
 
 Expectation handling
 Expectation handling support functionality.
 
 Function calling flow protection
 Support for flow protected functions.
 
 Looping flow protection
 Support for flow protected loops.
 
 Branching flow protection
 Support for flow protected branches.
 
 Switching flow protection
 Support for flow protected switches.
 
+

Detailed Description

+

Secure counter based implementation for the flow protection mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00878.js b/components/els_pkc/doc/mcxn/html/a00878.js new file mode 100644 index 000000000..704749e33 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00878.js @@ -0,0 +1,9 @@ +var a00878 = +[ + [ "Flow protection core functionality", "a00879.html", "a00879" ], + [ "Expectation handling", "a00880.html", "a00880" ], + [ "Function calling flow protection", "a00881.html", "a00881" ], + [ "Looping flow protection", "a00882.html", "a00882" ], + [ "Branching flow protection", "a00883.html", "a00883" ], + [ "Switching flow protection", "a00884.html", "a00884" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00879.html b/components/els_pkc/doc/mcxn/html/a00879.html new file mode 100644 index 000000000..a99906e5d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00879.html @@ -0,0 +1,281 @@ + + + + + + + +MCUX CLNS: Flow protection core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Flow protection core functionality
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Flow protection handling core functionality. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_DECL_NAME(type, id)
 Construct a name based on type and id. More...
 
#define MCUX_CSSL_FP_DECL_IMPL(type, id)
 Generic flow protected entity declaration implementation. More...
 
#define MCUX_CSSL_FP_ID_IMPL()
 Generic identifier generator based on current line number. More...
 
#define MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, ...)
 Conditional expectation aggregation. More...
 
+

Detailed Description

+

Flow protection handling core functionality.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_DECL_NAME

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_DECL_NAME( type,
 id 
)
+
+ +

Construct a name based on type and id.

+
Parameters
+ + + +
typeIndicator for the type of declaration.
idIdentifier for the flow protected entity.
+
+
+
Returns
CSSL flow protection entity name for given type and id.
+ +
+
+ +

◆ MCUX_CSSL_FP_DECL_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_DECL_IMPL( type,
 id 
)
+
+ +

Generic flow protected entity declaration implementation.

+
Parameters
+ + + +
typeIndicator for the type of declaration.
idIdentifier for the flow protected entity.
+
+
+
Returns
CSSL flow protection entity declaration.
+ +
+
+ +

◆ MCUX_CSSL_FP_ID_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_ID_IMPL()
+
+ +

Generic identifier generator based on current line number.

+
Returns
Counter value based on the current line number.
+ +
+
+ +

◆ MCUX_CSSL_FP_CONDITIONAL_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_CONDITIONAL_IMPL( condition,
 ... 
)
+
+ +

Conditional expectation aggregation.

+
Parameters
+ + + +
conditionCondition under which the given expectations apply
expectOne or more (comma separated) declarations of expected code code flow behavior.
+
+
+
Returns
Aggregated counter value for the given expectations, if condition is satisfied. Otherwise 0.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00879.js b/components/els_pkc/doc/mcxn/html/a00879.js new file mode 100644 index 000000000..0d0a6fb1a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00879.js @@ -0,0 +1,7 @@ +var a00879 = +[ + [ "MCUX_CSSL_FP_DECL_NAME", "a00879.html#ga116350fa9fa1a37d3fca3d3a15f010f3", null ], + [ "MCUX_CSSL_FP_DECL_IMPL", "a00879.html#gab0919c85280cbf0aa51daaec18cb524a", null ], + [ "MCUX_CSSL_FP_ID_IMPL", "a00879.html#ga6bc8b7f3f35325ca98c1b5d0f7658061", null ], + [ "MCUX_CSSL_FP_CONDITIONAL_IMPL", "a00879.html#ga643cc00e2fecb3e73de572797618ad35", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00880.html b/components/els_pkc/doc/mcxn/html/a00880.html new file mode 100644 index 000000000..cd977cf56 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00880.html @@ -0,0 +1,273 @@ + + + + + + + +MCUX CLNS: Expectation handling + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Expectation handling
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Expectation handling support functionality. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_EXPECTATIONS(...)
 Expectation aggregation. More...
 
#define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()
 Implementation of expectation of nothingThis expectation macro indicates to the flow protection mechanism that nothing is expected to happen. More...
 
#define MCUX_CSSL_FP_EXPECT_IMPL(...)
 Declaration(s) of expected code flow behavior. More...
 
#define MCUX_CSSL_FP_ASSERT_CALLBACK()
 Fallback assert callback implementation. More...
 
#define MCUX_CSSL_FP_ASSERT_IMPL(...)
 Assert an expected state of the code flow. More...
 
+

Detailed Description

+

Expectation handling support functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_EXPECTATIONS

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_EXPECTATIONS( ...)
+
+ +

Expectation aggregation.

+
Parameters
+ + +
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
Aggregated counter value for the given expectations.
+ +
+
+ +

◆ MCUX_CSSL_FP_VOID_EXPECTATION_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()
+
+ +

Implementation of expectation of nothingThis expectation macro indicates to the flow protection mechanism that nothing is expected to happen.

+

This is mainly intended for internal use (to ensure at least one expectation is passed).

+ +
+
+ +

◆ MCUX_CSSL_FP_EXPECT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_EXPECT_IMPL( ...)
+
+ +

Declaration(s) of expected code flow behavior.

+

This macro can be used to indicate expectations in the function body at another location than the function entry or exit.

+
See also
MCUX_CSSL_FP_EXPECTATIONS
+
Parameters
+ + +
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_ASSERT_CALLBACK

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_ASSERT_CALLBACK()
+
+ +

Fallback assert callback implementation.

+

This macro will be executed if an MCUX_CSSL_FP_ASSERT fails. In general this behavior should be defined by the user. This implementation is only in place to ensure that an implementation is always available.

+

This is implemented a division by 0, which should trigger a compiler warning when used, to inform the user that the default implementation is used. Additionally, when still used at run-time it should trigger some system exception.

+
See also
MCUX_CSSL_FP_ASSERT
+ +
+
+ +

◆ MCUX_CSSL_FP_ASSERT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_ASSERT_IMPL( ...)
+
+ +

Assert an expected state of the code flow.

+

This macro can be used to check whether the code flow up to this point matches the expected state. Unlike the MCUX_CSSL_FP_EXPECT macro, it will not update the expectations, but merely perform a check on the recorded events against the already recorded expectations plus the ones provided as parameters.

+

If the check fails, the code defined in MCUX_CSSL_FP_ASSERT_CALLBACK will be executed.

+
See also
MCUX_CSSL_FP_EXPECTATIONS
+
Parameters
+ + +
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00880.js b/components/els_pkc/doc/mcxn/html/a00880.js new file mode 100644 index 000000000..cdde5136a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00880.js @@ -0,0 +1,8 @@ +var a00880 = +[ + [ "MCUX_CSSL_FP_EXPECTATIONS", "a00880.html#ga173c3887e1d02b5cace9e622d0a3225b", null ], + [ "MCUX_CSSL_FP_VOID_EXPECTATION_IMPL", "a00880.html#ga4ea20ab3d4d080887fdfc12f6c7f6bab", null ], + [ "MCUX_CSSL_FP_EXPECT_IMPL", "a00880.html#ga7be0ed334bcf634f81d5d4b93a4c1657", null ], + [ "MCUX_CSSL_FP_ASSERT_CALLBACK", "a00880.html#ga0c29c395a9104c6d918091b12f63ca74", null ], + [ "MCUX_CSSL_FP_ASSERT_IMPL", "a00880.html#ga391e0f29868a1dd17bd0d23a4737c129", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00881.html b/components/els_pkc/doc/mcxn/html/a00881.html new file mode 100644 index 000000000..3c4fe758e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00881.html @@ -0,0 +1,1386 @@ + + + + + + + +MCUX CLNS: Function calling flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Function calling flow protection
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Support for flow protected functions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_FUNCTION_ID(id)
 Generator for function identifiers. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK
 Mask to be used to derive entry part from a function identifier. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id)
 Part of the function identifier to be used at function entry. More...
 
#define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id)
 Part of the function identifier to be used at function exit. More...
 
#define MCUX_CSSL_FP_FUNCTION_DECL_IMPL(...)
 Declaration implementation of a flow protected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_VALUE(id)
 Macro to get the value for a given function. More...
 
#define MCUX_CSSL_FP_FUNCTION_DEF_IMPL(...)
 Definition implementation of a flow protected function. More...
 
#define MCUX_CSSL_FP_RESULT_OFFSET
 Offset of the result in the return value. More...
 
#define MCUX_CSSL_FP_RESULT_MASK
 Bitmask of the result in the return value. More...
 
#define MCUX_CSSL_FP_RESULT_VALUE(result)
 Encode a result value for a protected return value. More...
 
#define MCUX_CSSL_FP_RESULT_IMPL(return)
 Extract the result value from a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_OFFSET
 Offset of the protection token in the return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_MASK
 Bitmask of the protection token in the return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(token)
 Encode a protection token for a protected return value. More...
 
#define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return)
 Extract the protection token value from a protected return value. More...
 
#define MCUX_CSSL_FP_COUNTER_COMPRESSED()
 Compressed version of the secure counter that can be used as a protection token. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(id)
 Expectation implementation of a called function. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id)
 Expectation implementation of an entered (but not exited) function. More...
 
#define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType)
 Based on a given base type, builds a return type with flow protection. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, ...)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1(function)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(...)
 Flow protection handler implementation for the function entry point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, ...)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1(id)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2(id, result)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(...)
 Flow protection handler implementation for the function exit point. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, ...)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3(id, pass, fail)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(...)
 Flow protection handler implementation for the function exit point which includes an actual check of the code flow. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1(id)
 Flow protection handler for the exit point of functions with the return type void. More...
 
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(...)
 Flow protection handler for the exit point of functions with the return type void. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL(result, call)
 Event implementation of a flow protected function call. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call)
 Implementation of a flow protected function call meant to be used from within an unprotected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call)
 Implementation of a flow protected void function call meant to be used from within an unprotected function. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(result, token, call)
 Implementation of a flow protected function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL()
 Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(token, call)
 Implementation of a flow protected void function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL. More...
 
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL()
 Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL. More...
 
+

Detailed Description

+

Support for flow protected functions.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_FUNCTION_ID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ID( id)
+
+ +

Generator for function identifiers.

+
Parameters
+ + +
idIdentifier for the flow protected function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK

+ +
+
+ + + + +
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK
+
+ +

Mask to be used to derive entry part from a function identifier.

+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART( id)
+
+ +

Part of the function identifier to be used at function entry.

+
Parameters
+ + +
idIdentifier for the flow protected function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART( id)
+
+ +

Part of the function identifier to be used at function exit.

+
Parameters
+ + +
idIdentifier for the flow protected function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_DECL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_DECL_IMPL( ...)
+
+ +

Declaration implementation of a flow protected function.

+
Event
MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+
Parameters
+ + + +
idIdentifier for the function that is flow protected.
ptrTypeOptional, pointer type matching this function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_VALUE( id)
+
+ +

Macro to get the value for a given function.

+
Parameters
+ + +
idIdentifier for the function that is flow protected.
+
+
+
Returns
The counter value for the given function id.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_DEF_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_DEF_IMPL( ...)
+
+ +

Definition implementation of a flow protected function.

+

Not used in the current implementation.

+
Parameters
+ + + +
idIdentifier for the function that is flow protected.
ptrTypeOptional, pointer type matching this function.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_RESULT_OFFSET

+ +
+
+ + + + +
#define MCUX_CSSL_FP_RESULT_OFFSET
+
+ +

Offset of the result in the return value.

+ +
+
+ +

◆ MCUX_CSSL_FP_RESULT_MASK

+ +
+
+ + + + +
#define MCUX_CSSL_FP_RESULT_MASK
+
+ +

Bitmask of the result in the return value.

+ +
+
+ +

◆ MCUX_CSSL_FP_RESULT_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_RESULT_VALUE( result)
+
+ +

Encode a result value for a protected return value.

+
Parameters
+ + +
resultThe result that needs to be encoded.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_RESULT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_RESULT_IMPL( return)
+
+ +

Extract the result value from a protected return value.

+
Parameters
+ + +
returnThe protected return value which contains the result.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTION_OFFSET

+ +
+
+ + + + +
#define MCUX_CSSL_FP_PROTECTION_OFFSET
+
+ +

Offset of the protection token in the return value.

+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTION_MASK

+ +
+
+ + + + +
#define MCUX_CSSL_FP_PROTECTION_MASK
+
+ +

Bitmask of the protection token in the return value.

+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE( token)
+
+ +

Encode a protection token for a protected return value.

+

Note that this macro is only used with a local security counter, e.g. for configuration CSSL_SC_USE_SW_LOCAL

+
Parameters
+ + +
tokenThe protection token that needs to be encoded.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL( return)
+
+ +

Extract the protection token value from a protected return value.

+

Note that this macro is only used with a local security counter, e.g. for configuration CSSL_SC_USE_SW_LOCAL

+
Parameters
+ + +
returnThe protected return value which contains the protection token.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_COUNTER_COMPRESSED

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_COUNTER_COMPRESSED()
+
+ +

Compressed version of the secure counter that can be used as a protection token.

+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALLED_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL( id)
+
+ +

Expectation implementation of a called function.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+
See also
MCUX_CSSL_FP_FUNCTION_VALUE
+
Parameters
+ + +
idIdentifier of the function that is expected to be called.
+
+
+
Returns
Counter value for the given function.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL( id)
+
+ +

Expectation implementation of an entered (but not exited) function.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Event
MCUX_CSSL_FP_FUNCTION_CALL_IMPL
+
See also
MCUX_CSSL_FP_FUNCTION_VALUE
+
Parameters
+ + +
idIdentifier of the function that is expected to be entered.
+
+
+
Returns
Counter value for the given function.
+ +
+
+ +

◆ MCUX_CSSL_FP_PROTECTED_TYPE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL( resultType)
+
+ +

Based on a given base type, builds a return type with flow protection.

+
See also
MCUX_CSSL_FP_FUNCTION_DEF_IMPL
+
Parameters
+ + +
resultTypeThe type to be converted into a protected type.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn( function,
 ... 
)
+
+ +

Flow protection handler implementation for the function entry point.

+

Initialize the counter with the entry part of the function identifier, and include expectations in the initialization value.

+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL
+
Parameters
+ + + +
idIdentifier of the function that has just been entered.
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1( function)
+
+ +

Flow protection handler implementation for the function entry point.

+

Initialize the counter with the entry part of the function identifier, without any potential expectations.

+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL
+
Parameters
+ + +
idIdentifier of the function that has just been entered.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL( ...)
+
+ +

Flow protection handler implementation for the function entry point.

+

Initialize the counter with entry part of the function identifier, and include potential expectations in the initialization value.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1
+
+MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn
+
Parameters
+ + + +
idIdentifier of the function that has just been entered.
expectZero or more (comma separated) declarations of expected code flow behavior.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn( id,
 result,
 ... 
)
+
+ +

Flow protection handler implementation for the function exit point.

+

Adjust the counter with the exit part of the function identifier, and include potential expectations in the adjustment value. Return the counter value together with the result via the function return value.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+
Parameters
+ + + + +
idIdentifier of the function from which we will exit.
resultResult that should be encoded in the return value.
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
A value in which both result and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1( id)
+
+ +

Flow protection handler implementation for the function exit point.

+

Adjust the counter with the exit part of the function identifier, without any potential expectations in the adjustment value. Return the counter value via the function return value.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+
Parameters
+ + +
idIdentifier of the function from which we will exit.
+
+
+
Returns
A value in which a flow protection token is encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2( id,
 result 
)
+
+ +

Flow protection handler implementation for the function exit point.

+

Adjust the counter with the exit part of the function identifier, without any potential expectations in the adjustment value. Return the counter value together with the result via the function return value.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_IMPL
+
Parameters
+ + + +
idIdentifier of the function from which we will exit.
resultResult that should be encoded in the return value.
+
+
+
Returns
A value in which both result and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL( ...)
+
+ +

Flow protection handler implementation for the function exit point.

+

Adjust the counter with the exit part of the function identifier, and include potential expectations in the adjustment value. Return the counter value together with the result via the function return value.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1
+
+MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2
+
+MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn
+
Parameters
+ + + + +
idIdentifier of the function from which we will exit.
resultResult that should be encoded in the return value.
expectZero or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
A value in which both result and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn( id,
 pass,
 fail,
 ... 
)
+
+ +

Flow protection handler implementation for the function exit point which includes an actual check of the code flow.

+

Adjust the counter with the exit part of the function identifier, and include potential expectations in the adjustment value. Check whether the counter matches the expected value, and choose the result from pass and fail and return it together with the counter value via the function return value.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn
+
Parameters
+ + + + + +
idIdentifier of the function from which we will exit.
passResult that should be encoded in the return value if the flow protection check passed.
failResult that should be encoded in the return value if the flow protection check failed.
expectOne or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
A value in which both the result (either pass or fail) and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3( id,
 pass,
 fail 
)
+
+ +

Flow protection handler implementation for the function exit point which includes an actual check of the code flow.

+

Adjust the counter with the exit part of the function identifier. Check whether the counter matches the expected value, and choose the result from pass and fail and return it together with the counter value via the function return value.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL
+
Parameters
+ + + + +
idIdentifier of the function from which we will exit.
passResult that should be encoded in the return value if the flow protection check passed.
failResult that should be encoded in the return value if the flow protection check failed.
+
+
+
Returns
A value in which both the result (either pass or fail) and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL( ...)
+
+ +

Flow protection handler implementation for the function exit point which includes an actual check of the code flow.

+

Adjust the counter with the exit part of the function identifier, and include potential expectations in the adjustment value. Check whether the counter matches the expected value, and choose the result from pass and fail and return it together with the counter value via the function return value.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3
+
+MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn
+
Parameters
+ + + + + +
idIdentifier of the function from which we will exit.
passResult that should be encoded in the return value if the flow protection check passed.
failResult that should be encoded in the return value if the flow protection check failed.
expectZero or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
A value in which both the result (either pass or fail) and a flow protection token are encoded.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1( id)
+
+ +

Flow protection handler for the exit point of functions with the return type void.

+
Parameters
+ + +
idIdentifier of the function from which we will exit.
+
+
+
Returns
A protected return value of type void.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL( ...)
+
+ +

Flow protection handler for the exit point of functions with the return type void.

+
Parameters
+ + + +
idIdentifier of the function from which we will exit.
expectZero or more (comma separated) declarations of expected code flow behavior.
+
+
+
Returns
A protected return value of type void.
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL( result,
 call 
)
+
+ +

Event implementation of a flow protected function call.

+
Declaration
MCUX_CSSL_FP_FUNCTION_DECL_IMPL
+
Expectation
MCUX_CSSL_FP_FUNCTION_CALLED_IMPL
+
Parameters
+ + + +
resultFresh variable name to store the result of call.
callThe (protected) function call that must be performed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL( result,
 token,
 call 
)
+
+ +

Implementation of a flow protected function call meant to be used from within an unprotected function.

+
Parameters
+ + + + +
resultFresh variable name to store the result of call.
tokenFresh variable name to store the protection token of call.
callThe (protected) function call that must be performed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL( token,
 call 
)
+
+ +

Implementation of a flow protected void function call meant to be used from within an unprotected function.

+
Parameters
+ + + +
tokenFresh variable name to store the protection token of call.
callThe (protected) function call that must be performed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL( result,
 token,
 call 
)
+
+ +

Implementation of a flow protected function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL.

+
Parameters
+ + + + +
resultFresh variable name to store the result of call.
tokenFresh variable name to store the protection token of call.
callThe (protected) function call that must be performed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL()
+
+ +

Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL.

+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL( token,
 call 
)
+
+ +

Implementation of a flow protected void function call meant to be used from within an unprotected function, that must be terminated by MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL.

+
Parameters
+ + + +
tokenFresh variable name to store the protection token of call.
callThe (protected) function call that must be performed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL()
+
+ +

Implementation of the end of a section started by MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00881.js b/components/els_pkc/doc/mcxn/html/a00881.js new file mode 100644 index 000000000..dc4bc9979 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00881.js @@ -0,0 +1,41 @@ +var a00881 = +[ + [ "MCUX_CSSL_FP_FUNCTION_ID", "a00881.html#ga479eda7e7852481c11efbc1959aee5ab", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK", "a00881.html#gaaee8a28145962c5b60693126fb43f577", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART", "a00881.html#gafee5e352ad736687d3b51475705cb7e3", null ], + [ "MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART", "a00881.html#ga0b9936d950500136323df9b790a53cbf", null ], + [ "MCUX_CSSL_FP_FUNCTION_DECL_IMPL", "a00881.html#gad18deaf144ed415268a00f1634552e22", null ], + [ "MCUX_CSSL_FP_FUNCTION_VALUE", "a00881.html#gad9e9dfa4b8b661a90fca8a8348d85797", null ], + [ "MCUX_CSSL_FP_FUNCTION_DEF_IMPL", "a00881.html#gae834db0dba75df2b3f18e773b6f054b8", null ], + [ "MCUX_CSSL_FP_RESULT_OFFSET", "a00881.html#ga7ec1aab92504892fe1f18c2890298b21", null ], + [ "MCUX_CSSL_FP_RESULT_MASK", "a00881.html#ga841d36aa501a694ec13c5f1cc0c55d18", null ], + [ "MCUX_CSSL_FP_RESULT_VALUE", "a00881.html#ga8fa4f755ce171f2497d143b627478aa8", null ], + [ "MCUX_CSSL_FP_RESULT_IMPL", "a00881.html#ga2464ae5055d514ca07dfd0a912d66233", null ], + [ "MCUX_CSSL_FP_PROTECTION_OFFSET", "a00881.html#ga4e64bd8d03d3e33458ee8a7fccb37c45", null ], + [ "MCUX_CSSL_FP_PROTECTION_MASK", "a00881.html#ga8778012875929ec230fcfdf10ff9500f", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE", "a00881.html#gaeba1f8f690177515b77e499d9d99b4e3", null ], + [ "MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL", "a00881.html#ga5da930d2d73279d4361af98b96771185", null ], + [ "MCUX_CSSL_FP_COUNTER_COMPRESSED", "a00881.html#ga2aa4e71591c9e48638a5733885a77972", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALLED_IMPL", "a00881.html#ga387940e23bd51390165c5cdffe5b2e6e", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL", "a00881.html#gaaf3937045ab2420f95b209d63d380b0e", null ], + [ "MCUX_CSSL_FP_PROTECTED_TYPE_IMPL", "a00881.html#ga8c5845ea3e1b932b969db83484b26ecf", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn", "a00881.html#ga1a8ea6cc710859bcadb79a488dd8db25", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1", "a00881.html#gab4ce00a3b45306924fe9b0b6664bde0a", null ], + [ "MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL", "a00881.html#gade96ac1fafaf20164fda6e40ec29b111", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn", "a00881.html#gadff771aa8e6ddffa0943c1e05d143d3b", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1", "a00881.html#gafbffa86482e7c82632c29b7b47268cc0", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2", "a00881.html#ga9c6252af0f1985853ed349c5d1ae1788", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_IMPL", "a00881.html#gaa04b0a2008a71b07057236083492ff59", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn", "a00881.html#ga98f3eec493dd7bf7b26f064c31302c73", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3", "a00881.html#gad1f605647ff376aba41b2362d8d02def", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL", "a00881.html#ga03a6226c405fe4012598d538b751d8e0", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1", "a00881.html#ga7d4f6f29ec46da78d39c6835c2353c43", null ], + [ "MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL", "a00881.html#gada3bd3043e47a7155cbd6f48a19d8a7b", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_IMPL", "a00881.html#ga6dea11ddfc9ee7a58fd4c002bd2aa298", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL", "a00881.html#gacf0993520e666067ce074749c90e3d84", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL", "a00881.html#gadc1544cfd424c8ea5e09a97a6b48defa", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL", "a00881.html#gab0ff0e165d943faba9241de4f57c2d75", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL", "a00881.html#ga260f6caaf5d3f526e664835f6889fec5", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL", "a00881.html#ga8f9fbedb24cf72ef01632cc7a2df1f91", null ], + [ "MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL", "a00881.html#gae44806e59bfa6e136c7df9c641809621", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00882.html b/components/els_pkc/doc/mcxn/html/a00882.html new file mode 100644 index 000000000..0a54e6404 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00882.html @@ -0,0 +1,371 @@ + + + + + + + +MCUX CLNS: Looping flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Looping flow protection
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Support for flow protected loops. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_LOOP_ID(id)
 Generator for loop identifiers. More...
 
#define MCUX_CSSL_FP_LOOP_DECL_IMPL(id)
 Declaration implementation of a flow protected loop. More...
 
#define MCUX_CSSL_FP_LOOP_VALUE(id)
 Macro to get the value for a given loop. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, ...)
 Event implementation of a loop iteration (with expectations). More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1(id)
 Event implementation of a loop iteration (without expectations). More...
 
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL(...)
 Event implementation of a loop iteration. More...
 
#define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count)
 Expectation implementation of a number of loop iterations. More...
 
+

Detailed Description

+

Support for flow protected loops.

+
Declaration
MCUX_CSSL_FP_LOOP_DECL_IMPL
+
Event
MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+
Expectation
MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_LOOP_ID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ID( id)
+
+ +

Generator for loop identifiers.

+
Parameters
+ + +
idIdentifier for the flow protected loop.
+
+
+
Returns
Counter value for the given loop.
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_DECL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_DECL_IMPL( id)
+
+ +

Declaration implementation of a flow protected loop.

+
Parameters
+ + +
idIdentifier for the loop that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_VALUE( id)
+
+ +

Macro to get the value for a given loop.

+
Parameters
+ + +
idIdentifier for the loop that is flow protected.
+
+
+
Returns
The counter value for the given loop id.
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATION_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn( id,
 ... 
)
+
+ +

Event implementation of a loop iteration (with expectations).

+
See also
MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+
Parameters
+ + + +
idIdentifier for the loop that is flow protected.
expectOne or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATION_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1( id)
+
+ +

Event implementation of a loop iteration (without expectations).

+
See also
MCUX_CSSL_FP_LOOP_ITERATION_IMPL
+
+MCUX_CSSL_FP_LOOP_ITERATION_IMPLn
+
Parameters
+ + +
idIdentifier for the loop that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATION_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL( ...)
+
+ +

Event implementation of a loop iteration.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_LOOP_ITERATION_IMPL1
+
+MCUX_CSSL_FP_LOOP_ITERATION_IMPLn
+
Parameters
+ + + +
idIdentifier for the loop that is flow protected.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL( id,
 count 
)
+
+ +

Expectation implementation of a number of loop iterations.

+
Parameters
+ + + +
idIdentifier of the flow protected loop.
countNumber of expected iterations.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00882.js b/components/els_pkc/doc/mcxn/html/a00882.js new file mode 100644 index 000000000..2ec044d99 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00882.js @@ -0,0 +1,10 @@ +var a00882 = +[ + [ "MCUX_CSSL_FP_LOOP_ID", "a00882.html#ga995fa3b11e4cc00e87135ada7aef8d5e", null ], + [ "MCUX_CSSL_FP_LOOP_DECL_IMPL", "a00882.html#gaf96c3a513125fcf430cbf3b5fe595e4f", null ], + [ "MCUX_CSSL_FP_LOOP_VALUE", "a00882.html#ga7eef9d81d7343fd127b4b05c14944d1c", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPLn", "a00882.html#ga60705dcec1d1ad92e356e66725d3bf3e", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPL1", "a00882.html#ga4c1cfe8ca5990c4c17f5193bcfe0df7e", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATION_IMPL", "a00882.html#ga5d124a3ac8175c17ef669fde72edb64f", null ], + [ "MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL", "a00882.html#gaae28d69224446d35fe5e09fcde65a16b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00883.html b/components/els_pkc/doc/mcxn/html/a00883.html new file mode 100644 index 000000000..aad99eeff --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00883.html @@ -0,0 +1,800 @@ + + + + + + + +MCUX CLNS: Branching flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Branching flow protection
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Support for flow protected branches. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_BRANCH_ID(id)
 Generator for branch identifiers. More...
 
#define MCUX_CSSL_FP_BRANCH_DECL_IMPL(id)
 Declaration implementation of a flow protected branch. More...
 
#define MCUX_CSSL_FP_BRANCH_VALUE(id)
 Macro to get the value for a given branch. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE
 Value to use for the positive scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE
 Value to use for the negative scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, scenario, ...)
 Event implementation for the execution of a specified branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn(id, ...)
 Event implementation for the execution of a positive branch scenario (with expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1(id)
 Event implementation for the execution of a positive branch scenario (without expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(...)
 Event implementation for the execution of a positive branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn(id, ...)
 Event implementation for the execution of a negative branch scenario (with expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1(id)
 Event implementation for the execution of a negative branch scenario (without expectations). More...
 
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(...)
 Event implementation for the execution of a negative branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, scenario, condition)
 Expectation implementation of an executed specified branch scenario. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2(id, condition)
 Expectation implementation of an executed positive branch (with condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1(id)
 Expectation implementation of an executed positive branch (without condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(...)
 Expectation implementation of an executed positive branch. More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2(id, condition)
 Expectation implementation of an executed negative branch (with condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1(id)
 Expectation implementation of an executed negative branch (without condition). More...
 
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(...)
 Expectation implementation of an executed negative branch. More...
 
+

Detailed Description

+

Support for flow protected branches.

+
Declaration
MCUX_CSSL_FP_BRANCH_DECL_IMPL
+
Events
MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+
Expectations
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_BRANCH_ID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_ID( id)
+
+ +

Generator for branch identifiers.

+
Parameters
+ + +
idIdentifier for the flow protected branch.
+
+
+
Returns
Counter value for the given branch.
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_DECL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_DECL_IMPL( id)
+
+ +

Declaration implementation of a flow protected branch.

+
Parameters
+ + +
idIdentifier for the branch that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_VALUE( id)
+
+ +

Macro to get the value for a given branch.

+
Parameters
+ + +
idIdentifier for the branch that is flow protected.
+
+
+
Returns
The counter value for the given branch id.
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE

+ +
+
+ + + + +
#define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE
+
+ +

Value to use for the positive scenario.

+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE

+ +
+
+ + + + +
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE
+
+ +

Value to use for the negative scenario.

+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL( id,
 scenario,
 ... 
)
+
+ +

Event implementation for the execution of a specified branch scenario.

+
See also
MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+
Parameters
+ + + + +
idIdentifier for the branch for which the given scenario is executed.
scenarioThe scenario for a branch is either positive or negative.
expectOne or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn( id,
 ... 
)
+
+ +

Event implementation for the execution of a positive branch scenario (with expectations).

+
See also
MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1
+
Parameters
+ + + +
idIdentifier for the branch for which the positive scenario is executed.
expectOne or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1( id)
+
+ +

Event implementation for the execution of a positive branch scenario (without expectations).

+
See also
MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn
+
Parameters
+ + +
idIdentifier for the branch for which the positive scenario is executed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL( ...)
+
+ +

Event implementation for the execution of a positive branch scenario.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1
+
+MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn
+
Parameters
+ + + +
idIdentifier for the branch for which the positive scenario is executed.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn( id,
 ... 
)
+
+ +

Event implementation for the execution of a negative branch scenario (with expectations).

+
See also
MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1
+
Parameters
+ + + +
idIdentifier for the branch for which the negative scenario is executed.
expectOne or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1( id)
+
+ +

Event implementation for the execution of a negative branch scenario (without expectations).

+
See also
MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn
+
Parameters
+ + +
idIdentifier for the branch for which the negative scenario is executed.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL( ...)
+
+ +

Event implementation for the execution of a negative branch scenario.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1
+
+MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn
+
Parameters
+ + + +
idIdentifier for the branch for which the negative scenario is executed.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_IMPL

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL( id,
 scenario,
 condition 
)
+
+ +

Expectation implementation of an executed specified branch scenario.

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+
Parameters
+ + + + +
idIdentifier of the flow protected branch.
scenarioThe scenario for a branch is either positive or negative.
conditionCondition under which this branch is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2( id,
 condition 
)
+
+ +

Expectation implementation of an executed positive branch (with condition).

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1
+
Parameters
+ + + +
idIdentifier of the flow protected branch.
conditionCondition under which this branch is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1( id)
+
+ +

Expectation implementation of an executed positive branch (without condition).

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2
+
Parameters
+ + +
idIdentifier of the flow protected branch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL( ...)
+
+ +

Expectation implementation of an executed positive branch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1
+
+MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2
+
Parameters
+ + + +
idIdentifier of the flow protected branch.
conditionOptional, condition under which this branch is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2( id,
 condition 
)
+
+ +

Expectation implementation of an executed negative branch (with condition).

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1
+
Parameters
+ + + +
idIdentifier of the flow protected branch.
conditionCondition under which this branch is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1( id)
+
+ +

Expectation implementation of an executed negative branch (without condition).

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL
+
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2
+
Parameters
+ + +
idIdentifier of the flow protected branch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL( ...)
+
+ +

Expectation implementation of an executed negative branch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1
+
+MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2
+
Parameters
+ + + +
idIdentifier of the flow protected branch.
conditionOptional, condition under which this branch is taken.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00883.js b/components/els_pkc/doc/mcxn/html/a00883.js new file mode 100644 index 000000000..bd188f94b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00883.js @@ -0,0 +1,22 @@ +var a00883 = +[ + [ "MCUX_CSSL_FP_BRANCH_ID", "a00883.html#ga0cd46ecad6c5ab6ef4ba6ff18a79b1eb", null ], + [ "MCUX_CSSL_FP_BRANCH_DECL_IMPL", "a00883.html#gaf4e4c76c10150fa1b5e8944f33720c44", null ], + [ "MCUX_CSSL_FP_BRANCH_VALUE", "a00883.html#ga24770b08dbac22e0ca123f737f9710b3", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE", "a00883.html#gafd8b6619c2105004d85eee8581c4969c", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE", "a00883.html#ga82df96ef3fb0b8718bff46f3f4cd9a5c", null ], + [ "MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL", "a00883.html#gab65273365a2139c4e6693664c8dc7e36", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn", "a00883.html#ga3232cfdb56c441fe5c6a914e38528494", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1", "a00883.html#ga54981abcad9da3f0d9a347ec3d0d2953", null ], + [ "MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL", "a00883.html#gadff057603f2018ef9440b0e981353a48", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn", "a00883.html#ga49e07e6c9d6faf768cd464d4cdb4a881", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1", "a00883.html#ga8547d895809dfb59bf0709fbc49e5483", null ], + [ "MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL", "a00883.html#gaf7f462f39963033ea44c0f7c7f41a76f", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_IMPL", "a00883.html#ga640bbb8417eb2e2fd975431d15a9364d", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2", "a00883.html#ga8a3b0d047ea142e74e5bef729508f683", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1", "a00883.html#ga29b42c7c0d701dc98159e7e04aafcd93", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL", "a00883.html#gaae07d1c658effb2daa3df7a75214b0f1", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2", "a00883.html#gae5068ae5b0a47a9d366e832f255e9ce9", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1", "a00883.html#gaff88c9879207f5f1d7ab643fdd9c278f", null ], + [ "MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL", "a00883.html#ga2142ecf918cf320bf1b15b8d8cfe5253", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00884.html b/components/els_pkc/doc/mcxn/html/a00884.html new file mode 100644 index 000000000..7bf0dba94 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00884.html @@ -0,0 +1,719 @@ + + + + + + + +MCUX CLNS: Switching flow protection + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Switching flow protection
MCUX CSSL &ndash; Implementations » Flow Protection: Secure Counter
+
+
+ +

Support for flow protected switches. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_FP_SWITCH_ID(id)
 Generator for switch identifiers. More...
 
#define MCUX_CSSL_FP_SWITCH_DECL_IMPL(id)
 Declaration implementation of a flow protected switch. More...
 
#define MCUX_CSSL_FP_SWITCH_VALUE(id)
 Macro to get the value for a given switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, ...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL2(id, case)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE
 Value to use for default case. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, ...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1(id)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(...)
 Case that is being handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, condition)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2(id, case)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(...)
 Expected that a specific case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, condition)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1(id)
 Expected that default case is handled from a switch. More...
 
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(...)
 Expected that default case is handled from a switch. More...
 
+

Detailed Description

+

Support for flow protected switches.

+
Declaration
MCUX_CSSL_FP_SWITCH_DECL_IMPL
+
Events
MCUX_CSSL_FP_SWITCH_CASE_IMPL
+MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+
Expectations
MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_FP_SWITCH_ID

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_ID( id)
+
+ +

Generator for switch identifiers.

+
Parameters
+ + +
idIdentifier for the flow protected switch.
+
+
+
Returns
Counter value for the given loop.
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DECL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DECL_IMPL( id)
+
+ +

Declaration implementation of a flow protected switch.

+
Parameters
+ + +
idIdentifier for the switch that is flow protected.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_VALUE

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_VALUE( id)
+
+ +

Macro to get the value for a given switch.

+
Parameters
+ + +
idIdentifier for the switch that is flow protected.
+
+
+
Returns
The counter value for the given switch id.
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_CASE_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_CASE_IMPLn( id,
 case,
 ... 
)
+
+ +

Case that is being handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_CASE_IMPL
+
+MCUX_CSSL_FP_SWITCH_CASE_IMPL2
+
Parameters
+ + + + +
idIdentifier of the flow protected switch.
caseCase value that is chosen in the switch.
expectOne or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_CASE_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL2( id,
 case 
)
+
+ +

Case that is being handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_CASE_IMPL
+
+MCUX_CSSL_FP_SWITCH_CASE_IMPLn
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
caseCase value that is chosen in the switch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_CASE_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_CASE_IMPL( ...)
+
+ +

Case that is being handled from a switch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_SWITCH_CASE_IMPL2
+
+MCUX_CSSL_FP_SWITCH_CASE_IMPLn
+
Parameters
+ + + + +
idIdentifier of the flow protected switch.
caseCase value that is chosen in the switch.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE

+ +
+
+ + + + +
#define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE
+
+ +

Value to use for default case.

+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn( id,
 ... 
)
+
+ +

Case that is being handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+
+MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1( id)
+
+ +

Case that is being handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL
+
+MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn
+
Parameters
+ + +
idIdentifier of the flow protected switch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL( ...)
+
+ +

Case that is being handled from a switch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1
+
+MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
expectZero or more (comma separated) declarations of expected code flow behavior related to this event.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3( id,
 case,
 condition 
)
+
+ +

Expected that a specific case is handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+
+MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2
+
Parameters
+ + + + +
idIdentifier of the flow protected switch.
caseValue of the case that is expected to be chosen in the switch.
conditionOptional, condition under which the case is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2( id,
 case 
)
+
+ +

Expected that a specific case is handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_IMPL
+
+MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
caseValue of the case that is expected to be chosen in the switch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL( ...)
+
+ +

Expected that a specific case is handled from a switch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2
+
+MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3
+
Parameters
+ + + + +
idIdentifier of the flow protected switch.
caseValue of the case that is expected to be chosen in the switch.
conditionOptional, condition under which the case is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2( id,
 condition 
)
+
+ +

Expected that default case is handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
conditionCondition under which the default case is taken.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1( id)
+
+ +

Expected that default case is handled from a switch.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL
+
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2
+
Parameters
+ + +
idIdentifier of the flow protected switch.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL( ...)
+
+ +

Expected that default case is handled from a switch.

+

Implemented as an overloaded macro to simplify the use of the API.

+
See also
MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1
+
+MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2
+
Parameters
+ + + +
idIdentifier of the flow protected switch.
conditionOptional, condition under which the default case is taken.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00884.js b/components/els_pkc/doc/mcxn/html/a00884.js new file mode 100644 index 000000000..f78c41689 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00884.js @@ -0,0 +1,19 @@ +var a00884 = +[ + [ "MCUX_CSSL_FP_SWITCH_ID", "a00884.html#gaf1c0885504f90cfa3da18399d96b1319", null ], + [ "MCUX_CSSL_FP_SWITCH_DECL_IMPL", "a00884.html#ga685b8b131aa17d9a2fbb215cf282e47e", null ], + [ "MCUX_CSSL_FP_SWITCH_VALUE", "a00884.html#ga60aebfce23f0dc04ef9035404526a049", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPLn", "a00884.html#ga5f9c86c89dde886bc8a4d0685c193b35", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPL2", "a00884.html#ga7228ed734302bc58312a7f120f437ea4", null ], + [ "MCUX_CSSL_FP_SWITCH_CASE_IMPL", "a00884.html#ga4fac747213aeed1e92363a2bdd68406b", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE", "a00884.html#ga3c29758b5fe14aacedaebdf5a77a2a24", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn", "a00884.html#gac3dcce63f39b86956e2535b5277781e7", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1", "a00884.html#gaf7458c44a5c0237192b047645b9fef44", null ], + [ "MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL", "a00884.html#gade7e9242949c3b56a6c26d4f9baa4184", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3", "a00884.html#gae6c4eb02ea889928868e6eae6d4fac9e", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2", "a00884.html#ga74061d2cc9faf009465c92cf7fa2806f", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_IMPL", "a00884.html#ga2cea4b8acd163c7b4877267c4221a9d4", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2", "a00884.html#gaf4a47979ed6e58b347658038ed393210", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1", "a00884.html#gaef7299bb6aa7dc7a367edae023cc2a41", null ], + [ "MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL", "a00884.html#gadd39e2b4cb02e9c849a289302465a8ff", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00885.html b/components/els_pkc/doc/mcxn/html/a00885.html new file mode 100644 index 000000000..cfc67a74f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00885.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: mcuxCssl Memory API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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mcuxCssl Memory API
MCUX CSSL &ndash; API
+
+
+ +

Control Flow Protected Memory Functions. +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 mcuxCssl Memory Clear
 Control Flow Protected Memory Clear Function.
 
 mcuxCssl Memory Compare
 Control Flow Protected Memory Compare Function.
 
 mcuxCssl Memory Copy
 Control Flow Protected Memory Copy Function.
 
 mcuxCssl Memory Set
 Control Flow Protected Memory Set Function.
 
 mcuxCsslMemory_Types
 Defines common macros and types of mcuxCssl Memory API.
 
+

Detailed Description

+

Control Flow Protected Memory Functions.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00885.js b/components/els_pkc/doc/mcxn/html/a00885.js new file mode 100644 index 000000000..4b36257af --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00885.js @@ -0,0 +1,8 @@ +var a00885 = +[ + [ "mcuxCssl Memory Clear", "a00886.html", "a00886" ], + [ "mcuxCssl Memory Compare", "a00888.html", "a00888" ], + [ "mcuxCssl Memory Copy", "a00890.html", "a00890" ], + [ "mcuxCssl Memory Set", "a00892.html", "a00892" ], + [ "mcuxCsslMemory_Types", "a00894.html", "a00894" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00886.html b/components/els_pkc/doc/mcxn/html/a00886.html new file mode 100644 index 000000000..d85780b5f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00886.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxCssl Memory Clear + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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mcuxCssl Memory Clear
MCUX CSSL &ndash; API » mcuxCssl Memory API
+
+
+ +

Control Flow Protected Memory Clear Function. +More...

+ + + + + +

+Modules

 mcuxCsslMemory_Clear Function Definitions
 mcuxCsslMemory_Clear Function Definitions
 
+

Detailed Description

+

Control Flow Protected Memory Clear Function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00886.js b/components/els_pkc/doc/mcxn/html/a00886.js new file mode 100644 index 000000000..6d2e2117d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00886.js @@ -0,0 +1,4 @@ +var a00886 = +[ + [ "mcuxCsslMemory_Clear Function Definitions", "a00887.html", "a00887" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00887.html b/components/els_pkc/doc/mcxn/html/a00887.html new file mode 100644 index 000000000..ad2ffff57 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00887.html @@ -0,0 +1,196 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Clear Function Definitions + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslMemory_Clear Function Definitions
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCssl Memory Clear
+
+
+ +

mcuxCsslMemory_Clear Function Definitions +More...

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Clear (mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, size_t dstLength, size_t length)
 Clear length bytes of data at pDst. More...
 
+

Detailed Description

+

mcuxCsslMemory_Clear Function Definitions

+

Function Documentation

+ +

◆ mcuxCsslMemory_Clear()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxCsslMemory_Status_t mcuxCsslMemory_Clear (mcuxCsslParamIntegrity_Checksum_t chk,
void * pDst,
size_t dstLength,
size_t length 
)
+
+ +

Clear length bytes of data at pDst.

+

The implementation is secure in the following aspects: Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum. Code flow protection: the function call is protected. Buffer overflow protection: no data is written to pDst beyond dstLength bytes.

+
Parameters
+ + + + + +
[in]chkThe parameter checksum, generated with mcuxCsslParamIntegrity_Protect.
[in]pDstThe destination pointer to buffer to be cleared. Must not be NULL.
[in]dstLengthThe size of the destination data buffer in bytes.
[in]lengthThe number of bytes to clear. Must be different from zero.
+
+
+
Returns
A status code encapsulated in a flow-protection type.
+
Return values
+ + + + +
MCUXCSSLMEMORY_STATUS_OKIf the contents in buffer at pDst is cleared.
MCUXCSSLMEMORY_STATUS_INVALID_PARAMETERIf one of the parameters is invalid.
MCUXCSSLMEMORY_STATUS_FAULTIf a fault was detected, included invalid checksum chk.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00887.js b/components/els_pkc/doc/mcxn/html/a00887.js new file mode 100644 index 000000000..755095e68 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00887.js @@ -0,0 +1,4 @@ +var a00887 = +[ + [ "mcuxCsslMemory_Clear", "a00887.html#gaea7d5f3c8d216e752f153827689e88c3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00888.html b/components/els_pkc/doc/mcxn/html/a00888.html new file mode 100644 index 000000000..aef55be1b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00888.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxCssl Memory Compare + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
+
mcuxCssl Memory Compare
MCUX CSSL &ndash; API » mcuxCssl Memory API
+
+
+ +

Control Flow Protected Memory Compare Function. +More...

+ + + + + +

+Modules

 mcuxCsslMemory_Compare Function Definitions
 mcuxCsslMemory_Compare Function Definitions
 
+

Detailed Description

+

Control Flow Protected Memory Compare Function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00888.js b/components/els_pkc/doc/mcxn/html/a00888.js new file mode 100644 index 000000000..13a1444ae --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00888.js @@ -0,0 +1,4 @@ +var a00888 = +[ + [ "mcuxCsslMemory_Compare Function Definitions", "a00889.html", "a00889" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00889.html b/components/els_pkc/doc/mcxn/html/a00889.html new file mode 100644 index 000000000..932ad103a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00889.html @@ -0,0 +1,202 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Compare Function Definitions + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslMemory_Compare Function Definitions
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCssl Memory Compare
+
+
+ +

mcuxCsslMemory_Compare Function Definitions +More...

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Compare (mcuxCsslParamIntegrity_Checksum_t chk, void const *pLhs, void const *pRhs, size_t length)
 Compares the two memory regions lhs and rhs. More...
 
+

Detailed Description

+

mcuxCsslMemory_Compare Function Definitions

+

Function Documentation

+ +

◆ mcuxCsslMemory_Compare()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxCsslMemory_Status_t mcuxCsslMemory_Compare (mcuxCsslParamIntegrity_Checksum_t chk,
void const * pLhs,
void const * pRhs,
size_t length 
)
+
+ +

Compares the two memory regions lhs and rhs.

+

The implementation is secure in the following aspects:

+
    +
  • Constant execution time: The execution sequence of the code is always identical for equal length parameters, i.e. no branches are performed based on the data in pLhs or pRhs.
    • +
  • Parameter integrity protection: An incorrect parameter checksum makes the function return immediately.
    • +
  • Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation.
    • +
+
Parameters
+ + + + + +
chkThe parameter checksum, generated with mcuxCsslParamIntegrity_Protect.
pLhsThe left-hand side data to compare. Must not be NULL.
pRhsThe right-hand side data to compare. Must not be NULL.
lengthThe number of bytes to compare. Must be different from zero.
+
+
+
Returns
A status code encapsulated in a flow-protection type.
+
Return values
+ + + + + +
MCUXCSSLMEMORY_STATUS_EQUALIf the contents of lhs and rhs are equal.
MCUXCSSLMEMORY_STATUS_NOT_EQUALIf the contents of lhs and rhs are not equal.
MCUXCSSLMEMORY_STATUS_INVALID_PARAMETERIf one of the parameters was invalid (i.e. lhs or rhs was NULL or length was zero).
MCUXCSSLMEMORY_STATUS_FAULTIf a fault was detected.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00889.js b/components/els_pkc/doc/mcxn/html/a00889.js new file mode 100644 index 000000000..a504c31be --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00889.js @@ -0,0 +1,4 @@ +var a00889 = +[ + [ "mcuxCsslMemory_Compare", "a00889.html#ga0a6695838853535250234994d7e4d5b1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00890.html b/components/els_pkc/doc/mcxn/html/a00890.html new file mode 100644 index 000000000..5f9053d71 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00890.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxCssl Memory Copy + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCssl Memory Copy
MCUX CSSL &ndash; API » mcuxCssl Memory API
+
+
+ +

Control Flow Protected Memory Copy Function. +More...

+ + + + + +

+Modules

 mcuxCsslMemory_Copy Function Definitions
 mcuxCsslMemory_Copy Function Definitions
 
+

Detailed Description

+

Control Flow Protected Memory Copy Function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00890.js b/components/els_pkc/doc/mcxn/html/a00890.js new file mode 100644 index 000000000..9bd46ae41 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00890.js @@ -0,0 +1,4 @@ +var a00890 = +[ + [ "mcuxCsslMemory_Copy Function Definitions", "a00891.html", "a00891" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00891.html b/components/els_pkc/doc/mcxn/html/a00891.html new file mode 100644 index 000000000..8e641fe2d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00891.html @@ -0,0 +1,209 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Copy Function Definitions + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslMemory_Copy Function Definitions
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCssl Memory Copy
+
+
+ +

mcuxCsslMemory_Copy Function Definitions +More...

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Copy (mcuxCsslParamIntegrity_Checksum_t chk, void const *pSrc, void *pDst, size_t dstLength, size_t length)
 Copies length bytes of data from pSrc to pDst. More...
 
+

Detailed Description

+

mcuxCsslMemory_Copy Function Definitions

+

Function Documentation

+ +

◆ mcuxCsslMemory_Copy()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxCsslMemory_Status_t mcuxCsslMemory_Copy (mcuxCsslParamIntegrity_Checksum_t chk,
void const * pSrc,
void * pDst,
size_t dstLength,
size_t length 
)
+
+ +

Copies length bytes of data from pSrc to pDst.

+

The implementation is secure in the following aspects:

+
    +
  • Constant execution time: If pSrc and pDst have the same offset to the nearest 16-byte boundary, and if length is the same, the execution sequence of the code is always identical.
    • +
  • Parameter integrity protection: An incorrect parameter checksum makes the function return immediately.
    • +
  • Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation.
    • +
  • Buffer overflow protection: No data is written to pDst beyond dstLength bytes.
    • +
+
Parameters
+ + + + + + +
[in]chkThe parameter checksum, generated with mcuxCsslParamIntegrity_Protect.
[in]pSrcThe data to be copied. Must not be NULL. Must not overlap with pDst.
[out]pDstThe destination pointer. Must not be NULL. Must not overlap with pSrc.
[in]dstLengthThe size of the destination data buffer in bytes.
[in]lengthThe number of bytes to copy. Must be different from zero.
+
+
+
Returns
A status code encapsulated in a flow-protection type.
+
Return values
+ + + + +
MCUXCSSLMEMORY_STATUS_OKIf the operation was successful.
MCUXCSSLMEMORY_STATUS_INVALID_PARAMETERIf one of the parameters was invalid (i.e. pSrc or pDst was NULL or length was zero).
MCUXCSSLMEMORY_STATUS_FAULTIf a fault was detected.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00891.js b/components/els_pkc/doc/mcxn/html/a00891.js new file mode 100644 index 000000000..ab019df8f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00891.js @@ -0,0 +1,4 @@ +var a00891 = +[ + [ "mcuxCsslMemory_Copy", "a00891.html#gaa29b7e8d23c8d95ce248fc8e0a4b37c8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00892.html b/components/els_pkc/doc/mcxn/html/a00892.html new file mode 100644 index 000000000..a228b672f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00892.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: mcuxCssl Memory Set + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
+
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mcuxCssl Memory Set
MCUX CSSL &ndash; API » mcuxCssl Memory API
+
+
+ +

Control Flow Protected Memory Set Function. +More...

+ + + + + +

+Modules

 mcuxCsslMemory_Set Function Definitions
 mcuxCsslMemory_Set Function Definitions
 
+

Detailed Description

+

Control Flow Protected Memory Set Function.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00892.js b/components/els_pkc/doc/mcxn/html/a00892.js new file mode 100644 index 000000000..92033bbe4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00892.js @@ -0,0 +1,4 @@ +var a00892 = +[ + [ "mcuxCsslMemory_Set Function Definitions", "a00893.html", "a00893" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00893.html b/components/els_pkc/doc/mcxn/html/a00893.html new file mode 100644 index 000000000..6503333bc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00893.html @@ -0,0 +1,203 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Set Function Definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
+
mcuxCsslMemory_Set Function Definitions
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCssl Memory Set
+
+
+ +

mcuxCsslMemory_Set Function Definitions +More...

+ + + + + +

+Functions

mcuxCsslMemory_Status_t mcuxCsslMemory_Set (mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, uint8_t val, size_t length, size_t bufLength)
 Set length bytes of data at pDst. More...
 
+

Detailed Description

+

mcuxCsslMemory_Set Function Definitions

+

Function Documentation

+ +

◆ mcuxCsslMemory_Set()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxCsslMemory_Status_t mcuxCsslMemory_Set (mcuxCsslParamIntegrity_Checksum_t chk,
void * pDst,
uint8_t val,
size_t length,
size_t bufLength 
)
+
+ +

Set length bytes of data at pDst.

+

The implementation is secure in the following aspects: Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum. Code flow protection: the function call is protected. Buffer overflow protection: no data is written to pDst beyond bufLength bytes.

+
Parameters
+ + + + + + +
[in]chkThe parameter checksum, generated with mcuxCsslParamIntegrity_Protect.
[in]pDstThe destination pointer to buffer to be set. Must not be NULL.
[in]valThe byte value to be set.
[in]lengthThe size in bytes to set. Must be different from zero.
[in]bufLengthThe buffer size (if bufLength < length, only bufLength bytes are set).
+
+
+
Returns
A status code encapsulated in a flow-protection type.
+
Return values
+ + + + +
MCUXCSSLMEMORY_STATUS_OKIf val set length times at pDst.
MCUXCSSLMEMORY_STATUS_INVALID_PARAMETERIf one of the parameters is invalid.
MCUXCSSLMEMORY_STATUS_FAULTIf a fault was detected, included invalid checksum chk.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00893.js b/components/els_pkc/doc/mcxn/html/a00893.js new file mode 100644 index 000000000..2c6a22fa7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00893.js @@ -0,0 +1,4 @@ +var a00893 = +[ + [ "mcuxCsslMemory_Set", "a00893.html#ga0a0ed6d55e0cb4d633ba19a32aca64c6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00894.html b/components/els_pkc/doc/mcxn/html/a00894.html new file mode 100644 index 000000000..0bd56edf9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00894.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
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+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
mcuxCsslMemory_Types
MCUX CSSL &ndash; API » mcuxCssl Memory API
+
+
+ +

Defines common macros and types of mcuxCssl Memory API. +More...

+ + + + + + + + +

+Modules

 mcuxCsslMemory_Types_Macros
 Defines all macros of mcuxCsslMemory_Types.
 
 mcuxCsslMemory_Types_Types
 Defines all types of mcuxCsslMemory_Types.
 
+

Detailed Description

+

Defines common macros and types of mcuxCssl Memory API.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00894.js b/components/els_pkc/doc/mcxn/html/a00894.js new file mode 100644 index 000000000..9a4c933ab --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00894.js @@ -0,0 +1,5 @@ +var a00894 = +[ + [ "mcuxCsslMemory_Types_Macros", "a00895.html", "a00895" ], + [ "mcuxCsslMemory_Types_Types", "a00896.html", "a00896" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00895.html b/components/els_pkc/doc/mcxn/html/a00895.html new file mode 100644 index 000000000..df5ccc82f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00895.html @@ -0,0 +1,265 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Types_Macros + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
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+ +
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+
+Macros
+
+
mcuxCsslMemory_Types_Macros
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCsslMemory_Types
+
+
+ +

Defines all macros of mcuxCsslMemory_Types. +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCSSLMEMORY_STATUS_OK
 The operation was successful. More...
 
#define MCUXCSSLMEMORY_STATUS_EQUAL
 The two contents of the Memory Compare are equal. More...
 
#define MCUXCSSLMEMORY_STATUS_NOT_EQUAL
 The two contents of the Memory Compare are not equal. More...
 
#define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER
 A parameter was invalid. More...
 
#define MCUXCSSLMEMORY_STATUS_FAULT
 A fault occurred in the execution. More...
 
#define MCUXCSSLMEMORY_KEEP_ORDER
 Data storing in destination buffer in original order. More...
 
#define MCUXCSSLMEMORY_REVERSE_ORDER
 Data storing in destination buffer with reversed order. More...
 
+

Detailed Description

+

Defines all macros of mcuxCsslMemory_Types.

+

Macro Definition Documentation

+ +

◆ MCUXCSSLMEMORY_STATUS_OK

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_STATUS_OK
+
+ +

The operation was successful.

+ +
+
+ +

◆ MCUXCSSLMEMORY_STATUS_EQUAL

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_STATUS_EQUAL
+
+ +

The two contents of the Memory Compare are equal.

+ +
+
+ +

◆ MCUXCSSLMEMORY_STATUS_NOT_EQUAL

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_STATUS_NOT_EQUAL
+
+ +

The two contents of the Memory Compare are not equal.

+ +
+
+ +

◆ MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER
+
+ +

A parameter was invalid.

+ +
+
+ +

◆ MCUXCSSLMEMORY_STATUS_FAULT

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_STATUS_FAULT
+
+ +

A fault occurred in the execution.

+ +
+
+ +

◆ MCUXCSSLMEMORY_KEEP_ORDER

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_KEEP_ORDER
+
+ +

Data storing in destination buffer in original order.

+ +
+
+ +

◆ MCUXCSSLMEMORY_REVERSE_ORDER

+ +
+
+ + + + +
#define MCUXCSSLMEMORY_REVERSE_ORDER
+
+ +

Data storing in destination buffer with reversed order.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00895.js b/components/els_pkc/doc/mcxn/html/a00895.js new file mode 100644 index 000000000..7aaee841a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00895.js @@ -0,0 +1,10 @@ +var a00895 = +[ + [ "MCUXCSSLMEMORY_STATUS_OK", "a00895.html#gab2993c75e7ef98fed36f03946630e41c", null ], + [ "MCUXCSSLMEMORY_STATUS_EQUAL", "a00895.html#gafaad4a560714fdff8064ba9a50f7d572", null ], + [ "MCUXCSSLMEMORY_STATUS_NOT_EQUAL", "a00895.html#ga2b5d2b24036bee244a9e7310160b3035", null ], + [ "MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER", "a00895.html#ga0e60adf6203cb3acb2bdb3ddec166766", null ], + [ "MCUXCSSLMEMORY_STATUS_FAULT", "a00895.html#gaf0923b98a5db9fd23732989986d72f4d", null ], + [ "MCUXCSSLMEMORY_KEEP_ORDER", "a00895.html#ga0072c925d0ab8c5b0b071abd1d5218af", null ], + [ "MCUXCSSLMEMORY_REVERSE_ORDER", "a00895.html#ga9c4cf10d8106eca9894d9e3b131b52f9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00896.html b/components/els_pkc/doc/mcxn/html/a00896.html new file mode 100644 index 000000000..da568d147 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00896.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: mcuxCsslMemory_Types_Types + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxCsslMemory_Types_Types
MCUX CSSL &ndash; API » mcuxCssl Memory API » mcuxCsslMemory_Types
+
+
+ +

Defines all types of mcuxCsslMemory_Types. +More...

+ + + + + +

+Typedefs

typedef uint32_t mcuxCsslMemory_Status_t
 Type for CSSL Memory status codes. More...
 
+

Detailed Description

+

Defines all types of mcuxCsslMemory_Types.

+

Typedef Documentation

+ +

◆ mcuxCsslMemory_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxCsslMemory_Status_t
+
+ +

Type for CSSL Memory status codes.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00896.js b/components/els_pkc/doc/mcxn/html/a00896.js new file mode 100644 index 000000000..e8d3f0b27 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00896.js @@ -0,0 +1,4 @@ +var a00896 = +[ + [ "mcuxCsslMemory_Status_t", "a00896.html#ga19c7a1367cb21d7bcb720607f495d86c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00897.html b/components/els_pkc/doc/mcxn/html/a00897.html new file mode 100644 index 000000000..fdb573d29 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00897.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: Parameter Integrity API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
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+Modules
+
+
Parameter Integrity API
MCUX CSSL &ndash; API
+
+
+ +

Functionality to ensure parameter integrity during function calls. +More...

+ + + + + + + + + + + +

+Modules

 mcuxCsslParamIntegrity Macro Definitions
 Macros of mcuxCsslParamIntegrity component.
 
 mcuxCsslParamIntegrity Type Definitions
 Types of mcuxCsslParamIntegrity component.
 
 mcuxCsslParamIntegrity Function Definitions
 Functions of mcuxCsslParamIntegrity component.
 
+

Detailed Description

+

Functionality to ensure parameter integrity during function calls.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00897.js b/components/els_pkc/doc/mcxn/html/a00897.js new file mode 100644 index 000000000..a02e07951 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00897.js @@ -0,0 +1,6 @@ +var a00897 = +[ + [ "mcuxCsslParamIntegrity Macro Definitions", "a00898.html", "a00898" ], + [ "mcuxCsslParamIntegrity Type Definitions", "a00899.html", "a00899" ], + [ "mcuxCsslParamIntegrity Function Definitions", "a00900.html", "a00900" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00898.html b/components/els_pkc/doc/mcxn/html/a00898.html new file mode 100644 index 000000000..4b90b6b60 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00898.html @@ -0,0 +1,189 @@ + + + + + + + +MCUX CLNS: mcuxCsslParamIntegrity Macro Definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
mcuxCsslParamIntegrity Macro Definitions
MCUX CSSL &ndash; API » Parameter Integrity API
+
+
+ +

Macros of mcuxCsslParamIntegrity component. +More...

+ + + + + + + + + + + +

+Macros

#define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM
 First eight hex digits of Eulers number. More...
 
#define MCUXCSSLPARAMINTEGRITY_CHECK_VALID
 Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was correct. More...
 
#define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID
 Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was incorrect. More...
 
+

Detailed Description

+

Macros of mcuxCsslParamIntegrity component.

+

Macro Definition Documentation

+ +

◆ MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM

+ +
+
+ + + + +
#define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM
+
+ +

First eight hex digits of Eulers number.

+ +
+
+ +

◆ MCUXCSSLPARAMINTEGRITY_CHECK_VALID

+ +
+
+ + + + +
#define MCUXCSSLPARAMINTEGRITY_CHECK_VALID
+
+ +

Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was correct.

+ +
+
+ +

◆ MCUXCSSLPARAMINTEGRITY_CHECK_INVALID

+ +
+
+ + + + +
#define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID
+
+ +

Return value of mcuxCsslParamIntegrity_Validate if the parameter checksum was incorrect.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00898.js b/components/els_pkc/doc/mcxn/html/a00898.js new file mode 100644 index 000000000..6a96f4cfc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00898.js @@ -0,0 +1,6 @@ +var a00898 = +[ + [ "MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM", "a00898.html#ga53aac27cab05b855d2ae62f2b1d3d7d0", null ], + [ "MCUXCSSLPARAMINTEGRITY_CHECK_VALID", "a00898.html#gad7a460092fbe39b438614ba1d159bb16", null ], + [ "MCUXCSSLPARAMINTEGRITY_CHECK_INVALID", "a00898.html#ga889eda2d841537edae8f0f7d80dde8b0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00899.html b/components/els_pkc/doc/mcxn/html/a00899.html new file mode 100644 index 000000000..8a0e36bdf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00899.html @@ -0,0 +1,170 @@ + + + + + + + +MCUX CLNS: mcuxCsslParamIntegrity Type Definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Typedefs
+
+
mcuxCsslParamIntegrity Type Definitions
MCUX CSSL &ndash; API » Parameter Integrity API
+
+
+ +

Types of mcuxCsslParamIntegrity component. +More...

+ + + + + + + + +

+Typedefs

typedef void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u==sizeof(size_t)) ?(+1) :(-1)]
 Build time assertion to ensure CPU word size of 32 bit. More...
 
typedef uint32_t mcuxCsslParamIntegrity_Checksum_t
 Type of a parameter checksum. More...
 
+

Detailed Description

+

Types of mcuxCsslParamIntegrity component.

+

Typedef Documentation

+ +

◆ mcuxCsslParamIntegrity_AssertionCpuWordSize_t

+ +
+
+ + + + +
typedef void* mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u==sizeof(size_t)) ?(+1) :(-1)]
+
+ +

Build time assertion to ensure CPU word size of 32 bit.

+ +
+
+ +

◆ mcuxCsslParamIntegrity_Checksum_t

+ +
+
+ + + + +
typedef uint32_t mcuxCsslParamIntegrity_Checksum_t
+
+ +

Type of a parameter checksum.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00899.js b/components/els_pkc/doc/mcxn/html/a00899.js new file mode 100644 index 000000000..798bedcb5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00899.js @@ -0,0 +1,5 @@ +var a00899 = +[ + [ "mcuxCsslParamIntegrity_AssertionCpuWordSize_t", "a00899.html#gaf2a8a66e39dd0d33d085d3d412cafb96", null ], + [ "mcuxCsslParamIntegrity_Checksum_t", "a00899.html#ga6a229130320b395fbb8a8a76a361bd1e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00900.html b/components/els_pkc/doc/mcxn/html/a00900.html new file mode 100644 index 000000000..37314111e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00900.html @@ -0,0 +1,228 @@ + + + + + + + +MCUX CLNS: mcuxCsslParamIntegrity Function Definitions + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
mcuxCsslParamIntegrity Function Definitions
MCUX CSSL &ndash; API » Parameter Integrity API
+
+
+ +

Functions of mcuxCsslParamIntegrity component. +More...

+ + + + + + + + +

+Functions

mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect (size_t nargs,...)
 Calculates a parameter checksum. More...
 
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Validate (mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs,...)
 Verifies the correctness of a parameter checksum. More...
 
+

Detailed Description

+

Functions of mcuxCsslParamIntegrity component.

+

Function Documentation

+ +

◆ mcuxCsslParamIntegrity_Protect()

+ +
+
+ + + + + + + + + + + + + + + + + + +
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect (size_t nargs,
 ... 
)
+
+ +

Calculates a parameter checksum.

+
Parameters
+ + + +
nargsThe number of parameters to be protected.
...The parameters that should be protected. Note that parameters bigger than a single machine word are not supported.
+
+
+
Returns
checksum over the input parameters to be protected
+ +
+
+ +

◆ mcuxCsslParamIntegrity_Validate()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Validate (mcuxCsslParamIntegrity_Checksum_t chk,
size_t nargs,
 ... 
)
+
+ +

Verifies the correctness of a parameter checksum.

+
Parameters
+ + + + +
chkThe parameter checksum.
nargsThe number of parameters to be protected.
...The parameters that were used to calculate the parameter checksum. Note that parameters bigger than a single machine word are not supported.
+
+
+
Returns
A status code encapsulated in a flow-protection type.
+
Return values
+ + + +
MCUXCSSLPARAMINTEGRITY_CHECK_VALIDThe parameter checksum was correct.
MCUXCSSLPARAMINTEGRITY_CHECK_INVALIDThe parameter checksum was incorrect.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00900.js b/components/els_pkc/doc/mcxn/html/a00900.js new file mode 100644 index 000000000..21f1c9a0d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00900.js @@ -0,0 +1,5 @@ +var a00900 = +[ + [ "mcuxCsslParamIntegrity_Protect", "a00900.html#gaaa2a9f40eb61dbe8ccce1b3b2dc824bb", null ], + [ "mcuxCsslParamIntegrity_Validate", "a00900.html#gaface23af4c626fe4adf70518056f2f33", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00901.html b/components/els_pkc/doc/mcxn/html/a00901.html new file mode 100644 index 000000000..1896ed911 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00901.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Secure Counter API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
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+
+
+ +
+ +
+
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+ +
+
+Modules
+
+
Secure Counter API
MCUX CSSL &ndash; API
+
+
+ +

Secure counter mechanism. +More...

+ + + + + + + + + + + + + + +

+Modules

 Secure counter core functionality
 Secure counter handling core functionality.
 
 Secure counter increment
 Support for incrementing the secure counter.
 
 Secure counter decrement
 Support for decrementing the secure counter.
 
 Secure counter direct access
 Support for directly accessing the secure counter.
 
+

Detailed Description

+

Secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00901.js b/components/els_pkc/doc/mcxn/html/a00901.js new file mode 100644 index 000000000..df005ebd2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00901.js @@ -0,0 +1,7 @@ +var a00901 = +[ + [ "Secure counter core functionality", "a00902.html", "a00902" ], + [ "Secure counter increment", "a00903.html", "a00903" ], + [ "Secure counter decrement", "a00904.html", "a00904" ], + [ "Secure counter direct access", "a00905.html", "a00905" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00902.html b/components/els_pkc/doc/mcxn/html/a00902.html new file mode 100644 index 000000000..a391e6cd9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00902.html @@ -0,0 +1,270 @@ + + + + + + + +MCUX CLNS: Secure counter core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
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+
+ +
+ +
+
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+
+Macros
+
+
Secure counter core functionality
MCUX CSSL &ndash; API » Secure Counter API
+
+
+ +

Secure counter handling core functionality. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_CHECK_PASSED
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_ALLOC()
 Allocation operation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT(value)
 Initialization operation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK(reference)
 Comparison operation for the secure counter. More...
 
+

Detailed Description

+

Secure counter handling core functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_CHECK_PASSED

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_PASSED
+
+ +

Positive comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_FAILED

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_FAILED
+
+ +

Negative comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_VALUE_TYPE

+ +
+
+ + + + +
#define MCUX_CSSL_SC_VALUE_TYPE
+
+ +

Data type used for the secure counter values.

+ +
+
+ +

◆ MCUX_CSSL_SC_ALLOC

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ALLOC()
+
+ +

Allocation operation for the secure counter.

+ +
+
+ +

◆ MCUX_CSSL_SC_INIT

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_INIT( value)
+
+ +

Initialization operation for the secure counter.

+
Parameters
+ + +
valueValue with which the secure counter must be initialized.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_CHECK( reference)
+
+ +

Comparison operation for the secure counter.

+
Parameters
+ + +
referenceReference value to compare the secure counter value against.
+
+
+
Returns
Either MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or MCUX_CSSL_SC_CHECK_FAILED if the value is different.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00902.js b/components/els_pkc/doc/mcxn/html/a00902.js new file mode 100644 index 000000000..48ddcb1b5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00902.js @@ -0,0 +1,9 @@ +var a00902 = +[ + [ "MCUX_CSSL_SC_CHECK_PASSED", "a00902.html#ga1f0a9fc2ca02b221c00acb56c1e93b9e", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED", "a00902.html#ga9c4c267ec8ea4df79b0f5affe471ee7b", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE", "a00902.html#ga614b8a54453d52240162efb2118db47f", null ], + [ "MCUX_CSSL_SC_ALLOC", "a00902.html#gae251628d245da18aa3c7aff92dbc8731", null ], + [ "MCUX_CSSL_SC_INIT", "a00902.html#ga25e2c92db2dee1b0cd339d3a8ca4112a", null ], + [ "MCUX_CSSL_SC_CHECK", "a00902.html#ga09971b594be3d77043145756712bd1bb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00903.html b/components/els_pkc/doc/mcxn/html/a00903.html new file mode 100644 index 000000000..54c502064 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00903.html @@ -0,0 +1,285 @@ + + + + + + + +MCUX CLNS: Secure counter increment + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter increment
MCUX CSSL &ndash; API » Secure Counter API
+
+
+ +

Support for incrementing the secure counter. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_ADD(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0x1()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0x10()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0x100()
 Increment the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for incrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_ADD

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD( value)
+
+ +

Increment the secure counter with value.

+
See also
MCUX_CSSL_SC_ADD_0x1
+
+MCUX_CSSL_SC_ADD_0x10
+
+MCUX_CSSL_SC_ADD_0x100
+
+MCUX_CSSL_SC_SUB
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_ON_CALL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD_ON_CALL( value)
+
+ +

Increment the secure counter with value in case of function call.

+
See also
MCUX_CSSL_SC_ADD
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0x1

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0x1()
+
+ +

Increment the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_ADD
+
+MCUX_CSSL_SC_ADD_0x10
+
+MCUX_CSSL_SC_ADD_0x100
+
+MCUX_CSSL_SC_SUB_0x1
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0x10

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0x10()
+
+ +

Increment the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_ADD
+
+MCUX_CSSL_SC_ADD_0x1
+
+MCUX_CSSL_SC_ADD_0x100
+
+MCUX_CSSL_SC_SUB_0x10
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0x100

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0x100()
+
+ +

Increment the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_ADD
+
+MCUX_CSSL_SC_ADD_0x1
+
+MCUX_CSSL_SC_ADD_0x10
+
+MCUX_CSSL_SC_SUB_0x100
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00903.js b/components/els_pkc/doc/mcxn/html/a00903.js new file mode 100644 index 000000000..9449f688d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00903.js @@ -0,0 +1,8 @@ +var a00903 = +[ + [ "MCUX_CSSL_SC_ADD", "a00903.html#gaebd375f1bd8786078a00d2d8326c23aa", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL", "a00903.html#ga4103d92fd5d240d12ace815c84d9d6f1", null ], + [ "MCUX_CSSL_SC_ADD_0x1", "a00903.html#gaca21d031efe80f6dd488932f0e335842", null ], + [ "MCUX_CSSL_SC_ADD_0x10", "a00903.html#gab6aafbee4e72e020907dc9f382ac6b65", null ], + [ "MCUX_CSSL_SC_ADD_0x100", "a00903.html#gaa7340bed15dc7026e9d2a0a9a1464cbf", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00904.html b/components/els_pkc/doc/mcxn/html/a00904.html new file mode 100644 index 000000000..334f1d41f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00904.html @@ -0,0 +1,255 @@ + + + + + + + +MCUX CLNS: Secure counter decrement + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter decrement
MCUX CSSL &ndash; API » Secure Counter API
+
+
+ +

Support for decrementing the secure counter. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_SUB(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0x1()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0x10()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0x100()
 Decrement the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for decrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_SUB

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_SUB( value)
+
+ +

Decrement the secure counter with value.

+
See also
MCUX_CSSL_SC_SUB_0x1
+
+MCUX_CSSL_SC_SUB_0x10
+
+MCUX_CSSL_SC_SUB_0x100
+
+MCUX_CSSL_SC_ADD
+
Parameters
+ + +
valueValue with which the secure counter must be decremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0x1

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0x1()
+
+ +

Decrement the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_SUB
+
+MCUX_CSSL_SC_SUB_0x10
+
+MCUX_CSSL_SC_SUB_0x100
+
+MCUX_CSSL_SC_ADD_0x1
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0x10

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0x10()
+
+ +

Decrement the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_SUB
+
+MCUX_CSSL_SC_SUB_0x1
+
+MCUX_CSSL_SC_SUB_0x100
+
+MCUX_CSSL_SC_ADD_0x10
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0x100

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0x100()
+
+ +

Decrement the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_SUB
+
+MCUX_CSSL_SC_SUB_0x1
+
+MCUX_CSSL_SC_SUB_0x10
+
+MCUX_CSSL_SC_ADD_0x100
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00904.js b/components/els_pkc/doc/mcxn/html/a00904.js new file mode 100644 index 000000000..610ed0cac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00904.js @@ -0,0 +1,7 @@ +var a00904 = +[ + [ "MCUX_CSSL_SC_SUB", "a00904.html#ga270e4467ff02a10df72b1da177385858", null ], + [ "MCUX_CSSL_SC_SUB_0x1", "a00904.html#ga7df8a7a4e7798142da2e668ca21f3a5e", null ], + [ "MCUX_CSSL_SC_SUB_0x10", "a00904.html#gabb6f649421ad8405aa47812615301933", null ], + [ "MCUX_CSSL_SC_SUB_0x100", "a00904.html#gacf7c177e9dbd78d8c5a81fe3b9b4b5cb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00905.html b/components/els_pkc/doc/mcxn/html/a00905.html new file mode 100644 index 000000000..df3f39aba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00905.html @@ -0,0 +1,187 @@ + + + + + + + +MCUX CLNS: Secure counter direct access + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter direct access
MCUX CSSL &ndash; API » Secure Counter API
+
+
+ +

Support for directly accessing the secure counter. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_SC_VALUE()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

Support for directly accessing the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed.
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_VALUE

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_VALUE()
+
+ +

Access operation for the current secure counter value.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed. For portable code it is best to only rely on the check operation to verify the secure counter value.
+
Returns
The current value of the secure counter.
+ +
+
+ +

◆ MCUX_CSSL_SC_ASSIGN

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ASSIGN( value)
+
+ +

Assignment operation for the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic assignment might not be allowed. For portable code it is best to only rely on the initialization, increment and decrement operations to change the secure counter value.
+
Parameters
+ + +
valueValue that needs to be assigned to the secure counter.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00905.js b/components/els_pkc/doc/mcxn/html/a00905.js new file mode 100644 index 000000000..5b77f4ce9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00905.js @@ -0,0 +1,5 @@ +var a00905 = +[ + [ "MCUX_CSSL_SC_VALUE", "a00905.html#ga2b674477b2a4111ad89fd95598c36e69", null ], + [ "MCUX_CSSL_SC_ASSIGN", "a00905.html#ga019087e1fe72c9ef7b1e5f9e19aa7493", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00906.html b/components/els_pkc/doc/mcxn/html/a00906.html new file mode 100644 index 000000000..0434ebe08 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00906.html @@ -0,0 +1,303 @@ + + + + + + + +MCUX CLNS: Secure Counter Configuration + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure Counter Configuration
MCUX CSSL &ndash; Configurations
+
+
+ +

Configuration options for the secure counter mechanism. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG
 If set to 1, use the hybrid secure counter mechanism implementation based on a SW counter stored in a local variable and the code watchdog (CDOG) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_CDOG
 If set to 1, use the secure counter mechanism implementation based on the code watchdog (CDOG) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_SCM
 If set to 1, use the secure counter mechanism implementation based on the subsystem control module (SCM) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_HW_S3SCM
 If set to 1, use the secure counter mechanism implementation based on the subsystem control module (S3SCM) HW IP block. More...
 
#define MCUX_CSSL_SC_USE_SW_LOCAL
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a local variable. More...
 
#define MCUX_CSSL_SC_USE_SW_CONTEXT
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a context structure. More...
 
#define MCUX_CSSL_SC_USE_SW_CALLBACK
 If set to 1, use the secure counter mechanism implementation based on a SW counter pointed to through a callback function. More...
 
#define MCUX_CSSL_SC_USE_SW_GLOBAL
 If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a global variable. More...
 
#define MCUX_CSSL_SC_USE_NONE
 If set to 1, do not use the secure counter mechanism. More...
 
+

Detailed Description

+

Configuration options for the secure counter mechanism.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG
+
+ +

If set to 1, use the hybrid secure counter mechanism implementation based on a SW counter stored in a local variable and the code watchdog (CDOG) HW IP block.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_HW_CDOG

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_HW_CDOG
+
+ +

If set to 1, use the secure counter mechanism implementation based on the code watchdog (CDOG) HW IP block.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_HW_SCM

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_HW_SCM
+
+ +

If set to 1, use the secure counter mechanism implementation based on the subsystem control module (SCM) HW IP block.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_HW_S3SCM

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_HW_S3SCM
+
+ +

If set to 1, use the secure counter mechanism implementation based on the subsystem control module (S3SCM) HW IP block.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_SW_LOCAL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_SW_LOCAL
+
+ +

If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a local variable.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_SW_CONTEXT

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_SW_CONTEXT
+
+ +

If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a context structure.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_SW_CALLBACK

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_SW_CALLBACK
+
+ +

If set to 1, use the secure counter mechanism implementation based on a SW counter pointed to through a callback function.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_SW_GLOBAL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_SW_GLOBAL
+
+ +

If set to 1, use the secure counter mechanism implementation based on a SW counter stored in a global variable.

+ +
+
+ +

◆ MCUX_CSSL_SC_USE_NONE

+ +
+
+ + + + +
#define MCUX_CSSL_SC_USE_NONE
+
+ +

If set to 1, do not use the secure counter mechanism.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00906.js b/components/els_pkc/doc/mcxn/html/a00906.js new file mode 100644 index 000000000..da20be985 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00906.js @@ -0,0 +1,12 @@ +var a00906 = +[ + [ "MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG", "a00906.html#gab32cca78e592e73eb1d15d06be994839", null ], + [ "MCUX_CSSL_SC_USE_HW_CDOG", "a00906.html#gaa488aa67a604f34f36c1a99b07a6ab71", null ], + [ "MCUX_CSSL_SC_USE_HW_SCM", "a00906.html#gae5b47bf9fecd4e15c34cb859cad286a4", null ], + [ "MCUX_CSSL_SC_USE_HW_S3SCM", "a00906.html#gaf65f19a392d0dda41627f1e4ef3f2291", null ], + [ "MCUX_CSSL_SC_USE_SW_LOCAL", "a00906.html#ga841fe66e0a59b9c720854ff0ee2c4678", null ], + [ "MCUX_CSSL_SC_USE_SW_CONTEXT", "a00906.html#gaff2c61772a19bdf2e5038b674ea04128", null ], + [ "MCUX_CSSL_SC_USE_SW_CALLBACK", "a00906.html#ga788677fbf1a036b432007aa84a2879ad", null ], + [ "MCUX_CSSL_SC_USE_SW_GLOBAL", "a00906.html#ga8743f66cbadb2592671510ed3160dc09", null ], + [ "MCUX_CSSL_SC_USE_NONE", "a00906.html#ga8141a2d6da07d7137207fb35505a6cb0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00907.html b/components/els_pkc/doc/mcxn/html/a00907.html new file mode 100644 index 000000000..4ae1fade7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00907.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Secure Counter: Disabled + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Secure Counter: Disabled
MCUX CSSL &ndash; Implementations
+
+
+ +

Disable the secure counter mechanism. +More...

+ + + + + + + + + + + + + + +

+Modules

 Secure counter core functionality
 Secure counter handling core functionality.
 
 Secure counter increment
 Support for incrementing the secure counter.
 
 Secure counter decrement
 Support for decrementing the secure counter.
 
 Secure counter direct access
 Support for directly accessing the secure counter.
 
+

Detailed Description

+

Disable the secure counter mechanism.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00907.js b/components/els_pkc/doc/mcxn/html/a00907.js new file mode 100644 index 000000000..8d87d8108 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00907.js @@ -0,0 +1,7 @@ +var a00907 = +[ + [ "Secure counter core functionality", "a00908.html", "a00908" ], + [ "Secure counter increment", "a00909.html", "a00909" ], + [ "Secure counter decrement", "a00910.html", "a00910" ], + [ "Secure counter direct access", "a00911.html", "a00911" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00908.html b/components/els_pkc/doc/mcxn/html/a00908.html new file mode 100644 index 000000000..801408e4b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00908.html @@ -0,0 +1,308 @@ + + + + + + + +MCUX CLNS: Secure counter core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter core functionality
MCUX CSSL &ndash; Implementations » Secure Counter: Disabled
+
+
+ +

Secure counter handling core functionality. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
 Data type used for the secure counter. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
 Data type used for properly casting the secure counter balancing values. More...
 
#define MCUX_CSSL_SC_ALLOC_IMPL()
 Allocation operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT_IMPL(value)
 Initialization operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK_IMPL(value)
 Comparison operation implementation for the secure counter. More...
 
+

Detailed Description

+

Secure counter handling core functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_CHECK_PASSED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
+
+ +

Positive comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_FAILED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
+
+ +

Negative comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_COUNTER_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
+
+ +

Data type used for the secure counter.

+ +
+
+ +

◆ MCUX_CSSL_SC_VALUE_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
+
+ +

Data type used for the secure counter values.

+ +
+
+ +

◆ MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
+
+ +

Data type used for properly casting the secure counter balancing values.

+ +
+
+ +

◆ MCUX_CSSL_SC_ALLOC_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ALLOC_IMPL()
+
+ +

Allocation operation implementation for the secure counter.

+ +
+
+ +

◆ MCUX_CSSL_SC_INIT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_INIT_IMPL( value)
+
+ +

Initialization operation implementation for the secure counter.

+
Parameters
+ + +
valueValue with which the secure counter must be initialized.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_CHECK_IMPL( value)
+
+ +

Comparison operation implementation for the secure counter.

+
Parameters
+ + +
referenceReference value to compare the secure counter value against.
+
+
+
Returns
Always MCUX_CSSL_SC_CHECK_PASSED.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00908.js b/components/els_pkc/doc/mcxn/html/a00908.js new file mode 100644 index 000000000..9b0886426 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00908.js @@ -0,0 +1,11 @@ +var a00908 = +[ + [ "MCUX_CSSL_SC_CHECK_PASSED_IMPL", "a00908.html#ga417202932e9a8a880e23e8a3321309ac", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED_IMPL", "a00908.html#gac1d032d150bd774f86bbb50fdfa0ee19", null ], + [ "MCUX_CSSL_SC_COUNTER_TYPE_IMPL", "a00908.html#gaafa4d13a4e311121551b8e49662c3470", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE_IMPL", "a00908.html#gaf84485a6eb6bbcd39933ff1abcb3ee61", null ], + [ "MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL", "a00908.html#ga919150430f3033eb5d6c8025216548b3", null ], + [ "MCUX_CSSL_SC_ALLOC_IMPL", "a00908.html#gad413de64b4cc420be30b5278fd5083d0", null ], + [ "MCUX_CSSL_SC_INIT_IMPL", "a00908.html#gaf8d9ebeb36322ea86fc8766afa84bc3f", null ], + [ "MCUX_CSSL_SC_CHECK_IMPL", "a00908.html#gaf15120a3e9f4edf59cb5b42860fe86dd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00909.html b/components/els_pkc/doc/mcxn/html/a00909.html new file mode 100644 index 000000000..4a6ff9958 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00909.html @@ -0,0 +1,261 @@ + + + + + + + +MCUX CLNS: Secure counter increment + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter increment
MCUX CSSL &ndash; Implementations » Secure Counter: Disabled
+
+
+ +

Support for incrementing the secure counter. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_ADD_IMPL(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
 Increment the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for incrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_ADD_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD_IMPL( value)
+
+ +

Increment the secure counter with value.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_ON_CALL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL( value)
+
+ +

Increment the secure counter with value in case of function call.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X1_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
+
+ +

Increment the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X10_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
+
+ +

Increment the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X100_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
+
+ +

Increment the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00909.js b/components/els_pkc/doc/mcxn/html/a00909.js new file mode 100644 index 000000000..1a376c538 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00909.js @@ -0,0 +1,8 @@ +var a00909 = +[ + [ "MCUX_CSSL_SC_ADD_IMPL", "a00909.html#gaa4a21360f6c3d08fc777879e4f4551ed", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL_IMPL", "a00909.html#ga9c0484fdff900c04462d668a0870bf33", null ], + [ "MCUX_CSSL_SC_ADD_0X1_IMPL", "a00909.html#ga45a909bcf29531036b1aad68ac8b0afb", null ], + [ "MCUX_CSSL_SC_ADD_0X10_IMPL", "a00909.html#gaac716380d3c29a995745053bb6915044", null ], + [ "MCUX_CSSL_SC_ADD_0X100_IMPL", "a00909.html#gafb5fa6d42145120126b00ab3707711be", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00910.html b/components/els_pkc/doc/mcxn/html/a00910.html new file mode 100644 index 000000000..ae4f21daf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00910.html @@ -0,0 +1,231 @@ + + + + + + + +MCUX CLNS: Secure counter decrement + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter decrement
MCUX CSSL &ndash; Implementations » Secure Counter: Disabled
+
+
+ +

Support for decrementing the secure counter. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_SUB_IMPL(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
 Decrement the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for decrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_SUB_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_SUB_IMPL( value)
+
+ +

Decrement the secure counter with value.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be decremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X1_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
+
+ +

Decrement the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X10_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
+
+ +

Decrement the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X100_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
+
+ +

Decrement the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00910.js b/components/els_pkc/doc/mcxn/html/a00910.js new file mode 100644 index 000000000..a8ce6e319 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00910.js @@ -0,0 +1,7 @@ +var a00910 = +[ + [ "MCUX_CSSL_SC_SUB_IMPL", "a00910.html#gaca0635e01e8eef97f9a06a50b24d0941", null ], + [ "MCUX_CSSL_SC_SUB_0X1_IMPL", "a00910.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8", null ], + [ "MCUX_CSSL_SC_SUB_0X10_IMPL", "a00910.html#gafa9701e3c0f7e757573c4bfcdae22959", null ], + [ "MCUX_CSSL_SC_SUB_0X100_IMPL", "a00910.html#gaa4a6dba75f476d29637e005dc8272083", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00911.html b/components/els_pkc/doc/mcxn/html/a00911.html new file mode 100644 index 000000000..3022ed5ac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00911.html @@ -0,0 +1,187 @@ + + + + + + + +MCUX CLNS: Secure counter direct access + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter direct access
MCUX CSSL &ndash; Implementations » Secure Counter: Disabled
+
+
+ +

Support for directly accessing the secure counter. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_SC_VALUE_IMPL()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN_IMPL(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

Support for directly accessing the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed.
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_VALUE_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_VALUE_IMPL()
+
+ +

Access operation for the current secure counter value.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed. For portable code it is best to only rely on the check operation to verify the secure counter value.
+
Returns
The current value of the secure counter.
+ +
+
+ +

◆ MCUX_CSSL_SC_ASSIGN_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ASSIGN_IMPL( value)
+
+ +

Assignment operation for the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic assignment might not be allowed. For portable code it is best to only rely on the initialization, increment and decrement operations to change the secure counter value.
+
Parameters
+ + +
valueValue that needs to be assigned to the secure counter.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00911.js b/components/els_pkc/doc/mcxn/html/a00911.js new file mode 100644 index 000000000..39984a8e6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00911.js @@ -0,0 +1,5 @@ +var a00911 = +[ + [ "MCUX_CSSL_SC_VALUE_IMPL", "a00911.html#ga5ebadc1cc4cc3e849527adcf3da5c258", null ], + [ "MCUX_CSSL_SC_ASSIGN_IMPL", "a00911.html#ga87e741e67b757bf719409530176e56b9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00912.html b/components/els_pkc/doc/mcxn/html/a00912.html new file mode 100644 index 000000000..e563ff929 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00912.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Secure Counter: SW Local + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Secure Counter: SW Local
MCUX CSSL &ndash; Implementations
+
+
+ +

Secure counter mechanism implementation using a local variable. +More...

+ + + + + + + + + + + + + + +

+Modules

 Secure counter core functionality
 Secure counter handling core functionality.
 
 Secure counter increment
 Support for incrementing the secure counter.
 
 Secure counter decrement
 Support for decrementing the secure counter.
 
 Secure counter direct access
 Support for directly accessing the secure counter.
 
+

Detailed Description

+

Secure counter mechanism implementation using a local variable.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00912.js b/components/els_pkc/doc/mcxn/html/a00912.js new file mode 100644 index 000000000..b379970a5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00912.js @@ -0,0 +1,7 @@ +var a00912 = +[ + [ "Secure counter core functionality", "a00913.html", "a00913" ], + [ "Secure counter increment", "a00914.html", "a00914" ], + [ "Secure counter decrement", "a00915.html", "a00915" ], + [ "Secure counter direct access", "a00916.html", "a00916" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00913.html b/components/els_pkc/doc/mcxn/html/a00913.html new file mode 100644 index 000000000..1d7c89d33 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00913.html @@ -0,0 +1,327 @@ + + + + + + + +MCUX CLNS: Secure counter core functionality + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter core functionality
MCUX CSSL &ndash; Implementations » Secure Counter: SW Local
+
+
+ +

Secure counter handling core functionality. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_COUNTER_NAME
 Variable name to use for storing the secure counter value. More...
 
#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
 Positive comparison result value. More...
 
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
 Negative comparison result value. More...
 
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
 Data type used for the secure counter. More...
 
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
 Data type used for the secure counter values. More...
 
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
 Data type used for properly casting the secure counter balancing values. More...
 
#define MCUX_CSSL_SC_ALLOC_IMPL()
 Allocation operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_INIT_IMPL(value)
 Initialization operation implementation for the secure counter. More...
 
#define MCUX_CSSL_SC_CHECK_IMPL(value)
 Comparison operation implementation for the secure counter. More...
 
+

Detailed Description

+

Secure counter handling core functionality.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_COUNTER_NAME

+ +
+
+ + + + +
#define MCUX_CSSL_SC_COUNTER_NAME
+
+ +

Variable name to use for storing the secure counter value.

+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_PASSED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_PASSED_IMPL
+
+ +

Positive comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_FAILED_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_CHECK_FAILED_IMPL
+
+ +

Negative comparison result value.

+ +
+
+ +

◆ MCUX_CSSL_SC_COUNTER_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL
+
+ +

Data type used for the secure counter.

+ +
+
+ +

◆ MCUX_CSSL_SC_VALUE_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_VALUE_TYPE_IMPL
+
+ +

Data type used for the secure counter values.

+ +
+
+ +

◆ MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL

+ +
+
+ + + + +
#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL
+
+ +

Data type used for properly casting the secure counter balancing values.

+ +
+
+ +

◆ MCUX_CSSL_SC_ALLOC_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ALLOC_IMPL()
+
+ +

Allocation operation implementation for the secure counter.

+ +
+
+ +

◆ MCUX_CSSL_SC_INIT_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_INIT_IMPL( value)
+
+ +

Initialization operation implementation for the secure counter.

+
Parameters
+ + +
valueValue with which the secure counter must be initialized.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_CHECK_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_CHECK_IMPL( value)
+
+ +

Comparison operation implementation for the secure counter.

+
Parameters
+ + +
valueReference value to compare the secure counter value against.
+
+
+
Returns
Either MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or MCUX_CSSL_SC_CHECK_FAILED if the value is different.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00913.js b/components/els_pkc/doc/mcxn/html/a00913.js new file mode 100644 index 000000000..8426f00ea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00913.js @@ -0,0 +1,12 @@ +var a00913 = +[ + [ "MCUX_CSSL_SC_COUNTER_NAME", "a00913.html#ga7cf637fa768fe3fe088dbf367ad46b8a", null ], + [ "MCUX_CSSL_SC_CHECK_PASSED_IMPL", "a00913.html#ga417202932e9a8a880e23e8a3321309ac", null ], + [ "MCUX_CSSL_SC_CHECK_FAILED_IMPL", "a00913.html#gac1d032d150bd774f86bbb50fdfa0ee19", null ], + [ "MCUX_CSSL_SC_COUNTER_TYPE_IMPL", "a00913.html#gaafa4d13a4e311121551b8e49662c3470", null ], + [ "MCUX_CSSL_SC_VALUE_TYPE_IMPL", "a00913.html#gaf84485a6eb6bbcd39933ff1abcb3ee61", null ], + [ "MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL", "a00913.html#ga919150430f3033eb5d6c8025216548b3", null ], + [ "MCUX_CSSL_SC_ALLOC_IMPL", "a00913.html#gad413de64b4cc420be30b5278fd5083d0", null ], + [ "MCUX_CSSL_SC_INIT_IMPL", "a00913.html#gaf8d9ebeb36322ea86fc8766afa84bc3f", null ], + [ "MCUX_CSSL_SC_CHECK_IMPL", "a00913.html#gaf15120a3e9f4edf59cb5b42860fe86dd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00914.html b/components/els_pkc/doc/mcxn/html/a00914.html new file mode 100644 index 000000000..caeebf857 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00914.html @@ -0,0 +1,261 @@ + + + + + + + +MCUX CLNS: Secure counter increment + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter increment
MCUX CSSL &ndash; Implementations » Secure Counter: SW Local
+
+
+ +

Support for incrementing the secure counter. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_ADD_IMPL(value)
 Increment the secure counter with value. More...
 
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value)
 Increment the secure counter with value in case of function call. More...
 
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
 Increment the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
 Increment the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
 Increment the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for incrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_ADD_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD_IMPL( value)
+
+ +

Increment the secure counter with value.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_ON_CALL_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL( value)
+
+ +

Increment the secure counter with value in case of function call.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be incremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X1_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X1_IMPL()
+
+ +

Increment the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X10_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X10_IMPL()
+
+ +

Increment the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_ADD_0X100_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_ADD_0X100_IMPL()
+
+ +

Increment the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00914.js b/components/els_pkc/doc/mcxn/html/a00914.js new file mode 100644 index 000000000..79fe1210f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00914.js @@ -0,0 +1,8 @@ +var a00914 = +[ + [ "MCUX_CSSL_SC_ADD_IMPL", "a00914.html#gaa4a21360f6c3d08fc777879e4f4551ed", null ], + [ "MCUX_CSSL_SC_ADD_ON_CALL_IMPL", "a00914.html#ga9c0484fdff900c04462d668a0870bf33", null ], + [ "MCUX_CSSL_SC_ADD_0X1_IMPL", "a00914.html#ga45a909bcf29531036b1aad68ac8b0afb", null ], + [ "MCUX_CSSL_SC_ADD_0X10_IMPL", "a00914.html#gaac716380d3c29a995745053bb6915044", null ], + [ "MCUX_CSSL_SC_ADD_0X100_IMPL", "a00914.html#gafb5fa6d42145120126b00ab3707711be", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00915.html b/components/els_pkc/doc/mcxn/html/a00915.html new file mode 100644 index 000000000..526797f6d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00915.html @@ -0,0 +1,231 @@ + + + + + + + +MCUX CLNS: Secure counter decrement + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter decrement
MCUX CSSL &ndash; Implementations » Secure Counter: SW Local
+
+
+ +

Support for decrementing the secure counter. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUX_CSSL_SC_SUB_IMPL(value)
 Decrement the secure counter with value. More...
 
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
 Decrement the secure counter with 0x1. More...
 
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
 Decrement the secure counter with 0x10. More...
 
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
 Decrement the secure counter with 0x100. More...
 
+

Detailed Description

+

Support for decrementing the secure counter.

+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_SUB_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_SUB_IMPL( value)
+
+ +

Decrement the secure counter with value.

+
See also
MCUX_CSSL_SC_ADD_IMPL
+
Parameters
+ + +
valueValue with which the secure counter must be decremented.
+
+
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X1_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X1_IMPL()
+
+ +

Decrement the secure counter with 0x1.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X10_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X10_IMPL()
+
+ +

Decrement the secure counter with 0x10.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+ +

◆ MCUX_CSSL_SC_SUB_0X100_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_SUB_0X100_IMPL()
+
+ +

Decrement the secure counter with 0x100.

+
See also
MCUX_CSSL_SC_SUB_IMPL
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00915.js b/components/els_pkc/doc/mcxn/html/a00915.js new file mode 100644 index 000000000..5a0f71414 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00915.js @@ -0,0 +1,7 @@ +var a00915 = +[ + [ "MCUX_CSSL_SC_SUB_IMPL", "a00915.html#gaca0635e01e8eef97f9a06a50b24d0941", null ], + [ "MCUX_CSSL_SC_SUB_0X1_IMPL", "a00915.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8", null ], + [ "MCUX_CSSL_SC_SUB_0X10_IMPL", "a00915.html#gafa9701e3c0f7e757573c4bfcdae22959", null ], + [ "MCUX_CSSL_SC_SUB_0X100_IMPL", "a00915.html#gaa4a6dba75f476d29637e005dc8272083", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00916.html b/components/els_pkc/doc/mcxn/html/a00916.html new file mode 100644 index 000000000..b62b15d10 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00916.html @@ -0,0 +1,187 @@ + + + + + + + +MCUX CLNS: Secure counter direct access + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Secure counter direct access
MCUX CSSL &ndash; Implementations » Secure Counter: SW Local
+
+
+ +

Support for directly accessing the secure counter. +More...

+ + + + + + + + +

+Macros

#define MCUX_CSSL_SC_VALUE_IMPL()
 Access operation for the current secure counter value. More...
 
#define MCUX_CSSL_SC_ASSIGN_IMPL(value)
 Assignment operation for the secure counter. More...
 
+

Detailed Description

+

Support for directly accessing the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed.
+

Macro Definition Documentation

+ +

◆ MCUX_CSSL_SC_VALUE_IMPL

+ +
+
+ + + + + + + +
#define MCUX_CSSL_SC_VALUE_IMPL()
+
+ +

Access operation for the current secure counter value.

+
Warning
Access to the secure counter is generally restricted, and generic access might not be allowed. For portable code it is best to only rely on the check operation to verify the secure counter value.
+
Returns
The current value of the secure counter.
+ +
+
+ +

◆ MCUX_CSSL_SC_ASSIGN_IMPL

+ +
+
+ + + + + + + + +
#define MCUX_CSSL_SC_ASSIGN_IMPL( value)
+
+ +

Assignment operation for the secure counter.

+
Warning
Access to the secure counter is generally restricted, and generic assignment might not be allowed. For portable code it is best to only rely on the initialization, increment and decrement operations to change the secure counter value.
+
Parameters
+ + +
valueValue that needs to be assigned to the secure counter.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00916.js b/components/els_pkc/doc/mcxn/html/a00916.js new file mode 100644 index 000000000..71327f7b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00916.js @@ -0,0 +1,5 @@ +var a00916 = +[ + [ "MCUX_CSSL_SC_VALUE_IMPL", "a00916.html#ga5ebadc1cc4cc3e849527adcf3da5c258", null ], + [ "MCUX_CSSL_SC_ASSIGN_IMPL", "a00916.html#ga87e741e67b757bf719409530176e56b9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00917.html b/components/els_pkc/doc/mcxn/html/a00917.html new file mode 100644 index 000000000..799637c40 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00917.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: Core API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Core API
MCUX CL &ndash; API
+
+
+ +

Essential types and functionality. +More...

+ + + + + +

+Modules

 Core type definitions
 Types used by basically all operations.
 
+

Detailed Description

+

Essential types and functionality.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00917.js b/components/els_pkc/doc/mcxn/html/a00917.js new file mode 100644 index 000000000..e485689fb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00917.js @@ -0,0 +1,4 @@ +var a00917 = +[ + [ "Core type definitions", "a00678.html", "a00678" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00918.html b/components/els_pkc/doc/mcxn/html/a00918.html new file mode 100644 index 000000000..43761feba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00918.html @@ -0,0 +1,238 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WACPU_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WACPU_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the CPU workarea size required by mcuxClEcc APIs. +More...

+ + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_ALIGN_SIZE_CPU(byteLen)
 
#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN)
 CPU workarea size (in bytes) for mcuxClEcc_KeyGen. Parameter byteLenN is just to keep the API consistent. More...
 
#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN)
 CPU workarea size (in bytes) for mcuxClEcc_Sign. Parameter byteLenN is just to keep the API consistent. More...
 
#define MCUXCLECC_VERIFY_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Verify. More...
 
#define MCUXCLECC_POINTMULT_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_PointMult. More...
 
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams. More...
 
+

Detailed Description

+

Define the CPU workarea size required by mcuxClEcc APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_KEYGEN_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLECC_KEYGEN_WACPU_SIZE( byteLenN)
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_KeyGen. Parameter byteLenN is just to keep the API consistent.

+ +
+
+ +

◆ MCUXCLECC_SIGN_WACPU_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLECC_SIGN_WACPU_SIZE( byteLenN)
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Sign. Parameter byteLenN is just to keep the API consistent.

+ +
+
+ +

◆ MCUXCLECC_VERIFY_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_VERIFY_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Verify.

+ +
+
+ +

◆ MCUXCLECC_POINTMULT_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_POINTMULT_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_PointMult.

+ +
+
+ +

◆ MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00918.js b/components/els_pkc/doc/mcxn/html/a00918.js new file mode 100644 index 000000000..6972939dd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00918.js @@ -0,0 +1,8 @@ +var a00918 = +[ + [ "MCUXCLECC_KEYGEN_WACPU_SIZE", "a00918.html#ga0fdfb866390f13e869a59e859da3866e", null ], + [ "MCUXCLECC_SIGN_WACPU_SIZE", "a00918.html#gabe6907845de629a54b0eae63da78d099", null ], + [ "MCUXCLECC_VERIFY_WACPU_SIZE", "a00918.html#ga77a772614cead92da188f20009bc24b5", null ], + [ "MCUXCLECC_POINTMULT_WACPU_SIZE", "a00918.html#ga46349810877e3b79a8d899648e1b2e06", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE", "a00918.html#ga29e85a389cf38d61196691fc4f3a35f1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00919.html b/components/els_pkc/doc/mcxn/html/a00919.html new file mode 100644 index 000000000..20a0db486 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00919.html @@ -0,0 +1,208 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_MONTDH_WACPU_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_MONTDH_WACPU_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the CPU workarea size required by mcuxClEcc MontDH APIs. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration. More...
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement. More...
 
+

Detailed Description

+

Define the CPU workarea size required by mcuxClEcc MontDH APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00919.js b/components/els_pkc/doc/mcxn/html/a00919.js new file mode 100644 index 000000000..d01588223 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00919.js @@ -0,0 +1,7 @@ +var a00919 = +[ + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE", "a00919.html#ga89090994d784943f6c0ff6858600a5c8", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE", "a00919.html#gaf968453d3c749fe1e2a79b10877e8c9b", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE", "a00919.html#gaaf4bad03752e8903fc972548c27b40a3", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE", "a00919.html#ga8051604c81692c541171eb8693eb0ebe", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00920.html b/components/els_pkc/doc/mcxn/html/a00920.html new file mode 100644 index 000000000..6079ca8ea --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00920.html @@ -0,0 +1,246 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_WACPU_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_WACPU_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the CPU workarea size required by mcuxClEcc EdDSA APIs. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed25519. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed25519. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE
 CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448. More...
 
+

Detailed Description

+

Define the CPU workarea size required by mcuxClEcc EdDSA APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE
+
+ +

CPU workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00920.js b/components/els_pkc/doc/mcxn/html/a00920.js new file mode 100644 index 000000000..958ac6c09 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00920.js @@ -0,0 +1,9 @@ +var a00920 = +[ + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE", "a00920.html#ga647bd322f94b65acba45b872cacf5ba8", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE", "a00920.html#gad7ee128279d1230a6f0dee32093e4dc0", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE", "a00920.html#ga9ec654b676b4d3e3ccdda604ba55e5ed", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE", "a00920.html#ga86d2a91a15fd9c10989b363bcd9ab6af", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE", "a00920.html#gaf1baa23b5fa695897dade1e24bd60881", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE", "a00920.html#gaeb4fa934c84d576b93c321b436af5ccd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00921.html b/components/els_pkc/doc/mcxn/html/a00921.html new file mode 100644 index 000000000..77f318b10 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00921.html @@ -0,0 +1,387 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WAPKC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WAPKC_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the PKC workarea size required by mcuxClEcc APIs. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_PKC_WORDSIZE
 PKC wordsize in ECC component. More...
 
#define MCUXCLECC_MAX(value0, value1)
 Helper macro to get the maximum of two given constants. More...
 
#define MCUXCLECC_ALIGN_SIZE_PKC(size)
 Helper macro to calculate size aligned to PKC word. More...
 
#define MCUXCLECC_KEYGEN_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_KeyGen for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_SIGN_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_Sign for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_VERIFY_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_Verify for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_POINTMULT_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_PointMult for arbitrary lengths of p and n. More...
 
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(pByteLen, nByteLen)
 PKC workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams for arbitrary lengths of p and n. More...
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_128
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_256
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_384
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_512
 
+#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_640
 
+

Detailed Description

+

Define the PKC workarea size required by mcuxClEcc APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_PKC_WORDSIZE

+ +
+
+ + + + +
#define MCUXCLECC_PKC_WORDSIZE
+
+ +

PKC wordsize in ECC component.

+ +
+
+ +

◆ MCUXCLECC_MAX

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_MAX( value0,
 value1 
)
+
+ +

Helper macro to get the maximum of two given constants.

+ +
+
+ +

◆ MCUXCLECC_ALIGN_SIZE_PKC

+ +
+
+ + + + + + + + +
#define MCUXCLECC_ALIGN_SIZE_PKC( size)
+
+ +

Helper macro to calculate size aligned to PKC word.

+ +
+
+ +

◆ MCUXCLECC_KEYGEN_WAPKC_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_KEYGEN_WAPKC_SIZE( pByteLen,
 nByteLen 
)
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_KeyGen for arbitrary lengths of p and n.

+ +
+
+ +

◆ MCUXCLECC_SIGN_WAPKC_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_SIGN_WAPKC_SIZE( pByteLen,
 nByteLen 
)
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Sign for arbitrary lengths of p and n.

+ +
+
+ +

◆ MCUXCLECC_VERIFY_WAPKC_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_VERIFY_WAPKC_SIZE( pByteLen,
 nByteLen 
)
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Verify for arbitrary lengths of p and n.

+ +
+
+ +

◆ MCUXCLECC_POINTMULT_WAPKC_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_POINTMULT_WAPKC_SIZE( pByteLen,
 nByteLen 
)
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_PointMult for arbitrary lengths of p and n.

+ +
+
+ +

◆ MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE( pByteLen,
 nByteLen 
)
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_WeierECC_GenerateDomainParams for arbitrary lengths of p and n.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00921.js b/components/els_pkc/doc/mcxn/html/a00921.js new file mode 100644 index 000000000..caffcbd10 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00921.js @@ -0,0 +1,11 @@ +var a00921 = +[ + [ "MCUXCLECC_PKC_WORDSIZE", "a00921.html#ga636a89c09b2210ea78da464825e4bf99", null ], + [ "MCUXCLECC_MAX", "a00921.html#gaf74ecb9246e198a6078c55c48ddf479e", null ], + [ "MCUXCLECC_ALIGN_SIZE_PKC", "a00921.html#gac836b17e161566b045beb35f53828d1b", null ], + [ "MCUXCLECC_KEYGEN_WAPKC_SIZE", "a00921.html#ga7e26bba72c6eefd7f91907d0df33f17b", null ], + [ "MCUXCLECC_SIGN_WAPKC_SIZE", "a00921.html#ga3574ac0f7b7b9b6d17003263fc47c6c0", null ], + [ "MCUXCLECC_VERIFY_WAPKC_SIZE", "a00921.html#gab4cdcbfb78c215dbee9ff06dc2955034", null ], + [ "MCUXCLECC_POINTMULT_WAPKC_SIZE", "a00921.html#ga36cab670f924640163fc1b02bb753792", null ], + [ "MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE", "a00921.html#gad8881999c0f76cfb55a70d953fb979da", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00922.html b/components/els_pkc/doc/mcxn/html/a00922.html new file mode 100644 index 000000000..a4e772fe3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00922.html @@ -0,0 +1,208 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_MONTDH_WAPKC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_MONTDH_WAPKC_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the PKC workarea size required by mcuxClEcc_Mont APIs. +More...

+ + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve25519. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve25519. More...
 
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve448. More...
 
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve448. More...
 
+

Detailed Description

+

Define the PKC workarea size required by mcuxClEcc_Mont APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve25519.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve25519.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyGeneration for Curve448.

+ +
+
+ +

◆ MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_Mont_DhKeyAgreement for Curve448.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00922.js b/components/els_pkc/doc/mcxn/html/a00922.js new file mode 100644 index 000000000..4e06e94f2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00922.js @@ -0,0 +1,7 @@ +var a00922 = +[ + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE", "a00922.html#gae36dff0de90c37f30b946bf2788b8c50", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE", "a00922.html#gab8a50884589fb6a8e9c3a27176a98f17", null ], + [ "MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE", "a00922.html#ga10eb15479cf16f2bbe6834d0dce7480b", null ], + [ "MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE", "a00922.html#ga42aed746692f49fa0a4e27f5b3f5d743", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00923.html b/components/els_pkc/doc/mcxn/html/a00923.html new file mode 100644 index 000000000..caf38ec62 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00923.html @@ -0,0 +1,249 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_WAPKC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_WAPKC_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define the PKC workarea size required by mcuxClEcc EdDSA APIs. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair. More...
 
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature. More...
 
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature. More...
 
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE
 PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448. More...
 
+

Detailed Description

+

Define the PKC workarea size required by mcuxClEcc EdDSA APIs.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair.

+

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateKeyPair for Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature.

+

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_GenerateSignature for Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature.

+

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE
+
+ +

PKC workarea size (in bytes) for mcuxClEcc_EdDSA_VerifySignature for Ed448.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00923.js b/components/els_pkc/doc/mcxn/html/a00923.js new file mode 100644 index 000000000..e62e31467 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00923.js @@ -0,0 +1,9 @@ +var a00923 = +[ + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE", "a00923.html#ga6584fe2b7bc2e31a739cfb453fd2a9e6", null ], + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE", "a00923.html#ga4dd4582e5d6cdec3e4537a3447281348", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE", "a00923.html#ga0e082808f23a46021d65be49224fef54", null ], + [ "MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE", "a00923.html#gaca347a8466c7addee0aa63eb112fcb72", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE", "a00923.html#ga1a0b00eab2150578dc7afc98f8e82f2a", null ], + [ "MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE", "a00923.html#gad04926b8f100205fb4726200c825e1f6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00924.html b/components/els_pkc/doc/mcxn/html/a00924.html new file mode 100644 index 000000000..2cfae42bc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00924.html @@ -0,0 +1,153 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define for the EdDSA key pair generation descriptor size. +More...

+ + + + + +

+Macros

#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE
 EdDSA key pair generation descriptor size. More...
 
+

Detailed Description

+

Define for the EdDSA key pair generation descriptor size.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE
+
+ +

EdDSA key pair generation descriptor size.

+
Examples
mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00924.js b/components/els_pkc/doc/mcxn/html/a00924.js new file mode 100644 index 000000000..e4bb4cf35 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00924.js @@ -0,0 +1,4 @@ +var a00924 = +[ + [ "MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE", "a00924.html#ga435b584a2a74e53c5987727a938aa65d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00925.html b/components/els_pkc/doc/mcxn/html/a00925.html new file mode 100644 index 000000000..f16ad26b2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00925.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_
mcuxClEcc » mcuxClEcc_MemoryConsumption
+
+
+ +

Define for the EdDSA signature protocol descriptor size. +More...

+ + + + + +

+Macros

#define MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE
 EdDSA signature generation descriptor size. More...
 
+

Detailed Description

+

Define for the EdDSA signature protocol descriptor size.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE
+
+ +

EdDSA signature generation descriptor size.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00925.js b/components/els_pkc/doc/mcxn/html/a00925.js new file mode 100644 index 000000000..bbd8421f3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00925.js @@ -0,0 +1,4 @@ +var a00925 = +[ + [ "MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE", "a00925.html#ga045352e805adba9dfc25b087371872a6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00926.html b/components/els_pkc/doc/mcxn/html/a00926.html new file mode 100644 index 000000000..a00af76f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00926.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_MONT_CURVE25519_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_MONT_CURVE25519_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

MontDH parameter size definitions for Curve25519. +More...

+ + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY
 
+#define MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET
 
+

Detailed Description

+

MontDH parameter size definitions for Curve25519.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00927.html b/components/els_pkc/doc/mcxn/html/a00927.html new file mode 100644 index 000000000..a1ec0bb17 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00927.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_MONT_CURVE448_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_MONT_CURVE448_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

MontDH parameter size definitions for Curve448. +More...

+ + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY
 
+#define MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET
 
+

Detailed Description

+

MontDH parameter size definitions for Curve448.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00928.html b/components/els_pkc/doc/mcxn/html/a00928.html new file mode 100644 index 000000000..5bd1bfb70 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00928.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP160K1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP160K1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp160k1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp160k1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00929.html b/components/els_pkc/doc/mcxn/html/a00929.html new file mode 100644 index 000000000..48e1dabad --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00929.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP192K1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP192K1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp192k1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp192k1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00930.html b/components/els_pkc/doc/mcxn/html/a00930.html new file mode 100644 index 000000000..f39fe3000 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00930.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP224K1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP224K1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp224k1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp224k1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00931.html b/components/els_pkc/doc/mcxn/html/a00931.html new file mode 100644 index 000000000..e15c0a939 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00931.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP256K1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP256K1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp256k1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp256k1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00932.html b/components/els_pkc/doc/mcxn/html/a00932.html new file mode 100644 index 000000000..ec405c0fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00932.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP192R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP192R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp192r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp192r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00933.html b/components/els_pkc/doc/mcxn/html/a00933.html new file mode 100644 index 000000000..f9e25ea40 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00933.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP224R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP224R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp224r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp224r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00934.html b/components/els_pkc/doc/mcxn/html/a00934.html new file mode 100644 index 000000000..044bfd1b4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00934.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP256R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP256R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp256r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp256r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00935.html b/components/els_pkc/doc/mcxn/html/a00935.html new file mode 100644 index 000000000..f97ff0c6d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00935.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP384R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP384R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp384r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp384r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00936.html b/components/els_pkc/doc/mcxn/html/a00936.html new file mode 100644 index 000000000..1b2543234 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00936.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_SECP521R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_SECP521R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for secp521r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for secp521r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00937.html b/components/els_pkc/doc/mcxn/html/a00937.html new file mode 100644 index 000000000..53cdd1969 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00937.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_NIST_P192_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_NIST_P192_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for NIST P-192. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for NIST P-192.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00938.html b/components/els_pkc/doc/mcxn/html/a00938.html new file mode 100644 index 000000000..66d47da13 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00938.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_NIST_P224_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_NIST_P224_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for NIST P-224. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for NIST P-224.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00939.html b/components/els_pkc/doc/mcxn/html/a00939.html new file mode 100644 index 000000000..50e26f52f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00939.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_NIST_P256_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_NIST_P256_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for NIST P-256. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for NIST P-256.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00940.html b/components/els_pkc/doc/mcxn/html/a00940.html new file mode 100644 index 000000000..34f3e08ec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00940.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_NIST_P384_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_NIST_P384_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for NIST P-384. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for NIST P-384.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00941.html b/components/els_pkc/doc/mcxn/html/a00941.html new file mode 100644 index 000000000..3ed1b1515 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00941.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_NIST_P521_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_NIST_P521_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for NIST P-521. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for NIST P-521.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00942.html b/components/els_pkc/doc/mcxn/html/a00942.html new file mode 100644 index 000000000..95a3f9cf7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00942.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP160r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP160r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00943.html b/components/els_pkc/doc/mcxn/html/a00943.html new file mode 100644 index 000000000..9e18aaaef --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00943.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP192r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP192r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00944.html b/components/els_pkc/doc/mcxn/html/a00944.html new file mode 100644 index 000000000..74ed64c95 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00944.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP224r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP224r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00945.html b/components/els_pkc/doc/mcxn/html/a00945.html new file mode 100644 index 000000000..5efb860f5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00945.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP256r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP256r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00946.html b/components/els_pkc/doc/mcxn/html/a00946.html new file mode 100644 index 000000000..25afcc313 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00946.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP320r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP320r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00947.html b/components/els_pkc/doc/mcxn/html/a00947.html new file mode 100644 index 000000000..5c0803bb6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00947.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP384r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP384r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00948.html b/components/els_pkc/doc/mcxn/html/a00948.html new file mode 100644 index 000000000..619c4ad6e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00948.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP512r1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP512r1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00949.html b/components/els_pkc/doc/mcxn/html/a00949.html new file mode 100644 index 000000000..f8197926e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00949.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP160t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP160t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00950.html b/components/els_pkc/doc/mcxn/html/a00950.html new file mode 100644 index 000000000..737d2b668 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00950.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP192t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP192t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00951.html b/components/els_pkc/doc/mcxn/html/a00951.html new file mode 100644 index 000000000..c0f7b3cac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00951.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP224t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP224t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00952.html b/components/els_pkc/doc/mcxn/html/a00952.html new file mode 100644 index 000000000..982ca9165 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00952.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP256t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP256t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00953.html b/components/els_pkc/doc/mcxn/html/a00953.html new file mode 100644 index 000000000..8d4b8a54a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00953.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP320t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP320t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00954.html b/components/els_pkc/doc/mcxn/html/a00954.html new file mode 100644 index 000000000..7714a7b0a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00954.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP384t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP384t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00955.html b/components/els_pkc/doc/mcxn/html/a00955.html new file mode 100644 index 000000000..4d13ab717 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00955.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

WeierECC parameter size definitions for brainpoolP512t1. +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SIGNATURE
 
+

Detailed Description

+

WeierECC parameter size definitions for brainpoolP512t1.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00956.html b/components/els_pkc/doc/mcxn/html/a00956.html new file mode 100644 index 000000000..b810191a7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00956.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_WEIERECC_MAX_SIZE + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_WEIERECC_MAX_SIZE
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

Maximum size definitions for WeierECC parameters (ECC component officially supports up to 640 bit Weierstrass curves) +More...

+ + + + + + + + + + + + + + +

+Macros

+#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIVATEKEY
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_PUBLICKEY
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_SHAREDSECRET
 
+#define MCUXCLECC_WEIERECC_MAX_SIZE_SIGNATURE
 
+

Detailed Description

+

Maximum size definitions for WeierECC parameters (ECC component officially supports up to 640 bit Weierstrass curves)

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00957.html b/components/els_pkc/doc/mcxn/html/a00957.html new file mode 100644 index 000000000..cf1649249 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00957.html @@ -0,0 +1,302 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_ED25519_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_ED25519_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

EdDSA parameter size definitions for Ed25519. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP
 Byte length of the underlying prime p used in Ed25519. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER
 Byte length of the base point order n used in Ed25519. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY
 Byte length of an Ed25519 private key. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA
 Byte length of an Ed25519 private key handle data buffer. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY
 Byte length of an Ed25519 public key. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE
 Byte length of an Ed25519 signature. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen)
 Byte length of an Ed25519 prefix. More...
 
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(contextLen)
 Byte length of an Ed25519 signature protocol descriptor. More...
 
+

Detailed Description

+

EdDSA parameter size definitions for Ed25519.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP
+
+ +

Byte length of the underlying prime p used in Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER
+
+ +

Byte length of the base point order n used in Ed25519.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY
+
+ +

Byte length of an Ed25519 private key.

+
Examples
mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
+
+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA
+
+ +

Byte length of an Ed25519 private key handle data buffer.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, and mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c.
+
+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY
+
+ +

Byte length of an Ed25519 public key.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, and mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c.
+
+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE
+
+ +

Byte length of an Ed25519 signature.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, and mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c.
+
+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX

+ +
+
+ + + + + + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX( contextLen)
+
+ +

Byte length of an Ed25519 prefix.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR

+ +
+
+ + + + + + + + +
#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR( contextLen)
+
+ +

Byte length of an Ed25519 signature protocol descriptor.

+
Examples
mcuxClEcc_EdDSA_Ed25519ctx_example.c, and mcuxClEcc_EdDSA_Ed25519ph_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00957.js b/components/els_pkc/doc/mcxn/html/a00957.js new file mode 100644 index 000000000..c787ffe64 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00957.js @@ -0,0 +1,11 @@ +var a00957 = +[ + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP", "a00957.html#gac14b636a63b6ad2a4ba8edb45d213aea", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER", "a00957.html#gab9dd06ce9086a33b19e20eba3aed8a7c", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY", "a00957.html#gab2c2539baf2994a0baae71d5d5c8f9fe", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA", "a00957.html#ga550f1830c8403002664123225e0f594f", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY", "a00957.html#gaf6cce889f1dc2b213479126d850af09c", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE", "a00957.html#gafd15d3ce72046f505d9763687d1614df", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX", "a00957.html#gae7f1a0f58d5d7690b379a651edda99ef", null ], + [ "MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR", "a00957.html#ga506d1f24af8a6f12335d65ddb6be97fb", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00958.html b/components/els_pkc/doc/mcxn/html/a00958.html new file mode 100644 index 000000000..3b86cbb51 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00958.html @@ -0,0 +1,246 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_EDDSA_ED448_SIZE_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_EDDSA_ED448_SIZE_
mcuxClEcc » mcuxClEcc_ParameterSizes
+
+
+ +

EdDSA parameter size definitions for Ed448. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP
 Byte length of the underlying prime p used in Ed448. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER
 Byte length of the base point order n used in Ed448. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY
 Byte length of an Ed448 private key. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA
 Byte length of an Ed448 private key handle data buffer. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY
 Byte length of an Ed448 public key. More...
 
#define MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE
 Byte length of an Ed448 signature. More...
 
+

Detailed Description

+

EdDSA parameter size definitions for Ed448.

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP
+
+ +

Byte length of the underlying prime p used in Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER
+
+ +

Byte length of the base point order n used in Ed448.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY
+
+ +

Byte length of an Ed448 private key.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA
+
+ +

Byte length of an Ed448 private key handle data buffer.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY
+
+ +

Byte length of an Ed448 public key.

+ +
+
+ +

◆ MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE

+ +
+
+ + + + +
#define MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE
+
+ +

Byte length of an Ed448 signature.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00958.js b/components/els_pkc/doc/mcxn/html/a00958.js new file mode 100644 index 000000000..aa02b10d6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00958.js @@ -0,0 +1,9 @@ +var a00958 = +[ + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP", "a00958.html#ga574cb628611266d5182378f52676024b", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER", "a00958.html#ga2fff3270c5870bb95a69c8f283d91ee4", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY", "a00958.html#ga37d97fd46dcc20e7f93a5e06017ff967", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA", "a00958.html#gae310bda6e4756493489df624280503ef", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY", "a00958.html#ga51affb40be89a5c0b1eb0d17a135786c", null ], + [ "MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE", "a00958.html#gae3ae89f1d488c9444e0f8c3813b9753a", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00959.html b/components/els_pkc/doc/mcxn/html/a00959.html new file mode 100644 index 000000000..d3422da42 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00959.html @@ -0,0 +1,267 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_STATUS_
mcuxClEcc » mcuxClEcc_Macros
+
+
+ +

mcuxClEcc return code definitions +More...

+ + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLECC_STATUS_OK
 Operation was successful. More...
 
#define MCUXCLECC_STATUS_INVALID_PARAMS
 Parameters are invalid. More...
 
#define MCUXCLECC_STATUS_RNG_ERROR
 Random number (DRBG / PRNG) error (unexpected behavior). More...
 
#define MCUXCLECC_STATUS_INVALID_SIGNATURE
 ECDSA Signature is invalid. More...
 
#define MCUXCLECC_STATUS_NEUTRAL_POINT
 The result of the point operation is the neutral point. More...
 
#define MCUXCLECC_STATUS_FAULT_ATTACK
 Fault attack (unexpected behavior) is detected. More...
 
#define MCUXCLECC_STATUS_NOT_SUPPORTED
 Functionality is not supported. More...
 
+

Detailed Description

+

mcuxClEcc return code definitions

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_OK
+
+ +

Operation was successful.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, and mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+ +
+
+ +

◆ MCUXCLECC_STATUS_INVALID_PARAMS

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_INVALID_PARAMS
+
+ +

Parameters are invalid.

+ +
+
+ +

◆ MCUXCLECC_STATUS_RNG_ERROR

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_RNG_ERROR
+
+ +

Random number (DRBG / PRNG) error (unexpected behavior).

+ +
+
+ +

◆ MCUXCLECC_STATUS_INVALID_SIGNATURE

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_INVALID_SIGNATURE
+
+ +

ECDSA Signature is invalid.

+ +
+
+ +

◆ MCUXCLECC_STATUS_NEUTRAL_POINT

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_NEUTRAL_POINT
+
+ +

The result of the point operation is the neutral point.

+ +
+
+ +

◆ MCUXCLECC_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_FAULT_ATTACK
+
+ +

Fault attack (unexpected behavior) is detected.

+ +
+
+ +

◆ MCUXCLECC_STATUS_NOT_SUPPORTED

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_NOT_SUPPORTED
+
+ +

Functionality is not supported.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00959.js b/components/els_pkc/doc/mcxn/html/a00959.js new file mode 100644 index 000000000..9d5bf9598 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00959.js @@ -0,0 +1,10 @@ +var a00959 = +[ + [ "MCUXCLECC_STATUS_OK", "a00959.html#gafed6866e44c300e1946713be81aefb9c", null ], + [ "MCUXCLECC_STATUS_INVALID_PARAMS", "a00959.html#ga7eec856d4a1438ff6e603ee42aaa9aae", null ], + [ "MCUXCLECC_STATUS_RNG_ERROR", "a00959.html#ga80ff10536e9cd063f733449d74b1c878", null ], + [ "MCUXCLECC_STATUS_INVALID_SIGNATURE", "a00959.html#gae739e1f3f62d1a66e2a862e40d5a0f37", null ], + [ "MCUXCLECC_STATUS_NEUTRAL_POINT", "a00959.html#gaad0d3ea3572cc175fe1608bca3ddac35", null ], + [ "MCUXCLECC_STATUS_FAULT_ATTACK", "a00959.html#ga9d53aaec17a413449e5cb6b73702c2c3", null ], + [ "MCUXCLECC_STATUS_NOT_SUPPORTED", "a00959.html#ga7f2a86f80fcda4760372af6cdbc11c1b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00960.html b/components/els_pkc/doc/mcxn/html/a00960.html new file mode 100644 index 000000000..b357b82a4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00960.html @@ -0,0 +1,151 @@ + + + + + + + +MCUX CLNS: MCUXCLECC_MONTDH_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MCUXCLECC_MONTDH_STATUS_
mcuxClEcc » mcuxClEcc_Macros
+
+
+ +

mcuxClEcc_Mont return code definitions +More...

+ + + + + +

+Macros

#define MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP
 MONTDH public key lies in small subgroup. More...
 
+

Detailed Description

+

mcuxClEcc_Mont return code definitions

+

Macro Definition Documentation

+ +

◆ MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP

+ +
+
+ + + + +
#define MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP
+
+ +

MONTDH public key lies in small subgroup.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00960.js b/components/els_pkc/doc/mcxn/html/a00960.js new file mode 100644 index 000000000..db38bf361 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00960.js @@ -0,0 +1,4 @@ +var a00960 = +[ + [ "MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP", "a00960.html#gaf70d3732e96746a174562deb076669f6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00961.html b/components/els_pkc/doc/mcxn/html/a00961.html new file mode 100644 index 000000000..087f59a58 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00961.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: HMAC Modes API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
HMAC Modes API
MCUX CL &ndash; API
+
+
+ +

HMAC mode operations. +More...

+ + + + + + + + + + + + + + + + + +

+Modules

 mcuxClHmac Constants
 Constants of HMAC Modes API component.
 
 mcuxClHmac Functions
 Defines all functions of HMAC Modes API.
 
 mcuxClHmac_KeyTypes
 Defines of supported key types of HMAC Modes API, see mcuxClKey.
 
 mcuxClHmac_MemoryConsumption
 Defines the memory consumption for the mcuxClHmac component.
 
 HMAC mode definitions
 Modes used by the HMAC operations.
 
+

Detailed Description

+

HMAC mode operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00961.js b/components/els_pkc/doc/mcxn/html/a00961.js new file mode 100644 index 000000000..fd5548187 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00961.js @@ -0,0 +1,8 @@ +var a00961 = +[ + [ "mcuxClHmac Constants", "a00778.html", "a00778" ], + [ "mcuxClHmac Functions", "a00779.html", "a00779" ], + [ "mcuxClHmac_KeyTypes", "a00781.html", "a00781" ], + [ "mcuxClHmac_MemoryConsumption", "a00782.html", "a00782" ], + [ "HMAC mode definitions", "a00783.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00962.html b/components/els_pkc/doc/mcxn/html/a00962.html new file mode 100644 index 000000000..426d32f1d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00962.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: MAC Modes API + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Modules
+
+
MAC Modes API
MCUX CL &ndash; API
+
+
+ +

Message Authentication Code (MAC) mode operations. +More...

+ + + + + + + + + + + + + + +

+Modules

 mcuxClMacModes Constants
 Constants of MAC Modes API component.
 
 mcuxClMacModes Functions
 Defines all functions of MAC Modes API.
 
 mcuxClMacModes_MemoryConsumption
 Defines the memory consumption for the mcuxClMacModes component.
 
 MAC mode definitions
 Modes used by the MAC operations.
 
+

Detailed Description

+

Message Authentication Code (MAC) mode operations.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00962.js b/components/els_pkc/doc/mcxn/html/a00962.js new file mode 100644 index 000000000..0102d9faa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00962.js @@ -0,0 +1,7 @@ +var a00962 = +[ + [ "mcuxClMacModes Constants", "a00800.html", "a00800" ], + [ "mcuxClMacModes Functions", "a00801.html", "a00801" ], + [ "mcuxClMacModes_MemoryConsumption", "a00803.html", null ], + [ "MAC mode definitions", "a00804.html", "a00804" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00963.html b/components/els_pkc/doc/mcxn/html/a00963.html new file mode 100644 index 000000000..8ae01736e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00963.html @@ -0,0 +1,330 @@ + + + + + + + +MCUX CLNS: McuxClPkc_Functions_Init + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Data Structures | +Macros | +Functions
+
+
McuxClPkc_Functions_Init
mcuxClPkc » mcuxClPkc_Functions
+
+
+ +

mcuxClPkc functions of PKC initialization and deinitialization +More...

+ + + + + +

+Data Structures

struct  mcuxClPkc_State_t
 Structure of PKC state backup. More...
 
+ + + + + + + +

+Macros

#define MCUXCLPKC_FP_INITIALIZE(pState)
 Helper macro to call mcuxClPkc_Initialize with flow protection. More...
 
#define MCUXCLPKC_FP_DEINITIALIZE(pState)
 Helper macro to call mcuxClPkc_Deinitialize with flow protection. More...
 
+ + + + + + + + + + + + + +

+Functions

 MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcInitializeEngine_t, typedef void(*mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState))
 Function type for PKC initialization engine. More...
 
 MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcDeInitializeEngine_t, typedef void(*mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState))
 Function type for PKC deinitialization engine. More...
 
void mcuxClPkc_Initialize (mcuxClPkc_State_t *pState)
 initialize PKC hardware More...
 
void mcuxClPkc_Deinitialize (const mcuxClPkc_State_t *pState)
 deinitialize PKC hardware More...
 
+

Detailed Description

+

mcuxClPkc functions of PKC initialization and deinitialization

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_FP_INITIALIZE

+ +
+
+ + + + + + + + +
#define MCUXCLPKC_FP_INITIALIZE( pState)
+
+ +

Helper macro to call mcuxClPkc_Initialize with flow protection.

+ +
+
+ +

◆ MCUXCLPKC_FP_DEINITIALIZE

+ +
+
+ + + + + + + + +
#define MCUXCLPKC_FP_DEINITIALIZE( pState)
+
+ +

Helper macro to call mcuxClPkc_Deinitialize with flow protection.

+ +
+
+

Function Documentation

+ +

◆ MCUX_CSSL_FP_FUNCTION_POINTER() [1/2]

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcInitializeEngine_t ,
typedef void(*)(mcuxClPkc_State_t *pState) mcuxClPkc_PkcInitializeEngine_t 
)
+
+ +

Function type for PKC initialization engine.

+

Generic function pointer to PKC initialization function

+
Parameters
+ + +
[out]pStatepointer to PKC state backup structure. If it's not a NULL pointer, PKC state before initialization will be stored in this structure.
+
+
+ +
+
+ +

◆ MCUX_CSSL_FP_FUNCTION_POINTER() [2/2]

+ +
+
+ + + + + + + + + + + + + + + + + + +
MCUX_CSSL_FP_FUNCTION_POINTER (mcuxClPkc_PkcDeInitializeEngine_t ,
typedef void(*)(const mcuxClPkc_State_t *pState) mcuxClPkc_PkcDeInitializeEngine_t 
)
+
+ +

Function type for PKC deinitialization engine.

+

Generic function pointer to PKC deinitialization function

+
Parameters
+ + +
[in]pStatepointer to PKC state backup structure. If it's not a NULL pointer, PKC state will be restored from this structure.
+
+
+ +
+
+ +

◆ mcuxClPkc_Initialize()

+ +
+
+ + + + + + + + +
void mcuxClPkc_Initialize (mcuxClPkc_State_t * pState)
+
+ +

initialize PKC hardware

+

This function initializes PKC hardware, and optionally backups the original PKC configuration (except STOP bit).

+
Parameters
+ + +
[out]pStatepointer to PKC state backup structure. If it's not a NULL pointer, PKC state before initialization will be stored in this structure.
+
+
+ +
+
+ +

◆ mcuxClPkc_Deinitialize()

+ +
+
+ + + + + + + + +
void mcuxClPkc_Deinitialize (const mcuxClPkc_State_t * pState)
+
+ +

deinitialize PKC hardware

+

This function deinitializes PKC hardware, and optionally restores PKC configuration (except STOP bit).

+
Parameters
+ + +
[in]pStatepointer to PKC state backup structure. If it's not a NULL pointer, PKC state will be restored from this structure.
+
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00963.js b/components/els_pkc/doc/mcxn/html/a00963.js new file mode 100644 index 000000000..409701c9a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00963.js @@ -0,0 +1,13 @@ +var a00963 = +[ + [ "mcuxClPkc_State_t", "a01261.html", [ + [ "ctrl", "a01261.html#a3b225011dfe5fd36551cb70210f9b41c", null ], + [ "cfg", "a01261.html#a5d5778eef90af40b0ba73b22fdeedb57", null ] + ] ], + [ "MCUXCLPKC_FP_INITIALIZE", "a00963.html#ga3a95e35addbaf26fa41f8e9cf27950f6", null ], + [ "MCUXCLPKC_FP_DEINITIALIZE", "a00963.html#gaf47041e2fee71acba1d37b89f7825e02", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00963.html#gaf821ec5ad694746ba28321b2bb802236", null ], + [ "MCUX_CSSL_FP_FUNCTION_POINTER", "a00963.html#ga4ad3a9a17b2090a8d761fcd9c9c86218", null ], + [ "mcuxClPkc_Initialize", "a00963.html#ga338ddc55800355531bd20236fa3710b8", null ], + [ "mcuxClPkc_Deinitialize", "a00963.html#ga0d09260a20ca358d02264f16a74369c1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00964.html b/components/els_pkc/doc/mcxn/html/a00964.html new file mode 100644 index 000000000..f331decd3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00964.html @@ -0,0 +1,397 @@ + + + + + + + +MCUX CLNS: McuxClPkc_Functions_UPTRT + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Macros | +Functions
+
+
McuxClPkc_Functions_UPTRT
mcuxClPkc » mcuxClPkc_Functions
+
+
+ +

mcuxClPkc functions of PKC UPTR table setup +More...

+ + + + + +

+Macros

#define MCUXCLPKC_FP_GENERATEUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer)
 Helper macro to call mcuxClPkc_GenerateUPTRT with flow protection. More...
 
+ + + + + + + + + + +

+Functions

void mcuxClPkc_GenerateUPTRT (uint16_t *pUPTRT, const uint8_t *pBaseBuffer, uint16_t bufferLength, uint8_t noOfBuffer)
 Initialize UPTR table. More...
 
mcuxClPkc_Status_t mcuxClPkc_RandomizeUPTRT (mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint8_t noOfBuffer)
 Randomize UPTR table. More...
 
mcuxClPkc_Status_t mcuxClPkc_ReRandomizeUPTRT (mcuxClSession_Handle_t pSession, uint16_t *pUPTRT, uint16_t bufferLength, uint8_t noOfBuffer)
 Randomize UPTR table and operands in PKC workarea. More...
 
+

Detailed Description

+

mcuxClPkc functions of PKC UPTR table setup

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_FP_GENERATEUPTRT

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLPKC_FP_GENERATEUPTRT( pUPTRT,
 pBaseBuffer,
 bufferSize,
 noOfBuffer 
)
+
+ +

Helper macro to call mcuxClPkc_GenerateUPTRT with flow protection.

+ +
+
+

Function Documentation

+ +

◆ mcuxClPkc_GenerateUPTRT()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void mcuxClPkc_GenerateUPTRT (uint16_t * pUPTRT,
const uint8_t * pBaseBuffer,
uint16_t bufferLength,
uint8_t noOfBuffer 
)
+
+ +

Initialize UPTR table.

+

This function initializes elements in UPTR table. UPTR table contains the address (16-bit offset in PKC workarea) of each buffer (PKC operand). Each element of the table will be initialized with a 16-bit offset, associated with a buffer allocated in sequence in PKC workarea. When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements.

+
Parameters
+ + + + + +
[out]pUPTRTpointer to the first element to be initialized in UPTR table.
[in]pBaseBufferaddress of the buffer in PKC workarea, with which the first element will be associated.
[in]bufferLengthbyte length of each buffer in PKC workarea.
[in]noOfBuffernumber of elements to be initialized.
+
+
+
+
Parameter properties
+
+
pUPTRT
+
this pointer shall be 2-byte aligned.
+
pBaseBuffer
+
this address shall be MCUXCLPKC_WORDSIZE aligned.
+
bufferLength
+
this length shall be a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+ +
+
+ +

◆ mcuxClPkc_RandomizeUPTRT()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClPkc_Status_t mcuxClPkc_RandomizeUPTRT (mcuxClSession_Handle_t pSession,
uint16_t * pUPTRT,
uint8_t noOfBuffer 
)
+
+ +

Randomize UPTR table.

+

This function randomly permutes offsets stored in UPTR table. It randomizes the buffer allocation (physical address in PKC workarea). When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements.

+
Parameters
+ + + + +
[in]pSessionhandle for the current CL session.
[in,out]pUPTRTpointer to the first element to be randomized in UPTR table.
[in]noOfBuffernumber of elements to be randomized.
+
+
+
+
Parameter properties
+
+
pSession:
+
The session pointed to by pSession has to be initialized prior to a call to this function.
+
pUPTRT
+
this pointer shall be 2-byte aligned.
+
+
+
+
Attention
Only the buffer allocation will be randomized, existing operands stored in each buffer will not be moved accordingly.
+
+This function uses PRNG. Caller needs to check if PRNG is ready.
+
Returns
A flow-protected status code (see Flow Protection API).
+
Return values
+ + + +
MCUXCLPKC_STATUS_OKif UPTR table is randomized successfully.
MCUXCLPKC_STATUS_NOKif the operation failed.
+
+
+
Attention
This function uses PRNG which has to be initialized prior to calling the function.
+ +
+
+ +

◆ mcuxClPkc_ReRandomizeUPTRT()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mcuxClPkc_Status_t mcuxClPkc_ReRandomizeUPTRT (mcuxClSession_Handle_t pSession,
uint16_t * pUPTRT,
uint16_t bufferLength,
uint8_t noOfBuffer 
)
+
+ +

Randomize UPTR table and operands in PKC workarea.

+

This function randomly permutes offsets stored in UPTR table, together with operands stored in each buffer in PKC workarea. It randomizes the buffer allocation (physical address in PKC workarea) and moves operands stored accordingly. When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements.

+
Parameters
+ + + + + +
[in]pSessionhandle for the current CL session.
[in,out]pUPTRTpointer to the first element to be randomized in UPTR table.
[in]bufferLengthbyte length of each buffer in PKC workarea.
[in]noOfBuffernumber of elements to be randomized.
+
+
+
+
Parameter properties
+
+
pSession:
+
The session pointed to by pSession has to be initialized prior to a call to this function.
+
pUPTRT
+
this pointer shall be 2-byte aligned.
+All offsets (pUPTRT[0~(noOfBuffer-1)]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+
bufferLength
+
this length shall be a multiple of MCUXCLPKC_WORDSIZE.
+
+
+
+
Attention
This function uses PRNG. Caller needs to check if PRNG is ready.
+
Returns
A flow-protected status code (see Flow Protection API).
+
Return values
+ + + +
MCUXCLPKC_STATUS_OKif UPTR table is randomized successfully.
MCUXCLPKC_STATUS_NOKif the operation failed.
+
+
+
Attention
This function uses PRNG which has to be initialized prior to calling the function.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00964.js b/components/els_pkc/doc/mcxn/html/a00964.js new file mode 100644 index 000000000..23cb331e4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00964.js @@ -0,0 +1,7 @@ +var a00964 = +[ + [ "MCUXCLPKC_FP_GENERATEUPTRT", "a00964.html#ga26921e5d9a66bd8247a277794b04b42c", null ], + [ "mcuxClPkc_GenerateUPTRT", "a00964.html#gae14e20fe9fd56e0ca8125773bc88f822", null ], + [ "mcuxClPkc_RandomizeUPTRT", "a00964.html#gaf961165a01be833d3200563399a2c9aa", null ], + [ "mcuxClPkc_ReRandomizeUPTRT", "a00964.html#ga195c78d51f2084c693257bc52c725c1f", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00965.html b/components/els_pkc/doc/mcxn/html/a00965.html new file mode 100644 index 000000000..724236246 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00965.html @@ -0,0 +1,361 @@ + + + + + + + +MCUX CLNS: McuxClPkc_Functions_Calculation + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Typedefs | +Functions
+
+
McuxClPkc_Functions_Calculation
mcuxClPkc » mcuxClPkc_Functions
+
+
+ +

mcuxClPkc functions of PKC calculation +More...

+ + + + + + + + +

+Macros

#define MCUXCLPKC_FP_CALCFUP(pUPTR, ulen)
 Helper macro to call mcuxClPkc_CalcFup with flow protection. More...
 
#define MCUXCLPKC_FP_CALCFUP_OFFSET(pUPTR, skipLen, ulen)
 Helper macro to call mcuxClPkc_CalcFup (skipping first skipLen calculation(s)) with flow protection. More...
 
+ + + + +

+Typedefs

typedef const struct mcuxClPkc_FUPEntry * mcuxClPkc_PtrFUPEntry_t
 type of FUP program address. More...
 
+ + + + + + + + + + +

+Functions

void mcuxClPkc_Calc (uint16_t param_mode, uint32_t iR_iX_iY_iZ)
 Start a PKC calculation. More...
 
void mcuxClPkc_CalcConst (uint16_t param_mode, uint32_t iR_iX_iY_C)
 Start a PKC calculation with one constant parameter. More...
 
void mcuxClPkc_CalcFup (mcuxClPkc_PtrFUPEntry_t pUPTR, uint8_t uLength)
 Start a PKC FUP program calculation. More...
 
+

Detailed Description

+

mcuxClPkc functions of PKC calculation

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_FP_CALCFUP

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLPKC_FP_CALCFUP( pUPTR,
 ulen 
)
+
+ +

Helper macro to call mcuxClPkc_CalcFup with flow protection.

+ +
+
+ +

◆ MCUXCLPKC_FP_CALCFUP_OFFSET

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLPKC_FP_CALCFUP_OFFSET( pUPTR,
 skipLen,
 ulen 
)
+
+ +

Helper macro to call mcuxClPkc_CalcFup (skipping first skipLen calculation(s)) with flow protection.

+ +
+
+

Typedef Documentation

+ +

◆ mcuxClPkc_PtrFUPEntry_t

+ +
+
+ + + + +
typedef const struct mcuxClPkc_FUPEntry* mcuxClPkc_PtrFUPEntry_t
+
+ +

type of FUP program address.

+ +
+
+

Function Documentation

+ +

◆ mcuxClPkc_Calc()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClPkc_Calc (uint16_t param_mode,
uint32_t iR_iX_iY_iZ 
)
+
+ +

Start a PKC calculation.

+

This function performs one specified PKC calculation, of which the operand(s) and result are specified by the indices of UPTR table.

+
Parameters
+ + + +
[in]param_modeparam (the higher 8 bits) indicates the type of the calculation (L0 or L1) and the parameter set (PS1 or PS2).
+ mode (the lower 8 bits) indicates the calculation, either an L0 operation or L1 microcode.
[in]iR_iX_iY_iZindices of the operand(s) and the result in UPTR table.
+
+
+
Attention
The PKC calculation might be still on-going when returning to caller, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ +
+
+ +

◆ mcuxClPkc_CalcConst()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClPkc_CalcConst (uint16_t param_mode,
uint32_t iR_iX_iY_C 
)
+
+ +

Start a PKC calculation with one constant parameter.

+

This function performs one specified PKC calculation, of which the operand(s) and result are specified by the indices of UPTR table, and a 8-bit constant parameter is directly provided. This function can also be used to perform an L0 operation without using Z operand, e.g., OP_MUL, R = X0 * Y.

+
Parameters
+ + + +
[in]param_modeparam (the higher 8 bits) indicates the type of the calculation (always L0) and the parameter set (PS1 or PS2).
+ mode (the lower 8 bits) indicates the calculation, an L0 operation.
[in]iR_iX_iY_Cindices of the operand(s) and the result in UPTR table, and a direct 8-bit constant.
+
+
+
Attention
The PKC calculation might be still on-going when returning to caller, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ +
+
+ +

◆ mcuxClPkc_CalcFup()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void mcuxClPkc_CalcFup (mcuxClPkc_PtrFUPEntry_t pUPTR,
uint8_t uLength 
)
+
+ +

Start a PKC FUP program calculation.

+

This function triggers PKC to start the calculation of a FUP program.

+
Parameters
+ + + +
[in]pUPTR2-byte aligned address of the FUP program.
[in]uLengthlength (number of calculation) of the FUP program.
+
+
+
Attention
The PKC calculation might be still on-going when returning to caller, call mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00965.js b/components/els_pkc/doc/mcxn/html/a00965.js new file mode 100644 index 000000000..471d956a8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00965.js @@ -0,0 +1,9 @@ +var a00965 = +[ + [ "MCUXCLPKC_FP_CALCFUP", "a00965.html#ga75385d0295607d89d375f6b8706f4299", null ], + [ "MCUXCLPKC_FP_CALCFUP_OFFSET", "a00965.html#gac16f7fd691d8868968cc643feed97846", null ], + [ "mcuxClPkc_PtrFUPEntry_t", "a00965.html#ga9c5b69d5d2b5e9b7551de9cbe163050f", null ], + [ "mcuxClPkc_Calc", "a00965.html#ga1fe435f5e72d9347692a7ac8fa2ba67f", null ], + [ "mcuxClPkc_CalcConst", "a00965.html#ga2d214326104dc2ced79098286852ae03", null ], + [ "mcuxClPkc_CalcFup", "a00965.html#gaec0a3e70eb593b9bd49edf9e7aba298e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00966.html b/components/els_pkc/doc/mcxn/html/a00966.html new file mode 100644 index 000000000..d4e5d98d4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00966.html @@ -0,0 +1,229 @@ + + + + + + + +MCUX CLNS: McuxClPkc_Functions_Wait + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+Macros | +Functions
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McuxClPkc_Functions_Wait
mcuxClPkc » mcuxClPkc_Functions
+
+
+ +

mcuxClPkc functions for waiting PKC computation +More...

+ + + + + + + + +

+Macros

#define MCUXCLPKC_FP_WAITFORFINISH()
 Helper macro to call mcuxClPkc_WaitForFinish with flow protection. More...
 
#define MCUXCLPKC_FP_WAITFORREADY()
 Helper macro to call mcuxClPkc_WaitForReady with flow protection. More...
 
+ + + + + + + +

+Functions

void mcuxClPkc_WaitForFinish (void)
 Wait until PKC finishes calculations. More...
 
void mcuxClPkc_WaitForReady (void)
 Wait until PKC is ready to accept new calculation. More...
 
+

Detailed Description

+

mcuxClPkc functions for waiting PKC computation

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_FP_WAITFORFINISH

+ +
+
+ + + + + + + +
#define MCUXCLPKC_FP_WAITFORFINISH()
+
+ +

Helper macro to call mcuxClPkc_WaitForFinish with flow protection.

+ +
+
+ +

◆ MCUXCLPKC_FP_WAITFORREADY

+ +
+
+ + + + + + + +
#define MCUXCLPKC_FP_WAITFORREADY()
+
+ +

Helper macro to call mcuxClPkc_WaitForReady with flow protection.

+ +
+
+

Function Documentation

+ +

◆ mcuxClPkc_WaitForFinish()

+ +
+
+ + + + + + + + +
void mcuxClPkc_WaitForFinish (void )
+
+ +

Wait until PKC finishes calculations.

+

This function waits until PKC finishes on-going and pending calculations (if there is any). When returning to caller, PKC is in idle state, and result in PKC workarea is ready.

+ +
+
+ +

◆ mcuxClPkc_WaitForReady()

+ +
+
+ + + + + + + + +
void mcuxClPkc_WaitForReady (void )
+
+ +

Wait until PKC is ready to accept new calculation.

+

This function waits until PKC is ready to accept next calculation (i.e., no pending calculation).

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00966.js b/components/els_pkc/doc/mcxn/html/a00966.js new file mode 100644 index 000000000..9ac307fe4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00966.js @@ -0,0 +1,7 @@ +var a00966 = +[ + [ "MCUXCLPKC_FP_WAITFORFINISH", "a00966.html#gac1f65eb00620f5683ffd7965a084a977", null ], + [ "MCUXCLPKC_FP_WAITFORREADY", "a00966.html#ga1733f3b346a3bd00ffdd8b3f7df0c3fc", null ], + [ "mcuxClPkc_WaitForFinish", "a00966.html#ga7d26efcc91094390f7c55fbd870692cd", null ], + [ "mcuxClPkc_WaitForReady", "a00966.html#ga963b13a65f2ae869947cbbebf2f9a823", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00967.html b/components/els_pkc/doc/mcxn/html/a00967.html new file mode 100644 index 000000000..38c28d3b9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00967.html @@ -0,0 +1,213 @@ + + + + + + + +MCUX CLNS: MCUXCLPKC_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros | +Typedefs
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+
MCUXCLPKC_STATUS_
mcuxClPkc » mcuxClPkc_Macros
+
+
+ +

mcuxClPkc return code definitions +More...

+ + + + + + + + +

+Macros

#define MCUXCLPKC_STATUS_OK
 PKC operation successful. More...
 
#define MCUXCLPKC_STATUS_NOK
 PKC operation not successful. More...
 
+ + + + + + + +

+Typedefs

typedef uint32_t mcuxClPkc_Status_t
 Type for error codes used by PKC component functions. More...
 
typedef mcuxClPkc_Status_t mcuxClPkc_Status_Protected_t
 Deprecated type for error codes used by code-flow protected PKC component functions. More...
 
+

Detailed Description

+

mcuxClPkc return code definitions

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLPKC_STATUS_OK
+
+ +

PKC operation successful.

+ +
+
+ +

◆ MCUXCLPKC_STATUS_NOK

+ +
+
+ + + + +
#define MCUXCLPKC_STATUS_NOK
+
+ +

PKC operation not successful.

+ +
+
+

Typedef Documentation

+ +

◆ mcuxClPkc_Status_t

+ +
+
+ + + + +
typedef uint32_t mcuxClPkc_Status_t
+
+ +

Type for error codes used by PKC component functions.

+ +
+
+ +

◆ mcuxClPkc_Status_Protected_t

+ +
+
+ + + + +
typedef mcuxClPkc_Status_t mcuxClPkc_Status_Protected_t
+
+ +

Deprecated type for error codes used by code-flow protected PKC component functions.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00967.js b/components/els_pkc/doc/mcxn/html/a00967.js new file mode 100644 index 000000000..07ebf63ef --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00967.js @@ -0,0 +1,7 @@ +var a00967 = +[ + [ "MCUXCLPKC_STATUS_OK", "a00967.html#ga12385077399c226411e29ef427246669", null ], + [ "MCUXCLPKC_STATUS_NOK", "a00967.html#gab1f0a5295736463652b7a8c1ba887991", null ], + [ "mcuxClPkc_Status_t", "a00967.html#ga9382ab1c4689794b50a3b75ad39a350c", null ], + [ "mcuxClPkc_Status_Protected_t", "a00967.html#gaaee98013327cc5777f68c6b9fdb1ef6d", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00968.html b/components/els_pkc/doc/mcxn/html/a00968.html new file mode 100644 index 000000000..9363c4906 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00968.html @@ -0,0 +1,271 @@ + + + + + + + +MCUX CLNS: MCUXCLPKC_MISC_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+Macros
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MCUXCLPKC_MISC_
mcuxClPkc » mcuxClPkc_Macros
+
+
+ +

mcuxClPkc misc macros and definitions +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLPKC_ROUNDUP_SIZE(byteLen)
 Round-up a length to a multiple of PKC wordsize. More...
 
#define MCUXCLPKC_PACKARGS4(byte3_MSByte, byte2, byte1, byte0_LSByte)
 Macros for packing 4 8-bit parameters. More...
 
#define MCUXCLPKC_PACKARGS2(hi8, lo8)
 Macros for packing 2 8-bit parameters. More...
 
#define MCUXCLPKC_RAM_START_ADDRESS
 PKC workarea address. More...
 
#define MCUXCLPKC_WORDSIZE
 PKC wordsize in byte. More...
 
+

Detailed Description

+

mcuxClPkc misc macros and definitions

+

Macro Definition Documentation

+ +

◆ MCUXCLPKC_ROUNDUP_SIZE

+ +
+
+ + + + + + + + +
#define MCUXCLPKC_ROUNDUP_SIZE( byteLen)
+
+ +

Round-up a length to a multiple of PKC wordsize.

+ +
+
+ +

◆ MCUXCLPKC_PACKARGS4

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define MCUXCLPKC_PACKARGS4( byte3_MSByte,
 byte2,
 byte1,
 byte0_LSByte 
)
+
+ +

Macros for packing 4 8-bit parameters.

+ +
+
+ +

◆ MCUXCLPKC_PACKARGS2

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define MCUXCLPKC_PACKARGS2( hi8,
 lo8 
)
+
+ +

Macros for packing 2 8-bit parameters.

+ +
+
+ +

◆ MCUXCLPKC_RAM_START_ADDRESS

+ +
+
+ + + + +
#define MCUXCLPKC_RAM_START_ADDRESS
+
+ +

PKC workarea address.

+ +
+
+ +

◆ MCUXCLPKC_WORDSIZE

+ +
+
+ + + + +
#define MCUXCLPKC_WORDSIZE
+
+ +

PKC wordsize in byte.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00968.js b/components/els_pkc/doc/mcxn/html/a00968.js new file mode 100644 index 000000000..391501989 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00968.js @@ -0,0 +1,8 @@ +var a00968 = +[ + [ "MCUXCLPKC_ROUNDUP_SIZE", "a00968.html#ga5d67b3705403f3a0cab0d71316df929b", null ], + [ "MCUXCLPKC_PACKARGS4", "a00968.html#gac13331e9f328b7a4446314837be58138", null ], + [ "MCUXCLPKC_PACKARGS2", "a00968.html#ga5040d930ab47ec9246a95cf32b8f5fed", null ], + [ "MCUXCLPKC_RAM_START_ADDRESS", "a00968.html#ga0de371abb530f10283d7f8ba4bf8dd76", null ], + [ "MCUXCLPKC_WORDSIZE", "a00968.html#ga275596959934aecdbc4dc35cefb1c6ba", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00969.html b/components/els_pkc/doc/mcxn/html/a00969.html new file mode 100644 index 000000000..242287bd4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00969.html @@ -0,0 +1,231 @@ + + + + + + + +MCUX CLNS: MCUXCLRANDOM_STATUS_ + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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MCUXCLRANDOM_STATUS_
mcuxClRandom » mcuxClRandom_Constants
+
+
+ +

mcuxClRandom return code definitions +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define MCUXCLRANDOM_STATUS_ERROR
 Random function returned error. More...
 
#define MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH
 Security strength of given RNG lower than requested. More...
 
#define MCUXCLRANDOM_STATUS_INVALID_PARAM
 Random function parameter invalid. More...
 
#define MCUXCLRANDOM_STATUS_OK
 Random function returned successfully. More...
 
#define MCUXCLRANDOM_STATUS_FAULT_ATTACK
 Random function returned fault attack. More...
 
+

Detailed Description

+

mcuxClRandom return code definitions

+

Macro Definition Documentation

+ +

◆ MCUXCLRANDOM_STATUS_ERROR

+ +
+
+ + + + +
#define MCUXCLRANDOM_STATUS_ERROR
+
+ +

Random function returned error.

+
Examples
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c.
+
+ +
+
+ +

◆ MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH

+ +
+
+ + + + +
#define MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH
+
+ +

Security strength of given RNG lower than requested.

+ +
+
+ +

◆ MCUXCLRANDOM_STATUS_INVALID_PARAM

+ +
+
+ + + + +
#define MCUXCLRANDOM_STATUS_INVALID_PARAM
+
+ +

Random function parameter invalid.

+ +
+
+ +

◆ MCUXCLRANDOM_STATUS_OK

+ +
+
+ + + + +
#define MCUXCLRANDOM_STATUS_OK
+
+ +

Random function returned successfully.

+
Examples
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ MCUXCLRANDOM_STATUS_FAULT_ATTACK

+ +
+
+ + + + +
#define MCUXCLRANDOM_STATUS_FAULT_ATTACK
+
+ +

Random function returned fault attack.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00969.js b/components/els_pkc/doc/mcxn/html/a00969.js new file mode 100644 index 000000000..132483529 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00969.js @@ -0,0 +1,8 @@ +var a00969 = +[ + [ "MCUXCLRANDOM_STATUS_ERROR", "a00969.html#ga1b55e6564466854e9bd070d5bf20c46c", null ], + [ "MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH", "a00969.html#ga1318606347b0aa4a477b68572a862552", null ], + [ "MCUXCLRANDOM_STATUS_INVALID_PARAM", "a00969.html#ga9b0f869c046d3055dcc6f994c9aa0191", null ], + [ "MCUXCLRANDOM_STATUS_OK", "a00969.html#ga951990ff5179cd6fce7310de16002b20", null ], + [ "MCUXCLRANDOM_STATUS_FAULT_ATTACK", "a00969.html#ga6d4a0c17c9ec70556936f749305dace8", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00973.html b/components/els_pkc/doc/mcxn/html/a00973.html new file mode 100644 index 000000000..21100eb04 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00973.html @@ -0,0 +1,253 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_DomainParam_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
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+
+Data Fields
+
+
mcuxClEcc_DomainParam_t Struct Reference
mcuxClEcc » mcuxClEcc_Types
+
+
+ +

Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p. + More...

+ +

#include <mcuxClEcc_Types.h>

+ + + + + + + + + + + + + + + + + + + + +

+Data Fields

const uint8_t * pA
 [in] pointer to octet string of curve parameter a (< p), of which the length is byteLenP. More...
 
const uint8_t * pB
 [in] pointer to octet string of curve parameter b (< p), of which the length is byteLenP. More...
 
const uint8_t * pP
 [in] pointer to octet string of prime modulus p, of which the length is byteLenP. More...
 
const uint8_t * pG
 [in] pointer to octet string of base point G. More...
 
const uint8_t * pN
 [in] pointer to octet string of base point order n, of which the length is byteLenN. More...
 
uint32_t misc
 [in] packed lengths, via mcuxClEcc_DomainParam_misc_Pack: bits 0~ 7: byteLenP: length of the octet string of curve parameters a, b and p, and x and y coordinates of base point G; bits 8~15: byteLenN: length of the octet string of curve parameter n; bits 16~31: reserved. More...
 
+

Detailed Description

+

Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p.

+

Each curve parameter is stored as a Big-endian octet string with exact byte length specified. For a small parameter, padding zero(s) is placed in the beginning of the octet string. This structure contains pointers to the octet strings and the lengths.

+

Field Documentation

+ +

◆ pA

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_DomainParam_t::pA
+
+ +

[in] pointer to octet string of curve parameter a (< p), of which the length is byteLenP.

+ +
+
+ +

◆ pB

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_DomainParam_t::pB
+
+ +

[in] pointer to octet string of curve parameter b (< p), of which the length is byteLenP.

+ +
+
+ +

◆ pP

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_DomainParam_t::pP
+
+ +

[in] pointer to octet string of prime modulus p, of which the length is byteLenP.

+

The leading byte of this octet string shall be nonzero (i.e., != 0x00).

+ +
+
+ +

◆ pG

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_DomainParam_t::pG
+
+ +

[in] pointer to octet string of base point G.

+

Each coordinate is an octet string of the length byteLenP. The string of x coordinate is followed by the string of y coordinate.

+ +
+
+ +

◆ pN

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_DomainParam_t::pN
+
+ +

[in] pointer to octet string of base point order n, of which the length is byteLenN.

+

The leading byte of this octet string shall be nonzero (i.e., != 0x00).

+ +
+
+ +

◆ misc

+ +
+
+ + + + +
uint32_t mcuxClEcc_DomainParam_t::misc
+
+ +

[in] packed lengths, via mcuxClEcc_DomainParam_misc_Pack: bits 0~ 7: byteLenP: length of the octet string of curve parameters a, b and p, and x and y coordinates of base point G; bits 8~15: byteLenN: length of the octet string of curve parameter n; bits 16~31: reserved.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00973.js b/components/els_pkc/doc/mcxn/html/a00973.js new file mode 100644 index 000000000..7c6db978e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00973.js @@ -0,0 +1,9 @@ +var a00973 = +[ + [ "pA", "a00973.html#a5916c96212c7f76a61ddc0c8aa957ef5", null ], + [ "pB", "a00973.html#abcaf03eba7dd8f697e3e582de2aa1eef", null ], + [ "pP", "a00973.html#adbfda4ce0ba171e1aa6f52e6b564d1e4", null ], + [ "pG", "a00973.html#a63d99844f35b075f23980f9c405d034b", null ], + [ "pN", "a00973.html#a484854783a458fd3d3ab50bfd38afcf3", null ], + [ "misc", "a00973.html#a90f3bfeae254eaa0eb7f5d97f2123906", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00977.html b/components/els_pkc/doc/mcxn/html/a00977.html new file mode 100644 index 000000000..3096a2d17 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00977.html @@ -0,0 +1,214 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_KeyGen_Param_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEcc_KeyGen_Param_t Struct Reference
mcuxClEcc » mcuxClEcc_Types
+
+
+ +

Parameter structure for function mcuxClEcc_KeyGen. + More...

+ +

#include <mcuxClEcc_Types.h>

+ + + + + + + + + + + + + + +

+Data Fields

mcuxClEcc_DomainParam_t curveParam
 [in] structure of pointers to curve parameters and length of parameters. More...
 
uint8_t * pPrivateKey
 [out] pointer to memory area, where the private key will be exported if KeyGen is executed successfully. More...
 
uint8_t * pPublicKey
 [out] pointer to memory area, where the public key will be exported if KeyGen is executed successfully. More...
 
uint32_t optLen
 [in] packed options (reserved): bits 0~31: reserved. More...
 
+

Detailed Description

+

Parameter structure for function mcuxClEcc_KeyGen.

+

Field Documentation

+ +

◆ curveParam

+ +
+
+ + + + +
mcuxClEcc_DomainParam_t mcuxClEcc_KeyGen_Param_t::curveParam
+
+ +

[in] structure of pointers to curve parameters and length of parameters.

+ +
+
+ +

◆ pPrivateKey

+ +
+
+ + + + +
uint8_t* mcuxClEcc_KeyGen_Param_t::pPrivateKey
+
+ +

[out] pointer to memory area, where the private key will be exported if KeyGen is executed successfully.

+

It will be stored as a Big-endian octet string of the exact length curveParam.byteLenN.

+ +
+
+ +

◆ pPublicKey

+ +
+
+ + + + +
uint8_t* mcuxClEcc_KeyGen_Param_t::pPublicKey
+
+ +

[out] pointer to memory area, where the public key will be exported if KeyGen is executed successfully.

+

It will be stored in the same format as the base point G.

+ +
+
+ +

◆ optLen

+ +
+
+ + + + +
uint32_t mcuxClEcc_KeyGen_Param_t::optLen
+
+ +

[in] packed options (reserved): bits 0~31: reserved.

+

CAUTION always set optLen = 0.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00977.js b/components/els_pkc/doc/mcxn/html/a00977.js new file mode 100644 index 000000000..ac662ddfd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00977.js @@ -0,0 +1,7 @@ +var a00977 = +[ + [ "curveParam", "a00977.html#a0396802978ddd78f753922c8dadadb18", null ], + [ "pPrivateKey", "a00977.html#a48dad4664822a37f78c78eca1e660a26", null ], + [ "pPublicKey", "a00977.html#a96680cb90b6901598b686b38edac1264", null ], + [ "optLen", "a00977.html#a6d0e636ce4f30294af6bcfe0ae717a01", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00981.html b/components/els_pkc/doc/mcxn/html/a00981.html new file mode 100644 index 000000000..9687cb163 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00981.html @@ -0,0 +1,231 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Sign_Param_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEcc_Sign_Param_t Struct Reference
mcuxClEcc » mcuxClEcc_Types
+
+
+ +

Parameter structure for function mcuxClEcc_Sign. + More...

+ +

#include <mcuxClEcc_Types.h>

+ + + + + + + + + + + + + + + + + +

+Data Fields

mcuxClEcc_DomainParam_t curveParam
 [in] structure of pointers to curve parameters and length of parameters. More...
 
const uint8_t * pHash
 [in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen). More...
 
const uint8_t * pPrivateKey
 [in] pointer to octet string of private key, which is of the same format as base point order n. More...
 
uint8_t * pSignature
 [out] pointer to memory area in which signature R and S will be exported if signature is generated successfully. More...
 
uint32_t optLen
 [in] packed options (reserved) and lengths: bits 0~7: byteLenHash: length of the string of message digest; bits 8~31: reserved. More...
 
+

Detailed Description

+

Parameter structure for function mcuxClEcc_Sign.

+

Field Documentation

+ +

◆ curveParam

+ +
+
+ + + + +
mcuxClEcc_DomainParam_t mcuxClEcc_Sign_Param_t::curveParam
+
+ +

[in] structure of pointers to curve parameters and length of parameters.

+ +
+
+ +

◆ pHash

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Sign_Param_t::pHash
+
+ +

[in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen).

+ +
+
+ +

◆ pPrivateKey

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Sign_Param_t::pPrivateKey
+
+ +

[in] pointer to octet string of private key, which is of the same format as base point order n.

+ +
+
+ +

◆ pSignature

+ +
+
+ + + + +
uint8_t* mcuxClEcc_Sign_Param_t::pSignature
+
+ +

[out] pointer to memory area in which signature R and S will be exported if signature is generated successfully.

+

They will be stored as Big-endian octet strings of the exact length curveParam.byteLenN. The string of R is followed by the string of S.

+ +
+
+ +

◆ optLen

+ +
+
+ + + + +
uint32_t mcuxClEcc_Sign_Param_t::optLen
+
+ +

[in] packed options (reserved) and lengths: bits 0~7: byteLenHash: length of the string of message digest; bits 8~31: reserved.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00981.js b/components/els_pkc/doc/mcxn/html/a00981.js new file mode 100644 index 000000000..8ccfeb683 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00981.js @@ -0,0 +1,8 @@ +var a00981 = +[ + [ "curveParam", "a00981.html#a9af6c185c258baa0a6a4b0080b35b1aa", null ], + [ "pHash", "a00981.html#aeccbb72505744e1f627b67b1f51508ef", null ], + [ "pPrivateKey", "a00981.html#a0e61b674ac7f46c4157397535d97ce81", null ], + [ "pSignature", "a00981.html#ae25d26ef489ff1614a0a6ab6abe9fc97", null ], + [ "optLen", "a00981.html#af5376d1c58c5cfaf33ae6156572700ff", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00985.html b/components/els_pkc/doc/mcxn/html/a00985.html new file mode 100644 index 000000000..8a9d4acb7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00985.html @@ -0,0 +1,271 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Verify_Param_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEcc_Verify_Param_t Struct Reference
mcuxClEcc » mcuxClEcc_Types
+
+
+ +

Parameter structure for function mcuxClEcc_Verify. + More...

+ +

#include <mcuxClEcc_Types.h>

+ + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

mcuxClEcc_DomainParam_t curveParam
 [in] structure of pointers to curve parameters and length of parameters. More...
 
const uint8_t * pPrecG
 [in] pointer to octet string of pre-computed point of base point G, which is of the same format as base point G. More...
 
const uint8_t * pHash
 [in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen). More...
 
const uint8_t * pSignature
 [in] pointer to octet string of signature R and S. More...
 
const uint8_t * pPublicKey
 [in] pointer to octet string of public key, which is of the same format as base point G. More...
 
uint8_t * pOutputR
 [out] pointer to memory area in which signature R calculated by verify function will be exported if signature is valid. More...
 
uint32_t optLen
 [in] packed options (reserved) and lengths: bits 0~7: byteLenHash: length of the string of message digest; bits 8~31: reserved. More...
 
+

Detailed Description

+

Parameter structure for function mcuxClEcc_Verify.

+

Field Documentation

+ +

◆ curveParam

+ +
+
+ + + + +
mcuxClEcc_DomainParam_t mcuxClEcc_Verify_Param_t::curveParam
+
+ +

[in] structure of pointers to curve parameters and length of parameters.

+ +
+
+ +

◆ pPrecG

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Verify_Param_t::pPrecG
+
+ +

[in] pointer to octet string of pre-computed point of base point G, which is of the same format as base point G.

+

It is calculated as (2 ^ (nByteLength * 4)) * G.

+ +
+
+ +

◆ pHash

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Verify_Param_t::pHash
+
+ +

[in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen).

+ +
+
+ +

◆ pSignature

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Verify_Param_t::pSignature
+
+ +

[in] pointer to octet string of signature R and S.

+

Each of R and S is a Big-endian octet string of the exact length curveParam.byteLenN. The string of R is followed by the string of S.

+ +
+
+ +

◆ pPublicKey

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_Verify_Param_t::pPublicKey
+
+ +

[in] pointer to octet string of public key, which is of the same format as base point G.

+ +
+
+ +

◆ pOutputR

+ +
+
+ + + + +
uint8_t* mcuxClEcc_Verify_Param_t::pOutputR
+
+ +

[out] pointer to memory area in which signature R calculated by verify function will be exported if signature is valid.

+

It will be stored as a Big-endian octet string of the exact length curveParam.byteLenN.

+ +
+
+ +

◆ optLen

+ +
+
+ + + + +
uint32_t mcuxClEcc_Verify_Param_t::optLen
+
+ +

[in] packed options (reserved) and lengths: bits 0~7: byteLenHash: length of the string of message digest; bits 8~31: reserved.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00985.js b/components/els_pkc/doc/mcxn/html/a00985.js new file mode 100644 index 000000000..88703315d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00985.js @@ -0,0 +1,10 @@ +var a00985 = +[ + [ "curveParam", "a00985.html#a58660c912b751cbea8360e214c482b42", null ], + [ "pPrecG", "a00985.html#ae5ba73e49b3346a860000f13d05bfbf0", null ], + [ "pHash", "a00985.html#adb5823e73ed5542ddd0b4a7103e62f1f", null ], + [ "pSignature", "a00985.html#ac9477410362aebdb892fdf382864342c", null ], + [ "pPublicKey", "a00985.html#a2db1a83966c659495b7bca80d7b5ab25", null ], + [ "pOutputR", "a00985.html#a6b6eb3da4f84de13269bb74d79583b51", null ], + [ "optLen", "a00985.html#afa16cb1249abe8848bfe2beeb909c4f3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00989.html b/components/els_pkc/doc/mcxn/html/a00989.html new file mode 100644 index 000000000..e434c2454 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00989.html @@ -0,0 +1,232 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_PointMult_Param_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEcc_PointMult_Param_t Struct Reference
mcuxClEcc » mcuxClEcc_Types
+
+
+ +

Parameter structure for function mcuxClEcc_PointMult. + More...

+ +

#include <mcuxClEcc_Types.h>

+ + + + + + + + + + + + + + + + + +

+Data Fields

mcuxClEcc_DomainParam_t curveParam
 [in] structure of pointers to curve parameters and length of parameters. More...
 
const uint8_t * pScalar
 [in] pointer to octet string of scalar d, which is of the same format as base point order n. More...
 
const uint8_t * pPoint
 [in] pointer to octet string of EC point Q, which is of the same format as base point G. More...
 
uint8_t * pResult
 [out] pointer to memory area, where the result R = dQ will be exported if PointMult is executed successfully. More...
 
uint32_t optLen
 [in] packed options (reserved): bits 0~31: reserved. More...
 
+

Detailed Description

+

Parameter structure for function mcuxClEcc_PointMult.

+

Field Documentation

+ +

◆ curveParam

+ +
+
+ + + + +
mcuxClEcc_DomainParam_t mcuxClEcc_PointMult_Param_t::curveParam
+
+ +

[in] structure of pointers to curve parameters and length of parameters.

+ +
+
+ +

◆ pScalar

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_PointMult_Param_t::pScalar
+
+ +

[in] pointer to octet string of scalar d, which is of the same format as base point order n.

+ +
+
+ +

◆ pPoint

+ +
+
+ + + + +
const uint8_t* mcuxClEcc_PointMult_Param_t::pPoint
+
+ +

[in] pointer to octet string of EC point Q, which is of the same format as base point G.

+ +
+
+ +

◆ pResult

+ +
+
+ + + + +
uint8_t* mcuxClEcc_PointMult_Param_t::pResult
+
+ +

[out] pointer to memory area, where the result R = dQ will be exported if PointMult is executed successfully.

+

It will be stored in the same format as the base point G.

+ +
+
+ +

◆ optLen

+ +
+
+ + + + +
uint32_t mcuxClEcc_PointMult_Param_t::optLen
+
+ +

[in] packed options (reserved): bits 0~31: reserved.

+

CAUTION always set optLen = 0.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00989.js b/components/els_pkc/doc/mcxn/html/a00989.js new file mode 100644 index 000000000..f8fbcbbdb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00989.js @@ -0,0 +1,8 @@ +var a00989 = +[ + [ "curveParam", "a00989.html#a264c295859d39a968b32efbc4f03942a", null ], + [ "pScalar", "a00989.html#a661018eb3da69cf8aa41f08690abc10a", null ], + [ "pPoint", "a00989.html#aa8a74b645f7f8b9c611afa1df8c6b523", null ], + [ "pResult", "a00989.html#a6bf3d35fa5651ee8eacd77d9ce1d97bf", null ], + [ "optLen", "a00989.html#a037bdeafd85441ec7c9a5edde80ed772", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00993.html b/components/els_pkc/doc/mcxn/html/a00993.html new file mode 100644 index 000000000..4d3125ee5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00993.html @@ -0,0 +1,157 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Weier_BasicDomainParams_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEcc_Weier_BasicDomainParams_t Struct Reference
+
+
+ +

Structure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1. + More...

+ +

#include <mcuxClEcc_WeierECC.h>

+ + + + + + + + + + + + + + + + +

+Data Fields

+const uint8_t * pP
 
+uint32_t pLen
 
+const uint8_t * pA
 
+const uint8_t * pB
 
+const uint8_t * pG
 
+const uint8_t * pN
 
+uint32_t nLen
 
+

Detailed Description

+

Structure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1.

+
Examples
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c.
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00993.js b/components/els_pkc/doc/mcxn/html/a00993.js new file mode 100644 index 000000000..f18a14137 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00993.js @@ -0,0 +1,10 @@ +var a00993 = +[ + [ "pP", "a00993.html#a7379d70ed28ccf53930c81ab03a1c3f6", null ], + [ "pLen", "a00993.html#a359859c7c6025790c1bc242a8a4abce1", null ], + [ "pA", "a00993.html#a9cf07507b4722d8aae5ac1832416bde1", null ], + [ "pB", "a00993.html#ac0cdc2af2879e34e6a67c1c7e54d0d56", null ], + [ "pG", "a00993.html#ada7a7f971d1c003be900818f1d0e30b2", null ], + [ "pN", "a00993.html#a84d45537f0688a91e4022287f4185029", null ], + [ "nLen", "a00993.html#ac9197a818ab1b47c887fe78127084ea9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a00997.html b/components/els_pkc/doc/mcxn/html/a00997.html new file mode 100644 index 000000000..7390a25a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00997.html @@ -0,0 +1,384 @@ + + + + + + + +MCUX CLNS: mcuxClEls_AeadOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_AeadOption_t Union Reference
mcuxClEls » mcuxClEls_Aead » mcuxClEls_Aead_Types
+
+
+ +

Command option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async, mcuxClEls_Aead_UpdateData_Async and mcuxClEls_Aead_Finalize_Async. + More...

+ +

#include <mcuxClEls_Aead.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_AeadOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:1
 RFU. More...
 
   uint32_t   dcrpt:1
 Defines if encryption or decryption shall be performed. More...
 
   uint32_t   acpmod:2
 This field is managed internally. More...
 
   uint32_t   acpsoe:1
 This field is managed internally. More...
 
   uint32_t   acpsie:1
 This field is managed internally. More...
 
   uint32_t   msgendw:4
 The size of the last data block (plain/cipher text) in bytes, without padding. More...
 
   uint32_t   lastinit:1
 Defines whether this is the last call to init. More...
 
   uint32_t   __pad1__:2
 RFU. More...
 
   uint32_t   extkey:1
 Defines whether an external key shall be used. More...
 
   uint32_t   __pad2__:18
 RFU. More...
 
} bits
 Access mcuxClEls_AeadOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async, mcuxClEls_Aead_UpdateData_Async and mcuxClEls_Aead_Finalize_Async.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_AeadOption_t::word
+
+ +

Access mcuxClEls_AeadOption_t word-wise.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ dcrpt

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::dcrpt
+
+ +

Defines if encryption or decryption shall be performed.

+ +
+
+ +

◆ acpmod

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::acpmod
+
+ +

This field is managed internally.

+ +
+
+ +

◆ acpsoe

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::acpsoe
+
+ +

This field is managed internally.

+ +
+
+ +

◆ acpsie

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::acpsie
+
+ +

This field is managed internally.

+ +
+
+ +

◆ msgendw

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::msgendw
+
+ +

The size of the last data block (plain/cipher text) in bytes, without padding.

+ +
+
+ +

◆ lastinit

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::lastinit
+
+ +

Defines whether this is the last call to init.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ extkey

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::extkey
+
+ +

Defines whether an external key shall be used.

+ +
+
+ +

◆ __pad2__

+ +
+
+ + + + +
uint32_t mcuxClEls_AeadOption_t::__pad2__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_AeadOption_t::bits
+
+ +

Access mcuxClEls_AeadOption_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a00997.js b/components/els_pkc/doc/mcxn/html/a00997.js new file mode 100644 index 000000000..f52e11e93 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a00997.js @@ -0,0 +1,16 @@ +var a00997 = +[ + [ "value", "a00997.html#ac8b3278eb96cd5ca0e15b9b2318305a7", null ], + [ "word", "a00997.html#a6a1cf6dca7babcb5b673312d79c3db9e", null ], + [ "__pad0__", "a00997.html#a55a86ab29b1e20072f48c56470568824", null ], + [ "dcrpt", "a00997.html#aabfd8fc5389ae7bfa2dea92c42441555", null ], + [ "acpmod", "a00997.html#a2504aa4fde601569a6c27276e76802f3", null ], + [ "acpsoe", "a00997.html#a77636eb7e553de47143580de37585920", null ], + [ "acpsie", "a00997.html#a5fafad6f592dfb928316273b5ccbec12", null ], + [ "msgendw", "a00997.html#a6e7b66230e97b647ba209b8f5eb68d2f", null ], + [ "lastinit", "a00997.html#a70ab6c857c7ae2e10b2f0580e4ea3669", null ], + [ "__pad1__", "a00997.html#a6b276f4a8ddbf8c2f337ad23c52d6963", null ], + [ "extkey", "a00997.html#a6e8a89cd7914a8f587ae7d2888a1e7cd", null ], + [ "__pad2__", "a00997.html#ae06263ba435ff9824be1f20c8f20b96c", null ], + [ "bits", "a00997.html#a2d11453f5716e58c8b34e92d434edd1b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01009.html b/components/els_pkc/doc/mcxn/html/a01009.html new file mode 100644 index 000000000..92077d1a5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01009.html @@ -0,0 +1,357 @@ + + + + + + + +MCUX CLNS: mcuxClEls_CipherOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_CipherOption_t Union Reference
mcuxClEls » mcuxClEls_Cipher » mcuxClEls_Cipher_Types
+
+
+ +

Command option bit field for mcuxClEls_Cipher_Async. + More...

+ +

#include <mcuxClEls_Cipher.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_CipherOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:1
 RFU. More...
 
   uint32_t   dcrpt:1
 Define operation mode. More...
 
   uint32_t   cphmde:2
 Define cipher mode. More...
 
   uint32_t   cphsoe:1
 Define whether the ELS internal cipher state should be extracted to external memory or kept internally. More...
 
   uint32_t   cphsie:1
 Define whether an external provided cipher state should be imported from external memory. More...
 
   uint32_t   __pad1__:7
 RFU. More...
 
   uint32_t   extkey:1
 Define whether an external key from memory or ELS internal key should be used. More...
 
   uint32_t   __pad2__:18
 RFU. More...
 
} bits
 Access mcuxClEls_CipherOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Cipher_Async.

+

Bit field to configure mcuxClEls_Cipher_Async. See MCUXCLELS_CIPHER_ for possible options.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_CipherOption_t::word
+
+ +

Access mcuxClEls_CipherOption_t word-wise.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ dcrpt

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::dcrpt
+
+ +

Define operation mode.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ cphmde

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::cphmde
+
+ +

Define cipher mode.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ cphsoe

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::cphsoe
+
+ +

Define whether the ELS internal cipher state should be extracted to external memory or kept internally.

+ +
+
+ +

◆ cphsie

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::cphsie
+
+ +

Define whether an external provided cipher state should be imported from external memory.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ extkey

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::extkey
+
+ +

Define whether an external key from memory or ELS internal key should be used.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+ +

◆ __pad2__

+ +
+
+ + + + +
uint32_t mcuxClEls_CipherOption_t::__pad2__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_CipherOption_t::bits
+
+ +

Access mcuxClEls_CipherOption_t bit-wise.

+
Examples
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c, and mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01009.js b/components/els_pkc/doc/mcxn/html/a01009.js new file mode 100644 index 000000000..dc4d6f48e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01009.js @@ -0,0 +1,14 @@ +var a01009 = +[ + [ "value", "a01009.html#a1c724d7ce478fcbb4cdd0ccb5c1fd899", null ], + [ "word", "a01009.html#afd7050544cd985c2dda66061e0f0c44f", null ], + [ "__pad0__", "a01009.html#abb6ec00ab841f6edcc37f6f51fb35975", null ], + [ "dcrpt", "a01009.html#ada47dbd9ac0d8ed1b171e4742ed5d73a", null ], + [ "cphmde", "a01009.html#a2e1e4a5d815c2559f0ef02e4fd0e5523", null ], + [ "cphsoe", "a01009.html#aa37b413e9a8ffa66655bc529aadaadbc", null ], + [ "cphsie", "a01009.html#af8735651384f21746fcea24b5c935a1d", null ], + [ "__pad1__", "a01009.html#a8b8096d5f06a8f303976697a0fa369aa", null ], + [ "extkey", "a01009.html#a833ce63bdab590215c35b82767479eee", null ], + [ "__pad2__", "a01009.html#a568f1ef7bba7f45209bf0cf43bb66b45", null ], + [ "bits", "a01009.html#af61168dc7998ed7862a56c85b64871c0", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01021.html b/components/els_pkc/doc/mcxn/html/a01021.html new file mode 100644 index 000000000..620862059 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01021.html @@ -0,0 +1,327 @@ + + + + + + + +MCUX CLNS: mcuxClEls_CmacOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_CmacOption_t Union Reference
mcuxClEls » mcuxClEls_Cmac » mcuxClEls_Cmac_Types
+
+
+ +

Command option bit field for mcuxClEls_Cmac_Async. + More...

+ +

#include <mcuxClEls_Cmac.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_CmacOption_t word-wise. More...
 
struct {
   uint32_t   initialize: 1
 Request initial processing for the first block of the message. More...
 
   uint32_t   finalize: 1
 Request final processing for the last block of the message. More...
 
   uint32_t   soe: 1
 This field is managed internally. More...
 
   uint32_t   sie: 1
 This field is managed internally. More...
 
   uint32_t   __pad0__:9
 RFU. More...
 
   uint32_t   extkey:1
 An external key should be used. More...
 
   uint32_t   __pad1__:18
 RFU. More...
 
} bits
 Access mcuxClEls_CmacOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Cmac_Async.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_CmacOption_t::word
+
+ +

Access mcuxClEls_CmacOption_t word-wise.

+ +
+
+ +

◆ initialize

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::initialize
+
+ +

Request initial processing for the first block of the message.

+ +
+
+ +

◆ finalize

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::finalize
+
+ +

Request final processing for the last block of the message.

+ +
+
+ +

◆ soe

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::soe
+
+ +

This field is managed internally.

+ +
+
+ +

◆ sie

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::sie
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ extkey

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::extkey
+
+ +

An external key should be used.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_CmacOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_CmacOption_t::bits
+
+ +

Access mcuxClEls_CmacOption_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01021.js b/components/els_pkc/doc/mcxn/html/a01021.js new file mode 100644 index 000000000..eb27737ba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01021.js @@ -0,0 +1,13 @@ +var a01021 = +[ + [ "value", "a01021.html#ab326f666bbbcabd39dc0bd26a83fa5c0", null ], + [ "word", "a01021.html#aa34c3bf115a202c3c96b967bc6114498", null ], + [ "initialize", "a01021.html#a90660bb1c9ee7d9f1d53209ab53dba4b", null ], + [ "finalize", "a01021.html#aabd3ce3a952bdd2279b7f4d0a2e22da8", null ], + [ "soe", "a01021.html#a69e48d5d1edf8300761b237872e4192f", null ], + [ "sie", "a01021.html#ab165c41c5cf41abf2b463ab742fa0c1b", null ], + [ "__pad0__", "a01021.html#add5bf1feb8f2a41a0f46c1bb06f15db0", null ], + [ "extkey", "a01021.html#a1d6db09e93aaf0c0d428e719dbff29fe", null ], + [ "__pad1__", "a01021.html#ace1fa4ccaa7741b93563ac6ace23989d", null ], + [ "bits", "a01021.html#a6cb17fd040a2db25cdaafe3e042b0831", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01033.html b/components/els_pkc/doc/mcxn/html/a01033.html new file mode 100644 index 000000000..d6284bce0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01033.html @@ -0,0 +1,302 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HwVersion_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HwVersion_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Result type of mcuxClEls_GetHwVersion. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_HwVersion_t word-wise. More...
 
struct {
   uint32_t   revision:4
 Revision number. More...
 
   uint32_t   minor:8
 Minor version. More...
 
   uint32_t   major:4
 Major version. More...
 
   uint32_t   level:4
 Release level version. More...
 
   uint32_t   __pad0__:12
 RFU. More...
 
} bits
 Access mcuxClEls_HwVersion_t bit-wise. More...
 
+

Detailed Description

+

Result type of mcuxClEls_GetHwVersion.

+

Contains the ELS version value.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwVersion_t::word
+
+ +

Access mcuxClEls_HwVersion_t word-wise.

+ +
+
+ +

◆ revision

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::revision
+
+ +

Revision number.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ minor

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::minor
+
+ +

Minor version.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ major

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::major
+
+ +

Major version.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ level

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::level
+
+ +

Release level version.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwVersion_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwVersion_t::bits
+
+ +

Access mcuxClEls_HwVersion_t bit-wise.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01033.js b/components/els_pkc/doc/mcxn/html/a01033.js new file mode 100644 index 000000000..f0be3cf77 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01033.js @@ -0,0 +1,11 @@ +var a01033 = +[ + [ "value", "a01033.html#a5e9b7103d2b419e9d860c04eb142d6e2", null ], + [ "word", "a01033.html#a87650934fb456d15383c0e0de64f93b2", null ], + [ "revision", "a01033.html#a11c1bba1b577058ea774f9fb51dfd449", null ], + [ "minor", "a01033.html#a648e4b690824c4652c70d707e00b6ffe", null ], + [ "major", "a01033.html#a0c4765f9784a475579e0fd433a753011", null ], + [ "level", "a01033.html#a362c318252fad3db6e55fde7dac2572f", null ], + [ "__pad0__", "a01033.html#a3f71ee0da1f604f06bce53faaee88549", null ], + [ "bits", "a01033.html#a107c920f079a09f0078dd0791faa2110", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01045.html b/components/els_pkc/doc/mcxn/html/a01045.html new file mode 100644 index 000000000..aa1ce4019 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01045.html @@ -0,0 +1,429 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HwState_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HwState_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Result type of mcuxClEls_GetHwState. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_HwState_t word-wise. More...
 
struct {
   uint32_t   busy:1
 ELS is busy. More...
 
   uint32_t   irq:1
 ELS interrupt activated. More...
 
   uint32_t   err:1
 ELS is in error state. More...
 
   uint32_t   prngready:1
 ELS PRNG is seeded and ready to use. More...
 
   uint32_t   ecdsavfy:2
 ECDSA verify operation state (For possible values of this field, see MCUXCLELS_STATUS_ECDSAVFY_) More...
 
   uint32_t   pprot:2
 The privilege/security level of the most recently started ELS command (For possible values of this field, see MCUXCLELS_STATUS_PPROT_) More...
 
   uint32_t   drbgentlvl:2
 Entropy quality of the current DRBG instance (For possible values of this field, see MCUXCLELS_STATUS_DRBGENTLVL_) More...
 
   uint32_t   dtrng_busy: 1
 Indicates the DTRNG is gathering entropy. More...
 
   uint32_t   __pad0__:2
 RFU. More...
 
   uint32_t   __pad1__:3
 RFU. More...
 
   uint32_t   __pad2__:1
 RFU. More...
 
   uint32_t   __pad3__:15
 RFU. More...
 
} bits
 Access mcuxClEls_HwState_t bit-wise. More...
 
+

Detailed Description

+

Result type of mcuxClEls_GetHwState.

+

Contains ELS status information.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwState_t::word
+
+ +

Access mcuxClEls_HwState_t word-wise.

+ +
+
+ +

◆ busy

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::busy
+
+ +

ELS is busy.

+ +
+
+ +

◆ irq

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::irq
+
+ +

ELS interrupt activated.

+ +
+
+ +

◆ err

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::err
+
+ +

ELS is in error state.

+ +
+
+ +

◆ prngready

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::prngready
+
+ +

ELS PRNG is seeded and ready to use.

+ +
+
+ +

◆ ecdsavfy

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::ecdsavfy
+
+ +

ECDSA verify operation state (For possible values of this field, see MCUXCLELS_STATUS_ECDSAVFY_)

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ pprot

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::pprot
+
+ +

The privilege/security level of the most recently started ELS command (For possible values of this field, see MCUXCLELS_STATUS_PPROT_)

+ +
+
+ +

◆ drbgentlvl

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::drbgentlvl
+
+ +

Entropy quality of the current DRBG instance (For possible values of this field, see MCUXCLELS_STATUS_DRBGENTLVL_)

+ +
+
+ +

◆ dtrng_busy

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::dtrng_busy
+
+ +

Indicates the DTRNG is gathering entropy.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ __pad2__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::__pad2__
+
+ +

RFU.

+ +
+
+ +

◆ __pad3__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwState_t::__pad3__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwState_t::bits
+
+ +

Access mcuxClEls_HwState_t bit-wise.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01045.js b/components/els_pkc/doc/mcxn/html/a01045.js new file mode 100644 index 000000000..823174fbd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01045.js @@ -0,0 +1,18 @@ +var a01045 = +[ + [ "value", "a01045.html#a9e0ca3d1f7797c407e594e55411549b0", null ], + [ "word", "a01045.html#a8318bd94bd3469bac07874ba2921d0cf", null ], + [ "busy", "a01045.html#a453ae753658b4809ea3141fffd5641c8", null ], + [ "irq", "a01045.html#afaa797f8db7f6252bf4ae54eb875c7fd", null ], + [ "err", "a01045.html#a5513d9d58397ac4701044421f2c8fd28", null ], + [ "prngready", "a01045.html#afbd164dd41b80e5a24310b6dac33cf79", null ], + [ "ecdsavfy", "a01045.html#a41492f22ac15d4cc4feebd517faa75ba", null ], + [ "pprot", "a01045.html#ac5b11ab2a0744e13303e920bee052f5b", null ], + [ "drbgentlvl", "a01045.html#a87b6c5ce545619bb478efcc020f862ff", null ], + [ "dtrng_busy", "a01045.html#a05b012990a92e9deaada4a5d87ac380a", null ], + [ "__pad0__", "a01045.html#ae4d9f2540dc7380b776ff6de6325c22f", null ], + [ "__pad1__", "a01045.html#aacebdfe99f0d29f126adc2a9d42a4b22", null ], + [ "__pad2__", "a01045.html#a68593765ff0c58861d600be91ee332a3", null ], + [ "__pad3__", "a01045.html#a240bdaa5a99cd057983b3cbe28e33fb1", null ], + [ "bits", "a01045.html#a3a7dbe3fd3f4e92c059cb39a04ac863e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01057.html b/components/els_pkc/doc/mcxn/html/a01057.html new file mode 100644 index 000000000..affd70ccd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01057.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionEn_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_InterruptOptionEn_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Command option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_InterruptOptionEn_t word-wise. More...
 
struct {
   uint32_t   elsint:1
 Whether ELS interrupt should be used. (For possible values of this field, see mcuxClEls_InterruptOptionEn_t) More...
 
   uint32_t   __pad0__:1
 RFU. More...
 
   uint32_t   __pad1__:30
 RFU. More...
 
} bits
 Access mcuxClEls_InterruptOptionEn_t bit-wise. More...
 
+

Detailed Description

+

Command option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags.

+

Used to get/set ELS interrupt enable options.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionEn_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionEn_t::word
+
+ +

Access mcuxClEls_InterruptOptionEn_t word-wise.

+ +
+
+ +

◆ elsint

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionEn_t::elsint
+
+ +

Whether ELS interrupt should be used. (For possible values of this field, see mcuxClEls_InterruptOptionEn_t)

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionEn_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionEn_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionEn_t::bits
+
+ +

Access mcuxClEls_InterruptOptionEn_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01057.js b/components/els_pkc/doc/mcxn/html/a01057.js new file mode 100644 index 000000000..e3b4719f1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01057.js @@ -0,0 +1,9 @@ +var a01057 = +[ + [ "value", "a01057.html#a24184dcdf86670224ea536fc20a0e4d8", null ], + [ "word", "a01057.html#ad7e19b6dde1c236ad751eb9208e942db", null ], + [ "elsint", "a01057.html#a1ceef382dbc3fbafdff1d553658c7ea9", null ], + [ "__pad0__", "a01057.html#a71d456bef9a7a21d8ff55bc711a6a3bc", null ], + [ "__pad1__", "a01057.html#a502fdb51eeb304aabfd1ed4550ac3258", null ], + [ "bits", "a01057.html#ad3bc5d3ed1f3a1e38687c1742d3cf8f3", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01069.html b/components/els_pkc/doc/mcxn/html/a01069.html new file mode 100644 index 000000000..68a1a1b9b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01069.html @@ -0,0 +1,251 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionRst_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_InterruptOptionRst_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Type to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_InterruptOptionRst_t word-wise. More...
 
struct {
   uint32_t   elsint:1
 Whether ELS interrupt should be reset. (For possible values of this field, see mcuxClEls_InterruptOptionRst_t) More...
 
   uint32_t   __pad0__:1
 RFU. More...
 
   uint32_t   __pad1__:30
 RFU. More...
 
} bits
 Access mcuxClEls_InterruptOptionRst_t bit-wise. More...
 
+

Detailed Description

+

Type to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionRst_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionRst_t::word
+
+ +

Access mcuxClEls_InterruptOptionRst_t word-wise.

+ +
+
+ +

◆ elsint

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionRst_t::elsint
+
+ +

Whether ELS interrupt should be reset. (For possible values of this field, see mcuxClEls_InterruptOptionRst_t)

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionRst_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionRst_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionRst_t::bits
+
+ +

Access mcuxClEls_InterruptOptionRst_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01069.js b/components/els_pkc/doc/mcxn/html/a01069.js new file mode 100644 index 000000000..8417a2ae2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01069.js @@ -0,0 +1,9 @@ +var a01069 = +[ + [ "value", "a01069.html#afe633f619c2da24bd5a99cf97782924b", null ], + [ "word", "a01069.html#ad45dfa4c603c021060fc0b4fdf0f769d", null ], + [ "elsint", "a01069.html#a8123125e41c363c03e6a671e94543d3d", null ], + [ "__pad0__", "a01069.html#ad560c85d9ea7975330ec5a2e207b30c0", null ], + [ "__pad1__", "a01069.html#a188253366e073fdcbdccbaa41ccbe915", null ], + [ "bits", "a01069.html#a38fff411deb5bfd137a206a35305d3e9", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01081.html b/components/els_pkc/doc/mcxn/html/a01081.html new file mode 100644 index 000000000..ef66be287 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01081.html @@ -0,0 +1,251 @@ + + + + + + + +MCUX CLNS: mcuxClEls_InterruptOptionSet_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_InterruptOptionSet_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Type to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_InterruptOptionSet_t word-wise. More...
 
struct {
   uint32_t   elsint:1
 Whether ELS interrupt should be set. (For possible values of this field, see mcuxClEls_InterruptOptionSet_t) More...
 
   uint32_t   __pad0__:2
 RFU. More...
 
   uint32_t   __pad1__:29
 RFU. More...
 
} bits
 Access mcuxClEls_InterruptOptionSet_t bit-wise. More...
 
+

Detailed Description

+

Type to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionSet_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionSet_t::word
+
+ +

Access mcuxClEls_InterruptOptionSet_t word-wise.

+ +
+
+ +

◆ elsint

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionSet_t::elsint
+
+ +

Whether ELS interrupt should be set. (For possible values of this field, see mcuxClEls_InterruptOptionSet_t)

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionSet_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_InterruptOptionSet_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_InterruptOptionSet_t::bits
+
+ +

Access mcuxClEls_InterruptOptionSet_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01081.js b/components/els_pkc/doc/mcxn/html/a01081.js new file mode 100644 index 000000000..51e1edff2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01081.js @@ -0,0 +1,9 @@ +var a01081 = +[ + [ "value", "a01081.html#a58934a4a256905327206ee08d8c5931f", null ], + [ "word", "a01081.html#ac3c1022b8a8d5034511fd6ffcb76625d", null ], + [ "elsint", "a01081.html#a694dd46e51d111832674fdd7827ba7a2", null ], + [ "__pad0__", "a01081.html#a6f7f7fb21a47e0ba886c9c5ebdaae7bf", null ], + [ "__pad1__", "a01081.html#a3a1d6b3eaa5f8be52531ddb20f3e85c8", null ], + [ "bits", "a01081.html#ac8b9b47932507184288a99d01ee45b39", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01093.html b/components/els_pkc/doc/mcxn/html/a01093.html new file mode 100644 index 000000000..e72f45cf8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01093.html @@ -0,0 +1,668 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HwConfig_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HwConfig_t Union Reference
mcuxClEls » mcuxClEls_Common » mcuxClEls_Common_Types
+
+
+ +

Result type of #mcuxClEls_GetHwConfig. + More...

+ +

#include <mcuxClEls_Common.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_InterruptOptionSet_t word-wise. More...
 
struct {
   uint32_t   ciphersup:1
 Indicates whether the cipher command is supported. More...
 
   uint32_t   authciphersup:1
 Indicates whether the auth_cipher command is supported. More...
 
   uint32_t   ecsignsup:1
 Indicates whether the ecsign command is supported. More...
 
   uint32_t   ecvfysup:1
 Indicates whether the ecvfy command is supported. More...
 
   uint32_t   eckxchsup:1
 Indicates whether the dhkey_xch command is supported. More...
 
   uint32_t   keygensup:1
 Indicates whether the keygen command is supported. More...
 
   uint32_t   keyinsup:1
 Indicates whether the keyin command is supported. More...
 
   uint32_t   keyoutsup:1
 Indicates whether the keyout command is supported. More...
 
   uint32_t   kdeletesup:1
 Indicates whether the kdelete command is supported. More...
 
   uint32_t   keyprovsup:1
 Indicates whether the keyprov command is supported. More...
 
   uint32_t   ckdfsup:1
 Indicates whether the ckdf command is supported. More...
 
   uint32_t   hkdfsup:1
 Indicates whether the hkdf command is supported. More...
 
   uint32_t   tlsinitsup:1
 Indicates whether the tls_init command is supported. More...
 
   uint32_t   hashsup:1
 Indicates whether the hash command is supported. More...
 
   uint32_t   hmacsup:1
 Indicates whether the hmac command is supported. More...
 
   uint32_t   cmacsup:1
 Indicates whether the cmac command is supported. More...
 
   uint32_t   drbgreqsup:1
 Indicates whether the drbg_req command is supported. More...
 
   uint32_t   drbgtestsup:1
 Indicates whether the drbg_test command is supported. More...
 
   uint32_t   dtrgncfgloadsup:1
 Indicates whether the dtrng_cfg_load command is is supported. More...
 
   uint32_t   dtrngevalsup:1
 Indicates whether the dtrng_eval command is supported. More...
 
   uint32_t   gdetcfgloadsup:1
 Indicates whether the gdet_cfg_load command is supported. More...
 
   uint32_t   gdettrimsup:1
 Indicates whether the gdet_trim command is supported. More...
 
   uint32_t   __pad0__:10
 RFU. More...
 
} bits
 Access mcuxClEls_InterruptOptionSet_t bit-wise. More...
 
+

Detailed Description

+

Result type of #mcuxClEls_GetHwConfig.

+

Contains ELS configuration values.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwConfig_t::word
+
+ +

Access mcuxClEls_InterruptOptionSet_t word-wise.

+ +
+
+ +

◆ ciphersup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::ciphersup
+
+ +

Indicates whether the cipher command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ authciphersup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::authciphersup
+
+ +

Indicates whether the auth_cipher command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ ecsignsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::ecsignsup
+
+ +

Indicates whether the ecsign command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ ecvfysup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::ecvfysup
+
+ +

Indicates whether the ecvfy command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ eckxchsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::eckxchsup
+
+ +

Indicates whether the dhkey_xch command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ keygensup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::keygensup
+
+ +

Indicates whether the keygen command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ keyinsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::keyinsup
+
+ +

Indicates whether the keyin command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ keyoutsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::keyoutsup
+
+ +

Indicates whether the keyout command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ kdeletesup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::kdeletesup
+
+ +

Indicates whether the kdelete command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ keyprovsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::keyprovsup
+
+ +

Indicates whether the keyprov command is supported.

+ +
+
+ +

◆ ckdfsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::ckdfsup
+
+ +

Indicates whether the ckdf command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ hkdfsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::hkdfsup
+
+ +

Indicates whether the hkdf command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ tlsinitsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::tlsinitsup
+
+ +

Indicates whether the tls_init command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ hashsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::hashsup
+
+ +

Indicates whether the hash command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ hmacsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::hmacsup
+
+ +

Indicates whether the hmac command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ cmacsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::cmacsup
+
+ +

Indicates whether the cmac command is supported.

+ +
+
+ +

◆ drbgreqsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::drbgreqsup
+
+ +

Indicates whether the drbg_req command is supported.

+ +
+
+ +

◆ drbgtestsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::drbgtestsup
+
+ +

Indicates whether the drbg_test command is supported.

+ +
+
+ +

◆ dtrgncfgloadsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::dtrgncfgloadsup
+
+ +

Indicates whether the dtrng_cfg_load command is is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ dtrngevalsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::dtrngevalsup
+
+ +

Indicates whether the dtrng_eval command is supported.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+ +

◆ gdetcfgloadsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::gdetcfgloadsup
+
+ +

Indicates whether the gdet_cfg_load command is supported.

+ +
+
+ +

◆ gdettrimsup

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::gdettrimsup
+
+ +

Indicates whether the gdet_trim command is supported.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_HwConfig_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_HwConfig_t::bits
+
+ +

Access mcuxClEls_InterruptOptionSet_t bit-wise.

+
Examples
mcuxClEls_Common_Get_Info_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01093.js b/components/els_pkc/doc/mcxn/html/a01093.js new file mode 100644 index 000000000..2f91b7b65 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01093.js @@ -0,0 +1,29 @@ +var a01093 = +[ + [ "value", "a01093.html#a2cf565902d36ad357eaaa793eb4be8d5", null ], + [ "word", "a01093.html#a57cd499ae60ad1bb19fc54517d9ff580", null ], + [ "ciphersup", "a01093.html#ac0db95aaf62ac50581111452e89de3ba", null ], + [ "authciphersup", "a01093.html#acd5dabf360244a33333e3063010ad26d", null ], + [ "ecsignsup", "a01093.html#ab5a3a301e2fa7ed724b1a10db46a4dc1", null ], + [ "ecvfysup", "a01093.html#a082dbc1af5f81f7d76e32c01e35a6c81", null ], + [ "eckxchsup", "a01093.html#ac9e323809993203e0867e37641f7d9e0", null ], + [ "keygensup", "a01093.html#add6853a64d3322d8400c601277d42afb", null ], + [ "keyinsup", "a01093.html#a10e2de8c251bc00183a2d578fb778661", null ], + [ "keyoutsup", "a01093.html#a6bbf59e55899238b17d7a1266d6a063a", null ], + [ "kdeletesup", "a01093.html#aff9488c467cfca4942ba41b51c4225b7", null ], + [ "keyprovsup", "a01093.html#a55ac97e5d1105cd9f5ac217d05a8e0c2", null ], + [ "ckdfsup", "a01093.html#a05b73ed0395351b9504c35f54ac50495", null ], + [ "hkdfsup", "a01093.html#af443a864be5d2d0ab3c6a2f007fe9afe", null ], + [ "tlsinitsup", "a01093.html#a9dc24a8f88688b9d4cc5c305acbf46e5", null ], + [ "hashsup", "a01093.html#ac5fc6ff1883c09e1ed72412f53514b13", null ], + [ "hmacsup", "a01093.html#a4cf06c58477f35949dc0089a3a3184ce", null ], + [ "cmacsup", "a01093.html#ad30966f27a451f027aed32c036289515", null ], + [ "drbgreqsup", "a01093.html#a1519b8980b5d2615c96ac1c788014e6d", null ], + [ "drbgtestsup", "a01093.html#ae70916d8e053e37a7de79db3c873cdd5", null ], + [ "dtrgncfgloadsup", "a01093.html#a1655b1afaf9b84514817f11e71f21232", null ], + [ "dtrngevalsup", "a01093.html#a7ab5fc2fd5378fbf9044f6eb47b74602", null ], + [ "gdetcfgloadsup", "a01093.html#a83e2de492b29950e62bdc159629a7e87", null ], + [ "gdettrimsup", "a01093.html#a546385b574e49302ba2e748303fa91a4", null ], + [ "__pad0__", "a01093.html#aa06967699abb851f567edb7ae687a0d2", null ], + [ "bits", "a01093.html#a95b4684aa6203efcdf26303743fdfcd5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01105.html b/components/els_pkc/doc/mcxn/html/a01105.html new file mode 100644 index 000000000..f305ff91e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01105.html @@ -0,0 +1,235 @@ + + + + + + + +MCUX CLNS: mcuxClEls_CommandCrcConfig_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_CommandCrcConfig_t Union Reference
mcuxClEls » mcuxClEls_Crc » mcuxClEls_Crc_Types
+
+
+ +

Type to control ELS Command CRC. + More...

+ +

#include <mcuxClEls_Crc.h>

+ + + + + + + + + + + + + + + + + + + + + +

+Data Fields

+struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 
struct {
   uint32_t   reset:1
 Reset the Command CRC to initial value, set by MCUXCLELS_CMD_CRC_RESET. More...
 
   uint32_t   enable:1
 Enable/Disable update of Command CRC value by executing commands, set with MCUXCLELS_CMD_CRC_ENABLE / MCUXCLELS_CMD_CRC_DISABLE. More...
 
   uint32_t   __pad0__: 30
 RFU. More...
 
} bits
 Access mcuxClEls_CommandCrcConfig_t bit-wise. More...
 
+

Detailed Description

+

Type to control ELS Command CRC.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_CommandCrcConfig_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ reset

+ +
+
+ + + + +
uint32_t mcuxClEls_CommandCrcConfig_t::reset
+
+ +

Reset the Command CRC to initial value, set by MCUXCLELS_CMD_CRC_RESET.

+ +
+
+ +

◆ enable

+ +
+
+ + + + +
uint32_t mcuxClEls_CommandCrcConfig_t::enable
+
+ +

Enable/Disable update of Command CRC value by executing commands, set with MCUXCLELS_CMD_CRC_ENABLE / MCUXCLELS_CMD_CRC_DISABLE.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_CommandCrcConfig_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_CommandCrcConfig_t::bits
+
+ +

Access mcuxClEls_CommandCrcConfig_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01105.js b/components/els_pkc/doc/mcxn/html/a01105.js new file mode 100644 index 000000000..787e9bd8e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01105.js @@ -0,0 +1,9 @@ +var a01105 = +[ + [ "value", "a01105.html#a4dc44ca29e9ef4bcea0b6469a5966f6d", null ], + [ "word", "a01105.html#aa9b1c3ce855f539fb39a251dc5fe0744", null ], + [ "reset", "a01105.html#ae72c778e615b7e6aa4e73eb242beb354", null ], + [ "enable", "a01105.html#a60c0c05eb7acf852589b6f5b7a7c9dd3", null ], + [ "__pad0__", "a01105.html#a49e0d7b8ada89de5bd766ac9cf2c3e27", null ], + [ "bits", "a01105.html#ac18d751428d40b3e3127a0779abc1cec", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01117.html b/components/els_pkc/doc/mcxn/html/a01117.html new file mode 100644 index 000000000..1f45daa3c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01117.html @@ -0,0 +1,296 @@ + + + + + + + +MCUX CLNS: mcuxClEls_EccSignOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_EccSignOption_t Union Reference
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Types
+
+
+ +

Command option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async. + More...

+ +

#include <mcuxClEls_Ecc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (Sign and Verify) option word values. More...
 
} word
 Access mcuxClEls_EccSignOption_t word-wise. More...
 
struct {
   uint32_t   echashchl:1
 Define type of input, plain message or hash of message. More...
 
   uint32_t   signrtf:1
 Define if signing the Run-Time Fingerprint. More...
 
   uint32_t   __pad0__:2
 RFU. More...
 
   uint32_t   revf:1
 This field is managed internally. More...
 
   uint32_t   __pad1__:27
 RFU. More...
 
} bits
 Access mcuxClEls_EccSignOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async.

+

See MCUXCLELS_ECC (Sign and Verify) option bit field values for possible options.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::value
+
+ +

Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (Sign and Verify) option word values.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccSignOption_t::word
+
+ +

Access mcuxClEls_EccSignOption_t word-wise.

+ +
+
+ +

◆ echashchl

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::echashchl
+
+ +

Define type of input, plain message or hash of message.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ signrtf

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::signrtf
+
+ +

Define if signing the Run-Time Fingerprint.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ revf

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::revf
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccSignOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccSignOption_t::bits
+
+ +

Access mcuxClEls_EccSignOption_t bit-wise.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01117.js b/components/els_pkc/doc/mcxn/html/a01117.js new file mode 100644 index 000000000..f1cac34c8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01117.js @@ -0,0 +1,11 @@ +var a01117 = +[ + [ "value", "a01117.html#a7e32d20de26a1ca2d7eee8fe2fd95456", null ], + [ "word", "a01117.html#a6f703afe07655c05795fd6061b321dc3", null ], + [ "echashchl", "a01117.html#ab825e88899ff7627304d25fbcc1adffd", null ], + [ "signrtf", "a01117.html#aa4bcc3f1aaf9e991e62cdc22ffd7500e", null ], + [ "__pad0__", "a01117.html#a0e9a4b194d887a2b2c4c2297c2cbd868", null ], + [ "revf", "a01117.html#aa75bf5c0b29ee02a16ca1b31e3300b0f", null ], + [ "__pad1__", "a01117.html#a5527caf737b06f5053f89c60354dbe65", null ], + [ "bits", "a01117.html#accf6312c26ce770b5647c4e45b00f7b5", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01129.html b/components/els_pkc/doc/mcxn/html/a01129.html new file mode 100644 index 000000000..a0f2ca0ac --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01129.html @@ -0,0 +1,273 @@ + + + + + + + +MCUX CLNS: mcuxClEls_EccVerifyOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_EccVerifyOption_t Union Reference
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Types
+
+
+ +

Command option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOption_t. + More...

+ +

#include <mcuxClEls_Ecc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (Sign and Verify) option word values. More...
 
} word
 Access mcuxClEls_EccVerifyOption_t word-wise. More...
 
struct {
   uint32_t   echashchl:1
 Define type of input, plain message or hash of message. More...
 
   uint32_t   __pad0__:3
 RFU. More...
 
   uint32_t   revf:1
 This field is managed internally. More...
 
   uint32_t   __pad1__:27
 RFU. More...
 
} bits
 Access mcuxClEls_EccVerifyOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOption_t.

+

See MCUXCLELS_ECC (Sign and Verify) option bit field values for possible options.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_EccVerifyOption_t::value
+
+ +

Access the bit field as a full word; initialize with a combination of constants from MCUXCLELS_ECC (Sign and Verify) option word values.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccVerifyOption_t::word
+
+ +

Access mcuxClEls_EccVerifyOption_t word-wise.

+ +
+
+ +

◆ echashchl

+ +
+
+ + + + +
uint32_t mcuxClEls_EccVerifyOption_t::echashchl
+
+ +

Define type of input, plain message or hash of message.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccVerifyOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ revf

+ +
+
+ + + + +
uint32_t mcuxClEls_EccVerifyOption_t::revf
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccVerifyOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccVerifyOption_t::bits
+
+ +

Access mcuxClEls_EccVerifyOption_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01129.js b/components/els_pkc/doc/mcxn/html/a01129.js new file mode 100644 index 000000000..b71e1d8e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01129.js @@ -0,0 +1,10 @@ +var a01129 = +[ + [ "value", "a01129.html#a73b0b8e42d753a97bb03cb053799e33a", null ], + [ "word", "a01129.html#a1d1416b8e584c34840183572e7b2df3d", null ], + [ "echashchl", "a01129.html#a2642a5936ec9f5c7394704161c984598", null ], + [ "__pad0__", "a01129.html#a7dffb127ef2f32236227c9023af7e5cd", null ], + [ "revf", "a01129.html#afbf76f7ebcfc43ca99708cd1064a651a", null ], + [ "__pad1__", "a01129.html#ad2bdfda87da142b43bfd1e64ee8bb072", null ], + [ "bits", "a01129.html#aa5f2cce580390956b07603eb64fe6fc7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01141.html b/components/els_pkc/doc/mcxn/html/a01141.html new file mode 100644 index 000000000..a281ecb39 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01141.html @@ -0,0 +1,340 @@ + + + + + + + +MCUX CLNS: mcuxClEls_EccKeyGenOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_EccKeyGenOption_t Union Reference
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Types
+
+
+ +

Command option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOption_t. + More...

+ +

#include <mcuxClEls_Ecc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYGEN option word values. More...
 
} word
 Access mcuxClEls_EccKeyGenOption_t word-wise. More...
 
struct {
   uint32_t   kgsign:1
 Define if signing the output public key. More...
 
   uint32_t   kgtypedh:1
 Define the usage of the output key. More...
 
   uint32_t   kgsrc:1
 Define if the output key is deterministic or random. More...
 
   uint32_t   skip_pbk:1
 Define if generating a public key. More...
 
   uint32_t   revf:1
 This field is managed internally. More...
 
   uint32_t   kgsign_rnd:1
 Define if using user provided random data for the signature. More...
 
   uint32_t   __pad0__:26
 RFU. More...
 
} bits
 Access mcuxClEls_EccKeyGenOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOption_t.

+

See MCUXCLELS_KEYGEN option bit field values for possible options.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYGEN option word values.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccKeyGenOption_t::word
+
+ +

Access mcuxClEls_EccKeyGenOption_t word-wise.

+ +
+
+ +

◆ kgsign

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::kgsign
+
+ +

Define if signing the output public key.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, and mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ kgtypedh

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::kgtypedh
+
+ +

Define the usage of the output key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ kgsrc

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::kgsrc
+
+ +

Define if the output key is deterministic or random.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ skip_pbk

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::skip_pbk
+
+ +

Define if generating a public key.

+ +
+
+ +

◆ revf

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::revf
+
+ +

This field is managed internally.

+ +
+
+ +

◆ kgsign_rnd

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::kgsign_rnd
+
+ +

Define if using user provided random data for the signature.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c.
+
+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyGenOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccKeyGenOption_t::bits
+
+ +

Access mcuxClEls_EccKeyGenOption_t bit-wise.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01141.js b/components/els_pkc/doc/mcxn/html/a01141.js new file mode 100644 index 000000000..de9b8d835 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01141.js @@ -0,0 +1,13 @@ +var a01141 = +[ + [ "value", "a01141.html#a2c377cdae550923ee7e1234735e08b40", null ], + [ "word", "a01141.html#ab5dac27ccbb4062c42c971d44e504519", null ], + [ "kgsign", "a01141.html#aa20a2dd1242cfa9c945d09332db760e1", null ], + [ "kgtypedh", "a01141.html#ade3f3190f07c3a1b8a5948988d3b85d5", null ], + [ "kgsrc", "a01141.html#aa60e98c0d7570daa80ab5536ebf71d94", null ], + [ "skip_pbk", "a01141.html#afa4cb29e6c55e30a30185180de2f8e49", null ], + [ "revf", "a01141.html#a7e2c0f35b5f6904c1a232f3552cb185f", null ], + [ "kgsign_rnd", "a01141.html#ab2d02455b74fc4f2999c8b579bd87c8d", null ], + [ "__pad0__", "a01141.html#ab6d97c184d6c34f0d6c1bc8e0a77057c", null ], + [ "bits", "a01141.html#afc19db0547800dd35ed3d3294831344b", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01153.html b/components/els_pkc/doc/mcxn/html/a01153.html new file mode 100644 index 000000000..bbeeab367 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01153.html @@ -0,0 +1,290 @@ + + + + + + + +MCUX CLNS: mcuxClEls_EccKeyExchOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_EccKeyExchOption_t Union Reference
mcuxClEls » mcuxClEls_Ecc » mcuxClEls_Ecc_Types
+
+
+ +

Command option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only. + More...

+ +

#include <mcuxClEls_Ecc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_EccKeyExchOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:4
 RFU. More...
 
   uint32_t   revf:1
 This field is managed internally. More...
 
   uint32_t   __pad1__:8
 RFU. More...
 
   uint32_t   extkey:1
 This field is managed internally. More...
 
   uint32_t   __pad2__:18
 RFU. More...
 
} bits
 Access mcuxClEls_EccKeyExchOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only.

+

Bit field to configure mcuxClEls_EccKeyExchOption_t.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccKeyExchOption_t::word
+
+ +

Access mcuxClEls_EccKeyExchOption_t word-wise.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ revf

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::revf
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ extkey

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::extkey
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad2__

+ +
+
+ + + + +
uint32_t mcuxClEls_EccKeyExchOption_t::__pad2__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_EccKeyExchOption_t::bits
+
+ +

Access mcuxClEls_EccKeyExchOption_t bit-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01153.js b/components/els_pkc/doc/mcxn/html/a01153.js new file mode 100644 index 000000000..a80fe4e0e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01153.js @@ -0,0 +1,11 @@ +var a01153 = +[ + [ "value", "a01153.html#aaa4e256f25f9c74123c28c5926d21ba2", null ], + [ "word", "a01153.html#a17969e2f10fec362e68869232cb1099b", null ], + [ "__pad0__", "a01153.html#a98a12e39b9f189c172f6b951c2ae781c", null ], + [ "revf", "a01153.html#a2a46aaff0c4f6f2cfa19b302ba713b43", null ], + [ "__pad1__", "a01153.html#a06d0377a60794946f8788a7fad8af177", null ], + [ "extkey", "a01153.html#ab28493ba971ceb64a4fa0f741e98358d", null ], + [ "__pad2__", "a01153.html#a82f1e57ea7fcdfd607a3954396e6ec84", null ], + [ "bits", "a01153.html#aa620a69ff6945f317f2df59bdf4284cd", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01165.html b/components/els_pkc/doc/mcxn/html/a01165.html new file mode 100644 index 000000000..c41ccc2e6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01165.html @@ -0,0 +1,357 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HashOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HashOption_t Union Reference
mcuxClEls » mcuxClEls_Hash » mcuxClEls_Hash_Types
+
+
+ +

Command option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. + More...

+ +

#include <mcuxClEls_Hash.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_HashOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:2
 RFU. More...
 
   uint32_t   hashini:1
 Defines if the hash engine shall be initialized. More...
 
   uint32_t   hashld:1
 Defines if the hash engine shall be initialized with an externally provided digest. More...
 
   uint32_t   hashmd:2
 Defines which hash algorithm shall be used. More...
 
   uint32_t   hashoe:1
 Defines if the hash digest shall be moved to the output buffer. More...
 
   uint32_t   rtfupd:1
 RTF (Runtime Fingerprint) Update. More...
 
   uint32_t   rtfoe:1
 RTF (Runtime Fingerprint) Output Enabled. More...
 
   uint32_t   __pad1__:23
 RFU. More...
 
} bits
 Access mcuxClEls_HashOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect.

+

Bit field to configure mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. See MCUXCLELS_HASH_ for possible options.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_HashOption_t::word
+
+ +

Access mcuxClEls_HashOption_t word-wise.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ hashini

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::hashini
+
+ +

Defines if the hash engine shall be initialized.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ hashld

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::hashld
+
+ +

Defines if the hash engine shall be initialized with an externally provided digest.

+ +
+
+ +

◆ hashmd

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::hashmd
+
+ +

Defines which hash algorithm shall be used.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ hashoe

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::hashoe
+
+ +

Defines if the hash digest shall be moved to the output buffer.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+ +

◆ rtfupd

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::rtfupd
+
+ +

RTF (Runtime Fingerprint) Update.

+ +
+
+ +

◆ rtfoe

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::rtfoe
+
+ +

RTF (Runtime Fingerprint) Output Enabled.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_HashOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_HashOption_t::bits
+
+ +

Access mcuxClEls_HashOption_t bit-wise.

+
Examples
mcuxClEls_Hash_Sha224_One_Block_example.c, mcuxClEls_Hash_Sha256_One_Block_example.c, mcuxClEls_Hash_Sha384_One_Block_example.c, and mcuxClEls_Hash_Sha512_One_Block_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01165.js b/components/els_pkc/doc/mcxn/html/a01165.js new file mode 100644 index 000000000..2c74a8e3c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01165.js @@ -0,0 +1,14 @@ +var a01165 = +[ + [ "value", "a01165.html#a71c7896e79c292ac111d85992a16c78d", null ], + [ "word", "a01165.html#a4addaf59a3d2ab2743fd4c622c0e97ac", null ], + [ "__pad0__", "a01165.html#aae0a2c87c57c974e9cb7a55126f95ca9", null ], + [ "hashini", "a01165.html#ac9b592abc979189fad34fde3ec0c163c", null ], + [ "hashld", "a01165.html#a4a982ed0c424187a716adba9c0c99996", null ], + [ "hashmd", "a01165.html#a91c25618e98d1a9db1b1b13cfe52495f", null ], + [ "hashoe", "a01165.html#a2a87b3f8cde5a5cfdbea784ca4c6a58a", null ], + [ "rtfupd", "a01165.html#a1d91adca6cd4e274287063d2ff8d1884", null ], + [ "rtfoe", "a01165.html#a8c09f754695c9adc3ffe482375fc5f36", null ], + [ "__pad1__", "a01165.html#a97d346a2d66df4edd1ab677769a7b648", null ], + [ "bits", "a01165.html#aacda3c97994f6b172c7fd69c89d275dc", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01177.html b/components/els_pkc/doc/mcxn/html/a01177.html new file mode 100644 index 000000000..51a1d0954 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01177.html @@ -0,0 +1,252 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HmacOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HmacOption_t Union Reference
mcuxClEls » mcuxClEls_Hmac » mcuxClEls_Hmac_Types
+
+
+ +

Command option bit field for mcuxClEls_Hmac_Async. + More...

+ +

#include <mcuxClEls_Hmac.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word. More...
 
} word
 Access mcuxClEls_CipherOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:13
 RFU. More...
 
   uint32_t   extkey:1
 Whether an external key should be used. More...
 
   uint32_t   __pad1__:18
 RFU. More...
 
} bits
 Access mcuxClEls_CipherOption_t word-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Hmac_Async.

+

Valid option values can be found under MCUXCLELS_HMAC_EXTERNAL_KEY_.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HmacOption_t::value
+
+ +

Accesses the bit field as a full word.

+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_HmacOption_t::word
+
+ +

Access mcuxClEls_CipherOption_t word-wise.

+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_HmacOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ extkey

+ +
+
+ + + + +
uint32_t mcuxClEls_HmacOption_t::extkey
+
+ +

Whether an external key should be used.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_HmacOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_HmacOption_t::bits
+
+ +

Access mcuxClEls_CipherOption_t word-wise.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01177.js b/components/els_pkc/doc/mcxn/html/a01177.js new file mode 100644 index 000000000..aa9ecc99e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01177.js @@ -0,0 +1,9 @@ +var a01177 = +[ + [ "value", "a01177.html#a577065f77e409f612e5a2fc2072b971d", null ], + [ "word", "a01177.html#a5f797c75232df146cecc9c76dd04d463", null ], + [ "__pad0__", "a01177.html#a590b1d47d31c598e6df237437a015b8e", null ], + [ "extkey", "a01177.html#a4e16fabb042914665cabe00f5d6a6795", null ], + [ "__pad1__", "a01177.html#afa33782e670b9a44a28f71cb097ad830", null ], + [ "bits", "a01177.html#ae06ed09126b22cf0131a97bff34cc166", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01189.html b/components/els_pkc/doc/mcxn/html/a01189.html new file mode 100644 index 000000000..89a40b767 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01189.html @@ -0,0 +1,188 @@ + + + + + + + +MCUX CLNS: mcuxClEls_CkdfOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_CkdfOption_t Union Reference
mcuxClEls » mcuxClEls_Kdf » mcuxClEls_Kdf_Macros » mcuxClEls_Kdf_Types
+
+
+ +

Internal command option bit field for CKDF functions. + More...

+ +

#include <mcuxClEls_Kdf.h>

+ + + + + + + + + + + + + + + + + + +

+Data Fields

+struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_. More...
 
} word
 
+struct {
+   uint32_t   __pad0__:12
 
   uint32_t   ckdf_algo:2
 Defines which algorithm and mode shall be used. More...
 
+   uint32_t   __pad1__:18
 
} bits
 
+

Detailed Description

+

Internal command option bit field for CKDF functions.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_CkdfOption_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_.

+ +
+
+ +

◆ ckdf_algo

+ +
+
+ + + + +
uint32_t mcuxClEls_CkdfOption_t::ckdf_algo
+
+ +

Defines which algorithm and mode shall be used.

+

This option is set internally and will be ignored: MCUXCLELS_CKDF_ALGO_SP800108 = Use SP800-108 algorithm

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01189.js b/components/els_pkc/doc/mcxn/html/a01189.js new file mode 100644 index 000000000..1506f0d7f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01189.js @@ -0,0 +1,9 @@ +var a01189 = +[ + [ "value", "a01189.html#a00abd43e6b7c9816562f2aa1d93c0b9e", null ], + [ "word", "a01189.html#a240aaf0efe5383f3f6c8cd250b31800d", null ], + [ "__pad0__", "a01189.html#a3d042b5093efe84ebc959168e0d4a5cc", null ], + [ "ckdf_algo", "a01189.html#afc52662f6e41b83e0c731d77c616506c", null ], + [ "__pad1__", "a01189.html#a00e88c3d9213e40f64c614df04a7735e", null ], + [ "bits", "a01189.html#a6e776ad52679cfa22fa4ca287c37d84c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01201.html b/components/els_pkc/doc/mcxn/html/a01201.html new file mode 100644 index 000000000..6ef03d893 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01201.html @@ -0,0 +1,204 @@ + + + + + + + +MCUX CLNS: mcuxClEls_HkdfOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_HkdfOption_t Union Reference
mcuxClEls » mcuxClEls_Kdf » mcuxClEls_Kdf_Macros » mcuxClEls_Kdf_Types
+
+
+ +

Command option bit field for mcuxClEls_Hkdf_Rfc5869_Async. + More...

+ +

#include <mcuxClEls_Kdf.h>

+ + + + + + + + + + + + + + + + + + + +

+Data Fields

+struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_. More...
 
} word
 
+struct {
   uint32_t   rtfdrvdat:1
 MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV=use derivation input from system memory, MCUXCLELS_HKDF_RTF_DERIV=use RTF (runtime fingerprint) as derivation input More...
 
   uint32_t   hkdf_algo:1
 Defines which algorithm shall be used. More...
 
+   uint32_t   __pad0__:30
 
} bits
 
+

Detailed Description

+

Command option bit field for mcuxClEls_Hkdf_Rfc5869_Async.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_HkdfOption_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_.

+ +
+
+ +

◆ rtfdrvdat

+ +
+
+ + + + +
uint32_t mcuxClEls_HkdfOption_t::rtfdrvdat
+
+ +

MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV=use derivation input from system memory, MCUXCLELS_HKDF_RTF_DERIV=use RTF (runtime fingerprint) as derivation input

+ +
+
+ +

◆ hkdf_algo

+ +
+
+ + + + +
uint32_t mcuxClEls_HkdfOption_t::hkdf_algo
+
+ +

Defines which algorithm shall be used.

+

This option is set internally and will be ignored: MCUXCLELS_HKDF_ALGO_RFC5869 = Use RFC5869 algorithm MCUXCLELS_HKDF_ALGO_SP80056C = Use SP800-56C algorithm

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01201.js b/components/els_pkc/doc/mcxn/html/a01201.js new file mode 100644 index 000000000..d1661259c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01201.js @@ -0,0 +1,9 @@ +var a01201 = +[ + [ "value", "a01201.html#aa39e185af4b2cfd758c0b7b7d3bea8db", null ], + [ "word", "a01201.html#a9f4a89742369066ab393e9389f8a01f4", null ], + [ "rtfdrvdat", "a01201.html#a7830e4ca489dcbca0e0b535e0979f5cc", null ], + [ "hkdf_algo", "a01201.html#ab385e81dfad37e2cdd8faaa1521ac405", null ], + [ "__pad0__", "a01201.html#aa8d2970a725074eb3ee5b9baed362eb3", null ], + [ "bits", "a01201.html#a09d3e6cb3ae38a2e55b7c9a3e8c80555", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01213.html b/components/els_pkc/doc/mcxn/html/a01213.html new file mode 100644 index 000000000..4c41bf21d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01213.html @@ -0,0 +1,188 @@ + + + + + + + +MCUX CLNS: mcuxClEls_TlsOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_TlsOption_t Union Reference
mcuxClEls » mcuxClEls_Kdf » mcuxClEls_Kdf_Macros » mcuxClEls_Kdf_Types
+
+
+ +

Internal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. + More...

+ +

#include <mcuxClEls_Kdf.h>

+ + + + + + + + + + + + + + + + + + +

+Data Fields

+struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_. More...
 
} word
 
+struct {
+   uint32_t   __pad0__:10
 
   uint32_t   mode:1
 Defines which phase of the key generation is performed. More...
 
+   uint32_t   __pad1__:21
 
} bits
 
+

Detailed Description

+

Internal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async.

+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_TlsOption_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_HKDF_VALUE_.

+ +
+
+ +

◆ mode

+ +
+
+ + + + +
uint32_t mcuxClEls_TlsOption_t::mode
+
+ +

Defines which phase of the key generation is performed.

+

This option is set internally and will be ignored: MCUXCLELS_TLS_INIT = Calculate master key from premaster key MCUXCLELS_TLS_FINALIZE = Calculate session keys from master key

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01213.js b/components/els_pkc/doc/mcxn/html/a01213.js new file mode 100644 index 000000000..6e1edaaee --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01213.js @@ -0,0 +1,9 @@ +var a01213 = +[ + [ "value", "a01213.html#acfe68053c7558c29e085ca434cf432cd", null ], + [ "word", "a01213.html#a90ee1034a9ee1809c079014fa19ed2ee", null ], + [ "__pad0__", "a01213.html#acff6fecdc2046f7299e575ff0b7177e4", null ], + [ "mode", "a01213.html#a3f8fbc06563e97492965d16d9f7a4ed1", null ], + [ "__pad1__", "a01213.html#a9d609161f300e9d3a67c2144079a17d3", null ], + [ "bits", "a01213.html#a06a84c2cb4e3b2e3f227995fa6c70dec", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01225.html b/components/els_pkc/doc/mcxn/html/a01225.html new file mode 100644 index 000000000..c2a025fae --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01225.html @@ -0,0 +1,300 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyImportOption_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_KeyImportOption_t Union Reference
mcuxClEls » mcuxClEls_KeyManagement » mcuxClEls_KeyManagement_Types
+
+
+ +

Command option bit field for mcuxClEls_KeyImport_Async. + More...

+ +

#include <mcuxClEls_KeyManagement.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYIMPORT_VALUE_KFMT_. More...
 
} word
 Access mcuxClEls_KeyImportOption_t word-wise. More...
 
struct {
   uint32_t   __pad0__:4
 RFU. More...
 
   uint32_t   revf:1
 This field is managed internally. More...
 
   uint32_t   __pad1__:1
 RFU. More...
 
   uint32_t   kfmt:2
 Defines the key import format, one of MCUXCLELS_KEYIMPORT_KFMT_. More...
 
   uint32_t   __pad2__:24
 RFU. More...
 
} bits
 Access mcuxClEls_KeyImportOption_t bit-wise. More...
 
+

Detailed Description

+

Command option bit field for mcuxClEls_KeyImport_Async.

+

Bit field to configure mcuxClEls_KeyImport_Async. See MCUXCLELS_KEYIMPORT_KFMT_ for possible options in case the struct is accessed bit-wise. See MCUXCLELS_KEYIMPORT_VALUE_KFMT_ for possible options in case the struct is accessed word-wise.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYIMPORT_VALUE_KFMT_.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_KeyImportOption_t::word
+
+ +

Access mcuxClEls_KeyImportOption_t word-wise.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ revf

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::revf
+
+ +

This field is managed internally.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ kfmt

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::kfmt
+
+ +

Defines the key import format, one of MCUXCLELS_KEYIMPORT_KFMT_.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ __pad2__

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyImportOption_t::__pad2__
+
+ +

RFU.

+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_KeyImportOption_t::bits
+
+ +

Access mcuxClEls_KeyImportOption_t bit-wise.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01225.js b/components/els_pkc/doc/mcxn/html/a01225.js new file mode 100644 index 000000000..0fae46115 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01225.js @@ -0,0 +1,11 @@ +var a01225 = +[ + [ "value", "a01225.html#ad5bfabd7e1e04a95627e0cbc144afdcb", null ], + [ "word", "a01225.html#a9a03426cf6b706ee292473b3d695ebe0", null ], + [ "__pad0__", "a01225.html#a2dfcb81e1476a07a6ab67f8c090b4ab5", null ], + [ "revf", "a01225.html#aa699b2cfb2fc82dcbc25d833e09d442e", null ], + [ "__pad1__", "a01225.html#ad67985d38d1563a926768316825e1944", null ], + [ "kfmt", "a01225.html#ae3892b035704c00a855dd43d96a21b2c", null ], + [ "__pad2__", "a01225.html#a05660839da43298f12f96572bf538330", null ], + [ "bits", "a01225.html#ad0fc563d3f708b06c986ec2ae604d69e", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01237.html b/components/els_pkc/doc/mcxn/html/a01237.html new file mode 100644 index 000000000..1c086082a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01237.html @@ -0,0 +1,733 @@ + + + + + + + +MCUX CLNS: mcuxClEls_KeyProp_t Union Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClEls_KeyProp_t Union Reference
mcuxClEls » mcuxClEls_Types » mcuxClEls_Types_Types
+
+
+ +

Type for ELS key store key properties. + More...

+ +

#include <mcuxClEls_Types.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

struct {
   uint32_t   value
 Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYPROPERTY_VALUE_. More...
 
} word
 Access mcuxClEls_KeyProp_t word-wise. More...
 
struct {
   uint32_t   ksize:1
 Key size. More...
 
   uint32_t   __pad0__:4
 RFU. More...
 
   uint32_t   kactv:1
 Status flag to indicate whether the key slot contains an active key or not. More...
 
   uint32_t   kbase:1
 Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key. More...
 
   uint32_t   fgp:1
 Hardware feature flag: General purpose key slot. More...
 
   uint32_t   frtn:1
 Hardware feature flag: Retention key slot. More...
 
   uint32_t   fhwo:1
 Hardware feature flag: Hardware-out key slot. More...
 
   uint32_t   __pad1__:3
 RFU. More...
 
   uint32_t   ucmac:1
 Usage permission for CMAC. More...
 
   uint32_t   uksk:1
 Usage permission for key signing. More...
 
   uint32_t   urtf:1
 Usage permission for RTF signing. More...
 
   uint32_t   uckdf:1
 Usage permission for CKDF. More...
 
   uint32_t   uhkdf:1
 Usage permission for HKDF. More...
 
   uint32_t   uecsg:1
 Usage permission for ECDSA signing. More...
 
   uint32_t   uecdh:1
 Usage permission for Elliptic Curve Diffie-Hellman. More...
 
   uint32_t   uaes:1
 Usage permission for AES. More...
 
   uint32_t   uhmac:1
 Usage permission for HMAC. More...
 
   uint32_t   ukwk:1
 Usage permission for key wrapping. More...
 
   uint32_t   ukuok:1
 Usage permission for key unwrapping, but not for key wrapping. More...
 
   uint32_t   utlspms:1
 Usage permission as a TLS premaster secret. More...
 
   uint32_t   utlsms:1
 Usage permission as a TLS master secret. More...
 
   uint32_t   ukgsrc:1
 Usage permission as input for ECC key generation. More...
 
   uint32_t   uhwo:1
 Usage permission in a hardware-out key slot. More...
 
   uint32_t   wrpok:1
 Usage permission to wrap. More...
 
   uint32_t   duk:1
 Device-unique key flag. More...
 
   uint32_t   upprot_priv:1
 Access restriction to privileged mode. More...
 
   uint32_t   upprot_sec:1
 Access restriction to TrustZone secure mode. More...
 
} bits
 Access mcuxClEls_KeyProp_t bit-wise. More...
 
+

Detailed Description

+

Type for ELS key store key properties.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, and mcuxClKey_example.c.
+
+

Field Documentation

+ +

◆ value

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::value
+
+ +

Accesses the bit field as a full word; initialize with a combination of constants from MCUXCLELS_KEYPROPERTY_VALUE_.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ word

+ +
+
+ + + + +
struct { ... } mcuxClEls_KeyProp_t::word
+
+ +

Access mcuxClEls_KeyProp_t word-wise.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ ksize

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::ksize
+
+ +

Key size.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ __pad0__

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::__pad0__
+
+ +

RFU.

+ +
+
+ +

◆ kactv

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::kactv
+
+ +

Status flag to indicate whether the key slot contains an active key or not.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClKey_example.c.
+
+ +
+
+ +

◆ kbase

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::kbase
+
+ +

Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ fgp

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::fgp
+
+ +

Hardware feature flag: General purpose key slot.

+ +
+
+ +

◆ frtn

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::frtn
+
+ +

Hardware feature flag: Retention key slot.

+ +
+
+ +

◆ fhwo

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::fhwo
+
+ +

Hardware feature flag: Hardware-out key slot.

+ +
+
+ +

◆ __pad1__

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::__pad1__
+
+ +

RFU.

+ +
+
+ +

◆ ucmac

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::ucmac
+
+ +

Usage permission for CMAC.

+ +
+
+ +

◆ uksk

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uksk
+
+ +

Usage permission for key signing.

+ +
+
+ +

◆ urtf

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::urtf
+
+ +

Usage permission for RTF signing.

+ +
+
+ +

◆ uckdf

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uckdf
+
+ +

Usage permission for CKDF.

+ +
+
+ +

◆ uhkdf

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uhkdf
+
+ +

Usage permission for HKDF.

+ +
+
+ +

◆ uecsg

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uecsg
+
+ +

Usage permission for ECDSA signing.

+ +
+
+ +

◆ uecdh

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uecdh
+
+ +

Usage permission for Elliptic Curve Diffie-Hellman.

+ +
+
+ +

◆ uaes

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uaes
+
+ +

Usage permission for AES.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ uhmac

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uhmac
+
+ +

Usage permission for HMAC.

+ +
+
+ +

◆ ukwk

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::ukwk
+
+ +

Usage permission for key wrapping.

+ +
+
+ +

◆ ukuok

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::ukuok
+
+ +

Usage permission for key unwrapping, but not for key wrapping.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ utlspms

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::utlspms
+
+ +

Usage permission as a TLS premaster secret.

+ +
+
+ +

◆ utlsms

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::utlsms
+
+ +

Usage permission as a TLS master secret.

+
Examples
mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ ukgsrc

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::ukgsrc
+
+ +

Usage permission as input for ECC key generation.

+ +
+
+ +

◆ uhwo

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::uhwo
+
+ +

Usage permission in a hardware-out key slot.

+ +
+
+ +

◆ wrpok

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::wrpok
+
+ +

Usage permission to wrap.

+
Examples
mcuxClEls_Key_Import_Puk_DER_example.c.
+
+ +
+
+ +

◆ duk

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::duk
+
+ +

Device-unique key flag.

+ +
+
+ +

◆ upprot_priv

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::upprot_priv
+
+ +

Access restriction to privileged mode.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ upprot_sec

+ +
+
+ + + + +
uint32_t mcuxClEls_KeyProp_t::upprot_sec
+
+ +

Access restriction to TrustZone secure mode.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, and mcuxClEls_Tls_Master_Key_Session_Keys_example.c.
+
+ +
+
+ +

◆ bits

+ +
+
+ + + + +
struct { ... } mcuxClEls_KeyProp_t::bits
+
+ +

Access mcuxClEls_KeyProp_t bit-wise.

+
Examples
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c, mcuxClEls_Key_Import_Puk_DER_example.c, mcuxClEls_Tls_Master_Key_Session_Keys_example.c, and mcuxClKey_example.c.
+
+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01237.js b/components/els_pkc/doc/mcxn/html/a01237.js new file mode 100644 index 000000000..dfb6775b1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01237.js @@ -0,0 +1,33 @@ +var a01237 = +[ + [ "value", "a01237.html#af184a952f255348629f27f24c0fd0bd9", null ], + [ "word", "a01237.html#a270029567d10cf5d46c68f3fd5762394", null ], + [ "ksize", "a01237.html#a49806c0136f41b701675799cb69d34d5", null ], + [ "__pad0__", "a01237.html#aef07ed5cdd67e69b2862d98fa9ce2bf2", null ], + [ "kactv", "a01237.html#ad0617bc9eea63043b1faf5fe9814ba97", null ], + [ "kbase", "a01237.html#ac8a7a5dac0515241438c5086d60ffcd2", null ], + [ "fgp", "a01237.html#af8743c57bd6d9dd9f329b5cafa3f5c0c", null ], + [ "frtn", "a01237.html#a6e2122f7d4c2706f56ec7fba67042206", null ], + [ "fhwo", "a01237.html#a0c56a02caf693cda953b333b89a51389", null ], + [ "__pad1__", "a01237.html#aba08650854846dd1ef4788c1a8ef0c58", null ], + [ "ucmac", "a01237.html#acceecb25ef42cd4017edfc9095272b3d", null ], + [ "uksk", "a01237.html#a1c20ef8f869a090cc90472821adba513", null ], + [ "urtf", "a01237.html#a32ac519b2729fc88babaaf23ecfb6523", null ], + [ "uckdf", "a01237.html#a3bdb1b36f76fe81225b14896d3429147", null ], + [ "uhkdf", "a01237.html#a983d6a05d50a4e6eeb929ecfab1c5ca0", null ], + [ "uecsg", "a01237.html#adb18f3c09ac78e8d74f2ff9563da084b", null ], + [ "uecdh", "a01237.html#af513bad0dfe63b94b601adae2590ef17", null ], + [ "uaes", "a01237.html#a18d3c3d356100d7bd01a9950c1f7b81e", null ], + [ "uhmac", "a01237.html#ae8e6215c6390b64024f5bb71d09013a6", null ], + [ "ukwk", "a01237.html#a006a40e53f4859e41e4b4ec5424c6c26", null ], + [ "ukuok", "a01237.html#ab0fe394151ed388fa03198d5710bc0d1", null ], + [ "utlspms", "a01237.html#a30f2161747c56e0de99561d38885be7e", null ], + [ "utlsms", "a01237.html#a5f7b5dc8e882536c83ff87ac246ca6ed", null ], + [ "ukgsrc", "a01237.html#ac4fbcd8af04b845353857e27ae6e90b8", null ], + [ "uhwo", "a01237.html#a08b731503e03ee90d1904cbb88e9c37c", null ], + [ "wrpok", "a01237.html#a8b01f95eb9069953fe7a48b6ec85e479", null ], + [ "duk", "a01237.html#ab8a152b213978003ebb149be0c0ae5a7", null ], + [ "upprot_priv", "a01237.html#a50d3bbaabf919fab908e2ae83fe5a5ab", null ], + [ "upprot_sec", "a01237.html#a0d130be83d337e7a5d9ef56f4a92f3a0", null ], + [ "bits", "a01237.html#abcae2eaaf0826e5548f0b416ecfff0b4", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01249.html b/components/els_pkc/doc/mcxn/html/a01249.html new file mode 100644 index 000000000..4e698eb83 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01249.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_ScratchPad_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClOscca_ScratchPad_t Struct Reference
+
+
+ +

global scratch pad structure definition + More...

+ +

#include <mcuxClOscca_PlatformTypes.h>

+ + + + + + + + +

+Data Fields

+volatile uint16_t securityCounter
 
+volatile uint16_t stackPointerBackup
 
+uint32_t generalPurposeValue
 
+

Detailed Description

+

global scratch pad structure definition

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01249.js b/components/els_pkc/doc/mcxn/html/a01249.js new file mode 100644 index 000000000..1759f6b18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01249.js @@ -0,0 +1,6 @@ +var a01249 = +[ + [ "securityCounter", "a01249.html#aaabefccce5bee0778f3327731677c4d0", null ], + [ "stackPointerBackup", "a01249.html#a6a824ec7cfc6f2f79ff114d525710ba2", null ], + [ "generalPurposeValue", "a01249.html#a3a701c9768a5d687ad058487e80ebb47", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01253.html b/components/els_pkc/doc/mcxn/html/a01253.html new file mode 100644 index 000000000..f11fb081f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01253.html @@ -0,0 +1,173 @@ + + + + + + + +MCUX CLNS: mcuxClOscca_MPInt_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClOscca_MPInt_t Struct Reference
+
+
+ +

Structure for multi-precision integer used in asymetric cryptography. + More...

+ +

#include <mcuxClOscca_Types.h>

+ + + + + + + + +

+Data Fields

uint8_t const * pMPInt
 Pointer to the multi precision integer. More...
 
uint16_t wNumBytes
 Length in bytes of multi precision integer. More...
 
+

Detailed Description

+

Structure for multi-precision integer used in asymetric cryptography.

+

Field Documentation

+ +

◆ pMPInt

+ +
+
+ + + + +
uint8_t const* mcuxClOscca_MPInt_t::pMPInt
+
+ +

Pointer to the multi precision integer.

+ +
+
+ +

◆ wNumBytes

+ +
+
+ + + + +
uint16_t mcuxClOscca_MPInt_t::wNumBytes
+
+ +

Length in bytes of multi precision integer.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01253.js b/components/els_pkc/doc/mcxn/html/a01253.js new file mode 100644 index 000000000..3d4edb49e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01253.js @@ -0,0 +1,5 @@ +var a01253 = +[ + [ "pMPInt", "a01253.html#a00c20f8c0e84c867dcdfb13cf1549ce6", null ], + [ "wNumBytes", "a01253.html#aa8adc5c5c0851f5adc6abd44edf06d1c", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01257.html b/components/els_pkc/doc/mcxn/html/a01257.html new file mode 100644 index 000000000..ffcff7c82 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01257.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: mcuxClOsccaPkc_State_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClOsccaPkc_State_t Struct Reference
mcuxClOsccaPkc » mcuxClOsccaPkc_Functions
+
+
+ +

Structure of PKC state backup. + More...

+ +

#include <mcuxClOsccaPkc_Functions.h>

+ + + + + + +

+Data Fields

+uint32_t cfg
 
+uint32_t ctrl
 
+

Detailed Description

+

Structure of PKC state backup.

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01257.js b/components/els_pkc/doc/mcxn/html/a01257.js new file mode 100644 index 000000000..fa36a9883 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01257.js @@ -0,0 +1,5 @@ +var a01257 = +[ + [ "cfg", "a01257.html#ad7810f1fb9ad33435dd7d916974106c7", null ], + [ "ctrl", "a01257.html#a51cc91fc838fe096cdd99b0fa45184b7", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01261.html b/components/els_pkc/doc/mcxn/html/a01261.html new file mode 100644 index 000000000..5fbce24a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01261.html @@ -0,0 +1,173 @@ + + + + + + + +MCUX CLNS: mcuxClPkc_State_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClPkc_State_t Struct Reference
mcuxClPkc » mcuxClPkc_Functions » McuxClPkc_Functions_Init
+
+
+ +

Structure of PKC state backup. + More...

+ +

#include <mcuxClPkc_Functions.h>

+ + + + + + + + +

+Data Fields

uint16_t ctrl
 backup of PKC CTRL bits More...
 
uint16_t cfg
 backup of PKC CFG bits More...
 
+

Detailed Description

+

Structure of PKC state backup.

+

Field Documentation

+ +

◆ ctrl

+ +
+
+ + + + +
uint16_t mcuxClPkc_State_t::ctrl
+
+ +

backup of PKC CTRL bits

+ +
+
+ +

◆ cfg

+ +
+
+ + + + +
uint16_t mcuxClPkc_State_t::cfg
+
+ +

backup of PKC CFG bits

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01261.js b/components/els_pkc/doc/mcxn/html/a01261.js new file mode 100644 index 000000000..cc9df3c4a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01261.js @@ -0,0 +1,5 @@ +var a01261 = +[ + [ "ctrl", "a01261.html#a3b225011dfe5fd36551cb70210f9b41c", null ], + [ "cfg", "a01261.html#a5d5778eef90af40b0ba73b22fdeedb57", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01265.html b/components/els_pkc/doc/mcxn/html/a01265.html new file mode 100644 index 000000000..7b7c5e891 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01265.html @@ -0,0 +1,174 @@ + + + + + + + +MCUX CLNS: mcuxClRandom_Config Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClRandom_Config Struct Reference
mcuxClRandom » mcuxClRandom_Types
+
+
+ +

Random config structure. + More...

+ +

#include <mcuxClRandom_Types.h>

+ + + + + + + + +

+Data Fields

mcuxClRandom_Mode_t mode
 Random data generation mode/algorithm. More...
 
mcuxClRandom_Context_t ctx
 Context for the Rng. More...
 
+

Detailed Description

+

Random config structure.

+

This structure is used to store context and mode pointers.

+

Field Documentation

+ +

◆ mode

+ +
+
+ + + + +
mcuxClRandom_Mode_t mcuxClRandom_Config::mode
+
+ +

Random data generation mode/algorithm.

+ +
+
+ +

◆ ctx

+ +
+
+ + + + +
mcuxClRandom_Context_t mcuxClRandom_Config::ctx
+
+ +

Context for the Rng.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01265.js b/components/els_pkc/doc/mcxn/html/a01265.js new file mode 100644 index 000000000..21de6ad2b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01265.js @@ -0,0 +1,5 @@ +var a01265 = +[ + [ "mode", "a01265.html#ad723b63c438689b0d5c978fceb289506", null ], + [ "ctx", "a01265.html#a2869dc5912686dc81c5076587bb83327", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01269.html b/components/els_pkc/doc/mcxn/html/a01269.html new file mode 100644 index 000000000..c6086f7d4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01269.html @@ -0,0 +1,177 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_KeyEntry_t Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClRsa_KeyEntry_t Struct Reference
mcuxClRsa » mcuxClRsa_Types
+
+
+ +

Structure type for Rsa key entries, specifying key entry length and data. + More...

+ +

#include <mcuxClRsa_Types.h>

+ + + + + + + + +

+Data Fields

uint8_t * pKeyEntryData
 Pointer to buffer containing the key entry data in big-endian byte order. More...
 
uint32_t keyEntryLength
 Byte-length of the buffer pointed to by pKeyEntryData. More...
 
+

Detailed Description

+

Structure type for Rsa key entries, specifying key entry length and data.

+
Examples
mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+

Field Documentation

+ +

◆ pKeyEntryData

+ +
+
+ + + + +
uint8_t* mcuxClRsa_KeyEntry_t::pKeyEntryData
+
+ +

Pointer to buffer containing the key entry data in big-endian byte order.

+
Examples
mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ keyEntryLength

+ +
+
+ + + + +
uint32_t mcuxClRsa_KeyEntry_t::keyEntryLength
+
+ +

Byte-length of the buffer pointed to by pKeyEntryData.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01269.js b/components/els_pkc/doc/mcxn/html/a01269.js new file mode 100644 index 000000000..23737a3e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01269.js @@ -0,0 +1,5 @@ +var a01269 = +[ + [ "pKeyEntryData", "a01269.html#a1f5a90f95105b9abaf31a7997a2fb24e", null ], + [ "keyEntryLength", "a01269.html#a441763378fea50af88f8cdf75648a0e6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01273.html b/components/els_pkc/doc/mcxn/html/a01273.html new file mode 100644 index 000000000..22e0baed3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01273.html @@ -0,0 +1,279 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_Key Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClRsa_Key Struct Reference
mcuxClRsa » mcuxClRsa_Types
+
+
+ +

Structure type for Rsa key, specifying key type and key entries. + More...

+ +

#include <mcuxClRsa_Types.h>

+ + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

uint32_t keytype
 Key type specifier: More...
 
mcuxClRsa_KeyEntry_t * pMod1
 Pointer to first key entry: More...
 
mcuxClRsa_KeyEntry_t * pMod2
 Pointer to second key entry: More...
 
mcuxClRsa_KeyEntry_t * pQInv
 Pointer to third key entry: More...
 
mcuxClRsa_KeyEntry_t * pExp1
 Pointer to fourth key entry: More...
 
mcuxClRsa_KeyEntry_t * pExp2
 Pointer to fifth key entry: More...
 
mcuxClRsa_KeyEntry_t * pExp3
 Pointer to sixth key entry: More...
 
+

Detailed Description

+

Structure type for Rsa key, specifying key type and key entries.

+
Examples
mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+

Field Documentation

+ +

◆ keytype

+ +
+
+ + + + +
uint32_t mcuxClRsa_Key::keytype
+
+ +

Key type specifier:

+

In case of an RSA public key this shall be set to MCUXCLRSA_KEY_PUBLIC. In case of an RSA private plain key this shall be set to MCUXCLRSA_KEY_PRIVATEPLAIN. In case of an RSA private CRT key this shall be set to MCUXCLRSA_KEY_PRIVATECRT. In case of an RSA private CRT key, with which a fault-protected CRT operation is executed, this shall be set to MCUXCLRSA_KEY_PRIVATECRT_DFA

+
Examples
mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+ +
+
+ +

◆ pMod1

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pMod1
+
+ +

Pointer to first key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC and MCUXCLRSA_KEY_PRIVATEPLAIN the first key entry points to the public parameter modulus N. In case of MCUXCLRSA_KEY_PRIVATECRT and MCUXCLRSA_KEY_PRIVATECRT_DFA the first key entry points to the private parameter prime factor P.

+ +
+
+ +

◆ pMod2

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pMod2
+
+ +

Pointer to second key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC and MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. In case of MCUXCLRSA_KEY_PRIVATECRT and MCUXCLRSA_KEY_PRIVATECRT_DFA the second key entry points to the private parameter prime factor Q.

+ +
+
+ +

◆ pQInv

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pQInv
+
+ +

Pointer to third key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC and MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. In case of MCUXCLRSA_KEY_PRIVATECRT and MCUXCLRSA_KEY_PRIVATECRT_DFA the third key entry points to the private parameter QInv = (1 / (Q % P)).

+ +
+
+ +

◆ pExp1

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pExp1
+
+ +

Pointer to fourth key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC the first exponent entry points to the public parameter exponent E. In case of MCUXCLRSA_KEY_PRIVATEPLAIN the first exponent entry points to the private parameter exponent D. In case of MCUXCLRSA_KEY_PRIVATECRT and MCUXCLRSA_KEY_PRIVATECRT_DFA the first exponent entry points to the private parameter DP = D % (P-1).

+ +
+
+ +

◆ pExp2

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pExp2
+
+ +

Pointer to fifth key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC and MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. In case of MCUXCLRSA_KEY_PRIVATECRT and MCUXCLRSA_KEY_PRIVATECRT_DFA the second exponent entry points to the private parameter DQ = D % (Q-1).

+ +
+
+ +

◆ pExp3

+ +
+
+ + + + +
mcuxClRsa_KeyEntry_t* mcuxClRsa_Key::pExp3
+
+ +

Pointer to sixth key entry:

+

In case of MCUXCLRSA_KEY_PUBLIC, MCUXCLRSA_KEY_PRIVATEPLAIN, and MCUXCLRSA_KEY_PRIVATECRT this pointer shall be set to NULL. In case of MCUXCLRSA_KEY_PRIVATECRT_DFA the third exponent entry points to the public parameter exponent E.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01273.js b/components/els_pkc/doc/mcxn/html/a01273.js new file mode 100644 index 000000000..39705246b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01273.js @@ -0,0 +1,10 @@ +var a01273 = +[ + [ "keytype", "a01273.html#a8d0791ef8960a4316931f55f5848c3fa", null ], + [ "pMod1", "a01273.html#ab53f60022abcb2c60300022907c460ce", null ], + [ "pMod2", "a01273.html#ab1b71c75486149a0b722dfe36d3ca6cd", null ], + [ "pQInv", "a01273.html#aa9188b106fa0b275218f8dc04fd9fa79", null ], + [ "pExp1", "a01273.html#a28deb463bb016edacb1938dc272deb8a", null ], + [ "pExp2", "a01273.html#accac28790b11f7574dd84f6da9877a2c", null ], + [ "pExp3", "a01273.html#a0846b30142dc6cb42d05b5c30afd71cc", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01277.html b/components/els_pkc/doc/mcxn/html/a01277.html new file mode 100644 index 000000000..5db73deba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01277.html @@ -0,0 +1,211 @@ + + + + + + + +MCUX CLNS: mcuxClSession_WorkArea Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClSession_WorkArea Struct Reference
mcuxClSession » mcuxClSession_Types
+
+
+ +

Type for mcuxClSession workareas flags. + More...

+ +

#include <mcuxClSession_Types.h>

+ + + + + + + + + + + + + + +

+Data Fields

uint32_t * buffer
 Pointer to the starting address of the workarea buffer. More...
 
uint32_t size
 Size of the workarea buffer in words (uint32_t) More...
 
uint32_t used
 Used portion of the workarea buffer in words (uint32_t) More...
 
uint32_t dirty
 Maximum used portion of the workarea buffer in words (uint32_t) More...
 
+

Detailed Description

+

Type for mcuxClSession workareas flags.

+

Field Documentation

+ +

◆ buffer

+ +
+
+ + + + +
uint32_t* mcuxClSession_WorkArea::buffer
+
+ +

Pointer to the starting address of the workarea buffer.

+ +
+
+ +

◆ size

+ +
+
+ + + + +
uint32_t mcuxClSession_WorkArea::size
+
+ +

Size of the workarea buffer in words (uint32_t)

+ +
+
+ +

◆ used

+ +
+
+ + + + +
uint32_t mcuxClSession_WorkArea::used
+
+ +

Used portion of the workarea buffer in words (uint32_t)

+ +
+
+ +

◆ dirty

+ +
+
+ + + + +
uint32_t mcuxClSession_WorkArea::dirty
+
+ +

Maximum used portion of the workarea buffer in words (uint32_t)

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01277.js b/components/els_pkc/doc/mcxn/html/a01277.js new file mode 100644 index 000000000..6b9f115d7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01277.js @@ -0,0 +1,7 @@ +var a01277 = +[ + [ "buffer", "a01277.html#acd3913d2b4adf01d7d95c687c578c752", null ], + [ "size", "a01277.html#a372ca932239a945030d51a23913c36e0", null ], + [ "used", "a01277.html#ab3280a7d27aa7837287e2fa4376492fb", null ], + [ "dirty", "a01277.html#a500aa3a1084704dbd9622a247458b9b1", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01281.html b/components/els_pkc/doc/mcxn/html/a01281.html new file mode 100644 index 000000000..76ef9d232 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01281.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: mcuxClSession_SecurityContext Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClSession_SecurityContext Struct Reference
mcuxClSession » mcuxClSession_Types
+
+
+ +

Type for mcuxClSession security context. + More...

+ +

#include <mcuxClSession_Types.h>

+ + + + + +

+Data Fields

uint32_t securityCounter
 Security counter. More...
 
+

Detailed Description

+

Type for mcuxClSession security context.

+

Field Documentation

+ +

◆ securityCounter

+ +
+
+ + + + +
uint32_t mcuxClSession_SecurityContext::securityCounter
+
+ +

Security counter.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01281.js b/components/els_pkc/doc/mcxn/html/a01281.js new file mode 100644 index 000000000..7c7ad1ca0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01281.js @@ -0,0 +1,4 @@ +var a01281 = +[ + [ "securityCounter", "a01281.html#a3bca2e1ffbfa74a0afd525444dee8f16", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01285.html b/components/els_pkc/doc/mcxn/html/a01285.html new file mode 100644 index 000000000..af4c04029 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01285.html @@ -0,0 +1,197 @@ + + + + + + + +MCUX CLNS: mcuxClSession_Descriptor Struct Reference + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Data Fields
+
+
mcuxClSession_Descriptor Struct Reference
mcuxClSession » mcuxClSession_Types
+
+
+ +

Type for mcuxClSession Descriptor. + More...

+ +

#include <mcuxClSession_Types.h>

+ + + + + + + + + + + + + +

+Data Fields

mcuxClSession_WorkArea_t cpuWa
 Workarea for the CPU. More...
 
mcuxClSession_WorkArea_t pkcWa
 Workarea for the PKC. More...
 
mcuxClSession_Rtf_t rtf
 Configuration of the RTF. More...
 
+uint8_t * pRtf
 
+

Detailed Description

+

Type for mcuxClSession Descriptor.

+
Examples
mcuxClEcc_EdDSA_Ed25519_example.c, mcuxClEcc_EdDSA_Ed25519ctx_example.c, mcuxClEcc_EdDSA_Ed25519ph_example.c, mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c, mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c, mcuxClEcc_Mont_Curve25519_example.c, mcuxClEcc_Mont_Curve448_example.c, mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c, mcuxClKey_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c, mcuxClRandomModes_Different_Sessions_example.c, mcuxClRandomModes_ELS_example.c, mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c, mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c, mcuxClRsa_sign_NoEncode_example.c, mcuxClRsa_sign_pss_sha2_256_example.c, mcuxClRsa_verify_NoVerify_example.c, and mcuxClRsa_verify_pssverify_sha2_256_example.c.
+
+

Field Documentation

+ +

◆ cpuWa

+ +
+
+ + + + +
mcuxClSession_WorkArea_t mcuxClSession_Descriptor::cpuWa
+
+ +

Workarea for the CPU.

+ +
+
+ +

◆ pkcWa

+ +
+
+ + + + +
mcuxClSession_WorkArea_t mcuxClSession_Descriptor::pkcWa
+
+ +

Workarea for the PKC.

+ +
+
+ +

◆ rtf

+ +
+
+ + + + +
mcuxClSession_Rtf_t mcuxClSession_Descriptor::rtf
+
+ +

Configuration of the RTF.

+ +
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01285.js b/components/els_pkc/doc/mcxn/html/a01285.js new file mode 100644 index 000000000..20bb412af --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01285.js @@ -0,0 +1,7 @@ +var a01285 = +[ + [ "cpuWa", "a01285.html#a8e3448a94cee26e27929d48656dcacb8", null ], + [ "pkcWa", "a01285.html#a394996570a6810808bd59d2f9672c76a", null ], + [ "rtf", "a01285.html#ab1b8f498d45832cba336165e6761ce0d", null ], + [ "pRtf", "a01285.html#a2c4ebdaa00f8277aa174313ced71a4b6", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/a01286.html b/components/els_pkc/doc/mcxn/html/a01286.html new file mode 100644 index 000000000..2d163f24d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01286.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c
+
+
+

Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x6BU, 0xC1U, 0xBEU, 0xE2U,
0x2EU, 0x40U, 0x9FU, 0x96U,
0xE9U, 0x3DU, 0x7EU, 0x11U,
0x73U, 0x93U, 0x17U, 0x2AU};
static uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x3AU, 0xD7U, 0x7BU, 0xB4U,
0x0DU, 0x7AU, 0x36U, 0x60U,
0xA8U, 0x9EU, 0xCAU, 0xF3U,
0x24U, 0x66U, 0xEFU, 0x97U};
static uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128 / sizeof(uint32_t)] = {0x16157E2B, 0xA6D2AE28, 0x8815F7AB, 0x3C4FCF09};
static uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES];
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_CipherOption_t cipher_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Cipher_Async operation.
cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB; // Configure the AES block cipher mode of operation to be the ECB (Electronic Codebook) mode.
cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; // Configure that the mcuxClEls_Cipher_Async operation shall perform encryption.
cipher_options.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; // Configure that an external key should be used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( // Perform the encryption.
cipher_options, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (keyIdx) is ignored, since an external key is used.
(const uint8_t *) aes128_key, MCUXCLELS_CIPHER_KEY_SIZE_AES_128, // The AES key for the encryption (external key).
aes128_input, sizeof(aes128_input), // The plaintext to encrypt. Note that this plaintext's length is a multiple of the block length, so no padding is required.
NULL, // This parameter (pIV) is ignored, since the ECB mode is used.
aes128_output // Output buffer, which the operation will write the ciphertext to.
));
// mcuxClEls_Cipher_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Cipher_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Cipher_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0U; i < sizeof(aes128_output); i++)
{
if (aes128_output[i] != aes128_expected_output[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting ciphertext matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01287.html b/components/els_pkc/doc/mcxn/html/a01287.html new file mode 100644 index 000000000..f278f8361 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01287.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c
+
+
+

Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x6BU, 0xC1U, 0xBEU, 0xE2U,
0x2EU, 0x40U, 0x9FU, 0x96U,
0xE9U, 0x3DU, 0x7EU, 0x11U,
0x73U, 0x93U, 0x17U, 0x2AU};
static uint8_t aes128_iv[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0xF8U, 0xD2U, 0x68U, 0x76U,
0x81U, 0x6FU, 0x0FU, 0xBAU,
0x86U, 0x2BU, 0xD8U, 0xA3U,
0x2DU, 0x04U, 0x67U, 0xC3U};
static uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0xCAU, 0xEAU, 0x07U, 0x26U,
0x62U, 0xE2U, 0x20U, 0x06U,
0x2DU, 0x45U, 0x46U, 0x41U,
0x5EU, 0xFFU, 0xFAU, 0xD2U};
static uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128 / sizeof(uint32_t)] = {0x16157E2B, 0xA6D2AE28, 0x8815F7AB, 0x3C4FCF09};
static uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES];
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_CipherOption_t cipher_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Cipher_Async operation.
cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC; // Configure the AES block cipher mode of operation to be the CBC (Cipher Block Chaining) mode.
cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; // Configure that the mcuxClEls_Cipher_Async operation shall perform encryption.
cipher_options.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; // Configure that an external key should be used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( // Perform the encryption.
cipher_options, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (keyIdx) is ignored, since an external key is used.
(const uint8_t *) aes128_key, MCUXCLELS_CIPHER_KEY_SIZE_AES_128, // The AES key for the encryption (external key).
aes128_input, sizeof(aes128_input), // The plaintext to encrypt. Note that this plaintext's length is a multiple of the block length, so no padding is required.
aes128_iv, // The IV (Initialization Vector) used for the encryption.
aes128_output // Output buffer, which the operation will write the ciphertext to.
));
// mcuxClEls_Cipher_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;// Expect that no error occurred, meaning that the mcuxClEls_Cipher_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Cipher_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0U; i < sizeof(aes128_output); i++)
{
if (aes128_output[i] != aes128_expected_output[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;// Expect that the resulting ciphertext matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01288.html b/components/els_pkc/doc/mcxn/html/a01288.html new file mode 100644 index 000000000..9aa09da11 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01288.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Ecc_Keygen_Sign_Verify_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Ecc_Keygen_Sign_Verify_example.c
+
+
+

Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_ELS_Key_Helper.h>
static uint32_t const ecc_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 / sizeof(uint32_t)] = {0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888};
static uint32_t ecc_public_key[MCUXCLELS_ECC_PUBLICKEY_SIZE / sizeof(uint32_t)];
static uint32_t ecc_signature[MCUXCLELS_ECC_SIGNATURE_SIZE / sizeof(uint32_t)];
static uint32_t ecc_signature_r[MCUXCLELS_ECC_SIGNATURE_R_SIZE / sizeof(uint32_t)];
static uint32_t ecc_signature_and_public_key[(MCUXCLELS_ECC_SIGNATURE_SIZE + MCUXCLELS_ECC_PUBLICKEY_SIZE) / sizeof(uint32_t)];
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Ecc_Keygen_Sign_Verify_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Generate signing key */
mcuxClEls_EccKeyGenOption_t KeyGenOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccKeyGen_Async operation.
KeyGenOptions.bits.kgsrc = MCUXCLELS_ECC_OUTPUTKEY_RANDOM; // Configure that a non-deterministic key is generated.
KeyGenOptions.bits.kgsign = MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE; // Configure that the generated public key is not signed
KeyGenOptions.bits.kgsign_rnd = MCUXCLELS_ECC_NO_RANDOM_DATA; // Configure that no external random data is provided
mcuxClEls_KeyProp_t GenKeyProp = {0}; // Initialize a new configuration for the mcuxClEls_EccKeyGen_Async generated key properties.
GenKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access
GenKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: non-secure access
mcuxClEls_KeyIndex_t keyIdx = 10u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation.
KeyGenOptions, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration.
keyIdx, // Keystore index at which the generated private key is stored.
GenKeyProp, // Set the generated key properties.
NULL, // No random data is provided
(uint8_t *) ecc_public_key // Output buffer, which the operation will write the public key to.
));
// mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Sign message digest */
mcuxClEls_EccSignOption_t SignOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccSign_Async operation.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccSign_Async(// Perform signature generation.
SignOptions, // Set the prepared configuration.
keyIdx, // Set index of private key in keystore.
(const uint8_t *) ecc_digest, NULL, (size_t) 0U, // Pre-hashed data to sign. Note that inputLength parameter is ignored since pre-hashed data has a fixed length.
(uint8_t *)ecc_signature // Output buffer, which the operation will write the signature to.
));
// mcuxClEls_EccSign_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccSign_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccSign_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccSign_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Verify signature */
/* Concatenate signature and public key to prepare input for EccVerify_Async */
for(size_t i = 0u; i < MCUXCLELS_ECC_SIGNATURE_SIZE; i++) {
((uint8_t *)ecc_signature_and_public_key)[i] = ((uint8_t *)ecc_signature)[i];
}
for(size_t i = 0u; i < MCUXCLELS_ECC_PUBLICKEY_SIZE; i++) {
((uint8_t *)ecc_signature_and_public_key)[MCUXCLELS_ECC_SIGNATURE_SIZE + i] = *((uint8_t *) ecc_public_key + i);
}
mcuxClEls_EccVerifyOption_t VerifyOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccVerify_Async operation.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccVerify_Async(// Perform signature verification.
VerifyOptions, // Set the prepared configuration.
(const uint8_t *) ecc_digest, NULL, (size_t) 0U, // Pre-hashed data to verify. Note that inputLength parameter is ignored since pre-hashed data has a fixed length.
(const uint8_t *)ecc_signature_and_public_key, // Concatenation of signature of the pre-hashed data and public key used
(uint8_t *)ecc_signature_r // Output buffer, which the operation will write the signature part r to, to allow external comparison of between given and recalculated r.
));
// mcuxClEls_EccVerify_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccVerify_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccVerify_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccVerify_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
mcuxClEls_HwState_t state;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwState(&state));
// mcuxClEls_GetHwState is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if (MCUXCLELS_STATUS_ECDSAVFY_OK != state.bits.ecdsavfy)
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that mcuxClEls_EccVerify_Async operation successfully performed the signature verification.
}
if(!mcuxClExample_Els_KeyDelete(keyIdx))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01289.html b/components/els_pkc/doc/mcxn/html/a01289.html new file mode 100644 index 000000000..ef776f579 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01289.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Common_Get_Info_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Common_Get_Info_example.c
+
+
+

Example of version and configuration load functions.

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxCl_clns.h> // Test the CLNS component-independent functionality
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Common_Get_Info_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
// Read the ELS hardware version.
mcuxClEls_HwVersion_t hw_version;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwVersion(&hw_version));
// mcuxClEls_GetHwVersion is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwVersion) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
// Access and store hw_version struct elements
uint32_t revision = hw_version.bits.revision; // Extended revision version
uint32_t minor = hw_version.bits.minor; // Minor version
uint32_t major = hw_version.bits.major; // Major version
(void) revision;
(void) minor;
(void) major;
#if MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0
uint32_t level = hw_version.bits.level; // Release level version
#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0 */
uint32_t fw_revision = hw_version.bits.fw_revision; // Firmware Extended revision version
uint32_t fw_minor = hw_version.bits.fw_minor; // Firmware Minor version
uint32_t fw_major = hw_version.bits.fw_major; // Firmware Major version
(void) fw_revision;
(void) fw_minor;
(void) fw_major;
#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0 */
#ifdef MCUXCL_FEATURE_ELS_HWCONFIG
// Read the ELS hardware configuration bitmap.
mcuxClEls_HwConfig_t config;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwConfig(&config));
// mcuxClEls_GetHwConfig is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwConfig) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
// Access and store config struct elements
uint32_t ciphersup = config.bits.ciphersup; // cipher command not supported
uint32_t authciphersup = config.bits.authciphersup; // auth_cipher command not supported
uint32_t ecsignsup = config.bits.ecsignsup; // ecsign command not supported
uint32_t ecvfysup = config.bits.ecvfysup; // ecvfy command not supported
uint32_t eckxchsup = config.bits.eckxchsup; // dhkey_xch command is supported
uint32_t keygensup = config.bits.keygensup; // keygen command not supported
uint32_t keyinsup = config.bits.keyinsup; // keyin command not supported
uint32_t keyoutsup = config.bits.keyoutsup; // keyout command not supported
uint32_t kdeletesup = config.bits.kdeletesup; // kdelete command not supported
uint32_t ckdfsup = config.bits.ckdfsup; // ckdf command not supported
uint32_t hkdfsup = config.bits.hkdfsup; // hkdf command not supported
uint32_t tlsinitsup = config.bits.tlsinitsup; // tls_init command not supported
uint32_t hashsup = config.bits.hashsup; // hash command not supported
uint32_t hmacsup = config.bits.hmacsup; // hmac command not supported
uint32_t drbgreqsub = config.bits.drbgreqsub; // drbg_req command not supported
uint32_t dtrgncfgloadsup = config.bits.dtrgncfgloadsup; // dtrng_cfg_load command is not supported
uint32_t dtrngevalsup = config.bits.dtrngevalsup; // dtrng_eval command not supported
char const* sw_version = mcuxCl_GetVersion(); // Read the CLNS version string that uniquely identifies this release of the CLNS.
// MCUXCL_VERSION_MAX_SIZE is the maximum size in bytes of the version string.
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
#endif
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01290.html b/components/els_pkc/doc/mcxn/html/a01290.html new file mode 100644 index 000000000..f1c1aaba0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01290.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Sha224_One_Block_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Hash_Sha224_One_Block_example.c
+
+
+

Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const sha224_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_224] = {0x61U, 0x62U, 0x63U, 0x80U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x18U};
static uint8_t sha224_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224] = {0x23U, 0x09U, 0x7dU, 0x22U,
0x34U, 0x05U, 0xd8U, 0x22U,
0x86U, 0x42U, 0xa4U, 0x77U,
0xbdU, 0xa2U, 0x55U, 0xb3U,
0x2aU, 0xadU, 0xbcU, 0xe4U,
0xbdU, 0xa0U, 0xb3U, 0xf7U,
0xe3U, 0x6cU, 0x9dU, 0xa7U};
static uint8_t sha2_224_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_224]; // MCUXCLELS_HASH_STATE_SIZE_SHA_224 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state.
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha224_One_Block_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation.
hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector).
hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation.
hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_224; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-224 algorithm is used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing.
hash_options, // Set the prepared configuration.
sha224_padded_input, sizeof(sha224_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required
sha2_224_digest // Output buffer, which the operation will write the hash digest to.
));
// mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0; i < sizeof(sha224_reference_digest); i++)
{
if (sha2_224_digest[i] != sha224_reference_digest[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01291.html b/components/els_pkc/doc/mcxn/html/a01291.html new file mode 100644 index 000000000..2899451dd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01291.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Sha256_One_Block_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Hash_Sha256_One_Block_example.c
+
+
+

Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const sha256_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_256] = {0x61U, 0x62U, 0x63U, 0x80U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x18U};
static uint8_t sha256_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256] = {0xBAU, 0x78U, 0x16U, 0xBFU,
0x8FU, 0x01U, 0xCFU, 0xEAU,
0x41U, 0x41U, 0x40U, 0xDEU,
0x5DU, 0xAEU, 0x22U, 0x23U,
0xB0U, 0x03U, 0x61U, 0xA3U,
0x96U, 0x17U, 0x7AU, 0x9CU,
0xB4U, 0x10U, 0xFFU, 0x61U,
0xF2U, 0x00U, 0x15U, 0xADU};
static uint8_t sha2_256_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_256]; // MCUXCLELS_HASH_STATE_SIZE_SHA_256 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state.
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha256_One_Block_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation.
hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector).
hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation.
hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_256; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-256 algorithm is used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing.
hash_options, // Set the prepared configuration.
sha256_padded_input, sizeof(sha256_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required
sha2_256_digest // Output buffer, which the operation will write the hash digest to.
));
// mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0; i < sizeof(sha256_reference_digest); i++)
{
if (sha2_256_digest[i] != sha256_reference_digest[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01292.html b/components/els_pkc/doc/mcxn/html/a01292.html new file mode 100644 index 000000000..c8710e7b3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01292.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Sha384_One_Block_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Hash_Sha384_One_Block_example.c
+
+
+

Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const sha384_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_384] = {0x61U, 0x62U, 0x63U, 0x80U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x18U};
static uint8_t sha384_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384] = {0xcbU, 0x00U, 0x75U, 0x3fU,
0x45U, 0xa3U, 0x5eU, 0x8bU,
0xb5U, 0xa0U, 0x3dU, 0x69U,
0x9aU, 0xc6U, 0x50U, 0x07U,
0x27U, 0x2cU, 0x32U, 0xabU,
0x0eU, 0xdeU, 0xd1U, 0x63U,
0x1aU, 0x8bU, 0x60U, 0x5aU,
0x43U, 0xffU, 0x5bU, 0xedU,
0x80U, 0x86U, 0x07U, 0x2bU,
0xa1U, 0xe7U, 0xccU, 0x23U,
0x58U, 0xbaU, 0xecU, 0xa1U,
0x34U, 0xc8U, 0x25U, 0xa7U};
static uint8_t sha2_384_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_384]; // MCUXCLELS_HASH_STATE_SIZE_SHA_384 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state.
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha384_One_Block_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation.
hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector).
hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation.
hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_384; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-384 algorithm is used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing.
hash_options, // Set the prepared configuration.
sha384_padded_input, sizeof(sha384_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required
sha2_384_digest // Output buffer, which the operation will write the hash digest to.
));
// mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0; i < sizeof(sha384_reference_digest); i++)
{
if (sha2_384_digest[i] != sha384_reference_digest[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01293.html b/components/els_pkc/doc/mcxn/html/a01293.html new file mode 100644 index 000000000..ed713f766 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01293.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Hash_Sha512_One_Block_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Hash_Sha512_One_Block_example.c
+
+
+

Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
static uint8_t const sha512_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_512] = {0x61U, 0x62U, 0x63U, 0x80U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00u, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x00U,
0x00U, 0x00U, 0x00U, 0x18U};
static uint8_t sha512_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512] = {0xddU, 0xafU, 0x35U, 0xa1U,
0x93U, 0x61U, 0x7aU, 0xbaU,
0xccU, 0x41U, 0x73U, 0x49U,
0xaeU, 0x20U, 0x41U, 0x31U,
0x12U, 0xe6U, 0xfaU, 0x4eU,
0x89U, 0xa9U, 0x7eU, 0xa2U,
0x0aU, 0x9eU, 0xeeU, 0xe6U,
0x4bU, 0x55U, 0xd3U, 0x9aU,
0x21U, 0x92U, 0x99U, 0x2aU,
0x27U, 0x4fU, 0xc1U, 0xa8U,
0x36U, 0xbaU, 0x3cU, 0x23U,
0xa3U, 0xfeU, 0xebU, 0xbdU,
0x45U, 0x4dU, 0x44U, 0x23U,
0x64U, 0x3cU, 0xe8U, 0x0eU,
0x2aU, 0x9aU, 0xc9U, 0x4fU,
0xa5U, 0x4cU, 0xa4U, 0x9fU};
static uint8_t sha2_512_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_512]; // MCUXCLELS_HASH_STATE_SIZE_SHA_512 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state.
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha512_One_Block_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation.
hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector).
hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation.
hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_512; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-512 algorithm is used.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing.
hash_options, // Set the prepared configuration.
sha512_padded_input, sizeof(sha512_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required
sha2_512_digest // Output buffer, which the operation will write the hash digest to.
));
// mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
for (size_t i = 0; i < sizeof(sha512_reference_digest); i++)
{
if (sha2_512_digest[i] != sha512_reference_digest[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01294.html b/components/els_pkc/doc/mcxn/html/a01294.html new file mode 100644 index 000000000..2c65bc124 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01294.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Rng_Prng_Get_Random_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Rng_Prng_Get_Random_example.c
+
+
+

Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_ELS_Key_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Rng_Prng_Get_Random_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
// PRNG needs to be initialized; this can be done by calling mcuxClEls_KeyDelete_Async (delete any key slot, can be empty)
if(!mcuxClExample_Els_KeyDelete(18))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
uint32_t dummy;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandomWord(&dummy));
// mcuxClEls_Prng_GetRandomWord is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandomWord) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandomWord operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint32_t random[16]; // buffers of 16 CPU words to be filled with random numbers from PRNG.
// fill the buffer with random numbers from PRNG.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom((uint8_t*) random, sizeof(random)));
// mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01295.html b/components/els_pkc/doc/mcxn/html/a01295.html new file mode 100644 index 000000000..520788871 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01295.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Tls_Master_Key_Session_Keys_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Tls_Master_Key_Session_Keys_example.c
+
+
+

TLS key derivation example

+
/*--------------------------------------------------------------------------*/
/* Copyright 2020, 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClMemory.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_ELS_Key_Helper.h>
static mcuxClEls_EccByte_t ecc_public_key_client[MCUXCLELS_ECC_PUBLICKEY_SIZE];
static mcuxClEls_EccByte_t ecc_public_key_server[MCUXCLELS_ECC_PUBLICKEY_SIZE];
static uint8_t derivation_data[MCUXCLELS_TLS_DERIVATIONDATA_SIZE];
static uint8_t client_random[MCUXCLELS_TLS_RANDOM_SIZE];
static uint8_t server_random[MCUXCLELS_TLS_RANDOM_SIZE];
static uint8_t master_key_string[] = "master secret";
static uint8_t key_expansion_string[] = "key expansion";
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Tls_Master_Key_Session_Keys_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Generate client key pair */
mcuxClEls_EccKeyGenOption_t KeyGenOptions = {0};
KeyGenOptions.bits.kgsrc = MCUXCLELS_ECC_OUTPUTKEY_RANDOM; // Configure that a non-deterministic key is generated.
KeyGenOptions.bits.kgtypedh = MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE; //Key will be used for Key Exchange
mcuxClEls_KeyProp_t GenKeyProp = {0};
GenKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access
GenKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access
mcuxClEls_KeyIndex_t keyIdxPrivClient = 0u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation.
KeyGenOptions, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration.
keyIdxPrivClient, // Keystore index at which the generated private key is stored.
GenKeyProp, // Set the generated key properties.
NULL,
ecc_public_key_client // Output buffer, which the operation will write the public key to.
));
// mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate server key pair */
mcuxClEls_KeyIndex_t keyIdxPrivServer = 2u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation.
KeyGenOptions, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration.
keyIdxPrivServer, // Keystore index at which the generated private key is stored.
GenKeyProp, // Set the generated key properties.
NULL,
ecc_public_key_server // Output buffer, which the operation will write the public key to.
));
// mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
//Perform Key Exchange
mcuxClEls_KeyIndex_t sharedSecretIdx = 10U; // Set shared key index
mcuxClEls_KeyProp_t SharedSecretProp = {0}; // Initialize a new configuration for the mcuxClEls_EccKeyExchange_Async generated key properties.
SharedSecretProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access
SharedSecretProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access
SharedSecretProp.bits.utlpsms = MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE; //Shared Secret is used as pre-master secret for TLS
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyExchange_Async(
keyIdxPrivClient,
ecc_public_key_server,
sharedSecretIdx,
SharedSecretProp));
// mcuxClEls_EccKeyExchange_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyExchange_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyExchange_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyExchange_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
// PRNG needs to be initialized; this can be done by calling mcuxClEls_KeyDelete_Async (delete any key slot, can be empty)
// However mcuxClEls_EccKeyExchange_Async also guarantees PRNG is initialized
//generate server random
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom(server_random, 32U));
// mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
//generate client random
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom(client_random, 32U));
// mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
//perpare derivation data for master key
//the derivation data has a fixed length of 640 bits and is composed as follows
//"key expansion"||server random||client random||800000
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data,
key_expansion_string,
sizeof(key_expansion_string),
sizeof(key_expansion_string)
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data+sizeof(key_expansion_string),
server_random,
sizeof(server_random),
sizeof(server_random)
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data+sizeof(key_expansion_string)+32U,
client_random,
sizeof(client_random),
sizeof(client_random)
));
// mcuxClMemory_set is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set(
derivation_data+sizeof(key_expansion_string)+32U+32U,
0x80,
1U,
1U
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set(
derivation_data+sizeof(key_expansion_string)+32U+32U+1U,
0x00,
2U,
2U
));
// mcuxClMemory_set is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
mcuxClEls_KeyProp_t tlsMasterKeyProp = {0};
tlsMasterKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access
tlsMasterKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access
tlsMasterKeyProp.bits.utlsms = MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE;
//Generate TLS master key
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async(
derivation_data,
tlsMasterKeyProp,
sharedSecretIdx
));
// mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
//perpare derivation data for session keys
//the derivation data has a fixed length of 640 bits and is composed as follows
//"master secret"||client random||server random||800000
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data,
master_key_string,
sizeof(master_key_string),
sizeof(master_key_string)
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data+sizeof(master_key_string),
client_random,
sizeof(client_random),
sizeof(client_random)
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
derivation_data+sizeof(master_key_string)+32U,
server_random,
sizeof(server_random),
sizeof(server_random)
));
// mcuxClMemory_set is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set(
derivation_data+sizeof(master_key_string)+32U+32U,
0x80,
1U,
1U
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set(
derivation_data+sizeof(master_key_string)+32U+32U+1U,
0x00,
2U,
2U
));
// mcuxClMemory_set is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
mcuxClEls_KeyProp_t KeyProp = {0};
mcuxClEls_GetKeyProperties(sharedSecretIdx, &KeyProp);
//Generate TLS session keys
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async(
derivation_data,
GenKeyProp,
sharedSecretIdx
));
// mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
//Delete all keys from keystore
if(!mcuxClExample_Els_KeyDelete(keyIdxPrivClient))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_KeyDelete(keyIdxPrivServer))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
for(uint8_t i = sharedSecretIdx;i<sharedSecretIdx + 6;i++)
{
if(!mcuxClExample_Els_KeyDelete(i))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
//Now the session keys are stored in the key store as follows:
//Client Mac Key : sharedSecretIdx (2-3)
//Server Mac Key : sharedSecretIdx+2 (4-5)
//Client Encryption Key : sharedSecretIdx+4 (6)
//Server Encryption Key : sharedSecretIdx+6 (7)
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01296.html b/components/els_pkc/doc/mcxn/html/a01296.html new file mode 100644 index 000000000..e01c47805 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01296.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEls_Key_Import_Puk_DER_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEls_Key_Import_Puk_DER_example.c
+
+
+

Example of PuK import from a DER-encoded certificate using the ELS (CLNS component mcuxClEls)

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClMemory.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_ELS_Key_Helper.h>
#include <mcuxClExample_RFC3394_Helper.h>
static uint8_t const der_certificate[450U] = {
// certificate
0x30U, 0x82U, 0x01U, 0xBEU, 0x30U, 0x82U, 0x01U, 0x63U, 0x02U, 0x14U, 0x14U, 0xFDU, 0x55U, 0xCAU, 0x4AU, 0x3BU,
0x27U, 0xB7U, 0x47U, 0xCAU, 0x12U, 0x5CU, 0xD4U, 0x52U, 0x6DU, 0x82U, 0xC9U, 0xB5U, 0xB7U, 0xA7U, 0x30U, 0x0AU,
0x06U, 0x08U, 0x2AU, 0x86U, 0x48U, 0xCEU, 0x3DU, 0x04U, 0x03U, 0x02U, 0x30U, 0x61U, 0x31U, 0x0BU, 0x30U, 0x09U,
0x06U, 0x03U, 0x55U, 0x04U, 0x06U, 0x13U, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U,
0x04U, 0x08U, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x07U, 0x0CU,
0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x0AU, 0x0CU, 0x02U, 0x30U, 0x30U,
0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x0BU, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U,
0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x03U, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x11U, 0x30U, 0x0FU, 0x06U, 0x09U,
0x2AU, 0x86U, 0x48U, 0x86U, 0xF7U, 0x0DU, 0x01U, 0x09U, 0x01U, 0x16U, 0x02U, 0x30U, 0x30U, 0x30U, 0x1EU, 0x17U,
0x0DU, 0x32U, 0x31U, 0x31U, 0x32U, 0x31U, 0x33U, 0x31U, 0x30U, 0x31U, 0x32U, 0x30U, 0x35U, 0x5AU, 0x17U, 0x0DU,
0x32U, 0x32U, 0x31U, 0x32U, 0x31U, 0x33U, 0x31U, 0x30U, 0x31U, 0x32U, 0x30U, 0x35U, 0x5AU, 0x30U, 0x61U, 0x31U,
0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x06U, 0x13U, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U,
0x06U, 0x03U, 0x55U, 0x04U, 0x08U, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U,
0x04U, 0x07U, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x0AU, 0x0CU,
0x02U, 0x30U, 0x30U, 0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x0BU, 0x0CU, 0x02U, 0x30U, 0x30U,
0x31U, 0x0BU, 0x30U, 0x09U, 0x06U, 0x03U, 0x55U, 0x04U, 0x03U, 0x0CU, 0x02U, 0x30U, 0x30U, 0x31U, 0x11U, 0x30U,
0x0FU, 0x06U, 0x09U, 0x2AU, 0x86U, 0x48U, 0x86U, 0xF7U, 0x0DU, 0x01U, 0x09U, 0x01U, 0x16U, 0x02U, 0x30U, 0x30U,
// public key metadata
0x30U, 0x59U, 0x30U, 0x13U, 0x06U, 0x07U, 0x2AU, 0x86U, 0x48U, 0xCEU, 0x3DU, 0x02U, 0x01U, 0x06U, 0x08U, 0x2AU,
0x86U, 0x48U, 0xCEU, 0x3DU, 0x03U, 0x01U, 0x07U,
// public key header
0x03U, 0x42U, 0x00U, 0x04U,
// public key
0x12U, 0x54U, 0x6EU, 0xDBU, 0x7CU, 0xD4U, 0x85U, 0xBEU, 0xDDU, 0x5BU, 0x3BU, 0x71U, 0xB7U, 0x0EU, 0xC2U, 0x19U,
0x34U, 0x76U, 0x3BU, 0xAFU, 0xD2U, 0xE5U, 0xA2U, 0x76U, 0xCAU, 0xB6U, 0x09U, 0x63U, 0x09U, 0xA5U, 0x7FU, 0xEEU,
0xF9U, 0x74U, 0x18U, 0x5DU, 0x9AU, 0x4AU, 0x0EU, 0x88U, 0x4AU, 0xBEU, 0xF4U, 0xBEU, 0xBDU, 0xC9U, 0x96U, 0x64U,
0xBBU, 0xD5U, 0x67U, 0x94U, 0xACU, 0x9CU, 0x30U, 0xBAU, 0xF7U, 0xCFU, 0x36U, 0x18U, 0x91U, 0x10U, 0xE6U, 0x7EU,
// signature header
0x30U, 0x0AU, 0x06U, 0x08U, 0x2AU, 0x86U, 0x48U, 0xCEU, 0x3DU, 0x04U, 0x03U, 0x02U, 0x03U, 0x49U, 0x00U, 0x30U,
0x46U,
// signature x header
0x02U, 0x21U,
// signature x
0x00U, 0xC3U, 0x08U, 0x77U, 0xFBU, 0x74U, 0x0FU, 0x18U, 0x57U, 0xC0U, 0x1EU, 0xE1U, 0x22U, 0x5CU, 0x07U, 0x54U,
0x29U, 0x2AU, 0xEAU, 0x79U, 0x1DU, 0x06U, 0xEFU, 0xF0U, 0x61U, 0xEAU, 0xB7U, 0xEDU, 0x83U, 0x5BU, 0x16U, 0x64U,
0x9BU,
// signature y header
0x02U, 0x21U,
// signature y
0x00U, 0xB0U, 0x8BU, 0xFAU, 0x21U, 0x8EU, 0x03U, 0x9BU, 0xA4U, 0x14U, 0x69U, 0x1AU, 0x81U, 0x93U, 0xF2U, 0x13U,
0x27U, 0x06U, 0x28U, 0x24U, 0xB1U, 0x1DU, 0x64U, 0x72U, 0x79U, 0xADU, 0x92U, 0x6EU, 0x9CU, 0xD2U, 0x79U, 0x8BU,
0xFDU
};
#define SHA256_BLOCK_SIZE 64U
static size_t der_certificate_offset_pbk = 299U;
static size_t der_certificate_len_without_signature = 363U;
static uint8_t key_rfc3394[MCUXCLELS_RFC3394_CONTAINER_SIZE_P256] = { 0U };
static uint8_t der_certificate_import[sizeof(der_certificate) + SHA256_BLOCK_SIZE] = { 0U };
static mcuxClEls_EccByte_t ecc_root_public_key[MCUXCLELS_ECC_PUBLICKEY_SIZE] = { 0U };
static mcuxClEls_EccByte_t ecc_root_public_key_switched[MCUXCLELS_ECC_PUBLICKEY_SIZE] = { 0U };
static mcuxClEls_EccByte_t ecc_signature[MCUXCLELS_ECC_SIGNATURE_SIZE] __attribute__ ((aligned (4))) = { 0U };
static mcuxClEls_EccByte_t ecc_signature_r[MCUXCLELS_ECC_SIGNATURE_R_SIZE] __attribute__ ((aligned (4))) = { 0U };
MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Key_Import_Puk_DER_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Key indices in internal keystore. */
uint8_t key_idx_helper_key = 0u;
uint8_t key_idx_ecc_root_private_key = 8u;
uint8_t key_idx_ecc_root_public_key = 12u;
uint8_t key_idx_ecc_import_public_key = 16u;
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set(
der_certificate_import,
0x00,
sizeof(der_certificate_import),
sizeof(der_certificate_import)
));
// mcuxClMemory_set is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy(
der_certificate_import,
der_certificate,
der_certificate_len_without_signature,
sizeof(der_certificate_import)
));
// mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value
if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_VOID_END();
/* Set one bit after the certificate. */
der_certificate_import[der_certificate_len_without_signature] = 0x80;
/* Compute length with added padding. */
size_t der_certificate_paddedLength = (((uint32_t) (der_certificate_len_without_signature) + SHA256_BLOCK_SIZE - 1u) & (~((uint32_t) SHA256_BLOCK_SIZE - 1u)));
/* Set certificate length in last padding bytes. */
size_t padIndex = der_certificate_paddedLength;
der_certificate_import[--padIndex] = (uint8_t)(der_certificate_len_without_signature << 3u);
der_certificate_import[--padIndex] = (uint8_t)(der_certificate_len_without_signature >> 5u);
der_certificate_import[--padIndex] = (uint8_t)(der_certificate_len_without_signature >> 13u);
der_certificate_import[--padIndex] = (uint8_t)(der_certificate_len_without_signature >> 21u);
der_certificate_import[--padIndex] = (uint8_t)(der_certificate_len_without_signature >> 29u);
/* Generate signing key */
mcuxClEls_EccKeyGenOption_t keygen_options = {0}; // Initialize a new configuration for the planned mcuxClEls_EccKeyGen_Async operation.
keygen_options.bits.kgsrc = MCUXCLELS_ECC_OUTPUTKEY_RANDOM; // Configure that a non-deterministic key is generated.
keygen_options.bits.kgsign = MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE; // Configure that the key does not need to be signed.
keygen_options.bits.kgtypedh = MCUXCLELS_ECC_OUTPUTKEY_SIGN; // Configure key to be a signing key.
mcuxClEls_KeyProp_t keygen_prop = {0}; // Initialize a new configuration for the mcuxClEls_EccKeyGen_Async generated key properties.
keygen_prop.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE; // Configure that user access rights: privileged access
keygen_prop.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_FALSE; // Configure that user access rights: non-secure access
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation.
keygen_options, // Set the prepared configuration.
(mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration.
key_idx_ecc_root_private_key, // Keystore index at which the generated private key is stored.
keygen_prop, // Set the generated key properties.
NULL, // No random data is provided
ecc_root_public_key // Output buffer, which the operation will write the public key to.
));
// mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Sign certificate */
mcuxClEls_EccSignOption_t sign_options = {0}; // Initialize a new configuration for the planned mcuxClEls_EccSign_Async operation.
sign_options.bits.echashchl = MCUXCLELS_ECC_NOT_HASHED; // Input is a full certificate, not a digest.
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccSign_Async( // Perform signature generation.
sign_options, // Set the prepared configuration.
key_idx_ecc_root_private_key, // Set index of private key in keystore.
NULL, // No input hash is provided
der_certificate_import, // Input is the certificate
der_certificate_paddedLength, // Length of the certificate
ecc_signature // Output buffer, which the operation will write the signature to.
));
// mcuxClEls_EccSign_Async is a flow-protected function: Check the protection token and the return value
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccSign_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccSign_Async operation was started.
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccSign_Async operation to complete.
// mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
mcuxClEls_KeyProp_t key_properties;
/* Provision helper key */
key_properties.word.value = 0U;
key_properties.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE;
key_properties.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE;
key_properties.bits.uaes = MCUXCLELS_KEYPROPERTY_AES_TRUE;
key_properties.bits.ukuok = MCUXCLELS_KEYPROPERTY_KUOK_TRUE;
key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_256;
key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
key_properties.bits.kbase = MCUXCLELS_KEYPROPERTY_BASE_SLOT;
mcuxClEls_KeyProvisionOption_t key_provision_options;
key_provision_options.word.value = 0U;
key_provision_options.bits.noic = MCUXCLELS_KEYPROV_NOIC_ENABLE;
#error KEYPROV command not supported
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Switch X and Y coordinates. */
for(size_t i = 0; i < MCUXCLELS_ECC_PUBLICKEY_SIZE / 2u; i++)
{
ecc_root_public_key_switched[i] = ecc_root_public_key[i + MCUXCLELS_ECC_PUBLICKEY_SIZE / 2u];
ecc_root_public_key_switched[i + MCUXCLELS_ECC_PUBLICKEY_SIZE / 2u] = ecc_root_public_key[i];
}
/* Wrap public key. */
key_properties.word.value = 0u;
key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_512;
key_properties.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE;
key_properties.bits.upuk = MCUXCLELS_KEYPROPERTY_PUK_TRUE;
key_properties.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_FALSE;
key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
bool wrap_result = mcuxClExample_rfc3394_wrap(
/*const uint8_t * pInput */ ecc_root_public_key_switched, /* pointer to key to be wrapped */
/*size_t inputLength, */ MCUXCLELS_ECC_PUBLICKEY_SIZE, /* length of key to be wrapped in bytes */
/*const uint8_t * pKek_in */ NULL, /* pointer to key wrapping key */
/*mcuxClEls_KeyIndex_t keyIdx */ key_idx_helper_key, /* keyslot index of key wrapping key */
/*uint8_t extkey */ 0U, /* 0-use key stored internally at keyIdx as wrapping key, 1-use external pKek_in as wrapping key */
/*size_t kekLength */ 0U, /* length of key wrapping key in bytes */
/*uint8_t * pOutput */ key_rfc3394, /* pointer to output buffer, size has to be inputLength + 16 bytes */
/*mcuxClEls_KeyProp_t properties */ key_properties); /* properties of the key to be wrapped */
if (!wrap_result)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Import root public key. */
mcuxClEls_KeyImportOption_t import_options;
import_options.word.value = 0u;
import_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyImport_Async(import_options,
key_rfc3394,
MCUXCLELS_RFC3394_CONTAINER_SIZE_P256,
key_idx_helper_key,
key_idx_ecc_root_public_key
)); // Wait for the mcuxClEls_KeyImportPuk_Async operation to complete.
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyImport_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
key_properties.word.value = 0u;
key_properties.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE;
key_properties.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_FALSE;
key_properties.bits.wrpok = MCUXCLELS_KEYPROPERTY_WRAP_TRUE;
key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_512;
key_properties.bits.upuk = MCUXCLELS_KEYPROPERTY_PUK_TRUE;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyImportPuk_Async(der_certificate_import,
der_certificate_paddedLength,
der_certificate_offset_pbk,
ecc_signature,
key_idx_ecc_root_public_key,
key_properties,
key_idx_ecc_import_public_key,
ecc_signature_r)); // Wait for the mcuxClEls_KeyImportPuk_Async operation to complete.
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyImportPuk_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete.
// mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Verify R. */
for(size_t i = 0; i < MCUXCLELS_ECC_SIGNATURE_R_SIZE; i++)
{
if ((uint8_t) ecc_signature[i] != (uint8_t) ecc_signature_r[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
/* Verify key properties of imported key. */
mcuxClEls_KeyProp_t key_properties_imported;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetKeyProperties(key_idx_ecc_import_public_key, &key_properties_imported));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties) != token) || (MCUXCLELS_STATUS_OK != result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if (key_properties.bits.ksize != key_properties_imported.bits.ksize)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if (key_properties.bits.kactv != key_properties_imported.bits.kactv)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if (key_properties.bits.upuk != key_properties_imported.bits.upuk)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_KeyDelete(key_idx_helper_key))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_KeyDelete(key_idx_ecc_root_private_key))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_KeyDelete(key_idx_ecc_root_public_key))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_KeyDelete(key_idx_ecc_import_public_key))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01297.html b/components/els_pkc/doc/mcxn/html/a01297.html new file mode 100644 index 000000000..95ef927a2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01297.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Mont_Curve25519_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_Mont_Curve25519_example.c
+
+
+

Example for the mcuxClEcc component Curve25519 related functions

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandomModes.h>
#include <mcuxClRandom.h>
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE)
#define MAX_PKCWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE)
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve25519_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
//Allocate and initialize session with pkcWA on the beginning of PKC RAM
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg);
/* Prepare input for Alice key generation */
uint8_t alicePrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t alicePrivKeyHandler = (mcuxClKey_Handle_t) &alicePrivKeyDesc;
uint8_t alicePubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t alicePubKeyHandler = (mcuxClKey_Handle_t) &alicePubKeyDesc;
uint8_t alicePrivKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY]={0};
uint8_t alicePubKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY]={0};
uint32_t alicePrivKeySize = 0u;
uint32_t alicePubKeySize = 0u;
/* Call Dh KeyGeneration for Alice keys generation and check FP and return code */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keygeneration_result, alice_keygeneration_token,
mcuxClEcc_Mont_DhKeyGeneration(&session,
mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair,
mcuxClKey_Protection_None,
alicePrivKeyHandler,
alicePrivKeyBuffer, &alicePrivKeySize,
alicePubKeyHandler,
alicePubKeyBuffer, &alicePubKeySize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != alice_keygeneration_token) || (MCUXCLECC_STATUS_OK != alice_keygeneration_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Bob key generation */
uint8_t bobPrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t bobPrivKeyHandler = (mcuxClKey_Handle_t) &bobPrivKeyDesc;
uint8_t bobPubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t bobPubKeyHandler = (mcuxClKey_Handle_t) &bobPubKeyDesc;
uint8_t bobPrivKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY]={0};
uint8_t bobPubKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY]={0};
uint32_t bobPrivKeySize = 0u;
uint32_t bobPubKeySize = 0u;
/* Call Dh KeyGeneration for Bob keys generation and check FP and return code */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keygeneration_result, bob_keygeneration_token,
mcuxClEcc_Mont_DhKeyGeneration(&session,
mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair,
mcuxClKey_Protection_None,
bobPrivKeyHandler,
bobPrivKeyBuffer, &bobPrivKeySize,
bobPubKeyHandler,
bobPubKeyBuffer, &bobPubKeySize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != bob_keygeneration_token) || (MCUXCLECC_STATUS_OK != bob_keygeneration_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Alice shared secret calculation */
uint8_t aliceSharedSecret[MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET];
uint32_t aliceSharedSecretSize;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keyagreement_result, alice_keyagreement_token,
mcuxClEcc_Mont_DhKeyAgreement(&session,
alicePrivKeyHandler,
bobPubKeyHandler,
aliceSharedSecret,
&aliceSharedSecretSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != alice_keyagreement_token) || (MCUXCLECC_STATUS_OK != alice_keyagreement_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Bob shared secret calculation */
uint8_t bobSharedSecret[MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET];
uint32_t bobSharedSecretSize;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keyagreement_result, bob_keyagreement_token,
mcuxClEcc_Mont_DhKeyAgreement(&session,
bobPrivKeyHandler,
alicePubKeyHandler,
bobSharedSecret,
&bobSharedSecretSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != bob_keyagreement_token) || (MCUXCLECC_STATUS_OK != bob_keyagreement_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Alice's shared secret shall be equal to Bob's shared secret */
for(size_t i = 0u; i < MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET; i++)
{
if(bobSharedSecret[i] != aliceSharedSecret[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01298.html b/components/els_pkc/doc/mcxn/html/a01298.html new file mode 100644 index 000000000..89ea57467 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01298.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_Mont_Curve448_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_Mont_Curve448_example.c
+
+
+

Example for the mcuxClEcc component curve448 related functions

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandomModes.h>
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClExample_ELS_Helper.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE)
#define MAX_PKCWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE)
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve448_example)
{
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
//Allocate and initialize session with pkcWA on the beginning of PKC RAM
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE, mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3);
/* Prepare input for Alice key generation */
uint8_t alicePrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t alicePrivKeyHandler = (mcuxClKey_Handle_t) &alicePrivKeyDesc;
uint8_t alicePubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t alicePubKeyHandler = (mcuxClKey_Handle_t) &alicePubKeyDesc;
uint8_t alicePrivKeyBuffer[MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY]={0};
uint8_t alicePubKeyBuffer[MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY]={0};
uint32_t alicePrivKeySize = 0u;
uint32_t alicePubKeySize = 0u;
/* Call Dh KeyGeneration for Alice keys generation and check FP and return code */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keygeneration_result, alice_keygeneration_token,
mcuxClEcc_Mont_DhKeyGeneration(&session,
mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair,
mcuxClKey_Protection_None,
alicePrivKeyHandler,
alicePrivKeyBuffer,
&alicePrivKeySize,
alicePubKeyHandler,
alicePubKeyBuffer,
&alicePubKeySize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != alice_keygeneration_token) || (MCUXCLECC_STATUS_OK != alice_keygeneration_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Bob key generation */
uint8_t bobPrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t bobPrivKeyHandler = (mcuxClKey_Handle_t) &bobPrivKeyDesc;
uint8_t bobPubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t bobPubKeyHandler = (mcuxClKey_Handle_t) &bobPubKeyDesc;
uint8_t bobPrivKeyBuffer[MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY]={0};
uint8_t bobPubKeyBuffer[MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY]={0};
uint32_t bobPrivKeySize = 0u;
uint32_t bobPubKeySize = 0u;
/* Call Dh KeyGeneration for Bob keys generation and check FP and return code */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keygeneration_result, bob_keygeneration_token,
mcuxClEcc_Mont_DhKeyGeneration(&session,
mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair,
mcuxClKey_Protection_None,
bobPrivKeyHandler,
bobPrivKeyBuffer, &bobPrivKeySize,
bobPubKeyHandler,
bobPubKeyBuffer,
&bobPubKeySize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != bob_keygeneration_token) || (MCUXCLECC_STATUS_OK != bob_keygeneration_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Alice shared secret calculation */
uint8_t aliceSharedSecret[MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET];
uint32_t aliceSharedSecretSize;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keyagreement_result, alice_keyagreement_token,
mcuxClEcc_Mont_DhKeyAgreement(&session,
alicePrivKeyHandler,
bobPubKeyHandler,
aliceSharedSecret,
&aliceSharedSecretSize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != alice_keyagreement_token) || (MCUXCLECC_STATUS_OK != alice_keyagreement_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Prepare input for Bob shared secret calculation */
uint8_t bobSharedSecret[MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET];
uint32_t bobSharedSecretSize;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keyagreement_result, bob_keyagreement_token,
mcuxClEcc_Mont_DhKeyAgreement(&session,
bobPrivKeyHandler,
alicePubKeyHandler,
bobSharedSecret,
&bobSharedSecretSize)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != bob_keyagreement_token) || (MCUXCLECC_STATUS_OK != bob_keyagreement_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Alice's shared secret shall be equal to Bob's shared secret */
for(size_t i = 0u; i < MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET; i++)
{
if(bobSharedSecret[i] != aliceSharedSecret[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01299.html b/components/els_pkc/doc/mcxn/html/a01299.html new file mode 100644 index 000000000..c4b54f973 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01299.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c
+
+
+

Example for the mcuxClEcc component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClCore_Examples.h>
#include <mcuxClSession.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClKey.h>
#include <mcuxClEcc.h>
#include <mcuxClEcc_WeierECC.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#define BN256_BYTE_LEN_P (32u)
#define BN256_BYTE_LEN_N (32u)
static const uint8_t BN_P256_P[BN256_BYTE_LEN_P] =
{
/* p = 0xFFFFFFFFFFFCF0CD46E5F25EEE71A49F0CDC65FB12980A82D3292DDBAED33013 */
0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFCu, 0xF0u, 0xCDu,
0x46u, 0xE5u, 0xF2u, 0x5Eu, 0xEEu, 0x71u, 0xA4u, 0x9Fu,
0x0Cu, 0xDCu, 0x65u, 0xFBu, 0x12u, 0x98u, 0x0Au, 0x82u,
0xD3u, 0x29u, 0x2Du, 0xDBu, 0xAEu, 0xD3u, 0x30u, 0x13u};
static const uint8_t BN_P256_A[BN256_BYTE_LEN_P] =
{
/* a = 0x0000000000000000000000000000000000000000000000000000000000000000 */
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u
};
static const uint8_t BN_P256_B[BN256_BYTE_LEN_P] =
{
/* b = 0x0000000000000000000000000000000000000000000000000000000000000003 */
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u
};
static const uint8_t BN_P256_G[2u * BN256_BYTE_LEN_P] =
{
/* G = (x,y) with
* x = 0x0000000000000000000000000000000000000000000000000000000000000001 */
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,
/* y = 0x0000000000000000000000000000000000000000000000000000000000000002 */
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u
};
static const uint8_t BN_P256_N[BN256_BYTE_LEN_N] =
{
/* n = 0xFFFFFFFFFFFCF0CD46E5F25EEE71A49E0CDC65FB1299921AF62D536CD10B500D */
0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFCu, 0xF0u, 0xCDu,
0x46u, 0xE5u, 0xF2u, 0x5Eu, 0xEEu, 0x71u, 0xA4u, 0x9Eu,
0x0Cu, 0xDCu, 0x65u, 0xFBu, 0x12u, 0x99u, 0x92u, 0x1Au,
0xF6u, 0x2Du, 0x53u, 0x6Cu, 0xD1u, 0x0Bu, 0x50u, 0x0Du
};
#define MAX_CPUWA_SIZE MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE
#define MAX_PKCWA_SIZE MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(BN256_BYTE_LEN_P, BN256_BYTE_LEN_N)
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t pSession = &sessionDesc;
/* Allocate and initialize session */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(pSession, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/**************************************************************************/
/* Create structure providing custom domain parameters (BN_P256), which */
/* will be converted to the optimized form accepted by mcuxClEcc APIs */
/**************************************************************************/
mcuxClEcc_Weier_BasicDomainParams_t EccWeierBasicDomainParams;
EccWeierBasicDomainParams.pP = BN_P256_P;
EccWeierBasicDomainParams.pLen = BN256_BYTE_LEN_P;
EccWeierBasicDomainParams.pA = BN_P256_A;
EccWeierBasicDomainParams.pB = BN_P256_B;
EccWeierBasicDomainParams.pG = BN_P256_G;
EccWeierBasicDomainParams.pN = BN_P256_N;
EccWeierBasicDomainParams.nLen = BN256_BYTE_LEN_N;
/**************************************************************************/
/* Convert custom domain parameters (BN_P256) and store it in */
/* the optimized form accepted by mcuxClEcc APIs */
/**************************************************************************/
uint32_t eccWeierDomainParams[MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(BN256_BYTE_LEN_P, BN256_BYTE_LEN_N) / (sizeof(uint32_t))];
mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams = (mcuxClEcc_Weier_DomainParams_t *) eccWeierDomainParams;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genOptEccParams_status, genOptEccParams_token,
mcuxClEcc_WeierECC_GenerateDomainParams(pSession,
pEccWeierDomainParams,
&EccWeierBasicDomainParams,
MCUXCLECC_OPTION_GENERATEPRECPOINT_YES)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateDomainParams) != genOptEccParams_token) || (MCUXCLECC_STATUS_OK != genOptEccParams_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate custom private and public key types for BN_P256 */
/**************************************************************************/
uint32_t customPrivKeyTypeDescriptor[MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS] = {0};
mcuxClKey_CustomType_t customPrivKeyType = (mcuxClKey_CustomType_t) customPrivKeyTypeDescriptor;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genPrivKeyType_status, genPrivKeyType_token, mcuxClEcc_WeierECC_GenerateCustomKeyType(
/* mcuxClKey_CustomType_t customType */ customPrivKeyType,
/* mcuxClKey_AlgorithmId_t algoId */ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY,
/* mcuxClKey_Size_t size */ MCUXCLKEY_SIZE_256,
/* void *pCustomParams */ (void *) pEccWeierDomainParams)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateCustomKeyType) != genPrivKeyType_token) || (MCUXCLECC_STATUS_OK != genPrivKeyType_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint32_t customPubKeyTypeDescriptor[MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS] = {0};
mcuxClKey_CustomType_t customPubKeyType = (mcuxClKey_CustomType_t) customPubKeyTypeDescriptor;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genPubKeyType_status, genPubKeyType_token, mcuxClEcc_WeierECC_GenerateCustomKeyType(
/* mcuxClKey_CustomType_t customType */ customPubKeyType,
/* mcuxClKey_AlgorithmId_t algoId */ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY,
/* mcuxClKey_Size_t size */ MCUXCLKEY_SIZE_512,
/* void *pCustomParams */ (void *) pEccWeierDomainParams)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateCustomKeyType) != genPubKeyType_token) || (MCUXCLECC_STATUS_OK != genPubKeyType_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize private key handle for an BN_P256 private key */
uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc;
uint8_t pPrivKeyData[MCUXCLKEY_SIZE_256];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ki_priv_status, ki_priv_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ pSession,
/* mcuxClKey_Handle_t key */ privKey,
/* mcuxClKey_Type_t type */ customPrivKeyType,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData,
/* uint32_t keyDataLength */ MCUXCLKEY_SIZE_256)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != ki_priv_token) || (MCUXCLKEY_STATUS_OK != ki_priv_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize public key handle for an BN_P256 public key */
uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc;
uint8_t pPubKeyData[MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ki_pub_status, ki_pub_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ pSession,
/* mcuxClKey_Handle_t key */ pubKey,
/* mcuxClKey_Type_t type */ customPubKeyType,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData,
/* uint32_t keyDataLength */ MCUXCLKEY_SIZE_512)
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != ki_pub_token) || (MCUXCLKEY_STATUS_OK != ki_pub_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Clean session */
/**************************************************************************/
if(!mcuxClExample_Session_Clean(pSession))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01300.html b/components/els_pkc/doc/mcxn/html/a01300.html new file mode 100644 index 000000000..d2f3708b2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01300.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_EdDSA_Ed25519ctx_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_EdDSA_Ed25519ctx_example.c
+
+
+

Example for the mcuxClEcc component EdDsa related functions

+
/*--------------------------------------------------------------------------*/
/* Copyright 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandomModes.h>
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxClExample_ELS_Helper.h>
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLEXAMPLE_MAX(\
MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE,\
MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE),\
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE)
#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLEXAMPLE_MAX(\
MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE,\
MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE),\
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE)
#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize) \
(((bytesize) + sizeof(uint32_t) - 1U ) / (sizeof(uint32_t)))
/* Input taken from "foo" from Section 7.2 of IRTF rfc 8032 */
static const uint8_t pMessage[] __attribute__ ((aligned (4))) =
{
0xf7u, 0x26u, 0x93u, 0x6du, 0x19u, 0xc8u, 0x00u, 0x49u,
0x4eu, 0x3fu, 0xdau, 0xffu, 0x20u, 0xb2u, 0x76u, 0xa8u,
};
/* Context taken from "foo" from Section 7.2 of IRTF rfc 8032 */
static const uint8_t pContext[] __attribute__ ((aligned (4))) =
{
0x66u, 0x6fu, 0x6fu
};
/* Signature taken from "foo" from Section 7.2 of IRTF rfc 8032 */
static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) =
{
0x55u, 0xa4u, 0xccu, 0x2fu, 0x70u, 0xa5u, 0x4eu, 0x04u,
0x28u, 0x8cu, 0x5fu, 0x4cu, 0xd1u, 0xe4u, 0x5au, 0x7bu,
0xb5u, 0x20u, 0xb3u, 0x62u, 0x92u, 0x91u, 0x18u, 0x76u,
0xcau, 0xdau, 0x73u, 0x23u, 0x19u, 0x8du, 0xd8u, 0x7au,
0x8bu, 0x36u, 0x95u, 0x0bu, 0x95u, 0x13u, 0x00u, 0x22u,
0x90u, 0x7au, 0x7fu, 0xb7u, 0xc4u, 0xe9u, 0xb2u, 0xd5u,
0xf6u, 0xccu, 0xa6u, 0x85u, 0xa5u, 0x87u, 0xb4u, 0xb2u,
0x1fu, 0x4bu, 0x88u, 0x8eu, 0x4eu, 0x7eu, 0xdbu, 0x0du
};
/* Private key taken from "foo" from Section 7.2 of IRTF rfc 8032 */
static const uint8_t pPrivateKey[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__ ((aligned (4))) =
{
0x03u, 0x05u, 0x33u, 0x4eu, 0x38u, 0x1au, 0xf7u, 0x8fu,
0x14u, 0x1cu, 0xb6u, 0x66u, 0xf6u, 0x19u, 0x9fu, 0x57u,
0xbcu, 0x34u, 0x95u, 0x33u, 0x5au, 0x25u, 0x6au, 0x95u,
0xbdu, 0x2au, 0x55u, 0xbfu, 0x54u, 0x66u, 0x63u, 0xf6u
};
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519ctx_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
/* Initialize ELS, Enable the ELS */
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
/* Allocate and initialize session with pkcWA on the beginning of PKC RAM */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG context and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg);
/* Allocate space for and initialize private key handle for an Ed25519 private key */
uint32_t privKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)];
mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc;
uint32_t pPrivKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv,
/* mcuxCl_InputBuffer_t pKeyData */ (mcuxCl_InputBuffer_t) pPrivKeyData,
/* uint32_t keyDataLength */ sizeof(pPrivKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize public key handle for an Ed25519 public key */
uint32_t pubKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)];
mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc;
uint32_t pPubKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData,
/* uint32_t keyDataLength */ sizeof(pPubKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */
uint32_t privKeyInputDescriptor[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor,
/* const uint8_t *pPrivKey */ pPrivateKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Key pair generation for EdDSA on Ed25519ctx */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor,
/* mcuxClKey_Handle_t privKey */ privKey,
/* mcuxClKey_Handle_t pubKey */ pubKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate the mode and protocol descriptor */
/**************************************************************************/
/* Allocate space for the hash prefix and a protocol descriptor for Ed25519ctx. */
uint32_t protocolDescBytes[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(sizeof(pContext)))];
mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDesc = (mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *) protocolDescBytes;
/* Generate Ed25519ctx protocol descriptor */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genProtocolDescr_result, protocolDescr_token, mcuxClEcc_EdDSA_GenerateProtocolDescriptor(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams */ &mcuxClEcc_EdDSA_DomainParams_Ed25519,
/* mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor */ pProtocolDesc,
/* uint32_t phflag */ MCUXCLECC_EDDSA_PHFLAG_ZERO,
/* mcuxCl_InputBuffer_t pContext */ (mcuxCl_InputBuffer_t) pContext,
/* uint32_t contextLen */ sizeof(pContext)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) != protocolDescr_token)
|| (MCUXCLECC_STATUS_OK != genProtocolDescr_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519ctx signature generation */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */
uint32_t signature[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE)] = {0u};
uint32_t signatureSize = 0u;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ pProtocolDesc,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* uint8_t *pSignature */ (uint8_t*)signature,
/* uint32_t *const pSignatureSize */ &signatureSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token)
|| (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize)
|| (MCUXCLECC_STATUS_OK != sign_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/******************************************/
/* Signature verification */
/******************************************/
/* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ pProtocolDesc,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* const uint8_t *pSignature */ (const uint8_t*) signature,
/* uint32_t signatureSize */ signatureSize
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Verify the signature with the reference signature. */
if(!mcuxClCore_assertEqual((const uint8_t*)signature, pRefSignature, sizeof(pRefSignature)))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/******************************************/
/* Clean up */
/******************************************/
/* Destroy Session and cleanup Session */
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Disable the ELS */
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01301.html b/components/els_pkc/doc/mcxn/html/a01301.html new file mode 100644 index 000000000..32b80fedb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01301.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_EdDSA_Ed25519ph_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_EdDSA_Ed25519ph_example.c
+
+
+

Example for the mcuxClEcc component EdDsa related functions

+
/*--------------------------------------------------------------------------*/
/* Copyright 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
/* Security Classification: Company Confidential */
/*--------------------------------------------------------------------------*/
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClSession.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxClRandomModes.h>
#include <mcuxClExample_ELS_Helper.h>
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_INIT_WACPU_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE, \
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE))))
#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE, \
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE))
#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize) \
(((bytesize) + sizeof(uint32_t) - 1U) / (sizeof(uint32_t)))
/* Input taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */
static const uint8_t pMessage[] __attribute__((aligned(4))) =
{
0x61u, 0x62u, 0x63u
};
/* Signature taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */
static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__((aligned(4))) =
{
0x98u, 0xa7u, 0x02u, 0x22u, 0xf0u, 0xb8u, 0x12u, 0x1au,
0xa9u, 0xd3u, 0x0fu, 0x81u, 0x3du, 0x68u, 0x3fu, 0x80u,
0x9eu, 0x46u, 0x2bu, 0x46u, 0x9cu, 0x7fu, 0xf8u, 0x76u,
0x39u, 0x49u, 0x9bu, 0xb9u, 0x4eu, 0x6du, 0xaeu, 0x41u,
0x31u, 0xf8u, 0x50u, 0x42u, 0x46u, 0x3cu, 0x2au, 0x35u,
0x5au, 0x20u, 0x03u, 0xd0u, 0x62u, 0xadu, 0xf5u, 0xaau,
0xa1u, 0x0bu, 0x8cu, 0x61u, 0xe6u, 0x36u, 0x06u, 0x2au,
0xaau, 0xd1u, 0x1cu, 0x2au, 0x26u, 0x08u, 0x34u, 0x06u
};
/* Private key taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */
static const uint8_t pPrivateKey[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__((aligned(4))) =
{
0x83u, 0x3fu, 0xe6u, 0x24u, 0x09u, 0x23u, 0x7bu, 0x9du,
0x62u, 0xecu, 0x77u, 0x58u, 0x75u, 0x20u, 0x91u, 0x1eu,
0x9au, 0x75u, 0x9cu, 0xecu, 0x1du, 0x19u, 0x75u, 0x5bu,
0x7du, 0xa9u, 0x01u, 0xb9u, 0x6du, 0xcau, 0x3du, 0x42u
};
/* Public key taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */
static const uint8_t pPublicKey[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY] __attribute__((aligned(4))) =
{
0xecu, 0x17u, 0x2bu, 0x93u, 0xadu, 0x5eu, 0x56u, 0x3bu,
0xf4u, 0x93u, 0x2cu, 0x70u, 0xe1u, 0x24u, 0x50u, 0x34u,
0xc3u, 0x54u, 0x67u, 0xefu, 0x2eu, 0xfdu, 0x4du, 0x64u,
0xebu, 0xf8u, 0x19u, 0x68u, 0x34u, 0x67u, 0xe2u, 0xbfu
};
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519ph_example)
{
/******************************************/
/* Set up the environment */
/******************************************/
/* Initialize ELS, Enable the ELS */
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
/* Allocate and initialize session with pkcWA on the beginning of PKC RAM */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG context and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg);
/******************************************/
/* Initialize the private and public keys */
/******************************************/
/* Allocate space for and initialize private key handle for an Ed25519 private key */
uint32_t privKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)];
mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t)&privKeyDesc;
uint32_t pPrivateKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t)pPrivateKeyData,
/* uint32_t keyDataLength */ sizeof(pPrivateKeyData)));
if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize public key handle for an Ed25519 public key */
uint32_t pubKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)];
mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t)&pubKeyDesc;
uint32_t pPublicKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t)pPublicKeyData,
/* uint32_t keyDataLength */ sizeof(pPublicKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */
uint32_t privKeyInputDescriptor[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *)&privKeyInputDescriptor,
/* const uint8_t *pPrivKey */ pPrivateKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Key pair generation for EdDSA on Ed25519ph */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor,
/* mcuxClKey_Handle_t privKey */ privKey,
/* mcuxClKey_Handle_t pubKey */ pubKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/******************************************/
/* Generate the protocol descriptor */
/******************************************/
/* Allocate space for the hash prefix and a protocol descriptor for Ed25519ph. */
uint32_t protocolDescBytes[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(0u))];
mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDesc = (mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *) protocolDescBytes;
/* Generate Ed25519ph protocol descriptor */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genProtocolDescr_result, protocolDescr_token, mcuxClEcc_EdDSA_GenerateProtocolDescriptor(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams */ &mcuxClEcc_EdDSA_DomainParams_Ed25519,
/* mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor */ pProtocolDesc,
/* uint32_t phflag */ MCUXCLECC_EDDSA_PHFLAG_ONE,
/* mcuxCl_InputBuffer_t pContext */ NULL,
/* uint32_t contextLen */ 0u));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) != protocolDescr_token)
|| (MCUXCLECC_STATUS_OK != genProtocolDescr_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519ph signature generation */
/**************************************************************************/
uint32_t signature[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE)] = {0u};
uint32_t signatureSize = 0u;
/* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ pProtocolDesc,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* uint8_t *pSignature */ (uint8_t*)signature,
/* uint32_t *const pSignatureSize */ &signatureSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token)
|| (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize)
|| (MCUXCLECC_STATUS_OK != sign_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519ph signature verification */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ pProtocolDesc,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* const uint8_t *pSignature */ (const uint8_t*)signature,
/* uint32_t signatureSize */ signatureSize
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Verify the signature with the reference signature. */
if(!mcuxClCore_assertEqual((const uint8_t*)signature, pRefSignature, sizeof(pRefSignature)))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/******************************************/
/* Clean up */
/******************************************/
/* Destroy Session and cleanup Session */
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Disable the ELS */
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01302.html b/components/els_pkc/doc/mcxn/html/a01302.html new file mode 100644 index 000000000..0e50638fb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01302.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_EdDSA_Ed25519_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_EdDSA_Ed25519_example.c
+
+
+

Example for the mcuxClEcc component EdDsa related functions

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClRandomModes.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxClExample_ELS_Helper.h>
static const uint8_t digest[] = {
0xC4u, 0x93u, 0xCFu, 0x6Bu, 0xE5u, 0x11u, 0x35u, 0x22u,
0x1Au, 0x3Fu, 0x5Cu, 0x7Bu, 0xCFu, 0xF4u, 0x6Du, 0xC6u,
0x10u, 0x77u, 0x6Eu, 0x2Cu, 0x04u, 0xA3u, 0xB9u, 0x9Du,
0x39u, 0x3Bu, 0x4Bu, 0xEEu, 0xD5u, 0xDDu, 0x88u, 0x86u,
};
#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE,\
MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_INIT_WACPU_SIZE,\
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE, \
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE))))
#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \
MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE, \
MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE))
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
/* Initialize ELS, Enable the ELS */
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
/* Allocate and initialize session with pkcWA on the beginning of PKC RAM */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG context and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg);
/* Prepare buffers for generated data */
uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc;
uint8_t pPrivKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData,
/* uint32_t keyDataLength */ sizeof(pPrivKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc;
uint8_t pPubKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData,
/* uint32_t keyDataLength */ sizeof(pPubKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Key pair generation for EdDSA on Ed25519 */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ &mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor,
/* mcuxClKey_Handle_t privKey */ privKey,
/* mcuxClKey_Handle_t pubKey */ pubKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519 signature generation */
/**************************************************************************/
uint8_t signature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] = {0};
uint32_t signatureSize = 0u;
/* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor,
/* const uint8_t *pIn */ digest,
/* uint32_t inSize */ sizeof(digest),
/* uint8_t *pSignature */ signature,
/* uint32_t *const pSignatureSize */ &signatureSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token)
|| (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize)
|| (MCUXCLECC_STATUS_OK != sign_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/**************************************************************************/
/* Ed25519 signature verification */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor,
/* const uint8_t *pIn */ digest,
/* uint32_t inSize */ sizeof(digest),
/* const uint8_t *pSignature */ signature,
/* uint32_t signatureSize */ signatureSize
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Destroy Session and cleanup Session */
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Disable the ELS */
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01303.html b/components/els_pkc/doc/mcxn/html/a01303.html new file mode 100644 index 000000000..93998f2e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01303.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c
+
+
+

Example for the mcuxClEcc component EdDsa signature verification using the test vectors from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_ELS_Helper.h>
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE
#define MAX_PKCWA_SIZE MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE
/* Input taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pIn[] __attribute__ ((aligned (4))) =
{
0xddu, 0xafu, 0x35u, 0xa1u, 0x93u, 0x61u, 0x7au, 0xbau,
0xccu, 0x41u, 0x73u, 0x49u, 0xaeu, 0x20u, 0x41u, 0x31u,
0x12u, 0xe6u, 0xfau, 0x4eu, 0x89u, 0xa9u, 0x7eu, 0xa2u,
0x0au, 0x9eu, 0xeeu, 0xe6u, 0x4bu, 0x55u, 0xd3u, 0x9au,
0x21u, 0x92u, 0x99u, 0x2au, 0x27u, 0x4fu, 0xc1u, 0xa8u,
0x36u, 0xbau, 0x3cu, 0x23u, 0xa3u, 0xfeu, 0xebu, 0xbdu,
0x45u, 0x4du, 0x44u, 0x23u, 0x64u, 0x3cu, 0xe8u, 0x0eu,
0x2au, 0x9au, 0xc9u, 0x4fu, 0xa5u, 0x4cu, 0xa4u, 0x9fu
};
/* Signature taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) =
{
0xdcu, 0x2au, 0x44u, 0x59u, 0xe7u, 0x36u, 0x96u, 0x33u,
0xa5u, 0x2bu, 0x1bu, 0xf2u, 0x77u, 0x83u, 0x9au, 0x00u,
0x20u, 0x10u, 0x09u, 0xa3u, 0xefu, 0xbfu, 0x3eu, 0xcbu,
0x69u, 0xbeu, 0xa2u, 0x18u, 0x6cu, 0x26u, 0xb5u, 0x89u,
0x09u, 0x35u, 0x1fu, 0xc9u, 0xacu, 0x90u, 0xb3u, 0xecu,
0xfdu, 0xfbu, 0xc7u, 0xc6u, 0x64u, 0x31u, 0xe0u, 0x30u,
0x3du, 0xcau, 0x17u, 0x9cu, 0x13u, 0x8au, 0xc1u, 0x7au,
0xd9u, 0xbeu, 0xf1u, 0x17u, 0x73u, 0x31u, 0xa7u, 0x04u
};
/* Public key taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pPublicKey[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY] __attribute__ ((aligned (4))) =
{
0xecu, 0x17u, 0x2bu, 0x93u, 0xadu, 0x5eu, 0x56u, 0x3bu,
0xf4u, 0x93u, 0x2cu, 0x70u, 0xe1u, 0x24u, 0x50u, 0x34u,
0xc3u, 0x54u, 0x67u, 0xefu, 0x2eu, 0xfdu, 0x4du, 0x64u,
0xebu, 0xf8u, 0x19u, 0x68u, 0x34u, 0x67u, 0xe2u, 0xbfu
};
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_VerifySignature_Ed25519_example)
{
/******************************************/
/* Set up the environment */
/******************************************/
/* Initialize ELS, Enable the ELS */
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
/* Allocate and initialize PKC workarea */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/******************************************/
/* Initialize the public key */
/******************************************/
/* Initialize public key */
uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t pubKeyHandler = (mcuxClKey_Handle_t) &pubKeyDesc;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keyInit_status, keyInit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ pubKeyHandler,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPublicKey,
/* uint32_t keyDataLength */ sizeof(pPublicKey))
);
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != keyInit_token) || (MCUXCLKEY_STATUS_OK != keyInit_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519 signature verification */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t pubKey */ pubKeyHandler,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t* */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor,
/* const uint8_t *pIn */ pIn,
/* uint32_t inSize */ sizeof(pIn),
/* const uint8_t *pSignature */ pSignature,
/* uint32_t signatureSize */ sizeof(pSignature)
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Destroy Session and cleanup Session */
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Disable the ELS */
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01304.html b/components/els_pkc/doc/mcxn/html/a01304.html new file mode 100644 index 000000000..4391467ba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01304.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c
+
+
+

Example for the mcuxClEcc component EdDsa signature generation using the test vectors from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandomModes.h>
#include <mcuxClEcc.h>
#include <mcuxClKey.h>
#include <mcuxClPkc_Types.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClExample_RNG_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_ELS_Helper.h>
#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS
#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \
MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE)
#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \
MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE)
/* Private key input taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pPrivKeyInput[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__ ((aligned (4))) =
{
0x83u, 0x3fu, 0xe6u, 0x24u, 0x09u, 0x23u, 0x7bu, 0x9du,
0x62u, 0xecu, 0x77u, 0x58u, 0x75u, 0x20u, 0x91u, 0x1eu,
0x9au, 0x75u, 0x9cu, 0xecu, 0x1du, 0x19u, 0x75u, 0x5bu,
0x7du, 0xa9u, 0x01u, 0xb9u, 0x6du, 0xcau, 0x3du, 0x42u
};
/* Reference signature taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) =
{
0xDCu, 0x2Au, 0x44u, 0x59u, 0xE7u, 0x36u, 0x96u, 0x33u,
0xA5u, 0x2Bu, 0x1Bu, 0xF2u, 0x77u, 0x83u, 0x9Au, 0x00u,
0x20u, 0x10u, 0x09u, 0xA3u, 0xEFu, 0xBFu, 0x3Eu, 0xCBu,
0x69u, 0xBEu, 0xA2u, 0x18u, 0x6Cu, 0x26u, 0xB5u, 0x89u,
0x09u, 0x35u, 0x1Fu, 0xC9u, 0xACu, 0x90u, 0xB3u, 0xECu,
0xFDu, 0xFBu, 0xC7u, 0xC6u, 0x64u, 0x31u, 0xE0u, 0x30u,
0x3Du, 0xCAu, 0x17u, 0x9Cu, 0x13u, 0x8Au, 0xC1u, 0x7Au,
0xD9u, 0xBEu, 0xF1u, 0x17u, 0x73u, 0x31u, 0xA7u, 0x04u
};
/* Input message taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */
static const uint8_t pMessage[] __attribute__ ((aligned (4))) =
{
0xDDu, 0xAFu, 0x35u, 0xA1u, 0x93u, 0x61u, 0x7Au, 0xBAu,
0xCCu, 0x41u, 0x73u, 0x49u, 0xAEu, 0x20u, 0x41u, 0x31u,
0x12u, 0xE6u, 0xFAu, 0x4Eu, 0x89u, 0xA9u, 0x7Eu, 0xA2u,
0x0Au, 0x9Eu, 0xEEu, 0xE6u, 0x4Bu, 0x55u, 0xD3u, 0x9Au,
0x21u, 0x92u, 0x99u, 0x2Au, 0x27u, 0x4Fu, 0xC1u, 0xA8u,
0x36u, 0xBAu, 0x3Cu, 0x23u, 0xA3u, 0xFEu, 0xEBu, 0xBDu,
0x45u, 0x4Du, 0x44u, 0x23u, 0x64u, 0x3Cu, 0xE8u, 0x0Eu,
0x2Au, 0x9Au, 0xC9u, 0x4Fu, 0xA5u, 0x4Cu, 0xA4u, 0x9Fu
};
MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example)
{
/******************************************/
/* Set up the environment */
/******************************************/
/* Initialize ELS, Enable the ELS */
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Setup one session to be used by all functions called */
mcuxClSession_Descriptor_t session;
/* Allocate and initialize PKC workarea */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE);
/* Initialize the RNG context and Initialize the PRNG */
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg);
/******************************************/
/* Initialize the private and public keys */
/******************************************/
/* Allocate space for and initialize private key handle for an Ed25519 private key */
uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc;
uint8_t pPrivKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData,
/* uint32_t keyDataLength */ sizeof(pPrivKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize public key handle for an Ed25519 public key */
uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE];
mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc;
uint8_t pPubKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init(
/* mcuxClSession_Handle_t session */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub,
/* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData,
/* uint32_t keyDataLength */ sizeof(pPubKeyData)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */
uint8_t privKeyInputDescriptor[MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor,
/* const uint8_t *pPrivKey */ pPrivKeyInput));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Key pair generation for EdDSA on Ed25519 */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair(
/* mcuxClSession_Handle_t pSession */ &session,
/* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor,
/* mcuxClKey_Handle_t privKey */ privKey,
/* mcuxClKey_Handle_t pubKey */ pubKey));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519 signature generation */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */
uint8_t signatureBuffer[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] = {0};
uint32_t signatureSize = 0u;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ privKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* uint8_t *pSignature */ signatureBuffer,
/* uint32_t *const pSignatureSize */ &signatureSize));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token)
|| (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize)
|| (MCUXCLECC_STATUS_OK != sign_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Ed25519 signature verification */
/**************************************************************************/
/* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature(
/* mcuxClSession_Handle_t pSession */ &session,
/* mcuxClKey_Handle_t key */ pubKey,
/* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor,
/* const uint8_t *pIn */ pMessage,
/* uint32_t inSize */ sizeof(pMessage),
/* const uint8_t *pSignature */ (const uint8_t*)signatureBuffer,
/* uint32_t signatureSize */ signatureSize
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Compare the generated signature to the reference. */
mcuxClCore_assertEqual(signatureBuffer, pRefSignature, MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE);
/******************************************/
/* Clean up */
/******************************************/
/* Destroy Session and cleanup Session */
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Disable the ELS */
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01305.html b/components/els_pkc/doc/mcxn/html/a01305.html new file mode 100644 index 000000000..188f185d6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01305.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClKey_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClKey_example.c
+
+
+

Example for the mcuxClKey component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClKey.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClCore_Examples.h>
#include <stdbool.h> // bool type for the example's return code
#include <mcuxClAes.h>
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClExample_Key_Helper.h>
/* Example AES-128 key. */
static uint32_t aes128_key[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS] =
{
0xb97d0b7cu, 0xd0101f81u, 0x7a6c470eu, 0xe0f6920du
};
MCUXCLEXAMPLE_FUNCTION(mcuxClKey_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
mcuxClSession_Descriptor_t session;
//Allocate and initialize session
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, 0u, 0u);
/**************************************************************************/
/* Key setup */
/**************************************************************************/
/* Create and initialize mcuxClKey_Descriptor_t structure. */
uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS];
mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc;
/* Set key properties. */
mcuxClEls_KeyProp_t key_properties;
key_properties.word.value = 0u;
key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128;
key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE;
/* Key buffer for the key in memory. */
uint32_t key_buffer[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS];
//Initializes a key handle, Set key properties and Load key.
if(!mcuxClExample_Key_Init_And_Load(&session,
key,
mcuxClKey_Type_Aes128,
(uint8_t *) aes128_key,
sizeof(aes128_key),
&key_properties,
key_buffer, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/**************************************************************************/
/* The key could now be used for a cryptographic operation. */
/**************************************************************************/
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Flush the key. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(resultFlush, tokenFlush, mcuxClKey_flush(
&session,
key));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != tokenFlush) || (MCUXCLKEY_STATUS_OK != resultFlush))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(&session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01307.html b/components/els_pkc/doc/mcxn/html/a01307.html new file mode 100644 index 000000000..1c7ca148e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01307.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClMac_cmac_oneshot_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClMac_cmac_oneshot_example.c
+
+
+

Example CMAC computation using functions of the mcuxClKey and mcuxClMac component

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01308.html b/components/els_pkc/doc/mcxn/html/a01308.html new file mode 100644 index 000000000..376453c6c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01308.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h> // Code flow protection
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h> // Defines and assertions for examples
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_ELS_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
//Allocate and initialize session
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/* selftest */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(selftestresult, token, mcuxClRandom_selftest(
session,
mcuxClRandomModes_Mode_CtrDrbg_AES256));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_selftest) != token) || (MCUXCLRANDOM_STATUS_OK != selftestresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
/**************************************************************************/
/* Random init */
/**************************************************************************/
/* Initialize the Random session with aes256 mode. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomInitresult, token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)context,
mcuxClRandomModes_Mode_CtrDrbg_AES256));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != token) || (MCUXCLRANDOM_STATUS_OK != randomInitresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate random values. */
/**************************************************************************/
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[4u];
uint8_t drbg_buffer3[5u];
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult1, token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult1))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult2, token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult2))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* reseed */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomReseedresult, token, mcuxClRandom_reseed(
session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != token) || (MCUXCLRANDOM_STATUS_OK != randomReseedresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult3, token, mcuxClRandom_generate(
session,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult3))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomUninitresult, token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != token) || (MCUXCLRANDOM_STATUS_OK != randomUninitresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01309.html b/components/els_pkc/doc/mcxn/html/a01309.html new file mode 100644 index 000000000..8bbe94743 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01309.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_ELS_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_ELS_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h> // Defines and assertions for examples
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_ELS_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Buffers to store the generated random values in. */
uint8_t prng_buffer[10u];
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[4u];
uint8_t drbg_buffer3[5u];
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
//Allocate and initialize session
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, 0u, 0u);
/* We don't need a context for ELS Rng. */
mcuxClRandom_Context_t context = NULL;
/**************************************************************************/
/* Random init */
/**************************************************************************/
/* Initialize the Random session with ELS mode. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomInitresult, token, mcuxClRandom_init(
session,
context,
mcuxClRandomModes_Mode_ELS_Drbg));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != token) || (MCUXCLRANDOM_STATUS_OK != randomInitresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate random values. */
/**************************************************************************/
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult1, token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult1))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult2, token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult2))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult3, token, mcuxClRandom_generate(
session,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult3))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate non-cryptographic random values. */
/**************************************************************************/
/* Initialize non-cryptographic Rng. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomNcInitresult, token, mcuxClRandom_ncInit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != token) || (MCUXCLRANDOM_STATUS_OK != randomNcInitresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomNcGenerateresult, token, mcuxClRandom_ncGenerate(
session,
prng_buffer,
sizeof(prng_buffer)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate) != token) || (MCUXCLRANDOM_STATUS_OK != randomNcGenerateresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomUninitresult, token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != token) || (MCUXCLRANDOM_STATUS_OK != randomUninitresult))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01310.html b/components/els_pkc/doc/mcxn/html/a01310.html new file mode 100644 index 000000000..2746f4a86 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01310.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h> // Defines and assertions for examples
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG3_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/**************************************************************************/
/* DRBG selftest. */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rs_status, selftest_token, mcuxClRandom_selftest(
session,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_selftest) != selftest_token) || (MCUXCLRANDOM_STATUS_OK != rs_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
/**************************************************************************/
/* DRBG initialization */
/**************************************************************************/
/* Initialize an AES-256 CTR_DRBG DRG.3 */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)context,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate several random byte strings and reseed the DRBG in between. */
/**************************************************************************/
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[16u];
uint8_t drbg_buffer3[31u];
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg1_status, generate1_token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate1_token) || (MCUXCLRANDOM_STATUS_OK != rg1_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg2_status, generate2_token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate2_token) || (MCUXCLRANDOM_STATUS_OK != rg2_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Reseed */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rr_status, reseed_token, mcuxClRandom_reseed(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != reseed_token) || (MCUXCLRANDOM_STATUS_OK != rr_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg3_status, generate3_token, mcuxClRandom_generate(
session,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate3_token) || (MCUXCLRANDOM_STATUS_OK != rg3_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01311.html b/components/els_pkc/doc/mcxn/html/a01311.html new file mode 100644 index 000000000..6b3fe4366 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01311.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_Different_Sessions_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_Different_Sessions_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h> // Defines and assertions for examples
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_Different_Sessions_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
mcuxClRandom_Mode_t mcuxClRandomModes_Mode = mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 ;
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[16u];
uint8_t drbg_buffer3[31u];
{ /* session_0 Scope */
mcuxClSession_Descriptor_t sessionDesc_0;
mcuxClSession_Handle_t session_0 = &sessionDesc_0;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session_0, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/**************************************************************************/
/* DRBG selftest. */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rs_status, selftest_token, mcuxClRandom_selftest(
session_0,
mcuxClRandomModes_Mode
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_selftest) != selftest_token) || (MCUXCLRANDOM_STATUS_OK != rs_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* DRBG initialization */
/**************************************************************************/
/* Initialize an AES-128 CTR_DRBG DRG.3 */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session_0,
(mcuxClRandom_Context_t)context,
mcuxClRandomModes_Mode
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate several random byte strings and reseed the DRBG in between. */
/**************************************************************************/
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg1_status, generate1_token, mcuxClRandom_generate(
session_0,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate1_token) || (MCUXCLRANDOM_STATUS_OK != rg1_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session_0))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
{ /* session_1 Scope */
mcuxClSession_Descriptor_t sessionDesc_1;
mcuxClSession_Handle_t session_1 = &sessionDesc_1;
mcuxClRandom_Context_t pContext = (mcuxClRandom_Context_t)&context;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session_1, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/* Set random context that was previously assigned to session_0 */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(setRandom_status, setRandom_token, mcuxClSession_setRandom(
session_1,
mcuxClRandomModes_Mode,
pContext));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_setRandom) != setRandom_token) || (MCUXCLSESSION_STATUS_OK != setRandom_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg2_status, generate2_token, mcuxClRandom_generate(
session_1,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate2_token) || (MCUXCLRANDOM_STATUS_OK != rg2_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Reseed */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rr_status, reseed_token, mcuxClRandom_reseed(session_1));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != reseed_token) || (MCUXCLRANDOM_STATUS_OK != rr_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg3_status, generate3_token, mcuxClRandom_generate(
session_1,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate3_token) || (MCUXCLRANDOM_STATUS_OK != rg3_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session_1));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session_1))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01312.html b/components/els_pkc/doc/mcxn/html/a01312.html new file mode 100644 index 000000000..d726cc798 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01312.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h> // Defines and assertions for examples
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG4_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/**************************************************************************/
/* DRBG selftest. */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rs_status, selftest_token, mcuxClRandom_selftest(
session,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG4
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_selftest) != selftest_token) || (MCUXCLRANDOM_STATUS_OK != rs_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
/**************************************************************************/
/* DRBG initialization */
/**************************************************************************/
/* Initialize an AES-256 CTR_DRBG DRG.4 */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)context,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG4
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate several random byte strings and reseed the DRBG in between to */
/* realize forward secrecy required for a DRG.4. */
/**************************************************************************/
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[16u];
uint8_t drbg_buffer3[31u];
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg1_status, generate1_token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate1_token) || (MCUXCLRANDOM_STATUS_OK != rg1_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg2_status, generate2_token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate2_token) || (MCUXCLRANDOM_STATUS_OK != rg2_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* To achieve the DRG.4 requirements the reseed API needs to be called whenever forward secrecy is required.
* The following only illustrates how such reseeding is done. When reseeding actually needs to be done for forward secrecy depends on the use case.
*/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rr_status, reseed_token, mcuxClRandom_reseed(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != reseed_token) || (MCUXCLRANDOM_STATUS_OK != rr_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg3_status, generate3_token, mcuxClRandom_generate(
session,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate3_token) || (MCUXCLRANDOM_STATUS_OK != rg3_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01313.html b/components/els_pkc/doc/mcxn/html/a01313.html new file mode 100644 index 000000000..db18d8bda --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01313.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/******************************************************************************
* Local and global function declarations
******************************************************************************/
static mcuxClRandom_Status_t RNG_Patch_function(
mcuxClSession_Handle_t session,
mcuxClRandom_Context_t pCustomCtx,
uint8_t *pOut,
uint32_t outLength
)
{
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t sessionCustom = &sessionDesc;
uint32_t cpuWa[MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE / sizeof(uint32_t)];
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(si_status, token, mcuxClSession_init(
/* mcuxClSession_Handle_t session: */ sessionCustom,
/* uint32_t * const cpuWaBuffer: */ cpuWa,
/* uint32_t cpuWaSize: */ MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE,
/* uint32_t * const pkcWaBuffer: */ NULL,
/* uint32_t pkcWaSize: */ 0U
));
/* mcuxClSession_init is a flow-protected function: Check the protection token and the return value */
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_init) != token) || (MCUXCLSESSION_STATUS_OK != si_status))
{
return MCUXCLRANDOM_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* DRBG initialization */
/**************************************************************************/
/* Initialize an AES-256 CTR_DRBG DRG.3 */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
sessionCustom,
(mcuxClRandom_Context_t)pCustomCtx,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLRANDOM_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate random byte strings */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg_status, generate_token, mcuxClRandom_generate(
sessionCustom,
pOut,
outLength
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate_token) || (MCUXCLRANDOM_STATUS_OK != rg_status))
{
return MCUXCLRANDOM_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(sessionCustom));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLRANDOM_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(sessionCustom))
{
return MCUXCLRANDOM_STATUS_ERROR;
}
return MCUXCLRANDOM_STATUS_OK;
}
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE + sizeof(mcuxClSession_Descriptor_t), 0u);
/* Fill mode descriptor with the relevant data */
uint32_t customModeDescBytes[(MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE + sizeof(uint32_t) - 1U)/sizeof(uint32_t)];
mcuxClRandom_ModeDescriptor_t *mcuxClRandomModes_Mode_Custom = (mcuxClRandom_ModeDescriptor_t *) customModeDescBytes;
uint32_t rngContext[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
/**************************************************************************/
/* RANDOM Patch Mode creation, use */
/* mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 as customer generate Algo */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cp_status, cp_token, mcuxClRandomModes_createPatchMode(
mcuxClRandomModes_Mode_Custom,
(mcuxClRandomModes_CustomGenerateAlgorithm_t)RNG_Patch_function,
(mcuxClRandom_Context_t)rngContext,
256U
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_createPatchMode) != cp_token) || (MCUXCLRANDOM_STATUS_OK != cp_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* patch mode initialization */
/**************************************************************************/
uint32_t* rngContextPatched = NULL;
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)rngContextPatched,
mcuxClRandomModes_Mode_Custom
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate several random byte strings */
/**************************************************************************/
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[3u];
uint8_t drbg_buffer2[16u];
uint8_t drbg_buffer3[31u];
/* Generate random values of smaller amount than one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg1_status, generate1_token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate1_token) || (MCUXCLRANDOM_STATUS_OK != rg1_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of multiple of word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg2_status, generate2_token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate2_token) || (MCUXCLRANDOM_STATUS_OK != rg2_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of larger amount than but not multiple of one word size. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg3_status, generate3_token, mcuxClRandom_generate(
session,
drbg_buffer3,
sizeof(drbg_buffer3)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate3_token) || (MCUXCLRANDOM_STATUS_OK != rg3_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01314.html b/components/els_pkc/doc/mcxn/html/a01314.html new file mode 100644 index 000000000..958d451ce --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01314.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
#define OUT_BUFFER_SIZE (MCUXCLRANDOMMODES_RESEED_INTERVAL_PTG3 * 2u)
static const uint32_t entropyInputInit[MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE, sizeof(uint32_t))] =
{
/* Entropy for init (last byte is zero, because initSize is 71 bytes) */
0x2848b943u, 0x9db0857au, 0x24947dbfu, 0xdf5d061bu,
0x3810b90bu, 0xb0c41bdfu, 0xd1ec5f6au, 0x067b147au,
0xcbc57229u, 0xf2862a00u, 0x781140fdu, 0xabfadd8du,
0x42d44243u, 0xd09d2fb3u, 0x0cbaf6a9u, 0x4d318e71u,
0xa5cd8cc0u, 0x00e52e1du
};
static const uint32_t entropyInputReseed[MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE, sizeof(uint32_t))] =
{
/* Entropy for reseed (last byte is zero, because initSize is 55 bytes) */
0x8553d279u, 0x177481a3u, 0xfb7ca01du, 0x848b24fdu,
0x4fc41239u, 0x5c28a84du, 0xe51096cau, 0xefdfd0e6u,
0x5d06582eu, 0x7f11b69eu, 0x0cdd1c59u, 0xa27fe549u,
0x3743696bu, 0x0031870au
};
static const uint32_t entropyInputGenerate[MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE * 2u, sizeof(uint32_t))] =
{
/* Entropy for first reseed at the beginning of the generate call (last byte is not used in first reseed, because reseedsize is 55) */
0xbd98f427u, 0x22de991bu, 0xfb8d02abu, 0xde9141a9u,
0x3b1e32e1u, 0x224c0a9eu, 0x8e41648du, 0x53384037u,
0xd79dd5fau, 0x596b6c68u, 0x76661e1eu, 0x6a51e100u,
0x10f264b1u, 0x1dfef494u,
/* Entropy for second reseed after 32 generated bytes (last byte from first reseed is used, two last bytes from this reseed are not used and set to zero, because reseedsize is 55) */
0xb63075a8u, 0x6aea5058u, 0xd4003ac9u, 0x7576baa3u,
0x801cc5c6u, 0xab22d6a4u, 0xd3dcd613u, 0x05be284du,
0xf22f7fd6u, 0xcd00b43bu, 0xc5adfb33u, 0xf7c67ce0u,
0xcf497dedu, 0x00007ed7u
};
/* Reference output is generated by running this example */
static const uint32_t refOutput[OUT_BUFFER_SIZE / sizeof(uint32_t)] =
{
0xae9f48d6u, 0xe65ac43eu, 0x297df3eau, 0xfcfad27du,
0x1903fe18u, 0xac2906a0u, 0xb8d6aadau, 0xd0d7a8a0u,
0xd30a8957u, 0xcc7620a4u, 0xcc37d610u, 0x2aa97088u,
0x193ac3f7u, 0xa7b78d8du, 0xe6278b5cu, 0xe1ba7253u
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/* Allocate space for a test mode descriptor for an AES-256 CTR_DRBG PTG3. */
uint32_t testModeDescBytes[(MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE + sizeof(uint32_t) - 1U)/sizeof(uint32_t)];
mcuxClRandom_ModeDescriptor_t *pTestModeDesc = (mcuxClRandom_ModeDescriptor_t *) testModeDescBytes;
/**************************************************************************/
/* Test mode creation and for an AES-256 CTR_DRBG PTG3 and preparation */
/* of known entropy input for later DRBG instantiation */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cp_status, cp_token, mcuxClRandomModes_createTestFromNormalMode(
pTestModeDesc,
mcuxClRandomModes_Mode_CtrDrbg_AES256_PTG3,
entropyInputInit
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_createTestFromNormalMode) != cp_token) || (MCUXCLRANDOM_STATUS_OK != cp_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Test mode initialization with known entropy input */
/**************************************************************************/
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)context,
pTestModeDesc
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Test mode reseeding with known entropy input */
/**************************************************************************/
/* Update entropy input to be taken for the upcoming reseed call */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ue_status_1, ue_token_1, mcuxClRandomModes_updateEntropyInput(pTestModeDesc, entropyInputReseed));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_updateEntropyInput) != ue_token_1) || (MCUXCLRANDOM_STATUS_OK != ue_status_1))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rr_status, reseed_token, mcuxClRandom_reseed(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != reseed_token) || (MCUXCLRANDOM_STATUS_OK != rr_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Generate 64 random bytes. This will reseed the DRBG with known entropy */
/* twice, once at the beginning of the generate call and once after 32 */
/* generated bytes */
/**************************************************************************/
/* Update entropy input to be taken for the upcoming reseeding in generate */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ue_status_2, ue_token_2, mcuxClRandomModes_updateEntropyInput(pTestModeDesc, entropyInputGenerate));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_updateEntropyInput) != ue_token_2) || (MCUXCLRANDOM_STATUS_OK != ue_status_2))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random bytes. */
uint8_t outBuffer[OUT_BUFFER_SIZE] = {0u};
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(generate_status, generate_token, mcuxClRandom_generate(
session,
outBuffer,
OUT_BUFFER_SIZE
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate_token) || (MCUXCLRANDOM_STATUS_OK != generate_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Compare the last generated random output to the expected output */
/**************************************************************************/
bool outputIsExpected = mcuxClCore_assertEqual((const uint8_t *) outBuffer, (const uint8_t*) refOutput, OUT_BUFFER_SIZE);
/* Return error if buffers are unequal */
if(!outputIsExpected)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01315.html b/components/els_pkc/doc/mcxn/html/a01315.html new file mode 100644 index 000000000..d70593950 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01315.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c
+
+
+

Example for the mcuxClRandomModes component

+
/*--------------------------------------------------------------------------*/
/* Copyright 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClRandom.h>
#include <mcuxClRandomModes.h>
#include <mcuxClSession.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClExample_Session_Helper.h>
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/* CAVP test vectors */
static const uint32_t entropyInputInit[MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE, sizeof(uint32_t))] =
{
0x5d97e604u, 0x45bf8250u, 0x93fdc193u, 0x240602c2u, 0x667688eeu, 0xc7fec3ceu, 0x37cd6b3du, 0x0f3fba6cu,
0x7e7cc018u, 0x143a77f6u, 0x929e7f5au, 0x2ccdb36cu, 0xb366cc42u, 0x1cec520au, 0x4796757au, 0x85399312u,
0x2db4e8f5u, 0x007f04au
};
/* Last byte is not used, because reseed entropy size is 55 bytes */
static const uint32_t entropyInputReseed[MCUXCLEXAMPLE_CEILING(MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE, sizeof(uint32_t))] =
{
0x20cfe741u, 0xd987b4e5u, 0x7aed81d9u, 0x2d878601u, 0x0b614e77u, 0x5a6c244eu, 0xf4a19d89u, 0x058c53a0u,
0x973bd4c6u, 0x60555726u, 0x11c4a6d3u, 0xa6cb397fu, 0x65ef9ebau, 0x009d46a8u
};
static const uint32_t refOutput[64u] =
{
0x8199928eu, 0x61249be5u, 0x163bc982u, 0x00790f1au, 0xff5ba6b1u, 0x3dab7965u, 0x04ac13bfu, 0x96b79e0eu,
0x7ee1234cu, 0xe6d553ceu, 0x46aedc8au, 0x6fb0fec9u, 0x1f60484du, 0xcedb8334u, 0xaa14c399u, 0x925fa977u
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE, 0u);
/* Allocate space for a test mode descriptor for an AES-256 CTR_DRBG DRG4. */
uint32_t testModeDescBytes[(MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE + sizeof(uint32_t) - 1U)/sizeof(uint32_t)];
mcuxClRandom_ModeDescriptor_t *pTestModeDesc = (mcuxClRandom_ModeDescriptor_t *) testModeDescBytes;
/**************************************************************************/
/* Test mode creation for an AES-256 CTR_DRBG DRG4 and preparation of */
/* known entropy input for later DRBG instantiation */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cp_status, cp_token, mcuxClRandomModes_createTestFromNormalMode(
pTestModeDesc,
mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG4,
entropyInputInit
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_createTestFromNormalMode) != cp_token) || (MCUXCLRANDOM_STATUS_OK != cp_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Test mode initialization with known entropy input */
/**************************************************************************/
uint32_t context[MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS] = {0};
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ri_status, init_token, mcuxClRandom_init(
session,
(mcuxClRandom_Context_t)context,
pTestModeDesc
));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != init_token) || (MCUXCLRANDOM_STATUS_OK != ri_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Reseed the DRBG with a known entropy, and generate two random bytes */
/* strings */
/**************************************************************************/
/* Buffers to store the generated random values in. */
uint8_t drbg_buffer1[64u] = {0u};
uint8_t drbg_buffer2[64u] = {0u};
/* Update entropy input to be taken for the upcoming reseeding */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ue_status, ue_token, mcuxClRandomModes_updateEntropyInput(pTestModeDesc, entropyInputReseed));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_updateEntropyInput) != ue_token) || (MCUXCLRANDOM_STATUS_OK != ue_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Reseed the DRBG with known entropy input */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rr_status, reseed_token, mcuxClRandom_reseed(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed) != reseed_token) || (MCUXCLRANDOM_STATUS_OK != rr_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of 512 bits */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg1_status, generate1_token, mcuxClRandom_generate(
session,
drbg_buffer1,
sizeof(drbg_buffer1)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate1_token) || (MCUXCLRANDOM_STATUS_OK != rg1_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Generate random values of 512 bits */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(rg2_status, generate2_token, mcuxClRandom_generate(
session,
drbg_buffer2,
sizeof(drbg_buffer2)));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != generate2_token) || (MCUXCLRANDOM_STATUS_OK != rg2_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Compare the last generated random output to the expected output */
/**************************************************************************/
bool outputIsExpected = mcuxClCore_assertEqual((const uint8_t*)drbg_buffer2, (const uint8_t*)refOutput, sizeof(drbg_buffer2));
/* Return error if buffers are unequal */
if(!outputIsExpected)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/**************************************************************************/
/* Cleanup */
/**************************************************************************/
/* Random uninit. */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ru_status, uninit_token, mcuxClRandom_uninit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != uninit_token) || (MCUXCLRANDOM_STATUS_OK != ru_status))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01316.html b/components/els_pkc/doc/mcxn/html/a01316.html new file mode 100644 index 000000000..045b8857b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01316.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_verify_pssverify_sha2_256_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRsa_verify_pssverify_sha2_256_example.c
+
+
+

Example of using function mcuxClRsa_verify to perform the RSA signature verification with EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2.

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClSession.h> // Interface to the entire mcuxClSession component
#include <mcuxClExample_Session_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClRandom.h> // Interface to the entire mcuxClRandom component
#include <mcuxClRsa.h> // Interface to the entire mcuxClRsa component
#include <mcuxClToolchain.h> // Memory segment definitions
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/**********************************************************/
/* Example test vectors */
/**********************************************************/
#define RSA_KEY_BIT_LENGTH (2048u)
#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u)
#define RSA_PUBLIC_EXP_BYTE_LENGTH (3u)
#define RSA_MESSAGE_DIGEST_LENGTH (32u)
#define RSA_PSS_SALT_LENGTH (32u)
static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0xb4u, 0xbfu, 0xc5u, 0xdeu, 0x4au, 0x63u, 0xe3u, 0xe2u, 0x58u, 0x1cu, 0x43u, 0x91u, 0xeau, 0x42u, 0x31u, 0x1au,
0x86u, 0xc3u, 0xddu, 0x71u, 0x8au, 0xa2u, 0x56u, 0xd2u, 0xdcu, 0xedu, 0xecu, 0x81u, 0x1cu, 0xebu, 0x6cu, 0xeeu,
0x54u, 0xe1u, 0x39u, 0xb2u, 0x53u, 0x34u, 0x5du, 0x4bu, 0xc5u, 0x37u, 0x0eu, 0xe9u, 0xcfu, 0xe3u, 0x93u, 0x47u,
0xdau, 0x6bu, 0x3du, 0x72u, 0x95u, 0xecu, 0xeeu, 0x13u, 0x9fu, 0xd0u, 0x00u, 0x06u, 0x57u, 0x29u, 0xe3u, 0xd2u,
0xc5u, 0x93u, 0x31u, 0x79u, 0x55u, 0x94u, 0x8cu, 0x3eu, 0xf1u, 0xfdu, 0x82u, 0xf1u, 0x26u, 0xf0u, 0x5bu, 0x28u,
0xc2u, 0x72u, 0x22u, 0x67u, 0x3au, 0x36u, 0x9cu, 0xf5u, 0x1fu, 0xb5u, 0xeeu, 0xc0u, 0x06u, 0x86u, 0xbbu, 0x3cu,
0xcdu, 0xbcu, 0x92u, 0x6fu, 0x82u, 0x08u, 0x7eu, 0xa8u, 0x05u, 0xd4u, 0xecu, 0xccu, 0xbcu, 0xacu, 0x68u, 0x19u,
0x7fu, 0x2du, 0x5cu, 0x2du, 0xe1u, 0x86u, 0xfdu, 0xa1u, 0xf6u, 0xffu, 0x8du, 0xa3u, 0x03u, 0x4fu, 0x71u, 0xe7u,
0x99u, 0x50u, 0xb9u, 0x69u, 0x7cu, 0xa4u, 0x10u, 0xcdu, 0xbeu, 0xbfu, 0x68u, 0xb6u, 0x5bu, 0xacu, 0xfbu, 0x74u,
0xe1u, 0x8du, 0x58u, 0x33u, 0x07u, 0x8eu, 0xcdu, 0x46u, 0x34u, 0x9au, 0xd8u, 0x49u, 0xb5u, 0x58u, 0x4bu, 0xceu,
0x2bu, 0xa2u, 0x0au, 0x77u, 0x46u, 0xdau, 0x8cu, 0xfbu, 0x7eu, 0xd7u, 0xc7u, 0xddu, 0xffu, 0x9eu, 0x10u, 0x43u,
0xb8u, 0xfeu, 0x67u, 0x95u, 0xe4u, 0x0fu, 0x68u, 0x47u, 0xd3u, 0xc2u, 0x11u, 0x83u, 0xbbu, 0x53u, 0x0du, 0xc5u,
0x4du, 0x8eu, 0x75u, 0x53u, 0x86u, 0xe5u, 0x90u, 0xffu, 0x7fu, 0x7au, 0x47u, 0x17u, 0x7au, 0x69u, 0x13u, 0x52u,
0xb6u, 0xa7u, 0xf0u, 0xceu, 0x48u, 0x9eu, 0x83u, 0xecu, 0x43u, 0xfdu, 0x05u, 0xd6u, 0xe4u, 0xbcu, 0xd5u, 0x1au,
0x90u, 0xc2u, 0x4bu, 0xfdu, 0x38u, 0xd3u, 0xf7u, 0x66u, 0x6du, 0x2au, 0xccu, 0x5bu, 0x5fu, 0xc5u, 0x67u, 0x0cu,
0x3eu, 0xe8u, 0xc8u, 0xbeu, 0xb9u, 0x2fu, 0xa4u, 0x8au, 0xb6u, 0x5du, 0x5fu, 0xecu, 0xfeu, 0xf3u, 0x2eu, 0xd7u,
};
static const uint8_t exponent[RSA_PUBLIC_EXP_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x01u, 0x00u, 0x01u
};
static const uint8_t message[RSA_MESSAGE_DIGEST_LENGTH] __attribute__ ((aligned (4))) = {
0x9fu, 0x86u, 0xd0u, 0x81u, 0x88u, 0x4cu, 0x7du, 0x65u, 0x9au, 0x2fu, 0xeau, 0xa0u, 0xc5u, 0x5au, 0xd0u, 0x15u,
0xa3u, 0xbfu, 0x4fu, 0x1bu, 0x2bu, 0x0bu, 0x82u, 0x2cu, 0xd1u, 0x5du, 0x6cu, 0x15u, 0xb0u, 0xf0u, 0x0au, 0x08u,
};
static const uint8_t signature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x5eu, 0xa5u, 0x03u, 0x94u, 0x3cu, 0x28u, 0xbcu, 0x90u, 0x66u, 0xb6u, 0xedu, 0x45u, 0x00u, 0x79u, 0x0fu, 0x85u,
0x23u, 0xf5u, 0x6bu, 0x20u, 0x7du, 0x55u, 0x6fu, 0x0fu, 0x28u, 0x5fu, 0x2du, 0xdbu, 0x85u, 0xe7u, 0x8eu, 0x7bu,
0x42u, 0xbau, 0x10u, 0x79u, 0xc0u, 0x16u, 0xd2u, 0x01u, 0x21u, 0x6bu, 0xc6u, 0x4cu, 0x57u, 0x0au, 0x4eu, 0x85u,
0x2au, 0x89u, 0xdeu, 0x4bu, 0xccu, 0xb3u, 0xa0u, 0xdcu, 0x35u, 0xe9u, 0xf7u, 0xfeu, 0xe8u, 0xe9u, 0x2cu, 0xfeu,
0x20u, 0x96u, 0x04u, 0x5fu, 0x46u, 0x09u, 0xb5u, 0xb7u, 0x1eu, 0xf9u, 0xcdu, 0x73u, 0x05u, 0xf8u, 0xe8u, 0xdeu,
0x2cu, 0x17u, 0x50u, 0xd1u, 0xd5u, 0x66u, 0x4fu, 0xa2u, 0x9au, 0x26u, 0x28u, 0xd9u, 0x66u, 0x7fu, 0x87u, 0x80u,
0x69u, 0x34u, 0x3du, 0xd3u, 0xdbu, 0x06u, 0xe5u, 0x7cu, 0x3cu, 0xf3u, 0x4au, 0x3fu, 0xb7u, 0x97u, 0x90u, 0x4fu,
0x72u, 0x92u, 0x54u, 0xa0u, 0x9cu, 0x2fu, 0x29u, 0x94u, 0x65u, 0xa0u, 0xd6u, 0xafu, 0x9bu, 0xcau, 0xa6u, 0x0fu,
0x90u, 0x45u, 0x79u, 0x36u, 0x00u, 0xeau, 0x08u, 0xb2u, 0x0du, 0x8cu, 0xe7u, 0xefu, 0x08u, 0x95u, 0x61u, 0xf3u,
0x79u, 0x54u, 0xd7u, 0xb6u, 0x22u, 0x01u, 0x46u, 0x41u, 0xb0u, 0xadu, 0xf1u, 0x03u, 0x0cu, 0x00u, 0xdcu, 0xb9u,
0x33u, 0x3du, 0x1cu, 0xe1u, 0x16u, 0xd6u, 0xd9u, 0x4au, 0x16u, 0x9cu, 0x51u, 0x12u, 0x22u, 0x54u, 0x15u, 0xe0u,
0xefu, 0x2au, 0xb9u, 0xeeu, 0x3cu, 0x2cu, 0xe8u, 0x5eu, 0xaau, 0x58u, 0x26u, 0x0cu, 0xeeu, 0x4bu, 0x34u, 0x94u,
0x53u, 0xc9u, 0x97u, 0x50u, 0xceu, 0xb4u, 0xd1u, 0xceu, 0x38u, 0xbfu, 0xe4u, 0x5cu, 0x5du, 0x24u, 0x00u, 0xceu,
0xfau, 0x8au, 0xbau, 0x42u, 0xeau, 0xa8u, 0x4fu, 0x7du, 0xa2u, 0x37u, 0x17u, 0x7eu, 0x62u, 0xe7u, 0x60u, 0x2cu,
0x01u, 0x97u, 0x68u, 0x26u, 0xb6u, 0xf0u, 0x8bu, 0xe6u, 0x4eu, 0xa6u, 0xb2u, 0x4fu, 0x0eu, 0x11u, 0x3cu, 0x93u,
0x5eu, 0xcdu, 0x35u, 0x70u, 0x82u, 0x63u, 0xadu, 0x5fu, 0x3cu, 0x6au, 0x51u, 0x9fu, 0x5eu, 0xd5u, 0xbau, 0xf6u,
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_pssverify_sha2_256_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Create session handle to be used by verify function */
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session,
MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE,
MCUXCLRSA_VERIFY_2048_WAPKC_SIZE);
/* Initialize the PRNG */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Create key struct of type MCUXCLRSA_KEY_PUBLIC */
const mcuxClRsa_KeyEntry_t Mod1 = {
.pKeyEntryData = (uint8_t *)modulus,
.keyEntryLength = RSA_KEY_BYTE_LENGTH };
const mcuxClRsa_KeyEntry_t Exp1 = {
.pKeyEntryData = (uint8_t *)exponent,
.keyEntryLength = RSA_PUBLIC_EXP_BYTE_LENGTH };
const mcuxClRsa_Key public_key = {
.keytype = MCUXCLRSA_KEY_PUBLIC,
.pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1,
.pMod2 = NULL,
.pQInv = NULL,
.pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1,
.pExp2 = NULL,
.pExp3 = NULL };
/**************************************************************************/
/* RSA verification call */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClRsa_verify(
/* mcuxClSession_Handle_t pSession: */ session,
/* const mcuxClRsa_Key * const pKey: */ &public_key,
/* mcuxCl_InputBuffer_t pMessageOrDigest: */ (uint8_t *)message,
/* const uint32_t messageLength: */ 0u,
/* mcuxCl_Buffer_t pSignature: */ (uint8_t *)signature,
/* const mcuxClRsa_SignVerifyMode pVerifyMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Verify_Pss_Sha2_256,
/* const uint32_t saltLength: */ RSA_PSS_SALT_LENGTH,
/* uint32_t options: */ MCUXCLRSA_OPTION_MESSAGE_DIGEST,
/* mcuxCl_Buffer_t pOutput: */ NULL));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_verify) != verify_token) || (MCUXCLRSA_STATUS_VERIFY_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Session clean-up */
/**************************************************************************/
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01317.html b/components/els_pkc/doc/mcxn/html/a01317.html new file mode 100644 index 000000000..d0de45e2c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01317.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_sign_pss_sha2_256_example.c + + + + + + + + + + + + + + + + +
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MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ + + +
+
+ +
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+ +
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+ +
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+
mcuxClRsa_sign_pss_sha2_256_example.c
+
+
+

Example of using function mcuxClRsa_sign to perform the RSA signature generation with EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2.

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClSession.h> // Interface to the entire mcuxClSession component
#include <mcuxClExample_Session_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClRandom.h> // Interface to the entire mcuxClRandom component
#include <mcuxClRsa.h> // Interface to the entire mcuxClRsa component
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/**********************************************************/
/* Example test vectors */
/**********************************************************/
#define RSA_KEY_BIT_LENGTH (2048u)
#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u)
#define RSA_MESSAGE_DIGEST_LENGTH (32u)
#define RSA_PSS_SALT_LENGTH (0u)
static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0xd3U, 0x24U, 0x96U, 0xe6U, 0x2dU, 0x16U, 0x34U, 0x6eU, 0x06U, 0xe7U, 0xa3U, 0x1cU, 0x12U, 0x0aU, 0x21U, 0xb5U,
0x45U, 0x32U, 0x32U, 0x35U, 0xeeU, 0x1dU, 0x90U, 0x72U, 0x1dU, 0xceU, 0xaaU, 0xd4U, 0x6dU, 0xc4U, 0xceU, 0xbdU,
0x80U, 0xc1U, 0x34U, 0x5aU, 0xffU, 0x95U, 0xb1U, 0xddU, 0xf8U, 0x71U, 0xebU, 0xb7U, 0xf2U, 0x0fU, 0xedU, 0xb6U,
0xe4U, 0x2eU, 0x67U, 0xa0U, 0xccU, 0x59U, 0xb3U, 0x9fU, 0xfdU, 0x31U, 0xe9U, 0x83U, 0x42U, 0xf4U, 0x0aU, 0xd9U,
0xafU, 0xf9U, 0x3cU, 0x3cU, 0x51U, 0xcfU, 0x5fU, 0x3cU, 0x8aU, 0xd0U, 0x64U, 0xb8U, 0x33U, 0xf9U, 0xacU, 0x34U,
0x22U, 0x9aU, 0x3eU, 0xd3U, 0xddU, 0x29U, 0x41U, 0xbeU, 0x12U, 0x5bU, 0xc5U, 0xa2U, 0x0cU, 0xb6U, 0xd2U, 0x31U,
0xb6U, 0xd1U, 0x84U, 0x7eU, 0xc4U, 0xfeU, 0xaeU, 0x2bU, 0x88U, 0x46U, 0xcfU, 0x00U, 0xc4U, 0xc6U, 0xe7U, 0x5aU,
0x51U, 0x32U, 0x65U, 0x7aU, 0x68U, 0xecU, 0x04U, 0x38U, 0x36U, 0x46U, 0x34U, 0xeaU, 0xf8U, 0x27U, 0xf9U, 0xbbU,
0x51U, 0x6cU, 0x93U, 0x27U, 0x48U, 0x1dU, 0x58U, 0xb8U, 0xffU, 0x1eU, 0xa4U, 0xc0U, 0x1fU, 0xa1U, 0xa2U, 0x57U,
0xa9U, 0x4eU, 0xa6U, 0xd4U, 0x72U, 0x60U, 0x3bU, 0x3fU, 0xb3U, 0x24U, 0x53U, 0x22U, 0x88U, 0xeaU, 0x3aU, 0x97U,
0x43U, 0x53U, 0x59U, 0x15U, 0x33U, 0xa0U, 0xebU, 0xbeU, 0xf2U, 0x9dU, 0xf4U, 0xf8U, 0xbcU, 0x4dU, 0xdbU, 0xf8U,
0x8eU, 0x47U, 0x1fU, 0x1dU, 0xa5U, 0x00U, 0xb8U, 0xf5U, 0x7bU, 0xb8U, 0xc3U, 0x7cU, 0xa5U, 0xeaU, 0x17U, 0x7cU,
0x4eU, 0x8aU, 0x39U, 0x06U, 0xb7U, 0xc1U, 0x42U, 0xf7U, 0x78U, 0x8cU, 0x45U, 0xeaU, 0xd0U, 0xc9U, 0xbcU, 0x36U,
0x92U, 0x48U, 0x3aU, 0xd8U, 0x13U, 0x61U, 0x11U, 0x45U, 0xb4U, 0x1fU, 0x9cU, 0x01U, 0x2eU, 0xf2U, 0x87U, 0xbeU,
0x8bU, 0xbfU, 0x93U, 0x19U, 0xcfU, 0x4bU, 0x91U, 0x84U, 0xdcU, 0x8eU, 0xffU, 0x83U, 0x58U, 0x9bU, 0xe9U, 0x0cU,
0x54U, 0x81U, 0x14U, 0xacU, 0xfaU, 0x5aU, 0xbfU, 0x79U, 0x54U, 0xbfU, 0x9fU, 0x7aU, 0xe5U, 0xb4U, 0x38U, 0xb5U
};
static const uint8_t exponent[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x15U, 0x5fU, 0xe6U, 0x60U, 0xcdU, 0xdeU, 0xaaU, 0x17U, 0x1bU, 0x5eU, 0xd6U, 0xbdU, 0xd0U, 0x3bU, 0xb3U, 0x56U,
0xe0U, 0xf6U, 0xe8U, 0x6bU, 0x5aU, 0x3cU, 0x26U, 0xf3U, 0xceU, 0x7dU, 0xaeU, 0x00U, 0x8cU, 0x4eU, 0x38U, 0xa9U,
0xa9U, 0x7fU, 0xa5U, 0x97U, 0xb2U, 0xb9U, 0x0aU, 0x45U, 0x10U, 0xd2U, 0x23U, 0x8dU, 0x3fU, 0x15U, 0x8aU, 0xb8U,
0x91U, 0x97U, 0xfbU, 0x08U, 0xa5U, 0xb7U, 0x4cU, 0xfeU, 0x5cU, 0xc8U, 0xf1U, 0x3dU, 0x47U, 0x09U, 0x62U, 0x91U,
0xd0U, 0x05U, 0x38U, 0xaaU, 0x58U, 0x93U, 0xd8U, 0x2dU, 0xceU, 0x55U, 0xb3U, 0x64U, 0x8cU, 0x6aU, 0x71U, 0x9aU,
0xe3U, 0x87U, 0xdeU, 0xe5U, 0x5eU, 0xc5U, 0xbeU, 0xf0U, 0x89U, 0x76U, 0x3dU, 0xe7U, 0x1eU, 0x47U, 0x61U, 0xb7U,
0x03U, 0xadU, 0x69U, 0x2eU, 0xd6U, 0x2dU, 0x7cU, 0x1fU, 0x4fU, 0x0fU, 0xf0U, 0x03U, 0xc1U, 0x67U, 0xebU, 0x62U,
0xd2U, 0xc6U, 0x79U, 0xccU, 0x6fU, 0x13U, 0xb9U, 0x87U, 0xa1U, 0x42U, 0xf1U, 0x37U, 0x7aU, 0x40U, 0xbdU, 0xc0U,
0xa0U, 0x36U, 0x60U, 0x72U, 0x94U, 0x40U, 0x14U, 0x63U, 0xa3U, 0x0eU, 0x82U, 0x91U, 0x2bU, 0x42U, 0x8aU, 0x1dU,
0x3fU, 0x80U, 0xb5U, 0xd0U, 0xd3U, 0x3eU, 0xa8U, 0x4eU, 0x8bU, 0xb6U, 0x4cU, 0x36U, 0x22U, 0xb9U, 0xbeU, 0xe3U,
0x56U, 0xf1U, 0x2cU, 0x6aU, 0x19U, 0x0eU, 0x55U, 0x7bU, 0xbfU, 0x25U, 0xe1U, 0x10U, 0x80U, 0x7bU, 0x85U, 0xcaU,
0xd5U, 0x1bU, 0x39U, 0x87U, 0x57U, 0x08U, 0x06U, 0xbeU, 0x81U, 0xf3U, 0x71U, 0x3fU, 0x5dU, 0x17U, 0x40U, 0x74U,
0x99U, 0xa5U, 0xdeU, 0xdaU, 0xc0U, 0xf3U, 0xe3U, 0xbcU, 0x79U, 0x96U, 0x35U, 0x95U, 0xf8U, 0xe0U, 0xcfU, 0x01U,
0x29U, 0x1dU, 0xc1U, 0x02U, 0x09U, 0xc0U, 0x6eU, 0xb6U, 0x0eU, 0x2eU, 0x9cU, 0x47U, 0xecU, 0x91U, 0x42U, 0xedU,
0xa5U, 0xf3U, 0xb7U, 0x0aU, 0xc6U, 0x7fU, 0x72U, 0xbfU, 0x52U, 0xb3U, 0x31U, 0x37U, 0xd1U, 0x49U, 0xb6U, 0xf6U,
0x06U, 0xe4U, 0x59U, 0x61U, 0x7dU, 0xaaU, 0x8eU, 0x10U, 0x18U, 0xa8U, 0x14U, 0x1dU, 0x89U, 0x4eU, 0xcaU, 0xffU
};
static const uint8_t message[RSA_MESSAGE_DIGEST_LENGTH] __attribute__ ((aligned (4))) = {
0xf4U, 0x45U, 0x80U, 0x1eU, 0x0cU, 0xb8U, 0x99U, 0x26U, 0x2cU, 0x9bU, 0x9eU, 0x21U, 0x98U, 0x36U, 0x88U, 0x0dU,
0x73U, 0xcaU, 0x2dU, 0x1bU, 0x0bU, 0x9cU, 0x15U, 0xfbU, 0x95U, 0x9cU, 0x90U, 0xebU, 0x12U, 0x12U, 0x34U, 0xe3U
};
static const uint8_t referenceSignature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x89U, 0x01U, 0x41U, 0x9fU, 0x26U, 0x14U, 0xc9U, 0x42U, 0xc9U, 0xeeU, 0x5eU, 0xfbU, 0xdfU, 0xbaU, 0x0cU, 0xcaU,
0x70U, 0x6bU, 0x3aU, 0x4eU, 0xd1U, 0xa8U, 0x5fU, 0x69U, 0x28U, 0xb7U, 0x60U, 0xffU, 0x1bU, 0xbaU, 0xb0U, 0xe7U,
0xb0U, 0x4cU, 0xbdU, 0xe6U, 0xb5U, 0x9fU, 0xc8U, 0x44U, 0x4fU, 0x4eU, 0xd1U, 0x0bU, 0xceU, 0xbeU, 0x30U, 0x75U,
0x47U, 0xb4U, 0xc6U, 0x34U, 0x35U, 0xd9U, 0xaaU, 0x4fU, 0x7dU, 0xf9U, 0x37U, 0x97U, 0xf6U, 0x27U, 0x0aU, 0x20U,
0x23U, 0x8aU, 0x42U, 0x36U, 0xb1U, 0x6fU, 0x47U, 0x72U, 0xb9U, 0x02U, 0x2fU, 0xadU, 0x11U, 0x9cU, 0x54U, 0x38U,
0xd7U, 0x08U, 0x17U, 0x45U, 0xe2U, 0xa7U, 0xe3U, 0x2bU, 0x55U, 0x63U, 0x0eU, 0x37U, 0x49U, 0xabU, 0x51U, 0x05U,
0x3eU, 0x1cU, 0x9cU, 0x77U, 0xf6U, 0x77U, 0xddU, 0x12U, 0x92U, 0x96U, 0x19U, 0xe7U, 0x80U, 0x22U, 0xbdU, 0xfdU,
0xcbU, 0x4bU, 0x8dU, 0x4eU, 0x47U, 0xbcU, 0x80U, 0xacU, 0x91U, 0xcfU, 0xe7U, 0x5fU, 0x11U, 0x91U, 0xa7U, 0x2dU,
0xfdU, 0x61U, 0x88U, 0xfdU, 0x28U, 0x9cU, 0xd5U, 0xb3U, 0x44U, 0xd4U, 0x33U, 0x4fU, 0xc1U, 0x5bU, 0xa7U, 0x64U,
0x1dU, 0xf6U, 0x9fU, 0xc5U, 0x73U, 0xa7U, 0x2fU, 0x08U, 0x46U, 0xd5U, 0x32U, 0x7eU, 0x24U, 0x03U, 0x17U, 0xc6U,
0x8eU, 0x02U, 0xbfU, 0x5dU, 0xe0U, 0x8cU, 0x40U, 0xbeU, 0x7eU, 0x2cU, 0xc1U, 0xa4U, 0x04U, 0xc0U, 0x6bU, 0xbfU,
0x56U, 0xf3U, 0x09U, 0x5aU, 0x8cU, 0x34U, 0x8fU, 0x7bU, 0x50U, 0xabU, 0x65U, 0x48U, 0x02U, 0x11U, 0x02U, 0x4bU,
0xacU, 0x3cU, 0xa5U, 0x93U, 0xa5U, 0xd4U, 0x4aU, 0x7dU, 0xa7U, 0xb8U, 0x69U, 0x6eU, 0xb6U, 0xe2U, 0xa1U, 0xd2U,
0xfcU, 0xa1U, 0x89U, 0x44U, 0x50U, 0xc9U, 0x01U, 0x5eU, 0xbdU, 0xafU, 0x25U, 0xadU, 0xd0U, 0x0cU, 0xb4U, 0x4fU,
0xb3U, 0x99U, 0x44U, 0x28U, 0xb2U, 0x45U, 0x1cU, 0x92U, 0x6bU, 0xbfU, 0xfcU, 0xfdU, 0x72U, 0xecU, 0x44U, 0xdaU,
0xaaU, 0xdaU, 0x65U, 0x19U, 0xc3U, 0x41U, 0x46U, 0xb6U, 0x01U, 0x67U, 0xdeU, 0x98U, 0xd8U, 0x1bU, 0x15U, 0x94U
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_pss_sha2_256_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Create session handle to be used by mcuxClRsa_sign */
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session,
MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE,
MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE);
/* Initialize the PRNG */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Create key struct of type MCUXCLRSA_KEY_PRIVATEPLAIN */
const mcuxClRsa_KeyEntry_t Mod1 = {
.pKeyEntryData = (uint8_t *)modulus,
.keyEntryLength = RSA_KEY_BYTE_LENGTH };
const mcuxClRsa_KeyEntry_t Exp1 = {
.pKeyEntryData = (uint8_t *)exponent,
.keyEntryLength = sizeof(exponent) };
const mcuxClRsa_Key private_key = {
.keytype = MCUXCLRSA_KEY_PRIVATEPLAIN,
.pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1,
.pMod2 = NULL,
.pQInv = NULL,
.pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1,
.pExp2 = NULL,
.pExp3 = NULL };
/* Prepare buffer to store the result */
uint8_t signature[RSA_KEY_BYTE_LENGTH];
/**************************************************************************/
/* RSA signature generation call */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClRsa_sign(
/* mcuxClSession_Handle_t pSession: */ session,
/* const mcuxClRsa_Key * const pKey: */ &private_key,
/* mcuxCl_InputBuffer_t pMessageOrDigest: */ message,
/* const uint32_t messageLength: */ RSA_MESSAGE_DIGEST_LENGTH,
/* const mcuxClRsa_SignVerifyMode pPaddingMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Sign_Pss_Sha2_256,
/* const uint32_t saltLength: */ RSA_PSS_SALT_LENGTH,
/* uint32_t options: */ MCUXCLRSA_OPTION_MESSAGE_DIGEST,
/* mcuxCl_Buffer_t pSignature: */ signature));
if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_sign) != sign_token || MCUXCLRSA_STATUS_SIGN_OK != sign_result)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Verification of the result */
/**************************************************************************/
for(size_t i = 0U; i < RSA_KEY_BYTE_LENGTH; i++)
{
if(referenceSignature[i] != signature[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
/**************************************************************************/
/* Session clean-up */
/**************************************************************************/
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01318.html b/components/els_pkc/doc/mcxn/html/a01318.html new file mode 100644 index 000000000..bafdcefda --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01318.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_verify_NoVerify_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRsa_verify_NoVerify_example.c
+
+
+

Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 (public exponentiation and NO padding verification) according to PKCS #1 v2.2.

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClSession.h> // Interface to the entire mcuxClSession component
#include <mcuxClExample_Session_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClRandom.h> // Interface to the entire mcuxClRandom component
#include <mcuxClRsa.h> // Interface to the entire mcuxClRsa component
#include <mcuxClToolchain.h> // Memory segment definitions
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/**********************************************************/
/* Example test vectors */
/**********************************************************/
#define RSA_KEY_BIT_LENGTH (2048u)
#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u)
static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0xbau,0xd4u,0x7au,0x84u,0xc1u,0x78u,0x2eu,0x4du,0xbdu,0xd9u,0x13u,0xf2u,0xa2u,0x61u,0xfcu,0x8bu,
0x65u,0x83u,0x84u,0x12u,0xc6u,0xe4u,0x5au,0x20u,0x68u,0xedu,0x6du,0x7fu,0x16u,0xe9u,0xcdu,0xf4u,
0x46u,0x2bu,0x39u,0x11u,0x95u,0x63u,0xcau,0xfbu,0x74u,0xb9u,0xcbu,0xf2u,0x5cu,0xfdu,0x54u,0x4bu,
0xdau,0xe2u,0x3bu,0xffu,0x0eu,0xbeu,0x7fu,0x64u,0x41u,0x04u,0x2bu,0x7eu,0x10u,0x9bu,0x9au,0x8au,
0xfau,0xa0u,0x56u,0x82u,0x1eu,0xf8u,0xefu,0xaau,0xb2u,0x19u,0xd2u,0x1du,0x67u,0x63u,0x48u,0x47u,
0x85u,0x62u,0x2du,0x91u,0x8du,0x39u,0x5au,0x2au,0x31u,0xf2u,0xecu,0xe8u,0x38u,0x5au,0x81u,0x31u,
0xe5u,0xffu,0x14u,0x33u,0x14u,0xa8u,0x2eu,0x21u,0xafu,0xd7u,0x13u,0xbau,0xe8u,0x17u,0xccu,0x0eu,
0xe3u,0x51u,0x4du,0x48u,0x39u,0x00u,0x7cu,0xcbu,0x55u,0xd6u,0x84u,0x09u,0xc9u,0x7au,0x18u,0xabu,
0x62u,0xfau,0x6fu,0x9fu,0x89u,0xb3u,0xf9u,0x4au,0x27u,0x77u,0xc4u,0x7du,0x61u,0x36u,0x77u,0x5au,
0x56u,0xa9u,0xa0u,0x12u,0x7fu,0x68u,0x24u,0x70u,0xbeu,0xf8u,0x31u,0xfbu,0xecu,0x4bu,0xcdu,0x7bu,
0x50u,0x95u,0xa7u,0x82u,0x3fu,0xd7u,0x07u,0x45u,0xd3u,0x7du,0x1bu,0xf7u,0x2bu,0x63u,0xc4u,0xb1u,
0xb4u,0xa3u,0xd0u,0x58u,0x1eu,0x74u,0xbfu,0x9au,0xdeu,0x93u,0xccu,0x46u,0x14u,0x86u,0x17u,0x55u,
0x39u,0x31u,0xa7u,0x9du,0x92u,0xe9u,0xe4u,0x88u,0xefu,0x47u,0x22u,0x3eu,0xe6u,0xf6u,0xc0u,0x61u,
0x88u,0x4bu,0x13u,0xc9u,0x06u,0x5bu,0x59u,0x11u,0x39u,0xdeu,0x13u,0xc1u,0xeau,0x29u,0x27u,0x49u,
0x1eu,0xd0u,0x0fu,0xb7u,0x93u,0xcdu,0x68u,0xf4u,0x63u,0xf5u,0xf6u,0x4bu,0xaau,0x53u,0x91u,0x6bu,
0x46u,0xc8u,0x18u,0xabu,0x99u,0x70u,0x65u,0x57u,0xa1u,0xc2u,0xd5u,0x0du,0x23u,0x25u,0x77u,0xd1u
};
static const uint8_t exponent[3] __attribute__ ((aligned (4))) = {
0x01u, 0x00u, 0x01u
};
static const uint8_t signature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x7eu,0x65u,0xb9u,0x98u,0xa0u,0x5fu,0x62u,0x6bu,0x02u,0x8cu,0x75u,0xdcu,0x3fu,0xbfu,0x98u,0x96u,
0x3du,0xceu,0x66u,0xd0u,0xf4u,0xc3u,0xaeu,0x42u,0x37u,0xcfu,0xf3u,0x04u,0xd8u,0x4du,0x88u,0x36u,
0xcbu,0x6bu,0xadu,0x9au,0xc8u,0x6fu,0x9du,0x1bu,0x8au,0x28u,0xddu,0x70u,0x40u,0x47u,0x88u,0xb8u,
0x69u,0xd2u,0x42u,0x9fu,0x1eu,0xc0u,0x66u,0x3eu,0x51u,0xb7u,0x53u,0xf7u,0x45u,0x1cu,0x6bu,0x46u,
0x45u,0xd9u,0x91u,0x26u,0xe4u,0x57u,0xc1u,0xdau,0xc4u,0x95u,0x51u,0xd8u,0x6au,0x8au,0x97u,0x4au,
0x31u,0x31u,0xe9u,0xb3u,0x71u,0xd5u,0xc2u,0x14u,0xccu,0x9fu,0xf2u,0x40u,0xc2u,0x99u,0xbdu,0x0eu,
0x62u,0xdbu,0xc7u,0xa9u,0xa2u,0xdau,0xd9u,0xfau,0x54u,0x04u,0xadu,0xb0u,0x06u,0x32u,0xd3u,0x63u,
0x32u,0xd5u,0xbeu,0x61u,0x06u,0xe9u,0xe6u,0xecu,0x81u,0xcau,0xc4u,0x5cu,0xd3u,0x39u,0xccu,0x87u,
0xabu,0xbeu,0x7fu,0x89u,0x43u,0x08u,0x00u,0xe1u,0x6eu,0x03u,0x2au,0x66u,0x21u,0x0bu,0x25u,0xe9u,
0x26u,0xedu,0xa2u,0x43u,0xd9u,0xf0u,0x99u,0x55u,0x49u,0x6du,0xdbu,0xc7u,0x7eu,0xf7u,0x4fu,0x17u,
0xfeu,0xe4u,0x1cu,0x44u,0x35u,0xe7u,0x8bu,0x46u,0x96u,0x5bu,0x71u,0x3du,0x72u,0xceu,0x8au,0x31u,
0xafu,0x64u,0x15u,0x38u,0xadu,0xd3u,0x87u,0xfeu,0xdfu,0xd8u,0x8bu,0xb2u,0x2au,0x42u,0xebu,0x3bu,
0xdau,0x40u,0xf7u,0x2eu,0xcau,0xd9u,0x41u,0xdbu,0xffu,0xddu,0x47u,0xb3u,0xe7u,0x77u,0x37u,0xdau,
0x74u,0x15u,0x53u,0xa4u,0x5bu,0x63u,0x0du,0x07u,0x0bu,0xccu,0x52u,0x05u,0x80u,0x4bu,0xf8u,0x0eu,
0xe2u,0xd5u,0x16u,0x12u,0x87u,0x5du,0xbcu,0x47u,0x96u,0x96u,0x00u,0x52u,0xf1u,0x68u,0x7eu,0x00u,
0x74u,0x00u,0x7eu,0x6au,0x33u,0xabu,0x8bu,0x20u,0x85u,0xc0u,0x33u,0xf9u,0x89u,0x2bu,0x6fu,0x74u
};
static const uint8_t reference_result[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x70u,0x99u,0x2cu,0x9du,0x95u,0xa4u,0x90u,0x8du,0x2au,0x94u,0xb3u,0xabu,0x9fu,0xa1u,0xcdu,0x64u,
0x3fu,0x12u,0x0eu,0x32u,0x6fu,0x9du,0x78u,0x08u,0xafu,0x50u,0xcau,0xc4u,0x2cu,0x4bu,0x0bu,0x4eu,
0xebu,0x7fu,0x0du,0x4du,0xf3u,0x03u,0xa5u,0x68u,0xfbu,0xfbu,0x82u,0xb0u,0xf5u,0x83u,0x00u,0xd2u,
0x53u,0x57u,0x64u,0x57u,0x21u,0xbbu,0x71u,0x86u,0x1cu,0xafu,0x81u,0xb2u,0x7au,0x56u,0x08u,0x2cu,
0x80u,0xa1u,0x46u,0x49u,0x9fu,0xb4u,0xeau,0xb5u,0xbdu,0xe4u,0x49u,0x3fu,0x5du,0x00u,0xf1u,0xa4u,
0x37u,0xbbu,0xc3u,0x60u,0xdfu,0xcdu,0x80u,0x56u,0xfeu,0x6bu,0xe1u,0x0eu,0x60u,0x8au,0xdbu,0x30u,
0xb6u,0xc2u,0xf7u,0x65u,0x24u,0x28u,0xb8u,0xd3u,0x2du,0x36u,0x29u,0x45u,0x98u,0x2au,0x46u,0x58u,
0x5du,0x21u,0x02u,0xefu,0x79u,0x95u,0xa8u,0xbau,0x6eu,0x8au,0xd8u,0xfdu,0x16u,0xbdu,0x7au,0xe8u,
0xf5u,0x3cu,0x3du,0x7fu,0xcfu,0xbau,0x29u,0x0bu,0x57u,0xceu,0x7fu,0x8fu,0x09u,0xc8u,0x28u,0xd6u,
0xf2u,0xd3u,0xceu,0x56u,0xf1u,0x31u,0xbdu,0x94u,0x61u,0xe5u,0x66u,0x7eu,0x5bu,0x73u,0xedu,0xacu,
0x77u,0xf5u,0x04u,0xdau,0xc4u,0xf2u,0x02u,0xa9u,0x57u,0x0eu,0xb4u,0x51u,0x5bu,0x2bu,0xf5u,0x16u,
0x40u,0x7du,0xb8u,0x31u,0x51u,0x8du,0xb8u,0xa2u,0x08u,0x3eu,0xc7u,0x01u,0xe8u,0xfdu,0x38u,0x7cu,
0x43u,0x0bu,0xb1u,0xa7u,0x2du,0xecu,0xa5u,0xb4u,0x9du,0x42u,0x9cu,0xf9u,0xdeu,0xb0u,0x9cu,0xc4u,
0x51u,0x8du,0xc5u,0xf5u,0x7cu,0x08u,0x9au,0xa2u,0xd3u,0x42u,0x0eu,0x56u,0x7eu,0x73u,0x21u,0x02u,
0xc2u,0xc9u,0x2bu,0x88u,0xa0u,0x7cu,0x69u,0xd7u,0x09u,0x17u,0x14u,0x0au,0xb3u,0x82u,0x3cu,0x63u,
0xf3u,0x12u,0xd3u,0xf1u,0x1fu,0xa8u,0x7bu,0xa2u,0x9du,0xa3u,0xc7u,0x22u,0x4bu,0x4fu,0xb4u,0xbcu
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_NoVerify_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Create session handle to be used by verify function */
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session,
MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE,
MCUXCLRSA_VERIFY_2048_WAPKC_SIZE);
/* Initialize the PRNG */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Create key struct of type MCUXCLRSA_KEY_PUBLIC */
const mcuxClRsa_KeyEntry_t Mod1 = {
.pKeyEntryData = (uint8_t *)modulus,
.keyEntryLength = RSA_KEY_BYTE_LENGTH };
const mcuxClRsa_KeyEntry_t Exp1 = {
.pKeyEntryData = (uint8_t *)exponent,
.keyEntryLength = 3U };
const mcuxClRsa_Key public_key = {
.keytype = MCUXCLRSA_KEY_PUBLIC,
.pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1,
.pMod2 = NULL,
.pQInv = NULL,
.pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1,
.pExp2 = NULL,
.pExp3 = NULL };
/* Prepare buffer to store the result */
uint8_t encodedMessag[RSA_KEY_BYTE_LENGTH];
/**************************************************************************/
/* RSA verification call */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClRsa_verify(
/* mcuxClSession_Handle_t pSession: */ session,
/* const mcuxClRsa_Key * const pKey: */ &public_key,
/* mcuxCl_InputBuffer_t pMessageOrDigest: */ NULL,
/* const uint32_t messageLength: */ 0u,
/* mcuxCl_Buffer_t pSignature: */ (uint8_t *)signature,
/* const mcuxClRsa_SignVerifyMode pVerifyMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Verify_NoVerify,
/* const uint32_t saltLength: */ 0u,
/* uint32_t options: */ 0u,
/* mcuxCl_Buffer_t pOutput: */ encodedMessag));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_verify) != verify_token) || (MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK != verify_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Verification of the result */
/**************************************************************************/
for (size_t i = 0U; i < sizeof(encodedMessag); i++)
{
if (reference_result[i] != encodedMessag[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
/**************************************************************************/
/* Session clean-up */
/**************************************************************************/
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01319.html b/components/els_pkc/doc/mcxn/html/a01319.html new file mode 100644 index 000000000..a6217b033 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01319.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: mcuxClRsa_sign_NoEncode_example.c + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
mcuxClRsa_sign_NoEncode_example.c
+
+
+

Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format.

+
/*--------------------------------------------------------------------------*/
/* Copyright 2021-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may */
/* only be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that */
/* you have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*--------------------------------------------------------------------------*/
#include <mcuxClSession.h> // Interface to the entire mcuxClSession component
#include <mcuxClExample_Session_Helper.h>
#include <mcuxCsslFlowProtection.h>
#include <mcuxClCore_FunctionIdentifiers.h> // Code flow protection
#include <mcuxClRandom.h> // Interface to the entire mcuxClRandom component
#include <mcuxClRsa.h> // Interface to the entire mcuxClRsa component
#include <mcuxClToolchain.h> // Memory segment definitions
#include <mcuxClCore_Examples.h>
#include <mcuxClEls.h> // Interface to the entire mcuxClEls component
#include <mcuxClExample_ELS_Helper.h>
/**********************************************************/
/* Example test vectors */
/**********************************************************/
#define RSA_KEY_BIT_LENGTH (1024U)
#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8U)
static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0xd0u, 0xb7u, 0x50u, 0xc8u, 0x55u, 0x4bu, 0x64u, 0xc7u,
0xa9u, 0xd3u, 0x4du, 0x06u, 0x8eu, 0x02u, 0x0fu, 0xb5u,
0x2fu, 0xeau, 0x1bu, 0x39u, 0xc4u, 0x79u, 0x71u, 0xa3u,
0x59u, 0xf0u, 0xeeu, 0xc5u, 0xdau, 0x04u, 0x37u, 0xeau,
0x3fu, 0xc9u, 0x45u, 0x97u, 0xd8u, 0xdbu, 0xffu, 0x54u,
0x44u, 0xf6u, 0xceu, 0x5au, 0x32u, 0x93u, 0xacu, 0x89u,
0xb1u, 0xeeu, 0xbbu, 0x3fu, 0x71u, 0x2bu, 0x3au, 0xd6u,
0xa0u, 0x63u, 0x86u, 0xe6u, 0x40u, 0x19u, 0x85u, 0xe1u,
0x98u, 0x98u, 0x71u, 0x5bu, 0x1eu, 0xa3u, 0x2au, 0xc0u,
0x34u, 0x56u, 0xfeu, 0x17u, 0x96u, 0xd3u, 0x1eu, 0xd4u,
0xafu, 0x38u, 0x9fu, 0x4fu, 0x67u, 0x5cu, 0x23u, 0xc4u,
0x21u, 0xa1u, 0x25u, 0x49u, 0x1eu, 0x74u, 0x0fu, 0xdau,
0xc4u, 0x32u, 0x2eu, 0xc2u, 0xd4u, 0x6eu, 0xc9u, 0x45u,
0xddu, 0xc3u, 0x49u, 0x22u, 0x7bu, 0x49u, 0x21u, 0x91u,
0xc9u, 0x04u, 0x91u, 0x45u, 0xfbu, 0x2fu, 0x8cu, 0x29u,
0x98u, 0xc4u, 0x86u, 0xa8u, 0x40u, 0xeau, 0xc4u, 0xd3u
};
static const uint8_t d[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x27u, 0xb7u, 0x11u, 0x9au, 0x09u, 0xedu, 0xb8u, 0x27u,
0xc1u, 0x34u, 0x18u, 0xc8u, 0x20u, 0xb5u, 0x22u, 0xa1u,
0xeeu, 0x08u, 0xdeu, 0x0eu, 0x4bu, 0xb2u, 0x81u, 0x06u,
0xdbu, 0x6bu, 0xb9u, 0x14u, 0x98u, 0xa3u, 0xb3u, 0x61u,
0xabu, 0x29u, 0x3au, 0xf8u, 0x3fu, 0xefu, 0xcdu, 0xd8u,
0xa6u, 0xbdu, 0x21u, 0x34u, 0xcau, 0x4au, 0xfau, 0xcfu,
0x64u, 0xa0u, 0xe3u, 0x3cu, 0x01u, 0x4fu, 0x48u, 0xf4u,
0x75u, 0x30u, 0xf8u, 0x84u, 0x7cu, 0xc9u, 0x18u, 0x5cu,
0xbeu, 0xdeu, 0xc0u, 0xd9u, 0x23u, 0x8cu, 0x8fu, 0x1du,
0x54u, 0x98u, 0xf7u, 0x1cu, 0x7cu, 0x0cu, 0xffu, 0x48u,
0xdcu, 0x21u, 0x34u, 0x21u, 0x74u, 0x2eu, 0x34u, 0x35u,
0x0cu, 0xa9u, 0x40u, 0x07u, 0x75u, 0x3cu, 0xc0u, 0xe5u,
0xa7u, 0x83u, 0x26u, 0x4cu, 0xf4u, 0x9fu, 0xf6u, 0x44u,
0xffu, 0xeau, 0x94u, 0x25u, 0x3cu, 0xfeu, 0x86u, 0x85u,
0x9au, 0xcdu, 0x2au, 0x22u, 0x76u, 0xcau, 0x4eu, 0x72u,
0x15u, 0xf8u, 0xebu, 0xaau, 0x2fu, 0x18u, 0x8fu, 0x51u
};
static const uint8_t message[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x00u, 0x01u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x30u, 0x31u, 0x30u,
0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u,
0x03u, 0x04u, 0x02u, 0x01u, 0x05u, 0x00u, 0x04u, 0x20u,
0x7cu, 0x50u, 0xbdu, 0xf5u, 0xafu, 0x92u, 0x3du, 0x43u,
0x2cu, 0xefu, 0x56u, 0x84u, 0xfdu, 0xfau, 0x9du, 0xbau,
0x18u, 0x9au, 0xaeu, 0x69u, 0x98u, 0x92u, 0xb9u, 0xa6u,
0x86u, 0x3au, 0x35u, 0xeeu, 0xcfu, 0x54u, 0x6du, 0xecu
};
static const uint8_t referenceSignature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = {
0x02u, 0x3au, 0x8du, 0x88u, 0x87u, 0xd3u, 0x81u, 0x4fu,
0xb6u, 0xceu, 0xb1u, 0x2cu, 0xf9u, 0x87u, 0x9cu, 0x49u,
0xebu, 0xf2u, 0x16u, 0xd0u, 0x6cu, 0x32u, 0x2du, 0xa7u,
0x72u, 0xb2u, 0xe5u, 0x1fu, 0x7au, 0x70u, 0xc1u, 0x30u,
0x74u, 0x3au, 0xacu, 0xebu, 0x0cu, 0x81u, 0x01u, 0x6cu,
0x55u, 0xe1u, 0x1cu, 0x7eu, 0x93u, 0x1fu, 0x1au, 0x28u,
0xcau, 0xe9u, 0xe1u, 0x70u, 0xa9u, 0xf9u, 0x7bu, 0x2du,
0xfcu, 0xc0u, 0xbfu, 0x3cu, 0x56u, 0xbdu, 0x8fu, 0xe1u,
0xd3u, 0xa1u, 0xb4u, 0xe3u, 0xe5u, 0xd2u, 0xb2u, 0x51u,
0x88u, 0xe9u, 0x9au, 0x90u, 0x19u, 0x33u, 0xb8u, 0xa6u,
0xd4u, 0x55u, 0x3du, 0xcbu, 0xc3u, 0x0cu, 0xdbu, 0x27u,
0xdcu, 0x86u, 0x55u, 0xe2u, 0x0du, 0x1du, 0x59u, 0xc5u,
0xb4u, 0x23u, 0xcbu, 0xaau, 0xcau, 0x1bu, 0x7bu, 0x8au,
0xe7u, 0x30u, 0x64u, 0xc8u, 0x42u, 0x28u, 0xd9u, 0xd3u,
0xdbu, 0x6au, 0x54u, 0x7fu, 0x21u, 0x95u, 0x12u, 0x58u,
0xf3u, 0xc9u, 0x98u, 0x54u, 0x1du, 0x6au, 0x15u, 0x96u
};
MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_NoEncode_example)
{
/**************************************************************************/
/* Preparation */
/**************************************************************************/
if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
/* Create session handle to be used by mcuxClRsa_sign */
mcuxClSession_Descriptor_t sessionDesc;
mcuxClSession_Handle_t session = &sessionDesc;
MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session,
MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE,
MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE);
/* Initialize the PRNG */
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session));
if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/* Create key struct of type MCUXCLRSA_KEY_PRIVATEPLAIN */
const mcuxClRsa_KeyEntry_t Mod1 = {
.pKeyEntryData = (uint8_t *)modulus,
.keyEntryLength = RSA_KEY_BYTE_LENGTH };
const mcuxClRsa_KeyEntry_t Exp1 = {
.pKeyEntryData = (uint8_t *)d,
.keyEntryLength = sizeof(d) };
const mcuxClRsa_Key private_key = {
.keytype = MCUXCLRSA_KEY_PRIVATEPLAIN,
.pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1,
.pMod2 = NULL,
.pQInv = NULL,
.pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1,
.pExp2 = NULL,
.pExp3 = NULL };
/* Prepare buffer to store the result */
uint8_t signature[RSA_KEY_BYTE_LENGTH];
/**************************************************************************/
/* RSA signature generation call */
/**************************************************************************/
MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_status, sign_token, mcuxClRsa_sign(
/* mcuxClSession_Handle_t pSession: */ session,
/* const mcuxClRsa_Key * const pKey: */ &private_key,
/* mcuxCl_InputBuffer_t pMessageOrDigest: */ message,
/* const uint32_t messageLength: */ RSA_KEY_BYTE_LENGTH,
/* const mcuxClRsa_SignVerifyMode pPaddingMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Sign_NoEncode,
/* const uint32_t saltLength: */ 0u,
/* uint32_t options: */ 0u,
/* mcuxCl_Buffer_t pSignature: */ signature));
if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_sign) != sign_token || MCUXCLRSA_STATUS_SIGN_OK != sign_status)
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
MCUX_CSSL_FP_FUNCTION_CALL_END();
/**************************************************************************/
/* Verification of the result */
/**************************************************************************/
for(size_t i = 0U; i < RSA_KEY_BYTE_LENGTH; i++)
{
if(referenceSignature[i] != signature[i])
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
}
/**************************************************************************/
/* Session clean-up */
/**************************************************************************/
if(!mcuxClExample_Session_Clean(session))
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
if(!mcuxClExample_Els_Disable())
{
return MCUXCLEXAMPLE_STATUS_ERROR;
}
return MCUXCLEXAMPLE_STATUS_OK;
}
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01320.html b/components/els_pkc/doc/mcxn/html/a01320.html new file mode 100644 index 000000000..fca8daed0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01320.html @@ -0,0 +1,175 @@ + + + + + + + +MCUX CLNS: User Guidance Manual + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
User Guidance Manual
+
+
+

General Information

+
    +
  • This documentation describes a version of the Crypto Library Normal Secure (CLNS). To identify your version of the CLNS, see #nxpCl_GetVersion.
    • +
  • The CLNS is separated into software components, each of which encapsulates a disjoint subset of its functionality with a common purpose. For example, that purpose can be the abstraction of a hardware IP (Intellectual Property) or the implementation of a specific cryptographic algorithm.
      +
    • Each component has a name that begins with the prefix nxpCl.
      • +
    • The names of all header files, functions and data types belonging to a component named <component-name> begin with the prefix <component-name>_.
      • +
    • The names of all preprocessor macros belonging to a component named nxpCl<Name> begin with the prefix NXPCL<NAME>_.
      • +
    +
    • +
  • Additionally, there is some component-independent functionality, such as CLNS version information.
      +
    • The names of all header files, functions and data types that are part of component-independent functionality begin with the prefix nxpCl_.
      • +
    • The names of all preprocessor macros that are part of component-independent functionality begin with the prefix NXPCL_.
      • +
    +
    • +
  • The CLNS API consists only of the declarations contained in the API header files. Other functions, macros or types found in other source files should not be used.
    • +

  • In order to minimize CPU wait cycles during coprocessor activities, some CLNS functions (non-blocking functions) are implemented in a non-blocking way, which means that the underlying operation has not completed at function return.

    +

    It is the caller's responsibility to ensure that the operation has completed before further processing on the operation output data is performed.

    +

    The names of all non-blocking functions end with the suffix _Async.

    +
    • +
+

Release Content

+

The release consists of three files, the NXP Software Content Register softwareContentRegister.txt, the NXP Software License Agreement LICENSE.htm and an archive with the file name extension .zip. The archive contains the following data:

    +
  • The doc folder contains Doxygen HTML documentation of the CLNS interfaces and example code. Open doc/html/index.html in a browser to view its main page.
    • +
  • The examples folder contains integration example code for each included component.
    • +
  • The includes folder directly contains the header source files that make up the API of the CLNS.
    • +
  • The includes/platform folder contains platform-specific header files that are required for integration of the CLNS.
    • +
  • The static_library folder contains a static library (archive of object code files) that contains the CLNS binaries.
    • +
  • The LICENSE.htm file contains the NXP Software License Agreement.
    • +
  • The softwareContentRegister.txt file contains the NXP Software Content Register. Note that this file is identical to the softwareContentRegister.txt delivered alongside the archive.
    • +
+

Components

+

nxpClEls

+

Hardware IP

+
    +
  • The Edge Lock Secure Subsystem (ELS) is a cryptographic coprocessor that can be configured to support a range of symmetric and asymmetric cryptographic operations.
    • +

  • This release of the CLNS is designed for compatibility with a specific version of the ELS hardware IP.

    +

    To identify that compatible version, see #NXPCLELS_HW_VERSION.

    +

    To identify your actual version of the ELS hardware IP at run-time, see #nxpClEls_GetHwVersion. For details about the ELS, read the document "Crypto Secure Sequencer – Reference Manual".

    ELS Base Address

    +
    • +
+

Enabling and Disabling the ELS

+

To optimize power utilization, the ELS hardware IP provides a clock gating mechanism to enable and disable itself. Prior to any ELS-based operations invoked via the CLNS, the ELS must be enabled. The CLNS API provides the following support functions to enable/disable the ELS hardware:

    +
  • #nxpClEls_Enable_Async
    • +
  • #nxpClEls_Disable
    • +
+

Buffer Allocation

+

All input and output buffers of nxpClEls functions must be placed in memory regions that are accessible to the ELS hardware IP.

+

Usage

+
Non-blocking Functions
+

It is the caller's responsibility to ensure that the operation of a non-blocking function has completed before further processing on the operation output data is performed. For nxpClEls functions, this can be achieved by either polling the ELS hardware status flag or by acting on hardware interrupts. The CLNS implements the support functions #nxpClEls_WaitForOperation and #nxpClEls_LimitedWaitForOperation for the former method. #nxpClEls_WaitForOperation potentially waits an infinite amount of time, while #nxpClEls_LimitedWaitForOperation uses a counter to limit the amount of time spent waiting.

+
Sha Direct Mode
+

The ELS hardware IP contains a stand-alone Sha module which can be used in parallel with other ELS operations. ELS operations make use of a ELS-internal DMA (Direct Memory Access) module for data handling. The stand-alone Sha module is an exception of this behavior: It is the caller's responsibility to perform the data handling, which can be achieved using the CPU or the system DMA.

+
Alignment
+

As for all other components, all input and output buffers of nxpClEls functions that store external keys must be CPU word-aligned. From a functional perspective, all other input and output buffers of nxpClEls functions have no alignment requirement, unless explicitly stated otherwise. Using CPU word-aligned buffers may improve operation performance.

+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/a01321.html b/components/els_pkc/doc/mcxn/html/a01321.html new file mode 100644 index 000000000..cd74a8fd8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/a01321.html @@ -0,0 +1,140 @@ + + + + + + + +MCUX CLNS: Security and Integration Guidance Manual + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Security and Integration Guidance Manual
+
+
+

When you write software which makes calls to CLNS, please follow these integration requirements. Not following them will most likely make your software vulnerable to attacks.

+

Checking the correctness of return values

+

In general, the return values of all CLNS API functions must be checked. These checks should ideally be written in such a way that, on an assembly code level, the code for the error condition is executed by default. This means that skipping all branch instructions must lead to an error condition, which helps avoid fault injection vulnerabilities. Depending on the architecture, the compiler may generate branch instructions or conditional instructions to reach the code for the success condition. We encourage that you check this manually.

+

Code-flow monitoring

+

Most CLNS API functions monitor the code path taken internally and calculate a protection value that must be verified by the caller of the library. This can be done with e.g. the following code snippet:

+
#include <nxpCsslFlowProtection.h>
#include <nxpClEls.h>
int main(void)
{
/* Enable the ELS.
*
* This macro opens a new scope `{}`.
* `result` and `token` are variables which are only valid in this scope.
*
* - `result` contains the function's return value.
* - `token`, referred to in the documentation as the protection token, contains the monitored code path check value.
* Under normal circumstances, this token must be equal to the reference value `NXP_CSSL_FP_FUNCTION_CALLED(nxpClEls_WaitForOperation)`.
* If the two differ, the code path has been altered, pointing to a fault injection attack.
*/
NXP_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, nxpClEls_Enable_Async());
/* Check the protection token and result. If an attack occurred, handle it here. */
if(NXP_CSSL_FP_FUNCTION_CALLED(nxpClEls_WaitForOperation) != token || NXPCLELS_STATUS_SW_FAULT == result || NXPCLELS_STATUS_HW_FAULT == result)
{
/* Attack handling */
resetDevice();
}
/* Check the result for functional errors. */
if(NXPCLELS_STATUS_OK != result)
{
/* Error handling */
return false;
}
/* This macro closes the scope `{}`. After this point, the variables `result` and `token` are no longer visible. */
NXP_CSSL_FP_FUNCTION_CALL_END();
/* Don't forget to do the same for nxpClEls_WaitForOperation()! */
return 0;
}

In cases where the attack handling and error handling methods are identical, the two if-statements may be merged like this:

+
#include <nxpCsslFlowProtection.h>
#include <nxpClEls.h>
int main(void)
{
/* Enable the ELS. */
NXP_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, nxpClEls_Enable_Async());
/* Check for attacks and/or errors. */
if(NXP_CSSL_FP_FUNCTION_CALLED(nxpClEls_WaitForOperation) != token || NXPCLELS_STATUS_OK != result)
{
/* Attack and error handling */
resetDevice();
}
NXP_CSSL_FP_FUNCTION_CALL_END();
/* Don't forget to do the same for nxpClEls_WaitForOperation()! */
return 0;
}

CLNS API functions which support this feature can be identified by their declaration: if NXP_CSSL_FP_FUNCTION_DECL is part of the declaration, the function supports code flow monitoring.

+

The underlying monitoring functionality is provided by a library called CSSL, which is bundled together with CLNS. For details, you may want to check the CSSL documentation.

+

Parameter integrity protection

+

Some CLNS API functions use parameter integrity protection, which provides additional assurance against fault injection attacks. The first parameter of such functions has the type nxpCsslParamIntegrity_Checksum_t. In order to call these functions correctly, you must first calculate the parameter checksum. See the example below:

+
#include <stdint.h>
#include <nxpCsslMemory.h>
#include <nxpCsslFlowProtection.h>
#include <nxpCsslParamIntegrity.h>
int main(void) {
uint8_t arr1[33U] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, 0x76u};
/* Compare arr1 with itself. Compute the parameter checksum and pass it to the function.
* The first parameter here is the number of arguments, and is followed by the actual arguments.
*/
nxpCsslParamIntegrity_Checksum_t checksum = nxpCsslParamIntegrity_Protect(3U, arr1, arr1, sizeof(arr1));
NXP_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, nxpCsslMemory_Compare(checksum, arr1, arr1, sizeof(arr1)));
/* Check for attacks and/or errors. */
if(NXP_CSSL_FP_FUNCTION_CALLED(nxpCsslMemory_Compare) != token || NXPCSSLMEMORY_STATUS_EQUAL != result)
{
/* Attack and error handling */
return -1;
}
NXP_CSSL_FP_FUNCTION_CALL_END();
return 0;
}

Alignment of sensitive data

+

All sensitive data (such as private keys), including sensitive CLNS API function parameters, should be aligned on a 4-byte (or CPU word size, whichever is greater) boundary to provide some protection against side-channel analysis.

+

Input sanitization and preventing privilege escalation

+

Do not use unsanitized input to compute input values to CLNS functions.

+

If you integrate CLNS so that it runs at a privileged execution level and can be called from a lower privileged level, take special care that the following types of input, which are directly used as pointers by CLNS (and called at the privilege level of CLNS), are not derived in any way from unsanitized input:

    +
  • (callback) function pointers passed to CLNS functions
    • +
  • mode pointers passed to CLNS functions (e.g. MAC, Hash or Cipher algorithms)
    • +
+

Otherwise privilege escalation attacks will be possible.

+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/annotated.html b/components/els_pkc/doc/mcxn/html/annotated.html new file mode 100644 index 000000000..949fd5369 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/annotated.html @@ -0,0 +1,161 @@ + + + + + + + +MCUX CLNS: Data Structures + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 CmcuxClEcc_DomainParam_tParameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p
 CmcuxClEcc_KeyGen_Param_tParameter structure for function mcuxClEcc_KeyGen
 CmcuxClEcc_PointMult_Param_tParameter structure for function mcuxClEcc_PointMult
 CmcuxClEcc_Sign_Param_tParameter structure for function mcuxClEcc_Sign
 CmcuxClEcc_Verify_Param_tParameter structure for function mcuxClEcc_Verify
 CmcuxClEcc_Weier_BasicDomainParams_tStructure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1
 CmcuxClEls_AeadOption_tCommand option bit field for mcuxClEls_Aead_Init_Async, mcuxClEls_Aead_UpdateAad_Async, mcuxClEls_Aead_UpdateData_Async and mcuxClEls_Aead_Finalize_Async
 CmcuxClEls_CipherOption_tCommand option bit field for mcuxClEls_Cipher_Async
 CmcuxClEls_CkdfOption_tInternal command option bit field for CKDF functions
 CmcuxClEls_CmacOption_tCommand option bit field for mcuxClEls_Cmac_Async
 CmcuxClEls_CommandCrcConfig_tType to control ELS Command CRC
 CmcuxClEls_EccKeyExchOption_tCommand option bit field for mcuxClEls_EccKeyExchange_Async, for internal use only
 CmcuxClEls_EccKeyGenOption_tCommand option bit field for mcuxClEls_EccKeyGen_Async Bit field to configure mcuxClEls_EccKeyGenOption_t
 CmcuxClEls_EccSignOption_tCommand option bit field for mcuxClEls_EccSign_Async Bit field to configure mcuxClEls_EccSign_Async
 CmcuxClEls_EccVerifyOption_tCommand option bit field for mcuxClEls_EccVerify_Async Bit field to configure mcuxClEls_EccVerifyOption_t
 CmcuxClEls_HashOption_tCommand option bit field for mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect
 CmcuxClEls_HkdfOption_tCommand option bit field for mcuxClEls_Hkdf_Rfc5869_Async
 CmcuxClEls_HmacOption_tCommand option bit field for mcuxClEls_Hmac_Async
 CmcuxClEls_HwConfig_tResult type of #mcuxClEls_GetHwConfig
 CmcuxClEls_HwState_tResult type of mcuxClEls_GetHwState
 CmcuxClEls_HwVersion_tResult type of mcuxClEls_GetHwVersion
 CmcuxClEls_InterruptOptionEn_tCommand option type for mcuxClEls_SetIntEnableFlags and mcuxClEls_GetIntEnableFlags
 CmcuxClEls_InterruptOptionRst_tType to control which ELS interrupts should be reset when calling mcuxClEls_ResetIntFlags
 CmcuxClEls_InterruptOptionSet_tType to control which ELS interrupts should be set when calling mcuxClEls_SetIntFlags
 CmcuxClEls_KeyImportOption_tCommand option bit field for mcuxClEls_KeyImport_Async
 CmcuxClEls_KeyProp_tType for ELS key store key properties
 CmcuxClEls_TlsOption_tInternal command option bit field for mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async
 CmcuxClOscca_MPInt_tStructure for multi-precision integer used in asymetric cryptography
 CmcuxClOscca_ScratchPad_tGlobal scratch pad structure definition
 CmcuxClOsccaPkc_State_tStructure of PKC state backup
 CmcuxClPkc_State_tStructure of PKC state backup
 CmcuxClRandom_ConfigRandom config structure
 CmcuxClRsa_KeyStructure type for Rsa key, specifying key type and key entries
 CmcuxClRsa_KeyEntry_tStructure type for Rsa key entries, specifying key entry length and data
 CmcuxClSession_DescriptorType for mcuxClSession Descriptor
 CmcuxClSession_SecurityContextType for mcuxClSession security context
 CmcuxClSession_WorkAreaType for mcuxClSession workareas flags
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/annotated_dup.js b/components/els_pkc/doc/mcxn/html/annotated_dup.js new file mode 100644 index 000000000..e1e278a53 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/annotated_dup.js @@ -0,0 +1,40 @@ +var annotated_dup = +[ + [ "mcuxClEcc_DomainParam_t", "a00973.html", "a00973" ], + [ "mcuxClEcc_KeyGen_Param_t", "a00977.html", "a00977" ], + [ "mcuxClEcc_PointMult_Param_t", "a00989.html", "a00989" ], + [ "mcuxClEcc_Sign_Param_t", "a00981.html", "a00981" ], + [ "mcuxClEcc_Verify_Param_t", "a00985.html", "a00985" ], + [ "mcuxClEcc_Weier_BasicDomainParams_t", "a00993.html", "a00993" ], + [ "mcuxClEls_AeadOption_t", "a00997.html", "a00997" ], + [ "mcuxClEls_CipherOption_t", "a01009.html", "a01009" ], + [ "mcuxClEls_CkdfOption_t", "a01189.html", "a01189" ], + [ "mcuxClEls_CmacOption_t", "a01021.html", "a01021" ], + [ "mcuxClEls_CommandCrcConfig_t", "a01105.html", "a01105" ], + [ "mcuxClEls_EccKeyExchOption_t", "a01153.html", "a01153" ], + [ "mcuxClEls_EccKeyGenOption_t", "a01141.html", "a01141" ], + [ "mcuxClEls_EccSignOption_t", "a01117.html", "a01117" ], + [ "mcuxClEls_EccVerifyOption_t", "a01129.html", "a01129" ], + [ "mcuxClEls_HashOption_t", "a01165.html", "a01165" ], + [ "mcuxClEls_HkdfOption_t", "a01201.html", "a01201" ], + [ "mcuxClEls_HmacOption_t", "a01177.html", "a01177" ], + [ "mcuxClEls_HwConfig_t", "a01093.html", "a01093" ], + [ "mcuxClEls_HwState_t", "a01045.html", "a01045" ], + [ "mcuxClEls_HwVersion_t", "a01033.html", "a01033" ], + [ "mcuxClEls_InterruptOptionEn_t", "a01057.html", "a01057" ], + [ "mcuxClEls_InterruptOptionRst_t", "a01069.html", "a01069" ], + [ "mcuxClEls_InterruptOptionSet_t", "a01081.html", "a01081" ], + [ "mcuxClEls_KeyImportOption_t", "a01225.html", "a01225" ], + [ "mcuxClEls_KeyProp_t", "a01237.html", "a01237" ], + [ "mcuxClEls_TlsOption_t", "a01213.html", "a01213" ], + [ "mcuxClOscca_MPInt_t", "a01253.html", "a01253" ], + [ "mcuxClOscca_ScratchPad_t", "a01249.html", "a01249" ], + [ "mcuxClOsccaPkc_State_t", "a01257.html", "a01257" ], + [ "mcuxClPkc_State_t", "a01261.html", "a01261" ], + [ "mcuxClRandom_Config", "a01265.html", "a01265" ], + [ "mcuxClRsa_Key", "a01273.html", "a01273" ], + [ "mcuxClRsa_KeyEntry_t", "a01269.html", "a01269" ], + [ "mcuxClSession_Descriptor", "a01285.html", "a01285" ], + [ "mcuxClSession_SecurityContext", "a01281.html", "a01281" ], + [ "mcuxClSession_WorkArea", "a01277.html", "a01277" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/bc_s.png b/components/els_pkc/doc/mcxn/html/bc_s.png new file mode 100644 index 0000000000000000000000000000000000000000..224b29aa9847d5a4b3902efd602b7ddf7d33e6c2 GIT binary patch literal 676 zcmV;V0$crwP)y__>=_9%My z{n931IS})GlGUF8K#6VIbs%684A^L3@%PlP2>_sk`UWPq@f;rU*V%rPy_ekbhXT&s z(GN{DxFv}*vZp`F>S!r||M`I*nOwwKX+BC~3P5N3-)Y{65c;ywYiAh-1*hZcToLHK ztpl1xomJ+Yb}K(cfbJr2=GNOnT!UFA7Vy~fBz8?J>XHsbZoDad^8PxfSa0GDgENZS zuLCEqzb*xWX2CG*b&5IiO#NzrW*;`VC9455M`o1NBh+(k8~`XCEEoC1Ybwf;vr4K3 zg|EB<07?SOqHp9DhLpS&bzgo70I+ghB_#)K7H%AMU3v}xuyQq9&Bm~++VYhF09a+U zl7>n7Jjm$K#b*FONz~fj;I->Bf;ule1prFN9FovcDGBkpg>)O*-}eLnC{6oZHZ$o% zXKW$;0_{8hxHQ>l;_*HATI(`7t#^{$(zLe}h*mqwOc*nRY9=?Sx4OOeVIfI|0V(V2 zBrW#G7Ss9wvzr@>H*`r>zE z+e8bOBgqIgldUJlG(YUDviMB`9+DH8n-s9SXRLyJHO1!=wY^79WYZMTa(wiZ!zP66 zA~!21vmF3H2{ngD;+`6j#~6j;$*f*G_2ZD1E;9(yaw7d-QnSCpK(cR1zU3qU0000< KMNUMnLSTYoA~SLT literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/bdwn.png b/components/els_pkc/doc/mcxn/html/bdwn.png new file mode 100644 index 0000000000000000000000000000000000000000..940a0b950443a0bb1b216ac03c45b8a16c955452 GIT binary patch literal 147 zcmeAS@N?(olHy`uVBq!ia0vp^>_E)H!3HEvS)PKZC{Gv1kP61Pb5HX&C2wk~_T + + + + + + +MCUX CLNS: Data Structure Index + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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Data Structure Index
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m
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  m  
+		mcuxClEls_AeadOption_t   mcuxClEls_EccVerifyOption_t   mcuxClEls_InterruptOptionRst_t   mcuxClPkc_State_t   
mcuxClEls_CipherOption_t   mcuxClEls_HashOption_t   mcuxClEls_InterruptOptionSet_t   mcuxClRandom_Config   
mcuxClEcc_DomainParam_t   mcuxClEls_CkdfOption_t   mcuxClEls_HkdfOption_t   mcuxClEls_KeyImportOption_t   mcuxClRsa_Key   
mcuxClEcc_KeyGen_Param_t   mcuxClEls_CmacOption_t   mcuxClEls_HmacOption_t   mcuxClEls_KeyProp_t   mcuxClRsa_KeyEntry_t   
mcuxClEcc_PointMult_Param_t   mcuxClEls_CommandCrcConfig_t   mcuxClEls_HwConfig_t   mcuxClEls_TlsOption_t   mcuxClSession_Descriptor   
mcuxClEcc_Sign_Param_t   mcuxClEls_EccKeyExchOption_t   mcuxClEls_HwState_t   mcuxClOscca_MPInt_t   mcuxClSession_SecurityContext   
mcuxClEcc_Verify_Param_t   mcuxClEls_EccKeyGenOption_t   mcuxClEls_HwVersion_t   mcuxClOscca_ScratchPad_t   mcuxClSession_WorkArea   
mcuxClEcc_Weier_BasicDomainParams_t   mcuxClEls_EccSignOption_t   mcuxClEls_InterruptOptionEn_t   mcuxClOsccaPkc_State_t   
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m
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/closed.png b/components/els_pkc/doc/mcxn/html/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..98cc2c909da37a6df914fbf67780eebd99c597f5 GIT binary patch literal 132 zcmeAS@N?(olHy`uVBq!ia0vp^oFL4>1|%O$WD@{V-kvUwAr*{o@8{^CZMh(5KoB^r_<4^zF@3)Cp&&t3hdujKf f*?bjBoY!V+E))@{xMcbjXe@)LtDnm{r-UW|*e5JT literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.html b/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.html new file mode 100644 index 000000000..c023529ec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: examples/mcuxCsslMemory Directory Reference + + + + + + + + + + + + + + + + +
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mcuxCsslMemory Directory Reference
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file  data_invariant_memory_compare.c
 Example constant-time memory compare (CSSL component mcuxCsslMemory)
 
file  data_invariant_memory_copy.c
 Example constant-time memory copy (CSSL component mcuxCsslMemory)
 
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.js b/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.js new file mode 100644 index 000000000..4235fc529 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_03f8764938985176bb82066f90476d0a.js @@ -0,0 +1,6 @@ +var dir_03f8764938985176bb82066f90476d0a = +[ + [ "inc", "dir_397074c11054ba9b56701968f508752f.html", "dir_397074c11054ba9b56701968f508752f" ], + [ "data_invariant_memory_compare.c", "a00173.html", "a00173" ], + [ "data_invariant_memory_copy.c", "a00176.html", "a00176" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_1ef99d9f3941c1bb5bff22950fd24df0.html b/components/els_pkc/doc/mcxn/html/dir_1ef99d9f3941c1bb5bff22950fd24df0.html new file mode 100644 index 000000000..cf10e5337 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_1ef99d9f3941c1bb5bff22950fd24df0.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: examples/mcuxClHashModes Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClHashModes Directory Reference
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mcuxClHmac Directory Reference
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inc Directory Reference
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inc Directory Reference
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mcuxClKey Directory Reference
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+Files

file  mcuxClKey_example.c
 Example for the mcuxClKey component.
 
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxCsslFlowProtection Directory Reference
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClCipherModes Directory Reference
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClOsccaSm3 Directory Reference
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MCUX Crypto Library Normal Secure
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_789b10fbea7cebd033e3b0362b1fecef.js b/components/els_pkc/doc/mcxn/html/dir_789b10fbea7cebd033e3b0362b1fecef.js new file mode 100644 index 000000000..ef2a8fd38 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_789b10fbea7cebd033e3b0362b1fecef.js @@ -0,0 +1,12 @@ +var dir_789b10fbea7cebd033e3b0362b1fecef = +[ + [ "mcuxClAeadModes", "dir_8794789cb36db87bacac0d738226e3a5.html", "dir_8794789cb36db87bacac0d738226e3a5" ], + [ "mcuxClEcc", "dir_fd86ae10c2a65c079928a83f489ab440.html", "dir_fd86ae10c2a65c079928a83f489ab440" ], + [ "mcuxClEls", "dir_8a434646fc8236fed8545f11b359bd33.html", "dir_8a434646fc8236fed8545f11b359bd33" ], + [ "mcuxClKey", "dir_48667f1bea109c59ee8faafddd8eabef.html", "dir_48667f1bea109c59ee8faafddd8eabef" ], + [ "mcuxClMacModes", "dir_b19d4aa211bb6dbce6ab36de7af852a2.html", "dir_b19d4aa211bb6dbce6ab36de7af852a2" ], + [ "mcuxClRandomModes", "dir_9213b388d9e49777ed89916a660dacc5.html", "dir_9213b388d9e49777ed89916a660dacc5" ], + [ "mcuxClRsa", "dir_8cc4b1983882a70286ae35228f42fe3d.html", "dir_8cc4b1983882a70286ae35228f42fe3d" ], + [ "mcuxCsslFlowProtection", "dir_596401c3c8fefb49e213c913ed9c7192.html", "dir_596401c3c8fefb49e213c913ed9c7192" ], + [ "mcuxCsslMemory", "dir_03f8764938985176bb82066f90476d0a.html", "dir_03f8764938985176bb82066f90476d0a" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.html b/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.html new file mode 100644 index 000000000..a63a3ccd5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.html @@ -0,0 +1,134 @@ + + + + + + + +MCUX CLNS: examples/mcuxClAeadModes Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClAeadModes Directory Reference
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+Files

file  mcuxClAeadModes_Multipart_Els_Ccm_Example.c
 : Example Aead application
 
file  mcuxClAeadModes_Oneshot_Els_Ccm_Example.c
 : Example Aead application
 
file  mcuxClAeadModes_Oneshot_Els_Gcm_Example.c
 : Example Aead application
 
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+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.js b/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.js new file mode 100644 index 000000000..bb55fb6d3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8794789cb36db87bacac0d738226e3a5.js @@ -0,0 +1,6 @@ +var dir_8794789cb36db87bacac0d738226e3a5 = +[ + [ "mcuxClAeadModes_Multipart_Els_Ccm_Example.c", "a00035.html", "a00035" ], + [ "mcuxClAeadModes_Oneshot_Els_Ccm_Example.c", "a00038.html", "a00038" ], + [ "mcuxClAeadModes_Oneshot_Els_Gcm_Example.c", "a00041.html", "a00041" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.html b/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.html new file mode 100644 index 000000000..23a70e4cf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.html @@ -0,0 +1,158 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEls Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEls Directory Reference
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+Files

file  mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c
 Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls.
 
file  mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c
 Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Common_Get_Info_example.c
 Example of version and configuration load functions.
 
file  mcuxClEls_Ecc_Keygen_Sign_Verify_example.c
 Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Hash_Sha224_One_Block_example.c
 Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Hash_Sha256_One_Block_example.c
 Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Hash_Sha384_One_Block_example.c
 Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Hash_Sha512_One_Block_example.c
 Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Key_Import_Puk_DER_example.c
 Example of PuK import from a DER-encoded certificate using the ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Rng_Prng_Get_Random_example.c
 Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls)
 
file  mcuxClEls_Tls_Master_Key_Session_Keys_example.c
 TLS key derivation example.
 
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.js b/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.js new file mode 100644 index 000000000..5e40d07e3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8a434646fc8236fed8545f11b359bd33.js @@ -0,0 +1,14 @@ +var dir_8a434646fc8236fed8545f11b359bd33 = +[ + [ "mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c", "a00005.html", "a00005" ], + [ "mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c", "a00002.html", "a00002" ], + [ "mcuxClEls_Common_Get_Info_example.c", "a00011.html", "a00011" ], + [ "mcuxClEls_Ecc_Keygen_Sign_Verify_example.c", "a00008.html", "a00008" ], + [ "mcuxClEls_Hash_Sha224_One_Block_example.c", "a00014.html", "a00014" ], + [ "mcuxClEls_Hash_Sha256_One_Block_example.c", "a00017.html", "a00017" ], + [ "mcuxClEls_Hash_Sha384_One_Block_example.c", "a00020.html", "a00020" ], + [ "mcuxClEls_Hash_Sha512_One_Block_example.c", "a00023.html", "a00023" ], + [ "mcuxClEls_Key_Import_Puk_DER_example.c", "a00032.html", "a00032" ], + [ "mcuxClEls_Rng_Prng_Get_Random_example.c", "a00026.html", "a00026" ], + [ "mcuxClEls_Tls_Master_Key_Session_Keys_example.c", "a00029.html", "a00029" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.html b/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.html new file mode 100644 index 000000000..0e984b300 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.html @@ -0,0 +1,137 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRsa Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClRsa Directory Reference
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+Files

file  mcuxClRsa_sign_NoEncode_example.c
 Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format.
 
file  mcuxClRsa_sign_pss_sha2_256_example.c
 Example of using function mcuxClRsa_sign to perform the RSA signature generation with EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2.
 
file  mcuxClRsa_verify_NoVerify_example.c
 Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 (public exponentiation and NO padding verification) according to PKCS #1 v2.2.
 
file  mcuxClRsa_verify_pssverify_sha2_256_example.c
 Example of using function mcuxClRsa_verify to perform the RSA signature verification with EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2.
 
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.js b/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.js new file mode 100644 index 000000000..c23456b0c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_8cc4b1983882a70286ae35228f42fe3d.js @@ -0,0 +1,7 @@ +var dir_8cc4b1983882a70286ae35228f42fe3d = +[ + [ "mcuxClRsa_sign_NoEncode_example.c", "a00167.html", "a00167" ], + [ "mcuxClRsa_sign_pss_sha2_256_example.c", "a00161.html", "a00161" ], + [ "mcuxClRsa_verify_NoVerify_example.c", "a00164.html", "a00164" ], + [ "mcuxClRsa_verify_pssverify_sha2_256_example.c", "a00158.html", "a00158" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.html b/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.html new file mode 100644 index 000000000..434fd39fd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: examples/mcuxClRandomModes Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClRandomModes Directory Reference
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+Files

file  mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_Different_Sessions_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_ELS_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c
 Example for the mcuxClRandomModes component.
 
file  mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c
 Example for the mcuxClRandomModes component.
 
+
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.js b/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.js new file mode 100644 index 000000000..1e6bd8d18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_9213b388d9e49777ed89916a660dacc5.js @@ -0,0 +1,11 @@ +var dir_9213b388d9e49777ed89916a660dacc5 = +[ + [ "mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c", "a00140.html", "a00140" ], + [ "mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c", "a00146.html", "a00146" ], + [ "mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c", "a00134.html", "a00134" ], + [ "mcuxClRandomModes_Different_Sessions_example.c", "a00143.html", "a00143" ], + [ "mcuxClRandomModes_ELS_example.c", "a00137.html", "a00137" ], + [ "mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c", "a00149.html", "a00149" ], + [ "mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c", "a00155.html", "a00155" ], + [ "mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c", "a00152.html", "a00152" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_9f351d46ce3cc29445a41dc3a31e6919.html b/components/els_pkc/doc/mcxn/html/dir_9f351d46ce3cc29445a41dc3a31e6919.html new file mode 100644 index 000000000..8b54a283a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_9f351d46ce3cc29445a41dc3a31e6919.html @@ -0,0 +1,121 @@ + + + + + + + +MCUX CLNS: C:/cccs-sw-tools/bamboo-agent/xml-data/build-dir/CB-CNWJSDKPRCR0-BNXT/config Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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config Directory Reference
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.html b/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.html new file mode 100644 index 000000000..b3e2d0647 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: examples/mcuxClMacModes Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClMacModes Directory Reference
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+Files

file  mcuxClMacModes_cmac_oneshot_example.c
 Example CMAC computation using functions of the mcuxClKey and mcuxClMac component.
 
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.js b/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.js new file mode 100644 index 000000000..b82d7e892 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_b19d4aa211bb6dbce6ab36de7af852a2.js @@ -0,0 +1,4 @@ +var dir_b19d4aa211bb6dbce6ab36de7af852a2 = +[ + [ "mcuxClMacModes_cmac_oneshot_example.c", "a00119.html", "a00119" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.html b/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.html new file mode 100644 index 000000000..cd14f0913 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: examples/mcuxClEcc Directory Reference + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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mcuxClEcc Directory Reference
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+Files

file  mcuxClEcc_EdDSA_Ed25519_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_EdDSA_Ed25519ctx_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_EdDSA_Ed25519ph_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_Mont_Curve25519_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_Mont_Curve448_example.c
 Example for the mcuxClEcc component.
 
file  mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c
 Example for the mcuxClEcc component.
 
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.js b/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.js new file mode 100644 index 000000000..1d8f40675 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dir_fd86ae10c2a65c079928a83f489ab440.js @@ -0,0 +1,11 @@ +var dir_fd86ae10c2a65c079928a83f489ab440 = +[ + [ "mcuxClEcc_EdDSA_Ed25519_example.c", "a00089.html", "a00089" ], + [ "mcuxClEcc_EdDSA_Ed25519ctx_example.c", "a00083.html", "a00083" ], + [ "mcuxClEcc_EdDSA_Ed25519ph_example.c", "a00086.html", "a00086" ], + [ "mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c", "a00095.html", "a00095" ], + [ "mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c", "a00092.html", "a00092" ], + [ "mcuxClEcc_Mont_Curve25519_example.c", "a00074.html", "a00074" ], + [ "mcuxClEcc_Mont_Curve448_example.c", "a00077.html", "a00077" ], + [ "mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c", "a00080.html", "a00080" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/doc.png b/components/els_pkc/doc/mcxn/html/doc.png new file mode 100644 index 0000000000000000000000000000000000000000..17edabff95f7b8da13c9516a04efe05493c29501 GIT binary patch literal 746 zcmV7=@pnbNXRFEm&G8P!&WHG=d)>K?YZ1bzou)2{$)) zumDct!>4SyxL;zgaG>wy`^Hv*+}0kUfCrz~BCOViSb$_*&;{TGGn2^x9K*!Sf0=lV zpP=7O;GA0*Jm*tTYj$IoXvimpnV4S1Z5f$p*f$Db2iq2zrVGQUz~yq`ahn7ck(|CE z7Gz;%OP~J6)tEZWDzjhL9h2hdfoU2)Nd%T<5Kt;Y0XLt&<@6pQx!nw*5`@bq#?l*?3z{Hlzoc=Pr>oB5(9i6~_&-}A(4{Q$>c>%rV&E|a(r&;?i5cQB=} zYSDU5nXG)NS4HEs0it2AHe2>shCyr7`6@4*6{r@8fXRbTA?=IFVWAQJL&H5H{)DpM#{W(GL+Idzf^)uRV@oB8u$ z8v{MfJbTiiRg4bza<41NAzrl{=3fl_D+$t+^!xlQ8S}{UtY`e z;;&9UhyZqQRN%2pot{*Ei0*4~hSF_3AH2@fKU!$NSflS>{@tZpDT4`M2WRTTVH+D? z)GFlEGGHe?koB}i|1w45!BF}N_q&^HJ&-tyR{(afC6H7|aml|tBBbv}55C5DNP8p3 z)~jLEO4Z&2hZmP^i-e%(@d!(E|KRafiU8Q5u(wU((j8un3OR*Hvj+t literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/doxygen.css b/components/els_pkc/doc/mcxn/html/doxygen.css new file mode 100644 index 000000000..e2515926c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/doxygen.css @@ -0,0 +1,1764 @@ +/* The standard CSS for doxygen 1.8.15 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +p.reference, p.definition { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #879ECB; + color: #354C7B; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +p.starttd { + margin-top: 0px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +p.interli { +} + +p.interdd { +} + +p.intertd { +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #FFFFFF; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #FFFFFF; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +ul { + overflow: hidden; /*Fixed: list item bullets overlap floating elements*/ +} + +#side-nav ul { + overflow: visible; /* reset ul rule for scroll bar in GENERATE_TREEVIEW window */ +} + +#main-nav ul { + overflow: visible; /* reset ul rule for the navigation bar drop down lists */ +} + +.fragment { + text-align: left; + direction: ltr; + overflow-x: auto; /*Fixed: fragment lines overlap floating elements*/ + overflow-y: hidden; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 0 0 1px 0; /*Fixed: last line underline overlap border*/ + margin: 4px 8px 4px 2px; + background-color: #FBFCFD; + border: 1px solid #C4CFE5; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line:after { + content:"\000A"; + white-space: pre; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +.lineno { + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +div.ah, span.ah { + background-color: black; + font-weight: bold; + color: #FFFFFF; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000 110%); +} + +div.classindex ul { + list-style: none; + padding-left: 0; +} + +div.classindex span.ai { + display: inline-block; +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl, img.inline { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +blockquote.DocNodeRTL { + border-left: 0; + border-right: 2px solid #9CAFD4; + margin: 0 4px 0 24px; + padding: 0 16px 0 12px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtitle { + padding: 8px; + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + border-top-right-radius: 4px; + border-top-left-radius: 4px; + margin-bottom: -1px; + background-image: url('nav_f.png'); + background-repeat: repeat-x; + background-color: #E2E8F2; + line-height: 1.25; + font-weight: 300; + float:left; +} + +.permalink +{ + font-size: 65%; + display: inline-block; + vertical-align: middle; +} + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: 400; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-color: #DFE5F1; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + +} + +.overload { + font-family: "courier new",courier,monospace; + font-size: 65%; +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname, .tparams .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype, .tparams .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir, .tparams .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view inside a (index) page */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #9CAFD4; + border-bottom: 1px solid #9CAFD4; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +.arrow { + color: #9CAFD4; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; + cursor: pointer; + font-size: 80%; + display: inline-block; + width: 16px; + height: 22px; +} + +.icon { + font-family: Arial, Helvetica; + font-weight: bold; + font-size: 12px; + height: 14px; + width: 16px; + display: inline-block; + background-color: #728DC1; + color: white; + text-align: center; + border-radius: 4px; + margin-left: 2px; + margin-right: 2px; +} + +.icona { + width: 24px; + height: 22px; + display: inline-block; +} + +.iconfopen { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderopen.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.iconfclosed { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderclosed.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.icondoc { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('doc.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +table.directory { + font: 400 14px Roboto,sans-serif; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable caption { + caption-side: top; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + font-weight: 400; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +table.classindex +{ + margin: 10px; + white-space: nowrap; + margin-left: 3%; + margin-right: 3%; + width: 94%; + border: 0; + border-spacing: 0; + padding: 0; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +.PageDocRTL-title div.headertitle { + text-align: right; + direction: rtl; +} + +dl { + padding: 0 0 0 0; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug, dl.examples */ +dl.section { + margin-left: 0px; + padding-left: 0px; +} + +dl.section.DocNodeRTL { + margin-right: 0px; + padding-right: 0px; +} + +dl.note { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #D0C000; +} + +dl.note.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #FF0000; +} + +dl.warning.DocNodeRTL, dl.attention.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00D000; +} + +dl.pre.DocNodeRTL, dl.post.DocNodeRTL, dl.invariant.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #00D000; +} + +dl.deprecated { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #505050; +} + +dl.deprecated.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #505050; +} + +dl.todo { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #00C0E0; +} + +dl.todo.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #00C0E0; +} + +dl.test { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #3030E0; +} + +dl.test.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #3030E0; +} + +dl.bug { + margin-left: -7px; + padding-left: 3px; + border-left: 4px solid; + border-color: #C08050; +} + +dl.bug.DocNodeRTL { + margin-left: 0; + padding-left: 0; + border-left: 0; + margin-right: -7px; + padding-right: 3px; + border-right: 4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectalign +{ + vertical-align: middle; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.plantumlgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #90A5CE; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#334975; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D8DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 8px 10px 10px; + width: 200px; +} + +.PageDocRTL-title div.toc { + float: left !important; + text-align: right; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +.PageDocRTL-title div.toc li { + background-position-x: right !important; + padding-left: 0 !important; + padding-right: 10px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.PageDocRTL-title div.toc li.level1 { + margin-left: 0 !important; + margin-right: 0; +} + +.PageDocRTL-title div.toc li.level2 { + margin-left: 0 !important; + margin-right: 15px; +} + +.PageDocRTL-title div.toc li.level3 { + margin-left: 0 !important; + margin-right: 30px; +} + +.PageDocRTL-title div.toc li.level4 { + margin-left: 0 !important; + margin-right: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.s:after, #powerTip.s:before, +#powerTip.w:after, #powerTip.w:before, +#powerTip.e:after, #powerTip.e:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.nw:after, #powerTip.nw:before, +#powerTip.sw:after, #powerTip.sw:before { + border: solid transparent; + content: " "; + height: 0; + width: 0; + position: absolute; +} + +#powerTip.n:after, #powerTip.s:after, +#powerTip.w:after, #powerTip.e:after, +#powerTip.nw:after, #powerTip.ne:after, +#powerTip.sw:after, #powerTip.se:after { + border-color: rgba(255, 255, 255, 0); +} + +#powerTip.n:before, #powerTip.s:before, +#powerTip.w:before, #powerTip.e:before, +#powerTip.nw:before, #powerTip.ne:before, +#powerTip.sw:before, #powerTip.se:before { + border-color: rgba(128, 128, 128, 0); +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.nw:after, #powerTip.nw:before { + top: 100%; +} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #FFFFFF; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #FFFFFF; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #FFFFFF; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #FFFFFF; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + +/* @group Markdown */ + +/* +table.markdownTable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.markdownTable td, table.markdownTable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.markdownTableHead tr { +} + +table.markdownTableBodyLeft td, table.markdownTable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +th.markdownTableHeadLeft th.markdownTableHeadRight th.markdownTableHeadCenter th.markdownTableHeadNone { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +th.markdownTableHeadLeft { + text-align: left +} + +th.markdownTableHeadRight { + text-align: right +} + +th.markdownTableHeadCenter { + text-align: center +} +*/ + +table.markdownTable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.markdownTable td, table.markdownTable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.markdownTable tr { +} + +th.markdownTableHeadLeft, th.markdownTableHeadRight, th.markdownTableHeadCenter, th.markdownTableHeadNone { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +th.markdownTableHeadLeft, td.markdownTableBodyLeft { + text-align: left +} + +th.markdownTableHeadRight, td.markdownTableBodyRight { + text-align: right +} + +th.markdownTableHeadCenter, td.markdownTableBodyCenter { + text-align: center +} + +.DocNodeRTL { + text-align: right; + direction: rtl; +} + +.DocNodeLTR { + text-align: left; + direction: ltr; +} + +table.DocNodeRTL { + width: auto; + margin-right: 0; + margin-left: auto; +} + +table.DocNodeLTR { + width: auto; + margin-right: auto; + margin-left: 0; +} + +tt, code, kbd, samp +{ + display: inline-block; + direction:ltr; +} +/* @end */ + +u { + text-decoration: underline; +} + diff --git a/components/els_pkc/doc/mcxn/html/doxygen.png b/components/els_pkc/doc/mcxn/html/doxygen.png new file mode 100644 index 0000000000000000000000000000000000000000..3ff17d807fd8aa003bed8bb2a69e8f0909592fd1 GIT binary patch literal 3779 zcmV;!4m|ORP)tMIv#Q0*~7*`IBSO7_x;@a8#Zk6_PeKR_s92J&)(m+);m9Iz3blw)z#Gi zP!9lj4$%+*>Hz@HCmM9L9|8c+0u=!H$O3?R0Kgx|#WP<6fKfC8fM-CQZT|_r@`>VO zX^Hgb|9cJqpdJA5$MCEK`F_2@2Y@s>^+;pF`~jdI0Pvr|vl4`=C)EH@1IFe7pdJ8F zH(qGi004~QnF)Ggga~8v08kGAs2hKTATxr7pwfNk|4#_AaT>w8P6TV+R2kbS$v==} zAjf`s0g#V8lB+b3)5oEI*q+{Yt$MZDruD2^;$+(_%Qn+%v0X-bJO=;@kiJ^ygLBnC z?1OVv_%aex1M@jKU|Z~$eI?PoF4Vj>fDzyo zAiLfpXY*a^Sj-S5D0S3@#V$sRW)g)_1e#$%8xdM>Jm7?!h zu0P2X=xoN>^!4DoPRgph2(2va07yfpXF+WH7EOg1GY%Zn z7~1A<(z7Q$ktEXhW_?GMpHp9l_UL18F3KOsxu81pqoBiNbFSGsof-W z6~eloMoz=4?OOnl2J268x5rOY`dCk0us(uS#Ud4yqOr@?=Q57a}tit|BhY>}~frH1sP`ScHS_d)oqH^lYy zZ%VP`#10MlE~P?cE(%(#(AUSv_T{+;t@$U}El}(1ig`vZo`Rm;+5&(AYzJ^Ae=h2X z@Re%vHwZU>|f0NI&%$*4eJweC5OROQrpPMA@*w|o z()A==l}(@bv^&>H1Ob3C=<^|hob?0+xJ?QQ3-ueQC}zy&JQNib!OqSO@-=>XzxlSF zAZ^U*1l6EEmg3r};_HY>&Jo_{dOPEFTWPmt=U&F#+0(O59^UIlHbNX+eF8UzyDR*T z(=5X$VF3!gm@RooS-&iiUYGG^`hMR(07zr_xP`d!^BH?uD>Phl8Rdifx3Af^Zr`Ku ztL+~HkVeL#bJ)7;`=>;{KNRvjmc}1}c58Sr#Treq=4{xo!ATy|c>iRSp4`dzMMVd@ zL8?uwXDY}Wqgh4mH`|$BTXpUIu6A1-cSq%hJw;@^Zr8TP=GMh*p(m(tN7@!^D~sl$ zz^tf4II4|};+irE$Fnm4NTc5%p{PRA`%}Zk`CE5?#h3|xcyQsS#iONZ z6H(@^i9td!$z~bZiJLTax$o>r(p}3o@< zyD7%(>ZYvy=6$U3e!F{Z`uSaYy`xQyl?b{}eg|G3&fz*`QH@mDUn)1%#5u`0m$%D} z?;tZ0u(mWeMV0QtzjgN!lT*pNRj;6510Wwx?Yi_=tYw|J#7@(Xe7ifDzXuK;JB;QO z#bg~K$cgm$@{QiL_3yr}y&~wuv=P=#O&Tj=Sr)aCUlYmZMcw?)T?c%0rUe1cS+o!qs_ zQ6Gp)-{)V!;=q}llyK3|^WeLKyjf%y;xHku;9(vM!j|~<7w1c*Mk-;P{T&yG) z@C-8E?QPynNQ<8f01D`2qexcVEIOU?y}MG)TAE6&VT5`rK8s(4PE;uQ92LTXUQ<>^ ztyQ@=@kRdh@ebUG^Z6NWWIL;_IGJ2ST>$t!$m$qvtj0Qmw8moN6GUV^!QKNK zHBXCtUH8)RY9++gH_TUV4^=-j$t}dD3qsN7GclJ^Zc&(j6&a_!$jCf}%c5ey`pm~1)@{yI3 zTdWyB+*X{JFw#z;PwRr5evb2!ueWF;v`B0HoUu4-(~aL=z;OXUUEtG`_$)Oxw6FKg zEzY`CyKaSBK3xt#8gA|r_|Kehn_HYVBMpEwbn9-fI*!u*eTA1ef8Mkl1=!jV4oYwWYM}i`A>_F4nhmlCIC6WLa zY%;4&@AlnaG11ejl61Jev21|r*m+?Kru3;1tFDl}#!OzUp6c>go4{C|^erwpG*&h6bspUPJag}oOkN2912Y3I?(eRc@U9>z#HPBHC?nps7H5!zP``90!Q1n80jo+B3TWXp!8Pe zwuKuLLI6l3Gv@+QH*Y}2wPLPQ1^EZhT#+Ed8q8Wo z1pTmIBxv14-{l&QVKxAyQF#8Q@NeJwWdKk>?cpiJLkJr+aZ!Me+Cfp!?FWSRf^j2k z73BRR{WSKaMkJ>1Nbx5dan5hg^_}O{Tj6u%iV%#QGz0Q@j{R^Ik)Z*+(YvY2ziBG)?AmJa|JV%4UT$k`hcOg5r9R?5>?o~JzK zJCrj&{i#hG>N7!B4kNX(%igb%kDj0fOQThC-8mtfap82PNRXr1D>lbgg)dYTQ(kbx z`Ee5kXG~Bh+BHQBf|kJEy6(ga%WfhvdQNDuOfQoe377l#ht&DrMGeIsI5C<&ai zWG$|hop2@@q5YDa)_-A?B02W;#fH!%k`daQLEItaJJ8Yf1L%8x;kg?)k)00P-lH+w z)5$QNV6r2$YtnV(4o=0^3{kmaXn*Dm0F*fU(@o)yVVjk|ln8ea6BMy%vZAhW9|wvA z8RoDkVoMEz1d>|5(k0Nw>22ZT){V<3$^C-cN+|~hKt2)){+l-?3m@-$c?-dlzQ)q- zZ)j%n^gerV{|+t}9m1_&&Ly!9$rtG4XX|WQ8`xYzGC~U@nYh~g(z9)bdAl#xH)xd5a=@|qql z|FzEil{P5(@gy!4ek05i$>`E^G~{;pnf6ftpLh$h#W?^#4UkPfa;;?bsIe&kz!+40 zI|6`F2n020)-r`pFaZ38F!S-lJM-o&inOw|66=GMeP@xQU5ghQH{~5Uh~TMTd;I9` z>YhVB`e^EVj*S7JF39ZgNf}A-0DwOcTT63ydN$I3b?yBQtUI*_fae~kPvzoD$zjX3 zoqBe#>12im4WzZ=f^4+u=!lA|#r%1`WB0-6*3BL#at`47#ebPpR|D1b)3BjT34nYY z%Ds%d?5$|{LgOIaRO{{oC&RK`O91$fqwM0(C_TALcozu*fWHb%%q&p-q{_8*2Zsi^ zh1ZCnr^UYa;4vQEtHk{~zi>wwMC5o{S=$P0X681y`SXwFH?Ewn{x-MOZynmc)JT5v zuHLwh;tLfxRrr%|k370}GofLl7thg>ACWWY&msqaVu&ry+`7+Ss>NL^%T1|z{IGMA zW-SKl=V-^{(f!Kf^#3(|T2W47d(%JVCI4JgRrT1pNz>+ietmFToNv^`gzC@&O-)+i zPQ~RwK8%C_vf%;%e>NyTp~dM5;!C|N0Q^6|CEb7Bw=Vz~$1#FA;Z*?mKSC)Hl-20s t8QyHj(g6VK0RYbl8UjE)0O0w=e*@m04r>stuEhWV002ovPDHLkV1hl;dM*F} literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/dynsections.js b/components/els_pkc/doc/mcxn/html/dynsections.js new file mode 100644 index 000000000..ea0a7b39a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/dynsections.js @@ -0,0 +1,120 @@ +/* + @licstart The following is the entire license notice for the + JavaScript code in this file. + + Copyright (C) 1997-2017 by Dimitri van Heesch + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + + @licend The above is the entire license notice + for the JavaScript code in this file + */ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} + +function toggleLevel(level) +{ + $('table.directory tr').each(function() { + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + + + +MCUX CLNS: Examples + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+
+ +
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+ +
+ +
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+ + +
+ +
+ +
+
+
Examples
+
+
+
Here is a list of all examples:
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/examples.js b/components/els_pkc/doc/mcxn/html/examples.js new file mode 100644 index 000000000..7355324a4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/examples.js @@ -0,0 +1,36 @@ +var examples = +[ + [ "mcuxClEcc_EdDSA_Ed25519_example.c", "a01302.html", null ], + [ "mcuxClEcc_EdDSA_Ed25519ctx_example.c", "a01300.html", null ], + [ "mcuxClEcc_EdDSA_Ed25519ph_example.c", "a01301.html", null ], + [ "mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c", "a01304.html", null ], + [ "mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c", "a01303.html", null ], + [ "mcuxClEcc_Mont_Curve25519_example.c", "a01297.html", null ], + [ "mcuxClEcc_Mont_Curve448_example.c", "a01298.html", null ], + [ "mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c", "a01299.html", null ], + [ "mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c", "a01287.html", null ], + [ "mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c", "a01286.html", null ], + [ "mcuxClEls_Common_Get_Info_example.c", "a01289.html", null ], + [ "mcuxClEls_Ecc_Keygen_Sign_Verify_example.c", "a01288.html", null ], + [ "mcuxClEls_Hash_Sha224_One_Block_example.c", "a01290.html", null ], + [ "mcuxClEls_Hash_Sha256_One_Block_example.c", "a01291.html", null ], + [ "mcuxClEls_Hash_Sha384_One_Block_example.c", "a01292.html", null ], + [ "mcuxClEls_Hash_Sha512_One_Block_example.c", "a01293.html", null ], + [ "mcuxClEls_Key_Import_Puk_DER_example.c", "a01296.html", null ], + [ "mcuxClEls_Rng_Prng_Get_Random_example.c", "a01294.html", null ], + [ "mcuxClEls_Tls_Master_Key_Session_Keys_example.c", "a01295.html", null ], + [ "mcuxClKey_example.c", "a01305.html", null ], + [ "mcuxClMac_cmac_oneshot_example.c", "a01307.html", null ], + [ "mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c", "a01310.html", null ], + [ "mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c", "a01312.html", null ], + [ "mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c", "a01308.html", null ], + [ "mcuxClRandomModes_Different_Sessions_example.c", "a01311.html", null ], + [ "mcuxClRandomModes_ELS_example.c", "a01309.html", null ], + [ "mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c", "a01313.html", null ], + [ "mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c", "a01315.html", null ], + [ "mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c", "a01314.html", null ], + [ "mcuxClRsa_sign_NoEncode_example.c", "a01319.html", null ], + [ "mcuxClRsa_sign_pss_sha2_256_example.c", "a01317.html", null ], + [ "mcuxClRsa_verify_NoVerify_example.c", "a01318.html", null ], + [ "mcuxClRsa_verify_pssverify_sha2_256_example.c", "a01316.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/files.html b/components/els_pkc/doc/mcxn/html/files.html new file mode 100644 index 000000000..c52f4f1a3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/files.html @@ -0,0 +1,327 @@ + + + + + + + +MCUX CLNS: File List + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ + + +
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+ +
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+ +
+ +
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+ + +
+ +
+ +
+
+
File List
+
+
+
Here is a list of all documented files with brief descriptions:
+
[detail level 1234]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 ► examples
 mcuxCl_clns.hCLNS header for component-independent functionality
 mcuxClAead.hTop-level include file for the mcuxClAead component
 mcuxClAead_Constants.hConstants for use with the mcuxClAead component
 mcuxClAead_Functions.hTop-level API of the mcuxClAead component
 mcuxClAead_Types.hType definitions for the mcuxClAead component
 mcuxClAeadModes.h
 mcuxClAeadModes_MemoryConsumption.hDefines the memory consumption for the clAeadModes component
 mcuxClAeadModes_Modes.hThis file defines the modes for the mcuxClAeadModes component
 mcuxClAes.hTop-level interface header for the mcuxClAes component
 mcuxClAes_Constants.h
 mcuxClAes_KeyTypes.hDefinition of supported key types in mcuxClAes component, see also mcuxClKey component
 mcuxClCipher.hTop-level include file for the mcuxClCipher component
 mcuxClCipher_Constants.hConstants for use with the mcuxClCipher component
 mcuxClCipher_Functions.hTop-level API of the mcuxClCipher component
 mcuxClCipher_Types.hType definitions for the mcuxClCipher component
 mcuxClCipherModes.h
 mcuxClCipherModes_MemoryConsumption.h
 mcuxClCipherModes_Modes.hSupported modes for the mcuxClCipher component
 mcuxClCore_Buffer.h
 mcuxClCore_Examples.h
 mcuxClCore_FunctionIdentifiers.hDefinition of function identifiers for the flow protection mechanism
 mcuxClCore_Platform.h
 mcuxClCore_Toolchain.h
 mcuxClEcc.hTop level header of mcuxClEcc component
 mcuxClEcc_Constants.hConstants definition for domain parameters of supported curves
 mcuxClEcc_Functions.hTop level APIs of mcuxClEcc component
 mcuxClEcc_KeyMechanisms.hECC related definitions to be used for key handling mechanisms of the mcuxClKey component
 mcuxClEcc_MemoryConsumption.hDefines the memory consumption for the mcuxClEcc component
 mcuxClEcc_ParameterSizes.hDefinitions of ECC domain parameter, key and signature sizes
 mcuxClEcc_Types.hType definitions of mcuxClEcc component
 mcuxClEcc_WeierECC.hHeader of mcuxClEcc functionalities related to ECC protocols based on (short) Weierstrass curves
 mcuxClEls.hTop-level include file for the ELS driver
 mcuxClEls_Aead.hELS header for Authenticated Encryption with Associated Data (AEAD)
 mcuxClEls_Cipher.hELS header for symmetric ciphers
 mcuxClEls_Cmac.hELS header for CMAC support
 mcuxClEls_Common.hELS header for common functionality
 mcuxClEls_Crc.hELS header for Command CRC functionality
 mcuxClEls_Ecc.hELS header for elliptic curve cryptography This header exposes functions that enable using the ELS for elliptic curve cryptography
 mcuxClEls_Hash.hELS header for hashing
 mcuxClEls_Hmac.hELS header for HMAC support
 mcuxClEls_Kdf.hELS header for key derivation
 mcuxClEls_KeyManagement.hELS header for key management
 mcuxClEls_mapping.hHeader providing mapping for legacy function/definition names (with CSS)
 mcuxClEls_Rng.hELS header for random number generation
 mcuxClEls_Types.hELS type header
 mcuxClExample_ELS_Helper.h
 mcuxClExample_ELS_Key_Helper.h
 mcuxClExample_Key_Helper.h
 mcuxClExample_RFC3394_Helper.h
 mcuxClExample_RNG_Helper.h
 mcuxClExample_Session_Helper.h
 mcuxClHash.hTop-level include file for the mcuxClHash component
 mcuxClHash_Constants.hConstants for use with the mcuxClHash component
 mcuxClHash_Functions.hTop-level API of the mcuxClHash component
 mcuxClHash_MemoryConsumption.hDefines the memory consumption for the mcuxClHash component
 mcuxClHash_Types.hType definitions for the mcuxClHash component
 mcuxClHashModes.h
 mcuxClHashModes_Algorithms.hAlgorithm/mode definitions for the mcuxClHashModes component
 mcuxClHashModes_Constants.hConstants for use with the mcuxClHashModes component
 mcuxClHashModes_Functions.h
 mcuxClHashModes_MemoryConsumption.hDefines the memory consumption for the mcuxClHash component
 mcuxClHmac.h
 mcuxClHmac_Constants.hConstants for the mcuxClHmac component
 mcuxClHmac_Functions.hFunctions for the mcuxClHmac component
 mcuxClHmac_KeyTypes.hDefinition of supported key types in mcuxClHmac component, see also mcuxClKey component
 mcuxClHmac_MemoryConsumption.hDefines the memory consumption for the mcuxClHmac component All work area sizes in bytes are a multiple of CPU wordsize
 mcuxClHmac_Modes.hMode descriptors for the mcuxClHmac component
 mcuxClKey.hTop-level include file for the mcuxClKey component
 mcuxClKey_Constants.hConstants for the mcuxClKey component
 mcuxClKey_Functions.hTop-level API of the mcuxClKey component
 mcuxClKey_MemoryConsumption.hDefines the memory consumption for the mcuxClKey component All work area sizes in bytes are a multiple of CPU wordsize
 mcuxClKey_ProtectionMechanisms.h
 mcuxClKey_Types.hType definitions for the mcuxClKey component
 mcuxClMac.hTop-level include file for the mcuxClMac component
 mcuxClMac_Constants.hConstants and status codes for the mcuxClMac component
 mcuxClMac_Functions.hTop-level API of the mcuxClMac component
 mcuxClMac_Types.hType definitions for the mcuxClMac component
 mcuxClMacModes.h
 mcuxClMacModes_Constants.hConstants for the mcuxClMacModes component
 mcuxClMacModes_Functions.hFunctions for the mcuxClMacModes component
 mcuxClMacModes_MemoryConsumption.hDefines the memory consumption for the mcuxClMacModes component All work area sizes in bytes are a multiple of CPU wordsize
 mcuxClMacModes_Modes.h
 mcuxClMath.hTop level header of mcuxClMath component
 mcuxClMath_Functions.hAPIs of mcuxClMath component
 mcuxClMath_Types.h
 mcuxClMemory.hTop-level include file for the memory operations
 mcuxClMemory_Clear.hMemory header for clear functions
 mcuxClMemory_Copy.hMemory header for copy functions
 mcuxClMemory_Copy_Reversed.hMemory header for reversed copy functions
 mcuxClMemory_Endianness.hMemory header for endianness support functions
 mcuxClMemory_Set.hMemory header for set function
 mcuxClMemory_Types.hMemory type header
 mcuxClOscca_FunctionIdentifiers.hDefinition of function identifiers for the flow protection mechanism
 mcuxClOscca_Memory.h: Macros for alignment memory
 mcuxClOscca_PlatformTypes.h: Platform type definitions
 mcuxClOscca_Types.h: Global type definitions
 mcuxClOsccaPkc.hTop level header of mcuxClOsccaPkc component (PKC hardware driver)
 mcuxClOsccaPkc_Functions.hAPIs of mcuxClOsccaPkc component
 mcuxClOsccaPkc_Types.hType definitions of mcuxClOsccaPkc component
 mcuxClOsccaSm3.hTop-level include file for the mcuxClOsccaSm3 component
 mcuxClOsccaSm3_Algorithms.hAlgorithm/mode definitions for the mcuxClOsccaSm3 component
 mcuxClOsccaSm3_Constants.hConstants for use with the mcuxClOsccaSm3 component
 mcuxClOsccaSm3_MemoryConsumption.hDefines the memory consumption for the mcuxClOsccaSm3 component
 mcuxClPadding.hTop-level include file for the padding component
 mcuxClPadding_Constants.hConstants definitions for the mcuxClPadding component
 mcuxClPadding_Types.hType definitions for the mcuxClPadding component
 mcuxClPkc.hTop level header of mcuxClPkc component (PKC hardware driver)
 mcuxClPkc_Functions.hAPIs of mcuxClPkc component
 mcuxClPkc_Types.hType definitions of mcuxClPkc component
 mcuxClRandom.hTop level header of mcuxClRandom component
 mcuxClRandom_Constants.hConstant definitions of mcuxClRandom component
 mcuxClRandom_Functions.hTop level APIs of mcuxClRandom component
 mcuxClRandom_Types.hType definitions of mcuxClRandom component
 mcuxClRandomModes.hTop level header of mcuxClRandomModes component
 mcuxClRandomModes_Constants.hMode definitions of mcuxClRandomModes component
 mcuxClRandomModes_Functions_PatchMode.h
 mcuxClRandomModes_Functions_TestMode.h
 mcuxClRandomModes_MemoryConsumption.hDefines the memory consumption for the mcuxClRandom component
 mcuxClRsa.hTop-level include file for the mcuxClRsa component
 mcuxClRsa_Constants.hConstant definitions for the mcuxClRsa component
 mcuxClRsa_Functions.hTop-level API of the mcuxClRsa component
 mcuxClRsa_MemoryConsumption.hDefines the memory consumption for the mcuxClRsa component
 mcuxClRsa_Types.hType definitions for the mcuxClRsa component
 mcuxClSession.hTop-level include file for the mcuxClSession component
 mcuxClSession_Functions.hTop-level API of the mcuxClSession component
 mcuxClSession_MemoryConsumption.hDefines the memory consumption for the mcuxClSession component
 mcuxClSession_Types.hType definitions for the mcuxClSession component
 mcuxCsslAnalysis.h
 mcuxCsslCPreProcessor.hThe default implementation is based on standard C preprocessor functionality
 mcuxCsslDataIntegrity.hProvides the API for the CSSL data integrity mechanism
 mcuxCsslDataIntegrity_Cfg.hConfiguration of the implementation for the data integrity mechanism
 mcuxCsslDataIntegrity_Impl.hSelection of the implementation for the data integrity mechanism
 mcuxCsslDataIntegrity_None.hImplementation that disables the CSSL data integrity mechanism
 mcuxCsslFlowProtection.hProvides the API for the CSSL flow protection mechanism
 mcuxCsslFlowProtection_Cfg.hConfiguration of the implementation for the flow protection mechanism
 mcuxCsslFlowProtection_FunctionIdentifiers.hDefinition of function identifiers for the flow protection mechanism
 mcuxCsslFlowProtection_Impl.hSelection of the implementation for the flow protection mechanism
 mcuxCsslFlowProtection_SecureCounter_Common.hCounter based implementation for the flow protection mechanism, for a local security counter
 mcuxCsslFlowProtection_SecureCounter_Local.hCounter based implementation for the flow protection mechanism, for a local security counter
 mcuxCsslMemory.hTop-level include file for the CSSL memory functions
 mcuxCsslMemory_Clear.hHeader file of memory clear function
 mcuxCsslMemory_Compare.hInclude file for constant time memory compare function
 mcuxCsslMemory_Copy.hInclude file for memory copy function
 mcuxCsslMemory_Set.hHeader file of memory set function
 mcuxCsslMemory_Types.hType definitions for the mcuxCsslMemory component
 mcuxCsslParamIntegrity.hTop-level include file for the parameter integrity protection mechanism
 mcuxCsslSecureCounter.hProvides the API for the CSSL secure counter mechanism
 mcuxCsslSecureCounter_Cfg.hConfiguration of the implementation for the secure counter mechanism
 mcuxCsslSecureCounter_Impl.hSelection of the implementation for the secure counter mechanism
 mcuxCsslSecureCounter_None.hImplementation that disables the CSSL secure counter mechanism
 mcuxCsslSecureCounter_SW_Local.hSW implementation of the CSSL secure counter mechanism (using a local variable)
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/files_dup.js b/components/els_pkc/doc/mcxn/html/files_dup.js new file mode 100644 index 000000000..ee1cc0fa5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/files_dup.js @@ -0,0 +1,155 @@ +var files_dup = +[ + [ "examples", "dir_789b10fbea7cebd033e3b0362b1fecef.html", "dir_789b10fbea7cebd033e3b0362b1fecef" ], + [ "mcuxCl_clns.h", "a00200.html", "a00200" ], + [ "mcuxClAead.h", "a00203.html", null ], + [ "mcuxClAead_Constants.h", "a00206.html", "a00206" ], + [ "mcuxClAead_Functions.h", "a00209.html", "a00209" ], + [ "mcuxClAead_Types.h", "a00212.html", "a00212" ], + [ "mcuxClAeadModes.h", "a00215_source.html", null ], + [ "mcuxClAeadModes_MemoryConsumption.h", "a00218.html", "a00218" ], + [ "mcuxClAeadModes_Modes.h", "a00221.html", "a00221" ], + [ "mcuxClAes.h", "a00224.html", null ], + [ "mcuxClAes_Constants.h", "a00227_source.html", null ], + [ "mcuxClAes_KeyTypes.h", "a00230.html", "a00230" ], + [ "mcuxClCipher.h", "a00233.html", null ], + [ "mcuxClCipher_Constants.h", "a00236.html", "a00236" ], + [ "mcuxClCipher_Functions.h", "a00239.html", "a00239" ], + [ "mcuxClCipher_Types.h", "a00242.html", "a00242" ], + [ "mcuxClCipherModes.h", "a00245_source.html", null ], + [ "mcuxClCipherModes_MemoryConsumption.h", "a00248_source.html", null ], + [ "mcuxClCipherModes_Modes.h", "a00251.html", "a00251" ], + [ "mcuxClCore_Buffer.h", "a00254_source.html", null ], + [ "mcuxClCore_Examples.h", "a00257_source.html", null ], + [ "mcuxClCore_FunctionIdentifiers.h", "a00260.html", "a00260" ], + [ "mcuxClCore_Platform.h", "a00263_source.html", null ], + [ "mcuxClCore_Toolchain.h", "a00266_source.html", null ], + [ "mcuxClEcc.h", "a00269.html", null ], + [ "mcuxClEcc_Constants.h", "a00272.html", "a00272" ], + [ "mcuxClEcc_Functions.h", "a00275.html", "a00275" ], + [ "mcuxClEcc_KeyMechanisms.h", "a00278.html", "a00278" ], + [ "mcuxClEcc_MemoryConsumption.h", "a00281.html", "a00281" ], + [ "mcuxClEcc_ParameterSizes.h", "a00284.html", "a00284" ], + [ "mcuxClEcc_Types.h", "a00287.html", "a00287" ], + [ "mcuxClEcc_WeierECC.h", "a00290.html", "a00290" ], + [ "mcuxClEls.h", "a00293.html", null ], + [ "mcuxClEls_Aead.h", "a00296.html", "a00296" ], + [ "mcuxClEls_Cipher.h", "a00299.html", "a00299" ], + [ "mcuxClEls_Cmac.h", "a00302.html", "a00302" ], + [ "mcuxClEls_Common.h", "a00305.html", "a00305" ], + [ "mcuxClEls_Crc.h", "a00308.html", "a00308" ], + [ "mcuxClEls_Ecc.h", "a00311.html", "a00311" ], + [ "mcuxClEls_Hash.h", "a00314.html", "a00314" ], + [ "mcuxClEls_Hmac.h", "a00317.html", "a00317" ], + [ "mcuxClEls_Kdf.h", "a00320.html", "a00320" ], + [ "mcuxClEls_KeyManagement.h", "a00323.html", "a00323" ], + [ "mcuxClEls_mapping.h", "a00326.html", "a00326" ], + [ "mcuxClEls_Rng.h", "a00329.html", "a00329" ], + [ "mcuxClEls_Types.h", "a00332.html", "a00332" ], + [ "mcuxClExample_ELS_Helper.h", "a00335_source.html", null ], + [ "mcuxClExample_ELS_Key_Helper.h", "a00338_source.html", null ], + [ "mcuxClExample_Key_Helper.h", "a00341_source.html", null ], + [ "mcuxClExample_RFC3394_Helper.h", "a00344_source.html", null ], + [ "mcuxClExample_RNG_Helper.h", "a00347_source.html", null ], + [ "mcuxClExample_Session_Helper.h", "a00350_source.html", null ], + [ "mcuxClHash.h", "a00353.html", null ], + [ "mcuxClHash_Constants.h", "a00356.html", "a00356" ], + [ "mcuxClHash_Functions.h", "a00359.html", "a00359" ], + [ "mcuxClHash_MemoryConsumption.h", "a00362.html", "a00362" ], + [ "mcuxClHash_Types.h", "a00365.html", "a00365" ], + [ "mcuxClHashModes.h", "a00368_source.html", null ], + [ "mcuxClHashModes_Algorithms.h", "a00371.html", "a00371" ], + [ "mcuxClHashModes_Constants.h", "a00374.html", "a00374" ], + [ "mcuxClHashModes_Functions.h", "a00377_source.html", null ], + [ "mcuxClHashModes_MemoryConsumption.h", "a00380.html", "a00380" ], + [ "mcuxClHmac.h", "a00383_source.html", null ], + [ "mcuxClHmac_Constants.h", "a00386.html", "a00386" ], + [ "mcuxClHmac_Functions.h", "a00389.html", "a00389" ], + [ "mcuxClHmac_KeyTypes.h", "a00392.html", "a00392" ], + [ "mcuxClHmac_MemoryConsumption.h", "a00395.html", "a00395" ], + [ "mcuxClHmac_Modes.h", "a00398.html", "a00398" ], + [ "mcuxClKey.h", "a00401.html", null ], + [ "mcuxClKey_Constants.h", "a00404.html", "a00404" ], + [ "mcuxClKey_Functions.h", "a00407.html", "a00407" ], + [ "mcuxClKey_MemoryConsumption.h", "a00410.html", "a00410" ], + [ "mcuxClKey_ProtectionMechanisms.h", "a00413_source.html", null ], + [ "mcuxClKey_Types.h", "a00416.html", "a00416" ], + [ "mcuxClMac.h", "a00419.html", null ], + [ "mcuxClMac_Constants.h", "a00422.html", "a00422" ], + [ "mcuxClMac_Functions.h", "a00425.html", "a00425" ], + [ "mcuxClMac_Types.h", "a00428.html", "a00428" ], + [ "mcuxClMacModes.h", "a00431_source.html", null ], + [ "mcuxClMacModes_Constants.h", "a00434.html", "a00434" ], + [ "mcuxClMacModes_Functions.h", "a00437.html", null ], + [ "mcuxClMacModes_MemoryConsumption.h", "a00440.html", "a00440" ], + [ "mcuxClMacModes_Modes.h", "a00443_source.html", null ], + [ "mcuxClMath.h", "a00446.html", null ], + [ "mcuxClMath_Functions.h", "a00449.html", "a00449" ], + [ "mcuxClMath_Types.h", "a00452_source.html", null ], + [ "mcuxClMemory.h", "a00455.html", null ], + [ "mcuxClMemory_Clear.h", "a00458.html", "a00458" ], + [ "mcuxClMemory_Copy.h", "a00461.html", "a00461" ], + [ "mcuxClMemory_Copy_Reversed.h", "a00464.html", "a00464" ], + [ "mcuxClMemory_Endianness.h", "a00467.html", "a00467" ], + [ "mcuxClMemory_Set.h", "a00470.html", "a00470" ], + [ "mcuxClMemory_Types.h", "a00473.html", "a00473" ], + [ "mcuxClOscca_FunctionIdentifiers.h", "a00476.html", "a00476" ], + [ "mcuxClOscca_Memory.h", "a00479.html", "a00479" ], + [ "mcuxClOscca_PlatformTypes.h", "a00482.html", "a00482" ], + [ "mcuxClOscca_Types.h", "a00485.html", "a00485" ], + [ "mcuxClOsccaPkc.h", "a00488.html", null ], + [ "mcuxClOsccaPkc_Functions.h", "a00491.html", "a00491" ], + [ "mcuxClOsccaPkc_Types.h", "a00494.html", "a00494" ], + [ "mcuxClOsccaSm3.h", "a00497.html", null ], + [ "mcuxClOsccaSm3_Algorithms.h", "a00500.html", null ], + [ "mcuxClOsccaSm3_Constants.h", "a00503.html", "a00503" ], + [ "mcuxClOsccaSm3_MemoryConsumption.h", "a00506.html", "a00506" ], + [ "mcuxClPadding.h", "a00509.html", null ], + [ "mcuxClPadding_Constants.h", "a00512.html", "a00512" ], + [ "mcuxClPadding_Types.h", "a00515.html", "a00515" ], + [ "mcuxClPkc.h", "a00518.html", null ], + [ "mcuxClPkc_Functions.h", "a00521.html", "a00521" ], + [ "mcuxClPkc_Types.h", "a00524.html", "a00524" ], + [ "mcuxClRandom.h", "a00527.html", null ], + [ "mcuxClRandom_Constants.h", "a00530.html", "a00530" ], + [ "mcuxClRandom_Functions.h", "a00533.html", "a00533" ], + [ "mcuxClRandom_Types.h", "a00536.html", "a00536" ], + [ "mcuxClRandomModes.h", "a00539.html", null ], + [ "mcuxClRandomModes_Constants.h", "a00542.html", "a00542" ], + [ "mcuxClRandomModes_Functions_PatchMode.h", "a00545_source.html", null ], + [ "mcuxClRandomModes_Functions_TestMode.h", "a00548_source.html", null ], + [ "mcuxClRandomModes_MemoryConsumption.h", "a00551.html", "a00551" ], + [ "mcuxClRsa.h", "a00554.html", null ], + [ "mcuxClRsa_Constants.h", "a00557.html", "a00557" ], + [ "mcuxClRsa_Functions.h", "a00560.html", "a00560" ], + [ "mcuxClRsa_MemoryConsumption.h", "a00563.html", "a00563" ], + [ "mcuxClRsa_Types.h", "a00566.html", "a00566" ], + [ "mcuxClSession.h", "a00569.html", null ], + [ "mcuxClSession_Functions.h", "a00572.html", "a00572" ], + [ "mcuxClSession_MemoryConsumption.h", "a00575.html", null ], + [ "mcuxClSession_Types.h", "a00578.html", "a00578" ], + [ "mcuxCsslAnalysis.h", "a00581_source.html", null ], + [ "mcuxCsslCPreProcessor.h", "a00584.html", "a00584" ], + [ "mcuxCsslDataIntegrity.h", "a00587.html", "a00587" ], + [ "mcuxCsslDataIntegrity_Cfg.h", "a00590.html", "a00590" ], + [ "mcuxCsslDataIntegrity_Impl.h", "a00593.html", null ], + [ "mcuxCsslDataIntegrity_None.h", "a00596.html", "a00596" ], + [ "mcuxCsslFlowProtection.h", "a00599.html", "a00599" ], + [ "mcuxCsslFlowProtection_Cfg.h", "a00602.html", "a00602" ], + [ "mcuxCsslFlowProtection_FunctionIdentifiers.h", "a00605.html", "a00605" ], + [ "mcuxCsslFlowProtection_Impl.h", "a00608.html", null ], + [ "mcuxCsslFlowProtection_SecureCounter_Common.h", "a00611.html", "a00611" ], + [ "mcuxCsslFlowProtection_SecureCounter_Local.h", "a00614.html", "a00614" ], + [ "mcuxCsslMemory.h", "a00617.html", null ], + [ "mcuxCsslMemory_Clear.h", "a00620.html", "a00620" ], + [ "mcuxCsslMemory_Compare.h", "a00623.html", "a00623" ], + [ "mcuxCsslMemory_Copy.h", "a00626.html", "a00626" ], + [ "mcuxCsslMemory_Set.h", "a00629.html", "a00629" ], + [ "mcuxCsslMemory_Types.h", "a00632.html", "a00632" ], + [ "mcuxCsslParamIntegrity.h", "a00635.html", "a00635" ], + [ "mcuxCsslSecureCounter.h", "a00638.html", "a00638" ], + [ "mcuxCsslSecureCounter_Cfg.h", "a00641.html", "a00641" ], + [ "mcuxCsslSecureCounter_Impl.h", "a00644.html", null ], + [ "mcuxCsslSecureCounter_None.h", "a00647.html", "a00647" ], + [ "mcuxCsslSecureCounter_SW_Local.h", "a00650.html", "a00650" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/folderclosed.png b/components/els_pkc/doc/mcxn/html/folderclosed.png new file mode 100644 index 0000000000000000000000000000000000000000..bb8ab35edce8e97554e360005ee9fc5bffb36e66 GIT binary patch literal 616 zcmV-u0+;=XP)a9#ETzayK)T~Jw&MMH>OIr#&;dC}is*2Mqdf&akCc=O@`qC+4i z5Iu3w#1M@KqXCz8TIZd1wli&kkl2HVcAiZ8PUn5z_kG@-y;?yK06=cA0U%H0PH+kU zl6dp}OR(|r8-RG+YLu`zbI}5TlOU6ToR41{9=uz^?dGTNL;wIMf|V3`d1Wj3y!#6` zBLZ?xpKR~^2x}?~zA(_NUu3IaDB$tKma*XUdOZN~c=dLt_h_k!dbxm_*ibDM zlFX`g{k$X}yIe%$N)cn1LNu=q9_CS)*>A zsX_mM4L@`(cSNQKMFc$RtYbx{79#j-J7hk*>*+ZZhM4Hw?I?rsXCi#mRWJ=-0LGV5a-WR0Qgt<|Nqf)C-@80`5gIz45^_20000IqP)X=#(TiCT&PiIIVc55T}TU}EUh*{q$|`3@{d>{Tc9Bo>e= zfmF3!f>fbI9#GoEHh0f`i5)wkLpva0ztf%HpZneK?w-7AK@b4Itw{y|Zd3k!fH?q2 zlhckHd_V2M_X7+)U&_Xcfvtw60l;--DgZmLSw-Y?S>)zIqMyJ1#FwLU*%bl38ok+! zh78H87n`ZTS;uhzAR$M`zZ`bVhq=+%u9^$5jDplgxd44}9;IRqUH1YHH|@6oFe%z( zo4)_>E$F&^P-f(#)>(TrnbE>Pefs9~@iN=|)Rz|V`sGfHNrJ)0gJb8xx+SBmRf@1l zvuzt=vGfI)<-F9!o&3l?>9~0QbUDT(wFdnQPv%xdD)m*g%!20>Bc9iYmGAp<9YAa( z0QgYgTWqf1qN++Gqp z8@AYPTB3E|6s=WLG?xw0tm|U!o=&zd+H0oRYE;Dbx+Na9s^STqX|Gnq%H8s(nGDGJ j8vwW|`Ts`)fSK|Kx=IK@RG@g200000NkvXXu0mjfauFEA literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/functions.html b/components/els_pkc/doc/mcxn/html/functions.html new file mode 100644 index 000000000..b15b8798b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions.html @@ -0,0 +1,166 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- _ -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_a.html b/components/els_pkc/doc/mcxn/html/functions_a.html new file mode 100644 index 000000000..f12b23457 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_a.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- a -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_b.html b/components/els_pkc/doc/mcxn/html/functions_b.html new file mode 100644 index 000000000..ba0e71b30 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_b.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- b -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_c.html b/components/els_pkc/doc/mcxn/html/functions_c.html new file mode 100644 index 000000000..ef69f4289 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_c.html @@ -0,0 +1,159 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- c -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_d.html b/components/els_pkc/doc/mcxn/html/functions_d.html new file mode 100644 index 000000000..1770a9e55 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_d.html @@ -0,0 +1,148 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- d -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_dup.js b/components/els_pkc/doc/mcxn/html/functions_dup.js new file mode 100644 index 000000000..150162cc2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_dup.js @@ -0,0 +1,24 @@ +var functions_dup = +[ + [ "_", "functions.html", null ], + [ "a", "functions_a.html", null ], + [ "b", "functions_b.html", null ], + [ "c", "functions_c.html", null ], + [ "d", "functions_d.html", null ], + [ "e", "functions_e.html", null ], + [ "f", "functions_f.html", null ], + [ "g", "functions_g.html", null ], + [ "h", "functions_h.html", null ], + [ "i", "functions_i.html", null ], + [ "k", "functions_k.html", null ], + [ "l", "functions_l.html", null ], + [ "m", "functions_m.html", null ], + [ "o", "functions_o.html", null ], + [ "p", "functions_p.html", null ], + [ "r", "functions_r.html", null ], + [ "s", "functions_s.html", null ], + [ "t", "functions_t.html", null ], + [ "u", "functions_u.html", null ], + [ "v", "functions_v.html", null ], + [ "w", "functions_w.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/functions_e.html b/components/els_pkc/doc/mcxn/html/functions_e.html new file mode 100644 index 000000000..53266237b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_e.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- e -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_f.html b/components/els_pkc/doc/mcxn/html/functions_f.html new file mode 100644 index 000000000..a37ff6a64 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_f.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- f -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_g.html b/components/els_pkc/doc/mcxn/html/functions_g.html new file mode 100644 index 000000000..6957b9bc8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_g.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- g -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_h.html b/components/els_pkc/doc/mcxn/html/functions_h.html new file mode 100644 index 000000000..9976fbf1e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_h.html @@ -0,0 +1,144 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ +
+ +
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+ + +
+ +
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+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- h -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_i.html b/components/els_pkc/doc/mcxn/html/functions_i.html new file mode 100644 index 000000000..497061aa0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_i.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- i -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_k.html b/components/els_pkc/doc/mcxn/html/functions_k.html new file mode 100644 index 000000000..68c0a3804 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_k.html @@ -0,0 +1,165 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- k -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_l.html b/components/els_pkc/doc/mcxn/html/functions_l.html new file mode 100644 index 000000000..5798b4a39 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_l.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- l -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_m.html b/components/els_pkc/doc/mcxn/html/functions_m.html new file mode 100644 index 000000000..a5436a589 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_m.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- m -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_o.html b/components/els_pkc/doc/mcxn/html/functions_o.html new file mode 100644 index 000000000..2d7ded7aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_o.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+ +
+
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+ +
+ +
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+ + +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- o -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_p.html b/components/els_pkc/doc/mcxn/html/functions_p.html new file mode 100644 index 000000000..377445f0b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_p.html @@ -0,0 +1,199 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
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+ +
+ +
+
+ + +
+ +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- p -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_r.html b/components/els_pkc/doc/mcxn/html/functions_r.html new file mode 100644 index 000000000..f45cdccd0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_r.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
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+ +
+ +
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+ + +
+ +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- r -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_s.html b/components/els_pkc/doc/mcxn/html/functions_s.html new file mode 100644 index 000000000..18fefe501 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_s.html @@ -0,0 +1,138 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
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+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- s -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_t.html b/components/els_pkc/doc/mcxn/html/functions_t.html new file mode 100644 index 000000000..4f748db18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_t.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
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+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- t -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_u.html b/components/els_pkc/doc/mcxn/html/functions_u.html new file mode 100644 index 000000000..fdaa2d4e8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_u.html @@ -0,0 +1,174 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
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+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
+
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- u -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_v.html b/components/els_pkc/doc/mcxn/html/functions_v.html new file mode 100644 index 000000000..8f965df1e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_v.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+ +

- v -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars.html b/components/els_pkc/doc/mcxn/html/functions_vars.html new file mode 100644 index 000000000..17b840f77 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars.html @@ -0,0 +1,166 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
+ + +
+ +
+ +
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- _ -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars.js b/components/els_pkc/doc/mcxn/html/functions_vars.js new file mode 100644 index 000000000..fda731967 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars.js @@ -0,0 +1,24 @@ +var functions_vars = +[ + [ "_", "functions_vars.html", null ], + [ "a", "functions_vars_a.html", null ], + [ "b", "functions_vars_b.html", null ], + [ "c", "functions_vars_c.html", null ], + [ "d", "functions_vars_d.html", null ], + [ "e", "functions_vars_e.html", null ], + [ "f", "functions_vars_f.html", null ], + [ "g", "functions_vars_g.html", null ], + [ "h", "functions_vars_h.html", null ], + [ "i", "functions_vars_i.html", null ], + [ "k", "functions_vars_k.html", null ], + [ "l", "functions_vars_l.html", null ], + [ "m", "functions_vars_m.html", null ], + [ "o", "functions_vars_o.html", null ], + [ "p", "functions_vars_p.html", null ], + [ "r", "functions_vars_r.html", null ], + [ "s", "functions_vars_s.html", null ], + [ "t", "functions_vars_t.html", null ], + [ "u", "functions_vars_u.html", null ], + [ "v", "functions_vars_v.html", null ], + [ "w", "functions_vars_w.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_a.html b/components/els_pkc/doc/mcxn/html/functions_vars_a.html new file mode 100644 index 000000000..4fc10a2f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_a.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- a -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_b.html b/components/els_pkc/doc/mcxn/html/functions_vars_b.html new file mode 100644 index 000000000..3c50cc504 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_b.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
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+ +
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+  + +

- b -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_c.html b/components/els_pkc/doc/mcxn/html/functions_vars_c.html new file mode 100644 index 000000000..f20c556d1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_c.html @@ -0,0 +1,159 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
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+ +
+ +
+
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+ +
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+  + +

- c -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_d.html b/components/els_pkc/doc/mcxn/html/functions_vars_d.html new file mode 100644 index 000000000..815e5f6b4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_d.html @@ -0,0 +1,148 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- d -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_e.html b/components/els_pkc/doc/mcxn/html/functions_vars_e.html new file mode 100644 index 000000000..927feae47 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_e.html @@ -0,0 +1,154 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
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+ + + +
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+ +
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+
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+ +
+ +
+  + +

- e -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_f.html b/components/els_pkc/doc/mcxn/html/functions_vars_f.html new file mode 100644 index 000000000..6d0059cca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_f.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
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+ +
+ +
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- f -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_g.html b/components/els_pkc/doc/mcxn/html/functions_vars_g.html new file mode 100644 index 000000000..fe3305e9a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_g.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
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+ +
+ +
+  + +

- g -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_h.html b/components/els_pkc/doc/mcxn/html/functions_vars_h.html new file mode 100644 index 000000000..3071e818b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_h.html @@ -0,0 +1,144 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- h -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_i.html b/components/els_pkc/doc/mcxn/html/functions_vars_i.html new file mode 100644 index 000000000..922224f6e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_i.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- i -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_k.html b/components/els_pkc/doc/mcxn/html/functions_vars_k.html new file mode 100644 index 000000000..01adce3e7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_k.html @@ -0,0 +1,165 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- k -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_l.html b/components/els_pkc/doc/mcxn/html/functions_vars_l.html new file mode 100644 index 000000000..5fe24192e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_l.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
+ +
+
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+ +
+ +
+  + +

- l -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_m.html b/components/els_pkc/doc/mcxn/html/functions_vars_m.html new file mode 100644 index 000000000..61f8f67eb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_m.html @@ -0,0 +1,136 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
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+ +
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+
+ + +
+ +
+ +
+  + +

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+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_o.html b/components/els_pkc/doc/mcxn/html/functions_vars_o.html new file mode 100644 index 000000000..0363fdf5b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_o.html @@ -0,0 +1,126 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
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+ +
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+
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+
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_p.html b/components/els_pkc/doc/mcxn/html/functions_vars_p.html new file mode 100644 index 000000000..3bc71a78d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_p.html @@ -0,0 +1,199 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_r.html b/components/els_pkc/doc/mcxn/html/functions_vars_r.html new file mode 100644 index 000000000..2e98f7a9c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_r.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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+ +
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+  + +

- r -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_s.html b/components/els_pkc/doc/mcxn/html/functions_vars_s.html new file mode 100644 index 000000000..a6789da18 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_s.html @@ -0,0 +1,138 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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+ +
+ +
+  + +

- s -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_t.html b/components/els_pkc/doc/mcxn/html/functions_vars_t.html new file mode 100644 index 000000000..ccab3b55b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_t.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
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MCUX CLNS +
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+  + +

- t -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_u.html b/components/els_pkc/doc/mcxn/html/functions_vars_u.html new file mode 100644 index 000000000..b84d178aa --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_u.html @@ -0,0 +1,174 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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- u -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_v.html b/components/els_pkc/doc/mcxn/html/functions_vars_v.html new file mode 100644 index 000000000..cd0e9c879 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_v.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
+
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- v -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_vars_w.html b/components/els_pkc/doc/mcxn/html/functions_vars_w.html new file mode 100644 index 000000000..938700f92 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_vars_w.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: Data Fields - Variables + + + + + + + + + + + + + + + + +
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/functions_w.html b/components/els_pkc/doc/mcxn/html/functions_w.html new file mode 100644 index 000000000..80e91c6e3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/functions_w.html @@ -0,0 +1,145 @@ + + + + + + + +MCUX CLNS: Data Fields + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals.html b/components/els_pkc/doc/mcxn/html/globals.html new file mode 100644 index 000000000..f84e4caaf --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals.html @@ -0,0 +1,127 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
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MCUX CLNS +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
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+
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MCUX CLNS +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
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MCUX CLNS +
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+  + +

- d -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_defs.js b/components/els_pkc/doc/mcxn/html/globals_defs.js new file mode 100644 index 000000000..b6d48df47 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_defs.js @@ -0,0 +1,8 @@ +var globals_defs = +[ + [ "d", "globals_defs.html", null ], + [ "e", "globals_defs_e.html", null ], + [ "m", "globals_defs_m.html", null ], + [ "r", "globals_defs_r.html", null ], + [ "u", "globals_defs_u.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/globals_defs_e.html b/components/els_pkc/doc/mcxn/html/globals_defs_e.html new file mode 100644 index 000000000..a5ea186ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_defs_e.html @@ -0,0 +1,128 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_defs_m.html b/components/els_pkc/doc/mcxn/html/globals_defs_m.html new file mode 100644 index 000000000..3fc9ce967 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_defs_m.html @@ -0,0 +1,2893 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_defs_r.html b/components/els_pkc/doc/mcxn/html/globals_defs_r.html new file mode 100644 index 000000000..92c0cf519 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_defs_r.html @@ -0,0 +1,143 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_defs_u.html b/components/els_pkc/doc/mcxn/html/globals_defs_u.html new file mode 100644 index 000000000..3cd0ffb7c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_defs_u.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
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- u -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_dup.js b/components/els_pkc/doc/mcxn/html/globals_dup.js new file mode 100644 index 000000000..42e8616bd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_dup.js @@ -0,0 +1,13 @@ +var globals_dup = +[ + [ "_", "globals.html", null ], + [ "a", "globals_a.html", null ], + [ "d", "globals_d.html", null ], + [ "e", "globals_e.html", null ], + [ "g", "globals_g.html", null ], + [ "k", "globals_k.html", null ], + [ "m", "globals_m.html", null ], + [ "r", "globals_r.html", null ], + [ "s", "globals_s.html", null ], + [ "u", "globals_u.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/globals_e.html b/components/els_pkc/doc/mcxn/html/globals_e.html new file mode 100644 index 000000000..22d230a15 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_e.html @@ -0,0 +1,149 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ + + + + + +
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+
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+ +
+ +
+
+ + +
+ +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_func.html b/components/els_pkc/doc/mcxn/html/globals_func.html new file mode 100644 index 000000000..441498d9f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_func.html @@ -0,0 +1,594 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ + +

- m -

+ + +

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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_g.html b/components/els_pkc/doc/mcxn/html/globals_g.html new file mode 100644 index 000000000..e4b977b73 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_g.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_k.html b/components/els_pkc/doc/mcxn/html/globals_k.html new file mode 100644 index 000000000..1f9bf2f80 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_k.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
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MCUX CLNS +
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MCUX Crypto Library Normal Secure
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_m.html b/components/els_pkc/doc/mcxn/html/globals_m.html new file mode 100644 index 000000000..b5daf5e4e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_m.html @@ -0,0 +1,4163 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
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+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_r.html b/components/els_pkc/doc/mcxn/html/globals_r.html new file mode 100644 index 000000000..137206a9c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_r.html @@ -0,0 +1,146 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
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MCUX CLNS +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_s.html b/components/els_pkc/doc/mcxn/html/globals_s.html new file mode 100644 index 000000000..9a36aa20f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_s.html @@ -0,0 +1,156 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
+ +
+
+ + +
+ +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_type.html b/components/els_pkc/doc/mcxn/html/globals_type.html new file mode 100644 index 000000000..91b9322ca --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_type.html @@ -0,0 +1,372 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
+ + + +
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+ +
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+ +
+ +
+
+ + +
+ +
+ +
+  + +

- m -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_u.html b/components/els_pkc/doc/mcxn/html/globals_u.html new file mode 100644 index 000000000..0dd270980 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_u.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
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+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ +
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+ +

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+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars.html b/components/els_pkc/doc/mcxn/html/globals_vars.html new file mode 100644 index 000000000..032b9cf73 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars.html @@ -0,0 +1,141 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+
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+ +
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+ +
+ +
+
+ + +
+ +
+ +
+  + +

- a -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars.js b/components/els_pkc/doc/mcxn/html/globals_vars.js new file mode 100644 index 000000000..24afdaeba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars.js @@ -0,0 +1,10 @@ +var globals_vars = +[ + [ "a", "globals_vars.html", null ], + [ "d", "globals_vars_d.html", null ], + [ "e", "globals_vars_e.html", null ], + [ "g", "globals_vars_g.html", null ], + [ "k", "globals_vars_k.html", null ], + [ "m", "globals_vars_m.html", null ], + [ "s", "globals_vars_s.html", null ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_d.html b/components/els_pkc/doc/mcxn/html/globals_vars_d.html new file mode 100644 index 000000000..3420f1353 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_d.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
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MCUX Crypto Library Normal Secure
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+ + + + + + +
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+ +
+ +
+
+ + +
+ +
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+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_e.html b/components/els_pkc/doc/mcxn/html/globals_vars_e.html new file mode 100644 index 000000000..3c49187e9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_e.html @@ -0,0 +1,141 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- e -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_g.html b/components/els_pkc/doc/mcxn/html/globals_vars_g.html new file mode 100644 index 000000000..06287321f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_g.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- g -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_k.html b/components/els_pkc/doc/mcxn/html/globals_vars_k.html new file mode 100644 index 000000000..4242b79da --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_k.html @@ -0,0 +1,123 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- k -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_m.html b/components/els_pkc/doc/mcxn/html/globals_vars_m.html new file mode 100644 index 000000000..9d6f7b244 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_m.html @@ -0,0 +1,684 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- m -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/globals_vars_s.html b/components/els_pkc/doc/mcxn/html/globals_vars_s.html new file mode 100644 index 000000000..6ffd3896b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/globals_vars_s.html @@ -0,0 +1,156 @@ + + + + + + + +MCUX CLNS: Globals + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+  + +

- s -

+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/index.html b/components/els_pkc/doc/mcxn/html/index.html new file mode 100644 index 000000000..fbc5ba448 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/index.html @@ -0,0 +1,132 @@ + + + + + + + +MCUX CLNS: User Manual of Crypto Library Normal Secure (CLNS) + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
+
+ + + + + + +
+
+
+ + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
User Manual of Crypto Library Normal Secure (CLNS)
+
+
+

Table of Contents

+ +
+

+User Guidance Manual

+

User Guidance Manual

+

+Security and Integration Guidance Manual

+

Security and Integration Guidance Manual

+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/jquery.js b/components/els_pkc/doc/mcxn/html/jquery.js new file mode 100644 index 000000000..1ee895ca3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/jquery.js @@ -0,0 +1,87 @@ +/*! + * jQuery JavaScript Library v1.7.2 + * http://jquery.com/ + * + * Copyright 2011, John Resig + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * Includes Sizzle.js + * http://sizzlejs.com/ + * Copyright 2011, The Dojo Foundation + * Released under the MIT, BSD, and GPL Licenses. + * + * Date: Wed Mar 21 12:46:34 2012 -0700 + */ +(function(bd,L){var av=bd.document,bu=bd.navigator,bm=bd.location;var b=(function(){var bF=function(b0,b1){return new bF.fn.init(b0,b1,bD)},bU=bd.jQuery,bH=bd.$,bD,bY=/^(?:[^#<]*(<[\w\W]+>)[^>]*$|#([\w\-]*)$)/,bM=/\S/,bI=/^\s+/,bE=/\s+$/,bA=/^<(\w+)\s*\/?>(?:<\/\1>)?$/,bN=/^[\],:{}\s]*$/,bW=/\\(?:["\\\/bfnrt]|u[0-9a-fA-F]{4})/g,bP=/"[^"\\\n\r]*"|true|false|null|-?\d+(?:\.\d*)?(?:[eE][+\-]?\d+)?/g,bJ=/(?:^|:|,)(?:\s*\[)+/g,by=/(webkit)[ \/]([\w.]+)/,bR=/(opera)(?:.*version)?[ \/]([\w.]+)/,bQ=/(msie) ([\w.]+)/,bS=/(mozilla)(?:.*? rv:([\w.]+))?/,bB=/-([a-z]|[0-9])/ig,bZ=/^-ms-/,bT=function(b0,b1){return(b1+"").toUpperCase()},bX=bu.userAgent,bV,bC,e,bL=Object.prototype.toString,bG=Object.prototype.hasOwnProperty,bz=Array.prototype.push,bK=Array.prototype.slice,bO=String.prototype.trim,bv=Array.prototype.indexOf,bx={};bF.fn=bF.prototype={constructor:bF,init:function(b0,b4,b3){var b2,b5,b1,b6;if(!b0){return this}if(b0.nodeType){this.context=this[0]=b0;this.length=1;return this}if(b0==="body"&&!b4&&av.body){this.context=av;this[0]=av.body;this.selector=b0;this.length=1;return this}if(typeof b0==="string"){if(b0.charAt(0)==="<"&&b0.charAt(b0.length-1)===">"&&b0.length>=3){b2=[null,b0,null]}else{b2=bY.exec(b0)}if(b2&&(b2[1]||!b4)){if(b2[1]){b4=b4 instanceof bF?b4[0]:b4;b6=(b4?b4.ownerDocument||b4:av);b1=bA.exec(b0);if(b1){if(bF.isPlainObject(b4)){b0=[av.createElement(b1[1])];bF.fn.attr.call(b0,b4,true)}else{b0=[b6.createElement(b1[1])]}}else{b1=bF.buildFragment([b2[1]],[b6]);b0=(b1.cacheable?bF.clone(b1.fragment):b1.fragment).childNodes}return bF.merge(this,b0)}else{b5=av.getElementById(b2[2]);if(b5&&b5.parentNode){if(b5.id!==b2[2]){return b3.find(b0)}this.length=1;this[0]=b5}this.context=av;this.selector=b0;return this}}else{if(!b4||b4.jquery){return(b4||b3).find(b0)}else{return this.constructor(b4).find(b0)}}}else{if(bF.isFunction(b0)){return b3.ready(b0)}}if(b0.selector!==L){this.selector=b0.selector;this.context=b0.context}return bF.makeArray(b0,this)},selector:"",jquery:"1.7.2",length:0,size:function(){return this.length},toArray:function(){return bK.call(this,0)},get:function(b0){return b0==null?this.toArray():(b0<0?this[this.length+b0]:this[b0])},pushStack:function(b1,b3,b0){var b2=this.constructor();if(bF.isArray(b1)){bz.apply(b2,b1)}else{bF.merge(b2,b1)}b2.prevObject=this;b2.context=this.context;if(b3==="find"){b2.selector=this.selector+(this.selector?" ":"")+b0}else{if(b3){b2.selector=this.selector+"."+b3+"("+b0+")"}}return b2},each:function(b1,b0){return bF.each(this,b1,b0)},ready:function(b0){bF.bindReady();bC.add(b0);return this},eq:function(b0){b0=+b0;return b0===-1?this.slice(b0):this.slice(b0,b0+1)},first:function(){return this.eq(0)},last:function(){return this.eq(-1)},slice:function(){return this.pushStack(bK.apply(this,arguments),"slice",bK.call(arguments).join(","))},map:function(b0){return this.pushStack(bF.map(this,function(b2,b1){return b0.call(b2,b1,b2)}))},end:function(){return this.prevObject||this.constructor(null)},push:bz,sort:[].sort,splice:[].splice};bF.fn.init.prototype=bF.fn;bF.extend=bF.fn.extend=function(){var b9,b2,b0,b1,b6,b7,b5=arguments[0]||{},b4=1,b3=arguments.length,b8=false;if(typeof b5==="boolean"){b8=b5;b5=arguments[1]||{};b4=2}if(typeof b5!=="object"&&!bF.isFunction(b5)){b5={}}if(b3===b4){b5=this;--b4}for(;b40){return}bC.fireWith(av,[bF]);if(bF.fn.trigger){bF(av).trigger("ready").off("ready")}}},bindReady:function(){if(bC){return}bC=bF.Callbacks("once memory");if(av.readyState==="complete"){return setTimeout(bF.ready,1)}if(av.addEventListener){av.addEventListener("DOMContentLoaded",e,false);bd.addEventListener("load",bF.ready,false)}else{if(av.attachEvent){av.attachEvent("onreadystatechange",e);bd.attachEvent("onload",bF.ready);var b0=false;try{b0=bd.frameElement==null}catch(b1){}if(av.documentElement.doScroll&&b0){bw()}}}},isFunction:function(b0){return bF.type(b0)==="function"},isArray:Array.isArray||function(b0){return bF.type(b0)==="array"},isWindow:function(b0){return b0!=null&&b0==b0.window},isNumeric:function(b0){return !isNaN(parseFloat(b0))&&isFinite(b0)},type:function(b0){return b0==null?String(b0):bx[bL.call(b0)]||"object"},isPlainObject:function(b2){if(!b2||bF.type(b2)!=="object"||b2.nodeType||bF.isWindow(b2)){return false}try{if(b2.constructor&&!bG.call(b2,"constructor")&&!bG.call(b2.constructor.prototype,"isPrototypeOf")){return false}}catch(b1){return false}var b0;for(b0 in b2){}return b0===L||bG.call(b2,b0)},isEmptyObject:function(b1){for(var b0 in b1){return false}return true},error:function(b0){throw new Error(b0)},parseJSON:function(b0){if(typeof b0!=="string"||!b0){return null}b0=bF.trim(b0);if(bd.JSON&&bd.JSON.parse){return bd.JSON.parse(b0)}if(bN.test(b0.replace(bW,"@").replace(bP,"]").replace(bJ,""))){return(new Function("return "+b0))()}bF.error("Invalid JSON: "+b0)},parseXML:function(b2){if(typeof b2!=="string"||!b2){return null}var b0,b1;try{if(bd.DOMParser){b1=new DOMParser();b0=b1.parseFromString(b2,"text/xml")}else{b0=new ActiveXObject("Microsoft.XMLDOM");b0.async="false";b0.loadXML(b2)}}catch(b3){b0=L}if(!b0||!b0.documentElement||b0.getElementsByTagName("parsererror").length){bF.error("Invalid XML: "+b2)}return b0},noop:function(){},globalEval:function(b0){if(b0&&bM.test(b0)){(bd.execScript||function(b1){bd["eval"].call(bd,b1)})(b0)}},camelCase:function(b0){return b0.replace(bZ,"ms-").replace(bB,bT)},nodeName:function(b1,b0){return b1.nodeName&&b1.nodeName.toUpperCase()===b0.toUpperCase()},each:function(b3,b6,b2){var b1,b4=0,b5=b3.length,b0=b5===L||bF.isFunction(b3);if(b2){if(b0){for(b1 in b3){if(b6.apply(b3[b1],b2)===false){break}}}else{for(;b40&&b0[0]&&b0[b1-1])||b1===0||bF.isArray(b0));if(b3){for(;b21?aK.call(arguments,0):bG;if(!(--bw)){bC.resolveWith(bC,bx)}}}function bz(bF){return function(bG){bB[bF]=arguments.length>1?aK.call(arguments,0):bG;bC.notifyWith(bE,bB)}}if(e>1){for(;bv
a";bH=bv.getElementsByTagName("*");bE=bv.getElementsByTagName("a")[0];if(!bH||!bH.length||!bE){return{}}bF=av.createElement("select");bx=bF.appendChild(av.createElement("option"));bD=bv.getElementsByTagName("input")[0];bI={leadingWhitespace:(bv.firstChild.nodeType===3),tbody:!bv.getElementsByTagName("tbody").length,htmlSerialize:!!bv.getElementsByTagName("link").length,style:/top/.test(bE.getAttribute("style")),hrefNormalized:(bE.getAttribute("href")==="/a"),opacity:/^0.55/.test(bE.style.opacity),cssFloat:!!bE.style.cssFloat,checkOn:(bD.value==="on"),optSelected:bx.selected,getSetAttribute:bv.className!=="t",enctype:!!av.createElement("form").enctype,html5Clone:av.createElement("nav").cloneNode(true).outerHTML!=="<:nav>",submitBubbles:true,changeBubbles:true,focusinBubbles:false,deleteExpando:true,noCloneEvent:true,inlineBlockNeedsLayout:false,shrinkWrapBlocks:false,reliableMarginRight:true,pixelMargin:true};b.boxModel=bI.boxModel=(av.compatMode==="CSS1Compat");bD.checked=true;bI.noCloneChecked=bD.cloneNode(true).checked;bF.disabled=true;bI.optDisabled=!bx.disabled;try{delete bv.test}catch(bB){bI.deleteExpando=false}if(!bv.addEventListener&&bv.attachEvent&&bv.fireEvent){bv.attachEvent("onclick",function(){bI.noCloneEvent=false});bv.cloneNode(true).fireEvent("onclick")}bD=av.createElement("input");bD.value="t";bD.setAttribute("type","radio");bI.radioValue=bD.value==="t";bD.setAttribute("checked","checked");bD.setAttribute("name","t");bv.appendChild(bD);bC=av.createDocumentFragment();bC.appendChild(bv.lastChild);bI.checkClone=bC.cloneNode(true).cloneNode(true).lastChild.checked;bI.appendChecked=bD.checked;bC.removeChild(bD);bC.appendChild(bv);if(bv.attachEvent){for(by in {submit:1,change:1,focusin:1}){bA="on"+by;bw=(bA in bv);if(!bw){bv.setAttribute(bA,"return;");bw=(typeof bv[bA]==="function")}bI[by+"Bubbles"]=bw}}bC.removeChild(bv);bC=bF=bx=bv=bD=null;b(function(){var bM,bV,bW,bU,bO,bP,bR,bL,bK,bQ,bN,e,bT,bS=av.getElementsByTagName("body")[0];if(!bS){return}bL=1;bT="padding:0;margin:0;border:";bN="position:absolute;top:0;left:0;width:1px;height:1px;";e=bT+"0;visibility:hidden;";bK="style='"+bN+bT+"5px solid #000;";bQ="
";bM=av.createElement("div");bM.style.cssText=e+"width:0;height:0;position:static;top:0;margin-top:"+bL+"px";bS.insertBefore(bM,bS.firstChild);bv=av.createElement("div");bM.appendChild(bv);bv.innerHTML="
t
";bz=bv.getElementsByTagName("td");bw=(bz[0].offsetHeight===0);bz[0].style.display="";bz[1].style.display="none";bI.reliableHiddenOffsets=bw&&(bz[0].offsetHeight===0);if(bd.getComputedStyle){bv.innerHTML="";bR=av.createElement("div");bR.style.width="0";bR.style.marginRight="0";bv.style.width="2px";bv.appendChild(bR);bI.reliableMarginRight=(parseInt((bd.getComputedStyle(bR,null)||{marginRight:0}).marginRight,10)||0)===0}if(typeof bv.style.zoom!=="undefined"){bv.innerHTML="";bv.style.width=bv.style.padding="1px";bv.style.border=0;bv.style.overflow="hidden";bv.style.display="inline";bv.style.zoom=1;bI.inlineBlockNeedsLayout=(bv.offsetWidth===3);bv.style.display="block";bv.style.overflow="visible";bv.innerHTML="
";bI.shrinkWrapBlocks=(bv.offsetWidth!==3)}bv.style.cssText=bN+e;bv.innerHTML=bQ;bV=bv.firstChild;bW=bV.firstChild;bO=bV.nextSibling.firstChild.firstChild;bP={doesNotAddBorder:(bW.offsetTop!==5),doesAddBorderForTableAndCells:(bO.offsetTop===5)};bW.style.position="fixed";bW.style.top="20px";bP.fixedPosition=(bW.offsetTop===20||bW.offsetTop===15);bW.style.position=bW.style.top="";bV.style.overflow="hidden";bV.style.position="relative";bP.subtractsBorderForOverflowNotVisible=(bW.offsetTop===-5);bP.doesNotIncludeMarginInBodyOffset=(bS.offsetTop!==bL);if(bd.getComputedStyle){bv.style.marginTop="1%";bI.pixelMargin=(bd.getComputedStyle(bv,null)||{marginTop:0}).marginTop!=="1%"}if(typeof bM.style.zoom!=="undefined"){bM.style.zoom=1}bS.removeChild(bM);bR=bv=bM=null;b.extend(bI,bP)});return bI})();var aT=/^(?:\{.*\}|\[.*\])$/,aA=/([A-Z])/g;b.extend({cache:{},uuid:0,expando:"jQuery"+(b.fn.jquery+Math.random()).replace(/\D/g,""),noData:{embed:true,object:"clsid:D27CDB6E-AE6D-11cf-96B8-444553540000",applet:true},hasData:function(e){e=e.nodeType?b.cache[e[b.expando]]:e[b.expando];return !!e&&!S(e)},data:function(bx,bv,bz,by){if(!b.acceptData(bx)){return}var bG,bA,bD,bE=b.expando,bC=typeof bv==="string",bF=bx.nodeType,e=bF?b.cache:bx,bw=bF?bx[bE]:bx[bE]&&bE,bB=bv==="events";if((!bw||!e[bw]||(!bB&&!by&&!e[bw].data))&&bC&&bz===L){return}if(!bw){if(bF){bx[bE]=bw=++b.uuid}else{bw=bE}}if(!e[bw]){e[bw]={};if(!bF){e[bw].toJSON=b.noop}}if(typeof bv==="object"||typeof bv==="function"){if(by){e[bw]=b.extend(e[bw],bv)}else{e[bw].data=b.extend(e[bw].data,bv)}}bG=bA=e[bw];if(!by){if(!bA.data){bA.data={}}bA=bA.data}if(bz!==L){bA[b.camelCase(bv)]=bz}if(bB&&!bA[bv]){return bG.events}if(bC){bD=bA[bv];if(bD==null){bD=bA[b.camelCase(bv)]}}else{bD=bA}return bD},removeData:function(bx,bv,by){if(!b.acceptData(bx)){return}var bB,bA,bz,bC=b.expando,bD=bx.nodeType,e=bD?b.cache:bx,bw=bD?bx[bC]:bC;if(!e[bw]){return}if(bv){bB=by?e[bw]:e[bw].data;if(bB){if(!b.isArray(bv)){if(bv in bB){bv=[bv]}else{bv=b.camelCase(bv);if(bv in bB){bv=[bv]}else{bv=bv.split(" ")}}}for(bA=0,bz=bv.length;bA1,null,false)},removeData:function(e){return this.each(function(){b.removeData(this,e)})}});function a6(bx,bw,by){if(by===L&&bx.nodeType===1){var bv="data-"+bw.replace(aA,"-$1").toLowerCase();by=bx.getAttribute(bv);if(typeof by==="string"){try{by=by==="true"?true:by==="false"?false:by==="null"?null:b.isNumeric(by)?+by:aT.test(by)?b.parseJSON(by):by}catch(bz){}b.data(bx,bw,by)}else{by=L}}return by}function S(bv){for(var e in bv){if(e==="data"&&b.isEmptyObject(bv[e])){continue}if(e!=="toJSON"){return false}}return true}function bj(by,bx,bA){var bw=bx+"defer",bv=bx+"queue",e=bx+"mark",bz=b._data(by,bw);if(bz&&(bA==="queue"||!b._data(by,bv))&&(bA==="mark"||!b._data(by,e))){setTimeout(function(){if(!b._data(by,bv)&&!b._data(by,e)){b.removeData(by,bw,true);bz.fire()}},0)}}b.extend({_mark:function(bv,e){if(bv){e=(e||"fx")+"mark";b._data(bv,e,(b._data(bv,e)||0)+1)}},_unmark:function(by,bx,bv){if(by!==true){bv=bx;bx=by;by=false}if(bx){bv=bv||"fx";var e=bv+"mark",bw=by?0:((b._data(bx,e)||1)-1);if(bw){b._data(bx,e,bw)}else{b.removeData(bx,e,true);bj(bx,bv,"mark")}}},queue:function(bv,e,bx){var bw;if(bv){e=(e||"fx")+"queue";bw=b._data(bv,e);if(bx){if(!bw||b.isArray(bx)){bw=b._data(bv,e,b.makeArray(bx))}else{bw.push(bx)}}return bw||[]}},dequeue:function(by,bx){bx=bx||"fx";var bv=b.queue(by,bx),bw=bv.shift(),e={};if(bw==="inprogress"){bw=bv.shift()}if(bw){if(bx==="fx"){bv.unshift("inprogress")}b._data(by,bx+".run",e);bw.call(by,function(){b.dequeue(by,bx)},e)}if(!bv.length){b.removeData(by,bx+"queue "+bx+".run",true);bj(by,bx,"queue")}}});b.fn.extend({queue:function(e,bv){var bw=2;if(typeof e!=="string"){bv=e;e="fx";bw--}if(arguments.length1)},removeAttr:function(e){return this.each(function(){b.removeAttr(this,e)})},prop:function(e,bv){return b.access(this,b.prop,e,bv,arguments.length>1)},removeProp:function(e){e=b.propFix[e]||e;return this.each(function(){try{this[e]=L;delete this[e]}catch(bv){}})},addClass:function(by){var bA,bw,bv,bx,bz,bB,e;if(b.isFunction(by)){return this.each(function(bC){b(this).addClass(by.call(this,bC,this.className))})}if(by&&typeof by==="string"){bA=by.split(ag);for(bw=0,bv=this.length;bw-1){return true}}return false},val:function(bx){var e,bv,by,bw=this[0];if(!arguments.length){if(bw){e=b.valHooks[bw.type]||b.valHooks[bw.nodeName.toLowerCase()];if(e&&"get" in e&&(bv=e.get(bw,"value"))!==L){return bv}bv=bw.value;return typeof bv==="string"?bv.replace(aV,""):bv==null?"":bv}return}by=b.isFunction(bx);return this.each(function(bA){var bz=b(this),bB;if(this.nodeType!==1){return}if(by){bB=bx.call(this,bA,bz.val())}else{bB=bx}if(bB==null){bB=""}else{if(typeof bB==="number"){bB+=""}else{if(b.isArray(bB)){bB=b.map(bB,function(bC){return bC==null?"":bC+""})}}}e=b.valHooks[this.type]||b.valHooks[this.nodeName.toLowerCase()];if(!e||!("set" in e)||e.set(this,bB,"value")===L){this.value=bB}})}});b.extend({valHooks:{option:{get:function(e){var bv=e.attributes.value;return !bv||bv.specified?e.value:e.text}},select:{get:function(e){var bA,bv,bz,bx,by=e.selectedIndex,bB=[],bC=e.options,bw=e.type==="select-one";if(by<0){return null}bv=bw?by:0;bz=bw?by+1:bC.length;for(;bv=0});if(!e.length){bv.selectedIndex=-1}return e}}},attrFn:{val:true,css:true,html:true,text:true,data:true,width:true,height:true,offset:true},attr:function(bA,bx,bB,bz){var bw,e,by,bv=bA.nodeType;if(!bA||bv===3||bv===8||bv===2){return}if(bz&&bx in b.attrFn){return b(bA)[bx](bB)}if(typeof bA.getAttribute==="undefined"){return b.prop(bA,bx,bB)}by=bv!==1||!b.isXMLDoc(bA);if(by){bx=bx.toLowerCase();e=b.attrHooks[bx]||(ao.test(bx)?aZ:bf)}if(bB!==L){if(bB===null){b.removeAttr(bA,bx);return}else{if(e&&"set" in e&&by&&(bw=e.set(bA,bB,bx))!==L){return bw}else{bA.setAttribute(bx,""+bB);return bB}}}else{if(e&&"get" in e&&by&&(bw=e.get(bA,bx))!==null){return bw}else{bw=bA.getAttribute(bx);return bw===null?L:bw}}},removeAttr:function(by,bA){var bz,bB,bw,e,bv,bx=0;if(bA&&by.nodeType===1){bB=bA.toLowerCase().split(ag);e=bB.length;for(;bx=0)}}})});var be=/^(?:textarea|input|select)$/i,n=/^([^\.]*)?(?:\.(.+))?$/,J=/(?:^|\s)hover(\.\S+)?\b/,aP=/^key/,bg=/^(?:mouse|contextmenu)|click/,T=/^(?:focusinfocus|focusoutblur)$/,U=/^(\w*)(?:#([\w\-]+))?(?:\.([\w\-]+))?$/,Y=function(e){var bv=U.exec(e);if(bv){bv[1]=(bv[1]||"").toLowerCase();bv[3]=bv[3]&&new RegExp("(?:^|\\s)"+bv[3]+"(?:\\s|$)")}return bv},j=function(bw,e){var bv=bw.attributes||{};return((!e[1]||bw.nodeName.toLowerCase()===e[1])&&(!e[2]||(bv.id||{}).value===e[2])&&(!e[3]||e[3].test((bv["class"]||{}).value)))},bt=function(e){return b.event.special.hover?e:e.replace(J,"mouseenter$1 mouseleave$1")};b.event={add:function(bx,bC,bJ,bA,by){var bD,bB,bK,bI,bH,bF,e,bG,bv,bz,bw,bE;if(bx.nodeType===3||bx.nodeType===8||!bC||!bJ||!(bD=b._data(bx))){return}if(bJ.handler){bv=bJ;bJ=bv.handler;by=bv.selector}if(!bJ.guid){bJ.guid=b.guid++}bK=bD.events;if(!bK){bD.events=bK={}}bB=bD.handle;if(!bB){bD.handle=bB=function(bL){return typeof b!=="undefined"&&(!bL||b.event.triggered!==bL.type)?b.event.dispatch.apply(bB.elem,arguments):L};bB.elem=bx}bC=b.trim(bt(bC)).split(" ");for(bI=0;bI=0){bG=bG.slice(0,-1);bw=true}if(bG.indexOf(".")>=0){bx=bG.split(".");bG=bx.shift();bx.sort()}if((!bA||b.event.customEvent[bG])&&!b.event.global[bG]){return}bv=typeof bv==="object"?bv[b.expando]?bv:new b.Event(bG,bv):new b.Event(bG);bv.type=bG;bv.isTrigger=true;bv.exclusive=bw;bv.namespace=bx.join(".");bv.namespace_re=bv.namespace?new RegExp("(^|\\.)"+bx.join("\\.(?:.*\\.)?")+"(\\.|$)"):null;by=bG.indexOf(":")<0?"on"+bG:"";if(!bA){e=b.cache;for(bC in e){if(e[bC].events&&e[bC].events[bG]){b.event.trigger(bv,bD,e[bC].handle.elem,true)}}return}bv.result=L;if(!bv.target){bv.target=bA}bD=bD!=null?b.makeArray(bD):[];bD.unshift(bv);bF=b.event.special[bG]||{};if(bF.trigger&&bF.trigger.apply(bA,bD)===false){return}bB=[[bA,bF.bindType||bG]];if(!bJ&&!bF.noBubble&&!b.isWindow(bA)){bI=bF.delegateType||bG;bH=T.test(bI+bG)?bA:bA.parentNode;bz=null;for(;bH;bH=bH.parentNode){bB.push([bH,bI]);bz=bH}if(bz&&bz===bA.ownerDocument){bB.push([bz.defaultView||bz.parentWindow||bd,bI])}}for(bC=0;bCbC){bv.push({elem:this,matches:bD.slice(bC)})}for(bJ=0;bJ0?this.on(e,null,bx,bw):this.trigger(e)};if(b.attrFn){b.attrFn[e]=true}if(aP.test(e)){b.event.fixHooks[e]=b.event.keyHooks}if(bg.test(e)){b.event.fixHooks[e]=b.event.mouseHooks}}); +/*! + * Sizzle CSS Selector Engine + * Copyright 2011, The Dojo Foundation + * Released under the MIT, BSD, and GPL Licenses. + * More information: http://sizzlejs.com/ + */ +(function(){var bH=/((?:\((?:\([^()]+\)|[^()]+)+\)|\[(?:\[[^\[\]]*\]|['"][^'"]*['"]|[^\[\]'"]+)+\]|\\.|[^ >+~,(\[\\]+)+|[>+~])(\s*,\s*)?((?:.|\r|\n)*)/g,bC="sizcache"+(Math.random()+"").replace(".",""),bI=0,bL=Object.prototype.toString,bB=false,bA=true,bK=/\\/g,bO=/\r\n/g,bQ=/\W/;[0,0].sort(function(){bA=false;return 0});var by=function(bV,e,bY,bZ){bY=bY||[];e=e||av;var b1=e;if(e.nodeType!==1&&e.nodeType!==9){return[]}if(!bV||typeof bV!=="string"){return bY}var bS,b3,b6,bR,b2,b5,b4,bX,bU=true,bT=by.isXML(e),bW=[],b0=bV;do{bH.exec("");bS=bH.exec(b0);if(bS){b0=bS[3];bW.push(bS[1]);if(bS[2]){bR=bS[3];break}}}while(bS);if(bW.length>1&&bD.exec(bV)){if(bW.length===2&&bE.relative[bW[0]]){b3=bM(bW[0]+bW[1],e,bZ)}else{b3=bE.relative[bW[0]]?[e]:by(bW.shift(),e);while(bW.length){bV=bW.shift();if(bE.relative[bV]){bV+=bW.shift()}b3=bM(bV,b3,bZ)}}}else{if(!bZ&&bW.length>1&&e.nodeType===9&&!bT&&bE.match.ID.test(bW[0])&&!bE.match.ID.test(bW[bW.length-1])){b2=by.find(bW.shift(),e,bT);e=b2.expr?by.filter(b2.expr,b2.set)[0]:b2.set[0]}if(e){b2=bZ?{expr:bW.pop(),set:bF(bZ)}:by.find(bW.pop(),bW.length===1&&(bW[0]==="~"||bW[0]==="+")&&e.parentNode?e.parentNode:e,bT);b3=b2.expr?by.filter(b2.expr,b2.set):b2.set;if(bW.length>0){b6=bF(b3)}else{bU=false}while(bW.length){b5=bW.pop();b4=b5;if(!bE.relative[b5]){b5=""}else{b4=bW.pop()}if(b4==null){b4=e}bE.relative[b5](b6,b4,bT)}}else{b6=bW=[]}}if(!b6){b6=b3}if(!b6){by.error(b5||bV)}if(bL.call(b6)==="[object Array]"){if(!bU){bY.push.apply(bY,b6)}else{if(e&&e.nodeType===1){for(bX=0;b6[bX]!=null;bX++){if(b6[bX]&&(b6[bX]===true||b6[bX].nodeType===1&&by.contains(e,b6[bX]))){bY.push(b3[bX])}}}else{for(bX=0;b6[bX]!=null;bX++){if(b6[bX]&&b6[bX].nodeType===1){bY.push(b3[bX])}}}}}else{bF(b6,bY)}if(bR){by(bR,b1,bY,bZ);by.uniqueSort(bY)}return bY};by.uniqueSort=function(bR){if(bJ){bB=bA;bR.sort(bJ);if(bB){for(var e=1;e0};by.find=function(bX,e,bY){var bW,bS,bU,bT,bV,bR;if(!bX){return[]}for(bS=0,bU=bE.order.length;bS":function(bW,bR){var bV,bU=typeof bR==="string",bS=0,e=bW.length;if(bU&&!bQ.test(bR)){bR=bR.toLowerCase();for(;bS=0)){if(!bS){e.push(bV)}}else{if(bS){bR[bU]=false}}}}return false},ID:function(e){return e[1].replace(bK,"")},TAG:function(bR,e){return bR[1].replace(bK,"").toLowerCase()},CHILD:function(e){if(e[1]==="nth"){if(!e[2]){by.error(e[0])}e[2]=e[2].replace(/^\+|\s*/g,"");var bR=/(-?)(\d*)(?:n([+\-]?\d*))?/.exec(e[2]==="even"&&"2n"||e[2]==="odd"&&"2n+1"||!/\D/.test(e[2])&&"0n+"+e[2]||e[2]);e[2]=(bR[1]+(bR[2]||1))-0;e[3]=bR[3]-0}else{if(e[2]){by.error(e[0])}}e[0]=bI++;return e},ATTR:function(bU,bR,bS,e,bV,bW){var bT=bU[1]=bU[1].replace(bK,"");if(!bW&&bE.attrMap[bT]){bU[1]=bE.attrMap[bT]}bU[4]=(bU[4]||bU[5]||"").replace(bK,"");if(bU[2]==="~="){bU[4]=" "+bU[4]+" "}return bU},PSEUDO:function(bU,bR,bS,e,bV){if(bU[1]==="not"){if((bH.exec(bU[3])||"").length>1||/^\w/.test(bU[3])){bU[3]=by(bU[3],null,null,bR)}else{var bT=by.filter(bU[3],bR,bS,true^bV);if(!bS){e.push.apply(e,bT)}return false}}else{if(bE.match.POS.test(bU[0])||bE.match.CHILD.test(bU[0])){return true}}return bU},POS:function(e){e.unshift(true);return e}},filters:{enabled:function(e){return e.disabled===false&&e.type!=="hidden"},disabled:function(e){return e.disabled===true},checked:function(e){return e.checked===true},selected:function(e){if(e.parentNode){e.parentNode.selectedIndex}return e.selected===true},parent:function(e){return !!e.firstChild},empty:function(e){return !e.firstChild},has:function(bS,bR,e){return !!by(e[3],bS).length},header:function(e){return(/h\d/i).test(e.nodeName)},text:function(bS){var e=bS.getAttribute("type"),bR=bS.type;return bS.nodeName.toLowerCase()==="input"&&"text"===bR&&(e===bR||e===null)},radio:function(e){return e.nodeName.toLowerCase()==="input"&&"radio"===e.type},checkbox:function(e){return e.nodeName.toLowerCase()==="input"&&"checkbox"===e.type},file:function(e){return e.nodeName.toLowerCase()==="input"&&"file"===e.type},password:function(e){return e.nodeName.toLowerCase()==="input"&&"password"===e.type},submit:function(bR){var e=bR.nodeName.toLowerCase();return(e==="input"||e==="button")&&"submit"===bR.type},image:function(e){return e.nodeName.toLowerCase()==="input"&&"image"===e.type},reset:function(bR){var e=bR.nodeName.toLowerCase();return(e==="input"||e==="button")&&"reset"===bR.type},button:function(bR){var e=bR.nodeName.toLowerCase();return e==="input"&&"button"===bR.type||e==="button"},input:function(e){return(/input|select|textarea|button/i).test(e.nodeName)},focus:function(e){return e===e.ownerDocument.activeElement}},setFilters:{first:function(bR,e){return e===0},last:function(bS,bR,e,bT){return bR===bT.length-1},even:function(bR,e){return e%2===0},odd:function(bR,e){return e%2===1},lt:function(bS,bR,e){return bRe[3]-0},nth:function(bS,bR,e){return e[3]-0===bR},eq:function(bS,bR,e){return e[3]-0===bR}},filter:{PSEUDO:function(bS,bX,bW,bY){var e=bX[1],bR=bE.filters[e];if(bR){return bR(bS,bW,bX,bY)}else{if(e==="contains"){return(bS.textContent||bS.innerText||bw([bS])||"").indexOf(bX[3])>=0}else{if(e==="not"){var bT=bX[3];for(var bV=0,bU=bT.length;bV=0)}}},ID:function(bR,e){return bR.nodeType===1&&bR.getAttribute("id")===e},TAG:function(bR,e){return(e==="*"&&bR.nodeType===1)||!!bR.nodeName&&bR.nodeName.toLowerCase()===e},CLASS:function(bR,e){return(" "+(bR.className||bR.getAttribute("class"))+" ").indexOf(e)>-1},ATTR:function(bV,bT){var bS=bT[1],e=by.attr?by.attr(bV,bS):bE.attrHandle[bS]?bE.attrHandle[bS](bV):bV[bS]!=null?bV[bS]:bV.getAttribute(bS),bW=e+"",bU=bT[2],bR=bT[4];return e==null?bU==="!=":!bU&&by.attr?e!=null:bU==="="?bW===bR:bU==="*="?bW.indexOf(bR)>=0:bU==="~="?(" "+bW+" ").indexOf(bR)>=0:!bR?bW&&e!==false:bU==="!="?bW!==bR:bU==="^="?bW.indexOf(bR)===0:bU==="$="?bW.substr(bW.length-bR.length)===bR:bU==="|="?bW===bR||bW.substr(0,bR.length+1)===bR+"-":false},POS:function(bU,bR,bS,bV){var e=bR[2],bT=bE.setFilters[e];if(bT){return bT(bU,bS,bR,bV)}}}};var bD=bE.match.POS,bx=function(bR,e){return"\\"+(e-0+1)};for(var bz in bE.match){bE.match[bz]=new RegExp(bE.match[bz].source+(/(?![^\[]*\])(?![^\(]*\))/.source));bE.leftMatch[bz]=new RegExp(/(^(?:.|\r|\n)*?)/.source+bE.match[bz].source.replace(/\\(\d+)/g,bx))}bE.match.globalPOS=bD;var bF=function(bR,e){bR=Array.prototype.slice.call(bR,0);if(e){e.push.apply(e,bR);return e}return bR};try{Array.prototype.slice.call(av.documentElement.childNodes,0)[0].nodeType}catch(bP){bF=function(bU,bT){var bS=0,bR=bT||[];if(bL.call(bU)==="[object Array]"){Array.prototype.push.apply(bR,bU)}else{if(typeof bU.length==="number"){for(var e=bU.length;bS";e.insertBefore(bR,e.firstChild);if(av.getElementById(bS)){bE.find.ID=function(bU,bV,bW){if(typeof bV.getElementById!=="undefined"&&!bW){var bT=bV.getElementById(bU[1]);return bT?bT.id===bU[1]||typeof bT.getAttributeNode!=="undefined"&&bT.getAttributeNode("id").nodeValue===bU[1]?[bT]:L:[]}};bE.filter.ID=function(bV,bT){var bU=typeof bV.getAttributeNode!=="undefined"&&bV.getAttributeNode("id");return bV.nodeType===1&&bU&&bU.nodeValue===bT}}e.removeChild(bR);e=bR=null})();(function(){var e=av.createElement("div");e.appendChild(av.createComment(""));if(e.getElementsByTagName("*").length>0){bE.find.TAG=function(bR,bV){var bU=bV.getElementsByTagName(bR[1]);if(bR[1]==="*"){var bT=[];for(var bS=0;bU[bS];bS++){if(bU[bS].nodeType===1){bT.push(bU[bS])}}bU=bT}return bU}}e.innerHTML="";if(e.firstChild&&typeof e.firstChild.getAttribute!=="undefined"&&e.firstChild.getAttribute("href")!=="#"){bE.attrHandle.href=function(bR){return bR.getAttribute("href",2)}}e=null})();if(av.querySelectorAll){(function(){var e=by,bT=av.createElement("div"),bS="__sizzle__";bT.innerHTML="

";if(bT.querySelectorAll&&bT.querySelectorAll(".TEST").length===0){return}by=function(b4,bV,bZ,b3){bV=bV||av;if(!b3&&!by.isXML(bV)){var b2=/^(\w+$)|^\.([\w\-]+$)|^#([\w\-]+$)/.exec(b4);if(b2&&(bV.nodeType===1||bV.nodeType===9)){if(b2[1]){return bF(bV.getElementsByTagName(b4),bZ)}else{if(b2[2]&&bE.find.CLASS&&bV.getElementsByClassName){return bF(bV.getElementsByClassName(b2[2]),bZ)}}}if(bV.nodeType===9){if(b4==="body"&&bV.body){return bF([bV.body],bZ)}else{if(b2&&b2[3]){var bY=bV.getElementById(b2[3]);if(bY&&bY.parentNode){if(bY.id===b2[3]){return bF([bY],bZ)}}else{return bF([],bZ)}}}try{return bF(bV.querySelectorAll(b4),bZ)}catch(b0){}}else{if(bV.nodeType===1&&bV.nodeName.toLowerCase()!=="object"){var bW=bV,bX=bV.getAttribute("id"),bU=bX||bS,b6=bV.parentNode,b5=/^\s*[+~]/.test(b4);if(!bX){bV.setAttribute("id",bU)}else{bU=bU.replace(/'/g,"\\$&")}if(b5&&b6){bV=bV.parentNode}try{if(!b5||b6){return bF(bV.querySelectorAll("[id='"+bU+"'] "+b4),bZ)}}catch(b1){}finally{if(!bX){bW.removeAttribute("id")}}}}}return e(b4,bV,bZ,b3)};for(var bR in e){by[bR]=e[bR]}bT=null})()}(function(){var e=av.documentElement,bS=e.matchesSelector||e.mozMatchesSelector||e.webkitMatchesSelector||e.msMatchesSelector;if(bS){var bU=!bS.call(av.createElement("div"),"div"),bR=false;try{bS.call(av.documentElement,"[test!='']:sizzle")}catch(bT){bR=true}by.matchesSelector=function(bW,bY){bY=bY.replace(/\=\s*([^'"\]]*)\s*\]/g,"='$1']");if(!by.isXML(bW)){try{if(bR||!bE.match.PSEUDO.test(bY)&&!/!=/.test(bY)){var bV=bS.call(bW,bY);if(bV||!bU||bW.document&&bW.document.nodeType!==11){return bV}}}catch(bX){}}return by(bY,null,null,[bW]).length>0}}})();(function(){var e=av.createElement("div");e.innerHTML="
";if(!e.getElementsByClassName||e.getElementsByClassName("e").length===0){return}e.lastChild.className="e";if(e.getElementsByClassName("e").length===1){return}bE.order.splice(1,0,"CLASS");bE.find.CLASS=function(bR,bS,bT){if(typeof bS.getElementsByClassName!=="undefined"&&!bT){return bS.getElementsByClassName(bR[1])}};e=null})();function bv(bR,bW,bV,bZ,bX,bY){for(var bT=0,bS=bZ.length;bT0){bU=e;break}}}e=e[bR]}bZ[bT]=bU}}}if(av.documentElement.contains){by.contains=function(bR,e){return bR!==e&&(bR.contains?bR.contains(e):true)}}else{if(av.documentElement.compareDocumentPosition){by.contains=function(bR,e){return !!(bR.compareDocumentPosition(e)&16)}}else{by.contains=function(){return false}}}by.isXML=function(e){var bR=(e?e.ownerDocument||e:0).documentElement;return bR?bR.nodeName!=="HTML":false};var bM=function(bS,e,bW){var bV,bX=[],bU="",bY=e.nodeType?[e]:e;while((bV=bE.match.PSEUDO.exec(bS))){bU+=bV[0];bS=bS.replace(bE.match.PSEUDO,"")}bS=bE.relative[bS]?bS+"*":bS;for(var bT=0,bR=bY.length;bT0){for(bB=bA;bB=0:b.filter(e,this).length>0:this.filter(e).length>0)},closest:function(by,bx){var bv=[],bw,e,bz=this[0];if(b.isArray(by)){var bB=1;while(bz&&bz.ownerDocument&&bz!==bx){for(bw=0;bw-1:b.find.matchesSelector(bz,by)){bv.push(bz);break}else{bz=bz.parentNode;if(!bz||!bz.ownerDocument||bz===bx||bz.nodeType===11){break}}}}bv=bv.length>1?b.unique(bv):bv;return this.pushStack(bv,"closest",by)},index:function(e){if(!e){return(this[0]&&this[0].parentNode)?this.prevAll().length:-1}if(typeof e==="string"){return b.inArray(this[0],b(e))}return b.inArray(e.jquery?e[0]:e,this)},add:function(e,bv){var bx=typeof e==="string"?b(e,bv):b.makeArray(e&&e.nodeType?[e]:e),bw=b.merge(this.get(),bx);return this.pushStack(B(bx[0])||B(bw[0])?bw:b.unique(bw))},andSelf:function(){return this.add(this.prevObject)}});function B(e){return !e||!e.parentNode||e.parentNode.nodeType===11}b.each({parent:function(bv){var e=bv.parentNode;return e&&e.nodeType!==11?e:null},parents:function(e){return b.dir(e,"parentNode")},parentsUntil:function(bv,e,bw){return b.dir(bv,"parentNode",bw)},next:function(e){return b.nth(e,2,"nextSibling")},prev:function(e){return b.nth(e,2,"previousSibling")},nextAll:function(e){return b.dir(e,"nextSibling")},prevAll:function(e){return b.dir(e,"previousSibling")},nextUntil:function(bv,e,bw){return b.dir(bv,"nextSibling",bw)},prevUntil:function(bv,e,bw){return b.dir(bv,"previousSibling",bw)},siblings:function(e){return b.sibling((e.parentNode||{}).firstChild,e)},children:function(e){return b.sibling(e.firstChild)},contents:function(e){return b.nodeName(e,"iframe")?e.contentDocument||e.contentWindow.document:b.makeArray(e.childNodes)}},function(e,bv){b.fn[e]=function(by,bw){var bx=b.map(this,bv,by);if(!ab.test(e)){bw=by}if(bw&&typeof bw==="string"){bx=b.filter(bw,bx)}bx=this.length>1&&!ay[e]?b.unique(bx):bx;if((this.length>1||bb.test(bw))&&aq.test(e)){bx=bx.reverse()}return this.pushStack(bx,e,P.call(arguments).join(","))}});b.extend({filter:function(bw,e,bv){if(bv){bw=":not("+bw+")"}return e.length===1?b.find.matchesSelector(e[0],bw)?[e[0]]:[]:b.find.matches(bw,e)},dir:function(bw,bv,by){var e=[],bx=bw[bv];while(bx&&bx.nodeType!==9&&(by===L||bx.nodeType!==1||!b(bx).is(by))){if(bx.nodeType===1){e.push(bx)}bx=bx[bv]}return e},nth:function(by,e,bw,bx){e=e||1;var bv=0;for(;by;by=by[bw]){if(by.nodeType===1&&++bv===e){break}}return by},sibling:function(bw,bv){var e=[];for(;bw;bw=bw.nextSibling){if(bw.nodeType===1&&bw!==bv){e.push(bw)}}return e}});function aH(bx,bw,e){bw=bw||0;if(b.isFunction(bw)){return b.grep(bx,function(bz,by){var bA=!!bw.call(bz,by,bz);return bA===e})}else{if(bw.nodeType){return b.grep(bx,function(bz,by){return(bz===bw)===e})}else{if(typeof bw==="string"){var bv=b.grep(bx,function(by){return by.nodeType===1});if(bp.test(bw)){return b.filter(bw,bv,!e)}else{bw=b.filter(bw,bv)}}}}return b.grep(bx,function(bz,by){return(b.inArray(bz,bw)>=0)===e})}function a(e){var bw=aS.split("|"),bv=e.createDocumentFragment();if(bv.createElement){while(bw.length){bv.createElement(bw.pop())}}return bv}var aS="abbr|article|aside|audio|bdi|canvas|data|datalist|details|figcaption|figure|footer|header|hgroup|mark|meter|nav|output|progress|section|summary|time|video",ah=/ jQuery\d+="(?:\d+|null)"/g,ar=/^\s+/,R=/<(?!area|br|col|embed|hr|img|input|link|meta|param)(([\w:]+)[^>]*)\/>/ig,d=/<([\w:]+)/,v=/]","i"),o=/checked\s*(?:[^=]|=\s*.checked.)/i,bn=/\/(java|ecma)script/i,aO=/^\s*",""],legend:[1,"
","
"],thead:[1,"","
"],tr:[2,"","
"],td:[3,"","
"],col:[2,"","
"],area:[1,"",""],_default:[0,"",""]},ac=a(av);ax.optgroup=ax.option;ax.tbody=ax.tfoot=ax.colgroup=ax.caption=ax.thead;ax.th=ax.td;if(!b.support.htmlSerialize){ax._default=[1,"div
","
"]}b.fn.extend({text:function(e){return b.access(this,function(bv){return bv===L?b.text(this):this.empty().append((this[0]&&this[0].ownerDocument||av).createTextNode(bv))},null,e,arguments.length)},wrapAll:function(e){if(b.isFunction(e)){return this.each(function(bw){b(this).wrapAll(e.call(this,bw))})}if(this[0]){var bv=b(e,this[0].ownerDocument).eq(0).clone(true);if(this[0].parentNode){bv.insertBefore(this[0])}bv.map(function(){var bw=this;while(bw.firstChild&&bw.firstChild.nodeType===1){bw=bw.firstChild}return bw}).append(this)}return this},wrapInner:function(e){if(b.isFunction(e)){return this.each(function(bv){b(this).wrapInner(e.call(this,bv))})}return this.each(function(){var bv=b(this),bw=bv.contents();if(bw.length){bw.wrapAll(e)}else{bv.append(e)}})},wrap:function(e){var bv=b.isFunction(e);return this.each(function(bw){b(this).wrapAll(bv?e.call(this,bw):e)})},unwrap:function(){return this.parent().each(function(){if(!b.nodeName(this,"body")){b(this).replaceWith(this.childNodes)}}).end()},append:function(){return this.domManip(arguments,true,function(e){if(this.nodeType===1){this.appendChild(e)}})},prepend:function(){return this.domManip(arguments,true,function(e){if(this.nodeType===1){this.insertBefore(e,this.firstChild)}})},before:function(){if(this[0]&&this[0].parentNode){return this.domManip(arguments,false,function(bv){this.parentNode.insertBefore(bv,this)})}else{if(arguments.length){var e=b.clean(arguments);e.push.apply(e,this.toArray());return this.pushStack(e,"before",arguments)}}},after:function(){if(this[0]&&this[0].parentNode){return this.domManip(arguments,false,function(bv){this.parentNode.insertBefore(bv,this.nextSibling)})}else{if(arguments.length){var e=this.pushStack(this,"after",arguments);e.push.apply(e,b.clean(arguments));return e}}},remove:function(e,bx){for(var bv=0,bw;(bw=this[bv])!=null;bv++){if(!e||b.filter(e,[bw]).length){if(!bx&&bw.nodeType===1){b.cleanData(bw.getElementsByTagName("*"));b.cleanData([bw])}if(bw.parentNode){bw.parentNode.removeChild(bw)}}}return this},empty:function(){for(var e=0,bv;(bv=this[e])!=null;e++){if(bv.nodeType===1){b.cleanData(bv.getElementsByTagName("*"))}while(bv.firstChild){bv.removeChild(bv.firstChild)}}return this},clone:function(bv,e){bv=bv==null?false:bv;e=e==null?bv:e;return this.map(function(){return b.clone(this,bv,e)})},html:function(e){return b.access(this,function(by){var bx=this[0]||{},bw=0,bv=this.length;if(by===L){return bx.nodeType===1?bx.innerHTML.replace(ah,""):null}if(typeof by==="string"&&!ae.test(by)&&(b.support.leadingWhitespace||!ar.test(by))&&!ax[(d.exec(by)||["",""])[1].toLowerCase()]){by=by.replace(R,"<$1>");try{for(;bw1&&bw0?this.clone(true):this).get();b(bC[bA])[bv](by);bz=bz.concat(by)}return this.pushStack(bz,e,bC.selector)}}});function bh(e){if(typeof e.getElementsByTagName!=="undefined"){return e.getElementsByTagName("*")}else{if(typeof e.querySelectorAll!=="undefined"){return e.querySelectorAll("*")}else{return[]}}}function az(e){if(e.type==="checkbox"||e.type==="radio"){e.defaultChecked=e.checked}}function D(e){var bv=(e.nodeName||"").toLowerCase();if(bv==="input"){az(e)}else{if(bv!=="script"&&typeof e.getElementsByTagName!=="undefined"){b.grep(e.getElementsByTagName("input"),az)}}}function am(e){var bv=av.createElement("div");ac.appendChild(bv);bv.innerHTML=e.outerHTML;return bv.firstChild}b.extend({clone:function(by,bA,bw){var e,bv,bx,bz=b.support.html5Clone||b.isXMLDoc(by)||!ai.test("<"+by.nodeName+">")?by.cloneNode(true):am(by);if((!b.support.noCloneEvent||!b.support.noCloneChecked)&&(by.nodeType===1||by.nodeType===11)&&!b.isXMLDoc(by)){aj(by,bz);e=bh(by);bv=bh(bz);for(bx=0;e[bx];++bx){if(bv[bx]){aj(e[bx],bv[bx])}}}if(bA){s(by,bz);if(bw){e=bh(by);bv=bh(bz);for(bx=0;e[bx];++bx){s(e[bx],bv[bx])}}}e=bv=null;return bz},clean:function(bI,bw,bv,bx){var bA,bH,bD,bJ=[];bw=bw||av;if(typeof bw.createElement==="undefined"){bw=bw.ownerDocument||bw[0]&&bw[0].ownerDocument||av}for(var bE=0,bG;(bG=bI[bE])!=null;bE++){if(typeof bG==="number"){bG+=""}if(!bG){continue}if(typeof bG==="string"){if(!W.test(bG)){bG=bw.createTextNode(bG)}else{bG=bG.replace(R,"<$1>");var bN=(d.exec(bG)||["",""])[1].toLowerCase(),bz=ax[bN]||ax._default,bK=bz[0],bB=bw.createElement("div"),bL=ac.childNodes,bM;if(bw===av){ac.appendChild(bB)}else{a(bw).appendChild(bB)}bB.innerHTML=bz[1]+bG+bz[2];while(bK--){bB=bB.lastChild}if(!b.support.tbody){var by=v.test(bG),e=bN==="table"&&!by?bB.firstChild&&bB.firstChild.childNodes:bz[1]===""&&!by?bB.childNodes:[];for(bD=e.length-1;bD>=0;--bD){if(b.nodeName(e[bD],"tbody")&&!e[bD].childNodes.length){e[bD].parentNode.removeChild(e[bD])}}}if(!b.support.leadingWhitespace&&ar.test(bG)){bB.insertBefore(bw.createTextNode(ar.exec(bG)[0]),bB.firstChild)}bG=bB.childNodes;if(bB){bB.parentNode.removeChild(bB);if(bL.length>0){bM=bL[bL.length-1];if(bM&&bM.parentNode){bM.parentNode.removeChild(bM)}}}}}var bF;if(!b.support.appendChecked){if(bG[0]&&typeof(bF=bG.length)==="number"){for(bD=0;bD1)};b.extend({cssHooks:{opacity:{get:function(bw,bv){if(bv){var e=Z(bw,"opacity");return e===""?"1":e}else{return bw.style.opacity}}}},cssNumber:{fillOpacity:true,fontWeight:true,lineHeight:true,opacity:true,orphans:true,widows:true,zIndex:true,zoom:true},cssProps:{"float":b.support.cssFloat?"cssFloat":"styleFloat"},style:function(bx,bw,bD,by){if(!bx||bx.nodeType===3||bx.nodeType===8||!bx.style){return}var bB,bC,bz=b.camelCase(bw),bv=bx.style,bE=b.cssHooks[bz];bw=b.cssProps[bz]||bz;if(bD!==L){bC=typeof bD;if(bC==="string"&&(bB=I.exec(bD))){bD=(+(bB[1]+1)*+bB[2])+parseFloat(b.css(bx,bw));bC="number"}if(bD==null||bC==="number"&&isNaN(bD)){return}if(bC==="number"&&!b.cssNumber[bz]){bD+="px"}if(!bE||!("set" in bE)||(bD=bE.set(bx,bD))!==L){try{bv[bw]=bD}catch(bA){}}}else{if(bE&&"get" in bE&&(bB=bE.get(bx,false,by))!==L){return bB}return bv[bw]}},css:function(by,bx,bv){var bw,e;bx=b.camelCase(bx);e=b.cssHooks[bx];bx=b.cssProps[bx]||bx;if(bx==="cssFloat"){bx="float"}if(e&&"get" in e&&(bw=e.get(by,true,bv))!==L){return bw}else{if(Z){return Z(by,bx)}}},swap:function(by,bx,bz){var e={},bw,bv;for(bv in bx){e[bv]=by.style[bv];by.style[bv]=bx[bv]}bw=bz.call(by);for(bv in bx){by.style[bv]=e[bv]}return bw}});b.curCSS=b.css;if(av.defaultView&&av.defaultView.getComputedStyle){aJ=function(bA,bw){var bv,bz,e,by,bx=bA.style;bw=bw.replace(y,"-$1").toLowerCase();if((bz=bA.ownerDocument.defaultView)&&(e=bz.getComputedStyle(bA,null))){bv=e.getPropertyValue(bw);if(bv===""&&!b.contains(bA.ownerDocument.documentElement,bA)){bv=b.style(bA,bw)}}if(!b.support.pixelMargin&&e&&aE.test(bw)&&a1.test(bv)){by=bx.width;bx.width=bv;bv=e.width;bx.width=by}return bv}}if(av.documentElement.currentStyle){aY=function(bz,bw){var bA,e,by,bv=bz.currentStyle&&bz.currentStyle[bw],bx=bz.style;if(bv==null&&bx&&(by=bx[bw])){bv=by}if(a1.test(bv)){bA=bx.left;e=bz.runtimeStyle&&bz.runtimeStyle.left;if(e){bz.runtimeStyle.left=bz.currentStyle.left}bx.left=bw==="fontSize"?"1em":bv;bv=bx.pixelLeft+"px";bx.left=bA;if(e){bz.runtimeStyle.left=e}}return bv===""?"auto":bv}}Z=aJ||aY;function af(by,bw,bv){var bz=bw==="width"?by.offsetWidth:by.offsetHeight,bx=bw==="width"?1:0,e=4;if(bz>0){if(bv!=="border"){for(;bx=1&&b.trim(bw.replace(al,""))===""){bx.removeAttribute("filter");if(bv&&!bv.filter){return}}bx.filter=al.test(bw)?bw.replace(al,e):bw+" "+e}}}b(function(){if(!b.support.reliableMarginRight){b.cssHooks.marginRight={get:function(bv,e){return b.swap(bv,{display:"inline-block"},function(){if(e){return Z(bv,"margin-right")}else{return bv.style.marginRight}})}}}});if(b.expr&&b.expr.filters){b.expr.filters.hidden=function(bw){var bv=bw.offsetWidth,e=bw.offsetHeight;return(bv===0&&e===0)||(!b.support.reliableHiddenOffsets&&((bw.style&&bw.style.display)||b.css(bw,"display"))==="none")};b.expr.filters.visible=function(e){return !b.expr.filters.hidden(e)}}b.each({margin:"",padding:"",border:"Width"},function(e,bv){b.cssHooks[e+bv]={expand:function(by){var bx,bz=typeof by==="string"?by.split(" "):[by],bw={};for(bx=0;bx<4;bx++){bw[e+G[bx]+bv]=bz[bx]||bz[bx-2]||bz[0]}return bw}}});var k=/%20/g,ap=/\[\]$/,bs=/\r?\n/g,bq=/#.*$/,aD=/^(.*?):[ \t]*([^\r\n]*)\r?$/mg,a0=/^(?:color|date|datetime|datetime-local|email|hidden|month|number|password|range|search|tel|text|time|url|week)$/i,aN=/^(?:about|app|app\-storage|.+\-extension|file|res|widget):$/,aR=/^(?:GET|HEAD)$/,c=/^\/\//,M=/\?/,a7=/)<[^<]*)*<\/script>/gi,p=/^(?:select|textarea)/i,h=/\s+/,br=/([?&])_=[^&]*/,K=/^([\w\+\.\-]+:)(?:\/\/([^\/?#:]*)(?::(\d+))?)?/,z=b.fn.load,aa={},q={},aF,r,aW=["*/"]+["*"];try{aF=bm.href}catch(aw){aF=av.createElement("a");aF.href="";aF=aF.href}r=K.exec(aF.toLowerCase())||[];function f(e){return function(by,bA){if(typeof by!=="string"){bA=by;by="*"}if(b.isFunction(bA)){var bx=by.toLowerCase().split(h),bw=0,bz=bx.length,bv,bB,bC;for(;bw=0){var e=bw.slice(by,bw.length);bw=bw.slice(0,by)}var bx="GET";if(bz){if(b.isFunction(bz)){bA=bz;bz=L}else{if(typeof bz==="object"){bz=b.param(bz,b.ajaxSettings.traditional);bx="POST"}}}var bv=this;b.ajax({url:bw,type:bx,dataType:"html",data:bz,complete:function(bC,bB,bD){bD=bC.responseText;if(bC.isResolved()){bC.done(function(bE){bD=bE});bv.html(e?b("
").append(bD.replace(a7,"")).find(e):bD)}if(bA){bv.each(bA,[bD,bB,bC])}}});return this},serialize:function(){return b.param(this.serializeArray())},serializeArray:function(){return this.map(function(){return this.elements?b.makeArray(this.elements):this}).filter(function(){return this.name&&!this.disabled&&(this.checked||p.test(this.nodeName)||a0.test(this.type))}).map(function(e,bv){var bw=b(this).val();return bw==null?null:b.isArray(bw)?b.map(bw,function(by,bx){return{name:bv.name,value:by.replace(bs,"\r\n")}}):{name:bv.name,value:bw.replace(bs,"\r\n")}}).get()}});b.each("ajaxStart ajaxStop ajaxComplete ajaxError ajaxSuccess ajaxSend".split(" "),function(e,bv){b.fn[bv]=function(bw){return this.on(bv,bw)}});b.each(["get","post"],function(e,bv){b[bv]=function(bw,by,bz,bx){if(b.isFunction(by)){bx=bx||bz;bz=by;by=L}return b.ajax({type:bv,url:bw,data:by,success:bz,dataType:bx})}});b.extend({getScript:function(e,bv){return b.get(e,L,bv,"script")},getJSON:function(e,bv,bw){return b.get(e,bv,bw,"json")},ajaxSetup:function(bv,e){if(e){an(bv,b.ajaxSettings)}else{e=bv;bv=b.ajaxSettings}an(bv,e);return bv},ajaxSettings:{url:aF,isLocal:aN.test(r[1]),global:true,type:"GET",contentType:"application/x-www-form-urlencoded; charset=UTF-8",processData:true,async:true,accepts:{xml:"application/xml, text/xml",html:"text/html",text:"text/plain",json:"application/json, text/javascript","*":aW},contents:{xml:/xml/,html:/html/,json:/json/},responseFields:{xml:"responseXML",text:"responseText"},converters:{"* text":bd.String,"text html":true,"text json":b.parseJSON,"text xml":b.parseXML},flatOptions:{context:true,url:true}},ajaxPrefilter:f(aa),ajaxTransport:f(q),ajax:function(bz,bx){if(typeof bz==="object"){bx=bz;bz=L}bx=bx||{};var bD=b.ajaxSetup({},bx),bS=bD.context||bD,bG=bS!==bD&&(bS.nodeType||bS instanceof b)?b(bS):b.event,bR=b.Deferred(),bN=b.Callbacks("once memory"),bB=bD.statusCode||{},bC,bH={},bO={},bQ,by,bL,bE,bI,bA=0,bw,bK,bJ={readyState:0,setRequestHeader:function(bT,bU){if(!bA){var e=bT.toLowerCase();bT=bO[e]=bO[e]||bT;bH[bT]=bU}return this},getAllResponseHeaders:function(){return bA===2?bQ:null},getResponseHeader:function(bT){var e;if(bA===2){if(!by){by={};while((e=aD.exec(bQ))){by[e[1].toLowerCase()]=e[2]}}e=by[bT.toLowerCase()]}return e===L?null:e},overrideMimeType:function(e){if(!bA){bD.mimeType=e}return this},abort:function(e){e=e||"abort";if(bL){bL.abort(e)}bF(0,e);return this}};function bF(bZ,bU,b0,bW){if(bA===2){return}bA=2;if(bE){clearTimeout(bE)}bL=L;bQ=bW||"";bJ.readyState=bZ>0?4:0;var bT,b4,b3,bX=bU,bY=b0?bk(bD,bJ,b0):L,bV,b2;if(bZ>=200&&bZ<300||bZ===304){if(bD.ifModified){if((bV=bJ.getResponseHeader("Last-Modified"))){b.lastModified[bC]=bV}if((b2=bJ.getResponseHeader("Etag"))){b.etag[bC]=b2}}if(bZ===304){bX="notmodified";bT=true}else{try{b4=F(bD,bY);bX="success";bT=true}catch(b1){bX="parsererror";b3=b1}}}else{b3=bX;if(!bX||bZ){bX="error";if(bZ<0){bZ=0}}}bJ.status=bZ;bJ.statusText=""+(bU||bX);if(bT){bR.resolveWith(bS,[b4,bX,bJ])}else{bR.rejectWith(bS,[bJ,bX,b3])}bJ.statusCode(bB);bB=L;if(bw){bG.trigger("ajax"+(bT?"Success":"Error"),[bJ,bD,bT?b4:b3])}bN.fireWith(bS,[bJ,bX]);if(bw){bG.trigger("ajaxComplete",[bJ,bD]);if(!(--b.active)){b.event.trigger("ajaxStop")}}}bR.promise(bJ);bJ.success=bJ.done;bJ.error=bJ.fail;bJ.complete=bN.add;bJ.statusCode=function(bT){if(bT){var e;if(bA<2){for(e in bT){bB[e]=[bB[e],bT[e]]}}else{e=bT[bJ.status];bJ.then(e,e)}}return this};bD.url=((bz||bD.url)+"").replace(bq,"").replace(c,r[1]+"//");bD.dataTypes=b.trim(bD.dataType||"*").toLowerCase().split(h);if(bD.crossDomain==null){bI=K.exec(bD.url.toLowerCase());bD.crossDomain=!!(bI&&(bI[1]!=r[1]||bI[2]!=r[2]||(bI[3]||(bI[1]==="http:"?80:443))!=(r[3]||(r[1]==="http:"?80:443))))}if(bD.data&&bD.processData&&typeof bD.data!=="string"){bD.data=b.param(bD.data,bD.traditional)}aX(aa,bD,bx,bJ);if(bA===2){return false}bw=bD.global;bD.type=bD.type.toUpperCase();bD.hasContent=!aR.test(bD.type);if(bw&&b.active++===0){b.event.trigger("ajaxStart")}if(!bD.hasContent){if(bD.data){bD.url+=(M.test(bD.url)?"&":"?")+bD.data;delete bD.data}bC=bD.url;if(bD.cache===false){var bv=b.now(),bP=bD.url.replace(br,"$1_="+bv);bD.url=bP+((bP===bD.url)?(M.test(bD.url)?"&":"?")+"_="+bv:"")}}if(bD.data&&bD.hasContent&&bD.contentType!==false||bx.contentType){bJ.setRequestHeader("Content-Type",bD.contentType)}if(bD.ifModified){bC=bC||bD.url;if(b.lastModified[bC]){bJ.setRequestHeader("If-Modified-Since",b.lastModified[bC])}if(b.etag[bC]){bJ.setRequestHeader("If-None-Match",b.etag[bC])}}bJ.setRequestHeader("Accept",bD.dataTypes[0]&&bD.accepts[bD.dataTypes[0]]?bD.accepts[bD.dataTypes[0]]+(bD.dataTypes[0]!=="*"?", "+aW+"; q=0.01":""):bD.accepts["*"]);for(bK in bD.headers){bJ.setRequestHeader(bK,bD.headers[bK])}if(bD.beforeSend&&(bD.beforeSend.call(bS,bJ,bD)===false||bA===2)){bJ.abort();return false}for(bK in {success:1,error:1,complete:1}){bJ[bK](bD[bK])}bL=aX(q,bD,bx,bJ);if(!bL){bF(-1,"No Transport")}else{bJ.readyState=1;if(bw){bG.trigger("ajaxSend",[bJ,bD])}if(bD.async&&bD.timeout>0){bE=setTimeout(function(){bJ.abort("timeout")},bD.timeout)}try{bA=1;bL.send(bH,bF)}catch(bM){if(bA<2){bF(-1,bM)}else{throw bM}}}return bJ},param:function(e,bw){var bv=[],by=function(bz,bA){bA=b.isFunction(bA)?bA():bA;bv[bv.length]=encodeURIComponent(bz)+"="+encodeURIComponent(bA)};if(bw===L){bw=b.ajaxSettings.traditional}if(b.isArray(e)||(e.jquery&&!b.isPlainObject(e))){b.each(e,function(){by(this.name,this.value)})}else{for(var bx in e){u(bx,e[bx],bw,by)}}return bv.join("&").replace(k,"+")}});function u(bw,by,bv,bx){if(b.isArray(by)){b.each(by,function(bA,bz){if(bv||ap.test(bw)){bx(bw,bz)}else{u(bw+"["+(typeof bz==="object"?bA:"")+"]",bz,bv,bx)}})}else{if(!bv&&b.type(by)==="object"){for(var e in by){u(bw+"["+e+"]",by[e],bv,bx)}}else{bx(bw,by)}}}b.extend({active:0,lastModified:{},etag:{}});function bk(bD,bC,bz){var bv=bD.contents,bB=bD.dataTypes,bw=bD.responseFields,by,bA,bx,e;for(bA in bw){if(bA in bz){bC[bw[bA]]=bz[bA]}}while(bB[0]==="*"){bB.shift();if(by===L){by=bD.mimeType||bC.getResponseHeader("content-type")}}if(by){for(bA in bv){if(bv[bA]&&bv[bA].test(by)){bB.unshift(bA);break}}}if(bB[0] in bz){bx=bB[0]}else{for(bA in bz){if(!bB[0]||bD.converters[bA+" "+bB[0]]){bx=bA;break}if(!e){e=bA}}bx=bx||e}if(bx){if(bx!==bB[0]){bB.unshift(bx)}return bz[bx]}}function F(bH,bz){if(bH.dataFilter){bz=bH.dataFilter(bz,bH.dataType)}var bD=bH.dataTypes,bG={},bA,bE,bw=bD.length,bB,bC=bD[0],bx,by,bF,bv,e;for(bA=1;bA=bw.duration+this.startTime){this.now=this.end;this.pos=this.state=1;this.update();bw.animatedProperties[this.prop]=true;for(bA in bw.animatedProperties){if(bw.animatedProperties[bA]!==true){e=false}}if(e){if(bw.overflow!=null&&!b.support.shrinkWrapBlocks){b.each(["","X","Y"],function(bC,bD){bz.style["overflow"+bD]=bw.overflow[bC]})}if(bw.hide){b(bz).hide()}if(bw.hide||bw.show){for(bA in bw.animatedProperties){b.style(bz,bA,bw.orig[bA]);b.removeData(bz,"fxshow"+bA,true);b.removeData(bz,"toggle"+bA,true)}}bv=bw.complete;if(bv){bw.complete=false;bv.call(bz)}}return false}else{if(bw.duration==Infinity){this.now=bx}else{bB=bx-this.startTime;this.state=bB/bw.duration;this.pos=b.easing[bw.animatedProperties[this.prop]](this.state,bB,0,1,bw.duration);this.now=this.start+((this.end-this.start)*this.pos)}this.update()}return true}};b.extend(b.fx,{tick:function(){var bw,bv=b.timers,e=0;for(;e").appendTo(e),bw=bv.css("display");bv.remove();if(bw==="none"||bw===""){if(!ba){ba=av.createElement("iframe");ba.frameBorder=ba.width=ba.height=0}e.appendChild(ba);if(!m||!ba.createElement){m=(ba.contentWindow||ba.contentDocument).document;m.write((b.support.boxModel?"":"")+"");m.close()}bv=m.createElement(bx);m.body.appendChild(bv);bw=b.css(bv,"display");e.removeChild(ba)}Q[bx]=bw}return Q[bx]}var a8,V=/^t(?:able|d|h)$/i,ad=/^(?:body|html)$/i;if("getBoundingClientRect" in av.documentElement){a8=function(by,bH,bw,bB){try{bB=by.getBoundingClientRect()}catch(bF){}if(!bB||!b.contains(bw,by)){return bB?{top:bB.top,left:bB.left}:{top:0,left:0}}var bC=bH.body,bD=aL(bH),bA=bw.clientTop||bC.clientTop||0,bE=bw.clientLeft||bC.clientLeft||0,bv=bD.pageYOffset||b.support.boxModel&&bw.scrollTop||bC.scrollTop,bz=bD.pageXOffset||b.support.boxModel&&bw.scrollLeft||bC.scrollLeft,bG=bB.top+bv-bA,bx=bB.left+bz-bE;return{top:bG,left:bx}}}else{a8=function(bz,bE,bx){var bC,bw=bz.offsetParent,bv=bz,bA=bE.body,bB=bE.defaultView,e=bB?bB.getComputedStyle(bz,null):bz.currentStyle,bD=bz.offsetTop,by=bz.offsetLeft;while((bz=bz.parentNode)&&bz!==bA&&bz!==bx){if(b.support.fixedPosition&&e.position==="fixed"){break}bC=bB?bB.getComputedStyle(bz,null):bz.currentStyle;bD-=bz.scrollTop;by-=bz.scrollLeft;if(bz===bw){bD+=bz.offsetTop;by+=bz.offsetLeft;if(b.support.doesNotAddBorder&&!(b.support.doesAddBorderForTableAndCells&&V.test(bz.nodeName))){bD+=parseFloat(bC.borderTopWidth)||0;by+=parseFloat(bC.borderLeftWidth)||0}bv=bw;bw=bz.offsetParent}if(b.support.subtractsBorderForOverflowNotVisible&&bC.overflow!=="visible"){bD+=parseFloat(bC.borderTopWidth)||0;by+=parseFloat(bC.borderLeftWidth)||0}e=bC}if(e.position==="relative"||e.position==="static"){bD+=bA.offsetTop;by+=bA.offsetLeft}if(b.support.fixedPosition&&e.position==="fixed"){bD+=Math.max(bx.scrollTop,bA.scrollTop);by+=Math.max(bx.scrollLeft,bA.scrollLeft)}return{top:bD,left:by}}}b.fn.offset=function(e){if(arguments.length){return e===L?this:this.each(function(bx){b.offset.setOffset(this,e,bx)})}var bv=this[0],bw=bv&&bv.ownerDocument;if(!bw){return null}if(bv===bw.body){return b.offset.bodyOffset(bv)}return a8(bv,bw,bw.documentElement)};b.offset={bodyOffset:function(e){var bw=e.offsetTop,bv=e.offsetLeft;if(b.support.doesNotIncludeMarginInBodyOffset){bw+=parseFloat(b.css(e,"marginTop"))||0;bv+=parseFloat(b.css(e,"marginLeft"))||0}return{top:bw,left:bv}},setOffset:function(bx,bG,bA){var bB=b.css(bx,"position");if(bB==="static"){bx.style.position="relative"}var bz=b(bx),bv=bz.offset(),e=b.css(bx,"top"),bE=b.css(bx,"left"),bF=(bB==="absolute"||bB==="fixed")&&b.inArray("auto",[e,bE])>-1,bD={},bC={},bw,by;if(bF){bC=bz.position();bw=bC.top;by=bC.left}else{bw=parseFloat(e)||0;by=parseFloat(bE)||0}if(b.isFunction(bG)){bG=bG.call(bx,bA,bv)}if(bG.top!=null){bD.top=(bG.top-bv.top)+bw}if(bG.left!=null){bD.left=(bG.left-bv.left)+by}if("using" in bG){bG.using.call(bx,bD)}else{bz.css(bD)}}};b.fn.extend({position:function(){if(!this[0]){return null}var bw=this[0],bv=this.offsetParent(),bx=this.offset(),e=ad.test(bv[0].nodeName)?{top:0,left:0}:bv.offset();bx.top-=parseFloat(b.css(bw,"marginTop"))||0;bx.left-=parseFloat(b.css(bw,"marginLeft"))||0;e.top+=parseFloat(b.css(bv[0],"borderTopWidth"))||0;e.left+=parseFloat(b.css(bv[0],"borderLeftWidth"))||0;return{top:bx.top-e.top,left:bx.left-e.left}},offsetParent:function(){return this.map(function(){var e=this.offsetParent||av.body;while(e&&(!ad.test(e.nodeName)&&b.css(e,"position")==="static")){e=e.offsetParent}return e})}});b.each({scrollLeft:"pageXOffset",scrollTop:"pageYOffset"},function(bw,bv){var e=/Y/.test(bv);b.fn[bw]=function(bx){return b.access(this,function(by,bB,bA){var bz=aL(by);if(bA===L){return bz?(bv in bz)?bz[bv]:b.support.boxModel&&bz.document.documentElement[bB]||bz.document.body[bB]:by[bB]}if(bz){bz.scrollTo(!e?bA:b(bz).scrollLeft(),e?bA:b(bz).scrollTop())}else{by[bB]=bA}},bw,bx,arguments.length,null)}});function aL(e){return b.isWindow(e)?e:e.nodeType===9?e.defaultView||e.parentWindow:false}b.each({Height:"height",Width:"width"},function(bw,bx){var bv="client"+bw,e="scroll"+bw,by="offset"+bw;b.fn["inner"+bw]=function(){var bz=this[0];return bz?bz.style?parseFloat(b.css(bz,bx,"padding")):this[bx]():null};b.fn["outer"+bw]=function(bA){var bz=this[0];return bz?bz.style?parseFloat(b.css(bz,bx,bA?"margin":"border")):this[bx]():null};b.fn[bx]=function(bz){return b.access(this,function(bC,bB,bD){var bF,bE,bG,bA;if(b.isWindow(bC)){bF=bC.document;bE=bF.documentElement[bv];return b.support.boxModel&&bE||bF.body&&bF.body[bv]||bE}if(bC.nodeType===9){bF=bC.documentElement;if(bF[bv]>=bF[e]){return bF[bv]}return Math.max(bC.body[e],bF[e],bC.body[by],bF[by])}if(bD===L){bG=b.css(bC,bB);bA=parseFloat(bG);return b.isNumeric(bA)?bA:bG}b(bC).css(bB,bD)},bx,bz,arguments.length,null)}});bd.jQuery=bd.$=b;if(typeof define==="function"&&define.amd&&define.amd.jQuery){define("jquery",[],function(){return b})}})(window);/*! + * jQuery UI 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI + */ +(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*! + * jQuery UI Widget 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Widget + */ +(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*! + * jQuery UI Mouse 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(hl.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var o={width:parseInt(p.element.css("width"),10),height:parseInt(p.element.css("height"),10),top:parseInt(p.element.css("top"),10),left:parseInt(p.element.css("left"),10)};if(h&&h.length){c(h[0]).css({width:o.width,height:o.height})}p._updateCache(o);p._propagate("resize",i)}})}});c.ui.plugin.add("resizable","containment",{start:function(f,r){var t=c(this).data("resizable"),j=t.options,l=t.element;var g=j.containment,k=(g instanceof c)?g.get(0):(/parent/.test(g))?l.parent().get(0):g;if(!k){return}t.containerElement=c(k);if(/document/.test(g)||g==document){t.containerOffset={left:0,top:0};t.containerPosition={left:0,top:0};t.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var n=c(k),i=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){i[p]=b(n.css("padding"+o))});t.containerOffset=n.offset();t.containerPosition=n.position();t.containerSize={height:(n.innerHeight()-i[3]),width:(n.innerWidth()-i[1])};var q=t.containerOffset,e=t.containerSize.height,m=t.containerSize.width,h=(c.ui.hasScroll(k,"left")?k.scrollWidth:m),s=(c.ui.hasScroll(k)?k.scrollHeight:e);t.parentData={element:k,left:q.left,top:q.top,width:h,height:s}}},resize:function(g,q){var t=c(this).data("resizable"),i=t.options,f=t.containerSize,p=t.containerOffset,m=t.size,n=t.position,r=t._aspectRatio||g.shiftKey,e={top:0,left:0},h=t.containerElement;if(h[0]!=document&&(/static/).test(h.css("position"))){e=p}if(n.left<(t._helper?p.left:0)){t.size.width=t.size.width+(t._helper?(t.position.left-p.left):(t.position.left-e.left));if(r){t.size.height=t.size.width/i.aspectRatio}t.position.left=i.helper?p.left:0}if(n.top<(t._helper?p.top:0)){t.size.height=t.size.height+(t._helper?(t.position.top-p.top):t.position.top);if(r){t.size.width=t.size.height*i.aspectRatio}t.position.top=t._helper?p.top:0}t.offset.left=t.parentData.left+t.position.left;t.offset.top=t.parentData.top+t.position.top;var l=Math.abs((t._helper?t.offset.left-e.left:(t.offset.left-e.left))+t.sizeDiff.width),s=Math.abs((t._helper?t.offset.top-e.top:(t.offset.top-p.top))+t.sizeDiff.height);var k=t.containerElement.get(0)==t.element.parent().get(0),j=/relative|absolute/.test(t.containerElement.css("position"));if(k&&j){l-=t.parentData.left}if(l+t.size.width>=t.parentData.width){t.size.width=t.parentData.width-l;if(r){t.size.height=t.size.width/t.aspectRatio}}if(s+t.size.height>=t.parentData.height){t.size.height=t.parentData.height-s;if(r){t.size.width=t.size.height*t.aspectRatio}}},stop:function(f,n){var q=c(this).data("resizable"),g=q.options,l=q.position,m=q.containerOffset,e=q.containerPosition,i=q.containerElement;var j=c(q.helper),r=j.offset(),p=j.outerWidth()-q.sizeDiff.width,k=j.outerHeight()-q.sizeDiff.height;if(q._helper&&!g.animate&&(/relative/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}if(q._helper&&!g.animate&&(/static/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}}});c.ui.plugin.add("resizable","ghost",{start:function(g,h){var e=c(this).data("resizable"),i=e.options,f=e.size;e.ghost=e.originalElement.clone();e.ghost.css({opacity:0.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof i.ghost=="string"?i.ghost:"");e.ghost.appendTo(e.helper)},resize:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost){e.ghost.css({position:"relative",height:e.size.height,width:e.size.width})}},stop:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost&&e.helper){e.helper.get(0).removeChild(e.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(e,m){var p=c(this).data("resizable"),h=p.options,k=p.size,i=p.originalSize,j=p.originalPosition,n=p.axis,l=h._aspectRatio||e.shiftKey;h.grid=typeof h.grid=="number"?[h.grid,h.grid]:h.grid;var g=Math.round((k.width-i.width)/(h.grid[0]||1))*(h.grid[0]||1),f=Math.round((k.height-i.height)/(h.grid[1]||1))*(h.grid[1]||1);if(/^(se|s|e)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f}else{if(/^(ne)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f}else{if(/^(sw)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.left=j.left-g}else{p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f;p.position.left=j.left-g}}}}});var b=function(e){return parseInt(e,10)||0};var a=function(e){return !isNaN(parseInt(e,10))}})(jQuery);/*! + * jQuery hashchange event - v1.3 - 7/21/2010 + * http://benalman.com/projects/jquery-hashchange-plugin/ + * + * Copyright (c) 2010 "Cowboy" Ben Alman + * Dual licensed under the MIT and GPL licenses. + * http://benalman.com/about/license/ + */ +(function($,e,b){var c="hashchange",h=document,f,g=$.event.special,i=h.documentMode,d="on"+c in e&&(i===b||i>7);function a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Modules
+
+
+
Here is a list of all modules:
+
[detail level 1234]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 mcuxClAes_ConstantsDefines of constants associated with mcuxClAes
 mcuxClAes_KeyTypesDefines of supported key types of mcuxClAes, see mcuxClKey
 ▼MCUX CL – API
 ►mcuxClCipherCipher component
 ►mcuxClKeyMcuxClKey component
 ►mcuxClMacMessage Authentication Code (MAC) componentThe mcuxClMac component implements Message Authentication Code (MAC) calculation, based on either HMAC or CMAC
 Random PATCH_MODE APIRandom operations in PATCH_MODE
 Random TEST_MODE APIRandom operations in TEST_MODE
 ►mcuxClAeadHash component
 ►Core APIEssential types and functionality
 ►HMAC Modes APIHMAC mode operations
 ►MAC Modes APIMessage Authentication Code (MAC) mode operations
 ▼mcuxClEccElliptic Curve Cryptography component
 mcuxClEcc_ConstantsDefines constants of mcuxClEcc
 mcuxClEcc_FunctionsDefines all functions of mcuxClEcc
 mcuxClEcc_KeyTypeDescriptorsDefinitions of ECC related key type descriptors
 ►mcuxClEcc_MemoryConsumptionDefines the memory consumption for the mcuxClEcc component
 ►mcuxClEcc_ParameterSizesDefines domain parameter, key and signature sizes of mcuxClEcc
 ►mcuxClEcc_MacrosDefines all macros of mcuxClEcc
 mcuxClEcc_TypesDefines all types of mcuxClEcc
 mcuxClEcc_DescriptorsDefines descriptors of mcuxClEcc
 ▼mcuxClElsELS driver
 ►mcuxClEls_AeadThis part of the mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD)
 ►mcuxClEls_CipherThis part of the mcuxClEls driver supports functionality for symmetric ciphers
 ►mcuxClEls_CmacThis part of the mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC)
 ►mcuxClEls_CommonThis part of the mcuxClEls driver supports common functionality
 ►mcuxClEls_CrcThis part of the mcuxClEls driver defines the Command CRC functionality
 ►mcuxClEls_EccThis part of the mcuxClEls driver supports functionality for elliptic curve cryptography
 ►mcuxClEls_HashThis part of the mcuxClEls driver supports hashing
 ►mcuxClEls_HmacThis part of the mcuxClEls driver supports functionality for hashed-key message authentication codes
 ►mcuxClEls_KdfThis part of the mcuxClEls driver supports functionality for key derivation
 ►mcuxClEls_KeyManagementThis part of the mcuxClEls driver supports functionality for keys management
 ►mcuxClEls_RngThis part of the mcuxClEls driver supports functionality for random number generation
 ►mcuxClEls_TypesThis part of the mcuxClEls driver defines common types
 ▼mcuxClHashHash component
 ►mcuxClHash_ConstantsConstants of mcuxClHash component
 mcuxClHash_FunctionsDefines all functions of mcuxClHash
 mcuxClHash_TypesDefines all types of the mcuxClHash component
 ▼mcuxClMathComponent of mathematics functions
 mcuxClMath_FunctionsDefines all functions of mcuxClMath
 mcuxClMath_MacrosDefines all macros of mcuxClMath
 ▼mcuxClMemoryBasic memory operations
 mcuxClMemory_ClearThis function clears a memory region
 mcuxClMemory_CopyThis function copies a memory region from src to dst
 mcuxClMemory_Copy_ReversedThis function copies a memory region from src to dst reversely
 mcuxClMemory_EndiannessThese macros implement endianess management on integers
 mcuxClMemory_SetThis function sets all bytes in a memory region to a specified value
 ►mcuxClMemory_TypesDefines all types used by the mcuxClMemory functions
 ▼mcuxClOsccaPkcComponent of PKC hardware driver
 mcuxClOsccaPkc_FunctionsDefines all functions of mcuxClOsccaPkc
 mcuxClOsccaSm3Hash component
 mcuxClOsccaSm3_ModesHashing modes of the mcuxClOsccaSm3 component
 MCUXCLOSCCASM3_OUTPUT_SIZE_Defines for digest sizes
 MCUXCLOSCCASM3_WADefinitions of workarea sizes for the mcuxClOsccaSm3 functions
 MCUXCLOSCCASM3_CONTEXTDefinitions of context sizes for the mcuxClOsccaSm3 multi-part functions
 Constants definitionsConstants used by the Padding component
 Padding type definitionsTypes used by the Padding component
 ▼mcuxClPkcComponent of PKC hardware driver
 ►mcuxClPkc_FunctionsDefines all functions of mcuxClPkc
 ►mcuxClPkc_MacrosDefines all macros of mcuxClPkc
 ▼mcuxClRandomComponent of random number generation
 ►mcuxClRandom_ConstantsDefines all contstants of mcuxClRandom
 mcuxClRandom_FunctionsDefines all functions of mcuxClRandom
 mcuxClRandom_TypesDefines all types of mcuxClRandom
 mcuxClRandom_ConstantsDefines all modes of mcuxClRandomModes
 Random interfacesInterfaces to perform Random handling operations
 Random interfacesInterfaces to perform Random handling operations
 mcuxClRandomModes_MemoryConsumptionDefines the memory consumption for the mcuxClRandom component
 ▼mcuxClRsaRSA component
 ►mcuxClRsa_ConstantsConstants of mcuxClRsa component
 mcuxClRsa_FunctionsDefines all functions of mcuxClRsa
 ►mcuxClRsa_MacrosDefines all macros of mcuxClRsa
 mcuxClRsa_TypesDefines all types of the mcuxClRsa component
 ▼mcuxClSessionThis component provides functions for managing a session
 mcuxClSession_FunctionsDefines all functions of mcuxClSession
 ►mcuxClSession_ConstantsDefines all constants of mcuxClSession
 mcuxClSession_TypesDefines all types of mcuxClSession
 ▼MCUX CSSL – API
 ►Data Integrity APIData integrity mechanism
 ►Flow Protection APIFlow protection mechanism
 ►mcuxCssl Memory APIControl Flow Protected Memory Functions
 ►Parameter Integrity APIFunctionality to ensure parameter integrity during function calls
 ►Secure Counter APISecure counter mechanism
 ▼MCUX CSSL – Configurations
 Data Integrity ConfigurationConfiguration options for the data integrity mechanism
 Flow Protection ConfigurationConfiguration options for the flow protection mechanism
 Secure Counter ConfigurationConfiguration options for the secure counter mechanism
 ▼MCUX CSSL – Implementations
 ►Data Integrity: DisabledDisable the data integrity mechanism
 ►Flow Protection: Secure CounterSecure counter based implementation for the flow protection mechanism
 ►Secure Counter: DisabledDisable the secure counter mechanism
 ►Secure Counter: SW LocalSecure counter mechanism implementation using a local variable
+ + + + + + + diff --git a/components/els_pkc/doc/mcxn/html/modules.js b/components/els_pkc/doc/mcxn/html/modules.js new file mode 100644 index 000000000..f8bc9620e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/modules.js @@ -0,0 +1,26 @@ +var modules = +[ + [ "mcuxClAes_Constants", "a00669.html", "a00669" ], + [ "mcuxClAes_KeyTypes", "a00670.html", "a00670" ], + [ "MCUX CL – API", "a00673.html", "a00673" ], + [ "mcuxClEcc", "a00679.html", "a00679" ], + [ "mcuxClEls", "a00688.html", "a00688" ], + [ "mcuxClHash", "a00769.html", "a00769" ], + [ "mcuxClMath", "a00805.html", "a00805" ], + [ "mcuxClMemory", "a00808.html", "a00808" ], + [ "mcuxClOsccaPkc", "a00817.html", "a00817" ], + [ "mcuxClOsccaSm3", "a00819.html", null ], + [ "mcuxClOsccaSm3_Modes", "a00820.html", null ], + [ "MCUXCLOSCCASM3_OUTPUT_SIZE_", "a00821.html", "a00821" ], + [ "MCUXCLOSCCASM3_WA", "a00822.html", "a00822" ], + [ "MCUXCLOSCCASM3_CONTEXT", "a00823.html", "a00823" ], + [ "Constants definitions", "a00824.html", "a00824" ], + [ "Padding type definitions", "a00825.html", "a00825" ], + [ "mcuxClPkc", "a00826.html", "a00826" ], + [ "mcuxClRandom", "a00829.html", "a00829" ], + [ "mcuxClRsa", "a00839.html", "a00839" ], + [ "mcuxClSession", "a00854.html", "a00854" ], + [ "MCUX CSSL – API", "a00860.html", "a00860" ], + [ "MCUX CSSL – Configurations", "a00864.html", "a00864" ], + [ "MCUX CSSL – Implementations", "a00866.html", "a00866" ] +]; \ No newline at end of file diff --git a/components/els_pkc/doc/mcxn/html/nav_f.png b/components/els_pkc/doc/mcxn/html/nav_f.png new file mode 100644 index 0000000000000000000000000000000000000000..72a58a529ed3a9ed6aa0c51a79cf207e026deee2 GIT binary patch literal 153 zcmeAS@N?(olHy`uVBq!ia0vp^j6iI`!2~2XGqLUlQVE_ejv*C{Z|{2ZH7M}7UYxc) zn!W8uqtnIQ>_z8U literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/nav_g.png b/components/els_pkc/doc/mcxn/html/nav_g.png new file mode 100644 index 0000000000000000000000000000000000000000..2093a237a94f6c83e19ec6e5fd42f7ddabdafa81 GIT binary patch literal 95 zcmeAS@N?(olHy`uVBq!ia0vp^j6lrB!3HFm1ilyoDK$?Q$B+ufw|5PB85lU25BhtE tr?otc=hd~V+ws&_A@j8Fiv!KF$B+ufw|5=67#uj90@pIL wZ=Q8~_Ju`#59=RjDrmm`tMD@M=!-l18IR?&vFVdQ&MBb@0HFXL=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function hashValue() +{ + return $(location).attr('hash').substring(1).replace(/[^\w\-]/g,''); +} + +function hashUrl() +{ + return '#'+hashValue(); +} + +function pathName() +{ + return $(location).attr('pathname').replace(/[^-A-Za-z0-9+&@#/%?=~_|!:,.;\(\)]/g, ''); +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + if ($.browser.msie && $.browser.version<=8) { + // script.onload does not work with older versions of IE + script.onreadystatechange = function() { + if (script.readyState=='complete' || script.readyState=='loaded') { + func(); if (show) showRoot(); + } + } + } + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + var level=-1; + var n = node; + while (n.parentNode) { level++; n=n.parentNode; } + if (node.childrenData) { + var imgNode = document.createElement("span"); + imgNode.className = 'arrow'; + imgNode.style.paddingLeft=(16*level).toString()+'px'; + imgNode.innerHTML=arrowRight; + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + node.plus_img.innerHTML=arrowRight; + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } else { + var span = document.createElement("span"); + span.className = 'arrow'; + span.style.width = 16*(level+1)+'px'; + span.innerHTML = ' '; + domNode.appendChild(span); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + var ancParent = $(anchor.parent()); + if (ancParent.hasClass('memItemLeft') || + ancParent.hasClass('fieldname') || + ancParent.hasClass('fieldtype') || + ancParent.is(':header')) + { + pos = ancParent.position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath(pathName()); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + node.plus_img.innerHTML = arrowDown; + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = hashUrl(); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+hashValue()+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parent().attr('class')=='fieldname'){ + glowEffect(anchor.parent().parent(),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } + gotoAnchor(anchor,aname,false); +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath(pathName())+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + if ($('#nav-tree-contents .item:first').hasClass('selected')) { + $('#nav-sync').css('top','30px'); + } else { + $('#nav-sync').css('top','5px'); + } + showRoot(); +} + +function showNode(o, node, index, hash) +{ + if (node && node.childrenData) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + showNode(o,node,index,hash); + },true); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).css({'display':'block'}); + node.plus_img.innerHTML = arrowDown; + node.expanded = true; + var n = node.children[o.breadcrumbs[index]]; + if (index+11) hash = '#'+parts[1].replace(/[^\w\-]/g,''); + else hash=''; + } + if (hash.match(/^#l\d+$/)) { + var anchor=$('a[name='+hash.substring(1)+']'); + glowEffect(anchor.parent(),1000); // line number + hash=''; // strip line number anchors + } + var url=root+hash; + var i=-1; + while (NAVTREEINDEX[i+1]<=url) i++; + if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath) + } else { + getScript(relpath+'navtreeindex'+i,function(){ + navTreeSubIndices[i] = eval('NAVTREEINDEX'+i); + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath); + } + },true); + } +} + +function showSyncOff(n,relpath) +{ + n.html(''); +} + +function showSyncOn(n,relpath) +{ + n.html(''); +} + +function toggleSyncButton(relpath) +{ + var navSync = $('#nav-sync'); + if (navSync.hasClass('sync')) { + navSync.removeClass('sync'); + showSyncOff(navSync,relpath); + storeLink(stripPath2(pathName())+hashUrl()); + } else { + navSync.addClass('sync'); + showSyncOn(navSync,relpath); + deleteLink(); + } +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + o.node.expanded = false; + o.node.isLast = true; + o.node.plus_img = document.createElement("span"); + o.node.plus_img.className = 'arrow'; + o.node.plus_img.innerHTML = arrowRight; + + if (localStorageSupported()) { + var navSync = $('#nav-sync'); + if (cachedLink()) { + showSyncOff(navSync,relpath); + navSync.removeClass('sync'); + } else { + showSyncOn(navSync,relpath); + } + navSync.click(function(){ toggleSyncButton(relpath); }); + } + + $(window).load(function(){ + navTo(o,toroot,hashUrl(),relpath); + showRoot(); + }); + + $(window).bind('hashchange', function(){ + if (window.location.hash && window.location.hash.length>1){ + var a; + if ($(location).attr('hash')){ + var clslink=stripPath(pathName())+':'+hashValue(); + a=$('.item a[class$="'+clslink.replace(/1|%O$WD@{VPM$7~Ar*{o?;hlAFyLXmaDC0y znK1_#cQqJWPES%4Uujug^TE?jMft$}Eq^WaR~)%f)vSNs&gek&x%A9X9sM + + + + + + +MCUX CLNS: Related Pages + + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
MCUX CLNS +
+
MCUX Crypto Library Normal Secure
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+
Related Pages
+
+
+
Here is a list of all related documentation pages:
+ + + +
 User Guidance Manual
 Security and Integration Guidance Manual
+
+
+
+ + + + diff --git a/components/els_pkc/doc/mcxn/html/resize.js b/components/els_pkc/doc/mcxn/html/resize.js new file mode 100644 index 000000000..6617aee8e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/resize.js @@ -0,0 +1,136 @@ +/* + @licstart The following is the entire license notice for the + JavaScript code in this file. + + Copyright (C) 1997-2017 by Dimitri van Heesch + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + + @licend The above is the entire license notice + for the JavaScript code in this file + */ +function initResizable() +{ + var cookie_namespace = 'doxygen'; + var sidenav,navtree,content,header,collapsed,collapsedWidth=0,barWidth=6,desktop_vp=768,titleHeight; + + function readCookie(cookie) + { + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) { + var index = document.cookie.indexOf(myCookie); + if (index != -1) { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; + } + + function writeCookie(cookie, val, expiration) + { + if (val==undefined) return; + if (expiration == null) { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; + } + + function resizeWidth() + { + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).outerWidth(); + content.css({marginLeft:parseInt(sidenavWidth)+"px"}); + writeCookie('width',sidenavWidth-barWidth, null); + } + + function restoreWidth(navWidth) + { + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+barWidth+"px"}); + sidenav.css({width:navWidth + "px"}); + } + + function resizeHeight() + { + var headerHeight = header.outerHeight(); + var footerHeight = footer.outerHeight(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px"}); + var width=$(window).width(); + if (width!=collapsedWidth) { + if (width=desktop_vp) { + if (!collapsed) { + collapseExpand(); + } + } else if (width>desktop_vp && collapsedWidth0) { + restoreWidth(0); + collapsed=true; + } + else { + var width = readCookie('width'); + if (width>200 && width<$(window).width()) { restoreWidth(width); } else { restoreWidth(200); } + collapsed=false; + } + } + + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(sidenav).resizable({ minWidth: 0 }); + $(window).resize(function() { resizeHeight(); }); + var device = navigator.userAgent.toLowerCase(); + var touch_device = device.match(/(iphone|ipod|ipad|android)/); + if (touch_device) { /* wider split bar for touch only devices */ + $(sidenav).css({ paddingRight:'20px' }); + $('.ui-resizable-e').css({ width:'20px' }); + $('#nav-sync').css({ right:'34px' }); + barWidth=20; + } + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); + $(".ui-resizable-handle").dblclick(collapseExpand); + $(window).load(resizeHeight); +} +/* @license-end */ diff --git a/components/els_pkc/doc/mcxn/html/search/all_0.html b/components/els_pkc/doc/mcxn/html/search/all_0.html new file mode 100644 index 000000000..5330204c2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
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+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_0.js b/components/els_pkc/doc/mcxn/html/search/all_0.js new file mode 100644 index 000000000..698503b77 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_0.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['_5f_5fattribute_5f_5f',['__attribute__',['../a00032.html#a3e0329840494bde2557d01ee51c9aa52',1,'__attribute__((aligned(4))): mcuxClEls_Key_Import_Puk_DER_example.c'],['../a00158.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_sign_NoEncode_example.c']]], + ['_5f_5fpad0_5f_5f',['__pad0__',['../a00997.html#a55a86ab29b1e20072f48c56470568824',1,'mcuxClEls_AeadOption_t::__pad0__()'],['../a01009.html#abb6ec00ab841f6edcc37f6f51fb35975',1,'mcuxClEls_CipherOption_t::__pad0__()'],['../a01021.html#add5bf1feb8f2a41a0f46c1bb06f15db0',1,'mcuxClEls_CmacOption_t::__pad0__()'],['../a01033.html#a3f71ee0da1f604f06bce53faaee88549',1,'mcuxClEls_HwVersion_t::__pad0__()'],['../a01045.html#ae4d9f2540dc7380b776ff6de6325c22f',1,'mcuxClEls_HwState_t::__pad0__()'],['../a01057.html#a71d456bef9a7a21d8ff55bc711a6a3bc',1,'mcuxClEls_InterruptOptionEn_t::__pad0__()'],['../a01069.html#ad560c85d9ea7975330ec5a2e207b30c0',1,'mcuxClEls_InterruptOptionRst_t::__pad0__()'],['../a01081.html#a6f7f7fb21a47e0ba886c9c5ebdaae7bf',1,'mcuxClEls_InterruptOptionSet_t::__pad0__()'],['../a01093.html#aa06967699abb851f567edb7ae687a0d2',1,'mcuxClEls_HwConfig_t::__pad0__()'],['../a01105.html#a49e0d7b8ada89de5bd766ac9cf2c3e27',1,'mcuxClEls_CommandCrcConfig_t::__pad0__()'],['../a01117.html#a0e9a4b194d887a2b2c4c2297c2cbd868',1,'mcuxClEls_EccSignOption_t::__pad0__()'],['../a01129.html#a7dffb127ef2f32236227c9023af7e5cd',1,'mcuxClEls_EccVerifyOption_t::__pad0__()'],['../a01141.html#ab6d97c184d6c34f0d6c1bc8e0a77057c',1,'mcuxClEls_EccKeyGenOption_t::__pad0__()'],['../a01153.html#a98a12e39b9f189c172f6b951c2ae781c',1,'mcuxClEls_EccKeyExchOption_t::__pad0__()'],['../a01165.html#aae0a2c87c57c974e9cb7a55126f95ca9',1,'mcuxClEls_HashOption_t::__pad0__()'],['../a01177.html#a590b1d47d31c598e6df237437a015b8e',1,'mcuxClEls_HmacOption_t::__pad0__()'],['../a01225.html#a2dfcb81e1476a07a6ab67f8c090b4ab5',1,'mcuxClEls_KeyImportOption_t::__pad0__()'],['../a01237.html#aef07ed5cdd67e69b2862d98fa9ce2bf2',1,'mcuxClEls_KeyProp_t::__pad0__()']]], + ['_5f_5fpad1_5f_5f',['__pad1__',['../a00997.html#a6b276f4a8ddbf8c2f337ad23c52d6963',1,'mcuxClEls_AeadOption_t::__pad1__()'],['../a01009.html#a8b8096d5f06a8f303976697a0fa369aa',1,'mcuxClEls_CipherOption_t::__pad1__()'],['../a01021.html#ace1fa4ccaa7741b93563ac6ace23989d',1,'mcuxClEls_CmacOption_t::__pad1__()'],['../a01045.html#aacebdfe99f0d29f126adc2a9d42a4b22',1,'mcuxClEls_HwState_t::__pad1__()'],['../a01057.html#a502fdb51eeb304aabfd1ed4550ac3258',1,'mcuxClEls_InterruptOptionEn_t::__pad1__()'],['../a01069.html#a188253366e073fdcbdccbaa41ccbe915',1,'mcuxClEls_InterruptOptionRst_t::__pad1__()'],['../a01081.html#a3a1d6b3eaa5f8be52531ddb20f3e85c8',1,'mcuxClEls_InterruptOptionSet_t::__pad1__()'],['../a01117.html#a5527caf737b06f5053f89c60354dbe65',1,'mcuxClEls_EccSignOption_t::__pad1__()'],['../a01129.html#ad2bdfda87da142b43bfd1e64ee8bb072',1,'mcuxClEls_EccVerifyOption_t::__pad1__()'],['../a01153.html#a06d0377a60794946f8788a7fad8af177',1,'mcuxClEls_EccKeyExchOption_t::__pad1__()'],['../a01165.html#a97d346a2d66df4edd1ab677769a7b648',1,'mcuxClEls_HashOption_t::__pad1__()'],['../a01177.html#afa33782e670b9a44a28f71cb097ad830',1,'mcuxClEls_HmacOption_t::__pad1__()'],['../a01225.html#ad67985d38d1563a926768316825e1944',1,'mcuxClEls_KeyImportOption_t::__pad1__()'],['../a01237.html#aba08650854846dd1ef4788c1a8ef0c58',1,'mcuxClEls_KeyProp_t::__pad1__()']]], + ['_5f_5fpad2_5f_5f',['__pad2__',['../a00997.html#ae06263ba435ff9824be1f20c8f20b96c',1,'mcuxClEls_AeadOption_t::__pad2__()'],['../a01009.html#a568f1ef7bba7f45209bf0cf43bb66b45',1,'mcuxClEls_CipherOption_t::__pad2__()'],['../a01045.html#a68593765ff0c58861d600be91ee332a3',1,'mcuxClEls_HwState_t::__pad2__()'],['../a01153.html#a82f1e57ea7fcdfd607a3954396e6ec84',1,'mcuxClEls_EccKeyExchOption_t::__pad2__()'],['../a01225.html#a05660839da43298f12f96572bf538330',1,'mcuxClEls_KeyImportOption_t::__pad2__()']]], + ['_5f_5fpad3_5f_5f',['__pad3__',['../a01045.html#a240bdaa5a99cd057983b3cbe28e33fb1',1,'mcuxClEls_HwState_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_1.html b/components/els_pkc/doc/mcxn/html/search/all_1.html new file mode 100644 index 000000000..2f4679366 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
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Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_1.js b/components/els_pkc/doc/mcxn/html/search/all_1.js new file mode 100644 index 000000000..889a925fc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_1.js @@ -0,0 +1,16 @@ +var searchData= +[ + ['acpmod',['acpmod',['../a00997.html#a2504aa4fde601569a6c27276e76802f3',1,'mcuxClEls_AeadOption_t']]], + ['acpsie',['acpsie',['../a00997.html#a5fafad6f592dfb928316273b5ccbec12',1,'mcuxClEls_AeadOption_t']]], + ['acpsoe',['acpsoe',['../a00997.html#a77636eb7e553de47143580de37585920',1,'mcuxClEls_AeadOption_t']]], + ['aes128_5fexpected_5foutput',['aes128_expected_output',['../a00002.html#a8f724484dd059cbe14851b0a799c0890',1,'aes128_expected_output(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#a8f724484dd059cbe14851b0a799c0890',1,'aes128_expected_output(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['aes128_5finput',['aes128_input',['../a00002.html#ad27e8e7cceb19331fe1611f2eeb66dc8',1,'aes128_input(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#ad27e8e7cceb19331fe1611f2eeb66dc8',1,'aes128_input(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['aes128_5fiv',['aes128_iv',['../a00005.html#a8eef9cffb37af88e29a455967c68e7bc',1,'aes128_iv(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00041.html#aef268ff45a3b41fd6678cfeaf409151e',1,'aes128_iv(): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['aes128_5fkey',['aes128_key',['../a00002.html#af381139a6e72029d4fa91365ecd128dc',1,'aes128_key(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#af381139a6e72029d4fa91365ecd128dc',1,'aes128_key(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00041.html#afd0e33c5f8fc3670f63b637fb2febba4',1,'aes128_key(): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['aes128_5foutput',['aes128_output',['../a00002.html#aac664c77a3ccf9254ab1afd4ce762854',1,'aes128_output(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#aac664c77a3ccf9254ab1afd4ce762854',1,'aes128_output(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['authciphersup',['authciphersup',['../a01093.html#acd5dabf360244a33333e3063010ad26d',1,'mcuxClEls_HwConfig_t']]], + ['aead_20mode_20definitions',['AEAD mode definitions',['../a00668.html',1,'']]], + ['aead_20type_20definitions',['AEAD type definitions',['../a00666.html',1,'']]], + ['apis_20to_20construct_20hmac_20modes',['APIs to construct HMAC modes',['../a00780.html',1,'']]], + ['apis_20to_20construct_20mac_20modes',['APIs to construct Mac modes',['../a00802.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_10.html b/components/els_pkc/doc/mcxn/html/search/all_10.html new file mode 100644 index 000000000..170dc09c6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_10.html @@ -0,0 +1,30 @@ + + + + + + + + + +
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No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_10.js b/components/els_pkc/doc/mcxn/html/search/all_10.js new file mode 100644 index 000000000..2bba18f54 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_10.js @@ -0,0 +1,42 @@ +var searchData= +[ + ['switching_20flow_20protection',['Switching flow protection',['../a00884.html',1,'']]], + ['switching_20flow_20protection',['Switching flow protection',['../a00875.html',1,'']]], + ['session_20rtf_20configuration_20values',['Session RTF configuration values',['../a00858.html',1,'']]], + ['session_20status_20values',['Session Status values',['../a00857.html',1,'']]], + ['secure_20counter_20api',['Secure Counter API',['../a00901.html',1,'']]], + ['secure_20counter_20configuration',['Secure Counter Configuration',['../a00906.html',1,'']]], + ['secure_20counter_3a_20disabled',['Secure Counter: Disabled',['../a00907.html',1,'']]], + ['secure_20counter_3a_20sw_20local',['Secure Counter: SW Local',['../a00912.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00902.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00904.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00905.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00903.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00908.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00910.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00911.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00909.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00913.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00915.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00916.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00914.html',1,'']]], + ['securitycounter',['securityCounter',['../a01281.html#a3bca2e1ffbfa74a0afd525444dee8f16',1,'mcuxClSession_SecurityContext']]], + ['security_20and_20integration_20guidance_20manual',['Security and Integration Guidance Manual',['../a01321.html',1,'']]], + ['sha224_5fpadded_5finput',['sha224_padded_input',['../a00014.html#a3a90d0719630869e92e2a830633b3276',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha224_5freference_5fdigest',['sha224_reference_digest',['../a00014.html#abf0bb6879a755eadc984fc84923cc0bf',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha256_5fpadded_5finput',['sha256_padded_input',['../a00017.html#a890aa9aa5c130271cfeb0c43324c4e51',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha256_5freference_5fdigest',['sha256_reference_digest',['../a00017.html#ab00b3a897c4bba2fc29a541a23c4a0ea',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha2_5f224_5fdigest',['sha2_224_digest',['../a00014.html#ad953a0e00811066696ef763b14c096f9',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha2_5f256_5fdigest',['sha2_256_digest',['../a00017.html#aff61e539755c5c8c4b21046c976abdfa',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha2_5f384_5fdigest',['sha2_384_digest',['../a00020.html#a4fdd7260badc8d686d79df408edb7c21',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha2_5f512_5fdigest',['sha2_512_digest',['../a00023.html#a0d806e17a1cf2005916602c6ebd303f2',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sha384_5fpadded_5finput',['sha384_padded_input',['../a00020.html#a157042750820e99bfa2441a0fcba481e',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha384_5freference_5fdigest',['sha384_reference_digest',['../a00020.html#a031991d5ae2823da0e9b5bd7c854e9b3',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha512_5fpadded_5finput',['sha512_padded_input',['../a00023.html#aa6ed8b927262ff98775b8726955ef8e0',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sha512_5freference_5fdigest',['sha512_reference_digest',['../a00023.html#a1e3cfc0c29a9863abf6ecd8c022d05ab',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sie',['sie',['../a01021.html#ab165c41c5cf41abf2b463ab742fa0c1b',1,'mcuxClEls_CmacOption_t']]], + ['signrtf',['signrtf',['../a01117.html#aa4bcc3f1aaf9e991e62cdc22ffd7500e',1,'mcuxClEls_EccSignOption_t']]], + ['size',['size',['../a01277.html#a372ca932239a945030d51a23913c36e0',1,'mcuxClSession_WorkArea']]], + ['skip_5fpbk',['skip_pbk',['../a01141.html#afa4cb29e6c55e30a30185180de2f8e49',1,'mcuxClEls_EccKeyGenOption_t']]], + ['soe',['soe',['../a01021.html#a69e48d5d1edf8300761b237872e4192f',1,'mcuxClEls_CmacOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_11.html b/components/els_pkc/doc/mcxn/html/search/all_11.html new file mode 100644 index 000000000..10fcd0919 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_11.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_11.js b/components/els_pkc/doc/mcxn/html/search/all_11.js new file mode 100644 index 000000000..104edad6e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_11.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['tlsinitsup',['tlsinitsup',['../a01093.html#a9dc24a8f88688b9d4cc5c305acbf46e5',1,'mcuxClEls_HwConfig_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_12.html b/components/els_pkc/doc/mcxn/html/search/all_12.html new file mode 100644 index 000000000..0876adf45 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_12.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_12.js b/components/els_pkc/doc/mcxn/html/search/all_12.js new file mode 100644 index 000000000..b5b032607 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_12.js @@ -0,0 +1,24 @@ +var searchData= +[ + ['user_20manual_20of_20crypto_20library_20normal_20secure_20_28clns_29',['User Manual of Crypto Library Normal Secure (CLNS)',['../index.html',1,'']]], + ['uaes',['uaes',['../a01237.html#a18d3c3d356100d7bd01a9950c1f7b81e',1,'mcuxClEls_KeyProp_t']]], + ['uckdf',['uckdf',['../a01237.html#a3bdb1b36f76fe81225b14896d3429147',1,'mcuxClEls_KeyProp_t']]], + ['ucmac',['ucmac',['../a01237.html#acceecb25ef42cd4017edfc9095272b3d',1,'mcuxClEls_KeyProp_t']]], + ['uecdh',['uecdh',['../a01237.html#af513bad0dfe63b94b601adae2590ef17',1,'mcuxClEls_KeyProp_t']]], + ['uecsg',['uecsg',['../a01237.html#adb18f3c09ac78e8d74f2ff9563da084b',1,'mcuxClEls_KeyProp_t']]], + ['uhkdf',['uhkdf',['../a01237.html#a983d6a05d50a4e6eeb929ecfab1c5ca0',1,'mcuxClEls_KeyProp_t']]], + ['uhmac',['uhmac',['../a01237.html#ae8e6215c6390b64024f5bb71d09013a6',1,'mcuxClEls_KeyProp_t']]], + ['uhwo',['uhwo',['../a01237.html#a08b731503e03ee90d1904cbb88e9c37c',1,'mcuxClEls_KeyProp_t']]], + ['ukgsrc',['ukgsrc',['../a01237.html#ac4fbcd8af04b845353857e27ae6e90b8',1,'mcuxClEls_KeyProp_t']]], + ['uksk',['uksk',['../a01237.html#a1c20ef8f869a090cc90472821adba513',1,'mcuxClEls_KeyProp_t']]], + ['ukuok',['ukuok',['../a01237.html#ab0fe394151ed388fa03198d5710bc0d1',1,'mcuxClEls_KeyProp_t']]], + ['ukwk',['ukwk',['../a01237.html#a006a40e53f4859e41e4b4ec5424c6c26',1,'mcuxClEls_KeyProp_t']]], + ['upprot_5fpriv',['upprot_priv',['../a01237.html#a50d3bbaabf919fab908e2ae83fe5a5ab',1,'mcuxClEls_KeyProp_t']]], + ['upprot_5fsec',['upprot_sec',['../a01237.html#a0d130be83d337e7a5d9ef56f4a92f3a0',1,'mcuxClEls_KeyProp_t']]], + ['urtf',['urtf',['../a01237.html#a32ac519b2729fc88babaaf23ecfb6523',1,'mcuxClEls_KeyProp_t']]], + ['used',['used',['../a01277.html#ab3280a7d27aa7837287e2fa4376492fb',1,'mcuxClSession_WorkArea']]], + ['user_20guidance_20manual',['User Guidance Manual',['../a01320.html',1,'']]], + ['utlpsms',['utlpsms',['../a00768.html#ga0056d58adc14ddca2f9eee45575393a8',1,'mcuxClEls_Types.h']]], + ['utlsms',['utlsms',['../a01237.html#a5f7b5dc8e882536c83ff87ac246ca6ed',1,'mcuxClEls_KeyProp_t']]], + ['utlspms',['utlspms',['../a01237.html#a30f2161747c56e0de99561d38885be7e',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_13.html b/components/els_pkc/doc/mcxn/html/search/all_13.html new file mode 100644 index 000000000..dc6c0496a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_13.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_13.js b/components/els_pkc/doc/mcxn/html/search/all_13.js new file mode 100644 index 000000000..b37bf271b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_13.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['value',['value',['../a00997.html#ac8b3278eb96cd5ca0e15b9b2318305a7',1,'mcuxClEls_AeadOption_t::value()'],['../a01009.html#a1c724d7ce478fcbb4cdd0ccb5c1fd899',1,'mcuxClEls_CipherOption_t::value()'],['../a01021.html#ab326f666bbbcabd39dc0bd26a83fa5c0',1,'mcuxClEls_CmacOption_t::value()'],['../a01033.html#a5e9b7103d2b419e9d860c04eb142d6e2',1,'mcuxClEls_HwVersion_t::value()'],['../a01045.html#a9e0ca3d1f7797c407e594e55411549b0',1,'mcuxClEls_HwState_t::value()'],['../a01057.html#a24184dcdf86670224ea536fc20a0e4d8',1,'mcuxClEls_InterruptOptionEn_t::value()'],['../a01069.html#afe633f619c2da24bd5a99cf97782924b',1,'mcuxClEls_InterruptOptionRst_t::value()'],['../a01081.html#a58934a4a256905327206ee08d8c5931f',1,'mcuxClEls_InterruptOptionSet_t::value()'],['../a01093.html#a2cf565902d36ad357eaaa793eb4be8d5',1,'mcuxClEls_HwConfig_t::value()'],['../a01105.html#a4dc44ca29e9ef4bcea0b6469a5966f6d',1,'mcuxClEls_CommandCrcConfig_t::value()'],['../a01117.html#a7e32d20de26a1ca2d7eee8fe2fd95456',1,'mcuxClEls_EccSignOption_t::value()'],['../a01129.html#a73b0b8e42d753a97bb03cb053799e33a',1,'mcuxClEls_EccVerifyOption_t::value()'],['../a01141.html#a2c377cdae550923ee7e1234735e08b40',1,'mcuxClEls_EccKeyGenOption_t::value()'],['../a01153.html#aaa4e256f25f9c74123c28c5926d21ba2',1,'mcuxClEls_EccKeyExchOption_t::value()'],['../a01165.html#a71c7896e79c292ac111d85992a16c78d',1,'mcuxClEls_HashOption_t::value()'],['../a01177.html#a577065f77e409f612e5a2fc2072b971d',1,'mcuxClEls_HmacOption_t::value()'],['../a01189.html#a00abd43e6b7c9816562f2aa1d93c0b9e',1,'mcuxClEls_CkdfOption_t::value()'],['../a01201.html#aa39e185af4b2cfd758c0b7b7d3bea8db',1,'mcuxClEls_HkdfOption_t::value()'],['../a01213.html#acfe68053c7558c29e085ca434cf432cd',1,'mcuxClEls_TlsOption_t::value()'],['../a01225.html#ad5bfabd7e1e04a95627e0cbc144afdcb',1,'mcuxClEls_KeyImportOption_t::value()'],['../a01237.html#af184a952f255348629f27f24c0fd0bd9',1,'mcuxClEls_KeyProp_t::value()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_14.html b/components/els_pkc/doc/mcxn/html/search/all_14.html new file mode 100644 index 000000000..7fe46634d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_14.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_14.js b/components/els_pkc/doc/mcxn/html/search/all_14.js new file mode 100644 index 000000000..e671a6f89 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_14.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['wnumbytes',['wNumBytes',['../a01253.html#aa8adc5c5c0851f5adc6abd44edf06d1c',1,'mcuxClOscca_MPInt_t']]], + ['word',['word',['../a00997.html#a6a1cf6dca7babcb5b673312d79c3db9e',1,'mcuxClEls_AeadOption_t::word()'],['../a01009.html#afd7050544cd985c2dda66061e0f0c44f',1,'mcuxClEls_CipherOption_t::word()'],['../a01021.html#aa34c3bf115a202c3c96b967bc6114498',1,'mcuxClEls_CmacOption_t::word()'],['../a01033.html#a87650934fb456d15383c0e0de64f93b2',1,'mcuxClEls_HwVersion_t::word()'],['../a01045.html#a8318bd94bd3469bac07874ba2921d0cf',1,'mcuxClEls_HwState_t::word()'],['../a01057.html#ad7e19b6dde1c236ad751eb9208e942db',1,'mcuxClEls_InterruptOptionEn_t::word()'],['../a01069.html#ad45dfa4c603c021060fc0b4fdf0f769d',1,'mcuxClEls_InterruptOptionRst_t::word()'],['../a01081.html#ac3c1022b8a8d5034511fd6ffcb76625d',1,'mcuxClEls_InterruptOptionSet_t::word()'],['../a01093.html#a57cd499ae60ad1bb19fc54517d9ff580',1,'mcuxClEls_HwConfig_t::word()'],['../a01117.html#a6f703afe07655c05795fd6061b321dc3',1,'mcuxClEls_EccSignOption_t::word()'],['../a01129.html#a1d1416b8e584c34840183572e7b2df3d',1,'mcuxClEls_EccVerifyOption_t::word()'],['../a01141.html#ab5dac27ccbb4062c42c971d44e504519',1,'mcuxClEls_EccKeyGenOption_t::word()'],['../a01153.html#a17969e2f10fec362e68869232cb1099b',1,'mcuxClEls_EccKeyExchOption_t::word()'],['../a01165.html#a4addaf59a3d2ab2743fd4c622c0e97ac',1,'mcuxClEls_HashOption_t::word()'],['../a01177.html#a5f797c75232df146cecc9c76dd04d463',1,'mcuxClEls_HmacOption_t::word()'],['../a01225.html#a9a03426cf6b706ee292473b3d695ebe0',1,'mcuxClEls_KeyImportOption_t::word()'],['../a01237.html#a270029567d10cf5d46c68f3fd5762394',1,'mcuxClEls_KeyProp_t::word()']]], + ['wrpok',['wrpok',['../a01237.html#a8b01f95eb9069953fe7a48b6ec85e479',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_2.html b/components/els_pkc/doc/mcxn/html/search/all_2.html new file mode 100644 index 000000000..4c33d8557 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_2.js b/components/els_pkc/doc/mcxn/html/search/all_2.js new file mode 100644 index 000000000..9ceb46486 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_2.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['bits',['bits',['../a00997.html#a2d11453f5716e58c8b34e92d434edd1b',1,'mcuxClEls_AeadOption_t::bits()'],['../a01009.html#af61168dc7998ed7862a56c85b64871c0',1,'mcuxClEls_CipherOption_t::bits()'],['../a01021.html#a6cb17fd040a2db25cdaafe3e042b0831',1,'mcuxClEls_CmacOption_t::bits()'],['../a01033.html#a107c920f079a09f0078dd0791faa2110',1,'mcuxClEls_HwVersion_t::bits()'],['../a01045.html#a3a7dbe3fd3f4e92c059cb39a04ac863e',1,'mcuxClEls_HwState_t::bits()'],['../a01057.html#ad3bc5d3ed1f3a1e38687c1742d3cf8f3',1,'mcuxClEls_InterruptOptionEn_t::bits()'],['../a01069.html#a38fff411deb5bfd137a206a35305d3e9',1,'mcuxClEls_InterruptOptionRst_t::bits()'],['../a01081.html#ac8b9b47932507184288a99d01ee45b39',1,'mcuxClEls_InterruptOptionSet_t::bits()'],['../a01093.html#a95b4684aa6203efcdf26303743fdfcd5',1,'mcuxClEls_HwConfig_t::bits()'],['../a01105.html#ac18d751428d40b3e3127a0779abc1cec',1,'mcuxClEls_CommandCrcConfig_t::bits()'],['../a01117.html#accf6312c26ce770b5647c4e45b00f7b5',1,'mcuxClEls_EccSignOption_t::bits()'],['../a01129.html#aa5f2cce580390956b07603eb64fe6fc7',1,'mcuxClEls_EccVerifyOption_t::bits()'],['../a01141.html#afc19db0547800dd35ed3d3294831344b',1,'mcuxClEls_EccKeyGenOption_t::bits()'],['../a01153.html#aa620a69ff6945f317f2df59bdf4284cd',1,'mcuxClEls_EccKeyExchOption_t::bits()'],['../a01165.html#aacda3c97994f6b172c7fd69c89d275dc',1,'mcuxClEls_HashOption_t::bits()'],['../a01177.html#ae06ed09126b22cf0131a97bff34cc166',1,'mcuxClEls_HmacOption_t::bits()'],['../a01225.html#ad0fc563d3f708b06c986ec2ae604d69e',1,'mcuxClEls_KeyImportOption_t::bits()'],['../a01237.html#abcae2eaaf0826e5548f0b416ecfff0b4',1,'mcuxClEls_KeyProp_t::bits()']]], + ['buffer',['buffer',['../a01277.html#acd3913d2b4adf01d7d95c687c578c752',1,'mcuxClSession_WorkArea']]], + ['busy',['busy',['../a01045.html#a453ae753658b4809ea3141fffd5641c8',1,'mcuxClEls_HwState_t']]], + ['branching_20flow_20protection',['Branching flow protection',['../a00874.html',1,'']]], + ['branching_20flow_20protection',['Branching flow protection',['../a00883.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_3.html b/components/els_pkc/doc/mcxn/html/search/all_3.html new file mode 100644 index 000000000..b634070bc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_3.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_3.js b/components/els_pkc/doc/mcxn/html/search/all_3.js new file mode 100644 index 000000000..fcdfc84ed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_3.js @@ -0,0 +1,20 @@ +var searchData= +[ + ['cfg',['cfg',['../a01261.html#a5d5778eef90af40b0ba73b22fdeedb57',1,'mcuxClPkc_State_t']]], + ['ciphersup',['ciphersup',['../a01093.html#ac0db95aaf62ac50581111452e89de3ba',1,'mcuxClEls_HwConfig_t']]], + ['ckdf_5falgo',['ckdf_algo',['../a01189.html#afc52662f6e41b83e0c731d77c616506c',1,'mcuxClEls_CkdfOption_t']]], + ['ckdfsup',['ckdfsup',['../a01093.html#a05b73ed0395351b9504c35f54ac50495',1,'mcuxClEls_HwConfig_t']]], + ['cipher_20mode_20definitions',['Cipher mode definitions',['../a00677.html',1,'']]], + ['cipher_20type_20definitions',['Cipher type definitions',['../a00676.html',1,'']]], + ['core_20type_20definitions',['Core type definitions',['../a00678.html',1,'']]], + ['constants_20definitions',['Constants definitions',['../a00824.html',1,'']]], + ['cmacsup',['cmacsup',['../a01093.html#ad30966f27a451f027aed32c036289515',1,'mcuxClEls_HwConfig_t']]], + ['cphmde',['cphmde',['../a01009.html#a2e1e4a5d815c2559f0ef02e4fd0e5523',1,'mcuxClEls_CipherOption_t']]], + ['cphsie',['cphsie',['../a01009.html#af8735651384f21746fcea24b5c935a1d',1,'mcuxClEls_CipherOption_t']]], + ['cphsoe',['cphsoe',['../a01009.html#aa37b413e9a8ffa66655bc529aadaadbc',1,'mcuxClEls_CipherOption_t']]], + ['cpuwa',['cpuWa',['../a01285.html#a8e3448a94cee26e27929d48656dcacb8',1,'mcuxClSession_Descriptor']]], + ['ctrl',['ctrl',['../a01261.html#a3b225011dfe5fd36551cb70210f9b41c',1,'mcuxClPkc_State_t']]], + ['ctx',['ctx',['../a01265.html#a2869dc5912686dc81c5076587bb83327',1,'mcuxClRandom_Config']]], + ['curveparam',['curveParam',['../a00977.html#a0396802978ddd78f753922c8dadadb18',1,'mcuxClEcc_KeyGen_Param_t::curveParam()'],['../a00981.html#a9af6c185c258baa0a6a4b0080b35b1aa',1,'mcuxClEcc_Sign_Param_t::curveParam()'],['../a00985.html#a58660c912b751cbea8360e214c482b42',1,'mcuxClEcc_Verify_Param_t::curveParam()'],['../a00989.html#a264c295859d39a968b32efbc4f03942a',1,'mcuxClEcc_PointMult_Param_t::curveParam()']]], + ['core_20api',['Core API',['../a00917.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_4.html b/components/els_pkc/doc/mcxn/html/search/all_4.html new file mode 100644 index 000000000..dd062aeae --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_4.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_4.js b/components/els_pkc/doc/mcxn/html/search/all_4.js new file mode 100644 index 000000000..6a18caa64 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_4.js @@ -0,0 +1,26 @@ +var searchData= +[ + ['data_5finvariant_5fmemory_5fcompare_2ec',['data_invariant_memory_compare.c',['../a00173.html',1,'']]], + ['data_5finvariant_5fmemory_5fcopy_2ec',['data_invariant_memory_copy.c',['../a00176.html',1,'']]], + ['dcrpt',['dcrpt',['../a00997.html#aabfd8fc5389ae7bfa2dea92c42441555',1,'mcuxClEls_AeadOption_t::dcrpt()'],['../a01009.html#ada47dbd9ac0d8ed1b171e4742ed5d73a',1,'mcuxClEls_CipherOption_t::dcrpt()']]], + ['der_5fcertificate',['der_certificate',['../a00032.html#a9aaa67299df29bf9b32ac94aa91dde50',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5fimport',['der_certificate_import',['../a00032.html#adf7528a77c2e6b48821cbed7c0337096',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5flen_5fwithout_5fsignature',['der_certificate_len_without_signature',['../a00032.html#a7edd27bd2edabd9a7a5c790b8605cd9a',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5foffset_5fpbk',['der_certificate_offset_pbk',['../a00032.html#af049ea7eafe6bdbb70ce3dd48adca426',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['data_20integrity_20core_20functionality',['Data integrity core functionality',['../a00862.html',1,'']]], + ['data_20integrity_20core_20functionality',['Data integrity core functionality',['../a00868.html',1,'']]], + ['data_20integrity_20record',['Data integrity record',['../a00869.html',1,'']]], + ['dirty',['dirty',['../a01277.html#a500aa3a1084704dbd9622a247458b9b1',1,'mcuxClSession_WorkArea']]], + ['data_20integrity_20record',['Data integrity record',['../a00863.html',1,'']]], + ['drbgentlvl',['drbgentlvl',['../a01045.html#a87b6c5ce545619bb478efcc020f862ff',1,'mcuxClEls_HwState_t']]], + ['drbgreqsub',['drbgreqsub',['../a00716.html#ga58d0f81d7d9c40f22d85d048150bbc72',1,'mcuxClEls_Common.h']]], + ['drbgreqsup',['drbgreqsup',['../a01093.html#a1519b8980b5d2615c96ac1c788014e6d',1,'mcuxClEls_HwConfig_t']]], + ['drbgtestsup',['drbgtestsup',['../a01093.html#ae70916d8e053e37a7de79db3c873cdd5',1,'mcuxClEls_HwConfig_t']]], + ['dtrgncfgloadsup',['dtrgncfgloadsup',['../a01093.html#a1655b1afaf9b84514817f11e71f21232',1,'mcuxClEls_HwConfig_t']]], + ['dtrng_5fbusy',['dtrng_busy',['../a01045.html#a05b012990a92e9deaada4a5d87ac380a',1,'mcuxClEls_HwState_t']]], + ['dtrngevalsup',['dtrngevalsup',['../a01093.html#a7ab5fc2fd5378fbf9044f6eb47b74602',1,'mcuxClEls_HwConfig_t']]], + ['duk',['duk',['../a01237.html#ab8a152b213978003ebb149be0c0ae5a7',1,'mcuxClEls_KeyProp_t']]], + ['data_20integrity_20api',['Data Integrity API',['../a00861.html',1,'']]], + ['data_20integrity_20configuration',['Data Integrity Configuration',['../a00865.html',1,'']]], + ['data_20integrity_3a_20disabled',['Data Integrity: Disabled',['../a00867.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_5.html b/components/els_pkc/doc/mcxn/html/search/all_5.html new file mode 100644 index 000000000..f0780fdd3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_5.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_5.js b/components/els_pkc/doc/mcxn/html/search/all_5.js new file mode 100644 index 000000000..ed622985f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_5.js @@ -0,0 +1,23 @@ +var searchData= +[ + ['expectation_20handling',['Expectation handling',['../a00880.html',1,'']]], + ['expectation_20handling',['Expectation handling',['../a00876.html',1,'']]], + ['ecc_5fdigest',['ecc_digest',['../a00008.html#ae951d0a54ca7834571b2870fdee3ee9c',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fpublic_5fkey',['ecc_public_key',['../a00008.html#ae2a6bb3aae38a75b559936cb2a304daa',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fpublic_5fkey_5fclient',['ecc_public_key_client',['../a00029.html#a0f8366d89d3959a37ba157fad828c3f5',1,'mcuxClEls_Tls_Master_Key_Session_Keys_example.c']]], + ['ecc_5froot_5fpublic_5fkey',['ecc_root_public_key',['../a00032.html#a961fa94f9b6e3852e50ad9417f7a6601',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['ecc_5fsignature',['ecc_signature',['../a00008.html#a0c919da2c9c7078b5c7243da9fa76322',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fsignature_5fand_5fpublic_5fkey',['ecc_signature_and_public_key',['../a00008.html#a94d4ee9f78d77b0c9e977400ad498190',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fsignature_5fr',['ecc_signature_r',['../a00008.html#a9723d2c5493f5403895e91d633105402',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecdsavfy',['ecdsavfy',['../a01045.html#a41492f22ac15d4cc4feebd517faa75ba',1,'mcuxClEls_HwState_t']]], + ['echashchl',['echashchl',['../a01117.html#ab825e88899ff7627304d25fbcc1adffd',1,'mcuxClEls_EccSignOption_t::echashchl()'],['../a01129.html#a2642a5936ec9f5c7394704161c984598',1,'mcuxClEls_EccVerifyOption_t::echashchl()']]], + ['eckxchsup',['eckxchsup',['../a01093.html#ac9e323809993203e0867e37641f7d9e0',1,'mcuxClEls_HwConfig_t']]], + ['ecsignsup',['ecsignsup',['../a01093.html#ab5a3a301e2fa7ed724b1a10db46a4dc1',1,'mcuxClEls_HwConfig_t']]], + ['ecvfysup',['ecvfysup',['../a01093.html#a082dbc1af5f81f7d76e32c01e35a6c81',1,'mcuxClEls_HwConfig_t']]], + ['elsint',['elsint',['../a01057.html#a1ceef382dbc3fbafdff1d553658c7ea9',1,'mcuxClEls_InterruptOptionEn_t::elsint()'],['../a01069.html#a8123125e41c363c03e6a671e94543d3d',1,'mcuxClEls_InterruptOptionRst_t::elsint()'],['../a01081.html#a694dd46e51d111832674fdd7827ba7a2',1,'mcuxClEls_InterruptOptionSet_t::elsint()']]], + ['enable',['enable',['../a01105.html#a60c0c05eb7acf852589b6f5b7a7c9dd3',1,'mcuxClEls_CommandCrcConfig_t']]], + ['err',['err',['../a01045.html#a5513d9d58397ac4701044421f2c8fd28',1,'mcuxClEls_HwState_t']]], + ['exit_5fcode_5ferror',['EXIT_CODE_ERROR',['../a00173.html#a1feeb5aa091fe94feea015623eeb53b7',1,'EXIT_CODE_ERROR(): data_invariant_memory_compare.c'],['../a00176.html#a1feeb5aa091fe94feea015623eeb53b7',1,'EXIT_CODE_ERROR(): data_invariant_memory_copy.c']]], + ['exit_5fcode_5fok',['EXIT_CODE_OK',['../a00173.html#ae6032b4b9390cdf8886f3b02ab488383',1,'EXIT_CODE_OK(): data_invariant_memory_compare.c'],['../a00176.html#ae6032b4b9390cdf8886f3b02ab488383',1,'EXIT_CODE_OK(): data_invariant_memory_copy.c']]], + ['extkey',['extkey',['../a00997.html#a6e8a89cd7914a8f587ae7d2888a1e7cd',1,'mcuxClEls_AeadOption_t::extkey()'],['../a01009.html#a833ce63bdab590215c35b82767479eee',1,'mcuxClEls_CipherOption_t::extkey()'],['../a01021.html#a1d6db09e93aaf0c0d428e719dbff29fe',1,'mcuxClEls_CmacOption_t::extkey()'],['../a01153.html#ab28493ba971ceb64a4fa0f741e98358d',1,'mcuxClEls_EccKeyExchOption_t::extkey()'],['../a01177.html#a4e16fabb042914665cabe00f5d6a6795',1,'mcuxClEls_HmacOption_t::extkey()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_6.html b/components/els_pkc/doc/mcxn/html/search/all_6.html new file mode 100644 index 000000000..39b0f555c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_6.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_6.js b/components/els_pkc/doc/mcxn/html/search/all_6.js new file mode 100644 index 000000000..72966ecae --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_6.js @@ -0,0 +1,14 @@ +var searchData= +[ + ['flow_20protection_20core_20functionality',['Flow protection core functionality',['../a00879.html',1,'']]], + ['function_20calling_20flow_20protection',['Function calling flow protection',['../a00881.html',1,'']]], + ['flow_20protection_20core_20functionality',['Flow protection core functionality',['../a00871.html',1,'']]], + ['function_20calling_20flow_20protection',['Function calling flow protection',['../a00872.html',1,'']]], + ['fgp',['fgp',['../a01237.html#af8743c57bd6d9dd9f329b5cafa3f5c0c',1,'mcuxClEls_KeyProp_t']]], + ['fhwo',['fhwo',['../a01237.html#a0c56a02caf693cda953b333b89a51389',1,'mcuxClEls_KeyProp_t']]], + ['finalize',['finalize',['../a01021.html#aabd3ce3a952bdd2279b7f4d0a2e22da8',1,'mcuxClEls_CmacOption_t']]], + ['frtn',['frtn',['../a01237.html#a6e2122f7d4c2706f56ec7fba67042206',1,'mcuxClEls_KeyProp_t']]], + ['flow_20protection_20api',['Flow Protection API',['../a00870.html',1,'']]], + ['flow_20protection_20configuration',['Flow Protection Configuration',['../a00877.html',1,'']]], + ['flow_20protection_3a_20secure_20counter',['Flow Protection: Secure Counter',['../a00878.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_7.html b/components/els_pkc/doc/mcxn/html/search/all_7.html new file mode 100644 index 000000000..9cd0196e7 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_7.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_7.js b/components/els_pkc/doc/mcxn/html/search/all_7.js new file mode 100644 index 000000000..f08f762c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_7.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['gdetcfgloadsup',['gdetcfgloadsup',['../a01093.html#a83e2de492b29950e62bdc159629a7e87',1,'mcuxClEls_HwConfig_t']]], + ['gdettrimsup',['gdettrimsup',['../a01093.html#a546385b574e49302ba2e748303fa91a4',1,'mcuxClEls_HwConfig_t']]], + ['gmcuxcloscca_5fscratchpad',['gmcuxClOscca_ScratchPad',['../a00482.html#ac37c24690a87ce8d10e039d46b426a2c',1,'mcuxClOscca_PlatformTypes.h']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_8.html b/components/els_pkc/doc/mcxn/html/search/all_8.html new file mode 100644 index 000000000..1e8fb9ceb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_8.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_8.js b/components/els_pkc/doc/mcxn/html/search/all_8.js new file mode 100644 index 000000000..bac640224 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_8.js @@ -0,0 +1,13 @@ +var searchData= +[ + ['hashini',['hashini',['../a01165.html#ac9b592abc979189fad34fde3ec0c163c',1,'mcuxClEls_HashOption_t']]], + ['hashld',['hashld',['../a01165.html#a4a982ed0c424187a716adba9c0c99996',1,'mcuxClEls_HashOption_t']]], + ['hashmd',['hashmd',['../a01165.html#a91c25618e98d1a9db1b1b13cfe52495f',1,'mcuxClEls_HashOption_t']]], + ['hashoe',['hashoe',['../a01165.html#a2a87b3f8cde5a5cfdbea784ca4c6a58a',1,'mcuxClEls_HashOption_t']]], + ['hashsup',['hashsup',['../a01093.html#ac5fc6ff1883c09e1ed72412f53514b13',1,'mcuxClEls_HwConfig_t']]], + ['hkdf_5falgo',['hkdf_algo',['../a01201.html#ab385e81dfad37e2cdd8faaa1521ac405',1,'mcuxClEls_HkdfOption_t']]], + ['hkdfsup',['hkdfsup',['../a01093.html#af443a864be5d2d0ab3c6a2f007fe9afe',1,'mcuxClEls_HwConfig_t']]], + ['hmacsup',['hmacsup',['../a01093.html#a4cf06c58477f35949dc0089a3a3184ce',1,'mcuxClEls_HwConfig_t']]], + ['hmac_20modes_20api',['HMAC Modes API',['../a00961.html',1,'']]], + ['hmac_20mode_20definitions',['HMAC mode definitions',['../a00783.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_9.html b/components/els_pkc/doc/mcxn/html/search/all_9.html new file mode 100644 index 000000000..27df366b2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_9.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_9.js b/components/els_pkc/doc/mcxn/html/search/all_9.js new file mode 100644 index 000000000..a7208fcdc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_9.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['initialize',['initialize',['../a01021.html#a90660bb1c9ee7d9f1d53209ab53dba4b',1,'mcuxClEls_CmacOption_t']]], + ['irq',['irq',['../a01045.html#afaa797f8db7f6252bf4ae54eb875c7fd',1,'mcuxClEls_HwState_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_a.html b/components/els_pkc/doc/mcxn/html/search/all_a.html new file mode 100644 index 000000000..63f9254d8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_a.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_a.js b/components/els_pkc/doc/mcxn/html/search/all_a.js new file mode 100644 index 000000000..b85c95f27 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_a.js @@ -0,0 +1,20 @@ +var searchData= +[ + ['key_20protection_20mechanism_20definitions',['Key protection mechanism definitions',['../a00792.html',1,'']]], + ['kactv',['kactv',['../a01237.html#ad0617bc9eea63043b1faf5fe9814ba97',1,'mcuxClEls_KeyProp_t']]], + ['kbase',['kbase',['../a01237.html#ac8a7a5dac0515241438c5086d60ffcd2',1,'mcuxClEls_KeyProp_t']]], + ['kdeletesup',['kdeletesup',['../a01093.html#aff9488c467cfca4942ba41b51c4225b7',1,'mcuxClEls_HwConfig_t']]], + ['key_5frfc3394',['key_rfc3394',['../a00032.html#adfc408cbf330d6e41a58a910f6a287d0',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['keyentrylength',['keyEntryLength',['../a01269.html#a441763378fea50af88f8cdf75648a0e6',1,'mcuxClRsa_KeyEntry_t']]], + ['keygensup',['keygensup',['../a01093.html#add6853a64d3322d8400c601277d42afb',1,'mcuxClEls_HwConfig_t']]], + ['keyinsup',['keyinsup',['../a01093.html#a10e2de8c251bc00183a2d578fb778661',1,'mcuxClEls_HwConfig_t']]], + ['keyoutsup',['keyoutsup',['../a01093.html#a6bbf59e55899238b17d7a1266d6a063a',1,'mcuxClEls_HwConfig_t']]], + ['keyprovsup',['keyprovsup',['../a01093.html#a55ac97e5d1105cd9f5ac217d05a8e0c2',1,'mcuxClEls_HwConfig_t']]], + ['keytype',['keytype',['../a01273.html#a8d0791ef8960a4316931f55f5848c3fa',1,'mcuxClRsa_Key']]], + ['kfmt',['kfmt',['../a01225.html#ae3892b035704c00a855dd43d96a21b2c',1,'mcuxClEls_KeyImportOption_t']]], + ['kgsign',['kgsign',['../a01141.html#aa20a2dd1242cfa9c945d09332db760e1',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgsign_5frnd',['kgsign_rnd',['../a01141.html#ab2d02455b74fc4f2999c8b579bd87c8d',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgsrc',['kgsrc',['../a01141.html#aa60e98c0d7570daa80ab5536ebf71d94',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgtypedh',['kgtypedh',['../a01141.html#ade3f3190f07c3a1b8a5948988d3b85d5',1,'mcuxClEls_EccKeyGenOption_t']]], + ['ksize',['ksize',['../a01237.html#a49806c0136f41b701675799cb69d34d5',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_b.html b/components/els_pkc/doc/mcxn/html/search/all_b.html new file mode 100644 index 000000000..44ae3e475 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_b.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_b.js b/components/els_pkc/doc/mcxn/html/search/all_b.js new file mode 100644 index 000000000..607e15a0f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_b.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['looping_20flow_20protection',['Looping flow protection',['../a00882.html',1,'']]], + ['looping_20flow_20protection',['Looping flow protection',['../a00873.html',1,'']]], + ['lastinit',['lastinit',['../a00997.html#a70ab6c857c7ae2e10b2f0580e4ea3669',1,'mcuxClEls_AeadOption_t']]], + ['level',['level',['../a01033.html#a362c318252fad3db6e55fde7dac2572f',1,'mcuxClEls_HwVersion_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_c.html b/components/els_pkc/doc/mcxn/html/search/all_c.html new file mode 100644 index 000000000..3de15867d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_c.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_c.js b/components/els_pkc/doc/mcxn/html/search/all_c.js new file mode 100644 index 000000000..014ed962f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_c.js @@ -0,0 +1,1794 @@ +var searchData= +[ + ['multi_2dpart_20cipher_20interfaces',['Multi-part Cipher interfaces',['../a00675.html',1,'']]], + ['major',['major',['../a01033.html#a0c4765f9784a475579e0fd433a753011',1,'mcuxClEls_HwVersion_t']]], + ['mcux_5fcssl_5fdi_5falloc',['MCUX_CSSL_DI_ALLOC',['../a00862.html#ga7f64db7a5134579f6225fc87a04c9e10',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5falloc_5fimpl',['MCUX_CSSL_DI_ALLOC_IMPL',['../a00868.html#ga923d5186da2eecf410950262961e03c5',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5fcheck',['MCUX_CSSL_DI_CHECK',['../a00862.html#ga86a850875eca35952e2c3a8312364896',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5fcheck_5ffailed',['MCUX_CSSL_DI_CHECK_FAILED',['../a00862.html#ga836c5e13eae4d1fdcfe33a41051c26b5',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5fcheck_5ffailed_5fimpl',['MCUX_CSSL_DI_CHECK_FAILED_IMPL',['../a00868.html#ga381a9c96de77bfc8d099d9ebcc54f71b',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5fcheck_5fimpl',['MCUX_CSSL_DI_CHECK_IMPL',['../a00868.html#gac19903f4bcc14df44ce3779e82eeec8b',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5fcheck_5fpassed',['MCUX_CSSL_DI_CHECK_PASSED',['../a00862.html#gaf795c9830ecd5c53d21ae5efb05716c0',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5fcheck_5fpassed_5fimpl',['MCUX_CSSL_DI_CHECK_PASSED_IMPL',['../a00868.html#ga4deb1836544c454f189e5aefe3a16b90',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5fexpunge',['MCUX_CSSL_DI_EXPUNGE',['../a00863.html#ga3e10066c4efffa9040982cde10a52076',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5fexpunge_5fimpl',['MCUX_CSSL_DI_EXPUNGE_IMPL',['../a00869.html#gaac8a8ea1888347d41f58f27f11c9caab',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5finit',['MCUX_CSSL_DI_INIT',['../a00862.html#ga8e9f35be6109155f823f827707af31fb',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5finit_5fdefault_5fvalue',['MCUX_CSSL_DI_INIT_DEFAULT_VALUE',['../a00862.html#ga43f4285ae50273c0c9ddd7bb4afa123d',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5finit_5fimpl',['MCUX_CSSL_DI_INIT_IMPL',['../a00868.html#gadc0c4c5c446999ac332e799edbe04249',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5frecord',['MCUX_CSSL_DI_RECORD',['../a00863.html#ga885885837b7340002b9782ffc41e4842',1,'mcuxCsslDataIntegrity.h']]], + ['mcux_5fcssl_5fdi_5frecord_5fimpl',['MCUX_CSSL_DI_RECORD_IMPL',['../a00869.html#ga528d28a827727ba460795460a30cccfd',1,'mcuxCsslDataIntegrity_None.h']]], + ['mcux_5fcssl_5fdi_5fuse_5fnone',['MCUX_CSSL_DI_USE_NONE',['../a00865.html#ga4f0cea555852c5171e55303b6cb062be',1,'mcuxCsslDataIntegrity_Cfg.h']]], + ['mcux_5fcssl_5fdi_5fuse_5fsecure_5fcounter',['MCUX_CSSL_DI_USE_SECURE_COUNTER',['../a00865.html#gad14940e758b00b26f2e699b4fc0144bb',1,'mcuxCsslDataIntegrity_Cfg.h']]], + ['mcux_5fcssl_5ffp_5fassert',['MCUX_CSSL_FP_ASSERT',['../a00876.html#ga301b8f23ac6981e62649c8f571a6c6eb',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fassert_5fcallback',['MCUX_CSSL_FP_ASSERT_CALLBACK',['../a00880.html#ga0c29c395a9104c6d918091b12f63ca74',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fassert_5fimpl',['MCUX_CSSL_FP_ASSERT_IMPL',['../a00880.html#ga391e0f29868a1dd17bd0d23a4737c129',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fdecl',['MCUX_CSSL_FP_BRANCH_DECL',['../a00874.html#ga1406430491edf42797f1fbb6fec6d400',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fdecl_5fimpl',['MCUX_CSSL_FP_BRANCH_DECL_IMPL',['../a00883.html#gaf4e4c76c10150fa1b5e8944f33720c44',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fid',['MCUX_CSSL_FP_BRANCH_ID',['../a00883.html#ga0cd46ecad6c5ab6ef4ba6ff18a79b1eb',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fnegative',['MCUX_CSSL_FP_BRANCH_NEGATIVE',['../a00874.html#ga67a87d7f006f7f4fc09f1a0b93d21043',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fnegative_5fimpl',['MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL',['../a00883.html#gaf7f462f39963033ea44c0f7c7f41a76f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fnegative_5fimpl1',['MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1',['../a00883.html#ga8547d895809dfb59bf0709fbc49e5483',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fnegative_5fimpln',['MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn',['../a00883.html#ga49e07e6c9d6faf768cd464d4cdb4a881',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fnegative_5fvalue',['MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE',['../a00883.html#ga82df96ef3fb0b8718bff46f3f4cd9a5c',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fpositive',['MCUX_CSSL_FP_BRANCH_POSITIVE',['../a00874.html#ga9aaebd3ae72dfb08a7a286c9cf02898c',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fpositive_5fimpl',['MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL',['../a00883.html#gadff057603f2018ef9440b0e981353a48',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fpositive_5fimpl1',['MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1',['../a00883.html#ga54981abcad9da3f0d9a347ec3d0d2953',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fpositive_5fimpln',['MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn',['../a00883.html#ga3232cfdb56c441fe5c6a914e38528494',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fpositive_5fvalue',['MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE',['../a00883.html#gafd8b6619c2105004d85eee8581c4969c',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fscenario_5fimpl',['MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL',['../a00883.html#gab65273365a2139c4e6693664c8dc7e36',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fimpl',['MCUX_CSSL_FP_BRANCH_TAKEN_IMPL',['../a00883.html#ga640bbb8417eb2e2fd975431d15a9364d',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fnegative',['MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE',['../a00874.html#ga7ca1b74234f560a110647fbc24fec3f9',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fnegative_5fimpl',['MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL',['../a00883.html#ga2142ecf918cf320bf1b15b8d8cfe5253',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fnegative_5fimpl1',['MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1',['../a00883.html#gaff88c9879207f5f1d7ab643fdd9c278f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fnegative_5fimpl2',['MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2',['../a00883.html#gae5068ae5b0a47a9d366e832f255e9ce9',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fpositive',['MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE',['../a00874.html#ga99db0902665c118dbfeacd73dd8c8672',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fpositive_5fimpl',['MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL',['../a00883.html#gaae07d1c658effb2daa3df7a75214b0f1',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fpositive_5fimpl1',['MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1',['../a00883.html#ga29b42c7c0d701dc98159e7e04aafcd93',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5ftaken_5fpositive_5fimpl2',['MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2',['../a00883.html#ga8a3b0d047ea142e74e5bef729508f683',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fbranch_5fvalue',['MCUX_CSSL_FP_BRANCH_VALUE',['../a00883.html#ga24770b08dbac22e0ca123f737f9710b3',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fconditional',['MCUX_CSSL_FP_CONDITIONAL',['../a00876.html#ga24a55fecde25d3aa0a227814345b9714',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fconditional_5fimpl',['MCUX_CSSL_FP_CONDITIONAL_IMPL',['../a00879.html#ga643cc00e2fecb3e73de572797618ad35',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fcounter_5fcompressed',['MCUX_CSSL_FP_COUNTER_COMPRESSED',['../a00881.html#ga2aa4e71591c9e48638a5733885a77972',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fcounter_5fstmt',['MCUX_CSSL_FP_COUNTER_STMT',['../a00872.html#gacb5d4268cc93c95b8e69da19d74de79f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fdecl_5fimpl',['MCUX_CSSL_FP_DECL_IMPL',['../a00879.html#gab0919c85280cbf0aa51daaec18cb524a',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fdecl_5fname',['MCUX_CSSL_FP_DECL_NAME',['../a00879.html#ga116350fa9fa1a37d3fca3d3a15f010f3',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fexpect',['MCUX_CSSL_FP_EXPECT',['../a00876.html#ga83db474d65df2b52abea45293f9684d0',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fexpect_5fimpl',['MCUX_CSSL_FP_EXPECT_IMPL',['../a00880.html#ga7be0ed334bcf634f81d5d4b93a4c1657',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fexpectations',['MCUX_CSSL_FP_EXPECTATIONS',['../a00880.html#ga173c3887e1d02b5cace9e622d0a3225b',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall',['MCUX_CSSL_FP_FUNCTION_CALL',['../a00872.html#ga9517fd35bea64a62f1cd3bf58a6218ef',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fbegin',['MCUX_CSSL_FP_FUNCTION_CALL_BEGIN',['../a00872.html#ga8a9b1ebbc02c8195618a339aa8e0003d',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fbegin_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL',['../a00881.html#gab0ff0e165d943faba9241de4f57c2d75',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fend',['MCUX_CSSL_FP_FUNCTION_CALL_END',['../a00872.html#gac4362de43d0e67ba6fac0057eb38008d',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fend_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL',['../a00881.html#ga260f6caaf5d3f526e664835f6889fec5',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_IMPL',['../a00881.html#ga6dea11ddfc9ee7a58fd4c002bd2aa298',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fprotected',['MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED',['../a00872.html#gac861d63fbf4a985b570845c02c5e412f',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fprotected_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL',['../a00881.html#gacf0993520e666067ce074749c90e3d84',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid',['MCUX_CSSL_FP_FUNCTION_CALL_VOID',['../a00872.html#ga8d8dfc8f87971ee861d0bc77118a97cb',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fbegin',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN',['../a00872.html#ga268f9c22cb59586556e0cbb21ac3320e',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fbegin_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL',['../a00881.html#ga8f9fbedb24cf72ef01632cc7a2df1f91',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fend',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_END',['../a00872.html#ga30de6960e0ce17187bce680980617f38',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fend_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL',['../a00881.html#gae44806e59bfa6e136c7df9c641809621',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL',['../a00614.html#aac90557cb39d20ea0c0fda3985497b45',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fprotected',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED',['../a00872.html#ga5544a5ce0e2478832eb1eacf339b4475',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fprotected_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL',['../a00881.html#gadc1544cfd424c8ea5e09a97a6b48defa',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcalled',['MCUX_CSSL_FP_FUNCTION_CALLED',['../a00872.html#gac16ad6597579a02a30ada37f86f216d5',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fcalled_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALLED_IMPL',['../a00881.html#ga387940e23bd51390165c5cdffe5b2e6e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fdecl',['MCUX_CSSL_FP_FUNCTION_DECL',['../a00872.html#ga21e1a3f12fd2772ca92216b888b3bdff',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fdecl_5fimpl',['MCUX_CSSL_FP_FUNCTION_DECL_IMPL',['../a00881.html#gad18deaf144ed415268a00f1634552e22',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fdef',['MCUX_CSSL_FP_FUNCTION_DEF',['../a00872.html#ga7c1d29e4d644c86f11e337e30dd2b210',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fdef_5fimpl',['MCUX_CSSL_FP_FUNCTION_DEF_IMPL',['../a00881.html#gae834db0dba75df2b3f18e773b6f054b8',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentered',['MCUX_CSSL_FP_FUNCTION_ENTERED',['../a00872.html#ga9f7aa860f353079a6da5188bd18b977c',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentered_5fimpl',['MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL',['../a00881.html#gaaf3937045ab2420f95b209d63d380b0e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentry',['MCUX_CSSL_FP_FUNCTION_ENTRY',['../a00872.html#ga2fda8e2a0e7d862b113b28bcc1b4d9bb',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentry_5fimpl',['MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL',['../a00881.html#gade96ac1fafaf20164fda6e40ec29b111',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentry_5fimpl1',['MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1',['../a00881.html#gab4ce00a3b45306924fe9b0b6664bde0a',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fentry_5fimpln',['MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn',['../a00881.html#ga1a8ea6cc710859bcadb79a488dd8db25',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit',['MCUX_CSSL_FP_FUNCTION_EXIT',['../a00872.html#ga9d9934b6d02da9505dd20ac36236b61d',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fimpl',['MCUX_CSSL_FP_FUNCTION_EXIT_IMPL',['../a00881.html#gaa04b0a2008a71b07057236083492ff59',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fimpl1',['MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1',['../a00881.html#gafbffa86482e7c82632c29b7b47268cc0',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fimpl2',['MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2',['../a00881.html#ga9c6252af0f1985853ed349c5d1ae1788',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fimpln',['MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn',['../a00881.html#gadff771aa8e6ddffa0943c1e05d143d3b',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fvoid',['MCUX_CSSL_FP_FUNCTION_EXIT_VOID',['../a00872.html#ga4c6863806f0054719824891271a5f598',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fvoid_5fimpl',['MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL',['../a00881.html#gada3bd3043e47a7155cbd6f48a19d8a7b',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fvoid_5fimpl1',['MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1',['../a00881.html#ga7d4f6f29ec46da78d39c6835c2353c43',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fwith_5fcheck',['MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK',['../a00872.html#ga7c4b79e79eecb68ef4e4fb4fb9fbc1b8',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fwith_5fcheck_5fimpl',['MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL',['../a00881.html#ga03a6226c405fe4012598d538b751d8e0',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fwith_5fcheck_5fimpl3',['MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3',['../a00881.html#gad1f605647ff376aba41b2362d8d02def',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fexit_5fwith_5fcheck_5fimpln',['MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn',['../a00881.html#ga98f3eec493dd7bf7b26f064c31302c73',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fid',['MCUX_CSSL_FP_FUNCTION_ID',['../a00881.html#ga479eda7e7852481c11efbc1959aee5ab',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fid_5fentry_5fmask',['MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK',['../a00881.html#gaaee8a28145962c5b60693126fb43f577',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fid_5fentry_5fpart',['MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART',['../a00881.html#gafee5e352ad736687d3b51475705cb7e3',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fid_5fexit_5fpart',['MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART',['../a00881.html#ga0b9936d950500136323df9b790a53cbf',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fpointer',['MCUX_CSSL_FP_FUNCTION_POINTER',['../a00872.html#gab9bdb43ee02202c53d729847dea78ccc',1,'MCUX_CSSL_FP_FUNCTION_POINTER(): mcuxCsslFlowProtection.h'],['../a00963.html#gaf821ec5ad694746ba28321b2bb802236',1,'MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcInitializeEngine_t, typedef void(*mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState)): mcuxClPkc_Functions.h'],['../a00963.html#ga4ad3a9a17b2090a8d761fcd9c9c86218',1,'MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcDeInitializeEngine_t, typedef void(*mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState)): mcuxClPkc_Functions.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fpointer_5fimpl',['MCUX_CSSL_FP_FUNCTION_POINTER_IMPL',['../a00611.html#a7d3ca21c8f547090d91d2d2b77607f45',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fvalue',['MCUX_CSSL_FP_FUNCTION_VALUE',['../a00881.html#gad9e9dfa4b8b661a90fca8a8348d85797',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fid_5fimpl',['MCUX_CSSL_FP_ID_IMPL',['../a00879.html#ga6bc8b7f3f35325ca98c1b5d0f7658061',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fdecl',['MCUX_CSSL_FP_LOOP_DECL',['../a00873.html#ga96df84766aff763718a84dd44246af38',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5floop_5fdecl_5fimpl',['MCUX_CSSL_FP_LOOP_DECL_IMPL',['../a00882.html#gaf96c3a513125fcf430cbf3b5fe595e4f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fid',['MCUX_CSSL_FP_LOOP_ID',['../a00882.html#ga995fa3b11e4cc00e87135ada7aef8d5e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiteration',['MCUX_CSSL_FP_LOOP_ITERATION',['../a00873.html#gae7942657c4fac73115908f05c382cc86',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiteration_5fimpl',['MCUX_CSSL_FP_LOOP_ITERATION_IMPL',['../a00882.html#ga5d124a3ac8175c17ef669fde72edb64f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiteration_5fimpl1',['MCUX_CSSL_FP_LOOP_ITERATION_IMPL1',['../a00882.html#ga4c1cfe8ca5990c4c17f5193bcfe0df7e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiteration_5fimpln',['MCUX_CSSL_FP_LOOP_ITERATION_IMPLn',['../a00882.html#ga60705dcec1d1ad92e356e66725d3bf3e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiterations',['MCUX_CSSL_FP_LOOP_ITERATIONS',['../a00873.html#gae5aabc3339a46a799d1fefd1095a4898',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5floop_5fiterations_5fimpl',['MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL',['../a00882.html#gaae28d69224446d35fe5e09fcde65a16b',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5floop_5fvalue',['MCUX_CSSL_FP_LOOP_VALUE',['../a00882.html#ga7eef9d81d7343fd127b4b05c14944d1c',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fprotected_5ftype',['MCUX_CSSL_FP_PROTECTED_TYPE',['../a00872.html#ga6cb5dab960bed02a02ad907bd2a54a4b',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fprotected_5ftype_5fimpl',['MCUX_CSSL_FP_PROTECTED_TYPE_IMPL',['../a00881.html#ga8c5845ea3e1b932b969db83484b26ecf',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5fprotection_5fmask',['MCUX_CSSL_FP_PROTECTION_MASK',['../a00881.html#ga8778012875929ec230fcfdf10ff9500f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fprotection_5foffset',['MCUX_CSSL_FP_PROTECTION_OFFSET',['../a00881.html#ga4e64bd8d03d3e33458ee8a7fccb37c45',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fprotection_5ftoken',['MCUX_CSSL_FP_PROTECTION_TOKEN',['../a00872.html#ga8d5c6d7d0c0aba35d4a841e964d5d607',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fprotection_5ftoken_5fimpl',['MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL',['../a00881.html#ga5da930d2d73279d4361af98b96771185',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fprotection_5ftoken_5fvalue',['MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE',['../a00881.html#gaeba1f8f690177515b77e499d9d99b4e3',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fresult',['MCUX_CSSL_FP_RESULT',['../a00872.html#ga3919086f41a5a26003dd28b528aa473f',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fresult_5fimpl',['MCUX_CSSL_FP_RESULT_IMPL',['../a00881.html#ga2464ae5055d514ca07dfd0a912d66233',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fresult_5fmask',['MCUX_CSSL_FP_RESULT_MASK',['../a00881.html#ga841d36aa501a694ec13c5f1cc0c55d18',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fresult_5foffset',['MCUX_CSSL_FP_RESULT_OFFSET',['../a00881.html#ga7ec1aab92504892fe1f18c2890298b21',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fresult_5fvalue',['MCUX_CSSL_FP_RESULT_VALUE',['../a00881.html#ga8fa4f755ce171f2497d143b627478aa8',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fcase',['MCUX_CSSL_FP_SWITCH_CASE',['../a00875.html#gab3a2723c9a344c245ff6b596aaee5414',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fcase_5fimpl',['MCUX_CSSL_FP_SWITCH_CASE_IMPL',['../a00884.html#ga4fac747213aeed1e92363a2bdd68406b',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fcase_5fimpl2',['MCUX_CSSL_FP_SWITCH_CASE_IMPL2',['../a00884.html#ga7228ed734302bc58312a7f120f437ea4',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fcase_5fimpln',['MCUX_CSSL_FP_SWITCH_CASE_IMPLn',['../a00884.html#ga5f9c86c89dde886bc8a4d0685c193b35',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdecl',['MCUX_CSSL_FP_SWITCH_DECL',['../a00875.html#gafc01be288246642c1b2779b69188adad',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdecl_5fimpl',['MCUX_CSSL_FP_SWITCH_DECL_IMPL',['../a00884.html#ga685b8b131aa17d9a2fbb215cf282e47e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdefault',['MCUX_CSSL_FP_SWITCH_DEFAULT',['../a00875.html#gaebd999394afa94e2c3e3b64f68d85e2a',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdefault_5fimpl',['MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL',['../a00884.html#gade7e9242949c3b56a6c26d4f9baa4184',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdefault_5fimpl1',['MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1',['../a00884.html#gaf7458c44a5c0237192b047645b9fef44',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdefault_5fimpln',['MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn',['../a00884.html#gac3dcce63f39b86956e2535b5277781e7',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fdefault_5fvalue',['MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE',['../a00884.html#ga3c29758b5fe14aacedaebdf5a77a2a24',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fid',['MCUX_CSSL_FP_SWITCH_ID',['../a00884.html#gaf1c0885504f90cfa3da18399d96b1319',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken',['MCUX_CSSL_FP_SWITCH_TAKEN',['../a00875.html#gaa620180722a4eaa8e7370a92d2bd18d9',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fdefault',['MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT',['../a00875.html#gac011e972fff0f38d704edfeadce256cd',1,'mcuxCsslFlowProtection.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fdefault_5fimpl',['MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL',['../a00884.html#gadd39e2b4cb02e9c849a289302465a8ff',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fdefault_5fimpl1',['MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1',['../a00884.html#gaef7299bb6aa7dc7a367edae023cc2a41',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fdefault_5fimpl2',['MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2',['../a00884.html#gaf4a47979ed6e58b347658038ed393210',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fimpl',['MCUX_CSSL_FP_SWITCH_TAKEN_IMPL',['../a00884.html#ga2cea4b8acd163c7b4877267c4221a9d4',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fimpl2',['MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2',['../a00884.html#ga74061d2cc9faf009465c92cf7fa2806f',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5ftaken_5fimpl3',['MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3',['../a00884.html#gae6c4eb02ea889928868e6eae6d4fac9e',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fswitch_5fvalue',['MCUX_CSSL_FP_SWITCH_VALUE',['../a00884.html#ga60aebfce23f0dc04ef9035404526a049',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5ffp_5fuse_5fcode_5fsignature',['MCUX_CSSL_FP_USE_CODE_SIGNATURE',['../a00877.html#gaeaecd08382d1bf7542d523e67c15b90b',1,'mcuxCsslFlowProtection_Cfg.h']]], + ['mcux_5fcssl_5ffp_5fuse_5fnone',['MCUX_CSSL_FP_USE_NONE',['../a00877.html#ga8fcbc78b6821d4cd6ea67bdc3d4e3ba7',1,'mcuxCsslFlowProtection_Cfg.h']]], + ['mcux_5fcssl_5ffp_5fuse_5fsecure_5fcounter',['MCUX_CSSL_FP_USE_SECURE_COUNTER',['../a00877.html#ga645fafaa87e927ec807c9679dfa6d74e',1,'mcuxCsslFlowProtection_Cfg.h']]], + ['mcux_5fcssl_5ffp_5fvoid_5fexpectation_5fimpl',['MCUX_CSSL_FP_VOID_EXPECTATION_IMPL',['../a00880.html#ga4ea20ab3d4d080887fdfc12f6c7f6bab',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcux_5fcssl_5fsc_5fadd',['MCUX_CSSL_SC_ADD',['../a00903.html#gaebd375f1bd8786078a00d2d8326c23aa',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x1',['MCUX_CSSL_SC_ADD_0x1',['../a00903.html#gaca21d031efe80f6dd488932f0e335842',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x10',['MCUX_CSSL_SC_ADD_0x10',['../a00903.html#gab6aafbee4e72e020907dc9f382ac6b65',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x100',['MCUX_CSSL_SC_ADD_0x100',['../a00903.html#gaa7340bed15dc7026e9d2a0a9a1464cbf',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x100_5fimpl',['MCUX_CSSL_SC_ADD_0X100_IMPL',['../a00909.html#gafb5fa6d42145120126b00ab3707711be',1,'MCUX_CSSL_SC_ADD_0X100_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00914.html#gafb5fa6d42145120126b00ab3707711be',1,'MCUX_CSSL_SC_ADD_0X100_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x10_5fimpl',['MCUX_CSSL_SC_ADD_0X10_IMPL',['../a00909.html#gaac716380d3c29a995745053bb6915044',1,'MCUX_CSSL_SC_ADD_0X10_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00914.html#gaac716380d3c29a995745053bb6915044',1,'MCUX_CSSL_SC_ADD_0X10_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fadd_5f0x1_5fimpl',['MCUX_CSSL_SC_ADD_0X1_IMPL',['../a00909.html#ga45a909bcf29531036b1aad68ac8b0afb',1,'MCUX_CSSL_SC_ADD_0X1_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00914.html#ga45a909bcf29531036b1aad68ac8b0afb',1,'MCUX_CSSL_SC_ADD_0X1_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fadd_5fimpl',['MCUX_CSSL_SC_ADD_IMPL',['../a00909.html#gaa4a21360f6c3d08fc777879e4f4551ed',1,'MCUX_CSSL_SC_ADD_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00914.html#gaa4a21360f6c3d08fc777879e4f4551ed',1,'MCUX_CSSL_SC_ADD_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fadd_5fon_5fcall',['MCUX_CSSL_SC_ADD_ON_CALL',['../a00903.html#ga4103d92fd5d240d12ace815c84d9d6f1',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fadd_5fon_5fcall_5fimpl',['MCUX_CSSL_SC_ADD_ON_CALL_IMPL',['../a00909.html#ga9c0484fdff900c04462d668a0870bf33',1,'MCUX_CSSL_SC_ADD_ON_CALL_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00914.html#ga9c0484fdff900c04462d668a0870bf33',1,'MCUX_CSSL_SC_ADD_ON_CALL_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5falloc',['MCUX_CSSL_SC_ALLOC',['../a00902.html#gae251628d245da18aa3c7aff92dbc8731',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5falloc_5fimpl',['MCUX_CSSL_SC_ALLOC_IMPL',['../a00908.html#gad413de64b4cc420be30b5278fd5083d0',1,'MCUX_CSSL_SC_ALLOC_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gad413de64b4cc420be30b5278fd5083d0',1,'MCUX_CSSL_SC_ALLOC_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fassign',['MCUX_CSSL_SC_ASSIGN',['../a00905.html#ga019087e1fe72c9ef7b1e5f9e19aa7493',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fassign_5fimpl',['MCUX_CSSL_SC_ASSIGN_IMPL',['../a00911.html#ga87e741e67b757bf719409530176e56b9',1,'MCUX_CSSL_SC_ASSIGN_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00916.html#ga87e741e67b757bf719409530176e56b9',1,'MCUX_CSSL_SC_ASSIGN_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fbalancing_5fvalue_5ftype_5fimpl',['MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL',['../a00908.html#ga919150430f3033eb5d6c8025216548b3',1,'MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#ga919150430f3033eb5d6c8025216548b3',1,'MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fcheck',['MCUX_CSSL_SC_CHECK',['../a00902.html#ga09971b594be3d77043145756712bd1bb',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fcheck_5ffailed',['MCUX_CSSL_SC_CHECK_FAILED',['../a00902.html#ga9c4c267ec8ea4df79b0f5affe471ee7b',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fcheck_5ffailed_5fimpl',['MCUX_CSSL_SC_CHECK_FAILED_IMPL',['../a00908.html#gac1d032d150bd774f86bbb50fdfa0ee19',1,'MCUX_CSSL_SC_CHECK_FAILED_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gac1d032d150bd774f86bbb50fdfa0ee19',1,'MCUX_CSSL_SC_CHECK_FAILED_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fcheck_5fimpl',['MCUX_CSSL_SC_CHECK_IMPL',['../a00908.html#gaf15120a3e9f4edf59cb5b42860fe86dd',1,'MCUX_CSSL_SC_CHECK_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gaf15120a3e9f4edf59cb5b42860fe86dd',1,'MCUX_CSSL_SC_CHECK_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fcheck_5fpassed',['MCUX_CSSL_SC_CHECK_PASSED',['../a00902.html#ga1f0a9fc2ca02b221c00acb56c1e93b9e',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fcheck_5fpassed_5fimpl',['MCUX_CSSL_SC_CHECK_PASSED_IMPL',['../a00908.html#ga417202932e9a8a880e23e8a3321309ac',1,'MCUX_CSSL_SC_CHECK_PASSED_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#ga417202932e9a8a880e23e8a3321309ac',1,'MCUX_CSSL_SC_CHECK_PASSED_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fcounter_5fname',['MCUX_CSSL_SC_COUNTER_NAME',['../a00913.html#ga7cf637fa768fe3fe088dbf367ad46b8a',1,'mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fcounter_5ftype_5fimpl',['MCUX_CSSL_SC_COUNTER_TYPE_IMPL',['../a00908.html#gaafa4d13a4e311121551b8e49662c3470',1,'MCUX_CSSL_SC_COUNTER_TYPE_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gaafa4d13a4e311121551b8e49662c3470',1,'MCUX_CSSL_SC_COUNTER_TYPE_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5finit',['MCUX_CSSL_SC_INIT',['../a00902.html#ga25e2c92db2dee1b0cd339d3a8ca4112a',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5finit_5fimpl',['MCUX_CSSL_SC_INIT_IMPL',['../a00908.html#gaf8d9ebeb36322ea86fc8766afa84bc3f',1,'MCUX_CSSL_SC_INIT_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gaf8d9ebeb36322ea86fc8766afa84bc3f',1,'MCUX_CSSL_SC_INIT_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fsub',['MCUX_CSSL_SC_SUB',['../a00904.html#ga270e4467ff02a10df72b1da177385858',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x1',['MCUX_CSSL_SC_SUB_0x1',['../a00904.html#ga7df8a7a4e7798142da2e668ca21f3a5e',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x10',['MCUX_CSSL_SC_SUB_0x10',['../a00904.html#gabb6f649421ad8405aa47812615301933',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x100',['MCUX_CSSL_SC_SUB_0x100',['../a00904.html#gacf7c177e9dbd78d8c5a81fe3b9b4b5cb',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x100_5fimpl',['MCUX_CSSL_SC_SUB_0X100_IMPL',['../a00910.html#gaa4a6dba75f476d29637e005dc8272083',1,'MCUX_CSSL_SC_SUB_0X100_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00915.html#gaa4a6dba75f476d29637e005dc8272083',1,'MCUX_CSSL_SC_SUB_0X100_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x10_5fimpl',['MCUX_CSSL_SC_SUB_0X10_IMPL',['../a00910.html#gafa9701e3c0f7e757573c4bfcdae22959',1,'MCUX_CSSL_SC_SUB_0X10_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00915.html#gafa9701e3c0f7e757573c4bfcdae22959',1,'MCUX_CSSL_SC_SUB_0X10_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fsub_5f0x1_5fimpl',['MCUX_CSSL_SC_SUB_0X1_IMPL',['../a00910.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8',1,'MCUX_CSSL_SC_SUB_0X1_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00915.html#ga0ffac921b9dfcb2fcf8796e0a4e1b0c8',1,'MCUX_CSSL_SC_SUB_0X1_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fsub_5fimpl',['MCUX_CSSL_SC_SUB_IMPL',['../a00910.html#gaca0635e01e8eef97f9a06a50b24d0941',1,'MCUX_CSSL_SC_SUB_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00915.html#gaca0635e01e8eef97f9a06a50b24d0941',1,'MCUX_CSSL_SC_SUB_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fhw_5fcdog',['MCUX_CSSL_SC_USE_HW_CDOG',['../a00906.html#gaa488aa67a604f34f36c1a99b07a6ab71',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fhw_5fs3scm',['MCUX_CSSL_SC_USE_HW_S3SCM',['../a00906.html#gaf65f19a392d0dda41627f1e4ef3f2291',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fhw_5fscm',['MCUX_CSSL_SC_USE_HW_SCM',['../a00906.html#gae5b47bf9fecd4e15c34cb859cad286a4',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fhybrid_5flocal_5fcdog',['MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG',['../a00906.html#gab32cca78e592e73eb1d15d06be994839',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fnone',['MCUX_CSSL_SC_USE_NONE',['../a00906.html#ga8141a2d6da07d7137207fb35505a6cb0',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fsw_5fcallback',['MCUX_CSSL_SC_USE_SW_CALLBACK',['../a00906.html#ga788677fbf1a036b432007aa84a2879ad',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fsw_5fcontext',['MCUX_CSSL_SC_USE_SW_CONTEXT',['../a00906.html#gaff2c61772a19bdf2e5038b674ea04128',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fsw_5fglobal',['MCUX_CSSL_SC_USE_SW_GLOBAL',['../a00906.html#ga8743f66cbadb2592671510ed3160dc09',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fuse_5fsw_5flocal',['MCUX_CSSL_SC_USE_SW_LOCAL',['../a00906.html#ga841fe66e0a59b9c720854ff0ee2c4678',1,'mcuxCsslSecureCounter_Cfg.h']]], + ['mcux_5fcssl_5fsc_5fvalue',['MCUX_CSSL_SC_VALUE',['../a00905.html#ga2b674477b2a4111ad89fd95598c36e69',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fvalue_5fimpl',['MCUX_CSSL_SC_VALUE_IMPL',['../a00911.html#ga5ebadc1cc4cc3e849527adcf3da5c258',1,'MCUX_CSSL_SC_VALUE_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00916.html#ga5ebadc1cc4cc3e849527adcf3da5c258',1,'MCUX_CSSL_SC_VALUE_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcux_5fcssl_5fsc_5fvalue_5ftype',['MCUX_CSSL_SC_VALUE_TYPE',['../a00902.html#ga614b8a54453d52240162efb2118db47f',1,'mcuxCsslSecureCounter.h']]], + ['mcux_5fcssl_5fsc_5fvalue_5ftype_5fimpl',['MCUX_CSSL_SC_VALUE_TYPE_IMPL',['../a00908.html#gaf84485a6eb6bbcd39933ff1abcb3ee61',1,'MCUX_CSSL_SC_VALUE_TYPE_IMPL(): mcuxCsslSecureCounter_None.h'],['../a00913.html#gaf84485a6eb6bbcd39933ff1abcb3ee61',1,'MCUX_CSSL_SC_VALUE_TYPE_IMPL(): mcuxCsslSecureCounter_SW_Local.h']]], + ['mcuxcl_5fapi',['MCUXCL_API',['../a00200.html#a3a2aa1bfb4cd2f30cd208b1f53fd3238',1,'mcuxCl_clns.h']]], + ['mcuxcl_5fbuffer_5ft',['mcuxCl_Buffer_t',['../a00678.html#gaa29a7ef1a28440e75f2c0d007011ae2b',1,'mcuxClCore_Buffer.h']]], + ['mcuxcl_5fclns_2eh',['mcuxCl_clns.h',['../a00200.html',1,'']]], + ['mcuxcl_5fgetversion',['mcuxCl_GetVersion',['../a00200.html#a41e47552892b4e05c396de4ab626aaa2',1,'mcuxCl_clns.h']]], + ['mcuxcl_5finputbuffer_5ft',['mcuxCl_InputBuffer_t',['../a00678.html#gae1ad733bc1a05d9dc6e9fb8b0e9b436d',1,'mcuxClCore_Buffer.h']]], + ['mcuxcl_5fversion',['MCUXCL_VERSION',['../a00200.html#aaac021cf1e464db8ec89a2313860577b',1,'mcuxCl_clns.h']]], + ['mcuxcl_5fversion_5fmax_5fsize',['MCUXCL_VERSION_MAX_SIZE',['../a00200.html#aac49d4488517875c56358012b911da08',1,'mcuxCl_clns.h']]], + ['mcuxclaead',['mcuxClAead',['../a00661.html',1,'']]], + ['mcuxclaead_2eh',['mcuxClAead.h',['../a00203.html',1,'']]], + ['mcuxclaead_5fconstants',['mcuxClAead_Constants',['../a00662.html',1,'']]], + ['mcuxclaead_5fconstants_2eh',['mcuxClAead_Constants.h',['../a00206.html',1,'']]], + ['mcuxclaead_5fcontext_5ft',['mcuxClAead_Context_t',['../a00666.html#gaf67b42507181f9793498bfaaab35a48a',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fcrypt',['mcuxClAead_crypt',['../a00664.html#gad0713168358588f9550468bf1ef7cfbb',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5ffinish',['mcuxClAead_finish',['../a00665.html#ga2b18aa6585e4d229d7ccfdd34f3f9dba',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5ffunctions_2eh',['mcuxClAead_Functions.h',['../a00209.html',1,'']]], + ['mcuxclaead_5finit',['mcuxClAead_init',['../a00665.html#gaeb2451aba7d135f7af05e94f9b095fae',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fmemoryconsumption',['mcuxClAead_MemoryConsumption',['../a00667.html',1,'']]], + ['mcuxclaead_5fmode_5faes_5fccm_5fdec',['mcuxClAead_Mode_AES_CCM_DEC',['../a00221.html#a2200749ce58283a93c563c8ca588b266',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fccm_5fenc',['mcuxClAead_Mode_AES_CCM_ENC',['../a00221.html#a2bcc801c8d408f932f10ef5834bd4dca',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fgcm_5fdec',['mcuxClAead_Mode_AES_GCM_DEC',['../a00221.html#afec8f3f6510075056a56f46fcec29f0d',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fgcm_5fenc',['mcuxClAead_Mode_AES_GCM_ENC',['../a00221.html#ac6b194ee963fcd02a46c187436486f3a',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5ft',['mcuxClAead_Mode_t',['../a00666.html#ga8084949e97b9ab9cd35ac041b8bbea0a',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fccm_5fdec',['mcuxClAead_ModeDescriptor_AES_CCM_DEC',['../a00221.html#a6a1aa3e495a39a8c6d8e399e2195daf2',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fccm_5fenc',['mcuxClAead_ModeDescriptor_AES_CCM_ENC',['../a00221.html#ac05fdd0d08e4c25390079671875363f3',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fgcm_5fdec',['mcuxClAead_ModeDescriptor_AES_GCM_DEC',['../a00221.html#ac167912520d7408603f0b4115ea59150',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fgcm_5fenc',['mcuxClAead_ModeDescriptor_AES_GCM_ENC',['../a00221.html#a8874663e21c7e81e855ebcceacdd300a',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5ft',['mcuxClAead_ModeDescriptor_t',['../a00666.html#ga8378bbf26468fde8248b08efca599481',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fprocess',['mcuxClAead_process',['../a00665.html#gaa4af5201aaf549186bf80cbf4284f3d1',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fprocess_5fadata',['mcuxClAead_process_adata',['../a00665.html#ga40cbd731ba8874d971213fa03605736d',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fstatus_5f',['MCUXCLAEAD_STATUS_',['../a00663.html',1,'']]], + ['mcuxclaead_5fstatus_5ft',['mcuxClAead_Status_t',['../a00666.html#ga1497c344a218545c5980a407e7c9194d',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5ftest_5ft',['mcuxClAead_Test_t',['../a00666.html#gab0222b5a8fcc204e08515b0b558fb5fe',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5ftestdescriptor_5ft',['mcuxClAead_TestDescriptor_t',['../a00666.html#gae182daa83ee8ec992f261f2b52b20adb',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5ftypes_2eh',['mcuxClAead_Types.h',['../a00212.html',1,'']]], + ['mcuxclaead_5fverify',['mcuxClAead_verify',['../a00665.html#gafb82bc41120d69281d0fbb719fb35d9d',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fwa_5fsize_5fmax',['MCUXCLAEAD_WA_SIZE_MAX',['../a00667.html#gab4cc3939b235a6d122ce012c23d3e61a',1,'mcuxClAeadModes_MemoryConsumption.h']]], + ['mcuxclaeadmodes_5fmemoryconsumption_2eh',['mcuxClAeadModes_MemoryConsumption.h',['../a00218.html',1,'']]], + ['mcuxclaeadmodes_5fmodes_2eh',['mcuxClAeadModes_Modes.h',['../a00221.html',1,'']]], + ['mcuxclaeadmodes_5fmultipart_5fels_5fccm_5fexample_2ec',['mcuxClAeadModes_Multipart_Els_Ccm_Example.c',['../a00035.html',1,'']]], + ['mcuxclaeadmodes_5foneshot_5fels_5fccm_5fexample_2ec',['mcuxClAeadModes_Oneshot_Els_Ccm_Example.c',['../a00038.html',1,'']]], + ['mcuxclaeadmodes_5foneshot_5fels_5fgcm_5fexample_2ec',['mcuxClAeadModes_Oneshot_Els_Gcm_Example.c',['../a00041.html',1,'']]], + ['multi_2dpart_20aead_20interfaces',['Multi-part AEAD interfaces',['../a00665.html',1,'']]], + ['mcuxclaes_2eh',['mcuxClAes.h',['../a00224.html',1,'']]], + ['mcuxclaes_5faes128_5fkey_5fsize',['MCUXCLAES_AES128_KEY_SIZE',['../a00669.html#gaf7377746dc3a4ea714c79c17f9ddbdde',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5faes128_5fkey_5fsize_5fin_5fwords',['MCUXCLAES_AES128_KEY_SIZE_IN_WORDS',['../a00669.html#ga82f8be599a040e7a44d1c4a78513b643',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5faes192_5fkey_5fsize',['MCUXCLAES_AES192_KEY_SIZE',['../a00669.html#ga10c60a14d43acdf3a32074b6104c00b4',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5faes192_5fkey_5fsize_5fin_5fwords',['MCUXCLAES_AES192_KEY_SIZE_IN_WORDS',['../a00669.html#ga68bc6c94d74d3ddde085798e06c5968a',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5faes256_5fkey_5fsize',['MCUXCLAES_AES256_KEY_SIZE',['../a00669.html#gaf85d02f88b56069ada0d2e6eaf184af8',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5faes256_5fkey_5fsize_5fin_5fwords',['MCUXCLAES_AES256_KEY_SIZE_IN_WORDS',['../a00669.html#ga59948f7fc4145e5dc383387f01dc439b',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5fblock_5fsize',['MCUXCLAES_BLOCK_SIZE',['../a00669.html#gaa988298f03dda2718fd7d6a893d84b6a',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5fblock_5fsize_5fin_5fwords',['MCUXCLAES_BLOCK_SIZE_IN_WORDS',['../a00669.html#ga70310305440fe83e2f18e79341de4830',1,'mcuxClAes_Constants.h']]], + ['mcuxclaes_5fconstants',['mcuxClAes_Constants',['../a00669.html',1,'']]], + ['mcuxclaes_5fkeytypes',['mcuxClAes_KeyTypes',['../a00670.html',1,'']]], + ['mcuxclaes_5fkeytypes_2eh',['mcuxClAes_KeyTypes.h',['../a00230.html',1,'']]], + ['mcux_20cl_20_26ndash_3b_20api',['MCUX CL &ndash; API',['../a00673.html',1,'']]], + ['mcuxclcipher',['mcuxClCipher',['../a00671.html',1,'']]], + ['mcuxclcipher_2eh',['mcuxClCipher.h',['../a00233.html',1,'']]], + ['mcuxclcipher_5fconstants',['mcuxClCipher_Constants',['../a00672.html',1,'']]], + ['mcuxclcipher_5fconstants_2eh',['mcuxClCipher_Constants.h',['../a00236.html',1,'']]], + ['mcuxclcipher_5fcontext_5ft',['mcuxClCipher_Context_t',['../a00676.html#ga9faa78dbb34107f8f28344b36b91c93d',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fcrypt',['mcuxClCipher_crypt',['../a00239.html#a3bc78aed20c4d8fcf8606d46dd27bf12',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5ffinish',['mcuxClCipher_finish',['../a00239.html#a90ac41c7d96f333de0708126b0bce4be',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5ffunctions_2eh',['mcuxClCipher_Functions.h',['../a00239.html',1,'']]], + ['mcuxclcipher_5finit',['mcuxClCipher_init',['../a00239.html#a3d0ee9a87aa371edeac7f361344aeb27',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fdec_5fnopadding',['mcuxClCipher_Mode_AES_CBC_Dec_NoPadding',['../a00677.html#gafcea66751b4008e0b5c9f3d3b982a3a4',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fnopadding',['mcuxClCipher_Mode_AES_CBC_Enc_NoPadding',['../a00677.html#ga807a672d6329f9c7d3beaabca651d517',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga20b89472f917ef5dcd1493e349a2851c',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga3656eebb0f185f9bec04f0cb293c42db',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpkcs7',['mcuxClCipher_Mode_AES_CBC_Enc_PKCS7',['../a00677.html#gad8399b835f6d454f0fa15b2b0ca41ee4',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fctr',['mcuxClCipher_Mode_AES_CTR',['../a00677.html#ga6f1b191b97196025c65851958eb2a700',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fdec_5fnopadding',['mcuxClCipher_Mode_AES_ECB_Dec_NoPadding',['../a00677.html#gade75d09ba133c93d3e46eb1c795bb451',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fnopadding',['mcuxClCipher_Mode_AES_ECB_Enc_NoPadding',['../a00677.html#gac5863201c397e8418c5284523119ea41',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga5c3dcb833ab559f75065e0e340b02886',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2',['../a00677.html#gae741b5b27af200b377425049545f6779',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingpkcs7',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7',['../a00677.html#ga76508d5bd12946fbb9b52749dac9f528',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5ft',['mcuxClCipher_Mode_t',['../a00676.html#gacd434e81399ac5f9752f61d55ecfb305',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fdec',['mcuxClCipher_ModeDescriptor_AES_CBC_Dec',['../a00677.html#ga4c8f02ead08c8c20259cf0c0120c8420',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fnopadding',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding',['../a00677.html#ga2cf616ea2d030fbe13a8b1ce8a3a6fa8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga22e8dfabe8c99f091cd41beeade83b2c',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga270643be668dfd110388711cae932bd6',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingpkcs7',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7',['../a00677.html#gab68a0cefd449150330bc4882ca957396',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fctr',['mcuxClCipher_ModeDescriptor_AES_CTR',['../a00677.html#ga93287cc9cd970f5c9103f1cc597027e0',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fdec',['mcuxClCipher_ModeDescriptor_AES_ECB_Dec',['../a00677.html#ga4a86accbf3ed6f707bca9208464b0fe8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fnopadding',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding',['../a00677.html#ga6d4a742e7880955c34b446d8d7ac4b18',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1',['../a00677.html#gae27dec2288073dac847fa49e1f3e9dd8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga887163d5d571468467116cf2017f00a9',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingpkcs7',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7',['../a00677.html#gad0e87e50be9066b625215cda60152589',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5ft',['mcuxClCipher_ModeDescriptor_t',['../a00676.html#gaa9586d961025bb80660a563be606451e',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fprocess',['mcuxClCipher_process',['../a00239.html#a1a5072096f7f82fbce313d414dbb438d',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5fstatus_5ft',['mcuxClCipher_Status_t',['../a00676.html#gadcf65a3850bca1bd4059213edf23df4f',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5ftest_5ft',['mcuxClCipher_Test_t',['../a00676.html#ga2d2ad865d5d552ea37a471acb2c48a74',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5ftestdescriptor_5ft',['mcuxClCipher_TestDescriptor_t',['../a00676.html#gae10b2dde7d4883d6992adb3e23d57714',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5ftypes_2eh',['mcuxClCipher_Types.h',['../a00242.html',1,'']]], + ['mcuxclciphermodes_5fmodes_2eh',['mcuxClCipherModes_Modes.h',['../a00251.html',1,'']]], + ['mcuxclcore_5ffunctionidentifiers_2eh',['mcuxClCore_FunctionIdentifiers.h',['../a00260.html',1,'']]], + ['mcuxclcss_5faead_5ffinalize_5fasync',['mcuxClCss_Aead_Finalize_Async',['../a00326.html#acd4f33dfe8b92796f5d88070e2cb45ec',1,'mcuxClEls_mapping.h']]], + ['mcuxclcss_5faeadoption_5ft',['mcuxClCss_AeadOption_t',['../a00326.html#adbc7825ddeb3a5325134b21ba92d895c',1,'mcuxClEls_mapping.h']]], + ['mcuxclcss_5fapi',['MCUXCLCSS_API',['../a00326.html#a943265c1ad7bb3d4163f108994aa7958',1,'mcuxClEls_mapping.h']]], + ['mcuxclecc',['mcuxClEcc',['../a00679.html',1,'']]], + ['mcuxclecc_2eh',['mcuxClEcc.h',['../a00269.html',1,'']]], + ['mcuxclecc_5falign_5fsize_5fpkc',['MCUXCLECC_ALIGN_SIZE_PKC',['../a00921.html#gac836b17e161566b045beb35f53828d1b',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fconstants',['mcuxClEcc_Constants',['../a00680.html',1,'']]], + ['mcuxclecc_5fconstants_2eh',['mcuxClEcc_Constants.h',['../a00272.html',1,'']]], + ['mcuxclecc_5fcustomweiereccdomainparams_5fsize',['MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE',['../a00683.html#gac8895d8165cf3c84b10ac986a30c37e4',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fdescriptors',['mcuxClEcc_Descriptors',['../a00687.html',1,'']]], + ['mcuxclecc_5fdomainparam_5fmisc_5fbytelenn_5fmask',['mcuxClEcc_DomainParam_misc_byteLenN_mask',['../a00686.html#ga26e4695e9a47f6a7c7d36af8e8432fa0',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fdomainparam_5fmisc_5fbytelenn_5foffset',['mcuxClEcc_DomainParam_misc_byteLenN_offset',['../a00686.html#ga2470875307a9264ff6e12046fd4a57eb',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fdomainparam_5fmisc_5fbytelenp_5fmask',['mcuxClEcc_DomainParam_misc_byteLenP_mask',['../a00686.html#ga6b450065c08ab2e1adf93c1015c2fe87',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fdomainparam_5fmisc_5fbytelenp_5foffset',['mcuxClEcc_DomainParam_misc_byteLenP_offset',['../a00686.html#ga62009de56f8d1fbbd2024072229a75fa',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fdomainparam_5fmisc_5fpack',['mcuxClEcc_DomainParam_misc_Pack',['../a00686.html#ga811c5fef9abbdfc1548b007e0d31c69f',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fdomainparam_5ft',['mcuxClEcc_DomainParam_t',['../a00973.html',1,'']]], + ['mcuxclecc_5feddsa_5fdomainparams_5ft',['mcuxClEcc_EdDSA_DomainParams_t',['../a00686.html#ga365359e63f156889e46845381455b321',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519_example.c',['../a00089.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5f',['MCUXCLECC_EDDSA_ED25519_SIZE_',['../a00957.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fbasepointorder',['MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER',['../a00957.html#gab9dd06ce9086a33b19e20eba3aed8a7c',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fhash_5fprefix',['MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX',['../a00957.html#gae7f1a0f58d5d7690b379a651edda99ef',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fprimep',['MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP',['../a00957.html#gac14b636a63b6ad2a4ba8edb45d213aea',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fprivatekey',['MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY',['../a00957.html#gab2c2539baf2994a0baae71d5d5c8f9fe',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fprivatekeydata',['MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA',['../a00957.html#ga550f1830c8403002664123225e0f594f',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fpublickey',['MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY',['../a00957.html#gaf6cce889f1dc2b213479126d850af09c',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fsignature',['MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE',['../a00957.html#gafd15d3ce72046f505d9763687d1614df',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5fsignature_5fprotocol_5fdescriptor',['MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR',['../a00957.html#ga506d1f24af8a6f12335d65ddb6be97fb',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed25519ctx_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519ctx_example.c',['../a00083.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519ph_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519ph_example.c',['../a00086.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519protocoldescriptor',['mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor',['../a00687.html#ga41770640b3d964f8add4ad005c6d81e6',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5f',['MCUXCLECC_EDDSA_ED448_SIZE_',['../a00958.html',1,'']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fbasepointorder',['MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER',['../a00958.html#ga2fff3270c5870bb95a69c8f283d91ee4',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fprimep',['MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP',['../a00958.html#ga574cb628611266d5182378f52676024b',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fprivatekey',['MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY',['../a00958.html#ga37d97fd46dcc20e7f93a5e06017ff967',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fprivatekeydata',['MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA',['../a00958.html#gae310bda6e4756493489df624280503ef',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fpublickey',['MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY',['../a00958.html#ga51affb40be89a5c0b1eb0d17a135786c',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5fsignature',['MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE',['../a00958.html#gae3ae89f1d488c9444e0f8c3813b9753a',1,'mcuxClEcc_ParameterSizes.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair',['mcuxClEcc_EdDSA_GenerateKeyPair',['../a00681.html#ga0ac2814cb9c8f4b8718a95d8c2ae2b85',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair_5fdescriptor_5fsize',['MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE',['../a00924.html#ga435b584a2a74e53c5987727a938aa65d',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair_5fed25519_5fwacpu_5fsize',['MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE',['../a00920.html#ga647bd322f94b65acba45b872cacf5ba8',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair_5fed25519_5fwapkc_5fsize',['MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE',['../a00923.html#ga6584fe2b7bc2e31a739cfb453fd2a9e6',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair_5fed448_5fwacpu_5fsize',['MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE',['../a00920.html#gad7ee128279d1230a6f0dee32093e4dc0',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair_5fed448_5fwapkc_5fsize',['MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE',['../a00923.html#ga4dd4582e5d6cdec3e4537a3447281348',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypairdescriptor_5ft',['mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t',['../a00686.html#gadee46209e43c63814a86e882b3927b27',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fgenerateprotocoldescriptor',['mcuxClEcc_EdDSA_GenerateProtocolDescriptor',['../a00681.html#ga54e3517cb9729321cdb4017b0fdc4485',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature',['mcuxClEcc_EdDSA_GenerateSignature',['../a00681.html#ga0b9ad0b0aa3afccae32a14aeddf9d8fe',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c',['../a00095.html',1,'']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed25519_5fwacpu_5fsize',['MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE',['../a00920.html#ga9ec654b676b4d3e3ccdda604ba55e5ed',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed25519_5fwapkc_5fsize',['MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE',['../a00923.html#ga0e082808f23a46021d65be49224fef54',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed448_5fwacpu_5fsize',['MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE',['../a00920.html#ga86d2a91a15fd9c10989b363bcd9ab6af',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed448_5fwapkc_5fsize',['MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE',['../a00923.html#gaca347a8466c7addee0aa63eb112fcb72',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fgenkeypair_5fdesc_5fsize_5f',['MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_',['../a00924.html',1,'']]], + ['mcuxclecc_5feddsa_5finitprivkeyinputmode',['mcuxClEcc_EdDSA_InitPrivKeyInputMode',['../a00681.html#ga78eaff72d9c8202b51c61c6668b9c3aa',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fsignature_5fprotocol_5fdesc_5fsize_5f',['MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_',['../a00925.html',1,'']]], + ['mcuxclecc_5feddsa_5fsignature_5fprotocol_5fdescriptor_5fsize',['MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE',['../a00925.html#ga045352e805adba9dfc25b087371872a6',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fsignatureprotocoldescriptor_5ft',['mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t',['../a00686.html#gaec003d78ecf36673f595fcc87f11b82c',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fverifysignature',['mcuxClEcc_EdDSA_VerifySignature',['../a00681.html#ga514b29374472b14ad00e0e5ef3469c7f',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c',['../a00092.html',1,'']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed25519_5fwacpu_5fsize',['MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE',['../a00920.html#gaf1baa23b5fa695897dade1e24bd60881',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed25519_5fwapkc_5fsize',['MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE',['../a00923.html#ga1a0b00eab2150578dc7afc98f8e82f2a',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed448_5fwacpu_5fsize',['MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE',['../a00920.html#gaeb4fa934c84d576b93c321b436af5ccd',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed448_5fwapkc_5fsize',['MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE',['../a00923.html#gad04926b8f100205fb4726200c825e1f6',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5feddsa_5fwacpu_5f',['MCUXCLECC_EDDSA_WACPU_',['../a00920.html',1,'']]], + ['mcuxclecc_5feddsa_5fwapkc_5f',['MCUXCLECC_EDDSA_WAPKC_',['../a00923.html',1,'']]], + ['mcuxclecc_5ffunctions',['mcuxClEcc_Functions',['../a00681.html',1,'']]], + ['mcuxclecc_5ffunctions_2eh',['mcuxClEcc_Functions.h',['../a00275.html',1,'']]], + ['mcuxclecc_5fkeygen',['mcuxClEcc_KeyGen',['../a00681.html#gabc728b0278908265f9923535391005dc',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fkeygen_5fparam_5ft',['mcuxClEcc_KeyGen_Param_t',['../a00977.html',1,'']]], + ['mcuxclecc_5fkeygen_5fwacpu_5fsize',['MCUXCLECC_KEYGEN_WACPU_SIZE',['../a00918.html#ga0fdfb866390f13e869a59e859da3866e',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fkeygen_5fwapkc_5fsize',['MCUXCLECC_KEYGEN_WAPKC_SIZE',['../a00921.html#ga7e26bba72c6eefd7f91907d0df33f17b',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fkeymechanisms_2eh',['mcuxClEcc_KeyMechanisms.h',['../a00278.html',1,'']]], + ['mcuxclecc_5fkeytypedescriptors',['mcuxClEcc_KeyTypeDescriptors',['../a00682.html',1,'']]], + ['mcuxclecc_5fmacros',['mcuxClEcc_Macros',['../a00685.html',1,'']]], + ['mcuxclecc_5fmax',['MCUXCLECC_MAX',['../a00921.html#gaf74ecb9246e198a6078c55c48ddf479e',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmemoryconsumption',['mcuxClEcc_MemoryConsumption',['../a00683.html',1,'']]], + ['mcuxclecc_5fmemoryconsumption_2eh',['mcuxClEcc_MemoryConsumption.h',['../a00281.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve25519_5fexample_2ec',['mcuxClEcc_Mont_Curve25519_example.c',['../a00074.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve25519_5fsize_5f',['MCUXCLECC_MONT_CURVE25519_SIZE_',['../a00926.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve448_5fexample_2ec',['mcuxClEcc_Mont_Curve448_example.c',['../a00077.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve448_5fsize_5f',['MCUXCLECC_MONT_CURVE448_SIZE_',['../a00927.html',1,'']]], + ['mcuxclecc_5fmont_5fdhkeyagreement',['mcuxClEcc_Mont_DhKeyAgreement',['../a00681.html#gaef77a1a80276b44da54c66a8d606f20d',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fmont_5fdhkeyagreement_5fcurve25519_5fwacpu_5fsize',['MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE',['../a00919.html#gaaf4bad03752e8903fc972548c27b40a3',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeyagreement_5fcurve25519_5fwapkc_5fsize',['MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE',['../a00922.html#gab8a50884589fb6a8e9c3a27176a98f17',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeyagreement_5fcurve448_5fwacpu_5fsize',['MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE',['../a00919.html#ga8051604c81692c541171eb8693eb0ebe',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeyagreement_5fcurve448_5fwapkc_5fsize',['MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE',['../a00922.html#ga42aed746692f49fa0a4e27f5b3f5d743',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration',['mcuxClEcc_Mont_DhKeyGeneration',['../a00681.html#ga71406ab7d35c51f12c01efcb73305196',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration_5fcurve25519_5fwacpu_5fsize',['MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE',['../a00919.html#ga89090994d784943f6c0ff6858600a5c8',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration_5fcurve25519_5fwapkc_5fsize',['MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE',['../a00922.html#gae36dff0de90c37f30b946bf2788b8c50',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration_5fcurve448_5fwacpu_5fsize',['MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE',['../a00919.html#gaf968453d3c749fe1e2a79b10877e8c9b',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration_5fcurve448_5fwapkc_5fsize',['MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE',['../a00922.html#ga10eb15479cf16f2bbe6834d0dce7480b',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fmontdh_5fdomainparams_5ft',['mcuxClEcc_MontDH_DomainParams_t',['../a00686.html#ga52205a42d2027ba1c3ec49589f9f0b8c',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fmontdh_5fstatus_5f',['MCUXCLECC_MONTDH_STATUS_',['../a00960.html',1,'']]], + ['mcuxclecc_5fmontdh_5fwacpu_5f',['MCUXCLECC_MONTDH_WACPU_',['../a00919.html',1,'']]], + ['mcuxclecc_5fmontdh_5fwapkc_5f',['MCUXCLECC_MONTDH_WAPKC_',['../a00922.html',1,'']]], + ['mcuxclecc_5fparametersizes',['mcuxClEcc_ParameterSizes',['../a00684.html',1,'']]], + ['mcuxclecc_5fparametersizes_2eh',['mcuxClEcc_ParameterSizes.h',['../a00284.html',1,'']]], + ['mcuxclecc_5fpkc_5fwordsize',['MCUXCLECC_PKC_WORDSIZE',['../a00921.html#ga636a89c09b2210ea78da464825e4bf99',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fpointmult',['mcuxClEcc_PointMult',['../a00681.html#gab199a221c61f252a0c755ab8d8a6a77c',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fpointmult_5fparam_5ft',['mcuxClEcc_PointMult_Param_t',['../a00989.html',1,'']]], + ['mcuxclecc_5fpointmult_5fwacpu_5fsize',['MCUXCLECC_POINTMULT_WACPU_SIZE',['../a00918.html#ga46349810877e3b79a8d899648e1b2e06',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fpointmult_5fwapkc_5fsize',['MCUXCLECC_POINTMULT_WAPKC_SIZE',['../a00921.html#ga36cab670f924640163fc1b02bb753792',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fsign',['mcuxClEcc_Sign',['../a00681.html#ga105ec4e9dc29573334f52979381686de',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fsign_5fparam_5foptlen_5fbytelenhash_5fmask',['mcuxClEcc_Sign_Param_optLen_byteLenHash_mask',['../a00686.html#ga4a74c55c76d977b39d1b387b75bbeebb',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fsign_5fparam_5foptlen_5fbytelenhash_5foffset',['mcuxClEcc_Sign_Param_optLen_byteLenHash_offset',['../a00686.html#ga25bfc46880eb604440c1facc7e55fc3d',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fsign_5fparam_5foptlen_5fpack',['mcuxClEcc_Sign_Param_optLen_Pack',['../a00686.html#ga05dbf2e2404af42bb6aaca0d0eaada8f',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fsign_5fparam_5ft',['mcuxClEcc_Sign_Param_t',['../a00981.html',1,'']]], + ['mcuxclecc_5fsign_5fwacpu_5fsize',['MCUXCLECC_SIGN_WACPU_SIZE',['../a00918.html#gabe6907845de629a54b0eae63da78d099',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fsign_5fwapkc_5fsize',['MCUXCLECC_SIGN_WAPKC_SIZE',['../a00921.html#ga3574ac0f7b7b9b6d17003263fc47c6c0',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fstatus_5f',['MCUXCLECC_STATUS_',['../a00959.html',1,'']]], + ['mcuxclecc_5fstatus_5ferror_5fsmall_5fsubgroup',['MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP',['../a00960.html#gaf70d3732e96746a174562deb076669f6',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5ffault_5fattack',['MCUXCLECC_STATUS_FAULT_ATTACK',['../a00959.html#ga9d53aaec17a413449e5cb6b73702c2c3',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5finvalid_5fparams',['MCUXCLECC_STATUS_INVALID_PARAMS',['../a00959.html#ga7eec856d4a1438ff6e603ee42aaa9aae',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5finvalid_5fsignature',['MCUXCLECC_STATUS_INVALID_SIGNATURE',['../a00959.html#gae739e1f3f62d1a66e2a862e40d5a0f37',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5fneutral_5fpoint',['MCUXCLECC_STATUS_NEUTRAL_POINT',['../a00959.html#gaad0d3ea3572cc175fe1608bca3ddac35',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5fnot_5fsupported',['MCUXCLECC_STATUS_NOT_SUPPORTED',['../a00959.html#ga7f2a86f80fcda4760372af6cdbc11c1b',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5fok',['MCUXCLECC_STATUS_OK',['../a00959.html#gafed6866e44c300e1946713be81aefb9c',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5fprotected_5ft',['mcuxClEcc_Status_Protected_t',['../a00685.html#ga3900d9bdb95a061d26b71f300318b6a1',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5frng_5ferror',['MCUXCLECC_STATUS_RNG_ERROR',['../a00959.html#ga80ff10536e9cd063f733449d74b1c878',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5ft',['mcuxClEcc_Status_t',['../a00685.html#gaf044f4a5eeeecc4ec5b01aed19f2fe41',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5ftypes',['mcuxClEcc_Types',['../a00686.html',1,'']]], + ['mcuxclecc_5ftypes_2eh',['mcuxClEcc_Types.h',['../a00287.html',1,'']]], + ['mcuxclecc_5fverify',['mcuxClEcc_Verify',['../a00681.html#ga80f15538ec3cb2d3bfa8dc2f2da86366',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fverify_5fparam_5foptlen_5fbytelenhash_5fmask',['mcuxClEcc_Verify_Param_optLen_byteLenHash_mask',['../a00686.html#gafeb4e3230717ac80d469d421918a8607',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fverify_5fparam_5foptlen_5fbytelenhash_5foffset',['mcuxClEcc_Verify_Param_optLen_byteLenHash_offset',['../a00686.html#ga9e4f2aa470eda485d1ca012222e37070',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fverify_5fparam_5foptlen_5fpack',['mcuxClEcc_Verify_Param_optLen_Pack',['../a00686.html#ga329b8cd689c64177a46e68b4f3a6a158',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fverify_5fparam_5ft',['mcuxClEcc_Verify_Param_t',['../a00985.html',1,'']]], + ['mcuxclecc_5fverify_5fwacpu_5fsize',['MCUXCLECC_VERIFY_WACPU_SIZE',['../a00918.html#ga77a772614cead92da188f20009bc24b5',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fverify_5fwapkc_5fsize',['MCUXCLECC_VERIFY_WAPKC_SIZE',['../a00921.html#gab4cdcbfb78c215dbee9ff06dc2955034',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fwacpu_5f',['MCUXCLECC_WACPU_',['../a00918.html',1,'']]], + ['mcuxclecc_5fwapkc_5f',['MCUXCLECC_WAPKC_',['../a00921.html',1,'']]], + ['mcuxclecc_5fweier_5fbasicdomainparams_5ft',['mcuxClEcc_Weier_BasicDomainParams_t',['../a00993.html',1,'']]], + ['mcuxclecc_5fweier_5fdomainparams_5ft',['mcuxClEcc_Weier_DomainParams_t',['../a00686.html#gafe84edad82c8934ef1634e9f29effa55',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fweierecc_2eh',['mcuxClEcc_WeierECC.h',['../a00290.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp160r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_',['../a00942.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp160t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_',['../a00949.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp192r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_',['../a00943.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp192t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_',['../a00950.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp224r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_',['../a00944.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp224t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_',['../a00951.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp256r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_',['../a00945.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp256t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_',['../a00952.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp320r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_',['../a00946.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp320t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_',['../a00953.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp384r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_',['../a00947.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp384t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_',['../a00954.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp512r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_',['../a00948.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp512t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_',['../a00955.html',1,'']]], + ['mcuxclecc_5fweierecc_5fcustomeccweiertype_5fbn256_5fexample_2ec',['mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c',['../a00080.html',1,'']]], + ['mcuxclecc_5fweierecc_5fgeneratecustomkeytype',['mcuxClEcc_WeierECC_GenerateCustomKeyType',['../a00290.html#abd1f9ebda4a913d82eefe752ca54923b',1,'mcuxClEcc_WeierECC.h']]], + ['mcuxclecc_5fweierecc_5fgeneratedomainparams',['mcuxClEcc_WeierECC_GenerateDomainParams',['../a00290.html#a1deb22c96b88674a4513e56cdd2dfe3a',1,'mcuxClEcc_WeierECC.h']]], + ['mcuxclecc_5fweierecc_5fgeneratedomainparams_5fwacpu_5fsize',['MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE',['../a00918.html#ga29e85a389cf38d61196691fc4f3a35f1',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fweierecc_5fgeneratedomainparams_5fwapkc_5fsize',['MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE',['../a00921.html#gad8881999c0f76cfb55a70d953fb979da',1,'mcuxClEcc_MemoryConsumption.h']]], + ['mcuxclecc_5fweierecc_5fmax_5fsize',['MCUXCLECC_WEIERECC_MAX_SIZE',['../a00956.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp192_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P192_SIZE_',['../a00937.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp224_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P224_SIZE_',['../a00938.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp256_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P256_SIZE_',['../a00939.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp384_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P384_SIZE_',['../a00940.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp521_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P521_SIZE_',['../a00941.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp160k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP160K1_SIZE_',['../a00928.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp192k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP192K1_SIZE_',['../a00929.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp192r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP192R1_SIZE_',['../a00932.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp224k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP224K1_SIZE_',['../a00930.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp224r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP224R1_SIZE_',['../a00933.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp256k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP256K1_SIZE_',['../a00931.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp256r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP256R1_SIZE_',['../a00934.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp384r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP384R1_SIZE_',['../a00935.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp521r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP521R1_SIZE_',['../a00936.html',1,'']]], + ['mcuxclels',['mcuxClEls',['../a00688.html',1,'']]], + ['mcuxclels_2eh',['mcuxClEls.h',['../a00293.html',1,'']]], + ['mcuxclels_5faead',['mcuxClEls_Aead',['../a00689.html',1,'']]], + ['mcuxclels_5faead_2eh',['mcuxClEls_Aead.h',['../a00296.html',1,'']]], + ['mcuxclels_5faead_5f',['MCUXCLELS_AEAD_',['../a00691.html',1,'']]], + ['mcuxclels_5faead_5faad_5fblock_5fsize',['MCUXCLELS_AEAD_AAD_BLOCK_SIZE',['../a00690.html#ga8a1dab00c208f1b7dc1cf8a2a30a3991',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5facpmod_5faadproc',['MCUXCLELS_AEAD_ACPMOD_AADPROC',['../a00691.html#ga536e8fa026cae719c095b47fbb0fd099',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5facpmod_5ffinal',['MCUXCLELS_AEAD_ACPMOD_FINAL',['../a00691.html#ga1d5a6d584b299721149ff9bdbeaee517',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5facpmod_5finit',['MCUXCLELS_AEAD_ACPMOD_INIT',['../a00691.html#ga6c775ee90e7ea1e3db4840a2037d303c',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5facpmod_5fmsgproc',['MCUXCLELS_AEAD_ACPMOD_MSGPROC',['../a00691.html#ga05e3ebc05c195d1f62ff6a40a98b8d3c',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fcontext_5fsize',['MCUXCLELS_AEAD_CONTEXT_SIZE',['../a00690.html#ga191963434b3271e31bdffc12943745e2',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fdecrypt',['MCUXCLELS_AEAD_DECRYPT',['../a00691.html#gaaf35b04563d926ceaa1782d82741d7b7',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fencrypt',['MCUXCLELS_AEAD_ENCRYPT',['../a00691.html#ga3bc61d00867e4344af9c7605a47028cf',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fextern_5fkey',['MCUXCLELS_AEAD_EXTERN_KEY',['../a00691.html#ga5b1a905706af4ecad1473f5e3ac8a710',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5ffinalize_5fasync',['mcuxClEls_Aead_Finalize_Async',['../a00693.html#gab2f0d1f82ce7537c78967ea2989a2054',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5ffunctions',['mcuxClEls_Aead_Functions',['../a00693.html',1,'']]], + ['mcuxclels_5faead_5finit_5fasync',['mcuxClEls_Aead_Init_Async',['../a00693.html#ga86bbde5d55c2e44102158ef7b802b819',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fintern_5fkey',['MCUXCLELS_AEAD_INTERN_KEY',['../a00691.html#gaa7d58cf548b411d9aaea17af1539203a',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fiv_5fblock_5fsize',['MCUXCLELS_AEAD_IV_BLOCK_SIZE',['../a00690.html#gacc54b347065e037fd7d5814334b82826',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5flastinit_5ffalse',['MCUXCLELS_AEAD_LASTINIT_FALSE',['../a00691.html#ga7f97e1488141405752147029eee6a818',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5flastinit_5ftrue',['MCUXCLELS_AEAD_LASTINIT_TRUE',['../a00691.html#ga7af98652f0dba78d1c665b2c9dfd0e29',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fmacros',['mcuxClEls_Aead_Macros',['../a00690.html',1,'']]], + ['mcuxclels_5faead_5fpartialinit_5fasync',['mcuxClEls_Aead_PartialInit_Async',['../a00693.html#ga817b12c984eb2afcaad9aa3c2b75040c',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fstate_5fin_5fdisable',['MCUXCLELS_AEAD_STATE_IN_DISABLE',['../a00691.html#ga445707b186d86232b626330863532c15',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fstate_5fin_5fenable',['MCUXCLELS_AEAD_STATE_IN_ENABLE',['../a00691.html#ga19f5684ee7ffea323b56bab96f7c059b',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fstate_5fout_5fenable',['MCUXCLELS_AEAD_STATE_OUT_ENABLE',['../a00691.html#ga944f3b21904cdbc22385fcfab1c1236b',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5ftag_5fsize',['MCUXCLELS_AEAD_TAG_SIZE',['../a00690.html#ga61d8f500ac3ed42fff023025b54692f2',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5ftypes',['mcuxClEls_Aead_Types',['../a00692.html',1,'']]], + ['mcuxclels_5faead_5fupdateaad_5fasync',['mcuxClEls_Aead_UpdateAad_Async',['../a00693.html#gaa34534b5e5196e07cbcef7c858cc0ea9',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fupdatedata_5fasync',['mcuxClEls_Aead_UpdateData_Async',['../a00693.html#ga7d5f1b08fbbcda07f881c274b0100c8b',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faeadoption_5ft',['mcuxClEls_AeadOption_t',['../a00997.html',1,'']]], + ['mcuxclels_5fapi',['MCUXCLELS_API',['../a00707.html#ga5f87370c0e52126f57afb5b13c283d73',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fcipher',['mcuxClEls_Cipher',['../a00694.html',1,'']]], + ['mcuxclels_5fcipher_2eh',['mcuxClEls_Cipher.h',['../a00299.html',1,'']]], + ['mcuxclels_5fcipher_5f',['MCUXCLELS_CIPHER_',['../a00696.html',1,'']]], + ['mcuxclels_5fcipher_5faes128_5fcbc_5fencrypt_5fexample_2ec',['mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c',['../a00005.html',1,'']]], + ['mcuxclels_5fcipher_5faes128_5fecb_5fencrypt_5fexample_2ec',['mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c',['../a00002.html',1,'']]], + ['mcuxclels_5fcipher_5fasync',['mcuxClEls_Cipher_Async',['../a00699.html#gad8b0506b0510f7dc6ef20fd488ee004b',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fblock_5fsize_5faes',['MCUXCLELS_CIPHER_BLOCK_SIZE_AES',['../a00695.html#ga36ebb8ab2b019997c6cf2c9d15b944b0',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fdecrypt',['MCUXCLELS_CIPHER_DECRYPT',['../a00696.html#ga15e29141f6a5eef67438d6db62cbaa72',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fencrypt',['MCUXCLELS_CIPHER_ENCRYPT',['../a00696.html#ga9840411e958cd2b7312c7e62e5dc06d0',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fexternal_5fkey',['MCUXCLELS_CIPHER_EXTERNAL_KEY',['../a00696.html#ga9feef12c93a57ed798263258e74cba73',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5ffunctions',['mcuxClEls_Cipher_Functions',['../a00699.html',1,'']]], + ['mcuxclels_5fcipher_5finternal_5fkey',['MCUXCLELS_CIPHER_INTERNAL_KEY',['../a00696.html#gad090b7cf60eb9468ae5fabf55672ab9d',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fkey_5fsize_5faes_5f',['MCUXCLELS_CIPHER_KEY_SIZE_AES_',['../a00697.html',1,'']]], + ['mcuxclels_5fcipher_5fkey_5fsize_5faes_5f128',['MCUXCLELS_CIPHER_KEY_SIZE_AES_128',['../a00697.html#ga68ee2f7110cd9f2dbce9af07b7c64f0f',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fkey_5fsize_5faes_5f192',['MCUXCLELS_CIPHER_KEY_SIZE_AES_192',['../a00697.html#ga40b6da61509c272916be81c25780eeff',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fkey_5fsize_5faes_5f256',['MCUXCLELS_CIPHER_KEY_SIZE_AES_256',['../a00697.html#ga474b8fd0f1e5832a4ba327ba7aee3520',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fmacros',['mcuxClEls_Cipher_Macros',['../a00695.html',1,'']]], + ['mcuxclels_5fcipher_5fstate_5fin_5fdisable',['MCUXCLELS_CIPHER_STATE_IN_DISABLE',['../a00696.html#gafc74b6823a43a2b50a27b4ec891ce9ef',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fstate_5fin_5fenable',['MCUXCLELS_CIPHER_STATE_IN_ENABLE',['../a00696.html#gab55a588688b790dd342dfc24f720a7aa',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fstate_5fout_5fdisable',['MCUXCLELS_CIPHER_STATE_OUT_DISABLE',['../a00696.html#ga3eb172e440a7290240fca36a6bf82fa0',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5fstate_5fout_5fenable',['MCUXCLELS_CIPHER_STATE_OUT_ENABLE',['../a00696.html#gabb9d9bd0dc215ef17a7ffbabd0f714c7',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipher_5ftypes',['mcuxClEls_Cipher_Types',['../a00698.html',1,'']]], + ['mcuxclels_5fcipheroption_5ft',['mcuxClEls_CipherOption_t',['../a01009.html',1,'']]], + ['mcuxclels_5fcipherparam_5falgorithm_5faes_5fcbc',['MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC',['../a00696.html#ga22151bc71de63404ddcb4dec66a3d99f',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipherparam_5falgorithm_5faes_5fctr',['MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR',['../a00696.html#ga4df5eca54609eed0ff0bf00152c87ccf',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fcipherparam_5falgorithm_5faes_5fecb',['MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB',['../a00696.html#ga6f585946c286cebc74b291c520eaaec9',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fckdf_5falgo_5fsp800108',['MCUXCLELS_CKDF_ALGO_SP800108',['../a00750.html#gacb24894c500384a885842b542053b60f',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fckdf_5fderivationdata_5fsize',['MCUXCLELS_CKDF_DERIVATIONDATA_SIZE',['../a00750.html#gae0e48994f0652e42fec3acca8c4469bb',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fckdf_5fsp800108_5fasync',['mcuxClEls_Ckdf_Sp800108_Async',['../a00752.html#ga4cf223def750c39f5c955fdfbe12bc8d',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fckdfoption_5ft',['mcuxClEls_CkdfOption_t',['../a01189.html',1,'']]], + ['mcuxclels_5fcmac',['mcuxClEls_Cmac',['../a00700.html',1,'']]], + ['mcuxclels_5fcmac_2eh',['mcuxClEls_Cmac.h',['../a00302.html',1,'']]], + ['mcuxclels_5fcmac_5f',['MCUXCLELS_CMAC_',['../a00703.html',1,'']]], + ['mcuxclels_5fcmac_5fasync',['mcuxClEls_Cmac_Async',['../a00705.html#ga0cc7e60d184ae44edd8ac6376ecf2387',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5fexternal_5fkey_5fdisable',['MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE',['../a00703.html#gaf8cc08552ae462283ee61cd55a1e6e6d',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5fexternal_5fkey_5fenable',['MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE',['../a00703.html#ga0b115dc62b80bece0cfbb37d8d6be71c',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5ffinalize_5fdisable',['MCUXCLELS_CMAC_FINALIZE_DISABLE',['../a00703.html#ga5a7186be485cefe12529107214dd872b',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5ffinalize_5fenable',['MCUXCLELS_CMAC_FINALIZE_ENABLE',['../a00703.html#ga923398d224ee92df39da7b5a27982850',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5ffunctions',['mcuxClEls_Cmac_Functions',['../a00705.html',1,'']]], + ['mcuxclels_5fcmac_5finitialize_5fdisable',['MCUXCLELS_CMAC_INITIALIZE_DISABLE',['../a00703.html#ga21b0dadab5a6ff16fa81b41a8bf8d190',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5finitialize_5fenable',['MCUXCLELS_CMAC_INITIALIZE_ENABLE',['../a00703.html#ga556198894993c42af47bb004ddde6f8e',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5fkey_5fsize_5f',['MCUXCLELS_CMAC_KEY_SIZE_',['../a00702.html',1,'']]], + ['mcuxclels_5fcmac_5fkey_5fsize_5f128',['MCUXCLELS_CMAC_KEY_SIZE_128',['../a00702.html#ga62fa42c9462e49ed1e357287492a64e8',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5fkey_5fsize_5f256',['MCUXCLELS_CMAC_KEY_SIZE_256',['../a00702.html#gab62855422ff04c5fb61bdcd555282931',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5fmacros',['mcuxClEls_Cmac_Macros',['../a00701.html',1,'']]], + ['mcuxclels_5fcmac_5fout_5fsize',['MCUXCLELS_CMAC_OUT_SIZE',['../a00701.html#ga5e153a25264389155e68014c29ddf815',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fcmac_5ftypes',['mcuxClEls_Cmac_Types',['../a00704.html',1,'']]], + ['mcuxclels_5fcmacoption_5ft',['mcuxClEls_CmacOption_t',['../a01021.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5f',['MCUXCLELS_CMD_CRC_',['../a00720.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5f',['MCUXCLELS_CMD_CRC_CMD_ID_',['../a00722.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fauth_5fcipher',['MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER',['../a00722.html#ga409e1dae95e89fd8ffb127c4f7ed88d2',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fchal_5fresp_5fgen',['MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN',['../a00722.html#ga2fdefdf18f7cb37b74ef2f49daeb7549',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fcipher',['MCUXCLELS_CMD_CRC_CMD_ID_CIPHER',['../a00722.html#ga2a3c7f74fe04bdbcce0856868ecf44ad',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fckdf',['MCUXCLELS_CMD_CRC_CMD_ID_CKDF',['../a00722.html#gacc64012f05a991897dc401f526fcc78b',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fcmac',['MCUXCLELS_CMD_CRC_CMD_ID_CMAC',['../a00722.html#ga9716ab821ee894a4cd64d0553311da2a',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fdrbg_5ftest',['MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST',['../a00722.html#ga4852767cbb713b107cf8e261fdbe5c17',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fdtrng_5fcfg_5fload',['MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD',['../a00722.html#ga33f246b5a6c663fd854726fbde6b260d',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fdtrng_5feval',['MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL',['../a00722.html#gaac8b6cfd8f9bf0bea117371edc80b974',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5feckxh',['MCUXCLELS_CMD_CRC_CMD_ID_ECKXH',['../a00722.html#ga04f3aa01819a18d5dbcedd795fddbc81',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fecsign',['MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN',['../a00722.html#gaeb55615316d2f67abc77976c752a4533',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fecvfy',['MCUXCLELS_CMD_CRC_CMD_ID_ECVFY',['../a00722.html#ga7cd6375c813a4de7d0ec9c9d4209c03a',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fgdet_5fcfg_5fload',['MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD',['../a00722.html#ga1dfda813fd0917ff50688736159435db',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fgdet_5ftrim',['MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM',['../a00722.html#gab752a820b7f5957518912f67576f3ea8',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fhash',['MCUXCLELS_CMD_CRC_CMD_ID_HASH',['../a00722.html#ga56f581e908a8889c11d0b916b6d69657',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fhkdf',['MCUXCLELS_CMD_CRC_CMD_ID_HKDF',['../a00722.html#ga3945648ed569844869fd7eb997e99df9',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fhmac',['MCUXCLELS_CMD_CRC_CMD_ID_HMAC',['../a00722.html#gab2cc703ff096c3b830019510855001a6',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fkdelete',['MCUXCLELS_CMD_CRC_CMD_ID_KDELETE',['../a00722.html#gaf9eadae3c47cdd4df67b150f91d6b30b',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fkeygen',['MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN',['../a00722.html#ga303a52799f5c842e761ae2c8527fb2f3',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fkeyin',['MCUXCLELS_CMD_CRC_CMD_ID_KEYIN',['../a00722.html#ga0d49dc33b50bd7db6ca58cb84db936e3',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fkeyout',['MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT',['../a00722.html#ga2fccccaeea8e4fb0e31bfa368caf39f7',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5fkeyprov',['MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV',['../a00722.html#gabaa8a08498f70bcccea59ee5472fe942',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5frnd_5freq',['MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ',['../a00722.html#ga72ff352c60a48b971c0ac0a772180fee',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5ftls',['MCUXCLELS_CMD_CRC_CMD_ID_TLS',['../a00722.html#gad86358f79337962338035ed5c49cb7ac',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fdisable',['MCUXCLELS_CMD_CRC_DISABLE',['../a00720.html#ga7dd3297a886e126c5c8c461e962b7c1e',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fenable',['MCUXCLELS_CMD_CRC_ENABLE',['../a00720.html#ga30485738143113e3a857d505076c0407',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5finitial_5fvalue',['MCUXCLELS_CMD_CRC_INITIAL_VALUE',['../a00720.html#ga2c5d32e550c9abea8ccc363d1fdb4a46',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fpolynomial',['MCUXCLELS_CMD_CRC_POLYNOMIAL',['../a00720.html#ga3ae77f6de5efb615e2f9bfe25d65eac5',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5f',['MCUXCLELS_CMD_CRC_REFERENCE_',['../a00721.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5finit',['MCUXCLELS_CMD_CRC_REFERENCE_INIT',['../a00721.html#ga2e1db01b3d5c51fd02a1e83060732e8c',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5freset',['MCUXCLELS_CMD_CRC_REFERENCE_RESET',['../a00721.html#ga9ce01bd5d4ea16985fa7b85cc15f2693',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5faead_5ffinalize',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE',['../a00721.html#gada728bb209a10e78365aaa4165fb1526',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5faead_5finit',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT',['../a00721.html#gae6ab0207e4403dcf5c2dcfde753cf655',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5faead_5fpartialinit',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT',['../a00721.html#gaefec8bc08ee26c21e77b5805ce9b7e60',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5faead_5fupdateaad',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD',['../a00721.html#ga245c09816fabe02aaaac29346c15be21',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5faead_5fupdatedata',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA',['../a00721.html#ga54d72bcb4788676fa1abfddfeb0b0500',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fcipher',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER',['../a00721.html#ga1bb77cbf1f29cfac9ca2db5f7b1a0450',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fckdf_5fsp800108',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108',['../a00721.html#ga47b490f3b6d5e627188d3130f475afbe',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fcmac',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC',['../a00721.html#ga064eac834320f9002cbfe9981b4e416f',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fecckeyexchange',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE',['../a00721.html#ga1e25c3e7350320526b8a46705d9eff7d',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fecckeygen',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN',['../a00721.html#gae92dbeb4c44c99edccfe08ebce63d7e7',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5feccsign',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN',['../a00721.html#ga625ee41cf33f31eafc17ccc527feeb08',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5feccverfify',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY',['../a00721.html#gab78f59c3466a002a40e3492054725c2c',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fglitchdetector_5floadconfig',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG',['../a00721.html#ga7ad4439beeb293ebc81605aff8080f06',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fglitchdetector_5ftrim',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM',['../a00721.html#ga93bffd65f1138c80e00562ce7c37456a',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fhash',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH',['../a00721.html#ga895449214513abfa3882c67be4cae8c1',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fhkdf_5frfc5869',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869',['../a00721.html#ga99f07b82231a11b71b66664e9a6cd632',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fhkdf_5fsp80056c',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C',['../a00721.html#gaf4580ba34e94564c4f608a55d120ea7b',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fhmac',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC',['../a00721.html#gae38cd842c0f20823078a071e4efe6b91',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fkeydelete',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE',['../a00721.html#ga78802e76c0a21709beb16b4764f395e4',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fkeyexport',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT',['../a00721.html#ga28cfed7894b7923478c183f52020ceec',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5fkeyimport',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT',['../a00721.html#gafda5328d88ce7cb623fbffe67f3f881a',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdrbgrequest',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST',['../a00721.html#gaa579d89877e771f69c92fbd0b3ed5752',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdrbgtestaesctr',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR',['../a00721.html#ga1aa20023a8871dcf226865cfdc4846b8',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdrbgtestaesecb',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB',['../a00721.html#ga931581b96f1c816a9b4f09ac6d219a68',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdrbgtestextract',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT',['../a00721.html#ga26fc4efbe3d744309300fdc73f6a507b',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdrbgtestinstantiate',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE',['../a00721.html#ga57115088afcd2e11f0742426df26c31a',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdtrng_5fconfigevaluate',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE',['../a00721.html#ga1fef6315409433815a4e64abfb23159f',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5frng_5fdtrng_5fconfigload',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD',['../a00721.html#gaabeccb19cfd99a1a83954d7676e792b4',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5ftlsgeneratemasterkeyfrompremasterkey',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY',['../a00721.html#gabf4ea11b932e2c372554a38d2b46af10',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5fupdate_5ftlsgeneratesessionkeysfrommasterkey',['MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY',['../a00721.html#ga4767023f07bf0519f9ced9c08931b2db',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5freset',['MCUXCLELS_CMD_CRC_RESET',['../a00720.html#ga223c08e1768387247f660f6ab9b2abd0',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fvalue_5fdisable',['MCUXCLELS_CMD_CRC_VALUE_DISABLE',['../a00720.html#ga989391a1c889ba01d0324f71e22d9cdb',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fvalue_5fenable',['MCUXCLELS_CMD_CRC_VALUE_ENABLE',['../a00720.html#ga72aafc14f6c0d2d5566095da8da12836',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcmd_5fcrc_5fvalue_5freset',['MCUXCLELS_CMD_CRC_VALUE_RESET',['../a00720.html#ga4ea6f474882d3641c24d667d3e27705e',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcommandcrcconfig_5ft',['mcuxClEls_CommandCrcConfig_t',['../a01105.html',1,'']]], + ['mcuxclels_5fcommon',['mcuxClEls_Common',['../a00706.html',1,'']]], + ['mcuxclels_5fcommon_2eh',['mcuxClEls_Common.h',['../a00305.html',1,'']]], + ['mcuxclels_5fcommon_5ffunctions',['mcuxClEls_Common_Functions',['../a00717.html',1,'']]], + ['mcuxclels_5fcommon_5fget_5finfo_5fexample_2ec',['mcuxClEls_Common_Get_Info_example.c',['../a00011.html',1,'']]], + ['mcuxclels_5fcommon_5fmacros',['mcuxClEls_Common_Macros',['../a00707.html',1,'']]], + ['mcuxclels_5fcommon_5ftypes',['mcuxClEls_Common_Types',['../a00716.html',1,'']]], + ['mcuxclels_5fconfigurecommandcrc',['mcuxClEls_ConfigureCommandCRC',['../a00724.html#ga4aaabd203c6c81a042bc4f3739ae8408',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fcrc',['mcuxClEls_Crc',['../a00718.html',1,'']]], + ['mcuxclels_5fcrc_2eh',['mcuxClEls_Crc.h',['../a00308.html',1,'']]], + ['mcuxclels_5fcrc_5ffunctions',['mcuxClEls_Crc_Functions',['../a00724.html',1,'']]], + ['mcuxclels_5fcrc_5fmacros',['mcuxClEls_Crc_Macros',['../a00719.html',1,'']]], + ['mcuxclels_5fcrc_5ftypes',['mcuxClEls_Crc_Types',['../a00723.html',1,'']]], + ['mcuxclels_5fdisable',['mcuxClEls_Disable',['../a00717.html#gacbf878536100314ce61081c54ea5ef9e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fecc',['mcuxClEls_Ecc',['../a00725.html',1,'']]], + ['mcuxclels_5fecc_2eh',['mcuxClEls_Ecc.h',['../a00311.html',1,'']]], + ['mcuxclels_5fecc_5ffunctions',['mcuxClEls_Ecc_Functions',['../a00734.html',1,'']]], + ['mcuxclels_5fecc_5fgen_5fpublic_5fkey',['MCUXCLELS_ECC_GEN_PUBLIC_KEY',['../a00730.html#gac67abe2d5052f753cc5f5aca24663066',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fhashed',['MCUXCLELS_ECC_HASHED',['../a00729.html#gafad38c505a64137b0283ad96c144c503',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5finclude_5frandom_5fdata',['MCUXCLELS_ECC_INCLUDE_RANDOM_DATA',['../a00730.html#gadcb581867b97e3c3988125eddc5f24e3',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fkeygen_5fsign_5fverify_5fexample_2ec',['mcuxClEls_Ecc_Keygen_Sign_Verify_example.c',['../a00008.html',1,'']]], + ['mcuxclels_5fecc_5fmacros',['mcuxClEls_Ecc_Macros',['../a00726.html',1,'']]], + ['mcuxclels_5fecc_5fno_5frandom_5fdata',['MCUXCLELS_ECC_NO_RANDOM_DATA',['../a00730.html#ga10f155f1020130f0b9c952f6df52c784',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fno_5frtf',['MCUXCLELS_ECC_NO_RTF',['../a00729.html#gae7ffc3999117e1796727bd7700d88745',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fnot_5fhashed',['MCUXCLELS_ECC_NOT_HASHED',['../a00729.html#ga871f176b3998d9b5dd709d5a6e2585bd',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5foutputkey_5fdeterministic',['MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC',['../a00730.html#ga8cdc8f5c722207aaef7fef9fd0cc3837',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5foutputkey_5fkeyexchange',['MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE',['../a00730.html#gabc39d5811bcaba4278e1f9c4874527ae',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5foutputkey_5frandom',['MCUXCLELS_ECC_OUTPUTKEY_RANDOM',['../a00730.html#ga67348b1833c0bfaccbe334c2cb68b448',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5foutputkey_5fsign',['MCUXCLELS_ECC_OUTPUTKEY_SIGN',['../a00730.html#gacff4169a4b48ee6c6e8ac13e2ea025ab',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fpublickey_5fsign_5fdisable',['MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE',['../a00730.html#gaf73a03883462465c3cabb2257981fc5f',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fpublickey_5fsign_5fenable',['MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE',['../a00730.html#ga9b6bd96ac94ff7bd763b9b9d057d139f',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fpublickey_5fsize',['MCUXCLELS_ECC_PUBLICKEY_SIZE',['../a00732.html#ga7298491d4e2d679496d0bacab6f351f8',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5freversefetch_5fdisable',['MCUXCLELS_ECC_REVERSEFETCH_DISABLE',['../a00731.html#ga92e6bbdd8cdd2d0ed90e6073e94924df',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5freversefetch_5fenable',['MCUXCLELS_ECC_REVERSEFETCH_ENABLE',['../a00731.html#ga0536723a417500b946e92b6432d0a4fd',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5frtf',['MCUXCLELS_ECC_RTF',['../a00729.html#ga04c77ad43887a66b1b8df87cb9258981',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fsignature_5fr_5fsize',['MCUXCLELS_ECC_SIGNATURE_R_SIZE',['../a00732.html#ga18a35b4e98dac7862895339b720d667a',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fsignature_5fsize',['MCUXCLELS_ECC_SIGNATURE_SIZE',['../a00732.html#ga922fa06cbacda443d50f2b3c29fdea8c',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fsize',['MCUXCLELS_ECC_SIZE',['../a00732.html',1,'']]], + ['mcuxclels_5fecc_5fskip_5fpublic_5fkey',['MCUXCLELS_ECC_SKIP_PUBLIC_KEY',['../a00730.html#gacbb5ce65a2ad59ec7a6709059f94426f',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5ftypes',['mcuxClEls_Ecc_Types',['../a00733.html',1,'']]], + ['mcuxclels_5fecc_20_28sign_20and_20verify_29_20option_20word_20values',['MCUXCLELS_ECC (Sign and Verify) option word values',['../a00727.html',1,'']]], + ['mcuxclels_5fecc_20_28sign_20and_20verify_29_20option_20bit_20field_20values',['MCUXCLELS_ECC (Sign and Verify) option bit field values',['../a00729.html',1,'']]], + ['mcuxclels_5fecc_5fvalue_5fhashed',['MCUXCLELS_ECC_VALUE_HASHED',['../a00727.html#gac3be2289b4247767251a8d85014652bb',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fvalue_5fno_5frtf',['MCUXCLELS_ECC_VALUE_NO_RTF',['../a00727.html#ga66a8fbee1f549d2ad1819c0e08780e13',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fvalue_5fnot_5fhashed',['MCUXCLELS_ECC_VALUE_NOT_HASHED',['../a00727.html#ga90e38c2c9caeb976594c32d92bbc5d05',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecc_5fvalue_5frtf',['MCUXCLELS_ECC_VALUE_RTF',['../a00727.html#ga48a69913a0b9d082ea72b81f56ac1fdc',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5feccbyte_5ft',['mcuxClEls_EccByte_t',['../a00733.html#gaaca57cf87336b1e866852443c47a019f',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecckeyexchange_5fasync',['mcuxClEls_EccKeyExchange_Async',['../a00734.html#ga39d6102bd9c792eb5a2e33af1f1830c3',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecckeyexchoption_5ft',['mcuxClEls_EccKeyExchOption_t',['../a01153.html',1,'']]], + ['mcuxclels_5fecckeygen_5fasync',['mcuxClEls_EccKeyGen_Async',['../a00734.html#ga060362493427031ef51110b7c381a986',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecckeygenoption_5ft',['mcuxClEls_EccKeyGenOption_t',['../a01141.html',1,'']]], + ['mcuxclels_5feccsign_5fasync',['mcuxClEls_EccSign_Async',['../a00734.html#ga96b17fadb9ee18906bb719e222908209',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5feccsignoption_5ft',['mcuxClEls_EccSignOption_t',['../a01117.html',1,'']]], + ['mcuxclels_5feccverify_5fasync',['mcuxClEls_EccVerify_Async',['../a00734.html#ga019a066eda05dab4955ed76e83d39b77',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5feccverifyoption_5ft',['mcuxClEls_EccVerifyOption_t',['../a01129.html',1,'']]], + ['mcuxclels_5fels_5finterrupt_5fdisable',['MCUXCLELS_ELS_INTERRUPT_DISABLE',['../a00708.html#ga2427d922e877e78bac483cf68f6c5892',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fels_5finterrupt_5fenable',['MCUXCLELS_ELS_INTERRUPT_ENABLE',['../a00708.html#ga845d16f6376f2c28864f1855ddbde61c',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fels_5finterrupt_5fkeep',['MCUXCLELS_ELS_INTERRUPT_KEEP',['../a00710.html#gab3911a79259043879d2446269741ac19',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fels_5finterrupt_5fset',['MCUXCLELS_ELS_INTERRUPT_SET',['../a00710.html#ga08923159f1ba8aff0b1b06a547db7ff6',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fels_5freset_5fclear',['MCUXCLELS_ELS_RESET_CLEAR',['../a00709.html#ga1a702565c0bfd8fa6b28db41f61ba3be',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fels_5freset_5fkeep',['MCUXCLELS_ELS_RESET_KEEP',['../a00709.html#gac963d24ca31b1b3e89d31efb7ccf6abf',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fenable_5fasync',['mcuxClEls_Enable_Async',['../a00717.html#ga6dbf394b38add1c6967dab368435b657',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5ferror_5fflags_5f',['MCUXCLELS_ERROR_FLAGS_',['../a00711.html',1,'']]], + ['mcuxclels_5ferror_5fflags_5fclear',['MCUXCLELS_ERROR_FLAGS_CLEAR',['../a00711.html#ga3528b1fa2b3c39524898299a3a90a753',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5ferror_5fflags_5fkeep',['MCUXCLELS_ERROR_FLAGS_KEEP',['../a00711.html#gab2b0ee14cae59a5f5f4f2563d7189854',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5ferrorhandling_5ft',['mcuxClEls_ErrorHandling_t',['../a00716.html#ga3411a9581b6770690eba6acc6b69c278',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetcommandcrc',['mcuxClEls_GetCommandCRC',['../a00724.html#gaf91caa2b1230676e9beedaa0eba442eb',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fgeterrorcode',['mcuxClEls_GetErrorCode',['../a00717.html#gaeb4fc2a3a1115489dcb9912f7160cb7f',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgeterrorlevel',['mcuxClEls_GetErrorLevel',['../a00717.html#ga896309eafc0aedbb5514ec4111b4d750',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgethwstate',['mcuxClEls_GetHwState',['../a00717.html#gadb25761b4c1a0de90f1420f459093bd5',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgethwversion',['mcuxClEls_GetHwVersion',['../a00717.html#gaade966640da314f17e6024ada7df6219',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetintenableflags',['mcuxClEls_GetIntEnableFlags',['../a00717.html#ga3de0def8758ec5320102a0beb521da37',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetkeyproperties',['mcuxClEls_GetKeyProperties',['../a00759.html#ga524d99bbf9aae0d299fbb52d2a121c4f',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fgetrandomstartdelay',['mcuxClEls_GetRandomStartDelay',['../a00717.html#ga1269f369af68e23e9ee8d282dc37c42b',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fhash',['mcuxClEls_Hash',['../a00735.html',1,'']]], + ['mcuxclels_5fhash_2eh',['mcuxClEls_Hash.h',['../a00314.html',1,'']]], + ['mcuxclels_5fhash_5f',['MCUXCLELS_HASH_',['../a00737.html',1,'']]], + ['mcuxclels_5fhash_5fasync',['mcuxClEls_Hash_Async',['../a00742.html#ga086eeafba9afb8ea16550414fd33a3b3',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fblock_5fsize_5f',['MCUXCLELS_HASH_BLOCK_SIZE_',['../a00738.html',1,'']]], + ['mcuxclels_5fhash_5fblock_5fsize_5fsha_5f224',['MCUXCLELS_HASH_BLOCK_SIZE_SHA_224',['../a00738.html#ga675b25b13fc541b6caf4ede098e62a3a',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fblock_5fsize_5fsha_5f256',['MCUXCLELS_HASH_BLOCK_SIZE_SHA_256',['../a00738.html#gaa8a671b476a7428d5a63addc98c196ce',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fblock_5fsize_5fsha_5f384',['MCUXCLELS_HASH_BLOCK_SIZE_SHA_384',['../a00738.html#ga3f675b49bbe27893e553c19279260be3',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fblock_5fsize_5fsha_5f512',['MCUXCLELS_HASH_BLOCK_SIZE_SHA_512',['../a00738.html#ga9488afdc7a3f5faf48e796ca3b2117dc',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5ffunctions',['mcuxClEls_Hash_Functions',['../a00742.html',1,'']]], + ['mcuxclels_5fhash_5finit_5fdisable',['MCUXCLELS_HASH_INIT_DISABLE',['../a00737.html#gae4ee87c1b75f1f1b0499c55e32362314',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5finit_5fenable',['MCUXCLELS_HASH_INIT_ENABLE',['../a00737.html#ga77bb4f8fa18f9e15f8a062c996aaa8b7',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fload_5fdisable',['MCUXCLELS_HASH_LOAD_DISABLE',['../a00737.html#ga149c6d67f2f81c94d931660a041ea02a',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fload_5fenable',['MCUXCLELS_HASH_LOAD_ENABLE',['../a00737.html#gae826483f63146be0fcf0c06c132096ec',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fmacros',['mcuxClEls_Hash_Macros',['../a00736.html',1,'']]], + ['mcuxclels_5fhash_5fmode_5fsha_5f224',['MCUXCLELS_HASH_MODE_SHA_224',['../a00737.html#gaf65949fa7e4326a043629a163a7b49d1',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fmode_5fsha_5f256',['MCUXCLELS_HASH_MODE_SHA_256',['../a00737.html#gadc8c733440eb2908d653e3647f650072',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fmode_5fsha_5f384',['MCUXCLELS_HASH_MODE_SHA_384',['../a00737.html#gaff4d85496f5f770b803a8b4643665d5e',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fmode_5fsha_5f512',['MCUXCLELS_HASH_MODE_SHA_512',['../a00737.html#gaff0fe735de78d7fb9bb090b82167e47e',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fdisable',['MCUXCLELS_HASH_OUTPUT_DISABLE',['../a00737.html#gaedcd4ce245169a7375f96e7fb68c6bb8',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fenable',['MCUXCLELS_HASH_OUTPUT_ENABLE',['../a00737.html#gaba86f7cd657db104d355d74840eb4d42',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fsize_5f',['MCUXCLELS_HASH_OUTPUT_SIZE_',['../a00740.html',1,'']]], + ['mcuxclels_5fhash_5foutput_5fsize_5fsha_5f224',['MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224',['../a00740.html#ga5cc6964abb7966c445feb2abf14f8067',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fsize_5fsha_5f256',['MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256',['../a00740.html#gaaa520442bedd60dec1b7e4b10ac57fe3',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fsize_5fsha_5f384',['MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384',['../a00740.html#gab961aed69bd7828bf783f318a9dde671',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5foutput_5fsize_5fsha_5f512',['MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512',['../a00740.html#gab75499823ecacb60bc8c9fdc8d541e95',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5frtf_5foutput_5fdisable',['MCUXCLELS_HASH_RTF_OUTPUT_DISABLE',['../a00737.html#gad1029c2f42df24f540d1d5ff7b3eaa2d',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5frtf_5foutput_5fenable',['MCUXCLELS_HASH_RTF_OUTPUT_ENABLE',['../a00737.html#ga5a22b37440c5513f49344f7fabb8537b',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5frtf_5foutput_5fsize',['MCUXCLELS_HASH_RTF_OUTPUT_SIZE',['../a00736.html#ga0441e5ea8ef5538062269e9da3be7b6f',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5frtf_5fupdate_5fdisable',['MCUXCLELS_HASH_RTF_UPDATE_DISABLE',['../a00737.html#ga403f2e98211fbc346b618654f9cbfaf2',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5frtf_5fupdate_5fenable',['MCUXCLELS_HASH_RTF_UPDATE_ENABLE',['../a00737.html#ga1aeb9d00c3be6bbbdb6421655f3b0c78',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fsha224_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha224_One_Block_example.c',['../a00014.html',1,'']]], + ['mcuxclels_5fhash_5fsha256_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha256_One_Block_example.c',['../a00017.html',1,'']]], + ['mcuxclels_5fhash_5fsha384_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha384_One_Block_example.c',['../a00020.html',1,'']]], + ['mcuxclels_5fhash_5fsha512_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha512_One_Block_example.c',['../a00023.html',1,'']]], + ['mcuxclels_5fhash_5fstate_5fsize_5f',['MCUXCLELS_HASH_STATE_SIZE_',['../a00739.html',1,'']]], + ['mcuxclels_5fhash_5fstate_5fsize_5fsha_5f224',['MCUXCLELS_HASH_STATE_SIZE_SHA_224',['../a00739.html#ga3fd16f21d04553be99f6c4bade526fcb',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fstate_5fsize_5fsha_5f256',['MCUXCLELS_HASH_STATE_SIZE_SHA_256',['../a00739.html#ga9a24ee94d01d6b1b8cb33c7af84f8d9e',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fstate_5fsize_5fsha_5f384',['MCUXCLELS_HASH_STATE_SIZE_SHA_384',['../a00739.html#ga2d78f8155107a52c3e618bab9bb52f85',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fstate_5fsize_5fsha_5f512',['MCUXCLELS_HASH_STATE_SIZE_SHA_512',['../a00739.html#gaf9f4da1c0d09797adb02f2af0bf4b429',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5ftypes',['mcuxClEls_Hash_Types',['../a00741.html',1,'']]], + ['mcuxclels_5fhash_5fvalue_5fmode_5fsha_5f224',['MCUXCLELS_HASH_VALUE_MODE_SHA_224',['../a00737.html#ga55483aa09654820ae31a84aae32e1b37',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fvalue_5fmode_5fsha_5f256',['MCUXCLELS_HASH_VALUE_MODE_SHA_256',['../a00737.html#ga3a02725bdd6679e1354b9dec7e12c22c',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fvalue_5fmode_5fsha_5f384',['MCUXCLELS_HASH_VALUE_MODE_SHA_384',['../a00737.html#gaa55acf6e0c6b46a2ae67c260819a3621',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhash_5fvalue_5fmode_5fsha_5f512',['MCUXCLELS_HASH_VALUE_MODE_SHA_512',['../a00737.html#ga9c10275675c3d6e4cccd6ebdfa229cc3',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhashoption_5ft',['mcuxClEls_HashOption_t',['../a01165.html',1,'']]], + ['mcuxclels_5fhkdf_5falgo_5frfc5869',['MCUXCLELS_HKDF_ALGO_RFC5869',['../a00750.html#ga3e905f07b3198e2853b8b099d68dc5d1',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5falgo_5fsp80056c',['MCUXCLELS_HKDF_ALGO_SP80056C',['../a00750.html#ga41a071a8d47d42ec8350dd2db4f37867',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5frfc5869_5fasync',['mcuxClEls_Hkdf_Rfc5869_Async',['../a00752.html#gaad9187ee88fcb4efae7fd9469b51dc81',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5frfc5869_5fderivationdata_5fsize',['MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE',['../a00750.html#ga7b1d08f458ed93ea2a17bdb8f8ecee40',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5frtf_5fderiv',['MCUXCLELS_HKDF_RTF_DERIV',['../a00750.html#ga9eb01402c540d2f07a66cb1a26a12b1d',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fsp80056c_5fasync',['mcuxClEls_Hkdf_Sp80056c_Async',['../a00752.html#ga8d44c8b880565afe51d941057570361b',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fsp80056c_5ftargetkey_5fsize',['MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE',['../a00750.html#gaf62127ae68ef3ec5815f3a7c3907d66f',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fsystem_5fmemory_5fderiv',['MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV',['../a00750.html#ga5b9747f125d34747a4707a5a08a572b2',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fvalue_5fmemory_5fderiv',['MCUXCLELS_HKDF_VALUE_MEMORY_DERIV',['../a00750.html#ga1af84f58a0ee007153d5e7dc65b43c2b',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fvalue_5frtf_5fderiv',['MCUXCLELS_HKDF_VALUE_RTF_DERIV',['../a00750.html#ga9590681d68b6ef92ba29e53ecd556213',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdfoption_5ft',['mcuxClEls_HkdfOption_t',['../a01201.html',1,'']]], + ['mcuxclels_5fhmac',['mcuxClEls_Hmac',['../a00743.html',1,'']]], + ['mcuxclels_5fhmac_2eh',['mcuxClEls_Hmac.h',['../a00317.html',1,'']]], + ['mcuxclels_5fhmac_5fasync',['mcuxClEls_Hmac_Async',['../a00747.html#gafc82ce850568a1e0c9f44f9e59d6fbbf',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fhmac_5fexternal_5fkey_5f',['MCUXCLELS_HMAC_EXTERNAL_KEY_',['../a00745.html',1,'']]], + ['mcuxclels_5fhmac_5fexternal_5fkey_5fdisable',['MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE',['../a00745.html#ga876370de65e0c65b54c39b34921a4444',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fhmac_5fexternal_5fkey_5fenable',['MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE',['../a00745.html#ga19feebc17331ebe966c67a9bfed79e33',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fhmac_5ffunctions',['mcuxClEls_Hmac_Functions',['../a00747.html',1,'']]], + ['mcuxclels_5fhmac_5fmacros',['mcuxClEls_Hmac_Macros',['../a00744.html',1,'']]], + ['mcuxclels_5fhmac_5foutput_5fsize',['MCUXCLELS_HMAC_OUTPUT_SIZE',['../a00744.html#ga80d89c1569e578566088cad0ea9127f4',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fhmac_5fpadded_5fkey_5fsize',['MCUXCLELS_HMAC_PADDED_KEY_SIZE',['../a00744.html#ga039409b9bba04a61be14b175117fb932',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fhmac_5ftypes',['mcuxClEls_Hmac_Types',['../a00746.html',1,'']]], + ['mcuxclels_5fhmacoption_5ft',['mcuxClEls_HmacOption_t',['../a01177.html',1,'']]], + ['mcuxclels_5fhw_5fversion',['MCUXCLELS_HW_VERSION',['../a00707.html#gac06d5de9fa68404bc11b426ed3cdd8f6',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fhwconfig_5ft',['mcuxClEls_HwConfig_t',['../a01093.html',1,'']]], + ['mcuxclels_5fhwstate_5ft',['mcuxClEls_HwState_t',['../a01045.html',1,'']]], + ['mcuxclels_5fhwversion_5ft',['mcuxClEls_HwVersion_t',['../a01033.html',1,'']]], + ['mcuxclels_5finterruptoptionen_5ft',['mcuxClEls_InterruptOptionEn_t',['../a01057.html',1,'']]], + ['mcuxclels_5finterruptoptionen_5ft',['mcuxClEls_InterruptOptionEn_t',['../a00708.html',1,'']]], + ['mcuxclels_5finterruptoptionrst_5ft',['mcuxClEls_InterruptOptionRst_t',['../a01069.html',1,'']]], + ['mcuxclels_5finterruptoptionrst_5ft',['mcuxClEls_InterruptOptionRst_t',['../a00709.html',1,'']]], + ['mcuxclels_5finterruptoptionset_5ft',['mcuxClEls_InterruptOptionSet_t',['../a01081.html',1,'']]], + ['mcuxclels_5finterruptoptionset_5ft',['mcuxClEls_InterruptOptionSet_t',['../a00710.html',1,'']]], + ['mcuxclels_5fkdf',['mcuxClEls_Kdf',['../a00748.html',1,'']]], + ['mcuxclels_5fkdf_2eh',['mcuxClEls_Kdf.h',['../a00320.html',1,'']]], + ['mcuxclels_5fkdf_5fdefine',['mcuxClEls_Kdf_Define',['../a00750.html',1,'']]], + ['mcuxclels_5fkdf_5ffunctions',['mcuxClEls_Kdf_Functions',['../a00752.html',1,'']]], + ['mcuxclels_5fkdf_5fmacros',['mcuxClEls_Kdf_Macros',['../a00749.html',1,'']]], + ['mcuxclels_5fkdf_5ftypes',['mcuxClEls_Kdf_Types',['../a00751.html',1,'']]], + ['mcuxclels_5fkey_5fimport_5fpuk_5fder_5fexample_2ec',['mcuxClEls_Key_Import_Puk_DER_example.c',['../a00032.html',1,'']]], + ['mcuxclels_5fkey_5fslots',['MCUXCLELS_KEY_SLOTS',['../a00764.html#ga68a354e8f8ccdcf5ea6b44458894e11c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeydelete_5fasync',['mcuxClEls_KeyDelete_Async',['../a00759.html#ga035d072c033f988194110973581c6303',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyexport_5fasync',['mcuxClEls_KeyExport_Async',['../a00759.html#ga698ad21f0b3576d2b9f4b7b3ef83134f',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeygen_20option_20word_20values',['MCUXCLELS_KEYGEN option word values',['../a00728.html',1,'']]], + ['mcuxclels_5fkeygen_20option_20bit_20field_20values',['MCUXCLELS_KEYGEN option bit field values',['../a00730.html',1,'']]], + ['mcuxclels_5fkeygen_5fvalue_5fdeterministic',['MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC',['../a00728.html#gabbd15e28f3e551acbc9b786a52bfd238',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5fgen_5fpub_5fkey',['MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY',['../a00728.html#ga4a2e708b9f9c46037356e2f4c6ab662b',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5fno_5fpub_5fkey',['MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY',['../a00728.html#gaa98c6e65867abd8ae959c9771eefcbe6',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5fno_5frandom_5fdata',['MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA',['../a00728.html#ga73dea3b73d48e7b74ba484bb8278e110',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5frandom',['MCUXCLELS_KEYGEN_VALUE_RANDOM',['../a00728.html#ga8bc95eb09238ba6e3716109472fe6c86',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5fsign_5fpublickey',['MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY',['../a00728.html#ga916703c91887cb429f5fc3c9f3f039c9',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5ftype_5fkeyexchange',['MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE',['../a00728.html#ga9263040a043abb0bfaf51fb16ba270e5',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5ftype_5fsign',['MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN',['../a00728.html#ga7bf099956f1b0d5e9b24a654023f28b7',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeygen_5fvalue_5fuse_5frandom_5fdata',['MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA',['../a00728.html#gaf9df52529671dea7267c60318bcfc3ec',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fkeyimport_5fasync',['mcuxClEls_KeyImport_Async',['../a00759.html#ga867d4be563b347273af25a559abd7f87',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fkfmt_5f',['MCUXCLELS_KEYIMPORT_KFMT_',['../a00756.html',1,'']]], + ['mcuxclels_5fkeyimport_5fkfmt_5fpuf',['MCUXCLELS_KEYIMPORT_KFMT_PUF',['../a00756.html#ga757baa3bf038e4f16c63e356a2a590a6',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fkfmt_5frfc3394',['MCUXCLELS_KEYIMPORT_KFMT_RFC3394',['../a00756.html#gaa3f8c4e99d3c233eeaa2685d9e0d4b67',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fkfmt_5fudf',['MCUXCLELS_KEYIMPORT_KFMT_UDF',['../a00756.html#ga1935d246d89a89d4d04c393b40161429',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fvalue_5fkfmt_5f',['MCUXCLELS_KEYIMPORT_VALUE_KFMT_',['../a00755.html',1,'']]], + ['mcuxclels_5fkeyimport_5fvalue_5fkfmt_5fpuf',['MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF',['../a00755.html#gabf3d81b763b4402dd1a4716ca7b10a56',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fvalue_5fkfmt_5frfc3394',['MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394',['../a00755.html#ga8ae5e78cfde658034967faafbbc84c97',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fvalue_5fkfmt_5fudf',['MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF',['../a00755.html#ga984d35cad96543f5cb269a9ee771834b',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimportoption_5ft',['mcuxClEls_KeyImportOption_t',['../a01225.html',1,'']]], + ['mcuxclels_5fkeyindex_5ft',['mcuxClEls_KeyIndex_t',['../a00768.html#ga769227492b28ef0d58a94b202113cee8',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeymanagement',['mcuxClEls_KeyManagement',['../a00753.html',1,'']]], + ['mcuxclels_5fkeymanagement_2eh',['mcuxClEls_KeyManagement.h',['../a00323.html',1,'']]], + ['mcuxclels_5fkeymanagement_5ffunctions',['mcuxClEls_KeyManagement_Functions',['../a00759.html',1,'']]], + ['mcuxclels_5fkeymanagement_5fmacros',['mcuxClEls_KeyManagement_Macros',['../a00754.html',1,'']]], + ['mcuxclels_5fkeymanagement_5ftypes',['mcuxClEls_KeyManagement_Types',['../a00758.html',1,'']]], + ['mcuxclels_5fkeyprop_5ft',['mcuxClEls_KeyProp_t',['../a01237.html',1,'']]], + ['mcuxclels_5fkeyproperty_5f',['MCUXCLELS_KEYPROPERTY_',['../a00766.html',1,'']]], + ['mcuxclels_5fkeyproperty_5factive_5ffalse',['MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE',['../a00766.html#gadba88640610efd722fd6cb31131476ac',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5factive_5ftrue',['MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE',['../a00766.html#ga80e7d70c48a472dba6067d6b8e97bb68',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5faes_5ffalse',['MCUXCLELS_KEYPROPERTY_AES_FALSE',['../a00766.html#ga9960540d8489d2022ee67e60e77858bf',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5faes_5ftrue',['MCUXCLELS_KEYPROPERTY_AES_TRUE',['../a00766.html#gae292b4575efaa152a6a2704c05e079c7',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fbase_5fslot',['MCUXCLELS_KEYPROPERTY_BASE_SLOT',['../a00766.html#ga8a549e38eaccd502bd48a82e95ff20f2',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fckdf_5ffalse',['MCUXCLELS_KEYPROPERTY_CKDF_FALSE',['../a00766.html#ga960f82984c81287e968904ffd41be70c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fckdf_5ftrue',['MCUXCLELS_KEYPROPERTY_CKDF_TRUE',['../a00766.html#ga8d6171d58db58d9ba6e15e7f9cb0c057',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fcmac_5ffalse',['MCUXCLELS_KEYPROPERTY_CMAC_FALSE',['../a00766.html#ga362b93220be9faf000985a3b28380ad0',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fcmac_5ftrue',['MCUXCLELS_KEYPROPERTY_CMAC_TRUE',['../a00766.html#ga2f6b74eae56797b769e35fb9d1d5465e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fdevice_5funique_5ffalse',['MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE',['../a00766.html#ga1ee99e7d2dcd7dd025bd9dbebfe31c2e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fdevice_5funique_5ftrue',['MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE',['../a00766.html#ga265cc12998ae7e8bb54e4f61ae2c21db',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fecc_5fdh_5fprivate_5ffalse',['MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE',['../a00766.html#gaec997cabe18f4c4188a602c39890aadf',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fecc_5fdh_5fprivate_5ftrue',['MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE',['../a00766.html#gaec7f78155e96050db23eaf4a623ea5a7',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fecc_5ffalse',['MCUXCLELS_KEYPROPERTY_ECC_FALSE',['../a00766.html#ga3f8380fec95cb01265199fd2a9e7c5a7',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fecc_5ftrue',['MCUXCLELS_KEYPROPERTY_ECC_TRUE',['../a00766.html#gab457f8b10780aad731269d29445a2333',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fgeneral_5fpurpose_5fslot_5ffalse',['MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE',['../a00766.html#gae3b99cfb55454bdc413aace5afd71890',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fgeneral_5fpurpose_5fslot_5ftrue',['MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE',['../a00766.html#ga7db639faa4a274e77743882b7057c537',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhkdf_5ffalse',['MCUXCLELS_KEYPROPERTY_HKDF_FALSE',['../a00766.html#gaa80640a904308caeb41895739ef281d1',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhkdf_5ftrue',['MCUXCLELS_KEYPROPERTY_HKDF_TRUE',['../a00766.html#gac0b2f4e4b25b10f1674d8baa8d38286e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhmac_5ffalse',['MCUXCLELS_KEYPROPERTY_HMAC_FALSE',['../a00766.html#gabaace8fb57f6d821d042639dd83024b4',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhmac_5ftrue',['MCUXCLELS_KEYPROPERTY_HMAC_TRUE',['../a00766.html#ga0174e78e6f43bf25603e6ac5791d6031',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhw_5fout_5ffalse',['MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE',['../a00766.html#gadade800ab03e3b7693f8a68005205a34',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhw_5fout_5fslot_5ffalse',['MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE',['../a00766.html#ga289019e9ef73c7f796ab0b69d2d5223f',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhw_5fout_5fslot_5ftrue',['MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE',['../a00766.html#ga644cefc65b923481fdf6013ffad6a664',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fhw_5fout_5ftrue',['MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE',['../a00766.html#ga0504273f3b2e50c2574b8a8d83475afb',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5finput_5ffor_5fecc_5ffalse',['MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE',['../a00766.html#ga6bb1e8b818ab13bec2351784f459c815',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5finput_5ffor_5fecc_5ftrue',['MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE',['../a00766.html#ga65bc587af872d79766a1990b644d65ad',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkey_5fsize_5f128',['MCUXCLELS_KEYPROPERTY_KEY_SIZE_128',['../a00766.html#ga4cacf5225b1aa96c74f05b111cfd0298',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkey_5fsize_5f256',['MCUXCLELS_KEYPROPERTY_KEY_SIZE_256',['../a00766.html#ga755a270fd53677522cafd0e56a6be66f',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fksk_5ffalse',['MCUXCLELS_KEYPROPERTY_KSK_FALSE',['../a00766.html#ga432995f0ef41d5b333e9b3829122bc42',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fksk_5ftrue',['MCUXCLELS_KEYPROPERTY_KSK_TRUE',['../a00766.html#ga00953660d09e3ed62645b167851b9cc9',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkuok_5ffalse',['MCUXCLELS_KEYPROPERTY_KUOK_FALSE',['../a00766.html#gaed363ebd3822cf20b7b6eb97477e4683',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkuok_5ftrue',['MCUXCLELS_KEYPROPERTY_KUOK_TRUE',['../a00766.html#ga116b9a68bec502c77b49b95189cdd51c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkwk_5ffalse',['MCUXCLELS_KEYPROPERTY_KWK_FALSE',['../a00766.html#ga456e3e1f4c7dbfedb45b81407b55619b',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fkwk_5ftrue',['MCUXCLELS_KEYPROPERTY_KWK_TRUE',['../a00766.html#ga8f78e035c0c348d9c95250cbb5c06bdc',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fprivileged_5ffalse',['MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE',['../a00766.html#gaa613ab074bf3fc6b9f90a69f505d2e28',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fprivileged_5ftrue',['MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE',['../a00766.html#ga45d5d7ba7da1060c55a4bac5279841cc',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fretention_5fslot_5ffalse',['MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE',['../a00766.html#ga69b01ec32c2541c387b1bab005e4b03e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fretention_5fslot_5ftrue',['MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE',['../a00766.html#ga9f77c7afd0e967dbde5dfd67b8d41257',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5frtf_5ffalse',['MCUXCLELS_KEYPROPERTY_RTF_FALSE',['../a00766.html#ga8a942c5fc98bc8ffdc5f009ba3bfa29c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5frtf_5ftrue',['MCUXCLELS_KEYPROPERTY_RTF_TRUE',['../a00766.html#gad03052755431d2adfeaa30277e418f04',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fsecond_5fslot',['MCUXCLELS_KEYPROPERTY_SECOND_SLOT',['../a00766.html#ga2a587ef5925801237ed4289ba7124bc1',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fsecure_5ffalse',['MCUXCLELS_KEYPROPERTY_SECURE_FALSE',['../a00766.html#gae85a65c3e6ae36cc74de69fa6a562a7a',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fsecure_5ftrue',['MCUXCLELS_KEYPROPERTY_SECURE_TRUE',['../a00766.html#ga2088d83e8ab366a72075f52e3ca352ad',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5ftls_5fmaster_5fsecret_5ffalse',['MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE',['../a00766.html#ga4723acef377d8337e76cf3a24b0e32df',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5ftls_5fmaster_5fsecret_5ftrue',['MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE',['../a00766.html#ga821ec254e0847c27f58345e3be802768',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5ftls_5fpremaster_5fsecret_5ffalse',['MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE',['../a00766.html#gab55f1e3817acebe4ac54babddac0ae54',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5ftls_5fpremaster_5fsecret_5ftrue',['MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE',['../a00766.html#gafb78c8a3541eb87092a513461fd77b16',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5f',['MCUXCLELS_KEYPROPERTY_VALUE_',['../a00765.html',1,'']]], + ['mcuxclels_5fkeyproperty_5fvalue_5factive',['MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE',['../a00765.html#ga38ccbdbdaade2b7880d64982044e8035',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5faes',['MCUXCLELS_KEYPROPERTY_VALUE_AES',['../a00765.html#gac45ebca89b1aa9788366cb5d1bbc92f8',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fbase_5fslot',['MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT',['../a00765.html#gabbdb03610e94b456d47ad12d7a12140e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fckdf',['MCUXCLELS_KEYPROPERTY_VALUE_CKDF',['../a00765.html#ga005bacc1cb8c881365bdf22cc3264af5',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fcmac',['MCUXCLELS_KEYPROPERTY_VALUE_CMAC',['../a00765.html#gae181bcf54a9e911574ac80f47e9478b0',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fduk',['MCUXCLELS_KEYPROPERTY_VALUE_DUK',['../a00765.html#ga5333f4f5fd6978a1c4bd9e6cae7a4955',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fecdh',['MCUXCLELS_KEYPROPERTY_VALUE_ECDH',['../a00765.html#gaa50202ab187ade63e84c8b589a08ce58',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fecsgn',['MCUXCLELS_KEYPROPERTY_VALUE_ECSGN',['../a00765.html#ga3a77d34b3cdb470dbe9cbac0c6383488',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fgeneral_5fpurpose_5fslot',['MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT',['../a00765.html#gad18d55603e3e1563ea9da2edafc26315',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fhkdf',['MCUXCLELS_KEYPROPERTY_VALUE_HKDF',['../a00765.html#gaa4e7e020109bb4a83c8f05f17fb860bb',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fhmac',['MCUXCLELS_KEYPROPERTY_VALUE_HMAC',['../a00765.html#ga64d0aa24d8057d5c96b8bc1a6f5d8711',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fhw_5fout',['MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT',['../a00765.html#ga7388b2da16ebf2291f6b4a682240f073',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fhw_5fout_5fslot',['MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT',['../a00765.html#ga7f07dfb893d2d9cd087f63c931f2ca29',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fkey_5fsize_5f128',['MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128',['../a00765.html#ga20705a3a067d321f364a1c5b278a32d8',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fkey_5fsize_5f256',['MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256',['../a00765.html#gaa605da5172899ce79cb55909ed4a3464',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fkgsrc',['MCUXCLELS_KEYPROPERTY_VALUE_KGSRC',['../a00765.html#ga70889526167cbf5e75912e430372a993',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fksk',['MCUXCLELS_KEYPROPERTY_VALUE_KSK',['../a00765.html#ga6dc65c24d84015a37cc697a1f8ebfa94',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fkuok',['MCUXCLELS_KEYPROPERTY_VALUE_KUOK',['../a00765.html#ga40d6978ccb822e1dccd7701cc635ffc9',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fkwk',['MCUXCLELS_KEYPROPERTY_VALUE_KWK',['../a00765.html#ga518248d788f4fe3746c9ca910d70f38b',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fnotprivileged',['MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED',['../a00765.html#ga193c53f3465e549c04bffb48c614b976',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fnotsecure',['MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE',['../a00765.html#gaee9d5c2f7654dab8449372339f6eb857',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fprivileged',['MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED',['../a00765.html#ga714925236ac3417792b5b51054c5f479',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fretention_5fslot',['MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT',['../a00765.html#gaacc968f77f54b1b66903aecb8fbb1e1c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5frtf',['MCUXCLELS_KEYPROPERTY_VALUE_RTF',['../a00765.html#ga0a33beb3623a2c3d1bdd1d3194419b51',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fsecure',['MCUXCLELS_KEYPROPERTY_VALUE_SECURE',['../a00765.html#ga938259096a964f99992874407cb75b5b',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5ftls_5fmaster_5fsecret',['MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET',['../a00765.html#gac71ffc243f1c14fea51a8cfe0a5bb7da',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5ftls_5fpremaster_5fsecret',['MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET',['../a00765.html#gadc12177ca1a434524bf41e3e646bea4c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fvalue_5fwrpok',['MCUXCLELS_KEYPROPERTY_VALUE_WRPOK',['../a00765.html#gadf248e85c19983b971956e30471b5b68',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fwrap_5ffalse',['MCUXCLELS_KEYPROPERTY_WRAP_FALSE',['../a00766.html#ga1b9c490f4f9556731df00636c902c76a',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fkeyproperty_5fwrap_5ftrue',['MCUXCLELS_KEYPROPERTY_WRAP_TRUE',['../a00766.html#gaf07168a64eb99d5788e096d735871c3f',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5flimitedwaitforoperation',['mcuxClEls_LimitedWaitForOperation',['../a00717.html#ga396f130363332586a56b9667cf46fe7e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fmapping_2eh',['mcuxClEls_mapping.h',['../a00326.html',1,'']]], + ['mcuxclels_5fprng_5fgetrandom',['mcuxClEls_Prng_GetRandom',['../a00762.html#ga222cf598c85ceb0483297169255688b0',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5fprng_5fgetrandomword',['mcuxClEls_Prng_GetRandomWord',['../a00762.html#ga10ee7783feeef4fbe5d5309c61f358a1',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5freset_5f',['MCUXCLELS_RESET_',['../a00712.html',1,'']]], + ['mcuxclels_5freset_5fasync',['mcuxClEls_Reset_Async',['../a00717.html#ga988b48898347ef4de0912cae0f631764',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5freset_5fcancel',['MCUXCLELS_RESET_CANCEL',['../a00712.html#ga1f4338ba7f7d0ddd5b84236bc4545ee3',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5freset_5fdo_5fnot_5fcancel',['MCUXCLELS_RESET_DO_NOT_CANCEL',['../a00712.html#gac02fc8694aa89061b1eb47bad8fca21d',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5freseterrorflags',['mcuxClEls_ResetErrorFlags',['../a00717.html#gaf5485491a0851bc3c475e50690219d74',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fresetintflags',['mcuxClEls_ResetIntFlags',['../a00717.html#ga02f29ce399968793e6091505ddd9fa5e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fresetoption_5ft',['mcuxClEls_ResetOption_t',['../a00716.html#gab1ed08db7ad22b92ac714d17566d2fff',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5frfc3394_5f',['MCUXCLELS_RFC3394_',['../a00757.html',1,'']]], + ['mcuxclels_5frfc3394_5fcontainer_5fsize_5f128',['MCUXCLELS_RFC3394_CONTAINER_SIZE_128',['../a00757.html#ga4d0fa5e5255eb1fa89b0cf6a30a452fb',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5frfc3394_5fcontainer_5fsize_5f256',['MCUXCLELS_RFC3394_CONTAINER_SIZE_256',['../a00757.html#ga46c8e56ff10c6a6ecb28c511cd32178c',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5frfc3394_5foverhead',['MCUXCLELS_RFC3394_OVERHEAD',['../a00756.html#ga9c38ef72ae48380b864e6e5fb950ee17',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5frng',['mcuxClEls_Rng',['../a00760.html',1,'']]], + ['mcuxclels_5frng_2eh',['mcuxClEls_Rng.h',['../a00329.html',1,'']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fextract_5foutput_5fmax_5fsize',['MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE',['../a00761.html#ga28815696e8ff825c435f97fd74a63682',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fextract_5foutput_5fmin_5fsize',['MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE',['../a00761.html#ga4e1cd62dea9fd027f68c6e95f887a052',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fmode_5faes_5fctr',['MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR',['../a00761.html#gafe0506d5703701493637b44873e80f9c',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fmode_5faes_5fecb',['MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB',['../a00761.html#gac1504aed0077bef23daf988d3630b089',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fmode_5fextract',['MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT',['../a00761.html#ga6e8e503cbc286ca4082b3f8f757e43b8',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbg_5ftest_5fmode_5finstantiate',['MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE',['../a00761.html#gaefdcd27bd482d26a59b449860c7c07e6',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgrequest_5fasync',['mcuxClEls_Rng_DrbgRequest_Async',['../a00762.html#gac48eddfc58d2fc6aebe0dd373baf4360',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestaesctr_5fasync',['mcuxClEls_Rng_DrbgTestAesCtr_Async',['../a00762.html#gada018f6414175632aa2328ffd2ed02bf',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestaesecb_5fasync',['mcuxClEls_Rng_DrbgTestAesEcb_Async',['../a00762.html#gaa356b6cafdb26f78c90fc9a24dd7dcd8',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestextract_5fasync',['mcuxClEls_Rng_DrbgTestExtract_Async',['../a00762.html#ga89b800a51c4046c7c7736d545595e097',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestinstantiate_5fasync',['mcuxClEls_Rng_DrbgTestInstantiate_Async',['../a00762.html#ga17e52c0038540a032faf460033df35e6',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5fconfig_5fsize',['MCUXCLELS_RNG_DTRNG_CONFIG_SIZE',['../a00761.html#ga62287bdc5d7f577d4196b409fa9e27c2',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5fconfigevaluate_5fasync',['mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async',['../a00762.html#gac7fb747c02024315df352977d8269535',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5fconfigload_5fasync',['mcuxClEls_Rng_Dtrng_ConfigLoad_Async',['../a00762.html#ga254ab1259a0688701233e1cf3636b244',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5feval_5fconfig_5fsize',['MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE',['../a00761.html#ga05b362ef8faa883390e693f6f0499261',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5feval_5fresult_5fsize',['MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE',['../a00761.html#ga612e743bb2a36fec076fbf45bb9fb871',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5ffunctions',['mcuxClEls_Rng_Functions',['../a00762.html',1,'']]], + ['mcuxclels_5frng_5fmacros',['mcuxClEls_Rng_Macros',['../a00761.html',1,'']]], + ['mcuxclels_5frng_5fprng_5fget_5frandom_5fexample_2ec',['mcuxClEls_Rng_Prng_Get_Random_example.c',['../a00026.html',1,'']]], + ['mcuxclels_5fsetintenableflags',['mcuxClEls_SetIntEnableFlags',['../a00717.html#ga1cfec63993fa918d3b590b41b3558d84',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fsetintflags',['mcuxClEls_SetIntFlags',['../a00717.html#ga90b8060544476c2e7278157833410c97',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fsetrandomstartdelay',['mcuxClEls_SetRandomStartDelay',['../a00717.html#gabe9a2fe0df05c3e99fcd4a7a9138a2c8',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5f',['MCUXCLELS_STATUS_',['../a00767.html',1,'']]], + ['mcuxclels_5fstatus_5fdrbgentlvl_5f',['MCUXCLELS_STATUS_DRBGENTLVL_',['../a00715.html',1,'']]], + ['mcuxclels_5fstatus_5fdrbgentlvl_5fhigh',['MCUXCLELS_STATUS_DRBGENTLVL_HIGH',['../a00715.html#ga9e70aa4c959f092c77fc154327bc4bdb',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fdrbgentlvl_5flow',['MCUXCLELS_STATUS_DRBGENTLVL_LOW',['../a00715.html#ga1276cd61f68f743f631cdae25662b310',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fdrbgentlvl_5fnone',['MCUXCLELS_STATUS_DRBGENTLVL_NONE',['../a00715.html#ga5fe71d0b1d8e1c52794c24a98b6e2645',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fecdsavfy_5f',['MCUXCLELS_STATUS_ECDSAVFY_',['../a00714.html',1,'']]], + ['mcuxclels_5fstatus_5fecdsavfy_5ferror',['MCUXCLELS_STATUS_ECDSAVFY_ERROR',['../a00714.html#ga9472855457417ea944570647a61c2b47',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fecdsavfy_5ffail',['MCUXCLELS_STATUS_ECDSAVFY_FAIL',['../a00714.html#ga647b29383be891aba96ede66ae327401',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fecdsavfy_5fnorun',['MCUXCLELS_STATUS_ECDSAVFY_NORUN',['../a00714.html#ga47e2750982e2b0db292e2a9944c1f635',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fecdsavfy_5fok',['MCUXCLELS_STATUS_ECDSAVFY_OK',['../a00714.html#ga893b34cd2238053fb44a50ebe33bb5e3',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fhw_5falgorithm',['MCUXCLELS_STATUS_HW_ALGORITHM',['../a00767.html#gacf60910b71f03c324d53f8b6563baf4c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5fbus',['MCUXCLELS_STATUS_HW_BUS',['../a00767.html#ga84e18c7cc39ffd66abc53f7353269a84',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5fdtrng',['MCUXCLELS_STATUS_HW_DTRNG',['../a00767.html#ga1dc849dc5b6501b5f1c9e68f89f07881',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5ffault',['MCUXCLELS_STATUS_HW_FAULT',['../a00767.html#ga5903a9bf2687c19a6a4c89a0486f2ccb',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5fintegrity',['MCUXCLELS_STATUS_HW_INTEGRITY',['../a00767.html#gac58ea9f6e1103f32cd5cac0b2c45549c',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5foperational',['MCUXCLELS_STATUS_HW_OPERATIONAL',['../a00767.html#ga6f70e740d4b57dc50083fd6f052ad434',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fhw_5fprng',['MCUXCLELS_STATUS_HW_PRNG',['../a00767.html#ga1ba84ebe125bbe9dc402d9089bc46164',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fis_5fhw_5ferror',['MCUXCLELS_STATUS_IS_HW_ERROR',['../a00764.html#gae333a22199f8899e33304329a5ea3a3e',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fis_5fsw_5ferror',['MCUXCLELS_STATUS_IS_SW_ERROR',['../a00764.html#ga1787a44ce530639142f3a63e5c38f1b5',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fok',['MCUXCLELS_STATUS_OK',['../a00767.html#ga022996920a649ed71428ed73e53eae8a',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fok_5fwait',['MCUXCLELS_STATUS_OK_WAIT',['../a00767.html#ga0c69ecf4e48929c38549c8b430dae4b2',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fpprot_5f',['MCUXCLELS_STATUS_PPROT_',['../a00713.html',1,'']]], + ['mcuxclels_5fstatus_5fpprot_5fprivileged_5fnonsecure',['MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE',['../a00713.html#ga9fd4449827c0ff5467277eca65c9d647',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fpprot_5fprivileged_5fsecure',['MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE',['../a00713.html#ga11ba151ce5c794f3f433b1261c95f68c',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fpprot_5funprivileged_5fnonsecure',['MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE',['../a00713.html#gab95d873091d5a836bc3e37079766fb2e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fpprot_5funprivileged_5fsecure',['MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE',['../a00713.html#gaa8bbf4768eed46d69b6a9077f51c1481',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fprotected_5ft',['mcuxClEls_Status_Protected_t',['../a00768.html#ga9d1e537d1dc0c3eda9c26ba9e82e0596',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5fcannot_5finterrupt',['MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT',['../a00767.html#ga20ac618d5c0b386df110135322b94ed6',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5fcomparison_5ffailed',['MCUXCLELS_STATUS_SW_COMPARISON_FAILED',['../a00767.html#gaddad780e0aef6a33d31b800ecb8673cd',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5fcounter_5fexpired',['MCUXCLELS_STATUS_SW_COUNTER_EXPIRED',['../a00767.html#gaf10c1ef8b7689807ed2d163fe71c4b89',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5ffault',['MCUXCLELS_STATUS_SW_FAULT',['../a00767.html#gad3b3fde6156b816225f119a525c7f0b4',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5finvalid_5fparam',['MCUXCLELS_STATUS_SW_INVALID_PARAM',['../a00767.html#ga96347d1bd07cc9ee18688f1973219878',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5fsw_5finvalid_5fstate',['MCUXCLELS_STATUS_SW_INVALID_STATE',['../a00767.html#gac167d607babe9a7f93950b581c08bdef',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5ft',['mcuxClEls_Status_t',['../a00768.html#ga734d7200290fe0eda6ef3347f52177f3',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5ftls_5fderivationdata_5fsize',['MCUXCLELS_TLS_DERIVATIONDATA_SIZE',['../a00750.html#ga542a08e762e187464b77a707973eff65',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftls_5ffinalize',['MCUXCLELS_TLS_FINALIZE',['../a00750.html#gac9f01f30577af236ba91f31c78c428d2',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftls_5finit',['MCUXCLELS_TLS_INIT',['../a00750.html#gaecd87e8690f333b6747f9e29848dfd08',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftls_5fmaster_5fkey_5fsession_5fkeys_5fexample_2ec',['mcuxClEls_Tls_Master_Key_Session_Keys_example.c',['../a00029.html',1,'']]], + ['mcuxclels_5ftls_5frandom_5fsize',['MCUXCLELS_TLS_RANDOM_SIZE',['../a00750.html#gaf6beb56c924bf4d0bcea3a6fa31803be',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftlsgeneratemasterkeyfrompremasterkey_5fasync',['mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async',['../a00752.html#gac8b832b6cfa9c2b15b51be04ab349ae6',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftlsgeneratesessionkeysfrommasterkey_5fasync',['mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async',['../a00752.html#ga50b0d0753ed6a370b187904db49826ff',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftlsoption_5ft',['mcuxClEls_TlsOption_t',['../a01213.html',1,'']]], + ['mcuxclels_5ftransfertoregisterfunction_5ft',['mcuxClEls_TransferToRegisterFunction_t',['../a00768.html#gacb342d252ea80b11e90b781c5e1aa331',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5ftypes',['mcuxClEls_Types',['../a00763.html',1,'']]], + ['mcuxclels_5ftypes_2eh',['mcuxClEls_Types.h',['../a00332.html',1,'']]], + ['mcuxclels_5ftypes_5fmacros',['mcuxClEls_Types_Macros',['../a00764.html',1,'']]], + ['mcuxclels_5ftypes_5ftypes',['mcuxClEls_Types_Types',['../a00768.html',1,'']]], + ['mcuxclels_5fupdaterefcrc',['mcuxClEls_UpdateRefCRC',['../a00724.html#gae04ed3290d9cb48f42f4f9aed4b1a825',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fverifyvsrefcrc',['mcuxClEls_VerifyVsRefCRC',['../a00724.html#ga5ebf64e6470c7a08c56ee44d9afe3990',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fwaitforoperation',['mcuxClEls_WaitForOperation',['../a00717.html#gaee73cb4825b7722d9e085565170eb18e',1,'mcuxClEls_Common.h']]], + ['mcuxclexample_5ffunction',['MCUXCLEXAMPLE_FUNCTION',['../a00002.html#a4557ce4897e01774148f2f764c833b3a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#a771a0ec79a4dd825868d4be9bc76c6b7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00008.html#a7871444a5008d1d5409e35c7c1cbd1d3',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Ecc_Keygen_Sign_Verify_example): mcuxClEls_Ecc_Keygen_Sign_Verify_example.c'],['../a00011.html#a2d5de980923b27edc61a1c9ffb521a1e',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Common_Get_Info_example): mcuxClEls_Common_Get_Info_example.c'],['../a00014.html#ab89d2312fc5c2fdc0298cc1ae1f278e3',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha224_One_Block_example): mcuxClEls_Hash_Sha224_One_Block_example.c'],['../a00017.html#ac6870823b93f74e0bc36a7d1d471bd9d',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha256_One_Block_example): mcuxClEls_Hash_Sha256_One_Block_example.c'],['../a00020.html#a5a28e0b6909b5d91b26a95077092fae7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha384_One_Block_example): mcuxClEls_Hash_Sha384_One_Block_example.c'],['../a00023.html#aca162de2f88b777e78145615790dde8d',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha512_One_Block_example): mcuxClEls_Hash_Sha512_One_Block_example.c'],['../a00026.html#a4533123497ea62887db3256587ae76ac',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Rng_Prng_Get_Random_example): mcuxClEls_Rng_Prng_Get_Random_example.c'],['../a00029.html#afca899ba16d4b475a0e780589dbfc560',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Tls_Master_Key_Session_Keys_example): mcuxClEls_Tls_Master_Key_Session_Keys_example.c'],['../a00032.html#afa131c8f7a3740ff4732892b4db16bec',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Key_Import_Puk_DER_example): mcuxClEls_Key_Import_Puk_DER_example.c'],['../a00035.html#a39688ef490286a2fed36617ad2c02795',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Multipart_Els_Ccm_Example): mcuxClAeadModes_Multipart_Els_Ccm_Example.c'],['../a00038.html#a54de761e25b3fd9e3b4d7e5b90ebd7ca',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Ccm_Example): mcuxClAeadModes_Oneshot_Els_Ccm_Example.c'],['../a00041.html#a92d351633686713a2dc9f051c5d63c12',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Gcm_Example): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c'],['../a00074.html#a75d0a2ced8164c38afbd0c95a1ff6686',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve25519_example): mcuxClEcc_Mont_Curve25519_example.c'],['../a00077.html#addf8fd48c03094abe17db5e808ed580c',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve448_example): mcuxClEcc_Mont_Curve448_example.c'],['../a00080.html#a9e584bfb84b74adc18f23fb9774ff2e7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example): mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c'],['../a00116.html#a4d4124fd2881a1d89bcb320735293fc7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClKey_example): mcuxClKey_example.c'],['../a00119.html#a71e50006ff7948794718e7aee5ca982a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClMacModes_cmac_oneshot_example): mcuxClMacModes_cmac_oneshot_example.c'],['../a00134.html#a4fb93b93e2f83f913ca6d51af1f61e0a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_ELS_example): mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c'],['../a00137.html#a91004e78f2323ae2750f3db18d7ed12f',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_ELS_example): mcuxClRandomModes_ELS_example.c'],['../a00140.html#a824a93e2c644f62de4ab1c413f3cdeaa',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG3_example): mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c'],['../a00143.html#a9b0834b958b1450723fab20a00fcefe1',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_Different_Sessions_example): mcuxClRandomModes_Different_Sessions_example.c'],['../a00146.html#a8cbc037b8fa449be72bf01c6b63ca7a7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG4_example): mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c'],['../a00149.html#a7cbd851346a84954cad6892fe66c1d90',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example): mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c'],['../a00152.html#a99ac8d5cb62fa1f7978221415653da14',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example): mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c'],['../a00155.html#a986952eb07f2ec086c4f6ff46bbbc9a0',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example): mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c'],['../a00158.html#a7299c7736f173efca4ade8d274e7d75b',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_pssverify_sha2_256_example): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a20789e8a17209cfcf845dd22d8a02462',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_pss_sha2_256_example): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#ab0f06c91945e4c60608e1508e1a40fdf',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_NoVerify_example): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#a80d285764029b6fa279a51015d492960',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_NoEncode_example): mcuxClRsa_sign_NoEncode_example.c']]], + ['mcuxclhash',['mcuxClHash',['../a00769.html',1,'']]], + ['mcuxclhash_2eh',['mcuxClHash.h',['../a00353.html',1,'']]], + ['mcuxclhash_5falgo_5ft',['mcuxClHash_Algo_t',['../a00773.html#ga0ffeeb89c76da6470176e7621713e1b2',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5falgorithm_5fsha224',['mcuxClHash_Algorithm_Sha224',['../a00774.html#ga4de6a5917dc46d3aae22f93df66fc228',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha256',['mcuxClHash_Algorithm_Sha256',['../a00774.html#ga672407195f718d55fcee73d1dfb7c623',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha384',['mcuxClHash_Algorithm_Sha384',['../a00774.html#gaa7389b8db9ec5c97b44db899e2b9f8db',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha512',['mcuxClHash_Algorithm_Sha512',['../a00774.html#gae0687309bef869b41302594c6c934d9a',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha224',['mcuxClHash_AlgorithmDescriptor_Sha224',['../a00774.html#ga56d71cf5a53a9e64a648c4d9776efa8e',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha256',['mcuxClHash_AlgorithmDescriptor_Sha256',['../a00774.html#ga0332b3c0540cd1761dfaa17b33f02f02',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha384',['mcuxClHash_AlgorithmDescriptor_Sha384',['../a00774.html#ga18de1261f5761dfc43ef89a102fda259',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha512',['mcuxClHash_AlgorithmDescriptor_Sha512',['../a00774.html#ga50a5ce5101cf1175127bdf1ea7bfb0e1',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5ft',['mcuxClHash_AlgorithmDescriptor_t',['../a00773.html#gacccec0a811d221d2cb0fd8416da271d8',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a8e985e955759e3f5f6fb1d11c3901e2c',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f224',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224',['../a00776.html#ga8ff96915814df592db3d68d925408a98',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f256',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256',['../a00776.html#gaa98512fd1ef5f7d8310a811035811fbb',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f384',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384',['../a00776.html#gaa4c0e341d16ed5fe2be37691f582e326',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512',['../a00776.html#ga762efcb01b7aaf95266adfb3c9b174b0',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f224',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224',['../a00776.html#ga6dbc0f41ec9388bbc8aeb99e2ee37230',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f256',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256',['../a00776.html#ga3e3ada3faaecda7fbef060e2c3e835f8',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompare_5fequal',['MCUXCLHASH_COMPARE_EQUAL',['../a00771.html#ga05eaccf399e17f323499f31e764d5173',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fcompare_5fnot_5fequal',['MCUXCLHASH_COMPARE_NOT_EQUAL',['../a00771.html#ga647cd722111188a5d028d1f3ab4eb795',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fcompute',['mcuxClHash_compute',['../a00772.html#ga7beb1bb4063eae682eca700efeba93db',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a8b3af117f171a613124593df58ada62a',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f224',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224',['../a00776.html#ga40b9eff6f42215fc5c98c0513fbd2c79',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f256',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256',['../a00776.html#ga0ebf52b4105a30badc619e7ba70193b3',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f384',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384',['../a00776.html#ga55b9dabdce9439ad6fec034dc86ead8c',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512',['../a00776.html#gaa7b677e561a919060c8c1eae1c5f2455',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f224',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224',['../a00776.html#gaa1ea090ae23f0e04f553cdfbeb2573a9',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f256',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256',['../a00776.html#gac7c04d4fd538f29eb200ae68a076853e',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fconstants',['mcuxClHash_Constants',['../a00770.html',1,'']]], + ['mcuxclhash_5fconstants_2eh',['mcuxClHash_Constants.h',['../a00356.html',1,'']]], + ['mcuxclhash_5fcontext_5fsize',['MCUXCLHASH_CONTEXT_SIZE',['../a00362.html#a42253ef03c357fbdcc8a0c502f34c4f3',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fcontext_5ft',['mcuxClHash_Context_t',['../a00773.html#ga84c437ceb6b43a992b75866f793d0956',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fcontextdescriptor_5ft',['mcuxClHash_ContextDescriptor_t',['../a00773.html#ga90ff7c4f43e59b80eca542e35722124c',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fexport_5fimport_5fstate_5fsize_5fsha2_5f224',['MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224',['../a00777.html#ga64ea4a6c44d5714d06cde9c858ca963f',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fexport_5fimport_5fstate_5fsize_5fsha2_5f256',['MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256',['../a00777.html#gac40907ce6e09e87b7931823ad48a50c3',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fexport_5fimport_5fstate_5fsize_5fsha2_5f384',['MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384',['../a00777.html#ga09b5656067c3ab3e89c3d0aaa9f2e5ad',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fexport_5fimport_5fstate_5fsize_5fsha2_5f512',['MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512',['../a00777.html#gad09b3d78d2a33f965308f2e4c34ea0cf',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fexport_5fstate_5fnot_5fmultiple_5fof_5fblock',['MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK',['../a00771.html#ga5cb4d265e6848270e5a3e38b5e57e84a',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5ffailure',['MCUXCLHASH_FAILURE',['../a00771.html#gaaef282127a4c3c3e8f9a034cba1b70e0',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5ffinish',['mcuxClHash_finish',['../a00772.html#gad55cc3a702b915f84d9cd2e94c2b7f6b',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a63da111398b07963ed1a77da6c97a64d',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f224',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224',['../a00776.html#gae23cdd9e00a486600ee5b90949f3842f',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f256',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256',['../a00776.html#ga7e0a2938cc503a204da719c7b8aab627',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f384',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384',['../a00776.html#ga64ac4667e73071d261d273b72abc70d9',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512',['../a00776.html#ga0b23abb47f314adac81fa08cabded273',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f224',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224',['../a00776.html#ga1d3671a1c73c8ef559ac12b3206ab952',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f256',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256',['../a00776.html#ga95fcec323ebd8dbfddc56a99e6f49900',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5ffunctions',['mcuxClHash_Functions',['../a00772.html',1,'']]], + ['mcuxclhash_5ffunctions_2eh',['mcuxClHash_Functions.h',['../a00359.html',1,'']]], + ['mcuxclhash_5finit',['mcuxClHash_init',['../a00772.html#ga68263436904cf849bfbe8c9b1f6542d4',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5finit_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE',['../a00362.html#a8434a263faa18d7d5f1db037eca3a130',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fmax_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE',['../a00362.html#a8c70073fba8e9b6bdd946ca99e3dfcf4',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fmax_5foutput_5fsize',['MCUXCLHASH_MAX_OUTPUT_SIZE',['../a00775.html#ga1be4781928bd9fa5aa9ea9fc9140320b',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5fmemoryconsumption_2eh',['mcuxClHash_MemoryConsumption.h',['../a00362.html',1,'']]], + ['mcuxclhash_5foutput_5fsize_5f',['MCUXCLHASH_OUTPUT_SIZE_',['../a00775.html',1,'']]], + ['mcuxclhash_5foutput_5fsize_5fmd5',['MCUXCLHASH_OUTPUT_SIZE_MD5',['../a00775.html#gafe7e3fec63db293d11223cf996b0f933',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5f224',['MCUXCLHASH_OUTPUT_SIZE_SHA3_224',['../a00775.html#ga9b455baf1195244a5a21f95d24d1bb78',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5f256',['MCUXCLHASH_OUTPUT_SIZE_SHA3_256',['../a00775.html#ga2d4ce7c5407c45486781710968933d59',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5f384',['MCUXCLHASH_OUTPUT_SIZE_SHA3_384',['../a00775.html#ga9ba519f3947e62fe3c33ba89912415f2',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5f512',['MCUXCLHASH_OUTPUT_SIZE_SHA3_512',['../a00775.html#ga98c0f235847458f6e0785ce7e1fa4de1',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5fcshake_5f128',['MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128',['../a00775.html#gabee2279c4070bb6e490acc465d19f7b1',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5fcshake_5f256',['MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256',['../a00775.html#ga1310682860222f35228b9b69e9110b7b',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5fshake_5f128',['MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128',['../a00775.html#gaf92c4c2afd86cf0276655d833fc92946',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha3_5fshake_5f256',['MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256',['../a00775.html#ga6208318273d199569492d2df54285bfb',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f1',['MCUXCLHASH_OUTPUT_SIZE_SHA_1',['../a00775.html#ga8e6f2196aa9cc22514327290e9c6d265',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f224',['MCUXCLHASH_OUTPUT_SIZE_SHA_224',['../a00775.html#ga4f3a086ffb19f8127e04dd2e9c458a48',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f256',['MCUXCLHASH_OUTPUT_SIZE_SHA_256',['../a00775.html#gaf4d4bd473c10a1c0e474dfa6ebad83d3',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f384',['MCUXCLHASH_OUTPUT_SIZE_SHA_384',['../a00775.html#gad9f68a357e04e78a8930ae8575d2fb95',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f512',['MCUXCLHASH_OUTPUT_SIZE_SHA_512',['../a00775.html#gab3854625bf1807c8be0d0eda40c9b15c',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f512_5f224',['MCUXCLHASH_OUTPUT_SIZE_SHA_512_224',['../a00775.html#ga2b26c1ca0f30feb3c3e12f97ca433935',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5foutput_5fsize_5fsha_5f512_5f256',['MCUXCLHASH_OUTPUT_SIZE_SHA_512_256',['../a00775.html#ga106037a11d7e73694703696f1cbd9b8a',1,'mcuxClHashModes_Constants.h']]], + ['mcuxclhash_5fprocess',['mcuxClHash_process',['../a00772.html#ga49bdf3dca9746328fe58e6d5859e92eb',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#ac7007695fab49af24194295d81f80b56',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f224',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224',['../a00776.html#ga2ff77f524496774f46c5294dfc7619bf',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f256',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256',['../a00776.html#ga6a38dced70e095517b706930b2c164c4',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f384',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384',['../a00776.html#gaeca1828134728d6d1d7da343711934e6',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512',['../a00776.html#gac571e29844bf3dc2cd052c28e40dc90e',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f224',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224',['../a00776.html#gab081523fa0e85169ed405bd514f0e318',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f256',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256',['../a00776.html#gac38cbbdbd0ae6c935f09f75ba51bf8de',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fstatus_5f',['MCUXCLHASH_STATUS_',['../a00771.html',1,'']]], + ['mcuxclhash_5fstatus_5fcompare_5fequal',['MCUXCLHASH_STATUS_COMPARE_EQUAL',['../a00771.html#gaaf06d7932b91cce6e94312a534f61934',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5fcompare_5fnot_5fequal',['MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL',['../a00771.html#gad39c265fd8728f3287eeef999cfeb599',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5fexport_5fstate_5fnot_5fmultiple_5fof_5fblock',['MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK',['../a00771.html#gabeb9fdba3834bd6d1b62b53d0b981bb9',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5ffailure',['MCUXCLHASH_STATUS_FAILURE',['../a00771.html#ga377eaddc82740c4c4590688c754f78a0',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5ffault_5fattack',['MCUXCLHASH_STATUS_FAULT_ATTACK',['../a00771.html#gaca3624d074b137e5587052f6ffb1b6f6',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5ffull',['MCUXCLHASH_STATUS_FULL',['../a00771.html#ga9abcd3d90166d6f4fd532d8b7c24931f',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5finvalid_5fparams',['MCUXCLHASH_STATUS_INVALID_PARAMS',['../a00771.html#ga6cd095f16a5ff26877cc877cecbd0e2b',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5fok',['MCUXCLHASH_STATUS_OK',['../a00771.html#gadf29410b02d95357d48a3ba443558da4',1,'mcuxClHash_Constants.h']]], + ['mcuxclhash_5fstatus_5ft',['mcuxClHash_Status_t',['../a00773.html#gacdfd7a833fcd06684a73c22364e89b7c',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5ftypes',['mcuxClHash_Types',['../a00773.html',1,'']]], + ['mcuxclhash_5ftypes_2eh',['mcuxClHash_Types.h',['../a00365.html',1,'']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a59a048780405bb5b38b256cf689bdf80',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f224',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224',['../a00776.html#gabf598385358401cea01d065d9d421d87',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f256',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256',['../a00776.html#gaf0e29b1e66d6d5a8af6b4c20ec5bb85e',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f384',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384',['../a00776.html#ga2dc773fc49bfd2c5dd1fc298a3dadb35',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512',['../a00776.html#ga50e9da09a4a92534775a94da69c17b48',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f224',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224',['../a00776.html#ga9e3c10d8b549eba86ff96332417ecbdb',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fsha2_5f512_5f256',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256',['../a00776.html#ga000d10c6a9b9475289a7ff08cb283394',1,'mcuxClHashModes_MemoryConsumption.h']]], + ['mcuxclhashmodes_5falgorithms',['mcuxClHashModes_Algorithms',['../a00774.html',1,'']]], + ['mcuxclhashmodes_5falgorithms_2eh',['mcuxClHashModes_Algorithms.h',['../a00371.html',1,'']]], + ['mcuxclhashmodes_5fconstants_2eh',['mcuxClHashModes_Constants.h',['../a00374.html',1,'']]], + ['mcuxclhashmodes_5fcontextsize',['mcuxClHashModes_ContextSize',['../a00777.html',1,'']]], + ['mcuxclhashmodes_5fmemoryconsumption_2eh',['mcuxClHashModes_MemoryConsumption.h',['../a00380.html',1,'']]], + ['mcuxclhashmodes_5fwoarkareaconsumption',['mcuxClHashModes_WoarkareaConsumption',['../a00776.html',1,'']]], + ['mcuxclhmac_20constants',['mcuxClHmac Constants',['../a00778.html',1,'']]], + ['mcuxclhmac_5fconstants_2eh',['mcuxClHmac_Constants.h',['../a00386.html',1,'']]], + ['mcuxclhmac_5fcreatehmacmode',['mcuxClHmac_createHmacMode',['../a00780.html#ga43f6d98b6b3b6a6e62263130e2c95a68',1,'mcuxClHmac_Functions.h']]], + ['mcuxclhmac_5fels_5finputbuffer_5flength',['MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH',['../a00778.html#gac9e4d270e79fa637dfac0c4919bf5eda',1,'mcuxClHmac_Constants.h']]], + ['mcuxclhmac_5fels_5fmin_5fpadding_5flength',['MCUXCLHMAC_ELS_MIN_PADDING_LENGTH',['../a00778.html#gaeea21ec876a193348d5f78b5014da165',1,'mcuxClHmac_Constants.h']]], + ['mcuxclhmac_20functions',['mcuxClHmac Functions',['../a00779.html',1,'']]], + ['mcuxclhmac_5ffunctions_2eh',['mcuxClHmac_Functions.h',['../a00389.html',1,'']]], + ['mcuxclhmac_5fkeytypes',['mcuxClHmac_KeyTypes',['../a00781.html',1,'']]], + ['mcuxclhmac_5fkeytypes_2eh',['mcuxClHmac_KeyTypes.h',['../a00392.html',1,'']]], + ['mcuxclhmac_5fmemoryconsumption',['mcuxClHmac_MemoryConsumption',['../a00782.html',1,'']]], + ['mcuxclhmac_5fmemoryconsumption_2eh',['mcuxClHmac_MemoryConsumption.h',['../a00395.html',1,'']]], + ['mcuxclhmac_5fmodedescriptor_5fsha2_5f256_5fels',['mcuxClHmac_ModeDescriptor_SHA2_256_ELS',['../a00398.html#a06144963f16c396f82dcab7f0a3bb0db',1,'mcuxClHmac_Modes.h']]], + ['mcuxclhmac_5fmodes_2eh',['mcuxClHmac_Modes.h',['../a00398.html',1,'']]], + ['mcuxclhmac_5fsize_5fin_5fcpuwords',['MCUXCLHMAC_SIZE_IN_CPUWORDS',['../a00782.html#ga7ebd777bda72a587fe816238ee14106c',1,'mcuxClHmac_MemoryConsumption.h']]], + ['mcuxclkey',['mcuxClKey',['../a00784.html',1,'']]], + ['mcuxclkey_2eh',['mcuxClKey.h',['../a00401.html',1,'']]], + ['mcuxclkey_5falgo_5fid_5faes',['MCUXCLKEY_ALGO_ID_AES',['../a00788.html#gaf342031191b667161f2db471ddbc1724',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5falgo_5fmask',['MCUXCLKEY_ALGO_ID_ALGO_MASK',['../a00788.html#gaf933f3469276e89b07aa395f90e2d180',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5feddsa',['MCUXCLKEY_ALGO_ID_ECC_EDDSA',['../a00788.html#gacbfa2e595e1fb1c6152cb4587ea01346',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5fmontdh',['MCUXCLKEY_ALGO_ID_ECC_MONTDH',['../a00788.html#gaace809498ccbffd63bc29f2b6d3a8db3',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5fshws_5fgf2m',['MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M',['../a00788.html#ga77f445482782348f049443d35a21662e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5fshws_5fgfp',['MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP',['../a00788.html#ga2270daa12f0592b07c5a657d3cc1ae87',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5fshws_5fgfp_5fephemeral_5fcustom',['MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM',['../a00788.html#gad51657624280512bd92719790363d763',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fecc_5fshws_5fgfp_5fstatic_5fcustom',['MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM',['../a00788.html#ga8de9456ab126f7227b1077462fbca3b4',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fhmac',['MCUXCLKEY_ALGO_ID_HMAC',['../a00788.html#gadb9ccdf41fc6a4868a0db982a601e226',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fkey_5fpair',['MCUXCLKEY_ALGO_ID_KEY_PAIR',['../a00788.html#ga73033441ba95ee2e3dd88a2d14f30bd5',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fprivate_5fkey',['MCUXCLKEY_ALGO_ID_PRIVATE_KEY',['../a00788.html#ga18dcc408cf88d59a8d55fcfd3efd3b75',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fprivate_5fkey_5fcrt',['MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT',['../a00788.html#gacc27c79457fc64101a84a110014f92e1',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fprivate_5fkey_5fcrt_5fdfa',['MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA',['../a00788.html#gabe8f17c80217f51dd7833e97ca169eee',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fpublic_5fkey',['MCUXCLKEY_ALGO_ID_PUBLIC_KEY',['../a00788.html#ga59fde148cf2683ed4371524df7ae3f06',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5frsa',['MCUXCLKEY_ALGO_ID_RSA',['../a00788.html#ga728c97658536b4430e2b0e2c7373f141',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fsm2',['MCUXCLKEY_ALGO_ID_SM2',['../a00788.html#gad4879e15a76d3c52e08855d993ba252e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fsm4',['MCUXCLKEY_ALGO_ID_SM4',['../a00788.html#ga8edc6b9dbe321d4e8a7f0681c4109111',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fsymmetric_5fkey',['MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY',['../a00788.html#gaa4fb66afe4c13047acc47ebf6d69e16e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgo_5fid_5fusage_5fmask',['MCUXCLKEY_ALGO_ID_USAGE_MASK',['../a00788.html#gadb73c82af33ca9b97d8465c36defdd6a',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5falgorithmid_5ft',['mcuxClKey_AlgorithmId_t',['../a00793.html#ga322cbacb57f10aa6cb6731d64d4e64e3',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fconstants_2eh',['mcuxClKey_Constants.h',['../a00404.html',1,'']]], + ['mcuxclkey_5fcustomtype_5ft',['mcuxClKey_CustomType_t',['../a00793.html#ga4249d6ccc1dab6d15b46270da3c3d6d4',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fdescriptor_5ft',['mcuxClKey_Descriptor_t',['../a00793.html#ga1b7557c7a8892e65d43b90f8d6226d6a',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fexample_2ec',['mcuxClKey_example.c',['../a00116.html',1,'']]], + ['mcuxclkey_5fflush',['mcuxClKey_flush',['../a00790.html#ga60a86766cba40477651948cfa55eb7cd',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5ffunctions',['mcuxClKey_Functions',['../a00790.html',1,'']]], + ['mcuxclkey_5ffunctions_2eh',['mcuxClKey_Functions.h',['../a00407.html',1,'']]], + ['mcuxclkey_5fgeneration_5ft',['mcuxClKey_Generation_t',['../a00793.html#gabb1e565ab474265cf8b53be6d9a1f758',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fgenerationdescriptor_5ft',['mcuxClKey_GenerationDescriptor_t',['../a00793.html#gaad2bc2272e961dd28dba4697d9287a14',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fhandle_5ft',['mcuxClKey_Handle_t',['../a00793.html#gafe84fa2aa66094f542164e0627a54c5d',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5finit',['mcuxClKey_init',['../a00790.html#ga8c6e891b1f7f973dbdccfe0f2a713142',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5finvalid_5fkeyslot',['MCUXCLKEY_INVALID_KEYSLOT',['../a00785.html#ga016a12d0d9ac976c44d4cf1f8a493763',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fkeysize',['mcuxClKey_KeySize',['../a00789.html',1,'']]], + ['mcuxclkey_5fkeytypes',['mcuxClKey_KeyTypes',['../a00788.html',1,'']]], + ['mcuxclkey_5flinkkeypair',['mcuxClKey_linkKeyPair',['../a00790.html#gadac5d6a29e1a0dba2b418b98e4ccd0ee',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5floadcopro',['mcuxClKey_loadCopro',['../a00790.html#ga616ead4a2aaab2d0ae5502ba52315fca',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5floadmemory',['mcuxClKey_loadMemory',['../a00790.html#gac4ec3d39748fc018dfb50316d2c51490',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5floadstatus_5f',['MCUXCLKEY_LOADSTATUS_',['../a00787.html',1,'']]], + ['mcuxclkey_5floadstatus_5fcopro',['MCUXCLKEY_LOADSTATUS_COPRO',['../a00787.html#ga3ab5a0669a60ff9b617bad0aeac71d72',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5floadstatus_5fkeeploaded',['MCUXCLKEY_LOADSTATUS_KEEPLOADED',['../a00787.html#gafd80ca5f40ff2e3898358c26cdd2caab',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5floadstatus_5fmemory',['MCUXCLKEY_LOADSTATUS_MEMORY',['../a00787.html#ga50a509b8aa4abb9219470b45a385c794',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5floadstatus_5fnotloaded',['MCUXCLKEY_LOADSTATUS_NOTLOADED',['../a00787.html#ga8ce719dd938dbdc0cf859fbb1e602a0e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fmacros',['mcuxClKey_Macros',['../a00785.html',1,'']]], + ['mcuxclkey_5fmemoryconsumption',['mcuxClKey_MemoryConsumption',['../a00791.html',1,'']]], + ['mcuxclkey_5fmemoryconsumption_2eh',['mcuxClKey_MemoryConsumption.h',['../a00410.html',1,'']]], + ['mcuxclkey_5fprotection_5fckdf',['mcuxClKey_Protection_Ckdf',['../a00792.html#ga46912713307ab64e4f20075064224838',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotection_5fnone',['mcuxClKey_Protection_None',['../a00792.html#gabf61ad39ecaba937f41b73721ce80b6a',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotection_5ft',['mcuxClKey_Protection_t',['../a00793.html#gab16fa58359f9994921f5d4a58c597c66',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fprotectiondescriptor_5fckdf',['mcuxClKey_ProtectionDescriptor_Ckdf',['../a00792.html#ga11724513bd08cb490212fa5d70c7c5b0',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotectiondescriptor_5fnone',['mcuxClKey_ProtectionDescriptor_None',['../a00792.html#gaa4fc9e15d78b127eaab9ec4c273d64b1',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotectiondescriptor_5ft',['mcuxClKey_ProtectionDescriptor_t',['../a00793.html#ga1c51acf51723d52dbcdc1a0f80f98572',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fsetkeyproperties',['mcuxClKey_setKeyproperties',['../a00790.html#gab1586a462e51711691901aa099f8b556',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5fsetprotection',['mcuxClKey_setProtection',['../a00790.html#ga761180099785b36b6d5a6014cae54bb8',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5fsize_5f1024',['MCUXCLKEY_SIZE_1024',['../a00789.html#gadd198add7df214eed81dbe316b150d3d',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f1024_5fin_5fwords',['MCUXCLKEY_SIZE_1024_IN_WORDS',['../a00789.html#ga0c357e26537083ca9164aab3820b4ca7',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f128',['MCUXCLKEY_SIZE_128',['../a00789.html#gab0cb72bbcdd5736790b183a6e49f8eb8',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f128_5fin_5fwords',['MCUXCLKEY_SIZE_128_IN_WORDS',['../a00789.html#ga46a4709b4a513ab6676ee24944d4d2f0',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f160',['MCUXCLKEY_SIZE_160',['../a00789.html#gac82b7eaeeb5f153630b71bbd59a7e515',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f160_5fin_5fwords',['MCUXCLKEY_SIZE_160_IN_WORDS',['../a00789.html#ga468b330bc005b81ccfe88e11171f391f',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f192',['MCUXCLKEY_SIZE_192',['../a00789.html#ga9871dfc831af8af21381f0f08007efe8',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f192_5fin_5fwords',['MCUXCLKEY_SIZE_192_IN_WORDS',['../a00789.html#gaeab881403cb2a9ade4906fda695a086e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f2048',['MCUXCLKEY_SIZE_2048',['../a00789.html#gacaf2b0cf43dc21e81e653d58be8320f6',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f2048_5fin_5fwords',['MCUXCLKEY_SIZE_2048_IN_WORDS',['../a00789.html#gae48b497b883fa63ef84465fcb4fb3ced',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f224',['MCUXCLKEY_SIZE_224',['../a00789.html#gaaeee050febe3515ef1369c27a77d8a79',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f224_5fin_5fwords',['MCUXCLKEY_SIZE_224_IN_WORDS',['../a00789.html#gaeb7c6bde09543bd3a45fc33c8e5beb3a',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f256',['MCUXCLKEY_SIZE_256',['../a00789.html#ga16f615ca2af0dcc6dad9930cbfc21b89',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f256_5fin_5fwords',['MCUXCLKEY_SIZE_256_IN_WORDS',['../a00789.html#ga6bea535c9b507d50ff14aa2dfb1ddf5b',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f3072',['MCUXCLKEY_SIZE_3072',['../a00789.html#gacdbba9c49cef3b7a47dc9570bdc72115',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f3072_5fin_5fwords',['MCUXCLKEY_SIZE_3072_IN_WORDS',['../a00789.html#gabbd3d5e04feb2c2f43a94d238cfca369',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f320',['MCUXCLKEY_SIZE_320',['../a00789.html#gad3a6f649d8e9b10a97bc0c04bc353718',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f320_5fin_5fwords',['MCUXCLKEY_SIZE_320_IN_WORDS',['../a00789.html#ga979dec395bea975d81634d14026159e4',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f384',['MCUXCLKEY_SIZE_384',['../a00789.html#ga0d300ed35264eccec76e71201613f065',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f384_5fin_5fwords',['MCUXCLKEY_SIZE_384_IN_WORDS',['../a00789.html#ga3ad1e0304140bdf547a93d45cbd7a5ff',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f4096',['MCUXCLKEY_SIZE_4096',['../a00789.html#ga44cf02ee5c2944fa72ec10c3be54642a',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f4096_5fin_5fwords',['MCUXCLKEY_SIZE_4096_IN_WORDS',['../a00789.html#gada1e24d3f9d8207287333085df1712dd',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f512',['MCUXCLKEY_SIZE_512',['../a00789.html#ga7dd4afbbc02c2612af98796af352b875',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f512_5fin_5fwords',['MCUXCLKEY_SIZE_512_IN_WORDS',['../a00789.html#gacfa3ec1113e89c824bc9d3aaad76d04e',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f521',['MCUXCLKEY_SIZE_521',['../a00789.html#ga704db03c84c8e46314089d8b052ba030',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f521_5fin_5fwords',['MCUXCLKEY_SIZE_521_IN_WORDS',['../a00789.html#gadaea316eb7a4a8b0b59e9f1879cae923',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f6144',['MCUXCLKEY_SIZE_6144',['../a00789.html#gaf8c45542e3fe919a3dddc532b44cecd2',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f6144_5fin_5fwords',['MCUXCLKEY_SIZE_6144_IN_WORDS',['../a00789.html#ga4de61cf46c4577ba0019f92814cbf804',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f8192',['MCUXCLKEY_SIZE_8192',['../a00789.html#gaaee55d800a45f767592c0071e5fca0d8',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5f8192_5fin_5fwords',['MCUXCLKEY_SIZE_8192_IN_WORDS',['../a00789.html#ga6c05f57184c5dd0da0cbb44ba28ce0f8',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5fnotused',['MCUXCLKEY_SIZE_NOTUSED',['../a00789.html#gaba60c5f0fa5e1bfb5299f1e6814c919f',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fsize_5ft',['mcuxClKey_Size_t',['../a00793.html#ga90c030f08081016123496c56021b9bab',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fstatus_5f',['MCUXCLKEY_STATUS_',['../a00786.html',1,'']]], + ['mcuxclkey_5fstatus_5fcrc_5fnot_5fok',['MCUXCLKEY_STATUS_CRC_NOT_OK',['../a00786.html#gaa1223f9f839075cd078103d4129b5218',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5ferror',['MCUXCLKEY_STATUS_ERROR',['../a00786.html#gaad298a05e6e023bc251b91ad5173ac59',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5ffailure',['MCUXCLKEY_STATUS_FAILURE',['../a00786.html#gabcc2c3ef67df555b363b5bb51f71d83b',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5ffault_5fattack',['MCUXCLKEY_STATUS_FAULT_ATTACK',['../a00786.html#ga7be083c8ca459a7290b5cf7784c75469',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5finvalid_5finput',['MCUXCLKEY_STATUS_INVALID_INPUT',['../a00786.html#gaf5c8b802949e1a7920cfdd65ec3fe42b',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5fnot_5fsupported',['MCUXCLKEY_STATUS_NOT_SUPPORTED',['../a00786.html#gacb7a3820f23f7cc17d33498ab12e3b3c',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5fok',['MCUXCLKEY_STATUS_OK',['../a00786.html#ga3cac3b08cb53d2949698e19319010c49',1,'mcuxClKey_Constants.h']]], + ['mcuxclkey_5fstatus_5fprotected_5ft',['mcuxClKey_Status_Protected_t',['../a00793.html#ga9886ee2d82f96093ad0a39385452cdfb',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fstatus_5ft',['mcuxClKey_Status_t',['../a00793.html#gaa19905c3963849a56ee26a9b0e5013f5',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5ftype_5faes128',['mcuxClKey_Type_Aes128',['../a00670.html#ga8f0a74b8ec63f9bcfff2723f37602d0d',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5faes192',['mcuxClKey_Type_Aes192',['../a00670.html#gaaeae50366310367805cb6ae6d81d88b1',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5faes256',['mcuxClKey_Type_Aes256',['../a00670.html#ga1249b014f089397821eceab3fd04ed5c',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5fecc_5fmontdh_5fcurve25519_5fkeypair',['mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair',['../a00682.html#gadcf4ca8f2a1626610da5b9bea5be3d89',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fecc_5fmontdh_5fcurve448_5fkeypair',['mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair',['../a00682.html#gae9116a45b5bfb237470625ae7d0fb29b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed25519_5fpriv',['mcuxClKey_Type_EdDSA_Ed25519_Priv',['../a00682.html#ga4f21b03709a5cac0b713f4e930102af8',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed25519_5fpub',['mcuxClKey_Type_EdDSA_Ed25519_Pub',['../a00682.html#gab1d91d013e28a086fd4e13175252c049',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed448_5fpriv',['mcuxClKey_Type_EdDSA_Ed448_Priv',['../a00682.html#ga5deb01671f213897a9d54c0e5b5b2ebe',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed448_5fpub',['mcuxClKey_Type_EdDSA_Ed448_Pub',['../a00682.html#gab35aa6e48e5bd8eda0a1b27c897f81a2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fhmac_5fvariablelength',['mcuxClKey_Type_Hmac_variableLength',['../a00781.html#ga42eb018ca876c87b3d4539532ab2154d',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftype_5fhmacsha256',['mcuxClKey_Type_HmacSha256',['../a00781.html#ga6d1ebb714b890c9b193a68edb3038720',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftype_5ft',['mcuxClKey_Type_t',['../a00793.html#ga9ea75aa8fe6ddb914d91b170bb5d8be5',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv',['../a00682.html#gadee38fd7f3c37112e45316828a1b421d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub',['../a00682.html#ga953ce0f67b3ba06382f7ca22eec53b3e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv',['../a00682.html#ga84b46e442f069d514c5061a03c4e9190',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub',['../a00682.html#ga8f69f4a645709620e99b354c8d28c57a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv',['../a00682.html#ga58315a40eb971b7d1ae90d906eb30319',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub',['../a00682.html#ga6f2fdb757ee68215625ffb9d32bab892',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv',['../a00682.html#ga9c3d2aedc7cdee77f194a281a79d1b38',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub',['../a00682.html#gaee8f56b3741cb2d385321184ecc3112a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv',['../a00682.html#ga67db10ea32d18c91b828214d9d38ac8b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub',['../a00682.html#ga78e896c33933303cacce198571f1d525',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv',['../a00682.html#ga6965a5067cf306af93fa18b0d7c40bf5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub',['../a00682.html#gaa70ef1ac082befbd2bcb06a1990cf8ca',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv',['../a00682.html#ga9de0651cd7e19b5a7d5b3e782a8cdb78',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub',['../a00682.html#ga37b4c94b2e841b2f3eb2331083b76f5f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv',['../a00682.html#ga5d0109f06ed0017ab64a625c290f84a0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub',['../a00682.html#ga5d9afd44cd025fbb0b3fc05c0b207597',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv',['../a00682.html#ga073b9c815509c8321bdeb396d8f377d5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub',['../a00682.html#ga91e507098e21780ba47f892d18197b26',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv',['../a00682.html#ga9fd102f8a9a37098e7fbaccd56ccb66c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub',['../a00682.html#ga660a4eedac67861ac691f8e6cce31a2e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv',['../a00682.html#ga8a996e206f32bd964d23537c41f27b25',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub',['../a00682.html#gade346aa31f4479a953d693d24be3005c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv',['../a00682.html#gaa83b67499981c694cc35d63173b908e5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub',['../a00682.html#ga9efe52ae3219c7c1401dcd2be13b5bd0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv',['../a00682.html#ga0973ccb9a10dba4e034096093ea24b22',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub',['../a00682.html#ga90516c497fc468872c20797ea042d7d6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv',['../a00682.html#ga6c0ef669e99f161073f329a5e08c7d10',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub',['../a00682.html#ga1346153805fc80794dcd54135e18ded9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp192_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P192_Priv',['../a00682.html#gab3bd456d3e79c18bb52852012a785a7c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp192_5fpub',['mcuxClKey_Type_WeierECC_NIST_P192_Pub',['../a00682.html#ga06b92e495eab87142fc07c469fac5526',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp224_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P224_Priv',['../a00682.html#ga8449862f98fdfc750c8990a06e561bc7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp224_5fpub',['mcuxClKey_Type_WeierECC_NIST_P224_Pub',['../a00682.html#ga0a61957ec8619856fe03204d56bd7a14',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp256_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P256_Priv',['../a00682.html#gacc7e8ff2ac5a8a3d894d7a9da0a80341',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp256_5fpub',['mcuxClKey_Type_WeierECC_NIST_P256_Pub',['../a00682.html#ga7f344daa7b996e30a163c9053f05ac5f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp384_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P384_Priv',['../a00682.html#ga690fd09dedd835e6d9e99e6de82f3ba0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp384_5fpub',['mcuxClKey_Type_WeierECC_NIST_P384_Pub',['../a00682.html#ga2ee917bf64caddab241b566099acf669',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp521_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P521_Priv',['../a00682.html#ga0b3881b7f5ef6077eaca0d37395a320e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp521_5fpub',['mcuxClKey_Type_WeierECC_NIST_P521_Pub',['../a00682.html#ga4fa543596682506a51f4078409dc3731',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp160k1_5fpriv',['mcuxClKey_Type_WeierECC_secp160k1_Priv',['../a00682.html#ga919b93483d11e303265fc8db41c4c03f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp160k1_5fpub',['mcuxClKey_Type_WeierECC_secp160k1_Pub',['../a00682.html#ga4345462d03a5a61641bfbbd3a2d5b86e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192k1_5fpriv',['mcuxClKey_Type_WeierECC_secp192k1_Priv',['../a00682.html#ga1bbeb45dc0f37b64ddf7d54890d1d5da',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192k1_5fpub',['mcuxClKey_Type_WeierECC_secp192k1_Pub',['../a00682.html#gaade00cdba0ae71d0ead7474186e8b9fa',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192r1_5fpriv',['mcuxClKey_Type_WeierECC_secp192r1_Priv',['../a00682.html#ga000d450d23f8c6980674668531ad4727',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192r1_5fpub',['mcuxClKey_Type_WeierECC_secp192r1_Pub',['../a00682.html#gaf003efa3e8861d0651ce6616abf5d919',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224k1_5fpriv',['mcuxClKey_Type_WeierECC_secp224k1_Priv',['../a00682.html#ga8754b1ec3ded884876adbb0145d1e054',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224k1_5fpub',['mcuxClKey_Type_WeierECC_secp224k1_Pub',['../a00682.html#ga75e6fbe876aa640a0fade7940ed23c3b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224r1_5fpriv',['mcuxClKey_Type_WeierECC_secp224r1_Priv',['../a00682.html#gabaef750bcfea399f7cf7e397d1b637e6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224r1_5fpub',['mcuxClKey_Type_WeierECC_secp224r1_Pub',['../a00682.html#ga3b602493fe22f22f91da3f6159ebe79c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256k1_5fpriv',['mcuxClKey_Type_WeierECC_secp256k1_Priv',['../a00682.html#ga9e922253404f7608e004929b2e994d7d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256k1_5fpub',['mcuxClKey_Type_WeierECC_secp256k1_Pub',['../a00682.html#ga41cecc27d7f37dfc1bca1158fa42af05',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256r1_5fpriv',['mcuxClKey_Type_WeierECC_secp256r1_Priv',['../a00682.html#gac945c22c4932453b64a0369e168aa05a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256r1_5fpub',['mcuxClKey_Type_WeierECC_secp256r1_Pub',['../a00682.html#gafc846d07facc686d0d6fcf7a46e7eb67',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp384r1_5fpriv',['mcuxClKey_Type_WeierECC_secp384r1_Priv',['../a00682.html#ga4456ec80ccaa45cf7a715719acb9195d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp384r1_5fpub',['mcuxClKey_Type_WeierECC_secp384r1_Pub',['../a00682.html#ga5e8db8f1f69ba0886f3a568e3eef3777',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp521r1_5fpriv',['mcuxClKey_Type_WeierECC_secp521r1_Priv',['../a00682.html#ga8898847c8409dd00985474ce2bfd9e7b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp521r1_5fpub',['mcuxClKey_Type_WeierECC_secp521r1_Pub',['../a00682.html#ga4922658a5dbdafb18e9a26aa62d047d9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5faes128',['mcuxClKey_TypeDescriptor_Aes128',['../a00670.html#ga8f7fce2b87e12c68354d223b9a75dc37',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5faes192',['mcuxClKey_TypeDescriptor_Aes192',['../a00670.html#ga16e79ab35a7a7da20948688481fe15ad',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5faes256',['mcuxClKey_TypeDescriptor_Aes256',['../a00670.html#ga5a8d0b88ec6b1da1730d861ca6fb7f97',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5fecc_5fmontdh_5fcurve25519_5fkeypair',['mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair',['../a00682.html#gadfd782e0581049bb1fe40049295807f6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fecc_5fmontdh_5fcurve448_5fkeypair',['mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair',['../a00682.html#ga033a43f0faf219f0e18ced032e1ad694',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed25519_5fpriv',['mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv',['../a00682.html#gab98021bcb61d1707d87106ddae87439c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed25519_5fpub',['mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub',['../a00682.html#ga3adea0c5fb26beb91e9d5cc798b167fd',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed448_5fpriv',['mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv',['../a00682.html#gab28b18fd50c1ec6bc4a05c56d1663046',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed448_5fpub',['mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub',['../a00682.html#gae06f9c4d573b51d538a42dfd2cbc4699',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fhmac_5fvariablelength',['mcuxClKey_TypeDescriptor_Hmac_variableLength',['../a00781.html#gae7b0c9b1b7b2c69b0d8c9ac6decdcf1f',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5fhmacsha256',['mcuxClKey_TypeDescriptor_HmacSha256',['../a00781.html#gaa7829411660f435c478e54884f9dc235',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5ft',['mcuxClKey_TypeDescriptor_t',['../a00793.html#gae9a4d21e5a5239fd0ef48978a3774a89',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv',['../a00682.html#gafee54bf1b90cab43955656fdf688e6b9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub',['../a00682.html#ga62389be1de20d8cf7dfdf9416766ce59',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv',['../a00682.html#ga3e834a29c37352e20f69567334a19ecb',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub',['../a00682.html#gabe551efbcc35efcba391ee767b7f7ff0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv',['../a00682.html#gaf7713f17a5c6504d79a4cc19a619d1bf',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub',['../a00682.html#ga55895a7c4d7dbde9cb53e27ce4aadc36',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv',['../a00682.html#gaec947c583361285beabd1515b85ffa05',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub',['../a00682.html#ga5a4502575819fa65e4afad99ce4c1d77',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv',['../a00682.html#ga2eefdf975f757f135792dedcc500c9f5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub',['../a00682.html#ga71ccfd1a0541def6aa05b24db3059b10',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv',['../a00682.html#ga8b497f39e491a6301f7e27edf74a1d94',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub',['../a00682.html#ga0532b3419b3886694736007f0b8e7944',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv',['../a00682.html#ga1c0248997a1ae57f004b96d063240fc7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub',['../a00682.html#ga81ed0e23c5cb230eaf68b43e2d037dde',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv',['../a00682.html#ga900bbb5cd092246e2bb83336df1af27e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub',['../a00682.html#ga649b579900b6ff23d3009026fa4a7a3a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv',['../a00682.html#ga3eb4a76b7cd7e5b04b69f1af7d430a24',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub',['../a00682.html#ga3578f443c84fa6e97c7fa21bd5765461',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv',['../a00682.html#ga055bfc9d1fa07fcd80911a4483ee8989',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub',['../a00682.html#ga45b70649d277b865e410beef5e815198',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv',['../a00682.html#ga4c70e1c0c3dec2ae4b89fd544987724b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub',['../a00682.html#ga72edef6223f86b15d63f282c0a9119bc',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv',['../a00682.html#gab5dc15b01d9c0d9dbf847026af187802',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub',['../a00682.html#ga7cd3157e70c933ce8f646c6277d832b6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv',['../a00682.html#gac15a4416fa5fa537f67a456e68b9e81a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub',['../a00682.html#gace90d3010bf72d3289a1f5ab249c07a2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv',['../a00682.html#ga980f0af6070d632d144d38c34ca26d0e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub',['../a00682.html#gaa585fea86a1de6d3eee179053ff71396',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp192_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv',['../a00682.html#gaf0d412d5ea6506c4afa947ef3d17646c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp192_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub',['../a00682.html#ga697b811095baa95d968a6710b78dda40',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp224_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv',['../a00682.html#gaf049264c890164b02d97139deb8c1471',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp224_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub',['../a00682.html#ga40820475ba5218c1746f3de54035367f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp256_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv',['../a00682.html#gab13c07ea082e362aefed4814123ff724',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp256_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub',['../a00682.html#ga66bb90651426a91d158794a3c79df29f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp384_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv',['../a00682.html#ga5177e841e9f5754aded42239c95b4263',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp384_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub',['../a00682.html#gadad85b76aaf6f7c99a0264392a31a5a1',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp521_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv',['../a00682.html#gac4ff88aeb6544eee998bbe565e870856',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fnist_5fp521_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub',['../a00682.html#ga34397e23e613e3662aabe96baeb7dd99',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp160k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv',['../a00682.html#ga5be9d578c7e89fb9ddeb24ce1dd87705',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp160k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub',['../a00682.html#ga45f80b52c3713407e5ea8d874fcab224',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv',['../a00682.html#ga4464ec90b697f37d0c77f371ffd25f73',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub',['../a00682.html#gae82b0b8a866aa021d9be12d673ea44cb',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv',['../a00682.html#ga9696729f938dcffb197bb7ec7cf68ab7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub',['../a00682.html#gad6f5289ef5ca2a8675ab7086b35522df',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv',['../a00682.html#gaacbea5c086db4ecfa1e481d64e64c034',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub',['../a00682.html#ga72e156ee2a9ac1c0808fb54be1c37854',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv',['../a00682.html#ga9d9727c76f81c36e06c5202eced2d73b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub',['../a00682.html#ga243160a6bd14bfcfae0feab8cfec4444',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv',['../a00682.html#ga39040d5c10a5245ba45acb94304704f5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub',['../a00682.html#gafb9d141d04c292a77577c8593f379dae',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv',['../a00682.html#gaddbf6d8826069565a1e79fb24d8cb3b2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub',['../a00682.html#ga82bfa972e94322b417a5ddf43932a2ec',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp384r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv',['../a00682.html#gac745b76bab619fff5fe1146fb7d71a50',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp384r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub',['../a00682.html#ga21b1d68989a19b915dd5106075e29cb3',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp521r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv',['../a00682.html#ga06483f379dc8873d7cc30c300610e327',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp521r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub',['../a00682.html#ga6269f061cab69e82df4cd7b9656c8a2c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypes',['mcuxClKey_Types',['../a00793.html',1,'']]], + ['mcuxclkey_5ftypes_2eh',['mcuxClKey_Types.h',['../a00416.html',1,'']]], + ['mcuxclkey_5fwa_5fsize_5fmax',['MCUXCLKEY_WA_SIZE_MAX',['../a00785.html#ga617470bb5f7da932c271545154fe31b7',1,'mcuxClKey_Constants.h']]], + ['mcuxclmac',['mcuxClMac',['../a00794.html',1,'']]], + ['mcuxclmac_2eh',['mcuxClMac.h',['../a00419.html',1,'']]], + ['mcuxclmac_5fcbcmac_5foutput_5fsize',['MCUXCLMAC_CBCMAC_OUTPUT_SIZE',['../a00800.html#gae3fbb2da7d5fef73ea388eb30cb0e8a4',1,'mcuxClMacModes_Constants.h']]], + ['mcuxclmac_5fcbcmac_5foutput_5fsize_5fin_5fwords',['MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS',['../a00800.html#ga071c1074dbc84e227e6bb7de4355d9e4',1,'mcuxClMacModes_Constants.h']]], + ['mcuxclmac_5fcmac_5foutput_5fsize',['MCUXCLMAC_CMAC_OUTPUT_SIZE',['../a00800.html#ga19fabc0fcc4bb740d3ae3f5af0801932',1,'mcuxClMacModes_Constants.h']]], + ['mcuxclmac_5fcmac_5foutput_5fsize_5fin_5fwords',['MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS',['../a00800.html#ga6c92dadeb46681334a49ccd369639ca3',1,'mcuxClMacModes_Constants.h']]], + ['mcuxclmac_5fcompute',['mcuxClMac_compute',['../a00797.html#gad2fe8b5e17f2b468fbe8a61f8fee5400',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5fconstants',['mcuxClMac_Constants',['../a00795.html',1,'']]], + ['mcuxclmac_5fconstants_2eh',['mcuxClMac_Constants.h',['../a00422.html',1,'']]], + ['mcuxclmac_5fcontext_5ft',['mcuxClMac_Context_t',['../a00799.html#gaf804dbff6e0d68d2d877b21995ed5c34',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fcustommode_5ft',['mcuxClMac_CustomMode_t',['../a00799.html#ga55e9279a13efd1dd87affcc88f3eb34a',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ffinish',['mcuxClMac_finish',['../a00798.html#ga9d66c6e242ff75b6ff4826fdcb784e08',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_20functions',['mcuxClMac Functions',['../a00796.html',1,'']]], + ['mcuxclmac_5ffunctions_2eh',['mcuxClMac_Functions.h',['../a00425.html',1,'']]], + ['mcuxclmac_5finit',['mcuxClMac_init',['../a00798.html#ga803bd7822372bdca8dfd0c81b5db96eb',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fnopadding',['mcuxClMac_Mode_CBCMAC_NoPadding',['../a00804.html#ga0edfb9edb1c66eba797754851e463a20',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fpaddingiso9797_5f1_5fmethod1',['mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1',['../a00804.html#ga39e525bf4e237be5933966afa1eafd02',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fpaddingiso9797_5f1_5fmethod2',['mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2',['../a00804.html#ga6727ecd0ad3c728bb1ba822f7fd6f485',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcmac',['mcuxClMac_Mode_CMAC',['../a00804.html#gab5f61e17bb7b7d97f69745700f107bc6',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fhmac_5fsha2_5f256_5fels',['mcuxClMac_Mode_HMAC_SHA2_256_ELS',['../a00398.html#ad6bd4a8254a45bfc3f319c4177fd8d80',1,'mcuxClHmac_Modes.h']]], + ['mcuxclmac_5fmode_5ft',['mcuxClMac_Mode_t',['../a00799.html#ga8e9aa3b88af43aaf819650568abc471f',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fnopadding',['mcuxClMac_ModeDescriptor_CBCMAC_NoPadding',['../a00804.html#gab8171ca5a2cad3f74f26cade42abb4fa',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fpaddingiso9797_5f1_5fmethod1',['mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1',['../a00804.html#gacf3978d54625d231254d9b42bcbf349c',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fpaddingiso9797_5f1_5fmethod2',['mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2',['../a00804.html#gaacbabbb60934ae05725b5cb2889c7bce',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcmac',['mcuxClMac_ModeDescriptor_CMAC',['../a00804.html#ga7df28da412f427562a5ffcb2b3ab8c35',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5ft',['mcuxClMac_ModeDescriptor_t',['../a00799.html#gaad5e6326d43f28d324ef2d98ac3ad2cc',1,'mcuxClMac_Types.h']]], + ['multi_20part_20mac_20interfaces',['Multi part MAC interfaces',['../a00798.html',1,'']]], + ['mcuxclmac_5fprocess',['mcuxClMac_process',['../a00798.html#ga2749e40209d4308f21ebe761485d4d56',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5fstatus_5ft',['mcuxClMac_Status_t',['../a00799.html#gaca63aa917056a18f99a911f329f3971b',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ftest_5ft',['mcuxClMac_Test_t',['../a00799.html#ga0af47561198575f7792301a2a5135e75',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ftestdescriptor_5ft',['mcuxClMac_TestDescriptor_t',['../a00799.html#ga05358be86e9c9b69f46225171d63f406',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ftypes',['mcuxClMac_Types',['../a00799.html',1,'']]], + ['mcuxclmac_5ftypes_2eh',['mcuxClMac_Types.h',['../a00428.html',1,'']]], + ['mac_20modes_20api',['MAC Modes API',['../a00962.html',1,'']]], + ['mcuxclmacmodes_5fcmac_5foneshot_5fexample_2ec',['mcuxClMacModes_cmac_oneshot_example.c',['../a00119.html',1,'']]], + ['mcuxclmacmodes_20constants',['mcuxClMacModes Constants',['../a00800.html',1,'']]], + ['mcuxclmacmodes_5fconstants_2eh',['mcuxClMacModes_Constants.h',['../a00434.html',1,'']]], + ['mcuxclmacmodes_20functions',['mcuxClMacModes Functions',['../a00801.html',1,'']]], + ['mcuxclmacmodes_5ffunctions_2eh',['mcuxClMacModes_Functions.h',['../a00437.html',1,'']]], + ['mcuxclmacmodes_5fmemoryconsumption',['mcuxClMacModes_MemoryConsumption',['../a00803.html',1,'']]], + ['mcuxclmacmodes_5fmemoryconsumption_2eh',['mcuxClMacModes_MemoryConsumption.h',['../a00440.html',1,'']]], + ['mac_20mode_20definitions',['MAC mode definitions',['../a00804.html',1,'']]], + ['mcuxclmath',['mcuxClMath',['../a00805.html',1,'']]], + ['mcuxclmath_2eh',['mcuxClMath.h',['../a00446.html',1,'']]], + ['mcuxclmath_5ferrorcode_5ferror',['MCUXCLMATH_ERRORCODE_ERROR',['../a00807.html#ga1427ab8cd82a164dee226ae554894772',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5ferrorcode_5fok',['MCUXCLMATH_ERRORCODE_OK',['../a00807.html#gacc4f37c95272b523a0ca1eca8d2e3735',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fexactdivide',['mcuxClMath_ExactDivide',['../a00806.html#ga9416369d37627425ecac95580d1c3ee4',1,'mcuxClMath_ExactDivide(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength): mcuxClMath_Functions.h'],['../a00806.html#gae99e5e55dda4387e4384e974a112a760',1,'MCUXCLMATH_EXACTDIVIDE(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fexactdivideodd',['mcuxClMath_ExactDivideOdd',['../a00806.html#ga7aa33c63d602fdb151d3e342284b2171',1,'mcuxClMath_ExactDivideOdd(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength): mcuxClMath_Functions.h'],['../a00806.html#gae807c4ed789f67aa150addbae31de180',1,'MCUXCLMATH_EXACTDIVIDEODD(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fexactdivide',['MCUXCLMATH_FP_EXACTDIVIDE',['../a00806.html#ga4dd21ea08b92f104bd3d9bff5ce7efe7',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fexactdivideodd',['MCUXCLMATH_FP_EXACTDIVIDEODD',['../a00806.html#gaf1d62616daa224745d2ed40fdfa4d724',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fmodexp_5fsqrmultl2r',['MCUXCLMATH_FP_MODEXP_SQRMULTL2R',['../a00806.html#ga9f0c8d67f0c192341fbf9ac436f02173',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fmodinv',['MCUXCLMATH_FP_MODINV',['../a00806.html#gab456571414ef2f49a91b61f0c91009ba',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fndash',['MCUXCLMATH_FP_NDASH',['../a00806.html#gafa0d390f4eb5728edfd764936aeee313',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fqdash',['MCUXCLMATH_FP_QDASH',['../a00806.html#ga7703703d552c5446acdf38d82cd81971',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fqsquared',['MCUXCLMATH_FP_QSQUARED',['../a00806.html#gadcd348426e9998703dc6f93194a62f80',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5freducemodeven',['MCUXCLMATH_FP_REDUCEMODEVEN',['../a00806.html#gaed2b24ff10b916eb07a842a2a05ad341',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffp_5fshiftmodulus',['MCUXCLMATH_FP_SHIFTMODULUS',['../a00806.html#ga35df7cdad4c81c5e276f373c70c571d0',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ffunctions',['mcuxClMath_Functions',['../a00806.html',1,'']]], + ['mcuxclmath_5ffunctions_2eh',['mcuxClMath_Functions.h',['../a00449.html',1,'']]], + ['mcuxclmath_5finitlocaluptrt',['mcuxClMath_InitLocalUptrt',['../a00806.html#ga716b9990024e2ea5e5984ca960a5e861',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fleadingzeros',['mcuxClMath_LeadingZeros',['../a00806.html#ga91e4885b266c16938e04aa036eae6977',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fmacros',['mcuxClMath_Macros',['../a00807.html',1,'']]], + ['mcuxclmath_5fmodexp_5fsqrmultl2r',['mcuxClMath_ModExp_SqrMultL2R',['../a00806.html#gabdd7a91f84faca1e208c143a25e318f8',1,'mcuxClMath_ModExp_SqrMultL2R(const uint8_t *pExp, uint32_t expByteLength, uint32_t iR_iX_iN_iT): mcuxClMath_Functions.h'],['../a00806.html#ga82842f4b45c0d86e4c2d6d29e23c259b',1,'MCUXCLMATH_MODEXP_SQRMULTL2R(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fmodinv',['MCUXCLMATH_MODINV',['../a00806.html#gaa59866fd485a59868a2a594a5858f1de',1,'MCUXCLMATH_MODINV(): mcuxClMath_Functions.h'],['../a00806.html#ga9c01f0090ea0220a735ea6992515cf7a',1,'mcuxClMath_ModInv(uint32_t iR_iX_iN_iT): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fndash',['mcuxClMath_NDash',['../a00806.html#ga47ca58caa097e65c0925aa488f287a1e',1,'mcuxClMath_NDash(uint16_t iN_iT): mcuxClMath_Functions.h'],['../a00806.html#gab588855e23f750a4c9f7533b54a11325',1,'MCUXCLMATH_NDASH(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fqdash',['MCUXCLMATH_QDASH',['../a00806.html#ga666d3347d6f96a09b791355e596de46d',1,'MCUXCLMATH_QDASH(): mcuxClMath_Functions.h'],['../a00806.html#ga61ef022af097c89154560df0f81b3caa',1,'mcuxClMath_QDash(uint32_t iQDash_iNShifted_iN_iT, uint16_t length): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fqsquared',['MCUXCLMATH_QSQUARED',['../a00806.html#ga4ee6d9b078ecc35a081a3a8cdbec0968',1,'MCUXCLMATH_QSQUARED(): mcuxClMath_Functions.h'],['../a00806.html#gae2ad68ea7641a23751583c27ed1d77a7',1,'mcuxClMath_QSquared(uint32_t iQSqr_iNShifted_iN_iT): mcuxClMath_Functions.h']]], + ['mcuxclmath_5freducemodeven',['mcuxClMath_ReduceModEven',['../a00806.html#gadcf87738f49ecf4c39ee725fa6cb88f9',1,'mcuxClMath_ReduceModEven(uint32_t iR_iX_iN_iT0, uint32_t iT1_iT2_iT3): mcuxClMath_Functions.h'],['../a00806.html#ga3ee39987ba7de0e36abc848d77b4eaa3',1,'MCUXCLMATH_REDUCEMODEVEN(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fsecmodexp',['mcuxClMath_SecModExp',['../a00806.html#ga5f0ebd971dee31e271c27ae02479ff55',1,'mcuxClMath_SecModExp(mcuxClSession_Handle_t session, const uint8_t *pExp, uint32_t *pExpTemp, uint32_t expByteLength, uint32_t iT3_iX_iT2_iT1, uint32_t iN_iTE_iT0_iR, uint32_t secOption): mcuxClMath_Functions.h'],['../a00806.html#ga3e0168ff93f7bffd7d56ce509ba29c59',1,'MCUXCLMATH_SECMODEXP(): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fsecmodexp_5foption_5fdis_5frerand',['MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND',['../a00807.html#ga81bd9ab98d67ca3c7e944ad922d1d353',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fsecmodexp_5fwithout_5frerandomization',['MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION',['../a00806.html#ga32eaa55458996d636a82ac9bda34e3e0',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fshiftmodulus',['MCUXCLMATH_SHIFTMODULUS',['../a00806.html#gaadd4485b0f1db32b6da6e6b7a2e6cc11',1,'MCUXCLMATH_SHIFTMODULUS(): mcuxClMath_Functions.h'],['../a00806.html#ga65003277bfc2c6eb64be0f23261cadd7',1,'mcuxClMath_ShiftModulus(uint16_t iNShifted_iN): mcuxClMath_Functions.h']]], + ['mcuxclmath_5fstatus_5ferror',['MCUXCLMATH_STATUS_ERROR',['../a00807.html#ga6e43ca61303440dc7e9a83fbe9cce4d3',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fstatus_5fok',['MCUXCLMATH_STATUS_OK',['../a00807.html#ga745dd2a8966d1760f3475089b2f7aa47',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fstatus_5fprotected_5ft',['mcuxClMath_Status_Protected_t',['../a00807.html#ga0560097c958abffba7b41198a7af6c8b',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fstatus_5ft',['mcuxClMath_Status_t',['../a00807.html#gaf541274a57cf9f823c029f73ff733ae0',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5ftrailingzeros',['mcuxClMath_TrailingZeros',['../a00806.html#ga0203db0be2a5c09157c0db697cc2685f',1,'mcuxClMath_Functions.h']]], + ['mcuxclmemory',['mcuxClMemory',['../a00808.html',1,'']]], + ['mcuxclmemory_2eh',['mcuxClMemory.h',['../a00455.html',1,'']]], + ['mcuxclmemory_5fapi',['MCUXCLMEMORY_API',['../a00815.html#ga2469abde1e59b6b478ba8c393dc3e95a',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5fclear',['mcuxClMemory_clear',['../a00809.html#ga1ac6e8a4335f620d41360c090ee5ce73',1,'mcuxClMemory_clear(uint8_t *pDst, size_t length, size_t bufLength): mcuxClMemory_Clear.h'],['../a00809.html',1,'(Global Namespace)']]], + ['mcuxclmemory_5fclear_2eh',['mcuxClMemory_Clear.h',['../a00458.html',1,'']]], + ['mcuxclmemory_5fcopy',['mcuxClMemory_copy',['../a00810.html#gab564183ab5f02cf11b66b6244ba2112a',1,'mcuxClMemory_copy(uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength): mcuxClMemory_Copy.h'],['../a00810.html',1,'(Global Namespace)']]], + ['mcuxclmemory_5fcopy_2eh',['mcuxClMemory_Copy.h',['../a00461.html',1,'']]], + ['mcuxclmemory_5fcopy_5freversed',['mcuxClMemory_copy_reversed',['../a00811.html#gafc918d181009c3af7638604e5e4b9281',1,'mcuxClMemory_copy_reversed(uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength): mcuxClMemory_Copy_Reversed.h'],['../a00811.html',1,'(Global Namespace)']]], + ['mcuxclmemory_5fcopy_5freversed_2eh',['mcuxClMemory_Copy_Reversed.h',['../a00464.html',1,'']]], + ['mcuxclmemory_5fendianness',['mcuxClMemory_Endianness',['../a00812.html',1,'']]], + ['mcuxclmemory_5fendianness_2eh',['mcuxClMemory_Endianness.h',['../a00467.html',1,'']]], + ['mcuxclmemory_5ferrorcode_5fok',['MCUXCLMEMORY_ERRORCODE_OK',['../a00815.html#ga0e92b528eed7533fedddfc3172c60fa8',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fclear',['MCUXCLMEMORY_FP_MEMORY_CLEAR',['../a00809.html#ga2dc0fdbb602c3777fffb8515f944d736',1,'mcuxClMemory_Clear.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fclear_5fwith_5fbuff',['MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF',['../a00809.html#ga76dcce466859684502b4725d51d5de4f',1,'mcuxClMemory_Clear.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fcopy',['MCUXCLMEMORY_FP_MEMORY_COPY',['../a00810.html#ga5d16560ac24ef6ba2dae129206e70208',1,'mcuxClMemory_Copy.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fcopy_5freversed',['MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED',['../a00811.html#ga34f4a48eda22ae64759db5d7893d0c36',1,'mcuxClMemory_Copy_Reversed.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fcopy_5fwith_5fbuff',['MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF',['../a00810.html#gaab249829be1231ec5f08f90093943a40',1,'mcuxClMemory_Copy.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fset',['MCUXCLMEMORY_FP_MEMORY_SET',['../a00813.html#ga039e0b482faab4d1aabe2dd5c79d3eb5',1,'mcuxClMemory_Set.h']]], + ['mcuxclmemory_5ffp_5fmemory_5fset_5fwith_5fbuff',['MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF',['../a00813.html#gad65a5023a0b0263462b6cfcd6761b904',1,'mcuxClMemory_Set.h']]], + ['mcuxclmemory_5floadbigendian32',['mcuxClMemory_LoadBigEndian32',['../a00812.html#gabd3fd1c7ee32c2cd202a67bce5036778',1,'mcuxClMemory_Endianness.h']]], + ['mcuxclmemory_5floadlittleendian32',['mcuxClMemory_LoadLittleEndian32',['../a00812.html#gaa3eba98f422623a6a02f15898449c874',1,'mcuxClMemory_Endianness.h']]], + ['mcuxclmemory_5fset',['mcuxClMemory_set',['../a00813.html#ga5d86af41c30044c28809914e2901884d',1,'mcuxClMemory_set(uint8_t *pDst, uint8_t val, size_t length, size_t bufLength): mcuxClMemory_Set.h'],['../a00813.html',1,'(Global Namespace)']]], + ['mcuxclmemory_5fset_2eh',['mcuxClMemory_Set.h',['../a00470.html',1,'']]], + ['mcuxclmemory_5fstatus_5f',['MCUXCLMEMORY_STATUS_',['../a00816.html',1,'']]], + ['mcuxclmemory_5fstatus_5fok',['MCUXCLMEMORY_STATUS_OK',['../a00816.html#ga0a6eff5e1bb27d6c237a16f7d60b9eb9',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5fstatus_5fprotected_5ft',['mcuxClMemory_Status_Protected_t',['../a00814.html#ga57c9ba76c62b4ad9bd565df4a98c19ba',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5fstatus_5ft',['mcuxClMemory_Status_t',['../a00814.html#gad25887c99517f13c547e1d2bf027ccd1',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5fstorebigendian32',['mcuxClMemory_StoreBigEndian32',['../a00812.html#ga84f8097975ebea39deaea4ab9306d2ce',1,'mcuxClMemory_Endianness.h']]], + ['mcuxclmemory_5fstorelittleendian32',['mcuxClMemory_StoreLittleEndian32',['../a00812.html#gaef4886d199c2539b209458a8c62378cd',1,'mcuxClMemory_Endianness.h']]], + ['mcuxclmemory_5fswitch_5f4byte_5fendianness',['MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS',['../a00812.html#gac426a079f1808ff0183d2851ead720c5',1,'mcuxClMemory_Endianness.h']]], + ['mcuxclmemory_5ftypes',['mcuxClMemory_Types',['../a00814.html',1,'']]], + ['mcuxclmemory_5ftypes_2eh',['mcuxClMemory_Types.h',['../a00473.html',1,'']]], + ['mcuxclmemory_5ftypes_5fmacros',['mcuxClMemory_Types_Macros',['../a00815.html',1,'']]], + ['mcuxcloscca_5ffunctionidentifiers_2eh',['mcuxClOscca_FunctionIdentifiers.h',['../a00476.html',1,'']]], + ['mcuxcloscca_5fmemory_2eh',['mcuxClOscca_Memory.h',['../a00479.html',1,'']]], + ['mcuxcloscca_5fmpint_5ft',['mcuxClOscca_MPInt_t',['../a01253.html',1,'mcuxClOscca_MPInt_t'],['../a00485.html#a167ac5bec44e63a398cce013bd85476f',1,'mcuxClOscca_MPInt_t(): mcuxClOscca_Types.h']]], + ['mcuxcloscca_5fplatformtypes_2eh',['mcuxClOscca_PlatformTypes.h',['../a00482.html',1,'']]], + ['mcuxcloscca_5frng_5fctx_5ft',['mcuxClOscca_Rng_Ctx_t',['../a00485.html#ab3464aacd01247830fe9a57570620d23',1,'mcuxClOscca_Types.h']]], + ['mcuxcloscca_5fscratchpad_5ft',['mcuxClOscca_ScratchPad_t',['../a01249.html',1,'']]], + ['mcuxcloscca_5ftypes_2eh',['mcuxClOscca_Types.h',['../a00485.html',1,'']]], + ['mcuxclosccapkc',['mcuxClOsccaPkc',['../a00817.html',1,'']]], + ['mcuxclosccapkc_2eh',['mcuxClOsccaPkc.h',['../a00488.html',1,'']]], + ['mcuxclosccapkc_5ffunctions',['mcuxClOsccaPkc_Functions',['../a00818.html',1,'']]], + ['mcuxclosccapkc_5ffunctions_2eh',['mcuxClOsccaPkc_Functions.h',['../a00491.html',1,'']]], + ['mcuxclosccapkc_5fpkcpackargs2',['MCUXCLOSCCAPKC_PKCPACKARGS2',['../a00494.html#aba1b2e7258d3f4a2080b728cc7f91eaf',1,'mcuxClOsccaPkc_Types.h']]], + ['mcuxclosccapkc_5fptrfupentry_5ft',['mcuxClOsccaPkc_PtrFUPEntry_t',['../a00818.html#gae42a19bfc4e7aaa16fdea5ef1e6bc6c4',1,'mcuxClOsccaPkc_Functions.h']]], + ['mcuxclosccapkc_5fstate_5ft',['mcuxClOsccaPkc_State_t',['../a01257.html',1,'mcuxClOsccaPkc_State_t'],['../a00818.html#ga83f8544bc01ae0f871addbfe5600e706',1,'mcuxClOsccaPkc_State_t(): mcuxClOsccaPkc_Functions.h']]], + ['mcuxclosccapkc_5ftypes_2eh',['mcuxClOsccaPkc_Types.h',['../a00494.html',1,'']]], + ['mcuxclosccasm3',['mcuxClOsccaSm3',['../a00819.html',1,'']]], + ['mcuxclosccasm3_2eh',['mcuxClOsccaSm3.h',['../a00497.html',1,'']]], + ['mcuxclosccasm3_5falgorithms_2eh',['mcuxClOsccaSm3_Algorithms.h',['../a00500.html',1,'']]], + ['mcuxclosccasm3_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX',['../a00822.html#gaac9381a82113d329dd25ab934c95dfd5',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fsm3',['MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3',['../a00822.html#ga69194394354130bb74c3a659c6a6382a',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fconstants_2eh',['mcuxClOsccaSm3_Constants.h',['../a00503.html',1,'']]], + ['mcuxclosccasm3_5fcontext',['MCUXCLOSCCASM3_CONTEXT',['../a00823.html',1,'']]], + ['mcuxclosccasm3_5fcontext_5fsize_5fin_5fwords',['MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS',['../a00823.html#ga60a96727f7daf1d9762c0c54544e0ca8',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fexport_5fimport_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE',['../a00823.html#ga55b2857bb7c8aec7fb22e3ebab7ebf77',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX',['../a00822.html#ga53ef6d92e75dc64d5cdf0bf5cf9c4231',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fsm3',['MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3',['../a00822.html#gac8ba7076a5518d52ce295d48099d4ae3',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5finit_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE',['../a00822.html#gab8638606efbce3f6c35b1584e2edf157',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fmax_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE',['../a00822.html#ga92c12b7d0bcd8ebcaf3ffa9bcac45b6b',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fmemoryconsumption_2eh',['mcuxClOsccaSm3_MemoryConsumption.h',['../a00506.html',1,'']]], + ['mcuxclosccasm3_5fmodes',['mcuxClOsccaSm3_Modes',['../a00820.html',1,'']]], + ['mcuxclosccasm3_5foutput_5fsize_5f',['MCUXCLOSCCASM3_OUTPUT_SIZE_',['../a00821.html',1,'']]], + ['mcuxclosccasm3_5foutput_5fsize_5fsm3',['MCUXCLOSCCASM3_OUTPUT_SIZE_SM3',['../a00821.html#ga12a91530ea05a544a80b18d4f436d51f',1,'mcuxClOsccaSm3_Constants.h']]], + ['mcuxclosccasm3_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX',['../a00822.html#ga7fc2a9c206d05b1b56fdb4a50964e8aa',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fsm3',['MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3',['../a00822.html#ga44f1d4fbc45ff4047678df48c2673868',1,'mcuxClOsccaSm3_MemoryConsumption.h']]], + ['mcuxclosccasm3_5fwa',['MCUXCLOSCCASM3_WA',['../a00822.html',1,'']]], + ['mcuxclpadding_2eh',['mcuxClPadding.h',['../a00509.html',1,'']]], + ['mcuxclpadding_5fconstants_2eh',['mcuxClPadding_Constants.h',['../a00512.html',1,'']]], + ['mcuxclpadding_5fstatus_5ferror',['MCUXCLPADDING_STATUS_ERROR',['../a00824.html#ga27d0fc33860c93a2241e1d6b37a92d94',1,'mcuxClPadding_Constants.h']]], + ['mcuxclpadding_5fstatus_5ffault_5fattack',['MCUXCLPADDING_STATUS_FAULT_ATTACK',['../a00824.html#ga4dff5913bd142d42c0a8825ce553bc3c',1,'mcuxClPadding_Constants.h']]], + ['mcuxclpadding_5fstatus_5fnot_5fok',['MCUXCLPADDING_STATUS_NOT_OK',['../a00824.html#ga6393900f48c3b32dd379a6ea30bc730a',1,'mcuxClPadding_Constants.h']]], + ['mcuxclpadding_5fstatus_5fok',['MCUXCLPADDING_STATUS_OK',['../a00824.html#gad64734c94edeab85fc1d8e05c4134f52',1,'mcuxClPadding_Constants.h']]], + ['mcuxclpadding_5fstatus_5ft',['mcuxClPadding_Status_t',['../a00825.html#ga965eb15986e53917365f3f3b769e0968',1,'mcuxClPadding_Types.h']]], + ['mcuxclpadding_5ftypes_2eh',['mcuxClPadding_Types.h',['../a00515.html',1,'']]], + ['mcuxclpkc',['mcuxClPkc',['../a00826.html',1,'']]], + ['mcuxclpkc_2eh',['mcuxClPkc.h',['../a00518.html',1,'']]], + ['mcuxclpkc_5fcalc',['mcuxClPkc_Calc',['../a00965.html#ga1fe435f5e72d9347692a7ac8fa2ba67f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fcalcconst',['mcuxClPkc_CalcConst',['../a00965.html#ga2d214326104dc2ced79098286852ae03',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fcalcfup',['mcuxClPkc_CalcFup',['../a00965.html#gaec0a3e70eb593b9bd49edf9e7aba298e',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fdeinitialize',['mcuxClPkc_Deinitialize',['../a00963.html#ga0d09260a20ca358d02264f16a74369c1',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fcalcfup',['MCUXCLPKC_FP_CALCFUP',['../a00965.html#ga75385d0295607d89d375f6b8706f4299',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fcalcfup_5foffset',['MCUXCLPKC_FP_CALCFUP_OFFSET',['../a00965.html#gac16f7fd691d8868968cc643feed97846',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fdeinitialize',['MCUXCLPKC_FP_DEINITIALIZE',['../a00963.html#gaf47041e2fee71acba1d37b89f7825e02',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fgenerateuptrt',['MCUXCLPKC_FP_GENERATEUPTRT',['../a00964.html#ga26921e5d9a66bd8247a277794b04b42c',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5finitialize',['MCUXCLPKC_FP_INITIALIZE',['../a00963.html#ga3a95e35addbaf26fa41f8e9cf27950f6',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fwaitforfinish',['MCUXCLPKC_FP_WAITFORFINISH',['../a00966.html#gac1f65eb00620f5683ffd7965a084a977',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffp_5fwaitforready',['MCUXCLPKC_FP_WAITFORREADY',['../a00966.html#ga1733f3b346a3bd00ffdd8b3f7df0c3fc',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5ffunctions',['mcuxClPkc_Functions',['../a00827.html',1,'']]], + ['mcuxclpkc_5ffunctions_2eh',['mcuxClPkc_Functions.h',['../a00521.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fcalculation',['McuxClPkc_Functions_Calculation',['../a00965.html',1,'']]], + ['mcuxclpkc_5ffunctions_5finit',['McuxClPkc_Functions_Init',['../a00963.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fuptrt',['McuxClPkc_Functions_UPTRT',['../a00964.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fwait',['McuxClPkc_Functions_Wait',['../a00966.html',1,'']]], + ['mcuxclpkc_5fgenerateuptrt',['mcuxClPkc_GenerateUPTRT',['../a00964.html#gae14e20fe9fd56e0ca8125773bc88f822',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5finitialize',['mcuxClPkc_Initialize',['../a00963.html#ga338ddc55800355531bd20236fa3710b8',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fmacros',['mcuxClPkc_Macros',['../a00828.html',1,'']]], + ['mcuxclpkc_5fmisc_5f',['MCUXCLPKC_MISC_',['../a00968.html',1,'']]], + ['mcuxclpkc_5fpackargs2',['MCUXCLPKC_PACKARGS2',['../a00968.html#ga5040d930ab47ec9246a95cf32b8f5fed',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fpackargs4',['MCUXCLPKC_PACKARGS4',['../a00968.html#gac13331e9f328b7a4446314837be58138',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fptrfupentry_5ft',['mcuxClPkc_PtrFUPEntry_t',['../a00965.html#ga9c5b69d5d2b5e9b7551de9cbe163050f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fram_5fstart_5faddress',['MCUXCLPKC_RAM_START_ADDRESS',['../a00968.html#ga0de371abb530f10283d7f8ba4bf8dd76',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5frandomizeuptrt',['mcuxClPkc_RandomizeUPTRT',['../a00964.html#gaf961165a01be833d3200563399a2c9aa',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5frerandomizeuptrt',['mcuxClPkc_ReRandomizeUPTRT',['../a00964.html#ga195c78d51f2084c693257bc52c725c1f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5froundup_5fsize',['MCUXCLPKC_ROUNDUP_SIZE',['../a00968.html#ga5d67b3705403f3a0cab0d71316df929b',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fstate_5ft',['mcuxClPkc_State_t',['../a01261.html',1,'']]], + ['mcuxclpkc_5fstatus_5f',['MCUXCLPKC_STATUS_',['../a00967.html',1,'']]], + ['mcuxclpkc_5fstatus_5fnok',['MCUXCLPKC_STATUS_NOK',['../a00967.html#gab1f0a5295736463652b7a8c1ba887991',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fstatus_5fok',['MCUXCLPKC_STATUS_OK',['../a00967.html#ga12385077399c226411e29ef427246669',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fstatus_5fprotected_5ft',['mcuxClPkc_Status_Protected_t',['../a00967.html#gaaee98013327cc5777f68c6b9fdb1ef6d',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fstatus_5ft',['mcuxClPkc_Status_t',['../a00967.html#ga9382ab1c4689794b50a3b75ad39a350c',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5ftypes_2eh',['mcuxClPkc_Types.h',['../a00524.html',1,'']]], + ['mcuxclpkc_5fwaitforfinish',['mcuxClPkc_WaitForFinish',['../a00966.html#ga7d26efcc91094390f7c55fbd870692cd',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fwaitforready',['mcuxClPkc_WaitForReady',['../a00966.html#ga963b13a65f2ae869947cbbebf2f9a823',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fwordsize',['MCUXCLPKC_WORDSIZE',['../a00968.html#ga275596959934aecdbc4dc35cefb1c6ba',1,'mcuxClPkc_Types.h']]], + ['mcuxclrandom',['mcuxClRandom',['../a00829.html',1,'']]], + ['mcuxclrandom_2eh',['mcuxClRandom.h',['../a00527.html',1,'']]], + ['mcuxclrandom_5fchecksecuritystrength',['mcuxClRandom_checkSecurityStrength',['../a00831.html#ga6e48c6007ea1d6cfa2ec329152072fc0',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fconfig',['mcuxClRandom_Config',['../a01265.html',1,'']]], + ['mcuxclrandom_5fconfig_5ft',['mcuxClRandom_Config_t',['../a00832.html#gaf1284eaa96ef47c06697f95e74ffc3ee',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fconstants',['mcuxClRandom_Constants',['../a00830.html',1,'']]], + ['mcuxclrandom_5fconstants_2eh',['mcuxClRandom_Constants.h',['../a00530.html',1,'']]], + ['mcuxclrandom_5fcontext_5ft',['mcuxClRandom_Context_t',['../a00832.html#gac2ce3a52788240794afde522cfad65c5',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fcontextdescriptor_5ft',['mcuxClRandom_ContextDescriptor_t',['../a00832.html#gab409cd7b1e5a4da822bf9ae43d00c79c',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5ffunctions',['mcuxClRandom_Functions',['../a00831.html',1,'']]], + ['mcuxclrandom_5ffunctions_2eh',['mcuxClRandom_Functions.h',['../a00533.html',1,'']]], + ['mcuxclrandom_5fgenerate',['mcuxClRandom_generate',['../a00831.html#gadb7d7b6ff820450be3533014cb47f279',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5finit',['mcuxClRandom_init',['../a00831.html#ga989cf9033b30c383d1548037f2ec8bc9',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fmode_5ft',['mcuxClRandom_Mode_t',['../a00832.html#ga2998181a66cbdc063aa08d76e5fdef9d',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fmodedescriptor_5ft',['mcuxClRandom_ModeDescriptor_t',['../a00832.html#gadcfae984a95f3e98617ca5fb9767f5cd',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fncgenerate',['mcuxClRandom_ncGenerate',['../a00831.html#ga942c035e4c1971f3e4da8cf252b6cdf6',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fncinit',['mcuxClRandom_ncInit',['../a00831.html#ga4522b9cfa28cb224b653003d481d7100',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5freseed',['mcuxClRandom_reseed',['../a00831.html#ga89fe90a4ca175d03b4a821cf2fa2004f',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fselftest',['mcuxClRandom_selftest',['../a00831.html#ga4c882c0d6b1e1bba418934c44acc873c',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fstatus_5f',['MCUXCLRANDOM_STATUS_',['../a00969.html',1,'']]], + ['mcuxclrandom_5fstatus_5ferror',['MCUXCLRANDOM_STATUS_ERROR',['../a00969.html#ga1b55e6564466854e9bd070d5bf20c46c',1,'mcuxClRandom_Constants.h']]], + ['mcuxclrandom_5fstatus_5ffault_5fattack',['MCUXCLRANDOM_STATUS_FAULT_ATTACK',['../a00969.html#ga6d4a0c17c9ec70556936f749305dace8',1,'mcuxClRandom_Constants.h']]], + ['mcuxclrandom_5fstatus_5finvalid_5fparam',['MCUXCLRANDOM_STATUS_INVALID_PARAM',['../a00969.html#ga9b0f869c046d3055dcc6f994c9aa0191',1,'mcuxClRandom_Constants.h']]], + ['mcuxclrandom_5fstatus_5flow_5fsecurity_5fstrength',['MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH',['../a00969.html#ga1318606347b0aa4a477b68572a862552',1,'mcuxClRandom_Constants.h']]], + ['mcuxclrandom_5fstatus_5fok',['MCUXCLRANDOM_STATUS_OK',['../a00969.html#ga951990ff5179cd6fce7310de16002b20',1,'mcuxClRandom_Constants.h']]], + ['mcuxclrandom_5fstatus_5ft',['mcuxClRandom_Status_t',['../a00832.html#ga768ea9930242003d2a68991684a1e948',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5ftypes',['mcuxClRandom_Types',['../a00832.html',1,'']]], + ['mcuxclrandom_5ftypes_2eh',['mcuxClRandom_Types.h',['../a00536.html',1,'']]], + ['mcuxclrandom_5funinit',['mcuxClRandom_uninit',['../a00831.html#ga92889d1e06ba33656278bd2a4110be99',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandommodes_2eh',['mcuxClRandomModes.h',['../a00539.html',1,'']]], + ['mcuxclrandom_5fconstants',['mcuxClRandom_Constants',['../a00833.html',1,'']]], + ['mcuxclrandommodes_5fconstants_2eh',['mcuxClRandomModes_Constants.h',['../a00542.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fdrg3_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c',['../a00140.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fdrg4_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c',['../a00146.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fels_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c',['../a00134.html',1,'']]], + ['mcuxclrandommodes_5fdifferent_5fsessions_5fexample_2ec',['mcuxClRandomModes_Different_Sessions_example.c',['../a00143.html',1,'']]], + ['mcuxclrandommodes_5fels_5fexample_2ec',['mcuxClRandomModes_ELS_example.c',['../a00137.html',1,'']]], + ['mcuxclrandommodes_5fmdels_5fdrbg',['mcuxClRandomModes_mdELS_Drbg',['../a00833.html#ga33a2ec75a1ffddc069c679de7c34b8fc',1,'mcuxClRandomModes_Constants.h']]], + ['mcuxclrandommodes_5fmemoryconsumption',['mcuxClRandomModes_MemoryConsumption',['../a00838.html',1,'']]], + ['mcuxclrandommodes_5fmemoryconsumption_2eh',['mcuxClRandomModes_MemoryConsumption.h',['../a00551.html',1,'']]], + ['mcuxclrandommodes_5fpatchmode_5fctrdrbg_5faes256_5fdrg3_5fexample_2ec',['mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c',['../a00149.html',1,'']]], + ['mcuxclrandommodes_5ftestmode_5fctrdrbg_5faes256_5fdrg4_5fexample_2ec',['mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c',['../a00155.html',1,'']]], + ['mcuxclrandommodes_5ftestmode_5fctrdrbg_5faes256_5fptg3_5fexample_2ec',['mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c',['../a00152.html',1,'']]], + ['mcuxclrsa',['mcuxClRsa',['../a00839.html',1,'']]], + ['mcuxclrsa_2eh',['mcuxClRsa.h',['../a00554.html',1,'']]], + ['mcuxclrsa_5fconstants',['mcuxClRsa_Constants',['../a00840.html',1,'']]], + ['mcuxclrsa_5fconstants_2eh',['mcuxClRsa_Constants.h',['../a00557.html',1,'']]], + ['mcuxclrsa_5ffunctions',['mcuxClRsa_Functions',['../a00843.html',1,'']]], + ['mcuxclrsa_5ffunctions_2eh',['mcuxClRsa_Functions.h',['../a00560.html',1,'']]], + ['mcuxclrsa_5fkey',['mcuxClRsa_Key',['../a01273.html',1,'mcuxClRsa_Key'],['../a00853.html#gaa10abda6e87540ddd4db42c84aa5f8f5',1,'mcuxClRsa_Key(): mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkey_5f',['MCUXCLRSA_KEY_',['../a00851.html',1,'']]], + ['mcuxclrsa_5fkey_5fprivatecrt',['MCUXCLRSA_KEY_PRIVATECRT',['../a00851.html#gade33615f2bc73e552ca020a1e43a41c3',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkey_5fprivatecrt_5fdfa',['MCUXCLRSA_KEY_PRIVATECRT_DFA',['../a00851.html#gac5562ce31d1bc26cf93b647a17e38814',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkey_5fprivateplain',['MCUXCLRSA_KEY_PRIVATEPLAIN',['../a00851.html#ga16c4298a66c8a1a7c2e18aca938442a6',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkey_5fpublic',['MCUXCLRSA_KEY_PUBLIC',['../a00851.html#ga4c194e24352de4ab02294292f35f24d9',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkeyentry',['mcuxClRsa_KeyEntry',['../a00853.html#ga45ab9e1108bb7a629af14c74d8392622',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkeyentry_5ft',['mcuxClRsa_KeyEntry_t',['../a01269.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fcrt',['mcuxClRsa_KeyGeneration_Crt',['../a00843.html#gaa099449b2290a333aac2dcf090a2740c',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f2048_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE',['../a00846.html#gad96d63918b029c58379a519458e0fe5e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f2048_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE',['../a00846.html#ga50df60e5ac10a4d18d91793b9975f931',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f3072_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE',['../a00846.html#ga4f7ea947e335da713b995b3dd5756726',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f3072_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE',['../a00846.html#ga9cddbdf9c06180c1ad4f1004c013a3b0',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f4096_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE',['../a00846.html#ga7cd47280b5c29ab35fe15afdb1aff9b5',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5f4096_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE',['../a00846.html#ga046e2a5713b8ad6d69f9882d2fde5b3f',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fkey_5fdata_5f2048_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE',['../a00848.html#ga726a733c6b7203ed8ffb1fcc542d3947',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fkey_5fdata_5f3072_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE',['../a00848.html#ga42819dfa5d08299cd05b1589d354aea8',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fkey_5fdata_5f4096_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE',['../a00848.html#ga9326e34e5b0cae6bba738466a089b523',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fwa',['MCUXCLRSA_KEYGENERATION_CRT_WA',['../a00846.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE',['../a00846.html#gab62b9607b6acf175174f192227482782',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE',['../a00846.html#ga398705431e601a6309bcf59a65f72328',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fkey_5fdata_5fsize',['MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE',['../a00848.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fplain',['mcuxClRsa_KeyGeneration_Plain',['../a00843.html#ga08dff8d41898b3f372ceab1038205b51',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f2048_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE',['../a00847.html#ga8bfbe68f2ddf833c65badc56832310ff',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f2048_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE',['../a00847.html#gaeaf97fe967de3e01d06b80d4aecf62ba',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f3072_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE',['../a00847.html#ga499a98e9b3b5f98b43d41bace11d6d2a',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f3072_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE',['../a00847.html#ga76dbc936b3c90bf4e66824697b16be80',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f4096_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE',['../a00847.html#gacfaaad0cd3da9dd167a4068a2a2fda7f',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5f4096_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE',['../a00847.html#ga2e6c1c9053ca24c4101e348c9f8d2588',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fkey_5fdata_5f2048_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE',['../a00848.html#gaad6be857cb7e5a3e95f09e0122f2e94a',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fkey_5fdata_5f3072_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE',['../a00848.html#gab391bd614cb01e50e382c9dd20c17666',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fkey_5fdata_5f4096_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE',['../a00848.html#gaa60cf674b45656cf7500cd50749d8088',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fwa',['MCUXCLRSA_KEYGENERATION_PLAIN_WA',['../a00847.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fwacpu_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE',['../a00847.html#gab0c5e4df4d6371815ec7b1d962053507',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fwapkc_5fsize',['MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE',['../a00847.html#ga989c3c758b19a6f32cb0ac16dc698bc2',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fpublic_5fkey_5fdata_5f2048_5fsize',['MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE',['../a00848.html#gae34fdb8022b5b8b2d62794b19ed310cf',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fpublic_5fkey_5fdata_5f3072_5fsize',['MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE',['../a00848.html#ga78776bc5abbc55e6ebe24450dac788f3',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fkeygeneration_5fpublic_5fkey_5fdata_5f4096_5fsize',['MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE',['../a00848.html#ga0cb2520b3056a154c1d551b2a677dd12',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fmacros',['mcuxClRsa_Macros',['../a00849.html',1,'']]], + ['mcuxclrsa_5fmemoryconsumption_2eh',['mcuxClRsa_MemoryConsumption.h',['../a00563.html',1,'']]], + ['mcuxclrsa_5fmode_5fsign_5fnoencode',['mcuxClRsa_Mode_Sign_NoEncode',['../a00841.html#ga4459d773156bf4ac906a1416dd4ed4f4',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f224',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224',['../a00841.html#gac7cfd526cb16ba49a48ea0881c12e778',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f256',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256',['../a00841.html#ga1845c307f6b2897cf563c1ad97523840',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f384',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384',['../a00841.html#ga2e630f5e6e06e0b5adc2d5f63268b77f',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f512',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512',['../a00841.html#ga61cdf384d5eb7774a35bec2dd28b67c8',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f224',['mcuxClRsa_Mode_Sign_Pss_Sha2_224',['../a00841.html#ga6544c3cc75077dde34304c5c45999edf',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f256',['mcuxClRsa_Mode_Sign_Pss_Sha2_256',['../a00841.html#gaf88819f8def0ed1dc626168103856a25',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f384',['mcuxClRsa_Mode_Sign_Pss_Sha2_384',['../a00841.html#ga884749f4e133157dcdc3b85d15b98ada',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f512',['mcuxClRsa_Mode_Sign_Pss_Sha2_512',['../a00841.html#gab71896db47c552effcdad152a574e5a1',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fnoverify',['mcuxClRsa_Mode_Verify_NoVerify',['../a00842.html#ga9274985a905326fe0bcbe3ab23123e75',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f224',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224',['../a00842.html#gafaa7d91b00e9a3e5edbcc8ea8d0d2320',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f256',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256',['../a00842.html#gaebc33a997f28ae34f977899c4da4f117',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f384',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384',['../a00842.html#ga6e5c11f4096af091859db6a5f3009c43',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f512',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512',['../a00842.html#gafc855e8c67d58fc5b0e79e89eac6d976',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f224',['mcuxClRsa_Mode_Verify_Pss_Sha2_224',['../a00842.html#gaba34c04545877c67789942d9a2c9134a',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f256',['mcuxClRsa_Mode_Verify_Pss_Sha2_256',['../a00842.html#gab80d7f48edeb8b4c401221180572e4f2',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f384',['mcuxClRsa_Mode_Verify_Pss_Sha2_384',['../a00842.html#ga74c434306a9d393e51b4997152381b8e',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f512',['mcuxClRsa_Mode_Verify_Pss_Sha2_512',['../a00842.html#ga4214b439b403de8eda53043cdf71ca83',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5foption_5f',['MCUXCLRSA_OPTION_',['../a00852.html',1,'']]], + ['mcuxclrsa_5foption_5fmessage_5fdigest',['MCUXCLRSA_OPTION_MESSAGE_DIGEST',['../a00852.html#gaae780b6c51aa31e7e9f20cb2afddf9c6',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5foption_5fmessage_5fmask',['MCUXCLRSA_OPTION_MESSAGE_MASK',['../a00852.html#gac091ddc4844c510873c4492061ce7a5f',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5foption_5fmessage_5fplain',['MCUXCLRSA_OPTION_MESSAGE_PLAIN',['../a00852.html#ga60de22c98680641aaef3331fbd5bb0f1',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fsign',['mcuxClRsa_sign',['../a00843.html#gaea19a43d7a52c159675d93d8e7d6ec51',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fsign_5fcrt_5f1024_5fwapkc_5fsize',['MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE',['../a00844.html#gaace82904ad5b20b810d80d9561e6277b',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5f2048_5fwapkc_5fsize',['MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE',['../a00844.html#gaab6efa4449159180daf2c0ad4452283c',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5f3072_5fwapkc_5fsize',['MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE',['../a00844.html#ga7844b694581a8cb752edd86444a10812',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5f4096_5fwapkc_5fsize',['MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE',['../a00844.html#ga56f2ed2760ce4db4e8246d96f768e23e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fnoencode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE',['../a00844.html#ga08af4d804d4c5dd22c246fe4ee55afd1',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fnoencode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE',['../a00844.html#gada60205f871f7cbdff86547038599ec8',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fnoencode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE',['../a00844.html#gaa9fbd44b2d8b333ef36b98aa36d8ce91',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fnoencode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE',['../a00844.html#ga9afbf286d2d7eda637ba13f19bbf727f',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fnoencode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE',['../a00844.html#ga97d05e715e7d13e8eccdaad372e7d50a',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpkcs1v15encode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE',['../a00844.html#gaf8a8d4ef6856d0325171771a38ed2b3f',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpkcs1v15encode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE',['../a00844.html#ga13a37dc2bf4e9369d0f97257eedbb240',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpkcs1v15encode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE',['../a00844.html#gaf1c40d9d43240fca324f6bddb7ba22b2',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpkcs1v15encode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE',['../a00844.html#ga85c6c2f1faf8413022119493161d08eb',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpkcs1v15encode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE',['../a00844.html#ga437b8eb62b4f1c455f0fcf9185dee790',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpssencode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE',['../a00844.html#ga94c5de50e6e2c146a56ca41fe875b1ae',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpssencode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE',['../a00844.html#gaffa8f7a22bc5dc5f0102e6a7d58aae22',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpssencode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE',['../a00844.html#ga622d0a8ac987bd0a74fbf3a6aafb0622',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpssencode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE',['../a00844.html#ga56c7e14b62345bd224a7dd133c9cf47e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fpssencode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE',['../a00844.html#gaae863be535c94424a53999e430f94345',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fcrt_5fwapkc_5fsize',['MCUXCLRSA_SIGN_CRT_WAPKC_SIZE',['../a00844.html#gae92072e416a0f52664b7720d33b1fd91',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fmodes',['mcuxClRsa_Sign_Modes',['../a00841.html',1,'']]], + ['mcuxclrsa_5fsign_5fnoencode_5fexample_2ec',['mcuxClRsa_sign_NoEncode_example.c',['../a00167.html',1,'']]], + ['mcuxclrsa_5fsign_5fplain_5f1024_5fwapkc_5fsize',['MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE',['../a00844.html#ga48b4346142911ddd75ac4bb4575b4a44',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5f2048_5fwapkc_5fsize',['MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE',['../a00844.html#ga5b2d3626004c26e5935658c75faed0fe',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5f3072_5fwapkc_5fsize',['MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE',['../a00844.html#ga87f2af5e231ca701d6c241260f6632c8',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5f4096_5fwapkc_5fsize',['MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE',['../a00844.html#gac51d995815daa1270660faa6c941556b',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fnoencode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE',['../a00844.html#ga62affe57ed8b934c432d1e4957ca2b96',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fnoencode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE',['../a00844.html#ga0771ad370b59155e8fee261c84e51531',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fnoencode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE',['../a00844.html#gae3e6841f0361a7df7d5308d663b114c6',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fnoencode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE',['../a00844.html#ga34b88e6a0e6b4168b989aa9d6bf9c569',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fnoencode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE',['../a00844.html#gaa605aa3b59dcc107147ddeb6fcb7e8c0',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpkcs1v15encode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE',['../a00844.html#ga25a8fb0b64b30957a85d6cc8ccff3694',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpkcs1v15encode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE',['../a00844.html#ga6c85361c450a7a291e4a21ba5ad8c829',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpkcs1v15encode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE',['../a00844.html#gaa0b8b7e5e999f0f647b157570879ab70',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpkcs1v15encode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE',['../a00844.html#ga48f0eed84fa89303aab8926a5af140e0',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpkcs1v15encode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE',['../a00844.html#gab630a43086137a34a22d379d99d4979e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpssencode_5f1024_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE',['../a00844.html#ga4312eb8909ce30ba6362af6aaa03f69e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpssencode_5f2048_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE',['../a00844.html#gaf455d79389af05675935d6d53d7ade7c',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpssencode_5f3072_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE',['../a00844.html#ga164cca6715f5d4ad090ccc4ab882dd68',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpssencode_5f4096_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE',['../a00844.html#ga773066aea6da7ba38442305ad2bf6af2',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fpssencode_5fwacpu_5fsize',['MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE',['../a00844.html#ga1dea31cb3edffff3b19d105f7374aa81',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fplain_5fwapkc_5fsize',['MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE',['../a00844.html#gab592bb2afe239d110b69019bbcfbf39a',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fsign_5fpss_5fsha2_5f256_5fexample_2ec',['mcuxClRsa_sign_pss_sha2_256_example.c',['../a00161.html',1,'']]], + ['mcuxclrsa_5fsign_5fwa',['MCUXCLRSA_SIGN_WA',['../a00844.html',1,'']]], + ['mcuxclrsa_5fsignverifymode',['mcuxClRsa_SignVerifyMode',['../a00853.html#ga9135a8d95f26a1b90c7a251886bce7e5',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fsignverifymode_5ft',['mcuxClRsa_SignVerifyMode_t',['../a00853.html#gabe334b37ac763b3943364b26e130d0df',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5f',['MCUXCLRSA_STATUS_',['../a00850.html',1,'']]], + ['mcuxclrsa_5fstatus_5ferror',['MCUXCLRSA_STATUS_ERROR',['../a00850.html#gac062bb04172f071a8595aa39bef80edc',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5ffault_5fattack',['MCUXCLRSA_STATUS_FAULT_ATTACK',['../a00850.html#gaf886957f4dc2794dd12839a690ae05d0',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5finvalid_5finput',['MCUXCLRSA_STATUS_INVALID_INPUT',['../a00850.html#ga14e28c4e4b6a325ddd1f038b5274ccec',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fkeygeneration_5fiterationsexceeded',['MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED',['../a00850.html#ga90072cc31c18394f5e5d3a2e63e014fa',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fkeygeneration_5fok',['MCUXCLRSA_STATUS_KEYGENERATION_OK',['../a00850.html#gab08354492e4b0feceab7a3615abee1f0',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fprotected_5ft',['mcuxClRsa_Status_Protected_t',['../a00853.html#ga60189e258e6739b78e900b025be0ab34',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5frng_5ferror',['MCUXCLRSA_STATUS_RNG_ERROR',['../a00850.html#gadd600ddd2a4c8c2fc79f427e438f81f4',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fsign_5fok',['MCUXCLRSA_STATUS_SIGN_OK',['../a00850.html#gac7719ba5cbecc181bef2b21dca99fdf3',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5ft',['mcuxClRsa_Status_t',['../a00853.html#gab654093108d59a4690e464f314356e69',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fverify_5ffailed',['MCUXCLRSA_STATUS_VERIFY_FAILED',['../a00850.html#ga05d091562f747706d7aecfb99b5a735c',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fverify_5fok',['MCUXCLRSA_STATUS_VERIFY_OK',['../a00850.html#ga2dbb489ad7452a487a5d49df5a979d69',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fverifyprimitive_5fok',['MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK',['../a00850.html#gadabda4063a5cfe9766a7201d271d8f0a',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5ftypes',['mcuxClRsa_Types',['../a00853.html',1,'']]], + ['mcuxclrsa_5ftypes_2eh',['mcuxClRsa_Types.h',['../a00566.html',1,'']]], + ['mcuxclrsa_5fverify',['mcuxClRsa_verify',['../a00843.html#ga21bf92b81f28be1b6b6fc7d3bdc69098',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fverify_5f1024_5fwapkc_5fsize',['MCUXCLRSA_VERIFY_1024_WAPKC_SIZE',['../a00845.html#gaf6485ca0f6a219994ba327e9f35dbb94',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5f2048_5fwapkc_5fsize',['MCUXCLRSA_VERIFY_2048_WAPKC_SIZE',['../a00845.html#ga347b86aaa2ec9e1c6b42d53b8b550139',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5f3072_5fwapkc_5fsize',['MCUXCLRSA_VERIFY_3072_WAPKC_SIZE',['../a00845.html#gaf370a2aea81eaa53070ecd49de1291fb',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5f4096_5fwapkc_5fsize',['MCUXCLRSA_VERIFY_4096_WAPKC_SIZE',['../a00845.html#ga8472e567acdaf653ea64617586e69dd5',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5fmodes',['mcuxClRsa_Verify_Modes',['../a00842.html',1,'']]], + ['mcuxclrsa_5fverify_5fnoverify_5fexample_2ec',['mcuxClRsa_verify_NoVerify_example.c',['../a00164.html',1,'']]], + ['mcuxclrsa_5fverify_5fnoverify_5fwacpu_5fsize',['MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE',['../a00845.html#gac0a79e3e30fbf6610c95ad399bb55165',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5fpkcs1v15verify_5fwacpu_5fsize',['MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE',['../a00845.html#gab9dc9df4db1e42592e9f23b90abf7432',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5fpssverify_5fsha2_5f256_5fexample_2ec',['mcuxClRsa_verify_pssverify_sha2_256_example.c',['../a00158.html',1,'']]], + ['mcuxclrsa_5fverify_5fpssverify_5fwacpu_5fsize',['MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE',['../a00845.html#gaf4bcc54a8a49029c2454d0afdca0a18e',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclrsa_5fverify_5fwa',['MCUXCLRSA_VERIFY_WA',['../a00845.html',1,'']]], + ['mcuxclrsa_5fverify_5fwapkc_5fsize',['MCUXCLRSA_VERIFY_WAPKC_SIZE',['../a00845.html#ga1890b9a82cba6144b533121da365baeb',1,'mcuxClRsa_MemoryConsumption.h']]], + ['mcuxclsession',['mcuxClSession',['../a00854.html',1,'']]], + ['mcuxclsession_2eh',['mcuxClSession.h',['../a00569.html',1,'']]], + ['mcuxclsession_5fcleanup',['mcuxClSession_cleanup',['../a00855.html#ga1ba3d2c6e561c86e1da8fcc0abfd046c',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5fconstants',['mcuxClSession_Constants',['../a00856.html',1,'']]], + ['mcuxclsession_5fdescriptor',['mcuxClSession_Descriptor',['../a01285.html',1,'']]], + ['mcuxclsession_5fdescriptor_5ft',['mcuxClSession_Descriptor_t',['../a00859.html#gafe6e209ab6b552af2011043383473f18',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fdestroy',['mcuxClSession_destroy',['../a00855.html#gaad324fd8f8eeefa29521c4297ac75fd2',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5ffunctions',['mcuxClSession_Functions',['../a00855.html',1,'']]], + ['mcuxclsession_5ffunctions_2eh',['mcuxClSession_Functions.h',['../a00572.html',1,'']]], + ['mcuxclsession_5fhandle_5ft',['mcuxClSession_Handle_t',['../a00859.html#ga17fd337618b05459b4a343393e099b56',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5finit',['mcuxClSession_init',['../a00855.html#gaf1b8776b0d519136df17f6dd632442cf',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5fmemoryconsumption_2eh',['mcuxClSession_MemoryConsumption.h',['../a00575.html',1,'']]], + ['mcuxclsession_5frtf_5ft',['mcuxClSession_Rtf_t',['../a00859.html#gac635eeca4268dbd500e45806ee37f685',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5frtf_5fupdate_5ffalse',['MCUXCLSESSION_RTF_UPDATE_FALSE',['../a00858.html#ga922a60abc33fb57bb5b4587324f2d73c',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5frtf_5fupdate_5ftrue',['MCUXCLSESSION_RTF_UPDATE_TRUE',['../a00858.html#ga17963249b8a091124c5442ca642a55d8',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fsecuritycontext',['mcuxClSession_SecurityContext',['../a01281.html',1,'']]], + ['mcuxclsession_5fsecuritycontext_5ft',['mcuxClSession_SecurityContext_t',['../a00859.html#gac2866aae4d5a869b0fa55c82190d0c93',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fsecurityoptions_5ft',['mcuxClSession_SecurityOptions_t',['../a00859.html#gabd24855c86970aaa97d3c6975a8ca53c',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fsetrtf',['mcuxClSession_setRtf',['../a00855.html#ga159bff529d405fd6da2930590a69ac06',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5fstatus_5ferror',['MCUXCLSESSION_STATUS_ERROR',['../a00857.html#ga547425b7379de3ee1fb96c79140fd68e',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5fhw_5funavailable',['MCUXCLSESSION_STATUS_HW_UNAVAILABLE',['../a00857.html#gaa3a0727f4c8a2658cb607d45cd28229e',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5fok',['MCUXCLSESSION_STATUS_OK',['../a00857.html#ga3f63cf17e4f26ba5ee4d92152fca1eb6',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5fprotected_5ft',['mcuxClSession_Status_Protected_t',['../a00859.html#ga09bbfe382aac167ec94e8e6e3d2b10f6',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5ft',['mcuxClSession_Status_t',['../a00859.html#ga9f2ec672d5a5fe92159f0e6159e04e4e',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5ftypes',['mcuxClSession_Types',['../a00859.html',1,'']]], + ['mcuxclsession_5ftypes_2eh',['mcuxClSession_Types.h',['../a00578.html',1,'']]], + ['mcuxclsession_5fworkarea',['mcuxClSession_WorkArea',['../a01277.html',1,'']]], + ['mcuxclsession_5fworkarea_5ft',['mcuxClSession_WorkArea_t',['../a00859.html#ga13a1a61b81f8b8bdc5272d33b44a2dac',1,'mcuxClSession_Types.h']]], + ['mcux_20cssl_20_26ndash_3b_20api',['MCUX CSSL &ndash; API',['../a00860.html',1,'']]], + ['mcux_20cssl_20_26ndash_3b_20configurations',['MCUX CSSL &ndash; Configurations',['../a00864.html',1,'']]], + ['mcuxcsslcpreprocessor_2eh',['mcuxCsslCPreProcessor.h',['../a00584.html',1,'']]], + ['mcuxcssldataintegrity_2eh',['mcuxCsslDataIntegrity.h',['../a00587.html',1,'']]], + ['mcuxcssldataintegrity_5fcfg_2eh',['mcuxCsslDataIntegrity_Cfg.h',['../a00590.html',1,'']]], + ['mcuxcssldataintegrity_5fimpl_2eh',['mcuxCsslDataIntegrity_Impl.h',['../a00593.html',1,'']]], + ['mcuxcssldataintegrity_5fnone_2eh',['mcuxCsslDataIntegrity_None.h',['../a00596.html',1,'']]], + ['mcuxcsslflowprotection_2eh',['mcuxCsslFlowProtection.h',['../a00599.html',1,'']]], + ['mcuxcsslflowprotection_5fcfg_2eh',['mcuxCsslFlowProtection_Cfg.h',['../a00602.html',1,'']]], + ['mcuxcsslflowprotection_5ffunctionidentifiers_2eh',['mcuxCsslFlowProtection_FunctionIdentifiers.h',['../a00605.html',1,'']]], + ['mcuxcsslflowprotection_5fimpl_2eh',['mcuxCsslFlowProtection_Impl.h',['../a00608.html',1,'']]], + ['mcuxcsslflowprotection_5fsecurecounter_5fcommon_2eh',['mcuxCsslFlowProtection_SecureCounter_Common.h',['../a00611.html',1,'']]], + ['mcuxcsslflowprotection_5fsecurecounter_5flocal_2eh',['mcuxCsslFlowProtection_SecureCounter_Local.h',['../a00614.html',1,'']]], + ['mcux_20cssl_20_26ndash_3b_20implementations',['MCUX CSSL &ndash; Implementations',['../a00866.html',1,'']]], + ['mcuxcssl_20memory_20api',['mcuxCssl Memory API',['../a00885.html',1,'']]], + ['mcuxcsslmemory_2eh',['mcuxCsslMemory.h',['../a00617.html',1,'']]], + ['mcuxcsslmemory_5fclear',['mcuxCsslMemory_Clear',['../a00887.html#gaea7d5f3c8d216e752f153827689e88c3',1,'mcuxCsslMemory_Clear(mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, size_t dstLength, size_t length): mcuxCsslMemory_Clear.h'],['../a00886.html',1,'(Global Namespace)']]], + ['mcuxcsslmemory_5fclear_2eh',['mcuxCsslMemory_Clear.h',['../a00620.html',1,'']]], + ['mcuxcsslmemory_5fclear_20function_20definitions',['mcuxCsslMemory_Clear Function Definitions',['../a00887.html',1,'']]], + ['mcuxcsslmemory_5fcompare',['mcuxCsslMemory_Compare',['../a00889.html#ga0a6695838853535250234994d7e4d5b1',1,'mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Checksum_t chk, void const *pLhs, void const *pRhs, size_t length): mcuxCsslMemory_Compare.h'],['../a00888.html',1,'(Global Namespace)']]], + ['mcuxcsslmemory_5fcompare_2eh',['mcuxCsslMemory_Compare.h',['../a00623.html',1,'']]], + ['mcuxcsslmemory_5fcompare_20function_20definitions',['mcuxCsslMemory_Compare Function Definitions',['../a00889.html',1,'']]], + ['mcuxcsslmemory_5fcopy',['mcuxCsslMemory_Copy',['../a00891.html#gaa29b7e8d23c8d95ce248fc8e0a4b37c8',1,'mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Checksum_t chk, void const *pSrc, void *pDst, size_t dstLength, size_t length): mcuxCsslMemory_Copy.h'],['../a00890.html',1,'(Global Namespace)']]], + ['mcuxcsslmemory_5fcopy_2eh',['mcuxCsslMemory_Copy.h',['../a00626.html',1,'']]], + ['mcuxcsslmemory_5fcopy_20function_20definitions',['mcuxCsslMemory_Copy Function Definitions',['../a00891.html',1,'']]], + ['mcuxcsslmemory_5fkeep_5forder',['MCUXCSSLMEMORY_KEEP_ORDER',['../a00895.html#ga0072c925d0ab8c5b0b071abd1d5218af',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5freverse_5forder',['MCUXCSSLMEMORY_REVERSE_ORDER',['../a00895.html#ga9c4cf10d8106eca9894d9e3b131b52f9',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fset',['mcuxCsslMemory_Set',['../a00893.html#ga0a0ed6d55e0cb4d633ba19a32aca64c6',1,'mcuxCsslMemory_Set(mcuxCsslParamIntegrity_Checksum_t chk, void *pDst, uint8_t val, size_t length, size_t bufLength): mcuxCsslMemory_Set.h'],['../a00892.html',1,'(Global Namespace)']]], + ['mcuxcsslmemory_5fset_2eh',['mcuxCsslMemory_Set.h',['../a00629.html',1,'']]], + ['mcuxcsslmemory_5fset_20function_20definitions',['mcuxCsslMemory_Set Function Definitions',['../a00893.html',1,'']]], + ['mcuxcsslmemory_5fstatus_5fequal',['MCUXCSSLMEMORY_STATUS_EQUAL',['../a00895.html#gafaad4a560714fdff8064ba9a50f7d572',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fstatus_5ffault',['MCUXCSSLMEMORY_STATUS_FAULT',['../a00895.html#gaf0923b98a5db9fd23732989986d72f4d',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fstatus_5finvalid_5fparameter',['MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER',['../a00895.html#ga0e60adf6203cb3acb2bdb3ddec166766',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fstatus_5fnot_5fequal',['MCUXCSSLMEMORY_STATUS_NOT_EQUAL',['../a00895.html#ga2b5d2b24036bee244a9e7310160b3035',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fstatus_5fok',['MCUXCSSLMEMORY_STATUS_OK',['../a00895.html#gab2993c75e7ef98fed36f03946630e41c',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5fstatus_5ft',['mcuxCsslMemory_Status_t',['../a00896.html#ga19c7a1367cb21d7bcb720607f495d86c',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslmemory_5ftypes',['mcuxCsslMemory_Types',['../a00894.html',1,'']]], + ['mcuxcsslmemory_5ftypes_2eh',['mcuxCsslMemory_Types.h',['../a00632.html',1,'']]], + ['mcuxcsslmemory_5ftypes_5fmacros',['mcuxCsslMemory_Types_Macros',['../a00895.html',1,'']]], + ['mcuxcsslmemory_5ftypes_5ftypes',['mcuxCsslMemory_Types_Types',['../a00896.html',1,'']]], + ['mcuxcsslparamintegrity_2eh',['mcuxCsslParamIntegrity.h',['../a00635.html',1,'']]], + ['mcuxcsslparamintegrity_5fassertioncpuwordsize_5ft',['mcuxCsslParamIntegrity_AssertionCpuWordSize_t',['../a00899.html#gaf2a8a66e39dd0d33d085d3d412cafb96',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fbase_5fchecksum',['MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM',['../a00898.html#ga53aac27cab05b855d2ae62f2b1d3d7d0',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fcheck_5finvalid',['MCUXCSSLPARAMINTEGRITY_CHECK_INVALID',['../a00898.html#ga889eda2d841537edae8f0f7d80dde8b0',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fcheck_5fvalid',['MCUXCSSLPARAMINTEGRITY_CHECK_VALID',['../a00898.html#gad7a460092fbe39b438614ba1d159bb16',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fchecksum_5ft',['mcuxCsslParamIntegrity_Checksum_t',['../a00899.html#ga6a229130320b395fbb8a8a76a361bd1e',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_20function_20definitions',['mcuxCsslParamIntegrity Function Definitions',['../a00900.html',1,'']]], + ['mcuxcsslparamintegrity_20macro_20definitions',['mcuxCsslParamIntegrity Macro Definitions',['../a00898.html',1,'']]], + ['mcuxcsslparamintegrity_5fprotect',['mcuxCsslParamIntegrity_Protect',['../a00900.html#gaaa2a9f40eb61dbe8ccce1b3b2dc824bb',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_20type_20definitions',['mcuxCsslParamIntegrity Type Definitions',['../a00899.html',1,'']]], + ['mcuxcsslparamintegrity_5fvalidate',['mcuxCsslParamIntegrity_Validate',['../a00900.html#gaface23af4c626fe4adf70518056f2f33',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslsecurecounter_2eh',['mcuxCsslSecureCounter.h',['../a00638.html',1,'']]], + ['mcuxcsslsecurecounter_5fcfg_2eh',['mcuxCsslSecureCounter_Cfg.h',['../a00641.html',1,'']]], + ['mcuxcsslsecurecounter_5fimpl_2eh',['mcuxCsslSecureCounter_Impl.h',['../a00644.html',1,'']]], + ['mcuxcsslsecurecounter_5fnone_2eh',['mcuxCsslSecureCounter_None.h',['../a00647.html',1,'']]], + ['mcuxcsslsecurecounter_5fsw_5flocal_2eh',['mcuxCsslSecureCounter_SW_Local.h',['../a00650.html',1,'']]], + ['minor',['minor',['../a01033.html#a648e4b690824c4652c70d707e00b6ffe',1,'mcuxClEls_HwVersion_t']]], + ['misc',['misc',['../a00973.html#a90f3bfeae254eaa0eb7f5d97f2123906',1,'mcuxClEcc_DomainParam_t']]], + ['mode',['mode',['../a01213.html#a3f8fbc06563e97492965d16d9f7a4ed1',1,'mcuxClEls_TlsOption_t::mode()'],['../a01265.html#ad723b63c438689b0d5c978fceb289506',1,'mcuxClRandom_Config::mode()']]], + ['msg_5fadata',['msg_adata',['../a00041.html#a437ec5d6cef80672b16b267a9038fb3e',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5fenc_5fexpected',['msg_enc_expected',['../a00041.html#a087137335e23969000b7aaee28cb398d',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5fplain',['msg_plain',['../a00041.html#ab5559a8546823f96b075fb6be010313e',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5ftag_5fexpected',['msg_tag_expected',['../a00041.html#abea9520607fe8679a77f6b7f902786af',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msgendw',['msgendw',['../a00997.html#a6e7b66230e97b647ba209b8f5eb68d2f',1,'mcuxClEls_AeadOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_d.html b/components/els_pkc/doc/mcxn/html/search/all_d.html new file mode 100644 index 000000000..a2d5bd7ed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_d.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_d.js b/components/els_pkc/doc/mcxn/html/search/all_d.js new file mode 100644 index 000000000..2a22d6cd9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_d.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['one_2dshot_20cipher_20interfaces',['One-shot Cipher interfaces',['../a00674.html',1,'']]], + ['one_2dshot_20aead_20interfaces',['One-shot AEAD interfaces',['../a00664.html',1,'']]], + ['option_20bit_20field_20values_20that_20are_20needed_20for_20internal_20use_20only',['Option bit field values that are needed for internal use only',['../a00731.html',1,'']]], + ['one_2dshot_20mac_20interfaces',['One-shot MAC interfaces',['../a00797.html',1,'']]], + ['optlen',['optLen',['../a00977.html#a6d0e636ce4f30294af6bcfe0ae717a01',1,'mcuxClEcc_KeyGen_Param_t::optLen()'],['../a00981.html#af5376d1c58c5cfaf33ae6156572700ff',1,'mcuxClEcc_Sign_Param_t::optLen()'],['../a00985.html#afa16cb1249abe8848bfe2beeb909c4f3',1,'mcuxClEcc_Verify_Param_t::optLen()'],['../a00989.html#a037bdeafd85441ec7c9a5edde80ed772',1,'mcuxClEcc_PointMult_Param_t::optLen()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_e.html b/components/els_pkc/doc/mcxn/html/search/all_e.html new file mode 100644 index 000000000..f9a056dcd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_e.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_e.js b/components/els_pkc/doc/mcxn/html/search/all_e.js new file mode 100644 index 000000000..7ea81fa4a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_e.js @@ -0,0 +1,30 @@ +var searchData= +[ + ['padding_20type_20definitions',['Padding type definitions',['../a00825.html',1,'']]], + ['parameter_20integrity_20api',['Parameter Integrity API',['../a00897.html',1,'']]], + ['pa',['pA',['../a00973.html#a5916c96212c7f76a61ddc0c8aa957ef5',1,'mcuxClEcc_DomainParam_t']]], + ['pb',['pB',['../a00973.html#abcaf03eba7dd8f697e3e582de2aa1eef',1,'mcuxClEcc_DomainParam_t']]], + ['pexp1',['pExp1',['../a01273.html#a28deb463bb016edacb1938dc272deb8a',1,'mcuxClRsa_Key']]], + ['pexp2',['pExp2',['../a01273.html#accac28790b11f7574dd84f6da9877a2c',1,'mcuxClRsa_Key']]], + ['pexp3',['pExp3',['../a01273.html#a0846b30142dc6cb42d05b5c30afd71cc',1,'mcuxClRsa_Key']]], + ['pg',['pG',['../a00973.html#a63d99844f35b075f23980f9c405d034b',1,'mcuxClEcc_DomainParam_t']]], + ['phash',['pHash',['../a00981.html#aeccbb72505744e1f627b67b1f51508ef',1,'mcuxClEcc_Sign_Param_t::pHash()'],['../a00985.html#adb5823e73ed5542ddd0b4a7103e62f1f',1,'mcuxClEcc_Verify_Param_t::pHash()']]], + ['pkcwa',['pkcWa',['../a01285.html#a394996570a6810808bd59d2f9672c76a',1,'mcuxClSession_Descriptor']]], + ['pkeyentrydata',['pKeyEntryData',['../a01269.html#a1f5a90f95105b9abaf31a7997a2fb24e',1,'mcuxClRsa_KeyEntry_t']]], + ['pmod1',['pMod1',['../a01273.html#ab53f60022abcb2c60300022907c460ce',1,'mcuxClRsa_Key']]], + ['pmod2',['pMod2',['../a01273.html#ab1b71c75486149a0b722dfe36d3ca6cd',1,'mcuxClRsa_Key']]], + ['pmpint',['pMPInt',['../a01253.html#a00c20f8c0e84c867dcdfb13cf1549ce6',1,'mcuxClOscca_MPInt_t']]], + ['pn',['pN',['../a00973.html#a484854783a458fd3d3ab50bfd38afcf3',1,'mcuxClEcc_DomainParam_t']]], + ['poutputr',['pOutputR',['../a00985.html#a6b6eb3da4f84de13269bb74d79583b51',1,'mcuxClEcc_Verify_Param_t']]], + ['pp',['pP',['../a00973.html#adbfda4ce0ba171e1aa6f52e6b564d1e4',1,'mcuxClEcc_DomainParam_t']]], + ['ppoint',['pPoint',['../a00989.html#aa8a74b645f7f8b9c611afa1df8c6b523',1,'mcuxClEcc_PointMult_Param_t']]], + ['pprecg',['pPrecG',['../a00985.html#ae5ba73e49b3346a860000f13d05bfbf0',1,'mcuxClEcc_Verify_Param_t']]], + ['pprivatekey',['pPrivateKey',['../a00977.html#a48dad4664822a37f78c78eca1e660a26',1,'mcuxClEcc_KeyGen_Param_t::pPrivateKey()'],['../a00981.html#a0e61b674ac7f46c4157397535d97ce81',1,'mcuxClEcc_Sign_Param_t::pPrivateKey()']]], + ['pprot',['pprot',['../a01045.html#ac5b11ab2a0744e13303e920bee052f5b',1,'mcuxClEls_HwState_t']]], + ['ppublickey',['pPublicKey',['../a00977.html#a96680cb90b6901598b686b38edac1264',1,'mcuxClEcc_KeyGen_Param_t::pPublicKey()'],['../a00985.html#a2db1a83966c659495b7bca80d7b5ab25',1,'mcuxClEcc_Verify_Param_t::pPublicKey()']]], + ['pqinv',['pQInv',['../a01273.html#aa9188b106fa0b275218f8dc04fd9fa79',1,'mcuxClRsa_Key']]], + ['presult',['pResult',['../a00989.html#a6bf3d35fa5651ee8eacd77d9ce1d97bf',1,'mcuxClEcc_PointMult_Param_t']]], + ['prngready',['prngready',['../a01045.html#afbd164dd41b80e5a24310b6dac33cf79',1,'mcuxClEls_HwState_t']]], + ['pscalar',['pScalar',['../a00989.html#a661018eb3da69cf8aa41f08690abc10a',1,'mcuxClEcc_PointMult_Param_t']]], + ['psignature',['pSignature',['../a00981.html#ae25d26ef489ff1614a0a6ab6abe9fc97',1,'mcuxClEcc_Sign_Param_t::pSignature()'],['../a00985.html#ac9477410362aebdb892fdf382864342c',1,'mcuxClEcc_Verify_Param_t::pSignature()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/all_f.html b/components/els_pkc/doc/mcxn/html/search/all_f.html new file mode 100644 index 000000000..f6997fa5f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_f.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/all_f.js b/components/els_pkc/doc/mcxn/html/search/all_f.js new file mode 100644 index 000000000..f78373c20 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/all_f.js @@ -0,0 +1,20 @@ +var searchData= +[ + ['random_20interfaces',['Random interfaces',['../a00835.html',1,'']]], + ['random_20interfaces',['Random interfaces',['../a00837.html',1,'']]], + ['random_20patch_5fmode_20api',['Random PATCH_MODE API',['../a00834.html',1,'']]], + ['random_20test_5fmode_20api',['Random TEST_MODE API',['../a00836.html',1,'']]], + ['reset',['reset',['../a01105.html#ae72c778e615b7e6aa4e73eb242beb354',1,'mcuxClEls_CommandCrcConfig_t']]], + ['revf',['revf',['../a01117.html#aa75bf5c0b29ee02a16ca1b31e3300b0f',1,'mcuxClEls_EccSignOption_t::revf()'],['../a01129.html#afbf76f7ebcfc43ca99708cd1064a651a',1,'mcuxClEls_EccVerifyOption_t::revf()'],['../a01141.html#a7e2c0f35b5f6904c1a232f3552cb185f',1,'mcuxClEls_EccKeyGenOption_t::revf()'],['../a01153.html#a2a46aaff0c4f6f2cfa19b302ba713b43',1,'mcuxClEls_EccKeyExchOption_t::revf()'],['../a01225.html#aa699b2cfb2fc82dcbc25d833e09d442e',1,'mcuxClEls_KeyImportOption_t::revf()']]], + ['revision',['revision',['../a01033.html#a11c1bba1b577058ea774f9fb51dfd449',1,'mcuxClEls_HwVersion_t']]], + ['rng_5fpatch_5ffunction',['RNG_Patch_function',['../a00149.html#af28f6bb34479e4b2fe6b40fa868ee71b',1,'mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c']]], + ['rsa_5fkey_5fbit_5flength',['RSA_KEY_BIT_LENGTH',['../a00158.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_sign_NoEncode_example.c']]], + ['rsa_5fkey_5fbyte_5flength',['RSA_KEY_BYTE_LENGTH',['../a00158.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_sign_NoEncode_example.c']]], + ['rsa_5fmessage_5fdigest_5flength',['RSA_MESSAGE_DIGEST_LENGTH',['../a00158.html#a5621c168ff2d53aa21bf267fa5f5d88c',1,'RSA_MESSAGE_DIGEST_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a5621c168ff2d53aa21bf267fa5f5d88c',1,'RSA_MESSAGE_DIGEST_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c']]], + ['rsa_5fpss_5fsalt_5flength',['RSA_PSS_SALT_LENGTH',['../a00158.html#aa130e86f5b203dd9bcd2b0daf72cc2d5',1,'RSA_PSS_SALT_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#aa130e86f5b203dd9bcd2b0daf72cc2d5',1,'RSA_PSS_SALT_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c']]], + ['rsa_5fpublic_5fexp_5fbyte_5flength',['RSA_PUBLIC_EXP_BYTE_LENGTH',['../a00158.html#a1318d0d378cd86d23dcf30d273a195a9',1,'mcuxClRsa_verify_pssverify_sha2_256_example.c']]], + ['rtf',['rtf',['../a01285.html#ab1b8f498d45832cba336165e6761ce0d',1,'mcuxClSession_Descriptor']]], + ['rtfdrvdat',['rtfdrvdat',['../a01201.html#a7830e4ca489dcbca0e0b535e0979f5cc',1,'mcuxClEls_HkdfOption_t']]], + ['rtfoe',['rtfoe',['../a01165.html#a8c09f754695c9adc3ffe482375fc5f36',1,'mcuxClEls_HashOption_t']]], + ['rtfupd',['rtfupd',['../a01165.html#a1d91adca6cd4e274287063d2ff8d1884',1,'mcuxClEls_HashOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/classes_0.html b/components/els_pkc/doc/mcxn/html/search/classes_0.html new file mode 100644 index 000000000..b3c6ec6af --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/classes_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/classes_0.js b/components/els_pkc/doc/mcxn/html/search/classes_0.js new file mode 100644 index 000000000..5695d9050 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/classes_0.js @@ -0,0 +1,40 @@ +var searchData= +[ + ['mcuxclecc_5fdomainparam_5ft',['mcuxClEcc_DomainParam_t',['../a00973.html',1,'']]], + ['mcuxclecc_5fkeygen_5fparam_5ft',['mcuxClEcc_KeyGen_Param_t',['../a00977.html',1,'']]], + ['mcuxclecc_5fpointmult_5fparam_5ft',['mcuxClEcc_PointMult_Param_t',['../a00989.html',1,'']]], + ['mcuxclecc_5fsign_5fparam_5ft',['mcuxClEcc_Sign_Param_t',['../a00981.html',1,'']]], + ['mcuxclecc_5fverify_5fparam_5ft',['mcuxClEcc_Verify_Param_t',['../a00985.html',1,'']]], + ['mcuxclecc_5fweier_5fbasicdomainparams_5ft',['mcuxClEcc_Weier_BasicDomainParams_t',['../a00993.html',1,'']]], + ['mcuxclels_5faeadoption_5ft',['mcuxClEls_AeadOption_t',['../a00997.html',1,'']]], + ['mcuxclels_5fcipheroption_5ft',['mcuxClEls_CipherOption_t',['../a01009.html',1,'']]], + ['mcuxclels_5fckdfoption_5ft',['mcuxClEls_CkdfOption_t',['../a01189.html',1,'']]], + ['mcuxclels_5fcmacoption_5ft',['mcuxClEls_CmacOption_t',['../a01021.html',1,'']]], + ['mcuxclels_5fcommandcrcconfig_5ft',['mcuxClEls_CommandCrcConfig_t',['../a01105.html',1,'']]], + ['mcuxclels_5fecckeyexchoption_5ft',['mcuxClEls_EccKeyExchOption_t',['../a01153.html',1,'']]], + ['mcuxclels_5fecckeygenoption_5ft',['mcuxClEls_EccKeyGenOption_t',['../a01141.html',1,'']]], + ['mcuxclels_5feccsignoption_5ft',['mcuxClEls_EccSignOption_t',['../a01117.html',1,'']]], + ['mcuxclels_5feccverifyoption_5ft',['mcuxClEls_EccVerifyOption_t',['../a01129.html',1,'']]], + ['mcuxclels_5fhashoption_5ft',['mcuxClEls_HashOption_t',['../a01165.html',1,'']]], + ['mcuxclels_5fhkdfoption_5ft',['mcuxClEls_HkdfOption_t',['../a01201.html',1,'']]], + ['mcuxclels_5fhmacoption_5ft',['mcuxClEls_HmacOption_t',['../a01177.html',1,'']]], + ['mcuxclels_5fhwconfig_5ft',['mcuxClEls_HwConfig_t',['../a01093.html',1,'']]], + ['mcuxclels_5fhwstate_5ft',['mcuxClEls_HwState_t',['../a01045.html',1,'']]], + ['mcuxclels_5fhwversion_5ft',['mcuxClEls_HwVersion_t',['../a01033.html',1,'']]], + ['mcuxclels_5finterruptoptionen_5ft',['mcuxClEls_InterruptOptionEn_t',['../a01057.html',1,'']]], + ['mcuxclels_5finterruptoptionrst_5ft',['mcuxClEls_InterruptOptionRst_t',['../a01069.html',1,'']]], + ['mcuxclels_5finterruptoptionset_5ft',['mcuxClEls_InterruptOptionSet_t',['../a01081.html',1,'']]], + ['mcuxclels_5fkeyimportoption_5ft',['mcuxClEls_KeyImportOption_t',['../a01225.html',1,'']]], + ['mcuxclels_5fkeyprop_5ft',['mcuxClEls_KeyProp_t',['../a01237.html',1,'']]], + ['mcuxclels_5ftlsoption_5ft',['mcuxClEls_TlsOption_t',['../a01213.html',1,'']]], + ['mcuxcloscca_5fmpint_5ft',['mcuxClOscca_MPInt_t',['../a01253.html',1,'']]], + ['mcuxcloscca_5fscratchpad_5ft',['mcuxClOscca_ScratchPad_t',['../a01249.html',1,'']]], + ['mcuxclosccapkc_5fstate_5ft',['mcuxClOsccaPkc_State_t',['../a01257.html',1,'']]], + ['mcuxclpkc_5fstate_5ft',['mcuxClPkc_State_t',['../a01261.html',1,'']]], + ['mcuxclrandom_5fconfig',['mcuxClRandom_Config',['../a01265.html',1,'']]], + ['mcuxclrsa_5fkey',['mcuxClRsa_Key',['../a01273.html',1,'']]], + ['mcuxclrsa_5fkeyentry_5ft',['mcuxClRsa_KeyEntry_t',['../a01269.html',1,'']]], + ['mcuxclsession_5fdescriptor',['mcuxClSession_Descriptor',['../a01285.html',1,'']]], + ['mcuxclsession_5fsecuritycontext',['mcuxClSession_SecurityContext',['../a01281.html',1,'']]], + ['mcuxclsession_5fworkarea',['mcuxClSession_WorkArea',['../a01277.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/close.png b/components/els_pkc/doc/mcxn/html/search/close.png new file mode 100644 index 0000000000000000000000000000000000000000..9342d3dfeea7b7c4ee610987e717804b5a42ceb9 GIT binary patch literal 273 zcmV+s0q*{ZP)4(RlMby96)VwnbG{ zbe&}^BDn7x>$<{ck4zAK-=nT;=hHG)kmplIF${xqm8db3oX6wT3bvp`TE@m0cg;b) zBuSL}5?N7O(iZLdAlz@)b)Rd~DnSsSX&P5qC`XwuFwcAYLC+d2>+1(8on;wpt8QIC X2MT$R4iQDd00000NkvXXu0mjfia~GN literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/search/defines_0.html b/components/els_pkc/doc/mcxn/html/search/defines_0.html new file mode 100644 index 000000000..dbe0642ef --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/defines_0.js b/components/els_pkc/doc/mcxn/html/search/defines_0.js new file mode 100644 index 000000000..9e0c3921a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_0.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['exit_5fcode_5ferror',['EXIT_CODE_ERROR',['../a00173.html#a1feeb5aa091fe94feea015623eeb53b7',1,'EXIT_CODE_ERROR(): data_invariant_memory_compare.c'],['../a00176.html#a1feeb5aa091fe94feea015623eeb53b7',1,'EXIT_CODE_ERROR(): data_invariant_memory_copy.c']]], + ['exit_5fcode_5fok',['EXIT_CODE_OK',['../a00173.html#ae6032b4b9390cdf8886f3b02ab488383',1,'EXIT_CODE_OK(): data_invariant_memory_compare.c'],['../a00176.html#ae6032b4b9390cdf8886f3b02ab488383',1,'EXIT_CODE_OK(): data_invariant_memory_copy.c']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/defines_1.html b/components/els_pkc/doc/mcxn/html/search/defines_1.html new file mode 100644 index 000000000..7af932407 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/defines_1.js b/components/els_pkc/doc/mcxn/html/search/defines_1.js new file mode 100644 index 000000000..828f58c94 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_1.js @@ -0,0 +1,20 @@ +var searchData= +[ + ['mcux_5fcssl_5ffp_5ffunction_5fcall_5fvoid_5fimpl',['MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL',['../a00614.html#aac90557cb39d20ea0c0fda3985497b45',1,'mcuxCsslFlowProtection_SecureCounter_Local.h']]], + ['mcux_5fcssl_5ffp_5ffunction_5fpointer_5fimpl',['MCUX_CSSL_FP_FUNCTION_POINTER_IMPL',['../a00611.html#a7d3ca21c8f547090d91d2d2b77607f45',1,'mcuxCsslFlowProtection_SecureCounter_Common.h']]], + ['mcuxcl_5fapi',['MCUXCL_API',['../a00200.html#a3a2aa1bfb4cd2f30cd208b1f53fd3238',1,'mcuxCl_clns.h']]], + ['mcuxcl_5fversion',['MCUXCL_VERSION',['../a00200.html#aaac021cf1e464db8ec89a2313860577b',1,'mcuxCl_clns.h']]], + ['mcuxcl_5fversion_5fmax_5fsize',['MCUXCL_VERSION_MAX_SIZE',['../a00200.html#aac49d4488517875c56358012b911da08',1,'mcuxCl_clns.h']]], + ['mcuxclcss_5faead_5ffinalize_5fasync',['mcuxClCss_Aead_Finalize_Async',['../a00326.html#acd4f33dfe8b92796f5d88070e2cb45ec',1,'mcuxClEls_mapping.h']]], + ['mcuxclcss_5faeadoption_5ft',['mcuxClCss_AeadOption_t',['../a00326.html#adbc7825ddeb3a5325134b21ba92d895c',1,'mcuxClEls_mapping.h']]], + ['mcuxclcss_5fapi',['MCUXCLCSS_API',['../a00326.html#a943265c1ad7bb3d4163f108994aa7958',1,'mcuxClEls_mapping.h']]], + ['mcuxclhash_5fcompare_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a8e985e955759e3f5f6fb1d11c3901e2c',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fcompute_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a8b3af117f171a613124593df58ada62a',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fcontext_5fsize',['MCUXCLHASH_CONTEXT_SIZE',['../a00362.html#a42253ef03c357fbdcc8a0c502f34c4f3',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5ffinish_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a63da111398b07963ed1a77da6c97a64d',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5finit_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE',['../a00362.html#a8434a263faa18d7d5f1db037eca3a130',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fmax_5fcpu_5fwa_5fbuffer_5fsize',['MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE',['../a00362.html#a8c70073fba8e9b6bdd946ca99e3dfcf4',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fprocess_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#ac7007695fab49af24194295d81f80b56',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclhash_5fverify_5fcpu_5fwa_5fbuffer_5fsize_5fmax',['MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX',['../a00362.html#a59a048780405bb5b38b256cf689bdf80',1,'mcuxClHash_MemoryConsumption.h']]], + ['mcuxclosccapkc_5fpkcpackargs2',['MCUXCLOSCCAPKC_PKCPACKARGS2',['../a00494.html#aba1b2e7258d3f4a2080b728cc7f91eaf',1,'mcuxClOsccaPkc_Types.h']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/defines_2.html b/components/els_pkc/doc/mcxn/html/search/defines_2.html new file mode 100644 index 000000000..462922115 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/defines_2.js b/components/els_pkc/doc/mcxn/html/search/defines_2.js new file mode 100644 index 000000000..c955c9349 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/defines_2.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['rsa_5fkey_5fbit_5flength',['RSA_KEY_BIT_LENGTH',['../a00158.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#af6c7fb8ff2076d86e2d0ed1c48fdeabe',1,'RSA_KEY_BIT_LENGTH(): mcuxClRsa_sign_NoEncode_example.c']]], + ['rsa_5fkey_5fbyte_5flength',['RSA_KEY_BYTE_LENGTH',['../a00158.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#a682e80cec7574ae978654511689ad090',1,'RSA_KEY_BYTE_LENGTH(): mcuxClRsa_sign_NoEncode_example.c']]], + ['rsa_5fmessage_5fdigest_5flength',['RSA_MESSAGE_DIGEST_LENGTH',['../a00158.html#a5621c168ff2d53aa21bf267fa5f5d88c',1,'RSA_MESSAGE_DIGEST_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a5621c168ff2d53aa21bf267fa5f5d88c',1,'RSA_MESSAGE_DIGEST_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c']]], + ['rsa_5fpss_5fsalt_5flength',['RSA_PSS_SALT_LENGTH',['../a00158.html#aa130e86f5b203dd9bcd2b0daf72cc2d5',1,'RSA_PSS_SALT_LENGTH(): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#aa130e86f5b203dd9bcd2b0daf72cc2d5',1,'RSA_PSS_SALT_LENGTH(): mcuxClRsa_sign_pss_sha2_256_example.c']]], + ['rsa_5fpublic_5fexp_5fbyte_5flength',['RSA_PUBLIC_EXP_BYTE_LENGTH',['../a00158.html#a1318d0d378cd86d23dcf30d273a195a9',1,'mcuxClRsa_verify_pssverify_sha2_256_example.c']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/files_0.html b/components/els_pkc/doc/mcxn/html/search/files_0.html new file mode 100644 index 000000000..40cd45543 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/files_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/files_0.js b/components/els_pkc/doc/mcxn/html/search/files_0.js new file mode 100644 index 000000000..ab7bc874c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/files_0.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['data_5finvariant_5fmemory_5fcompare_2ec',['data_invariant_memory_compare.c',['../a00173.html',1,'']]], + ['data_5finvariant_5fmemory_5fcopy_2ec',['data_invariant_memory_copy.c',['../a00176.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/files_1.html b/components/els_pkc/doc/mcxn/html/search/files_1.html new file mode 100644 index 000000000..646d1f4cc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/files_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/files_1.js b/components/els_pkc/doc/mcxn/html/search/files_1.js new file mode 100644 index 000000000..41103844a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/files_1.js @@ -0,0 +1,166 @@ +var searchData= +[ + ['mcuxcl_5fclns_2eh',['mcuxCl_clns.h',['../a00200.html',1,'']]], + ['mcuxclaead_2eh',['mcuxClAead.h',['../a00203.html',1,'']]], + ['mcuxclaead_5fconstants_2eh',['mcuxClAead_Constants.h',['../a00206.html',1,'']]], + ['mcuxclaead_5ffunctions_2eh',['mcuxClAead_Functions.h',['../a00209.html',1,'']]], + ['mcuxclaead_5ftypes_2eh',['mcuxClAead_Types.h',['../a00212.html',1,'']]], + ['mcuxclaeadmodes_5fmemoryconsumption_2eh',['mcuxClAeadModes_MemoryConsumption.h',['../a00218.html',1,'']]], + ['mcuxclaeadmodes_5fmodes_2eh',['mcuxClAeadModes_Modes.h',['../a00221.html',1,'']]], + ['mcuxclaeadmodes_5fmultipart_5fels_5fccm_5fexample_2ec',['mcuxClAeadModes_Multipart_Els_Ccm_Example.c',['../a00035.html',1,'']]], + ['mcuxclaeadmodes_5foneshot_5fels_5fccm_5fexample_2ec',['mcuxClAeadModes_Oneshot_Els_Ccm_Example.c',['../a00038.html',1,'']]], + ['mcuxclaeadmodes_5foneshot_5fels_5fgcm_5fexample_2ec',['mcuxClAeadModes_Oneshot_Els_Gcm_Example.c',['../a00041.html',1,'']]], + ['mcuxclaes_2eh',['mcuxClAes.h',['../a00224.html',1,'']]], + ['mcuxclaes_5fkeytypes_2eh',['mcuxClAes_KeyTypes.h',['../a00230.html',1,'']]], + ['mcuxclcipher_2eh',['mcuxClCipher.h',['../a00233.html',1,'']]], + ['mcuxclcipher_5fconstants_2eh',['mcuxClCipher_Constants.h',['../a00236.html',1,'']]], + ['mcuxclcipher_5ffunctions_2eh',['mcuxClCipher_Functions.h',['../a00239.html',1,'']]], + ['mcuxclcipher_5ftypes_2eh',['mcuxClCipher_Types.h',['../a00242.html',1,'']]], + ['mcuxclciphermodes_5fmodes_2eh',['mcuxClCipherModes_Modes.h',['../a00251.html',1,'']]], + ['mcuxclcore_5ffunctionidentifiers_2eh',['mcuxClCore_FunctionIdentifiers.h',['../a00260.html',1,'']]], + ['mcuxclecc_2eh',['mcuxClEcc.h',['../a00269.html',1,'']]], + ['mcuxclecc_5fconstants_2eh',['mcuxClEcc_Constants.h',['../a00272.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519_example.c',['../a00089.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519ctx_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519ctx_example.c',['../a00083.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519ph_5fexample_2ec',['mcuxClEcc_EdDSA_Ed25519ph_example.c',['../a00086.html',1,'']]], + ['mcuxclecc_5feddsa_5fgeneratesignature_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c',['../a00095.html',1,'']]], + ['mcuxclecc_5feddsa_5fverifysignature_5fed25519_5fexample_2ec',['mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c',['../a00092.html',1,'']]], + ['mcuxclecc_5ffunctions_2eh',['mcuxClEcc_Functions.h',['../a00275.html',1,'']]], + ['mcuxclecc_5fkeymechanisms_2eh',['mcuxClEcc_KeyMechanisms.h',['../a00278.html',1,'']]], + ['mcuxclecc_5fmemoryconsumption_2eh',['mcuxClEcc_MemoryConsumption.h',['../a00281.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve25519_5fexample_2ec',['mcuxClEcc_Mont_Curve25519_example.c',['../a00074.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve448_5fexample_2ec',['mcuxClEcc_Mont_Curve448_example.c',['../a00077.html',1,'']]], + ['mcuxclecc_5fparametersizes_2eh',['mcuxClEcc_ParameterSizes.h',['../a00284.html',1,'']]], + ['mcuxclecc_5ftypes_2eh',['mcuxClEcc_Types.h',['../a00287.html',1,'']]], + ['mcuxclecc_5fweierecc_2eh',['mcuxClEcc_WeierECC.h',['../a00290.html',1,'']]], + ['mcuxclecc_5fweierecc_5fcustomeccweiertype_5fbn256_5fexample_2ec',['mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c',['../a00080.html',1,'']]], + ['mcuxclels_2eh',['mcuxClEls.h',['../a00293.html',1,'']]], + ['mcuxclels_5faead_2eh',['mcuxClEls_Aead.h',['../a00296.html',1,'']]], + ['mcuxclels_5fcipher_2eh',['mcuxClEls_Cipher.h',['../a00299.html',1,'']]], + ['mcuxclels_5fcipher_5faes128_5fcbc_5fencrypt_5fexample_2ec',['mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c',['../a00005.html',1,'']]], + ['mcuxclels_5fcipher_5faes128_5fecb_5fencrypt_5fexample_2ec',['mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c',['../a00002.html',1,'']]], + ['mcuxclels_5fcmac_2eh',['mcuxClEls_Cmac.h',['../a00302.html',1,'']]], + ['mcuxclels_5fcommon_2eh',['mcuxClEls_Common.h',['../a00305.html',1,'']]], + ['mcuxclels_5fcommon_5fget_5finfo_5fexample_2ec',['mcuxClEls_Common_Get_Info_example.c',['../a00011.html',1,'']]], + ['mcuxclels_5fcrc_2eh',['mcuxClEls_Crc.h',['../a00308.html',1,'']]], + ['mcuxclels_5fecc_2eh',['mcuxClEls_Ecc.h',['../a00311.html',1,'']]], + ['mcuxclels_5fecc_5fkeygen_5fsign_5fverify_5fexample_2ec',['mcuxClEls_Ecc_Keygen_Sign_Verify_example.c',['../a00008.html',1,'']]], + ['mcuxclels_5fhash_2eh',['mcuxClEls_Hash.h',['../a00314.html',1,'']]], + ['mcuxclels_5fhash_5fsha224_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha224_One_Block_example.c',['../a00014.html',1,'']]], + ['mcuxclels_5fhash_5fsha256_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha256_One_Block_example.c',['../a00017.html',1,'']]], + ['mcuxclels_5fhash_5fsha384_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha384_One_Block_example.c',['../a00020.html',1,'']]], + ['mcuxclels_5fhash_5fsha512_5fone_5fblock_5fexample_2ec',['mcuxClEls_Hash_Sha512_One_Block_example.c',['../a00023.html',1,'']]], + ['mcuxclels_5fhmac_2eh',['mcuxClEls_Hmac.h',['../a00317.html',1,'']]], + ['mcuxclels_5fkdf_2eh',['mcuxClEls_Kdf.h',['../a00320.html',1,'']]], + ['mcuxclels_5fkey_5fimport_5fpuk_5fder_5fexample_2ec',['mcuxClEls_Key_Import_Puk_DER_example.c',['../a00032.html',1,'']]], + ['mcuxclels_5fkeymanagement_2eh',['mcuxClEls_KeyManagement.h',['../a00323.html',1,'']]], + ['mcuxclels_5fmapping_2eh',['mcuxClEls_mapping.h',['../a00326.html',1,'']]], + ['mcuxclels_5frng_2eh',['mcuxClEls_Rng.h',['../a00329.html',1,'']]], + ['mcuxclels_5frng_5fprng_5fget_5frandom_5fexample_2ec',['mcuxClEls_Rng_Prng_Get_Random_example.c',['../a00026.html',1,'']]], + ['mcuxclels_5ftls_5fmaster_5fkey_5fsession_5fkeys_5fexample_2ec',['mcuxClEls_Tls_Master_Key_Session_Keys_example.c',['../a00029.html',1,'']]], + ['mcuxclels_5ftypes_2eh',['mcuxClEls_Types.h',['../a00332.html',1,'']]], + ['mcuxclhash_2eh',['mcuxClHash.h',['../a00353.html',1,'']]], + ['mcuxclhash_5fconstants_2eh',['mcuxClHash_Constants.h',['../a00356.html',1,'']]], + ['mcuxclhash_5ffunctions_2eh',['mcuxClHash_Functions.h',['../a00359.html',1,'']]], + ['mcuxclhash_5fmemoryconsumption_2eh',['mcuxClHash_MemoryConsumption.h',['../a00362.html',1,'']]], + ['mcuxclhash_5ftypes_2eh',['mcuxClHash_Types.h',['../a00365.html',1,'']]], + ['mcuxclhashmodes_5falgorithms_2eh',['mcuxClHashModes_Algorithms.h',['../a00371.html',1,'']]], + ['mcuxclhashmodes_5fconstants_2eh',['mcuxClHashModes_Constants.h',['../a00374.html',1,'']]], + ['mcuxclhashmodes_5fmemoryconsumption_2eh',['mcuxClHashModes_MemoryConsumption.h',['../a00380.html',1,'']]], + ['mcuxclhmac_5fconstants_2eh',['mcuxClHmac_Constants.h',['../a00386.html',1,'']]], + ['mcuxclhmac_5ffunctions_2eh',['mcuxClHmac_Functions.h',['../a00389.html',1,'']]], + ['mcuxclhmac_5fkeytypes_2eh',['mcuxClHmac_KeyTypes.h',['../a00392.html',1,'']]], + ['mcuxclhmac_5fmemoryconsumption_2eh',['mcuxClHmac_MemoryConsumption.h',['../a00395.html',1,'']]], + ['mcuxclhmac_5fmodes_2eh',['mcuxClHmac_Modes.h',['../a00398.html',1,'']]], + ['mcuxclkey_2eh',['mcuxClKey.h',['../a00401.html',1,'']]], + ['mcuxclkey_5fconstants_2eh',['mcuxClKey_Constants.h',['../a00404.html',1,'']]], + ['mcuxclkey_5fexample_2ec',['mcuxClKey_example.c',['../a00116.html',1,'']]], + ['mcuxclkey_5ffunctions_2eh',['mcuxClKey_Functions.h',['../a00407.html',1,'']]], + ['mcuxclkey_5fmemoryconsumption_2eh',['mcuxClKey_MemoryConsumption.h',['../a00410.html',1,'']]], + ['mcuxclkey_5ftypes_2eh',['mcuxClKey_Types.h',['../a00416.html',1,'']]], + ['mcuxclmac_2eh',['mcuxClMac.h',['../a00419.html',1,'']]], + ['mcuxclmac_5fconstants_2eh',['mcuxClMac_Constants.h',['../a00422.html',1,'']]], + ['mcuxclmac_5ffunctions_2eh',['mcuxClMac_Functions.h',['../a00425.html',1,'']]], + ['mcuxclmac_5ftypes_2eh',['mcuxClMac_Types.h',['../a00428.html',1,'']]], + ['mcuxclmacmodes_5fcmac_5foneshot_5fexample_2ec',['mcuxClMacModes_cmac_oneshot_example.c',['../a00119.html',1,'']]], + ['mcuxclmacmodes_5fconstants_2eh',['mcuxClMacModes_Constants.h',['../a00434.html',1,'']]], + ['mcuxclmacmodes_5ffunctions_2eh',['mcuxClMacModes_Functions.h',['../a00437.html',1,'']]], + ['mcuxclmacmodes_5fmemoryconsumption_2eh',['mcuxClMacModes_MemoryConsumption.h',['../a00440.html',1,'']]], + ['mcuxclmath_2eh',['mcuxClMath.h',['../a00446.html',1,'']]], + ['mcuxclmath_5ffunctions_2eh',['mcuxClMath_Functions.h',['../a00449.html',1,'']]], + ['mcuxclmemory_2eh',['mcuxClMemory.h',['../a00455.html',1,'']]], + ['mcuxclmemory_5fclear_2eh',['mcuxClMemory_Clear.h',['../a00458.html',1,'']]], + ['mcuxclmemory_5fcopy_2eh',['mcuxClMemory_Copy.h',['../a00461.html',1,'']]], + ['mcuxclmemory_5fcopy_5freversed_2eh',['mcuxClMemory_Copy_Reversed.h',['../a00464.html',1,'']]], + ['mcuxclmemory_5fendianness_2eh',['mcuxClMemory_Endianness.h',['../a00467.html',1,'']]], + ['mcuxclmemory_5fset_2eh',['mcuxClMemory_Set.h',['../a00470.html',1,'']]], + ['mcuxclmemory_5ftypes_2eh',['mcuxClMemory_Types.h',['../a00473.html',1,'']]], + ['mcuxcloscca_5ffunctionidentifiers_2eh',['mcuxClOscca_FunctionIdentifiers.h',['../a00476.html',1,'']]], + ['mcuxcloscca_5fmemory_2eh',['mcuxClOscca_Memory.h',['../a00479.html',1,'']]], + ['mcuxcloscca_5fplatformtypes_2eh',['mcuxClOscca_PlatformTypes.h',['../a00482.html',1,'']]], + ['mcuxcloscca_5ftypes_2eh',['mcuxClOscca_Types.h',['../a00485.html',1,'']]], + ['mcuxclosccapkc_2eh',['mcuxClOsccaPkc.h',['../a00488.html',1,'']]], + ['mcuxclosccapkc_5ffunctions_2eh',['mcuxClOsccaPkc_Functions.h',['../a00491.html',1,'']]], + ['mcuxclosccapkc_5ftypes_2eh',['mcuxClOsccaPkc_Types.h',['../a00494.html',1,'']]], + ['mcuxclosccasm3_2eh',['mcuxClOsccaSm3.h',['../a00497.html',1,'']]], + ['mcuxclosccasm3_5falgorithms_2eh',['mcuxClOsccaSm3_Algorithms.h',['../a00500.html',1,'']]], + ['mcuxclosccasm3_5fconstants_2eh',['mcuxClOsccaSm3_Constants.h',['../a00503.html',1,'']]], + ['mcuxclosccasm3_5fmemoryconsumption_2eh',['mcuxClOsccaSm3_MemoryConsumption.h',['../a00506.html',1,'']]], + ['mcuxclpadding_2eh',['mcuxClPadding.h',['../a00509.html',1,'']]], + ['mcuxclpadding_5fconstants_2eh',['mcuxClPadding_Constants.h',['../a00512.html',1,'']]], + ['mcuxclpadding_5ftypes_2eh',['mcuxClPadding_Types.h',['../a00515.html',1,'']]], + ['mcuxclpkc_2eh',['mcuxClPkc.h',['../a00518.html',1,'']]], + ['mcuxclpkc_5ffunctions_2eh',['mcuxClPkc_Functions.h',['../a00521.html',1,'']]], + ['mcuxclpkc_5ftypes_2eh',['mcuxClPkc_Types.h',['../a00524.html',1,'']]], + ['mcuxclrandom_2eh',['mcuxClRandom.h',['../a00527.html',1,'']]], + ['mcuxclrandom_5fconstants_2eh',['mcuxClRandom_Constants.h',['../a00530.html',1,'']]], + ['mcuxclrandom_5ffunctions_2eh',['mcuxClRandom_Functions.h',['../a00533.html',1,'']]], + ['mcuxclrandom_5ftypes_2eh',['mcuxClRandom_Types.h',['../a00536.html',1,'']]], + ['mcuxclrandommodes_2eh',['mcuxClRandomModes.h',['../a00539.html',1,'']]], + ['mcuxclrandommodes_5fconstants_2eh',['mcuxClRandomModes_Constants.h',['../a00542.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fdrg3_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c',['../a00140.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fdrg4_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c',['../a00146.html',1,'']]], + ['mcuxclrandommodes_5fctrdrbg_5faes256_5fels_5fexample_2ec',['mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c',['../a00134.html',1,'']]], + ['mcuxclrandommodes_5fdifferent_5fsessions_5fexample_2ec',['mcuxClRandomModes_Different_Sessions_example.c',['../a00143.html',1,'']]], + ['mcuxclrandommodes_5fels_5fexample_2ec',['mcuxClRandomModes_ELS_example.c',['../a00137.html',1,'']]], + ['mcuxclrandommodes_5fmemoryconsumption_2eh',['mcuxClRandomModes_MemoryConsumption.h',['../a00551.html',1,'']]], + ['mcuxclrandommodes_5fpatchmode_5fctrdrbg_5faes256_5fdrg3_5fexample_2ec',['mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c',['../a00149.html',1,'']]], + ['mcuxclrandommodes_5ftestmode_5fctrdrbg_5faes256_5fdrg4_5fexample_2ec',['mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c',['../a00155.html',1,'']]], + ['mcuxclrandommodes_5ftestmode_5fctrdrbg_5faes256_5fptg3_5fexample_2ec',['mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c',['../a00152.html',1,'']]], + ['mcuxclrsa_2eh',['mcuxClRsa.h',['../a00554.html',1,'']]], + ['mcuxclrsa_5fconstants_2eh',['mcuxClRsa_Constants.h',['../a00557.html',1,'']]], + ['mcuxclrsa_5ffunctions_2eh',['mcuxClRsa_Functions.h',['../a00560.html',1,'']]], + ['mcuxclrsa_5fmemoryconsumption_2eh',['mcuxClRsa_MemoryConsumption.h',['../a00563.html',1,'']]], + ['mcuxclrsa_5fsign_5fnoencode_5fexample_2ec',['mcuxClRsa_sign_NoEncode_example.c',['../a00167.html',1,'']]], + ['mcuxclrsa_5fsign_5fpss_5fsha2_5f256_5fexample_2ec',['mcuxClRsa_sign_pss_sha2_256_example.c',['../a00161.html',1,'']]], + ['mcuxclrsa_5ftypes_2eh',['mcuxClRsa_Types.h',['../a00566.html',1,'']]], + ['mcuxclrsa_5fverify_5fnoverify_5fexample_2ec',['mcuxClRsa_verify_NoVerify_example.c',['../a00164.html',1,'']]], + ['mcuxclrsa_5fverify_5fpssverify_5fsha2_5f256_5fexample_2ec',['mcuxClRsa_verify_pssverify_sha2_256_example.c',['../a00158.html',1,'']]], + ['mcuxclsession_2eh',['mcuxClSession.h',['../a00569.html',1,'']]], + ['mcuxclsession_5ffunctions_2eh',['mcuxClSession_Functions.h',['../a00572.html',1,'']]], + ['mcuxclsession_5fmemoryconsumption_2eh',['mcuxClSession_MemoryConsumption.h',['../a00575.html',1,'']]], + ['mcuxclsession_5ftypes_2eh',['mcuxClSession_Types.h',['../a00578.html',1,'']]], + ['mcuxcsslcpreprocessor_2eh',['mcuxCsslCPreProcessor.h',['../a00584.html',1,'']]], + ['mcuxcssldataintegrity_2eh',['mcuxCsslDataIntegrity.h',['../a00587.html',1,'']]], + ['mcuxcssldataintegrity_5fcfg_2eh',['mcuxCsslDataIntegrity_Cfg.h',['../a00590.html',1,'']]], + ['mcuxcssldataintegrity_5fimpl_2eh',['mcuxCsslDataIntegrity_Impl.h',['../a00593.html',1,'']]], + ['mcuxcssldataintegrity_5fnone_2eh',['mcuxCsslDataIntegrity_None.h',['../a00596.html',1,'']]], + ['mcuxcsslflowprotection_2eh',['mcuxCsslFlowProtection.h',['../a00599.html',1,'']]], + ['mcuxcsslflowprotection_5fcfg_2eh',['mcuxCsslFlowProtection_Cfg.h',['../a00602.html',1,'']]], + ['mcuxcsslflowprotection_5ffunctionidentifiers_2eh',['mcuxCsslFlowProtection_FunctionIdentifiers.h',['../a00605.html',1,'']]], + ['mcuxcsslflowprotection_5fimpl_2eh',['mcuxCsslFlowProtection_Impl.h',['../a00608.html',1,'']]], + ['mcuxcsslflowprotection_5fsecurecounter_5fcommon_2eh',['mcuxCsslFlowProtection_SecureCounter_Common.h',['../a00611.html',1,'']]], + ['mcuxcsslflowprotection_5fsecurecounter_5flocal_2eh',['mcuxCsslFlowProtection_SecureCounter_Local.h',['../a00614.html',1,'']]], + ['mcuxcsslmemory_2eh',['mcuxCsslMemory.h',['../a00617.html',1,'']]], + ['mcuxcsslmemory_5fclear_2eh',['mcuxCsslMemory_Clear.h',['../a00620.html',1,'']]], + ['mcuxcsslmemory_5fcompare_2eh',['mcuxCsslMemory_Compare.h',['../a00623.html',1,'']]], + ['mcuxcsslmemory_5fcopy_2eh',['mcuxCsslMemory_Copy.h',['../a00626.html',1,'']]], + ['mcuxcsslmemory_5fset_2eh',['mcuxCsslMemory_Set.h',['../a00629.html',1,'']]], + ['mcuxcsslmemory_5ftypes_2eh',['mcuxCsslMemory_Types.h',['../a00632.html',1,'']]], + ['mcuxcsslparamintegrity_2eh',['mcuxCsslParamIntegrity.h',['../a00635.html',1,'']]], + ['mcuxcsslsecurecounter_2eh',['mcuxCsslSecureCounter.h',['../a00638.html',1,'']]], + ['mcuxcsslsecurecounter_5fcfg_2eh',['mcuxCsslSecureCounter_Cfg.h',['../a00641.html',1,'']]], + ['mcuxcsslsecurecounter_5fimpl_2eh',['mcuxCsslSecureCounter_Impl.h',['../a00644.html',1,'']]], + ['mcuxcsslsecurecounter_5fnone_2eh',['mcuxCsslSecureCounter_None.h',['../a00647.html',1,'']]], + ['mcuxcsslsecurecounter_5fsw_5flocal_2eh',['mcuxCsslSecureCounter_SW_Local.h',['../a00650.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/functions_0.html b/components/els_pkc/doc/mcxn/html/search/functions_0.html new file mode 100644 index 000000000..bc73761f5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/functions_0.js b/components/els_pkc/doc/mcxn/html/search/functions_0.js new file mode 100644 index 000000000..1052303ec --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5f_5fattribute_5f_5f',['__attribute__',['../a00032.html#a3e0329840494bde2557d01ee51c9aa52',1,'__attribute__((aligned(4))): mcuxClEls_Key_Import_Puk_DER_example.c'],['../a00158.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#ac653ec70e8637a68edb49fd66e7e3edc',1,'__attribute__((aligned(4))): mcuxClRsa_sign_NoEncode_example.c']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/functions_1.html b/components/els_pkc/doc/mcxn/html/search/functions_1.html new file mode 100644 index 000000000..bfcf880be --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/functions_1.js b/components/els_pkc/doc/mcxn/html/search/functions_1.js new file mode 100644 index 000000000..29a2c40df --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_1.js @@ -0,0 +1,145 @@ +var searchData= +[ + ['mcux_5fcssl_5ffp_5ffunction_5fpointer',['MCUX_CSSL_FP_FUNCTION_POINTER',['../a00963.html#gaf821ec5ad694746ba28321b2bb802236',1,'MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcInitializeEngine_t, typedef void(*mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState)): mcuxClPkc_Functions.h'],['../a00963.html#ga4ad3a9a17b2090a8d761fcd9c9c86218',1,'MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcDeInitializeEngine_t, typedef void(*mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState)): mcuxClPkc_Functions.h']]], + ['mcuxcl_5fgetversion',['mcuxCl_GetVersion',['../a00200.html#a41e47552892b4e05c396de4ab626aaa2',1,'mcuxCl_clns.h']]], + ['mcuxclaead_5fcrypt',['mcuxClAead_crypt',['../a00664.html#gad0713168358588f9550468bf1ef7cfbb',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5ffinish',['mcuxClAead_finish',['../a00665.html#ga2b18aa6585e4d229d7ccfdd34f3f9dba',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5finit',['mcuxClAead_init',['../a00665.html#gaeb2451aba7d135f7af05e94f9b095fae',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fprocess',['mcuxClAead_process',['../a00665.html#gaa4af5201aaf549186bf80cbf4284f3d1',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fprocess_5fadata',['mcuxClAead_process_adata',['../a00665.html#ga40cbd731ba8874d971213fa03605736d',1,'mcuxClAead_Functions.h']]], + ['mcuxclaead_5fverify',['mcuxClAead_verify',['../a00665.html#gafb82bc41120d69281d0fbb719fb35d9d',1,'mcuxClAead_Functions.h']]], + ['mcuxclcipher_5fcrypt',['mcuxClCipher_crypt',['../a00239.html#a3bc78aed20c4d8fcf8606d46dd27bf12',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5ffinish',['mcuxClCipher_finish',['../a00239.html#a90ac41c7d96f333de0708126b0bce4be',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5finit',['mcuxClCipher_init',['../a00239.html#a3d0ee9a87aa371edeac7f361344aeb27',1,'mcuxClCipher_Functions.h']]], + ['mcuxclcipher_5fprocess',['mcuxClCipher_process',['../a00239.html#a1a5072096f7f82fbce313d414dbb438d',1,'mcuxClCipher_Functions.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypair',['mcuxClEcc_EdDSA_GenerateKeyPair',['../a00681.html#ga0ac2814cb9c8f4b8718a95d8c2ae2b85',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fgenerateprotocoldescriptor',['mcuxClEcc_EdDSA_GenerateProtocolDescriptor',['../a00681.html#ga54e3517cb9729321cdb4017b0fdc4485',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fgeneratesignature',['mcuxClEcc_EdDSA_GenerateSignature',['../a00681.html#ga0b9ad0b0aa3afccae32a14aeddf9d8fe',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5finitprivkeyinputmode',['mcuxClEcc_EdDSA_InitPrivKeyInputMode',['../a00681.html#ga78eaff72d9c8202b51c61c6668b9c3aa',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5feddsa_5fverifysignature',['mcuxClEcc_EdDSA_VerifySignature',['../a00681.html#ga514b29374472b14ad00e0e5ef3469c7f',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fkeygen',['mcuxClEcc_KeyGen',['../a00681.html#gabc728b0278908265f9923535391005dc',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fmont_5fdhkeyagreement',['mcuxClEcc_Mont_DhKeyAgreement',['../a00681.html#gaef77a1a80276b44da54c66a8d606f20d',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fmont_5fdhkeygeneration',['mcuxClEcc_Mont_DhKeyGeneration',['../a00681.html#ga71406ab7d35c51f12c01efcb73305196',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fpointmult',['mcuxClEcc_PointMult',['../a00681.html#gab199a221c61f252a0c755ab8d8a6a77c',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fsign',['mcuxClEcc_Sign',['../a00681.html#ga105ec4e9dc29573334f52979381686de',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fverify',['mcuxClEcc_Verify',['../a00681.html#ga80f15538ec3cb2d3bfa8dc2f2da86366',1,'mcuxClEcc_Functions.h']]], + ['mcuxclecc_5fweierecc_5fgeneratecustomkeytype',['mcuxClEcc_WeierECC_GenerateCustomKeyType',['../a00290.html#abd1f9ebda4a913d82eefe752ca54923b',1,'mcuxClEcc_WeierECC.h']]], + ['mcuxclecc_5fweierecc_5fgeneratedomainparams',['mcuxClEcc_WeierECC_GenerateDomainParams',['../a00290.html#a1deb22c96b88674a4513e56cdd2dfe3a',1,'mcuxClEcc_WeierECC.h']]], + ['mcuxclels_5faead_5ffinalize_5fasync',['mcuxClEls_Aead_Finalize_Async',['../a00693.html#gab2f0d1f82ce7537c78967ea2989a2054',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5finit_5fasync',['mcuxClEls_Aead_Init_Async',['../a00693.html#ga86bbde5d55c2e44102158ef7b802b819',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fpartialinit_5fasync',['mcuxClEls_Aead_PartialInit_Async',['../a00693.html#ga817b12c984eb2afcaad9aa3c2b75040c',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fupdateaad_5fasync',['mcuxClEls_Aead_UpdateAad_Async',['../a00693.html#gaa34534b5e5196e07cbcef7c858cc0ea9',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5faead_5fupdatedata_5fasync',['mcuxClEls_Aead_UpdateData_Async',['../a00693.html#ga7d5f1b08fbbcda07f881c274b0100c8b',1,'mcuxClEls_Aead.h']]], + ['mcuxclels_5fcipher_5fasync',['mcuxClEls_Cipher_Async',['../a00699.html#gad8b0506b0510f7dc6ef20fd488ee004b',1,'mcuxClEls_Cipher.h']]], + ['mcuxclels_5fckdf_5fsp800108_5fasync',['mcuxClEls_Ckdf_Sp800108_Async',['../a00752.html#ga4cf223def750c39f5c955fdfbe12bc8d',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fcmac_5fasync',['mcuxClEls_Cmac_Async',['../a00705.html#ga0cc7e60d184ae44edd8ac6376ecf2387',1,'mcuxClEls_Cmac.h']]], + ['mcuxclels_5fconfigurecommandcrc',['mcuxClEls_ConfigureCommandCRC',['../a00724.html#ga4aaabd203c6c81a042bc4f3739ae8408',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fdisable',['mcuxClEls_Disable',['../a00717.html#gacbf878536100314ce61081c54ea5ef9e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fecckeyexchange_5fasync',['mcuxClEls_EccKeyExchange_Async',['../a00734.html#ga39d6102bd9c792eb5a2e33af1f1830c3',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fecckeygen_5fasync',['mcuxClEls_EccKeyGen_Async',['../a00734.html#ga060362493427031ef51110b7c381a986',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5feccsign_5fasync',['mcuxClEls_EccSign_Async',['../a00734.html#ga96b17fadb9ee18906bb719e222908209',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5feccverify_5fasync',['mcuxClEls_EccVerify_Async',['../a00734.html#ga019a066eda05dab4955ed76e83d39b77',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5fenable_5fasync',['mcuxClEls_Enable_Async',['../a00717.html#ga6dbf394b38add1c6967dab368435b657',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetcommandcrc',['mcuxClEls_GetCommandCRC',['../a00724.html#gaf91caa2b1230676e9beedaa0eba442eb',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fgeterrorcode',['mcuxClEls_GetErrorCode',['../a00717.html#gaeb4fc2a3a1115489dcb9912f7160cb7f',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgeterrorlevel',['mcuxClEls_GetErrorLevel',['../a00717.html#ga896309eafc0aedbb5514ec4111b4d750',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgethwstate',['mcuxClEls_GetHwState',['../a00717.html#gadb25761b4c1a0de90f1420f459093bd5',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgethwversion',['mcuxClEls_GetHwVersion',['../a00717.html#gaade966640da314f17e6024ada7df6219',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetintenableflags',['mcuxClEls_GetIntEnableFlags',['../a00717.html#ga3de0def8758ec5320102a0beb521da37',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fgetkeyproperties',['mcuxClEls_GetKeyProperties',['../a00759.html#ga524d99bbf9aae0d299fbb52d2a121c4f',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fgetrandomstartdelay',['mcuxClEls_GetRandomStartDelay',['../a00717.html#ga1269f369af68e23e9ee8d282dc37c42b',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fhash_5fasync',['mcuxClEls_Hash_Async',['../a00742.html#ga086eeafba9afb8ea16550414fd33a3b3',1,'mcuxClEls_Hash.h']]], + ['mcuxclels_5fhkdf_5frfc5869_5fasync',['mcuxClEls_Hkdf_Rfc5869_Async',['../a00752.html#gaad9187ee88fcb4efae7fd9469b51dc81',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhkdf_5fsp80056c_5fasync',['mcuxClEls_Hkdf_Sp80056c_Async',['../a00752.html#ga8d44c8b880565afe51d941057570361b',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fhmac_5fasync',['mcuxClEls_Hmac_Async',['../a00747.html#gafc82ce850568a1e0c9f44f9e59d6fbbf',1,'mcuxClEls_Hmac.h']]], + ['mcuxclels_5fkeydelete_5fasync',['mcuxClEls_KeyDelete_Async',['../a00759.html#ga035d072c033f988194110973581c6303',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyexport_5fasync',['mcuxClEls_KeyExport_Async',['../a00759.html#ga698ad21f0b3576d2b9f4b7b3ef83134f',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5fkeyimport_5fasync',['mcuxClEls_KeyImport_Async',['../a00759.html#ga867d4be563b347273af25a559abd7f87',1,'mcuxClEls_KeyManagement.h']]], + ['mcuxclels_5flimitedwaitforoperation',['mcuxClEls_LimitedWaitForOperation',['../a00717.html#ga396f130363332586a56b9667cf46fe7e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fprng_5fgetrandom',['mcuxClEls_Prng_GetRandom',['../a00762.html#ga222cf598c85ceb0483297169255688b0',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5fprng_5fgetrandomword',['mcuxClEls_Prng_GetRandomWord',['../a00762.html#ga10ee7783feeef4fbe5d5309c61f358a1',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5freset_5fasync',['mcuxClEls_Reset_Async',['../a00717.html#ga988b48898347ef4de0912cae0f631764',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5freseterrorflags',['mcuxClEls_ResetErrorFlags',['../a00717.html#gaf5485491a0851bc3c475e50690219d74',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fresetintflags',['mcuxClEls_ResetIntFlags',['../a00717.html#ga02f29ce399968793e6091505ddd9fa5e',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5frng_5fdrbgrequest_5fasync',['mcuxClEls_Rng_DrbgRequest_Async',['../a00762.html#gac48eddfc58d2fc6aebe0dd373baf4360',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestaesctr_5fasync',['mcuxClEls_Rng_DrbgTestAesCtr_Async',['../a00762.html#gada018f6414175632aa2328ffd2ed02bf',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestaesecb_5fasync',['mcuxClEls_Rng_DrbgTestAesEcb_Async',['../a00762.html#gaa356b6cafdb26f78c90fc9a24dd7dcd8',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestextract_5fasync',['mcuxClEls_Rng_DrbgTestExtract_Async',['../a00762.html#ga89b800a51c4046c7c7736d545595e097',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdrbgtestinstantiate_5fasync',['mcuxClEls_Rng_DrbgTestInstantiate_Async',['../a00762.html#ga17e52c0038540a032faf460033df35e6',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5fconfigevaluate_5fasync',['mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async',['../a00762.html#gac7fb747c02024315df352977d8269535',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5frng_5fdtrng_5fconfigload_5fasync',['mcuxClEls_Rng_Dtrng_ConfigLoad_Async',['../a00762.html#ga254ab1259a0688701233e1cf3636b244',1,'mcuxClEls_Rng.h']]], + ['mcuxclels_5fsetintenableflags',['mcuxClEls_SetIntEnableFlags',['../a00717.html#ga1cfec63993fa918d3b590b41b3558d84',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fsetintflags',['mcuxClEls_SetIntFlags',['../a00717.html#ga90b8060544476c2e7278157833410c97',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fsetrandomstartdelay',['mcuxClEls_SetRandomStartDelay',['../a00717.html#gabe9a2fe0df05c3e99fcd4a7a9138a2c8',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5ftlsgeneratemasterkeyfrompremasterkey_5fasync',['mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async',['../a00752.html#gac8b832b6cfa9c2b15b51be04ab349ae6',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5ftlsgeneratesessionkeysfrommasterkey_5fasync',['mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async',['../a00752.html#ga50b0d0753ed6a370b187904db49826ff',1,'mcuxClEls_Kdf.h']]], + ['mcuxclels_5fupdaterefcrc',['mcuxClEls_UpdateRefCRC',['../a00724.html#gae04ed3290d9cb48f42f4f9aed4b1a825',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fverifyvsrefcrc',['mcuxClEls_VerifyVsRefCRC',['../a00724.html#ga5ebf64e6470c7a08c56ee44d9afe3990',1,'mcuxClEls_Crc.h']]], + ['mcuxclels_5fwaitforoperation',['mcuxClEls_WaitForOperation',['../a00717.html#gaee73cb4825b7722d9e085565170eb18e',1,'mcuxClEls_Common.h']]], + ['mcuxclexample_5ffunction',['MCUXCLEXAMPLE_FUNCTION',['../a00002.html#a4557ce4897e01774148f2f764c833b3a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#a771a0ec79a4dd825868d4be9bc76c6b7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00008.html#a7871444a5008d1d5409e35c7c1cbd1d3',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Ecc_Keygen_Sign_Verify_example): mcuxClEls_Ecc_Keygen_Sign_Verify_example.c'],['../a00011.html#a2d5de980923b27edc61a1c9ffb521a1e',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Common_Get_Info_example): mcuxClEls_Common_Get_Info_example.c'],['../a00014.html#ab89d2312fc5c2fdc0298cc1ae1f278e3',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha224_One_Block_example): mcuxClEls_Hash_Sha224_One_Block_example.c'],['../a00017.html#ac6870823b93f74e0bc36a7d1d471bd9d',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha256_One_Block_example): mcuxClEls_Hash_Sha256_One_Block_example.c'],['../a00020.html#a5a28e0b6909b5d91b26a95077092fae7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha384_One_Block_example): mcuxClEls_Hash_Sha384_One_Block_example.c'],['../a00023.html#aca162de2f88b777e78145615790dde8d',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha512_One_Block_example): mcuxClEls_Hash_Sha512_One_Block_example.c'],['../a00026.html#a4533123497ea62887db3256587ae76ac',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Rng_Prng_Get_Random_example): mcuxClEls_Rng_Prng_Get_Random_example.c'],['../a00029.html#afca899ba16d4b475a0e780589dbfc560',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Tls_Master_Key_Session_Keys_example): mcuxClEls_Tls_Master_Key_Session_Keys_example.c'],['../a00032.html#afa131c8f7a3740ff4732892b4db16bec',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Key_Import_Puk_DER_example): mcuxClEls_Key_Import_Puk_DER_example.c'],['../a00035.html#a39688ef490286a2fed36617ad2c02795',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Multipart_Els_Ccm_Example): mcuxClAeadModes_Multipart_Els_Ccm_Example.c'],['../a00038.html#a54de761e25b3fd9e3b4d7e5b90ebd7ca',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Ccm_Example): mcuxClAeadModes_Oneshot_Els_Ccm_Example.c'],['../a00041.html#a92d351633686713a2dc9f051c5d63c12',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Gcm_Example): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c'],['../a00074.html#a75d0a2ced8164c38afbd0c95a1ff6686',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve25519_example): mcuxClEcc_Mont_Curve25519_example.c'],['../a00077.html#addf8fd48c03094abe17db5e808ed580c',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve448_example): mcuxClEcc_Mont_Curve448_example.c'],['../a00080.html#a9e584bfb84b74adc18f23fb9774ff2e7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example): mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c'],['../a00116.html#a4d4124fd2881a1d89bcb320735293fc7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClKey_example): mcuxClKey_example.c'],['../a00119.html#a71e50006ff7948794718e7aee5ca982a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClMacModes_cmac_oneshot_example): mcuxClMacModes_cmac_oneshot_example.c'],['../a00134.html#a4fb93b93e2f83f913ca6d51af1f61e0a',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_ELS_example): mcuxClRandomModes_CtrDrbg_AES256_ELS_example.c'],['../a00137.html#a91004e78f2323ae2750f3db18d7ed12f',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_ELS_example): mcuxClRandomModes_ELS_example.c'],['../a00140.html#a824a93e2c644f62de4ab1c413f3cdeaa',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG3_example): mcuxClRandomModes_CtrDrbg_AES256_DRG3_example.c'],['../a00143.html#a9b0834b958b1450723fab20a00fcefe1',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_Different_Sessions_example): mcuxClRandomModes_Different_Sessions_example.c'],['../a00146.html#a8cbc037b8fa449be72bf01c6b63ca7a7',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_CtrDrbg_AES256_DRG4_example): mcuxClRandomModes_CtrDrbg_AES256_DRG4_example.c'],['../a00149.html#a7cbd851346a84954cad6892fe66c1d90',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example): mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c'],['../a00152.html#a99ac8d5cb62fa1f7978221415653da14',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example): mcuxClRandomModes_TestMode_CtrDrbg_AES256_PTG3_example.c'],['../a00155.html#a986952eb07f2ec086c4f6ff46bbbc9a0',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example): mcuxClRandomModes_TestMode_CtrDrbg_AES256_DRG4_example.c'],['../a00158.html#a7299c7736f173efca4ade8d274e7d75b',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_pssverify_sha2_256_example): mcuxClRsa_verify_pssverify_sha2_256_example.c'],['../a00161.html#a20789e8a17209cfcf845dd22d8a02462',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_pss_sha2_256_example): mcuxClRsa_sign_pss_sha2_256_example.c'],['../a00164.html#ab0f06c91945e4c60608e1508e1a40fdf',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_NoVerify_example): mcuxClRsa_verify_NoVerify_example.c'],['../a00167.html#a80d285764029b6fa279a51015d492960',1,'MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_NoEncode_example): mcuxClRsa_sign_NoEncode_example.c']]], + ['mcuxclhash_5fcompute',['mcuxClHash_compute',['../a00772.html#ga7beb1bb4063eae682eca700efeba93db',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5ffinish',['mcuxClHash_finish',['../a00772.html#gad55cc3a702b915f84d9cd2e94c2b7f6b',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5finit',['mcuxClHash_init',['../a00772.html#ga68263436904cf849bfbe8c9b1f6542d4',1,'mcuxClHash_Functions.h']]], + ['mcuxclhash_5fprocess',['mcuxClHash_process',['../a00772.html#ga49bdf3dca9746328fe58e6d5859e92eb',1,'mcuxClHash_Functions.h']]], + ['mcuxclhmac_5fcreatehmacmode',['mcuxClHmac_createHmacMode',['../a00780.html#ga43f6d98b6b3b6a6e62263130e2c95a68',1,'mcuxClHmac_Functions.h']]], + ['mcuxclkey_5fflush',['mcuxClKey_flush',['../a00790.html#ga60a86766cba40477651948cfa55eb7cd',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5finit',['mcuxClKey_init',['../a00790.html#ga8c6e891b1f7f973dbdccfe0f2a713142',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5flinkkeypair',['mcuxClKey_linkKeyPair',['../a00790.html#gadac5d6a29e1a0dba2b418b98e4ccd0ee',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5floadcopro',['mcuxClKey_loadCopro',['../a00790.html#ga616ead4a2aaab2d0ae5502ba52315fca',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5floadmemory',['mcuxClKey_loadMemory',['../a00790.html#gac4ec3d39748fc018dfb50316d2c51490',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5fsetkeyproperties',['mcuxClKey_setKeyproperties',['../a00790.html#gab1586a462e51711691901aa099f8b556',1,'mcuxClKey_Functions.h']]], + ['mcuxclkey_5fsetprotection',['mcuxClKey_setProtection',['../a00790.html#ga761180099785b36b6d5a6014cae54bb8',1,'mcuxClKey_Functions.h']]], + ['mcuxclmac_5fcompute',['mcuxClMac_compute',['../a00797.html#gad2fe8b5e17f2b468fbe8a61f8fee5400',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5ffinish',['mcuxClMac_finish',['../a00798.html#ga9d66c6e242ff75b6ff4826fdcb784e08',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5finit',['mcuxClMac_init',['../a00798.html#ga803bd7822372bdca8dfd0c81b5db96eb',1,'mcuxClMac_Functions.h']]], + ['mcuxclmac_5fprocess',['mcuxClMac_process',['../a00798.html#ga2749e40209d4308f21ebe761485d4d56',1,'mcuxClMac_Functions.h']]], + ['mcuxclmath_5fexactdivide',['mcuxClMath_ExactDivide',['../a00806.html#ga9416369d37627425ecac95580d1c3ee4',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fexactdivideodd',['mcuxClMath_ExactDivideOdd',['../a00806.html#ga7aa33c63d602fdb151d3e342284b2171',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5finitlocaluptrt',['mcuxClMath_InitLocalUptrt',['../a00806.html#ga716b9990024e2ea5e5984ca960a5e861',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fleadingzeros',['mcuxClMath_LeadingZeros',['../a00806.html#ga91e4885b266c16938e04aa036eae6977',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fmodexp_5fsqrmultl2r',['mcuxClMath_ModExp_SqrMultL2R',['../a00806.html#gabdd7a91f84faca1e208c143a25e318f8',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fmodinv',['mcuxClMath_ModInv',['../a00806.html#ga9c01f0090ea0220a735ea6992515cf7a',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fndash',['mcuxClMath_NDash',['../a00806.html#ga47ca58caa097e65c0925aa488f287a1e',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fqdash',['mcuxClMath_QDash',['../a00806.html#ga61ef022af097c89154560df0f81b3caa',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fqsquared',['mcuxClMath_QSquared',['../a00806.html#gae2ad68ea7641a23751583c27ed1d77a7',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5freducemodeven',['mcuxClMath_ReduceModEven',['../a00806.html#gadcf87738f49ecf4c39ee725fa6cb88f9',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fsecmodexp',['mcuxClMath_SecModExp',['../a00806.html#ga5f0ebd971dee31e271c27ae02479ff55',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5fshiftmodulus',['mcuxClMath_ShiftModulus',['../a00806.html#ga65003277bfc2c6eb64be0f23261cadd7',1,'mcuxClMath_Functions.h']]], + ['mcuxclmath_5ftrailingzeros',['mcuxClMath_TrailingZeros',['../a00806.html#ga0203db0be2a5c09157c0db697cc2685f',1,'mcuxClMath_Functions.h']]], + ['mcuxclmemory_5fclear',['mcuxClMemory_clear',['../a00809.html#ga1ac6e8a4335f620d41360c090ee5ce73',1,'mcuxClMemory_Clear.h']]], + ['mcuxclmemory_5fcopy',['mcuxClMemory_copy',['../a00810.html#gab564183ab5f02cf11b66b6244ba2112a',1,'mcuxClMemory_Copy.h']]], + ['mcuxclmemory_5fcopy_5freversed',['mcuxClMemory_copy_reversed',['../a00811.html#gafc918d181009c3af7638604e5e4b9281',1,'mcuxClMemory_Copy_Reversed.h']]], + ['mcuxclmemory_5fset',['mcuxClMemory_set',['../a00813.html#ga5d86af41c30044c28809914e2901884d',1,'mcuxClMemory_Set.h']]], + ['mcuxclpkc_5fcalc',['mcuxClPkc_Calc',['../a00965.html#ga1fe435f5e72d9347692a7ac8fa2ba67f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fcalcconst',['mcuxClPkc_CalcConst',['../a00965.html#ga2d214326104dc2ced79098286852ae03',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fcalcfup',['mcuxClPkc_CalcFup',['../a00965.html#gaec0a3e70eb593b9bd49edf9e7aba298e',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fdeinitialize',['mcuxClPkc_Deinitialize',['../a00963.html#ga0d09260a20ca358d02264f16a74369c1',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fgenerateuptrt',['mcuxClPkc_GenerateUPTRT',['../a00964.html#gae14e20fe9fd56e0ca8125773bc88f822',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5finitialize',['mcuxClPkc_Initialize',['../a00963.html#ga338ddc55800355531bd20236fa3710b8',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5frandomizeuptrt',['mcuxClPkc_RandomizeUPTRT',['../a00964.html#gaf961165a01be833d3200563399a2c9aa',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5frerandomizeuptrt',['mcuxClPkc_ReRandomizeUPTRT',['../a00964.html#ga195c78d51f2084c693257bc52c725c1f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fwaitforfinish',['mcuxClPkc_WaitForFinish',['../a00966.html#ga7d26efcc91094390f7c55fbd870692cd',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fwaitforready',['mcuxClPkc_WaitForReady',['../a00966.html#ga963b13a65f2ae869947cbbebf2f9a823',1,'mcuxClPkc_Functions.h']]], + ['mcuxclrandom_5fchecksecuritystrength',['mcuxClRandom_checkSecurityStrength',['../a00831.html#ga6e48c6007ea1d6cfa2ec329152072fc0',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fgenerate',['mcuxClRandom_generate',['../a00831.html#gadb7d7b6ff820450be3533014cb47f279',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5finit',['mcuxClRandom_init',['../a00831.html#ga989cf9033b30c383d1548037f2ec8bc9',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fncgenerate',['mcuxClRandom_ncGenerate',['../a00831.html#ga942c035e4c1971f3e4da8cf252b6cdf6',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fncinit',['mcuxClRandom_ncInit',['../a00831.html#ga4522b9cfa28cb224b653003d481d7100',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5freseed',['mcuxClRandom_reseed',['../a00831.html#ga89fe90a4ca175d03b4a821cf2fa2004f',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5fselftest',['mcuxClRandom_selftest',['../a00831.html#ga4c882c0d6b1e1bba418934c44acc873c',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrandom_5funinit',['mcuxClRandom_uninit',['../a00831.html#ga92889d1e06ba33656278bd2a4110be99',1,'mcuxClRandom_Functions.h']]], + ['mcuxclrsa_5fkeygeneration_5fcrt',['mcuxClRsa_KeyGeneration_Crt',['../a00843.html#gaa099449b2290a333aac2dcf090a2740c',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fkeygeneration_5fplain',['mcuxClRsa_KeyGeneration_Plain',['../a00843.html#ga08dff8d41898b3f372ceab1038205b51',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fsign',['mcuxClRsa_sign',['../a00843.html#gaea19a43d7a52c159675d93d8e7d6ec51',1,'mcuxClRsa_Functions.h']]], + ['mcuxclrsa_5fverify',['mcuxClRsa_verify',['../a00843.html#ga21bf92b81f28be1b6b6fc7d3bdc69098',1,'mcuxClRsa_Functions.h']]], + ['mcuxclsession_5fcleanup',['mcuxClSession_cleanup',['../a00855.html#ga1ba3d2c6e561c86e1da8fcc0abfd046c',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5fdestroy',['mcuxClSession_destroy',['../a00855.html#gaad324fd8f8eeefa29521c4297ac75fd2',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5finit',['mcuxClSession_init',['../a00855.html#gaf1b8776b0d519136df17f6dd632442cf',1,'mcuxClSession_Functions.h']]], + ['mcuxclsession_5fsetrtf',['mcuxClSession_setRtf',['../a00855.html#ga159bff529d405fd6da2930590a69ac06',1,'mcuxClSession_Functions.h']]], + ['mcuxcsslmemory_5fclear',['mcuxCsslMemory_Clear',['../a00887.html#gaea7d5f3c8d216e752f153827689e88c3',1,'mcuxCsslMemory_Clear.h']]], + ['mcuxcsslmemory_5fcompare',['mcuxCsslMemory_Compare',['../a00889.html#ga0a6695838853535250234994d7e4d5b1',1,'mcuxCsslMemory_Compare.h']]], + ['mcuxcsslmemory_5fcopy',['mcuxCsslMemory_Copy',['../a00891.html#gaa29b7e8d23c8d95ce248fc8e0a4b37c8',1,'mcuxCsslMemory_Copy.h']]], + ['mcuxcsslmemory_5fset',['mcuxCsslMemory_Set',['../a00893.html#ga0a0ed6d55e0cb4d633ba19a32aca64c6',1,'mcuxCsslMemory_Set.h']]], + ['mcuxcsslparamintegrity_5fprotect',['mcuxCsslParamIntegrity_Protect',['../a00900.html#gaaa2a9f40eb61dbe8ccce1b3b2dc824bb',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fvalidate',['mcuxCsslParamIntegrity_Validate',['../a00900.html#gaface23af4c626fe4adf70518056f2f33',1,'mcuxCsslParamIntegrity.h']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/functions_2.html b/components/els_pkc/doc/mcxn/html/search/functions_2.html new file mode 100644 index 000000000..2b44474ed --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
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+
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+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/functions_2.js b/components/els_pkc/doc/mcxn/html/search/functions_2.js new file mode 100644 index 000000000..216894b0e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/functions_2.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['rng_5fpatch_5ffunction',['RNG_Patch_function',['../a00149.html#af28f6bb34479e4b2fe6b40fa868ee71b',1,'mcuxClRandomModes_PatchMode_CtrDrbg_AES256_DRG3_example.c']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_0.html b/components/els_pkc/doc/mcxn/html/search/groups_0.html new file mode 100644 index 000000000..194bb7bcb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
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+
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+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_0.js b/components/els_pkc/doc/mcxn/html/search/groups_0.js new file mode 100644 index 000000000..d5eedc26e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_0.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['aead_20mode_20definitions',['AEAD mode definitions',['../a00668.html',1,'']]], + ['aead_20type_20definitions',['AEAD type definitions',['../a00666.html',1,'']]], + ['apis_20to_20construct_20hmac_20modes',['APIs to construct HMAC modes',['../a00780.html',1,'']]], + ['apis_20to_20construct_20mac_20modes',['APIs to construct Mac modes',['../a00802.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_1.html b/components/els_pkc/doc/mcxn/html/search/groups_1.html new file mode 100644 index 000000000..ed9b5c61e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
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+
+ +
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+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_1.js b/components/els_pkc/doc/mcxn/html/search/groups_1.js new file mode 100644 index 000000000..91fb7fb30 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_1.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['branching_20flow_20protection',['Branching flow protection',['../a00874.html',1,'']]], + ['branching_20flow_20protection',['Branching flow protection',['../a00883.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_2.html b/components/els_pkc/doc/mcxn/html/search/groups_2.html new file mode 100644 index 000000000..17d4e06ab --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_2.js b/components/els_pkc/doc/mcxn/html/search/groups_2.js new file mode 100644 index 000000000..e4a5fdcba --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_2.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['cipher_20mode_20definitions',['Cipher mode definitions',['../a00677.html',1,'']]], + ['cipher_20type_20definitions',['Cipher type definitions',['../a00676.html',1,'']]], + ['core_20type_20definitions',['Core type definitions',['../a00678.html',1,'']]], + ['constants_20definitions',['Constants definitions',['../a00824.html',1,'']]], + ['core_20api',['Core API',['../a00917.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_3.html b/components/els_pkc/doc/mcxn/html/search/groups_3.html new file mode 100644 index 000000000..7d4a624e4 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_3.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_3.js b/components/els_pkc/doc/mcxn/html/search/groups_3.js new file mode 100644 index 000000000..8da31d836 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_3.js @@ -0,0 +1,10 @@ +var searchData= +[ + ['data_20integrity_20core_20functionality',['Data integrity core functionality',['../a00862.html',1,'']]], + ['data_20integrity_20core_20functionality',['Data integrity core functionality',['../a00868.html',1,'']]], + ['data_20integrity_20record',['Data integrity record',['../a00869.html',1,'']]], + ['data_20integrity_20record',['Data integrity record',['../a00863.html',1,'']]], + ['data_20integrity_20api',['Data Integrity API',['../a00861.html',1,'']]], + ['data_20integrity_20configuration',['Data Integrity Configuration',['../a00865.html',1,'']]], + ['data_20integrity_3a_20disabled',['Data Integrity: Disabled',['../a00867.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_4.html b/components/els_pkc/doc/mcxn/html/search/groups_4.html new file mode 100644 index 000000000..5e5ae2ac1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_4.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_4.js b/components/els_pkc/doc/mcxn/html/search/groups_4.js new file mode 100644 index 000000000..a2e468ae2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_4.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['expectation_20handling',['Expectation handling',['../a00880.html',1,'']]], + ['expectation_20handling',['Expectation handling',['../a00876.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_5.html b/components/els_pkc/doc/mcxn/html/search/groups_5.html new file mode 100644 index 000000000..fbd146059 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_5.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_5.js b/components/els_pkc/doc/mcxn/html/search/groups_5.js new file mode 100644 index 000000000..30c5f1a23 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_5.js @@ -0,0 +1,10 @@ +var searchData= +[ + ['flow_20protection_20core_20functionality',['Flow protection core functionality',['../a00879.html',1,'']]], + ['function_20calling_20flow_20protection',['Function calling flow protection',['../a00881.html',1,'']]], + ['flow_20protection_20core_20functionality',['Flow protection core functionality',['../a00871.html',1,'']]], + ['function_20calling_20flow_20protection',['Function calling flow protection',['../a00872.html',1,'']]], + ['flow_20protection_20api',['Flow Protection API',['../a00870.html',1,'']]], + ['flow_20protection_20configuration',['Flow Protection Configuration',['../a00877.html',1,'']]], + ['flow_20protection_3a_20secure_20counter',['Flow Protection: Secure Counter',['../a00878.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_6.html b/components/els_pkc/doc/mcxn/html/search/groups_6.html new file mode 100644 index 000000000..277d80e19 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_6.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_6.js b/components/els_pkc/doc/mcxn/html/search/groups_6.js new file mode 100644 index 000000000..40767531d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_6.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['hmac_20modes_20api',['HMAC Modes API',['../a00961.html',1,'']]], + ['hmac_20mode_20definitions',['HMAC mode definitions',['../a00783.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_7.html b/components/els_pkc/doc/mcxn/html/search/groups_7.html new file mode 100644 index 000000000..6a24e7cf2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_7.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_7.js b/components/els_pkc/doc/mcxn/html/search/groups_7.js new file mode 100644 index 000000000..d6f2fdedd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_7.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['key_20protection_20mechanism_20definitions',['Key protection mechanism definitions',['../a00792.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_8.html b/components/els_pkc/doc/mcxn/html/search/groups_8.html new file mode 100644 index 000000000..81ac95080 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_8.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_8.js b/components/els_pkc/doc/mcxn/html/search/groups_8.js new file mode 100644 index 000000000..314287354 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_8.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['looping_20flow_20protection',['Looping flow protection',['../a00882.html',1,'']]], + ['looping_20flow_20protection',['Looping flow protection',['../a00873.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_9.html b/components/els_pkc/doc/mcxn/html/search/groups_9.html new file mode 100644 index 000000000..2a1fc0ab2 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_9.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_9.js b/components/els_pkc/doc/mcxn/html/search/groups_9.js new file mode 100644 index 000000000..ea6002f5b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_9.js @@ -0,0 +1,250 @@ +var searchData= +[ + ['multi_2dpart_20cipher_20interfaces',['Multi-part Cipher interfaces',['../a00675.html',1,'']]], + ['mcuxclaead',['mcuxClAead',['../a00661.html',1,'']]], + ['mcuxclaead_5fconstants',['mcuxClAead_Constants',['../a00662.html',1,'']]], + ['mcuxclaead_5fmemoryconsumption',['mcuxClAead_MemoryConsumption',['../a00667.html',1,'']]], + ['mcuxclaead_5fstatus_5f',['MCUXCLAEAD_STATUS_',['../a00663.html',1,'']]], + ['multi_2dpart_20aead_20interfaces',['Multi-part AEAD interfaces',['../a00665.html',1,'']]], + ['mcuxclaes_5fconstants',['mcuxClAes_Constants',['../a00669.html',1,'']]], + ['mcuxclaes_5fkeytypes',['mcuxClAes_KeyTypes',['../a00670.html',1,'']]], + ['mcux_20cl_20_26ndash_3b_20api',['MCUX CL &ndash; API',['../a00673.html',1,'']]], + ['mcuxclcipher',['mcuxClCipher',['../a00671.html',1,'']]], + ['mcuxclcipher_5fconstants',['mcuxClCipher_Constants',['../a00672.html',1,'']]], + ['mcuxclecc',['mcuxClEcc',['../a00679.html',1,'']]], + ['mcuxclecc_5fconstants',['mcuxClEcc_Constants',['../a00680.html',1,'']]], + ['mcuxclecc_5fdescriptors',['mcuxClEcc_Descriptors',['../a00687.html',1,'']]], + ['mcuxclecc_5feddsa_5fed25519_5fsize_5f',['MCUXCLECC_EDDSA_ED25519_SIZE_',['../a00957.html',1,'']]], + ['mcuxclecc_5feddsa_5fed448_5fsize_5f',['MCUXCLECC_EDDSA_ED448_SIZE_',['../a00958.html',1,'']]], + ['mcuxclecc_5feddsa_5fgenkeypair_5fdesc_5fsize_5f',['MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_',['../a00924.html',1,'']]], + ['mcuxclecc_5feddsa_5fsignature_5fprotocol_5fdesc_5fsize_5f',['MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_',['../a00925.html',1,'']]], + ['mcuxclecc_5feddsa_5fwacpu_5f',['MCUXCLECC_EDDSA_WACPU_',['../a00920.html',1,'']]], + ['mcuxclecc_5feddsa_5fwapkc_5f',['MCUXCLECC_EDDSA_WAPKC_',['../a00923.html',1,'']]], + ['mcuxclecc_5ffunctions',['mcuxClEcc_Functions',['../a00681.html',1,'']]], + ['mcuxclecc_5fkeytypedescriptors',['mcuxClEcc_KeyTypeDescriptors',['../a00682.html',1,'']]], + ['mcuxclecc_5fmacros',['mcuxClEcc_Macros',['../a00685.html',1,'']]], + ['mcuxclecc_5fmemoryconsumption',['mcuxClEcc_MemoryConsumption',['../a00683.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve25519_5fsize_5f',['MCUXCLECC_MONT_CURVE25519_SIZE_',['../a00926.html',1,'']]], + ['mcuxclecc_5fmont_5fcurve448_5fsize_5f',['MCUXCLECC_MONT_CURVE448_SIZE_',['../a00927.html',1,'']]], + ['mcuxclecc_5fmontdh_5fstatus_5f',['MCUXCLECC_MONTDH_STATUS_',['../a00960.html',1,'']]], + ['mcuxclecc_5fmontdh_5fwacpu_5f',['MCUXCLECC_MONTDH_WACPU_',['../a00919.html',1,'']]], + ['mcuxclecc_5fmontdh_5fwapkc_5f',['MCUXCLECC_MONTDH_WAPKC_',['../a00922.html',1,'']]], + ['mcuxclecc_5fparametersizes',['mcuxClEcc_ParameterSizes',['../a00684.html',1,'']]], + ['mcuxclecc_5fstatus_5f',['MCUXCLECC_STATUS_',['../a00959.html',1,'']]], + ['mcuxclecc_5ftypes',['mcuxClEcc_Types',['../a00686.html',1,'']]], + ['mcuxclecc_5fwacpu_5f',['MCUXCLECC_WACPU_',['../a00918.html',1,'']]], + ['mcuxclecc_5fwapkc_5f',['MCUXCLECC_WAPKC_',['../a00921.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp160r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_',['../a00942.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp160t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_',['../a00949.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp192r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_',['../a00943.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp192t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_',['../a00950.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp224r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_',['../a00944.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp224t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_',['../a00951.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp256r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_',['../a00945.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp256t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_',['../a00952.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp320r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_',['../a00946.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp320t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_',['../a00953.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp384r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_',['../a00947.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp384t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_',['../a00954.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp512r1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_',['../a00948.html',1,'']]], + ['mcuxclecc_5fweierecc_5fbrainpoolp512t1_5fsize_5f',['MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_',['../a00955.html',1,'']]], + ['mcuxclecc_5fweierecc_5fmax_5fsize',['MCUXCLECC_WEIERECC_MAX_SIZE',['../a00956.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp192_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P192_SIZE_',['../a00937.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp224_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P224_SIZE_',['../a00938.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp256_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P256_SIZE_',['../a00939.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp384_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P384_SIZE_',['../a00940.html',1,'']]], + ['mcuxclecc_5fweierecc_5fnist_5fp521_5fsize_5f',['MCUXCLECC_WEIERECC_NIST_P521_SIZE_',['../a00941.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp160k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP160K1_SIZE_',['../a00928.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp192k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP192K1_SIZE_',['../a00929.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp192r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP192R1_SIZE_',['../a00932.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp224k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP224K1_SIZE_',['../a00930.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp224r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP224R1_SIZE_',['../a00933.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp256k1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP256K1_SIZE_',['../a00931.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp256r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP256R1_SIZE_',['../a00934.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp384r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP384R1_SIZE_',['../a00935.html',1,'']]], + ['mcuxclecc_5fweierecc_5fsecp521r1_5fsize_5f',['MCUXCLECC_WEIERECC_SECP521R1_SIZE_',['../a00936.html',1,'']]], + ['mcuxclels',['mcuxClEls',['../a00688.html',1,'']]], + ['mcuxclels_5faead',['mcuxClEls_Aead',['../a00689.html',1,'']]], + ['mcuxclels_5faead_5f',['MCUXCLELS_AEAD_',['../a00691.html',1,'']]], + ['mcuxclels_5faead_5ffunctions',['mcuxClEls_Aead_Functions',['../a00693.html',1,'']]], + ['mcuxclels_5faead_5fmacros',['mcuxClEls_Aead_Macros',['../a00690.html',1,'']]], + ['mcuxclels_5faead_5ftypes',['mcuxClEls_Aead_Types',['../a00692.html',1,'']]], + ['mcuxclels_5fcipher',['mcuxClEls_Cipher',['../a00694.html',1,'']]], + ['mcuxclels_5fcipher_5f',['MCUXCLELS_CIPHER_',['../a00696.html',1,'']]], + ['mcuxclels_5fcipher_5ffunctions',['mcuxClEls_Cipher_Functions',['../a00699.html',1,'']]], + ['mcuxclels_5fcipher_5fkey_5fsize_5faes_5f',['MCUXCLELS_CIPHER_KEY_SIZE_AES_',['../a00697.html',1,'']]], + ['mcuxclels_5fcipher_5fmacros',['mcuxClEls_Cipher_Macros',['../a00695.html',1,'']]], + ['mcuxclels_5fcipher_5ftypes',['mcuxClEls_Cipher_Types',['../a00698.html',1,'']]], + ['mcuxclels_5fcmac',['mcuxClEls_Cmac',['../a00700.html',1,'']]], + ['mcuxclels_5fcmac_5f',['MCUXCLELS_CMAC_',['../a00703.html',1,'']]], + ['mcuxclels_5fcmac_5ffunctions',['mcuxClEls_Cmac_Functions',['../a00705.html',1,'']]], + ['mcuxclels_5fcmac_5fkey_5fsize_5f',['MCUXCLELS_CMAC_KEY_SIZE_',['../a00702.html',1,'']]], + ['mcuxclels_5fcmac_5fmacros',['mcuxClEls_Cmac_Macros',['../a00701.html',1,'']]], + ['mcuxclels_5fcmac_5ftypes',['mcuxClEls_Cmac_Types',['../a00704.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5f',['MCUXCLELS_CMD_CRC_',['../a00720.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5fcmd_5fid_5f',['MCUXCLELS_CMD_CRC_CMD_ID_',['../a00722.html',1,'']]], + ['mcuxclels_5fcmd_5fcrc_5freference_5f',['MCUXCLELS_CMD_CRC_REFERENCE_',['../a00721.html',1,'']]], + ['mcuxclels_5fcommon',['mcuxClEls_Common',['../a00706.html',1,'']]], + ['mcuxclels_5fcommon_5ffunctions',['mcuxClEls_Common_Functions',['../a00717.html',1,'']]], + ['mcuxclels_5fcommon_5fmacros',['mcuxClEls_Common_Macros',['../a00707.html',1,'']]], + ['mcuxclels_5fcommon_5ftypes',['mcuxClEls_Common_Types',['../a00716.html',1,'']]], + ['mcuxclels_5fcrc',['mcuxClEls_Crc',['../a00718.html',1,'']]], + ['mcuxclels_5fcrc_5ffunctions',['mcuxClEls_Crc_Functions',['../a00724.html',1,'']]], + ['mcuxclels_5fcrc_5fmacros',['mcuxClEls_Crc_Macros',['../a00719.html',1,'']]], + ['mcuxclels_5fcrc_5ftypes',['mcuxClEls_Crc_Types',['../a00723.html',1,'']]], + ['mcuxclels_5fecc',['mcuxClEls_Ecc',['../a00725.html',1,'']]], + ['mcuxclels_5fecc_5ffunctions',['mcuxClEls_Ecc_Functions',['../a00734.html',1,'']]], + ['mcuxclels_5fecc_5fmacros',['mcuxClEls_Ecc_Macros',['../a00726.html',1,'']]], + ['mcuxclels_5fecc_5fsize',['MCUXCLELS_ECC_SIZE',['../a00732.html',1,'']]], + ['mcuxclels_5fecc_5ftypes',['mcuxClEls_Ecc_Types',['../a00733.html',1,'']]], + ['mcuxclels_5fecc_20_28sign_20and_20verify_29_20option_20word_20values',['MCUXCLELS_ECC (Sign and Verify) option word values',['../a00727.html',1,'']]], + ['mcuxclels_5fecc_20_28sign_20and_20verify_29_20option_20bit_20field_20values',['MCUXCLELS_ECC (Sign and Verify) option bit field values',['../a00729.html',1,'']]], + ['mcuxclels_5ferror_5fflags_5f',['MCUXCLELS_ERROR_FLAGS_',['../a00711.html',1,'']]], + ['mcuxclels_5fhash',['mcuxClEls_Hash',['../a00735.html',1,'']]], + ['mcuxclels_5fhash_5f',['MCUXCLELS_HASH_',['../a00737.html',1,'']]], + ['mcuxclels_5fhash_5fblock_5fsize_5f',['MCUXCLELS_HASH_BLOCK_SIZE_',['../a00738.html',1,'']]], + ['mcuxclels_5fhash_5ffunctions',['mcuxClEls_Hash_Functions',['../a00742.html',1,'']]], + ['mcuxclels_5fhash_5fmacros',['mcuxClEls_Hash_Macros',['../a00736.html',1,'']]], + ['mcuxclels_5fhash_5foutput_5fsize_5f',['MCUXCLELS_HASH_OUTPUT_SIZE_',['../a00740.html',1,'']]], + ['mcuxclels_5fhash_5fstate_5fsize_5f',['MCUXCLELS_HASH_STATE_SIZE_',['../a00739.html',1,'']]], + ['mcuxclels_5fhash_5ftypes',['mcuxClEls_Hash_Types',['../a00741.html',1,'']]], + ['mcuxclels_5fhmac',['mcuxClEls_Hmac',['../a00743.html',1,'']]], + ['mcuxclels_5fhmac_5fexternal_5fkey_5f',['MCUXCLELS_HMAC_EXTERNAL_KEY_',['../a00745.html',1,'']]], + ['mcuxclels_5fhmac_5ffunctions',['mcuxClEls_Hmac_Functions',['../a00747.html',1,'']]], + ['mcuxclels_5fhmac_5fmacros',['mcuxClEls_Hmac_Macros',['../a00744.html',1,'']]], + ['mcuxclels_5fhmac_5ftypes',['mcuxClEls_Hmac_Types',['../a00746.html',1,'']]], + ['mcuxclels_5finterruptoptionen_5ft',['mcuxClEls_InterruptOptionEn_t',['../a00708.html',1,'']]], + ['mcuxclels_5finterruptoptionrst_5ft',['mcuxClEls_InterruptOptionRst_t',['../a00709.html',1,'']]], + ['mcuxclels_5finterruptoptionset_5ft',['mcuxClEls_InterruptOptionSet_t',['../a00710.html',1,'']]], + ['mcuxclels_5fkdf',['mcuxClEls_Kdf',['../a00748.html',1,'']]], + ['mcuxclels_5fkdf_5fdefine',['mcuxClEls_Kdf_Define',['../a00750.html',1,'']]], + ['mcuxclels_5fkdf_5ffunctions',['mcuxClEls_Kdf_Functions',['../a00752.html',1,'']]], + ['mcuxclels_5fkdf_5fmacros',['mcuxClEls_Kdf_Macros',['../a00749.html',1,'']]], + ['mcuxclels_5fkdf_5ftypes',['mcuxClEls_Kdf_Types',['../a00751.html',1,'']]], + ['mcuxclels_5fkeygen_20option_20word_20values',['MCUXCLELS_KEYGEN option word values',['../a00728.html',1,'']]], + ['mcuxclels_5fkeygen_20option_20bit_20field_20values',['MCUXCLELS_KEYGEN option bit field values',['../a00730.html',1,'']]], + ['mcuxclels_5fkeyimport_5fkfmt_5f',['MCUXCLELS_KEYIMPORT_KFMT_',['../a00756.html',1,'']]], + ['mcuxclels_5fkeyimport_5fvalue_5fkfmt_5f',['MCUXCLELS_KEYIMPORT_VALUE_KFMT_',['../a00755.html',1,'']]], + ['mcuxclels_5fkeymanagement',['mcuxClEls_KeyManagement',['../a00753.html',1,'']]], + ['mcuxclels_5fkeymanagement_5ffunctions',['mcuxClEls_KeyManagement_Functions',['../a00759.html',1,'']]], + ['mcuxclels_5fkeymanagement_5fmacros',['mcuxClEls_KeyManagement_Macros',['../a00754.html',1,'']]], + ['mcuxclels_5fkeymanagement_5ftypes',['mcuxClEls_KeyManagement_Types',['../a00758.html',1,'']]], + ['mcuxclels_5fkeyproperty_5f',['MCUXCLELS_KEYPROPERTY_',['../a00766.html',1,'']]], + ['mcuxclels_5fkeyproperty_5fvalue_5f',['MCUXCLELS_KEYPROPERTY_VALUE_',['../a00765.html',1,'']]], + ['mcuxclels_5freset_5f',['MCUXCLELS_RESET_',['../a00712.html',1,'']]], + ['mcuxclels_5frfc3394_5f',['MCUXCLELS_RFC3394_',['../a00757.html',1,'']]], + ['mcuxclels_5frng',['mcuxClEls_Rng',['../a00760.html',1,'']]], + ['mcuxclels_5frng_5ffunctions',['mcuxClEls_Rng_Functions',['../a00762.html',1,'']]], + ['mcuxclels_5frng_5fmacros',['mcuxClEls_Rng_Macros',['../a00761.html',1,'']]], + ['mcuxclels_5fstatus_5f',['MCUXCLELS_STATUS_',['../a00767.html',1,'']]], + ['mcuxclels_5fstatus_5fdrbgentlvl_5f',['MCUXCLELS_STATUS_DRBGENTLVL_',['../a00715.html',1,'']]], + ['mcuxclels_5fstatus_5fecdsavfy_5f',['MCUXCLELS_STATUS_ECDSAVFY_',['../a00714.html',1,'']]], + ['mcuxclels_5fstatus_5fpprot_5f',['MCUXCLELS_STATUS_PPROT_',['../a00713.html',1,'']]], + ['mcuxclels_5ftypes',['mcuxClEls_Types',['../a00763.html',1,'']]], + ['mcuxclels_5ftypes_5fmacros',['mcuxClEls_Types_Macros',['../a00764.html',1,'']]], + ['mcuxclels_5ftypes_5ftypes',['mcuxClEls_Types_Types',['../a00768.html',1,'']]], + ['mcuxclhash',['mcuxClHash',['../a00769.html',1,'']]], + ['mcuxclhash_5fconstants',['mcuxClHash_Constants',['../a00770.html',1,'']]], + ['mcuxclhash_5ffunctions',['mcuxClHash_Functions',['../a00772.html',1,'']]], + ['mcuxclhash_5foutput_5fsize_5f',['MCUXCLHASH_OUTPUT_SIZE_',['../a00775.html',1,'']]], + ['mcuxclhash_5fstatus_5f',['MCUXCLHASH_STATUS_',['../a00771.html',1,'']]], + ['mcuxclhash_5ftypes',['mcuxClHash_Types',['../a00773.html',1,'']]], + ['mcuxclhashmodes_5falgorithms',['mcuxClHashModes_Algorithms',['../a00774.html',1,'']]], + ['mcuxclhashmodes_5fcontextsize',['mcuxClHashModes_ContextSize',['../a00777.html',1,'']]], + ['mcuxclhashmodes_5fwoarkareaconsumption',['mcuxClHashModes_WoarkareaConsumption',['../a00776.html',1,'']]], + ['mcuxclhmac_20constants',['mcuxClHmac Constants',['../a00778.html',1,'']]], + ['mcuxclhmac_20functions',['mcuxClHmac Functions',['../a00779.html',1,'']]], + ['mcuxclhmac_5fkeytypes',['mcuxClHmac_KeyTypes',['../a00781.html',1,'']]], + ['mcuxclhmac_5fmemoryconsumption',['mcuxClHmac_MemoryConsumption',['../a00782.html',1,'']]], + ['mcuxclkey',['mcuxClKey',['../a00784.html',1,'']]], + ['mcuxclkey_5ffunctions',['mcuxClKey_Functions',['../a00790.html',1,'']]], + ['mcuxclkey_5fkeysize',['mcuxClKey_KeySize',['../a00789.html',1,'']]], + ['mcuxclkey_5fkeytypes',['mcuxClKey_KeyTypes',['../a00788.html',1,'']]], + ['mcuxclkey_5floadstatus_5f',['MCUXCLKEY_LOADSTATUS_',['../a00787.html',1,'']]], + ['mcuxclkey_5fmacros',['mcuxClKey_Macros',['../a00785.html',1,'']]], + ['mcuxclkey_5fmemoryconsumption',['mcuxClKey_MemoryConsumption',['../a00791.html',1,'']]], + ['mcuxclkey_5fstatus_5f',['MCUXCLKEY_STATUS_',['../a00786.html',1,'']]], + ['mcuxclkey_5ftypes',['mcuxClKey_Types',['../a00793.html',1,'']]], + ['mcuxclmac',['mcuxClMac',['../a00794.html',1,'']]], + ['mcuxclmac_5fconstants',['mcuxClMac_Constants',['../a00795.html',1,'']]], + ['mcuxclmac_20functions',['mcuxClMac Functions',['../a00796.html',1,'']]], + ['multi_20part_20mac_20interfaces',['Multi part MAC interfaces',['../a00798.html',1,'']]], + ['mcuxclmac_5ftypes',['mcuxClMac_Types',['../a00799.html',1,'']]], + ['mac_20modes_20api',['MAC Modes API',['../a00962.html',1,'']]], + ['mcuxclmacmodes_20constants',['mcuxClMacModes Constants',['../a00800.html',1,'']]], + ['mcuxclmacmodes_20functions',['mcuxClMacModes Functions',['../a00801.html',1,'']]], + ['mcuxclmacmodes_5fmemoryconsumption',['mcuxClMacModes_MemoryConsumption',['../a00803.html',1,'']]], + ['mac_20mode_20definitions',['MAC mode definitions',['../a00804.html',1,'']]], + ['mcuxclmath',['mcuxClMath',['../a00805.html',1,'']]], + ['mcuxclmath_5ffunctions',['mcuxClMath_Functions',['../a00806.html',1,'']]], + ['mcuxclmath_5fmacros',['mcuxClMath_Macros',['../a00807.html',1,'']]], + ['mcuxclmemory',['mcuxClMemory',['../a00808.html',1,'']]], + ['mcuxclmemory_5fclear',['mcuxClMemory_Clear',['../a00809.html',1,'']]], + ['mcuxclmemory_5fcopy',['mcuxClMemory_Copy',['../a00810.html',1,'']]], + ['mcuxclmemory_5fcopy_5freversed',['mcuxClMemory_Copy_Reversed',['../a00811.html',1,'']]], + ['mcuxclmemory_5fendianness',['mcuxClMemory_Endianness',['../a00812.html',1,'']]], + ['mcuxclmemory_5fset',['mcuxClMemory_Set',['../a00813.html',1,'']]], + ['mcuxclmemory_5fstatus_5f',['MCUXCLMEMORY_STATUS_',['../a00816.html',1,'']]], + ['mcuxclmemory_5ftypes',['mcuxClMemory_Types',['../a00814.html',1,'']]], + ['mcuxclmemory_5ftypes_5fmacros',['mcuxClMemory_Types_Macros',['../a00815.html',1,'']]], + ['mcuxclosccapkc',['mcuxClOsccaPkc',['../a00817.html',1,'']]], + ['mcuxclosccapkc_5ffunctions',['mcuxClOsccaPkc_Functions',['../a00818.html',1,'']]], + ['mcuxclosccasm3',['mcuxClOsccaSm3',['../a00819.html',1,'']]], + ['mcuxclosccasm3_5fcontext',['MCUXCLOSCCASM3_CONTEXT',['../a00823.html',1,'']]], + ['mcuxclosccasm3_5fmodes',['mcuxClOsccaSm3_Modes',['../a00820.html',1,'']]], + ['mcuxclosccasm3_5foutput_5fsize_5f',['MCUXCLOSCCASM3_OUTPUT_SIZE_',['../a00821.html',1,'']]], + ['mcuxclosccasm3_5fwa',['MCUXCLOSCCASM3_WA',['../a00822.html',1,'']]], + ['mcuxclpkc',['mcuxClPkc',['../a00826.html',1,'']]], + ['mcuxclpkc_5ffunctions',['mcuxClPkc_Functions',['../a00827.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fcalculation',['McuxClPkc_Functions_Calculation',['../a00965.html',1,'']]], + ['mcuxclpkc_5ffunctions_5finit',['McuxClPkc_Functions_Init',['../a00963.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fuptrt',['McuxClPkc_Functions_UPTRT',['../a00964.html',1,'']]], + ['mcuxclpkc_5ffunctions_5fwait',['McuxClPkc_Functions_Wait',['../a00966.html',1,'']]], + ['mcuxclpkc_5fmacros',['mcuxClPkc_Macros',['../a00828.html',1,'']]], + ['mcuxclpkc_5fmisc_5f',['MCUXCLPKC_MISC_',['../a00968.html',1,'']]], + ['mcuxclpkc_5fstatus_5f',['MCUXCLPKC_STATUS_',['../a00967.html',1,'']]], + ['mcuxclrandom',['mcuxClRandom',['../a00829.html',1,'']]], + ['mcuxclrandom_5fconstants',['mcuxClRandom_Constants',['../a00830.html',1,'']]], + ['mcuxclrandom_5ffunctions',['mcuxClRandom_Functions',['../a00831.html',1,'']]], + ['mcuxclrandom_5fstatus_5f',['MCUXCLRANDOM_STATUS_',['../a00969.html',1,'']]], + ['mcuxclrandom_5ftypes',['mcuxClRandom_Types',['../a00832.html',1,'']]], + ['mcuxclrandom_5fconstants',['mcuxClRandom_Constants',['../a00833.html',1,'']]], + ['mcuxclrandommodes_5fmemoryconsumption',['mcuxClRandomModes_MemoryConsumption',['../a00838.html',1,'']]], + ['mcuxclrsa',['mcuxClRsa',['../a00839.html',1,'']]], + ['mcuxclrsa_5fconstants',['mcuxClRsa_Constants',['../a00840.html',1,'']]], + ['mcuxclrsa_5ffunctions',['mcuxClRsa_Functions',['../a00843.html',1,'']]], + ['mcuxclrsa_5fkey_5f',['MCUXCLRSA_KEY_',['../a00851.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fcrt_5fwa',['MCUXCLRSA_KEYGENERATION_CRT_WA',['../a00846.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fkey_5fdata_5fsize',['MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE',['../a00848.html',1,'']]], + ['mcuxclrsa_5fkeygeneration_5fplain_5fwa',['MCUXCLRSA_KEYGENERATION_PLAIN_WA',['../a00847.html',1,'']]], + ['mcuxclrsa_5fmacros',['mcuxClRsa_Macros',['../a00849.html',1,'']]], + ['mcuxclrsa_5foption_5f',['MCUXCLRSA_OPTION_',['../a00852.html',1,'']]], + ['mcuxclrsa_5fsign_5fmodes',['mcuxClRsa_Sign_Modes',['../a00841.html',1,'']]], + ['mcuxclrsa_5fsign_5fwa',['MCUXCLRSA_SIGN_WA',['../a00844.html',1,'']]], + ['mcuxclrsa_5fstatus_5f',['MCUXCLRSA_STATUS_',['../a00850.html',1,'']]], + ['mcuxclrsa_5ftypes',['mcuxClRsa_Types',['../a00853.html',1,'']]], + ['mcuxclrsa_5fverify_5fmodes',['mcuxClRsa_Verify_Modes',['../a00842.html',1,'']]], + ['mcuxclrsa_5fverify_5fwa',['MCUXCLRSA_VERIFY_WA',['../a00845.html',1,'']]], + ['mcuxclsession',['mcuxClSession',['../a00854.html',1,'']]], + ['mcuxclsession_5fconstants',['mcuxClSession_Constants',['../a00856.html',1,'']]], + ['mcuxclsession_5ffunctions',['mcuxClSession_Functions',['../a00855.html',1,'']]], + ['mcuxclsession_5ftypes',['mcuxClSession_Types',['../a00859.html',1,'']]], + ['mcux_20cssl_20_26ndash_3b_20api',['MCUX CSSL &ndash; API',['../a00860.html',1,'']]], + ['mcux_20cssl_20_26ndash_3b_20configurations',['MCUX CSSL &ndash; Configurations',['../a00864.html',1,'']]], + ['mcux_20cssl_20_26ndash_3b_20implementations',['MCUX CSSL &ndash; Implementations',['../a00866.html',1,'']]], + ['mcuxcssl_20memory_20api',['mcuxCssl Memory API',['../a00885.html',1,'']]], + ['mcuxcssl_20memory_20clear',['mcuxCssl Memory Clear',['../a00886.html',1,'']]], + ['mcuxcsslmemory_5fclear_20function_20definitions',['mcuxCsslMemory_Clear Function Definitions',['../a00887.html',1,'']]], + ['mcuxcssl_20memory_20compare',['mcuxCssl Memory Compare',['../a00888.html',1,'']]], + ['mcuxcsslmemory_5fcompare_20function_20definitions',['mcuxCsslMemory_Compare Function Definitions',['../a00889.html',1,'']]], + ['mcuxcssl_20memory_20copy',['mcuxCssl Memory Copy',['../a00890.html',1,'']]], + ['mcuxcsslmemory_5fcopy_20function_20definitions',['mcuxCsslMemory_Copy Function Definitions',['../a00891.html',1,'']]], + ['mcuxcssl_20memory_20set',['mcuxCssl Memory Set',['../a00892.html',1,'']]], + ['mcuxcsslmemory_5fset_20function_20definitions',['mcuxCsslMemory_Set Function Definitions',['../a00893.html',1,'']]], + ['mcuxcsslmemory_5ftypes',['mcuxCsslMemory_Types',['../a00894.html',1,'']]], + ['mcuxcsslmemory_5ftypes_5fmacros',['mcuxCsslMemory_Types_Macros',['../a00895.html',1,'']]], + ['mcuxcsslmemory_5ftypes_5ftypes',['mcuxCsslMemory_Types_Types',['../a00896.html',1,'']]], + ['mcuxcsslparamintegrity_20function_20definitions',['mcuxCsslParamIntegrity Function Definitions',['../a00900.html',1,'']]], + ['mcuxcsslparamintegrity_20macro_20definitions',['mcuxCsslParamIntegrity Macro Definitions',['../a00898.html',1,'']]], + ['mcuxcsslparamintegrity_20type_20definitions',['mcuxCsslParamIntegrity Type Definitions',['../a00899.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_a.html b/components/els_pkc/doc/mcxn/html/search/groups_a.html new file mode 100644 index 000000000..86d6b0099 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_a.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_a.js b/components/els_pkc/doc/mcxn/html/search/groups_a.js new file mode 100644 index 000000000..05d86edd6 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_a.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['one_2dshot_20cipher_20interfaces',['One-shot Cipher interfaces',['../a00674.html',1,'']]], + ['one_2dshot_20aead_20interfaces',['One-shot AEAD interfaces',['../a00664.html',1,'']]], + ['option_20bit_20field_20values_20that_20are_20needed_20for_20internal_20use_20only',['Option bit field values that are needed for internal use only',['../a00731.html',1,'']]], + ['one_2dshot_20mac_20interfaces',['One-shot MAC interfaces',['../a00797.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_b.html b/components/els_pkc/doc/mcxn/html/search/groups_b.html new file mode 100644 index 000000000..e06c79b5b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_b.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_b.js b/components/els_pkc/doc/mcxn/html/search/groups_b.js new file mode 100644 index 000000000..256380312 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_b.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['padding_20type_20definitions',['Padding type definitions',['../a00825.html',1,'']]], + ['parameter_20integrity_20api',['Parameter Integrity API',['../a00897.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_c.html b/components/els_pkc/doc/mcxn/html/search/groups_c.html new file mode 100644 index 000000000..5515baa09 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_c.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_c.js b/components/els_pkc/doc/mcxn/html/search/groups_c.js new file mode 100644 index 000000000..999369702 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_c.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['random_20interfaces',['Random interfaces',['../a00835.html',1,'']]], + ['random_20interfaces',['Random interfaces',['../a00837.html',1,'']]], + ['random_20patch_5fmode_20api',['Random PATCH_MODE API',['../a00834.html',1,'']]], + ['random_20test_5fmode_20api',['Random TEST_MODE API',['../a00836.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/groups_d.html b/components/els_pkc/doc/mcxn/html/search/groups_d.html new file mode 100644 index 000000000..1c191eba5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_d.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/groups_d.js b/components/els_pkc/doc/mcxn/html/search/groups_d.js new file mode 100644 index 000000000..04c6cce6e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/groups_d.js @@ -0,0 +1,23 @@ +var searchData= +[ + ['switching_20flow_20protection',['Switching flow protection',['../a00884.html',1,'']]], + ['switching_20flow_20protection',['Switching flow protection',['../a00875.html',1,'']]], + ['session_20rtf_20configuration_20values',['Session RTF configuration values',['../a00858.html',1,'']]], + ['session_20status_20values',['Session Status values',['../a00857.html',1,'']]], + ['secure_20counter_20api',['Secure Counter API',['../a00901.html',1,'']]], + ['secure_20counter_20configuration',['Secure Counter Configuration',['../a00906.html',1,'']]], + ['secure_20counter_3a_20disabled',['Secure Counter: Disabled',['../a00907.html',1,'']]], + ['secure_20counter_3a_20sw_20local',['Secure Counter: SW Local',['../a00912.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00902.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00904.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00905.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00903.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00908.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00910.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00911.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00909.html',1,'']]], + ['secure_20counter_20core_20functionality',['Secure counter core functionality',['../a00913.html',1,'']]], + ['secure_20counter_20decrement',['Secure counter decrement',['../a00915.html',1,'']]], + ['secure_20counter_20direct_20access',['Secure counter direct access',['../a00916.html',1,'']]], + ['secure_20counter_20increment',['Secure counter increment',['../a00914.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/mag_sel.png b/components/els_pkc/doc/mcxn/html/search/mag_sel.png new file mode 100644 index 0000000000000000000000000000000000000000..39c0ed52a25dd9d080ee0d42ae6c6042bdfa04d7 GIT binary patch literal 465 zcmeAS@N?(olHy`uVBq!ia0vp^B0wz6!2%?$TA$hhDVB6cUq=Rpjs4tz5?O(Kg=CK) zUj~NU84L`?eGCi_EEpJ?t}-xGu`@87+QPtK?83kxQ`TapwHK(CDaqU2h2ejD|C#+j z9%q3^WHAE+w=f7ZGR&GI0Tg5}@$_|Nf5gMiEhFgvHvB$N=!mC_V~EE2vzPXI9ZnEo zd+1zHor@dYLod2Y{ z@R$7$Z!PXTbY$|@#T!bMzm?`b<(R`cbw(gxJHzu zB$lLFB^RXvDF!10LknF)BV7aY5JN*NBMU1-b8Q0yD+2>vd*|CI8glbfGSez?Ylunu RoetE%;OXk;vd$@?2>>CYplSdB literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/search/nomatches.html b/components/els_pkc/doc/mcxn/html/search/nomatches.html new file mode 100644 index 000000000..437732089 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
+
No Matches
+
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/pages_0.html b/components/els_pkc/doc/mcxn/html/search/pages_0.html new file mode 100644 index 000000000..3d06b0521 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/pages_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/pages_0.js b/components/els_pkc/doc/mcxn/html/search/pages_0.js new file mode 100644 index 000000000..73cec8f2a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/pages_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['security_20and_20integration_20guidance_20manual',['Security and Integration Guidance Manual',['../a01321.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/pages_1.html b/components/els_pkc/doc/mcxn/html/search/pages_1.html new file mode 100644 index 000000000..06f1e40f0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/pages_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/pages_1.js b/components/els_pkc/doc/mcxn/html/search/pages_1.js new file mode 100644 index 000000000..2ffe4014e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/pages_1.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['user_20manual_20of_20crypto_20library_20normal_20secure_20_28clns_29',['User Manual of Crypto Library Normal Secure (CLNS)',['../index.html',1,'']]], + ['user_20guidance_20manual',['User Guidance Manual',['../a01320.html',1,'']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/search.css b/components/els_pkc/doc/mcxn/html/search/search.css new file mode 100644 index 000000000..a0dba441c --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/search.css @@ -0,0 +1,273 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#MSearchBox { + white-space : nowrap; + float: none; + margin-top: 0px; + right: 0px; + width: 170px; + height: 24px; + z-index: 102; + display: inline; + position: absolute; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:111px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; + -webkit-border-radius: 0px; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 10001; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; + z-index:10000; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.searchresult { + background-color: #F0F3F8; +} + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: url("../tab_a.png"); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + diff --git a/components/els_pkc/doc/mcxn/html/search/search.js b/components/els_pkc/doc/mcxn/html/search/search.js new file mode 100644 index 000000000..a554ab9cb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/search.js @@ -0,0 +1,814 @@ +/* + @licstart The following is the entire license notice for the + JavaScript code in this file. + + Copyright (C) 1997-2017 by Dimitri van Heesch + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + + @licend The above is the entire license notice + for the JavaScript code in this file + */ +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e(R!W8j_r#qQ#gnr4kAxdU#F0+OBry$Z+ z_0PMi;P|#{d%mw(dnw=jM%@$onTJa%@6Nm3`;2S#nwtVFJI#`U@2Q@@JCCctagvF- z8H=anvo~dTmJ2YA%wA6IHRv%{vxvUm|R)kgZeo zmX%Zb;mpflGZdXCTAgit`||AFzkI#z&(3d4(htA?U2FOL4WF6wY&TB#n3n*I4+hl| z*NBpo#FA92vEu822WQ%mvv4FO#qs` BFGc_W literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/search/search_r.png b/components/els_pkc/doc/mcxn/html/search/search_r.png new file mode 100644 index 0000000000000000000000000000000000000000..1af5d21ee13e070d7600f1c4657fde843b953a69 GIT binary patch literal 553 zcmeAS@N?(olHy`uVBq!ia0vp^LO?9c!2%@BXHTsJQY`6?zK#qG8~eHcB(ehe3dtTp zz6=bxGZ+|(`xqD=STHa&U1eaXVrO7DwS|Gf*oA>XrmV$GYcEhOQT(QLuS{~ooZ2P@v=Xc@RKW@Irliv8_;wroU0*)0O?temdsA~70jrdux+`@W7 z-N(<(C)L?hOO?KV{>8(jC{hpKsws)#Fh zvsO>IB+gb@b+rGWaO&!a9Z{!U+fV*s7TS>fdt&j$L%^U@Epd$~Nl7e8wMs5Z1yT$~ z28I^8hDN#u<{^fLRz?<9hUVG^237_Jy7tbuQ8eV{r(~v8;?@w8^gA7>fx*+&&t;uc GLK6VEQpiUD literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/search/searchdata.js b/components/els_pkc/doc/mcxn/html/search/searchdata.js new file mode 100644 index 000000000..32cb09eeb --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/searchdata.js @@ -0,0 +1,39 @@ +var indexSectionsWithContent = +{ + 0: "_abcdefghiklmoprstuvw", + 1: "m", + 2: "dm", + 3: "_mr", + 4: "_abcdefghiklmoprstuvw", + 5: "m", + 6: "emr", + 7: "abcdefhklmoprs", + 8: "su" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "typedefs", + 6: "defines", + 7: "groups", + 8: "pages" +}; + +var indexSectionLabels = +{ + 0: "All", + 1: "Data Structures", + 2: "Files", + 3: "Functions", + 4: "Variables", + 5: "Typedefs", + 6: "Macros", + 7: "Modules", + 8: "Pages" +}; + diff --git a/components/els_pkc/doc/mcxn/html/search/typedefs_0.html b/components/els_pkc/doc/mcxn/html/search/typedefs_0.html new file mode 100644 index 000000000..3848b20e9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/typedefs_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/typedefs_0.js b/components/els_pkc/doc/mcxn/html/search/typedefs_0.js new file mode 100644 index 000000000..e27fb14d8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/typedefs_0.js @@ -0,0 +1,91 @@ +var searchData= +[ + ['mcuxcl_5fbuffer_5ft',['mcuxCl_Buffer_t',['../a00678.html#gaa29a7ef1a28440e75f2c0d007011ae2b',1,'mcuxClCore_Buffer.h']]], + ['mcuxcl_5finputbuffer_5ft',['mcuxCl_InputBuffer_t',['../a00678.html#gae1ad733bc1a05d9dc6e9fb8b0e9b436d',1,'mcuxClCore_Buffer.h']]], + ['mcuxclaead_5fcontext_5ft',['mcuxClAead_Context_t',['../a00666.html#gaf67b42507181f9793498bfaaab35a48a',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fmode_5ft',['mcuxClAead_Mode_t',['../a00666.html#ga8084949e97b9ab9cd35ac041b8bbea0a',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fmodedescriptor_5ft',['mcuxClAead_ModeDescriptor_t',['../a00666.html#ga8378bbf26468fde8248b08efca599481',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5fstatus_5ft',['mcuxClAead_Status_t',['../a00666.html#ga1497c344a218545c5980a407e7c9194d',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5ftest_5ft',['mcuxClAead_Test_t',['../a00666.html#gab0222b5a8fcc204e08515b0b558fb5fe',1,'mcuxClAead_Types.h']]], + ['mcuxclaead_5ftestdescriptor_5ft',['mcuxClAead_TestDescriptor_t',['../a00666.html#gae182daa83ee8ec992f261f2b52b20adb',1,'mcuxClAead_Types.h']]], + ['mcuxclcipher_5fcontext_5ft',['mcuxClCipher_Context_t',['../a00676.html#ga9faa78dbb34107f8f28344b36b91c93d',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fmode_5ft',['mcuxClCipher_Mode_t',['../a00676.html#gacd434e81399ac5f9752f61d55ecfb305',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fmodedescriptor_5ft',['mcuxClCipher_ModeDescriptor_t',['../a00676.html#gaa9586d961025bb80660a563be606451e',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5fstatus_5ft',['mcuxClCipher_Status_t',['../a00676.html#gadcf65a3850bca1bd4059213edf23df4f',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5ftest_5ft',['mcuxClCipher_Test_t',['../a00676.html#ga2d2ad865d5d552ea37a471acb2c48a74',1,'mcuxClCipher_Types.h']]], + ['mcuxclcipher_5ftestdescriptor_5ft',['mcuxClCipher_TestDescriptor_t',['../a00676.html#gae10b2dde7d4883d6992adb3e23d57714',1,'mcuxClCipher_Types.h']]], + ['mcuxclecc_5feddsa_5fdomainparams_5ft',['mcuxClEcc_EdDSA_DomainParams_t',['../a00686.html#ga365359e63f156889e46845381455b321',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fgeneratekeypairdescriptor_5ft',['mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t',['../a00686.html#gadee46209e43c63814a86e882b3927b27',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5feddsa_5fsignatureprotocoldescriptor_5ft',['mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t',['../a00686.html#gaec003d78ecf36673f595fcc87f11b82c',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fmontdh_5fdomainparams_5ft',['mcuxClEcc_MontDH_DomainParams_t',['../a00686.html#ga52205a42d2027ba1c3ec49589f9f0b8c',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5fprotected_5ft',['mcuxClEcc_Status_Protected_t',['../a00685.html#ga3900d9bdb95a061d26b71f300318b6a1',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fstatus_5ft',['mcuxClEcc_Status_t',['../a00685.html#gaf044f4a5eeeecc4ec5b01aed19f2fe41',1,'mcuxClEcc_Types.h']]], + ['mcuxclecc_5fweier_5fdomainparams_5ft',['mcuxClEcc_Weier_DomainParams_t',['../a00686.html#gafe84edad82c8934ef1634e9f29effa55',1,'mcuxClEcc_Types.h']]], + ['mcuxclels_5feccbyte_5ft',['mcuxClEls_EccByte_t',['../a00733.html#gaaca57cf87336b1e866852443c47a019f',1,'mcuxClEls_Ecc.h']]], + ['mcuxclels_5ferrorhandling_5ft',['mcuxClEls_ErrorHandling_t',['../a00716.html#ga3411a9581b6770690eba6acc6b69c278',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fkeyindex_5ft',['mcuxClEls_KeyIndex_t',['../a00768.html#ga769227492b28ef0d58a94b202113cee8',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fresetoption_5ft',['mcuxClEls_ResetOption_t',['../a00716.html#gab1ed08db7ad22b92ac714d17566d2fff',1,'mcuxClEls_Common.h']]], + ['mcuxclels_5fstatus_5fprotected_5ft',['mcuxClEls_Status_Protected_t',['../a00768.html#ga9d1e537d1dc0c3eda9c26ba9e82e0596',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5fstatus_5ft',['mcuxClEls_Status_t',['../a00768.html#ga734d7200290fe0eda6ef3347f52177f3',1,'mcuxClEls_Types.h']]], + ['mcuxclels_5ftransfertoregisterfunction_5ft',['mcuxClEls_TransferToRegisterFunction_t',['../a00768.html#gacb342d252ea80b11e90b781c5e1aa331',1,'mcuxClEls_Types.h']]], + ['mcuxclhash_5falgo_5ft',['mcuxClHash_Algo_t',['../a00773.html#ga0ffeeb89c76da6470176e7621713e1b2',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5falgorithmdescriptor_5ft',['mcuxClHash_AlgorithmDescriptor_t',['../a00773.html#gacccec0a811d221d2cb0fd8416da271d8',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fcontext_5ft',['mcuxClHash_Context_t',['../a00773.html#ga84c437ceb6b43a992b75866f793d0956',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fcontextdescriptor_5ft',['mcuxClHash_ContextDescriptor_t',['../a00773.html#ga90ff7c4f43e59b80eca542e35722124c',1,'mcuxClHash_Types.h']]], + ['mcuxclhash_5fstatus_5ft',['mcuxClHash_Status_t',['../a00773.html#gacdfd7a833fcd06684a73c22364e89b7c',1,'mcuxClHash_Types.h']]], + ['mcuxclkey_5falgorithmid_5ft',['mcuxClKey_AlgorithmId_t',['../a00793.html#ga322cbacb57f10aa6cb6731d64d4e64e3',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fcustomtype_5ft',['mcuxClKey_CustomType_t',['../a00793.html#ga4249d6ccc1dab6d15b46270da3c3d6d4',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fdescriptor_5ft',['mcuxClKey_Descriptor_t',['../a00793.html#ga1b7557c7a8892e65d43b90f8d6226d6a',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fgeneration_5ft',['mcuxClKey_Generation_t',['../a00793.html#gabb1e565ab474265cf8b53be6d9a1f758',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fgenerationdescriptor_5ft',['mcuxClKey_GenerationDescriptor_t',['../a00793.html#gaad2bc2272e961dd28dba4697d9287a14',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fhandle_5ft',['mcuxClKey_Handle_t',['../a00793.html#gafe84fa2aa66094f542164e0627a54c5d',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fprotection_5ft',['mcuxClKey_Protection_t',['../a00793.html#gab16fa58359f9994921f5d4a58c597c66',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fprotectiondescriptor_5ft',['mcuxClKey_ProtectionDescriptor_t',['../a00793.html#ga1c51acf51723d52dbcdc1a0f80f98572',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fsize_5ft',['mcuxClKey_Size_t',['../a00793.html#ga90c030f08081016123496c56021b9bab',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fstatus_5fprotected_5ft',['mcuxClKey_Status_Protected_t',['../a00793.html#ga9886ee2d82f96093ad0a39385452cdfb',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5fstatus_5ft',['mcuxClKey_Status_t',['../a00793.html#gaa19905c3963849a56ee26a9b0e5013f5',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5ftype_5ft',['mcuxClKey_Type_t',['../a00793.html#ga9ea75aa8fe6ddb914d91b170bb5d8be5',1,'mcuxClKey_Types.h']]], + ['mcuxclkey_5ftypedescriptor_5ft',['mcuxClKey_TypeDescriptor_t',['../a00793.html#gae9a4d21e5a5239fd0ef48978a3774a89',1,'mcuxClKey_Types.h']]], + ['mcuxclmac_5fcontext_5ft',['mcuxClMac_Context_t',['../a00799.html#gaf804dbff6e0d68d2d877b21995ed5c34',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fcustommode_5ft',['mcuxClMac_CustomMode_t',['../a00799.html#ga55e9279a13efd1dd87affcc88f3eb34a',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fmode_5ft',['mcuxClMac_Mode_t',['../a00799.html#ga8e9aa3b88af43aaf819650568abc471f',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fmodedescriptor_5ft',['mcuxClMac_ModeDescriptor_t',['../a00799.html#gaad5e6326d43f28d324ef2d98ac3ad2cc',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5fstatus_5ft',['mcuxClMac_Status_t',['../a00799.html#gaca63aa917056a18f99a911f329f3971b',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ftest_5ft',['mcuxClMac_Test_t',['../a00799.html#ga0af47561198575f7792301a2a5135e75',1,'mcuxClMac_Types.h']]], + ['mcuxclmac_5ftestdescriptor_5ft',['mcuxClMac_TestDescriptor_t',['../a00799.html#ga05358be86e9c9b69f46225171d63f406',1,'mcuxClMac_Types.h']]], + ['mcuxclmath_5fstatus_5fprotected_5ft',['mcuxClMath_Status_Protected_t',['../a00807.html#ga0560097c958abffba7b41198a7af6c8b',1,'mcuxClMath_Types.h']]], + ['mcuxclmath_5fstatus_5ft',['mcuxClMath_Status_t',['../a00807.html#gaf541274a57cf9f823c029f73ff733ae0',1,'mcuxClMath_Types.h']]], + ['mcuxclmemory_5fstatus_5fprotected_5ft',['mcuxClMemory_Status_Protected_t',['../a00814.html#ga57c9ba76c62b4ad9bd565df4a98c19ba',1,'mcuxClMemory_Types.h']]], + ['mcuxclmemory_5fstatus_5ft',['mcuxClMemory_Status_t',['../a00814.html#gad25887c99517f13c547e1d2bf027ccd1',1,'mcuxClMemory_Types.h']]], + ['mcuxcloscca_5fmpint_5ft',['mcuxClOscca_MPInt_t',['../a00485.html#a167ac5bec44e63a398cce013bd85476f',1,'mcuxClOscca_Types.h']]], + ['mcuxcloscca_5frng_5fctx_5ft',['mcuxClOscca_Rng_Ctx_t',['../a00485.html#ab3464aacd01247830fe9a57570620d23',1,'mcuxClOscca_Types.h']]], + ['mcuxclosccapkc_5fptrfupentry_5ft',['mcuxClOsccaPkc_PtrFUPEntry_t',['../a00818.html#gae42a19bfc4e7aaa16fdea5ef1e6bc6c4',1,'mcuxClOsccaPkc_Functions.h']]], + ['mcuxclosccapkc_5fstate_5ft',['mcuxClOsccaPkc_State_t',['../a00818.html#ga83f8544bc01ae0f871addbfe5600e706',1,'mcuxClOsccaPkc_Functions.h']]], + ['mcuxclpadding_5fstatus_5ft',['mcuxClPadding_Status_t',['../a00825.html#ga965eb15986e53917365f3f3b769e0968',1,'mcuxClPadding_Types.h']]], + ['mcuxclpkc_5fptrfupentry_5ft',['mcuxClPkc_PtrFUPEntry_t',['../a00965.html#ga9c5b69d5d2b5e9b7551de9cbe163050f',1,'mcuxClPkc_Functions.h']]], + ['mcuxclpkc_5fstatus_5fprotected_5ft',['mcuxClPkc_Status_Protected_t',['../a00967.html#gaaee98013327cc5777f68c6b9fdb1ef6d',1,'mcuxClPkc_Types.h']]], + ['mcuxclpkc_5fstatus_5ft',['mcuxClPkc_Status_t',['../a00967.html#ga9382ab1c4689794b50a3b75ad39a350c',1,'mcuxClPkc_Types.h']]], + ['mcuxclrandom_5fconfig_5ft',['mcuxClRandom_Config_t',['../a00832.html#gaf1284eaa96ef47c06697f95e74ffc3ee',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fcontext_5ft',['mcuxClRandom_Context_t',['../a00832.html#gac2ce3a52788240794afde522cfad65c5',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fcontextdescriptor_5ft',['mcuxClRandom_ContextDescriptor_t',['../a00832.html#gab409cd7b1e5a4da822bf9ae43d00c79c',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fmode_5ft',['mcuxClRandom_Mode_t',['../a00832.html#ga2998181a66cbdc063aa08d76e5fdef9d',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fmodedescriptor_5ft',['mcuxClRandom_ModeDescriptor_t',['../a00832.html#gadcfae984a95f3e98617ca5fb9767f5cd',1,'mcuxClRandom_Types.h']]], + ['mcuxclrandom_5fstatus_5ft',['mcuxClRandom_Status_t',['../a00832.html#ga768ea9930242003d2a68991684a1e948',1,'mcuxClRandom_Types.h']]], + ['mcuxclrsa_5fkey',['mcuxClRsa_Key',['../a00853.html#gaa10abda6e87540ddd4db42c84aa5f8f5',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fkeyentry',['mcuxClRsa_KeyEntry',['../a00853.html#ga45ab9e1108bb7a629af14c74d8392622',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fsignverifymode',['mcuxClRsa_SignVerifyMode',['../a00853.html#ga9135a8d95f26a1b90c7a251886bce7e5',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fsignverifymode_5ft',['mcuxClRsa_SignVerifyMode_t',['../a00853.html#gabe334b37ac763b3943364b26e130d0df',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5fprotected_5ft',['mcuxClRsa_Status_Protected_t',['../a00853.html#ga60189e258e6739b78e900b025be0ab34',1,'mcuxClRsa_Types.h']]], + ['mcuxclrsa_5fstatus_5ft',['mcuxClRsa_Status_t',['../a00853.html#gab654093108d59a4690e464f314356e69',1,'mcuxClRsa_Types.h']]], + ['mcuxclsession_5fdescriptor_5ft',['mcuxClSession_Descriptor_t',['../a00859.html#gafe6e209ab6b552af2011043383473f18',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fhandle_5ft',['mcuxClSession_Handle_t',['../a00859.html#ga17fd337618b05459b4a343393e099b56',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5frtf_5ft',['mcuxClSession_Rtf_t',['../a00859.html#gac635eeca4268dbd500e45806ee37f685',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fsecuritycontext_5ft',['mcuxClSession_SecurityContext_t',['../a00859.html#gac2866aae4d5a869b0fa55c82190d0c93',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fsecurityoptions_5ft',['mcuxClSession_SecurityOptions_t',['../a00859.html#gabd24855c86970aaa97d3c6975a8ca53c',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5fprotected_5ft',['mcuxClSession_Status_Protected_t',['../a00859.html#ga09bbfe382aac167ec94e8e6e3d2b10f6',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fstatus_5ft',['mcuxClSession_Status_t',['../a00859.html#ga9f2ec672d5a5fe92159f0e6159e04e4e',1,'mcuxClSession_Types.h']]], + ['mcuxclsession_5fworkarea_5ft',['mcuxClSession_WorkArea_t',['../a00859.html#ga13a1a61b81f8b8bdc5272d33b44a2dac',1,'mcuxClSession_Types.h']]], + ['mcuxcsslmemory_5fstatus_5ft',['mcuxCsslMemory_Status_t',['../a00896.html#ga19c7a1367cb21d7bcb720607f495d86c',1,'mcuxCsslMemory_Types.h']]], + ['mcuxcsslparamintegrity_5fassertioncpuwordsize_5ft',['mcuxCsslParamIntegrity_AssertionCpuWordSize_t',['../a00899.html#gaf2a8a66e39dd0d33d085d3d412cafb96',1,'mcuxCsslParamIntegrity.h']]], + ['mcuxcsslparamintegrity_5fchecksum_5ft',['mcuxCsslParamIntegrity_Checksum_t',['../a00899.html#ga6a229130320b395fbb8a8a76a361bd1e',1,'mcuxCsslParamIntegrity.h']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_0.html b/components/els_pkc/doc/mcxn/html/search/variables_0.html new file mode 100644 index 000000000..12104bcb5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_0.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_0.js b/components/els_pkc/doc/mcxn/html/search/variables_0.js new file mode 100644 index 000000000..d209116fd --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_0.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['_5f_5fpad0_5f_5f',['__pad0__',['../a00997.html#a55a86ab29b1e20072f48c56470568824',1,'mcuxClEls_AeadOption_t::__pad0__()'],['../a01009.html#abb6ec00ab841f6edcc37f6f51fb35975',1,'mcuxClEls_CipherOption_t::__pad0__()'],['../a01021.html#add5bf1feb8f2a41a0f46c1bb06f15db0',1,'mcuxClEls_CmacOption_t::__pad0__()'],['../a01033.html#a3f71ee0da1f604f06bce53faaee88549',1,'mcuxClEls_HwVersion_t::__pad0__()'],['../a01045.html#ae4d9f2540dc7380b776ff6de6325c22f',1,'mcuxClEls_HwState_t::__pad0__()'],['../a01057.html#a71d456bef9a7a21d8ff55bc711a6a3bc',1,'mcuxClEls_InterruptOptionEn_t::__pad0__()'],['../a01069.html#ad560c85d9ea7975330ec5a2e207b30c0',1,'mcuxClEls_InterruptOptionRst_t::__pad0__()'],['../a01081.html#a6f7f7fb21a47e0ba886c9c5ebdaae7bf',1,'mcuxClEls_InterruptOptionSet_t::__pad0__()'],['../a01093.html#aa06967699abb851f567edb7ae687a0d2',1,'mcuxClEls_HwConfig_t::__pad0__()'],['../a01105.html#a49e0d7b8ada89de5bd766ac9cf2c3e27',1,'mcuxClEls_CommandCrcConfig_t::__pad0__()'],['../a01117.html#a0e9a4b194d887a2b2c4c2297c2cbd868',1,'mcuxClEls_EccSignOption_t::__pad0__()'],['../a01129.html#a7dffb127ef2f32236227c9023af7e5cd',1,'mcuxClEls_EccVerifyOption_t::__pad0__()'],['../a01141.html#ab6d97c184d6c34f0d6c1bc8e0a77057c',1,'mcuxClEls_EccKeyGenOption_t::__pad0__()'],['../a01153.html#a98a12e39b9f189c172f6b951c2ae781c',1,'mcuxClEls_EccKeyExchOption_t::__pad0__()'],['../a01165.html#aae0a2c87c57c974e9cb7a55126f95ca9',1,'mcuxClEls_HashOption_t::__pad0__()'],['../a01177.html#a590b1d47d31c598e6df237437a015b8e',1,'mcuxClEls_HmacOption_t::__pad0__()'],['../a01225.html#a2dfcb81e1476a07a6ab67f8c090b4ab5',1,'mcuxClEls_KeyImportOption_t::__pad0__()'],['../a01237.html#aef07ed5cdd67e69b2862d98fa9ce2bf2',1,'mcuxClEls_KeyProp_t::__pad0__()']]], + ['_5f_5fpad1_5f_5f',['__pad1__',['../a00997.html#a6b276f4a8ddbf8c2f337ad23c52d6963',1,'mcuxClEls_AeadOption_t::__pad1__()'],['../a01009.html#a8b8096d5f06a8f303976697a0fa369aa',1,'mcuxClEls_CipherOption_t::__pad1__()'],['../a01021.html#ace1fa4ccaa7741b93563ac6ace23989d',1,'mcuxClEls_CmacOption_t::__pad1__()'],['../a01045.html#aacebdfe99f0d29f126adc2a9d42a4b22',1,'mcuxClEls_HwState_t::__pad1__()'],['../a01057.html#a502fdb51eeb304aabfd1ed4550ac3258',1,'mcuxClEls_InterruptOptionEn_t::__pad1__()'],['../a01069.html#a188253366e073fdcbdccbaa41ccbe915',1,'mcuxClEls_InterruptOptionRst_t::__pad1__()'],['../a01081.html#a3a1d6b3eaa5f8be52531ddb20f3e85c8',1,'mcuxClEls_InterruptOptionSet_t::__pad1__()'],['../a01117.html#a5527caf737b06f5053f89c60354dbe65',1,'mcuxClEls_EccSignOption_t::__pad1__()'],['../a01129.html#ad2bdfda87da142b43bfd1e64ee8bb072',1,'mcuxClEls_EccVerifyOption_t::__pad1__()'],['../a01153.html#a06d0377a60794946f8788a7fad8af177',1,'mcuxClEls_EccKeyExchOption_t::__pad1__()'],['../a01165.html#a97d346a2d66df4edd1ab677769a7b648',1,'mcuxClEls_HashOption_t::__pad1__()'],['../a01177.html#afa33782e670b9a44a28f71cb097ad830',1,'mcuxClEls_HmacOption_t::__pad1__()'],['../a01225.html#ad67985d38d1563a926768316825e1944',1,'mcuxClEls_KeyImportOption_t::__pad1__()'],['../a01237.html#aba08650854846dd1ef4788c1a8ef0c58',1,'mcuxClEls_KeyProp_t::__pad1__()']]], + ['_5f_5fpad2_5f_5f',['__pad2__',['../a00997.html#ae06263ba435ff9824be1f20c8f20b96c',1,'mcuxClEls_AeadOption_t::__pad2__()'],['../a01009.html#a568f1ef7bba7f45209bf0cf43bb66b45',1,'mcuxClEls_CipherOption_t::__pad2__()'],['../a01045.html#a68593765ff0c58861d600be91ee332a3',1,'mcuxClEls_HwState_t::__pad2__()'],['../a01153.html#a82f1e57ea7fcdfd607a3954396e6ec84',1,'mcuxClEls_EccKeyExchOption_t::__pad2__()'],['../a01225.html#a05660839da43298f12f96572bf538330',1,'mcuxClEls_KeyImportOption_t::__pad2__()']]], + ['_5f_5fpad3_5f_5f',['__pad3__',['../a01045.html#a240bdaa5a99cd057983b3cbe28e33fb1',1,'mcuxClEls_HwState_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_1.html b/components/els_pkc/doc/mcxn/html/search/variables_1.html new file mode 100644 index 000000000..b784017a1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_1.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_1.js b/components/els_pkc/doc/mcxn/html/search/variables_1.js new file mode 100644 index 000000000..88cd3c04d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_1.js @@ -0,0 +1,12 @@ +var searchData= +[ + ['acpmod',['acpmod',['../a00997.html#a2504aa4fde601569a6c27276e76802f3',1,'mcuxClEls_AeadOption_t']]], + ['acpsie',['acpsie',['../a00997.html#a5fafad6f592dfb928316273b5ccbec12',1,'mcuxClEls_AeadOption_t']]], + ['acpsoe',['acpsoe',['../a00997.html#a77636eb7e553de47143580de37585920',1,'mcuxClEls_AeadOption_t']]], + ['aes128_5fexpected_5foutput',['aes128_expected_output',['../a00002.html#a8f724484dd059cbe14851b0a799c0890',1,'aes128_expected_output(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#a8f724484dd059cbe14851b0a799c0890',1,'aes128_expected_output(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['aes128_5finput',['aes128_input',['../a00002.html#ad27e8e7cceb19331fe1611f2eeb66dc8',1,'aes128_input(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#ad27e8e7cceb19331fe1611f2eeb66dc8',1,'aes128_input(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['aes128_5fiv',['aes128_iv',['../a00005.html#a8eef9cffb37af88e29a455967c68e7bc',1,'aes128_iv(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00041.html#aef268ff45a3b41fd6678cfeaf409151e',1,'aes128_iv(): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['aes128_5fkey',['aes128_key',['../a00002.html#af381139a6e72029d4fa91365ecd128dc',1,'aes128_key(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#af381139a6e72029d4fa91365ecd128dc',1,'aes128_key(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c'],['../a00041.html#afd0e33c5f8fc3670f63b637fb2febba4',1,'aes128_key(): mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['aes128_5foutput',['aes128_output',['../a00002.html#aac664c77a3ccf9254ab1afd4ce762854',1,'aes128_output(): mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c'],['../a00005.html#aac664c77a3ccf9254ab1afd4ce762854',1,'aes128_output(): mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c']]], + ['authciphersup',['authciphersup',['../a01093.html#acd5dabf360244a33333e3063010ad26d',1,'mcuxClEls_HwConfig_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_10.html b/components/els_pkc/doc/mcxn/html/search/variables_10.html new file mode 100644 index 000000000..308afd51e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_10.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_10.js b/components/els_pkc/doc/mcxn/html/search/variables_10.js new file mode 100644 index 000000000..2499a0283 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_10.js @@ -0,0 +1,21 @@ +var searchData= +[ + ['securitycounter',['securityCounter',['../a01281.html#a3bca2e1ffbfa74a0afd525444dee8f16',1,'mcuxClSession_SecurityContext']]], + ['sha224_5fpadded_5finput',['sha224_padded_input',['../a00014.html#a3a90d0719630869e92e2a830633b3276',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha224_5freference_5fdigest',['sha224_reference_digest',['../a00014.html#abf0bb6879a755eadc984fc84923cc0bf',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha256_5fpadded_5finput',['sha256_padded_input',['../a00017.html#a890aa9aa5c130271cfeb0c43324c4e51',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha256_5freference_5fdigest',['sha256_reference_digest',['../a00017.html#ab00b3a897c4bba2fc29a541a23c4a0ea',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha2_5f224_5fdigest',['sha2_224_digest',['../a00014.html#ad953a0e00811066696ef763b14c096f9',1,'mcuxClEls_Hash_Sha224_One_Block_example.c']]], + ['sha2_5f256_5fdigest',['sha2_256_digest',['../a00017.html#aff61e539755c5c8c4b21046c976abdfa',1,'mcuxClEls_Hash_Sha256_One_Block_example.c']]], + ['sha2_5f384_5fdigest',['sha2_384_digest',['../a00020.html#a4fdd7260badc8d686d79df408edb7c21',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha2_5f512_5fdigest',['sha2_512_digest',['../a00023.html#a0d806e17a1cf2005916602c6ebd303f2',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sha384_5fpadded_5finput',['sha384_padded_input',['../a00020.html#a157042750820e99bfa2441a0fcba481e',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha384_5freference_5fdigest',['sha384_reference_digest',['../a00020.html#a031991d5ae2823da0e9b5bd7c854e9b3',1,'mcuxClEls_Hash_Sha384_One_Block_example.c']]], + ['sha512_5fpadded_5finput',['sha512_padded_input',['../a00023.html#aa6ed8b927262ff98775b8726955ef8e0',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sha512_5freference_5fdigest',['sha512_reference_digest',['../a00023.html#a1e3cfc0c29a9863abf6ecd8c022d05ab',1,'mcuxClEls_Hash_Sha512_One_Block_example.c']]], + ['sie',['sie',['../a01021.html#ab165c41c5cf41abf2b463ab742fa0c1b',1,'mcuxClEls_CmacOption_t']]], + ['signrtf',['signrtf',['../a01117.html#aa4bcc3f1aaf9e991e62cdc22ffd7500e',1,'mcuxClEls_EccSignOption_t']]], + ['size',['size',['../a01277.html#a372ca932239a945030d51a23913c36e0',1,'mcuxClSession_WorkArea']]], + ['skip_5fpbk',['skip_pbk',['../a01141.html#afa4cb29e6c55e30a30185180de2f8e49',1,'mcuxClEls_EccKeyGenOption_t']]], + ['soe',['soe',['../a01021.html#a69e48d5d1edf8300761b237872e4192f',1,'mcuxClEls_CmacOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_11.html b/components/els_pkc/doc/mcxn/html/search/variables_11.html new file mode 100644 index 000000000..c27682770 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_11.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_11.js b/components/els_pkc/doc/mcxn/html/search/variables_11.js new file mode 100644 index 000000000..104edad6e --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_11.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['tlsinitsup',['tlsinitsup',['../a01093.html#a9dc24a8f88688b9d4cc5c305acbf46e5',1,'mcuxClEls_HwConfig_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_12.html b/components/els_pkc/doc/mcxn/html/search/variables_12.html new file mode 100644 index 000000000..bad4c794f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_12.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_12.js b/components/els_pkc/doc/mcxn/html/search/variables_12.js new file mode 100644 index 000000000..7c7a96de0 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_12.js @@ -0,0 +1,21 @@ +var searchData= +[ + ['uaes',['uaes',['../a01237.html#a18d3c3d356100d7bd01a9950c1f7b81e',1,'mcuxClEls_KeyProp_t']]], + ['uckdf',['uckdf',['../a01237.html#a3bdb1b36f76fe81225b14896d3429147',1,'mcuxClEls_KeyProp_t']]], + ['ucmac',['ucmac',['../a01237.html#acceecb25ef42cd4017edfc9095272b3d',1,'mcuxClEls_KeyProp_t']]], + ['uecdh',['uecdh',['../a01237.html#af513bad0dfe63b94b601adae2590ef17',1,'mcuxClEls_KeyProp_t']]], + ['uecsg',['uecsg',['../a01237.html#adb18f3c09ac78e8d74f2ff9563da084b',1,'mcuxClEls_KeyProp_t']]], + ['uhkdf',['uhkdf',['../a01237.html#a983d6a05d50a4e6eeb929ecfab1c5ca0',1,'mcuxClEls_KeyProp_t']]], + ['uhmac',['uhmac',['../a01237.html#ae8e6215c6390b64024f5bb71d09013a6',1,'mcuxClEls_KeyProp_t']]], + ['uhwo',['uhwo',['../a01237.html#a08b731503e03ee90d1904cbb88e9c37c',1,'mcuxClEls_KeyProp_t']]], + ['ukgsrc',['ukgsrc',['../a01237.html#ac4fbcd8af04b845353857e27ae6e90b8',1,'mcuxClEls_KeyProp_t']]], + ['uksk',['uksk',['../a01237.html#a1c20ef8f869a090cc90472821adba513',1,'mcuxClEls_KeyProp_t']]], + ['ukuok',['ukuok',['../a01237.html#ab0fe394151ed388fa03198d5710bc0d1',1,'mcuxClEls_KeyProp_t']]], + ['ukwk',['ukwk',['../a01237.html#a006a40e53f4859e41e4b4ec5424c6c26',1,'mcuxClEls_KeyProp_t']]], + ['upprot_5fpriv',['upprot_priv',['../a01237.html#a50d3bbaabf919fab908e2ae83fe5a5ab',1,'mcuxClEls_KeyProp_t']]], + ['upprot_5fsec',['upprot_sec',['../a01237.html#a0d130be83d337e7a5d9ef56f4a92f3a0',1,'mcuxClEls_KeyProp_t']]], + ['urtf',['urtf',['../a01237.html#a32ac519b2729fc88babaaf23ecfb6523',1,'mcuxClEls_KeyProp_t']]], + ['used',['used',['../a01277.html#ab3280a7d27aa7837287e2fa4376492fb',1,'mcuxClSession_WorkArea']]], + ['utlsms',['utlsms',['../a01237.html#a5f7b5dc8e882536c83ff87ac246ca6ed',1,'mcuxClEls_KeyProp_t']]], + ['utlspms',['utlspms',['../a01237.html#a30f2161747c56e0de99561d38885be7e',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_13.html b/components/els_pkc/doc/mcxn/html/search/variables_13.html new file mode 100644 index 000000000..ef6d36cf3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_13.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_13.js b/components/els_pkc/doc/mcxn/html/search/variables_13.js new file mode 100644 index 000000000..b37bf271b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_13.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['value',['value',['../a00997.html#ac8b3278eb96cd5ca0e15b9b2318305a7',1,'mcuxClEls_AeadOption_t::value()'],['../a01009.html#a1c724d7ce478fcbb4cdd0ccb5c1fd899',1,'mcuxClEls_CipherOption_t::value()'],['../a01021.html#ab326f666bbbcabd39dc0bd26a83fa5c0',1,'mcuxClEls_CmacOption_t::value()'],['../a01033.html#a5e9b7103d2b419e9d860c04eb142d6e2',1,'mcuxClEls_HwVersion_t::value()'],['../a01045.html#a9e0ca3d1f7797c407e594e55411549b0',1,'mcuxClEls_HwState_t::value()'],['../a01057.html#a24184dcdf86670224ea536fc20a0e4d8',1,'mcuxClEls_InterruptOptionEn_t::value()'],['../a01069.html#afe633f619c2da24bd5a99cf97782924b',1,'mcuxClEls_InterruptOptionRst_t::value()'],['../a01081.html#a58934a4a256905327206ee08d8c5931f',1,'mcuxClEls_InterruptOptionSet_t::value()'],['../a01093.html#a2cf565902d36ad357eaaa793eb4be8d5',1,'mcuxClEls_HwConfig_t::value()'],['../a01105.html#a4dc44ca29e9ef4bcea0b6469a5966f6d',1,'mcuxClEls_CommandCrcConfig_t::value()'],['../a01117.html#a7e32d20de26a1ca2d7eee8fe2fd95456',1,'mcuxClEls_EccSignOption_t::value()'],['../a01129.html#a73b0b8e42d753a97bb03cb053799e33a',1,'mcuxClEls_EccVerifyOption_t::value()'],['../a01141.html#a2c377cdae550923ee7e1234735e08b40',1,'mcuxClEls_EccKeyGenOption_t::value()'],['../a01153.html#aaa4e256f25f9c74123c28c5926d21ba2',1,'mcuxClEls_EccKeyExchOption_t::value()'],['../a01165.html#a71c7896e79c292ac111d85992a16c78d',1,'mcuxClEls_HashOption_t::value()'],['../a01177.html#a577065f77e409f612e5a2fc2072b971d',1,'mcuxClEls_HmacOption_t::value()'],['../a01189.html#a00abd43e6b7c9816562f2aa1d93c0b9e',1,'mcuxClEls_CkdfOption_t::value()'],['../a01201.html#aa39e185af4b2cfd758c0b7b7d3bea8db',1,'mcuxClEls_HkdfOption_t::value()'],['../a01213.html#acfe68053c7558c29e085ca434cf432cd',1,'mcuxClEls_TlsOption_t::value()'],['../a01225.html#ad5bfabd7e1e04a95627e0cbc144afdcb',1,'mcuxClEls_KeyImportOption_t::value()'],['../a01237.html#af184a952f255348629f27f24c0fd0bd9',1,'mcuxClEls_KeyProp_t::value()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_14.html b/components/els_pkc/doc/mcxn/html/search/variables_14.html new file mode 100644 index 000000000..305ea5376 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_14.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_14.js b/components/els_pkc/doc/mcxn/html/search/variables_14.js new file mode 100644 index 000000000..e671a6f89 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_14.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['wnumbytes',['wNumBytes',['../a01253.html#aa8adc5c5c0851f5adc6abd44edf06d1c',1,'mcuxClOscca_MPInt_t']]], + ['word',['word',['../a00997.html#a6a1cf6dca7babcb5b673312d79c3db9e',1,'mcuxClEls_AeadOption_t::word()'],['../a01009.html#afd7050544cd985c2dda66061e0f0c44f',1,'mcuxClEls_CipherOption_t::word()'],['../a01021.html#aa34c3bf115a202c3c96b967bc6114498',1,'mcuxClEls_CmacOption_t::word()'],['../a01033.html#a87650934fb456d15383c0e0de64f93b2',1,'mcuxClEls_HwVersion_t::word()'],['../a01045.html#a8318bd94bd3469bac07874ba2921d0cf',1,'mcuxClEls_HwState_t::word()'],['../a01057.html#ad7e19b6dde1c236ad751eb9208e942db',1,'mcuxClEls_InterruptOptionEn_t::word()'],['../a01069.html#ad45dfa4c603c021060fc0b4fdf0f769d',1,'mcuxClEls_InterruptOptionRst_t::word()'],['../a01081.html#ac3c1022b8a8d5034511fd6ffcb76625d',1,'mcuxClEls_InterruptOptionSet_t::word()'],['../a01093.html#a57cd499ae60ad1bb19fc54517d9ff580',1,'mcuxClEls_HwConfig_t::word()'],['../a01117.html#a6f703afe07655c05795fd6061b321dc3',1,'mcuxClEls_EccSignOption_t::word()'],['../a01129.html#a1d1416b8e584c34840183572e7b2df3d',1,'mcuxClEls_EccVerifyOption_t::word()'],['../a01141.html#ab5dac27ccbb4062c42c971d44e504519',1,'mcuxClEls_EccKeyGenOption_t::word()'],['../a01153.html#a17969e2f10fec362e68869232cb1099b',1,'mcuxClEls_EccKeyExchOption_t::word()'],['../a01165.html#a4addaf59a3d2ab2743fd4c622c0e97ac',1,'mcuxClEls_HashOption_t::word()'],['../a01177.html#a5f797c75232df146cecc9c76dd04d463',1,'mcuxClEls_HmacOption_t::word()'],['../a01225.html#a9a03426cf6b706ee292473b3d695ebe0',1,'mcuxClEls_KeyImportOption_t::word()'],['../a01237.html#a270029567d10cf5d46c68f3fd5762394',1,'mcuxClEls_KeyProp_t::word()']]], + ['wrpok',['wrpok',['../a01237.html#a8b01f95eb9069953fe7a48b6ec85e479',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_2.html b/components/els_pkc/doc/mcxn/html/search/variables_2.html new file mode 100644 index 000000000..0cb98d305 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_2.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_2.js b/components/els_pkc/doc/mcxn/html/search/variables_2.js new file mode 100644 index 000000000..d0cc42777 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_2.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['bits',['bits',['../a00997.html#a2d11453f5716e58c8b34e92d434edd1b',1,'mcuxClEls_AeadOption_t::bits()'],['../a01009.html#af61168dc7998ed7862a56c85b64871c0',1,'mcuxClEls_CipherOption_t::bits()'],['../a01021.html#a6cb17fd040a2db25cdaafe3e042b0831',1,'mcuxClEls_CmacOption_t::bits()'],['../a01033.html#a107c920f079a09f0078dd0791faa2110',1,'mcuxClEls_HwVersion_t::bits()'],['../a01045.html#a3a7dbe3fd3f4e92c059cb39a04ac863e',1,'mcuxClEls_HwState_t::bits()'],['../a01057.html#ad3bc5d3ed1f3a1e38687c1742d3cf8f3',1,'mcuxClEls_InterruptOptionEn_t::bits()'],['../a01069.html#a38fff411deb5bfd137a206a35305d3e9',1,'mcuxClEls_InterruptOptionRst_t::bits()'],['../a01081.html#ac8b9b47932507184288a99d01ee45b39',1,'mcuxClEls_InterruptOptionSet_t::bits()'],['../a01093.html#a95b4684aa6203efcdf26303743fdfcd5',1,'mcuxClEls_HwConfig_t::bits()'],['../a01105.html#ac18d751428d40b3e3127a0779abc1cec',1,'mcuxClEls_CommandCrcConfig_t::bits()'],['../a01117.html#accf6312c26ce770b5647c4e45b00f7b5',1,'mcuxClEls_EccSignOption_t::bits()'],['../a01129.html#aa5f2cce580390956b07603eb64fe6fc7',1,'mcuxClEls_EccVerifyOption_t::bits()'],['../a01141.html#afc19db0547800dd35ed3d3294831344b',1,'mcuxClEls_EccKeyGenOption_t::bits()'],['../a01153.html#aa620a69ff6945f317f2df59bdf4284cd',1,'mcuxClEls_EccKeyExchOption_t::bits()'],['../a01165.html#aacda3c97994f6b172c7fd69c89d275dc',1,'mcuxClEls_HashOption_t::bits()'],['../a01177.html#ae06ed09126b22cf0131a97bff34cc166',1,'mcuxClEls_HmacOption_t::bits()'],['../a01225.html#ad0fc563d3f708b06c986ec2ae604d69e',1,'mcuxClEls_KeyImportOption_t::bits()'],['../a01237.html#abcae2eaaf0826e5548f0b416ecfff0b4',1,'mcuxClEls_KeyProp_t::bits()']]], + ['buffer',['buffer',['../a01277.html#acd3913d2b4adf01d7d95c687c578c752',1,'mcuxClSession_WorkArea']]], + ['busy',['busy',['../a01045.html#a453ae753658b4809ea3141fffd5641c8',1,'mcuxClEls_HwState_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_3.html b/components/els_pkc/doc/mcxn/html/search/variables_3.html new file mode 100644 index 000000000..1e83bf5a9 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_3.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_3.js b/components/els_pkc/doc/mcxn/html/search/variables_3.js new file mode 100644 index 000000000..2ad54564f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_3.js @@ -0,0 +1,15 @@ +var searchData= +[ + ['cfg',['cfg',['../a01261.html#a5d5778eef90af40b0ba73b22fdeedb57',1,'mcuxClPkc_State_t']]], + ['ciphersup',['ciphersup',['../a01093.html#ac0db95aaf62ac50581111452e89de3ba',1,'mcuxClEls_HwConfig_t']]], + ['ckdf_5falgo',['ckdf_algo',['../a01189.html#afc52662f6e41b83e0c731d77c616506c',1,'mcuxClEls_CkdfOption_t']]], + ['ckdfsup',['ckdfsup',['../a01093.html#a05b73ed0395351b9504c35f54ac50495',1,'mcuxClEls_HwConfig_t']]], + ['cmacsup',['cmacsup',['../a01093.html#ad30966f27a451f027aed32c036289515',1,'mcuxClEls_HwConfig_t']]], + ['cphmde',['cphmde',['../a01009.html#a2e1e4a5d815c2559f0ef02e4fd0e5523',1,'mcuxClEls_CipherOption_t']]], + ['cphsie',['cphsie',['../a01009.html#af8735651384f21746fcea24b5c935a1d',1,'mcuxClEls_CipherOption_t']]], + ['cphsoe',['cphsoe',['../a01009.html#aa37b413e9a8ffa66655bc529aadaadbc',1,'mcuxClEls_CipherOption_t']]], + ['cpuwa',['cpuWa',['../a01285.html#a8e3448a94cee26e27929d48656dcacb8',1,'mcuxClSession_Descriptor']]], + ['ctrl',['ctrl',['../a01261.html#a3b225011dfe5fd36551cb70210f9b41c',1,'mcuxClPkc_State_t']]], + ['ctx',['ctx',['../a01265.html#a2869dc5912686dc81c5076587bb83327',1,'mcuxClRandom_Config']]], + ['curveparam',['curveParam',['../a00977.html#a0396802978ddd78f753922c8dadadb18',1,'mcuxClEcc_KeyGen_Param_t::curveParam()'],['../a00981.html#a9af6c185c258baa0a6a4b0080b35b1aa',1,'mcuxClEcc_Sign_Param_t::curveParam()'],['../a00985.html#a58660c912b751cbea8360e214c482b42',1,'mcuxClEcc_Verify_Param_t::curveParam()'],['../a00989.html#a264c295859d39a968b32efbc4f03942a',1,'mcuxClEcc_PointMult_Param_t::curveParam()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_4.html b/components/els_pkc/doc/mcxn/html/search/variables_4.html new file mode 100644 index 000000000..39883bd60 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_4.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_4.js b/components/els_pkc/doc/mcxn/html/search/variables_4.js new file mode 100644 index 000000000..ace8deb5f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_4.js @@ -0,0 +1,16 @@ +var searchData= +[ + ['dcrpt',['dcrpt',['../a00997.html#aabfd8fc5389ae7bfa2dea92c42441555',1,'mcuxClEls_AeadOption_t::dcrpt()'],['../a01009.html#ada47dbd9ac0d8ed1b171e4742ed5d73a',1,'mcuxClEls_CipherOption_t::dcrpt()']]], + ['der_5fcertificate',['der_certificate',['../a00032.html#a9aaa67299df29bf9b32ac94aa91dde50',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5fimport',['der_certificate_import',['../a00032.html#adf7528a77c2e6b48821cbed7c0337096',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5flen_5fwithout_5fsignature',['der_certificate_len_without_signature',['../a00032.html#a7edd27bd2edabd9a7a5c790b8605cd9a',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['der_5fcertificate_5foffset_5fpbk',['der_certificate_offset_pbk',['../a00032.html#af049ea7eafe6bdbb70ce3dd48adca426',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['dirty',['dirty',['../a01277.html#a500aa3a1084704dbd9622a247458b9b1',1,'mcuxClSession_WorkArea']]], + ['drbgentlvl',['drbgentlvl',['../a01045.html#a87b6c5ce545619bb478efcc020f862ff',1,'mcuxClEls_HwState_t']]], + ['drbgreqsup',['drbgreqsup',['../a01093.html#a1519b8980b5d2615c96ac1c788014e6d',1,'mcuxClEls_HwConfig_t']]], + ['drbgtestsup',['drbgtestsup',['../a01093.html#ae70916d8e053e37a7de79db3c873cdd5',1,'mcuxClEls_HwConfig_t']]], + ['dtrgncfgloadsup',['dtrgncfgloadsup',['../a01093.html#a1655b1afaf9b84514817f11e71f21232',1,'mcuxClEls_HwConfig_t']]], + ['dtrng_5fbusy',['dtrng_busy',['../a01045.html#a05b012990a92e9deaada4a5d87ac380a',1,'mcuxClEls_HwState_t']]], + ['dtrngevalsup',['dtrngevalsup',['../a01093.html#a7ab5fc2fd5378fbf9044f6eb47b74602',1,'mcuxClEls_HwConfig_t']]], + ['duk',['duk',['../a01237.html#ab8a152b213978003ebb149be0c0ae5a7',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_5.html b/components/els_pkc/doc/mcxn/html/search/variables_5.html new file mode 100644 index 000000000..f25879c02 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_5.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_5.js b/components/els_pkc/doc/mcxn/html/search/variables_5.js new file mode 100644 index 000000000..b4946b661 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_5.js @@ -0,0 +1,19 @@ +var searchData= +[ + ['ecc_5fdigest',['ecc_digest',['../a00008.html#ae951d0a54ca7834571b2870fdee3ee9c',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fpublic_5fkey',['ecc_public_key',['../a00008.html#ae2a6bb3aae38a75b559936cb2a304daa',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fpublic_5fkey_5fclient',['ecc_public_key_client',['../a00029.html#a0f8366d89d3959a37ba157fad828c3f5',1,'mcuxClEls_Tls_Master_Key_Session_Keys_example.c']]], + ['ecc_5froot_5fpublic_5fkey',['ecc_root_public_key',['../a00032.html#a961fa94f9b6e3852e50ad9417f7a6601',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['ecc_5fsignature',['ecc_signature',['../a00008.html#a0c919da2c9c7078b5c7243da9fa76322',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fsignature_5fand_5fpublic_5fkey',['ecc_signature_and_public_key',['../a00008.html#a94d4ee9f78d77b0c9e977400ad498190',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecc_5fsignature_5fr',['ecc_signature_r',['../a00008.html#a9723d2c5493f5403895e91d633105402',1,'mcuxClEls_Ecc_Keygen_Sign_Verify_example.c']]], + ['ecdsavfy',['ecdsavfy',['../a01045.html#a41492f22ac15d4cc4feebd517faa75ba',1,'mcuxClEls_HwState_t']]], + ['echashchl',['echashchl',['../a01117.html#ab825e88899ff7627304d25fbcc1adffd',1,'mcuxClEls_EccSignOption_t::echashchl()'],['../a01129.html#a2642a5936ec9f5c7394704161c984598',1,'mcuxClEls_EccVerifyOption_t::echashchl()']]], + ['eckxchsup',['eckxchsup',['../a01093.html#ac9e323809993203e0867e37641f7d9e0',1,'mcuxClEls_HwConfig_t']]], + ['ecsignsup',['ecsignsup',['../a01093.html#ab5a3a301e2fa7ed724b1a10db46a4dc1',1,'mcuxClEls_HwConfig_t']]], + ['ecvfysup',['ecvfysup',['../a01093.html#a082dbc1af5f81f7d76e32c01e35a6c81',1,'mcuxClEls_HwConfig_t']]], + ['elsint',['elsint',['../a01057.html#a1ceef382dbc3fbafdff1d553658c7ea9',1,'mcuxClEls_InterruptOptionEn_t::elsint()'],['../a01069.html#a8123125e41c363c03e6a671e94543d3d',1,'mcuxClEls_InterruptOptionRst_t::elsint()'],['../a01081.html#a694dd46e51d111832674fdd7827ba7a2',1,'mcuxClEls_InterruptOptionSet_t::elsint()']]], + ['enable',['enable',['../a01105.html#a60c0c05eb7acf852589b6f5b7a7c9dd3',1,'mcuxClEls_CommandCrcConfig_t']]], + ['err',['err',['../a01045.html#a5513d9d58397ac4701044421f2c8fd28',1,'mcuxClEls_HwState_t']]], + ['extkey',['extkey',['../a00997.html#a6e8a89cd7914a8f587ae7d2888a1e7cd',1,'mcuxClEls_AeadOption_t::extkey()'],['../a01009.html#a833ce63bdab590215c35b82767479eee',1,'mcuxClEls_CipherOption_t::extkey()'],['../a01021.html#a1d6db09e93aaf0c0d428e719dbff29fe',1,'mcuxClEls_CmacOption_t::extkey()'],['../a01153.html#ab28493ba971ceb64a4fa0f741e98358d',1,'mcuxClEls_EccKeyExchOption_t::extkey()'],['../a01177.html#a4e16fabb042914665cabe00f5d6a6795',1,'mcuxClEls_HmacOption_t::extkey()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_6.html b/components/els_pkc/doc/mcxn/html/search/variables_6.html new file mode 100644 index 000000000..0fcd6c2f8 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_6.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_6.js b/components/els_pkc/doc/mcxn/html/search/variables_6.js new file mode 100644 index 000000000..3d1bbef0d --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_6.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['fgp',['fgp',['../a01237.html#af8743c57bd6d9dd9f329b5cafa3f5c0c',1,'mcuxClEls_KeyProp_t']]], + ['fhwo',['fhwo',['../a01237.html#a0c56a02caf693cda953b333b89a51389',1,'mcuxClEls_KeyProp_t']]], + ['finalize',['finalize',['../a01021.html#aabd3ce3a952bdd2279b7f4d0a2e22da8',1,'mcuxClEls_CmacOption_t']]], + ['frtn',['frtn',['../a01237.html#a6e2122f7d4c2706f56ec7fba67042206',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_7.html b/components/els_pkc/doc/mcxn/html/search/variables_7.html new file mode 100644 index 000000000..ad2fa37a5 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_7.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_7.js b/components/els_pkc/doc/mcxn/html/search/variables_7.js new file mode 100644 index 000000000..f08f762c3 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_7.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['gdetcfgloadsup',['gdetcfgloadsup',['../a01093.html#a83e2de492b29950e62bdc159629a7e87',1,'mcuxClEls_HwConfig_t']]], + ['gdettrimsup',['gdettrimsup',['../a01093.html#a546385b574e49302ba2e748303fa91a4',1,'mcuxClEls_HwConfig_t']]], + ['gmcuxcloscca_5fscratchpad',['gmcuxClOscca_ScratchPad',['../a00482.html#ac37c24690a87ce8d10e039d46b426a2c',1,'mcuxClOscca_PlatformTypes.h']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_8.html b/components/els_pkc/doc/mcxn/html/search/variables_8.html new file mode 100644 index 000000000..23887d77b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_8.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_8.js b/components/els_pkc/doc/mcxn/html/search/variables_8.js new file mode 100644 index 000000000..22e3f6c28 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_8.js @@ -0,0 +1,11 @@ +var searchData= +[ + ['hashini',['hashini',['../a01165.html#ac9b592abc979189fad34fde3ec0c163c',1,'mcuxClEls_HashOption_t']]], + ['hashld',['hashld',['../a01165.html#a4a982ed0c424187a716adba9c0c99996',1,'mcuxClEls_HashOption_t']]], + ['hashmd',['hashmd',['../a01165.html#a91c25618e98d1a9db1b1b13cfe52495f',1,'mcuxClEls_HashOption_t']]], + ['hashoe',['hashoe',['../a01165.html#a2a87b3f8cde5a5cfdbea784ca4c6a58a',1,'mcuxClEls_HashOption_t']]], + ['hashsup',['hashsup',['../a01093.html#ac5fc6ff1883c09e1ed72412f53514b13',1,'mcuxClEls_HwConfig_t']]], + ['hkdf_5falgo',['hkdf_algo',['../a01201.html#ab385e81dfad37e2cdd8faaa1521ac405',1,'mcuxClEls_HkdfOption_t']]], + ['hkdfsup',['hkdfsup',['../a01093.html#af443a864be5d2d0ab3c6a2f007fe9afe',1,'mcuxClEls_HwConfig_t']]], + ['hmacsup',['hmacsup',['../a01093.html#a4cf06c58477f35949dc0089a3a3184ce',1,'mcuxClEls_HwConfig_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_9.html b/components/els_pkc/doc/mcxn/html/search/variables_9.html new file mode 100644 index 000000000..f44664990 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_9.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_9.js b/components/els_pkc/doc/mcxn/html/search/variables_9.js new file mode 100644 index 000000000..a7208fcdc --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_9.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['initialize',['initialize',['../a01021.html#a90660bb1c9ee7d9f1d53209ab53dba4b',1,'mcuxClEls_CmacOption_t']]], + ['irq',['irq',['../a01045.html#afaa797f8db7f6252bf4ae54eb875c7fd',1,'mcuxClEls_HwState_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_a.html b/components/els_pkc/doc/mcxn/html/search/variables_a.html new file mode 100644 index 000000000..59633b357 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_a.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_a.js b/components/els_pkc/doc/mcxn/html/search/variables_a.js new file mode 100644 index 000000000..73e509b5a --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_a.js @@ -0,0 +1,19 @@ +var searchData= +[ + ['kactv',['kactv',['../a01237.html#ad0617bc9eea63043b1faf5fe9814ba97',1,'mcuxClEls_KeyProp_t']]], + ['kbase',['kbase',['../a01237.html#ac8a7a5dac0515241438c5086d60ffcd2',1,'mcuxClEls_KeyProp_t']]], + ['kdeletesup',['kdeletesup',['../a01093.html#aff9488c467cfca4942ba41b51c4225b7',1,'mcuxClEls_HwConfig_t']]], + ['key_5frfc3394',['key_rfc3394',['../a00032.html#adfc408cbf330d6e41a58a910f6a287d0',1,'mcuxClEls_Key_Import_Puk_DER_example.c']]], + ['keyentrylength',['keyEntryLength',['../a01269.html#a441763378fea50af88f8cdf75648a0e6',1,'mcuxClRsa_KeyEntry_t']]], + ['keygensup',['keygensup',['../a01093.html#add6853a64d3322d8400c601277d42afb',1,'mcuxClEls_HwConfig_t']]], + ['keyinsup',['keyinsup',['../a01093.html#a10e2de8c251bc00183a2d578fb778661',1,'mcuxClEls_HwConfig_t']]], + ['keyoutsup',['keyoutsup',['../a01093.html#a6bbf59e55899238b17d7a1266d6a063a',1,'mcuxClEls_HwConfig_t']]], + ['keyprovsup',['keyprovsup',['../a01093.html#a55ac97e5d1105cd9f5ac217d05a8e0c2',1,'mcuxClEls_HwConfig_t']]], + ['keytype',['keytype',['../a01273.html#a8d0791ef8960a4316931f55f5848c3fa',1,'mcuxClRsa_Key']]], + ['kfmt',['kfmt',['../a01225.html#ae3892b035704c00a855dd43d96a21b2c',1,'mcuxClEls_KeyImportOption_t']]], + ['kgsign',['kgsign',['../a01141.html#aa20a2dd1242cfa9c945d09332db760e1',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgsign_5frnd',['kgsign_rnd',['../a01141.html#ab2d02455b74fc4f2999c8b579bd87c8d',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgsrc',['kgsrc',['../a01141.html#aa60e98c0d7570daa80ab5536ebf71d94',1,'mcuxClEls_EccKeyGenOption_t']]], + ['kgtypedh',['kgtypedh',['../a01141.html#ade3f3190f07c3a1b8a5948988d3b85d5',1,'mcuxClEls_EccKeyGenOption_t']]], + ['ksize',['ksize',['../a01237.html#a49806c0136f41b701675799cb69d34d5',1,'mcuxClEls_KeyProp_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_b.html b/components/els_pkc/doc/mcxn/html/search/variables_b.html new file mode 100644 index 000000000..17216090f --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_b.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_b.js b/components/els_pkc/doc/mcxn/html/search/variables_b.js new file mode 100644 index 000000000..3cb6f3b50 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_b.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['lastinit',['lastinit',['../a00997.html#a70ab6c857c7ae2e10b2f0580e4ea3669',1,'mcuxClEls_AeadOption_t']]], + ['level',['level',['../a01033.html#a362c318252fad3db6e55fde7dac2572f',1,'mcuxClEls_HwVersion_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_c.html b/components/els_pkc/doc/mcxn/html/search/variables_c.html new file mode 100644 index 000000000..78e211ac1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_c.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_c.js b/components/els_pkc/doc/mcxn/html/search/variables_c.js new file mode 100644 index 000000000..d71724dd1 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_c.js @@ -0,0 +1,208 @@ +var searchData= +[ + ['major',['major',['../a01033.html#a0c4765f9784a475579e0fd433a753011',1,'mcuxClEls_HwVersion_t']]], + ['mcuxclaead_5fmode_5faes_5fccm_5fdec',['mcuxClAead_Mode_AES_CCM_DEC',['../a00221.html#a2200749ce58283a93c563c8ca588b266',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fccm_5fenc',['mcuxClAead_Mode_AES_CCM_ENC',['../a00221.html#a2bcc801c8d408f932f10ef5834bd4dca',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fgcm_5fdec',['mcuxClAead_Mode_AES_GCM_DEC',['../a00221.html#afec8f3f6510075056a56f46fcec29f0d',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmode_5faes_5fgcm_5fenc',['mcuxClAead_Mode_AES_GCM_ENC',['../a00221.html#ac6b194ee963fcd02a46c187436486f3a',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fccm_5fdec',['mcuxClAead_ModeDescriptor_AES_CCM_DEC',['../a00221.html#a6a1aa3e495a39a8c6d8e399e2195daf2',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fccm_5fenc',['mcuxClAead_ModeDescriptor_AES_CCM_ENC',['../a00221.html#ac05fdd0d08e4c25390079671875363f3',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fgcm_5fdec',['mcuxClAead_ModeDescriptor_AES_GCM_DEC',['../a00221.html#ac167912520d7408603f0b4115ea59150',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclaead_5fmodedescriptor_5faes_5fgcm_5fenc',['mcuxClAead_ModeDescriptor_AES_GCM_ENC',['../a00221.html#a8874663e21c7e81e855ebcceacdd300a',1,'mcuxClAeadModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fdec_5fnopadding',['mcuxClCipher_Mode_AES_CBC_Dec_NoPadding',['../a00677.html#gafcea66751b4008e0b5c9f3d3b982a3a4',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fnopadding',['mcuxClCipher_Mode_AES_CBC_Enc_NoPadding',['../a00677.html#ga807a672d6329f9c7d3beaabca651d517',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga20b89472f917ef5dcd1493e349a2851c',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga3656eebb0f185f9bec04f0cb293c42db',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fcbc_5fenc_5fpkcs7',['mcuxClCipher_Mode_AES_CBC_Enc_PKCS7',['../a00677.html#gad8399b835f6d454f0fa15b2b0ca41ee4',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fctr',['mcuxClCipher_Mode_AES_CTR',['../a00677.html#ga6f1b191b97196025c65851958eb2a700',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fdec_5fnopadding',['mcuxClCipher_Mode_AES_ECB_Dec_NoPadding',['../a00677.html#gade75d09ba133c93d3e46eb1c795bb451',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fnopadding',['mcuxClCipher_Mode_AES_ECB_Enc_NoPadding',['../a00677.html#gac5863201c397e8418c5284523119ea41',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga5c3dcb833ab559f75065e0e340b02886',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2',['../a00677.html#gae741b5b27af200b377425049545f6779',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmode_5faes_5fecb_5fenc_5fpaddingpkcs7',['mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7',['../a00677.html#ga76508d5bd12946fbb9b52749dac9f528',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fdec',['mcuxClCipher_ModeDescriptor_AES_CBC_Dec',['../a00677.html#ga4c8f02ead08c8c20259cf0c0120c8420',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fnopadding',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding',['../a00677.html#ga2cf616ea2d030fbe13a8b1ce8a3a6fa8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1',['../a00677.html#ga22e8dfabe8c99f091cd41beeade83b2c',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga270643be668dfd110388711cae932bd6',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fcbc_5fenc_5fpaddingpkcs7',['mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7',['../a00677.html#gab68a0cefd449150330bc4882ca957396',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fctr',['mcuxClCipher_ModeDescriptor_AES_CTR',['../a00677.html#ga93287cc9cd970f5c9103f1cc597027e0',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fdec',['mcuxClCipher_ModeDescriptor_AES_ECB_Dec',['../a00677.html#ga4a86accbf3ed6f707bca9208464b0fe8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fnopadding',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding',['../a00677.html#ga6d4a742e7880955c34b446d8d7ac4b18',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod1',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1',['../a00677.html#gae27dec2288073dac847fa49e1f3e9dd8',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingiso9797_5f1_5fmethod2',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2',['../a00677.html#ga887163d5d571468467116cf2017f00a9',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclcipher_5fmodedescriptor_5faes_5fecb_5fenc_5fpaddingpkcs7',['mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7',['../a00677.html#gad0e87e50be9066b625215cda60152589',1,'mcuxClCipherModes_Modes.h']]], + ['mcuxclecc_5feddsa_5fed25519protocoldescriptor',['mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor',['../a00687.html#ga41770640b3d964f8add4ad005c6d81e6',1,'mcuxClEcc_Types.h']]], + ['mcuxclhash_5falgorithm_5fsha224',['mcuxClHash_Algorithm_Sha224',['../a00774.html#ga4de6a5917dc46d3aae22f93df66fc228',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha256',['mcuxClHash_Algorithm_Sha256',['../a00774.html#ga672407195f718d55fcee73d1dfb7c623',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha384',['mcuxClHash_Algorithm_Sha384',['../a00774.html#gaa7389b8db9ec5c97b44db899e2b9f8db',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithm_5fsha512',['mcuxClHash_Algorithm_Sha512',['../a00774.html#gae0687309bef869b41302594c6c934d9a',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha224',['mcuxClHash_AlgorithmDescriptor_Sha224',['../a00774.html#ga56d71cf5a53a9e64a648c4d9776efa8e',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha256',['mcuxClHash_AlgorithmDescriptor_Sha256',['../a00774.html#ga0332b3c0540cd1761dfaa17b33f02f02',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha384',['mcuxClHash_AlgorithmDescriptor_Sha384',['../a00774.html#ga18de1261f5761dfc43ef89a102fda259',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhash_5falgorithmdescriptor_5fsha512',['mcuxClHash_AlgorithmDescriptor_Sha512',['../a00774.html#ga50a5ce5101cf1175127bdf1ea7bfb0e1',1,'mcuxClHashModes_Algorithms.h']]], + ['mcuxclhmac_5fmodedescriptor_5fsha2_5f256_5fels',['mcuxClHmac_ModeDescriptor_SHA2_256_ELS',['../a00398.html#a06144963f16c396f82dcab7f0a3bb0db',1,'mcuxClHmac_Modes.h']]], + ['mcuxclkey_5fprotection_5fckdf',['mcuxClKey_Protection_Ckdf',['../a00792.html#ga46912713307ab64e4f20075064224838',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotection_5fnone',['mcuxClKey_Protection_None',['../a00792.html#gabf61ad39ecaba937f41b73721ce80b6a',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotectiondescriptor_5fckdf',['mcuxClKey_ProtectionDescriptor_Ckdf',['../a00792.html#ga11724513bd08cb490212fa5d70c7c5b0',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5fprotectiondescriptor_5fnone',['mcuxClKey_ProtectionDescriptor_None',['../a00792.html#gaa4fc9e15d78b127eaab9ec4c273d64b1',1,'mcuxClKey_ProtectionMechanisms.h']]], + ['mcuxclkey_5ftype_5faes128',['mcuxClKey_Type_Aes128',['../a00670.html#ga8f0a74b8ec63f9bcfff2723f37602d0d',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5faes192',['mcuxClKey_Type_Aes192',['../a00670.html#gaaeae50366310367805cb6ae6d81d88b1',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5faes256',['mcuxClKey_Type_Aes256',['../a00670.html#ga1249b014f089397821eceab3fd04ed5c',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftype_5fecc_5fmontdh_5fcurve25519_5fkeypair',['mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair',['../a00682.html#gadcf4ca8f2a1626610da5b9bea5be3d89',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fecc_5fmontdh_5fcurve448_5fkeypair',['mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair',['../a00682.html#gae9116a45b5bfb237470625ae7d0fb29b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed25519_5fpriv',['mcuxClKey_Type_EdDSA_Ed25519_Priv',['../a00682.html#ga4f21b03709a5cac0b713f4e930102af8',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed25519_5fpub',['mcuxClKey_Type_EdDSA_Ed25519_Pub',['../a00682.html#gab1d91d013e28a086fd4e13175252c049',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed448_5fpriv',['mcuxClKey_Type_EdDSA_Ed448_Priv',['../a00682.html#ga5deb01671f213897a9d54c0e5b5b2ebe',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5feddsa_5fed448_5fpub',['mcuxClKey_Type_EdDSA_Ed448_Pub',['../a00682.html#gab35aa6e48e5bd8eda0a1b27c897f81a2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fhmac_5fvariablelength',['mcuxClKey_Type_Hmac_variableLength',['../a00781.html#ga42eb018ca876c87b3d4539532ab2154d',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftype_5fhmacsha256',['mcuxClKey_Type_HmacSha256',['../a00781.html#ga6d1ebb714b890c9b193a68edb3038720',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv',['../a00682.html#gadee38fd7f3c37112e45316828a1b421d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub',['../a00682.html#ga953ce0f67b3ba06382f7ca22eec53b3e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv',['../a00682.html#ga84b46e442f069d514c5061a03c4e9190',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp160t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub',['../a00682.html#ga8f69f4a645709620e99b354c8d28c57a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv',['../a00682.html#ga58315a40eb971b7d1ae90d906eb30319',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub',['../a00682.html#ga6f2fdb757ee68215625ffb9d32bab892',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv',['../a00682.html#ga9c3d2aedc7cdee77f194a281a79d1b38',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp192t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub',['../a00682.html#gaee8f56b3741cb2d385321184ecc3112a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv',['../a00682.html#ga67db10ea32d18c91b828214d9d38ac8b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub',['../a00682.html#ga78e896c33933303cacce198571f1d525',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv',['../a00682.html#ga6965a5067cf306af93fa18b0d7c40bf5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp224t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub',['../a00682.html#gaa70ef1ac082befbd2bcb06a1990cf8ca',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv',['../a00682.html#ga9de0651cd7e19b5a7d5b3e782a8cdb78',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub',['../a00682.html#ga37b4c94b2e841b2f3eb2331083b76f5f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv',['../a00682.html#ga5d0109f06ed0017ab64a625c290f84a0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp256t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub',['../a00682.html#ga5d9afd44cd025fbb0b3fc05c0b207597',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv',['../a00682.html#ga073b9c815509c8321bdeb396d8f377d5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub',['../a00682.html#ga91e507098e21780ba47f892d18197b26',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv',['../a00682.html#ga9fd102f8a9a37098e7fbaccd56ccb66c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp320t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub',['../a00682.html#ga660a4eedac67861ac691f8e6cce31a2e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv',['../a00682.html#ga8a996e206f32bd964d23537c41f27b25',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub',['../a00682.html#gade346aa31f4479a953d693d24be3005c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv',['../a00682.html#gaa83b67499981c694cc35d63173b908e5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp384t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub',['../a00682.html#ga9efe52ae3219c7c1401dcd2be13b5bd0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512r1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv',['../a00682.html#ga0973ccb9a10dba4e034096093ea24b22',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512r1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub',['../a00682.html#ga90516c497fc468872c20797ea042d7d6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512t1_5fpriv',['mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv',['../a00682.html#ga6c0ef669e99f161073f329a5e08c7d10',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fbrainpoolp512t1_5fpub',['mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub',['../a00682.html#ga1346153805fc80794dcd54135e18ded9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp192_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P192_Priv',['../a00682.html#gab3bd456d3e79c18bb52852012a785a7c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp192_5fpub',['mcuxClKey_Type_WeierECC_NIST_P192_Pub',['../a00682.html#ga06b92e495eab87142fc07c469fac5526',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp224_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P224_Priv',['../a00682.html#ga8449862f98fdfc750c8990a06e561bc7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp224_5fpub',['mcuxClKey_Type_WeierECC_NIST_P224_Pub',['../a00682.html#ga0a61957ec8619856fe03204d56bd7a14',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp256_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P256_Priv',['../a00682.html#gacc7e8ff2ac5a8a3d894d7a9da0a80341',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp256_5fpub',['mcuxClKey_Type_WeierECC_NIST_P256_Pub',['../a00682.html#ga7f344daa7b996e30a163c9053f05ac5f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp384_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P384_Priv',['../a00682.html#ga690fd09dedd835e6d9e99e6de82f3ba0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp384_5fpub',['mcuxClKey_Type_WeierECC_NIST_P384_Pub',['../a00682.html#ga2ee917bf64caddab241b566099acf669',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp521_5fpriv',['mcuxClKey_Type_WeierECC_NIST_P521_Priv',['../a00682.html#ga0b3881b7f5ef6077eaca0d37395a320e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fnist_5fp521_5fpub',['mcuxClKey_Type_WeierECC_NIST_P521_Pub',['../a00682.html#ga4fa543596682506a51f4078409dc3731',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp160k1_5fpriv',['mcuxClKey_Type_WeierECC_secp160k1_Priv',['../a00682.html#ga919b93483d11e303265fc8db41c4c03f',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp160k1_5fpub',['mcuxClKey_Type_WeierECC_secp160k1_Pub',['../a00682.html#ga4345462d03a5a61641bfbbd3a2d5b86e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192k1_5fpriv',['mcuxClKey_Type_WeierECC_secp192k1_Priv',['../a00682.html#ga1bbeb45dc0f37b64ddf7d54890d1d5da',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192k1_5fpub',['mcuxClKey_Type_WeierECC_secp192k1_Pub',['../a00682.html#gaade00cdba0ae71d0ead7474186e8b9fa',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192r1_5fpriv',['mcuxClKey_Type_WeierECC_secp192r1_Priv',['../a00682.html#ga000d450d23f8c6980674668531ad4727',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp192r1_5fpub',['mcuxClKey_Type_WeierECC_secp192r1_Pub',['../a00682.html#gaf003efa3e8861d0651ce6616abf5d919',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224k1_5fpriv',['mcuxClKey_Type_WeierECC_secp224k1_Priv',['../a00682.html#ga8754b1ec3ded884876adbb0145d1e054',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224k1_5fpub',['mcuxClKey_Type_WeierECC_secp224k1_Pub',['../a00682.html#ga75e6fbe876aa640a0fade7940ed23c3b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224r1_5fpriv',['mcuxClKey_Type_WeierECC_secp224r1_Priv',['../a00682.html#gabaef750bcfea399f7cf7e397d1b637e6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp224r1_5fpub',['mcuxClKey_Type_WeierECC_secp224r1_Pub',['../a00682.html#ga3b602493fe22f22f91da3f6159ebe79c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256k1_5fpriv',['mcuxClKey_Type_WeierECC_secp256k1_Priv',['../a00682.html#ga9e922253404f7608e004929b2e994d7d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256k1_5fpub',['mcuxClKey_Type_WeierECC_secp256k1_Pub',['../a00682.html#ga41cecc27d7f37dfc1bca1158fa42af05',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256r1_5fpriv',['mcuxClKey_Type_WeierECC_secp256r1_Priv',['../a00682.html#gac945c22c4932453b64a0369e168aa05a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp256r1_5fpub',['mcuxClKey_Type_WeierECC_secp256r1_Pub',['../a00682.html#gafc846d07facc686d0d6fcf7a46e7eb67',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp384r1_5fpriv',['mcuxClKey_Type_WeierECC_secp384r1_Priv',['../a00682.html#ga4456ec80ccaa45cf7a715719acb9195d',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp384r1_5fpub',['mcuxClKey_Type_WeierECC_secp384r1_Pub',['../a00682.html#ga5e8db8f1f69ba0886f3a568e3eef3777',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp521r1_5fpriv',['mcuxClKey_Type_WeierECC_secp521r1_Priv',['../a00682.html#ga8898847c8409dd00985474ce2bfd9e7b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftype_5fweierecc_5fsecp521r1_5fpub',['mcuxClKey_Type_WeierECC_secp521r1_Pub',['../a00682.html#ga4922658a5dbdafb18e9a26aa62d047d9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5faes128',['mcuxClKey_TypeDescriptor_Aes128',['../a00670.html#ga8f7fce2b87e12c68354d223b9a75dc37',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5faes192',['mcuxClKey_TypeDescriptor_Aes192',['../a00670.html#ga16e79ab35a7a7da20948688481fe15ad',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5faes256',['mcuxClKey_TypeDescriptor_Aes256',['../a00670.html#ga5a8d0b88ec6b1da1730d861ca6fb7f97',1,'mcuxClAes_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5fecc_5fmontdh_5fcurve25519_5fkeypair',['mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair',['../a00682.html#gadfd782e0581049bb1fe40049295807f6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fecc_5fmontdh_5fcurve448_5fkeypair',['mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair',['../a00682.html#ga033a43f0faf219f0e18ced032e1ad694',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed25519_5fpriv',['mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv',['../a00682.html#gab98021bcb61d1707d87106ddae87439c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed25519_5fpub',['mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub',['../a00682.html#ga3adea0c5fb26beb91e9d5cc798b167fd',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed448_5fpriv',['mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv',['../a00682.html#gab28b18fd50c1ec6bc4a05c56d1663046',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5feddsa_5fed448_5fpub',['mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub',['../a00682.html#gae06f9c4d573b51d538a42dfd2cbc4699',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fhmac_5fvariablelength',['mcuxClKey_TypeDescriptor_Hmac_variableLength',['../a00781.html#gae7b0c9b1b7b2c69b0d8c9ac6decdcf1f',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5fhmacsha256',['mcuxClKey_TypeDescriptor_HmacSha256',['../a00781.html#gaa7829411660f435c478e54884f9dc235',1,'mcuxClHmac_KeyTypes.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv',['../a00682.html#gafee54bf1b90cab43955656fdf688e6b9',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub',['../a00682.html#ga62389be1de20d8cf7dfdf9416766ce59',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv',['../a00682.html#ga3e834a29c37352e20f69567334a19ecb',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp160t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub',['../a00682.html#gabe551efbcc35efcba391ee767b7f7ff0',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv',['../a00682.html#gaf7713f17a5c6504d79a4cc19a619d1bf',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub',['../a00682.html#ga55895a7c4d7dbde9cb53e27ce4aadc36',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv',['../a00682.html#gaec947c583361285beabd1515b85ffa05',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp192t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub',['../a00682.html#ga5a4502575819fa65e4afad99ce4c1d77',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv',['../a00682.html#ga2eefdf975f757f135792dedcc500c9f5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub',['../a00682.html#ga71ccfd1a0541def6aa05b24db3059b10',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv',['../a00682.html#ga8b497f39e491a6301f7e27edf74a1d94',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp224t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub',['../a00682.html#ga0532b3419b3886694736007f0b8e7944',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv',['../a00682.html#ga1c0248997a1ae57f004b96d063240fc7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub',['../a00682.html#ga81ed0e23c5cb230eaf68b43e2d037dde',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv',['../a00682.html#ga900bbb5cd092246e2bb83336df1af27e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp256t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub',['../a00682.html#ga649b579900b6ff23d3009026fa4a7a3a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv',['../a00682.html#ga3eb4a76b7cd7e5b04b69f1af7d430a24',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub',['../a00682.html#ga3578f443c84fa6e97c7fa21bd5765461',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv',['../a00682.html#ga055bfc9d1fa07fcd80911a4483ee8989',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp320t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub',['../a00682.html#ga45b70649d277b865e410beef5e815198',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv',['../a00682.html#ga4c70e1c0c3dec2ae4b89fd544987724b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub',['../a00682.html#ga72edef6223f86b15d63f282c0a9119bc',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv',['../a00682.html#gab5dc15b01d9c0d9dbf847026af187802',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp384t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub',['../a00682.html#ga7cd3157e70c933ce8f646c6277d832b6',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv',['../a00682.html#gac15a4416fa5fa537f67a456e68b9e81a',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub',['../a00682.html#gace90d3010bf72d3289a1f5ab249c07a2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512t1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv',['../a00682.html#ga980f0af6070d632d144d38c34ca26d0e',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fbrainpoolp512t1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub',['../a00682.html#gaa585fea86a1de6d3eee179053ff71396',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp160k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv',['../a00682.html#ga5be9d578c7e89fb9ddeb24ce1dd87705',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp160k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub',['../a00682.html#ga45f80b52c3713407e5ea8d874fcab224',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv',['../a00682.html#ga4464ec90b697f37d0c77f371ffd25f73',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub',['../a00682.html#gae82b0b8a866aa021d9be12d673ea44cb',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv',['../a00682.html#ga9696729f938dcffb197bb7ec7cf68ab7',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp192r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub',['../a00682.html#gad6f5289ef5ca2a8675ab7086b35522df',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv',['../a00682.html#gaacbea5c086db4ecfa1e481d64e64c034',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub',['../a00682.html#ga72e156ee2a9ac1c0808fb54be1c37854',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv',['../a00682.html#ga9d9727c76f81c36e06c5202eced2d73b',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp224r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub',['../a00682.html#ga243160a6bd14bfcfae0feab8cfec4444',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256k1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv',['../a00682.html#ga39040d5c10a5245ba45acb94304704f5',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256k1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub',['../a00682.html#gafb9d141d04c292a77577c8593f379dae',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv',['../a00682.html#gaddbf6d8826069565a1e79fb24d8cb3b2',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp256r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub',['../a00682.html#ga82bfa972e94322b417a5ddf43932a2ec',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp384r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv',['../a00682.html#gac745b76bab619fff5fe1146fb7d71a50',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp384r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub',['../a00682.html#ga21b1d68989a19b915dd5106075e29cb3',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp521r1_5fpriv',['mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv',['../a00682.html#ga06483f379dc8873d7cc30c300610e327',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclkey_5ftypedescriptor_5fweierecc_5fsecp521r1_5fpub',['mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub',['../a00682.html#ga6269f061cab69e82df4cd7b9656c8a2c',1,'mcuxClEcc_KeyMechanisms.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fnopadding',['mcuxClMac_Mode_CBCMAC_NoPadding',['../a00804.html#ga0edfb9edb1c66eba797754851e463a20',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fpaddingiso9797_5f1_5fmethod1',['mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1',['../a00804.html#ga39e525bf4e237be5933966afa1eafd02',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcbcmac_5fpaddingiso9797_5f1_5fmethod2',['mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2',['../a00804.html#ga6727ecd0ad3c728bb1ba822f7fd6f485',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fcmac',['mcuxClMac_Mode_CMAC',['../a00804.html#gab5f61e17bb7b7d97f69745700f107bc6',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmode_5fhmac_5fsha2_5f256_5fels',['mcuxClMac_Mode_HMAC_SHA2_256_ELS',['../a00398.html#ad6bd4a8254a45bfc3f319c4177fd8d80',1,'mcuxClHmac_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fnopadding',['mcuxClMac_ModeDescriptor_CBCMAC_NoPadding',['../a00804.html#gab8171ca5a2cad3f74f26cade42abb4fa',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fpaddingiso9797_5f1_5fmethod1',['mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1',['../a00804.html#gacf3978d54625d231254d9b42bcbf349c',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcbcmac_5fpaddingiso9797_5f1_5fmethod2',['mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2',['../a00804.html#gaacbabbb60934ae05725b5cb2889c7bce',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclmac_5fmodedescriptor_5fcmac',['mcuxClMac_ModeDescriptor_CMAC',['../a00804.html#ga7df28da412f427562a5ffcb2b3ab8c35',1,'mcuxClMacModes_Modes.h']]], + ['mcuxclrandommodes_5fmdels_5fdrbg',['mcuxClRandomModes_mdELS_Drbg',['../a00833.html#ga33a2ec75a1ffddc069c679de7c34b8fc',1,'mcuxClRandomModes_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fnoencode',['mcuxClRsa_Mode_Sign_NoEncode',['../a00841.html#ga4459d773156bf4ac906a1416dd4ed4f4',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f224',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224',['../a00841.html#gac7cfd526cb16ba49a48ea0881c12e778',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f256',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256',['../a00841.html#ga1845c307f6b2897cf563c1ad97523840',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f384',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384',['../a00841.html#ga2e630f5e6e06e0b5adc2d5f63268b77f',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpkcs1v15_5fsha2_5f512',['mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512',['../a00841.html#ga61cdf384d5eb7774a35bec2dd28b67c8',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f224',['mcuxClRsa_Mode_Sign_Pss_Sha2_224',['../a00841.html#ga6544c3cc75077dde34304c5c45999edf',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f256',['mcuxClRsa_Mode_Sign_Pss_Sha2_256',['../a00841.html#gaf88819f8def0ed1dc626168103856a25',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f384',['mcuxClRsa_Mode_Sign_Pss_Sha2_384',['../a00841.html#ga884749f4e133157dcdc3b85d15b98ada',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fsign_5fpss_5fsha2_5f512',['mcuxClRsa_Mode_Sign_Pss_Sha2_512',['../a00841.html#gab71896db47c552effcdad152a574e5a1',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fnoverify',['mcuxClRsa_Mode_Verify_NoVerify',['../a00842.html#ga9274985a905326fe0bcbe3ab23123e75',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f224',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224',['../a00842.html#gafaa7d91b00e9a3e5edbcc8ea8d0d2320',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f256',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256',['../a00842.html#gaebc33a997f28ae34f977899c4da4f117',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f384',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384',['../a00842.html#ga6e5c11f4096af091859db6a5f3009c43',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpkcs1v15_5fsha2_5f512',['mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512',['../a00842.html#gafc855e8c67d58fc5b0e79e89eac6d976',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f224',['mcuxClRsa_Mode_Verify_Pss_Sha2_224',['../a00842.html#gaba34c04545877c67789942d9a2c9134a',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f256',['mcuxClRsa_Mode_Verify_Pss_Sha2_256',['../a00842.html#gab80d7f48edeb8b4c401221180572e4f2',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f384',['mcuxClRsa_Mode_Verify_Pss_Sha2_384',['../a00842.html#ga74c434306a9d393e51b4997152381b8e',1,'mcuxClRsa_Constants.h']]], + ['mcuxclrsa_5fmode_5fverify_5fpss_5fsha2_5f512',['mcuxClRsa_Mode_Verify_Pss_Sha2_512',['../a00842.html#ga4214b439b403de8eda53043cdf71ca83',1,'mcuxClRsa_Constants.h']]], + ['minor',['minor',['../a01033.html#a648e4b690824c4652c70d707e00b6ffe',1,'mcuxClEls_HwVersion_t']]], + ['misc',['misc',['../a00973.html#a90f3bfeae254eaa0eb7f5d97f2123906',1,'mcuxClEcc_DomainParam_t']]], + ['mode',['mode',['../a01213.html#a3f8fbc06563e97492965d16d9f7a4ed1',1,'mcuxClEls_TlsOption_t::mode()'],['../a01265.html#ad723b63c438689b0d5c978fceb289506',1,'mcuxClRandom_Config::mode()']]], + ['msg_5fadata',['msg_adata',['../a00041.html#a437ec5d6cef80672b16b267a9038fb3e',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5fenc_5fexpected',['msg_enc_expected',['../a00041.html#a087137335e23969000b7aaee28cb398d',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5fplain',['msg_plain',['../a00041.html#ab5559a8546823f96b075fb6be010313e',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msg_5ftag_5fexpected',['msg_tag_expected',['../a00041.html#abea9520607fe8679a77f6b7f902786af',1,'mcuxClAeadModes_Oneshot_Els_Gcm_Example.c']]], + ['msgendw',['msgendw',['../a00997.html#a6e7b66230e97b647ba209b8f5eb68d2f',1,'mcuxClEls_AeadOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_d.html b/components/els_pkc/doc/mcxn/html/search/variables_d.html new file mode 100644 index 000000000..bd27a70be --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_d.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_d.js b/components/els_pkc/doc/mcxn/html/search/variables_d.js new file mode 100644 index 000000000..e98560258 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_d.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['optlen',['optLen',['../a00977.html#a6d0e636ce4f30294af6bcfe0ae717a01',1,'mcuxClEcc_KeyGen_Param_t::optLen()'],['../a00981.html#af5376d1c58c5cfaf33ae6156572700ff',1,'mcuxClEcc_Sign_Param_t::optLen()'],['../a00985.html#afa16cb1249abe8848bfe2beeb909c4f3',1,'mcuxClEcc_Verify_Param_t::optLen()'],['../a00989.html#a037bdeafd85441ec7c9a5edde80ed772',1,'mcuxClEcc_PointMult_Param_t::optLen()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_e.html b/components/els_pkc/doc/mcxn/html/search/variables_e.html new file mode 100644 index 000000000..f2130e01b --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_e.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_e.js b/components/els_pkc/doc/mcxn/html/search/variables_e.js new file mode 100644 index 000000000..d06439822 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_e.js @@ -0,0 +1,28 @@ +var searchData= +[ + ['pa',['pA',['../a00973.html#a5916c96212c7f76a61ddc0c8aa957ef5',1,'mcuxClEcc_DomainParam_t']]], + ['pb',['pB',['../a00973.html#abcaf03eba7dd8f697e3e582de2aa1eef',1,'mcuxClEcc_DomainParam_t']]], + ['pexp1',['pExp1',['../a01273.html#a28deb463bb016edacb1938dc272deb8a',1,'mcuxClRsa_Key']]], + ['pexp2',['pExp2',['../a01273.html#accac28790b11f7574dd84f6da9877a2c',1,'mcuxClRsa_Key']]], + ['pexp3',['pExp3',['../a01273.html#a0846b30142dc6cb42d05b5c30afd71cc',1,'mcuxClRsa_Key']]], + ['pg',['pG',['../a00973.html#a63d99844f35b075f23980f9c405d034b',1,'mcuxClEcc_DomainParam_t']]], + ['phash',['pHash',['../a00981.html#aeccbb72505744e1f627b67b1f51508ef',1,'mcuxClEcc_Sign_Param_t::pHash()'],['../a00985.html#adb5823e73ed5542ddd0b4a7103e62f1f',1,'mcuxClEcc_Verify_Param_t::pHash()']]], + ['pkcwa',['pkcWa',['../a01285.html#a394996570a6810808bd59d2f9672c76a',1,'mcuxClSession_Descriptor']]], + ['pkeyentrydata',['pKeyEntryData',['../a01269.html#a1f5a90f95105b9abaf31a7997a2fb24e',1,'mcuxClRsa_KeyEntry_t']]], + ['pmod1',['pMod1',['../a01273.html#ab53f60022abcb2c60300022907c460ce',1,'mcuxClRsa_Key']]], + ['pmod2',['pMod2',['../a01273.html#ab1b71c75486149a0b722dfe36d3ca6cd',1,'mcuxClRsa_Key']]], + ['pmpint',['pMPInt',['../a01253.html#a00c20f8c0e84c867dcdfb13cf1549ce6',1,'mcuxClOscca_MPInt_t']]], + ['pn',['pN',['../a00973.html#a484854783a458fd3d3ab50bfd38afcf3',1,'mcuxClEcc_DomainParam_t']]], + ['poutputr',['pOutputR',['../a00985.html#a6b6eb3da4f84de13269bb74d79583b51',1,'mcuxClEcc_Verify_Param_t']]], + ['pp',['pP',['../a00973.html#adbfda4ce0ba171e1aa6f52e6b564d1e4',1,'mcuxClEcc_DomainParam_t']]], + ['ppoint',['pPoint',['../a00989.html#aa8a74b645f7f8b9c611afa1df8c6b523',1,'mcuxClEcc_PointMult_Param_t']]], + ['pprecg',['pPrecG',['../a00985.html#ae5ba73e49b3346a860000f13d05bfbf0',1,'mcuxClEcc_Verify_Param_t']]], + ['pprivatekey',['pPrivateKey',['../a00977.html#a48dad4664822a37f78c78eca1e660a26',1,'mcuxClEcc_KeyGen_Param_t::pPrivateKey()'],['../a00981.html#a0e61b674ac7f46c4157397535d97ce81',1,'mcuxClEcc_Sign_Param_t::pPrivateKey()']]], + ['pprot',['pprot',['../a01045.html#ac5b11ab2a0744e13303e920bee052f5b',1,'mcuxClEls_HwState_t']]], + ['ppublickey',['pPublicKey',['../a00977.html#a96680cb90b6901598b686b38edac1264',1,'mcuxClEcc_KeyGen_Param_t::pPublicKey()'],['../a00985.html#a2db1a83966c659495b7bca80d7b5ab25',1,'mcuxClEcc_Verify_Param_t::pPublicKey()']]], + ['pqinv',['pQInv',['../a01273.html#aa9188b106fa0b275218f8dc04fd9fa79',1,'mcuxClRsa_Key']]], + ['presult',['pResult',['../a00989.html#a6bf3d35fa5651ee8eacd77d9ce1d97bf',1,'mcuxClEcc_PointMult_Param_t']]], + ['prngready',['prngready',['../a01045.html#afbd164dd41b80e5a24310b6dac33cf79',1,'mcuxClEls_HwState_t']]], + ['pscalar',['pScalar',['../a00989.html#a661018eb3da69cf8aa41f08690abc10a',1,'mcuxClEcc_PointMult_Param_t']]], + ['psignature',['pSignature',['../a00981.html#ae25d26ef489ff1614a0a6ab6abe9fc97',1,'mcuxClEcc_Sign_Param_t::pSignature()'],['../a00985.html#ac9477410362aebdb892fdf382864342c',1,'mcuxClEcc_Verify_Param_t::pSignature()']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/search/variables_f.html b/components/els_pkc/doc/mcxn/html/search/variables_f.html new file mode 100644 index 000000000..d66069769 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_f.html @@ -0,0 +1,30 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/components/els_pkc/doc/mcxn/html/search/variables_f.js b/components/els_pkc/doc/mcxn/html/search/variables_f.js new file mode 100644 index 000000000..de5b34a47 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/search/variables_f.js @@ -0,0 +1,10 @@ +var searchData= +[ + ['reset',['reset',['../a01105.html#ae72c778e615b7e6aa4e73eb242beb354',1,'mcuxClEls_CommandCrcConfig_t']]], + ['revf',['revf',['../a01117.html#aa75bf5c0b29ee02a16ca1b31e3300b0f',1,'mcuxClEls_EccSignOption_t::revf()'],['../a01129.html#afbf76f7ebcfc43ca99708cd1064a651a',1,'mcuxClEls_EccVerifyOption_t::revf()'],['../a01141.html#a7e2c0f35b5f6904c1a232f3552cb185f',1,'mcuxClEls_EccKeyGenOption_t::revf()'],['../a01153.html#a2a46aaff0c4f6f2cfa19b302ba713b43',1,'mcuxClEls_EccKeyExchOption_t::revf()'],['../a01225.html#aa699b2cfb2fc82dcbc25d833e09d442e',1,'mcuxClEls_KeyImportOption_t::revf()']]], + ['revision',['revision',['../a01033.html#a11c1bba1b577058ea774f9fb51dfd449',1,'mcuxClEls_HwVersion_t']]], + ['rtf',['rtf',['../a01285.html#ab1b8f498d45832cba336165e6761ce0d',1,'mcuxClSession_Descriptor']]], + ['rtfdrvdat',['rtfdrvdat',['../a01201.html#a7830e4ca489dcbca0e0b535e0979f5cc',1,'mcuxClEls_HkdfOption_t']]], + ['rtfoe',['rtfoe',['../a01165.html#a8c09f754695c9adc3ffe482375fc5f36',1,'mcuxClEls_HashOption_t']]], + ['rtfupd',['rtfupd',['../a01165.html#a1d91adca6cd4e274287063d2ff8d1884',1,'mcuxClEls_HashOption_t']]] +]; diff --git a/components/els_pkc/doc/mcxn/html/splitbar.png b/components/els_pkc/doc/mcxn/html/splitbar.png new file mode 100644 index 0000000000000000000000000000000000000000..fe895f2c58179b471a22d8320b39a4bd7312ec8e GIT binary patch literal 314 zcmeAS@N?(olHy`uVBq!ia0vp^Yzz!63>-{AmhX=Jf(#6djGiuzAr*{o?=JLmPLyc> z_*`QK&+BH@jWrYJ7>r6%keRM@)Qyv8R=enp0jiI>aWlGyB58O zFVR20d+y`K7vDw(hJF3;>dD*3-?v=<8M)@x|EEGLnJsniYK!2U1 Y!`|5biEc?d1`HDhPgg&ebxsLQ02F6;9RL6T literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/sync_off.png b/components/els_pkc/doc/mcxn/html/sync_off.png new file mode 100644 index 0000000000000000000000000000000000000000..3b443fc62892114406e3d399421b2a881b897acc GIT binary patch literal 853 zcmV-b1FHOqP)oT|#XixUYy%lpuf3i8{fX!o zUyDD0jOrAiT^tq>fLSOOABs-#u{dV^F$b{L9&!2=9&RmV;;8s^x&UqB$PCj4FdKbh zoB1WTskPUPu05XzFbA}=KZ-GP1fPpAfSs>6AHb12UlR%-i&uOlTpFNS7{jm@mkU1V zh`nrXr~+^lsV-s1dkZOaI|kYyVj3WBpPCY{n~yd%u%e+d=f%`N0FItMPtdgBb@py; zq@v6NVArhyTC7)ULw-Jy8y42S1~4n(3LkrW8mW(F-4oXUP3E`e#g**YyqI7h-J2zK zK{m9##m4ri!7N>CqQqCcnI3hqo1I;Yh&QLNY4T`*ptiQGozK>FF$!$+84Z`xwmeMh zJ0WT+OH$WYFALEaGj2_l+#DC3t7_S`vHpSivNeFbP6+r50cO8iu)`7i%Z4BTPh@_m3Tk!nAm^)5Bqnr%Ov|Baunj#&RPtRuK& z4RGz|D5HNrW83-#ydk}tVKJrNmyYt-sTxLGlJY5nc&Re zU4SgHNPx8~Yxwr$bsju?4q&%T1874xxzq+_%?h8_ofw~(bld=o3iC)LUNR*BY%c0y zWd_jX{Y8`l%z+ol1$@Qa?Cy!(0CVIEeYpKZ`(9{z>3$CIe;pJDQk$m3p}$>xBm4lb zKo{4S)`wdU9Ba9jJbVJ0C=SOefZe%d$8=2r={nu<_^a3~>c#t_U6dye5)JrR(_a^E f@}b6j1K9lwFJq@>o)+Ry00000NkvXXu0mjfWa5j* literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/sync_on.png b/components/els_pkc/doc/mcxn/html/sync_on.png new file mode 100644 index 0000000000000000000000000000000000000000..e08320fb64e6fa33b573005ed6d8fe294e19db76 GIT binary patch literal 845 zcmV-T1G4;yP)Y;xxyHF2B5Wzm| zOOGupOTn@c(JmBOl)e;XMNnZuiTJP>rM8<|Q`7I_))aP?*T)ow&n59{}X4$3Goat zgjs?*aasfbrokzG5cT4K=uG`E14xZl@z)F={P0Y^?$4t z>v!teRnNZym<6h{7sLyF1V0HsfEl+l6TrZpsfr1}luH~F7L}ktXu|*uVX^RG$L0`K zWs3j|0tIvVe(N%_?2{(iCPFGf#B6Hjy6o&}D$A%W%jfO8_W%ZO#-mh}EM$LMn7joJ z05dHr!5Y92g+31l<%i1(=L1a1pXX+OYnalY>31V4K}BjyRe3)9n#;-cCVRD_IG1fT zOKGeNY8q;TL@K{dj@D^scf&VCs*-Jb>8b>|`b*osv52-!A?BpbYtTQBns5EAU**$m zSnVSm(teh>tQi*S*A>#ySc=n;`BHz`DuG4&g4Kf8lLhca+zvZ7t7RflD6-i-mcK=M z!=^P$*u2)bkY5asG4gsss!Hn%u~>}kIW`vMs%lJLH+u*9<4PaV_c6U`KqWXQH%+Nu zTv41O(^ZVi@qhjQdG!fbZw&y+2o!iYymO^?ud3{P*HdoX83YV*Uu_HB=?U&W9%AU# z80}k1SS-CXTU7dcQlsm<^oYLxVSseqY6NO}dc`Nj?8vrhNuCdm@^{a3AQ_>6myOj+ z`1RsLUXF|dm|3k7s2jD(B{rzE>WI2scH8i1;=O5Cc9xB3^aJk%fQjqsu+kH#0=_5a z0nCE8@dbQa-|YIuUVvG0L_IwHMEhOj$Mj4Uq05 X8=0q~qBNan00000NkvXXu0mjfptF>5 literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/tab_a.png b/components/els_pkc/doc/mcxn/html/tab_a.png new file mode 100644 index 0000000000000000000000000000000000000000..3b725c41c5a527a3a3e40097077d0e206a681247 GIT binary patch literal 142 zcmeAS@N?(olHy`uVBq!ia0vp^j6kfy!2~3aiye;!QlXwMjv*C{Z|8b*H5dputLHD# z=<0|*y7z(Vor?d;H&?EG&cXR}?!j-Lm&u1OOI7AIF5&c)RFE;&p0MYK>*Kl@eiymD r@|NpwKX@^z+;{u_Z~trSBfrMKa%3`zocFjEXaR$#tDnm{r-UW|TZ1%4 literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/tab_b.png b/components/els_pkc/doc/mcxn/html/tab_b.png new file mode 100644 index 0000000000000000000000000000000000000000..e2b4a8638cb3496a016eaed9e16ffc12846dea18 GIT binary patch literal 169 zcmeAS@N?(olHy`uVBq!ia0vp^j6kfy!2~3aiye;!QU#tajv*C{Z}0l@H7kg?K0Lnr z!j&C6_(~HV9oQ0Pa6x{-v0AGV_E?vLn=ZI-;YrdjIl`U`uzuDWSP?o#Dmo{%SgM#oan kX~E1%D-|#H#QbHoIja2U-MgvsK&LQxy85}Sb4q9e0Efg%P5=M^ literal 0 HcmV?d00001 diff --git a/components/els_pkc/doc/mcxn/html/tabs.css b/components/els_pkc/doc/mcxn/html/tabs.css new file mode 100644 index 000000000..8ea7d5496 --- /dev/null +++ b/components/els_pkc/doc/mcxn/html/tabs.css @@ -0,0 +1 @@ +.sm{position:relative;z-index:9999}.sm,.sm ul,.sm li{display:block;list-style:none;margin:0;padding:0;line-height:normal;direction:ltr;text-align:left;-webkit-tap-highlight-color:rgba(0,0,0,0)}.sm-rtl,.sm-rtl ul,.sm-rtl li{direction:rtl;text-align:right}.sm>li>h1,.sm>li>h2,.sm>li>h3,.sm>li>h4,.sm>li>h5,.sm>li>h6{margin:0;padding:0}.sm ul{display:none}.sm li,.sm a{position:relative}.sm a{display:block}.sm a.disabled{cursor:not-allowed}.sm:after{content:"\00a0";display:block;height:0;font:0/0 serif;clear:both;visibility:hidden;overflow:hidden}.sm,.sm *,.sm *:before,.sm *:after{-moz-box-sizing:border-box;-webkit-box-sizing:border-box;box-sizing:border-box}.sm-dox{background-image:url("tab_b.png")}.sm-dox a,.sm-dox a:focus,.sm-dox a:hover,.sm-dox a:active{padding:0 12px;padding-right:43px;font-family:"Lucida Grande","Geneva","Helvetica",Arial,sans-serif;font-size:13px;font-weight:bold;line-height:36px;text-decoration:none;text-shadow:0 1px 1px rgba(255,255,255,0.9);color:#283a5d;outline:0}.sm-dox a:hover{background-image:url("tab_a.png");background-repeat:repeat-x;color:white;text-shadow:0 1px 1px black}.sm-dox a.current{color:#d23600}.sm-dox a.disabled{color:#bbb}.sm-dox a span.sub-arrow{position:absolute;top:50%;margin-top:-14px;left:auto;right:3px;width:28px;height:28px;overflow:hidden;font:bold 12px/28px monospace !important;text-align:center;text-shadow:none;background:rgba(255,255,255,0.5);-moz-border-radius:5px;-webkit-border-radius:5px;border-radius:5px}.sm-dox a.highlighted span.sub-arrow:before{display:block;content:'-'}.sm-dox>li:first-child>a,.sm-dox>li:first-child>:not(ul) a{-moz-border-radius:5px 5px 0 0;-webkit-border-radius:5px;border-radius:5px 5px 0 0}.sm-dox>li:last-child>a,.sm-dox>li:last-child>*:not(ul) a,.sm-dox>li:last-child>ul,.sm-dox>li:last-child>ul>li:last-child>a,.sm-dox>li:last-child>ul>li:last-child>*:not(ul) a,.sm-dox>li:last-child>ul>li:last-child>ul,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul{-moz-border-radius:0 0 5px 5px;-webkit-border-radius:0;border-radius:0 0 5px 5px}.sm-dox>li:last-child>a.highlighted,.sm-dox>li:last-child>*:not(ul) a.highlighted,.sm-dox>li:last-child>ul>li:last-child>a.highlighted,.sm-dox>li:last-child>ul>li:last-child>*:not(ul) a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>a.highlighted,.sm-dox>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>ul>li:last-child>*:not(ul) a.highlighted{-moz-border-radius:0;-webkit-border-radius:0;border-radius:0}.sm-dox ul{background:rgba(162,162,162,0.1)}.sm-dox ul a,.sm-dox ul a:focus,.sm-dox ul a:hover,.sm-dox ul a:active{font-size:12px;border-left:8px solid transparent;line-height:36px;text-shadow:none;background-color:white;background-image:none}.sm-dox ul a:hover{background-image:url("tab_a.png");background-repeat:repeat-x;color:white;text-shadow:0 1px 1px black}.sm-dox ul ul a,.sm-dox ul ul a:hover,.sm-dox ul ul a:focus,.sm-dox ul ul a:active{border-left:16px solid transparent}.sm-dox ul ul ul a,.sm-dox ul ul ul a:hover,.sm-dox ul ul ul a:focus,.sm-dox ul ul ul a:active{border-left:24px solid transparent}.sm-dox ul ul ul ul a,.sm-dox ul ul ul ul a:hover,.sm-dox ul ul ul ul a:focus,.sm-dox ul ul ul ul a:active{border-left:32px solid transparent}.sm-dox ul ul ul ul ul a,.sm-dox ul ul ul ul ul a:hover,.sm-dox ul ul ul ul ul a:focus,.sm-dox ul ul ul ul ul a:active{border-left:40px solid transparent}@media(min-width:768px){.sm-dox ul{position:absolute;width:12em}.sm-dox li{float:left}.sm-dox.sm-rtl li{float:right}.sm-dox ul li,.sm-dox.sm-rtl ul li,.sm-dox.sm-vertical li{float:none}.sm-dox a{white-space:nowrap}.sm-dox ul a,.sm-dox.sm-vertical a{white-space:normal}.sm-dox .sm-nowrap>li>a,.sm-dox .sm-nowrap>li>:not(ul) a{white-space:nowrap}.sm-dox{padding:0 10px;background-image:url("tab_b.png");line-height:36px}.sm-dox a span.sub-arrow{top:50%;margin-top:-2px;right:12px;width:0;height:0;border-width:4px;border-style:solid dashed dashed dashed;border-color:#283a5d transparent transparent transparent;background:transparent;-moz-border-radius:0;-webkit-border-radius:0;border-radius:0}.sm-dox a,.sm-dox a:focus,.sm-dox a:active,.sm-dox a:hover,.sm-dox a.highlighted{padding:0 12px;background-image:url("tab_s.png");background-repeat:no-repeat;background-position:right;-moz-border-radius:0 !important;-webkit-border-radius:0;border-radius:0 !important}.sm-dox a:hover{background-image:url("tab_a.png");background-repeat:repeat-x;color:white;text-shadow:0 1px 1px black}.sm-dox a:hover span.sub-arrow{border-color:white transparent transparent transparent}.sm-dox a.has-submenu{padding-right:24px}.sm-dox li{border-top:0}.sm-dox>li>ul:before,.sm-dox>li>ul:after{content:'';position:absolute;top:-18px;left:30px;width:0;height:0;overflow:hidden;border-width:9px;border-style:dashed dashed solid dashed;border-color:transparent transparent #bbb transparent}.sm-dox>li>ul:after{top:-16px;left:31px;border-width:8px;border-color:transparent transparent #fff transparent}.sm-dox ul{border:1px solid #bbb;padding:5px 0;background:#fff;-moz-border-radius:5px !important;-webkit-border-radius:5px;border-radius:5px !important;-moz-box-shadow:0 5px 9px rgba(0,0,0,0.2);-webkit-box-shadow:0 5px 9px rgba(0,0,0,0.2);box-shadow:0 5px 9px rgba(0,0,0,0.2)}.sm-dox ul a span.sub-arrow{right:8px;top:50%;margin-top:-5px;border-width:5px;border-color:transparent transparent transparent #555;border-style:dashed dashed dashed solid}.sm-dox ul a,.sm-dox ul a:hover,.sm-dox ul a:focus,.sm-dox ul a:active,.sm-dox ul a.highlighted{color:#555;background-image:none;border:0 !important;color:#555;background-image:none}.sm-dox ul a:hover{background-image:url("tab_a.png");background-repeat:repeat-x;color:white;text-shadow:0 1px 1px black}.sm-dox ul a:hover span.sub-arrow{border-color:transparent transparent transparent white}.sm-dox span.scroll-up,.sm-dox span.scroll-down{position:absolute;display:none;visibility:hidden;overflow:hidden;background:#fff;height:36px}.sm-dox span.scroll-up:hover,.sm-dox span.scroll-down:hover{background:#eee}.sm-dox span.scroll-up:hover span.scroll-up-arrow,.sm-dox span.scroll-up:hover span.scroll-down-arrow{border-color:transparent transparent #d23600 transparent}.sm-dox span.scroll-down:hover span.scroll-down-arrow{border-color:#d23600 transparent transparent transparent}.sm-dox span.scroll-up-arrow,.sm-dox span.scroll-down-arrow{position:absolute;top:0;left:50%;margin-left:-6px;width:0;height:0;overflow:hidden;border-width:6px;border-style:dashed dashed solid dashed;border-color:transparent transparent #555 transparent}.sm-dox span.scroll-down-arrow{top:8px;border-style:solid dashed dashed dashed;border-color:#555 transparent transparent transparent}.sm-dox.sm-rtl a.has-submenu{padding-right:12px;padding-left:24px}.sm-dox.sm-rtl a span.sub-arrow{right:auto;left:12px}.sm-dox.sm-rtl.sm-vertical a.has-submenu{padding:10px 20px}.sm-dox.sm-rtl.sm-vertical a span.sub-arrow{right:auto;left:8px;border-style:dashed solid dashed dashed;border-color:transparent #555 transparent transparent}.sm-dox.sm-rtl>li>ul:before{left:auto;right:30px}.sm-dox.sm-rtl>li>ul:after{left:auto;right:31px}.sm-dox.sm-rtl ul a.has-submenu{padding:10px 20px !important}.sm-dox.sm-rtl ul a span.sub-arrow{right:auto;left:8px;border-style:dashed solid dashed dashed;border-color:transparent #555 transparent transparent}.sm-dox.sm-vertical{padding:10px 0;-moz-border-radius:5px;-webkit-border-radius:5px;border-radius:5px}.sm-dox.sm-vertical a{padding:10px 20px}.sm-dox.sm-vertical a:hover,.sm-dox.sm-vertical a:focus,.sm-dox.sm-vertical a:active,.sm-dox.sm-vertical a.highlighted{background:#fff}.sm-dox.sm-vertical a.disabled{background-image:url("tab_b.png")}.sm-dox.sm-vertical a span.sub-arrow{right:8px;top:50%;margin-top:-5px;border-width:5px;border-style:dashed dashed dashed solid;border-color:transparent transparent transparent #555}.sm-dox.sm-vertical>li>ul:before,.sm-dox.sm-vertical>li>ul:after{display:none}.sm-dox.sm-vertical ul a{padding:10px 20px}.sm-dox.sm-vertical ul a:hover,.sm-dox.sm-vertical ul a:focus,.sm-dox.sm-vertical ul a:active,.sm-dox.sm-vertical ul a.highlighted{background:#eee}.sm-dox.sm-vertical ul a.disabled{background:#fff}} \ No newline at end of file diff --git a/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Multipart_Els_Ccm_Example.c b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Multipart_Els_Ccm_Example.c new file mode 100644 index 000000000..d2d465511 --- /dev/null +++ b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Multipart_Els_Ccm_Example.c @@ -0,0 +1,302 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file: mcuxClAeadModes_Multipart_Els_Ccm_Example.c + * @brief: Example Aead application + */ + +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClAead component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include // bool type for the example's return code +#include + +static const uint8_t msg_plain[24] = { + 0x20u, 0x21u, 0x22u, 0x23u, 0x24u, 0x25u, 0x26u, 0x27u, + 0x28u, 0x29u, 0x2au, 0x2bu, 0x2cu, 0x2du, 0x2eu, 0x2fu, + 0x30u, 0x31u, 0x32u, 0x33u, 0x34u, 0x35u, 0x36u, 0x37u +}; + +static const uint8_t msg_adata[20] = { + 0x00u, 0x01u, 0x02u, 0x03u, 0x04u, 0x05u, 0x06u, 0x07u, + 0x08u, 0x09u, 0x0au, 0x0bu, 0x0cu, 0x0du, 0x0eu, 0x0fu, + 0x10u, 0x11u, 0x12u, 0x13u +}; + +static const uint8_t aes128_iv[12] = { + 0x10u, 0x11u, 0x12u, 0x13u, 0x14u, 0x15u, 0x16u, 0x17u, + 0x18u, 0x19u, 0x1au, 0x1bu +}; + +static const uint8_t aes128_key[16] = { + 0x40u, 0x41u, 0x42u, 0x43u, 0x44u, 0x45u, 0x46u, 0x47u, + 0x48u, 0x49u, 0x4au, 0x4bu, 0x4cu, 0x4du, 0x4eu, 0x4fu +}; + +static const uint8_t msg_tag_expected[8] = { + 0x48u, 0x43u, 0x92u, 0xfbu, 0xc1u, 0xb0u, 0x99u, 0x51 +}; + +static const uint8_t msg_enc_expected[24] = { + 0xe3u, 0xb2u, 0x01u, 0xa9u, 0xf5u, 0xb7u, 0x1au, 0x7a, + 0x9bu, 0x1cu, 0xeau, 0xecu, 0xcdu, 0x97u, 0xe7u, 0x0b, + 0x61u, 0x76u, 0xaau, 0xd9u, 0xa4u, 0x42u, 0x8au, 0xa5 +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Multipart_Els_Ccm_Example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLAEAD_WA_SIZE_MAX + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + mcuxClEls_KeyProp_t key_properties; + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[sizeof(msg_enc_expected)]; + uint32_t msg_enc_size = 0u; + + uint8_t msg_tag[sizeof(msg_tag_expected)]; + + uint8_t ctxBuf[MCUXCLAEAD_CONTEXT_SIZE]; + mcuxClAead_Context_t *ctx = (mcuxClAead_Context_t *) ctxBuf; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClAead_init( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_CCM_ENC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* uint32_t inSize, */ sizeof(msg_plain), + /* uint32_t adataSize, */ sizeof(msg_adata), + /* uint32_t tagSize */ sizeof(msg_tag_expected) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_init) != token_init) || (MCUXCLAEAD_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* + * mcuxClAead_process_adata() processes the header data. This needs to be completed + * before other data can be processed. Therefore all calls to mcuxClAead_process_adata() + * need to be made before calls to mcuxClAead_process(). + */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_aad, token_aad, mcuxClAead_process_adata( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_process_adata) != token_aad) || (MCUXCLAEAD_STATUS_OK != result_aad)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_indata, token_indata, mcuxClAead_process( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_InputBuffer_t pIn, */ msg_plain, + /* uint32_t inSize, */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut, */ msg_enc, + /* uint32_t * const pOutSize */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_process) != token_indata) || (MCUXCLAEAD_STATUS_OK != result_indata)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_final, token_final, mcuxClAead_finish( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_Buffer_t pOut, */ &msg_enc[msg_enc_size], + /* uint32_t * const pOutSize */ &msg_enc_size, + /* mcuxCl_Buffer_t pTag, */ msg_tag + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_finish) != token_final) || (MCUXCLAEAD_STATUS_OK != result_final)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < msg_enc_size; i++) + { + if (msg_enc[i] != msg_enc_expected[i]) // Expect that the resulting encrypted msg matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + // TODO: change to MCUXCLELS_AEAD_TAG_SIZE + for (size_t i = 0U; i < sizeof(msg_tag_expected); i++) + { + if (msg_tag[i] != msg_tag_expected[i]) // Expect that the resulting authentication tag matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[sizeof(msg_plain)]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClAead_init( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_CCM_DEC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* uint32_t inSize, */ sizeof(msg_plain), + /* uint32_t adataSize, */ sizeof(msg_adata), + /* uint32_t tagSize */ sizeof(msg_tag_expected) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_init) != token_init) || (MCUXCLAEAD_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* + * mcuxClAead_process_adata() processes the header data. This needs to be completed + * before other data can be processed. Therefore all calls to mcuxClAead_process_adata() + * need to be made before calls to mcuxClAead_process(). + */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_aad, token_aad, mcuxClAead_process_adata( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_process_adata) != token_aad) || (MCUXCLAEAD_STATUS_OK != result_aad)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_indata, token_indata, mcuxClAead_process( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_InputBuffer_t pIn, */ msg_enc, + /* uint32_t inSize, */ msg_enc_size, + /* mcuxCl_Buffer_t pOut, */ msg_dec, + /* uint32_t * const pOutSize */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_process) != token_indata) || (MCUXCLAEAD_STATUS_OK != result_indata)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_verify, token_verify, mcuxClAead_verify( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t pContext, */ ctx, + /* mcuxCl_Buffer_t pTag, */ msg_tag, + /* mcuxCl_Buffer_t pOut, */ &msg_dec[msg_dec_size], + /* uint32_t * const pOutSize */ &msg_dec_size + )); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_verify) != token_verify) || (MCUXCLAEAD_STATUS_OK != result_verify)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Ccm_Example.c b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Ccm_Example.c new file mode 100644 index 000000000..053acc2aa --- /dev/null +++ b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Ccm_Example.c @@ -0,0 +1,223 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file: mcuxClAeadModes_Oneshot_Els_Ccm_Example.c + * @brief: Example Aead application + */ + +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClAead component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include // bool type for the example's return code +#include + +/* NIST Special Publication 800-38C example 2 test vectors */ +static const uint8_t msg_plain[16] = { + 0x20u, 0x21u, 0x22u, 0x23u, 0x24u, 0x25u, 0x26u, 0x27u, + 0x28u, 0x29u, 0x2au, 0x2bu, 0x2cu, 0x2du, 0x2eu, 0x2fu +}; + +static const uint8_t msg_adata[16] = { + 0x00u, 0x01u, 0x02u, 0x03u, 0x04u, 0x05u, 0x06u, 0x07u, + 0x08u, 0x09u, 0x0au, 0x0bu, 0x0cu, 0x0du, 0x0eu, 0x0fu +}; + +static const uint8_t aes128_iv[8] = { + 0x10u, 0x11u, 0x12u, 0x13u, 0x14u, 0x15u, 0x16u, 0x17u +}; + +static const uint8_t aes128_key[16] = { + 0x40u, 0x41u, 0x42u, 0x43u, 0x44u, 0x45u, 0x46u, 0x47u, + 0x48u, 0x49u, 0x4au, 0x4bu, 0x4cu, 0x4du, 0x4eu, 0x4fu +}; + +static const uint8_t msg_tag_expected[6] = { + 0x1fu, 0xc6u, 0x4fu, 0xbfu, 0xacu, 0xcdu +}; + +static const uint8_t msg_enc_expected[16] = { + 0xd2u, 0xa1u, 0xf0u, 0xe0u, 0x51u, 0xeau, 0x5fu, 0x62u, + 0x08u, 0x1au, 0x77u, 0x92u, 0x07u, 0x3du, 0x59u, 0x3du +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Ccm_Example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[sizeof(msg_enc_expected)]; + uint32_t msg_enc_size = 0u; + + uint8_t msg_tag[sizeof(msg_tag_expected)]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClAead_crypt( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_CCM_ENC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn, */ msg_plain, + /* uint32_t inSize, */ sizeof(msg_plain), + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata), + /* mcuxCl_Buffer_t pOut, */ msg_enc, + /* uint32_t * const pOutSize */ &msg_enc_size, + /* mcuxCl_Buffer_t pTag, */ msg_tag, + /* uint32_t tagSize */ sizeof(msg_tag_expected) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_crypt) != token_enc) || (MCUXCLAEAD_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < msg_enc_size; i++) + { + if (msg_enc[i] != msg_enc_expected[i]) // Expect that the resulting encrypted msg matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + // TODO: change to MCUXCLELS_AEAD_TAG_SIZE + for (size_t i = 0U; i < sizeof(msg_tag_expected); i++) + { + if (msg_tag[i] != msg_tag_expected[i]) // Expect that the resulting authentication tag matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[sizeof(msg_plain)]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClAead_crypt( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_CCM_DEC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn, */ msg_enc, + /* uint32_t inSize, */ msg_enc_size, + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata), + /* mcuxCl_Buffer_t pOut, */ msg_dec, + /* uint32_t * const pOutSize */ &msg_dec_size, + /* mcuxCl_Buffer_t pTag, */ msg_tag, + /* uint32_t tagSize */ sizeof(msg_tag_expected) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_crypt) != token_dec) || (MCUXCLAEAD_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < msg_dec_size; i++) + { + if (msg_dec[i] != msg_plain[i]) // Expect that the resulting decrypted msg matches our initial message + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Gcm_Example.c b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Gcm_Example.c new file mode 100644 index 000000000..c5bbb82ee --- /dev/null +++ b/components/els_pkc/examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Gcm_Example.c @@ -0,0 +1,227 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file: mcuxClAeadModes_Oneshot_Els_Gcm_Example.c + * @brief: Example Aead application + */ + +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClAead component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include // bool type for the example's return code +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[16u] = {0x2BU, 0x7EU, 0x15U, 0x16U, + 0x28U, 0xAEU, 0xD2U, 0xA6U, + 0xABU, 0xF7U, 0x15U, 0x88U, + 0x09U, 0xCFU, 0x4FU, 0x3CU}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[12u] = {0xF8U, 0xD2U, 0x68U, 0x76U, + 0x81U, 0x6FU, 0x0FU, 0xBAU, + 0x86U, 0x2BU, 0xD8U, 0xA3U}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[16u] = {0x6BU, 0xC1U, 0xBEU, 0xE2U, + 0x2EU, 0x40U, 0x9FU, 0x96U, + 0xE9U, 0x3DU, 0x7EU, 0x11U, + 0x73U, 0x93U, 0x17U, 0x2AU}; + +/** Additional authenticated data. */ +static uint8_t const msg_adata[16u] = {0xCAU, 0xEAU, 0x07U, 0x26U, + 0x62U, 0xE2U, 0x20U, 0x06U, + 0x2DU, 0x45U, 0x46U, 0x41U, + 0x5EU, 0xFFU, 0xFAU, 0xD2U}; + +/** Expected ciphertext output of the AES-GCM encryption. */ +static uint8_t const msg_enc_expected[16u] = {0x4FU, 0x74U, 0x2DU, 0xF6U, + 0x9DU, 0x1CU, 0x03U, 0x6BU, + 0x56U, 0xBCU, 0xC2U, 0x81U, + 0x5FU, 0xDAU, 0x8DU, 0x6DU}; + +/** Expected authentication tag output. */ +static uint8_t const msg_tag_expected[16u] = {0xB2U, 0xC5U, 0xCFU, 0xC3U, + 0xF2U, 0x8CU, 0x9FU, 0x78U, + 0xFCU, 0x25U, 0xBCU, 0x10U, + 0xC9U, 0xCAU, 0xFFU, 0xD5U}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClAeadModes_Oneshot_Els_Gcm_Example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[sizeof(msg_enc_expected)]; + uint32_t msg_enc_size = 0u; + + uint8_t msg_tag[32]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClAead_crypt( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_GCM_ENC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn, */ msg_plain, + /* uint32_t inSize, */ sizeof(msg_plain), + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata), + /* mcuxCl_Buffer_t pOut, */ msg_enc, + /* uint32_t * const pOutSize */ &msg_enc_size, + /* mcuxCl_Buffer_t pTag, */ msg_tag, + /* uint32_t tagSize */ 16u + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_crypt) != token_enc) || (MCUXCLAEAD_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < msg_enc_size; i++) + { + if (msg_enc[i] != msg_enc_expected[i]) // Expect that the resulting encrypted msg matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + // TODO: change to MCUXCLELS_AEAD_TAG_SIZE + for (size_t i = 0U; i < 16u; i++) + { + if (msg_tag[i] != msg_tag_expected[i]) // Expect that the resulting authentication tag matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[sizeof(msg_plain)]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClAead_crypt( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mcuxClAead_Mode_AES_GCM_DEC, + /* mcuxCl_InputBuffer_t pNonce, */ aes128_iv, + /* uint32_t nonceSize, */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn, */ msg_enc, + /* uint32_t inSize, */ msg_enc_size, + /* mcuxCl_InputBuffer_t pAdata, */ msg_adata, + /* uint32_t adataSize, */ sizeof(msg_adata), + /* mcuxCl_Buffer_t pOut, */ msg_dec, + /* uint32_t * const pOutSize */ &msg_dec_size, + /* mcuxCl_Buffer_t pTag, */ msg_tag, + /* uint32_t tagSize */ 16u + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAead_crypt) != token_dec) || (MCUXCLAEAD_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < msg_dec_size; i++) + { + if (msg_dec[i] != msg_plain[i]) // Expect that the resulting decrypted msg matches our initial message + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Cbc_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Cbc_Els_example.c new file mode 100644 index 000000000..ade86cef7 --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Cbc_Els_example.c @@ -0,0 +1,212 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLAES_BLOCK_SIZE] = { + 0xF8u, 0xD2u, 0x68u, 0x76u, + 0x81u, 0x6Fu, 0x0Fu, 0xBAu, + 0x86u, 0x2Bu, 0xD8u, 0xA3u, + 0x2Du, 0x04u, 0x67u, 0xC3u +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[MCUXCLAES_BLOCK_SIZE] = { + 0x6Bu, 0xC1u, 0xBEu, 0xE2u, + 0x2Eu, 0x40u, 0x9Fu, 0x96u, + 0xE9u, 0x3Du, 0x7Eu, 0x11u, + 0x73u, 0x93u, 0x17u, 0x2Au +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[MCUXCLAES_BLOCK_SIZE] = { + 0xCAu, 0xEAu, 0x07u, 0x26u, + 0x62u, 0xE2u, 0x20u, 0x06u, + 0x2Du, 0x45u, 0x46u, 0x41u, + 0x5Eu, 0xFFu, 0xFAu, 0xD2u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Multipart_Cbc_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create a buffer for the context */ + uint8_t ctxBuf[MCUXCLCIPHER_AES_CONTEXT_SIZE]; + mcuxClCipher_Context_t * const ctx = (mcuxClCipher_Context_t *) ctxBuf; + + /* Declare message buffer and size. */ + uint8_t msg_enc[MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + /**************************************************************************/ + /* Init */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClCipher_init( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext: */ ctx, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CBC_Enc_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_init) != token_init) || (MCUXCLCIPHER_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Process */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_proc, token_proc, mcuxClCipher_process( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_process) != token_proc) || (MCUXCLCIPHER_STATUS_OK != result_proc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Finish */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_fin, token_fin, mcuxClCipher_finish( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_finish) != token_fin) || (MCUXCLCIPHER_STATUS_OK != result_fin)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ctr_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ctr_Els_example.c new file mode 100644 index 000000000..1e96bce9a --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ctr_Els_example.c @@ -0,0 +1,212 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLAES_BLOCK_SIZE] = { + 0xF8u, 0xD2u, 0x68u, 0x76u, + 0x81u, 0x6Fu, 0x0Fu, 0xBAu, + 0x86u, 0x2Bu, 0xD8u, 0xA3u, + 0x2Du, 0x04u, 0x67u, 0xC3u +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[MCUXCLAES_BLOCK_SIZE] = { + 0x6Bu, 0xC1u, 0xBEu, 0xE2u, + 0x2Eu, 0x40u, 0x9Fu, 0x96u, + 0xE9u, 0x3Du, 0x7Eu, 0x11u, + 0x73u, 0x93u, 0x17u, 0x2Au +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[MCUXCLAES_BLOCK_SIZE] = { + 0x1Au, 0x75u, 0xE5u, 0xF9u, + 0x98u, 0x9Eu, 0xC2u, 0x84u, + 0x41u, 0x74u, 0x62u, 0xBDu, + 0xFBu, 0x16u, 0xF9u, 0xA5u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Multipart_Ctr_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create a buffer for the context */ + uint8_t ctxBuf[MCUXCLCIPHER_AES_CONTEXT_SIZE]; + mcuxClCipher_Context_t * const ctx = (mcuxClCipher_Context_t *) ctxBuf; + + /* Declare message buffer and size. */ + uint8_t msg_enc[MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + /**************************************************************************/ + /* Init */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClCipher_init( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext: */ ctx, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CTR, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_init) != token_init) || (MCUXCLCIPHER_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Process */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_proc, token_proc, mcuxClCipher_process( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_process) != token_proc) || (MCUXCLCIPHER_STATUS_OK != result_proc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Finish */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_fin, token_fin, mcuxClCipher_finish( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_finish) != token_fin) || (MCUXCLCIPHER_STATUS_OK != result_fin)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_Els_example.c new file mode 100644 index 000000000..ae7f8e544 --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_Els_example.c @@ -0,0 +1,204 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[MCUXCLAES_BLOCK_SIZE] = { + 0x6Bu, 0xC1u, 0xBEu, 0xE2u, + 0x2Eu, 0x40u, 0x9Fu, 0x96u, + 0xE9u, 0x3Du, 0x7Eu, 0x11u, + 0x73u, 0x93u, 0x17u, 0x2Au +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[MCUXCLAES_BLOCK_SIZE] = { + 0x3Au, 0xD7u, 0x7Bu, 0xB4u, + 0x0Du, 0x7Au, 0x36u, 0x60u, + 0xA8u, 0x9Eu, 0xCAu, 0xF3u, + 0x24u, 0x66u, 0xEFu, 0x97u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Multipart_Ecb_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create a buffer for the context */ + uint8_t ctxBuf[MCUXCLCIPHER_AES_CONTEXT_SIZE]; + mcuxClCipher_Context_t * const ctx = (mcuxClCipher_Context_t *) ctxBuf; + + /* Declare message buffer and size. */ + uint8_t msg_enc[MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + /**************************************************************************/ + /* Init */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClCipher_init( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext: */ ctx, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Enc_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_init) != token_init) || (MCUXCLCIPHER_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Process */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_proc, token_proc, mcuxClCipher_process( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_process) != token_proc) || (MCUXCLCIPHER_STATUS_OK != result_proc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Finish */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_fin, token_fin, mcuxClCipher_finish( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_finish) != token_fin) || (MCUXCLCIPHER_STATUS_OK != result_fin)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_PaddingPKCS7_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_PaddingPKCS7_Els_example.c new file mode 100644 index 000000000..25bbfa49f --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_PaddingPKCS7_Els_example.c @@ -0,0 +1,208 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +static const uint8_t msg_plain[62] = { + 0x61u, 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, + 0x69u, 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, + 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, + 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, + 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, + 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x72u, + 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, 0x6Bu, + 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u +}; + +/* ECB encrypted data */ +static const uint8_t msg_enc_expected[64] = { + 0x82u, 0x4fu, 0x7au, 0xb3u, 0xdfu, 0x5eu, 0x73u, 0x42u, + 0x35u, 0xbbu, 0xcfu, 0xeau, 0xdau, 0x7eu, 0x74u, 0xc1u, + 0x7au, 0x08u, 0x34u, 0x2du, 0x49u, 0xacu, 0xadu, 0x72u, + 0x0eu, 0xb3u, 0x23u, 0xb6u, 0x49u, 0x42u, 0x01u, 0xf2u, + 0x06u, 0x87u, 0x58u, 0xcfu, 0x41u, 0xb0u, 0xd6u, 0x63u, + 0x66u, 0x50u, 0x1bu, 0xe8u, 0x05u, 0x66u, 0xa8u, 0xfbu, + 0xf4u, 0x8fu, 0x4du, 0xa2u, 0x73u, 0x10u, 0x7eu, 0xd7u, + 0xfau, 0xf5u, 0x52u, 0x15u, 0x53u, 0x93u, 0x54u, 0x40u +}; + +static const uint8_t aes128_key[16] = { + 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x72u, + 0x73u, 0x74u, 0x75u, 0x76u, 0x77u, 0x78u, 0x79u, 0x7Au, +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Multipart_Ecb_PaddingPKCS7_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[4]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create a buffer for the context */ + uint8_t ctxBuf[MCUXCLCIPHER_AES_CONTEXT_SIZE]; + mcuxClCipher_Context_t * const ctx = (mcuxClCipher_Context_t *) ctxBuf; + + /* Declare message buffer and size. */ + uint8_t msg_enc[sizeof(msg_enc_expected)]; + uint32_t msg_enc_size = 0u; + + /**************************************************************************/ + /* Init */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_init, token_init, mcuxClCipher_init( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext: */ ctx, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_init) != token_init) || (MCUXCLCIPHER_STATUS_OK != result_init)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Process */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_proc, token_proc, mcuxClCipher_process( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_process) != token_proc) || (MCUXCLCIPHER_STATUS_OK != result_proc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Finish */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_fin, token_fin, mcuxClCipher_finish( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClCipher_Context_t * const pContext:*/ ctx, + /* mcuxCl_Buffer_t pOut: */ msg_enc + msg_enc_size, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_finish) != token_fin) || (MCUXCLCIPHER_STATUS_OK != result_fin)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_Els_example.c new file mode 100644 index 000000000..ee34e6719 --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_Els_example.c @@ -0,0 +1,213 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLAES_BLOCK_SIZE] = { + 0xF8u, 0xD2u, 0x68u, 0x76u, + 0x81u, 0x6Fu, 0x0Fu, 0xBAu, + 0x86u, 0x2Bu, 0xD8u, 0xA3u, + 0x2Du, 0x04u, 0x67u, 0xC3u +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[3u * MCUXCLAES_BLOCK_SIZE] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, 0x6Eu, 0x47u, 0x2Bu, 0xE4u +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[3u * MCUXCLAES_BLOCK_SIZE] = { + 0x1Au, 0xC4u, 0x7Bu, 0x49u, 0x45u, 0x42u, 0xFBu, 0xAFu, + 0x65u, 0x98u, 0xDDu, 0x9Du, 0xE2u, 0xE2u, 0x2Au, 0x10u, + 0x26u, 0x84u, 0x4Au, 0xEAu, 0x31u, 0x4Fu, 0x73u, 0x9Cu, + 0x03u, 0x2Eu, 0xDEu, 0xB4u, 0x8Fu, 0x38u, 0x04u, 0xC1u, + 0x12u, 0x24u, 0xC9u, 0xA1u, 0xCCu, 0xD5u, 0x05u, 0x76u, + 0x27u, 0xB7u, 0x12u, 0x37u, 0xF8u, 0x8Cu, 0xE1u, 0x2Au +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Cbc_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CBC_Enc_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CBC_Dec_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_dec_size != sizeof(msg_plain)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the decryption, compare it against the plain message */ + if(!mcuxClCore_assertEqual(msg_dec, msg_plain, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_ZeroPadding_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_ZeroPadding_Els_example.c new file mode 100644 index 000000000..e422d60fb --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_ZeroPadding_Els_example.c @@ -0,0 +1,223 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLAES_BLOCK_SIZE] = { + 0xF8u, 0xD2u, 0x68u, 0x76u, + 0x81u, 0x6Fu, 0x0Fu, 0xBAu, + 0x86u, 0x2Bu, 0xD8u, 0xA3u, + 0x2Du, 0x04u, 0x67u, 0xC3u +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[] = { + 0x1Au, 0xC4u, 0x7Bu, 0x49u, 0x45u, 0x42u, 0xFBu, 0xAFu, + 0x65u, 0x98u, 0xDDu, 0x9Du, 0xE2u, 0xE2u, 0x2Au, 0x10u, + 0x26u, 0x84u, 0x4Au, 0xEAu, 0x31u, 0x4Fu, 0x73u, 0x9Cu, + 0x03u, 0x2Eu, 0xDEu, 0xB4u, 0x8Fu, 0x38u, 0x04u, 0xC1u, + 0x6Eu, 0x79u, 0x66u, 0xF5u, 0x78u, 0x71u, 0xA7u, 0x13u, + 0x94u, 0x9Cu, 0x35u, 0xEBu, 0xFDu, 0x6Du, 0xA6u, 0x18u +}; + +/** Expected plaintext output of the AES decryption. */ +static uint8_t const msg_dec_expected[] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Cbc_ZeroPadding_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CBC_Dec_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_dec_size != sizeof(msg_dec_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the decryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_dec, msg_dec_expected, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ctr_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ctr_Els_example.c new file mode 100644 index 000000000..ad8c1ff8a --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ctr_Els_example.c @@ -0,0 +1,207 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLAES_BLOCK_SIZE] = { + 0xF8u, 0xD2u, 0x68u, 0x76u, + 0x81u, 0x6Fu, 0x0Fu, 0xBAu, + 0x86u, 0x2Bu, 0xD8u, 0xA3u, + 0x2Du, 0x04u, 0x67u, 0xC3u +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[3u * MCUXCLAES_BLOCK_SIZE - 4u] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[3u * MCUXCLAES_BLOCK_SIZE - 4u] = { + 0xB9u, 0x72u, 0x31u, 0xAFu, 0x93u, 0x5Fu, 0xCCu, 0xEFu, + 0x86u, 0x15u, 0x38u, 0xB2u, 0x20u, 0x4Eu, 0x9Du, 0x78u, + 0x85u, 0xE8u, 0x84u, 0xD8u, 0x14u, 0x00u, 0xC9u, 0x0Du, + 0x11u, 0x97u, 0x6Bu, 0x45u, 0xA8u, 0xB1u, 0x6Cu, 0x4Fu, + 0x2Au, 0xF0u, 0x64u, 0xCBu, 0x7Du, 0x08u, 0x23u, 0x2Cu, + 0xA8u, 0x30u, 0x65u, 0x8Fu +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Ctr_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[3u * MCUXCLAES_BLOCK_SIZE - 4u]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CTR, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[3u * MCUXCLAES_BLOCK_SIZE - 4u]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_CTR, + /* mcuxCl_InputBuffer_t pIv: */ aes128_iv, + /* uint32_t ivLength: */ sizeof(aes128_iv), + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Check the result of the decryption, compare it against the plain message */ + if(!mcuxClCore_assertEqual(msg_dec, msg_plain, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_Els_example.c new file mode 100644 index 000000000..38fea68f9 --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_Els_example.c @@ -0,0 +1,204 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[3u * MCUXCLAES_BLOCK_SIZE] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, 0x6Eu, 0x47u, 0x2Bu, 0xE4u +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[3u * MCUXCLAES_BLOCK_SIZE] = { + 0x57u, 0xF5u, 0xD5u, 0xBEu, 0x68u, 0xFFu, 0xF9u, 0x06u, + 0xE8u, 0x61u, 0xF4u, 0x30u, 0x99u, 0x20u, 0x3Au, 0xFFu, + 0x3Du, 0x56u, 0xDBu, 0x42u, 0x07u, 0xB3u, 0xBBu, 0xBDu, + 0x66u, 0xE4u, 0xAFu, 0x0Au, 0x1Eu, 0xDBu, 0xB0u, 0x93u, + 0xA6u, 0x9Bu, 0xC1u, 0x11u, 0x42u, 0x6Eu, 0xB1u, 0x6Du, + 0x06u, 0xFDu, 0xD7u, 0xE9u, 0x60u, 0x91u, 0x78u, 0x84u + +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Ecb_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Enc_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Dec_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u, + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_dec_size != sizeof(msg_plain)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the decryption, compare it against the plain message */ + if(!mcuxClCore_assertEqual(msg_dec, msg_plain, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_PaddingPKCS7_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_PaddingPKCS7_Els_example.c new file mode 100644 index 000000000..eee2c5f0d --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_PaddingPKCS7_Els_example.c @@ -0,0 +1,216 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +static const uint8_t msg_plain[62] = { + 0x61u, 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, + 0x69u, 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, + 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, + 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, + 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, + 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x72u, + 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, 0x6Bu, + 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u +}; + +/* ECB encrypted data */ +static const uint8_t msg_enc_expected[64] = { + 0x82u, 0x4fu, 0x7au, 0xb3u, 0xdfu, 0x5eu, 0x73u, 0x42u, + 0x35u, 0xbbu, 0xcfu, 0xeau, 0xdau, 0x7eu, 0x74u, 0xc1u, + 0x7au, 0x08u, 0x34u, 0x2du, 0x49u, 0xacu, 0xadu, 0x72u, + 0x0eu, 0xb3u, 0x23u, 0xb6u, 0x49u, 0x42u, 0x01u, 0xf2u, + 0x06u, 0x87u, 0x58u, 0xcfu, 0x41u, 0xb0u, 0xd6u, 0x63u, + 0x66u, 0x50u, 0x1bu, 0xe8u, 0x05u, 0x66u, 0xa8u, 0xfbu, + 0xf4u, 0x8fu, 0x4du, 0xa2u, 0x73u, 0x10u, 0x7eu, 0xd7u, + 0xfau, 0xf5u, 0x52u, 0x15u, 0x53u, 0x93u, 0x54u, 0x40u +}; + +static const uint8_t msg_dec_expected[64] = { + 0x61u, 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, + 0x69u, 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, + 0x62u, 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, + 0x6Au, 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, + 0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, + 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x72u, + 0x64u, 0x65u, 0x66u, 0x67u, 0x68u, 0x69u, 0x6Au, 0x6Bu, + 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x02u, 0x02u +}; + +static const uint8_t aes128_key[16] = { + 0x6Bu, 0x6Cu, 0x6Du, 0x6Eu, 0x6Fu, 0x70u, 0x71u, 0x72u, + 0x73u, 0x74u, 0x75u, 0x76u, 0x77u, 0x78u, 0x79u, 0x7Au, +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Ecb_PaddingPKCS7_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[4]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[sizeof(msg_enc_expected)]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[sizeof(msg_dec_expected)]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Dec_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u, + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_dec_size != sizeof(msg_dec_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the decryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_dec, msg_dec_expected, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_ZeroPadding_Els_example.c b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_ZeroPadding_Els_example.c new file mode 100644 index 000000000..10ab61ca7 --- /dev/null +++ b/components/els_pkc/examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_ZeroPadding_Els_example.c @@ -0,0 +1,216 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include +#include +#include // Interface to the entire mcuxClEls component +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClKey component +#include +#include // Code flow protection +#include // memory segment definitions +#include // Interface to AES-related definitions and types +#include // Interface to the entire mcuxClCipher component +#include // Interface to the entire mcuxClCipherModes component +#include + +/** Key for the AES encryption. */ +static uint8_t aes128_key[MCUXCLAES_BLOCK_SIZE] = { + 0x2Bu, 0x7Eu, 0x15u, 0x16u, + 0x28u, 0xAEu, 0xD2u, 0xA6u, + 0xABu, 0xF7u, 0x15u, 0x88u, + 0x09u, 0xCFu, 0x4Fu, 0x3Cu +}; + +/** Plaintext input for the AES encryption. */ +static uint8_t const msg_plain[] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, +}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const msg_enc_expected[] = { + 0x57u, 0xF5u, 0xD5u, 0xBEu, 0x68u, 0xFFu, 0xF9u, 0x06u, + 0xE8u, 0x61u, 0xF4u, 0x30u, 0x99u, 0x20u, 0x3Au, 0xFFu, + 0x3Du, 0x56u, 0xDBu, 0x42u, 0x07u, 0xB3u, 0xBBu, 0xBDu, + 0x66u, 0xE4u, 0xAFu, 0x0Au, 0x1Eu, 0xDBu, 0xB0u, 0x93u, + 0x01u, 0x5Au, 0x16u, 0x20u, 0x8Du, 0x40u, 0x75u, 0x25u, + 0x81u, 0xB6u, 0xADu, 0xA8u, 0xFBu, 0xBAu, 0xF2u, 0x6Eu +}; + +/** Expected plaintext output of the AES decryption. */ +static uint8_t const msg_dec_expected[] = { + 0xC8u, 0xC6u, 0x6Au, 0xB4u, 0x25u, 0x81u, 0x91u, 0xFDu, + 0x2Eu, 0x5Cu, 0x24u, 0x1Eu, 0xA8u, 0xCBu, 0x73u, 0xF7u, + 0x74u, 0x24u, 0xEAu, 0xD8u, 0x77u, 0x59u, 0x75u, 0x73u, + 0x17u, 0xC3u, 0x4Eu, 0x6Bu, 0xD5u, 0x8Du, 0xF8u, 0xDFu, + 0xA2u, 0x3Fu, 0xCFu, 0x2Au, 0x16u, 0xBEu, 0x30u, 0x55u, + 0x6Fu, 0xA8u, 0xF8u, 0xC6u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClCipherModes_Oneshot_Ecb_ZeroPadding_Els_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* Initialize key */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Load key. */ + uint32_t dstData[8]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &key_properties, + dstData, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Encryption */ + /**************************************************************************/ + + uint8_t msg_enc[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_enc_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_enc, token_enc, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u, + /* mcuxCl_InputBuffer_t pIn: */ msg_plain, + /* uint32_t inLength: */ sizeof(msg_plain), + /* mcuxCl_Buffer_t pOut: */ msg_enc, + /* uint32_t * const pOutLength: */ &msg_enc_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_enc) || (MCUXCLCIPHER_STATUS_OK != result_enc)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_enc_size != sizeof(msg_enc_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the encryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_enc, msg_enc_expected, msg_enc_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Decryption */ + /**************************************************************************/ + + uint8_t msg_dec[3u * MCUXCLAES_BLOCK_SIZE]; + uint32_t msg_dec_size = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result_dec, token_dec, mcuxClCipher_crypt( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* mcuxClCipher_Mode_t mode: */ mcuxClCipher_Mode_AES_ECB_Dec_NoPadding, + /* mcuxCl_InputBuffer_t pIv: */ NULL, + /* uint32_t ivLength: */ 0u, + /* mcuxCl_InputBuffer_t pIn: */ msg_enc, + /* uint32_t inLength: */ msg_enc_size, + /* mcuxCl_Buffer_t pOut: */ msg_dec, + /* uint32_t * const pOutLength: */ &msg_dec_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipher_crypt) != token_dec) || (MCUXCLCIPHER_STATUS_OK != result_dec)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(msg_dec_size != sizeof(msg_dec_expected)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Check the result of the decryption, compare it against the reference */ + if(!mcuxClCore_assertEqual(msg_dec, msg_dec_expected, msg_dec_size)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_FAILURE; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519_example.c new file mode 100644 index 000000000..37cd7646f --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519_example.c @@ -0,0 +1,186 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Ed25519_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_EdDSA_Ed25519_example.c + * @brief Example for the mcuxClEcc component EdDsa related functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include // Code flow protection +#include + +#include + +static const uint8_t digest[] = { + 0xC4u, 0x93u, 0xCFu, 0x6Bu, 0xE5u, 0x11u, 0x35u, 0x22u, + 0x1Au, 0x3Fu, 0x5Cu, 0x7Bu, 0xCFu, 0xF4u, 0x6Du, 0xC6u, + 0x10u, 0x77u, 0x6Eu, 0x2Cu, 0x04u, 0xA3u, 0xB9u, 0x9Du, + 0x39u, 0x3Bu, 0x4Bu, 0xEEu, 0xD5u, 0xDDu, 0x88u, 0x86u, +}; + +#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE,\ + MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_INIT_WACPU_SIZE,\ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE, \ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE)))) +#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE, \ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE)) + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /* Initialize ELS, Enable the ELS */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + /* Allocate and initialize session with pkcWA on the beginning of PKC RAM */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + /* Initialize the RNG context and Initialize the PRNG */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg); + + /* Prepare buffers for generated data */ + uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc; + uint8_t pPrivKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData, + /* uint32_t keyDataLength */ sizeof(pPrivKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc; + uint8_t pPubKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData, + /* uint32_t keyDataLength */ sizeof(pPubKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Key pair generation for EdDSA on Ed25519 */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ &mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor, + /* mcuxClKey_Handle_t privKey */ privKey, + /* mcuxClKey_Handle_t pubKey */ pubKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Ed25519 signature generation */ + /**************************************************************************/ + + uint8_t signature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] = {0}; + uint32_t signatureSize = 0u; + + /* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor, + /* const uint8_t *pIn */ digest, + /* uint32_t inSize */ sizeof(digest), + /* uint8_t *pSignature */ signature, + /* uint32_t *const pSignatureSize */ &signatureSize)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token) + || (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize) + || (MCUXCLECC_STATUS_OK != sign_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Ed25519 signature verification */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor, + /* const uint8_t *pIn */ digest, + /* uint32_t inSize */ sizeof(digest), + /* const uint8_t *pSignature */ signature, + /* uint32_t signatureSize */ signatureSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Destroy Session and cleanup Session */ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Disable the ELS */ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ctx_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ctx_example.c new file mode 100644 index 000000000..2f0be7c3d --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ctx_example.c @@ -0,0 +1,262 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Ed25519ctx_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_EdDSA_Ed25519ctx_example.c + * @brief Example for the mcuxClEcc component EdDsa related functions + */ + + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS +#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLEXAMPLE_MAX(\ + MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE,\ + MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE),\ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE) + +#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLEXAMPLE_MAX(\ + MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE,\ + MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE),\ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE) + +#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize) \ + (((bytesize) + sizeof(uint32_t) - 1U ) / (sizeof(uint32_t))) + +/* Input taken from "foo" from Section 7.2 of IRTF rfc 8032 */ +static const uint8_t pMessage[] __attribute__ ((aligned (4))) = +{ + 0xf7u, 0x26u, 0x93u, 0x6du, 0x19u, 0xc8u, 0x00u, 0x49u, + 0x4eu, 0x3fu, 0xdau, 0xffu, 0x20u, 0xb2u, 0x76u, 0xa8u, +}; + +/* Context taken from "foo" from Section 7.2 of IRTF rfc 8032 */ +static const uint8_t pContext[] __attribute__ ((aligned (4))) = +{ + 0x66u, 0x6fu, 0x6fu +}; + +/* Signature taken from "foo" from Section 7.2 of IRTF rfc 8032 */ +static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) = +{ + 0x55u, 0xa4u, 0xccu, 0x2fu, 0x70u, 0xa5u, 0x4eu, 0x04u, + 0x28u, 0x8cu, 0x5fu, 0x4cu, 0xd1u, 0xe4u, 0x5au, 0x7bu, + 0xb5u, 0x20u, 0xb3u, 0x62u, 0x92u, 0x91u, 0x18u, 0x76u, + 0xcau, 0xdau, 0x73u, 0x23u, 0x19u, 0x8du, 0xd8u, 0x7au, + 0x8bu, 0x36u, 0x95u, 0x0bu, 0x95u, 0x13u, 0x00u, 0x22u, + 0x90u, 0x7au, 0x7fu, 0xb7u, 0xc4u, 0xe9u, 0xb2u, 0xd5u, + 0xf6u, 0xccu, 0xa6u, 0x85u, 0xa5u, 0x87u, 0xb4u, 0xb2u, + 0x1fu, 0x4bu, 0x88u, 0x8eu, 0x4eu, 0x7eu, 0xdbu, 0x0du +}; + +/* Private key taken from "foo" from Section 7.2 of IRTF rfc 8032 */ +static const uint8_t pPrivateKey[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__ ((aligned (4))) = +{ + 0x03u, 0x05u, 0x33u, 0x4eu, 0x38u, 0x1au, 0xf7u, 0x8fu, + 0x14u, 0x1cu, 0xb6u, 0x66u, 0xf6u, 0x19u, 0x9fu, 0x57u, + 0xbcu, 0x34u, 0x95u, 0x33u, 0x5au, 0x25u, 0x6au, 0x95u, + 0xbdu, 0x2au, 0x55u, 0xbfu, 0x54u, 0x66u, 0x63u, 0xf6u +}; + + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519ctx_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /* Initialize ELS, Enable the ELS */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + /* Allocate and initialize session with pkcWA on the beginning of PKC RAM */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + /* Initialize the RNG context and Initialize the PRNG */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg); + + /* Allocate space for and initialize private key handle for an Ed25519 private key */ + uint32_t privKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)]; + mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc; + uint32_t pPrivKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA)]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv, + /* mcuxCl_InputBuffer_t pKeyData */ (mcuxCl_InputBuffer_t) pPrivKeyData, + /* uint32_t keyDataLength */ sizeof(pPrivKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize public key handle for an Ed25519 public key */ + uint32_t pubKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)]; + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc; + uint32_t pPubKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY)]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData, + /* uint32_t keyDataLength */ sizeof(pPubKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */ + uint32_t privKeyInputDescriptor[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE)]; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor, + /* const uint8_t *pPrivKey */ pPrivateKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Key pair generation for EdDSA on Ed25519ctx */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor, + /* mcuxClKey_Handle_t privKey */ privKey, + /* mcuxClKey_Handle_t pubKey */ pubKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Generate the mode and protocol descriptor */ + /**************************************************************************/ + + /* Allocate space for the hash prefix and a protocol descriptor for Ed25519ctx. */ + uint32_t protocolDescBytes[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(sizeof(pContext)))]; + mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDesc = (mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *) protocolDescBytes; + + /* Generate Ed25519ctx protocol descriptor */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genProtocolDescr_result, protocolDescr_token, mcuxClEcc_EdDSA_GenerateProtocolDescriptor( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams */ &mcuxClEcc_EdDSA_DomainParams_Ed25519, + /* mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor */ pProtocolDesc, + /* uint32_t phflag */ MCUXCLECC_EDDSA_PHFLAG_ZERO, + /* mcuxCl_InputBuffer_t pContext */ (mcuxCl_InputBuffer_t) pContext, + /* uint32_t contextLen */ sizeof(pContext))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) != protocolDescr_token) + || (MCUXCLECC_STATUS_OK != genProtocolDescr_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Ed25519ctx signature generation */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */ + uint32_t signature[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE)] = {0u}; + uint32_t signatureSize = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ pProtocolDesc, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* uint8_t *pSignature */ (uint8_t*)signature, + /* uint32_t *const pSignatureSize */ &signatureSize)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token) + || (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize) + || (MCUXCLECC_STATUS_OK != sign_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /******************************************/ + /* Signature verification */ + /******************************************/ + + /* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ pProtocolDesc, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* const uint8_t *pSignature */ (const uint8_t*) signature, + /* uint32_t signatureSize */ signatureSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Verify the signature with the reference signature. */ + if(!mcuxClCore_assertEqual((const uint8_t*)signature, pRefSignature, sizeof(pRefSignature))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /******************************************/ + /* Clean up */ + /******************************************/ + + /* Destroy Session and cleanup Session */ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Disable the ELS */ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ph_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ph_example.c new file mode 100644 index 000000000..630737afe --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ph_example.c @@ -0,0 +1,270 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ +/* Security Classification: Company Confidential */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Ed25519ph_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_EdDSA_Ed25519ph_example.c + * @brief Example for the mcuxClEcc component EdDsa related functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS +#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLRANDOMMODES_INIT_WACPU_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE, \ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE)))) +#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \ + MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE, \ + MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE)) + +#define CPUALIGN_FROM_BYTES_TO_WORDSIZE(bytesize) \ + (((bytesize) + sizeof(uint32_t) - 1U) / (sizeof(uint32_t))) + +/* Input taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */ +static const uint8_t pMessage[] __attribute__((aligned(4))) = +{ + 0x61u, 0x62u, 0x63u +}; + +/* Signature taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */ +static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__((aligned(4))) = +{ + 0x98u, 0xa7u, 0x02u, 0x22u, 0xf0u, 0xb8u, 0x12u, 0x1au, + 0xa9u, 0xd3u, 0x0fu, 0x81u, 0x3du, 0x68u, 0x3fu, 0x80u, + 0x9eu, 0x46u, 0x2bu, 0x46u, 0x9cu, 0x7fu, 0xf8u, 0x76u, + 0x39u, 0x49u, 0x9bu, 0xb9u, 0x4eu, 0x6du, 0xaeu, 0x41u, + 0x31u, 0xf8u, 0x50u, 0x42u, 0x46u, 0x3cu, 0x2au, 0x35u, + 0x5au, 0x20u, 0x03u, 0xd0u, 0x62u, 0xadu, 0xf5u, 0xaau, + 0xa1u, 0x0bu, 0x8cu, 0x61u, 0xe6u, 0x36u, 0x06u, 0x2au, + 0xaau, 0xd1u, 0x1cu, 0x2au, 0x26u, 0x08u, 0x34u, 0x06u +}; + +/* Private key taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */ +static const uint8_t pPrivateKey[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__((aligned(4))) = +{ + 0x83u, 0x3fu, 0xe6u, 0x24u, 0x09u, 0x23u, 0x7bu, 0x9du, + 0x62u, 0xecu, 0x77u, 0x58u, 0x75u, 0x20u, 0x91u, 0x1eu, + 0x9au, 0x75u, 0x9cu, 0xecu, 0x1du, 0x19u, 0x75u, 0x5bu, + 0x7du, 0xa9u, 0x01u, 0xb9u, 0x6du, 0xcau, 0x3du, 0x42u +}; + +/* Public key taken from "TEST abc" from Section 7.3 of IRTF rfc 8032 */ +static const uint8_t pPublicKey[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY] __attribute__((aligned(4))) = +{ + 0xecu, 0x17u, 0x2bu, 0x93u, 0xadu, 0x5eu, 0x56u, 0x3bu, + 0xf4u, 0x93u, 0x2cu, 0x70u, 0xe1u, 0x24u, 0x50u, 0x34u, + 0xc3u, 0x54u, 0x67u, 0xefu, 0x2eu, 0xfdu, 0x4du, 0x64u, + 0xebu, 0xf8u, 0x19u, 0x68u, 0x34u, 0x67u, 0xe2u, 0xbfu +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_Ed25519ph_example) +{ + /******************************************/ + /* Set up the environment */ + /******************************************/ + + /* Initialize ELS, Enable the ELS */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + (void) pPublicKey; + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + /* Allocate and initialize session with pkcWA on the beginning of PKC RAM */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + /* Initialize the RNG context and Initialize the PRNG */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg); + + /******************************************/ + /* Initialize the private and public keys */ + /******************************************/ + + /* Allocate space for and initialize private key handle for an Ed25519 private key */ + uint32_t privKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)]; + mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t)&privKeyDesc; + uint32_t pPrivateKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA)]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t)pPrivateKeyData, + /* uint32_t keyDataLength */ sizeof(pPrivateKeyData))); + + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize public key handle for an Ed25519 public key */ + uint32_t pubKeyDesc[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLKEY_DESCRIPTOR_SIZE)]; + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t)&pubKeyDesc; + uint32_t pPublicKeyData[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY)]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t)pPublicKeyData, + /* uint32_t keyDataLength */ sizeof(pPublicKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */ + uint32_t privKeyInputDescriptor[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE)]; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *)&privKeyInputDescriptor, + /* const uint8_t *pPrivKey */ pPrivateKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Key pair generation for EdDSA on Ed25519ph */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor, + /* mcuxClKey_Handle_t privKey */ privKey, + /* mcuxClKey_Handle_t pubKey */ pubKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /******************************************/ + /* Generate the protocol descriptor */ + /******************************************/ + + /* Allocate space for the hash prefix and a protocol descriptor for Ed25519ph. */ + uint32_t protocolDescBytes[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(0u))]; + mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDesc = (mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *) protocolDescBytes; + + /* Generate Ed25519ph protocol descriptor */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genProtocolDescr_result, protocolDescr_token, mcuxClEcc_EdDSA_GenerateProtocolDescriptor( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams */ &mcuxClEcc_EdDSA_DomainParams_Ed25519, + /* mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor */ pProtocolDesc, + /* uint32_t phflag */ MCUXCLECC_EDDSA_PHFLAG_ONE, + /* mcuxCl_InputBuffer_t pContext */ NULL, + /* uint32_t contextLen */ 0u)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) != protocolDescr_token) + || (MCUXCLECC_STATUS_OK != genProtocolDescr_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Ed25519ph signature generation */ + /**************************************************************************/ + + uint32_t signature[CPUALIGN_FROM_BYTES_TO_WORDSIZE(MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE)] = {0u}; + uint32_t signatureSize = 0u; + + /* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ pProtocolDesc, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* uint8_t *pSignature */ (uint8_t*)signature, + /* uint32_t *const pSignatureSize */ &signatureSize)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token) + || (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize) + || (MCUXCLECC_STATUS_OK != sign_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Ed25519ph signature verification */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ pProtocolDesc, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* const uint8_t *pSignature */ (const uint8_t*)signature, + /* uint32_t signatureSize */ signatureSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Verify the signature with the reference signature. */ + if(!mcuxClCore_assertEqual((const uint8_t*)signature, pRefSignature, sizeof(pRefSignature))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /******************************************/ + /* Clean up */ + /******************************************/ + + /* Destroy Session and cleanup Session */ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Disable the ELS */ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c new file mode 100644 index 000000000..c6acb9b86 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c @@ -0,0 +1,238 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c + * @brief Example for the mcuxClEcc component EdDsa signature generation using the test vectors + * from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include // Code flow protection + +#include + +#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS +#define MAX_CPUWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE, \ + MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE) +#define MAX_PKCWA_SIZE MCUXCLEXAMPLE_MAX(MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE, \ + MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE) + +/* Private key input taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pPrivKeyInput[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY] __attribute__ ((aligned (4))) = +{ + 0x83u, 0x3fu, 0xe6u, 0x24u, 0x09u, 0x23u, 0x7bu, 0x9du, + 0x62u, 0xecu, 0x77u, 0x58u, 0x75u, 0x20u, 0x91u, 0x1eu, + 0x9au, 0x75u, 0x9cu, 0xecu, 0x1du, 0x19u, 0x75u, 0x5bu, + 0x7du, 0xa9u, 0x01u, 0xb9u, 0x6du, 0xcau, 0x3du, 0x42u +}; + +/* Reference signature taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pRefSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) = +{ + 0xDCu, 0x2Au, 0x44u, 0x59u, 0xE7u, 0x36u, 0x96u, 0x33u, + 0xA5u, 0x2Bu, 0x1Bu, 0xF2u, 0x77u, 0x83u, 0x9Au, 0x00u, + 0x20u, 0x10u, 0x09u, 0xA3u, 0xEFu, 0xBFu, 0x3Eu, 0xCBu, + 0x69u, 0xBEu, 0xA2u, 0x18u, 0x6Cu, 0x26u, 0xB5u, 0x89u, + 0x09u, 0x35u, 0x1Fu, 0xC9u, 0xACu, 0x90u, 0xB3u, 0xECu, + 0xFDu, 0xFBu, 0xC7u, 0xC6u, 0x64u, 0x31u, 0xE0u, 0x30u, + 0x3Du, 0xCAu, 0x17u, 0x9Cu, 0x13u, 0x8Au, 0xC1u, 0x7Au, + 0xD9u, 0xBEu, 0xF1u, 0x17u, 0x73u, 0x31u, 0xA7u, 0x04u +}; + +/* Input message taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pMessage[] __attribute__ ((aligned (4))) = +{ + 0xDDu, 0xAFu, 0x35u, 0xA1u, 0x93u, 0x61u, 0x7Au, 0xBAu, + 0xCCu, 0x41u, 0x73u, 0x49u, 0xAEu, 0x20u, 0x41u, 0x31u, + 0x12u, 0xE6u, 0xFAu, 0x4Eu, 0x89u, 0xA9u, 0x7Eu, 0xA2u, + 0x0Au, 0x9Eu, 0xEEu, 0xE6u, 0x4Bu, 0x55u, 0xD3u, 0x9Au, + 0x21u, 0x92u, 0x99u, 0x2Au, 0x27u, 0x4Fu, 0xC1u, 0xA8u, + 0x36u, 0xBAu, 0x3Cu, 0x23u, 0xA3u, 0xFEu, 0xEBu, 0xBDu, + 0x45u, 0x4Du, 0x44u, 0x23u, 0x64u, 0x3Cu, 0xE8u, 0x0Eu, + 0x2Au, 0x9Au, 0xC9u, 0x4Fu, 0xA5u, 0x4Cu, 0xA4u, 0x9Fu +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example) +{ + /******************************************/ + /* Set up the environment */ + /******************************************/ + + /* Initialize ELS, Enable the ELS */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + + /* Allocate and initialize PKC workarea */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + + /* Initialize the RNG context and Initialize the PRNG */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg); + + /******************************************/ + /* Initialize the private and public keys */ + /******************************************/ + + /* Allocate space for and initialize private key handle for an Ed25519 private key */ + uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc; + uint8_t pPrivKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(privkeyinit_result, privkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Priv, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData, + /* uint32_t keyDataLength */ sizeof(pPrivKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != privkeyinit_token) || (MCUXCLKEY_STATUS_OK != privkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Allocate space for and initialize public key handle for an Ed25519 public key */ + uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc; + uint8_t pPubKeyData[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(pubkeyinit_result, pubkeyinit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData, + /* uint32_t keyDataLength */ sizeof(pPubKeyData))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != pubkeyinit_token) || (MCUXCLKEY_STATUS_OK != pubkeyinit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize EdDSA key pair generation descriptor for private key input */ + uint8_t privKeyInputDescriptor[MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE]; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initmode_result, initmode_token, mcuxClEcc_EdDSA_InitPrivKeyInputMode( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor, + /* const uint8_t *pPrivKey */ pPrivKeyInput)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_InitPrivKeyInputMode) != initmode_token) || (MCUXCLECC_STATUS_OK != initmode_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Key pair generation for EdDSA on Ed25519 */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateKeyPair to derive the public key from the private one. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keygen_result, keygen_token, mcuxClEcc_EdDSA_GenerateKeyPair( + /* mcuxClSession_Handle_t pSession */ &session, + /* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ (mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *) &privKeyInputDescriptor, + /* mcuxClKey_Handle_t privKey */ privKey, + /* mcuxClKey_Handle_t pubKey */ pubKey)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair) != keygen_token) || (MCUXCLECC_STATUS_OK != keygen_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Ed25519 signature generation */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_GenerateSignature to generate the signature. */ + uint8_t signatureBuffer[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] = {0}; + uint32_t signatureSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClEcc_EdDSA_GenerateSignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ privKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* uint8_t *pSignature */ signatureBuffer, + /* uint32_t *const pSignatureSize */ &signatureSize)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature) != sign_token) + || (MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE != signatureSize) + || (MCUXCLECC_STATUS_OK != sign_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Ed25519 signature verification */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t key */ pubKey, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t * */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor, + /* const uint8_t *pIn */ pMessage, + /* uint32_t inSize */ sizeof(pMessage), + /* const uint8_t *pSignature */ (const uint8_t*)signatureBuffer, + /* uint32_t signatureSize */ signatureSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Compare the generated signature to the reference. */ + mcuxClCore_assertEqual(signatureBuffer, pRefSignature, MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE); + + /******************************************/ + /* Clean up */ + /******************************************/ + + /* Destroy Session and cleanup Session */ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Disable the ELS */ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c new file mode 100644 index 000000000..791310415 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c @@ -0,0 +1,147 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c + * @brief Example for the mcuxClEcc component EdDsa signature verification using the test vectors + * from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 + */ + +#include +#include +#include +#include +#include +#include +#include // Code flow protection + +#include + +#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS +#define MAX_CPUWA_SIZE MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE +#define MAX_PKCWA_SIZE MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE + +/* Input taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pIn[] __attribute__ ((aligned (4))) = +{ + 0xddu, 0xafu, 0x35u, 0xa1u, 0x93u, 0x61u, 0x7au, 0xbau, + 0xccu, 0x41u, 0x73u, 0x49u, 0xaeu, 0x20u, 0x41u, 0x31u, + 0x12u, 0xe6u, 0xfau, 0x4eu, 0x89u, 0xa9u, 0x7eu, 0xa2u, + 0x0au, 0x9eu, 0xeeu, 0xe6u, 0x4bu, 0x55u, 0xd3u, 0x9au, + 0x21u, 0x92u, 0x99u, 0x2au, 0x27u, 0x4fu, 0xc1u, 0xa8u, + 0x36u, 0xbau, 0x3cu, 0x23u, 0xa3u, 0xfeu, 0xebu, 0xbdu, + 0x45u, 0x4du, 0x44u, 0x23u, 0x64u, 0x3cu, 0xe8u, 0x0eu, + 0x2au, 0x9au, 0xc9u, 0x4fu, 0xa5u, 0x4cu, 0xa4u, 0x9fu +}; + +/* Signature taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pSignature[MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE] __attribute__ ((aligned (4))) = +{ + 0xdcu, 0x2au, 0x44u, 0x59u, 0xe7u, 0x36u, 0x96u, 0x33u, + 0xa5u, 0x2bu, 0x1bu, 0xf2u, 0x77u, 0x83u, 0x9au, 0x00u, + 0x20u, 0x10u, 0x09u, 0xa3u, 0xefu, 0xbfu, 0x3eu, 0xcbu, + 0x69u, 0xbeu, 0xa2u, 0x18u, 0x6cu, 0x26u, 0xb5u, 0x89u, + 0x09u, 0x35u, 0x1fu, 0xc9u, 0xacu, 0x90u, 0xb3u, 0xecu, + 0xfdu, 0xfbu, 0xc7u, 0xc6u, 0x64u, 0x31u, 0xe0u, 0x30u, + 0x3du, 0xcau, 0x17u, 0x9cu, 0x13u, 0x8au, 0xc1u, 0x7au, + 0xd9u, 0xbeu, 0xf1u, 0x17u, 0x73u, 0x31u, 0xa7u, 0x04u +}; + +/* Public key taken from "TEST SHA(abc)" from Section 7.1 of IRTF rfc 8032 */ +static const uint8_t pPublicKey[MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY] __attribute__ ((aligned (4))) = +{ + 0xecu, 0x17u, 0x2bu, 0x93u, 0xadu, 0x5eu, 0x56u, 0x3bu, + 0xf4u, 0x93u, 0x2cu, 0x70u, 0xe1u, 0x24u, 0x50u, 0x34u, + 0xc3u, 0x54u, 0x67u, 0xefu, 0x2eu, 0xfdu, 0x4du, 0x64u, + 0xebu, 0xf8u, 0x19u, 0x68u, 0x34u, 0x67u, 0xe2u, 0xbfu +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_EdDSA_VerifySignature_Ed25519_example) +{ + /******************************************/ + /* Set up the environment */ + /******************************************/ + + /* Initialize ELS, Enable the ELS */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + + /* Allocate and initialize PKC workarea */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + /******************************************/ + /* Initialize the public key */ + /******************************************/ + + /* Initialize public key */ + uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t pubKeyHandler = (mcuxClKey_Handle_t) &pubKeyDesc; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keyInit_status, keyInit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ &session, + /* mcuxClKey_Handle_t key */ pubKeyHandler, + /* mcuxClKey_Type_t type */ mcuxClKey_Type_EdDSA_Ed25519_Pub, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPublicKey, + /* uint32_t keyDataLength */ sizeof(pPublicKey)) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != keyInit_token) || (MCUXCLKEY_STATUS_OK != keyInit_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Ed25519 signature verification */ + /**************************************************************************/ + + /* Call mcuxClEcc_EdDSA_VerifySignature to verify the signature */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClEcc_EdDSA_VerifySignature( + /* mcuxClSession_Handle_t pSession */ &session, + /* mcuxClKey_Handle_t pubKey */ pubKeyHandler, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t* */ &mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor, + /* const uint8_t *pIn */ pIn, + /* uint32_t inSize */ sizeof(pIn), + /* const uint8_t *pSignature */ pSignature, + /* uint32_t signatureSize */ sizeof(pSignature) + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature) != verify_token) || (MCUXCLECC_STATUS_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Destroy Session and cleanup Session */ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Disable the ELS */ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_Mont_Curve25519_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_Mont_Curve25519_example.c new file mode 100644 index 000000000..d51a22382 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_Mont_Curve25519_example.c @@ -0,0 +1,160 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Curve25519_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_Mont_Curve25519_example.c + * @brief Example for the mcuxClEcc component Curve25519 related functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include // Code flow protection + +#define RAM_START_ADDRESS MCUXCLPKC_RAM_START_ADDRESS +#define MAX_CPUWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE) +#define MAX_PKCWA_SIZE ((MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE >= MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE) ? MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE : MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE) + +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_Mont_Curve25519_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Setup one session to be used by all functions called */ + mcuxClSession_Descriptor_t session; + //Allocate and initialize session with pkcWA on the beginning of PKC RAM + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + /* Initialize the RNG and Initialize the PRNG */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(&session, 0u, mcuxClRandomModes_Mode_ELS_Drbg); + + /* Prepare input for Alice key generation */ + uint8_t alicePrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t alicePrivKeyHandler = (mcuxClKey_Handle_t) &alicePrivKeyDesc; + uint8_t alicePubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t alicePubKeyHandler = (mcuxClKey_Handle_t) &alicePubKeyDesc; + uint8_t alicePrivKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY]={0}; + uint8_t alicePubKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY]={0}; + uint32_t alicePrivKeySize = 0u; + uint32_t alicePubKeySize = 0u; + + /* Call Dh KeyGeneration for Alice keys generation and check FP and return code */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keygeneration_result, alice_keygeneration_token, + mcuxClEcc_Mont_DhKeyGeneration(&session, + mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair, + mcuxClKey_Protection_None, + alicePrivKeyHandler, + alicePrivKeyBuffer, &alicePrivKeySize, + alicePubKeyHandler, + alicePubKeyBuffer, &alicePubKeySize) + ); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != alice_keygeneration_token) || (MCUXCLECC_STATUS_OK != alice_keygeneration_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Prepare input for Bob key generation */ + uint8_t bobPrivKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t bobPrivKeyHandler = (mcuxClKey_Handle_t) &bobPrivKeyDesc; + uint8_t bobPubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t bobPubKeyHandler = (mcuxClKey_Handle_t) &bobPubKeyDesc; + uint8_t bobPrivKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY]={0}; + uint8_t bobPubKeyBuffer[MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY]={0}; + uint32_t bobPrivKeySize = 0u; + uint32_t bobPubKeySize = 0u; + + /* Call Dh KeyGeneration for Bob keys generation and check FP and return code */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keygeneration_result, bob_keygeneration_token, + mcuxClEcc_Mont_DhKeyGeneration(&session, + mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair, + mcuxClKey_Protection_None, + bobPrivKeyHandler, + bobPrivKeyBuffer, &bobPrivKeySize, + bobPubKeyHandler, + bobPubKeyBuffer, &bobPubKeySize) + ); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyGeneration) != bob_keygeneration_token) || (MCUXCLECC_STATUS_OK != bob_keygeneration_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + + /* Prepare input for Alice shared secret calculation */ + uint8_t aliceSharedSecret[MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET]; + uint32_t aliceSharedSecretSize; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(alice_keyagreement_result, alice_keyagreement_token, + mcuxClEcc_Mont_DhKeyAgreement(&session, + alicePrivKeyHandler, + bobPubKeyHandler, + aliceSharedSecret, + &aliceSharedSecretSize)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != alice_keyagreement_token) || (MCUXCLECC_STATUS_OK != alice_keyagreement_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Prepare input for Bob shared secret calculation */ + uint8_t bobSharedSecret[MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET]; + uint32_t bobSharedSecretSize; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(bob_keyagreement_result, bob_keyagreement_token, + mcuxClEcc_Mont_DhKeyAgreement(&session, + bobPrivKeyHandler, + alicePubKeyHandler, + bobSharedSecret, + &bobSharedSecretSize)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_DhKeyAgreement) != bob_keyagreement_token) || (MCUXCLECC_STATUS_OK != bob_keyagreement_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Alice's shared secret shall be equal to Bob's shared secret */ + for(size_t i = 0u; i < MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET; i++) + { + if(bobSharedSecret[i] != aliceSharedSecret[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c new file mode 100644 index 000000000..9adfd142b --- /dev/null +++ b/components/els_pkc/examples/mcuxClEcc/mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c @@ -0,0 +1,232 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c + * @brief Example for the mcuxClEcc component + * + * @example mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c + * @brief Example for the mcuxClEcc component + */ + +#include +#include +#include // Code flow protection +#include +#include +#include +#include +#include +#include // Code flow protection +#include +#include + +#define BN256_BYTE_LEN_P (32u) +#define BN256_BYTE_LEN_N (32u) + +static const uint8_t BN_P256_P[BN256_BYTE_LEN_P] = +{ + /* p = 0xFFFFFFFFFFFCF0CD46E5F25EEE71A49F0CDC65FB12980A82D3292DDBAED33013 */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFCu, 0xF0u, 0xCDu, + 0x46u, 0xE5u, 0xF2u, 0x5Eu, 0xEEu, 0x71u, 0xA4u, 0x9Fu, + 0x0Cu, 0xDCu, 0x65u, 0xFBu, 0x12u, 0x98u, 0x0Au, 0x82u, + 0xD3u, 0x29u, 0x2Du, 0xDBu, 0xAEu, 0xD3u, 0x30u, 0x13u}; + +static const uint8_t BN_P256_A[BN256_BYTE_LEN_P] = +{ + /* a = 0x0000000000000000000000000000000000000000000000000000000000000000 */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t BN_P256_B[BN256_BYTE_LEN_P] = +{ + /* b = 0x0000000000000000000000000000000000000000000000000000000000000003 */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u +}; + +static const uint8_t BN_P256_G[2u * BN256_BYTE_LEN_P] = +{ + /* G = (x,y) with + * x = 0x0000000000000000000000000000000000000000000000000000000000000001 */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + /* y = 0x0000000000000000000000000000000000000000000000000000000000000002 */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u +}; + +static const uint8_t BN_P256_N[BN256_BYTE_LEN_N] = +{ + /* n = 0xFFFFFFFFFFFCF0CD46E5F25EEE71A49E0CDC65FB1299921AF62D536CD10B500D */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFCu, 0xF0u, 0xCDu, + 0x46u, 0xE5u, 0xF2u, 0x5Eu, 0xEEu, 0x71u, 0xA4u, 0x9Eu, + 0x0Cu, 0xDCu, 0x65u, 0xFBu, 0x12u, 0x99u, 0x92u, 0x1Au, + 0xF6u, 0x2Du, 0x53u, 0x6Cu, 0xD1u, 0x0Bu, 0x50u, 0x0Du +}; + + +#define MAX_CPUWA_SIZE MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE +#define MAX_PKCWA_SIZE MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(BN256_BYTE_LEN_P, BN256_BYTE_LEN_N) + + +/** + * Performs an example key derivation using the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed + */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t pSession = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(pSession, MAX_CPUWA_SIZE, MAX_PKCWA_SIZE); + + + /**************************************************************************/ + /* Create structure providing custom domain parameters (BN_P256), which */ + /* will be converted to the optimized form accepted by mcuxClEcc APIs */ + /**************************************************************************/ + + mcuxClEcc_Weier_BasicDomainParams_t EccWeierBasicDomainParams; + EccWeierBasicDomainParams.pP = BN_P256_P; + EccWeierBasicDomainParams.pLen = BN256_BYTE_LEN_P; + EccWeierBasicDomainParams.pA = BN_P256_A; + EccWeierBasicDomainParams.pB = BN_P256_B; + EccWeierBasicDomainParams.pG = BN_P256_G; + EccWeierBasicDomainParams.pN = BN_P256_N; + EccWeierBasicDomainParams.nLen = BN256_BYTE_LEN_N; + + + /**************************************************************************/ + /* Convert custom domain parameters (BN_P256) and store it in */ + /* the optimized form accepted by mcuxClEcc APIs */ + /**************************************************************************/ + + uint32_t eccWeierDomainParams[MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(BN256_BYTE_LEN_P, BN256_BYTE_LEN_N) / (sizeof(uint32_t))]; + mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams = (mcuxClEcc_Weier_DomainParams_t *) eccWeierDomainParams; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genOptEccParams_status, genOptEccParams_token, + mcuxClEcc_WeierECC_GenerateDomainParams(pSession, + pEccWeierDomainParams, + &EccWeierBasicDomainParams, + MCUXCLECC_OPTION_GENERATEPRECPOINT_YES) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateDomainParams) != genOptEccParams_token) || (MCUXCLECC_STATUS_OK != genOptEccParams_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Generate custom private and public key types for BN_P256 */ + /**************************************************************************/ + + uint32_t customPrivKeyTypeDescriptor[MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS] = {0}; + mcuxClKey_CustomType_t customPrivKeyType = (mcuxClKey_CustomType_t) customPrivKeyTypeDescriptor; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genPrivKeyType_status, genPrivKeyType_token, mcuxClEcc_WeierECC_GenerateCustomKeyType( + /* mcuxClKey_CustomType_t customType */ customPrivKeyType, + /* mcuxClKey_AlgorithmId_t algoId */ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY, + /* mcuxClKey_Size_t size */ MCUXCLKEY_SIZE_256, + /* void *pCustomParams */ (void *) pEccWeierDomainParams) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateCustomKeyType) != genPrivKeyType_token) || (MCUXCLECC_STATUS_OK != genPrivKeyType_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + uint32_t customPubKeyTypeDescriptor[MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS] = {0}; + mcuxClKey_CustomType_t customPubKeyType = (mcuxClKey_CustomType_t) customPubKeyTypeDescriptor; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(genPubKeyType_status, genPubKeyType_token, mcuxClEcc_WeierECC_GenerateCustomKeyType( + /* mcuxClKey_CustomType_t customType */ customPubKeyType, + /* mcuxClKey_AlgorithmId_t algoId */ MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY, + /* mcuxClKey_Size_t size */ MCUXCLKEY_SIZE_512, + /* void *pCustomParams */ (void *) pEccWeierDomainParams) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_WeierECC_GenerateCustomKeyType) != genPubKeyType_token) || (MCUXCLECC_STATUS_OK != genPubKeyType_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize private key handle for an BN_P256 private key */ + uint8_t privKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t privKey = (mcuxClKey_Handle_t) &privKeyDesc; + uint8_t pPrivKeyData[MCUXCLKEY_SIZE_256]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ki_priv_status, ki_priv_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ pSession, + /* mcuxClKey_Handle_t key */ privKey, + /* mcuxClKey_Type_t type */ customPrivKeyType, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPrivKeyData, + /* uint32_t keyDataLength */ MCUXCLKEY_SIZE_256) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != ki_priv_token) || (MCUXCLKEY_STATUS_OK != ki_priv_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Allocate space for and initialize public key handle for an BN_P256 public key */ + uint8_t pubKeyDesc[MCUXCLKEY_DESCRIPTOR_SIZE]; + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) &pubKeyDesc; + uint8_t pPubKeyData[MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(ki_pub_status, ki_pub_token, mcuxClKey_init( + /* mcuxClSession_Handle_t session */ pSession, + /* mcuxClKey_Handle_t key */ pubKey, + /* mcuxClKey_Type_t type */ customPubKeyType, + /* mcuxCl_Buffer_t pKeyData */ (mcuxCl_Buffer_t) pPubKeyData, + /* uint32_t keyDataLength */ MCUXCLKEY_SIZE_512) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != ki_pub_token) || (MCUXCLKEY_STATUS_OK != ki_pub_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Clean session */ + /**************************************************************************/ + + if(!mcuxClExample_Session_Clean(pSession)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c new file mode 100644 index 000000000..2b8c0cc68 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c @@ -0,0 +1,107 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c + * @brief Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls + * + * @example mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c + * @brief Example AES-128 CBC encryption using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Plaintext input for the AES encryption. */ +static uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x6BU, 0xC1U, 0xBEU, 0xE2U, + 0x2EU, 0x40U, 0x9FU, 0x96U, + 0xE9U, 0x3DU, 0x7EU, 0x11U, + 0x73U, 0x93U, 0x17U, 0x2AU}; + +/** IV of the AES encryption. */ +static uint8_t aes128_iv[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0xF8U, 0xD2U, 0x68U, 0x76U, + 0x81U, 0x6FU, 0x0FU, 0xBAU, + 0x86U, 0x2BU, 0xD8U, 0xA3U, + 0x2DU, 0x04U, 0x67U, 0xC3U}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0xCAU, 0xEAU, 0x07U, 0x26U, + 0x62U, 0xE2U, 0x20U, 0x06U, + 0x2DU, 0x45U, 0x46U, 0x41U, + 0x5EU, 0xFFU, 0xFAU, 0xD2U}; + +/** Key for the AES encryption. */ +static uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128 / sizeof(uint32_t)] = {0x16157E2B, 0xA6D2AE28, 0x8815F7AB, 0x3C4FCF09}; + +/** Destination buffer to receive the ciphertext output of the AES encryption. */ +static uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]; + + +/** Performs AES-128 CBC encryption using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_CipherOption_t cipher_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Cipher_Async operation. + cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC; // Configure the AES block cipher mode of operation to be the CBC (Cipher Block Chaining) mode. + cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; // Configure that the mcuxClEls_Cipher_Async operation shall perform encryption. + cipher_options.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; // Configure that an external key should be used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( // Perform the encryption. + cipher_options, // Set the prepared configuration. + (mcuxClEls_KeyIndex_t) 0U, // This parameter (keyIdx) is ignored, since an external key is used. + (const uint8_t *) aes128_key, MCUXCLELS_CIPHER_KEY_SIZE_AES_128, // The AES key for the encryption (external key). + aes128_input, sizeof(aes128_input), // The plaintext to encrypt. Note that this plaintext's length is a multiple of the block length, so no padding is required. + aes128_iv, // The IV (Initialization Vector) used for the encryption. + aes128_output // Output buffer, which the operation will write the ciphertext to. + )); + // mcuxClEls_Cipher_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR;// Expect that no error occurred, meaning that the mcuxClEls_Cipher_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Cipher_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < sizeof(aes128_output); i++) + { + if (aes128_output[i] != aes128_expected_output[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR;// Expect that the resulting ciphertext matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c new file mode 100644 index 000000000..a7a0acb08 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c @@ -0,0 +1,102 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c + * @brief Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c + * @brief Example AES-128 ECB encryption using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Plaintext input for the AES encryption. */ +static uint8_t const aes128_input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x6BU, 0xC1U, 0xBEU, 0xE2U, + 0x2EU, 0x40U, 0x9FU, 0x96U, + 0xE9U, 0x3DU, 0x7EU, 0x11U, + 0x73U, 0x93U, 0x17U, 0x2AU}; + +/** Expected ciphertext output of the AES encryption. */ +static uint8_t const aes128_expected_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES] = {0x3AU, 0xD7U, 0x7BU, 0xB4U, + 0x0DU, 0x7AU, 0x36U, 0x60U, + 0xA8U, 0x9EU, 0xCAU, 0xF3U, + 0x24U, 0x66U, 0xEFU, 0x97U}; + +/** Key for the AES encryption. */ +static uint32_t const aes128_key[MCUXCLELS_CIPHER_KEY_SIZE_AES_128 / sizeof(uint32_t)] = {0x16157E2B, 0xA6D2AE28, 0x8815F7AB, 0x3C4FCF09}; + +/** Destination buffer to receive the ciphertext output of the AES encryption. */ +static uint8_t aes128_output[MCUXCLELS_CIPHER_BLOCK_SIZE_AES]; + + + +/** Performs AES-128 ECB encryption using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_CipherOption_t cipher_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Cipher_Async operation. + cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB; // Configure the AES block cipher mode of operation to be the ECB (Electronic Codebook) mode. + cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; // Configure that the mcuxClEls_Cipher_Async operation shall perform encryption. + cipher_options.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; // Configure that an external key should be used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( // Perform the encryption. + cipher_options, // Set the prepared configuration. + (mcuxClEls_KeyIndex_t) 0U, // This parameter (keyIdx) is ignored, since an external key is used. + (const uint8_t *) aes128_key, MCUXCLELS_CIPHER_KEY_SIZE_AES_128, // The AES key for the encryption (external key). + aes128_input, sizeof(aes128_input), // The plaintext to encrypt. Note that this plaintext's length is a multiple of the block length, so no padding is required. + NULL, // This parameter (pIV) is ignored, since the ECB mode is used. + aes128_output // Output buffer, which the operation will write the ciphertext to. + )); + // mcuxClEls_Cipher_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Cipher_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Cipher_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0U; i < sizeof(aes128_output); i++) + { + if (aes128_output[i] != aes128_expected_output[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting ciphertext matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Common_Get_Info_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Common_Get_Info_example.c new file mode 100644 index 000000000..5c93521cc --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Common_Get_Info_example.c @@ -0,0 +1,109 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Common_Get_Info_example.c + * @brief Example of version and configuration load functions. + * + * @example mcuxClEls_Common_Get_Info_example.c + * @brief Example of version and configuration load functions. + */ + +#include // Test the CLNS component-independent functionality +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Common_Get_Info_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + // Read the ELS hardware version. + mcuxClEls_HwVersion_t hw_version; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwVersion(&hw_version)); + // mcuxClEls_GetHwVersion is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwVersion) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Access and store hw_version struct elements + uint32_t revision = hw_version.bits.revision; // Extended revision version + uint32_t minor = hw_version.bits.minor; // Minor version + uint32_t major = hw_version.bits.major; // Major version + (void) revision; + (void) minor; + (void) major; +#if MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0 + uint32_t level = hw_version.bits.level; // Release level version + (void) level; +#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0 */ + uint32_t fw_revision = hw_version.bits.fw_revision; // Firmware Extended revision version + uint32_t fw_minor = hw_version.bits.fw_minor; // Firmware Minor version + uint32_t fw_major = hw_version.bits.fw_major; // Firmware Major version + (void) fw_revision; + (void) fw_minor; + (void) fw_major; +#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION == 0 */ + +#ifdef MCUXCL_FEATURE_ELS_HWCONFIG + // Read the ELS hardware configuration bitmap. + mcuxClEls_HwConfig_t config; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwConfig(&config)); + // mcuxClEls_GetHwConfig is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwConfig) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Access and store config struct elements + uint32_t ciphersup = config.bits.ciphersup; // cipher command not supported + uint32_t authciphersup = config.bits.authciphersup; // auth_cipher command not supported + uint32_t ecsignsup = config.bits.ecsignsup; // ecsign command not supported + uint32_t ecvfysup = config.bits.ecvfysup; // ecvfy command not supported + uint32_t eckxchsup = config.bits.eckxchsup; // dhkey_xch command is supported + uint32_t keygensup = config.bits.keygensup; // keygen command not supported + uint32_t keyinsup = config.bits.keyinsup; // keyin command not supported + uint32_t keyoutsup = config.bits.keyoutsup; // keyout command not supported + uint32_t kdeletesup = config.bits.kdeletesup; // kdelete command not supported + uint32_t ckdfsup = config.bits.ckdfsup; // ckdf command not supported + uint32_t hkdfsup = config.bits.hkdfsup; // hkdf command not supported + uint32_t tlsinitsup = config.bits.tlsinitsup; // tls_init command not supported + uint32_t hashsup = config.bits.hashsup; // hash command not supported + uint32_t hmacsup = config.bits.hmacsup; // hmac command not supported + uint32_t drbgreqsub = config.bits.drbgreqsub; // drbg_req command not supported + uint32_t dtrgncfgloadsup = config.bits.dtrgncfgloadsup; // dtrng_cfg_load command is not supported + uint32_t dtrngevalsup = config.bits.dtrngevalsup; // dtrng_eval command not supported + + char const* sw_version = mcuxCl_GetVersion(); // Read the CLNS version string that uniquely identifies this release of the CLNS. + // MCUXCL_VERSION_MAX_SIZE is the maximum size in bytes of the version string. + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } +#endif + return MCUXCLEXAMPLE_STATUS_OK; +} + diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Ecc_Keygen_Sign_Verify_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Ecc_Keygen_Sign_Verify_example.c new file mode 100644 index 000000000..ebf03c22d --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Ecc_Keygen_Sign_Verify_example.c @@ -0,0 +1,186 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Ecc_Keygen_Sign_Verify_example.c + * @brief Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Ecc_Keygen_Sign_Verify_example.c + * @brief Example of ECC for key generation, signing and verification using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include +#include + + +/** Pre-hashed data to be signed */ +static uint32_t const ecc_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 / sizeof(uint32_t)] = {0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888}; + +/** Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation. */ +static uint32_t ecc_public_key[MCUXCLELS_ECC_PUBLICKEY_SIZE / sizeof(uint32_t)]; + +/** Destination buffer to receive the signature of the mcuxClEls_EccSign_Async operation. */ +static uint32_t ecc_signature[MCUXCLELS_ECC_SIGNATURE_SIZE / sizeof(uint32_t)]; + + +/** Destination buffer to receive the signature part r of the VerifyOptions operation. */ +static uint32_t ecc_signature_r[MCUXCLELS_ECC_SIGNATURE_R_SIZE / sizeof(uint32_t)]; + + +/** Concatenation of the ECC signature and public key, needed for the mcuxClEls_EccVerify_Async operation. */ +static uint32_t ecc_signature_and_public_key[(MCUXCLELS_ECC_SIGNATURE_SIZE + MCUXCLELS_ECC_PUBLICKEY_SIZE) / sizeof(uint32_t)]; + + +/** + * Performs SHA2-256 hashing using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Ecc_Keygen_Sign_Verify_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Generate signing key */ + mcuxClEls_EccKeyGenOption_t KeyGenOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccKeyGen_Async operation. + KeyGenOptions.bits.kgsrc = MCUXCLELS_ECC_OUTPUTKEY_RANDOM; // Configure that a non-deterministic key is generated. + KeyGenOptions.bits.kgsign = MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE; // Configure that the generated public key is not signed + KeyGenOptions.bits.kgsign_rnd = MCUXCLELS_ECC_NO_RANDOM_DATA; // Configure that no external random data is provided + + mcuxClEls_KeyProp_t GenKeyProp = {0}; // Initialize a new configuration for the mcuxClEls_EccKeyGen_Async generated key properties. + GenKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access + GenKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: non-secure access + + mcuxClEls_KeyIndex_t keyIdx = 10u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation. + KeyGenOptions, // Set the prepared configuration. + (mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration. + keyIdx, // Keystore index at which the generated private key is stored. + GenKeyProp, // Set the generated key properties. + NULL, // No random data is provided + (uint8_t *) ecc_public_key // Output buffer, which the operation will write the public key to. + )); + // mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Sign message digest */ + mcuxClEls_EccSignOption_t SignOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccSign_Async operation. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccSign_Async(// Perform signature generation. + SignOptions, // Set the prepared configuration. + keyIdx, // Set index of private key in keystore. + (const uint8_t *) ecc_digest, NULL, (size_t) 0U, // Pre-hashed data to sign. Note that inputLength parameter is ignored since pre-hashed data has a fixed length. + (uint8_t *)ecc_signature // Output buffer, which the operation will write the signature to. + )); + // mcuxClEls_EccSign_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccSign_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccSign_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccSign_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Verify signature */ + /* Concatenate signature and public key to prepare input for EccVerify_Async */ + for(size_t i = 0u; i < MCUXCLELS_ECC_SIGNATURE_SIZE; i++) { + ((uint8_t *)ecc_signature_and_public_key)[i] = ((uint8_t *)ecc_signature)[i]; + } + for(size_t i = 0u; i < MCUXCLELS_ECC_PUBLICKEY_SIZE; i++) { + ((uint8_t *)ecc_signature_and_public_key)[MCUXCLELS_ECC_SIGNATURE_SIZE + i] = *((uint8_t *) ecc_public_key + i); + } + + mcuxClEls_EccVerifyOption_t VerifyOptions = {0}; // Initialize a new configuration for the planned mcuxClEls_EccVerify_Async operation. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccVerify_Async(// Perform signature verification. + VerifyOptions, // Set the prepared configuration. + (const uint8_t *) ecc_digest, NULL, (size_t) 0U, // Pre-hashed data to verify. Note that inputLength parameter is ignored since pre-hashed data has a fixed length. + (const uint8_t *)ecc_signature_and_public_key, // Concatenation of signature of the pre-hashed data and public key used + (uint8_t *)ecc_signature_r // Output buffer, which the operation will write the signature part r to, to allow external comparison of between given and recalculated r. + )); + // mcuxClEls_EccVerify_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccVerify_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccVerify_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccVerify_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + mcuxClEls_HwState_t state; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_GetHwState(&state)); + // mcuxClEls_GetHwState is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if (MCUXCLELS_STATUS_ECDSAVFY_OK != state.bits.ecdsavfy) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that mcuxClEls_EccVerify_Async operation successfully performed the signature verification. + } + + /** deleted keyIdx keySlot **/ + if(!mcuxClExample_Els_KeyDelete(keyIdx)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha224_One_Block_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha224_One_Block_example.c new file mode 100644 index 000000000..cc483b4ca --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha224_One_Block_example.c @@ -0,0 +1,110 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hash_Sha224_One_Block_example.c + * @brief Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Hash_Sha224_One_Block_example.c + * @brief Example of SHA2-224 hashing using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Data input for SHA2-224 hashing. */ +static uint8_t const sha224_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_224] = {0x61U, 0x62U, 0x63U, 0x80U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x18U}; + +/** Expected hash value. */ +static uint8_t sha224_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224] = {0x23U, 0x09U, 0x7dU, 0x22U, + 0x34U, 0x05U, 0xd8U, 0x22U, + 0x86U, 0x42U, 0xa4U, 0x77U, + 0xbdU, 0xa2U, 0x55U, 0xb3U, + 0x2aU, 0xadU, 0xbcU, 0xe4U, + 0xbdU, 0xa0U, 0xb3U, 0xf7U, + 0xe3U, 0x6cU, 0x9dU, 0xa7U}; + +/** Destination buffer to receive the hash output of the SHA2-224 hashing. */ +static uint8_t sha2_224_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_224]; // MCUXCLELS_HASH_STATE_SIZE_SHA_224 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state. + + +/** Performs SHA2-224 hashing using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha224_One_Block_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation. + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector). + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation. + hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_224; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-224 algorithm is used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing. + hash_options, // Set the prepared configuration. + sha224_padded_input, sizeof(sha224_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required + sha2_224_digest // Output buffer, which the operation will write the hash digest to. + )); + // mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0; i < sizeof(sha224_reference_digest); i++) + { + if (sha2_224_digest[i] != sha224_reference_digest[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha256_One_Block_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha256_One_Block_example.c new file mode 100644 index 000000000..ad9ada399 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha256_One_Block_example.c @@ -0,0 +1,112 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hash_Sha256_One_Block_example.c + * @brief Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Hash_Sha256_One_Block_example.c + * @brief Example of SHA2-256 hashing using the ELS (CLNS component mcuxClEls) + * */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Data input for SHA2-256 hashing. */ +static uint8_t const sha256_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_256] = {0x61U, 0x62U, 0x63U, 0x80U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x18U}; + +/** Expected hash value. */ +static uint8_t sha256_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256] = {0xBAU, 0x78U, 0x16U, 0xBFU, + 0x8FU, 0x01U, 0xCFU, 0xEAU, + 0x41U, 0x41U, 0x40U, 0xDEU, + 0x5DU, 0xAEU, 0x22U, 0x23U, + 0xB0U, 0x03U, 0x61U, 0xA3U, + 0x96U, 0x17U, 0x7AU, 0x9CU, + 0xB4U, 0x10U, 0xFFU, 0x61U, + 0xF2U, 0x00U, 0x15U, 0xADU}; + +/** Destination buffer to receive the hash output of the SHA2-256 hashing. */ +static uint8_t sha2_256_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_256]; // MCUXCLELS_HASH_STATE_SIZE_SHA_256 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state. + + + +/** Performs SHA2-256 hashing using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha256_One_Block_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation. + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector). + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation. + hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_256; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-256 algorithm is used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing. + hash_options, // Set the prepared configuration. + sha256_padded_input, sizeof(sha256_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required + sha2_256_digest // Output buffer, which the operation will write the hash digest to. + )); + // mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0; i < sizeof(sha256_reference_digest); i++) + { + if (sha2_256_digest[i] != sha256_reference_digest[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha384_One_Block_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha384_One_Block_example.c new file mode 100644 index 000000000..df7f48d68 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha384_One_Block_example.c @@ -0,0 +1,132 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hash_Sha384_One_Block_example.c + * @brief Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Hash_Sha384_One_Block_example.c + * @brief Example of SHA2-384 hashing using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Data input for SHA2-384 hashing. */ +static uint8_t const sha384_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_384] = {0x61U, 0x62U, 0x63U, 0x80U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x18U}; + +/** Expected hash value. */ +static uint8_t sha384_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384] = {0xcbU, 0x00U, 0x75U, 0x3fU, + 0x45U, 0xa3U, 0x5eU, 0x8bU, + 0xb5U, 0xa0U, 0x3dU, 0x69U, + 0x9aU, 0xc6U, 0x50U, 0x07U, + 0x27U, 0x2cU, 0x32U, 0xabU, + 0x0eU, 0xdeU, 0xd1U, 0x63U, + 0x1aU, 0x8bU, 0x60U, 0x5aU, + 0x43U, 0xffU, 0x5bU, 0xedU, + 0x80U, 0x86U, 0x07U, 0x2bU, + 0xa1U, 0xe7U, 0xccU, 0x23U, + 0x58U, 0xbaU, 0xecU, 0xa1U, + 0x34U, 0xc8U, 0x25U, 0xa7U}; + +/** Destination buffer to receive the hash output of the SHA2-384 hashing. */ +static uint8_t sha2_384_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_384]; // MCUXCLELS_HASH_STATE_SIZE_SHA_384 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state. + + + +/** Performs SHA2-384 hashing using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha384_One_Block_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation. + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector). + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation. + hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_384; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-384 algorithm is used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing. + hash_options, // Set the prepared configuration. + sha384_padded_input, sizeof(sha384_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required + sha2_384_digest // Output buffer, which the operation will write the hash digest to. + )); + // mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0; i < sizeof(sha384_reference_digest); i++) + { + if (sha2_384_digest[i] != sha384_reference_digest[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha512_One_Block_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha512_One_Block_example.c new file mode 100644 index 000000000..f95354ea3 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Hash_Sha512_One_Block_example.c @@ -0,0 +1,135 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hash_Sha512_One_Block_example.c + * @brief Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Hash_Sha512_One_Block_example.c + * @brief Example of SHA2-512 hashing using the ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include + +/** Data input for SHA2-512 hashing. */ +static uint8_t const sha512_padded_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_512] = {0x61U, 0x62U, 0x63U, 0x80U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00u, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x18U}; + +/** Expected hash value. */ +static uint8_t sha512_reference_digest[MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512] = {0xddU, 0xafU, 0x35U, 0xa1U, + 0x93U, 0x61U, 0x7aU, 0xbaU, + 0xccU, 0x41U, 0x73U, 0x49U, + 0xaeU, 0x20U, 0x41U, 0x31U, + 0x12U, 0xe6U, 0xfaU, 0x4eU, + 0x89U, 0xa9U, 0x7eU, 0xa2U, + 0x0aU, 0x9eU, 0xeeU, 0xe6U, + 0x4bU, 0x55U, 0xd3U, 0x9aU, + 0x21U, 0x92U, 0x99U, 0x2aU, + 0x27U, 0x4fU, 0xc1U, 0xa8U, + 0x36U, 0xbaU, 0x3cU, 0x23U, + 0xa3U, 0xfeU, 0xebU, 0xbdU, + 0x45U, 0x4dU, 0x44U, 0x23U, + 0x64U, 0x3cU, 0xe8U, 0x0eU, + 0x2aU, 0x9aU, 0xc9U, 0x4fU, + 0xa5U, 0x4cU, 0xa4U, 0x9fU}; + +/** Destination buffer to receive the hash output of the SHA2-512 hashing. */ +static uint8_t sha2_512_digest[MCUXCLELS_HASH_STATE_SIZE_SHA_512]; // MCUXCLELS_HASH_STATE_SIZE_SHA_512 has to be used as the mcuxClEls_Hash_Async do not perform the truncation of the hash state. + + +/** Performs SHA2-512 hashing using mcuxClEls functions. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Hash_Sha512_One_Block_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + mcuxClEls_HashOption_t hash_options = {0U}; // Initialize a new configuration for the planned mcuxClEls_Hash_Async operation. + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; // Configure that the mcuxClEls_Hash_Async operation shall initialized with the standard IV (Initialization Vector). + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; // Configure the mcuxClEls_Hash_Async operation so that the hash digest is moved into memory at the end of the operation. + hash_options.bits.hashmd = MCUXCLELS_HASH_MODE_SHA_512; // Configure the mcuxClEls_Hash_Async operation so that the Sha2-512 algorithm is used. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Hash_Async( // Perform the hashing. + hash_options, // Set the prepared configuration. + sha512_padded_input, sizeof(sha512_padded_input), // Set the data to be hashed. Note that this data's length is a multiple of the block length, so no padding is required + sha2_512_digest // Output buffer, which the operation will write the hash digest to. + )); + // mcuxClEls_Hash_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Hash_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Hash_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + for (size_t i = 0; i < sizeof(sha512_reference_digest); i++) + { + if (sha2_512_digest[i] != sha512_reference_digest[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that the resulting hash digest matches our expected output + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Rng_Prng_Get_Random_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Rng_Prng_Get_Random_example.c new file mode 100644 index 000000000..948623345 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Rng_Prng_Get_Random_example.c @@ -0,0 +1,75 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Rng_Prng_Get_Random_example.c + * @brief Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls) + * + * @example mcuxClEls_Rng_Prng_Get_Random_example.c + * @brief Example of getting a random number from PRNG of ELS (CLNS component mcuxClEls) + */ + +#include // Interface to the entire mcuxClEls component +#include +#include // Code flow protection +#include +#include +#include + +/** Uses random number from PRNG of ELS. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Rng_Prng_Get_Random_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + // PRNG needs to be initialized; this can be done by calling mcuxClEls_KeyDelete_Async (delete any key slot, can be empty) + /** deleted 18 keySlot **/ + if(!mcuxClExample_Els_KeyDelete(18)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + uint32_t dummy; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandomWord(&dummy)); + // mcuxClEls_Prng_GetRandomWord is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandomWord) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandomWord operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + uint32_t random[16]; // buffers of 16 CPU words to be filled with random numbers from PRNG. + + // fill the buffer with random numbers from PRNG. + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom((uint8_t*) random, sizeof(random))); + // mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClEls/mcuxClEls_Tls_Master_Key_Session_Keys_example.c b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Tls_Master_Key_Session_Keys_example.c new file mode 100644 index 000000000..1f60543a4 --- /dev/null +++ b/components/els_pkc/examples/mcuxClEls/mcuxClEls_Tls_Master_Key_Session_Keys_example.c @@ -0,0 +1,381 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Tls_Master_Key_Session_Keys_example.c + * @brief TLS key derivation example + * + * @example mcuxClEls_Tls_Master_Key_Session_Keys_example.c + * @brief TLS key derivation example + */ + +#include // Interface to the entire mcuxClEls component +#include +#include +#include // Code flow protection +#include +#include +#include + + +/** Destination buffer to receive the public key of the mcuxClEls_EccKeyGen_Async operation. */ +static uint32_t ecc_public_key_client[MCUXCLELS_ECC_PUBLICKEY_SIZE / sizeof(uint32_t)]; +static uint32_t ecc_public_key_server[MCUXCLELS_ECC_PUBLICKEY_SIZE / sizeof(uint32_t)]; + +static uint8_t derivation_data[MCUXCLELS_TLS_DERIVATIONDATA_SIZE]; +static uint8_t client_random[MCUXCLELS_TLS_RANDOM_SIZE]; +static uint8_t server_random[MCUXCLELS_TLS_RANDOM_SIZE]; + +static uint8_t master_key_string[] = "master secret"; +static uint8_t key_expansion_string[] = "key expansion"; + + +/** Performs key derivation for TLS protocol. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClEls_Tls_Master_Key_Session_Keys_example) +{ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Generate client key pair */ + mcuxClEls_EccKeyGenOption_t KeyGenOptions = {0}; + KeyGenOptions.bits.kgsrc = MCUXCLELS_ECC_OUTPUTKEY_RANDOM; // Configure that a non-deterministic key is generated. + KeyGenOptions.bits.kgtypedh = MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE; //Key will be used for Key Exchange + + mcuxClEls_KeyProp_t GenKeyProp = {0}; + GenKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access + GenKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access + + mcuxClEls_KeyIndex_t keyIdxPrivClient = 0u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation. + KeyGenOptions, // Set the prepared configuration. + (mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration. + keyIdxPrivClient, // Keystore index at which the generated private key is stored. + GenKeyProp, // Set the generated key properties. + NULL, + (uint8_t *)ecc_public_key_client // Output buffer, which the operation will write the public key to. + )); + // mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Generate server key pair */ + mcuxClEls_KeyIndex_t keyIdxPrivServer = 2u; // Set keystore index at which mcuxClEls_EccKeyGen_Async is storing the private key. + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyGen_Async( // Perform key generation. + KeyGenOptions, // Set the prepared configuration. + (mcuxClEls_KeyIndex_t) 0U, // This parameter (signingKeyIdx) is ignored, since no signature is requested in the configuration. + keyIdxPrivServer, // Keystore index at which the generated private key is stored. + GenKeyProp, // Set the generated key properties. + NULL, + (uint8_t *)ecc_public_key_server // Output buffer, which the operation will write the public key to. + )); + // mcuxClEls_EccKeyGen_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyGen_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyGen_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyGen_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + //Perform Key Exchange + mcuxClEls_KeyIndex_t sharedSecretIdx = 10U; // Set shared key index + + mcuxClEls_KeyProp_t SharedSecretProp = {0}; // Initialize a new configuration for the mcuxClEls_EccKeyExchange_Async generated key properties. + SharedSecretProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access + SharedSecretProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access + SharedSecretProp.bits.utlpsms = MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE; //Shared Secret is used as pre-master secret for TLS + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_EccKeyExchange_Async( + keyIdxPrivClient, + (uint8_t *)ecc_public_key_server, + sharedSecretIdx, + SharedSecretProp)); + + // mcuxClEls_EccKeyExchange_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_EccKeyExchange_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_EccKeyExchange_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_EccKeyExchange_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // PRNG needs to be initialized; this can be done by calling mcuxClEls_KeyDelete_Async (delete any key slot, can be empty) + // However mcuxClEls_EccKeyExchange_Async also guarantees PRNG is initialized + + //generate server random + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom(server_random, 32U)); + // mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + //generate client random + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Prng_GetRandom(client_random, 32U)); + // mcuxClEls_Prng_GetRandom is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; // Expect that no error occurred, meaning that the mcuxClEls_Prng_GetRandom operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + //perpare derivation data for master key + //the derivation data has a fixed length of 640 bits and is composed as follows + //"key expansion"||server random||client random||800000 + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data, + key_expansion_string, + sizeof(key_expansion_string), + sizeof(key_expansion_string) + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data+sizeof(key_expansion_string), + server_random, + sizeof(server_random), + sizeof(server_random) + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data+sizeof(key_expansion_string)+32U, + client_random, + sizeof(client_random), + sizeof(client_random) + )); + // mcuxClMemory_set is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set( + derivation_data+sizeof(key_expansion_string)+32U+32U, + 0x80, + 1U, + 1U + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set( + derivation_data+sizeof(key_expansion_string)+32U+32U+1U, + 0x00, + 2U, + 2U + )); + // mcuxClMemory_set is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + + mcuxClEls_KeyProp_t tlsMasterKeyProp = {0}; + tlsMasterKeyProp.bits.upprot_priv = MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE; // Configure that user access rights: non-privileged access + tlsMasterKeyProp.bits.upprot_sec = MCUXCLELS_KEYPROPERTY_SECURE_TRUE; // Configure that user access rights: secure access + tlsMasterKeyProp.bits.utlsms = MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE; + //Generate TLS master key + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async( + derivation_data, ///< [in] The TLS derivation data + tlsMasterKeyProp, ///< [in] Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored. + sharedSecretIdx ///< [in] The index of the TLS pre-master key, which is overwritten with the master key + )); + // mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + //perpare derivation data for session keys + //the derivation data has a fixed length of 640 bits and is composed as follows + //"master secret"||client random||server random||800000 + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data, + master_key_string, + sizeof(master_key_string), + sizeof(master_key_string) + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data+sizeof(master_key_string), + client_random, + sizeof(client_random), + sizeof(client_random) + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy( + derivation_data+sizeof(master_key_string)+32U, + server_random, + sizeof(server_random), + sizeof(server_random) + )); + // mcuxClMemory_set is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set( + derivation_data+sizeof(master_key_string)+32U+32U, + 0x80, + 1U, + 1U + )); + // mcuxClMemory_copy is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_set( + derivation_data+sizeof(master_key_string)+32U+32U+1U, + 0x00, + 2U, + 2U + )); + // mcuxClMemory_set is a flow-protected function: Check the protection token and the return value + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) != token) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + mcuxClEls_KeyProp_t KeyProp = {0}; + mcuxClEls_GetKeyProperties(sharedSecretIdx, &KeyProp); + + //Generate TLS session keys + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async( + derivation_data, ///< [in] The TLS derivation data + GenKeyProp, ///< [in] Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored. + sharedSecretIdx ///< [in] The index of the TLS master key, which is overwritten with one of the session keys. + )); + // mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_LimitedWaitForOperation(0x00100000U, MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async operation to complete. + // mcuxClEls_LimitedWaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_LimitedWaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + //Delete all keys from keystore + /** deleted keyIdxPrivClient keySlot **/ + if(!mcuxClExample_Els_KeyDelete(keyIdxPrivClient)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** deleted keyIdxPrivServer keySlot **/ + if(!mcuxClExample_Els_KeyDelete(keyIdxPrivServer)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + for(uint8_t i = sharedSecretIdx;i // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +static const uint8_t data[3] CSS_CONST_SEGMENT = { + 0x61u, 0x62u, 0x63u +}; + +static const uint8_t hashExpected[28] CSS_CONST_SEGMENT = { + 0x23u, 0x09u, 0x7Du, 0x22u, 0x34u, 0x05u, 0xD8u, 0x22u, + 0x86u, 0x42u, 0xA4u, 0x77u, 0xBDu, 0xA2u, 0x55u, 0xB3u, + 0x2Au, 0xADu, 0xBCu, 0xE4u, 0xBDu, 0xA0u, 0xB3u, 0xF7u, + 0xE3u, 0x6Cu, 0x9Du, 0xA7u +}; + + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha224_oneshot_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_224]; + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token2, mcuxClHash_compute( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha224, + /* mcuxCl_InputBuffer_t pIn: */ data, + /* uint32_t inSize: */ sizeof(data), + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) != token2) || (MCUXCLHASH_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + for(size_t i = 0U; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) // Expect that the resulting hash matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_longMsgOneshot_example.c b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_longMsgOneshot_example.c new file mode 100644 index 000000000..df6117afb --- /dev/null +++ b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_longMsgOneshot_example.c @@ -0,0 +1,136 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +/* Test vector from CAVS 11.0 "SHA-256 LongMsg" */ +static const uint8_t data[] = { + 0x45u, 0x11u, 0x01u, 0x25u, 0x0eu, 0xc6u, 0xf2u, 0x66u, + 0x52u, 0x24u, 0x9du, 0x59u, 0xdcu, 0x97u, 0x4bu, 0x73u, + 0x61u, 0xd5u, 0x71u, 0xa8u, 0x10u, 0x1cu, 0xdfu, 0xd3u, + 0x6au, 0xbau, 0x3bu, 0x58u, 0x54u, 0xd3u, 0xaeu, 0x08u, + 0x6bu, 0x5fu, 0xddu, 0x45u, 0x97u, 0x72u, 0x1bu, 0x66u, + 0xe3u, 0xc0u, 0xdcu, 0x5du, 0x8cu, 0x60u, 0x6du, 0x96u, + 0x57u, 0xd0u, 0xe3u, 0x23u, 0x28u, 0x3au, 0x52u, 0x17u, + 0xd1u, 0xf5u, 0x3fu, 0x2fu, 0x28u, 0x4fu, 0x57u, 0xb8u, + 0x5cu, 0x8au, 0x61u, 0xacu, 0x89u, 0x24u, 0x71u, 0x1fu, + 0x89u, 0x5cu, 0x5eu, 0xd9u, 0x0eu, 0xf1u, 0x77u, 0x45u, + 0xedu, 0x2du, 0x72u, 0x8au, 0xbdu, 0x22u, 0xa5u, 0xf7u, + 0xa1u, 0x34u, 0x79u, 0xa4u, 0x62u, 0xd7u, 0x1bu, 0x56u, + 0xc1u, 0x9au, 0x74u, 0xa4u, 0x0bu, 0x65u, 0x5cu, 0x58u, + 0xedu, 0xfeu, 0x0au, 0x18u, 0x8au, 0xd2u, 0xcfu, 0x46u, + 0xcbu, 0xf3u, 0x05u, 0x24u, 0xf6u, 0x5du, 0x42u, 0x3cu, + 0x83u, 0x7du, 0xd1u, 0xffu, 0x2bu, 0xf4u, 0x62u, 0xacu, + 0x41u, 0x98u, 0x00u, 0x73u, 0x45u, 0xbbu, 0x44u, 0xdbu, + 0xb7u, 0xb1u, 0xc8u, 0x61u, 0x29u, 0x8cu, 0xdfu, 0x61u, + 0x98u, 0x2au, 0x83u, 0x3au, 0xfcu, 0x72u, 0x8fu, 0xaeu, + 0x1eu, 0xdau, 0x2fu, 0x87u, 0xaau, 0x2cu, 0x94u, 0x80u, + 0x85u, 0x8bu, 0xecu +}; + +static const uint8_t hashExpected[MCUXCLHASH_OUTPUT_SIZE_SHA_256] = { + 0x3cu, 0x59u, 0x3au, 0xa5u, 0x39u, 0xfdu, 0xcdu, 0xaeu, + 0x51u, 0x6cu, 0xdfu, 0x2fu, 0x15u, 0x00u, 0x0fu, 0x66u, + 0x34u, 0x18u, 0x5cu, 0x88u, 0xf5u, 0x05u, 0xb3u, 0x97u, + 0x75u, 0xfbu, 0x9au, 0xb1u, 0x37u, 0xa1u, 0x0au, 0xa2u +}; + + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha256_longMsgOneshot_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_256]; + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token2, mcuxClHash_compute( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha256, + /* mcuxCl_InputBuffer_t pIn: */ data, + /* uint32_t inSize: */ sizeof(data), + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) != token2) || (MCUXCLHASH_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + for(size_t i = 0U; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) // Expect that the resulting hash matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_oneshot_example.c b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_oneshot_example.c new file mode 100644 index 000000000..60e6c725c --- /dev/null +++ b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_oneshot_example.c @@ -0,0 +1,141 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +static const uint8_t data[3] CSS_CONST_SEGMENT = { + 0x61u, 0x62u, 0x63u +}; + +static const uint8_t hashExpected[32] CSS_CONST_SEGMENT = { + 0xbau, 0x78u, 0x16u, 0xbfu, 0x8fu, 0x01u, 0xcfu, 0xeau, + 0x41u, 0x41u, 0x40u, 0xdeu, 0x5du, 0xaeu, 0x22u, 0x23u, + 0xb0u, 0x03u, 0x61u, 0xa3u, 0x96u, 0x17u, 0x7au, 0x9cu, + 0xb4u, 0x10u, 0xffu, 0x61u, 0xf2u, 0x00u, 0x15u, 0xadu +}; + +static const uint8_t rtfExpected[32] CSS_CONST_SEGMENT = { + 0x58u, 0x9Fu, 0x9Fu, 0xFEu, 0xD4u, 0xC4u, 0x77u, 0x96u, + 0x6Bu, 0xFBu, 0x8Du, 0x41u, 0xF3u, 0x78u, 0x95u, 0xB0u, + 0x8Cu, 0x69u, 0x04u, 0x7Du, 0xF8u, 0xF9u, 0x11u, 0xD6u, + 0xF3u, 0xB5u, 0x7Fu, 0xBEu, 0x08u, 0xFAu, 0xEEu, 0x8Du +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha256_oneshot_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_256]; + uint8_t rtf[32]; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sr_status, token, mcuxClSession_setRtf( + /* mcuxClSession_Handle_t session: */ session, + /* uint8_t const * pRtf: */ rtf, + /* mcuxClSession_Rtf RtfOptions: */ MCUXCLSESSION_RTF_UPDATE_TRUE + )); // Enable the ELS. + // mcuxClSession_setRtf is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_setRtf) != token) || (MCUXCLSESSION_STATUS_OK != sr_status)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + uint32_t hashOutputSize = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token2, mcuxClHash_compute( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha256, + /* mcuxCl_InputBuffer_t pIn: */ data, + /* uint32_t inSize: */ sizeof(data), + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) != token2) || (MCUXCLHASH_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + for(size_t i = 0U; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) // Expect that the resulting hash matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + for(size_t i = 0U; i < sizeof(hash); i++) + { + if(rtfExpected[i] != rtf[i]) // Expect that the resulting rtf matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_streaming_example.c b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_streaming_example.c new file mode 100644 index 000000000..3397bb81d --- /dev/null +++ b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha256_streaming_example.c @@ -0,0 +1,181 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +static const uint8_t data1[7] CSS_CONST_SEGMENT = { + 0x65u, 0x78u, 0x61u, 0x6du, 0x70u, 0x6cu, 0x65u //example +}; + +static const uint8_t data2[4] CSS_CONST_SEGMENT = { + 0x68u, 0x61u, 0x73u, 0x68u //hash +}; + +static const uint8_t data3[9] CSS_CONST_SEGMENT = { + 0x73u, 0x74u, 0x72u, 0x65u, 0x61u, 0x6du, 0x69u, 0x6eu, 0x67u //streaming +}; + +static const uint8_t hashExpected[32] CSS_CONST_SEGMENT = { + 0xb3u, 0xdcu, 0xe3u, 0x33u, 0x68u, 0x24u, 0x6du, 0x98u, + 0x04u, 0x6bu, 0xd4u, 0x52u, 0x6cu, 0x69u, 0xc1u, 0xd0u, + 0x37u, 0x01u, 0x57u, 0x60u, 0x95u, 0xbau, 0x74u, 0x74u, + 0xc6u, 0xcbu, 0xf2u, 0x5eu, 0x3fu, 0xffu, 0xe8u, 0xc4u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha256_streaming_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /* RTF update is set to false by default */ + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint64_t context[MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS / 2u]; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result2, token2, mcuxClHash_init( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ (mcuxClHash_Context_t) context, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha256 + )); + // mcuxClHash_init is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_init) != token2) || (MCUXCLHASH_STATUS_OK != result2)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result3, token3, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ (mcuxClHash_Context_t) context, + /* mcuxCl_InputBuffer_t in: */ data1, + /* uint32_t inSize: */ sizeof(data1) + )); + // mcuxClHash_process is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process) != token3) || (MCUXCLHASH_STATUS_OK != result3)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result4, token4, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ (mcuxClHash_Context_t) context, + /* mcuxCl_InputBuffer_t in: */ data2, + /* uint32_t inSize: */ sizeof(data2) + )); + // mcuxClHash_process is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process) != token4) || (MCUXCLHASH_STATUS_OK != result4)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result5, token5, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ (mcuxClHash_Context_t) context, + /* mcuxCl_InputBuffer_t in: */ data3, + /* uint32_t inSize: */ sizeof(data3) + )); + // mcuxClHash_process is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process) != token5) || (MCUXCLHASH_STATUS_OK != result5)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_256]; + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result6, token6, mcuxClHash_finish( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ (mcuxClHash_Context_t) context, + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + // mcuxClHash_finish is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_finish) != token6) || (MCUXCLHASH_STATUS_OK != result6)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + uint8_t hashDifferent = 0u; + for(size_t i = 0u; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) + { + hashDifferent |= 1u; + } + } + + if(hashDifferent) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha384_oneshot_example.c b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha384_oneshot_example.c new file mode 100644 index 000000000..324d70f14 --- /dev/null +++ b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha384_oneshot_example.c @@ -0,0 +1,116 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +static const uint8_t data[3] CSS_CONST_SEGMENT = { + 0x61u, 0x62u, 0x63u +}; + +static const uint8_t hashExpected[48] CSS_CONST_SEGMENT = { + 0xCBu, 0x00u, 0x75u, 0x3Fu, 0x45u, 0xA3u, 0x5Eu, 0x8Bu, + 0xB5u, 0xA0u, 0x3Du, 0x69u, 0x9Au, 0xC6u, 0x50u, 0x07u, + 0x27u, 0x2Cu, 0x32u, 0xABu, 0x0Eu, 0xDEu, 0xD1u, 0x63u, + 0x1Au, 0x8Bu, 0x60u, 0x5Au, 0x43u, 0xFFu, 0x5Bu, 0xEDu, + 0x80u, 0x86u, 0x07u, 0x2Bu, 0xA1u, 0xE7u, 0xCCu, 0x23u, + 0x58u, 0xBAu, 0xECu, 0xA1u, 0x34u, 0xC8u, 0x25u, 0xA7u +}; + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha384_oneshot_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_384]; + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token2, mcuxClHash_compute( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha384, + /* mcuxCl_InputBuffer_t pIn: */ data, + /* uint32_t inSize: */ sizeof(data), + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) != token2) || (MCUXCLHASH_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + for(size_t i = 0u; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) // Expect that the resulting hash matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha512_oneshot_example.c b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha512_oneshot_example.c new file mode 100644 index 000000000..59cb2ab92 --- /dev/null +++ b/components/els_pkc/examples/mcuxClHashModes/mcuxClHashModes_sha512_oneshot_example.c @@ -0,0 +1,119 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to the entire mcuxClSession component +#include // Interface to the entire mcuxClHash component +#include +#include +#include // Code flow protection +#include // memory segment definitions +#include +#include +#include + +static const uint8_t data[3] CSS_CONST_SEGMENT = { + 0x61u, 0x62u, 0x63u +}; + +static const uint8_t hashExpected[64] CSS_CONST_SEGMENT = { + 0xDDu, 0xAFu, 0x35u, 0xA1u, 0x93u, 0x61u, 0x7Au, 0xBAu, + 0xCCu, 0x41u, 0x73u, 0x49u, 0xAEu, 0x20u, 0x41u, 0x31u, + 0x12u, 0xE6u, 0xFAu, 0x4Eu, 0x89u, 0xA9u, 0x7Eu, 0xA2u, + 0x0Au, 0x9Eu, 0xEEu, 0xE6u, 0x4Bu, 0x55u, 0xD3u, 0x9Au, + 0x21u, 0x92u, 0x99u, 0x2Au, 0x27u, 0x4Fu, 0xC1u, 0xA8u, + 0x36u, 0xBAu, 0x3Cu, 0x23u, 0xA3u, 0xFEu, 0xEBu, 0xBDu, + 0x45u, 0x4Du, 0x44u, 0x23u, 0x64u, 0x3Cu, 0xE8u, 0x0Eu, + 0x2Au, 0x9Au, 0xC9u, 0x4Fu, 0xA5u, 0x4Cu, 0xA4u, 0x9Fu +}; + + +MCUXCLEXAMPLE_FUNCTION(mcuxClHashModes_sha512_oneshot_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + + /** Initialize ELS, MCUXCLELS_RESET_DO_NOT_CANCEL **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Initialize session */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Hash computation */ + /**************************************************************************/ + + uint8_t hash[MCUXCLHASH_OUTPUT_SIZE_SHA_512]; + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token2, mcuxClHash_compute( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClHash_Algo_t algorithm: */ mcuxClHash_Algorithm_Sha512, + /* mcuxCl_InputBuffer_t pIn: */ data, + /* uint32_t inSize: */ sizeof(data), + /* mcuxCl_Buffer_t pOut */ hash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) != token2) || (MCUXCLHASH_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(sizeof(hash) != hashOutputSize) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + for(size_t i = 0u; i < sizeof(hash); i++) + { + if(hashExpected[i] != hash[i]) // Expect that the resulting hash matches our expected output + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Els_Oneshot_External_Key_example.c b/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Els_Oneshot_External_Key_example.c new file mode 100644 index 000000000..aa1617106 --- /dev/null +++ b/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Els_Oneshot_External_Key_example.c @@ -0,0 +1,217 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include + +#include // Interface to the entire mcuxClEls component +#include +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClMac component +#include // Interface to the entire mcuxClHmac component +#include +#include // Interface to the entire mcuxClHmac component + + +/** Performs a HMAC computation using functions of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClHmac_Els_Oneshot_External_Key_example) +{ + /* Example (unpadded) key. */ + const uint8_t hmac_key[] = { + 0x00u, 0x11u, 0x22u, 0x33u, 0x44u, 0x55u, 0x66u, 0x77u, + 0x88u, 0x99u, 0xaau, 0xbbu, 0xccu, 0xddu, 0xeeu, 0xffu, + 0x00u, 0x11u, 0x22u, 0x33u, 0x44u, 0x55u, 0x66u, 0x77u, + 0x88u, 0x99u, 0xaau, 0xbbu, 0xccu, 0xddu, 0xeeu, 0xffu + }; + + /* Example input to the HMAC function. */ + const uint8_t hmac_input[MCUXCLELS_HASH_BLOCK_SIZE_SHA_256] = { + 0x00u, 0x9fu, 0x5eu, 0x39u, 0x94u, 0x30u, 0x03u, 0x82u, + 0x50u, 0x72u, 0x1bu, 0xe1u, 0x79u, 0x65u, 0x35u, 0xffu, + 0x21u, 0xa6u, 0x09u, 0xfdu, 0xf9u, 0xf0u, 0xf6u, 0x12u, + 0x66u, 0xe3u, 0xafu, 0x75u, 0xd7u, 0x04u, 0x31u, 0x7du, + 0x55u, 0x06u, 0xf8u, 0x06u, 0x5cu, 0x48u, 0x72u, 0x18u, + 0xe9u, 0x9eu, 0xb4u, 0xc3u, 0xd4u, 0x54u, 0x6cu, 0x4du, + 0x60u, 0x70u, 0x16u, 0x90u, 0x11u, 0x38u, 0x73u, 0x9du, + 0xbdu, 0xf4u, 0x37u, 0xa5u, 0xe6u, 0xf5u, 0x02u, 0x1au + }; + + /* Example reference HMAC. */ + const uint8_t hmac_output_reference[MCUXCLHMAC_ELS_OUTPUT_SIZE] = { + 0x06u, 0xb8u, 0xb8u, 0xc3u, 0x21u, 0x79u, 0x15u, 0xbeu, + 0x0bu, 0x0fu, 0x86u, 0x90u, 0x4fu, 0x76u, 0x74u, 0x1bu, + 0x1bu, 0xe2u, 0x86u, 0x79u, 0x38u, 0xf4u, 0xf0u, 0x5du, + 0x34u, 0x15u, 0xbbu, 0x36u, 0x8fu, 0x4au, 0x57u, 0xfbu + }; + + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /* Enable ELS */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Enable_Async()); // Enable the ELS. + // mcuxClEls_Enable_Async is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Enable_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[sizeof(hmac_key) / sizeof(uint32_t)]; + + /* Output buffer for the computed MAC. */ + static uint8_t result_buffer[MCUXCLHMAC_ELS_OUTPUT_SIZE]; + + /* Allocate and initialize session / workarea */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_init( + /* mcuxClSession_Handle_t pSession: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* const mcuxClKey_Type* type: */ mcuxClKey_Type_Hmac_variableLength, + /* mcuxCl_Buffer_t pKeyData: */ (uint8_t *) hmac_key, + /* uint32_t keyDataLength: */ sizeof(hmac_key))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Load key to memory. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_loadMemory(session, + key, + key_buffer)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadMemory) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* HMAC computation */ + /**************************************************************************/ + /* Copy the input data to temp buffer with proper size */ + uint8_t tempIn [MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH(sizeof(hmac_input))]; + + for(int i=0 ; i < MCUXCLELS_HASH_BLOCK_SIZE_SHA_256; i++) + { + tempIn[i] = hmac_input[i]; + } + + /* Call the mcuxClMac_compute function to compute a HMAC in one shot. */ + uint32_t result_size = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClMac_compute( + /* mcuxClSession_Handle_t session: */ session, + /* const mcuxClKey_Handle_t key: */ key, + /* const mcuxClMac_Mode_t mode: */ mcuxClMac_Mode_HMAC_SHA2_256_ELS, + /* mcuxCl_InputBuffer_t pIn: */ (uint8_t*) tempIn, + /* uint32_t inLength: */ sizeof(hmac_input), + /* mcuxCl_Buffer_t pMac: */ result_buffer, + /* uint32_t * const pMacLength: */ &result_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_compute) != token) || (MCUXCLMAC_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + /* Compare the output size with the expected MAC size */ + if(sizeof(hmac_output_reference) != result_size) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Compare the result to the reference value. */ + if(!mcuxClCore_assertEqual(hmac_output_reference, result_buffer, sizeof(hmac_output_reference))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, + key)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Clean-up and destroy the session. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cleanup_result, cleanup_token, mcuxClSession_cleanup( + /* mcuxClSession_Handle_t pSession: */ session)); + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_cleanup) != cleanup_token || MCUXCLSESSION_STATUS_OK != cleanup_result) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(destroy_result, destroy_token, mcuxClSession_destroy( + /* mcuxClSession_Handle_t pSession: */ session)); + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_destroy) != destroy_token || MCUXCLSESSION_STATUS_OK != destroy_result) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Disable ELS */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Disable()); // Disable the ELS. + // mcuxClEls_Disable is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Disable) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Sw_Oneshot_example.c b/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Sw_Oneshot_example.c new file mode 100644 index 000000000..8a2f00e02 --- /dev/null +++ b/components/els_pkc/examples/mcuxClHmac/mcuxClHmac_Sw_Oneshot_example.c @@ -0,0 +1,213 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples +#include +#include // Interface to the entire mcuxClEls component +#include +#include +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClMac component +#include // Interface to the entire mcuxClHmac component +#include +#include +#include + +/** Performs a HMAC computation using functions of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClHmac_Sw_Oneshot_example) +{ + /* Example (unpadded) key. */ + const uint8_t hmac_key[] = { + 0x00u, 0x11u, 0x22u, 0x33u, 0x44u, 0x55u, 0x66u, 0x77u, + 0x88u, 0x99u, 0xaau, 0xbbu, 0xccu, 0xddu, 0xeeu, 0xffu, + 0x00u, 0x11u, 0x22u, 0x33u, 0x44u, 0x55u, 0x66u, 0x77u, + 0x88u, 0x99u, 0xaau, 0xbbu, 0xccu, 0xddu, 0xeeu, 0xffu + }; + + /* Example input to the HMAC function. */ + const uint8_t hmac_input[] = { + 0x00u, 0x9fu, 0x5eu, 0x39u, 0x94u, 0x30u, 0x03u, 0x82u, + 0x50u, 0x72u, 0x1bu, 0xe1u, 0x79u, 0x65u, 0x35u, 0xffu, + 0x21u, 0xa6u, 0x09u, 0xfdu, 0xf9u, 0xf0u, 0xf6u, 0x12u, + 0x66u, 0xe3u, 0xafu, 0x75u, 0xd7u, 0x04u, 0x31u, 0x7du, + 0x55u, 0x06u, 0xf8u, 0x06u, 0x5cu, 0x48u, 0x72u, 0x18u, + 0xe9u, 0x9eu, 0xb4u, 0xc3u, 0xd4u, 0x54u, 0x6cu, 0x4du, + 0x60u, 0x70u, 0x16u, 0x90u, 0x11u, 0x38u, 0x73u, 0x9du, + 0xbdu, 0xf4u, 0x37u, 0xa5u, 0xe6u, 0xf5u, 0x02u, 0x1au + }; + + /* Example reference HMAC. */ + const uint8_t hmac_output_reference[MCUXCLHASH_OUTPUT_SIZE_SHA_256] = { + 0x06u, 0xb8u, 0xb8u, 0xc3u, 0x21u, 0x79u, 0x15u, 0xbeu, + 0x0bu, 0x0fu, 0x86u, 0x90u, 0x4fu, 0x76u, 0x74u, 0x1bu, + 0x1bu, 0xe2u, 0x86u, 0x79u, 0x38u, 0xf4u, 0xf0u, 0x5du, + 0x34u, 0x15u, 0xbbu, 0x36u, 0x8fu, 0x4au, 0x57u, 0xfbu + }; + + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /* Initialize ELS (needed for Hash computation) */ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[sizeof(hmac_key) / sizeof(uint32_t)]; + + /* Output buffer for the computed MAC. */ + static uint8_t result_buffer[MCUXCLHMAC_MAX_OUTPUT_SIZE]; + + /* Allocate and initialize session / workarea */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session / workarea */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keyInit_result, keyInit_token, mcuxClKey_init( + /* mcuxClSession_Handle_t pSession: */ session, + /* mcuxClKey_Handle_t key: */ key, + /* const mcuxClKey_Type* type: */ mcuxClKey_Type_Hmac_variableLength, + /* mcuxCl_Buffer_t pKeyData: */ (uint8_t *) hmac_key, + /* uint32_t keyDataLength: */ sizeof(hmac_key))); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != keyInit_token) || (MCUXCLKEY_STATUS_OK != keyInit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Load key to memory. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keyLoad_result, keyLoad_token, mcuxClKey_loadMemory(session, + key, + key_buffer)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadMemory) != keyLoad_token) || (MCUXCLKEY_STATUS_OK != keyLoad_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Generate an HMAC mode containing the hash algorithm */ + /**************************************************************************/ + + uint8_t hmacModeDescBuffer[MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE]; + mcuxClMac_CustomMode_t mode = (mcuxClMac_CustomMode_t) hmacModeDescBuffer; + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(hashCreateMode_result, hashCreateMode_token, mcuxClHmac_createHmacMode( + /* mcuxClMac_CustomMode_t mode: */ mode, + /* mcuxClHash_Algo_t hashAlgorithm: */ mcuxClHash_Algorithm_Sha256) + ); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_createHmacMode) != hashCreateMode_token) || (MCUXCLMAC_STATUS_OK != hashCreateMode_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* HMAC computation */ + /**************************************************************************/ + + /* Call the mcuxClMac_compute function to compute a HMAC in one shot. */ + uint32_t result_size = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(macCompute_result, macCompute_token, mcuxClMac_compute( + /* mcuxClSession_Handle_t session: */ session, + /* const mcuxClKey_Handle_t key: */ key, + /* const mcuxClMac_Mode_t mode: */ mode, + /* mcuxCl_InputBuffer_t pIn: */ (uint8_t*) hmac_input, /* No extra space for padding is required */ + /* uint32_t inLength: */ sizeof(hmac_input), + /* mcuxCl_Buffer_t pMac: */ result_buffer, + /* uint32_t * const pMacLength: */ &result_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_compute) != macCompute_token) || (MCUXCLMAC_STATUS_OK != macCompute_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + /* Compare the output size with the expected MAC size */ + if(sizeof(hmac_output_reference) != result_size) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Compare the result to the reference value. */ + if(!mcuxClCore_assertEqual(hmac_output_reference, result_buffer, sizeof(hmac_output_reference))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(keyFlush_result, keyFlush_token, mcuxClKey_flush(session, + key)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != keyFlush_token) || (MCUXCLKEY_STATUS_OK != keyFlush_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Clean-up and destroy the session. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sessionCleanup_result, sessionCleanup_token, mcuxClSession_cleanup( + /* mcuxClSession_Handle_t pSession: */ session)); + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_cleanup) != sessionCleanup_token || MCUXCLSESSION_STATUS_OK != sessionCleanup_result) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sessionDestroy_result, sessionDestroy_token, mcuxClSession_destroy( + /* mcuxClSession_Handle_t pSession: */ session)); + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_destroy) != sessionDestroy_token || MCUXCLSESSION_STATUS_OK != sessionDestroy_result) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClKey/mcuxClKey_example.c b/components/els_pkc/examples/mcuxClKey/mcuxClKey_example.c new file mode 100644 index 000000000..9c877ec09 --- /dev/null +++ b/components/els_pkc/examples/mcuxClKey/mcuxClKey_example.c @@ -0,0 +1,109 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_example.c + * @brief Example for the mcuxClKey component + * + * @example mcuxClKey_example.c + * @brief Example for the mcuxClKey component + */ + +#include +#include +#include +#include // Code flow protection +#include +#include // bool type for the example's return code +#include +#include +#include + + +/* Example AES-128 key. */ +static uint32_t aes128_key[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS] = +{ + 0xb97d0b7cu, 0xd0101f81u, 0x7a6c470eu, 0xe0f6920du +}; + + + +/** Performs an example initialization and cleanup of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClKey_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + mcuxClSession_Descriptor_t session; + //Allocate and initialize session + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(&session, 0u, 0u); + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t key_properties; + + key_properties.word.value = 0u; + key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS]; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(&session, + key, + mcuxClKey_Type_Aes128, + (uint8_t *) aes128_key, + sizeof(aes128_key), + &key_properties, + key_buffer, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* The key could now be used for a cryptographic operation. */ + /**************************************************************************/ + + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(resultFlush, tokenFlush, mcuxClKey_flush( + &session, + key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != tokenFlush) || (MCUXCLKEY_STATUS_OK != resultFlush)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(&session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_multipart_zero_padding_example.c b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_multipart_zero_padding_example.c new file mode 100644 index 000000000..cc8c62bd6 --- /dev/null +++ b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_multipart_zero_padding_example.c @@ -0,0 +1,204 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to AES-related definitions and types +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClMac component +#include // Interface to the entire mcuxClMacModes component +#include +#include +#include +#include + +/** Performs a CMAC computation using functions of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClMacModes_cbc_mac_multipart_zero_padding_example) +{ + static uint8_t key256[] = { + 0x12u, 0xE6u, 0xDFu, 0x61u, 0xD7u, 0xEBu, 0xD1u, 0xAEu, + 0x7Au, 0x59u, 0x93u, 0x0Eu, 0x05u, 0x8Au, 0x76u, 0x4Fu, + 0x2Eu, 0x1Bu, 0x6Eu, 0xC7u, 0xA1u, 0xDEu, 0xF8u, 0x68u, + 0x19u, 0x66u, 0x43u, 0x47u, 0x83u, 0x8Bu, 0x30u, 0x6Du + }; + + static const uint8_t inputZeroPadd[] = { + 0x51u, 0x44u, 0xA5u, 0xDCu, 0x29u, 0x0Eu, 0x16u, 0x85u, + 0xB5u, 0x0Bu, 0x2Bu, 0x0Bu, 0xA9u, 0x1Eu, 0x8Cu, 0xD3u, + 0x6Eu, 0xD9u, 0xADu, 0x87u, 0x58u + }; + + static const uint8_t resZeroPadd[] = { + 0xC2u, 0x21u, 0x5Bu, 0xC7u, 0xA2u, 0x28u, 0x68u, 0x93u, + 0x2Eu, 0x5Au, 0xFCu, 0x22u, 0xB7u, 0xF2u, 0x25u, 0x0Eu + }; + + /* Example input size. */ + size_t cmac_input_size = 21u; + + + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[MCUXCLKEY_SIZE_256 / sizeof(uint32_t)]; + + /* Output buffer for the computed MAC. */ + static uint8_t result_buffer[MCUXCLELS_CMAC_OUT_SIZE]; + + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t cmac_key_properties; + + cmac_key_properties.word.value = 0u; + cmac_key_properties.bits.ucmac = MCUXCLELS_KEYPROPERTY_CMAC_TRUE; + cmac_key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + cmac_key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes256, + (mcuxCl_Buffer_t) key256, + sizeof(key256), + &cmac_key_properties, + key_buffer, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* MAC computation */ + /**************************************************************************/ + // init + // process + // finish + uint8_t context[MCUXCLMAC_CONTEXT_SIZE]; + mcuxClMac_Context_t * ctx = (mcuxClMac_Context_t *) context; + + /* Call the mcuxClMac_init */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(initResult, initToken, mcuxClMac_init( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClMac_Context_t * const pContext: */ ctx, + /* const mcuxClKey_Handle_t key: */ key, + /* mcuxClMac_Mode_t mode: */ mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1 + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_init) != initToken) || (MCUXCLMAC_STATUS_OK != initResult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Call the mcuxClMac_process */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(processResult, processToken, mcuxClMac_process( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClMac_Context_t * const pContext: */ ctx, + /* mcuxCl_InputBuffer_t pIn: */ inputZeroPadd, + /* uint32_t inLength: */ cmac_input_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_process) != processToken) || (MCUXCLMAC_STATUS_OK != processResult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Call the mcuxClMac_finish */ + uint32_t result_size = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(finishResult, finishToken, mcuxClMac_finish( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClMac_Context_t * const pContext: */ ctx, + /* mcuxCl_Buffer_t pMac: */ result_buffer, + /* uint32_t * const pMacLength: */ &result_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_finish) != finishToken) || (MCUXCLMAC_STATUS_OK != finishResult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + /* Compare the output size with the expected MAC size */ + if(sizeof(resZeroPadd) != result_size) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Compare the result to the reference value. */ + if(!mcuxClCore_assertEqual(resZeroPadd, result_buffer, sizeof(resZeroPadd))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, + key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_oneshot_example.c b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_oneshot_example.c new file mode 100644 index 000000000..daaa73554 --- /dev/null +++ b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_oneshot_example.c @@ -0,0 +1,167 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include // Defines and assertions for examples + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to AES-related definitions and types +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClMac component +#include // Interface to the entire mcuxClMacModes component +#include +#include +#include +#include + +/** Performs a CMAC computation using functions of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClMacModes_cbc_mac_oneshot_example) +{ + /* Example AES-128 key. */ + static const uint8_t aes128_key[MCUXCLAES_AES128_KEY_SIZE] = { + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + }; + + /* Example input size. */ + size_t cmac_input_size_16 = 32u; + + /* Example input to the CMAC function. */ + static const uint8_t cmac_input16_in[] = { + 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, + 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, + 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, + 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu, 0xddu + }; + + /* Example reference CMAC. */ + static const uint8_t cmac_output_reference16[MCUXCLELS_CMAC_OUT_SIZE] = { + 0x55u, 0xffu, 0x3du, 0x8cu, 0xa5u, 0xc7u, 0x4eu, 0x8fu, + 0x75u, 0x4du, 0x57u, 0xabu, 0xfau, 0xb4u, 0x76u, 0x97u + }; + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS]; + + /* Output buffer for the computed MAC. */ + static uint8_t result_buffer[MCUXCLELS_CMAC_OUT_SIZE]; + + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t cmac_key_properties; + + cmac_key_properties.word.value = 0u; + cmac_key_properties.bits.ucmac = MCUXCLELS_KEYPROPERTY_CMAC_TRUE; + cmac_key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + cmac_key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &cmac_key_properties, + key_buffer, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* MAC computation */ + /**************************************************************************/ + + /* Call the mcuxClMac_compute function to compute a CMAC in one shot. */ + uint32_t result_size = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClMac_compute( + /* mcuxClSession_Handle_t session: */ session, + /* const mcuxClKey_Handle_t key: */ key, + /* const mcuxClMac_Mode_t mode: */ mcuxClMac_Mode_CBCMAC_NoPadding, + /* mcuxCl_InputBuffer_t pIn: */ cmac_input16_in, + /* uint32_t inLength: */ cmac_input_size_16, + /* mcuxCl_Buffer_t pMac: */ result_buffer, + /* uint32_t * const pMacLength: */ &result_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_compute) != token) || (MCUXCLMAC_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + /* Compare the result to the reference value. */ + if(!mcuxClCore_assertEqual(cmac_output_reference16, result_buffer, sizeof(cmac_output_reference16))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, + key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c new file mode 100644 index 000000000..3ecae3a53 --- /dev/null +++ b/components/els_pkc/examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c @@ -0,0 +1,191 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMacModes_cmac_oneshot_example.c + * @brief Example CMAC computation using functions of the mcuxClKey and mcuxClMac component + * + * @example mcuxClMac_cmac_oneshot_example.c + * @brief Example CMAC computation using functions of the mcuxClKey and mcuxClMac component + */ + +#include // Defines and assertions for examples + +#include // Interface to the entire mcuxClEls component +#include +#include // Interface to AES-related definitions and types +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClMac component +#include // Interface to the entire mcuxClMacModes component +#include +#include +#include +#include + +/** Performs a CMAC computation using functions of the mcuxClKey component. + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClMacModes_cmac_oneshot_example) +{ + /* Example AES-128 key. */ + static uint8_t aes128_key[MCUXCLAES_AES128_KEY_SIZE] = { + 0x7c, 0x0b, 0x7d, 0xb9, + 0x81, 0x1f, 0x10, 0xd0, + 0x0e, 0x47, 0x6c, 0x7a, + 0x0d, 0x92, 0xf6, 0xe0 + }; + + /* Example input size. */ + size_t cmac_input_size_16 = 32u; + + /* Example input to the CMAC function. */ + static uint8_t cmac_input16_in[] = { + 0x1eu, 0xe0u, 0xecu, 0x46u, + 0x6du, 0x46u, 0xfdu, 0x84u, + 0x9bu, 0x40u, 0xc0u, 0x66u, + 0xb4u, 0xfbu, 0xbdu, 0x22u, + 0xa2u, 0x0au, 0x4du, 0x80u, + 0xa0u, 0x08u, 0xacu, 0x9au, + 0xf1u, 0x7eu, 0x4fu, 0xdfu, + 0xd1u, 0x06u, 0x78u, 0x5eu + }; + + /* Example reference CMAC. */ + static uint8_t cmac_output_reference16[MCUXCLELS_CMAC_OUT_SIZE] = { + 0xbau, 0xecu, 0xdcu, 0x91u, + 0xe9u, 0xa1u, 0xfcu, 0x35u, + 0x72u, 0xadu, 0xf1u, 0xe4u, + 0x23u, 0x2au, 0xe2u, 0x85u + }; + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + /* Key buffer for the key in memory. */ + uint32_t key_buffer[MCUXCLAES_AES128_KEY_SIZE_IN_WORDS]; + + /* Output buffer for the computed MAC. */ + static uint8_t result_buffer[MCUXCLELS_CMAC_OUT_SIZE]; + + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + /* Allocate and initialize session */ + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE + MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE, 0u); + + /* Initialize the PRNG */ + MCUXCLEXAMPLE_INITIALIZE_PRNG(session); + + /**************************************************************************/ + /* Key setup */ + /**************************************************************************/ + + /* Create and initialize mcuxClKey_Descriptor_t structure. */ + uint32_t keyDesc[MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS]; + mcuxClKey_Handle_t key = (mcuxClKey_Handle_t) &keyDesc; + + /* Set key properties. */ + mcuxClEls_KeyProp_t cmac_key_properties; + + cmac_key_properties.word.value = 0u; + cmac_key_properties.bits.ucmac = MCUXCLELS_KEYPROPERTY_CMAC_TRUE; + cmac_key_properties.bits.ksize = MCUXCLELS_KEYPROPERTY_KEY_SIZE_128; + cmac_key_properties.bits.kactv = MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE; + + //Initializes a key handle, Set key properties and Load key. + if(!mcuxClExample_Key_Init_And_Load(session, + key, + mcuxClKey_Type_Aes128, + (mcuxCl_Buffer_t) aes128_key, + sizeof(aes128_key), + &cmac_key_properties, + key_buffer, MCUXCLEXAMPLE_CONST_EXTERNAL_KEY)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* MAC computation */ + /**************************************************************************/ + + /* Call the mcuxClMac_compute function to compute a CMAC in one shot. */ + uint32_t result_size = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClMac_compute( + /* mcuxClSession_Handle_t session: */ session, + /* const mcuxClKey_Handle_t key: */ key, + /* const mcuxClMac_Mode_t mode: */ mcuxClMac_Mode_CMAC, + /* mcuxCl_InputBuffer_t pIn: */ cmac_input16_in, + /* uint32_t inLength: */ cmac_input_size_16, + /* mcuxCl_Buffer_t pMac: */ result_buffer, + /* uint32_t * const pMacLength: */ &result_size + )); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMac_compute) != token) || (MCUXCLMAC_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification */ + /**************************************************************************/ + + /* Compare the output size with the expected MAC size */ + if(sizeof(cmac_output_reference16) != result_size) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Compare the result to the reference value. */ + if(!mcuxClCore_assertEqual(cmac_output_reference16, result_buffer, sizeof(cmac_output_reference16))) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Flush the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_flush(session, + key)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_flush) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c b/components/els_pkc/examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c new file mode 100644 index 000000000..fc25d774c --- /dev/null +++ b/components/els_pkc/examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c @@ -0,0 +1,169 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandomModes_ELS_example.c + * @brief Example for the mcuxClRandomModes component + * + * @example mcuxClRandomModes_ELS_example.c + * @brief Example for the mcuxClRandomModes component + */ + +#include +#include +#include +#include +#include // Code flow protection +#include +#include // Defines and assertions for examples +#include // Interface to the entire mcuxClEls component +#include + +/** Performs an example usage of the mcuxClRandom and mcuxClRandomModes components with ELS mode. + * @retval true The example code completed successfully + * @retval false The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClRandomModes_ELS_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Buffers to store the generated random values in. */ + uint8_t prng_buffer[10u]; + + uint8_t drbg_buffer1[3u]; + uint8_t drbg_buffer2[4u]; + uint8_t drbg_buffer3[5u]; + + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + //Allocate and initialize session + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, 0u, 0u); + + /* We don't need a context for ELS Rng. */ + mcuxClRandom_Context_t context = NULL; + + /**************************************************************************/ + /* Random init */ + /**************************************************************************/ + + /* Initialize the Random session with ELS mode. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomInitresult, token, mcuxClRandom_init( + session, + context, + mcuxClRandomModes_Mode_ELS_Drbg)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != token) || (MCUXCLRANDOM_STATUS_OK != randomInitresult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Generate random values. */ + /**************************************************************************/ + + /* Generate random values of smaller amount than one word size. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult1, token, mcuxClRandom_generate( + session, + drbg_buffer1, + sizeof(drbg_buffer1))); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult1)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Generate random values of multiple of word size. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult2, token, mcuxClRandom_generate( + session, + drbg_buffer2, + sizeof(drbg_buffer2))); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult2)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Generate random values of larger amount than but not multiple of one word size. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomGenerateresult3, token, mcuxClRandom_generate( + session, + drbg_buffer3, + sizeof(drbg_buffer3))); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) != token) || (MCUXCLRANDOM_STATUS_OK != randomGenerateresult3)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Generate non-cryptographic random values. */ + /**************************************************************************/ + + /* Initialize non-cryptographic Rng. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomNcInitresult, token, mcuxClRandom_ncInit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != token) || (MCUXCLRANDOM_STATUS_OK != randomNcInitresult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Generate random values. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomNcGenerateresult, token, mcuxClRandom_ncGenerate( + session, + prng_buffer, + sizeof(prng_buffer))); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate) != token) || (MCUXCLRANDOM_STATUS_OK != randomNcGenerateresult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Cleanup */ + /**************************************************************************/ + + /* Random uninit. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomUninitresult, token, mcuxClRandom_uninit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) != token) || (MCUXCLRANDOM_STATUS_OK != randomUninitresult)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c new file mode 100644 index 000000000..6e0a42589 --- /dev/null +++ b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c @@ -0,0 +1,233 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_sign_NoEncode_example.c + * @brief Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 + * (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format. + * + * @example mcuxClRsa_sign_NoEncode_example.c + * @brief Example of using function mcuxClRsa_sign to perform the RSA signature generation primitive RSASP1 + * (private exponentiation and NO padding) according to PKCS #1 v2.2, using a key in plain format. + */ + +#include // Interface to the entire mcuxClSession component +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClRandom component +#include // Interface to the entire mcuxClRsa component +#include // Memory segment definitions +#include + #include // Interface to the entire mcuxClEls component + #include + +/**********************************************************/ +/* Example test vectors */ +/**********************************************************/ +#define RSA_KEY_BIT_LENGTH (1024U) ///< The example uses a 1024-bit key +#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8U) ///< Converting the key-bitlength to bytelength + + +/** + * @brief Example value for public RSA modulus N. + */ +static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0xd0u, 0xb7u, 0x50u, 0xc8u, 0x55u, 0x4bu, 0x64u, 0xc7u, + 0xa9u, 0xd3u, 0x4du, 0x06u, 0x8eu, 0x02u, 0x0fu, 0xb5u, + 0x2fu, 0xeau, 0x1bu, 0x39u, 0xc4u, 0x79u, 0x71u, 0xa3u, + 0x59u, 0xf0u, 0xeeu, 0xc5u, 0xdau, 0x04u, 0x37u, 0xeau, + 0x3fu, 0xc9u, 0x45u, 0x97u, 0xd8u, 0xdbu, 0xffu, 0x54u, + 0x44u, 0xf6u, 0xceu, 0x5au, 0x32u, 0x93u, 0xacu, 0x89u, + 0xb1u, 0xeeu, 0xbbu, 0x3fu, 0x71u, 0x2bu, 0x3au, 0xd6u, + 0xa0u, 0x63u, 0x86u, 0xe6u, 0x40u, 0x19u, 0x85u, 0xe1u, + 0x98u, 0x98u, 0x71u, 0x5bu, 0x1eu, 0xa3u, 0x2au, 0xc0u, + 0x34u, 0x56u, 0xfeu, 0x17u, 0x96u, 0xd3u, 0x1eu, 0xd4u, + 0xafu, 0x38u, 0x9fu, 0x4fu, 0x67u, 0x5cu, 0x23u, 0xc4u, + 0x21u, 0xa1u, 0x25u, 0x49u, 0x1eu, 0x74u, 0x0fu, 0xdau, + 0xc4u, 0x32u, 0x2eu, 0xc2u, 0xd4u, 0x6eu, 0xc9u, 0x45u, + 0xddu, 0xc3u, 0x49u, 0x22u, 0x7bu, 0x49u, 0x21u, 0x91u, + 0xc9u, 0x04u, 0x91u, 0x45u, 0xfbu, 0x2fu, 0x8cu, 0x29u, + 0x98u, 0xc4u, 0x86u, 0xa8u, 0x40u, 0xeau, 0xc4u, 0xd3u + }; + + +/** + * @brief Example value for private RSA exponent d. + */ +static const uint8_t d[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x27u, 0xb7u, 0x11u, 0x9au, 0x09u, 0xedu, 0xb8u, 0x27u, + 0xc1u, 0x34u, 0x18u, 0xc8u, 0x20u, 0xb5u, 0x22u, 0xa1u, + 0xeeu, 0x08u, 0xdeu, 0x0eu, 0x4bu, 0xb2u, 0x81u, 0x06u, + 0xdbu, 0x6bu, 0xb9u, 0x14u, 0x98u, 0xa3u, 0xb3u, 0x61u, + 0xabu, 0x29u, 0x3au, 0xf8u, 0x3fu, 0xefu, 0xcdu, 0xd8u, + 0xa6u, 0xbdu, 0x21u, 0x34u, 0xcau, 0x4au, 0xfau, 0xcfu, + 0x64u, 0xa0u, 0xe3u, 0x3cu, 0x01u, 0x4fu, 0x48u, 0xf4u, + 0x75u, 0x30u, 0xf8u, 0x84u, 0x7cu, 0xc9u, 0x18u, 0x5cu, + 0xbeu, 0xdeu, 0xc0u, 0xd9u, 0x23u, 0x8cu, 0x8fu, 0x1du, + 0x54u, 0x98u, 0xf7u, 0x1cu, 0x7cu, 0x0cu, 0xffu, 0x48u, + 0xdcu, 0x21u, 0x34u, 0x21u, 0x74u, 0x2eu, 0x34u, 0x35u, + 0x0cu, 0xa9u, 0x40u, 0x07u, 0x75u, 0x3cu, 0xc0u, 0xe5u, + 0xa7u, 0x83u, 0x26u, 0x4cu, 0xf4u, 0x9fu, 0xf6u, 0x44u, + 0xffu, 0xeau, 0x94u, 0x25u, 0x3cu, 0xfeu, 0x86u, 0x85u, + 0x9au, 0xcdu, 0x2au, 0x22u, 0x76u, 0xcau, 0x4eu, 0x72u, + 0x15u, 0xf8u, 0xebu, 0xaau, 0x2fu, 0x18u, 0x8fu, 0x51u + }; + + /** + * @brief Input message + */ +static const uint8_t message[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x00u, 0x01u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x30u, 0x31u, 0x30u, + 0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u, + 0x03u, 0x04u, 0x02u, 0x01u, 0x05u, 0x00u, 0x04u, 0x20u, + 0x7cu, 0x50u, 0xbdu, 0xf5u, 0xafu, 0x92u, 0x3du, 0x43u, + 0x2cu, 0xefu, 0x56u, 0x84u, 0xfdu, 0xfau, 0x9du, 0xbau, + 0x18u, 0x9au, 0xaeu, 0x69u, 0x98u, 0x92u, 0xb9u, 0xa6u, + 0x86u, 0x3au, 0x35u, 0xeeu, 0xcfu, 0x54u, 0x6du, 0xecu + }; + + /** + * @brief Expected signature + */ +static const uint8_t referenceSignature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x02u, 0x3au, 0x8du, 0x88u, 0x87u, 0xd3u, 0x81u, 0x4fu, + 0xb6u, 0xceu, 0xb1u, 0x2cu, 0xf9u, 0x87u, 0x9cu, 0x49u, + 0xebu, 0xf2u, 0x16u, 0xd0u, 0x6cu, 0x32u, 0x2du, 0xa7u, + 0x72u, 0xb2u, 0xe5u, 0x1fu, 0x7au, 0x70u, 0xc1u, 0x30u, + 0x74u, 0x3au, 0xacu, 0xebu, 0x0cu, 0x81u, 0x01u, 0x6cu, + 0x55u, 0xe1u, 0x1cu, 0x7eu, 0x93u, 0x1fu, 0x1au, 0x28u, + 0xcau, 0xe9u, 0xe1u, 0x70u, 0xa9u, 0xf9u, 0x7bu, 0x2du, + 0xfcu, 0xc0u, 0xbfu, 0x3cu, 0x56u, 0xbdu, 0x8fu, 0xe1u, + 0xd3u, 0xa1u, 0xb4u, 0xe3u, 0xe5u, 0xd2u, 0xb2u, 0x51u, + 0x88u, 0xe9u, 0x9au, 0x90u, 0x19u, 0x33u, 0xb8u, 0xa6u, + 0xd4u, 0x55u, 0x3du, 0xcbu, 0xc3u, 0x0cu, 0xdbu, 0x27u, + 0xdcu, 0x86u, 0x55u, 0xe2u, 0x0du, 0x1du, 0x59u, 0xc5u, + 0xb4u, 0x23u, 0xcbu, 0xaau, 0xcau, 0x1bu, 0x7bu, 0x8au, + 0xe7u, 0x30u, 0x64u, 0xc8u, 0x42u, 0x28u, 0xd9u, 0xd3u, + 0xdbu, 0x6au, 0x54u, 0x7fu, 0x21u, 0x95u, 0x12u, 0x58u, + 0xf3u, 0xc9u, 0x98u, 0x54u, 0x1du, 0x6au, 0x15u, 0x96u + }; + + + +/** Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_NoEncode_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create session handle to be used by mcuxClRsa_sign */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, + MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE, + MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE); + + /* Initialize the PRNG */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Create key struct of type MCUXCLRSA_KEY_PRIVATEPLAIN */ + const mcuxClRsa_KeyEntry_t Mod1 = { + .pKeyEntryData = (uint8_t *)modulus, + .keyEntryLength = RSA_KEY_BYTE_LENGTH }; + + const mcuxClRsa_KeyEntry_t Exp1 = { + .pKeyEntryData = (uint8_t *)d, + .keyEntryLength = sizeof(d) }; + + const mcuxClRsa_Key private_key = { + .keytype = MCUXCLRSA_KEY_PRIVATEPLAIN, + .pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1, + .pMod2 = NULL, + .pQInv = NULL, + .pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1, + .pExp2 = NULL, + .pExp3 = NULL }; + + /* Prepare buffer to store the result */ + uint8_t signature[RSA_KEY_BYTE_LENGTH]; + + /**************************************************************************/ + /* RSA signature generation call */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_status, sign_token, mcuxClRsa_sign( + /* mcuxClSession_Handle_t pSession: */ session, + /* const mcuxClRsa_Key * const pKey: */ &private_key, + /* mcuxCl_InputBuffer_t pMessageOrDigest: */ message, + /* const uint32_t messageLength: */ RSA_KEY_BYTE_LENGTH, + /* const mcuxClRsa_SignVerifyMode pPaddingMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Sign_NoEncode, + /* const uint32_t saltLength: */ 0u, + /* uint32_t options: */ 0u, + /* mcuxCl_Buffer_t pSignature: */ signature)); + + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_sign) != sign_token || MCUXCLRSA_STATUS_SIGN_OK != sign_status) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification of the result */ + /**************************************************************************/ + for(size_t i = 0U; i < RSA_KEY_BYTE_LENGTH; i++) + { + if(referenceSignature[i] != signature[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c new file mode 100644 index 000000000..4861205e3 --- /dev/null +++ b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c @@ -0,0 +1,218 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_sign_pss_sha2_256_example.c + * @brief Example of using function mcuxClRsa_sign to perform the RSA signature generation with + * EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2. + * + * @example mcuxClRsa_sign_pss_sha2_256_example.c + * @brief Example of using function mcuxClRsa_sign to perform the RSA signature generation with + * EMSA-PSS-SIGN padding scheme according to PKCS #1 v2.2. + */ + +#include // Interface to the entire mcuxClSession component +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClRandom component +#include // Interface to the entire mcuxClRsa component +#include +#include // Interface to the entire mcuxClEls component +#include + +/**********************************************************/ +/* Example test vectors */ +/**********************************************************/ + +#define RSA_KEY_BIT_LENGTH (2048u) ///< The example uses a 2048-bit key +#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u) ///< Converting the key-bitlength to bytelength +#define RSA_MESSAGE_DIGEST_LENGTH (32u) ///< The example uses a Sha2-256 digest, which is 32 bytes long +#define RSA_PSS_SALT_LENGTH (0u) ///< The salt length is set to 0 in this example + +/** + * @brief Example value for public RSA modulus N. + */ +static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0xd3U, 0x24U, 0x96U, 0xe6U, 0x2dU, 0x16U, 0x34U, 0x6eU, 0x06U, 0xe7U, 0xa3U, 0x1cU, 0x12U, 0x0aU, 0x21U, 0xb5U, + 0x45U, 0x32U, 0x32U, 0x35U, 0xeeU, 0x1dU, 0x90U, 0x72U, 0x1dU, 0xceU, 0xaaU, 0xd4U, 0x6dU, 0xc4U, 0xceU, 0xbdU, + 0x80U, 0xc1U, 0x34U, 0x5aU, 0xffU, 0x95U, 0xb1U, 0xddU, 0xf8U, 0x71U, 0xebU, 0xb7U, 0xf2U, 0x0fU, 0xedU, 0xb6U, + 0xe4U, 0x2eU, 0x67U, 0xa0U, 0xccU, 0x59U, 0xb3U, 0x9fU, 0xfdU, 0x31U, 0xe9U, 0x83U, 0x42U, 0xf4U, 0x0aU, 0xd9U, + 0xafU, 0xf9U, 0x3cU, 0x3cU, 0x51U, 0xcfU, 0x5fU, 0x3cU, 0x8aU, 0xd0U, 0x64U, 0xb8U, 0x33U, 0xf9U, 0xacU, 0x34U, + 0x22U, 0x9aU, 0x3eU, 0xd3U, 0xddU, 0x29U, 0x41U, 0xbeU, 0x12U, 0x5bU, 0xc5U, 0xa2U, 0x0cU, 0xb6U, 0xd2U, 0x31U, + 0xb6U, 0xd1U, 0x84U, 0x7eU, 0xc4U, 0xfeU, 0xaeU, 0x2bU, 0x88U, 0x46U, 0xcfU, 0x00U, 0xc4U, 0xc6U, 0xe7U, 0x5aU, + 0x51U, 0x32U, 0x65U, 0x7aU, 0x68U, 0xecU, 0x04U, 0x38U, 0x36U, 0x46U, 0x34U, 0xeaU, 0xf8U, 0x27U, 0xf9U, 0xbbU, + 0x51U, 0x6cU, 0x93U, 0x27U, 0x48U, 0x1dU, 0x58U, 0xb8U, 0xffU, 0x1eU, 0xa4U, 0xc0U, 0x1fU, 0xa1U, 0xa2U, 0x57U, + 0xa9U, 0x4eU, 0xa6U, 0xd4U, 0x72U, 0x60U, 0x3bU, 0x3fU, 0xb3U, 0x24U, 0x53U, 0x22U, 0x88U, 0xeaU, 0x3aU, 0x97U, + 0x43U, 0x53U, 0x59U, 0x15U, 0x33U, 0xa0U, 0xebU, 0xbeU, 0xf2U, 0x9dU, 0xf4U, 0xf8U, 0xbcU, 0x4dU, 0xdbU, 0xf8U, + 0x8eU, 0x47U, 0x1fU, 0x1dU, 0xa5U, 0x00U, 0xb8U, 0xf5U, 0x7bU, 0xb8U, 0xc3U, 0x7cU, 0xa5U, 0xeaU, 0x17U, 0x7cU, + 0x4eU, 0x8aU, 0x39U, 0x06U, 0xb7U, 0xc1U, 0x42U, 0xf7U, 0x78U, 0x8cU, 0x45U, 0xeaU, 0xd0U, 0xc9U, 0xbcU, 0x36U, + 0x92U, 0x48U, 0x3aU, 0xd8U, 0x13U, 0x61U, 0x11U, 0x45U, 0xb4U, 0x1fU, 0x9cU, 0x01U, 0x2eU, 0xf2U, 0x87U, 0xbeU, + 0x8bU, 0xbfU, 0x93U, 0x19U, 0xcfU, 0x4bU, 0x91U, 0x84U, 0xdcU, 0x8eU, 0xffU, 0x83U, 0x58U, 0x9bU, 0xe9U, 0x0cU, + 0x54U, 0x81U, 0x14U, 0xacU, 0xfaU, 0x5aU, 0xbfU, 0x79U, 0x54U, 0xbfU, 0x9fU, 0x7aU, 0xe5U, 0xb4U, 0x38U, 0xb5U + }; + +/** + * @brief Example value for private RSA exponent d. + */ +static const uint8_t exponent[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x15U, 0x5fU, 0xe6U, 0x60U, 0xcdU, 0xdeU, 0xaaU, 0x17U, 0x1bU, 0x5eU, 0xd6U, 0xbdU, 0xd0U, 0x3bU, 0xb3U, 0x56U, + 0xe0U, 0xf6U, 0xe8U, 0x6bU, 0x5aU, 0x3cU, 0x26U, 0xf3U, 0xceU, 0x7dU, 0xaeU, 0x00U, 0x8cU, 0x4eU, 0x38U, 0xa9U, + 0xa9U, 0x7fU, 0xa5U, 0x97U, 0xb2U, 0xb9U, 0x0aU, 0x45U, 0x10U, 0xd2U, 0x23U, 0x8dU, 0x3fU, 0x15U, 0x8aU, 0xb8U, + 0x91U, 0x97U, 0xfbU, 0x08U, 0xa5U, 0xb7U, 0x4cU, 0xfeU, 0x5cU, 0xc8U, 0xf1U, 0x3dU, 0x47U, 0x09U, 0x62U, 0x91U, + 0xd0U, 0x05U, 0x38U, 0xaaU, 0x58U, 0x93U, 0xd8U, 0x2dU, 0xceU, 0x55U, 0xb3U, 0x64U, 0x8cU, 0x6aU, 0x71U, 0x9aU, + 0xe3U, 0x87U, 0xdeU, 0xe5U, 0x5eU, 0xc5U, 0xbeU, 0xf0U, 0x89U, 0x76U, 0x3dU, 0xe7U, 0x1eU, 0x47U, 0x61U, 0xb7U, + 0x03U, 0xadU, 0x69U, 0x2eU, 0xd6U, 0x2dU, 0x7cU, 0x1fU, 0x4fU, 0x0fU, 0xf0U, 0x03U, 0xc1U, 0x67U, 0xebU, 0x62U, + 0xd2U, 0xc6U, 0x79U, 0xccU, 0x6fU, 0x13U, 0xb9U, 0x87U, 0xa1U, 0x42U, 0xf1U, 0x37U, 0x7aU, 0x40U, 0xbdU, 0xc0U, + 0xa0U, 0x36U, 0x60U, 0x72U, 0x94U, 0x40U, 0x14U, 0x63U, 0xa3U, 0x0eU, 0x82U, 0x91U, 0x2bU, 0x42U, 0x8aU, 0x1dU, + 0x3fU, 0x80U, 0xb5U, 0xd0U, 0xd3U, 0x3eU, 0xa8U, 0x4eU, 0x8bU, 0xb6U, 0x4cU, 0x36U, 0x22U, 0xb9U, 0xbeU, 0xe3U, + 0x56U, 0xf1U, 0x2cU, 0x6aU, 0x19U, 0x0eU, 0x55U, 0x7bU, 0xbfU, 0x25U, 0xe1U, 0x10U, 0x80U, 0x7bU, 0x85U, 0xcaU, + 0xd5U, 0x1bU, 0x39U, 0x87U, 0x57U, 0x08U, 0x06U, 0xbeU, 0x81U, 0xf3U, 0x71U, 0x3fU, 0x5dU, 0x17U, 0x40U, 0x74U, + 0x99U, 0xa5U, 0xdeU, 0xdaU, 0xc0U, 0xf3U, 0xe3U, 0xbcU, 0x79U, 0x96U, 0x35U, 0x95U, 0xf8U, 0xe0U, 0xcfU, 0x01U, + 0x29U, 0x1dU, 0xc1U, 0x02U, 0x09U, 0xc0U, 0x6eU, 0xb6U, 0x0eU, 0x2eU, 0x9cU, 0x47U, 0xecU, 0x91U, 0x42U, 0xedU, + 0xa5U, 0xf3U, 0xb7U, 0x0aU, 0xc6U, 0x7fU, 0x72U, 0xbfU, 0x52U, 0xb3U, 0x31U, 0x37U, 0xd1U, 0x49U, 0xb6U, 0xf6U, + 0x06U, 0xe4U, 0x59U, 0x61U, 0x7dU, 0xaaU, 0x8eU, 0x10U, 0x18U, 0xa8U, 0x14U, 0x1dU, 0x89U, 0x4eU, 0xcaU, 0xffU +}; + +/** + * @brief Example value for Sha2-256 message digest. + */ +static const uint8_t message[RSA_MESSAGE_DIGEST_LENGTH] __attribute__ ((aligned (4))) = { + 0xf4U, 0x45U, 0x80U, 0x1eU, 0x0cU, 0xb8U, 0x99U, 0x26U, 0x2cU, 0x9bU, 0x9eU, 0x21U, 0x98U, 0x36U, 0x88U, 0x0dU, + 0x73U, 0xcaU, 0x2dU, 0x1bU, 0x0bU, 0x9cU, 0x15U, 0xfbU, 0x95U, 0x9cU, 0x90U, 0xebU, 0x12U, 0x12U, 0x34U, 0xe3U +}; + +/** + * @brief Expected signature + */ +static const uint8_t referenceSignature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x89U, 0x01U, 0x41U, 0x9fU, 0x26U, 0x14U, 0xc9U, 0x42U, 0xc9U, 0xeeU, 0x5eU, 0xfbU, 0xdfU, 0xbaU, 0x0cU, 0xcaU, + 0x70U, 0x6bU, 0x3aU, 0x4eU, 0xd1U, 0xa8U, 0x5fU, 0x69U, 0x28U, 0xb7U, 0x60U, 0xffU, 0x1bU, 0xbaU, 0xb0U, 0xe7U, + 0xb0U, 0x4cU, 0xbdU, 0xe6U, 0xb5U, 0x9fU, 0xc8U, 0x44U, 0x4fU, 0x4eU, 0xd1U, 0x0bU, 0xceU, 0xbeU, 0x30U, 0x75U, + 0x47U, 0xb4U, 0xc6U, 0x34U, 0x35U, 0xd9U, 0xaaU, 0x4fU, 0x7dU, 0xf9U, 0x37U, 0x97U, 0xf6U, 0x27U, 0x0aU, 0x20U, + 0x23U, 0x8aU, 0x42U, 0x36U, 0xb1U, 0x6fU, 0x47U, 0x72U, 0xb9U, 0x02U, 0x2fU, 0xadU, 0x11U, 0x9cU, 0x54U, 0x38U, + 0xd7U, 0x08U, 0x17U, 0x45U, 0xe2U, 0xa7U, 0xe3U, 0x2bU, 0x55U, 0x63U, 0x0eU, 0x37U, 0x49U, 0xabU, 0x51U, 0x05U, + 0x3eU, 0x1cU, 0x9cU, 0x77U, 0xf6U, 0x77U, 0xddU, 0x12U, 0x92U, 0x96U, 0x19U, 0xe7U, 0x80U, 0x22U, 0xbdU, 0xfdU, + 0xcbU, 0x4bU, 0x8dU, 0x4eU, 0x47U, 0xbcU, 0x80U, 0xacU, 0x91U, 0xcfU, 0xe7U, 0x5fU, 0x11U, 0x91U, 0xa7U, 0x2dU, + 0xfdU, 0x61U, 0x88U, 0xfdU, 0x28U, 0x9cU, 0xd5U, 0xb3U, 0x44U, 0xd4U, 0x33U, 0x4fU, 0xc1U, 0x5bU, 0xa7U, 0x64U, + 0x1dU, 0xf6U, 0x9fU, 0xc5U, 0x73U, 0xa7U, 0x2fU, 0x08U, 0x46U, 0xd5U, 0x32U, 0x7eU, 0x24U, 0x03U, 0x17U, 0xc6U, + 0x8eU, 0x02U, 0xbfU, 0x5dU, 0xe0U, 0x8cU, 0x40U, 0xbeU, 0x7eU, 0x2cU, 0xc1U, 0xa4U, 0x04U, 0xc0U, 0x6bU, 0xbfU, + 0x56U, 0xf3U, 0x09U, 0x5aU, 0x8cU, 0x34U, 0x8fU, 0x7bU, 0x50U, 0xabU, 0x65U, 0x48U, 0x02U, 0x11U, 0x02U, 0x4bU, + 0xacU, 0x3cU, 0xa5U, 0x93U, 0xa5U, 0xd4U, 0x4aU, 0x7dU, 0xa7U, 0xb8U, 0x69U, 0x6eU, 0xb6U, 0xe2U, 0xa1U, 0xd2U, + 0xfcU, 0xa1U, 0x89U, 0x44U, 0x50U, 0xc9U, 0x01U, 0x5eU, 0xbdU, 0xafU, 0x25U, 0xadU, 0xd0U, 0x0cU, 0xb4U, 0x4fU, + 0xb3U, 0x99U, 0x44U, 0x28U, 0xb2U, 0x45U, 0x1cU, 0x92U, 0x6bU, 0xbfU, 0xfcU, 0xfdU, 0x72U, 0xecU, 0x44U, 0xdaU, + 0xaaU, 0xdaU, 0x65U, 0x19U, 0xc3U, 0x41U, 0x46U, 0xb6U, 0x01U, 0x67U, 0xdeU, 0x98U, 0xd8U, 0x1bU, 0x15U, 0x94U +}; + + +/** Performs a session set-up; a call to function mcuxClRsa_sign using mode mcuxClRsa_Mode_Sign_Pss_Sha2_256; a session clean-up + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_sign_pss_sha2_256_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create session handle to be used by mcuxClRsa_sign */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, + MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE, + MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE); + + /* Initialize the PRNG */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Create key struct of type MCUXCLRSA_KEY_PRIVATEPLAIN */ + const mcuxClRsa_KeyEntry_t Mod1 = { + .pKeyEntryData = (uint8_t *)modulus, + .keyEntryLength = RSA_KEY_BYTE_LENGTH }; + + const mcuxClRsa_KeyEntry_t Exp1 = { + .pKeyEntryData = (uint8_t *)exponent, + .keyEntryLength = sizeof(exponent) }; + + const mcuxClRsa_Key private_key = { + .keytype = MCUXCLRSA_KEY_PRIVATEPLAIN, + .pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1, + .pMod2 = NULL, + .pQInv = NULL, + .pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1, + .pExp2 = NULL, + .pExp3 = NULL }; + + + /* Prepare buffer to store the result */ + uint8_t signature[RSA_KEY_BYTE_LENGTH]; + + /**************************************************************************/ + /* RSA signature generation call */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(sign_result, sign_token, mcuxClRsa_sign( + /* mcuxClSession_Handle_t pSession: */ session, + /* const mcuxClRsa_Key * const pKey: */ &private_key, + /* mcuxCl_InputBuffer_t pMessageOrDigest: */ message, + /* const uint32_t messageLength: */ RSA_MESSAGE_DIGEST_LENGTH, + /* const mcuxClRsa_SignVerifyMode pPaddingMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Sign_Pss_Sha2_256, + /* const uint32_t saltLength: */ RSA_PSS_SALT_LENGTH, + /* uint32_t options: */ MCUXCLRSA_OPTION_MESSAGE_DIGEST, + /* mcuxCl_Buffer_t pSignature: */ signature)); + + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_sign) != sign_token || MCUXCLRSA_STATUS_SIGN_OK != sign_result) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Verification of the result */ + /**************************************************************************/ + for(size_t i = 0U; i < RSA_KEY_BYTE_LENGTH; i++) + { + if(referenceSignature[i] != signature[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c new file mode 100644 index 000000000..30425b0d1 --- /dev/null +++ b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c @@ -0,0 +1,221 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_verify_NoVerify_example.c + * @brief Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 + * (public exponentiation and NO padding verification) according to PKCS #1 v2.2. + * + * @example mcuxClRsa_verify_NoVerify_example.c + * @brief Example of using function mcuxClRsa_verify to perform the RSA signature verification primitive RSAVP1 + * (public exponentiation and NO padding verification) according to PKCS #1 v2.2. + */ + +#include // Interface to the entire mcuxClSession component +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClRandom component +#include // Interface to the entire mcuxClRsa component +#include // Memory segment definitions +#include +#include // Interface to the entire mcuxClEls component +#include + +/**********************************************************/ +/* Example test vectors */ +/**********************************************************/ + +#define RSA_KEY_BIT_LENGTH (2048u) ///< The example uses a 2048-bit key +#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u) ///< Converting the key-bitlength to bytelength + + +/** + * @brief Example value for public RSA modulus N. + */ +static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0xbau,0xd4u,0x7au,0x84u,0xc1u,0x78u,0x2eu,0x4du,0xbdu,0xd9u,0x13u,0xf2u,0xa2u,0x61u,0xfcu,0x8bu, + 0x65u,0x83u,0x84u,0x12u,0xc6u,0xe4u,0x5au,0x20u,0x68u,0xedu,0x6du,0x7fu,0x16u,0xe9u,0xcdu,0xf4u, + 0x46u,0x2bu,0x39u,0x11u,0x95u,0x63u,0xcau,0xfbu,0x74u,0xb9u,0xcbu,0xf2u,0x5cu,0xfdu,0x54u,0x4bu, + 0xdau,0xe2u,0x3bu,0xffu,0x0eu,0xbeu,0x7fu,0x64u,0x41u,0x04u,0x2bu,0x7eu,0x10u,0x9bu,0x9au,0x8au, + 0xfau,0xa0u,0x56u,0x82u,0x1eu,0xf8u,0xefu,0xaau,0xb2u,0x19u,0xd2u,0x1du,0x67u,0x63u,0x48u,0x47u, + 0x85u,0x62u,0x2du,0x91u,0x8du,0x39u,0x5au,0x2au,0x31u,0xf2u,0xecu,0xe8u,0x38u,0x5au,0x81u,0x31u, + 0xe5u,0xffu,0x14u,0x33u,0x14u,0xa8u,0x2eu,0x21u,0xafu,0xd7u,0x13u,0xbau,0xe8u,0x17u,0xccu,0x0eu, + 0xe3u,0x51u,0x4du,0x48u,0x39u,0x00u,0x7cu,0xcbu,0x55u,0xd6u,0x84u,0x09u,0xc9u,0x7au,0x18u,0xabu, + 0x62u,0xfau,0x6fu,0x9fu,0x89u,0xb3u,0xf9u,0x4au,0x27u,0x77u,0xc4u,0x7du,0x61u,0x36u,0x77u,0x5au, + 0x56u,0xa9u,0xa0u,0x12u,0x7fu,0x68u,0x24u,0x70u,0xbeu,0xf8u,0x31u,0xfbu,0xecu,0x4bu,0xcdu,0x7bu, + 0x50u,0x95u,0xa7u,0x82u,0x3fu,0xd7u,0x07u,0x45u,0xd3u,0x7du,0x1bu,0xf7u,0x2bu,0x63u,0xc4u,0xb1u, + 0xb4u,0xa3u,0xd0u,0x58u,0x1eu,0x74u,0xbfu,0x9au,0xdeu,0x93u,0xccu,0x46u,0x14u,0x86u,0x17u,0x55u, + 0x39u,0x31u,0xa7u,0x9du,0x92u,0xe9u,0xe4u,0x88u,0xefu,0x47u,0x22u,0x3eu,0xe6u,0xf6u,0xc0u,0x61u, + 0x88u,0x4bu,0x13u,0xc9u,0x06u,0x5bu,0x59u,0x11u,0x39u,0xdeu,0x13u,0xc1u,0xeau,0x29u,0x27u,0x49u, + 0x1eu,0xd0u,0x0fu,0xb7u,0x93u,0xcdu,0x68u,0xf4u,0x63u,0xf5u,0xf6u,0x4bu,0xaau,0x53u,0x91u,0x6bu, + 0x46u,0xc8u,0x18u,0xabu,0x99u,0x70u,0x65u,0x57u,0xa1u,0xc2u,0xd5u,0x0du,0x23u,0x25u,0x77u,0xd1u + }; + +/** + * @brief Example value for public RSA exponent e. + */ +static const uint8_t exponent[3] __attribute__ ((aligned (4))) = { + 0x01u, 0x00u, 0x01u +}; + +/** + * @brief Example value for RSA signature s. + */ +static const uint8_t signature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x7eu,0x65u,0xb9u,0x98u,0xa0u,0x5fu,0x62u,0x6bu,0x02u,0x8cu,0x75u,0xdcu,0x3fu,0xbfu,0x98u,0x96u, + 0x3du,0xceu,0x66u,0xd0u,0xf4u,0xc3u,0xaeu,0x42u,0x37u,0xcfu,0xf3u,0x04u,0xd8u,0x4du,0x88u,0x36u, + 0xcbu,0x6bu,0xadu,0x9au,0xc8u,0x6fu,0x9du,0x1bu,0x8au,0x28u,0xddu,0x70u,0x40u,0x47u,0x88u,0xb8u, + 0x69u,0xd2u,0x42u,0x9fu,0x1eu,0xc0u,0x66u,0x3eu,0x51u,0xb7u,0x53u,0xf7u,0x45u,0x1cu,0x6bu,0x46u, + 0x45u,0xd9u,0x91u,0x26u,0xe4u,0x57u,0xc1u,0xdau,0xc4u,0x95u,0x51u,0xd8u,0x6au,0x8au,0x97u,0x4au, + 0x31u,0x31u,0xe9u,0xb3u,0x71u,0xd5u,0xc2u,0x14u,0xccu,0x9fu,0xf2u,0x40u,0xc2u,0x99u,0xbdu,0x0eu, + 0x62u,0xdbu,0xc7u,0xa9u,0xa2u,0xdau,0xd9u,0xfau,0x54u,0x04u,0xadu,0xb0u,0x06u,0x32u,0xd3u,0x63u, + 0x32u,0xd5u,0xbeu,0x61u,0x06u,0xe9u,0xe6u,0xecu,0x81u,0xcau,0xc4u,0x5cu,0xd3u,0x39u,0xccu,0x87u, + 0xabu,0xbeu,0x7fu,0x89u,0x43u,0x08u,0x00u,0xe1u,0x6eu,0x03u,0x2au,0x66u,0x21u,0x0bu,0x25u,0xe9u, + 0x26u,0xedu,0xa2u,0x43u,0xd9u,0xf0u,0x99u,0x55u,0x49u,0x6du,0xdbu,0xc7u,0x7eu,0xf7u,0x4fu,0x17u, + 0xfeu,0xe4u,0x1cu,0x44u,0x35u,0xe7u,0x8bu,0x46u,0x96u,0x5bu,0x71u,0x3du,0x72u,0xceu,0x8au,0x31u, + 0xafu,0x64u,0x15u,0x38u,0xadu,0xd3u,0x87u,0xfeu,0xdfu,0xd8u,0x8bu,0xb2u,0x2au,0x42u,0xebu,0x3bu, + 0xdau,0x40u,0xf7u,0x2eu,0xcau,0xd9u,0x41u,0xdbu,0xffu,0xddu,0x47u,0xb3u,0xe7u,0x77u,0x37u,0xdau, + 0x74u,0x15u,0x53u,0xa4u,0x5bu,0x63u,0x0du,0x07u,0x0bu,0xccu,0x52u,0x05u,0x80u,0x4bu,0xf8u,0x0eu, + 0xe2u,0xd5u,0x16u,0x12u,0x87u,0x5du,0xbcu,0x47u,0x96u,0x96u,0x00u,0x52u,0xf1u,0x68u,0x7eu,0x00u, + 0x74u,0x00u,0x7eu,0x6au,0x33u,0xabu,0x8bu,0x20u,0x85u,0xc0u,0x33u,0xf9u,0x89u,0x2bu,0x6fu,0x74u +}; + +/** + * @brief Reference output when calling mcuxClRsa_verify on signature s using the RSA public key pair (N,e) + * and choosing mode mcuxClRsa_Mode_Verify_NoVerify. + */ +static const uint8_t reference_result[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x70u,0x99u,0x2cu,0x9du,0x95u,0xa4u,0x90u,0x8du,0x2au,0x94u,0xb3u,0xabu,0x9fu,0xa1u,0xcdu,0x64u, + 0x3fu,0x12u,0x0eu,0x32u,0x6fu,0x9du,0x78u,0x08u,0xafu,0x50u,0xcau,0xc4u,0x2cu,0x4bu,0x0bu,0x4eu, + 0xebu,0x7fu,0x0du,0x4du,0xf3u,0x03u,0xa5u,0x68u,0xfbu,0xfbu,0x82u,0xb0u,0xf5u,0x83u,0x00u,0xd2u, + 0x53u,0x57u,0x64u,0x57u,0x21u,0xbbu,0x71u,0x86u,0x1cu,0xafu,0x81u,0xb2u,0x7au,0x56u,0x08u,0x2cu, + 0x80u,0xa1u,0x46u,0x49u,0x9fu,0xb4u,0xeau,0xb5u,0xbdu,0xe4u,0x49u,0x3fu,0x5du,0x00u,0xf1u,0xa4u, + 0x37u,0xbbu,0xc3u,0x60u,0xdfu,0xcdu,0x80u,0x56u,0xfeu,0x6bu,0xe1u,0x0eu,0x60u,0x8au,0xdbu,0x30u, + 0xb6u,0xc2u,0xf7u,0x65u,0x24u,0x28u,0xb8u,0xd3u,0x2du,0x36u,0x29u,0x45u,0x98u,0x2au,0x46u,0x58u, + 0x5du,0x21u,0x02u,0xefu,0x79u,0x95u,0xa8u,0xbau,0x6eu,0x8au,0xd8u,0xfdu,0x16u,0xbdu,0x7au,0xe8u, + 0xf5u,0x3cu,0x3du,0x7fu,0xcfu,0xbau,0x29u,0x0bu,0x57u,0xceu,0x7fu,0x8fu,0x09u,0xc8u,0x28u,0xd6u, + 0xf2u,0xd3u,0xceu,0x56u,0xf1u,0x31u,0xbdu,0x94u,0x61u,0xe5u,0x66u,0x7eu,0x5bu,0x73u,0xedu,0xacu, + 0x77u,0xf5u,0x04u,0xdau,0xc4u,0xf2u,0x02u,0xa9u,0x57u,0x0eu,0xb4u,0x51u,0x5bu,0x2bu,0xf5u,0x16u, + 0x40u,0x7du,0xb8u,0x31u,0x51u,0x8du,0xb8u,0xa2u,0x08u,0x3eu,0xc7u,0x01u,0xe8u,0xfdu,0x38u,0x7cu, + 0x43u,0x0bu,0xb1u,0xa7u,0x2du,0xecu,0xa5u,0xb4u,0x9du,0x42u,0x9cu,0xf9u,0xdeu,0xb0u,0x9cu,0xc4u, + 0x51u,0x8du,0xc5u,0xf5u,0x7cu,0x08u,0x9au,0xa2u,0xd3u,0x42u,0x0eu,0x56u,0x7eu,0x73u,0x21u,0x02u, + 0xc2u,0xc9u,0x2bu,0x88u,0xa0u,0x7cu,0x69u,0xd7u,0x09u,0x17u,0x14u,0x0au,0xb3u,0x82u,0x3cu,0x63u, + 0xf3u,0x12u,0xd3u,0xf1u,0x1fu,0xa8u,0x7bu,0xa2u,0x9du,0xa3u,0xc7u,0x22u,0x4bu,0x4fu,0xb4u,0xbcu +}; + + +/** Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_NoVerify; a session clean-up + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_NoVerify_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create session handle to be used by verify function */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, + MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE, + MCUXCLRSA_VERIFY_2048_WAPKC_SIZE); + + /* Initialize the PRNG */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Create key struct of type MCUXCLRSA_KEY_PUBLIC */ + const mcuxClRsa_KeyEntry_t Mod1 = { + .pKeyEntryData = (uint8_t *)modulus, + .keyEntryLength = RSA_KEY_BYTE_LENGTH }; + + const mcuxClRsa_KeyEntry_t Exp1 = { + .pKeyEntryData = (uint8_t *)exponent, + .keyEntryLength = 3U }; + + const mcuxClRsa_Key public_key = { + .keytype = MCUXCLRSA_KEY_PUBLIC, + .pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1, + .pMod2 = NULL, + .pQInv = NULL, + .pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1, + .pExp2 = NULL, + .pExp3 = NULL }; + + /* Prepare buffer to store the result */ + uint8_t encodedMessag[RSA_KEY_BYTE_LENGTH]; + + /**************************************************************************/ + /* RSA verification call */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClRsa_verify( + /* mcuxClSession_Handle_t pSession: */ session, + /* const mcuxClRsa_Key * const pKey: */ &public_key, + /* mcuxCl_InputBuffer_t pMessageOrDigest: */ NULL, + /* const uint32_t messageLength: */ 0u, + /* mcuxCl_Buffer_t pSignature: */ (uint8_t *)signature, + /* const mcuxClRsa_SignVerifyMode pVerifyMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Verify_NoVerify, + /* const uint32_t saltLength: */ 0u, + /* uint32_t options: */ 0u, + /* mcuxCl_Buffer_t pOutput: */ encodedMessag)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_verify) != verify_token) || (MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /**************************************************************************/ + /* Verification of the result */ + /**************************************************************************/ + for (size_t i = 0U; i < sizeof(encodedMessag); i++) + { + if (reference_result[i] != encodedMessag[i]) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + } + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_pssverify_sha2_256_example.c b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_pssverify_sha2_256_example.c new file mode 100644 index 000000000..6b552de24 --- /dev/null +++ b/components/els_pkc/examples/mcuxClRsa/mcuxClRsa_verify_pssverify_sha2_256_example.c @@ -0,0 +1,194 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_verify_pssverify_sha2_256_example.c + * @brief Example of using function mcuxClRsa_verify to perform the RSA signature verification with + * EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2. + * + * @example mcuxClRsa_verify_pssverify_sha2_256_example.c + * @brief Example of using function mcuxClRsa_verify to perform the RSA signature verification with + * EMSA-PSS-VERIFY padding scheme according to PKCS #1 v2.2. + */ + +#include // Interface to the entire mcuxClSession component +#include +#include +#include // Code flow protection +#include // Interface to the entire mcuxClRandom component +#include // Interface to the entire mcuxClRsa component +#include // Memory segment definitions +#include +#include // Interface to the entire mcuxClEls component +#include + +/**********************************************************/ +/* Example test vectors */ +/**********************************************************/ + +#define RSA_KEY_BIT_LENGTH (2048u) ///< The example uses a 2048-bit key +#define RSA_KEY_BYTE_LENGTH (RSA_KEY_BIT_LENGTH / 8u) ///< Converting the key-bitlength to bytelength +#define RSA_PUBLIC_EXP_BYTE_LENGTH (3u) ///< The public exponent has a length of three bytes +#define RSA_MESSAGE_DIGEST_LENGTH (32u) ///< The example uses a Sha2-256 digest, which is 32 bytes long +#define RSA_PSS_SALT_LENGTH (32u) ///< The salt for the PSS padding is 32 bytes long + +/** + * @brief Example value for public RSA modulus N. + */ +static const uint8_t modulus[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0xb4u, 0xbfu, 0xc5u, 0xdeu, 0x4au, 0x63u, 0xe3u, 0xe2u, 0x58u, 0x1cu, 0x43u, 0x91u, 0xeau, 0x42u, 0x31u, 0x1au, + 0x86u, 0xc3u, 0xddu, 0x71u, 0x8au, 0xa2u, 0x56u, 0xd2u, 0xdcu, 0xedu, 0xecu, 0x81u, 0x1cu, 0xebu, 0x6cu, 0xeeu, + 0x54u, 0xe1u, 0x39u, 0xb2u, 0x53u, 0x34u, 0x5du, 0x4bu, 0xc5u, 0x37u, 0x0eu, 0xe9u, 0xcfu, 0xe3u, 0x93u, 0x47u, + 0xdau, 0x6bu, 0x3du, 0x72u, 0x95u, 0xecu, 0xeeu, 0x13u, 0x9fu, 0xd0u, 0x00u, 0x06u, 0x57u, 0x29u, 0xe3u, 0xd2u, + 0xc5u, 0x93u, 0x31u, 0x79u, 0x55u, 0x94u, 0x8cu, 0x3eu, 0xf1u, 0xfdu, 0x82u, 0xf1u, 0x26u, 0xf0u, 0x5bu, 0x28u, + 0xc2u, 0x72u, 0x22u, 0x67u, 0x3au, 0x36u, 0x9cu, 0xf5u, 0x1fu, 0xb5u, 0xeeu, 0xc0u, 0x06u, 0x86u, 0xbbu, 0x3cu, + 0xcdu, 0xbcu, 0x92u, 0x6fu, 0x82u, 0x08u, 0x7eu, 0xa8u, 0x05u, 0xd4u, 0xecu, 0xccu, 0xbcu, 0xacu, 0x68u, 0x19u, + 0x7fu, 0x2du, 0x5cu, 0x2du, 0xe1u, 0x86u, 0xfdu, 0xa1u, 0xf6u, 0xffu, 0x8du, 0xa3u, 0x03u, 0x4fu, 0x71u, 0xe7u, + 0x99u, 0x50u, 0xb9u, 0x69u, 0x7cu, 0xa4u, 0x10u, 0xcdu, 0xbeu, 0xbfu, 0x68u, 0xb6u, 0x5bu, 0xacu, 0xfbu, 0x74u, + 0xe1u, 0x8du, 0x58u, 0x33u, 0x07u, 0x8eu, 0xcdu, 0x46u, 0x34u, 0x9au, 0xd8u, 0x49u, 0xb5u, 0x58u, 0x4bu, 0xceu, + 0x2bu, 0xa2u, 0x0au, 0x77u, 0x46u, 0xdau, 0x8cu, 0xfbu, 0x7eu, 0xd7u, 0xc7u, 0xddu, 0xffu, 0x9eu, 0x10u, 0x43u, + 0xb8u, 0xfeu, 0x67u, 0x95u, 0xe4u, 0x0fu, 0x68u, 0x47u, 0xd3u, 0xc2u, 0x11u, 0x83u, 0xbbu, 0x53u, 0x0du, 0xc5u, + 0x4du, 0x8eu, 0x75u, 0x53u, 0x86u, 0xe5u, 0x90u, 0xffu, 0x7fu, 0x7au, 0x47u, 0x17u, 0x7au, 0x69u, 0x13u, 0x52u, + 0xb6u, 0xa7u, 0xf0u, 0xceu, 0x48u, 0x9eu, 0x83u, 0xecu, 0x43u, 0xfdu, 0x05u, 0xd6u, 0xe4u, 0xbcu, 0xd5u, 0x1au, + 0x90u, 0xc2u, 0x4bu, 0xfdu, 0x38u, 0xd3u, 0xf7u, 0x66u, 0x6du, 0x2au, 0xccu, 0x5bu, 0x5fu, 0xc5u, 0x67u, 0x0cu, + 0x3eu, 0xe8u, 0xc8u, 0xbeu, 0xb9u, 0x2fu, 0xa4u, 0x8au, 0xb6u, 0x5du, 0x5fu, 0xecu, 0xfeu, 0xf3u, 0x2eu, 0xd7u, + }; + +/** + * @brief Example value for public RSA exponent e. + */ +static const uint8_t exponent[RSA_PUBLIC_EXP_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x01u, 0x00u, 0x01u +}; + +/** + * @brief Example value for Sha2-256 message digest. + */ +static const uint8_t message[RSA_MESSAGE_DIGEST_LENGTH] __attribute__ ((aligned (4))) = { + 0x9fu, 0x86u, 0xd0u, 0x81u, 0x88u, 0x4cu, 0x7du, 0x65u, 0x9au, 0x2fu, 0xeau, 0xa0u, 0xc5u, 0x5au, 0xd0u, 0x15u, + 0xa3u, 0xbfu, 0x4fu, 0x1bu, 0x2bu, 0x0bu, 0x82u, 0x2cu, 0xd1u, 0x5du, 0x6cu, 0x15u, 0xb0u, 0xf0u, 0x0au, 0x08u, +}; + +/** + * @brief Example value for RSA signature s. + */ +static const uint8_t signature[RSA_KEY_BYTE_LENGTH] __attribute__ ((aligned (4))) = { + 0x5eu, 0xa5u, 0x03u, 0x94u, 0x3cu, 0x28u, 0xbcu, 0x90u, 0x66u, 0xb6u, 0xedu, 0x45u, 0x00u, 0x79u, 0x0fu, 0x85u, + 0x23u, 0xf5u, 0x6bu, 0x20u, 0x7du, 0x55u, 0x6fu, 0x0fu, 0x28u, 0x5fu, 0x2du, 0xdbu, 0x85u, 0xe7u, 0x8eu, 0x7bu, + 0x42u, 0xbau, 0x10u, 0x79u, 0xc0u, 0x16u, 0xd2u, 0x01u, 0x21u, 0x6bu, 0xc6u, 0x4cu, 0x57u, 0x0au, 0x4eu, 0x85u, + 0x2au, 0x89u, 0xdeu, 0x4bu, 0xccu, 0xb3u, 0xa0u, 0xdcu, 0x35u, 0xe9u, 0xf7u, 0xfeu, 0xe8u, 0xe9u, 0x2cu, 0xfeu, + 0x20u, 0x96u, 0x04u, 0x5fu, 0x46u, 0x09u, 0xb5u, 0xb7u, 0x1eu, 0xf9u, 0xcdu, 0x73u, 0x05u, 0xf8u, 0xe8u, 0xdeu, + 0x2cu, 0x17u, 0x50u, 0xd1u, 0xd5u, 0x66u, 0x4fu, 0xa2u, 0x9au, 0x26u, 0x28u, 0xd9u, 0x66u, 0x7fu, 0x87u, 0x80u, + 0x69u, 0x34u, 0x3du, 0xd3u, 0xdbu, 0x06u, 0xe5u, 0x7cu, 0x3cu, 0xf3u, 0x4au, 0x3fu, 0xb7u, 0x97u, 0x90u, 0x4fu, + 0x72u, 0x92u, 0x54u, 0xa0u, 0x9cu, 0x2fu, 0x29u, 0x94u, 0x65u, 0xa0u, 0xd6u, 0xafu, 0x9bu, 0xcau, 0xa6u, 0x0fu, + 0x90u, 0x45u, 0x79u, 0x36u, 0x00u, 0xeau, 0x08u, 0xb2u, 0x0du, 0x8cu, 0xe7u, 0xefu, 0x08u, 0x95u, 0x61u, 0xf3u, + 0x79u, 0x54u, 0xd7u, 0xb6u, 0x22u, 0x01u, 0x46u, 0x41u, 0xb0u, 0xadu, 0xf1u, 0x03u, 0x0cu, 0x00u, 0xdcu, 0xb9u, + 0x33u, 0x3du, 0x1cu, 0xe1u, 0x16u, 0xd6u, 0xd9u, 0x4au, 0x16u, 0x9cu, 0x51u, 0x12u, 0x22u, 0x54u, 0x15u, 0xe0u, + 0xefu, 0x2au, 0xb9u, 0xeeu, 0x3cu, 0x2cu, 0xe8u, 0x5eu, 0xaau, 0x58u, 0x26u, 0x0cu, 0xeeu, 0x4bu, 0x34u, 0x94u, + 0x53u, 0xc9u, 0x97u, 0x50u, 0xceu, 0xb4u, 0xd1u, 0xceu, 0x38u, 0xbfu, 0xe4u, 0x5cu, 0x5du, 0x24u, 0x00u, 0xceu, + 0xfau, 0x8au, 0xbau, 0x42u, 0xeau, 0xa8u, 0x4fu, 0x7du, 0xa2u, 0x37u, 0x17u, 0x7eu, 0x62u, 0xe7u, 0x60u, 0x2cu, + 0x01u, 0x97u, 0x68u, 0x26u, 0xb6u, 0xf0u, 0x8bu, 0xe6u, 0x4eu, 0xa6u, 0xb2u, 0x4fu, 0x0eu, 0x11u, 0x3cu, 0x93u, + 0x5eu, 0xcdu, 0x35u, 0x70u, 0x82u, 0x63u, 0xadu, 0x5fu, 0x3cu, 0x6au, 0x51u, 0x9fu, 0x5eu, 0xd5u, 0xbau, 0xf6u, +}; + + + +/** Performs a session set-up; a call to function mcuxClRsa_verify using mode mcuxClRsa_Mode_Verify_Pss_Sha2_256; a session clean-up + * @retval MCUXCLEXAMPLE_STATUS_OK The example code completed successfully + * @retval MCUXCLEXAMPLE_STATUS_ERROR The example code failed */ +MCUXCLEXAMPLE_FUNCTION(mcuxClRsa_verify_pssverify_sha2_256_example) +{ + /**************************************************************************/ + /* Preparation */ + /**************************************************************************/ + + /** Initialize ELS, Enable the ELS **/ + if(!mcuxClExample_Els_Init(MCUXCLELS_RESET_DO_NOT_CANCEL)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /* Create session handle to be used by verify function */ + mcuxClSession_Descriptor_t sessionDesc; + mcuxClSession_Handle_t session = &sessionDesc; + + MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(session, + MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE, + MCUXCLRSA_VERIFY_2048_WAPKC_SIZE); + + /* Initialize the PRNG */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Create key struct of type MCUXCLRSA_KEY_PUBLIC */ + const mcuxClRsa_KeyEntry_t Mod1 = { + .pKeyEntryData = (uint8_t *)modulus, + .keyEntryLength = RSA_KEY_BYTE_LENGTH }; + + const mcuxClRsa_KeyEntry_t Exp1 = { + .pKeyEntryData = (uint8_t *)exponent, + .keyEntryLength = RSA_PUBLIC_EXP_BYTE_LENGTH }; + + const mcuxClRsa_Key public_key = { + .keytype = MCUXCLRSA_KEY_PUBLIC, + .pMod1 = (mcuxClRsa_KeyEntry_t *)&Mod1, + .pMod2 = NULL, + .pQInv = NULL, + .pExp1 = (mcuxClRsa_KeyEntry_t *)&Exp1, + .pExp2 = NULL, + .pExp3 = NULL }; + + /**************************************************************************/ + /* RSA verification call */ + /**************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(verify_result, verify_token, mcuxClRsa_verify( + /* mcuxClSession_Handle_t pSession: */ session, + /* const mcuxClRsa_Key * const pKey: */ &public_key, + /* mcuxCl_InputBuffer_t pMessageOrDigest: */ (uint8_t *)message, + /* const uint32_t messageLength: */ 0u, + /* mcuxCl_Buffer_t pSignature: */ (uint8_t *)signature, + /* const mcuxClRsa_SignVerifyMode pVerifyMode: */ (mcuxClRsa_SignVerifyMode_t *)&mcuxClRsa_Mode_Verify_Pss_Sha2_256, + /* const uint32_t saltLength: */ RSA_PSS_SALT_LENGTH, + /* uint32_t options: */ MCUXCLRSA_OPTION_MESSAGE_DIGEST, + /* mcuxCl_Buffer_t pOutput: */ NULL)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_verify) != verify_token) || (MCUXCLRSA_STATUS_VERIFY_OK != verify_result)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /**************************************************************************/ + /* Session clean-up */ + /**************************************************************************/ + + /** Destroy Session and cleanup Session **/ + if(!mcuxClExample_Session_Clean(session)) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + /** Disable the ELS **/ + if(!mcuxClExample_Els_Disable()) + { + return MCUXCLEXAMPLE_STATUS_ERROR; + } + + return MCUXCLEXAMPLE_STATUS_OK; +} diff --git a/components/els_pkc/examples/mcuxCsslFlowProtection/inc/mcuxCsslExamples.h b/components/els_pkc/examples/mcuxCsslFlowProtection/inc/mcuxCsslExamples.h new file mode 100644 index 000000000..60dd7192b --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslFlowProtection/inc/mcuxCsslExamples.h @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUX_CSSL_EXAMPLES_H_ +#define MCUX_CSSL_EXAMPLES_H_ + +#include +#include +#include + +#define MCUX_CSSL_EX_FUNCTION(_name) bool _name(void) + +#define MCUX_CSSL_EX_OK true +#define MCUX_CSSL_EX_ERROR false + +static inline bool mcuxCsslExamples_assertEqual(const uint8_t * const x, const uint8_t * const y, uint32_t length) +{ + for (uint32_t i = 0; i < length; ++i) + { + if (x[i] != y[i]) + { + return false; + } + } + + return true; +} + +MCUX_CSSL_EX_FUNCTION(mcuxCsslFlowProtection_example); + +#endif /* MCUX_CSSL_EXAMPLES_H_ */ diff --git a/components/els_pkc/examples/mcuxCsslFlowProtection/mcuxCsslFlowProtection_example.c b/components/els_pkc/examples/mcuxCsslFlowProtection/mcuxCsslFlowProtection_example.c new file mode 100644 index 000000000..f7df981ce --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslFlowProtection/mcuxCsslFlowProtection_example.c @@ -0,0 +1,473 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + + +#define MCUX_CSSL_FP_ASSERT_CALLBACK() assertCallback() + + +#include +#include +#include + +/* Example global SC */ +static volatile uint32_t testVariable = 0u; + +/* Protected function pointer type */ +MCUX_CSSL_FP_FUNCTION_POINTER(functionPointerType_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) (*functionPointerType_t)(void)); + + +/****************************************************************************/ +/* Function declaration */ +/****************************************************************************/ + +uint32_t functionOnly(void); +void assertCallback(void); + + +/****************************************************************************/ +/* Protected function declarations */ +/****************************************************************************/ + +MCUX_CSSL_FP_FUNCTION_DECL(functionOnly0) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionOnly0(void); + +MCUX_CSSL_FP_FUNCTION_DECL(functionOnly1) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionOnly1(void); + +MCUX_CSSL_FP_FUNCTION_DECL(functionOnly2, functionPointerType_t) /* Important: no semicolon here & adding functionPointerType info! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionOnly2(void); + +MCUX_CSSL_FP_FUNCTION_DECL(functionCall) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionCall(void); + +MCUX_CSSL_FP_FUNCTION_DECL(functionCalls) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionCalls(void); + +MCUX_CSSL_FP_FUNCTION_DECL(functionLoop) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionLoop(uint32_t count); + +MCUX_CSSL_FP_FUNCTION_DECL(functionBranch) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionBranch(uint32_t arg); + +MCUX_CSSL_FP_FUNCTION_DECL(functionSwitch) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionSwitch(uint32_t arg); + +MCUX_CSSL_FP_FUNCTION_DECL(functionAssert) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionAssert(void); + + + +/****************************************************************************/ +/* Function definitions */ +/****************************************************************************/ + +uint32_t functionOnly(void) +{ + return 0xC0DEu; +} + +void assertCallback(void) +{ + testVariable += 1UL; +} + +/****************************************************************************/ +/* Protected function definitions */ +/****************************************************************************/ + +/* + * Example for a very basic protected function (without any protected code). + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionOnly0) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionOnly0(void) +{ + /* FUNCTION_ENTRY initializes the flow protection for this function. */ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionOnly0); + + /* FUNCTION_EXIT encodes the result together with a protection token in the + * return code. */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(functionOnly0); +} + +/* + * Example of a function that performs a protected function call. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionCall) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionCall(void) +{ + /* The protected function that will be called must be declared as expected, + * either in the FUNCTION_ENTRY, FUNCTION_EXIT, EXPECT, or an event that + * accepts expectation declarations. + * FUNCTION_ENTRY can be used with and without providing expectations. */ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionCall, + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly0) + ); + + /* A call to a protected function must be wrapped using FUNCTION_CALL. This + * is needed to capture and process the protection token, returned by the + * function that is called, and inform the flow protection mechanism of this + * function call event. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(functionOnly0()); + + /* FUNCTION_EXIT can be used with and without providing expectations. */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(functionCall); +} + +/* Another simple protected function, used in functionCalls example. */ +MCUX_CSSL_FP_FUNCTION_DEF(functionOnly1) +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionOnly1(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionOnly1); + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(functionOnly1, 1u, 0xFAFAu); +} + +/* Another simple protected function, used in functionCalls example. */ +MCUX_CSSL_FP_FUNCTION_DEF(functionOnly2, functionPointerType_t) +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionOnly2(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionOnly2); + MCUX_CSSL_FP_FUNCTION_EXIT(functionOnly2, 2u); +} + +/* + * Example of a function that performs multiple function calls. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionCalls) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionCalls(void) +{ + /* FUNCTION_ENTRY can be used with multiple expectations. */ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionCalls, + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly0), + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly1) + ); + + /* Multiple calls to protected functions. + * Note: the provided result variables must be unique. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(functionOnly0()); + MCUX_CSSL_FP_FUNCTION_CALL(result1, functionOnly1()); + MCUX_CSSL_FP_FUNCTION_CALL(result2, functionOnly2()); + + /* EXPECT can be used to provide expectations in the body of the function. + * Note: using it with a single expectation is considered unsecure. */ + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly0) + ); + + /* It is still possible to call unprotected functions. */ + uint32_t result = functionOnly(); + + /* Another block of protected function calls. + * Note: the provided result variables must be unique. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(functionOnly0()); + MCUX_CSSL_FP_FUNCTION_CALL(result1_, functionOnly1()); + MCUX_CSSL_FP_FUNCTION_CALL(result2_, functionOnly2()); + + /* EXPECT can also be used with multiple expectations. */ + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly0), + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly2) + ); + + /* Another protected function call */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(functionOnly0()); + + result += result1 + result2 + result1_ + result2_; + /* FUNCTION_EXIT can also be used with multiple expectations. */ + MCUX_CSSL_FP_FUNCTION_EXIT(functionCalls, result, + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly1), + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly2) + ); + + /* In this function we have had various calls, i.e. call events: + * - functionOnly0 (3 times) + * - functionOnly1 (2 times) + * - functionOnly2 (2 times) + * - functionOnly (unprotected, so not considered as a protected event) + * + * Every one of these events needs to be declared as expected for the flow + * protection mechanism to be able operate properly, in this example: + * - functionOnly0, in FUNCTION_ENTRY and twice in EXPECT + * - functionOnly1, in FUNCTION_EXIT and EXPECT + * - functionOnly2, in FUNCTION_EXIT and EXPECT + * - functionOnly, no need to declare, since unprotected. + */ +} + +/* + * Example of a function that performs a protected loop. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionLoop) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionLoop(uint32_t count) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionLoop); + + /* Every protected entity needs to be declared, hence also this loop. */ + MCUX_CSSL_FP_LOOP_DECL(loop); + for (uint32_t i = 0; i < count; ++i) + { + /* Within the protected loop, a LOOP_ITERATION event must be placed, to + * indicate to the flow protection mechanism that a loop iteration event + * occured. */ + MCUX_CSSL_FP_LOOP_ITERATION(loop); + } + + /* For a protected loop the expectation is that it should perform an certain + * number of iterations. This can be indicated to the flow protection + * mechanism by using the LOOP_ITERATIONS expectation. */ + MCUX_CSSL_FP_FUNCTION_EXIT(functionLoop, 0xC0DEu, + MCUX_CSSL_FP_LOOP_ITERATIONS(loop, count) + ); +} + +/* + * Example of a function that performs a protected branch. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionBranch) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionBranch(uint32_t arg) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionBranch); + + /* Every protected entity needs to be declared, hence also this branch. */ + MCUX_CSSL_FP_BRANCH_DECL(argCheck); + uint32_t result; + if (0xC0DEu == arg) + { + result = 0xC0DEu; + + /* Within the positive scenario of a protected branch, a BRANCH_POSITIVE + * event must be placed, to indicate to the flow protection mechanism that + * the positive scenario of the protected branch has been executed. */ + MCUX_CSSL_FP_BRANCH_POSITIVE(argCheck); + } + else + { + result = 0xDEADu; + + /* Within the negative scenario of a protected branch, a BRANCH_NEGATIVE + * event must be placed, to indicate to the flow protection mechanism that + * the negative scenario of the protected branch has been executed. */ + MCUX_CSSL_FP_BRANCH_NEGATIVE(argCheck); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(functionBranch, result, 0xFAFAu, + /* Option 1: provide the condition as part of the branch expectation. */ + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(argCheck, 0xC0DEu == arg), + /* Option 2: place the branch expectation in a conditional block. */ + MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg, + MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(argCheck) + ) + ); +} + +/* + * Example of a function that performs a protected switch. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionSwitch) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) functionSwitch(uint32_t arg) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionSwitch); + + /* Every protected entity needs to be declared, hence also this switch. */ + MCUX_CSSL_FP_SWITCH_DECL(argSwitch); + uint32_t result; + switch (arg) + { + case 0xC0DEu: + { + result = 0xC0DEu; + + /* Within a case of a protected switch, a SWITCH_CASE event must be + * placed, to indicate to the flow protection mechanism that this + * particular case has been executed. */ + MCUX_CSSL_FP_SWITCH_CASE(argSwitch, 0xC0DEu); + break; + } + case 0xDEADu: + { + result = 0xDEADu; + + /* Within a case of a protected switch, a SWITCH_CASE event must be + * placed, to indicate to the flow protection mechanism that this + * particular case has been executed. */ + MCUX_CSSL_FP_SWITCH_CASE(argSwitch, 0xDEADu); + break; + } + default: + { + result = 0; + + /* Within the default case of a protected switch, a SWITCH_DEFAULT event + * must be placed, to indicate to the flow protection mechanism that the + * default case has been executed. */ + MCUX_CSSL_FP_SWITCH_DEFAULT(argSwitch); + break; + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT(functionSwitch, result, + /* Option 1: provide the condition as part of the switch expectation. */ + MCUX_CSSL_FP_SWITCH_TAKEN(argSwitch, 0xC0DEu, 0xC0DEu == arg), + MCUX_CSSL_FP_SWITCH_TAKEN(argSwitch, 0xDEADu, 0xDEADu == arg), + /* Option 2: place the switch expectation in a conditional block. */ + MCUX_CSSL_FP_CONDITIONAL((0xC0DEu != arg) && (0xDEADu != arg), + MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(argSwitch) + ) + ); +} + +/* + * Example of a function that performs an assertion. + */ +MCUX_CSSL_FP_FUNCTION_DEF(functionAssert) /* Important: no semicolon here! */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) functionAssert(void) +{ + /* The protected function that will be called must be declared as expected, + * either in the FUNCTION_ENTRY, FUNCTION_EXIT, EXPECT, or an event that + * accepts expectation declarations. + * FUNCTION_ENTRY can be used with and without providing expectations. */ + MCUX_CSSL_FP_FUNCTION_ENTRY(functionAssert, + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly0) + ); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(functionOnly0()); + + /* The ASSERT macro allows the currently recorded code flow to be checked. + * The call to functionOnly has already been recorded as expected at the + * function entry, so at this point the only remaining expectation is that + * the function has been entered. */ + MCUX_CSSL_FP_ASSERT( + MCUX_CSSL_FP_FUNCTION_ENTERED(functionAssert) + ); + + (void) functionOnly1(); + + /* At this point the functionOnly1 call event should have happened, but not + * yet recorded as an expectation. Therefore it should be specified as an + * expected event for the assertion to pass. */ + MCUX_CSSL_FP_ASSERT( + MCUX_CSSL_FP_FUNCTION_ENTERED(functionAssert), + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly1) + ); + + /* This assertion will fail since it misses the expectation for the + * functionOnly1 call event. */ + MCUX_CSSL_FP_ASSERT( + MCUX_CSSL_FP_FUNCTION_ENTERED(functionAssert) + ); + + /* At this point MCUX_CSSL_FP_ASSERT_CALLBACK should be already executed + testVariable should be set to 0xFF*/ + + /* FUNCTION_EXIT can be used with and without providing expectations. */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(functionAssert, + MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly1) + ); +} + +MCUX_CSSL_EX_FUNCTION(mcuxCsslFlowProtection_example) +{ + const uint32_t rOnly = functionOnly(); + (void) rOnly; + functionCall(); + + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(returnCode, token, functionCalls()); + + if (0xC0E4u != returnCode) + { + return MCUX_CSSL_EX_ERROR; + } + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + if (MCUX_CSSL_FP_FUNCTION_CALLED(functionCalls) != token) + { + return MCUX_CSSL_EX_ERROR; + } +#else + (void) token; +#endif + + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(returnCode1, token1, functionLoop(10)); + + if (0xC0DEu != returnCode1) + { + return MCUX_CSSL_EX_ERROR; + } + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + if (!(MCUX_CSSL_FP_FUNCTION_CALLED(functionLoop) == token1)) + { + return MCUX_CSSL_EX_ERROR; + } +#else + (void) token1; +#endif + + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(returnCode2, token2, functionBranch(0xC0DEu)); + + if (0xC0DEu != returnCode2) + { + return MCUX_CSSL_EX_ERROR; + } + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + if (!(MCUX_CSSL_FP_FUNCTION_CALLED(functionBranch) == token2)) + { + return MCUX_CSSL_EX_ERROR; + } +#else + (void) token2; +#endif + + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(returnCode3, token3, functionSwitch(0xC0DEu)); + + if (0xC0DEu != returnCode3) + { + return MCUX_CSSL_EX_ERROR; + } + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + if (!(MCUX_CSSL_FP_FUNCTION_CALLED(functionSwitch) == token3)) + { + return MCUX_CSSL_EX_ERROR; + } +#else + (void) token3; +#endif + + functionPointerType_t funcPtr = functionOnly2; + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + const uint32_t funcPtrToken = MCUX_CSSL_FP_FUNCTION_CALLED(functionOnly2); +#endif + + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(returnCode4, token4, funcPtr()); + + if (0x2u != returnCode4) + { + return MCUX_CSSL_EX_ERROR; + } + +#if !defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && !defined(MCUX_CSSL_FP_USE_NONE) + if (!(funcPtrToken == token4)) + { + return MCUX_CSSL_EX_ERROR; + } +#else + (void) token4; +#endif + + functionAssert(); + + return MCUX_CSSL_EX_OK; +} diff --git a/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_compare.c b/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_compare.c new file mode 100644 index 000000000..55443b22a --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_compare.c @@ -0,0 +1,98 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file data_invariant_memory_compare.c + * @brief Example constant-time memory compare (CSSL component mcuxCsslMemory) */ + +#include +#include +#include +#include +#include +#include +#include + +#define EXIT_CODE_ERROR false ///< example return code in case an error occurred +#define EXIT_CODE_OK true ///< example return code in case of successful operation + +bool data_invariant_memory_compare(void) +{ + /* Define data arrays */ + uint8_t arr1[] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, + 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, + 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, + 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, + 0x76u}; + uint8_t arr2[sizeof(arr1)] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, + 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, + 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, + 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, + 0x71u}; + uint8_t arr3[sizeof(arr1)] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, + 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, + 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, + 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, + 0x76u}; + + + /* Compare arr1 with itself => Should be true */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(compareResult, compareToken, mcuxCsslMemory_Compare( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(3u, arr1, arr1, sizeof(arr1)), + /* void const * lhs, */ arr1, + /* void const * rhs, */ arr1, + /* size_t length */ sizeof(arr1))); + + /* Check the return code of mcuxCsslMemory_Compare */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) != compareToken) || (MCUXCSSLMEMORY_STATUS_EQUAL != compareResult)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Compare arr1 with arr2 => Should be false */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(compareResult1, compareToken1, mcuxCsslMemory_Compare( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(3u, arr1, arr2, sizeof(arr1)), + /* void const * lhs, */ arr1, + /* void const * rhs, */ arr2, + /* size_t length */ sizeof(arr1))); + + /* Check the return code of mcuxCsslMemory_Compare */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) != compareToken1) || (MCUXCSSLMEMORY_STATUS_NOT_EQUAL != compareResult1)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Compare arr1 with arr3 => Should be true */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(compareResult2, compareToken2, mcuxCsslMemory_Compare( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(3u, arr1, arr3, sizeof(arr1)), + /* void const * lhs, */ arr1, + /* void const * rhs, */ arr3, + /* size_t length */ sizeof(arr1))); + + /* Check the return code of mcuxCsslMemory_Compare */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) != compareToken2) || (MCUXCSSLMEMORY_STATUS_EQUAL != compareResult2)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* No error occurred during execution, exit with EXIT_CODE_OK */ + return EXIT_CODE_OK; +} diff --git a/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_copy.c b/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_copy.c new file mode 100644 index 000000000..31c7272b8 --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslMemory/data_invariant_memory_copy.c @@ -0,0 +1,93 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file data_invariant_memory_copy.c + * @brief Example constant-time memory copy (CSSL component mcuxCsslMemory) */ + +#include +#include +#include +#include +#include +#include +#include + +#define EXIT_CODE_ERROR false ///< example return code in case an error occurred +#define EXIT_CODE_OK true ///< example return code in case of successful operation + +bool data_invariant_memory_copy(void) +{ + /* Define data arrays */ + uint8_t arr1[] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, + 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, + 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, + 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, + 0x76u}; + + uint8_t arr2[sizeof(arr1)] = {0u}; + + + /* Provoke buffer overflow => should return invalid parameter error */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(copyResult, copyToken, mcuxCsslMemory_Copy( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(4u, arr1, arr2, sizeof(arr1), sizeof(arr1) + 1u), + /* void const * src, */ arr1, + /* void * dst, */ arr2, + /* size_t dstLength, */ sizeof(arr1), + /* size_t length */ sizeof(arr1) + 1u)); + + /* Check the return code of mcuxCsslMemory_Copy */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) != copyToken) || (MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER != copyResult)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Try to copy nothing (length = 0 bytes) => should return invalid parameter error */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(copyResult1, copyToken1, mcuxCsslMemory_Copy( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(4u, arr1, arr2, sizeof(arr1), 0u), + /* void const * src, */ arr1, + /* void * dst, */ arr2, + /* size_t dstLength, */ sizeof(arr1), + /* size_t length */ 0u)); + + /* Check the return code of mcuxCsslMemory_Copy */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) != copyToken1) || (MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER != copyResult1)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* Copy arr1 to arr2 => should return success */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(copyResult2, copyToken2, mcuxCsslMemory_Copy( + /* mcuxCsslParamIntegrity_Checksum_t chk,*/ mcuxCsslParamIntegrity_Protect(4u, arr1, arr2, sizeof(arr1), sizeof(arr1)), + /* void const * src, */ arr1, + /* void * dst, */ arr2, + /* size_t dstLength, */ sizeof(arr1), + /* size_t length */ sizeof(arr1))); + + /* Check the return code of mcuxCsslMemory_Copy */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) != copyToken2) || (MCUXCSSLMEMORY_STATUS_OK != copyResult2)) + { + return EXIT_CODE_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + /* No error occurred during execution, exit with EXIT_CODE_OK */ + return EXIT_CODE_OK; +} diff --git a/components/els_pkc/examples/mcuxCsslMemory/inc/mcuxCsslMemory_Examples.h b/components/els_pkc/examples/mcuxCsslMemory/inc/mcuxCsslMemory_Examples.h new file mode 100644 index 000000000..79af4ee59 --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslMemory/inc/mcuxCsslMemory_Examples.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCSSLMEMORY_EXAMPLES_H_ +#define MCUXCSSLMEMORY_EXAMPLES_H_ + +#include +#include +#include + +#define MCUXCSSL_MEMORY_EX_FUNCTION(_name) bool _name(void) + +#define MCUXCSSLMEMORY_EX_OK true +#define MCUXCSSLMEMORY_EX_ERROR false + +bool data_invariant_memory_compare(void); +bool data_invariant_memory_copy(void); +MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Clear_example); +MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Set_example); + +#endif /* MCUXCSSLMEMORY_EXAMPLES_H_ */ diff --git a/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Clear_example.c b/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Clear_example.c new file mode 100644 index 000000000..be3eb6ebe --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Clear_example.c @@ -0,0 +1,50 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file csslMemory_Clear_example.c + * @brief Example constant-time memory clear (CSSL component mcuxCsslMemory) */ + +#include +#include +#include +#include +#include + +MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Clear_example) +{ + /* Define data array */ + uint8_t arr[] = {0xe4u, 0xf9u, 0x26u, 0x4cu, 0x65u, 0xe2u, 0x13u, 0xa3u, + 0x9au, 0x40u, 0xd7u, 0x87u, 0xccu, 0x0bu, 0x31u, 0x18u, + 0xacu, 0x55u, 0xb5u, 0x7du, 0x06u, 0x7fu, 0xceu, 0xe4u, + 0xb2u, 0x7eu, 0xd5u, 0xaau, 0x90u, 0x9au, 0x42u, 0x56u, + 0x76u}; + + /* Clear whole array => should return success */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(clearResult, clearToken, mcuxCsslMemory_Clear( + /* mcuxCsslParamIntegrity_Checksum_t chk */ mcuxCsslParamIntegrity_Protect(3u, arr, sizeof(arr), sizeof(arr)), + /* void * pDst */ arr, + /* size_t dstLength */ sizeof(arr), + /* size_t length */ sizeof(arr) + )); + + /* Check the return code of mcuxCsslMemory_Clear */ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Clear) != clearToken) || (MCUXCSSLMEMORY_STATUS_OK != clearResult)) + { + return MCUXCSSLMEMORY_EX_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + + return MCUXCSSLMEMORY_EX_OK; +} diff --git a/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Set_example.c b/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Set_example.c new file mode 100644 index 000000000..1a61b8f68 --- /dev/null +++ b/components/els_pkc/examples/mcuxCsslMemory/mcuxCsslMemory_Set_example.c @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file csslMemory_Set_example.c + * @brief Example constant-time memory set (CSSL component mcuxCsslMemory) */ + +#include +#include +#include +#include +#include + +MCUXCSSL_MEMORY_EX_FUNCTION(mcuxCsslMemory_Set_example) +{ + /* Define data array */ + uint8_t arr[33] = { 0u }; + + /* Try to set nothing (length = 0 bytes) => should return invalid parameter error */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(setResult, setToken, mcuxCsslMemory_Set( + /* mcuxCsslParamIntegrity_Checksum_t chk */ mcuxCsslParamIntegrity_Protect(4u, arr, 42u, 0u, sizeof(arr)), + /* void * pDst */ arr, + /* uint8_t val */ 42u, + /* size_t length */ 0u, + /* size_t bufLength */ sizeof(arr) + )); + + /* Check the return code of mcuxCsslMemory_Set */ + if(((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set) != setToken)) || (MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER != setResult)) + { + return MCUXCSSLMEMORY_EX_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Try to call the function with NULL as destination => should return invalid parameter error */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(setResult1, setToken1, mcuxCsslMemory_Set( + /* mcuxCsslParamIntegrity_Checksum_t chk */ mcuxCsslParamIntegrity_Protect(4u, NULL, 42u, sizeof(arr), sizeof(arr)), + /* void * pDst */ NULL, + /* uint8_t val */ 42u, + /* size_t length */ sizeof(arr), + /* size_t bufLength */ sizeof(arr) + )); + + /* Check the return code of mcuxCsslMemory_Set */ + if(((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set) != setToken1)) || (MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER != setResult1)) + { + return MCUXCSSLMEMORY_EX_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Set all bytes in the buffer to 42 => should return success */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(setResult2, setToken2, mcuxCsslMemory_Set( + /* mcuxCsslParamIntegrity_Checksum_t chk */ mcuxCsslParamIntegrity_Protect(4u, arr, 42u, sizeof(arr), sizeof(arr)), + /* void * pDst */ arr, + /* uint8_t val */ 42u, + /* size_t length */ sizeof(arr), + /* size_t bufLength */ sizeof(arr) + )); + + /* Check the return code of mcuxCsslMemory_Set */ + if(((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set) != setToken2)) || (MCUXCSSLMEMORY_STATUS_OK != setResult2)) + { + return MCUXCSSLMEMORY_EX_ERROR; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return MCUXCSSLMEMORY_EX_OK; +} diff --git a/components/els_pkc/set_component_els_pkc.cmake b/components/els_pkc/set_component_els_pkc.cmake new file mode 100644 index 000000000..aa7a8172e --- /dev/null +++ b/components/els_pkc/set_component_els_pkc.cmake @@ -0,0 +1,1286 @@ +include_guard(GLOBAL) + + +if (CONFIG_USE_component_els_pkc_core) +# Add set(CONFIG_USE_component_els_pkc_core true) in config.cmake to use this component + +message("component_els_pkc_core component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCore/inc +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_data_integrity) +# Add set(CONFIG_USE_component_els_pkc_data_integrity true) in config.cmake to use this component + +message("component_els_pkc_data_integrity component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslDataIntegrity/inc +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_els_header_only) +# Add set(CONFIG_USE_component_els_pkc_els_header_only true) in config.cmake to use this component + +message("component_els_pkc_els_header_only component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/inc/internal +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_padding) +# Add set(CONFIG_USE_component_els_pkc_padding true) in config.cmake to use this component + +message("component_els_pkc_padding component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPadding/src/mcuxClPadding.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPadding/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPadding/inc/internal +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_pre_processor) +# Add set(CONFIG_USE_component_els_pkc_pre_processor true) in config.cmake to use this component + +message("component_els_pkc_pre_processor component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslCPreProcessor/inc +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_secure_counter) +# Add set(CONFIG_USE_component_els_pkc_secure_counter true) in config.cmake to use this component + +message("component_els_pkc_secure_counter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslSecureCounter/inc +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_toolchain) +# Add set(CONFIG_USE_component_els_pkc_toolchain true) in config.cmake to use this component + +message("component_els_pkc_toolchain component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/compiler +) + + +endif() + + +if (CONFIG_USE_component_els_pkc_doc_mcxn) +# Add set(CONFIG_USE_component_els_pkc_doc_mcxn true) in config.cmake to use this component + +message("component_els_pkc_doc_mcxn component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN235 OR CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "component_els_pkc_doc_mcxn dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_static_lib_mcxn) +# Add set(CONFIG_USE_component_els_pkc_static_lib_mcxn true) in config.cmake to use this component + +message("component_els_pkc_static_lib_mcxn component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN235 OR CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "component_els_pkc_static_lib_mcxn dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_common) +# Add set(CONFIG_USE_component_els_pkc_common true) in config.cmake to use this component + +message("component_els_pkc_common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_memory) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/common/src/mcuxClOscca_CommonOperations.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/common/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_common dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_aead) +# Add set(CONFIG_USE_component_els_pkc_aead true) in config.cmake to use this component + +message("component_els_pkc_aead component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_els) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAead/src/mcuxClAead.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAead/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAead/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_aead dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_aead_modes) +# Add set(CONFIG_USE_component_els_pkc_aead_modes true) in config.cmake to use this component + +message("component_els_pkc_aead_modes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_aead) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesCcm.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesGcm.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_CcmEngineAes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Modes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_GcmEngineAes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Multipart.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Oneshot.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAeadModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_aead_modes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_aes) +# Add set(CONFIG_USE_component_els_pkc_aes true) in config.cmake to use this component + +message("component_els_pkc_aes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_key) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAes/src/mcuxClAes_KeyTypes.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClAes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_aes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_cipher) +# Add set(CONFIG_USE_component_els_pkc_cipher true) in config.cmake to use this component + +message("component_els_pkc_cipher component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_els) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipher/src/mcuxClCipher.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipher/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipher/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_cipher dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_cipher_modes) +# Add set(CONFIG_USE_component_els_pkc_cipher_modes true) in config.cmake to use this component + +message("component_els_pkc_cipher_modes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_cipher) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_Aes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_EngineAes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Helper.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Modes.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClCipherModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_cipher_modes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_ecc) +# Add set(CONFIG_USE_component_els_pkc_ecc true) in config.cmake to use this component + +message("component_els_pkc_ecc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_pkc AND CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_key AND CONFIG_USE_component_els_pkc_els) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Constants.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignatureMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_InitPrivKeyInputMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SetupEnvironment.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SignatureMechanisms.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_VerifySignature.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_BlindedScalarMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Convert_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_GenerateMultiplicativeBlinding.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Interleave_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveScalar.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveTwoScalars.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_PointComparison_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_RecodeAndReorderScalar.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Types.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_KeyTypes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyAgreement.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyGeneration.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_DhSetupEnvironment.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_SignatureMechanisms.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_FixScalarMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectComb.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectML.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainVarScalarMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointValidation_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SetupEnvironment.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_SetupEnvironment.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEcc/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_ecc dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_els_common) +# Add set(CONFIG_USE_component_els_pkc_els_common true) in config.cmake to use this component + +message("component_els_pkc_els_common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_core) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Common.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_els_common dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_standalone_keyManagement) +# Add set(CONFIG_USE_component_els_pkc_standalone_keyManagement true) in config.cmake to use this component + +message("component_els_pkc_standalone_keyManagement component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_memory) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_KeyManagement.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_standalone_keyManagement dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_standalone_gdet) +# Add set(CONFIG_USE_component_els_pkc_standalone_gdet true) in config.cmake to use this component + +message("component_els_pkc_standalone_gdet component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_els_header_only AND CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_standalone_gdet dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_els) +# Add set(CONFIG_USE_component_els_pkc_els true) in config.cmake to use this component + +message("component_els_pkc_els component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_els_header_only AND CONFIG_USE_component_els_pkc_els_common AND CONFIG_USE_component_els_pkc_standalone_keyManagement AND CONFIG_USE_component_els_pkc_hash AND CONFIG_USE_component_els_pkc_core AND CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_key AND CONFIG_USE_component_els_pkc_mac_modes AND CONFIG_USE_component_els_pkc_aead_modes AND CONFIG_USE_component_els_pkc_data_integrity AND CONFIG_USE_component_els_pkc_cipher_modes) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Aead.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Cipher.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Cmac.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Ecc.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Hash.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Hmac.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Kdf.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClEls/src/mcuxClEls_Rng.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "component_els_pkc_els dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_hash) +# Add set(CONFIG_USE_component_els_pkc_hash true) in config.cmake to use this component + +message("component_els_pkc_hash component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_els AND CONFIG_USE_component_els_pkc_hashmodes) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHash/src/mcuxClHash_api_multipart_common.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHash/src/mcuxClHash_api_multipart_compute.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHash/src/mcuxClHash_api_oneshot_compute.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHash/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_hash dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_hashmodes) +# Add set(CONFIG_USE_component_els_pkc_hashmodes true) in config.cmake to use this component + +message("component_els_pkc_hashmodes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_els) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHashModes/src/mcuxClHashModes_Core_els_sha2.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHashModes/src/mcuxClHashModes_Internal_els_sha2.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHashModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHashModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_hashmodes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_key) +# Add set(CONFIG_USE_component_els_pkc_key true) in config.cmake to use this component + +message("component_els_pkc_key component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_els AND CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_ecc) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClKey/src/mcuxClKey.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClKey/src/mcuxClKey_Protection.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClKey/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_key dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_mac) +# Add set(CONFIG_USE_component_els_pkc_mac true) in config.cmake to use this component + +message("component_els_pkc_mac component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_key AND CONFIG_USE_component_els_pkc_toolchain AND CONFIG_USE_component_els_pkc_padding AND CONFIG_USE_component_els_pkc_hmac) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMac/src/mcuxClMac.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMac/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMac/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_mac dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_hmac) +# Add set(CONFIG_USE_component_els_pkc_hmac true) in config.cmake to use this component + +message("component_els_pkc_hmac component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_key AND CONFIG_USE_component_els_pkc_toolchain AND CONFIG_USE_component_els_pkc_padding) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/size/size.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_Els.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_Functions.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_Helper.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_KeyTypes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_Modes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/src/mcuxClHmac_Sw.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClHmac/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_hmac dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_mac_modes) +# Add set(CONFIG_USE_component_els_pkc_mac_modes true) in config.cmake to use this component + +message("component_els_pkc_mac_modes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_mac) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/src/mcuxClMacModes.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cbcmac.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cmac.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Functions.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/src/mcuxClMacModes_Modes.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMacModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_mac_modes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_math) +# Add set(CONFIG_USE_component_els_pkc_math true) in config.cmake to use this component + +message("component_els_pkc_math component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_pkc) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ExactDivide.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ModExp_SqrMultL2R.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ModInv.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ModInv_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_NDash.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_NDash_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_QDash.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_QDash_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_ReduceModEven.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_SecModExp.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_SecModExp_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/src/mcuxClMath_Utils.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMath/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_math dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_memory) +# Add set(CONFIG_USE_component_els_pkc_memory true) in config.cmake to use this component + +message("component_els_pkc_memory component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_param_integrity AND CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_toolchain) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMemory/src/mcuxClMemory.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClMemory/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslMemory/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_memory dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_oscca_pkc) +# Add set(CONFIG_USE_component_els_pkc_oscca_pkc true) in config.cmake to use this component + +message("component_els_pkc_oscca_pkc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaPkc/src/mcuxClOsccaPkc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaPkc/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaPkc/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_oscca_pkc dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_oscca_sm3) +# Add set(CONFIG_USE_component_els_pkc_oscca_sm3 true) in config.cmake to use this component + +message("component_els_pkc_oscca_sm3 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_core_sm3.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_internal_sm3.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaSm3/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClOsccaSm3/inc/internal +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + if(CONFIG_TOOLCHAIN STREQUAL iar) + target_compile_options(${MCUX_SDK_PROJECT_NAME} PUBLIC + --diag_suppress Pe177 + ) + endif() + if(CONFIG_TOOLCHAIN STREQUAL armgcc) + target_compile_options(${MCUX_SDK_PROJECT_NAME} PUBLIC + -Wno-unused-function + ) + endif() + +endif() + +else() + +message(SEND_ERROR "component_els_pkc_oscca_sm3 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_pkc) +# Add set(CONFIG_USE_component_els_pkc_pkc true) in config.cmake to use this component + +message("component_els_pkc_pkc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_ecc AND CONFIG_USE_component_els_pkc_math AND CONFIG_USE_component_els_pkc_rsa) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/src/mcuxClPkc_Calculate.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/src/mcuxClPkc_ImportExport.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/src/mcuxClPkc_Initialize.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/src/mcuxClPkc_UPTRT.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPkc/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_pkc dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_prng) +# Add set(CONFIG_USE_component_els_pkc_prng true) in config.cmake to use this component + +message("component_els_pkc_prng component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_ecc AND CONFIG_USE_component_els_pkc_math AND CONFIG_USE_component_els_pkc_rsa) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPrng/src/mcuxClPrng_ELS.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPrng/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClPrng/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_prng dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_random) +# Add set(CONFIG_USE_component_els_pkc_random true) in config.cmake to use this component + +message("component_els_pkc_random component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_random_modes AND CONFIG_USE_component_els_pkc_prng) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandom/src/mcuxClRandom_DRBG.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandom/src/mcuxClRandom_PRNG.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandom/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandom/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_random dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_random_modes) +# Add set(CONFIG_USE_component_els_pkc_random_modes true) in config.cmake to use this component + +message("component_els_pkc_random_modes component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_aes AND CONFIG_USE_component_els_pkc_trng) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_Els.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_ElsMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PatchMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_TestMode.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_random_modes dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_random_modes_ctr) +# Add set(CONFIG_USE_component_els_pkc_random_modes_ctr true) in config.cmake to use this component + +message("component_els_pkc_random_modes_ctr component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_aes AND CONFIG_USE_component_els_pkc_trng) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_PrDisabled.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_NormalMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PrDisabled.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_random_modes_ctr dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_rsa) +# Add set(CONFIG_USE_component_els_pkc_rsa true) in config.cmake to use this component + +message("component_els_pkc_rsa component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_pkc AND CONFIG_USE_component_els_pkc_toolchain) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_GenerateProbablePrime.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Plain.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Mgf1.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_ModInv.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_NoEncode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_NoVerify.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Encode_sign.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Verify.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_PrivatePlain.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_PssEncode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_PssVerify.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Public.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Public_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Sign.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate_FUP.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_Verify.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_VerifyE.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding_FUP.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRsa/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_rsa dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_session) +# Add set(CONFIG_USE_component_els_pkc_session true) in config.cmake to use this component + +message("component_els_pkc_session component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_toolchain AND CONFIG_USE_component_els_pkc_random) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClSession/src/mcuxClSession.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClSession/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClSession/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_session dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_trng) +# Add set(CONFIG_USE_component_els_pkc_trng true) in config.cmake to use this component + +message("component_els_pkc_trng component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_els) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_trng dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_trng_type_els) +# Add set(CONFIG_USE_component_els_pkc_trng_type_els true) in config.cmake to use this component + +message("component_els_pkc_trng_type_els component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_trng AND CONFIG_USE_component_els_pkc_els) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClRandomModes/src/mcuxClRandomModes_NormalMode.c + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/src/mcuxClTrng_ELS.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "component_els_pkc_trng_type_els dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_trng_type_rng4) +# Add set(CONFIG_USE_component_els_pkc_trng_type_rng4 true) in config.cmake to use this component + +message("component_els_pkc_trng_type_rng4 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_trng) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/src/mcuxClTrng_SA_TRNG.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClTrng/inc/internal +) + +else() + +message(SEND_ERROR "component_els_pkc_trng_type_rng4 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_flow_protection) +# Add set(CONFIG_USE_component_els_pkc_flow_protection true) in config.cmake to use this component + +message("component_els_pkc_flow_protection component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_core) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslFlowProtection/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_flow_protection dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_param_integrity) +# Add set(CONFIG_USE_component_els_pkc_param_integrity true) in config.cmake to use this component + +message("component_els_pkc_param_integrity component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_secure_counter AND CONFIG_USE_component_els_pkc_pre_processor) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxCsslParamIntegrity/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_param_integrity dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc) +# Add set(CONFIG_USE_component_els_pkc true) in config.cmake to use this component + +message("component_els_pkc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_els AND CONFIG_USE_component_els_pkc_pkc AND CONFIG_USE_component_els_pkc_trng AND ((CONFIG_USE_component_els_pkc_platform_mcxn AND CONFIG_USE_component_els_pkc_doc_mcxn AND CONFIG_USE_component_els_pkc_static_lib_mcxn AND (CONFIG_DEVICE_ID STREQUAL MCXN235 OR CONFIG_DEVICE_ID STREQUAL MCXN236)))) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/inc/impl +) + +else() + +message(SEND_ERROR "component_els_pkc dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_platform_mcxn) +# Add set(CONFIG_USE_component_els_pkc_platform_mcxn true) in config.cmake to use this component + +message("component_els_pkc_platform_mcxn component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc AND CONFIG_USE_component_els_pkc_random_modes_ctr AND ((CONFIG_USE_component_els_pkc_trng_type_els AND (CONFIG_DEVICE_ID STREQUAL MCXN235 OR CONFIG_DEVICE_ID STREQUAL MCXN236)))) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./src/platforms/mcxn/mcux_els.c + ${CMAKE_CURRENT_LIST_DIR}/./src/platforms/mcxn/mcux_pkc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./src/platforms/mcxn + ${CMAKE_CURRENT_LIST_DIR}/./src/platforms/mcxn/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_platform_mcxn dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_els_pkc_examples) +# Add set(CONFIG_USE_component_els_pkc_examples true) in config.cmake to use this component + +message("component_els_pkc_examples component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_els_pkc_flow_protection AND CONFIG_USE_component_els_pkc_session AND CONFIG_USE_component_els_pkc_memory AND CONFIG_USE_component_els_pkc_els AND CONFIG_USE_component_els_pkc_pkc AND CONFIG_USE_component_els_pkc) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClAeadModes/mcuxClAeadModes_Multipart_Els_Ccm_Example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Ccm_Example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClAeadModes/mcuxClAeadModes_Oneshot_Els_Gcm_Example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Cbc_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ctr_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Multipart_Ecb_PaddingPKCS7_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Cbc_ZeroPadding_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ctr_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_PaddingPKCS7_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClCipherModes/mcuxClCipherModes_Oneshot_Ecb_ZeroPadding_Els_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_EdDSA_GenerateSignature_Ed25519_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_EdDSA_VerifySignature_Ed25519_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_Mont_Curve25519_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_WeierECC_CustomEccWeierType_BN256_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ctx_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEcc/mcuxClEcc_EdDSA_Ed25519ph_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Cbc_Encrypt_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Cipher_Aes128_Ecb_Encrypt_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Common_Get_Info_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Ecc_Keygen_Sign_Verify_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Hash_Sha224_One_Block_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Hash_Sha256_One_Block_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Hash_Sha384_One_Block_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Hash_Sha512_One_Block_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Rng_Prng_Get_Random_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClEls/mcuxClEls_Tls_Master_Key_Session_Keys_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha224_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha256_longMsgOneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha256_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha256_streaming_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha384_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHashModes/mcuxClHashModes_sha512_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHmac/mcuxClHmac_Els_Oneshot_External_Key_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClHmac/mcuxClHmac_Sw_Oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClKey/mcuxClKey_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_multipart_zero_padding_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClMacModes/mcuxClMacModes_cbc_mac_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClMacModes/mcuxClMacModes_cmac_oneshot_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClRandomModes/mcuxClRandomModes_ELS_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClRsa/mcuxClRsa_sign_NoEncode_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClRsa/mcuxClRsa_sign_pss_sha2_256_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClRsa/mcuxClRsa_verify_NoVerify_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxClRsa/mcuxClRsa_verify_pssverify_sha2_256_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslFlowProtection/mcuxCsslFlowProtection_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslMemory/data_invariant_memory_compare.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslMemory/data_invariant_memory_copy.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslMemory/mcuxCsslMemory_Clear_example.c + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslMemory/mcuxCsslMemory_Set_example.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslFlowProtection/inc + ${CMAKE_CURRENT_LIST_DIR}/./examples/mcuxCsslMemory/inc + ${CMAKE_CURRENT_LIST_DIR}/./src/comps/mcuxClExample/inc +) + +else() + +message(SEND_ERROR "component_els_pkc_examples dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + diff --git a/components/els_pkc/softwareContentRegister.txt b/components/els_pkc/softwareContentRegister.txt new file mode 100644 index 000000000..6d758e50d --- /dev/null +++ b/components/els_pkc/softwareContentRegister.txt @@ -0,0 +1,14 @@ +-------------------------------------------- +NXP Software Content Register + +Package: clns-SDK_v1.7.0.zip +Outgoing License: LA_OPT_NXP_Software_License - No distribution permitted, license in Section 2.2 applies. +License Files: LICENSE.htm +Type of content: Static library, headers, sources +Description and comments: Cryptographic library running on NXP ELS and PKC Crypto Hardware IP +Release Location: Nexus +Origin: Crypto Library (LA_OPT_NXP_Software_License) + Mbed TLS header files (Apache License 2.0; https://github.com/Mbed-TLS/mbedtls) + CMSIS header files (Apache License 2.0; https://github.com/ARM-software/CMSIS_5) + +-------------------------------------------- diff --git a/components/els_pkc/src/compiler/mcuxClToolchain.h b/components/els_pkc/src/compiler/mcuxClToolchain.h new file mode 100644 index 000000000..b63924c4b --- /dev/null +++ b/components/els_pkc/src/compiler/mcuxClToolchain.h @@ -0,0 +1,132 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef COMPILER_TOOLCHAIN_H_ +#define COMPILER_TOOLCHAIN_H_ + +/* for armclang */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT"))) + #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT"))) + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section("MCUX_OBFUSCATED_FUP_SEGMENT"))) + #define UNUSED_PARAM __attribute__((unused)) + /* + Use of UNALIGNED on ARMCLANG + + The __unaligned keyword is a type qualifier that tells the compiler to treat the pointer or variable as an unaligned pointer or variable. + www.keil.com/support/man/docs/armclang_ref/armclang_ref_pfl1493130433688.htm + + The use of __attribute__((packed)) is incorrect on ARMCLANG + + The packed type attribute specifies that a type must have the smallest possible alignment. This attribute only applies to struct and union types. + www.keil.com/support/man/docs/armclang_ref/armclang_ref_chr1393328521340.htm + + -munaligned-access is the default for architectures that support unaligned accesses to data. This default applies to all architectures supported by Arm Compiler for Embedded 6, except Armv6-M, and Armv8-M without the Main Extension. + */ + #define UNALIGNED __unaligned + #define MCUX_CSSL_UNUSED(p) ((void) (p)) + +/* using the gcc toolchain file for both gcc and armgcc */ +#elif defined ( __GNUC__ ) + #define CSS_IDATA_SEGMENT + #define CSS_CONST_SEGMENT + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) + #define UNUSED_PARAM __attribute__((unused)) + #define UNALIGNED + +/* for armcc compiler */ +#elif defined ( __CC_ARM ) + #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT"))) + #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT"))) + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section("MCUX_OBFUSCATED_FUP_SEGMENT"))) + #define UNUSED_PARAM __attribute__((unused)) + #define UNALIGNED __packed + +/* for ghs compiler */ +#elif defined ( __ghs__ ) + #define CSS_IDATA_SEGMENT + #define CSS_CONST_SEGMENT + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) + #define UNUSED_PARAM __attribute__((unused)) + #define UNALIGNED + +/* for iar compiler */ +#elif defined ( __ICCARM__ ) + #define CSS_IDATA_SEGMENT __attribute__((section("CSS_IDATA_SEGMENT"))) + #define CSS_CONST_SEGMENT __attribute__((section("CSS_CONST_SEGMENT"))) + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) __attribute__((section(".mcux_obfuscated_fup_segment"))) + #define UNUSED_PARAM __attribute__((unused)) + #define UNALIGNED __packed + +/* for llvm */ +#elif defined ( __clang__ ) + #define CSS_IDATA_SEGMENT + #define CSS_CONST_SEGMENT + #define MCUX_FUP_ATTRIBUTE __attribute__((aligned(4))) + #define UNUSED_PARAM __attribute__((unused)) + #define UNALIGNED + + +#endif + + +#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__) + #define GHS_ICCARM_ARMCC_GT_10_5_GNUC +#endif + +#if defined(__ghs__) || defined(__gcc__) || defined(__ICCARM__) || defined(__GNUC__) + #define GHS_GCC_ICCARM_GNUC +#endif + +#if defined(__ghs__) || defined(__gcc__) || defined(__ICCARM__) + #define GHS_GCC_ICCARM +#endif + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__CC_ARM) || defined(__GNUC__) + #define ICCARM_ARMCC_GNUC +#endif + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__GNUC__) + #define ICCARM_ARMCLANG_GNUC +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) + #define ARMCC_LT_10_5 //6.01 build 0050 +#endif + + +#if defined ( __CC_ARM ) +/* Arm Compiler 4/5 */ +#define MCUX_CL_COMPILER_ARMCC +#define MCUX_CL_COMPILER_ARM_COMPILER + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +/* Arm Compiler 6.6 LTM (armclang) */ +#define MCUX_CL_COMPILER_ARMCLANG_LTM +#define MCUX_CL_COMPILER_ARM_COMPILER + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +/* Arm Compiler above 6.10.1 (armclang) */ +#define MCUX_CL_COMPILER_ARMCLANG +#define MCUX_CL_COMPILER_ARM_COMPILER + +#elif defined (_clang_) +#define MCUX_CL_COMPILER_ARM_COMPILER /* i.e. Version 6.01 build 0019 */ +#endif + + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && !defined(inline) && !defined(__cplusplus) + #define ARMCC_MSC_VER_NOT_INLINE_NOT_CPP +#endif + +#endif /* COMPILER_TOOLCHAIN_H_ */ diff --git a/components/els_pkc/src/comps/common/inc/mcuxClOscca_FunctionIdentifiers.h b/components/els_pkc/src/comps/common/inc/mcuxClOscca_FunctionIdentifiers.h new file mode 100644 index 000000000..faf6ed9cb --- /dev/null +++ b/components/els_pkc/src/comps/common/inc/mcuxClOscca_FunctionIdentifiers.h @@ -0,0 +1,324 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOscca_FunctionIdentifiers.h + * @brief Definition of function identifiers for the flow protection mechanism. + * + * @note This file might be post-processed to update the identifier values to + * proper/secure values. + */ + +#ifndef MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ +#define MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ + +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_encrypt (0x1766u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_encrypt_Sm4 (0x5AE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_internal_decrypt_Sm4 (0x7C26u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_OnlyVerify_SelfTest (0x1F43u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_SignVerify_SelfTest (0x3BE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_EncDec_selftest (0x3A2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange_SelfTest (0x3A8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_finish (0x1E63u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_process (0x1B8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compute (0x5A87u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_init (0x2E4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_SM4_Gen_K1K2 (0x413Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Finalize (0x52D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Finalize (0x14EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Update (0x7247u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Update (0x14B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Init (0x06F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Init (0x489Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CBCMAC_Oneshot (0x3BA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_CMAC_Oneshot (0x11BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_reseed (0x49DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_finish_Sm4 (0x724Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_process_Sm4 (0x68AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_decrypt_Sm4 (0x7D0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_init_encrypt_Sm4 (0x54C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_decrypt_Sm4 (0x39ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_encrypt_Sm4 (0x21DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_FastSecureXor (0x6C35u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_switch_endianness (0x2C1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_finish_sm3 (0x60EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_process_sm3 (0x519Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sw_oneShotSkeleton_sm3 (0x5572u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_finishSkeleton (0x70A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_processSkeleton (0x06EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_sm3_oneShotSkeleton (0x574Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_selftest (0x5335u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PowerOnTest (0x155Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_DeliverySimpleTest (0x6E49u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_PokerTest (0x31ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_generate (0x563Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaRandomModes_ROtrng_init (0x7BC0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SkeletonCcm (0x30BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CalcMontInverse (0x6B2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_EngineCcm (0x2E47u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_Internal_Ctr (0x457Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeModInv (0x2BB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_LeadingZeros (0x496Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_MultipleShiftRotate_Index (0x52F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GeneratePointerTable (0x6D54u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeQSquared (0x1A57u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_ComputeNDash (0x3B61u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_StartFupProgram (0x161Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Op (0x5A6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetFupTable (0x339Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_WaitforFinish (0x156Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_GetWordSize (0x1E4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_SetWordSize (0x6798u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Init (0x16ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_Reset (0x4C73u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init (0x61CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_encrypt (0x168Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_init_decrypt (0x6F82u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process (0x2BD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_process_adata (0x0B2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_finish (0x1D8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_verify (0x4B87u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_crypt (0x4BD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_encrypt (0x5CA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_decrypt (0x6A5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_prepareHMACKey (0x469Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Init (0x2787u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tprime (0x3B43u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Lprime (0x2CBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_T (0x6D45u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_L (0x743Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Finalize (0x45B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Oneshot (0x2BA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Tau (0x383Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Engine_HMAC_Update (0x5C0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_SkeletonSM2 (0x41F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_finish (0x3F11u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_process (0x5A5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_init_decrypt (0x1C5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSM2_GenerateKeyPair (0x392Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_PreLoad (0x0DAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Auto (0x1CC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_Safo_Hash_Norm (0x39E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi (0x5F24u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_ProcessMessageBlock_Sgi (0x4D17u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareToZero (0x50FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_RobustCompareBoolean (0x5D62u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SignVerify_SelfTest (0x6437u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_SelfTest (0x21CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyExchange (0x52ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Decrypt (0x6E38u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Encrypt (0x4D0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ComputePrehash (0x60F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_InvertPrivateKey (0x5EB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Verify (0x48F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Sign (0x3947u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Export (0x5933u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Import (0x1B4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointCheckCoordinate (0x4B71u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAddOrDouble (0x4A7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccTransAffinePoint2Jac (0x09E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenRandomBytes (0x5E62u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultMontgomery (0x5C63u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointAdd (0x0D6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointDouble (0x0D9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointConvert2Affine (0x4973u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccJacPointCheck (0x2A97u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointYNegNoInit (0x2E78u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccImportInputPointWithInit (0x2F62u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccGenerateZ (0x4B55u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPrepareParameters (0x722Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccInit (0x11E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_WrapHash (0x6E58u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccExitClear (0x7E06u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_ValidateEncDecCtx (0x7496u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EncDec_UpdatePhase (0x7345u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecondPartOfInitPhase (0x7670u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KDF (0x63B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SetParamCrcValue (0x4793u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_CheckParamCrc (0x4A79u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_decrypt (0x16B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Cipher_encrypt (0x293Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleSM4Key (0x58B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_EngineSM4 (0x4E74u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_SkeletonSM4 (0x65CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_key_agreement (0x362Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_compare (0x3D94u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_verify (0x532Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Init (0x43A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Finish (0x387Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PreHash (0x22D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_KeyAgreement_SelfTest (0x70F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_PrepareDigest (0x1DF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_SM4_Crypt_IncCounter (0x2BACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaPkc_CountLeadingZerosWord (0x7741u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_core_sm3_processMessageBlock (0x4B74u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_Engine (0x153Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm4_ScheduleKey (0x1774u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccSecurePointMult (0x398Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_EccPointMultSplitScalar (0x70C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureExport (0x3D51u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_SecureImport (0x09FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Init (0x31B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm2_Signature_Internal_Finish (0x25DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Ecb_EncDec_SelfTest (0x1747u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaCipherModes_Sm4Cbc_EncDec_SelfTest (0x06E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4Cmac_SelfTest (0x29BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaMacModes_Sm4CbcMac_SelfTest (0x53D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Sm4Ccm_EncDec_SelfTest (0x2D0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaSm3_selftest (0x7474u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Init (0x13F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_ProcessAad (0x5D15u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Process (0x3DB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOsccaAeadModes_Ccm_Internal_Finish (0x472Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_25 (0x7E18u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_26 (0x1576u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_27 (0x5C36u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_28 (0x3A65u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_29 (0x0B73u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_30 (0x29ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_31 (0x6D85u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_32 (0x4F83u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_33 (0x09BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_34 (0x6167u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_35 (0x6A2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_36 (0x1BD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_37 (0x554Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_38 (0x6F60u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_39 (0x46A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_40 (0x1BE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_41 (0x4EA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_42 (0x59ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_43 (0x7A89u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_44 (0x7691u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_45 (0x2277u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_46 (0x6EA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_47 (0x3F14u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_48 (0x164Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_49 (0x3D0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_50 (0x0D7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_51 (0x13B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_52 (0x60E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_53 (0x6794u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_54 (0x127Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_55 (0x255Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_56 (0x583Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_57 (0x235Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_58 (0x2CA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_59 (0x65AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_60 (0x553Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_61 (0x4DA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_62 (0x179Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_63 (0x36A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_64 (0x16DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_65 (0x661Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_66 (0x0FA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_67 (0x49CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_68 (0x0B3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_69 (0x7E22u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_70 (0x52E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_71 (0x133Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_72 (0x3B91u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_73 (0x5C55u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_74 (0x2C5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_75 (0x31E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_76 (0x16F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_77 (0x21F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_78 (0x7B14u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_79 (0x6F42u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_80 (0x36A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_81 (0x3565u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_82 (0x6715u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_83 (0x4D4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_84 (0x21FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_85 (0x1D8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_86 (0x0E9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_87 (0x4E39u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_88 (0x12EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_89 (0x431Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_90 (0x12EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_91 (0x3333u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_92 (0x5E8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_93 (0x56CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_94 (0x5566u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_95 (0x151Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_96 (0x5BA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_97 (0x4F25u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_98 (0x5077u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_99 (0x59A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_100 (0x354Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_101 (0x2EB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_102 (0x3762u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_103 (0x5764u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_104 (0x651Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_105 (0x0F2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_106 (0x23BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_107 (0x65C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_108 (0x393Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_109 (0x5273u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_110 (0x239Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_111 (0x6876u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_112 (0x37C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_113 (0x5CA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_114 (0x792Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_115 (0x4C5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_116 (0x5E8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_117 (0x27E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_118 (0x3EA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_119 (0x6DC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_120 (0x09F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_121 (0x5656u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_122 (0x59B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_123 (0x4D71u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_124 (0x7265u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_125 (0x78D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_126 (0x0E57u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_127 (0x217Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_128 (0x525Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_129 (0x3873u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_130 (0x4C7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_131 (0x0F4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_132 (0x364Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_133 (0x1AEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_134 (0x3E85u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_135 (0x2C37u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_136 (0x2A6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_137 (0x38D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_138 (0x6707u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_139 (0x51CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_140 (0x7859u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_141 (0x3713u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_142 (0x45F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_143 (0x29B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_144 (0x51F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_145 (0x5671u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_146 (0x435Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_147 (0x18DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_148 (0x1B71u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_149 (0x45B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_150 (0x46DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_151 (0x233Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_152 (0x689Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_153 (0x2E8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_154 (0x2E93u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_155 (0x7B28u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_156 (0x469Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_157 (0x3A2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_158 (0x714Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_159 (0x7AA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_160 (0x2C9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_161 (0x19D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_162 (0x5E16u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_163 (0x0BD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_164 (0x6517u) +#define MCUX_CSSL_FP_FUNCID_mcuxClOscca_165 (0x433Eu) +#endif /* MCUX_OSCCACL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */ diff --git a/components/els_pkc/src/comps/common/inc/mcuxClOscca_Memory.h b/components/els_pkc/src/comps/common/inc/mcuxClOscca_Memory.h new file mode 100644 index 000000000..d5e8e8c3e --- /dev/null +++ b/components/els_pkc/src/comps/common/inc/mcuxClOscca_Memory.h @@ -0,0 +1,65 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2016, 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ +/* Security Classification: Company Confidential */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: mcuxClOscca_Memory.h + * @brief: Macros for alignment memory + * + */ + +#ifndef MCUXCLOSCCA_MEMORY_H_ +#define MCUXCLOSCCA_MEMORY_H_ + +#include // Exported features flags header +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUXCLOSCCA_SIZE_ALIGN_OFFSET (sizeof(size_t) - 1U) + +#define mcuxClOscca_alignAddress(address) \ + ((void*)( (((size_t)(address)) + (sizeof(size_t) - 1U)) \ + & ((size_t)(~(sizeof(size_t) - 1U))) )) + +#define mcuxClOscca_alignSize(size) \ + ((size_t)(((size_t)(size)) + (sizeof(size_t) - 1U)) \ + & ((size_t)(~(sizeof(size_t) - 1U))) ) + +#define mcuxClOscca_alignAddressWithOffset(address, offset) \ + ((void*)( (((size_t)(address) + (size_t)(offset)) + (sizeof(size_t) - 1U)) \ + & ((size_t)(~(sizeof(size_t) - 1U))) )) + +#define mcuxClOscca_alignAddressToBoundary(address, boundary) \ + ((void*)( (((size_t)(address)) + (boundary - 1U)) \ + & ((size_t)(~(boundary - 1U))) )) + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOscca_FastSecureXor) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_FastSecureXor(void *pTgt, + void *pSrc1, + void *pSrc2, + uint32_t length); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOscca_switch_endianness) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_switch_endianness(uint32_t *ptr, uint32_t length); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLOSCCA_MEMORY_H_ */ diff --git a/components/els_pkc/src/comps/common/inc/mcuxClOscca_PlatformTypes.h b/components/els_pkc/src/comps/common/inc/mcuxClOscca_PlatformTypes.h new file mode 100644 index 000000000..41de6c1ea --- /dev/null +++ b/components/els_pkc/src/comps/common/inc/mcuxClOscca_PlatformTypes.h @@ -0,0 +1,51 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2016, 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ +/* Security Classification: Company Confidential */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: mcuxClOscca_PlatformTypes.h + * @brief: Platform type definitions + * + */ +#ifndef MCUXCLOSCCA_PLATFORMTYPES_H_ +#define MCUXCLOSCCA_PLATFORMTYPES_H_ + +#include +#include +#include +#include + +typedef uint32_t mcuxClOscca_Size_t; +typedef uint32_t mcuxClOscca_Uint_t; +typedef int32_t mcuxClOscca_Int_t; + +/** + * global scratch pad structure definition + */ +typedef struct +{ + volatile uint16_t securityCounter; + volatile uint16_t stackPointerBackup; + uint32_t generalPurposeValue; +} mcuxClOscca_ScratchPad_t; + +#define MCUX_CLOSCCA_SCRATCHPAD_SECTION __attribute__((section(".data.gmcuxClOscca_ScratchPad"))) + +/** + * global scratch pad object + */ +extern mcuxClOscca_ScratchPad_t MCUX_CLOSCCA_SCRATCHPAD_SECTION gmcuxClOscca_ScratchPad; + +#endif /* MCUXCLOSCCA_PLATFORMTYPES_H_ */ diff --git a/components/els_pkc/src/comps/common/inc/mcuxClOscca_Types.h b/components/els_pkc/src/comps/common/inc/mcuxClOscca_Types.h new file mode 100644 index 000000000..eb7be5a30 --- /dev/null +++ b/components/els_pkc/src/comps/common/inc/mcuxClOscca_Types.h @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2016, 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ +/* Security Classification: Company Confidential */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: mcuxClOscca_Types.h + * @brief: Global type definitions + * + */ + +#ifndef MCUXCLOSCCA_TYPES_H_ +#define MCUXCLOSCCA_TYPES_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifndef __RNG_TYPES_DEFINED_ +/** +* \brief The RNG context forward declaration +*/ +typedef struct mcuxClOscca_Rng_Ctx_t mcuxClOscca_Rng_Ctx_t; +#endif + +/** \brief Structure for multi-precision integer used in asymetric cryptography. */ +typedef struct mcuxClOscca_MPInt_t +{ + uint8_t const *pMPInt; /**< Pointer to the multi precision integer. */ + uint16_t wNumBytes; /**< Length in bytes of multi precision integer. */ +} mcuxClOscca_MPInt_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLOSCCA_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/common/src/mcuxClOscca_CommonOperations.c b/components/els_pkc/src/comps/common/src/mcuxClOscca_CommonOperations.c new file mode 100644 index 000000000..9a460f774 --- /dev/null +++ b/components/els_pkc/src/comps/common/src/mcuxClOscca_CommonOperations.c @@ -0,0 +1,180 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOscca_CommonOperations.c + * @brief implementation of common functions */ + +#include +#include +#include +#include +#include +#include +#include + +/********************************************************** + * Helper functions + **********************************************************/ +/** + * This function reverses a byte string in-place (switches the endianness). + * + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOscca_switch_endianness) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_switch_endianness(uint32_t *ptr, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOscca_switch_endianness); + if(0u == length) + { + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOscca_switch_endianness); + } +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + if (0u != (length % (sizeof(uint32_t)))) + { + uint8_t *ptrL = (uint8_t *) ptr; + uint8_t *ptrH = & ((uint8_t *) ptr)[length]; + + uint32_t remainLength = length / 2u; + while (0u < remainLength) + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("ptrH will be in the valid range [ptr+length-(length/2), ptr+length] and ptrL will be in the valid range [ptr, ptr+length/2].") + ptrH--; + uint8_t byteH = *ptrH; + uint8_t byteL = *ptrL; + + *ptrL = byteH; + *ptrH = byteL; + ptrL++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + remainLength--; + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOscca_switch_endianness); + } + + /* When the length is a multiple of CPU word size, fall down to the original implementation. */ + /* length is a multiple of CPU word size (4). */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("ptr is CPU word aligned, and length is a multiple of CPU word size.") + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("ptrH32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t *ptrH32 = (uint32_t *) ((uint8_t *) ptr + length - 4u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() +#else + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("use of UNALIGNED keyword") + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP36_C, "use of UNALIGNED keyword") + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("ptrH32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t UNALIGNED *ptrH32 = (uint32_t UNALIGNED *) ((uint8_t *) ptr + length - 4u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP36_C) + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() +#endif + uint32_t *ptrL32 = ptr; + + /* While there are >= 4 bytes to switch the endianness. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3, "both ptrH32 and ptrL32 point into ptr[].") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_ARR36_C, "both ptrH32 and ptrL32 point into ptr[].") + while (ptrH32 >= ptrL32) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_ARR36_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3) + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("ptrH32 and ptrL32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t wordL = *ptrL32; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("ptrH32 = (uint32_t *) ((uint8_t *) ptr + length - 4u) is safe.") + uint32_t wordH = *ptrH32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + wordL = MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(wordL); + wordH = MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(wordH); + + *ptrH32 = wordL; + ptrH32--; + *ptrL32 = wordH; + ptrL32++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + /* Now, ptrH32 = phtL32 - 4 or ptrL32 - 8, nothing more to do. */ +#else + /* If ptrH <= ptrL - 4, nothing more to do. */ + /* If ptrH == ptrL - 3, swap ptrL[0] with ptrH[3] = ptrL[0], i.e., nothing to do. */ + /* If ptrH == ptrL - 2, swap ptrL[0] with ptrH[3] = ptrL[1]. */ + /* If ptrH == ptrL - 1, swap ptrL[0] with ptrH[3] = ptrL[2], and leave ptrL[1] unchanged. */ + + /* Wrongly reports MISRA violation to Rule 11.8 that ptrH8 and ptrL8 are not point into the same object */ + uint8_t *ptrL8 = (uint8_t *) ptrL32; + uint8_t *ptrH8 = (uint8_t *) ptrH32 + 3u; + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3, "both ptrH8 and ptrL8 point into ptr[].") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_ARR36_C, "both ptrH32 and ptrL32 point into ptr[].") + if (ptrH8 > ptrL8) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_ARR36_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3) + { + uint8_t byteL = *ptrL8; + uint8_t byteH = *ptrH8; + + *ptrH8 = byteL; + *ptrL8 = byteH; + } +#endif + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOscca_switch_endianness); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOscca_FastSecureXor) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOscca_FastSecureXor(void *pTgt, + void *pSrc1, + void *pSrc2, + uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOscca_FastSecureXor); + uint8_t *pTgtBt = pTgt; + uint32_t *pTgtWd = pTgt; + uint8_t *pSrc1Bt = pSrc1; + uint8_t *pSrc2Bt = pSrc2; + uint32_t *pSrc1Wd = pSrc1; + uint32_t *pSrc2Wd = pSrc2; + uint32_t i; + uint32_t wordSize = sizeof(uint32_t); + + /* xor by word if aligned */ + /* MISRA Ex.2 - Rule 11.6 */ + if ((length >= wordSize) && (0U == ((uint32_t)pTgt & (wordSize - 1U))) + && (0U == ((uint32_t)pSrc1 & (wordSize - 1U))) + && (0U == ((uint32_t)pSrc2 & (wordSize - 1U)))) + { + i = 0U; + while (length >= wordSize) + { + pTgtWd[i] = pSrc1Wd[i] ^ pSrc2Wd[i]; + length -= wordSize; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("The size of i is big enough, it cannot overflow.") + i++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("In the actual situation, i * wordSize cannot overflow.") + pTgtBt = pTgtBt + i * wordSize; + pSrc1Bt = pSrc1Bt + i * wordSize; + pSrc2Bt = pSrc2Bt + i * wordSize; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } + + + if (0U < length) + { + /* xor the remain bytes */ + for (i = 0U; i < length; i++) + { + pTgtBt[i] = pSrc1Bt[i] ^ pSrc2Bt[i]; + } + } + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOscca_FastSecureXor); +} diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Ctx.h b/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Ctx.h new file mode 100644 index 000000000..bb3802bc9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Ctx.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead_Internal_Ctx.h + * @brief Internal structure of the context for the mcuxClAead component + */ + +#ifndef MCUXCLAEAD_INTERNAL_CTX_H_ +#define MCUXCLAEAD_INTERNAL_CTX_H_ + +#include // Exported features flags header +#include + +#include + +struct mcuxClAead_Context +{ + const mcuxClAead_ModeDescriptor_t *mode; +}; + +#endif /* MCUXCLAEAD_INTERNAL_CTX_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Descriptor.h b/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Descriptor.h new file mode 100644 index 000000000..3167f1120 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/internal/mcuxClAead_Internal_Descriptor.h @@ -0,0 +1,152 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead_Internal_Descriptor.h + * @brief Internal definitions for the mcuxClAead component + */ + +#ifndef MCUXCLAEAD_INTERNAL_DESCRIPTOR_H_ +#define MCUXCLAEAD_INTERNAL_DESCRIPTOR_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_init_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_init_t)( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t *const pContext, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + uint32_t inLength, + uint32_t adataLength, + uint32_t tagLength + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_process_aad_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_process_aad_t)( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t *const pContext, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_process_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_process_t)( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_finish_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_finish_t)( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t *const pContext, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutLength, + mcuxCl_Buffer_t pTag + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_verify_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_verify_t)( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t *const pContext, + mcuxCl_InputBuffer_t pTag, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_crypt_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_crypt_t)( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength + )); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClAead_decrypt_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_decrypt_t)( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceSize, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataSize, + mcuxCl_InputBuffer_t pTag, + uint32_t tagSize, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutSize + )); + +struct mcuxClAead_ModeDescriptor +{ +//------------OneShot + + mcuxClAead_crypt_t crypt; + uint32_t protection_token_crypt; + + + + +//------------MultiPart + + mcuxClAead_init_t init; + uint32_t protection_token_init; + + + mcuxClAead_process_aad_t processAad; + uint32_t protection_token_processAad; + mcuxClAead_process_t process; + uint32_t protection_token_process; + mcuxClAead_finish_t finish; + uint32_t protection_token_finish; + mcuxClAead_verify_t verify; + uint32_t protection_token_verify; + + + //-------------Common + const struct mcuxClAead_AlgorithmDescriptor *algorithm; + + //TODO add CTR mode - CLNS-4374 + //TODO add macMode (gmac/cbc_mac) - CLNS-4374 +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEAD_INTERNAL_DESCRIPTOR_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead.h b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead.h new file mode 100644 index 000000000..a4d434318 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead.h @@ -0,0 +1,56 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead.h + * @brief Top-level include file for the @ref mcuxClAead component + * + * This includes headers for all of the functionality provided by the @ref mcuxClAead component. + * + * @defgroup mcuxClAead mcuxClAead + * @brief Hash component + * + * The mcuxClAead component implements the Authenticated Encryption with Associated Data (AEAD) + * operations supported by CLNS. + * + * An example of how to use the @ref mcuxClAead component can be found in /mcuxClAead/ex. + * + * The component uses the ELS hardware. The ELS hardware has to be initialized, prior to + * calling any function of the @ref mcuxClAead component. + * + * The @ref mcuxClAead component supports interfaces to either authenticate and encrypt or + * verify and decrypt a message in one shot (mcuxClAead_crypt) or to either authenticate and + * encrypt or verify and decrypt it in parts (mcuxClAead_init, mcuxClAead_process, + * mcuxClAead_process_adata and mcuxClAead_finish). In case of processing a message in parts, + * first an initialization has to be performed (mcuxClAead_init), followed by zero, one + * or multiple updates (mcuxClAead_process_adata and mcuxClAead_process), followed by a + * finalization or verification (mcuxClAead_finish/mcuxClAead_verify). The finalization generates + * the output tag and destroys the context. The verification generates and compares the output + * tag and destroys the context. After the finalization/verification step, no further updates + * are possible. + * + * The targeted AEAD algorithm is selected by passing one of the offered algorithm mode + * descriptors (@ref mcuxClAead_Modes), which are listed in file mcuxClAead_Modes.h + * + * */ + +#ifndef MCUXCLAEAD_H_ +#define MCUXCLAEAD_H_ + +#include // Exported features flags header + +#include +#include +#include + + +#endif /* MCUXCLAEAD_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Constants.h b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Constants.h new file mode 100644 index 000000000..6f1ac7161 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Constants.h @@ -0,0 +1,47 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead_Constants.h + * @brief Constants for use with the mcuxClAead component */ + +#ifndef MCUXCLAEAD_CONSTANTS_H_ +#define MCUXCLAEAD_CONSTANTS_H_ + +/** + * @defgroup mcuxClAead_Constants mcuxClAead_Constants + * @brief Constants of @ref mcuxClAead component + * @ingroup mcuxClAead + * @{ + */ + +/** + * @defgroup MCUXCLAEAD_STATUS_ MCUXCLAEAD_STATUS_ + * @brief Return code definitions + * @ingroup mcuxClAead_Constants + * @{ + */ + +#include // Exported features flags header + +/* Error codes */ +/* TODO CLNS-8684: Unionize and describe return codes */ +#define MCUXCLAEAD_STATUS_ERROR ((mcuxClAead_Status_t) 0x01115330u) +#define MCUXCLAEAD_STATUS_FAULT_ATTACK ((mcuxClAead_Status_t) 0x0111F0F0u) +#define MCUXCLAEAD_STATUS_OK ((mcuxClAead_Status_t) 0x01112E03u) +#define MCUXCLAEAD_STATUS_NOT_OK ((mcuxClAead_Status_t) 0x011153FCu) + +/**@}*/ + +/**@}*/ + +#endif /* MCUXCLAEAD_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Functions.h b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Functions.h new file mode 100644 index 000000000..3fdecf23f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Functions.h @@ -0,0 +1,264 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead_Functions.h + * @brief Top-level API of the mcuxClAead component */ + +#ifndef MCUXCLAEAD_FUNCTIONS_H_ +#define MCUXCLAEAD_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClAeadOneShot One-shot AEAD interfaces + * @brief Interfaces to perform AEAD operations in one shot. + * @ingroup mcuxClAead + * @{ + */ +/** + * @brief One-shot authenticated encryption/decryption function + * @api + * + * This function performs an authenticated encryption/decryption operation in one shot. + * The algorithm to be used will be determined based on the mode that is provided. + * + * For example, to perform an AES authenticated encryption operation with a + * 128-bit key in GCM mode on padded data, the following needs to be provided: + * - AES128 key + * - AES GCM encryption mode + * - Nonce + * - Plain input data + * - Associated data + * - Output data buffer + * - Output length buffer, to store the amount of written bytes + * - Tag buffer, to store the authentication tag + * + * @param session Handle for the current CL session. + * @param key Key to be used to encrypt the data. + * @param mode AEAD mode that should be used during the encryption + * operation. + * @param[in] pNonce Pointer to the buffer that contains the nonce. + * @param nonceLength Number of bytes of nonce data in the @p nonce buffer. + * @param[in] pIn Pointer to the input buffer that contains the plain + * data that need to be authenticated and encrypted. + * @param inLength Number of bytes of plain data in the @p in buffer. + * @param[in] pAdata Associated data for the authenticated encryption + * operation. Data format depends on the chosen @p mode. + * @param adataLength Number of bytes of associated data in the @p adata + * buffer. + * @param[out] pOut Pointer to the output buffer where the authenticated + * encrypted data needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of + * authenticated encrypted data that have been written + * to the @p out buffer. + * @param[out] pTag Pointer to the output buffer where the tag needs to + * be written. + * @param tagLength Number of bytes of tag data that will be written to + * the @p tag buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength +); + +/** + * @defgroup mcuxClAeadMultiPart Multi-part AEAD interfaces + * @brief Interfaces to perform AEAD operations in multiple parts. + * @ingroup mcuxClAead + * @{ + */ +/** + * @brief Multi-part authenticated encryption/decryption initialization function + * @api + * + * This function performs the initialization for a multi part authenticated + * encryption/decryption operation. The algorithm to be used will be determined + * based on the key and mode that are provided. + * + * @param session Handle for the current CL session. + * @param pContext AEAD context which is used to maintain the state and + * store other relevant information about the operation. + * @param key Key to be used to encrypt the data. + * @param mode AEAD mode that should be used during the + * encryption/decryption operation. + * @param[in] pNonce Pointer to the buffer that contains the nonce. + * @param nonceLength Number of bytes of nonce data in the @p nonce buffer. + * @param inLength Number of bytes of plain data that will be processed. + * @param adataLength Number of bytes of associated data that will be + * processed. + * @param tagLength Number of bytes to be used for the authentication tag. + * @return status + */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_init( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + uint32_t inLength, + uint32_t adataLength, + uint32_t tagLength +); /* init encrypt */ + +/** + * @brief Multi-part authenticated encryption/decryption processing function + * for the regular data (authenticated and encrypted) + * @api + * + * This function performs the processing of (a part of) a data stream for an + * authenticated encryption/decryption operation. The algorithm and key to be + * used will be determined based on the context that is provided. + * + * @param session Handle for the current CL session. + * @param pContext AEAD context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pIn Pointer to the input buffer that contains the data + * that needs to be processed. + * @param inLength Number of bytes of data in the @p in buffer. + * @param[out] pOut Pointer to the output buffer where the processed data + * needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of + * processed data that have been written to the @p out + * buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); /* update */ + +/** + * @brief Multi-part authenticated encryption/decryption processing function + * for the associated data (authenticated only) + * @api + * + * This function performs the processing of (a part of) an associated data + * stream for an authenticated encryption/decryption operation. The algorithm + * and key to be used will be determined based on the context that is provided. + * + * @param session Handle for the current CL session. + * @param pContext AEAD context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pAdata Associated data that needs to be proccessed. + * @param adataLength Number of bytes of associated data in the @p adata + * buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_process_adata) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process_adata( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength +); /* update associated data */ + +/** + * @brief Multi-part authenticated encryption/decryption finalization function + * @api + * + * This function performs the finalization of an authenticated encryption or + * decryption operation and produces the authentication tag. The algorithm and + * key to be used will be determined based on the context that is provided. + * + * Note: the taglength is already specified when the INIT function is called. + * + * @param session Handle for the current CL session. + * @param pContext AEAD context which is used to maintain the state and + * store other relevant information about the operation. + * @param[out] pOut Pointer to the output buffer where the processed data + * needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of + * processed data that have been written to the @p out + * buffer. + * @param[out] pTag Pointer to the output buffer where the tag needs to + * be written. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_finish( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag +); /* finalize encrypt/decrypt + output tag */ + +/** + * @brief Multi-part authenticated decryption verification function + * @api + * + * This function performs the finalization of an authenticated decryption + * operation and verifies the authentication tag. The algorithm and key to be + * used will be determined based on the context that is provided. + * + * This function can be used as an alternative for @p mcuxClAead_finish when one + * also wants to perform the tag verification step. + * + * Note: the taglength is already specified when the INIT function is called. + * + * @param session Handle for the current CL session. + * @param pContext AEAD context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pTag Pointer to the buffer that contains the tag. + * @param[out] pOut Pointer to the output buffer where the authenticated + * decrypted data needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of + * authenticated decrypted data that have been written + * to the @p out buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAead_verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_verify( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pTag, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); /* finalize decrypt + compare tag */ + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEAD_FUNCTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Types.h b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Types.h new file mode 100644 index 000000000..2f08b6a81 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/inc/mcuxClAead_Types.h @@ -0,0 +1,118 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021,2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead_Types.h + * @brief Type definitions for the mcuxClAead component + */ + +#ifndef MCUXCLAEAD_TYPES_H_ +#define MCUXCLAEAD_TYPES_H_ + +#include // Exported features flags header + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup clAeadTypes AEAD type definitions + * @brief Types used by the AEAD operations. + * @ingroup mcuxClAead + * @{ + */ + +/** + * @brief AEAD mode/algorithm descriptor structure + * + * This structure captures all the information that the AEAD interfaces need + * to know about a particular AEAD mode/algorithm. + */ +struct mcuxClAead_ModeDescriptor; + +/** + * @brief AEAD mode/algorithm descriptor type + * + * This type captures all the information that the AEAD interfaces need to + * know about a particular AEAD mode/algorithm. + */ +typedef struct mcuxClAead_ModeDescriptor mcuxClAead_ModeDescriptor_t; + + +/** + * @brief AEAD mode/algorithm type + * + * This type is used to refer to an AEAD mode/algorithm. + */ +typedef const mcuxClAead_ModeDescriptor_t * const mcuxClAead_Mode_t; + +/** + * @brief Aead selftest mode/algorithm descriptor structure + * + * This structure captures all the information that the Aead selftest interfaces need + * to know about a particular Aead selftest mode/algorithm. + */ +struct mcuxClAead_TestDescriptor; + +/** + * @brief Aead selftest mode/algorithm descriptor type + * + * This type captures all the information that the Aead selftest interfaces need + * to know about a particular Aead selftest mode/algorithm. + */ +typedef struct mcuxClAead_TestDescriptor mcuxClAead_TestDescriptor_t; + +/** + * @brief Aead selftest mode/algorithm type + * + * This type is used to refer to a Aead selftest mode/algorithm. + */ +typedef const mcuxClAead_TestDescriptor_t * const mcuxClAead_Test_t; + +/** + * @brief AEAD context structure + * + * This structure is used in the multi-part interfaces to store the + * information about the current operation and the relevant internal state. + */ +struct mcuxClAead_Context; + +/** + * @brief AEAD context type + * + * This type is used in the multi-part interfaces to store the information + * about the current operation and the relevant internal state. + */ +typedef struct mcuxClAead_Context mcuxClAead_Context_t; + +/** + * @brief AEAD status code + * + * This type provides information about the status of the AEAD operation that + * has been performed. + */ +typedef uint32_t mcuxClAead_Status_t; + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEAD_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAead/src/mcuxClAead.c b/components/els_pkc/src/comps/mcuxClAead/src/mcuxClAead.c new file mode 100644 index 000000000..0aff46b6f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAead/src/mcuxClAead.c @@ -0,0 +1,233 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAead.c + * @brief Implementation of the multipart and one shot functions of the mcuxClAead component */ + +#include +#include +#include +#include +#include +#include + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_crypt); + + MCUX_CSSL_FP_FUNCTION_CALL(status, mode->crypt( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mode, + /* mcuxCl_InputBuffer_t pNonce, */ pNonce, + /* uint32_t nonceLength, */ nonceLength, + /* mcuxCl_InputBuffer_t pIn, */ pIn, + /* uint32_t inLength, */ inLength, + /* mcuxCl_InputBuffer_t pAdata, */ pAdata, + /* uint32_t adataLength, */ adataLength, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ pTag, + /* uint32_t tagLength, */ tagLength + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_crypt, MCUXCLAEAD_STATUS_ERROR, + mode->protection_token_crypt); + } + + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_crypt, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + mode->protection_token_crypt); +} + + + + + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_init( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + uint32_t inLength, + uint32_t adataLength, + uint32_t tagLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_init); + + MCUX_CSSL_FP_FUNCTION_CALL(status, mode->init( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pContext, + /* mcuxClKey_Handle_t key, */ key, + /* mcuxClAead_Mode_t mode, */ mode, + /* mcuxCl_InputBuffer_t pNonce, */ pNonce, + /* uint32_t nonceLength, */ nonceLength, + /* uint32_t inLength, */ inLength, + /* uint32_t adataLength, */ adataLength, + /* uint32_t tagLength, */ tagLength + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_init, MCUXCLAEAD_STATUS_ERROR, + mode->protection_token_init); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_init, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + mode->protection_token_init); +} + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_process); + + MCUX_CSSL_FP_FUNCTION_CALL(status, pContext->mode->process( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pContext, + /* mcuxCl_InputBuffer_t pIn, */ pIn, + /* uint32_t inLength, */ inLength, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_process, MCUXCLAEAD_STATUS_ERROR, + pContext->mode->protection_token_process); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_process, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pContext->mode->protection_token_process); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_process_adata) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_process_adata( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_process_adata); + + MCUX_CSSL_FP_FUNCTION_CALL(status, pContext->mode->processAad( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pContext, + /* mcuxCl_InputBuffer_t pAdata, */ pAdata, + /* uint32_t adataLength, */ adataLength + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_process_adata, MCUXCLAEAD_STATUS_ERROR, + pContext->mode->protection_token_processAad); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_process_adata, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pContext->mode->protection_token_processAad); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_finish( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_finish); + + + MCUX_CSSL_FP_FUNCTION_CALL(status, pContext->mode->finish( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pContext, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ pTag + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_finish, MCUXCLAEAD_STATUS_ERROR, + pContext->mode->protection_token_finish); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_finish, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pContext->mode->protection_token_finish); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAead_verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAead_verify( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pTag, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAead_verify); + + MCUX_CSSL_FP_FUNCTION_CALL(status, pContext->mode->verify( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pContext, + /* mcuxCl_InputBuffer_t pTag, */ pTag, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength + )); + + if(MCUXCLAEAD_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_verify, MCUXCLAEAD_STATUS_ERROR, + pContext->mode->protection_token_verify); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAead_verify, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pContext->mode->protection_token_verify); +} + diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Common_Functions.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Common_Functions.h new file mode 100644 index 000000000..ffed35dfb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Common_Functions.h @@ -0,0 +1,98 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Common_Functions.h + * @brief Internal function declaration for the mcuxClAeadModes component */ + +#ifndef MCUXCLAEADMODES_COMMON_FUNCTIONS_H_ +#define MCUXCLAEADMODES_COMMON_FUNCTIONS_H_ + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_process_adata, mcuxClAead_process_aad_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_process_adata( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_process, mcuxClAead_process_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_process( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_finish, mcuxClAead_finish_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_finish( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_verify, mcuxClAead_verify_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_verify( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pTag, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); + + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_init( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + uint32_t inLength, + uint32_t adataLength, + uint32_t tagLength +); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength +); + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /*MCUXCLAEADMODES_COMMON_FUNCTIONS_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Algorithms.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Algorithms.h new file mode 100644 index 000000000..c60bf912c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Algorithms.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Algorithms.h + * @brief Internal exports of the algorithm descriptors for the mcuxClAeadModes component + */ + +#ifndef MCUXCLAEADMODES_ELS_ALGORITHMS_H_ +#define MCUXCLAEADMODES_ELS_ALGORITHMS_H_ + +#include + +extern const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_dec; + +extern const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_enc; + +extern const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_dec; + +extern const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_enc; + + +#endif /* MCUXCLAEADMODES_ELS_ALGORITHMS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Functions.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Functions.h new file mode 100644 index 000000000..38618d9f9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Functions.h @@ -0,0 +1,86 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Functions.h + * @brief Internal function declaration for the mcuxClAeadModes component */ + +#ifndef MCUXCLAEADMODES_ELS_FUNCTIONS_H_ +#define MCUXCLAEADMODES_ELS_FUNCTIONS_H_ + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_SkeletonAesCcm) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_SkeletonAesCcm( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_EngineAesCcmEls) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_EngineAesCcmEls ( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_SkeletonAesGcm) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_SkeletonAesGcm( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClAeadModes_EngineAesGcmEls) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_EngineAesGcmEls ( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEADMODES_ELS_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Types.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Types.h new file mode 100644 index 000000000..9ba0cbfa3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Els_Types.h @@ -0,0 +1,140 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Types.h + * @brief Internal: Definitions type for the mcuxClAeadModes component */ + + +#ifndef MCUXCLAEADMODES_ELS_TYPES_H_ +#define MCUXCLAEADMODES_ELS_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup MCUXCLAEADMODES_OPTION_ MCUXCLAEADMODES_OPTION_ + * @brief Options for the skeleton function + * @ingroup mcuxClAead_Internal_Types + * @{ + */ + +/* Options for the skeleton function */ +#define MCUXCLAEADMODES_OPTION_ONESHOT 0x0000000Fu +#define MCUXCLAEADMODES_OPTION_INIT 0x00000001u +#define MCUXCLAEADMODES_OPTION_PROCESS_AAD 0x00000002u +#define MCUXCLAEADMODES_OPTION_PROCESS 0x00000004u +#define MCUXCLAEADMODES_OPTION_FINISH 0x00000008u +#define MCUXCLAEADMODES_OPTION_VERIFY 0x00000010u + +/* Options for the engine function */ +#define MCUXCLAEADMODES_ENGINE_OPTION_AUTH 0x00000001u +#define MCUXCLAEADMODES_ENGINE_OPTION_ENC 0x00000002u +#define MCUXCLAEADMODES_ENGINE_OPTION_AEAD 0x00000003u +#define MCUXCLAEADMODES_ENGINE_OPTION_INIT 0x00000008u +#define MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL MCUXCLAEADMODES_ENGINE_OPTION_INIT +#define MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START 0x00000010u +#define MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT 0x00000020u +#define MCUXCLAEADMODES_ENGINE_OPTION_AAD 0x00000040u +#define MCUXCLAEADMODES_ENGINE_OPTION_DATA 0x00000080u +#define MCUXCLAEADMODES_ENGINE_OPTION_DATA_FINAL 0x00000100u +#define MCUXCLAEADMODES_ENGINE_OPTION_FINISH 0x00000200u + +#define MCUXCLAEADMODES_ENGINE_OPTION_IV_MASK (MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL | MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START | MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT) +#define MCUXCLAEADMODES_ENGINE_OPTION_DATA_MASK (MCUXCLAEADMODES_ENGINE_OPTION_DATA | MCUXCLAEADMODES_ENGINE_OPTION_DATA_FINAL) + + +struct mcuxClAeadModes_Context; +typedef struct mcuxClAeadModes_Context mcuxClAeadModes_Context_t; + +/* Offset for the expected final address from the input address to compare with the DMA final output address */ +#define MCUXCLAEADMODES_DMA_STEP 0x50u +/** + * @brief Function type for an AEAD mode skeleton function + * + * An AEAD mode skeleton function encrypts or decrypts the input message @p pIn to the output @p pOut according to the @p mode. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_ModeSkeleton_t) ( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength, + uint32_t options //!< 15: oneshot, 1: init, 2: update aad, 4: update, 8: finish, 16: verify +); + +/** + * @brief Function type for an AEAD mode engine function + * + * An AEAD mode engine function encrypts or decrypts a single block @p pIn to the output @p pOut. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) (*mcuxClAead_ModeEngine_t) ( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t options //!< 1: auth, 2: enc, 3: aead, 4: init, 8: finish +); + +/** + * @brief AEAD mode/algorithm descriptor structure + * + * This structure captures all the information that the AEAD interfaces need + * to know about a particular AEAD mode/algorithm. + */ +typedef struct mcuxClAead_AlgorithmDescriptor { + mcuxClAead_ModeSkeleton_t pSkeleton; + mcuxClAead_ModeEngine_t pEngine; + uint32_t protection_token_skeleton; + uint32_t protection_token_engine; + uint32_t direction; +} mcuxClAeadModes_AlgorithmDescriptor_t; + +/** + * @brief AEAD context structure + * + * This structure is used in the multi-part interfaces to store the + * information about the current operation and the relevant internal state. + */ +struct mcuxClAeadModes_Context{ + mcuxClAead_Context_t common; + uint8_t partialData[16]; + uint32_t partialDataLength; + uint32_t aadLength; + uint32_t dataLength; + uint32_t tagLength; + uint8_t state[MCUXCLELS_AEAD_CONTEXT_SIZE]; + uint32_t processedDataLength; + mcuxClKey_Descriptor_t *key; +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEADMODES_ELS_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal.h new file mode 100644 index 000000000..c0f1db9f6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal.h @@ -0,0 +1,38 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Internal.h + * @brief Internal definitions and headers for the mcuxClAeadModes component */ + +#ifndef MCUXCLAEADMODES_INTERNAL_H_ +#define MCUXCLAEADMODES_INTERNAL_H_ + +#include // Exported features flags header + +#include +#include + + +#include +#include +#include + +/* Macro used to align the size to the CPU wordsize */ +#define MCUXCLAEADMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) \ + (((uint32_t) (((uint32_t) (size)) + ((sizeof(uint32_t)) - 1U))) & ((uint32_t) (~((sizeof(uint32_t)) - 1U)))) + +/* Macro used to compute number of CPU words */ +#define MCUXCLAEADMODES_INTERNAL_COMPUTE_CPUWORDS(size) \ + (MCUXCLAEADMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) / (sizeof(uint32_t))) + +#endif /* MCUXCLAEADMODES_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal_Constants.h new file mode 100644 index 000000000..93dd7e772 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/internal/mcuxClAeadModes_Internal_Constants.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Internal_Constants.h + * @brief Internal definitions for the mcuxClAeadModes component */ + + +#ifndef MCUXCLAEADMODES_INTERNAL_CONSTANTS_H_ +#define MCUXCLAEADMODES_INTERNAL_CONSTANTS_H_ + +#include // Exported features flags header + +#define MCUXCLAEADMODES_ENCRYPTION (1u) +#define MCUXCLAEADMODES_DECRYPTION (2u) + +/* Buffer B0 contains the first block B0, l(a), and the first AAD bytes */ +#define MCUXCLAEADMODES_CCM_B0_SIZE (32u) + +/* The maximum lengths for tag and nonce are given by the limitations from CCM: + * The only possible lengths are: + * nonce: 7,8,9,10,11,12,13 + * tag: 4,6,8,10,12,14,16 + */ +#define MCUXCLAEADMODES_TAGLEN_MAX (16u) +#define MCUXCLAEADMODES_NONCELEN_MAX (13u) + +#endif /* MCUXCLAEADMODES_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes.h new file mode 100644 index 000000000..938906fea --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes.h @@ -0,0 +1,22 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLAEADMODES_H_ +#define MCUXCLAEADMODES_H_ + +#include // Exported features flags header +#include +#include + + +#endif /* MCUXCLAEADMODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_MemoryConsumption.h new file mode 100644 index 000000000..9f18e5455 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_MemoryConsumption.h @@ -0,0 +1,65 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_MemoryConsumption.h + * @brief Defines the memory consumption for the clAeadModes component */ + +#ifndef MCUXCLAEADMODES_MEMORYCONSUMPTION_H_ +#define MCUXCLAEADMODES_MEMORYCONSUMPTION_H_ +/** + * @defgroup mcuxClAead_MemoryConsumption mcuxClAead_MemoryConsumption + * @brief Defines the memory consumption for the mcuxClAead component + * All work area sizes in bytes are a multiple of CPU wordsize. + * @ingroup mcuxClAead + * @{ + */ + +/* Macro to calculate the WA size in the CPU wordsize */ +#define MCUXCLAEAD_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t))) + + +#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE (124u) +#define MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_CRYPT_CPU_WA_BUFFER_SIZE ) + +#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_INIT_CPU_WA_BUFFER_SIZE ) + + + + +#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_PROCESS_CPU_WA_BUFFER_SIZE ) +#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_PROCESS_ADATA_CPU_WA_BUFFER_SIZE ) +#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_FINISH_CPU_WA_BUFFER_SIZE ) +#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_VERIFY_CPU_WA_BUFFER_SIZE ) +#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE (124u) +#define MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_MAX_CPU_WA_BUFFER_SIZE ) + +#define MCUXCLAEAD_CONTEXT_SIZE (124u) + + +/** @def MCUXCLAEAD_WA_SIZE_MAX + * @brief Define the max workarea size in bytes required for this component. + * Work area sizes in bytes are a multiple of CPU wordsize. + */ +#define MCUXCLAEAD_WA_SIZE_MAX (124u) +#define MCUXCLAEAD_WA_SIZE_IN_WORDS_MAX MCUXCLAEAD_SIZE_IN_CPUWORDS(MCUXCLAEAD_WA_SIZE_MAX ) + +/** + * @} + */ /* mcuxClAead_MemoryConsumption */ + +#endif /* MCUXCLAEADMODES_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_Modes.h b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_Modes.h new file mode 100644 index 000000000..f88c2fae0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/inc/mcuxClAeadModes_Modes.h @@ -0,0 +1,93 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Modes.h + * @brief This file defines the modes for the mcuxClAeadModes component */ + +#ifndef MCUXCLAEADMODES_MODES_H_ +#define MCUXCLAEADMODES_MODES_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @addtogroup mcuxClAead Aead API + * @brief Authenticated Encryption with Associated Data (AEAD) operations. + * @ingroup mcuxClAPI + */ + +/** + * @defgroup clAeadModes AEAD mode definitions + * @brief Modes used by the AEAD operations. + * @ingroup mcuxClAead + */ + + + +/** + * @brief AES CCM encrypt mode descriptor + */ +extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC; + +/** + * @brief AES CCM encrypt mode + */ +static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_ENC = + &mcuxClAead_ModeDescriptor_AES_CCM_ENC; + +/** + * @brief AES CCM decrypt mode descriptor + */ +extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC; + +/** + * @brief AES CCM decrypt mode + */ +static mcuxClAead_Mode_t mcuxClAead_Mode_AES_CCM_DEC = + &mcuxClAead_ModeDescriptor_AES_CCM_DEC; + +/** + * @brief AES GCM encrypt mode descriptor + */ +extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC; + +/** + * @brief AES GCM encrypt mode + */ +static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_ENC = + &mcuxClAead_ModeDescriptor_AES_GCM_ENC; + +/** + * @brief AES GCM decrypt mode descriptor + */ +extern const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC; + +/** + * @brief AES GCM decrypt mode + */ +static mcuxClAead_Mode_t mcuxClAead_Mode_AES_GCM_DEC = + &mcuxClAead_ModeDescriptor_AES_GCM_DEC; +/** @} */ + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAEADMODES_MODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesCcm.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesCcm.c new file mode 100644 index 000000000..d4f5364d7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesCcm.c @@ -0,0 +1,677 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_AesCcm.c + * @brief Implementation of the AES CCM skeleton functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_SkeletonAesCcm) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_SkeletonAesCcm( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ) +{ + /* [Design] + ATTN: pOutLength will be _incremented_ by the number of bytes of encrypted data that have been + written to the @p pOut buffer. Except otherwise mentioned processing steps _output_ data + to pOut and update pOutLength + + Note: + - options is a bitmask: 1: init, 2: aad, 4: process, 8: finish, 15: oneshot, 16: verify + + - Preconditions + - aadLength in context has been initialized + - dataLength in context has been initialized + - tagLength in context has been initialized + - key in context has been initialized + - mode in context has been initialized + - processedDataLength in context has been initialized and maintained + + - Context usage: + - the state contains both the CTR counter and the partial CBC-MAC + + - Common IV processing (options == oneshot / init) + - set partialDataLength in context to zero + - construct the first block using the nonce from the input and the dataLength, aadLength and tagLength from the + context. partialData can be used for this as it is not in use yet. + - process the first block using pEngine(option: auth+init) with zero IV (the engine will update the state in context) + - construct the counter for CTR mode encryption and output to state in context, let it start at 'one' + + - AAD processing (options == oneshot / update aad) + - if adataLength != 0 add the new data from the input to partialData[partialDataLength] and process using + pEngine(option: auth) if possible, adapt partialDataLength and processedDataLength + - process remaining complete blocks from the input using pEngine(option: auth), adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength + - [Assertion] aadLength <= processedDataLength + - if aadLength == processedDataLength padd partialData with zeros and process using pEngine(option: auth), set + partialDataLength to zero + + - Data processing (options == oneshot / update data) + - if inLength != 0 add the new data from the input to partialData and process using pEngine(option: auth+enc) if possible, + adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks from the input using pEngine(option: auth+enc), adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength + - [Assertion] aadLength + dataLength <= processedDataLength + - if aadLength + dataLength == processedDataLength padd partialData with zeros + and process using pEngine(option: auth+enc), set partialDataLength to zero + + - Finalization processing (options == oneshot / finish / verify) + - if partialDataLength != 0 exit with ERROR + - reset counter value to 'zero' (leaving the other fields intact) + - process the CBC-MAC state with pEngine(option: enc), and store the result in partialData + + - Finalization processing (options == oneshot / finish) + - copy tagLength bytes from partialData to the tag + - clean up context + + - Finalization processing (options == verify) + - compare tagLength bytes from partialData to the tag + - clean up context + + - exit + */ + + const mcuxClAeadModes_AlgorithmDescriptor_t* const pAlgo = pContext->common.mode->algorithm; + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_SkeletonAesCcm, + MCUX_CSSL_FP_CONDITIONAL(((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_INIT)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ) + ); + + + +/* + - Common IV processing (options == oneshot / init) + - set partialDataLength in context to zero + - construct the first block using the nonce from the input and the dataLength, aadLength and tagLength from the + context. partialData can be used for this as it is not in use yet. + - process the first block using pEngine(option: auth+init) with zero IV (the engine will update the state in context) + - construct the counter for CTR mode encryption and output to state in context, let it start at 'one' +*/ + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_INIT)) + { + /* Init tag. For CCM, the state store the tag value */ + MCUXCLMEMORY_FP_MEMORY_SET(pContext->state, 0u, MCUXCLAES_BLOCK_SIZE); + + pContext->partialDataLength = 0u; + + /* Generate the plain tag -> CBC-MAC with zero IV */ + // Clear first blocks to guarantee zero padding + MCUXCLMEMORY_FP_MEMORY_SET(pContext->partialData, 0u, MCUXCLAES_BLOCK_SIZE); + + + //Determine whether the nonceLength is less than MCUXCLAES_BLOCK_SIZE -1 to prevent memory overflow later + if(nonceLength > MCUXCLAES_BLOCK_SIZE - 1u) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + // Get length of auth field from parameter + uint8_t t = (uint8_t)((tagLength - 2u) / 2u); + // Get q-1 from parameter + uint8_t q = (uint8_t)(15u - nonceLength); + // Assemble the flags byte for B0 + // -------------------------------------------- + // | 7 | 6 | 5..3 | 2..0 | + // | Reserved | Adata | [(t-2)/2]_3 | [q-1]_3 | + // -------------------------------------------- + uint8_t isheaderLen = (uint8_t)(adataLength > 0u); + pContext->partialData[0u] = (uint8_t)((uint8_t)((isheaderLen << 6u) | (t << 3u)) | (q - 1u)); + + // Create B0 + // ---------------------------------- + // | 0 | 1 .. 15-q | 16-q .. 15 | + // | Flags | N | Q | + // ---------------------------------- + + // Copy nonce N + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->partialData[1u], pNonce,nonceLength); + + // Create Q + uint32_t inMask = 0x000000FFu; + for(int32_t it = 15; it >= (16 - ((int32_t)q)); --it) + { + pContext->partialData[it] = (uint8_t)((inLength & inMask) >> (((15u - (uint8_t)it) * 8u) & 0x0Fu)); + inMask = inMask << 8u; + } + + //Calculate tag over B0 + //process the first block using pEngine(option: auth) with zero IV and output to state in context + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(authRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH | MCUXCLAEADMODES_ENGINE_OPTION_INIT)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != authRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + // Formatting of the associated data + // Encode a and concatenate with associated data + // Check if AAD has to be processed + if(0u == adataLength) + { + pContext->partialDataLength = 0u; + } + // If 0 < a < 2^{16}-2^{8}, then a is encoded as [a]_16, i.e., two octets. + else if(adataLength < ((1UL << 16u) - (1UL << 8u))) + { + // a < 2^{16}-2^{8} + pContext->partialData[0] = (uint8_t)((adataLength & 0x0000FF00u) >> 8u); + pContext->partialData[1] = (uint8_t)((adataLength & 0x000000FFu) >> 0u); + + pContext->partialDataLength = 2u; + } + // If 2^{16}-2^{8} <= a < 2^{32}, then a is encoded as 0xff || 0xfe || [a]_32, i.e., six octets. + else + { + // a >= 2^{16}-2^{8} + pContext->partialData[0] = (uint8_t)0xFFu; + pContext->partialData[1] = (uint8_t)0xFEu; + pContext->partialData[2] = (uint8_t)((adataLength & 0xFF000000u) >> 24u); + pContext->partialData[3] = (uint8_t)((adataLength & 0x00FF0000u) >> 16u); + pContext->partialData[4] = (uint8_t)((adataLength & 0x0000FF00u) >> 8u); + pContext->partialData[5] = (uint8_t)((adataLength & 0x000000FFu) >> 0u); + + pContext->partialDataLength = 6u; + } + + // If 2^{32} <= a < 2^{64}, then a is encoded as 0xff || 0xff || [a]_64, i.e., ten octets. + // This case is not supported in CL and hence does not occur since inLength is uint32_t + + /* Generate the counter for CTR mode encryption */ + // &pContext->state[32] won't be used in CCM mode, so write it to store the counter0Data. + // Use &pContext->state[48] to store the counterData + // Set counter to zero first + MCUXCLMEMORY_FP_MEMORY_SET(&pContext->state[32], 0u, MCUXCLAES_BLOCK_SIZE); + + + // Assemble the flags byte + // ------------------------------------------ + // | 7 | 6 | 5..3 | 2..0 | + // | Reserved | Reserved | 000 | [q-1]_3 | + // ------------------------------------------ + pContext->state[32] = q - 1u; + + // Create CTR0 + // ---------------------------------- + // | 0 | 1 .. 15-q | 16-q .. 15 | + // | Flags | N | 0 | + // ---------------------------------- + + // Copy nonce into counter block + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->state[33],pNonce,nonceLength); + + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->state[48],&pContext->state[32],MCUXCLAES_BLOCK_SIZE); + // Last X bytes of counterData are always equal zero, set last byte to one for the next computation + pContext->state[63] = 0x1u; + } + +/* + - AAD processing (options == oneshot / update aad) + - if adataLength != 0 add the new data from the input to partialData[partialDataLength] and process using + pEngine(option: auth) if possible, adapt partialDataLength and processedDataLength + - process remaining complete blocks from the input using pEngine(option: auth), adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength + - [Assertion] aadLength <= processedDataLength + - if aadLength == processedDataLength padd partialData with zeros and process using pEngine(option: auth), set + partialDataLength to zero +*/ + //below variable definitions are used for flow protection of AAD process + uint32_t mainAadFpFlag = 0u; + uint32_t secondAadFpFlag = 0u; + uint32_t thirdAadFpFlag = 0u; + uint32_t forthAadFpFlag = 0u; + uint32_t fifthAadFpFlag = 0u; + + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS_AAD)) + { + uint32_t lenToCopy = adataLength; + // adataLength is the length of AAD for this AAD process call + if(0u != lenToCopy) + { + if((pContext->partialDataLength + lenToCopy) >= MCUXCLAES_BLOCK_SIZE) + { + secondAadFpFlag = 1u; + uint8_t const* pAad = (uint8_t const*)pAdata; + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->partialData[pContext->partialDataLength],pAad,MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + pAad += MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength; + + lenToCopy -= (MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + pContext->partialDataLength = 0u; + + //Calculate tag over adata + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(aadAuthRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != aadAuthRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + if(lenToCopy >= MCUXCLAES_BLOCK_SIZE) + { + thirdAadFpFlag = 1u; + uint32_t adataBlocks = lenToCopy / MCUXCLAES_BLOCK_SIZE; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(aadBlkAuthRet, pAlgo->pEngine(session, pContext, + pAad, + adataBlocks * MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != aadBlkAuthRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + pAad += adataBlocks * MCUXCLAES_BLOCK_SIZE; + + lenToCopy -= (adataBlocks * MCUXCLAES_BLOCK_SIZE); + } + + if(0u != lenToCopy) + { + forthAadFpFlag = 1u; + //copy remaining data into partialData + MCUXCLMEMORY_FP_MEMORY_COPY(pContext->partialData,pAad,lenToCopy); + pContext->partialDataLength = lenToCopy; + } + } + else + { + mainAadFpFlag = 1u; + //bytes in buffer and new adata is less then blockSize - save data into partialData + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->partialData[pContext->partialDataLength],pAdata,lenToCopy); + pContext->partialDataLength += lenToCopy; + } + } + + //update adata size to processedDataLength in ctx + pContext->processedDataLength += adataLength;//The processedDataLength add the length of each processing + + //Check if we done all adata and if we have some remaining data in buffer, this is for + //the last adata block processing, add zero padding and calc pretag + if((pContext->processedDataLength == pContext->aadLength) && (0u != pContext->partialDataLength)) + { + fifthAadFpFlag = 1u; + /* Apply the padding function specified in the mode on the partial data. */ + MCUXCLMEMORY_FP_MEMORY_SET(&pContext->partialData[pContext->partialDataLength], 0x00u, MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + + //Process remaining adata and create pretag + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(aadPadAuthRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != aadPadAuthRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + pContext->partialDataLength = 0u; + } + } + +/* + - Data processing (options == oneshot / update data) + - if inLength != 0 add the new data from the input to partialData and process using pEngine(option: aead) if possible, + adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks from the input using pEngine(option: aead), adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength + - [Assertion] aadLength + dataLength <= processedDataLength + - if aadLength + dataLength == processedDataLength padd partialData with zeros + and process using pEngine(option: auth+enc), set partialDataLength to zero +*/ + //below variable definitions are used for flow protection of plaintext data process + uint32_t mainProFpFlag = 0u; + uint32_t secondProFpFlag = 0u; + uint32_t thirdProFpFlag = 0u; + uint32_t forthProFpFlag = 0u; + uint8_t *pOutput = pOut; + //below variable definitions are used for flow protection of final one block process + uint32_t mainFinFpFlag = 0u; + + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS)) + { + if(0u != inLength) + { + uint8_t const* pInput = (uint8_t const*)pIn; + if((pContext->partialDataLength + inLength) >= MCUXCLAES_BLOCK_SIZE) + { + mainProFpFlag = 1u; + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->partialData[pContext->partialDataLength],pInput,MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + pInput += MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength; + inLength -= (MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + //update processed input data length to processedDataLength + pContext->processedDataLength += (MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + pContext->partialDataLength = 0u; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(inAeadRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + pOutput, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AEAD)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != inAeadRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + pOutput += MCUXCLAES_BLOCK_SIZE; + *pOutLength += MCUXCLAES_BLOCK_SIZE; + + if(inLength >= MCUXCLAES_BLOCK_SIZE) + { + secondProFpFlag = 1u; + uint32_t inputBlocks = inLength / MCUXCLAES_BLOCK_SIZE; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(inBlkAeadRet, pAlgo->pEngine(session, pContext, + pInput, + inputBlocks * MCUXCLAES_BLOCK_SIZE, + pOutput, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AEAD)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != inBlkAeadRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + pInput += inputBlocks * MCUXCLAES_BLOCK_SIZE; + inLength -= inputBlocks * MCUXCLAES_BLOCK_SIZE; + //update processed input data length to processedDataLength + pContext->processedDataLength += inputBlocks * MCUXCLAES_BLOCK_SIZE; + pOutput += inputBlocks * MCUXCLAES_BLOCK_SIZE; + *pOutLength += inputBlocks * MCUXCLAES_BLOCK_SIZE; + } + + if(0u != inLength) + { + thirdProFpFlag = 1u; + //copy remaining data into blockBuffer + MCUXCLMEMORY_FP_MEMORY_COPY(pContext->partialData,pInput,inLength); + pContext->partialDataLength = inLength; + //update processed input data length to processedDataLength + pContext->processedDataLength += inLength; + } + } + else + { + forthProFpFlag = 1u; + //bytes in buffer and new adata is less then blockSize - save data into partialData + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->partialData[pContext->partialDataLength],pIn,inLength); + pContext->partialDataLength += inLength; + //update processed input data length to processedDataLength + pContext->processedDataLength += inLength; + } + } + + //Check if we done all input data and if we have some remaining data in buffer, this is for + //the last input data block processing, add zero padding and calc final tag + if((pContext->processedDataLength == pContext->dataLength + pContext->aadLength) && (0u != pContext->partialDataLength)) + { + if(pContext->partialDataLength < MCUXCLAES_BLOCK_SIZE) + { + mainFinFpFlag = 1u; + MCUXCLMEMORY_FP_MEMORY_SET(&pContext->partialData[pContext->partialDataLength], 0x00u, MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + //This last block length less then MCUXCLAES_BLOCK_SIZE, so can't directly write result to pOut + //&pContext->state[16] have not been used, so can re-write it to store the CTR result + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(inPaddEncRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + &pContext->state[16], + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_ENC)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != inPaddEncRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* Copy the padding to the output and update pOutLength accordingly. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOutput, + &pContext->state[16], + pContext->partialDataLength, + MCUXCLAES_BLOCK_SIZE); + + + *pOutLength += pContext->partialDataLength; + + if(MCUXCLELS_AEAD_ENCRYPT == pAlgo->direction) + { + //Process remaining data and create pretag + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(inPaddAuthRet, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != inPaddAuthRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + } + else + { + //Process remaining data and create pretag + MCUXCLMEMORY_FP_MEMORY_SET(&pContext->state[16u + pContext->partialDataLength], 0x00u, MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(inPaddAuthRet, pAlgo->pEngine(session, pContext, + &pContext->state[16], + MCUXCLAES_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AUTH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != inPaddAuthRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + } + pContext->partialDataLength = 0u; + } + + } + +/* + - Finalization processing (options == oneshot / finish / verify) + - if partialDataLength != 0 exit with ERROR + - reset counter value to 'zero' (leaving the other fields intact) + - process the CBC-MAC state with pEngine(option: enc), and store the result in partialData +*/ + + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH) || (options == MCUXCLAEADMODES_OPTION_VERIFY)) + { + + + if (0u != pContext->partialDataLength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + //reset counter value to 'zero' (leaving the other fields intact) + MCUXCLMEMORY_FP_MEMORY_COPY(&pContext->state[48],&pContext->state[32],MCUXCLAES_BLOCK_SIZE); + + //Encrypt pretag with counter0 to get final tag + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(finalTagEncRet, pAlgo->pEngine(session, pContext, + pContext->state, + MCUXCLAES_BLOCK_SIZE, + pContext->partialData, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_ENC)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != finalTagEncRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + } + +/* + - Finalization processing (options == oneshot / finish) + - copy tagLength bytes from partialData to the tag + - clean up context +*/ + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH)) + { + MCUXCLMEMORY_FP_MEMORY_COPY(pTag,pContext->partialData,pContext->tagLength); + + //Clear Ctx content + //it will still be used, so can't clear in this step + // MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *)pContext, // sizeof(mcuxClAead_Context_t)); + + + + } + +/* + - Finalization processing (options == verify) + - compare tagLength bytes from partialData to the tag + - clean up context + + - exit +*/ + if (options == MCUXCLAEADMODES_OPTION_VERIFY) + { + MCUX_CSSL_FP_FUNCTION_CALL(compare_result, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pTag, pContext->partialData, pContext->tagLength), + pTag, + pContext->partialData, + pContext->tagLength)); + + if(compare_result != MCUXCSSLMEMORY_STATUS_EQUAL) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_ERROR); + } + + //Clear Ctx content + //it will still be used, so can't clear in this step + // MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *)pContext, // sizeof(mcuxClAead_Context_t)); + + + } + + /* Exit and balance the flow protection. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_SkeletonAesCcm, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS_AAD))), + MCUX_CSSL_FP_CONDITIONAL((secondAadFpFlag == 1u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_CONDITIONAL((thirdAadFpFlag == 1u),pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((forthAadFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ) + ), + MCUX_CSSL_FP_CONDITIONAL((mainAadFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL((fifthAadFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + pAlgo->protection_token_engine + ) + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS))), + MCUX_CSSL_FP_CONDITIONAL((mainProFpFlag == 1u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_CONDITIONAL((secondProFpFlag == 1u),pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((thirdProFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ) + ), + MCUX_CSSL_FP_CONDITIONAL((forthProFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL((mainFinFpFlag == 1u),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLELS_AEAD_DECRYPT == pAlgo->direction),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) + ) + ) + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH) || (options == MCUXCLAEADMODES_OPTION_VERIFY))), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH))), + //MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL(((options == MCUXCLAEADMODES_OPTION_VERIFY)), + //MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) + ) + ); +} + diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesGcm.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesGcm.c new file mode 100644 index 000000000..623ac0588 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_AesGcm.c @@ -0,0 +1,605 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_AesGcm.c + * @brief Implementation of the AES GCM skeleton functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_SkeletonAesGcm) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_SkeletonAesGcm( + mcuxClSession_Handle_t session, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ) +{ + /* [Design] + ATTN: pOutLength will be _incremented_ by the number of bytes of encrypted data that have been + written to the @p pOut buffer. Except otherwise mentioned processing steps _output_ data + to pOut and update pOutLength + + - Preconditions + - aadLength in context has been initialized + - dataLength in context has been initialized + - tagLength in context has been initialized + - key in context has been initialized + - mode in context has been initialized + - processedDataLength in context has been initialized and maintained + + - Context usage: + - the state contains both the counter and the partial MAC + + - Common IV processing (options == oneshot / init) + - set partialDataLength in context to zero + - process IV with ELS and output to state in context + - if the IV length is not 12 use using pEngine(option:iv) to process the complete blocks + - partialData can be used to padd the IV since it is not used at this time + + - AAD processing (options == oneshot / update aad) + - if partialDataLength != 0 add the new data from the input to partialData and process using pEngine(option:aad) + if possible,adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks using pEngine(option:aad) from the input, adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength (this can happen + for oneshot) + - [Assertion] aadLength <= processedDataLength + - if aadLength == processedDataLength padd partialData with zeros and process using pEngine(option:aad), set + partialDataLength to zero + + - Data processing (options == oneshot / update data) + - if partialDataLength != 0 add the new data from the input to partialData and process using pEngine(option:data) + if possible,adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks using pEngine(option:data)from the input, adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength (this can happen + for oneshot) + - [Assertion] aadLength + dataLength <= processedDataLength + - if aadLength + dataLength == processedDataLength padd partialData with zeros + and process using pEngine(option:data), set partialDataLength to zero + + - Finalization processing (options == oneshot / finish / verify) + - if partialDataLength != 0 exit with ERROR + - perform the finalize processing using pEngine(option:finish), store tag in partialData in context + + - Finalization processing (options == oneshot / finish) + - copy tagLength bytes from partialData to the tag + - clean up context + + - Finalization processing (options == verify) + - compare tagLength bytes from partialData to the tag + - clean up context + + - exit + */ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_SkeletonAesGcm); + + const mcuxClAeadModes_AlgorithmDescriptor_t* const pAlgo = pContext->common.mode->algorithm; + + uint32_t bytesToCopy = 0u; + uint32_t bytesCopied = 0u; + uint32_t bytesFullIvBlocks = 0u; + uint32_t bytesRemainingAad = 0u; + uint32_t bytesRemainingData = 0u; + +/* + - Common IV processing (options == oneshot / init) + - set partialDataLength in context to zero + - process IV with ELS and output to state in context + - if the IV length is not 12 use using pEngine(option:iv) to process the complete blocks + - partialData can be used to padd the IV since it is not used at this time +*/ + + /* Number of bytes added by the padding. */ + uint32_t padOutLength = 0u; + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_INIT)) + { + pContext->partialDataLength = 0u; + + if (nonceLength != 12u) + { + uint32_t engineOptions = MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START; + + /* If nonce is not 12 bytes, perform a partial init. Start with the full blocks of the IV */ + bytesFullIvBlocks = (nonceLength / MCUXCLAES_BLOCK_SIZE) * MCUXCLAES_BLOCK_SIZE; + if(0u != bytesFullIvBlocks) + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retIV, pAlgo->pEngine(session, pContext, + pNonce, + bytesFullIvBlocks, + NULL, + NULL, + engineOptions)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retIV) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + engineOptions = MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT; + } + + MCUX_CSSL_FP_FUNCTION_CALL(padResult, mcuxClPadding_addPadding_ISO9797_1_Method1(MCUXCLELS_AEAD_IV_BLOCK_SIZE, + pNonce + bytesFullIvBlocks, + nonceLength - bytesFullIvBlocks, + nonceLength, + pContext->partialData, + &padOutLength)); + + if (MCUXCLPADDING_STATUS_OK != padResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + if(MCUXCLELS_AEAD_IV_BLOCK_SIZE == padOutLength) + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retIV, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLELS_AEAD_IV_BLOCK_SIZE, + NULL, + NULL, + engineOptions)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retIV) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + engineOptions = MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT; + } + + + MCUXCLMEMORY_FP_MEMORY_SET(pContext->partialData, 0u, MCUXCLELS_AEAD_IV_BLOCK_SIZE); + + /* Set nonce length in bits. */ + pContext->partialData[15] = (uint8_t)(nonceLength << 3u); + pContext->partialData[14] = (uint8_t)(nonceLength >> 5u); + pContext->partialData[13] = (uint8_t)(nonceLength >> 13u); + pContext->partialData[12] = (uint8_t)(nonceLength >> 21u); + pContext->partialData[11] = (uint8_t)(nonceLength >> 29u); + + /* Finish the nonce initialization. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retIVFinal, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLELS_AEAD_IV_BLOCK_SIZE, + NULL, + NULL, + engineOptions | MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retIVFinal) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + } + else + { + /* Nonce is 12 bytes. Pad the nonce. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pContext->partialData, + pNonce, + 12u, + MCUXCLELS_AEAD_IV_BLOCK_SIZE); + + pContext->partialData[12] = 0x00u; + pContext->partialData[13] = 0x00u; + pContext->partialData[14] = 0x00u; + pContext->partialData[15] = 0x01u; + + /* Do the nonce initialization. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retIV, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLELS_AEAD_IV_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retIV) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + } + } + + +/* + - AAD processing (options == oneshot / update aad) + - if partialDataLength != 0 add the new data from the input to partialData and process using pEngine(option:aad) + if possible,adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks using pEngine(option:aad) from the input, adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength (this can happen + for oneshot) + - [Assertion] aadLength <= processedDataLength + - if aadLength == processedDataLength padd partialData with zeros and process using pEngine(option:aad), set + partialDataLength to zero +*/ + //below variable definitions are used for flow protection of plaintext data process + uint32_t aadProFPFlag = 0u; + uint32_t aadProFPFlag1 = 0u; + uint32_t aadProFPFlag2 = 0u; + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS_AAD)) + { + /* Number of bytes to possibly copy into the partial data buffer, which is min(free buffer space, new data). */ + bytesToCopy = (((MCUXCLELS_AEAD_AAD_BLOCK_SIZE - pContext->partialDataLength) < (adataLength)) ? + (MCUXCLELS_AEAD_AAD_BLOCK_SIZE - pContext->partialDataLength) : (adataLength)); + + if (pContext->partialDataLength != 0u) + { + aadProFPFlag1 = 1u; + /* Add new data into the partial data buffer and process, if possible. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pContext->partialData + pContext->partialDataLength, + pAdata, + bytesToCopy, + MCUXCLELS_AEAD_AAD_BLOCK_SIZE); + + /* Update the number of bytes in the partial data buffer. */ + pContext->partialDataLength += bytesToCopy; + + if (MCUXCLELS_AEAD_AAD_BLOCK_SIZE == pContext->partialDataLength) + { + aadProFPFlag2 = 1u; + /* partialData now contains a full block, so process it. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retAad, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLELS_AEAD_AAD_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AAD)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retAad) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* The partial data buffer is now empty. */ + pContext->partialDataLength = 0u; + + } + + /* The bytes copied already should not be taken into account further. */ + bytesCopied += bytesToCopy; + adataLength -= bytesToCopy; + pContext->processedDataLength += bytesToCopy; + } + + bytesRemainingAad = (adataLength / MCUXCLELS_AEAD_AAD_BLOCK_SIZE) * MCUXCLELS_AEAD_AAD_BLOCK_SIZE; + if(0u != bytesRemainingAad) + { + /* Process as many remaining full blocks as possible. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retBlkAad, pAlgo->pEngine(session, pContext, + pAdata + bytesCopied, + bytesRemainingAad, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AAD)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retBlkAad) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* The bytes copied already should not be taken into account further. */ + bytesCopied += bytesRemainingAad; + pContext->processedDataLength += bytesRemainingAad; + } + + bytesRemainingAad = adataLength - bytesRemainingAad; + if (0u != bytesRemainingAad) + { + /* If there is still data in the input, copy it to the partial data buffer for the next iteration. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pContext->partialData, + pAdata + bytesCopied, + bytesRemainingAad, + MCUXCLELS_AEAD_AAD_BLOCK_SIZE); + + pContext->partialDataLength = bytesRemainingAad; + pContext->processedDataLength += bytesRemainingAad; + } + + //Check if we done all adata and if we have some remaining data in buffer, this is for + //the last adata block processing, add zero padding and calc + if((pContext->processedDataLength == pContext->aadLength) && (0u != pContext->partialDataLength)) + { + aadProFPFlag = 1u; + /* There is still AAD which needs to be zero-padded and processed. */ + MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pContext->partialData + pContext->partialDataLength, 0u, MCUXCLELS_AEAD_AAD_BLOCK_SIZE - pContext->partialDataLength, MCUXCLELS_AEAD_AAD_BLOCK_SIZE); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retPadAad, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLELS_AEAD_AAD_BLOCK_SIZE, + NULL, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_AAD)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retPadAad) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + pContext->partialDataLength = 0u; + } + + } + +/* + - Data processing (options == oneshot / update data) + - if partialDataLength != 0 add the new data from the input to partialData and process using pEngine(option:data) + if possible,adapt partialDataLength and processedDataLength (this will never be the case for oneshot) + - process remaining complete blocks using pEngine(option:data)from the input, adapt processedDataLength + - add remaining data to partialData, adapt partialDataLength and processedDataLength (this can happen + for oneshot) + - [Assertion] aadLength + dataLength <= processedDataLength + - if aadLength + dataLength == processedDataLength padd partialData with zeros + and process using pEngine(option:data), set partialDataLength to zero +*/ + + //below variable definitions are used for flow protection of plaintext data process + uint32_t dataProFPFlag = 0u; + uint32_t dataProFPFlag1 = 0u; + uint32_t dataProFPFlag2 = 0u; + uint8_t *pOutput = pOut; + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS)) + { + /* Number of bytes to possibly copy into the partial data buffer. */ + bytesCopied = 0u; + bytesToCopy = (((MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength) < (inLength)) ? + (MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength) : (inLength)); + + if (pContext->partialDataLength != 0u) + { + dataProFPFlag1 = 1u; + /* Process input data. */ + /* Add new data into the partial data buffer and process, if possible. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pContext->partialData + pContext->partialDataLength, + pIn, + bytesToCopy, + MCUXCLAES_BLOCK_SIZE); + + /* Update the number of bytes in the partial data buffer. */ + pContext->partialDataLength += bytesToCopy; + + if (MCUXCLAES_BLOCK_SIZE == pContext->partialDataLength) + { + dataProFPFlag2 = 1u; + /* partialData now contains a full block, so process it. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retData, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + pOutput, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_DATA)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* The partial data buffer is now empty. */ + pContext->partialDataLength = 0u; + + /* Write to pOutLength how many bytes have been written, and update the output buffer */ + *pOutLength += MCUXCLAES_BLOCK_SIZE; + pOutput += MCUXCLAES_BLOCK_SIZE; + } + + /* The bytes copied already should not be taken into account further. */ + pContext->processedDataLength += bytesToCopy; + bytesCopied += bytesToCopy; + inLength -= bytesToCopy; + } + + bytesRemainingData = (inLength / MCUXCLAES_BLOCK_SIZE) * MCUXCLAES_BLOCK_SIZE; + if(0u != bytesRemainingData) + { + /* Process as many remaining full blocks as possible. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retBlkData, pAlgo->pEngine(session, pContext, + pIn + bytesCopied, + bytesRemainingData, + pOutput, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_DATA)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retBlkData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + pContext->processedDataLength += bytesRemainingData; + /* The bytes copied already should not be taken into account further. */ + bytesCopied += bytesRemainingData; + /* Write to pOutLength how many bytes have been written. */ + *pOutLength += bytesRemainingData; + pOutput += bytesRemainingData; + } + + bytesRemainingData = inLength - bytesRemainingData; + if (0u != bytesRemainingData) + { + /* If there is still data in the input, copy it to the partial data buffer for the next iteration. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pContext->partialData, + pIn + bytesCopied, + bytesRemainingData, + MCUXCLAES_BLOCK_SIZE); + pContext->partialDataLength = bytesRemainingData; + pContext->processedDataLength += bytesRemainingData; + } + + //Check if we done all input data and if we have some remaining data in buffer, this is for + //the last input data block processing, add zero padding and calc + if((pContext->processedDataLength == pContext->dataLength + pContext->aadLength) && (0u != pContext->partialDataLength)) + { + dataProFPFlag = 1u; + /* There is still data which needs to be zero-padded and processed. */ + MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pContext->partialData + pContext->partialDataLength, 0u, MCUXCLAES_BLOCK_SIZE - pContext->partialDataLength, MCUXCLAES_BLOCK_SIZE); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(redFinalData, pAlgo->pEngine(session, pContext, + pContext->partialData, + MCUXCLAES_BLOCK_SIZE, + pOutput, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_DATA_FINAL)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != redFinalData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* Write to pOutLength how many bytes have been processed. */ + *pOutLength += pContext->partialDataLength; + + /* The partial data buffer is now empty. */ + pContext->partialDataLength = 0u; + } + + } + +/* + - Finalization processing (options == oneshot / finish / verify) + - if partialDataLength != 0 exit with ERROR + - perform the finalize processing using pEngine(option:finish), store tag in partialData in context +*/ + + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH) || (options == MCUXCLAEADMODES_OPTION_VERIFY)) + { + if (pContext->partialDataLength != 0u) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + /* Call the finalize function. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(retFinal, pAlgo->pEngine(session, pContext, + NULL, + 0u, + pContext->partialData, + NULL, + MCUXCLAEADMODES_ENGINE_OPTION_FINISH)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != retFinal) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + } + +/* + - Finalization processing (options == oneshot / finish) + - copy tagLength bytes from partialData to the tag + - clean up context +*/ + if ((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH)) + { + MCUXCLMEMORY_FP_MEMORY_COPY(pTag,pContext->partialData,tagLength); + } + + // TODO: clean up context? + +/* + - Finalization processing (options == verify) + - compare tagLength bytes from partialData to the tag + - clean up context + + - exit +*/ + if (options == MCUXCLAEADMODES_OPTION_VERIFY) + { + MCUX_CSSL_FP_FUNCTION_CALL(compare_result, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pTag, pContext->partialData, tagLength), + pTag, + pContext->partialData, + tagLength)); + + if(compare_result != MCUXCSSLMEMORY_STATUS_EQUAL) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + } + + /* Exit and balance the flow protection. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_INIT)), + MCUX_CSSL_FP_CONDITIONAL((nonceLength != 12u), MCUX_CSSL_FP_CONDITIONAL((0u != bytesFullIvBlocks), pAlgo->protection_token_engine), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method1), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLELS_AEAD_IV_BLOCK_SIZE == padOutLength), pAlgo->protection_token_engine), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) + ), + MCUX_CSSL_FP_CONDITIONAL((nonceLength == 12u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS_AAD))), + MCUX_CSSL_FP_CONDITIONAL((aadProFPFlag1 == 1u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((aadProFPFlag2 == 1u), pAlgo->protection_token_engine) + ), + MCUX_CSSL_FP_CONDITIONAL((0u != ((adataLength / MCUXCLELS_AEAD_AAD_BLOCK_SIZE) * MCUXCLELS_AEAD_AAD_BLOCK_SIZE)), pAlgo->protection_token_engine), + MCUX_CSSL_FP_CONDITIONAL((bytesRemainingAad != 0u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + MCUX_CSSL_FP_CONDITIONAL((aadProFPFlag != 0u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + pAlgo->protection_token_engine) + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_PROCESS))), + MCUX_CSSL_FP_CONDITIONAL((dataProFPFlag1 == 1u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((dataProFPFlag2 == 1u), pAlgo->protection_token_engine) + ), + MCUX_CSSL_FP_CONDITIONAL((0u != ((inLength / MCUXCLAES_BLOCK_SIZE) * MCUXCLAES_BLOCK_SIZE)), pAlgo->protection_token_engine), + MCUX_CSSL_FP_CONDITIONAL((bytesRemainingData != 0u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + MCUX_CSSL_FP_CONDITIONAL((dataProFPFlag != 0u), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + pAlgo->protection_token_engine) + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH) || (options == MCUXCLAEADMODES_OPTION_VERIFY))), + pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((((options == MCUXCLAEADMODES_OPTION_ONESHOT) || (options == MCUXCLAEADMODES_OPTION_FINISH))), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL(((options == MCUXCLAEADMODES_OPTION_VERIFY)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) + ) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_CcmEngineAes.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_CcmEngineAes.c new file mode 100644 index 000000000..8442518df --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_CcmEngineAes.c @@ -0,0 +1,274 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_CcmEngineAes.c + * @brief implementation of the AES CCM Engine functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_EngineAesCcmEls) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_EngineAesCcmEls ( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ) +{ + /* [Design] + + - Note: + - options is a bitmask: 1: auth, 2: enc, 3: aead, 4: init, 8: finish + - processing is done in this particular order such that in-place encryption/decryption is supported + + - Preconditions + - mode in context has been initialized + - inLength is a multiple of the block size (16 bytes) + + - Initialization + - set pData equal to pIn + + - Decryption (options == enc / aead AND direction = decryption) + - set pData equal to pOut + - use ELS in CTR mode to decrypt the data pIn and store the output at pOut + + - Authentication (options == auth / aead) + - use ELS in CBC-MAC mode to update the state in the context with the contents of pData + + - Encryption (options == enc / aead AND direction = encryption) + - use ELS in CTR mode to encrypt the data pIn and store the output at pOut + + - exit + */ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_EngineAesCcmEls); + const uint32_t direction = pContext->common.mode->algorithm->direction; + + /* Initialize ELS key info based on the key in the context. */ + mcuxClEls_KeyIndex_t keyIdx = (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key); + uint8_t const * pKey = mcuxClKey_getLoadedKeyData(pContext->key); + uint32_t keyLength = mcuxClKey_getSize(pContext->key); + + /* Initialize ELS CMAC options. */ + mcuxClEls_CmacOption_t cmacOpt; + cmacOpt.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + cmacOpt.bits.finalize = MCUXCLELS_CMAC_FINALIZE_DISABLE; + + /* Initialize ELS Cipher options. */ + mcuxClEls_CipherOption_t cipherElsOpt; + cipherElsOpt.word.value = 0u; + cipherElsOpt.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; + cipherElsOpt.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR; + cipherElsOpt.bits.cphsoe = MCUXCLELS_CIPHER_STATE_OUT_ENABLE; + #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + cipherElsOpt.bits.cphsie = MCUXCLELS_CIPHER_STATE_IN_ENABLE; + #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + // Get key location + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + cmacOpt.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE; + cipherElsOpt.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + cmacOpt.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE; + cipherElsOpt.bits.extkey = MCUXCLELS_CIPHER_INTERNAL_KEY; + } + else + { + // Error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + if(options == MCUXCLAEADMODES_ENGINE_OPTION_INIT) + { + + } + + if(((options & MCUXCLAEADMODES_ENGINE_OPTION_ENC) == MCUXCLAEADMODES_ENGINE_OPTION_ENC) + && (MCUXCLELS_AEAD_DECRYPT == direction)) + { + MCUX_CSSL_FP_FUNCTION_CALL(ctrRet, mcuxClEls_Cipher_Async(cipherElsOpt, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + &pContext->state[48], + pOut)); + + if(MCUXCLELS_STATUS_OK_WAIT != ctrRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(ctrWaitRet, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != ctrWaitRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(&pContext->state[48], MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + + } + + if((options & MCUXCLAEADMODES_ENGINE_OPTION_AUTH) == MCUXCLAEADMODES_ENGINE_OPTION_AUTH) + { + if((options == MCUXCLAEADMODES_ENGINE_OPTION_AEAD) && (MCUXCLELS_AEAD_DECRYPT == direction)) + { + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult, mcuxClEls_Cmac_Async(cmacOpt, + keyIdx, + pKey, + keyLength, + pOut, + inLength, + pContext->state)); + + if( MCUXCLELS_STATUS_OK_WAIT != cmacResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + } + else + { + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult, mcuxClEls_Cmac_Async(cmacOpt, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + pContext->state)); + if( MCUXCLELS_STATUS_OK_WAIT != cmacResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + } + + MCUX_CSSL_FP_FUNCTION_CALL(cmacWaitResult, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != cmacWaitResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + + } + + if(((options & MCUXCLAEADMODES_ENGINE_OPTION_ENC) == MCUXCLAEADMODES_ENGINE_OPTION_ENC) + && (MCUXCLELS_AEAD_ENCRYPT == direction)) + { + MCUX_CSSL_FP_FUNCTION_CALL(ctrRet, mcuxClEls_Cipher_Async(cipherElsOpt, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + &pContext->state[48], + pOut)); + + if(MCUXCLELS_STATUS_OK_WAIT != ctrRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(ctrWaitRet, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != ctrWaitRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(&pContext->state[48], MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + } + + /* Exit and balance the flow protection. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_ENC) == MCUXCLAEADMODES_ENGINE_OPTION_ENC) + && (MCUXCLELS_AEAD_DECRYPT == direction), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_AUTH) == MCUXCLAEADMODES_ENGINE_OPTION_AUTH), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_ENC) == MCUXCLAEADMODES_ENGINE_OPTION_ENC) + && (MCUXCLELS_AEAD_ENCRYPT == direction), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ) + ); +} +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_enc = { + .pSkeleton = mcuxClAeadModes_SkeletonAesCcm, + .pEngine = mcuxClAeadModes_EngineAesCcmEls, + .protection_token_skeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_SkeletonAesCcm), + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_EngineAesCcmEls), + .direction = MCUXCLELS_AEAD_ENCRYPT +}; + +const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_dec = { + .pSkeleton = mcuxClAeadModes_SkeletonAesCcm, + .pEngine = mcuxClAeadModes_EngineAesCcmEls, + .protection_token_skeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_SkeletonAesCcm), + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_EngineAesCcmEls), + .direction = MCUXCLELS_AEAD_DECRYPT +}; +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() \ No newline at end of file diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_GcmEngineAes.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_GcmEngineAes.c new file mode 100644 index 000000000..39c694871 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_GcmEngineAes.c @@ -0,0 +1,331 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_GcmEngineAes.c + * @brief implementation of the AES GCM Engine functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_EngineAesGcmEls) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_EngineAesGcmEls ( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClAeadModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t options //!< options is a bitmask with one bit reserved for each of the operations + ) +{ + /* [Design] + + - Note: + - options is a bitmask: 1: aad, 2: iv, 4: data, 8: finish + + - Preconditions + - mode in context has been initialized + - inLength is a multiple of the block size (16 bytes) + + - IV (options == iv) + - if(options == finish), the IV final process + - or use ELS in auth cipher mode initialize stage to create the partial starting counter state J0 + + - AAD (options == aad) + - use ELS in auth cipher mode AAD stage to create the starting tag + + - DATA (options == data) + - use ELS in auth cipher mode Process message stage to output the processed text to pOut and update the tag to state of Context + + - FINAL (options == finish) + - use ELS in auth cipher mode Final stage to create the final tag to pOut + + - exit + */ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_EngineAesGcmEls); + + /* Initialize ELS key info based on the key in the context. */ + mcuxClEls_KeyIndex_t keyIdx = (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key); + uint8_t const * pKey = mcuxClKey_getLoadedKeyData(pContext->key); + uint32_t keyLength = mcuxClKey_getSize(pContext->key); + + /* Initialize ELS options. */ + mcuxClEls_AeadOption_t elsOptions; + elsOptions.word.value = 0u; + elsOptions.bits.dcrpt = (uint8_t)pContext->common.mode->algorithm->direction; + elsOptions.bits.acpsie = (uint8_t)MCUXCLELS_AEAD_STATE_IN_ENABLE; + elsOptions.bits.lastinit = (uint8_t)MCUXCLELS_AEAD_LASTINIT_FALSE; + + if (MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + elsOptions.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; + } + else if (MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + elsOptions.bits.extkey = MCUXCLELS_CIPHER_INTERNAL_KEY; + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + if(0u != (options & MCUXCLAEADMODES_ENGINE_OPTION_IV_MASK)) + { + if((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_MASK) == MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL) + { + /* Disable state input for one-time init */ + elsOptions.bits.acpsie = (uint8_t)MCUXCLELS_AEAD_STATE_IN_DISABLE; + + MCUX_CSSL_FP_FUNCTION_CALL(retInit, mcuxClEls_Aead_Init_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + pContext->state)); + + if (MCUXCLELS_STATUS_OK_WAIT != retInit) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + MCUX_CSSL_FP_FUNCTION_CALL(ivWaitRet, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLAEADMODES_DMA_STEP)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesCcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + if (MCUXCLELS_STATUS_OK != ivWaitRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + } + else + { + if((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START) == MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START) + { + /* Disable state input for first partial init */ + elsOptions.bits.acpsie = (uint8_t)MCUXCLELS_AEAD_STATE_IN_DISABLE; + } + + if((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL) == MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL) + { + /* Enable lastinit for final partial init */ + elsOptions.bits.lastinit = (uint8_t)MCUXCLELS_AEAD_LASTINIT_TRUE; + } + + MCUX_CSSL_FP_FUNCTION_CALL(retInitPartial, mcuxClEls_Aead_PartialInit_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + pContext->state)); + + if(MCUXCLELS_STATUS_OK_WAIT != retInitPartial) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(ivWaitRet, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != ivWaitRet) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLAEADMODES_DMA_STEP)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + } + } + + if((options & MCUXCLAEADMODES_ENGINE_OPTION_AAD) == MCUXCLAEADMODES_ENGINE_OPTION_AAD) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_updateAad, mcuxClEls_Aead_UpdateAad_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + pContext->state)); + + if (ret_updateAad != MCUXCLELS_STATUS_OK_WAIT) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(aadWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (aadWait != MCUXCLELS_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_SkeletonAesGcm, MCUXCLAEAD_STATUS_ERROR); + } + + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state , MCUXCLAEADMODES_DMA_STEP)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + } + + if(0u != (options & MCUXCLAEADMODES_ENGINE_OPTION_DATA_MASK)) + { + if(((options & MCUXCLAEADMODES_ENGINE_OPTION_DATA_FINAL) == MCUXCLAEADMODES_ENGINE_OPTION_DATA_FINAL) + && (MCUXCLAES_BLOCK_SIZE != pContext->partialDataLength)) + { + /* Enable special processing for final, partial block */ + elsOptions.bits.msgendw = (uint8_t)pContext->partialDataLength; + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_updateData, mcuxClEls_Aead_UpdateData_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + pOut, + pContext->state)); + + if (ret_updateData != MCUXCLELS_STATUS_OK_WAIT) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(waitData, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (waitData != MCUXCLELS_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state , MCUXCLAEADMODES_DMA_STEP)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + } + + if((options & MCUXCLAEADMODES_ENGINE_OPTION_FINISH) == MCUXCLAEADMODES_ENGINE_OPTION_FINISH) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_finish, mcuxClEls_Aead_Finalize_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pContext->aadLength, + pContext->dataLength, + pOut, + pContext->state)); + + if (ret_finish != MCUXCLELS_STATUS_OK_WAIT) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(waitFinish, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (waitFinish != MCUXCLELS_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pOut , MCUXCLELS_AEAD_TAG_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + } + + /* Exit and balance the flow protection. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_EngineAesGcmEls, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_MASK) == MCUXCLAEADMODES_ENGINE_OPTION_IV_FINAL), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Aead_Init_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START) == MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_START) + || ((options & MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT) == MCUXCLAEADMODES_ENGINE_OPTION_IV_PARTIAL_CONT), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Aead_PartialInit_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_AAD) == MCUXCLAEADMODES_ENGINE_OPTION_AAD), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Aead_UpdateAad_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL((0u != (options & MCUXCLAEADMODES_ENGINE_OPTION_DATA_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Aead_UpdateData_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ), + MCUX_CSSL_FP_CONDITIONAL(((options & MCUXCLAEADMODES_ENGINE_OPTION_FINISH) == MCUXCLAEADMODES_ENGINE_OPTION_FINISH), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Aead_Finalize_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + ) + ); +} + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_enc = { + .pSkeleton = mcuxClAeadModes_SkeletonAesGcm, + .pEngine = mcuxClAeadModes_EngineAesGcmEls, + .protection_token_skeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_SkeletonAesGcm), + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_EngineAesGcmEls), + .direction = MCUXCLELS_AEAD_ENCRYPT +}; + +const mcuxClAeadModes_AlgorithmDescriptor_t mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_dec = { + .pSkeleton = mcuxClAeadModes_SkeletonAesGcm, + .pEngine = mcuxClAeadModes_EngineAesGcmEls, + .protection_token_skeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_SkeletonAesGcm), + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_EngineAesGcmEls), + .direction = MCUXCLELS_AEAD_DECRYPT +}; +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() \ No newline at end of file diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Modes.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Modes.c new file mode 100644 index 000000000..27821ff54 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Modes.c @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Modes.c + * @brief Definition of the mode descriptors for all provided Cipher modes + */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_ENC = { + .crypt = mcuxClAeadModes_crypt, + .protection_token_crypt = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_crypt), + + .init = mcuxClAeadModes_init, + .protection_token_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_init), + .processAad = mcuxClAeadModes_process_adata, + .protection_token_processAad = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process_adata), + .process = mcuxClAeadModes_process, + .protection_token_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process), + .finish = mcuxClAeadModes_finish, + .protection_token_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_finish), + .verify = mcuxClAeadModes_verify, + .protection_token_verify = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_verify), + .algorithm = &mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_enc +}; + +const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_GCM_DEC = { + .crypt = mcuxClAeadModes_crypt, + .protection_token_crypt = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_crypt), + + .init = mcuxClAeadModes_init, + .protection_token_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_init), + .processAad = mcuxClAeadModes_process_adata, + .protection_token_processAad = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process_adata), + .process = mcuxClAeadModes_process, + .protection_token_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process), + .finish = mcuxClAeadModes_finish, + .protection_token_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_finish), + .verify = mcuxClAeadModes_verify, + .protection_token_verify = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_verify), + .algorithm = &mcuxClAeadModes_AlgorithmDescriptor_Aes_Gcm_dec +}; + + +const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_ENC = { + .crypt = mcuxClAeadModes_crypt, + .protection_token_crypt = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_crypt), + + .init = mcuxClAeadModes_init, + .protection_token_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_init), + .processAad = mcuxClAeadModes_process_adata, + .protection_token_processAad = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process_adata), + .process = mcuxClAeadModes_process, + .protection_token_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process), + .finish = mcuxClAeadModes_finish, + .protection_token_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_finish), + .verify = mcuxClAeadModes_verify, + .protection_token_verify = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_verify), + .algorithm = &mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_enc +}; + +const mcuxClAead_ModeDescriptor_t mcuxClAead_ModeDescriptor_AES_CCM_DEC = { + .crypt = mcuxClAeadModes_crypt, + .protection_token_crypt = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_crypt), + + .init = mcuxClAeadModes_init, + .protection_token_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_init), + .processAad = mcuxClAeadModes_process_adata, + .protection_token_processAad = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process_adata), + .process = mcuxClAeadModes_process, + .protection_token_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_process), + .finish = mcuxClAeadModes_finish, + .protection_token_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_finish), + .verify = mcuxClAeadModes_verify, + .protection_token_verify = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClAeadModes_verify), + .algorithm = &mcuxClAeadModes_AlgorithmDescriptor_Aes_Ccm_dec +}; +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Multipart.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Multipart.c new file mode 100644 index 000000000..bde97ecf2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Multipart.c @@ -0,0 +1,308 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Multipart.c + * @brief implementation of the multipart functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_init( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + uint32_t inLength, + uint32_t adataLength, + uint32_t tagLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_init); + /* [Design] + - initialize the context: + - copy mode to mode in context + - copy key to key in context + - copy inLength to dataLength in context + - copy adataLength to aadLength in context + - copy tagLength to tagLength in context + - initialize processedDataLength in context to zero + - call the Skeleton with + - context + - options = 1: init + - all other arguments + - unused arguments = NULL/0 + */ + /* MISRA Ex. 9 to Rule 11.3 */ + mcuxClAeadModes_Context_t * pCtx = (mcuxClAeadModes_Context_t * ) pContext; + pCtx->common.mode = mode; + pCtx->key = key; + pCtx->dataLength = inLength; + pCtx->aadLength = adataLength; + pCtx->tagLength = tagLength; + pCtx->processedDataLength = 0u; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, pCtx->common.mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pCtx, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ pNonce, + /* uint32_t nonceLength, */ nonceLength, + /* mcuxCl_InputBuffer_t pIn, */ NULL, + /* uint32_t inLength, */ inLength, + /* mcuxCl_InputBuffer_t pAdata, */ NULL, + /* uint32_t adataLength, */ adataLength, + /* mcuxCl_Buffer_t pOut, */ NULL, + /* uint32_t * const pOutLength, */ NULL, + /* mcuxCl_Buffer_t pTag, */ NULL, + /* uint32_t tagLength, */ tagLength, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_INIT + )); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_init, MCUXCLAEAD_STATUS_ERROR, + pCtx->common.mode->algorithm->protection_token_skeleton); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_init, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pCtx->common.mode->algorithm->protection_token_skeleton); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_process( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_process); + /* [Design] + - Precondition: processedDataLength(context) contains the total data processed (incl. partialData, exl. padding) + - return ERROR in case: processedDataLength(context) < aadLength(context) [not finished processing adata] + - return ERROR in case: processedDataLength(context) + inLength(input) > aadLength(context) + dataLength(context) + - call the Skeleton with + - context + - options = 4: update data + - all other arguments + - unused arguments = NULL/0 + */ + /* MISRA Ex. 9 to Rule 11.3 */ + mcuxClAeadModes_Context_t * pCtx = (mcuxClAeadModes_Context_t * ) pContext; + if((pCtx->processedDataLength < pCtx->aadLength) || + ((pCtx->processedDataLength + inLength) > (pCtx->aadLength + pCtx->dataLength))) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAead_process, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, pCtx->common.mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pCtx, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ NULL, + /* uint32_t nonceLength, */ 0u, + /* mcuxCl_InputBuffer_t pIn, */ pIn, + /* uint32_t inLength, */ inLength, + /* mcuxCl_InputBuffer_t pAdata, */ NULL, + /* uint32_t adataLength, */ 0u, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ NULL, + /* uint32_t tagLength, */ 0u, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_PROCESS + )); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_process, MCUXCLAEAD_STATUS_ERROR, + pCtx->common.mode->algorithm->protection_token_skeleton); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_process, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pCtx->common.mode->algorithm->protection_token_skeleton); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_process_adata) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_process_adata( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_process_adata); + /* [Design] + - Precondition: processedDataLength(context) contains the total data procesed (incl. partialData, exl. padding) + - return ERROR in case: processedDataLength(context) + inLength(input) > aadLength(context) + - call the Skeleton with + - context + - options = 2: update adata + - all other arguments + - unused arguments = NULL/0 + */ + /* MISRA Ex. 9 to Rule 11.3 */ + mcuxClAeadModes_Context_t * pCtx = (mcuxClAeadModes_Context_t * ) pContext; + if((pCtx->processedDataLength + adataLength) > pCtx->aadLength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_process_adata, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, pCtx->common.mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pCtx, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ NULL, + /* uint32_t nonceLength, */ 0u, + /* mcuxCl_InputBuffer_t pIn, */ NULL, + /* uint32_t inLength, */ 0u, + /* mcuxCl_InputBuffer_t pAdata, */ pAdata, + /* uint32_t adataLength, */ adataLength, + /* mcuxCl_Buffer_t pOut, */ NULL, + /* uint32_t * const pOutLength, */ NULL, + /* mcuxCl_Buffer_t pTag, */ NULL, + /* uint32_t tagLength, */ 0u, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_PROCESS_AAD + )); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_process_adata, MCUXCLAEAD_STATUS_ERROR, + pCtx->common.mode->algorithm->protection_token_skeleton); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_process_adata, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pCtx->common.mode->algorithm->protection_token_skeleton); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_finish( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_finish); + /* [Design] + - Precondition: processedDataLength(context) contains the total data procesed (incl. partialData, exl. padding) + - return ERROR in case: processedDataLength(context) != aadLength(context) + dataLength(context) + - call the Skeleton with + - context + - options = 8: finish + - all other arguments + - unused arguments = NULL/0 + */ + /* MISRA Ex. 9 to Rule 11.3 */ + mcuxClAeadModes_Context_t * pCtx = (mcuxClAeadModes_Context_t * ) pContext; + if(pCtx->processedDataLength != (pCtx->dataLength + pCtx->aadLength)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_finish, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, pCtx->common.mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pCtx, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ NULL, + /* uint32_t nonceLength, */ 0u, + /* mcuxCl_InputBuffer_t pIn, */ NULL, + /* uint32_t inLength, */ 0u, + /* mcuxCl_InputBuffer_t pAdata, */ NULL, + /* uint32_t adataLength, */ 0u, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ pTag, + /* uint32_t tagLength, */ pCtx->tagLength, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_FINISH + )); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_finish, MCUXCLAEAD_STATUS_ERROR, + pCtx->common.mode->algorithm->protection_token_skeleton); + } + //if in Context->mode->pSkeletonfunction for MCUXCLAEADMODES_OPTION_VERIFY or MCUXCLAEADMODES_OPTION_FINISH options, + //the context has been clear, ctx.mode->protection_token_skeleton can't be used here + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_finish, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pCtx->common.mode->algorithm->protection_token_skeleton); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_verify( + mcuxClSession_Handle_t session, + mcuxClAead_Context_t * const pContext, + mcuxCl_InputBuffer_t pTag, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_verify); + /* [Design] + - Precondition: processedDataLength(context) contains the total data procesed (incl. partialData, exl. padding) + - return ERROR in case: processedDataLength(context) != aadLength(context) + dataLength(context) + - call the Skeleton with + - context + - options = 16: verify + - all other arguments + - unused arguments = NULL/0 + */ + /* MISRA Ex. 9 to Rule 11.3 */ + mcuxClAeadModes_Context_t * pCtx = (mcuxClAeadModes_Context_t * ) pContext; + if(pCtx->processedDataLength != pCtx->dataLength + pCtx->aadLength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_verify, MCUXCLAEAD_STATUS_ERROR); + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, pCtx->common.mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pCtx, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ NULL, + /* uint32_t nonceLength, */ 0u, + /* mcuxCl_InputBuffer_t pIn, */ NULL, + /* uint32_t inLength, */ 0u, + /* mcuxCl_InputBuffer_t pAdata, */ NULL, + /* uint32_t adataLength, */ 0u, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ (mcuxCl_Buffer_t) pTag, + /* uint32_t tagLength, */ pCtx->tagLength, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_VERIFY + )); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_verify, MCUXCLAEAD_STATUS_ERROR, + pCtx->common.mode->algorithm->protection_token_skeleton); + } + //if in Context->mode->pSkeletonfunction for MCUXCLAEADMODES_OPTION_VERIFY or MCUXCLAEADMODES_OPTION_FINISH options, + //the context has been clear, ctx.mode->protection_token_skeleton can't be used here + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_verify, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + pCtx->common.mode->algorithm->protection_token_skeleton); +} diff --git a/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Oneshot.c b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Oneshot.c new file mode 100644 index 000000000..177077f0c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAeadModes/src/mcuxClAeadModes_Els_Oneshot.c @@ -0,0 +1,103 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAeadModes_Els_Oneshot.c + * @brief implementation of the oneshot functions of the mcuxClAeadModes component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClAeadModes_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClAead_Status_t) mcuxClAeadModes_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClAead_Mode_t mode, + mcuxCl_InputBuffer_t pNonce, + uint32_t nonceLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_InputBuffer_t pAdata, + uint32_t adataLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + mcuxCl_Buffer_t pTag, + uint32_t tagLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClAeadModes_crypt); + /* [Design] + - allocate a context in the session + - initialize the context: + - copy mode to mode in context + - copy key to key in context + - copy inLength to dataLength in context + - copy adataLength to aadLength in context + - copy tagLength to tagLength in context + - initialize processedDataLength in context to zero + - call the Skeleton with + - context + - options = 15: oneshot + - all other arguments + - unused arguments = NULL/0 + - clean up session + */ + + /* Allocate context */ + const uint32_t cpuCtxSizeInWords = MCUXCLAEADMODES_INTERNAL_COMPUTE_CPUWORDS(sizeof(mcuxClAeadModes_Context_t)); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClAeadModes_Context_t *pCtx = (mcuxClAeadModes_Context_t *) mcuxClSession_allocateWords_cpuWa(session, cpuCtxSizeInWords); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + pCtx->common.mode = mode; + pCtx->key = key; + pCtx->dataLength = inLength; + pCtx->aadLength = adataLength; + pCtx->tagLength = tagLength; + pCtx->processedDataLength = 0u; + pCtx->partialDataLength = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Skeleton, mode->algorithm->pSkeleton( + /* mcuxClSession_Handle_t session, */ session, + /* mcuxClAead_Context_t * const pContext, */ pCtx, + /* mcuxCl_InputBuffer_t pNonce, */ pNonce, + /* uint32_t nonceLength, */ nonceLength, + /* mcuxCl_InputBuffer_t pIn, */ pIn, + /* uint32_t inLength, */ inLength, + /* mcuxCl_InputBuffer_t pAdata, */ pAdata, + /* uint32_t adataLength, */ adataLength, + /* mcuxCl_Buffer_t pOut, */ pOut, + /* uint32_t * const pOutLength, */ pOutLength, + /* mcuxCl_Buffer_t pTag, */ pTag, + /* uint32_t tagLength, */ tagLength, + /* uint32_t options */ MCUXCLAEADMODES_OPTION_ONESHOT + )); + + if(MCUXCLAEAD_STATUS_OK != ret_Skeleton) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClAeadModes_crypt, MCUXCLAEAD_STATUS_ERROR, + mode->algorithm->protection_token_skeleton); + } + + mcuxClSession_freeWords_cpuWa(session, cpuCtxSizeInWords); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClAeadModes_crypt, MCUXCLAEAD_STATUS_OK, MCUXCLAEAD_STATUS_FAULT_ATTACK, + mode->algorithm->protection_token_skeleton); +} + diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Ctx.h b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Ctx.h new file mode 100644 index 000000000..f679dc7b3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Ctx.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLAES_CTX_H_ +#define MCUXCLAES_CTX_H_ + +#include // Exported features flags header +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_CTX_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Constants.h new file mode 100644 index 000000000..5065a1216 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Constants.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLAES_INTERNAL_CONSTANTS_H_ +#define MCUXCLAES_INTERNAL_CONSTANTS_H_ + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUXCLAES_MASKED_KEY_SIZE (32u) +#define MCUXCLAES_MASKED_KEY_SIZE_IN_WORDS (MCUXCLAES_MASKED_KEY_SIZE / sizeof(uint32_t)) + +#define MCUXCLAES_GCM_H_KEY_SIZE (16u) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Functions.h new file mode 100644 index 000000000..c5917ca4c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Internal_Functions.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClAes_Internal_Functions.h + * @brief Internal helper function definitions for the mcuxClAes component + */ + +#ifndef MCUXCLAES_INTERNAL_FUNCTIONS_H_ +#define MCUXCLAES_INTERNAL_FUNCTIONS_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Wa.h b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Wa.h new file mode 100644 index 000000000..8ec34d4ab --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/internal/mcuxClAes_Wa.h @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLAES_WA_H_ +#define MCUXCLAES_WA_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_WA_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes.h b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes.h new file mode 100644 index 000000000..7d0722db2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClAes.h + * @brief Top-level interface header for the mcuxClAes component + */ + +#ifndef MCUXCLAES_H_ +#define MCUXCLAES_H_ + +#include // Exported features flags header + +#include +#include +#endif /* MCUXCLAES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_Constants.h b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_Constants.h new file mode 100644 index 000000000..ae3794d71 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_Constants.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLAES_CONSTANTS_H_ +#define MCUXCLAES_CONSTANTS_H_ + +#include // Exported features flags header + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClAes_Constants mcuxClAes_Constants + * @brief Defines of constants associated with @ref mcuxClAes + * @ingroup mcuxClAes + * @{ + */ + +/* Block size */ +#define MCUXCLAES_BLOCK_SIZE (16u) ///< AES block size in bytes +#define MCUXCLAES_BLOCK_SIZE_IN_WORDS (MCUXCLAES_BLOCK_SIZE / sizeof(uint32_t)) ///< AES block size in words + +/* Key sizes */ +#define MCUXCLAES_AES128_KEY_SIZE (MCUXCLKEY_SIZE_128) ///< AES-128 key size in bytes +#define MCUXCLAES_AES128_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_128_IN_WORDS) ///< AES-128 key size in words +#define MCUXCLAES_AES192_KEY_SIZE (MCUXCLKEY_SIZE_192) ///< AES-192 key size in bytes +#define MCUXCLAES_AES192_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_192_IN_WORDS) ///< AES-192 key size in words +#define MCUXCLAES_AES256_KEY_SIZE (MCUXCLKEY_SIZE_256) ///< AES-256 key size in bytes +#define MCUXCLAES_AES256_KEY_SIZE_IN_WORDS (MCUXCLKEY_SIZE_256_IN_WORDS) ///< AES-256 key size in words + +/** + * @} + */ /* mcuxClAes_Constants */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_KeyTypes.h b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_KeyTypes.h new file mode 100644 index 000000000..11a844076 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/inc/mcuxClAes_KeyTypes.h @@ -0,0 +1,84 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClAes_KeyTypes.h + * @brief Definition of supported key types in mcuxClAes component, see also @ref mcuxClKey component + */ + +#ifndef MCUXCLAES_KEYTYPES_H_ +#define MCUXCLAES_KEYTYPES_H_ + +#include // Exported features flags header + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ") + +/** + * @defgroup mcuxClAes_KeyTypes mcuxClAes_KeyTypes + * @brief Defines of supported key types of @ref mcuxClAes, see @ref mcuxClKey + * @ingroup mcuxClAes + * @{ + */ + +/** + * @brief Key type structure for AES-128 based keys. + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128; + +/** + * @brief Key type pointer for AES-128 based keys. + */ +static const mcuxClKey_Type_t mcuxClKey_Type_Aes128 = &mcuxClKey_TypeDescriptor_Aes128; + +/** + * @brief Key type structure for AES-192 based keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192; + +/** + * @brief Key type pointer for AES-192 based keys. + */ +static const mcuxClKey_Type_t mcuxClKey_Type_Aes192 = &mcuxClKey_TypeDescriptor_Aes192; + +/** + * @brief Key type structure for AES-256 based keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256; + +/** + * @brief Key type pointer for AES-256 based keys. + */ +static const mcuxClKey_Type_t mcuxClKey_Type_Aes256 = &mcuxClKey_TypeDescriptor_Aes256; + +/** + * @} + */ /* mcuxClAes_KeyTypes */ + +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLAES_KEYTYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClAes/src/mcuxClAes_KeyTypes.c b/components/els_pkc/src/comps/mcuxClAes/src/mcuxClAes_KeyTypes.c new file mode 100644 index 000000000..ccc82c8aa --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClAes/src/mcuxClAes_KeyTypes.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClAes_KeyTypes.c + * @brief Instantiation of the key types supported by the mcuxClAes component. */ + +#include +#include +#include +#include + +// fully supported AES key types +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes128 = {.algoId = MCUXCLKEY_ALGO_ID_AES + MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY, .size = MCUXCLAES_AES128_KEY_SIZE, .info = NULL}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes256 = {.algoId = MCUXCLKEY_ALGO_ID_AES + MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY, .size = MCUXCLAES_AES256_KEY_SIZE, .info = NULL}; + +// AES key types supported by key from memory only +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Aes192 = {.algoId = MCUXCLKEY_ALGO_ID_AES + MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY, .size = MCUXCLAES_AES192_KEY_SIZE, .info = NULL}; diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal.h b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal.h new file mode 100644 index 000000000..b68bc89a3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal.h @@ -0,0 +1,25 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHER_INTERNAL_H_ +#define MCUXCLCIPHER_INTERNAL_H_ + +#include // Exported features flags header + +#include +#include +#include +#include + + +#endif /* MCUXCLCIPHER_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Constants.h new file mode 100644 index 000000000..a6391b087 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Constants.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHER_INTERNAL_CONSTANTS_H_ +#define MCUXCLCIPHER_INTERNAL_CONSTANTS_H_ + +/* Options for the crypt mode function */ +#define MCUXCLCIPHER_OPTION_ONESHOT 0x00000007u +#define MCUXCLCIPHER_OPTION_INIT 0x00000001u +#define MCUXCLCIPHER_OPTION_PROCESS 0x00000002u +#define MCUXCLCIPHER_OPTION_FINISH 0x00000004u + +#endif /* MCUXCLCIPHER_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Functions.h new file mode 100644 index 000000000..8bdbd6810 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Functions.h @@ -0,0 +1,50 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHER_INTERNAL_FUNCTONS_H_ +#define MCUXCLCIPHER_INTERNAL_FUNCTONS_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_computeContextCrc) +static inline MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClCipher_computeContextCrc(mcuxClCipher_Context_t * const pCtx, uint32_t contextSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_computeContextCrc); + + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClCipher_computeContextCrc + ); + +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_verifyContextCrc) +static inline MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_verifyContextCrc(mcuxClCipher_Context_t * const pCtx, uint32_t contextSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_verifyContextCrc); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipher_verifyContextCrc, MCUXCLCIPHER_STATUS_OK + ); +} + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHER_INTERNAL_FUNCTONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Types.h b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Types.h new file mode 100644 index 000000000..fd357cef7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/internal/mcuxClCipher_Internal_Types.h @@ -0,0 +1,108 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipher_Internal_Types.h + * @brief Internal type definitions for the mcuxClCipher component */ + +#ifndef MCUXCLCIPHER_INTERNAL_TYPES_H_ +#define MCUXCLCIPHER_INTERNAL_TYPES_H_ + +#include // Exported features flags header + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Mode/Skeleton function types + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClCipher_CryptFunc_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) (*mcuxClCipher_CryptFunc_t) ( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxClKey_Handle_t pKey, + mcuxClCipher_Mode_t pMode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t steps //!< steps is a bitmask with one bit reserved for each of the steps below +)); + + + +/** + * @brief Macros for @ref mcuxClCipher_ModeFunctions_t + */ +#define MCUXCLCIPHER_CRYPT_MODEFUNCTIONS \ + mcuxClCipher_CryptFunc_t crypt; \ + uint32_t protection_token_crypt; + +#define MCUXCLCIPHER_ENCRYPT_DECRYPT_ONESHOT_MODEFUNCTIONS +#define MCUXCLCIPHER_ENCRYPT_DECRYPT_MULTIPART_MODEFUNCTIONS + +/** + * @brief Cipher mode function structure + * + * This structure captures all the information related to the functions + * of the Cipher interfaces. + */ +typedef struct mcuxClCipher_ModeFunctions +{ + MCUXCLCIPHER_ENCRYPT_DECRYPT_ONESHOT_MODEFUNCTIONS + MCUXCLCIPHER_ENCRYPT_DECRYPT_MULTIPART_MODEFUNCTIONS + MCUXCLCIPHER_CRYPT_MODEFUNCTIONS +} mcuxClCipher_ModeFunctions_t; + +/** + * @brief Cipher mode/algorithm descriptor structure + * + * This structure captures all the information that the Cipher interfaces need + * to know about a particular Cipher mode/algorithm. + */ +struct mcuxClCipher_ModeDescriptor +{ + const void *pModeFunctions; + void * pAlgorithm; +}; + +/** + * @brief Cipher context structure + * + * This structure is used in the multi-part interfaces to store the + * information about the current operation and the relevant internal state. + * This is the common part of the context needed by cipher modes. + */ +struct mcuxClCipher_Context +{ + const mcuxClCipher_ModeDescriptor_t * pMode; + + uint32_t blockBufferUsed; /* How many bytes in blockBuffer is used */ + uint32_t totalInputLength;/* Total number of bytes that were encrypted */ +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHER_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher.h b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher.h new file mode 100644 index 000000000..d6636ae58 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHER_H_ +#define MCUXCLCIPHER_H_ + +/** @file mcuxClCipher.h + * @brief Top-level include file for the @ref mcuxClCipher component + * + * This includes headers for all of the functionality provided by the @ref mcuxClCipher component. + * + * @defgroup mcuxClCipher mcuxClCipher + * @brief Cipher component + * + * The mcuxClCipher component implements the Encryption and Decryption functionality supported by CLNS. + * It supports Symmetric encryption algorithms. + * + * An example of how to use the @ref mcuxClCipher component can be found in /mcuxClCipher/ex. + * + * The component uses the ELS hardware. The ELS hardware has to be initialized, prior to + * calling any function of the @ref mcuxClCipher component. + * + * The @ref mcuxClCipher component supports interfaces to either encrypt/decrypt a message + * in one shot (mcuxClCipher_crypt) or to encrypt/decrypt it in parts (mcuxClCipher_init, + * mcuxClCipher_process, and mcuxClCipher_finish). In case of encrypting/decrypting a message + * in parts, first an initialization has to be performed (mcuxClCipher_init), followed by + * zero, one or multiple updates (mcuxClCipher_process), followed by a finalization + * (mcuxClCipher_finish). The finalization generates the encrypted/decrypted output data and + * destroys the context. After the finalization step, no further updates are possible. + * + * The targeted encryption algorithm is selected by passing one of the offered algorithm mode + * descriptors, which are available in the @ref mcuxClCipherModes components. + * + * */ + +#include // Exported features flags header +#include +#include +#include +#include + +#endif /* MCUXCLCIPHER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Constants.h b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Constants.h new file mode 100644 index 000000000..48ab0af1d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Constants.h @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipher_Constants.h + * @brief Constants for use with the mcuxClCipher component */ + +#ifndef MCUXCLCIPHER_CONSTANTS_H_ +#define MCUXCLCIPHER_CONSTANTS_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClCipher_Constants mcuxClCipher_Constants + * @brief Constants of @ref mcuxClCipher component + * @ingroup mcuxClCipher + * @{ + */ + +/* Error codes */ +/* TODO CLNS-8684: Unionize and describe return codes */ +#define MCUXCLCIPHER_STATUS_ERROR ((mcuxClCipher_Status_t) 0x02225330u) +#define MCUXCLCIPHER_STATUS_FAILURE ((mcuxClCipher_Status_t) 0x02225334u) +#define MCUXCLCIPHER_STATUS_INVALID_INPUT ((mcuxClCipher_Status_t) 0x022253F8u) +#define MCUXCLCIPHER_STATUS_ERROR_MEMORY_ALLOCATION ((mcuxClCipher_Status_t) 0x0222533Cu) // memory allocation error +#define MCUXCLCIPHER_STATUS_FAULT_ATTACK ((mcuxClCipher_Status_t) 0x0222F0F0u) +#define MCUXCLCIPHER_STATUS_OK ((mcuxClCipher_Status_t) 0x02222E03u) +#define MCUXCLCIPHER_STATUS_JOB_STARTED ((mcuxClCipher_Status_t) 0x02222E47u) +#define MCUXCLCIPHER_STATUS_JOB_COMPLETED ((mcuxClCipher_Status_t) 0x02222E8Bu) +#define MCUXCLCIPHER_STATUS_JOB_UNAVAILABLE ((mcuxClCipher_Status_t) 0x022289BCu) + +/** @}*/ +#endif /* MCUXCLCIPHER_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Functions.h b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Functions.h new file mode 100644 index 000000000..682a2b195 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Functions.h @@ -0,0 +1,195 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipher_Functions.h + * @brief Top-level API of the mcuxClCipher component */ + +#ifndef MCUXCLCIPHER_FUNCTIONS_H_ +#define MCUXCLCIPHER_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @defgroup mcuxClCipher Cipher API + * @brief Cipher operations. + * @ingroup mcuxClAPI + */ + + +/** + * @defgroup clCipherOneShot One-shot Cipher interfaces + * @brief Interfaces to perform Cipher operations in one shot. + * @ingroup mcuxClCipher + */ + +/** + * @brief One-shot encryption/decryption function + * @api + * + * This function performs an encryption/decryption operation in one shot. The + * algorithm to be used will be determined based on the mode that is provided. + * + * For example, to perform an AES encryption/decryption operation with a 128-bit key in + * CBC mode on padded data, the following needs to be provided: + * - AES128 key + * - CBC mode for encryption, without padding + * - IV, same size as the AES block size + * - Plain input data, size must be a multiple of the AES block size + * - Output data buffer, with the same size as the input data + * - Output size buffer, to store the amount of written bytes + * + * @param session Handle for the current CL session. + * @param key Key to be used to encrypt the data. + * @param mode Cipher mode that should be used during the encryption/decryption + * operation. + * @param[in] pIv Pointer to the buffer that contains the IV, if needed + * for the chosen @p mode, otherwise ignored. + * @param ivLength Number of bytes of data in the @p pIv buffer. + * @param[in] pIn Pointer to the input buffer that contains the plain + * data that needs to be encrypted. + * @param inLength Number of bytes of plain data in the @p pIn buffer. + * @param[out] pOut Pointer to the output buffer where the encrypted data + * needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of encrypted + * data that have been written to the @p pOut buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClCipher_Mode_t mode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); + + + +/** + * @defgroup clCipherMultiPart Multi-part Cipher interfaces + * @brief Interfaces to perform Cipher operations in multiple parts. + * @ingroup mcuxClCipher + */ + +/** + * @brief Multi-part encryption/decryption initialization function + * @api + * + * This function performs the initialization for a multi part encryption/decryption + * operation. The algorithm to be used will be determined based on the mode + * that is provided. + * + * @param session Handle for the current CL session. + * @param pContext Cipher context which is used to maintain the state and + * store other relevant information about the operation. + * @param key Key to be used to encrypt the data. + * @param mode Cipher mode that should be used during the encryption/decryption + * operation. + * @param[in] pIv Pointer to the buffer that contains the IV, if needed + * for the chosen @p mode, otherwise ignored. + * @param ivLength Number of bytes of data in the @p pIv buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_init( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClCipher_Mode_t mode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength +); /* init */ + +/** + * @brief Multi-part encryption/decryption processing function + * @api + * + * This function performs the processing of (a part of) a data stream for an + * encryption/decryption operation. The algorithm and key to be used will be + * determined based on the context that is provided. + * Data is processed in full blocks only. Remaining data is stored in the context + * to be handled in later process or finish calls. + * + * @param session Handle for the current CL session. + * @param pContext Cipher context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pIn Pointer to the input buffer that contains the data that + * needs to be processed. + * @param inLength Number of bytes of data in the @p pIn buffer. + * @param[out] pOut Pointer to the output buffer where the processed data + * needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of processed + * data that have been written to the @p pOut buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_process( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); /* update */ + +/** + * @brief Multi-part encryption/decryption finalization function + * @api + * + * This function performs the finalization of an encryption or decryption + * operation. The algorithm and key to be used will be determined based on the + * context that is provided. + * No new data is accepted but remaining data in the context is processed. + * + * @param session Handle for the current CL session. + * @param pContext Cipher context which is used to maintain the state and + * store other relevant information about the operation. + * @param[out] pOut Pointer to the output buffer where the processed data + * needs to be written. + * @param[out] pOutLength Will be incremented by the number of bytes of processed + * data that have been written to the @p pOut buffer. + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipher_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_finish( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +); /* finalize */ + + + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHER_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Types.h b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Types.h new file mode 100644 index 000000000..c2715dd1d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/inc/mcuxClCipher_Types.h @@ -0,0 +1,116 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipher_Types.h + * @brief Type definitions for the mcuxClCipher component + */ + +#ifndef MCUXCLCIPHER_TYPES_H_ +#define MCUXCLCIPHER_TYPES_H_ + +#include +#include +#include + +#include // Exported features flags header +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup clCipherTypes Cipher type definitions + * @brief Types used by the Cipher operations. + * @ingroup mcuxClCipher + * @{ + */ + +/** + * @brief Cipher mode/algorithm descriptor structure + * + * This structure captures all the information that the Cipher interfaces need + * to know about a particular Cipher mode/algorithm. + */ +struct mcuxClCipher_ModeDescriptor; + +/** + * @brief Cipher mode/algorithm descriptor type + * + * This type captures all the information that the Cipher interfaces need to + * know about a particular Cipher mode/algorithm. + */ +typedef struct mcuxClCipher_ModeDescriptor mcuxClCipher_ModeDescriptor_t; + +/** + * @brief Cipher mode/algorithm type + * + * This type is used to refer to a Cipher mode/algorithm. + */ +typedef const mcuxClCipher_ModeDescriptor_t * const mcuxClCipher_Mode_t; + +/** + * @brief Cipher selftest mode/algorithm descriptor structure + * + * This structure captures all the information that the Cipher selftest interfaces need + * to know about a particular Cipher selftest mode/algorithm. + */ +struct mcuxClCipher_TestDescriptor; + +/** + * @brief Cipher selftest mode/algorithm descriptor type + * + * This type captures all the information that the Cipher selftest interfaces need to + * know about a particular Cipher selftest mode/algorithm. + */ +typedef struct mcuxClCipher_TestDescriptor mcuxClCipher_TestDescriptor_t; + +/** + * @brief Cipher selftest mode/algorithm type + * + * This type is used to refer to a Cipher selftest mode/algorithm. + */ +typedef const mcuxClCipher_TestDescriptor_t * const mcuxClCipher_Test_t; + +/** + * @brief Cipher context structure + * + * This structure is used in the multi-part interfaces to store the + * information about the current operation and the relevant internal state. + */ +struct mcuxClCipher_Context; + +/** + * @brief Cipher context type + * + * This type is used in the multi-part interfaces to store the information + * about the current operation and the relevant internal state. + */ +typedef struct mcuxClCipher_Context mcuxClCipher_Context_t; + +/** + * @brief Cipher status code + * + * This type provides information about the status of the Cipher operation that + * has been performed. + */ +typedef uint32_t mcuxClCipher_Status_t; + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHER_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipher/src/mcuxClCipher.c b/components/els_pkc/src/comps/mcuxClCipher/src/mcuxClCipher.c new file mode 100644 index 000000000..3b6a9d2a2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipher/src/mcuxClCipher.c @@ -0,0 +1,184 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_crypt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_crypt( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClCipher_Mode_t mode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_crypt); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClCipher_ModeFunctions_t *pModeFunctions = (const mcuxClCipher_ModeFunctions_t *)mode->pModeFunctions; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + MCUX_CSSL_FP_FUNCTION_CALL(status, pModeFunctions->crypt( + session, + NULL, /* pContext */ + key, + mode, + pIv, + ivLength, + pIn, + inLength, + pOut, + pOutLength, + MCUXCLCIPHER_OPTION_ONESHOT)); + + if(MCUXCLCIPHER_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipher_crypt, status, pModeFunctions->protection_token_crypt); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClCipher_crypt, MCUXCLCIPHER_STATUS_OK, MCUXCLCIPHER_STATUS_FAULT_ATTACK, + pModeFunctions->protection_token_crypt); + +} + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_init( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClCipher_Mode_t mode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_init); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClCipher_ModeFunctions_t *pModeFunctions = (const mcuxClCipher_ModeFunctions_t *)mode->pModeFunctions; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + MCUX_CSSL_FP_FUNCTION_CALL(status, pModeFunctions->crypt( + session, + pContext, + key, + mode, + pIv, + ivLength, + NULL, /* pIn */ + 0u, /* inLength */ + NULL, /* pOut */ + 0u, /* pOutLength */ + MCUXCLCIPHER_OPTION_INIT)); + + if(MCUXCLCIPHER_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipher_init, status, pModeFunctions->protection_token_crypt); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClCipher_init, MCUXCLCIPHER_STATUS_OK, MCUXCLCIPHER_STATUS_FAULT_ATTACK, + pModeFunctions->protection_token_crypt); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_process( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_process); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClCipher_ModeFunctions_t *pModeFunctions = (const mcuxClCipher_ModeFunctions_t *)pContext->pMode->pModeFunctions; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + MCUX_CSSL_FP_FUNCTION_CALL(status, pModeFunctions->crypt( + session, + pContext, + NULL, /* pKey, is already stored in context */ + NULL, /* pMode, is already stored in context */ + NULL, /* pIv */ + 0u, /* ivLength */ + pIn, + inLength, + pOut, + pOutLength, + MCUXCLCIPHER_OPTION_PROCESS)); + + if(MCUXCLCIPHER_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipher_process, status, pModeFunctions->protection_token_crypt); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClCipher_process, MCUXCLCIPHER_STATUS_OK, MCUXCLCIPHER_STATUS_FAULT_ATTACK, + pModeFunctions->protection_token_crypt); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipher_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipher_finish( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipher_finish); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClCipher_ModeFunctions_t *pModeFunctions = (const mcuxClCipher_ModeFunctions_t *)pContext->pMode->pModeFunctions; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + MCUX_CSSL_FP_FUNCTION_CALL(status, pModeFunctions->crypt( + session, + pContext, + NULL, /* pKey, is already stored in context */ + NULL, /* pMode, is already stored in context */ + NULL, /* pIv */ + 0u, /* ivLength */ + NULL, /* pIn */ + 0u, /* inLength */ + pOut, + pOutLength, + MCUXCLCIPHER_OPTION_FINISH)); + + if(MCUXCLCIPHER_STATUS_OK != status) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipher_finish, status, pModeFunctions->protection_token_crypt); + } + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClCipher_finish, MCUXCLCIPHER_STATUS_OK, MCUXCLCIPHER_STATUS_FAULT_ATTACK, + pModeFunctions->protection_token_crypt); +} + + diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Algorithms_Els.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Algorithms_Els.h new file mode 100644 index 000000000..243a11c38 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Algorithms_Els.h @@ -0,0 +1,105 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Algorithms_Els.h + * @brief Supported algorithms for the mcuxClCipherModes component + */ + +#ifndef MCUXCLCIPHERMODES_ALGORITHMS_ELS_H_ +#define MCUXCLCIPHERMODES_ALGORITHMS_ELS_H_ + +#include // Exported features flags header + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup clCipherModesAlgorithms Cipher algorithm definitions + * @brief Modes used by the Cipher operations. + * @ingroup mcuxClCipherModes + * @{ + */ + +/** + * @brief AES ECB Encryption algorithm descriptor without padding, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_NoPadding_Els; + +/** + * @brief AES ECB Encryption algorithm descriptor with ISO/IEC 9797-1 padding method 1, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1_Els; + +/** + * @brief AES ECB Encryption algorithm descriptor with ISO/IEC 9797-1 padding method 2, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2_Els; + + +/** + * @brief AES ECB Encryption algorithm descriptor with PKCS7 padding, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingPKCS7_Els; + + +/** + * @brief AES ECB Decryption algorithm descriptor, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Dec_Els; + + +/** + * @brief AES CBC Encryption algorithm descriptor without padding, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_NoPadding_Els; + +/** + * @brief AES CBC Encryption algorithm descriptor with ISO/IEC 9797-1 padding method 1, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1_Els; + +/** + * @brief AES CBC Encryption algorithm descriptor with ISO/IEC 9797-1 padding method 2, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2_Els; + + +/** + * @brief AES CBC Encryption algorithm descriptor with PKCS7 padding, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingPKCS7_Els; + + +/** + * @brief AES CBC Decryption algorithm descriptor, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Dec_Els; + + +/** + * @brief CTR Encryption/Decryption algorithm descriptor, using ELS + */ +extern const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CTR_Els; + + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHERMODES_ALGORITHMS_ELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Helper.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Helper.h new file mode 100644 index 000000000..0b0a2a62a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Helper.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_HELPER_H_ +#define MCUXCLCIPHERMODES_HELPER_H_ + +#include + +#include + +/* + * Helper macros + */ + +/* Macro used to align the size to the CPU wordsize */ +#define MCUXCLCIPHERMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) \ + (((uint32_t) (((uint32_t) (size)) + ((sizeof(uint32_t)) - 1U))) & ((uint32_t) (~((sizeof(uint32_t)) - 1U)))) + +/* Macro used to compute number of CPU words */ +#define MCUXCLCIPHERMODES_INTERNAL_COMPUTE_CPUWORDS(size) \ + (MCUXCLCIPHERMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) / (sizeof(uint32_t))) + + +/* + * Helper functions + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipherModes_MemClear) +void mcuxClCipherModes_MemClear(uint8_t *pDst, uint32_t length); + +#endif /* MCUXCLCIPHERMODES_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal.h new file mode 100644 index 000000000..4ca2f51ee --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_INTERNAL_H_ +#define MCUXCLCIPHERMODES_INTERNAL_H_ + +#include // Exported features flags header + +#include +#include +#include +#include +#include +#include + +#endif /* MCUXCLCIPHERMODES_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Constants.h new file mode 100644 index 000000000..666a79953 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Constants.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_INTERNAL_CONSTANTS_H_ +#define MCUXCLCIPHERMODES_INTERNAL_CONSTANTS_H_ + +#define MCUXCLCIPHERMODES_ENCRYPT (0u) +#define MCUXCLCIPHERMODES_DECRYPT (1u) + +#define MCUXCLCIPHERMODES_PADDING_ADDED (0x001234u) +#define MCUXCLCIPHERMODES_PADDING_NOT_NEEDED (0x004321u) + +#endif /* MCUXCLCIPHERMODES_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Functions_Els.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Functions_Els.h new file mode 100644 index 000000000..79709c29e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Functions_Els.h @@ -0,0 +1,60 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_INTERNAL_FUNCTONS_ELS_H_ +#define MCUXCLCIPHERMODES_INTERNAL_FUNCTONS_ELS_H_ + +#include // Exported features flags header + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Skeleton and Engine functions + * */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipherModes_EngineEls) + MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipherModes_EngineEls( + mcuxClSession_Handle_t session, + mcuxClCipherModes_Context_Aes_Els_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClCipherModes_SkeletonAes) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipherModes_SkeletonAes( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxClKey_Handle_t pKey, + mcuxClCipher_Mode_t pMode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t steps //!< steps is a bitmask with one bit reserved for each of the steps below +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHERMODES_INTERNAL_FUNCTONS_ELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Types_Els.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Types_Els.h new file mode 100644 index 000000000..441f23686 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Internal_Types_Els.h @@ -0,0 +1,97 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Internal_Types_Els.h + * @brief Internal type definitions for the mcuxClCipherModes component + */ + +#ifndef MCUXCLCIPHERMODES_INTERNAL_TYPES_ELS_H_ +#define MCUXCLCIPHERMODES_INTERNAL_TYPES_ELS_H_ + +#include // Exported features flags header + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Cipher context structure for ELS modes + * + * This structure is used to store the information about the current operation + * and the relevant internal ELS state. + */ +typedef struct mcuxClCipherModes_Context_Aes_Els +{ + mcuxClCipher_Context_t common; + + mcuxClKey_Descriptor_t * pKey; + uint8_t blockBuffer[MCUXCLAES_BLOCK_SIZE]; /* Buffer used when not enough data for full block */ + uint32_t ivState[MCUXCLAES_BLOCK_SIZE_IN_WORDS]; /* IV and internal state */ +} mcuxClCipherModes_Context_Aes_Els_t; + +/** + * @brief Engine function type for ELS modes + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) (*mcuxClCipherModes_EngineFunc_AesEls_t) ( + mcuxClSession_Handle_t session, + mcuxClCipherModes_Context_Aes_Els_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut +); + +/** + * @brief Cipher mode algorithm descriptor structure for AES algorithms using ELS + * + * This structure captures all the information that the Cipher interfaces need + * to know about an ELS AES Cipher mode algorithm. + */ +typedef struct mcuxClCipherModes_AlgorithmDescriptor_Aes_Els +{ + mcuxClCipherModes_EngineFunc_AesEls_t cryptEngine; + mcuxClPadding_addPaddingMode_t addPadding; + uint32_t protection_token_engine; + uint32_t protection_token_addPadding; + uint32_t mode; + uint32_t direction; + uint32_t blockLength; + uint32_t ivLength; + uint32_t granularity; +} mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t; + +/** + * @brief Cipher mode algorithm type for AES algorithms using ELS + * + * This type is used to refer to an ELS AES Cipher mode algorithm. + */ +typedef const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t * const mcuxClCipherModes_Algorithm_Aes_Els_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHERMODES_INTERNAL_TYPES_ELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Wa.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Wa.h new file mode 100644 index 000000000..a04c991f5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/internal/mcuxClCipherModes_Wa.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_WA_H_ +#define MCUXCLCIPHERMODES_WA_H_ + +#include // Exported features flags header + +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +/* TODO CLNS-5399: this is AES SGI specific, rework WA */ +typedef struct mcuxClCipherModes_WorkArea +{ + uint8_t paddingBuff[MCUXCLAES_BLOCK_SIZE]; + uint32_t *pIV; +} mcuxClCipherModes_WorkArea_t; + + +#endif /* MCUXCLCIPHERMODES_WA_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes.h new file mode 100644 index 000000000..9a4643d15 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCIPHERMODES_H_ +#define MCUXCLCIPHERMODES_H_ + +/** @file mcuxClCipher.h + * @brief Top-level include file for the @ref mcuxClCipherModes component + */ + +#include // Exported features flags header + +#include +#include + +#endif /* MCUXCLCIPHERMODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_MemoryConsumption.h new file mode 100644 index 000000000..15483eff1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_MemoryConsumption.h @@ -0,0 +1,44 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipher_MemoryConsumption.h + * @brief Memory consumption of the mcuxClCipher component + * All work area sizes in bytes are a multiple of CPU wordsize. + */ + +#ifndef MCUXCLCIPHER_MEMORYCONSUMPTION_H_ +#define MCUXCLCIPHER_MEMORYCONSUMPTION_H_ + +/* Macro to calculate the WA size in the CPU wordsize */ +#define MCUXCLCIPHER_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t))) + +/* Workarea sizes */ +#define MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE (48u) +#define MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE) + +#define MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_INIT_CPU_WA_BUFFER_SIZE) +#define MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_PROCESS_CPU_WA_BUFFER_SIZE) +#define MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_FINISH_CPU_WA_BUFFER_SIZE) + +#define MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE (MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE) +#define MCUXCLCIPHER_MAX_AES_CPU_WA_BUFFER_SIZE_IN_WORDS (MCUXCLCIPHER_AES_CRYPT_CPU_WA_BUFFER_SIZE_IN_WORDS) + +/* Context sizes */ +#define MCUXCLCIPHER_AES_CONTEXT_SIZE (48u) +#define MCUXCLCIPHER_AES_CONTEXT_SIZE_IN_WORDS MCUXCLCIPHER_SIZE_IN_CPUWORDS(MCUXCLCIPHER_AES_CONTEXT_SIZE) + + +#endif /* MCUXCLCIPHER_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_Modes.h b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_Modes.h new file mode 100644 index 000000000..7ea4c5f0b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/inc/mcuxClCipherModes_Modes.h @@ -0,0 +1,175 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Modes.h + * @brief Supported modes for the mcuxClCipher component + */ + +#ifndef MCUXCLCIPHERMODES_MODES_H_ +#define MCUXCLCIPHERMODES_MODES_H_ + +#include + +#include + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup clCipherModes Cipher mode definitions + * @brief Modes used by the Cipher operations. + * @ingroup mcuxClCipher + * @{ + */ + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ") + +/* + * Crypt Modes using the ELS + */ +/** + * @brief AES ECB Encryption mode descriptor without padding + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding; + +/** + * @brief AES ECB Encryption mode without padding + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_NoPadding = + &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding; + +/** + * @brief AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 1 + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1; + +/** + * @brief AES ECB Encryption mode with ISO/IEC 9797-1 padding method 1 + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method1 = + &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1; + +/** + * @brief AES ECB Encryption mode descriptor with ISO/IEC 9797-1 padding method 2 + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2; + +/** + * @brief AES ECB Encryption mode with ISO/IEC 9797-1 padding method 2 + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingISO9797_1_Method2 = + &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2; + +/** + * @brief AES ECB Encryption mode descriptor with PKCS7 padding + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7; + +/** + * @brief AES ECB Encryption mode with PKCS7 padding + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Enc_PaddingPKCS7 = + &mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7; + +/** + * @brief AES ECB Decryption mode descriptor + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec; + +/** + * @brief AES ECB Decryption mode + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_ECB_Dec_NoPadding = + &mcuxClCipher_ModeDescriptor_AES_ECB_Dec; + +/** + * @brief AES CBC Encryption mode descriptor without padding + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding; + +/** + * @brief AES CBC Encryption mode without padding + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_NoPadding = + &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding; + +/** + * @brief AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 1 + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1; + +/** + * @brief AES CBC Encryption mode with ISO/IEC 9797-1 padding method 1 + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method1 = + &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1; + +/** + * @brief AES CBC Encryption mode descriptor with ISO/IEC 9797-1 padding method 2 + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2; + +/** + * @brief AES CBC Encryption mode with ISO/IEC 9797-1 padding method 2 + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PaddingISO9797_1_Method2 = + &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2; + +/** + * @brief AES CBC Encryption mode descriptor with PKCS7 padding + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7; + +/** + * @brief AES CBC Encryption mode with PKCS7 padding + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Enc_PKCS7 = + &mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7; + +/** + * @brief AES CBC Decryption mode descriptor + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec; + +/** + * @brief AES CBC Decryption mode + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CBC_Dec_NoPadding = + &mcuxClCipher_ModeDescriptor_AES_CBC_Dec; + +/** + * @brief CTR Encryption/Decryption mode descriptor + */ +extern const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR; + +/** + * @brief CTR Encryption/Decryption mode + */ +static mcuxClCipher_Mode_t mcuxClCipher_Mode_AES_CTR = + &mcuxClCipher_ModeDescriptor_AES_CTR; + + + +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLCIPHERMODES_MODES_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_Aes.c b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_Aes.c new file mode 100644 index 000000000..3d416c3d2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_Aes.c @@ -0,0 +1,317 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Els_Aes.c + * @brief implementation of the Skeleton functions of the mcuxClCipher component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipherModes_SkeletonAes) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipherModes_SkeletonAes( + mcuxClSession_Handle_t session, + mcuxClCipher_Context_t * const pContext, + mcuxClKey_Handle_t pKey, + mcuxClCipher_Mode_t pMode, + mcuxCl_InputBuffer_t pIv, + uint32_t ivLength, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut, + uint32_t * const pOutLength, + uint32_t steps //!< steps is a bitmask with one bit reserved for each of the steps below + ) +{ + /* [Design] + ATTN: pOutLength will be incremented by the number of bytes of encrypted data that have been + written to the @p pOut buffer. Except otherwise mentioned processing steps output data + to pOut and update pOutLength + + - Oneshot Initialization (steps == oneshot) + - check if inLength is a multiple of granularity (in the mode), if not exit with ERROR + + - Init processing (steps == oneshot / init) + - if mode requires IV: copy pIv to ivState in context and check IV length == blocklength otherwise error + - set blockBufferUsed in context to zero + + - Update processing (steps == oneshot / update) + - if blockBufferUsed != 0 (this will never be the case for oneshot) + - set elsOptions + - add the new data from the input to blockBuffer and process if possible + - adapt blockBufferUsed + - set elsOptions + - process remaining complete blocks from the input + - add remaining data to blockBuffer, adapt blockBufferUsed (this can happen for oneshot) + + - Finish processing (steps == oneshot / finish) + - dataToCopy = blockBufferUsed rounded up to the next multiple of granularity from the context + - Check if the padding function does not point to NULL, if it does exit with ERROR + - Apply the padding function on blockBuffer from context + - If the output of the padding function is longer than zero, set elsOptions and process the blockBuffer, + store the result in blockBuffer + - copy dataToCopy bytes from blockBuffer to the output and update pOutLength accordingly + - clean up context + + */ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipherModes_SkeletonAes); + + /* Keep track of where we are in input and output */ + uint8_t const* pInput = (uint8_t const*) pIn; + uint8_t * pOutput = (uint8_t *) pOut; + + /* Correct Context type for Aes ELS Skeleton */ + mcuxClCipherModes_Context_Aes_Els_t * pCtx = NULL; + uint32_t cpuWaSizeInWords = 0; + + /* Correct algorithm type for Aes ELS Skeleton */ + const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t *pAlgo = NULL; + + if ((MCUXCLCIPHER_OPTION_INIT == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)) + { + if(NULL == session) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + + pAlgo = pMode->pAlgorithm; + + if(MCUXCLCIPHER_OPTION_ONESHOT == steps) + { + /* Create context for Oneshot, needed by ELS */ + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + cpuWaSizeInWords = MCUXCLCIPHERMODES_INTERNAL_COMPUTE_CPUWORDS(sizeof(mcuxClCipherModes_Context_Aes_Els_t)); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + pCtx = (mcuxClCipherModes_Context_Aes_Els_t *) mcuxClSession_allocateWords_cpuWa(session, cpuWaSizeInWords); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + if(NULL == pCtx) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_FAILURE); + } + + /* inLength needs to be a multiple of the granularity, if this is not the case, return an error. + The granularity is set in the mode as such: + - for CTR it is set to 1 + - for paddingNone it is set to blocksize + - for other padding modes it is set to 1 + */ + if (0u != (inLength % pAlgo->granularity)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + } + else + { + pCtx = (mcuxClCipherModes_Context_Aes_Els_t *) pContext; + } + + /* Store mode and key in context */ + pCtx->common.pMode = pMode; + pCtx->pKey = pKey; + + /* InitialDataLength is initialized with zero (for oneshot, this will always be zero). */ + pCtx->common.blockBufferUsed = 0u; + /* Total number of bytes that were encrypted is initialized with zero */ + pCtx->common.totalInputLength = 0u; + + if ((0u != pAlgo->ivLength) && (ivLength != pAlgo->ivLength)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + + /* If there is an IV, copy it to the ivState buffer. */ + if (0u != pAlgo->ivLength) + { + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF((uint8_t *) pCtx->ivState, pIv, ivLength, MCUXCLAES_BLOCK_SIZE); + } + } + else + { + /* MISRA Ex. 9 to Rule 11.3 */ + pCtx = (mcuxClCipherModes_Context_Aes_Els_t *) pContext; + pAlgo = (const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t *) pCtx->common.pMode->pAlgorithm; + } + + // below variable definitions are used for flow protection of plaintext data process + uint32_t processFPFlag_partData = 0u; + uint32_t processFPFlag_partDataHandling = 0u; + uint32_t bytesRemaining = 0u; + + if ((MCUXCLCIPHER_OPTION_PROCESS == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)) + { + const uint32_t inputLength = inLength; + if (0u != pCtx->common.blockBufferUsed) + { + processFPFlag_partData = 1u; + + /* Number of bytes to copy into the partial data buffer. */ + uint32_t bytesToCopy = (((MCUXCLAES_BLOCK_SIZE - pCtx->common.blockBufferUsed) < (inLength)) ? + (MCUXCLAES_BLOCK_SIZE - pCtx->common.blockBufferUsed) : (inLength)); + + /* Add new data into the partial data buffer and process, if possible. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pCtx->blockBuffer + pCtx->common.blockBufferUsed, + pInput, + bytesToCopy, + MCUXCLAES_BLOCK_SIZE); + /* Update the number of bytes in the partial data buffer.*/ + pCtx->common.blockBufferUsed += bytesToCopy; + + if (MCUXCLAES_BLOCK_SIZE == pCtx->common.blockBufferUsed) + { + processFPFlag_partDataHandling = 1u; + MCUX_CSSL_FP_FUNCTION_CALL(cipherResult, pAlgo->cryptEngine(session, + pCtx, + pCtx->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + pOutput)); + if (cipherResult != MCUXCLCIPHER_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + /* Write to pOutLength how many bytes have been written. */ + *pOutLength += MCUXCLAES_BLOCK_SIZE; + pOutput += MCUXCLAES_BLOCK_SIZE; + + /* The partial data buffer is now empty. */ + pCtx->common.blockBufferUsed = 0u; + } + /* Update input location and remaining length */ + pInput += bytesToCopy; + inLength -= bytesToCopy; + } + + /* Calculate bytes in the input that do not form a full block. */ + bytesRemaining = inLength % MCUXCLAES_BLOCK_SIZE; + + if (inLength >= MCUXCLAES_BLOCK_SIZE) + { + /* Calculate bytes in the input that form full blocks. */ + uint32_t bytesToProcess = inLength - bytesRemaining; + /* Process remaining full blocks from the input. */ + MCUX_CSSL_FP_FUNCTION_CALL(cipherResult1, pAlgo->cryptEngine(session, + pCtx, + pInput, + bytesToProcess, + pOutput)); + if (cipherResult1 != MCUXCLCIPHER_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + /* Update input location */ + pInput += bytesToProcess; + + /* Write to pOutLength how many bytes have been written. */ + *pOutLength += bytesToProcess; + pOutput += bytesToProcess; + } + + if (0u != bytesRemaining) + { + /* If there are still bytes less than one block in the input, write them into the partial data buffer. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pCtx->blockBuffer, + pInput, + bytesRemaining, + MCUXCLAES_BLOCK_SIZE); + pCtx->common.blockBufferUsed = bytesRemaining; + } + /* Update total number of bytes that were encrypted */ + pCtx->common.totalInputLength += inputLength; + } + + /* Number of bytes of the padded block - also used to determine how much data to copy to the output, + therefore it is initialized to the partial data length in case no padding is applied (CTR) . */ + uint32_t padOutLength = pCtx->common.blockBufferUsed; + + if ((MCUXCLCIPHER_OPTION_FINISH == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)) + { + if (NULL != pAlgo->addPadding) + { + /* Apply the padding function specified in the mode on the partial data. */ + MCUX_CSSL_FP_FUNCTION_CALL(padResult, pAlgo->addPadding(pAlgo->blockLength, + pCtx->blockBuffer, + pCtx->common.blockBufferUsed, + pCtx->common.totalInputLength, + pCtx->blockBuffer, + &padOutLength)); + + if (MCUXCLPADDING_STATUS_OK != padResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + } + + if (padOutLength > 0u) + { + /* If padding was added, process the data in the partial data buffer. */ + MCUX_CSSL_FP_FUNCTION_CALL(cipherResult2, pAlgo->cryptEngine(session, + pCtx, + pCtx->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + pCtx->blockBuffer)); + if (cipherResult2 != MCUXCLCIPHER_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_ERROR); + } + + /* Copy the padding to the output and update pOutLength accordingly. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOutput, + pCtx->blockBuffer, + padOutLength, + MCUXCLAES_BLOCK_SIZE); + *pOutLength += padOutLength; + } + } + + if(MCUXCLCIPHER_OPTION_ONESHOT == steps) + { + /* Free context in Session */ + mcuxClSession_freeWords_cpuWa(session, cpuWaSizeInWords); + } + + /* Exit and balance the flow protection. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClCipherModes_SkeletonAes, MCUXCLCIPHER_STATUS_OK, MCUXCLCIPHER_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(((MCUXCLCIPHER_OPTION_INIT == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)), + MCUX_CSSL_FP_CONDITIONAL((0u != ivLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ) + ), + MCUX_CSSL_FP_CONDITIONAL(((MCUXCLCIPHER_OPTION_PROCESS == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)), + MCUX_CSSL_FP_CONDITIONAL((1u == processFPFlag_partData), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((1u == processFPFlag_partDataHandling), + pAlgo->protection_token_engine) + ), + MCUX_CSSL_FP_CONDITIONAL((inLength >= MCUXCLAES_BLOCK_SIZE), + pAlgo->protection_token_engine + ), + MCUX_CSSL_FP_CONDITIONAL((0u != bytesRemaining), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)) + ), + MCUX_CSSL_FP_CONDITIONAL(((MCUXCLCIPHER_OPTION_FINISH == steps) || (MCUXCLCIPHER_OPTION_ONESHOT == steps)), + MCUX_CSSL_FP_CONDITIONAL((NULL != pAlgo->addPadding), + pAlgo->protection_token_addPadding), + MCUX_CSSL_FP_CONDITIONAL((padOutLength > 0u), + pAlgo->protection_token_engine, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ) + ) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_EngineAes.c b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_EngineAes.c new file mode 100644 index 000000000..1cd6dcb2a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Els_EngineAes.c @@ -0,0 +1,352 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Els_EngineAes.c + * @brief implementation of the Engine functions of the mcuxClCipher component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipherModes_EngineEls) + MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClCipher_Status_t) mcuxClCipherModes_EngineEls( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClCipherModes_Context_Aes_Els_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pOut +) +{ + /* [Design] + + - Preconditions + - mode and state in context have been initialized + - inLength is a multiple of the block size (16 bytes) + + - Operation + - set elsOptions according to mode's required operations + - if (CBC Decryption) : copy last input block to temporary buffer + - perform the required operation by calling mcuxClEls_Cipher_Async + - if (CBC Encryption) : copy last output block to ivState + - if (CBC Decryption) : copy temporary buffer to ivState + + - Exit + */ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClCipherModes_EngineEls); + + mcuxClCipherModes_Algorithm_Aes_Els_t pAlgo = (mcuxClCipherModes_Algorithm_Aes_Els_t) pContext->common.pMode->pAlgorithm; + + /* Initialize ELS key info based on the key in the context. */ + mcuxClEls_KeyIndex_t keyIdx = (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->pKey); + uint8_t const * pKey = mcuxClKey_getLoadedKeyData(pContext->pKey); + uint8_t tempBlock[MCUXCLAES_BLOCK_SIZE]; + uint8_t* nextState = NULL; + uint32_t keyLength = mcuxClKey_getSize(pContext->pKey); + + /* Initialize ELS options. */ + mcuxClEls_CipherOption_t elsOptions; + elsOptions.word.value = 0u; + elsOptions.bits.dcrpt = (uint8_t) pAlgo->direction; + elsOptions.bits.cphmde = (uint8_t) pAlgo->mode; + + if(elsOptions.bits.cphmde != MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB) { + elsOptions.bits.cphsoe = MCUXCLELS_CIPHER_STATE_OUT_ENABLE; + #ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + elsOptions.bits.cphsie = MCUXCLELS_CIPHER_STATE_IN_ENABLE; + #endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + } + + /* Copy last input block to a temp buffer to handle in-place operations. Needed in case of CBC Mode decryption */ + if(MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC == elsOptions.bits.cphmde) + { + if (MCUXCLELS_CIPHER_DECRYPT == pAlgo->direction) + { + MCUXCLMEMORY_FP_MEMORY_COPY(tempBlock, (uint8_t const*)(pIn + inLength - MCUXCLAES_BLOCK_SIZE), MCUXCLAES_BLOCK_SIZE); + nextState = tempBlock; + } + else + { + nextState = (uint8_t*)(pOut + inLength - MCUXCLAES_BLOCK_SIZE); + } + } + if (MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->pKey)) + { + elsOptions.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; + } + else if (MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->pKey)) + { + elsOptions.bits.extkey = MCUXCLELS_CIPHER_INTERNAL_KEY; + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_EngineEls, MCUXCLCIPHER_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(cipherResult, mcuxClEls_Cipher_Async(elsOptions, + keyIdx, + pKey, + keyLength, + pIn, + inLength, + (uint8_t *) pContext->ivState, + pOut)); + if (cipherResult != MCUXCLELS_STATUS_OK_WAIT) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_EngineEls, MCUXCLCIPHER_STATUS_ERROR); + } + MCUX_CSSL_FP_FUNCTION_CALL(wait1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if (wait1 != MCUXCLELS_STATUS_OK) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_EngineEls, MCUXCLCIPHER_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + uint8_t *pFinalOutputStartAddress = pOut; + uint32_t finalLength = inLength; + if (MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR == pAlgo->mode) + { + pFinalOutputStartAddress = (uint8_t *)pContext->ivState; + finalLength = MCUXCLAES_BLOCK_SIZE; + } + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(pFinalOutputStartAddress, finalLength)); + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_EngineEls, MCUXCLCIPHER_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + if(MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC == elsOptions.bits.cphmde) + { + MCUXCLMEMORY_FP_MEMORY_COPY((uint8_t *) pContext->ivState, nextState, MCUXCLAES_BLOCK_SIZE); + } + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClCipherModes_EngineEls, MCUXCLCIPHER_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC == elsOptions.bits.cphmde), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLELS_CIPHER_DECRYPT == pAlgo->direction), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async)); + +} + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_NoPadding_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_None + granularity = 16 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_None, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_None), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = 0u, + .granularity = 16u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_ISO9797_1_Method1 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method1, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method1), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = 0u, + .granularity = 1u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_ISO9797_1_Method2 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method2, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method2), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = 0u, + .granularity = 1u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingPKCS7_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_PKCS7 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_PKCS7, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_PKCS7), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = 0u, + .granularity = 1u +}; + + + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Dec_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_None + granularity = 16 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_None, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_None), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB, + .direction = MCUXCLELS_CIPHER_DECRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = 0u, + .granularity = 16u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_NoPadding_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_None + granularity = 16 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_None, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_None), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 16u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_ISO9797_1_Method1 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method1, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method1), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 1u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_ISO9797_1_Method2 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method2, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method2), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 1u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingPKCS7_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_PKCS7 + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_PKCS7, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_PKCS7), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 1u +}; + + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Dec_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + mcuxClPadding_addPadding_None + granularity = 16 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = mcuxClPadding_addPadding_None, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_None), + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC, + .direction = MCUXCLELS_CIPHER_DECRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 16u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipherModes_AlgorithmDescriptor_Aes_Els_t mcuxClCipherModes_AlgorithmDescriptor_AES_CTR_Els = { +/* [Design] + mcuxClCipherModes_ModeSkeletonAes + granularity = 1 +*/ + .cryptEngine = mcuxClCipherModes_EngineEls, + .addPadding = NULL, + .protection_token_engine = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_EngineEls), + .protection_token_addPadding = 0u, + .mode = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR, + .direction = MCUXCLELS_CIPHER_ENCRYPT, + .blockLength = MCUXCLAES_BLOCK_SIZE, + .ivLength = MCUXCLAES_BLOCK_SIZE, + .granularity = 1u +}; diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Helper.c b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Helper.c new file mode 100644 index 000000000..94943a7ac --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Helper.c @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCipherModes_MemClear) +void mcuxClCipherModes_MemClear(uint8_t *pDst, uint32_t length) +{ + for (uint32_t i = 0u; i < length; ++i) + { + pDst[i] = 0u; + } +} diff --git a/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Modes.c b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Modes.c new file mode 100644 index 000000000..3f846424e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCipherModes/src/mcuxClCipherModes_Modes.c @@ -0,0 +1,119 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClCipherModes_Modes.c + * @brief Definition of the mode descriptors for all provided Cipher modes + */ + +#include +#include +#include +#include + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const mcuxClCipher_ModeFunctions_t mcuxClCipher_ModeFunctions_CipherModes = { + .crypt = mcuxClCipherModes_SkeletonAes, + .protection_token_crypt = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCipherModes_SkeletonAes) +}; + +/* + * Crypt Modes using the ELS + */ +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_NoPadding = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_NoPadding_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method1_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingISO9797_1_Method2_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Dec = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Dec_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_ECB_Enc_PaddingPKCS7 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_ECB_Enc_PaddingPKCS7_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_NoPadding = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_NoPadding_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method1_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingISO9797_1_Method2_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + + +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Enc_PaddingPKCS7 = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Enc_PaddingPKCS7_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CBC_Dec = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CBC_Dec_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClCipher_ModeDescriptor_t mcuxClCipher_ModeDescriptor_AES_CTR = { + .pModeFunctions = (const void *) &mcuxClCipher_ModeFunctions_CipherModes, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithm = (void *) &mcuxClCipherModes_AlgorithmDescriptor_AES_CTR_Els + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Buffer.h b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Buffer.h new file mode 100644 index 000000000..9c6f1cadb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Buffer.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCORE_BUFFER_H_ +#define MCUXCLCORE_BUFFER_H_ + +#include // Exported features flags header +#include + +/** + * \addtogroup mcuxClAPI MCUX CL -- API + * + * \addtogroup mcuxClCore Core API + * \brief Essential types and functionality. + * \ingroup mcuxClAPI + */ + +/** + * \defgroup clCoreTypes Core type definitions + * \brief Types used by basically all operations. + * \ingroup mcuxClCore + */ + + +/** + * \brief Input buffer type + * \ingroup clCoreTypes + * + * This type provides a pointer to the memory location that should be used to + * read input data from. + */ +typedef const uint8_t * const mcuxCl_InputBuffer_t; + +/** + * \brief Generic buffer type + * \ingroup clCoreTypes + * + * This type provides a pointer to the memory location that can be used for + * both reading input data and writing output data. + */ +typedef uint8_t * const mcuxCl_Buffer_t; + + +#endif /* MCUXCLCORE_BUFFER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h new file mode 100644 index 000000000..f3c25b125 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Examples.h @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCORE_EXAMPLES_H_ +#define MCUXCLCORE_EXAMPLES_H_ + +#include +#include + +/** + * \def MCUXCLEXAMPLE_FUNCTION + * \brief Macro to indicate that the symbol is an example function. + */ +// TODO CLNS-3599: #define MCUXCLEXAMPLE_FUNCTION(_name) uint32_t _name(void) +#define MCUXCLEXAMPLE_FUNCTION(_name) bool _name(void) + +/** + * \def MCUXCLEXAMPLE_STATUS_OK + * \brief Example execution completed successfully. + */ +#define MCUXCLEXAMPLE_STATUS_OK true // TODO CLNS-3599: 0xC001C0DEu + +/** + * \def MCUXCLEXAMPLE_OK + * \brief Example execution completed successfully. + * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_OK} + */ +#define MCUXCLEXAMPLE_OK MCUXCLEXAMPLE_STATUS_OK + +/** + * \def MCUXCLEXAMPLE_STATUS_ERROR + * \brief Example execution resulted in an unexpected error. + */ +#define MCUXCLEXAMPLE_STATUS_ERROR false // TODO CLNS-3599: 0xEEEEEEEEu + +/** + * \def MCUXCLEXAMPLE_ERROR + * \brief Example execution resulted in an unexpected error. + * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_ERROR} + */ +#define MCUXCLEXAMPLE_ERROR MCUXCLEXAMPLE_STATUS_ERROR + + +/** + * \def MCUXCLEXAMPLE_STATUS_FAILURE + * \brief Example execution resulted in an expected failure. + */ +#define MCUXCLEXAMPLE_STATUS_FAILURE false // TODO CLNS-3599: 0xFFFFFFFFu + +/** + * \def MCUXCLEXAMPLE_FAILURE + * \brief Example execution resulted in an expected failure. + * \deprecated{Replaced by MCUXCLEXAMPLE_STATUS_FAILURE} + */ +#define MCUXCLEXAMPLE_FAILURE MCUXCLEXAMPLE_STATUS_FAILURE + +/** + * \brief Macro to calculate the maximum of two values. + */ +#define MCUXCLEXAMPLE_MAX( x, y ) ( ( x ) > ( y ) ? ( x ) : ( y ) ) + +/** + * \brief Macro to calculate the ceiling of x/y. + */ +#define MCUXCLEXAMPLE_CEILING(x,y) (((x) + (y) - 1U) / (y)) + +/** + * \brief Assert whether two buffers are equal. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClCore_assertEqual) +static inline bool mcuxClCore_assertEqual(const uint8_t * const x, const uint8_t * const y, uint32_t length) +{ + for (uint32_t i = 0; i < length; ++i) + { + if (x[i] != y[i]) + { + return false; + } + } + + return true; +} + +#endif /* MCUXCLCORE_EXAMPLES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h new file mode 100644 index 000000000..4c17d830c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_FunctionIdentifiers.h @@ -0,0 +1,6014 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClCore_FunctionIdentifiers.h + * @brief Definition of function identifiers for the flow protection mechanism. + * + * @note This file might be post-processed to update the identifier values to + * proper/secure values. + */ + +#ifndef MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ +#define MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ + +#include // Exported features flags header + +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwVersion (0x6366u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwConfig (0x4C37u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetHwState (0x7907u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Enable_Async (0x44DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Reset_Async (0x5457u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Disable (0x466Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntEnableFlags (0x0DB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetIntEnableFlags (0x4E2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetIntFlags (0x0FB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetIntFlags (0x55CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_WaitForOperation (0x34B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_LimitedWaitForOperation (0x6CE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ResetErrorFlags (0x710Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorCode (0x7456u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetErrorLevel (0x59D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_Async (0x59D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Enable (0x496Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ShaDirect_Disable (0x23CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hash_ShaDirect (0x7C29u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cipher_Async (0x13D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyGen_Async (0x2E95u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchange_Async (0x5762u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccKeyExchangeInt_Async (0x555Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccSign_Async (0x3C36u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerify_Async (0x5B0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_EccVerifyInt_Async (0x62ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp (0x5578u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_SecModExp_SqrMultAws (0x067Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Init_Async (0x607Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_PartialInit_Async (0x035Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateAad_Async (0x0F59u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_UpdateData_Async (0x2E9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Aead_Finalize_Async (0x2DA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Cmac_Async (0x1793u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_LoadConfig_Async (0x693Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_Trim_Async (0x09BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hmac_Async (0x4BE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Rfc5869_Async (0x5B92u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp800108_Async (0x27A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async (0x3F84u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async (0x7545u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyDelete_Async (0x58F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvision_Async (0x5ED0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyProvisionRom_Async (0x64B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImport_Async (0x1397u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyImportPuk_Async (0x2CAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_KeyExport_Async (0x258Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_handleKeyExportError (0x46B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequest_Async (0x4D9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgRequestRaw_Async (0x62D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoad_Async (0x2756u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async (0x42F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async (0x62E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_Reseed (0x5939u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_Init_Async (0x3BC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandomWord (0x3AC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Prng_GetRandom (0x49D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetKeyProperties (0x7E14u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compute (0x2DAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_compare (0x42DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_verify (0x3D45u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_init (0x416Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_process (0x5873u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_finish (0x17D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_selftest (0x68F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_export_state (0x7871u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHash_import_state (0x79C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Md5 (0x25CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Md5 (0x29F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Md5 (0x396Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha1 (0x61B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha1 (0x7196u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha1 (0x52D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha224 (0x7958u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha224 (0x6B19u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha224 (0x1A76u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha256 (0x5AC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha256 (0x4F1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha256 (0x39C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha384 (0x4E5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha384 (0x115Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha384 (0x512Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_Sha512 (0x28E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_Sha512 (0x15E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_Sha512 (0x54CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3_shake (0x4D1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3_shake (0x1B8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3_shake (0x1EC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_oneShot_sha3 (0x7326u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_process_sha3 (0x3B94u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_finish_sha3 (0x2F49u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_finishAbsorb (0x25F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_C_shake_squeeze (0x2D4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_createShakeAlgorithm (0x5B23u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_Sha2 (0x784Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_Sha2 (0x076Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_Sha2 (0x23B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_oneShot_MiyaguchiPreneel (0x45F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_process_MiyaguchiPreneel (0x5C1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Sgi_finish_MiyaguchiPreneel (0x166Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_process_Sha2 (0x36C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_finish_Sha2 (0x73B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Els_oneShot_Sha2 (0x4E33u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_dmaProtectionAddressReadback (0x5C71u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha256 (0x718Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_Ranger5_oneShot_Sha384 (0x3B0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2 (0x195Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_els_core_sha2_direct (0x4EACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_md5 (0x2CE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha1 (0x70B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha256 (0x72C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_sha512 (0x7B82u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_c_keccak (0x54DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha3_Keccak (0x3627u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha1 (0x33C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha256 (0x1A76u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_core_secSha512 (0x3E16u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha (0x4E5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha (0x115Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha (0x33ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_oneShot_SecSha3 (0x0FE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_process_SecSha3 (0x2AF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHashModes_finish_SecSha3 (0x4771u) +#define MCUX_CSSL_FP_FUNCID_mcuxClXof_compute (0x41AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXof_init (0x6A72u) +#define MCUX_CSSL_FP_FUNCID_mcuxClXof_process (0x5396u) +#define MCUX_CSSL_FP_FUNCID_mcuxClXof_generate (0x1A6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXof_finish (0x6B0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_generate_shake (0x271Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_init_sha3_shake (0x22EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_process_sha3_shake (0x2A37u) +#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_oneshot_sha3_shake (0x0E7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClXofModes_C_finish_shake (0x3572u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadCopro (0x2579u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_loadMemory (0x7962u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_flush (0x26ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setKeyproperties (0x3879u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_LoadFuncPtr_t (0x55C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_FlushFuncPtr_t (0x476Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_init (0x3635u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_setProtection (0x6C3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement (0x7A19u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect (0x33A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compute (0x22F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_compare (0x7686u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_init (0x16EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_process (0x5CB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_finish (0x4D59u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_verify (0x29F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compute (0x36ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_compare (0x316Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_init (0x6B1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_process (0x29CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_finish (0x70DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_verify (0x3077u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_createGmacMode (0x7CB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Oneshot (0x6783u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Init (0x528Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Update (0x475Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CMAC_Finalize (0x7295u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Oneshot (0x2C9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Init (0x5F41u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Update (0x5786u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMacModes_Engine_CBCMAC_Finalize (0x6734u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Sw (0x17D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Sw (0x1D4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Sw (0x47C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Sw (0x323Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Oneshot_Els (0x2B6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Init_Els (0x34D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Update_Els (0x66A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_Engine_Finalize_Els (0x4D2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_compute (0x453Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_init (0x43BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_process (0x4BA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_finish (0x7623u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_prepareHMACKey (0x46E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClHmac_createHmacMode (0x634Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_InitLocalUptrt (0x6762u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_LeadingZeros (0x0DE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ShiftModulus (0x63E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_NDash (0x236Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QDash (0x60BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_QSquared (0x197Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModInv (0x48DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ModExp_SqrMultL2R (0x791Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestInstantiate_Async (0x5C27u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestExtract_Async (0x2E9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesEcb_Async (0x0B97u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Rng_DrbgTestAesCtr_Async (0x743Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_clear (0x6BC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy (0x126Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_set (0x6AA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Initialize (0x7319u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Deinitialize (0x7315u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_GenerateUPTRT (0x1C5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_Calc (0x152Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcConst (0x6693u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_CalcFup (0x2B71u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForFinish (0x255Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_WaitForReady (0x05AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_init (0x58B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_allocateCpuBuffer (0x6F09u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_freeAllCpuBuffers (0x58AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRtf (0x057Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_cleanup (0x2CD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_destroy (0x6A4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setSecurityOptions (0x0F63u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setRandom (0x78B4u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_sha512 (0x6E2Cu) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_aead (0x4D4Du) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p256 (0x1769u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ecdsa_p384 (0x7526u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hmac (0x7067u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_eckxh (0x2D36u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_extract (0x61ABu) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ctr (0x3E64u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_drbg_ecb (0x415Fu) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_ckdf (0x3E83u) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest_hkdf (0x4E2Du) +#define MCUX_CSSL_FP_FUNCID_nboot_selftest (0x4F58u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Extract_Async (0x1F23u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Ckdf_Sp80056c_Expand_Async (0x7427u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Hkdf_Sp80056c_Async (0x307Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_keyProv (0x59AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_get_oem_cust_cert_dice_puk (0x436Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_eck_sign (0x1F89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_enc_blk (0x7C43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_key_gen (0x653Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_sb_store_key (0x75E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_rts_get_id_clns (0x5935u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_gen_oem_master_share (0x5D83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_set_oem_master_share (0x7D50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_store_key (0x1AADu) +#define MCUX_CSSL_FP_FUNCID_mcuxClTrustProv_rfc3394_wrap_manual (0x6B70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_mcux_ssf_insert_cert (0x15E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify_P384 (0x155Du) +#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_cmac (0x3E34u) +#define MCUX_CSSL_FP_FUNCID_nboot_key_delete (0x29DAu) +#define MCUX_CSSL_FP_FUNCID_nboot_key_store_export_key (0x6A4Eu) +#define MCUX_CSSL_FP_FUNCID_nboot_key_store_is_loaded (0x7744u) +#define MCUX_CSSL_FP_FUNCID_nboot_key_store_init (0x32BCu) +#define MCUX_CSSL_FP_FUNCID_nboot_key_store_generate_rom_key (0x259Du) +#define MCUX_CSSL_FP_FUNCID_nboot_cmac_authenticate_romapi (0x4CB5u) +#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_manifest (0x76C4u) +#define MCUX_CSSL_FP_FUNCID_nboot_sb3_load_block (0x36E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockVerify (0x1BA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDecrypt_Start (0x238Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockEncrypt_Start (0x785Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockCrypt_Finish (0x478Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_BlockDeriveKey (0x54EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestImportPck (0x437Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_ManifestDeriveKdk (0x732Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_DeletePck (0x5A5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Cleanup (0x4ED8u) +#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa (0x6E62u) +#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_romapi (0x2D99u) +#define MCUX_CSSL_FP_FUNCID_nboot_sb3_img_authenticate_ecdsa (0x5AC6u) +#define MCUX_CSSL_FP_FUNCID_nboot_img_authenticate_ecdsa_internal (0x4E65u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_none (0x5A4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_protect_fct_ckdf (0x588Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveTwoScalars (0x28DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble_NIST (0x4EB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult_NIST (0x3672u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR_NIST (0x05E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd_NIST (0x629Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SwitchEndianness_P384 (0x7C8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_rts_insert_cert (0x0EBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetRandomStartDelay (0x134Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetRandomStartDelay (0x51C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLock (0x4AE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ReleaseLock (0x61D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_IsLocked (0x646Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_SetMasterUnlock (0x30B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_ConfigureCommandCRC (0x4CF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetCommandCRC (0x0B9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_VerifyVsRefCRC (0x5C17u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_RespGen_Async (0x7256u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportBigEndianToPkc (0x5F30u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportBigEndianFromPkc (0x3D1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Verify (0x5CA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SwitchEndianness (0x36A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointCheckAffineNR (0x65ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RepeatPointDouble (0x7986u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointFullAdd (0x10FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_PointMult (0x59B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_RandomizeUPTRT (0x1D87u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ReRandomizeUPTRT (0x5E54u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SecurePointMult (0x03BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwVersion (0x0CCFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetHwState (0x0B57u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntEnableFlags (0x176Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntEnableFlags (0x346Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ResetIntFlags (0x3E29u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_SetIntFlags (0x5D2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Configuration (0x4EE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Lock (0x1177u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_ConfigEval (0x28EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Enroll (0x31B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reconstruct (0x3C9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_KeyGeneration (0x3EC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_GetIntFlags (0x6AD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_img_authenticate_ecdsa (0x788Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_dev_set_wrap_data (0x5369u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge (0x4A6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_mcux (0x48D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCLTrustProv_nboot_isp_hsm_dev_auth_challenge_oem (0x12FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_TrailingZeros (0x037Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ReduceModEven (0x235Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_KeyGen (0x6726u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportBigEndianFromPkc (0x19E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Int_CoreKeyGen (0x5C87u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_ResetEventCounter (0x14EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GlitchDetector_GetEventCounter (0x2D72u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportBigEndianToPkc (0x271Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Sign (0x59A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_PointMult (0x5AD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_public (0x7469u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privatePlain (0x0E7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_verify (0x2D78u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noVerify (0x689Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_sign (0x50DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Verify (0x270Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivideOdd (0x509Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssVerify (0x69B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_mgf1 (0x7878u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_privateCRT (0x69D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_sign (0x1C7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_noEncode (0x758Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pssEncode (0x3C66u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_SetupEnvironment (0x318Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_SetupEnvironment (0x6A39u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_SecureScalarMult_XZMontLadder (0x4D55u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_X (0x147Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeScalar (0x5197u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_MontDH_DecodeCoordinate (0x44F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_GenerateMultiplicativeBlinding (0x03BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_GetLastDmaAddress (0x3E51u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_CompareDmaFinalOutputAddress (0x6A3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyAgreement (0x6933u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Mont_DhKeyGeneration (0x097Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMath_ExactDivide (0x3CE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_init (0x456Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_reseed (0x4CE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_generate (0x7D28u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_uninit (0x41FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_selftest (0x51E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_checkSecurityStrength (0x3B13u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncInit (0x4E8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandom_ncGenerate (0x20DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPQDistance (0x345Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ModInv (0x178Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_MillerRabinTest (0x5F42u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_ComputeD (0x6A36u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_VerifyE (0x53F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_GenerateProbablePrime (0x1ACEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Crt (0x5F12u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_UpdateRefCRC (0x05BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_TestPrimeCandidate (0x10EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_Plain (0x58B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ImportLittleEndianToPkc (0x275Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_ExportLittleEndianFromPkc (0x0BDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureImportLittleEndianToPkc (0x64F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPkc_SecureExportLittleEndianFromPkc (0x16E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_Weier_SetupEnvironment (0x54B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_SkeletonAes (0x05B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_crypt (0x1BB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init (0x7683u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_process (0x61E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_finish (0x60EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_None (0x529Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Random (0x1B9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_Decrypt (0x368Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method1 (0x33C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_ISO9797_1_Method2 (0x15BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_PKCS7 (0x3974u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_None (0x5AA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Default (0x075Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method1 (0x61B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_ISO9797_1_Method2 (0x6D1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_PKCS7 (0x7923u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_removePadding_Stream (0x3C6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesGcm (0x6731u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_crypt (0x68BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init (0x6EA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process (0x3E89u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_process_adata (0x19D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_finish (0x21BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_verify (0x6D0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_SkeletonAesCcm (0x5633u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesCcmEls (0x25A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_EngineAesGcmEls (0x3BA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_encrypt (0x5C65u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_decrypt (0x137Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_encrypt (0x3B89u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_init_decrypt (0x2F0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_getEntropyInput (0x34E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_generate (0x246Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_init (0x5A1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_reseed (0x41E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_ElsMode_selftest (0x14DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm (0x517Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm (0x42FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_generatePrHandler (0x447Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm (0x54BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PTG3_selftestAlgorithm (0x435Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateOutput (0x6D8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_UpdateState (0x35A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_bcc (0x5B54u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_df (0x13E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_updateEntropyInput (0x525Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction (0x70DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction (0x5CCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createTestFromNormalMode (0x72C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction (0x327Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction (0x3C33u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_DRBG_AES_Internal_blockcipher (0x5E98u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled (0x541Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction (0x4755u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm (0x22F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PTG3 (0x72A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction (0x6E2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction (0x20FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction (0x72A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction (0x6939u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_createPatchMode (0x642Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_incV (0x09AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction (0x4BB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_Init (0x73D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRoPuf_Reset (0x334Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_EngineEls (0x3B46u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair (0x2D6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature (0x43F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature (0x15DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Encode_encrypt (0x3B70u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_pkcs1v15Decode_decrypt (0x56CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_SetupEnvironment (0x31CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateCustomKeyType (0x4D6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateDomainParams (0x321Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClPadding_addPadding_MAC_ISO9797_1_Method2 (0x5857u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepEncode (0x6A27u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_oaepDecode (0x2DC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_init (0x7346u) +#define MCUX_CSSL_FP_FUNCID_mcuxClPrng_generate (0x44F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_RecodeAndReorderScalar (0x39E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_FixScalarMult (0x08EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainFixScalarMult25519 (0x612Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectComb (0x0EAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PointDoubleEd25519 (0x3E43u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_MixedPointAddEd25519 (0x13EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainPtrSelectML (0x4D99u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_VarScalarMult (0x05BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PlainVarScalarMult (0x7C54u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_TwEd_PrecPointImportAndValidate (0x7323u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSb3_Ckdf (0x19E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_verify (0x72B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_crypt (0x0F78u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_finish (0x0E8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process (0x1375u) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_init (0x2A5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAeadModes_process_adata (0x18D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_GenerateKeyPair (0x19D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_generate_keypair (0x5BC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_KeyGeneration_GenerateKeyPair (0x47A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_Public (0x195Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_NoHwAcc_UtilsAsym_ModularExponentiation (0x47F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcInitialize (0x294Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_Empty_PkcDeinitialize (0x69C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_BlindedScalarMult (0x2AD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_BlindedScalarMult (0x76A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PointDecFct_SEC (0x3674u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_S5xyStub (0x0F96u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_S5xyStub (0x05F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_selftest (0x05F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_sign (0x08FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_verify (0x46DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_init (0x169Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSignature_finish (0x61DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_selftest (0x3571u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_SetupEnvironment (0x132Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetVersionAndConfig (0x694Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetStatus (0x346Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SyncReset (0x3DC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntEnable (0x0F2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_GetIntEnable (0x683Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ClearIntStatus (0x6D94u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_SetIntStatus (0x15E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_Lock (0x68B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsLocked (0x5653u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_IsIndexLocked (0x3B19u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_StartEnable (0x725Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ContinueEnable (0x0B5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_LockIndex (0x30BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_ResetIndex (0x1F19u) +#define MCUX_CSSL_FP_FUNCID_mcuxClGlikey_EndOperation (0x17C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_CalcHashModN (0x1A79u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed25519 (0x6CA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_DecodePoint_Ed448 (0x58DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_InitPrivKeyInputMode (0x536Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_setResource (0x3785u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_configure_job (0x761Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_request (0x559Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_release (0x48EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_triggerUserCallback (0x1D36u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_init (0x7968u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_handle_interrupt (0x7634u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_request (0x23D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_release (0x78CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxClTrng_checkConfig (0x471Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_linkKeyPair (0x50F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithmeticOperation (0x61A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointAdd (0x0797u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_RemoveBlinding (0x6CE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_ScalarMult (0x599Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_agreement_selftest (0x5939u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDH_KeyAgreement (0x10F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_encrypt (0x6279u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_decrypt (0x1F1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_encrypt (0x5659u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_init_decrypt (0x119Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi (0x6C3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi (0x1DB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_encrypt_Sgi (0x4DD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_init_decrypt_Sgi (0x5EE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi (0x3374u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finish_Sgi (0x51ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_selftest_VerifyArrays (0x5D13u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_InterleaveScalar (0x1FA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PrivateKeyValidation (0x0DEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_WeierECC_PublicKeyValidation (0x2F32u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateHashPrefix (0x4957u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateProtocolDescriptor (0x19CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignatureModeDescriptor (0x5BC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_PreHashMessage (0x396Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateKeyPair_Core (0x436Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_GenerateSignature_Core (0x47E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_EdDSA_VerifySignature_Core (0x57A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_GenerateSignature (0x3CCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ECDSA_VerifySignature (0x5574u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed (0x37D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClEcc_ArithOp_PointSub (0x395Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivation (0x3B2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_108 (0x784Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_108 (0x3D38u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ISOIEC_18033_2 (0x1A3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ISOIEC_18033_2 (0x15CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_NIST_SP800_56C (0x45E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_OneStep (0x7E84u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_NIST_SP800_56C_TwoStep (0x4CDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_ANSI_X9_63 (0x4E5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_ANSI_X9_63 (0x115Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_Derivation_ModeConstructor_HKDF (0x6786u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKey_derivationEngine_HKDF (0x54B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_Randombytes (0x2D1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_XOF_Hash (0x78D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Init_And_Absorb (0x2CCBu) +#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Absorb (0x64F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClUtilsPqc_ShakeXXX_Squeeze (0x6C1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Keypair (0x307Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Sign (0x6DE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Verify (0x24EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_Verify_checkInputs (0x6786u) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_computeMu (0x54B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxClDilithium_Internal_performPolynomialArithmetic (0x58DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxClMemory_copy_reversed (0x7B41u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcInitialize (0x3DA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxClRsa_PkcDeinitialize (0x1CB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_backup (0x23E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClResource_restore (0x652Du) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_resume (0x3AB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxClMac_selftest (0x42AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClAead_selftest (0x24AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC16 (0x425Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_computeCRC32 (0x4B39u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_verifyContextCrc (0x2C7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipher_computeContextCrc (0x325Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC32 (0x4EE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCrc_Internal_updateCRC16 (0x706Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKem_encapsulate (0x15D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxClKem_decapsulate (0x05DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxClKyber_KeyGen (0x1B99u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_encrypt_Sgi_nonBlocking (0x474Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_decrypt_Sgi_nonBlocking (0x4BC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_setWa (0x2CD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClSession_job_getWa (0x18F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_process_Sgi_nonBlocking (0x7790u) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Multipart (0x1A6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxClCipherModes_finishNonBlocking_Oneshot (0x75C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxClLtc_BackupStatus (0x1697u) +#define MCUX_CSSL_FP_FUNCID_mcuxClLtc_RestoreStatus (0x135Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_180 (0x4FA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_181 (0x243Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_182 (0x1F16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_183 (0x683Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_184 (0x6E31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_185 (0x623Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_186 (0x47E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_187 (0x53C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_188 (0x6535u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_189 (0x2697u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_190 (0x07E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_191 (0x599Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_192 (0x2B93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_193 (0x4AF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_194 (0x2C5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_195 (0x518Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_196 (0x738Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_197 (0x49E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_198 (0x43BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_199 (0x296Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_200 (0x54F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_201 (0x2B36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_202 (0x58C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_203 (0x7632u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_204 (0x2B78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_205 (0x5CF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_206 (0x1C75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_207 (0x39A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_208 (0x5E2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_209 (0x728Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_210 (0x5D2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_211 (0x6399u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_212 (0x724Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_213 (0x53A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_214 (0x1D2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_215 (0x5726u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_216 (0x03B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_217 (0x0D37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_218 (0x362Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_219 (0x4AE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_220 (0x4BD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_221 (0x7945u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_222 (0x5B34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_223 (0x749Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_224 (0x4D56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_225 (0x1D53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_226 (0x1573u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_227 (0x78C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_228 (0x4C6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_229 (0x65D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_230 (0x5599u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_231 (0x4EE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_232 (0x256Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_233 (0x2CB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_234 (0x4753u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_235 (0x0E6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_236 (0x52DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_237 (0x2F70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_238 (0x1877u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_239 (0x5CAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_240 (0x325Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_241 (0x11AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_242 (0x63B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_243 (0x5917u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_244 (0x2D95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_245 (0x1EC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_246 (0x27ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_247 (0x1CBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_248 (0x037Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_249 (0x4BC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_250 (0x4A6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_251 (0x7856u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_252 (0x5BA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_253 (0x6B92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_254 (0x32E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_255 (0x2F1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_256 (0x136Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_257 (0x2C6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_258 (0x356Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_259 (0x46ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_260 (0x319Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_261 (0x5B2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_262 (0x1BCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_263 (0x33A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_264 (0x2B59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_265 (0x6E07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_266 (0x529Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_267 (0x1B95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_268 (0x78CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_269 (0x21F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_270 (0x549Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_271 (0x0BF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_272 (0x6CA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_273 (0x4575u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_274 (0x06FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_275 (0x1B33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_276 (0x4CB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_277 (0x3D70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_278 (0x632Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_279 (0x2C4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_280 (0x51B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_281 (0x459Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_282 (0x6AAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_283 (0x19ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_284 (0x7B84u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_285 (0x53ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_286 (0x3B25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_287 (0x2D33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_288 (0x3A66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_289 (0x5D86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_290 (0x3A0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_291 (0x6F12u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_292 (0x6633u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_293 (0x5E0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_294 (0x253Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_295 (0x1D39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_296 (0x06CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_297 (0x3A4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_298 (0x7C0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_299 (0x7172u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_300 (0x2B56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_301 (0x24DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_302 (0x46F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_303 (0x3C9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_304 (0x731Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_305 (0x5A2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_306 (0x117Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_307 (0x6785u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_308 (0x53E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_309 (0x3596u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_310 (0x03BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_311 (0x3CE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_312 (0x54D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_313 (0x362Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_314 (0x530Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_315 (0x7A32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_316 (0x3475u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_317 (0x61CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_318 (0x668Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_319 (0x5876u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_320 (0x549Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_321 (0x721Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_322 (0x3578u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_323 (0x2A3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_324 (0x63C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_325 (0x4ED4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_326 (0x2ABCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_327 (0x231Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_328 (0x1EE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_329 (0x0E73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_330 (0x29DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_331 (0x5A2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_332 (0x48FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_333 (0x35AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_334 (0x2D74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_335 (0x3B8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_336 (0x0577u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_337 (0x6D58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_338 (0x7929u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_339 (0x6E0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_340 (0x47D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_341 (0x4E4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_342 (0x6F0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_343 (0x4F15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_344 (0x7D60u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_345 (0x32C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_346 (0x685Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_347 (0x1ED4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_348 (0x4EA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_349 (0x27B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_350 (0x1C9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_351 (0x45CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_352 (0x38CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_353 (0x3A55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_354 (0x5536u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_355 (0x5E29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_356 (0x427Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_357 (0x5D52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_358 (0x272Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_359 (0x05EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_360 (0x2D8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_361 (0x3F28u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_362 (0x32F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_363 (0x70ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_364 (0x28BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_365 (0x74C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_366 (0x3663u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_367 (0x266Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_368 (0x1EB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_369 (0x395Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_370 (0x6A96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_371 (0x08FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_372 (0x0CDEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_373 (0x4F0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_374 (0x2FA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_375 (0x4D27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_376 (0x2B47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_377 (0x2CC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_378 (0x507Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_379 (0x6A56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_380 (0x7DA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_381 (0x25DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_382 (0x371Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_383 (0x5E86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_384 (0x1EE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_385 (0x52B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_386 (0x17D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_387 (0x370Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_388 (0x5AB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_389 (0x11FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_390 (0x6C2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_391 (0x28F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_392 (0x6C8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_393 (0x71CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_394 (0x12BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_395 (0x529Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_396 (0x07ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_397 (0x5336u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_398 (0x40DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_399 (0x59B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_400 (0x7784u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_401 (0x5966u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_402 (0x2973u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_403 (0x15ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_404 (0x36AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_405 (0x0ADBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_406 (0x173Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_407 (0x3999u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_408 (0x5A95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_409 (0x4B2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_410 (0x46D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_411 (0x519Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_412 (0x646Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_413 (0x0F1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_414 (0x0ABBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_415 (0x571Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_416 (0x59C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_417 (0x334Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_418 (0x7827u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_419 (0x29B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_420 (0x2CCDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_421 (0x37C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_422 (0x0DBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_423 (0x7435u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_424 (0x66E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_425 (0x49F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_426 (0x7926u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_427 (0x5C96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_428 (0x45AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_429 (0x185Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_430 (0x38CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_431 (0x619Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_432 (0x3927u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_433 (0x38D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_434 (0x67C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_435 (0x5E1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_436 (0x73A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_437 (0x71F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_438 (0x435Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_439 (0x651Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_440 (0x7B24u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_441 (0x625Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_442 (0x53AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_443 (0x11D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_444 (0x5789u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_445 (0x3E62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_446 (0x623Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_447 (0x7895u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_448 (0x7370u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_449 (0x2D71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_450 (0x1C2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_451 (0x5D1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_452 (0x5F22u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_453 (0x46F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_454 (0x1CD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_455 (0x4CADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_456 (0x558Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_457 (0x153Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_458 (0x26E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_459 (0x1DC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_460 (0x307Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_461 (0x2537u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_462 (0x3AA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_463 (0x6D86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_464 (0x67A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_465 (0x52F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_466 (0x09F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_467 (0x6DC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_468 (0x5E1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_469 (0x7A86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_470 (0x2D47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_471 (0x09EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_472 (0x1D27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_473 (0x68EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_474 (0x29D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_475 (0x66B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_476 (0x1537u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_477 (0x6F05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_478 (0x4CF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_479 (0x1D3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_480 (0x15D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_481 (0x6173u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_482 (0x04BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_483 (0x4B47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_484 (0x07B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_485 (0x3AD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_486 (0x638Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_487 (0x3953u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_488 (0x7135u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_489 (0x585Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_490 (0x43CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_491 (0x2B74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_492 (0x6569u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_493 (0x4C6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_494 (0x0737u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_495 (0x7916u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_496 (0x28BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_497 (0x2557u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_498 (0x609Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_499 (0x691Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_500 (0x31E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_501 (0x3A53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_502 (0x7658u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_503 (0x5C59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_504 (0x6725u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_505 (0x7A38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_506 (0x3356u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_507 (0x6696u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_508 (0x52ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_509 (0x4F49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_510 (0x2799u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_511 (0x2E17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_512 (0x2AD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_513 (0x524Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_514 (0x7561u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_515 (0x4D8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_516 (0x0CF6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_517 (0x39B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_518 (0x45BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_519 (0x5665u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_520 (0x70E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_521 (0x2EB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_522 (0x06D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_523 (0x5E45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_524 (0x72D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_525 (0x129Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_526 (0x21BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_527 (0x0D5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_528 (0x0F3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_529 (0x131Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_530 (0x539Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_531 (0x7D06u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_532 (0x47D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_533 (0x25D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_534 (0x13F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_535 (0x14F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_536 (0x2759u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_537 (0x7994u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_538 (0x45B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_539 (0x38C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_540 (0x52DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_541 (0x29ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_542 (0x6B29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_543 (0x5476u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_544 (0x467Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_545 (0x49BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_546 (0x40EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_547 (0x6B8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_548 (0x28EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_549 (0x11F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_550 (0x5C1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_551 (0x7998u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_552 (0x7887u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_553 (0x30BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_554 (0x0DF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_555 (0x3257u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_556 (0x6D2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_557 (0x670Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_558 (0x04FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_559 (0x6E25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_560 (0x52B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_561 (0x1F34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_562 (0x1AB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_563 (0x4E56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_564 (0x53D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_565 (0x70ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_566 (0x3B4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_567 (0x5176u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_568 (0x4DF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_569 (0x29AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_570 (0x3955u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_571 (0x7A1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_572 (0x1C6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_573 (0x053Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_574 (0x499Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_575 (0x23B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_576 (0x6A35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_577 (0x4F16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_578 (0x0BC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_579 (0x13ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_580 (0x5437u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_581 (0x51DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_582 (0x27E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_583 (0x3D29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_584 (0x6137u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_585 (0x64CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_586 (0x4C8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_587 (0x45F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_588 (0x07D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_589 (0x551Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_590 (0x3AD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_591 (0x5EC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_592 (0x63B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_593 (0x4B2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_594 (0x1E1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_595 (0x53A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_596 (0x34DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_597 (0x11FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_598 (0x3A95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_599 (0x6D51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_600 (0x56C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_601 (0x64D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_602 (0x633Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_603 (0x2B1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_604 (0x255Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_605 (0x764Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_606 (0x0B6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_607 (0x63ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_608 (0x7F02u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_609 (0x0F35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_610 (0x1B2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_611 (0x0ABEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_612 (0x4CCBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_613 (0x7554u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_614 (0x5639u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_615 (0x6758u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_616 (0x30F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_617 (0x0FB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_618 (0x30EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_619 (0x4C5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_620 (0x61D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_621 (0x5C9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_622 (0x7D11u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_623 (0x6F81u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_624 (0x3A59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_625 (0x383Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_626 (0x3B4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_627 (0x3AB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_628 (0x1CE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_629 (0x372Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_630 (0x3745u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_631 (0x7938u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_632 (0x55D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_633 (0x21F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_634 (0x1B65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_635 (0x4D6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_636 (0x54B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_637 (0x7136u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_638 (0x5DA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_639 (0x52BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_640 (0x3D92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_641 (0x20FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_642 (0x43CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_643 (0x4C75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_644 (0x2B33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_645 (0x0EADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_646 (0x1ED1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_647 (0x34BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_648 (0x4DE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_649 (0x13F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_650 (0x6D43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_651 (0x60F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_652 (0x519Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_653 (0x0DBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_654 (0x43DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_655 (0x03AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_656 (0x6E61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_657 (0x64B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_658 (0x2A9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_659 (0x3659u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_660 (0x6CD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_661 (0x17B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_662 (0x0E2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_663 (0x6179u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_664 (0x14FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_665 (0x1D5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_666 (0x5CC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_667 (0x4EA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_668 (0x097Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_669 (0x33E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_670 (0x68F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_671 (0x5B25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_672 (0x6473u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_673 (0x5479u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_674 (0x2771u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_675 (0x0A7Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_676 (0x61AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_677 (0x3D4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_678 (0x13CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_679 (0x0C5Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_680 (0x35E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_681 (0x19F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_682 (0x7A54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_683 (0x760Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_684 (0x1FA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_685 (0x1F64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_686 (0x36B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_687 (0x0A9Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_688 (0x54E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_689 (0x6CC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_690 (0x3792u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_691 (0x4766u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_692 (0x69B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_693 (0x48B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_694 (0x3719u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_695 (0x3F06u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_696 (0x715Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_697 (0x12DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_698 (0x721Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_699 (0x1D65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_700 (0x2736u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_701 (0x29D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_702 (0x1CDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_703 (0x1D1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_704 (0x29D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_705 (0x5D64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_706 (0x30FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_707 (0x63B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_708 (0x2FC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_709 (0x1F29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_710 (0x4D65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_711 (0x7AC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_712 (0x0DDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_713 (0x38ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_714 (0x56A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_715 (0x1CE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_716 (0x0DE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_717 (0x5553u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_718 (0x7E24u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_719 (0x3B32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_720 (0x7C62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_721 (0x61C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_722 (0x3D8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_723 (0x4FC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_724 (0x61EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_725 (0x3B86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_726 (0x19BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_727 (0x43B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_728 (0x1D8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_729 (0x4E35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_730 (0x7C23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_731 (0x734Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_732 (0x3327u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_733 (0x6716u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_734 (0x707Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_735 (0x3897u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_736 (0x4F43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_737 (0x3723u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_738 (0x5A36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_739 (0x333Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_740 (0x6C99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_741 (0x15ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_742 (0x1DCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_743 (0x538Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_744 (0x6C5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_745 (0x53D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_746 (0x5E46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_747 (0x5E0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_748 (0x233Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_749 (0x686Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_750 (0x1B3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_751 (0x691Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_752 (0x50BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_753 (0x46D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_754 (0x2DB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_755 (0x154Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_756 (0x6BC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_757 (0x0FB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_758 (0x3DC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_759 (0x44D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_760 (0x3DE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_761 (0x7463u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_762 (0x39CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_763 (0x643Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_764 (0x4AB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_765 (0x495Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_766 (0x5CD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_767 (0x6C65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_768 (0x34B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_769 (0x781Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_770 (0x67C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_771 (0x7259u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_772 (0x5C93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_773 (0x1AB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_774 (0x2DD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_775 (0x076Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_776 (0x19E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_777 (0x47D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_778 (0x5672u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_779 (0x476Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_780 (0x15B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_781 (0x1B69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_782 (0x53B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_783 (0x29E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_784 (0x5B62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_785 (0x316Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_786 (0x5897u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_787 (0x6ACAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_788 (0x235Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_789 (0x1F0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_790 (0x618Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_791 (0x0DADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_792 (0x7A94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_793 (0x78D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_794 (0x7949u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_795 (0x5B51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_796 (0x1B2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_797 (0x116Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_798 (0x386Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_799 (0x5BE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_800 (0x4EC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_801 (0x505Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_802 (0x4675u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_803 (0x305Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_804 (0x7E90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_805 (0x5969u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_806 (0x7AA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_807 (0x4BC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_808 (0x2379u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_809 (0x23B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_810 (0x7CC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_811 (0x715Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_812 (0x2B53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_813 (0x1579u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_814 (0x4657u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_815 (0x6AC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_816 (0x4E1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_817 (0x7724u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_818 (0x52CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_819 (0x495Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_820 (0x1B5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_821 (0x682Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_822 (0x32DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_823 (0x133Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_824 (0x0EF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_825 (0x5B89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_826 (0x0FA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_827 (0x4CD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_828 (0x479Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_829 (0x6363u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_830 (0x4D74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_831 (0x18EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_832 (0x748Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_833 (0x3A3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_834 (0x5D49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_835 (0x198Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_836 (0x762Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_837 (0x0BD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_838 (0x2F34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_839 (0x75D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_840 (0x1D78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_841 (0x62A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_842 (0x4F68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_843 (0x5791u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_844 (0x39D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_845 (0x285Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_846 (0x6E86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_847 (0x05EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_848 (0x59C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_849 (0x5BC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_850 (0x740Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_851 (0x0E76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_852 (0x157Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_853 (0x6B0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_854 (0x6A47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_855 (0x0E3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_856 (0x7638u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_857 (0x24E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_858 (0x0D6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_859 (0x5517u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_860 (0x30D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_861 (0x1D59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_862 (0x57E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_863 (0x745Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_864 (0x43D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_865 (0x3B58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_866 (0x730Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_867 (0x75C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_868 (0x278Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_869 (0x54ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_870 (0x0AEDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_871 (0x46CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_872 (0x56D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_873 (0x5CB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_874 (0x317Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_875 (0x73C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_876 (0x2BB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_877 (0x079Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_878 (0x31CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_879 (0x47CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_880 (0x2AB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_881 (0x52E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_882 (0x5CA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_883 (0x16F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_884 (0x5713u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_885 (0x6B86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_886 (0x5A93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_887 (0x66E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_888 (0x5257u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_889 (0x3B34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_890 (0x0CB7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_891 (0x6335u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_892 (0x1D93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_893 (0x38B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_894 (0x4F8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_895 (0x2E2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_896 (0x7A51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_897 (0x56AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_898 (0x1BD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_899 (0x1AF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_900 (0x1975u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_901 (0x2CB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_902 (0x11BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_903 (0x681Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_904 (0x5E23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_905 (0x7AB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_906 (0x7534u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_907 (0x3DC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_908 (0x655Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_909 (0x4B1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_910 (0x70CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_911 (0x1E66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_912 (0x556Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_913 (0x5B07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_914 (0x390Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_915 (0x4DCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_916 (0x596Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_917 (0x1AECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_918 (0x41DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_919 (0x5617u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_920 (0x5C4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_921 (0x4F23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_922 (0x662Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_923 (0x24FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_924 (0x0E4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_925 (0x62F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_926 (0x35CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_927 (0x68E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_928 (0x7D81u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_929 (0x58E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_930 (0x1C97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_931 (0x25B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_932 (0x0AD7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_933 (0x39C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_934 (0x3C27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_935 (0x28F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_936 (0x175Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_937 (0x39A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_938 (0x2375u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_939 (0x3699u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_940 (0x3D43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_941 (0x70B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_942 (0x34E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_943 (0x4FC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_944 (0x03FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_945 (0x5AACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_946 (0x46EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_947 (0x065Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_948 (0x49CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_949 (0x64C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_950 (0x6393u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_951 (0x392Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_952 (0x16DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_953 (0x0BB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_954 (0x591Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_955 (0x4C6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_956 (0x4C7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_957 (0x1E99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_958 (0x14E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_959 (0x3479u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_960 (0x5CB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_961 (0x0ECBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_962 (0x748Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_963 (0x23F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_964 (0x5B68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_965 (0x6CD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_966 (0x4B93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_967 (0x712Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_968 (0x19DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_969 (0x4C76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_970 (0x6356u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_971 (0x41F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_972 (0x30FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_973 (0x6B4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_974 (0x55D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_975 (0x2C2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_976 (0x5A9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_977 (0x5CD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_978 (0x23E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_979 (0x6C17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_980 (0x5C8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_981 (0x7934u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_982 (0x526Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_983 (0x1B59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_984 (0x694Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_985 (0x1E55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_986 (0x163Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_987 (0x6F41u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_988 (0x06DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_989 (0x5D94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_990 (0x2A9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_991 (0x6636u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_992 (0x5C6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_993 (0x4AB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_994 (0x0DCBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_995 (0x7A25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_996 (0x3E52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_997 (0x7361u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_998 (0x4576u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_999 (0x25E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1000 (0x60CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1001 (0x5B31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1002 (0x16AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1003 (0x1AC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1004 (0x3AA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1005 (0x6C95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1006 (0x7159u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1007 (0x7C4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1008 (0x4733u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1009 (0x4567u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1010 (0x38B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1011 (0x24F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1012 (0x724Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1013 (0x6AB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1014 (0x5A69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1015 (0x72AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1016 (0x7643u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1017 (0x2C6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1018 (0x25C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1019 (0x3A87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1020 (0x225Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1021 (0x6D16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1022 (0x35ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1023 (0x3E91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1024 (0x789Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1025 (0x7B0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1026 (0x12F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1027 (0x34F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1028 (0x7C86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1029 (0x56E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1030 (0x569Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1031 (0x3AC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1032 (0x3339u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1033 (0x1957u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1034 (0x5563u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1035 (0x6A71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1036 (0x55B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1037 (0x1DD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1038 (0x499Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1039 (0x3359u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1040 (0x2AD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1041 (0x592Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1042 (0x5E4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1043 (0x0F8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1044 (0x6D49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1045 (0x6B58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1046 (0x34D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1047 (0x16F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1048 (0x2D6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1049 (0x239Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1050 (0x16D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1051 (0x58BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1052 (0x44FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1053 (0x359Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1054 (0x6D91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1055 (0x4D2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1056 (0x1E4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1057 (0x33B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1058 (0x1CBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1059 (0x7278u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1060 (0x3B29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1061 (0x7447u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1062 (0x4E99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1063 (0x78E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1064 (0x58F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1065 (0x750Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1066 (0x7E09u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1067 (0x14CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1068 (0x1DB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1069 (0x615Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1070 (0x3B8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1071 (0x58F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1072 (0x2AB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1073 (0x6B25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1074 (0x0C77u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1075 (0x5972u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1076 (0x13AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1077 (0x12F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1078 (0x38ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1079 (0x5CD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1080 (0x26CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1081 (0x2ECAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1082 (0x37C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1083 (0x5A3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1084 (0x38E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1085 (0x4F19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1086 (0x2795u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1087 (0x768Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1088 (0x393Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1089 (0x417Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1090 (0x5A66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1091 (0x35B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1092 (0x65D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1093 (0x6956u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1094 (0x2F45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1095 (0x4ED2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1096 (0x586Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1097 (0x6371u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1098 (0x52A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1099 (0x27D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1100 (0x5D16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1101 (0x36B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1102 (0x5A17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1103 (0x295Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1104 (0x13ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1105 (0x0ED3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1106 (0x5B26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1107 (0x61DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1108 (0x3C56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1109 (0x660Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1110 (0x6365u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1111 (0x5A0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1112 (0x3743u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1113 (0x06F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1114 (0x4CAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1115 (0x5974u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1116 (0x17E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1117 (0x1A67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1118 (0x7C49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1119 (0x14D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1120 (0x2B17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1121 (0x741Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1122 (0x5745u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1123 (0x7C1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1124 (0x2B2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1125 (0x6C1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1126 (0x35CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1127 (0x05F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1128 (0x2C9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1129 (0x71A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1130 (0x123Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1131 (0x069Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1132 (0x136Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1133 (0x6857u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1134 (0x4E0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1135 (0x193Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1136 (0x15F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1137 (0x127Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1138 (0x668Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1139 (0x34ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1140 (0x7AA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1141 (0x3E25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1142 (0x3365u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1143 (0x4C5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1144 (0x2E1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1145 (0x2B55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1146 (0x64EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1147 (0x36D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1148 (0x70E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1149 (0x3794u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1150 (0x5167u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1151 (0x1A6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1152 (0x6A66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1153 (0x311Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1154 (0x62F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1155 (0x6A6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1156 (0x13BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1157 (0x274Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1158 (0x6AA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1159 (0x22F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1160 (0x2755u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1161 (0x5E26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1162 (0x726Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1163 (0x5AC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1164 (0x51D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1165 (0x04DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1166 (0x4DA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1167 (0x49DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1168 (0x7439u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1169 (0x645Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1170 (0x6C96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1171 (0x236Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1172 (0x2AADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1173 (0x5BA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1174 (0x2673u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1175 (0x41EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1176 (0x18E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1177 (0x705Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1178 (0x1C3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1179 (0x7607u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1180 (0x0E97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1181 (0x4A9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1182 (0x1759u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1183 (0x3A47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1184 (0x5A27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1185 (0x4A6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1186 (0x6267u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1187 (0x4B59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1188 (0x2ACBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1189 (0x16CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1190 (0x6CF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1191 (0x7D42u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1192 (0x432Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1193 (0x25F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1194 (0x546Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1195 (0x69E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1196 (0x7C91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1197 (0x232Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1198 (0x2337u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1199 (0x6E1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1200 (0x5E85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1201 (0x1A73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1202 (0x29F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1203 (0x5738u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1204 (0x1DCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1205 (0x21EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1206 (0x3B0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1207 (0x25EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1208 (0x0DB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1209 (0x7543u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1210 (0x4735u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1211 (0x11EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1212 (0x458Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1213 (0x6C2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1214 (0x15B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1215 (0x3C3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1216 (0x5C5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1217 (0x53A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1218 (0x635Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1219 (0x638Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1220 (0x70AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1221 (0x1DD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1222 (0x34BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1223 (0x491Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1224 (0x0DD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1225 (0x2BC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1226 (0x6536u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1227 (0x63D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1228 (0x75A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1229 (0x1357u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1230 (0x4F98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1231 (0x2FC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1232 (0x139Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1233 (0x64ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1234 (0x13CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1235 (0x332Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1236 (0x6663u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1237 (0x4FC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1238 (0x65A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1239 (0x67C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1240 (0x487Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1241 (0x6B0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1242 (0x516Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1243 (0x0FC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1244 (0x3E46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1245 (0x627Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1246 (0x4A5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1247 (0x2DD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1248 (0x6A65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1249 (0x7760u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1250 (0x7750u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1251 (0x5879u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1252 (0x3D64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1253 (0x06F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1254 (0x4787u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1255 (0x1CF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1256 (0x70E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1257 (0x41B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1258 (0x12BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1259 (0x146Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1260 (0x5497u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1261 (0x633Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1262 (0x48F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1263 (0x1BC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1264 (0x545Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1265 (0x616Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1266 (0x51BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1267 (0x728Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1268 (0x3965u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1269 (0x47A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1270 (0x74CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1271 (0x0CBEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1272 (0x3C6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1273 (0x50EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1274 (0x45F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1275 (0x30DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1276 (0x6DA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1277 (0x68ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1278 (0x0CFCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1279 (0x273Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1280 (0x51B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1281 (0x1B4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1282 (0x35F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1283 (0x0D57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1284 (0x02EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1285 (0x4A67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1286 (0x457Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1287 (0x54E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1288 (0x2AF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1289 (0x746Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1290 (0x6A74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1291 (0x099Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1292 (0x654Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1293 (0x3C5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1294 (0x18BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1295 (0x617Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1296 (0x2E5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1297 (0x6E68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1298 (0x713Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1299 (0x26F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1300 (0x6257u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1301 (0x786Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1302 (0x16D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1303 (0x1C67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1304 (0x64CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1305 (0x62B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1306 (0x47C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1307 (0x78A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1308 (0x2ED8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1309 (0x3B07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1310 (0x5B1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1311 (0x1E47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1312 (0x39B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1313 (0x30E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1314 (0x41EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1315 (0x5547u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1316 (0x4B4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1317 (0x2E1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1318 (0x5A3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1319 (0x7558u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1320 (0x32F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1321 (0x4727u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1322 (0x3ACCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1323 (0x3655u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1324 (0x1F49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1325 (0x3B1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1326 (0x6077u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1327 (0x4EB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1328 (0x056Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1329 (0x7C58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1330 (0x45D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1331 (0x3FA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1332 (0x63D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1333 (0x76C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1334 (0x4D95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1335 (0x370Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1336 (0x1F8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1337 (0x4CDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1338 (0x3539u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1339 (0x24CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1340 (0x1D99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1341 (0x451Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1342 (0x15B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1343 (0x5CC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1344 (0x3CC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1345 (0x6C56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1346 (0x04F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1347 (0x7D84u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1348 (0x25BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1349 (0x2CD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1350 (0x391Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1351 (0x075Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1352 (0x67A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1353 (0x195Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1354 (0x478Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1355 (0x47E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1356 (0x52C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1357 (0x18BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1358 (0x3473u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1359 (0x798Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1360 (0x3378u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1361 (0x72D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1362 (0x7163u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1363 (0x18DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1364 (0x22FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1365 (0x2BCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1366 (0x0E6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1367 (0x2CF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1368 (0x5D4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1369 (0x3527u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1370 (0x3353u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1371 (0x1CCEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1372 (0x4BD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1373 (0x1E8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1374 (0x7D24u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1375 (0x4E47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1376 (0x5955u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1377 (0x72A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1378 (0x1E33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1379 (0x5AD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1380 (0x247Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1381 (0x67E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1382 (0x4BA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1383 (0x594Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1384 (0x454Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1385 (0x58EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1386 (0x4DD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1387 (0x7364u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1388 (0x0B3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1389 (0x1E53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1390 (0x5EC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1391 (0x31F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1392 (0x7495u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1393 (0x439Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1394 (0x344Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1395 (0x5A1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1396 (0x3963u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1397 (0x46ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1398 (0x1DAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1399 (0x326Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1400 (0x522Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1401 (0x73C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1402 (0x1DB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1403 (0x14F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1404 (0x26F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1405 (0x32D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1406 (0x6B15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1407 (0x19AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1408 (0x0D5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1409 (0x7899u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1410 (0x5587u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1411 (0x674Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1412 (0x2C73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1413 (0x2B1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1414 (0x12AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1415 (0x78B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1416 (0x3731u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1417 (0x4D35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1418 (0x23D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1419 (0x4B65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1420 (0x29F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1421 (0x7394u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1422 (0x65D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1423 (0x386Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1424 (0x6C0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1425 (0x6C4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1426 (0x2BA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1427 (0x2F46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1428 (0x3D26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1429 (0x7A15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1430 (0x7398u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1431 (0x73C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1432 (0x32DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1433 (0x21F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1434 (0x162Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1435 (0x1E2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1436 (0x22DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1437 (0x593Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1438 (0x173Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1439 (0x66D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1440 (0x217Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1441 (0x44EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1442 (0x3617u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1443 (0x09DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1444 (0x51CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1445 (0x591Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1446 (0x45ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1447 (0x19ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1448 (0x7649u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1449 (0x3653u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1450 (0x6574u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1451 (0x7C16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1452 (0x7932u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1453 (0x364Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1454 (0x790Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1455 (0x323Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1456 (0x586Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1457 (0x1B35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1458 (0x78E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1459 (0x6F06u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1460 (0x0BF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1461 (0x14DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1462 (0x5959u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1463 (0x3CAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1464 (0x5734u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1465 (0x46E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1466 (0x2ABAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1467 (0x0AEBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1468 (0x46CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1469 (0x6273u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1470 (0x32AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1471 (0x4E93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1472 (0x369Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1473 (0x4DB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1474 (0x23F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1475 (0x3AB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1476 (0x744Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1477 (0x26D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1478 (0x5953u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1479 (0x558Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1480 (0x5D45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1481 (0x2B35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1482 (0x32D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1483 (0x7943u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1484 (0x0AAFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1485 (0x2F91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1486 (0x68F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1487 (0x3D54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1488 (0x1BF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1489 (0x2AABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1490 (0x1C4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1491 (0x0D67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1492 (0x159Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1493 (0x1E59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1494 (0x6A2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1495 (0x18FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1496 (0x39C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1497 (0x6F28u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1498 (0x219Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1499 (0x1976u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1500 (0x24DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1501 (0x51ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1502 (0x7217u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1503 (0x5137u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1504 (0x2F43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1505 (0x14BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1506 (0x5297u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1507 (0x40FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1508 (0x2A79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1509 (0x117Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1510 (0x269Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1511 (0x66C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1512 (0x42EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1513 (0x153Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1514 (0x55A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1515 (0x7615u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1516 (0x43F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1517 (0x1BE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1518 (0x3C1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1519 (0x33D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1520 (0x607Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1521 (0x6475u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1522 (0x3C8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1523 (0x1799u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1524 (0x5EA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1525 (0x7459u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1526 (0x2735u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1527 (0x6476u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1528 (0x6C27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1529 (0x2B1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1530 (0x61BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1531 (0x3B16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1532 (0x2AB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1533 (0x644Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1534 (0x2ED1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1535 (0x1F68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1536 (0x1557u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1537 (0x3D07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1538 (0x1A5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1539 (0x55E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1540 (0x3995u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1541 (0x5E70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1542 (0x71D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1543 (0x3E0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1544 (0x2F07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1545 (0x163Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1546 (0x4B33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1547 (0x3D85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1548 (0x297Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1549 (0x0EDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1550 (0x4A2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1551 (0x5E43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1552 (0x4F32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1553 (0x1AB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1554 (0x64B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1555 (0x4EC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1556 (0x6E19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1557 (0x42BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1558 (0x3B92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1559 (0x5A56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1560 (0x6587u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1561 (0x66A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1562 (0x19B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1563 (0x21D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1564 (0x4376u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1565 (0x32A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1566 (0x7951u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1567 (0x1B2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1568 (0x5754u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1569 (0x0D8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1570 (0x1D3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1571 (0x3E86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1572 (0x43CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1573 (0x1739u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1574 (0x7985u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1575 (0x7472u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1576 (0x196Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1577 (0x2DE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1578 (0x6A78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1579 (0x38BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1580 (0x1F51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1581 (0x0F6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1582 (0x70B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1583 (0x34D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1584 (0x64E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1585 (0x352Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1586 (0x6764u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1587 (0x3555u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1588 (0x378Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1589 (0x1D35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1590 (0x515Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1591 (0x292Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1592 (0x4C3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1593 (0x1733u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1594 (0x5BA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1595 (0x59E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1596 (0x7313u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1597 (0x48BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1598 (0x7075u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1599 (0x11BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1600 (0x5D43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1601 (0x3876u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1602 (0x1B6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1603 (0x1BCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1604 (0x18F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1605 (0x559Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1606 (0x19BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1607 (0x382Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1608 (0x3751u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1609 (0x5768u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1610 (0x1BC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1611 (0x7E60u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1612 (0x27C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1613 (0x33C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1614 (0x2B87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1615 (0x2E74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1616 (0x7B05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1617 (0x59B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1618 (0x465Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1619 (0x3D15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1620 (0x0F8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1621 (0x38D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1622 (0x659Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1623 (0x295Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1624 (0x265Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1625 (0x7626u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1626 (0x27B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1627 (0x55B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1628 (0x64E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1629 (0x315Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1630 (0x299Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1631 (0x6C59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1632 (0x169Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1633 (0x3639u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1634 (0x0F6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1635 (0x4ACDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1636 (0x3D1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1637 (0x2397u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1638 (0x664Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1639 (0x5731u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1640 (0x2E66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1641 (0x1BE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1642 (0x5B2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1643 (0x27B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1644 (0x4BC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1645 (0x433Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1646 (0x2F83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1647 (0x1657u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1648 (0x2B65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1649 (0x2BD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1650 (0x561Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1651 (0x4375u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1652 (0x1AAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1653 (0x39F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1654 (0x668Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1655 (0x4C9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1656 (0x6EA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1657 (0x1667u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1658 (0x0AEEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1659 (0x075Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1660 (0x2A2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1661 (0x643Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1662 (0x564Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1663 (0x33CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1664 (0x63A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1665 (0x56B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1666 (0x53CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1667 (0x7299u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1668 (0x0DE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1669 (0x47A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1670 (0x632Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1671 (0x7307u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1672 (0x3917u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1673 (0x719Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1674 (0x3B31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1675 (0x658Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1676 (0x3C59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1677 (0x744Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1678 (0x63CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1679 (0x0677u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1680 (0x74CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1681 (0x1B39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1682 (0x4BCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1683 (0x45D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1684 (0x2CABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1685 (0x456Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1686 (0x0F9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1687 (0x1CB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1688 (0x327Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1689 (0x0E6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1690 (0x23DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1691 (0x55E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1692 (0x69D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1693 (0x5B16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1694 (0x78B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1695 (0x69CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1696 (0x385Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1697 (0x4937u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1698 (0x6CA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1699 (0x263Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1700 (0x709Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1701 (0x513Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1702 (0x496Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1703 (0x6E0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1704 (0x57C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1705 (0x3F41u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1706 (0x2B3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1707 (0x7A0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1708 (0x7931u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1709 (0x63C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1710 (0x783Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1711 (0x5B70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1712 (0x65B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1713 (0x49B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1714 (0x65A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1715 (0x6996u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1716 (0x2F86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1717 (0x574Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1718 (0x423Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1719 (0x564Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1720 (0x3636u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1721 (0x0D1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1722 (0x782Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1723 (0x2AA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1724 (0x5D91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1725 (0x1277u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1726 (0x265Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1727 (0x0F1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1728 (0x606Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1729 (0x5C9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1730 (0x5353u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1731 (0x191Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1732 (0x330Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1733 (0x5E25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1734 (0x08FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1735 (0x5175u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1736 (0x6CAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1737 (0x5333u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1738 (0x1ACBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1739 (0x6672u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1740 (0x39D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1741 (0x3BB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1742 (0x7A52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1743 (0x5794u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1744 (0x5D23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1745 (0x6D1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1746 (0x72E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1747 (0x5F82u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1748 (0x650Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1749 (0x0D9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1750 (0x1B3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1751 (0x36D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1752 (0x0B75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1753 (0x583Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1754 (0x2EE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1755 (0x41DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1756 (0x159Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1757 (0x6F44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1758 (0x7B30u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1759 (0x46BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1760 (0x0B6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1761 (0x3CD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1762 (0x06DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1763 (0x69B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1764 (0x216Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1765 (0x3F90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1766 (0x166Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1767 (0x1D96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1768 (0x32E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1769 (0x32D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1770 (0x17A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1771 (0x5A8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1772 (0x2373u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1773 (0x2DC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1774 (0x51F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1775 (0x6E91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1776 (0x4F92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1777 (0x7325u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1778 (0x31B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1779 (0x495Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1780 (0x1ABAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1781 (0x75B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1782 (0x56C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1783 (0x26DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1784 (0x5387u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1785 (0x64E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1786 (0x11DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1787 (0x591Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1788 (0x23CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1789 (0x7358u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1790 (0x6317u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1791 (0x4F34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1792 (0x49B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1793 (0x27E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1794 (0x6593u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1795 (0x44EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1796 (0x6C1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1797 (0x26BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1798 (0x30EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1799 (0x276Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1800 (0x47C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1801 (0x5173u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1802 (0x07D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1803 (0x714Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1804 (0x3D8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1805 (0x0D4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1806 (0x6533u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1807 (0x2778u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1808 (0x1ECCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1809 (0x7A23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1810 (0x49F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1811 (0x3F0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1812 (0x1B1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1813 (0x0D76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1814 (0x24BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1815 (0x07CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1816 (0x2DCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1817 (0x7952u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1818 (0x5D0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1819 (0x55E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1820 (0x672Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1821 (0x549Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1822 (0x1B53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1823 (0x0DC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1824 (0x1E5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1825 (0x6B64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1826 (0x0DA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1827 (0x289Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1828 (0x7B42u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1829 (0x59E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1830 (0x07F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1831 (0x3CA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1832 (0x1F4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1833 (0x2DACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1834 (0x39D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1835 (0x0B3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1836 (0x751Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1837 (0x1C9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1838 (0x55A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1839 (0x7568u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1840 (0x46AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1841 (0x70D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1842 (0x5AA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1843 (0x3D68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1844 (0x570Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1845 (0x0BB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1846 (0x641Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1847 (0x3E58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1848 (0x62C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1849 (0x6B46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1850 (0x57D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1851 (0x7E30u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1852 (0x6789u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1853 (0x12F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1854 (0x12BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1855 (0x7654u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1856 (0x15A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1857 (0x2AECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1858 (0x6CACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1859 (0x236Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1860 (0x5F48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1861 (0x269Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1862 (0x6B26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1863 (0x578Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1864 (0x532Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1865 (0x18CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1866 (0x5B38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1867 (0x2AE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1868 (0x0977u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1869 (0x6A8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1870 (0x3A56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1871 (0x6947u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1872 (0x1A2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1873 (0x655Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1874 (0x3D52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1875 (0x2B4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1876 (0x26F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1877 (0x2E71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1878 (0x35D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1879 (0x1EB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1880 (0x1CB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1881 (0x171Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1882 (0x5DC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1883 (0x4D1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1884 (0x3A5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1885 (0x6D89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1886 (0x36D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1887 (0x3D89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1888 (0x0EBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1889 (0x4759u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1890 (0x7AC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1891 (0x4F29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1892 (0x2D2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1893 (0x2F31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1894 (0x3E13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1895 (0x62CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1896 (0x3E26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1897 (0x06BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1898 (0x662Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1899 (0x0EDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1900 (0x54CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1901 (0x0BDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1902 (0x11EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1903 (0x54D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1904 (0x51D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1905 (0x1F2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1906 (0x0BD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1907 (0x324Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1908 (0x4D53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1909 (0x4DE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1910 (0x3EC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1911 (0x34B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1912 (0x7564u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1913 (0x03F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1914 (0x155Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1915 (0x0D7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1916 (0x6547u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1917 (0x3D31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1918 (0x3C65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1919 (0x3395u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1920 (0x16ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1921 (0x66A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1922 (0x33B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1923 (0x7C92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1924 (0x4E17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1925 (0x745Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1926 (0x2BC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1927 (0x26B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1928 (0x5EA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1929 (0x3396u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1930 (0x0F27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1931 (0x4B53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1932 (0x3C2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1933 (0x349Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1934 (0x5378u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1935 (0x722Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1936 (0x2B6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1937 (0x6EB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1938 (0x6D64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1939 (0x2E72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1940 (0x4DE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1941 (0x3738u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1942 (0x4BAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1943 (0x7271u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1944 (0x3497u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1945 (0x4DC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1946 (0x2EB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1947 (0x7A2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1948 (0x0FCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1949 (0x3734u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1950 (0x748Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1951 (0x690Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1952 (0x6E83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1953 (0x7F08u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1954 (0x5276u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1955 (0x41BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1956 (0x43ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1957 (0x34D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1958 (0x7097u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1959 (0x237Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1960 (0x6745u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1961 (0x3B54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1962 (0x4E1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1963 (0x3D34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1964 (0x0E5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1965 (0x3AF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1966 (0x723Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1967 (0x671Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1968 (0x30F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1969 (0x5723u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1970 (0x6F18u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1971 (0x3E4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1972 (0x55A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1973 (0x08DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1974 (0x26CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1975 (0x1D5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1976 (0x2C97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1977 (0x3BA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1978 (0x7A46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1979 (0x44EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1980 (0x1DC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1981 (0x41FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1982 (0x5E94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1983 (0x76A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1984 (0x295Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1985 (0x629Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1986 (0x3E0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1987 (0x464Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1988 (0x2F51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1989 (0x6761u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1990 (0x0ACFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1991 (0x3D58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1992 (0x257Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1993 (0x44F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1994 (0x62EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1995 (0x4CB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1996 (0x659Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1997 (0x7A07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1998 (0x5C33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_1999 (0x2BA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2000 (0x703Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2001 (0x5D58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2002 (0x7139u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2003 (0x3656u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2004 (0x4EB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2005 (0x7E81u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2006 (0x33E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2007 (0x2CADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2008 (0x59CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2009 (0x1EB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2010 (0x3764u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2011 (0x23D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2012 (0x4537u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2013 (0x7651u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2014 (0x7591u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2015 (0x4E6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2016 (0x1679u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2017 (0x259Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2018 (0x389Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2019 (0x1FB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2020 (0x3F09u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2021 (0x227Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2022 (0x74C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2023 (0x70F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2024 (0x14DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2025 (0x61B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2026 (0x336Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2027 (0x619Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2028 (0x266Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2029 (0x4C2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2030 (0x6F22u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2031 (0x58E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2032 (0x26EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2033 (0x3E8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2034 (0x28DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2035 (0x72D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2036 (0x1F54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2037 (0x07ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2038 (0x0BCBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2039 (0x7709u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2040 (0x4A5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2041 (0x3CD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2042 (0x0F17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2043 (0x24EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2044 (0x3C4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2045 (0x0ED9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2046 (0x7865u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2047 (0x4477u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2048 (0x6738u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2049 (0x2E96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2050 (0x6A63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2051 (0x7D48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2052 (0x419Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2053 (0x58D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2054 (0x6EC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2055 (0x427Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2056 (0x52D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2057 (0x13D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2058 (0x5C78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2059 (0x63A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2060 (0x3E1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2061 (0x6B8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2062 (0x31DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2063 (0x6B32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2064 (0x74D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2065 (0x374Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2066 (0x6666u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2067 (0x4C97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2068 (0x269Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2069 (0x41CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2070 (0x1A9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2071 (0x4DB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2072 (0x31EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2073 (0x1E74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2074 (0x762Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2075 (0x70D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2076 (0x0B4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2077 (0x653Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2078 (0x7C31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2079 (0x4ED1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2080 (0x30F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2081 (0x11B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2082 (0x48DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2083 (0x0767u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2084 (0x125Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2085 (0x3CB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2086 (0x7586u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2087 (0x0FE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2088 (0x62AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2089 (0x3536u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2090 (0x7117u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2091 (0x6D15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2092 (0x0FD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2093 (0x3A1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2094 (0x5D1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2095 (0x0A7Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2096 (0x0A5Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2097 (0x4CCDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2098 (0x314Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2099 (0x3A9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2100 (0x670Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2101 (0x523Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2102 (0x58BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2103 (0x3157u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2104 (0x3770u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2105 (0x3972u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2106 (0x2ACDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2107 (0x71C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2108 (0x4F51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2109 (0x1A97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2110 (0x34CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2111 (0x622Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2112 (0x514Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2113 (0x1736u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2114 (0x23CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2115 (0x72B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2116 (0x7552u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2117 (0x1B1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2118 (0x6175u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2119 (0x3AE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2120 (0x32EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2121 (0x2727u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2122 (0x66C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2123 (0x4EC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2124 (0x16BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2125 (0x4717u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2126 (0x558Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2127 (0x7C98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2128 (0x734Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2129 (0x2EA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2130 (0x358Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2131 (0x54D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2132 (0x12EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2133 (0x7E50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2134 (0x523Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2135 (0x6BA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2136 (0x0CF3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2137 (0x78A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2138 (0x5716u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2139 (0x351Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2140 (0x157Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2141 (0x2997u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2142 (0x718Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2143 (0x7992u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2144 (0x5A9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2145 (0x2BB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2146 (0x455Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2147 (0x569Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2148 (0x3CA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2149 (0x2B2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2150 (0x6837u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2151 (0x58D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2152 (0x2E87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2153 (0x1FD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2154 (0x58ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2155 (0x786Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2156 (0x5F18u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2157 (0x5A8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2158 (0x4D9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2159 (0x453Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2160 (0x2F2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2161 (0x11CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2162 (0x0F4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2163 (0x48EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2164 (0x2EC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2165 (0x2B27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2166 (0x31DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2167 (0x66D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2168 (0x1E6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2169 (0x7CC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2170 (0x0AF6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2171 (0x52AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2172 (0x48FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2173 (0x2AC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2174 (0x69E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2175 (0x1C37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2176 (0x3ACAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2177 (0x174Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2178 (0x68B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2179 (0x17F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2180 (0x1C3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2181 (0x59A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2182 (0x2C57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2183 (0x5F14u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2184 (0x3EA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2185 (0x43E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2186 (0x4D39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2187 (0x32CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2188 (0x2597u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2189 (0x4F8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2190 (0x11F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2191 (0x15D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2192 (0x351Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2193 (0x4AB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2194 (0x7073u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2195 (0x331Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2196 (0x3A8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2197 (0x39B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2198 (0x341Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2199 (0x62F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2200 (0x43B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2201 (0x4DA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2202 (0x4ADAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2203 (0x546Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2204 (0x4FA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2205 (0x6647u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2206 (0x654Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2207 (0x17D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2208 (0x05FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2209 (0x4AAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2210 (0x7239u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2211 (0x0F74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2212 (0x02BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2213 (0x4E63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2214 (0x7076u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2215 (0x0EABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2216 (0x6C71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2217 (0x21B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2218 (0x49C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2219 (0x754Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2220 (0x58E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2221 (0x6867u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2222 (0x5E61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2223 (0x398Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2224 (0x7685u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2225 (0x366Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2226 (0x6A5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2227 (0x03EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2228 (0x5C4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2229 (0x171Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2230 (0x45D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2231 (0x649Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2232 (0x261Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2233 (0x137Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2234 (0x596Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2235 (0x3C72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2236 (0x4AD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2237 (0x2B9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2238 (0x56F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2239 (0x2DCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2240 (0x578Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2241 (0x3467u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2242 (0x36B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2243 (0x22DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2244 (0x339Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2245 (0x07DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2246 (0x07B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2247 (0x1597u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2248 (0x47B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2249 (0x6D19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2250 (0x2667u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2251 (0x6D25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2252 (0x09DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2253 (0x33A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2254 (0x1D9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2255 (0x6CD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2256 (0x1CA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2257 (0x43F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2258 (0x2F68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2259 (0x227Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2260 (0x4F46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2261 (0x3E92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2262 (0x698Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2263 (0x359Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2264 (0x6A9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2265 (0x7714u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2266 (0x6347u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2267 (0x16B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2268 (0x3DD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2269 (0x66F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2270 (0x6873u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2271 (0x589Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2272 (0x621Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2273 (0x61BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2274 (0x23ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2275 (0x1F32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2276 (0x6E0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2277 (0x78A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2278 (0x6E32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2279 (0x6AD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2280 (0x0DECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2281 (0x51B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2282 (0x2ED4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2283 (0x3837u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2284 (0x0FB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2285 (0x22BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2286 (0x2FD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2287 (0x695Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2288 (0x4E36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2289 (0x2E8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2290 (0x553Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2291 (0x4975u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2292 (0x25CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2293 (0x43D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2294 (0x6359u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2295 (0x6751u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2296 (0x0B6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2297 (0x729Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2298 (0x217Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2299 (0x598Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2300 (0x4E4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2301 (0x49ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2302 (0x746Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2303 (0x3D0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2304 (0x25B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2305 (0x1A9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2306 (0x21EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2307 (0x5E68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2308 (0x7A43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2309 (0x1A3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2310 (0x5D0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2311 (0x4795u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2312 (0x0F8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2313 (0x5C5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2314 (0x7523u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2315 (0x251Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2316 (0x7915u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2317 (0x493Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2318 (0x2ADAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2319 (0x3C4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2320 (0x7E11u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2321 (0x1D2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2322 (0x3A63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2323 (0x0F5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2324 (0x5C99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2325 (0x5AE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2326 (0x17A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2327 (0x0BB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2328 (0x07B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2329 (0x1F0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2330 (0x6E70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2331 (0x389Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2332 (0x631Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2333 (0x45CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2334 (0x4B9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2335 (0x2877u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2336 (0x32ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2337 (0x5C56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2338 (0x3E8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2339 (0x6DD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2340 (0x6927u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2341 (0x5C3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2342 (0x6BC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2343 (0x5D46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2344 (0x6E51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2345 (0x742Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2346 (0x536Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2347 (0x543Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2348 (0x3987u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2349 (0x2AF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2350 (0x3A17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2351 (0x62D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2352 (0x2B4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2353 (0x60AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2354 (0x19CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2355 (0x4CE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2356 (0x5467u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2357 (0x52CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2358 (0x5C6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2359 (0x561Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2360 (0x06FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2361 (0x616Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2362 (0x68D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2363 (0x3E45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2364 (0x274Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2365 (0x1E39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2366 (0x60FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2367 (0x728Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2368 (0x76C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2369 (0x3EA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2370 (0x178Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2371 (0x7964u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2372 (0x6DA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2373 (0x61D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2374 (0x14BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2375 (0x613Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2376 (0x58E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2377 (0x3AA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2378 (0x712Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2379 (0x44CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2380 (0x7171u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2381 (0x783Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2382 (0x6E85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2383 (0x44BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2384 (0x5DC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2385 (0x76A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2386 (0x6969u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2387 (0x328Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2388 (0x3372u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2389 (0x1E5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2390 (0x68E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2391 (0x615Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2392 (0x6CB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2393 (0x1BB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2394 (0x13C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2395 (0x2F52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2396 (0x24DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2397 (0x7A83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2398 (0x7CA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2399 (0x2A8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2400 (0x79A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2401 (0x0F53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2402 (0x58B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2403 (0x3C69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2404 (0x03DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2405 (0x648Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2406 (0x49B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2407 (0x4A3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2408 (0x7B60u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2409 (0x67A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2410 (0x25BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2411 (0x34CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2412 (0x192Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2413 (0x7C2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2414 (0x07CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2415 (0x4AEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2416 (0x78C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2417 (0x7853u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2418 (0x19B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2419 (0x686Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2420 (0x34E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2421 (0x1CADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2422 (0x7913u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2423 (0x2DB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2424 (0x32D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2425 (0x6AA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2426 (0x554Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2427 (0x74A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2428 (0x355Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2429 (0x5BC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2430 (0x199Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2431 (0x7147u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2432 (0x672Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2433 (0x4F52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2434 (0x5356u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2435 (0x7E44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2436 (0x2567u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2437 (0x447Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2438 (0x13A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2439 (0x744Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2440 (0x057Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2441 (0x2357u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2442 (0x5393u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2443 (0x614Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2444 (0x055Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2445 (0x7227u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2446 (0x57C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2447 (0x7961u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2448 (0x3A33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2449 (0x18AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2450 (0x658Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2451 (0x1F91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2452 (0x3BD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2453 (0x3F44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2454 (0x4D72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2455 (0x54D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2456 (0x2DE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2457 (0x4772u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2458 (0x26B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2459 (0x36C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2460 (0x1FC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2461 (0x05DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2462 (0x0BE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2463 (0x4AF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2464 (0x2B2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2465 (0x07E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2466 (0x245Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2467 (0x3D25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2468 (0x5EC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2469 (0x69D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2470 (0x174Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2471 (0x3563u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2472 (0x07EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2473 (0x32ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2474 (0x25D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2475 (0x35D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2476 (0x3275u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2477 (0x3647u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2478 (0x6E4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2479 (0x27D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2480 (0x6D70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2481 (0x6752u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2482 (0x7C52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2483 (0x343Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2484 (0x272Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2485 (0x7AE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2486 (0x1BA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2487 (0x51D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2488 (0x2EAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2489 (0x20FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2490 (0x2E65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2491 (0x4CC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2492 (0x2CF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2493 (0x66E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2494 (0x353Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2495 (0x2F15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2496 (0x3A96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2497 (0x24F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2498 (0x2A7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2499 (0x4277u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2500 (0x58D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2501 (0x1DC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2502 (0x4ACEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2503 (0x0377u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2504 (0x358Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2505 (0x4B8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2506 (0x6E15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2507 (0x0ECDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2508 (0x7C8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2509 (0x4CD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2510 (0x6699u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2511 (0x64F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2512 (0x75C4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2513 (0x665Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2514 (0x5A47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2515 (0x51DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2516 (0x7A45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2517 (0x6B07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2518 (0x312Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2519 (0x338Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2520 (0x17C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2521 (0x7A68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2522 (0x44FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2523 (0x532Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2524 (0x30DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2525 (0x5798u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2526 (0x31CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2527 (0x3A72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2528 (0x5DC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2529 (0x5CC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2530 (0x5770u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2531 (0x2765u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2532 (0x5D8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2533 (0x1AE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2534 (0x1B56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2535 (0x5339u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2536 (0x7925u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2537 (0x5947u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2538 (0x6AC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2539 (0x4679u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2540 (0x570Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2541 (0x66D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2542 (0x18F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2543 (0x652Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2544 (0x5758u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2545 (0x568Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2546 (0x692Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2547 (0x479Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2548 (0x1CE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2549 (0x2ADCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2550 (0x7748u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2551 (0x346Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2552 (0x754Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2553 (0x720Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2554 (0x1AE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2555 (0x14F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2556 (0x5A2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2557 (0x56A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2558 (0x2F0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2559 (0x2D1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2560 (0x0EE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2561 (0x11F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2562 (0x28F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2563 (0x22FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2564 (0x3F48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2565 (0x0E79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2566 (0x6DC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2567 (0x64D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2568 (0x7236u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2569 (0x4B3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2570 (0x7316u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2571 (0x36CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2572 (0x61F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2573 (0x439Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2574 (0x7991u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2575 (0x14EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2576 (0x65D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2577 (0x2A5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2578 (0x19DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2579 (0x55C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2580 (0x1BD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2581 (0x69C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2582 (0x6974u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2583 (0x6E89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2584 (0x561Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2585 (0x69F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2586 (0x43ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2587 (0x3D83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2588 (0x366Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2589 (0x47B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2590 (0x68CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2591 (0x7538u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2592 (0x6AB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2593 (0x3335u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2594 (0x56A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2595 (0x58D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2596 (0x74D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2597 (0x0FCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2598 (0x3C1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2599 (0x0B9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2600 (0x6E34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2601 (0x4CA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2602 (0x1B87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2603 (0x34F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2604 (0x1C3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2605 (0x60BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2606 (0x38D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2607 (0x4B66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2608 (0x345Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2609 (0x1771u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2610 (0x688Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2611 (0x3CCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2612 (0x6E54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2613 (0x6A99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2614 (0x58A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2615 (0x0F47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2616 (0x2CEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2617 (0x24BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2618 (0x2F58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2619 (0x1B36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2620 (0x66B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2621 (0x50E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2622 (0x0D97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2623 (0x5655u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2624 (0x1F4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2625 (0x1373u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2626 (0x590Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2627 (0x71A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2628 (0x2B63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2629 (0x784Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2630 (0x46D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2631 (0x39E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2632 (0x2D65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2633 (0x6A17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2634 (0x33E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2635 (0x342Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2636 (0x0A6Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2637 (0x2A76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2638 (0x4673u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2639 (0x5E34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2640 (0x5372u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2641 (0x2C3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2642 (0x0EEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2643 (0x5D70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2644 (0x4F4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2645 (0x361Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2646 (0x33AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2647 (0x3EB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2648 (0x0DCDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2649 (0x4E8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2650 (0x2F2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2651 (0x365Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2652 (0x5A4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2653 (0x5A74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2654 (0x61ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2655 (0x1D72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2656 (0x7A26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2657 (0x53B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2658 (0x78F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2659 (0x23E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2660 (0x56D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2661 (0x2CDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2662 (0x3A1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2663 (0x159Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2664 (0x18FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2665 (0x7C94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2666 (0x25E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2667 (0x1BB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2668 (0x25F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2669 (0x3C17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2670 (0x2FB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2671 (0x65A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2672 (0x634Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2673 (0x0CEDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2674 (0x05D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2675 (0x6D62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2676 (0x65C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2677 (0x55E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2678 (0x199Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2679 (0x65C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2680 (0x6E8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2681 (0x42FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2682 (0x1DE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2683 (0x4C4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2684 (0x40F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2685 (0x7EC0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2686 (0x0B7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2687 (0x7A91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2688 (0x6D52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2689 (0x4E8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2690 (0x492Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2691 (0x3A93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2692 (0x35C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2693 (0x6CE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2694 (0x33D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2695 (0x0CF5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2696 (0x66CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2697 (0x716Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2698 (0x16E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2699 (0x42F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2700 (0x593Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2701 (0x3F18u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2702 (0x264Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2703 (0x1755u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2704 (0x6E64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2705 (0x55F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2706 (0x5B43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2707 (0x4AE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2708 (0x74E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2709 (0x4763u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2710 (0x59A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2711 (0x252Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2712 (0x6AACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2713 (0x4D96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2714 (0x2C7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2715 (0x4B2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2716 (0x21AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2717 (0x4E9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2718 (0x1D95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2719 (0x391Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2720 (0x7782u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2721 (0x2BC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2722 (0x23EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2723 (0x69A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2724 (0x354Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2725 (0x2EB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2726 (0x1D55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2727 (0x2DC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2728 (0x652Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2729 (0x5C4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2730 (0x6C55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2731 (0x167Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2732 (0x2BE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2733 (0x15AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2734 (0x6E52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2735 (0x7193u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2736 (0x25ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2737 (0x4D33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2738 (0x215Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2739 (0x613Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2740 (0x22DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2741 (0x6665u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2742 (0x7195u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2743 (0x7A0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2744 (0x7362u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2745 (0x6EA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2746 (0x0DCEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2747 (0x7661u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2748 (0x63D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2749 (0x4979u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2750 (0x25CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2751 (0x5F28u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2752 (0x5327u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2753 (0x0F72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2754 (0x0A3Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2755 (0x0CD7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2756 (0x48E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2757 (0x63CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2758 (0x2E99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2759 (0x117Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2760 (0x2A6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2761 (0x4CEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2762 (0x4BB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2763 (0x1ED2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2764 (0x2EC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2765 (0x385Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2766 (0x16B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2767 (0x32F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2768 (0x69CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2769 (0x433Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2770 (0x35B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2771 (0x1E87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2772 (0x6E45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2773 (0x61F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2774 (0x7525u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2775 (0x547Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2776 (0x63AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2777 (0x1717u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2778 (0x1C76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2779 (0x7F40u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2780 (0x3A69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2781 (0x4C3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2782 (0x497Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2783 (0x6F30u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2784 (0x29D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2785 (0x55D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2786 (0x5473u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2787 (0x70F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2788 (0x2C76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2789 (0x02F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2790 (0x3A71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2791 (0x0E3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2792 (0x03F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2793 (0x33B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2794 (0x542Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2795 (0x6E29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2796 (0x515Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2797 (0x11EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2798 (0x7255u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2799 (0x663Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2800 (0x0EE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2801 (0x7718u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2802 (0x50F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2803 (0x1B93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2804 (0x729Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2805 (0x5AB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2806 (0x319Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2807 (0x6C36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2808 (0x48BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2809 (0x3693u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2810 (0x2A57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2811 (0x5D0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2812 (0x1B55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2813 (0x790Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2814 (0x42BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2815 (0x13B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2816 (0x2CCEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2817 (0x23F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2818 (0x7B90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2819 (0x1937u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2820 (0x543Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2821 (0x5D92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2822 (0x256Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2823 (0x6F88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2824 (0x139Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2825 (0x5F0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2826 (0x7343u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2827 (0x096Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2828 (0x4F64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2829 (0x7235u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2830 (0x68D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2831 (0x7DC0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2832 (0x38E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2833 (0x3C93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2834 (0x385Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2835 (0x38E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2836 (0x19EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2837 (0x2C75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2838 (0x6CA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2839 (0x7338u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2840 (0x2CBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2841 (0x3935u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2842 (0x506Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2843 (0x5D85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2844 (0x15ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2845 (0x53B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2846 (0x731Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2847 (0x3559u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2848 (0x24F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2849 (0x68E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2850 (0x3B38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2851 (0x4BE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2852 (0x299Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2853 (0x59E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2854 (0x3B83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2855 (0x2AE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2856 (0x07D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2857 (0x52B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2858 (0x6635u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2859 (0x1F25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2860 (0x7391u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2861 (0x37C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2862 (0x06F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2863 (0x19F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2864 (0x4EB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2865 (0x1E72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2866 (0x4B4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2867 (0x31F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2868 (0x3978u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2869 (0x6A55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2870 (0x0EECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2871 (0x5E92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2872 (0x685Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2873 (0x2DA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2874 (0x3DA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2875 (0x439Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2876 (0x7570u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2877 (0x48CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2878 (0x595Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2879 (0x513Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2880 (0x0BABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2881 (0x61CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2882 (0x60F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2883 (0x50B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2884 (0x1B47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2885 (0x1B74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2886 (0x5BB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2887 (0x31F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2888 (0x13B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2889 (0x6F0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2890 (0x3167u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2891 (0x60FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2892 (0x7989u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2893 (0x3695u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2894 (0x4B3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2895 (0x7A4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2896 (0x5B52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2897 (0x4AD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2898 (0x68DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2899 (0x15E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2900 (0x572Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2901 (0x730Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2902 (0x369Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2903 (0x5A39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2904 (0x4ECAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2905 (0x5DE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2906 (0x7728u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2907 (0x6F48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2908 (0x077Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2909 (0x69E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2910 (0x2739u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2911 (0x19B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2912 (0x6497u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2913 (0x2C8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2914 (0x1637u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2915 (0x316Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2916 (0x3F24u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2917 (0x0B67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2918 (0x3AACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2919 (0x227Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2920 (0x15CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2921 (0x658Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2922 (0x3D16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2923 (0x6E92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2924 (0x2E0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2925 (0x494Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2926 (0x2B66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2927 (0x2C67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2928 (0x7896u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2929 (0x31E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2930 (0x4579u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2931 (0x1B8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2932 (0x2576u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2933 (0x3437u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2934 (0x3AE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2935 (0x73A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2936 (0x74AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2937 (0x5C35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2938 (0x0CE7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2939 (0x7619u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2940 (0x79B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2941 (0x1EA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2942 (0x623Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2943 (0x547Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2944 (0x12CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2945 (0x4CBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2946 (0x2AD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2947 (0x2CD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2948 (0x1DA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2949 (0x691Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2950 (0x7A85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2951 (0x4796u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2952 (0x66C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2953 (0x4D8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2954 (0x535Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2955 (0x3D4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2956 (0x23BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2957 (0x6E8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2958 (0x48BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2959 (0x5867u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2960 (0x41F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2961 (0x5CE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2962 (0x1CE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2963 (0x5CD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2964 (0x3A39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2965 (0x3678u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2966 (0x35D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2967 (0x5956u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2968 (0x7E82u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2969 (0x0FAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2970 (0x2ECCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2971 (0x63D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2972 (0x5B85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2973 (0x617Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2974 (0x7562u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2975 (0x2A67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2976 (0x368Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2977 (0x79E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2978 (0x4F45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2979 (0x3197u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2980 (0x5C53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2981 (0x0CBDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2982 (0x2E59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2983 (0x527Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2984 (0x770Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2985 (0x2A5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2986 (0x2BD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2987 (0x2E5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2988 (0x42BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2989 (0x76C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2990 (0x6BD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2991 (0x3E54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2992 (0x6F14u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2993 (0x6966u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2994 (0x2CE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2995 (0x664Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2996 (0x62DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2997 (0x31A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2998 (0x2F19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_2999 (0x6A33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3000 (0x2BCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3001 (0x4EC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3002 (0x6AE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3003 (0x2F0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3004 (0x2F38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3005 (0x493Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3006 (0x15D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3007 (0x1A7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3008 (0x3DA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3009 (0x5EC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3010 (0x12E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3011 (0x7629u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3012 (0x62B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3013 (0x6669u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3014 (0x7D0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3015 (0x187Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3016 (0x4BE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3017 (0x3399u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3018 (0x332Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3019 (0x0B9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3020 (0x68F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3021 (0x70CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3022 (0x69A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3023 (0x4AD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3024 (0x2CE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3025 (0x4367u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3026 (0x28F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3027 (0x3AE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3028 (0x19C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3029 (0x0DD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3030 (0x1787u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3031 (0x3BC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3032 (0x1DE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3033 (0x6599u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3034 (0x7079u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3035 (0x4DAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3036 (0x5317u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3037 (0x4F2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3038 (0x7D09u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3039 (0x18F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3040 (0x17A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3041 (0x706Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3042 (0x02DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3043 (0x3666u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3044 (0x64DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3045 (0x5635u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3046 (0x03DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3047 (0x1DE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3048 (0x7CC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3049 (0x48DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3050 (0x6CB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3051 (0x68CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3052 (0x2979u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3053 (0x52F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3054 (0x26C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3055 (0x2BD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3056 (0x5347u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3057 (0x372Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3058 (0x41EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3059 (0x0E9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3060 (0x0B5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3061 (0x07E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3062 (0x1B96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3063 (0x5A78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3064 (0x09EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3065 (0x45ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3066 (0x37A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3067 (0x0FD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3068 (0x45BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3069 (0x15F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3070 (0x515Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3071 (0x7272u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3072 (0x388Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3073 (0x1F2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3074 (0x287Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3075 (0x7A0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3076 (0x72CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3077 (0x1E2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3078 (0x25D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3079 (0x2D56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3080 (0x478Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3081 (0x1BAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3082 (0x79C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3083 (0x6A0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3084 (0x6A8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3085 (0x0BCEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3086 (0x67B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3087 (0x2D17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3088 (0x394Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3089 (0x70ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3090 (0x26ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3091 (0x1BACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3092 (0x49D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3093 (0x4CCEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3094 (0x5875u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3095 (0x7037u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3096 (0x543Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3097 (0x714Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3098 (0x7293u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3099 (0x6B34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3100 (0x7781u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3101 (0x4BB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3102 (0x4D47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3103 (0x71C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3104 (0x1C79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3105 (0x1477u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3106 (0x661Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3107 (0x26AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3108 (0x0ED6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3109 (0x68B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3110 (0x374Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3111 (0x5267u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3112 (0x636Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3113 (0x69C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3114 (0x7668u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3115 (0x417Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3116 (0x4E96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3117 (0x147Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3118 (0x378Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3119 (0x14BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3120 (0x17E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3121 (0x483Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3122 (0x63E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3123 (0x78D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3124 (0x7133u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3125 (0x0B8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3126 (0x7D41u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3127 (0x1D69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3128 (0x6AE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3129 (0x4676u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3130 (0x698Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3131 (0x790Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3132 (0x7169u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3133 (0x4573u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3134 (0x6457u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3135 (0x27B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3136 (0x09BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3137 (0x3A78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3138 (0x1D17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3139 (0x15C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3140 (0x1CECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3141 (0x6CCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3142 (0x656Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3143 (0x5E51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3144 (0x2D4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3145 (0x3457u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3146 (0x2975u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3147 (0x05FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3148 (0x5D26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3149 (0x7385u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3150 (0x51E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3151 (0x2679u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3152 (0x2E3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3153 (0x35B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3154 (0x3F0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3155 (0x095Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3156 (0x587Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3157 (0x7C70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3158 (0x463Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3159 (0x696Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3160 (0x3A74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3161 (0x03EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3162 (0x47A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3163 (0x61D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3164 (0x267Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3165 (0x791Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3166 (0x79A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3167 (0x7664u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3168 (0x6369u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3169 (0x36D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3170 (0x6955u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3171 (0x7705u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3172 (0x36CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3173 (0x07B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3174 (0x711Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3175 (0x5F09u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3176 (0x565Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3177 (0x71E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3178 (0x07BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3179 (0x6F03u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3180 (0x741Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3181 (0x5A55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3182 (0x16D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3183 (0x326Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3184 (0x7AA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3185 (0x1CD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3186 (0x453Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3187 (0x05CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3188 (0x097Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3189 (0x6639u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3190 (0x4A8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3191 (0x2D55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3192 (0x511Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3193 (0x175Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3194 (0x5EA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3195 (0x1F45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3196 (0x436Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3197 (0x66D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3198 (0x563Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3199 (0x0DD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3200 (0x4D93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3201 (0x5719u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3202 (0x3AE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3203 (0x1E3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3204 (0x335Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3205 (0x2BC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3206 (0x3E70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3207 (0x0F66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3208 (0x55CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3209 (0x70BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3210 (0x45DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3211 (0x2DB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3212 (0x338Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3213 (0x34A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3214 (0x06EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3215 (0x6D32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3216 (0x7C13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3217 (0x634Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3218 (0x0BE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3219 (0x4D5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3220 (0x4F94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3221 (0x716Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3222 (0x3971u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3223 (0x705Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3224 (0x5D61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3225 (0x7872u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3226 (0x723Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3227 (0x394Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3228 (0x3363u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3229 (0x6396u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3230 (0x34EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3231 (0x0D75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3232 (0x6723u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3233 (0x325Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3234 (0x58ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3235 (0x5D89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3236 (0x296Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3237 (0x0DDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3238 (0x1F58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3239 (0x7B06u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3240 (0x74C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3241 (0x0A77u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3242 (0x7B22u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3243 (0x352Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3244 (0x3A4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3245 (0x1EB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3246 (0x6C66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3247 (0x545Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3248 (0x54F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3249 (0x585Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3250 (0x5C2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3251 (0x2CECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3252 (0x7847u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3253 (0x036Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3254 (0x7698u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3255 (0x72C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3256 (0x1FC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3257 (0x4A73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3258 (0x7499u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3259 (0x78C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3260 (0x03EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3261 (0x4C1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3262 (0x31C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3263 (0x5A63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3264 (0x5C3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3265 (0x63E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3266 (0x7389u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3267 (0x5695u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3268 (0x6AF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3269 (0x23C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3270 (0x607Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3271 (0x66CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3272 (0x631Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3273 (0x057Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3274 (0x568Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3275 (0x2E33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3276 (0x3179u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3277 (0x5A99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3278 (0x7592u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3279 (0x6372u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3280 (0x794Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3281 (0x0F69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3282 (0x5C72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3283 (0x4A3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3284 (0x49F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3285 (0x7253u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3286 (0x507Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3287 (0x615Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3288 (0x4CABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3289 (0x5D98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3290 (0x1756u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3291 (0x53CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3292 (0x4EAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3293 (0x7383u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3294 (0x0D9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3295 (0x139Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3296 (0x5E07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3297 (0x0F56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3298 (0x34F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3299 (0x7B11u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3300 (0x3875u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3301 (0x0DE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3302 (0x04FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3303 (0x43B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3304 (0x3857u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3305 (0x1ECAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3306 (0x18DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3307 (0x1A1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3308 (0x13DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3309 (0x4FB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3310 (0x6B43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3311 (0x54B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3312 (0x5AB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3313 (0x3783u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3314 (0x4E3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3315 (0x3959u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3316 (0x0AF9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3317 (0x463Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3318 (0x7546u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3319 (0x4E27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3320 (0x730Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3321 (0x4B1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3322 (0x1753u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3323 (0x1F26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3324 (0x343Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3325 (0x7B21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3326 (0x43ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3327 (0x4EA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3328 (0x38F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3329 (0x1F70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3330 (0x0757u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3331 (0x4D3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3332 (0x279Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3333 (0x74B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3334 (0x1F98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3335 (0x1673u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3336 (0x313Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3337 (0x2D53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3338 (0x0BBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3339 (0x0B7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3340 (0x59D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3341 (0x69D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3342 (0x02FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3343 (0x5663u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3344 (0x0B76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3345 (0x165Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3346 (0x7F20u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3347 (0x647Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3348 (0x4756u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3349 (0x71B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3350 (0x7A8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3351 (0x2763u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3352 (0x2FA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3353 (0x353Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3354 (0x4BCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3355 (0x17E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3356 (0x3669u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3357 (0x067Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3358 (0x27CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3359 (0x651Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3360 (0x0EF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3361 (0x0BADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3362 (0x38A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3363 (0x7A2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3364 (0x6D4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3365 (0x49BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3366 (0x7334u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3367 (0x64ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3368 (0x709Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3369 (0x59C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3370 (0x768Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3371 (0x645Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3372 (0x31BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3373 (0x4778u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3374 (0x1AF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3375 (0x14AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3376 (0x4BF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3377 (0x3671u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3378 (0x0D3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3379 (0x3B2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3380 (0x7EA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3381 (0x5978u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3382 (0x7E88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3383 (0x3C2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3384 (0x2DD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3385 (0x361Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3386 (0x18BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3387 (0x429Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3388 (0x3C35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3389 (0x239Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3390 (0x6D8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3391 (0x1EA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3392 (0x23F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3393 (0x1F38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3394 (0x5C69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3395 (0x28FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3396 (0x4F07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3397 (0x7A16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3398 (0x535Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3399 (0x0FA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3400 (0x45DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3401 (0x5B29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3402 (0x0C7Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3403 (0x4F31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3404 (0x4736u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3405 (0x1EC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3406 (0x6B4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3407 (0x68A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3408 (0x798Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3409 (0x319Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3410 (0x25E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3411 (0x62B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3412 (0x237Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3413 (0x19A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3414 (0x13E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3415 (0x2EA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3416 (0x2F54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3417 (0x329Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3418 (0x69A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3419 (0x26F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3420 (0x443Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3421 (0x5569u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3422 (0x4C79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3423 (0x2E3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3424 (0x46BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3425 (0x263Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3426 (0x6527u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3427 (0x6B61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3428 (0x3297u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3429 (0x62D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3430 (0x3996u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3431 (0x138Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3432 (0x0D73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3433 (0x794Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3434 (0x69A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3435 (0x39AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3436 (0x2D96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3437 (0x4337u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3438 (0x78C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3439 (0x5D54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3440 (0x459Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3441 (0x2D27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3442 (0x5E0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3443 (0x1C57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3444 (0x6C4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3445 (0x32B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3446 (0x2676u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3447 (0x6999u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3448 (0x348Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3449 (0x5A71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3450 (0x516Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3451 (0x6395u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3452 (0x293Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3453 (0x26ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3454 (0x7A92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3455 (0x259Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3456 (0x1675u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3457 (0x7516u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3458 (0x229Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3459 (0x4EE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3460 (0x332Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3461 (0x3371u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3462 (0x5F03u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3463 (0x4A7Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3464 (0x0CEBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3465 (0x4CF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3466 (0x788Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3467 (0x44AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3468 (0x03DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3469 (0x5D19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3470 (0x3939u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3471 (0x551Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3472 (0x41DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3473 (0x493Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3474 (0x7839u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3475 (0x5F88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3476 (0x56ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3477 (0x2F4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3478 (0x3A5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3479 (0x649Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3480 (0x6B49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3481 (0x5A96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3482 (0x1D1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3483 (0x3CB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3484 (0x4AC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3485 (0x46F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3486 (0x4F70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3487 (0x30F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3488 (0x11DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3489 (0x692Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3490 (0x147Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3491 (0x2E6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3492 (0x3CC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3493 (0x56B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3494 (0x34AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3495 (0x4DD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3496 (0x33F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3497 (0x3E23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3498 (0x3F42u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3499 (0x6791u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3500 (0x2DE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3501 (0x663Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3502 (0x54ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3503 (0x3CACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3504 (0x3716u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3505 (0x2E1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3506 (0x7C45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3507 (0x707Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3508 (0x71A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3509 (0x57A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3510 (0x073Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3511 (0x705Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3512 (0x6D0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3513 (0x65E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3514 (0x74D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3515 (0x6D07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3516 (0x661Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3517 (0x74B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3518 (0x0EB6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3519 (0x16F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3520 (0x5E58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3521 (0x3732u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3522 (0x5A35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3523 (0x2477u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3524 (0x30CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3525 (0x3EC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3526 (0x0DF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3527 (0x71D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3528 (0x178Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3529 (0x22B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3530 (0x35D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3531 (0x37A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3532 (0x5707u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3533 (0x702Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3534 (0x6B45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3535 (0x4B6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3536 (0x17C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3537 (0x2B96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3538 (0x6743u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3539 (0x6D98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3540 (0x7C83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3541 (0x71D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3542 (0x15DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3543 (0x3633u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3544 (0x64BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3545 (0x55A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3546 (0x1B0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3547 (0x4E95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3548 (0x368Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3549 (0x5355u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3550 (0x5C95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3551 (0x0ED5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3552 (0x472Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3553 (0x6D4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3554 (0x6653u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3555 (0x32B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3556 (0x467Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3557 (0x2F26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3558 (0x3A9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3559 (0x470Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3560 (0x554Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3561 (0x6D0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3562 (0x0BEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3563 (0x64AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3564 (0x4ACBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3565 (0x1676u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3566 (0x6993u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3567 (0x2CF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3568 (0x170Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3569 (0x72CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3570 (0x595Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3571 (0x4B17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3572 (0x2BAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3573 (0x2D5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3574 (0x785Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3575 (0x13DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3576 (0x3D0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3577 (0x6CC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3578 (0x66AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3579 (0x4CECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3580 (0x16D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3581 (0x6467u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3582 (0x15CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3583 (0x5A65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3584 (0x43AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3585 (0x3798u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3586 (0x60F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3587 (0x455Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3588 (0x4F38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3589 (0x64A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3590 (0x7616u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3591 (0x2F89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3592 (0x4E4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3593 (0x15F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3594 (0x36C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3595 (0x6355u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3596 (0x544Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3597 (0x7D22u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3598 (0x39A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3599 (0x5A8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3600 (0x2D87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3601 (0x465Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3602 (0x761Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3603 (0x65F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3604 (0x093Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3605 (0x50DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3606 (0x2F29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3607 (0x05BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3608 (0x7722u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3609 (0x709Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3610 (0x4E59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3611 (0x2B8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3612 (0x1F15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3613 (0x5DB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3614 (0x6770u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3615 (0x2F92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3616 (0x44BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3617 (0x6B31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3618 (0x1967u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3619 (0x626Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3620 (0x3E49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3621 (0x62DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3622 (0x76B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3623 (0x40BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3624 (0x625Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3625 (0x63E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3626 (0x6FA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3627 (0x1973u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3628 (0x6875u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3629 (0x56C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3630 (0x3DA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3631 (0x51E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3632 (0x5AC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3633 (0x4373u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3634 (0x12DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3635 (0x721Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3636 (0x067Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3637 (0x166Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3638 (0x41F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3639 (0x247Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3640 (0x0AB7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3641 (0x4E6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3642 (0x2573u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3643 (0x3393u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3644 (0x07AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3645 (0x6595u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3646 (0x5565u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3647 (0x1EE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3648 (0x3DC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3649 (0x74A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3650 (0x3CB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3651 (0x6978u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3652 (0x07CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3653 (0x47B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3654 (0x3D61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3655 (0x1F0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3656 (0x626Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3657 (0x54A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3658 (0x685Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3659 (0x572Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3660 (0x358Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3661 (0x4BD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3662 (0x31D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3663 (0x56E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3664 (0x6EC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3665 (0x38F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3666 (0x7C34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3667 (0x664Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3668 (0x1CABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3669 (0x6565u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3670 (0x0A7Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3671 (0x7199u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3672 (0x19B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3673 (0x48EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3674 (0x07DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3675 (0x08F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3676 (0x6B98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3677 (0x329Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3678 (0x74D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3679 (0x71E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3680 (0x0F65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3681 (0x5E83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3682 (0x2D35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3683 (0x3336u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3684 (0x38DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3685 (0x58DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3686 (0x7B0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3687 (0x4CB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3688 (0x61B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3689 (0x4E2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3690 (0x26BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3691 (0x55B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3692 (0x3867u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3693 (0x47CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3694 (0x7C0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3695 (0x61ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3696 (0x163Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3697 (0x0D5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3698 (0x16E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3699 (0x10DFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3700 (0x5F90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3701 (0x58CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3702 (0x35C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3703 (0x072Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3704 (0x687Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3705 (0x1CB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3706 (0x4E66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3707 (0x19F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3708 (0x4AB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3709 (0x55C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3710 (0x589Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3711 (0x5363u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3712 (0x4D3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3713 (0x169Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3714 (0x197Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3715 (0x6C39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3716 (0x6F11u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3717 (0x1BD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3718 (0x2B0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3719 (0x1F92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3720 (0x44DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3721 (0x7692u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3722 (0x7E48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3723 (0x4B63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3724 (0x52F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3725 (0x6D68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3726 (0x2FE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3727 (0x2657u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3728 (0x5A6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3729 (0x71C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3730 (0x4B1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3731 (0x27A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3732 (0x6AE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3733 (0x51ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3734 (0x21DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3735 (0x1E9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3736 (0x7417u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3737 (0x35A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3738 (0x2ACEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3739 (0x3F05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3740 (0x6C47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3741 (0x2E2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3742 (0x12DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3743 (0x1765u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3744 (0x2B99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3745 (0x24F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3746 (0x1AF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3747 (0x4A9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3748 (0x0F4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3749 (0x562Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3750 (0x7E05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3751 (0x6713u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3752 (0x1B17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3753 (0x32B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3754 (0x6695u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3755 (0x59CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3756 (0x7127u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3757 (0x0CFAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3758 (0x7513u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3759 (0x71E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3760 (0x78ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3761 (0x5475u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3762 (0x59C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3763 (0x585Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3764 (0x32BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3765 (0x75C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3766 (0x167Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3767 (0x5E32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3768 (0x5993u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3769 (0x233Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3770 (0x4BACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3771 (0x3C63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3772 (0x4877u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3773 (0x3B23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3774 (0x1A8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3775 (0x213Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3776 (0x7589u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3777 (0x5B32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3778 (0x1BC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3779 (0x6AC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3780 (0x438Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3781 (0x61E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3782 (0x70EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3783 (0x30EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3784 (0x5AD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3785 (0x0ECEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3786 (0x5FC0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3787 (0x273Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3788 (0x1E27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3789 (0x5CACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3790 (0x3ED0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3791 (0x6C72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3792 (0x7F04u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3793 (0x70BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3794 (0x19F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3795 (0x6D31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3796 (0x7156u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3797 (0x7712u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3798 (0x12B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3799 (0x598Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3800 (0x689Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3801 (0x5DA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3802 (0x5556u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3803 (0x172Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3804 (0x7352u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3805 (0x71B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3806 (0x26E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3807 (0x17A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3808 (0x0CBBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3809 (0x669Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3810 (0x5F50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3811 (0x687Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3812 (0x2A73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3813 (0x3C53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3814 (0x360Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3815 (0x594Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3816 (0x7392u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3817 (0x4B8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3818 (0x38CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3819 (0x7835u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3820 (0x33C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3821 (0x598Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3822 (0x2D69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3823 (0x2DD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3824 (0x7E21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3825 (0x71B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3826 (0x4739u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3827 (0x3C39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3828 (0x5593u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3829 (0x42F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3830 (0x4E3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3831 (0x0F39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3832 (0x7742u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3833 (0x3E98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3834 (0x0F3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3835 (0x384Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3836 (0x5D29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3837 (0x4CE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3838 (0x6C8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3839 (0x6387u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3840 (0x674Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3841 (0x586Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3842 (0x693Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3843 (0x63C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3844 (0x54ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3845 (0x1AABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3846 (0x333Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3847 (0x7BA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3848 (0x41BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3849 (0x4B35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3850 (0x09F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3851 (0x50AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3852 (0x329Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3853 (0x2A7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3854 (0x7E0Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3855 (0x05DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3856 (0x59F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3857 (0x72ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3858 (0x3B85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3859 (0x2B5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3860 (0x4FD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3861 (0x249Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3862 (0x13E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3863 (0x68E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3864 (0x62E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3865 (0x2774u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3866 (0x28FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3867 (0x5D51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3868 (0x60DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3869 (0x1DA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3870 (0x6553u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3871 (0x5A59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3872 (0x71D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3873 (0x6ACCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3874 (0x40FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3875 (0x59E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3876 (0x50CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3877 (0x770Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3878 (0x4F61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3879 (0x4B69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3880 (0x534Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3881 (0x0EF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3882 (0x45CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3883 (0x2733u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3884 (0x5157u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3885 (0x29C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3886 (0x09B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3887 (0x6B68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3888 (0x45E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3889 (0x2DC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3890 (0x6A6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3891 (0x23D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3892 (0x4177u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3893 (0x54AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3894 (0x56D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3895 (0x73A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3896 (0x27CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3897 (0x5B91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3898 (0x2F1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3899 (0x3F12u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3900 (0x0E5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3901 (0x271Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3902 (0x671Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3903 (0x4BE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3904 (0x4976u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3905 (0x5A1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3906 (0x3F30u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3907 (0x725Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3908 (0x12D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3909 (0x29E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3910 (0x3749u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3911 (0x49D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3912 (0x466Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3913 (0x254Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3914 (0x2A1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3915 (0x3786u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3916 (0x7A62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3917 (0x79A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3918 (0x7A1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3919 (0x7D12u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3920 (0x3E61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3921 (0x4F2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3922 (0x2E63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3923 (0x3C87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3924 (0x09CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3925 (0x68C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3926 (0x5715u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3927 (0x67A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3928 (0x2EACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3929 (0x79C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3930 (0x3267u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3931 (0x4B36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3932 (0x5571u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3933 (0x16B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3934 (0x077Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3935 (0x14FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3936 (0x1D1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3937 (0x5179u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3938 (0x5AAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3939 (0x4B99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3940 (0x1ABCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3941 (0x0E5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3942 (0x64D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3943 (0x28B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3944 (0x5C8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3945 (0x4F0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3946 (0x7266u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3947 (0x5527u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3948 (0x1E65u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3949 (0x626Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3950 (0x1CCDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3951 (0x51BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3952 (0x11DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3953 (0x6176u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3954 (0x35A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3955 (0x5DD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3956 (0x2747u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3957 (0x7583u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3958 (0x3746u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3959 (0x2575u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3960 (0x33E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3961 (0x1E36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3962 (0x2F8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3963 (0x3CE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3964 (0x22EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3965 (0x2E35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3966 (0x4AABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3967 (0x4D2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3968 (0x07BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3969 (0x758Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3970 (0x631Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3971 (0x3599u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3972 (0x7551u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3973 (0x6768u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3974 (0x4BB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3975 (0x7B09u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3976 (0x74ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3977 (0x26B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3978 (0x72B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3979 (0x7B81u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3980 (0x56B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3981 (0x2E56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3982 (0x474Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3983 (0x445Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3984 (0x43DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3985 (0x7519u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3986 (0x1D63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3987 (0x2BE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3988 (0x265Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3989 (0x4CF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3990 (0x5D07u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3991 (0x0FC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3992 (0x5999u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3993 (0x27F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3994 (0x6C69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3995 (0x1A37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3996 (0x627Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3997 (0x6687u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3998 (0x24BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_3999 (0x5D38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4000 (0x0FACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4001 (0x3754u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4002 (0x7351u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4003 (0x0BD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4004 (0x7919u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4005 (0x28BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4006 (0x3B15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4007 (0x34B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4008 (0x3B62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4009 (0x2EA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4010 (0x7694u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4011 (0x54E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4012 (0x6D61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4013 (0x5399u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4014 (0x718Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4015 (0x3B64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4016 (0x6333u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4017 (0x1D47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4018 (0x31D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4019 (0x5539u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4020 (0x68ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4021 (0x4E5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4022 (0x3BC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4023 (0x0EC7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4024 (0x74E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4025 (0x193Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4026 (0x7332u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4027 (0x287Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4028 (0x13D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4029 (0x43D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4030 (0x38EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4031 (0x3F22u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4032 (0x6EC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4033 (0x45A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4034 (0x7B18u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4035 (0x5E31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4036 (0x73C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4037 (0x74E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4038 (0x6C9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4039 (0x6ED0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4040 (0x1CAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4041 (0x389Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4042 (0x5751u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4043 (0x36C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4044 (0x45C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4045 (0x36A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4046 (0x1575u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4047 (0x7836u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4048 (0x42F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4049 (0x3A6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4050 (0x3347u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4051 (0x2B4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4052 (0x27C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4053 (0x15EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4054 (0x48F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4055 (0x6A95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4056 (0x3B1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4057 (0x4B6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4058 (0x29A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4059 (0x0EE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4060 (0x4B56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4061 (0x5E15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4062 (0x22EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4063 (0x43C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4064 (0x1F1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4065 (0x71E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4066 (0x28EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4067 (0x36E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4068 (0x247Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4069 (0x4F26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4070 (0x7D82u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4071 (0x6674u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4072 (0x04FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4073 (0x531Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4074 (0x5761u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4075 (0x49D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4076 (0x7B50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4077 (0x5732u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4078 (0x2675u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4079 (0x7478u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4080 (0x3CA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4081 (0x4B5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4082 (0x4C57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4083 (0x6BE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4084 (0x2C79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4085 (0x1B66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4086 (0x74B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4087 (0x6E23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4088 (0x6C2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4089 (0x03D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4090 (0x5A33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4091 (0x3EC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4092 (0x55D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4093 (0x719Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4094 (0x639Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4095 (0x7349u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4096 (0x4B27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4097 (0x1CD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4098 (0x584Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4099 (0x33D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4100 (0x2FC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4101 (0x545Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4102 (0x7CA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4103 (0x3D2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4104 (0x1CEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4105 (0x4DA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4106 (0x65CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4107 (0x4ECCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4108 (0x4B95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4109 (0x7817u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4110 (0x6D83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4111 (0x6A1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4112 (0x29B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4113 (0x6DB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4114 (0x135Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4115 (0x3791u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4116 (0x16ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4117 (0x1DD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4118 (0x5792u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4119 (0x4F91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4120 (0x4FC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4121 (0x471Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4122 (0x1763u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4123 (0x6C78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4124 (0x6B94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4125 (0x133Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4126 (0x581Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4127 (0x5F60u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4128 (0x7E42u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4129 (0x6F84u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4130 (0x1BA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4131 (0x62BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4132 (0x26D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4133 (0x751Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4134 (0x34ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4135 (0x0776u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4136 (0x2B95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4137 (0x7855u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4138 (0x60D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4139 (0x13E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4140 (0x5971u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4141 (0x45E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4142 (0x447Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4143 (0x4A57u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4144 (0x23ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4145 (0x3B68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4146 (0x3595u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4147 (0x06AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4148 (0x65C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4149 (0x31ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4150 (0x1F46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4151 (0x750Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4152 (0x323Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4153 (0x62ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4154 (0x6378u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4155 (0x5F21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4156 (0x24EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4157 (0x26B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4158 (0x2CDCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4159 (0x7A34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4160 (0x355Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4161 (0x1ADAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4162 (0x5666u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4163 (0x5CE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4164 (0x21DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4165 (0x3D98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4166 (0x19D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4167 (0x64E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4168 (0x6A53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4169 (0x145Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4170 (0x23A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4171 (0x3725u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4172 (0x782Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4173 (0x6539u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4174 (0x2B72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4175 (0x54F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4176 (0x462Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4177 (0x63A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4178 (0x6617u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4179 (0x16E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4180 (0x6B23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4181 (0x3933u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4182 (0x52B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4183 (0x3A3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4184 (0x5B4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4185 (0x636Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4186 (0x706Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4187 (0x0F1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4188 (0x0EB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4189 (0x46B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4190 (0x5837u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4191 (0x0AE7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4192 (0x7689u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4193 (0x3993u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4194 (0x68B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4195 (0x4A4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4196 (0x3789u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4197 (0x2E55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4198 (0x5678u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4199 (0x7532u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4200 (0x4F85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4201 (0x6BA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4202 (0x61F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4203 (0x0ADEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4204 (0x678Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4205 (0x2F25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4206 (0x13F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4207 (0x4D78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4208 (0x67C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4209 (0x1AD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4210 (0x647Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4211 (0x3B52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4212 (0x43B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4213 (0x4D36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4214 (0x611Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4215 (0x6D34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4216 (0x7296u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4217 (0x1A5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4218 (0x7C51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4219 (0x3F82u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4220 (0x0DF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4221 (0x760Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4222 (0x07D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4223 (0x1F85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4224 (0x568Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4225 (0x6197u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4226 (0x499Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4227 (0x6B51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4228 (0x2637u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4229 (0x12FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4230 (0x49AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4231 (0x1D0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4232 (0x3AA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4233 (0x0FC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4234 (0x2D93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4235 (0x5E13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4236 (0x331Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4237 (0x73A1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4238 (0x3E2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4239 (0x5A53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4240 (0x6746u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4241 (0x371Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4242 (0x70D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4243 (0x51F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4244 (0x4774u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4245 (0x4C9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4246 (0x3665u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4247 (0x531Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4248 (0x473Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4249 (0x1C6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4250 (0x16A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4251 (0x44DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4252 (0x1E6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4253 (0x3175u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4254 (0x5743u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4255 (0x6B1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4256 (0x55C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4257 (0x2A3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4258 (0x5729u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4259 (0x336Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4260 (0x4E87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4261 (0x4CBAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4262 (0x1D66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4263 (0x33A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4264 (0x17B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4265 (0x6B91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4266 (0x43EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4267 (0x61F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4268 (0x0ABDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4269 (0x5647u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4270 (0x4B78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4271 (0x02FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4272 (0x53C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4273 (0x68D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4274 (0x742Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4275 (0x7AC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4276 (0x3768u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4277 (0x1E8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4278 (0x7263u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4279 (0x0B1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4280 (0x2D9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4281 (0x7CA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4282 (0x46B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4283 (0x526Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4284 (0x7869u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4285 (0x7E0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4286 (0x268Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4287 (0x57A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4288 (0x6276u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4289 (0x0DD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4290 (0x16C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4291 (0x35C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4292 (0x7433u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4293 (0x2B3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4294 (0x5963u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4295 (0x30AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4296 (0x0F93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4297 (0x1E35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4298 (0x5237u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4299 (0x6297u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4300 (0x34F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4301 (0x399Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4302 (0x6374u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4303 (0x2EC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4304 (0x3E31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4305 (0x27C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4306 (0x565Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4307 (0x27A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4308 (0x475Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4309 (0x738Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4310 (0x53B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4311 (0x7057u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4312 (0x66ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4313 (0x7D18u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4314 (0x38F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4315 (0x3CC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4316 (0x6754u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4317 (0x26CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4318 (0x7C1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4319 (0x42CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4320 (0x562Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4321 (0x6A93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4322 (0x54E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4323 (0x2B8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4324 (0x6D92u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4325 (0x5B94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4326 (0x7703u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4327 (0x552Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4328 (0x6A9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4329 (0x5B46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4330 (0x1A3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4331 (0x53E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4332 (0x136Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4333 (0x7645u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4334 (0x0BAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4335 (0x72B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4336 (0x3355u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4337 (0x7155u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4338 (0x64BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4339 (0x683Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4340 (0x7B12u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4341 (0x526Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4342 (0x3E1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4343 (0x2717u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4344 (0x2F13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4345 (0x05F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4346 (0x656Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4347 (0x624Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4348 (0x1FA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4349 (0x507Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4350 (0x3C1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4351 (0x742Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4352 (0x1DC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4353 (0x6E94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4354 (0x53E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4355 (0x1F52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4356 (0x073Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4357 (0x4F4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4358 (0x7C25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4359 (0x38AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4360 (0x13B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4361 (0x0EB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4362 (0x3C5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4363 (0x127Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4364 (0x6555u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4365 (0x158Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4366 (0x3D19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4367 (0x1997u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4368 (0x2D8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4369 (0x0C7Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4370 (0x3BC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4371 (0x7386u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4372 (0x7A4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4373 (0x5AD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4374 (0x0BCDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4375 (0x2F98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4376 (0x06B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4377 (0x7368u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4378 (0x1D33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4379 (0x33D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4380 (0x363Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4381 (0x3AB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4382 (0x7507u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4383 (0x7721u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4384 (0x2E27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4385 (0x4C3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4386 (0x5DC2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4387 (0x5B13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4388 (0x69B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4389 (0x3A1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4390 (0x452Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4391 (0x2A6Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4392 (0x5371u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4393 (0x4D87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4394 (0x7C15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4395 (0x6E4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4396 (0x58CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4397 (0x276Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4398 (0x70D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4399 (0x68BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4400 (0x4769u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4401 (0x2AEAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4402 (0x527Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4403 (0x2E6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4404 (0x781Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4405 (0x5AA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4406 (0x2D3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4407 (0x764Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4408 (0x592Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4409 (0x7C61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4410 (0x2B9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4411 (0x463Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4412 (0x3726u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4413 (0x62CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4414 (0x665Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4415 (0x4F13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4416 (0x20EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4417 (0x1979u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4418 (0x0FD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4419 (0x29CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4420 (0x1B27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4421 (0x666Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4422 (0x70F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4423 (0x6C6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4424 (0x193Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4425 (0x3A36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4426 (0x43F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4427 (0x37E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4428 (0x06EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4429 (0x1C8Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4430 (0x74F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4431 (0x4765u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4432 (0x6E43u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4433 (0x29E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4434 (0x5D32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4435 (0x1ACDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4436 (0x0CAFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4437 (0x2772u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4438 (0x5E89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4439 (0x6C53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4440 (0x1E78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4441 (0x5B49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4442 (0x552Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4443 (0x0CDBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4444 (0x2AE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4445 (0x654Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4446 (0x0F2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4447 (0x6B13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4448 (0x299Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4449 (0x65E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4450 (0x4FE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4451 (0x0D3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4452 (0x44BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4453 (0x287Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4454 (0x75A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4455 (0x639Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4456 (0x1E1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4457 (0x1B1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4458 (0x3533u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4459 (0x1E17u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4460 (0x465Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4461 (0x2EE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4462 (0x335Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4463 (0x54DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4464 (0x497Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4465 (0x4597u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4466 (0x6CC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4467 (0x34C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4468 (0x538Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4469 (0x3476u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4470 (0x5D8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4471 (0x15B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4472 (0x2DF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4473 (0x3AC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4474 (0x274Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4475 (0x5B0Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4476 (0x43E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4477 (0x3AD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4478 (0x6897u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4479 (0x37A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4480 (0x69AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4481 (0x6DA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4482 (0x5AE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4483 (0x1E9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4484 (0x1E93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4485 (0x6D2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4486 (0x5CB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4487 (0x4DACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4488 (0x0DB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4489 (0x17CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4490 (0x7C46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4491 (0x194Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4492 (0x0F71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4493 (0x4799u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4494 (0x6559u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4495 (0x4E1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4496 (0x23E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4497 (0x28DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4498 (0x7C19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4499 (0x6AE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4500 (0x6959u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4501 (0x6556u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4502 (0x52E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4503 (0x43D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4504 (0x7866u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4505 (0x2769u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4506 (0x30DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4507 (0x1FC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4508 (0x45E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4509 (0x6792u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4510 (0x5F11u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4511 (0x073Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4512 (0x309Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4513 (0x24FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4514 (0x4637u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4515 (0x29EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4516 (0x22BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4517 (0x2B39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4518 (0x469Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4519 (0x3B51u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4520 (0x1AD5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4521 (0x58ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4522 (0x649Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4523 (0x31BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4524 (0x25B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4525 (0x2D1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4526 (0x7174u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4527 (0x4E78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4528 (0x0F33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4529 (0x5693u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4530 (0x27D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4531 (0x6BC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4532 (0x5936u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4533 (0x09F5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4534 (0x64B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4535 (0x29E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4536 (0x3EE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4537 (0x5CCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4538 (0x0BECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4539 (0x7153u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4540 (0x4B4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4541 (0x6C4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4542 (0x165Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4543 (0x3758u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4544 (0x2BA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4545 (0x3CA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4546 (0x1E2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4547 (0x49F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4548 (0x262Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4549 (0x44B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4550 (0x33CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4551 (0x13BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4552 (0x172Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4553 (0x4ADCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4554 (0x7646u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4555 (0x09EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4556 (0x326Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4557 (0x0DABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4558 (0x7CA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4559 (0x4EF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4560 (0x51E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4561 (0x5CE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4562 (0x6571u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4563 (0x2EF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4564 (0x74A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4565 (0x1F61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4566 (0x25AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4567 (0x5E52u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4568 (0x461Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4569 (0x61E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4570 (0x605Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4571 (0x3E15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4572 (0x571Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4573 (0x27A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4574 (0x2EA5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4575 (0x283Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4576 (0x392Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4577 (0x49E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4578 (0x5B8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4579 (0x3C8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4580 (0x383Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4581 (0x6E98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4582 (0x47C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4583 (0x45ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4584 (0x678Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4585 (0x18B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4586 (0x1376u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4587 (0x1337u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4588 (0x62B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4589 (0x39D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4590 (0x037Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4591 (0x296Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4592 (0x31D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4593 (0x3936u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4594 (0x076Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4595 (0x3D86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4596 (0x29CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4597 (0x78E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4598 (0x5366u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4599 (0x49EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4600 (0x760Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4601 (0x2B8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4602 (0x4CD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4603 (0x7B88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4604 (0x4DC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4605 (0x3956u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4606 (0x51A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4607 (0x293Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4608 (0x267Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4609 (0x0E37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4610 (0x2E39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4611 (0x7B48u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4612 (0x7178u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4613 (0x6C5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4614 (0x51EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4615 (0x7970u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4616 (0x2A3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4617 (0x2C5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4618 (0x6729u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4619 (0x3707u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4620 (0x4DCAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4621 (0x2957u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4622 (0x266Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4623 (0x4ABCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4624 (0x4967u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4625 (0x199Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4626 (0x5725u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4627 (0x0F99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4628 (0x42E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4629 (0x5365u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4630 (0x2376u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4631 (0x275Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4632 (0x3C47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4633 (0x22E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4634 (0x4F86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4635 (0x0FE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4636 (0x5D25u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4637 (0x6D46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4638 (0x555Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4639 (0x18EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4640 (0x5D4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4641 (0x487Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4642 (0x71ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4643 (0x354Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4644 (0x4F0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4645 (0x0DF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4646 (0x3C74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4647 (0x0AF5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4648 (0x32CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4649 (0x298Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4650 (0x42DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4651 (0x186Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4652 (0x3C2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4653 (0x72A5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4654 (0x1B4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4655 (0x1E4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4656 (0x7863u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4657 (0x7C2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4658 (0x646Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4659 (0x4B5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4660 (0x583Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4661 (0x3387u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4662 (0x1BA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4663 (0x53C6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4664 (0x2FA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4665 (0x16BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4666 (0x7893u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4667 (0x31E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4668 (0x3276u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4669 (0x45D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4670 (0x25B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4671 (0x468Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4672 (0x1E96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4673 (0x079Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4674 (0x45EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4675 (0x361Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4676 (0x54BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4677 (0x3566u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4678 (0x0AF3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4679 (0x7CC8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4680 (0x5B61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4681 (0x6A8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4682 (0x398Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4683 (0x789Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4684 (0x50BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4685 (0x1EA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4686 (0x3715u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4687 (0x5783u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4688 (0x750Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4689 (0x75A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4690 (0x059Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4691 (0x1EAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4692 (0x0CEEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4693 (0x6719u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4694 (0x3E32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4695 (0x2B69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4696 (0x156Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4697 (0x57C8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4698 (0x60BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4699 (0x5C1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4700 (0x5C39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4701 (0x19CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4702 (0x7D90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4703 (0x315Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4704 (0x272Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4705 (0x66B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4706 (0x6E1Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4707 (0x6C6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4708 (0x4A3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4709 (0x23B6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4710 (0x560Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4711 (0x6FC0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4712 (0x3C4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4713 (0x1AD9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4714 (0x5DA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4715 (0x5E38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4716 (0x26E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4717 (0x517Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4718 (0x2C3Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4719 (0x3273u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4720 (0x6953u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4721 (0x50EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4722 (0x5275u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4723 (0x3AD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4724 (0x592Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4725 (0x51AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4726 (0x6A59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4727 (0x5699u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4728 (0x31F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4729 (0x3C8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4730 (0x7487u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4731 (0x427Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4732 (0x1F86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4733 (0x5E49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4734 (0x5F05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4735 (0x1D56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4736 (0x1CF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4737 (0x3752u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4738 (0x35B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4739 (0x670Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4740 (0x64D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4741 (0x2F4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4742 (0x5D34u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4743 (0x0DB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4744 (0x6F90u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4745 (0x306Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4746 (0x466Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4747 (0x6C9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4748 (0x1367u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4749 (0x69ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4750 (0x513Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4751 (0x3D62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4752 (0x313Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4753 (0x2D8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4754 (0x3B98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4755 (0x53E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4756 (0x3569u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4757 (0x6353u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4758 (0x1F31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4759 (0x1D6Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4760 (0x5687u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4761 (0x7515u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4762 (0x5BD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4763 (0x1772u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4764 (0x43E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4765 (0x36E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4766 (0x5B0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4767 (0x72E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4768 (0x349Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4769 (0x06BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4770 (0x5669u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4771 (0x5B8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4772 (0x498Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4773 (0x3535u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4774 (0x1D2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4775 (0x6B85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4776 (0x703Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4777 (0x7269u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4778 (0x50D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4779 (0x68CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4780 (0x69E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4781 (0x72E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4782 (0x752Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4783 (0x5749u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4784 (0x364Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4785 (0x1B9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4786 (0x5B86u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4787 (0x7C0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4788 (0x3F21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4789 (0x694Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4790 (0x5C2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4791 (0x6A3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4792 (0x2E2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4793 (0x38B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4794 (0x4ABAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4795 (0x52ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4796 (0x53D2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4797 (0x47ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4798 (0x187Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4799 (0x449Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4800 (0x25E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4801 (0x7354u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4802 (0x60B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4803 (0x1CDAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4804 (0x5395u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4805 (0x257Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4806 (0x471Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4807 (0x62E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4808 (0x331Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4809 (0x46C7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4810 (0x7D88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4811 (0x3AC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4812 (0x2367u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4813 (0x7598u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4814 (0x47B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4815 (0x7613u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4816 (0x58F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4817 (0x6C63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4818 (0x6A4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4819 (0x6F24u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4820 (0x5987u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4821 (0x234Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4822 (0x42DBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4823 (0x638Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4824 (0x4A37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4825 (0x2FC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4826 (0x7A49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4827 (0x417Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4828 (0x7C89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4829 (0x68ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4830 (0x51D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4831 (0x253Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4832 (0x6B83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4833 (0x1BB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4834 (0x1778u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4835 (0x3237u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4836 (0x74E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4837 (0x63C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4838 (0x1C6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4839 (0x31AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4840 (0x1ADCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4841 (0x5636u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4842 (0x2AF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4843 (0x64CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4844 (0x55ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4845 (0x1B72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4846 (0x6AD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4847 (0x40FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4848 (0x52CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4849 (0x343Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4850 (0x6935u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4851 (0x6578u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4852 (0x7466u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4853 (0x6BA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4854 (0x5AE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4855 (0x5596u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4856 (0x7529u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4857 (0x566Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4858 (0x4B9Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4859 (0x6A1Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4860 (0x174Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4861 (0x0AFCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4862 (0x1A7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4863 (0x394Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4864 (0x7A29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4865 (0x2E69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4866 (0x7C38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4867 (0x3BA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4868 (0x32ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4869 (0x5E64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4870 (0x179Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4871 (0x26DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4872 (0x32E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4873 (0x315Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4874 (0x7730u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4875 (0x2793u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4876 (0x24D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4877 (0x5F06u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4878 (0x3D2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4879 (0x5B45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4880 (0x4FA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4881 (0x3173u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4882 (0x628Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4883 (0x4BA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4884 (0x6AA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4885 (0x4D4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4886 (0x5752u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4887 (0x62F8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4888 (0x50EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4889 (0x63A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4890 (0x6566u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4891 (0x55B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4892 (0x62E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4893 (0x666Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4894 (0x5359u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4895 (0x5B15u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4896 (0x5B98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4897 (0x35C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4898 (0x1A75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4899 (0x28D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4900 (0x4397u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4901 (0x3D32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4902 (0x426Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4903 (0x5374u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4904 (0x13D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4905 (0x749Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4906 (0x196Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4907 (0x2753u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4908 (0x64ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4909 (0x6A2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4910 (0x6336u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4911 (0x39E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4912 (0x1EA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4913 (0x7A70u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4914 (0x2177u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4915 (0x5559u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4916 (0x223Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4917 (0x5FA0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4918 (0x4697u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4919 (0x1DE8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4920 (0x50F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4921 (0x2ED2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4922 (0x3C71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4923 (0x3317u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4924 (0x0E75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4925 (0x2DA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4926 (0x534Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4927 (0x09D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4928 (0x703Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4929 (0x6BA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4930 (0x31D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4931 (0x6EE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4932 (0x46CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4933 (0x1B78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4934 (0x6879u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4935 (0x5C8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4936 (0x5C66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4937 (0x50F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4938 (0x25ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4939 (0x6563u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4940 (0x726Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4941 (0x135Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4942 (0x7D03u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4943 (0x25ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4944 (0x3D91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4945 (0x26D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4946 (0x2D66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4947 (0x587Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4948 (0x4357u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4949 (0x09DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4950 (0x51F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4951 (0x5A72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4952 (0x7453u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4953 (0x171Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4954 (0x351Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4955 (0x1AE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4956 (0x699Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4957 (0x0FA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4958 (0x3729u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4959 (0x21EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4960 (0x6B16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4961 (0x3F60u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4962 (0x539Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4963 (0x3E68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4964 (0x1D74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4965 (0x732Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4966 (0x10FBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4967 (0x1AE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4968 (0x538Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4969 (0x0B79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4970 (0x1CD3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4971 (0x42EDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4972 (0x5555u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4973 (0x2D59u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4974 (0x594Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4975 (0x34E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4976 (0x60DEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4977 (0x533Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4978 (0x71A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4979 (0x516Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4980 (0x07F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4981 (0x6971u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4982 (0x546Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4983 (0x551Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4984 (0x2796u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4985 (0x0F55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4986 (0x72F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4987 (0x1DD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4988 (0x15F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4989 (0x5E19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4990 (0x39A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4991 (0x3574u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4992 (0x73E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4993 (0x6D23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4994 (0x4DD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4995 (0x564Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4996 (0x46ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4997 (0x36F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4998 (0x2E53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_4999 (0x523Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5000 (0x566Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5001 (0x0B37u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5002 (0x49ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5003 (0x52E6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5004 (0x7AC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5005 (0x5DA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5006 (0x1B63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5007 (0x5E2Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5008 (0x23ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5009 (0x350Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5010 (0x6DA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5011 (0x07ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5012 (0x76E0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5013 (0x27E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5014 (0x6AB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5015 (0x53A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5016 (0x62CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5017 (0x11F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5018 (0x41BEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5019 (0x7187u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5020 (0x4379u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5021 (0x7631u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5022 (0x32F1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5023 (0x356Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5024 (0x1C7Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5025 (0x2F85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5026 (0x49CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5027 (0x27C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5028 (0x52D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5029 (0x13CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5030 (0x1DACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5031 (0x78E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5032 (0x3C96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5033 (0x3C3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5034 (0x5ACCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5035 (0x1E69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5036 (0x7331u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5037 (0x3CB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5038 (0x56A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5039 (0x345Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5040 (0x6D38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5041 (0x149Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5042 (0x23AEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5043 (0x32B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5044 (0x66E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5045 (0x3D46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5046 (0x630Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5047 (0x38E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5048 (0x07A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5049 (0x6339u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5050 (0x6CD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5051 (0x3C95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5052 (0x6F50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5053 (0x1D4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5054 (0x56B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5055 (0x7A8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5056 (0x45B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5057 (0x1B5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5058 (0x2976u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5059 (0x6678u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5060 (0x6972u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5061 (0x2BE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5062 (0x066Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5063 (0x7455u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5064 (0x2D39u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5065 (0x32E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5066 (0x7D14u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5067 (0x21E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5068 (0x29B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5069 (0x46B5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5070 (0x3547u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5071 (0x534Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5072 (0x7A13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5073 (0x19E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5074 (0x32CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5075 (0x1CCBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5076 (0x349Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5077 (0x2D9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5078 (0x7C4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5079 (0x5EA8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5080 (0x5C2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5081 (0x1795u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5082 (0x434Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5083 (0x3556u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5084 (0x473Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5085 (0x6A69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5086 (0x5B4Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5087 (0x7662u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5088 (0x1727u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5089 (0x2F61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5090 (0x2DB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5091 (0x49A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5092 (0x46E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5093 (0x6479u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5094 (0x792Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5095 (0x34ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5096 (0x0EA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5097 (0x6627u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5098 (0x3696u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5099 (0x3593u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5100 (0x02FEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5101 (0x47AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5102 (0x57A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5103 (0x686Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5104 (0x256Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5105 (0x6917u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5106 (0x5C47u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5107 (0x5CC6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5108 (0x5E4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5109 (0x17ACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5110 (0x2F23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5111 (0x6936u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5112 (0x2AB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5113 (0x2CB3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5114 (0x5C74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5115 (0x286Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5116 (0x06DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5117 (0x6C74u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5118 (0x3587u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5119 (0x3EA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5120 (0x2D4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5121 (0x2EE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5122 (0x6572u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5123 (0x4D1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5124 (0x44E7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5125 (0x74A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5126 (0x4AADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5127 (0x0BE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5128 (0x4F62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5129 (0x35E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5130 (0x4E69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5131 (0x4F54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5132 (0x4667u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5133 (0x49E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5134 (0x7287u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5135 (0x1F62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5136 (0x7233u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5137 (0x71CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5138 (0x3369u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5139 (0x46E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5140 (0x2E4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5141 (0x3D23u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5142 (0x334Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5143 (0x56E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5144 (0x71AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5145 (0x38B9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5146 (0x3B45u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5147 (0x0BF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5148 (0x365Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5149 (0x1567u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5150 (0x635Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5151 (0x23DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5152 (0x2766u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5153 (0x6CE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5154 (0x1CF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5155 (0x1379u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5156 (0x4D69u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5157 (0x0D79u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5158 (0x22F6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5159 (0x7F10u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5160 (0x50FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5161 (0x4E9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5162 (0x347Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5163 (0x399Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5164 (0x39B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5165 (0x6C33u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5166 (0x6E26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5167 (0x5CE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5168 (0x4AE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5169 (0x548Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5170 (0x33B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5171 (0x226Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5172 (0x3969u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5173 (0x56D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5174 (0x692Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5175 (0x7531u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5176 (0x2F94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5177 (0x1DA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5178 (0x1EE1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5179 (0x165Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5180 (0x46D5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5181 (0x55AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5182 (0x38BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5183 (0x6CC9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5184 (0x36E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5185 (0x156Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5186 (0x68D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5187 (0x26D6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5188 (0x1C9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5189 (0x7329u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5190 (0x752Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5191 (0x28AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5192 (0x1F13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5193 (0x7954u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5194 (0x79D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5195 (0x21FCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5196 (0x54F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5197 (0x7C32u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5198 (0x6C87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5199 (0x5279u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5200 (0x4D5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5201 (0x5AA6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5202 (0x4A75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5203 (0x669Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5204 (0x3A35u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5205 (0x552Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5206 (0x4DE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5207 (0x41D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5208 (0x455Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5209 (0x0BB5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5210 (0x1CF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5211 (0x6157u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5212 (0x1B6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5213 (0x2C6Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5214 (0x4DB2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5215 (0x22CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5216 (0x2F8Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5217 (0x6656u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5218 (0x7A58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5219 (0x3A8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5220 (0x5533u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5221 (0x1DA9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5222 (0x7A98u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5223 (0x27D1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5224 (0x1DB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5225 (0x0F5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5226 (0x6E13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5227 (0x65B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5228 (0x3D49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5229 (0x36B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5230 (0x3B0Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5231 (0x0C9Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5232 (0x143Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5233 (0x17AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5234 (0x5995u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5235 (0x5785u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5236 (0x176Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5237 (0x51B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5238 (0x386Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5239 (0x7652u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5240 (0x7E41u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5241 (0x37A8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5242 (0x619Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5243 (0x6AD2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5244 (0x3E4Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5245 (0x7471u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5246 (0x503Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5247 (0x66B2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5248 (0x4DC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5249 (0x2CF2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5250 (0x6B54u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5251 (0x65B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5252 (0x7874u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5253 (0x42B7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5254 (0x1F94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5255 (0x1D4Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5256 (0x5F84u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5257 (0x6987u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5258 (0x31B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5259 (0x347Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5260 (0x16CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5261 (0x4A9Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5262 (0x0D6Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5263 (0x3F50u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5264 (0x2F64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5265 (0x3687u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5266 (0x0ADDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5267 (0x0BF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5268 (0x3C99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5269 (0x1C5Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5270 (0x20F7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5271 (0x09FAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5272 (0x3CF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5273 (0x456Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5274 (0x18EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5275 (0x782Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5276 (0x0FD8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5277 (0x69C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5278 (0x2E4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5279 (0x7A64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5280 (0x1AF1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5281 (0x1AB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5282 (0x48F3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5283 (0x1FA4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5284 (0x12F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5285 (0x485Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5286 (0x7B44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5287 (0x645Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5288 (0x5746u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5289 (0x7C85u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5290 (0x0773u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5291 (0x4997u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5292 (0x5F0Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5293 (0x2A4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5294 (0x317Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5295 (0x722Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5296 (0x7C64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5297 (0x459Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5298 (0x525Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5299 (0x7493u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5300 (0x708Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5301 (0x15BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5302 (0x7AD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5303 (0x3B49u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5304 (0x6EC4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5305 (0x3E2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5306 (0x278Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5307 (0x3D13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5308 (0x70CDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5309 (0x4A1Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5310 (0x3CE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5311 (0x17B4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5312 (0x17E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5313 (0x49ADu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5314 (0x6AC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5315 (0x6D29u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5316 (0x0EB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5317 (0x6D13u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5318 (0x172Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5319 (0x77A0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5320 (0x10FDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5321 (0x0BA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5322 (0x3966u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5323 (0x38F4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5324 (0x20BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5325 (0x31ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5326 (0x1E3Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5327 (0x5ACAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5328 (0x5D68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5329 (0x322Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5330 (0x2FA1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5331 (0x079Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5332 (0x6965u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5333 (0x4A76u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5334 (0x712Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5335 (0x7D30u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5336 (0x5B19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5337 (0x0EE6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5338 (0x0F95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5339 (0x68DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5340 (0x2BF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5341 (0x2EE4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5342 (0x632Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5343 (0x3C78u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5344 (0x7CD0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5345 (0x74B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5346 (0x189Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5347 (0x08BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5348 (0x0BE9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5349 (0x0CDDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5350 (0x60EBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5351 (0x550Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5352 (0x17B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5353 (0x4DB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5354 (0x76A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5355 (0x1D71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5356 (0x2DA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5357 (0x17CCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5358 (0x3F88u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5359 (0x65E8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5360 (0x788Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5361 (0x7706u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5362 (0x7983u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5363 (0x3A6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5364 (0x5996u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5365 (0x1735u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5366 (0x25D9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5367 (0x37B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5368 (0x2BB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5369 (0x5E91u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5370 (0x5D31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5371 (0x4D63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5372 (0x7E12u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5373 (0x5A4Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5374 (0x7465u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5375 (0x39C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5376 (0x6237u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5377 (0x7A61u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5378 (0x2A75u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5379 (0x2967u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5380 (0x6749u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5381 (0x1ED8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5382 (0x3CC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5383 (0x34CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5384 (0x4B0Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5385 (0x6CB8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5386 (0x54CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5387 (0x253Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5388 (0x313Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5389 (0x4AF4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5390 (0x2B5Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5391 (0x5B64u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5392 (0x570Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5393 (0x5F81u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5394 (0x6327u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5395 (0x556Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5396 (0x3A4Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5397 (0x6659u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5398 (0x3A99u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5399 (0x62ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5400 (0x0C7Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5401 (0x625Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5402 (0x487Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5403 (0x2E8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5404 (0x66A9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5405 (0x486Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5406 (0x05EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5407 (0x1E1Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5408 (0x6596u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5409 (0x59D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5410 (0x2CB9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5411 (0x74C9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5412 (0x291Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5413 (0x472Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5414 (0x279Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5415 (0x113Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5416 (0x474Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5417 (0x5965u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5418 (0x0EF8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5419 (0x35E2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5420 (0x0F9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5421 (0x5535u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5422 (0x352Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5423 (0x6DC1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5424 (0x6C8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5425 (0x29ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5426 (0x22BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5427 (0x6963u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5428 (0x363Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5429 (0x3CD1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5430 (0x196Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5431 (0x64DAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5432 (0x5696u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5433 (0x1E71u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5434 (0x6B89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5435 (0x3176u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5436 (0x6275u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5437 (0x39CAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5438 (0x4B96u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5439 (0x76D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5440 (0x13ECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5441 (0x698Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5442 (0x3E19u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5443 (0x65B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5444 (0x741Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5445 (0x4FA2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5446 (0x7A31u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5447 (0x695Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5448 (0x2D2Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5449 (0x4D8Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5450 (0x4747u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5451 (0x26E5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5452 (0x4CD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5453 (0x71C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5454 (0x4E53u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5455 (0x2AAEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5456 (0x3517u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5457 (0x1D6Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5458 (0x10BFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5459 (0x531Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5460 (0x0E67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5461 (0x62D3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5462 (0x3553u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5463 (0x4BA3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5464 (0x613Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5465 (0x7166u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5466 (0x3137u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5467 (0x2D5Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5468 (0x0AFAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5469 (0x446Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5470 (0x0BBCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5471 (0x6CB4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5472 (0x699Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5473 (0x1C73u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5474 (0x28CFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5475 (0x3A27u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5476 (0x7D05u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5477 (0x6995u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5478 (0x1AD6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5479 (0x1A5Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5480 (0x1F8Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5481 (0x79A2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5482 (0x70E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5483 (0x5F44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5484 (0x6B62u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5485 (0x3AAAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5486 (0x5AB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5487 (0x6CCCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5488 (0x47E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5489 (0x0E3Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5490 (0x6D26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5491 (0x2BE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5492 (0x47D8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5493 (0x66C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5494 (0x437Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5495 (0x06BBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5496 (0x4B8Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5497 (0x4B72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5498 (0x1E95u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5499 (0x1A4Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5500 (0x16CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5501 (0x7788u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5502 (0x6BB0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5503 (0x71B8u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5504 (0x4E55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5505 (0x7C68u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5506 (0x42EEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5507 (0x6C93u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5508 (0x2DE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5509 (0x338Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5510 (0x1EC3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5511 (0x64F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5512 (0x56C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5513 (0x1EF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5514 (0x52BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5515 (0x72D4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5516 (0x4C9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5517 (0x6B38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5518 (0x3E0Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5519 (0x391Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5520 (0x56E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5521 (0x7625u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5522 (0x4AECu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5523 (0x074Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5524 (0x0CF9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5525 (0x263Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5526 (0x3E38u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5527 (0x7946u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5528 (0x1BC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5529 (0x2D2Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5530 (0x38ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5531 (0x370Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5532 (0x3A2Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5533 (0x3279u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5534 (0x711Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5535 (0x72E1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5536 (0x57B0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5537 (0x65E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5538 (0x643Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5539 (0x49E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5540 (0x387Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5541 (0x7B03u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5542 (0x4CE5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5543 (0x582Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5544 (0x6A1Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5545 (0x0779u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5546 (0x1E56u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5547 (0x58CBu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5548 (0x713Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5549 (0x4F89u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5550 (0x7436u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5551 (0x7594u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5552 (0x1A9Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5553 (0x6E16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5554 (0x48AFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5555 (0x49B3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5556 (0x2D3Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5557 (0x7165u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5558 (0x0775u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5559 (0x4E72u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5560 (0x65A6u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5561 (0x04EFu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5562 (0x616Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5563 (0x2E36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5564 (0x704Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5565 (0x35A3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5566 (0x4C67u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5567 (0x72C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5568 (0x7711u) +#define MCUX_CSSL_FP_FUNCID_mcuxCl_unused_5569 (0x4AD6u) + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +#endif /* MCUX_CL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h new file mode 100644 index 000000000..1424cc6ae --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Platform.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCORE_PLATFORM_H_ +#define MCUXCLCORE_PLATFORM_H_ + +#include +#include +#include + +#include // Exported features flags header + +#endif /* MCUXCLCORE_PLATFORM_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h new file mode 100644 index 000000000..e59b6ea11 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClCore/inc/mcuxClCore_Toolchain.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLCORE_TOOLCHAIN_H_ +#define MCUXCLCORE_TOOLCHAIN_H_ + +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap64) +static inline uint64_t mcuxCl_Core_Swap64(uint64_t value) +{ + return __builtin_bswap64(value); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCl_Core_Swap32) +static inline uint32_t mcuxCl_Core_Swap32(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +#endif /* MCUXCLCORE_TOOLCHAIN_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h new file mode 100644 index 000000000..c1a775fab --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP_H_ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP_H_ + +#include // Exported features flags header +#include + + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S + */ +#define mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S_LEN 6u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S[mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S_LEN]; + + +#endif /* MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateSignature_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateSignature_FUP.h new file mode 100644 index 000000000..07004bb50 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_GenerateSignature_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateSignature_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP_H_ +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN + */ +#define mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN[mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S + */ +#define mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S[mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal.h new file mode 100644 index 000000000..03d7f68c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal.h @@ -0,0 +1,169 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal.h + * @brief internal header of mcuxClEcc EdDSA functionalities + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_H_ +#define MCUXCLECC_EDDSA_INTERNAL_H_ + + +#include + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Internal return codes for EdDSA functions */ +/**********************************************************/ +// None + + +/**********************************************************/ +/* Internal EdDSA defines */ +/**********************************************************/ + +/** + * Options for EdDSA key pair generation descriptors + */ +#define MCUXCLECC_EDDSA_PRIVKEY_INPUT (0xA5A5A5A5U) ///< the private key d is passed as input +#define MCUXCLECC_EDDSA_PRIVKEY_GENERATE (0X5A5A5A5AU) ///< the private key is generated internally + +/** + * Length for EdDSA Domain prefix + */ +#define MCUXCLECC_EDDSA_ED25519_DOMPREFIXLEN (32u) ///< the length of ED25519 domain prefix +#define MCUXCLECC_EDDSA_ED448_DOMPREFIXLEN (8u) ///< the length of ED448 domain prefix + +/**********************************************************/ +/* Declarations for internal EdDSA functions */ +/**********************************************************/ + + + + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint8_t noOfBuffers + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_CalcHashModN) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_CalcHashModN( + mcuxClSession_Handle_t pSession, + mcuxClHash_Context_t pCtx, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pHashPrefix, + uint32_t hashPrefixLen, + const uint8_t *pSignatureR, + const uint8_t *pPubKey, + const uint8_t *pIn, + uint32_t inSize + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateHashPrefix) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateHashPrefix( + const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint32_t phflag, + mcuxCl_InputBuffer_t pContext, + uint32_t contextLen, + mcuxCl_Buffer_t pHashPrefix + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_PreHashMessage) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_PreHashMessage( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint32_t phflag, + const uint8_t *pIn, + uint32_t inSize, + const uint8_t **pMessage, + uint32_t *messageSize + ); + + +/**********************************************************/ +/* Internal EdDSA types */ +/**********************************************************/ + +/** + * Decode function pointer structure for EdDsa point decoding. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClEcc_EdDSA_DecodePointFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) (*mcuxClEcc_EdDSA_DecodePointFunction_t)(mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pEncPoint)); + +/** + * Domain parameter structure for EdDSA functions. + */ +struct mcuxClEcc_EdDSA_DomainParams +{ + mcuxClEcc_CommonDomainParams_t common; ///< structure containing pointers and lengths for common ECC parameters (see Common ECC Domain parameters) + uint16_t b; ///< Integer satisfying 2^(b-1) > p. EdDSA public keys have exactly b bits, and EdDSA signatures have exactly 2*b bits. + uint16_t c; ///< cofactor exponent + uint16_t t; ///< bit position of MSBit of decoded scalar + uint8_t *pSqrtMinusOne; ///< Pointer to a square root of -1 modulo p which is needed for point decoding in case p = 5 mod 8 (i.e. only needed for Ed25519, not for Ed448) + mcuxClHash_Algo_t algoSecHash; ///< Hash algorithm descriptor of the hash function H() to be used for hashing the private key hash (see Public and private keys) + mcuxClHash_Algo_t algoHash; ///< Hash algorithm descriptor of the hash function H() to be used for hashing the private key, public data and plaintext messages + mcuxClEcc_EdDSA_DecodePointFunction_t pDecodePointFct; ///< Function to be used to decode a point + uint32_t pDecodePoint_FP_FuncId; ///< ID of function to be used to decode a point + const uint32_t *pDomPrefix; ///< The prefix string for dom2 or dom4 + uint32_t domPrefixLen; ///< Length of the prefix string for dom2 or dom4 in bytes +}; + +/** + * EdDSA GenerateKeyPair variant structure. + */ +struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor +{ + uint32_t options; ///< option of GenerateKeyPair, see @ref MCUXCLECC_EDDSA_GENERATEKEYPAIR_OPTION_ + uint8_t *pPrivKeyInput; ///< Pointer to private key input; set to NULL, if MCUXCLECC_EDDSA_GENERATEKEYPAIR_OPTION_GENERATE is chosen +}; + +/** + * EdDSA SignatureProtocol variant structure. + */ +struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor +{ + uint32_t generateOption; ///< option of signature generation + uint32_t verifyOption; ///< option of signature verification + uint32_t phflag; ///< option of pre-hashing + const uint8_t *pHashPrefix; ///< pointer to hash prefix + uint32_t hashPrefixLen; ///< size of hash prefix +}; + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h new file mode 100644 index 000000000..5b6f37373 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP_H_ +#define MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN + */ +#define mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN[mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h new file mode 100644 index 000000000..c81619ca9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP_H_ +#define MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP_H_ + +#include // Exported features flags header +#include + + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common + */ +#define mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common[mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519 + */ +#define mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519[mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519 + */ +#define mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519[mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448 + */ +#define mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448[mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448 + */ +#define mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448_LEN 6u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448[mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448_LEN]; + + +#endif /* MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed25519.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed25519.h new file mode 100644 index 000000000..4891ec0cc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed25519.h @@ -0,0 +1,48 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_Ed25519.h + * @brief internal header of mcuxClEcc Ed25519's functionalities + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_ED25519_H_ +#define MCUXCLECC_EDDSA_INTERNAL_ED25519_H_ + + +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Declaration of the point decoding function on Ed25519 + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_DecodePoint_Ed25519, mcuxClEcc_EdDSA_DecodePointFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_DecodePoint_Ed25519( + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pEncPoint + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_INTERNAL_ED25519_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed448.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed448.h new file mode 100644 index 000000000..6d90a04d5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Ed448.h @@ -0,0 +1,48 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_Ed448.h + * @brief internal header of mcuxClEcc Ed448's functionalities + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_ED448_H_ +#define MCUXCLECC_EDDSA_INTERNAL_ED448_H_ + + +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Declaration of the point decoding function on Ed448 + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_DecodePoint_Ed448, mcuxClEcc_EdDSA_DecodePointFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_DecodePoint_Ed448( + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pEncPoint + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_INTERNAL_ED448_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Hash.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Hash.h new file mode 100644 index 000000000..d52a2b5c6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_Hash.h @@ -0,0 +1,239 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_Hash.h + * @brief internal header for abstracting hash calls in mcuxClEcc EdDSA + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_HASH_H_ +#define MCUXCLECC_EDDSA_INTERNAL_HASH_H_ + +#include // Exported features flags header +#include +#include +#include + +#include + + +/******************************************************************************/ +/* Macro to compute private key hash and store it in PKC workarea. */ +/* Since the parameter b of both Ed25519 and Ed448 is a multiple of 8, */ +/* byte length of private key hash (= 2b/8) can be derived from */ +/* byte length of private key (= b/8). */ +/******************************************************************************/ +#define MCUXCLECC_FP_EDDSA_KEYGEN_HASH_PRIVKEY(pSession, hashAlg, pPrivKey, pPrivKeyHash, privKeyLen) \ + do{ \ + uint32_t outLength = 0u; \ + MCUXCLPKC_WAITFORFINISH(); \ + MCUX_CSSL_FP_FUNCTION_CALL(retHash, \ + mcuxClHash_compute(pSession, \ + hashAlg, \ + (mcuxCl_InputBuffer_t) (pPrivKey), \ + privKeyLen, \ + (mcuxCl_Buffer_t) (pPrivKeyHash), \ + &outLength) ); \ + if (MCUXCLHASH_STATUS_OK != retHash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \ + } while(false) \ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() + + +#define MCUXCLECC_FP_CALLED_EDDSA_KEYGEN_HASH_PRIVKEY \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) + + +/******************************************************************************/ +/* Macros to compute the hash H(prefix || (h_b,...,h_{2b-1}) || m') using */ +/* - the hash function algoSecHash to hash the blocks containing the secret */ +/* (h_b,\dots,h_{2b-1}), and */ +/* - the hash function algoHash to hash the remaining part of the input */ +/* Since the parameter b of both Ed25519 and Ed448 is a multiple of 8, */ +/* byte length of hash (= 2b/8) can be derived from */ +/* byte length of (h_b,...,h_{2b-1}) (= b/8). */ +/******************************************************************************/ +#define MCUXCLECC_FP_EDDSA_SIGN_CALC_SCALAR(pSession, pCtx, algoHash, algoSecHash, pHashPrefix, hashPrefixLen, pPrivKeyHalfHash, privKeyHalfHashLength, pIn, inSize, pOutput) \ + do{ \ + uint32_t outLength = 0u; \ + \ + (void) (algoHash); /* TODO: Use algoHash for blocks with not sensitive data (CLNS-7002) */ \ + \ + /* Initialize the hash context */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retInitHash, \ + mcuxClHash_init(pSession, \ + pCtx, \ + algoSecHash) ); \ + if (MCUXCLHASH_STATUS_OK != retInitHash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with prefix */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess1Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pHashPrefix), \ + hashPrefixLen) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess1Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with (h_b,...,h_{2b-1}) */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess2Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pPrivKeyHalfHash), \ + privKeyHalfHashLength) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess2Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with m' */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess3Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pIn), \ + inSize) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess3Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Finalize hash computation */ \ + MCUXCLPKC_WAITFORFINISH(); \ + MCUX_CSSL_FP_FUNCTION_CALL(retFinishHash, \ + mcuxClHash_finish(pSession, \ + pCtx, \ + pOutput, \ + &outLength) ); \ + if (MCUXCLHASH_STATUS_OK != retFinishHash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \ + } while(false) \ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() + +#define MCUXCLECC_FP_CALLED_EDDSA_SIGN_CALC_SCALAR \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_init), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_finish) + + +/******************************************************************************/ +/* Macro to compute input hash and store it in PKC workarea. */ +/* Since the parameter b of both Ed25519 and Ed448 is a multiple of 8, */ +/* byte length of hash (= 2b/8) can be derived from */ +/* byte length of encoded public key (= b/8). */ +/******************************************************************************/ +#define MCUXCLECC_FP_EDDSA_SIGN_VERIFY_CALC_HASH(pSession, pCtx, hashAlg, pHashPrefix, hashPrefixLen, pSignatureR, signatureRLen, pPubKey, pubKeyLen, pIn, inSize, pOutput) \ + do{ \ + uint32_t outLength = 0u; \ + \ + /* Initialize the hash context */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retInitHash, \ + mcuxClHash_init(pSession, \ + pCtx, \ + hashAlg) ); \ + if (MCUXCLHASH_STATUS_OK != retInitHash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with prefix */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess1Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pHashPrefix), \ + hashPrefixLen) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess1Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with Renc */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess2Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pSignatureR), \ + signatureRLen) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess2Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with Qenc */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess3Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pPubKey), \ + pubKeyLen) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess3Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + /* Update hash context with m' */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retProcess4Hash, \ + mcuxClHash_process(pSession, \ + pCtx, \ + (mcuxCl_InputBuffer_t) (pIn), \ + inSize) ); \ + if (MCUXCLHASH_STATUS_OK != retProcess4Hash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + \ + MCUXCLPKC_WAITFORFINISH(); \ + /* Finalize hash computation */ \ + MCUX_CSSL_FP_FUNCTION_CALL(retFinishHash, \ + mcuxClHash_finish(pSession, \ + pCtx, \ + (mcuxCl_Buffer_t) pOutput, \ + &outLength) ); \ + if (MCUXCLHASH_STATUS_OK != retFinishHash) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, \ + MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + } while(false) + +#define MCUXCLECC_FP_CALLED_EDDSA_SIGN_VERIFY_CALC_HASH \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_init), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_finish) + +#endif /* MCUXCLECC_EDDSA_INTERNAL_HASH_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_PkcWaLayout.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_PkcWaLayout.h new file mode 100644 index 000000000..34d1acb38 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_EdDSA_Internal_PkcWaLayout.h @@ -0,0 +1,88 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_PkcWaLayout.h + * @brief internal header of mcuxClEcc TwEd PKC workarea layout + */ + + +#ifndef MCUXCLECC_EDDSA_INTERNAL_PKCWALAYOUT_H_ +#define MCUXCLECC_EDDSA_INTERNAL_PKCWALAYOUT_H_ + +#include // Exported features flags header +#include + +/**********************************************************/ +/** PKC workarea memory layout used for TwEd functions. */ +/**********************************************************/ +#define TWED_V0 ECC_V0 +#define TWED_V1 ECC_V1 +#define TWED_V2 ECC_V2 +#define TWED_V3 ECC_V3 +#define TWED_V4 ECC_V4 +#define TWED_V5 ECC_V5 +#define TWED_PP_VX1 ECC_V6 +#define TWED_PP_VY1 ECC_V7 +#define TWED_PP_VT1 ECC_V8 +#define TWED_PP_VX0 ECC_V9 +#define TWED_PP_VY0 ECC_VA +#define TWED_PP_VT0 ECC_VB + +#define TWED_VY1 ECC_V8 +#define TWED_VZ1 ECC_V9 +#define TWED_VY2 ECC_VA +#define TWED_VZ2 ECC_VB + +#define TWED_X ECC_COORD00 +#define TWED_Y ECC_COORD01 +#define TWED_Z ECC_COORD02 +#define TWED_T ECC_COORD03 + +#define TWED_ML_Y1 ECC_COORD04 +#define TWED_ML_Z1 ECC_COORD05 +#define TWED_ML_Y2 ECC_COORD06 +#define TWED_ML_Z2 ECC_COORD07 + +#define TWED_PP_X0 ECC_COORD04 +#define TWED_PP_Y0 ECC_COORD05 +#define TWED_PP_T0 ECC_COORD06 +#define TWED_PP_X1 ECC_COORD07 +#define TWED_PP_Y1 ECC_COORD08 +#define TWED_PP_T1 ECC_COORD09 +#define TWED_PP_X2 ECC_COORD10 +#define TWED_PP_Y2 ECC_COORD11 +#define TWED_PP_T2 ECC_COORD12 +#define TWED_PP_X3 ECC_COORD13 +#define TWED_PP_Y3 ECC_COORD14 +#define TWED_PP_T3 ECC_COORD15 +#define TWED_PP_X4 ECC_COORD16 +#define TWED_PP_Y4 ECC_COORD17 +#define TWED_PP_T4 ECC_COORD18 +#define TWED_PP_X5 ECC_COORD19 +#define TWED_PP_Y5 ECC_COORD20 +#define TWED_PP_T5 ECC_COORD21 +#define TWED_PP_X6 ECC_COORD22 +#define TWED_PP_Y6 ECC_COORD23 +#define TWED_PP_T6 ECC_COORD24 +#define TWED_PP_X7 ECC_COORD25 +#define TWED_PP_Y7 ECC_COORD26 +#define TWED_PP_T7 ECC_COORD27 + + +/* Virtual and real buffer amounts definition for EdDSA functions */ +#define ECC_EDDSA_NO_OF_VIRTUALS (ECC_NO_OF_VIRTUALS) +#define ECC_EDDSA_NO_OF_BUFFERS (TWED_PP_T7 + 1u - ECC_EDDSA_NO_OF_VIRTUALS) + + +#endif /* MCUXCLECC_EDDSA_INTERNAL_PKCWALAYOUT_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal.h new file mode 100644 index 000000000..523fe0d4a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal.h @@ -0,0 +1,282 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal.h + * @brief internal header of mcuxClEcc functionalities + */ + + +#ifndef MCUXCLECC_INTERNAL_H_ +#define MCUXCLECC_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* */ +/* Definition of generic CPU and PKC workarea layout */ +/* */ +/**********************************************************/ + +/** + * Generic ECC PKC workarea memory layout. + */ +#define ECC_P 0x00u +#define ECC_N 0x01u +#define ECC_ONE 0x02u +#define ECC_ZERO 0x03u + +#define ECC_V0 0x04u +#define ECC_V1 0x05u +#define ECC_V2 0x06u +#define ECC_V3 0x07u +#define ECC_V4 0x08u +#define ECC_V5 0x09u +#define ECC_V6 0x0Au +#define ECC_V7 0x0Bu +#define ECC_V8 0x0Cu +#define ECC_V9 0x0Du +#define ECC_VA 0x0Eu +#define ECC_VB 0x0Fu + +#define ECC_PS 0x10u +#define ECC_NS 0x11u +#define ECC_CP0 0x12u +#define ECC_CP1 0x13u +#define ECC_PFULL 0x14u +#define ECC_NFULL 0x15u +#define ECC_PQSQR 0x16u +#define ECC_NQSQR 0x17u + +#define ECC_S0 0x18u +#define ECC_T0 0x19u +#define ECC_S1 0x1Au +#define ECC_T1 0x1Bu +#define ECC_S2 0x1Cu +#define ECC_T2 0x1Du +#define ECC_S3 0x1Eu +#define ECC_T3 0x1Fu + +#define ECC_COORD00 0x20u +#define ECC_COORD01 0x21u +#define ECC_COORD02 0x22u +#define ECC_COORD03 0x23u +#define ECC_COORD04 0x24u +#define ECC_COORD05 0x25u +#define ECC_COORD06 0x26u +#define ECC_COORD07 0x27u +#define ECC_COORD08 0x28u +#define ECC_COORD09 0x29u +#define ECC_COORD10 0x2Au +#define ECC_COORD11 0x2Bu +#define ECC_COORD12 0x2Cu +#define ECC_COORD13 0x2Du +#define ECC_COORD14 0x2Eu +#define ECC_COORD15 0x2Fu +#define ECC_COORD16 0x30u +#define ECC_COORD17 0x31u +#define ECC_COORD18 0x32u +#define ECC_COORD19 0x33u +#define ECC_COORD20 0x34u +#define ECC_COORD21 0x35u +#define ECC_COORD22 0x36u +#define ECC_COORD23 0x37u +#define ECC_COORD24 0x38u +#define ECC_COORD25 0x39u +#define ECC_COORD26 0x3Au +#define ECC_COORD27 0x3Bu + +#define ECC_NO_OF_VIRTUALS ECC_PS + + +/** + * CPU workarea layout of ECC APIs. + */ +typedef struct +{ + uint32_t wordNumCpuWa; /* number of words (uint32_t) used in CPU workarea */ + uint32_t wordNumPkcWa; /* number of words (uint32_t) used in PKC workarea */ + mcuxClPkc_State_t pkcStateBackup; + uint32_t pOperands32[]; +} mcuxClEcc_CpuWa_t; + + + +/**********************************************************/ +/* */ +/* Definition of generic ECC domain parameters */ +/* */ +/**********************************************************/ + +typedef struct mcuxClEcc_CommonDomainParams mcuxClEcc_CommonDomainParams_t; + + +/** + * The scalar multiplication function declaration + * and structure containing the function pointer and its associated flow protection ID. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClEcc_ScalarMultFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) (*mcuxClEcc_ScalarMultFunction_t)( + mcuxClSession_Handle_t pSession, ///< Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< Pointer to ECC domain parameters structure + uint8_t iScalar, ///< Pointer table index of scalar buffer in PKC RAM + uint32_t scalarBitLength, ///< Bit length of the scalar + uint32_t options ///< Parameter to pass options + )); +typedef struct +{ + mcuxClEcc_ScalarMultFunction_t pScalarMultFct; ///< scalar multiplication function pointer + uint32_t scalarMultFct_FP_FuncId; ///< FP ID of the function +} mcuxClEcc_ScalarMultFunction_FP_t; + +/** + * Common part of domain parameter structure, shared by all ECC functions. + */ +struct mcuxClEcc_CommonDomainParams +{ + uint16_t byteLenP; ///< byte length of prime p + uint16_t byteLenN; ///< byte length of base point order n + uint8_t *pFullModulusP; ///< pointer to p'||p (in little endian format) + uint8_t *pFullModulusN; ///< pointer to n'||n (in little endian format) + uint8_t *pR2P; ///< pointer to Montgomery parameter R^2 mod p (in little endian format) + uint8_t *pR2N; ///< pointer to Montgomery parameter R^2 mod n (in little endian format) + uint8_t *pCurveParam1; ///< Pointer to first curve parameter (a for Weierstrass and twisted Edwards curves and A for Montgomery curves) + uint8_t *pCurveParam2; ///< Pointer to second curve parameter (b for Weierstrass curves, d for twisted Edwards curves and B for Montgomery curves) + uint8_t *pGx; ///< Pointer to x-coordinate Gx of base point G + uint8_t *pGy; ///< Pointer to y-coordinate Gy of base point G + uint8_t *pPrecPoints; ///< Pointer to pre-computed points for fixed base point scalar multiplication (2^(byteLenN * 4) * G for Weierstrass curves, used in ECDSA signature verification; reserved for other curves) + uint8_t *pLadderConst; ///< Pointer to pre-computed Montgomery ladder constant (in little endian format, used for Montgomery and Twisted Edwards curves) + const mcuxClEcc_ScalarMultFunction_FP_t *pSecFixScalarMultFctFP; ///< Pointer to secure scalar multiplication function and FP ID that shall be used to perform a scalar multiplication lambda*G for secret scalar lambda in {1,...,n-1} and base point G + const mcuxClEcc_ScalarMultFunction_FP_t *pSecVarScalarMultFctFP; ///< Pointer to secure scalar multiplication function and FP ID that shall be used to perform a scalar multiplication lambad*P for secret scalar lambda in {1,...,n-1} and arbitrary point P on the curve + const mcuxClEcc_ScalarMultFunction_FP_t *pPlainFixScalarMultFctFP; ///< Pointer to plain scalar multiplication function and FP ID that shall be used to perform a scalar multiplication lambda*G for non-secret scalar lambda in {1,...,n-1} and base point G + const mcuxClEcc_ScalarMultFunction_FP_t *pPlainVarScalarMultFctFP; ///< Pointer to plain scalar multiplication function and FP ID that shall be used to perform a scalar multiplication lambda*G for non-secret scalar lambda in {1,...,n-1} and arbitrary point P on the curve +}; + + + + +/**********************************************************/ +/* */ +/* Miscellanious definitions */ +/* */ +/**********************************************************/ + +/** + * Macro to provide truncated digest length + */ +#define MCUXCLECC_TRUNCATED_HASH_LEN(hash, max_len) (((hash) < (max_len)) ? (hash) : (max_len)) + +/** + * Options to determine whether scalar multiplication input/output are in affine or projective format. + */ +#define MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT (0x000000A5u) +#define MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT (0x0000005Au) +#define MCUXCLECC_SCALARMULT_OPTION_INPUT_MASK (0x000000FFu) +#define MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_OUTPUT (0x0000C300u) +#define MCUXCLECC_SCALARMULT_OPTION_AFFINE_OUTPUT (0x00003C00u) +#define MCUXCLECC_SCALARMULT_OPTION_OUTPUT_MASK (0x0000FF00u) + +/** + * Define specifying the size of the multiplicative scalar blinding bit size + */ +#define MCUXCLECC_SCALARBLINDING_BITSIZE (32u) +#define MCUXCLECC_SCALARBLINDING_BYTELEN (MCUXCLECC_SCALARBLINDING_BITSIZE / 8u) + + +#define MCUXCLECC_ALIGNED_SIZE(byteLength) \ + ((((byteLength) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t))) * (sizeof(uint32_t))) + + + +/**********************************************************/ +/* */ +/* Internal function declarations */ +/* */ +/**********************************************************/ + +/** Helper macro to get the minimum of two given constants. */ +#define MCUXCLECC_MIN(value0, value1) (((value0) < (value1)) ? (value0) : (value1)) + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_InterleaveScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_InterleaveScalar(uint16_t iScalar, uint32_t scalarBitLength, uint32_t numberOfInterleavings); + +/** Helper macro to call #mcuxClEcc_InterleaveScalar with flow protection. */ +#define MCUXCLECC_FP_INTERLEAVESCALAR(iScalar, bitLenScalar, numberOfInterleavings) \ + do{ \ + MCUX_CSSL_FP_FUNCTION_CALL(retValTemp, mcuxClEcc_InterleaveScalar(iScalar, bitLenScalar, numberOfInterleavings)); \ + (void) retValTemp; /* Checking is unnecessary, because it always returns OK. */ \ + } while (false) + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_InterleaveTwoScalars) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_InterleaveTwoScalars(uint16_t iScalar0_iScalar1, uint32_t scalarBitLength); + +/** Helper macro to call #mcuxClEcc_InterleaveTwoScalars with flow protection. */ +#define MCUXCLECC_FP_INTERLEAVETWOSCALARS(iS0_iS1, bitLenScalar) \ + do{ \ + MCUX_CSSL_FP_FUNCTION_CALL(retValTemp, mcuxClEcc_InterleaveTwoScalars(iS0_iS1, bitLenScalar)); \ + (void) retValTemp; /* Checking is unnecessary, because it always returns OK. */ \ + } while (false) + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_GenerateMultiplicativeBlinding) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_GenerateMultiplicativeBlinding( + mcuxClSession_Handle_t pSession, + uint8_t scalarIndex + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_BlindedScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_BlindedScalarMult( + mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pCommonDomainParams + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pCommonDomainParams, + uint8_t noOfBuffers + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_RecodeAndReorderScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_RecodeAndReorderScalar( + mcuxClSession_Handle_t pSession, + uint8_t scalarIndex, + uint8_t f, + uint32_t scalarBitLength + ); + +/** Helper macro to call #mcuxClEcc_RecodeAndReorderScalar with flow protection. */ +#define MCUXCLECC_FP_RECODEANDREORDERSCALAR(scalarIndex, f, scalarBitLength) \ + do{ \ + MCUX_CSSL_FP_FUNCTION_CALL(retValTemp, mcuxClEcc_RecodeAndReorderScalar(pSession, scalarIndex, f, scalarBitLength)); \ + (void) retValTemp; /* Checking is unnecessary, because it always returns OK. */ \ + } while (false) + + + + #define MCUXCLECC_HANDLE_HW_UNAVAILABLE(retCodeReceived, callerName) do{} while(false) + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Convert_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Convert_FUP.h new file mode 100644 index 000000000..289b479ed --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Convert_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Convert_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_INTERNAL_CONVERT_FUP_H_ +#define MCUXCLECC_INTERNAL_CONVERT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClEcc_FUP_ConvertHomToAffine + */ +#define mcuxClEcc_FUP_ConvertHomToAffine_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_ConvertHomToAffine[mcuxClEcc_FUP_ConvertHomToAffine_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_INTERNAL_CONVERT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Interleave_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Interleave_FUP.h new file mode 100644 index 000000000..9d0cb2926 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Interleave_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Interleave_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_INTERNAL_INTERLEAVE_FUP_H_ +#define MCUXCLECC_INTERNAL_INTERLEAVE_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClEcc_FUP_Interleave + */ +#define mcuxClEcc_FUP_Interleave_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Interleave[mcuxClEcc_FUP_Interleave_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_INTERNAL_INTERLEAVE_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_PointComparison_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_PointComparison_FUP.h new file mode 100644 index 000000000..e88aad224 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_PointComparison_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_PointComparison_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP_H_ +#define MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_PointComparisonHom + */ +#define mcuxClEcc_FUP_PointComparisonHom_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_PointComparisonHom[mcuxClEcc_FUP_PointComparisonHom_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Random.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Random.h new file mode 100644 index 000000000..4c21791e5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_Random.h @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Random.h + * @brief internal header for abstracting random access in mcuxClEcc + */ + + +#ifndef MCUXCLECC_INTERNAL_RANDOM_H_ +#define MCUXCLECC_INTERNAL_RANDOM_H_ + +#include // Exported features flags header +#include + + +/******************************************************************************/ +/* Macro to generate high-quality random number in PKC workarea. */ +/******************************************************************************/ +#if defined(MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND) +#include + +#define MCUXCLECC_FP_RANDOM_HQRNG_PKCWA(callerID, pSession, pOutPKCWA, length) \ + do{ \ + /* Generate random number in CPU workarea. */ \ + const uint32_t tempSizeWord = ((length) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); \ + uint8_t * pTemp = (uint8_t*) mcuxClSession_allocateWords_cpuWa(pSession, tempSizeWord); \ + if (NULL == pTemp) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(callerID, MCUXCLECC_STATUS_FAULT_ATTACK); \ + } \ + MCUX_CSSL_FP_FUNCTION_CALL(ret_random, mcuxClRandom_generate(pSession, pTemp, length)); \ + if (MCUXCLRANDOM_STATUS_OK != ret_random) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(callerID, MCUXCLECC_STATUS_RNG_ERROR); \ + } \ + /* Copy generated random numbers to PKC workarea. */ \ + MCUXCLMEMORY_FP_MEMORY_COPY(pOutPKCWA, pTemp, length); \ + \ + /* Release temporary buffer. */ \ + mcuxClSession_freeWords_cpuWa(pSession, tempSizeWord); \ + } while(false) + +#define MCUXCLECC_FP_CALLED_RANDOM_HQRNG_PKCWA \ + MCUX_CSSL_FP_CONDITIONAL(true, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) ) +#else +#define MCUXCLECC_FP_RANDOM_HQRNG_PKCWA(callerID, pSession, pOutPKCWA, length) \ + do{ \ + MCUX_CSSL_FP_FUNCTION_CALL(ret_random, mcuxClRandom_generate(pSession, pOutPKCWA, length)); \ + if (MCUXCLRANDOM_STATUS_OK != ret_random) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(callerID, MCUXCLECC_STATUS_RNG_ERROR); \ + } \ + } while(false) + +#define MCUXCLECC_FP_CALLED_RANDOM_HQRNG_PKCWA MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) +#endif /* MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ + + +#endif /* MCUXCLECC_INTERNAL_RANDOM_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SecurePointSelect.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SecurePointSelect.h new file mode 100644 index 000000000..f168720fa --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SecurePointSelect.h @@ -0,0 +1,123 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_SecurePointSelect.h + * @brief Internal header of mcuxClEcc SecurePointSelect macro + */ + + +#ifndef MCUXCLECC_INTERNAL_SECUREPOINTSELECT_H_ +#define MCUXCLECC_INTERNAL_SECUREPOINTSELECT_H_ + +#include +#include +#include // Exported features flags header + +/** + * This macro securely loads ofsP0 and ofsP1 from pOps[] table. + * When b = "the bit at bitOffset of (scalarW0 XOR scalarW1)" = 0, + * it returns ofsP0 = pOps_[iBase + 1] || pOps_[iBase], and + * ofsP1 = pOps_[iBase + 3] || pOps_[iBase + 2]; + * when b = 1, + * it returns ofsP0 = pOps_[iBase + 3] || pOps_[iBase + 2], and + * ofsP1 = pOps_[iBase + 1] || pOps_[iBase]. + */ +#if defined(__RISCV32) + +#define CREATE_ROR_TEMP \ + uint32_t temp3 +#define ALLOCATE_ROR_TEMP \ + , [tmp3] "=&r" (temp3) +#define ROTATE_RIGHT(dest, src, bitsToRotate, tmp) \ + "neg "#tmp", "#bitsToRotate"\n"\ + "sll "#tmp", "#src", "#tmp"\n"\ + "srl "#dest", "#src", "#bitsToRotate"\n"\ + "or "#dest", "#dest", "#tmp"\n" + +#define MCUXCLECC_SECUREPOINTSELECT(ofsP0_, ofsP1_, pOps_, iBase, scalarW0_, scalarW1_, randomWord_, bitOffset_) \ + do{ \ + uint32_t temp0; \ + uint32_t temp1 = (bitOffset_); \ + uint32_t temp2 = (randomWord_); \ + CREATE_ROR_TEMP; \ + __asm volatile ( \ + "addi %[tmp1], %[tmp1], -2\n"\ + ROTATE_RIGHT(%[tmp0], %[s0], %[tmp1], %[tmp3]) /* t0 = ( s0 .... ) || b0 || .. */\ + "andi %[tmp2], %[tmp2], -5\n" /* t2 = ( rand .. ) || 0 || .. */\ + "xor %[tmp0], %[tmp0], %[tmp2]\n" /* t0 = ( s0^rand ) || b0 || .. */\ + ROTATE_RIGHT(%[tmp1], %[s1], %[tmp1], %[tmp3]) /* t1 = ( s1 .... ) || b1 || .. */\ + "xor %[tmp0], %[tmp0], %[tmp1]\n" /* t0 = ( s^rand ) || b || .. */\ + "or %[tmp0], %[tmp0], %[tmp2]\n" /* t0 = ( s|rand ) || b || .. */\ + "sub %[tmp1], %[pOps], %[tmp2]\n"\ + "addi %[tmp2], %[tmp2], 4\n" /* t2 = ( rand .. ) || 1 || .. */\ + "and %[tmp2], %[tmp2], %[tmp0]\n" /* t2 = ( rand .. ) || b || .. */\ + "add %[tmp0], %[tmp1], %[tmp2]\n" /* update address offset */\ + "lw %[tmp0], %[ofsX0](%[tmp0])\n"\ + "xori %[tmp2], %[tmp2], 4\n" /* t2 = ( rand .. ) || 1-b || .. */\ + "add %[tmp1], %[tmp1], %[tmp2]\n" /* update address offset */\ + "lw %[tmp1], %[ofsX0](%[tmp1])\n"\ + : [tmp0] "=&r" (temp0), \ + [tmp1] "+&r" (temp1), \ + [tmp2] "+&r" (temp2) \ + ALLOCATE_ROR_TEMP \ + : [pOps] "r" (pOps_), \ + [s0] "r" (scalarW0_), \ + [s1] "r" (scalarW1_), \ + [ofsX0] "i" ((iBase) * 2u) \ + ); \ + (ofsP0_) = temp0; \ + (ofsP1_) = temp1; \ + } while (false) + +#elif defined(ICCARM_ARMCC_GNUC) + +#define MCUXCLECC_SECUREPOINTSELECT(ofsP0_, ofsP1_, pOps_, iBase, scalarW0_, scalarW1_, randomWord_, bitOffset_) \ + do{ \ + uint32_t temp0; \ + uint32_t temp1 = (bitOffset_); \ + uint32_t temp2 = (randomWord_); \ + __asm volatile ( \ + "SUBS %[tmp1], %[tmp1], #2\n"\ + "ROR %[tmp0], %[s0], %[tmp1]\n" /* t0 = ( s0 .... ) || b0 || .. */\ + "BIC %[tmp2], %[tmp2], #4\n" /* t2 = ( rand .. ) || 0 || .. */\ + "EORS %[tmp0], %[tmp0], %[tmp2]\n" /* t0 = ( s0^rand ) || b0 || .. */\ + "ROR %[tmp1], %[s1], %[tmp1]\n" /* t1 = ( s1 .... ) || b1 || .. */\ + "EORS %[tmp0], %[tmp0], %[tmp1]\n" /* t0 = ( s^rand ) || b || .. */\ + "ORRS %[tmp0], %[tmp0], %[tmp2]\n" /* t0 = ( s|rand ) || b || .. */\ + "SUBS %[tmp1], %[pOps], %[tmp2]\n"\ + "ADDS %[tmp2], %[tmp2], #4\n" /* t2 = ( rand .. ) || 1 || .. */\ + "ADDS %[tmp1], %[tmp1], %[ofsX0]\n"\ + "ANDS %[tmp2], %[tmp2], %[tmp0]\n" /* t2 = ( rand .. ) || b || .. */\ + "LDR %[tmp0], [%[tmp1], %[tmp2]]\n"\ + "EOR %[tmp2], %[tmp2], #4\n" /* t2 = ( rand .. ) || 1-b || .. */\ + "LDR %[tmp1], [%[tmp1], %[tmp2]]\n"\ + : [tmp0] "=&r" (temp0), \ + [tmp1] "+&r" (temp1), \ + [tmp2] "+&r" (temp2) \ + : [pOps] "r" (pOps_), \ + [s0] "r" (scalarW0_), \ + [s1] "r" (scalarW1_), \ + [ofsX0] "i" ((iBase) * 2u) \ + : "cc" \ + ); \ + (ofsP0_) = temp0; \ + (ofsP1_) = temp1; \ + } while (false) + +#else + #error Unsupported compiler. The above section must be manually adapted to support the inline assembly syntax. +#endif + + +#endif /* MCUXCLECC_INTERNAL_SECUREPOINTSELECT_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SetupEnvironment_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SetupEnvironment_FUP.h new file mode 100644 index 000000000..6d90f096e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_SetupEnvironment_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_SetupEnvironment_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP_H_ +#define MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_SetupEnvironment_ClearBuffers + */ +#define mcuxClEcc_FUP_SetupEnvironment_ClearBuffers_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SetupEnvironment_ClearBuffers[mcuxClEcc_FUP_SetupEnvironment_ClearBuffers_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_UPTRT_access.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_UPTRT_access.h new file mode 100644 index 000000000..f8f392487 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Internal_UPTRT_access.h @@ -0,0 +1,85 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_UPTRT_access.h + * @brief Internal header with helper macros for UPTRT access + */ + + +#ifndef MCUXCLECC_INTERNAL_UPTRT_ACCESS_H_ +#define MCUXCLECC_INTERNAL_UPTRT_ACCESS_H_ + +#include // Exported features flags header + +/**********************************************************/ +/* Helper macros for accessing UPTRT table */ +/**********************************************************/ +/** Macro for reading 2 offsets in UPTRT table. + * [in] pOps: pointer to 16-bit offset table. This pointer must be 32-bit aligned; + * [in] idx0, idx1: compile-time-constant indices of offsets in the table. + * @attention not compile-time-constant indices will cause extra code size. + * @attention if the two offsets are not in the same CPU word, this macro might cause extra code size. + */ +#define MCUXCLECC_LOAD_2OFFSETS(pOps, idx0, idx1) \ + ( \ + ((0u == ((idx0) & (0x01u))) && ((idx1) == ((idx0) + (0x01u)))) ? \ + (((uint32_t *) (pOps))[(idx0) / 2u]) : \ + ((uint32_t) ((uint16_t *) (pOps))[idx0] | ((uint32_t) ((uint16_t *) (pOps))[idx1] << 16)) \ + ) + +/** Macro for writing 2 offsets to UPTRT table. + * [in] pOps: pointer to 16-bit offset table. This pointer must be 32-bit aligned; + * [in] idx0, idx1: compile-time-constant indices of offsets in the table. + * @attention not compile-time-constant indices will cause extra code size. + * @attention if the two offsets are not in the same CPU word, this macro might cause extra code size. + */ +#define MCUXCLECC_STORE_2OFFSETS(pOps, idx0, idx1, ofs1_ofs0) \ + do{ \ + if ( (0u == ((idx0) & (0x01u))) && ((idx1) == ((idx0) + (0x01u))) ) \ + { \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 - Rule 11.3 - UPTR table is 32-bit aligned in ECC component"); \ + ((uint32_t *) (pOps))[(idx0) / 2u] = (ofs1_ofs0); \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); \ + } \ + else \ + { MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - Cast to 16-bit pointer table") \ + ((uint16_t *) (pOps))[idx0] = (uint16_t) ((ofs1_ofs0) & 0xFFFFu); \ + ((uint16_t *) (pOps))[idx1] = (uint16_t) ((ofs1_ofs0) >> 16); \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() \ + } \ + } while(false) + +/** Macro for copying 2 offsets in UPTRT table. + * [in] pOps: pointer to 16-bit offset table. This pointer must be 32-bit aligned; + * [in] dIdx0, dIdx1, sIdx0, sIdx1: compile-time-constant indices of offsets in the table. + * @attention not compile-time-constant indices will cause extra code size. + */ +#define MCUXCLECC_COPY_2OFFSETS(pOps, dIdx0, dIdx1, sIdx0, sIdx1) \ + do{ \ + if ( (0u == ((dIdx0) & (0x01u))) \ + && ((dIdx1) == ((dIdx0) + (0x01u))) \ + && (0u == ((sIdx0) & (0x01u))) \ + && ((sIdx1) == ((sIdx0) + (0x01u))) ) \ + { /* MISRA Ex. 9 - Rule 11.3 - UPTR table is 32-bit aligned in ECC component */ \ + ((uint32_t *) (pOps))[(dIdx0) / 2u] = ((uint32_t *) (pOps))[(sIdx0) / 2u]; \ + } \ + else \ + { MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - Cast to 16-bit pointer table") \ + ((uint16_t *) (pOps))[dIdx0] = ((uint16_t *) (pOps))[sIdx0]; \ + ((uint16_t *) (pOps))[dIdx1] = ((uint16_t *) (pOps))[sIdx1]; \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() \ + } \ + } while (false) + +#endif /* MCUXCLECC_INTERNAL_UPTRT_ACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal.h new file mode 100644 index 000000000..d80d1d727 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal.h @@ -0,0 +1,110 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal.h + * @brief internal header of mcuxClEcc MontDh functionalities + */ + + +#ifndef MCUXCLECC_MONT_INTERNAL_H_ +#define MCUXCLECC_MONT_INTERNAL_H_ + +#include + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Internal return codes for MontDH functions */ +/**********************************************************/ +// None + + +/**********************************************************/ +/* Internal MontDH defines */ +/**********************************************************/ + +/** Use 4-byte (32-bit) multiplicative blinding in MontDh. */ +#define MCUXCLECC_MONTDH_SCALAR_BLINDING_BYTELEN 4u + + +/**********************************************************/ +/* Internal MontDH types */ +/**********************************************************/ + +/** + * Domain parameter structure for MontDh functions. + */ +struct mcuxClEcc_MontDH_DomainParams +{ + mcuxClEcc_CommonDomainParams_t common; ///< structure containing pointers and lengths for common ECC parameters (see Common ECC Domain parameters) + uint16_t c; ///< cofactor exponent + uint16_t t; ///< bit position of MSBit of decoded scalar +}; + + + +/**********************************************************/ +/* Declarations for internal MontDH functions */ +/**********************************************************/ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_MontDH_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_MontDH_DomainParams_t *pDomainParams, + uint8_t noOfBuffers + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_MontDH_DecodeScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_DecodeScalar( + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_MontDH_DecodeCoordinate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_DecodeCoordinate( + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters, + const uint8_t *pCoordinateEnc + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_SecureScalarMult_XZMontLadder( + mcuxClSession_Handle_t pSession, + uint8_t iScalar, + uint32_t scalarBitLength, + uint32_t optionAffineOrProjective + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_MontDH_X) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_X( + mcuxClSession_Handle_t pSession, + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters, + const uint8_t *pCoordinateUEnc + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_MONT_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_MontDhX_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_MontDhX_FUP.h new file mode 100644 index 000000000..06241935a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_MontDhX_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_MontDhX_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP_H_ +#define MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include // Exported features flags header +#include + +/** + * FUP program declaration mcuxClEcc_FUP_MontDhDecodeScalar + */ +#define mcuxClEcc_FUP_MontDhDecodeScalar_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhDecodeScalar[mcuxClEcc_FUP_MontDhDecodeScalar_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_MontDhX_CalcAffineX + */ +#define mcuxClEcc_FUP_MontDhX_CalcAffineX_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhX_CalcAffineX[mcuxClEcc_FUP_MontDhX_CalcAffineX_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_PkcWaLayout.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_PkcWaLayout.h new file mode 100644 index 000000000..e5d11c1f6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_PkcWaLayout.h @@ -0,0 +1,56 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_PkcWaLayout.h + * @brief internal header of mcuxClEcc MontDh PKC workarea layout + */ + + +#ifndef MCUXCLECC_MONT_INTERNAL_PKCWALAYOUT_H_ +#define MCUXCLECC_MONT_INTERNAL_PKCWALAYOUT_H_ + +#include // Exported features flags header +#include + + +/**********************************************************/ +/** PKC workarea memory layout used for MontDh functions. */ +/**********************************************************/ +#define MONT_V0 ECC_V0 +#define MONT_V1 ECC_V1 +#define MONT_V2 ECC_V2 +#define MONT_V3 ECC_V3 +#define MONT_V4 ECC_V4 +#define MONT_V5 ECC_V5 +#define MONT_V6 ECC_V6 +#define MONT_V7 ECC_V7 + +#define MONT_VX1 ECC_V8 +#define MONT_VZ1 ECC_V9 +#define MONT_VX2 ECC_VA +#define MONT_VZ2 ECC_VB + +#define MONT_X0 ECC_COORD00 +#define MONT_Z0 ECC_COORD01 +#define MONT_X1 ECC_COORD02 +#define MONT_Z1 ECC_COORD03 +#define MONT_X2 ECC_COORD04 +#define MONT_Z2 ECC_COORD05 + +/* Virtual and real buffer amounts definition for Mont functions */ +#define ECC_MONTDH_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_MONTDH_NO_OF_BUFFERS (MONT_Z2 + 1u - ECC_MONTDH_NO_OF_VIRTUALS) + + +#endif /* MCUXCLECC_MONT_INTERNAL_PKCWALAYOUT_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h new file mode 100644 index 000000000..985dede3f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP_H_ +#define MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep + */ +#define mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep_Affine_LEN 19u +#define mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep_Projective_LEN 22u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep[mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep_Projective_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal.h new file mode 100644 index 000000000..2962b53d2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal.h @@ -0,0 +1,176 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal.h + * @brief internal header of mcuxClEcc Twisted Edward's functionalities + */ + + +#ifndef MCUXCLECC_TWED_INTERNAL_H_ +#define MCUXCLECC_TWED_INTERNAL_H_ + +#include + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Internal return codes of mcuxClEcc_TwEd */ +/**********************************************************/ + +// None + + +/**********************************************************/ +/* Internal mcuxClEcc_TwEd function defines */ +/**********************************************************/ + +#define MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE (4u) +#define MCUXCLECC_TWED_FIXSCALARMULT_DIGITMASK (0xFu) +#define MCUXCLECC_TWED_FIXSCALARMULT_NOOFPRECPOINTS (8u) + + +/**********************************************************/ +/* Internal mcuxClEcc_TwEd functions */ +/**********************************************************/ + +/** + * Declaration of function to perform plain (not protected against side-channel attacks) scalar multiplication with variable input point + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PlainVarScalarMult, mcuxClEcc_ScalarMultFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainVarScalarMult( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< [in] pDomainParams Pointer to ECC common domain parameters structure + uint8_t iScalar, ///< [in] iScalar Pointer table index of secret scalar lambda + uint32_t scalarBitLength, ///< [in] scalarBitLength Bit length of the scalar + uint32_t options ///< [in] options Parameter to pass options + ); + +/** + * Declaration of the mixed point addition function + * and structure containing the function pointer and its associated flow protection ID. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClEcc_TwEd_MixedPointAddFunction_t, + typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) (*mcuxClEcc_TwEd_MixedPointAddFunction_t)(void)); +typedef struct +{ + mcuxClEcc_TwEd_MixedPointAddFunction_t pMixedPointAddFct; ///< mixed point addition function + uint32_t mixedPointAddFct_FP_FuncId; ///< FP ID of the function +} mcuxClEcc_TwEd_MixedPointAddFunction_FP_t; + +/** + * Declaration of the point doubling function + * and structure containing the function pointer and its associated flow protection ID. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClEcc_TwEd_PointDoubleFunction_t, + typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) (*mcuxClEcc_TwEd_PointDoubleFunction_t)(void)); +typedef struct +{ + mcuxClEcc_TwEd_PointDoubleFunction_t pPointDoubleFct; ///< point doubling function + uint32_t pointDoubleFct_FP_FuncId; ///< FP ID of the function +} mcuxClEcc_TwEd_PointDoubleFunction_FP_t; + +/** + * Declaration of the comb method pointer selection function + * and structure containing the function pointer and its associated flow protection ID. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClEcc_TwEd_PtrSelectFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) (*mcuxClEcc_TwEd_PtrSelectFunction_t)( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + uint32_t scalarWord, ///< [in] scalarWord CPU word containing the scalar bits to be processed + uint8_t scalarOffset ///< [in] scalarDigitOffset Offset in scalarWord of scalar bit(s) to be processed +)); +typedef struct +{ + mcuxClEcc_TwEd_PtrSelectFunction_t pPtrSelectFct; ///< Pointer selection function + uint32_t ptrSelectFct_FP_FuncId; ///< FP ID of the function +} mcuxClEcc_TwEd_PtrSelectFunction_FP_t; + +/** + * Declaration of the plain (not protected against side-channel attacks) comb method pointer selection function + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PlainPtrSelectComb, mcuxClEcc_TwEd_PtrSelectFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainPtrSelectComb( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + uint32_t scalarWord, ///< [in] scalarWord CPU word containing the digit (i3i2i1i0)_2 + uint8_t scalarDigitOffset ///< [in] scalarDigitOffset Bit offset in scalarWord of the digit (i3i2i1i0)_2 +); + +/** + * Declaration of the plain (not protected against side-channel attacks) Montgomery ladder pointer selection function + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PlainPtrSelectML, mcuxClEcc_TwEd_PtrSelectFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainPtrSelectML( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + uint32_t scalarWord, ///< [in] scalarWord CPU word containing the current scalar bit b + uint8_t scalarBitOffset ///< [in] scalarBitOffset Offset in scalarWord of scalar bit b +); + +/** + * Declaration of function to import, convert and validate pre-computed points + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PrecPointImportAndValidate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PrecPointImportAndValidate( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + uint8_t iDst, ///< [in] iDst Pointer table index of buffer to which the x-coordinate shall be copied + uint8_t *pSrc, ///< [in] pSrc Pointer to the pre-computed point x-coordinate + uint16_t byteLenP ///< [in] byteLenP Byte length of P +); + +/** + * Declaration of function to perform scalar multiplication with the base point + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_FixScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_FixScalarMult( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< [in] pDomainParams Pointer to ECC common domain parameters structure + uint8_t iScalar, ///< [in] iScalar Pointer table index of secret scalar lambda + uint32_t scalarBitLength, ///< [in] scalarBitLength Bit length of the scalar; must be a multiple of 4 + const mcuxClEcc_TwEd_MixedPointAddFunction_FP_t *pMixedPointAddFctFP,///< [in] pMixedPointAddFct Curve dependent function to perform mixed point addition on twisted Edwards curve + const mcuxClEcc_TwEd_PointDoubleFunction_FP_t *pPointDoubleFctFP, ///< [in] pPointDoubleFct Curve dependent function to perform point doubling on twisted Edwards curve + const mcuxClEcc_TwEd_PtrSelectFunction_FP_t *pPtrSelectFctFP ///< [in] pPtrSelectFct Function to select pre-computed point to be added + ); + + +/** + * Declaration of function to perform scalar multiplication with variable input point + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_VarScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_VarScalarMult( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< [in] pDomainParams Pointer to ECC common domain parameters structure + uint8_t iScalar, ///< [in] iScalar Pointer table index of secret scalar lambda + uint32_t scalarBitLength, ///< [in] scalarBitLength Bit length of the scalar + uint32_t options, ///< [in] options Parameter to pass options + const mcuxClEcc_TwEd_PtrSelectFunction_FP_t *pPtrSelectFctFP ///< [in] pPtrSelectFct Function to select accumulated ladder points + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_TWED_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519.h new file mode 100644 index 000000000..6fb2f731e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519.h @@ -0,0 +1,63 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_Ed25519.h + * @brief internal header of mcuxClEcc Twisted Edward's functionalities + */ + + +#ifndef MCUXCLECC_TWED_INTERNAL_ED25519_H_ +#define MCUXCLECC_TWED_INTERNAL_ED25519_H_ + + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + +/** + * Declaration of the point doubling function on Ed25519 + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PointDoubleEd25519, mcuxClEcc_TwEd_PointDoubleFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PointDoubleEd25519(void); + +/** + * Declaration of the mixed point addition function on Ed25519 + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_MixedPointAddEd25519, mcuxClEcc_TwEd_MixedPointAddFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_MixedPointAddEd25519(void); + +/** + * Declaration of function to perform plain (not protected against side-channel attacks) scalar multiplication with the base point on Ed25519 + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PlainFixScalarMult25519, mcuxClEcc_ScalarMultFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainFixScalarMult25519( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< [in] pDomainParams Pointer to ECC common domain parameters structure + uint8_t iScalar, ///< [in] iScalar Pointer table index of secret scalar lambda + uint32_t scalarBitLength, ///< [in] scalarBitLength Bit length of the scalar; must be a multiple of 4 + uint32_t options ///< [in] options Parameter to pass options +); + + +#endif /* MCUXCLECC_TWED_INTERNAL_ED25519_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519_FUP.h new file mode 100644 index 000000000..52ba66098 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_Ed25519_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_Ed25519_FUP.h + * @brief defines FUP programs byte arrays for twisted Edwards curve Ed25519 + */ + + +#ifndef MCUXCLECC_TWED_INTERNAL_ED25519_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_ED25519_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_TwEd_PointDoubleEd25519 + */ +#define mcuxClEcc_FUP_TwEd_PointDoubleEd25519_Len 16u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointDoubleEd25519[mcuxClEcc_FUP_TwEd_PointDoubleEd25519_Len]; + +/** + * FUP program declaration mcuxClEcc_FUP_TwEd_MixedPointAddEd25519 + */ +#define mcuxClEcc_FUP_TwEd_MixedPointAddEd25519_Len 19u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_MixedPointAddEd25519[mcuxClEcc_FUP_TwEd_MixedPointAddEd25519_Len]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_TWED_INTERNAL_ED25519_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h new file mode 100644 index 000000000..81e7876ae --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_EDDSA_POINTSUBTRACTION_FUP_H_ +#define MCUXCLECC_EDDSA_POINTSUBTRACTION_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_TwEd_PointSubtraction + */ +#define mcuxClEcc_FUP_TwEd_PointSubtraction_LEN 22u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointSubtraction[mcuxClEcc_FUP_TwEd_PointSubtraction_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_EDDSA_POINTSUBTRACTION_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h new file mode 100644 index 000000000..67c5586b0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PointValidation_FUP.h + * @brief defines FUP programs byte arrays for twisted Edwards curves + */ + + +#ifndef MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_TwEd_PointValidation + */ +#define mcuxClEcc_FUP_TwEd_PointValidation_Len 14u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointValidation[mcuxClEcc_FUP_TwEd_PointValidation_Len]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h new file mode 100644 index 000000000..3f8fff2b1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep + */ +#define mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep_LEN 29u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep[mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate + */ +#define mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate_LEN 15u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate[mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_DecodePoint_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_DecodePoint_FUP.h new file mode 100644 index 000000000..6ff0542de --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_DecodePoint_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_DecodePoint_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIERECC_INTERNAL_DECODEPOINT_FUP_H_ +#define MCUXCLECC_WEIERECC_INTERNAL_DECODEPOINT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_DecodePoint_SEC_CalcAlphaAndExponent + */ +#define mcuxClEcc_FUP_DecodePoint_SEC_CalcAlphaAndExponent_Len 9u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_DecodePoint_SEC_CalcAlphaAndExponent[mcuxClEcc_FUP_DecodePoint_SEC_CalcAlphaAndExponent_Len]; + +/** + * FUP program declaration mcuxClEcc_FUP_DecodePoint_SEC_VerifyBeta + */ +#define mcuxClEcc_FUP_DecodePoint_SEC_VerifyBeta_Len 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_DecodePoint_SEC_VerifyBeta[mcuxClEcc_FUP_DecodePoint_SEC_VerifyBeta_Len]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIERECC_INTERNAL_DECODEPOINT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.h new file mode 100644 index 000000000..47697805f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.h @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_GenerateDomainParams.h + * @brief internal header of mcuxClEcc functionalities related to function MCUXCLECC_CUSTOMPARAMS + */ + + +#ifndef MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_H_ +#define MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_H_ + + +#include + + +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_PFULL (0u) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_NFULL(byteLenP) ((byteLenP) + MCUXCLPKC_WORDSIZE) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_R2P(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_NFULL(byteLenP) + (byteLenN) + MCUXCLPKC_WORDSIZE) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_R2N(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_R2P(byteLenP, byteLenN) + (byteLenP)) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_CP1(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_R2N(byteLenP, byteLenN) + (byteLenN)) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_CP2(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_CP1(byteLenP, byteLenN) + (byteLenP)) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_GX(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_CP2(byteLenP, byteLenN) + (byteLenP)) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_GY(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_GX(byteLenP, byteLenN) + (byteLenP)) +#define MCUXCLECC_CUSTOMPARAMS_OFFSET_PP(byteLenP, byteLenN) (MCUXCLECC_CUSTOMPARAMS_OFFSET_GY(byteLenP, byteLenN) + (byteLenP)) + +#define MCUXCLECC_CUSTOMPARAMS_SIZE_FIXED (sizeof(mcuxClEcc_Weier_DomainParams_t) + 2u * MCUXCLPKC_WORDSIZE) +#define MCUXCLECC_CUSTOMPARAMS_SIZE_NO_OF_PLEN (8u /* PFULL, R2P, CP1, CP2, GX, GY, PP */) +#define MCUXCLECC_CUSTOMPARAMS_SIZE_NO_OF_NLEN (2u /* NFULL, R2N */) + + +#endif /* MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h new file mode 100644 index 000000000..efd7fa7fd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h @@ -0,0 +1,45 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP +#define MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P + */ +#define mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P_Len 4u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P[mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P_Len]; + +/** + * FUP program declaration mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR + */ +#define mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR_Len 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR[mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR_Len]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal.h new file mode 100644 index 000000000..2c9da7c98 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal.h @@ -0,0 +1,226 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal.h + * @brief internal header for short Weierstrass curves + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_H_ +#define MCUXCLECC_WEIER_INTERNAL_H_ + + +#include +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Domain parameter structure for ECC functions based on Weierstrass functions. + */ +struct mcuxClEcc_Weier_DomainParams +{ + mcuxClEcc_CommonDomainParams_t common; ///< structure containing pointers and lengths for common ECC parameters (see Common ECC Domain parameters) +}; + + + +/**********************************************************/ +/* Internal return codes of mcuxClEcc */ +/**********************************************************/ + +#define MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK ((mcuxClEcc_Status_t) 0x55AAE817u) + +/* Rule of ECC return codes: + * All return codes are of the format: 0x55XXYYTT + * API : XX = 55 + * Internal : XX = AA + * HammingWeight(YY) = HammingWeight(TT) = 4, according to coding guidelines + * YY needs to be a balanced byte, and TT = ~YY + * + * General OK : YYTT = 5555 + * Fault Attack : YYTT = F00F + */ + + +/**********************************************************/ +/** PKC workarea memory layout for Weierstrass functions. */ +/**********************************************************/ +#define WEIER_VX0 ECC_V0 +#define WEIER_VY0 ECC_V1 +#define WEIER_VZ0 ECC_V2 +#define WEIER_VZ ECC_V3 + +#define WEIER_VX1 ECC_V4 +#define WEIER_VY1 ECC_V5 +#define WEIER_VT2 ECC_V6 +#define WEIER_VT3 ECC_V7 + +#define WEIER_VX2 ECC_V8 +#define WEIER_VY2 ECC_V9 +#define WEIER_VZ2 ECC_VA +#define WEIER_VT ECC_VB + +#define WEIER_A ECC_CP0 +#define WEIER_B ECC_CP1 + +#define WEIER_XA ECC_COORD00 +#define WEIER_YA ECC_COORD01 +#define WEIER_ZA ECC_COORD02 +#define WEIER_Z ECC_COORD03 +#define WEIER_X0 ECC_COORD04 +#define WEIER_Y0 ECC_COORD05 +#define WEIER_X1 ECC_COORD06 +#define WEIER_Y1 ECC_COORD07 +#define WEIER_X2 ECC_COORD08 +#define WEIER_Y2 ECC_COORD09 +#define WEIER_X3 ECC_COORD10 +#define WEIER_Y3 ECC_COORD11 + +#define ECC_KEYGEN_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_KEYGEN_NO_OF_BUFFERS (WEIER_Y1 + 1u - ECC_KEYGEN_NO_OF_VIRTUALS) + +#define ECC_SIGN_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_SIGN_NO_OF_BUFFERS (WEIER_Y1 + 1u - ECC_SIGN_NO_OF_VIRTUALS) + +#define ECC_VERIFY_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_VERIFY_NO_OF_BUFFERS (WEIER_Y3 + 1u - ECC_VERIFY_NO_OF_VIRTUALS) + +#define ECC_POINTMULT_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_POINTMULT_NO_OF_BUFFERS (WEIER_Y1 + 1u - ECC_POINTMULT_NO_OF_VIRTUALS) + +#define ECC_GENERATEDOMAINPARAMS_NO_OF_VIRTUALS ECC_NO_OF_VIRTUALS +#define ECC_GENERATEDOMAINPARAMS_NO_OF_BUFFERS (WEIER_Y0 + 1u - ECC_GENERATEDOMAINPARAMS_NO_OF_VIRTUALS) + + + + +/**********************************************************/ +/* Helper macros of import/export with flow protection */ +/**********************************************************/ + +/** Helper macro to call #mcuxClMemory_copy for importing data to PKC workarea with flow protection. */ +#define MCUXCLECC_FP_IMPORT_TO_PKC_BUFFER(pOffsetTable, iTarget, pSource, byteLen) \ + MCUXCLECC_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR((pOffsetTable)[iTarget]), pSource, byteLen) + +#define MCUXCLECC_FP_CALLED_MEMORY_COPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) +#define MCUXCLECC_FP_CALLED_IMPORT_TO_PKC_BUFFER MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + + +/**********************************************************/ +/* Internal function declaration */ +/**********************************************************/ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Weier_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Weier_SetupEnvironment( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_DomainParam_t *pWeierDomainParams, + uint8_t noOfBuffers + ); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_Weier_DomainParams_t *pWeierDomainParams, + uint8_t noOfBuffers + ); + + + +/**********************************************************/ +/* Internal function declaration - point check */ +/**********************************************************/ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_PointCheckAffineNR) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointCheckAffineNR(void); + + +/**********************************************************/ +/* Internal function declaration - point arithmetic */ +/**********************************************************/ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_RepeatPointDouble) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClEcc_RepeatPointDouble(uint32_t iteration); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_PointFullAdd) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointFullAdd(void); + +/**********************************************************/ +/* Internal function declaration - point multiplication */ +/**********************************************************/ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Int_PointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClEcc_Int_PointMult(uint8_t iScalar, uint32_t scalarBitLength); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_SecurePointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_SecurePointMult(mcuxClSession_Handle_t pSession, + uint8_t iScalar, + uint32_t scalarBitLength); + + +/**********************************************************/ +/* Internal function declaration - key generation */ +/**********************************************************/ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Int_CoreKeyGen) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Int_CoreKeyGen(mcuxClSession_Handle_t pSession, + uint32_t nByteLength); + +/** + * @brief Function implementing WeierECC key pair generation. + * @api + * + * This function generates an ECC key pair for usage within WeierECC protocols such as ECDSA and ECDH. + * + * @param pSession Handle for the current CL session. + * @param[in] generation Key generation algorithm specifier. + * @param[out] privKey Key handle for the generated private key. + * @param[out] pubKey Key handle for the generated public key. + * + * @return status + * @retval #MCUXCLECC_STATUS_OK if private key and public key are generated successfully; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_RNG_ERROR if random number (DRBG / PRNG) error (unexpected behavior); + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * + * @attention This function uses DRBG and PRNG. Caller needs to check if DRBG and PRNG are ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_GenerateKeyPair, mcuxClKey_KeyGenFct_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClEcc_WeierECC_GenerateKeyPair( + mcuxClSession_Handle_t pSession, + mcuxClKey_Generation_t generation, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey + ); + + + +/**********************************************************/ +/* Internal function declaration - key agreement */ +/**********************************************************/ + + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h new file mode 100644 index 000000000..c96718793 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine + */ +#define mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine_LEN 11u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine[mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac + */ +#define mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac[mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_ConvertJacToAffine + */ +#define mcuxClEcc_FUP_Weier_ConvertJacToAffine_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertJacToAffine[mcuxClEcc_FUP_Weier_ConvertJacToAffine_LEN]; + +/* + * FUP program declaration mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian + */ +#define mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian[mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FP.h new file mode 100644 index 000000000..b1483c4e9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FP.h @@ -0,0 +1,344 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_FP.h + * @brief flow protection definitions + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_FP_H_ +#define MCUXCLECC_WEIER_INTERNAL_FP_H_ + +#include // Exported features flags header + +/**********************************************************/ +/* mcuxClEcc_KeyGen */ +/**********************************************************/ + +/* Initialization */ +#define MCUXCLECC_FP_KEYGEN_INIT \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_RandomizeUPTRT), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared) + +/* Import/check base point */ +#define MCUXCLECC_FP_KEYGEN_BASE_POINT \ + MCUXCLECC_FP_KEYGEN_INIT, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +/* Generate private key */ +#define MCUXCLECC_FP_KEYGEN_GENERATE_PRIKEY \ + MCUXCLECC_FP_KEYGEN_BASE_POINT, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_CoreKeyGen), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + +/* Calculate public key */ +#define MCUXCLECC_FP_KEYGEN_CALC_PUBKEY \ + MCUXCLECC_FP_KEYGEN_GENERATE_PRIKEY, \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_LSB0s, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult) + +/* Convert/check public key */ +#define MCUXCLECC_FP_KEYGEN_CONVERT_PUBKEY \ + MCUXCLECC_FP_KEYGEN_CALC_PUBKEY, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +/* Check n/p and export */ +#define MCUXCLECC_FP_KEYGEN_FINAL \ + MCUXCLECC_FP_KEYGEN_CONVERT_PUBKEY, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportBigEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, \ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE + + +/**********************************************************/ +/* mcuxClEcc_Sign */ +/**********************************************************/ + +/* Initialization */ +#define MCUXCLECC_FP_SIGN_INIT \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) + +#define MCUXCLECC_FP_SIGN_BEFORE_LOOP \ + MCUXCLECC_FP_SIGN_INIT, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_RandomizeUPTRT), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared) + +/* Mail loop - first part, until checking r */ +#define MCUXCLECC_FP_SIGN_LOOP_R_0 \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +#define MCUXCLECC_FP_SIGN_LOOP_R_1 \ + MCUXCLECC_FP_SIGN_LOOP_R_0, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_CoreKeyGen) + +#define MCUXCLECC_FP_SIGN_LOOP_R \ + MCUXCLECC_FP_SIGN_LOOP_R_1, \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_LSB0s, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS + +/* Mail loop - second part, checking s */ +#define MCUXCLECC_FP_SIGN_LOOP_S \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + /* optional SHR will be balanced separately */ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS + +#define MCUXCLECC_FP_SIGN_FINAL \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, \ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE + + +/**********************************************************/ +/* mcuxClEcc_PointMult */ +/**********************************************************/ + +/* Initialization */ +#define MCUXCLECC_FP_POINTMULT_INIT \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_RandomizeUPTRT), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash) + +/* Import/check base point */ +#define MCUXCLECC_FP_POINTMULT_BASE_POINT \ + MCUXCLECC_FP_POINTMULT_INIT, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +/* Import scalar */ +// TODO (CLNS-979) Avoid multiplication with 2 if CLNS-979 is reseolved +#define MCUXCLECC_FP_POINTMULT_SCALAR \ + MCUXCLECC_FP_POINTMULT_BASE_POINT, \ + (2u * MCUXCLPKC_FP_CALLED_CALC_OP1_CONST), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + +/* Calculate scalar multiplication */ +#define MCUXCLECC_FP_POINTMULT_SCALAR_MULTIPLICATION \ + MCUXCLECC_FP_POINTMULT_SCALAR, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_LSB0s, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SecurePointMult) + +/* Convert/check result of scalar multiplication */ +#define MCUXCLECC_FP_POINTMULT_CONVERT_POINT \ + MCUXCLECC_FP_POINTMULT_SCALAR_MULTIPLICATION, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +/* Check n/p and export */ +// TODO (CLNS-979) Avoid multiplication with 2 if CLNS-979 is reseolved +#define MCUXCLECC_FP_POINTMULT_FINAL \ + MCUXCLECC_FP_POINTMULT_CONVERT_POINT, \ + (2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, \ + (2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportBigEndianFromPkc)), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, \ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE + + +/**********************************************************/ +/* mcuxClEcc_Verify */ +/**********************************************************/ + +#define MCUXCLECC_FP_VERIFY_INIT \ + (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)) + +#define MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK \ + (MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)+ \ + MCUX_CSSL_FP_CONDITIONAL((byteLenHash >= byteLenN), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR)+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MR+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_InterleaveTwoScalars)) + +#define MCUXCLECC_FP_VERIFY_CALC_P1 \ + (MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_ZERO != checkHashZero), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_PointMult), \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST)+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)) + +#define MCUXCLECC_FP_VERIFY_CALC_P2 \ + (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_RepeatPointDouble)+ \ + MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_PointMult)) + +#define MCUXCLECC_FP_VERIFY_CALC_P1_ADD_P2 \ + (MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_ZERO != checkHashZero), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointFullAdd))+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR)+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP) + +#define MCUXCLECC_FP_VERIFY_P384_BEFORE_POINT_ADD \ + (MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SwitchEndianness_P384)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SwitchEndianness_P384)+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_AND_CONST+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SwitchEndianness_P384)+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MS+ \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MR+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_InterleaveTwoScalars)+ \ + MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_NONZERO == checkHashZero), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR_NIST), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR_NIST), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_PointMult_NIST), \ + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST)+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SwitchEndianness_P384)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SwitchEndianness_P384)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR_NIST)) + +#define MCUXCLECC_FP_VERIFY_P384_POINT_ADD \ + (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_RepeatPointDouble_NIST)+ \ + MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Int_PointMult_NIST)+ \ + MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_ZERO != checkHashZero), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointFullAdd_NIST))) + +#define MCUXCLECC_FP_VERIFY_P384_FINAL \ + (MCUXCLPKC_FP_CALLED_CALC_MC1_MM+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)+ \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR_NIST)+ \ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP) + + +/**********************************************************/ +/* mcuxClEcc_WeierECC_GenerateDomainParams */ +/**********************************************************/ + +#define MCUXCLECC_FP_WEIERECC_GENERATEDOMAINPARAMS_INIT_AND_VERIFY \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR) + +#define MCUXCLECC_FP_WEIERECC_GENERATEDOMAINPARAMS_FINAL(options) \ + MCUXCLECC_FP_WEIERECC_GENERATEDOMAINPARAMS_INIT_AND_VERIFY, \ + MCUX_CSSL_FP_CONDITIONAL(MCUXCLECC_OPTION_GENERATEPRECPOINT_YES == ((options) & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_RepeatPointDouble), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_CONDITIONAL(MCUXCLECC_OPTION_GENERATEPRECPOINT_YES == ((options) & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc) ), \ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE + + +#endif /* MCUXCLECC_WEIER_INTERNAL_FP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FUP.h new file mode 100644 index 000000000..ac9068447 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_UpdateJacobianCoordinates + */ +#define mcuxClEcc_FUP_UpdateJacobianCoordinates_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_UpdateJacobianCoordinates[mcuxClEcc_FUP_UpdateJacobianCoordinates_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_INTERNAL_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_KeyGen_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_KeyGen_FUP.h new file mode 100644 index 000000000..625665d0b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_KeyGen_FUP.h @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_KeyGen_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34 + */ +#define mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34_LEN 6u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34[mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56 + */ +#define mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56_LEN 8u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56[mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56_LEN]; + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_CoreKeyGen_Step7 + */ +#define mcuxClEcc_FUP_Weier_CoreKeyGen_Step7_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Step7[mcuxClEcc_FUP_Weier_CoreKeyGen_Step7_LEN]; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h new file mode 100644 index 000000000..9a7f9a0e8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h @@ -0,0 +1,64 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP_H_ + +#include // Exported features flags header +#include + + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_DoubleAdd + */ +#define mcuxClEcc_FUP_Weier_DoubleAdd_Len1 5u +#define mcuxClEcc_FUP_Weier_DoubleAdd_Len2 15u +#define mcuxClEcc_FUP_Weier_DoubleAdd_Len (mcuxClEcc_FUP_Weier_DoubleAdd_Len1 + mcuxClEcc_FUP_Weier_DoubleAdd_Len2) +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_DoubleAdd[mcuxClEcc_FUP_Weier_DoubleAdd_Len]; + +#define MCUXCLECC_FP_CALCFUP_ADD_ONLY() \ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_DoubleAdd, mcuxClEcc_FUP_Weier_DoubleAdd_Len) +#define MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + +#define MCUXCLECC_FP_CALCFUP_DOUBLE_ADD() \ + do{ \ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_DoubleAdd, mcuxClEcc_FUP_Weier_DoubleAdd_Len); \ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_DoubleAdd, mcuxClEcc_FUP_Weier_DoubleAdd_Len1, \ + mcuxClEcc_FUP_Weier_DoubleAdd_Len2); \ + } while (false) +#define MCUXCLECC_FP_CALLED_CALCFUP_DOUBLE_ADD \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_RepeatDouble + */ +#define mcuxClEcc_FUP_Weier_RepeatDouble_Len1 5u +#define mcuxClEcc_FUP_Weier_RepeatDouble_Len2 16u +#define mcuxClEcc_FUP_Weier_RepeatDouble_Len3 3u +#define mcuxClEcc_FUP_Weier_RepeatDouble_Len (mcuxClEcc_FUP_Weier_RepeatDouble_Len1 + mcuxClEcc_FUP_Weier_RepeatDouble_Len2 + mcuxClEcc_FUP_Weier_RepeatDouble_Len3) +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_RepeatDouble[mcuxClEcc_FUP_Weier_RepeatDouble_Len]; + +#define MCUXCLECC_FP_CALCFUP_ONE_DOUBLE() \ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_RepeatDouble, \ + mcuxClEcc_FUP_Weier_RepeatDouble_Len1 + mcuxClEcc_FUP_Weier_RepeatDouble_Len2) +#define MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + + +#endif /* MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointCheck_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointCheck_FUP.h new file mode 100644 index 000000000..a10587742 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_PointCheck_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointCheck_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_PointCheckAffNR + */ +#define mcuxClEcc_FUP_Weier_PointCheckAffNR_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointCheckAffNR[mcuxClEcc_FUP_Weier_PointCheckAffNR_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h new file mode 100644 index 000000000..09ee00ef2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP_H_ + +#include // Exported features flags header +#include + + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_CoZPointAddSub + */ +#define mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN1 7u +#define mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN2 18u +#define mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN3 3u +#define mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN \ + (mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN1 + mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN2 + mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN3) +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoZPointAddSub[mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN]; + + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP + */ +#define mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP_LEN 8 +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP[mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP_LEN]; + + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1 + */ +#define mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN1 4u +#define mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN2 11u +#define mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN3 5u +#define mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN \ + ( mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN1 \ + + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN2 \ + + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN3 ) +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1[mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN]; + + +#endif /* MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_KeyGen_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_KeyGen_FUP.h new file mode 100644 index 000000000..007e242ed --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_KeyGen_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_KeyGen_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_KEYGEN_FUP_H_ +#define MCUXCLECC_WEIER_KEYGEN_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey + */ +#define mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey_LEN 7u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey[mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_KEYGEN_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_PointMult_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_PointMult_FUP.h new file mode 100644 index 000000000..173a02639 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_PointMult_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_PointMult_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_POINTMULT_FUP_H_ +#define MCUXCLECC_WEIER_POINTMULT_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR + */ +#define mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR[mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_POINTMULT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Sign_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Sign_FUP.h new file mode 100644 index 000000000..74f58ebe8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Sign_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Sign_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_SIGN_FUP_H_ +#define MCUXCLECC_WEIER_SIGN_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_Sign_CalculateS + */ +#define mcuxClEcc_FUP_Weier_Sign_CalculateS_LEN 13u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Sign_CalculateS[mcuxClEcc_FUP_Weier_Sign_CalculateS_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_SIGN_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Verify_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Verify_FUP.h new file mode 100644 index 000000000..cf46c78c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/internal/mcuxClEcc_Weier_Verify_FUP.h @@ -0,0 +1,70 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Verify_FUP.h + * @brief defines FUP programs byte arrays + */ + + +#ifndef MCUXCLECC_WEIER_VERIFY_FUP_H_ +#define MCUXCLECC_WEIER_VERIFY_FUP_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * FUP program declaration mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR + */ +#define mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR[mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR_LEN]; + +/** + * FUP program declaration mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR + */ +#define mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR_LEN 10u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR[mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR_LEN]; + +/** + * FUP program declaration mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR + */ +#define mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR_LEN 6u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR[mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR_LEN]; + +/** + * FUP program declaration mcuxClEcc_Fup_Verify_InitZ_CalcU1U2 + */ +#define mcuxClEcc_Fup_Verify_InitZ_CalcU1U2_LEN 6u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_InitZ_CalcU1U2[mcuxClEcc_Fup_Verify_InitZ_CalcU1U2_LEN]; + +/** + * FUP program declaration mcuxClEcc_Fup_Verify_Update_G_to_Prec1 + */ +#define mcuxClEcc_Fup_Verify_Update_G_to_Prec1_LEN 5u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_G_to_Prec1[mcuxClEcc_Fup_Verify_Update_G_to_Prec1_LEN]; + +/** + * FUP program declaration mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z + */ +#define mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z_LEN 9u +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z[mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIER_VERIFY_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc.h new file mode 100644 index 000000000..3449148dc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc.h + * @brief Top level header of mcuxClEcc component + * + * @defgroup mcuxClEcc mcuxClEcc + * @brief Elliptic Curve Cryptography component + */ + + +#ifndef MCUXCLECC_H_ +#define MCUXCLECC_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + + + +#endif /* MCUXCLECC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Constants.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Constants.h new file mode 100644 index 000000000..71c63454c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Constants.h @@ -0,0 +1,143 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Constants.h + * @brief Constants definition for domain parameters of supported curves + */ + +/* TODO: domain parameters are not verified, and will be verified in CLNS-5817 */ + +#ifndef MCUXCLECC_CONSTANTS_H_ +#define MCUXCLECC_CONSTANTS_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEcc_Constants mcuxClEcc_Constants + * @brief Defines constants of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + + +/* Curve25519 domain parameters */ +extern const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve25519; + +/* Curve448 domain parameters */ +extern const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve448; + +/* secp160k1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp160k1; + +/* secp192k1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192k1; + +/* sec224k1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224k1; + +/* secp256k1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256k1; + +/* secp192r1 (nistp192r1, ansix9p192r1) domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192r1; +#define mcuxClEcc_Weier_DomainParams_NIST_P192 mcuxClEcc_Weier_DomainParams_secp192r1 +#define mcuxClEcc_Weier_DomainParams_ansix9p192r1 mcuxClEcc_Weier_DomainParams_secp192r1 + +/* secp224r1 (nistp224r1, ansix9p224r1) domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224r1; +#define mcuxClEcc_Weier_DomainParams_NIST_P224 mcuxClEcc_Weier_DomainParams_secp224r1 +#define mcuxClEcc_Weier_DomainParams_ansix9p224r1 mcuxClEcc_Weier_DomainParams_secp224r1 + +/* secp256r1 (nistp256r1, ansix9p256r1) domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256r1; +#define mcuxClEcc_Weier_DomainParams_NIST_P256 mcuxClEcc_Weier_DomainParams_secp256r1 +#define mcuxClEcc_Weier_DomainParams_ansix9p256r1 mcuxClEcc_Weier_DomainParams_secp256r1 + +/* secp384r1 (nistp384r1, ansix9p384r1) domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp384r1; +#define mcuxClEcc_Weier_DomainParams_NIST_P384 mcuxClEcc_Weier_DomainParams_secp384r1 +#define mcuxClEcc_Weier_DomainParams_ansix9p384r1 mcuxClEcc_Weier_DomainParams_secp384r1 + +/* secp521r1 (nistp521r1, ansix9p521r1) domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp521r1; +#define mcuxClEcc_Weier_DomainParams_NIST_P521 mcuxClEcc_Weier_DomainParams_secp521r1 +#define mcuxClEcc_Weier_DomainParams_ansix9p521r1 mcuxClEcc_Weier_DomainParams_secp521r1 + +/* brainpoolP160r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160r1; + +/* brainpoolP192r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192r1; + +/* brainpoolP224r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224r1; + +/* brainpoolP256r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256r1; + +/* brainpoolP320r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320r1; + +/* brainpoolP384r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384r1; + +/* brainpoolP512r1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512r1; + +/* brainpoolP160t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160t1; + +/* brainpoolP192t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192t1; + +/* brainpoolP224t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224t1; + +/* brainpoolP256t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256t1; + +/* brainpoolP320t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320t1; + +/* brainpoolP384t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384t1; + +/* brainpoolP512t1 domain parameters */ +extern const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512t1; + + +/* Ed25519 domain parameters */ +extern const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed25519; + +/* Ed448 domain parameters */ +extern const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed448; + +/* phflag values for EdDSA */ +#define MCUXCLECC_EDDSA_PHFLAG_ZERO 0u +#define MCUXCLECC_EDDSA_PHFLAG_ONE 1u + +/** + * @} + */ /* mcuxClEcc_Constants */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h new file mode 100644 index 000000000..c97be8073 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_EdDSA_GenerateKeyPair_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP_H_ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S[6]; + +#endif /* MCUXCLECC_EDDSA_GENERATEKEYPAIR_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateSignature_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateSignature_FUP.h new file mode 100644 index 000000000..efe7258fe --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_GenerateSignature_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_EdDSA_GenerateSignature_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP_H_ +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S[10]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN[10]; + +#endif /* MCUXCLECC_EDDSA_GENERATESIGNATURE_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h new file mode 100644 index 000000000..450ea17fe --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP_H_ +#define MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN[7]; + +#endif /* MCUXCLECC_EDDSA_INTERNAL_CALCHASHMODN_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h new file mode 100644 index 000000000..882accece --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP_H_ +#define MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448[6]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448[7]; + +#endif /* MCUXCLECC_EDDSA_INTERNAL_DECODEPOINT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Functions.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Functions.h new file mode 100644 index 000000000..5a43ab43f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Functions.h @@ -0,0 +1,370 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Functions.h + * @brief Top level APIs of mcuxClEcc component + */ + + +#ifndef MCUXCLECC_FUNCTIONS_H_ +#define MCUXCLECC_FUNCTIONS_H_ + + +#include +#include // Exported features flags header +#include +#include +#include +#include + +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Public APIs of mcuxClEcc */ +/**********************************************************/ + +/** + * @defgroup mcuxClEcc_Functions mcuxClEcc_Functions + * @brief Defines all functions of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + +/** implements ECDSA key generation. + * @retval #MCUXCLECC_STATUS_OK if private key and public key are generated successfully; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_RNG_ERROR if random number (DRBG / PRNG) error (unexpected behavior); + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * @attention This function uses DRBG and PRNG. Caller needs to check if DRBG and PRNG are ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_KeyGen) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_KeyGen( + mcuxClSession_Handle_t pSession, ///< [in] pointer to #mcuxClSession_Descriptor. + const mcuxClEcc_KeyGen_Param_t * pParam ///< [in] pointer to ECDSA Key Generation parameter structure. + ); + +/** implements ECDSA signature generation. + * @retval #MCUXCLECC_STATUS_OK if signature is generated successfully; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_RNG_ERROR if random number (DRBG / PRNG) error (unexpected behavior); + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * @attention This function uses DRBG and PRNG. Caller needs to check if DRBG and PRNG are ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Sign) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Sign( + mcuxClSession_Handle_t pSession, ///< [in] pointer to #mcuxClSession_Descriptor. + const mcuxClEcc_Sign_Param_t * pParam ///< [in] pointer to ECDSA Sign parameter structure. + ); + + +/** implements ECDSA signature verification. + * @retval #MCUXCLECC_STATUS_OK if ECDSA Signature is valid; + * @retval #MCUXCLECC_STATUS_INVALID_SIGNATURE if ECDSA Signature is invalid; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Verify( + mcuxClSession_Handle_t pSession, ///< [in] pointer to #mcuxClSession_Descriptor. + const mcuxClEcc_Verify_Param_t * pParam ///< [in] pointer to ECDSA Verify parameter structure. + ); + +/** + * @brief implements ECC point multiplication. + * + * This API performs elliptic curve point multiplication on the given elliptic curve in short Weierstrass form. + * This API does not check if the curve parameters and the given point are valid or not. + * Invalid curve parameters or point might cause the return of #MCUXCLECC_STATUS_INVALID_PARAMS, + * invalid result, and unexpected behavior (e.g., the return of #MCUXCLECC_STATUS_FAULT_ATTACK). + * + * @param[in] pSession pointer to #mcuxClSession_Descriptor. + * @param[in] pParam pointer to ECC point multiplication parameter structure. + * + *
+ *
Parameter properties
+ *
+ *
pParam.curveParam.pG
+ *
the base point is not used in this API. This pointer can be left unspecified.
+ *
+ *
+ * + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK if point multiplication is calculated successfully, and the result is not the neutral point; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_NEUTRAL_POINT if result is the neutral point; + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * + * @attention This function uses PRNG. Caller needs to check if PRNG is ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_PointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointMult( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_PointMult_Param_t * pParam + ); + + +/** + * @brief implements ECC key pair generation step for a MontDh key agreement according to rfc7748. + * + * This API performs elliptic curve key generation of the private key and calculates corresponding public key for MontDh key agreement + * This API does not check if the curve parameters are correct. + * This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way + * Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK. + * + * @param[in] pSession #mcuxClSession_Descriptor structure + * @param[in] type type structure specifying requested key type to be generated. Also contains domain parameters + * @param[in] protection #mcuxClKey_Protection structure + * @param[out] privKey private key handling structure + * @param[out] pPrivData buffer for private key of the MCUXCLECC_MONT_CURVE25519/448_SIZE_PRIVATEKEY length + * @param[out] pPrivDataLength private key length + * @param[out] pubKey public key handling structure + * @param[out] pPubData buffer for public key x-coordinate of MCUXCLECC_MONT_CURVE25519/448_SIZE_PUBLICKEY length + * @param[out] pPubDataLength public key x-coordinate length + * + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_ and @ref MCUXCLECC_MONTDH_STATUS_) + * @retval #MCUXCLECC_STATUS_OK if key generation correctly calculate private and public keys, public key does not belong to the small subgroup. + * @retval #MCUXCLECC_STATUS_RNG_ERROR if RNG return an error. + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * + * @attention This function uses PRNG. Caller needs to check if PRNG is ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Mont_DhKeyGeneration) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyGeneration( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength + ); + +/** + * @brief implements ECC key agreement according to rfc7748. + * + * This API performs elliptic curve key agreement to compute shared secret between two parties using the function X25519 + * This API does not check if the curve parameters are correct. + * This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way + * This API might return MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP if generated public key lies in the small subgroup + * Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK. + * + * @param[in] pSession pointer to #mcuxClSession_Descriptor. + * @param[in] key private key handling structure + * @param[in] otherKey public key handling structure + * @param[out] pOut buffer for shared secret of length MCUXCLECC_MONT_CURVE25519/448_SIZE_SHAREDSECRET + * @param[out] pOutLength shared secret length + * + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_ and @ref MCUXCLECC_MONTDH_STATUS_) + * @retval #MCUXCLECC_STATUS_OK if key generation correctly calculate private and public keys, public key does not belong to the small subgroup. + * @retval #MCUXCLECC_STATUS_RNG_ERROR if RNG return an error. + * @retval #MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP if calculated public key lies in small subgroup. + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + * + * @attention This function uses PRNG. Caller needs to check if PRNG is ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_Mont_DhKeyAgreement) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyAgreement( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + mcuxClKey_Handle_t otherKey, + uint8_t * pOut, + uint32_t * const pOutLength + ); + + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * @brief This function implements the EdDSA key pair generation for Ed25519 and Ed448 as specified in rfc8032 + * (see Sections 5.1.5 and 5.2.5 of https://datatracker.ietf.org/doc/html/rfc8032). + * For an M byte private key d, which is either generated internally at random or passed as input, + * this function calculates the private key hash H(d)=(h0,...,h{2b-1}) and deduces and returns + * - the secret integer s + * - the second half (hb,...,h{2b-1}) of the private key hash + * - the public key Qenc=(s*G)enc where G is the base point. + * + * This API does not check if the curve parameters are correct. + * This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way + * Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK. + * + * + * @param[in] pSession Handle for the current CL session + * @param[in] mode Mode descriptor specifying the EdDSA GenerateKeyPair variant + * @param[in/out] privKey Key handle for the private key. + * @param[in/out] pubKey Key handle for the public key. + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK private key data and public key have been generated successfully + * @retval #MCUXCLECC_STATUS_RNG_ERROR random number generation (DRBG / PRNG) error (unexpected behavior) + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateKeyPair) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateKeyPair( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey + ); + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * @brief This function implements the EdDSA signature generation for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.6 and 5.2.6 of https://datatracker.ietf.org/doc/html/rfc8032). + * For given hash prefix prefix (either dom2(x, y) or dom4(x, y) according to the chosen EdDSA variant; see Sections 5.1 and 5.2 of https://datatracker.ietf.org/doc/html/rfc8032), + * a message digest m', i.e. either the message itself for PureEdDSA or the message hash for HashEdDSA (see Section 4 of https://datatracker.ietf.org/doc/html/rfc8032), + * the signing keys s and (hb,...,h{2b-1}) derived from the private key d (see mcuxClEcc_EdDSA_GenerateKeyPair) + * and a public key Qenc, this function calculates an EdDSA signature (Renc,S), where Renc and S are given by + * + * - Renc = (r*G)enc + * - S = r+H(prefix||Renc||Qenc||m')*s mod n + * + * where the secret scalar r is given by r=H(prefix||(hb,...,h{2b-1})||m') and G is the base point. + * + * This API does not check if the curve parameters are correct. + * This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way + * Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK. + * + * + * @param[in] pSession Handle for the current CL session + * @param[in] key Key handle for private key related data which a.o. references the secret signing keys s and (hb,...,h{2b-1}) as well as the public key Qenc. + * @param[in] mode Mode descriptor specifying the EdDSA variant + * @param[in] pIn Pointer to message digest m' + * @param[in] inSize Size of message digest m' + * @param[out] pSignature Pointer to buffer where the signature (Renc,S) will be stored + * @param[out] pSignatureSize Will be set to the number of bytes of data that have been written to the pSignature buffer + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK signature generation was successful + * @retval #MCUXCLECC_STATUS_RNG_ERROR random number generation (DRBG / PRNG) error (unexpected behavior) + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateSignature) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateSignature( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + uint8_t *pSignature, + uint32_t * const pSignatureSize + ); + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * @brief This function implements the EdDSA signature verification for Ed25519 and Ed448 as specified in rfc8032 (see Sections 5.1.7 and 5.2.7 of https://datatracker.ietf.org/doc/html/rfc8032). + * For given hash prefix prefix (either dom2(x, y) or dom4(x, y) according to the chosen EdDSA variant; see Sections 5.1 and 5.2 of https://datatracker.ietf.org/doc/html/rfc8032), + * a message digest m', i.e. either the message itself for PureEdDSA or the message hash for HashEdDSA (see Section 4 of https://datatracker.ietf.org/doc/html/rfc8032), + * and a public key Qenc, this function: + * - verifies the public key Qenc + * - verifies that the signature component S satisfies S in [0,n-1] + * - verifies if the following signature equation holds: + * * h*S*G=h*R+h*H(prefix||Renc||Qenc||m')*Q + * + * This API does not check if the curve parameters are correct. + * This API might return MCUXCLECC_STATUS_RNG_ERROR when RNG behave in unexpected way + * Unexpected behavior will return MCUXCLECC_STATUS_FAULT_ATTACK. + * + * + * @param[in] session Handle for the current CL session + * @param[in] key Key handle for public key Qenc + * @param[in] mode Mode descriptor specifying the EdDSA variant + * @param[in] pIn Pointer to message digest m' + * @param[in] inSize Size of message digest m' + * @param[in] pSignature Pointer to buffer containing the signature (Renc,S) + * @param[in] signatureSize Number of bytes of data in the pSignature buffer + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK signature verification passed + * @retval #MCUXCLECC_STATUS_INVALID_SIGNATURE EdDSA signature is invalid + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS input parameters are invalid + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_VerifySignature) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_VerifySignature( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + const uint8_t *pSignature, + uint32_t signatureSize + ); + +/** + * @brief This function initializes an EdDSA mode descriptor for EdDSA key pair generation with private key input. + * + * @param[in] pSession Handle for the current CL session + * @param[in/out] mode Pointer to mode descriptor to be initialized for EdDSA key pair generation with private key input + * @param[in] pPrivKey Pointer to private key input + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK EdDSA mode descriptor has been initialized successfully + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_InitPrivKeyInputMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_InitPrivKeyInputMode( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + const uint8_t *pPrivKey + ); + +/** + * @brief This function implements the protocol descriptor generation for Ed25519ctx, Ed25519ph, Ed448 and Ed448ph + * + * @param[in] pSession pointer to #mcuxClSession_Descriptor + * @param[in] pDomainParams Pointer to domain parameters of the used curve + * @param[in] pProtocolDescriptor Protocol descriptor specifying the EdDSA variant + * @param[in] phflag Option whether pre-hashing is enabled + * @param[in] pContext User input context for the hash prefix + * @param[in] contextLen Length of the context + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK signature verification passed + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateProtocolDescriptor( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor, + uint32_t phflag, + mcuxCl_InputBuffer_t pContext, + uint32_t contextLen); + + + + + +/** + * @} + */ /* mcuxClEcc_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Convert_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Convert_FUP.h new file mode 100644 index 000000000..52ac07c19 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Convert_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Internal_Convert_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_INTERNAL_CONVERT_FUP_H_ +#define MCUXCLECC_INTERNAL_CONVERT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_ConvertHomToAffine[7]; + +#endif /* MCUXCLECC_INTERNAL_CONVERT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Interleave_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Interleave_FUP.h new file mode 100644 index 000000000..f36a4035f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_Interleave_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Internal_Interleave_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_INTERNAL_INTERLEAVE_FUP_H_ +#define MCUXCLECC_INTERNAL_INTERLEAVE_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Interleave[7]; + +#endif /* MCUXCLECC_INTERNAL_INTERLEAVE_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_PointComparison_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_PointComparison_FUP.h new file mode 100644 index 000000000..295bba35b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_PointComparison_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Internal_PointComparison_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP_H_ +#define MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_PointComparisonHom[10]; + +#endif /* MCUXCLECC_INTERNAL_POINTCOMPARISON_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_SetupEnvironment_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_SetupEnvironment_FUP.h new file mode 100644 index 000000000..a7d3bdcf2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Internal_SetupEnvironment_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Internal_SetupEnvironment_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP_H_ +#define MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SetupEnvironment_ClearBuffers[5]; + +#endif /* MCUXCLECC_INTERNAL_SETUPENVIRONMENT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_KeyMechanisms.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_KeyMechanisms.h new file mode 100644 index 000000000..d8045fb07 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_KeyMechanisms.h @@ -0,0 +1,1077 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_KeyMechanisms.h + * @brief ECC related definitions to be used for key handling mechanisms of the mcuxClKey component + */ + + +#ifndef MCUXCLECC_KEYMECHANISMS_H_ +#define MCUXCLECC_KEYMECHANISMS_H_ + +#include // Exported features flags header +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEcc_KeyTypeDescriptors mcuxClEcc_KeyTypeDescriptors + * @brief Definitions of ECC related key type descriptors + * @ingroup mcuxClEcc + * @{ + */ + +/***********************************************/ +/* Key types for secp160k1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp160k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp160k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp160k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp160k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp160k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp192k1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp192k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp192k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp192k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp224k1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp224k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp224k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp224k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp256k1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp256k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp256k1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp256k1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256k1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp192r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp192r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp192r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp192r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp192r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp192r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp224r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp224r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp224r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp224r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp224r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp224r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp256r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp256r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp256r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp256r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp256r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp256r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp384r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp384r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp384r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp384r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp384r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp384r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for secp521r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve secp521r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve secp521r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve secp521r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve secp521r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_secp521r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for NIST P-192 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve NIST P-192. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-192. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve NIST P-192. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve NIST P-256. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P192_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P192_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for NIST P-224 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve NIST P-224. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-224. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve NIST P-224. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve NIST P-224. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P224_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P224_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for NIST P-256 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve NIST P-256. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-256. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve NIST P-256. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve NIST P-256. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P256_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P256_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for NIST P-384 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve NIST P-384. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-384. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve NIST P-384. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve NIST P-384. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P384_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P384_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for NIST P-521 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve NIST P-521. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve NIST P-521. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Pub = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve NIST P-521. + * + */ +#define mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve NIST P-521. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_NIST_P521_Priv = &mcuxClKey_TypeDescriptor_WeierECC_NIST_P521_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP160r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP160r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP160r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP160r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP192r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP192r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP192r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP192r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP224r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP224r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP224r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP224r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP256r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP256r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP256r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP256r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP320r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP320r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP320r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP320r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP384r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP384r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP384r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP384r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP512r1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP512r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP512r1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP512r1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512r1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP160t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP160t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP160t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP160t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP160t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP160t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP192t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP192t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP192t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP192t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP192t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP192t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP224t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP224t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP224t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP224t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP224t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP224t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP256t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP256t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP256t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP256t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP256t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP256t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP320t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP320t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP320t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP320t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP320t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP320t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP384t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP384t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP384t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP384t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP384t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP384t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for brainpoolP512t1 */ +/***********************************************/ + +/** + * @brief Key type structure for public ECC keys for Weierstrass curve brainpoolP512t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub; + +/** + * @brief Key type pointer for public ECC Weierstrass keys for Weierstrass curve brainpoolP512t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Pub = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for private ECC keys for Weierstrass curve brainpoolP512t1. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv; + +/** + * @brief Key type pointer for private ECC keys for Weierstrass curve brainpoolP512t1. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_WeierECC_brainpoolP512t1_Priv = &mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + + +/***********************************************/ +/* Key types for Ed25519 */ +/***********************************************/ + +/** + * @brief Key type structure for ECC EdDSA Ed25519 private keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv; + +/** + * @brief Key type pointer for ECC EdDSA Ed25519 private keys. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Priv = &mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for ECC EdDSA Ed25519 public keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub; + +/** + * @brief Key type pointer for ECC EdDSA Ed25519 public keys. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed25519_Pub = &mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/***********************************************/ +/* Key types for Ed448 */ +/***********************************************/ + +/** + * @brief Key type structure for ECC EdDSA Ed448 private keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv; + +/** + * @brief Key type pointer for ECC EdDSA Ed448 private keys. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Priv = &mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief Key type structure for ECC EdDSA Ed448 public keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub; + +/** + * @brief Key type pointer for ECC EdDSA Ed448 public keys. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_EdDSA_Ed448_Pub = &mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for Curve25519 */ +/***********************************************/ + +/** + * @brief Key type structure for ECC MontDH Curve25519 Key pairs. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair; + +/** + * @brief Key type pointer for ECC MontDH Curve25519 Key pairs. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve25519_KeyPair = &mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +/***********************************************/ +/* Key types for Curve448 */ +/***********************************************/ + +/** + * @brief Key type structure for ECC MontDH Curve448 Key pairs. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair; + +/** + * @brief Key type pointer for ECC MontDH Curve448 Key pairs. + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by mcuxClKey component. Hence, it is declared but never referenced.") +static const mcuxClKey_Type_t mcuxClKey_Type_Ecc_MontDH_Curve448_KeyPair = &mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() +/** + * @} + */ /* mcuxClEcc_KeyTypeDescriptors */ + + + + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_KEYMECHANISMS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_MemoryConsumption.h new file mode 100644 index 000000000..f7e5e1d30 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_MemoryConsumption.h @@ -0,0 +1,308 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClEcc component + */ + +#ifndef MCUXCLECC_MEMORYCONSUMPTION_H_ +#define MCUXCLECC_MEMORYCONSUMPTION_H_ + + +/** + * @defgroup mcuxClEcc_MemoryConsumption mcuxClEcc_MemoryConsumption + * @brief Defines the memory consumption for the @ref mcuxClEcc component + * @ingroup mcuxClEcc + * @{ + */ + +/** + * @addtogroup MCUXCLECC_WACPU_ + * @brief Define the CPU workarea size required by mcuxClEcc APIs. + * @{ + */ +#define MCUXCLECC_ALIGN_SIZE_CPU(byteLen) ((((byteLen) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t))) * (sizeof(uint32_t))) + +#ifdef MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) (96u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u)) ///< CPU workarea size (in bytes) for #mcuxClEcc_KeyGen. +#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) (96u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u)) ///< CPU workarea size (in bytes) for #mcuxClEcc_Sign. +#else /* ! MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ +#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) 96u ///< CPU workarea size (in bytes) for #mcuxClEcc_KeyGen. Parameter byteLenN is just to keep the API consistent. +#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) 96u ///< CPU workarea size (in bytes) for #mcuxClEcc_Sign. Parameter byteLenN is just to keep the API consistent. +#endif /* MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ + +#define MCUXCLECC_VERIFY_WACPU_SIZE 104u ///< CPU workarea size (in bytes) for #mcuxClEcc_Verify. +#define MCUXCLECC_POINTMULT_WACPU_SIZE 96u ///< CPU workarea size (in bytes) for #mcuxClEcc_PointMult. +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_WeierECC_GenerateDomainParams. + + +/** + * @} + */ /* MCUXCLECC_WACPU_ */ + +/** + * @addtogroup MCUXCLECC_MONTDH_WACPU_ + * @brief Define the CPU workarea size required by mcuxClEcc MontDH APIs. + * @{ + */ +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE 92u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration. +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE 92u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration. + +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement. +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement. +/** + * @} + */ /* MCUXCLECC_MONTDH_WACPU_ */ + + /** + * @addtogroup MCUXCLECC_EDDSA_WACPU_ + * @brief Define the CPU workarea size required by mcuxClEcc EdDSA APIs. + * @{ + */ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE 360u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519. +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE 196u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. + +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE 540u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed25519. +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE 132u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed448. + +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE 540u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed25519. +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE 132u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed448. + +#else + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) (416u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u)) ///< CPU workarea size (in bytes) for #mcuxClEcc_KeyGen. +#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) (416u + MCUXCLECC_ALIGN_SIZE_CPU(byteLenN + 8u)) ///< CPU workarea size (in bytes) for #mcuxClEcc_Sign. +#else /* ! MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ +#define MCUXCLECC_KEYGEN_WACPU_SIZE(byteLenN) 416u ///< CPU workarea size (in bytes) for #mcuxClEcc_KeyGen. Parameter byteLenN is just to keep the API consistent. +#define MCUXCLECC_SIGN_WACPU_SIZE(byteLenN) 416u ///< CPU workarea size (in bytes) for #mcuxClEcc_Sign. Parameter byteLenN is just to keep the API consistent. +#endif /* MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ + +#define MCUXCLECC_VERIFY_WACPU_SIZE 424u ///< CPU workarea size (in bytes) for #mcuxClEcc_Verify. +#define MCUXCLECC_POINTMULT_WACPU_SIZE 416u ///< CPU workarea size (in bytes) for #mcuxClEcc_PointMult. +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_WeierECC_GenerateDomainParams. + + +/** + * @} + */ /* MCUXCLECC_WACPU_ */ + +/** + * @addtogroup MCUXCLECC_MONTDH_WACPU_ + * @brief Define the CPU workarea size required by mcuxClEcc MontDH APIs. + * @{ + */ +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WACPU_SIZE 444u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration. +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WACPU_SIZE 468u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration. + +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement. +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WACPU_SIZE 88u ///< CPU workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement. +/** + * @} + */ /* MCUXCLECC_MONTDH_WACPU_ */ + + /** + * @addtogroup MCUXCLECC_EDDSA_WACPU_ + * @brief Define the CPU workarea size required by mcuxClEcc EdDSA APIs. + * @{ + */ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WACPU_SIZE 680u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519. +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WACPU_SIZE 516u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. + +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WACPU_SIZE 540u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed25519. +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WACPU_SIZE 132u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed448. + +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WACPU_SIZE 540u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed25519. +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WACPU_SIZE 132u ///< CPU workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed448. + +#endif +/** + * @} + */ /* MCUXCLECC_EDDSA_WACPU_ */ + + +/** + * @addtogroup MCUXCLECC_WAPKC_ + * @brief Define the PKC workarea size required by mcuxClEcc APIs. + * @{ + */ + +/** + * @brief PKC wordsize in ECC component. + */ +#define MCUXCLECC_PKC_WORDSIZE 8u + +/** + * @brief Helper macro to get the maximum of two given constants. + */ +#define MCUXCLECC_MAX(value0, value1) (((value0) > (value1)) ? (value0) : (value1)) + +/** + * @brief Helper macro to calculate size aligned to PKC word. + */ +#define MCUXCLECC_ALIGN_SIZE_PKC(size) ((((size) + MCUXCLECC_PKC_WORDSIZE - 1u) / MCUXCLECC_PKC_WORDSIZE) * MCUXCLECC_PKC_WORDSIZE) + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_KeyGen for arbitrary lengths of p and n. + */ +#define MCUXCLECC_KEYGEN_WAPKC_SIZE(pByteLen,nByteLen) \ + (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Sign for arbitrary lengths of p and n. + */ +#define MCUXCLECC_SIGN_WAPKC_SIZE(pByteLen,nByteLen) \ + (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Verify for arbitrary lengths of p and n. + */ + +#define MCUXCLECC_VERIFY_WAPKC_SIZE(pByteLen,nByteLen) \ + (28u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_PointMult for arbitrary lengths of p and n. + */ +#define MCUXCLECC_POINTMULT_WAPKC_SIZE(pByteLen,nByteLen) \ + (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_WeierECC_GenerateDomainParams for arbitrary lengths of p and n. + */ +#ifdef MCUXCL_FEATURE_PLATFORM_RW61X + +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(pByteLen,nByteLen) \ + (22u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + +#else + +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE(pByteLen,nByteLen) \ + (24u * (MCUXCLECC_ALIGN_SIZE_PKC(MCUXCLECC_MAX(pByteLen,nByteLen)) + MCUXCLECC_PKC_WORDSIZE)) + +#endif + +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_128 (528u ) +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_256 (880u ) +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_384 (1232u ) +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_512 (1584u ) +#define MCUXCLECC_WEIERECC_GENERATEDOMAINPARAMS_WAPKC_SIZE_640 (1936u ) + + + + +/** + * @} + */ /* MCUXCLECC_WAPKC_ */ + + +/** + * @addtogroup MCUXCLECC_MONTDH_WAPKC_ + * @brief Define the PKC workarea size required by mcuxClEcc_Mont APIs. + * @{ + */ + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration for Curve25519. + */ +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE25519_WAPKC_SIZE 880u + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement for Curve25519. + */ +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE25519_WAPKC_SIZE 880u + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyGeneration for Curve448. + */ +#define MCUXCLECC_MONT_DHKEYGENERATION_CURVE448_WAPKC_SIZE 1408u + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_Mont_DhKeyAgreement for Curve448. + */ +#define MCUXCLECC_MONT_DHKEYAGREEMENT_CURVE448_WAPKC_SIZE 1408u + +/** + * @} + */ /* MCUXCLECC_MONTDH_WAPKC_ */ + +/** + * @addtogroup MCUXCLECC_EDDSA_WAPKC_ + * @brief Define the PKC workarea size required by mcuxClEcc EdDSA APIs. + * @{ + */ + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair. + */ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED25519_WAPKC_SIZE 1760u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed25519. +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_ED448_WAPKC_SIZE 2816u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateKeyPair for Ed448. + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature. + */ +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED25519_WAPKC_SIZE 1760u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed25519. +#define MCUXCLECC_EDDSA_GENERATESIGNATURE_ED448_WAPKC_SIZE 2816u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_GenerateSignature for Ed448. + +/** + * PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature. + */ +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED25519_WAPKC_SIZE 1760u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed25519. +#define MCUXCLECC_EDDSA_VERIFYSIGNATURE_ED448_WAPKC_SIZE 2816u ///< PKC workarea size (in bytes) for #mcuxClEcc_EdDSA_VerifySignature for Ed448. + +/** + * @} + */ /* MCUXCLECC_EDDSA_WAPKC_ */ + +/** + * @brief Define for the buffer size (in bytes) for optimized custom ECC Weierstrass domain parameters + */ +#define MCUXCLECC_CUSTOMWEIERECCDOMAINPARAMS_SIZE(byteLenP, byteLenN) \ + MCUXCLECC_ALIGN_SIZE_CPU(76u \ + + 8u * (byteLenP) \ + + 2u * (byteLenN) ) + +/** + * @addtogroup MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_ + * @brief Define for the EdDSA key pair generation descriptor size. + * @{ + */ +#define MCUXCLECC_EDDSA_GENERATEKEYPAIR_DESCRIPTOR_SIZE 8u ///< EdDSA key pair generation descriptor size. +/** + * @} + */ /* MCUXCLECC_EDDSA_GENKEYPAIR_DESC_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_ + * @brief Define for the EdDSA signature protocol descriptor size. + * @{ + */ +#define MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE 20u ///< EdDSA signature generation descriptor size. +/** + * @} + */ /* MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESC_SIZE_ */ + + + +/** + * @} + */ /* mcuxClEcc_MemoryConsumption */ + +#endif /* MCUXCLECC_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_MontDhX_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_MontDhX_FUP.h new file mode 100644 index 000000000..961b52337 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_MontDhX_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Mont_Internal_MontDhX_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP_H_ +#define MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhDecodeScalar[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhX_CalcAffineX[5]; + +#endif /* MCUXCLECC_MONT_INTERNAL_MONTDHX_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h new file mode 100644 index 000000000..542261f16 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP_H_ +#define MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep[22]; + +#endif /* MCUXCLECC_MONT_INTERNAL_SECURESCALARMULT_XZMONTLADDER_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_ParameterSizes.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_ParameterSizes.h new file mode 100644 index 000000000..81713f3b9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_ParameterSizes.h @@ -0,0 +1,433 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_ParameterSizes.h + * @brief Definitions of ECC domain parameter, key and signature sizes + */ + + +#ifndef MCUXCLECC_PARAMETERSIZES_H_ +#define MCUXCLECC_PARAMETERSIZES_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClEcc_ParameterSizes mcuxClEcc_ParameterSizes + * @brief Defines domain parameter, key and signature sizes of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + + + +/** + * @addtogroup MCUXCLECC_MONT_CURVE25519_SIZE_ + * MontDH parameter size definitions for Curve25519 + * @{ */ +#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP (32U) +#define MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER (32U) +#define MCUXCLECC_MONT_CURVE25519_SIZE_PRIVATEKEY (MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER) +#define MCUXCLECC_MONT_CURVE25519_SIZE_PUBLICKEY (MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP) +#define MCUXCLECC_MONT_CURVE25519_SIZE_SHAREDSECRET (MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP) +/** @} */ /* MCUXCLECC_MONT_CURVE25519_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_MONT_CURVE448_SIZE_ + * MontDH parameter size definitions for Curve448 + * @{ */ +#define MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP (56U) +#define MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER (56U) +#define MCUXCLECC_MONT_CURVE448_SIZE_PRIVATEKEY (MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER) +#define MCUXCLECC_MONT_CURVE448_SIZE_PUBLICKEY (MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP) +#define MCUXCLECC_MONT_CURVE448_SIZE_SHAREDSECRET (MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP) +/** @} */ /* MCUXCLECC_MONT_CURVE448_SIZE_ */ + + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP160K1_SIZE_ + * WeierECC parameter size definitions for secp160k1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP (20U) +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER (21U) +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP160K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP160K1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP192K1_SIZE_ + * WeierECC parameter size definitions for secp192k1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP (24U) +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER (24U) +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP192K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP192K1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP224K1_SIZE_ + * WeierECC parameter size definitions for secp224k1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP (28U) +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER (29U) +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP224K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP224K1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP256K1_SIZE_ + * WeierECC parameter size definitions for secp256k1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP (32U) +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER (32U) +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP256K1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP256K1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP192R1_SIZE_ + * WeierECC parameter size definitions for secp192r1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP (24U) +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER (24U) +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP192R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP224R1_SIZE_ + * WeierECC parameter size definitions for secp224r1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP (28U) +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER (28U) +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP224R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP256R1_SIZE_ + * WeierECC parameter size definitions for secp256r1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP (32U) +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER (32U) +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP256R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP384R1_SIZE_ + * WeierECC parameter size definitions for secp384r1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP (48U) +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER (48U) +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP384R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_SECP521R1_SIZE_ + * WeierECC parameter size definitions for secp521r1 + * @{ */ +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP (66U) +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER (66U) +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_SECP521R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_NIST_P192_SIZE_ + * WeierECC parameter size definitions for NIST P-192 + * @{ */ +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY) +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY) +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP192R1_SIZE_SHAREDSECRET) +#define MCUXCLECC_WEIERECC_NIST_P192_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP192R1_SIZE_SIGNATURE) +/** @} */ /* MCUXCLECC_WEIERECC_NIST_P192_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_NIST_P224_SIZE_ + * WeierECC parameter size definitions for NIST P-224 + * @{ */ +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY) +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY) +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP224R1_SIZE_SHAREDSECRET) +#define MCUXCLECC_WEIERECC_NIST_P224_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP224R1_SIZE_SIGNATURE) +/** @} */ /* MCUXCLECC_WEIERECC_NIST_P224_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_NIST_P256_SIZE_ + * WeierECC parameter size definitions for NIST P-256 + * @{ */ +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY) +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY) +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP256R1_SIZE_SHAREDSECRET) +#define MCUXCLECC_WEIERECC_NIST_P256_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP256R1_SIZE_SIGNATURE) +/** @} */ /* MCUXCLECC_WEIERECC_NIST_P256_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_NIST_P384_SIZE_ + * WeierECC parameter size definitions for NIST P-384 + * @{ */ +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY) +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY) +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP384R1_SIZE_SHAREDSECRET) +#define MCUXCLECC_WEIERECC_NIST_P384_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP384R1_SIZE_SIGNATURE) +/** @} */ /* MCUXCLECC_WEIERECC_NIST_P384_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_NIST_P521_SIZE_ + * WeierECC parameter size definitions for NIST P-521 + * @{ */ +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIMEP (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_BASEPOINTORDER (MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY) +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_PUBLICKEY (MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY) +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_SECP521R1_SIZE_SHAREDSECRET) +#define MCUXCLECC_WEIERECC_NIST_P521_SIZE_SIGNATURE (MCUXCLECC_WEIERECC_SECP521R1_SIZE_SIGNATURE) +/** @} */ /* MCUXCLECC_WEIERECC_NIST_P521_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP160r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP (20U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER (20U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP192r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP (24U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER (24U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP224r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP (28U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER (28U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP256r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP (32U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER (32U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP320r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP (40U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER (40U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP384r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP (48U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER (48U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_ + * WeierECC parameter size definitions for brainpoolP512r1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP (64U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER (64U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP160t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP (20U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER (20U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP192t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP (24U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER (24U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP224t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP (28U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER (28U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP256t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP (32U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER (32U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP320t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP (40U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER (40U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP384t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP (48U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER (48U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_ */ + +/** + * @addtogroup MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_ + * WeierECC parameter size definitions for brainpoolP512t1 + * @{ */ +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP (64U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER (64U) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_ */ + +/** @addtogroup MCUXCLECC_WEIERECC_MAX_SIZE + * Maximum size definitions for WeierECC parameters (ECC component officially supports up to 640 bit Weierstrass curves) + * @{ */ +#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP (80U) +#define MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER (80U) +#define MCUXCLECC_WEIERECC_MAX_SIZE_PRIVATEKEY (MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER) +#define MCUXCLECC_WEIERECC_MAX_SIZE_PUBLICKEY (2U * MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_MAX_SIZE_SHAREDSECRET (MCUXCLECC_WEIERECC_MAX_SIZE_PRIMEP) +#define MCUXCLECC_WEIERECC_MAX_SIZE_SIGNATURE (2U * MCUXCLECC_WEIERECC_MAX_SIZE_BASEPOINTORDER) +/** @} */ /* MCUXCLECC_WEIERECC_MAX_SIZE */ + +/** @addtogroup MCUXCLECC_EDDSA_ED25519_SIZE_ + * EdDSA parameter size definitions for Ed25519 + * @{ */ +#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP (32u) ///< Byte length of the underlying prime p used in Ed25519. +#define MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER (32u) ///< Byte length of the base point order n used in Ed25519. +#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY (32u) ///< Byte length of an Ed25519 private key. +#define MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEYDATA (96u) ///< Byte length of an Ed25519 private key handle data buffer. +#define MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY (32u) ///< Byte length of an Ed25519 public key. +#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE (64u) ///< Byte length of an Ed25519 signature. +#define MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen) (34u + (contextLen)) ///< Byte length of an Ed25519 prefix. +#define MCUXCLECC_EDDSA_ED25519_SIZE_SIGNATURE_PROTOCOL_DESCRIPTOR(contextLen) \ + (MCUXCLECC_EDDSA_SIGNATURE_PROTOCOL_DESCRIPTOR_SIZE + MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen)) ///< Byte length of an Ed25519 signature protocol descriptor. + +/** @} */ /* MCUXCLECC_EDDSA_ED25519_SIZE_ */ + +/** @addtogroup MCUXCLECC_EDDSA_ED448_SIZE_ + * EdDSA parameter size definitions for Ed448 + * @{ */ +#define MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP (56u) ///< Byte length of the underlying prime p used in Ed448. +#define MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER (56u) ///< Byte length of the base point order n used in Ed448. +#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY (57u) ///< Byte length of an Ed448 private key. +#define MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEYDATA (171u) ///< Byte length of an Ed448 private key handle data buffer. +#define MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY (57u) ///< Byte length of an Ed448 public key. +#define MCUXCLECC_EDDSA_ED448_SIZE_SIGNATURE (114u) ///< Byte length of an Ed448 signature. +/** @} */ /* MCUXCLECC_EDDSA_ED448_SIZE_ */ +/** + * @} + */ /* mcuxClEcc_ParameterSizes */ + +#endif /* MCUXCLECC_PARAMETERSIZES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.h new file mode 100644 index 000000000..f5e610628 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_TWED_INTERNAL_POINTARITHMETICED25519_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_POINTARITHMETICED25519_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_MixedPointAddEd25519[19]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointDoubleEd25519[16]; + +#endif /* MCUXCLECC_TWED_INTERNAL_POINTARITHMETICED25519_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h new file mode 100644 index 000000000..6b31a6c01 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_TWED_INTERNAL_POINTSUBTRACTION_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_POINTSUBTRACTION_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointSubtraction[22]; + +#endif /* MCUXCLECC_TWED_INTERNAL_POINTSUBTRACTION_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h new file mode 100644 index 000000000..cff737dfd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_PointValidation_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_TwEd_Internal_PointValidation_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointValidation[14]; + +#endif /* MCUXCLECC_TWED_INTERNAL_POINTVALIDATION_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h new file mode 100644 index 000000000..20c177bc2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP_H_ +#define MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate[15]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep[29]; + +#endif /* MCUXCLECC_TWED_INTERNAL_VARSCALARMULT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Types.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Types.h new file mode 100644 index 000000000..46b1ae5b4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Types.h @@ -0,0 +1,264 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Types.h + * @brief Type definitions of mcuxClEcc component + */ + + +#ifndef MCUXCLECC_TYPES_H_ +#define MCUXCLECC_TYPES_H_ + + +#include +#include // Exported features flags header +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Return codes of mcuxClEcc */ +/**********************************************************/ +/** + * @defgroup mcuxClEcc_Macros mcuxClEcc_Macros + * @brief Defines all macros of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + +/** + * @brief Type for mcuxClEcc component return codes. + */ +typedef uint32_t mcuxClEcc_Status_t; + +/** + * @brief Deprecated type for mcuxClEcc component return codes. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Status_Protected_t; + + +/** + * @addtogroup MCUXCLECC_STATUS_ + * mcuxClEcc return code definitions + * @{ */ +#define MCUXCLECC_STATUS_OK ((mcuxClEcc_Status_t) 0x04442E03u) ///< Operation was successful. +#define MCUXCLECC_STATUS_INVALID_PARAMS ((mcuxClEcc_Status_t) 0x044453F8u) ///< Parameters are invalid. +#define MCUXCLECC_STATUS_RNG_ERROR ((mcuxClEcc_Status_t) 0x04445334u) ///< Random number (DRBG / PRNG) error (unexpected behavior). +#define MCUXCLECC_STATUS_INVALID_SIGNATURE ((mcuxClEcc_Status_t) 0x04448930u) ///< ECDSA Signature is invalid. +#define MCUXCLECC_STATUS_NEUTRAL_POINT ((mcuxClEcc_Status_t) 0x04448934u) ///< The result of the point operation is the neutral point. +#define MCUXCLECC_STATUS_FAULT_ATTACK ((mcuxClEcc_Status_t) 0x0444F0F0u) ///< Fault attack (unexpected behavior) is detected. +#define MCUXCLECC_STATUS_NOT_SUPPORTED ((mcuxClEcc_Status_t) 0x04445370u) ///< Functionality is not supported. +/** @} */ + +/** + * @addtogroup MCUXCLECC_MONTDH_STATUS_ + * mcuxClEcc_Mont return code definitions + * @{ */ +#define MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP ((mcuxClEcc_Status_t) 0x04445374u) ///< MONTDH public key lies in small subgroup. +/** @} */ /* MCUXCLECC_MONTDH_STATUS_ */ +/** + * @} + */ /* mcuxClEcc_Macros */ + + +/**********************************************************/ +/* Parameter structure of mcuxClEcc APIs */ +/**********************************************************/ +/** + * @defgroup mcuxClEcc_Types mcuxClEcc_Types + * @brief Defines all types of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + + +/** Type for MontDH domain parameters */ +typedef struct mcuxClEcc_MontDH_DomainParams mcuxClEcc_MontDH_DomainParams_t; + + +/** Type for EdDSA domain parameters */ +typedef struct mcuxClEcc_EdDSA_DomainParams mcuxClEcc_EdDSA_DomainParams_t; + +/** + * @brief Forward declaration for EdDSA GenerateKeyPair variant structure + */ +struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor; + +/** + * @brief EdDSA GenerateKeyPair variant descriptor type + */ +typedef struct mcuxClEcc_EdDSA_GenerateKeyPairDescriptor mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t; + +/** + * @brief Forward declaration for EdDSA SignatureProtocol variant structure + */ +struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor; + +/** + * @brief EdDSA SignatureProtocol variant descriptor type + */ +typedef struct mcuxClEcc_EdDSA_SignatureProtocolDescriptor mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t; + + +/** Type for Weierstrass ECC domain parameters */ +typedef struct mcuxClEcc_Weier_DomainParams mcuxClEcc_Weier_DomainParams_t; + +/** Parameter structure of elliptic curve of the form, y^2 = x^3 + a*x + b modulo prime p. + * Each curve parameter is stored as a Big-endian octet string with exact byte length specified. + * For a small parameter, padding zero(s) is placed in the beginning of the octet string. + * This structure contains pointers to the octet strings and the lengths. + */ +typedef struct +{ + const uint8_t *pA; ///< [in] pointer to octet string of curve parameter a (< p), of which the length is byteLenP. + const uint8_t *pB; ///< [in] pointer to octet string of curve parameter b (< p), of which the length is byteLenP. + const uint8_t *pP; ///< [in] pointer to octet string of prime modulus p, of which the length is byteLenP. + ///< The leading byte of this octet string shall be nonzero (i.e., != 0x00). + const uint8_t *pG; ///< [in] pointer to octet string of base point G. Each coordinate is an octet string of the length byteLenP. + ///< The string of x coordinate is followed by the string of y coordinate. + const uint8_t *pN; ///< [in] pointer to octet string of base point order n, of which the length is byteLenN. + ///< The leading byte of this octet string shall be nonzero (i.e., != 0x00). + uint32_t misc; ///< [in] packed lengths, via #mcuxClEcc_DomainParam_misc_Pack: + ///< bits 0~ 7: byteLenP: length of the octet string of curve parameters a, b and p, and x and y coordinates of base point G; + ///< bits 8~15: byteLenN: length of the octet string of curve parameter n; + ///< bits 16~31: reserved. +} mcuxClEcc_DomainParam_t; + +/** mcuxClEcc macros and defines to pack or access components of misc parameter of #mcuxClEcc_DomainParam_t */ +#define mcuxClEcc_DomainParam_misc_Pack(byteLenN, byteLenP) MCUXCLPKC_PACKARGS4(0u, 0u, (uint8_t) byteLenN, (uint8_t) byteLenP) ///< Helper macro to pack misc parameter of #mcuxClEcc_DomainParam_t +#define mcuxClEcc_DomainParam_misc_byteLenP_offset 0 ///< Offset of byteLenP in packed misc parameter of #mcuxClEcc_DomainParam_t +#define mcuxClEcc_DomainParam_misc_byteLenP_mask ((uint32_t) 0x000000FFu) ///< Mask to extract byteLenP from packed misc parameter of #mcuxClEcc_DomainParam_t +#define mcuxClEcc_DomainParam_misc_byteLenN_offset 8 ///< Offset of byteLenN in packed misc parameter of #mcuxClEcc_DomainParam_t +#define mcuxClEcc_DomainParam_misc_byteLenN_mask ((uint32_t) 0x0000FF00u) ///< Mask to extract byteLenN from packed misc parameter of #mcuxClEcc_DomainParam_t + + +/** Parameter structure for function #mcuxClEcc_KeyGen. */ +typedef struct +{ + mcuxClEcc_DomainParam_t curveParam; ///< [in] structure of pointers to curve parameters and length of parameters. + uint8_t * pPrivateKey; ///< [out] pointer to memory area, where the private key will be exported if KeyGen is executed successfully. + ///< It will be stored as a Big-endian octet string of the exact length curveParam.byteLenN. + uint8_t * pPublicKey; ///< [out] pointer to memory area, where the public key will be exported if KeyGen is executed successfully. + ///< It will be stored in the same format as the base point G. + uint32_t optLen; ///< [in] packed options (reserved): + ///< bits 0~31: reserved. **CAUTION** always set optLen = 0. +} mcuxClEcc_KeyGen_Param_t; + +/** Parameter structure for function #mcuxClEcc_Sign. */ +typedef struct +{ + mcuxClEcc_DomainParam_t curveParam; ///< [in] structure of pointers to curve parameters and length of parameters. + const uint8_t * pHash; ///< [in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen). + const uint8_t * pPrivateKey; ///< [in] pointer to octet string of private key, which is of the same format as base point order n. + uint8_t * pSignature; ///< [out] pointer to memory area in which signature R and S will be exported if signature is generated successfully. + ///< They will be stored as Big-endian octet strings of the exact length curveParam.byteLenN. + ///< The string of R is followed by the string of S. + uint32_t optLen; ///< [in] packed options (reserved) and lengths: + ///< bits 0~7: byteLenHash: length of the string of message digest; + ///< bits 8~31: reserved. +} mcuxClEcc_Sign_Param_t; + +/** mcuxClEcc macros and defines to pack or access components of optLen parameter of #mcuxClEcc_Sign_Param_t */ +#define mcuxClEcc_Sign_Param_optLen_Pack(byteLenHash) ((uint32_t) (byteLenHash) & 0xFFu) ///< Helper macro to pack optLen parameter of #mcuxClEcc_Sign_Param_t +#define mcuxClEcc_Sign_Param_optLen_byteLenHash_offset 0 ///< Offset of byteLenHash in packed optLen parameter of #mcuxClEcc_Sign_Param_t +#define mcuxClEcc_Sign_Param_optLen_byteLenHash_mask ((uint32_t) 0x000000FFu) ///< Mask to extract byteLenHash from packed optLen parameter of #mcuxClEcc_Sign_Param_t + +/** Parameter structure for function #mcuxClEcc_Verify. */ +typedef struct +{ + mcuxClEcc_DomainParam_t curveParam; ///< [in] structure of pointers to curve parameters and length of parameters. + const uint8_t * pPrecG; ///< [in] pointer to octet string of pre-computed point of base point G, which is of the same format as base point G. + ///< It is calculated as (2 ^ (nByteLength * 4)) * G. + const uint8_t * pHash; ///< [in] pointer to string of message digest (hash), of which the length is byteLenHash (in optLen). + const uint8_t * pSignature; ///< [in] pointer to octet string of signature R and S. Each of R and S is a Big-endian octet string of the exact length curveParam.byteLenN. + ///< The string of R is followed by the string of S. + const uint8_t * pPublicKey; ///< [in] pointer to octet string of public key, which is of the same format as base point G. + uint8_t * pOutputR; ///< [out] pointer to memory area in which signature R calculated by verify function will be exported if signature is valid. + ///< It will be stored as a Big-endian octet string of the exact length curveParam.byteLenN. + uint32_t optLen; ///< [in] packed options (reserved) and lengths: + ///< bits 0~7: byteLenHash: length of the string of message digest; + ///< bits 8~31: reserved. +} mcuxClEcc_Verify_Param_t; + +/** mcuxClEcc macros and defines to pack or access components of optLen parameter of #mcuxClEcc_Verify_Param_t */ +#define mcuxClEcc_Verify_Param_optLen_Pack(byteLenHash) ((uint32_t) (byteLenHash) & 0xFFu) ///< Helper macro to pack optLen parameter of #mcuxClEcc_Verify_Param_t +#define mcuxClEcc_Verify_Param_optLen_byteLenHash_offset 0 ///< Offset of byteLenHash in packed optLen parameter of #mcuxClEcc_Verify_Param_t +#define mcuxClEcc_Verify_Param_optLen_byteLenHash_mask ((uint32_t) 0x000000FFu) ///< Mask to extract byteLenHash from packed optLen parameter of #mcuxClEcc_Verify_Param_t + +/** Parameter structure for function #mcuxClEcc_PointMult. */ +typedef struct +{ + mcuxClEcc_DomainParam_t curveParam; ///< [in] structure of pointers to curve parameters and length of parameters. + const uint8_t * pScalar; ///< [in] pointer to octet string of scalar d, which is of the same format as base point order n. + const uint8_t * pPoint; ///< [in] pointer to octet string of EC point Q, which is of the same format as base point G. + uint8_t * pResult; ///< [out] pointer to memory area, where the result R = dQ will be exported if PointMult is executed successfully. + ///< It will be stored in the same format as the base point G. + uint32_t optLen; ///< [in] packed options (reserved): + ///< bits 0~31: reserved. **CAUTION** always set optLen = 0. +} mcuxClEcc_PointMult_Param_t; +/** + * @} + */ /* mcuxClEcc_Types */ + +/**********************************************************/ +/* Descriptors of mcuxClEcc APIs */ +/**********************************************************/ +/** + * @defgroup mcuxClEcc_Descriptors mcuxClEcc_Descriptors + * @brief Defines descriptors of @ref mcuxClEcc + * @ingroup mcuxClEcc + * @{ + */ + +/**********************************************************/ +/* Key pair generation descriptors */ +/**********************************************************/ + +/* EdDSA key pair generation descriptor to be used when the private key shall be generated by the + * EdDSA key pair generation function */ +extern const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor; + + +/**********************************************************/ +/* Signature ProtocolDescriptors and ModeDescriptors */ +/**********************************************************/ + +/** + * \brief Ed25519 signature protocol descriptor + * + * NOTE: To be able to perform an Ed25519 signature generation using this mode, the private key handle must be properly linked to a key handle + * for the associated public key using the function mcuxClKey_linkKeyPair. This is necessary to make the public key accessible during an + * Ed25519 signature generation. If this is not satisfied the Ed25519 signature generation will fail. + * If the key pair has been generated using the mcuxClKey_generate_keypair function, this linking step is already + * performed by mcuxClKey_generate_keypair. + */ +extern const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor; + + + + +/** + * @} + */ /* mcuxClEcc_Descriptors */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC.h new file mode 100644 index 000000000..3a2a4fca9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC.h @@ -0,0 +1,124 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC.h + * @brief header of mcuxClEcc functionalities related to ECC protocols based on (short) Weierstrass curves + */ + + +#ifndef MCUXCLECC_WEIERECC_H_ +#define MCUXCLECC_WEIERECC_H_ + + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Structure to define basic custom domain parameters for (short) Weierstrass curves with cofactor 1. + */ +typedef struct { + const uint8_t *pP; + uint32_t pLen; + const uint8_t *pA; + const uint8_t *pB; + const uint8_t *pG; + const uint8_t *pN; + uint32_t nLen; +} mcuxClEcc_Weier_BasicDomainParams_t; + + +/** + * @brief ECC Weierstrass custom domain parameter generation function. + * + * Given pointers and lengths specifying domain parameters of a custom (short) Weierstrass curve with cofactor 1, + * this function generates a corresponding optimized custom domain parameter struct. + * + * @param pSession Handle for the current CL session. + * @param[out] pEccWeierDomainParams Pointer to memory area in which the optimized domain parameters shall be stored. + * @param[in] pEccWeierBasicDomainParams Pointer to struct containing pointers and lengths specifying the custom domain parameters. + * @param[in] options Parameter specifying whether or not the pre-computed point (2 ^ (byteLenN * 4)) * G corresponding to + * the base point G shall be calculated or not, If set to + * - MCUXCLECC_OPTION_GENERATEPRECPOINT_YES, the pre-computed point will be calculated + * - MCUXCLECC_OPTION_GENERATEPRECPOINT_NO, the pre-computed point will not be calculated + * + * @attention the generated optimized domain parameter cannot be copied or moved, + * but shall be used in the original memory address where it is generated. + * + * @return A code-flow protected error code (see @ref MCUXCLECC_STATUS_) + * @retval #MCUXCLECC_STATUS_OK if optimized domain parameters are generated successfully; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if parameters are invalid; + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_GenerateDomainParams) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateDomainParams( + mcuxClSession_Handle_t pSession, + mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams, + mcuxClEcc_Weier_BasicDomainParams_t *pEccWeierBasicDomainParams, + uint32_t options + ); + +#define MCUXCLECC_OPTION_GENERATEPRECPOINT_YES (0x00000001u) +#define MCUXCLECC_OPTION_GENERATEPRECPOINT_NO (0x00000002u) +#define MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK (MCUXCLECC_OPTION_GENERATEPRECPOINT_YES | MCUXCLECC_OPTION_GENERATEPRECPOINT_NO) +#define MCUXCLECC_OPTION_GENERATEPRECPOINT_OFFSET 0u + + +/** + * @brief Key type constructor. + * @api + * + * This function allows to generate custom key types according to the passed \p algoId. + * + * @param[out] customType Handle for the custom key type. + * @param[in] algoId Algorithm identifier specifying the key type descriptor to be generated. The supported algoIds are + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM | MCUXCLKEY_ALGO_ID_KEY_PAIR + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PUBLIC_KEY + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_PRIVATE_KEY + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM | MCUXCLKEY_ALGO_ID_KEY_PAIR + * All other values will trigger an error. + * @param[in] size Algorithm based key size. + * @param[in] pCustomParams Pointer to algorithm based custom parameters. If algoId & MCUXCLKEY_ALGO_ID_ALGO_MASK equals + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM, a pointer to an mcuxClEcc_Weier_BasicDomainParams_t struct + * specifying custom ECC Weierstrass domain parameters + * - MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM, a pointer to an mcuxClEcc_Weier_DomainParams_t struct + * specifying optimized custom ECC Weierstrass domain parameters + * In all other cases, the pointer shall be set to NULL + * @return status + * @retval #MCUXCLECC_STATUS_OK if custom key type is generated successfully; + * @retval #MCUXCLECC_STATUS_INVALID_PARAMS if Parameters are invalid. + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK if fault attack (unexpected behavior) is detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_WeierECC_GenerateCustomKeyType) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateCustomKeyType( + mcuxClKey_CustomType_t customType, + mcuxClKey_AlgorithmId_t algoId, + mcuxClKey_Size_t size, + void *pCustomParams + ); + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLECC_WEIERECC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h new file mode 100644 index 000000000..91fa95efc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP_H_ +#define MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P[4]; + +#endif /* MCUXCLECC_WEIERECC_INTERNAL_GENERATEDOMAINPARAMS_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h new file mode 100644 index 000000000..c305e6b46 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_ConvertPoint_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertJacToAffine[10]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine[11]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_CONVERTPOINT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_FUP.h new file mode 100644 index 000000000..2b552b922 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_UpdateJacobianCoordinates[7]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_KeyGen_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_KeyGen_FUP.h new file mode 100644 index 000000000..9c0e05ad9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_KeyGen_FUP.h @@ -0,0 +1,25 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_KeyGen_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Step7[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34[6]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56[8]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_KEYGEN_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h new file mode 100644 index 000000000..bbd5ae409 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_PointArithmetic_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_DoubleAdd[20]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_RepeatDouble[24]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_POINTARITHMETIC_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointCheck_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointCheck_FUP.h new file mode 100644 index 000000000..4bf41f97f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_PointCheck_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_PointCheck_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointCheckAffNR[10]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_POINTCHECK_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h new file mode 100644 index 000000000..c4c1946f2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h @@ -0,0 +1,25 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP_H_ +#define MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoZPointAddSub[28]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1[20]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP[8]; + +#endif /* MCUXCLECC_WEIER_INTERNAL_SECUREPOINTMULT_COZMONTLADDER_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_KeyGen_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_KeyGen_FUP.h new file mode 100644 index 000000000..c6684e9f8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_KeyGen_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_KeyGen_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_KEYGEN_FUP_H_ +#define MCUXCLECC_WEIER_KEYGEN_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey[7]; + +#endif /* MCUXCLECC_WEIER_KEYGEN_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_PointMult_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_PointMult_FUP.h new file mode 100644 index 000000000..cc0cc2fb1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_PointMult_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_PointMult_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_POINTMULT_FUP_H_ +#define MCUXCLECC_WEIER_POINTMULT_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR[10]; + +#endif /* MCUXCLECC_WEIER_POINTMULT_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Sign_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Sign_FUP.h new file mode 100644 index 000000000..307bb247e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Sign_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Sign_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_SIGN_FUP_H_ +#define MCUXCLECC_WEIER_SIGN_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Sign_CalculateS[13]; + +#endif /* MCUXCLECC_WEIER_SIGN_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Verify_FUP.h b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Verify_FUP.h new file mode 100644 index 000000000..bb8b15027 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/inc/mcuxClEcc_Weier_Verify_FUP.h @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEcc_Weier_Verify_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLECC_WEIER_VERIFY_FUP_H_ +#define MCUXCLECC_WEIER_VERIFY_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR[10]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR[6]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_InitZ_CalcU1U2[6]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_G_to_Prec1[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z[9]; + +#endif /* MCUXCLECC_WEIER_VERIFY_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Constants.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Constants.c new file mode 100644 index 000000000..8447581c6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Constants.c @@ -0,0 +1,2983 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Constants.c + * @brief Provides constants definitions for domain parameters + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + + +/**********************************************************/ +/* MontDh domain parameters */ +/**********************************************************/ + +/* Curve 25519 domain parameters */ + +static const uint8_t pCurve25519_FullP[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x1bu, 0xcau, 0x6bu, 0x28u, 0xafu, 0xa1u, 0xbcu, 0x86u, + 0xedu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x7fu +}; + +static const uint8_t pCurve25519_FullN[MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x1bu, 0x7eu, 0x54u, 0x12u, 0xa3u, 0x1du, 0xb5u, 0xd2u, + 0xedu, 0xd3u, 0xf5u, 0x5cu, 0x1au, 0x63u, 0x12u, 0x58u, 0xd6u, 0x9cu, 0xf7u, 0xa2u, 0xdeu, 0xf9u, 0xdeu, 0x14u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u +}; + +static const uint8_t pCurve25519_R2P[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0xa4u, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve25519_R2N[MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x01u, 0x0fu, 0x9cu, 0x44u, 0xe3u, 0x11u, 0x06u, 0xa4u, 0x47u, 0x93u, 0x85u, 0x68u, 0xa7u, 0x1bu, 0x0eu, 0xd0u, + 0x65u, 0xbeu, 0xf5u, 0x17u, 0xd2u, 0x73u, 0xecu, 0xceu, 0x3du, 0x9au, 0x30u, 0x7cu, 0x1bu, 0x41u, 0x99u, 0x03u +}; + +static const uint8_t pCurve25519_PointGX[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u ,0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve25519_PointGY[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0xD9u, 0xD3u, 0xCEu, 0x7Eu, 0xA2u, 0xC5u, 0xE9u, 0x29u, 0xB2u, 0x61u, 0x7Cu, 0x6Du, 0x7Eu, 0x4Du, 0x3Du, 0x92u, + 0x4Cu, 0xD1u, 0x48u, 0x77u, 0x2Cu, 0xDDu, 0x1Eu, 0xE0u, 0xB4u, 0x86u, 0xA0u, 0xB8u, 0xA1u, 0x19u, 0xAEu, 0x20u +}; + +static const uint8_t pCurve25519_LadderConst[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x42u, 0xDBu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve25519_A[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x06u, 0x6Du, 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve25519_B[MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +/* Curve 448 domain parameters */ + +static const uint8_t pCurve448_FullP[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t pCurve448_FullN[MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0xc5u, 0x8bu, 0x91u, 0xaeu, 0x0fu, 0x44u, 0xbdu, 0x03u, + 0xF3u, 0x44u, 0x58u, 0xABu, 0x92u, 0xC2u, 0x78u, 0x23u, 0x55u, 0x8Fu, 0xC5u, 0x8Du, 0x72u, 0xC2u, + 0x6Cu, 0x21u, 0x90u, 0x36u, 0xD6u, 0xAEu, 0x49u, 0xDBu, 0x4Eu, 0xC4u, 0xE9u, 0x23u, 0xCAu, 0x7Cu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x3Fu +}; + +static const uint8_t pCurve448_R2P[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve448_R2N[MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x60u, 0x9bu, 0x9bu, 0x04u, 0x57u, 0x92u, 0x53u, 0xe3u, 0xd9u, 0x95u, 0xb1u, 0xc1u, 0x4bu, 0x2cu, + 0xf3u, 0x7au, 0x59u, 0x18u, 0xeau, 0x88u, 0x23u, 0xdeu, 0x66u, 0x0du, 0x38u, 0xd8u, 0xe4u, 0x5eu, + 0x72u, 0xcfu, 0x17u, 0xaeu, 0x44u, 0x7cu, 0xc4u, 0xa3u, 0x4bu, 0xc1u, 0x9cu, 0x1au, 0xafu, 0x70u, + 0xd0u, 0xe4u, 0xb7u, 0xbcu, 0x52u, 0x20u, 0x29u, 0xb7u, 0x23u, 0xf8u, 0x39u, 0xa9u, 0x02u, 0x34u +}; + +static const uint8_t pCurve448_LadderConst[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0xAAu, 0x98u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve448_PointGX[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u ,0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u ,0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u ,0x00u, 0x00u +}; + +static const uint8_t pCurve448_PointGY[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x1au, 0x5bu, 0x7bu, 0x45u, 0x3du, 0x22u, 0xd7u, 0x6fu, 0xf7u, 0x7au, 0x67u, 0x50u, 0xb1u, 0xc4u, + 0x12u, 0x13u, 0x21u, 0x0du, 0x43u, 0x46u, 0x23u, 0x7eu, 0x02u, 0xb8u, 0xedu, 0xf6u, 0xf3u, 0x8du, + 0xc2u, 0x5du, 0xf7u, 0x60u, 0xd0u, 0x45u, 0x55u, 0xf5u, 0x34u, 0x5du, 0xaeu, 0xcbu, 0xceu, 0x6fu, + 0x32u, 0x58u, 0x6eu, 0xabu, 0x98u, 0x6cu, 0xf6u, 0xb1u, 0xf5u, 0x95u, 0x12u, 0x5du, 0x23u, 0x7du +}; + +static const uint8_t pCurve448_A[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0xA6u, 0x62u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pCurve448_B[MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve25519 __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve25519"))) = +{ + .common.byteLenP = MCUXCLECC_MONT_CURVE25519_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_MONT_CURVE25519_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &pCurve25519_FullP, + .common.pFullModulusN = (uint8_t *) &pCurve25519_FullN, + .common.pR2P = (uint8_t *) &pCurve25519_R2P, + .common.pR2N = (uint8_t *) &pCurve25519_R2N, + .common.pCurveParam1 = (uint8_t *) &pCurve25519_A, + .common.pCurveParam2 = (uint8_t *) &pCurve25519_B, + .common.pGx = (uint8_t *) &pCurve25519_PointGX, + .common.pGy = (uint8_t *) &pCurve25519_PointGY, + .common.pPrecPoints = NULL, + .common.pLadderConst = (uint8_t *) &pCurve25519_LadderConst, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL, + .c = 3u, + .t = 254u +}; + +const mcuxClEcc_MontDH_DomainParams_t mcuxClEcc_MontDH_DomainParams_Curve448 __attribute__((section(".rodata.curve.mcuxClEcc_MontDH_Curve_448"))) = +{ + .common.byteLenP = MCUXCLECC_MONT_CURVE448_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_MONT_CURVE448_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &pCurve448_FullP, + .common.pFullModulusN = (uint8_t *) &pCurve448_FullN, + .common.pR2P = (uint8_t *) &pCurve448_R2P, + .common.pR2N = (uint8_t *) &pCurve448_R2N, + .common.pCurveParam1 = (uint8_t *) &pCurve448_A, + .common.pCurveParam2 = (uint8_t *) &pCurve448_B, + .common.pGx = (uint8_t *) &pCurve448_PointGX, + .common.pGy = (uint8_t *) &pCurve448_PointGY, + .common.pPrecPoints = NULL, + .common.pLadderConst = (uint8_t *) &pCurve448_LadderConst, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL, + .c = 2u, + .t = 447u +}; + + +/**********************************************************/ +/* Weierstrass curve domain parameters */ +/**********************************************************/ + +/**********************************************************/ +/* secp192r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP192R1_P[MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* pDash = 0x1 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF [BE] */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP192R1_N[MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* nDash = 0x882672070ddbcf2f [BE] */ + 0x2Fu, 0xCFu, 0xDBu, 0x0Du, 0x07u, 0x72u, 0x26u, 0x88u, + + /* n = 0xFFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831 [BE] */ + 0x31u, 0x28u, 0xD2u, 0xB4u, 0xB1u, 0xC9u, 0x6Bu, 0x14u, + 0x36u, 0xF8u, 0xDEu, 0x99u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP192R1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* A = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC [BE] */ + 0xFCu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP192R1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* B = 0x64210519E59C80E70FA7E9AB72243049FEB8DEECC146B9B1 [BE] */ + 0xB1u, 0xB9u, 0x46u, 0xC1u, 0xECu, 0xDEu, 0xB8u, 0xFEu, + 0x49u, 0x30u, 0x24u, 0x72u, 0xABu, 0xE9u, 0xA7u, 0x0Fu, + 0xE7u, 0x80u, 0x9Cu, 0xE5u, 0x19u, 0x05u, 0x21u, 0x64u +}; + +static const uint8_t SECP192R1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* PointGX = 0x188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012 [BE] */ + 0x12u, 0x10u, 0xFFu, 0x82u, 0xFDu, 0x0Au, 0xFFu, 0xF4u, + 0x00u, 0x88u, 0xA1u, 0x43u, 0xEBu, 0x20u, 0xBFu, 0x7Cu, + 0xF6u, 0x90u, 0x30u, 0xB0u, 0x0Eu, 0xA8u, 0x8Du, 0x18u +}; + +static const uint8_t SECP192R1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* PointGY = 0x07192B95FFC8DA78631011ED6B24CDD573F977A11E794811 [BE] */ + 0x11u, 0x48u, 0x79u, 0x1Eu, 0xA1u, 0x77u, 0xF9u, 0x73u, + 0xD5u, 0xCDu, 0x24u, 0x6Bu, 0xEDu, 0x11u, 0x10u, 0x63u, + 0x78u, 0xDAu, 0xC8u, 0xFFu, 0x95u, 0x2Bu, 0x19u, 0x07u +}; + +static const uint8_t SECP192R1_PRECG[MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* 0x51A581D9184AC7374730D4F480D1090BB19963D8C0A1E340 [BE] */ + 0x40u, 0xE3u, 0xA1u, 0xC0u, 0xD8u, 0x63u, 0x99u, 0xB1u, + 0x0Bu, 0x09u, 0xD1u, 0x80u, 0xF4u, 0xD4u, 0x30u, 0x47u, + 0x37u, 0xC7u, 0x4Au, 0x18u, 0xD9u, 0x81u, 0xA5u, 0x51u, + /* 0x5BD81EE2E0BB9F6E7CDFCEA02F683F16ECC56731E69912A5 [BE] */ + 0xA5u, 0x12u, 0x99u, 0xE6u, 0x31u, 0x67u, 0xC5u, 0xECu, + 0x16u, 0x3Fu, 0x68u, 0x2Fu, 0xA0u, 0xCEu, 0xDFu, 0x7Cu, + 0x6Eu, 0x9Fu, 0xBBu, 0xE0u, 0xE2u, 0x1Eu, 0xD8u, 0x5Bu +}; + +static const uint8_t SECP192R1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* R2P = 0x100000000000000020000000000000001 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP192R1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + /* R2N = 0x28be5677ea0581a24696ea5bbb3a6beece66baccdeb35961 [BE] */ + 0x61u, 0x59u, 0xB3u, 0xDEu, 0xCCu, 0xBAu, 0x66u, 0xCEu, + 0xEEu, 0x6Bu, 0x3Au, 0xBBu, 0x5Bu, 0xEAu, 0x96u, 0x46u, + 0xA2u, 0x81u, 0x05u, 0xEAu, 0x77u, 0x56u, 0xBEu, 0x28u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP192R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP192R1_P, + .common.pFullModulusN = (uint8_t *) &SECP192R1_N, + .common.pR2P = (uint8_t *) &SECP192R1_R2P, + .common.pR2N = (uint8_t *) &SECP192R1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP192R1_A, + .common.pCurveParam2 = (uint8_t *) &SECP192R1_B, + .common.pGx = (uint8_t *) &SECP192R1_GX, + .common.pGy = (uint8_t *) &SECP192R1_GY, + .common.pPrecPoints = (uint8_t *) &SECP192R1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp160k1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP160k1_P[MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* pDash = 0x63c361d4b4ab2745 [BE] */ + 0x45u, 0x27u, 0xABu, 0xB4u, 0xD4u, 0x61u, 0xC3u, 0x63u, + + /* p = 0xfffffffffffffffffffffffffffffffeffffac73 [BE] */ + 0x73u, 0xACu, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP160k1_N[MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* nDash = 0xd10d67b535931785 [BE] */ + 0x85u, 0x17u, 0x93u, 0x35u, 0xB5u, 0x67u, 0x0Du, 0xD1u, + + /* n = 0x0100000000000000000001b8fa16dfab9aca16b6b3 [BE] */ + 0xB3u, 0xB6u, 0x16u, 0xCAu, 0x9Au, 0xABu, 0xDFu, 0x16u, + 0xFAu, 0xB8u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u +}; + +static const uint8_t SECP160k1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* A = 0x0000000000000000000000000000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP160k1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* B = 0x0000000000000000000000000000000000000007 [BE] */ + 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP160k1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* PointGX = 0x3b4c382ce37aa192a4019e763036f4f5dd4d7ebb [BE] */ + 0xBBu, 0x7Eu, 0x4Du, 0xDDu, 0xF5u, 0xF4u, 0x36u, 0x30u, + 0x76u, 0x9Eu, 0x01u, 0xA4u, 0x92u, 0xA1u, 0x7Au, 0xE3u, + 0x2Cu, 0x38u, 0x4Cu, 0x3Bu +}; + +static const uint8_t SECP160k1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* PointGY = 0x938cf935318fdced6bc28286531733c3f03c4fee [BE] */ + 0xEEu, 0x4Fu, 0x3Cu, 0xF0u, 0xC3u, 0x33u, 0x17u, 0x53u, + 0x86u, 0x82u, 0xC2u, 0x6Bu, 0xEDu, 0xDCu, 0x8Fu, 0x31u, + 0x35u, 0xF9u, 0x8Cu, 0x93u +}; + +static const uint8_t SECP160k1_PRECG[MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* 0xaf188ba8029e41acaf9e8000aa6337e58852a9c7 [BE] */ + 0xC7u, 0xA9u, 0x52u, 0x88u, 0xE5u, 0x37u, 0x63u, 0xAAu, + 0x00u, 0x80u, 0x9Eu, 0xAFu, 0xACu, 0x41u, 0x9Eu, 0x02u, + 0xA8u, 0x8Bu, 0x18u, 0xAFu, + /* 0x879472ab4e43293adda8793edf57b6b6961dda64 [BE] */ + 0x64u, 0xDAu, 0x1Du, 0x96u, 0xB6u, 0xB6u, 0x57u, 0xDFu, + 0x3Eu, 0x79u, 0xA8u, 0xDDu, 0x3Au, 0x29u, 0x43u, 0x4Eu, + 0xABu, 0x72u, 0x94u, 0x87u +}; + +static const uint8_t SECP160k1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* R2P = 0x10000a71a1b44bba90000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xA9u, 0xBBu, 0x44u, 0x1Bu, 0x1Au, 0xA7u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP160k1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + /* R2N = 0xcdcf2babdfe35d2f4d8a8aad0f8494330e687aaf [BE] */ + 0xAFu, 0x7Au, 0x68u, 0x0Eu, 0x33u, 0x94u, 0x84u, 0x0Fu, + 0xADu, 0x8Au, 0x8Au, 0x4Du, 0x2Fu, 0x5Du, 0xE3u, 0xDFu, + 0xABu, 0x2Bu, 0xCFu, 0xCDu, 0x00u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp160k1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp160k1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP160K1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP160k1_P, + .common.pFullModulusN = (uint8_t *) &SECP160k1_N, + .common.pR2P = (uint8_t *) &SECP160k1_R2P, + .common.pR2N = (uint8_t *) &SECP160k1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP160k1_A, + .common.pCurveParam2 = (uint8_t *) &SECP160k1_B, + .common.pGx = (uint8_t *) &SECP160k1_GX, + .common.pGy = (uint8_t *) &SECP160k1_GY, + .common.pPrecPoints = (uint8_t *) &SECP160k1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp192k1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP192K1_P[MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* pDash 0xf27ae55b7446d879 [BE] */ + 0x79u, 0xD8u, 0x46u, 0x74u, 0x5Bu, 0xE5u, 0x7A, 0xF2u, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37 [BE] */ + 0x37u, 0xEEu, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP192K1_N[MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* nDash 0x8203e3a8560472bb [BE] */ + 0xBBu, 0x72u, 0x04u, 0x56u, 0xA8u, 0xE3u, 0x03u, 0x82u, + + /* n = 0xFFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D [BE] */ + 0x8Du, 0xFDu, 0xDEu, 0x74u, 0x6Au, 0x46u, 0x69u, 0x0Fu, + 0x17u, 0xFCu, 0xF2u, 0x26u, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP192K1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* A = 0x000000000000000000000000000000000000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP192K1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* B = 0x000000000000000000000000000000000000000000000003 [BE] */ + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP192K1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* PointGX = 0xDB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D [BE] */ + 0x7Du, 0x6Cu, 0xE0u, 0xEAu, 0xB1u, 0xD1u, 0xA5u, 0x1Du, + 0x34u, 0xF4u, 0xB7u, 0x80u, 0x02u, 0x7Du, 0xB0u, 0x26u, + 0xAEu, 0xE9u, 0x57u, 0xC0u, 0x0Eu, 0xF1u, 0x4Fu, 0xDBu +}; + +static const uint8_t SECP192K1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* PointGY = 0x9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D [BE] */ + 0x9Du, 0x2Fu, 0x5Eu, 0xD9u, 0x88u, 0xAAu, 0x82u, 0x40u, + 0x34u, 0x86u, 0xBEu, 0x15u, 0xD0u, 0x63u, 0x41u, 0x84u, + 0xA7u, 0x28u, 0x56u, 0x9Cu, 0x6Du, 0x2Fu, 0x2Fu, 0x9Bu +}; + +static const uint8_t SECP192K1_PRECG[MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* 0x79C8D6B2F3B65531119C7C2BA6FD6C4A4A0A43C83C3803C1 [BE] */ + 0xC1u, 0x03u, 0x38u, 0x3Cu, 0xC8u, 0x43u, 0x0Au, 0x4Au, + 0x4Au, 0x6Cu, 0xFDu, 0xA6u, 0x2Bu, 0x7Cu, 0x9Cu, 0x11u, + 0x31u, 0x55u, 0xB6u, 0xF3u, 0xB2u, 0xD6u, 0xC8u, 0x79u, + /* 0xEB64375BE3A1306E71A2E4D22EFDCE4C3962A2ABB7488B1E [BE] */ + 0x1Eu, 0x8Bu, 0x48u, 0xB7u, 0xABu, 0xA2u, 0x62u, 0x39u, + 0x4Cu, 0xCEu, 0xFDu, 0x2Eu, 0xD2u, 0xE4u, 0xA2u, 0x71u, + 0x6Eu, 0x30u, 0xA1u, 0xE3u, 0x5Bu, 0x37u, 0x64u, 0xEBu +}; + +static const uint8_t SECP192K1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* R2P = 0x100002392013c4fd1 [BE] */ + 0xD1u, 0x4Fu, 0x3Cu, 0x01u, 0x92u, 0x23u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP192K1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + /* R2N = 0x6a21191c2ec4b2b1f0f4f172195e97e2461c1989250f0702 [BE] */ + 0x02u, 0x07u, 0x0Fu, 0x25u, 0x89u, 0x19u, 0x1Cu, 0x46u, + 0xE2u, 0x97u, 0x5Eu, 0x19u, 0x72u, 0xF1u, 0xF4u, 0xF0u, + 0xB1u, 0xB2u, 0xC4u, 0x2Eu, 0x1Cu, 0x19u, 0x21u, 0x6Au +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp192k1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp192k1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP192K1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP192K1_P, + .common.pFullModulusN = (uint8_t *) &SECP192K1_N, + .common.pR2P = (uint8_t *) &SECP192K1_R2P, + .common.pR2N = (uint8_t *) &SECP192K1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP192K1_A, + .common.pCurveParam2 = (uint8_t *) &SECP192K1_B, + .common.pGx = (uint8_t *) &SECP192K1_GX, + .common.pGy = (uint8_t *) &SECP192K1_GY, + .common.pPrecPoints = (uint8_t *) &SECP192K1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + + + + +/**********************************************************/ +/* secp224r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP224R1_P[MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* pDash 0xffffffffffffffff [BE] */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP224R1_N[MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* nDash 0xd6e242706a1fc2eb [BE] */ + 0xEBu, 0xC2u, 0x1Fu, 0x6Au, 0x70u, 0x42u, 0xE2u, 0xD6, + + /* n = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D [BE] */ + 0x3Du, 0x2Au, 0x5Cu, 0x5Cu, 0x45u, 0x29u, 0xDDu, 0x13u, + 0x3Eu, 0xF0u, 0xB8u, 0xE0u, 0xA2u, 0x16u, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP224R1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* A = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE [BE] */ + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP224R1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* B = 0xB4050A850C04B3ABF54132565044B0B7D7BFD8BA270B39432355FFB4 [BE] */ + 0xB4u, 0xFFu, 0x55u, 0x23u, 0x43u, 0x39u, 0x0Bu, 0x27u, + 0xBAu, 0xD8u, 0xBFu, 0xD7u, 0xB7u, 0xB0u, 0x44u, 0x50u, + 0x56u, 0x32u, 0x41u, 0xF5u, 0xABu, 0xB3u, 0x04u, 0x0Cu, + 0x85u, 0x0Au, 0x05u, 0xB4u +}; + +static const uint8_t SECP224R1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* PointGX = 0xB70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21 [BE] */ + 0x21u, 0x1Du, 0x5Cu, 0x11u, 0xD6u, 0x80u, 0x32u, 0x34u, + 0x22u, 0x11u, 0xC2u, 0x56u, 0xD3u, 0xC1u, 0x03u, 0x4Au, + 0xB9u, 0x90u, 0x13u, 0x32u, 0x7Fu, 0xBFu, 0xB4u, 0x6Bu, + 0xBDu, 0x0Cu, 0x0Eu, 0xB7u +}; + +static const uint8_t SECP224R1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* PointGY = 0xBD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34 [BE] */ + 0x34u, 0x7Eu, 0x00u, 0x85u, 0x99u, 0x81u, 0xD5u, 0x44u, + 0x64u, 0x47u, 0x07u, 0x5Au, 0xA0u, 0x75u, 0x43u, 0xCDu, + 0xE6u, 0xDFu, 0x22u, 0x4Cu, 0xFBu, 0x23u, 0xF7u, 0xB5u, + 0x88u, 0x63u, 0x37u, 0xBDu +}; + +static const uint8_t SECP224R1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* R2P = 0xfffffffffffffffe00000000ffffffff00000000ffffffff00000001 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP224R1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* R2N = 0xb1e979616ad15f7cd9714856abc8ff5931d63f4b29947a695f517d15 [BE] */ + 0x15u, 0x7Du, 0x51u, 0x5Fu, 0x69u, 0x7Au, 0x94u, 0x29u, + 0x4Bu, 0x3Fu, 0xD6u, 0x31u, 0x59u, 0xFFu, 0xC8u, 0xABu, + 0x56u, 0x48u, 0x71u, 0xD9u, 0x7Cu, 0x5Fu, 0xD1u, 0x6Au, + 0x61u, 0x79u, 0xE9u, 0xB1u +}; + +static const uint8_t SECP224R1_PRECG[MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + /* 0x0499AA8A5F8EBEEFEC27A4E13A0B91FB2991FAB0A00641966CAB26E3 [BE] */ + 0xE3u, 0x26u, 0xABu, 0x6Cu, 0x96u, 0x41u, 0x06u, 0xA0u, + 0xB0u, 0xFAu, 0x91u, 0x29u, 0xFBu, 0x91u, 0x0Bu, 0x3Au, + 0xE1u, 0xA4u, 0x27u, 0xECu, 0xEFu, 0xBEu, 0x8Eu, 0x5Fu, + 0x8Au, 0xAAu, 0x99u, 0x04u, + /* 0x6916F6D4338C5B81D77AAE82F70684D929610D54507510407766AF5D [BE] */ + 0x5Du, 0xAFu, 0x66u, 0x77u, 0x40u, 0x10u, 0x75u, 0x50u, + 0x54u, 0x0Du, 0x61u, 0x29u, 0xD9u, 0x84u, 0x06u, 0xF7u, + 0x82u, 0xAEu, 0x7Au, 0xD7u, 0x81u, 0x5Bu, 0x8Cu, 0x33u, + 0xD4u, 0xF6u, 0x16u, 0x69u +}; +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP224R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP224R1_P, + .common.pFullModulusN = (uint8_t *) &SECP224R1_N, + .common.pR2P = (uint8_t *) &SECP224R1_R2P, + .common.pR2N = (uint8_t *) &SECP224R1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP224R1_A, + .common.pCurveParam2 = (uint8_t *) &SECP224R1_B, + .common.pGx = (uint8_t *) &SECP224R1_GX, + .common.pGy = (uint8_t *) &SECP224R1_GY, + .common.pPrecPoints = (uint8_t *) &SECP224R1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp224k1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP224K1_P[MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* pDash 0x5a92a00a198d139b [BE] */ + 0x9Bu, 0x13u, 0x8Du, 0x19u, 0x0Au, 0xA0u, 0x92u, 0x5Au, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D [BE] */ + 0x6Du, 0xE5u, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP224K1_N[MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* nDash 0x43fa520244c1a039 [BE] */ + 0x39u, 0xA0u, 0xC1u, 0x44u, 0x02u, 0x52u, 0xFAu, 0x43u, + + /* n = 0x010000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7 [BE] */ + 0xF7u, 0xB1u, 0x9Fu, 0x76u, 0x71u, 0xA9u, 0xF0u, 0xCAu, + 0x84u, 0x61u, 0xECu, 0xD2u, 0xE8u, 0xDCu, 0x01u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u +}; + +static const uint8_t SECP224K1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* A = 0x00000000000000000000000000000000000000000000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP224K1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* B = 0x00000000000000000000000000000000000000000000000000000005 [BE] */ + 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP224K1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* PointGX = 0xA1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C [BE] */ + 0x5Cu, 0xA4u, 0xB7u, 0xB6u, 0x0Eu, 0x65u, 0x7Eu, 0x0Fu, + 0xA9u, 0x75u, 0x70u, 0xE4u, 0xE9u, 0x67u, 0xA4u, 0x69u, + 0xA1u, 0x28u, 0xFCu, 0x30u, 0xDFu, 0x99u, 0xF0u, 0x4Du, + 0x33u, 0x5Bu, 0x45u, 0xA1u +}; + +static const uint8_t SECP224K1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* PointGY = 0x7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5 [BE] */ + 0xA5u, 0x61u, 0x6Du, 0x55u, 0xDBu, 0x4Bu, 0xCAu, 0xE2u, + 0x59u, 0xBDu, 0xB0u, 0xC0u, 0xF7u, 0x19u, 0xE3u, 0xF7u, + 0xD6u, 0xFBu, 0xCAu, 0x82u, 0x42u, 0x34u, 0xBAu, 0x7Fu, + 0xEDu, 0x9Fu, 0x08u, 0x7Eu +}; + +static const uint8_t SECP224K1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* R2N = 0x993ff72bb882bd88bbff32e48be0320816f60af534ce24fbec9feaa0 [BE] */ + 0xA0u, 0xEAu, 0x9Fu, 0xECu, 0xFBu, 0x24u, 0xCEu, 0x34u, + 0xF5u, 0x0Au, 0xF6u, 0x16u, 0x08u, 0x32u, 0xE0u, 0x8Bu, + 0xE4u, 0x32u, 0xFFu, 0xBBu, 0x88u, 0xBDu, 0x82u, 0xB8u, + 0x2Bu, 0xF7u, 0x3Fu, 0x99u, 0x00u +}; + +static const uint8_t SECP224K1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* R2P = 0x10000352602c230690000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x69u, 0x30u, 0xC2u, 0x02u, 0x26u, 0x35u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP224K1_PRECG[MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + /* 0x79d91a4a04c6421d20e59c5b2f9e62d128375d5c322fe03a5646df86 [BE] */ + 0x86u, 0xDFu, 0x46u, 0x56u, 0x3Au, 0xE0u, 0x2Fu, 0x32u, + 0x5Cu, 0x5Du, 0x37u, 0x28u, 0xD1u, 0x62u, 0x9Eu, 0x2Fu, + 0x5Bu, 0x9Cu, 0xE5u, 0x20u, 0x1Du, 0x42u, 0xC6u, 0x04u, + 0x4Au, 0x1Au, 0xD9u, 0x79u, + /* 0xfb58bafefb84206a651d0dcc71442874537dd82e9b88d5432a4ab901 [BE] */ + 0x01u, 0xB9u, 0x4Au, 0x2Au, 0x43u, 0xD5u, 0x88u, 0x9Bu, + 0x2Eu, 0xD8u, 0x7Du, 0x53u, 0x74u, 0x28u, 0x44u, 0x71u, + 0xCCu, 0x0Du, 0x1Du, 0x65u, 0x6Au, 0x20u, 0x84u, 0xFBu, + 0xFEu, 0xBAu, 0x58u, 0xFBU +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp224k1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp224k1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP224K1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP224K1_P, + .common.pFullModulusN = (uint8_t *) &SECP224K1_N, + .common.pR2P = (uint8_t *) &SECP224K1_R2P, + .common.pR2N = (uint8_t *) &SECP224K1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP224K1_A, + .common.pCurveParam2 = (uint8_t *) &SECP224K1_B, + .common.pGx = (uint8_t *) &SECP224K1_GX, + .common.pGy = (uint8_t *) &SECP224K1_GY, + .common.pPrecPoints = (uint8_t *) &SECP224K1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp256r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP256R1_P[MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* pDash 0x1 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + + /* p = 0xFFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF [BE] */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP256R1_N[MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* nDash 0xccd1c8aaee00bc4f [BE] */ + 0x4Fu, 0xBCu, 0x00u, 0xEEu, 0xAAu, 0xC8u, 0xD1u, 0xCCu, + + /* n = 0xFFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551 [BE] */ + 0x51u, 0x25u, 0x63u, 0xFCu, 0xC2u, 0xCAu, 0xB9u, 0xF3u, + 0x84u, 0x9Eu, 0x17u, 0xA7u, 0xADu, 0xFAu, 0xE6u, 0xBCu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP256R1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* A = 0xFFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC [BE] */ + 0xFCu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP256R1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* B = 0x5AC635D8AA3A93E7B3EBBD55769886BC651D06B0CC53B0F63BCE3C3E27D2604B [BE] */ + 0x4Bu, 0x60u, 0xD2u, 0x27u, 0x3Eu, 0x3Cu, 0xCEu, 0x3Bu, + 0xF6u, 0xB0u, 0x53u, 0xCCu, 0xB0u, 0x06u, 0x1Du, 0x65u, + 0xBCu, 0x86u, 0x98u, 0x76u, 0x55u, 0xBDu, 0xEBu, 0xB3u, + 0xE7u, 0x93u, 0x3Au, 0xAAu, 0xD8u, 0x35u, 0xC6u, 0x5Au +}; + +static const uint8_t SECP256R1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* PointGX = 0x6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296 [BE] */ + 0x96u, 0xC2u, 0x98u, 0xD8u, 0x45u, 0x39u, 0xA1u, 0xF4u, + 0xA0u, 0x33u, 0xEBu, 0x2Du, 0x81u, 0x7Du, 0x03u, 0x77u, + 0xF2u, 0x40u, 0xA4u, 0x63u, 0xE5u, 0xE6u, 0xBCu, 0xF8u, + 0x47u, 0x42u, 0x2Cu, 0xE1u, 0xF2u, 0xD1u, 0x17u, 0x6Bu +}; + +static const uint8_t SECP256R1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* PointGY = 0x4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5 [BE] */ + 0xF5u, 0x51u, 0xBFu, 0x37u, 0x68u, 0x40u, 0xB6u, 0xCBu, + 0xCEu, 0x5Eu, 0x31u, 0x6Bu, 0x57u, 0x33u, 0xCEu, 0x2Bu, + 0x16u, 0x9Eu, 0x0Fu, 0x7Cu, 0x4Au, 0xEBu, 0xE7u, 0x8Eu, + 0x9Bu, 0x7Fu, 0x1Au, 0xFEu, 0xE2u, 0x42u, 0xE3u, 0x4Fu +}; + +static const uint8_t SECP256R1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* R2P = 0x4fffffffdfffffffffffffffefffffffbffffffff0000000000000003 [BE] */ + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFBu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFDu, 0xFFu, 0xFFu, 0xFFu, 0x04u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP256R1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* R2N = 0x66e12d94f3d956202845b2392b6bec594699799c49bd6fa683244c95be79eea2 [BE] */ + 0xA2u, 0xEEu, 0x79u, 0xBEu, 0x95u, 0x4Cu, 0x24u, 0x83u, + 0xA6u, 0x6Fu, 0xBDu, 0x49u, 0x9Cu, 0x79u, 0x99u, 0x46u, + 0x59u, 0xECu, 0x6Bu, 0x2Bu, 0x39u, 0xB2u, 0x45u, 0x28u, + 0x20u, 0x56u, 0xD9u, 0xF3u, 0x94u, 0x2Du, 0xE1u, 0x66u +}; + +static const uint8_t SECP256R1_PRECG[MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + /* 0x447D739BEEDB5E67FB982FD588C6766EFC35FF7DC297EAC357C84FC9D789BD85 [BE] */ + 0x85u, 0xBDu, 0x89u, 0xD7u, 0xC9u, 0x4Fu, 0xC8u, 0x57u, + 0xC3u, 0xEAu, 0x97u, 0xC2u, 0x7Du, 0xFFu, 0x35u, 0xFCu, + 0x6Eu, 0x76u, 0xC6u, 0x88u, 0xD5u, 0x2Fu, 0x98u, 0xFBu, + 0x67u, 0x5Eu, 0xDBu, 0xEEu, 0x9Bu, 0x73u, 0x7Du, 0x44u, + /* 0x2D4825AB834131EEE12E9D953A4AAFF73D349B95A7FAE5000C7E33C972E25B32 [BE] */ + 0x32u, 0x5Bu, 0xE2u, 0x72u, 0xC9u, 0x33u, 0x7Eu, 0x0Cu, + 0x00u, 0xE5u, 0xFAu, 0xA7u, 0x95u, 0x9Bu, 0x34u, 0x3Du, + 0xF7u, 0xAFu, 0x4Au, 0x3Au, 0x95u, 0x9Du, 0x2Eu, 0xE1u, + 0xEEu, 0x31u, 0x41u, 0x83u, 0xABu, 0x25u, 0x48u, 0x2Du +}; +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP256R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP256R1_P, + .common.pFullModulusN = (uint8_t *) &SECP256R1_N, + .common.pR2P = (uint8_t *) &SECP256R1_R2P, + .common.pR2N = (uint8_t *) &SECP256R1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP256R1_A, + .common.pCurveParam2 = (uint8_t *) &SECP256R1_B, + .common.pGx = (uint8_t *) &SECP256R1_GX, + .common.pGy = (uint8_t *) &SECP256R1_GY, + .common.pPrecPoints = (uint8_t *) &SECP256R1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp256k1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP256K1_P[MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* pDash 0xd838091dd2253531 [BE] */ + 0x31u, 0x35u, 0x25u, 0xD2u, 0x1Du, 0x09u, 0x38u, 0xD8u, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F [BE] */ + 0x2Fu, 0xFCu, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP256K1_N[MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* nDash 0x4b0dff665588b13f [BE] */ + 0x3Fu, 0xB1u, 0x88u, 0x55u, 0x66u, 0xFFu, 0x0Du, 0x4Bu, + + /* n = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141 [BE] */ + 0x41u, 0x41u, 0x36u, 0xD0u, 0x8Cu, 0x5Eu, 0xD2u, 0xBFu, + 0x3Bu, 0xA0u, 0x48u, 0xAFu, 0xE6u, 0xDCu, 0xAEu, 0xBAu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP256K1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* A = 0x0000000000000000000000000000000000000000000000000000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP256K1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* B = 0x0000000000000000000000000000000000000000000000000000000000000007 [BE] */ + 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP256K1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* PointGX = 0x79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798 [BE] */ + 0x98u, 0x17u, 0xF8u, 0x16u, 0x5Bu, 0x81u, 0xF2u, 0x59u, + 0xD9u, 0x28u, 0xCEu, 0x2Du, 0xDBu, 0xFCu, 0x9Bu, 0x02u, + 0x07u, 0x0Bu, 0x87u, 0xCEu, 0x95u, 0x62u, 0xA0u, 0x55u, + 0xACu, 0xBBu, 0xDCu, 0xF9u, 0x7Eu, 0x66u, 0xBEu, 0x79u +}; + +static const uint8_t SECP256K1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* PointGY = 0x483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8 [BE] */ + 0xB8u, 0xD4u, 0x10u, 0xFBu, 0x8Fu, 0xD0u, 0x47u, 0x9Cu, + 0x19u, 0x54u, 0x85u, 0xA6u, 0x48u, 0xB4u, 0x17u, 0xFDu, + 0xA8u, 0x08u, 0x11u, 0x0Eu, 0xFCu, 0xFBu, 0xA4u, 0x5Du, + 0x65u, 0xC4u, 0xA3u, 0x26u, 0x77u, 0xDAu, 0x3Au, 0x48u +}; + +static const uint8_t SECP256K1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* R2P = 0x1000007a2000e90a1 [BE] */ + 0xA1u, 0x90u, 0x0Eu, 0x00u, 0xA2u, 0x07u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP256K1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* R2N = 0x9d671cd581c69bc5e697f5e45bcd07c6741496c20e7cf878896cf21467d7d140 [BE] */ + 0x40u, 0xD1u, 0xD7u, 0x67u, 0x14u, 0xF2u, 0x6Cu, 0x89u, + 0x78u, 0xF8u, 0x7Cu, 0x0Eu, 0xC2u, 0x96u, 0x14u, 0x74u, + 0xC6u, 0x07u, 0xCDu, 0x5Bu, 0xE4u, 0xF5u, 0x97u, 0xE6u, + 0xC5u, 0x9Bu, 0xC6u, 0x81u, 0xD5u, 0x1Cu, 0x67u, 0x9Du +}; + +static const uint8_t SECP256K1_PRECG[MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + /* 0x8F68B9D2F63B5F339239C1AD981F162EE88C5678723EA3351B7B444C9EC4C0DA [BE] */ + 0xDAu, 0xC0u, 0xC4u, 0x9Eu, 0x4Cu, 0x44u, 0x7Bu, 0x1Bu, + 0x35u, 0xA3u, 0x3Eu, 0x72u, 0x78u, 0x56u, 0x8Cu, 0xE8u, + 0x2Eu, 0x16u, 0x1Fu, 0x98u, 0xADu, 0xC1u, 0x39u, 0x92u, + 0x33u, 0x5Fu, 0x3Bu, 0xF6u, 0xD2u, 0xB9u, 0x68u, 0x8Fu, + /* 0x662A9F2DBA063986DE1D90C2B6BE215DBBEA2CFE95510BFDF23CBF79501FFF82 [BE] */ + 0x82u, 0xFFu, 0x1Fu, 0x50u, 0x79u, 0xBFu, 0x3Cu, 0xF2u, + 0xFDu, 0x0Bu, 0x51u, 0x95u, 0xFEu, 0x2Cu, 0xEAu, 0xBBu, + 0x5Du, 0x21u, 0xBEu, 0xB6u, 0xC2u, 0x90u, 0x1Du, 0xDEu, + 0x86u, 0x39u, 0x06u, 0xBAu, 0x2Du, 0x9Fu, 0x2Au, 0x66u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp256k1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp256k1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP256K1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP256K1_P, + .common.pFullModulusN = (uint8_t *) &SECP256K1_N, + .common.pR2P = (uint8_t *) &SECP256K1_R2P, + .common.pR2N = (uint8_t *) &SECP256K1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP256K1_A, + .common.pCurveParam2 = (uint8_t *) &SECP256K1_B, + .common.pGx = (uint8_t *) &SECP256K1_GX, + .common.pGy = (uint8_t *) &SECP256K1_GY, + .common.pPrecPoints = (uint8_t *) &SECP256K1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + + +/**********************************************************/ +/* secp384r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP384R1_P[MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* pDash 0x100000001 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + + /* p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF [BE] */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP384R1_N[MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* nDash 0x6ed46089e88fdc45 [BE] */ + 0x45u, 0xDCu, 0x8Fu, 0xE8u, 0x89u, 0x60u, 0xD4u, 0x6Eu, + + /* n = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973 [BE] */ + 0x73u, 0x29u, 0xC5u, 0xCCu, 0x6Au, 0x19u, 0xECu, 0xECu, 0x7Au, 0xA7u, 0xB0u, 0x48u, 0xB2u, 0x0Du, 0x1Au, 0x58u, + 0xDFu, 0x2Du, 0x37u, 0xF4u, 0x81u, 0x4Du, 0x63u, 0xC7u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP384R1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* A = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC [BE] */ + 0xFCu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t SECP384R1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* B = 0xB3312FA7E23EE7E4988E056BE3F82D19181D9C6EFE8141120314088F5013875AC656398D8A2ED19D2A85C8EDD3EC2AEF [BE] */ + 0xEFu, 0x2Au, 0xECu, 0xD3u, 0xEDu, 0xC8u, 0x85u, 0x2Au, 0x9Du, 0xD1u, 0x2Eu, 0x8Au, 0x8Du, 0x39u, 0x56u, 0xC6u, + 0x5Au, 0x87u, 0x13u, 0x50u, 0x8Fu, 0x08u, 0x14u, 0x03u, 0x12u, 0x41u, 0x81u, 0xFEu, 0x6Eu, 0x9Cu, 0x1Du, 0x18u, + 0x19u, 0x2Du, 0xF8u, 0xE3u, 0x6Bu, 0x05u, 0x8Eu, 0x98u, 0xE4u, 0xE7u, 0x3Eu, 0xE2u, 0xA7u, 0x2Fu, 0x31u, 0xB3u +}; + +static const uint8_t SECP384R1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* PointGX = 0xAA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7 [BE] */ + 0xB7u, 0x0Au, 0x76u, 0x72u, 0x38u, 0x5Eu, 0x54u, 0x3Au, 0x6Cu, 0x29u, 0x55u, 0xBFu, 0x5Du, 0xF2u, 0x02u, 0x55u, + 0x38u, 0x2Au, 0x54u, 0x82u, 0xE0u, 0x41u, 0xF7u, 0x59u, 0x98u, 0x9Bu, 0xA7u, 0x8Bu, 0x62u, 0x3Bu, 0x1Du, 0x6Eu, + 0x74u, 0xADu, 0x20u, 0xF3u, 0x1Eu, 0xC7u, 0xB1u, 0x8Eu, 0x37u, 0x05u, 0x8Bu, 0xBEu, 0x22u, 0xCAu, 0x87u, 0xAAu +}; + +static const uint8_t SECP384R1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* PointGY = 0x3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F [BE] */ + 0x5Fu, 0x0Eu, 0xEAu, 0x90u, 0x7Cu, 0x1Du, 0x43u, 0x7Au, 0x9Du, 0x81u, 0x7Eu, 0x1Du, 0xCEu, 0xB1u, 0x60u, 0x0Au, + 0xC0u, 0xB8u, 0xF0u, 0xB5u, 0x13u, 0x31u, 0xDAu, 0xE9u, 0x7Cu, 0x14u, 0x9Au, 0x28u, 0xBDu, 0x1Du, 0xF4u, 0xF8u, + 0x29u, 0xDCu, 0x92u, 0x92u, 0xBFu, 0x98u, 0x9Eu, 0x5Du, 0x6Fu, 0x2Cu, 0x26u, 0x96u, 0x4Au, 0xDEu, 0x17u, 0x36u +}; + +static const uint8_t SECP384R1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* R2P = 0x10000000200000000fffffffe000000000000000200000000fffffffe00000001 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t SECP384R1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* R2N = 0xc84ee012b39bf213fb05b7a28266895d40d49174aab1cc5bc3e483afcb82947ff3d81e5df1aa4192d319b2419b409a9 [BE] */ + 0xA9u, 0x09u, 0xB4u, 0x19u, 0x24u, 0x9Bu, 0x31u, 0x2Du, 0x19u, 0xA4u, 0x1Au, 0xDFu, 0xE5u, 0x81u, 0x3Du, 0xFFu, + 0x47u, 0x29u, 0xB8u, 0xFCu, 0x3Au, 0x48u, 0x3Eu, 0xBCu, 0xC5u, 0x1Cu, 0xABu, 0x4Au, 0x17u, 0x49u, 0x0Du, 0xD4u, + 0x95u, 0x68u, 0x26u, 0x28u, 0x7Au, 0x5Bu, 0xB0u, 0x3Fu, 0x21u, 0xBFu, 0x39u, 0x2Bu, 0x01u, 0xEEu, 0x84u, 0x0C +}; + +static const uint8_t SECP384R1_PRECG[MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + /* 0xC19E0B4C800119C440F7F9E706421279B42A31AF8A3E297DDB2987894D10DDEABA065458A4F52D78A628B09AAA03BD53 [BE] */ + 0x53u, 0xBDu, 0x03u, 0xAAu, 0x9Au, 0xB0u, 0x28u, 0xA6u, 0x78u, 0x2Du, 0xF5u, 0xA4u, 0x58u, 0x54u, 0x06u, 0xBAu, + 0xEAu, 0xDDu, 0x10u, 0x4Du, 0x89u, 0x87u, 0x29u, 0xDBu, 0x7Du, 0x29u, 0x3Eu, 0x8Au, 0xAFu, 0x31u, 0x2Au, 0xB4u, + 0x79u, 0x12u, 0x42u, 0x06u, 0xE7u, 0xF9u, 0xF7u, 0x40u, 0xC4u, 0x19u, 0x01u, 0x80u, 0x4Cu, 0x0Bu, 0x9Eu, 0xC1u, + + /* 0x16F3FDBF0356B301E5A0191D1F5B77F6577A30EAE3567AF9C1C7CAD135F6EBF2AF68AA6DE639D858822D0FC5E6C88C41 [BE] */ + 0x41u, 0x8Cu, 0xC8u, 0xE6u, 0xC5u, 0x0Fu, 0x2Du, 0x82u, 0x58u, 0xD8u, 0x39u, 0xE6u, 0x6Du, 0xAAu, 0x68u, 0xAFu, + 0xF2u, 0xEBu, 0xF6u, 0x35u, 0xD1u, 0xCAu, 0xC7u, 0xC1u, 0xF9u, 0x7Au, 0x56u, 0xE3u, 0xEAu, 0x30u, 0x7Au, 0x57u, + 0xF6u, 0x77u, 0x5Bu, 0x1Fu, 0x1Du, 0x19u, 0xA0u, 0xE5u, 0x01u, 0xB3u, 0x56u, 0x03u, 0xBFu, 0xFDu, 0xF3u, 0x16u, + +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp384r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp384r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP384R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP384R1_P, + .common.pFullModulusN = (uint8_t *) &SECP384R1_N, + .common.pR2P = (uint8_t *) &SECP384R1_R2P, + .common.pR2N = (uint8_t *) &SECP384R1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP384R1_A, + .common.pCurveParam2 = (uint8_t *) &SECP384R1_B, + .common.pGx = (uint8_t *) &SECP384R1_GX, + .common.pGy = (uint8_t *) &SECP384R1_GY, + .common.pPrecPoints = (uint8_t *) &SECP384R1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* secp521r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t SECP521R1_P[MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* pDash 0x1 [BE] */ + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + + /* p = 0x01FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF [BE] */ + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0x01u +}; + +static const uint8_t SECP521R1_N[MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* nDash 0x1d2f5ccd79a995c7 [BE] */ + 0xC7u, 0x95u, 0xA9u, 0x79u, 0xCDu, 0x5Cu, 0x2Fu, 0x1Du, + + /* n = 0x01FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409 [BE] */ + 0x09u, 0x64u, 0x38u, 0x91u, 0x1Eu, 0xB7u, 0x6Fu, 0xBBu, + 0xAEu, 0x47u, 0x9Cu, 0x89u, 0xB8u, 0xC9u, 0xB5u, 0x3Bu, + 0xD0u, 0xA5u, 0x09u, 0xF7u, 0x48u, 0x01u, 0xCCu, 0x7Fu, + 0x6Bu, 0x96u, 0x2Fu, 0xBFu, 0x83u, 0x87u, 0x86u, 0x51u, + 0xFAu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0x01u +}; + +static const uint8_t SECP521R1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* A = 0x01FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC [BE] */ + 0xFCu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0x01u +}; + +static const uint8_t SECP521R1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* B = 0x0051953EB9618E1C9A1F929A21A0B68540EEA2DA725B99B315F3B8B489918EF109E156193951EC7E937B1652C0BD3BB1BF073573DF883D2C34F1EF451FD46B503F00 [BE] */ + 0x00u, 0x3Fu, 0x50u, 0x6Bu, 0xD4u, 0x1Fu, 0x45u, 0xEFu, + 0xF1u, 0x34u, 0x2Cu, 0x3Du, 0x88u, 0xDFu, 0x73u, 0x35u, + 0x07u, 0xBFu, 0xB1u, 0x3Bu, 0xBDu, 0xC0u, 0x52u, 0x16u, + 0x7Bu, 0x93u, 0x7Eu, 0xECu, 0x51u, 0x39u, 0x19u, 0x56u, + 0xE1u, 0x09u, 0xF1u, 0x8Eu, 0x91u, 0x89u, 0xB4u, 0xB8u, + 0xF3u, 0x15u, 0xB3u, 0x99u, 0x5Bu, 0x72u, 0xDAu, 0xA2u, + 0xEEu, 0x40u, 0x85u, 0xB6u, 0xA0u, 0x21u, 0x9Au, 0x92u, + 0x1Fu, 0x9Au, 0x1Cu, 0x8Eu, 0x61u, 0xB9u, 0x3Eu, 0x95u, + 0x51u, 0x00u +}; + +static const uint8_t SECP521R1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* PointGX = 0x00C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66 [BE] */ + 0x66u, 0xBDu, 0xE5u, 0xC2u, 0x31u, 0x7Eu, 0x7Eu, 0xF9u, + 0x9Bu, 0x42u, 0x6Au, 0x85u, 0xC1u, 0xB3u, 0x48u, 0x33u, + 0xDEu, 0xA8u, 0xFFu, 0xA2u, 0x27u, 0xC1u, 0x1Du, 0xFEu, + 0x28u, 0x59u, 0xE7u, 0xEFu, 0x77u, 0x5Eu, 0x4Bu, 0xA1u, + 0xBAu, 0x3Du, 0x4Du, 0x6Bu, 0x60u, 0xAFu, 0x28u, 0xF8u, + 0x21u, 0xB5u, 0x3Fu, 0x05u, 0x39u, 0x81u, 0x64u, 0x9Cu, + 0x42u, 0xB4u, 0x95u, 0x23u, 0x66u, 0xCBu, 0x3Eu, 0x9Eu, + 0xCDu, 0xE9u, 0x04u, 0x04u, 0xB7u, 0x06u, 0x8Eu, 0x85u, + 0xC6u, 0x00u +}; + +static const uint8_t SECP521R1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* PointGY = 0x011839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650 [BE] */ + 0x50u, 0x66u, 0xD1u, 0x9Fu, 0x76u, 0x94u, 0xBEu, 0x88u, + 0x40u, 0xC2u, 0x72u, 0xA2u, 0x86u, 0x70u, 0x3Cu, 0x35u, + 0x61u, 0x07u, 0xADu, 0x3Fu, 0x01u, 0xB9u, 0x50u, 0xC5u, + 0x40u, 0x26u, 0xF4u, 0x5Eu, 0x99u, 0x72u, 0xEEu, 0x97u, + 0x2Cu, 0x66u, 0x3Eu, 0x27u, 0x17u, 0xBDu, 0xAFu, 0x17u, + 0x68u, 0x44u, 0x9Bu, 0x57u, 0x49u, 0x44u, 0xF5u, 0x98u, + 0xD9u, 0x1Bu, 0x7Du, 0x2Cu, 0xB4u, 0x5Fu, 0x8Au, 0x5Cu, + 0x04u, 0xC0u, 0x3Bu, 0x9Au, 0x78u, 0x6Au, 0x29u, 0x39u, + 0x18u, 0x01u +}; + +static const uint8_t SECP521R1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* R2P = 0x4000000000000000000000000000 [BE] */ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u +}; + +static const uint8_t SECP521R1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* R2N = 0x3d2d8e03d1492d0d455bcc6d61a8e567bccff3d142b7756e3edd6e23d82e49c7dbd3721ef557f75e0612a78d38794573fff707badce5547ea3137cd04dcf15dd04 [BE] */ + 0x04u, 0xDDu, 0x15u, 0xCFu, 0x4Du, 0xD0u, 0x7Cu, 0x13u, + 0xA3u, 0x7Eu, 0x54u, 0xE5u, 0xDCu, 0xBAu, 0x07u, 0xF7u, + 0xFFu, 0x73u, 0x45u, 0x79u, 0x38u, 0x8Du, 0xA7u, 0x12u, + 0x06u, 0x5Eu, 0xF7u, 0x57u, 0xF5u, 0x1Eu, 0x72u, 0xD3u, + 0xDBu, 0xC7u, 0x49u, 0x2Eu, 0xD8u, 0x23u, 0x6Eu, 0xDDu, + 0x3Eu, 0x6Eu, 0x75u, 0xB7u, 0x42u, 0xD1u, 0xF3u, 0xCFu, + 0xBCu, 0x67u, 0xE5u, 0xA8u, 0x61u, 0x6Du, 0xCCu, 0x5Bu, + 0x45u, 0x0Du, 0x2Du, 0x49u, 0xD1u, 0x03u, 0x8Eu, 0x2Du, + 0x3Du, 0x00u +}; + +static const uint8_t SECP521R1_PRECG[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + /* 0x008e818d28f381d8b205edff69613b962e0c77d223ef25cc1c99d9a62e4f2572c1617ad0f5e9a86b7104e89700d4da713cb408f3de4465f86ac4ee31e71a286492ad [BE] */ + 0xADu, 0x92u, 0x64u, 0x28u, 0x1Au, 0xE7u, 0x31u, 0xEEu, + 0xC4u, 0x6Au, 0xF8u, 0x65u, 0x44u, 0xDEu, 0xF3u, 0x08u, + 0xB4u, 0x3Cu, 0x71u, 0xDAu, 0xD4u, 0x00u, 0x97u, 0xE8u, + 0x04u, 0x71u, 0x6Bu, 0xA8u, 0xE9u, 0xF5u, 0xD0u, 0x7Au, + 0x61u, 0xC1u, 0x72u, 0x25u, 0x4Fu, 0x2Eu, 0xA6u, 0xD9u, + 0x99u, 0x1Cu, 0xCCu, 0x25u, 0xEFu, 0x23u, 0xD2u, 0x77u, + 0x0Cu, 0x2Eu, 0x96u, 0x3Bu, 0x61u, 0x69u, 0xFFu, 0xEDu, + 0x05u, 0xB2u, 0xD8u, 0x81u, 0xF3u, 0x28u, 0x8Du, 0x81u, + 0x8Eu, 0x00u, + /* 0x013efdbc856e8f68bf44d4e19fc7c326fe48a16f7855c80866237196bf8f72ea0dcb422285dc0370689fbe726f8ce045a4038b640f2b6717760f721231cf8cdf1f60 [BE] */ + 0x60u, 0x1Fu, 0xDFu, 0x8Cu, 0xCFu, 0x31u, 0x12u, 0x72u, + 0x0Fu, 0x76u, 0x17u, 0x67u, 0x2Bu, 0x0Fu, 0x64u, 0x8Bu, + 0x03u, 0xA4u, 0x45u, 0xE0u, 0x8Cu, 0x6Fu, 0x72u, 0xBEu, + 0x9Fu, 0x68u, 0x70u, 0x03u, 0xDCu, 0x85u, 0x22u, 0x42u, + 0xCBu, 0x0Du, 0xEAu, 0x72u, 0x8Fu, 0xBFu, 0x96u, 0x71u, + 0x23u, 0x66u, 0x08u, 0xC8u, 0x55u, 0x78u, 0x6Fu, 0xA1u, + 0x48u, 0xFEu, 0x26u, 0xC3u, 0xC7u, 0x9Fu, 0xE1u, 0xD4u, + 0x44u, 0xBFu, 0x68u, 0x8Fu, 0x6Eu, 0x85u, 0xBCu, 0xFDu, + 0x3Eu, 0x01u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_secp521r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_secp521r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_SECP521R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &SECP521R1_P, + .common.pFullModulusN = (uint8_t *) &SECP521R1_N, + .common.pR2P = (uint8_t *) &SECP521R1_R2P, + .common.pR2N = (uint8_t *) &SECP521R1_R2N, + .common.pCurveParam1 = (uint8_t *) &SECP521R1_A, + .common.pCurveParam2 = (uint8_t *) &SECP521R1_B, + .common.pGx = (uint8_t *) &SECP521R1_GX, + .common.pGy = (uint8_t *) &SECP521R1_GY, + .common.pPrecPoints = (uint8_t *) &SECP521R1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP160r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP160r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* pDash 0x4522ab3adbcb311 [BE] */ + 0x11u, 0xB3u, 0xBCu, 0xADu, 0xB3u, 0x2Au, 0x52u, 0x04u, + + /* p = 0xE95E4A5F737059DC60DFC7AD95B3D8139515620F [BE] */ + 0x0Fu, 0x62u, 0x15u, 0x95u, 0x13u, 0xD8u, 0xB3u, 0x95u, + 0xADu, 0xC7u, 0xDFu, 0x60u, 0xDCu, 0x59u, 0x70u, 0x73u, + 0x5Fu, 0x4Au, 0x5Eu, 0xE9u +}; + +static const uint8_t brainpoolP160r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* nDash 0xe3d0b7e25c7aadc7 [BE] */ + 0xC7u, 0xADu, 0x7Au, 0x5Cu, 0xE2u, 0xB7u, 0xD0u, 0xE3, + + /* n = 0xE95E4A5F737059DC60DF5991D45029409E60FC09 [BE] */ + 0x09u, 0xFCu, 0x60u, 0x9Eu, 0x40u, 0x29u, 0x50u, 0xD4u, + 0x91u, 0x59u, 0xDFu, 0x60u, 0xDCu, 0x59u, 0x70u, 0x73u, + 0x5Fu, 0x4Au, 0x5Eu, 0xE9u +}; + +static const uint8_t brainpoolP160r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* A = 0x340E7BE2A280EB74E2BE61BADA745D97E8F7C300 [BE] */ + 0x00u, 0xC3u, 0xF7u, 0xE8u, 0x97u, 0x5Du, 0x74u, 0xDAu, + 0xBAu, 0x61u, 0xBEu, 0xE2u, 0x74u, 0xEBu, 0x80u, 0xA2u, + 0xE2u, 0x7Bu, 0x0Eu, 0x34u +}; + +static const uint8_t brainpoolP160r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* B = 0x1E589A8595423412134FAA2DBDEC95C8D8675E58 [BE] */ + 0x58u, 0x5Eu, 0x67u, 0xD8u, 0xC8u, 0x95u, 0xECu, 0xBDu, + 0x2Du, 0xAAu, 0x4Fu, 0x13u, 0x12u, 0x34u, 0x42u, 0x95u, + 0x85u, 0x9Au, 0x58u, 0x1Eu +}; + +static const uint8_t brainpoolP160r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* PointGX = 0xBED5AF16EA3F6A4F62938C4631EB5AF7BDBCDBC3 [BE] */ + 0xC3u, 0xDBu, 0xBCu, 0xBDu, 0xF7u, 0x5Au, 0xEBu, 0x31u, + 0x46u, 0x8Cu, 0x93u, 0x62u, 0x4Fu, 0x6Au, 0x3Fu, 0xEAu, + 0x16u, 0xAFu, 0xD5u, 0xBEu +}; + +static const uint8_t brainpoolP160r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* PointGY = 0x1667CB477A1A8EC338F94741669C976316DA6321 [BE] */ + 0x21u, 0x63u, 0xDAu, 0x16u, 0x63, 0x97u, 0x9Cu, 0x66u, + 0x41u, 0x47u, 0xF9u, 0x38u, 0xC3, 0x8Eu, 0x1Au, 0x7Au, + 0x47u, 0xCBu, 0x67u, 0x16u +}; + +static const uint8_t brainpoolP160r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* R2N = 0xcad5a1d8d38e031bf9502858780d638a45a3fdc4 [BE] */ + 0xC4u, 0xFDu, 0xA3u, 0x45u, 0x8Au, 0x63u, 0x0Du, 0x78u, + 0x58u, 0x28u, 0x50u, 0xF9u, 0x1Bu, 0x03u, 0x8Eu, 0xD3u, + 0xD8u, 0xA1u, 0xD5u, 0xCAu +}; + +static const uint8_t brainpoolP160r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* R2P = 0xde9b6b4c5e48b7a01518fd109a27f58da5aeb5a3 [BE] */ + 0xA3u, 0xB5u, 0xAEu, 0xA5u, 0x8Du, 0xF5u, 0x27u, 0x9Au, + 0x10u, 0xFDu, 0x18u, 0x15u, 0xA0u, 0xB7u, 0x48u, 0x5Eu, + 0x4Cu, 0x6Bu, 0x9Bu, 0xDEu +}; + +static const uint8_t brainpoolP160r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + /* 0x8E63BD3939FC8E94BB518725D3B8210CB19BD5A1 [BE] */ + 0xA1u, 0xD5u, 0x9Bu, 0xB1u, 0x0Cu, 0x21u, 0xB8u, 0xD3u, + 0x25u, 0x87u, 0x51u, 0xBBu, 0x94u, 0x8Eu, 0xFCu, 0x39u, + 0x39u, 0xBDu, 0x63u, 0x8Eu, + /* 0x4D1E977B17A683908E138836AF1015A368DE4448 [BE] */ + 0x48u, 0x44u, 0xDEu, 0x68u, 0xA3u, 0x15u, 0x10u, 0xAFu, + 0x36u, 0x88u, 0x13u, 0x8Eu, 0x90u, 0x83u, 0xA6u, 0x17u, + 0x7Bu, 0x97u, 0x1Eu, 0x4Du +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP160r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP160r1_N, + .common.pR2P = (uint8_t *) &brainpoolP160r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP160r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP160r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP160r1_B, + .common.pGx = (uint8_t *) &brainpoolP160r1_GX, + .common.pGy = (uint8_t *) &brainpoolP160r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP160r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP192r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP192r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* pDash 0xe08496db56a2c2d9 [BE] */ + 0xD9u, 0xC2u, 0xA2u, 0x56u, 0xDBu, 0x96u, 0x84u, 0xE0u, + + /* p = 0xC302F41D932A36CDA7A3463093D18DB78FCE476DE1A86297 [BE] */ + 0x97u, 0x62u, 0xA8u, 0xE1u, 0x6Du, 0x47u, 0xCEu, 0x8Fu, + 0xB7u, 0x8Du, 0xD1u, 0x93u, 0x30u, 0x46u, 0xA3u, 0xA7u, + 0xCDu, 0x36u, 0x2Au, 0x93u, 0x1Du, 0xF4u, 0x02u, 0xC3u +}; + +static const uint8_t brainpoolP192r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* nDash 0x6f3cf15f75de1cbf [BE] */ + 0xBFu, 0x1Cu, 0xDEu, 0x75u, 0x5Fu, 0xF1u, 0x3Cu, 0x6Fu, + + /* n = 0xC302F41D932A36CDA7A3462F9E9E916B5BE8F1029AC4ACC1 [BE] */ + 0xC1u, 0xACu, 0xC4u, 0x9Au, 0x02u, 0xF1u, 0xE8u, 0x5Bu, + 0x6Bu, 0x91u, 0x9Eu, 0x9Eu, 0x2Fu, 0x46u, 0xA3u, 0xA7u, + 0xCDu, 0x36u, 0x2Au, 0x93u, 0x1Du, 0xF4u, 0x02u, 0xC3u +}; + +static const uint8_t brainpoolP192r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* A = 0x6A91174076B1E0E19C39C031FE8685C1CAE040E5C69A28EF [BE] */ + 0xEFu, 0x28u, 0x9Au, 0xC6u, 0xE5u, 0x40u, 0xE0u, 0xCAu, + 0xC1u, 0x85u, 0x86u, 0xFEu, 0x31u, 0xC0u, 0x39u, 0x9Cu, + 0xE1u, 0xE0u, 0xB1u, 0x76u, 0x40u, 0x17u, 0x91u, 0x6Au +}; + +static const uint8_t brainpoolP192r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* B = 0x469A28EF7C28CCA3DC721D044F4496BCCA7EF4146FBF25C9 [BE] */ + 0xC9u, 0x25u, 0xBFu, 0x6Fu, 0x14u, 0xF4u, 0x7Eu, 0xCAu, + 0xBCu, 0x96u, 0x44u, 0x4Fu, 0x04u, 0x1Du, 0x72u, 0xDCu, + 0xA3u, 0xCCu, 0x28u, 0x7Cu, 0xEFu, 0x28u, 0x9Au, 0x46u +}; + +static const uint8_t brainpoolP192r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* PointGX = 0xC0A0647EAAB6A48753B033C56CB0F0900A2F5C4853375FD6 [BE] */ + 0xD6u, 0x5Fu, 0x37u, 0x53u, 0x48u, 0x5Cu, 0x2Fu, 0x0Au, + 0x90u, 0xF0u, 0xB0u, 0x6Cu, 0xC5u, 0x33u, 0xB0u, 0x53u, + 0x87u, 0xA4u, 0xB6u, 0xAAu, 0x7Eu, 0x64u, 0xA0u, 0xC0u +}; + +static const uint8_t brainpoolP192r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* PointGY = 0x14B690866ABD5BB88B5F4828C1490002E6773FA2FA299B8F [BE] */ + 0x8Fu, 0x9Bu, 0x29u, 0xFAu, 0xA2u, 0x3Fu, 0x77u, 0xE6u, + 0x02u, 0x00u, 0x49u, 0xC1u, 0x28u, 0x48u, 0x5Fu, 0x8Bu, + 0xB8u, 0x5Bu, 0xBDu, 0x6Au, 0x86u, 0x90u, 0xB6u, 0x14u +}; + +static const uint8_t brainpoolP192r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* R2P = 0xb6225126eed34f1033bf484602c3fe69e2474c6972c7b21a [BE] */ + 0x1Au, 0xB2u, 0xC7u, 0x72u, 0x69u, 0x4Cu, 0x47u, 0xE2u, + 0x69u, 0xFEu, 0xC3u, 0x02u, 0x46u, 0x48u, 0xBFu, 0x33u, + 0x10u, 0x4Fu, 0xD3u, 0xEEu, 0x26u, 0x51u, 0x22u, 0xB6u +}; + +static const uint8_t brainpoolP192r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* R2N = 0x98769b9ce772102bbf4afd5dbf53aff0b4727c80e407e8f8 [BE] */ + 0xF8u, 0xE8u, 0x07u, 0xE4u, 0x80u, 0x7Cu, 0x72u, 0xB4u, + 0xF0u, 0xAFu, 0x53u, 0xBFu, 0x5Du, 0xFDu, 0x4Au, 0xBFu, + 0x2Bu, 0x10u, 0x72u, 0xE7u, 0x9Cu, 0x9Bu, 0x76u, 0x98u +}; + +static const uint8_t brainpoolP192r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + /* 0x773D02971E972E92086B6F1DB5B55527B4006CD56E55384C [BE] */ + 0x4Cu, 0x38u, 0x55u, 0x6Eu, 0xD5u, 0x6Cu, 0x00u, 0xB4u, + 0x27u, 0x55u, 0xB5u, 0xB5u, 0x1Du, 0x6Fu, 0x6Bu, 0x08u, + 0x92u, 0x2Eu, 0x97u, 0x1Eu, 0x97u, 0x02u, 0x3Du, 0x77u, + /* 0x807F615C01CE0488A3D9346E6634C2CE32828E3D3014234C [BE] */ + 0x4Cu, 0x23u, 0x14u, 0x30u, 0x3Du, 0x8Eu, 0x82u, 0x32u, + 0xCEu, 0xC2u, 0x34u, 0x66u, 0x6Eu, 0x34u, 0xD9u, 0xA3u, + 0x88u, 0x04u, 0xCEu, 0x01u, 0x5Cu, 0x61u, 0x7Fu, 0x80u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP192r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP192r1_N, + .common.pR2P = (uint8_t *) &brainpoolP192r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP192r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP192r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP192r1_B, + .common.pGx = (uint8_t *) &brainpoolP192r1_GX, + .common.pGy = (uint8_t *) &brainpoolP192r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP192r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP224r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP224r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* pDash 0xe24d216ae149c101 [BE] */ + 0x01u, 0xC1u, 0x49u, 0xE1u, 0x6Au, 0x21u, 0x4Du, 0xE2u, + + /* p = 0xD7C134AA264366862A18302575D1D787B09F075797DA89F57EC8C0FF [BE] */ + 0xFFu, 0xC0u, 0xC8u, 0x7Eu, 0xF5u, 0x89u, 0xDAu, 0x97u, + 0x57u, 0x07u, 0x9Fu, 0xB0u, 0x87u, 0xD7u, 0xD1u, 0x75u, + 0x25u, 0x30u, 0x18u, 0x2Au, 0x86u, 0x66u, 0x43u, 0x26u, + 0xAAu, 0x34u, 0xC1u, 0xD7u +}; + +static const uint8_t brainpoolP224r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* nDash 0x5fc488776cfb37a1 [BE] */ + 0xA1u, 0x37u, 0xFBu, 0x6Cu, 0x77u, 0x88u, 0xC4u, 0x5Fu, + + /* n = 0xD7C134AA264366862A18302575D0FB98D116BC4B6DDEBCA3A5A7939F [BE] */ + 0x9Fu, 0x93u, 0xA7u, 0xA5u, 0xA3u, 0xBCu, 0xDEu, 0x6Du, + 0x4Bu, 0xBCu, 0x16u, 0xD1u, 0x98u, 0xFBu, 0xD0u, 0x75u, + 0x25u, 0x30u, 0x18u, 0x2Au, 0x86u, 0x66u, 0x43u, 0x26u, + 0xAAu, 0x34u, 0xC1u, 0xD7u +}; + +static const uint8_t brainpoolP224r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* A = 0x68A5E62CA9CE6C1C299803A6C1530B514E182AD8B0042A59CAD29F43 [BE] */ + 0x43u, 0x9Fu, 0xD2u, 0xCAu, 0x59u, 0x2Au, 0x04u, 0xB0u, + 0xD8u, 0x2Au, 0x18u, 0x4Eu, 0x51u, 0x0Bu, 0x53u, 0xC1u, + 0xA6u, 0x03u, 0x98u, 0x29u, 0x1Cu, 0x6Cu, 0xCEu, 0xA9u, + 0x2Cu, 0xE6u, 0xA5u, 0x68u +}; + +static const uint8_t brainpoolP224r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* B = 0x2580F63CCFE44138870713B1A92369E33E2135D266DBB372386C400B [BE] */ + 0x0Bu, 0x40u, 0x6Cu, 0x38u, 0x72u, 0xB3u, 0xDBu, 0x66u, + 0xD2u, 0x35u, 0x21u, 0x3Eu, 0xE3u, 0x69u, 0x23u, 0xA9u, + 0xB1u, 0x13u, 0x07u, 0x87u, 0x38u, 0x41u, 0xE4u, 0xCFu, + 0x3Cu, 0xF6u, 0x80u, 0x25u +}; + +static const uint8_t brainpoolP224r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* PointGX = 0x0D9029AD2C7E5CF4340823B2A87DC68C9E4CE3174C1E6EFDEE12C07D [BE] */ + 0x7Du, 0xC0u, 0x12u, 0xEEu, 0xFDu, 0x6Eu, 0x1Eu, 0x4Cu, + 0x17u, 0xE3u, 0x4Cu, 0x9Eu, 0x8Cu, 0xC6u, 0x7Du, 0xA8u, + 0xB2u, 0x23u, 0x08u, 0x34u, 0xF4u, 0x5Cu, 0x7Eu, 0x2Cu, + 0xADu, 0x29u, 0x90u, 0x0Du +}; + +static const uint8_t brainpoolP224r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* PointGY = 0x58AA56F772C0726F24C6B89E4ECDAC24354B9E99CAA3F6D3761402CD [BE] */ + 0xCDu, 0x02u, 0x14u, 0x76u, 0xD3u, 0xF6u, 0xA3u, 0xCAu, + 0x99u, 0x9Eu, 0x4Bu, 0x35u, 0x24u, 0xACu, 0xCDu, 0x4Eu, + 0x9Eu, 0xB8u, 0xC6u, 0x24u, 0x6Fu,0x72u, 0xC0u, 0x72u, + 0xF7u, 0x56u, 0xAAu, 0x58u +}; + +static const uint8_t brainpoolP224r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* R2P = 0x2b3d40dd7ea5577c77e3d7e476f9ee46f691d1053bfbc9bf6b3d58ff [BE] */ + 0xFFu, 0x58u, 0x3Du, 0x6Bu, 0xBFu, 0xC9u, 0xFBu, 0x3Bu, + 0x05u, 0xD1u, 0x91u, 0xF6u, 0x46u, 0xEEu, 0xF9u, 0x76u, + 0xE4u, 0xD7u, 0xE3u, 0x77u, 0x7Cu, 0x57u, 0xA5u, 0x7Eu, + 0xDDu, 0x40u, 0x3Du, 0x2Bu +}; + +static const uint8_t brainpoolP224r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* R2N = 0x5234fe17b4581327a35371e1f0f40a07bab96b21f3d67605e0d86b49 [BE] */ + 0x49u, 0x6Bu, 0xD8u, 0xE0u, 0x05u, 0x76u, 0xD6u, 0xF3u, + 0x21u, 0x6Bu, 0xB9u, 0xBAu, 0x07u, 0x0Au, 0xF4u, 0xF0u, + 0xE1u, 0x71u, 0x53u, 0xA3u, 0x27u, 0x13u, 0x58u, 0xB4u, + 0x17u, 0xFEu, 0x34u, 0x52u +}; + +static const uint8_t brainpoolP224r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + /* 0xB3CDA5BC0699B4A5D7C84B0EEE591079619F1D35794ADD4818671CAC [BE] */ + 0xACu, 0x1Cu, 0x67u, 0x18u, 0x48u, 0xDDu, 0x4Au, 0x79u, + 0x35u, 0x1Du, 0x9Fu, 0x61u, 0x79u, 0x10u, 0x59u, 0xEEu, + 0x0Eu, 0x4Bu, 0xC8u, 0xD7u, 0xA5u, 0xB4u, 0x99u, 0x06u, + 0xBCu, 0xA5u, 0xCDu, 0xB3u, + /* 0xBC2DC034FEF32E40D6D750A13B07A68C4D88B7676E6080C1BB4A5447 [BE] */ + 0x47u, 0x54u, 0x4Au, 0xBBu, 0xC1u, 0x80u, 0x60u, 0x6Eu, + 0x67u, 0xB7u, 0x88u, 0x4Du, 0x8Cu, 0xA6u, 0x07u, 0x3Bu, + 0xA1u, 0x50u, 0xD7u, 0xD6u, 0x40u, 0x2Eu, 0xF3u, 0xFEu, + 0x34u, 0xC0u, 0x2Du, 0xBCu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP224r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP224r1_N, + .common.pR2P = (uint8_t *) &brainpoolP224r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP224r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP224r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP224r1_B, + .common.pGx = (uint8_t *) &brainpoolP224r1_GX, + .common.pGy = (uint8_t *) &brainpoolP224r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP224r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP256r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP256r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* pDash 0xc6a75590cefd89b9 [BE] */ + 0xB9u, 0x89u, 0xFDu, 0xCEu, 0x90u, 0x55u, 0xA7u, 0xC6u, + + /* p = 0xA9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377 [BE] */ + 0x77u, 0x53u, 0x6Eu, 0x1Fu, 0x1Du, 0x48u, 0x13u, 0x20u, + 0x28u, 0x20u, 0x26u, 0xD5u, 0x23u, 0xF6u, 0x3Bu, 0x6Eu, + 0x72u, 0x8Du, 0x83u, 0x9Du, 0x90u, 0x0Au, 0x66u, 0x3Eu, + 0xBCu, 0xA9u, 0xEEu, 0xA1u, 0xDBu, 0x57u, 0xFBu, 0xA9u +}; + +static const uint8_t brainpoolP256r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* nDash 0xfbffbebdcbb40ee9 [BE] */ + 0xE9u, 0x0Eu, 0xB4u, 0xCBu, 0xBDu, 0xBEu, 0xFFu, 0xFBu, + + /* n = 0xA9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7 [BE] */ + 0xA7u, 0x56u, 0x48u, 0x97u, 0x82u, 0x0Eu, 0x1Eu, 0x90u, + 0xF7u, 0xA6u, 0x61u, 0xB5u, 0xA3u, 0x7Au, 0x39u, 0x8Cu, + 0x71u, 0x8Du, 0x83u, 0x9Du, 0x90u, 0x0Au, 0x66u, 0x3Eu, + 0xBCu, 0xA9u, 0xEEu, 0xA1u, 0xDBu, 0x57u, 0xFBu, 0xA9u +}; + +static const uint8_t brainpoolP256r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* A = 0x7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9 [BE] */ + 0xD9u, 0xB5u, 0x30u, 0xF3u, 0x44u, 0x4Bu, 0x4Au, 0xE9u, + 0x6Cu, 0x5Cu, 0xDCu, 0x26u, 0xC1u, 0x55u, 0x80u, 0xFBu, + 0xE7u, 0xFFu, 0x7Au, 0x41u, 0x30u, 0x75u, 0xF6u, 0xEEu, + 0x57u, 0x30u, 0x2Cu, 0xFCu, 0x75u, 0x09u, 0x5Au, 0x7Du +}; + +static const uint8_t brainpoolP256r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* B = 0x26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6 [BE] */ + 0xB6u, 0x07u, 0x8Cu, 0xFFu, 0x18u, 0xDCu, 0xCCu, 0x6Bu, + 0xCEu, 0xE1u, 0xF7u, 0x5Cu, 0x29u, 0x16u, 0x84u, 0x95u, + 0xBFu, 0x7Cu, 0xD7u, 0xBBu, 0xD9u, 0xB5u, 0x30u, 0xF3u, + 0x44u, 0x4Bu, 0x4Au, 0xE9u, 0x6Cu, 0x5Cu, 0xDCu, 0x26u +}; + +static const uint8_t brainpoolP256r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* PointGX = 0x8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262 [BE] */ + 0x62u, 0x32u, 0xCEu, 0x9Au, 0xBDu, 0x53u, 0x44u, 0x3Au, + 0xC2u, 0x23u, 0xBDu, 0xE3u, 0xE1u, 0x27u, 0xDEu, 0xB9u, + 0xAFu, 0xB7u, 0x81u, 0xFCu, 0x2Fu, 0x48u, 0x4Bu, 0x2Cu, + 0xCBu, 0x57u, 0x7Eu, 0xCBu, 0xB9u, 0xAEu, 0xD2u, 0x8Bu +}; + +static const uint8_t brainpoolP256r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* PointGY = 0x547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997 [BE] */ + 0x97u, 0x69u, 0x04u, 0x2Fu, 0xC7u, 0x54u, 0x1Du, 0x5Cu, + 0x54u, 0x8Eu, 0xEDu, 0x2Du, 0x13u, 0x45u, 0x77u, 0xC2u, + 0xC9u, 0x1Du, 0x61u, 0x14u, 0x1Au, 0x46u, 0xF8u, 0x97u, + 0xFDu, 0xC4u, 0xDAu, 0xC3u, 0x35u, 0xF8u, 0x7Eu, 0x54u +}; + +static const uint8_t brainpoolP256r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* R2P = 0x4717aa21e5957fa8a1ecdacd6b1ac8075cce4c26614d4f4d8cfedf7ba6465b6c [BE] */ + 0x6Cu, 0x5Bu, 0x46u, 0xA6u, 0x7Bu, 0xDFu, 0xFEu, 0x8Cu, + 0x4Du, 0x4Fu, 0x4Du, 0x61u, 0x26u, 0x4Cu, 0xCEu, 0x5Cu, + 0x07u, 0xC8u, 0x1Au, 0x6Bu, 0xCDu, 0xDAu, 0xECu, 0xA1u, + 0xA8u, 0x7Fu, 0x95u, 0xE5u, 0x21u, 0xAAu, 0x17u, 0x47u +}; + +static const uint8_t brainpoolP256r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* R2N = 0xb25f1b9c32367629b7f25e76c815cb0f35d176a1134e4a0e1d8d8de3312fca6 [BE] */ + 0xA6u, 0xFCu, 0x12u, 0x33u, 0xDEu, 0xD8u, 0xD8u, 0xE1u, + 0xA0u, 0xE4u, 0x34u, 0x11u, 0x6Au, 0x17u, 0x5Du, 0xF3u, + 0xB0u, 0x5Cu, 0x81u, 0x6Cu, 0xE7u, 0x25u, 0x7Fu, 0x9Bu, + 0x62u, 0x67u, 0x23u, 0xC3u, 0xB9u, 0xF1u, 0x25u, 0x0Bu +}; + +static const uint8_t brainpoolP256r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + /* 0x4A14C0303B856C94B44385117F87ED9D1200CA9B11006590EB6B651CF58472C9 [BE] */ + 0xC9u, 0x72u, 0x84u, 0xF5u, 0x1Cu, 0x65u, 0x6Bu, 0xEBu, + 0x90u, 0x65u, 0x00u, 0x11u, 0x9Bu, 0xCAu, 0x00u, 0x12u, + 0x9Du, 0xEDu, 0x87u, 0x7Fu, 0x11u, 0x85u, 0x43u, 0xB4u, + 0x94u, 0x6Cu, 0x85u, 0x3Bu, 0x30u, 0xC0u, 0x14u, 0x4Au, + /* 0x7B81E470DAE2D5EFE63873498B47CC5ED544A068CD732117529C5CD628F852D1 [BE] */ + 0xD1u, 0x52u, 0xF8u, 0x28u, 0xD6u, 0x5Cu, 0x9Cu, 0x52u, + 0x17u, 0x21u, 0x73u, 0xCDu, 0x68u, 0xA0u, 0x44u, 0xD5u, + 0x5Eu, 0xCCu, 0x47u, 0x8Bu, 0x49u, 0x73u, 0x38u, 0xE6u, + 0xEFu, 0xD5u, 0xE2u, 0xDAu, 0x70u, 0xE4u, 0x81u, 0x7Bu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP256r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP256r1_N, + .common.pR2P = (uint8_t *) &brainpoolP256r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP256r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP256r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP256r1_B, + .common.pGx = (uint8_t *) &brainpoolP256r1_GX, + .common.pGy = (uint8_t *) &brainpoolP256r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP256r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP320r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP320r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* pDash 0x3d1e9ba22a8a9e69 [BE] */ + 0x69u, 0x9Eu, 0x8Au, 0x2Au, 0xA2u, 0x9Bu, 0x1Eu, 0x3D, + + /* p = 0xD35E472036BC4FB7E13C785ED201E065F98FCFA6F6F40DEF4F92B9EC7893EC28FCD412B1F1B32E27 [BE] */ + 0x27u, 0x2Eu, 0xB3u, 0xF1u, 0xB1u, 0x12u, 0xD4u, 0xFCu, + 0x28u, 0xECu, 0x93u, 0x78u, 0xECu, 0xB9u, 0x92u, 0x4Fu, + 0xEFu, 0x0Du, 0xF4u, 0xF6u, 0xA6u, 0xCFu, 0x8Fu, 0xF9u, + 0x65u, 0xE0u, 0x01u, 0xD2u, 0x5Eu, 0x78u, 0x3Cu, 0xE1u, + 0xB7u, 0x4Fu, 0xBCu, 0x36u, 0x20u, 0x47u, 0x5Eu, 0xD3u +}; + +static const uint8_t brainpoolP320r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* nDash 0x6d42e535fc62420f [BE] */ + 0x0Fu, 0x42u, 0x62u, 0xFCu, 0x35u, 0xE5u, 0x42u, 0x6D, + + /* n = 0xD35E472036BC4FB7E13C785ED201E065F98FCFA5B68F12A32D482EC7EE8658E98691555B44C59311 [BE] */ + 0x11u, 0x93u, 0xC5u, 0x44u, 0x5Bu, 0x55u, 0x91u, 0x86u, + 0xE9u, 0x58u, 0x86u, 0xEEu, 0xC7u, 0x2Eu, 0x48u, 0x2Du, + 0xA3u, 0x12u, 0x8Fu, 0xB6u, 0xA5u, 0xCFu, 0x8Fu, 0xF9u, + 0x65u, 0xE0u, 0x01u, 0xD2u, 0x5Eu, 0x78u, 0x3Cu, 0xE1u, + 0xB7u, 0x4Fu, 0xBCu, 0x36u, 0x20u, 0x47u, 0x5Eu, 0xD3u +}; + +static const uint8_t brainpoolP320r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* A = 0x3EE30B568FBAB0F883CCEBD46D3F3BB8A2A73513F5EB79DA66190EB085FFA9F492F375A97D860EB4 [BE] */ + 0xB4u, 0x0Eu, 0x86u, 0x7Du, 0xA9u, 0x75u, 0xF3u, 0x92u, + 0xF4u, 0xA9u, 0xFFu, 0x85u, 0xB0u, 0x0Eu, 0x19u, 0x66u, + 0xDAu, 0x79u, 0xEBu, 0xF5u, 0x13u, 0x35u, 0xA7u, 0xA2u, + 0xB8u, 0x3Bu, 0x3Fu, 0x6Du, 0xD4u, 0xEBu, 0xCCu, 0x83u, + 0xF8u, 0xB0u, 0xBAu, 0x8Fu, 0x56u, 0x0Bu, 0xE3u, 0x3Eu +}; + +static const uint8_t brainpoolP320r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* B = 0x520883949DFDBC42D3AD198640688A6FE13F41349554B49ACC31DCCD884539816F5EB4AC8FB1F1A6 [BE] */ + 0xA6u, 0xF1u, 0xB1u, 0x8Fu, 0xACu, 0xB4u, 0x5Eu, 0x6Fu, + 0x81u, 0x39u, 0x45u, 0x88u, 0xCDu, 0xDCu, 0x31u, 0xCCu, + 0x9Au, 0xB4u, 0x54u, 0x95u, 0x34u, 0x41u, 0x3Fu, 0xE1u, + 0x6Fu, 0x8Au, 0x68u, 0x40u, 0x86u, 0x19u, 0xADu, 0xD3u, + 0x42u, 0xBCu, 0xFDu, 0x9Du, 0x94u, 0x83u, 0x08u, 0x52u +}; + +static const uint8_t brainpoolP320r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* PointGX = 0x43BD7E9AFB53D8B85289BCC48EE5BFE6F20137D10A087EB6E7871E2A10A599C710AF8D0D39E20611 [BE] */ + 0x11u, 0x06u, 0xE2u, 0x39u, 0x0Du, 0x8Du, 0xAFu, 0x10u, + 0xC7u, 0x99u, 0xA5u, 0x10u, 0x2Au, 0x1Eu, 0x87u, 0xE7u, + 0xB6u, 0x7Eu, 0x08u, 0x0Au, 0xD1u, 0x37u, 0x01u, 0xF2u, + 0xE6u, 0xBFu, 0xE5u, 0x8Eu, 0xC4u, 0xBCu, 0x89u, 0x52u, + 0xB8u, 0xD8u, 0x53u, 0xFBu, 0x9Au, 0x7Eu, 0xBDu, 0x43u +}; + +static const uint8_t brainpoolP320r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* PointGY = 0x14FDD05545EC1CC8AB4093247F77275E0743FFED117182EAA9C77877AAAC6AC7D35245D1692E8EE1 [BE] */ + 0xE1u, 0x8Eu, 0x2Eu, 0x69u, 0xD1u, 0x45u, 0x52u, 0xD3u, + 0xC7u, 0x6Au, 0xACu, 0xAAu, 0x77u, 0x78u, 0xC7u, 0xA9u, + 0xEAu, 0x82u, 0x71u, 0x11u, 0xEDu, 0xFFu, 0x43u, 0x07u, + 0x5Eu, 0x27u, 0x77u, 0x7Fu, 0x24u, 0x93u, 0x40u, 0xABu, + 0xC8u, 0x1Cu, 0xECu, 0x45u, 0x55u, 0xD0u, 0xFDu, 0x14u +}; + +static const uint8_t brainpoolP320r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* R2P = 0xa259ba4a6c2d92525455a964e614d6d21f4c881f30c5b676c2478a8d906978ef994ee88a743b52f9 [BE] */ + 0xF9u, 0x52u, 0x3Bu, 0x74u, 0x8Au, 0xE8u, 0x4Eu, 0x99u, + 0xEFu, 0x78u, 0x69u, 0x90u, 0x8Du, 0x8Au, 0x47u, 0xC2u, + 0x76u, 0xB6u, 0xC5u, 0x30u, 0x1Fu, 0x88u, 0x4Cu, 0x1Fu, + 0xD2u, 0xD6u, 0x14u, 0xE6u, 0x64u, 0xA9u, 0x55u, 0x54u, + 0x52u, 0x92u, 0x2Du, 0x6Cu, 0x4Au, 0xBAu, 0x59u, 0xA2u +}; + +static const uint8_t brainpoolP320r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* R2N = 0x31ec87c73200b14fe30d35244e6390fe86b330bcaf86c40991c3001be0e16805679d29df2513e4cd [BE] */ + 0xCDu, 0xE4u, 0x13u, 0x25u, 0xDFu, 0x29u, 0x9Du, 0x67u, + 0x05u, 0x68u, 0xE1u, 0xE0u, 0x1Bu, 0x00u, 0xC3u, 0x91u, + 0x09u, 0xC4u, 0x86u, 0xAFu, 0xBCu, 0x30u, 0xB3u, 0x86u, + 0xFEu, 0x90u, 0x63u, 0x4Eu, 0x24u, 0x35u, 0x0Du, 0xE3u, + 0x4Fu, 0xB1u, 0x00u, 0x32u, 0xC7u, 0x87u, 0xECu, 0x31u +}; + +static const uint8_t brainpoolP320r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + /* 0x3BC19CAE675062D337C47C97D324B0FF41C14B62B7ED9FD820619B2A13C4A1FA7723D2D17C841CBC [BE] */ + 0xBCu, 0x1Cu, 0x84u, 0x7Cu, 0xD1u, 0xD2u, 0x23u, 0x77u, + 0xFAu, 0xA1u, 0xC4u, 0x13u, 0x2Au, 0x9Bu, 0x61u, 0x20u, + 0xD8u, 0x9Fu, 0xEDu, 0xB7u, 0x62u, 0x4Bu, 0xC1u, 0x41u, + 0xFFu, 0xB0u, 0x24u, 0xD3u, 0x97u, 0x7Cu, 0xC4u, 0x37u, + 0xD3u, 0x62u, 0x50u, 0x67u, 0xAEu, 0x9Cu, 0xC1u, 0x3Bu, + /* 0x8C1DE9E0E7B2DC94704D6FB76B9BA3E5A45BC5182422C60968A3020A4F8EA777EB2238EE45BEE1AA [BE] */ + 0xAAu, 0xE1u, 0xBEu, 0x45u, 0xEEu, 0x38u, 0x22u, 0xEBu, + 0x77u, 0xA7u, 0x8Eu, 0x4Fu, 0x0Au, 0x02u, 0xA3u, 0x68u, + 0x09u, 0xC6u, 0x22u, 0x24u, 0x18u, 0xC5u, 0x5Bu, 0xA4u, + 0xE5u, 0xA3u, 0x9Bu, 0x6Bu, 0xB7u, 0x6Fu, 0x4Du, 0x70u, + 0x94u, 0xDCu, 0xB2u, 0xE7u, 0xE0u, 0xE9u, 0x1Du, 0x8Cu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP320r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP320r1_N, + .common.pR2P = (uint8_t *) &brainpoolP320r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP320r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP320r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP320r1_B, + .common.pGx = (uint8_t *) &brainpoolP320r1_GX, + .common.pGy = (uint8_t *) &brainpoolP320r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP320r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP384r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP384r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* pDash 0x9a6ea96cea9ec825 [BE] */ + 0x25u, 0xC8u, 0x9Eu, 0xEAu, 0x6Cu, 0xA9u, 0x6Eu, 0x9Au, + + /* p = 0x8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53 [BE] */ + 0x53u, 0xECu, 0x07u, 0x31u, 0x13u, 0x00u, 0x47u, 0x87u, + 0x71u, 0x1Au, 0x1Du, 0x90u, 0x29u, 0xA7u, 0xD3u, 0xACu, + 0x23u, 0x11u, 0xB7u, 0x7Fu, 0x19u, 0xDAu, 0xB1u, 0x12u, + 0xB4u, 0x56u, 0x54u, 0xEDu, 0x09u, 0x71u, 0x2Fu, 0x15u, + 0xDFu, 0x41u, 0xE6u, 0x50u, 0x7Eu, 0x6Fu, 0x5Du, 0x0Fu, + 0x28u, 0x6Du, 0x38u, 0xA3u, 0x82u, 0x1Eu, 0xB9u, 0x8Cu +}; + +static const uint8_t brainpoolP384r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* nDash 0x5cfedd2a5cb5bb93 [BE] */ + 0x93u, 0xBBu, 0xB5u, 0x5Cu, 0x2Au, 0xDDu, 0xFEu, 0x5Cu, + + /* n = 0x8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565 [BE] */ + 0x65u, 0x65u, 0x04u, 0xE9u, 0x02u, 0x32u, 0x88u, 0x3Bu, + 0x10u, 0xC3u, 0x7Fu, 0x6Bu, 0xAFu, 0xB6u, 0x3Au, 0xCFu, + 0xA7u, 0x25u, 0x04u, 0xACu, 0x6Cu, 0x6Eu, 0x16u, 0x1Fu, + 0xB3u, 0x56u, 0x54u, 0xEDu, 0x09u, 0x71u, 0x2Fu, 0x15u, + 0xDFu, 0x41u, 0xE6u, 0x50u, 0x7Eu, 0x6Fu, 0x5Du, 0x0Fu, + 0x28u, 0x6Du, 0x38u, 0xA3u, 0x82u, 0x1Eu, 0xB9u, 0x8Cu +}; + +static const uint8_t brainpoolP384r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* A = 0x7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826 [BE] */ + 0x26u, 0x28u, 0xCEu, 0x22u, 0xDDu, 0xC7u, 0xA8u, 0x04u, + 0xEBu, 0xD4u, 0x3Au, 0x50u, 0x4Au, 0x81u, 0xA5u, 0x8Au, + 0x0Fu, 0xF9u, 0x91u, 0xBAu, 0xEFu, 0x65u, 0x91u, 0x13u, + 0x87u, 0x27u, 0xB2u, 0x4Fu, 0x8Eu, 0xA2u, 0xBEu, 0xC2u, + 0xA0u, 0xAFu, 0x05u, 0xCEu, 0x0Au, 0x08u, 0x72u, 0x3Cu, + 0x0Cu, 0x15u, 0x8Cu, 0x3Du, 0xC6u, 0x82u, 0xC3u, 0x7Bu +}; + +static const uint8_t brainpoolP384r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* B = 0x04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11 [BE] */ + 0x11u, 0x4Cu, 0x50u, 0xFAu, 0x96u, 0x86u, 0xB7u, 0x3Au, + 0x94u, 0xC9u, 0xDBu, 0x95u, 0x02u, 0x39u, 0xB4u, 0x7Cu, + 0xD5u, 0x62u, 0xEBu, 0x3Eu, 0xA5u, 0x0Eu, 0x88u, 0x2Eu, + 0xA6u, 0xD2u, 0xDCu, 0x07u, 0xE1u, 0x7Du, 0xB7u, 0x2Fu, + 0x7Cu, 0x44u, 0xF0u, 0x16u, 0x54u, 0xB5u, 0x39u, 0x8Bu, + 0x26u, 0x28u, 0xCEu, 0x22u, 0xDDu, 0xC7u, 0xA8u, 0x04u +}; + +static const uint8_t brainpoolP384r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* PointGX = 0x1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E [BE] */ + 0x1Eu, 0xAFu, 0xD4u, 0x47u, 0xE2u, 0xB2u, 0x87u, 0xEFu, + 0xAAu, 0x46u, 0xD6u, 0x36u, 0x34u, 0xE0u, 0x26u, 0xE8u, + 0xE8u, 0x10u, 0xBDu, 0x0Cu, 0xFEu, 0xCAu, 0x7Fu, 0xDBu, + 0xE3u, 0x4Fu, 0xF1u, 0x7Eu, 0xE7u, 0xA3u, 0x47u, 0x88u, + 0x6Bu, 0x3Fu, 0xC1u, 0xB7u, 0x81u, 0x3Au, 0xA6u, 0xA2u, + 0xFFu, 0x45u, 0xCFu, 0x68u, 0xF0u, 0x64u, 0x1Cu, 0x1Du +}; + +static const uint8_t brainpoolP384r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* PointGY = 0x8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315 [BE] */ + 0x15u, 0x53u, 0x3Cu, 0x26u, 0x41u, 0x03u, 0x82u, 0x42u, + 0x11u, 0x81u, 0x91u, 0x77u, 0x21u, 0x46u, 0x46u, 0x0Eu, + 0x28u, 0x29u, 0x91u, 0xF9u, 0x4Fu, 0x05u, 0x9Cu, 0xE1u, + 0x64u, 0x58u, 0xECu, 0xFEu, 0x29u, 0x0Bu, 0xB7u, 0x62u, + 0x52u, 0xD5u, 0xCFu, 0x95u, 0x8Eu, 0xEBu, 0xB1u, 0x5Cu, + 0xA4u, 0xC2u, 0xF9u, 0x20u, 0x75u, 0x1Du, 0xBEu, 0x8Au +}; + +static const uint8_t brainpoolP384r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* R2P = 0x36bf6883178df842d5c6ef3ba57e052c621401919918d5af8e28f99cc9940899535283343d7fd965087cefff40b64bde [BE] */ + 0xDEu, 0x4Bu, 0xB6u, 0x40u, 0xFFu, 0xEFu, 0x7Cu, 0x08u, + 0x65u, 0xD9u, 0x7Fu, 0x3Du, 0x34u, 0x83u, 0x52u, 0x53u, + 0x99u, 0x08u, 0x94u, 0xC9u, 0x9Cu, 0xF9u, 0x28u, 0x8Eu, + 0xAFu, 0xD5u, 0x18u, 0x99u, 0x91u, 0x01u, 0x14u, 0x62u, + 0x2Cu, 0x05u, 0x7Eu, 0xA5u, 0x3Bu, 0xEFu, 0xC6u, 0xD5u, + 0x42u, 0xF8u, 0x8Du, 0x17u, 0x83u, 0x68u, 0xBFu, 0x36u +}; + +static const uint8_t brainpoolP384r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* R2N = 0xce8941a614e97c28f886dc965165fdb574a74cb52d748ff2a927e3b9802688a37264e202f2b6b6eac4ed3a2de771c8e [BE] */ + 0x8Eu, 0x1Cu, 0x77u, 0xDEu, 0xA2u, 0xD3u, 0x4Eu, 0xACu, + 0x6Eu, 0x6Bu, 0x2Bu, 0x2Fu, 0x20u, 0x4Eu, 0x26u, 0x37u, + 0x8Au, 0x68u, 0x02u, 0x98u, 0x3Bu, 0x7Eu, 0x92u, 0x2Au, + 0xFFu, 0x48u, 0xD7u, 0x52u, 0xCBu, 0x74u, 0x4Au, 0x57u, + 0xDBu, 0x5Fu, 0x16u, 0x65u, 0xC9u, 0x6Du, 0x88u, 0x8Fu, + 0xC2u, 0x97u, 0x4Eu, 0x61u, 0x1Au, 0x94u, 0xE8u, 0x0Cu +}; + +static const uint8_t brainpoolP384r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + /* 0x2369DBB6397C99F18974B5688E81AF98DF4DDACCBB1FDC04E18A5D2D02C7F72702A353BC5345A9466BF550B04D994B04 [BE] */ + 0x04u, 0x4Bu, 0x99u, 0x4Du, 0xB0u, 0x50u, 0xF5u, 0x6Bu, + 0x46u, 0xA9u, 0x45u, 0x53u, 0xBCu, 0x53u, 0xA3u, 0x02u, + 0x27u, 0xF7u, 0xC7u, 0x02u, 0x2Du, 0x5Du, 0x8Au, 0xE1u, + 0x04u, 0xDCu, 0x1Fu, 0xBBu, 0xCCu, 0xDAu, 0x4Du, 0xDFu, + 0x98u, 0xAFu, 0x81u, 0x8Eu, 0x68u, 0xB5u, 0x74u, 0x89u, + 0xF1u, 0x99u, 0x7Cu, 0x39u, 0xB6u, 0xDBu, 0x69u, 0x23u, + /* 0x6F47B11DAA3B124F93B08775925FF0A8127368F10742FA8FCD41CAE93334CE6643F143E6500CB2C10EE188BB14504C85 [BE] */ + 0x85u, 0x4Cu, 0x50u, 0x14u, 0xBBu, 0x88u, 0xE1u, 0x0Eu, + 0xC1u, 0xB2u, 0x0Cu, 0x50u, 0xE6u, 0x43u, 0xF1u, 0x43u, + 0x66u, 0xCEu, 0x34u, 0x33u, 0xE9u, 0xCAu, 0x41u, 0xCDu, + 0x8Fu, 0xFAu, 0x42u, 0x07u, 0xF1u, 0x68u, 0x73u, 0x12u, + 0xA8u, 0xF0u, 0x5Fu, 0x92u, 0x75u, 0x87u, 0xB0u, 0x93u, + 0x4Fu, 0x12u, 0x3Bu, 0xAAu, 0x1Du, 0xB1u, 0x47u, 0x6Fu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP384r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP384r1_N, + .common.pR2P = (uint8_t *) &brainpoolP384r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP384r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP384r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP384r1_B, + .common.pGx = (uint8_t *) &brainpoolP384r1_GX, + .common.pGy = (uint8_t *) &brainpoolP384r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP384r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP512r1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP512r1_P[MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* pDash 0x839b32207d89efc5 [BE] */ + 0xC5u, 0xEFu, 0x89u, 0x7Du, 0x20u, 0x32u, 0x9Bu, 0x83u, + + /* p = 0xAADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3 [BE] */ + 0xF3u, 0x48u, 0x3Au, 0x58u, 0x56u, 0x60u, 0xAAu, 0x28u, + 0x85u, 0xC6u, 0x82u, 0x2Du, 0x2Fu, 0xFFu, 0x81u, 0x28u, + 0xE6u, 0x80u, 0xA3u, 0xE6u, 0x2Au, 0xA1u, 0xCDu, 0xAEu, + 0x42u, 0x68u, 0xC6u, 0x9Bu, 0x00u, 0x9Bu, 0x4Du, 0x7Du, + 0x71u, 0x08u, 0x33u, 0x70u, 0xCAu, 0x9Cu, 0x63u, 0xD6u, + 0x0Eu, 0xD2u, 0xC9u, 0xB3u, 0xB3u, 0x8Du, 0x30u, 0xCBu, + 0x07u, 0xFCu, 0xC9u, 0x33u, 0xAEu, 0xE6u, 0xD4u, 0x3Fu, + 0x8Bu, 0xC4u, 0xE9u, 0xDBu, 0xB8u, 0x9Du, 0xDDu, 0xAAu +}; + +static const uint8_t brainpoolP512r1_N[MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER + MCUXCLPKC_WORDSIZE] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* nDash 0xad49541f0f1b7027 [BE] */ + 0x27u, 0x70u, 0x1Bu, 0x0Fu, 0x1Fu, 0x54u, 0x49u, 0xADu, + + /* n = 0xAADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069 [BE] */ + 0x69u, 0x00u, 0xA9u, 0x9Cu, 0x82u, 0x96u, 0x87u, 0xB5u, + 0xDDu, 0xDAu, 0x5Du, 0x08u, 0x81u, 0xD3u, 0xB1u, 0x1Du, + 0x47u, 0x10u, 0xACu, 0x7Fu, 0x19u, 0x61u, 0x86u, 0x41u, + 0x19u, 0x26u, 0xA9u, 0x4Cu, 0x41u, 0x5Cu, 0x3Eu, 0x55u, + 0x70u, 0x08u, 0x33u, 0x70u, 0xCAu, 0x9Cu, 0x63u, 0xD6u, + 0x0Eu, 0xD2u, 0xC9u, 0xB3u, 0xB3u, 0x8Du, 0x30u, 0xCBu, + 0x07u, 0xFCu, 0xC9u, 0x33u, 0xAEu, 0xE6u, 0xD4u, 0x3Fu, + 0x8Bu, 0xC4u, 0xE9u, 0xDBu, 0xB8u, 0x9Du, 0xDDu, 0xAAu +}; + +static const uint8_t brainpoolP512r1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* A = 0x7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA [BE] */ + 0xCAu, 0x94u, 0xFCu, 0x77u, 0x4Du, 0xACu, 0xC1u, 0xE7u, + 0xB9u, 0xC7u, 0xF2u, 0x2Bu, 0xA7u, 0x17u, 0x11u, 0x7Fu, + 0xB5u, 0xC8u, 0x9Au, 0x8Bu, 0xC9u, 0xF1u, 0x2Eu, 0x0Au, + 0xA1u, 0x3Au, 0x25u, 0xA8u, 0x5Au, 0x5Du, 0xEDu, 0x2Du, + 0xBCu, 0x63u, 0x98u, 0xEAu, 0xCAu, 0x41u, 0x34u, 0xA8u, + 0x10u, 0x16u, 0xF9u, 0x3Du, 0x8Du, 0xDDu, 0xCBu, 0x94u, + 0xC5u, 0x4Cu, 0x23u, 0xACu, 0x45u, 0x71u, 0x32u, 0xE2u, + 0x89u, 0x3Bu, 0x60u, 0x8Bu, 0x31u, 0xA3u, 0x30u, 0x78u +}; + +static const uint8_t brainpoolP512r1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* B = 0x3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723 [BE] */ + 0x23u, 0xF7u, 0x16u, 0x80u, 0x63u, 0xBDu, 0x09u, 0x28u, + 0xDDu, 0xE5u, 0xBAu, 0x5Eu, 0xB7u, 0x50u, 0x40u, 0x98u, + 0x67u, 0x3Eu, 0x08u, 0xDCu, 0xCAu, 0x94u, 0xFCu, 0x77u, + 0x4Du, 0xACu, 0xC1u, 0xE7u, 0xB9u, 0xC7u, 0xF2u, 0x2Bu, + 0xA7u, 0x17u, 0x11u, 0x7Fu, 0xB5u, 0xC8u, 0x9Au, 0x8Bu, + 0xC9u, 0xF1u, 0x2Eu, 0x0Au, 0xA1u, 0x3Au, 0x25u, 0xA8u, + 0x5Au, 0x5Du, 0xEDu, 0x2Du, 0xBCu, 0x63u, 0x98u, 0xEAu, + 0xCAu, 0x41u, 0x34u, 0xA8u, 0x10u, 0x16u, 0xF9u, 0x3Du +}; + +static const uint8_t brainpoolP512r1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* PointGX = 0x81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822 [BE] */ + 0x22u, 0xF8u, 0xB9u, 0xBCu, 0x09u, 0x22u, 0x35u, 0x8Bu, + 0x68u, 0x5Eu, 0x6Au, 0x40u, 0x47u, 0x50u, 0x6Du, 0x7Cu, + 0x5Fu, 0x7Du, 0xB9u, 0x93u, 0x7Bu, 0x68u, 0xD1u, 0x50u, + 0x8Du, 0xD4u, 0xD0u, 0xE2u, 0x78u, 0x1Fu, 0x3Bu, 0xFFu, + 0x8Eu, 0x09u, 0xD0u, 0xF4u, 0xEEu, 0x62u, 0x3Bu, 0xB4u, + 0xC1u, 0x16u, 0xD9u, 0xB5u, 0x70u, 0x9Fu, 0xEDu, 0x85u, + 0x93u, 0x6Au, 0x4Cu, 0x9Cu, 0x2Eu, 0x32u, 0x21u, 0x5Au, + 0x64u, 0xD9u, 0x2Eu, 0xD8u, 0xBDu, 0xE4u, 0xAEu, 0x81u +}; + +static const uint8_t brainpoolP512r1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* PointGY = 0x7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892 [BE] */ + 0x92u, 0x08u, 0xD8u, 0x3Au, 0x0Fu, 0x1Eu, 0xCDu, 0x78u, + 0x06u, 0x54u, 0xF0u, 0xA8u, 0x2Fu, 0x2Bu, 0xCAu, 0xD1u, + 0xAEu, 0x63u, 0x27u, 0x8Au, 0xD8u, 0x4Bu, 0xCAu, 0x5Bu, + 0x5Eu, 0x48u, 0x5Fu, 0x4Au, 0x49u, 0xDEu, 0xDCu, 0xB2u, + 0x11u, 0x81u, 0x1Fu, 0x88u, 0x5Bu, 0xC5u, 0x00u, 0xA0u, + 0x1Au, 0x7Bu, 0xA5u, 0x24u, 0x00u, 0xF7u, 0x09u, 0xF2u, + 0xFDu, 0x22u, 0x78u, 0xCFu, 0xA9u, 0xBFu, 0xEAu, 0xC0u, + 0xECu, 0x32u, 0x63u, 0x56u, 0x5Du, 0x38u, 0xDEu, 0x7Du +}; + +static const uint8_t brainpoolP512r1_R2P[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* R2P = 0x3c4c9d05a9ff6450202e19402056eecca16daa5fd42bff8319486fd8d5898057e0c19a7783514a2553b7f9bc905affd3793fb1302715790549ad144a6158f205 [BE] */ + 0x05u, 0xF2u, 0x58u, 0x61u, 0x4Au, 0x14u, 0xADu, 0x49u, + 0x05u, 0x79u, 0x15u, 0x27u, 0x30u, 0xB1u, 0x3Fu, 0x79u, + 0xD3u, 0xFFu, 0x5Au, 0x90u, 0xBCu, 0xF9u, 0xB7u, 0x53u, + 0x25u, 0x4Au, 0x51u, 0x83u, 0x77u, 0x9Au, 0xC1u, 0xE0u, + 0x57u, 0x80u, 0x89u, 0xD5u, 0xD8u, 0x6Fu, 0x48u, 0x19u, + 0x83u, 0xFFu, 0x2Bu, 0xD4u, 0x5Fu, 0xAAu, 0x6Du, 0xA1u, + 0xCCu, 0xEEu, 0x56u, 0x20u, 0x40u, 0x19u, 0x2Eu, 0x20u, + 0x50u, 0x64u, 0xFFu, 0xA9u, 0x05u, 0x9Du, 0x4Cu, 0x3Cu +}; + +static const uint8_t brainpoolP512r1_R2N[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* R2N = 0xa794586a718407b095df1b4c194b2e56723c37a22f16bbdfd7f9cc263b790de3a6f230c72f0207e83ec64bd033b7627f0886b75895283dddd2a3681ecda81671 [BE] */ + 0x71u, 0x16u, 0xA8u, 0xCDu, 0x1Eu, 0x68u, 0xA3u, 0xD2u, + 0xDDu, 0x3Du, 0x28u, 0x95u, 0x58u, 0xB7u, 0x86u, 0x08u, + 0x7Fu, 0x62u, 0xB7u, 0x33u, 0xD0u, 0x4Bu, 0xC6u, 0x3Eu, + 0xE8u, 0x07u, 0x02u, 0x2Fu, 0xC7u, 0x30u, 0xF2u, 0xA6u, + 0xE3u, 0x0Du, 0x79u, 0x3Bu, 0x26u, 0xCCu, 0xF9u, 0xD7u, + 0xDFu, 0xBBu, 0x16u, 0x2Fu, 0xA2u, 0x37u, 0x3Cu, 0x72u, + 0x56u, 0x2Eu, 0x4Bu, 0x19u, 0x4Cu, 0x1Bu, 0xDFu, 0x95u, + 0xB0u, 0x07u, 0x84u, 0x71u, 0x6Au, 0x58u, 0x94u, 0xA7u +}; + +static const uint8_t brainpoolP512r1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + /* 0x7B5913F766C4ED95D5262CE1B8F1B2AFC056FD658F28487079A83D9B945E84601BAE0F47ACA3B94E97502F33730A37219D189C5408AC7DA5CA448127EF66EFB5 [BE] */ + 0xB5u, 0xEFu, 0x66u, 0xEFu, 0x27u, 0x81u, 0x44u, 0xCAu, + 0xA5u, 0x7Du, 0xACu, 0x08u, 0x54u, 0x9Cu, 0x18u, 0x9Du, + 0x21u, 0x37u, 0x0Au, 0x73u, 0x33u, 0x2Fu, 0x50u, 0x97u, + 0x4Eu, 0xB9u, 0xA3u, 0xACu, 0x47u, 0x0Fu, 0xAEu, 0x1Bu, + 0x60u, 0x84u, 0x5Eu, 0x94u, 0x9Bu, 0x3Du, 0xA8u, 0x79u, + 0x70u, 0x48u, 0x28u, 0x8Fu, 0x65u, 0xFDu, 0x56u, 0xC0u, + 0xAFu, 0xB2u, 0xF1u, 0xB8u, 0xE1u, 0x2Cu, 0x26u, 0xD5u, + 0x95u, 0xEDu, 0xC4u, 0x66u, 0xF7u, 0x13u, 0x59u, 0x7Bu, + /* 0x3B4D8E454FFC593A3727EA1EEA20B708C21FCA9161306AF0E46656A75FC450A8FB4EDB0DBC57887724EC6F844EB496C33E9470F8DA0092C9D610453CC2F45872 [BE] */ + 0x72u, 0x58u, 0xF4u, 0xC2u, 0x3Cu, 0x45u, 0x10u, 0xD6u, + 0xC9u, 0x92u, 0x00u, 0xDAu, 0xF8u, 0x70u, 0x94u, 0x3Eu, + 0xC3u, 0x96u, 0xB4u, 0x4Eu, 0x84u, 0x6Fu, 0xECu, 0x24u, + 0x77u, 0x88u, 0x57u, 0xBCu, 0x0Du, 0xDBu, 0x4Eu, 0xFBu, + 0xA8u, 0x50u, 0xC4u, 0x5Fu, 0xA7u, 0x56u, 0x66u, 0xE4u, + 0xF0u, 0x6Au, 0x30u, 0x61u, 0x91u, 0xCAu, 0x1Fu, 0xC2u, + 0x08u, 0xB7u, 0x20u, 0xEAu, 0x1Eu, 0xEAu, 0x27u, 0x37u, + 0x3Au, 0x59u, 0xFCu, 0x4Fu, 0x45u, 0x8Eu, 0x4Du, 0x3Bu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512r1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512r1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP512r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP512r1_N, + .common.pR2P = (uint8_t *) &brainpoolP512r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP512r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP512r1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP512r1_B, + .common.pGx = (uint8_t *) &brainpoolP512r1_GX, + .common.pGy = (uint8_t *) &brainpoolP512r1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP512r1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP160t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP160t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + /* A = 0xE95E4A5F737059DC60DFC7AD95B3D8139515620C [BE] */ + 0x0Cu, 0x62u, 0x15u, 0x95u, 0x13u, 0xD8u, 0xB3u, 0x95u, + 0xADu, 0xC7u, 0xDFu, 0x60u, 0xDCu, 0x59u, 0x70u, 0x73u, + 0x5Fu, 0x4Au, 0x5Eu, 0xE9u +}; + +static const uint8_t brainpoolP160t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + /* B = 0x7A556B6DAE535B7B51ED2C4D7DAA7A0B5C55F380 [BE] */ + 0x80u, 0xF3u, 0x55u, 0x5Cu, 0x0Bu, 0x7Au, 0xAAu, 0x7Du, + 0x4Du, 0x2Cu, 0xEDu, 0x51u, 0x7Bu, 0x5Bu, 0x53u, 0xAEu, + 0x6Du, 0x6Bu, 0x55u, 0x7Au +}; + +static const uint8_t brainpoolP160t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + /* PointGX = 0xB199B13B9B34EFC1397E64BAEB05ACC265FF2378 [BE] */ + 0x78u, 0x23u, 0xFFu, 0x65u, 0xC2u, 0xACu, 0x05u, 0xEBu, + 0xBAu, 0x64u, 0x7Eu, 0x39u, 0xC1u, 0xEFu, 0x34u, 0x9Bu, + 0x3Bu, 0xB1u, 0x99u, 0xB1u +}; + +static const uint8_t brainpoolP160t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + /* PointGY = 0xADD6718B7C7C1961F0991B842443772152C9E0AD [BE] */ + 0xADu, 0xE0u, 0xC9u, 0x52u, 0x21u, 0x77u, 0x43u, 0x24u, + 0x84u, 0x1Bu, 0x99u, 0xF0u, 0x61u, 0x19u, 0x7Cu, 0x7Cu, + 0x8Bu, 0x71u, 0xD6u, 0xADu +}; + +static const uint8_t brainpoolP160t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + /* Gy = 0x5bc89492ef997c10ab58a622e09c1acb87ab38d8 [BE] */ + 0xD8u, 0x38u, 0xABu, 0x87u, 0xCBu, 0x1Au, 0x9Cu, 0xE0u, + 0x22u, 0xA6u, 0x58u, 0xABu, 0x10u, 0x7Cu, 0x99u, 0xEFu, + 0x92u, 0x94u, 0xC8u, 0x5Bu, + /* Gx = 0x96f1456f8317a6e420b0969e7d905a03f07dfbce [BE] */ + 0xCEu, 0xFBu, 0x7Du, 0xF0u, 0x03u, 0x5Au, 0x90u, 0x7Du, + 0x9Eu, 0x96u, 0xB0u, 0x20u, 0xE4u, 0xA6u, 0x17u, 0x83u, + 0x6Fu, 0x45u, 0xF1u, 0x96u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP160t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP160t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP160r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP160r1_N, + .common.pR2P = (uint8_t *) &brainpoolP160r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP160r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP160t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP160t1_B, + .common.pGx = (uint8_t *) &brainpoolP160t1_GX, + .common.pGy = (uint8_t *) &brainpoolP160t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP160t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP192t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP192t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + /* A = 0xC302F41D932A36CDA7A3463093D18DB78FCE476DE1A86294 [BE] */ + 0x94u, 0x62u, 0xA8u, 0xE1u, 0x6Du, 0x47u, 0xCEu, 0x8Fu, + 0xB7u, 0x8Du, 0xD1u, 0x93u, 0x30u, 0x46u, 0xA3u, 0xA7u, + 0xCDu, 0x36u, 0x2Au, 0x93u, 0x1Du, 0xF4u, 0x02u, 0xC3u +}; + +static const uint8_t brainpoolP192t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + /* B = 0x13D56FFAEC78681E68F9DEB43B35BEC2FB68542E27897B79 [BE] */ + 0x79u, 0x7Bu, 0x89u, 0x27u, 0x2Eu, 0x54u, 0x68u, 0xFBu, + 0xC2u, 0xBEu, 0x35u, 0x3Bu, 0xB4u, 0xDEu, 0xF9u, 0x68u, + 0x1Eu, 0x68u, 0x78u, 0xECu, 0xFAu, 0x6Fu, 0xD5u, 0x13u +}; + +static const uint8_t brainpoolP192t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + /* PointGX = 0x3AE9E58C82F63C30282E1FE7BBF43FA72C446AF6F4618129 [BE] */ + 0x29u, 0x81u, 0x61u, 0xF4u, 0xF6u, 0x6Au, 0x44u, 0x2Cu, + 0xA7u, 0x3Fu, 0xF4u, 0xBBu, 0xE7u, 0x1Fu, 0x2Eu, 0x28u, + 0x30u, 0x3Cu, 0xF6u, 0x82u, 0x8Cu, 0xE5u, 0xE9u, 0x3Au +}; + +static const uint8_t brainpoolP192t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + /* PointGY = 0x097E2C5667C2223A902AB5CA449D0084B7E5B3DE7CCC01C9 [BE] */ + 0xC9u, 0x01u, 0xCCu, 0x7Cu, 0xDEu, 0xB3u, 0xE5u, 0xB7u, + 0x84u, 0x00u, 0x9Du, 0x44u, 0xCAu, 0xB5u, 0x2Au, 0x90u, + 0x3Au, 0x22u, 0xC2u, 0x67u, 0x56u, 0x2Cu, 0x7Eu, 0x09u +}; + +static const uint8_t brainpoolP192t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + /* PPx = 0xafa01a77799b50cff28985e9dcd327f63b32bf88de39650b [BE] */ + 0x0Bu, 0x65u, 0x39u, 0xDEu, 0x88u, 0xBFu, 0x32u, 0x3Bu, + 0xF6u, 0x27u, 0xD3u, 0xDCu, 0xE9u, 0x85u, 0x89u, 0xF2u, + 0xCFu, 0x50u, 0x9Bu, 0x79u, 0x77u, 0x1Au, 0xA0u, 0xAFu, + /* PPy = 0x807F615C01CE0488A3D9346E6634C2CE32828E3D3014234C [BE] */ + 0x0Du, 0xC0u, 0x6Eu, 0xBAu, 0xD2u, 0xD5u, 0x5Bu, 0x80u, + 0x0Du, 0xB5u, 0xF3u, 0x49u, 0x40u, 0x9Du, 0x70u, 0x37u, + 0x84u, 0xD5u, 0x4Eu, 0x67u, 0xB8u, 0x08u, 0x4Du, 0x47u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP192t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP192t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP192r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP192r1_N, + .common.pR2P = (uint8_t *) &brainpoolP192r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP192r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP192t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP192t1_B, + .common.pGx = (uint8_t *) &brainpoolP192t1_GX, + .common.pGy = (uint8_t *) &brainpoolP192t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP192t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP224t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP224t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + /* A = 0xD7C134AA264366862A18302575D1D787B09F075797DA89F57EC8C0FC [BE] */ + 0xFCu, 0xC0u, 0xC8u, 0x7Eu, 0xF5u, 0x89u, 0xDAu, 0x97u, + 0x57u, 0x07u, 0x9Fu, 0xB0u, 0x87u, 0xD7u, 0xD1u, 0x75u, + 0x25u, 0x30u, 0x18u, 0x2Au, 0x86u, 0x66u, 0x43u, 0x26u, + 0xAAu, 0x34u, 0xC1u, 0xD7u +}; + +static const uint8_t brainpoolP224t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + /* B = 0x4B337D934104CD7BEF271BF60CED1ED20DA14C08B3BB64F18A60888D [BE] */ + 0x8Du, 0x88u, 0x60u, 0x8Au, 0xF1u, 0x64u, 0xBBu, 0xB3u, + 0x08u, 0x4Cu, 0xA1u, 0x0Du, 0xD2u, 0x1Eu, 0xEDu, 0x0Cu, + 0xF6u, 0x1Bu, 0x27u, 0xEFu, 0x7Bu, 0xCDu, 0x04u, 0x41u, + 0x93u, 0x7Du, 0x33u, 0x4Bu +}; + +static const uint8_t brainpoolP224t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + /* PointGX = 0x6AB1E344CE25FF3896424E7FFE14762ECB49F8928AC0C76029B4D580 [BE] */ + 0x80u, 0xD5u, 0xB4u, 0x29u, 0x60u, 0xC7u, 0xC0u, 0x8Au, + 0x92u, 0xF8u, 0x49u, 0xCBu, 0x2Eu, 0x76u, 0x14u, 0xFEu, + 0x7Fu, 0x4Eu, 0x42u, 0x96u, 0x38u, 0xFFu, 0x25u, 0xCEu, + 0x44u, 0xE3u, 0xB1u, 0x6Au +}; + +static const uint8_t brainpoolP224t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + /* PointGY = 0x0374E9F5143E568CD23F3F4D7C0D4B1E41C8CC0D1C6ABD5F1A46DB4C [BE] */ + 0x4Cu, 0xDBu, 0x46u, 0x1Au, 0x5Fu, 0xBDu, 0x6Au, 0x1Cu, + 0x0Du, 0xCCu, 0xC8u, 0x41u, 0x1Eu, 0x4Bu, 0x0Du, 0x7Cu, + 0x4Du, 0x3Fu, 0x3Fu, 0xD2u, 0x8Cu, 0x56u, 0x3Eu, 0x14u, + 0xF5u, 0xE9u, 0x74u, 0x03u +}; + +static const uint8_t brainpoolP224t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + /* 0x5d6a2b7060566fe4671e9055947e40131365a60a1f8682cc5be89ce2 [BE] */ + 0xE2u, 0x9Cu, 0xE8u, 0x5Bu, 0xCCu, 0x82u, 0x86u, 0x1Fu, + 0x0Au, 0xA6u, 0x65u, 0x13u, 0x13u, 0x40u, 0x7Eu, 0x94u, + 0x55u, 0x90u, 0x1Eu, 0x67u, 0xE4u, 0x6Fu, 0x56u, 0x60u, + 0x70u, 0x2Bu, 0x6Au, 0x5Du, + /* 0x1bee90f68bf62971f644d741bc3f1fe177a17040c9c9dd34f2cc605b [BE] */ + 0x5Bu, 0x60u, 0xCCu, 0xF2u, 0x34u, 0xDDu, 0xC9u, 0xC9u, + 0x40u, 0x70u, 0xA1u, 0x77u, 0xE1u, 0x1Fu, 0x3Fu, 0xBCu, + 0x41u, 0xD7u, 0x44u, 0xF6u, 0x71u, 0x29u, 0xF6u, 0x8Bu, + 0xF6u, 0x90u, 0xEEu, 0x1Bu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP224t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP224t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP224r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP224r1_N, + .common.pR2P = (uint8_t *) &brainpoolP224r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP224r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP224t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP224t1_B, + .common.pGx = (uint8_t *) &brainpoolP224t1_GX, + .common.pGy = (uint8_t *) &brainpoolP224t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP224t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP256t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP256t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + /* A = 0xA9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5374 [BE] */ + 0x74u, 0x53u, 0x6Eu, 0x1Fu, 0x1Du, 0x48u, 0x13u, 0x20u, + 0x28u, 0x20u, 0x26u, 0xD5u, 0x23u, 0xF6u, 0x3Bu, 0x6Eu, + 0x72u, 0x8Du, 0x83u, 0x9Du, 0x90u, 0x0Au, 0x66u, 0x3Eu, + 0xBCu, 0xA9u, 0xEEu, 0xA1u, 0xDBu, 0x57u, 0xFBu, 0xA9u +}; + +static const uint8_t brainpoolP256t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + /* B = 0x662C61C430D84EA4FE66A7733D0B76B7BF93EBC4AF2F49256AE58101FEE92B04 [BE] */ + 0x04u, 0x2Bu, 0xE9u, 0xFEu, 0x01u, 0x81u, 0xE5u, 0x6Au, + 0x25u, 0x49u, 0x2Fu, 0xAFu, 0xC4u, 0xEBu, 0x93u, 0xBFu, + 0xB7u, 0x76u, 0x0Bu, 0x3Du, 0x73u, 0xA7u, 0x66u, 0xFEu, + 0xA4u, 0x4Eu, 0xD8u, 0x30u, 0xC4u, 0x61u, 0x2Cu, 0x66u +}; + +static const uint8_t brainpoolP256t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + /* PointGX = 0xA3E8EB3CC1CFE7B7732213B23A656149AFA142C47AAFBC2B79A191562E1305F4 [BE] */ + 0xF4u, 0x05u, 0x13u, 0x2Eu, 0x56u, 0x91u, 0xA1u, 0x79u, + 0x2Bu, 0xBCu, 0xAFu, 0x7Au, 0xC4u, 0x42u, 0xA1u, 0xAFu, + 0x49u, 0x61u, 0x65u, 0x3Au, 0xB2u, 0x13u, 0x22u, 0x73u, + 0xB7u, 0xE7u, 0xCFu, 0xC1u, 0x3Cu, 0xEBu, 0xE8u, 0xA3u +}; + +static const uint8_t brainpoolP256t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + /* PointGY = 0x2D996C823439C56D7F7B22E14644417E69BCB6DE39D027001DABE8F35B25C9BE [BE] */ + 0xBEu, 0xC9u, 0x25u, 0x5Bu, 0xF3u, 0xE8u, 0xABu, 0x1Du, + 0x00u, 0x27u, 0xD0u, 0x39u, 0xDEu, 0xB6u, 0xBCu, 0x69u, + 0x7Eu, 0x41u, 0x44u, 0x46u, 0xE1u, 0x22u, 0x7Bu, 0x7Fu, + 0x6Du, 0xC5u, 0x39u, 0x34u, 0x82u, 0x6Cu, 0x99u, 0x2Du +}; + +static const uint8_t brainpoolP256t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + /* 0x8d3285eee42ebe8808c6c385438dedd62c5095657970dfff2f8196ed9b01699d [BE] */ + 0x9Du, 0x69u, 0x01u, 0x9Bu, 0xEDu, 0x96u, 0x81u, 0x2Fu, + 0xFFu, 0xDFu, 0x70u, 0x79u, 0x65u, 0x95u, 0x50u, 0x2Cu, + 0xD6u, 0xEDu, 0x8Du, 0x43u, 0x85u, 0xC3u, 0xC6u, 0x08u, + 0x88u, 0xBEu, 0x2Eu, 0xE4u, 0xEEu, 0x85u, 0x32u, 0x8Du, + /* 0x242e491de7861bd5e555a492ff6fe4ffe4f7dc0a0075e0e50b26ffe522435610 [BE] */ + 0x10u, 0x56u, 0x43u, 0x22u, 0xE5u, 0xFFu, 0x26u, 0x0Bu, + 0xE5u, 0xE0u, 0x75u, 0x00u, 0x0Au, 0xDCu, 0xF7u, 0xE4u, + 0xFFu, 0xE4u, 0x6Fu, 0xFFu, 0x92u, 0xA4u, 0x55u, 0xE5u, + 0xD5u, 0x1Bu, 0x86u, 0xE7u, 0x1Du, 0x49u, 0x2Eu, 0x24u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP256t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP256t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP256r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP256r1_N, + .common.pR2P = (uint8_t *) &brainpoolP256r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP256r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP256t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP256t1_B, + .common.pGx = (uint8_t *) &brainpoolP256t1_GX, + .common.pGy = (uint8_t *) &brainpoolP256t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP256t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP320t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP320t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + /* A = 0xD35E472036BC4FB7E13C785ED201E065F98FCFA6F6F40DEF4F92B9EC7893EC28FCD412B1F1B32E24 [BE] */ + 0x24u, 0x2Eu, 0xB3u, 0xF1u, 0xB1u, 0x12u, 0xD4u, 0xFCu, + 0x28u, 0xECu, 0x93u, 0x78u, 0xECu, 0xB9u, 0x92u, 0x4Fu, + 0xEFu, 0x0Du, 0xF4u, 0xF6u, 0xA6u, 0xCFu, 0x8Fu, 0xF9u, + 0x65u, 0xE0u, 0x01u, 0xD2u, 0x5Eu, 0x78u, 0x3Cu, 0xE1u, + 0xB7u, 0x4Fu, 0xBCu, 0x36u, 0x20u, 0x47u, 0x5Eu, 0xD3u +}; + +static const uint8_t brainpoolP320t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + /* B = 0xA7F561E038EB1ED560B3D147DB782013064C19F27ED27C6780AAF77FB8A547CEB5B4FEF422340353 [BE] */ + 0x53u, 0x03u, 0x34u, 0x22u, 0xF4u, 0xFEu, 0xB4u, 0xB5u, + 0xCEu, 0x47u, 0xA5u, 0xB8u, 0x7Fu, 0xF7u, 0xAAu, 0x80u, + 0x67u, 0x7Cu, 0xD2u, 0x7Eu, 0xF2u, 0x19u, 0x4Cu, 0x06u, + 0x13u, 0x20u, 0x78u, 0xDBu, 0x47u, 0xD1u, 0xB3u, 0x60u, + 0xD5u, 0x1Eu, 0xEBu, 0x38u, 0xE0u, 0x61u, 0xF5u, 0xA7u +}; + +static const uint8_t brainpoolP320t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + /* PointGX = 0x925BE9FB01AFC6FB4D3E7D4990010F813408AB106C4F09CB7EE07868CC136FFF3357F624A21BED52 [BE] */ + 0x52u, 0xEDu, 0x1Bu, 0xA2u, 0x24u, 0xF6u, 0x57u, 0x33u, + 0xFFu, 0x6Fu, 0x13u, 0xCCu, 0x68u, 0x78u, 0xE0u, 0x7Eu, + 0xCBu, 0x09u, 0x4Fu, 0x6Cu, 0x10u, 0xABu, 0x08u, 0x34u, + 0x81u, 0x0Fu, 0x01u, 0x90u, 0x49u, 0x7Du, 0x3Eu, 0x4Du, + 0xFBu, 0xC6u, 0xAFu, 0x01u, 0xFBu, 0xE9u, 0x5Bu, 0x92u +}; + +static const uint8_t brainpoolP320t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + /* PointGY = 0x63BA3A7A27483EBF6671DBEF7ABB30EBEE084E58A0B077AD42A5A0989D1EE71B1B9BC0455FB0D2C3 [BE] */ + 0xC3u, 0xD2u, 0xB0u, 0x5Fu, 0x45u, 0xC0u, 0x9Bu, 0x1Bu, + 0x1Bu, 0xE7u, 0x1Eu, 0x9Du, 0x98u, 0xA0u, 0xA5u, 0x42u, + 0xADu, 0x77u, 0xB0u, 0xA0u, 0x58u, 0x4Eu, 0x08u, 0xEEu, + 0xEBu, 0x30u, 0xBBu, 0x7Au, 0xEFu, 0xDBu, 0x71u, 0x66u, + 0xBFu, 0x3Eu, 0x48u, 0x27u, 0x7Au, 0x3Au, 0xBAu, 0x63u +}; + +static const uint8_t brainpoolP320t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + /* 0x85b929aa2600c461b96b2fcc20698e46840d860868b3b37ca7bb4ecd668739ae61fcff4aa2ff7ed1 [BE] */ + 0xD1u, 0x7Eu, 0xFFu, 0xA2u, 0x4Au, 0xFFu, 0xFCu, 0x61u, + 0xAEu, 0x39u, 0x87u, 0x66u, 0xCDu, 0x4Eu, 0xBBu, 0xA7u, + 0x7Cu, 0xB3u, 0xB3u, 0x68u, 0x08u, 0x86u, 0x0Du, 0x84u, + 0x46u, 0x8Eu, 0x69u, 0x20u, 0xCCu, 0x2Fu, 0x6Bu, 0xB9u, + 0x61u, 0xC4u, 0x00u, 0x26u, 0xAAu, 0x29u, 0xB9u, 0x85u, + /* 0x0x4ff0e991322d07ff5930ea5069e5860bff6fdb2b19137640d4b38519d6bf7b7fa1ca1d02fe048f8d [BE] */ + 0x8Du, 0x8Fu, 0x04u, 0xFEu, 0x02u, 0x1Du, 0xCAu, 0xA1u, + 0x7Fu, 0x7Bu, 0xBFu, 0xD6u, 0x19u, 0x85u, 0xB3u, 0xD4u, + 0x40u, 0x76u, 0x13u, 0x19u, 0x2Bu, 0xDBu, 0x6Fu, 0xFFu, + 0x0Bu, 0x86u, 0xE5u, 0x69u, 0x50u, 0xEAu, 0x30u, 0x59u, + 0xFFu, 0x07u, 0x2Du, 0x32u, 0x91u, 0xE9u, 0xF0u, 0x4Fu +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP320t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP320t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP320r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP320r1_N, + .common.pR2P = (uint8_t *) &brainpoolP320r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP320r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP320t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP320t1_B, + .common.pGx = (uint8_t *) &brainpoolP320t1_GX, + .common.pGy = (uint8_t *) &brainpoolP320t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP320t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP384t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP384t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + /* A = 0x8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC50 [BE] */ + 0x50u, 0xECu, 0x07u, 0x31u, 0x13u, 0x00u, 0x47u, 0x87u, + 0x71u, 0x1Au, 0x1Du, 0x90u, 0x29u, 0xA7u, 0xD3u, 0xACu, + 0x23u, 0x11u, 0xB7u, 0x7Fu, 0x19u, 0xDAu, 0xB1u, 0x12u, + 0xB4u, 0x56u, 0x54u, 0xEDu, 0x09u, 0x71u, 0x2Fu, 0x15u, + 0xDFu, 0x41u, 0xE6u, 0x50u, 0x7Eu, 0x6Fu, 0x5Du, 0x0Fu, + 0x28u, 0x6Du, 0x38u, 0xA3u, 0x82u, 0x1Eu, 0xB9u, 0x8Cu +}; + +static const uint8_t brainpoolP384t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + /* B = 0x7F519EADA7BDA81BD826DBA647910F8C4B9346ED8CCDC64E4B1ABD11756DCE1D2074AA263B88805CED70355A33B471EE [BE] */ + 0xEEu, 0x71u, 0xB4u, 0x33u, 0x5Au, 0x35u, 0x70u, 0xEDu, + 0x5Cu, 0x80u, 0x88u, 0x3Bu, 0x26u, 0xAAu, 0x74u, 0x20u, + 0x1Du, 0xCEu, 0x6Du, 0x75u, 0x11u, 0xBDu, 0x1Au, 0x4Bu, + 0x4Eu, 0xC6u, 0xCDu, 0x8Cu, 0xEDu, 0x46u, 0x93u, 0x4Bu, + 0x8Cu, 0x0Fu, 0x91u, 0x47u, 0xA6u, 0xDBu, 0x26u, 0xD8u, + 0x1Bu, 0xA8u, 0xBDu, 0xA7u, 0xADu, 0x9Eu, 0x51u, 0x7Fu +}; + +static const uint8_t brainpoolP384t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + /* PointGX = 0x18DE98B02DB9A306F2AFCD7235F72A819B80AB12EBD653172476FECD462AABFFC4FF191B946A5F54D8D0AA2F418808CC [BE] */ + 0xCCu, 0x08u, 0x88u, 0x41u, 0x2Fu, 0xAAu, 0xD0u, 0xD8u, + 0x54u, 0x5Fu, 0x6Au, 0x94u, 0x1Bu, 0x19u, 0xFFu, 0xC4u, + 0xFFu, 0xABu, 0x2Au, 0x46u, 0xCDu, 0xFEu, 0x76u, 0x24u, + 0x17u, 0x53u, 0xD6u, 0xEBu, 0x12u, 0xABu, 0x80u, 0x9Bu, + 0x81u, 0x2Au, 0xF7u, 0x35u, 0x72u, 0xCDu, 0xAFu, 0xF2u, + 0x06u, 0xA3u, 0xB9u, 0x2Du, 0xB0u, 0x98u, 0xDEu, 0x18u +}; + +static const uint8_t brainpoolP384t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + /* PointGY = 0x25AB056962D30651A114AFD2755AD336747F93475B7A1FCA3B88F2B6A208CCFE469408584DC2B2912675BF5B9E582928 [BE] */ + 0x28u, 0x29u, 0x58u, 0x9Eu, 0x5Bu, 0xBFu, 0x75u, 0x26u, + 0x91u, 0xB2u, 0xC2u, 0x4Du, 0x58u, 0x08u, 0x94u, 0x46u, + 0xFEu, 0xCCu, 0x08u, 0xA2u, 0xB6u, 0xF2u, 0x88u, 0x3Bu, + 0xCAu, 0x1Fu, 0x7Au, 0x5Bu, 0x47u, 0x93u, 0x7Fu, 0x74u, + 0x36u, 0xD3u, 0x5Au, 0x75u, 0xD2u, 0xAFu, 0x14u, 0xA1u, + 0x51u, 0x06u, 0xD3u, 0x62u, 0x69u, 0x05u, 0xABu, 0x25u +}; + +static const uint8_t brainpoolP384t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + /* 0x29a4dda85b9410db63d95d3cd39f37dad9036fd6f8474f68422425e5d858d5311c8cd512d7dafaed011c514c55c37501 [BE] */ + 0x01u, 0x75u, 0xC3u, 0x55u, 0x4Cu, 0x51u, 0x1Cu, 0x01u, + 0xEDu, 0xFAu, 0xDAu, 0xD7u, 0x12u, 0xD5u, 0x8Cu, 0x1Cu, + 0x31u, 0xD5u, 0x58u, 0xD8u, 0xE5u, 0x25u, 0x24u, 0x42u, + 0x68u, 0x4Fu, 0x47u, 0xF8u, 0xD6u, 0x6Fu, 0x03u, 0xD9u, + 0xDAu, 0x37u, 0x9Fu, 0xD3u, 0x3Cu, 0x5Du, 0xD9u, 0x63u, + 0xDBu, 0x10u, 0x94u, 0x5Bu, 0xA8u, 0xDDu, 0xA4u, 0x29u, + /* 0x620bbb7547e1443d3971c047850c29be1b530a9715a13ed252347a58b1d6a7e3bbc0a3615055a0b5176b934ffa82bc28 [BE] */ + 0x28u, 0xBCu, 0x82u, 0xFAu, 0x4Fu, 0x93u, 0x6Bu, 0x17u, + 0xB5u, 0xA0u, 0x55u, 0x50u, 0x61u, 0xA3u, 0xC0u, 0xBBu, + 0xE3u, 0xA7u, 0xD6u, 0xB1u, 0x58u, 0x7Au, 0x34u, 0x52u, + 0xD2u, 0x3Eu, 0xA1u, 0x15u, 0x97u, 0x0Au, 0x53u, 0x1Bu, + 0xBEu, 0x29u, 0x0Cu, 0x85u, 0x47u, 0xC0u, 0x71u, 0x39u, + 0x3Du, 0x44u, 0xE1u, 0x47u, 0x75u, 0xBBu, 0x0Bu, 0x62u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP384t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP384t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP384r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP384r1_N, + .common.pR2P = (uint8_t *) &brainpoolP384r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP384r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP384t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP384t1_B, + .common.pGx = (uint8_t *) &brainpoolP384t1_GX, + .common.pGy = (uint8_t *) &brainpoolP384t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP384t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + +/**********************************************************/ +/* brainpoolP512t1 Curve parameters (LE) */ +/**********************************************************/ + +static const uint8_t brainpoolP512t1_A[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + /* A = 0xAADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F0 [BE] */ + 0xF0u, 0x48u, 0x3Au, 0x58u, 0x56u, 0x60u, 0xAAu, 0x28u, + 0x85u, 0xC6u, 0x82u, 0x2Du, 0x2Fu, 0xFFu, 0x81u, 0x28u, + 0xE6u, 0x80u, 0xA3u, 0xE6u, 0x2Au, 0xA1u, 0xCDu, 0xAEu, + 0x42u, 0x68u, 0xC6u, 0x9Bu, 0x00u, 0x9Bu, 0x4Du, 0x7Du, + 0x71u, 0x08u, 0x33u, 0x70u, 0xCAu, 0x9Cu, 0x63u, 0xD6u, + 0x0Eu, 0xD2u, 0xC9u, 0xB3u, 0xB3u, 0x8Du, 0x30u, 0xCBu, + 0x07u, 0xFCu, 0xC9u, 0x33u, 0xAEu, 0xE6u, 0xD4u, 0x3Fu, + 0x8Bu, 0xC4u, 0xE9u, 0xDBu, 0xB8u, 0x9Du, 0xDDu, 0xAAu +}; + +static const uint8_t brainpoolP512t1_B[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + /* B = 0x7CBBBCF9441CFAB76E1890E46884EAE321F70C0BCB4981527897504BEC3E36A62BCDFA2304976540F6450085F2DAE145C22553B465763689180EA2571867423E [BE] */ + 0x3Eu, 0x42u, 0x67u, 0x18u, 0x57u, 0xA2u, 0x0Eu, 0x18u, + 0x89u, 0x36u, 0x76u, 0x65u, 0xB4u, 0x53u, 0x25u, 0xC2u, + 0x45u, 0xE1u, 0xDAu, 0xF2u, 0x85u, 0x00u, 0x45u, 0xF6u, + 0x40u, 0x65u, 0x97u, 0x04u, 0x23u, 0xFAu, 0xCDu, 0x2Bu, + 0xA6u, 0x36u, 0x3Eu, 0xECu, 0x4Bu, 0x50u, 0x97u, 0x78u, + 0x52u, 0x81u, 0x49u, 0xCBu, 0x0Bu, 0x0Cu, 0xF7u, 0x21u, + 0xE3u, 0xEAu, 0x84u, 0x68u, 0xE4u, 0x90u, 0x18u, 0x6Eu, + 0xB7u, 0xFAu, 0x1Cu, 0x44u, 0xF9u, 0xBCu, 0xBBu, 0x7Cu +}; + +static const uint8_t brainpoolP512t1_GX[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + /* PointGX = 0x640ECE5C12788717B9C1BA06CBC2A6FEBA85842458C56DDE9DB1758D39C0313D82BA51735CDB3EA499AA77A7D6943A64F7A3F25FE26F06B51BAA2696FA9035DA [BE] */ + 0xDAu, 0x35u, 0x90u, 0xFAu, 0x96u, 0x26u, 0xAAu, 0x1Bu, + 0xB5u, 0x06u, 0x6Fu, 0xE2u, 0x5Fu, 0xF2u, 0xA3u, 0xF7u, + 0x64u, 0x3Au, 0x94u, 0xD6u, 0xA7u, 0x77u, 0xAAu, 0x99u, + 0xA4u, 0x3Eu, 0xDBu, 0x5Cu, 0x73u, 0x51u, 0xBAu, 0x82u, + 0x3Du, 0x31u, 0xC0u, 0x39u, 0x8Du, 0x75u, 0xB1u, 0x9Du, + 0xDEu, 0x6Du, 0xC5u, 0x58u, 0x24u, 0x84u, 0x85u, 0xBAu, + 0xFEu, 0xA6u, 0xC2u, 0xCBu, 0x06u, 0xBAu, 0xC1u, 0xB9u, + 0x17u, 0x87u, 0x78u, 0x12u, 0x5Cu, 0xCEu, 0x0Eu, 0x64u +}; + +static const uint8_t brainpoolP512t1_GY[] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + /* PointGY = 0x5B534BD595F5AF0FA2C892376C84ACE1BB4E3019B71634C01131159CAE03CEE9D9932184BEEF216BD71DF2DADF86A627306ECFF96DBB8BACE198B61E00F8B332 [BE] */ + 0x32u, 0xB3u, 0xF8u, 0x00u, 0x1Eu, 0xB6u, 0x98u, 0xE1u, + 0xACu, 0x8Bu, 0xBBu, 0x6Du, 0xF9u, 0xCFu, 0x6Eu, 0x30u, + 0x27u, 0xA6u, 0x86u, 0xDFu, 0xDAu, 0xF2u, 0x1Du, 0xD7u, + 0x6Bu, 0x21u, 0xEFu, 0xBEu, 0x84u, 0x21u, 0x93u, 0xD9u, + 0xE9u, 0xCEu, 0x03u, 0xAEu, 0x9Cu, 0x15u, 0x31u, 0x11u, + 0xC0u, 0x34u, 0x16u, 0xB7u, 0x19u, 0x30u, 0x4Eu, 0xBBu, + 0xE1u, 0xACu, 0x84u, 0x6Cu, 0x37u, 0x92u, 0xC8u, 0xA2u, + 0x0Fu, 0xAFu, 0xF5u, 0x95u, 0xD5u, 0x4Bu, 0x53u, 0x5Bu +}; + +static const uint8_t brainpoolP512t1_PRECG[MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP * 2u] __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + /* 0xc26d7c5f9a7e9cfc3092bb291ec5b5c79a6581ef89311fb3842fc4b52cef4b3d2a9253c0a8789ef5c82f91e0a53ef5e03b91a8a1457108be53595c10c79bab1 [BE] */ + 0xB1u, 0xBAu, 0x79u, 0x0Cu, 0xC1u, 0x95u, 0x35u, 0xE5u, + 0x8Bu, 0x10u, 0x57u, 0x14u, 0x8Au, 0x1Au, 0xB9u, 0x03u, + 0x5Eu, 0xEFu, 0x53u, 0x0Au, 0x1Eu, 0xF9u, 0x82u, 0x5Cu, + 0xEFu, 0x89u, 0x87u, 0x0Au, 0x3Cu, 0x25u, 0xA9u, 0xD2u, + 0xB3u, 0xF4u, 0xCEu, 0x52u, 0x4Bu, 0xFCu, 0x42u, 0x38u, + 0xFBu, 0x11u, 0x93u, 0xF8u, 0x1Eu, 0x58u, 0xA6u, 0x79u, + 0x5Cu, 0x5Bu, 0xECu, 0x91u, 0xB2u, 0x2Bu, 0x09u, 0xC3u, + 0xCFu, 0xE9u, 0xA7u, 0xF9u, 0xC5u, 0xD7u, 0x26u, 0x0Cu, + /* 0x6011322420f417fa2e593a3ac169a94ee66a1227a42ee0e632de6752458e66565ead4d382169a231a9dd3f27c4b0eeadf3206540fbdcab90c1b06cc28b91e6d7 [BE] */ + 0xD7u, 0xE6u, 0x91u, 0x8Bu, 0xC2u, 0x6Cu, 0xB0u, 0xC1u, + 0x90u, 0xABu, 0xDCu, 0xFBu, 0x40u, 0x65u, 0x20u, 0xF3u, + 0xADu, 0xEEu, 0xB0u, 0xC4u, 0x27u, 0x3Fu, 0xDDu, 0xA9u, + 0x31u, 0xA2u, 0x69u, 0x21u, 0x38u, 0x4Du, 0xADu, 0x5Eu, + 0x56u, 0x66u, 0x8Eu, 0x45u, 0x52u, 0x67u, 0xDEu, 0x32u, + 0xE6u, 0xE0u, 0x2Eu, 0xA4u, 0x27u, 0x12u, 0x6Au, 0xE6u, + 0x4Eu, 0xA9u, 0x69u, 0xC1u, 0x3Au, 0x3Au, 0x59u, 0x2Eu, + 0xFAu, 0x17u, 0xF4u, 0x20u, 0x24u, 0x32u, 0x11u, 0x60u +}; + +const mcuxClEcc_Weier_DomainParams_t mcuxClEcc_Weier_DomainParams_brainpoolP512t1 __attribute__((section(".rodata.curve.mcuxClEcc_Weier_brainpoolP512t1"))) = +{ + .common.byteLenP = MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &brainpoolP512r1_P, + .common.pFullModulusN = (uint8_t *) &brainpoolP512r1_N, + .common.pR2P = (uint8_t *) &brainpoolP512r1_R2P, + .common.pR2N = (uint8_t *) &brainpoolP512r1_R2N, + .common.pCurveParam1 = (uint8_t *) &brainpoolP512t1_A, + .common.pCurveParam2 = (uint8_t *) &brainpoolP512t1_B, + .common.pGx = (uint8_t *) &brainpoolP512t1_GX, + .common.pGy = (uint8_t *) &brainpoolP512t1_GY, + .common.pPrecPoints = (uint8_t *) &brainpoolP512t1_PRECG, + .common.pLadderConst = NULL, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL +}; + + +/**********************************************************/ +/* EdDSA domain parameters */ +/**********************************************************/ + +/* Ed25519 domain parameters */ +static const uint8_t pEd25519_FullP[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // p = 0x7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffed [BE] + // pDash = 0x86bca1af286bca1b [BE] + 0x1bu, 0xcau, 0x6bu, 0x28u, 0xafu, 0xa1u, 0xbcu, 0x86u, + 0xedu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x7fu +}; + +static const uint8_t pEd25519_FullN[MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // n = 0x1000000000000000000000000000000014def9dea2f79cd65812631a5cf5d3ed [BE] + // nDash = 0xd2b51da312547e1b [BE] + 0x1bu, 0x7eu, 0x54u, 0x12u, 0xa3u, 0x1du, 0xb5u, 0xd2u, + 0xedu, 0xd3u, 0xf5u, 0x5cu, 0x1au, 0x63u, 0x12u, 0x58u, 0xd6u, 0x9cu, 0xf7u, 0xa2u, 0xdeu, 0xf9u, 0xdeu, 0x14u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u +}; + +static const uint8_t pEd25519_R2P[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // R2P = 0x00000000000000000000000000000000000000000000000000000000000005a4 [BE] + 0xa4u, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pEd25519_R2N[MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // R2N = 0x0399411b7c309a3dceec73d217f5be65d00e1ba768859347a40611e3449c0f01 [BE] + 0x01u, 0x0fu, 0x9cu, 0x44u, 0xe3u, 0x11u, 0x06u, 0xa4u, 0x47u, 0x93u, 0x85u, 0x68u, 0xa7u, 0x1bu, 0x0eu, 0xd0u, + 0x65u, 0xbeu, 0xf5u, 0x17u, 0xd2u, 0x73u, 0xecu, 0xceu, 0x3du, 0x9au, 0x30u, 0x7cu, 0x1bu, 0x41u, 0x99u, 0x03u +}; + +static const uint8_t pEd25519_PointGX[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // PointGX = 0x216936d3cd6e53fec0a4e231fdd6dc5c692cc7609525a7b2c9562d608f25d51a [BE] + 0x1au, 0xd5u, 0x25u, 0x8fu, 0x60u, 0x2du, 0x56u, 0xc9u, 0xb2u, 0xa7u, 0x25u, 0x95u, 0x60u, 0xc7u, 0x2cu, 0x69u, + 0x5cu, 0xdcu, 0xd6u, 0xfdu, 0x31u, 0xe2u, 0xa4u, 0xc0u, 0xfeu, 0x53u, 0x6eu, 0xcdu, 0xd3u, 0x36u, 0x69u, 0x21u +}; + +static const uint8_t pEd25519_PointGY[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // PointGY = 0x6666666666666666666666666666666666666666666666666666666666666658 [BE] + 0x58u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, + 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u, 0x66u +}; + +static const uint8_t pEd25519_PrecPoints[16u * MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // Precomputed points are stored concatenated as P0.x||P0.y||...||P7.x||P7.y, each coordinate is given in MR in LE format + 0x4cu, 0x1au, 0xc9u, 0x50u, 0x39u, 0x30u, 0x3eu, 0x39u, 0xdbu, 0x8bu, 0x3au, 0xc9u, 0x01u, 0x44u, 0x7fu, 0xafu, 0xd4u, 0xffu, 0xf7u, 0xf1u, 0x39u, 0x4bu, 0x5cu, 0xe0u, 0xe7u, 0xfbu, 0x0fu, 0x1cu, 0x8du, 0xbdu, 0x7du, 0x7cu, + 0x3cu, 0x85u, 0x15u, 0x7du, 0xecu, 0x21u, 0x87u, 0x09u, 0xf2u, 0x17u, 0xdeu, 0xdau, 0xc9u, 0x01u, 0x22u, 0xb7u, 0x74u, 0xedu, 0x78u, 0x02u, 0x16u, 0x3eu, 0x5fu, 0x94u, 0xddu, 0x94u, 0x2cu, 0x3du, 0xdcu, 0x18u, 0xbeu, 0x61u, + 0xd6u, 0x91u, 0xd3u, 0xc0u, 0x6fu, 0xa4u, 0x36u, 0x4eu, 0x58u, 0x97u, 0xcbu, 0x70u, 0x85u, 0x07u, 0x30u, 0xeau, 0xdau, 0x0bu, 0x05u, 0xb8u, 0x48u, 0xc2u, 0x4au, 0x59u, 0x74u, 0xcau, 0x7cu, 0x4fu, 0xe3u, 0x67u, 0xecu, 0x1du, + 0x37u, 0x71u, 0x2fu, 0xedu, 0x29u, 0xabu, 0x90u, 0x0cu, 0x53u, 0x89u, 0x87u, 0x0cu, 0x3fu, 0xe6u, 0x61u, 0x88u, 0x87u, 0x9fu, 0x94u, 0x5eu, 0xd8u, 0x34u, 0xf2u, 0x8eu, 0x1du, 0x88u, 0xd0u, 0x5bu, 0x7fu, 0x7eu, 0x70u, 0x01u, + 0x32u, 0x8fu, 0xb5u, 0xeau, 0x19u, 0x6eu, 0x4au, 0xf4u, 0x89u, 0x48u, 0x75u, 0x3au, 0xe1u, 0x40u, 0xb0u, 0x7eu, 0x2du, 0xe8u, 0xf4u, 0xb1u, 0x2eu, 0x5cu, 0x19u, 0x9au, 0x5eu, 0xeau, 0xbbu, 0x72u, 0x79u, 0xfdu, 0x45u, 0x3cu, + 0x03u, 0x2du, 0x58u, 0x73u, 0xf1u, 0xa2u, 0x4bu, 0xadu, 0xccu, 0x38u, 0x75u, 0xafu, 0xa2u, 0xe7u, 0xd5u, 0x2fu, 0x66u, 0xefu, 0x2eu, 0x7du, 0x66u, 0x14u, 0x65u, 0xf2u, 0x51u, 0x9bu, 0x55u, 0x41u, 0xf8u, 0x29u, 0xabu, 0x21u, + 0x17u, 0x50u, 0x9au, 0x96u, 0x9eu, 0x64u, 0xb6u, 0x4bu, 0x22u, 0x67u, 0xb5u, 0x19u, 0x6au, 0x0au, 0xd4u, 0xe5u, 0x90u, 0xe9u, 0x13u, 0xaeu, 0x0eu, 0xc7u, 0xa1u, 0x44u, 0x39u, 0x88u, 0xd0u, 0x3au, 0xc1u, 0xa0u, 0x17u, 0x20u, + 0xedu, 0xaau, 0xb4u, 0xffu, 0x53u, 0x8eu, 0xeeu, 0x87u, 0xa5u, 0x23u, 0x9cu, 0x82u, 0xb1u, 0x44u, 0xc6u, 0x9du, 0xabu, 0x97u, 0x66u, 0xf4u, 0x7bu, 0xb6u, 0x30u, 0x30u, 0x12u, 0xfeu, 0x0fu, 0xecu, 0x2fu, 0xa3u, 0xc1u, 0x60u, + 0xa3u, 0xdfu, 0x3au, 0x3fu, 0xedu, 0xd6u, 0x19u, 0x56u, 0x00u, 0x13u, 0x30u, 0x48u, 0xa0u, 0xd4u, 0xa4u, 0x18u, 0x05u, 0x82u, 0x7du, 0xf6u, 0x76u, 0xc2u, 0x31u, 0xbdu, 0x33u, 0xb9u, 0x15u, 0x16u, 0xbeu, 0xdcu, 0xa9u, 0x6du, + 0x10u, 0xb4u, 0x08u, 0x9eu, 0x62u, 0x14u, 0x2du, 0x0du, 0x11u, 0x91u, 0x73u, 0xd2u, 0x7eu, 0xc8u, 0xa7u, 0x7eu, 0x69u, 0xbfu, 0x99u, 0x53u, 0x17u, 0xe4u, 0x28u, 0xcdu, 0x0bu, 0xd2u, 0x10u, 0x88u, 0x0cu, 0xd0u, 0x6bu, 0x1du, + 0xe7u, 0xa9u, 0x77u, 0x96u, 0x7du, 0x0du, 0x81u, 0x8bu, 0xa4u, 0xd3u, 0x04u, 0xa6u, 0xa3u, 0xa9u, 0xaeu, 0x1fu, 0xeau, 0x79u, 0xe4u, 0xf9u, 0xd1u, 0x83u, 0x31u, 0xc1u, 0xccu, 0x77u, 0x5fu, 0x41u, 0xfcu, 0x9cu, 0xf1u, 0x6du, + 0xdau, 0x37u, 0xb7u, 0xf5u, 0x43u, 0x96u, 0x57u, 0x41u, 0xc9u, 0x7fu, 0x27u, 0x3au, 0x20u, 0x0au, 0x73u, 0xa2u, 0xb8u, 0x2du, 0x41u, 0xa8u, 0xa6u, 0x93u, 0x80u, 0x9du, 0xb0u, 0x94u, 0x39u, 0x49u, 0x3bu, 0x0du, 0x8fu, 0x59u, + 0x51u, 0xafu, 0x60u, 0x5fu, 0x31u, 0x40u, 0x37u, 0xc8u, 0x9fu, 0x48u, 0x94u, 0x3eu, 0xc4u, 0x6cu, 0x01u, 0x8fu, 0x1du, 0x71u, 0x36u, 0x38u, 0x28u, 0xeau, 0x49u, 0x45u, 0xcfu, 0xbcu, 0x2bu, 0xe6u, 0x1eu, 0xeau, 0x6au, 0x76u, + 0x42u, 0x90u, 0x4du, 0x70u, 0x50u, 0x5du, 0x1au, 0x9fu, 0x4au, 0x35u, 0xe1u, 0xc4u, 0xf9u, 0x0cu, 0xb9u, 0xceu, 0x2du, 0x92u, 0x50u, 0xb6u, 0x93u, 0x65u, 0xf2u, 0xcbu, 0x2du, 0x0fu, 0x41u, 0xcfu, 0xd5u, 0xb8u, 0xbcu, 0x07u, + 0xc7u, 0x3fu, 0x42u, 0xfau, 0x08u, 0x62u, 0xe4u, 0x5fu, 0x74u, 0x8fu, 0x9du, 0x11u, 0x21u, 0x18u, 0x16u, 0xdcu, 0x2cu, 0xfeu, 0xf9u, 0xfbu, 0x43u, 0xfau, 0xbau, 0xe3u, 0xdfu, 0x9au, 0x29u, 0x62u, 0x01u, 0x96u, 0x8bu, 0x6au, + 0x2bu, 0x1au, 0x1bu, 0xb5u, 0x4bu, 0x8fu, 0xf2u, 0x84u, 0x30u, 0x61u, 0x8cu, 0x41u, 0x4bu, 0xa1u, 0x11u, 0x3bu, 0xc1u, 0xc8u, 0xf3u, 0xeeu, 0x46u, 0xe0u, 0xbfu, 0x7eu, 0xf9u, 0x5bu, 0xacu, 0x7du, 0xcbu, 0xb2u, 0x98u, 0x01u +}; + +static const uint8_t pEd25519_A[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // A = 0x7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffec [BE] + 0xecu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, + 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x7fu +}; + +static const uint8_t pEd25519_D[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // D = 0x52036cee2b6ffe738cc740797779e89800700a4d4141d8ab75eb4dca135978a3 [BE] + 0xa3u, 0x78u, 0x59u, 0x13u, 0xcau, 0x4du, 0xebu, 0x75u, 0xabu, 0xd8u, 0x41u, 0x41u, 0x4du, 0x0au, 0x70u, 0x00u, + 0x98u, 0xe8u, 0x79u, 0x77u, 0x79u, 0x40u, 0xc7u, 0x8cu, 0x73u, 0xfeu, 0x6fu, 0x2bu, 0xeeu, 0x6cu, 0x03u, 0x52u +}; + +static const uint8_t pEd25519_SQRT_MINUS_ONE[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // SQRT_MINUS_ONE = 0x2b8324804fc1df0b2b4d00993dfbd7a72f431806ad2fe478c4ee1b274a0ea0b0 [BE] + 0xb0u, 0xa0u, 0x0eu, 0x4au, 0x27u, 0x1bu, 0xeeu, 0xc4u, 0x78u, 0xe4u, 0x2fu, 0xadu, 0x06u, 0x18u, 0x43u, 0x2fu, + 0xa7u, 0xd7u, 0xfbu, 0x3du, 0x99u, 0x00u, 0x4du, 0x2bu, 0x0bu, 0xdfu, 0xc1u, 0x4fu, 0x80u, 0x24u, 0x83u, 0x2bu +}; + +static const uint8_t pEd25519_LADDER_CONST[MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + // LADDER_CONST = a/d mod p = 0x3f6f812deb2a31bcd4e9deeb32463099f4a22967bd86abd1da1f0d89323607aa [BE] + 0xaau, 0x07u, 0x36u, 0x32u, 0x89u, 0x0du, 0x1fu, 0xdau, 0xd1u, 0xabu, 0x86u, 0xbdu, 0x67u, 0x29u, 0xa2u, 0xf4u, + 0x99u, 0x30u, 0x46u, 0x32u, 0xebu, 0xdeu, 0xe9u, 0xd4u, 0xbcu, 0x31u, 0x2au, 0xebu, 0x2du, 0x81u, 0x6fu, 0x3fu +}; + +/* ASCII "SigEd25519 no Ed25519 collisions" in hex for prefix generation function dom2 */ +static const uint32_t pEd25519_dom2Prefix[8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + 0x45676953u, 0x35353264u, 0x6e203931u, 0x6445206fu, + 0x31353532u, 0x6f632039u, 0x73696c6cu, 0x736e6f69u +}; + +/* Ed448 domain parameters */ +static const uint8_t pEd448_FullP[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // p = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF [BE] + // pDash = 0x0000000000000001 [BE] + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFEu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t pEd448_FullN[MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER + 8u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // n = 0x3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CCA23E9C44EDB49AED63690216CC2728DC58F552378C292AB5844F3 [BE] + // nDash = 03bd440fae918bc5 [BE] + 0xc5u, 0x8bu, 0x91u, 0xaeu, 0x0fu, 0x44u, 0xbdu, 0x03u, + 0xF3u, 0x44u, 0x58u, 0xABu, 0x92u, 0xC2u, 0x78u, 0x23u, 0x55u, 0x8Fu, 0xC5u, 0x8Du, 0x72u, 0xC2u, + 0x6Cu, 0x21u, 0x90u, 0x36u, 0xD6u, 0xAEu, 0x49u, 0xDBu, 0x4Eu, 0xC4u, 0xE9u, 0x23u, 0xCAu, 0x7Cu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x3Fu +}; + +static const uint8_t pEd448_R2P[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // R2P = 0x0000000000000000000000000000000000000000000000000000000300000000000000000000000000000000000000000000000000000002 [BE] + 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pEd448_R2N[MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // R2N = 0x3402a939f823b7292052bcb7e4d070af1a9cc14ba3c47c44ae17cf725ee4d8380d66de2388ea18597af32c4bc1b195d9e3539257049b9b60 [BE] + 0x60u, 0x9bu, 0x9bu, 0x04u, 0x57u, 0x92u, 0x53u, 0xe3u, 0xd9u, 0x95u, 0xb1u, 0xc1u, 0x4bu, 0x2cu, + 0xf3u, 0x7au, 0x59u, 0x18u, 0xeau, 0x88u, 0x23u, 0xdeu, 0x66u, 0x0du, 0x38u, 0xd8u, 0xe4u, 0x5eu, + 0x72u, 0xcfu, 0x17u, 0xaeu, 0x44u, 0x7cu, 0xc4u, 0xa3u, 0x4bu, 0xc1u, 0x9cu, 0x1au, 0xafu, 0x70u, + 0xd0u, 0xe4u, 0xb7u, 0xbcu, 0x52u, 0x20u, 0x29u, 0xb7u, 0x23u, 0xf8u, 0x39u, 0xa9u, 0x02u, 0x34u +}; + +static const uint8_t pEd448_PointGX[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // PointGX = 0x4f1970c66bed0ded221d15a622bf36da9e146570470f1767ea6de324a3d3a46412ae1af72ab66511433b80e18b00938e2626a82bc70cc05e [BE] + 0x5eu, 0xc0u, 0x0cu, 0xc7u, 0x2bu, 0xa8u, 0x26u, 0x26u, 0x8eu, 0x93u, 0x00u, 0x8bu, 0xe1u, 0x80u, 0x3bu, 0x43u, + 0x11u, 0x65u, 0xb6u, 0x2au, 0xf7u, 0x1au, 0xaeu, 0x12u, 0x64u, 0xa4u, 0xd3u, 0xa3u, 0x24u, 0xe3u, 0x6du, 0xeau, + 0x67u, 0x17u, 0x0fu, 0x47u, 0x70u, 0x65u, 0x14u, 0x9eu, 0xdau, 0x36u, 0xbfu, 0x22u, 0xa6u, 0x15u, 0x1du, 0x22u, + 0xedu, 0x0du, 0xedu, 0x6bu, 0xc6u, 0x70u, 0x19u, 0x4fu +}; + +static const uint8_t pEd448_PointGY[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // PointGY = 0x693f46716eb6bc248876203756c9c7624bea73736ca3984087789c1e05a0c2d73ad3ff1ce67c39c4fdbd132c4ed7c8ad9808795bf230fa14 [BE] + 0x14u, 0xfau, 0x30u, 0xf2u, 0x5bu, 0x79u, 0x08u, 0x98u, 0xadu, 0xc8u, 0xd7u, 0x4eu, 0x2cu, 0x13u, 0xbdu, 0xfdu, + 0xc4u, 0x39u, 0x7cu, 0xe6u, 0x1cu, 0xffu, 0xd3u, 0x3au, 0xd7u, 0xc2u, 0xa0u, 0x05u, 0x1eu, 0x9cu, 0x78u, 0x87u, + 0x40u, 0x98u, 0xa3u, 0x6cu, 0x73u, 0x73u, 0xeau, 0x4bu, 0x62u, 0xc7u, 0xc9u, 0x56u, 0x37u, 0x20u, 0x76u, 0x88u, + 0x24u, 0xbcu, 0xb6u, 0x6eu, 0x71u, 0x46u, 0x3fu, 0x69u +}; + +static const uint8_t pEd448_PrecPoints[16u * MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // Precomputed points are stored concatenated as P0.x||P0.y||...||P7.x||P7.y, each coordinate is given in MR in LE format + 0xf1u, 0x94u, 0x29u, 0x92u, 0x55u, 0x5eu, 0x12u, 0x61u, 0xc1u, 0x10u, 0x29u, 0x05u, 0xafu, 0xa9u, 0x82u, 0x1eu, 0xdeu, 0x8au, 0xbcu, 0x12u, 0x7au, 0xa7u, 0x47u, 0x8du, 0xa8u, 0x3fu, 0x89u, 0xa3u, 0x8eu, 0x2eu, 0xbcu, 0x1du, 0x2bu, 0x6cu, 0x8fu, 0x47u, 0x8eu, 0x22u, 0xa9u, 0x72u, 0x93u, 0xabu, 0xfcu, 0xbdu, 0xa0u, 0xe4u, 0xcfu, 0x77u, 0xeeu, 0xfau, 0xdau, 0x76u, 0x02u, 0x7du, 0x6cu, 0x5au, + 0x50u, 0xdfu, 0x37u, 0xb4u, 0x62u, 0x03u, 0xb2u, 0xd8u, 0xc1u, 0x01u, 0x00u, 0x63u, 0x06u, 0x8bu, 0x46u, 0x7du, 0x60u, 0x20u, 0x1eu, 0x63u, 0x23u, 0x29u, 0xa6u, 0x4eu, 0x9du, 0xdeu, 0xaau, 0x4eu, 0xe5u, 0xccu, 0x16u, 0x74u, 0xf2u, 0x7cu, 0x9du, 0x99u, 0xf1u, 0x3bu, 0xafu, 0x24u, 0x50u, 0x28u, 0x95u, 0x53u, 0xf6u, 0x22u, 0xd8u, 0xbdu, 0xf5u, 0x29u, 0xb2u, 0x2fu, 0x95u, 0xedu, 0x25u, 0x0au, + 0xf0u, 0x4bu, 0xc5u, 0x09u, 0x5bu, 0x37u, 0xa5u, 0xbeu, 0xc8u, 0xc8u, 0xefu, 0xddu, 0x8bu, 0xbdu, 0xecu, 0xb3u, 0x41u, 0x43u, 0x75u, 0xe7u, 0x7eu, 0x65u, 0x4cu, 0x64u, 0xffu, 0xbdu, 0xf8u, 0x27u, 0x1fu, 0x40u, 0x7au, 0xefu, 0x92u, 0xd7u, 0x05u, 0x85u, 0xd7u, 0xd8u, 0x90u, 0xf0u, 0x59u, 0x57u, 0x5eu, 0x4fu, 0x3au, 0x9cu, 0x07u, 0xfeu, 0xc2u, 0x8cu, 0x92u, 0x0au, 0x93u, 0x8bu, 0x0du, 0x60u, + 0x49u, 0x0cu, 0xaeu, 0xa7u, 0xa9u, 0x28u, 0xa4u, 0x01u, 0x1au, 0x16u, 0xf5u, 0x74u, 0x53u, 0x0eu, 0x71u, 0xf9u, 0x63u, 0x26u, 0x46u, 0xd4u, 0x6du, 0x39u, 0x6du, 0x31u, 0x1cu, 0x81u, 0x36u, 0xf8u, 0x60u, 0x17u, 0xa7u, 0x83u, 0xe5u, 0xb2u, 0x81u, 0xe7u, 0xccu, 0x5fu, 0x04u, 0xc5u, 0xfcu, 0xacu, 0x14u, 0x57u, 0xf5u, 0xd0u, 0x2fu, 0xc6u, 0x5au, 0x05u, 0x6fu, 0x8fu, 0x99u, 0xf2u, 0x2du, 0x06u, + 0x6du, 0x4bu, 0x5bu, 0xffu, 0xfau, 0x2bu, 0x5eu, 0xc5u, 0x20u, 0x13u, 0x1fu, 0x99u, 0x03u, 0x45u, 0x96u, 0x32u, 0x25u, 0xa1u, 0x93u, 0xf7u, 0x66u, 0x69u, 0x79u, 0x65u, 0x84u, 0x37u, 0x90u, 0x2eu, 0xddu, 0xc6u, 0x6fu, 0xa5u, 0x87u, 0x9fu, 0xfcu, 0xfau, 0x5eu, 0x93u, 0xa0u, 0xbbu, 0x6cu, 0x65u, 0xa7u, 0x41u, 0x6fu, 0xf3u, 0x9bu, 0x09u, 0xb3u, 0x55u, 0xb6u, 0xf0u, 0xcfu, 0x3eu, 0xb4u, 0x72u, + 0x10u, 0xe7u, 0xb4u, 0x3fu, 0x44u, 0x91u, 0xf9u, 0x45u, 0xccu, 0xc1u, 0x82u, 0xf7u, 0xdau, 0x6au, 0x1bu, 0x71u, 0xeau, 0xc8u, 0xfcu, 0x94u, 0x9cu, 0x72u, 0xabu, 0x09u, 0x07u, 0x3bu, 0x5bu, 0x21u, 0xe7u, 0xcbu, 0x5cu, 0xbau, 0x5au, 0xdcu, 0xe2u, 0x3eu, 0xefu, 0xf2u, 0x5cu, 0x54u, 0xd1u, 0xa2u, 0x2eu, 0x59u, 0x74u, 0x57u, 0x65u, 0xf4u, 0x8du, 0xb5u, 0x47u, 0x9au, 0x4du, 0xccu, 0x96u, 0xb3u, + 0x75u, 0x29u, 0x91u, 0x6du, 0x42u, 0x3du, 0x7cu, 0x0eu, 0x6du, 0x5eu, 0x94u, 0x62u, 0xd5u, 0x05u, 0xd1u, 0x24u, 0x27u, 0x97u, 0x97u, 0xdau, 0xd8u, 0x82u, 0xbeu, 0x94u, 0xcfu, 0x96u, 0x8bu, 0x58u, 0x38u, 0x51u, 0x15u, 0x76u, 0x72u, 0xc0u, 0x67u, 0x15u, 0x47u, 0x89u, 0x63u, 0x28u, 0xecu, 0xc8u, 0xf7u, 0xe9u, 0xecu, 0xbau, 0x46u, 0x4du, 0x6bu, 0xdau, 0x90u, 0x65u, 0xc4u, 0xf2u, 0x80u, 0xafu, + 0x7eu, 0x05u, 0x7fu, 0x70u, 0x57u, 0x51u, 0x89u, 0xb4u, 0x5fu, 0x0bu, 0xc6u, 0x3fu, 0x4du, 0x35u, 0x31u, 0x9eu, 0x03u, 0x01u, 0xa1u, 0xb1u, 0xbfu, 0x34u, 0x4au, 0x5au, 0xe6u, 0x8bu, 0x8bu, 0x8cu, 0x84u, 0xfeu, 0x12u, 0xbcu, 0x89u, 0x1au, 0x1cu, 0xd3u, 0x87u, 0x98u, 0x20u, 0x04u, 0xdfu, 0x5bu, 0x2eu, 0x02u, 0x17u, 0xc3u, 0x68u, 0x4du, 0xedu, 0x9fu, 0xe4u, 0x59u, 0x21u, 0xdfu, 0x43u, 0xbau, + 0xadu, 0xd4u, 0x83u, 0x97u, 0xa6u, 0x2bu, 0x3du, 0x5au, 0x62u, 0xfdu, 0x43u, 0xb4u, 0x5eu, 0x87u, 0xc1u, 0xaeu, 0xd2u, 0xc1u, 0x86u, 0xd2u, 0x0au, 0xdau, 0x3fu, 0x2fu, 0x30u, 0x01u, 0xdau, 0x70u, 0xbdu, 0x7eu, 0xffu, 0xbeu, 0xb8u, 0x92u, 0x6cu, 0x96u, 0x7eu, 0x67u, 0x8fu, 0x9cu, 0xb9u, 0x74u, 0xd8u, 0x4bu, 0x06u, 0x38u, 0x69u, 0x25u, 0x4eu, 0xdeu, 0x3cu, 0xe3u, 0xf7u, 0x58u, 0xc6u, 0x81u, + 0x6au, 0xb7u, 0xecu, 0x65u, 0x93u, 0xe6u, 0x8du, 0xa1u, 0xb0u, 0x95u, 0xbfu, 0xcfu, 0x3du, 0xceu, 0xa7u, 0x3au, 0xbau, 0x68u, 0xabu, 0x0cu, 0x44u, 0x7cu, 0xf6u, 0x25u, 0x06u, 0xeeu, 0x0du, 0x3au, 0x52u, 0x70u, 0xefu, 0x40u, 0x5au, 0xb7u, 0x4au, 0xc2u, 0xf3u, 0xdeu, 0x8eu, 0x5fu, 0x7bu, 0x07u, 0x48u, 0x4au, 0xa5u, 0x38u, 0x53u, 0x6fu, 0x64u, 0x58u, 0xb3u, 0x4au, 0x09u, 0x78u, 0xb7u, 0xfau, + 0xf2u, 0x70u, 0x5bu, 0x94u, 0x74u, 0xe0u, 0x4du, 0x6eu, 0xebu, 0x71u, 0x9fu, 0x63u, 0xedu, 0x29u, 0xc2u, 0x1eu, 0x57u, 0x1du, 0xf7u, 0xa6u, 0xc9u, 0xbau, 0x06u, 0xb6u, 0xe7u, 0x20u, 0x86u, 0x34u, 0x49u, 0x15u, 0x36u, 0xd8u, 0x91u, 0x3bu, 0x88u, 0x57u, 0xcfu, 0x76u, 0x71u, 0x52u, 0x1du, 0x73u, 0xcbu, 0x79u, 0x12u, 0x0au, 0xbau, 0xaeu, 0x05u, 0x6du, 0xccu, 0xb5u, 0xe8u, 0xa6u, 0xbau, 0x58u, + 0x7bu, 0xd0u, 0x8bu, 0xb3u, 0x75u, 0x67u, 0x21u, 0x22u, 0x9bu, 0x3cu, 0x51u, 0x39u, 0x2fu, 0x70u, 0xdeu, 0x50u, 0x87u, 0x1cu, 0xb4u, 0xf0u, 0x51u, 0x93u, 0x09u, 0x88u, 0x6fu, 0xbfu, 0x27u, 0xd0u, 0x47u, 0x9fu, 0x97u, 0xc1u, 0xdcu, 0x19u, 0xf6u, 0x6du, 0x6fu, 0x49u, 0xfeu, 0x19u, 0xdeu, 0xa0u, 0xb2u, 0x1eu, 0x4cu, 0x36u, 0x6bu, 0xa7u, 0x14u, 0x65u, 0x90u, 0x6cu, 0x76u, 0x2bu, 0xaeu, 0xa4u, + 0xf4u, 0x5eu, 0x2au, 0x56u, 0x2bu, 0x7fu, 0xfdu, 0x5eu, 0x42u, 0xc1u, 0x3du, 0x8fu, 0x17u, 0x8cu, 0xbbu, 0x73u, 0xa8u, 0x6eu, 0x80u, 0x3eu, 0x1fu, 0xafu, 0xaau, 0x68u, 0x8fu, 0xdcu, 0x5au, 0x57u, 0xcdu, 0x40u, 0x73u, 0x1fu, 0x7cu, 0x57u, 0x63u, 0x85u, 0xe7u, 0xa5u, 0xe9u, 0x24u, 0x63u, 0x0au, 0x3bu, 0xd3u, 0x32u, 0xf8u, 0x4eu, 0x4du, 0x87u, 0xbcu, 0xf5u, 0x01u, 0x86u, 0xa0u, 0x05u, 0x7du, + 0x74u, 0x68u, 0xcau, 0x2eu, 0x10u, 0xd8u, 0xc0u, 0xcbu, 0x98u, 0xa9u, 0x57u, 0x65u, 0x8cu, 0x61u, 0xd5u, 0x75u, 0x63u, 0xdcu, 0xccu, 0xfau, 0xf4u, 0xf9u, 0x95u, 0xcdu, 0x46u, 0x71u, 0xfbu, 0xd2u, 0x16u, 0xbbu, 0xf6u, 0x11u, 0xdcu, 0x29u, 0xd8u, 0xe8u, 0x93u, 0x07u, 0xeeu, 0x69u, 0xc5u, 0x8eu, 0xd4u, 0x37u, 0x36u, 0x70u, 0xc5u, 0xa7u, 0x8au, 0xdcu, 0xb9u, 0xd4u, 0x17u, 0x2bu, 0x45u, 0xa8u, + 0xb5u, 0x05u, 0x11u, 0x4du, 0x14u, 0x48u, 0xa4u, 0xa1u, 0xaau, 0xb1u, 0x7du, 0xdau, 0xd1u, 0x66u, 0x88u, 0x6fu, 0x75u, 0x80u, 0xeau, 0x5cu, 0xddu, 0xebu, 0xdeu, 0x1cu, 0x06u, 0xaau, 0x28u, 0x05u, 0x4bu, 0xf7u, 0xcbu, 0x17u, 0x45u, 0xafu, 0x56u, 0xcfu, 0x2eu, 0xb8u, 0x8au, 0xc0u, 0xcdu, 0xddu, 0x60u, 0x3au, 0xf6u, 0x95u, 0xc3u, 0x70u, 0x03u, 0xccu, 0x69u, 0x73u, 0xe1u, 0x5bu, 0x0eu, 0xc8u, + 0xbeu, 0x78u, 0x0fu, 0x85u, 0xdfu, 0xd4u, 0x81u, 0xc0u, 0xaeu, 0x50u, 0x63u, 0x4du, 0xd0u, 0x40u, 0x9du, 0xa6u, 0x50u, 0x53u, 0x08u, 0x62u, 0x80u, 0x4cu, 0xe8u, 0x3fu, 0x1eu, 0x72u, 0xd1u, 0xd6u, 0x62u, 0x07u, 0xf8u, 0x1bu, 0x7eu, 0xdau, 0xa4u, 0xcbu, 0x6bu, 0xe3u, 0xc2u, 0x50u, 0x78u, 0x05u, 0x40u, 0xebu, 0xacu, 0x7fu, 0xcau, 0x30u, 0x7du, 0xeeu, 0x66u, 0x35u, 0xe6u, 0x79u, 0x53u, 0x30u +}; + +static const uint8_t pEd448_A[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // A = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [BE] + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +static const uint8_t pEd448_D[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // D = 0xfffffffffffffffffffffffffffffffffffffffffffffffffffffffeffffffffffffffffffffffffffffffffffffffffffffffffffff6756 [BE] + 0x56u, 0x67u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFEu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu +}; + +static const uint8_t pEd448_LADDER_CONST[MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + // LADDER_CONST = a/d mod p = 0x2874b42380f250e60db0c73d6c8c5d3352b9ea8dbd5af0c87f64e25bbed5ed186333637ed9b301652f7f668fa7049e3bdbc33cd2455ea947 [BE] + 0x47u, 0xa9u, 0x5eu, 0x45u, 0xd2u, 0x3cu, 0xc3u, 0xdbu, 0x3bu, 0x9eu, 0x04u, 0xa7u, 0x8fu, 0x66u, 0x7fu, 0x2fu, + 0x65u, 0x01u, 0xb3u, 0xd9u, 0x7eu, 0x63u, 0x33u, 0x63u, 0x18u, 0xedu, 0xd5u, 0xbeu, 0x5bu, 0xe2u, 0x64u, 0x7fu, + 0xc8u, 0xf0u, 0x5au, 0xbdu, 0x8du, 0xeau, 0xb9u, 0x52u, 0x33u, 0x5du, 0x8cu, 0x6cu, 0x3du, 0xc7u, 0xb0u, 0x0du, + 0xe6u, 0x50u, 0xf2u, 0x80u, 0x23u, 0xb4u, 0x74u, 0x28u +}; + +/* ASCII "SigEd448" in hex for prefix generation function dom4 */ +static const uint32_t pEd448_dom4Prefix[2u] __attribute__ ((aligned (4))) __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + 0x45676953u, 0x38343464u +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +static const mcuxClEcc_ScalarMultFunction_FP_t mcuxClEcc_TwEd_PlainFixScalarMult25519_FP = { + .pScalarMultFct = mcuxClEcc_TwEd_PlainFixScalarMult25519, + .scalarMultFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PlainFixScalarMult25519), +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +static const mcuxClEcc_ScalarMultFunction_FP_t mcuxClEcc_TwEd_PlainVarScalarMult_FP = { + .pScalarMultFct = mcuxClEcc_TwEd_PlainVarScalarMult, + .scalarMultFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PlainVarScalarMult), +}; + +const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed25519 __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed25519"))) = +{ + .common.byteLenP = MCUXCLECC_EDDSA_ED25519_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_EDDSA_ED25519_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &pEd25519_FullP, + .common.pFullModulusN = (uint8_t *) &pEd25519_FullN, + .common.pR2P = (uint8_t *) &pEd25519_R2P, + .common.pR2N = (uint8_t *) &pEd25519_R2N, + .common.pCurveParam1 = (uint8_t *) &pEd25519_A, /* a */ + .common.pCurveParam2 = (uint8_t *) &pEd25519_D, /* d */ + .common.pGx = (uint8_t *) &pEd25519_PointGX, + .common.pGy = (uint8_t *) &pEd25519_PointGY, + .common.pPrecPoints = (uint8_t *) &pEd25519_PrecPoints, + .common.pLadderConst = (uint8_t *) &pEd25519_LADDER_CONST, + .common.pSecFixScalarMultFctFP = &mcuxClEcc_TwEd_PlainFixScalarMult25519_FP, + .common.pSecVarScalarMultFctFP = &mcuxClEcc_TwEd_PlainVarScalarMult_FP, + .common.pPlainFixScalarMultFctFP = &mcuxClEcc_TwEd_PlainFixScalarMult25519_FP, + .common.pPlainVarScalarMultFctFP = &mcuxClEcc_TwEd_PlainVarScalarMult_FP, + .b = 256u, + .c = 3u, + .t = 254u, + .pSqrtMinusOne = (uint8_t *) &pEd25519_SQRT_MINUS_ONE, + .algoSecHash = &mcuxClHash_AlgorithmDescriptor_Sha512, + .algoHash = &mcuxClHash_AlgorithmDescriptor_Sha512, + .pDecodePointFct = mcuxClEcc_EdDSA_DecodePoint_Ed25519, + .pDecodePoint_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_DecodePoint_Ed25519), + .pDomPrefix = pEd25519_dom2Prefix, + .domPrefixLen = MCUXCLECC_EDDSA_ED25519_DOMPREFIXLEN +}; + +const mcuxClEcc_EdDSA_DomainParams_t mcuxClEcc_EdDSA_DomainParams_Ed448 __attribute__((section(".rodata.curve.mcuxClEcc_EdDSA_Ed448"))) = +{ + .common.byteLenP = MCUXCLECC_EDDSA_ED448_SIZE_PRIMEP, + .common.byteLenN = MCUXCLECC_EDDSA_ED448_SIZE_BASEPOINTORDER, + .common.pFullModulusP = (uint8_t *) &pEd448_FullP, + .common.pFullModulusN = (uint8_t *) &pEd448_FullN, + .common.pR2P = (uint8_t *) &pEd448_R2P, + .common.pR2N = (uint8_t *) &pEd448_R2N, + .common.pCurveParam1 = (uint8_t *) &pEd448_A, /* a */ + .common.pCurveParam2 = (uint8_t *) &pEd448_D, /* d */ + .common.pGx = (uint8_t *) &pEd448_PointGX, + .common.pGy = (uint8_t *) &pEd448_PointGY, + .common.pPrecPoints = (uint8_t *) &pEd448_PrecPoints, + .common.pLadderConst = (uint8_t *) &pEd448_LADDER_CONST, + .common.pSecFixScalarMultFctFP = NULL, + .common.pSecVarScalarMultFctFP = NULL, + .common.pPlainFixScalarMultFctFP = NULL, + .common.pPlainVarScalarMultFctFP = NULL, + .b = 456u, + .c = 2u, + .t = 447u, + .pSqrtMinusOne = NULL, + .algoSecHash = NULL, + .algoHash = NULL, + .pDecodePointFct = NULL, + .pDecodePoint_FP_FuncId = 0u, + .pDomPrefix = pEd448_dom4Prefix, + .domPrefixLen = MCUXCLECC_EDDSA_ED448_DOMPREFIXLEN +}; + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair.c new file mode 100644 index 000000000..13842afb6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair.c @@ -0,0 +1,322 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateKeyPair.c + * @brief Implementation of EdDSA key pair generation functionality + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK +#define MCUXCLECC_FP_GENKEYPAIR_SECSTRENGTH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) +#else +#define MCUXCLECC_FP_GENKEYPAIR_SECSTRENGTH (0u) +#endif + + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_EdDSA_GenerateKeyPair_Core) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateKeyPair_Core( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey +); +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateKeyPair_Core) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateKeyPair_Core( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateKeyPair_Core); + + /* + * Step 1: Set up the environment + */ + + /* Verify that the key handles are correctly initialized for the EdDSA use case */ + if((MCUXCLKEY_ALGO_ID_ECC_EDDSA != mcuxClKey_getAlgorithm(privKey)) + || (MCUXCLKEY_ALGO_ID_ECC_EDDSA != mcuxClKey_getAlgorithm(pubKey)) + || (mcuxClKey_getTypeInfo(privKey) != mcuxClKey_getTypeInfo(pubKey)) + || (MCUXCLKEY_ALGO_ID_PRIVATE_KEY != mcuxClKey_getKeyUsage(privKey)) + || (MCUXCLKEY_ALGO_ID_PUBLIC_KEY != mcuxClKey_getKeyUsage(pubKey)) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory") + mcuxClEcc_CpuWa_t * const pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + mcuxClEcc_EdDSA_DomainParams_t * const pDomainParams = (mcuxClEcc_EdDSA_DomainParams_t *) (privKey->type.info); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_EdDSA_SetupEnvironment(pSession, + pDomainParams, + ECC_EDDSA_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_EdDSA_GenerateKeyPair_Core); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* private and public key length = M = 32-byte for Ed25519 (b = 256 = 32*8) */ + /* or 57-byte for Ed448 (b = 456 = 57*8). */ + const uint32_t keyLength = (uint32_t) pDomainParams->b / 8u; + uint8_t * pPrivKey = NULL; + + + /* + * Step 2: Determine whether the private key is passed to the function or needs to be generated. In the latter case, generate the private key d. + */ + uint32_t options = mode->options; + uint8_t *pPrivData = privKey->container.pData; + MCUX_CSSL_FP_BRANCH_DECL(privKeyOption); + if (MCUXCLECC_EDDSA_PRIVKEY_GENERATE == options) + { + /* Derive the security strength required for the RNG from (keyLength * 8) / 2 and check whether it can be provided. */ +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK + MCUX_CSSL_FP_FUNCTION_CALL(ret_checkSecurityStrength, mcuxClRandom_checkSecurityStrength(pSession, (keyLength * 8u) / 2u)); + if (MCUXCLRANDOM_STATUS_OK != ret_checkSecurityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_RNG_ERROR); + } +#endif + /* Reserve space on CPU workarea for the private key. */ + const uint32_t privKeyWords = MCUXCLECC_ALIGNED_SIZE(keyLength) / (sizeof(uint32_t)); + pPrivKey = (uint8_t *) mcuxClSession_allocateWords_cpuWa(pSession, privKeyWords); + pCpuWorkarea->wordNumCpuWa += privKeyWords; + + MCUX_CSSL_FP_FUNCTION_CALL(retRandom, mcuxClRandom_generate(pSession, pPrivKey, keyLength) ); + + if (MCUXCLRANDOM_STATUS_OK != retRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUX_CSSL_FP_BRANCH_POSITIVE(privKeyOption, + MCUXCLECC_FP_GENKEYPAIR_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) ); + } + else if (MCUXCLECC_EDDSA_PRIVKEY_INPUT == options) + { + pPrivKey = mode->pPrivKeyInput; + if(NULL == pPrivKey) + { + /* Invalid mode passed */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_BRANCH_NEGATIVE(privKeyOption); + } + else + { + /* invalid option */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* + * Step 3: Hash the private key using the hash function specified in the EdDSA domain parameters and store + * the hash result (h_0,...,h_{2b-1}) in buffers ECC_T2 and ECC_S3 with offset such that the second half + * (h_b,...,h_{2b-1}) is stored at the beginning of ECC_S3. + */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pS3 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S3]); + uint8_t *pPrivKeyHashPkc = pS3 - keyLength; + + /* Calculate 2b-bit hash of private key. */ + MCUXCLECC_FP_EDDSA_KEYGEN_HASH_PRIVKEY(pSession, + pDomainParams->algoHash, + pPrivKey, pPrivKeyHashPkc, + keyLength); + + + /* + * Step 4: Derive the secret scalar s from the first half (h_b,..,h_{2b-1}) of the private key hash and store it in buffer ECC_S2. + */ + + /* The bits 0~(b-1) of private key hash is placed before and adjacent to PKC operand S3. */ + const uint32_t b = pDomainParams->b; /* = 256 (Ed25519); 456 (Ed448) */ + const uint32_t c = pDomainParams->c; /* = 3 (Ed25519); 2 (Ed448) */ + const uint32_t t = pDomainParams->t; /* = 254 (Ed25519); 447 (Ed448) */ + const uint32_t offsetS3 = (uint32_t) pOperands[ECC_S3]; + /* V0 = PKC operand containing the first half of private key hash. */ + /* V1 = V0 for Ed25519 (64/128-bit PkcWord) and Ed448 (128-bit PkcWord); */ + /* = V0 + 64-bit for Ed448 (64-bit PkcWord). */ + /* ps, PKC will ignore non-aligned part of offsets. */ + pOperands[ECC_V0] = (uint16_t) (offsetS3 - (b/8u)); + pOperands[ECC_V1] = (uint16_t) (offsetS3 - (t/8u)); + /* V2/V3/V4 are shift/rotate amounts used in FUP program below. */ + /* V2 = 2 (Ed25519); 9 (Ed448). */ + /* V3 = -252 \equiv 4 (Ed25519); */ + /* -446 \equiv 2 (Ed448, 64-bit PkcWord) */ + /* or 66 (Ed448, 128-bit PkcWord). */ + pOperands[ECC_V2] = (uint16_t) (b - t); + pOperands[ECC_V3] = (uint16_t) (c - 1u - t); + pOperands[ECC_V4] = (uint16_t) c; + uint32_t keyLengthPkc = MCUXCLPKC_ROUNDUP_SIZE(keyLength); + MCUXCLPKC_PS2_SETLENGTH(0u, keyLengthPkc); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S, + mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S_LEN); + + + /* + * Step 5: Perform a blinded scalar multiplication Q = s*G and store the resulting point in encoded form Q_enc in buffer ECC_COORD02. + */ + + /* Call the BlindedScalarMult function. + * If the function returns OK, ECC_COORD00 and ECC_COORD01 contain the affine x- and y-coordinates of Q. + * If the function returns NEUTRAL_POINT, ECC_COORD00 and ECC_COORD01 are set to the coordinates of the neutral point (0,1). */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_BlindedScalarMult, mcuxClEcc_BlindedScalarMult(pSession, (mcuxClEcc_CommonDomainParams_t *) &pDomainParams->common) ); + if (MCUXCLECC_STATUS_RNG_ERROR == ret_BlindedScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_RNG_ERROR); + } + else if (MCUXCLECC_STATUS_NEUTRAL_POINT == ret_BlindedScalarMult) + { + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_COORD00, 0u); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_COORD01, 0u); + MCUXCLPKC_FP_CALC_OP1_ADD_CONST(ECC_COORD01, ECC_COORD01, 1u); + } + else if (MCUXCLECC_STATUS_OK != ret_BlindedScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Derive the encoding Q_enc of Q and store it in buffer ECC_COORD02. + * + * NOTE: PS2 lengths are still set to (0u, keyLengthPkc) */ + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_COORD02, 0u); /* Clear keyLengthPkc bytes of buffer ECC_COORD02 */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD02, ECC_COORD01, 0u); /* Copy operandSize < keyLengthPkc bytes of the y-coordinate from ECC_COORD01 to ECC_COORD02 */ + uint8_t *pQX = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD00]); + uint8_t *pQEncLsbXByte = &MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD02])[keyLength - 1u]; + MCUXCLPKC_WAITFORFINISH(); + uint8_t lsbX = (*pQX) & 0x01u; + *pQEncLsbXByte |= (lsbX << 7u); + + + /* + * Step 6: (Securely) copy the key data to the key handles and link the key pair. + */ + // TODO: Is this copy function secure enough? + MCUXCLMEMORY_FP_MEMORY_COPY(pPrivData, pPrivKey, keyLength); + + + /* Securely export the scalar s from PKC buffer ECC_S2. */ + const uint32_t scalarSLength = (t + 7u) >> 3u; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportScalarS, mcuxClPkc_SecureExportLittleEndianFromPkc((uint8_t *) &pPrivData[keyLength], ECC_S2, scalarSLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportScalarS) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Securely export the private key hash (h_b,...,h_{2b-1}) from PKC buffer ECC_S3. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportHash, mcuxClPkc_SecureExportLittleEndianFromPkc((uint8_t *) &pPrivData[keyLength + scalarSLength], ECC_S3, keyLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportHash) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Export the public key to the public key handle. */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pubKey->container.pData, ECC_COORD02, keyLength); + + /* Create link between private and public key handles */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_linkKeyPair, mcuxClKey_linkKeyPair(pSession, privKey, pubKey)); + if (MCUXCLKEY_STATUS_OK != ret_linkKeyPair) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* Clean up and exit */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateKeyPair_Core, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), + /* Step 2 */ + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(privKeyOption, MCUXCLECC_EDDSA_PRIVKEY_GENERATE == options), + MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(privKeyOption, MCUXCLECC_EDDSA_PRIVKEY_INPUT == options), + /* Step 3 */ + MCUXCLECC_FP_CALLED_EDDSA_KEYGEN_HASH_PRIVKEY, + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_BlindedScalarMult), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLECC_STATUS_NEUTRAL_POINT == ret_BlindedScalarMult), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD_CONST), + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + /* Step 6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportLittleEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportLittleEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_linkKeyPair), + /* Step 7 */ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateKeyPair) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateKeyPair( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateKeyPair); + + /* Call core function to calculate EdDSA signature */ + MCUX_CSSL_FP_FUNCTION_CALL(keygen_result, mcuxClEcc_EdDSA_GenerateKeyPair_Core( + /* mcuxClSession_Handle_t pSession: */ pSession, + /* const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode */ mode, + /* mcuxClKey_Handle_t privKey */ privKey, + /* mcuxClKey_Handle_t privKey */ pubKey)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateKeyPair, keygen_result, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateKeyPair_Core)); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c new file mode 100644 index 000000000..2af017648 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c + * @brief FUP programs for EdDSA Key Generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateKeyPair_Prepare_S[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x95u,0x8du,0x40u,0xc9u},{0x40u,0x14u,0x00u,0x04u,0x06u,0x18u},{0x00u,0x1au,0x00u,0x18u,0x02u,0x18u},{0x40u,0x17u,0x00u,0x18u,0x02u,0x04u},{0x00u,0x15u,0x00u,0x05u,0x07u,0x18u},{0x00u,0x14u,0x00u,0x18u,0x08u,0x1cu}}; + + + +/** + * [DESIGN] Ed25519 Ed448 + * PS1 LEN = 256-bit 448-bit (64-bit PkcWord) or 512-bit (128-bit PkcWord) + * PS2 LEN = 256-bit 512-bit + * v2 = 2 9 + * v3 = 4 2 (64-bit PkcWord) or 66 (128-bit PkcWord) + * v4 = 3 2 + * + * V0 = (h0..h255) (?*56,h0..h455) + * 1. L-shift v2 bits: S0 = (0,0,h0..h253) (0,0*8,?*56,h0..h446) + * 2. +1: S0 = (1,0,h0..h253) (1,0*8,?*56,h0..h446) + * 3. R-rotate 1 bit: V0 = (0,h0..h253,1) (0*8,?*56,h0..h446,1) + * V1 = V0 (h0..h446,1) if 64-bit PkcWord; or V0 if 128-bit PkcWord + * 4. R-shift v3 bits: S0 = (h3..h253,1,0*4) (h2..h446,1,0*2) if 64-bit PkcWord; or (h2..h446,1,0*66) if 128-bit PkcWord + * 5. L-shift v4 bits: S2 = (0,0,0,h3..h253,1,0) (0,0,h2..h446,1) if 64-bit PkcWord; or (0,0,h2..h446,1,0*64) if 128-bit PkcWord + */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature.c new file mode 100644 index 000000000..44b239002 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature.c @@ -0,0 +1,375 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateSignature.c + * @brief Implementation of the EdDSA signature generation functionality + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateSignature_Core) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateSignature_Core( +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + uint8_t *pSignature, + uint32_t * const pSignatureSize ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateSignature_Core); + + /* + * Step 1: Set up the environment + */ + + /* Derive the pointer to the public key handle and verify that the key handles are correctly initialized for the EdDSA use case */ + mcuxClKey_Handle_t pubKey = (mcuxClKey_Handle_t) mcuxClKey_getLinkedData(key); + if((MCUXCLKEY_ALGO_ID_ECC_EDDSA != mcuxClKey_getAlgorithm(key)) + || (MCUXCLKEY_ALGO_ID_ECC_EDDSA != mcuxClKey_getAlgorithm(pubKey)) + || (mcuxClKey_getTypeInfo(key) != mcuxClKey_getTypeInfo(pubKey)) + || (MCUXCLKEY_ALGO_ID_PRIVATE_KEY != mcuxClKey_getKeyUsage(key)) + || (MCUXCLKEY_ALGO_ID_PUBLIC_KEY != mcuxClKey_getKeyUsage(pubKey)) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory") + mcuxClEcc_CpuWa_t * const pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + mcuxClEcc_EdDSA_DomainParams_t * const pDomainParams = (mcuxClEcc_EdDSA_DomainParams_t *) mcuxClKey_getTypeInfo(key); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_EdDSA_SetupEnvironment(pSession, + pDomainParams, + ECC_EDDSA_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_EdDSA_GenerateSignature_Core); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* + * Step 2: Derive the hash prefix from the mode parameter and calculate the secret scalar + * + * r = H(prefix || (h_b,...,h_{2b-1}) || m') + * + * using + * - the hash function algoSecHash to hash the blocks containing the secret (h_b,\dots,h_{2b-1}), and + * - the hash function algoHash to hash the remaining part of the hash input + * and store the hash output in buffers ECC_S3 and ECC_T3. + */ + + /* Generate digest m' from m in case phflag is set */ + const uint8_t *pMessage = NULL; + uint32_t messageSize = 0u; + MCUX_CSSL_FP_FUNCTION_CALL(retPreHash, mcuxClEcc_EdDSA_PreHashMessage(pSession, pDomainParams, mode->phflag, pIn, inSize, &pMessage, &messageSize)); + if (MCUXCLECC_STATUS_OK != retPreHash) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Initialize hash context buffer in CPU workarea (used for all secure and non-secure hash operations) */ + uint32_t hashContextSizeInWords = MCUXCLECC_MAX(mcuxClHash_getContextWordSize(pDomainParams->algoHash), mcuxClHash_getContextWordSize(pDomainParams->algoSecHash)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("Return pointer is 32-bit aligned and satisfies the requirement of mcuxClHash_Context_t"); + mcuxClHash_Context_t pCtx = (mcuxClHash_Context_t) mcuxClSession_allocateWords_cpuWa(pSession, hashContextSizeInWords); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + + /* Clear upper bytes of buffer to store H(prefix || (h_b,...,h_{2b-1}) || m') which will later be considered of size (operandSize + bufferSize). */ + mcuxClEcc_CommonDomainParams_t *pCommonDomainParams = (mcuxClEcc_CommonDomainParams_t *) &pDomainParams->common; + const uint32_t byteLenP = (uint32_t) pCommonDomainParams->byteLenP; + const uint32_t operandSize = MCUXCLPKC_ROUNDUP_SIZE(byteLenP); /* Note that n < p for EdDSA */ + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + const uint32_t keyLength = (uint32_t) pDomainParams->b / 8u; + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pS3 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S3]); + const uint32_t bytesToClear = operandSize + bufferSize - (2u * keyLength); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + MCUXCLMEMORY_FP_MEMORY_CLEAR(&pS3[2u * keyLength],bytesToClear); + + /* Calculate 2b-bit hash H(prefix || (h_b,\dots,h_{2b-1}) || m') and store it in the concatenated buffers ECC_S3 and ECC_T3. */ + uint8_t *pPrivData = mcuxClKey_getKeyData(key); + const uint32_t scalarSLength = ((uint32_t) pDomainParams->t + 7u) >> 3u; + MCUXCLECC_FP_EDDSA_SIGN_CALC_SCALAR(pSession, + pCtx, + pDomainParams->algoHash, + pDomainParams->algoSecHash, + mode->pHashPrefix, + mode->hashPrefixLen, + &pPrivData[keyLength + scalarSLength], + keyLength, + pMessage, + messageSize, + pS3); + + + /* + * Step 3: Reduce the scalar r modulo n in a blinded way and store the result in buffer ECC_S2. + */ + + /* Generate a blinding value rndR of byte length (operandSize + bufferSize - 1) in buffer ECC_T0 for an additive blinding of r. + * + * NOTES: + * - Irrespective of the PKC word size, we have byteLen(r) <= operandSize + bufferSize - 1, so one can additively + * blind r with rndR (both considered as operands of size (operandSize + bufferSize)) using a plain addition instead + * of a modular one in order to avoid a carry to the next PKC word. + * - This will also overwrite part of ECC_S1 which lies on top of ECC_T0. */ + + uint8_t *pT0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T0]); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("pT0 is PKC operand address and is aligned to 32 bit boundry") + uint32_t *pT0MSWord = & ((uint32_t *) pT0)[((operandSize + bufferSize) / sizeof(uint32_t)) - 1u]; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() + *pT0MSWord = 0u; /* Clear most significant word of ECC_T0 considered as buffer of byte size (bufferSize + operandSize). */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_ncGenerate_rndR, mcuxClRandom_ncGenerate(pSession, pT0, operandSize + bufferSize - 1u)); + if (MCUXCLRANDOM_STATUS_OK != ret_ncGenerate_rndR) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* Additively blind r with rndR (considered of size (operandSize + bufferSize)) */ + MCUXCLPKC_PS2_SETLENGTH(0u, operandSize + bufferSize); + MCUXCLPKC_FP_CALC_OP2_ADD(ECC_S3, ECC_S3, ECC_T0); /* ECC_S3 = r + rndR */ + + /* Calculate r mod n in a blinded way and store it in ECC_S2. + * + * NOTES: + * - The scalar r is of byte length b/4, i.e. we have, irrespective of the underlying PKC word size + * - for Ed25519: byteLen(r) = 64 = 2*operandSize < operandSize + bufferSize + * - for Ed448: byteLen(r) = 114 < operandSize + bufferSize. + * Thus, in both cases, we can obtain r mod n by a Montgomery multiplication of r (considered as operand of size + * (operandSize + bufferSize)) with Q' = 2 ^ (8*(operandSize + bufferSize)) mod n. */ + const uint8_t * pT1 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T1]); + MCUXCLPKC_WAITFORREADY(); + pOperands[ECC_V0] = MCUXCLPKC_PTR2OFFSET(&pT1[MCUXCLPKC_WORDSIZE]); + MCUXCLPKC_PS2_SETLENGTH(operandSize + bufferSize, operandSize); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN, + mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN_LEN); + + + /* + * Step 4: Perform a blinded scalar multiplication R = (r mod n)*G and store the resulting point in encoded form R^enc in buffer ECC_COORD02. + */ + + /* Call the BlindedScalarMult function. + * If the function returns OK, ECC_COORD00 and ECC_COORD01 contain the affine x- and y-coordinates of R. + * If the function returns NEUTRAL_POINT, ECC_COORD00 and ECC_COORD01 are set to the coordinates of the neutral point (0,1). */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_BlindedScalarMult, mcuxClEcc_BlindedScalarMult(pSession, pCommonDomainParams) ); + if (MCUXCLECC_STATUS_RNG_ERROR == ret_BlindedScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_RNG_ERROR); + } + else if (MCUXCLECC_STATUS_NEUTRAL_POINT == ret_BlindedScalarMult) + { + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_COORD00, 0u); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_COORD01, 0u); + MCUXCLPKC_FP_CALC_OP1_ADD_CONST(ECC_COORD01, ECC_COORD01, 1u); + } + else if (MCUXCLECC_STATUS_OK != ret_BlindedScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Derive the encoding R_enc of R and store it in buffer ECC_COORD02. + * + * NOTE: PS2 lengths are still set to (0u, keyLengthPkc) */ + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_COORD02, 0u); /* Clear keyLengthPkc bytes of buffer ECC_COORD02 */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD02, ECC_COORD01, 0u); /* Copy operandSize < keyLengthPkc bytes of the y-coordinate from ECC_COORD01 to ECC_COORD02 */ + const uint8_t *pRX = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD00]); + uint8_t *pREncLsbXByte = &MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD02])[keyLength - 1u]; + MCUXCLPKC_WAITFORFINISH(); + uint8_t lsbX = (*pRX) & 0x01u; + *pREncLsbXByte |= (lsbX << 7u); + + /* + * Step 5: Calculate H(prefix || R^{enc} || Q^{enc} || m') mod n using the hash function algoHash specified in the EdDSA domain parameters + * and store it in buffer ECC_S0 + */ + + /* Derive the pointer to the public key data */ + const uint8_t *pPubData = mcuxClKey_getKeyData(pubKey); + + /* Calculate H(prefix || R^{enc} || Q^{enc} || m') mod n */ + const uint8_t *pSignatureR = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD02]); + MCUX_CSSL_FP_FUNCTION_CALL(ret_CalcHashModN, mcuxClEcc_EdDSA_CalcHashModN(pSession, + pCtx, + pDomainParams, + mode->pHashPrefix, + mode->hashPrefixLen, + pSignatureR, + pPubData, + pMessage, + messageSize)); + if (MCUXCLECC_STATUS_OK != ret_CalcHashModN) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Free the hash context (it's not needed anymore) */ + mcuxClSession_freeWords_cpuWa(pSession, hashContextSizeInWords); + + /* + * Step 6: Securely import the secret scalar s and securely calculate signature component + * + * S = r + H(prefix || R^{enc} || Q^{enc} || m') * s mod n. + */ + + /* Clear buffers ECC_S1 and ECC_S3 considered of size 2*operandSize to prepare them for the blinded calculations below. + * + * NOTE: The clearing ECC_S1 and ECC_S3 will also clear parts of ECC_T1 and ECC_T3. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(0u, 2u * operandSize); + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_S1, 0u); + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_S3, 0u); + + /* Generate an additive blinding rndS in ECC_S1 for blinding the secret scalar s (and r implicitly) of byte size 2*operandSize - 1. + * + * NOTE: In the following, we will consider s and rndS as values of byte length 2*operandSize as this allows to + * use a plain addition for the additive blinding and makes it easier to compensate for Montgomery factors added by Montgomery multiplication. */ + uint8_t *pS1 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S1]); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(ret_ncGenerate_rndS, mcuxClRandom_ncGenerate(pSession, pS1, (2u * operandSize) - 1u)); + if (MCUXCLRANDOM_STATUS_OK != ret_ncGenerate_rndS) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* Securely import the secret scalar s to ECC_S3. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImportScalarS, mcuxClPkc_SecureImportLittleEndianToPkc(ECC_S3, &pPrivData[keyLength], scalarSLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecImportScalarS) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Calculate S = r + H(prefix || R^{enc} || Q^{enc} || m') * s mod n in a blinded way. */ + MCUXCLPKC_FP_CALC_OP2_ADD(ECC_S3, ECC_S1, ECC_S3); /* ECC_S3 = s + rndS */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(2u * operandSize, operandSize); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S, + mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S_LEN); + + + /* + * Step 7: Copy + * - the signature component R^{enc} to the beginning of buffer pSignature + * - the signature component S on behind R^{enc} in the pSignature buffer + * + * NOTE: No need to wait for the PKC here, as this will be done in the export functions. */ + uint32_t halfSignatureSize = keyLength; + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pSignature, ECC_COORD02, halfSignatureSize); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(&pSignature[halfSignatureSize], ECC_T0, halfSignatureSize); + + + /* + * Step 8: Set the size *pSignatureSize to the size of the generated signature. + */ + *pSignatureSize = 2u * halfSignatureSize; + + + /* Clean up and exit */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateSignature_Core, MCUXCLECC_STATUS_OK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), + /* Step 2 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_PreHashMessage), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLECC_FP_CALLED_EDDSA_SIGN_CALC_SCALAR, + /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP2_ADD, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_BlindedScalarMult), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLECC_STATUS_NEUTRAL_POINT == ret_BlindedScalarMult), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST * 2u, + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD_CONST), + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_CalcHashModN), + /* Step 6 */ + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST * 2u, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP2_ADD, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + /* Step 7 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc) * 2u, + /* Step 8 */ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateSignature) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateSignature( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + uint8_t *pSignature, + uint32_t * const pSignatureSize ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateSignature); + + /* Call core function to calculate EdDSA signature */ + MCUX_CSSL_FP_FUNCTION_CALL(sign_result, mcuxClEcc_EdDSA_GenerateSignature_Core( + /* mcuxClSession_Handle_t pSession: */ pSession, + /* mcuxClKey_Handle_t key */ key, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ mode, + /* const uint8_t *pIn */ pIn, + /* uint32_t inSize */ inSize, + /* uint8_t *pSignature */ pSignature, + /* uint32_t * const pSignatureSize */ pSignatureSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateSignature, sign_result, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateSignature_Core)); +} + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignatureMode.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignatureMode.c new file mode 100644 index 000000000..2e70bfa7e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignatureMode.c @@ -0,0 +1,62 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateSignatureMode.c + * @brief implementation of signature modes + */ + +#include +#include +#include +#include +#include + +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateProtocolDescriptor) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateProtocolDescriptor( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *pProtocolDescriptor, + uint32_t phflag, + mcuxCl_InputBuffer_t pContext, + uint32_t contextLen) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateProtocolDescriptor); + + (void) pSession; + + /* Create pHashPrefix buffer after the protocol descriptor. */ + /* It is assumed that sufficient space was allocated by users, with the macro MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX() */ + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxCl_Buffer_t pHashPrefix = (mcuxCl_Buffer_t) ((uint8_t*)pProtocolDescriptor + sizeof(mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + /* Generate the hash prefix */ + MCUX_CSSL_FP_FUNCTION_CALL(retVal_GenHashPrefix, mcuxClEcc_EdDSA_GenerateHashPrefix(pDomainParams, phflag, pContext, contextLen, pHashPrefix)); + if (MCUXCLECC_STATUS_OK != retVal_GenHashPrefix) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateHashPrefix, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + pProtocolDescriptor->generateOption = 0u; + pProtocolDescriptor->verifyOption = 0u; + pProtocolDescriptor->phflag = phflag; + pProtocolDescriptor->pHashPrefix = (const uint8_t*)pHashPrefix; + pProtocolDescriptor->hashPrefixLen = MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_GenerateProtocolDescriptor, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_GenerateHashPrefix) ); +} + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature_FUP.c new file mode 100644 index 000000000..542a8bb5b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_GenerateSignature_FUP.c @@ -0,0 +1,51 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateKeyPair_FUP.c + * @brief FUP programs for EdDSA Signature Generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_Compute_S[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xd9u,0x44u,0xc0u,0xc6u},{0xc0u,0x00u,0x1eu,0x17u,0x01u,0x1du},{0xc0u,0x00u,0x1au,0x17u,0x01u,0x1fu},{0x80u,0x00u,0x18u,0x17u,0x01u,0x1bu},{0x80u,0x2au,0x01u,0x1bu,0x01u,0x1bu},{0x80u,0x00u,0x1bu,0x1du,0x01u,0x19u},{0x80u,0x21u,0x01u,0x19u,0x1cu,0x19u},{0x80u,0x00u,0x1bu,0x1fu,0x01u,0x1du},{0x80u,0x2au,0x01u,0x19u,0x1du,0x19u},{0x81u,0x2au,0x01u,0x19u,0x01u,0x19u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_GenerateSignature_ReduceScalarModN[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x12u,0x9fu,0xbfu,0x50u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x1bu},{0x00u,0x1au,0x00u,0x04u,0x02u,0x04u},{0x80u,0x00u,0x1bu,0x17u,0x01u,0x1du},{0x80u,0x00u,0x1du,0x17u,0x01u,0x1bu},{0x80u,0x2au,0x01u,0x1bu,0x01u,0x1bu},{0xc0u,0x00u,0x1eu,0x1bu,0x01u,0x1du},{0xc0u,0x00u,0x19u,0x1bu,0x01u,0x1fu},{0x80u,0x2au,0x01u,0x1du,0x01u,0x1du},{0x80u,0x2au,0x01u,0x1du,0x1fu,0x1cu}}; + + + + +/** + * FUP program to securely reduce the secret scalar r modulo n + * + * Prerequisites: + * - ECC_V0 points to the second PKC word of ECC_T1 + * - ECC_S3 contains the blinded secret scalar (r + rndR) (of size (operandSize + bufferSize) + * - ECC_T0 contains the blinding rndR (of size (operandSize + bufferSize) + * - PS2 lengths set to (operandSize + bufferSize, operandSize) + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/** + * FUP program to securely compute the EdDSA signature value S + * + * Prerequisites: + * - ECC_S3 contains the blinding s + rndS of the secret scalar s (considered as of size 2*operandSize) + * - ECC_S1 contains the blinding rndS (considered as of size 2*operandSize) with MSByte set to 0 + * - ECC_S0 contains H := H(prefix || R^{enc} || Q^{enc} || m') mod n + * - ECC_S2 contains the secret scalar r + * - PS2 lengths set to (2u * operandSize, operandSize) + */ +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_InitPrivKeyInputMode.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_InitPrivKeyInputMode.c new file mode 100644 index 000000000..c5cba2962 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_InitPrivKeyInputMode.c @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_GenerateKeyPair.c + * @brief implementation of TwEd_EdDsaKeyGen function + */ + + +#include + +#include +#include +#include +#include + +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_InitPrivKeyInputMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_InitPrivKeyInputMode( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t *mode, + const uint8_t *pPrivKey + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_InitPrivKeyInputMode); + + (void) pSession; + mode->options = MCUXCLECC_EDDSA_PRIVKEY_INPUT; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") + mode->pPrivKeyInput = (uint8_t *)pPrivKey; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_InitPrivKeyInputMode, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN.c new file mode 100644 index 000000000..bbfc664df --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN.c @@ -0,0 +1,123 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_CalcHashModN.c + * @brief Function to calculate the hash H(prefix||Renc||Qenc||m') mod n + */ + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/** + * This function calculates the hash H(prefix||Renc||Qenc||m') mod n using the hash function algoHash + * specified in the EdDSA domain parameters. + * + * Input: + * - pSession Handle for the current CL session + * - pCtx Pointer to hash context + * - pDomainParams Pointer to ECC common domain parameters structure + * - pHashPrefix Pointer to prefix + * - hashPrefixLen Byte length of prefix + * - pSignatureR Pointer to Renc + * - pPubKey Pointer to Qenc + * - pIn Pointer to input for hash algorithm + * - inSize Size of pIn + * + * Prerequisites: + * - ps1Len = (operandSize, operandSize) + * - Buffer ECC_NFULL contains n'||n + * - Buffer ECC_N contains n + * + * Result: + * - The result H(prefix||Renc||Qenc||m') mod n is stored in buffer ECC_S0 in NR + * + * Return values: + * - MCUXCLECC_STATUS_OK if the function executed successfully + * - MCUXCLECC_STATUS_FAULT_ATTACK if the hashing failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_CalcHashModN) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_CalcHashModN( + mcuxClSession_Handle_t pSession, + mcuxClHash_Context_t pCtx, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pHashPrefix, + uint32_t hashPrefixLen, + const uint8_t *pSignatureR, + const uint8_t *pPubKey, + const uint8_t *pIn, + uint32_t inSize +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_CalcHashModN); + + /* Step 1: Calculate the hash value H(prefix||Renc||Qenc||m') and store it in the consecutive buffers ECC_S0 and ECC_T0. */ + /* Encoded length = M = 32-byte for Ed25519 (b = 256 = 32*8) */ + /* or 57-byte for Ed448 (b = 456 = 57*8). */ + const uint32_t encodedLen = (uint32_t) pDomainParams->b / 8u; + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pS0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S0]); + + /* Clear T0 with 0's, so ECC_S0 and ECC_T0 will only contain h and thereafter modular reduction can be done */ + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(0u, bufferSize); + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_T0, 0u); + + /* Calculate 2b-bit hash of (prefix||Renc||Qenc||m'). */ + MCUXCLECC_FP_EDDSA_SIGN_VERIFY_CALC_HASH(pSession, + pCtx, + pDomainParams->algoHash, + pHashPrefix, hashPrefixLen, + pSignatureR, encodedLen, + pPubKey, encodedLen, + pIn, inSize, + pS0); + + /* Step 2: Use the PKC to calculate H(prefix||Renc||Qenc||m') mod n, and store the result in ECC_S0. */ + /* Calculate the Montgomery parameter Q' = 2 ^ (8*(operandSize + bufferSize)) mod n and store it in ECC_T1 + * + * NOTE: The scalar r is of byte length b/4, i.e. we have, irrespective of the underlying PKC word size + * - for Ed25519: byteLen(h) = 64 = 2*operandSize < operandSize + bufferSize + * - for Ed448: byteLen(h) = 114 < operandSize + bufferSize. + * Thus, we can obtain h mod n by a multiplication of h (considered as operand of size + * (operandSize + bufferSize)) with Q' modulo n + * Which is: + * MM(H(..), 2^(8*(operandSize(H(..)))), n) = H(..) * 2^(8*(operandSize(H(..)))) * 2^(-8*(operandSize(H(..)))) mod n + * = H(..) mod n + * with: operandSize(H(..)) = operandSize + bufferSize = operandSize + operandSize + PKC_WORDSIZE */ + const uint8_t *pT1 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T1]); + MCUXCLPKC_WAITFORREADY(); + pOperands[ECC_V0] = MCUXCLPKC_PTR2OFFSET(&pT1[MCUXCLPKC_WORDSIZE]); + MCUXCLPKC_PS2_SETLENGTH(operandSize + bufferSize, operandSize); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN, + mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN_LEN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_CalcHashModN, MCUXCLECC_STATUS_OK, + /* Step 1 */ + MCUXCLECC_FP_CALLED_EDDSA_SIGN_VERIFY_CALC_HASH, + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, + /* Step 2 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.c new file mode 100644 index 000000000..79db323ad --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.c @@ -0,0 +1,38 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.c + * @brief FUP programs for EdDSA Signature Verification + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_CalcHashModN_ModN[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xc6u,0xb7u,0x95u,0x24u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x1bu},{0x00u,0x1au,0x00u,0x04u,0x02u,0x04u},{0x80u,0x00u,0x1bu,0x17u,0x01u,0x1du},{0xc0u,0x00u,0x18u,0x1du,0x01u,0x1bu},{0x80u,0x00u,0x1bu,0x17u,0x01u,0x1du},{0x80u,0x2au,0x01u,0x1du,0x01u,0x18u}}; + + + +/** + * FUP program to compute Hash mod N + * + * Prerequisites: + * - ECC_V0 points to the second PKC word of ECC_T1 + * - ECC_S0 contains the hash h (of size (operandSize + bufferSize)) + * - PS2 lengths set to (operandSize + bufferSize, operandSize) + * + * Result: + * - ECC_S0 contains Hash mod N in NR + */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.c new file mode 100644 index 000000000..70fe04941 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.c @@ -0,0 +1,205 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.c + * @brief Function to decode a point + */ + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + * This function decodes an encoded point Penc on Ed25519 and converts it to homogeneous coordinates + * (x:y:1) in MR. It also verifies that the resulting point lies on the curve Ed25519. + * + * Input: + * - pDomainParams Pointer to ECC common domain parameters for Ed25519 + * - pEncPoint Pointer to encoded point + * + * Prerequisites: + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_CP0 and ECC_CP1 contain the curve parameters a and d in MR + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - Buffers ECC_COORD00, ECC_COORD01, ECC_COORD02 contain the homogeneous coordinates (x:y:1) in MR + * + * Return values: + * - MCUXCLECC_STATUS_OK if the function executed successfully + * - MCUXCLECC_STATUS_INVALID_PARAMS if the input point is invalid, i.e. the decoing failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_DecodePoint_Ed25519, mcuxClEcc_EdDSA_DecodePointFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_DecodePoint_Ed25519( + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pEncPoint +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_DecodePoint_Ed25519); + + /* Step 1: Copy the encoded point to buffer ECC_T0. */ + const uint32_t encodedLen = (uint32_t) pDomainParams->b / 8u; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pEncPoint, encodedLen); + + /* Step 2: Read and backup the LSBit x0 from buffer ECC_T0 and clear it in buffer ECC_T0. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pT0LastByte = &MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T0])[encodedLen - 1u]; + uint8_t x0 = (*pT0LastByte) >> 7u; + *pT0LastByte &= 0x7Fu; + + /* Step 3: Compute ECC_T0 - ECC_P. If the CARRY flag is not set, the decoding failed + and #MCUXCLECC_STATUS_INVALID_PARAMS is returned. */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed25519, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP); /* Step 3 */ + } + + /* Step 4: Import pDomainParams->pSqrtMinusOne to buffer ECC_COORD04. */ + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_COORD04, pDomainParams->pSqrtMinusOne, pDomainParams->common.byteLenP); + + /* Step 5: Set u = y^2-1 and v = d*y^2 + 1 and perform the following steps to compute the x-coordinate candidate x': + * - Set x~ = u*v^3 * (u*v^7)^((p-5)/8) mod p + * - If v * x~^2 = -u mod p, set x' = x~ * 2^((p-1)/4) mod p. + * - If v * x~^2 = u mod p, set x' = x~. + * - If v * x~^2 != +/- u mod p, the decoding failed. */ + + /* Compute (u * v^7)^((p-5)/8) mod p and the Y-, and Z-coordinate for the point decoding result (X:Y:Z) */ + uint8_t *pC3 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD03]); + pOperands[ECC_V0] = (uint16_t) 3u; + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common_LEN); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519_LEN); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("pC3 is 32-bit aligned.") + MCUXCLPKC_FP_SWITCHENDIANNESS((uint32_t*)pC3, pDomainParams->common.byteLenP); // the exponent should be in big endian format for MCUXCLMATH_FP_MODEXP_SQRMULTL2R + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pC3, (uint32_t) pDomainParams->common.byteLenP, ECC_COORD00, ECC_T3, ECC_P, TWED_PP_Y0); // ECC_COORD00 = (u * v^7)^((p-5)/8) mod p; use TWED_PP_Y0 as temp buffer + + /* Compute the x~ candidate, x~^2 * v + u, and the square root of -1 mod p */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519_LEN); + uint32_t zeroFlag_check1 = MCUXCLPKC_WAITFORFINISH_GETZERO(); // If flag is set, x~^2 * v = -u mod p + + /* Calculate value x' */ + MCUX_CSSL_FP_BRANCH_DECL(vx2IsMinusU); + if (MCUXCLPKC_FLAG_ZERO == zeroFlag_check1) + { + /* If x~^2 * v == -u, set x' = x~ * 2^((p-1)/4) */ + MCUXCLPKC_FP_CALC_MC1_MM(ECC_COORD00, ECC_T3, ECC_T1, ECC_P); // = x~ * 2^((p-1)/4) = x' in MR + MCUXCLPKC_FP_CALC_MC1_MS(ECC_COORD00, ECC_COORD00, ECC_P, ECC_P); + MCUXCLPKC_FP_CALC_MC1_MS(ECC_COORD00, ECC_COORD00, ECC_P, ECC_P); // x' in MR in range [0,p-1] because 2^256-1 < 3*p + + MCUX_CSSL_FP_BRANCH_POSITIVE(vx2IsMinusU, MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS); + } + else + { + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T2, ECC_T2, ECC_T0, ECC_P); // = x~^2 * v + u - u in MR + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T2, ECC_T2, ECC_T0, ECC_P); // = x~^2 * v - u in MR in range [0,p-1] + if (MCUXCLPKC_FLAG_ZERO != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + /* If x~^2 * v != +/- u, decoding fails */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed25519, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS); + } + /* Set x' = x~ */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_COORD00, ECC_T3, ECC_P, ECC_P); + MCUXCLPKC_FP_CALC_MC1_MS(ECC_COORD00, ECC_COORD00, ECC_P, ECC_P); // x' in MR in range [0,p-1] because 2^256-1 < 3*p + + MCUX_CSSL_FP_BRANCH_NEGATIVE(vx2IsMinusU, MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS); + } + /* After this, we have x' in ECC_COORD00 in MR in range [0,p-1], y in MR in ECC_COORD01, 1 in MR in ECC_COORD02, and PKC_ZERO is set if and only if x' = 0 */ + + /* Step 6: If the ZERO flag of the PKC is set and x0=1, return #MCUXCLECC_STATUS_INVALID_PARAMS, decoding failed. */ + if ((MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) && (1u == x0)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed25519, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(vx2IsMinusU, MCUXCLPKC_FLAG_ZERO == zeroFlag_check1), + MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(vx2IsMinusU, MCUXCLPKC_FLAG_ZERO != zeroFlag_check1) ); + } + + /* Step 7: If x0!=x' mod 2, set ECC_COORD00 = ECC_P - ECC_COORD00. Finally ECC_COORD00 contains x in MR. */ + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T3, ECC_COORD00, ECC_P); // x' mod p in NR in range [0,p-1] because ECC_COORD00 is in range [0,p-1] + + uint32_t *pT3FirstWord = MCUXCLPKC_OFFSET2PTRWORD(pOperands[ECC_T3]); // Loading a word is usually cheaper than loading a byte + MCUXCLPKC_WAITFORFINISH(); + uint8_t x0_candidate = (uint8_t)(*pT3FirstWord) & 0x01u; // LSBit of x~ + + /* Check if x0 != x' mod 2 */ + MCUX_CSSL_FP_BRANCH_DECL(x0Isx); + if (x0 != x0_candidate) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_COORD00, ECC_P, ECC_COORD00); + + MCUX_CSSL_FP_BRANCH_POSITIVE(x0Isx, MCUXCLPKC_FP_CALLED_CALC_OP1_SUB); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed25519, MCUXCLECC_STATUS_OK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(vx2IsMinusU, MCUXCLPKC_FLAG_ZERO == zeroFlag_check1), + MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(vx2IsMinusU, MCUXCLPKC_FLAG_ZERO != zeroFlag_check1), + /* Step 7 */ + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(x0Isx, x0 != x0_candidate) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.c new file mode 100644 index 000000000..331edbd59 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.c @@ -0,0 +1,180 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.c + * @brief Function to decode a point + */ + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + * This function decodes an encoded point Penc on Ed448 and converts it to homogeneous coordinates + * (x:y:1) in MR. It also verifies that the resulting point lies on the curve Ed448. + * + * Input: + * - pDomainParams Pointer to ECC common domain parameters for Ed448 + * - pEncPoint Pointer to encoded point + * + * Prerequisites: + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_CP0 and ECC_CP1 contain the curve parameters a and d in MR + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - Buffers ECC_COORD00, ECC_COORD01, ECC_COORD02 contain the homogeneous coordinates (x:y:1) in MR + * + * Return values: + * - MCUXCLECC_STATUS_OK if the function executed successfully + * - MCUXCLECC_STATUS_INVALID_PARAMS if the input point is invalid, i.e. the decoing failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_DecodePoint_Ed448, mcuxClEcc_EdDSA_DecodePointFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_DecodePoint_Ed448( + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + const uint8_t *pEncPoint +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_DecodePoint_Ed448); + +#if !(MCUXCLPKC_WORDSIZE == 8u) + #error "This implementation only supports 64-bit PKC word" +#endif + + /* Step 1: Copy the encoded point to buffer ECC_T0. */ + const uint32_t encodedLen = (uint32_t) pDomainParams->b / 8u; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pEncPoint, encodedLen); + + /* Step 2: Read and backup the LSBit x0 from buffer ECC_T0 and clear it in buffer ECC_T0. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pT0LastByte = &MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T0])[encodedLen - 1u]; + /* MSByte should be 0x80 or 0x00 */ + uint8_t T0LastByte = *pT0LastByte; + if ((0x80u != T0LastByte) && (0x00u != T0LastByte)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed448, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc)); /* Step 1 */ + } + uint8_t x0 = T0LastByte >> 7u; + *pT0LastByte = 0x00u; + + /* Step 3: Compute ECC_T0 - ECC_P. If the CARRY flag is not set, the decoding failed + and #MCUXCLECC_STATUS_INVALID_PARAMS is returned. */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed448, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP); /* Step 3 */ + } + + /* Step 4: Set u = y^2-1 and v = d*y^2 - 1 and perform the following steps to compute the x-coordinate candidate x': + * - Set x~ = u^3 * v * (u^5*v^3)^((p-3)/4) mod p + * - If v * x~^2 = u mod p, set x' = x~. + * - If v * x~^2 != u mod p, the decoding failed. */ + + /* Compute (u^5*v^3)^((p-3)/4) mod p and the Y-, and Z-coordinate for the point decoding result (X:Y:Z) */ + uint8_t *pC3 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD03]); + pOperands[ECC_V0] = (uint16_t) 2u; + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common_LEN); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448_LEN); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("pC3 is 32-bit aligned.") + MCUXCLPKC_FP_SWITCHENDIANNESS((uint32_t*)pC3, pDomainParams->common.byteLenP); // the exponent should be in big endian format for MCUXCLMATH_FP_MODEXP_SQRMULTL2R + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pC3, (uint32_t) pDomainParams->common.byteLenP, ECC_COORD00, ECC_COORD04, ECC_P, TWED_PP_Y0); // ECC_COORD00 = (u^5 * v^3)^((p-3)/4) mod p; use TWED_PP_Y0 as temp buffer + + /* Compute the x~ candidate, x~^2 * v - u */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448, + mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448_LEN); + uint32_t zeroFlag_check1 = MCUXCLPKC_WAITFORFINISH_GETZERO(); // If flag is set, x~^2 * v = u mod p + + /* If x~^2 * v != u, return #MCUXCLECC_STATUS_INVALID_PARAMS, decoding failed. */ + if (MCUXCLPKC_FLAG_NONZERO == zeroFlag_check1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed448, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + } + + /* Set x' = x~ */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_COORD00, ECC_T3, ECC_P, ECC_P); // x' in MR in range [0,p-1] + /* After this, we have x' in ECC_COORD00 in MR in range [0,p-1], y in MR in ECC_COORD01, 1 in MR in ECC_COORD02, and PKC_ZERO is set if and only if x' = 0 */ + + /* Step 5: If the ZERO flag of the PKC is set and x0=1, return #MCUXCLECC_STATUS_INVALID_PARAMS, decoding failed. */ + if ((MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) && (1u == x0)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed448, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 1 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_MC1_MS); + } + + /* Step 6: If x0!=x' mod 2, set ECC_T3 = ECC_P - ECC_T3. Finally ECC_COORD00 contains x in MR. */ + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T3, ECC_COORD00, ECC_P); // x' mod p in NR in range [0,p-1] because ECC_COORD00 is in range [0,p-1] + + uint32_t *pT3FirstWord = MCUXCLPKC_OFFSET2PTRWORD(pOperands[ECC_T3]); // Loading a word is usually cheaper than loading a byte + MCUXCLPKC_WAITFORFINISH(); + uint8_t x0_candidate = (uint8_t)(*pT3FirstWord) & 0x01u; // LSBit of x~ + + /* Check if x0 != x' mod 2 */ + MCUX_CSSL_FP_BRANCH_DECL(x0Isx); + if (x0 != x0_candidate) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_COORD00, ECC_P, ECC_COORD00); + + MCUX_CSSL_FP_BRANCH_POSITIVE(x0Isx, MCUXCLPKC_FP_CALLED_CALC_OP1_SUB); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_DecodePoint_Ed448, MCUXCLECC_STATUS_OK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + /* Step 6 */ + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(x0Isx, x0 != x0_candidate) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.c new file mode 100644 index 000000000..234393f4d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.c @@ -0,0 +1,123 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.c + * @brief FUP programs for EdDSA Signature Verification + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed25519[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x64u,0x95u,0x0eu,0x43u},{0x80u,0x00u,0x1du,0x20u,0x00u,0x1fu},{0x80u,0x00u,0x1fu,0x1fu,0x00u,0x23u},{0x80u,0x00u,0x23u,0x1bu,0x00u,0x1du},{0x80u,0x21u,0x10u,0x1du,0x19u,0x1du},{0x80u,0x00u,0x24u,0x16u,0x00u,0x1bu},{0x82u,0x2au,0x00u,0x1du,0x00u,0x1du}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_ComputeXCandidate_Ed448[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x39u,0x1bu,0x89u,0xe7u},{0x80u,0x00u,0x1du,0x20u,0x00u,0x1fu},{0x80u,0x00u,0x1fu,0x1fu,0x00u,0x23u},{0x80u,0x00u,0x23u,0x1bu,0x00u,0x1du},{0x80u,0x2au,0x10u,0x1du,0x19u,0x1du},{0x80u,0x2au,0x00u,0x1du,0x00u,0x1du}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Common[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xddu,0x23u,0x11u,0x23u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x22u},{0x80u,0x00u,0x19u,0x16u,0x00u,0x21u},{0x80u,0x00u,0x21u,0x21u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x13u,0x00u,0x1bu},{0x80u,0x2au,0x10u,0x19u,0x22u,0x19u},{0x00u,0x15u,0x00u,0x00u,0x04u,0x23u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed25519[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x2du,0x7au,0x46u,0x16u},{0x80u,0x21u,0x10u,0x1bu,0x22u,0x1bu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x1du},{0x80u,0x00u,0x1du,0x1bu,0x00u,0x1fu},{0x80u,0x00u,0x19u,0x1fu,0x00u,0x1du},{0x80u,0x00u,0x1du,0x1fu,0x00u,0x20u},{0x80u,0x00u,0x20u,0x1bu,0x00u,0x1fu}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_EdDSA_Internal_DecodePoint_PrepareExp_Ed448[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x34u,0xfau,0x14u,0x48u},{0x80u,0x2au,0x10u,0x1bu,0x22u,0x1bu},{0x80u,0x00u,0x19u,0x1bu,0x00u,0x24u},{0x80u,0x00u,0x19u,0x24u,0x00u,0x1fu},{0x80u,0x00u,0x1fu,0x24u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x1fu,0x00u,0x24u},{0x80u,0x00u,0x19u,0x1fu,0x00u,0x1du}}; + + + +/** + * FUP program to compute in Decode Point: Y, Z, u and exp in MR, with + * Y = Y-coordinate for the point decoding result (X:Y:Z) + * Z = Z-coordinate for the point decoding result (X:Y:Z) + * u = y^2 - 1 + * exp = (p-5)/8 for Ed25519 or (p-3)/4 for Ed448 + * + * Prerequisites: + * - ECC_T0 contains Y in NR + * - ECC_V0 contains 3 for Ed25519 or 2 for Ed448 + * - ECC_P contains modulus p in NR + * - ECC_CP1 contains domain parameter d in MR + * + * Result: + * - ECC_T0 contains u in MR + * - ECC_T1 contains d * y^2 in MR + * - ECC_COORD01 contains Y in MR + * - ECC_COORD02 contains Z in MR + * - ECC_COORD03 contains the exp (p-5)/8 for Ed25519 or (p-3)/4 for Ed448 + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/** + * FUP program to compute in Decode Point: exp, v and v^3 in MR, with + * v = d * y^2 + 1 + * + * Prerequisites: + * - ECC_T0 contains u in MR + * - ECC_T1 contains d * y^2 in MR + * - ECC_COORD02 contains 1 in MR + * - ECC_P contains modulus p in NR + * + * Result: + * - ECC_T1 contains v in MR + * - ECC_T3 contains u*v^7 in MR + */ + +/** + * FUP program to compute in Decode Point: x~ and x~^2 * v + u and square root of -1 mod p in MR, with + * x~ = u * v^3 * (u * v^7)^((p-5)/8) mod p = X-coordinate candidate for the point decoding result (X:Y:Z) + * v = d * y^2 + 1 + * u = y^2 - 1 + * + * Prerequisites: + * - ECC_T0 contains u in MR + * - ECC_T1 contains v in MR + * - ECC_T2 contains u * v^3 in MR + * - ECC_COORD00 contains (u * v^7)^((p-5)/8) mod p in NR + * - ECC_COORD04 contains square root of -1 mod p in NR + * - ECC_P contains modulus p in NR + * + * Result: + * - ECC_T1 contains square root of -1 mod p in MR + * - ECC_T2 contains x~^2 * v + u in MR + * - ECC_T3 contains x~ in MR + */ + +/** + * FUP program to compute in Decode Point: exp, v, u^5 * v^3 and u^3 * v in MR, with + * v = d * y^2 - 1 + * u = y^2 - 1 + * + * Prerequisites: + * - ECC_T0 contains u in MR + * - ECC_T1 contains d * y^2 in MR + * - ECC_COORD02 contains 1 in MR + * - ECC_P contains modulus p in NR + * + * Result: + * - ECC_T1 contains v in MR + * - ECC_T2 contains u^3 * v in MR + * - ECC_COORD04 contains u^5 * v^3 in MR + */ + +/** + * FUP program to compute in Decode Point: x~ and x~^2 * v - u in MR, with + * x~ = u^3 * v * (u^5 * v^3)^((p-3)/4) mod p = X-coordinate candidate for the point decoding result (X:Y:Z) + * v = d * y^2 - 1 + * u = y^2 - 1 + * + * Prerequisites: + * - ECC_T0 contains u in MR + * - ECC_T1 contains v in MR + * - ECC_T2 contains u^3 * v in MR + * - ECC_COORD00 contains (u^5 * v^3)^((p-3)/4) mod p in NR + * - ECC_P contains modulus p in NR + * + * Result: + * - ECC_T2 contains x~^2 * v - u in MR + * - ECC_T3 contains x~ in MR + */ +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SetupEnvironment.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SetupEnvironment.c new file mode 100644 index 000000000..2b7aff56a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SetupEnvironment.c @@ -0,0 +1,79 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_SetupEnvironment.c + * @brief EdDSA internal setup environment + */ + + +#include +#include +#include + +#include +#include +#include + + +/** + * This function sets up the general environment used by EdDSA functions. + * In particular, it sets up the utilized co-processors, prepares the PKC workarea layout, + * and initializes it for Montgomery arithmetic modulo p and n. + * + * Input: + * - pSession Handle for the current CL session + * - pCommonDomainParams Pointer to domain parameter struct passed via API + * - noOfBuffers Number of PKC buffers to be allocated + * + * Result: + * - The pointer table has been properly setup in CPU workarea and PKC buffers have been allocated + * - The PKC state has been backed up in CPU workarea and the PKC has been enabled + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_PFULL and ECC_NFULL contain p'||p and n'||n, respectively + * - Buffers ECC_PS and ECC_NS contain the p resp. n shifted to the PKC word boundary + * - Buffers ECC_PQSQR and ECC_NQSQR contain the R^2 values modulo p and n, respectively + * - Virtual pointers ECC_P and ECC_N point to the second PKC word of ECC_PFULL and ECC_NFULL, respectively + * - Virtual pointers ECC_ZERO and ECC_ONE have been initialized with 0 and 1, respecitvely + * - The domain parameters a and d are stored in buffers ECC_CP0 and ECC_CP1 in MR + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint8_t noOfBuffers ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_SetupEnvironment); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_SetupEnvironment(pSession, &(pDomainParams->common), noOfBuffers)); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_EdDSA_SetupEnvironment); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Import curve parameters a and d, convert them to MR modulo p, and store them in buffers ECC_CP0 and ECC_CP1. */ + uint32_t byteLenP = (uint32_t) pDomainParams->common.byteLenP; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pDomainParams->common.pCurveParam1, byteLenP); + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T1, pDomainParams->common.pCurveParam2, byteLenP); + MCUXCLPKC_FP_CALC_MC1_MM(ECC_CP0, ECC_T0, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_CALC_MC1_MM(ECC_CP1, ECC_T1, ECC_PQSQR, ECC_P); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_SetupEnvironment, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUXCLPKC_FP_CALLED_CALC_MC1_MM ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SignatureMechanisms.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SignatureMechanisms.c new file mode 100644 index 000000000..5eae6160a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_Internal_SignatureMechanisms.c @@ -0,0 +1,127 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_Internal_SignatureMechanisms.c + * @brief implementation of functions for signature modes + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_GenerateHashPrefix) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_GenerateHashPrefix( + const mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint32_t phflag, + mcuxCl_InputBuffer_t pContext, + uint32_t contextLen, + mcuxCl_Buffer_t pHashPrefix) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_GenerateHashPrefix); + + uint8_t *pHashPrefixTmp = (uint8_t*) pHashPrefix; + + /* Check whether the pContext is not NULL if the contextLen is set */ + if (((0u < contextLen) && (NULL == pContext)) || (255u < contextLen) || (2u < phflag)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateHashPrefix, MCUXCLECC_STATUS_INVALID_PARAMS); + } + + /* Check whether the pDomPrefix is not NULL if the domPrefixLen is set */ + /* pHashPrefixTmp is not NULL and allocate the buffer pHashPrefix with sufficient size */ + if ((MCUXCLECC_EDDSA_ED25519_DOMPREFIXLEN < pDomainParams->domPrefixLen) || (NULL == pDomainParams->pDomPrefix) + || (NULL == pHashPrefixTmp)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateHashPrefix, MCUXCLECC_STATUS_INVALID_PARAMS); + } + + /* Write the fixed prefix string for dom2/dom4 to the output buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pHashPrefixTmp, + (const uint8_t*)pDomainParams->pDomPrefix, + pDomainParams->domPrefixLen, + MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen)); + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pHashPrefixTmp will be in the valid range pHashPrefix[0 ~ pDomainParams->domPrefixLen+contextLen+1u].") + pHashPrefixTmp += pDomainParams->domPrefixLen; + + /* Write phflag to the output buffer */ + *pHashPrefixTmp = (uint8_t)phflag; + pHashPrefixTmp++; + /* Write contextLen to the output buffer */ + *pHashPrefixTmp = (uint8_t)contextLen; + pHashPrefixTmp++; + /* Write pContext to the output buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pHashPrefixTmp, + pContext, + contextLen, + MCUXCLECC_EDDSA_ED25519_SIZE_HASH_PREFIX(contextLen)); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_GenerateHashPrefix, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) ); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_PreHashMessage) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_PreHashMessage( + mcuxClSession_Handle_t pSession, + mcuxClEcc_EdDSA_DomainParams_t *pDomainParams, + uint32_t phflag, + const uint8_t *pIn, + uint32_t inSize, + const uint8_t **pMessage, + uint32_t *messageSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_PreHashMessage); + + MCUX_CSSL_FP_BRANCH_DECL(phflagSet); + if (MCUXCLECC_EDDSA_PHFLAG_ONE == phflag) + { + /* phflag is set, pre-hash the message */ + uint8_t *pMessageTmp = (uint8_t*) mcuxClSession_allocateWords_cpuWa(pSession, (uint32_t)pDomainParams->b / 4u); + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result, mcuxClHash_compute(pSession, pDomainParams->algoHash, pIn, inSize, pMessageTmp, &hashOutputSize)); + + if (MCUXCLHASH_STATUS_OK != hash_result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_PreHashMessage, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + *pMessage = (const uint8_t *) pMessageTmp; + *messageSize = (uint32_t)pDomainParams->b / 4u; + + MCUX_CSSL_FP_BRANCH_POSITIVE(phflagSet, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) ); + } + else if (MCUXCLECC_EDDSA_PHFLAG_ZERO == phflag) + { + /* phflag is not set, the message is not modified */ + *pMessage = pIn; + *messageSize = inSize; + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_PreHashMessage, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_PreHashMessage, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(phflagSet, MCUXCLECC_EDDSA_PHFLAG_ONE == phflag) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_VerifySignature.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_VerifySignature.c new file mode 100644 index 000000000..45e1b82c6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_EdDSA_VerifySignature.c @@ -0,0 +1,516 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_EdDSA_VerifySignature.c + * @brief Implementation of the EdDSA signature verification functionality + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_VerifySignature_Core) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_VerifySignature_Core( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + const uint8_t *pSignature, + uint32_t signatureSize ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_VerifySignature_Core); + + /* + * Step 1: Set up the environment + */ + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory") + mcuxClEcc_CpuWa_t * const pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(session, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + mcuxClEcc_EdDSA_DomainParams_t * const pDomainParams = (mcuxClEcc_EdDSA_DomainParams_t *) mcuxClKey_getTypeInfo(key); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_EdDSA_SetupEnvironment(session, pDomainParams, ECC_EDDSA_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_EdDSA_VerifySignature_Core); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + const uint32_t encodedLen = (uint32_t) pDomainParams->b / 8u; + const uint32_t sigLength = encodedLen * 2u; + const uint8_t *pSignatureR = pSignature; + const uint8_t *pSignatureS = pSignature + encodedLen; + + /* + * Step 2: Verify that the passed signatureSize value is as expected. + */ + + if (signatureSize != sigLength) + { + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, /* Clean up */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment)); /* Step 1 */ + } + + + /* + * Step 3: Import signature component S to buffer ECC_S0 and check if it is smaller than n. + */ + + /* Import S to ECC_S0 */ + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_S0, pSignatureS, encodedLen); + + /* Check s < n. */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_S0, ECC_N); + if (MCUXCLPKC_FLAG_NOCARRY == MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { /* s >= n. */ + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, /* Clean up */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP); + } + + + /* + * Step 4: Calculate P1 = S * G, and store the result in homogeneous coordinates in MR in buffers + * ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + uint32_t leadingZeroN = 0u; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(ECC_N, &leadingZeroN)); + uint32_t bitLenN = (operandSize * 8u) - leadingZeroN; + + /* Calculate P1 = S * G */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_plainFixScalarMult, + pDomainParams->common.pPlainFixScalarMultFctFP->pScalarMultFct( + session, + (mcuxClEcc_CommonDomainParams_t *)&pDomainParams->common, + ECC_S0, + bitLenN, + 0)); + if(MCUXCLECC_STATUS_OK != ret_plainFixScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* + * Step 5: Back up the coordinates of P1 in buffers ECC_COORD25, ECC_COORD26 and ECC_COORD27. + */ + + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD25, ECC_COORD00, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD26, ECC_COORD01, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD27, ECC_COORD02, 0u); + + + /* + * Step 6: Derive the hash prefix from the mode parameter and calculate H(prefix||Renc||Qenc||m') mod n + * and store it in buffer ECC_S0. + */ + + uint8_t *pPubKey = mcuxClKey_getKeyData(key); + + /* Generate digest m' from m in case phflag is set */ + const uint8_t *m = NULL; + uint32_t mLen = 0u; + MCUX_CSSL_FP_FUNCTION_CALL(retPreHash, mcuxClEcc_EdDSA_PreHashMessage(session, pDomainParams, mode->phflag, pIn, inSize, &m, &mLen)); + if (MCUXCLECC_STATUS_OK != retPreHash) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Initialize hash context */ + uint32_t hashContextSizeInWords = mcuxClHash_getContextWordSize(pDomainParams->algoHash); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("Return pointer is 32-bit aligned and satisfies the requirement of mcuxClHash_Context_t"); + mcuxClHash_Context_t pCtx = (mcuxClHash_Context_t) mcuxClSession_allocateWords_cpuWa(session, hashContextSizeInWords); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CalcHashModN, + mcuxClEcc_EdDSA_CalcHashModN( + session, pCtx, pDomainParams, + mode->pHashPrefix, mode->hashPrefixLen, + pSignatureR, + (const uint8_t*)pPubKey, + m, mLen) ); + if (MCUXCLECC_STATUS_OK != ret_CalcHashModN) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Free the hash context */ + mcuxClSession_freeWords_cpuWa(session, hashContextSizeInWords); + + + /* + * Step 7: Call function pDomainParams->pDecodePointFct to decode the public key Qenc and store + * the homogeneous coordinates of the decoded point Q in buffers ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_decodePoint, + pDomainParams->pDecodePointFct( + pDomainParams, + (const uint8_t*)pPubKey) ); + if(MCUXCLECC_STATUS_INVALID_PARAMS == ret_decodePoint) + { + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, /* Clean up */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), /* Step 4 */ + pDomainParams->common.pPlainFixScalarMultFctFP->scalarMultFct_FP_FuncId, + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_PreHashMessage), /* Step 6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_CalcHashModN), + pDomainParams->pDecodePoint_FP_FuncId); /* Step 7 */ + } + else if(MCUXCLECC_STATUS_OK != ret_decodePoint) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + + /* + * Step 8: Call function pDomainParameters->pPlainVarScalarMultFct to calculate + * P2 = (H(prefix||Renc||Qenc||m') mod n)*Q and store the result in homogeneous coordinates in MR + * in buffers ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_plainVarScalarMult, + pDomainParams->common.pPlainVarScalarMultFctFP->pScalarMultFct( + session, + &pDomainParams->common, + ECC_S0, + bitLenN, + 0)); + if(MCUXCLECC_STATUS_OK != ret_plainVarScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* + * Step 9: Calculate R' = P1-P2 and store the homogeneous coordinates of R' in ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_TwEd_PointSubtraction, + mcuxClEcc_FUP_TwEd_PointSubtraction_LEN); + + + /* + * Step 10: Derive the encoding (R')enc of R' and store it in ECC_COORD03. + */ + MCUXCLPKC_WAITFORREADY(); /* TODO: PS2 length is not used in the above FUP, but this is required due to unknown reason (CLNS-7276) */ + uint32_t encodedLenPkc = MCUXCLPKC_ROUNDUP_SIZE(encodedLen); + MCUXCLPKC_PS2_SETLENGTH(0u, encodedLenPkc); + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_COORD03, 0u); /* Clear encodedLenPkc bytes of buffer ECC_COORD03 */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD03, ECC_COORD01, 0u); /* Copy operandSize < encodedLenPkc bytes of the y-coordinate from ECC_COORD01 to ECC_COORD03 */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t *pRX = MCUXCLPKC_OFFSET2PTRWORD(pOperands[ECC_COORD00]); + uint8_t *pREncLastByte = &MCUXCLPKC_OFFSET2PTR(pOperands[ECC_COORD03])[encodedLen - 1u]; + MCUXCLPKC_WAITFORFINISH(); + uint32_t lsbX = (*pRX) & (uint32_t)0x01u; /* Loading a word is usually cheaper than loading a byte */ + *pREncLastByte |= ((uint8_t)lsbX << 7u); + + /* + * Step 11: Import the signature component Renc and compare it against (R')enc. + */ + + /* Import Renc to ECC_S0 */ + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_S0, pSignature, encodedLen); + + /* Compare ECC_S0 against ECC_COORD03 */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_S0, ECC_COORD03); + + + /* + * Step 12: If (R')enc != Renc, then compare if h*R' and h*R are equal points + */ + + uint32_t zeroFlag_check = MCUXCLPKC_WAITFORFINISH_GETZERO(); + MCUX_CSSL_FP_BRANCH_DECL(RencNotEqual); + if (MCUXCLPKC_FLAG_ZERO != zeroFlag_check) + { + /* + * Step 12a: Call function pDomainParameters->pPlainVarScalarMultFct to calculate h*R' and store the result in + * homogeneous coordinates in MR in buffers ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + + /* Compute h and store it in ECC_S1 */ + const uint8_t h = (uint8_t) (1u << ((uint32_t) pDomainParams->c & 0x1Fu)); /* c = cofactor exponent, i.e. cofactor: h = 2^c */ + uint8_t *pS1 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S1]); + pS1[0] = h; + uint32_t bitLenH = (uint32_t)pDomainParams->c + (uint32_t)1u; + + /* Compute h*R' */ + MCUX_CSSL_FP_FUNCTION_CALL(ret2_plainVarScalarMult, + pDomainParams->common.pPlainVarScalarMultFctFP->pScalarMultFct( + session, + &pDomainParams->common, + ECC_S1, + bitLenH, + 0)); + if(MCUXCLECC_STATUS_OK != ret2_plainVarScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* + * Step 12b: Back up the coordinates of h*R' in buffers ECC_COORD25, ECC_COORD26 and ECC_COORD27. + */ + + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD25, ECC_COORD00, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD26, ECC_COORD01, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_COORD27, ECC_COORD02, 0u); + + + /* + * Step 12c: Call function pDomainParams->pDecodePointFct to decode Renc and store the homogeneous coordinates of + * the decoded point R in buffers ECC_COORD00, ECC_COORD01 and ECC_COORD02. If the decoding fails, return #MCUXCLECC_STATUS_INVALID_SIGNATURE. + */ + + MCUX_CSSL_FP_FUNCTION_CALL(ret2_decodePoint, + pDomainParams->pDecodePointFct( + pDomainParams, + pSignature) ); + if(MCUXCLECC_STATUS_INVALID_PARAMS == ret2_decodePoint) + { + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, /* Clean up */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), /* Step 4 */ + pDomainParams->common.pPlainFixScalarMultFctFP->scalarMultFct_FP_FuncId, + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_PreHashMessage), /* Step 6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_CalcHashModN), + pDomainParams->pDecodePoint_FP_FuncId, /* Step 7 */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, /* Step 8 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 9 */ + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, /* Step 10 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 11 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, /* Step 12a */ + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, /* Step 12b */ + pDomainParams->pDecodePoint_FP_FuncId); /* Step 12c */ + } + else if(MCUXCLECC_STATUS_OK != ret2_decodePoint) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + + /* + * Step 12d: Call function pDomainParameters->pPlainVarScalarMultFct to calculate h*R and store the result in + * homogeneous coordinates in MR in buffers ECC_COORD00, ECC_COORD01 and ECC_COORD02. + */ + + MCUX_CSSL_FP_FUNCTION_CALL(ret3_plainVarScalarMult, + pDomainParams->common.pPlainVarScalarMultFctFP->pScalarMultFct( + session, + &pDomainParams->common, + ECC_S1, + bitLenH, + 0)); + if(MCUXCLECC_STATUS_OK != ret3_plainVarScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* + * Step 12e: Bring h*R' and h*R to the same Z-coordinate and compare the coordinates. + * If the points are not equal, return #MCUXCLECC_STATUS_INVALID_SIGNATURE. + */ + pOperands[ECC_V0] = pOperands[ECC_COORD25]; + pOperands[ECC_V1] = pOperands[ECC_COORD26]; + pOperands[ECC_V2] = pOperands[ECC_COORD27]; + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_PointComparisonHom, + mcuxClEcc_FUP_PointComparisonHom_LEN); + + /* The last result is only zero if and only if R'=R */ + if (MCUXCLPKC_FLAG_ZERO != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, /* Clean up */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 3 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), /* Step 4 */ + pDomainParams->common.pPlainFixScalarMultFctFP->scalarMultFct_FP_FuncId, + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, /* Step 5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_PreHashMessage), /* Step 6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_CalcHashModN), + pDomainParams->pDecodePoint_FP_FuncId, /* Step 7 */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, /* Step 8 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Step 9 */ + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, /* Step 10 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), /* Step 11 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, /* Step 12a */ + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, /* Step 12b */ + pDomainParams->pDecodePoint_FP_FuncId, /* Step 12c */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, /* Step 12d */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); /* Step 12e */ + } + + MCUX_CSSL_FP_BRANCH_POSITIVE(RencNotEqual, + /* Step 12a */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, + /* Step 12b */ + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + /* Step 12c */ + pDomainParams->pDecodePoint_FP_FuncId, + /* Step 12d */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, + /* Step 12e */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + } + + /* + * Step 13: Return #MCUXCLECC_STATUS_OK. + */ + + /* Clean up and exit */ + mcuxClSession_freeWords_pkcWa(session, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(session, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_VerifySignature_Core, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_SetupEnvironment), + /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + pDomainParams->common.pPlainFixScalarMultFctFP->scalarMultFct_FP_FuncId, + /* Step 5 */ + 3u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + /* Step 6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_PreHashMessage), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_CalcHashModN), + /* Step 7 */ + pDomainParams->pDecodePoint_FP_FuncId, + /* Step 8 */ + pDomainParams->common.pPlainVarScalarMultFctFP->scalarMultFct_FP_FuncId, + /* Step 9 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + /* Step 10 */ + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + /* Step 11 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + /* Step 12 */ + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(RencNotEqual, MCUXCLPKC_FLAG_ZERO != zeroFlag_check), + /* Step 13 */ + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_EdDSA_VerifySignature) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_EdDSA_VerifySignature( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode, + const uint8_t *pIn, + uint32_t inSize, + const uint8_t *pSignature, + uint32_t signatureSize ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_EdDSA_VerifySignature); + + /* Call core function to calculate EdDSA signature */ + MCUX_CSSL_FP_FUNCTION_CALL(verify_result, mcuxClEcc_EdDSA_VerifySignature_Core( + /* mcuxClSession_Handle_t session: */ session, + /* mcuxClKey_Handle_t key */ key, + /* const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t *mode */ mode, + /* const uint8_t *pIn */ pIn, + /* uint32_t inSize */ inSize, + /* const uint8_t *pSignature */ pSignature, + /* uint32_t pSignatureSize */ signatureSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_EdDSA_VerifySignature, verify_result, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_EdDSA_VerifySignature_Core)); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_BlindedScalarMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_BlindedScalarMult.c new file mode 100644 index 000000000..85d534d71 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_BlindedScalarMult.c @@ -0,0 +1,162 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_BlindedScalarMult.c + * @brief mcuxClEcc: implementation of mcuxClEcc_BlindedScalarMult + */ + + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + + +/** + * This function implements the scalar multiplication k*G for a secret scalar k in {0,...,n-1} + * and the base point G of order n on the given curve. If the scalar k is zero, the function + * returns MCUXCLECC_STATUS_NEUTRAL_POINT. If it is not zero, the function generates a blinded + * multiplicative splitting of the scalar k and performs two secure scalar multiplications, + * the first with the blinded scalar and the second with the blinding by calling the generic + * function mcuxClEcc_BlindedScalarMult. + * + * Input: + * - pSession Handle for the current CL session + * - pDomainParameters Pointer to common domain parameters + * + * Return values: + * - MCUXCLECC_STATUS_OK if the function executed successfully + * - MCUXCLECC_STATUS_NEUTRAL_POINT if the scalar is zero + * - MCUXCLECC_STATUS_RNG_ERROR random number generation (PRNG) error (unexpected behavior) + * - MCUXCLECC_STATUS_FAULT_ATTACK fault attack (unexpected behavior) is detected + * + * Prerequisites: + * - The secret scalar k is contained in buffer ECC_S2 + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_CP0 and ECC_CP1 contain the curve parameters a and d in MR + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_NFULL contains n'||n + * - Buffers ECC_PS and ECC_NS contain the shifted moduli associated to p and n + * + * Result: + * - If MCUXCLECC_STATUS_OK is returned, the result k*G is stored in curve dependent coordinates in buffers ECC_COORD00, ECC_COORD01,.... + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_BlindedScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_BlindedScalarMult(mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pCommonDomainParams) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_BlindedScalarMult); + + /* + * Step 1: Securely compare k against zero and return MCUXCLECC_STATUS_NEUTRAL_POINT if k is zero. + */ + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_T0, 0u); + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_S2, ECC_T0); + uint32_t zeroFlag = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if (MCUXCLPKC_FLAG_ZERO == zeroFlag) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_NEUTRAL_POINT, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP ); + } + + + /* + * Step 2: Securely generate a multiplicative decomposition (sigma,phi) of k with a 32 bit random phi + * with MSBit and LSBit set to 1 stored in ECC_S0 and sigma = phi^(-1)*k mod n stored in ECC_S1 + * by calling function mcuxClEcc_GenerateMultiplicativeBlinding. + */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_GenMulBlind, + mcuxClEcc_GenerateMultiplicativeBlinding(pSession, ECC_S2)); + if (MCUXCLECC_STATUS_OK != ret_GenMulBlind) + { + /* GenerateMultiplicativeBlinding is returning only OK or RNG_ERROR */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + + /* + * Step 3: Call pDomainParameters->pSecFixScalarMultFct to securely calculate the scalar multiplication sigma*G + * and store the result P' in curve dependent coordinates in MR in buffers ECC_COORD00, ECC_COORD01,.... + */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + uint32_t leadingZeroN; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(ECC_N, &leadingZeroN)); + uint32_t bitLenN = (operandSize * 8u) - leadingZeroN; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_secFixScalarMult, + pCommonDomainParams->pSecFixScalarMultFctFP->pScalarMultFct( + pSession, + pCommonDomainParams, + ECC_S1, + bitLenN, + 0)); + if(MCUXCLECC_STATUS_RNG_ERROR == ret_secFixScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != ret_secFixScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + + /* + * Step 4: Call pDomainParameters->pSecVarScalarMultFct to securely calculate the scalar multiplication phi*P' + * and store the result P in curve dependent coordinates in MR in buffers ECC_COORD00, ECC_COORD01,.... + */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_secVarScalarMult, + pCommonDomainParams->pSecVarScalarMultFctFP->pScalarMultFct( + pSession, + pCommonDomainParams, + ECC_S0, + MCUXCLECC_SCALARBLINDING_BITSIZE, + MCUXCLECC_SCALARMULT_OPTION_AFFINE_OUTPUT)); + if(MCUXCLECC_STATUS_RNG_ERROR == ret_secVarScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != ret_secVarScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_BlindedScalarMult, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_GenerateMultiplicativeBlinding), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + pCommonDomainParams->pSecFixScalarMultFctFP->scalarMultFct_FP_FuncId, + pCommonDomainParams->pSecVarScalarMultFctFP->scalarMultFct_FP_FuncId); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Convert_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Convert_FUP.c new file mode 100644 index 000000000..46978e738 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Convert_FUP.c @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Convert_FUP.c + * @brief mcuxClEcc: FUP programs for generic ECC coordinate conversion + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_ConvertHomToAffine[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x4eu,0xd7u,0xe8u,0x4cu},{0x80u,0x00u,0x19u,0x16u,0x00u,0x1bu},{0x80u,0x2au,0x00u,0x1bu,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x20u,0x00u,0x19u},{0x80u,0x2au,0x00u,0x19u,0x00u,0x20u},{0x80u,0x00u,0x1bu,0x21u,0x00u,0x19u},{0x80u,0x2au,0x00u,0x19u,0x00u,0x21u}}; + + + +/* Prerequisites: + * - Homogeneous X- and Y-coordinates are stored in ECC_COORD00 and ECC_COORD01 + * - (Z*R)^(-1), where Z is the homogeneous Z-coordinate is stored in ECC_T0 */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_GenerateMultiplicativeBlinding.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_GenerateMultiplicativeBlinding.c new file mode 100644 index 000000000..8e18318ef --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_GenerateMultiplicativeBlinding.c @@ -0,0 +1,103 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_GenerateMultiplicativeBlinding.c + * @brief mcuxClEcc: implementation of GenerateMultiplicativeBlinding functions + */ + + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + + + +/** + * \brief This function securely generates a multiplicative decomposition (sigma, phi) + * of a secret scalar k with a 32-bit random phi with MSBit and LSBit set to 1 and + * sigma = phi^(-1) * k mod n. + * + * Inputs: + * pSession: handle for the current CL session; + * scalarIndex: table index of buffer storing the scalar k to be blinded. + * + * Prerequisites: + * - The decoded secret scalar k is contained in buffer scalarIndex; + * - ps1Len = (operandSize, operandSize). + * + * Results: + * - the 32-bit blinding phi is contained in buffer ECC_S0; + * - the blinded scalar sigma is contained in buffer ECC_S1. + * + * Other modifications: + * - buffers ECC_T0 and ECC_T1 are modified (as temp). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_GenerateMultiplicativeBlinding) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_GenerateMultiplicativeBlinding(mcuxClSession_Handle_t pSession, uint8_t scalarIndex) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_GenerateMultiplicativeBlinding); + + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_S0, 0u); + + const uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + + uint8_t *pS0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S0]); + + /* Generate S0 = phi = a 32-bit non-zero random, with PRNG. */ + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("PKC buffer is CPU word aligned.") + volatile uint32_t *p32S0 = (volatile uint32_t *) pS0; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + MCUX_CSSL_FP_FUNCTION_CALL(retGetRandom, mcuxClRandom_ncGenerate(pSession, pS0, MCUXCLECC_SCALARBLINDING_BYTELEN)); + if (MCUXCLRANDOM_STATUS_OK != retGetRandom) + { + /* if it fails, error code is related to RNG issue, so translated to generic return code */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_GenerateMultiplicativeBlinding, MCUXCLECC_STATUS_RNG_ERROR, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST); + } + + /* Set MSBit and LSBit of phi */ + *p32S0 |= 0x80000001u; + + /* Copy S0 = phi to S1 before calling ModInv (which will destroy input). */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_S1, ECC_S0, 0u); + + /* Calculate T0 = phi^(-1) mod n. */ + MCUXCLMATH_FP_MODINV(ECC_T0, ECC_S1, ECC_N, ECC_T1); + + /* Calculate S1 = sigma = phi^(-1) * k mod n, in the range [1, n-1]. */ + MCUXCLPKC_FP_CALC_MC1_MM(ECC_S1, scalarIndex, ECC_T0, ECC_N); + MCUXCLPKC_FP_CALC_MC1_MM(ECC_T0, ECC_S1, ECC_NQSQR, ECC_N); /* since NQSQR < n, the result is in [1, 2n-2]. */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_S1, ECC_T0, ECC_N, ECC_N); /* sigma in range [1, n-1]. */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_GenerateMultiplicativeBlinding, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveScalar.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveScalar.c new file mode 100644 index 000000000..fb2bc8068 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveScalar.c @@ -0,0 +1,95 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_InterleaveOneScalar.c + * @brief mcuxClEcc: implementation of ECC function mcuxClEcc_InterleaveScalar + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include + + +/** + * This function prepares one scalar to be used in scalar multiplication. + * The scalar will be bit-wised interleaved, e.g., + * (L0, L1, L2, ..., H0, H1, H2, ...) --> (L0, H0, L1, H1, L2, H2, ...). + * + * Inputs: + * iScalar index of PKC operand which contains the scalar; + * scalarBitLength: scalar length in bits. + * numberOfInterleavings: scalar will be numberOfInterleavings times interleaved + * + * Inputs in pOperands[] and PKC workarea: + * buffer iScalar which contains the scalar. + * + * Prerequisites: N/A. + * + * Result in PKC workarea: + * buffer iScalar which contain the interleaved scalar (always in-place). + * + * Other modifications: + * buffers T0 and T1 are modified (as temp); + * offsets pOperands[ECC_V0/ECC_V1/ECC_V3] are modified; + * ps2 LEN and MCLEN are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_InterleaveScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_InterleaveScalar(uint16_t iScalar, uint32_t scalarBitLength, uint32_t numberOfInterleavings) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_InterleaveScalar); + + uint32_t ps1LenRegBackup = MCUXCLPKC_PS1_GETLENGTH_REG(); + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - UPTR table is 32-bit aligned in ECC component."); + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + uint32_t bitLenHalfScalar = scalarBitLength - (scalarBitLength >> 1); /* ceil(bitLen / 2) */ + uint32_t byteLenHalfScalar_PKCWord = ((bitLenHalfScalar + (MCUXCLPKC_WORDSIZE * 8u) - 1u) / (MCUXCLPKC_WORDSIZE * 8u)) * MCUXCLPKC_WORDSIZE; + + uint32_t offsets_V1_V0 = /* ECC_V0 */ (uint32_t) pOperands[iScalar] + /* ECC_V1 */ + (((uint32_t) pOperands[ECC_T0] + byteLenHalfScalar_PKCWord) << 16); + + MCUXCLPKC_WAITFORREADY(); + /* MISRA Ex. 9 to Rule 11.3 - pOperands32 is pointer to 16-bit offset table */ + MCUXCLECC_STORE_2OFFSETS(pOperands32, ECC_V0, ECC_V1, offsets_V1_V0); + pOperands[ECC_V3] = (uint16_t) (0u - bitLenHalfScalar); /* PKC will ignore higher bits of shifting amount. */ + + MCUXCLPKC_ENABLEGF2(); + MCUXCLPKC_PS1_SETLENGTH(0u, 2u * byteLenHalfScalar_PKCWord); + MCUXCLPKC_PS2_SETLENGTH(byteLenHalfScalar_PKCWord, byteLenHalfScalar_PKCWord); + + /* Interleave iScalar. */ + for(uint32_t i = numberOfInterleavings; i > 0u ; i--) + { + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Interleave, mcuxClEcc_FUP_Interleave_LEN); + } + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_DISABLEGF2(); + MCUXCLPKC_PS1_SETLENGTH_REG(ps1LenRegBackup); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_InterleaveScalar, MCUXCLECC_STATUS_OK, + numberOfInterleavings * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveTwoScalars.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveTwoScalars.c new file mode 100644 index 000000000..dda03b292 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_InterleaveTwoScalars.c @@ -0,0 +1,100 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_InterleaveTwoScalars.c + * @brief mcuxClEcc: implementation of ECC function mcuxClEcc_InterleaveTwoScalars + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include + + +/** + * This function prepares two scalars to be used in scalar multiplication. + * Each scalar will be bit-wised interleaved, e.g., + * (L0, L1, L2, ..., H0, H1, H2, ...) --> (L0, H0, L1, H1, L2, H2, ...). + * + * Inputs: + * iScalar0_iScalar1: two indices of PKC operands, containing two scalars; + * scalarBitLength: scalar length in bits. + * + * Inputs in pOperands[] and PKC workarea: + * buffers iScalar0 and iScalar1 contain two scalars. + * + * Prerequisites: N/A. + * + * Result in PKC workarea: + * buffers iScalar0 and iScalar1 contain two interleaved scalars (always in-place). + * + * Other modifications: + * buffers T0 and T1 are modified (as temp); + * offsets pOperands[ECC_V0/ECC_V1/ECC_V3] are modified; + * ps2 LEN and MCLEN are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_InterleaveTwoScalars) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_InterleaveTwoScalars(uint16_t iScalar0_iScalar1, uint32_t scalarBitLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_InterleaveTwoScalars); + + uint32_t ps1LenRegBackup = MCUXCLPKC_PS1_GETLENGTH_REG(); + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + uint8_t iScalar0 = (uint8_t) (iScalar0_iScalar1 >> 8); + uint8_t iScalar1 = (uint8_t) (iScalar0_iScalar1 & 0xFFu); + + uint32_t bitLenHalfScalar = scalarBitLength - (scalarBitLength >> 1); /* ceil(bitLen / 2) */ + uint32_t byteLenHalfScalar_PKCWord = ((bitLenHalfScalar + (MCUXCLPKC_WORDSIZE * 8u) - 1u) / (MCUXCLPKC_WORDSIZE * 8u)) * MCUXCLPKC_WORDSIZE; + + uint32_t offsets_V1_V0 = /* ECC_V0 */ (uint32_t) pOperands[iScalar0] + /* ECC_V1 */ + (((uint32_t) pOperands[ECC_T0] + byteLenHalfScalar_PKCWord) << 16); + + MCUXCLPKC_WAITFORREADY(); + /* MISRA Ex. 9 to Rule 11.3 - pOperands32 is pointer to 16-bit offset table */ + MCUXCLECC_STORE_2OFFSETS(pOperands32, ECC_V0, ECC_V1, offsets_V1_V0); + pOperands[ECC_V3] = (uint16_t) (0u - bitLenHalfScalar); /* PKC will ignore higher bits of shifting amount. */ + + MCUXCLPKC_ENABLEGF2(); + MCUXCLPKC_PS1_SETLENGTH(0u, 2u * byteLenHalfScalar_PKCWord); + MCUXCLPKC_PS2_SETLENGTH(byteLenHalfScalar_PKCWord, byteLenHalfScalar_PKCWord); + + /* Interleave scalar0. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Interleave, mcuxClEcc_FUP_Interleave_LEN); + + /* Interleave scalar1. */ + MCUXCLPKC_WAITFORREADY(); + pOperands[ECC_V0] = pOperands[iScalar1]; + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Interleave, mcuxClEcc_FUP_Interleave_LEN); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_DISABLEGF2(); + MCUXCLPKC_PS1_SETLENGTH_REG(ps1LenRegBackup); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_InterleaveTwoScalars, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Interleave_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Interleave_FUP.c new file mode 100644 index 000000000..f6cd159a8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Interleave_FUP.c @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Interleave_FUP.c + * @brief mcuxClEcc: FUP program for internal interleave function + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Interleave[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xb8u,0x7cu,0x09u,0x1du},{0x00u,0x14u,0x00u,0x04u,0x07u,0x19u},{0xc0u,0x13u,0x05u,0x05u,0x00u,0x1bu},{0x00u,0x14u,0x00u,0x1bu,0x02u,0x1bu},{0x40u,0x15u,0x00u,0x19u,0x07u,0x04u},{0xc0u,0x13u,0x04u,0x04u,0x00u,0x19u},{0x00u,0x0eu,0x00u,0x19u,0x1bu,0x04u}}; + + + +/* Prerequisites: */ +/* ECC_V3 = shifting amount to have higher half of scalar aligned to PKC word; */ +/* VY0 points to higher half of buffer T0. */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_PointComparison_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_PointComparison_FUP.c new file mode 100644 index 000000000..6800dd1f4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_PointComparison_FUP.c @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_PointComparison_FUP.c + * @brief FUP programs for EdDSA Signature Verification + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_PointComparisonHom[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xf0u,0xf1u,0xd8u,0x77u},{0x80u,0x00u,0x04u,0x22u,0x00u,0x19u},{0x80u,0x00u,0x05u,0x22u,0x00u,0x1bu},{0x80u,0x00u,0x20u,0x06u,0x00u,0x1du},{0x80u,0x00u,0x21u,0x06u,0x00u,0x1fu},{0x80u,0x2au,0x10u,0x19u,0x1du,0x19u},{0x80u,0x2au,0x10u,0x1bu,0x1fu,0x1bu},{0x80u,0x00u,0x19u,0x1bu,0x00u,0x1du},{0x80u,0x33u,0x1du,0x00u,0x00u,0x1bu},{0x80u,0x2au,0x00u,0x1bu,0x00u,0x1bu}}; + + + +/** + * FUP program to check if two projective points P1 and P2 are equal + * + * Prerequisites: + * - ECC_V0 contains the X-coordinate of point P1 + * - ECC_V1 contains the Y-coordinate of point P1 + * - ECC_V2 contains the Z-coordinate of point P1 + * - ECC_COORD00 contains the X-coordinate of point P2 + * - ECC_COORD01 contains the Y-coordinate of point P2 + * - ECC_COORD02 contains the Z-coordinate of point P2 + * + * Result: + * - The zero flag is set if and only if the two points are equal + */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_RecodeAndReorderScalar.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_RecodeAndReorderScalar.c new file mode 100644 index 000000000..4206347f7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_RecodeAndReorderScalar.c @@ -0,0 +1,109 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_RecodeAndReorderScalar.c + * @brief mcuxClEcc: implementation of mcuxClEcc_RecodeAndReorderScalar + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + + +/** + * This function recodes an odd, potentially secret, scalar lambda = (lambda_{f*K-1},...,lambda_0)_2 of (not necessarily exact) bit length f*K, + * into non-zero BSD representation by rotating it right by one bit to obtain + * + * lambda~ = (lambda~_{f*K-1},...,lambda~_0)_2 = (lambda_{f*K-1},...,lambda_0)_2. + * + * Further, it reorders the bits of lambda~ for usage within the comb method by splitting it into f parts and interleaving them to obtain + * + * lambda' = (lambda~_{f*K-1}, lambda~_{(f-1)*K-1},...,lambda~_{K-1},...,lambda~_{(f-1)*K},lambda~_{(f-2)*K},...,lambda~_0)_2 + * + * Input: + * - pSession Handle for the current CL session + * - scalarIndex Table index of buffer storing the scalar lambda to be blinded + * - f Number of parts into which the scalar will be divided; must be a power of two + * - scalarBitLength scalar length in bits, must be a multiple of f. + * + * Prerequisites: + * - ps1Len = (operandSize, operandSize) + * + * Result: + * - The recoded and reordered scalar lambda' is contained in the buffer with table index scalarIndex. + * + * Other modifications: + * - Buffers ECC_T0 and ECC_T1 are modified (as temp). + * - Offsets pOperands[ECC_V0/ECC_V1/ECC_V3] are modified. + * - ps2 LEN and MCLEN are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_RecodeAndReorderScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_RecodeAndReorderScalar(mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint8_t scalarIndex, + uint8_t f, + uint32_t scalarBitLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_RecodeAndReorderScalar); + + /* Step 1: + * Set the pointer in ECC_V0 to the buffer corresponding to scalarIndex. + */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUXCLPKC_WAITFORREADY(); + pOperands[ECC_V0] = pOperands[scalarIndex]; + + /* Step 2: + * Use PKC to rotate the buffer ECC_V0 to the right by one bit. + */ + MCUXCLPKC_FP_CALC_OP1_ROTR(ECC_V0, ECC_V0, 1u); + + /* Step 3: + * Use the PKC to move the MSBit of the buffer to bit position f*K-1 of the buffer ECC_V0. The buffer now contains lambda~. + */ + // TODO: Moving the MSBit still to be done (but not necessary for Ed25519 and Ed448 with f = 4) -> CLNS-6486 + + /* Step 4: + * Successively ( log_2(f) times ) do the following: + * - Shift upper half of the f*K bit value in ECC_V0 to the next FAME word boundary + * - Use PKC to square lower and upper half of the value in ECC_V0 and store the results in ECC_T0 and ECC_T1, respectively + * - Left shift ECC_T1 by one bit + * - Set ECC_V0 = ECC_T0 | ECC_T1 + * + * This is all done by mcuxClEcc_InterleaveScalar. + */ + uint32_t fLog = 32u - mcuxClMath_CountLeadingZerosWord((uint32_t) f) - 1u; + MCUXCLECC_FP_INTERLEAVESCALAR(scalarIndex, scalarBitLength, fLog); + + /* Step 5: + * Complete pkc operations + */ + MCUXCLPKC_WAITFORREADY(); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_RecodeAndReorderScalar, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_CALC_OP1_ROTR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_InterleaveScalar)); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment.c new file mode 100644 index 000000000..08fefcfdd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment.c @@ -0,0 +1,136 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_SetupEnvironment.c + * @brief mcuxClEcc: implementation of mcuxClEcc_SetupEnvironment + */ + + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + + +/** + * This function sets up the general environment used by ECC functions. + * In particular, it sets up the utilized co-processors, prepares the PKC workarea layout, + * and initializes it for Montgomery arithmetic modulo p and n. + * + * Input: + * - pSession Handle for the current CL session + * - pCommonDomainParams Pointer to domain parameter struct passed via API + * - noOfBuffers Number of PKC buffers to be allocated + * + * Result: + * - The pointer table has been properly setup in CPU workarea and PKC buffers have been allocated + * - The PKC state has been backed up in CPU workarea and the PKC has been enabled + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_PFULL and ECC_NFULL contain p'||p and n'||n, respectively + * - Buffers ECC_PS and ECC_NS contain the p resp. n shifted to the PKC word boundary + * - Buffers ECC_PQSQR and ECC_NQSQR contain the R^2 values modulo p and n, respectively + * - Virtual pointers ECC_P and ECC_N point to the second PKC word of ECC_PFULL and ECC_NFULL, respectively + * - Virtual pointers ECC_ZERO and ECC_ONE have been initialized with 0 and 1, respecitvely + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_SetupEnvironment(mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pCommonDomainParams, + uint8_t noOfBuffers) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_SetupEnvironment); + + const uint32_t byteLenP = (uint32_t) pCommonDomainParams->byteLenP; + const uint32_t byteLenN = (uint32_t) pCommonDomainParams->byteLenN; + const uint32_t byteLenMax = ((byteLenP > byteLenN) ? byteLenP : byteLenN); + const uint32_t operandSize = MCUXCLPKC_ROUNDUP_SIZE(byteLenMax); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + + /* Setup CPU workarea and PKC buffer. */ + const uint32_t byteLenOperandsTable = (sizeof(uint16_t)) * (ECC_NO_OF_VIRTUALS + (uint32_t) noOfBuffers); + const uint32_t alignedByteLenCpuWa = (sizeof(mcuxClEcc_CpuWa_t)) + MCUXCLECC_ALIGNED_SIZE(byteLenOperandsTable); + const uint32_t wordNumCpuWa = alignedByteLenCpuWa / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, wordNumCpuWa); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t wordNumPkcWa = (bufferSize * (uint32_t) noOfBuffers) / (sizeof(uint32_t)); /* PKC bufferSize is a multiple of CPU word size. */ + const uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordNumPkcWa); + if ((NULL == pCpuWorkarea) || (NULL == pPkcWorkarea)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + } + pCpuWorkarea->wordNumCpuWa = wordNumCpuWa; + pCpuWorkarea->wordNumPkcWa = wordNumPkcWa; + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, &pCpuWorkarea->pkcStateBackup, mcuxClEcc_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + + /* Set PS1 MCLEN and LEN. */ + MCUXCLPKC_PS1_SETLENGTH(operandSize, operandSize); + + /* Setup UPTR table. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - Cast to 16-bit pointer table") + uint16_t *pOperands = (uint16_t *) pCpuWorkarea->pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_GENERATEUPTRT(& pOperands[ECC_NO_OF_VIRTUALS], + pPkcWorkarea, + (uint16_t) bufferSize, + noOfBuffers); + MCUXCLPKC_SETUPTRT(pOperands); + + /* Setup virtual offsets to prime p and curve order n. */ + pOperands[ECC_P] = pOperands[ECC_PFULL] + MCUXCLPKC_WORDSIZE; + pOperands[ECC_N] = pOperands[ECC_NFULL] + MCUXCLPKC_WORDSIZE; + + /* Initialize constants ONE = 0x0001 and ZERO = 0x0000 in uptr table. */ + pOperands[ECC_ONE] = 0x0001u; + pOperands[ECC_ZERO] = 0x0000u; + + /* Clear buffers P, N, PQSQR and NQSQR. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_SetupEnvironment_ClearBuffers, + mcuxClEcc_FUP_SetupEnvironment_ClearBuffers_LEN); + MCUXCLPKC_WAITFORFINISH(); + + /* Import prime p and order n, and corresponding Montgomery parameter (NDash). */ + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[ECC_PFULL]), pCommonDomainParams->pFullModulusP, MCUXCLPKC_WORDSIZE + byteLenP); + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[ECC_NFULL]), pCommonDomainParams->pFullModulusN, MCUXCLPKC_WORDSIZE + byteLenN); + + /* Import R^2 mod p and R^2 mod n. */ + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[ECC_PQSQR]), pCommonDomainParams->pR2P, byteLenP); + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[ECC_NQSQR]), pCommonDomainParams->pR2N, byteLenN); + + /* Calculate shifted modulus of p and n. */ + MCUXCLMATH_FP_SHIFTMODULUS(ECC_PS, ECC_P); + MCUXCLMATH_FP_SHIFTMODULUS(ECC_NS, ECC_N); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SetupEnvironment, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_GenerateUPTRT), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment_FUP.c new file mode 100644 index 000000000..de03daed0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_SetupEnvironment_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_SetupEnvironment_FUP.c + * @brief mcuxClEcc: FUP program for of mcuxClEcc_SetupEnvironment + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SetupEnvironment_ClearBuffers[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x2fu,0x3bu,0x1bu,0x01u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x00u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x01u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x16u},{0x00u,0x3eu,0x00u,0x00u,0x03u,0x17u}}; + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Types.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Types.c new file mode 100644 index 000000000..f4bcfa837 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Internal_Types.c @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Internal_Types.c + * @brief Instantiation of the type descriptors supported by the mcuxClEcc component. + */ + +#include + +/**********************************************************/ +/* Key pair generation descriptors */ +/**********************************************************/ + +const mcuxClEcc_EdDSA_GenerateKeyPairDescriptor_t mcuxClEcc_EdDsa_GeneratePrivKeyDescriptor = +{ + .options = MCUXCLECC_EDDSA_PRIVKEY_GENERATE, + .pPrivKeyInput = NULL +}; + + +/**********************************************************/ +/* Signature protocol descriptors */ +/**********************************************************/ +const mcuxClEcc_EdDSA_SignatureProtocolDescriptor_t mcuxClEcc_EdDsa_Ed25519ProtocolDescriptor = +{ + .generateOption = 0u, + .verifyOption = 0u, + .pHashPrefix = NULL, + .hashPrefixLen = 0u +}; + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_KeyTypes.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_KeyTypes.c new file mode 100644 index 000000000..7ae7acda7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_KeyTypes.c @@ -0,0 +1,133 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_KeyTypes.c + * @brief mcuxClEcc: implementation of ECC related key type descriptors + */ + +#include + +#include +#include +#include +#include + +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the key parameters.") +/* Key type structure for private and public ECC keys for Weierstrass curve secp160k1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP160K1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp160k1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp160k1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP160K1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp160k1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp192k1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP192K1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp192k1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192k1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP192K1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp192k1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp224k1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP224K1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp224k1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224k1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP224K1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp224k1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp256k1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP256K1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp256k1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256k1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP256K1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp256k1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp192r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP192R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp192r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp192r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP192R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp192r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp224r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP224R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp224r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp224r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP224R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp224r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp256r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP256R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp256r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp256r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP256R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp256r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp384r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP384R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp384r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp384r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP384R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp384r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve secp521r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_SECP521R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp521r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_secp521r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_SECP521R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_secp521r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP160r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP160r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP160R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP160r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP192r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP192r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP192R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP192r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP224r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP224r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP224R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP224r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP256r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP256r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP256R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP256r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP320r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP320r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP320R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP320r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP384r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP384r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP384R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP384r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP512r1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP512r1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512r1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP512R1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP512r1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP160t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP160t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP160t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP160T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP160t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP192t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP192t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP192t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP192T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP192t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP224t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP224t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP224t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP224T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP224t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP256t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP256t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP256t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP256T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP256t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP320t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP320t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP320t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP320T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP320t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP384t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP384t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP384t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP384T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP384t1}; + +/* Key type structure for private and public ECC keys for Weierstrass curve brainpoolP512t1 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP512t1}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_WeierECC_brainpoolP512t1_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP + MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_WEIERECC_BRAINPOOLP512T1_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_Weier_DomainParams_brainpoolP512t1}; + +/* Key type structure for private and public EdDSA keys for twisted Edwards curve Ed25519 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_EDDSA | MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_EDDSA_ED25519_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_EdDSA_DomainParams_Ed25519}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed25519_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_EDDSA | MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_EDDSA_ED25519_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_EdDSA_DomainParams_Ed25519}; + +/* Key type structure for private and public EdDSA keys for twisted Edwards curve Ed448 */ +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Priv = {.algoId = MCUXCLKEY_ALGO_ID_ECC_EDDSA | MCUXCLKEY_ALGO_ID_PRIVATE_KEY, .size = MCUXCLECC_EDDSA_ED448_SIZE_PRIVATEKEY, .info = (void *) &mcuxClEcc_EdDSA_DomainParams_Ed448}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_EdDSA_Ed448_Pub = {.algoId = MCUXCLKEY_ALGO_ID_ECC_EDDSA | MCUXCLKEY_ALGO_ID_PUBLIC_KEY, .size = MCUXCLECC_EDDSA_ED448_SIZE_PUBLICKEY, .info = (void *) &mcuxClEcc_EdDSA_DomainParams_Ed448}; + +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve25519_KeyPair = {.algoId = MCUXCLKEY_ALGO_ID_ECC_MONTDH | MCUXCLKEY_ALGO_ID_KEY_PAIR, .size = MCUXCLKEY_SIZE_NOTUSED, .info = (void *) &mcuxClEcc_MontDH_DomainParams_Curve25519}; +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Ecc_MontDH_Curve448_KeyPair = {.algoId = MCUXCLKEY_ALGO_ID_ECC_MONTDH | MCUXCLKEY_ALGO_ID_KEY_PAIR, .size = MCUXCLKEY_SIZE_NOTUSED, .info = (void *) &mcuxClEcc_MontDH_DomainParams_Curve448}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyAgreement.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyAgreement.c new file mode 100644 index 000000000..c6f39c6b3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyAgreement.c @@ -0,0 +1,131 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_DhKeyAgreement.c + * @brief mcuxClEcc: implementation of MontDh key agreement function acc to rfc 7748 + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Mont_DhKeyAgreement) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyAgreement( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + mcuxClKey_Handle_t otherKey, + uint8_t * pOut, + uint32_t * const pOutLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Mont_DhKeyAgreement); + + mcuxClKey_Descriptor_t * pKey = (mcuxClKey_Descriptor_t *)key; + mcuxClKey_Descriptor_t * pOtherKey = (mcuxClKey_Descriptor_t *)otherKey; + + if(((MCUXCLKEY_ALGO_ID_ECC_MONTDH | MCUXCLKEY_ALGO_ID_PRIVATE_KEY) != mcuxClKey_getAlgoId(pKey)) || (MCUXCLKEY_SIZE_NOTUSED != mcuxClKey_getSize(pKey)) + ||((MCUXCLKEY_ALGO_ID_ECC_MONTDH | MCUXCLKEY_ALGO_ID_PUBLIC_KEY) != mcuxClKey_getAlgoId(pOtherKey)) || (MCUXCLKEY_SIZE_NOTUSED != mcuxClKey_getSize(pOtherKey)) + ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Set up the environment */ + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters = (mcuxClEcc_MontDH_DomainParams_t *)mcuxClKey_getTypeInfo(pKey); + mcuxClEcc_CommonDomainParams_t *pCommonDomainParameters = &(pDomainParameters->common); + + /* For Curve25519 and Curve448, private and public keys have the same length as the prime p */ + uint16_t keyLen = pCommonDomainParameters->byteLenP; + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_FP_FUNCTION_CALL(retCode_MontDH_SetupEnvironment, mcuxClEcc_MontDH_SetupEnvironment(pSession, + pDomainParameters, + ECC_MONTDH_NO_OF_BUFFERS)); + if(MCUXCLECC_STATUS_OK != retCode_MontDH_SetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retCode_MontDH_SetupEnvironment, mcuxClEcc_Mont_DhKeyAgreement); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Securely import private key d to PKC buffer ECC_S2 */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_importPrivKey, mcuxClPkc_SecureImportLittleEndianToPkc(ECC_S2, mcuxClKey_getKeyData(pKey), keyLen)); + + /* Check the return code of mcuxClPkc_SecureImportLittleEndianToPkc */ + if(MCUXCLPKC_STATUS_OK != retCode_importPrivKey) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Call mcuxClEcc_Mont_DhX to calculate the public key q=MontDhX(d,Gx) and store it in buffer MONT_X0. If the function returns NEUTRAL_POINT, return MCUXCLECC_STATUS_FAULT_ATTACK */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_Mont_Dhx, mcuxClEcc_MontDH_X(pSession, pDomainParameters, mcuxClKey_getKeyData(pOtherKey))); + + if(MCUXCLECC_STATUS_RNG_ERROR == retCode_Mont_Dhx) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != retCode_Mont_Dhx) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_ERROR_SMALL_SUBGROUP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportLittleEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_X) + ); + } + else + { + /* Securely export shared secret from MONT_X0 */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_exportSS, mcuxClPkc_SecureExportLittleEndianFromPkc(pOut, MONT_X0, keyLen)); + + /* Check the return code of mcuxClPkc_SecureExportLittleEndianFromPkc */ + if(MCUXCLPKC_STATUS_OK != retCode_exportSS) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + *pOutLength = keyLen; + + /* Return OK and exit */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_Mont_DhKeyAgreement, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportLittleEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_X), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportLittleEndianFromPkc), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyGeneration.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyGeneration.c new file mode 100644 index 000000000..71d9640b7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_DhKeyGeneration.c @@ -0,0 +1,176 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_DhKeyGeneration.c + * @brief mcuxClEcc: implementation of MontDh key generation function + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK +#define MCUXCLECC_FP_MONT_DHKEYGEN_SECSTRENGTH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) +#else +#define MCUXCLECC_FP_MONT_DHKEYGEN_SECSTRENGTH (0u) +#endif + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Mont_DhKeyGeneration) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_DhKeyGeneration( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Mont_DhKeyGeneration); + + mcuxClKey_Descriptor_t * pPrivKey = (mcuxClKey_Descriptor_t *)privKey; + mcuxClKey_Descriptor_t * pPubKey = (mcuxClKey_Descriptor_t *)pubKey; + + if( ((MCUXCLKEY_ALGO_ID_ECC_MONTDH | MCUXCLKEY_ALGO_ID_KEY_PAIR) != type->algoId) + || (MCUXCLKEY_SIZE_NOTUSED != type->size) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + } + /* Set up the environment */ + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters = (mcuxClEcc_MontDH_DomainParams_t *)(type->info); + mcuxClEcc_CommonDomainParams_t *pCommonDomainParameters = (mcuxClEcc_CommonDomainParams_t *)&(pDomainParameters->common); + + /* For Curve25519 and Curve448, private and public keys have the same length as the prime p */ + uint16_t keyLen = pCommonDomainParameters->byteLenP; + + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_FP_FUNCTION_CALL(retCode_MontDH_SetupEnvironment, mcuxClEcc_MontDH_SetupEnvironment(pSession, + pDomainParameters, + ECC_MONTDH_NO_OF_BUFFERS)); + if(MCUXCLECC_STATUS_OK != retCode_MontDH_SetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retCode_MontDH_SetupEnvironment, mcuxClEcc_Mont_DhKeyGeneration); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + + /* Generate a M byte random private key d using the DRBG and store it in PKC buffer ECC_S2, M equals to dp->nLen */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint8_t * ptrS2 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S2]); + + /* Derive the security strength required for the RNG from bitLenN/2 and check whether it can be provided. */ +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK + MCUX_CSSL_FP_FUNCTION_CALL(ret_checkSecurityStrength, mcuxClRandom_checkSecurityStrength(pSession, ((uint32_t) pCommonDomainParameters->byteLenN * 8u) / 2u)); + if (MCUXCLRANDOM_STATUS_OK != ret_checkSecurityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) ); + } +#endif + + MCUXCLECC_FP_RANDOM_HQRNG_PKCWA(mcuxClEcc_Mont_DhKeyGeneration, pSession, ptrS2, keyLen); + + /* Call mcuxClEcc_MontDH_X to calculate the public key q=MontDhX(d,Gx) and store it in buffer MONT_X0. If the function returns NEUTRAL_POINT, return MCUXCLECC_STATUS_FAULT_ATTACK */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_Mont_Dhx, mcuxClEcc_MontDH_X(pSession, pDomainParameters, pDomainParameters->common.pGx)); + + if(MCUXCLECC_STATUS_RNG_ERROR == retCode_Mont_Dhx) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_SetupEnvironment), + MCUXCLECC_FP_MONT_DHKEYGEN_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_X)); + } + else if(MCUXCLECC_STATUS_OK != retCode_Mont_Dhx) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Securely export the private key d from PKC buffer ECC_S2 and export the public key q from MONT_X0 */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExport, mcuxClPkc_SecureExportLittleEndianFromPkc(pPrivData, ECC_S2, keyLen)); + if (MCUXCLPKC_STATUS_OK != ret_SecExport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Export x-coordinate of the public key in Little Endian */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pPubData, MONT_X0, keyLen); + + /* Fill key_handle_t structures */ + mcuxClKey_TypeDescriptor_t keyType_private = { type->algoId ^ MCUXCLKEY_ALGO_ID_KEY_PAIR ^ MCUXCLKEY_ALGO_ID_PRIVATE_KEY, + type->size, type->info }; // TODO CLNS-5165: move the generation of these types into the key component + mcuxClKey_setTypeDescriptor(pPrivKey, keyType_private); + mcuxClKey_setProtectionType(pPrivKey, protection); + mcuxClKey_setKeyData(pPrivKey, pPrivData); + + mcuxClKey_TypeDescriptor_t keyType_public = { type->algoId ^ MCUXCLKEY_ALGO_ID_KEY_PAIR ^ MCUXCLKEY_ALGO_ID_PUBLIC_KEY, + type->size, type->info }; // TODO CLNS-5165: move the generation of these types into the key component + mcuxClKey_setTypeDescriptor(pPubKey, keyType_public); + mcuxClKey_setProtectionType(pPubKey, protection); + mcuxClKey_setKeyData(pPubKey, pPubData); + + *(pPrivDataLength) = keyLen; + *(pPubDataLength) = keyLen; + + /* Create link between private and public key handles */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_linkKeyPair, mcuxClKey_linkKeyPair(pSession, privKey, pubKey)); + if (MCUXCLKEY_STATUS_OK != ret_linkKeyPair) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Return OK and exit */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_Mont_DhKeyGeneration, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_SetupEnvironment), + MCUXCLECC_FP_MONT_DHKEYGEN_SECSTRENGTH, + MCUXCLECC_FP_CALLED_RANDOM_HQRNG_PKCWA, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_X), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportLittleEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportLittleEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_linkKeyPair), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_DhSetupEnvironment.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_DhSetupEnvironment.c new file mode 100644 index 000000000..730f68f5e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_DhSetupEnvironment.c @@ -0,0 +1,76 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_DhSetupEnvironment.c + * @brief Montgomery curve internal setup environment + */ + + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + + +/** + * \brief This function sets up environment used by MontDH functions. + * + * On top of generic ECC environment setup function, mcuxClEcc_SetupEnvironment, + * this function further imports the ladder constant A24 = (A+2)/4 mod p, + * converts it to Montgomery representation, and stores in buffer ECC_CP0. + * + * Inputs: + * - pSession: pointer to session descriptor; + * - pDomainParams: pointer to MontDH domain parameter structure; + * - noOfBuffers: number of buffers in PKC workarea used by calling API. + * + * Results: + * - results of mcuxClEcc_SetupEnvironment; + * - Buffer ECC_CP0 contains the ladder constant (A+2)/4 mod p in MR. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_MontDH_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_SetupEnvironment(mcuxClSession_Handle_t pSession, + mcuxClEcc_MontDH_DomainParams_t *pDomainParams, + uint8_t noOfBuffers) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_MontDH_SetupEnvironment); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_SetupEnvironment(pSession, &(pDomainParams->common), noOfBuffers) ); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_MontDH_SetupEnvironment); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Import ladder constant (A+2)/4 mod p. */ + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, + pDomainParams->common.pLadderConst, + (uint32_t) pDomainParams->common.byteLenP); + + /* Convert ladder constant to Montgomery representation. */ + MCUXCLPKC_FP_CALC_MC1_MM(ECC_CP0, ECC_T0, ECC_PQSQR, ECC_P); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_SetupEnvironment, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX.c new file mode 100644 index 000000000..b39ecb669 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX.c @@ -0,0 +1,252 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_MontDhX.c + * @brief implementation of MontDhX functions + */ + + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + + +/** + * \brief This function decodes an encoded Curve25519 or Curve448 scalar kEnc. + * + * Input: + * - pDomainParameters: pointer to domain parameter structure passed via API. + * + * Prerequisites: + * - the encoded secret scalar kEnc is contained in buffer ECC_S2; + * - ps1Len = (operandSize, operandSize). + * + * Result: + * - the decoded secret scalar k is contained in buffer ECC_S3. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_MontDH_DecodeScalar) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_DecodeScalar( + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_MontDH_DecodeScalar); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t c = (uint32_t) pDomainParameters->c; + uint32_t t = (uint32_t) pDomainParameters->t; + + MCUXCLPKC_WAITFORREADY(); + pOperands[MONT_V0] = (uint16_t) c; /* Clear c LSbits by right shift */ + pOperands[MONT_V1] = (uint16_t) (c - t); /* Clear bit t ~ MSbits by left shift. PKC will left shift (c - t mod PKCWordBitLen) bits */ + pOperands[MONT_V2] = (uint16_t) (0u - t); /* Left rotate the bit "1" back to bit position t */ + + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_MontDhDecodeScalar, + mcuxClEcc_FUP_MontDhDecodeScalar_LEN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_DecodeScalar, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); +} + + +/** + * \brief This function imports and decodes an encoded Curve25519 or Curve448 + * x-coordinate uEnc. + * + * Inputs: + * - pDomainParameters: pointer to domain parameter structure passed via API; + * - pCoordinateEnc: pointer to encoded x-coordinate. + * + * Prerequisite: + * - ps1Len = (operandSize, operandSize). + * + * Result: + * - the decoded x-coordinate u is contained in buffer MONT_X0 in MR. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_MontDH_DecodeCoordinate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_DecodeCoordinate( + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters, + const uint8_t *pCoordinateEnc) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_MontDH_DecodeCoordinate); + + /* Import encoded x-coordinate uEnc. */ + uint32_t byteLenP = (uint32_t) pDomainParameters->common.byteLenP; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pCoordinateEnc, byteLenP); + + /* If leadingZerosP != 0 (X25519), mask MSByte according to rfc7748, Ch5. */ + uint32_t leadingZerosP; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(ECC_P, &leadingZerosP)); + if (0u != leadingZerosP) + { + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + uint32_t bitLenP = (operandSize * 8u) - leadingZerosP; + uint32_t mask = ((uint32_t) 1u << (bitLenP % 32u)) - 1u; + + const uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pT0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_T0]); + uint32_t *p32T0 = (uint32_t *) pT0; /* PKC word is CPU word aligned. */ + p32T0[bitLenP / 32u] &= mask; + } + + /* Covert x-coordinate to Montgomery representation. */ + MCUXCLPKC_FP_CALC_MC1_MM(MONT_X0, ECC_T0, ECC_PQSQR, ECC_P); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_DecodeCoordinate, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM); +} + + +/** + * \brief This function implements the X25519 and X448 functions specified + * in rfc7748, depending on the used curve, which basically performs + * a secure x-only scalar multiplication of an encoded scalar kEnc and + * an encoded x-coordinate uEnc and returns the encoded resulting x-coordinate + * as MontDhX(kEnc, uEnc). Here, the encoding of scalars and x-coordinates + * are following the specification in rfc7748. + * + * Inputs: + * - pSession: pointer to mcuxClSession_Descriptor. + * - pDomainParameters: pointer to domain parameter structure passed via API; + * - pCoordinateUEnc: pointer to encoded x-coordinate uEnc. + * + * Return values: + * - MCUXCLECC_STATUS_OK: if the function executed successfully; + * - MCUXCLECC_STATUS_NEUTRAL_POINT: if the resulting point is zero. + * + * Prerequisite: + * - the encoded secret scalar kEnc is contained in buffer ECC_S2. + * + * Result: + * - the decoded secret scalar k is stored in buffer ECC_S2; + * - if MCUXCLECC_STATUS_OK is returned, then the result MontDhX(kEnc, uEnc) + * is stored in buffer MONT_X0 (in NR, in the range [0, p-1]); + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_MontDH_X) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_MontDH_X( + mcuxClSession_Handle_t pSession, + mcuxClEcc_MontDH_DomainParams_t *pDomainParameters, + const uint8_t *pCoordinateUEnc) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_MontDH_X); + + /* Decode the scalar kEnc and obtain ECC_S3 = k. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_MontDH_DecodeScalar(pDomainParameters)); + + /* Compute the cofactorless scalar k' = k/h for cofactorless blinded scalar multiplication */ + MCUXCLPKC_FP_CALC_OP1_SHR(ECC_S3, ECC_S3, (uint32_t) pDomainParameters->c & 0xFFu); + + /* Generate multiplicative scalar splitting k' = phi*sigma mod n and store (phi, sigma) in (ECC_S1, ECC_S0). */ + MCUX_CSSL_FP_FUNCTION_CALL(retGenMulBlind, + mcuxClEcc_GenerateMultiplicativeBlinding(pSession, ECC_S3)); + if (MCUXCLECC_STATUS_OK != retGenMulBlind) + { + /* GenerateMultiplicativeBlinding is returning only OK or RNG_ERROR */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_RNG_ERROR); + + } + MCUXCLPKC_WAITFORFINISH(); + /* Decode x-coordinate uEnc and obtain X0 = u in MR. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_MontDH_DecodeCoordinate(pDomainParameters, pCoordinateUEnc)); + + /* Securely calculate, R' = sigma * (u, 1), stored result in buffers (X0, Z0). */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + uint32_t leadingZeroN; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(ECC_N, &leadingZeroN)); + uint32_t bitLenN = (operandSize * 8u) - leadingZeroN; + MCUX_CSSL_FP_FUNCTION_CALL(retSecScalarMult0, + mcuxClEcc_Mont_SecureScalarMult_XZMontLadder(pSession, ECC_S1, bitLenN, MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT)); + if (MCUXCLECC_STATUS_OK != retSecScalarMult0) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Securely calculate, R'' = phi * R', stored result in buffers (X0, Z0). */ + /* Secure multiplication is not needed here, but we do not have non secure one */ + MCUX_CSSL_FP_FUNCTION_CALL(retSecScalarMult1, + mcuxClEcc_Mont_SecureScalarMult_XZMontLadder(pSession, ECC_S0, MCUXCLECC_SCALARBLINDING_BITSIZE, MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT)); + if (MCUXCLECC_STATUS_OK != retSecScalarMult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_FAULT_ATTACK); + } + /* Copy cofactor to the buffer ECC_S0 overwriting phi */ + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_S0, 0u); + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pS0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S0]); + MCUXCLPKC_WAITFORFINISH(); + *(pS0) = (1u << pDomainParameters->c); + /* Securely calculate, R = cofactor * R'', stored result in buffers (X0, Z0). */ + MCUX_CSSL_FP_FUNCTION_CALL(retSecScalarMult2, + mcuxClEcc_Mont_SecureScalarMult_XZMontLadder(pSession, ECC_S0, (uint32_t)(pDomainParameters->c) + 1u, MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT)); + if (MCUXCLECC_STATUS_OK != retSecScalarMult2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T0, MONT_Z0, ECC_P); /* T0 = Z in NR, in range [0, p] */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T0, ECC_T0, ECC_P, ECC_P); /* T0 = Z in NR, in range [0, p-1] */ + + /* Check against NEUTRAL_POINT. */ + uint32_t zeroFlag = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if (MCUXCLPKC_FLAG_ZERO == zeroFlag) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_NEUTRAL_POINT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_DecodeScalar), + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_GenerateMultiplicativeBlinding), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_DecodeCoordinate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + } + + /* Calculate T1 = Z^(-1) in NR. */ + MCUXCLMATH_FP_MODINV(ECC_T1, ECC_T0, ECC_P, MONT_Z0); + /* Calculate X0 = X * Z^(-1) in NR. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_MontDhX_CalcAffineX, + mcuxClEcc_FUP_MontDhX_CalcAffineX_LEN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_MontDH_X, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_DecodeScalar), + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_GenerateMultiplicativeBlinding), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_MontDH_DecodeCoordinate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder), + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX_FUP.c new file mode 100644 index 000000000..0bdd0b8ac --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_MontDhX_FUP.c @@ -0,0 +1,35 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_MontDhX_FUP.c + * @brief FUP programs for MontDhX functions + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhDecodeScalar[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x2bu,0x0au,0x97u,0x1fu},{0x00u,0x15u,0x00u,0x1cu,0x04u,0x1eu},{0x00u,0x14u,0x00u,0x1eu,0x05u,0x1eu},{0x00u,0x1au,0x00u,0x1eu,0x02u,0x1eu},{0x00u,0x17u,0x00u,0x1eu,0x06u,0x1eu}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_MontDhX_CalcAffineX[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x11u,0x0bu,0x8fu,0x7du},{0x80u,0x00u,0x1bu,0x16u,0x00u,0x19u},{0x80u,0x00u,0x20u,0x19u,0x00u,0x1bu},{0x80u,0x33u,0x1bu,0x00u,0x00u,0x20u},{0x80u,0x2au,0x00u,0x20u,0x00u,0x20u}}; + + +/* The algorithm implemented by this FUP program to decode an encoded Curve25519 or Curve448 private key + * only works if: + * c < 8*pkcWordSize + * 0 < 8*operandSize - t + c < 8*pkcWordSize-1 + * + * For the use cases Curve25519 and Curve448 these conditions are met. */ + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c new file mode 100644 index 000000000..229f150e2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c @@ -0,0 +1,193 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.c + * @brief mcuxClEcc: implementation of ECC internal secure scalar multiplication function montgomery ladder based + */ + + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + + +/** + * This function implements secure point scalar multiplication, R = scalar * P, based on XZ coordinates Montgomery ladder. + * + * Inputs: + * iScalar: index of PKC buffer storing the scalar, which is non-zero and in little-endian; + * scalarBitLength: bit length of scalar. + * optionAffineOrProjective: Option value specifying whether the input point P is given in affine or randomized projective coordinates + * + * + * Prerequisites: + * If optionAffineOrProjective is set to MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT, buffer MONT_X0 contains x in MR + * If optionAffineOrProjective is set to MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT, buffers MONT_X0 and MONT_Z0 contain X and Z in MR + * buffer buf(iScalar) contains the secret scalar lambda of bit length scalarBitLength + * buffer ECC_CP0 contains the ladder constant A24=(A+2)/4 mod p in MR + * ps1Len = (operandSize, operandSize) + * Buffer ECC_PFULL contains p'||p + * Buffer ECC_PS contains the shifted modulus associated to p + * + * Result in PKC workarea: + * buffers MONT_X0 and MONT_Z0 contain Xres and Zres in MR + * + * Other modifications: + * buffers ECC_T0, ECC_T1, ECC_T2, ECC_T3, MONT_X1, MONT_X2, MONT_Z1, MONT_Z2 modified + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Mont_SecureScalarMult_XZMontLadder(mcuxClSession_Handle_t pSession, uint8_t iScalar, uint32_t scalarBitLength, uint32_t optionAffineOrProjective) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder); + + /* Determine pointer table pointer */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy - TODO CLNS-6410: check if this is necessary + const uint32_t *pScalar = (const uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[iScalar]); /* MISRA Ex. 9 to Rule 11.3 - PKC word is CPU word aligned. */ + + /* Initialize accumulated coordinate buffers for the ladder iteration depending on optionAffineOrProjective + * NOTE: As discussed with SA, no coordinate or pointer table randomization/re-randomization is needed for the moment. It can easily be added at a later point in time. + */ + MCUXCLPKC_FP_CALC_OP1_NEG(MONT_X1, ECC_P); /* 1 in MR */ + MCUXCLPKC_FP_CALC_OP1_CONST(MONT_Z1, 0u); + + MCUX_CSSL_FP_SWITCH_DECL(optionAffineOrProjectiveSwitch); + if(MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT == optionAffineOrProjective) + { + MCUXCLPKC_FP_CALC_OP1_OR_CONST(MONT_X2, MONT_X0, 0u); + MCUXCLPKC_FP_CALC_OP1_NEG(MONT_Z2, ECC_P); /* 1 in MR */ + MCUX_CSSL_FP_SWITCH_CASE(optionAffineOrProjectiveSwitch, MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT, MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, MCUXCLPKC_FP_CALLED_CALC_OP1_NEG); + + } + else if(MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT == (MCUXCLECC_SCALARMULT_OPTION_INPUT_MASK & optionAffineOrProjective)) + { + MCUXCLPKC_FP_CALC_OP1_OR_CONST(MONT_X2, MONT_X0, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(MONT_Z2, MONT_Z0, 0u); + MCUX_CSSL_FP_SWITCH_CASE(optionAffineOrProjectiveSwitch, MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT, MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST); + + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /* Perform ladder iteration to calculate (X_res:Z_res) */ + uint32_t i = scalarBitLength; + uint32_t maskedCurrentScalarWord = 0u; + MCUX_CSSL_FP_LOOP_DECL(whileLoop); + MCUX_CSSL_FP_BRANCH_DECL(ifInWhile); + while(0u < i) + { + + /* Update loop counter, deviation from the design to let iterate over unsigned value */ + --i; + /* Set pointers pOperands(MONT_VX1),...,pOperands(MONT_VZ2) according to the bit to be processed */ + MCUXCLPKC_WAITFORFINISH(); + uint32_t currentScalarBitInWord = i % 32u; + uint32_t currentScalarWordMask; + + if((i == (scalarBitLength - 1u)) || ((i % 32u) == 31u)) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom0, mcuxClRandom_ncGenerate(pSession, (uint8_t*)¤tScalarWordMask, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Prng_GetRandom0) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + + uint32_t currentScalarWordIndex = i / 32u; + maskedCurrentScalarWord = pScalar[currentScalarWordIndex] ^ currentScalarWordMask; + MCUX_CSSL_FP_BRANCH_POSITIVE(ifInWhile, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + } + uint32_t offsetsP0 = 0xFFFFFFFFu; + uint32_t offsetsP1 = 0xFFFFFFFFu; + uint32_t randomMask; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom1, mcuxClRandom_ncGenerate(pSession, (uint8_t*)&randomMask, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Prng_GetRandom1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* When bit of scalar = 0, the macro returns: */ + /* offsetsP0 = pOperands[MONT_Z1] || pOperands[MONT_X1], and */ + /* offsetsP1 = pOperands[MONT_Z2] || pOperands[MONT_X2]; */ + /* when bit = 1, */ + /* offsetsP0 = pOperands[MONT_Z2] || pOperands[MONT_X2], and */ + /* offsetsP1 = pOperands[MONT_Z1] || pOperands[MONT_X1]. */ + MCUXCLECC_SECUREPOINTSELECT(offsetsP0, offsetsP1, pOperands, MONT_X1, + maskedCurrentScalarWord, currentScalarWordMask, randomMask, currentScalarBitInWord); + + MCUXCLPKC_WAITFORREADY(); + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUXCLECC_STORE_2OFFSETS(pOperands32, MONT_VX1, MONT_VZ1, offsetsP0); + MCUXCLECC_STORE_2OFFSETS(pOperands32, MONT_VX2, MONT_VZ2, offsetsP1); + + /* Perform the ladder step to calculate (MONT_VX1,MONT_VZ1) = 2 * (MONT_VX1,MONT_VZ1) and (MONT_VX2, MONT_VZ2) = (MONT_VX1,MONT_VZ1) + (MONT_VX2,MONT_VZ2)*/ + + /* FP balancing at the end of loop iteration end as both cases are calling same function */ + if(MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT == (MCUXCLECC_SCALARMULT_OPTION_INPUT_MASK & optionAffineOrProjective)) + { + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep, + mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep_Projective_LEN); + } + else + { + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep, + mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep_Affine_LEN); + } + + MCUX_CSSL_FP_LOOP_ITERATION(whileLoop, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(ifInWhile, (i == (scalarBitLength - 1u)) || ((i % 32u) == 31u)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); + } + + /* Copy resulting coordinates to buffers MONT_X0 and MONT_Z0 */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(MONT_X0, MONT_X1, 0u); /* MONT_X0 = MONT_X1 */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(MONT_Z0, MONT_Z1, 0u); /* MONT_Z0 = MONT_Z1 */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Mont_SecureScalarMult_XZMontLadder, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + /* switch statement */ + MCUX_CSSL_FP_SWITCH_TAKEN( + optionAffineOrProjectiveSwitch, + MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT, + MCUXCLECC_SCALARMULT_OPTION_AFFINE_INPUT == (MCUXCLECC_SCALARMULT_OPTION_INPUT_MASK & optionAffineOrProjective)), + MCUX_CSSL_FP_SWITCH_TAKEN( + optionAffineOrProjectiveSwitch, + MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT, + MCUXCLECC_SCALARMULT_OPTION_PROJECTIVE_INPUT == (MCUXCLECC_SCALARMULT_OPTION_INPUT_MASK & optionAffineOrProjective)), + MCUX_CSSL_FP_LOOP_ITERATIONS(whileLoop, scalarBitLength), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.c new file mode 100644 index 000000000..b03f5be6a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.c + * @brief mcuxClEcc: FUP programs for implementation of ECC internal secure scalar multiplication function montgomery ladder based + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_SecureScalarMult_XZMontLadder_LadderStep[22] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x7du,0x8cu,0x47u,0x56u},{0x80u,0x21u,0x10u,0x0cu,0x0du,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1du},{0x80u,0x2au,0x10u,0x0cu,0x0du,0x1bu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x1fu},{0x80u,0x00u,0x1du,0x1fu,0x00u,0x0cu},{0x80u,0x2au,0x10u,0x1du,0x1fu,0x1du},{0x80u,0x00u,0x12u,0x1du,0x00u,0x0du},{0x80u,0x21u,0x10u,0x1fu,0x0du,0x1fu},{0x80u,0x00u,0x1du,0x1fu,0x00u,0x0du},{0x80u,0x21u,0x10u,0x0eu,0x0fu,0x1du},{0x80u,0x00u,0x1du,0x1bu,0x00u,0x1fu},{0x80u,0x2au,0x10u,0x0eu,0x0fu,0x1bu},{0x80u,0x00u,0x1bu,0x19u,0x00u,0x1du},{0x80u,0x2au,0x10u,0x1du,0x1fu,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1bu},{0x80u,0x00u,0x20u,0x1bu,0x00u,0x0fu},{0x80u,0x21u,0x10u,0x1du,0x1fu,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x0eu},{0x10u,0x00u,0x4bu,0x90u,0x6au,0xfcu},{0x00u,0x1eu,0x00u,0x0eu,0x03u,0x1bu},{0x80u,0x00u,0x21u,0x1bu,0x00u,0x0eu}}; + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_SignatureMechanisms.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_SignatureMechanisms.c new file mode 100644 index 000000000..f8e9e1781 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_SignatureMechanisms.c @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_SignatureModes.c + * @brief mcuxClEcc: implementation of ECC related signature mode descriptors + */ + +#include +#include +#include + +#include + +#include + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_FixScalarMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_FixScalarMult.c new file mode 100644 index 000000000..67bd1f083 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_FixScalarMult.c @@ -0,0 +1,222 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_FixScalarMult.c + * @brief EdDSA internal function for scalar multiplication with the base points + */ + + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * This function implements a scalar multiplication lambda*G for a given secret scalar lambda in {1,...,n-1} + * and the base point G on a twisted Edwards curves. The result will be returned in homogeneous coordinates (Xres:Yres:Zres). + * The scalar multiplication is implemented using a regular comb method processing 4 bits at a time. To achieve regularity, + * the scalar is recoded into a non-zero BSD representation and the comb method is implemented by doing a double-and-add-or-subtract + * loop using pre-computed points + * + * P_(i3 i2 i1)_2 = G_0 + (-1)^(1 - i1) * G1 + (-1)^(1-i2) * G2 + (-1)^(1-i3) * G3, + * + * where Gi = 2^(i*scalarBitLength/4), which are provided by the EdDSA Domain Parameters. + * + * For the point arithmetic executed during the scalar multiplication iterations, extended homogeneous coordinates are used + * as described in https://eprint.iacr.org/2008/522.pdf which represent a point (x,y) by (X:Y:Z:T) with x=X/Z, y=Y/Z and x*y=T/Z. + * Due to the fact that with the chosen regular scalar multiplication algorithm we don't have consecutive doublings, there's no point + * in mixing extended homogeneous with homogeneous coordinates as suggested in Section 4.3 of https://eprint.iacr.org/2008/522.pdf. + * + * Input: + * - pSession Handle for the current CL session + * - pDomainParams Pointer to ECC common domain parameters structure + * - iScalar Pointer table index of secret scalar lambda + * - scalarBitLength Bit length of the scalar; must coincide with the bit length of n + * - pMixedPointAddFct Curve dependent function to perform mixed point addition on twisted Edwards curve + * - pPointDoubleFct Curve dependent function to perform point doubling on twisted Edwards curve + * - pPtrSelectFctFP Function to select pre-computed point to be added + * + * Prerequisites: + * - Buffer buf(iScalar) contains the secret scalar lambda of bit length scalarBitLength + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_CP0 and ECC_CP1 contain the curve parameters a and d in MR + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - Buffers TWED_X, TWED_Y and TWED_Z contain Xres, Yres and Zres in MR + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_FixScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_FixScalarMult( + mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pDomainParams, + uint8_t iScalar, + uint32_t scalarBitLength, + const mcuxClEcc_TwEd_MixedPointAddFunction_FP_t *pMixedPointAddFctFP, + const mcuxClEcc_TwEd_PointDoubleFunction_FP_t *pPointDoubleFctFP, + const mcuxClEcc_TwEd_PtrSelectFunction_FP_t *pPtrSelectFctFP + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_FixScalarMult); + + const uint32_t byteLenP = pDomainParams->byteLenP; + + /* Determine pointer table pointer */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy - TODO CLNS-6410: check if this is necessary + + + /* + * Step 1: Ensure that the scalar used subsequently is odd by negating it modulo n + * + * NOTE: As a prerequisite of this function, the passed scalarBitLength equals the bit length of n. + * Hence, scalarBitLength is also an appropriate scalar length for the negative scalar. + */ + // TODO: hardening + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - pOperands is 32-bit aligned"); + uint32_t *pScalar = (uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[iScalar]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + MCUXCLPKC_WAITFORFINISH(); + const uint32_t scalarLsb = pScalar[0u] & 0x1u; + if(0u == scalarLsb) + { + MCUXCLPKC_FP_CALC_OP1_SUB(iScalar, ECC_N, iScalar); + } + + /* + * Step 2: Call function mcuxClEcc_RecodeAndReorderScalar to obtain the recoded + * and reordered secret scalar lambda' in buffer buf(iScalar). + */ + + /* Round scalar length up to the next multiple of f as this is required by the reordering and comb method. */ + scalarBitLength = MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE * ((scalarBitLength + (MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE - 1u)) / MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE); + + /* Recode and reorder scalar. */ + MCUXCLECC_FP_RECODEANDREORDERSCALAR(iScalar, MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE, scalarBitLength); + + /* + * Step 3: Initialize the accumulated point P in buffers TWED_X, TWED_Y, TWED_Z and TWED_T with + * the coordinates of the neutral point given in extended homogeneous coordinates (0:Z:Z:0) for some Z (!==) 0 modp (in MR). + */ + MCUXCLPKC_FP_CALC_OP1_CONST(TWED_X, 0u); + MCUXCLPKC_FP_CALC_OP1_NEG(TWED_Y, ECC_P); + MCUXCLPKC_FP_CALC_OP1_NEG(TWED_Z, ECC_P); + MCUXCLPKC_FP_CALC_OP1_CONST(TWED_T, 0u); + + /* + * Step 4: For each of the 8 pre-computed points Pi, i = 0,...,7, call function mcuxClEcc_TwEd_PrecPointImportAndValidate to + * - import its x- and y-coordinates, convert them to extended affine coordinates in MR and in range [0,p-1] + * and store them in buffers TWED_PP_Xi TWED_PP_Yi. + * - calculate the t-coordinates (ti = xi * yi) in MR in range [0,p-1] and store them in buffers TWED_PP_Ti. + * - verify that the point lies on the curve + */ + for(uint32_t i = 0u; i < MCUXCLECC_TWED_FIXSCALARMULT_NOOFPRECPOINTS; i++) + { + MCUX_CSSL_FP_FUNCTION_CALL(importPointStatus, + mcuxClEcc_TwEd_PrecPointImportAndValidate(pSession, (uint8_t)(TWED_PP_X0 + (TWED_PP_X1 - TWED_PP_X0) * i), pDomainParams->pPrecPoints + (2u * i * byteLenP), (uint16_t)byteLenP)); + if(MCUXCLECC_STATUS_OK != importPointStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_FixScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + } + + /* + * Step 5: For i from (scalarBitLength - 4) down to 0: + * - Call point doubling routine defined by pPointDoubleFct to compute P = 2*P + * - Get digit (i3 i2 i1 i0)_2 at offset i in buf(iScalar), and set PP = P_((i3 i2 i1)_2 ^ (i0 i0 i0)_2 ^ (1 1 1)_2) + * - Call pointer selection routine specified by pPtrSelectFct to set TWED_PP_VX0 to the buffer storing the X-coordinate of PP and + * - if i0 = 1, set TWED_PP_VY0 and TWED_PP_VT0 to the buffers storing the Y- and T-coordinates of PP. + * - if i0 = 0, set TWED_PP_VY0 and TWED_PP_VT0 to buffers ECC_T2 and ECC_T3 and store the negative Y- and T-coordinates of PP in buffers ECC_T2 and ECC_T3. + * - Call mixed point addition routine defined by pMixedPointAddFct to compute P = P + PP. + */ + uint32_t currentDigitBitIndex = scalarBitLength; /* scalarBitLength is multiple of MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE, so index can be unsigned. */ + uint32_t currentScalarWord = 0u; + MCUX_CSSL_FP_LOOP_DECL(whileLoop); + MCUX_CSSL_FP_BRANCH_DECL(ifInWhile); + while(currentDigitBitIndex > 0u) + { + /* Update loop counter, deviation from the design to let iterate over unsigned value */ + currentDigitBitIndex -= MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE; + + /* Read next scalar word if needed. */ + uint32_t currentDigitInWordIndex = currentDigitBitIndex % 32u; + if(((uint32_t)currentDigitBitIndex == (scalarBitLength - 4u)) || (currentDigitInWordIndex == (32u - MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE))) + { + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t currentScalarWordIndex = currentDigitBitIndex / 32u; + currentScalarWord = pScalar[currentScalarWordIndex]; + MCUX_CSSL_FP_BRANCH_POSITIVE(ifInWhile); + } + + /* Call point doubling routine defined by pPointDoubleFct to compute P = 2*P */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_DoubleFct, pPointDoubleFctFP->pPointDoubleFct()); + + /* Call pointer selection routine specified by pPtrSelectFct to set TWED_PP_VX0, TWED_PP_VY0 and TWED_PP_VT0 + * to the buffers storing the X-, Y- and T-coordinates of PP. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_PtrSelectFct, pPtrSelectFctFP->pPtrSelectFct(pSession, currentScalarWord, currentDigitInWordIndex)); + + /* Call mixed point addition routine defined by pMixedPointAddFct to compute P = P + PP. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_MixedAddFct, pMixedPointAddFctFP->pMixedPointAddFct()); + + if((MCUXCLECC_STATUS_OK != ret_DoubleFct) || (MCUXCLECC_STATUS_OK != ret_PtrSelectFct) || (MCUXCLECC_STATUS_OK != ret_MixedAddFct)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_FixScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* FP balancing for the loop iteration */ + MCUX_CSSL_FP_LOOP_ITERATION(whileLoop, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(ifInWhile, + (currentDigitBitIndex == (scalarBitLength - 1u)) || (currentDigitInWordIndex == (32u - MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE))), + pPointDoubleFctFP->pointDoubleFct_FP_FuncId, + pPtrSelectFctFP->ptrSelectFct_FP_FuncId, + pMixedPointAddFctFP->mixedPointAddFct_FP_FuncId + ); + } + + /* + * Step 6: Restore the original scalar and negate the resulting point if needed. + */ + if(0u == scalarLsb) + { + MCUXCLPKC_FP_CALC_OP1_SUB(iScalar, ECC_N, iScalar); + MCUXCLPKC_FP_CALC_MC1_MS(TWED_X, ECC_P, TWED_X, ECC_PS); + } + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_FixScalarMult, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((0u == scalarLsb), + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_RecodeAndReorderScalar), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLECC_TWED_FIXSCALARMULT_NOOFPRECPOINTS * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PrecPointImportAndValidate), + MCUX_CSSL_FP_LOOP_ITERATIONS(whileLoop, (scalarBitLength / MCUXCLECC_TWED_FIXSCALARMULT_DIGITSIZE)), + MCUX_CSSL_FP_CONDITIONAL((0u == scalarLsb), + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.c new file mode 100644 index 000000000..a3d3a520d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.c @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.c + * @brief Edwards curve plain scalar point multiplication for curve 25519 + */ + + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* MISRA Ex. 20 - Rule 5.1 */ +static const mcuxClEcc_TwEd_PointDoubleFunction_FP_t mcuxClEcc_TwEd_PointDoubleEd25519_FP = { + .pPointDoubleFct = mcuxClEcc_TwEd_PointDoubleEd25519, + .pointDoubleFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PointDoubleEd25519), +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +static const mcuxClEcc_TwEd_MixedPointAddFunction_FP_t mcuxClEcc_TwEd_MixedPointAddEd25519_FP = { + .pMixedPointAddFct = mcuxClEcc_TwEd_MixedPointAddEd25519, + .mixedPointAddFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_MixedPointAddEd25519), +}; + +/* MISRA Ex. 20 - Rule 5.1 */ +static const mcuxClEcc_TwEd_PtrSelectFunction_FP_t mcuxClEcc_TwEd_PlainPtrSelectComb_FP = { + .pPtrSelectFct = mcuxClEcc_TwEd_PlainPtrSelectComb, + .ptrSelectFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PlainPtrSelectComb), +}; + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEcc_TwEd_PlainFixScalarMult25519, mcuxClEcc_ScalarMultFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainFixScalarMult25519( + mcuxClSession_Handle_t pSession, ///< [in] pSession Handle for the current CL session + mcuxClEcc_CommonDomainParams_t *pDomainParams, ///< [in] pDomainParams Pointer to ECC common domain parameters structure + uint8_t iScalar, ///< [in] iScalar Pointer table index of secret scalar lambda + uint32_t scalarBitLength, ///< [in] scalarBitLength Bit length of the scalar; must be a multiple of 4 + uint32_t options ///< [in] options Parameter to pass options +) +{ + (void) pSession; + (void) options; + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PlainFixScalarMult25519); + + MCUX_CSSL_FP_FUNCTION_CALL(returnScalarMult, mcuxClEcc_TwEd_FixScalarMult(pSession, + pDomainParams, + iScalar, + scalarBitLength, + &mcuxClEcc_TwEd_MixedPointAddEd25519_FP, + &mcuxClEcc_TwEd_PointDoubleEd25519_FP, + &mcuxClEcc_TwEd_PlainPtrSelectComb_FP + ) + ); + + if(MCUXCLECC_STATUS_OK != returnScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainFixScalarMult25519, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainFixScalarMult25519, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_FixScalarMult) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectComb.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectComb.c new file mode 100644 index 000000000..f87bc30c4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectComb.c @@ -0,0 +1,90 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c + * @brief Function to import, convert and validate the coordinates of a pre-computed point + */ + +#include +#include +#include +#include + +#include +#include +#include + + +/** + * For a given 4 bit scalar digit (i3 i2 i1 i0)_2, this function sets TWED_PP_VX0 to the buffer + * storing the X-coordinate of PP = P_{(i3 i2 i1)_2 ^ (i0 i0 i0)_2 ^ (1 1 1)_2} and + * - if i0 = 1, sets TWED_PP_VY0 and TWED_PP_VT0 to the buffers storing the Y- and T-coordinates of PP. + * - if i0 = 0, sets TWED_PP_VY0 and TWED_PP_VT0 to buffers ECC_T2 and ECC_T3 and store the negative Y- + * and T-coordinates of PP in buffers ECC_T2 and ECC_T3. + * + * The function is not implemented to protect against side-channel attacks. + * + * Parameters: + * - pSession Handle for the current CL session + * - scalarWord CPU word containing the digit (i3 i2 i1 i0)_2 + * - scalarDigitOffset Bit offset in scalarWord of the digit (i3 i2 i1 i0)_2 + * + * Prerequisites: + * - ps1Len = (operandSize, operandSize) + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - Virtual pointers TWED_PP_VX0, TWED_PP_VY0 and TWED_PP_VT0 as well as buffers ECC_T2 and ECC_T3 are prepared as described above. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_PlainPtrSelectComb, mcuxClEcc_TwEd_PtrSelectFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainPtrSelectComb( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint32_t scalarWord, + uint8_t scalarDigitOffset +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PlainPtrSelectComb); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + + /* Step 1: Derive digit (i3 i2 i1 i0)_2 from scalarWord. */ + uint32_t nibble = (scalarWord >> scalarDigitOffset) & MCUXCLECC_TWED_FIXSCALARMULT_DIGITMASK; + + /* Step 2: Derive table index tiX of buffer storing the X-coordinate of PP = P_{(i3 i2 i1)_2 ^ (i0 i0 i0)_2 ^ (1 1 1)_2}. */ + uint32_t tiX = TWED_PP_X0 + 3u * ( ((nibble & 0xEu)>>1) ^ (7u * (nibble & 0x1u)) ^ (0x7u)); + + /* Step 3: Set virtual pointers TWED_PP_VX0, TWED_PP_VY0 and TWED_PP_VT0 to the pointer table entries with indices tiX, tiX+1 and tiX+2. */ + MCUXCLPKC_WAITFORREADY(); + pOperands[TWED_PP_VX0] = (uint16_t) pOperands[tiX]; + pOperands[TWED_PP_VY0] = (uint16_t) pOperands[tiX + 1u]; + pOperands[TWED_PP_VT0] = (uint16_t) pOperands[tiX + 2u]; + + if(0u == (nibble & 0x1u)) + { + /* Step 4: If i0 == 0: + * - Compute ECC_T2 = ECC_P - TWED_PP_VX0 and ECC_T3 = ECC_P - TWED_PP_VT0. + * - Set virtual pointers TWED_PP_VX0 and TWED_PP_VT0 to buffers ECC_T2 and ECC_T3. */ + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_T2, ECC_P, TWED_PP_VX0); + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_T3, ECC_P, TWED_PP_VT0); + pOperands[TWED_PP_VX0] = (uint16_t) pOperands[ECC_T2]; + pOperands[TWED_PP_VT0] = (uint16_t) pOperands[ECC_T3]; + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainPtrSelectComb, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL(0u == (nibble & 0x1u), + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectML.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectML.c new file mode 100644 index 000000000..e423a94c3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainPtrSelectML.c @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PlainPtrSelectML.c + * @brief Function to set the virtual pointers of coordinates of accumulated ladder points + * to be used by the upcoming Montgomery Ladder step depending on the current scalar bit b + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +/** + * Plain pointer selection function + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_PlainPtrSelectML, mcuxClEcc_TwEd_PtrSelectFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainPtrSelectML( + mcuxClSession_Handle_t pSession, + uint32_t scalarWord, + uint8_t scalarBitOffset +) +{ + (void)pSession; + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PlainPtrSelectML); + + /* Select bit b */ + uint32_t b = (scalarWord >> scalarBitOffset) & 0x01u; + + /* Select the pointers for the accumulated Montgomery ladder points. + * As TWED_ML_Y1, ... TWED_ML_Z2 are four consecutive offsets in the UPTR table, the selection of + * (TWED_ML_Y1, TWED_ML_Z1) or (TWED_ML_Y2, TWED_ML_Z2) can be done based on the value of the bit b, + * to achieve the following: + * if (1u == b) + * { + * pOperands[TWED_VY1] = pOperands[TWED_ML_Y2]; + * pOperands[TWED_VZ1] = pOperands[TWED_ML_Z2]; + * pOperands[TWED_VY2] = pOperands[TWED_ML_Y1]; + * pOperands[TWED_VZ2] = pOperands[TWED_ML_Z1]; + * } + * else + * { + * pOperands[TWED_VY1] = pOperands[TWED_ML_Y1]; + * pOperands[TWED_VZ1] = pOperands[TWED_ML_Z1]; + * pOperands[TWED_VY2] = pOperands[TWED_ML_Y2]; + * pOperands[TWED_VZ2] = pOperands[TWED_ML_Z2]; + * }; + */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + uint32_t offsets_VY1_VZ1 = pOperands32[(TWED_ML_Y1 / 2u) + b]; + uint32_t offsets_VY2_VZ2 = pOperands32[(TWED_ML_Y2 / 2u) - b]; + + MCUXCLPKC_WAITFORREADY(); + + MCUXCLECC_STORE_2OFFSETS(pOperands32, TWED_VY1, TWED_VZ1, offsets_VY1_VZ1); + MCUXCLECC_STORE_2OFFSETS(pOperands32, TWED_VY2, TWED_VZ2, offsets_VY2_VZ2); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainPtrSelectML, MCUXCLECC_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainVarScalarMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainVarScalarMult.c new file mode 100644 index 000000000..a033a2032 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PlainVarScalarMult.c @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PlainVarScalarMult.c + * @brief Plain scalar multiplication with a variable point P on a twisted Edwards curve + */ + +#include +#include +#include + +#include +#include +#include + +static const mcuxClEcc_TwEd_PtrSelectFunction_FP_t mcuxClEcc_TwEd_PlainPtrSelectML_FP = { + .pPtrSelectFct = mcuxClEcc_TwEd_PlainPtrSelectML, + .ptrSelectFct_FP_FuncId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_PlainPtrSelectML), +}; + +/** + * Function that performs a scalar multiplication with a variable point P on a twisted Edwards curve, unprotected against SCA. + * This function is a wrapper to mcuxClEcc_TwEd_VarScalarMult. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_PlainVarScalarMult, mcuxClEcc_ScalarMultFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PlainVarScalarMult( + mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pDomainParams, + uint8_t iScalar, + uint32_t scalarBitLength, + uint32_t options +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PlainVarScalarMult); + + MCUX_CSSL_FP_FUNCTION_CALL(returnScalarMult, + mcuxClEcc_TwEd_VarScalarMult(pSession, pDomainParams, iScalar, scalarBitLength, options, &mcuxClEcc_TwEd_PlainPtrSelectML_FP)); + + if(MCUXCLECC_STATUS_OK != returnScalarMult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainVarScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PlainVarScalarMult, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_TwEd_VarScalarMult) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.c new file mode 100644 index 000000000..c7ef0e151 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.c @@ -0,0 +1,102 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.c + * @brief Edwards curve internal point arithmetic for curve Ed25519 + */ + + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * This function implements a point doubling on Ed25519 in extended homogeneous coordinates. + * More precisely, given a point P = (X:Y:Z:T) in extended homogeneous coordinates it calculates + * 2*P = (Xres:Yres:Zres:Tres) according to the algorithm specified in Section 3.3 of + * https://eprint.iacr.org/2008/522.pdf with a = -1. + * + * Input: + * - pSession Handle for the current CL session + * + * Prerequisites: + * - Buffers TWED_X, TWED_Y, TWED_Z and TWED_T contain the homogeneous coordinates (X:Y:Z:T) of P in MR + * - ps1Len = (operandSize, operandSize) + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - The resulting coordinates (Xres:Yres:Zres:Tres) are stored in buffers TWED_X, TWED_Y, TWED_Z and TWED_T in MR. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_PointDoubleEd25519, mcuxClEcc_TwEd_PointDoubleFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PointDoubleEd25519(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PointDoubleEd25519); + + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_TwEd_PointDoubleEd25519, mcuxClEcc_FUP_TwEd_PointDoubleEd25519_Len); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PointDoubleEd25519, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); +} + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * This function implements a unified mixed extended point addition on Ed25519. + * More precisely, given a point P1 = (X1:Y1:Z1:T1) in extended homogeneous + * coordinates and a point P2 = (X2:Y2:1:T2) in extended affine coordinates, + * it calculates the sum P1 + P2 in extended homogeneous coordinates + * P1 = (Xres:Yres:Zres:Tres). To this end the a = -1 specific algorithm specified + * in Section 3.1 of https://eprint.iacr.org/2008/522.pdf is used with Z2 = 1. + * + * Input: + * - pSession Handle for the current CL session + * + * Prerequisites: + * - Buffers TWED_X, TWED_Y, TWED_Z and TWED_T contain the homogeneous coordinates (X1:Y1:Z1:T1) of P1 in MR + * - Pointers TWED_PP_VX0, TWED_PP_VY0 and TWED_PP_VT0 point to the coordinates X2, Y2 and T2 in MR. + * - ps1Len = (operandSize, operandSize) + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - The resulting coordinates (Xres:Yres:Zres:Tres) are stored in buffers TWED_X, TWED_Y, TWED_Z and TWED_T in MR. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_MixedPointAddEd25519, mcuxClEcc_TwEd_MixedPointAddFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_MixedPointAddEd25519(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_MixedPointAddEd25519); + + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_TwEd_MixedPointAddEd25519, mcuxClEcc_FUP_TwEd_MixedPointAddEd25519_Len); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_MixedPointAddEd25519, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.c new file mode 100644 index 000000000..e8d6e5bbf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.c @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_FUP.c + * @brief mcuxClEcc: FUP programs used in ECC functions for Twisted Edwards curve Ed25519 + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_MixedPointAddEd25519[19] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xd8u,0x3fu,0xd1u,0x4cu},{0x80u,0x00u,0x23u,0x0fu,0x00u,0x19u},{0x80u,0x00u,0x13u,0x19u,0x00u,0x1fu},{0x80u,0x21u,0x10u,0x1fu,0x1fu,0x1fu},{0x80u,0x21u,0x10u,0x0eu,0x0du,0x23u},{0x80u,0x2au,0x10u,0x0eu,0x0du,0x1du},{0x80u,0x21u,0x10u,0x21u,0x20u,0x19u},{0x80u,0x2au,0x10u,0x21u,0x20u,0x21u},{0x80u,0x00u,0x19u,0x23u,0x00u,0x1bu},{0x80u,0x00u,0x21u,0x1du,0x00u,0x19u},{0x80u,0x21u,0x10u,0x22u,0x22u,0x22u},{0x80u,0x2au,0x10u,0x1bu,0x19u,0x1du},{0x80u,0x21u,0x10u,0x1bu,0x19u,0x19u},{0x80u,0x2au,0x10u,0x22u,0x1fu,0x1bu},{0x80u,0x21u,0x10u,0x22u,0x1fu,0x1fu},{0x80u,0x00u,0x1du,0x1bu,0x00u,0x20u},{0x80u,0x00u,0x1fu,0x19u,0x00u,0x21u},{0x80u,0x00u,0x1du,0x19u,0x00u,0x23u},{0x80u,0x00u,0x1bu,0x1fu,0x00u,0x22u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointDoubleEd25519[16] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x6eu,0x03u,0x54u,0xcbu},{0x80u,0x00u,0x20u,0x20u,0x00u,0x19u},{0x80u,0x00u,0x21u,0x21u,0x00u,0x1bu},{0x80u,0x00u,0x22u,0x22u,0x00u,0x1du},{0x80u,0x21u,0x10u,0x1du,0x1du,0x1du},{0x80u,0x21u,0x10u,0x21u,0x20u,0x23u},{0x80u,0x00u,0x23u,0x23u,0x00u,0x1fu},{0x80u,0x21u,0x10u,0x19u,0x1bu,0x23u},{0x80u,0x2au,0x10u,0x1fu,0x23u,0x1fu},{0x80u,0x2au,0x10u,0x1bu,0x19u,0x19u},{0x80u,0x2au,0x10u,0x19u,0x1du,0x1du},{0x80u,0x2au,0x10u,0x10u,0x23u,0x1bu},{0x80u,0x00u,0x1fu,0x1du,0x00u,0x20u},{0x80u,0x00u,0x19u,0x1bu,0x00u,0x21u},{0x80u,0x00u,0x1fu,0x1bu,0x00u,0x23u},{0x80u,0x00u,0x1du,0x19u,0x00u,0x22u}}; + + + +/* FUP program: perform point doubling on Ed25519 in extended homogeneous */ +/* coordinates. */ +/* Prerequisites: */ +/* - Buffers TWED_X, TWED_Y, TWED_Z and TWED_T contain the homogeneous */ +/* coordinates (X:Y:Z:T) of P in MR */ +/* - ps1Len = (operandSize, operandSize) */ +/* - Buffer ECC_PFULL contains p'||p */ +/* - Buffer ECC_PS contains the shifted modulus associated to p */ +/* Result: */ +/* - The resulting coordinates (Xres:Yres:Zres:Tres) are stored in buffers */ +/* TWED_X, TWED_Y, TWED_Z and TWED_T in MR. */ + + +/* FUP program: perform unified mixed extended point addition on Ed25519 */ +/* Prerequisites: */ +/* - Buffers TWED_X, TWED_Y, TWED_Z and TWED_T contain the homogeneous */ +/* coordinates (X1:Y1:Z1:T1) of P1 in MR */ +/* - Pointers TWED_PP_VX0, TWED_PP_VY0 and TWED_PP_VT0 point to the */ +/* coordinates X2, Y2 and T2 in MR. */ +/* - ps1Len = (operandSize, operandSize) */ +/* - Buffer ECC_PFULL contains p'||p */ +/* - Buffer ECC_PS contains the shifted modulus associated to p */ +/* Result: */ +/* - The resulting coordinates (Xres:Yres:Zres:Tres) are stored in buffers */ +/* TWED_X, TWED_Y, TWED_Z and TWED_T in MR. */ + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.c new file mode 100644 index 000000000..26c79eec7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.c @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.c + * @brief FUP programs used in ECC functions for Twisted Edwards curve Ed25519 + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointSubtraction[22] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x88u,0x80u,0xb5u,0xf0u},{0x80u,0x2au,0x10u,0x10u,0x20u,0x20u},{0x80u,0x00u,0x3bu,0x22u,0x00u,0x18u},{0x80u,0x00u,0x18u,0x18u,0x00u,0x19u},{0x80u,0x00u,0x39u,0x20u,0x00u,0x1au},{0x80u,0x00u,0x3au,0x21u,0x00u,0x1bu},{0x80u,0x00u,0x1au,0x1bu,0x00u,0x1cu},{0x80u,0x00u,0x13u,0x1cu,0x00u,0x1eu},{0x80u,0x2au,0x10u,0x19u,0x1eu,0x1du},{0x80u,0x21u,0x10u,0x19u,0x1eu,0x19u},{0x80u,0x21u,0x10u,0x39u,0x3au,0x1cu},{0x80u,0x21u,0x10u,0x20u,0x21u,0x1eu},{0x80u,0x00u,0x1cu,0x1eu,0x00u,0x1fu},{0x80u,0x2au,0x10u,0x1fu,0x1au,0x1cu},{0x80u,0x2au,0x10u,0x1cu,0x1bu,0x1cu},{0x80u,0x00u,0x18u,0x1du,0x00u,0x1eu},{0x80u,0x00u,0x1eu,0x1cu,0x00u,0x20u},{0x80u,0x00u,0x12u,0x1au,0x00u,0x1cu},{0x80u,0x2au,0x10u,0x1bu,0x1cu,0x1bu},{0x80u,0x00u,0x18u,0x19u,0x00u,0x1au},{0x80u,0x00u,0x1au,0x1bu,0x00u,0x21u},{0x80u,0x00u,0x1du,0x19u,0x00u,0x22u}}; + + + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") +/** + * FUP program to do point subtraction P1 - P2. + * The source for algorithm used for addition is: + * 2008 Bernstein--Birkner--Joye--Lange--Peters http://eprint.iacr.org/2008/013 Section 6 + * + * Prerequisites: + * - TWED_PP_X7 contains the X-coordinate of point P1 + * - TWED_PP_Y7 contains the Y-coordinate of point P1 + * - TWED_PP_T7 contains the Z-coordinate of point P1 + * - TWED_X contains the X-coordinate of point P2 + * - TWED_Y contains the Y-coordinate of point P2 + * - TWED_Z contains the Z-coordinate of point P2 + * - ECC_CP0 contains domain parameter a + * + * Result: + * - Buffers TWED_X, TWED_Y, TWED_Z contain the result (X:Y:Z) in MR + */ +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointValidation_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointValidation_FUP.c new file mode 100644 index 000000000..db7f0177c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PointValidation_FUP.c @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PointValidation_FUP.c + * @brief mcuxClEcc: FUP programs used in ECC functions for Twisted Edwards curves + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_TwEd_PointValidation[14] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x67u,0xe4u,0x10u,0x75u},{0x80u,0x00u,0x04u,0x04u,0x00u,0x19u},{0x80u,0x00u,0x05u,0x05u,0x00u,0x1bu},{0x80u,0x00u,0x04u,0x05u,0x00u,0x06u},{0x80u,0x2au,0x00u,0x06u,0x00u,0x06u},{0x80u,0x00u,0x12u,0x19u,0x00u,0x1du},{0x80u,0x21u,0x10u,0x1du,0x1bu,0x1du},{0x80u,0x00u,0x13u,0x19u,0x00u,0x1fu},{0x80u,0x00u,0x1fu,0x1bu,0x00u,0x19u},{0x80u,0x2au,0x10u,0x1du,0x19u,0x1du},{0x00u,0x09u,0x00u,0x00u,0x00u,0x1fu},{0x80u,0x2au,0x10u,0x1du,0x1fu,0x1du},{0x80u,0x33u,0x1du,0x00u,0x00u,0x1fu},{0x80u,0x2au,0x00u,0x1fu,0x00u,0x1fu}}; + + + +/* FUP program: calculate curve equation for given point */ +/* Prerequisites: */ +/* Input: P = (x,y) in (TWED_V0,TWED_V1); */ +/* Output: ECC_T3 = 0 if input point is a valid point */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c new file mode 100644 index 000000000..7644a8350 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c @@ -0,0 +1,92 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.c + * @brief Function to import, convert and validate the coordinates of a pre-computed point + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/** + * This function imports the affine coordinates (x,y) of a pre-computed point to the PKC workarea, + * converts them to extended affine coordinates (x:y:1:t) in MR and in range [0,p-1] and verifies + * that the point lies on the curve. + * + * Input: + * - pSession Handle for the current CL session + * - iDst Pointer table index of buffer to which the x-coordinate shall be copied + * - pSrc Pointer to the pre-computed point x-coordinate + * + * Prerequisites: + * - The coordinates x and y are stored in MR (in LE format) concatenated at address pSrc + * - ps1Len = (operandSize, operandSize) + * - Buffers ECC_CP0 and ECC_CP1 contain the curve parameters a and d in MR + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + * + * Result: + * - Buffers buf(iDst), buf(iDst+1) and buf(iDst+2) contain the coordinates x, y and t in MR + * + * Return values: + * - MCUXCLECC_STATUS_OK if the function executed successfully + * - MCUXCLECC_STATUS_FAULT_ATTACK if the point validation failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_PrecPointImportAndValidate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_PrecPointImportAndValidate( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint8_t iDst, + uint8_t *pSrc, + uint16_t byteLenP +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_PrecPointImportAndValidate); + + /* Step 1: Copy the coordinates x and y to the buffers buf(iDst) and buf(iDst+1). */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUXCLPKC_WAITFORFINISH(); + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[iDst]), pSrc, byteLenP); + MCUXCLMEMORY_FP_MEMORY_COPY(MCUXCLPKC_OFFSET2PTR(pOperands[iDst+1u]), pSrc+byteLenP, byteLenP); + + /* Step 2: Let pointer table pointers corresponding to TWED_V0, TWED_V1 and TWED_V2 point to buf(iDst), buf(iDst+1) and buf(iDst+2). */ + pOperands[TWED_V0] = (uint16_t) pOperands[iDst]; + pOperands[TWED_V1] = (uint16_t) pOperands[iDst+1u]; + pOperands[TWED_V2] = (uint16_t) pOperands[iDst+2u]; + + /* Step 3: Validate the coordinates by checking the curve equation a*x2 + y2 = 1 + d*x2*y2: */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_TwEd_PointValidation, mcuxClEcc_FUP_TwEd_PointValidation_Len); + + /* Step 4: If the ZERO flag of the PKC is not set, return #MCUXCLECC_STATUS_FAULT_ATTACK. Otherwise, return #MCUXCLECC_STATUS_OK. */ + if (MCUXCLPKC_FLAG_ZERO != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PrecPointImportAndValidate, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_PrecPointImportAndValidate, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); + } +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult.c new file mode 100644 index 000000000..7cee054f7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult.c @@ -0,0 +1,146 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_VarScalarMult.c + * @brief Scalar multiplication with a variable point P on a twisted Edwards curve + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + * Function that performs a scalar multiplication with a variable point P on a twisted Edwards curve + * + * Prerequisites: + * - Buffer buf(iScalar) contains the secret scalar lambda of bit length scalarBitLength + * - Buffers TWED_X, TWED_Y and TWED_Z contain the homogeneous coordinates (X:Y:Z) of P in MR + * - Buffer ECC_CP1 contains d in MR + * - ps1Len = (operandSize, operandSize) + * - Buffer ECC_PFULL contains p'||p + * - Buffer ECC_PS contains the shifted modulus associated to p + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_TwEd_VarScalarMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_TwEd_VarScalarMult( + mcuxClSession_Handle_t pSession, + mcuxClEcc_CommonDomainParams_t *pDomainParams, + uint8_t iScalar, + uint32_t scalarBitLength, + uint32_t options, + const mcuxClEcc_TwEd_PtrSelectFunction_FP_t *pPtrSelectFctFP +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_TwEd_VarScalarMult); + + /* Determine pointer table pointer */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy - TODO CLNS-6410: check if this is necessary + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - PKC word is CPU word aligned."); + const uint32_t *pScalar = (const uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[iScalar]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + + /* Step 1: Initialize the accumulated points in YZ-coordinates */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(TWED_ML_Y1, TWED_Z, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(TWED_ML_Z1, TWED_Z, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(TWED_ML_Y2, TWED_Y, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(TWED_ML_Z2, TWED_Z, 0u); + + /* Step 2: Import ladder constant (a/d mod p), convert it to MR modulo p, and store it in buffer ECC_CP0. */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t byteLenP = (uint32_t) pDomainParams->byteLenP; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pDomainParams->pLadderConst, byteLenP); + MCUXCLPKC_FP_CALC_MC1_MM(ECC_CP0, ECC_T0, ECC_PQSQR, ECC_P); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS("Links are allowed in comments.") + /* Step 3: Perform ladder loop to calculate YZ-coordinates for the resulting point according to Algorithms 4 and 5 in https://ieeexplore.ieee.org/document/6550581 + * For the pointer selection, the function specified by pPtrSelectFctFP is used. + */ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() + uint32_t i = scalarBitLength; + uint32_t currentScalarWord = 0u; + MCUX_CSSL_FP_LOOP_DECL(whileLoop); + MCUX_CSSL_FP_BRANCH_DECL(ifInWhile); + while(0u < i) + { + /* Update loop counter, deviation from the design to let iterate over unsigned value */ + --i; + + /* Select pointers pOperands[TWED_VY1],...,pOperands[TWED_VZ2] according to the bit to be processed */ + uint32_t currentScalarBitInWord = i % 32u; + if((i == (scalarBitLength - 1u)) || ((i % 32u) == 31u)) + { + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t currentScalarWordIndex = i / 32u; + currentScalarWord = pScalar[currentScalarWordIndex]; + MCUX_CSSL_FP_BRANCH_POSITIVE(ifInWhile); + } + MCUX_CSSL_FP_FUNCTION_CALL(ret_PtrSelectFct, pPtrSelectFctFP->pPtrSelectFct(pSession, currentScalarWord, (uint8_t)currentScalarBitInWord)); + if(MCUXCLECC_STATUS_OK != ret_PtrSelectFct) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_VarScalarMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Perform the ladder step to calculate (VY2:VZ2) = (VY1:VZ1) + (VY2:VZ2) and (VY1:VZ1) = 2*(VY1:VZ1) */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep, mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep_LEN); + + /* FP balancing for the loop iteration */ + MCUX_CSSL_FP_LOOP_ITERATION(whileLoop, + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(ifInWhile, (i == (scalarBitLength - 1u)) || ((i % 32u) == 31u)), + pPtrSelectFctFP->ptrSelectFct_FP_FuncId, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); + } + + /* Step 4: Import curve parameter a, convert it to MR modulo p, and store it in buffer ECC_CP0. */ + MCUXCLPKC_WAITFORFINISH(); + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pDomainParams->pCurveParam1, byteLenP); + MCUXCLPKC_FP_CALC_MC1_MM(ECC_CP0, ECC_T0, ECC_PQSQR, ECC_P); + + /* Step 5: Recover the missing X-coordinate */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate, mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate_LEN); + + /* Step 6: If requested, convert the result to affine coordinates */ + if(MCUXCLECC_SCALARMULT_OPTION_AFFINE_OUTPUT == (MCUXCLECC_SCALARMULT_OPTION_OUTPUT_MASK & options)) + { + MCUXCLMATH_FP_MODINV(ECC_T0, TWED_Z, ECC_P, ECC_T1); /* T0 = Z^(-1)*R^(-1) mod p */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_ConvertHomToAffine, mcuxClEcc_FUP_ConvertHomToAffine_LEN); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_TwEd_VarScalarMult, MCUXCLECC_STATUS_OK, + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_LOOP_ITERATIONS(whileLoop, scalarBitLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLECC_SCALARMULT_OPTION_AFFINE_OUTPUT == (MCUXCLECC_SCALARMULT_OPTION_OUTPUT_MASK & options)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.c new file mode 100644 index 000000000..7ee9404e9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.c @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.c + * @brief mcuxClEcc: FUP programs for implementation of scalar multiplication with a variable point P on a twisted Edwards curve + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_Recover_X_Coordinate[15] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xffu,0x36u,0x4cu,0x27u},{0x80u,0x00u,0x21u,0x24u,0x00u,0x19u},{0x80u,0x00u,0x22u,0x25u,0x00u,0x1bu},{0x80u,0x00u,0x19u,0x26u,0x00u,0x1du},{0x80u,0x00u,0x1bu,0x27u,0x00u,0x1fu},{0x80u,0x00u,0x12u,0x1fu,0x00u,0x21u},{0x80u,0x00u,0x13u,0x1du,0x00u,0x22u},{0x80u,0x2au,0x10u,0x21u,0x22u,0x1du},{0x80u,0x00u,0x20u,0x1du,0x00u,0x1fu},{0x80u,0x00u,0x24u,0x1fu,0x00u,0x21u},{0x80u,0x00u,0x25u,0x1fu,0x00u,0x22u},{0x80u,0x00u,0x19u,0x27u,0x00u,0x1du},{0x80u,0x00u,0x1bu,0x26u,0x00u,0x1fu},{0x80u,0x2au,0x10u,0x1du,0x1fu,0x1du},{0x80u,0x00u,0x1bu,0x1du,0x00u,0x20u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_VarScalarMult_YZMontLadder_LadderStep[29] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x63u,0xb7u,0xc2u,0xc2u},{0x80u,0x00u,0x0eu,0x0du,0x00u,0x19u},{0x80u,0x00u,0x0fu,0x0cu,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x0fu},{0x80u,0x21u,0x10u,0x1bu,0x19u,0x1bu},{0x80u,0x00u,0x19u,0x19u,0x00u,0x0eu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x19u},{0x80u,0x21u,0x10u,0x0fu,0x0eu,0x0fu},{0x80u,0x2au,0x10u,0x19u,0x0fu,0x19u},{0x80u,0x00u,0x21u,0x0fu,0x00u,0x0eu},{0x80u,0x00u,0x19u,0x22u,0x00u,0x1bu},{0x80u,0x2au,0x10u,0x1bu,0x0eu,0x0eu},{0x80u,0x00u,0x21u,0x19u,0x00u,0x1bu},{0x80u,0x00u,0x0fu,0x22u,0x00u,0x19u},{0x80u,0x2au,0x10u,0x19u,0x1bu,0x0fu},{0x80u,0x00u,0x0cu,0x0cu,0x00u,0x1bu},{0x80u,0x00u,0x0du,0x0du,0x00u,0x19u},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x0cu},{0x80u,0x2au,0x10u,0x1bu,0x19u,0x1bu},{0x80u,0x00u,0x19u,0x19u,0x00u,0x0du},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x19u},{0x80u,0x2au,0x10u,0x19u,0x0cu,0x19u},{0x80u,0x2au,0x10u,0x0du,0x19u,0x0du},{0x80u,0x00u,0x12u,0x19u,0x00u,0x1bu},{0x80u,0x21u,0x10u,0x0cu,0x1bu,0x0cu},{0x80u,0x2au,0x10u,0x10u,0x0du,0x1bu},{0x80u,0x00u,0x12u,0x1bu,0x00u,0x19u},{0x80u,0x2au,0x10u,0x0cu,0x19u,0x1bu},{0x80u,0x2au,0x10u,0x0du,0x1bu,0x0du}}; + + + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.c new file mode 100644 index 000000000..a0a25487b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.c @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.c + * @brief Implementation of the custom key type constructor. + */ + + +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_WeierECC_GenerateCustomKeyType) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateCustomKeyType( + mcuxClKey_CustomType_t customType, + mcuxClKey_AlgorithmId_t algoId, + mcuxClKey_Size_t size, + void *pCustomParams) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_WeierECC_GenerateCustomKeyType); + + /* Extract algo and usage specifiers from the algoId */ + const uint32_t algoSpecifier = (uint32_t) algoId & MCUXCLKEY_ALGO_ID_ALGO_MASK; + const uint32_t usageSpecifier = (uint32_t) algoId & MCUXCLKEY_ALGO_ID_USAGE_MASK; + + /* Verify that the algoId is supported. If not, return FAULT_ATTACK */ + if ( (MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM != algoSpecifier) + && (MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM != algoSpecifier) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateCustomKeyType, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + if ( (MCUXCLKEY_ALGO_ID_PUBLIC_KEY != usageSpecifier) + && (MCUXCLKEY_ALGO_ID_PRIVATE_KEY != usageSpecifier) + && (MCUXCLKEY_ALGO_ID_KEY_PAIR != usageSpecifier) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateCustomKeyType, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Fill custom key type descriptor */ + customType->algoId = algoId; + customType->size = size; + customType->info = pCustomParams; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateCustomKeyType, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.c new file mode 100644 index 000000000..a8db4b9e1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams.c @@ -0,0 +1,256 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_GenerateDomainParams.c + * @brief ECC Weierstrass custom domain parameter generation function + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_WeierECC_GenerateDomainParams) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_GenerateDomainParams( + mcuxClSession_Handle_t pSession, + mcuxClEcc_Weier_DomainParams_t *pEccWeierDomainParams, + mcuxClEcc_Weier_BasicDomainParams_t *pEccWeierBasicDomainParams, + uint32_t options) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_WeierECC_GenerateDomainParams); + + /**********************************************************/ + /* Initialization and parameter verification */ + /**********************************************************/ + + /* Get CPU workarea pointers */ + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) (& pSession->cpuWa.buffer[pSession->cpuWa.used]); + + /* Set up the environment. This includes import/calculation of the full moduli p and n incl. their nDash values + * as well as the calculation of R2P. */ + mcuxClEcc_DomainParam_t curveParam; + curveParam.pA = pEccWeierBasicDomainParams->pA; + curveParam.pB = pEccWeierBasicDomainParams->pB; + curveParam.pP = pEccWeierBasicDomainParams->pP; + curveParam.pG = pEccWeierBasicDomainParams->pG; + curveParam.pN = pEccWeierBasicDomainParams->pN; + curveParam.misc = mcuxClEcc_DomainParam_misc_Pack(pEccWeierBasicDomainParams->nLen, pEccWeierBasicDomainParams->pLen); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SetupEnvironment, + mcuxClEcc_Weier_SetupEnvironment(pSession, + &curveParam, + ECC_GENERATEDOMAINPARAMS_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_INVALID_PARAMS == ret_SetupEnvironment) + { + /* Session has been cleaned, PKC has been deinitialized in SetupEnvironment. */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) ); + } + + MCUXCLECC_HANDLE_HW_UNAVAILABLE(ret_SetupEnvironment, mcuxClEcc_WeierECC_GenerateDomainParams); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + + /* Calculate R3N, and then reduce R2N < N and R2P < P. */ + MCUXCLMATH_FP_QDASH(ECC_T3, ECC_NS, ECC_N, ECC_T0, (uint16_t) (2u * operandSize)); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P, + mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P_Len); + + const uint32_t byteLenP = pEccWeierBasicDomainParams->pLen; + const uint32_t byteLenN = pEccWeierBasicDomainParams->nLen; + + /* Import the base point coordinates (x,y) to buffers (ECC_S0,ECC_S1). */ +// MCUXCLPKC_WAITFORFINISH(); <== unnecessary, because buffers ECC_S0/ECC_S1 and offsets ECC_VX0/ECC_VX1 are not used in the FUP, _Reduce_R2N_R2P. + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_S0, pEccWeierBasicDomainParams->pG, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_S1, pEccWeierBasicDomainParams->pG + byteLenP, byteLenP); + + /* Verify correctness of affine coordinates of G in NR. */ + pOperands[WEIER_VX0] = pOperands[ECC_S0]; + pOperands[WEIER_VY0] = pOperands[ECC_S1]; + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckBasePointStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckBasePointStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_INVALID_PARAMS, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_WEIERECC_GENERATEDOMAINPARAMS_INIT_AND_VERIFY, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckBasePointStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + + /**********************************************************/ + /* Optionally, generate the pre-computed point */ + /**********************************************************/ + + if (MCUXCLECC_OPTION_GENERATEPRECPOINT_YES == (options & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK)) + { + /* Convert the affine base point coordinates (x,y) stored in ECC_S0 and ECC_S1 to + * Jacobian coordinates (X:Y:Z=1) in MR and store them in buffers (WEIER_X0,WEIER_Y0,WEIER_Z). + * Also initialize the relative Z-coordinate Z' as 1 in MR and store it in WEIER_ZA. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR, + mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR_Len); + + /* Calculate prec point PrecG = 2^(byteLenN * 4) * G using function mcuxClEcc_RepeatPointDouble. + * Input/output buffers of mcuxClEcc_RepeatPointDouble are set as follows: + * + * Input: + * - ECC_VX2, ECC_VY2, ECC_VZ is set to the Jacobian coordinates (X:Y:Z=1) of the base point in buffers (WEIER_X0,WEIER_Y0,WEIER_Z) + * - ECC_VZ2 is set to the relative Jacobian coordinate Z'=1 stored in WEIER_ZA + * Output: + * - ECC_VX0, ECC_VY0, ECC_VZ0 are set to buffers (WEIER_XA,WEIER_YA,WEIER_ZA) to store the result precG in relative Jacobian coordinates + * Temp: + * - ECC_VT is set to temp buffer ECC_S2 + * + * NOTE: Since the input Z-coordinate is 1 in MR, the resulting relative Jacobian coordinate is in fact the Z-coordinate + * of the result. So, ECC_VX0, ECC_VY0, ECC_VZ0 will effectively contains Jacobian coordinates for precG. */ +// MCUXCLPKC_WAITFORREADY() <== unnecessary, because VX0/VY0/VZ0/VZ/VX2/VY2/VZ2 are not used in the FUP program before. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_XA, WEIER_YA); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VZ0, WEIER_VZ, WEIER_ZA, WEIER_Z); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, WEIER_X0, WEIER_Y0); + pOperands[WEIER_VZ2] = pOperands[WEIER_ZA]; + pOperands[WEIER_VT] = pOperands[ECC_S2]; + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_RepeatPointDouble((byteLenN * 8u) / 2u)); + + /* Convert precG to affine coordinates in NR and store them in (WEIER_X0,WEIER_Y0). */ + MCUXCLMATH_FP_MODINV(ECC_T0, WEIER_ZA, ECC_P, ECC_T1); + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_ConvertJacToAffine, + mcuxClEcc_FUP_Weier_ConvertJacToAffine_LEN); + } + else if (MCUXCLECC_OPTION_GENERATEPRECPOINT_NO != (options & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + + /**********************************************************/ + /* Initialize optimized domain parameters struct at the */ + /* start of target memory area */ + /**********************************************************/ + + /* Interpret start of memory area pEccWeierDomainParams as struct of type mcuxClEcc_Weier_DomainParams_t */ + mcuxClEcc_Weier_DomainParams_t *pDomainParams = (mcuxClEcc_Weier_DomainParams_t *) pEccWeierDomainParams; + + /* Initialize pointers to where the domain parameters shall be stored */ + uint8_t *pDomainParamBuffers = (uint8_t *) pEccWeierDomainParams + sizeof(mcuxClEcc_Weier_DomainParams_t); + pDomainParams->common.pFullModulusP = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_PFULL; + pDomainParams->common.pFullModulusN = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_NFULL(byteLenP); + pDomainParams->common.pR2P = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_R2P(byteLenP, byteLenN); + pDomainParams->common.pR2N = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_R2N(byteLenP, byteLenN); + pDomainParams->common.pCurveParam1 = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_CP1(byteLenP, byteLenN); + pDomainParams->common.pCurveParam2 = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_CP2(byteLenP, byteLenN); + pDomainParams->common.pGx = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_GX(byteLenP, byteLenN); + pDomainParams->common.pGy = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_GY(byteLenP, byteLenN); + pDomainParams->common.pPrecPoints = pDomainParamBuffers + MCUXCLECC_CUSTOMPARAMS_OFFSET_PP(byteLenP, byteLenN); + + + /**********************************************************/ + /* Fill optimized domain parameters */ + /**********************************************************/ + + /* Initialize lengths and function pointers in optimized domain parameter struct */ + pDomainParams->common.byteLenP = (uint16_t) byteLenP; + pDomainParams->common.byteLenN = (uint16_t) byteLenN; + pDomainParams->common.pSecFixScalarMultFctFP = NULL; + pDomainParams->common.pSecVarScalarMultFctFP = NULL; + pDomainParams->common.pPlainFixScalarMultFctFP = NULL; + pDomainParams->common.pPlainVarScalarMultFctFP = NULL; + + /* Export full moduli for p and n to optimized domain parameter struct. */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pFullModulusP, ECC_PFULL, byteLenP + MCUXCLPKC_WORDSIZE); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pFullModulusN, ECC_NFULL, byteLenN + MCUXCLPKC_WORDSIZE); + + /* Export Montgomery parameters R2P and R2N to optimized domain parameter struct. */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pR2P, ECC_PQSQR, byteLenP); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pR2N, ECC_NQSQR, byteLenN); + + /* Copy domain parameters a and b to optimized domain parameter struct. + * + * NOTE: This is done in two steps via imports to/exports from the PKC RAM + * because no ordinary memory copy with endianess reversal exists. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pEccWeierBasicDomainParams->pA, byteLenP); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pCurveParam1, ECC_T0, byteLenP); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pCurveParam2, WEIER_B, byteLenP); + + /* Export base point coordinates to optimized domain parameter struct. */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pGx, ECC_S0, byteLenP); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pGy, ECC_S1, byteLenP); + + if(MCUXCLECC_OPTION_GENERATEPRECPOINT_YES == (options & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK)) + { + /* Optionally, export prec point coordinates to optimized domain parameter struct. */ + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pPrecPoints, WEIER_X0, byteLenP); + MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(pDomainParams->common.pPrecPoints + byteLenP, WEIER_Y0, byteLenP); + } + else if (MCUXCLECC_OPTION_GENERATEPRECPOINT_NO != (options & MCUXCLECC_OPTION_GENERATEPRECPOINT_MASK)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + + /**********************************************************/ + /* Clean up */ + /**********************************************************/ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_WeierECC_GenerateDomainParams, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_WEIERECC_GENERATEDOMAINPARAMS_FINAL(options)); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.c new file mode 100644 index 000000000..2517fb570 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.c @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.c + * @brief FUP programs for Weierstrass domain parameter generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Convert_G_toJacMR[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xa9u,0xb8u,0x80u,0xfeu},{0x00u,0x09u,0x00u,0x00u,0x00u,0x23u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x22u},{0x80u,0x00u,0x18u,0x16u,0x00u,0x24u},{0x80u,0x00u,0x1au,0x16u,0x00u,0x25u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_GenerateDomainParams_Reduce_R2N_R2P[4] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xb3u,0xa5u,0xceu,0x11u},{0x80u,0x33u,0x1fu,0x00u,0x01u,0x17u},{0x80u,0x00u,0x16u,0x16u,0x00u,0x1fu},{0x80u,0x33u,0x1fu,0x00u,0x00u,0x16u}}; + + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +/* FUP program: prepare R2P and R2N strictly smaller than P and N. */ + + +/* FUP program: converts base point G to Jacobian coordinates (X:Y:Z=1) in MR */ +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_SetupEnvironment.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_SetupEnvironment.c new file mode 100644 index 000000000..d5a6d3b37 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_WeierECC_Internal_SetupEnvironment.c @@ -0,0 +1,78 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_WeierECC_Internal_SetupEnvironment.c + * @brief Weierstrass curve internal setup environment + */ + + +#include + +#include +#include +#include +#include + +#include +#include +#include + + +/** + * \brief This function sets up environment used by Weierstrass functions. + * + * On top of generic ECC environment setup function, mcuxClEcc_SetupEnvironment, + * this function further imports the curve coefficients a and b, and converts + * coefficient a into montgomery representation. + * + * Inputs: + * - pSession: pointer to session descriptor; + * - pDomainParams: pointer to Weier domain parameter structure; + * - noOfBuffers: number of buffers in PKC workarea used by calling API. + * + * Results: + * - results of mcuxClEcc_SetupEnvironment; + * - Buffer WEIER_A contains the coefficient a in MR. + * - Buffer WEIER_B contains the coefficient b in NR. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the results. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_WeierECC_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_WeierECC_SetupEnvironment( + mcuxClSession_Handle_t pSession, + mcuxClEcc_Weier_DomainParams_t *pWeierDomainParams, + uint8_t noOfBuffers) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_WeierECC_SetupEnvironment); + + MCUX_CSSL_FP_FUNCTION_CALL(retSetupEnvironment, + mcuxClEcc_SetupEnvironment(pSession, &(pWeierDomainParams->common), noOfBuffers) ); + if (MCUXCLECC_STATUS_OK != retSetupEnvironment) + { + MCUXCLECC_HANDLE_HW_UNAVAILABLE(retSetupEnvironment, mcuxClEcc_WeierECC_SetupEnvironment); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_WeierECC_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Import coefficients a and b, and convert a to MR. */ + uint32_t byteLenP = pWeierDomainParams->common.byteLenP; + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(ECC_T0, pWeierDomainParams->common.pCurveParam1, byteLenP); + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_A, ECC_T0, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(WEIER_B, pWeierDomainParams->common.pCurveParam2, byteLenP); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_WeierECC_SetupEnvironment, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_SetupEnvironment), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportLittleEndianToPkc) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.c new file mode 100644 index 000000000..bd2fda861 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_ConvertPoint_FUP.c @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_ConvertPoint_FUP.c + * @brief FUP program for Weierstrass curve internal point conversion + */ + + +#include +#include +#include + +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePoint_ToJacobian[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x5bu,0xa9u,0x51u,0x00u},{0x80u,0x00u,0x20u,0x16u,0x00u,0x24u},{0x80u,0x00u,0x21u,0x16u,0x00u,0x25u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x23u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x22u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertAffinePointsToJac[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x10u,0x8cu,0x25u,0x66u},{0x80u,0x00u,0x26u,0x16u,0x00u,0x20u},{0x80u,0x00u,0x27u,0x16u,0x00u,0x21u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x22u},{0x80u,0x00u,0x28u,0x16u,0x00u,0x24u},{0x80u,0x00u,0x29u,0x16u,0x00u,0x25u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x23u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertJacToAffine[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x2bu,0xd4u,0x4fu,0x6cu},{0x80u,0x00u,0x19u,0x16u,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x16u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x19u,0x00u,0x1fu},{0x80u,0x00u,0x20u,0x1du,0x00u,0x19u},{0x80u,0x33u,0x19u,0x00u,0x00u,0x24u},{0x80u,0x2au,0x00u,0x24u,0x00u,0x24u},{0x80u,0x00u,0x21u,0x1fu,0x00u,0x19u},{0x80u,0x33u,0x19u,0x00u,0x00u,0x25u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine[11] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xb2u,0xc8u,0x75u,0x8bu},{0x80u,0x00u,0x19u,0x16u,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x16u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x19u,0x00u,0x1fu},{0x80u,0x00u,0x24u,0x1du,0x00u,0x19u},{0x80u,0x00u,0x25u,0x1fu,0x00u,0x1bu},{0x80u,0x33u,0x19u,0x00u,0x00u,0x20u},{0x80u,0x33u,0x1bu,0x00u,0x00u,0x21u},{0x80u,0x2au,0x00u,0x20u,0x00u,0x20u},{0x80u,0x2au,0x00u,0x21u,0x00u,0x21u}}; + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* FUP program: convert points P1 and P2 from affine coordinates */ +/* to Jacobian coordinates in MR */ +/* Input: P1 = (x,y) in NR in (WEIER_X1,WEIER_Y1) */ +/* P2 = (x,y) in NR in (WEIER_X2,WEIER_Y2) */ +/* Output: P1 = (X,Y,Z) in MR in (WEIER_XA,WEIER_YA,WEIER_ZA) */ +/* P2 = (X,Y,Z) in MR in (WEIER_X0,WEIER_Y0,WEIER_Z) */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* FUP program: convert point P from affine coordinates */ +/* to Jacobian coordinates in MR */ +/* Input: P = (x,y) in NR in (XA,YA) */ +/* Output: P = (X,Y,Z) in MR in (WEIER_X0, WEIER_Y0, WEIER_Z) */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* FUP program: convert point P from Jacobian in MR to affine coordinates in NR */ +/* Input: */ +/* P = (X,Y,Z) in (WEIER_XA,WEIER_YA,-), Jacobian coordinates */ +/* ECC_T0 = (z*z')^(-1) * 256^(-LEN), with z is Z coordinate in P relative to z' */ +/* Output: */ +/* P = (x,y) in (WEIER_X0,WEIER_Y0), affine coordinates */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_FUP.c new file mode 100644 index 000000000..ba45b2bb0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_FUP.c @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_FUP.c + * @brief Generic FUP programs for ECC + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_UpdateJacobianCoordinates[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xa7u,0xcfu,0xb1u,0x04u},{0x80u,0x00u,0x22u,0x22u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x22u,0x00u,0x1fu},{0x80u,0x00u,0x24u,0x1du,0x00u,0x26u},{0x80u,0x00u,0x25u,0x1fu,0x00u,0x27u},{0x00u,0x1eu,0x00u,0x23u,0x03u,0x19u},{0x80u,0x00u,0x19u,0x22u,0x00u,0x23u}}; + + + +/* FUP program: update P: (X0,Y0, old Z) -> (X1,Y1, new Z) Jacobian; */ +/* update z = z * z'. */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen.c new file mode 100644 index 000000000..c17c4152c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen.c @@ -0,0 +1,278 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_KeyGen.c + * @brief Weierstrass curve internal key generation + */ + + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK +#define MCUXCLECC_FP_WEIER_KEYGEN_SECSTRENGTH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) +#else +#define MCUXCLECC_FP_WEIER_KEYGEN_SECSTRENGTH (0u) +#endif + + +/** + * This function implements secure ECDSA private key / ephemeral key generation, + * according to FIPS 186-4. It outputs multiplicative split d0 and d1 as well as d, + * satisfying d0*d1 mod n = d = (c mod (n-1)) + 1, in which d is the private key + * derived from a (bitLen(n)+64)-bit true (DRBG) random number c and d0 is a 64-bit + * random number (with bit 63 set). + * + * Inputs: + * nByteLength: byte length of n (base point order). + * + * Inputs in pOperands[] and PKC workarea: N/A. + * + * Prerequisites: + * ps1Len = (operandSize, operandSize); + * curve order n in N, NDash of n in NFULL; + * no on-going calculation on N; + * buffers S1, S2 and S3 are with doubled-size (2*operandSize). + * + * Result in PKC workarea: + * buffers S0 and S1 contain multiplicative split private key d0 and d1 (operandSize); + * buffer S3 contains a random value usable for blinding operations of size opLen. + * + * Other modifications: + * buffers T0, XA, YA, ZA and Z are modified (as temp, buffer size); + * buffers S1, S2 and S3 are modified (as temp, double buffer size); + * offsets pOperands[VT] is modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Int_CoreKeyGen) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Int_CoreKeyGen(mcuxClSession_Handle_t pSession, + uint32_t nByteLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Int_CoreKeyGen, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST ); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + const uint32_t mcLen_opLen = MCUXCLPKC_PS1_GETLENGTH_REG(); + const uint32_t opLen = MCUXCLPKC_PS1_UNPACK_OPLEN(mcLen_opLen); + + /* Count leading zeros in most significant word of n. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - PKC word is CPU word aligned."); + const uint32_t *ptr32N = (const uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[ECC_N]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + const uint32_t wordNumN = (nByteLength + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t nMSWord = ptr32N[wordNumN - 1u]; + uint32_t nMSWord_LeadZeros = mcuxClMath_CountLeadingZerosWord(nMSWord); + uint32_t bitLenN65 = (wordNumN * (sizeof(uint32_t)) * 8u) - nMSWord_LeadZeros + 65u; + uint32_t pkcByteLenN65 = (bitLenN65 + (MCUXCLPKC_WORDSIZE * 8u) - 1u) / (MCUXCLPKC_WORDSIZE * 8u) * MCUXCLPKC_WORDSIZE; + + /* Clear buffer S0. */ + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_S0, 0u); + + /* Clear buffer S3, with OPLEN = pkcByteLenN65. */ +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS2 after submitting a PS1 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS2_SETLENGTH(0u, pkcByteLenN65); + MCUXCLPKC_FP_CALC_OP2_CONST(ECC_S3, 0u); + + + /**********************************************************/ + /* Step 1: generate 64-bit random d0, (MSb set); */ + /* compute v = ModInv(d0) = d0^(-1) mod n. */ + /**********************************************************/ + + /* Generate S0 = 64-bit random d0, with PRNG. */ + uint8_t *ptrS0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S0]); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_GetRandom_d0, mcuxClRandom_ncGenerate(pSession, ptrS0, 8u)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_GetRandom_d0) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Int_CoreKeyGen, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate) ); + } + + /* Set MSBit of d0 (to ensure d0 != 0) using the PKC. + * + * NOTES: + * - PKC PS1 can be used, because operandSize >= 64. + * - The LSWord of S3 has already been cleared above */ + uint32_t *ptr32S3 = MCUXCLPKC_OFFSET2PTRWORD(pOperands[ECC_S3]); + ptr32S3[1] = 0x80000000u; + MCUXCLPKC_FP_CALC_OP1_OR(ECC_S0, ECC_S0, ECC_S3); + + + /**********************************************************/ + /* Step 2: generate (bitLenN+64)-bit DRBG random seed c. */ + /* a. c is in a buffer of size, pkcSize(bitLenN+65). */ + /**********************************************************/ + + /* Prepare buffer S2 for key seed: Initialize it with PRNG data and clear garbage bytes */ + uint8_t *ptrS2 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S2]); + const uint32_t keySeedLength = (wordNumN * (sizeof(uint32_t))) + 8u; + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); + MCUXCLMEMORY_FP_MEMORY_CLEAR(&ptrS2[keySeedLength], pkcByteLenN65 - keySeedLength); + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_GetRandom_InitKeySeed, mcuxClRandom_ncGenerate(pSession, ptrS2, keySeedLength)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_GetRandom_InitKeySeed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Int_CoreKeyGen, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + } + + /* Derive the security strength required for the RNG from bitLenN / 2 and check whether it can be provided. */ +#ifdef MCUXCL_FEATURE_ECC_STRENGTH_CHECK + MCUX_CSSL_FP_FUNCTION_CALL(ret_checkSecurityStrength, mcuxClRandom_checkSecurityStrength(pSession, MCUXCLECC_MIN((nByteLength * 8u) / 2u, 256u))); + if (MCUXCLRANDOM_STATUS_OK != ret_checkSecurityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Int_CoreKeyGen, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) ); + } +#endif + + /* Generate (wordNumN * 4 + 8)-byte random c with DRBG in buffer S2. */ + MCUXCLECC_FP_RANDOM_HQRNG_PKCWA(mcuxClEcc_Int_CoreKeyGen, pSession, ptrS2, keySeedLength); + + + /**********************************************************/ + /* Step 3: generate (bitLenN+64)-bit PRNG random number r;*/ + /* compute c' = c + r. */ + /* a. OPLEN = pkcSize(bitLenN+65 bit). */ + /**********************************************************/ + + /* S3 = (wordNumN * 4 + 8)-byte random r, with PRNG. */ + uint8_t *ptrS3 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S3]); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_GetRandom_r, mcuxClRandom_ncGenerate(pSession, ptrS3, (wordNumN * (sizeof(uint32_t))) + 8u)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_GetRandom_r) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Int_CoreKeyGen, MCUXCLECC_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLECC_FP_WEIER_KEYGEN_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate) ); + } + + /* Step 3: Truncate c and r to (bitLenN + 64)-bit, with OPLEN = pkcByteLenN65. */ + /* S2 = c' = c + r, the result fits in (bitLenN+65) bits, with OPLEN = pkcByteLenN65. */ + /* ZA = d0, duplicate because ModInv(d0) will destroy input d0. */ + /* Step 4: Z = n-1. */ + pOperands[WEIER_VT] = (uint16_t) nMSWord_LeadZeros; + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34, + mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34_LEN); + + /* T0 = v = ModInv(d0), with temp S1. */ + MCUXCLMATH_FP_MODINV(ECC_T0, WEIER_ZA, ECC_N, ECC_S1); + + /* Now, S0 = d0 (opLen), T0 = v (opLen), Z = n-1 (opLen), */ + /* S2 = c' (pkcByteLenN65), S3 = r (pkcByteLenN65). */ + + + /**********************************************************/ + /* Step 4: use ReduceModEven to compute: */ + /* s = r mod (n-1); */ + /* c" = c' mod (n-1) = (c+s) mod (n-1). */ + /* a. ReduceModEven guarantees the result is < (n-1). */ + /**********************************************************/ + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenN65, opLen); + + /* S1 = c" = ReduceModEven(c', n-1). */ + MCUXCLMATH_FP_REDUCEMODEVEN(ECC_S1, ECC_S2, WEIER_Z, WEIER_XA, ECC_S1, WEIER_YA, WEIER_ZA); + /* S2 = s = ReduceModEven(r, n-1). */ + MCUXCLMATH_FP_REDUCEMODEVEN(ECC_S2, ECC_S3, WEIER_Z, WEIER_XA, ECC_S2, WEIER_YA, WEIER_ZA); + + + /**********************************************************/ + /* Step 5: compute d' = (v*c") - (v*s) mod (v*(n-1)), */ + /* = v * (c mod (n-1)). */ + /* a. 3 plain multiplications (PM): */ + /* MCLEN = OPLEN = opLen, RLEN = 2 * opLen; */ + /* b. modular subtraction (MS): OPLEN = 2 * opLen. */ + /**********************************************************/ + + /**********************************************************/ + /* Step 6: compute d" = d' + v, */ + /* = v * ((c mod (n-1)) + 1) = v * d. */ + /* a. plain addition (ADD): OPLEN = 2 * opLen; */ + /* b. v shall be prepared in buffer of size, 2*opLen. */ + /**********************************************************/ + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH_REG(mcLen_opLen); /* MCLEN = OPLEN = opLen. */ + MCUXCLPKC_PS2_SETLENGTH(0u, opLen * 2u); + + /* Step 5: S2 = d' = (v*c") - (v*s) mod (v*(n-1)); */ + /* S3 = v * s, as another random number. */ + /* Step 6: S2 = d" = d' + v. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56, + mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56_LEN); + + + /**********************************************************/ + /* Step 7: compute d1 = d" mod n < n. */ + /* a. length of d" is (2 * opLen). */ + /**********************************************************/ + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(opLen * 2u, opLen); + + /* Step 7: S1 = d1 = (d" mod n) < n. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_CoreKeyGen_Step7, + mcuxClEcc_FUP_Weier_CoreKeyGen_Step7_LEN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Int_CoreKeyGen, MCUXCLECC_STATUS_OK, + /* Step 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_OR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + /* Step 2 */ + MCUXCLECC_FP_WEIER_KEYGEN_SECSTRENGTH, + MCUXCLECC_FP_CALLED_RANDOM_HQRNG_PKCWA, + /* Step 3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + /* Step 4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ReduceModEven), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ReduceModEven), + /* Steps 5/6 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + /* Steps 7 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen_FUP.c new file mode 100644 index 000000000..e56536b2e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_KeyGen_FUP.c @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_KeyGen_FUP.c + * @brief FUP programs for Weierstrass curve internal key generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Step7[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x62u,0x21u,0x9du,0xacu},{0xc0u,0x00u,0x1cu,0x17u,0x01u,0x1au},{0x80u,0x00u,0x1au,0x17u,0x01u,0x19u},{0x80u,0x33u,0x19u,0x00u,0x01u,0x1au},{0x80u,0x2au,0x01u,0x1au,0x01u,0x1au}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps34[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x40u,0x0au,0x51u,0xe6u},{0x40u,0x15u,0x00u,0x1cu,0x0fu,0x1cu},{0x40u,0x15u,0x00u,0x1eu,0x0fu,0x1eu},{0x40u,0x0au,0x00u,0x1cu,0x1eu,0x1cu},{0x00u,0x1eu,0x00u,0x18u,0x03u,0x22u},{0x00u,0x1bu,0x00u,0x01u,0x02u,0x23u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoreKeyGen_Steps56[8] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x1du,0x72u,0x02u,0x10u},{0x80u,0x13u,0x19u,0x1cu,0x00u,0x1eu},{0x80u,0x13u,0x19u,0x1au,0x00u,0x1cu},{0x80u,0x13u,0x19u,0x23u,0x00u,0x1au},{0xc0u,0x2au,0x1au,0x1cu,0x1eu,0x1cu},{0x40u,0x3eu,0x00u,0x00u,0x03u,0x1au},{0x00u,0x1eu,0x00u,0x19u,0x03u,0x1au},{0x40u,0x0au,0x00u,0x1cu,0x1au,0x1cu}}; + + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +/* Prerequisites: VT = number of bit(s) to be truncated; */ + + + + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic.c new file mode 100644 index 000000000..be715d7f6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic.c @@ -0,0 +1,190 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointArithmetic.c + * @brief Weierstrass curve internal point arithmetic + */ + + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/** + * This function implements repeated point doubling, R = 2^(iteration) * P. + * + * Input: + * iteration: the iteration number of doubling. + * + * Inputs in pOperands[] and PKC workarea: + * buffers (VX2,VY2, VZ2) contain input P, relative-z; + * buffer VZ contains z coordinate. + * + * Prerequisites: + * **CAUTION** VT is the 5th temp buffer (different from T0/T1/T2/T3); + * ps1Len = (operandSize, operandSize); + * buffer WEIER_A contains curve coefficient a, Montgomery representation; + * curve order p in P, NDash of p in PFULL, shifted modulus of p in PS. + * + * Result in PKC workarea: + * buffers (VX0,VY0, VZ0) contain result R, relative-z (w.r.t. z). + * + * Other modifications: + * buffers VT, T0, T1, T2 and T3 are modified (as temp); + * offsets pOperands[VX2/VY2/VZ2] are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_RepeatPointDouble) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClEcc_RepeatPointDouble(uint32_t iteration) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_RepeatPointDouble); + + if (1u == iteration) + { + /* Only 1 iteration: init/double. */ + MCUXCLECC_FP_CALCFUP_ONE_DOUBLE(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClEcc_RepeatPointDouble, + MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE ); + } + + /* The 1st iteration: init/double/update. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_RepeatDouble, + mcuxClEcc_FUP_Weier_RepeatDouble_Len); + + /* Switch to in-place. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, WEIER_VX0, WEIER_VY0); + pOperands[WEIER_VZ2] = pOperands[WEIER_VZ0]; + + uint32_t remIter = iteration - 1u; + MCUX_CSSL_FP_LOOP_DECL(Doublings); + while(remIter > 1u) + { + MCUX_CSSL_FP_LOOP_ITERATION(Doublings, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + + /* Iterations in between: double/update. */ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_RepeatDouble, mcuxClEcc_FUP_Weier_RepeatDouble_Len1, + mcuxClEcc_FUP_Weier_RepeatDouble_Len2 + mcuxClEcc_FUP_Weier_RepeatDouble_Len3); + remIter--; + } + + /* The last iteration: only double. */ + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_RepeatDouble, mcuxClEcc_FUP_Weier_RepeatDouble_Len1, + mcuxClEcc_FUP_Weier_RepeatDouble_Len2); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClEcc_RepeatPointDouble, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_LOOP_ITERATIONS(Doublings, iteration - 2u), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} + + +/** This function calculates point addition, ... + * @retval #MCUXCLECC_STATUS_OK if the result is not the neutral point; + * @retval #MCUXCLECC_STATUS_NEUTRAL_POINT if the result is the neutral point. + * + * Inputs in pOperands[] and PKC workarea: + * buffers (VX0,VY0, VZ0) contain P0, relative-z; + * buffers (VX1,VY1, VZ) contain P1, Jacobian. + * + * Prerequisites: + * **CAUTION** VT is the 5th temp buffer (different from T0/T1/T2/T3); + * ps1Len = (operandSize, operandSize); + * buffer VA contains curve coefficient a, Montgomery representation; + * curve order p in P, NDash of p in PFULL, shifted modulus of p in PS. + * + * Result in PKC workarea: + * buffers (VX0,VY0, VZ0) contain result P0+P1, relative-z, if the result is not the neutral point. + * + * Other modifications: + * buffers VT, T0, T1, T2 and T3 are modified (as temp); + * offsets pOperands[VT2/VT3/VX2/VY2] are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_PointFullAdd) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointFullAdd(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_PointFullAdd, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + MCUXCLPKC_WAITFORREADY(); + + /* Convert P1: (VX1,VY1, VZ) Jacobain -> P2: (T2,T3, VZ0) relative-z. */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VT2, WEIER_VT3, ECC_T2, ECC_T3); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_DoubleAdd, mcuxClEcc_FUP_Weier_DoubleAdd_Len1); + + /* Check if P0.x != P2.x. */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T1, WEIER_VX0, WEIER_VT2, ECC_PS); // t1 = P0.x - P2.x + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T0, ECC_T1, ECC_P); // t0 = P0.x - P2.x in NR in range [0, p] + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T0, ECC_T0, ECC_P, ECC_P); // t0 in range [0, p-1] + if (MCUXCLPKC_FLAG_ZERO != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { /* Addition */ + + /* Calculate P1 + P2 in (VX0,VY0, VZ0) relative-z. */ + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_DoubleAdd, mcuxClEcc_FUP_Weier_DoubleAdd_Len1, + mcuxClEcc_FUP_Weier_DoubleAdd_Len2); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointFullAdd, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + } + + /* Check if P0.y == - P2.y. */ + MCUXCLPKC_FP_CALC_MC1_MA(ECC_T1, WEIER_VY0, WEIER_VT3, ECC_PS); // t1 = P0.x + P2.x + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T0, ECC_T1, ECC_P); // t0 = P0.x + P2.x in NR in range [0,p] + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T0, ECC_T0, ECC_P, ECC_P); // t0 in range [0, p-1] + if (MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) + { /* Neutral point */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointFullAdd, MCUXCLECC_STATUS_NEUTRAL_POINT, + MCUXCLPKC_FP_CALLED_CALC_MC1_MA, + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + } + + /* Calculate 2*P0 in (VX0,VY0, VZ0) relative-z. */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, WEIER_VX0, WEIER_VY0); + MCUXCLECC_FP_CALCFUP_ONE_DOUBLE(); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointFullAdd, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_CALC_MC1_MA, + MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.c new file mode 100644 index 000000000..2ef5aff68 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointArithmetic_FUP.c @@ -0,0 +1,51 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointArithmetic_FUP.c + * @brief FUP programs for Weierstrass curve internal point arithmetic + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_DoubleAdd[20] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xebu,0x2fu,0xf2u,0x80u},{0x80u,0x00u,0x06u,0x06u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x06u,0x00u,0x1bu},{0x80u,0x00u,0x08u,0x19u,0x00u,0x0au},{0x80u,0x00u,0x09u,0x1bu,0x00u,0x0bu},{0x10u,0x00u,0x7bu,0xb3u,0xe5u,0xc3u},{0x80u,0x2au,0x10u,0x05u,0x0bu,0x1bu},{0x80u,0x2au,0x10u,0x04u,0x0au,0x0bu},{0x80u,0x00u,0x06u,0x0bu,0x00u,0x19u},{0x00u,0x1eu,0x00u,0x19u,0x03u,0x06u},{0x80u,0x00u,0x0bu,0x0bu,0x00u,0x19u},{0x80u,0x00u,0x04u,0x19u,0x00u,0x0au},{0x80u,0x00u,0x19u,0x0bu,0x00u,0x04u},{0x80u,0x00u,0x05u,0x04u,0x00u,0x0bu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x19u},{0x81u,0x2au,0x10u,0x04u,0x0au,0x04u},{0x80u,0x21u,0x10u,0x04u,0x19u,0x04u},{0x80u,0x2au,0x10u,0x0au,0x04u,0x05u},{0x80u,0x00u,0x05u,0x1bu,0x00u,0x19u},{0x80u,0x2au,0x10u,0x19u,0x0bu,0x05u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_RepeatDouble[24] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x95u,0xa1u,0x06u,0xe4u},{0x80u,0x00u,0x0eu,0x07u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x0fu},{0x80u,0x00u,0x0fu,0x0fu,0x00u,0x19u},{0x80u,0x00u,0x12u,0x19u,0x00u,0x0fu},{0x10u,0x00u,0x1cu,0x0du,0xf9u,0x90u},{0x80u,0x00u,0x0cu,0x0cu,0x00u,0x1bu},{0x80u,0x21u,0x10u,0x0fu,0x1bu,0x19u},{0x81u,0x21u,0x10u,0x19u,0x1bu,0x19u},{0x80u,0x21u,0x10u,0x0du,0x0du,0x1bu},{0x80u,0x00u,0x1bu,0x0eu,0x00u,0x1du},{0x00u,0x1eu,0x00u,0x1du,0x03u,0x06u},{0x80u,0x00u,0x1bu,0x0du,0x00u,0x1du},{0x80u,0x21u,0x10u,0x1du,0x1du,0x1bu},{0x80u,0x00u,0x0cu,0x1bu,0x00u,0x1fu},{0x80u,0x00u,0x19u,0x19u,0x00u,0x04u},{0x81u,0x2au,0x10u,0x04u,0x1fu,0x04u},{0x80u,0x2au,0x10u,0x1fu,0x04u,0x1fu},{0x80u,0x00u,0x19u,0x1fu,0x00u,0x05u},{0x80u,0x00u,0x1bu,0x1du,0x00u,0x19u},{0x80u,0x2au,0x10u,0x05u,0x19u,0x05u},{0x10u,0x00u,0x7eu,0x91u,0x25u,0x10u},{0x80u,0x21u,0x10u,0x0fu,0x0fu,0x1bu},{0x80u,0x00u,0x19u,0x1bu,0x00u,0x0fu}}; + + + +/* FUP program: repeated point doubling. */ +/* Prerequisites: **CAUTION** the 5th temp VT is assigned; */ +/* coefficient a (in MR) is stored in buffer A. */ +/* Input: P = (x,y, z') in (VX2,VY2, VZ2), relative-z; */ +/* zRef is stored in buffer VZ. */ +/* Output: P_Dbl = 2P in (VX0,VY0, VZ0), relative-z, */ +/* supporting result in-place. */ + + +/* FUP program: point doubling-addition with mix-coordinates. */ +/* Input: */ +/* P0 = (x0,y0, z') in (VX0,VY0, VZ0), relative-z; */ +/* P1 = (x1,y1, z) in (VX1,VY1, unused), Jacobian. */ +/* Output: */ +/* (1 iteration) */ +/* P'0 := P1 + P0 in relative-z, and */ +/* P0 will be updated (according to new z') and stored in (VT2,VT3). */ +/* (2 iterations, skip the first 4 operations in the 2nd iteration) */ +/* P"0 := P1 + 2*P0 in relative-z. */ +/* P'0 / P"0 will be stored in (VX0,VY0, VZ0), always result in-place. */ +/* Attention: */ +/* 1. P0 != +/- P1, avoid doubling and O (point at infinity); */ +/* 2. VT2 and VT3 are different buffers from VX0/VY0/VZ0/VX1/VY1. */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck.c new file mode 100644 index 000000000..3fa7ea2f3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck.c @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointCheck.c + * @brief Weierstrass curve internal point check + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include + + +/** + * This function checks a point, if y^2 == x^3 + a*x + b (mod p). + * @retval #MCUXCLECC_STATUS_OK + * @retval #MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK + * @retval #MCUXCLECC_STATUS_FAULT_ATTACK + * + * Inputs in pOperands[] and PKC workarea: + * buffers (VX0,VY0) contain the point, affine, normal representation. + * + * Prerequisites: + * buffer WEIER_A contains curve coefficient a, Montgomery representation; + * buffer WEIER_B contains curve coefficient b, normal representation; + * ps1Len = (operandSize, operandSize); + * curve order p in P, NDash of p in PFULL, + * shifted modulus of p in PS, QSquare of p in PQSQR. + * + * Result in PKC workarea: + * buffer T0 contains (- y^2 + x^3 + a*x + b) mod p, in the range [0, p-1]. + * + * Other modifications: + * buffers T1 and T2 are modified (as temp). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_PointCheckAffineNR) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointCheckAffineNR(void) + +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_PointCheckAffineNR); + + /* Calculate t0 = (- y^2 + x^3 + ax + b) mod p. */ + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_PointCheckAffNR, + mcuxClEcc_FUP_Weier_PointCheckAffNR_LEN); + + /* Check: if t0 != 0. */ + if (MCUXCLPKC_FLAG_NONZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointCheckAffineNR, MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + } + + /* Check (2nd): if t0 == 0. */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(ECC_T1, ECC_T0, 1u); + if (MCUXCLPKC_FLAG_CARRY == MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointCheckAffineNR, MCUXCLECC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST ); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointCheckAffineNR, MCUXCLECC_STATUS_FAULT_ATTACK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck_FUP.c new file mode 100644 index 000000000..d7690232c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointCheck_FUP.c @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointCheck_FUP.c + * @brief FUP program for Weierstrass curve internal point check + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointCheckAffNR[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x21u,0x93u,0x5bu,0xc3u},{0x80u,0x00u,0x04u,0x16u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1bu},{0x80u,0x21u,0x10u,0x1bu,0x12u,0x1bu},{0x80u,0x00u,0x19u,0x1bu,0x00u,0x1du},{0x80u,0x00u,0x05u,0x16u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x19u,0x00u,0x1bu},{0x80u,0x2au,0x10u,0x1bu,0x1du,0x1bu},{0x80u,0x33u,0x1bu,0x00u,0x00u,0x19u},{0x80u,0x2au,0x00u,0x13u,0x19u,0x19u}}; + + + +/* FUP program: calculate (- y^2 + x^3 + a*x + b) mod p. */ +/* Input: (x,y) in (VX0,VY0), affine, normal representation. */ +/* Output: (- y^2 + x^3 + a*x + b) mod p in T0, in the range [0, p-1]. */ diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointMult.c new file mode 100644 index 000000000..14577a397 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_PointMult.c @@ -0,0 +1,194 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_PointMult.c + * @brief Weierstrass curve internal point multiplication + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include + + +/** + * This function implements (non-secure) point scalar multiplication, R = scalar * P. + * + * Inputs: + * iScalar: index of PKC buffer storing the scalar, which is + * in little-endian, non-zero and interleaved; + * scalarBitLength: bit length of scalar. + * + * Inputs in pOperands[] and PKC workarea: + * Prec1 = P, in (X1,Y1, Z) Jacobian; + * Prec2 = PrecP, in (X2,Y2, Z) Jacobian; + * Prec3 = P + PrecP, in (X3,Y3, Z) Jacobian. + * + * Prerequisites: + * **CAUTION** VT is the 5th temp buffer (different from T0/T1/T2/T3); + * ps1Len = (operandSize, operandSize); + * buffer VA contains curve coefficient a, Montgomery representation; + * curve order p in P, NDash of p in PFULL, shifted modulus of p in PS. + * + * Result in PKC workarea: + * buffers (XA,YA, ZA) contain result R, relative-z (w.r.t. Z). + * + * Other modifications: + * buffers VT, T0, T1, T2 and T3 are modified (as temp); + * offsets pOperands[VT2/VT3/VX0/VY0/VZ0/VZ/VX1/VY1/VX2/VY2/VZ2] are modified. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Int_PointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClEcc_Int_PointMult(uint8_t iScalar, uint32_t scalarBitLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Int_PointMult); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - PKC word is CPU word aligned."); + const uint32_t *pScalar = (const uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[iScalar]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + + uint32_t scalarWord; + uint32_t scalarBits; + uint32_t index = scalarBitLength; + + /* Scan scalar and skip leading zero bits. */ + MCUX_CSSL_FP_LOOP_DECL(PointMult_Double); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + do + { + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Double); /* trivial double */ + + index -= 2u; + scalarWord = pScalar[index / 32u]; + scalarBits = (scalarWord >> (index & 31u)) & 0x3u; + } while (0u == scalarBits); /* assume scalar is non-zero. */ + + /* Prepare offsets to coordinates of Prec_i. */ + uint32_t offsets_VY_VX = pOperands32[(WEIER_X1 / 2u) - 1u + scalarBits]; + /* Prepare offsets to coordinates of R. */ + uint32_t offsets_VYA_VXA = MCUXCLECC_LOAD_2OFFSETS(pOperands32, WEIER_XA, WEIER_YA); + + /* Initialize z' = 1 in MR. */ + MCUXCLPKC_FP_CALC_OP1_NEG(WEIER_ZA, ECC_P); + + /* Select Prec_i by updating (VX2, VY2). */ +// MCUXCLPKC_WAITFORREADY(); <== unnecessary, because VX2 and VY2 are not used in previous computation. + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, offsets_VY_VX); + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t NoOfAdd = 0u); + + MCUX_CSSL_FP_LOOP_DECL(PointMult_Add); + if (0u == index) + { + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Add, /* trivial add */ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST ); + MCUX_CSSL_FP_COUNTER_STMT(NoOfAdd += 1u); + + /* Copy, R = Prec_i. */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(WEIER_XA, WEIER_VX2, 0u); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(WEIER_YA, WEIER_VY2, 0u); + } + else + { + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Double, + MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE ); + + /* Set offsets to buffers for FUPs: RepeatDouble and DoubleAdd. */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VT2, WEIER_VT3, ECC_T2, ECC_T3); /* temp for FUP DoubleAdd */ + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, offsets_VYA_VXA); /* result for both FUPs */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VZ0, WEIER_VZ, WEIER_ZA, WEIER_Z); /* input(DoubleAdd)/output(both FUPs): z' in ZA; input(RepeatDouble): zRef in Z */ + pOperands[WEIER_VZ2] = pOperands[WEIER_ZA]; /* input: z' in ZA, for FUP RepeatDouble */ + + /* Double, R = 2 * Prec_i, where Prec_i is selected by (VX2, VY2). */ + MCUXCLECC_FP_CALCFUP_ONE_DOUBLE(); + + index -= 2u; + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + scalarWord = pScalar[index / 32u]; + scalarBits = (scalarWord >> (index & 31u)) & 0x3u; + + /* Set VX2/VY2 to calculate R = 2 * R in the remaining iterations. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, offsets_VYA_VXA); + + /* Point addition (optional) */ + if (0u != scalarBits) + { + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Add, + MCUXCLECC_FP_CALLED_CALCFUP_ADD_ONLY ); + MCUX_CSSL_FP_COUNTER_STMT(NoOfAdd += 1u); + + /* Select Prec_i by updating (VX1, VY1) according to scalarBits. */ + offsets_VY_VX = pOperands32[(WEIER_X1 / 2u) - 1u + scalarBits]; + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, offsets_VY_VX); + + /* Add, R = R + Prec_i. */ + MCUXCLECC_FP_CALCFUP_ADD_ONLY(); + } + } + + /* Point double and addition (not always) of the remaining iteration(s). */ + while (0u != index) + { + index -= 2u; + if (0x1Eu == (index & 0x1Fu)) + { + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + scalarWord = pScalar[index / 32u]; + } + scalarBits = (scalarWord >> (index & 0x1Fu)) & 0x3u; + + if (0u == scalarBits) + { /* Double only */ + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Double, + MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE ); + + /* Calculate: R = 2R. */ + MCUXCLECC_FP_CALCFUP_ONE_DOUBLE(); + } + else + { /* Double and Add */ + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Double); + MCUX_CSSL_FP_LOOP_ITERATION(PointMult_Add, + MCUXCLECC_FP_CALLED_CALCFUP_DOUBLE_ADD ); + MCUX_CSSL_FP_COUNTER_STMT(NoOfAdd += 1u); + + /* Select Prec_i by updating (VX1, VY1) according to scalarBits. */ + offsets_VY_VX = pOperands32[(WEIER_X1 / 2u) - 1u + scalarBits]; + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, offsets_VY_VX); + + /* Calculate: R = 2R + Prec_i. */ + MCUXCLECC_FP_CALCFUP_DOUBLE_ADD(); + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClEcc_Int_PointMult, + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, + MCUX_CSSL_FP_LOOP_ITERATIONS(PointMult_Double, scalarBitLength / 2u), + MCUX_CSSL_FP_LOOP_ITERATIONS(PointMult_Add, NoOfAdd) ); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.c new file mode 100644 index 000000000..9c88a3387 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.c @@ -0,0 +1,272 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.c + * @brief Weierstrass curve internal secure point multiplication + */ + + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +/** This function implements secure point scalar multiplication, R = scalar * P, based on Co-Z Montgomery ladder. + * + * Inputs: + * pSession: pointer to mcuxClSession_Descriptor. + * iScalar: index of PKC buffer storing the scalar, which is non-zero and in little-endian; + * scalarBitLength: bit length of scalar. + * + * Inputs in pOperands[] and PKC workarea: + * P in (X0,Y0, Z) Jacobian. + * + * Prerequisites: + * buffer VA contains curve coefficient a, Montgomery representation; + * ps1Len = (operandSize, operandSize); + * curve order p in P, NDash of p in PFULL, shifted modulus of p in PS. + * + * Result in PKC workarea: + * buffers (X0,Y0, Z) contain result R, Jacobian. + * + * Other modifications: + * buffers T0, T1, T2 and T3 are modified (as temp); + * buffers ZA, X1 and Y1 are modified; + * offsets pOperands[VX0/VY0/VZ0/VZ/VX1/VY1/VX2/VY2/VZ2/VT] are modified; + * pOperands[X0/Y0/X1/Y1] and location of corresponding buffers are randomized. + * + * @attention The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_SecurePointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_SecurePointMult(mcuxClSession_Handle_t pSession, + uint8_t iScalar, + uint32_t scalarBitLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_SecurePointMult, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG, + MCUXCLECC_FP_CALLED_CALCFUP_ONE_DOUBLE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("MISRA Ex. 9 to Rule 11.3 - PKC word is CPU word aligned."); + const uint32_t *pScalar = (const uint32_t *) MCUXCLPKC_OFFSET2PTR(pOperands[iScalar]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING(); + + /** + * Step 1: Randomize input point P coordinates (X0, Y0, Z) + */ + + /* Generate a randomized relative Z-coordinate in ZA */ + uint8_t *pZA = MCUXCLPKC_OFFSET2PTR(pOperands[WEIER_ZA]); + uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom0, mcuxClRandom_ncGenerate(pSession, pZA, operandSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_Prng_GetRandom0) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* Reduce ZA modulo p, update the Z-coordinate and update the coordinates of P0 to the new Z-coordinate */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1, + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN1 /* PrepareZ */ + + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN2); /* UpdateZ and P0 */ + + + /** + * Step 2: Skip leading scalar zeros and read and XOR-mask first non-zero scalar word + */ + + /* Initialize scalar word shares variables and generate XOR-mask for the first non-zero scalar word */ + uint32_t scalarBitIndex = scalarBitLength - 1u; + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint32_t scalarWord0 = pScalar[scalarBitIndex / 32u]; + uint32_t scalarWord1; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandWord, mcuxClRandom_ncGenerate(pSession, (uint8_t*)&scalarWord1, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Prng_GetRandWord) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* Scan scalar and skip leading zero bits. */ + while (0u == scalarWord0) + { + scalarBitIndex -= 32u; + scalarWord0 = pScalar[scalarBitIndex / 32u]; + } + scalarBitIndex = (scalarBitIndex | 31u) - mcuxClMath_CountLeadingZerosWord(scalarWord0); /* bit position of most significant non-zero bit */ + scalarWord0 ^= scalarWord1; + + + /** + * Step 3: Prepare accumulated ladder points R0 (X0, Y0, Z) and R1 (X1, Y1, Z) and ensure that their + * X- and Y-coordinates are in range [0,p-1], a prerequisite for each ladder step. + */ + + /* Initialize z' = 1 in MR. */ + MCUXCLPKC_FP_CALC_OP1_NEG(WEIER_ZA, ECC_P); + + /* Calculate R1 = P + P = 2*R0 */ + /* Input: R0 in (X0,Y0, ZA=1) relative-Z (w.r.t. ZRef in Z) */ + /* Output: R1 in (X1,Y1, ZA) relative-Z */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); /* R1 */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VZ0, WEIER_VZ, WEIER_ZA, WEIER_Z); /* R1.z and ZRef */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, WEIER_X0, WEIER_Y0); /* R0 */ + pOperands[WEIER_VZ2] = pOperands[WEIER_ZA]; /* R0.z */ + pOperands[WEIER_VT] = pOperands[ECC_T3]; /* 5th temp */ + MCUXCLECC_FP_CALCFUP_ONE_DOUBLE(); + + /* Ensure that X1 and Y1 are in range [0,p-1] as a prerequisite for the scalar multiplication loop. + * Also ensure ZA < p as a prerequisite for the upcoming coordinate update*/ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP, mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP_LEN); + + /* Update z = z * z', so R1: (X1,Y1, ZA) relative-z -> (X1,Y1, Z) Jacobian. + * Update Jacobian coordinates in MR of R0 (X0,Y0, Z). + * + * NOTE: Since ZA < p before the FUP program, the same holds for X0 and Y0 after the FUP program + * which is a prerequisite for the scalar multiplication loop */ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1, + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN1, /* Skip the first part (PrepareZA) */ + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN2); /* Only UpdateZ and P0 */ + + + /** + * Step 4: Execute Montgomery ladder to process the remaining scalar words and compute the result + * + * NOTES: + * - It is ensured that before and after every ladder step the X- and Y-coordinates of the accumulated points are in range [0,p-1]. + * This shall help to avoid side-channel leakage. + * - For every new scalar word, the coordinates of the accumulated points are re-randomized with a fresh random Z-coordinate and + * also buffers are shuffled + */ + + /* FP balance here, to avoid keeping another copy of scalarBitIndex. */ + MCUX_CSSL_FP_LOOP_DECL(MainLoop); + MCUX_CSSL_FP_LOOP_DECL(RandomizeInMainLoop); /* This needs to be declared outside the loop. */ + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_LOOP_ITERATIONS(MainLoop, scalarBitIndex), + MCUX_CSSL_FP_LOOP_ITERATIONS(RandomizeInMainLoop, scalarBitIndex/32u) ); + + /* The remaining iteration(s) of Montgomery ladder. */ + while (0u != scalarBitIndex) + { + MCUX_CSSL_FP_LOOP_ITERATION(MainLoop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + + scalarBitIndex -= 1u; + uint32_t bitOffset = scalarBitIndex & 0x1Fu; + if (0x1Fu == bitOffset) + { + MCUX_CSSL_FP_LOOP_ITERATION(RandomizeInMainLoop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ReRandomizeUPTRT), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate) ); + + /* Randomize offsets UPTRT XA/YA/ZA/Z/X0/Y0/X1/Y1. */ + /* (pkcwa order is changed accordingly) */ + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(retReRandomUptrt, + mcuxClPkc_ReRandomizeUPTRT(pSession, + &pOperands[WEIER_XA], + (uint16_t) operandSize, + (WEIER_Y1 - WEIER_XA + 1u)) ); + if (MCUXCLPKC_STATUS_OK != retReRandomUptrt) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* After rerandomization, pointer pZA (used in mcuxClRandom_ncGenerate call) */ + /* and pOperands[WEIER_VZ] (used by double-and-add FUP program) need to be updated. */ + pOperands[WEIER_VZ] = pOperands[WEIER_Z]; + pZA = MCUXCLPKC_OFFSET2PTR(pOperands[WEIER_ZA]); + /* Rerandomize R0 (X0,Y0, Z) and R1 (X1,Y1, Z) and ensure that the X- and Y-coordinates are in range [0,p-1]. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom1, mcuxClRandom_ncGenerate(pSession, pZA, operandSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_Prng_GetRandom1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1, + mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1_LEN); + + /* Read next CPU word of scalar. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_innerloop, mcuxClRandom_ncGenerate(pSession, (uint8_t*)&scalarWord1, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_innerloop) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + scalarWord0 = pScalar[scalarBitIndex / 32u] ^ scalarWord1; + } + + uint32_t offsetsP0; + uint32_t offsetsP1; + uint32_t randomMask; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_loop, mcuxClRandom_ncGenerate(pSession, (uint8_t*)&randomMask, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_loop) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + /* When bit of scalar = 0, the macro returns: */ + /* offsetsP0 = pOperands[WEIER_Y0] || pOperands[WEIER_X0], and */ + /* offsetsP1 = pOperands[WEIER_Y1] || pOperands[WEIER_X1]; */ + /* when bit = 1, */ + /* offsetsP0 = pOperands[WEIER_Y1] || pOperands[WEIER_X1], and */ + /* offsetsP1 = pOperands[WEIER_Y0] || pOperands[WEIER_X0]. */ + MCUXCLECC_SECUREPOINTSELECT(offsetsP0, offsetsP1, pOperands, WEIER_X0, + scalarWord0, scalarWord1, randomMask, bitOffset); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, offsetsP0); + MCUXCLECC_STORE_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, offsetsP1); + + /* Perform double-and-add step. + * + * NOTE: Since X0, Y0, X1, Y1 < p before the double-and-add step, the same holds for those coordinates afterwards. */ + MCUXCLPKC_FP_CALCFUP_OFFSET(mcuxClEcc_FUP_Weier_CoZPointAddSub, + mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN1, + mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN2); + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_CoZPointAddSub, mcuxClEcc_FUP_Weier_CoZPointAddSub_LEN); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_SecurePointMult, MCUXCLECC_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.c new file mode 100644 index 000000000..3744616bb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.c @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.c + * @brief FUP programs for Weierstrass curve internal secure point multiplication + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_CoZPointAddSub[28] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xc8u,0x49u,0x18u,0x02u},{0x00u,0x1eu,0x00u,0x08u,0x03u,0x1du},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x08u},{0x80u,0x21u,0x00u,0x08u,0x19u,0x08u},{0x80u,0x2au,0x00u,0x1du,0x08u,0x1du},{0x80u,0x00u,0x1bu,0x1du,0x00u,0x19u},{0x80u,0x2au,0x00u,0x19u,0x09u,0x09u},{0x10u,0x00u,0xd0u,0xdeu,0x33u,0x29u},{0x80u,0x2au,0x00u,0x04u,0x08u,0x1du},{0x80u,0x00u,0x07u,0x1du,0x00u,0x1bu},{0x00u,0x1eu,0x00u,0x1bu,0x03u,0x07u},{0x80u,0x00u,0x1du,0x1du,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x04u,0x00u,0x08u},{0x80u,0x00u,0x1bu,0x1du,0x00u,0x19u},{0x80u,0x21u,0x00u,0x05u,0x09u,0x1bu},{0x80u,0x2au,0x00u,0x05u,0x09u,0x1du},{0x80u,0x00u,0x05u,0x19u,0x00u,0x09u},{0x81u,0x2au,0x00u,0x19u,0x08u,0x19u},{0x80u,0x00u,0x1du,0x1du,0x00u,0x04u},{0x80u,0x21u,0x00u,0x04u,0x19u,0x04u},{0x82u,0x2au,0x00u,0x04u,0x00u,0x04u},{0x80u,0x2au,0x00u,0x08u,0x04u,0x1fu},{0x80u,0x00u,0x1fu,0x1du,0x00u,0x05u},{0x80u,0x2au,0x00u,0x05u,0x09u,0x05u},{0x80u,0x2au,0x00u,0x05u,0x00u,0x05u},{0x10u,0x00u,0xd7u,0xe0u,0x2au,0x7eu},{0x80u,0x2au,0x00u,0x08u,0x00u,0x08u},{0x80u,0x2au,0x00u,0x09u,0x00u,0x09u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_PrepareZA_UpdateZ_P0_P1[20] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xf2u,0xf2u,0x1au,0xe6u},{0x80u,0x33u,0x22u,0x00u,0x00u,0x19u},{0x00u,0x15u,0x00u,0x19u,0x02u,0x22u},{0x00u,0x1au,0x00u,0x22u,0x02u,0x22u},{0x10u,0x00u,0xedu,0x4bu,0x97u,0xdau},{0x80u,0x00u,0x23u,0x22u,0x00u,0x19u},{0x00u,0x1eu,0x00u,0x19u,0x03u,0x23u},{0x80u,0x00u,0x22u,0x22u,0x00u,0x19u},{0x80u,0x2au,0x00u,0x19u,0x00u,0x19u},{0x80u,0x00u,0x22u,0x19u,0x00u,0x1bu},{0x80u,0x2au,0x00u,0x1bu,0x00u,0x1bu},{0x80u,0x00u,0x24u,0x19u,0x00u,0x1du},{0x80u,0x00u,0x25u,0x1bu,0x00u,0x1fu},{0x80u,0x2au,0x00u,0x1du,0x00u,0x24u},{0x80u,0x2au,0x00u,0x1fu,0x00u,0x25u},{0x10u,0x00u,0xc6u,0x85u,0x6eu,0x2du},{0x80u,0x00u,0x26u,0x19u,0x00u,0x1du},{0x80u,0x00u,0x27u,0x1bu,0x00u,0x1fu},{0x80u,0x2au,0x00u,0x1du,0x00u,0x26u},{0x80u,0x2au,0x00u,0x1fu,0x00u,0x27u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_SecurePointMult_Reduce_X1_Y1_ZA_ModP[8] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x9du,0x26u,0xf0u,0xb4u},{0x80u,0x33u,0x16u,0x00u,0x00u,0x19u},{0x80u,0x00u,0x26u,0x19u,0x00u,0x1bu},{0x80u,0x00u,0x27u,0x19u,0x00u,0x1du},{0x80u,0x2au,0x00u,0x1bu,0x00u,0x26u},{0x80u,0x2au,0x00u,0x1du,0x00u,0x27u},{0x80u,0x00u,0x22u,0x19u,0x00u,0x1bu},{0x80u,0x2au,0x00u,0x1bu,0x00u,0x22u}}; + + + +/* FUP program for point addition and subtraction with co-Z coordinate + * to be used for a Montgomery ladder step with following input and output: + * + * Input: + * P0 = (x0,y0, z) in (VX0,VY0,VZ) in Jacobian coordinates in MR with x0,y0 < p + * P1 = (x1,y1, z) in (VX1,VY1,VZ) in Jacobian coordinates in MR with x1,y1 < p + * + * Output: + * P0Res = (x0Res,y0Res,zRes) = 2*P0 in (VX0,VY0,VZ) in Jacobian coordinates in MR with x0Res,y0Res < p + * P1Res = (x1Res,y1Res,zRes) = P0 + P1 in (VX1,VY1,VZ) in Jacobian coordinates in MR with x0Res,y0Res < p + * + * The FUP program is divided into several parts which perform different arithmetic operations. + * It shall be called twice with different entry points and FUP program lengths to realize + * a full Montgomery ladder step: + * 1. Execute part 2 of the FUP program for the first point addition and Z-coordinate update: + * - P0Int = (x0Int,y0Int,zInt) = P0 + P1 in (VX0,VY0,VZ) in Jacobian coordinates in MR with x0Int,y0Int < p + * - P1Int = (x1Int,y1Int,zInt) = P0 (with updated Z) in (VX1,VY1,VZ) in Jacobian coordinates in MR + * + * 2. Execute parts 1-3 of the FUP program for point subtraction, second point addition and coordinate reduction: + * - P1Sub = (x1Sub,y1Sub,zInt) = P1Int - P1 = P0 - P1 in (VX1,VY1,VZ) in Jacobian coordinates in MR + * - P0Res = (x0Res,y0Res,zRes) = P0Int + P0 - P1 = 2*P0 in (VX0,VY0,VZ) in Jacobian coordinates in MR with x0Res,y0Res < p + * - P1Res = (x1Res,y1Res,zRes) = P0Int (with updated Z) in (VX1,VY1,VZ) in Jacobian coordinates in MR with x1Res,y1Res < p + * + * ATTENTION: The FUP program shall only be used with P0 != +/- P1, otherwise the result will be incorrect. + * + * NOTE: The FUP program performs modular additions and subtractions modulo p instead of modulo the shifted modulus. + * While this helps to ensure that the output coordinates are again < p, it might as a side-effect cause conditional + * subtractions resp. additions with the modulus p. Due to the assumptions on the input coordinates, however, + * the number of these conditional operations is usually rather small and in no case related to the scalar bits. */ + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + + +/* FUP program to reduce values in X1, Y1 and ZA modulo p */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* FUP program: + * - 1st part: Preparation of ZA in [1,p-1] + * - 2nd part: Update Z-coordinate and update Jacobian coordinates of R0 in MR + * - 3nd part: Update Jacobian coordinates of R1 in MR + * + * Input: + * R0 = (x0,y0, z) in (X0, Y0, Z), Jacobian in MR with x0, y0 < p + * R1 = (x1,y1, z) in (X1, Y1, Z), Jacobian in MR with x1, y1 < p + * Output: + * Updated R0 = (x0,y0, z) in (X0, Y0, Z), Jacobian in MR with x0, y0 < p + * Updated R1 = (x1,y1, z) in (X1, Y1, Z), Jacobian in MR with x1, y1 < p + * + * NOTES: + * - If the 1st part is skipped, then X0, Y0, X1, Y1 are only in [0,p-1] if ZA is ensured to be in [0,p-1] */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SetupEnvironment.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SetupEnvironment.c new file mode 100644 index 000000000..01f7ae046 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Internal_SetupEnvironment.c @@ -0,0 +1,151 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Internal_SetupEnvironment.c + * @brief Weierstrass curve internal setup environment + */ + + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Weier_SetupEnvironment) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Weier_SetupEnvironment( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_DomainParam_t *pWeierDomainParams, + uint8_t noOfBuffers ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Weier_SetupEnvironment); + + /**********************************************************/ + /* Initialization */ + /**********************************************************/ + const uint32_t byteLenP = (pWeierDomainParams->misc & mcuxClEcc_DomainParam_misc_byteLenP_mask) >> mcuxClEcc_DomainParam_misc_byteLenP_offset; + const uint32_t byteLenN = (pWeierDomainParams->misc & mcuxClEcc_DomainParam_misc_byteLenN_mask) >> mcuxClEcc_DomainParam_misc_byteLenN_offset; + const uint32_t byteLenMax = ((byteLenP > byteLenN) ? byteLenP : byteLenN); + const uint32_t operandSize = MCUXCLPKC_ROUNDUP_SIZE(byteLenMax); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + + /* Setup CPU workarea and PKC buffer. */ + const uint32_t byteLenOperandsTable = (sizeof(uint16_t)) * (ECC_NO_OF_VIRTUALS + (uint32_t) noOfBuffers); + const uint32_t alignedByteLenCpuWa = (sizeof(mcuxClEcc_CpuWa_t)) + MCUXCLECC_ALIGNED_SIZE(byteLenOperandsTable); + const uint32_t wordNumCpuWa = alignedByteLenCpuWa / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, wordNumCpuWa); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t wordNumPkcWa = (bufferSize * noOfBuffers) / (sizeof(uint32_t)); + const uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordNumPkcWa); + + if ((NULL == pCpuWorkarea) || (NULL == pPkcWorkarea)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Weier_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + } + pCpuWorkarea->wordNumCpuWa = wordNumCpuWa; + pCpuWorkarea->wordNumPkcWa = wordNumPkcWa; + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, &pCpuWorkarea->pkcStateBackup, mcuxClEcc_Weier_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + + /* Set PS1 MCLEN and LEN. */ + MCUXCLPKC_PS1_SETLENGTH(operandSize, operandSize); + + /* Setup uptr table. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t *pOperands = (uint16_t *) pCpuWorkarea->pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + MCUXCLPKC_FP_GENERATEUPTRT(& pOperands[ECC_NO_OF_VIRTUALS], + pPkcWorkarea, + (uint16_t) bufferSize, + noOfBuffers); + MCUXCLPKC_SETUPTRT(pOperands); + + /* Setup virtual offsets to prime p and curve order n. */ + pOperands[ECC_P] = (uint16_t) (pOperands[ECC_PFULL] + MCUXCLPKC_WORDSIZE); + pOperands[ECC_N] = (uint16_t) (pOperands[ECC_NFULL] + MCUXCLPKC_WORDSIZE); + + /* Initialize constants ONE = 0x0001 and ZERO = 0x0000 in uptr table. */ + pOperands[ECC_ONE] = 0x0001u; + pOperands[ECC_ZERO] = 0x0000u; + + + /**********************************************************/ + /* Import / prepare curve parameters */ + /**********************************************************/ + + /* Import prime p and order n. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_P, pWeierDomainParams->pP, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_N, pWeierDomainParams->pN, byteLenN); + + /* Check p and n are odd (Math functions assume modulus is odd). */ + const volatile uint8_t * ptrP = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_P]); + const volatile uint8_t * ptrN = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_N]); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("PKC buffer is CPU word aligned") + uint32_t p0 = ((const volatile uint32_t *) ptrP)[0]; + uint32_t n0 = ((const volatile uint32_t *) ptrN)[0]; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (0x01u != (0x01u & p0 & n0)) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Weier_SetupEnvironment, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Weier_SetupEnvironment, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_GenerateUPTRT), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Calculate NDash of p and n, ShiftModulus of p and n, QSquared of p. */ + MCUXCLMATH_FP_NDASH(ECC_P, ECC_T0); + MCUXCLMATH_FP_NDASH(ECC_N, ECC_T0); + MCUXCLMATH_FP_SHIFTMODULUS(ECC_PS, ECC_P); + MCUXCLMATH_FP_SHIFTMODULUS(ECC_NS, ECC_N); + MCUXCLMATH_FP_QSQUARED(ECC_PQSQR, ECC_PS, ECC_P, ECC_T0); + + /* Import coefficients a and b, and convert a to MR. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pWeierDomainParams->pA, byteLenP); + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_A, ECC_T0, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_B, pWeierDomainParams->pB, byteLenP); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Weier_SetupEnvironment, MCUXCLECC_STATUS_OK, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_GenerateUPTRT), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen.c new file mode 100644 index 000000000..173d9b281 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen.c @@ -0,0 +1,286 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_KeyGen.c + * @brief Weierstrass curve ECDSA key generation API + */ + + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_KeyGen) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_KeyGen( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_KeyGen_Param_t * pParam) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_KeyGen); + + /**********************************************************/ + /* Initialization */ + /**********************************************************/ + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, 0u); + MCUX_CSSL_FP_FUNCTION_CALL(ret_SetupEnvironment, + mcuxClEcc_Weier_SetupEnvironment(pSession, + & pParam->curveParam, + ECC_KEYGEN_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != ret_SetupEnvironment) + { + if (MCUXCLECC_STATUS_INVALID_PARAMS == ret_SetupEnvironment) + { + /* Session has been cleaned, PKC has been deinitialized in SetupEnvironment. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) ); + } + + MCUXCLECC_HANDLE_HW_UNAVAILABLE(ret_SetupEnvironment, mcuxClEcc_KeyGen); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Randomize buffers XA/YA/ZA/Z/X0/Y0/X1/Y1. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_FP_FUNCTION_CALL(retRandomUptrt, + mcuxClPkc_RandomizeUPTRT(pSession, + &pOperands[WEIER_XA], + (WEIER_Y1 - WEIER_XA + 1u)) ); + if (MCUXCLPKC_STATUS_OK != retRandomUptrt) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUXCLMATH_FP_QSQUARED(ECC_NQSQR, ECC_NS, ECC_N, ECC_T0); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + + const uint32_t byteLenP = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenP_mask) >> mcuxClEcc_DomainParam_misc_byteLenP_offset; + const uint32_t byteLenN = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenN_mask) >> mcuxClEcc_DomainParam_misc_byteLenN_offset; + + /**********************************************************/ + /* Import and check base point G */ + /**********************************************************/ + + /* Import G to (X1,Y1). */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X1, pParam->curveParam.pG, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y1, pParam->curveParam.pG + byteLenP, byteLenP); + + /* Check G in (X1,Y1) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in import function. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_KEYGEN_BASE_POINT, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + + /**********************************************************/ + /* Generate multiplicative split private key d0 and d1, */ + /* d = d0 * d1 mod n, where d0 is a 64-bit odd number. */ + /**********************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CoreKeyGen, mcuxClEcc_Int_CoreKeyGen(pSession, byteLenN)); + if (MCUXCLECC_STATUS_OK != ret_CoreKeyGen) + { + if (MCUXCLECC_STATUS_RNG_ERROR == ret_CoreKeyGen) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_RNG_ERROR, + MCUXCLECC_FP_KEYGEN_GENERATE_PRIKEY, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /**********************************************************/ + /* Derive the plain private key d = d0 * d1 mod n < n. */ + /**********************************************************/ + + /* Compute d in S2 using a blinded multiplication utilizing the random still stored in S3 after mcuxClEcc_Int_CoreKeyGen. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey, + mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey_LEN); + + /**********************************************************/ + /* Calculate public key Q = d1 * (d0 * G) */ + /**********************************************************/ + + /* Convert coordinates of G to Montgomery representation. */ + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_X0, WEIER_X1, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_Y0, WEIER_Y1, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_CALC_OP1_NEG(WEIER_Z, ECC_P); /* 1 in MR */ + /* G will be randomized (projective coordinate randomization) in SecurePointMult. */ + + /* Calculate Q0 = d0 * G. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusFirst, mcuxClEcc_SecurePointMult(pSession, ECC_S0, 64u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* In case d1 is even, perform scalar multiplication d1 * Q0 by computing (n-d1) * (-Q0) as this avoids the exceptional case d1 = n-1 */ + MCUX_CSSL_FP_BRANCH_DECL(scalarEvenBranch); + MCUXCLPKC_FP_CALC_OP1_LSB0s(ECC_S1); + uint32_t d1NoOfTrailingZeros = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if(MCUXCLPKC_FLAG_NONZERO == d1NoOfTrailingZeros) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_S1, ECC_N, ECC_S1); + MCUXCLPKC_FP_CALC_MC1_MS(WEIER_Y0, ECC_PS, WEIER_Y0, ECC_PS); + + MCUX_CSSL_FP_BRANCH_POSITIVE(scalarEvenBranch, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + } + + /* Calculate Q = d1 * Q0. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusSecond, mcuxClEcc_SecurePointMult(pSession, ECC_S1, byteLenN * 8u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(scalarEvenBranch, MCUXCLPKC_FLAG_NONZERO == d1NoOfTrailingZeros)); + + + /**********************************************************/ + /* Convert public key to affine coordinates and check */ + /**********************************************************/ + + /* T0 = ModInv(Z), where Z = (z * 256^LEN) \equiv z in MR. */ + MCUXCLMATH_FP_MODINV(ECC_T0, WEIER_Z, ECC_P, ECC_T1); + /* T0 = z^(-1) * 256^(-LEN) \equiv z^(-1) * 256^(-2LEN) in MR. */ + + /* Convert Q to affine coordinates. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine, + mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine_LEN); + + /* Check Q in (XA,YA) affine NR. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_XA, WEIER_YA); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckQStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_STATUS_OK != pointCheckQStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /**********************************************************/ + /* Check n and p and export private and public key. */ + /**********************************************************/ + + /* Import prime p and order n again, and check (compare with) existing one. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pParam->curveParam.pP, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T1, pParam->curveParam.pN, byteLenN); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + uint32_t zeroFlag_checkP = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T1, ECC_N); + uint32_t zeroFlag_checkN = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + if ( (zeroFlag_checkP == MCUXCLPKC_FLAG_ZERO) + && (zeroFlag_checkN == MCUXCLPKC_FLAG_ZERO) ) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExport, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pParam->pPrivateKey, + MCUXCLPKC_PACKARGS2(ECC_S2, ECC_T0), + byteLenN) ); + if (MCUXCLPKC_STATUS_OK != ret_SecExport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pParam->pPublicKey, WEIER_XA, byteLenP); + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pParam->pPublicKey + byteLenP, WEIER_YA, byteLenP); + + /* Clear PKC workarea. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSize * ECC_KEYGEN_NO_OF_BUFFERS); + pOperands[ECC_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_P, 0u); + + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_KEYGEN_FINAL); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_KeyGen, MCUXCLECC_STATUS_FAULT_ATTACK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen_FUP.c new file mode 100644 index 000000000..1ce0b162e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_KeyGen_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_KeyGen_FUP.c + * @brief FUP program for Weierstrass curve key generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_KeyGen_DerivePlainPrivKey[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xcfu,0x8du,0x82u,0xabu},{0x80u,0x33u,0x1eu,0x00u,0x01u,0x1cu},{0x80u,0x00u,0x1cu,0x18u,0x01u,0x1eu},{0x80u,0x21u,0x01u,0x19u,0x1cu,0x19u},{0x80u,0x00u,0x19u,0x18u,0x01u,0x1cu},{0x80u,0x2au,0x01u,0x1cu,0x01u,0x1cu},{0x80u,0x2au,0x01u,0x1cu,0x1eu,0x1cu}}; + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult.c new file mode 100644 index 000000000..fed22ab77 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult.c @@ -0,0 +1,342 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_PointMult.c + * @brief Weierstrass curve point multiplication API + */ + + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_PointMult) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_PointMult( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_PointMult_Param_t * pParam) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_PointMult); + + /**********************************************************/ + /* Initialization */ + /**********************************************************/ + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, 0u); + MCUX_CSSL_FP_FUNCTION_CALL(ret_SetupEnvironment, + mcuxClEcc_Weier_SetupEnvironment(pSession, + & pParam->curveParam, + ECC_POINTMULT_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != ret_SetupEnvironment) + { + if (MCUXCLECC_STATUS_INVALID_PARAMS == ret_SetupEnvironment) + { + /* Session has been cleaned, PKC has been deinitialized in SetupEnvironment. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) ); + } + + MCUXCLECC_HANDLE_HW_UNAVAILABLE(ret_SetupEnvironment, mcuxClEcc_PointMult); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Randomize buffers XA/YA/ZA/Z/X0/Y0/X1/Y1. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_FP_FUNCTION_CALL(retRandomUptrt, + mcuxClPkc_RandomizeUPTRT(pSession, + &pOperands[WEIER_XA], + (WEIER_Y1 - WEIER_XA + 1u)) ); + if (MCUXCLPKC_STATUS_OK != retRandomUptrt) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + + MCUXCLMATH_FP_QDASH(ECC_NQSQR, ECC_NS, ECC_N, ECC_T0, (uint16_t) (operandSize + bufferSize)); /* **CAUTION** */ + + const uint32_t byteLenP = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenP_mask) >> mcuxClEcc_DomainParam_misc_byteLenP_offset; + const uint32_t byteLenN = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenN_mask) >> mcuxClEcc_DomainParam_misc_byteLenN_offset; + + /**********************************************************/ + /* Import and check point P */ + /**********************************************************/ + + /* Import P to (X1,Y1). */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X1, pParam->pPoint, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y1, pParam->pPoint + byteLenP, byteLenP); + + /* Check P in (X1,Y1) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in import function. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_POINTMULT_BASE_POINT, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + + /**********************************************************/ + /* Securely import scalar d, and multiplicative split to */ + /* d = d0 * d1 mod n, where d0 is a 64-bit odd number. */ + /**********************************************************/ + + // TODO: CLNS-3449: check if reducing the blinding factor d0 to 32-bit, + // and use mcuxClEcc_GenerateMultiplicativeBlinding. + /* Generate 64-bit random number d0 in buffer S0 of size = operandSize. */ + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_S0, 0u); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_S3, 0u); + uint8_t *ptrS0 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S0]); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_randWord1, mcuxClRandom_ncGenerate(pSession, ptrS0, 8u)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_randWord1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + /* Set MSBit of d0 (to ensure d0 != 0) using the PKC + * + * NOTE: PKC PS1 can be used, because operandSize >= 64.*/ + uint32_t *ptr32S3 = MCUXCLPKC_OFFSET2PTRWORD(pOperands[ECC_S3]); + ptr32S3[0u] = 0x00000000u; + ptr32S3[1u] = 0x80000000u; + MCUXCLPKC_FP_CALC_OP1_OR(ECC_S0, ECC_S0, ECC_S3); + + /* T0 = ModInv(d0), with temp T1. */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(ECC_S1, ECC_S0, 0u); + MCUXCLMATH_FP_MODINV(ECC_T0, ECC_S1, ECC_N, ECC_T1); + + MCUXCLPKC_WAITFORREADY(); + + /* Securely import scalar d to buffer S1 of size = bufferSize, with temp T1. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSize); + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImport, + mcuxClPkc_SecureImportBigEndianToPkc(pSession, MCUXCLPKC_PACKARGS2(ECC_S1, ECC_T1), + pParam->pScalar, byteLenN) ); + if (MCUXCLPKC_STATUS_OK != ret_SecImport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Generate (buffer size minus 1 bit) random number d' in buffer S2. */ + uint8_t *ptrS2 = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S2]); /* PKC word is CPU word aligned. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_GetRandom, mcuxClRandom_ncGenerate(pSession, ptrS2, bufferSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUXCLPKC_FP_CALC_OP1_SHR(ECC_S2, ECC_S2, 1u); + + /* S3 = d" = d + d' */ + MCUXCLPKC_FP_CALC_OP1_ADD(ECC_S3, ECC_S1, ECC_S2); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(operandSize, operandSize); + MCUXCLPKC_PS2_SETLENGTH(bufferSize, operandSize); + + /* Split scalar d = d0 * d1, and convert coordinates of P to Montgomery representation. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR, + mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR_LEN); + + /* Check if d is zero. */ + if (MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + /* Clear PKC workarea. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSize * ECC_POINTMULT_NO_OF_BUFFERS); + pOperands[ECC_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_P, 0u); + + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_NEUTRAL_POINT, + MCUXCLECC_FP_POINTMULT_SCALAR, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + + /**********************************************************/ + /* Calculate scalar multiplications Q = d1 * (d0 * P) */ + /**********************************************************/ + + /* P has been converted to MR, and Z has been initialized to 1 (in MR). */ + /* P will be randomized (projective coordinate randomization) in SecurePointMult. */ + + /* Calculate Q0 = d0 * P. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusFirst, mcuxClEcc_SecurePointMult(pSession, ECC_S0, 64u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* In case d1 is even, perform scalar multiplication d1 * Q0 by computing (n-d1) * (-Q0) as this avoids the exceptional case d1 = n-1 */ + MCUX_CSSL_FP_BRANCH_DECL(scalarEvenBranch); + MCUXCLPKC_FP_CALC_OP1_LSB0s(ECC_S1); + uint32_t d1NoOfTrailingZeros = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if(MCUXCLPKC_FLAG_NONZERO == d1NoOfTrailingZeros) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_S1, ECC_N, ECC_S1); + MCUXCLPKC_FP_CALC_MC1_MS(WEIER_Y0, ECC_PS, WEIER_Y0, ECC_PS); + + MCUX_CSSL_FP_BRANCH_POSITIVE(scalarEvenBranch, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + } + + /* Calculate Q = d1 * Q0. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusSecond, mcuxClEcc_SecurePointMult(pSession, ECC_S1, byteLenN * 8u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(scalarEvenBranch, MCUXCLPKC_FLAG_NONZERO == d1NoOfTrailingZeros)); + + /**********************************************************/ + /* Convert result point to affine coordinates and check */ + /**********************************************************/ + + /* T0 = ModInv(Z), where Z = (z * 256^LEN) \equiv z in MR. */ + MCUXCLMATH_FP_MODINV(ECC_T0, WEIER_Z, ECC_P, ECC_T1); + /* T0 = z^(-1) * 256^(-LEN) \equiv z^(-1) * 256^(-2LEN) in MR. */ + + /* Convert Q to affine coordinates. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine, + mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine_LEN); + + /* Check Q in (XA,YA) affine NR. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_XA, WEIER_YA); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckQStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_STATUS_OK != pointCheckQStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /**********************************************************/ + /* Check n and p and export private and public key. */ + /**********************************************************/ + + /* Import prime p and order n again, and check (compare with) existing one. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pParam->curveParam.pP, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T1, pParam->curveParam.pN, byteLenN); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + uint32_t zeroFlag_checkP = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T1, ECC_N); + uint32_t zeroFlag_checkN = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + if ( (zeroFlag_checkP == MCUXCLPKC_FLAG_ZERO) + && (zeroFlag_checkN == MCUXCLPKC_FLAG_ZERO) ) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportXa, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pParam->pResult, + MCUXCLPKC_PACKARGS2(WEIER_XA, ECC_T0), + byteLenP) ); + if (MCUXCLPKC_STATUS_OK != ret_SecExportXa) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportYa, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pParam->pResult + byteLenP, + MCUXCLPKC_PACKARGS2(WEIER_YA, ECC_T1), + byteLenP) ); + if (MCUXCLPKC_STATUS_OK != ret_SecExportYa) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Clear PKC workarea. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSize * ECC_POINTMULT_NO_OF_BUFFERS); + pOperands[ECC_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_P, 0u); + + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_PointMult, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_POINTMULT_FINAL); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_PointMult, MCUXCLECC_STATUS_FAULT_ATTACK); +} diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult_FUP.c new file mode 100644 index 000000000..35f1ecd43 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_PointMult_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_PointMult_FUP.c + * @brief FUP program for Weierstrass curve point multiplication + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_PointMult_SplitScalar_ConvertPoint2MR[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xb2u,0xc7u,0xddu,0x8au},{0x80u,0x00u,0x19u,0x17u,0x01u,0x1au},{0xc0u,0x00u,0x1cu,0x1au,0x01u,0x19u},{0xc0u,0x00u,0x1eu,0x1au,0x01u,0x1bu},{0x80u,0x00u,0x26u,0x16u,0x00u,0x24u},{0x80u,0x00u,0x27u,0x16u,0x00u,0x25u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x23u},{0x80u,0x2au,0x11u,0x1bu,0x19u,0x1bu},{0x80u,0x33u,0x1bu,0x00u,0x01u,0x19u},{0x80u,0x2au,0x01u,0x19u,0x01u,0x1au}}; + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign.c new file mode 100644 index 000000000..89e6823f1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign.c @@ -0,0 +1,391 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Sign.c + * @brief Weierstrass curve ECDSA signature generation API + */ + + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Sign) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Sign( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_Sign_Param_t * pParam) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Sign); + + /**********************************************************/ + /* Initialization */ + /**********************************************************/ + + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + /* MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, 0u); + MCUX_CSSL_FP_FUNCTION_CALL(ret_SetupEnvironment, + mcuxClEcc_Weier_SetupEnvironment(pSession, + & pParam->curveParam, + ECC_SIGN_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != ret_SetupEnvironment) + { + if (MCUXCLECC_STATUS_INVALID_PARAMS == ret_SetupEnvironment) + { + /* Session has been cleaned, PKC has been deinitialized in SetupEnvironment. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) ); + } + + MCUXCLECC_HANDLE_HW_UNAVAILABLE(ret_SetupEnvironment, mcuxClEcc_Sign); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Randomize buffers XA/YA/ZA/Z/X0/Y0/X1/Y1. */ + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_FP_FUNCTION_CALL(retRandomUptrt, + mcuxClPkc_RandomizeUPTRT(pSession, + &pOperands[WEIER_XA], + (WEIER_Y1 - WEIER_XA + 1u)) ); + if (MCUXCLPKC_STATUS_OK != retRandomUptrt) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_RNG_ERROR); + } + + MCUXCLMATH_FP_QSQUARED(ECC_NQSQR, ECC_NS, ECC_N, ECC_T0); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint32_t bufferSize = operandSize + MCUXCLPKC_WORDSIZE; + + const uint32_t byteLenP = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenP_mask) >> mcuxClEcc_DomainParam_misc_byteLenP_offset; + const uint32_t byteLenN = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenN_mask) >> mcuxClEcc_DomainParam_misc_byteLenN_offset; + + /* Main loop of signature generation until both r and s are nonzero. */ + uint32_t fail_r = 0u; + uint32_t fail_s = 0u; + MCUX_CSSL_FP_LOOP_DECL(MainLoop_R); + MCUX_CSSL_FP_LOOP_DECL(MainLoop_S); + do + { + /**********************************************************/ + /* Import and check base point G */ + /**********************************************************/ + + /* Import G to (X1,Y1). */ /* TODO: create a function to import and check point. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X1, pParam->curveParam.pG, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y1, pParam->curveParam.pG + byteLenP, byteLenP); + + /* Check G in (X1,Y1) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in import function. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckStatus) + { + if ((0u == fail_r) && (0u == fail_s)) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_SIGN_BEFORE_LOOP, + MCUXCLECC_FP_SIGN_LOOP_R_0, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* The result of checking G is inconsistent. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else if (MCUXCLECC_STATUS_OK != pointCheckStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /**********************************************************/ + /* Generate multiplicative split ephemeral key k0 and k1, */ + /* k = k0 * k1 mod n, where k0 is a 64-bit odd number */ + /**********************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CoreKeyGen, mcuxClEcc_Int_CoreKeyGen(pSession, byteLenN)); + if (MCUXCLECC_STATUS_OK != ret_CoreKeyGen) + { + if ( (MCUXCLECC_STATUS_RNG_ERROR == ret_CoreKeyGen) + && (0u == fail_r) && (0u == fail_s) ) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_RNG_ERROR, + MCUXCLECC_FP_SIGN_BEFORE_LOOP, + MCUXCLECC_FP_SIGN_LOOP_R_1, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_LOOP_ITERATION(MainLoop_R, + MCUXCLECC_FP_SIGN_LOOP_R ); + + + /**********************************************************/ + /* Calculate Q = k1 * (k0 * G) */ + /**********************************************************/ + + /* Convert coordinates of G to Montgomery representation. */ + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_X0, WEIER_X1, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_Y0, WEIER_Y1, ECC_PQSQR, ECC_P); + MCUXCLPKC_FP_CALC_OP1_NEG(WEIER_Z, ECC_P); /* 1 in MR */ + /* G will be randomized (projective coordinate randomization) in SecurePointMult. */ + + /* Calculate Q0 = k0 * G. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusFirst, mcuxClEcc_SecurePointMult(pSession, ECC_S0, 64u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusFirst) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* In case k1 is even, perform scalar multiplication k1 * Q0 by computing (n - k1) * (-Q0) + * as this avoids the exceptional case k1 = n-1. scalar modification will need to be reverted later on + */ + MCUX_CSSL_FP_BRANCH_DECL(scalarEvenBranch); + MCUXCLPKC_FP_CALC_OP1_LSB0s(ECC_S1); + uint32_t k1NoOfTrailingZeros = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if(MCUXCLPKC_FLAG_NONZERO == k1NoOfTrailingZeros) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_S1, ECC_N, ECC_S1); + MCUXCLPKC_FP_CALC_MC1_MS(WEIER_Y0, ECC_PS, WEIER_Y0, ECC_PS); + + MCUX_CSSL_FP_BRANCH_POSITIVE(scalarEvenBranch, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS ); + } + + /* Calculate Q = k1 * Q0. */ + MCUX_CSSL_FP_FUNCTION_CALL(securePointMultStatusSecond, mcuxClEcc_SecurePointMult(pSession, ECC_S1, byteLenN * 8u)); + if(MCUXCLECC_STATUS_RNG_ERROR == securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_RNG_ERROR); + } + else if(MCUXCLECC_STATUS_OK != securePointMultStatusSecond) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(scalarEvenBranch, MCUXCLPKC_FLAG_NONZERO == k1NoOfTrailingZeros)); + + + /**********************************************************/ + /* Convert Q to affine coordinates and check */ + /**********************************************************/ + + /* T0 = ModInv(Z), where Z = (z * 256^LEN) \equiv z in MR. */ + MCUXCLMATH_FP_MODINV(ECC_T0, WEIER_Z, ECC_P, ECC_T1); + /* T0 = z^(-1) * 256^(-LEN) \equiv z^(-1) * 256^(-2LEN) in MR. */ + + /* Convert Q to affine coordinates. */ + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine, + mcuxClEcc_FUP_Weier_ConvertPoint_ToAffine_LEN); + + /* Check Q in (XA,YA) affine NR. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_XA, WEIER_YA); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckQStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_STATUS_OK != pointCheckQStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /**********************************************************/ + /* Calculate r = Q.x mod n, and check if r is zero */ + /**********************************************************/ + + MCUXCLPKC_FP_CALC_MC1_MS(WEIER_XA, WEIER_XA, ECC_N, ECC_N); /* Hasse's theorem: Abs(n - (p+1)) <= 2 * sqrt(p). */ + + fail_r += MCUXCLPKC_WAITFORFINISH_GETZERO(); + if (MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_GETZERO()) + { + continue; + } + + /**********************************************************/ + /* Securely import private key */ + /**********************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImport, + mcuxClPkc_SecureImportBigEndianToPkc(pSession, MCUXCLPKC_PACKARGS2(WEIER_ZA, ECC_T0), + pParam->pPrivateKey, byteLenN) ); + if (MCUXCLPKC_STATUS_OK != ret_SecImport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /* Generate random number d1 (to blind the private key). */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + uint8_t * ptrZ = MCUXCLPKC_OFFSET2PTR(pOperands[WEIER_Z]); + MCUX_CSSL_FP_FUNCTION_CALL(ret_PRNG_GetRandom, mcuxClRandom_ncGenerate(pSession, ptrZ, operandSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_PRNG_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_RNG_ERROR); + } + + + /**********************************************************/ + /* Import message hash, and truncate if longer than n */ + /**********************************************************/ + + /* Import message hash (up to byteLenN bytes). */ + uint32_t byteLenHash = (pParam->optLen & mcuxClEcc_Verify_Param_optLen_byteLenHash_mask) >> mcuxClEcc_Verify_Param_optLen_byteLenHash_offset; + uint32_t byteLenHashImport = MCUXCLECC_TRUNCATED_HASH_LEN(byteLenHash, byteLenN); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_S2, pParam->pHash, byteLenHashImport); + + /* Truncate message hash if its bit length is longer than that of n. */ + if (byteLenHash >= byteLenN) + { + /* Count leading zeros in MSByte of n. */ + const volatile uint8_t * ptrN = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_N]); + uint8_t nMSByte = ptrN[byteLenN - 1u]; + uint32_t nMSByte_LeadZeros = (uint32_t) mcuxClMath_CountLeadingZerosWord((uint32_t) nMSByte) - (8u * ((sizeof(uint32_t)) - 1u)); + + /* Only keep the first bitLenN bits of hash. */ + MCUXCLPKC_FP_CALC_OP1_SHR(ECC_S2, ECC_S2, (uint8_t) nMSByte_LeadZeros); + } + + MCUX_CSSL_FP_LOOP_ITERATION(MainLoop_S, + MCUX_CSSL_FP_CONDITIONAL((byteLenHash >= byteLenN), + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR ), + MCUXCLECC_FP_SIGN_LOOP_S ); + + + /**********************************************************/ + /* Securely calculate signature s, and check if s is zero */ + /**********************************************************/ + /* Revert scalar modification by computing n-k1 in place again before calculating signature s */ + if(MCUXCLPKC_FLAG_NONZERO == k1NoOfTrailingZeros) + { + MCUXCLPKC_FP_CALC_OP1_SUB(ECC_S1, ECC_N, ECC_S1); + MCUX_CSSL_FP_EXPECT(MCUXCLPKC_FP_CALLED_CALC_OP1_SUB); + } + /* Now, XA = r, S2 = z (hash of message); */ + /* S0 = k0, S1 = k1, k = k0 * k1 mod n; */ + /* ZA = d, Z = d1. */ + /* s = k^(-1) * (z + r * d) = (k0*k1)^(-1) * (z + r * (d0-d1)) mod n. */ + + /* T1 = s' = k1*(z+r*d) * R^(-2) mod n <= n; */ + /* T2 = k0' = (k*k1) * R^(-3) mod n. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_Sign_CalculateS, + mcuxClEcc_FUP_Weier_Sign_CalculateS_LEN); + + /* T0 = h0 = ModInv(k0') = (k*k1)^(-1) * R^3 mod n. */ + MCUXCLMATH_FP_MODINV(ECC_T0, ECC_T2, ECC_N, ECC_T3); + + /* YA = s = h0 * s' - n mod n < n. */ + /* MM(h0, s') < 2n because s' <= n. */ + MCUXCLPKC_FP_CALC_MC1_MM(WEIER_YA, ECC_T0, ECC_T1, ECC_N); + MCUXCLPKC_FP_CALC_MC1_MS(WEIER_YA, WEIER_YA, ECC_N, ECC_N); + + fail_s += MCUXCLPKC_WAITFORFINISH_GETZERO(); + + } while(MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_GETZERO()); + + + /**********************************************************/ + /* Check n and p and export signature r and s */ + /**********************************************************/ + + /* Import prime p and order n again, and check (compare with) existing one. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pParam->curveParam.pP, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T1, pParam->curveParam.pN, byteLenN); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + uint32_t zeroFlag_checkP = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T1, ECC_N); + uint32_t zeroFlag_checkN = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + if ( (zeroFlag_checkP == MCUXCLPKC_FLAG_ZERO) + && (zeroFlag_checkN == MCUXCLPKC_FLAG_ZERO) ) + { + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pParam->pSignature, WEIER_XA, byteLenN); + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pParam->pSignature + byteLenN, WEIER_YA, byteLenN); + + /* Clear PKC workarea. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSize * ECC_SIGN_NO_OF_BUFFERS); + pOperands[ECC_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(ECC_P, 0u); + + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_Sign, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_SIGN_BEFORE_LOOP, + MCUX_CSSL_FP_LOOP_ITERATIONS(MainLoop_R, fail_r + fail_s + 1u), + MCUX_CSSL_FP_LOOP_ITERATIONS(MainLoop_S, fail_s + 1u), + MCUXCLECC_FP_SIGN_FINAL); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Sign, MCUXCLECC_STATUS_FAULT_ATTACK); +} + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign_FUP.c new file mode 100644 index 000000000..13d46ec9e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Sign_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Sign_FUP.c + * @brief FUP program for Weierstrass curve ECDSA signature generation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Sign_CalculateS[13] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xddu,0x80u,0x64u,0xd0u},{0x80u,0x00u,0x20u,0x17u,0x01u,0x21u},{0x80u,0x21u,0x01u,0x22u,0x23u,0x22u},{0x80u,0x00u,0x21u,0x22u,0x01u,0x1du},{0x80u,0x21u,0x11u,0x1cu,0x1du,0x1du},{0x80u,0x00u,0x1au,0x1du,0x01u,0x19u},{0x80u,0x00u,0x21u,0x23u,0x01u,0x1fu},{0x80u,0x00u,0x1au,0x1fu,0x01u,0x1bu},{0x80u,0x2au,0x11u,0x19u,0x1bu,0x19u},{0x80u,0x33u,0x19u,0x00u,0x01u,0x1bu},{0x80u,0x33u,0x18u,0x00u,0x01u,0x19u},{0x80u,0x00u,0x1au,0x1au,0x01u,0x1fu},{0x80u,0x00u,0x19u,0x1fu,0x01u,0x1du}}; + + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify.c new file mode 100644 index 000000000..118a124ce --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify.c @@ -0,0 +1,545 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Verify.c + * @brief Weierstrass curve ECDSA signature verification API + */ + + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEcc_Verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEcc_Status_t) mcuxClEcc_Verify( + mcuxClSession_Handle_t pSession, + const mcuxClEcc_Verify_Param_t * pParam) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEcc_Verify); + + + /**********************************************************/ + /* Initialization */ + /**********************************************************/ + /* mcuxClEcc_CpuWa_t will be allocated and placed in the beginning of CPU workarea free space by SetupEnvironment. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 to Rule 11.3 - mcuxClEcc_CpuWa_t is 32 bit aligned") + mcuxClEcc_CpuWa_t *pCpuWorkarea = (mcuxClEcc_CpuWa_t *) mcuxClSession_allocateWords_cpuWa(pSession, 0u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SetupEnvironment, + mcuxClEcc_Weier_SetupEnvironment(pSession, + & pParam->curveParam, + ECC_VERIFY_NO_OF_BUFFERS) ); + if (MCUXCLECC_STATUS_OK != ret_SetupEnvironment) + { + if (MCUXCLECC_STATUS_INVALID_PARAMS == ret_SetupEnvironment) + { + /* Session has been cleaned, PKC has been deinitialized in SetupEnvironment. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_Weier_SetupEnvironment) ); + } + + MCUXCLECC_HANDLE_HW_UNAVAILABLE(ret_SetupEnvironment, mcuxClEcc_Verify); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("32-bit aligned UPTRT table is assigned in CPU workarea") + uint32_t *pOperands32 = (uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + + const uint32_t byteLenP = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenP_mask) >> mcuxClEcc_DomainParam_misc_byteLenP_offset; + const uint32_t byteLenN = (pParam->curveParam.misc & mcuxClEcc_DomainParam_misc_byteLenN_mask) >> mcuxClEcc_DomainParam_misc_byteLenN_offset; + + + /**********************************************************/ + /* Import signature r and s, and */ + /* check both r,s are in range [1, n-1] */ + /**********************************************************/ + + /* Import r to S3 and s to T1. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_S3, pParam->pSignature, byteLenN); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T1, pParam->pSignature + byteLenN, byteLenN); + + /* If r < n, then t2 = r; otherwise t2 = r - n. */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T2, ECC_S3, ECC_N, ECC_N); + + /* Check r != 0, r != n. */ + if (MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) + { /* r = 0 or n. */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Check r < n. */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_S3, ECC_N); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { /* r > n. */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* If s < n, then t3 = s; otherwise t3 = s - n. */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_T3, ECC_T1, ECC_N, ECC_N); + + /* Check s != 0, s != n. */ + if (MCUXCLPKC_FLAG_ZERO == MCUXCLPKC_WAITFORFINISH_GETZERO()) + { /* s = 0 or n. */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Check s < n. */ + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T1, ECC_N); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { /* s > n. */ + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + + /**********************************************************/ + /* Import message hash, and truncate if longer than n */ + /**********************************************************/ + + /* Import message hash (up to byteLenN bytes). */ + uint32_t byteLenHash = (pParam->optLen & mcuxClEcc_Verify_Param_optLen_byteLenHash_mask) >> mcuxClEcc_Verify_Param_optLen_byteLenHash_offset; + uint32_t byteLenHashImport = MCUXCLECC_TRUNCATED_HASH_LEN(byteLenHash, byteLenN); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_S2, pParam->pHash, byteLenHashImport); + + /* Truncate message hash if its bit length is longer than that of n. */ + if (byteLenHash >= byteLenN) + { + /* Count leading zeros in MSByte of n. */ + const volatile uint8_t * ptrN = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_N]); + uint8_t nMSByte = ptrN[byteLenN - 1u]; + uint32_t nMSByte_LeadZeros = (uint32_t) mcuxClMath_CountLeadingZerosWord((uint32_t) nMSByte) - (8u * ((sizeof(uint32_t)) - 1u)); + + /* Only keep the first bitLenN bits of hash. */ + MCUXCLPKC_FP_CALC_OP1_SHR(ECC_S2, ECC_S2, (uint8_t) nMSByte_LeadZeros); + } + + /* Check if hash is 0 modulo n (one subtraction is enough, because bit length of hash <= bit length of n). */ + MCUXCLPKC_FP_CALC_MC1_MS(ECC_S2, ECC_S2, ECC_N, ECC_N); + uint32_t checkHashZero = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + + /**********************************************************/ + /* Calculate s^(-1), and */ + /* u1 = hash * s^(-1) mod n and u2 = r * s^(-1) mod n */ + /**********************************************************/ + + /* Calculate s^(-1) * 256^LEN mod n. */ + MCUXCLPKC_FP_CALC_MC1_MR(ECC_T2, ECC_T1, ECC_N); // t2 = s * (256^LEN)^(-1) + MCUXCLMATH_FP_MODINV(ECC_T1, ECC_T2, ECC_N, ECC_T3); // t1 = t2^(-1) = s^(-1) * 256^LEN, using T3 as temp + + /* Initialize z coordinate, z = 1 in MR, in Z. */ + /* Calculate u1 and u2, store result in S0 and S1. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_Fup_Verify_InitZ_CalcU1U2, + mcuxClEcc_Fup_Verify_InitZ_CalcU1U2_LEN); + /* Check if u1 is zero. */ + if (checkHashZero != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + + /**********************************************************/ + /* Calculate P1 = u1 * G */ + /**********************************************************/ + + /* Interleave u1 in S0 and u2 in S1. */ + MCUXCLECC_FP_INTERLEAVETWOSCALARS(MCUXCLPKC_PACKARGS2(ECC_S0, ECC_S1), byteLenN * 8u); + + /* Calculate P1 = u1 * G, if u1 != 0 */ + if (MCUXCLPKC_FLAG_ZERO != checkHashZero) + { + /* Import G to (X1,Y1). */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X1, pParam->curveParam.pG, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y1, pParam->curveParam.pG + byteLenP, byteLenP); + /* Import PrecG to (X2, Y2). */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X2, pParam->pPrecG, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y2, pParam->pPrecG + byteLenP, byteLenP); + + /* Check G in (X1,Y1) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in import function. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckBasePointStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckBasePointStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckBasePointStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* Check PrecG in (X2,Y2) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in _PointCheckAffineNR. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X2, WEIER_Y2); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckPrecPointStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckPrecPointStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckPrecPointStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* Convert coordinates of G and PrecG to MR. */ + /* G: (X1,Y1) affine NR -> (XA,YA, 1) Jacobian; */ + /* PrecG: (X2,X2) affine NR -> (X3,Y3, Z=1) relative-z. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR, + mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR_LEN); + + /* Prepare 3 pre-computed points for G, with the same z coordinate. */ + /* The relative z-coordinate, z' is stored in Z, instead of ZA. */ + /* Input: G in (XA,YA, 1) Jacobian; */ + /* PrecG in (X3,Y3, Z=1) relative-z. (ps, not in ZA) */ + /* Output: Prec1 = G (unchanged) in (XA,YA, 1) Jacobian; */ + /* Prec2 = PrecG (updated) in (X2,Y2, Z) relative-z; */ + /* Prec3 = G + PrecG in (X3,Y3, Z) relative-z. */ +// MCUXCLPKC_WAITFORREADY(); <== unnecessary, because VT2/VT3/VX0/VY0/VZ0/VX1/VY1 are not used in the FUP program before. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VT2, WEIER_VT3, WEIER_X2, WEIER_Y2); /* output: Prec2 */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X3, WEIER_Y3); /* input: PrecG; output: Prec3 */ + pOperands[WEIER_VZ0] = pOperands[WEIER_Z]; /* input: z'; output: z' */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, WEIER_XA, WEIER_YA); /* input: G */ + MCUXCLECC_FP_CALCFUP_ADD_ONLY(); + /* Hint: since z' (@ Z) = 1, the initial part of double-add FUP program (4 mul) can be skipped, */ + /* by manually copying G in (XA,YA) to (X2,Y2), which needs extra code size. */ + + /* Update z = z * z' = z' (skipped because z=1, and z' has been stored in Z). */ + /* Update Prec1: (XA,YA, 1) -> (X1,Y1, Z) Jacobian. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_Fup_Verify_Update_G_to_Prec1, + mcuxClEcc_Fup_Verify_Update_G_to_Prec1_LEN); + + /* Calculate P1 = u1 * G. */ + /* Input: 3 Prec_i, in (Xi,Yi, Z) Jacobian. */ + /* Output: P1 in (XA,YA, ZA) relative-z, w.r.t. Z. */ +// MCUXCLPKC_WAITFORREADY(); <==unnecessary, because VT is not used in the FUP program before. + pOperands[WEIER_VT] = pOperands[ECC_S2]; /* Use S2 as 5th temp. */ + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_Int_PointMult(ECC_S0, byteLenN * 8u)); + + /* Update z = z * z', so P1: (XA,YA, ZA) relative-z -> (XA,YA, Z) Jacobian. */ + MCUXCLPKC_FP_CALC_MC1_MM(ECC_T0, WEIER_Z, WEIER_ZA, ECC_P); + MCUXCLPKC_FP_CALC_OP1_OR_CONST(WEIER_Z, ECC_T0, 0u); + } + + /* Reset z' = 1 in MR (or initialize z' if u1 == 0). */ + MCUXCLPKC_FP_CALC_OP1_NEG(WEIER_ZA, ECC_P); + + + /**********************************************************/ + /* Calculate P2 = u2 * Q, and update P1 accordingly */ + /**********************************************************/ + + /* Import public key Q to (X1,Y1) affine NR. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_X1, pParam->pPublicKey, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(WEIER_Y1, pParam->pPublicKey + byteLenP, byteLenP); + + /* Check Q in (X1,Y1) affine NR. */ +// MCUXCLPKC_WAITFORREADY(); <== there is WaitForFinish in import function. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X1, WEIER_Y1); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckPubKeyStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_INTSTATUS_POINTCHECK_NOT_OK == pointCheckPubKeyStatus) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_PARAMS, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUXCLECC_FP_VERIFY_CALC_P1, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointCheckAffineNR), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if (MCUXCLECC_STATUS_OK != pointCheckPubKeyStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + else + { + /* Do nothing. */ + } + + /* Convert Q: (X1,Y1) affine NR -> (X0,Y0, Z) Jacobian. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR, + mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR_LEN); + + /* Calculate PrecQ = (2^(byteLenN *4)) * Q. */ + /* Input: Q in (X0,Y0, ZA=1) relative-z. */ + /* Output: PrecQ in (X3,Y3, ZA) relative-z. */ +// MCUXCLPKC_WAITFORREADY(); <== unnecessary, because VX0/VY0/VZ0/VZ/VX2/VY2/VZ2 are not used in the FUP program before. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X3, WEIER_Y3); /* output: PrecQ */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VZ0, WEIER_VZ, WEIER_ZA, WEIER_Z); /* input: z, z'; output z' */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX2, WEIER_VY2, WEIER_X0, WEIER_Y0); /* input: Q */ + pOperands[WEIER_VZ2] = pOperands[WEIER_ZA]; + pOperands[WEIER_VT] = pOperands[ECC_S2]; /* Use S2 as 5th temp. */ + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_RepeatPointDouble((byteLenN * 8u) / 2u)); + + /* Prepare 3 pre-computed points for Q, with the same z coordinate. */ + /* Input: Q in (X0, Y0, Z) Jacobian; */ + /* PrecQ in (X3, Y3, ZA) relative-z. */ + /* Output: Prec1 = Q (unchanged) in (X0, Y0, Z) Jacobian; */ + /* Prec2 = PrecQ (updated) in (X2, Y2, ZA) relative-z; */ + /* Prec3 = Q + PrecQ in (X3, Y3, ZA) relative-z. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VT2, WEIER_VT3, WEIER_X2, WEIER_Y2); /* output: Prec2 */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X3, WEIER_Y3); /* input: PrecQ; output: Prec3 */ + pOperands[WEIER_VZ0] = pOperands[WEIER_ZA]; /* input/output: z' */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, WEIER_X0, WEIER_Y0); /* input: Q */ + MCUXCLECC_FP_CALCFUP_ADD_ONLY(); + + /* Update Q: (X0,Y0, old Z) -> (X1,Y1, new Z) Jacobian; */ + /* P1: (XA,YA, old Z) -> (X0,Y0, new Z) Jacobian. */ + /* Update z = z * z'. */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z, + mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z_LEN); + + /* Calculate P2 = u2 * Q. */ + /* Input: 3 Prec_i, in (Xi,Yi, Z) Jacobian. */ + /* Output: P2 in (XA,YA, ZA) relative-z, w.r.t. Z. */ +// pOperands[WEIER_VT] = pOperands[ECC_S2]; <== the 5th temp WEIER_VT has been set before calling _RepeatPointDouble. + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEcc_Int_PointMult(ECC_S1, byteLenN * 8u)); + + /**********************************************************/ + /* Calculate (x1, y1) = P1 + P2, and check the result */ + /**********************************************************/ + + /* Calculate P2 += P1, if u1 != 0. */ + if (MCUXCLPKC_FLAG_ZERO != checkHashZero) + { + /* Input: P1 in (X0,Y0, Z) Jacobian; */ + /* P2 in (XA,YA, ZA) relative-z. */ + /* Output: P1 + P2 in (XA,YA, ZA) relative-z. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_XA, WEIER_YA); /* input: P2; output P1 + P2 */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VZ0, WEIER_VZ, WEIER_ZA, WEIER_Z); /* input: z' and z; output z' */ + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX1, WEIER_VY1, WEIER_X0, WEIER_Y0); /* input: P1 */ + MCUX_CSSL_FP_FUNCTION_CALL(statusPointFullAdd, mcuxClEcc_PointFullAdd()); + if (MCUXCLECC_STATUS_NEUTRAL_POINT == statusPointFullAdd) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUXCLECC_FP_VERIFY_CALC_P1, + MCUXCLECC_FP_VERIFY_CALC_P2, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEcc_PointFullAdd), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + } + + /* Convert P1 + P2 (or P2 if u1 == 0) to (X0,Y0), affine NR. */ + /* Calculate R = x mod n, in X1. */ + MCUXCLPKC_FP_CALC_MC1_MM(ECC_T0, WEIER_Z, WEIER_ZA, ECC_P); // t0 = z*z' * 256^LEN = z*z' in MR + MCUXCLMATH_FP_MODINV(ECC_T1, ECC_T0, ECC_P, ECC_T2); // t1 = (z*z')^(-1) * 256^(-LEN), use T2 as temp + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLPKC_FP_CALCFUP(mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR, + mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR_LEN); + + /* Check if P1 + P2 is valid. */ +// MCUXCLPKC_WAITFORREADY(); <== unnecessary, because VX0/VY0 are not used in the FUP program before. + MCUXCLECC_COPY_2OFFSETS(pOperands32, WEIER_VX0, WEIER_VY0, WEIER_X0, WEIER_Y0); + MCUX_CSSL_FP_FUNCTION_CALL(pointCheckStatus, mcuxClEcc_PointCheckAffineNR()); + if (MCUXCLECC_STATUS_OK != pointCheckStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + } + + /**********************************************************/ + /* Check r = (x mod n) robustly, and check p and n */ + /**********************************************************/ + + /* Check if imported signature R is equal to the calculated R. */ + MCUXCLPKC_FP_CALC_OP1_CMP(WEIER_X1, ECC_S3); + if (MCUXCLPKC_FLAG_ZERO != MCUXCLPKC_WAITFORFINISH_GETZERO()) + { + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_INVALID_SIGNATURE, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUXCLECC_FP_VERIFY_CALC_P1, + MCUXCLECC_FP_VERIFY_CALC_P2, + MCUXCLECC_FP_VERIFY_CALC_P1_ADD_P2, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Import prime p and order n again, and check (compare with) existing one. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T0, pParam->curveParam.pP, byteLenP); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(ECC_T1, pParam->curveParam.pN, byteLenN); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T0, ECC_P); + uint32_t zeroFlag_checkP = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + MCUXCLPKC_FP_CALC_OP1_CMP(ECC_T1, ECC_N); + uint32_t zeroFlag_checkN = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + /* Check signature R again by CPU. */ + uint8_t *pImportR = MCUXCLPKC_OFFSET2PTR(pOperands[ECC_S3]); + uint8_t *pCalcR = MCUXCLPKC_OFFSET2PTR(pOperands[WEIER_X1]); + mcuxCsslParamIntegrity_Checksum_t compareR_paramChkSum = mcuxCsslParamIntegrity_Protect(3u, pImportR, pCalcR, operandSize); + MCUX_CSSL_FP_FUNCTION_CALL(cmpareR_result, mcuxCsslMemory_Compare(compareR_paramChkSum, pImportR, pCalcR, operandSize)); + + if ( (MCUXCSSLMEMORY_STATUS_EQUAL == cmpareR_result) + && (zeroFlag_checkP == MCUXCLPKC_FLAG_ZERO) + && (zeroFlag_checkN == MCUXCLPKC_FLAG_ZERO) ) + { + + /**********************************************************/ + /* Clean up and exit */ + /**********************************************************/ + + /* Export the calculated r. */ + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pParam->pOutputR, WEIER_X1, byteLenN); + + mcuxClSession_freeWords_pkcWa(pSession, pCpuWorkarea->wordNumPkcWa); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, &pCpuWorkarea->pkcStateBackup, + mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, pCpuWorkarea->wordNumCpuWa); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClEcc_Verify, MCUXCLECC_STATUS_OK, MCUXCLECC_STATUS_FAULT_ATTACK, + MCUXCLECC_FP_VERIFY_INIT, + MCUXCLECC_FP_VERIFY_PREPARE_AND_CHECK, + MCUXCLECC_FP_VERIFY_CALC_P1, + MCUXCLECC_FP_VERIFY_CALC_P2, + MCUXCLECC_FP_VERIFY_CALC_P1_ADD_P2, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare), + /* Clean up and exit */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Results of checking R are inconsistent, or p or n got modified. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEcc_Verify, MCUXCLECC_STATUS_FAULT_ATTACK); +} + + diff --git a/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify_FUP.c b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify_FUP.c new file mode 100644 index 000000000..66554ad05 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEcc/src/mcuxClEcc_Weier_Verify_FUP.c @@ -0,0 +1,49 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEcc_Weier_Verify_FUP.c + * @brief FUP programs for Weierstrass curve ECDSA signature verification + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClEcc_FUP_Weier_Verify_Convert_G_PrecG_toMR[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x34u,0x74u,0xadu,0xfbu},{0x80u,0x00u,0x26u,0x16u,0x00u,0x20u},{0x80u,0x00u,0x27u,0x16u,0x00u,0x21u},{0x80u,0x00u,0x28u,0x16u,0x00u,0x2au},{0x80u,0x00u,0x29u,0x16u,0x00u,0x2bu}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_P1plusP2_toAffineNR_CalcR[10] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x20u,0x77u,0x74u,0xf6u},{0x80u,0x00u,0x1bu,0x16u,0x00u,0x19u},{0x80u,0x00u,0x19u,0x16u,0x00u,0x1bu},{0x80u,0x00u,0x1bu,0x1bu,0x00u,0x1du},{0x80u,0x00u,0x1du,0x19u,0x00u,0x1fu},{0x80u,0x00u,0x20u,0x1du,0x00u,0x26u},{0x80u,0x33u,0x26u,0x00u,0x00u,0x24u},{0x80u,0x2au,0x00u,0x24u,0x00u,0x24u},{0x80u,0x00u,0x21u,0x1fu,0x00u,0x25u},{0x80u,0x2au,0x01u,0x24u,0x01u,0x26u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Convert_pubkeyQ_toJacobianMR[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x1fu,0x94u,0xd1u,0xbdu},{0x80u,0x00u,0x23u,0x16u,0x00u,0x1fu},{0x80u,0x00u,0x1fu,0x23u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x23u,0x00u,0x1fu},{0x80u,0x00u,0x26u,0x1du,0x00u,0x24u},{0x80u,0x00u,0x27u,0x1fu,0x00u,0x25u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_InitZ_CalcU1U2[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x6bu,0x39u,0x6cu,0xf6u},{0x00u,0x09u,0x00u,0x00u,0x00u,0x23u},{0x80u,0x00u,0x1cu,0x1bu,0x01u,0x18u},{0x80u,0x00u,0x1eu,0x1bu,0x01u,0x1au},{0x80u,0x2au,0x01u,0x1au,0x01u,0x1au},{0x80u,0x2au,0x01u,0x18u,0x01u,0x18u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_G_to_Prec1[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x6bu,0x50u,0xcau,0x35u},{0x80u,0x00u,0x23u,0x23u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x23u,0x00u,0x1fu},{0x80u,0x00u,0x20u,0x1du,0x00u,0x26u},{0x80u,0x00u,0x21u,0x1fu,0x00u,0x27u}}; +const mcuxClPkc_FUPEntry_t mcuxClEcc_Fup_Verify_Update_pubkeyQ_P1_z[9] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x99u,0x16u,0x4du,0xffu},{0x80u,0x00u,0x22u,0x22u,0x00u,0x1du},{0x80u,0x00u,0x1du,0x22u,0x00u,0x1fu},{0x80u,0x00u,0x24u,0x1du,0x00u,0x26u},{0x80u,0x00u,0x25u,0x1fu,0x00u,0x27u},{0x80u,0x00u,0x20u,0x1du,0x00u,0x24u},{0x80u,0x00u,0x21u,0x1fu,0x00u,0x25u},{0x00u,0x1eu,0x00u,0x23u,0x03u,0x19u},{0x80u,0x00u,0x19u,0x22u,0x00u,0x23u}}; + + + +/* FUP program: calculates the scalars u1 and u2: + * u1 = hash * s^(-1), in range [0, n-1]; + * u2 = r * s^(-1), in range [0, n-1]. + */ + +/* FUP program: converts x- and y-coordinates of G and PrecG from NR to MR */ + +/* FUP program: update G: (XA,YA, 1) -> Prec1: (X1,Y1, Z) Jacobian.*/ + +/* FUP program: convert Q: (X1,Y1) affine NR -> (X0,Y0, Z) Jacobian. */ + +/* FUP program: update Q: (X0,Y0, old Z) -> (X1,Y1, new Z) Jacobian; */ +/* P1: (XA,YA, old Z) -> (X0,Y0, new Z) Jacobian; */ +/* update z = z * z'. */ + +/* FUP program: convert P1 + P2 (or P2 if u1 == 0) to affine NR; */ +/* calculate r = x mod n. */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h new file mode 100644 index 000000000..3b3c42053 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal.h @@ -0,0 +1,349 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Internal.h + * @brief Provide macros for mcuxClEls internal use. + * This header declares internal macros to deduplicate code and support for internal use only. */ + +#ifndef MCUXCLELS_INTERNAL_H_ +#define MCUXCLELS_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**** ****/ +/**** ELS Hardware Abstraction Layer ****/ +/**** ****/ + + +/** Asserts the correctness of the supplied parameters*/ +#define MCUXCLELS_INPUT_PARAM_CHECK(x) if((x)) { return MCUXCLELS_STATUS_SW_INVALID_PARAM; } +#define MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(funcid, x) \ +do \ +{ \ + if ((x)) \ + { \ + MCUX_CSSL_FP_FUNCTION_EXIT(funcid, MCUXCLELS_STATUS_SW_INVALID_PARAM); \ + } \ +} while (false) + +#define ELS_CMD_BIG_ENDIAN ((uint8_t) 0x01U) ///< ELS command option specifying big-endian byte order +#define ELS_CMD_LITTLE_ENDIAN ((uint8_t) 0x00U) ///< ELS command option specifying little-endian byte order + +// Utility code of mcuxClEls implementation + +/** Sets the variable-size input buffer from which the input 0 of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setInput0(const uint8_t *pInput, uint32_t inputSize) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0, (uint32_t) pInput); + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0_LEN, inputSize); +} + +/** Sets the fixed-size input buffer from which the input 0 of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setInput0_fixedSize(const uint8_t *pInput) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC0, (uint32_t) pInput); +} + +/** Sets the fixed-size input buffer from which the input 1 of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setInput1_fixedSize(const uint8_t *pInput) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC1, (uint32_t) pInput); +} + +/** Sets the variable-size input buffer from which the input 2 of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setInput2(const uint8_t *pInput, uint32_t inputSize) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2, (uint32_t) pInput); + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2_LEN, inputSize); +} + +/** Sets the fixed-size input buffer from which the input 2 of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setInput2_fixedSize(const uint8_t * pInput) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_SRC2, (uint32_t) pInput); +} + +/** Sets the variable-size output buffer to which the result of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setOutput(uint8_t *pOutput, uint32_t outputSize) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_RES0, (uint32_t) pOutput); + MCUXCLELS_SFR_WRITE(ELS_DMA_RES0_LEN, outputSize); +} + +/** Sets the output buffer to which the result of the ELS operation will be transferred via DMA. */ +static inline void mcuxClEls_setOutput_fixedSize(uint8_t *pOutput) +{ + MCUXCLELS_SFR_WRITE(ELS_DMA_RES0, (uint32_t) pOutput); +} + +/** Sets the ELS keystore index 0, for commands that access a single key. */ +static inline void mcuxClEls_setKeystoreIndex0(uint32_t index) +{ + MCUXCLELS_SFR_WRITE(ELS_KIDX0, index); +} + + +/** Sets the ELS keystore index 1, for commands that access 2 keys. */ +static inline void mcuxClEls_setKeystoreIndex1(uint32_t index) +{ + MCUXCLELS_SFR_WRITE(ELS_KIDX1, index); +} + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** Sets the ELS keystore index 2, for commands that access 3 keys. */ +static inline void mcuxClEls_setKeystoreIndex2(uint32_t index) +{ + MCUXCLELS_SFR_WRITE(ELS_KIDX2, index); +} +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** Sets the ELS requested key properties, for commands that create a key. */ +static inline void mcuxClEls_setRequestedKeyProperties(uint32_t properties) +{ + MCUXCLELS_SFR_WRITE(ELS_KPROPIN, properties); +} + +/** Starts an ELS command. */ +static inline void mcuxClEls_startCommand(uint32_t command, uint32_t cmdcfg0, uint32_t byteOrder) +{ + uint32_t ctrl = MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_CMD, command) + | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_START, 1u) + | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_EN, 1u) + | MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, BYTE_ORDER, byteOrder); + + MCUXCLELS_SFR_WRITE(ELS_CMDCFG0, cmdcfg0); + MCUXCLELS_SFR_WRITE(ELS_CTRL, ctrl); +} + + +/** Gets a specific field in the given SFR value, according to the given mask and shift value. + * @retval @c value of the requested field in the given ELS SFR value */ +static inline uint32_t mcuxClEls_getSfrField(uint32_t sfrValue, uint32_t mask, uint32_t shift) +{ + return ((uint32_t)(sfrValue & mask) >> shift); +} + +/** Set a specific field in the given SFR value, according to the given mask and shift value. + * The unrelated fields/bits will not be changed */ +static inline void mcuxClEls_setSfrField(volatile uint32_t *pSfr, uint32_t value, uint32_t mask, uint32_t shift) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address") + /* get the current value of the SFR and clear the bits that will be set */ + uint32_t sfrValue = *pSfr & (~mask); + /* set the bits and re-write the full value to the SFR */ + *pSfr = sfrValue | (((uint32_t)(value << shift)) & mask); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() +} + +/** Tests if the ELS is in BUSY state. + * @retval @c true if the ELS is in BUSY state */ +static inline bool mcuxClEls_isBusy(void) +{ + return (0u != MCUXCLELS_SFR_BITREAD(ELS_STATUS, ELS_BUSY) ); +} + + +/** Macros to access the bit fields for the ELS_STATUS SFR */ +#define MCUXCLELS_SFR_STATUS_ELS_BUSY ELS_BUSY +#define MCUXCLELS_SFR_STATUS_ELS_IRQ ELS_IRQ +#define MCUXCLELS_SFR_STATUS_ELS_ERR ELS_ERR +#define MCUXCLELS_SFR_STATUS_PRNG_RDY PRNG_RDY +#define MCUXCLELS_SFR_STATUS_ECDSA_VFY_STATUS ECDSA_VFY_STATUS +#define MCUXCLELS_SFR_STATUS_PPROT PPROT +#define MCUXCLELS_SFR_STATUS_DRBG_ENT_LVL DRBG_ENT_LVL +#define MCUXCLELS_SFR_STATUS_DTRNG_BUSY DTRNG_BUSY +#define MCUXCLELS_SFR_STATUS_ELS_LOCKED ELS_LOCKED + +/** Gets a specific field in the ELS_STATUS SFR. + * @param field: Any field name in MCUXCLELS_SFR_STATUS_* */ +#define MCUXCLELS_GET_STATUS_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_STATUS, field)) + + +/** Macros to access the bit fields for the ELS_CTRL SFR */ +#define MCUXCLELS_SFR_CTRL_ELS_EN ELS_EN +#define MCUXCLELS_SFR_CTRL_START ELS_START +#define MCUXCLELS_SFR_CTRL_RESET ELS_RESET +#define MCUXCLELS_SFR_CTRL_CMD ELS_CMD +#define MCUXCLELS_SFR_CTRL_BYTE_ORDER BYTE_ORDER + +/** Gets a specific field in the ELS_CTRL SFR. + * @param field: Any field name in MCUXCLELS_SFR_CTRL_* */ +#define MCUXCLELS_GET_CTRL_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_CTRL), MCUXCLELS_SFR_FIELD_MASK(ELS_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CTRL, field)) + +/** Sets a specific field in the ELS_CTRL SFR. The unrelated fields/bits will not be changed + * @param field: Any field name in MCUXCLELS_SFR_CTRL_* + * @param value: The value to set the requested SFR field to */ +#define MCUXCLELS_SET_CTRL_FIELD(field, value) \ + mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CTRL, field)) + + +/** Macros to access the bit fields for the ELS_CFG SFR */ +#define MCUXCLELS_SFR_CFG_ADCTRL ADCTRL +#define MCUXCLELS_SFR_CFG_SHA2_DIRECT SHA2_DIRECT + +/** Gets a specific field in the ELS_CFG SFR. + * @param field: Any field name in MCUXCLELS_SFR_CFG_* */ +#define MCUXCLELS_GET_CFG_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_CFG), MCUXCLELS_SFR_FIELD_MASK(ELS_CFG, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CFG, field)) + +/** Sets a specific field in the ELS_CFG SFR. The unrelated fields/bits will not be changed + * @param field: Any field name in MCUXCLELS_SFR_CFG_* + * @param value: The value to set the requested SFR field to */ +#define MCUXCLELS_SET_CFG_FIELD(field, value) \ + mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CFG), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CFG, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CFG, field)) + + +/** Macros to access the bit fields for the ELS_ERR_STATUS SFR */ +#define MCUXCLELS_SFR_ERR_STATUS_BUS_ERR BUS_ERR +#define MCUXCLELS_SFR_ERR_STATUS_OPN_ERR OPN_ERR +#define MCUXCLELS_SFR_ERR_STATUS_ALG_ERR ALG_ERR +#define MCUXCLELS_SFR_ERR_STATUS_ITG_ERR ITG_ERR +#define MCUXCLELS_SFR_ERR_STATUS_FLT_ERR FLT_ERR +#define MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR PRNG_ERR +#define MCUXCLELS_SFR_ERR_STATUS_ERR_LVL ERR_LVL +#define MCUXCLELS_SFR_ERR_STATUS_DTRNG_ERR DTRNG_ERR + +/** Gets a specific field in the ELS_ERR_STATUS SFR. + * @param field: Any field name in MCUXCLELS_SFR_ERR_STATUS_* */ +#define MCUXCLELS_GET_ERROR_STATUS_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_ERR_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_ERR_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_ERR_STATUS, field)) + +/** Checks if a specific error bit in the ELS_ERR_STATUS SFR is set. + * @retval @c true if the requested ELS error status bit is set */ +#define MCUXCLELS_IS_ERROR_BIT_SET(field) \ + (1u == MCUXCLELS_GET_ERROR_STATUS_FIELD(field)) + + +/** Macros to access the bit fields for the ELS_CMDCRC_CTRL SFR */ +#define MCUXCLELS_SFR_CMDCRC_CTRL_CMDCRC_RST CMDCRC_RST +#define MCUXCLELS_SFR_CMDCRC_CTRL_CMDCRC_EN CMDCRC_EN + +/** Sets a specific field in the ELS_CMDCRC_CTRL SFR. The unrelated fields/bits will not be changed + * @param field: Any field name in MCUXCLELS_SFR_CMDCRC_CTRL_* + * @param value: The value to set the requested SFR field to */ +#define MCUXCLELS_SET_CMDCRC_CTRL_FIELD(field, value) \ + mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_CMDCRC_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_CMDCRC_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_CMDCRC_CTRL, field)) + +/** Macros to access the bit fields for the ELS_SHA2_CTRL SFR */ +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_START SHA2_START +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_RST SHA2_RST +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_INIT SHA2_INIT +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_LOAD SHA2_LOAD +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_MODE SHA2_MODE +#define MCUXCLELS_SFR_SHA2_CTRL_SHA2_BYTE_ORDER SHA2_BYTE_ORDER + +/** Gets a specific field in the ELS_SHA2_CTRL SFR. + * @param field: Any field name in MCUXCLELS_SFR_SHA2_CTRL_* */ +#define MCUXCLELS_GET_SHA2_CTRL_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_SHA2_CTRL), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_CTRL, field)) + +/** Sets a specific field in the ELS_SHA2_CTRL SFR. The unrelated fields/bits will not be changed + * @param field: Any field name in MCUXCLELS_SFR_SHA2_CTRL_* + * @param value: The value to set the requested SFR field to */ +#define MCUXCLELS_SET_SHA2_CTRL_FIELD(field, value) \ + mcuxClEls_setSfrField(&MCUXCLELS_SFR_READ(ELS_SHA2_CTRL), (value), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_CTRL, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_CTRL, field)) + + +/** Macro to access the bit fields for the ELS_SHA2_STATUS SFR */ +#define MCUXCLELS_SFR_SHA2_STATUS_SHA2_BUSY SHA2_BUSY + +/** Gets a specific field in the ELS_SHA2_STATUS SFR. + * @param field: Any field name in MCUXCLELS_SFR_SHA2_STATUS_* */ +#define MCUXCLELS_GET_SHA2_STATUS_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_SHA2_STATUS), MCUXCLELS_SFR_FIELD_MASK(ELS_SHA2_STATUS, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_SHA2_STATUS, field)) + +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +/** + * Macros to access the bit fields for the ELS_GDET_EVTCNT SFR + * */ +#define MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT GDET_EVTCNT +#define MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE GDET_EVTCNT_CLR_DONE + +/** Gets a specific field in ELS_GDET_EVTCNT SFR. + * @param field: Any field name in MCUXCLELS_SFR_GDET_EVTCNT_* */ +#define MCUXCLELS_GET_GDET_EVTCNT_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_GDET_EVTCNT), MCUXCLELS_SFR_FIELD_MASK(ELS_GDET_EVTCNT, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_GDET_EVTCNT, field)) + +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + +/** Macros to access the bit fields for the ELS_INT_ENABLE SFR */ +#define MCUXCLELS_SFR_INT_ENABLE_INT_EN INT_EN +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +#define MCUXCLELS_SFR_INT_ENABLE_GDET_INT_EN GDET_INT_EN +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + +/** Gets a specific field in the ELS_INT_ENABLE SFR. + * @param field: Any field name in MCUXCLELS_SFR_INT_ENABLE_* */ +#define MCUXCLELS_GET_INT_ENABLE_FIELD(field) \ + mcuxClEls_getSfrField(MCUXCLELS_SFR_READ(ELS_INT_ENABLE), MCUXCLELS_SFR_FIELD_MASK(ELS_INT_ENABLE, field), MCUXCLELS_SFR_FIELD_SHIFT(ELS_INT_ENABLE, field)) + + +/* Total buffer size in output, which is used for cache maintenance */ +#define MCUXCLELS_HASH_BUFFER_SIZE(options) MCUXCLELS_HASH_BUFFER_SIZE_DIGEST(options) + MCUXCLELS_HASH_BUFFER_SIZE_RTF(options) +#define MCUXCLELS_HASH_BUFFER_SIZE_RTF(options) ( (MCUXCLELS_HASH_RTF_OUTPUT_ENABLE == options.bits.rtfoe) ? MCUXCLELS_HASH_RTF_OUTPUT_SIZE : 0u ) +#define MCUXCLELS_HASH_BUFFER_SIZE_DIGEST(options) ( (1u < options.bits.hashmd) ? MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 : MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 ) + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +extern uint32_t mcuxClEls_rng_drbg_block_counter; + +#define MCUXCLELS_RNG_DRBG_ITERATIVE_SEEDING_ITERATIONS 8u +#define MCUXCLELS_RNG_DRBG_BLOCK_COUNTER_THRESHOLD 4096u +#define MCUXCLELS_RNG_DRBG_ECCKEYGEN_INCREASE 10u +#define MCUXCLELS_RNG_DRBG_ECCSIGN_INCREASE 14u +#define MCUXCLELS_RNG_DRBG_ECCVERIFY_INCREASE 5u +#define MCUXCLELS_RNG_DRBG_KEYDELETE128_INCREASE 4u +#define MCUXCLELS_RNG_DRBG_KEYDELETE256_INCREASE 6u +#define MCUXCLELS_RNG_DRBG_DRBGREQUEST_INCREASE(outputLength) ((outputLength + 15u) / 16u) + +/** + * @brief This function resets the internal ELS DRBG block counter and reseeds the ELS DRBG + * using the iterative reseeding procedure + * + * @retval #MCUXCLELS_STATUS_SW_FAULT if a failure occurred + * @retval #MCUXCLELS_STATUS_OK on successful operation + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Dtrng_IterativeReseeding_Reseed) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_Reseed(const uint8_t *pDtrngConfig); +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + +/* Functional macro to check for ELS Level 1 errors */ +#define MCUXCLELS_LEVEL1_ERROR(returnCode) (MCUXCLELS_STATUS_HW_OPERATIONAL == (returnCode)) || (MCUXCLELS_STATUS_HW_ALGORITHM == (returnCode)) || (MCUXCLELS_STATUS_HW_BUS == (returnCode)) + +/** read from ELS PRNG SFR. */ +static inline uint32_t mcuxClEls_readPrngOut(void) +{ + return MCUXCLELS_SFR_READ(ELS_PRNG_DATOUT); +} + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h new file mode 100644 index 000000000..2b15e4992 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_Internal_mapping.h @@ -0,0 +1,105 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Internal_mapping.h + * @brief Header providing mapping for legacy definitions (with CSS) + */ + +#ifndef MCUXCLELS_INTERNAL_MAPPING_H_ +#define MCUXCLELS_INTERNAL_MAPPING_H_ + +#if !defined(ELS_KS_CNT) +#define ELS_KS_CNT CSS_KS_CNT +#endif + +#if !defined(ID_CFG_ELS_CMD_AUTH_CIPHER) +#define ID_CFG_ELS_CMD_AUTH_CIPHER ID_CFG_CSS_CMD_AUTH_CIPHER +#endif +#if !defined(ID_CFG_ELS_CMD_CHAL_RESP_GEN) +#define ID_CFG_ELS_CMD_CHAL_RESP_GEN ID_CFG_CSS_CMD_CHAL_RESP_GEN +#endif +#if !defined(ID_CFG_ELS_CMD_CIPHER) +#define ID_CFG_ELS_CMD_CIPHER ID_CFG_CSS_CMD_CIPHER +#endif +#if !defined(ID_CFG_ELS_CMD_CKDF) +#define ID_CFG_ELS_CMD_CKDF ID_CFG_CSS_CMD_CKDF +#endif +#if !defined(ID_CFG_ELS_CMD_CMAC) +#define ID_CFG_ELS_CMD_CMAC ID_CFG_CSS_CMD_CMAC +#endif +#if !defined(ID_CFG_ELS_CMD_DRBG_TEST) +#define ID_CFG_ELS_CMD_DRBG_TEST ID_CFG_CSS_CMD_DRBG_TEST +#endif +#if !defined(ID_CFG_ELS_CMD_DTRNG_CFG_LOAD) +#define ID_CFG_ELS_CMD_DTRNG_CFG_LOAD ID_CFG_CSS_CMD_DTRNG_CFG_LOAD +#endif +#if !defined(ID_CFG_ELS_CMD_DTRNG_EVAL) +#define ID_CFG_ELS_CMD_DTRNG_EVAL ID_CFG_CSS_CMD_DTRNG_EVAL +#endif +#if !defined(ID_CFG_ELS_CMD_DTRNG_PRVL_CFG_LOAD) +#define ID_CFG_ELS_CMD_DTRNG_PRVL_CFG_LOAD ID_CFG_CSS_CMD_DTRNG_PRVL_CFG_LOAD +#endif +#if !defined(ID_CFG_ELS_CMD_ECKXH) +#define ID_CFG_ELS_CMD_ECKXH ID_CFG_CSS_CMD_ECKXH +#endif +#if !defined(ID_CFG_ELS_CMD_ECSIGN) +#define ID_CFG_ELS_CMD_ECSIGN ID_CFG_CSS_CMD_ECSIGN +#endif +#if !defined(ID_CFG_ELS_CMD_ECVFY) +#define ID_CFG_ELS_CMD_ECVFY ID_CFG_CSS_CMD_ECVFY +#endif +#if !defined(ID_CFG_ELS_CMD_GDET_CFG_LOAD) +#define ID_CFG_ELS_CMD_GDET_CFG_LOAD ID_CFG_CSS_CMD_GDET_CFG_LOAD +#endif +#if !defined(ID_CFG_ELS_CMD_GDET_TRIM) +#define ID_CFG_ELS_CMD_GDET_TRIM ID_CFG_CSS_CMD_GDET_TRIM +#endif +#if !defined(ID_CFG_ELS_CMD_HASH) +#define ID_CFG_ELS_CMD_HASH ID_CFG_CSS_CMD_HASH +#endif +#if !defined(ID_CFG_ELS_CMD_HKDF) +#define ID_CFG_ELS_CMD_HKDF ID_CFG_CSS_CMD_HKDF +#endif +#if !defined(ID_CFG_ELS_CMD_HMAC) +#define ID_CFG_ELS_CMD_HMAC ID_CFG_CSS_CMD_HMAC +#endif +#if !defined(ID_CFG_ELS_CMD_KDELETE) +#define ID_CFG_ELS_CMD_KDELETE ID_CFG_CSS_CMD_KDELETE +#endif +#if !defined(ID_CFG_ELS_CMD_KEYGEN) +#define ID_CFG_ELS_CMD_KEYGEN ID_CFG_CSS_CMD_KEYGEN +#endif +#if !defined(ID_CFG_ELS_CMD_KEYIN) +#define ID_CFG_ELS_CMD_KEYIN ID_CFG_CSS_CMD_KEYIN +#endif +#if !defined(ID_CFG_ELS_CMD_KEYOUT) +#define ID_CFG_ELS_CMD_KEYOUT ID_CFG_CSS_CMD_KEYOUT +#endif +#if !defined(ID_CFG_ELS_CMD_KEYPROV) +#define ID_CFG_ELS_CMD_KEYPROV ID_CFG_CSS_CMD_KEYPROV +#endif +#if !defined(ID_CFG_ELS_CMD_TLS) +#define ID_CFG_ELS_CMD_TLS ID_CFG_CSS_CMD_TLS +#endif + +#if (!defined(ID_CFG_ELS_CMD_RND_REQ)) && defined(ID_CFG_CSS_CMD_RND_REQ) +#define ID_CFG_ELS_CMD_RND_REQ ID_CFG_CSS_CMD_RND_REQ +#endif + +#if (!defined(ID_CFG_ELS_CMD_DRBG_REQ)) && defined(ID_CFG_CSS_CMD_DRBG_REQ) +#define ID_CFG_ELS_CMD_DRBG_REQ ID_CFG_CSS_CMD_DRBG_REQ +#endif + + +#endif /* MCUXCLELS_INTERNAL_MAPPING_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h new file mode 100644 index 000000000..961b93b29 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/internal/mcuxClEls_SfrAccess.h @@ -0,0 +1,92 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_SfrAccess.h + * @brief Provide macros for mcuxClEls internal use. + * This header declares internal macros to deduplicate code and support for internal use only. */ + +#ifndef MCUXCLELS_SFRACCESS_H_ +#define MCUXCLELS_SFRACCESS_H_ + +#include // Exported features flags header +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**** ****/ +/**** ELS Hardware Abstraction Layer ****/ +/**** ****/ + +/** + * Definitions for accessing ELS SFRs via, e.g., IP_ELS->STATUS. + */ + +/** Helper macros for constructing SFR field name constants */ +#define MCUXCLELS_PASTE(a,b) a ## b +#define MCUXCLELS_CONCAT(a,b) MCUXCLELS_PASTE(a,b) +#define MCUXCLELS_SFR_FIELD(prefix,sfr,field) MCUXCLELS_CONCAT(prefix, sfr ## _ ## field) + +/** Helper macros to get the mask and shift values for a specific ELS SFR field */ +#define MCUXCLELS_SFR_FIELD_MASK(sfr, field) MCUXCLELS_CONCAT(MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field), _MASK) +#define MCUXCLELS_SFR_FIELD_SHIFT(sfr, field) MCUXCLELS_CONCAT(MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field), _SHIFT) +#define MCUXCLELS_SFR_FIELD_FORMAT(sfr, field, val) (MCUXCLELS_SFR_FIELD(ELS_SFR_PREFIX,sfr,field) (val)) + +/**********************************************************/ +/* Helper macros for ELS SFR access */ +/**********************************************************/ + +/** Read from ELS SFR */ +#define MCUXCLELS_SFR_READ(sfr) (ELS_SFR_BASE->ELS_SFR_NAME(sfr)) + +/** Write to ELS SFR */ +#define MCUXCLELS_SFR_WRITE(sfr, value) \ + do{ \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address") \ + ELS_SFR_BASE->ELS_SFR_NAME(sfr) = (value); \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() \ + } while(false) + +/** Read from ELS SFR bit field */ +#define MCUXCLELS_SFR_BITREAD(sfr, bit) \ + ((ELS_SFR_BASE->ELS_SFR_NAME(sfr) & MCUXCLELS_SFR_FIELD_MASK(sfr, bit)) >> MCUXCLELS_SFR_FIELD_SHIFT(sfr, bit)) + +/** Set bit field of ELS SFR (read-modify-write) */ +#define MCUXCLELS_SFR_BITSET(sfr, bit) \ + do{ ELS_SFR_BASE->ELS_SFR_NAME(sfr) |= MCUXCLELS_SFR_FIELD_MASK(sfr, bit); } while(false) + +/** Clear bit field of ELS SFR (read-modify-write) */ +#define MCUXCLELS_SFR_BITCLEAR(sfr, bit) \ + do{ ELS_SFR_BASE->ELS_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLELS_SFR_FIELD_MASK(sfr, bit)); } while(false) + +/** Set value of multi-bit field of ELS SFR (read-modify-write) */ +#define MCUXCLELS_SFR_BITVALSET(sfr, bit, val) \ + do{ \ + uint32_t temp = ELS_SFR_BASE->ELS_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLELS_SFR_FIELD_MASK(sfr, bit)); \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address") \ + ELS_SFR_BASE->ELS_SFR_NAME(sfr) = temp | ((val) << MCUXCLELS_SFR_FIELD_SHIFT(sfr, bit)) & MCUXCLELS_SFR_FIELD_MASK(sfr, bit); \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() \ + } while(false) + +/**** ------------------------------ ****/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_SFRACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h new file mode 100644 index 000000000..c475610fa --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls.h @@ -0,0 +1,257 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls.h + * @brief Top-level include file for the ELS driver + * + * This includes headers for all of the functionality provided by the ELS IP. + * + * @defgroup mcuxClEls mcuxClEls + * @brief ELS driver + * + * This component abstracts the hardware access to the ELS IP. + * The library exposes the following hardware functionality: + *
    + *
  1. COMMON + *
      + *
    • Determine information of the underlying ELS hardware IP + *
      • #mcuxClEls_GetHwVersion
      + * @if MCUXCL_FEATURE_ELS_HWCONFIG + *
      • #mcuxClEls_GetHwConfig
      + * @endif + *
      • #mcuxClEls_GetHwState
      + *
    • ELS enabling, disabling, and software reset + *
      • #mcuxClEls_Enable_Async
      + *
      • #mcuxClEls_Reset_Async
      + *
      • #mcuxClEls_Disable
      + *
    • Interrupt management + *
      • #mcuxClEls_SetIntEnableFlags
      + *
      • #mcuxClEls_GetIntEnableFlags
      + *
      • #mcuxClEls_ResetIntFlags
      + *
      • #mcuxClEls_SetIntFlags
      + *
    • Wait for completion of an ELS operation + *
      • #mcuxClEls_WaitForOperation
      + *
      • #mcuxClEls_LimitedWaitForOperation
      + *
    • Error handling + *
      • #mcuxClEls_ResetErrorFlags
      + *
      • #mcuxClEls_GetErrorCode
      + *
      • #mcuxClEls_GetErrorLevel
      + *
    • Random delay feature for AES based operations + *
      • #mcuxClEls_SetRandomStartDelay
      + *
      • #mcuxClEls_GetRandomStartDelay
      + * @if MCUXCL_FEATURE_ELS_LOCKING + *
    • ELS Locking + *
      • #mcuxClEls_GetLock
      + *
      • #mcuxClEls_ReleaseLock
      + *
      • #mcuxClEls_IsLocked
      + *
      • #mcuxClEls_SetMasterUnlock
      + * @endif + * @if MCUXCL_FEATURE_ELS_RESP_GEN + *
    • Calculate response to a hardware generated challenge + *
      • #mcuxClEls_RespGen_Async
      + * @endif + * @if MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK + *
    • Final Address Readback (security feature) + *
      • #mcuxClEls_GetLastDmaAddress
      + * @endif + * @if MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + *
    • Final Address Compare (security feature) + *
      • #mcuxClEls_CompareDmaFinalOutputAddress
      + * @endif + *
    + *
  2. CRC + *
      + *
    • Command CRC checks + *
      • #mcuxClEls_ConfigureCommandCRC
      + *
      • #mcuxClEls_GetCommandCRC
      + *
      • #mcuxClEls_VerifyVsRefCRC
      + *
      • #mcuxClEls_UpdateRefCRC
      + *
    + *
  3. HASH + *
      + *
    • SHA-2 hashing + *
      • #mcuxClEls_Hash_Async
      + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + *
    • SHA-2 hashing in direct mode + *
      • #mcuxClEls_ShaDirect_Enable
      + *
      • #mcuxClEls_ShaDirect_Disable
      + *
      • #mcuxClEls_Hash_ShaDirect
      + * @endif + *
    + * @if MCUXCL_FEATURE_ELS_HMAC + *
  4. HMAC (Keyed-Hash Message Authentication Code) + *
      + *
    • HMAC + *
      • #mcuxClEls_Hmac_Async
      + *
    + * @endif + * @if MCUXCL_FEATURE_ELS_CMAC + *
  5. CMAC (Cipher-Based Message Authentication Code) + *
      + *
    • CMAC + *
      • #mcuxClEls_Cmac_Async
      + *
    + * @endif + *
  6. CIPHER (Symmetric Encryption) + *
      + *
    • AES + *
      • #mcuxClEls_Cipher_Async
      + *
    + * @if MCUXCL_FEATURE_ELS_AEAD + *
  7. AEAD (Authenticated Encryption with Associated Data) + *
      + *
    • Authenticated Encryption with Associated Data + *
        + *
      • #mcuxClEls_Aead_Init_Async + *
      • #mcuxClEls_Aead_UpdateAad_Async + *
      • #mcuxClEls_Aead_UpdateData_Async + *
      • #mcuxClEls_Aead_Finalize_Async + *
      + *
    + * @endif + *
  8. KEY MANAGEMENT + *
      + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE + *
    • Key deletion + *
      • #mcuxClEls_KeyDelete_Async
      + * @endif + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV + *
    • Key provisioning + *
      • #mcuxClEls_KeyProvision_Async
      + * @endif + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM + *
    • Key provisioning (ROM) + *
      • #mcuxClEls_KeyProvisionRom_Async
      + * @endif + *
    • Key import + *
      • #mcuxClEls_KeyImport_Async
      + * @if MCUXCL_FEATURE_ELS_PUK_INTERNAL + *
    • Public key import + *
      • #mcuxClEls_KeyImportPuk_Async
      + * @endif + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT + *
    • Key export + *
      • #mcuxClEls_KeyExport_Async
      + * @endif + *
    • Key properties + *
      • #mcuxClEls_GetKeyProperties
      + *
    + * @if MCUXCL_FEATURE_ELS_RNG + *
  9. RNG + *
      + *
    • Random data generation using DRBG + *
      • #mcuxClEls_Rng_DrbgRequest_Async
      + * @if MCUXCL_FEATURE_ELS_RND_RAW + *
    • Get raw (unprocessed) random data from the DTRNG + *
      • #mcuxClEls_Rng_DrbgRequestRaw_Async
      + * @endif + *
    • FIPS CAVP test mode + *
      • #mcuxClEls_Rng_DrbgTestInstantiate_Async
      + *
      • #mcuxClEls_Rng_DrbgTestExtract_Async
      + *
      • #mcuxClEls_Rng_DrbgTestAesEcb_Async
      + *
      • #mcuxClEls_Rng_DrbgTestAesCtr_Async
      + *
    • Configuration of the DTRNG + *
      • #mcuxClEls_Rng_Dtrng_ConfigLoad_Async
      + *
      • #mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async
      + *
    • PRNG + * @if MCUXCL_FEATURE_ELS_PRND_INIT + *
      • #mcuxClEls_Prng_Init_Async
      + * @endif + *
      • #mcuxClEls_Prng_GetRandomWord
      + *
      • #mcuxClEls_Prng_GetRandom
      + *
    + * @endif + *
  10. ECC (Elliptic Curve Cryptography) + *
      + *
    • ECC Key generation + *
      • #mcuxClEls_EccKeyGen_Async
      + * @if MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE + *
    • ECC key exchange + *
      • #mcuxClEls_EccKeyExchange_Async
      + * @if MCUXCL_FEATURE_ELS_PUK_INTERNAL + *
      • #mcuxClEls_EccKeyExchangeInt_Async
      + * @endif + * @endif + *
    • ECC signature generation + *
      • #mcuxClEls_EccSign_Async
      + *
    • ECC signature verification + *
      • #mcuxClEls_EccVerify_Async
      + * @if MCUXCL_FEATURE_ELS_PUK_INTERNAL + *
      • #mcuxClEls_EccVerifyInt_Async
      + * @endif + *
    + *
  11. KEY DERIVATION + *
      + *
    • Key derivation + *
        + * @if MCUXCL_FEATURE_ELS_CKDF + *
      • #mcuxClEls_Ckdf_Sp800108_Async + * @if MCUXCL_FEATURE_ELS_CKDF_SP80056C + *
      • #mcuxClEls_Ckdf_Sp80056c_Extract_Async + *
      • #mcuxClEls_Ckdf_Sp80056c_Expand_Async + * @endif + * @endif + * @if MCUXCL_FEATURE_ELS_HKDF + *
      • #mcuxClEls_Hkdf_Rfc5869_Async + *
      • #mcuxClEls_Hkdf_Sp80056c_Async + * @endif + *
      + * @if MCUXCL_FEATURE_ELS_TLS + *
    • Master Key and Session Key derivation + *
        + *
      • #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async + *
      • #mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async + *
      + * @endif + *
    + * @if MCUXCL_FEATURE_ELS_GLITCHDETECTOR + *
  12. ELS Glitch Detector control + *
      + *
    • #mcuxClEls_GlitchDetector_LoadConfig_Async + *
    • #mcuxClEls_GlitchDetector_Trim_Async + *
    • #mcuxClEls_GlitchDetector_GetEventCounter + *
    • #mcuxClEls_GlitchDetector_ResetEventCounter + *
    + * @endif + *
+ * + * After each call to a function ending in _Async, one of the waiting functions #mcuxClEls_WaitForOperation or #mcuxClEls_LimitedWaitForOperation must be called to ensure completion. + * The waiting functions may fail, e.g., when the ELS enters an error state. + */ + +#ifndef MCUXCLELS_H_ +#define MCUXCLELS_H_ + +#include // Exported features flags header +#include + +#include +#include +#ifdef MCUXCL_FEATURE_ELS_CMD_CRC +#include +#endif /* MCUXCL_FEATURE_ELS_CMD_CRC */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +#include +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + +#endif /* MCUXCLELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h new file mode 100644 index 000000000..218554214 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Aead.h @@ -0,0 +1,457 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Aead.h + * @brief ELS header for Authenticated Encryption with Associated Data (AEAD). + * + * This header exposes functions that enable using the ELS for Authenticated Encryption with Associated Data (AEAD). + * The AEAD algorithm supported by ELS is AES in Galois/Counter Mode (GCM), as described in NIST Special Publication + * 800-38D. + */ + + /** + * @defgroup mcuxClEls_Aead mcuxClEls_Aead + * @brief This part of the @ref mcuxClEls driver supports Authenticated Encryption with Associated Data (AEAD). + * @ingroup mcuxClEls + * @{ + */ +#ifndef MCUXCLELS_AEAD_H_ +#define MCUXCLELS_AEAD_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_Aead_Macros mcuxClEls_Aead_Macros + * @brief Defines all macros of @ref mcuxClEls_Aead + * @ingroup mcuxClEls_Aead + * @{ + */ +/** + * @defgroup MCUXCLELS_AEAD_ MCUXCLELS_AEAD_ + * @brief Defines macros used to initialize #mcuxClEls_AeadOption_t + * @ingroup mcuxClEls_Aead_Macros + * @{ + */ +#define MCUXCLELS_AEAD_ENCRYPT (0x00U) ///< Set #mcuxClEls_AeadOption_t.dcrpt to this value to encrypt data +#define MCUXCLELS_AEAD_DECRYPT (0x01U) ///< Set #mcuxClEls_AeadOption_t.dcrpt to this value to decrypt data + +#define MCUXCLELS_AEAD_STATE_IN_DISABLE (0x00U) ///< Set #mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from ELS +#define MCUXCLELS_AEAD_STATE_IN_ENABLE (0x01U) ///< Set #mcuxClEls_AeadOption_t.acpsie to this value to load the GCM state from the context + +#define MCUXCLELS_AEAD_LASTINIT_TRUE (0x01U) ///< Set #mcuxClEls_AeadOption_t.lastinit to this value if this is the last call to init +#define MCUXCLELS_AEAD_LASTINIT_FALSE (0x00U) ///< Set #mcuxClEls_AeadOption_t.lastinit to this value if this is not the last call to init + +#define MCUXCLELS_AEAD_EXTERN_KEY (0x01U) ///< Set #mcuxClEls_AeadOption_t.extkey to this value to use an external key +#define MCUXCLELS_AEAD_INTERN_KEY (0x00U) ///< Set #mcuxClEls_AeadOption_t.extkey to this value to use a key from the ELS keystore + +#define MCUXCLELS_AEAD_ACPMOD_INIT (0x00U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Init mode. For internal use +#define MCUXCLELS_AEAD_ACPMOD_AADPROC (0x01U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Process Additional Authenticated Data mode. For internal use +#define MCUXCLELS_AEAD_ACPMOD_MSGPROC (0x02U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Process Message mode. For internal use +#define MCUXCLELS_AEAD_ACPMOD_FINAL (0x03U) ///< Set #mcuxClEls_AeadOption_t.acpmod to this value for Finalize mode. For internal use + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_AEAD_STATE_OUT_ENABLE (0x01U) ///< Set #mcuxClEls_AeadOption_t.acpsoe to this value to save the state to the context. For internal use +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ +/** + * @} + */ + +#define MCUXCLELS_AEAD_IV_BLOCK_SIZE 16U ///< AES-GCM IV Granularity: 128 bit (16 bytes) +#define MCUXCLELS_AEAD_AAD_BLOCK_SIZE 16U ///< AES-GCM AAD Granularity: 128 bit (16 bytes) +#define MCUXCLELS_AEAD_TAG_SIZE 16U ///< tag size: Tag generation supports only a 128 bit wide tag (16 bytes) +#define MCUXCLELS_AEAD_CONTEXT_SIZE 80U ///< context size: 512 bit (64 bytes) + 16 bytes for finalize +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Aead_Types mcuxClEls_Aead_Types + * @brief Defines all types of @ref mcuxClEls_Aead + * @ingroup mcuxClEls_Aead + * @{ + */ +/** + * @brief Command option bit field for #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async, #mcuxClEls_Aead_UpdateData_Async and #mcuxClEls_Aead_Finalize_Async. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_AeadOption_t word-wise + struct + { + uint32_t :1; ///< RFU + uint32_t dcrpt :1; ///< Defines if encryption or decryption shall be performed + uint32_t acpmod :2; ///< This field is managed internally +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + uint32_t acpsoe :1; ///< This field is managed internally +#else + uint32_t :1; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + uint32_t acpsie :1; ///< This field is managed internally + uint32_t msgendw :4; ///< The size of the last data block (plain/cipher text) in bytes, without padding + uint32_t lastinit :1; ///< Defines whether this is the last call to init + uint32_t :2; ///< RFU + uint32_t extkey :1; ///< Defines whether an external key shall be used + uint32_t :18; ///< RFU + } bits; ///< Access #mcuxClEls_AeadOption_t bit-wise +} mcuxClEls_AeadOption_t; +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Aead_Functions mcuxClEls_Aead_Functions + * @brief Defines all functions of @ref mcuxClEls_Aead + * @ingroup mcuxClEls_Aead + * @{ + */ + +/** + * @brief AES-GCM initialization + * + * This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV @p pIV and the key (@p pKey or @p keyIdx). + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The AEAD command options. For more information, see #mcuxClEls_AeadOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore + * @param[in] pKey Pointer to the key + * @param[in] keyLength Size of @p pKey in bytes + * @param[in] pIV Pointer to memory area that contains the IV + * @param[in] ivLength Size of @p pIV in bytes, with padding + * @param [out] pAeadCtx Pointer to the memory area that receives the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY
+ *
@p keyIdx is ignored. + * + * @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).
+ * + *
@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY
+ *
@p keyIdx must be a valid key index with the correct usage rights. + * + * @p pKey and @p keyLength are ignored.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Init_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Init_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pIV, + size_t ivLength, + uint8_t * pAeadCtx + ); + +/** + * @brief AES-GCM partial initialization + * + * This is the first stage of AEAD encryption/decryption. This generates the initial context out of the IV @p pIV and the key (@p pKey or @p keyIdx). + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The AEAD command options. For more information, see #mcuxClEls_AeadOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore + * @param[in] pKey Pointer to the key + * @param[in] keyLength Size of @p pKey in bytes + * @param[in] pIV Pointer to memory area that contains the IV + * @param[in] ivLength Size of @p pIV in bytes, with padding + * @param [out] pAeadCtx Pointer to the memory area that receives the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY
+ *
@p keyIdx is ignored. + * + * @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).
+ * + *
@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY
+ *
@p keyIdx must be a valid key index with the correct usage rights. + * + * @p pKey and @p keyLength are ignored.
+ * + *
@p options.msgendw
+ *
This field is ignored
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_PartialInit_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_PartialInit_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pIV, + size_t ivLength, + uint8_t * pAeadCtx + ); + +/** + * @brief AES-GCM update of the Additional Authenticated Data (AAD) + * + * This is the second stage of AEAD encryption/decryption. This updates the internal authentication tag with the AAD. + * + * #mcuxClEls_Aead_Init_Async must have been called before calling this function. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The AEAD command options. For more information, see #mcuxClEls_AeadOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore + * @param[in] pKey Pointer to the key + * @param[in] keyLength Size of @p pKey in bytes + * @param[in] pAad Memory area that contains the AAD + * @param[in] aadLength Length of the @p pAad in bytes with padding + * @param[in, out] pAeadCtx Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY
+ *
@p keyIdx is ignored. + * + * @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).
+ * + *
@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY
+ *
@p keyIdx must be a valid key index with the correct usage rights. + * + * @p pKey and @p keyLength are ignored.
+ * + *
@p options.msgendw
+ *
This field is ignored
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateAad_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateAad_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pAad, + size_t aadLength, + uint8_t * pAeadCtx + ); + +/** + * @brief AES-GCM update of the encrypted data + * + * This is the third stage of AEAD encryption/decryption. This processes the given plaintext (in case of encryption) + * or ciphertext (in case of decryption) and outputs the ciphertext (in case of encryption) or plaintext (in case of decryption). + * + * #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async must have been called before calling this function. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The AEAD command options. For more information, see #mcuxClEls_AeadOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore + * @param[in] pKey Pointer to the key + * @param[in] keyLength Size of @p pKey in bytes + * @param[in] pInput Pointer to the memory location of the data to be processed + * @param[in] inputLength Size of @p pInput in bytes with padding + * @param [out] pOutput Pointer to the processed data memory location + * @param[in, out] pAeadCtx Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY
+ *
@p keyIdx is ignored. + * + * @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).
+ * + *
@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY
+ *
@p keyIdx must be a valid key index with the correct usage rights. + * + * @p pKey and @p keyLength are ignored.
+ * + *
@p options.msgendw
+ *
This field has to be set to the size of the last data block (plain/cipher text) in bytes, without padding. + * In case the last block is a full block, this field has to be set to 0.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_UpdateData_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateData_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pOutput, + uint8_t * pAeadCtx + ); + +/** + * @brief AES-GCM final encryption/decryption + * + * This is the fourth stage of AEAD encryption/decryption. This updates the authentication tag with the final data + * length block and outputs the tag at the desired location. + * + * #mcuxClEls_Aead_Init_Async, #mcuxClEls_Aead_UpdateAad_Async and #mcuxClEls_Aead_UpdateData_Async must have been called + * before calling this function. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The AEAD command options. For more information, see #mcuxClEls_AeadOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore + * @param[in] pKey Pointer to the key + * @param[in] keyLength Size of @p pKey in bytes + * @param[in] aadLength Length of the complete Additional Authenticated Data (AAD) in bytes, without padding. + * @param[in] dataLength Length of the complete plaintext/ciphertext in bytes, without padding. + * @param [out] pTag Pointer where the resulting tag will be stored + * @param[in] pAeadCtx Pointer to the AEAD context structure. Must be at least #MCUXCLELS_AEAD_CONTEXT_SIZE bytes long. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_AEAD_EXTERN_KEY
+ *
@p keyIdx is ignored. + * + * @p pKey must be a valid AES key and @p keyLength a valid AES key size (see @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_).
+ * + *
@p options.extkey == #MCUXCLELS_AEAD_INTERN_KEY
+ *
@p keyIdx must be a valid key index with the correct usage rights. + * + * @p pKey and @p keyLength are ignored.
+ * + *
@p options.msgendw
+ *
This field is ignored
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Aead_Finalize_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Finalize_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + size_t aadLength, + size_t dataLength, + uint8_t * pTag, + uint8_t * pAeadCtx + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_AEAD_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h new file mode 100644 index 000000000..702ccaeb0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cipher.h @@ -0,0 +1,239 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Cipher.h + * @brief ELS header for symmetric ciphers. + * + * This header exposes functions that enable using the ELS for symmetric encryption/decryption. + * The cipher algorithm supported by ELS is AES in the following modes: + * - Electronic Code Book (ECB) mode, + * - Cipher Block Chaining (CBC) mode, and + * - Counter (CTR) mode. + * Supported key sizes are 128, 192, and 256 bits. + */ + +/** + * @defgroup mcuxClEls_Cipher mcuxClEls_Cipher + * @brief This part of the @ref mcuxClEls driver supports functionality for symmetric ciphers + * @ingroup mcuxClEls + * @{ + */ + +#ifndef MCUXCLELS_CIPHER_H_ +#define MCUXCLELS_CIPHER_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_Cipher_Macros mcuxClEls_Cipher_Macros + * @brief Defines all macros of @ref mcuxClEls_Cipher + * @ingroup mcuxClEls_Cipher + * @{ + */ + +/** + * @defgroup MCUXCLELS_CIPHER_ MCUXCLELS_CIPHER_ + * @brief Defines valid options to be used by #mcuxClEls_CipherOption_t + * @ingroup mcuxClEls_Cipher_Macros + * + * Valid AES key sizes in bytes + * @{ + */ + +#define MCUXCLELS_CIPHER_ENCRYPT 0U ///< Set this option at #mcuxClEls_CipherOption_t.dcrpt to perform an encryption +#define MCUXCLELS_CIPHER_DECRYPT 1U ///< Set this option at #mcuxClEls_CipherOption_t.dcrpt to perform a decryption + +#define MCUXCLELS_CIPHER_STATE_OUT_ENABLE 1U ///< Set this option at #mcuxClEls_CipherOption_t.cphsoe to export the internal ELS state to @p pIV +#define MCUXCLELS_CIPHER_STATE_OUT_DISABLE 0U ///< Set this option at #mcuxClEls_CipherOption_t.cphsoe to not export the internal ELS state + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CIPHER_STATE_IN_ENABLE 1U ///< Set this option at #mcuxClEls_CipherOption_t.cphsie to import an external ELS state from @p pIV +#define MCUXCLELS_CIPHER_STATE_IN_DISABLE 0U ///< Set this option at #mcuxClEls_CipherOption_t.cphsie to not import an external ELS state +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +#define MCUXCLELS_CIPHER_EXTERNAL_KEY 1U ///< Set this option at #mcuxClEls_CipherOption_t.extkey to use a key located in CPU memory provided by @p pKey +#define MCUXCLELS_CIPHER_INTERNAL_KEY 0U ///< Set this option at #mcuxClEls_CipherOption_t.extkey to use a key located in ELS keystore privded by @p keyIdx + +#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB 0x00U ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Electornic Code Book (ECB) mode +#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC 0x01U ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Cipher Block Chaining (CBC) mode +#define MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR 0x02U ///< Set this option at #mcuxClEls_CipherOption_t.cphmde to use AES engine in Counter (CTR) mode +/** + * @} + */ + + +/** + * @ingroup mcuxClEls_Cipher_Macros + */ +#define MCUXCLELS_CIPHER_BLOCK_SIZE_AES ((size_t) 16U) ///< Size of an AES input block: 128 bit (16 bytes) + +/** + * @defgroup MCUXCLELS_CIPHER_KEY_SIZE_AES_ MCUXCLELS_CIPHER_KEY_SIZE_AES_ + * @brief Defines valid AES key sizes in bytes + * @ingroup mcuxClEls_Cipher_Macros + * @{ + */ + +#define MCUXCLELS_CIPHER_KEY_SIZE_AES_128 ((size_t) 16U) ///< Size of an AES128 key: 128 bit (16 bytes) +#define MCUXCLELS_CIPHER_KEY_SIZE_AES_192 ((size_t) 24U) ///< Size of an AES192 key: 192 bit (24 bytes) +#define MCUXCLELS_CIPHER_KEY_SIZE_AES_256 ((size_t) 32U) ///< Size of an AES192 key: 256 bit (32 bytes) +/** + * @} + * + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Cipher_Types mcuxClEls_Cipher_Types + * @brief Defines all types of @ref mcuxClEls_Cipher + * @ingroup mcuxClEls_Cipher + * @{ + */ + +/** + * @brief Command option bit field for #mcuxClEls_Cipher_Async + * + * Bit field to configure #mcuxClEls_Cipher_Async. See @ref MCUXCLELS_CIPHER_ for possible options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_CipherOption_t word-wise + struct + { + uint32_t :1; ///< RFU + uint32_t dcrpt :1; ///< Define operation mode + uint32_t cphmde :2; ///< Define cipher mode + uint32_t cphsoe :1; ///< Define whether the ELS internal cipher state should be extracted to external memory or kept internally +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + uint32_t cphsie :1; ///< Define whether an external provided cipher state should be imported from external memory + uint32_t :7; ///< RFU +#else + uint32_t :8; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + uint32_t extkey :1; ///< Define whether an external key from memory or ELS internal key should be used + uint32_t :18; ///< RFU + } bits; ///< Access #mcuxClEls_CipherOption_t bit-wise +} mcuxClEls_CipherOption_t; +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Cipher_Functions mcuxClEls_Cipher_Functions + * @brief Defines all functions of @ref mcuxClEls_Cipher + * @ingroup mcuxClEls_Cipher + * @{ + */ + + /** + * @brief Performs AES encryption/decryption. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Performs an AES encryption/decryption. Call #mcuxClEls_WaitForOperation to complete the operation. + * @param[in] options Encryption/decryption command options. For detailed information, see #mcuxClEls_CipherOption_t. + * @param[in] keyIdx Index of the key inside the ELS keystore. See parameter properties section in function description. + * @param[in] pKey Memory area that contains the key. See parameter properties section in function description. + * @param[in] keyLength Size of @p pKey in bytes. Must be a valid key size of @ref MCUXCLELS_CIPHER_KEY_SIZE_AES_. See parameter properties section in function description. + * @param[in] pInput Pointer to the input data to be encrypted/decrypted. Padding must be already applied. + * @param[in] inputLength Size of @p pInput in bytes, must be a multiple of the block size. + * @param[in, out] pIV A pointer to the memory location which contains/receives the IV/state of cipher. See parameter properties section in function description. + * @param[out] pOutput Pointer to the output buffer to store encrypted/decrypted data. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB
+ *
@p pIV is ignored. + * + *
@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC
+ *
@p pIV must be set to the IV (when encrypting the first block) or to the last block of the ciphertext of the previous operation. + * ELS will always read and write to this location. + * + * @ifnot ELS_NO_INTERNAL_STATE_FLAGS + * @p options.cphsie is ignored. + * @endif + * + * @p options.cphsoe is ignored.
+ * + *
@p options.cphmde == #MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR
+ *
@p pIV must be set to the IV (when encrypting the first block) or to the state output of the previous + * encryption/decryption operation. ELS will write to this location if @p options.cphsoe == #MCUXCLELS_CIPHER_STATE_OUT_ENABLE.
+ * + *
@p options.extkey == #MCUXCLELS_CIPHER_EXTERNAL_KEY
+ *
@p keyIdx is ignored.
+ * + *
@p options.extkey == #MCUXCLELS_CIPHER_INTERNAL_KEY
+ *
@p pKey is ignored. + * + * @p keyLength is ignored.
+ * + *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cipher_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cipher_Async( + mcuxClEls_CipherOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pIV, + uint8_t * pOutput + ); + +/** + * @} + */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_CIPHER_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h new file mode 100644 index 000000000..5b613fed1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Cmac.h @@ -0,0 +1,191 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Cmac.h + * @brief ELS header for CMAC support. + * This header exposes functions that enable using the ELS for the generation of cipher-based message authentication + * codes (CMAC). + * The supported cipher algorithm is AES-128 and AES-256. + */ + +/** + * @defgroup mcuxClEls_Cmac mcuxClEls_Cmac + * @brief This part of the @ref mcuxClEls driver supports functionality for cipher-based message authentication codes (CMAC). + * @ingroup mcuxClEls + * @{ + */ + +#ifndef MCUXCLELS_CMAC_H_ +#define MCUXCLELS_CMAC_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * MACROS + **********************************************/ +/** + * @defgroup mcuxClEls_Cmac_Macros mcuxClEls_Cmac_Macros + * @brief Defines all macros of @ref mcuxClEls_Cmac + * @ingroup mcuxClEls_Cmac + * @{ + */ + +/** + * @defgroup MCUXCLELS_CMAC_KEY_SIZE_ MCUXCLELS_CMAC_KEY_SIZE_ + * @brief Valid CMAC key sizes in bytes + * @ingroup mcuxClEls_Cmac_Macros + * @{ */ +#define MCUXCLELS_CMAC_KEY_SIZE_128 ((size_t) 16U) ///< Size of 128 bit CMAC key (16 bytes) +#define MCUXCLELS_CMAC_KEY_SIZE_256 ((size_t) 32U) ///< Size of 256 bit CMAC key (32 bytes) +/** @} */ + +/** + * @defgroup MCUXCLELS_CMAC_ MCUXCLELS_CMAC_ + * @brief Option values for #mcuxClEls_CmacOption_t + * @ingroup mcuxClEls_Cmac_Macros + * @{ */ +#define MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE 1U ///< Set #mcuxClEls_CmacOption_t.extkey to this value to use an external key +#define MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.extkey to this value to use a key from the ELS keystore +#define MCUXCLELS_CMAC_INITIALIZE_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.initialize to this value if the message chunk does not include the first block of the message +#define MCUXCLELS_CMAC_INITIALIZE_ENABLE 1U ///< Set #mcuxClEls_CmacOption_t.initialize to this value if the message chunk includes the first block of the message +#define MCUXCLELS_CMAC_FINALIZE_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.finalize to this value if the message chunk does not include the last block of the message +#define MCUXCLELS_CMAC_FINALIZE_ENABLE 1U ///< Set #mcuxClEls_CmacOption_t.finalize to this value if the message chunk includes the last block of the message +/** + * @} + */ + +#define MCUXCLELS_CMAC_OUT_SIZE ((size_t) 16U) ///< Size of CMAC output: 128 bit (16 bytes) + +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Cmac_Types mcuxClEls_Cmac_Types + * @brief Defines all types of @ref mcuxClEls_Cmac + * @ingroup mcuxClEls_Cmac + * @{ + */ +/** + * @brief Command option bit field for #mcuxClEls_Cmac_Async. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_CmacOption_t word-wise + struct + { + uint32_t initialize : 1; ///< Request initial processing for the first block of the message + uint32_t finalize : 1; ///< Request final processing for the last block of the message + uint32_t soe : 1; ///< This field is managed internally + uint32_t sie : 1; ///< This field is managed internally + uint32_t :9; ///< RFU + uint32_t extkey :1; ///< An external key should be used + uint32_t :18; ///< RFU + } bits; ///< Access #mcuxClEls_CmacOption_t bit-wise +} mcuxClEls_CmacOption_t; +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Cmac_Functions mcuxClEls_Cmac_Functions + * @brief Defines all functions of @ref mcuxClEls_Cmac + * @ingroup mcuxClEls_Cmac + * @{ + */ +/** + * @brief Performs CMAC with AES-128 or AES-256 + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The command options. For more information, see #mcuxClEls_CmacOption_t. + * @param[in] keyIdx The CMAC key index + * @param[in] pKey Pointer to the padded CMAC key + * @param[in] keyLength Size of @p pKey in bytes. Must be a @ref MCUXCLELS_CMAC_KEY_SIZE_ "valid CMAC key size". See the parameter properties section in the function description. + * @param[in] pInput Pointer to a memory location which contains the data, padded via SP 800-38b standard, to be authenticated + * @param[in] inputLength Size of @p pInput in bytes before padding + * @param[in, out] pMac Pointer to the CMAC command state input/output. See the parameter properties section in the function description. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE
+ *
@p keyIdx is ignored.
+ * + *
@p options.extkey == #MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE
+ *
@p pKey is ignored. + * + * @p keyLength is ignored.
+ * + *
(@p options.finalize == #MCUXCLELS_CMAC_FINALIZE_DISABLE)
+ *
The intermediate state is written to @p pMac.
+ * + *
@p options.finalize == #MCUXCLELS_CMAC_FINALIZE_ENABLE
+ *
The resulting MAC is written to @p pMac. + * + * @p options.soe is ignored.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if an invalid parameter was specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Cmac_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cmac_Async( + mcuxClEls_CmacOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pMac + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_CMAC_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h new file mode 100644 index 000000000..67fb15a80 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Common.h @@ -0,0 +1,876 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Common.h + * @brief ELS header for common functionality. + * + * This header exposes functions that support hardware state management for other ELS commands. + */ + +/** + * @defgroup mcuxClEls_Common mcuxClEls_Common + * @brief This part of the @ref mcuxClEls driver supports common functionality + * @ingroup mcuxClEls + * @{ + */ +#ifndef MCUXCLELS_COMMON_H_ +#define MCUXCLELS_COMMON_H_ + +#include // Exported features flags header +#include // Common types +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEls_Common_Macros mcuxClEls_Common_Macros + * @brief Defines all macros of @ref mcuxClEls_Common + * @ingroup mcuxClEls_Common + * @{ + */ + +#define MCUXCLELS_API ///< Marks a function as a public API function of the mcuxClEls component + +/********************************************** + * CONSTANTS + **********************************************/ + +/** + * @def MCUXCLELS_HW_VERSION + * @brief Compatible ELS hardware IP version for the CLNS release that this header is part of. + */ +#ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION +#define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \ + .bits = { \ + .revision = (uint32_t) ELS_HW_VERSION_REVISION, \ + .minor = (uint32_t) ELS_HW_VERSION_MINOR, \ + .major = (uint32_t) ELS_HW_VERSION_MAJOR, \ + .level = (uint32_t) ELS_HW_VERSION_LEVEL \ + } \ + }) +#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */ +#define MCUXCLELS_HW_VERSION ((mcuxClEls_HwVersion_t) { \ + .bits = { \ + .revision = (uint32_t) ELS_HW_VERSION_REVISION, \ + .minor = (uint32_t) ELS_HW_VERSION_MINOR, \ + .major = (uint32_t) ELS_HW_VERSION_MAJOR, \ + .fw_revision = (uint32_t) ELS_HW_VERSION_FW_REVISION, \ + .fw_minor = (uint32_t) ELS_HW_VERSION_FW_MINOR, \ + .fw_major = (uint32_t) ELS_HW_VERSION_FW_MAJOR \ + } \ + }) +#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */ + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_CompareDmaFinalOutputAddress) +#else + #define MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN (0u) +#endif + + +/** + * @defgroup mcuxClEls_InterruptOptionEn_t_Macros mcuxClEls_InterruptOptionEn_t + * @brief Defines interrupt enable option values + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_ELS_INTERRUPT_ENABLE (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.elsint to allow ELS to trigger an interrupt +#define MCUXCLELS_ELS_INTERRUPT_DISABLE (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.elsint to prevent ELS from triggering an interrupt +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +#define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE ((uint32_t) 1U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.gdetint to allow the Glitch Detector to trigger an interrupt +#define MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE ((uint32_t) 0U) ///< Set this option at #mcuxClEls_InterruptOptionEn_t.gdetint to prevent the Glitch Detector from triggering an interrupt +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ +/**@}*/ + +/** + * @defgroup mcuxClEls_InterruptOptionRst_t_Macros mcuxClEls_InterruptOptionRst_t + * @brief Defines interrupt reset option values + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_ELS_RESET_CLEAR (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.elsint to reset the ELS interrupt flag +#define MCUXCLELS_ELS_RESET_KEEP (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.elsint to keep the ELS interrupt flag +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +#define MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR ((uint32_t) 1U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.gdetint to reset the Glitch Detector interrupt flag +#define MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP ((uint32_t) 0U) ///< Set this option at #mcuxClEls_InterruptOptionRst_t.gdetint to keep the Glitch Detector interrupt flag +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ +/**@}*/ + +/** + * @defgroup mcuxClEls_InterruptOptionSet_t_Macros mcuxClEls_InterruptOptionSet_t + * @brief Defines interrupt set option values + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_ELS_INTERRUPT_SET (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.elsint to set the ELS interrupt flag +#define MCUXCLELS_ELS_INTERRUPT_KEEP (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.elsint to leave the ELS interrupt flag unchanged +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR +#define MCUXCLELS_GLITCH_DETECTOR_NEG_SET (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_neg to set the negative Glitch Detector interrupt flag +#define MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_neg to leave the negative Glitch Detector interrupt flag unchanged +#define MCUXCLELS_GLITCH_DETECTOR_POS_SET (0x01U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_pos to set the positive Glitch Detector interrupt flag +#define MCUXCLELS_GLITCH_DETECTOR_POS_KEEP (0x00U) ///< Set this option at #mcuxClEls_InterruptOptionSet_t.gdetint_pos to leave the positive Glitch Detector interrupt flag unchanged +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ +/**@}*/ + +/** + * @defgroup MCUXCLELS_ERROR_FLAGS_ MCUXCLELS_ERROR_FLAGS_ + * @brief Options for error flag clearing + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_ERROR_FLAGS_KEEP ((mcuxClEls_ErrorHandling_t) 0x0u) ///< Set this option at #mcuxClEls_ErrorHandling_t to not clear any error flags +#define MCUXCLELS_ERROR_FLAGS_CLEAR ((mcuxClEls_ErrorHandling_t) 0x1u) ///< Set this option at #mcuxClEls_ErrorHandling_t to clear all ELS error flags +/**@}*/ + +/** + * @defgroup MCUXCLELS_RESET_ MCUXCLELS_RESET_ + * @brief Options for reset handling + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_RESET_DO_NOT_CANCEL ((mcuxClEls_ResetOption_t) 0x0u) ///< Set this option at #mcuxClEls_ResetOption_t to abort the requested command if another ELS operation is still running +#define MCUXCLELS_RESET_CANCEL ((mcuxClEls_ResetOption_t) 0x1u) ///< Set this option at #mcuxClEls_ResetOption_t to execute the requested command even if another ELS operation is still running +/**@}*/ + +/** + * @defgroup MCUXCLELS_STATUS_PPROT_ MCUXCLELS_STATUS_PPROT_ + * @brief Values for the privilege/security level of ELS commands + * + * Note that some keys and memory areas may only be accessible when ELS is on a certain privilege/security level. + * + * The default value, before any command has been executed, is #MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE. + * + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged secure mode +#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged secure mode +#define MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in unprivileged non-secure mode +#define MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE ((uint32_t) 0x3u) ///< This value of #mcuxClEls_HwState_t.pprot means that the most recently started ELS operation was or is running in privileged non-secure mode +/**@}*/ + +/** + * @defgroup MCUXCLELS_STATUS_ECDSAVFY_ MCUXCLELS_STATUS_ECDSAVFY_ + * @brief ECDSA verify check values + * @ingroup mcuxClEls_Common_Macros + * @{ + */ +#define MCUXCLELS_STATUS_ECDSAVFY_NORUN ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that no ECDSA verify operation has been executed +#define MCUXCLELS_STATUS_ECDSAVFY_FAIL ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification failed +#define MCUXCLELS_STATUS_ECDSAVFY_OK ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that the most recently finished ECDSA signature verification passed +#define MCUXCLELS_STATUS_ECDSAVFY_ERROR ((uint32_t) 0x3u) ///< This value of #mcuxClEls_HwState_t.ecdsavfy means that an error has occurred +/**@}*/ + +/** + * @defgroup MCUXCLELS_STATUS_DRBGENTLVL_ MCUXCLELS_STATUS_DRBGENTLVL_ + * @brief Constants for Entropy quality of the current DRBG instance + * @ingroup mcuxClEls_Common_Macros + * @{ */ +#define MCUXCLELS_STATUS_DRBGENTLVL_NONE ((uint32_t) 0x0u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG is not running +#define MCUXCLELS_STATUS_DRBGENTLVL_LOW ((uint32_t) 0x1u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with a low security strength (sufficient for commands with a low DRBG security strength requirement, see the function description to check which level is required) +#define MCUXCLELS_STATUS_DRBGENTLVL_HIGH ((uint32_t) 0x2u) ///< This value of #mcuxClEls_HwState_t.drbgentlvl means that the DRBG can generate random numbers with 128 bits of security strength (sufficient for commands with a high DRBG security strength requirement, see the function description to check which level is required) +/** @} */ + +#ifdef MCUXCL_FEATURE_ELS_LOCKING +/** + * @defgroup MCUXCLELS_LOCKING_ MCUXCLELS_LOCKING_ + * @brief Constants for ELS locking feature + * @ingroup mcuxClEls_Common_Macros + * @{ */ +#define MCUXCLELS_MASTER_UNLOCK_ANY ((uint32_t) 0x1Fu) ///< Any bus master ID can override ELS lock +/** @} */ +#endif /* MCUXCL_FEATURE_ELS_LOCKING */ + + + +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ + +/** + * @defgroup mcuxClEls_Common_Types mcuxClEls_Common_Types + * @brief Defines all types of @ref mcuxClEls_Common + * @ingroup mcuxClEls_Common + * @{ + */ + +/** + * @brief Result type of #mcuxClEls_GetHwVersion + * + * Contains the ELS version value. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_HwVersion_t word-wise + struct + { + uint32_t revision :4; ///< Revision number + uint32_t minor :8; ///< Minor version + uint32_t major :4; ///< Major version +#ifndef MCUXCL_FEATURE_ELS_GET_FW_VERSION + uint32_t level :4; ///< Release level version + uint32_t :12; ///< RFU +#else /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */ + uint32_t fw_revision :4; ///< Firmware Revision number + uint32_t fw_minor :8; ///< Firmware Minor version + uint32_t fw_major :4; ///< Firmware Major version +#endif /* MCUXCL_FEATURE_ELS_GET_FW_VERSION */ + } bits; ///< Access #mcuxClEls_HwVersion_t bit-wise +} mcuxClEls_HwVersion_t; + +/** + * @brief Result type of #mcuxClEls_GetHwState + * + * Contains ELS status information. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_HwState_t word-wise + struct + { + uint32_t busy :1; ///< ELS is busy + uint32_t irq :1; ///< ELS interrupt activated + uint32_t err :1; ///< ELS is in error state + uint32_t prngready :1; ///< ELS PRNG is seeded and ready to use + uint32_t ecdsavfy :2; ///< ECDSA verify operation state (For possible values of this field, see @ref MCUXCLELS_STATUS_ECDSAVFY_) + uint32_t pprot :2; ///< The privilege/security level of the most recently started ELS command (For possible values of this field, see @ref MCUXCLELS_STATUS_PPROT_) + uint32_t drbgentlvl :2; ///< Entropy quality of the current DRBG instance (For possible values of this field, see @ref MCUXCLELS_STATUS_DRBGENTLVL_) + uint32_t dtrng_busy: 1; ///< Indicates the DTRNG is gathering entropy +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR + uint32_t gdet_pos :1; ///< Glitch detector interrupt activated (positive) + uint32_t gdet_neg :1; ///< Glitch detector interrupt activated (negative) +#else + uint32_t :2; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + uint32_t :3; ///< RFU +#ifdef MCUXCL_FEATURE_ELS_LOCKING + uint32_t els_locked :1; ///< ELS is locked +#else + uint32_t :1; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_LOCKING */ + uint32_t :15; ///< RFU + } bits; ///< Access #mcuxClEls_HwState_t bit-wise +} mcuxClEls_HwState_t; + +/** + * @brief Type to handle ELS error clearing options + * + * For possible values, see @ref MCUXCLELS_ERROR_FLAGS_. + */ +typedef uint32_t mcuxClEls_ErrorHandling_t; + +/** + * @brief Type to handle ELS reset options + * + * For possible values, see @ref MCUXCLELS_RESET_. + */ +typedef uint32_t mcuxClEls_ResetOption_t; + +/** + * @brief Command option type for #mcuxClEls_SetIntEnableFlags and #mcuxClEls_GetIntEnableFlags + * + * Used to get/set ELS interrupt enable options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_InterruptOptionEn_t word-wise + struct + { + uint32_t elsint :1; ///< Whether ELS interrupt should be used. (For possible values of this field, see @ref mcuxClEls_InterruptOptionEn_t_Macros) +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR + uint32_t gdetint :1; ///< Whether Glitch detector interrupt should be used. (For possible values of this field, see @ref mcuxClEls_InterruptOptionEn_t_Macros) +#else + uint32_t :1; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + uint32_t :30; ///< RFU + } bits; ///< Access #mcuxClEls_InterruptOptionEn_t bit-wise +} mcuxClEls_InterruptOptionEn_t; + +/** + * @brief Type to control which ELS interrupts should be reset when calling #mcuxClEls_ResetIntFlags + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_InterruptOptionRst_t word-wise + struct + { + uint32_t elsint :1; ///< Whether ELS interrupt should be reset. (For possible values of this field, see @ref mcuxClEls_InterruptOptionRst_t_Macros) +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR + uint32_t gdetint :1; ///< Whether Glitch detector interrupt should be reset. (For possible values of this field, see @ref mcuxClEls_InterruptOptionRst_t_Macros) +#else + uint32_t :1; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + uint32_t :30; ///< RFU + } bits; ///< Access #mcuxClEls_InterruptOptionRst_t bit-wise +} mcuxClEls_InterruptOptionRst_t; + +/** + * @brief Type to control which ELS interrupts should be set when calling #mcuxClEls_SetIntFlags + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_InterruptOptionSet_t word-wise + struct + { + uint32_t elsint :1; ///< Whether ELS interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros) +#ifdef MCUXCL_FEATURE_ELS_GLITCHDETECTOR + uint32_t gdetint_neg :1;///< Whether Glitch detector neg interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros) + uint32_t gdetint_pos :1;///< Whether Glitch detector pos interrupt should be set. (For possible values of this field, see @ref mcuxClEls_InterruptOptionSet_t_Macros) +#else + uint32_t :2; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_GLITCHDETECTOR */ + uint32_t :29; ///< RFU + } bits; ///< Access #mcuxClEls_InterruptOptionSet_t bit-wise +} mcuxClEls_InterruptOptionSet_t; + +/** + * @brief Result type of #mcuxClEls_GetHwConfig + * + * Contains ELS configuration values. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_InterruptOptionSet_t word-wise + struct + { + uint32_t ciphersup :1; ///< Indicates whether the cipher command is supported + uint32_t authciphersup :1; ///< Indicates whether the auth_cipher command is supported + uint32_t ecsignsup :1; ///< Indicates whether the ecsign command is supported + uint32_t ecvfysup :1; ///< Indicates whether the ecvfy command is supported + uint32_t eckxchsup :1; ///< Indicates whether the dhkey_xch command is supported + uint32_t keygensup :1; ///< Indicates whether the keygen command is supported + uint32_t keyinsup :1; ///< Indicates whether the keyin command is supported + uint32_t keyoutsup :1; ///< Indicates whether the keyout command is supported + uint32_t kdeletesup :1; ///< Indicates whether the kdelete command is supported + uint32_t keyprovsup :1; ///< Indicates whether the keyprov command is supported + uint32_t ckdfsup :1; ///< Indicates whether the ckdf command is supported + uint32_t hkdfsup :1; ///< Indicates whether the hkdf command is supported + uint32_t tlsinitsup :1; ///< Indicates whether the tls_init command is supported + uint32_t hashsup :1; ///< Indicates whether the hash command is supported + uint32_t hmacsup :1; ///< Indicates whether the hmac command is supported + uint32_t cmacsup :1; ///< Indicates whether the cmac command is supported + uint32_t drbgreqsup :1; ///< Indicates whether the drbg_req command is supported + uint32_t drbgtestsup :1; ///< Indicates whether the drbg_test command is supported + uint32_t dtrgncfgloadsup :1; ///< Indicates whether the dtrng_cfg_load command is is supported + uint32_t dtrngevalsup :1; ///< Indicates whether the dtrng_eval command is supported + uint32_t gdetcfgloadsup :1; ///< Indicates whether the gdet_cfg_load command is supported + uint32_t gdettrimsup :1; ///< Indicates whether the gdet_trim command is supported + uint32_t :10; ///< RFU + } bits; ///< Access #mcuxClEls_InterruptOptionSet_t bit-wise +} mcuxClEls_HwConfig_t; + +#define drbgreqsub drbgreqsup ///< Deprecated name for #mcuxClEls_HwConfig_t.drbgreqsup + + +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Common_Functions mcuxClEls_Common_Functions + * @brief Defines all functions of @ref mcuxClEls_Common + * @ingroup mcuxClEls_Common + * @{ + */ +/** + * @brief Determines the version of the underlying ELS hardware IP. + * + * @attention This header was delivered as part of a CLNS release which is compatible with a specific ELS hardware IP version, + * which is defined by the macro #MCUXCLELS_HW_VERSION. + * + * @param[out] result Pointer which will be filled with the ELS hardware version + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwVersion) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwVersion( + mcuxClEls_HwVersion_t * result + ); + +#ifdef MCUXCL_FEATURE_ELS_HWCONFIG +/** + * @brief Determines the hardware configuration of the underlying ELS hardware IP. + * + * @param[out] result Pointer which will be filled with the ELS hardware configuration + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwConfig) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwConfig( + mcuxClEls_HwConfig_t * result + ); +#endif /* MCUXCL_FEATURE_ELS_HWCONFIG */ + +/** + * @brief Determines the current state of the ELS. + * + * @param[out] result Pointer which will be filled with the ELS status information + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetHwState) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwState( + mcuxClEls_HwState_t * result + ); + +/** + * @brief Enables the ELS. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK_WAIT + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK_WAIT + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Enable_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Enable_Async( + void + ); + +/** + * @brief Perform a synchronous reset of the ELS. + * + * This means that: + * - any running ELS command will be stopped, + * - all errors will be cleared, + * - all keys will be deleted, + * - any RNG entropy will be discarded, + * - the glitch detector will be reset and + * - the run-time fingerprint will be restored to its default value. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options A value indicating whether any running ELS operations shall be canceled + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the reset + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Reset_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Reset_Async( + mcuxClEls_ResetOption_t options + ); + +/** + * @brief Disable the ELS. + * + * This is useful as a power saving mechanism. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Disable) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Disable( + void +); + +/** + * @brief Set interrupt enable flags. + * + * @param[in] options The command options, determining which interrupts should be enabled or disabled. For more information, see #mcuxClEls_InterruptOptionEn_t. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntEnableFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntEnableFlags( + mcuxClEls_InterruptOptionEn_t options + ); + +/** + * @brief Get interrupt enable flags. + * + * @param[out] result Pointer which is filled with the configuration of the interrupts enable register. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetIntEnableFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetIntEnableFlags( + mcuxClEls_InterruptOptionEn_t * result + ); + +/** + * @brief Clear the interrupt status register. + * + * @param[in] options The command options, determining which interrupt status bits should be cleared. For more information, see #mcuxClEls_InterruptOptionRst_t. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetIntFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetIntFlags( + mcuxClEls_InterruptOptionRst_t options + ); + +/** + * @brief Set the interrupt status register, for debug and testing purposes. + * + * @param[in] options The command options, determining which interrupt status bits should be set. For more information, see #mcuxClEls_InterruptOptionSet_t. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetIntFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntFlags( + mcuxClEls_InterruptOptionSet_t options + ); + +/** + * @brief Wait for an ELS operation and optionally clear the error status. + * + * If an ELS operation is active, this function waits for completion of that operation. For this, the + * busy flag of ELS is polled. Additionally, this function checks and returns any applicable error indication. + * If no operation is active, the function returns immediately. + * + * @param[in] errorHandling Define if error flags shall be cleared. + * + * @retval #MCUXCLELS_STATUS_OK if the last operation was successful, or no operation was active + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_WaitForOperation) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_WaitForOperation( + mcuxClEls_ErrorHandling_t errorHandling + ); + +/** + * @brief Await the completion of an ELS operation for a limited amount of time and optionally clear the error status. + * + * If an ELS operation is active, this function waits for completion of that operation until a counter expires. + * For this, the busy flag of ELS is polled. The counting mechanism behaves like a simple for-loop from + * @p counterLimit to one. This counter does not have a well-defined relationship to real-world time. + * Additionally, this function checks and returns any applicable error indication. + * If no operation is active, the function returns immediately. + * + * @param[in] counterLimit The limit of the wait counter. + * @param[in] errorHandling Define if error flags shall be cleared. + * + * @retval #MCUXCLELS_STATUS_OK if the last operation was successful, or no operation was active + * @retval #MCUXCLELS_STATUS_SW_COUNTER_EXPIRED if the counter expired while waiting for the operation to complete + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_LimitedWaitForOperation) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_LimitedWaitForOperation( + uint32_t counterLimit, + mcuxClEls_ErrorHandling_t errorHandling + ); + +/** + * @brief Resets all error flags that have been set by a previous operation. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ResetErrorFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetErrorFlags( + void); + +/** + * @brief Get the last ELS error code and optionally clear the error status. + * + * @param[in] errorHandling Define if error flags shall be cleared. + * + * @retval #MCUXCLELS_STATUS_OK if the last operation was successful or no operation was active + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorCode) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorCode( + mcuxClEls_ErrorHandling_t errorHandling + ); + +/** + * @brief Get the last ELS error code and level and optionally clear the error status. + * + * @param[in] errorHandling Define if error flags shall be cleared. + * @param[out] errorLevel Pointer to the location that will receive the value of the error level. + * + * @retval #MCUXCLELS_STATUS_OK if the last operation was successful or no operation was active + * @retval #MCUXCLELS_STATUS_ if the last operation resulted in an error + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetErrorLevel) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorLevel( + mcuxClEls_ErrorHandling_t errorHandling, + uint32_t *errorLevel + ); + +/** + * @brief Set the random start delay for AES based operations. This impacts mcuxClEls_Aead_*, mcuxClEls_Cipher_*, mcuxClEls_Cmac_*, ncpClEls_Ckdf_*, mcuxClEls_KeyImport_Async, mcuxClEls_KeyExport_Async + * + * @param[in] delay Define the max random start delay. Acceptable values are a power of 2 minus one, starting from 0 to 1023 (0, 1, 3, 7, ..., 1023). + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetRandomStartDelay) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetRandomStartDelay( + uint32_t delay + ); + +/** + * @brief Get the random start delay for AES based operations. + * + * @param[out] delay Pointer to store random start delay configuration. + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetRandomStartDelay) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetRandomStartDelay( + uint32_t * delay + ); + +#ifdef MCUXCL_FEATURE_ELS_LOCKING +/** + * @brief Lock ELS to a session + * + * This operation locks the ELS, when the lock is obtained a nonzero value will be stored in @p sessionId, and the PPROT and bus Master ID + * of the locking command will be recorded. Subsequent unlocking can only be done by one of the following: + * 1. ELS reset + * 2. Normal unlock: calling #mcuxClEls_ReleaseLock with the correct @p sessionId, from the same bus Master ID and using the same PPROT settings. + * 3. Privileged unlock: calling #mcuxClEls_ReleaseLock with any value of @p sessionId, from the bus Master ID set with the #mcuxClEls_SetMasterUnlock + * command and PPROT settings 'secure privileged'. + * While ELS is locked read access is only permitted to ELS_STATUS and ELS_SESSION_ID and writes are only permitted to ELS_RESET, except for accesses that + * have the same bus Master ID and PPROT settings. + * + * @param[out] pSessionId The session identifier assigned to the lock, it is required to unlock the session, it will be zero when a lock could not be obtained. + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful + * @retval #MCUXCLELS_STATUS_SW_LOCKING_FAILED if the operation was not successful + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLock( + uint32_t * pSessionId + ); + +/** + * @brief Release ELS lock for the session + * + * This operation unlocks the ELS when following conditions are met: + * 1. Normal unlock: providing the correct @p sessionId, from the same bus Master ID and using the same PPROT settings. + * 2. Privileged unlock: providing any value of @p sessionId, from the bus Master ID set with the #mcuxClEls_SetMasterUnlock command + * and PPROT settings 'secure privileged'. + * Invalid attempts to unlock ELS will result in a bus error. + * + * @param[in] sessionId The session identifier obtained while locking ELS + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ReleaseLock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ReleaseLock( + uint32_t sessionId + ); + +/** + * @brief Check if ELS is locked + * + * This operation returns the locking status of ELS. + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful and ELS is not locked + * @retval #MCUXCLELS_STATUS_SW_STATUS_LOCKED if the operation was successful and ELS is locked + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_IsLocked) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_IsLocked(void); + +/** + * @brief Set the bus master ID that can unlock ELS + * + * This operation sets the bus master ID of the master that can override ELS lock. This command can only be executed once after reset. + * Invalid attempts to set the bus master ID will result in a bus error. + * + * @param[in] masterId The bus master identifier that can override the ELS lock. Special value #MCUXCLELS_MASTER_UNLOCK_ANY allows any bus master identifier to override the ELS lock. + * + * @retval #MCUXCLELS_STATUS_OK if the operation was successful + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_SetMasterUnlock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetMasterUnlock( + uint32_t masterId + ); + +#endif /* MCUXCL_FEATURE_ELS_LOCKING */ + + +#ifdef MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK +/** + * @brief Reads back the last address processed by the ELS DMA (security feature) + * + * @param[out] pLastAddress Pointer to the last address read/written by the ELS DMA + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetLastDmaAddress) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLastDmaAddress( + uint32_t* pLastAddress + ); +#endif /* MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK */ + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +/** + * @brief Compares the last address processed by the ELS DMA with the expected final address of the output buffer given to the last ELS command (security feature). + * The given address @p outputStartAddress and expected length @p expectedLength determine the expected final address. + * This function can be used to verify that the final DMA transfer of an ELS command has completed as expected. + * + * @param[in] outputStartAddress Pointer to the output buffer of the last ELS operation + * @param[in] expectedLength Expected length of the output buffer of the last ELS operation + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLELS_STATUS_SW_COMPARISON_FAILED if the comparison between the expected final address and the actual final address processed by ELS fails + * @retval #MCUXCLELS_STATUS_OK_WAIT if the comparison was successful + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_CompareDmaFinalOutputAddress) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_CompareDmaFinalOutputAddress( + uint8_t *outputStartAddress, + size_t expectedLength + ); +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_COMMON_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h new file mode 100644 index 000000000..9aacd530e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Crc.h @@ -0,0 +1,637 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Crc.h + * @brief ELS header for Command CRC functionality. + * + * This header exposes functions that support the usage of the Command CRC feature for ELS. + */ +/** + * @defgroup mcuxClEls_Crc mcuxClEls_Crc + * @brief This part of the @ref mcuxClEls driver defines the Command CRC functionality + * @ingroup mcuxClEls + * @{ + */ +#ifndef MCUXCLELS_CRC_H_ +#define MCUXCLELS_CRC_H_ + +#include // Exported features flags header +#include // Common types +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_Crc_Macros mcuxClEls_Crc_Macros + * @brief Defines all macros of @ref mcuxClEls_Crc + * @ingroup mcuxClEls_Crc + * @{ + */ + +/** + * @defgroup MCUXCLELS_CMD_CRC_ MCUXCLELS_CMD_CRC_ + * @brief Constants for ELS Command CRC + * @ingroup mcuxClEls_Crc_Macros + * @{ */ +#define MCUXCLELS_CMD_CRC_VALUE_RESET ((uint32_t) 0x1u) ///< Reset the Command CRC to initial value +#define MCUXCLELS_CMD_CRC_VALUE_ENABLE ((uint32_t) 0x2u) ///< Enable update of Command CRC value by executing commands +#define MCUXCLELS_CMD_CRC_VALUE_DISABLE ((uint32_t) 0x0u) ///< Disable update of Command CRC value by executing commands + +#define MCUXCLELS_CMD_CRC_RESET ((uint32_t) 0x1u) ///< Reset the Command CRC to initial value +#define MCUXCLELS_CMD_CRC_ENABLE ((uint32_t) 0x1u) ///< Enable update of Command CRC value by executing commands +#define MCUXCLELS_CMD_CRC_DISABLE ((uint32_t) 0x0u) ///< Disable update of Command CRC value by executing commands + +#define MCUXCLELS_CMD_CRC_POLYNOMIAL ((uint32_t) 0x04C11DB7u) ///< CRC polynomial for the Command CRC +#define MCUXCLELS_CMD_CRC_INITIAL_VALUE ((uint32_t) 0xA5A5A5A5u) ///< Initial value for the Command CRC +/** @} */ + +/** + * @defgroup MCUXCLELS_CMD_CRC_REFERENCE_ MCUXCLELS_CMD_CRC_REFERENCE_ + * @brief Macros for reference ELS Command CRC + * @ingroup mcuxClEls_Crc_Macros + * @{ + */ + +/** + * @brief Initializes a reference CRC variable with the command CRC initial value. + * The new variable has the given name. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_INIT(crc) \ + uint32_t (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE + +/** + * @brief Resets the given reference CRC variable to the command CRC initial value. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_RESET(crc) \ + (crc) = MCUXCLELS_CMD_CRC_INITIAL_VALUE + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_Init_Async. + */ +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \ + (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE; \ + (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE; \ + (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \ + (options).bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE; \ + (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_PartialInit_Async. + */ +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \ + (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_UpdateAad_Async. + */ +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC \ + (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \ + (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_UpdateData_Async. + */ +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC \ + (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \ + (options).bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Aead_Finalize_Async. + */ +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL \ + (options).bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE(crc, options) \ + ({ \ + (options).bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Cipher_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER(crc, options) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CIPHER, (options).word.value, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Cmac_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC(crc, options) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CMAC, (options).word.value, &(crc)) + + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyGen_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN(crc, options) \ + ({ \ + (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN, (options).word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyExchange_Async. + */ +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc) \ + ({ \ + mcuxClEls_EccKeyExchOption_t options = {0u}; \ + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE(crc) \ + ({ \ + mcuxClEls_EccKeyExchOption_t options = {0u}; \ + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccKeyExchangeInt_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT(crc) \ + ({ \ + mcuxClEls_EccKeyExchOption_t options = {0u}; \ + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECKXH, options.word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccSign_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN(crc, options) \ + ({ \ + (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN, (options).word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccVerify_Async. + */ +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options) \ + ({ \ + (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \ + (retVal); \ + }) +#else +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY(crc, options) \ + ({ \ + (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_EccVerifyInt_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT(crc, options) \ + ({ \ + (options).bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; \ + (options).bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_ECVFY, (options).word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_GlitchDetector_LoadConfig_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD, 0u, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_GlitchDetector_Trim_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM, 0u, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Hash_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH(crc, options) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HASH, (options).word.value, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Hmac_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC(crc, options) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HMAC, (options).word.value, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Ckdf_Sp800108_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108(crc) \ + ({ \ + mcuxClEls_CkdfOption_t options = {0u}; \ + options.bits.ckdf_algo = MCUXCLELS_CKDF_ALGO_SP800108; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_CKDF, options.word.value, &(crc)); \ + (retVal); \ + }) + + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Hkdf_Rfc5869_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869(crc, options) \ + ({ \ + (options).bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_RFC5869; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, (options).word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Hkdf_Sp80056c_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C(crc) \ + ({ \ + mcuxClEls_HkdfOption_t options = {0u}; \ + options.bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_SP80056C; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_HKDF, options.word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY(crc) \ + ({ \ + mcuxClEls_TlsOption_t options = {0u}; \ + options.bits.mode = MCUXCLELS_TLS_INIT; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY(crc) \ + ({ \ + mcuxClEls_TlsOption_t options = {0u}; \ + options.bits.mode = MCUXCLELS_TLS_FINALIZE; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_TLS, options.word.value, &(crc)); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyDelete_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KDELETE, 0u, &(crc)) + + + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyImport_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, options) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, (options).word.value, &(crc)) + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyImportPuk_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK(crc) \ + ({ \ + mcuxClEls_KeyImportOption_t options = {0u}; \ + options.bits.revf = MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE; \ + options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_PBK; \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYIN, options.word.value, &(crc)); \ + (retVal); \ + }) +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_KeyExport_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT(crc) \ + ({ \ + mcuxClEls_Status_t retVal = mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT, 0u, &(crc)); \ + mcuxClEls_KeyImportOption_t import_options = {0u}; \ + import_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394; \ + retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE(crc); \ + retVal = MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT(crc, import_options); \ + (retVal); \ + }) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgRequest_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, 0u, &(crc)) + +#ifdef MCUXCL_FEATURE_ELS_RND_RAW +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgRequestRaw_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_RND_RAW, &(crc)) +#endif /* MCUXCL_FEATURE_ELS_RND_RAW */ + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestInstantiate_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestExtract_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestAesEcb_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_DrbgTestAesCtr_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_Dtrng_ConfigLoad_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD, 0u, &(crc)) + +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL, 0u, &(crc)) + +#ifdef MCUXCL_FEATURE_ELS_PRND_INIT +/** + * @brief Updates given reference command CRC with command @ref mcuxClEls_Prng_Init_Async. + */ +#define MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT(crc) \ + mcuxClEls_UpdateRefCRC(MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ, MCUXCLELS_RNG_RND_REQ_PRND_INIT, &(crc)) +#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */ +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_CMD_CRC_CMD_ID_ MCUXCLELS_CMD_CRC_CMD_ID_ + * @brief Constants for ELS Command IDs + * @ingroup mcuxClEls_Crc_Macros + * @{ + */ +#define MCUXCLELS_CMD_CRC_CMD_ID_CIPHER 0 ///< ELS Command ID for CIPHER command +#define MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER 1 ///< ELS Command ID for AUTH_CIPHER command +#define MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN 3 ///< ELS Command ID for CHAL_RESP_GEN command +#define MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN 4 ///< ELS Command ID for ECSIGN command +#define MCUXCLELS_CMD_CRC_CMD_ID_ECVFY 5 ///< ELS Command ID for ECVFY command +#define MCUXCLELS_CMD_CRC_CMD_ID_ECKXH 6 ///< ELS Command ID for ECKXH command +#define MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN 8 ///< ELS Command ID for KEYGEN command +#define MCUXCLELS_CMD_CRC_CMD_ID_KEYIN 9 ///< ELS Command ID for KEYIN command +#define MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT 10 ///< ELS Command ID for KEYOUT command +#define MCUXCLELS_CMD_CRC_CMD_ID_KDELETE 11 ///< ELS Command ID for KDELETE command +#define MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV 12 ///< ELS Command ID for KEYPROV command +#define MCUXCLELS_CMD_CRC_CMD_ID_CKDF 16 ///< ELS Command ID for CKDF command +#define MCUXCLELS_CMD_CRC_CMD_ID_HKDF 17 ///< ELS Command ID for HKDF command +#define MCUXCLELS_CMD_CRC_CMD_ID_TLS 18 ///< ELS Command ID for TLS command +#define MCUXCLELS_CMD_CRC_CMD_ID_HASH 20 ///< ELS Command ID for HASH command +#define MCUXCLELS_CMD_CRC_CMD_ID_HMAC 21 ///< ELS Command ID for HMAC command +#define MCUXCLELS_CMD_CRC_CMD_ID_CMAC 22 ///< ELS Command ID for CMAC command +#define MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ 24 ///< ELS Command ID for RND_REQ command +#define MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST 25 ///< ELS Command ID for DRBG_TEST command +#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD 28 ///< ELS Command ID for DTRNG_CFG_LOAD command +#define MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL 29 ///< ELS Command ID for DTRNG_EVAL command +#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD 30 ///< ELS Command ID for GDET_CFG_LOAD command +#define MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM 31 ///< ELS Command ID for GDET_TRIM command +/** + * @} + * + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Crc_Types mcuxClEls_Crc_Types + * @brief Defines all types of @ref mcuxClEls_Crc + * @ingroup mcuxClEls_Crc + * @{ + */ + +/** + * @brief Type to control ELS Command CRC + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; + struct + { + uint32_t reset :1; ///< Reset the Command CRC to initial value, set by #MCUXCLELS_CMD_CRC_RESET + uint32_t enable :1; ///< Enable/Disable update of Command CRC value by executing commands, set with #MCUXCLELS_CMD_CRC_ENABLE / #MCUXCLELS_CMD_CRC_DISABLE + uint32_t : 30; ///< RFU + } bits; ///< Access #mcuxClEls_CommandCrcConfig_t bit-wise +} mcuxClEls_CommandCrcConfig_t; + +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Crc_Functions mcuxClEls_Crc_Functions + * @brief Defines all functions of @ref mcuxClEls_Crc + * @ingroup mcuxClEls_Crc + * @{ + */ + +/** + * @brief Set command CRC flags. + * + * @param[in] options The command CRC options. For more information, see #mcuxClEls_CommandCrcConfig_t. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code is always #MCUXCLELS_STATUS_OK + * @else + * @return An error code that is always #MCUXCLELS_STATUS_OK + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_ConfigureCommandCRC) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ConfigureCommandCRC( + mcuxClEls_CommandCrcConfig_t options + ); + +/** + * @brief Get the current command CRC value. + * + * @param[out] commandCrc The command CRC value. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). + * @retval MCUXCLELS_STATUS_OK Operation successful + * @retval MCUXCLELS_STATUS_SW_INVALID_PARAM Parameter commandCRC points to NULL + * @else + * @return An error code + * @retval MCUXCLELS_STATUS_OK Operation successful + * @retval MCUXCLELS_STATUS_SW_INVALID_PARAM Parameter commandCRC points to NULL + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetCommandCRC) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetCommandCRC( + uint32_t* commandCrc + ); + +/** + * @brief Verifies a reference CRC against the computed ELS command CRC. + * + * @param[in] refCrc The reference CRC value. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_VerifyVsRefCRC) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_VerifyVsRefCRC( + uint32_t refCrc + ); + +/** + * @brief Updates a reference CRC with the parameters of an ELS command. + * This can be used to verify against the ELS command CRC. + * + * @param[in] command The ELS command ID. + * @param[in] options The command options for the given ELS command. + * @param[in,out] refCrc The current reference CRC value to update. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). + * @retval MCUXCLELS_STATUS_OK Operation successful + * @retval MCUXCLELS_STATUS_SW_INVALID_PARAM Parameter crc points to NULL + * @else + * @return An error code + * @retval MCUXCLELS_STATUS_OK Operation successful + * @retval MCUXCLELS_STATUS_SW_INVALID_PARAM Parameter crc points to NULL + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_UpdateRefCRC) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_UpdateRefCRC( + uint8_t command, + uint32_t options, + uint32_t* refCrc + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_CRC_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h new file mode 100644 index 000000000..c523207d8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Ecc.h @@ -0,0 +1,593 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Ecc.h + * @brief ELS header for elliptic curve cryptography + * This header exposes functions that enable using the ELS for elliptic curve cryptography. + * All functions operate on the NIST P-256 curve. + * The ECC operations supported are: + * - ECC key generation + * - ECC Diffie-Hellman key exchange + * - ECDSA signature generation/verification + */ + + +#ifndef MCUXCLELS_ECC_H_ +#define MCUXCLELS_ECC_H_ + +#include // Exported features flags header +#include // Common types & functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEls_Ecc mcuxClEls_Ecc + * @brief This part of the @ref mcuxClEls driver supports functionality for elliptic curve cryptography + * @ingroup mcuxClEls + * @{ + */ + + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_Ecc_Macros mcuxClEls_Ecc_Macros + * @brief Defines all macros of @ref mcuxClEls_Ecc + * @ingroup mcuxClEls_Ecc + * @{ + */ + +/** + * @defgroup MCUXCLELS_ECC_VALUE_ MCUXCLELS_ECC (Sign and Verify) option word values + * @brief Constants for #mcuxClEls_EccSignOption_t and #mcuxClEls_EccVerifyOption_t + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_ECC_VALUE_HASHED ((uint32_t) 0u<< 0u) ///< Set this option at #mcuxClEls_EccSignOption_t.value or #mcuxClEls_EccVerifyOption_t.value to specify input is the hash of the message +#define MCUXCLELS_ECC_VALUE_NOT_HASHED ((uint32_t) 1u<< 0u) ///< Set this option at #mcuxClEls_EccSignOption_t.value or #mcuxClEls_EccVerifyOption_t.value to specify input is the plain message +#define MCUXCLELS_ECC_VALUE_RTF ((uint32_t) 1u<< 1u) ///< Set this option at #mcuxClEls_EccSignOption_t.value to include the RTF in the signature, only for #mcuxClEls_EccSignOption_t +#define MCUXCLELS_ECC_VALUE_NO_RTF ((uint32_t) 0u<< 1u) ///< Set this option at #mcuxClEls_EccSignOption_t.value to not include the RTF in the signature, only for #mcuxClEls_EccSignOption_t +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_KEYGEN_VALUE_ MCUXCLELS_KEYGEN option word values + * @brief Constants for #mcuxClEls_EccKeyGenOption_t + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY ((uint32_t) 1u<< 0u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to sign the public key +#define MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN ((uint32_t) 0u<< 1u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key will be a signing key usable by #mcuxClEls_EccSign_Async +#define MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE ((uint32_t) 1u<< 1u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key will be a Diffie Helman key usable by #mcuxClEls_EccKeyExchange_Async +#define MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC ((uint32_t) 0u<< 2u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key is deterministic +#define MCUXCLELS_KEYGEN_VALUE_RANDOM ((uint32_t) 1u<< 2u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to specify output key is random +#define MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY ((uint32_t) 0u<< 3u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to generate a public key +#define MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY ((uint32_t) 1u<< 3u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to not generate a public key +#define MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA ((uint32_t) 0u<< 5u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to not use random data for signing the public key +#define MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA ((uint32_t) 1u<< 5u) ///< Set this option at #mcuxClEls_EccKeyGenOption_t.value to use random data for signing the public key +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_ECC_VALUE_BITS MCUXCLELS_ECC (Sign and Verify) option bit field values + * @brief Bit field constants for #mcuxClEls_EccSignOption_t and #mcuxClEls_EccVerifyOption_t + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_ECC_HASHED ((uint32_t) 0U) ///< Set this option at #mcuxClEls_EccSignOption_t.echashchl or #mcuxClEls_EccVerifyOption_t.echashchl to specify input is the hash of the message +#define MCUXCLELS_ECC_NOT_HASHED ((uint32_t) 1U) ///< Set this option at #mcuxClEls_EccSignOption_t.echashchl or #mcuxClEls_EccVerifyOption_t.echashchl to specify input is the plain message + +#define MCUXCLELS_ECC_RTF ((uint32_t) 1U) ///< Set this option at #mcuxClEls_EccSignOption_t.signrtf to include the RTF in the signature +#define MCUXCLELS_ECC_NO_RTF ((uint32_t) 0U) ///< Set this option at #mcuxClEls_EccSignOption_t.signrtf to not include the RTF in the signature +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_KEYGEN_VALUE_BITS MCUXCLELS_KEYGEN option bit field values + * @brief Bit field constants for #mcuxClEls_EccKeyGenOption_t + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE 1U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign to sign the public key (signature will be concatenated to the output public key) +#define MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE 0U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign to not sign the public key + +#define MCUXCLELS_ECC_OUTPUTKEY_SIGN 0U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a signing key usable by #mcuxClEls_EccSign_Async +#define MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE 1U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgtypedh to specify output key will be a Diffie Helman key usable by #mcuxClEls_EccKeyExchange_Async + +#define MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC 0U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is deterministic +#define MCUXCLELS_ECC_OUTPUTKEY_RANDOM 1U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsrc to specify output key is random + +#define MCUXCLELS_ECC_GEN_PUBLIC_KEY 0U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.skip_pbk to generate a public key +#define MCUXCLELS_ECC_SKIP_PUBLIC_KEY 1U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.skip_pbk to not generate a public key. + ///< If #MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE set, this option will be ignored and a public key will be generated. + +#define MCUXCLELS_ECC_NO_RANDOM_DATA 0U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign_rnd to not include user provided random data for the signature +#define MCUXCLELS_ECC_INCLUDE_RANDOM_DATA 1U ///< Set this option at #mcuxClEls_EccKeyGenOption_t.kgsign_rnd to include user provided random data for the signature. + ///< #MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE must be set in this case. +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_INTERNAL_VALUE_BITS Option bit field values that are needed for internal use only + * @brief Internal bit field constants for several option types. + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_ECC_REVERSEFETCH_ENABLE (0x01U) ///< Reverse Fetch enabled. For internal use +#define MCUXCLELS_ECC_REVERSEFETCH_DISABLE (0x00U) ///< Reverse Fetch disabled. For internal use + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT +#define MCUXCLELS_ECC_EXTKEY_EXTERNAL (0x01U) ///< Public key is taken from system memory. For internal use +#define MCUXCLELS_ECC_EXTKEY_INTERNAL (0x00U) ///< Public key is taken from internal keystore. For internal use +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_ECC_SIZE MCUXCLELS_ECC_SIZE + * @brief Defines size of public key and signature in bytes + * @ingroup mcuxClEls_Ecc_Macros + * @{ + */ +#define MCUXCLELS_ECC_PUBLICKEY_SIZE ((size_t) 64U) ///< Size of the public key +#define MCUXCLELS_ECC_SIGNATURE_SIZE ((size_t) 64U) ///< Size of the signature +#define MCUXCLELS_ECC_SIGNATURE_R_SIZE ((size_t) 32U) ///< Size of the signature part r +/** + * @} + */ + +/** + * @} + */ /* mcuxClEls_Ecc_Macros */ + + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Ecc_Types mcuxClEls_Ecc_Types + * @brief Defines all types of @ref mcuxClEls_Ecc + * @ingroup mcuxClEls_Ecc + * @{ + */ + +/** + * @brief Data type for ECC parameters in ELS format + * @deprecated All ELS ECC functions now operate on uint8_t. This type will be removed soon. + */ +typedef uint8_t mcuxClEls_EccByte_t; + +/** + * @brief Command option bit field for #mcuxClEls_EccSign_Async + * Bit field to configure #mcuxClEls_EccSign_Async. See @ref MCUXCLELS_ECC_VALUE_BITS for possible options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Access the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_ECC_VALUE_ + } word; ///< Access #mcuxClEls_EccSignOption_t word-wise + struct + { + uint32_t echashchl :1; ///< Define type of input, plain message or hash of message + uint32_t signrtf :1; ///< Define if signing the Run-Time Fingerprint + uint32_t :2; ///< RFU + uint32_t revf :1; ///< This field is managed internally + uint32_t :27; ///< RFU + } bits; ///< Access #mcuxClEls_EccSignOption_t bit-wise +} mcuxClEls_EccSignOption_t; + +/** + * @brief Command option bit field for #mcuxClEls_EccVerify_Async + * Bit field to configure #mcuxClEls_EccVerifyOption_t. See @ref MCUXCLELS_ECC_VALUE_BITS for possible options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Access the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_ECC_VALUE_ + } word; ///< Access #mcuxClEls_EccVerifyOption_t word-wise + struct + { + uint32_t echashchl :1; ///< Define type of input, plain message or hash of message + uint32_t :3; ///< RFU + uint32_t revf :1; ///< This field is managed internally +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT + uint32_t :8; ///< RFU + uint32_t extkey :1; ///< This field is managed internally + uint32_t :18; ///< RFU +#else + uint32_t :27; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ + } bits; ///< Access #mcuxClEls_EccVerifyOption_t bit-wise +} mcuxClEls_EccVerifyOption_t; + +/** + * @brief Command option bit field for #mcuxClEls_EccKeyGen_Async + * Bit field to configure #mcuxClEls_EccKeyGenOption_t. See @ref MCUXCLELS_KEYGEN_VALUE_BITS for possible options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYGEN_VALUE_ + } word; ///< Access #mcuxClEls_EccKeyGenOption_t word-wise + struct + { + uint32_t kgsign :1; ///< Define if signing the output public key + uint32_t kgtypedh :1; ///< Define the usage of the output key + uint32_t kgsrc :1; ///< Define if the output key is deterministic or random + uint32_t skip_pbk :1; ///< Define if generating a public key + uint32_t revf :1; ///< This field is managed internally + uint32_t kgsign_rnd :1; ///< Define if using user provided random data for the signature. + uint32_t :26; ///< RFU + } bits; ///< Access #mcuxClEls_EccKeyGenOption_t bit-wise +} mcuxClEls_EccKeyGenOption_t; + +/** + * @brief Command option bit field for #mcuxClEls_EccKeyExchange_Async, for internal use only. + * Bit field to configure #mcuxClEls_EccKeyExchOption_t. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_EccKeyExchOption_t word-wise + struct + { + uint32_t :4; ///< RFU + uint32_t revf :1; ///< This field is managed internally + uint32_t :8; ///< RFU + uint32_t extkey :1; ///< This field is managed internally + uint32_t :18; ///< RFU + } bits; ///< Access #mcuxClEls_EccKeyExchOption_t bit-wise +} mcuxClEls_EccKeyExchOption_t; + +/** + * @} + */ /* mcuxClEls_Ecc_Types */ + + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Ecc_Functions mcuxClEls_Ecc_Functions + * @brief Defines all functions of @ref mcuxClEls_Ecc + * @ingroup mcuxClEls_Ecc + * @{ + */ + +/** + * @brief Generates an ECC key pair on the NIST P-256 curve. + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * The public key will be stored in the standard ANSI X9.62 byte order (big-endian). + * + * @param[in] options The command options. For more information, see #mcuxClEls_EccKeyGenOption_t. + * @param[in] signingKeyIdx The index of the key to sign the generated public key. + * @param[in] privateKeyIdx Output key index. + * @param[in] generatedKeyProperties The desired key properties of the generated key. + * @param[in] pRandomData Random data provided by the user. + * @param[out] pPublicKey Pointer to the memory area which receives the public key and optionally the key signature. + * + *
+ *
Parameter properties
+ *
+ *
@p options.kgsign == #MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE
+ *
@p signingKeyIdx is ignored.
+ *
@p options.kgsrc == #MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC
+ *
@p privateKeyIdx also defines the key index of the source key material. + * The source key material will be overwritten by the output public key.
+ *
@p options.kgsign_rnd == #MCUXCLELS_ECC_NO_RANDOM_DATA
+ *
@p pRandomData is ignored.
+ *
@p pPublicKey must be aligned on a 4-byte boundary.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyGen_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyGen_Async( + mcuxClEls_EccKeyGenOption_t options, + mcuxClEls_KeyIndex_t signingKeyIdx, + mcuxClEls_KeyIndex_t privateKeyIdx, + mcuxClEls_KeyProp_t generatedKeyProperties, + uint8_t const * pRandomData, + uint8_t * pPublicKey + ); + +/** + * @brief Performs a Diffie-Hellman key exchange with an internal ECC private key and an external ECC public key. + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * The public key must be stored in the standard ANSI X9.62 byte order (big-endian). + * + * @param[in] privateKeyIdx The private key index. + * @param[in] pPublicKey Pointer to the public key of a third party. + * @param[in] sharedSecretIdx The index in the ELS keystore that receives the shared secret that is generated by the ECDH operation. + * @param[in] sharedSecretProperties The desired key properties of the shared secret. + * + *
+ *
Parameter properties
+ *
+ *
@p pPublicKey
+ *
The public key consists of the 256-bit X coordinate and the 256-bit Y coordinate. + * The point must lie on the NIST P-256 curve, be encoded in X9.62 format and aligned on a 4-byte boundary.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchange_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchange_Async( + mcuxClEls_KeyIndex_t privateKeyIdx, + uint8_t const * pPublicKey, + mcuxClEls_KeyIndex_t sharedSecretIdx, + mcuxClEls_KeyProp_t sharedSecretProperties + ); + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** + * @brief Performs a Diffie-Hellman key exchange with an internal ECC private key and an internal ECC public key. + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] privateKeyIdx The private key index. + * @param[in] publicKeyIdx The public key index. + * @param[in] sharedSecretIdx The index in the ELS keystore that receives the shared secret that is generated by the ECDH operation. + * @param[in] sharedSecretProperties The desired key properties of the shared secret. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccKeyExchangeInt_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchangeInt_Async( + mcuxClEls_KeyIndex_t privateKeyIdx, + mcuxClEls_KeyIndex_t publicKeyIdx, + mcuxClEls_KeyIndex_t sharedSecretIdx, + mcuxClEls_KeyProp_t sharedSecretProperties + ); +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @brief Generates an ECDSA signature of a given message. + * + * The curve is NIST P-256. + * The message hash, must be stored in the standard ANSI X9.62 format. + * If the message is provided in plain, no prior conversion is necessary. + * The signature will be stored in the standard ANSI X9.62 byte order (big-endian). + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The command options. For more information, see #mcuxClEls_EccSignOption_t. + * @param[in] keyIdx The private key index. + * @param[in] pInputHash The hash of the message to sign in X9.62 format. + * @param[in] pInputMessage The message to sign. + * @param[in] inputMessageLength Size of @p pInputMessage in bytes. + * @param[out] pOutput Pointer to the memory area which receives the generated signature in X9.62 format. (64 bytes) + * + *
+ *
Parameter properties
+ *
+ *
@p options.echashchl == #MCUXCLELS_ECC_HASHED
+ *
@p pInputHash is used, and it must be aligned on a 4-byte boundary. + * @p pInputMessage is ignored.
+ *
@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED
+ *
@p pInputHash is ignored. + * @p pInputMessage and @p inputMessageLength are used.
+ *
@p pOptput must be aligned on a 4-byte boundary.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccSign_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccSign_Async( + mcuxClEls_EccSignOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t * pOutput + ); + +/** + * @brief Verifies an ECDSA signature of a given message. + * + * The curve is NIST P-256. + * The message hash, must be stored in the standard ANSI X9.62 format. + * If the message is provided in plain, no prior conversion is necessary. + * The signature and public key must be stored in the standard ANSI X9.62 byte order (big-endian). + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The command options. For more information, see #mcuxClEls_EccVerifyOption_t. + * @param[in] pInputHash The hash of the signed message in X9.62 format. + * @param[in] pInputMessage The message to sign. + * @param[in] inputMessageLength Size of @p pInputMessage in bytes. + * @param[in] pSignatureAndPubKey Pointer to the memory area which contains the concatenation of the signature and the public key. + * @param[out] pOutput Pointer to the memory area which will receive the recalculated value of the R component in case of a successful + * signature verification. + * + *
+ *
Parameter properties
+ *
+ *
@p options.echashchl == #MCUXCLELS_ECC_HASHED
+ *
@p pInputHash is used, and it must be aligned on a 4-byte boundary. + * @p pInputMessage is ignored.
+ *
@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED
+ *
@p pInputHash is ignored. + * @p pInputMessage and @p inputMessageLength are used.
+ *
@p pSignatureAndPubKey
+ *
It must be aligned on a 4-byte boundary. + * The signature to be verified consists of the 256-bit R component and the 256-bit S component. + * The public key is the one for verification. (Uncompressed, X and Y components) + * The signature and the public key are in X9.62 format.
+ *
@p pOutput
+ *
It must be aligned on a 4-byte boundary. + * The output shall be compared to the first 32 bytes stored at @p pSignatureAndPublicKey.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerify_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerify_Async( + mcuxClEls_EccVerifyOption_t options, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t const * pSignatureAndPubKey, + uint8_t * pOutput + ); + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** + * @brief Verifies an ECDSA signature of a given message. + * + * The curve is NIST P-256. + * The message hash, must be stored in the standard ANSI X9.62 format. + * If the message is provided in plain, no prior conversion is necessary. + * The signature must be stored in the standard ANSI X9.62 byte order (big-endian). + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * No matter the value of @p options.echashchl, it must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The command options. For more information, see #mcuxClEls_EccVerifyOption_t. + * @param[in] publicKeyIdx The public key index. + * @param[in] pInputHash The hash of the signed message in X9.62 format. + * @param[in] pInputMessage The message to sign. + * @param[in] inputMessageLength Size of @p pInputMessage in bytes. + * @param[in] pSignature Pointer to the memory area which contains the concatenation of the signature and the public key. + * @param[out] pOutput Pointer to the memory area which will receive the recalculated value of the R component in case of a successful + * signature verification. + * + *
+ *
Parameter properties
+ *
+ *
@p options.echashchl == #MCUXCLELS_ECC_HASHED
+ *
@p pInputHash is used, and it must be aligned on a 4-byte boundary. + * @p pInputMessage is ignored.
+ *
@p options.echashchl == #MCUXCLELS_ECC_NOT_HASHED
+ *
@p pInputHash is ignored. + * @p pInputMessage and @p inputMessageLength are used.
+ *
@p pSignature
+ *
It must be aligned on a 4-byte boundary. + * The signature to be verified consists of the 256-bit R component and the 256-bit S component. + * The signature is in X9.62 format.
+ *
@p pOutput
+ *
It must be aligned on a 4-byte boundary. + * The output shall be compared to the first 32 bytes stored at @p pSignatureAndPublicKey.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_EccVerifyInt_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerifyInt_Async( + mcuxClEls_EccVerifyOption_t options, + mcuxClEls_KeyIndex_t publicKeyIdx, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t const * pSignature, + uint8_t * pOutput + ); + +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @} + */ /* mcuxClEls_Ecc_Functions */ + +/** + * @} + */ /* mcuxClEls_Ecc */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_ECC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h new file mode 100644 index 000000000..6a3858c05 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_GlitchDetector.h @@ -0,0 +1,157 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_GlitchDetector.h + * @brief ELS header for controlling the glitch detector. + * + * This header exposes functions that configure the ELS glitch detector. + */ + +#ifndef MCUXCLELS_GLITCHDETECTOR_H_ +#define MCUXCLELS_GLITCHDETECTOR_H_ + +#include // Exported features flags header +#include // Common types & functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEls_GlitchDetector mcuxClEls_GlitchDetector + * @brief This part of the @ref mcuxClEls driver supports glitch detector functionality + * @ingroup mcuxClEls + * @{ + */ + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_GlitchDetector_Macros mcuxClEls_GlitchDetector_Macros + * @brief Defines all macros of @ref mcuxClEls_GlitchDetector + * @ingroup mcuxClEls_GlitchDetector + * @{ + */ + +#define MCUXCLELS_GLITCHDETECTOR_CFG_SIZE ((size_t) 0x18u) ///< Glitch detector configuration size + +#define MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE ((size_t) 0x04u) ///< Glitch detector trim value size + +/** + * @} + */ /* mcuxClEls_GlitchDetector_Macros */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_GlitchDetector_Functions mcuxClEls_GlitchDetector_Functions + * @brief Defines all functions of @ref mcuxClEls_GlitchDetector + * @ingroup mcuxClEls_GlitchDetector + * @{ + */ + +/** + * @brief Loads a glitch detector configuration. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] Pointer to the memory area which contains the glitch detector configuration. The size is fixed at #MCUXCLELS_GLITCHDETECTOR_CFG_SIZE bytes. + * + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_LoadConfig_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_LoadConfig_Async( + uint8_t const * pInput + ); + +/** + * @brief Calculates optimal ELS glitch detector configuration and writes it to system memory. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[out] Pointer to the memory area which receives the glitch detector trim value. The size is fixed at #MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE bytes. + * + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_Trim_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_Trim_Async( + uint8_t * pOutput + ); + +/** + * @brief Reads the glitch detector's event counter + * + * This function converts the event counter from Gray code to an unsigned number. + * + * @param[in] Pointer to the word where the counter value will be stored. + * + * @retval #MCUXCLELS_STATUS_OK on successful request + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_GetEventCounter) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_GetEventCounter( + uint8_t * pCount + ); + +/** + * @brief Resets the glitch detector's event counter + * + * @retval #MCUXCLELS_STATUS_OK on successful request + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GlitchDetector_ResetEventCounter) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_ResetEventCounter( void + ); + +/** + * @} + */ /* mcuxClEls_GlitchDetector_Functions */ + +/** + * @} + */ /* mcuxClEls_GlitchDetector */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_GLITCHDETECTOR_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h new file mode 100644 index 000000000..db6f7a24d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hash.h @@ -0,0 +1,256 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hash.h + * @brief ELS header for hashing. + * + * This header exposes functions that enable using the ELS for hashing. + * There are two modes to hash a message: The asynchronous way as an ELS command, and the SHA-Direct mode which feeds + * data to the internal registers of the ELS and is synchronous (blocking). + * The SHA-Direct mode is meant to be used when another command should be executed in parallel on the ELS while the + * hash operation is still ongoing. For this, use the DMA callback option in #mcuxClEls_Hash_ShaDirect. + */ + +/** + * @defgroup mcuxClEls_Hash mcuxClEls_Hash + * @brief This part of the @ref mcuxClEls driver supports hashing + * @ingroup mcuxClEls + * @{ + */ + +#ifndef MCUXCLELS_HASH_H_ +#define MCUXCLELS_HASH_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ + +/** + * @defgroup mcuxClEls_Hash_Macros mcuxClEls_Hash_Macros + * @brief Defines all macros of @ref mcuxClEls_Hash + * @ingroup mcuxClEls_Hash + * @{ + */ + +/** + * @defgroup MCUXCLELS_HASH_ MCUXCLELS_HASH_ + * @brief Defines valid options to be used by #mcuxClEls_HashOption_t + * @ingroup mcuxClEls_Hash_Macros + * @{ + */ + +#define MCUXCLELS_HASH_INIT_ENABLE 1U ///< Set this option at #mcuxClEls_HashOption_t.hashini to initialize the hash +#define MCUXCLELS_HASH_INIT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashini to continue the hash + +#define MCUXCLELS_HASH_LOAD_ENABLE 1U ///< Set this option at #mcuxClEls_HashOption_t.hashld to load the hash state from @p pDigest +#define MCUXCLELS_HASH_LOAD_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashld to not load the hash state + +#define MCUXCLELS_HASH_OUTPUT_ENABLE 1U ///< Set this option at #mcuxClEls_HashOption_t.hashoe to output the hash to @p pDigest +#define MCUXCLELS_HASH_OUTPUT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.hashoe to not output the hash + +#define MCUXCLELS_HASH_RTF_UPDATE_ENABLE 1U ///< Set this option at #mcuxClEls_HashOption_t.rtfupd to update the run-time fingerprint (only supported by #mcuxClEls_Hash_Async) +#define MCUXCLELS_HASH_RTF_UPDATE_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.rtfupd to not update the run-time fingerprint + +#define MCUXCLELS_HASH_RTF_OUTPUT_ENABLE 1U ///< Set this option at #mcuxClEls_HashOption_t.rtfoe to output the run-time fingerprint (only supported by #mcuxClEls_Hash_Async) +#define MCUXCLELS_HASH_RTF_OUTPUT_DISABLE 0U ///< Set this option at #mcuxClEls_HashOption_t.rtfoe to not output the run-time fingerprint + +#define MCUXCLELS_HASH_MODE_SHA_224 1U ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-224 +#define MCUXCLELS_HASH_MODE_SHA_256 0U ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-256 +#define MCUXCLELS_HASH_MODE_SHA_384 2U ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-384 +#define MCUXCLELS_HASH_MODE_SHA_512 3U ///< Set this option at #mcuxClEls_HashOption_t.hashmd to use the hash algorithm SHA-512 + + +#define MCUXCLELS_HASH_VALUE_MODE_SHA_224 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_224 << 4) ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-224 +#define MCUXCLELS_HASH_VALUE_MODE_SHA_256 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_256 << 4) ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-256 +#define MCUXCLELS_HASH_VALUE_MODE_SHA_384 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_384 << 4) ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-384 +#define MCUXCLELS_HASH_VALUE_MODE_SHA_512 ((uint32_t) MCUXCLELS_HASH_MODE_SHA_512 << 4) ///< Set this option at #mcuxClEls_HashOption_t.word.value to use the hash algorithm SHA-512 + + +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_HASH_BLOCK_SIZE_ MCUXCLELS_HASH_BLOCK_SIZE_ + * @brief Defines block sizes used by the supported hash algorithms + * @ingroup mcuxClEls_Hash_Macros + * @{ + */ +#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_224 64U ///< SHA-224 output size: 512 bit (64 bytes) +#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_256 64U ///< SHA-256 output size: 512 bit (64 bytes) +#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_384 128U ///< SHA-384 output size: 1024 bit (128 bytes) +#define MCUXCLELS_HASH_BLOCK_SIZE_SHA_512 128U ///< SHA-512 output size: 1024 bit (128 bytes) +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_HASH_STATE_SIZE_ MCUXCLELS_HASH_STATE_SIZE_ + * @brief Defines the intermediate state sizes of the supported hash algorithms + * @ingroup mcuxClEls_Hash_Macros + * @{ + */ +#define MCUXCLELS_HASH_STATE_SIZE_SHA_224 32U ///< SHA-224 state size: 256 bit (32 bytes) +#define MCUXCLELS_HASH_STATE_SIZE_SHA_256 32U ///< SHA-256 state size: 256 bit (32 bytes) +#define MCUXCLELS_HASH_STATE_SIZE_SHA_384 64U ///< SHA-384 state size: 512 bit (64 bytes) +#define MCUXCLELS_HASH_STATE_SIZE_SHA_512 64U ///< SHA-512 state size: 512 bit (64 bytes) +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_HASH_OUTPUT_SIZE_ MCUXCLELS_HASH_OUTPUT_SIZE_ + * @brief Defines the output sizes of the supported hash algorithms (do not use for allocation) + * @ingroup mcuxClEls_Hash_Macros + * @{ + */ +#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224 28U ///< SHA-224 output size: 224 bit (28 bytes) +#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 32U ///< SHA-256 output size: 256 bit (32 bytes) +#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384 48U ///< SHA-384 output size: 384 bit (48 bytes) +#define MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 64U ///< SHA-512 output size: 512 bit (64 bytes) +/** + * @} + */ + +/** + * @ingroup mcuxClEls_Hash_Macros + * @{ + */ +#define MCUXCLELS_HASH_RTF_OUTPUT_SIZE ((size_t)32U) ///< Size of run-time fingerprint appended to the hash in @p pDigest in bytes, if #MCUXCLELS_HASH_RTF_OUTPUT_ENABLE was specified +/** + * @} + * + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ + +/** + * @defgroup mcuxClEls_Hash_Types mcuxClEls_Hash_Types + * @brief Defines all types of @ref mcuxClEls_Hash + * @ingroup mcuxClEls_Hash + * @{ + */ + +/** + * @brief Command option bit field for #mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. + * + * Bit field to configure #mcuxClEls_Hash_Async and #mcuxClEls_Hash_ShaDirect. See @ref MCUXCLELS_HASH_ for possible options. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_HashOption_t word-wise + struct + { + uint32_t :2; ///< RFU + uint32_t hashini :1; ///< Defines if the hash engine shall be initialized + uint32_t hashld :1; ///< Defines if the hash engine shall be initialized with an externally provided digest + uint32_t hashmd :2; ///< Defines which hash algorithm shall be used + uint32_t hashoe :1; ///< Defines if the hash digest shall be moved to the output buffer + uint32_t rtfupd :1; ///< RTF (Runtime Fingerprint) Update + uint32_t rtfoe :1; ///< RTF (Runtime Fingerprint) Output Enabled + uint32_t :23; ///< RFU + } bits; ///< Access #mcuxClEls_HashOption_t bit-wise +} mcuxClEls_HashOption_t; + +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * @defgroup mcuxClEls_Hash_Functions mcuxClEls_Hash_Functions + * @brief Defines all functions of @ref mcuxClEls_Hash + * @ingroup mcuxClEls_Hash + * @{ + */ + +/** + * @brief Computes the hash of a message. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * @param[in] options The command options. For more information, see #mcuxClEls_HashOption_t. + * @param[in] pInput Padded input data to be hashed + * @param[in] inputLength Size of @p pInput in bytes. Since the input is padded, the length must be a multiple of the block size, see @ref MCUXCLELS_HASH_BLOCK_SIZE_. + * @param[in, out] pDigest Pointer to the memory area that contains/receives the (intermediate) hash digest, allocated by the caller, see @ref MCUXCLELS_HASH_STATE_SIZE_. + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.hashini == #MCUXCLELS_HASH_INIT_ENABLE
+ *
@p options.hashld has no effect and shall be #MCUXCLELS_HASH_LOAD_DISABLE. No data is read from @p pDigest.
+ * + *
@p options.hashld == #MCUXCLELS_HASH_LOAD_DISABLE
+ *
@p pDigest is not expected to contain an initial state. No data is read from @p pDigest.
+ * + *
@p options.rtfoe == #MCUXCLELS_HASH_RTF_UPDATE_ENABLE
+ *
When this option is used the current runtime fingerprint (RTF) value will be appended to the output @p pDigest; an additional #MCUXCLELS_HASH_RTF_OUTPUT_SIZE bytes has to be allocated for @p pDigest.
+ * + *
@p options.hashoe == #MCUXCLELS_HASH_OUTPUT_ENABLE
+ *
The hash state is written to @p pDigest. The size varies depending on the choice of @p options.hashmd, for more information see @ref MCUXCLELS_HASH_STATE_SIZE_ . In cases where the state size and output size differ - see @ref MCUXCLELS_HASH_OUTPUT_SIZE_ -, the state must be truncated by the caller to obtain the final hash value.
+ * + *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hash_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hash_Async( + mcuxClEls_HashOption_t options, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pDigest + ); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_HASH_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h new file mode 100644 index 000000000..c85d8f999 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Hmac.h @@ -0,0 +1,170 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Hmac.h + * @brief ELS header for HMAC support. + * + * This header exposes functions that enable using the ELS for the generation of hashed-key message authentication + * codes (HMAC). + * The supported hash algorithm is SHA2-256. + */ + +/** + * @defgroup mcuxClEls_Hmac mcuxClEls_Hmac + * @brief This part of the @ref mcuxClEls driver supports functionality for hashed-key message authentication codes. + * @ingroup mcuxClEls + * @{ + */ +#ifndef MCUXCLELS_HMAC_H_ +#define MCUXCLELS_HMAC_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * MACROS + **********************************************/ +/** + * @defgroup mcuxClEls_Hmac_Macros mcuxClEls_Hmac_Macros + * @brief Defines all macros of @ref mcuxClEls_Hmac + * @ingroup mcuxClEls_Hmac + * @{ + */ +/** + * @defgroup MCUXCLELS_HMAC_EXTERNAL_KEY_ MCUXCLELS_HMAC_EXTERNAL_KEY_ + * @brief Defines valid options to be used by #mcuxClEls_HmacOption_t + * @ingroup mcuxClEls_Hmac_Macros + * @{ + */ +#define MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE 1U ///< Set #mcuxClEls_HmacOption_t.extkey to this value to use an external key +#define MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE 0U ///< Set #mcuxClEls_HmacOption_t.extkey to this value to use a key from the ELS keystore +/** + * @} + */ + +#define MCUXCLELS_HMAC_PADDED_KEY_SIZE ((size_t) 64U) ///< HMAC Key size: 64 bytes +#define MCUXCLELS_HMAC_OUTPUT_SIZE ((size_t) 32U) ///< HMAC Output size: 32 bytes +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Hmac_Types mcuxClEls_Hmac_Types + * @brief Defines all types of @ref mcuxClEls_Hmac + * @ingroup mcuxClEls_Hmac + * @{ + */ +/** + * @brief Command option bit field for #mcuxClEls_Hmac_Async. + * + * Valid option values can be found under @ref MCUXCLELS_HMAC_EXTERNAL_KEY_. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word + } word; ///< Access #mcuxClEls_CipherOption_t word-wise + struct + { + uint32_t :13; ///< RFU + uint32_t extkey :1; ///< Whether an external key should be used + uint32_t :18; ///< RFU + } bits; ///< Access #mcuxClEls_CipherOption_t word-wise +} mcuxClEls_HmacOption_t; +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Hmac_Functions mcuxClEls_Hmac_Functions + * @brief Defines all functions of @ref mcuxClEls_Hmac + * @ingroup mcuxClEls_Hmac + * @{ + */ +/** + * @brief Performs HMAC with SHA-256. + * + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options The command options. For more information, see #mcuxClEls_HmacOption_t. + * @param[in] keyIdx The HMAC key index, if an internal key shall be used + * @param[in] pPaddedKey Pointer to a memory location containing the padded HMAC key + * @param[in] pInput Pointer to a memory location which contains the data to be authenticated + * @param[in] inputLength Size of @p pInput in bytes + * @param [out] pOutput The output message authentication code + * + * The properties of some parameters change with respect to selected options. + * + *
+ *
Parameter properties
+ * + *
+ *
@p options.extkey == #MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE
+ *
@p keyIdx is ignored. + * + * @p pPaddedKey must contain the padded HMAC key, which can mean one of two things depending on the length of the original HMAC key, LkHMAC: + *
  • If LkHMAC ≤ #MCUXCLELS_HMAC_PADDED_KEY_SIZE, @p pPaddedKey must be the HMAC key padded with zero-bytes to fill the required length of #MCUXCLELS_HMAC_PADDED_KEY_SIZE bytes.
    • + * + *
  • If LkHMAC > #MCUXCLELS_HMAC_PADDED_KEY_SIZE, @p pPaddedKey must contain the SHA-256 hash of the HMAC key, padded with zero-bytes to fill the required length of #MCUXCLELS_HMAC_PADDED_KEY_SIZE bytes.
+ * + *
@p options.extkey == #MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE
+ *
@p keyIdx must be a valid key index with the correct usage rights for HMAC. + * + * @p pPaddedKey is ignored.
+ * + *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hmac_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hmac_Async( + mcuxClEls_HmacOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pPaddedKey, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pOutput + ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_HMAC_H_ */ +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h new file mode 100644 index 000000000..a92efbfa2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Kdf.h @@ -0,0 +1,338 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Kdf.h + * @brief ELS header for key derivation. + * + * This header exposes functions that enable using the ELS for various key derivation commands. + * The supported key derivation algorithms are CKDF, HKDF, TLS + */ + + +/** + * @defgroup mcuxClEls_Kdf mcuxClEls_Kdf + * @brief This part of the @ref mcuxClEls driver supports functionality for key derivation + * @ingroup mcuxClEls + * @{ + */ + +/** + * @defgroup mcuxClEls_Kdf_Macros mcuxClEls_Kdf_Macros + * @brief Defines all macros of @ref mcuxClEls_Kdf + * @ingroup mcuxClEls_Kdf + * @{ + */ + +#ifndef MCUXCLELS_KDF_H_ +#define MCUXCLELS_KDF_H_ + +#include // Exported features flags header + + + + + +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ + +/** + * @defgroup mcuxClEls_Kdf_Define mcuxClEls_Kdf_Define + * @brief constants + * @ingroup mcuxClEls_Kdf_Macros + * @{ + */ + + +#define MCUXCLELS_CKDF_DERIVATIONDATA_SIZE 12u ///< Size of CKDF SP800-108 derivation data +#define MCUXCLELS_CKDF_ALGO_SP800108 0x0u ///< Use SP800-108 algorithm + + + + +#define MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE 32u ///< Size of HKDF derivation data +#define MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE 32u ///< Size of HKDF SP800-56C derived key + +#define MCUXCLELS_HKDF_VALUE_RTF_DERIV ((uint32_t) 1u<< 0u) ///< Use RTF as derivation input +#define MCUXCLELS_HKDF_VALUE_MEMORY_DERIV ((uint32_t) 0u<< 0u) ///< Use derivation input from system memory + +#define MCUXCLELS_HKDF_ALGO_RFC5869 0x0u ///< Use RFC5869 algorithm +#define MCUXCLELS_HKDF_ALGO_SP80056C 0x1u ///< Use SP800-56C algorithm + +#define MCUXCLELS_HKDF_RTF_DERIV 1U ///< Use RTF as derivation input +#define MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV 0U ///< Use derivation input from system memory + +#define MCUXCLELS_TLS_DERIVATIONDATA_SIZE ((size_t) 80u) ///< Size of TLS derivation data +#define MCUXCLELS_TLS_RANDOM_SIZE ((size_t) 32u) ///< Size of random bytes for TLS + +#define MCUXCLELS_TLS_INIT 0u ///< Perform master key generation +#define MCUXCLELS_TLS_FINALIZE 1u ///< Perform session key generation + +/** + * @} + */ /* mcuxClEls_Kdf_Define */ + +/********************************************** + * TYPEDEFS + **********************************************/ + +/** + * @defgroup mcuxClEls_Kdf_Types mcuxClEls_Kdf_Types + * @brief Defines all types of @ref mcuxClEls_Kdf + * @ingroup mcuxClEls_Kdf + * @{ + */ + +/** Internal command option bit field for CKDF functions. */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_ + } word; + struct + { + uint32_t :12; + uint32_t ckdf_algo :2; ///< Defines which algorithm and mode shall be used. This option is set internally and will be ignored: + ///< #MCUXCLELS_CKDF_ALGO_SP800108 = Use SP800-108 algorithm + uint32_t :18; + } bits; +} mcuxClEls_CkdfOption_t; + +/** Command option bit field for #mcuxClEls_Hkdf_Rfc5869_Async. */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_ + } word; + struct + { + uint32_t rtfdrvdat :1; ///< #MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV=use derivation input from system memory, #MCUXCLELS_HKDF_RTF_DERIV=use RTF (runtime fingerprint) as derivation input + uint32_t hkdf_algo :1; ///< Defines which algorithm shall be used. This option is set internally and will be ignored: + ///< #MCUXCLELS_HKDF_ALGO_RFC5869 = Use RFC5869 algorithm + ///< #MCUXCLELS_HKDF_ALGO_SP80056C = Use SP800-56C algorithm + uint32_t :30; + } bits; +} mcuxClEls_HkdfOption_t; + +/** Internal command option bit field for #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, and #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_HKDF_VALUE_ + } word; + struct + { + uint32_t :10; + uint32_t mode :1; ///< Defines which phase of the key generation is performed. This option is set internally and will be ignored: + ///< #MCUXCLELS_TLS_INIT = Calculate master key from premaster key + ///< #MCUXCLELS_TLS_FINALIZE = Calculate session keys from master key + uint32_t :21; + } bits; +} mcuxClEls_TlsOption_t; + +/** + * @} + */ /* mcuxClEls_Kdf_Types */ + +/** + * @} + */ /* mcuxClEls_Kdf_Macros */ + + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Kdf_Functions mcuxClEls_Kdf_Functions + * @brief Defines all functions of @ref mcuxClEls_Kdf + * @ingroup mcuxClEls_Kdf + * @{ + */ + + +/** + * @brief Derives a key using the HKDF (HMAC-based key derivation function) according to RFC5869. + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * Call #mcuxClEls_WaitForOperation to complete the operation. + * @param[in] options The command options. For more information, see #mcuxClEls_HkdfOption_t. + * @param[in] derivationKeyIdx Key index used for derivation. Must be a 256-bit key with HKDF property bit set to 1. + * @param[in] targetKeyIdx Key bank number of the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key. + * @param[in] targetKeyProperties Requested properties for the derived key. The ksize field will be ignored. + * @param[in] pDerivationData The algorithm-specific derivation data, the length is #MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE bytes + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * + * + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Rfc5869_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Rfc5869_Async( + mcuxClEls_HkdfOption_t options, + mcuxClEls_KeyIndex_t derivationKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx, + mcuxClEls_KeyProp_t targetKeyProperties, + uint8_t const * pDerivationData + ); + +/** Derives a key using the HKDF (HMAC-based key derivation function) according to SP800-56C one-step approach with Sha2-256. + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] derivationKeyIdx Key index used for derivation. Must be a 256-bit key with HKDF property bit set to 1. + * @param[out] pTagetKey Memory area to store the derived key. Will be a 256-bit key, the user must ensure there is enough space in the keystore to hold the derived key. + * @param[in] pDerivationData The algorithm-specific derivation data + * @param[in] derivationDataLength Length of the derivation data + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Hkdf_Sp80056c_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Sp80056c_Async( + mcuxClEls_KeyIndex_t derivationKeyIdx, + uint8_t * pTagetKey, + uint8_t const * pDerivationData, + size_t derivationDataLength + ); + + +/** Derives a key using the NIST SP 800-108 CMAC-based Extract-and-Expand Key Derivation Function. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] derivationKeyIdx Key index used for derivation + * @param[in] targetKeyIdx Key bank number of the derived key + * @param[in] targetKeyProperties Requested properties for the derived key. Only set usage bits. + * @param[in] pDerivationData The algorithm-specific derivation data, the length is #MCUXCLELS_CKDF_DERIVATIONDATA_SIZE bytes + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Ckdf_Sp800108_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Ckdf_Sp800108_Async( + mcuxClEls_KeyIndex_t derivationKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx, + mcuxClEls_KeyProp_t targetKeyProperties, + uint8_t const * pDerivationData + ); + + + +/** Generates a TLS master key based on a pre-master key and derivation data, according to the TLS 1.2 specification. + * The pre-master key is overwritten in this operation. + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] pDerivationData The TLS derivation data, consisting of Label, Client Random and Server Random from the TLS 1.2 specification. + * Note: The order is different from #mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async. + * @param[in] keyProperties Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored. + * @param[in] keyIdx The index of the TLS pre-master key, which is overwritten with the master key + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async( + uint8_t const * pDerivationData, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t keyIdx + ); + +/** Generates TLS session keys based on a master key and derivation data, according to the TLS 1.2 specification. + * The master key and the following five key indices are overwritten in this operation. + * The keys are written in the following order: + *
    + *
  1. Client Encryption Key + *
  2. Client Message Authentication Key + *
  3. Server Encryption Key + *
  4. Server Message Authentication Key + *
+ * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] pDerivationData The TLS derivation data, consisting of Label, Server Random and Client Random from the TLS 1.2 specification. + * Note: The order is different from #mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async. + * @param[in] keyProperties Desired key properties. Only #mcuxClEls_KeyProp_t::upprot_priv and #mcuxClEls_KeyProp_t::upprot_sec are used, the rest are ignored. + * @param[in] keyIdx The index of the TLS master key, which is overwritten with one of the session keys. + * There must be three further consecutive unoccupied key indices following this index. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async( + uint8_t const * pDerivationData, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t keyIdx + ); + +/** + * @} + */ /* mcuxClEls_Kdf_Functions */ + +/** + * @} + */ /* mcuxClEls_Kdf */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_KDF_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h new file mode 100644 index 000000000..8b2c8b233 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_KeyManagement.h @@ -0,0 +1,332 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_KeyManagement.h + * @brief ELS header for key management. + * + * This header exposes functions that can be used to manage the keystore of ELS. + * This includes: + * - Importing keys + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT + * - Exporting keys + * @endif + * @if MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE + * - Deleting keys + * @endif + */ + +/** + * @defgroup mcuxClEls_KeyManagement mcuxClEls_KeyManagement + * @brief This part of the @ref mcuxClEls driver supports functionality for keys management + * @ingroup mcuxClEls + * @{ + */ + +#ifndef MCUXCLELS_KEYMANAGEMENT_H_ +#define MCUXCLELS_KEYMANAGEMENT_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_KeyManagement_Macros mcuxClEls_KeyManagement_Macros + * @brief Defines all macros of @ref mcuxClEls_KeyManagement + * @ingroup mcuxClEls_KeyManagement + * @{ + */ + +/** + * @defgroup MCUXCLELS_KEYIMPORT_VALUE_KFMT_ MCUXCLELS_KEYIMPORT_VALUE_KFMT_ + * @brief Defines valid options (word value) to be used by #mcuxClEls_KeyImport_Async + * @ingroup mcuxClEls_KeyManagement_Macros + * + * @{ + */ + +#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF ((uint32_t) 0u<< 6u) ///< Key format UDF with shares in RTL or memory +#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394 ((uint32_t) 1u<< 6u) ///< Key format RFC3394 with shares in memory +#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF ((uint32_t) 2u<< 6u) ///< Key from PUF +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK ((uint32_t) 3u<< 6u) ///< Key from Public Key Certificate +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_KEYIMPORT_KFMT_ MCUXCLELS_KEYIMPORT_KFMT_ + * @brief Defines valid options (bit values) to be used by #mcuxClEls_KeyImport_Async + * @ingroup mcuxClEls_KeyManagement_Macros + * + * @{ + */ +#define MCUXCLELS_KEYIMPORT_KFMT_UDF (0x00u) ///< Key format UDF with shares in RTL or memory +#define MCUXCLELS_KEYIMPORT_KFMT_RFC3394 (0x01u) ///< Key format RFC3394 with shares in memory +#define MCUXCLELS_KEYIMPORT_KFMT_PUF (0x02u) ///< Key from PUF +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYIMPORT_KFMT_PBK (0x03u) ///< Key from Public Key Certificate +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE (0x01U) ///< Reverse fetch enabled. For internal use +#define MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE (0x00U) ///< Reverse fetch disabled. For internal use +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +#define MCUXCLELS_RFC3394_OVERHEAD ((size_t) 16u) ///< Overhead between RFC3394 blob and key size +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_RFC3394_ MCUXCLELS_RFC3394_ + * @brief Defines specifying the length of RFC3394 containers + * @ingroup mcuxClEls_KeyManagement_Macros + * + * @{ + */ +#define MCUXCLELS_RFC3394_CONTAINER_SIZE_128 ((size_t) 256u/8u) ///< Size of RFC3394 container for 128 bit key +#define MCUXCLELS_RFC3394_CONTAINER_SIZE_256 ((size_t) 384u/8u) ///< Size of RFC3394 container for 256 bit key +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_RFC3394_CONTAINER_SIZE_P256 ((size_t) 640u/8u) ///< Size of RFC3394 container for P256 bit public key +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ +/** + * @} + */ + +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_KeyManagement_Types mcuxClEls_KeyManagement_Types + * @brief Defines all types of @ref mcuxClEls_KeyManagement + * @ingroup mcuxClEls_KeyManagement + * @{ + */ + +/** + * @brief Command option bit field for #mcuxClEls_KeyImport_Async + * + * Bit field to configure #mcuxClEls_KeyImport_Async. + * See @ref MCUXCLELS_KEYIMPORT_KFMT_ for possible options in case the struct is accessed bit-wise. + * See @ref MCUXCLELS_KEYIMPORT_VALUE_KFMT_ for possible options in case the struct is accessed word-wise. + */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYIMPORT_VALUE_KFMT_ + } word; ///< Access #mcuxClEls_KeyImportOption_t word-wise + struct + { + uint32_t :4; ///< RFU + uint32_t revf :1; ///< This field is managed internally + uint32_t :1; ///< RFU + uint32_t kfmt :2; ///< Defines the key import format, one of @ref MCUXCLELS_KEYIMPORT_KFMT_ + uint32_t :24; ///< RFU + } bits; ///< Access #mcuxClEls_KeyImportOption_t bit-wise +} mcuxClEls_KeyImportOption_t; + +/** + * @} + */ + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_KeyManagement_Functions mcuxClEls_KeyManagement_Functions + * @brief Defines all functions of @ref mcuxClEls_KeyManagement + * @ingroup mcuxClEls_KeyManagement + * @{ + */ + +/** + * @brief Deletes a key from keystore at the given index. + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] keyIdx The index of the key to be deleted + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_SW_FAULT if a failure occurred + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyDelete_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyDelete_Async( + mcuxClEls_KeyIndex_t keyIdx +); + + + +/** @brief Imports a key from external storage to an internal key register. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] options One of @ref MCUXCLELS_KEYIMPORT_KFMT_ + * @param[in] pImportKey Pointer to the RFC3394 container of the key to be imported + * @param[in] importKeyLength Length of the RFC3394 container of the key to be imported + * @param[in] wrappingKeyIdx Index of the key wrapping key, if importing RFC3394 format + * @param[in] targetKeyIdx The desired key index of the imported key + * + *
+ *
Parameter properties
+ *
+ *
@p options.kfmt != #MCUXCLELS_KEYIMPORT_KFMT_RFC3394
+ *
    + *
  • @p pImportKey is ignored.
    • + *
  • @p importKeyLength is ignored.
    • + *
  • @p wrappingKeyIdx is ignored.
    • + *
  • @p targetKeyIdx is ignored. The unpacked key is automatically stored in key slots 0, 1.
    • + *
+ * + *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImport_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImport_Async( + mcuxClEls_KeyImportOption_t options, + uint8_t const * pImportKey, + size_t importKeyLength, + mcuxClEls_KeyIndex_t wrappingKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx + ); + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +/** @brief Imports a public key to an internal key register if the signature verification of the provided public key against + * the provided signature is correct. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] pCertificate Pointer to the Certificate structure + * @param[in] certificateLength Length of the Certificate structure + * @param[in] publicKeyOffset Offset of the Public key to be imported within @p pCertificate + * @param[in] pSignature Signed challenge used to authenticate the imported key. Must be word aligned + * @param[in] verifyingKeyIdx The key index of the verifying public key + * @param[in] keyProperties The desired key properties of the imported key + * @param[in] targetKeyIdx The desired key index of the imported key + * @param[out] pOutput Pointer to the memory area which will receive the recalculated value of the R component in case of a successful + * certificate verification. Must be word aligned + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyImportPuk_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImportPuk_Async( + uint8_t const * pCertificate, + size_t certificateLength, + size_t publicKeyOffset, + uint8_t const * pSignature, + mcuxClEls_KeyIndex_t verifyingKeyIdx, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t targetKeyIdx, + uint8_t * pOutput + ); +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +/** @brief Exports a key from an internal key register to external storage, using a wrapping key. + * + * @if ELS_AES_WITH_SIDE_CHANNEL_PROTECTION + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * @endif + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] wrappingKeyIdx The key used for key wrapping + * @param[in] exportKeyIdx The key to export + * @param[out] pOutput The memory address of the exported key + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_INVALID_PARAM if invalid parameters were specified + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_KeyExport_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyExport_Async( + mcuxClEls_KeyIndex_t wrappingKeyIdx, ///< [in] The key used for key wrapping + mcuxClEls_KeyIndex_t exportKeyIdx, ///< [in] The key to export + uint8_t * pOutput ///< [out] The memory address of the exported key + ); + +/** @brief Exports the properties of the keys stored in the ELS internal keystore + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[in] keyIdx Request key properties of the index defined here + * @param[out] pKeyProp Key properties of the index provided + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK on successful request */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_GetKeyProperties) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetKeyProperties( + mcuxClEls_KeyIndex_t keyIdx, + mcuxClEls_KeyProp_t * pKeyProp + ); + +/** + * @} + */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_KEYMANAGEMENT_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h new file mode 100644 index 000000000..afb11526d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Rng.h @@ -0,0 +1,435 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Rng.h + * @brief ELS header for random number generation. + * This header exposes functions to configure the ELS RNGs (DRBG and DTRNG) and to generate random data. + */ + +#ifndef MCUXCLELS_RNG_H_ +#define MCUXCLELS_RNG_H_ + +#include // Exported features flags header +#include // Common functionality + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClEls_Rng mcuxClEls_Rng + * @brief This part of the @ref mcuxClEls driver supports functionality for random number generation + * @ingroup mcuxClEls + * @{ + */ + + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClEls_Rng_Macros mcuxClEls_Rng_Macros + * @brief Defines all macros of @ref mcuxClEls_Rng + * @ingroup mcuxClEls_Rng + * @{ + */ +#define MCUXCLELS_RNG_DTRNG_CONFIG_SIZE ((uint8_t) 84) ///< Size of DTRNG configuration +#define MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE ((uint8_t) 52) ///< Size of DTRNG characterization data +#define MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE ((uint8_t) 188) ///< Size of DTRNG characterization result + +#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE 4U ///< Minimum output size of #mcuxClEls_Rng_DrbgTestExtract_Async +#define MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE ((uint32_t) 1U << 16U) ///< Maximum output size of #mcuxClEls_Rng_DrbgTestExtract_Async + +#define MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE ((uint32_t) 0U) ///< Command options value for DRBG Test Instantiate command. For internal use +#define MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT ((uint32_t) 1U) ///< Command options value for DRBG Test Extract command. For internal use +#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB ((uint32_t) 3U) ///< Command options value for DRBG Test AES-ECB command. For internal use +#define MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR ((uint32_t) 2U) ///< Command options value for DRBG Test AES-CTR command. For internal use + +#ifdef MCUXCL_FEATURE_ELS_RND_RAW +#define MCUXCLELS_RNG_RND_REQ_RND_RAW ((uint32_t) 1U << 1) ///< Command options value for RND_REQ command. For internal use +#define MCUXCLELS_RNG_RAW_ENTROPY_SIZE ((uint32_t) 32U) ///< Fixed size of raw entropy when using the DTRNG +#endif /* MCUXCL_FEATURE_ELS_RND_RAW */ +#ifdef MCUXCL_FEATURE_ELS_PRND_INIT +#define MCUXCLELS_RNG_RND_REQ_PRND_INIT ((uint32_t) 1U << 0) ///< Command options value for PRND_INIT command. For internal use +#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */ +/** + * @} + */ + + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClEls_Rng_Functions mcuxClEls_Rng_Functions + * @brief Defines all functions of @ref mcuxClEls_Rng + * @ingroup mcuxClEls_Rng + * @{ + */ + +/** + * @brief Writes random data from the ELS DRBG to the given buffer. + * + * This function fills a buffer with random values from the DRBG. The DRBG provides 128 bits of security strength. + * + * Before execution, ELS will wait until #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_HIGH. This can lead to a delay if the DRBG is in a state with less security strength at the time of the call. + * + * If the random values from the DRBG are later used as a cryptographic key, the security strength of the cryptographic operation using the generated key should not exceed that of the DRBG. + * + * To name a few examples, this means (as per NIST SP 800-57 Part 1 Rev. 5): + * - AES-192 or AES-256 keys generated with this function will provide only 128 bits of security strength + * - RSA keys longer than 3072 bits will provide only 128 bits of security strength + * - ECC keys longer than 383 bits will provide only 128 bits of security strength + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[out] pOutput Pointer to the beginning of the memory area to fill with random data + * @param[in] outputLength Number of requested random bytes + * + *
+ *
Parameter properties
+ *
+ *
@p outputLength
+ *
supported values are #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to + * #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_SW_FAULT in case of an internal error + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequest_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequest_Async( + uint8_t * pOutput, + size_t outputLength + ); + +#ifdef MCUXCL_FEATURE_ELS_RND_RAW +/** + * @brief Writes 32 bytes of raw random data from the ELS TRNG to the given buffer. + * + * This function fills a buffer with raw (unprocessed) random values from the TRNG. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @param[out] pOutput Pointer to the beginning of the memory area to fill with random data + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgRequestRaw_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequestRaw_Async( + uint8_t * pOutput + ); +#endif /* MCUXCL_FEATURE_ELS_RND_RAW */ + +/** + * @brief Instantiates the DRBG in test mode. + * + * This function is a support function for FIPS CAVP testing. This function turns the ELS internal DRBG in test mode by loading known entropy from system memory. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. + * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy. + * + * @param[in] pEntropy Pointer to the input entropy data + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestInstantiate_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestInstantiate_Async( + uint8_t const * pEntropy + ); + +/** + * @brief Performs a DRBG extraction. + * + * This function is a support function for FIPS CAVP testing. This function mimics the behavior of #mcuxClEls_Rng_DrbgRequest_Async and fills a buffer with random data when DRBG is in test mode. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. + * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy. + * + * @attention #mcuxClEls_Rng_DrbgTestInstantiate_Async must be called prior to this function. + * + * @param[out] pOutput Pointer to the output random number + * @param[in] outputLength Length of the random number + * + *
+ *
Parameter properties
+ *
+ *
@p outputLength
+ *
supported values are #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE bytes up to + * #MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE bytes. The size must be a multiple of 4.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref MCUXCLELS_STATUS_ and @ref mcuxCsslFlowProtection) + * @else + * @return An error code (see @ref MCUXCLELS_STATUS_) + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestExtract_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestExtract_Async( + uint8_t * pOutput, + size_t outputLength + ); + +/** + * @brief Encrypts data using the AES-ECB engine of the DRBG. + * + * This function is a support function for FIPS CAVP testing. This function performs an AES-ECB encryption on system data to evaluate the encryption engine of the DRBG. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. + * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy. + * + * @param[in] pDataKey Pointer to the data and key + * @param[out] pOutput Pointer to the encrypted output + * + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesEcb_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesEcb_Async( + uint8_t const * pDataKey, + uint8_t * pOutput + ); + +/** + * @brief Encrypts data using the AES-CTR engine of the DRBG. + * + + * This function is a support function for FIPS CAVP testing. This function performs an AES-CTR encryption on system data to evaluate the encryption engine of the DRBG in test mode. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * Note that this function will alter the ELS internal entropy state which needs to be updated by the TRNG to use the DRBG in normal mode. + * The update process is majorly impacted by the time the TRNG needs to provide fresh entropy. + * + * @param[in] pData Pointer to the data to be encrypted + * @param[in] dataLength Length of the data to be encrypted + * @param[in] pIvKey Pointer to the IV and key + * @param[out] pOutput Pointer to the encrypted output + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_DrbgTestAesCtr_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesCtr_Async( + uint8_t const * pData, + size_t dataLength, + uint8_t const * pIvKey, + uint8_t * pOutput + ); + +/** + * @brief Loads a configuration of the ELS DTRNG. + * + * This function overwrites the default DTRNG configuration in order to optimize or fine tune the DTRNG entropy gathering process. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * Note that the TRNG configuration set by this function is non-persistent and any reset of the ELS (e.g. a power-cycle or calling #mcuxClEls_Reset_Async) will resets the DTRNG configuration to its default value. + * + * @if MCUXCL_FEATURE_ELS_SHA_DIRECT + * It must be ensured that SHA-Direct mode is disabled when calling this function (see #mcuxClEls_ShaDirect_Disable). + * @endif + * + * @param[in] pInput The pointer to DTRNG initialization data + * + *
+ *
Parameter properties
+ *
+ *
@p pInput
+ *
The size is #MCUXCLELS_RNG_DTRNG_CONFIG_SIZE bytes.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigLoad_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigLoad_Async( + uint8_t const * pInput + ); + + +/** + * @brief Performs characterization of the ELS DTRNG. + * + * This function evaluates a DTRNG configuration for device specific characterization. The configuration used for characterization has to be placed in system memory. + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @attention If this function is called once, all other ELS commands except #mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async are blocked until any reset of the ELS (e.g. a power-cycle or calling #mcuxClEls_Reset_Async) is triggered. + * + * @param[in] pInput The pointer to DTRNG initialization data + * @param[out] pOutput The pointer to the evaluation result + * + *
+ *
Parameter properties
+ *
+ *
@p pInput
+ *
The size is #MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE bytes.
+ *
@p pOutput
+ *
The size is #MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE bytes.
+ *
+ *
+ * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async( + uint8_t const * pInput, + uint8_t * pOutput + ); + +#ifdef MCUXCL_FEATURE_ELS_PRND_INIT +/** + * @brief Initializes the ELS PRNG. + * + * This function initializes the PRNG. After this operation #mcuxClEls_HwState_t.drbgentlvl == #MCUXCLELS_STATUS_DRBGENTLVL_LOW. This can lead to a delay if the DRBG is in a state with lower security strength at the time of the call. + * + * Call #mcuxClEls_WaitForOperation to complete the operation. + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT if a running operation prevented the request + * @retval #MCUXCLELS_STATUS_OK_WAIT on successful request + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_Init_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_Init_Async(void); +#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */ + +/** + * @brief Returns one random word from the ELS PRNG. + * + * This function returns one low-quality random CPU word gathered from the PRNG. + * + * @attention PRNG has to be initialized prior to the first time calling this function. + * + * @param[out] pWord The pointer to the random word + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_OK on successful request + * @retval #MCUXCLELS_STATUS_HW_PRNG in case of insufficient entropy + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandomWord) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandomWord( + uint32_t * pWord + ); + +/** + * @brief Writes random data from the ELS PRNG to the given buffer. + * + * This function fills a buffer with low-quality random values gathered from the PRNG. + * + * @attention PRNG has to be initialized prior to the first time calling this function. + * + * @param[out] pOutput Pointer to the beginning of the memory area to fill with random data from PRNG + * @param[in] outputLength Size of @p pOutput in bytes + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_OK on successful request + * @retval #MCUXCLELS_STATUS_HW_PRNG in case of insufficient entropy + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Prng_GetRandom) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandom( + uint8_t * pOutput, + size_t outputLength + ); + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +/** + * @brief This function checks if a DRBG reseeding is needed and if so reseeds the ELS DRBG. + * + * This function checks if the ELS DRBG needs to be reseeded by the DTRNG, and if so, executes the iterative seeding process. + * The function internally disables ELS interrupts before (potentially) running the iterative seeding process and restores + * the original ELS interrupt enable flags afterwards, before returning to the caller. This allows to properly use the function + * in an ELS interrupt handler to reseed the ELS DRBG when needed. + * + * @param[in] pDtrngConfig Pointer to the beginning of the memory area which contains the ELS DTRNG config + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + * @endif + * @retval #MCUXCLELS_STATUS_OK on successful request + * @retval #MCUXCLELS_STATUS_SW_FAULT in case the iterative seeding failed + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed(const uint8_t *pDtrngConfig); +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + +/** + * @} + */ /* mcuxClEls_Rng_Functions */ + + +/** + * @} + */ /* mcuxClEls_Rng */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_RNG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h new file mode 100644 index 000000000..fc3573f60 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_Types.h @@ -0,0 +1,305 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Types.h + * @brief ELS type header. + * + * This header defines types that are used by other mcuxClEls headers. + */ +/** + * @defgroup mcuxClEls_Types mcuxClEls_Types + * @brief This part of the @ref mcuxClEls driver defines common types + * @ingroup mcuxClEls + * @{ + */ +#ifndef MCUXCLELS_TYPES_H_ +#define MCUXCLELS_TYPES_H_ + +#include +#include +#include // Exported features flags header +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * MACROS + **********************************************/ +/** + * @defgroup mcuxClEls_Types_Macros mcuxClEls_Types_Macros + * @brief Defines all macros of @ref mcuxClEls_Types + * @ingroup mcuxClEls_Types + * @{ + */ + +#define MCUXCLELS_KEY_SLOTS (20U) ///< Number of key slots in the ELS key store. + +/** @defgroup MCUXCLELS_KEYPROPERTY_VALUE_ MCUXCLELS_KEYPROPERTY_VALUE_ + * @brief Constants for initalizing #mcuxClEls_KeyProp_t.word + * @ingroup mcuxClEls_Types_Macros + * @{ + */ +#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128 ((uint32_t) 0u<< 0u) ///< 128-bit key +#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256 ((uint32_t) 1u<< 0u) ///< 256-bit key +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512 ((uint32_t) 3u<< 0u) ///< 512-bit key +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ +#define MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE ((uint32_t) 1u<< 5u) ///< Key is active (loaded) +#define MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT ((uint32_t) 1u<< 6u) ///< First part of multi-slot key +#define MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT ((uint32_t) 1u<< 7u) ///< General purpose key slot +#define MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT ((uint32_t) 1u<< 8u) ///< Retention key slot +#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT ((uint32_t) 1u<< 9u) ///< Hardware output key slot +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYPROPERTY_VALUE_PUK ((uint32_t) 1u<<11u) ///< Trusted Public Key +#define MCUXCLELS_KEYPROPERTY_VALUE_TECDH ((uint32_t) 1u<<12u) ///< Private key that can only be used in ECDH with Trusted Public Key +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ +#define MCUXCLELS_KEYPROPERTY_VALUE_CMAC ((uint32_t) 1u<<13u) ///< CMAC key +#define MCUXCLELS_KEYPROPERTY_VALUE_KSK ((uint32_t) 1u<<14u) ///< Key signing key +#define MCUXCLELS_KEYPROPERTY_VALUE_RTF ((uint32_t) 1u<<15u) ///< RTF signing key +#define MCUXCLELS_KEYPROPERTY_VALUE_CKDF ((uint32_t) 1u<<16u) ///< CKDF signing key +#define MCUXCLELS_KEYPROPERTY_VALUE_HKDF ((uint32_t) 1u<<17u) ///< HKDF signing key +#define MCUXCLELS_KEYPROPERTY_VALUE_ECSGN ((uint32_t) 1u<<18u) ///< ECC signing key +#define MCUXCLELS_KEYPROPERTY_VALUE_ECDH ((uint32_t) 1u<<19u) ///< ECC Diffie Hellman private key +#define MCUXCLELS_KEYPROPERTY_VALUE_AES ((uint32_t) 1u<<20u) ///< AES key +#define MCUXCLELS_KEYPROPERTY_VALUE_HMAC ((uint32_t) 1u<<21u) ///< HMAC key +#define MCUXCLELS_KEYPROPERTY_VALUE_KWK ((uint32_t) 1u<<22u) ///< Key Wrapping Key +#define MCUXCLELS_KEYPROPERTY_VALUE_KUOK ((uint32_t) 1u<<23u) ///< Key Unwrapping Only Key +#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET ((uint32_t) 1u<<24u) ///< TLS Premaster Secret +#define MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET ((uint32_t) 1u<<25u) ///< TLS Master Secret +#define MCUXCLELS_KEYPROPERTY_VALUE_KGSRC ((uint32_t) 1u<<26u) ///< Can provide key material input for ECC key generation +#define MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT ((uint32_t) 1u<<27u) ///< A key to be used in a hardware out key slot +#define MCUXCLELS_KEYPROPERTY_VALUE_WRPOK ((uint32_t) 1u<<28u) ///< The key can be wrapped +#define MCUXCLELS_KEYPROPERTY_VALUE_DUK ((uint32_t) 1u<<29u) ///< Device Unique Key +#define MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED ((uint32_t) 1u<<30u) ///< Caller must be in privileged mode to use the key +#define MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED ((uint32_t) 0u<<30u) ///< Caller does not have to be in privileged mode to use the key +#define MCUXCLELS_KEYPROPERTY_VALUE_SECURE ((uint32_t) 0u<<31u) ///< Caller must be in secure mode to use the key +#define MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE ((uint32_t) 1u<<31u) ///< Caller does not have to be in secure mode to use the key +/** + * @} + */ + +/** @defgroup MCUXCLELS_KEYPROPERTY_ MCUXCLELS_KEYPROPERTY_ + * @brief Constants for initalizing #mcuxClEls_KeyProp_t.bits + * @ingroup mcuxClEls_Types_Macros + * @{ + */ +#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_128 0U ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 128 bit key +#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_256 1U ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 256 bit key +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYPROPERTY_KEY_SIZE_512 3U ///< This value of #mcuxClEls_KeyProp_t.ksize indicates a 512 bit key +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ +#define MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.kactv indicates that the slot contains an active key +#define MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.kactv indicates that the slot does not contain active key +#define MCUXCLELS_KEYPROPERTY_BASE_SLOT 1U ///< This value of #mcuxClEls_KeyProp_t.kbase indicates that the slot is the base slot of a 2-slot key +#define MCUXCLELS_KEYPROPERTY_SECOND_SLOT 0U ///< This value of #mcuxClEls_KeyProp_t.kbase indicates that the slot is the second slot of a 2-slot key +#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.fgp indicates that the slot is a retention key slot or a hardware out key slot +#define MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.fgp indicates that the slot is a neither retention key slot nor hardware out key slot +#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.frtn indicates that the slot is a retention key slot +#define MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.frtn indicates that the slot is not a retention key slot +#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.fhwo indicates that the slot is a hardware out key slot +#define MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.fhwo indicates that the slot is not a hardware out key slot +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +#define MCUXCLELS_KEYPROPERTY_PUK_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.upuk indicates that the slot is a Trusted Public Key +#define MCUXCLELS_KEYPROPERTY_PUK_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.upuk indicates that the slot is not a Trusted Public Key +#define MCUXCLELS_KEYPROPERTY_TECDH_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.utecdh indicates that the slot is a Private key that can only be used in ECDH with Trusted Public Key +#define MCUXCLELS_KEYPROPERTY_TECDH_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.utecdh indicates that the slot is not a Private key that can only be used in ECDH with Trusted Public Key +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ +#define MCUXCLELS_KEYPROPERTY_CMAC_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.ucmac indicates that the key can be used for CMAC +#define MCUXCLELS_KEYPROPERTY_CMAC_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.ucmac indicates that the key cannot be used for CMAC +#define MCUXCLELS_KEYPROPERTY_KSK_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uksk indicates that the key can be used for key signing +#define MCUXCLELS_KEYPROPERTY_KSK_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uksk indicates that the key cannot be used for key signing +#define MCUXCLELS_KEYPROPERTY_RTF_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.urtf indicates that the key can be used for RTF signing +#define MCUXCLELS_KEYPROPERTY_RTF_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.urtf indicates that the key cannot be used for RTF signing +#define MCUXCLELS_KEYPROPERTY_CKDF_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uckdf indicates that the key can be used for CKDF +#define MCUXCLELS_KEYPROPERTY_CKDF_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uckdf indicates that the key cannot be used for CKDF +#define MCUXCLELS_KEYPROPERTY_HKDF_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uhkdf indicates that the key can be used for HKDF +#define MCUXCLELS_KEYPROPERTY_HKDF_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uhkdf indicates that the key cannot be used for HKDF +#define MCUXCLELS_KEYPROPERTY_ECC_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uecsg indicates that the key can be used for ECC signing +#define MCUXCLELS_KEYPROPERTY_ECC_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uecsg indicates that the key cannot be used for ECC signing +#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uecdh indicates that the key is a ECC Diffie Hellman private key +#define MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uecdh indicates that the key is not an ECC Diffie Hellman private key +#define MCUXCLELS_KEYPROPERTY_AES_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uaes indicates that the key is an AES key +#define MCUXCLELS_KEYPROPERTY_AES_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uaes indicates that the key is not an AES key +#define MCUXCLELS_KEYPROPERTY_HMAC_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uhmac indicates that the key is an HMAC key +#define MCUXCLELS_KEYPROPERTY_HMAC_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uhmac indicates that the key is not an HMAC key +#define MCUXCLELS_KEYPROPERTY_KWK_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.ukwk indicates that the key is a Key Wrapping Key +#define MCUXCLELS_KEYPROPERTY_KWK_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.ukwk indicates that the key is not a Key Wrapping Key +#define MCUXCLELS_KEYPROPERTY_KUOK_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.ukuok indicates that the key is a Key Unwrapping Only Key +#define MCUXCLELS_KEYPROPERTY_KUOK_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.ukuok indicates that the key is not a Key Unwrapping Only Key +#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.utlspms indicates that the key is a TLS Premaster Secret +#define MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.utlspms indicates that the key is not a TLS Premaster Secret +#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.utlsms indicates that the key is a TLS Master Secret +#define MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.utlsms indicates that the key is not a TLS Master Secret +#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.ukgsrc indicates that the key can be used as key material input for ECC key generation +#define MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.ukgsrc indicates that the key cannot be used as key material input for ECC key generation +#define MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.uhwo indicates that the key can be used in a hardware out key slot +#define MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.uhwo indicates that the key cannot be used in a hardware out key slot +#define MCUXCLELS_KEYPROPERTY_WRAP_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.wrpok indicates that the key can be wrapped +#define MCUXCLELS_KEYPROPERTY_WRAP_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.wrpok indicates that the key cannot be wrapped +#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.duk indicates that the key is a Device Unique Key +#define MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.duk indicates that the key is not a Device Unique Key +#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE 1U ///< This value of #mcuxClEls_KeyProp_t.upprot_priv indicates that the caller must be in privileged mode to use the key +#define MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE 0U ///< This value of #mcuxClEls_KeyProp_t.upprot_priv indicates that the caller does not need to be in privileged mode to use the key +#define MCUXCLELS_KEYPROPERTY_SECURE_TRUE 0U ///< This value of #mcuxClEls_KeyProp_t.upprot_sec indicates that the caller must be in secure mode to use the key +#define MCUXCLELS_KEYPROPERTY_SECURE_FALSE 1U ///< This value of #mcuxClEls_KeyProp_t.upprot_sec indicates that the caller does not need to be in secure mode to use the key +/** + * @} + */ + +/** + * @defgroup MCUXCLELS_STATUS_ MCUXCLELS_STATUS_ + * @brief Return code definitions + * @ingroup mcuxClEls_Types_Macros + * @{ + */ +#define MCUXCLELS_STATUS_OK ((mcuxClEls_Status_t) 0x05552E03u) ///< No error occurred +#define MCUXCLELS_STATUS_OK_WAIT ((mcuxClEls_Status_t) 0x05552E07u) ///< An _Async function successfully started an ELS command. Call #mcuxClEls_WaitForOperation to complete it +#define MCUXCLELS_STATUS_HW_FAULT ((mcuxClEls_Status_t) 0x05555330u) ///< ELS hardware detected a fault +#define MCUXCLELS_STATUS_HW_ALGORITHM ((mcuxClEls_Status_t) 0x05555334u) ///< An algorithm failed in hardware +#define MCUXCLELS_STATUS_HW_OPERATIONAL ((mcuxClEls_Status_t) 0x05555338u) ///< ELS was operated incorrectly +#define MCUXCLELS_STATUS_HW_BUS ((mcuxClEls_Status_t) 0x0555533Cu) ///< A bus access failed +#define MCUXCLELS_STATUS_HW_INTEGRITY ((mcuxClEls_Status_t) 0x05555370u) ///< An integrity check failed in hardware +#define MCUXCLELS_STATUS_HW_PRNG ((mcuxClEls_Status_t) 0x05555374u) ///< Read access to PRNG output while PRNG is not in ready state +#define MCUXCLELS_STATUS_HW_DTRNG ((mcuxClEls_Status_t) 0x05555378u) ///< Unable to get entropy from dTRNG with current configuration +#define MCUXCLELS_STATUS_SW_FAULT ((mcuxClEls_Status_t) 0x0555F0F0u) ///< Software detected a fault +#define MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT ((mcuxClEls_Status_t) 0x055553B0u) ///< an ELS command was started while the ELS was still busy, or a SHA-Direct command was started while the SHA kernel was still busy +#define MCUXCLELS_STATUS_SW_INVALID_PARAM ((mcuxClEls_Status_t) 0x055553F8u) ///< Incorrect parameters were supplied +#define MCUXCLELS_STATUS_SW_INVALID_STATE ((mcuxClEls_Status_t) 0x055553B8u) ///< This can happen when ELS is in a wrong state for the requested ELS command +#define MCUXCLELS_STATUS_SW_COUNTER_EXPIRED ((mcuxClEls_Status_t) 0x055553BCu) ///< A software counter expired while waiting for an ELS operation to finish +#define MCUXCLELS_STATUS_SW_COMPARISON_FAILED ((mcuxClEls_Status_t) 0x05558930u) ///< A comparison between an ELS flag and its expected value failed +#ifdef MCUXCL_FEATURE_ELS_LOCKING +#define MCUXCLELS_STATUS_SW_LOCKING_FAILED ((mcuxClEls_Status_t) 0x055553F4u) ///< Unable to obtain ELS lock +#define MCUXCLELS_STATUS_SW_STATUS_LOCKED ((mcuxClEls_Status_t) 0x05552E0Bu) ///< ELS status is locked +#endif /* MCUXCL_FEATURE_ELS_LOCKING */ +/** @} */ + +#define MCUXCLELS_STATUS_IS_HW_ERROR(x) ((((mcuxClEls_Status_t) (x)) & 0x0000FF00U) == 0x0000E100U) ///< Checks whether an error code is a hardware error. Indicates that an error was reported by ELS hardware. + +#define MCUXCLELS_STATUS_IS_SW_ERROR(x) ((((mcuxClEls_Status_t) (x)) & 0x0000FF00U) == 0x0000F000U) ///< Checks whether an error code is a software error. Indicates that the error was detected by the driver software and not by ELS hardware. + +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClEls_Types_Types mcuxClEls_Types_Types + * @brief Defines all types of @ref mcuxClEls_Types + * @ingroup mcuxClEls_Types + * @{ + */ +/** + * @brief Type for ELS driver status codes + */ +typedef uint32_t mcuxClEls_Status_t; + +/** + * @brief Deprecated type for ELS driver protected status codes + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Status_Protected_t; + +/** + * @brief Type for ELS keystore indices + */ +typedef uint32_t mcuxClEls_KeyIndex_t; + +/** Type for ELS key store key properties */ +typedef union +{ + struct + { + uint32_t value; ///< Accesses the bit field as a full word; initialize with a combination of constants from @ref MCUXCLELS_KEYPROPERTY_VALUE_ + } word; ///< Access #mcuxClEls_KeyProp_t word-wise + struct + { +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL + uint32_t ksize :2; ///< Key size + uint32_t :3; ///< RFU +#else + uint32_t ksize :1; ///< Key size + uint32_t :4; ///< RFU +#endif + uint32_t kactv :1; ///< Status flag to indicate whether the key slot contains an active key or not + uint32_t kbase :1; ///< Status flag to indicate whether the key slot is a base slot or the second slot of a 256-bit key + uint32_t fgp :1; ///< Hardware feature flag: General purpose key slot + uint32_t frtn :1; ///< Hardware feature flag: Retention key slot + uint32_t fhwo :1; ///< Hardware feature flag: Hardware-out key slot +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL + uint32_t :1; ///< RFU + uint32_t upuk :1; ///< Usage permission for Trusted Public Key + uint32_t utecdh :1; ///< Usage permission for Private key that can only be used in ECDH with Trusted Public Key +#else + uint32_t :3; ///< RFU +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + uint32_t ucmac :1; ///< Usage permission for CMAC + uint32_t uksk :1; ///< Usage permission for key signing + uint32_t urtf :1; ///< Usage permission for RTF signing + uint32_t uckdf :1; ///< Usage permission for CKDF + uint32_t uhkdf :1; ///< Usage permission for HKDF + uint32_t uecsg :1; ///< Usage permission for ECDSA signing + uint32_t uecdh :1; ///< Usage permission for Elliptic Curve Diffie-Hellman + uint32_t uaes :1; ///< Usage permission for AES + uint32_t uhmac :1; ///< Usage permission for HMAC + uint32_t ukwk :1; ///< Usage permission for key wrapping + uint32_t ukuok :1; ///< Usage permission for key unwrapping, but not for key wrapping + uint32_t utlspms :1; ///< Usage permission as a TLS premaster secret + uint32_t utlsms :1; ///< Usage permission as a TLS master secret + uint32_t ukgsrc :1; ///< Usage permission as input for ECC key generation + uint32_t uhwo :1; ///< Usage permission in a hardware-out key slot + uint32_t wrpok :1; ///< Usage permission to wrap + uint32_t duk :1; ///< Device-unique key flag + uint32_t upprot_priv :1; ///< Access restriction to privileged mode + uint32_t upprot_sec :1; ///< Access restriction to TrustZone secure mode + } bits; ///< Access #mcuxClEls_KeyProp_t bit-wise +} mcuxClEls_KeyProp_t; + + +#define utlpsms utlspms ///< Deprecated name for #mcuxClEls_KeyProp_t.utlspms + +/** + * @brief Function type for transfer of data to a memory-mapped register + * + * This function type is used as a callback for handling data transfer from memory to a memory-mapped register. + * Such a function shall read data from the @c uint8_t array source, and write data via a sequence of writes to @p destRegister. + * Further specification of this function's behavior can be found in the documentation of the function that accepts this function as a callback parameter. + * + * @param [out] pDestRegister Memory-mapped register that the output data shall be written to + * @param [in] pSource Array containing the input data + * @param [in] sourceLength Size of @p source in bytes + * @param [in, out] pCallerData Custom pointer that is provided by the caller and forwarded to the callback function by the operation + * @return An error code that can be any error code in @ref MCUXCLELS_STATUS_, see individual documentation for more information + */ +typedef mcuxClEls_Status_t (*mcuxClEls_TransferToRegisterFunction_t)( + uint32_t volatile * pDestRegister, + uint8_t const * pSource, + size_t sourceLength, + void * pCallerData); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLELS_TYPES_H_ */ + +/** + * @} + * + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h new file mode 100644 index 000000000..06c8b8905 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/inc/mcuxClEls_mapping.h @@ -0,0 +1,549 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_mapping.h + * @brief Header providing mapping for legacy function/definition names (with CSS) + */ + + +#ifndef MCUXCLELS_MAPPING_H_ +#define MCUXCLELS_MAPPING_H_ + +/* Public definitions */ +/** + * MCUXCLCSS_CSS_((?:INTERRUPT_DISABLE|INTERRUPT_ENABLE|INTERRUPT_KEEP|INTERRUPT_SET|RESET_CLEAR|RESET_KEEP))(?!\w) + * --> + * MCUXCLELS_ELS_\1 + * + * MCUXCLCSS_((?:API|AEAD_AAD_BLOCK_SIZE|AEAD_ACPMOD_AADPROC|AEAD_ACPMOD_FINAL|AEAD_ACPMOD_INIT|AEAD_ACPMOD_MSGPROC|AEAD_CONTEXT_SIZE|AEAD_DECRYPT|AEAD_ENCRYPT|AEAD_EXTERN_KEY|AEAD_INTERN_KEY|AEAD_IV_BLOCK_SIZE|AEAD_LASTINIT_FALSE|AEAD_LASTINIT_TRUE|AEAD_STATE_IN_DISABLE|AEAD_STATE_IN_ENABLE|AEAD_STATE_OUT_ENABLE|AEAD_TAG_SIZE|CIPHERPARAM_ALGORITHM_AES_CBC|CIPHERPARAM_ALGORITHM_AES_CTR|CIPHERPARAM_ALGORITHM_AES_ECB|CIPHER_BLOCK_SIZE_AES|CIPHER_DECRYPT|CIPHER_ENCRYPT|CIPHER_EXTERNAL_KEY|CIPHER_INTERNAL_KEY|CIPHER_KEY_SIZE_AES_128|CIPHER_KEY_SIZE_AES_192|CIPHER_KEY_SIZE_AES_256|CIPHER_STATE_IN_DISABLE|CIPHER_STATE_IN_ENABLE|CIPHER_STATE_OUT_DISABLE|CIPHER_STATE_OUT_ENABLE|CKDF_ALGO_SP800108|CKDF_ALGO_SP80056C_EXPAND|CKDF_ALGO_SP80056C_EXTRACT|CKDF_DERIVATIONDATA_SIZE|CKDF_RTF_DERIV|CKDF_SP80056C_DERIVATIONDATA_SIZE_16|CKDF_SP80056C_DERIVATIONDATA_SIZE_32|CKDF_SYSTEM_MEMORY_DERIV|CMAC_EXTERNAL_KEY_DISABLE|CMAC_EXTERNAL_KEY_ENABLE|CMAC_FINALIZE_DISABLE|CMAC_FINALIZE_ENABLE|CMAC_INITIALIZE_DISABLE|CMAC_INITIALIZE_ENABLE|CMAC_KEY_SIZE_128|CMAC_KEY_SIZE_256|CMAC_OUT_SIZE))(?!\w) + * MCUXCLCSS_((?:CMD_CRC_CMD_ID_AUTH_CIPHER|CMD_CRC_CMD_ID_CHAL_RESP_GEN|CMD_CRC_CMD_ID_CIPHER|CMD_CRC_CMD_ID_CKDF|CMD_CRC_CMD_ID_CMAC|CMD_CRC_CMD_ID_DRBG_TEST|CMD_CRC_CMD_ID_DTRNG_CFG_LOAD|CMD_CRC_CMD_ID_DTRNG_EVAL|CMD_CRC_CMD_ID_ECKXH|CMD_CRC_CMD_ID_ECSIGN|CMD_CRC_CMD_ID_ECVFY|CMD_CRC_CMD_ID_GDET_CFG_LOAD|CMD_CRC_CMD_ID_GDET_TRIM|CMD_CRC_CMD_ID_HASH|CMD_CRC_CMD_ID_HKDF|CMD_CRC_CMD_ID_HMAC|CMD_CRC_CMD_ID_KDELETE|CMD_CRC_CMD_ID_KEYGEN|CMD_CRC_CMD_ID_KEYIN|CMD_CRC_CMD_ID_KEYOUT|CMD_CRC_CMD_ID_KEYPROV|CMD_CRC_CMD_ID_RND_REQ|CMD_CRC_CMD_ID_TLS|CMD_CRC_DISABLE|CMD_CRC_ENABLE|CMD_CRC_INITIAL_VALUE|CMD_CRC_POLYNOMIAL|CMD_CRC_REFERENCE_INIT|CMD_CRC_REFERENCE_RESET|CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE|CMD_CRC_REFERENCE_UPDATE_AEAD_INIT|CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD|CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA|CMD_CRC_REFERENCE_UPDATE_CIPHER|CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND|CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT|CMD_CRC_REFERENCE_UPDATE_CMAC))(?!\w) + * MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE|CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT|CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN|CMD_CRC_REFERENCE_UPDATE_ECCSIGN|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY|CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG|CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM|CMD_CRC_REFERENCE_UPDATE_HASH|CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869|CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C|CMD_CRC_REFERENCE_UPDATE_HMAC|CMD_CRC_REFERENCE_UPDATE_KEYDELETE|CMD_CRC_REFERENCE_UPDATE_KEYEXPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORT|CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK|CMD_CRC_REFERENCE_UPDATE_KEYPROVISION|CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM|CMD_CRC_REFERENCE_UPDATE_PRNG_INIT|CMD_CRC_REFERENCE_UPDATE_RESPGEN|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT|CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE|CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE))(?!\w) + * MCUXCLCSS_((?:CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD|CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY|CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY|CMD_CRC_RESET|CMD_CRC_VALUE_DISABLE|CMD_CRC_VALUE_ENABLE|CMD_CRC_VALUE_RESET|DMA_READBACK_PROTECTION_TOKEN|ECC_EXTKEY_EXTERNAL|ECC_EXTKEY_INTERNAL|ECC_GEN_PUBLIC_KEY|ECC_HASHED|ECC_INCLUDE_RANDOM_DATA|ECC_NOT_HASHED|ECC_NO_RANDOM_DATA|ECC_NO_RTF|ECC_OUTPUTKEY_DETERMINISTIC|ECC_OUTPUTKEY_KEYEXCHANGE|ECC_OUTPUTKEY_RANDOM|ECC_OUTPUTKEY_SIGN|ECC_PUBLICKEY_SIGN_DISABLE|ECC_PUBLICKEY_SIGN_ENABLE|ECC_PUBLICKEY_SIZE|ECC_REVERSEFETCH_DISABLE|ECC_REVERSEFETCH_ENABLE|ECC_RTF|ECC_SIGNATURE_R_SIZE|ECC_SIGNATURE_SIZE|ECC_SKIP_PUBLIC_KEY|ECC_VALUE_HASHED|ECC_VALUE_NOT_HASHED|ECC_VALUE_NO_RTF|ECC_VALUE_RTF|ERROR_FLAGS_CLEAR|ERROR_FLAGS_KEEP|GLITCHDETECTOR_CFG_SIZE|GLITCHDETECTOR_TRIM_SIZE|GLITCH_DETECTOR_INTERRUPT_DISABLE|GLITCH_DETECTOR_INTERRUPT_ENABLE|GLITCH_DETECTOR_NEG_KEEP))(?!\w) + * MCUXCLCSS_((?:GLITCH_DETECTOR_NEG_SET|GLITCH_DETECTOR_POS_KEEP|GLITCH_DETECTOR_POS_SET|GLITCH_DETECTOR_RESET_CLEAR|GLITCH_DETECTOR_RESET_KEEP|HASH_BLOCK_SIZE_SHA_224|HASH_BLOCK_SIZE_SHA_256|HASH_BLOCK_SIZE_SHA_384|HASH_BLOCK_SIZE_SHA_512|HASH_INIT_DISABLE|HASH_INIT_ENABLE|HASH_LOAD_DISABLE|HASH_LOAD_ENABLE|HASH_MODE_SHA_224|HASH_MODE_SHA_256|HASH_MODE_SHA_384|HASH_MODE_SHA_512|HASH_OUTPUT_DISABLE|HASH_OUTPUT_ENABLE|HASH_OUTPUT_SIZE_SHA_224|HASH_OUTPUT_SIZE_SHA_256|HASH_OUTPUT_SIZE_SHA_384|HASH_OUTPUT_SIZE_SHA_512|HASH_RTF_OUTPUT_DISABLE|HASH_RTF_OUTPUT_ENABLE|HASH_RTF_OUTPUT_SIZE|HASH_RTF_UPDATE_DISABLE|HASH_RTF_UPDATE_ENABLE|HASH_STATE_SIZE_SHA_224|HASH_STATE_SIZE_SHA_256|HASH_STATE_SIZE_SHA_384|HASH_STATE_SIZE_SHA_512|HASH_VALUE_MODE_SHA_224|HASH_VALUE_MODE_SHA_256|HASH_VALUE_MODE_SHA_384|HASH_VALUE_MODE_SHA_512|HKDF_ALGO_RFC5869|HKDF_ALGO_SP80056C|HKDF_RFC5869_DERIVATIONDATA_SIZE|HKDF_SP80056C_TARGETKEY_SIZE|HKDF_VALUE_MEMORY_DERIV|HKDF_VALUE_RTF_DERIV|HMAC_EXTERNAL_KEY_DISABLE|HMAC_EXTERNAL_KEY_ENABLE|HMAC_OUTPUT_SIZE|HMAC_PADDED_KEY_SIZE|HW_VERSION))(?!\w) + * MCUXCLCSS_((?:KEYGEN_VALUE_DETERMINISTIC|KEYGEN_VALUE_GEN_PUB_KEY|KEYGEN_VALUE_NO_PUB_KEY|KEYGEN_VALUE_NO_RANDOM_DATA|KEYGEN_VALUE_RANDOM|KEYGEN_VALUE_SIGN_PUBLICKEY|KEYGEN_VALUE_TYPE_KEYEXCHANGE|KEYGEN_VALUE_TYPE_SIGN|KEYGEN_VALUE_USE_RANDOM_DATA|KEYIMPORT_KFMT_PBK|KEYIMPORT_KFMT_PUF|KEYIMPORT_KFMT_RFC3394|KEYIMPORT_KFMT_UDF|KEYIMPORT_REVERSEFETCH_DISABLE|KEYIMPORT_REVERSEFETCH_ENABLE|KEYIMPORT_VALUE_KFMT_PBK|KEYIMPORT_VALUE_KFMT_PUF|KEYIMPORT_VALUE_KFMT_RFC3394|KEYIMPORT_VALUE_KFMT_UDF|KEYPROPERTY_ACTIVE_FALSE|KEYPROPERTY_ACTIVE_TRUE|KEYPROPERTY_AES_FALSE|KEYPROPERTY_AES_TRUE|KEYPROPERTY_BASE_SLOT|KEYPROPERTY_CKDF_FALSE|KEYPROPERTY_CKDF_TRUE|KEYPROPERTY_CMAC_FALSE|KEYPROPERTY_CMAC_TRUE|KEYPROPERTY_DEVICE_UNIQUE_FALSE|KEYPROPERTY_DEVICE_UNIQUE_TRUE|KEYPROPERTY_ECC_DH_PRIVATE_FALSE|KEYPROPERTY_ECC_DH_PRIVATE_TRUE|KEYPROPERTY_ECC_FALSE|KEYPROPERTY_ECC_TRUE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE|KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE|KEYPROPERTY_HKDF_FALSE|KEYPROPERTY_HKDF_TRUE|KEYPROPERTY_HMAC_FALSE|KEYPROPERTY_HMAC_TRUE|KEYPROPERTY_HW_OUT_FALSE|KEYPROPERTY_HW_OUT_SLOT_FALSE))(?!\w) + * MCUXCLCSS_((?:KEYPROPERTY_HW_OUT_SLOT_TRUE|KEYPROPERTY_HW_OUT_TRUE|KEYPROPERTY_INPUT_FOR_ECC_FALSE|KEYPROPERTY_INPUT_FOR_ECC_TRUE|KEYPROPERTY_KEY_SIZE_128|KEYPROPERTY_KEY_SIZE_256|KEYPROPERTY_KEY_SIZE_512|KEYPROPERTY_KSK_FALSE|KEYPROPERTY_KSK_TRUE|KEYPROPERTY_KUOK_FALSE|KEYPROPERTY_KUOK_TRUE|KEYPROPERTY_KWK_FALSE|KEYPROPERTY_KWK_TRUE|KEYPROPERTY_PRIVILEGED_FALSE|KEYPROPERTY_PRIVILEGED_TRUE|KEYPROPERTY_PUK_FALSE|KEYPROPERTY_PUK_TRUE|KEYPROPERTY_RETENTION_SLOT_FALSE|KEYPROPERTY_RETENTION_SLOT_TRUE|KEYPROPERTY_RTF_FALSE|KEYPROPERTY_RTF_TRUE|KEYPROPERTY_SECOND_SLOT|KEYPROPERTY_SECURE_FALSE|KEYPROPERTY_SECURE_TRUE|KEYPROPERTY_TECDH_FALSE|KEYPROPERTY_TECDH_TRUE|KEYPROPERTY_TLS_MASTER_SECRET_FALSE|KEYPROPERTY_TLS_MASTER_SECRET_TRUE|KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE|KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE|KEYPROPERTY_VALUE_ACTIVE|KEYPROPERTY_VALUE_AES|KEYPROPERTY_VALUE_BASE_SLOT|KEYPROPERTY_VALUE_CKDF|KEYPROPERTY_VALUE_CMAC|KEYPROPERTY_VALUE_DUK|KEYPROPERTY_VALUE_ECDH|KEYPROPERTY_VALUE_ECSGN|KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT|KEYPROPERTY_VALUE_HKDF|KEYPROPERTY_VALUE_HMAC))(?!\w) + * MCUXCLCSS_((?:KEYPROPERTY_VALUE_HW_OUT|KEYPROPERTY_VALUE_HW_OUT_SLOT|KEYPROPERTY_VALUE_KEY_SIZE_128|KEYPROPERTY_VALUE_KEY_SIZE_256|KEYPROPERTY_VALUE_KEY_SIZE_512|KEYPROPERTY_VALUE_KGSRC|KEYPROPERTY_VALUE_KSK|KEYPROPERTY_VALUE_KUOK|KEYPROPERTY_VALUE_KWK|KEYPROPERTY_VALUE_NOTPRIVILEGED|KEYPROPERTY_VALUE_NOTSECURE|KEYPROPERTY_VALUE_PRIVILEGED|KEYPROPERTY_VALUE_PUK|KEYPROPERTY_VALUE_RETENTION_SLOT|KEYPROPERTY_VALUE_RTF|KEYPROPERTY_VALUE_SECURE|KEYPROPERTY_VALUE_TECDH|KEYPROPERTY_VALUE_TLS_MASTER_SECRET|KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET|KEYPROPERTY_VALUE_WRPOK|KEYPROPERTY_WRAP_FALSE|KEYPROPERTY_WRAP_TRUE|KEYPROV_DUK_UPDATE_DISABLE|KEYPROV_DUK_UPDATE_ENABLE|KEYPROV_KEYSHARE_TABLE_SIZE|KEYPROV_KEY_PART_1_SIZE|KEYPROV_NOIC_DISABLE|KEYPROV_NOIC_ENABLE|KEYPROV_TESTERSHARE_SIZE|KEYPROV_VALUE_NOIC|KEY_SLOTS|MASTER_UNLOCK_ANY|RESET_CANCEL|RESET_DO_NOT_CANCEL|RESP_GEN_AVAILABLE_SLOT_0|RESP_GEN_AVAILABLE_SLOT_1|RESP_GEN_AVAILABLE_SLOT_2|RESP_GEN_SLOTS|RFC3394_CONTAINER_SIZE_128|RFC3394_CONTAINER_SIZE_256|RFC3394_CONTAINER_SIZE_P256|RFC3394_OVERHEAD|RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE))(?!\w) + * MCUXCLCSS_((?:RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE|RNG_DRBG_TEST_MODE_AES_CTR|RNG_DRBG_TEST_MODE_AES_ECB|RNG_DRBG_TEST_MODE_EXTRACT|RNG_DRBG_TEST_MODE_INSTANTIATE|RNG_DTRNG_CONFIG_SIZE|RNG_DTRNG_EVAL_CONFIG_SIZE|RNG_DTRNG_EVAL_RESULT_SIZE|RNG_RAW_ENTROPY_SIZE|RNG_RND_REQ_PRND_INIT|RNG_RND_REQ_RND_RAW|STATUS_DRBGENTLVL_HIGH|STATUS_DRBGENTLVL_LOW|STATUS_DRBGENTLVL_NONE|STATUS_ECDSAVFY_ERROR|STATUS_ECDSAVFY_FAIL|STATUS_ECDSAVFY_NORUN|STATUS_ECDSAVFY_OK|STATUS_HW_ALGORITHM|STATUS_HW_BUS|STATUS_HW_DTRNG|STATUS_HW_FAULT|STATUS_HW_INTEGRITY|STATUS_HW_OPERATIONAL|STATUS_HW_PRNG|STATUS_IS_HW_ERROR|STATUS_IS_SW_ERROR|STATUS_OK|STATUS_OK_WAIT|STATUS_PPROT_PRIVILEGED_NONSECURE|STATUS_PPROT_PRIVILEGED_SECURE|STATUS_PPROT_UNPRIVILEGED_NONSECURE|STATUS_PPROT_UNPRIVILEGED_SECURE|STATUS_SW_CANNOT_INTERRUPT|STATUS_SW_COMPARISON_FAILED|STATUS_SW_COUNTER_EXPIRED|STATUS_SW_FAULT|STATUS_SW_INVALID_PARAM|STATUS_SW_INVALID_STATE|STATUS_SW_LOCKING_FAILED|STATUS_SW_STATUS_LOCKED|TLS_DERIVATIONDATA_SIZE|TLS_FINALIZE|TLS_INIT|TLS_RANDOM_SIZE))(?!\w) + * --> + * MCUXCLELS_\1 + */ +#define MCUXCLCSS_API MCUXCLELS_API +#define MCUXCLCSS_AEAD_AAD_BLOCK_SIZE MCUXCLELS_AEAD_AAD_BLOCK_SIZE +#define MCUXCLCSS_AEAD_ACPMOD_AADPROC MCUXCLELS_AEAD_ACPMOD_AADPROC +#define MCUXCLCSS_AEAD_ACPMOD_FINAL MCUXCLELS_AEAD_ACPMOD_FINAL +#define MCUXCLCSS_AEAD_ACPMOD_INIT MCUXCLELS_AEAD_ACPMOD_INIT +#define MCUXCLCSS_AEAD_ACPMOD_MSGPROC MCUXCLELS_AEAD_ACPMOD_MSGPROC +#define MCUXCLCSS_AEAD_CONTEXT_SIZE MCUXCLELS_AEAD_CONTEXT_SIZE +#define MCUXCLCSS_AEAD_DECRYPT MCUXCLELS_AEAD_DECRYPT +#define MCUXCLCSS_AEAD_ENCRYPT MCUXCLELS_AEAD_ENCRYPT +#define MCUXCLCSS_AEAD_EXTERN_KEY MCUXCLELS_AEAD_EXTERN_KEY +#define MCUXCLCSS_AEAD_INTERN_KEY MCUXCLELS_AEAD_INTERN_KEY +#define MCUXCLCSS_AEAD_IV_BLOCK_SIZE MCUXCLELS_AEAD_IV_BLOCK_SIZE +#define MCUXCLCSS_AEAD_LASTINIT_FALSE MCUXCLELS_AEAD_LASTINIT_FALSE +#define MCUXCLCSS_AEAD_LASTINIT_TRUE MCUXCLELS_AEAD_LASTINIT_TRUE +#define MCUXCLCSS_AEAD_STATE_IN_DISABLE MCUXCLELS_AEAD_STATE_IN_DISABLE +#define MCUXCLCSS_AEAD_STATE_IN_ENABLE MCUXCLELS_AEAD_STATE_IN_ENABLE +#define MCUXCLCSS_AEAD_STATE_OUT_ENABLE MCUXCLELS_AEAD_STATE_OUT_ENABLE +#define MCUXCLCSS_AEAD_TAG_SIZE MCUXCLELS_AEAD_TAG_SIZE +#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CBC MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CBC +#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_CTR MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR +#define MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB +#define MCUXCLCSS_CIPHER_BLOCK_SIZE_AES MCUXCLELS_CIPHER_BLOCK_SIZE_AES +#define MCUXCLCSS_CIPHER_DECRYPT MCUXCLELS_CIPHER_DECRYPT +#define MCUXCLCSS_CIPHER_ENCRYPT MCUXCLELS_CIPHER_ENCRYPT +#define MCUXCLCSS_CIPHER_EXTERNAL_KEY MCUXCLELS_CIPHER_EXTERNAL_KEY +#define MCUXCLCSS_CIPHER_INTERNAL_KEY MCUXCLELS_CIPHER_INTERNAL_KEY +#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_128 MCUXCLELS_CIPHER_KEY_SIZE_AES_128 +#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_192 MCUXCLELS_CIPHER_KEY_SIZE_AES_192 +#define MCUXCLCSS_CIPHER_KEY_SIZE_AES_256 MCUXCLELS_CIPHER_KEY_SIZE_AES_256 +#define MCUXCLCSS_CIPHER_STATE_IN_DISABLE MCUXCLELS_CIPHER_STATE_IN_DISABLE +#define MCUXCLCSS_CIPHER_STATE_IN_ENABLE MCUXCLELS_CIPHER_STATE_IN_ENABLE +#define MCUXCLCSS_CIPHER_STATE_OUT_DISABLE MCUXCLELS_CIPHER_STATE_OUT_DISABLE +#define MCUXCLCSS_CIPHER_STATE_OUT_ENABLE MCUXCLELS_CIPHER_STATE_OUT_ENABLE +#define MCUXCLCSS_CKDF_ALGO_SP800108 MCUXCLELS_CKDF_ALGO_SP800108 +#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXPAND MCUXCLELS_CKDF_ALGO_SP80056C_EXPAND +#define MCUXCLCSS_CKDF_ALGO_SP80056C_EXTRACT MCUXCLELS_CKDF_ALGO_SP80056C_EXTRACT +#define MCUXCLCSS_CKDF_DERIVATIONDATA_SIZE MCUXCLELS_CKDF_DERIVATIONDATA_SIZE +#define MCUXCLCSS_HKDF_RTF_DERIV MCUXCLELS_HKDF_RTF_DERIV +#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16 MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_16 +#define MCUXCLCSS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32 MCUXCLELS_CKDF_SP80056C_DERIVATIONDATA_SIZE_32 +#define MCUXCLCSS_HKDF_SYSTEM_MEMORY_DERIV MCUXCLELS_HKDF_SYSTEM_MEMORY_DERIV +#define MCUXCLCSS_CMAC_EXTERNAL_KEY_DISABLE MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE +#define MCUXCLCSS_CMAC_EXTERNAL_KEY_ENABLE MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE +#define MCUXCLCSS_CMAC_FINALIZE_DISABLE MCUXCLELS_CMAC_FINALIZE_DISABLE +#define MCUXCLCSS_CMAC_FINALIZE_ENABLE MCUXCLELS_CMAC_FINALIZE_ENABLE +#define MCUXCLCSS_CMAC_INITIALIZE_DISABLE MCUXCLELS_CMAC_INITIALIZE_DISABLE +#define MCUXCLCSS_CMAC_INITIALIZE_ENABLE MCUXCLELS_CMAC_INITIALIZE_ENABLE +#define MCUXCLCSS_CMAC_KEY_SIZE_128 MCUXCLELS_CMAC_KEY_SIZE_128 +#define MCUXCLCSS_CMAC_KEY_SIZE_256 MCUXCLELS_CMAC_KEY_SIZE_256 +#define MCUXCLCSS_CMAC_OUT_SIZE MCUXCLELS_CMAC_OUT_SIZE +#define MCUXCLCSS_CMD_CRC_CMD_ID_AUTH_CIPHER MCUXCLELS_CMD_CRC_CMD_ID_AUTH_CIPHER +#define MCUXCLCSS_CMD_CRC_CMD_ID_CHAL_RESP_GEN MCUXCLELS_CMD_CRC_CMD_ID_CHAL_RESP_GEN +#define MCUXCLCSS_CMD_CRC_CMD_ID_CIPHER MCUXCLELS_CMD_CRC_CMD_ID_CIPHER +#define MCUXCLCSS_CMD_CRC_CMD_ID_CKDF MCUXCLELS_CMD_CRC_CMD_ID_CKDF +#define MCUXCLCSS_CMD_CRC_CMD_ID_CMAC MCUXCLELS_CMD_CRC_CMD_ID_CMAC +#define MCUXCLCSS_CMD_CRC_CMD_ID_DRBG_TEST MCUXCLELS_CMD_CRC_CMD_ID_DRBG_TEST +#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_CFG_LOAD +#define MCUXCLCSS_CMD_CRC_CMD_ID_DTRNG_EVAL MCUXCLELS_CMD_CRC_CMD_ID_DTRNG_EVAL +#define MCUXCLCSS_CMD_CRC_CMD_ID_ECKXH MCUXCLELS_CMD_CRC_CMD_ID_ECKXH +#define MCUXCLCSS_CMD_CRC_CMD_ID_ECSIGN MCUXCLELS_CMD_CRC_CMD_ID_ECSIGN +#define MCUXCLCSS_CMD_CRC_CMD_ID_ECVFY MCUXCLELS_CMD_CRC_CMD_ID_ECVFY +#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_CFG_LOAD MCUXCLELS_CMD_CRC_CMD_ID_GDET_CFG_LOAD +#define MCUXCLCSS_CMD_CRC_CMD_ID_GDET_TRIM MCUXCLELS_CMD_CRC_CMD_ID_GDET_TRIM +#define MCUXCLCSS_CMD_CRC_CMD_ID_HASH MCUXCLELS_CMD_CRC_CMD_ID_HASH +#define MCUXCLCSS_CMD_CRC_CMD_ID_HKDF MCUXCLELS_CMD_CRC_CMD_ID_HKDF +#define MCUXCLCSS_CMD_CRC_CMD_ID_HMAC MCUXCLELS_CMD_CRC_CMD_ID_HMAC +#define MCUXCLCSS_CMD_CRC_CMD_ID_KDELETE MCUXCLELS_CMD_CRC_CMD_ID_KDELETE +#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYGEN MCUXCLELS_CMD_CRC_CMD_ID_KEYGEN +#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYIN MCUXCLELS_CMD_CRC_CMD_ID_KEYIN +#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYOUT MCUXCLELS_CMD_CRC_CMD_ID_KEYOUT +#define MCUXCLCSS_CMD_CRC_CMD_ID_KEYPROV MCUXCLELS_CMD_CRC_CMD_ID_KEYPROV +#define MCUXCLCSS_CMD_CRC_CMD_ID_RND_REQ MCUXCLELS_CMD_CRC_CMD_ID_RND_REQ +#define MCUXCLCSS_CMD_CRC_CMD_ID_TLS MCUXCLELS_CMD_CRC_CMD_ID_TLS +#define MCUXCLCSS_CMD_CRC_DISABLE MCUXCLELS_CMD_CRC_DISABLE +#define MCUXCLCSS_CMD_CRC_ENABLE MCUXCLELS_CMD_CRC_ENABLE +#define MCUXCLCSS_CMD_CRC_INITIAL_VALUE MCUXCLELS_CMD_CRC_INITIAL_VALUE +#define MCUXCLCSS_CMD_CRC_POLYNOMIAL MCUXCLELS_CMD_CRC_POLYNOMIAL +#define MCUXCLCSS_CMD_CRC_REFERENCE_INIT MCUXCLELS_CMD_CRC_REFERENCE_INIT +#define MCUXCLCSS_CMD_CRC_REFERENCE_RESET MCUXCLELS_CMD_CRC_REFERENCE_RESET +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_FINALIZE +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_INIT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_PARTIALINIT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEAAD +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_AEAD_UPDATEDATA +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CIPHER MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CIPHER +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108 MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP800108 +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXPAND +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CKDF_SP80056C_EXTRACT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_CMAC MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_CMAC +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGE +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYEXCHANGEINT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCKEYGEN +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCSIGN +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFY +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_ECCVERFIFYINT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_LOADCONFIG +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_GLITCHDETECTOR_TRIM +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HASH MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HASH +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869 MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_RFC5869 +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HKDF_SP80056C +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_HMAC MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_HMAC +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYDELETE +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYEXPORT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYIMPORTPUK +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISION +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_KEYPROVISIONROM +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_PRNG_INIT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RESPGEN MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RESPGEN +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUEST +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGREQUESTRAW +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESCTR +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTAESECB +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTEXTRACT +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DRBGTESTINSTANTIATE +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGEVALUATE +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_RNG_DTRNG_CONFIGLOAD +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATEMASTERKEYFROMPREMASTERKEY +#define MCUXCLCSS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY MCUXCLELS_CMD_CRC_REFERENCE_UPDATE_TLSGENERATESESSIONKEYSFROMMASTERKEY +#define MCUXCLCSS_CMD_CRC_RESET MCUXCLELS_CMD_CRC_RESET +#define MCUXCLCSS_CMD_CRC_VALUE_DISABLE MCUXCLELS_CMD_CRC_VALUE_DISABLE +#define MCUXCLCSS_CMD_CRC_VALUE_ENABLE MCUXCLELS_CMD_CRC_VALUE_ENABLE +#define MCUXCLCSS_CMD_CRC_VALUE_RESET MCUXCLELS_CMD_CRC_VALUE_RESET +#define MCUXCLCSS_CSS_INTERRUPT_DISABLE MCUXCLELS_ELS_INTERRUPT_DISABLE +#define MCUXCLCSS_CSS_INTERRUPT_ENABLE MCUXCLELS_ELS_INTERRUPT_ENABLE +#define MCUXCLCSS_CSS_INTERRUPT_KEEP MCUXCLELS_ELS_INTERRUPT_KEEP +#define MCUXCLCSS_CSS_INTERRUPT_SET MCUXCLELS_ELS_INTERRUPT_SET +#define MCUXCLCSS_CSS_RESET_CLEAR MCUXCLELS_ELS_RESET_CLEAR +#define MCUXCLCSS_CSS_RESET_KEEP MCUXCLELS_ELS_RESET_KEEP +#define MCUXCLCSS_DMA_READBACK_PROTECTION_TOKEN MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN +#define MCUXCLCSS_ECC_EXTKEY_EXTERNAL MCUXCLELS_ECC_EXTKEY_EXTERNAL +#define MCUXCLCSS_ECC_EXTKEY_INTERNAL MCUXCLELS_ECC_EXTKEY_INTERNAL +#define MCUXCLCSS_ECC_GEN_PUBLIC_KEY MCUXCLELS_ECC_GEN_PUBLIC_KEY +#define MCUXCLCSS_ECC_HASHED MCUXCLELS_ECC_HASHED +#define MCUXCLCSS_ECC_INCLUDE_RANDOM_DATA MCUXCLELS_ECC_INCLUDE_RANDOM_DATA +#define MCUXCLCSS_ECC_NOT_HASHED MCUXCLELS_ECC_NOT_HASHED +#define MCUXCLCSS_ECC_NO_RANDOM_DATA MCUXCLELS_ECC_NO_RANDOM_DATA +#define MCUXCLCSS_ECC_NO_RTF MCUXCLELS_ECC_NO_RTF +#define MCUXCLCSS_ECC_OUTPUTKEY_DETERMINISTIC MCUXCLELS_ECC_OUTPUTKEY_DETERMINISTIC +#define MCUXCLCSS_ECC_OUTPUTKEY_KEYEXCHANGE MCUXCLELS_ECC_OUTPUTKEY_KEYEXCHANGE +#define MCUXCLCSS_ECC_OUTPUTKEY_RANDOM MCUXCLELS_ECC_OUTPUTKEY_RANDOM +#define MCUXCLCSS_ECC_OUTPUTKEY_SIGN MCUXCLELS_ECC_OUTPUTKEY_SIGN +#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_DISABLE MCUXCLELS_ECC_PUBLICKEY_SIGN_DISABLE +#define MCUXCLCSS_ECC_PUBLICKEY_SIGN_ENABLE MCUXCLELS_ECC_PUBLICKEY_SIGN_ENABLE +#define MCUXCLCSS_ECC_PUBLICKEY_SIZE MCUXCLELS_ECC_PUBLICKEY_SIZE +#define MCUXCLCSS_ECC_REVERSEFETCH_DISABLE MCUXCLELS_ECC_REVERSEFETCH_DISABLE +#define MCUXCLCSS_ECC_REVERSEFETCH_ENABLE MCUXCLELS_ECC_REVERSEFETCH_ENABLE +#define MCUXCLCSS_ECC_RTF MCUXCLELS_ECC_RTF +#define MCUXCLCSS_ECC_SIGNATURE_R_SIZE MCUXCLELS_ECC_SIGNATURE_R_SIZE +#define MCUXCLCSS_ECC_SIGNATURE_SIZE MCUXCLELS_ECC_SIGNATURE_SIZE +#define MCUXCLCSS_ECC_SKIP_PUBLIC_KEY MCUXCLELS_ECC_SKIP_PUBLIC_KEY +#define MCUXCLCSS_ECC_VALUE_HASHED MCUXCLELS_ECC_VALUE_HASHED +#define MCUXCLCSS_ECC_VALUE_NOT_HASHED MCUXCLELS_ECC_VALUE_NOT_HASHED +#define MCUXCLCSS_ECC_VALUE_NO_RTF MCUXCLELS_ECC_VALUE_NO_RTF +#define MCUXCLCSS_ECC_VALUE_RTF MCUXCLELS_ECC_VALUE_RTF +#define MCUXCLCSS_ERROR_FLAGS_CLEAR MCUXCLELS_ERROR_FLAGS_CLEAR +#define MCUXCLCSS_ERROR_FLAGS_KEEP MCUXCLELS_ERROR_FLAGS_KEEP +#define MCUXCLCSS_GLITCHDETECTOR_CFG_SIZE MCUXCLELS_GLITCHDETECTOR_CFG_SIZE +#define MCUXCLCSS_GLITCHDETECTOR_TRIM_SIZE MCUXCLELS_GLITCHDETECTOR_TRIM_SIZE +#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_DISABLE MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_DISABLE +#define MCUXCLCSS_GLITCH_DETECTOR_INTERRUPT_ENABLE MCUXCLELS_GLITCH_DETECTOR_INTERRUPT_ENABLE +#define MCUXCLCSS_GLITCH_DETECTOR_NEG_KEEP MCUXCLELS_GLITCH_DETECTOR_NEG_KEEP +#define MCUXCLCSS_GLITCH_DETECTOR_NEG_SET MCUXCLELS_GLITCH_DETECTOR_NEG_SET +#define MCUXCLCSS_GLITCH_DETECTOR_POS_KEEP MCUXCLELS_GLITCH_DETECTOR_POS_KEEP +#define MCUXCLCSS_GLITCH_DETECTOR_POS_SET MCUXCLELS_GLITCH_DETECTOR_POS_SET +#define MCUXCLCSS_GLITCH_DETECTOR_RESET_CLEAR MCUXCLELS_GLITCH_DETECTOR_RESET_CLEAR +#define MCUXCLCSS_GLITCH_DETECTOR_RESET_KEEP MCUXCLELS_GLITCH_DETECTOR_RESET_KEEP +#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_224 MCUXCLELS_HASH_BLOCK_SIZE_SHA_224 +#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_256 MCUXCLELS_HASH_BLOCK_SIZE_SHA_256 +#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_384 MCUXCLELS_HASH_BLOCK_SIZE_SHA_384 +#define MCUXCLCSS_HASH_BLOCK_SIZE_SHA_512 MCUXCLELS_HASH_BLOCK_SIZE_SHA_512 +#define MCUXCLCSS_HASH_INIT_DISABLE MCUXCLELS_HASH_INIT_DISABLE +#define MCUXCLCSS_HASH_INIT_ENABLE MCUXCLELS_HASH_INIT_ENABLE +#define MCUXCLCSS_HASH_LOAD_DISABLE MCUXCLELS_HASH_LOAD_DISABLE +#define MCUXCLCSS_HASH_LOAD_ENABLE MCUXCLELS_HASH_LOAD_ENABLE +#define MCUXCLCSS_HASH_MODE_SHA_224 MCUXCLELS_HASH_MODE_SHA_224 +#define MCUXCLCSS_HASH_MODE_SHA_256 MCUXCLELS_HASH_MODE_SHA_256 +#define MCUXCLCSS_HASH_MODE_SHA_384 MCUXCLELS_HASH_MODE_SHA_384 +#define MCUXCLCSS_HASH_MODE_SHA_512 MCUXCLELS_HASH_MODE_SHA_512 +#define MCUXCLCSS_HASH_OUTPUT_DISABLE MCUXCLELS_HASH_OUTPUT_DISABLE +#define MCUXCLCSS_HASH_OUTPUT_ENABLE MCUXCLELS_HASH_OUTPUT_ENABLE +#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_224 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_224 +#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_256 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_256 +#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_384 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_384 +#define MCUXCLCSS_HASH_OUTPUT_SIZE_SHA_512 MCUXCLELS_HASH_OUTPUT_SIZE_SHA_512 +#define MCUXCLCSS_HASH_RTF_OUTPUT_DISABLE MCUXCLELS_HASH_RTF_OUTPUT_DISABLE +#define MCUXCLCSS_HASH_RTF_OUTPUT_ENABLE MCUXCLELS_HASH_RTF_OUTPUT_ENABLE +#define MCUXCLCSS_HASH_RTF_OUTPUT_SIZE MCUXCLELS_HASH_RTF_OUTPUT_SIZE +#define MCUXCLCSS_HASH_RTF_UPDATE_DISABLE MCUXCLELS_HASH_RTF_UPDATE_DISABLE +#define MCUXCLCSS_HASH_RTF_UPDATE_ENABLE MCUXCLELS_HASH_RTF_UPDATE_ENABLE +#define MCUXCLCSS_HASH_STATE_SIZE_SHA_224 MCUXCLELS_HASH_STATE_SIZE_SHA_224 +#define MCUXCLCSS_HASH_STATE_SIZE_SHA_256 MCUXCLELS_HASH_STATE_SIZE_SHA_256 +#define MCUXCLCSS_HASH_STATE_SIZE_SHA_384 MCUXCLELS_HASH_STATE_SIZE_SHA_384 +#define MCUXCLCSS_HASH_STATE_SIZE_SHA_512 MCUXCLELS_HASH_STATE_SIZE_SHA_512 +#define MCUXCLCSS_HASH_VALUE_MODE_SHA_224 MCUXCLELS_HASH_VALUE_MODE_SHA_224 +#define MCUXCLCSS_HASH_VALUE_MODE_SHA_256 MCUXCLELS_HASH_VALUE_MODE_SHA_256 +#define MCUXCLCSS_HASH_VALUE_MODE_SHA_384 MCUXCLELS_HASH_VALUE_MODE_SHA_384 +#define MCUXCLCSS_HASH_VALUE_MODE_SHA_512 MCUXCLELS_HASH_VALUE_MODE_SHA_512 +#define MCUXCLCSS_HKDF_ALGO_RFC5869 MCUXCLELS_HKDF_ALGO_RFC5869 +#define MCUXCLCSS_HKDF_ALGO_SP80056C MCUXCLELS_HKDF_ALGO_SP80056C +#define MCUXCLCSS_HKDF_RFC5869_DERIVATIONDATA_SIZE MCUXCLELS_HKDF_RFC5869_DERIVATIONDATA_SIZE +#define MCUXCLCSS_HKDF_SP80056C_TARGETKEY_SIZE MCUXCLELS_HKDF_SP80056C_TARGETKEY_SIZE +#define MCUXCLCSS_HKDF_VALUE_MEMORY_DERIV MCUXCLELS_HKDF_VALUE_MEMORY_DERIV +#define MCUXCLCSS_HKDF_VALUE_RTF_DERIV MCUXCLELS_HKDF_VALUE_RTF_DERIV +#define MCUXCLCSS_HMAC_EXTERNAL_KEY_DISABLE MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE +#define MCUXCLCSS_HMAC_EXTERNAL_KEY_ENABLE MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE +#define MCUXCLCSS_HMAC_OUTPUT_SIZE MCUXCLELS_HMAC_OUTPUT_SIZE +#define MCUXCLCSS_HMAC_PADDED_KEY_SIZE MCUXCLELS_HMAC_PADDED_KEY_SIZE +#define MCUXCLCSS_HW_VERSION MCUXCLELS_HW_VERSION +#define MCUXCLCSS_KEYGEN_VALUE_DETERMINISTIC MCUXCLELS_KEYGEN_VALUE_DETERMINISTIC +#define MCUXCLCSS_KEYGEN_VALUE_GEN_PUB_KEY MCUXCLELS_KEYGEN_VALUE_GEN_PUB_KEY +#define MCUXCLCSS_KEYGEN_VALUE_NO_PUB_KEY MCUXCLELS_KEYGEN_VALUE_NO_PUB_KEY +#define MCUXCLCSS_KEYGEN_VALUE_NO_RANDOM_DATA MCUXCLELS_KEYGEN_VALUE_NO_RANDOM_DATA +#define MCUXCLCSS_KEYGEN_VALUE_RANDOM MCUXCLELS_KEYGEN_VALUE_RANDOM +#define MCUXCLCSS_KEYGEN_VALUE_SIGN_PUBLICKEY MCUXCLELS_KEYGEN_VALUE_SIGN_PUBLICKEY +#define MCUXCLCSS_KEYGEN_VALUE_TYPE_KEYEXCHANGE MCUXCLELS_KEYGEN_VALUE_TYPE_KEYEXCHANGE +#define MCUXCLCSS_KEYGEN_VALUE_TYPE_SIGN MCUXCLELS_KEYGEN_VALUE_TYPE_SIGN +#define MCUXCLCSS_KEYGEN_VALUE_USE_RANDOM_DATA MCUXCLELS_KEYGEN_VALUE_USE_RANDOM_DATA +#define MCUXCLCSS_KEYIMPORT_KFMT_PBK MCUXCLELS_KEYIMPORT_KFMT_PBK +#define MCUXCLCSS_KEYIMPORT_KFMT_PUF MCUXCLELS_KEYIMPORT_KFMT_PUF +#define MCUXCLCSS_KEYIMPORT_KFMT_RFC3394 MCUXCLELS_KEYIMPORT_KFMT_RFC3394 +#define MCUXCLCSS_KEYIMPORT_KFMT_UDF MCUXCLELS_KEYIMPORT_KFMT_UDF +#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_DISABLE MCUXCLELS_KEYIMPORT_REVERSEFETCH_DISABLE +#define MCUXCLCSS_KEYIMPORT_REVERSEFETCH_ENABLE MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE +#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PBK MCUXCLELS_KEYIMPORT_VALUE_KFMT_PBK +#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_PUF MCUXCLELS_KEYIMPORT_VALUE_KFMT_PUF +#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_RFC3394 MCUXCLELS_KEYIMPORT_VALUE_KFMT_RFC3394 +#define MCUXCLCSS_KEYIMPORT_VALUE_KFMT_UDF MCUXCLELS_KEYIMPORT_VALUE_KFMT_UDF +#define MCUXCLCSS_KEYPROPERTY_ACTIVE_FALSE MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE +#define MCUXCLCSS_KEYPROPERTY_ACTIVE_TRUE MCUXCLELS_KEYPROPERTY_ACTIVE_TRUE +#define MCUXCLCSS_KEYPROPERTY_AES_FALSE MCUXCLELS_KEYPROPERTY_AES_FALSE +#define MCUXCLCSS_KEYPROPERTY_AES_TRUE MCUXCLELS_KEYPROPERTY_AES_TRUE +#define MCUXCLCSS_KEYPROPERTY_BASE_SLOT MCUXCLELS_KEYPROPERTY_BASE_SLOT +#define MCUXCLCSS_KEYPROPERTY_CKDF_FALSE MCUXCLELS_KEYPROPERTY_CKDF_FALSE +#define MCUXCLCSS_KEYPROPERTY_CKDF_TRUE MCUXCLELS_KEYPROPERTY_CKDF_TRUE +#define MCUXCLCSS_KEYPROPERTY_CMAC_FALSE MCUXCLELS_KEYPROPERTY_CMAC_FALSE +#define MCUXCLCSS_KEYPROPERTY_CMAC_TRUE MCUXCLELS_KEYPROPERTY_CMAC_TRUE +#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_FALSE MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_FALSE +#define MCUXCLCSS_KEYPROPERTY_DEVICE_UNIQUE_TRUE MCUXCLELS_KEYPROPERTY_DEVICE_UNIQUE_TRUE +#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_FALSE +#define MCUXCLCSS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE MCUXCLELS_KEYPROPERTY_ECC_DH_PRIVATE_TRUE +#define MCUXCLCSS_KEYPROPERTY_ECC_FALSE MCUXCLELS_KEYPROPERTY_ECC_FALSE +#define MCUXCLCSS_KEYPROPERTY_ECC_TRUE MCUXCLELS_KEYPROPERTY_ECC_TRUE +#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_FALSE +#define MCUXCLCSS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE MCUXCLELS_KEYPROPERTY_GENERAL_PURPOSE_SLOT_TRUE +#define MCUXCLCSS_KEYPROPERTY_HKDF_FALSE MCUXCLELS_KEYPROPERTY_HKDF_FALSE +#define MCUXCLCSS_KEYPROPERTY_HKDF_TRUE MCUXCLELS_KEYPROPERTY_HKDF_TRUE +#define MCUXCLCSS_KEYPROPERTY_HMAC_FALSE MCUXCLELS_KEYPROPERTY_HMAC_FALSE +#define MCUXCLCSS_KEYPROPERTY_HMAC_TRUE MCUXCLELS_KEYPROPERTY_HMAC_TRUE +#define MCUXCLCSS_KEYPROPERTY_HW_OUT_FALSE MCUXCLELS_KEYPROPERTY_HW_OUT_FALSE +#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_FALSE MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_FALSE +#define MCUXCLCSS_KEYPROPERTY_HW_OUT_SLOT_TRUE MCUXCLELS_KEYPROPERTY_HW_OUT_SLOT_TRUE +#define MCUXCLCSS_KEYPROPERTY_HW_OUT_TRUE MCUXCLELS_KEYPROPERTY_HW_OUT_TRUE +#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_FALSE MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_FALSE +#define MCUXCLCSS_KEYPROPERTY_INPUT_FOR_ECC_TRUE MCUXCLELS_KEYPROPERTY_INPUT_FOR_ECC_TRUE +#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_128 MCUXCLELS_KEYPROPERTY_KEY_SIZE_128 +#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_256 MCUXCLELS_KEYPROPERTY_KEY_SIZE_256 +#define MCUXCLCSS_KEYPROPERTY_KEY_SIZE_512 MCUXCLELS_KEYPROPERTY_KEY_SIZE_512 +#define MCUXCLCSS_KEYPROPERTY_KSK_FALSE MCUXCLELS_KEYPROPERTY_KSK_FALSE +#define MCUXCLCSS_KEYPROPERTY_KSK_TRUE MCUXCLELS_KEYPROPERTY_KSK_TRUE +#define MCUXCLCSS_KEYPROPERTY_KUOK_FALSE MCUXCLELS_KEYPROPERTY_KUOK_FALSE +#define MCUXCLCSS_KEYPROPERTY_KUOK_TRUE MCUXCLELS_KEYPROPERTY_KUOK_TRUE +#define MCUXCLCSS_KEYPROPERTY_KWK_FALSE MCUXCLELS_KEYPROPERTY_KWK_FALSE +#define MCUXCLCSS_KEYPROPERTY_KWK_TRUE MCUXCLELS_KEYPROPERTY_KWK_TRUE +#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_FALSE MCUXCLELS_KEYPROPERTY_PRIVILEGED_FALSE +#define MCUXCLCSS_KEYPROPERTY_PRIVILEGED_TRUE MCUXCLELS_KEYPROPERTY_PRIVILEGED_TRUE +#define MCUXCLCSS_KEYPROPERTY_PUK_FALSE MCUXCLELS_KEYPROPERTY_PUK_FALSE +#define MCUXCLCSS_KEYPROPERTY_PUK_TRUE MCUXCLELS_KEYPROPERTY_PUK_TRUE +#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_FALSE MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_FALSE +#define MCUXCLCSS_KEYPROPERTY_RETENTION_SLOT_TRUE MCUXCLELS_KEYPROPERTY_RETENTION_SLOT_TRUE +#define MCUXCLCSS_KEYPROPERTY_RTF_FALSE MCUXCLELS_KEYPROPERTY_RTF_FALSE +#define MCUXCLCSS_KEYPROPERTY_RTF_TRUE MCUXCLELS_KEYPROPERTY_RTF_TRUE +#define MCUXCLCSS_KEYPROPERTY_SECOND_SLOT MCUXCLELS_KEYPROPERTY_SECOND_SLOT +#define MCUXCLCSS_KEYPROPERTY_SECURE_FALSE MCUXCLELS_KEYPROPERTY_SECURE_FALSE +#define MCUXCLCSS_KEYPROPERTY_SECURE_TRUE MCUXCLELS_KEYPROPERTY_SECURE_TRUE +#define MCUXCLCSS_KEYPROPERTY_TECDH_FALSE MCUXCLELS_KEYPROPERTY_TECDH_FALSE +#define MCUXCLCSS_KEYPROPERTY_TECDH_TRUE MCUXCLELS_KEYPROPERTY_TECDH_TRUE +#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_FALSE +#define MCUXCLCSS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE MCUXCLELS_KEYPROPERTY_TLS_MASTER_SECRET_TRUE +#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_FALSE +#define MCUXCLCSS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE MCUXCLELS_KEYPROPERTY_TLS_PREMASTER_SECRET_TRUE +#define MCUXCLCSS_KEYPROPERTY_VALUE_ACTIVE MCUXCLELS_KEYPROPERTY_VALUE_ACTIVE +#define MCUXCLCSS_KEYPROPERTY_VALUE_AES MCUXCLELS_KEYPROPERTY_VALUE_AES +#define MCUXCLCSS_KEYPROPERTY_VALUE_BASE_SLOT MCUXCLELS_KEYPROPERTY_VALUE_BASE_SLOT +#define MCUXCLCSS_KEYPROPERTY_VALUE_CKDF MCUXCLELS_KEYPROPERTY_VALUE_CKDF +#define MCUXCLCSS_KEYPROPERTY_VALUE_CMAC MCUXCLELS_KEYPROPERTY_VALUE_CMAC +#define MCUXCLCSS_KEYPROPERTY_VALUE_DUK MCUXCLELS_KEYPROPERTY_VALUE_DUK +#define MCUXCLCSS_KEYPROPERTY_VALUE_ECDH MCUXCLELS_KEYPROPERTY_VALUE_ECDH +#define MCUXCLCSS_KEYPROPERTY_VALUE_ECSGN MCUXCLELS_KEYPROPERTY_VALUE_ECSGN +#define MCUXCLCSS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT MCUXCLELS_KEYPROPERTY_VALUE_GENERAL_PURPOSE_SLOT +#define MCUXCLCSS_KEYPROPERTY_VALUE_HKDF MCUXCLELS_KEYPROPERTY_VALUE_HKDF +#define MCUXCLCSS_KEYPROPERTY_VALUE_HMAC MCUXCLELS_KEYPROPERTY_VALUE_HMAC +#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT +#define MCUXCLCSS_KEYPROPERTY_VALUE_HW_OUT_SLOT MCUXCLELS_KEYPROPERTY_VALUE_HW_OUT_SLOT +#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_128 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_128 +#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_256 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_256 +#define MCUXCLCSS_KEYPROPERTY_VALUE_KEY_SIZE_512 MCUXCLELS_KEYPROPERTY_VALUE_KEY_SIZE_512 +#define MCUXCLCSS_KEYPROPERTY_VALUE_KGSRC MCUXCLELS_KEYPROPERTY_VALUE_KGSRC +#define MCUXCLCSS_KEYPROPERTY_VALUE_KSK MCUXCLELS_KEYPROPERTY_VALUE_KSK +#define MCUXCLCSS_KEYPROPERTY_VALUE_KUOK MCUXCLELS_KEYPROPERTY_VALUE_KUOK +#define MCUXCLCSS_KEYPROPERTY_VALUE_KWK MCUXCLELS_KEYPROPERTY_VALUE_KWK +#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTPRIVILEGED MCUXCLELS_KEYPROPERTY_VALUE_NOTPRIVILEGED +#define MCUXCLCSS_KEYPROPERTY_VALUE_NOTSECURE MCUXCLELS_KEYPROPERTY_VALUE_NOTSECURE +#define MCUXCLCSS_KEYPROPERTY_VALUE_PRIVILEGED MCUXCLELS_KEYPROPERTY_VALUE_PRIVILEGED +#define MCUXCLCSS_KEYPROPERTY_VALUE_PUK MCUXCLELS_KEYPROPERTY_VALUE_PUK +#define MCUXCLCSS_KEYPROPERTY_VALUE_RETENTION_SLOT MCUXCLELS_KEYPROPERTY_VALUE_RETENTION_SLOT +#define MCUXCLCSS_KEYPROPERTY_VALUE_RTF MCUXCLELS_KEYPROPERTY_VALUE_RTF +#define MCUXCLCSS_KEYPROPERTY_VALUE_SECURE MCUXCLELS_KEYPROPERTY_VALUE_SECURE +#define MCUXCLCSS_KEYPROPERTY_VALUE_TECDH MCUXCLELS_KEYPROPERTY_VALUE_TECDH +#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET MCUXCLELS_KEYPROPERTY_VALUE_TLS_MASTER_SECRET +#define MCUXCLCSS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET MCUXCLELS_KEYPROPERTY_VALUE_TLS_PREMASTER_SECRET +#define MCUXCLCSS_KEYPROPERTY_VALUE_WRPOK MCUXCLELS_KEYPROPERTY_VALUE_WRPOK +#define MCUXCLCSS_KEYPROPERTY_WRAP_FALSE MCUXCLELS_KEYPROPERTY_WRAP_FALSE +#define MCUXCLCSS_KEYPROPERTY_WRAP_TRUE MCUXCLELS_KEYPROPERTY_WRAP_TRUE +#define MCUXCLCSS_KEYPROV_DUK_UPDATE_DISABLE MCUXCLELS_KEYPROV_DUK_UPDATE_DISABLE +#define MCUXCLCSS_KEYPROV_DUK_UPDATE_ENABLE MCUXCLELS_KEYPROV_DUK_UPDATE_ENABLE +#define MCUXCLCSS_KEYPROV_KEYSHARE_TABLE_SIZE MCUXCLELS_KEYPROV_KEYSHARE_TABLE_SIZE +#define MCUXCLCSS_KEYPROV_KEY_PART_1_SIZE MCUXCLELS_KEYPROV_KEY_PART_1_SIZE +#define MCUXCLCSS_KEYPROV_NOIC_DISABLE MCUXCLELS_KEYPROV_NOIC_DISABLE +#define MCUXCLCSS_KEYPROV_NOIC_ENABLE MCUXCLELS_KEYPROV_NOIC_ENABLE +#define MCUXCLCSS_KEYPROV_TESTERSHARE_SIZE MCUXCLELS_KEYPROV_TESTERSHARE_SIZE +#define MCUXCLCSS_KEYPROV_VALUE_NOIC MCUXCLELS_KEYPROV_VALUE_NOIC +#define MCUXCLCSS_KEY_SLOTS MCUXCLELS_KEY_SLOTS +#define MCUXCLCSS_MASTER_UNLOCK_ANY MCUXCLELS_MASTER_UNLOCK_ANY +#define MCUXCLCSS_RESET_CANCEL MCUXCLELS_RESET_CANCEL +#define MCUXCLCSS_RESET_DO_NOT_CANCEL MCUXCLELS_RESET_DO_NOT_CANCEL +#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_0 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_0 +#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_1 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_1 +#define MCUXCLCSS_RESP_GEN_AVAILABLE_SLOT_2 MCUXCLELS_RESP_GEN_AVAILABLE_SLOT_2 +#define MCUXCLCSS_RESP_GEN_SLOTS MCUXCLELS_RESP_GEN_SLOTS +#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_128 MCUXCLELS_RFC3394_CONTAINER_SIZE_128 +#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_256 MCUXCLELS_RFC3394_CONTAINER_SIZE_256 +#define MCUXCLCSS_RFC3394_CONTAINER_SIZE_P256 MCUXCLELS_RFC3394_CONTAINER_SIZE_P256 +#define MCUXCLCSS_RFC3394_OVERHEAD MCUXCLELS_RFC3394_OVERHEAD +#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE +#define MCUXCLCSS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE +#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_CTR MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR +#define MCUXCLCSS_RNG_DRBG_TEST_MODE_AES_ECB MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB +#define MCUXCLCSS_RNG_DRBG_TEST_MODE_EXTRACT MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT +#define MCUXCLCSS_RNG_DRBG_TEST_MODE_INSTANTIATE MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE +#define MCUXCLCSS_RNG_DTRNG_CONFIG_SIZE MCUXCLELS_RNG_DTRNG_CONFIG_SIZE +#define MCUXCLCSS_RNG_DTRNG_EVAL_CONFIG_SIZE MCUXCLELS_RNG_DTRNG_EVAL_CONFIG_SIZE +#define MCUXCLCSS_RNG_DTRNG_EVAL_RESULT_SIZE MCUXCLELS_RNG_DTRNG_EVAL_RESULT_SIZE +#define MCUXCLCSS_RNG_RAW_ENTROPY_SIZE MCUXCLELS_RNG_RAW_ENTROPY_SIZE +#define MCUXCLCSS_RNG_RND_REQ_PRND_INIT MCUXCLELS_RNG_RND_REQ_PRND_INIT +#define MCUXCLCSS_RNG_RND_REQ_RND_RAW MCUXCLELS_RNG_RND_REQ_RND_RAW +#define MCUXCLCSS_STATUS_DRBGENTLVL_HIGH MCUXCLELS_STATUS_DRBGENTLVL_HIGH +#define MCUXCLCSS_STATUS_DRBGENTLVL_LOW MCUXCLELS_STATUS_DRBGENTLVL_LOW +#define MCUXCLCSS_STATUS_DRBGENTLVL_NONE MCUXCLELS_STATUS_DRBGENTLVL_NONE +#define MCUXCLCSS_STATUS_ECDSAVFY_ERROR MCUXCLELS_STATUS_ECDSAVFY_ERROR +#define MCUXCLCSS_STATUS_ECDSAVFY_FAIL MCUXCLELS_STATUS_ECDSAVFY_FAIL +#define MCUXCLCSS_STATUS_ECDSAVFY_NORUN MCUXCLELS_STATUS_ECDSAVFY_NORUN +#define MCUXCLCSS_STATUS_ECDSAVFY_OK MCUXCLELS_STATUS_ECDSAVFY_OK +#define MCUXCLCSS_STATUS_HW_ALGORITHM MCUXCLELS_STATUS_HW_ALGORITHM +#define MCUXCLCSS_STATUS_HW_BUS MCUXCLELS_STATUS_HW_BUS +#define MCUXCLCSS_STATUS_HW_DTRNG MCUXCLELS_STATUS_HW_DTRNG +#define MCUXCLCSS_STATUS_HW_FAULT MCUXCLELS_STATUS_HW_FAULT +#define MCUXCLCSS_STATUS_HW_INTEGRITY MCUXCLELS_STATUS_HW_INTEGRITY +#define MCUXCLCSS_STATUS_HW_OPERATIONAL MCUXCLELS_STATUS_HW_OPERATIONAL +#define MCUXCLCSS_STATUS_HW_PRNG MCUXCLELS_STATUS_HW_PRNG +#define MCUXCLCSS_STATUS_IS_HW_ERROR MCUXCLELS_STATUS_IS_HW_ERROR +#define MCUXCLCSS_STATUS_IS_SW_ERROR MCUXCLELS_STATUS_IS_SW_ERROR +#define MCUXCLCSS_STATUS_OK MCUXCLELS_STATUS_OK +#define MCUXCLCSS_STATUS_OK_WAIT MCUXCLELS_STATUS_OK_WAIT +#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_NONSECURE MCUXCLELS_STATUS_PPROT_PRIVILEGED_NONSECURE +#define MCUXCLCSS_STATUS_PPROT_PRIVILEGED_SECURE MCUXCLELS_STATUS_PPROT_PRIVILEGED_SECURE +#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_NONSECURE MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_NONSECURE +#define MCUXCLCSS_STATUS_PPROT_UNPRIVILEGED_SECURE MCUXCLELS_STATUS_PPROT_UNPRIVILEGED_SECURE +#define MCUXCLCSS_STATUS_SW_CANNOT_INTERRUPT MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT +#define MCUXCLCSS_STATUS_SW_COMPARISON_FAILED MCUXCLELS_STATUS_SW_COMPARISON_FAILED +#define MCUXCLCSS_STATUS_SW_COUNTER_EXPIRED MCUXCLELS_STATUS_SW_COUNTER_EXPIRED +#define MCUXCLCSS_STATUS_SW_FAULT MCUXCLELS_STATUS_SW_FAULT +#define MCUXCLCSS_STATUS_SW_INVALID_PARAM MCUXCLELS_STATUS_SW_INVALID_PARAM +#define MCUXCLCSS_STATUS_SW_INVALID_STATE MCUXCLELS_STATUS_SW_INVALID_STATE +#define MCUXCLCSS_STATUS_SW_LOCKING_FAILED MCUXCLELS_STATUS_SW_LOCKING_FAILED +#define MCUXCLCSS_STATUS_SW_STATUS_LOCKED MCUXCLELS_STATUS_SW_STATUS_LOCKED +#define MCUXCLCSS_TLS_DERIVATIONDATA_SIZE MCUXCLELS_TLS_DERIVATIONDATA_SIZE +#define MCUXCLCSS_TLS_FINALIZE MCUXCLELS_TLS_FINALIZE +#define MCUXCLCSS_TLS_INIT MCUXCLELS_TLS_INIT +#define MCUXCLCSS_TLS_RANDOM_SIZE MCUXCLELS_TLS_RANDOM_SIZE + + +/* Public types */ +/** + * mcuxClCss_((?:AeadOption_t|CipherOption_t|CkdfOption_t|CmacOption_t|CommandCrcConfig_t|EccByte_t|EccKeyExchOption_t|EccKeyGenOption_t|EccSignOption_t|EccVerifyOption_t|ErrorHandling_t|HashOption_t|HkdfOption_t|HmacOption_t|HwConfig_t|HwState_t|HwVersion_t|InterruptOptionEn_t|InterruptOptionRst_t|InterruptOptionSet_t|KeyImportOption_t|KeyIndex_t|KeyProp_t|KeyProvisionOption_t|ResetOption_t|Status_Protected_t|Status_t|TlsOption_t|TransferToRegisterFunction_t))(?!\w) + * --> + * mcuxClEls_\1 + */ +#define mcuxClCss_AeadOption_t mcuxClEls_AeadOption_t +#define mcuxClCss_CipherOption_t mcuxClEls_CipherOption_t +#define mcuxClCss_CkdfOption_t mcuxClEls_CkdfOption_t +#define mcuxClCss_CmacOption_t mcuxClEls_CmacOption_t +#define mcuxClCss_CommandCrcConfig_t mcuxClEls_CommandCrcConfig_t +#define mcuxClCss_EccByte_t mcuxClEls_EccByte_t +#define mcuxClCss_EccKeyExchOption_t mcuxClEls_EccKeyExchOption_t +#define mcuxClCss_EccKeyGenOption_t mcuxClEls_EccKeyGenOption_t +#define mcuxClCss_EccSignOption_t mcuxClEls_EccSignOption_t +#define mcuxClCss_EccVerifyOption_t mcuxClEls_EccVerifyOption_t +#define mcuxClCss_ErrorHandling_t mcuxClEls_ErrorHandling_t +#define mcuxClCss_HashOption_t mcuxClEls_HashOption_t +#define mcuxClCss_HkdfOption_t mcuxClEls_HkdfOption_t +#define mcuxClCss_HmacOption_t mcuxClEls_HmacOption_t +#define mcuxClCss_HwConfig_t mcuxClEls_HwConfig_t +#define mcuxClCss_HwState_t mcuxClEls_HwState_t +#define mcuxClCss_HwVersion_t mcuxClEls_HwVersion_t +#define mcuxClCss_InterruptOptionEn_t mcuxClEls_InterruptOptionEn_t +#define mcuxClCss_InterruptOptionRst_t mcuxClEls_InterruptOptionRst_t +#define mcuxClCss_InterruptOptionSet_t mcuxClEls_InterruptOptionSet_t +#define mcuxClCss_KeyImportOption_t mcuxClEls_KeyImportOption_t +#define mcuxClCss_KeyIndex_t mcuxClEls_KeyIndex_t +#define mcuxClCss_KeyProp_t mcuxClEls_KeyProp_t +#define mcuxClCss_KeyProvisionOption_t mcuxClEls_KeyProvisionOption_t +#define mcuxClCss_ResetOption_t mcuxClEls_ResetOption_t +#define mcuxClCss_Status_Protected_t mcuxClEls_Status_Protected_t +#define mcuxClCss_Status_t mcuxClEls_Status_t +#define mcuxClCss_TlsOption_t mcuxClEls_TlsOption_t +#define mcuxClCss_TransferToRegisterFunction_t mcuxClEls_TransferToRegisterFunction_t + + +/* Public functions */ +/** + * mcuxClCss_((?:Aead_Finalize_Async|Aead_Init_Async|Aead_PartialInit_Async|Aead_UpdateAad_Async|Aead_UpdateData_Async|Cipher_Async|Ckdf_Sp800108_Async|Ckdf_Sp80056c_Expand_Async|Ckdf_Sp80056c_Extract_Async|Cmac_Async|CompareDmaFinalOutputAddress|ConfigureCommandCRC|Disable|EccKeyExchangeInt_Async|EccKeyExchange_Async|EccKeyGen_Async|EccSign_Async|EccVerifyInt_Async|EccVerify_Async|Enable_Async|GetCommandCRC|GetErrorCode|GetErrorLevel|GetHwConfig|GetHwState|GetHwVersion|GetIntEnableFlags|GetKeyProperties|GetLastDmaAddress|GetLock|GetRandomStartDelay|GlitchDetector_GetEventCounter|GlitchDetector_LoadConfig_Async|GlitchDetector_ResetEventCounter|GlitchDetector_Trim_Async|Hash_Async|Hash_ShaDirect|Hkdf_Rfc5869_Async|Hkdf_Sp80056c_Async|Hmac_Async|IsLocked|KeyDelete_Async|KeyExport_Async|KeyImportPuk_Async|KeyImport_Async|KeyProvisionRom_Async|KeyProvision_Async|LimitedWaitForOperation|Prng_GetRandom|Prng_GetRandomWord|Prng_Init_Async|ReleaseLock|ResetErrorFlags|ResetIntFlags|Reset_Async|RespGen_Async|Rng_DrbgRequestRaw_Async|Rng_DrbgRequest_Async|Rng_DrbgTestAesCtr_Async|Rng_DrbgTestAesEcb_Async|Rng_DrbgTestExtract_Async|Rng_DrbgTestInstantiate_Async|Rng_Dtrng_ConfigEvaluate_Async|Rng_Dtrng_ConfigLoadPrv_Async|Rng_Dtrng_ConfigLoad_Async|SetIntEnableFlags|SetIntFlags|SetMasterUnlock|SetRandomStartDelay|ShaDirect_Disable|ShaDirect_Enable|TlsGenerateMasterKeyFromPreMasterKey_Async|TlsGenerateSessionKeysFromMasterKey_Async|UpdateRefCRC|VerifyVsRefCRC|WaitForOperation))(?!\w) + * --> + * mcuxClEls_\1 + */ +#define mcuxClCss_Aead_Finalize_Async mcuxClEls_Aead_Finalize_Async +#define mcuxClCss_Aead_Init_Async mcuxClEls_Aead_Init_Async +#define mcuxClCss_Aead_PartialInit_Async mcuxClEls_Aead_PartialInit_Async +#define mcuxClCss_Aead_UpdateAad_Async mcuxClEls_Aead_UpdateAad_Async +#define mcuxClCss_Aead_UpdateData_Async mcuxClEls_Aead_UpdateData_Async +#define mcuxClCss_Cipher_Async mcuxClEls_Cipher_Async +#define mcuxClCss_Ckdf_Sp800108_Async mcuxClEls_Ckdf_Sp800108_Async +#define mcuxClCss_Ckdf_Sp80056c_Expand_Async mcuxClEls_Ckdf_Sp80056c_Expand_Async +#define mcuxClCss_Ckdf_Sp80056c_Extract_Async mcuxClEls_Ckdf_Sp80056c_Extract_Async +#define mcuxClCss_Cmac_Async mcuxClEls_Cmac_Async +#define mcuxClCss_CompareDmaFinalOutputAddress mcuxClEls_CompareDmaFinalOutputAddress +#define mcuxClCss_ConfigureCommandCRC mcuxClEls_ConfigureCommandCRC +#define mcuxClCss_Disable mcuxClEls_Disable +#define mcuxClCss_EccKeyExchangeInt_Async mcuxClEls_EccKeyExchangeInt_Async +#define mcuxClCss_EccKeyExchange_Async mcuxClEls_EccKeyExchange_Async +#define mcuxClCss_EccKeyGen_Async mcuxClEls_EccKeyGen_Async +#define mcuxClCss_EccSign_Async mcuxClEls_EccSign_Async +#define mcuxClCss_EccVerifyInt_Async mcuxClEls_EccVerifyInt_Async +#define mcuxClCss_EccVerify_Async mcuxClEls_EccVerify_Async +#define mcuxClCss_Enable_Async mcuxClEls_Enable_Async +#define mcuxClCss_GetCommandCRC mcuxClEls_GetCommandCRC +#define mcuxClCss_GetErrorCode mcuxClEls_GetErrorCode +#define mcuxClCss_GetErrorLevel mcuxClEls_GetErrorLevel +#define mcuxClCss_GetHwConfig mcuxClEls_GetHwConfig +#define mcuxClCss_GetHwState mcuxClEls_GetHwState +#define mcuxClCss_GetHwVersion mcuxClEls_GetHwVersion +#define mcuxClCss_GetIntEnableFlags mcuxClEls_GetIntEnableFlags +#define mcuxClCss_GetKeyProperties mcuxClEls_GetKeyProperties +#define mcuxClCss_GetLastDmaAddress mcuxClEls_GetLastDmaAddress +#define mcuxClCss_GetLock mcuxClEls_GetLock +#define mcuxClCss_GetRandomStartDelay mcuxClEls_GetRandomStartDelay +#define mcuxClCss_GlitchDetector_GetEventCounter mcuxClEls_GlitchDetector_GetEventCounter +#define mcuxClCss_GlitchDetector_LoadConfig_Async mcuxClEls_GlitchDetector_LoadConfig_Async +#define mcuxClCss_GlitchDetector_ResetEventCounter mcuxClEls_GlitchDetector_ResetEventCounter +#define mcuxClCss_GlitchDetector_Trim_Async mcuxClEls_GlitchDetector_Trim_Async +#define mcuxClCss_Hash_Async mcuxClEls_Hash_Async +#define mcuxClCss_Hash_ShaDirect mcuxClEls_Hash_ShaDirect +#define mcuxClCss_Hkdf_Rfc5869_Async mcuxClEls_Hkdf_Rfc5869_Async +#define mcuxClCss_Hkdf_Sp80056c_Async mcuxClEls_Hkdf_Sp80056c_Async +#define mcuxClCss_Hmac_Async mcuxClEls_Hmac_Async +#define mcuxClCss_IsLocked mcuxClEls_IsLocked +#define mcuxClCss_KeyDelete_Async mcuxClEls_KeyDelete_Async +#define mcuxClCss_KeyExport_Async mcuxClEls_KeyExport_Async +#define mcuxClCss_KeyImportPuk_Async mcuxClEls_KeyImportPuk_Async +#define mcuxClCss_KeyImport_Async mcuxClEls_KeyImport_Async +#define mcuxClCss_KeyProvisionRom_Async mcuxClEls_KeyProvisionRom_Async +#define mcuxClCss_KeyProvision_Async mcuxClEls_KeyProvision_Async +#define mcuxClCss_LimitedWaitForOperation mcuxClEls_LimitedWaitForOperation +#define mcuxClCss_Prng_GetRandom mcuxClEls_Prng_GetRandom +#define mcuxClCss_Prng_GetRandomWord mcuxClEls_Prng_GetRandomWord +#define mcuxClCss_Prng_Init_Async mcuxClEls_Prng_Init_Async +#define mcuxClCss_ReleaseLock mcuxClEls_ReleaseLock +#define mcuxClCss_ResetErrorFlags mcuxClEls_ResetErrorFlags +#define mcuxClCss_ResetIntFlags mcuxClEls_ResetIntFlags +#define mcuxClCss_Reset_Async mcuxClEls_Reset_Async +#define mcuxClCss_RespGen_Async mcuxClEls_RespGen_Async +#define mcuxClCss_Rng_DrbgRequestRaw_Async mcuxClEls_Rng_DrbgRequestRaw_Async +#define mcuxClCss_Rng_DrbgRequest_Async mcuxClEls_Rng_DrbgRequest_Async +#define mcuxClCss_Rng_DrbgTestAesCtr_Async mcuxClEls_Rng_DrbgTestAesCtr_Async +#define mcuxClCss_Rng_DrbgTestAesEcb_Async mcuxClEls_Rng_DrbgTestAesEcb_Async +#define mcuxClCss_Rng_DrbgTestExtract_Async mcuxClEls_Rng_DrbgTestExtract_Async +#define mcuxClCss_Rng_DrbgTestInstantiate_Async mcuxClEls_Rng_DrbgTestInstantiate_Async +#define mcuxClCss_Rng_Dtrng_ConfigEvaluate_Async mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async +#define mcuxClCss_Rng_Dtrng_ConfigLoadPrv_Async mcuxClEls_Rng_Dtrng_ConfigLoadPrv_Async +#define mcuxClCss_Rng_Dtrng_ConfigLoad_Async mcuxClEls_Rng_Dtrng_ConfigLoad_Async +#define mcuxClCss_SetIntEnableFlags mcuxClEls_SetIntEnableFlags +#define mcuxClCss_SetIntFlags mcuxClEls_SetIntFlags +#define mcuxClCss_SetMasterUnlock mcuxClEls_SetMasterUnlock +#define mcuxClCss_SetRandomStartDelay mcuxClEls_SetRandomStartDelay +#define mcuxClCss_ShaDirect_Disable mcuxClEls_ShaDirect_Disable +#define mcuxClCss_ShaDirect_Enable mcuxClEls_ShaDirect_Enable +#define mcuxClCss_TlsGenerateMasterKeyFromPreMasterKey_Async mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async +#define mcuxClCss_TlsGenerateSessionKeysFromMasterKey_Async mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async +#define mcuxClCss_UpdateRefCRC mcuxClEls_UpdateRefCRC +#define mcuxClCss_VerifyVsRefCRC mcuxClEls_VerifyVsRefCRC +#define mcuxClCss_WaitForOperation mcuxClEls_WaitForOperation + +/** + * There are also corresponding changes in other components: + * mcuxClMac_Mode_HMAC_SHA2_256_CSS -> mcuxClMac_Mode_HMAC_SHA2_256_ELS + * mcuxClRandomModes_Mode_CSS_Drbg -> mcuxClRandomModes_Mode_ELS_Drbg + */ + +#endif /* MCUXCLELS_MAPPING_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Aead.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Aead.c new file mode 100644 index 000000000..d9de176a1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Aead.c @@ -0,0 +1,239 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Aead.c + * @brief ELS implementation for Authenticated Encryption with Associated Data (AEAD). + * This file implements the functions declared in mcuxClEls_Aead.h. */ + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Aead_Init_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Init_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pIV, + size_t ivLength, + uint8_t * pAeadCtx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Aead_Init_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Aead_Init_Async, (MCUXCLELS_AEAD_INTERN_KEY == options.bits.extkey && ELS_KS_CNT <= keyIdx) || ((MCUXCLELS_AEAD_EXTERN_KEY == options.bits.extkey && ((MCUXCLELS_CIPHER_KEY_SIZE_AES_128 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_192 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_256 != keyLength)))) + || (0u == ivLength) || (0u != ivLength % MCUXCLELS_AEAD_IV_BLOCK_SIZE)); + + uint8_t * pStartIpCtxArea = pAeadCtx + MCUXCLELS_CIPHER_BLOCK_SIZE_AES; + + /* Set init mode */ + options.bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; + options.bits.lastinit = MCUXCLELS_AEAD_LASTINIT_TRUE; + + options.bits.acpsie = MCUXCLELS_AEAD_STATE_IN_DISABLE; +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + options.bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_Init_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0(pIV, ivLength); + mcuxClEls_setInput1_fixedSize(pStartIpCtxArea); + mcuxClEls_setInput2(pKey, keyLength); + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_AUTH_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_Init_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Aead_PartialInit_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_PartialInit_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pIV, + size_t ivLength, + uint8_t * pAeadCtx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Aead_PartialInit_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Aead_PartialInit_Async, (MCUXCLELS_AEAD_INTERN_KEY == options.bits.extkey && ELS_KS_CNT <= keyIdx) || ((MCUXCLELS_AEAD_EXTERN_KEY == options.bits.extkey && ((MCUXCLELS_CIPHER_KEY_SIZE_AES_128 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_192 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_256 != keyLength)))) + || (0u == ivLength) || (0u != ivLength % MCUXCLELS_AEAD_IV_BLOCK_SIZE)); + + uint8_t * pStartIpCtxArea = pAeadCtx + MCUXCLELS_CIPHER_BLOCK_SIZE_AES; + + /* Set init mode */ + options.bits.acpmod = MCUXCLELS_AEAD_ACPMOD_INIT; + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + options.bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_PartialInit_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0(pIV, ivLength); + mcuxClEls_setInput1_fixedSize(pStartIpCtxArea); + mcuxClEls_setInput2(pKey, keyLength); + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_AUTH_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_PartialInit_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Aead_UpdateAad_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateAad_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pAad, + size_t aadLength, + uint8_t * pAeadCtx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Aead_UpdateAad_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Aead_UpdateAad_Async, (MCUXCLELS_AEAD_INTERN_KEY == options.bits.extkey && ELS_KS_CNT <= keyIdx) + || (MCUXCLELS_AEAD_EXTERN_KEY == options.bits.extkey && (MCUXCLELS_CIPHER_KEY_SIZE_AES_128 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_192 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_256 != keyLength)) + || (0U == aadLength) || (0u != aadLength % MCUXCLELS_AEAD_AAD_BLOCK_SIZE)); + + uint8_t * pStartIpCtxArea = pAeadCtx + MCUXCLELS_CIPHER_BLOCK_SIZE_AES; + + options.bits.acpmod = MCUXCLELS_AEAD_ACPMOD_AADPROC; + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + options.bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; + options.bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_UpdateAad_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput2(pKey, keyLength); + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setInput0(pAad, aadLength); + mcuxClEls_setInput1_fixedSize(pStartIpCtxArea); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_AUTH_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_UpdateAad_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Aead_UpdateData_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_UpdateData_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pOutput, + uint8_t * pAeadCtx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Aead_UpdateData_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Aead_UpdateData_Async, (0U == inputLength) || (0u != inputLength % MCUXCLELS_CIPHER_BLOCK_SIZE_AES) || (MCUXCLELS_AEAD_INTERN_KEY == options.bits.extkey && ELS_KS_CNT <= keyIdx) + || (MCUXCLELS_AEAD_EXTERN_KEY == options.bits.extkey && (MCUXCLELS_CIPHER_KEY_SIZE_AES_128 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_192 != keyLength && MCUXCLELS_CIPHER_KEY_SIZE_AES_256 != keyLength))); + + uint8_t * pStartIpCtxArea = pAeadCtx + MCUXCLELS_CIPHER_BLOCK_SIZE_AES; + + options.bits.acpmod = MCUXCLELS_AEAD_ACPMOD_MSGPROC; + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + options.bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; + options.bits.acpsoe = MCUXCLELS_AEAD_STATE_OUT_ENABLE; +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_UpdateData_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput2(pKey, keyLength); + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setInput0(pInput, inputLength); + mcuxClEls_setInput1_fixedSize(pStartIpCtxArea); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_AUTH_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_UpdateData_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Aead_Finalize_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Aead_Finalize_Async( + mcuxClEls_AeadOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + size_t aadLength, + size_t dataLength, + uint8_t * pTag, + uint8_t * pAeadCtx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Aead_Finalize_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Aead_Finalize_Async, (MCUXCLELS_AEAD_INTERN_KEY == options.bits.extkey && ELS_KS_CNT <= keyIdx) || (MCUXCLELS_AEAD_EXTERN_KEY == options.bits.extkey && (16U != keyLength && 24U != keyLength && 32U != keyLength))); + + uint8_t * pStartIpCtxArea = pAeadCtx + MCUXCLELS_CIPHER_BLOCK_SIZE_AES; + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + options.bits.acpsie = MCUXCLELS_AEAD_STATE_IN_ENABLE; +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + /* Update the length of the AAD to store in the context */ + aadLength <<= 3; + /* Update the length of the data to store in the context */ + dataLength <<= 3; + /* Store both in the context */ + mcuxClMemory_StoreBigEndian32(&pAeadCtx[ 0u], (uint32_t) 0U); + mcuxClMemory_StoreBigEndian32(&pAeadCtx[ 4u], aadLength ); + mcuxClMemory_StoreBigEndian32(&pAeadCtx[ 8u], (uint32_t) 0U); + mcuxClMemory_StoreBigEndian32(&pAeadCtx[12u], dataLength); + + options.bits.acpmod = MCUXCLELS_AEAD_ACPMOD_FINAL; + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_Finalize_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput2(pKey, keyLength); + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setInput0_fixedSize(pAeadCtx); + mcuxClEls_setInput1_fixedSize(pStartIpCtxArea); + mcuxClEls_setOutput_fixedSize(pTag); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_AUTH_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Aead_Finalize_Async, MCUXCLELS_STATUS_OK_WAIT); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cipher.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cipher.c new file mode 100644 index 000000000..671e87584 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cipher.c @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Cipher.c + * @brief ELS implementation for symmetric ciphers. + * This file implements the functions declared in mcuxClEls_Cipher.h. */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Cipher_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cipher_Async( + mcuxClEls_CipherOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pIV, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Cipher_Async); + + // ignored misra violation -> false positive + // misra_c_2012_rule_11_9_violation: Literal 0 shall not be used as null pointer constant. + +#ifndef MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS + #define TMP_NO_INTERNAL_STATE_FLAGS (MCUXCLELS_CIPHER_STATE_IN_ENABLE == options.bits.cphsie) +#else + #define TMP_NO_INTERNAL_STATE_FLAGS (false) +#endif /* MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS */ + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Cipher_Async, + (0U == inputLength) + || (0U != (inputLength % MCUXCLELS_CIPHER_BLOCK_SIZE_AES)) + || ((MCUXCLELS_CIPHER_INTERNAL_KEY == options.bits.extkey) && (ELS_KS_CNT <= keyIdx)) + || ((MCUXCLELS_CIPHER_EXTERNAL_KEY == options.bits.extkey) && ((MCUXCLELS_CIPHER_KEY_SIZE_AES_128 != keyLength) && (MCUXCLELS_CIPHER_KEY_SIZE_AES_192 != keyLength) && (MCUXCLELS_CIPHER_KEY_SIZE_AES_256 != keyLength))) + || (MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_CTR < options.bits.cphmde) + /* ECB doesn't support importing or exporting an IV */ + || ((MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB == options.bits.cphmde) && ((MCUXCLELS_CIPHER_STATE_OUT_ENABLE == options.bits.cphsoe) || (TMP_NO_INTERNAL_STATE_FLAGS == true)))); + +#undef TMP_NO_INTERNAL_STATE_FLAGS + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Cipher_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0(pInput, inputLength); + if (0U == options.bits.extkey) + { + mcuxClEls_setKeystoreIndex0(keyIdx); + } + else + { + mcuxClEls_setInput2(pKey, keyLength); + } + + mcuxClEls_setInput1_fixedSize(pIV); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_CIPHER, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Cipher_Async, MCUXCLELS_STATUS_OK_WAIT); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cmac.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cmac.c new file mode 100644 index 000000000..d2300a089 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Cmac.c @@ -0,0 +1,85 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Cmac.c + * @brief ELS implementation for CMAC support. + * This file implements the functions declared in mcuxClEls_Cmac.h. */ + +#include +#include +#include +#include +#include +#include +#include + +#define MCUXCLELS_CMAC_STATE_IN_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.sie to this value to use the CMAC state that is present inside ELS +#define MCUXCLELS_CMAC_STATE_IN_ENABLE 1U ///< Set #mcuxClEls_CmacOption_t.sie to this value to import the CMAC state from memory +#define MCUXCLELS_CMAC_STATE_OUT_DISABLE 0U ///< Set #mcuxClEls_CmacOption_t.soe to this value to keep the CMAC state inside ELS at the end of the command +#define MCUXCLELS_CMAC_STATE_OUT_ENABLE 1U ///< Set #mcuxClEls_CmacOption_t.soe to this value to export the CMAC state to memory at the end of the command + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Cmac_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Cmac_Async( + mcuxClEls_CmacOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pKey, + size_t keyLength, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pMac) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Cmac_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Cmac_Async, (MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE == options.bits.extkey && ELS_KS_CNT <= keyIdx) || (MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE == options.bits.extkey && ((MCUXCLELS_CMAC_KEY_SIZE_128 != keyLength) && (MCUXCLELS_CMAC_KEY_SIZE_256 != keyLength)))); + + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Cmac_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + if(MCUXCLELS_CMAC_INITIALIZE_ENABLE == options.bits.initialize) + { + options.bits.sie = MCUXCLELS_CMAC_STATE_IN_DISABLE; + } + else + { + options.bits.sie = MCUXCLELS_CMAC_STATE_IN_ENABLE; + } + if(MCUXCLELS_CMAC_FINALIZE_ENABLE == options.bits.finalize) + { + options.bits.soe = MCUXCLELS_CMAC_STATE_OUT_DISABLE; + } + else + { + options.bits.soe = MCUXCLELS_CMAC_STATE_OUT_ENABLE; + } + + if (0U == options.bits.extkey) + { + mcuxClEls_setKeystoreIndex0(keyIdx); + } + else + { + mcuxClEls_setInput2(pKey, keyLength); + } + + mcuxClEls_setInput0(pInput, inputLength); + mcuxClEls_setInput1_fixedSize(pMac); + mcuxClEls_setOutput_fixedSize(pMac); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_CMAC, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Cmac_Async, MCUXCLELS_STATUS_OK_WAIT); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c new file mode 100644 index 000000000..50b522070 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Common.c @@ -0,0 +1,381 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Common.c + * @brief ELS implementation for common functionality. + * This file implements the functions declared in mcuxClEls_Common.h and adds helper functions used by other implementation headers. */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwVersion) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwVersion( + mcuxClEls_HwVersion_t * result) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwVersion); + result->word.value = MCUXCLELS_SFR_READ(ELS_VERSION); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwVersion, MCUXCLELS_STATUS_OK); +} + +#ifdef MCUXCL_FEATURE_ELS_HWCONFIG +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwConfig) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwConfig( + mcuxClEls_HwConfig_t * result) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwConfig); + result->word.value = MCUXCLELS_SFR_READ(ELS_CONFIG); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwConfig, MCUXCLELS_STATUS_OK); +} +#endif /* MCUXCL_FEATURE_ELS_HWCONFIG */ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetHwState) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetHwState( + mcuxClEls_HwState_t * result) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetHwState); + result->word.value = MCUXCLELS_SFR_READ(ELS_STATUS); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetHwState, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Enable_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Enable_Async( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Enable_Async); + MCUXCLELS_SFR_WRITE(ELS_CTRL, MCUXCLELS_SFR_FIELD_FORMAT(ELS_CTRL, ELS_EN, 1u)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Enable_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Disable) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Disable( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Disable); + MCUXCLELS_SET_CTRL_FIELD(MCUXCLELS_SFR_CTRL_ELS_EN, 0u); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Disable, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetErrorCode) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorCode( + mcuxClEls_ErrorHandling_t errorHandling) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetErrorCode); + + mcuxClEls_Status_t result = MCUXCLELS_STATUS_SW_FAULT; + if (1U == MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_ERR)) + { + if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_FLT_ERR)) + { + result = MCUXCLELS_STATUS_HW_FAULT; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_ITG_ERR)) + { + result = MCUXCLELS_STATUS_HW_INTEGRITY; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_OPN_ERR)) + { + result = MCUXCLELS_STATUS_HW_OPERATIONAL; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_ALG_ERR)) + { + result = MCUXCLELS_STATUS_HW_ALGORITHM; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_BUS_ERR)) + { + result = MCUXCLELS_STATUS_HW_BUS; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR)) + { + result = MCUXCLELS_STATUS_HW_PRNG; + } + else if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_DTRNG_ERR)) + { + result = MCUXCLELS_STATUS_HW_DTRNG; + } + else + { + result = MCUXCLELS_STATUS_SW_FAULT; + } + } + else + { + result = MCUXCLELS_STATUS_OK; + } + + if (MCUXCLELS_ERROR_FLAGS_CLEAR == errorHandling){ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetErrorFlags()); /* always returns MCUXCLELS_STATUS_OK. */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorCode, result, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetErrorFlags)); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorCode, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetErrorLevel) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetErrorLevel( + mcuxClEls_ErrorHandling_t errorHandling, + uint32_t *errorLevel) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetErrorLevel); + + *errorLevel = MCUXCLELS_GET_ERROR_STATUS_FIELD(MCUXCLELS_SFR_ERR_STATUS_ERR_LVL); + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling)); + + /* Exit function with expectation: mcuxClEls_GetErrorCode was called unconditionally */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetErrorLevel, result, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_WaitForOperation) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_WaitForOperation( + mcuxClEls_ErrorHandling_t errorHandling) +{ + /* Enter flow-protected function with expectation: mcuxClEls_GetErrorCode will be called (unconditionally) */ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_WaitForOperation, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode)); + + while (mcuxClEls_isBusy()) + { + // Do nothing + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_WaitForOperation, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_LimitedWaitForOperation) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_LimitedWaitForOperation( + uint32_t counterLimit, + mcuxClEls_ErrorHandling_t errorHandling) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_LimitedWaitForOperation); + + bool counterExpired = true; + while (0U != counterLimit) + { + if (!mcuxClEls_isBusy()) + { + counterExpired = false; + break; + } + counterLimit--; + } + + if (true == counterExpired) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_LimitedWaitForOperation, MCUXCLELS_STATUS_SW_COUNTER_EXPIRED); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_GetErrorCode(errorHandling)); + + /* Exit function with expectation: mcuxClEls_GetErrorCode was called */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_LimitedWaitForOperation, result, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetErrorCode)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ResetErrorFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetErrorFlags( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ResetErrorFlags); + + MCUXCLELS_SFR_WRITE(ELS_ERR_STATUS_CLR, MCUXCLELS_SFR_FIELD_FORMAT(ELS_ERR_STATUS, CLR_ERR_CLR, MCUXCLELS_ERROR_FLAGS_CLEAR)); + // Poll error bit to be sure that error bits has been cleared. Required by HW spec. + while(0u != MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_ERR)) + { + // Do nothing + } + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ResetErrorFlags, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Reset_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Reset_Async( + mcuxClEls_ResetOption_t options) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Reset_Async); + + if (mcuxClEls_isBusy() && (MCUXCLELS_RESET_DO_NOT_CANCEL == options)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Reset_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Set the drbg_block_counter to a value triggering a reseed after the upcoming RESET operation via interrupt */ + mcuxClEls_rng_drbg_block_counter = MCUXCLELS_RNG_DRBG_BLOCK_COUNTER_THRESHOLD; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + MCUXCLELS_SET_CTRL_FIELD(MCUXCLELS_SFR_CTRL_RESET, 1u); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Reset_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetIntEnableFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntEnableFlags( + mcuxClEls_InterruptOptionEn_t options) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetIntEnableFlags); + MCUXCLELS_SFR_WRITE(ELS_INT_ENABLE, options.word.value); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetIntEnableFlags, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetIntEnableFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetIntEnableFlags( + mcuxClEls_InterruptOptionEn_t * result) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetIntEnableFlags); + result->word.value = MCUXCLELS_SFR_READ(ELS_INT_ENABLE); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetIntEnableFlags, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ResetIntFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ResetIntFlags( + mcuxClEls_InterruptOptionRst_t options) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ResetIntFlags); + MCUXCLELS_SFR_WRITE(ELS_INT_STATUS_CLR, options.word.value); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ResetIntFlags, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetIntFlags) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetIntFlags( + mcuxClEls_InterruptOptionSet_t options) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetIntFlags); + MCUXCLELS_SFR_WRITE(ELS_INT_STATUS_SET, options.word.value); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetIntFlags, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetRandomStartDelay) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetRandomStartDelay( + uint32_t delay) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetRandomStartDelay); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_SetRandomStartDelay, 1024u < delay); + + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetRandomStartDelay, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + MCUXCLELS_SET_CFG_FIELD(MCUXCLELS_SFR_CFG_ADCTRL, delay); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetRandomStartDelay, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetRandomStartDelay) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetRandomStartDelay( + uint32_t *delay) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetRandomStartDelay); + + *delay = MCUXCLELS_GET_CFG_FIELD(MCUXCLELS_SFR_CFG_ADCTRL); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetRandomStartDelay, MCUXCLELS_STATUS_OK); +} + +#ifdef MCUXCL_FEATURE_ELS_LOCKING +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetLock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLock( + uint32_t * pSessionId) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetLock); + + *pSessionId = MCUXCLELS_SFR_READ(ELS_SESSION_ID); + if(0u == *pSessionId) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLock, MCUXCLELS_STATUS_SW_LOCKING_FAILED); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLock, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_ReleaseLock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_ReleaseLock( + uint32_t sessionId) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_ReleaseLock); + MCUXCLELS_SFR_WRITE(ELS_SESSION_ID, sessionId); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_ReleaseLock, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_IsLocked) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_IsLocked( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_IsLocked); + + if(1u == MCUXCLELS_GET_STATUS_FIELD(MCUXCLELS_SFR_STATUS_ELS_LOCKED)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_IsLocked, MCUXCLELS_STATUS_SW_STATUS_LOCKED); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_IsLocked, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_SetMasterUnlock) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_SetMasterUnlock( + uint32_t masterId) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_SetMasterUnlock); + MCUXCLELS_SFR_WRITE(ELS_MASTER_ID, masterId); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_SetMasterUnlock, MCUXCLELS_STATUS_OK); +} +#endif /* MCUXCL_FEATURE_ELS_LOCKING */ + + +#ifdef MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetLastDmaAddress) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetLastDmaAddress(uint32_t* pLastAddress) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetLastDmaAddress); + + *pLastAddress = MCUXCLELS_SFR_READ(ELS_DMA_FIN_ADDR); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetLastDmaAddress, MCUXCLELS_STATUS_OK); + +} +#endif /* MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK */ + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_CompareDmaFinalOutputAddress) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_CompareDmaFinalOutputAddress( + uint8_t *outputStartAddress, + size_t expectedLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_CompareDmaFinalOutputAddress, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetLastDmaAddress)); + + /* Calculate the expected final address from the input */ + uint32_t expectedFinalAddress = (uint32_t)outputStartAddress + expectedLength; + + /* Get the actual final address from ELS - no result check as function always returns OK */ + uint32_t finalAddress; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_GetLastDmaAddress(&finalAddress)); + + /* Compare the expected address to the actual one */ + if(finalAddress != expectedFinalAddress) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_CompareDmaFinalOutputAddress, MCUXCLELS_STATUS_SW_COMPARISON_FAILED); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_CompareDmaFinalOutputAddress, MCUXCLELS_STATUS_OK); + +} +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Ecc.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Ecc.c new file mode 100644 index 000000000..55e9dc7fb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Ecc.c @@ -0,0 +1,250 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Ecc.c + * @brief ELS implementation for elliptic curve cryptography. + * This file implements the functions declared in mcuxClEls_Ecc.h. + */ + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccKeyGen_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyGen_Async( + mcuxClEls_EccKeyGenOption_t options, + mcuxClEls_KeyIndex_t signingKeyIdx, + mcuxClEls_KeyIndex_t privateKeyIdx, + mcuxClEls_KeyProp_t generatedKeyProperties, + uint8_t const * pRandomData, + uint8_t * pPublicKey) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccKeyGen_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_EccKeyGen_Async, (ELS_KS_CNT <= signingKeyIdx) || (ELS_KS_CNT <= privateKeyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyGen_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + if(MCUXCLELS_ECC_OUTPUTKEY_RANDOM == options.bits.kgsrc) + { + /* If the DRBG was used, increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + mcuxClEls_rng_drbg_block_counter += MCUXCLELS_RNG_DRBG_ECCKEYGEN_INCREASE; + } +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + mcuxClEls_setKeystoreIndex0(privateKeyIdx); + mcuxClEls_setKeystoreIndex1(signingKeyIdx); + mcuxClEls_setRequestedKeyProperties(generatedKeyProperties.word.value); + mcuxClEls_setInput0_fixedSize(pRandomData); + mcuxClEls_setOutput_fixedSize(pPublicKey); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_KEYGEN, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyGen_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccKeyExchange_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchange_Async( + mcuxClEls_KeyIndex_t privateKeyIdx, + uint8_t const * pPublicKey, + mcuxClEls_KeyIndex_t sharedSecretIdx, + mcuxClEls_KeyProp_t sharedSecretProperties) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccKeyExchange_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_EccKeyExchange_Async, (ELS_KS_CNT <= privateKeyIdx) || (ELS_KS_CNT <= sharedSecretIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyExchange_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_EccKeyExchOption_t options = {0}; + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ + + mcuxClEls_setKeystoreIndex0(privateKeyIdx); + mcuxClEls_setInput1_fixedSize(pPublicKey); + mcuxClEls_setKeystoreIndex1(sharedSecretIdx); + mcuxClEls_setRequestedKeyProperties(sharedSecretProperties.word.value); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_ECKXH, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyExchange_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccKeyExchangeInt_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccKeyExchangeInt_Async( + mcuxClEls_KeyIndex_t privateKeyIdx, + mcuxClEls_KeyIndex_t publicKeyIdx, + mcuxClEls_KeyIndex_t sharedSecretIdx, + mcuxClEls_KeyProp_t sharedSecretProperties) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccKeyExchangeInt_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_EccKeyExchangeInt_Async, (ELS_KS_CNT <= privateKeyIdx) + || (ELS_KS_CNT <= publicKeyIdx) + || (ELS_KS_CNT <= sharedSecretIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyExchangeInt_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_EccKeyExchOption_t options = {0}; + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; + + mcuxClEls_setKeystoreIndex0(privateKeyIdx); + mcuxClEls_setKeystoreIndex2(publicKeyIdx); + mcuxClEls_setKeystoreIndex1(sharedSecretIdx); + mcuxClEls_setRequestedKeyProperties(sharedSecretProperties.word.value); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_ECKXH, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccKeyExchangeInt_Async, MCUXCLELS_STATUS_OK_WAIT); +} +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccSign_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccSign_Async( + mcuxClEls_EccSignOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccSign_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_EccSign_Async, (ELS_KS_CNT <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccSign_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + mcuxClEls_rng_drbg_block_counter += MCUXCLELS_RNG_DRBG_ECCSIGN_INCREASE; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setInput0((options.bits.echashchl == 0u) ? pInputHash : pInputMessage, inputMessageLength); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_ECSIGN, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccSign_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccVerify_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerify_Async( + mcuxClEls_EccVerifyOption_t options, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t const * pSignatureAndPubKey, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccVerify_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccVerify_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_EXTERNAL; +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT */ + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + mcuxClEls_rng_drbg_block_counter += MCUXCLELS_RNG_DRBG_ECCVERIFY_INCREASE; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + mcuxClEls_setInput0((options.bits.echashchl == 0u) ? pInputHash : pInputMessage, inputMessageLength); + mcuxClEls_setInput1_fixedSize(pSignatureAndPubKey); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_ECVFY, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccVerify_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_EccVerifyInt_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_EccVerifyInt_Async( + mcuxClEls_EccVerifyOption_t options, + mcuxClEls_KeyIndex_t publicKeyIdx, + uint8_t const * pInputHash, + uint8_t const * pInputMessage, + size_t inputMessageLength, + uint8_t const * pSignature, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_EccVerifyInt_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_EccVerifyInt_Async, (ELS_KS_CNT <= publicKeyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccVerifyInt_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + options.bits.revf = MCUXCLELS_ECC_REVERSEFETCH_ENABLE; + options.bits.extkey = MCUXCLELS_ECC_EXTKEY_INTERNAL; + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + mcuxClEls_rng_drbg_block_counter += MCUXCLELS_RNG_DRBG_ECCVERIFY_INCREASE; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + mcuxClEls_setInput0((options.bits.echashchl == 0u) ? pInputHash : pInputMessage, inputMessageLength); + mcuxClEls_setInput1_fixedSize(pSignature); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_setKeystoreIndex2(publicKeyIdx); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_ECVFY, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_EccVerifyInt_Async, MCUXCLELS_STATUS_OK_WAIT); +} +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c new file mode 100644 index 000000000..ba3fe95bb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_GlitchDetector.c @@ -0,0 +1,98 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_GlitchDetector.c + * @brief ELS implementation for key management. + * This file implements the functions declared in mcuxClEls_GlitchDetector.h. */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_LoadConfig_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_LoadConfig_Async( + uint8_t const * pInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_LoadConfig_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_LoadConfig_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0_fixedSize(pInput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_GDET_CFG_LOAD, 0U, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_LoadConfig_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_Trim_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_Trim_Async( + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_Trim_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_Trim_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_GDET_TRIM, 0U, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_Trim_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_GetEventCounter) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_GetEventCounter( + uint8_t * pCount) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_GetEventCounter); + + // Decode from Gray coding + uint8_t count8 = (uint8_t) MCUXCLELS_GET_GDET_EVTCNT_FIELD(MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT); + count8 ^= count8 >> 4u; + count8 ^= count8 >> 2u; + count8 ^= count8 >> 1u; + + // Assign to the result variable + *pCount = count8; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_GetEventCounter, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GlitchDetector_ResetEventCounter) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GlitchDetector_ResetEventCounter( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GlitchDetector_ResetEventCounter); + + // Start GDET Event Counter reset + MCUXCLELS_SFR_WRITE(ELS_GDET_EVTCNT_CLR, 1u); + + // The actual reset occurs in a different clock domain from the ELS core clock, so we have to wait for synchroni- + // zation. The spec states that this takes on the order of 2 cycles of the ELS core clock plus 2 cycles of the + // Glitch Detector reference clock. + while(1u != MCUXCLELS_GET_GDET_EVTCNT_FIELD(MCUXCLELS_SFR_GDET_EVTCNT_GDET_EVTCNT_CLR_DONE)) + { + // Do nothing + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GlitchDetector_ResetEventCounter, MCUXCLELS_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hash.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hash.c new file mode 100644 index 000000000..2f60d4eb7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hash.c @@ -0,0 +1,62 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Hash.c + * @brief ELS implementation for hashing. + * This file implements the functions declared in mcuxClEls_Hash.h. */ + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Hash_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hash_Async( + mcuxClEls_HashOption_t options, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pDigest) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Hash_Async); + + /* Length must not be zero and aligned with the block length */ + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Hash_Async, + (0 == 1) // fixing MISRA warning + || ((MCUXCLELS_HASH_MODE_SHA_224 == options.bits.hashmd) && (0u != (inputLength % MCUXCLELS_HASH_BLOCK_SIZE_SHA_224))) + || ((MCUXCLELS_HASH_MODE_SHA_256 == options.bits.hashmd) && (0u != (inputLength % MCUXCLELS_HASH_BLOCK_SIZE_SHA_256))) + || ((MCUXCLELS_HASH_RTF_UPDATE_ENABLE == options.bits.rtfupd) && (MCUXCLELS_HASH_MODE_SHA_256 != options.bits.hashmd)) + || ((MCUXCLELS_HASH_RTF_UPDATE_ENABLE != options.bits.rtfupd) && (MCUXCLELS_HASH_RTF_OUTPUT_ENABLE == options.bits.rtfoe)) + || ((MCUXCLELS_HASH_OUTPUT_ENABLE != options.bits.hashoe) && (MCUXCLELS_HASH_RTF_OUTPUT_ENABLE == options.bits.rtfoe)) + || ((MCUXCLELS_HASH_MODE_SHA_384 == options.bits.hashmd) && (0u != (inputLength % MCUXCLELS_HASH_BLOCK_SIZE_SHA_384))) + || ((MCUXCLELS_HASH_MODE_SHA_512 == options.bits.hashmd) && (0u != (inputLength % MCUXCLELS_HASH_BLOCK_SIZE_SHA_512))) + ); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hash_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0(pInput, inputLength); + mcuxClEls_setInput1_fixedSize(pDigest); + mcuxClEls_setOutput_fixedSize(pDigest); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_HASH, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hash_Async, MCUXCLELS_STATUS_OK_WAIT); + +} + diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hmac.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hmac.c new file mode 100644 index 000000000..4d74de5fb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Hmac.c @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Hmac.c + * @brief ELS implementation for HMAC support. + * This file implements the functions declared in mcuxClEls_Hmac.h. */ + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Hmac_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hmac_Async( + mcuxClEls_HmacOption_t options, + mcuxClEls_KeyIndex_t keyIdx, + uint8_t const * pPaddedKey, + uint8_t const * pInput, + size_t inputLength, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Hmac_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Hmac_Async, (0U == inputLength) || (MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE == options.bits.extkey && ELS_KS_CNT <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hmac_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + if (0U == options.bits.extkey) + { + mcuxClEls_setKeystoreIndex0(keyIdx); + } + else + { + mcuxClEls_setInput2_fixedSize(pPaddedKey); + } + mcuxClEls_setInput0(pInput, inputLength); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_HMAC, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hmac_Async, MCUXCLELS_STATUS_OK_WAIT); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Kdf.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Kdf.c new file mode 100644 index 000000000..e58c2bfee --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Kdf.c @@ -0,0 +1,164 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_Kdf.c + * @brief ELS implementation for key derivation. + * This file implements the functions declared in mcuxClEls_Kdf.h. */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Ckdf_Sp800108_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Ckdf_Sp800108_Async( + mcuxClEls_KeyIndex_t derivationKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx, + mcuxClEls_KeyProp_t targetKeyProperties, + uint8_t const * pDerivationData) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Ckdf_Sp800108_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Ckdf_Sp800108_Async, (ELS_KS_CNT <= derivationKeyIdx) || (ELS_KS_CNT <= targetKeyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Ckdf_Sp800108_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_CkdfOption_t option = {0}; + option.bits.ckdf_algo = MCUXCLELS_CKDF_ALGO_SP800108; + + mcuxClEls_setKeystoreIndex0(derivationKeyIdx); + mcuxClEls_setKeystoreIndex1(targetKeyIdx); + mcuxClEls_setRequestedKeyProperties(targetKeyProperties.word.value); + mcuxClEls_setInput0_fixedSize(pDerivationData); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_CKDF, option.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Ckdf_Sp800108_Async, MCUXCLELS_STATUS_OK_WAIT); +} + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Hkdf_Rfc5869_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Rfc5869_Async( + mcuxClEls_HkdfOption_t options, + mcuxClEls_KeyIndex_t derivationKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx, + mcuxClEls_KeyProp_t targetKeyProperties, + uint8_t const * pDerivationData) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Hkdf_Rfc5869_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Hkdf_Rfc5869_Async, (ELS_KS_CNT <= derivationKeyIdx) || (ELS_KS_CNT <= targetKeyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hkdf_Rfc5869_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + options.bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_RFC5869; + + mcuxClEls_setKeystoreIndex0(derivationKeyIdx); + mcuxClEls_setKeystoreIndex1(targetKeyIdx); + mcuxClEls_setRequestedKeyProperties(targetKeyProperties.word.value); + mcuxClEls_setInput0_fixedSize(pDerivationData); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_HKDF, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hkdf_Rfc5869_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Hkdf_Sp80056c_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Hkdf_Sp80056c_Async( + mcuxClEls_KeyIndex_t derivationKeyIdx, + uint8_t * pTagetKey, + uint8_t const * pDerivationData, + size_t derivationDataLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Hkdf_Sp80056c_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Hkdf_Sp80056c_Async, (ELS_KS_CNT <= derivationKeyIdx) ); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hkdf_Sp80056c_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_HkdfOption_t options = {0}; + options.bits.hkdf_algo = MCUXCLELS_HKDF_ALGO_SP80056C; + + mcuxClEls_setKeystoreIndex0(derivationKeyIdx); + mcuxClEls_setInput0(pDerivationData, derivationDataLength); + mcuxClEls_setOutput_fixedSize(pTagetKey); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_HKDF, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Hkdf_Sp80056c_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async( + uint8_t const * pDerivationData, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t keyIdx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, (ELS_KS_CNT <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_TlsOption_t options = {0}; + options.bits.mode = MCUXCLELS_TLS_INIT; + + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setRequestedKeyProperties(keyProperties.word.value); + mcuxClEls_setInput0_fixedSize(pDerivationData); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_TLS, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_TlsGenerateMasterKeyFromPreMasterKey_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async( + uint8_t const * pDerivationData, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t keyIdx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async, ((ELS_KS_CNT - 4U) <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_TlsOption_t options = {0}; + options.bits.mode = MCUXCLELS_TLS_FINALIZE; + + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_setRequestedKeyProperties(keyProperties.word.value); + mcuxClEls_setInput0_fixedSize(pDerivationData); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_TLS, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_TlsGenerateSessionKeysFromMasterKey_Async, MCUXCLELS_STATUS_OK_WAIT); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_KeyManagement.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_KeyManagement.c new file mode 100644 index 000000000..fa39885b5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_KeyManagement.c @@ -0,0 +1,347 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClEls_KeyManagement.c + * @brief ELS implementation for key management. + * This file implements the functions declared in mcuxClEls_KeyManagement.h. */ + +#include +#include // Implement mcuxClEls interface "KeyManagement" +#include +#include +#include +#include +#include +#include + + +// Implementation of mcuxClEls interface "KeyManagement" + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_KeyDelete_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyDelete_Async( + mcuxClEls_KeyIndex_t keyIdx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_KeyDelete_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_KeyDelete_Async, (ELS_KS_CNT <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyDelete_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Get key properties */ + mcuxClEls_KeyProp_t key_properties; + MCUX_CSSL_FP_FUNCTION_CALL(status_keyprop, mcuxClEls_GetKeyProperties(keyIdx, &key_properties)); + if(MCUXCLELS_STATUS_OK != status_keyprop) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyDelete_Async, MCUXCLELS_STATUS_SW_FAULT); + } + uint32_t drbg_counter_increase = + ((key_properties.bits.ksize == MCUXCLELS_KEYPROPERTY_KEY_SIZE_128) + ? MCUXCLELS_RNG_DRBG_KEYDELETE128_INCREASE + : MCUXCLELS_RNG_DRBG_KEYDELETE256_INCREASE + ); + + /* Increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + mcuxClEls_rng_drbg_block_counter += drbg_counter_increase; + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties)); +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + mcuxClEls_setKeystoreIndex0(keyIdx); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_KDELETE, 0U, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyDelete_Async, MCUXCLELS_STATUS_OK_WAIT); +} + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_KeyImport_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImport_Async( + mcuxClEls_KeyImportOption_t options, + uint8_t const * pImportKey, + size_t importKeyLength, + mcuxClEls_KeyIndex_t wrappingKeyIdx, + mcuxClEls_KeyIndex_t targetKeyIdx) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_KeyImport_Async); + /* Key indices out of bounds or the source key pointer is NULL although the key format indicates that it should be imported from memory */ + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_KeyImport_Async, + (wrappingKeyIdx >= ELS_KS_CNT) + || (targetKeyIdx >= ELS_KS_CNT) + || ((options.bits.kfmt == MCUXCLELS_KEYIMPORT_KFMT_RFC3394) && (importKeyLength == 0u))); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyImport_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setKeystoreIndex0(wrappingKeyIdx); + mcuxClEls_setKeystoreIndex1(targetKeyIdx); + mcuxClEls_setInput0(pImportKey, importKeyLength); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_KEYIN, options.word.value, ELS_CMD_BIG_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyImport_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +#ifdef MCUXCL_FEATURE_ELS_PUK_INTERNAL +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_KeyImportPuk_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyImportPuk_Async( + uint8_t const * pCertificate, + size_t certificateLength, + size_t publicKeyOffset, + uint8_t const * pSignature, + mcuxClEls_KeyIndex_t verifyingKeyIdx, + mcuxClEls_KeyProp_t keyProperties, + mcuxClEls_KeyIndex_t targetKeyIdx, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_KeyImportPuk_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_KeyImportPuk_Async, (verifyingKeyIdx >= ELS_KS_CNT) || (targetKeyIdx >= ELS_KS_CNT)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyImportPuk_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_KeyImportOption_t options; + options.word.value = 0u; + options.bits.revf = MCUXCLELS_KEYIMPORT_REVERSEFETCH_ENABLE; + options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_PBK; + + mcuxClEls_setInput0(pCertificate, certificateLength); + mcuxClEls_setInput1_fixedSize(pSignature); + mcuxClEls_setInput2_fixedSize((const uint8_t *) publicKeyOffset); + + mcuxClEls_setRequestedKeyProperties(keyProperties.word.value); + mcuxClEls_setKeystoreIndex1(targetKeyIdx); + mcuxClEls_setKeystoreIndex2(verifyingKeyIdx); + + mcuxClEls_setOutput_fixedSize(pOutput); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_KEYIN, options.word.value, ELS_CMD_BIG_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyImportPuk_Async, MCUXCLELS_STATUS_OK_WAIT); +} +#endif /* MCUXCL_FEATURE_ELS_PUK_INTERNAL */ + +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_handleKeyExportError(uint8_t *pOutput, size_t keyLength, mcuxClEls_InterruptOptionEn_t interrupt_state_old) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_handleKeyExportError, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetIntFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + + /* Clear the interrupt state */ + mcuxClEls_InterruptOptionRst_t interrupt_options_1; + interrupt_options_1.bits.elsint = MCUXCLELS_ELS_RESET_CLEAR; + // no return value check in this call since mcuxClEls_ResetIntFlags always returns OK + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetIntFlags(interrupt_options_1)); + + /* Restore the ELS interrupt settings */ + // no return value check in this call since mcuxClEls_SetIntEnableFlags always returns OK + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_SetIntEnableFlags(interrupt_state_old)); + + /* clear the memory to which the key was exported */ + // no return value check in this call since MCUXCLELS_STATUS_SW_FAULT gets returned anyway + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set(pOutput, 0x00, keyLength, keyLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_handleKeyExportError, MCUXCLELS_STATUS_SW_FAULT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_KeyExport_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_KeyExport_Async( + mcuxClEls_KeyIndex_t wrappingKeyIdx, + mcuxClEls_KeyIndex_t exportKeyIdx, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_KeyExport_Async); + + /* Key indices out of bounds or the source key pointer is NULL although the key format indicates that it should be imported from memory */ + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_KeyExport_Async, wrappingKeyIdx >= ELS_KS_CNT || exportKeyIdx >= ELS_KS_CNT); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + /* ELS KEYOUT */ + mcuxClEls_setKeystoreIndex0(wrappingKeyIdx); + mcuxClEls_setKeystoreIndex1(exportKeyIdx); + mcuxClEls_setOutput_fixedSize(pOutput); + + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetIntEnableFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags)); + + /* Save current ELS interrupts state */ + mcuxClEls_InterruptOptionEn_t interrupt_state; + + MCUX_CSSL_FP_FUNCTION_CALL(status_get, mcuxClEls_GetIntEnableFlags(&interrupt_state)); + + if(MCUXCLELS_STATUS_OK != status_get) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_SW_FAULT); + } + + /* Disable ELS interrupts */ + mcuxClEls_InterruptOptionEn_t interrupt_state_new = interrupt_state; + interrupt_state_new.bits.elsint = MCUXCLELS_ELS_INTERRUPT_DISABLE; + + MCUX_CSSL_FP_FUNCTION_CALL(status_set, mcuxClEls_SetIntEnableFlags(interrupt_state_new)); + + if(MCUXCLELS_STATUS_OK != status_set) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_SW_FAULT); + } + + + /* Start KEYOUT command */ + mcuxClEls_startCommand(ID_CFG_ELS_CMD_KEYOUT, 0U, ELS_CMD_BIG_ENDIAN); + + + + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + + /* Wait for operation ELS KEYOUT */ + MCUX_CSSL_FP_FUNCTION_CALL(status_wait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_KEEP)); // flags not cleared because the error is caught in the wait for operation after this function exits + + if(MCUXCLELS_STATUS_OK != status_wait) + { + // no return value check in this call since mcuxClEls_SetIntEnableFlags always returns OK + // In case of interrupt driven operation the error will be caught by the interrupt handler since re-enabling the interrupt when ELS_IRQ is set will immediately trigger an interrupt + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_SetIntEnableFlags(interrupt_state)); + + // OK_WAIT is returned here so that the error can be captured by the wait for operation following this function + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_OK_WAIT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags)); + } + + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyImport_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags)); + + /* Save key properties */ + mcuxClEls_KeyProp_t key_properties; + + MCUX_CSSL_FP_FUNCTION_CALL(status_keyprop, mcuxClEls_GetKeyProperties(exportKeyIdx, &key_properties)); + + if(MCUXCLELS_STATUS_OK != status_keyprop) + { + // no return value check in this call since mcuxClEls_SetIntEnableFlags always returns OK + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_SetIntEnableFlags(interrupt_state)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_SW_FAULT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags)); + } + + size_t key_length = (key_properties.bits.ksize == MCUXCLELS_KEYPROPERTY_KEY_SIZE_128) ? MCUXCLELS_RFC3394_CONTAINER_SIZE_128 : MCUXCLELS_RFC3394_CONTAINER_SIZE_256; + + /* ELS KDELETE */ + MCUX_CSSL_FP_FUNCTION_CALL(status_delete, mcuxClEls_KeyDelete_Async(exportKeyIdx)); + + if(MCUXCLELS_STATUS_OK_WAIT != status_delete) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, + mcuxClEls_handleKeyExportError(pOutput, key_length, interrupt_state), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + + /* wait for ELS KDELETE */ + MCUX_CSSL_FP_FUNCTION_CALL(status_wait1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if(MCUXCLELS_STATUS_OK != status_wait1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, + mcuxClEls_handleKeyExportError(pOutput, key_length, interrupt_state), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + + /* ELS KEYIN */ + mcuxClEls_KeyImportOption_t import_options; + import_options.word.value = 0U; + import_options.bits.kfmt = MCUXCLELS_KEYIMPORT_KFMT_RFC3394; + + MCUX_CSSL_FP_FUNCTION_CALL(status_import, + mcuxClEls_KeyImport_Async( + import_options, + pOutput, + key_length, + wrappingKeyIdx, + exportKeyIdx + )); + + if(MCUXCLELS_STATUS_OK_WAIT != status_import) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, + mcuxClEls_handleKeyExportError(pOutput, key_length, interrupt_state), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + + /* wait for ELS KEYIN */ + MCUX_CSSL_FP_FUNCTION_CALL(status_wait2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if(MCUXCLELS_STATUS_OK != status_wait2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, + mcuxClEls_handleKeyExportError(pOutput, key_length, interrupt_state), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + + /* Restore ELS interrupt state - will trigger an interrupt immediately if interrupt is enabled since ELS_IRQ is expected to be set at this point */ + MCUX_CSSL_FP_FUNCTION_CALL(status_set1, mcuxClEls_SetIntEnableFlags(interrupt_state)); + if(MCUXCLELS_STATUS_OK != status_set1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_SW_FAULT); + } + + + /* Exit function */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_KeyExport_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +/** Exports the properties of the keys stored in the ELS internal keystore */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_GetKeyProperties) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_GetKeyProperties( + mcuxClEls_KeyIndex_t keyIdx, + mcuxClEls_KeyProp_t * pKeyProp + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_GetKeyProperties); + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_GetKeyProperties, (ELS_KS_CNT <= keyIdx)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetKeyProperties, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS("Sfr offset from address") + pKeyProp->word.value = ((const volatile uint32_t *) (&MCUXCLELS_SFR_READ(ELS_KS0)))[keyIdx]; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_GetKeyProperties, MCUXCLELS_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Rng.c b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Rng.c new file mode 100644 index 000000000..a88da21cd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClEls/src/mcuxClEls_Rng.c @@ -0,0 +1,519 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClEls_Rng.c + * @brief ELS implementation for random number generation. + * This file implements the functions declared in mcuxClEls_Rng.h. + */ + +#include +#include +#include // Implement mcuxClEls interface "Rng" +#include +#include +#include +#include +#include +#include +#include + +#define RANDOM_BIT_ARRAY_SIZE 4U + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +uint32_t mcuxClEls_rng_drbg_block_counter = 0u; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + +// Command name change -- should move to top level platform header +#ifndef ID_CFG_ELS_CMD_RND_REQ +#define ID_CFG_ELS_CMD_RND_REQ ID_CFG_ELS_CMD_DRBG_REQ +#endif + +// Utility code of mcuxClEls implementation for PRNG access + +/** + * Gets a pseudo-random 32-bit integer from the ELS PRNG. + */ +static inline uint32_t els_getPRNGWord( + void) +{ + return MCUXCLELS_SFR_READ(ELS_PRNG_DATOUT); +} + +// Implementation of mcuxClEls interface "Rng" + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgRequest_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequest_Async( + uint8_t * pOutput, + size_t outputLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgRequest_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Rng_DrbgRequest_Async, (MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE > outputLength) || + (MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE < outputLength) || + (0U != outputLength % 4U)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgRequest_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING + /* Increment drbg_block_counter. If the counter overflowed, the interrupt handler will + * reseed the DRBG and reset the counter after the upcoming ELS operation. */ + uint32_t counter_increase = MCUXCLELS_RNG_DRBG_DRBGREQUEST_INCREASE(outputLength); + mcuxClEls_rng_drbg_block_counter += counter_increase; +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ + + + mcuxClEls_setOutput(pOutput, outputLength); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_RND_REQ, 0U, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgRequest_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +#ifdef MCUXCL_FEATURE_ELS_RND_RAW +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgRequestRaw_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgRequestRaw_Async( + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgRequestRaw_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgRequestRaw_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setOutput_fixedSize(pOutput); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_RND_REQ, MCUXCLELS_RNG_RND_REQ_RND_RAW, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgRequestRaw_Async, MCUXCLELS_STATUS_OK_WAIT); +} +#endif /* MCUXCL_FEATURE_ELS_RND_RAW */ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgTestInstantiate_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestInstantiate_Async( + uint8_t const * pEntropy) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgTestInstantiate_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestInstantiate_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0_fixedSize(pEntropy); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_INSTANTIATE, ELS_CMD_LITTLE_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestInstantiate_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgTestExtract_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestExtract_Async( + uint8_t * pOutput, + size_t outputLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgTestExtract_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Rng_DrbgTestExtract_Async, (MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE > outputLength) || + (MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MAX_SIZE < outputLength) || + (0U != outputLength % 4U)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestExtract_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setOutput(pOutput, outputLength); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_EXTRACT, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestExtract_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgTestAesEcb_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesEcb_Async( + uint8_t const * pDataKey, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgTestAesEcb_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestAesEcb_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput1_fixedSize(pDataKey); + mcuxClEls_setOutput_fixedSize(pOutput); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_ECB, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestAesEcb_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_DrbgTestAesCtr_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_DrbgTestAesCtr_Async( + uint8_t const * pData, + size_t dataLength, + uint8_t const * pIvKey, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_DrbgTestAesCtr_Async); + + MCUXCLELS_INPUT_PARAM_CHECK_PROTECTED(mcuxClEls_Rng_DrbgTestAesCtr_Async, (0U != (dataLength % 16U)) || (0U == dataLength)); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestAesCtr_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0(pData, dataLength); + mcuxClEls_setInput1_fixedSize(pIvKey); + mcuxClEls_setOutput_fixedSize(pOutput); + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DRBG_TEST, MCUXCLELS_RNG_DRBG_TEST_MODE_AES_CTR, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_DrbgTestAesCtr_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_Dtrng_ConfigLoad_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigLoad_Async( + uint8_t const * pInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_Dtrng_ConfigLoad_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_Dtrng_ConfigLoad_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0_fixedSize(pInput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DTRNG_CFG_LOAD, 0U, ELS_CMD_LITTLE_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_Dtrng_ConfigLoad_Async, MCUXCLELS_STATUS_OK_WAIT); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async( + uint8_t const * pInput, + uint8_t * pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_setInput0_fixedSize(pInput); + mcuxClEls_setOutput_fixedSize(pOutput); + mcuxClEls_startCommand(ID_CFG_ELS_CMD_DTRNG_EVAL, 0U, ELS_CMD_LITTLE_ENDIAN); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Rng_Dtrng_ConfigEvaluate_Async, MCUXCLELS_STATUS_OK_WAIT); +} + +#ifdef MCUXCL_FEATURE_ELS_PRND_INIT +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Prng_Init_Async) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_Init_Async( + void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Prng_Init_Async); + + /* ELS SFRs are not cached => Tell SW to wait for ELS to come back from BUSY state before modifying the SFRs */ + if (mcuxClEls_isBusy()) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_Init_Async, MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT); + } + + mcuxClEls_startCommand(ID_CFG_ELS_CMD_RND_REQ, MCUXCLELS_RNG_RND_REQ_PRND_INIT, ELS_CMD_LITTLE_ENDIAN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_Init_Async, MCUXCLELS_STATUS_OK_WAIT); +} +#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Prng_GetRandomWord) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandomWord( + uint32_t * pWord) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Prng_GetRandomWord); + + *pWord = els_getPRNGWord(); + + /* check if enough entropy is available */ + if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR)) + { + /* clear ELS error flags */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetErrorFlags()); /* always returns MCUXCLELS_STATUS_OK. */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_GetRandomWord, MCUXCLELS_STATUS_HW_PRNG, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetErrorFlags)); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_GetRandomWord, MCUXCLELS_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Prng_GetRandom) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Prng_GetRandom( + uint8_t * pOutput, + size_t outputLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Prng_GetRandom); + + uint8_t * bytePtr = pOutput; + uint8_t * const pOutputEnd = pOutput + outputLength; + + /* Fetch one word of PRNG and fill the leading "not word aligned" bytes */ + if (0u != ((uint32_t) bytePtr & 0x03u)) + { + uint32_t randomWord = els_getPRNGWord(); + do + { + *bytePtr = (uint8_t) (randomWord & 0xFFu); + bytePtr += 1u; + randomWord >>= 8u; + } while ((0u != ((uint32_t) bytePtr & 0x03u)) && (pOutputEnd > bytePtr)); + } + + /* Fill the specified buffer wordwise */ + uint8_t * const pOutputWordEnd = (uint8_t*) ((uint32_t) pOutputEnd & 0xFFFFFFFCu); + while (pOutputWordEnd > bytePtr) + { + mcuxClMemory_StoreLittleEndian32(bytePtr, els_getPRNGWord()); + bytePtr += 4; + } + + /* Fetch one word of PRNG and fill the remaining "less than one word" bytes */ + if (pOutputEnd > bytePtr) + { + uint32_t randomWord = els_getPRNGWord(); + do + { + *bytePtr = (uint8_t) (randomWord & 0xFFu); + bytePtr += 1u; + randomWord >>= 8u; + } while (pOutputEnd > bytePtr); + } + + /* check if enough entropy is available */ + if (MCUXCLELS_IS_ERROR_BIT_SET(MCUXCLELS_SFR_ERR_STATUS_PRNG_ERR)) + { + /* clear ELS error flags */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetErrorFlags()); /* always returns MCUXCLELS_STATUS_OK. */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_GetRandom, MCUXCLELS_STATUS_HW_PRNG, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetErrorFlags)); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Prng_GetRandom, MCUXCLELS_STATUS_OK); +} + +#ifdef MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Dtrng_IterativeReseeding_Reseed) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_Reseed(const uint8_t *pDtrngConfig) +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Dtrng_IterativeReseeding_Reseed, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_Dtrng_ConfigLoad_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) + ); + + /* Reset the counter */ + mcuxClEls_rng_drbg_block_counter = 0u; + + uint8_t keyBuffer[MCUXCLELS_HMAC_PADDED_KEY_SIZE] = {0}; + uint8_t unusedData[MCUXCLELS_HMAC_OUTPUT_SIZE] = {0}; + uint8_t emptyMsg[32U] = {0}; + + /* Prepare the options for the HMAC command which is called further down */ + mcuxClEls_HmacOption_t hmac_options = { + .bits = { + .extkey = MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE + } + }; + + /* Wait for Operation (to avoid crashing a running operation). */ + MCUX_CSSL_FP_FUNCTION_CALL(status_wait1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + /* Run DTRNG_CFG_LOAD procedure */ + MCUX_CSSL_FP_FUNCTION_CALL(status_dtrng_configLoad1, mcuxClEls_Rng_Dtrng_ConfigLoad_Async(pDtrngConfig)); + if(MCUXCLELS_STATUS_OK_WAIT != status_dtrng_configLoad1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + MCUX_CSSL_FP_FUNCTION_CALL(status_wait2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + /* Request DRBG data for the HMAC Key */ + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(status_drbgRequest1, mcuxClEls_Rng_DrbgRequest_Async(keyBuffer, MCUXCLELS_HMAC_PADDED_KEY_SIZE)); + if(MCUXCLELS_STATUS_OK_WAIT != status_drbgRequest1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + + MCUX_CSSL_FP_FUNCTION_CALL(status_wait3, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait3) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + for(uint32_t j = 0; j < (MCUXCLELS_RNG_DRBG_ITERATIVE_SEEDING_ITERATIONS - 1u); j++) { + /* Run DTRNG_CFG_LOAD procedure */ + MCUX_CSSL_FP_FUNCTION_CALL(status_dtrng_configLoad2, mcuxClEls_Rng_Dtrng_ConfigLoad_Async(pDtrngConfig)); + if(MCUXCLELS_STATUS_OK_WAIT != status_dtrng_configLoad2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + MCUX_CSSL_FP_FUNCTION_CALL(status_wait4, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait4) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + /* Run HMAC command with external key: + key = keyBuffer (the DRBG output) + message = 32 bytes of 0 + output goes into unusedData (array on stack) + */ + MCUX_CSSL_FP_FUNCTION_CALL(status_hmac, mcuxClEls_Hmac_Async( + hmac_options, + 0U, + keyBuffer, + emptyMsg, + 32U, + unusedData)); + if (MCUXCLELS_STATUS_OK_WAIT != status_hmac) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + MCUX_CSSL_FP_FUNCTION_CALL(status_wait5, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait5) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + + /* Run DRBG_REQ procedure */ + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(status_drbgRequest2, mcuxClEls_Rng_DrbgRequest_Async(keyBuffer, MCUXCLELS_HMAC_PADDED_KEY_SIZE)); + if(MCUXCLELS_STATUS_OK_WAIT != status_drbgRequest2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + + MCUX_CSSL_FP_FUNCTION_CALL(status_wait6, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_STATUS_OK != status_wait6) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_SW_FAULT); + } + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_Dtrng_ConfigLoad_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) + ); + } + + MCUXCLMEMORY_FP_MEMORY_CLEAR(keyBuffer,MCUXCLELS_HMAC_PADDED_KEY_SIZE); + + + MCUXCLMEMORY_FP_MEMORY_CLEAR(unusedData,MCUXCLELS_HMAC_OUTPUT_SIZE); + + + /* No errors if we have reached this point */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_Reseed, MCUXCLELS_STATUS_OK); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed) +MCUXCLELS_API MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClEls_Status_t) mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed(const uint8_t *pDtrngConfig) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed); + + /* Check if the block counter has overflowed, and if so, call iterative reseeding procedure. */ + if(MCUXCLELS_RNG_DRBG_BLOCK_COUNTER_THRESHOLD <= mcuxClEls_rng_drbg_block_counter) + { + /* Back up interrupt enable flags */ + mcuxClEls_InterruptOptionEn_t interrupt_getter; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_GetIntEnableFlags(&interrupt_getter)); + + /* Set interrupt enable flags to DISABLE */ + mcuxClEls_InterruptOptionEn_t interrupt_setter = {0}; + interrupt_setter.bits.elsint = MCUXCLELS_ELS_INTERRUPT_DISABLE; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_SetIntEnableFlags(interrupt_setter)); + + /* Call function for iterative seeding of the DTRNG */ + MCUX_CSSL_FP_FUNCTION_CALL(status_itReseeding, mcuxClEls_Dtrng_IterativeReseeding_Reseed(pDtrngConfig)); + + /* Clear interrupt status for the current interrupt before restoring interrupt enable flags to + * mark this interrupt as handled and ensure that it is not handled again. */ + mcuxClEls_InterruptOptionRst_t interrupt_clear = {0}; + interrupt_clear.bits.elsint = MCUXCLELS_ELS_RESET_CLEAR; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_ResetIntFlags(interrupt_clear)); + + /* Restore interrupt enable flags */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClEls_SetIntEnableFlags(interrupt_getter)); + + /* Check error code of iterative seeding function */ + if(MCUXCLELS_STATUS_OK != status_itReseeding) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed, MCUXCLELS_STATUS_SW_FAULT); + } + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetIntEnableFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Dtrng_IterativeReseeding_Reseed), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_ResetIntFlags), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_SetIntEnableFlags)); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClEls_Dtrng_IterativeReseeding_CheckAndReseed, MCUXCLELS_STATUS_OK); +} + +#endif /* MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Helper.h new file mode 100644 index 000000000..dba305686 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Helper.h @@ -0,0 +1,81 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_ELS_HELPER_H_ +#define MCUXCLEXAMPLE_ELS_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +/** + * Enable and reset ELS via mcuxClEls_Enable_Async and mcuxClEls_Reset_Async. + * [in] options: Indicating whether any running ELS operations shall be canceled + * MCUXCLELS_RESET_DO_NOT_CANCEL or MCUXCLELS_RESET_CANCEL + **/ +static inline bool mcuxClExample_Els_Init(mcuxClEls_ResetOption_t options) +{ + /* Enable ELS */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Enable_Async()); // Enable the ELS. + // mcuxClEls_Enable_Async is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Enable_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Reset ELS */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Reset_Async(options)); + // mcuxClEls_Reset_Async is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Reset_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Reset_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + return true; +} + +/** + * Disable ELS via mcuxClEls_Disable. + */ +static inline bool mcuxClExample_Els_Disable(void) +{ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Disable()); // Disable the ELS. + // mcuxClEls_Disable is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Disable) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + return true; +} + +#endif /* MCUXCLEXAMPLE_ELS_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Key_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Key_Helper.h new file mode 100644 index 000000000..906884479 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_ELS_Key_Helper.h @@ -0,0 +1,83 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_ELS_KEY_HELPER_H_ +#define MCUXCLEXAMPLE_ELS_KEY_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +/** + * Delete keyslot via mcuxClEls_KeyDelete_Async. + * [in] keyIdx: The index of the key to be deleted + **/ +static inline bool mcuxClExample_Els_KeyDelete(mcuxClEls_KeyIndex_t keyIdx) +{ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_KeyDelete_Async(keyIdx)); + // mcuxClEls_KeyDelete_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; // Expect that no error occurred, meaning that the mcuxClEls_KeyDelete_Async operation was started. + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_KeyDelete_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + return true; +} + +/** + * Delete all keyslot via mcuxClEls_Reset_Async. + **/ +static inline bool mcuxClExample_Els_KeyDeleteAll(void) +{ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Reset_Async(0U)); + // mcuxClEls_Reset_Async is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Reset_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Reset_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + return true; +} + + +/* + * Check only if the mcuxClEls_KeyDelete_Async is defined "because mcuxClEls_KeyProvision_Async will be always defined" + * via CL library or via the TEST OS + * Function that loads a known key into the ELS key store + * [in] helperKeyIdx: The index of the helper key + * [in] targetKeyIdx: The key index at which the target key shall be loaded + * [in] targetKeyProperties: The target properties of the key + * [in] pKey: Pointer to the key to be loaded +*/ +#define ELS_RFC_PADDING_LENGTH 16U + +#endif /* MCUXCLEXAMPLE_ELS_KEY_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Key_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Key_Helper.h new file mode 100644 index 000000000..05ea8f232 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Key_Helper.h @@ -0,0 +1,102 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_KEY_HELPER_H_ +#define MCUXCLEXAMPLE_KEY_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +/** + * Load key via mcuxClKey_loadMemory or mcuxClKey_loadCopro according to the key_loading_option parameter. + * [in] pSession: Pointer to the session handle. + * [in,out] pKey: Pointer to the key handle. + * [in] type: Define which key type shall be initialized + * [in] pData: Provide pointer to source data of the key + * [in] keyDataLength: Number of bytes available in the pData buffer. + * [in] key_properties: Pointer to the requested key properties of the destination key. Will be set in key->container.pAuxData + * [in] dst: if MCUXCLEXAMPLE_CONST_EXTERNAL_KEY, Pointer to dstData, if MCUXCLEXAMPLE_CONST_INTERNAL_KEY, Pointer to dstSlot value + * [in] key_loading_option:0 = external key, 1 = internal key + **/ +#define MCUXCLEXAMPLE_CONST_EXTERNAL_KEY 0U +#define MCUXCLEXAMPLE_CONST_INTERNAL_KEY 1U +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClExample_Key_Init_And_Load) +static inline bool mcuxClExample_Key_Init_And_Load(mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t pKey, + mcuxClKey_Type_t type, + mcuxCl_Buffer_t pData, + uint32_t keyDataLength, + mcuxClEls_KeyProp_t * key_properties, + uint32_t * dst, + uint8_t key_loading_option) +{ + /* Init the key. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_init(pSession, + pKey, + type, + pData, + keyDataLength)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_init) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Set the key properties. */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_setKeyproperties(pKey, + key_properties)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_setKeyproperties) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + if(MCUXCLEXAMPLE_CONST_EXTERNAL_KEY == key_loading_option) + { + /* load key into destination memory buffer */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_loadMemory( + /* mcuxClSession_Handle_t pSession: */ pSession, + /* mcuxClKey_Handle_t key: */ pKey, + /* uint32_t * dstData: */ dst)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadMemory) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + } + else + { + /* load key into destination key slot of coprocessor (key_slot = '*dst') */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClKey_loadCopro( + /* mcuxClSession_Handle_t pSession: */ pSession, + /* mcuxClKey_Handle_t key: */ pKey, + /* uint32_t dstSlot: */ *dst)); + + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_loadCopro) != token) || (MCUXCLKEY_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + } + return true; +} + +#endif /* MCUXCLEXAMPLE_KEY_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RFC3394_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RFC3394_Helper.h new file mode 100644 index 000000000..210da1b85 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RFC3394_Helper.h @@ -0,0 +1,258 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_RFC3394_HELPER_H_ +#define MCUXCLEXAMPLE_RFC3394_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +/** + * Function that performs RFC3394 key wrapping. + * @retval true Wrapping successful. + * @retval false Wrapping error. */ +static inline bool mcuxClExample_rfc3394_wrap( + const uint8_t * pInput, //< pointer to key to be wrapped + size_t inputLength, //< length of key to be wrapped in bytes + const uint8_t * pKek_in, //< pointer to key wrapping key + mcuxClEls_KeyIndex_t keyIdx, //< keyslot index of key wrapping key + uint8_t extkey, //< 0-use key stored internally at keyIdx as wrapping key, 1-use external pKek_in as wrapping key + size_t kekLength, //< length of key wrapping key in bytes + uint8_t * pOutput, //< pointer to output buffer, size has to be inputLength + 16 bytes + mcuxClEls_KeyProp_t properties //< properties of the key to be wrapped +) +{ + uint32_t concat[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u }; + + uint32_t input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u }; + uint8_t pKek[MCUXCLELS_CIPHER_KEY_SIZE_AES_256] = { 0u }; + + if (extkey == MCUXCLELS_CIPHER_EXTERNAL_KEY) + { + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy (pKek, + pKek_in, + kekLength, + kekLength)); + + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return false; + } + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + } + + // Intermediate state is stored in pOutput as it is large enough + + // initialize buffer + concat[0] = 0xA6A6A6A6u; // first half of concat is the A from the standard, initialized to RFC3394 IV + concat[1] = 0xA6A6A6A6u; + concat[2] = properties.word.value; // second half of concat is R(input)/B(output), first R consists of properties... + concat[3] = 0x00000000u; // ... and ELS padding (zeros) + concat[2] = (concat[2] << 24u) | (concat[2] >> 24u) | ((concat[2] & 0x0000ff00u) << 8u) | ((concat[2] >> 8u) & 0x0000ff00u); // swap endianness + + // initialize ELS encryption parameters + mcuxClEls_CipherOption_t cipher_options; + cipher_options.word.value = 0; + cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB; + cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; + cipher_options.bits.extkey = extkey; + + // input has to be multiple of 64 bits + if (inputLength % sizeof(uint64_t) != 0u) + { + return false; + } + + uint32_t *pSource = (uint32_t*) pInput; + uint32_t *pDest = (uint32_t*) pOutput; + uint32_t std_n = inputLength/sizeof(uint64_t) + 1; // n value from standard + for(size_t jdx = 0u; jdx < 6u; jdx++) + { + for(size_t idx = 0u; idx < std_n; idx++) + { + input[0]=concat[0]; + input[1]=concat[1]; + input[2]=concat[2]; + input[3]=concat[3]; + + // Encrypt concatenated A and chunk to be processed + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( + cipher_options, + keyIdx, + pKek, + kekLength, + (uint8_t*) input, + MCUXCLELS_CIPHER_BLOCK_SIZE_AES, + NULL, + (uint8_t*) concat)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Write out processed key chunk + pDest[2u*idx + 2u] = concat[2u]; + pDest[2u*idx + 3u] = concat[3u]; + + if( idx == std_n - 1u) + { + // Load next key chunk + concat[2u] = pDest[2u]; + concat[3u] = pDest[3u]; + pSource = pDest + 4; + } + else + { + // Load next key chunk + concat[2u] = pSource[2u*idx + 0u]; + concat[3u] = pSource[2u*idx + 1u]; + } + + // XOR round constant into A + uint32_t gdx = std_n * jdx + (idx+1); // all values should fit into a uint32_t + gdx = (gdx << 24u) | (gdx >> 24u) | ((gdx & 0x0000ff00u) << 8u) | ((gdx >> 8u) & 0x0000ff00u); // swap endianness + concat[1u] ^= gdx; + } + } + // Write out processed key chunk + pDest[0u] = concat[0u]; + pDest[1u] = concat[1u]; + + return true; +} + +/** + * Function that performs RFC3394 key unwrapping. + * @retval true Unwrapping successful. + * @retval false Unwrapping error. */ +static inline bool mcuxClExample_rfc3394_unwrap( + const uint8_t * pInput, //< pointer to rfc3394 blob to be wrapped + size_t inputLength, //< length of key the rfc3394 blob in bytes + const uint8_t * pKek_in, //< pointer to key wrapping key + mcuxClEls_KeyIndex_t keyIdx, //< keyslot index of key wrapping key + uint8_t extkey, //< 0-use key stored internally at keyIdx as wrapping key, 1-use external pKek_in as wrapping key + size_t kekLength, //< length of key wrapping key in bytes + uint8_t * pOutput //< pointer to output buffer, size has to inputLength - 8 bytes, contents will be properties|zeros|key +) +{ + uint32_t concat[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u }; + + uint32_t input[MCUXCLELS_CIPHER_BLOCK_SIZE_AES/sizeof(uint32_t)] = { 0u }; + uint8_t pKek[MCUXCLELS_CIPHER_KEY_SIZE_AES_256] = { 0u }; + + if (extkey == MCUXCLELS_CIPHER_EXTERNAL_KEY) + { + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(token, mcuxClMemory_copy (pKek, + pKek_in, + kekLength, + kekLength)); + + if (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) != token) + { + return false; + } + + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + } + + // initialize buffer + concat[0] = ((uint32_t*) pInput)[0]; // first half of concat is the A from the standard, to first chunk of input + concat[1] = ((uint32_t*) pInput)[1]; + + // initialize ELS encryption parameters + mcuxClEls_CipherOption_t cipher_options; + cipher_options.word.value = 0; + cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB; + cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_DECRYPT; + cipher_options.bits.extkey = extkey; + + // input has to be multiple of 64 bits + if (inputLength % sizeof(uint64_t) != 0u) + { + return false; + } + + + uint32_t std_n = inputLength/sizeof(uint64_t) - 1; // n value from standard + uint32_t *pSource = ((uint32_t*) pInput ) + 2u; // skip first 64 bits + uint32_t *pDest = ((uint32_t*) pOutput) + 0u; + for(size_t jdx = 6u; jdx > 0u; jdx--) + { + for(size_t idx = std_n; idx > 0u; idx--) + { + // Load next key chunk + concat[2u] = pSource[2u*(idx-1) + 0u]; + concat[3u] = pSource[2u*(idx-1) + 1u]; + + // XOR round constant into A + uint32_t gdx = std_n * (jdx-1u) + idx; // all values should fit into a uint32_t + gdx = (gdx << 24u) | (gdx >> 24u) | ((gdx & 0x0000ff00u) << 8u) | ((gdx >> 8u) & 0x0000ff00u); // swap endianness + concat[1u] ^= gdx; + + input[0]=concat[0]; + input[1]=concat[1]; + input[2]=concat[2]; + input[3]=concat[3]; + + // Decrypt concatenated A and chunk to be processed + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Cipher_Async( + cipher_options, + keyIdx, + pKek, + kekLength, + (uint8_t*) input, + MCUXCLELS_CIPHER_BLOCK_SIZE_AES, + NULL, + (uint8_t*) concat)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return false; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Write out processed key chunk + pDest[2u*(idx-1) + 0u] = concat[2u]; + pDest[2u*(idx-1) + 1u] = concat[3u]; + } + pSource = pDest; + } + pDest[0] = (pDest[0] << 24u) | (pDest[0] >> 24u) | ((pDest[0] & 0x0000ff00u) << 8u) | ((pDest[0] >> 8u) & 0x0000ff00u); // swap endianness + // Check padding + if((concat[0u] != 0xA6A6A6A6u) || (concat[1u] != 0xA6A6A6A6u)) + { + return false; + } + return true; +} + +#endif /* MCUXCLEXAMPLE_RFC3394_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RNG_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RNG_Helper.h new file mode 100644 index 000000000..e62f5c143 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_RNG_Helper.h @@ -0,0 +1,66 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_RNG_HELPER_H_ +#define MCUXCLEXAMPLE_RNG_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +// always allocate a minimum size buffer to avoid issues +// The size is given in bytes and allocated in words +#define MCUXCLEXAMPLE_ALLOCATE_RNG_CTXT(rngCtxLength) (rngCtxLength?((rngCtxLength + sizeof(uint32_t) - 1u) / sizeof(uint32_t)):1u) + + +/** + * Random data generator and Non-cryptographic PRNG initialization function via mcuxClRandom_init and mcuxClRandom_ncInit. + * [in] pSession Handle for the current CL session. + * [in] rngCtxLength Size (in bytes) of the RNG context need to be allocated based on the mode. + * [in] mode Mode of operation for random data generator. + **/ + +#define MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_RNG(pSession, rngCtxLength, mode) \ + uint32_t context[MCUXCLEXAMPLE_ALLOCATE_RNG_CTXT(rngCtxLength)] = {0}; \ + mcuxClRandom_Context_t pRng_ctx = (mcuxClRandom_Context_t)context; \ + \ + /* Initialize the RNG context */ \ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(randomInit_result, randomInit_token, mcuxClRandom_init(pSession, \ + pRng_ctx, \ + mode)); \ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init) != randomInit_token) || (MCUXCLRANDOM_STATUS_OK != randomInit_result)) \ + { \ + return MCUXCLEXAMPLE_STATUS_ERROR; \ + } \ + MCUX_CSSL_FP_FUNCTION_CALL_END(); \ + /* Initialize the PRNG */ \ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(pSession)); \ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) \ + { \ + return MCUXCLEXAMPLE_STATUS_ERROR; \ + } \ + MCUX_CSSL_FP_FUNCTION_CALL_END(); + +#define MCUXCLEXAMPLE_INITIALIZE_PRNG(session) \ + /* Initialize the PRNG */ \ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(prngInit_result, prngInit_token, mcuxClRandom_ncInit(session)); \ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncInit) != prngInit_token) || (MCUXCLRANDOM_STATUS_OK != prngInit_result)) \ + { \ + return MCUXCLEXAMPLE_STATUS_ERROR; \ + } \ + MCUX_CSSL_FP_FUNCTION_CALL_END(); + +#endif /* MCUXCLEXAMPLE_RNG_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Session_Helper.h b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Session_Helper.h new file mode 100644 index 000000000..8156793e9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClExample/inc/mcuxClExample_Session_Helper.h @@ -0,0 +1,83 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLEXAMPLE_SESSION_HELPER_H_ +#define MCUXCLEXAMPLE_SESSION_HELPER_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +/** + * Initialize Session via mcuxClSession_init. + * [in] pSession : Pointer to the session handle. + * [in] cpuWaLength : Size (in bytes) of the workarea for CPU operations. The size shall be a multiple of CPU wordsize. + * [in] pkcWaLength : Size (in bytes) of the workarea for PKC operations. The size shall be a multiple of CPU wordsize. + */ + +/* TODO: CLNS-5886 [DEV][Session][Example] enable size checking when allocating buffers and update example macros */ +#if 0 +#define MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength) ((cpuWaLength?cpuWaLength:(sizeof(uint32_t))) / (sizeof(uint32_t))) // always allocate a minimum size buffer to avoid issues +#define MCUXCLEXAMPLE_ALLOCATE_PKCWA(pkcWaLength) ((pkcWaLength?pkcWaLength:(sizeof(uint32_t))) / (sizeof(uint32_t))) // always allocate a minimum size buffer to avoid issues +#else +#define MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength) (cpuWaLength?cpuWaLength:1u) // always allocate a minimum size buffer to avoid issues +#define MCUXCLEXAMPLE_ALLOCATE_PKCWA(pkcWaLength) (pkcWaLength?pkcWaLength:1u) // always allocate a minimum size buffer to avoid issues +#endif + +#define MCUXCLEXAMPLE_ALLOCATE_AND_INITIALIZE_SESSION(pSession, cpuWaLength, pkcWaLength) \ + uint32_t cpuWaBuffer[MCUXCLEXAMPLE_ALLOCATE_CPUWA(cpuWaLength)]; \ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(si_status, token, mcuxClSession_init( \ + /* mcuxClSession_Handle_t session: */ pSession, \ + /* uint32_t * const cpuWaBuffer: */ cpuWaBuffer, \ + /* uint32_t cpuWaSize: */ cpuWaLength, \ + /* uint32_t * const pkcWaBuffer: */ (uint32_t *) PKC_RAM_ADDR, \ + /* uint32_t pkcWaSize: */ pkcWaLength \ + )); \ + /* mcuxClSession_init is a flow-protected function: Check the protection token and the return value */ \ + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_init) != token) || (MCUXCLSESSION_STATUS_OK != si_status)) \ + { \ + return false; \ + } \ + MCUX_CSSL_FP_FUNCTION_CALL_END(); + +/** + * Destroy Session and cleanup Session via mcuxClSession_cleanup and mcuxClSession_destroy + * [in] pSession: Pointer to the session handle. + **/ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClExample_Session_Clean) +static inline bool mcuxClExample_Session_Clean(mcuxClSession_Handle_t pSession) +{ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(cleanup_result, cleanup_token, mcuxClSession_cleanup(pSession)); + + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_cleanup) != cleanup_token || MCUXCLSESSION_STATUS_OK != cleanup_result) + { + return false; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(destroy_result, destroy_token, mcuxClSession_destroy(pSession)); + + if(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_destroy) != destroy_token || MCUXCLSESSION_STATUS_OK != destroy_result) + { + return false; + } + + MCUX_CSSL_FP_FUNCTION_CALL_END(); + return true; +} + +#endif /* MCUXCLEXAMPLE_SESSION_HELPER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal.h b/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal.h new file mode 100644 index 000000000..e6f37fbd2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal.h @@ -0,0 +1,186 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_Internal.h + * @brief Definitions and declarations of the *INTERNAL* layer of the + * @ref mcuxClHash component + */ + +#ifndef MCUXCLHASH_INTERNAL_H_ +#define MCUXCLHASH_INTERNAL_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/********************************************** + * Type declarations + **********************************************/ + /** + * @defgroup mcuxClHash_Internal_Types mcuxClHash_Internal_Types + * @brief Defines all internal types of the @ref mcuxClHash component + * @ingroup mcuxClHash_Types + * @{ + */ + +/** + * @brief Hash Context structure + * + * Maintains the state of a hash computation when using the streaming API. + * + * This structure only holds metadata, and the actual hash algorithm's state is part of the context but stored behind this structure. + * + * See #mcuxClHash_init for information about the streaming API. + */ +struct mcuxClHash_ContextDescriptor +{ + uint64_t processedLength[2]; + uint32_t unprocessedLength; + const mcuxClHash_AlgorithmDescriptor_t * algo; +}; + +#define MCUXCLHASH_CONTEXT_DATA_OFFSET (sizeof(mcuxClHash_ContextDescriptor_t)) ///< Offset of data buffers from the start of the context + + +/** + * @brief Hash one-shot skeleton function type + * + * This function will accumulate, pad, etc. the input message and then process it with the Hash core function (mcuxClHash_AlgoCore_t) + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHash_AlgoSkeleton_OneShot_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) (*mcuxClHash_AlgoSkeleton_OneShot_t)( + mcuxClSession_Handle_t session, + mcuxClHash_Algo_t algorithm, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize)); + +/** + * @brief Hash process skeleton function type + * + * This function will accumulate the input message and then process it with the Hash core function (mcuxClHash_AlgoEngine_t) + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHash_AlgoSkeleton_Process_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) (*mcuxClHash_AlgoSkeleton_Process_t)( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t context, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize)); + +/** + * @brief Hash multi-part skeleton function type + * + * This function will accumulate, padd, etc. the input message and then process it with the Hash core function (mcuxClHash_AlgoCore_t) + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHash_AlgoSkeleton_Finish_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) (*mcuxClHash_AlgoSkeleton_Finish_t)( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t context, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize)); + + +/** + * @brief Hash Algorithm structure + * + */ +struct mcuxClHash_AlgorithmDescriptor +{ + mcuxClHash_AlgoSkeleton_OneShot_t oneShotSkeleton; ///< One-shot hash skeleton function + uint32_t protection_token_oneShotSkeleton; ///< Protection token value for the used one-shot skeleton + mcuxClHash_AlgoSkeleton_Process_t processSkeleton; ///< Process hash skeleton function + uint32_t protection_token_processSkeleton; ///< Protection token value for the used process skeleton + mcuxClHash_AlgoSkeleton_Finish_t finishSkeleton; ///< Multi-part hash skeleton function + uint32_t protection_token_finishSkeleton; ///< Protection token value for the used multi-part skeleton + size_t blockSize; ///< Size of the block used by the hash algorithm + size_t hashSize; ///< Size of the output of the hash algorithm + size_t stateSize; ///< Size of the state used by the hash algorithm + uint32_t counterSize; ///< Size of the counter used by the hash algorithm + const void *pAlgorithmDetails; ///< Contains algorithm specific details not needed on API level +}; + +/**@}*/ + +/********************************************** + * Function declarations + **********************************************/ +/** + * @brief support bigger input length up to 2^128 bits + */ +static inline void mcuxClHash_processedLength_add(uint64_t *pLen128, uint32_t addLen) +{ + if (pLen128[0] > (0xffffffffffffffffu - addLen)) + { + pLen128[1] += 1u; + } + pLen128[0] += addLen; +} + +/** + * @brief support 128bit number compare + */ +static inline int mcuxClHash_processedLength_cmp(uint64_t *pLen128, uint64_t cmpLenHigh64, uint64_t cmpLenLow64) +{ + return pLen128[1] > cmpLenHigh64 ? 1 : (cmpLenHigh64 > pLen128[1] ? -1 : ((pLen128[0] > cmpLenLow64 ? 1 : (pLen128[0] == cmpLenLow64 ? 0 : -1)))); +} + +static inline uint32_t mcuxClHash_getContextWordSize(mcuxClHash_Algo_t algo) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Context size will never overflow.") + return (sizeof(mcuxClHash_ContextDescriptor_t) + algo->stateSize + algo->blockSize) / sizeof(uint32_t); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() +} + +/** + * @brief Returns the address of the state within the given context + * +*/ +static inline uint32_t *mcuxClHash_getStatePtr(mcuxClHash_Context_t pContext) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Context and offset are word-aligned") + return (uint32_t *)((uint8_t *)pContext + MCUXCLHASH_CONTEXT_DATA_OFFSET); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() +} + +/** + * @brief Returns the address of the unprocessed buffer within the given context + * + * @param[in] stateSize Byte size of the state includidng a potential mask + * +*/ +static inline uint32_t *mcuxClHash_getUnprocessedPtr(mcuxClHash_Context_t pContext) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Context, offset and all state sizes are word-aligned") + return (uint32_t *)((uint8_t *)pContext + MCUXCLHASH_CONTEXT_DATA_OFFSET + pContext->algo->stateSize); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() +} + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASH_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal_Memory.h b/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal_Memory.h new file mode 100644 index 000000000..bde5e2129 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/internal/mcuxClHash_Internal_Memory.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_Internal_Memory.h + * @brief Internal memory consumption definitions of the mcuxClHash component */ + +#ifndef MCUXCLHASH_INTERNAL_MEMORY_H_ +#define MCUXCLHASH_INTERNAL_MEMORY_H_ + +#include +#if defined(MCUXCL_FEATURE_HASH_HW_SM3) +#include +#endif /* defined(MCUXCL_FEATURE_HASH_SW_SM3) || defined(MCUXCL_FEATURE_HASH_HW_SM3) */ + +#if defined(MCUXCL_FEATURE_HASH_HW_SM3) +#define MCUXCLHASH_INTERNAL_WACPU_MAX MCUXCLHASHMODES_MAX(MCUXCLHASHMODES_INTERNAL_WACPU_MAX, MCUXCLOSCCASM3_WACPU_SIZE_SM3) +#define MCUXCLHASH_CONTEXT_MAX_SIZE_INTERNAL MCUXCLHASHMODES_MAX(MCUXCLHASHMODES_CONTEXT_MAX_SIZE_INTERNAL, MCUXCLOSCCASM3_CONTEXT_SIZE_SM3) +#else +#define MCUXCLHASH_INTERNAL_WACPU_MAX MCUXCLHASHMODES_INTERNAL_WACPU_MAX +#define MCUXCLHASH_CONTEXT_MAX_SIZE_INTERNAL MCUXCLHASHMODES_CONTEXT_MAX_SIZE_INTERNAL +#endif + +#endif /* MCUXCLHASH_INTERNAL_MEMORY_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash.h b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash.h new file mode 100644 index 000000000..9a380f740 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash.h + * @brief Top-level include file for the @ref mcuxClHash component + * + * This includes headers for all of the functionality provided by the @ref mcuxClHash component. + * + * @defgroup mcuxClHash mcuxClHash + * @brief Hash component + * + * The mcuxClHash component implements the Hash functionality supported by CLNS. + * + * An example of how to use the @ref mcuxClHash component can be found in /mcuxClHash/ex. + * + * The @ref mcuxClHash component supports interfaces to either hash a message in one shot + * (mcuxClHash_compute) or to hash it in parts (mcuxClHash_init, mcuxClHash_process, + * and mcuxClHash_finish). In case of hashing a message in parts, first an initialization + * has to be performed (mcuxClHash_init), followed by zero, one, or multiple updates + * (mcuxClHash_process), followed by a finalization (mcuxClHash_finish). The finalization + * generates the output data (digest) and destroys the context. After the finalization step, + * no further updates are possible. + * + * The targeted hash algorithm is selected by passing one of the offered algorithm mode + * descriptors (@ref mcuxClHash_Modes), which are listed in file mcuxClHash_Algorithms.h + * + * Note: In case the hashing functionality is based on a hardware co-processor, it might + * be necessary to initialize the co-processor, before it's use in the @ref mcuxClHash + * component. Please refer to the example for further information on this. + * + * */ + +#ifndef MCUXCLHASH_H_ +#define MCUXCLHASH_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#endif /* MCUXCLHASH_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Constants.h b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Constants.h new file mode 100644 index 000000000..9b4dda92a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Constants.h @@ -0,0 +1,51 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_Constants.h + * @brief Constants for use with the mcuxClHash component */ + +#ifndef MCUXCLHASH_CONSTANTS_H_ +#define MCUXCLHASH_CONSTANTS_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClHash_Constants mcuxClHash_Constants + * @brief Constants of @ref mcuxClHash component + * @ingroup mcuxClHash + * @{ + */ + +/** + * @defgroup MCUXCLHASH_STATUS_ MCUXCLHASH_STATUS_ + * @brief Return code definitions + * @ingroup mcuxClHash_Constants + * @{ + */ +#define MCUXCLHASH_STATUS_OK ((mcuxClHash_Status_t) 0x06662E03u) ///< Hash operation successful +#define MCUXCLHASH_STATUS_COMPARE_EQUAL ((mcuxClHash_Status_t) 0x06662E07u) ///< Hash operation and comparison of result successful +#define MCUXCLHASH_COMPARE_EQUAL MCUXCLHASH_STATUS_COMPARE_EQUAL ///< \deprecated Replaced by MCUXCLHASH_STATUS_COMPARE_EQUAL +#define MCUXCLHASH_STATUS_FAILURE ((mcuxClHash_Status_t) 0x06665330u) ///< Hash operation failed +#define MCUXCLHASH_FAILURE MCUXCLHASH_STATUS_FAILURE ///< \deprecated Replaced by MCUXCLHASH_STATUS_FAILURE +#define MCUXCLHASH_STATUS_INVALID_PARAMS ((mcuxClHash_Status_t) 0x066653F8u) ///< Hash function called with invalid parameters +#define MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK ((mcuxClHash_Status_t) 0x06665338u) ///< Export on state, for which a NON-multiple of the blocksize has been hashed +#define MCUXCLHASH_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK ///< \deprecated Replaced by MCUXCLHASH_STATUS_EXPORT_STATE_NOT_MULTIPLE_OF_BLOCK +#define MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL ((mcuxClHash_Status_t) 0x06668930u) ///< Hash operation succeeded, but comparison of result failed +#define MCUXCLHASH_COMPARE_NOT_EQUAL ((mcuxClHash_Status_t) 0x06668930u) ///< \deprecated Replaced by MCUXCLHASH_STATUS_COMPARE_NOT_EQUAL +#define MCUXCLHASH_STATUS_FULL ((mcuxClHash_Status_t) 0x0666538Eu) ///< Hash operation failed because the total input size exceeds the upper limit +#define MCUXCLHASH_STATUS_FAULT_ATTACK ((mcuxClHash_Status_t) 0x0666F0F0u) ///< Fault attack (unexpected behavior) detected +/**@}*/ + +/**@}*/ + +#endif /* MCUXCLHASH_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Functions.h b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Functions.h new file mode 100644 index 000000000..7774fa94b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Functions.h @@ -0,0 +1,192 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_Functions.h + * @brief Top-level API of the mcuxClHash component */ + +#ifndef MCUXCLHASH_FUNCTIONS_H_ +#define MCUXCLHASH_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClHash_Functions mcuxClHash_Functions + * @brief Defines all functions of @ref mcuxClHash + * @ingroup mcuxClHash + * @{ + */ + +/**********************************************************************/ +/* ONE-SHOT */ +/**********************************************************************/ + +/** + * @brief One-shot Hash computation function + * + * This function performs a hash computation over the input message \p pIn, using the hash function provided by the + * \p algorithm input parameter, in one shot. Up to 2^32 bytes of data can be hashed with this function. + * + * For example, to perform a SHA256 computation, the following needs to be + * provided: + * - SHA256 algorithm + * - Input data + * - Output hash buffer + * + * The input parameter \p session has to be initialized by the function mcuxClSession_init prior to + * calling this function. + * @if (MCUXCL_FEATURE_SESSION_HAS_RTF) + * Certain \ref mcuxClHashAlgorithms support maintaining a Runtime Fingerprint (RTF). + * Updating of the RTF has to be enabled/disabled by calling the mcuxClSession_setRtf function on the session + * prior to calling this function. + * @endif (MCUXCL_FEATURE_SESSION_HAS_RTF) + * + * @param[in/out] session Handle for the current CL session. + * @param[in] algorithm Hash algorithm that should be used during the computation. + * @param[in] pIn Pointer to the input buffer that contains the data + * that needs to be hashed. + * @param[in] inSize Number of bytes of data in the \p pIn buffer. + * @param[out] pOut Pointer to the output buffer where the computed hash + * value is written. + * @param[out] pOutSize Will be incremented by the number of bytes of data + * that have been written to the \p pOut buffer. + * + * @return status + * @retval MCUXCLHASH_STATUS_OK Hash operation successful + * @retval MCUXCLHASH_STATUS_FAILURE Error occured during Hash operation + * @retval MCUXCLHASH_STATUS_INVALID_PARAMS The provided function parameters do not fulfill requirements + * @retval MCUXCLHASH_STATUS_FAULT_ATTACK A fault attack was detected + * + * @implements{REQ_2245974} + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_compute) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_compute( + mcuxClSession_Handle_t session, + mcuxClHash_Algo_t algorithm, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize +); /* oneshot compute */ + + + +/**********************************************************************/ +/* MULTIPART */ +/**********************************************************************/ + +/** + * @brief Multi-part Hash initialization function + * + * This function performs the initialization for a multi-part hash operation. + * + * @param[in/out] session Handle for the current CL session. + * @param[out] pContext Hash context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] algorithm Hash algorithm that should be used during the + * computation operation. + * + * @return status + * @retval MCUXCLHASH_STATUS_OK Initialization successful + * @retval MCUXCLHASH_STATUS_FAILURE Error occurred during initialization function + * + * @implements{REQ_2207116} + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_init( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxClHash_Algo_t algorithm +); /* init */ + +/** + * @brief Multi-part Hash processing function + * + * This function performs the processing of (a part of) a data stream for a + * Hash operation. The algorithm to be used will be determined based on the + * context that is provided. + * + * @param[in/out] session Handle for the current CL session. + * @param[in/out] pContext Hash context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pIn Pointer to the input buffer that contains the data that + * needs to be processed. + * @param[in] inSize Number of bytes of data in the \p pIn buffer. + * + * @return status + * @retval MCUXCLHASH_STATUS_OK Hash operation successful + * @retval MCUXCLHASH_STATUS_FAILURE Error occurred during Hash operation + * @retval MCUXCLHASH_STATUS_INVALID_PARAMS The provided function parameters do not fulfill requirements + * @retval MCUXCLHASH_STATUS_FAULT_ATTACK A fault attack was detected + * + * @implements{REQ_2207116} + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_process( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize +); /* update */ + +/** + * @brief Multi-part Hash computation finalization function + * + * This function performs the finalization of a Hash computation operation. + * The algorithm to be used will be determined based on the context that is + * provided + * + * @param[in/out] session Handle for the current CL session. + * @param[in/out] pContext Hash context which is used to maintain the state and + * store other relevant information about the operation. + * @param[out] pOut Pointer to the output buffer where the computed hash + * value needs to be written. + * @param[out] pOutSize Will be incremented by the number of bytes of data + * that have been written to the \p pOut buffer. + * + * @return status + * @retval MCUXCLHASH_STATUS_OK Hash operation successful + * @retval MCUXCLHASH_STATUS_FAILURE Error occurred during Hash operation + * @retval MCUXCLHASH_STATUS_INVALID_PARAMS The provided function parameters do not fulfill requirements + * @retval MCUXCLHASH_STATUS_FAULT_ATTACK A fault attack was detected + * + * @implements{REQ_2207116} + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHash_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_finish( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize +); /* finalize compute */ + + + +/** + * @} + */ /* mcuxClHash_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASH_FUNCTIONS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_MemoryConsumption.h new file mode 100644 index 000000000..a349c6a7f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_MemoryConsumption.h @@ -0,0 +1,38 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClHash component */ + +#ifndef MCUXCLHASH_MEMORYCONSUMPTION_H_ +#define MCUXCLHASH_MEMORYCONSUMPTION_H_ + +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX (192u) ///< Defines the max workarea size required for mcuxClHash_compute +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_MAX MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_MAX ///< Defines the max workarea size required for mcuxClHash_compare +#define MCUXCLHASH_INIT_CPU_WA_BUFFER_SIZE (4u) ///< Defines the max workarea size required for mcuxClHash_init +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_MAX (4u) ///< Defines the max workarea size required for mcuxClHash_process +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX (192u) ///< Defines the max workarea size required for mcuxClHash_finish +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_MAX MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_MAX ///< Defines the max workarea size required for mcuxClHash_verify + +#define MCUXCLHASH_MAX_CPU_WA_BUFFER_SIZE (192u) ///< Defines the max workarea size required for this component + + +/****************************************************************************/ +/* Definitions of context sizes for the mcuxClHash multi-part functions. */ +/****************************************************************************/ + +#define MCUXCLHASH_CONTEXT_SIZE (392u) ///< Defines the maximum size a context might need. +#define MCUXCLHASH_CONTEXT_SIZE_IN_WORDS (392u / sizeof(uint32_t)) + + +#endif /* MCUXCLHASH_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Types.h b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Types.h new file mode 100644 index 000000000..8ae63773e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/inc/mcuxClHash_Types.h @@ -0,0 +1,86 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHash_Types.h + * @brief Type definitions for the mcuxClHash component + */ + +#ifndef MCUXCLHASH_TYPES_H_ +#define MCUXCLHASH_TYPES_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClHash_Types mcuxClHash_Types + * @brief Defines all types of the @ref mcuxClHash component + * @ingroup mcuxClHash + * @{ + */ + +/** + * @brief Hash mode/algorithm descriptor type + * + * This type captures all the information that the Hash interfaces need to + * know about a particular Hash mode/algorithm. + * + */ +typedef struct mcuxClHash_AlgorithmDescriptor mcuxClHash_AlgorithmDescriptor_t; + +/** + * @brief Hash mode/algorithm type + * + * This type is used to refer to a Hash mode/algorithm. + * + */ +typedef const mcuxClHash_AlgorithmDescriptor_t * const mcuxClHash_Algo_t; + + + +/** + * @brief Hash Context buffer type + * + * This type is used in the streaming interfaces to store the information + * about the current operation and the relevant internal state. + * + */ +typedef struct mcuxClHash_ContextDescriptor mcuxClHash_ContextDescriptor_t; + +/** + * @brief Hash Context type + * + * This type is used to refer to the Hash context. + * It needs to be placed at a 64 Bit-aligned address. + * + */ +typedef mcuxClHash_ContextDescriptor_t * const mcuxClHash_Context_t; + +/** + * @brief Hash Status type + * + * This type is used for hash return values: \ref mcuxClHashStatusValues + * + */ +typedef uint32_t mcuxClHash_Status_t; + +/**@}*/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASH_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_common.c b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_common.c new file mode 100644 index 000000000..7ad303db5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_common.c @@ -0,0 +1,65 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHash_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_init( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClHash_Context_t pContext, + mcuxClHash_Algo_t algorithm +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHash_init); + + pContext->unprocessedLength = 0u; + pContext->processedLength[0] = 0u; + pContext->processedLength[1] = 0u; + pContext->algo = algorithm; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClHash_init, MCUXCLHASH_STATUS_OK, MCUXCLHASH_STATUS_FAULT_ATTACK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHash_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_process( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHash_process); + + if((NULL == pContext->algo) || (NULL == pContext->algo->processSkeleton) +#if(1 == MCUX_CSSL_SC_USE_SW_LOCAL) + || (0u == pContext->algo->protection_token_processSkeleton) +#endif /* (1 == MCUX_CSSL_SC_USE_SW_LOCAL) */ + ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHash_process, MCUXCLHASH_STATUS_INVALID_PARAMS); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, pContext->algo->processSkeleton(session, pContext, pIn, inSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClHash_process, + result, + MCUXCLHASH_STATUS_FAULT_ATTACK, + pContext->algo->protection_token_processSkeleton); +} diff --git a/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_compute.c b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_compute.c new file mode 100644 index 000000000..812020f32 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_multipart_compute.c @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHash_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_finish( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHash_finish); + + if((NULL == pContext->algo) || (NULL == pContext->algo->finishSkeleton) +#if(1 == MCUX_CSSL_SC_USE_SW_LOCAL) + || (0u == pContext->algo->protection_token_finishSkeleton) +#endif /* (1 == MCUX_CSSL_SC_USE_SW_LOCAL) */ + ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHash_finish, MCUXCLHASH_STATUS_INVALID_PARAMS); + } + + /* Save protection token before context is cleared */ + MCUX_CSSL_FP_COUNTER_STMT(uint32_t token_finish = pContext->algo->protection_token_finishSkeleton); + + MCUX_CSSL_FP_FUNCTION_CALL(result, pContext->algo->finishSkeleton(session, + pContext, + pOut, + pOutSize + )); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClHash_finish, + result, + MCUXCLHASH_STATUS_FAULT_ATTACK, + token_finish); +} diff --git a/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_oneshot_compute.c b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_oneshot_compute.c new file mode 100644 index 000000000..f75bc4fe5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHash/src/mcuxClHash_api_oneshot_compute.c @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHash_compute) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHash_compute( + mcuxClSession_Handle_t session, + mcuxClHash_Algo_t algorithm, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHash_compute); + + /*Validate input parameters */ + if((NULL == algorithm) || (NULL == algorithm->oneShotSkeleton) +#if(1 == MCUX_CSSL_SC_USE_SW_LOCAL) + || (0u == algorithm->protection_token_oneShotSkeleton) +#endif /* (1 == MCUX_CSSL_SC_USE_SW_LOCAL) */ + ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHash_compute, MCUXCLHASH_STATUS_INVALID_PARAMS); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, algorithm->oneShotSkeleton (session, + algorithm, + pIn, + inSize, + pOut, + pOutSize + )); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClHash_compute, result, MCUXCLHASH_STATUS_FAULT_ATTACK, algorithm->protection_token_oneShotSkeleton); +} diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Core_els_sha2.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Core_els_sha2.h new file mode 100644 index 000000000..6b67b6f41 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Core_els_sha2.h @@ -0,0 +1,79 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Core_els_sha2.h + * @brief Internal definitions and declarations of the *CORE* layer dedicated to ELS + */ + +#ifndef MCUXCLHASHMODES_CORE_ELS_SHA2_H_ +#define MCUXCLHASHMODES_CORE_ELS_SHA2_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************** + * Type declarations + **********************************************************/ + +/** + * @brief Hash Core function type + * + * This function will process one or more blocks of the Hash algorithm + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHashModes_els_AlgoCore_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) (*mcuxClHashModes_els_AlgoCore_t)( + uint32_t options, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut)); + +/********************************************************** + * Function declarations + **********************************************************/ + +/** + * @brief ELS hash processing + * + * This function calls mcuxClEls_Hash_Async to call ELS to process a input data. Note + * it does not perform padding. This has to be done before calling the function. + * + * @param options ELS options + * @param in Pointer to the input message + * @param out Result of processed input data + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval MCUXCLHASH_STATUS_OK Hash operation successful + * @retval MCUXCLHASH_STATUS_FAILURE Error occured during Hash operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHashModes_els_core_sha2, mcuxClHashModes_els_AlgoCore_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_els_core_sha2( + uint32_t options, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASHMODES_CORE_ELS_SHA2_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal.h new file mode 100644 index 000000000..f59191288 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal.h @@ -0,0 +1,141 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Internal.h + * @brief Definitions and declarations of the *INTERNAL* layer of the + * @ref mcuxClHashModes component + */ + +#ifndef MCUXCLHASHMODES_INTERNAL_H_ +#define MCUXCLHASHMODES_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * CONSTANTS + **********************************************/ + +#define MCUXCLHASHMODES_SHAKE_PHASE_INIT (0UL) /* Initialization phase of Shake: buffer will be cleared */ +#define MCUXCLHASHMODES_SHAKE_PHASE_ABSORB (1UL) /* Absorb phase of Shake: don't clear any more, but also don't add padding yet */ +#define MCUXCLHASHMODES_SHAKE_PHASE_SQUEEZE (2UL) /* Squeeze phase of Shake: padding has been added, from now on only permute on the state */ + +/********************************************** + * Type declarations + **********************************************/ + +/** + * @brief Internal Hash Algorithm structure + * + */ +typedef struct mcuxClHashModes_Internal_AlgorithmDescriptor +{ + mcuxClHashModes_els_AlgoCore_t els_core; ///< ELS hash core function (access to ELS coprocessor) + uint32_t protection_token_els_core; ///< Protection token value for the used core + uint32_t rtfSize; ///< Size of the Runtime Fingerprint used by the hash function; has to be set to zero when not supported + mcuxClEls_HashOption_t hashOptions; +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + mcuxClHashModes_AlgoDmaProtection_t dmaProtection; ///< DMA protection function + uint32_t protection_token_dma_protection; ///< Protection token value for the used DMA protection function +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + uint32_t dummyValue; ///< needed in the absense of any algorithm using internal algorithm properties +} mcuxClHashModes_Internal_AlgorithmDescriptor_t; +/**@}*/ + +/********************************************** + * Function declarations + **********************************************/ + +#define MCUXCLHASHMODES_SWITCH_4BYTE_ENDIANNESS(val) \ + ((((val) & 0xFFu) << 24) \ + | (((val) & 0xFF00u) << 8) \ + | (((val) & 0xFF0000u) >> 8) \ + | (((val) & 0xFF000000u) >> 24)) ///< Macro to switch the endianness of a CPU word + +#define MCUXCLHASHMODES_SWITCH_8BYTE_ENDIANNESS(val) \ + ((((val) << 56u) & 0xFF00000000000000u) | \ + (((val) << 40u) & 0x00FF000000000000u) | \ + (((val) << 24u) & 0x0000FF0000000000u) | \ + (((val) << 8u ) & 0x000000FF00000000u) | \ + (((val) >> 8u ) & 0x00000000FF000000u) | \ + (((val) >> 24u) & 0x0000000000FF0000u) | \ + (((val) >> 40u) & 0x000000000000FF00u) | \ + (((val) >> 56u) & 0x00000000000000FFu)) + + +/** + * @brief Function to switch endianness of arbitrary size words in a buffer + * + * This function switches the endianness of byteLen buffer consisting of wordLen words + * pointed to by ptr + * Only endianness of full words within the buffer with be switched. + * + * @param[in/out] ptr Pointer to the buffer + * @param[in] byteLen Byte length of buffer pointed to by ptr + * + * @return void + */ +static inline void mcuxClHashModes_internal_c_genericSwitchEndiannessOfBufferWords(uint32_t *ptr, uint32_t byteLen, uint32_t wordLen) +{ + if(sizeof(uint32_t) == wordLen) + { + for(uint32_t i = 0u; i < (byteLen / sizeof(uint32_t)); i++) + { + ptr[i] = MCUXCLHASHMODES_SWITCH_4BYTE_ENDIANNESS(ptr[i]); + } + } + else if(sizeof(uint64_t) == wordLen) + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("Accessing 64 bit data with 32 bit alignment is supported on target platform") + uint64_t * ptr64 = (uint64_t *)ptr; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() + for(uint32_t i = 0u; i < (byteLen / sizeof(uint64_t)); i++) + { + ptr64[i] = MCUXCLHASHMODES_SWITCH_8BYTE_ENDIANNESS(ptr64[i]); + } + } + else + { + /* not supported */ + } +} + +/** + * @brief convert 128 bit number of bytes to number of bits + */ +static inline void mcuxClHashModes_processedLength_toBits(uint64_t *pLen128) +{ + pLen128[1] = (pLen128[1] << 3u) | (pLen128[0] >> 61u); + pLen128[0] = pLen128[0] << 3u; +} + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASHMODES_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_Memory.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_Memory.h new file mode 100644 index 000000000..c0c05fb18 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_Memory.h @@ -0,0 +1,124 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Internal_Memory.h + * @brief Internal memory consumption definitions of the mcuxClHashModes component + */ + +#ifndef MCUXCLHASHMODES_INTERNAL_MEMORY_H_ +#define MCUXCLHASHMODES_INTERNAL_MEMORY_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/********************************************** + * Block, State and Counter sizes + **********************************************/ + +#define MCUXCLHASH_BLOCK_SIZE_MD5 (64U) ///< MD5 block size: MD5 bit (64 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA_1 (64U) ///< SHA-1 block size: 512 bit (64 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA_224 (64U) ///< SHA-224 block size: 512 bit (64 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA_256 (64U) ///< SHA-256 block size: 512 bit (64 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA_384 (128U) ///< SHA-384 block size: 1024 bit (128 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA_512 (128U) ///< SHA-512 block size: 1024 bit (128 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_224 (144U) ///< SHA3-224 block size: 1152 bit (144 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_256 (136U) ///< SHA3-256 block size: 1088 bit (136 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_384 (104U) ///< SHA3-384 block size: 832 bit (104 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_512 (72U) ///< SHA3-512 block size: 576 bit (72 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_SHAKE_128 (168U) ///< SHAKE-128 block size: 1344 bit (168 bytes) +#define MCUXCLHASH_BLOCK_SIZE_SHA3_SHAKE_256 (136U) ///< SHAKE-256 block size: 1088 bit (136 bytes) +#define MCUXCLHASH_BLOCK_SIZE_MAX (MCUXCLHASH_BLOCK_SIZE_SHA3_SHAKE_128) ///< Maximum block size + +#define MCUXCLHASH_STATE_SIZE_MD5 (16U) ///< MD5 state size: 64 bit (8 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA_1 (20U) ///< SHA-1 state size: 160 bit (20 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA_224 (32U) ///< SHA-224 state size: 256 bit (32 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA_256 (32U) ///< SHA-256 state size: 256 bit (32 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA_384 (64U) ///< SHA-384 state size: 512 bit (64 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA_512 (64U) ///< SHA-512 state size: 512 bit (64 bytes) +#define MCUXCLHASH_STATE_SIZE_SHA3 (200U) ///< SHA3 all variants state size: 1600 bits (200 bytes) +#define MCUXCLHASH_STATE_SIZE_SECSHA_1 (2U * MCUXCLHASH_STATE_SIZE_SHA_1) ///< SECSHA-1 state size: 160 bit (2*20 bytes) +#define MCUXCLHASH_STATE_SIZE_SECSHA_224 (2U * MCUXCLHASH_STATE_SIZE_SHA_224) ///< SECSHA-224 state size: 2*256 bit (2*32 bytes). Includes the mask. +#define MCUXCLHASH_STATE_SIZE_SECSHA_256 (2U * MCUXCLHASH_STATE_SIZE_SHA_256) ///< SECSHA-256 state size: 2*256 bit (2*32 bytes). Includes the mask. +#define MCUXCLHASH_STATE_SIZE_SECSHA_384 (2U * MCUXCLHASH_STATE_SIZE_SHA_384) ///< SECSHA-384 state size: 2*512 bit (2*64 bytes). Includes the mask. +#define MCUXCLHASH_STATE_SIZE_SECSHA_512 (2U * MCUXCLHASH_STATE_SIZE_SHA_512) ///< SECSHA-512 state size: 2*512 bit (2*64 bytes). Includes the mask. +#define MCUXCLHASH_STATE_SIZE_SECSHA3 (2U * MCUXCLHASH_STATE_SIZE_SHA3) ///< SECSHA3 all variants state size: 2*1600 bits (2*200 bytes). Includes the mask. +#define MCUXCLHASH_STATE_SIZE_MAX (MCUXCLHASH_STATE_SIZE_SHA3) ///< Maximum block size + +#define MCUXCLHASH_COUNTER_SIZE_MIYAGUCHI_PRENEEL (1U) ///< Counter size for Miyaguchi Preneel, only indicates whether a block has already been processed +#define MCUXCLHASH_COUNTER_SIZE_MD5 (8U) ///< Counter size for MD5 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA_1 (8U) ///< Counter size for SHA-1 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA_224 (8U) ///< Counter size for SHA-224 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA_256 (8U) ///< Counter size for SHA-256 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA_384 (16U) ///< Counter size for SHA-384 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA_512 (16U) ///< Counter size for SHA-512 padding +#define MCUXCLHASH_COUNTER_SIZE_SHA3 (16U) ///< Counter size for SHA3 padding +#define MCUXCLHASH_COUNTER_SIZE_MAX (16U) ///< Maximal counter size for any supported algorithm + + +/********************************************** + * Workarea sizes + **********************************************/ + +/** + * @brief WaCpu buffer is used in oneshot mode to add padding to the last message block. + * Further it is used to store the resulting hash and in case of SHA-256 an RTF. + * Regardless of SHA-2 variant, the size requirement is dominated by block size. + * In streaming mode WaCpu buffer is not used at all. + * For mcuxClHash_verify and mcuxClHash_compare an extra temporary buffer of size state is used. + */ +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_MIYAGUCHI_PRENEEL (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_MD5 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA1 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_224 (MCUXCLHASH_BLOCK_SIZE_SHA_224 + MCUXCLHASH_STATE_SIZE_SHA_224) ///< CPU workarea consumption of SHA2-224 +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_256 (MCUXCLHASH_BLOCK_SIZE_SHA_256 + MCUXCLHASH_STATE_SIZE_SHA_256) ///< CPU workarea consumption of SHA2-256 +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_384 (MCUXCLHASH_BLOCK_SIZE_SHA_384 + MCUXCLHASH_STATE_SIZE_SHA_384) ///< CPU workarea consumption of SHA2-384 +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_512 (MCUXCLHASH_BLOCK_SIZE_SHA_512 + MCUXCLHASH_STATE_SIZE_SHA_512) ///< CPU workarea consumption of SHA2-512 +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA3 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA_1 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_224 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_256 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_384 (4u) +#define MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_512 (4u) + +#define MCUXCLHASHMODES_MAX(a,b) ((a) > (b) ? (a) : (b)) + +#define MCUXCLHASHMODES_INTERNAL_WACPU_MAX (MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_MIYAGUCHI_PRENEEL, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_MD5, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA1, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_224, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_256, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_384, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA2_512, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SHA3, \ + MCUXCLHASHMODES_MAX(MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_256, \ + MCUXCLHASH_INTERNAL_WACPU_SIZE_SECSHA2_512)))))))))) + +#define MCUXCLHASHMODES_CONTEXT_MAX_SIZE_INTERNAL (sizeof(mcuxClHash_ContextDescriptor_t) + MCUXCLHASH_BLOCK_SIZE_MAX + MCUXCLHASH_STATE_SIZE_MAX) +/* TODO: CLNS-10242*/ +#define MCUXCLHASHMODES_CONTEXT_MAX_SIZE_INTERNAL_NO_SECSHA (sizeof(mcuxClHash_ContextDescriptor_t) + MCUXCLHASH_BLOCK_SIZE_SHA3_SHAKE_128 + MCUXCLHASH_STATE_SIZE_SHA3) + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASHMODES_INTERNAL_MEMORY_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_els_sha2.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_els_sha2.h new file mode 100644 index 000000000..f48067984 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/internal/mcuxClHashModes_Internal_els_sha2.h @@ -0,0 +1,55 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Internal_els_sha2.h + * @brief Internal definitions and declarations of the *INTERNAL* layer dedicated to ELS + */ + +#ifndef MCUXCLHASHMODES_INTERNAL_ELS_SHA2_H_ +#define MCUXCLHASHMODES_INTERNAL_ELS_SHA2_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************** + * Type declarations + **********************************************************/ + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +/** + * @brief DMA protection function type + * + * This function will verify if the DMA transfer of the last hardware accelerator operation finished on the expected address + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHashModes_AlgoDmaProtection_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) (*mcuxClHashModes_AlgoDmaProtection_t)(uint8_t *startAddress, + size_t expectedLength)); + +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + +/********************************************************** + * Function declarations + **********************************************************/ +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASHMODES_INTERNAL_ELS_SHA2_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes.h new file mode 100644 index 000000000..e84a3b5d3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLHASHMODES_H_ +#define MCUXCLHASHMODES_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#endif /* MCUXCLHASHMODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Algorithms.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Algorithms.h new file mode 100644 index 000000000..9df3f09bd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Algorithms.h @@ -0,0 +1,145 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Algorithms.h + * @brief Algorithm/mode definitions for the mcuxClHashModes component + */ + +#ifndef MCUXCLHASHMODES_ALGORITHMS_H_ +#define MCUXCLHASHMODES_ALGORITHMS_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @defgroup mcuxClHashModes_Algorithms mcuxClHashModes_Algorithms +* @brief Hashing algorithms of the @ref mcuxClHashModes component +* @ingroup mcuxClHash_Constants +* @{ +*/ + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + + + + + + + + + + + +/** + * @brief Sha-224 algorithm descriptor + * Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224; + +/** + * @brief Sha-224 algorithm + * Sha-224 hash calculation using the Hash functionality of ELS, it does not support RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha224 = &mcuxClHash_AlgorithmDescriptor_Sha224; + + +/** + * @brief Sha-256 algorithm descriptor + * Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256; + +/** + * @brief Sha-256 algorithm + * Sha-256 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha256 = &mcuxClHash_AlgorithmDescriptor_Sha256; + + +/** + * @brief Sha-384 algorithm descriptor + * Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384; + +/** + * @brief Sha-384 algorithm + * Sha-384 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha384 = &mcuxClHash_AlgorithmDescriptor_Sha384; + + +/** + * @brief Sha-512 algorithm descriptor + * Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +extern const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512; + +/** + * @brief Sha-512 algorithm + * Sha-512 hash calculation using the Hash functionality of ELS, it supports RTF. + * SHA-direct mode has to be disabled prior to using this algorithm + */ +static mcuxClHash_Algo_t mcuxClHash_Algorithm_Sha512 = &mcuxClHash_AlgorithmDescriptor_Sha512; + + + + + + + + + + + + + + + + + + + + + + + + + + + + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/**@}*/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHASHMODES_ALGORITHMS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Constants.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Constants.h new file mode 100644 index 000000000..0e039c742 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Constants.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_Constants.h + * @brief Constants for use with the mcuxClHashModes component */ + +#ifndef MCUXCLHASHMODES_CONSTANTS_H_ +#define MCUXCLHASHMODES_CONSTANTS_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClHash_Constants mcuxClHash_Constants + * @brief Constants of @ref mcuxClHash component + * @ingroup mcuxClHash + * @{ + */ + +/** + * @defgroup MCUXCLHASH_OUTPUT_SIZE_ MCUXCLHASH_OUTPUT_SIZE_ + * @brief Defines for digest sizes + * @ingroup mcuxClHash_Constants + * @{ + */ +#define MCUXCLHASH_OUTPUT_SIZE_MD5 (16U) ///< MD5 output size: 128 bit (16 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_1 (20U) ///< SHA-1 output size: 160 bit (20 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_224 (28U) ///< SHA-224 output size: 224 bit (28 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_256 (32U) ///< SHA-256 output size: 256 bit (32 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_384 (48U) ///< SHA-384 output size: 384 bit (48 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_512 (64U) ///< SHA-512 output size: 512 bit (64 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_224 (28U) ///< SHA-512/224 output size: 224 bit (28 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA_512_256 (32U) ///< SHA-512/256 output size: 256 bit (32 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_224 (28uL) ///< SHA3-224 output size: 224 bit (28 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_256 (32uL) ///< SHA3-256 output size: 256 bit (32 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_384 (48uL) ///< SHA3-384 output size: 384 bit (48 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_512 (64uL) ///< SHA3-512 output size: 512 bit (64 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128 (168uL) ///< SHA3-SHAKE 128 output size: 1344 bit (168 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_256 (136uL) ///< SHA3-SHAKE 256 output size: 1088 bit (136 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_128 (168uL) ///< SHA3-CSHAKE 128 output size: 1344 bit (168 bytes) +#define MCUXCLHASH_OUTPUT_SIZE_SHA3_CSHAKE_256 (136uL) ///< SHA3-CSHAKE 256 output size: 1088 bit (136 bytes) +#define MCUXCLHASH_MAX_OUTPUT_SIZE (MCUXCLHASH_OUTPUT_SIZE_SHA3_SHAKE_128) ///< Maximum output size +/**@}*/ + + + + +/**@}*/ + +#endif /* MCUXCLHASHMODES_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Functions.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Functions.h new file mode 100644 index 000000000..56758475c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_Functions.h @@ -0,0 +1,21 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLHASHMODES_FUNCTIONS_H_ +#define MCUXCLHASHMODES_FUNCTIONS_H_ + +#include // Exported features flags header +#include + + +#endif /* MCUXCLHASHMODES_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_MemoryConsumption.h new file mode 100644 index 000000000..1b5b863b5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/inc/mcuxClHashModes_MemoryConsumption.h @@ -0,0 +1,86 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHashModes_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClHash component */ + +#ifndef MCUXCLHASHMODES_MEMORYCONSUMPTION_H_ +#define MCUXCLHASHMODES_MEMORYCONSUMPTION_H_ + +/** + * @defgroup mcuxClHashModes_WoarkareaConsumption mcuxClHashModes_WoarkareaConsumption + * @brief Definitions of workarea sizes for the mcuxClHashModes functions. + * @ingroup mcuxClHash_Constants + * @{ + */ + +/****************************************************************************/ +/* Definitions of workarea buffer sizes for the mcuxClHashModes functions. */ +/****************************************************************************/ + +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224 (96u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-224 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_224 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_224 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-224 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_224 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-224 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224 (96u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-224 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_224 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_224 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-224 +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256 (96u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-256 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_256 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_256 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-256 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_256 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-256 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256 (96u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-256 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_256 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_256 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-256 +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384 (192u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-384 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_384 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_384 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-384 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_384 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-384 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384 (192u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-384 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_384 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_384 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-384 +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512 (192u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-512 +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224 (192u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-512/224 +#define MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256 (192u) ///< Defines the workarea size required for mcuxClHash_compute on SHA2-512/256 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-512 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_224 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_224 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-512/224 +#define MCUXCLHASH_COMPARE_CPU_WA_BUFFER_SIZE_SHA2_512_256 MCUXCLHASH_COMPUTE_CPU_WA_BUFFER_SIZE_SHA2_512_256 ///< Defines the workarea size required for mcuxClHash_compare on SHA2-512/256 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-512 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_224 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-512/224 +#define MCUXCLHASH_PROCESS_CPU_WA_BUFFER_SIZE_SHA2_512_256 (4u) ///< Defines the workarea size required for mcuxClHash_process on SHA2-512/256 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512 (192u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-512 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224 (192u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-512/224 +#define MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256 (192u) ///< Defines the workarea size required for mcuxClHash_finish on SHA2-512/256 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-512 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_224 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_224 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-512/224 +#define MCUXCLHASH_VERIFY_CPU_WA_BUFFER_SIZE_SHA2_512_256 MCUXCLHASH_FINISH_CPU_WA_BUFFER_SIZE_SHA2_512_256 ///< Defines the workarea size required for mcuxClHash_verify on SHA2-512/256 +/** @} */ + + +/** + * @defgroup mcuxClHashModes_ContextSize mcuxClHashModes_ContextSize + * @brief Definitions of context sizes and state sizes for extraction of states of a hash operation. + * @ingroup mcuxClHash_Constants + * @{ + */ + +/**************************************************************************************************************/ +/* Definitions of context sizes and state buffer sizes for mcuxClHash_export_state and mcuxClHash_import_state */ +/**************************************************************************************************************/ + +#define MCUXCLHASH_CONTEXT_SIZE_SHA2_224_IN_WORDS (120u / sizeof(uint32_t)) +#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_224 (40u) ///< Defines the state size required for SHA2-224 +#define MCUXCLHASH_CONTEXT_SIZE_SHA2_256_IN_WORDS (120u / sizeof(uint32_t)) +#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_256 (40u) ///< Defines the state size required for SHA2-256 +#define MCUXCLHASH_CONTEXT_SIZE_SHA2_384_IN_WORDS (216u / sizeof(uint32_t)) +#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_384 (80u) ///< Defines the state size required for SHA2-384 +#define MCUXCLHASH_CONTEXT_SIZE_SHA2_512_IN_WORDS (216u / sizeof(uint32_t)) +#define MCUXCLHASH_EXPORT_IMPORT_STATE_SIZE_SHA2_512 (80u) ///< Defines the state size required for SHA2-512 +/** @} */ + + +#endif /* MCUXCLHASHMODES_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Core_els_sha2.c b/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Core_els_sha2.c new file mode 100644 index 000000000..9823d1ef0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Core_els_sha2.c @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHashModes_els_core_sha2, mcuxClHashModes_els_AlgoCore_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_els_core_sha2( + uint32_t options, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHashModes_els_core_sha2, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hash_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + + mcuxClEls_HashOption_t hash_options; + hash_options.word.value = options; + + MCUX_CSSL_FP_FUNCTION_CALL(result_hash, mcuxClEls_Hash_Async(hash_options, + pIn, + inSize, + pOut)); + + if (MCUXCLELS_STATUS_OK_WAIT != result_hash) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_els_core_sha2, MCUXCLHASH_STATUS_FAILURE); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_els_core_sha2, MCUXCLHASH_STATUS_FAILURE); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_els_core_sha2, MCUXCLHASH_STATUS_OK); +} + diff --git a/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Internal_els_sha2.c b/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Internal_els_sha2.c new file mode 100644 index 000000000..bfdec688e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHashModes/src/mcuxClHashModes_Internal_els_sha2.c @@ -0,0 +1,893 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#include +#include +#endif + +/********************************************************** + * Helper functions + **********************************************************/ + +/* Writes the correct RTF flags to the hashOptions struct, based on the rtf parameter */ +static inline mcuxClHash_Status_t mcuxClHashModes_els_selectRtfFlags(mcuxClSession_Rtf_t rtf, + mcuxClEls_HashOption_t *hashOptions) +{ + /* Set RTF processing options */ + if(MCUXCLSESSION_RTF_UPDATE_TRUE == rtf) + { + hashOptions->bits.rtfupd = MCUXCLELS_HASH_RTF_UPDATE_ENABLE; + } + else if(MCUXCLSESSION_RTF_UPDATE_FALSE == rtf) + { + hashOptions->bits.rtfupd = MCUXCLELS_HASH_RTF_UPDATE_DISABLE; + } + else + { + return MCUXCLHASH_STATUS_FAILURE; + } + return MCUXCLHASH_STATUS_OK; +} + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHashModes_els_dmaProtectionAddressReadback) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_els_dmaProtectionAddressReadback(uint8_t * startAddress, + size_t expectedLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHashModes_els_dmaProtectionAddressReadback, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_CompareDmaFinalOutputAddress)); + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_CompareDmaFinalOutputAddress(startAddress, expectedLength)); + + if (MCUXCLELS_STATUS_OK != result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_els_dmaProtectionAddressReadback, MCUXCLHASH_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_els_dmaProtectionAddressReadback, MCUXCLHASH_STATUS_OK); +} +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + +/********************************************************** + * *INTERNAL* layer functions + **********************************************************/ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHashModes_Els_oneShot_Sha2, mcuxClHash_AlgoSkeleton_OneShot_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_Els_oneShot_Sha2 ( + mcuxClSession_Handle_t session, + mcuxClHash_Algo_t algorithm, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHashModes_Els_oneShot_Sha2); + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + const bool isInputInPKC = + (((uint32_t) pIn + inSize)> (uint32_t) MCUXCLPKC_RAM_START_ADDRESS) + && ((uint32_t) pIn < ((uint32_t) MCUXCLPKC_RAM_START_ADDRESS + MCUXCLPKC_RAM_SIZE)); +#endif + + /************************************************************************************** + * Step 1: Set ELS options for initialization, continuation from external state, or from + * internal state + **************************************************************************************/ + + const mcuxClHashModes_Internal_AlgorithmDescriptor_t *algorithmDetails = (const mcuxClHashModes_Internal_AlgorithmDescriptor_t *) algorithm->pAlgorithmDetails; + + /* Start setting initial options for ELS hash */ + mcuxClEls_HashOption_t hash_options = algorithmDetails->hashOptions; + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_DISABLE; + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + + /* Set RTF processing options */ + if(MCUXCLHASH_STATUS_OK != mcuxClHashModes_els_selectRtfFlags(session->rtf, &hash_options)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, MCUXCLHASH_STATUS_FAILURE); + } + + /************************************************************************************** + * Step 2: Process full blocks of input data + **************************************************************************************/ + + /* All blocks can be processed in bulk directly from in */ + size_t const sizeOfFullBlocks = (inSize / algorithm->blockSize) * algorithm->blockSize; + + if (0u < sizeOfFullBlocks) + { +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + /* Check if pIn is in PKC workarea. */ + if (false != isInputInPKC) + { + /* Allocate buffer in CPU WA to copy the input block of data from PKC WA */ + uint8_t * pInCpu = (uint8_t *) mcuxClSession_allocateWords_cpuWa(session, algorithm->blockSize / sizeof(uint32_t)); + size_t processedIn = 0u; + while(processedIn < sizeOfFullBlocks) + { + MCUXCLMEMORY_FP_MEMORY_COPY(pInCpu, &pIn[processedIn], algorithm->blockSize); + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pInCpu, + algorithm->blockSize, + NULL)); + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultElsCore); + } + processedIn += algorithm->blockSize; + } + /* Free workarea (pInCpu) */ + mcuxClSession_freeWords_cpuWa(session, algorithm->blockSize / sizeof(uint32_t)); + } + else + { + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pIn, + sizeOfFullBlocks, + NULL)); + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultElsCore); + } + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + } +#else + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pIn, + sizeOfFullBlocks, + NULL)); + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultElsCore); + } + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; +#endif + } + + /************************************************************************************** + * Step 3: Pad the input data and process last block + **************************************************************************************/ + + /* Buffer in CPU WA to store the last block of data in the finalization phase */ + uint8_t *shablock = (uint8_t *) mcuxClSession_allocateWords_cpuWa(session, algorithm->blockSize / sizeof(uint32_t)); + if(NULL == shablock) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, MCUXCLHASH_STATUS_FAILURE); + } + size_t posdst = inSize - sizeOfFullBlocks; + size_t buflen = algorithm->blockSize; + + /* Copy the data to the buffer in the workspace. */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(shablock, &pIn[sizeOfFullBlocks], posdst, buflen); + + + buflen -= posdst; + + /* add first byte of the padding: (remaining) < (block length) so there is space in the buffer */ + shablock[posdst] = 0x80u; + posdst += 1u; + buflen -= 1u; + + /* Process partial padded block if needed */ + if ( (algorithm->blockSize - algorithm->counterSize) < posdst ) // need room for 64 bit counter and one additional byte + { + MCUXCLMEMORY_FP_MEMORY_SET(&shablock[posdst], 0x00, buflen); + + /* It is currently necessary to set buflen to algorithm->blockSize to distinguish whether this if-branch was taken + * (for the conditional expectations in the exit statement!). Otherwise we could set it to posdst here and save + * some performance overhead */ + buflen = algorithm->blockSize; + posdst = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + shablock, + algorithm->blockSize, + NULL)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultElsCore); + } + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + } + + /* Perform padding by adding data counter */ + MCUXCLMEMORY_FP_MEMORY_SET(&shablock[posdst], 0x00, buflen); + posdst = algorithm->blockSize; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("posdst-4 is always bigger than 1."); + shablock[--posdst] = (uint8_t)(inSize << 3u); + shablock[--posdst] = (uint8_t)(inSize >> 5u); + shablock[--posdst] = (uint8_t)(inSize >> 13u); + shablock[--posdst] = (uint8_t)(inSize >> 21u); + shablock[posdst - 1u] = (uint8_t)(inSize >> 29u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + /* Set output options */ + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; + hash_options.bits.rtfoe = hash_options.bits.rtfupd; + + /* Process last block */ + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + shablock, + algorithm->blockSize, + shablock /* shablock is large enough to hold internal state of hash algorithm + RTF */)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultElsCore); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + uint32_t rtfSize = 0; + rtfSize = (MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf) ? algorithmDetails->rtfSize : 0u; + if(NULL != algorithmDetails->dmaProtection) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDma, algorithmDetails->dmaProtection(shablock, + algorithm->stateSize + rtfSize)); + + if (MCUXCLHASH_STATUS_OK != resultDma) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, resultDma); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + /************************************************************************************** + * Step 4: Copy result to output buffers + **************************************************************************************/ + + /* Copy RTF to corresponding buffer */ + if((MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf) && (NULL != session->pRtf)) + { + MCUXCLMEMORY_FP_MEMORY_COPY(session->pRtf, &shablock[algorithm->hashSize], algorithmDetails->rtfSize); + } + + /* Copy hash digest to output buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY(pOut, shablock, algorithm->hashSize); + *pOutSize += algorithm->hashSize; + + /* Free workarea (shablock) */ + mcuxClSession_freeWords_cpuWa(session, algorithm->blockSize / sizeof(uint32_t)); + + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t scBalance = 0u); +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + MCUX_CSSL_FP_COUNTER_STMT(scBalance = MCUX_CSSL_FP_CONDITIONAL( \ + (0u != sizeOfFullBlocks), \ + MCUX_CSSL_FP_CONDITIONAL(false != isInputInPKC, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + algorithmDetails->protection_token_els_core) * \ + (sizeOfFullBlocks / algorithm->blockSize), \ + MCUX_CSSL_FP_CONDITIONAL(false == isInputInPKC, \ + algorithmDetails->protection_token_els_core))); +#else + MCUX_CSSL_FP_COUNTER_STMT(scBalance = MCUX_CSSL_FP_CONDITIONAL((0u != sizeOfFullBlocks), algorithmDetails->protection_token_els_core)); +#endif + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_COUNTER_STMT(scBalance += (algorithmDetails->protection_token_dma_protection)); +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + MCUX_CSSL_FP_COUNTER_STMT(scBalance += MCUX_CSSL_FP_CONDITIONAL((MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy))); + + /* Set expectations and exit */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_oneShot_Sha2, MCUXCLHASH_STATUS_OK, + scBalance, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((buflen == algorithm->blockSize), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), algorithmDetails->protection_token_els_core), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + (algorithmDetails->protection_token_els_core), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHashModes_Els_process_Sha2, mcuxClHash_AlgoSkeleton_Process_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_Els_process_Sha2 ( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t context, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize) +{ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHashModes_Els_process_Sha2); + + /************************************************************************************** + * Step 1: Initialization - Calculate sizes, set pointers, and set ELS options for + * initialization, continuation from external state, or from internal state + **************************************************************************************/ + + /* Total length of data to be processed */ + size_t unprocessedTotalLength = context->unprocessedLength + inSize; + + const mcuxClHash_AlgorithmDescriptor_t * algorithm = context->algo; + const mcuxClHashModes_Internal_AlgorithmDescriptor_t *algorithmDetails = (const mcuxClHashModes_Internal_AlgorithmDescriptor_t *) algorithm->pAlgorithmDetails; + const size_t algoBlockSize = context->algo->blockSize; + /* The amount of unprocessed data that fills complete blocks */ + size_t unprocessedCompleteBlockLength = (unprocessedTotalLength / algoBlockSize) * (algoBlockSize); + + /* Need to store the initial values of these variables for correct calculation of flow protection values at the end of the function */ + MCUX_CSSL_FP_COUNTER_STMT(const size_t initialUnprocessedCompleteBlockLength = unprocessedCompleteBlockLength); + MCUX_CSSL_FP_COUNTER_STMT(const size_t initialUnprocessedContextLength = context->unprocessedLength); + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + const bool isInputInPKC = + (((uint32_t) pIn + inSize) > (uint32_t) MCUXCLPKC_RAM_START_ADDRESS) + && ((uint32_t) pIn < ((uint32_t) MCUXCLPKC_RAM_START_ADDRESS + MCUXCLPKC_RAM_SIZE)); +#endif + + /* Pointer to the buffer where the state is stored. Either it ends up in the work area, or in the state buffer of the context */ + uint8_t *partialdigest = (uint8_t *)mcuxClHash_getStatePtr(context); + /* Pointer to unprocessed data buffer */ + uint8_t *pUnprocessed = (uint8_t *)mcuxClHash_getUnprocessedPtr(context); + + /* Input pointer that changes throughout the function */ + const uint8_t *pInput = (const uint8_t *)pIn; + /* Start setting initial options for ELS hash */ + mcuxClEls_HashOption_t hash_options = algorithmDetails->hashOptions; + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + + + /************************************************************************************** + * Step 2: Load state (partial digest), if data had been processed before + **************************************************************************************/ + + /* Set hash init/load flags depending on whether there is a valid state to load or not */ + int32_t processedLengthNotZero = mcuxClHash_processedLength_cmp(context->processedLength, 0, 0); + if(0 != processedLengthNotZero) + { + /* There is already a valid state in the context -> load state from context */ + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_ENABLE; + } + + /* Set RTF processing options */ + if(MCUXCLHASH_STATUS_OK != mcuxClHashModes_els_selectRtfFlags(session->rtf, &hash_options)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, MCUXCLHASH_STATUS_FAILURE); + } + + /************************************************************************************** + * Step 3: Process full blocks + **************************************************************************************/ + + /* The first block can either be completely in `pInput`, or partially in the context buffer. */ + if((0u != unprocessedCompleteBlockLength) && (0u != context->unprocessedLength)) + { + /* There is some data in the context buffer. Append enough data from `pInput` to complete a block. */ + MCUXCLMEMORY_FP_MEMORY_COPY(pUnprocessed + context->unprocessedLength, + pInput, + algoBlockSize - context->unprocessedLength); + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pUnprocessed, + algoBlockSize, + partialdigest)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultElsCore); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != algorithmDetails->dmaProtection) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDma, algorithmDetails->dmaProtection(partialdigest, algorithm->stateSize)); + + if (MCUXCLHASH_STATUS_OK != resultDma) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultDma); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + + pInput += algoBlockSize - context->unprocessedLength; + + mcuxClHash_processedLength_add(context->processedLength, algoBlockSize); + context->unprocessedLength = 0u; + + unprocessedCompleteBlockLength -= algoBlockSize; + unprocessedTotalLength -= algoBlockSize; + } + + /* At this point, there is no more data in the context buffer, so remaining blocks can be processed in bulk directly from pIn */ + if (0u != unprocessedCompleteBlockLength) + { +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + /* Check pInput is in PKC workarea. */ + if (false != isInputInPKC) + { + size_t processedIn = 0u; + while(processedIn < unprocessedCompleteBlockLength) + { + /* Copy block of the input data in the context buffer. */ + MCUXCLMEMORY_FP_MEMORY_COPY(pUnprocessed, + &pInput[processedIn], + algoBlockSize); + + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pUnprocessed, + algoBlockSize, + partialdigest)); + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultElsCore); + } + processedIn += algoBlockSize; + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + } + } + else + { + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pInput, + unprocessedCompleteBlockLength, + partialdigest)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultElsCore); + } + + } +#else + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + pInput, + unprocessedCompleteBlockLength, + partialdigest)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultElsCore); + } +#endif + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != algorithmDetails->dmaProtection) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDma, algorithmDetails->dmaProtection(partialdigest, algorithm->stateSize)); + + if (MCUXCLHASH_STATUS_OK != resultDma) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, resultDma); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + + pInput += unprocessedCompleteBlockLength; + + mcuxClHash_processedLength_add(context->processedLength, unprocessedCompleteBlockLength); + + unprocessedTotalLength -= unprocessedCompleteBlockLength; + } + + /************************************************************************************** + * Step 4: Process incomplete blocks + **************************************************************************************/ + + if(0u < unprocessedTotalLength) + { + /* Append data from `pInput` to accumulation buffer. */ + MCUXCLMEMORY_FP_MEMORY_COPY(pUnprocessed + context->unprocessedLength, + pInput, + (unprocessedTotalLength - context->unprocessedLength)); + context->unprocessedLength = unprocessedTotalLength; + + } + + /************************************************************************************** + * Step 5: Exit + **************************************************************************************/ + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t scBalance = 0u); +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + MCUX_CSSL_FP_COUNTER_STMT(scBalance = MCUX_CSSL_FP_CONDITIONAL(false != isInputInPKC, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), \ + algorithmDetails->protection_token_els_core) \ + * initialUnprocessedCompleteBlockLength / algoBlockSize \ + + MCUX_CSSL_FP_CONDITIONAL(false == isInputInPKC, algorithmDetails->protection_token_els_core)); +#else + MCUX_CSSL_FP_COUNTER_STMT(scBalance = algorithmDetails->protection_token_els_core); +#endif + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t dmaFinal_token = 0u); +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_COUNTER_STMT(dmaFinal_token = algorithmDetails->protection_token_dma_protection); +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_process_Sha2, MCUXCLHASH_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((0u != initialUnprocessedCompleteBlockLength) && (0u != initialUnprocessedContextLength), + algorithmDetails->protection_token_els_core, + dmaFinal_token, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + MCUX_CSSL_FP_CONDITIONAL((((0u != initialUnprocessedCompleteBlockLength) && (0u == initialUnprocessedContextLength)) || ((algoBlockSize < initialUnprocessedCompleteBlockLength) && (0u != initialUnprocessedContextLength))), + dmaFinal_token, + scBalance), + MCUX_CSSL_FP_CONDITIONAL((0u < unprocessedTotalLength), + (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)))); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHashModes_Els_finish_Sha2, mcuxClHash_AlgoSkeleton_Finish_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClHashModes_Els_finish_Sha2 ( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t context, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHashModes_Els_finish_Sha2); + + /************************************************************************************** + * Step 1: Initialization - Calculate sizes, set pointers, and set ELS options for + * initialization, continuation from external state, or from internal state + **************************************************************************************/ + + if(NULL == pOut) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_STATUS_INVALID_PARAMS); + } + + /* Pointer to the buffer where the state is stored. Either it ends up in the work area, or in the state buffer of the context */ + uint8_t *partialdigest = (uint8_t *)mcuxClHash_getStatePtr(context); + + /* Start setting initial options for ELS hash */ + const mcuxClHash_AlgorithmDescriptor_t *algorithm = context->algo; + const mcuxClHashModes_Internal_AlgorithmDescriptor_t *algorithmDetails = (const mcuxClHashModes_Internal_AlgorithmDescriptor_t *) algorithm->pAlgorithmDetails; + mcuxClEls_HashOption_t hash_options = algorithmDetails->hashOptions; + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_ENABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_DISABLE; + + if((algorithm->blockSize < MCUXCLHASH_BLOCK_SIZE_SHA_224)||(algorithm->blockSize > MCUXCLHASH_BLOCK_SIZE_SHA_512)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_FAILURE); + } + /* Set RTF processing options */ + if(MCUXCLHASH_STATUS_OK != mcuxClHashModes_els_selectRtfFlags(session->rtf, &hash_options)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_STATUS_FAILURE); + } + + /************************************************************************************** + * Step 2: Load state (partial digest), if data had been processed before + **************************************************************************************/ + + /* Set hash init/load flags depending on whether there is a valid state to load or not */ + int32_t processedLengthNotZero = mcuxClHash_processedLength_cmp(context->processedLength, 0, 0); + if(0 != processedLengthNotZero) + { + /* There is already a valid state in the context -> load state from context */ + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_ENABLE; + } + + /************************************************************************************** + * Step 3: Padd data and process last block + **************************************************************************************/ + + /* Pointer to the buffer where the last block of data is stored in the finalization phase */ + uint8_t *shablock = (uint8_t *)mcuxClHash_getUnprocessedPtr(context); + + /* Buffer in CPU WA to store the digest and RTF output in the finalization phase */ + uint8_t *pOutput = (uint8_t *) mcuxClSession_allocateWords_cpuWa(session, (algorithm->stateSize + algorithmDetails->rtfSize) / sizeof(uint32_t)); + if(NULL == pOutput) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_STATUS_FAILURE); + } + + size_t posdst, buflen; + buflen = algorithm->blockSize - context->unprocessedLength; + posdst = context->unprocessedLength; + + // add first byte of the padding: (remaining) < (block length) so there is space in the buffer + shablock[posdst] = 0x80u; + posdst += 1u; + buflen -= 1u; + + /* Process partial padded block if needed */ + if (algorithm->blockSize - algorithm->counterSize - 1u < context->unprocessedLength) // need room for 64 bit counter and one additional byte + { + MCUXCLMEMORY_FP_MEMORY_SET(shablock + posdst, 0x00u, buflen); + buflen = algorithm->blockSize; + posdst = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + shablock, + algorithm->blockSize, + partialdigest)); + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, resultElsCore); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != algorithmDetails->dmaProtection) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDma, algorithmDetails->dmaProtection(partialdigest, algorithm->stateSize)); + + if (MCUXCLHASH_STATUS_OK != resultDma) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, resultDma); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + hash_options.bits.hashini = MCUXCLELS_HASH_INIT_DISABLE; + hash_options.bits.hashld = MCUXCLELS_HASH_LOAD_ENABLE; + } + + /* Perform padding by adding data counter */ + MCUXCLMEMORY_FP_MEMORY_SET(shablock + posdst, 0x00u, buflen); + + posdst = algorithm->blockSize; + mcuxClHash_processedLength_add(context->processedLength, context->unprocessedLength); + shablock[--posdst] = (uint8_t)(context->processedLength[0] << 3u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 5u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 13u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 21u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 29u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 37u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 45u); + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 53u); + if (context->algo->counterSize > 8u) + { + shablock[--posdst] = (uint8_t)(context->processedLength[0] >> 61u) | + (uint8_t)(context->processedLength[1] << 5u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 5u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 13u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 21u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 29u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 37u); + shablock[--posdst] = (uint8_t)(context->processedLength[1] >> 45u); + shablock[posdst - 1u] = (uint8_t)(context->processedLength[1] >> 53u); + } + hash_options.bits.hashoe = MCUXCLELS_HASH_OUTPUT_ENABLE; + + MCUXCLMEMORY_FP_MEMORY_COPY(pOutput, partialdigest, algorithm->stateSize); + + /* Set RTF processing options */ + hash_options.bits.rtfoe = hash_options.bits.rtfupd; + + /* Process last block */ + MCUX_CSSL_FP_FUNCTION_CALL(resultElsCore, algorithmDetails->els_core(hash_options.word.value, + shablock, + algorithm->blockSize, + pOutput)); + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + uint32_t rtfSize = 0; + rtfSize = (MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf) ? algorithmDetails->rtfSize : 0u; + if(NULL != algorithmDetails->dmaProtection) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDma, algorithmDetails->dmaProtection(pOutput, + algorithm->stateSize + rtfSize)); + + if (MCUXCLHASH_STATUS_OK != resultDma) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, resultDma); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + if (MCUXCLHASH_STATUS_OK != resultElsCore) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, resultElsCore); + } + + /************************************************************************************** + * Step 4: Copy result to output buffers and clear context + **************************************************************************************/ + + /* Copy RTF to corresponding buffer */ + if((MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf)) + { + if (NULL == session->pRtf) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_STATUS_INVALID_PARAMS); + } + else + { + MCUXCLMEMORY_FP_MEMORY_COPY(session->pRtf, pOutput + algorithm->hashSize, algorithmDetails->rtfSize); + } + } + + /* Copy hash digest to output buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY(pOut, pOutput, algorithm->hashSize); + + *pOutSize += algorithm->hashSize; + + /* Free workarea (pOutput) */ + mcuxClSession_freeWords_cpuWa(session, (algorithm->stateSize + algorithmDetails->rtfSize) / sizeof(uint32_t)); + + /* Backup unprocessedLength before context clearing */ + MCUX_CSSL_FP_COUNTER_STMT(const size_t unprocessedLength = context->unprocessedLength); + + /* Clear context */ + MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *)context, sizeof(mcuxClHash_ContextDescriptor_t) + context->algo->blockSize + context->algo->stateSize); + + + /************************************************************************************** + * Step 5: Exit + **************************************************************************************/ + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t dma_token = 0u); +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_COUNTER_STMT(dma_token = algorithmDetails->protection_token_dma_protection); +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t rtfSC = 0u); + MCUX_CSSL_FP_COUNTER_STMT(rtfSC = MCUX_CSSL_FP_CONDITIONAL((MCUXCLSESSION_RTF_UPDATE_TRUE == session->rtf),MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy))); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHashModes_Els_finish_Sha2, MCUXCLHASH_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL(algorithm->blockSize - algorithm->counterSize - 1u < unprocessedLength, + dma_token, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + algorithmDetails->protection_token_els_core), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + algorithmDetails->protection_token_els_core, + dma_token, + rtfSC, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + +} + + +/********************************************************** + * Algorithm descriptor implementations + **********************************************************/ + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() + +static const mcuxClHashModes_Internal_AlgorithmDescriptor_t mcuxClHashModes_Internal_AlgorithmDescriptor_Sha224 = +{ + .els_core = mcuxClHashModes_els_core_sha2, + .protection_token_els_core = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_core_sha2), + .rtfSize = 0u, + .hashOptions.word.value = MCUXCLELS_HASH_VALUE_MODE_SHA_224, +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + .dmaProtection = mcuxClHashModes_els_dmaProtectionAddressReadback, + .protection_token_dma_protection = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_dmaProtectionAddressReadback), +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ +}; + +const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha224 = { + .oneShotSkeleton = mcuxClHashModes_Els_oneShot_Sha2, + .protection_token_oneShotSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_oneShot_Sha2), + .processSkeleton = mcuxClHashModes_Els_process_Sha2, + .protection_token_processSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_process_Sha2), + .finishSkeleton = mcuxClHashModes_Els_finish_Sha2, + .protection_token_finishSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_finish_Sha2), + .blockSize = MCUXCLHASH_BLOCK_SIZE_SHA_224, + .hashSize = MCUXCLHASH_OUTPUT_SIZE_SHA_224, + .stateSize = MCUXCLHASH_STATE_SIZE_SHA_224, + .counterSize = MCUXCLHASH_COUNTER_SIZE_SHA_224, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithmDetails = (void *) &mcuxClHashModes_Internal_AlgorithmDescriptor_Sha224 + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + + +static const mcuxClHashModes_Internal_AlgorithmDescriptor_t mcuxClHashModes_Internal_AlgorithmDescriptor_Sha256 = +{ + .els_core = mcuxClHashModes_els_core_sha2, + .protection_token_els_core = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_core_sha2), + .rtfSize = MCUXCLELS_HASH_RTF_OUTPUT_SIZE, + .hashOptions.word.value = MCUXCLELS_HASH_VALUE_MODE_SHA_256, +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + .dmaProtection = mcuxClHashModes_els_dmaProtectionAddressReadback, + .protection_token_dma_protection = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_dmaProtectionAddressReadback), +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ +}; + +const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha256 = { + .oneShotSkeleton = mcuxClHashModes_Els_oneShot_Sha2, + .protection_token_oneShotSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_oneShot_Sha2), + .processSkeleton = mcuxClHashModes_Els_process_Sha2, + .protection_token_processSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_process_Sha2), + .finishSkeleton = mcuxClHashModes_Els_finish_Sha2, + .protection_token_finishSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_finish_Sha2), + .blockSize = MCUXCLHASH_BLOCK_SIZE_SHA_256, + .hashSize = MCUXCLHASH_OUTPUT_SIZE_SHA_256, + .stateSize = MCUXCLHASH_STATE_SIZE_SHA_256, + .counterSize = MCUXCLHASH_COUNTER_SIZE_SHA_256, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithmDetails = (void *) &mcuxClHashModes_Internal_AlgorithmDescriptor_Sha256 + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + + +static const mcuxClHashModes_Internal_AlgorithmDescriptor_t mcuxClHashModes_Internal_AlgorithmDescriptor_Sha384 = +{ + .els_core = mcuxClHashModes_els_core_sha2, + .protection_token_els_core = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_core_sha2), + .rtfSize = 0u, + .hashOptions.word.value = MCUXCLELS_HASH_VALUE_MODE_SHA_384, +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + .dmaProtection = mcuxClHashModes_els_dmaProtectionAddressReadback, + .protection_token_dma_protection = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_dmaProtectionAddressReadback), +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ +}; + +const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha384 = { + .oneShotSkeleton = mcuxClHashModes_Els_oneShot_Sha2, + .protection_token_oneShotSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_oneShot_Sha2), + .processSkeleton = mcuxClHashModes_Els_process_Sha2, + .protection_token_processSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_process_Sha2), + .finishSkeleton = mcuxClHashModes_Els_finish_Sha2, + .protection_token_finishSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_finish_Sha2), + .blockSize = MCUXCLHASH_BLOCK_SIZE_SHA_384, + .hashSize = MCUXCLHASH_OUTPUT_SIZE_SHA_384, + .stateSize = MCUXCLHASH_STATE_SIZE_SHA_384, + .counterSize = MCUXCLHASH_COUNTER_SIZE_SHA_384, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithmDetails = (void *) &mcuxClHashModes_Internal_AlgorithmDescriptor_Sha384 + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; + + +static const mcuxClHashModes_Internal_AlgorithmDescriptor_t mcuxClHashModes_Internal_AlgorithmDescriptor_Sha512 = +{ + .els_core = mcuxClHashModes_els_core_sha2, + .protection_token_els_core = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_core_sha2), + .rtfSize = 0u, + .hashOptions.word.value = MCUXCLELS_HASH_VALUE_MODE_SHA_512, +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + .dmaProtection = mcuxClHashModes_els_dmaProtectionAddressReadback, + .protection_token_dma_protection = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_els_dmaProtectionAddressReadback), +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ +}; + +const mcuxClHash_AlgorithmDescriptor_t mcuxClHash_AlgorithmDescriptor_Sha512 = { + .oneShotSkeleton = mcuxClHashModes_Els_oneShot_Sha2, + .protection_token_oneShotSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_oneShot_Sha2), + .processSkeleton = mcuxClHashModes_Els_process_Sha2, + .protection_token_processSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_process_Sha2), + .finishSkeleton = mcuxClHashModes_Els_finish_Sha2, + .protection_token_finishSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHashModes_Els_finish_Sha2), + .blockSize = MCUXCLHASH_BLOCK_SIZE_SHA_512, + .hashSize = MCUXCLHASH_OUTPUT_SIZE_SHA_512, + .stateSize = MCUXCLHASH_STATE_SIZE_SHA_512, + .counterSize = MCUXCLHASH_COUNTER_SIZE_SHA_512, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the algorithm.") + .pAlgorithmDetails = (void *) &mcuxClHashModes_Internal_AlgorithmDescriptor_Sha512 + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +}; +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Els.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Els.h new file mode 100644 index 000000000..fc0758d35 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Els.h @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Core_Functions_Els.h + * @brief Internal definitions of ELS engine functions for the HMAC component + */ + +#ifndef MCUXCLHMAC_CORE_FUNCTIONS_ELS_H_ +#define MCUXCLHMAC_CORE_FUNCTIONS_ELS_H_ + +#include // Exported features flags header +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************/ +/* Engine functions */ +/****************************/ + +/** + * @brief HMAC engine function for the oneshot computation using ELS HW + * + * This function performs the actual HMAC operation using the ELS HW. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Oneshot_Els, mcuxClHmac_ComputeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Oneshot_Els( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + const uint8_t * const pIn, /* HMAC input */ + uint32_t inLength, /* Input size */ + uint8_t * const pOut, /* HMAC output */ + uint32_t * const pOutLength /* Output size */ +); + +/** + * @brief HMAC engine function for the init phase of a multi-part computation using ELS HW + * + * This function prepares the ELS HW to start a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Init_Els, mcuxClHmac_InitEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Init_Els( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext /* HMAC context */ +); + +/** + * @brief HMAC engine function for the update phase of a multi-part computation using ELS HW + * + * This function provides the ELS HW with additional data for a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Update_Els, mcuxClHmac_UpdateEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Update_Els( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + const uint8_t *const pIn, /* HMAC input */ + uint32_t inLength /* Input size */ +); + +/** + * @brief HMAC engine function for the finalize phase of a multi-part computation using ELS HW + * + * This function provides the ELS HW with an output buffer to finalize a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Finalize_Els, mcuxClHmac_FinalizeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Finalize_Els( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + uint8_t *const pOut, /* HMAC output */ + uint32_t *const pOutLength /* Output size */ +); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_CORE_FUNCTIONS_ELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Sw.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Sw.h new file mode 100644 index 000000000..71060341a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Core_Functions_Sw.h @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Core_Functions_Sw.h + * @brief Internal definitions of SW engine functions for the HMAC component + */ + +#ifndef MCUXCLHMAC_CORE_FUNCTIONS_SW_H_ +#define MCUXCLHMAC_CORE_FUNCTIONS_SW_H_ + +#include // Exported features flags header +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************/ +/* Engine functions */ +/****************************/ + +/** + * @brief HMAC engine function for the oneshot computation using SW + * + * This function performs the actual HMAC operation using the SW. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Oneshot_Sw, mcuxClHmac_ComputeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Oneshot_Sw( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + const uint8_t * const pIn, /* HMAC input */ + uint32_t inLength, /* Input size */ + uint8_t * const pOut, /* HMAC output */ + uint32_t * const pOutLength /* Output size */ +); + +/** + * @brief HMAC engine function for the init phase of a multi-part computation using SW + * + * This function prepares a context to start a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Init_Sw, mcuxClHmac_InitEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Init_Sw( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext /* HMAC context */ +); + +/** + * @brief HMAC engine function for the update phase of a multi-part computation using SW + * + * This function processes additional data for a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Update_Sw, mcuxClHmac_UpdateEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Update_Sw( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + const uint8_t *const pIn, /* HMAC input */ + uint32_t inLength /* Input size */ +); + +/** + * @brief HMAC engine function for the finalize phase of a multi-part computation using SW + * + * This function finalizes a multi-part HMAC computation. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_Engine_Finalize_Sw, mcuxClHmac_FinalizeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Finalize_Sw( + mcuxClSession_Handle_t session, /* HMAC session handle */ + mcuxClHmac_Context_Generic_t * const pContext, /* HMAC context */ + uint8_t *const pOut, /* HMAC output */ + uint32_t *const pOutLength /* Output size */ +); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_CORE_FUNCTIONS_SW_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Functions.h new file mode 100644 index 000000000..84bd815d2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Functions.h @@ -0,0 +1,117 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Internal_Functions.h + * @brief Internal definitions of helper functions for the HMAC component + */ + +#ifndef MCUXCLHMAC_INTERNAL_FUNCTIONS_H_ +#define MCUXCLHMAC_INTERNAL_FUNCTIONS_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************/ +/* Skeleton functions */ +/****************************/ + +/** + * @brief HMAC Oneshot Compute function + * + * This function acts as an intermediate layer between the mcuxClMac_compute API and specific HMAC algorithm cores + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_compute, mcuxClMac_ComputeFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_compute( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); + + +/** + * @brief HMAC Multipart Init function + * + * This function acts as an intermediate layer between the mcuxClMac_init API and specific HMAC algorithm cores + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_init, mcuxClMac_InitFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key +); + +/** + * @brief HMAC Multipart Process function + * + * This function acts as an intermediate layer between the mcuxClMac_process API and specific HMAC algorithm cores + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_process, mcuxClMac_ProcessFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +); + +/** + * @brief HMAC Multipart Finish function + * + * This function acts as an intermediate layer between the mcuxClMac_finish API and specific HMAC algorithm cores + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_finish, mcuxClMac_FinishFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); + + + +/****************************/ +/* Helper functions */ +/****************************/ + +/** + * Prepares the given HMAC key by hashing and/or padding it to a length of MCUXCLELS_HMAC_PADDED_KEY_SIZE bytes. + * Both the input key and the output padded key are taken from/written to the context. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_prepareHMACKey) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_prepareHMACKey( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + uint32_t * preparedHmacKey +); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Macros.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Macros.h new file mode 100644 index 000000000..7a08f432f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Macros.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Internal_Macros.h + * @brief Internal definitions of helper macros for the HMAC component + */ + +#ifndef MCUXCLHMAC_INTERNAL_MACROS_H_ +#define MCUXCLHMAC_INTERNAL_MACROS_H_ + +#include // Exported features flags header + +/* TODO CLNS-5054: Move these macros to a central location */ + +/* Macro used to align the size to the CPU wordsize */ +#define MCUXCLHMAC_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) \ + (((uint32_t) (((uint32_t) (size)) + ((sizeof(uint32_t)) - 1U))) & ((uint32_t) (~((sizeof(uint32_t)) - 1U)))) + +/* Macro used to compute number of CPU words */ +#define MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(size) \ + (MCUXCLHMAC_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) / (sizeof(uint32_t))) + +#define MCUXCLHMAC_MAX(a,b) ((a) > (b) ? (a) : (b)) + +#endif /* MCUXCLHMAC_INTERNAL_MACROS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Memory.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Memory.h new file mode 100644 index 000000000..0da9386f7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Memory.h @@ -0,0 +1,39 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Internal_Memory.h + * @brief Internal definitions of memory sizes for the HMAC component + */ + +#ifndef MCUXCLHMAC_INTERNAL_MEMORY_H_ +#define MCUXCLHMAC_INTERNAL_MEMORY_H_ + +#include // Exported features flags header + +#include +#include +#include +#include +#include +#include + +#define MCUXCLHMAC_INTERNAL_WACPU_INIT MCUXCLHASH_BLOCK_SIZE_MAX + MCUXCLHASH_INTERNAL_WACPU_MAX +#define MCUXCLHMAC_INTERNAL_WACPU_FINISH MCUXCLHASH_MAX_OUTPUT_SIZE + +#define MCUXCLHMAC_INTERNAL_MAX_WACPU MCUXCLHMAC_MAX(MCUXCLHMAC_INTERNAL_WACPU_INIT, MCUXCLHMAC_INTERNAL_WACPU_FINISH) + +#define MCUXCLHMAC_INTERNAL_MAX_CONTEXT_SIZE (sizeof(mcuxClHmac_Context_Sw_t)) + + +#endif /* MCUXCLHMAC_INTERNAL_MEMORY_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Types.h b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Types.h new file mode 100644 index 000000000..664f2f96e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/internal/mcuxClHmac_Internal_Types.h @@ -0,0 +1,222 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Internal_Types.h + * @brief Internal header for HMAC types * + */ + +#ifndef MCUXCLHMAC_INTERNAL_TYPES_H_ +#define MCUXCLHMAC_INTERNAL_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for mcuxClHash_ContextBuffer_t */ +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************/ +/* Context types */ +/****************************/ + +/* Contains common part of any mac context for all modes and key descriptor of the key to be used. */ +#define MCUXCLHMAC_CONTEXT_COMMON_ENTRIES \ + mcuxClMac_Context_t common; \ + mcuxClKey_Descriptor_t * key; + +/** + * @brief HMAC context structure for modes using ELS HW + * + * This structure captures all the information that the Mac interface needs to + * know for a particular HMAC mode/algorithm to work. + */ +typedef struct mcuxClHmac_Context_Generic +{ + MCUXCLHMAC_CONTEXT_COMMON_ENTRIES +} mcuxClHmac_Context_Generic_t; + +/** + * @brief HMAC context structure for modes using ELS HW + * + * This structure captures all the information that the Mac interface needs to + * know for a particular HMAC mode/algorithm to work. + * It also contains information specific to the ELS HW implementation of HMAC. + */ +typedef struct mcuxClHmac_Context_Els +{ + MCUXCLHMAC_CONTEXT_COMMON_ENTRIES + uint32_t preparedHmacKey[MCUXCLELS_HMAC_PADDED_KEY_SIZE / sizeof(uint32_t)]; /* Padded/Hashed HMAC key, buffer for external HMAC keys */ +} mcuxClHmac_Context_Els_t; + +/** + * @brief HMAC context structure for modes using a SW implementation + * + * This structure captures all the information that the Mac interface needs to + * know for a particular HMAC mode/algorithm to work. + * It also contains information specific to the SW implementation of HMAC. + */ +typedef struct mcuxClHmac_Context_Sw +{ + MCUXCLHMAC_CONTEXT_COMMON_ENTRIES + mcuxClHash_ContextDescriptor_t *hashCtx; /* Hash context for SW-HMAC */ + uint32_t hashContextBuffer[MCUXCLHASHMODES_CONTEXT_MAX_SIZE_INTERNAL_NO_SECSHA / sizeof(uint32_t)]; /* Buffer to store the actual hash context data using maximum size of a hash context */ + uint32_t preparedHmacKey[MCUXCLHASH_BLOCK_SIZE_MAX / sizeof(uint32_t)]; /* Padded/Hashed HMAC key, must be large enough to hold any block */ +} mcuxClHmac_Context_Sw_t; + + +/****************************/ +/* Engine function types */ +/****************************/ + +/** + * @brief HMAC engine function type for the oneshot computation + * + * These functions will perform the actual HMAC operation. + * See specific function declarations for details. + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHmac_ComputeEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClHmac_ComputeEngine_t)( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t *const pOut, + uint32_t *const outLength +)); + +/** + * @brief HMAC engine function type for the init phase of a multi-part computation + * + * These functions will perform the actual HMAC init operation. + * See specific function declarations for details. + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHmac_InitEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClHmac_InitEngine_t)( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext +)); + +/** + * @brief HMAC engine function type for the update phase of a multi-part computation + * + * These functions will perform the actual HMAC update operation. + * See specific function declarations for details. + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHmac_UpdateEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClHmac_UpdateEngine_t)( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +)); + +/** + * @brief HMAC engine function type for the finalize phase of a multi-part computation + * + * These functions will perform the actual HMAC finalize operation. + * See specific function declarations for details. + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClHmac_FinalizeEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClHmac_FinalizeEngine_t)( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const outLength +)); + + +/****************************/ +/* Algorithm types */ +/****************************/ + +/** + * @brief HMAC structure + * + * This internal structure provides all implementation details for the top level mcuxClHmac functions. + * It consists of Init, Update, Finalize and Oneshot engines and the output size. + * + */ +typedef struct mcuxClHMac_AlgorithmDescriptor +{ + mcuxClHmac_InitEngine_t engineInit; ///< engine function to perform the init operation + uint32_t protectionToken_engineInit; ///< protection token of the engine function to perform the init operation + mcuxClHmac_UpdateEngine_t engineUpdate; ///< engine function to perform the update operation + uint32_t protectionToken_engineUpdate; ///< protection token of the engine function to perform the update operation + mcuxClHmac_FinalizeEngine_t engineFinalize; ///< engine function to perform the finalize operation + uint32_t protectionToken_engineFinalize; ///< protection token of the engine function to perform the finalize operation + mcuxClHmac_ComputeEngine_t engineOneshot; ///< engine function to perform the Mac operation in one shot + uint32_t protectionToken_engineOneshot; ///< protection token of the engine function to perform the Mac operation in one shot + mcuxClPadding_addPaddingMode_t addPadding; ///< padding function to be used. One of mcuxClPaddingMode + uint32_t protectionToken_addPadding; ///< protection token of the padding funtion +} mcuxClHmac_AlgorithmDescriptor_t; + +/** + * @brief HMAC algorithm type for algorithms + * + * This type is used to refer to an HMAC algorithm. + */ +typedef const mcuxClHmac_AlgorithmDescriptor_t * const mcuxClHmac_Algorithm_t; + + +/** + * @brief Forward declaration of HMAC algorithm instances + * + */ +extern const mcuxClHmac_AlgorithmDescriptor_t mcuxClHmac_AlgorithmDescriptor_Els; + +extern const mcuxClHmac_AlgorithmDescriptor_t mcuxClHmac_AlgorithmDescriptor_Sw; + + +/****************************/ +/* Mode descriptor types */ +/****************************/ + +/** + * @brief HMAC specific mode descriptor structure + * + * This structure captures all the additional information for the SW-HMAC implementation + * that is not contained in the @ref mcuxClMac_CommonModeDescriptor_t type. + */ +typedef struct mcuxClHmac_ModeDescriptor +{ + const mcuxClHash_AlgorithmDescriptor_t * hashAlgorithm; +} mcuxClHmac_ModeDescriptor_t; + +/** + * @brief Forward declaration of common mode descriptor needed for constructor of HMAC mode + * + */ +extern const mcuxClMac_CommonModeDescriptor_t mcuxClHmac_CommonModeDescriptor_Sw; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac.h new file mode 100644 index 000000000..2dc96726f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLHMAC_H_ +#define MCUXCLHMAC_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#endif /* MCUXCLHMAC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Constants.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Constants.h new file mode 100644 index 000000000..0151ee0d8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Constants.h @@ -0,0 +1,49 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClHmac_Constants.h + * @brief Constants for the mcuxClHmac component + */ + +#ifndef MCUXCLHMAC_CONSTANTS_H_ +#define MCUXCLHMAC_CONSTANTS_H_ + +#include // Exported features flags header +#include + +/** + * @defgroup mcuxClHmac_Constants mcuxClHmac Constants + * @brief Constants of @ref mcuxClHmac component + * @ingroup mcuxClHmac + * @{ + */ + +/* Output sizes */ + +#define MCUXCLHMAC_ELS_OUTPUT_SIZE (32u) /* Size of HMAC SHA-256 output in bytes: 256 bits (32 bytes) */ +#define MCUXCLHMAC_ELS_OUTPUT_SIZE_IN_WORDS (MCUXCLHMAC_ELS_OUTPUT_SIZE / sizeof(uint32_t)) + +#define MCUXCLHMAC_MAX_OUTPUT_SIZE (MCUXCLHASH_MAX_OUTPUT_SIZE) +#define MCUXCLHMAC_MAX_OUTPUT_SIZE_IN_WORDS (MCUXCLHMAC_MAX_OUTPUT_SIZE / sizeof(uint32_t)) + +/* Helper macros and constants for HMAC buffer sizes, assuming HMAC on ELS with SHA-256 is used */ +#define MCUXCLHMAC_ELS_BLOCK_SIZE (64u) +#define MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD (8u) +#define MCUXCLHMAC_ELS_MIN_PADDING_LENGTH (MCUXCLHMAC_ELS_SIZE_OF_LENGTH_FIELD + 1u) ///< Size of minimum HMAC padding length +#define MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH(dataLength) \ + ((((dataLength) + MCUXCLHMAC_ELS_MIN_PADDING_LENGTH) + (MCUXCLHMAC_ELS_BLOCK_SIZE) - 1) / (MCUXCLHMAC_ELS_BLOCK_SIZE)) * MCUXCLHMAC_ELS_BLOCK_SIZE ///< Formula to calculate input buffer size for HMAC with SHA-256 + +/** @}*/ + +#endif /* MCUXCLHMAC_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Functions.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Functions.h new file mode 100644 index 000000000..50575711d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Functions.h @@ -0,0 +1,78 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClHmac_Functions.h + * @brief Functions for the mcuxClHmac component + */ + +#ifndef MCUXCLHMAC_FUNCTIONS_H_ +#define MCUXCLHMAC_FUNCTIONS_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClHmac_Functions mcuxClHmac Functions + * @brief Defines all functions of @ref mcuxClHmac + * @ingroup mcuxClHmac + * @{ +*/ + +/** + * @defgroup mcuxClHmac_Constructors APIs to construct HMAC modes + * @brief Interfaces to construct HMAC modes of operation. + * @ingroup mcuxClHmac_Functions + * @{ + */ + +/** + * @brief This function creates a HMAC mode descriptor for software implementations of HMAC. + * + * The SW-HMAC modes of operation require additional input, hence a + * mode descriptor has to be constructed with this function. + * The resulting descriptor will be written to @p mode. + * + * This function must be called before any SW-HMAC operation is performed. + * + * @param mode[out] Pointer to HMAC custom mode to be initialized. + * @param mcuxClHash_Algo_t[in] Pointer to the Hash algorithm descriptor to be used. SecSha algorithm descriptors are not supported. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClHmac_createHmacMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_createHmacMode( + mcuxClMac_CustomMode_t mode, + mcuxClHash_Algo_t hashAlgorithm +); + +/** + * @} + */ /* mcuxClHmac_Constructors */ + +/** + * @} + */ /* mcuxClHmac_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_KeyTypes.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_KeyTypes.h new file mode 100644 index 000000000..a8a5c4962 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_KeyTypes.h @@ -0,0 +1,68 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClHmac_KeyTypes.h + * @brief Definition of supported key types in mcuxClHmac component, see also @ref mcuxClKey component + */ + +#ifndef MCUXCLHMAC_KEYTYPES_H_ +#define MCUXCLHMAC_KEYTYPES_H_ + +#include // Exported features flags header + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClHmac_KeyTypes mcuxClHmac_KeyTypes + * @brief Defines of supported key types of @ref mcuxClHmac, see @ref mcuxClKey + * @ingroup mcuxClHmac + * @{ + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ") +/** + * @brief Key type structure for HMAC-SHA256 based keys. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256; + +/** + * @brief Key type pointer for HMAC-SHA256 based keys. + */ +static const mcuxClKey_Type_t mcuxClKey_Type_HmacSha256 = &mcuxClKey_TypeDescriptor_HmacSha256; + +/** + * \brief Key type structure for Sw-HMAC based keys with variable length. + * + */ +extern const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength; + +/** + * \brief Key type pointer for HMAC-SHA256 based keys with variable length. + */ +static const mcuxClKey_Type_t mcuxClKey_Type_Hmac_variableLength = &mcuxClKey_TypeDescriptor_Hmac_variableLength; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @} + */ /* mcuxClHmac_KeyTypes */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_KEYTYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_MemoryConsumption.h new file mode 100644 index 000000000..b292e3dbc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_MemoryConsumption.h @@ -0,0 +1,63 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClHmac component + * All work area sizes in bytes are a multiple of CPU wordsize. + */ + +#ifndef MCUXCLHMAC_MEMORYCONSUMPTION_H_ +#define MCUXCLHMAC_MEMORYCONSUMPTION_H_ + +/** + * @defgroup mcuxClHmac_MemoryConsumption mcuxClHmac_MemoryConsumption + * @brief Defines the memory consumption for the mcuxClHmac component + * @ingroup mcuxClHmac + * @{ + */ + +/** + * @brief Helper macro to calculate size aligned to CPU word. + */ +#define MCUXCLHMAC_SIZE_IN_CPUWORDS(size) ((((size) + sizeof(uint32_t) - 1u) / sizeof(uint32_t))) + +/* Workarea sizes */ +#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE (360u) +#define MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_COMPUTE_CPU_WA_BUFFER_SIZE) +#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE (360u) +#define MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_INIT_CPU_WA_BUFFER_SIZE) +#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE (4u) +#define MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_PROCESS_CPU_WA_BUFFER_SIZE) +#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE (168u) +#define MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_FINISH_CPU_WA_BUFFER_SIZE) + +#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE (360u) +#define MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_MAX_CPU_WA_BUFFER_SIZE) + +/* Context sizes */ +#define MCUXCLHMAC_CONTEXT_SIZE_SW (572u) +#define MCUXCLHMAC_CONTEXT_SIZE_SW_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_CONTEXT_SIZE_SW) +#define MCUXCLHMAC_CONTEXT_SIZE_ELS (72u) +#define MCUXCLHMAC_CONTEXT_SIZE_ELS_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_CONTEXT_SIZE_ELS) +#define MCUXCLHMAC_MAX_CONTEXT_SIZE (572u) +#define MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_MAX_CONTEXT_SIZE) + +/* Mode descriptor sizes */ +#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE (48u) +#define MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE_IN_WORDS MCUXCLHMAC_SIZE_IN_CPUWORDS(MCUXCLHMAC_HMAC_MODE_DESCRIPTOR_SIZE) + +/** + * @} + */ /* mcuxClMac_MemoryConsumption */ + +#endif /* MCUXCLHMAC_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Modes.h b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Modes.h new file mode 100644 index 000000000..ab73bffd8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/inc/mcuxClHmac_Modes.h @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClHmac_Modes.h + * @brief Mode descriptors for the mcuxClHmac component + */ + +#ifndef MCUXCLHMAC_MODES_H_ +#define MCUXCLHMAC_MODES_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @addtogroup mcuxClHmac HMAC Modes API + * @brief HMAC mode operations + * @ingroup mcuxClAPI + */ + +/** + * @defgroup mcuxClHmac_Modes HMAC mode definitions + * @brief Modes used by the HMAC operations. + * @ingroup mcuxClHmac + */ + +/** + * @brief HMAC-SHA2-256 mode descriptor using ELS HW + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS; + +/** + * @brief HMAC-SHA2-256 mode using ELS HW + * + * The input buffer @p in will be modified by applying padding to it. The caller + * must ensure that the input buffer is large enough to hold this padding. + * The total buffer size including padding can be calculated using the macro + * #MCUXCLHMAC_ELS_INPUTBUFFER_LENGTH on the data size @p inLength. + * + * Also note that #mcuxClMac_Mode_HMAC_SHA2_256_ELS only works with keys loaded + * into coprocessor (see @ref mcuxClKey for details). + * + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_HMAC_SHA2_256_ELS = + &mcuxClHmac_ModeDescriptor_SHA2_256_ELS; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLHMAC_MODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Els.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Els.c new file mode 100644 index 000000000..8c3270fd6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Els.c @@ -0,0 +1,223 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Els.c + * @brief Implementation of ELS engine functions for the HMAC component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Oneshot_Els, mcuxClHmac_ComputeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Oneshot_Els( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Oneshot_Els, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Els_t * const pCtxEls = (mcuxClHmac_Context_Els_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + size_t completeLen = (inLength / MCUXCLHMAC_ELS_BLOCK_SIZE) * MCUXCLHMAC_ELS_BLOCK_SIZE; + size_t lastDataChunkLength = inLength - completeLen; + size_t totalPaddingLength = 0u; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const is discarded to perform byte-wise padding") + uint8_t *pDataIn = (uint8_t*) pIn; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() + + /* Apply padding to the input buffer */ + //caller needs to assure that the buffer is big enough + + //compute total padding length + if((MCUXCLHMAC_ELS_BLOCK_SIZE - MCUXCLHMAC_ELS_MIN_PADDING_LENGTH) < lastDataChunkLength) + { + totalPaddingLength = (2u * MCUXCLHMAC_ELS_BLOCK_SIZE) - lastDataChunkLength; + } + else + { + totalPaddingLength = MCUXCLHMAC_ELS_BLOCK_SIZE - lastDataChunkLength; + } + pDataIn += inLength; + + //set 0x80 byte + MCUXCLMEMORY_FP_MEMORY_SET(pDataIn, 0x80, 1u); + + //set 0x00 bytes (+3 0x00 bytes because inLength is only 32 bits while length field in padding is 64 bits + MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pDataIn + 1, 0x00, totalPaddingLength - MCUXCLHMAC_ELS_MIN_PADDING_LENGTH + 1u + 3u, totalPaddingLength - 1u); + pDataIn += totalPaddingLength - 1u; + + //length of the unpadded message in bits + //ELS requires that the length of the key is added as well + uint64_t lengthField = (uint64_t) inLength + MCUXCLELS_HMAC_PADDED_KEY_SIZE; + + *pDataIn-- = (uint8_t)(lengthField << 3); + *pDataIn-- = (uint8_t)(lengthField >> 5); + *pDataIn-- = (uint8_t)(lengthField >> 13); + *pDataIn-- = (uint8_t)(lengthField >> 21); + *pDataIn-- = (uint8_t)(lengthField >> 29); + + /* Set-up the HMAC ELS options */ + mcuxClEls_HmacOption_t hmac_options; + hmac_options.word.value = 0u; + + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pCtxEls->key)) + { + hmac_options.bits.extkey = MCUXCLELS_HMAC_EXTERNAL_KEY_ENABLE; + + /* Prepare the external HMAC key */ + MCUX_CSSL_FP_FUNCTION_CALL(prepareKeyResult, mcuxClHmac_prepareHMACKey(session, pCtxEls->key, pCtxEls->preparedHmacKey)); + + if(MCUXCLMAC_STATUS_OK != prepareKeyResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_prepareHMACKey), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pCtxEls->key)) + { + hmac_options.bits.extkey = MCUXCLELS_HMAC_EXTERNAL_KEY_DISABLE; + } + else + { + // error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxClEls_Hmac_Async( + hmac_options, + (mcuxClEls_KeyIndex_t) (mcuxClKey_getLoadedKeySlot(pCtxEls->key)), + (uint8_t const *) pCtxEls->preparedHmacKey, + pIn, + inLength + totalPaddingLength, + pOut)); + + if (MCUXCLELS_STATUS_OK_WAIT != result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pCtxEls->key)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_prepareHMACKey) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hmac_Async)); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if ((MCUXCLELS_STATUS_OK != resultWait)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pCtxEls->key)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_prepareHMACKey) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != pOut) + { + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(pOut, MCUXCLELS_HMAC_OUTPUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + *pOutLength = MCUXCLELS_HMAC_OUTPUT_SIZE; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT("NULL is used in code") + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Els, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pCtxEls->key)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_prepareHMACKey) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Hmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_CONDITIONAL(NULL != pOut, MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN) + ); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() + +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Init_Els, mcuxClHmac_InitEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Init_Els( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClHmac_Context_Generic_t * const pContext UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Init_Els); + //ELS HMAC doesn't support partial processing + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Els, MCUXCLMAC_STATUS_ERROR); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Update_Els, mcuxClHmac_UpdateEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Update_Els( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClHmac_Context_Generic_t * const pContext UNUSED_PARAM, + const uint8_t *const pIn UNUSED_PARAM, + uint32_t inLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Update_Els); + //HMAC doesn't support partial processing + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Update_Els, MCUXCLMAC_STATUS_ERROR); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Finalize_Els, mcuxClHmac_FinalizeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Finalize_Els( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClHmac_Context_Generic_t * const pContext UNUSED_PARAM, + uint8_t *const pOut UNUSED_PARAM, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Finalize_Els); + //HMAC doesn't support partial processing + *pOutLength = 0u; + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Els, MCUXCLMAC_STATUS_ERROR); +} + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClHmac_AlgorithmDescriptor_t mcuxClHmac_AlgorithmDescriptor_Els = { +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + .engineInit = mcuxClHmac_Engine_Init_Els, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Init_Els), + .engineUpdate = mcuxClHmac_Engine_Update_Els, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Update_Els), + .engineFinalize = mcuxClHmac_Engine_Finalize_Els, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Finalize_Els), + .engineOneshot = mcuxClHmac_Engine_Oneshot_Els, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Oneshot_Els), + .addPadding = NULL, + .protectionToken_addPadding = 0u, +}; diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Functions.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Functions.c new file mode 100644 index 000000000..16268651d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Functions.c @@ -0,0 +1,111 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Functions.c + * @brief Intermediate layer mcuxClHmac functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_compute, mcuxClMac_ComputeFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_compute( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC Algorithm types") + mcuxClHmac_Algorithm_t pAlgo = (mcuxClHmac_Algorithm_t) mode->common.pAlgorithm; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_compute, pAlgo->protectionToken_engineOneshot); + + uint32_t contextBuffer[MCUXCLHMAC_MAX_CONTEXT_SIZE_IN_WORDS]; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Generic_t *context = (mcuxClHmac_Context_Generic_t *)contextBuffer; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + context->common.pMode = mode; + context->key = (mcuxClKey_Descriptor_t *) key; + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineOneshot(session, context, pIn, inLength, pMac, pMacLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_compute, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_init, mcuxClMac_InitFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Generic_t * const pCtx = (mcuxClHmac_Context_Generic_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClHmac_Algorithm_t pAlgo = (mcuxClHmac_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_init, pAlgo->protectionToken_engineInit); + + pCtx->key = (mcuxClKey_Descriptor_t *) key; + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineInit(session, pCtx)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_init, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_process, mcuxClMac_ProcessFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Generic_t * const pCtx = (mcuxClHmac_Context_Generic_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClHmac_Algorithm_t pAlgo = (mcuxClHmac_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_process, pAlgo->protectionToken_engineUpdate); + + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineUpdate(session, pCtx, pIn, inLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_process, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_finish, mcuxClMac_FinishFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Generic_t * const pCtx = (mcuxClHmac_Context_Generic_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClHmac_Algorithm_t pAlgo = (mcuxClHmac_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_finish, pAlgo->protectionToken_engineFinalize); + + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineFinalize(session, pCtx, pMac, pMacLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_finish, result); +} + diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Helper.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Helper.c new file mode 100644 index 000000000..f5ba742c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Helper.c @@ -0,0 +1,119 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Helper.c + * @brief Helper functions of mcuxClHmac + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_createHmacMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_createHmacMode( + mcuxClMac_CustomMode_t mode, + mcuxClHash_Algo_t hashAlgorithm) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_createHmacMode); + + /* copy the common HMAC mode descriptor into the mode */ + MCUXCLMEMORY_FP_MEMORY_COPY((uint8_t *) &mode->common, (uint8_t const *) &mcuxClHmac_CommonModeDescriptor_Sw, sizeof(mcuxClHmac_CommonModeDescriptor_Sw)); + + /* Insert hashSize from the hashAlgorithm into the macByteSize field */ + mode->common.macByteSize = hashAlgorithm->hashSize; + + /* pCustom points to the end of the mode descriptor in memory, + assumes user allocated sufficient memory with MCUXCLMAC_HMAC_MODE_DESCRIPTOR_SIZE */ + uintptr_t pCustomLocation = (uintptr_t)mode + sizeof(mcuxClMac_ModeDescriptor_t); + mode->pCustom = (void *) (mcuxClHmac_ModeDescriptor_t *) pCustomLocation; + + mcuxClHmac_ModeDescriptor_t * hmacModeDescriptor = (mcuxClHmac_ModeDescriptor_t *) mode->pCustom; + hmacModeDescriptor->hashAlgorithm = (const mcuxClHash_AlgorithmDescriptor_t *) hashAlgorithm; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_createHmacMode, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_prepareHMACKey) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_prepareHMACKey( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + uint32_t * preparedHmacKey) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_prepareHMACKey); + + size_t alreadyFilledKeyDataSize = 0u; + uint8_t *pPreparedHmacKey = (uint8_t *) preparedHmacKey; + uint8_t *pKeyData = mcuxClKey_getLoadedKeyData(key); + uint32_t keySize = mcuxClKey_getSize(key); + + if(mcuxClKey_getSize(key) <= MCUXCLELS_HMAC_PADDED_KEY_SIZE) + { + /* Given key must be zero-padded up to MCUXCLELS_HMAC_PADDED_KEY_SIZE */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pPreparedHmacKey, + pKeyData, + keySize, + MCUXCLELS_HMAC_PADDED_KEY_SIZE); + + alreadyFilledKeyDataSize = keySize; + } + else + { + uint32_t hashOutputSize = 0u; + /* Given key must be hashed and then zero-padded up to MCUXCLELS_HMAC_PADDED_KEY_SIZE */ + MCUX_CSSL_FP_FUNCTION_CALL(hashResult, mcuxClHash_compute(session, + mcuxClHash_Algorithm_Sha256, + pKeyData, + (uint32_t) keySize, + pPreparedHmacKey, + &hashOutputSize)); + + if(MCUXCLHASH_STATUS_OK != hashResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_prepareHMACKey, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)); + } + + alreadyFilledKeyDataSize = MCUXCLHASH_OUTPUT_SIZE_SHA_256; + } + + /* Zero-pad the key */ + MCUXCLMEMORY_FP_MEMORY_SET(pPreparedHmacKey + alreadyFilledKeyDataSize, 0u, MCUXCLELS_HMAC_PADDED_KEY_SIZE - alreadyFilledKeyDataSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_prepareHMACKey, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((mcuxClKey_getSize(key) <= MCUXCLELS_HMAC_PADDED_KEY_SIZE), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL((mcuxClKey_getSize(key) > MCUXCLELS_HMAC_PADDED_KEY_SIZE), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_KeyTypes.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_KeyTypes.c new file mode 100644 index 000000000..ca765bd89 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_KeyTypes.c @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_KeyTypes.c + * @brief Instantiation of the key types supported by the mcuxClHmac component. */ + +#include +#include +#include +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +// HMAC internal only supports 256-bit keys +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_HmacSha256 = {.algoId = MCUXCLKEY_ALGO_ID_HMAC + MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY, .size = MCUXCLKEY_SIZE_256, .info = NULL}; + +const mcuxClKey_TypeDescriptor_t mcuxClKey_TypeDescriptor_Hmac_variableLength = {.algoId = MCUXCLKEY_ALGO_ID_HMAC + MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY, .size = 0u, .info = NULL}; + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Modes.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Modes.c new file mode 100644 index 000000000..5a5e573e8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Modes.c @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHmac_Modes.c + * @brief Definition of the mode descriptors for all provided HMAC modes + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * Constant top-level mode descriptors and common mode descriptors for custom modes + */ + +/* + * Common mode descriptor needed for constructor of HMAC mode + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_CommonModeDescriptor_t mcuxClHmac_CommonModeDescriptor_Sw = { + .compute = mcuxClHmac_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_compute), + .init = mcuxClHmac_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_init), + .process = mcuxClHmac_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_process), + .finish = mcuxClHmac_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_finish), + .macByteSize = 0u, /* To be set by create function */ + .pAlgorithm = (void *) &mcuxClHmac_AlgorithmDescriptor_Sw +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/** + * Top-level mode structure for HMAC using ELS + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClHmac_ModeDescriptor_SHA2_256_ELS = { + .common = { + .compute = mcuxClHmac_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_compute), + .init = mcuxClHmac_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_init), + .process = mcuxClHmac_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_process), + .finish = mcuxClHmac_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_finish), + .macByteSize = MCUXCLHMAC_ELS_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClHmac_AlgorithmDescriptor_Els + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Sw.c b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Sw.c new file mode 100644 index 000000000..3f7f577da --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/mcuxClHmac_Sw.c @@ -0,0 +1,397 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClHMac_Sw.c + * @brief Implementation of SW engine functions for the HMAC component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MCUXCLMAC_HMAC_IPAD_BYTE (0x36u) +#define MCUXCLMAC_HMAC_OPAD_BYTE (0x5cu) + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Init_Sw, mcuxClHmac_InitEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Init_Sw( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Init_Sw); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Sw_t * const pCtxSw = (mcuxClHmac_Context_Sw_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + const mcuxClHash_AlgorithmDescriptor_t *hashAlgo = ((mcuxClHmac_ModeDescriptor_t *) (pCtxSw->common.pMode->pCustom))->hashAlgorithm; + mcuxClKey_Descriptor_t * key = pCtxSw->key; + const uint32_t hashBlockSize = hashAlgo->blockSize; + + uint32_t keySize = mcuxClKey_getSize(key); + uint8_t *pKeyData = mcuxClKey_getLoadedKeyData(key); + size_t alreadyFilledKeyDataSize = 0u; + uint32_t *pPreparedHmacKey = mcuxClSession_allocateWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashBlockSize)); + if(NULL == pPreparedHmacKey) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /*********************************************************************************************************/ + /* Prepare a block-sized key from the key given in the Hmac context (pContext) and store it in work area */ + /*********************************************************************************************************/ + if(keySize > hashBlockSize) /* key is too long */ + { + uint32_t hashOutputSize = 0u; + /* Given key must be hashed and then zero-padded up to hashBlockSize */ + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_compute, mcuxClHash_compute(session, + hashAlgo, + pKeyData, + keySize, + (uint8_t *)pPreparedHmacKey, + &hashOutputSize)); + + if(MCUXCLHASH_STATUS_OK != result_Hash_compute) + { + /* Free workarea (pPreparedHmacKey) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashBlockSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + alreadyFilledKeyDataSize = MCUXCLHASH_OUTPUT_SIZE_SHA_256; + } + else /* key is not too long */ + { + /* Given key must be zero-padded up to hashBlockSize */ + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pPreparedHmacKey, + pKeyData, + keySize, + hashBlockSize); + alreadyFilledKeyDataSize = keySize; + } + + /* Zero-pad the key */ + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *)pPreparedHmacKey + alreadyFilledKeyDataSize, 0u, hashBlockSize - alreadyFilledKeyDataSize); + + /***************************************************************************************************************/ + /* Store the prepared block-sized key in the Hmac context for later use in the outer hash during finalization */ + /***************************************************************************************************************/ + + MCUXCLMEMORY_FP_MEMORY_COPY(pCtxSw->preparedHmacKey, pPreparedHmacKey, hashBlockSize); + + /********************************************************************/ + /* Initialize a Hash context for multipart within the Hmac context */ + /********************************************************************/ + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + pCtxSw->hashCtx = (mcuxClHash_Context_t) &(pCtxSw->hashContextBuffer); /* The content of the hash context is stored in the Hmac context */ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_init, mcuxClHash_init( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxClHash_Algo_t algorithm: */ hashAlgo + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_init) + { + /* Free workarea (pPreparedHmacKey) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashBlockSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /*****************************************************************************************************************/ + /* XOR the ipad to the block-sized key in the work area and Hash-process it (the first block of the inner hash) */ + /*****************************************************************************************************************/ + for(size_t i = 0u; i < hashBlockSize; i++ ) + { + ((uint8_t *)pPreparedHmacKey)[i] ^= MCUXCLMAC_HMAC_IPAD_BYTE; + } + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_process, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_InputBuffer_t in: */ (uint8_t *) pPreparedHmacKey, + /* uint32_t inSize: */ hashBlockSize + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_process) + { + /* Free workarea (pPreparedHmacKey) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashBlockSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /* Free workarea (pPreparedHmacKey) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashBlockSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Init_Sw, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((keySize <= hashBlockSize), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + ), + MCUX_CSSL_FP_CONDITIONAL((keySize > hashBlockSize), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_init), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process) + ); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Update_Sw, mcuxClHmac_UpdateEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Update_Sw( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Update_Sw); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Sw_t * const pCtxSw = (mcuxClHmac_Context_Sw_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_process, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_InputBuffer_t in: */ pIn, + /* uint32_t inSize: */ inLength + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_process) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Update_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Update_Sw, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Finalize_Sw, mcuxClHmac_FinalizeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Finalize_Sw( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Finalize_Sw); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different HMAC context types") + mcuxClHmac_Context_Sw_t * const pCtxSw = (mcuxClHmac_Context_Sw_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + const mcuxClHash_AlgorithmDescriptor_t *hashAlgo = ((mcuxClHmac_ModeDescriptor_t *) (pCtxSw->common.pMode->pCustom))->hashAlgorithm; + const uint32_t hashSize = hashAlgo->hashSize; + const uint32_t hashBlockSize = hashAlgo->blockSize; + + /****************************************************************************************************************************************/ + /* Finalize the inner hash by calling Hash-finalize with the Hash context stored in the Hmac context and write the digest to work area */ + /****************************************************************************************************************************************/ + + uint32_t *pInnerHash = mcuxClSession_allocateWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + if(NULL == pInnerHash) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_ERROR); + } + + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_finish_1, mcuxClHash_finish( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_Buffer_t pOut */ (uint8_t *) pInnerHash, + /* uint32_t *const pOutSize, */ &hashOutputSize + )); + if((hashOutputSize != hashSize) || (MCUXCLHASH_STATUS_OK != result_Hash_finish_1)) + { + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /**********************************************************************/ + /* Initialize a new Hash context (re-using the old context's memory) */ + /**********************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_init, mcuxClHash_init( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxClHash_Algo_t algorithm: */ hashAlgo + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_init) + { + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /***********************************************************************************************************************************/ + /* XOR the opad to the block-sized key that is stored in the Hmac context and Hash-process it (the first block of the outer hash) */ + /***********************************************************************************************************************************/ + + uint8_t *pKeyData = (uint8_t *) pCtxSw->preparedHmacKey; + + for(size_t i = 0u; i < hashBlockSize; i++ ) + { + pKeyData[i] ^= MCUXCLMAC_HMAC_OPAD_BYTE; + } + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_process_1, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_InputBuffer_t in: */ pKeyData, + /* uint32_t inSize: */ hashBlockSize + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_process_1) + { + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /********************************************************************************/ + /* Hash-process the digest from before, residing in work area (the inner hash) */ + /********************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_process_2, mcuxClHash_process( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_InputBuffer_t in: */ (uint8_t *) pInnerHash, + /* uint32_t inSize: */ hashSize + )); + if(MCUXCLHASH_STATUS_OK != result_Hash_process_2) + { + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /**********************************************************************************************************************/ + /* Finalize the outer hash by calling Hash-finalize, write the resulting digest to pOut and its length to pOutLength */ + /**********************************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(result_Hash_finish_2, mcuxClHash_finish( + /* mcuxCLSession_Handle_t session: */ session, + /* mcuxClHash_Context_t context: */ pCtxSw->hashCtx, + /* mcuxCl_Buffer_t pOut */ pOut, + /* uint32_t *const pOutSize, */ pOutLength + )); + if((*pOutLength != hashSize) || (MCUXCLHASH_STATUS_OK != result_Hash_finish_2)) + { + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + /* Free workarea (pInnerHash) */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLHMAC_INTERNAL_COMPUTE_CPUWORDS(hashSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Finalize_Sw, MCUXCLMAC_STATUS_OK, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_finish), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_init), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_process)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClHmac_Engine_Oneshot_Sw, mcuxClHmac_ComputeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClHmac_Engine_Oneshot_Sw( + mcuxClSession_Handle_t session, + mcuxClHmac_Context_Generic_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + /* [Design] + - TODO: In my opinion, we cannot save much when doing Hmac_Oneshot except for the storing of the block-sized key in context. + We could oneshot the outer hash instead of multipart (with just two parts), but we have a hash context from the + inner hash anyway, so we can just as well re-use that. + So it's probably easiest to just call Hmac_Init, Hmac_Update, Hmac_Finalize here. + Otherwise, here's the slightly optimized design, leaving out the key-storing: + + - Prepare a block-sized key from the key given in the Hmac context (pContext) and store it in work area + - If keySize > blockSize + - Hash the key in OneShot + - Append the digest with (blockSize - digestSize) zero bytes such that it fills one hash block + - Else just append the key with (blockSize - keySize) zero bytes such that it fills one hash block + - Initialize a Hash context for multipart + - XOR the ipad to the block-sized key in the work area and Hash-process it (the first block of the inner hash) + - Hash-process the input pIn with length inLength using the Hash context + - Finalize the inner hash by calling Hash-finalize with the Hash context and write the digest to work area + - Initialize a new Hash context (re-using the old context's memory) + - XOR ipad^opad (to remove the ipad from before) to the block-sized key in the work area and Hash-process it (the first block of the outer hash) + - Hash-process the digest from before (the inner hash) + - Finalize the outer hash by calling Hash-finalize, write the resulting digest to pOut and its length to pOutLength + */ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClHmac_Engine_Oneshot_Sw); + + MCUX_CSSL_FP_FUNCTION_CALL(result_HMAC_init, mcuxClHmac_Engine_Init_Sw( + session, + pContext + )); + if(MCUXCLMAC_STATUS_OK != result_HMAC_init) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result_HMAC_update, mcuxClHmac_Engine_Update_Sw( + session, + pContext, + pIn, + inLength + )); + if(MCUXCLMAC_STATUS_OK != result_HMAC_update) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(result_HMAC_finalize, mcuxClHmac_Engine_Finalize_Sw( + session, + pContext, + pOut, + pOutLength + )); + if(MCUXCLMAC_STATUS_OK != result_HMAC_finalize) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Sw, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClHmac_Engine_Oneshot_Sw, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Init_Sw), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Update_Sw), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Finalize_Sw)); +} + +const mcuxClHmac_AlgorithmDescriptor_t mcuxClHmac_AlgorithmDescriptor_Sw = { + .engineInit = mcuxClHmac_Engine_Init_Sw, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Init_Sw), + .engineUpdate = mcuxClHmac_Engine_Update_Sw, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Update_Sw), + .engineFinalize = mcuxClHmac_Engine_Finalize_Sw, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Finalize_Sw), + .engineOneshot = mcuxClHmac_Engine_Oneshot_Sw, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHmac_Engine_Oneshot_Sw), + .addPadding = NULL, +}; diff --git a/components/els_pkc/src/comps/mcuxClHmac/src/size/size.c b/components/els_pkc/src/comps/mcuxClHmac/src/size/size.c new file mode 100644 index 000000000..7c7019f40 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClHmac/src/size/size.c @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: size.c + * @brief: This file contains objects which will be used to measure size of particular types. + * + */ + +#include +#include + +#include +#include +#include + +/*************************/ +/**** Work area sizes ****/ +/*************************/ + +MCUX_CSSL_ANALYSIS_START_PATTERN_OBJ_SIZES() + +/* Context and WA for MAC computation */ +volatile mcuxClHmac_Context_Sw_t mcuxClHmac_Context_Sw; + +volatile mcuxClHmac_Context_Els_t mcuxClHmac_Context_Els; + +volatile uint8_t mcuxClHmac_Context_Max[MCUXCLHMAC_INTERNAL_MAX_CONTEXT_SIZE]; + + +volatile uint8_t mcuxClHmac_WorkArea_Init[MCUXCLHMAC_INTERNAL_WACPU_INIT]; +volatile uint8_t mcuxClHmac_WorkArea_Finish[MCUXCLHMAC_INTERNAL_WACPU_FINISH]; +volatile uint8_t mcuxClHmac_WorkArea_Max[MCUXCLHMAC_INTERNAL_MAX_WACPU]; +volatile uint8_t mcuxClHmac_WorkArea_Process[4u]; + + + +/* Mode-specific structures */ +volatile uint8_t mcuxClHmac_ModeDescriptor[sizeof(mcuxClMac_ModeDescriptor_t) + sizeof(mcuxClHmac_ModeDescriptor_t)]; + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_OBJ_SIZES() diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Functions_Internal.h b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Functions_Internal.h new file mode 100644 index 000000000..b1fa69027 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Functions_Internal.h @@ -0,0 +1,338 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Functions_Internal.h + * @brief Internal function definitions for the mcuxClKey component + */ + +#ifndef MCUXCLKEY_FUNCTIONS_INTERNAL_H_ +#define MCUXCLKEY_FUNCTIONS_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/************************************************************ + * INTERNAL INLINED FUNCTIONS TO ACCESS THE KEY DESCRIPTOR + ************************************************************/ + +/** + * Returns the key data pointer of the key handle + * + * @return Key data pointer of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getKeyData) +static inline uint8_t * mcuxClKey_getKeyData(mcuxClKey_Handle_t key) +{ + return key->container.pData; +} + +/** + * Sets the key data pointer of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setKeyData) +static inline void mcuxClKey_setKeyData(mcuxClKey_Handle_t key, uint8_t * pKeyData) +{ + key->container.pData = pKeyData; +} + + +/** + * Returns the aux data pointer of the key handle + * + * @return Aux data pointer of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getAuxData) +static inline uint8_t * mcuxClKey_getAuxData(mcuxClKey_Handle_t key) +{ + return key->container.pAuxData; +} + +/** + * Sets the aux data pointer of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setAuxData) +static inline void mcuxClKey_setAuxData(mcuxClKey_Handle_t key, uint8_t * pAuxData) +{ + key->container.pAuxData = pAuxData; +} + + +/** + * Sets the protection descriptor pointer of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setProtectionType) +static inline void mcuxClKey_setProtectionType(mcuxClKey_Handle_t key, const mcuxClKey_ProtectionDescriptor_t * pProtection) +{ + key->protection = pProtection; +} + +/** + * Returns the linked data pointer of the key handle + * + * @return linked data pointer of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getLinkedData) +static inline void * mcuxClKey_getLinkedData(mcuxClKey_Handle_t key) +{ + return key->pLinkedData; +} + +/** + * Sets the linked data pointer of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setLinkedData) +static inline void mcuxClKey_setLinkedData(mcuxClKey_Handle_t key, void * pLinkedData) +{ + key->pLinkedData = pLinkedData; +} + +/** + * Gets the type structure of the key handle + * + * @return Type structure of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getTypeDescriptor) +static inline mcuxClKey_TypeDescriptor_t mcuxClKey_getTypeDescriptor(mcuxClKey_Handle_t key) +{ + return key->type; +} + +/** + * Sets the type structure of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setTypeDescriptor) +static inline void mcuxClKey_setTypeDescriptor(mcuxClKey_Handle_t key, mcuxClKey_TypeDescriptor_t pType) +{ + key->type = pType; +} + + +/** + * Gets the type info field of the key handle, which might contain pointer to ECC domain parameters + * + * @return Type info of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getTypeInfo) +static inline void * mcuxClKey_getTypeInfo(mcuxClKey_Handle_t key) +{ + return key->type.info; +} + + +/** + * Returns the key size in bytes of the key handle + * + * @return Key size in bytes of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getSize) +static inline mcuxClKey_Size_t mcuxClKey_getSize(mcuxClKey_Handle_t key) +{ + return key->type.size; +} + + +/** + * Returns the algorithm identifier of the key handle + * + * @return Algorithm identifier of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getAlgoId) +static inline mcuxClKey_AlgorithmId_t mcuxClKey_getAlgoId(mcuxClKey_Handle_t key) +{ + return key->type.algoId; +} + +/** + * Returns the algorithm of the key handle + * + * @return Algorithm identifier of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getAlgorithm) +static inline mcuxClKey_AlgorithmId_t mcuxClKey_getAlgorithm(mcuxClKey_Handle_t key) +{ + return key->type.algoId & MCUXCLKEY_ALGO_ID_ALGO_MASK; +} + +/** + * Returns the key usage of the key handle + * + * @return Algorithm identifier of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getKeyUsage) +static inline mcuxClKey_AlgorithmId_t mcuxClKey_getKeyUsage(mcuxClKey_Handle_t key) +{ + return key->type.algoId & MCUXCLKEY_ALGO_ID_USAGE_MASK; +} + + +/** + * Returns the pointer of the loaded key data of the key handle + * + * @return Pointer to the loaded key data + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getLoadedKeyData) +static inline uint8_t * mcuxClKey_getLoadedKeyData(mcuxClKey_Handle_t key) +{ + return key->location.pData; +} + +/** + * Sets the pointer of the (to be) loaded key data + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setLoadedKeyData) +static inline void mcuxClKey_setLoadedKeyData(mcuxClKey_Handle_t key, uint32_t * pKeyDataLoadLocation) +{ + key->location.pData = (uint8_t *) pKeyDataLoadLocation; +} + + +/** + * Returns the length of the loaded key data + * + * @return Length of to the loaded key data of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getLoadedKeyLength) +static inline uint32_t mcuxClKey_getLoadedKeyLength(mcuxClKey_Handle_t key) +{ + return key->location.length; +} + +/** + * Sets the length of the loaded key data + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setLoadedKeyLength) +static inline void mcuxClKey_setLoadedKeyLength(mcuxClKey_Handle_t key, uint32_t keyLength) +{ + key->location.length = keyLength; +} + + +/** + * Returns the hardware slot of the loaded key + * + * @return Hardware slot of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getLoadedKeySlot) +static inline uint32_t mcuxClKey_getLoadedKeySlot(mcuxClKey_Handle_t key) +{ + return key->location.slot; +} + +/** + * Sets the pointer of the (to be) loaded data of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setLoadedKeySlot) +static inline void mcuxClKey_setLoadedKeySlot(mcuxClKey_Handle_t key, uint32_t keySlot) +{ + key->location.slot = keySlot; +} + + +/** + * Returns the load status of the key handle + * + * @return Load status of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getLoadStatus) +static inline mcuxClKey_LoadStatus_t mcuxClKey_getLoadStatus(mcuxClKey_Handle_t key) +{ + return key->location.status; +} + +/** + * Sets the load status of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setLoadStatus) +static inline void mcuxClKey_setLoadStatus(mcuxClKey_Handle_t key, mcuxClKey_LoadStatus_t loadStatus) +{ + key->location.status = loadStatus; +} + + +/** + * Returns the pointer to the parent key of the key handle + * + * @return Pointer to the parent key of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getParentKey) +static inline mcuxClKey_Descriptor_t * mcuxClKey_getParentKey(mcuxClKey_Handle_t key) +{ + return key->container.parentKey; +} + +/** + * Sets the pointer to the parent key of the key handle + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setParentKey) +static inline void mcuxClKey_setParentKey(mcuxClKey_Handle_t key, mcuxClKey_Descriptor_t * pParentKey) +{ + key->container.parentKey = pParentKey; +} + + +/** + * Returns the size of the key data container + * + * @return Size of the key data container of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getKeyContainerSize) +static inline uint32_t mcuxClKey_getKeyContainerSize(mcuxClKey_Handle_t key) +{ + return key->container.length; +} + +/** + * Sets the size of the key data container of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setKeyContainerSize) +static inline void mcuxClKey_setKeyContainerSize(mcuxClKey_Handle_t key, uint32_t keyContainerSize) +{ + key->container.length = keyContainerSize; +} + + +/** + * Returns the used size of the key data container + * + * @return Used size of the key data container of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_getKeyContainerUsedSize) +static inline uint32_t mcuxClKey_getKeyContainerUsedSize(mcuxClKey_Handle_t key) +{ + return key->container.used; +} + +/** + * Sets the used size of the key data container of the given key + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setKeyContainerUsedSize) +static inline void mcuxClKey_setKeyContainerUsedSize(mcuxClKey_Handle_t key, uint32_t keyContainerUsedSize) +{ + key->container.used = keyContainerUsedSize; +} + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_FUNCTIONS_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Internal.h b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Internal.h new file mode 100644 index 000000000..4796362f1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Internal.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLKEY_INTERNAL_H_ +#define MCUXCLKEY_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Protection_Internal.h b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Protection_Internal.h new file mode 100644 index 000000000..aa0a0e659 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Protection_Internal.h @@ -0,0 +1,73 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClKey_Protection_Internal.h + * @brief Internal header of mcuxClKey_Protection + */ + +#ifndef MCUXCLKEY_PROTECTION_INTERNAL_H_ +#define MCUXCLKEY_PROTECTION_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * INTERNAL FUNCTIONS + **********************************************/ +/*! @brief Internal functions for the key component */ + +/** + * @brief no key protection function + * + * @param[in] key The key of type mcuxClKey_Handle_t + * + * @return status + * @retval MCUXCLKEY_STATUS_ERROR On error + * @retval MCUXCLKEY_STATUS_OK On success + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_protect_fct_none, mcuxClKey_LoadFuncPtr_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_protect_fct_none( + mcuxClKey_Handle_t key + ); + +/** + * @brief ckdf key protection function + * + * @param[in] key The key of type mcuxClKey_Handle_t + * + * The key properties must be set before calling this function + * by calling @ref mcuxClKey_setKeyproperties + * + * @return status + * @retval MCUXCLKEY_STATUS_ERROR On error + * @retval MCUXCLKEY_STATUS_OK On success + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_protect_fct_ckdf, mcuxClKey_LoadFuncPtr_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_protect_fct_ckdf( + mcuxClKey_Handle_t key + ); + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_PROTECTION_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Types_Internal.h b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Types_Internal.h new file mode 100644 index 000000000..f85125d11 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/internal/mcuxClKey_Types_Internal.h @@ -0,0 +1,174 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Types_Internal.h + * @brief Type definitions for the mcuxClKey component + */ + +#ifndef MCUXCLKEY_TYPES_INTERNAL_H_ +#define MCUXCLKEY_TYPES_INTERNAL_H_ + +#include +#include + +#include // Exported features flags header +#include + + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTION TYPE DEFINITIONS + **********************************************/ + +/** + * @brief Functions to load a key into coprocessor or memory buffer. + * + * @param[in] key Key handle that provides information to load the key + * + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClKey_LoadFuncPtr_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) (*mcuxClKey_LoadFuncPtr_t)(mcuxClKey_Handle_t key)); + +/** + * @brief Functions to store a key. + * + * @param[in] key Key handle that provides information to store the key + * + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClKey_StoreFuncPtr_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) (*mcuxClKey_StoreFuncPtr_t)(mcuxClKey_Handle_t key)); + +/** + * @brief Functions to flush a key from coprocessor or memory buffer. + * + * @param[in] key Key handle that provides information to flush the key + * + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClKey_FlushFuncPtr_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) (*mcuxClKey_FlushFuncPtr_t)(mcuxClKey_Handle_t key)); + + + + +/********************************************** + * DATA TYPE DEFINITIONS + **********************************************/ + +/** + * @brief Type for key load location options. + */ +typedef uint16_t mcuxClKey_LoadStatus_t; + + +/********************************************** + * STRUCTURES + **********************************************/ + +/** + * @brief Struct to map algorithm id and size. + */ +struct mcuxClKey_TypeDescriptor { + mcuxClKey_AlgorithmId_t algoId; ///< the identifier of the algorithm, refer to #mcuxClKey_KeyTypes + /* uint16_t PADDING_FOR_32BIT_ALIGNMENT; */ + mcuxClKey_Size_t size; ///< the key size for the key type in bytes, refer to #mcuxClKey_KeySize + void * info; ///< pointer to additional information for this key type (e.g. curve parameters, public exponent) +}; + +/** + * @brief Struct for key internal storage information (destination key) + * Key data can be provided in @param pData or loaded to a @param slot + * @param status is one of MCUXCLKEY_LOADSTATUS_ + */ +typedef struct mcuxClKey_Location { + uint8_t * pData; ///< Pointer to the data buffer + uint32_t length; ///< Length of the data buffer + uint32_t slot; ///< Key slot to which the key is loaded + mcuxClKey_LoadStatus_t status; ///< Load status of the key + uint16_t PADDING_FOR_32BIT_ALIGNMENT; +} mcuxClKey_Location_t; + +/** + * @brief Struct for key external storage information (source for mcuxClKey_Location_t) + */ +typedef struct mcuxClKey_Container { + uint8_t * pData; ///< Pointer to the data buffer + uint32_t length; ///< Length of the data buffer + uint32_t used; ///< Length of the used part of the data buffer + mcuxClKey_Descriptor_t * parentKey; ///< Handle of the parent of the key + uint8_t * pAuxData; ///< Pointer to auxiliary data needed by the key protection mechanism +} mcuxClKey_Container_t; + +/** + * @brief Type for mapping load, store and flush functions. + */ +struct mcuxClKey_ProtectionDescriptor { + mcuxClKey_LoadFuncPtr_t loadFunc; ///< Function pointer to a load function + mcuxClKey_StoreFuncPtr_t storeFunc; ///< Function pointer to an store function + uint32_t protectionTokenLoad; ///< Protection token of the load function + uint32_t protectionTokenStore; ///< Protection token of the store function +}; + +/** + * @brief Struct of the key handle. + */ +struct mcuxClKey_Descriptor { + mcuxClKey_Container_t container; ///< Container for external (protected) storage of the key, it cannot be used directly by an operation + /* TODO CLNS-5378: use pointer to the keyType instead of full struct? To be discussed */ + mcuxClKey_TypeDescriptor_t type; ///< Type of the key + mcuxClKey_Location_t location; ///< Internal location of the key + const mcuxClKey_ProtectionDescriptor_t * protection; ///< Protection mechanism applied to the key stored in the container + void * pLinkedData; ///< Pointer to auxiliary data linked to the key +}; + +/** + * @brief Function prototype for protocol specific key generation function pointer. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClKey_KeyGenFct_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) (* mcuxClKey_KeyGenFct_t)( + mcuxClSession_Handle_t pSession, + mcuxClKey_Generation_t generation, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey +)); + +/** + * @brief Struct of generation descriptor + */ +struct mcuxClKey_GenerationDescriptor +{ + mcuxClKey_KeyGenFct_t pKeyGenFct; ///< Pointer to the protocol specific key pair generation function + uint32_t protectionTokenKeyGenFct; ///< Protection token of the protocol specific key generation function + const void *pProtocolDescriptor; ///< Pointer to additional parameters for the protocol specific key generation function +}; + + + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_TYPES_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey.h new file mode 100644 index 000000000..f6c5b5f05 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey.h @@ -0,0 +1,32 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey.h + * @brief Top-level include file for the mcuxClKey component + * + * @defgroup mcuxClKey mcuxClKey + * @brief mcuxClKey component + */ + +#ifndef MCUXCLKEY_H_ +#define MCUXCLKEY_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#endif /* MCUXCLKEY_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Constants.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Constants.h new file mode 100644 index 000000000..8e5f8f7a4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Constants.h @@ -0,0 +1,146 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Constants.h + * @brief Constants for the mcuxClKey component. + */ + +#ifndef MCUXCLKEY_CONSTANTS_H_ +#define MCUXCLKEY_CONSTANTS_H_ + +#include +#include // Exported features flags header + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClKey_Macros mcuxClKey_Macros + * @brief Defines all macros of @ref mcuxClKey + * @ingroup mcuxClKey + * @{ + */ +/** + * @defgroup MCUXCLKEY_STATUS_ MCUXCLKEY_STATUS_ + * @brief Return code definitions + * @{ + */ +#define MCUXCLKEY_STATUS_OK ((mcuxClKey_Status_t) 0x07772E03u) ///< Key operation successful +#define MCUXCLKEY_STATUS_ERROR ((mcuxClKey_Status_t) 0x07775330u) ///< Error occured during Key operation +#define MCUXCLKEY_STATUS_FAILURE ((mcuxClKey_Status_t) 0x07775334u) ///< Failure during execution +#define MCUXCLKEY_STATUS_INVALID_INPUT ((mcuxClKey_Status_t) 0x07775338u) ///< Invalid input +#define MCUXCLKEY_STATUS_FAULT_ATTACK ((mcuxClKey_Status_t) 0x0777F0F0u) ///< Fault attack detected +#define MCUXCLKEY_STATUS_CRC_NOT_OK ((mcuxClKey_Status_t) 0x077753FCu) ///< CRC verification failed +#define MCUXCLKEY_STATUS_NOT_SUPPORTED ((mcuxClKey_Status_t) 0x07775370u) ///< Functionality not supported +/** @} */ + +/** + * @defgroup MCUXCLKEY_LOADSTATUS_ MCUXCLKEY_LOADSTATUS_ + * @brief Load location options + * @ingroup mcuxClKey_Macros + * @{ */ +#define MCUXCLKEY_LOADSTATUS_NOTLOADED 0x0000u ///< Key not loaded +#define MCUXCLKEY_LOADSTATUS_MEMORY 0x0001u ///< Key is loaded to memory +#define MCUXCLKEY_LOADSTATUS_COPRO 0x0002u ///< Key is loaded to HW IP slot +#define MCUXCLKEY_LOADSTATUS_KEEPLOADED 0x8000u ///< Do not flush the key after the operation (for Symmetric keys only) +/** @} */ + + +/* Define algorithm IDs */ +/** + * @defgroup mcuxClKey_KeyTypes mcuxClKey_KeyTypes + * @brief Defines all key types of @ref mcuxClKey + * @ingroup mcuxClKey_Macros + * @{ + */ +#define MCUXCLKEY_ALGO_ID_AES 0x0F01u ///< AES key +#define MCUXCLKEY_ALGO_ID_RSA 0x0E02u ///< RSA key +#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP 0x0D03u ///< ECC key using Short Weierstrass Curve over GF(p) +#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GF2M 0x0C04u ///< ECC key using Short Weierstrass Curve over GF(2^m) +#define MCUXCLKEY_ALGO_ID_ECC_MONTDH 0x0B05u ///< ECC key for MontDH key exchange scheme +#define MCUXCLKEY_ALGO_ID_ECC_EDDSA 0x0A06u ///< ECC key for EdDSA signature scheme +#define MCUXCLKEY_ALGO_ID_HMAC 0x0907u ///< HMAC key +#define MCUXCLKEY_ALGO_ID_SM4 0x0808u ///< SM4 key +#define MCUXCLKEY_ALGO_ID_SM2 0x0809u ///< SM2 key +#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_EPHEMERAL_CUSTOM 0x0709u ///< ECC key using Short Weierstrass Curve over GF(p) with ephemeral custom domain parameters +#define MCUXCLKEY_ALGO_ID_ECC_SHWS_GFP_STATIC_CUSTOM 0x060Au ///< ECC key using Short Weierstrass Curve over GF(p) with static custom domain parameters +#define MCUXCLKEY_ALGO_ID_ALGO_MASK 0x0FFFu ///< Mask for Algorithm + +#define MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY 0x0000u ///< Symmetric key +#define MCUXCLKEY_ALGO_ID_PUBLIC_KEY 0x8000u ///< Public key +#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY 0x4000u ///< Private key +#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT 0x6000u ///< Private RSA key in CRT format +#define MCUXCLKEY_ALGO_ID_KEY_PAIR 0xC000u ///< Key pair +#define MCUXCLKEY_ALGO_ID_PRIVATE_KEY_CRT_DFA 0xE000u ///< RSA key pair, with the private part in CRT format + +#define MCUXCLKEY_ALGO_ID_USAGE_MASK 0xF000u ///< Mask for Key Usage +/** @} */ + +/* Define key sizes */ +/** + * @defgroup mcuxClKey_KeySize mcuxClKey_KeySize + * @brief Defines all key sizes of @ref mcuxClKey + * @ingroup mcuxClKey + * @{ + */ +#define MCUXCLKEY_SIZE_NOTUSED 0u ///< key length field is not used (e.g. ECC keys) +#define MCUXCLKEY_SIZE_128 16u ///< 128 bit key, size in bytes +#define MCUXCLKEY_SIZE_160 20u ///< 160 bit key, size in bytes +#define MCUXCLKEY_SIZE_192 24u ///< 192 bit key, size in bytes +#define MCUXCLKEY_SIZE_224 28u ///< 224 bit key, size in bytes +#define MCUXCLKEY_SIZE_256 32u ///< 256 bit key, size in bytes +#define MCUXCLKEY_SIZE_320 40u ///< 320 bit key, size in bytes +#define MCUXCLKEY_SIZE_384 48u ///< 348 bit key, size in bytes +#define MCUXCLKEY_SIZE_512 64u ///< 512 bit key, size in bytes +#define MCUXCLKEY_SIZE_521 66u ///< 521 bit key, size in bytes +#define MCUXCLKEY_SIZE_1024 1024u ///< 1024 bit key, size in bits +#define MCUXCLKEY_SIZE_2048 2048u ///< 2048 bit key, size in bits +#define MCUXCLKEY_SIZE_3072 3072u ///< 3072 bit key, size in bits +#define MCUXCLKEY_SIZE_4096 4096u ///< 4096 bit key, size in bits +#define MCUXCLKEY_SIZE_6144 6144u ///< 6144 bit key, size in bits +#define MCUXCLKEY_SIZE_8192 8192u ///< 8192 bit key, size in bits + +// TODO CLNS-6135: replace these divides by a macro that ensures rounding up +#define MCUXCLKEY_SIZE_128_IN_WORDS (MCUXCLKEY_SIZE_128 / sizeof(uint32_t)) ///< 128 bit key, size in words +#define MCUXCLKEY_SIZE_160_IN_WORDS (MCUXCLKEY_SIZE_160 / sizeof(uint32_t)) ///< 160 bit key, size in words +#define MCUXCLKEY_SIZE_192_IN_WORDS (MCUXCLKEY_SIZE_192 / sizeof(uint32_t)) ///< 192 bit key, size in words +#define MCUXCLKEY_SIZE_224_IN_WORDS (MCUXCLKEY_SIZE_224 / sizeof(uint32_t)) ///< 224 bit key, size in words +#define MCUXCLKEY_SIZE_256_IN_WORDS (MCUXCLKEY_SIZE_256 / sizeof(uint32_t)) ///< 256 bit key, size in words +#define MCUXCLKEY_SIZE_320_IN_WORDS (MCUXCLKEY_SIZE_320 / sizeof(uint32_t)) ///< 320 bit key, size in words +#define MCUXCLKEY_SIZE_384_IN_WORDS (MCUXCLKEY_SIZE_384 / sizeof(uint32_t)) ///< 348 bit key, size in words +#define MCUXCLKEY_SIZE_512_IN_WORDS (MCUXCLKEY_SIZE_512 / sizeof(uint32_t)) ///< 512 bit key, size in words +#define MCUXCLKEY_SIZE_521_IN_WORDS ((MCUXCLKEY_SIZE_521 + sizeof(uint32_t) - 1u) / sizeof(uint32_t)) ///< 521 bit key, size in words +#define MCUXCLKEY_SIZE_1024_IN_WORDS (MCUXCLKEY_SIZE_1024 / (sizeof(uint32_t) * 8u)) ///< 1024 bit key, size in words +#define MCUXCLKEY_SIZE_2048_IN_WORDS (MCUXCLKEY_SIZE_2048 / (sizeof(uint32_t) * 8u)) ///< 2048 bit key, size in words +#define MCUXCLKEY_SIZE_3072_IN_WORDS (MCUXCLKEY_SIZE_3072 / (sizeof(uint32_t) * 8u)) ///< 3072 bit key, size in words +#define MCUXCLKEY_SIZE_4096_IN_WORDS (MCUXCLKEY_SIZE_4096 / (sizeof(uint32_t) * 8u)) ///< 4096 bit key, size in words +#define MCUXCLKEY_SIZE_6144_IN_WORDS (MCUXCLKEY_SIZE_6144 / (sizeof(uint32_t) * 8u)) ///< 6144 bit key, size in words +#define MCUXCLKEY_SIZE_8192_IN_WORDS (MCUXCLKEY_SIZE_8192 / (sizeof(uint32_t) * 8u)) ///< 8192 bit key, size in words +/** @} */ + + + +/** + * @def MCUXCLKEY_WA_SIZE_MAX + * @brief Define the max workarea size required for this component + */ +#define MCUXCLKEY_WA_SIZE_MAX 0U + +/** + * @def MCUXCLKEY_INVALID_KEYSLOT + * @brief Define the value for an invalid key slot. + */ +#define MCUXCLKEY_INVALID_KEYSLOT 0xFFu + +#endif /* MCUXCLKEY_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Functions.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Functions.h new file mode 100644 index 000000000..be2365bbd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Functions.h @@ -0,0 +1,239 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Functions.h + * @brief Top-level API of the mcuxClKey component. It is capable to load and flush + * keys into memory locations or coprocessors. + */ + +#ifndef MCUXCLKEY_FUNCTIONS_H_ +#define MCUXCLKEY_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @defgroup mcuxClKey Key API + * @brief Key handling operations. + * @ingroup mcuxClAPI + */ + +/** + * @defgroup mcuxClKey_Functions mcuxClKey_Functions + * @brief Defines all functions of @ref mcuxClKey + * @ingroup mcuxClKey + * @{ + */ + +/** + * @brief Initializes a key handle. + * + * Initializes a key handle with default protection values. + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in,out] key Key handle that will be initialized + * @param[in] type Define which key type shall be initialized + * @param[in] pKeyData Provide pointer to source data of the key. This can be a pointer to a plain key buffer, a share, or a key blob. The protection function defines the purpose of this parameter + * @param[in] keyDataLength Length of the provided key data @p pKeyData + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_init( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + mcuxClKey_Type_t type, + mcuxCl_InputBuffer_t pKeyData, + uint32_t keyDataLength +); + +/** + * @brief Establishes a key pair link between a private and public key handle. + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in,out] privKey Key handle of private key + * @param[in,out] pubKey Key handle of public key + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_linkKeyPair) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_linkKeyPair( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey +); + +/** + * @brief Configures they protection mechanism for to the given key handle. + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in,out] key Key handle that will be configured + * @param[in] protection Define the protection and flush mechanism that shall be used with this @p key + * @param[in] pAuxData Provide pointer to additional data the protection function may use + * @param[in] parentKey Provide parent key information in case it exists. The protection function defines the purpose of this parameter + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_setProtection) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setProtection( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + mcuxClKey_Protection_t protection, + mcuxCl_Buffer_t pAuxData, + mcuxClKey_Handle_t parentKey +); + +/** + * @brief Load key into destination key slot of a coprocessor + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in] key Key handle that provides information to load the key + * @param[out] dstSlot Provide destination key slot in case the key has to loaded to a key slot. The protection function defines the purpose of this parameter + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_loadCopro) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadCopro( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + uint32_t dstSlot +); + +/** + * @brief Load key into destination memory buffer + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in] key Key handle that provides information to load the key + * @param[out] dstData Provide pointer to destination key memory in case the key has to be loaded to memory. The protection function defines the purpose of this parameter + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_loadMemory) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadMemory( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key, + uint32_t * dstData +); + +/** + * @brief Flush key from destination which can be a key slot of coprocessor or memory buffer + * + * @param[in] pSession Session handle to provide session dependent information + * @param[in] key Key handle that provides information to flush the key + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_flush) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_flush( + mcuxClSession_Handle_t pSession, + mcuxClKey_Handle_t key +); + + + +/** + * @brief Set the requested key properties of the destination key. + * + * @param[in,out] key key handle that provides information to flush the key + * @param[in] key_properties Pointer to the requested key properties of the destination key. Will be set in key->container.pAuxData + * + * @if (MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER && MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL) + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection). The error code can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @else + * @return An error code that can be any error code in @ref MCUXCLKEY_STATUS_, see individual documentation for more information + * @endif + * + * @retval #MCUXCLKEY_STATUS_ERROR on unsuccessful operation + * @retval #MCUXCLKEY_STATUS_OK on successful operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClKey_setKeyproperties) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setKeyproperties( + mcuxClKey_Handle_t key, + mcuxClEls_KeyProp_t * key_properties +); + + + + + + +/** + * @} + */ /* mcuxClKey_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_MemoryConsumption.h new file mode 100644 index 000000000..25e488a52 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_MemoryConsumption.h @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClKey_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClKey component + * All work area sizes in bytes are a multiple of CPU wordsize. + */ + +#ifndef MCUXCLKEY_MEMORYCONSUMPTION_H_ +#define MCUXCLKEY_MEMORYCONSUMPTION_H_ + +/** + * @defgroup mcuxClKey_MemoryConsumption mcuxClKey_MemoryConsumption + * @brief Defines the memory consumption for the mcuxClKey component + * @ingroup mcuxClKey + * @{ + */ + +#define MCUXCLKEY_DESCRIPTOR_SIZE (56u) +#define MCUXCLKEY_DESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_DESCRIPTOR_SIZE / sizeof(uint32_t)) + +#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE (12u) +#define MCUXCLKEY_TYPEDESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_TYPEDESCRIPTOR_SIZE / sizeof(uint32_t)) + +#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE (12u) +#define MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE_IN_WORDS (MCUXCLKEY_CUSTOMTYPEDESCRIPTOR_SIZE / sizeof(uint32_t)) + + +/** + * @} + */ /* mcuxClKey_MemoryConsumption */ + +#endif /* MCUXCLKEY_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_ProtectionMechanisms.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_ProtectionMechanisms.h new file mode 100644 index 000000000..08de032f8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_ProtectionMechanisms.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Protections.h + * @brief Provide API of the mcuxClKey_Protection functions + */ + +#ifndef MCUXCLKEY_PROTECTIONMECHANISMS_H_ +#define MCUXCLKEY_PROTECTIONMECHANISMS_H_ + +#include // Exported features flags header +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ") + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @addtogroup mcuxClKey Key API + * @brief Key handling operations. + * @ingroup mcuxClAPI + */ + +/** + * @defgroup clKeyProtectionMechanisms Key protection mechanism definitions + * @brief Mechanisms used by the Key operations. + * @ingroup mcuxClKey + * @{ + */ + +/** + * @brief Key protection descriptor for using no key protection + */ +extern const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None; + +/** + * @brief No key protection + */ +static const mcuxClKey_Protection_t mcuxClKey_Protection_None = + &mcuxClKey_ProtectionDescriptor_None; + +/** + * @brief Key protection descriptor for using CKDF based key protection + * This protection mechanism cannot be used for #mcuxClKey_loadMemory + */ +extern const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf; + +/** + * @brief CKDF key protection + */ +static const mcuxClKey_Protection_t mcuxClKey_Protection_Ckdf = + &mcuxClKey_ProtectionDescriptor_Ckdf; + + + + +/** @} */ + +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_PROTECTIONMECHANISMS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Types.h b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Types.h new file mode 100644 index 000000000..5189852a5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/inc/mcuxClKey_Types.h @@ -0,0 +1,178 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClKey_Types.h + * @brief Type definitions for the mcuxClKey component + */ + +#ifndef MCUXCLKEY_TYPES_H_ +#define MCUXCLKEY_TYPES_H_ + +#include +#include +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClKey_Types mcuxClKey_Types + * @brief Defines all types of @ref mcuxClKey + * @ingroup mcuxClKey + * @{ + */ + +/** + * @brief Type for Key component error codes. + */ +typedef uint32_t mcuxClKey_Status_t; + +/** + * @brief Type for algorithm based key id. + */ +typedef uint16_t mcuxClKey_AlgorithmId_t; + +/** + * @brief Type for algorithm based key size. + */ +typedef uint32_t mcuxClKey_Size_t; + +/** + * @brief Deprecated type for Key component error codes, returned by functions with code-flow protection. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_Status_Protected_t; + +/* Forward declaration */ +struct mcuxClKey_Protection; + +/** + * @brief Forward declaration for Key descriptor structure + * + * This structure captures all the information that the Key interfaces need + * to know about a particular key. + */ +struct mcuxClKey_Descriptor; + +/** + * @brief Key descriptor type + * + * This type captures all the information that the Key interfaces need to know + * about a particular Key. + */ +typedef struct mcuxClKey_Descriptor mcuxClKey_Descriptor_t; + +/** + * @brief Key handle type + * + * This type is used to refer to the opaque key descriptor. + */ +typedef mcuxClKey_Descriptor_t * const mcuxClKey_Handle_t; + +/** + * @brief Forward declaration for Key type structure + * + * This structure captures all the information that the Key interfaces need to + * know about a particular Key type. + */ +struct mcuxClKey_TypeDescriptor; + +/** + * @brief Key type descriptor type + * + * This type captures all the information that the Key interfaces need to know + * about a particular Key type. + */ +typedef struct mcuxClKey_TypeDescriptor mcuxClKey_TypeDescriptor_t; + +/** + * @brief Key type handle type + * + * This type is used to refer to a key type descriptor. + */ +typedef const mcuxClKey_TypeDescriptor_t * mcuxClKey_Type_t; + +/** + * @brief Custom key type handle type + * + * This type is used to refer to a custom key type descriptor. + */ +typedef mcuxClKey_TypeDescriptor_t * mcuxClKey_CustomType_t; + +/** + * @brief Key protection mechanism descriptor structure + * + * This structure captures all the information that the Key interfaces need to + * know about a particular Key protection mechanism. + */ +struct mcuxClKey_ProtectionDescriptor; + +/** + * @brief Key protection mechanism descriptor type + * + * This type captures all the information that the Key interfaces need to know + * about a particular Key protection mechanism. + */ +typedef struct mcuxClKey_ProtectionDescriptor mcuxClKey_ProtectionDescriptor_t; + +/** + * Key protection mechanism type + * + * This type is used to refer to a Key protection mechanism. + */ +typedef const mcuxClKey_ProtectionDescriptor_t * mcuxClKey_Protection_t; + + +/** + * @brief Key generation descriptor structure + * + * This structure captures all the information that the Key interfaces need to + * know about a particular Key generation algorithm. + */ +struct mcuxClKey_GenerationDescriptor; + +/** + * @brief Key generation descriptor type + * + * This type captures all the information that the Key interfaces need to know + * about a particular Key generation algorithm. + */ +typedef struct mcuxClKey_GenerationDescriptor mcuxClKey_GenerationDescriptor_t; + +/** + * @brief Key generation type + * + * This type is used to refer to a Key generation algorithm. + */ +typedef const mcuxClKey_GenerationDescriptor_t * const mcuxClKey_Generation_t; + + + + +/** + * @} + */ /* mcuxClKey_Types */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLKEY_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey.c b/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey.c new file mode 100644 index 000000000..8ad52884b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey.c @@ -0,0 +1,208 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClKey.c + * @brief Implementation of the Key component to deal with keys used by + * higher-level components. This file implements the functions declared in + * mcuxClKey.h. */ + +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_init( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t key, + mcuxClKey_Type_t type, + mcuxCl_InputBuffer_t pKeyData, + uint32_t keyDataLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_init); + + /* Fill key structure */ + mcuxClKey_setTypeDescriptor(key, *type); + mcuxClKey_setProtectionType(key, mcuxClKey_Protection_None); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("pKeyData can not made const inside of key component as it is possible that the data changes after init due to generation/agreement/derivation of keys."); + mcuxClKey_setKeyData(key, (mcuxCl_Buffer_t)pKeyData); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER(); + mcuxClKey_setKeyContainerSize(key, keyDataLength); + mcuxClKey_setKeyContainerUsedSize(key, keyDataLength); + mcuxClKey_setLoadedKeySlot(key, MCUXCLKEY_INVALID_KEYSLOT); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_NOTLOADED); + mcuxClKey_setLinkedData(key, NULL); + + /* Check if this is a variable-length external HMAC key */ + if(0u == type->size) + { + /* Overwrite the type's size with the given one */ + key->type.size = keyDataLength; + } + + if(NULL != pKeyData) + { + /* key data size validation in case of symmetric keys*/ + if(((key->type.algoId & MCUXCLKEY_ALGO_ID_USAGE_MASK) == MCUXCLKEY_ALGO_ID_SYMMETRIC_KEY) && (key->type.size != keyDataLength)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_init, MCUXCLKEY_STATUS_FAILURE); + } + } + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_init, MCUXCLKEY_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_linkKeyPair) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_linkKeyPair( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t privKey, + mcuxClKey_Handle_t pubKey) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_linkKeyPair); + + /* Link key pair handles */ + mcuxClKey_setLinkedData(privKey, (void *) pubKey); + mcuxClKey_setLinkedData(pubKey, (void *) privKey); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_linkKeyPair, MCUXCLKEY_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setProtection) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setProtection( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t key, + mcuxClKey_Protection_t protection, + mcuxCl_Buffer_t pAuxData, + mcuxClKey_Handle_t parentKey +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_setProtection); + + /* Fill key structure */ + mcuxClKey_setProtectionType(key, protection); + mcuxClKey_setAuxData(key, (uint8_t *) pAuxData); + mcuxClKey_setParentKey(key, parentKey); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_setProtection, MCUXCLKEY_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_loadMemory) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadMemory( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t key, + uint32_t * dstData +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_loadMemory, key->protection->protectionTokenLoad); + + /* Set additional parameters */ + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_MEMORY); + mcuxClKey_setLoadedKeyData(key, dstData); + + /* Perform key loading */ + MCUX_CSSL_FP_FUNCTION_CALL(result, key->protection->loadFunc(key)); + + if(MCUXCLKEY_STATUS_OK != result) + { + mcuxClKey_setLoadedKeyData(key, NULL); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_NOTLOADED); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_loadMemory, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_loadCopro) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_loadCopro( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t key, + uint32_t dstSlot +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_loadCopro, key->protection->protectionTokenLoad); + + /* Set additional parameters */ + mcuxClKey_setLoadedKeySlot(key, dstSlot); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_COPRO); + + /* Perform key loading */ + MCUX_CSSL_FP_FUNCTION_CALL(result, key->protection->loadFunc(key)); + + if(MCUXCLKEY_STATUS_OK != result) + { + /* Set additional parameters */ + mcuxClKey_setLoadedKeySlot(key, MCUXCLKEY_INVALID_KEYSLOT); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_NOTLOADED); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_loadCopro, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_flush) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_flush( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClKey_Handle_t key +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_flush); + + mcuxClKey_LoadStatus_t location = mcuxClKey_getLoadStatus(key); + + if(MCUXCLKEY_LOADSTATUS_NOTLOADED == location) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_OK); + } + else if(MCUXCLKEY_LOADSTATUS_MEMORY == location) + { + uint32_t len = mcuxClKey_getSize(key); + //TODO may need to be replaced by a secure set function + MCUXCLMEMORY_FP_MEMORY_CLEAR(mcuxClKey_getLoadedKeyData(key), len); + mcuxClKey_setLoadedKeySlot(key, MCUXCLKEY_INVALID_KEYSLOT); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_NOTLOADED); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_OK, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == location) + { + MCUX_CSSL_FP_FUNCTION_CALL(resultDelete, mcuxClEls_KeyDelete_Async((mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(key))); + if (MCUXCLELS_STATUS_OK_WAIT != resultDelete) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_ERROR, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async)); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if ((MCUXCLELS_STATUS_OK != resultWait)) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_ERROR, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async)); + } + mcuxClKey_setLoadedKeySlot(key, MCUXCLKEY_INVALID_KEYSLOT); + mcuxClKey_setLoadStatus(key, MCUXCLKEY_LOADSTATUS_NOTLOADED); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_OK, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async)); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_flush, MCUXCLKEY_STATUS_ERROR); + } +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_setKeyproperties) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_setKeyproperties( + mcuxClKey_Handle_t key, + mcuxClEls_KeyProp_t * key_properties +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_setKeyproperties); + + mcuxClKey_setAuxData(key, (uint8_t *) key_properties); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_setKeyproperties, MCUXCLKEY_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey_Protection.c b/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey_Protection.c new file mode 100644 index 000000000..4ba4b35b8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClKey/src/mcuxClKey_Protection.c @@ -0,0 +1,91 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClKey_Protection.c + * @brief Implementation of the Key protection functions that are supported + * by component. */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_protect_fct_none, mcuxClKey_LoadFuncPtr_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_protect_fct_none(mcuxClKey_Handle_t key) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_protect_fct_none); + + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(key)) + { + // copy key source to destination memory buffer + uint32_t len = mcuxClKey_getSize(key); + + MCUXCLMEMORY_FP_MEMORY_COPY(mcuxClKey_getLoadedKeyData(key), mcuxClKey_getKeyData(key), len); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_none, MCUXCLKEY_STATUS_OK, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); + } + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_none, MCUXCLKEY_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClKey_protect_fct_ckdf, mcuxClKey_LoadFuncPtr_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClKey_Status_t) mcuxClKey_protect_fct_ckdf(mcuxClKey_Handle_t key) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClKey_protect_fct_ckdf, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Ckdf_Sp800108_Async)); + + if(NULL == key->container.parentKey) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_ckdf, MCUXCLKEY_STATUS_ERROR); + } + + mcuxClEls_KeyIndex_t key_idx_sk = (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(mcuxClKey_getParentKey(key)); + mcuxClEls_KeyIndex_t key_idx_mack = (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(key); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClEls_KeyProp_t key_properties = *((mcuxClEls_KeyProp_t*) mcuxClKey_getAuxData(key)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + MCUX_CSSL_FP_FUNCTION_CALL(resultCkdf, mcuxClEls_Ckdf_Sp800108_Async( + key_idx_sk, + key_idx_mack, + key_properties, + mcuxClKey_getKeyData(key) + )); + // mcuxClEls_Ckdf_Sp800108_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != resultCkdf) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_ckdf, MCUXCLKEY_STATUS_ERROR); // Expect that no error occurred, meaning that the mcuxClEls_Ckdf_Sp800108_Async operation was started. + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_ckdf, MCUXCLKEY_STATUS_ERROR, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClKey_protect_fct_ckdf, MCUXCLKEY_STATUS_OK, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); +} + + +const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_None = {&mcuxClKey_protect_fct_none, + NULL, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_protect_fct_none), + 0u}; + +const mcuxClKey_ProtectionDescriptor_t mcuxClKey_ProtectionDescriptor_Ckdf = {&mcuxClKey_protect_fct_ckdf, + NULL, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_protect_fct_ckdf), + 0u}; + + diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Ctx.h b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Ctx.h new file mode 100644 index 000000000..d19ec222f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Ctx.h @@ -0,0 +1,44 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMac_Ctx.h + * @brief Internal header for MAC types + */ + +#ifndef MCUXCLMAC_CTX_H_ +#define MCUXCLMAC_CTX_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Mac context structure + * + * This structure is used in the multi-part interfaces to store the + * information about the current operation and the relevant internal state. + * This is the common part of the context needed by cipher modes. + */ +struct mcuxClMac_Context +{ + const mcuxClMac_ModeDescriptor_t * pMode; +}; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMAC_CTX_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Constants.h new file mode 100644 index 000000000..ceb5d59c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Constants.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMac_Internal_Constants.h + * @brief Internal header for MAC constants + */ + +#ifndef MCUXCLMAC_INTERNAL_CONSTANTS_H_ +#define MCUXCLMAC_INTERNAL_CONSTANTS_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define maximum output size for mcuxClHmac modes */ +#define MCUXCLMAC_MAX_OUTPUT_SIZE_HMAC (MCUXCLHMAC_MAX_OUTPUT_SIZE) + +/* Define maximum output size for mcuxClMacModes modes */ +#define MCUXCLMAC_MAX_OUTPUT_SIZE_MACMODES (MCUXCLMACMODES_MAX_OUTPUT_SIZE) + +#define MCUXCLMAC_MAX_OUTPUT_SIZE ((MCUXCLMAC_MAX_OUTPUT_SIZE_HMAC > MCUXCLMAC_MAX_OUTPUT_SIZE_MACMODES) ? MCUXCLMAC_MAX_OUTPUT_SIZE_HMAC : MCUXCLMAC_MAX_OUTPUT_SIZE_MACMODES) +#define MCUXCLMAC_MAX_OUTPUT_SIZE_IN_WORDS (MCUXCLMAC_MAX_OUTPUT_SIZE / sizeof(uint32_t)) + + +/* Define maximum context size for mcuxClHmac modes */ +#define MCUXCLMAC_MAX_CONTEXT_SIZE_HMAC (MCUXCLHMAC_INTERNAL_MAX_CONTEXT_SIZE) + +/* Define maximum context size for mcuxClMacModes modes */ +#define MCUXCLMAC_MAX_CONTEXT_SIZE_MACMODES (sizeof(mcuxClMacModes_Context_t)) + +#define MCUXCLMAC_MAX_CONTEXT_SIZE ((MCUXCLMAC_MAX_CONTEXT_SIZE_HMAC > MCUXCLMAC_MAX_CONTEXT_SIZE_MACMODES) ? MCUXCLMAC_MAX_CONTEXT_SIZE_HMAC : MCUXCLMAC_MAX_CONTEXT_SIZE_MACMODES) +#define MCUXCLMAC_MAX_CONTEXT_SIZE_IN_WORDS (MCUXCLMAC_MAX_CONTEXT_SIZE / sizeof(uint32_t)) + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMAC_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Types.h b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Types.h new file mode 100644 index 000000000..e5ca6c0bf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/internal/mcuxClMac_Internal_Types.h @@ -0,0 +1,135 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMac_Internal_Types.h + * @brief Internal header for MAC types + */ + +#ifndef MCUXCLMAC_INTERNAL_TYPES_H_ +#define MCUXCLMAC_INTERNAL_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Mode/Skeleton function types + */ + +/** + * @brief Mac Oneshot Compute function type + * + * This function will perform the actual MAC compute operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClMac_ComputeFunc_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_ComputeFunc_t)( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +)); + +/** + * @brief Mac Multipart Init function type + * + * This function will perform the actual MAC init operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClMac_InitFunc_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_InitFunc_t)( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key +)); + +/** + * @brief Mac Multipart Process function type + * + * This function will perform the actual MAC process operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClMac_ProcessFunc_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_ProcessFunc_t)( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +)); + +/** + * @brief Mac Multipart Finish function type + * + * This function will perform the actual MAC finish operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClMac_FinishFunc_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_FinishFunc_t)( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +)); + + + +/** + * Internal structures + */ + +/** + * @brief Mac common mode descriptor structure + * + * This structure captures all the information that the MAC interfaces need + * to know about a particular MAC mode/algorithm. + */ +typedef struct mcuxClMac_CommonModeDescriptor +{ + mcuxClMac_ComputeFunc_t compute; + uint32_t protectionToken_compute; + mcuxClMac_InitFunc_t init; + uint32_t protectionToken_init; + mcuxClMac_ProcessFunc_t process; + uint32_t protectionToken_process; + mcuxClMac_FinishFunc_t finish; + uint32_t protectionToken_finish; + uint32_t macByteSize; /* output size of the MAC computation in bytes */ + void * pAlgorithm; /* pointer to algorithm specifics, individual structures can be assigned here */ +} mcuxClMac_CommonModeDescriptor_t; + +/** + * @brief Mac top-level mode/algorithm descriptor structure + * + * This structure contains common information for all MAC modes. + */ +struct mcuxClMac_ModeDescriptor +{ + mcuxClMac_CommonModeDescriptor_t common; /* top-level mode information */ + void * pCustom; /* additional mode-specific data structure */ +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMAC_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac.h b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac.h new file mode 100644 index 000000000..c389adc8b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMac.h + * @brief Top-level include file for the mcuxClMac component + * + * @defgroup mcuxClMac mcuxClMac + * @brief Message Authentication Code (MAC) component + * @ingroup mcuxClAPI + * + * The mcuxClMac component implements Message Authentication Code (MAC) calculation, + * based on either HMAC or CMAC. + * + * An example of how to use the @ref mcuxClMac component can be found in /mcuxClMac/ex. + * + * The MAC can either be computed in one shot, using the mcuxClMac_compute function, + * or the input can be split into multiple parts. In that case, an initialization + * has to be performed first by calling the mcuxClMac_init function. Now zero, one, + * or more messages can be added for authentication by calling mcuxClMac_process. + * Finally, the MAC is generated when the mcuxClMac_finish function is called. + * + * The mode to be used, HMAC or CMAC, is defined by passing the corresponding mode + * descriptor (mcuxClMac_Mode_t) to mcuxClMac_compute or mcuxClMac_init. + * + */ + +#ifndef MCUXCLMAC_H_ +#define MCUXCLMAC_H_ + +#include // Exported features flags header +#include +#include +#include + +#endif /* MCUXCLMAC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Constants.h b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Constants.h new file mode 100644 index 000000000..74bf4b46d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Constants.h @@ -0,0 +1,39 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMac_Constants.h + * @brief Constants and status codes for the mcuxClMac component + */ + +#ifndef MCUXCLMAC_CONSTANTS_H_ +#define MCUXCLMAC_CONSTANTS_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClMac_Constants mcuxClMac_Constants + * @brief Constants of @ref mcuxClMac component + * @ingroup mcuxClMac + * @{ + */ +/* TODO CLNS-8684: Unionize and describe return codes */ +#define MCUXCLMAC_STATUS_ERROR ((mcuxClMac_Status_t) 0x08885330u) +#define MCUXCLMAC_STATUS_FAILURE ((mcuxClMac_Status_t) 0x08885334u) +#define MCUXCLMAC_STATUS_INVALID_PARAM ((mcuxClMac_Status_t) 0x088853F8u) +#define MCUXCLMAC_STATUS_FAULT_ATTACK ((mcuxClMac_Status_t) 0x0888F0F0u) +#define MCUXCLMAC_STATUS_OK ((mcuxClMac_Status_t) 0x08882E03u) +#define MCUXCLMAC_STATUS_COMPARE_NOK ((mcuxClMac_Status_t) 0x088853FCu) +/** @}*/ + +#endif /* MCUXCLMAC_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Functions.h b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Functions.h new file mode 100644 index 000000000..16ae80776 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Functions.h @@ -0,0 +1,241 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMac_Functions.h + * @brief Top-level API of the mcuxClMac component + */ + +#ifndef MCUXCLMAC_FUNCTIONS_H_ +#define MCUXCLMAC_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClMac_Functions mcuxClMac Functions + * @brief Defines all functions of @ref mcuxClMac + * @ingroup mcuxClMac + * @{ +*/ + +/****************************************************************************/ +/* ONESHOT */ +/****************************************************************************/ + +/** + * @defgroup mcuxClMac_OneShot One-shot MAC interfaces + * @brief Interfaces to perform MAC operations in one shot. + * @ingroup mcuxClMac_Functions + * @{ + */ + +/** + * @brief One-shot message authentication code (MAC) computation function. + * + * This function performs a MAC computation in one shot. The algorithm to be + * used will be determined based on the key that is provided. + * + * For example, to perform an AES MAC computation with a 128-bit key in CMAC + * mode on padded data, the following needs to be provided: + * - AES128 key + * - CMAC mode + * - Input data + * - Output data buffer, at least the size of a single AES block + * + * @attention In some cases restrictions may apply, e.g. the input buffer must + * be prepared for padding. Please refer to mcuxClMac_Modes.h to find further + * details and restrictions for each specific mode. + * + * @param[in] session Handle for the current CL session. + * @param[in] key Key to be used to authenticate the data. + * @param[in] mode Mode that should be used during the MAC operation. + * @param[in] pIn Pointer to the input buffer that contains the data that + * needs to be authenticated. + * @param[in] inLength Number of bytes of data in the @p pIn buffer. + * @param[out] pMac Pointer to the output buffer where the MAC needs to be written. + * @param[out] pMacLength Will be incremented by the number of bytes of data that + * have been written to the @p pMac buffer. + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval MCUXCLMAC_STATUS_OK Mac operation successful + * @retval MCUXCLMAC_STATUS_ERROR Error occurred during Mac operation + * @retval MCUXCLMAC_STATUS_INVALID_PARAM An invalid parameter was given to the function + * @retval MCUXCLMAC_STATUS_FAULT_ATTACK Fault attack detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_compute) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_compute( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); + +/** + * @} + */ /* mcuxClMac_OneShot */ + + +/****************************************************************************/ +/* MULTIPART */ +/****************************************************************************/ + +/** + * @defgroup mcuxClMac_MultiPart Multi part MAC interfaces + * @brief Interfaces to perform MAC operations in multi part. + * @ingroup mcuxClMac_Functions + * @{ + */ + +/** + * @brief Initialization for a multipart MAC computation. + * + * This function performs the initialization of a context for a multipart MAC + * computation. The algorithm to be used will be determined based on the key + * that is provided. + * + * This function should only be called once, as the first step for a multipart + * computation. + * + * For example, to perform a multipart AES MAC computation with a 128-bit key + * in CMAC mode on padded data, the following needs to be provided in this step: + * - AES128 key + * - CMAC mode + * + * The size of the context depends on the mode used + * (see @ref mcuxClMac_MemoryConsumption). + * + * @param[in] session Handle for the current CL session. + * @param[in] pContext MAC context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] key Key to be used to MAC the data. + * @param[in] mode Mode that should be used during the MAC operation. + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval MCUXCLMAC_STATUS_OK Mac operation successful + * @retval MCUXCLMAC_STATUS_ERROR Error occurred during Mac operation + * @retval MCUXCLMAC_STATUS_INVALID_PARAM An invalid parameter was given to the function + * @retval MCUXCLMAC_STATUS_FAULT_ATTACK Fault attack detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode +); /* init */ + +/** + * @brief Data processing for a multipart MAC computation. + * + * This function performs the data processing for a multipart MAC computation. + * The algorithm and key to be used will be determined based on the context that is provided. + + * This function can be called multiple times, after the multipart context + * initialization. + * + * For example, to perform a multipart AES MAC computation with a 128-bit key + * in CMAC mode on padded data, the following needs to be provided in this step: + * - Input data + * + * The size of the context depends on the mode used + * (see @ref mcuxClMac_MemoryConsumption). + * + * @see mcuxClMac_init + * + * @param session Handle for the current CL session. + * @param[in] pContext MAC context which is used to maintain the state and + * store other relevant information about the operation. + * @param[in] pIn Pointer to the input buffer that contains the data that + * need to be processed. + * @param[in] inLength Number of bytes of data in the @p in buffer. + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval MCUXCLMAC_STATUS_OK Mac operation successful + * @retval MCUXCLMAC_STATUS_ERROR Error occurred during Mac operation + * @retval MCUXCLMAC_STATUS_INVALID_PARAM An invalid parameter was given to the function + * @retval MCUXCLMAC_STATUS_FAULT_ATTACK Fault attack detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +); /* update */ + +/** + * @brief Finalize a MAC generation for a multipart MAC computation. + * + * This function performs the final MAC generation step for a multipart MAC + * computation. + * The algorithm and key to be used will be determined based on the context that is provided. + * + * This function should only be called once, as the last step for a multipart + * computation. + * + * For example, to perform a multipart AES MAC computation with a 128-bit key + * in CMAC mode on padded data, the following needs to be provided in this step: + * - Output data buffer, at least the size of a single AES block + * + * The size of the context depends on the mode used + * (see @ref mcuxClMac_MemoryConsumption). + * + * @see mcuxClMac_init + * @see mcuxClMac_process + * + * @param[in] session Handle for the current CL session. + * @param[in] pContext MAC context which is used to maintain the state and + * store other relevant information about the operation. + * @param[out] pMac Pointer to the output buffer where the MAC needs to be written. + * @param[out] pMacLength Will be incremented by the number of bytes of data that + * have been written to the @p pMac buffer. + * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval MCUXCLMAC_STATUS_OK Mac operation successful + * @retval MCUXCLMAC_STATUS_ERROR Error occurred during Mac operation + * @retval MCUXCLMAC_STATUS_INVALID_PARAM An invalid parameter was given to the function + * @retval MCUXCLMAC_STATUS_FAULT_ATTACK Fault attack detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMac_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); /* finalize compute */ + +/** + * @} + */ /* mcuxClMac_MultiPart */ + +/** + * @} + */ /* mcuxClMac_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMAC_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Types.h b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Types.h new file mode 100644 index 000000000..808f5759c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/inc/mcuxClMac_Types.h @@ -0,0 +1,124 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMac_Types.h + * @brief Type definitions for the mcuxClMac component + */ + +#ifndef MCUXCLMAC_TYPES_H_ +#define MCUXCLMAC_TYPES_H_ + +#include +#include +#include + +#include // Exported features flags header +#include +#include +#include + +/** + * @defgroup mcuxClMac_Types mcuxClMac_Types + * @brief Defines all types of the @ref mcuxClMac component + * @ingroup mcuxClMac + * @{ + */ + +/********************************************** + * TYPEDEFS + **********************************************/ + +/** + * @brief Type for Mac component error codes. + */ +typedef uint32_t mcuxClMac_Status_t; + +/** + * @brief MAC mode/algorithm descriptor structure + * + * This structure captures all the information that the MAC interfaces need to + * know about a particular MAC mode/algorithm. + */ +struct mcuxClMac_ModeDescriptor; + +/** + * @brief MAC mode/algorithm descriptor type + * + * This type captures all the information that the MAC interfaces need to + * know about a particular MAC mode/algorithm. +*/ +typedef struct mcuxClMac_ModeDescriptor mcuxClMac_ModeDescriptor_t; + +/** + * @brief MAC mode/algorithm type + * + * This type is used to refer to a MAC mode/algorithm. + */ +typedef const mcuxClMac_ModeDescriptor_t * const mcuxClMac_Mode_t; + +/** + * @brief MAC custom mode/algorithm type + * + * This type is used to refer to a custom MAC mode/algorithm that + * can be created via a provided constructor. + */ +typedef mcuxClMac_ModeDescriptor_t * const mcuxClMac_CustomMode_t; + +/** + * @brief Mac selftest mode/algorithm descriptor structure + * + * This structure captures all the information that the Mac selftest interfaces need + * to know about a particular Mac selftest mode/algorithm. + */ +struct mcuxClMac_TestDescriptor; + +/** + * @brief Mac selftest mode/algorithm descriptor type + * + * This type captures all the information that the Mac selftest interfaces need + * to know about a particular Mac selftest mode/algorithm. + */ +typedef struct mcuxClMac_TestDescriptor mcuxClMac_TestDescriptor_t; + +/** + * @brief Mac selftest mode/algorithm type + * + * This type is used to refer to a Mac selftest mode/algorithm. + */ +typedef const mcuxClMac_TestDescriptor_t * const mcuxClMac_Test_t; + +/** + * @brief Mac context structure + * + * This structure captures all the information that the Mac interface needs to + * know for a particular Mac mode/algorithm to work. + */ +struct mcuxClMac_Context; + +/** + * @brief Mac context type + * + * This type captures all the information that the Mac interface needs to + * know for a particular Mac mode/algorithm to work. + * + * The size of the context depends on the mode used + * (see @ref mcuxClMac_MemoryConsumption). + * + */ +typedef struct mcuxClMac_Context mcuxClMac_Context_t; + +/** + * @} + */ /* mcuxClMac_Types */ + +#endif /* MCUXCLMAC_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMac/src/mcuxClMac.c b/components/els_pkc/src/comps/mcuxClMac/src/mcuxClMac.c new file mode 100644 index 000000000..ee33d5760 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMac/src/mcuxClMac.c @@ -0,0 +1,107 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMac.c + * @brief Implementation of mcuxClMac component public API */ + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMac_compute) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_compute( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMac_compute, mode->common.protectionToken_compute); + + MCUX_CSSL_FP_FUNCTION_CALL(result, mode->common.compute( + session, + key, + mode, + pIn, + inLength, + pMac, + pMacLength + )); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMac_compute, result); +} + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMac_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMac_init, mode->common.protectionToken_init); + + pContext->pMode = mode; + MCUX_CSSL_FP_FUNCTION_CALL(result, mode->common.init( + session, + pContext, + key + )); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMac_init, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMac_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMac_process, pContext->pMode->common.protectionToken_process); + + MCUX_CSSL_FP_FUNCTION_CALL(result, pContext->pMode->common.process( + session, + pContext, + pIn, + inLength + )); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMac_process, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMac_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMac_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMac_finish, pContext->pMode->common.protectionToken_finish); + + MCUX_CSSL_FP_FUNCTION_CALL(result, pContext->pMode->common.finish( + session, + pContext, + pMac, + pMacLength + )); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMac_finish, result); +} + diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Algorithms.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Algorithms.h new file mode 100644 index 000000000..6dc69df31 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Algorithms.h @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Algorithms.h + * @brief Internal header for the MAC context for modes using the SGI + */ + +#ifndef MCUXCLMACMODES_ALGORITHMS_H_ +#define MCUXCLMACMODES_ALGORITHMS_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Common mode and algorithm descriptors + */ +extern const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CMAC; +extern const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_NoPadding; +extern const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method1; +extern const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method2; +extern const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_Padding_PKCS7; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_ALGORITHMS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cbcmac.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cbcmac.h new file mode 100644 index 000000000..af871ff41 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cbcmac.h @@ -0,0 +1,70 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_ELS_CBCMAC_H_ +#define MCUXCLMACMODES_ELS_CBCMAC_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Engine functions + */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CBCMAC_Oneshot) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Oneshot( + mcuxClSession_Handle_t session, /*! CBC-MAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CBC-MAC context */ + const uint8_t * const pIn, /*! CBC-MAC input */ + uint32_t inLength, /*! Input size */ + uint8_t * const pOut, /*! CBC-MAC output */ + uint32_t * const pOutLength /*! Output size */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CBCMAC_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Init( + mcuxClSession_Handle_t session, /*! CBC-MAC session handle */ + mcuxClMacModes_Context_t * const pContext /*! CBC-MAC context */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CBCMAC_Update) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Update( + mcuxClSession_Handle_t session, /*! CBC-MAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CBC-MAC context */ + const uint8_t * const pIn, /*! CBC-MAC input */ + uint32_t inLength /*! Input size */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CBCMAC_Finalize) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Finalize( + mcuxClSession_Handle_t session, /*! CBC-MAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CBC-MAC context */ + uint8_t * const pOut, /*! CBC-MAC output */ + uint32_t * const pOutLength /*! Output size */ +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_ELS_CBCMAC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cmac.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cmac.h new file mode 100644 index 000000000..1ac43483a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Cmac.h @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_ELS_CMAC_H_ +#define MCUXCLMACMODES_ELS_CMAC_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Engine functions + */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CMAC_Oneshot) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Oneshot( + mcuxClSession_Handle_t session, /*! CMAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CMAC context */ + const uint8_t *const pIn, /*! CMAC input */ + uint32_t inLength, /*! Input size */ + uint8_t *const pOut, /*! CMAC output */ + uint32_t *const pOutLength /*! Output size */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CMAC_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Init( + mcuxClSession_Handle_t session, /*! CMAC session handle */ + mcuxClMacModes_Context_t * const pContext /*! CMAC context */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CMAC_Update) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Update( + mcuxClSession_Handle_t session, /*! CMAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CMAC context */ + const uint8_t *const pIn, /*! CMAC input */ + uint32_t inLength /*! Input size */ +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_Engine_CMAC_Finalize) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Finalize( + mcuxClSession_Handle_t session, /*! CMAC session handle */ + mcuxClMacModes_Context_t * const pContext,/*! CMAC context */ + uint8_t *const pOut, /*! CMAC output */ + uint32_t *const pOutLength /*! Output size */ +); + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_ELS_CMAC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Ctx.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Ctx.h new file mode 100644 index 000000000..ece5fbccd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Ctx.h @@ -0,0 +1,55 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Els_Ctx.h + * @brief Internal header for the MAC context for modes using the ELS + */ + +#ifndef MCUXCLMACMODES_ELS_CTX_H_ +#define MCUXCLMACMODES_ELS_CTX_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Mac context structure for modes using ELS HW + * + * This structure captures all the information that the Mac interface needs to + * know for a particular Mac mode/algorithm to work. + */ +typedef struct mcuxClMacModes_Context +{ + mcuxClMac_Context_t common; ///< Common part of the context, for all modes + mcuxClKey_Descriptor_t * key; ///< Key descriptor of the key to be used + uint32_t blockBuffer[MCUXCLAES_BLOCK_SIZE_IN_WORDS]; ///< Not yet processed input data from the input stream + uint32_t blockBufferUsed; ///< Used bytes in blockBuffer + uint32_t state[MCUXCLAES_BLOCK_SIZE_IN_WORDS]; ///< state/intermediate result of the mac operation + mcuxClEls_CmacOption_t cmac_options; ///< Cmac ELS options to be used + uint32_t totalInput; ///< Total input length +} mcuxClMacModes_Context_t; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_ELS_CTX_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Types.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Types.h new file mode 100644 index 000000000..dc8794e90 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Els_Types.h @@ -0,0 +1,132 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Els_Types.h + * @brief Internal header for MAC types for modes using the ELS HW + */ + +#ifndef MCUXCLMACMODES_ELS_TYPES_H_ +#define MCUXCLMACMODES_ELS_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Engine function types + */ + +/** + * @brief Mac engine function type for the oneshot computation + * + * This function will perform the actual MAC operation + * + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_ComputeEngine_t)( + mcuxClSession_Handle_t session, + mcuxClMacModes_Context_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t *const pOut, + uint32_t *const outLength +); + +/** + * @brief Mac engine function type for the init phase of a multi-part computation + * + * This function will perform the actual MAC init operation + * + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_InitEngine_t)( + mcuxClSession_Handle_t session, + mcuxClMacModes_Context_t * const pContext +); + +/** + * @brief Mac engine function type for the update phase of a multi-part computation + * + * This function will perform the actual MAC update operation + * + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_UpdateEngine_t)( + mcuxClSession_Handle_t session, + mcuxClMacModes_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +); + +/** + * @brief Mac engine function type for the finish phase of a multi-part computation + * + * This function will perform the actual MAC finish operation + * + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) (*mcuxClMac_FinishEngine_t)( + mcuxClSession_Handle_t session, + mcuxClMacModes_Context_t * const pContext, + mcuxCl_Buffer_t pOut, + uint32_t * const outLength +); + + + +/** + * Internal structures / types + */ + +/** + * @brief Mac Mode structure + * + * This internal structure provides all implementation details for an ELS-based mode to the top level mcuxClMacMode functions. + * It consists of Init, Update, Finalize and Oneshot engines and the output size. + * + */ +typedef struct mcuxClMacModes_AlgorithmDescriptor +{ + mcuxClMac_InitEngine_t engineInit; ///< engine function to perform the init operation + uint32_t protectionToken_engineInit; ///< protection token of the engine function to perform the init operation + mcuxClMac_UpdateEngine_t engineUpdate; ///< engine function to perform the update operation + uint32_t protectionToken_engineUpdate; ///< protection token of the engine function to perform the update operation + mcuxClMac_FinishEngine_t engineFinalize; ///< engine function to perform the finalize operation + uint32_t protectionToken_engineFinalize; ///< protection token of the engine function to perform the finalize operation + mcuxClMac_ComputeEngine_t engineOneshot; ///< engine function to perform the Mac operation in one shot + uint32_t protectionToken_engineOneshot; ///< protection token of the engine function to perform the Mac operation in one shot + mcuxClPadding_addPaddingMode_t addPadding; ///< padding function to be used. One of mcuxClPaddingMode + uint32_t protectionToken_addPadding; ///< protection token of the padding funtion +} mcuxClMacModes_AlgorithmDescriptor_t; + +/** + * @brief MAC mode algorithm type for algorithms using ELS + * + * This type is used to refer to an ELS-based MAC mode algorithm. + */ +typedef const mcuxClMacModes_AlgorithmDescriptor_t * const mcuxClMacModes_Algorithm_t; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + + +#endif /* MCUXCLMACMODES_ELS_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Constants.h new file mode 100644 index 000000000..d377bb332 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Constants.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_INTERNAL_CONSTANTS_H_ +#define MCUXCLMACMODES_INTERNAL_CONSTANTS_H_ + +#include // Exported features flags header +#include +#include + +#define MCUXCLMACMODES_XCBCMAC_SUBKEY_KEY_2_INDEX (0u) +#define MCUXCLMACMODES_XCBCMAC_SUBKEY_KEY_3_INDEX (1u) + +#define MCUXCLMACMODES_SUBKEY_WORD_SIZE (4u) + +#define MCUXCLMACMODES_COMPARE_OK (0xA5A5A5A5u) +#define MCUXCLMACMODES_COMPARE_NOT_OK (0x5A5A5A5Au) + +#define MCUXCLMACMODES_TRUE (0xA5A5A5A5u) +#define MCUXCLMACMODES_FALSE (0x5A5A5A5Au) + + +#endif /* MCUXCLMACMODES_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Functions.h new file mode 100644 index 000000000..fce0ba55a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Functions.h @@ -0,0 +1,98 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Internal_Functions.h + * @brief Internal definitions of helper functions for the MacModes component + */ + +#ifndef MCUXCLMACMODES_INTERNAL_FUNCTIONS_H_ +#define MCUXCLMACMODES_INTERNAL_FUNCTIONS_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Skeleton functions for the MAC modes + */ + +/** + * @brief Mac Oneshot Compute function type + * + * This function will perform the actual MAC compute operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_compute, mcuxClMac_ComputeFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_compute( + mcuxClSession_Handle_t session, + mcuxClKey_Handle_t key, + mcuxClMac_Mode_t mode, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); + +/** + * @brief MacModes Multipart Init function type + * + * This function will perform the actual MAC init operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_init, mcuxClMac_InitFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key +); + +/** + * @brief MacModes Multipart Process function type + * + * This function will perform the actual MAC process operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_process, mcuxClMac_ProcessFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength +); + +/** + * @brief MacModes Multipart Finish function type + * + * This function will perform the actual MAC finish operation based on the given mode + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMacModes_finish, mcuxClMac_FinishFunc_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Macros.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Macros.h new file mode 100644 index 000000000..4f426d11e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Macros.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_INTERNAL_MACROS_H_ +#define MCUXCLMACMODES_INTERNAL_MACROS_H_ + +#include // Exported features flags header + +/* TODO CLNS-5054: Move these macros to a central location */ + +/* Macro used to align the size to the CPU wordsize */ +#define MCUXCLMACMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) \ + (((uint32_t) (((uint32_t) (size)) + ((sizeof(uint32_t)) - 1U))) & ((uint32_t) (~((sizeof(uint32_t)) - 1U)))) + +/* Macro used to compute number of CPU words */ +#define MCUXCLMACMODES_INTERNAL_COMPUTE_CPUWORDS(size) \ + (MCUXCLMACMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(size) / (sizeof(uint32_t))) + +#endif /* MCUXCLMACMODES_INTERNAL_MACROS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Memory.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Memory.h new file mode 100644 index 000000000..48b3e7be3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Memory.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_INTERNAL_MEMORY_H_ +#define MCUXCLMACMODES_INTERNAL_MEMORY_H_ + +#include // Exported features flags header + +#include +#include +#include + +#define MCUXCLMACMODES_INTERNAL_WASIZE MCUXCLMACMODES_INTERNAL_ALIGN_SIZE_TO_CPUWORDS(sizeof(mcuxClMacModes_WorkArea_t)) + +#endif /* MCUXCLMACMODES_INTERNAL_MEMORY_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Types.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Types.h new file mode 100644 index 000000000..8149209fc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Internal_Types.h @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_INTERNAL_TYPES_H_ +#define MCUXCLMACMODES_INTERNAL_TYPES_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Wa.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Wa.h new file mode 100644 index 000000000..3403e0d85 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/internal/mcuxClMacModes_Wa.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_WA_H_ +#define MCUXCLMACMODES_WA_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mcuxClMacModes_WorkArea +{ + uint32_t paddingBuff[MCUXCLAES_BLOCK_SIZE_IN_WORDS]; /* Buffer for padding */ +} mcuxClMacModes_WorkArea_t; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_WA_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes.h new file mode 100644 index 000000000..986729fbf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_H_ +#define MCUXCLMACMODES_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#endif /* MCUXCLMACMODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Constants.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Constants.h new file mode 100644 index 000000000..5da60bc20 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Constants.h @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMacModes_Constants.h + * @brief Constants for the mcuxClMacModes component + */ + +#ifndef MCUXCLMACMODES_CONSTANTS_H_ +#define MCUXCLMACMODES_CONSTANTS_H_ + +#include // Exported features flags header + +/** + * @defgroup mcuxClMacModes_Constants mcuxClMacModes Constants + * @brief Constants of @ref mcuxClMacModes component + * @ingroup mcuxClMacModes + * @{ + */ + +/* Output sizes */ +#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE (16u) ///< Size of CBCMAC output in bytes: 128 bits (16 bytes) +#define MCUXCLMAC_CBCMAC_OUTPUT_SIZE_IN_WORDS (MCUXCLMAC_CBCMAC_OUTPUT_SIZE / sizeof(uint32_t)) ///< Size of CBCMAC output in bytes: 128 bits (16 bytes) +#define MCUXCLMAC_CMAC_OUTPUT_SIZE (16u) ///< Size of CMAC output in bytes: 128 bits (16 bytes) +#define MCUXCLMAC_CMAC_OUTPUT_SIZE_IN_WORDS (MCUXCLMAC_CMAC_OUTPUT_SIZE / sizeof(uint32_t)) ///< Size of CMAC output in bytes: 128 bits (16 bytes) + +#define MCUXCLMACMODES_MAX_OUTPUT_SIZE (16u) + +#define MCUXCLMACMODES_MAX_OUTPUT_SIZE_IN_WORDS (MCUXCLMACMODES_MAX_OUTPUT_SIZE / sizeof(uint32_t)) + +/** @}*/ + +#endif /* MCUXCLMACMODES_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Functions.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Functions.h new file mode 100644 index 000000000..763641fd2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Functions.h @@ -0,0 +1,60 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMacModes_Functions.h + * @brief Functions for the mcuxClMacModes component + */ + +#ifndef MCUXCLMACMODES_FUNCTIONS_H_ +#define MCUXCLMACMODES_FUNCTIONS_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClMacModes_Functions mcuxClMacModes Functions + * @brief Defines all functions of @ref mcuxClMacModes + * @ingroup mcuxClMacModes + * @{ +*/ + +/** + * @defgroup mcuxClMacModes_Constructors APIs to construct Mac modes + * @brief Interfaces to construct Mac modes of operation. + * @ingroup mcuxClMacModes_Functions + * @{ + */ + + +/** + * @} + */ /* mcuxClMacModes_Constructors */ + +/** + * @} + */ /* mcuxClMacModes_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_MemoryConsumption.h new file mode 100644 index 000000000..f3248dfef --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_MemoryConsumption.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClMacModes component + * All work area sizes in bytes are a multiple of CPU wordsize. + */ + +#ifndef MCUXCLMACMODES_MEMORYCONSUMPTION_H_ +#define MCUXCLMACMODES_MEMORYCONSUMPTION_H_ + +/** + * @defgroup mcuxClMacModes_MemoryConsumption mcuxClMacModes_MemoryConsumption + * @brief Defines the memory consumption for the mcuxClMacModes component + * @ingroup mcuxClMacModes + * @{ + */ + +#define MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(size) (((uint32_t) (size)) / (sizeof(uint32_t))) + +/* Workarea sizes */ +#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE (16u) +#define MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_MAX_CPU_WA_BUFFER_SIZE) + +#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE (16u) +#define MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_COMPUTE_CPU_WA_BUFFER_SIZE) +#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE (sizeof(uint32_t)) +#define MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_INIT_CPU_WA_BUFFER_SIZE) +#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE (sizeof(uint32_t)) +#define MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_PROCESS_CPU_WA_BUFFER_SIZE) +#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE (16u) +#define MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_FINISH_CPU_WA_BUFFER_SIZE) + +/* Context sizes */ +#define MCUXCLMAC_CONTEXT_SIZE (52u) +#define MCUXCLMAC_CONTEXT_SIZE_IN_WORDS MCUXCLMAC_MAX_SIZE_IN_CPUWORDS(MCUXCLMAC_CONTEXT_SIZE) + +/* Mode descriptor sizes */ + +/** + * @} + */ /* mcuxClMac_MemoryConsumption */ + +#endif /* MCUXCLMACMODES_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Modes.h b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Modes.h new file mode 100644 index 000000000..afdc55243 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/inc/mcuxClMacModes_Modes.h @@ -0,0 +1,121 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLMACMODES_MODES_H_ +#define MCUXCLMACMODES_MODES_H_ + +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup mcuxClAPI MCUX CL -- API + * + * @addtogroup mcuxClMacModes MAC Modes API + * @brief Message Authentication Code (MAC) mode operations. + * @ingroup mcuxClAPI + */ + +/** + * @defgroup mcuxClMacModes_Modes MAC mode definitions + * @brief Modes used by the MAC operations. + * @ingroup mcuxClMacModes + */ + + +/** + * @brief CMAC mode descriptor + * @ingroup mcuxClMacModes_Modes + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC; + +/** + * @brief CMAC mode + * @ingroup mcuxClMacModes_Modes + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_CMAC = + &mcuxClMac_ModeDescriptor_CMAC; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + + +/** + * @brief CBC-MAC mode descriptor without padding + * @ingroup mcuxClMacModes_Modes + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding; + +/** + * @brief CBC-MAC mode without padding + * @ingroup mcuxClMacModes_Modes + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_NoPadding = + &mcuxClMac_ModeDescriptor_CBCMAC_NoPadding; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 1 + * @ingroup mcuxClMacModes_Modes + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1; + +/** + * @brief CBC-MAC mode with ISO/IEC 9797-1 padding method 1 + * @ingroup mcuxClMacModes_Modes + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method1 = + &mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief CBC-MAC mode descriptor with ISO/IEC 9797-1 padding method 2 + * @ingroup mcuxClMacModes_Modes + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2; + +/** + * @brief CBC-MAC mode with ISO/IEC 9797-1 padding method 2 + * @ingroup mcuxClMacModes_Modes + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_PaddingISO9797_1_Method2 = + &mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/** + * @brief CBC-MAC mode descriptor with PKCS7 padding padding + */ +extern const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_Padding_PKCS7; + +/** + * @brief CBC-MAC mode with PKCS7 padding + */ +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Declaration provided for externally accessible API") +static mcuxClMac_Mode_t mcuxClMac_Mode_CBCMAC_Padding_PKCS7 = + &mcuxClMac_ModeDescriptor_CBCMAC_Padding_PKCS7; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMACMODES_MODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes.c b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes.c new file mode 100644 index 000000000..14b5f843a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes.c @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes.c + * @brief Implementation of mcuxClMacModes component public API + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + diff --git a/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cbcmac.c b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cbcmac.c new file mode 100644 index 000000000..2bd2973e2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cbcmac.c @@ -0,0 +1,487 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Els_Cbcmac.c + * @brief implementation of CBC-MAC part of mcuxClMac component */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CBCMAC_Oneshot) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Oneshot( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CBCMAC_Oneshot); + + // Check if key matches the algorithm + if (MCUXCLKEY_ALGO_ID_AES != mcuxClKey_getAlgorithm(pContext->key)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) pContext->common.pMode->common.pAlgorithm; + + // Disable initialize/finalize for cbc-mac compitability. + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + pContext->cmac_options.bits.finalize = MCUXCLELS_CMAC_FINALIZE_DISABLE; + + // Get key location + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE; + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE; + } + else + { + // Error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + + size_t noOfFullBlocks = inLength / MCUXCLAES_BLOCK_SIZE; + size_t remainingBytes = inLength - (noOfFullBlocks * MCUXCLAES_BLOCK_SIZE); + MCUXCLMEMORY_FP_MEMORY_SET(pOut, 0x00, MCUXCLELS_CMAC_OUT_SIZE); + + if(0u != noOfFullBlocks) + { + // Call ELS cmac on all full blocks + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult1, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + pIn, + noOfFullBlocks * MCUXCLAES_BLOCK_SIZE, + pOut)); + + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != cmacResult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async)); + } + + MCUX_CSSL_FP_FUNCTION_CALL(waitResult1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(pOut, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + if (MCUXCLELS_STATUS_OK != waitResult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + } + uint32_t paddingOutLength = 0u; + // Call padding function + MCUX_CSSL_FP_FUNCTION_CALL(paddingResult, pAlgo->addPadding( + /* uint32_t blockLength */ MCUXCLAES_BLOCK_SIZE, + /* const uint8_t *const pIn */ (pIn + (MCUXCLAES_BLOCK_SIZE * noOfFullBlocks)), // this should be only the last block! + /* uint32_t lastBlockLength */ remainingBytes, + /* uint32_t totalInputLength */ inLength, + /* uint8_t *const pOut */ (uint8_t*)pContext->blockBuffer, + /* uint32_t *const pOutLength */ &paddingOutLength)); + + // padding functions are flow-protected: Check the protection token and the return value + if (MCUXCLPADDING_STATUS_OK != paddingResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + + if(paddingOutLength != 0u) + { + // Call ELS cmac on the padded block + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult2, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t*)pContext->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + pOut)); + + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != cmacResult2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async)); + } + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + + MCUX_CSSL_FP_FUNCTION_CALL(waitResult2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != waitResult2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress(pOut, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + } + + if((0u != inLength) || (paddingOutLength != 0u)) + { + *pOutLength = MCUXCLELS_CMAC_OUT_SIZE; + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Oneshot, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((noOfFullBlocks != 0u), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN), + pAlgo->protectionToken_addPadding, + MCUX_CSSL_FP_CONDITIONAL((paddingOutLength != 0u), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CBCMAC_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Init( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CBCMAC_Init, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + + pContext->blockBufferUsed = 0; + + pContext->totalInput = 0; + + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t*)(pContext->blockBuffer), 0x00, MCUXCLAES_BLOCK_SIZE); + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t*)(pContext->state), 0x00, MCUXCLAES_BLOCK_SIZE); + + pContext->cmac_options.word.value = 0U; + + // Disable initialize/finalize for cbc-mac compitability. + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + pContext->cmac_options.bits.finalize = MCUXCLELS_CMAC_FINALIZE_DISABLE; + + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE; + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE; + } + else + { + // Error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Init, MCUXCLMAC_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClMacModes_Engine_CBCMAC_Init, MCUXCLMAC_STATUS_OK, MCUXCLMAC_STATUS_FAULT_ATTACK); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CBCMAC_Update) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Update( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CBCMAC_Update); + + size_t pInNrProcessedBytes = 0; + + // Check if there are remaining bytes in the context from previous calls to this function + // pContext->blockBufferUsed can be at most MCUXCLAES_BLOCK_SIZE - 1 + // The case where inLength + pContext->blockBufferUsed is less than a block size is handeled later + const bool hasBlockSizedBytesInBuffer = ((0u < pContext->blockBufferUsed) && (MCUXCLAES_BLOCK_SIZE <= (inLength + pContext->blockBufferUsed))); + if (hasBlockSizedBytesInBuffer) + { + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); + + // Copy as many bytes from pIn to pContext->blockBuffer in order to create one full block + MCUXCLMEMORY_FP_MEMORY_COPY(((uint8_t*)pContext->blockBuffer + pContext->blockBufferUsed), pIn, MCUXCLAES_BLOCK_SIZE - pContext->blockBufferUsed); + // Process this block + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t*) pContext->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + (uint8_t*) pContext->state)); + + if (MCUXCLELS_STATUS_OK_WAIT != cmacResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } + + pContext->totalInput += MCUXCLAES_BLOCK_SIZE; + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + MCUX_CSSL_FP_FUNCTION_CALL(waitResult, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != waitResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + pInNrProcessedBytes = MCUXCLAES_BLOCK_SIZE - pContext->blockBufferUsed; + + pContext->blockBufferUsed = 0; + + } + + // Check if there are full blocks to process + const bool hasFullBlocks = (MCUXCLAES_BLOCK_SIZE <= (inLength - pInNrProcessedBytes)); + if(hasFullBlocks) + { + size_t noOfFullBlocks = (inLength - pInNrProcessedBytes) / MCUXCLAES_BLOCK_SIZE; + + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + pIn + pInNrProcessedBytes, + noOfFullBlocks * MCUXCLAES_BLOCK_SIZE, + (uint8_t*) pContext->state)); + + if (MCUXCLELS_STATUS_OK_WAIT != cmacResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } + + pContext->totalInput += noOfFullBlocks * MCUXCLAES_BLOCK_SIZE; + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + MCUX_CSSL_FP_FUNCTION_CALL(waitResult, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != waitResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLAES_BLOCK_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + pInNrProcessedBytes += (noOfFullBlocks * MCUXCLAES_BLOCK_SIZE); + } + + // Check if there are remaining bytes and copy them to the context + if(pInNrProcessedBytes < inLength) + { + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); + MCUXCLMEMORY_FP_MEMORY_COPY(((uint8_t*)pContext->blockBuffer + pContext->blockBufferUsed), (pIn + pInNrProcessedBytes), (inLength - pInNrProcessedBytes)); + // Update number of bytes in blockBuffer + pContext->blockBufferUsed += (inLength - pInNrProcessedBytes); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL(hasBlockSizedBytesInBuffer, + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async)), + MCUX_CSSL_FP_CONDITIONAL(hasFullBlocks, + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async))); + +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CBCMAC_Finalize) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CBCMAC_Finalize( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CBCMAC_Finalize); + + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) pContext->common.pMode->common.pAlgorithm; + + // Check if additional block needs to be processed + uint32_t paddingOutLength = 0u; + + // Call padding function + MCUX_CSSL_FP_FUNCTION_CALL(paddingResult, pAlgo->addPadding( + /* uint32_t blockLength */ MCUXCLELS_CIPHER_BLOCK_SIZE_AES, + /* const uint8_t *const pIn */ (uint8_t*)pContext->blockBuffer, + /* uint32_t lastBlockLength */ pContext->blockBufferUsed, + /* uint32_t totalInputLength */ pContext->totalInput, + /* uint8_t *const pOut */ (uint8_t*)pContext->blockBuffer, + /* uint32_t *const pOutLength */ &paddingOutLength)); + + // padding functions are flow-protected: Check the protection token and the return value + if (MCUXCLPADDING_STATUS_OK != paddingResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Finalize, MCUXCLMAC_STATUS_ERROR); + } + + if(paddingOutLength != 0u) + { + // Call ELS cmac on padded block + MCUX_CSSL_FP_FUNCTION_CALL(cmacResult, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t*)pContext->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + (uint8_t*)pContext->state)); + + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != cmacResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Finalize, MCUXCLMAC_STATUS_ERROR); + } + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + + MCUX_CSSL_FP_FUNCTION_CALL(waitResult, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != waitResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Finalize, MCUXCLMAC_STATUS_ERROR); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Update, MCUXCLMAC_STATUS_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + } + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); + + // Copy final result from the context to the output + MCUXCLMEMORY_FP_MEMORY_COPY(pOut, (uint8_t*)pContext->state, MCUXCLAES_BLOCK_SIZE); + + *pOutLength = MCUXCLELS_CMAC_OUT_SIZE; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CBCMAC_Finalize, MCUXCLMAC_STATUS_OK, + pAlgo->protectionToken_addPadding, + MCUX_CSSL_FP_CONDITIONAL((paddingOutLength != 0u), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async))); +} + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_NoPadding = { + .engineInit = mcuxClMacModes_Engine_CBCMAC_Init, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Init), + .engineUpdate = mcuxClMacModes_Engine_CBCMAC_Update, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Update), + .engineFinalize = mcuxClMacModes_Engine_CBCMAC_Finalize, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Finalize), + .engineOneshot = mcuxClMacModes_Engine_CBCMAC_Oneshot, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Oneshot), + .addPadding = mcuxClPadding_addPadding_None, + .protectionToken_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_None), +}; + +const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method1 = { + .engineInit = mcuxClMacModes_Engine_CBCMAC_Init, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Init), + .engineUpdate = mcuxClMacModes_Engine_CBCMAC_Update, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Update), + .engineFinalize = mcuxClMacModes_Engine_CBCMAC_Finalize, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Finalize), + .engineOneshot = mcuxClMacModes_Engine_CBCMAC_Oneshot, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Oneshot), + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method1, + .protectionToken_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method1), +}; + +const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method2 = { + .engineInit = mcuxClMacModes_Engine_CBCMAC_Init, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Init), + .engineUpdate = mcuxClMacModes_Engine_CBCMAC_Update, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Update), + .engineFinalize = mcuxClMacModes_Engine_CBCMAC_Finalize, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Finalize), + .engineOneshot = mcuxClMacModes_Engine_CBCMAC_Oneshot, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Oneshot), + .addPadding = mcuxClPadding_addPadding_ISO9797_1_Method2, + .protectionToken_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method2), +}; + +const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CBCMAC_Padding_PKCS7 = { + .engineInit = mcuxClMacModes_Engine_CBCMAC_Init, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Init), + .engineUpdate = mcuxClMacModes_Engine_CBCMAC_Update, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Update), + .engineFinalize = mcuxClMacModes_Engine_CBCMAC_Finalize, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Finalize), + .engineOneshot = mcuxClMacModes_Engine_CBCMAC_Oneshot, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CBCMAC_Oneshot), + .addPadding = mcuxClPadding_addPadding_PKCS7, + .protectionToken_addPadding = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_PKCS7), +}; + + +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + diff --git a/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cmac.c b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cmac.c new file mode 100644 index 000000000..1972092cf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Cmac.c @@ -0,0 +1,478 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Els_Cmac.c + * @brief implementation of CMAC part of mcuxClMac component */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CMAC_Oneshot) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Oneshot( + mcuxClSession_Handle_t session, + mcuxClMacModes_Context_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CMAC_Oneshot); + size_t const completeLen = (inLength/MCUXCLAES_BLOCK_SIZE)*MCUXCLAES_BLOCK_SIZE; + size_t bufLen = MCUXCLAES_BLOCK_SIZE; + size_t const remainingLen = inLength - completeLen; + + // Check if key matches to the algorithm + if (MCUXCLKEY_ALGO_ID_AES != mcuxClKey_getAlgorithm(pContext->key)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + + /* Create workarea */ + /* MISRA Ex. 9 to Rule 11.3 - reinterpret memory */ + uint32_t cpuWaSizeInWords = MCUXCLMACMODES_INTERNAL_COMPUTE_CPUWORDS(sizeof(mcuxClMacModes_WorkArea_t)); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClMacModes_WorkArea_t *workArea = (mcuxClMacModes_WorkArea_t *) mcuxClSession_allocateWords_cpuWa(session, cpuWaSizeInWords); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + if(NULL == workArea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_FAILURE); + } + + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_ENABLE; + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE; + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE; + } + else + { + // error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR); + } + + //processing part of the data which is a multiple of the block size + if (completeLen != 0u) + { + //data length is a multiple of the block size ==> no padding needed + if(0u == remainingLen) + { + pContext->cmac_options.bits.finalize = MCUXCLELS_CMAC_FINALIZE_ENABLE; + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultCmac, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + pIn, + completeLen, + pOut + )); + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != resultCmac) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async) ); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != pOut) + { + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult1, mcuxClEls_CompareDmaFinalOutputAddress(pOut, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + + } + + //apply padding or process empty message + if((0u != remainingLen) || (0u == inLength)) + { + //maximum 15 bytes left to process + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF((uint8_t *)workArea->paddingBuff, pIn + completeLen, remainingLen, bufLen); + bufLen -= remainingLen; + + MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF((uint8_t *)workArea->paddingBuff + remainingLen, 0x80, 0x01U, bufLen); + bufLen--; + + //fill the rest of the buffer with 0x00 + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *)workArea->paddingBuff + remainingLen + 1u, 0x00, bufLen); + + pContext->cmac_options.bits.finalize = MCUXCLELS_CMAC_FINALIZE_ENABLE; + + MCUX_CSSL_FP_FUNCTION_CALL(resultCmac, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t *)workArea->paddingBuff, + remainingLen, + pOut + )); + + if (MCUXCLELS_STATUS_OK_WAIT != resultCmac) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_CONDITIONAL(completeLen != 0u, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async) ); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_CONDITIONAL(completeLen != 0u, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + if(NULL != pOut) + { + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult2, mcuxClEls_CompareDmaFinalOutputAddress(pOut, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_FAULT_ATTACK); + } + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + } + + *pOutLength = MCUXCLELS_CMAC_OUT_SIZE; + + /* Free workArea in Session */ + mcuxClSession_freeWords_cpuWa(session, cpuWaSizeInWords); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClMacModes_Engine_CMAC_Oneshot, MCUXCLMAC_STATUS_OK, MCUXCLMAC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(completeLen != 0u, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_CONDITIONAL(NULL != pOut, MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN) + ), + MCUX_CSSL_FP_CONDITIONAL((0u != remainingLen) || (0u == inLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_CONDITIONAL(NULL != pOut, MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN) + ) + ); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CMAC_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Init( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CMAC_Init, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + pContext->blockBufferUsed = 0; + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t*)(pContext->blockBuffer),0x00,MCUXCLAES_BLOCK_SIZE); + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t*)(pContext->state), 0x00, MCUXCLAES_BLOCK_SIZE); + + pContext->cmac_options.word.value = 0U; + + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_ENABLE; + if(MCUXCLKEY_LOADSTATUS_MEMORY == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_ENABLE; + } + else if(MCUXCLKEY_LOADSTATUS_COPRO == mcuxClKey_getLoadStatus(pContext->key)) + { + pContext->cmac_options.bits.extkey = MCUXCLELS_CMAC_EXTERNAL_KEY_DISABLE; + } + else + { + // error: no key loaded + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Init, MCUXCLMAC_STATUS_ERROR); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClMacModes_Engine_CMAC_Init, MCUXCLMAC_STATUS_OK, MCUXCLMAC_STATUS_FAULT_ATTACK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CMAC_Update) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Update( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext, + const uint8_t *const pIn, + uint32_t inLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CMAC_Update); + size_t remainingLength = inLength; + size_t alreadyProcessedBytes = 0; + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_CONDITIONAL(((pContext->blockBufferUsed > 0U) && ((pContext->blockBufferUsed + inLength) > MCUXCLAES_BLOCK_SIZE)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN + )); + //check if there are "old" bytes to process + if((pContext->blockBufferUsed > 0U) && ((pContext->blockBufferUsed + inLength) > MCUXCLAES_BLOCK_SIZE)) + { + //copy new input data + MCUXCLMEMORY_FP_MEMORY_COPY((uint8_t*)pContext->blockBuffer + pContext->blockBufferUsed, pIn, MCUXCLAES_BLOCK_SIZE - pContext->blockBufferUsed); + //perform cmac operation + MCUX_CSSL_FP_FUNCTION_CALL(resultCmac, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t*)pContext->blockBuffer, + MCUXCLAES_BLOCK_SIZE, + (uint8_t*)pContext->state + )); + + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != resultCmac) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async) ); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) ); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult1, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_FAULT_ATTACK); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + //update options for the next operations + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + + remainingLength -= (MCUXCLAES_BLOCK_SIZE - pContext->blockBufferUsed); + alreadyProcessedBytes = (MCUXCLAES_BLOCK_SIZE - pContext->blockBufferUsed); + + pContext->blockBufferUsed = 0; + + } + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_CONDITIONAL((MCUXCLAES_BLOCK_SIZE < remainingLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN)); + + //check if there are full block of input data available + if(MCUXCLAES_BLOCK_SIZE < remainingLength) + { + size_t completeLen = (remainingLength/MCUXCLAES_BLOCK_SIZE)*MCUXCLAES_BLOCK_SIZE; + + //if remaining length is a multiple of the block size, + //keep on block. We need it for the finalize operation + if(remainingLength == completeLen) + { + completeLen -= MCUXCLAES_BLOCK_SIZE; + } + + //perform cmac operation + MCUX_CSSL_FP_FUNCTION_CALL(resultCmac, mcuxClEls_Cmac_Async( + pContext->cmac_options, + (mcuxClEls_KeyIndex_t) mcuxClKey_getLoadedKeySlot(pContext->key), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + pIn + alreadyProcessedBytes, + completeLen, + (uint8_t*)pContext->state + )); + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != resultCmac) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async) ); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) ); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult2, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_FAULT_ATTACK); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + pContext->cmac_options.bits.initialize = MCUXCLELS_CMAC_INITIALIZE_DISABLE; + + remainingLength -= completeLen; + alreadyProcessedBytes += completeLen; + + } + + //check if there is still input data left that needs to be copied to the context + if(remainingLength != 0u) + { + //maximum 16 bytes left + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF((uint8_t*)pContext->blockBuffer + pContext->blockBufferUsed, + pIn + alreadyProcessedBytes, + remainingLength, + sizeof(pContext->blockBuffer) - pContext->blockBufferUsed); + + pContext->blockBufferUsed += (uint8_t) remainingLength; + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClMacModes_Engine_CMAC_Update, MCUXCLMAC_STATUS_OK, MCUXCLMAC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_CONDITIONAL(remainingLength != 0u, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)) + ); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_Engine_CMAC_Finalize) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_Engine_CMAC_Finalize( + mcuxClSession_Handle_t session UNUSED_PARAM, + mcuxClMacModes_Context_t * const pContext, + uint8_t *const pOut, + uint32_t *const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_Engine_CMAC_Finalize); + pContext->cmac_options.bits.finalize = MCUXCLELS_CMAC_FINALIZE_ENABLE; + + //apply padding if needed + if(MCUXCLAES_BLOCK_SIZE > pContext->blockBufferUsed) + { + ((uint8_t*)(pContext->blockBuffer))[pContext->blockBufferUsed] = 0x80U; + + if((MCUXCLAES_BLOCK_SIZE - 1u) > pContext->blockBufferUsed) + { + //fill the rest of the buffer with 0x00 if there is more to fill + MCUXCLMEMORY_FP_MEMORY_SET(((uint8_t*)pContext->blockBuffer) + pContext->blockBufferUsed + 1u, 0x00, MCUXCLAES_BLOCK_SIZE - ((size_t) pContext->blockBufferUsed + 1u) ); + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + } + + //perform cmac operation + MCUX_CSSL_FP_FUNCTION_CALL(resultCmac, mcuxClEls_Cmac_Async(pContext->cmac_options, + (mcuxClEls_KeyIndex_t) (mcuxClKey_getLoadedKeySlot(pContext->key)), + (uint8_t const *) mcuxClKey_getLoadedKeyData(pContext->key), + (size_t) mcuxClKey_getSize(pContext->key), + (uint8_t*)(pContext->blockBuffer), + pContext->blockBufferUsed, + (uint8_t*)(pContext->state))); + // mcuxClEls_Cmac_Async is a flow-protected function: Check the protection token and the return value + if (MCUXCLELS_STATUS_OK_WAIT != resultCmac) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Finalize, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async) ); + } + + MCUX_CSSL_FP_FUNCTION_CALL(resultWait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + + if (MCUXCLELS_STATUS_OK != resultWait) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Finalize, MCUXCLMAC_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) ); + } + +#ifdef MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK + MCUX_CSSL_FP_FUNCTION_CALL(addressComparisonResult1, mcuxClEls_CompareDmaFinalOutputAddress((uint8_t*)pContext->state, MCUXCLELS_CMAC_OUT_SIZE)); + + if (MCUXCLELS_STATUS_OK != addressComparisonResult1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_Engine_CMAC_Finalize, MCUXCLMAC_STATUS_FAULT_ATTACK); + } +#endif /* MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK */ + + //copy result to output buffer + MCUXCLMEMORY_FP_MEMORY_COPY(pOut,(uint8_t*)pContext->state,pContext->common.pMode->common.macByteSize); + + + *pOutLength = MCUXCLELS_CMAC_OUT_SIZE; + + //context isn't needed any longer; destroy it + MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t*)(pContext), sizeof(mcuxClMacModes_Context_t)); + + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClMacModes_Engine_CMAC_Finalize, MCUXCLMAC_STATUS_OK, MCUXCLMAC_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cmac_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLELS_DMA_READBACK_PROTECTION_TOKEN); +} + +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClMacModes_AlgorithmDescriptor_t mcuxClMacModes_AlgorithmDescriptor_CMAC = { + .engineInit = mcuxClMacModes_Engine_CMAC_Init, + .protectionToken_engineInit = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CMAC_Init), + .engineUpdate = mcuxClMacModes_Engine_CMAC_Update, + .protectionToken_engineUpdate = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CMAC_Update), + .engineFinalize = mcuxClMacModes_Engine_CMAC_Finalize, + .protectionToken_engineFinalize = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CMAC_Finalize), + .engineOneshot = mcuxClMacModes_Engine_CMAC_Oneshot, + .protectionToken_engineOneshot = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_Engine_CMAC_Oneshot), + .addPadding = NULL, + .protectionToken_addPadding = 0u, +}; diff --git a/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Functions.c b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Functions.c new file mode 100644 index 000000000..78963334c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Els_Functions.c @@ -0,0 +1,96 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Els_Functions.c + * @brief Implementation of mcuxClMacModes functions for ELS-based modes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_compute) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_compute( +mcuxClSession_Handle_t session, +mcuxClKey_Handle_t key, +mcuxClMac_Mode_t mode, +mcuxCl_InputBuffer_t pIn, +uint32_t inLength, +mcuxCl_Buffer_t pMac, +uint32_t * const pMacLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different MacModes Algorithm types") + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) mode->common.pAlgorithm; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_compute, pAlgo->protectionToken_engineOneshot); + mcuxClMacModes_Context_t context = {0u}; + context.common.pMode = mode; + context.key = (mcuxClKey_Descriptor_t *) key; + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineOneshot(session, &context, pIn, inLength, pMac, pMacLength)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_compute, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_init( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxClKey_Handle_t key) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different MacModes Algorithm types") + mcuxClMacModes_Context_t * const pCtx = (mcuxClMacModes_Context_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_init, pAlgo->protectionToken_engineInit); + pCtx->key = (mcuxClKey_Descriptor_t *) key; + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineInit(session, pCtx)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_init, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_process) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_process( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different MacModes Algorithm types") + mcuxClMacModes_Context_t * const pCtx = (mcuxClMacModes_Context_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_process, pAlgo->protectionToken_engineUpdate); + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineUpdate(session, pCtx, pIn, inLength)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_process, result); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMacModes_finish) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMac_Status_t) mcuxClMacModes_finish( + mcuxClSession_Handle_t session, + mcuxClMac_Context_t * const pContext, + mcuxCl_Buffer_t pMac, + uint32_t * const pMacLength) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret structure for different MacModes Algorithm types") + mcuxClMacModes_Context_t * const pCtx = (mcuxClMacModes_Context_t *) pContext; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + mcuxClMacModes_Algorithm_t pAlgo = (mcuxClMacModes_Algorithm_t) pCtx->common.pMode->common.pAlgorithm; + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMacModes_finish, pAlgo->protectionToken_engineFinalize); + MCUX_CSSL_FP_FUNCTION_CALL(result, pAlgo->engineFinalize(session, pCtx, pMac, pMacLength)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMacModes_finish, result); +} diff --git a/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Modes.c b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Modes.c new file mode 100644 index 000000000..ad7da8905 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMacModes/src/mcuxClMacModes_Modes.c @@ -0,0 +1,148 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMacModes_Modes.c + * @brief Definition of the mode descriptors for all provided MAC modes + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * Constant top-level mode descriptors and common mode descriptors for custom modes + */ + + +/** + * Top-level mode structure for CMAC + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CMAC = { + .common = { + .compute = mcuxClMacModes_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_compute), + .init = mcuxClMacModes_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_init), + .process = mcuxClMacModes_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_process), + .finish = mcuxClMacModes_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_finish), + .macByteSize = MCUXCLMAC_CMAC_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClMacModes_AlgorithmDescriptor_CMAC + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + + +/** + * Top-level mode structure for CBCMAC without padding + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_NoPadding = { + .common = { + .compute = mcuxClMacModes_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_compute), + .init = mcuxClMacModes_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_init), + .process = mcuxClMacModes_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_process), + .finish = mcuxClMacModes_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_finish), + .macByteSize = MCUXCLMAC_CBCMAC_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClMacModes_AlgorithmDescriptor_CBCMAC_NoPadding + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +/** + * Top-level mode structure for CBCMAC using ISO9797-1 Method 1 Padding + */ +/* MISRA Ex. 20 - Rule 5.1 */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method1 = { + .common = { + .compute = mcuxClMacModes_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_compute), + .init = mcuxClMacModes_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_init), + .process = mcuxClMacModes_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_process), + .finish = mcuxClMacModes_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_finish), + .macByteSize = MCUXCLMAC_CBCMAC_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method1 + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/** + * Top-level mode structure forCBCMAC using ISO9797-1 Method 2 Padding + */ +/* MISRA Ex. 20 - Rule 5.1 */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_PaddingISO9797_1_Method2 = { + .common = { + .compute = mcuxClMacModes_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_compute), + .init = mcuxClMacModes_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_init), + .process = mcuxClMacModes_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_process), + .finish = mcuxClMacModes_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_finish), + .macByteSize = MCUXCLMAC_CBCMAC_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClMacModes_AlgorithmDescriptor_CBCMAC_PaddingISO9797_1_Method2 + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/** + * Top-level mode structure for CBCMAC using PKCS7 Padding + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClMac_ModeDescriptor_t mcuxClMac_ModeDescriptor_CBCMAC_Padding_PKCS7 = { + .common = { + .compute = mcuxClMacModes_compute, + .protectionToken_compute = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_compute), + .init = mcuxClMacModes_init, + .protectionToken_init = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_init), + .process = mcuxClMacModes_process, + .protectionToken_process = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_process), + .finish = mcuxClMacModes_finish, + .protectionToken_finish = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMacModes_finish), + .macByteSize = MCUXCLMAC_CBCMAC_OUTPUT_SIZE, + .pAlgorithm = (void *) &mcuxClMacModes_AlgorithmDescriptor_CBCMAC_Padding_PKCS7 + }, + .pCustom = NULL +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ExactDivideOdd_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ExactDivideOdd_FUP.h new file mode 100644 index 000000000..ed22abd55 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ExactDivideOdd_FUP.h @@ -0,0 +1,47 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ExactDivideOdd_FUP.h + * @brief defines FUP program byte arrays for mcuxClMath_ExactDivideOdd + */ + +#ifndef MCUXCLMATH_EXACTDIVIDEODD_FUP_H_ +#define MCUXCLMATH_EXACTDIVIDEODD_FUP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClMath_Fup_ExactDivideOdd_DivideLoop + */ +#define mcuxClMath_Fup_ExactDivideOdd_DivideLoop_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_DivideLoop[mcuxClMath_Fup_ExactDivideOdd_DivideLoop_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_ExactDivideOdd_NDashY + */ +#define mcuxClMath_Fup_ExactDivideOdd_NDashY_LEN 4u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_NDashY[mcuxClMath_Fup_ExactDivideOdd_NDashY_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_EXACTDIVIDEODD_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ExactDivideOdd.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ExactDivideOdd.h new file mode 100644 index 000000000..5c5370e91 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ExactDivideOdd.h @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Internal_ExactDivideOdd.h + * @brief mcuxClMath: internal header of exact divide with odd divisor + */ + + +#ifndef MCUXCLMATH_INTERNAL_EXACTDIVIDEODD_H_ +#define MCUXCLMATH_INTERNAL_EXACTDIVIDEODD_H_ + +#include + + +/**********************************************************/ +/* Indices of operands in PKC workarea and UPTR table */ +/**********************************************************/ +#define DivOdd_T 0u +#define DivOdd_Y 1u +#define DivOdd_X 2u +#define DivOdd_R 3u +#define DivOdd_T1 4u +#define DivOdd_Ri 5u +#define DivOdd_Xa 6u +#define DivOdd_Xb 7u +#define DivOdd_CONST0 8u +#define DivOdd_UPTRT_SIZE 9u + + +#endif /* MCUXCLMATH_INTERNAL_EXACTDIVIDEODD_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ModInv.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ModInv.h new file mode 100644 index 000000000..a26448175 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_ModInv.h @@ -0,0 +1,39 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Internal_ModInv.h + * @brief mcuxClMath: internal header of modular inverse + */ + + +#ifndef MCUXCLMATH_INTERNAL_MODINV_H_ +#define MCUXCLMATH_INTERNAL_MODINV_H_ + +#include + + +/**********************************************************/ +/* Indices of operands in PKC workarea and UPTR table */ +/**********************************************************/ +#define MODINV_T 0u +#define MODINV_N 1u +#define MODINV_X 2u +#define MODINV_R 3u +#define MODINV_T1 4u +#define MODINV_CONST1 5u +#define MODINV_CONST0 6u +#define MODINV_UPTRT_SIZE 7u + + +#endif /* MCUXCLMATH_INTERNAL_MODINV_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_NDash.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_NDash.h new file mode 100644 index 000000000..7daf258e9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_NDash.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Internal_NDash.h + * @brief mcuxClMath: internal header of mcuxClMath_NDash + */ + + +#ifndef MCUXCLMATH_INTERNAL_NDASH_H_ +#define MCUXCLMATH_INTERNAL_NDASH_H_ + +#include + + +/**********************************************************/ +/* Indices of operands in PKC workarea and UPTR table */ +/**********************************************************/ +#define NDASH_T 0u +#define NDASH_N 1u +#define NDASH_NDASH 2u +#define NDASH_CONST2 3u +#define NDASH_CONST0 4u +#define NDASH_UPTRT_SIZE 5u + + +#endif /* MCUXCLMATH_INTERNAL_NDASH_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_QDash.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_QDash.h new file mode 100644 index 000000000..15860bf08 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_QDash.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Internal_QDash.h + * @brief mcuxClMath: internal header of mcuxClMath_QDash + */ + + +#ifndef MCUXCLMATH_INTERNAL_QDASH_H_ +#define MCUXCLMATH_INTERNAL_QDASH_H_ + +#include + + +/**********************************************************/ +/* Indices of operands in PKC workarea and UPTR table */ +/**********************************************************/ +#define QDASH_T 0u +#define QDASH_N 1u +#define QDASH_NS 2u +#define QDASH_QDASH 3u +#define QDASH_CONST0 4u +#define QDASH_UPTRT_SIZE 5u + +#endif /* MCUXCLMATH_INTERNAL_QDASH_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_SecModExp.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_SecModExp.h new file mode 100644 index 000000000..9e9d8bc95 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_SecModExp.h @@ -0,0 +1,139 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Internal_SecModExp.h + * @brief mcuxClMath: internal header of secure modular exponentiation + */ + + +#ifndef MCUXCLMATH_INTERNAL_SECMODEXP_H_ +#define MCUXCLMATH_INTERNAL_SECMODEXP_H_ + +#include + + +/**********************************************************/ +/* Indices of operands in PKC workarea and UPTR table */ +/**********************************************************/ +#define SECMODEXP_M0 0u +#define SECMODEXP_M2 1u +#define SECMODEXP_M1 2u +#define SECMODEXP_M3 3u +#define SECMODEXP_A0 4u +#define SECMODEXP_A1 5u +#define SECMODEXP_TE 6u +#define SECMODEXP_N 7u +#define SECMODEXP_V0 8u +#define SECMODEXP_V1 9u +#define SECMODEXP_NDASH 10u +#define SECMODEXP_R0 11u +#define SECMODEXP_R1 12u +#define SECMODEXP_R2 13u +#define SECMODEXP_R2H 14u +#define SECMODEXP_ZERO 15u +#define SECMODEXP_ONE 16u +#define SECMODEXP_UPTRT_SIZE 17u + +/**********************************************************/ +/* Inline asm macro */ +/**********************************************************/ +/** This macro securely select offsets Mi (i=0~3) according to 2 shares of exponent word. + * oMsH8 = ROL((M3H, M2H, M1H, M0H), 4); + * oMsL8 = ROL((M3L, M2L, M1L, M0L), 4), + * where, e.g., M3H/M3L are the higher/lower 8 bits of the 16-bit offset M3. + * + * ********************************************************** + * pseudocode: + * + * input: oMsH8, oMsL8, bIdx (not modified); rndW (destroyed); + * input/output: expW0, expW1, ofsA; + * output: ofsYX + * + * Functional algorithm: + * expW0 ^= rndW (can be skipped in functional version) + * expW1 ^= rndW (can be skipped in functional version) + * expW = expW0 ^ expW1 + * expBits = (expW >> (bIdx & 31)) & 3 + * rotateAmount = expBits*8 + 4 + * miH = oMsH8 >>> rotateAmount (right rotate) + * miL = oMsL8 >>> rotateAmount (right rotate) + * ofsYX = ((ofsA & 0xFFFF) << 16) | ((miH & 0xFF) << 8) | (miL & 0xFF) + * ofsA >>>= 16 (swap hi16 and lo16) + ******************************************************************************** + * It swaps ofsAt and ofsA(1-t) (stored in ofsAs), and outputs ofsYX = ofsA(1-t) || ofsMi. + */ +#if defined(ICCARM_ARMCLANG_GNUC) + +#define MCUXCLMATH_SECMODEXP_WRITEOFFSET(ofsY_ofsX,maskVal) MCUXCLPKC_PS1_SETXY_REG(ofsY_ofsX) +#define MCUXCLMATH_SECMODEXP_SECUREOFFSETSELECT(expW0_, expW1_, ofsAs_, ofsYX_, rndW_, bIdx_, oMsH8_, oMsL8_, rnd64_0_, rnd64_1_, mask_) \ +do{ \ + uint32_t temp0, temp1; /* local variable */ \ + (void) (rnd64_0_); /* unused variable, avoid compiler warning */ \ + (void) (rnd64_1_); /* unused variable, avoid compiler warning */ \ + (void) (mask_); /* unused variable, avoid compiler warning */ \ + __asm volatile ( \ + "EORS %[exp0], %[exp0], %[rnd] \n" \ + "SUBS %[tmp0], %[bIdx], #3 \n" \ + "ROR %[tmp0], %[exp0], %[tmp0] \n" /* rotate exp0[i+1:i] to tmp0[4:3] */ \ +\ + "EORS %[exp1], %[exp1], %[rnd] \n" \ + "ROR %[tmp1], %[exp1], %[bIdx] \n" /* rotate exp1[i+1:i] to tmp1[1:0] */ \ + "BFI %[rnd], %[tmp1], #3, #2 \n" /* insert exp1[i+1:i] to rnd[4:3] */ \ +\ + "EORS %[tmp1], %[rnd], %[tmp0] \n" /* tmp1[4:3] = exp[i+1:i] */ \ + "BIC %[tmp1], %[tmp1], #3 \n" /* clear rnd[1:0] */ \ + "ORR %[tmp1], %[tmp1], #4 \n" /* set rnd[2] */ \ + "ROR %[tmp0], %[ofL8], %[tmp1] \n" /* tmp0[7:0] = Mi[7:0] */ \ + "ROR %[tmp1], %[ofH8], %[tmp1] \n" /* tmp1[7:0] = Mi[15:8] */ \ +\ + "BFI %[rnd], %[tmp0], #0, #8 \n" \ + "BFI %[rnd], %[tmp1], #8, #8 \n" \ + "BFI %[rnd], %[ofAs], #16, #16 \n" /* set offsetY @hi16 */ \ + "ROR %[ofAs], %[ofAs], #16 \n" /* swap A0 and A1, i.e., let t := 1-t. */ \ +\ + : [exp0] "+&r" (expW0_), \ + [exp1] "+&r" (expW1_), \ + [ofAs] "+r" (ofsAs_), \ + [rnd] "+&r" (rndW_), \ + [tmp0] "=&r" (temp0), \ + [tmp1] "=&r" (temp1) \ + : [bIdx] "r" (bIdx_), \ + [ofH8] "r" (oMsH8_), \ + [ofL8] "r" (oMsL8_) \ + : "cc" \ + ); \ + (ofsYX_) = (rndW_); \ +} while (false) + +#else +#warning Unsupported compiler. The above section must be manually adapted to support the inline assembly syntax. +#define MCUXCLMATH_SECMODEXP_WRITEOFFSET(ofsY_ofsX,maskVal) MCUXCLPKC_PS1_SETXY_REG(ofsY_ofsX) +#define MCUXCLMATH_ROR(x,y) (((x) >> (y)) | ((x) << ((32u - (y)) & 31u))) +#define MCUXCLMATH_SECMODEXP_SECUREOFFSETSELECT(expW0, expW1, ofsA, ofsYX, rndW, bIdx, oMsH8, oMsL8,rand64_0,rand64_1,mask) \ +do{ \ + (void) (rndW); /* unused variable, avoid compiler warning */ \ + (void) (rand64_0); /* unused variable, avoid compiler warning */ \ + (void) (rand64_1); /* unused variable, avoid compiler warning */ \ + (void) (mask); /* unused variable, avoid compiler warning */ \ + uint32_t expW = (expW0) ^ (expW1); \ + uint32_t expBits = (expW >> ((bIdx) & 31u)) & 3u; \ + uint32_t rotateAmount = expBits * 8u + 4u; \ + uint32_t miH = MCUXCLMATH_ROR((oMsH8), rotateAmount); \ + uint32_t miL = MCUXCLMATH_ROR((oMsL8), rotateAmount); \ + (ofsYX) = ((((ofsA) & 0xFFFFu) << 16u) | ((miH & 0xFFu) << 8u) | (miL & 0xFFu)); \ + (ofsA) = MCUXCLMATH_ROR((ofsA), 16u); \ +} while (false) +#endif + +#endif /* MCUXCLMATH_INTERNAL_SECMODEXP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_Utils.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_Utils.h new file mode 100644 index 000000000..3985de3c4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_Internal_Utils.h @@ -0,0 +1,69 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Utils_Math.h + * @brief platform independent abstraction over math related builtin functions + */ + +#ifndef MCUXCLMATH_INTERNAL_UTILS_H_ +#define MCUXCLMATH_INTERNAL_UTILS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Count leading zeros of non-zero value. + * If the value is 0, the result is undefined. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_CountLeadingZerosWord) +static inline uint32_t mcuxClMath_CountLeadingZerosWord(uint32_t value) +{ +#ifdef __CLZ + return __CLZ(value); +#else + return (uint32_t)__builtin_clz(value); +#endif +} + +/* + * Count trailing zeros of non-zero value. + * If the value is 0, the result is undefined. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_CountTrailingZeroesWord) +static inline uint32_t mcuxClMath_CountTrailingZeroesWord(uint32_t value) +{ +#if defined(__CLZ) && defined(__RBIT) + return __CLZ(__RBIT(value)); +#else + uint32_t zeroes = 0u; + uint32_t valueShifted = value; + uint32_t lsb = valueShifted & 0x01u; + while((lsb == 0u) && (zeroes < 32u) ) + { + zeroes++; + valueShifted >>= 1u; + lsb = valueShifted & 0x01u; + } + return zeroes; +#endif +} + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /*MCUXCLMATH_INTERNAL_UTILS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ModInv_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ModInv_FUP.h new file mode 100644 index 000000000..06a541be9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_ModInv_FUP.h @@ -0,0 +1,48 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ModInv_FUP.h + * @brief defines FUP program byte arrays for mcuxClMath_ModInv + */ + +#ifndef MCUXCLMATH_MODINV_FUP_H_ +#define MCUXCLMATH_MODINV_FUP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClMath_ModInv_Fup1 + */ +#define mcuxClMath_ModInv_Fup1_LEN 7u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup1[7]; + +/* + * FUP program declaration mcuxClMath_ModInv_Fup3 + */ +#define mcuxClMath_ModInv_Fup3_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3a[mcuxClMath_ModInv_Fup3_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3b[mcuxClMath_ModInv_Fup3_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_MODINV_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_NDash_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_NDash_FUP.h new file mode 100644 index 000000000..83887ccab --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_NDash_FUP.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_NDash_FUP.h + * @brief defines FUP program byte arrays for mcuxClMath_NDash + */ + +#ifndef MCUXCLMATH_NDASH_FUP_H_ +#define MCUXCLMATH_NDASH_FUP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClMath_NDash_Fup + */ +#define mcuxClMath_NDash_Fup_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_NDash_Fup[mcuxClMath_NDash_Fup_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_NDASH_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_QDash_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_QDash_FUP.h new file mode 100644 index 000000000..6bdbc73c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_QDash_FUP.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_QDash_FUP.h + * @brief defines FUP program byte arrays for mcuxClMath_QDash + */ + +#ifndef MCUXCLMATH_QDASH_FUP_H_ +#define MCUXCLMATH_QDASH_FUP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClMath_QDash_Fup_Init + */ +#define mcuxClMath_QDash_Fup_Init_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Init[mcuxClMath_QDash_Fup_Init_LEN]; + +/* + * FUP program declaration mcuxClMath_QDash_Fup_Loop0 + */ +#define mcuxClMath_QDash_Fup_Loop0_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop0[mcuxClMath_QDash_Fup_Loop0_LEN]; + +/* + * FUP program declaration mcuxClMath_QDash_Fup_Loop1 + */ +#define mcuxClMath_QDash_Fup_Loop1_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop1[mcuxClMath_QDash_Fup_Loop1_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_QDASH_FUP_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_SecModExp_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_SecModExp_FUP.h new file mode 100644 index 000000000..991038271 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/internal/mcuxClMath_SecModExp_FUP.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_SecModExp_FUP.h + * @brief defines FUP program byte arrays for mcuxClMath_SecModExp + */ + +#ifndef MCUXCLMATH_SECMODEXP_FUP_H_ +#define MCUXCLMATH_SECMODEXP_FUP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * FUP program declaration mcuxClMath_Fup_Aws_Init + */ +#define mcuxClMath_Fup_Aws_Init_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Init[mcuxClMath_Fup_Aws_Init_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_Aws_Rerand + */ +#define mcuxClMath_Fup_Aws_Rerand_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Rerand[mcuxClMath_Fup_Aws_Rerand_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_EuclideanSplit_1 + */ +#define mcuxClMath_Fup_EuclideanSplit_1_LEN 8u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_1[mcuxClMath_Fup_EuclideanSplit_1_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_EuclideanSplit_2 + */ +#define mcuxClMath_Fup_EuclideanSplit_2_LEN 7u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_2[mcuxClMath_Fup_EuclideanSplit_2_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_ExactDivideLoop + */ +#define mcuxClMath_Fup_ExactDivideLoop_LEN 9u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideLoop[mcuxClMath_Fup_ExactDivideLoop_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_CalcQAndInterleave + */ +#define mcuxClMath_Fup_CalcQAndInterleave_LEN 6u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_CalcQAndInterleave[mcuxClMath_Fup_CalcQAndInterleave_LEN]; + +/* + * FUP program declaration mcuxClMath_Fup_PrepareFirstExp + */ +#define mcuxClMath_Fup_PrepareFirstExp_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_PrepareFirstExp[mcuxClMath_Fup_PrepareFirstExp_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_SECMODEXP_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath.h new file mode 100644 index 000000000..9d7f126a9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath.h + * @brief Top level header of mcuxClMath component + * + * @defgroup mcuxClMath mcuxClMath + * @brief component of mathematics functions + */ + + +#ifndef MCUXCLMATH_H_ +#define MCUXCLMATH_H_ + +#include +#include +#include + + +#endif /* MCUXCLMATH_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ExactDivideOdd_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ExactDivideOdd_FUP.h new file mode 100644 index 000000000..3638df5de --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ExactDivideOdd_FUP.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMath_ExactDivideOdd_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLMATH_EXACTDIVIDEODD_FUP_H_ +#define MCUXCLMATH_EXACTDIVIDEODD_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_DivideLoop[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_NDashY[4]; + +#endif /* MCUXCLMATH_EXACTDIVIDEODD_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Functions.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Functions.h new file mode 100644 index 000000000..a164403e7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Functions.h @@ -0,0 +1,768 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Functions.h + * @brief APIs of mcuxClMath component + */ + + +#ifndef MCUXCLMATH_FUNCTIONS_H_ +#define MCUXCLMATH_FUNCTIONS_H_ + + +#include +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClMath_Functions mcuxClMath_Functions + * @brief Defines all functions of @ref mcuxClMath + * @ingroup mcuxClMath + * @{ + */ + + +/** + * @brief Initializes and uses the new UPTRT and returns the address of original UPTRT. + * + * This function copies up to 8 offsets of PKC operands from current UPTRT to the new UPTRT, + * sets PKC to use the new UPTRT, and returns the address of original UPTRT. + * + * @param[in] i3_i2_i1_i0 the first 4 indices of offsets to be copied + * @param[in] i7_i6_i5_i4 the second 4 indices of offsets to be copied + * @param[in,out] localPtrUptrt address of the new UPTRT to be filled + * @param[in] noOfIndices number of offsets to be copied from original UPTRT to new UPTRT + * @param[out] oldPtrUptrt pointer to where receives the original UPTRT address + * + *
+ *
Parameter properties
+ *
+ *
@p i3_i2_i1_i0
+ *
i0 (bits 0~7): originalUptrt[i0] will be copied to @p localPtrUptrt[0], if @p noOfIndices >= 1. + *
i1 (bits 8~15): originalUptrt[i1] will be copied to @p localPtrUptrt[1], if @p noOfIndices >= 2. + *
i2 (bits 16~23): originalUptrt[i2] will be copied to @p localPtrUptrt[2], if @p noOfIndices >= 3. + *
i3 (bits 24~31): originalUptrt[i3] will be copied to @p localPtrUptrt[3], if @p noOfIndices >= 4.
+ *
@p i7_i6_i5_i4
+ *
i4 (bits 0~7): originalUptrt[i4] will be copied to @p localPtrUptrt[4], if @p noOfIndices >= 5. + *
i5 (bits 8~15): originalUptrt[i5] will be copied to @p localPtrUptrt[5], if @p noOfIndices >= 6. + *
i6 (bits 16~23): originalUptrt[i6] will be copied to @p localPtrUptrt[6], if @p noOfIndices >= 7. + *
i7 (bits 24~31): originalUptrt[i7] will be copied to @p localPtrUptrt[7], if @p noOfIndices >= 8.
+ *
@p localPtrUptrt
+ *
This address shall be 2-byte aligned. + *
Caller shall allocate at least @p noOfIndices 2-byte entries in this table.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
UPTRT
+ *
This function will retrieve the original UPTRT address and return it to caller via @p oldPtrUptrt. + *
This function will overwrite this address by @p localPtrUptrt.
+ *
PS1 lengths
+ *
Unused.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
This function shall not be called during a running FUP program (i.e., GOANY bit is set). + * Caller shall call #mcuxClPkc_WaitForReady before calling this function, if a FUP program has been called.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_InitLocalUptrt) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_InitLocalUptrt( + uint32_t i3_i2_i1_i0, + uint32_t i7_i6_i5_i4, + uint16_t *localPtrUptrt, + uint8_t noOfIndices, + const uint16_t **oldPtrUptrt + ); + + +/** + * @brief Counts number of leading zero bits of a PKC operand. + * + * This function counts the number of leading zero bits of a PKC operand + * at offset UPTRT[iX] and of size PS1 OPLEN. + * + * @param[in] iX index of PKC operand + * @param[out] pNumLeadingZeros pointer to where the number of leading zero bits will be stored + * + *
+ *
Parameter properties
+ *
+ *
@p iX
+ *
index of X (PKC operand), size = operandSize. + *
The offset (UPTRT[iX]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
This function will not use PKC, and assumes PKC will not modify the operand iX simultaneously.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_LeadingZeros) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_LeadingZeros( + uint8_t iX, + uint32_t *pNumLeadingZeros + ); + + +/** + * @brief Counts number of trailing zero bits of a PKC operand. + * + * This function counts the number of trailing zero bits of a PKC operand + * at offset UPTRT[iX] and of size PS1 OPLEN. + * + * @param[in] iX index of PKC operand + * + *
+ *
Parameter properties
+ *
+ *
@p iX
+ *
index of X (PKC operand), size = operandSize. + *
The offset (UPTRT[iX]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
This function will not use PKC, and assumes PKC will not modify the operand iX simultaneously.
+ *
+ *
+ * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval #numTrailingZeroes Number of trailing zeroes + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_TrailingZeros) +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClMath_TrailingZeros( + uint8_t iX + ); + + +/** + * @brief Prepares shifted modulus + * + * This function left shifts modulus (PKC operand iN) until there is no leading zero + * and stores the result in PKC operand iNShifted. + * + * @param[in] iNShifted_iN indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p iNShifted_iN
+ *
iN (bits 0~7): index of modulus (PKC operand), size = operandSize. + *
The modulus shall be non-zero. + *
The offset (UPTRT[iN]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iNShifted (bits 8~15): index of shifted modulus (PKC operand), size = operandSize. + *
This function supports in-place operation, i.e., iNShifted = iN.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ShiftModulus) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ShiftModulus( + uint16_t iNShifted_iN + ); +/** Helper macro for #mcuxClMath_ShiftModulus. */ +#define MCUXCLMATH_SHIFTMODULUS(iNShifted, iN) \ + mcuxClMath_ShiftModulus(MCUXCLPKC_PACKARGS2(iNShifted, iN)) +/** Helper macro for #mcuxClMath_ShiftModulus with flow protection. */ +#define MCUXCLMATH_FP_SHIFTMODULUS(iNShifted, iN) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_SHIFTMODULUS(iNShifted, iN)) + + +/** + * @brief Prepares modulus (calculates NDash) for PKC modular multiplication. + * + * This function calculates NDash = (-modulus)^(-1) mod 256^(MCUXCLPKC_WORDSIZE) + * and stores NDash in the PKC word in front of the PKC operand of modulus (iN). + * + * @param[in] iN_iT indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p iN_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
The size of temp shall be at least (2 * MCUXCLPKC_WORDSIZE). + *
iN (bits 8~15): index of modulus (PKC operand). + *
The modulus shall be an odd number. + *
The result NDash will be stored in the PKC word before modulus, + * i.e., at the offset, (UPTRT[iN] - MCUXCLPKC_WORDSIZE).
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
Unused.
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_NDash) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_NDash( + uint16_t iN_iT + ); +/** Helper macro for #mcuxClMath_NDash. */ +#define MCUXCLMATH_NDASH(iN, iT) \ + mcuxClMath_NDash(MCUXCLPKC_PACKARGS2(iN, iT)) +/** Helper macro for #mcuxClMath_NDash with flow protection. */ +#define MCUXCLMATH_FP_NDASH(iN, iT) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_NDASH(iN, iT)) + + +/** + * @brief Calculates QDash = Q * Q' mod n, where Q = 256^(operandSize) mod n, and Q' = 256^length mod n. + * + * This function computes QDash which can be used to convert a PKC operand + * (of the size @p length) to its Montgomery representation (of the size operandSize). + * + * @param[in] iQDash_iNShifted_iN_iT indices of PKC operands + * @param[in] length specify Q' = 256^length mod n + * + *
+ *
Parameter properties
+ *
+ *
@p iQDash_iNShifted_iN_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
The size of temp shall be at least (operandSize + MCUXCLPKC_WORDSIZE). + *
iN (bits 8~15): index of modulus (PKC operand), size = operandSize. + *
NDash of modulus shall be stored in the PKC word before modulus. + *
iNShifted (bits 16~23): index of shifted modulus (PKC operand), size = operandSize. + *
If there is no leading zero in the PKC operand modulus, it can be iN. + *
iQDash (bits 24~31): index of result QDash (PKC operand), size = operandSize. + *
QDash might be greater than modulus.
+ *
@p length
+ *
It shall be nonzero. A zero length will cause undefined behavior.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_QDash) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QDash( + uint32_t iQDash_iNShifted_iN_iT, + uint16_t length + ); +/** Helper macro for #mcuxClMath_QDash. */ +#define MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len) \ + mcuxClMath_QDash(MCUXCLPKC_PACKARGS4(iQDash, iNShifted, iN, iT), len) +/** Helper macro for #mcuxClMath_QDash with flow protection. */ +#define MCUXCLMATH_FP_QDASH(iQDash, iNShifted, iN, iT, len) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_QDASH(iQDash, iNShifted, iN, iT, len)) + + +/** + * @brief Calculates QSquared = Q^2 mod n, where Q = 256^(operandSize) mod n. + * + * This function computes QSquared which can be used to convert a PKC operand + * to its Montgomery representation (both are of the size operandSize). + * + * @param[in] iQSqr_iNShifted_iN_iT indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p iQSqr_iNShifted_iN_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
The size of temp shall be at least (operandSize + MCUXCLPKC_WORDSIZE). + *
iN (bits 8~15): index of modulus (PKC operand), size = operandSize. + *
NDash of modulus shall be stored in the PKC word before modulus. + *
iNShifted (bits 16~23): index of shifted modulus (PKC operand), size = operandSize. + *
If there is no leading zero in the PKC operand modulus, it can be iN. + *
iQSqr (bits 24~31): index of result QSquared (PKC operand), size = operandSize. + *
QSquared might be greater than modulus.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize and shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_QSquared) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QSquared( + uint32_t iQSqr_iNShifted_iN_iT + ); +/** Helper macro for #mcuxClMath_QSquared. */ +#define MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT) \ + mcuxClMath_QSquared(MCUXCLPKC_PACKARGS4(iQSqr, iNShifted, iN, iT)) +/** Helper macro for #mcuxClMath_QSquared with flow protection. */ +#define MCUXCLMATH_FP_QSQUARED(iQSqr, iNShifted, iN, iT) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_QSQUARED(iQSqr, iNShifted, iN, iT)) + + +/** + * @brief Calculates modular inversion, with odd modulus + * + * This function calculates modular inversion, result = X^(-1) mod n. + * + * @param[in] iR_iX_iN_iT indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p iR_iX_iN_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
Its size shall be at least (operandSize + MCUXCLPKC_WORDSIZE). + *
The offset (UPTRT[iT]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iN (bits 8~15): index of modulus (PKC operand), size = operandSize. + *
NDash of modulus shall be stored in the PKC word before modulus. + *
iX (bits 16~23): index of X (PKC operand), size = operandSize. + *
X will be destroyed by this function. + *
X and the modulus shall be coprime, otherwise the result will be incorrect. + *
iR (bits 24~31): index of result (PKC operand). + *
Its size shall be at least (operandSize + MCUXCLPKC_WORDSIZE). + *
The offset (UPTRT[iR]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
The result fits in operandSize, but might be greater than modulus.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize.
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ModInv) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModInv( + uint32_t iR_iX_iN_iT + ); +/** Helper macro for #mcuxClMath_ModInv. */ +#define MCUXCLMATH_MODINV(iR, iX, iN, iT) \ + mcuxClMath_ModInv(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT)) +/** Helper macro for #mcuxClMath_ModInv with flow protection. */ +#define MCUXCLMATH_FP_MODINV(iR, iX, iN, iT) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_MODINV(iR, iX, iN, iT)) + + +/** + * @brief Calculates modular reduction with even modulus + * + * This function calculates modular reduction result = X mod n, where the modulus n is even. + * + * @param[in] iR_iX_iN_iT0 indices of PKC operands + * @param[in] iT1_iT2_iT3 indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p iR_iX_iN_iT0
+ *
iT0 (bits 0~7): index of temp0 (PKC operand). + *
Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE). + *
The operand of modulus can be used as temp0 (i.e., iT0 = iN), but the modulus will be destroyed. + *
iN (bits 8~15): index of modulus (PKC operand), size = lenN. + *
The offset (UPTRT[iN]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iX (bits 16~23): index of X (PKC operand). + *
Its size shall be at least (lenX + MCUXCLPKC_WORDSIZE). + *
iR (bits 24~31): index of result (PKC operand). + *
Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+ *
@p iT1_iT2_iT3
+ *
iT3 (bits 0~7): index of temp3 (PKC operand). + *
Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE). + *
iT2 (bits 8~15): index of temp2 (PKC operand). + *
Its size shall be at least lenN. + *
iT1 (bits 16~23): index of temp1 (PKC operand). + *
Its size shall be at least lenN. + *
The operand of result can be used as temp1 (i.e., iT1 = iR). + * TODO: always use R (any reason not using R?)
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN defines lenN (length of modulus n), and MCLEN defines lenX (length of X). + *
Both OPLEN and MCLEN shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ReduceModEven) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ReduceModEven( + uint32_t iR_iX_iN_iT0, + uint32_t iT1_iT2_iT3 + ); +/** Helper macro for #mcuxClMath_ReduceModEven. */ +#define MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3) \ + mcuxClMath_ReduceModEven(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT0), MCUXCLPKC_PACKARGS4(0u, iT1, iT2, iT3)) +/** Helper macro for #mcuxClMath_ReduceModEven with flow protection. */ +#define MCUXCLMATH_FP_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_REDUCEMODEVEN(iR, iX, iN, iT0, iT1, iT2, iT3)) + + +/** + * @brief Calculates modular exponentiation. + * + * This function calculates modular exponentiation with left-to-right binary + * square-and-multiply algorithm. + * + * @param[in] pExp pointer to exponent + * @param[in] expByteLength byte length of exponent + * @param[in] iR_iX_iN_iT indices of PKC operands + * + *
+ *
Parameter properties
+ *
+ *
@p pExp
+ *
the exponent is a big-endian octet string and shall be non-zero.
+ *
@p iR_iX_iN_iT
+ *
iT (bits 0~7): index of temp operand (PKC operand). + *
Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE). + *
iN (bits 8~15): index of modulus (PKC operand), size = operandSize. + *
NDash of modulus shall be stored in the PKC word before modulus. + *
iX (bits 16~23): index of base number (PKC operand), size = operandSize. + *
iR (bits 24~31): index of result (PKC operand). + *
Its size shall be at least (lenN + MCUXCLPKC_WORDSIZE).
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize.
+ *
PS2 lengths
+ *
Unused.
+ *
ACTIV/GOANY
+ *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ModExp_SqrMultL2R) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModExp_SqrMultL2R( + const uint8_t *pExp, + uint32_t expByteLength, + uint32_t iR_iX_iN_iT + ); +/** Helper macro for #mcuxClMath_ModExp_SqrMultL2R. */ +#define MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT) \ + mcuxClMath_ModExp_SqrMultL2R(pExp, byteLenExp, MCUXCLPKC_PACKARGS4(iR, iX, iN, iT)) +/** Helper macro for #mcuxClMath_ModExp_SqrMultL2R with flow protection. */ +#define MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_MODEXP_SQRMULTL2R(pExp, byteLenExp, iR, iX, iN, iT)) + + +/** + * @brief Securely calculates modular exponentiation. + * + * This function calculates modular exponentiation in a secure manner. + * It randomizes the computation by Euclidean splitting: exponent = b * q + r, + * where b is a 64-bit odd random number (with both MSbit and LSbit set), and + * r = exponent % b. The exponentiation is calculated by two steps: + * (1) m0 = m^q mod n; and (2) result = m0^b * m^r mod n. + * In addition, base operands are re-randomized, by adding random multiples of the + * modulus to them before performing modular multiplications. + * + * @param[in] pSession handle for the current CL session. + * @param[in] pExp pointer to exponent + * @param[in] pExpTemp pointer to temporary buffer + * @param[in] expByteLength byte length of exponent + * @param[in] iT3_iX_iT2_iT1 indices of PKC operands + * @param[in] iN_iTE_iT0_iR indices of PKC operands + * @param[in] secOption option to disable the operand re-randomization + * + *
+ *
Parameter properties
+ *
+ *
@p session:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function.
+ *
@p pExp
+ *
the exponent is a big-endian octet string and shall be non-zero.
+ *
@p pExpTemp
+ *
the temporary buffer can be in either CPU or PKC workarea. + *
It shall be CPU word aligned, and its length shall be a multiple of CPU word and greater than @p expByteLength. + *
It can share the space with exponent (i.e., pExpTemp = pExp), but the exponent will be overwritten.
+ *
@p iT3_iX_iT2_iT1
+ *
iT1 (bits 0~7): index of temp1 (PKC operand). + *
Its size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(@p expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE). + *
iT2 (bits 8~15): index of temp2 (PKC operand). + *
Its size shall be at least max(lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE). + *
iX (bits 16~23): index of base number (PKC operand), size = operandSize + MCUXCLPKC_WORDSIZE (= lenN + MCUXCLPKC_WORDSIZE). + *
It will be overwritten. + *
iT3 (bits 24~31): index of temp3 (PKC operand). + *
Its size shall be at least max(lenN + MCUXCLPKC_WORDSIZE, 2 * MCUXCLPKC_WORDSIZE).
+ *
@p iN_iTE_iT0_iR
+ *
iR (bits 0~7): index of result (PKC operand). + *
The size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(@p expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE). + *
iT0 (bits 8~15): index of temp0 (PKC operand). + *
The size shall be at least max(MCUXCLPKC_ROUNDUP_SIZE(@p expByteLength + 1), lenN + MCUXCLPKC_WORDSIZE). + *
iTE (bits 16~23): index of temp4 (PKC operand). + *
The size shall be at least (6 * MCUXCLPKC_WORDSIZE). + *
iN (bits 24~31): index of modulus (PKC operand), size = operandSize (= lenN). + *
The upper 32 bits of N shall be null, which can be obtained for instance by applying 32-bit modulus blinding, + * or by artificially increasing PS1 lengths and all buffer sizes by 1 PKC word. + *
NDash of modulus shall be stored in the PKC word before modulus.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize = MCUXCLPKC_ROUNDUP_SIZE(lenN), where lenN is the length of modulus n.
+ *
As the upper 32 bits of N should be null, operandSize >= lenN + 4 bytes.
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller.
+ *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ * + * @return A code-flow protected error code (see @ref mcuxCsslFlowProtection) + * @retval #MCUXCLMATH_STATUS_OK function executed successfully + * @retval #MCUXCLMATH_STATUS_ERROR error occurred during operation + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_SecModExp) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) mcuxClMath_SecModExp( + mcuxClSession_Handle_t session, + const uint8_t *pExp, + uint32_t *pExpTemp, + uint32_t expByteLength, + uint32_t iT3_iX_iT2_iT1, + uint32_t iN_iTE_iT0_iR, + uint32_t secOption + ); +/** Helper macro for #mcuxClMath_SecModExp. */ +#define MCUXCLMATH_SECMODEXP(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3) \ + mcuxClMath_SecModExp(session, pExp, pExpTemp, byteLenExp, MCUXCLPKC_PACKARGS4(iT3, iX, iT2, iT1), MCUXCLPKC_PACKARGS4(iN, iTE, iT0, iR), 0u) +/** Helper macro for #mcuxClMath_SecModExp with disabled operand re-randomization. + * TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption to always re-randomize */ +#define MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION(session, pExp, pExpTemp, byteLenExp, iR, iX, iN, iTE, iT0, iT1, iT2, iT3) \ + mcuxClMath_SecModExp(session, pExp, pExpTemp, byteLenExp, MCUXCLPKC_PACKARGS4(iT3, iX, iT2, iT1), MCUXCLPKC_PACKARGS4(iN, iTE, iT0, iR), MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND) + + +/** + * @brief Calculates exact division with odd divisor. + * + * This function calculates exact division R = X/Y, where divisor Y is odd and + * dividend X shall be exactly a multiple of Y. If X is not a multiple of Y, + * result will be incorrect. + * + * @param[in] iR_iX_iY_iT indices of PKC operands + * @param[in] xPkcByteLength length of X + * @param[in] yPkcByteLength length of Y + * + *
+ *
Parameter properties
+ *
+ *
@p iR_iX_iY_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
Its size shall be at least (3 * MCUXCLPKC_WORDSIZE). + *
The offset (UPTRT[iT]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iY (bits 8~15): index of divisor Y (PKC operand), size = yPkcByteLength. + *
The most significant PKC word of Y shall be nonzero. + *
iX (bits 16~23): index of dividend X (PKC operand), size = xPkcByteLength. + *
X will be destroyed by this function. + *
CAUTION: if xPkcByteLength = MCUXCLPKC_WORDSIZE, + * this function will access to (read) one extra PKC word of X, i.e., + * X[MCUXCLPKC_WORDSIZE ~ 2*MCUXCLPKC_WORDSIZE - 1]. The value of this + * PKC word will not affect correctness of the result, but caller shall + * ensure that this PKC word is accessible by PKC. + *
iR (bits 24~31): index of result R (PKC operand), + * size = (xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE).
+ *
@p xPkcByteLength
+ *
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+ *
@p yPkcByteLength
+ *
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
Unused (modified and restored in the function).
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ExactDivideOdd) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivideOdd(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength); +/** Helper macro for #mcuxClMath_ExactDivideOdd. */ +#define MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \ + mcuxClMath_ExactDivideOdd(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT), xPkcByteLen, yPkcByteLen) +/** Helper macro for #mcuxClMath_ExactDivideOdd with flow protection. */ +#define MCUXCLMATH_FP_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_EXACTDIVIDEODD(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)) + + +/** + * @brief Calculates exact division (supporting even divisor). + * + * This function calculates exact division R = X/Y, where dividend X shall be + * exactly a multiple of divisor Y. If X is not a multiple of Y, result will be + * incorrect. + * + * This function trims trailing zero bits of Y and gets Y' = Y >> trailingZeros(Y), + * and X' = X >> ((trailingZeros(Y) / 8*MCUXCLPKC_WORDSIZE) * 8*MCUXCLPKC_WORDSIZE). + * It relies on mcuxClMath_ExactDivideOdd to calculate R' = X'/Y', and then calculates + * R = R' >> (trailingZeros(Y) % (8*MCUXCLPKC_WORDSIZE)). + * + * @param[in] iR_iX_iY_iT Pointer table indices of parameters + * @param[in] xPkcByteLength length of X + * @param[in] yPkcByteLength length of Y + * + *
+ *
Parameter properties
+ *
+ *
@p iR_iX_iY_iT
+ *
iT (bits 0~7): index of temp (PKC operand). + *
Its size shall be at least (3 * MCUXCLPKC_WORDSIZE). + *
iY (bits 8~15): index of divisor Y (PKC operand), size = yPkcByteLength. + *
The most significant PKC word of Y shall be nonzero. + *
The offset (UPTRT[iY]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iX (bits 16~23): index of dividend X (PKC operand), size = xPkcByteLength. + *
X will be destroyed by this function. + *
CAUTION: if the length of trimmed X' is MCUXCLPKC_WORDSIZE, + * this function will access to (read) one extra PKC word of X, i.e., + * X[xPkcByteLength ~ xPkcByteLength + MCUXCLPKC_WORDSIZE - 1]. + * The value of this PKC word will not affect correctness of the result, + * but caller shall ensure that this PKC word is accessible by PKC. + * If caller cannot guarantee the length of trimmed X' greater than + * MCUXCLPKC_WORDSIZE, X shall be stored in buffer of the size, + * xPkcByteLength + MCUXCLPKC_WORDSIZE. + *
iR (bits 24~31): index of result R (PKC operand). + * Its buffer size shall be at least (xPkcByteLength - yPkcByteLength + 2*MCUXCLPKC_WORDSIZE). + * The result fits in size = (xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE).
+ *
@p xPkcByteLength
+ *
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+ *
@p yPkcByteLength
+ *
It shall be a multiple of MCUXCLPKC_WORDSIZE.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
Unused (modified and restored in the function).
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_ExactDivide) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivide(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength); +/** Helper macro for #mcuxClMath_ExactDivide. */ +#define MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \ + mcuxClMath_ExactDivide(MCUXCLPKC_PACKARGS4(iR, iX, iN, iT), xPkcByteLen, yPkcByteLen) + +/** Helper macro for #mcuxClMath_ExactDivide with flow protection. */ +#define MCUXCLMATH_FP_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(MCUXCLMATH_EXACTDIVIDE(iR, iX, iN, iT, xPkcByteLen, yPkcByteLen)) + + +/** + * @} + */ /* mcuxClMath_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMATH_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ModInv_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ModInv_FUP.h new file mode 100644 index 000000000..c5c2d6329 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_ModInv_FUP.h @@ -0,0 +1,25 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMath_ModInv_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLMATH_MODINV_FUP_H_ +#define MCUXCLMATH_MODINV_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup1[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3a[3]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3b[3]; + +#endif /* MCUXCLMATH_MODINV_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_NDash_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_NDash_FUP.h new file mode 100644 index 000000000..f964a7fca --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_NDash_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMath_NDash_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLMATH_NDASH_FUP_H_ +#define MCUXCLMATH_NDASH_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_NDash_Fup[5]; + +#endif /* MCUXCLMATH_NDASH_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_QDash_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_QDash_FUP.h new file mode 100644 index 000000000..6f3c5aff8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_QDash_FUP.h @@ -0,0 +1,25 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMath_QDash_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLMATH_QDASH_FUP_H_ +#define MCUXCLMATH_QDASH_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Init[3]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop0[3]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop1[3]; + +#endif /* MCUXCLMATH_QDASH_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_SecModExp_FUP.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_SecModExp_FUP.h new file mode 100644 index 000000000..0f00a4d12 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_SecModExp_FUP.h @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMath_SecModExp_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLMATH_SECMODEXP_FUP_H_ +#define MCUXCLMATH_SECMODEXP_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Init[3]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Rerand[5]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_CalcQAndInterleave[6]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_1[8]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_2[7]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideLoop[9]; +extern const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_PrepareFirstExp[5]; + +#endif /* MCUXCLMATH_SECMODEXP_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Types.h b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Types.h new file mode 100644 index 000000000..f6614c420 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/inc/mcuxClMath_Types.h @@ -0,0 +1,69 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMac_Types.h + * @brief Type definitions for the mcuxClMac component + */ + + +#ifndef MCUXCLMATH_TYPES_H_ +#define MCUXCLMATH_TYPES_H_ + +#include +#include +#include + + +/********************************************** + * CONSTANTS + **********************************************/ +/* None */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClMath_Macros mcuxClMath_Macros + * @brief Defines all macros of @ref mcuxClMath + * @ingroup mcuxClMath + * @{ + */ + +/** + * @brief Type for error codes used by Math component functions. + */ +typedef uint32_t mcuxClMath_Status_t; + +/** + * @brief Deprecated type for error codes used by code-flow protected Math component functions. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) mcuxClMath_Status_Protected_t; + +#define MCUXCLMATH_STATUS_OK ((mcuxClMath_Status_t) 0x0FF32E03u) ///< Math operation successful +#define MCUXCLMATH_ERRORCODE_OK MCUXCLMATH_STATUS_OK ///< \deprecated Replaced by MCUXCLMATH_STATUS_OK +#define MCUXCLMATH_STATUS_ERROR ((mcuxClMath_Status_t) 0x0FF35330u) ///< Error occurred during Math operation +#define MCUXCLMATH_ERRORCODE_ERROR MCUXCLMATH_STATUS_ERROR ///< \deprecated Replaced by MCUXCLMATH_STATUS_ERROR + +/** + * @brief Option to disable the operand re-randomization in the secure modular exponentiation. + * TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption to always re-randomize + */ +#define MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND (0xA5A5A5A5u) + +/** + * @} + */ /* mcuxClMath_Macros */ + + +#endif /* MCUXCLMATH_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivide.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivide.c new file mode 100644 index 000000000..2eb84c415 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivide.c @@ -0,0 +1,143 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ExactDivide.c + * @brief mcuxClMath: implementation of exact division + */ + + +#include +#include +#include + +#include +#include +#include + +#include + + +/** + * [DESIGN] + * + * Since mcuxClMath_ExactDivideOdd only supports odd divisor, this function trims + * trailing zero bits of Y and gets odd Y' = Y >> trailingZeros(Y). It also trims + * X' = X >> ((trailingZeros(Y) / 8*MCUXCLPKC_WORDSIZE) * 8*MCUXCLPKC_WORDSIZE), + * by shifting the address of X in UPTR table. It relies on mcuxClMath_ExactDivideOdd + * to calculate R' = X'/Y', and then calculates the result, + * R = R' >> (trailingZeros(Y) % (8*MCUXCLPKC_WORDSIZE)). + * + * Since mcuxClMath_ExactDivideOdd assumes there is no leading zero PKC word of Y', + * this function counts the number of leading zeros of Y' and updates the length + * of Y' if the number of leading zeros of Y' exceeds a PKC word. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ExactDivide) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivide(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ExactDivide); + + /* Backup PS1 length to restore in the end. */ + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + + /***************************************************************************************/ + /* Step 1: Count trailing zeros of Y and make Y odd to be used in math_ExactDivideOdd */ + /***************************************************************************************/ + + MCUXCLPKC_WAITFORFINISH(); + MCUXCLPKC_PS1_SETLENGTH(0u, yPkcByteLength); /* MCLEN on higher 16 bits is not used. */ + + uint32_t uptrtIndexY = (iR_iX_iY_iT >> 8) & 0xFFu; + + MCUX_CSSL_FP_FUNCTION_CALL(noOfTrailingZeroBits, mcuxClMath_TrailingZeros((uint8_t)uptrtIndexY)); + uint32_t noOfTrailingZeroPkcWords = noOfTrailingZeroBits / (8u * MCUXCLPKC_WORDSIZE); + + /* If number of trailing zero bits exceeds a PKC word, shift pointer in UPTR table. */ + uint32_t noOfShiftBytes = noOfTrailingZeroPkcWords * MCUXCLPKC_WORDSIZE; + + uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + pOperands[uptrtIndexY] = (uint16_t) (pOperands[uptrtIndexY] + noOfShiftBytes); + + uint32_t uptrtIndexX = (iR_iX_iY_iT >> 16) & 0xFFu; + pOperands[uptrtIndexX] = (uint16_t) (pOperands[uptrtIndexX] + noOfShiftBytes); + + /* Shift number of bits, which are less than one PKC word. */ + uint32_t noOfShiftBits = noOfTrailingZeroBits % (8u * MCUXCLPKC_WORDSIZE); + + uint32_t pkcByteLenYtmp = yPkcByteLength - noOfShiftBytes; + + MCUXCLPKC_PS1_SETLENGTH(0u, pkcByteLenYtmp); /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_FP_CALC_OP1_SHR(uptrtIndexY, uptrtIndexY, noOfShiftBits); + + /* If number of leading zero bits after shift exceeds a PKC word, reduce length of Y. */ + MCUXCLPKC_WAITFORFINISH(); + uint32_t leadingZeroBits; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros((uint8_t)uptrtIndexY, &leadingZeroBits)); + + if((8u * MCUXCLPKC_WORDSIZE) <= leadingZeroBits) + { + pkcByteLenYtmp -= MCUXCLPKC_WORDSIZE; + } + + /***************************************************************************************/ + /* Step 2: Call math_ExactDivideOdd with odd Y */ + /***************************************************************************************/ + + uint32_t uptrtIndexT = iR_iX_iY_iT & 0xFFu; + uint32_t uptrtIndexR = (iR_iX_iY_iT >> 24) & 0xFFu; + + MCUXCLMATH_FP_EXACTDIVIDEODD(uptrtIndexR, + uptrtIndexX, + uptrtIndexY, + uptrtIndexT, + xPkcByteLength - noOfShiftBytes, + pkcByteLenYtmp); + + /***************************************************************************************/ + /* Step 3: Recover y and shift result to account for trailing zero bits of y */ + /***************************************************************************************/ + + MCUXCLPKC_FP_CALC_OP1_SHL(uptrtIndexY, uptrtIndexY, noOfShiftBits); + + /* If number of leading zero bits of Y' after shift does not exceed a PKC word, */ + /* result R' is of the size (xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE). */ + /* An extra PKC word needs to be cleared before right shifting result R' with */ + /* OPLEN = xPkcByteLength - yPkcByteLength + (2u * MCUXCLPKC_WORDSIZE). */ + if((8u * MCUXCLPKC_WORDSIZE) > leadingZeroBits) + { + MCUXCLPKC_PS2_SETLENGTH_REG(MCUXCLPKC_WORDSIZE); /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_PS2_SETMODE(MCUXCLPKC_OP_CONST); + MCUXCLPKC_PS2_SETZR(0u, (uint32_t) pOperands[uptrtIndexR] + xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE); + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_START_L0(); + MCUXCLPKC_WAITFORREADY(); + } + + MCUXCLPKC_PS2_SETLENGTH(0u, xPkcByteLength - yPkcByteLength + (2u * MCUXCLPKC_WORDSIZE)); /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_FP_CALC_OP2_SHR(uptrtIndexR, uptrtIndexR, noOfShiftBits); + + /* Restore UPTR table and PKC settings. */ + pOperands[uptrtIndexY] = (uint16_t) (pOperands[uptrtIndexY] - noOfShiftBytes); + pOperands[uptrtIndexX] = (uint16_t) (pOperands[uptrtIndexX] - noOfShiftBytes); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ExactDivide, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_TrailingZeros), + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivideOdd), + MCUXCLPKC_FP_CALLED_CALC_OP1_SHL, + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd.c new file mode 100644 index 000000000..aad468369 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd.c @@ -0,0 +1,158 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ExactDivideOdd.c + * @brief mcuxClMath: implementation of exact divide with odd divisor + */ + + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/** + * [DESIGN] + * This function assumes the dividend X is exactly a multiple of the divisor Y. + * Since the most significant PKC word of Y is assumed to be nonzero, the result + * length is rPkcByteLen = xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE. + * This function calculates R = X/Y by solving R satisfying ((-X) + R*Y) mod W^rPkcWord, + * where W = 256^MCUXCLPKC_WORDSIZE and rPkcWord = rPkcByteLen / MCUXCLPKC_WORDSIZE. + * + * R is solved from its least significant PKC word R[0] to the most significant word R[rPkcWord - 1]. + * Let X0 = (-X) mod 256^rPkcByteLen. Since X0 + R*Y mod W = 0, + * R[0] = NDash(Y) * X0[0] mod W, where NDash(Y) = (-Y)^(-1) mod W. And X1 = (X0 + R[0]*Y)/W. + * This function calculates R[i] = NDash(Y) * Xi[0] mod W, and + * X{i+1} = (Xi + R[i]*Y)/W = (X0 + R[i:0]*Y)/(W^(i+1)), until i = rPkcWord - 1. + * + * Since X0 = (X{i+1}*(W^(i+1)) - R[i:0]*Y) \equiv 0 (mod W^rPkcWord), this function + * needs to calculate only the least significant (rPkcWord - (i+1)) PKC words of X{i+1}. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ExactDivideOdd) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ExactDivideOdd(uint32_t iR_iX_iY_iT, uint32_t xPkcByteLength, uint32_t yPkcByteLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ExactDivideOdd); + + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + + /* Prepare local UPTRT. */ + uint16_t pOperands[DivOdd_UPTRT_SIZE]; + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iR_iX_iY_iT, 0u, pOperands, 4u, &backupPtrUptrt)); + uint16_t offsetT = pOperands[DivOdd_T]; + pOperands[DivOdd_T1] = (uint16_t) (offsetT + MCUXCLPKC_WORDSIZE); + pOperands[DivOdd_Ri] = 2u; /* for _Fup_ExactDivideOdd_NDashY */ + pOperands[DivOdd_CONST0] = 0u; + + MCUX_CSSL_FP_LOOP_DECL(NDashY); + + MCUXCLPKC_PS2_SETLENGTH(0u, MCUXCLPKC_WORDSIZE); /* MCLEN on higher 16 bits is not used. */ + volatile uint32_t *pT = (volatile uint32_t *) MCUXCLPKC_OFFSET2PTRWORD(offsetT); + MCUXCLPKC_WAITFORFINISH(); + pT[0] = 1u; /* 1 = (-Y)^(-1) mod 2. */ + + /* Calculate T = NDash(Y) = (-Y)^(-1) mod W, where W = 256^MCUXCLPKC_WORDSIZE. */ + for (uint32_t bit = 1u; bit < (MCUXCLPKC_WORDSIZE * 8u); bit <<= 1u) + { + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_ExactDivideOdd_NDashY, + mcuxClMath_Fup_ExactDivideOdd_NDashY_LEN); + + MCUX_CSSL_FP_LOOP_ITERATION(NDashY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + } + + uint32_t rPkcByteLen = xPkcByteLength - yPkcByteLength + MCUXCLPKC_WORDSIZE; + MCUXCLPKC_WAITFORREADY(); + + /* Calculate X0 = -X mod W^rPkcWord, where rPkcWord = rPkcByteLen / MCUXCLPKC_WORDSIZE. */ + MCUXCLPKC_PS1_SETLENGTH(0u, rPkcByteLen); /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_FP_CALC_OP1_NEG(DivOdd_X, DivOdd_X); + + /* Prepare for carry handling. */ + /* When the length of Y is small, the MACCR in the FUP program in the loop */ + /* only calculates, e.g., (X[yPkcWord:0] + R[0]*Y)/W in the first iteration. */ + /* Carry propagation to X[rPkcWord-1:yPkcWord+1] needs to be handled separately. */ + uint32_t offsetX = (uint32_t) pOperands[DivOdd_X]; + pOperands[DivOdd_Xa] = (uint16_t) (offsetX + yPkcByteLength); + pOperands[DivOdd_Xb] = (uint16_t) (offsetX + yPkcByteLength + MCUXCLPKC_WORDSIZE); + uint32_t pkcByteLenCarryHandling = (rPkcByteLen > (yPkcByteLength + MCUXCLPKC_WORDSIZE)) + ? (rPkcByteLen - (yPkcByteLength + MCUXCLPKC_WORDSIZE)) : 0u; + + MCUX_CSSL_FP_LOOP_DECL(DivideLoop); + MCUX_CSSL_FP_LOOP_DECL(CarryHandling); + + /* Balance FP in advance to avoid keeping variables in register/stack. */ + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_LOOP_ITERATIONS(DivideLoop, rPkcByteLen / MCUXCLPKC_WORDSIZE), + MCUX_CSSL_FP_LOOP_ITERATIONS(CarryHandling, pkcByteLenCarryHandling / MCUXCLPKC_WORDSIZE) ); + + /* This loop calculates R[rPkcWord-1:0] such that X0 + R*Y mod W^rPkcWord = 0. */ + uint32_t rRemainingPkcByteLen = rPkcByteLen; + uint32_t offsetRi = (uint32_t) pOperands[DivOdd_R]; + do + { + /* In iteration i (i = 0 ~ rPkcWord-1), calculate R[i] and X{i+1}. */ + + /* Prepare OPLEN = min(yPkcWord, rPkcWord-i) * MCUXCLPKC_WORDSIZE. */ + uint32_t effectivePkcByteLenY = (rRemainingPkcByteLen > yPkcByteLength) + ? yPkcByteLength : rRemainingPkcByteLen; + + MCUXCLPKC_WAITFORREADY(); + pOperands[DivOdd_Ri] = (uint16_t) offsetRi; + MCUXCLPKC_PS1_SETLENGTH(0u, effectivePkcByteLenY); /* MCLEN on higher 16 bits is not used. */ + + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_ExactDivideOdd_DivideLoop, + mcuxClMath_Fup_ExactDivideOdd_DivideLoop_LEN); + + MCUX_CSSL_FP_LOOP_ITERATION(DivideLoop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + + offsetRi += MCUXCLPKC_WORDSIZE; + + /* Handle carry and copy most significant words of X{i+1}. */ + if (0u < pkcByteLenCarryHandling) + { + MCUXCLPKC_WAITFORFINISH(); + uint8_t carry = (uint8_t) MCUXCLPKC_GETCARRY(); + MCUXCLPKC_PS1_SETLENGTH(0u, pkcByteLenCarryHandling); /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_FP_CALC_OP1_ADD_CONST(DivOdd_Xa, DivOdd_Xb, carry); + + MCUX_CSSL_FP_LOOP_ITERATION(CarryHandling, + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD_CONST ); + + pkcByteLenCarryHandling -= MCUXCLPKC_WORDSIZE; + } + + rRemainingPkcByteLen -= MCUXCLPKC_WORDSIZE; + } while (0u != rRemainingPkcByteLen); + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ExactDivideOdd, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUX_CSSL_FP_LOOP_ITERATIONS(NDashY, MCUXCLPKC_LOG2_WORDSIZE + 3u), + MCUXCLPKC_FP_CALLED_CALC_OP1_NEG ); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd_FUP.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd_FUP.c new file mode 100644 index 000000000..21a844754 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ExactDivideOdd_FUP.c @@ -0,0 +1,47 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ExactDivideOdd_FUP.c + * @brief mcuxClMath: implementation of exact divide with odd divisor + */ + +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_DivideLoop[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xd5u,0x8bu,0x65u,0xe0u},{0x40u,0x20u,0x02u,0x00u,0x00u,0x00u},{0x40u,0x00u,0x02u,0x00u,0x00u,0x04u},{0x40u,0x1eu,0x00u,0x04u,0x08u,0x05u},{0x00u,0x62u,0x00u,0x01u,0x02u,0x02u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideOdd_NDashY[4] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x8fu,0x8au,0x30u,0x35u},{0x40u,0x00u,0x00u,0x01u,0x00u,0x04u},{0x40u,0x1au,0x00u,0x04u,0x05u,0x04u},{0x40u,0x00u,0x04u,0x00u,0x00u,0x00u}}; + + +/** + * [DESIGN] + * Suppose T \equiv (-Y)^(-1) (mod 2^(bit)). + * Since (T*Y+1) \equiv 0 (mod 2^(bit)), so (T*Y+1)^2 = ((T*Y+2)*T*Y + 1) \equiv 0 (mod 2^(2*bit)). + * This FUP program calculates: T := (T*Y+2)*T \equiv (-Y)^(-1) (mod 2^(2*bit)). + */ +/* PS2 length = (-, MCUXCLPKC_WORDSIZE) */ +/* uptrt[DivOdd_Ri] = 2 */ + +/** + * [DESIGN] + * In iteration i (i = 0 ~ rPkcWord-1), this FUP program calculates R[i], and + * X{i+1} = (Xi + R[i]*Y) / W = (X0 + R[i~0]*Y) / W^(i+1). + * + * CAUTION: + * The MACCR in this FUP program will access to t+1 PKC words of X, where + * t = min(yPkcWord, rPkcWord - i) = effectivePkcByteLenY / MCUXCLPKC_WORDSIZE. + * In the boundary case, t = 1 (when xPkcByteLen = yPkcByteLen = MCUXCLPKC_WORDSIZE), + * and 2 PKC words of X will be read (but xPkcByteLen = MCUXCLPKC_WORDSIZE). + */ +/* PS1 length = (-, effectivePkcByteLenY) */ +/* PS2 length = (-, MCUXCLPKC_WORDSIZE) */ diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModExp_SqrMultL2R.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModExp_SqrMultL2R.c new file mode 100644 index 000000000..3de66762e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModExp_SqrMultL2R.c @@ -0,0 +1,150 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ModExp_SqrMultL2R.c + * @brief mcuxClMath: modular exponentiation, left-to-right binary square and multiply + */ + + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +/** + * [DESIGN] + * This function calculates exponentiation x^exp mod n by left-to-right binary + * square-and-multiply algorithm. It scans the exponent from most to least + * significant bit. If a bit is 0, this algorithm performs a modular squaring; + * and if a bit is 1, it performs a modular squaring followed by a modular multiplication. + * + * Since PKC does not support in-place modular multiplication (squaring), this + * algorithm needs 2 operands T0 and T1. The computation is controlled by 2-bit "state". + * The indices of operands and result is stored in an array args[], indexed by "state". + * When a bit of exponent is 1, the loop of this algorithm will scan that bit twice: + * performs a modular squaring and a modular multiplication, i.e., state = + * 0b01 (square) --> 0b10 (multiply), or 0b11 (square) --> 0b00 (multiply). + * When a bit is 0, only a modular squaring is performed (state = 0b01 or 0b11), + * and then the loop moves to the next bit. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ModExp_SqrMultL2R) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModExp_SqrMultL2R(const uint8_t *pExp, uint32_t expByteLength, uint32_t iR_iX_iN_iT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ModExp_SqrMultL2R); + + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + + /* Count Hamming weight of exponent. */ + MCUX_CSSL_FP_COUNTER_STMT(uint32_t hwExp = 0u); + uint32_t byteIndex_MSNZByte = 0u; + + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_INT31_C, "expByteLength is bounded by memory size (and smaller than 2^16).") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_INT02_C, "expByteLength is bounded by memory size (and smaller than 2^16).") + for (int32_t idx = (int32_t) expByteLength - 1; idx >= 0; idx--) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_INT02_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_INT31_C) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "idx < expByteLength, which is bounded by memory size (and smaller than 2^16).") + uint32_t expByte = (uint32_t) pExp[idx]; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + /* Find the most significant nonzero byte (= the last nonzero byte when scanning from LSByte to MSByte). */ + if (0u != expByte) + { + byteIndex_MSNZByte = (uint32_t) idx; + } + + /* Count Hamming weight of a byte. */ + expByte = expByte - ((expByte >> 1) & 0x55u); + expByte = (expByte & 0x33u) + ((expByte & 0xCCu) >> 2); + expByte = (expByte & 0x07u) + ((expByte & 0x70u) >> 4); + MCUX_CSSL_FP_COUNTER_STMT(hwExp += expByte); + } + + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "byteIndex_MSNZByte < expByteLength, which is bounded by memory size (and smaller than 2^16).") + uint32_t byteExp = (uint32_t) pExp[byteIndex_MSNZByte]; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + /* Calculate bit index of starting bit (skip the most significant nonzero bit). */ + const uint32_t bitIndex_MSBitNext = (8u * (expByteLength - byteIndex_MSNZByte)) - (mcuxClMath_CountLeadingZerosWord(byteExp) - 24u) - 2u; + int32_t bitIndex = (int32_t) bitIndex_MSBitNext; + + /* Calculate the number of loop iteration for FP. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("bitIndex is capped at exponent bit length, and Hamming weight hwExp > 0 because exponent is non-zero.") + MCUX_CSSL_FP_COUNTER_STMT(const uint32_t loopIteration = (bitIndex_MSBitNext + 1u) + (hwExp - 1u)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + const uint32_t iR = (iR_iX_iN_iT >> 24) & 0xFFu; /* Also used as T1. */ + const uint32_t iX = (iR_iX_iN_iT >> 16) & 0xFFu; + const uint32_t iN = (iR_iX_iN_iT >> 8) & 0xFFu; + const uint32_t iT = iR_iX_iN_iT & 0xFFu; /* T0 */ + + MCUXCLPKC_FP_CALC_OP1_OR_CONST(iR, iX, 0u); /* Copy X to R (T1). */ + + uint32_t args[4]; + args[0] = MCUXCLPKC_PACKARGS4(iT,iR,iX,iN); /* state=0b00, T0 = T1 * X mod N (multiply) */ + args[1] = MCUXCLPKC_PACKARGS4(iT,iR,iR,iN); /* state=0b01, T0 = T1 * T1 mod N (square) */ + args[2] = MCUXCLPKC_PACKARGS4(iR,iT,iX,iN); /* state=0b10, T1 = T0 * X mod N (multiply) */ + args[3] = MCUXCLPKC_PACKARGS4(iR,iT,iT,iN); /* state=0b11, T1 = T0 * T0 mod N (square) */ + + uint32_t state = 1u; + uint32_t shift = 1u; /* shift to next bit (=1) or not (=0) */ + + MCUX_CSSL_FP_LOOP_DECL(SquMulLoop); + while(bitIndex >= 0) + { + MCUX_CSSL_FP_LOOP_ITERATION(SquMulLoop, + MCUXCLPKC_FP_CALLED_CALC_MC1_MM); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_MC1(MM), args[state])); + /* mcuxClPkc_Calc always returns OK. */ + + /* Swap the two temp operands. */ + state = 3u ^ state; + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + + /* Calculate byte index of exponent in BE. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_INT30_C, "expByteLength > 0, and bitIndex in range [0, 8*expByteLength - 2].") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "expByteLength > 0, and bitIndex in range [0, 8*expByteLength - 2].") + uint32_t expBit = ((uint32_t) pExp[expByteLength - 1u - ((uint32_t) bitIndex / 8u)] >> ((uint32_t) bitIndex & 7u)) & 1u; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_INT30_C) + + /* If expBit = 1, the while-loop will stay in this bit for one more iteration. */ + shift ^= expBit; + /* Always squaring in next iteration if shifting to a new bit (state = 0b01 or 0b11). */ + state |= shift; + + bitIndex -= (int32_t) shift; + } + + /* The result is in T1 (R) if state.bit1 = 0; */ + /* T0 (T) if state.bit1 = 1. */ + if (0u != (state >> 1)) + { + MCUXCLPKC_FP_CALC_OP1_OR_CONST(iR, iT, 0u); /* Copy result to R. */ + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ModExp_SqrMultL2R, + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_LOOP_ITERATIONS(SquMulLoop, loopIteration), + MCUX_CSSL_FP_CONDITIONAL((1u == (loopIteration & 0x01u)), MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST) ); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv.c new file mode 100644 index 000000000..ebb19e27d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv.c @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ModInv.c + * @brief mcuxClMath: modular inversion implementation + */ + + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ModInv) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ModInv(uint32_t iR_iX_iN_iT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ModInv); + + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + uint32_t operandSize = MCUXCLPKC_PS1_UNPACK_OPLEN(backupPs1LenReg); + operandSize &= ~((uint32_t) MCUXCLPKC_WORDSIZE - 1u); /* round down to a multiple of MCUXCLPKC_WORDSIZE, to calculate exponent correctly. */ + + /* Prepare local UPTRT. */ + uint16_t pOperands[MODINV_UPTRT_SIZE]; + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iR_iX_iN_iT, 0, pOperands, 4u, &backupPtrUptrt)); + + /* WAITFORREADY in mcuxClMath_InitLocalUptrt(...). */ + uint16_t offsetT = pOperands[MODINV_T]; + pOperands[MODINV_T1] = (uint16_t) (offsetT + MCUXCLPKC_WORDSIZE); + pOperands[MODINV_CONST1] = 0x0001u; + pOperands[MODINV_CONST0] = 0x0000u; + + MCUXCLPKC_PS1_SETLENGTH((uint32_t)31u * (uint32_t)MCUXCLPKC_WORDSIZE, operandSize); /* Loop counter = 31 for MCUXCLPKC_MC_MI. */ + MCUXCLPKC_PS2_SETLENGTH_REG(operandSize + MCUXCLPKC_WORDSIZE); /* MCLEN on higher 16 bits is not used. */ + + MCUXCLPKC_FP_CALCFUP(mcuxClMath_ModInv_Fup1, mcuxClMath_ModInv_Fup1_LEN ); + + const volatile uint32_t *pExp = (volatile uint32_t *) MCUXCLPKC_OFFSET2PTRWORD(offsetT); + volatile uint32_t *pR = (volatile uint32_t *) MCUXCLPKC_OFFSET2PTRWORD(pOperands[MODINV_R]); + + MCUXCLPKC_WAITFORFINISH(); + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + uint32_t exponent = *pExp; + uint32_t operandBitLen = operandSize << 3; + const mcuxClPkc_FUPEntry_t* mcuxClMath_ModInv_Fup3; + + if (exponent <= operandBitLen) + { + exponent = operandBitLen - exponent; + mcuxClMath_ModInv_Fup3 = mcuxClMath_ModInv_Fup3a; + } + else + { + exponent = (operandBitLen * 2u) - exponent; + mcuxClMath_ModInv_Fup3 = mcuxClMath_ModInv_Fup3b; + } + + /* Set R = 2^(operandBitLEn - exponent) or 2^(2*operandBitLEn - exponent). */ + pR[exponent >> 5] = (uint32_t) 1u << (exponent & 0x0000001Fu); + + /* Convert AlmostMontgomeryInverse to modular inverse. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_ModInv_Fup3, mcuxClMath_ModInv_Fup3_LEN); + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ModInv, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* Fup1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); /* Fup3a or Fup3b */ +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv_FUP.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv_FUP.c new file mode 100644 index 000000000..4040bd6db --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ModInv_FUP.c @@ -0,0 +1,39 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ModInv_FUP.c + * @brief mcuxClMath: modular inversion implementation + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup1[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x1bu,0x93u,0xa9u,0x40u},{0x40u,0x3eu,0x00u,0x00u,0x06u,0x00u},{0x00u,0x1au,0x00u,0x00u,0x05u,0x03u},{0x80u,0x5du,0x01u,0x02u,0x03u,0x04u},{0x00u,0x1eu,0x00u,0x03u,0x06u,0x01u},{0x00u,0x3eu,0x00u,0x00u,0x06u,0x03u},{0x80u,0x2au,0x01u,0x01u,0x04u,0x02u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3a[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xc9u,0x51u,0x7au,0xe2u},{0x80u,0x00u,0x02u,0x03u,0x01u,0x00u},{0x00u,0x1eu,0x00u,0x00u,0x06u,0x03u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_ModInv_Fup3b[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x00u,0xf6u,0x90u,0xd4u},{0x80u,0x00u,0x02u,0x03u,0x01u,0x00u},{0x80u,0x33u,0x00u,0x00u,0x01u,0x03u}}; + + +/* ps1Len = (31*MCUXCLPKC_WORDSIZE, operandSize), i.e., LC = 31 */ +/* ps2Len = ( -, operandSize + PKC wordsize) */ + +/* If the modulus n shall be restored even when x and n are not coprime, */ +/* n can be calculated by FUP_MC1_MMP2(MODINV_T, MODINV_N, MODINV_R). */ +/* ps, MMP2 needs extra PKC word of T as workspace, and this FUP program */ +/* needs to be split to backup T0 before calculating n. */ + +/* ps1Len = (operandSize, operandSize) */ + +/* ps1Len = (operandSize, operandSize) */ diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash.c new file mode 100644 index 000000000..9cca1e7d3 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash.c @@ -0,0 +1,101 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_NDash.c + * @brief mcuxClMath: implementation of the function mcuxClMath_NDash + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include + + +/** + * [Design] + * This function calculates NDash = (-n)^(-1) mod 256^(MCUXCLPKC_WORDSIZE), + * where n is an odd number, by using mathematical induction: + * + * Let x0 \equiv 1 (mod 2), and suppose xi \equiv (-n)^(-1) (mod 2^(2^i)). + * Since 1 + xi * n \equiv 0 (mod 2^(2^i)), so + * (1 + xi * n)^2 = 1 + (2*xi + xi^2 *n) * n \equiv 0 (mod 2^(2^(i+1))), and + * x_{i+1} \equiv 2*xi + xi^2 * n = (xi * n + 2) * xi (mod 2^(2^(i+1))). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_NDash) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_NDash(uint16_t iN_iT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_NDash); + + /* Prepare local UPTRT. */ + uint16_t pOperands[NDASH_UPTRT_SIZE]; + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt((uint32_t) iN_iT, 0, pOperands, 2u, &backupPtrUptrt)); + + /* WAITFORREADY in mcuxClMath_InitLocalUptrt(...). */ + uint16_t offsetNDash = pOperands[NDASH_N] - MCUXCLPKC_WORDSIZE; + pOperands[NDASH_NDASH] = offsetNDash; + pOperands[NDASH_CONST2] = 2u; + pOperands[NDASH_CONST0] = 0u; + + MCUXCLPKC_PS2_SETLENGTH(0, MCUXCLPKC_WORDSIZE); + + /* x1 \equiv 1 (mod 4), if n mod 4 = 3; */ + /* \equiv 3 (mod 4), if n mod 4 = 1. */ + MCUXCLPKC_FP_CALC_OP2_NEG(NDASH_NDASH, NDASH_N); + + for (uint32_t bit = 2u; bit < (MCUXCLPKC_WORDSIZE * 8u); bit <<= 1) + { + MCUXCLPKC_FP_CALCFUP(mcuxClMath_NDash_Fup, mcuxClMath_NDash_Fup_LEN); + } + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + +#if (16u == MCUXCLPKC_WORDSIZE) + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_NDash, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUXCLPKC_FP_CALLED_CALC_OP2_NEG, + /* hard-coded (log2PkcWordsize + 3) - 1 = 5 iterations of the loop. */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x2 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x6 = ... (mod 2^(2^6)). */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) /* calculate x7 = ... (mod 2^(2^7)). */ + ); +#else + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_NDash, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUXCLPKC_FP_CALLED_CALC_OP2_NEG, + /* hard-coded (log2PkcWordsize + 3) - 1 = 5 iterations of the loop. */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x2 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x3 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x4 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), /* calculate x5 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) /* calculate x6 = ... (mod 2^(2^6)). */ + ); +#endif + + +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash_FUP.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash_FUP.c new file mode 100644 index 000000000..520478f0d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_NDash_FUP.c @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_NDash_FUP.c + * @brief mcuxClMath: FUP program used in mcuxClMath_NDash + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClMath_NDash_Fup[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x33u,0x15u,0x36u,0x51u},{0x40u,0x00u,0x02u,0x01u,0x00u,0x00u},{0x40u,0x1au,0x00u,0x00u,0x03u,0x00u},{0x40u,0x00u,0x00u,0x02u,0x00u,0x00u},{0x40u,0x1eu,0x00u,0x00u,0x04u,0x02u}}; + + + +/** + * [DESIGN] + * Since the operand NDash is of the size MCUXCLPKC_WORDSIZE, + * the result of multiplication (OP2_MUL) is stored in T (2 * MCUXCLPKC_WORDSIZE), + * and then copied to NDash. + */ diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash.c new file mode 100644 index 000000000..3943a93e2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash.c @@ -0,0 +1,123 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_QDash.c + * @brief mcuxClMath: implementation of the functions mcuxClMath_QDash and mcuxClMathQSquared + */ + + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + + +/** + * [DESIGN] + * This function calculates QDash = Q * Q' mod n, where Q = 256^(PS1 OPLEN) mod n, + * and Q' = 256^length mod n, in the following steps: + * (1) calculate (Q mod n), which is the Montgomery representation of 1 modulo n. + * it is equivalent to NEG(n) = Q - n, the two's complement representation; + * (2) calculate the Montgomery representation of 2 by using modular addition: + * MA(NEG(n), NEG(n), ns) \equiv (NEG(n) + NEG(n) mod n), where ns = ShiftModulus(n); + * (3) calculate QDash, which is the Montgomery representation of Q', by using + * binary left-to-right exponentiation. Since the base number is 2, the modular + * multiplication with 2 in exponentiation is implemented as modular addition. + * + * ps, if there are many leading zeros in n, NEG(n) will be much bigger than n. + * Calculating MA in step (2) and (3) with shifted modulus ns can avoid + * too many iterations of subtraction loop. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_QDash) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QDash(uint32_t iQDash_iNShifted_iN_iT, uint16_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_QDash); + + uint16_t pOperands[QDASH_UPTRT_SIZE]; + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iQDash_iNShifted_iN_iT, 0, pOperands, 4u, &backupPtrUptrt)); + pOperands[QDASH_CONST0] = 0u; + + /* Prepare 2Q mod n, which is the Montgomery representation of 2. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_QDash_Fup_Init, mcuxClMath_QDash_Fup_Init_LEN); + + /* Prepare exponent for calculating (2^8)^(length) = 2^(8 * length). */ + uint32_t exponent = (uint32_t) length << 3; + + /* Scan exponent from MSbit (bit 15 + 3), and skip leading zeros plus one more bit (leading 1). */ + uint32_t bitMask = (uint32_t) 1u << ((8u * (sizeof(uint16_t))) - 1u + 3u); + uint32_t bit; + do + { + bit = exponent & bitMask; + bitMask >>= 1; + } while(0u == bit); /* Assume exponent != 0, otherwise, this is an endless loop. */ + + MCUX_CSSL_FP_LOOP_DECL(QDash_SquareMultiply); + do + { + MCUX_CSSL_FP_LOOP_ITERATION(QDash_SquareMultiply, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); + + if (0u == (exponent & bitMask)) + { + /* Squaring only. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_QDash_Fup_Loop0, mcuxClMath_QDash_Fup_Loop0_LEN); + } + else + { + /* Squaring and multiplication. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_QDash_Fup_Loop1, mcuxClMath_QDash_Fup_Loop1_LEN); + } + + bitMask >>= 1; + } while(0u != bitMask); /* Assume exponent != 0, there are at least 3 squarings. */ + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t leadingZeroExponent = (uint32_t) mcuxClMath_CountLeadingZerosWord((uint32_t) length) - 3u); + MCUX_CSSL_FP_COUNTER_STMT(uint32_t lterationsSquareMultiply = ((sizeof(uint32_t)) * 8u) - leadingZeroExponent - 1u); /* "-1" to skip the first nonzero bit. */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_QDash, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_LOOP_ITERATIONS(QDash_SquareMultiply, lterationsSquareMultiply)); +} + + +/** + * [DESIGN] + * This function calculates QSquared = Q^2 mod n, where Q = 256^(PS1 OPLEN) mod n, + * by calling the above mcuxClMath_QDash. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_QSquared) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_QSquared(uint32_t iQSqr_iNShifted_iN_iT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_QSquared, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash)); + + uint16_t len = MCUXCLPKC_PS1_GETOPLEN(); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_QDash(iQSqr_iNShifted_iN_iT, len)); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_QSquared); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash_FUP.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash_FUP.c new file mode 100644 index 000000000..246c0f2a6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_QDash_FUP.c @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_QDash_FUP.c + * @brief mcuxClMath: FUP programs used in mcuxClMath_QDash + */ + + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Init[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x21u,0xccu,0x16u,0x07u},{0x00u,0x09u,0x00u,0x00u,0x01u,0x00u},{0x80u,0x21u,0x02u,0x00u,0x00u,0x03u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop0[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xddu,0x52u,0x99u,0x5du},{0x80u,0x00u,0x03u,0x03u,0x01u,0x00u},{0x00u,0x1eu,0x00u,0x00u,0x04u,0x03u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_QDash_Fup_Loop1[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xa1u,0xc5u,0x15u,0x04u},{0x80u,0x00u,0x03u,0x03u,0x01u,0x00u},{0x80u,0x21u,0x02u,0x00u,0x00u,0x03u}}; + + + +/* ps1Len = ( -, operandSize) */ + + +/** + * [DESIGN] Square only + * CAUTION: + * According to PKC specification, when calculating MM (Modular Multiplication) + * with OPLEN = MCUXCLPKC_WORDSIZE, PKC will read the least significant PKC word + * of the result buffer in PKC workarea (T[0] in this FUP program) before writing + * any intermediate result to it. This behavior will not affect the correctness, + * but the PKC word T[0] needs to be initialized before this FUP program, + * if the platform requires explicit memory initialization. + * + * ps, T[0] has been initialized when calling the FUP program above (QDash_Fup_init). + */ +/* ps1Len = (operandSize, operandSize) */ + + +/** + * [DESIGN] Square and multiply + * CAUTION: see the above FUP program, mcuxClMath_QDash_Fup_Loop0. + */ +/* ps1Len = (operandSize, operandSize) */ diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ReduceModEven.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ReduceModEven.c new file mode 100644 index 000000000..b7d72abd9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_ReduceModEven.c @@ -0,0 +1,261 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_ReduceModEven.c + * @brief mcuxClMath: implementation of the function mcuxClMath_ReduceModEven + */ + + +#include +#include +#include + +#include +#include +#include + +#include + + +#define REDUCEMODEVEN_T0 0u +#define REDUCEMODEVEN_N 1u +#define REDUCEMODEVEN_X 2u /* offsetX and offsetR shall be in the same CPU word. */ +#define REDUCEMODEVEN_R 3u +#define REDUCEMODEVEN_T3 4u +#define REDUCEMODEVEN_T2 5u +#define REDUCEMODEVEN_T1 6u +#define REDUCEMODEVEN_T0H 7u +#define REDUCEMODEVEN_XH 8u /* offsetXH and offsetRH shall be in the same CPU word. */ +#define REDUCEMODEVEN_RH 9u +#define REDUCEMODEVEN_UPTRT_SIZE 10u + + +/** + * [DESIGN] + * Modular reduction with even modulus, r = x mod n, where n = n' * 2^k (n' is odd and nonzero). + * Assume xH = x / 2^k, xL = x mod 2^k + * rL = r mod 2^k = (x mod n) mod 2^k = x mod 2^k = xL + * (r - rL) = (r - xL) \equiv (x - xL) mod (n'*2^k) + * rH = ((r - rL) / 2^k) \equiv ((x - xL) / 2^k) mod (n' * 2^k) + * rH = xH mod n' + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ReduceModEven) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ReduceModEven(uint32_t iR_iX_iN_iT0, uint32_t iT1_iT2_iT3) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ReduceModEven); + + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + + /* Assume both OPLEN and MCLEN are initialized properly (must be a multiple of MCUXCLPKC_WORDSIZE). */ + uint32_t pkcByteLenN = MCUXCLPKC_PS1_UNPACK_OPLEN(backupPs1LenReg); + uint32_t pkcByteLenX = MCUXCLPKC_PS1_UNPACK_MCLEN(backupPs1LenReg); + + /* Prepare local UPTRT. */ + uint32_t pOperands32[(REDUCEMODEVEN_UPTRT_SIZE + 1u) / 2u]; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - Cast to 16-bit pointer table"); + uint16_t *pOperands = (uint16_t *) pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES(); + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iR_iX_iN_iT0, iT1_iT2_iT3, pOperands, 7u, &backupPtrUptrt)); + pOperands[REDUCEMODEVEN_T0H] = pOperands[REDUCEMODEVEN_T0] + MCUXCLPKC_WORDSIZE; + + + /****************************************************************/ + /* Step 1: count k = trailing zeros of n */ + /****************************************************************/ + + MCUXCLPKC_WAITFORFINISH(); /* Avoid any ongoing computation of N. */ + MCUX_CSSL_FP_FUNCTION_CALL(numTrailZeroBits, mcuxClMath_TrailingZeros(REDUCEMODEVEN_N)); + + + /****************************************************************/ + /* Step 2: T0H = n >> k = n', and T0L = NDash(T0H) */ + /* a. OPLEN = pkcLenN */ + /* b. operand T0 is of size, (pkcLenN + pkcWordSize) */ + /* T0L is the least significant pkcWord (for NDash), and */ + /* T0H is the higher significant pkcWord(s), size = pkcLenN */ + /* c. use T3 as temp when calculating NDash, size = 2 pkcWords */ + /****************************************************************/ + + // (optional) we might create a new function to support both shift left and right, and use it also in mcuxClMath_ShiftModulus. + // In ECC, n-1 (the curve order - 1) is usually with only few trailing zeros, we don't really need a highly optimized right shifting here. + + uint32_t shiftAmountThisIteration = (numTrailZeroBits >= (MCUXCLPKC_WORDSIZE * 8u)) ? + ((MCUXCLPKC_WORDSIZE * 8u) - 1u) : numTrailZeroBits; + uint32_t shiftAmountRemaining = numTrailZeroBits - shiftAmountThisIteration; + MCUXCLPKC_FP_CALC_OP1_SHR(REDUCEMODEVEN_T0H, REDUCEMODEVEN_N, shiftAmountThisIteration); + + MCUX_CSSL_FP_LOOP_DECL(RightShift); + while (0u != shiftAmountRemaining) + { + MCUX_CSSL_FP_LOOP_ITERATION(RightShift, + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR ); + + shiftAmountThisIteration = (shiftAmountRemaining >= (MCUXCLPKC_WORDSIZE * 8u)) ? + ((MCUXCLPKC_WORDSIZE * 8u) - 1u) : shiftAmountRemaining; + shiftAmountRemaining -= shiftAmountThisIteration; + MCUXCLPKC_FP_CALC_OP1_SHR(REDUCEMODEVEN_T0H, REDUCEMODEVEN_T0H, shiftAmountThisIteration); + } + + MCUXCLMATH_FP_NDASH(REDUCEMODEVEN_T0H, /* iN */ + REDUCEMODEVEN_T3); /* iT */ + + + /****************************************************************/ + /* Step 3: T1 = ShiftModulus(T0H) */ + /* a. OPLEN = pkcLenN' = pkcSize(bitLenN - k) <= pkcLenN */ + /* b. result T1 is of size, pkcLenN' */ + /****************************************************************/ + + /* Number of trailing zero pkcWord(s). */ + /* **Caution** This length might be 0 if the trailing zeros are less than a PKC word. */ + uint32_t pkcByteLenTZWords = numTrailZeroBits / (MCUXCLPKC_WORDSIZE * 8u) * MCUXCLPKC_WORDSIZE; + /* pkcLenN' */ + uint32_t pkcByteLenNPrime = pkcByteLenN - pkcByteLenTZWords; + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenNPrime, pkcByteLenNPrime); /* Also set MCLEN for the next step. */ + MCUXCLMATH_FP_SHIFTMODULUS(REDUCEMODEVEN_T1, /* iNShifted */ + REDUCEMODEVEN_T0H); /* iN */ + + + /****************************************************************/ + /* Step 4: T2 = QDash(T0H), QDash_len = pkcSize(bitLenX - k) */ + /* a. OPLEN = MCLEN = pkcLenN' = pkcSize(bitLenN - k) */ + /* b. result T2 is of size, pkcLenN' */ + /* c. use T3 as temp, size = (pkcLenN + pkcWordSize) */ + /****************************************************************/ + + MCUXCLMATH_FP_QDASH(REDUCEMODEVEN_T2, /* iQDash */ + REDUCEMODEVEN_T1, /* iNShifted */ + REDUCEMODEVEN_T0H, /* iN */ + REDUCEMODEVEN_T3, /* iT */ + (uint16_t) (pkcByteLenX - pkcByteLenTZWords)); /* QDash_len */ + + + /****************************************************************/ + /* Step 5: X = X << ((-k) mod (8*pkcWordSize)), i.e., */ + /* shift XH to be aligned with PKC word */ + /* a. clean extra pkcWord (at offsetX + pkcLenN) before shift */ + /* b. OPLEN = pkcLenX + pkcWordSize */ + /* c. XL is the least significant pkcWord(s), size = pkcSize(k) */ + /* XH is the higher significant pkcWord(s), */ + /* size = pkcSize(bitLenX - k) */ + /****************************************************************/ + + uint32_t shiftAmountNeg = (0u - numTrailZeroBits) & (((uint32_t) MCUXCLPKC_WORDSIZE * 8u) - 1u); + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(0, MCUXCLPKC_WORDSIZE); + + /* Clean the extra pkcWord. */ + MCUXCLPKC_PS2_SETMODE(MCUXCLPKC_OP_CONST); /* offsetX and offsetY are not used. */ + MCUXCLPKC_PS2_SETZR(0u, pOperands[REDUCEMODEVEN_X] + pkcByteLenX); + MCUXCLPKC_PS2_START_L0(); + + MCUXCLPKC_PS1_SETLENGTH(0, pkcByteLenX + MCUXCLPKC_WORDSIZE); + MCUXCLPKC_FP_CALC_OP1_SHL(REDUCEMODEVEN_X, REDUCEMODEVEN_X, shiftAmountNeg); + + + /****************************************************************/ + /* Step 6: T3 = MMul(XH, T2, T0H) = xH * 256^pkcLenN' mod n' */ + /* a. MCLEN = pkcLenXH = pkcSize(bitLenX - k), OPLEN = pkcLenN' */ + /****************************************************************/ + + /* pkcLenXH. */ + uint32_t pkcByteLenXH = pkcByteLenX - pkcByteLenTZWords; + /* pkcLenXL = pkcSize(k) = pkcByteLenTZWords, if length of trailing zeros are exactly a multiple of PKC word; or */ + /* = (pkcByteLenTZWords + pkcWordSize), otherwise. **Caution** */ + uint32_t pkcByteLenXL = (numTrailZeroBits + (MCUXCLPKC_WORDSIZE * 8u) - 1u) / (MCUXCLPKC_WORDSIZE * 8u) * MCUXCLPKC_WORDSIZE; + + /* Set offsetXH = offsetX + pkcSize(k) and offsetRH = offsetR + pkcSize(k). */ + pOperands32[REDUCEMODEVEN_XH / 2u] = pOperands32[REDUCEMODEVEN_X / 2u] + ((pkcByteLenXL << 16) + pkcByteLenXL); + +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS2 after submitting a PS1 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS2_SETLENGTH(pkcByteLenXH, pkcByteLenNPrime); + MCUXCLPKC_FP_CALC_MC2_MM(REDUCEMODEVEN_T3, REDUCEMODEVEN_XH, REDUCEMODEVEN_T2, REDUCEMODEVEN_T0H); + + + /****************************************************************/ + /* Step 7: R = MRed(T3, T0H) \equiv xH (mod n') <= n' */ + /* a. MCLEN = OPLEN = pkcLenN' */ + /****************************************************************/ + +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS1 after submitting a PS2 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenNPrime, pkcByteLenNPrime); + /* **Caution** Result space = pkcLenN' + pkcWordSize <= pkcLenN + pkcWordSize. */ + MCUXCLPKC_FP_CALC_MC1_MR(REDUCEMODEVEN_R, REDUCEMODEVEN_T3, REDUCEMODEVEN_T0H); + + + /****************************************************************/ + /* Step 8: RH = MSub(R, T0H, T0H) = (xH mod n') < n' */ + /* a. OPLEN = pkcLenN' */ + /* b. RH is at offset pkcSize(k) from R */ + /****************************************************************/ + + MCUXCLPKC_FP_CALC_MC1_MS(REDUCEMODEVEN_RH, REDUCEMODEVEN_R, REDUCEMODEVEN_T0H, REDUCEMODEVEN_T0H); + + + /****************************************************************/ + /* Step 9: copy XL to RL */ + /* a. OPLEN = pkcLenXL = pkcSize(k) >= pkcWordSize */ + /* if k = 0 (n is odd), OPLEN = 0 will trigger PKC alarm */ + /****************************************************************/ + +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS2 after submitting a PS1 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS2_SETLENGTH(0u, pkcByteLenXL); + MCUXCLPKC_FP_CALC_OP2_OR_CONST(REDUCEMODEVEN_R, REDUCEMODEVEN_X, 0u); + + + /****************************************************************/ + /* Step 10: R = R >> ((-k) mod (8*pkcWordSize)) */ + /* a. OPLEN = pkcSize(k) + pkcSize(bitLenN - k) */ + /* = pkcLenN or (pkcLenN + pkcWordSize) */ + /****************************************************************/ + +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS1 after submitting a PS2 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS1_SETLENGTH(0u, pkcByteLenNPrime + pkcByteLenXL); + MCUXCLPKC_FP_CALC_OP1_SHR(REDUCEMODEVEN_R, REDUCEMODEVEN_R, shiftAmountNeg); + + + /****************************************************************/ + /* Step 11: X = X >> ((-k) mod (8*pkcWordSize)) */ + /* a. OPLEN = pkcLenX + pkcWordSize */ + /****************************************************************/ + +// MCUXCLPKC_WAITFORREADY(); <== not necessary when setting PS2 after submitting a PS1 computation via mcuxClPkc_Calc(...) + MCUXCLPKC_PS2_SETLENGTH(0u, pkcByteLenX + MCUXCLPKC_WORDSIZE); + MCUXCLPKC_FP_CALC_OP2_SHR(REDUCEMODEVEN_X, REDUCEMODEVEN_X, shiftAmountNeg); + + /* Restore pUptrt and ps1 OPLEN/MCLEN. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ReduceModEven, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + /* S01 */ MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_TrailingZeros), + /* S02 */ MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_LOOP_ITERATIONS(RightShift, (numTrailZeroBits - 1u) / ((MCUXCLPKC_WORDSIZE * 8u) - 1u)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + /* S03 */ MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + /* S04 */ MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), + /* S05 */ MCUXCLPKC_FP_CALLED_CALC_OP1_SHL, + /* S06 */ MCUXCLPKC_FP_CALLED_CALC_MC2_MM, + /* S07 */ MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + /* S08 */ MCUXCLPKC_FP_CALLED_CALC_MC1_MS, + /* S09 */ MCUXCLPKC_FP_CALLED_CALC_OP2_OR_CONST, + /* S10 */ MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + /* S11 */ MCUXCLPKC_FP_CALLED_CALC_OP2_SHR ); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp.c new file mode 100644 index 000000000..5a3bd058a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp.c @@ -0,0 +1,441 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_SecModExp.c + * @brief mcuxClMath: secure modular exponentiation + */ + + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +/** + * [DESIGN] + * Internal square-and-multiply-always modular exponentiation function, which supports: + * (1) when numSqr = 1, double-exponentiation (Shamir's trick), m1^e1 * m2^e2. + * m1 and m2 need to be stored in PKC operands M1 and M2, and + * exponent e1 and e2 should be interleaved. + * (2) when numSqr = 2, fixed 2-bit window algorithm, x^e. + * x and x^2 need to be stored in PKC operands M1 and M2. + * + * CAUTION: expByteLength should be a multiple of CPU word length. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMath_SecModExp_SqrMultAws) +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_SecModExp_SqrMultAws) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) +mcuxClMath_SecModExp_SqrMultAws(mcuxClSession_Handle_t session, const uint32_t *pExp, uint32_t expByteLength, uint32_t numSqr, uint32_t secOption) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_SecModExp_SqrMultAws); + + /* Prepare m3 = m1 * m2 mod n, m0 = 1, a0 = 1. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_Aws_Init, + mcuxClMath_Fup_Aws_Init_LEN); + + const uint16_t *pOperands = MCUXCLPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - UPTR table is 32-bit aligned in SecModExp") + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP36_C, "UPTR table is 32-bit aligned in SecModExp") + const uint32_t *pOperands32 = (const uint32_t *) pOperands; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP36_C) + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /* A0 and A1 will be the intermediate result A(t) and temp buffer A(1-t). */ + /* In the beginning, A0 is the intermediate result, i.e., t = 0. */ + uint16_t ofsN = pOperands[SECMODEXP_N]; + const uint32_t ofsA1_ofsA0 = pOperands32[SECMODEXP_A0 / 2u]; /* hi16 = ofsA1, lo16 = ofsA0. */ + uint32_t ofsAs = ofsA1_ofsA0; + + /* Prepare modular multiplications in the loop */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETMODE(MCUXCLPKC_MC_MM); + + MCUX_CSSL_FP_LOOP_DECL(SquMulLoop); + MCUX_CSSL_FP_LOOP_DECL(SquMulLoop_LoadExpWord); + MCUX_CSSL_FP_LOOP_DECL(SquMulLoop_Square); + MCUX_CSSL_FP_LOOP_DECL(SquMulLoop_OperandRerandomization); + + /* Balance FP in advance to avoid keeping expByteLength in reg/stack. */ + MCUX_CSSL_FP_EXPECT( + MCUX_CSSL_FP_LOOP_ITERATIONS(SquMulLoop, expByteLength * 4u), + MCUX_CSSL_FP_LOOP_ITERATIONS(SquMulLoop_LoadExpWord, expByteLength / 4u), + MCUX_CSSL_FP_LOOP_ITERATIONS(SquMulLoop_Square, expByteLength * 4u * numSqr), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND != secOption), MCUX_CSSL_FP_LOOP_ITERATIONS(SquMulLoop_OperandRerandomization, 32u))); + + /* Assume expByteLength is a multiple of CPU word size (4), otherwise, some higher bits of exponent will be ignored. */ + uint32_t expWord0 = 0u; + uint32_t expWord1 = 0u; + + uint32_t rnd64_0; + uint32_t rnd64_1; + + uint32_t ofsM3_ofsM1 = pOperands32[SECMODEXP_M1 / 2u]; /* (offsetM3, offsetM1) = (M3H, M3L, M1H, M1L) */ + uint32_t ofsM2_ofsM0 = pOperands32[SECMODEXP_M0 / 2u]; /* (offsetM2, offsetM0) = (M2H, M2L, M0H, M0L) */ + /* Prepare (M3H, M2H, M1H, M0H), where e.g., M3H is the higher 8 bits of the 16-bit offset M3. */ + uint32_t ofsMsHi8 = (ofsM3_ofsM1 & 0xFF00FF00u) | ((ofsM2_ofsM0 & 0xFF00FF00u) >> 8u); + /* Prepare (M3L, M2L, M1L, M0L), where e.g., M3L is the lower 8 bits of the 16-bit offset M3. */ + uint32_t ofsMsLo8 = ((ofsM3_ofsM1 & 0x00FF00FFu) << 8u) | (ofsM2_ofsM0 & 0x00FF00FFu); + + /* Rotate left 4-bit, such that the rotation amount in SecureOffsetSelect is always nonzero (4/12/20/28). */ + ofsMsHi8 = (ofsMsHi8 << 4u) | (ofsMsHi8 >> 28u); + ofsMsLo8 = (ofsMsLo8 << 4u) | (ofsMsLo8 >> 28u); + + + /* Prepare pointer to the random buffers (R0 || R1 || R2 || R2H), which will be used for the operand re-randomization. */ + uint32_t *p32R0 = MCUXCLPKC_OFFSET2PTRWORD(pOperands[SECMODEXP_R0]); /* operand R0 shall be PKC word aligned. */ + + /* Scan from most to least significant bits of exponent, */ + /* which is stored in little-endian in CPU-word aligned buffer. */ + uint32_t bitLenExp = expByteLength * 8u; + int32_t bitIndex = (int32_t) bitLenExp - 2; + do + { + MCUX_CSSL_FP_LOOP_ITERATION(SquMulLoop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + + /* Load next CPU word of exponent. */ + if (0x1Eu == ((uint32_t) bitIndex & 0x1Fu)) + { + MCUX_CSSL_FP_LOOP_ITERATION(SquMulLoop_LoadExpWord, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + + /* Read one CPU word of exponent and mask it. */ + uint32_t randomWordStack; + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate1, mcuxClRandom_ncGenerate(session, (uint8_t *) &randomWordStack, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp_SqrMultAws, MCUXCLMATH_STATUS_ERROR); + } + expWord1 = randomWordStack; /* avoid compiler writing randomWord back to stack */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "bitIndex < 8*expByteLength, and expByteLength is bounded by memory size (and smaller than 2^16).") + expWord0 = pExp[(uint32_t) bitIndex / 32u] ^ expWord1; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + /* Re-randomize base operands, for the first 64 bits of exponent processed */ + /* TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption */ + if ((((int32_t) bitLenExp - 64) <= bitIndex) && (MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND != secOption)) + { + MCUX_CSSL_FP_LOOP_ITERATION(SquMulLoop_OperandRerandomization, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); + + /* Generate random numbers in R0, R1, R2 and R2H. + * In order to optimize calls to the PRNG function, one single random number, of 128 bits, is generated over R0 and R1, and split with the CPU across the four buffers. + * In order to avoid overflows when adding in-place multiples of the modulus over 2*32=2^6 iterations in total, 26-bit random numbers are used. + * The upper words of buffers R2 and R2H have already been cleared.*/ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate2, mcuxClRandom_ncGenerate(session, (uint8_t *) p32R0, 16u)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp_SqrMultAws, MCUXCLMATH_STATUS_ERROR); + } + + p32R0[4u] = p32R0[1u] >> 6u; /* Copy random from R0[63:32] to R2, and keep only 26 bits */ + p32R0[6u] = p32R0[3u] >> 6u; /* Copy random from R1[63:32] to R2H, and keep only 26 bits */ + p32R0[0u] >>= 6u; /* Clear R0[63:26] */ + p32R0[1u] = 0x00000000u; + p32R0[2u] >>= 6u; /* Clear R1[63:26] */ + p32R0[3u] = 0x00000000u; + + /* Add random multiples of the modulus, in-place, to the base operands M0, M1, M2 and M3. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_Aws_Rerand, + mcuxClMath_Fup_Aws_Rerand_LEN); + } + + uint32_t iterSqr = numSqr; + do + { + MCUX_CSSL_FP_LOOP_ITERATION(SquMulLoop_Square); + + /* Swap intermediate result A(t) and temp buffer A(1-t), i.e., let t := 1-t. */ + ofsAs = (ofsAs << 16u) | (ofsAs >> 16u); /* hi16 = ofsA(1-t), lo16 = ofsA(t). */ + + /* Calculate A(t) = A(1-t) * A(1-t) mod N. */ + uint32_t Sqr_ofsY_ofsX = (ofsAs & 0xFFFF0000u) | (ofsAs >> 16u); + uint32_t Sqr_ofsR_ofsZ = (ofsAs << 16u) | ofsN; + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETXY_REG(Sqr_ofsY_ofsX); + MCUXCLPKC_PS1_SETZR_REG(Sqr_ofsR_ofsZ); + MCUXCLPKC_PS1_START_L1(); + + iterSqr--; + } while (0u < iterSqr); + + /* Generate a fresh random word for secure offset selection.*/ + uint32_t rndWordStack; + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate3, mcuxClRandom_ncGenerate(session, (uint8_t *) &rndWordStack, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate3) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp_SqrMultAws, MCUXCLMATH_STATUS_ERROR); + } + uint32_t rndWord = rndWordStack; /* avoid compiler writing rndWord back to stack */ + + /* Modular Multiplication: X * Y mod Z =: R, */ + /* for t = 0 or 1, M[i] * A(1-t) mod N =: A(t). */ + + /* Securely select ofsX, set ofsY_ofsX, and also swap A0 and A1 (i.e., let t := 1-t). */ + uint32_t ofsY_ofsX; + uint32_t maskVal; + MCUXCLMATH_SECMODEXP_SECUREOFFSETSELECT(expWord0, expWord1, ofsAs, ofsY_ofsX, rndWord, (uint32_t)bitIndex, ofsMsHi8, ofsMsLo8, rnd64_0, rnd64_1, maskVal); + uint32_t ofsR_ofsZ = (ofsAs << 16u) | ofsN; + MCUXCLPKC_WAITFORREADY(); + MCUXCLMATH_SECMODEXP_WRITEOFFSET(ofsY_ofsX,maskVal); + MCUXCLPKC_PS1_SETZR_REG(ofsR_ofsZ); + MCUXCLPKC_PS1_START_L1(); + + bitIndex -= 2; + } while (0 <= bitIndex); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp_SqrMultAws, MCUXCLMATH_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_SecModExp) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMath_Status_t) mcuxClMath_SecModExp( + mcuxClSession_Handle_t session, const uint8_t *pExp, uint32_t *pExpTemp, uint32_t expByteLength, uint32_t iT3_iX_iT2_iT1, uint32_t iN_iTE_iT0_iR, uint32_t secOption) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_SecModExp); + + /* Create local UPTR table. */ + uint32_t pOperands32[(SECMODEXP_UPTRT_SIZE + 1u) / 2u]; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("MISRA Ex. 9 - Rule 11.3 - Cast to 16-bit pointer table") + uint16_t *pOperands = (uint16_t *) pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + const uint16_t *backupPtrUptrt; + /* Mapping to internal indices: M3 M1 M2 M0 N TE A1 A0 */ + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iT3_iX_iT2_iT1, iN_iTE_iT0_iR, pOperands, 8u, &backupPtrUptrt)); + + uint32_t ps1LenBackup = MCUXCLPKC_PS1_GETLENGTH_REG(); + + /* Import exponent (big-endian to little-endian). */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_INT30_C, "pkcLenExpPlus in range [expByteLength+1, expByteLength+MCUXCLPKC_WORDSIZE].") + uint32_t pkcLenExpPlus = MCUXCLPKC_ROUNDUP_SIZE(expByteLength + 1u); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_INT30_C) + MCUXCLPKC_PS1_SETLENGTH_REG(pkcLenExpPlus); /* MCLEN on higher 16 bits is not used. */ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImport, mcuxClPkc_SecureImportBigEndianToPkc(session, MCUXCLPKC_PACKARGS2(SECMODEXP_A0, SECMODEXP_A1), pExp, expByteLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecImport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + + /******************************************************/ + /* Euclidean exponent split: exp = b * q + r, */ + /* where b is 64-bit random (MSb and LSb set) */ + /******************************************************/ + + /* Generate random expB and blind exponent, expA = exp + expB. */ + uint8_t *pA1 = MCUXCLPKC_OFFSET2PTR(pOperands[SECMODEXP_A1]); + /* A1 = expB < (256^pkcLenExpPlus)/2. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pkcLenExpPlus in range [expByteLength+1, expByteLength+MCUXCLPKC_WORDSIZE].") + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate1, mcuxClRandom_ncGenerate(session, pA1, pkcLenExpPlus)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + pA1[pkcLenExpPlus - 1u] &= 0x7Fu; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + /* A0 = expA = exp + expB < 256^pkcLenExpPlus. */ + MCUXCLPKC_FP_CALC_OP1_ADD(SECMODEXP_A0, SECMODEXP_A0, SECMODEXP_A1); + + /* Partition buffer TE to "TE || NDASH || R0 || R1 || (R2L, R2H)". */ + uint32_t offsetTE = (uint32_t) pOperands[SECMODEXP_TE]; + uint32_t offsetNDASH = offsetTE + MCUXCLPKC_WORDSIZE; + uint32_t offsetR0 = offsetNDASH + MCUXCLPKC_WORDSIZE; + uint32_t offsetR1 = offsetR0 + MCUXCLPKC_WORDSIZE; + uint32_t offsetR2 = offsetR1 + MCUXCLPKC_WORDSIZE; + uint32_t offsetR2H = offsetR2 + MCUXCLPKC_WORDSIZE; + pOperands32[SECMODEXP_NDASH / 2u] = (offsetR0 << 16u) + offsetNDASH; + pOperands32[SECMODEXP_R1 / 2u] = (offsetR2 << 16u) + offsetR1; + pOperands32[SECMODEXP_R2H / 2u] = offsetR2H; /* Also initialize SECMODEXP_ZERO */ + pOperands[SECMODEXP_ONE] = 0x0001u; + + /* Generate a 64-bit random b with both MSbit and LSbit set. */ + uint32_t *p32R0 = MCUXCLPKC_OFFSET2PTRWORD((uint16_t) offsetR0); /* opernad R0 shall be PKC word aligned. */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate2, mcuxClRandom_ncGenerate(session, (uint8_t *) p32R0, 8u)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + p32R0[0] |= 0x00000001u; + p32R0[1] |= 0x80000000u; + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(MCUXCLPKC_WORDSIZE, MCUXCLPKC_WORDSIZE); + + /* Calculate NDash and QDash of b. + * As the MSB of b is set, shifting the modulus is not necessary. */ + MCUXCLMATH_FP_NDASH(SECMODEXP_R0, SECMODEXP_M2); + MCUXCLMATH_FP_QDASH(SECMODEXP_M0, SECMODEXP_R0, SECMODEXP_R0, SECMODEXP_M3, (uint16_t) pkcLenExpPlus); + +// MCUXCLPKC_WAITFORREADY(); <== there is WAITFORREADY in QDASH + MCUXCLPKC_PS2_SETLENGTH(pkcLenExpPlus, MCUXCLPKC_WORDSIZE); + + /* M2 = expB mod b, R1 = r = exp mod b. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_EuclideanSplit_1, + mcuxClMath_Fup_EuclideanSplit_1_LEN); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH_REG(pkcLenExpPlus); /* MCLEN on higher 16 bits is not used. */ + + /* A0 = -(expA - (expB mod b) - ((expA - expB) mod b)); */ + /* A1 = -(expB - (expB mod b)). */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_EuclideanSplit_2, + mcuxClMath_Fup_EuclideanSplit_2_LEN); + + MCUX_CSSL_FP_LOOP_DECL(ExactDivideLoop); + + /* Calculate exact division: */ + /* A0 = (expA - (expB mod b) - ((expA - expB) mod b)) / b; */ + /* A1 = (expB - (expB mod b)) / b. */ + uint32_t ofsV1_ofsV0 = pOperands32[SECMODEXP_A0 / 2u]; + uint32_t remainLength = pkcLenExpPlus; + do + { + MCUX_CSSL_FP_LOOP_ITERATION(ExactDivideLoop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) ); + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH_REG(remainLength); /* MCLEN on higher 16 bits is not used. */ + pOperands32[SECMODEXP_V0 / 2u] = ofsV1_ofsV0; + + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_ExactDivideLoop, + mcuxClMath_Fup_ExactDivideLoop_LEN); + + ofsV1_ofsV0 += (((uint32_t) MCUXCLPKC_WORDSIZE << 16u) + MCUXCLPKC_WORDSIZE); + remainLength -= MCUXCLPKC_WORDSIZE; + } while(0u != remainLength); + + /* Set PS2_LEN = pkcLenExpPlus to calculate q */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH_REG(pkcLenExpPlus); /* MCLEN on higher 16 bits is not used. */ + + /* FUP program: + * 1) A0 = q = A0 - A1 = ((expA - expB) - ((expA - expB) mod b)) / b = (exp - (exp mod b)) / b. + * 2) Interleave R0 = b and R1 = r, into (TE || NDASH). */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_CalcQAndInterleave, + mcuxClMath_Fup_CalcQAndInterleave_LEN); + + /* Export A0 = q. */ + const uint8_t *pA0 = MCUXCLPKC_OFFSET2PTR(pOperands[SECMODEXP_A0]); + uint32_t wordLenExp = (expByteLength + 3u) & 0xFFFFFFFCu; + MCUXCLPKC_WAITFORFINISH(); + MCUXCLMEMORY_FP_MEMORY_COPY((uint8_t *) pExpTemp, pA0, wordLenExp); + + + /* Calculate QSquared, to prepare for the upcoming calculation of M0 = 1 in MR, M0 < N */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH_REG(ps1LenBackup); + MCUXCLMATH_FP_SHIFTMODULUS(SECMODEXP_A0, SECMODEXP_N); + MCUXCLMATH_FP_QSQUARED(SECMODEXP_A1, SECMODEXP_A0, SECMODEXP_N, SECMODEXP_M3); + + /* Prepare M2 = m^2. + * This operation is randomized, by adding a random 16-bit multiple of the modulus to m before squaring: M2 = m + (r16 * N). */ + uint8_t *pR1 = MCUXCLPKC_OFFSET2PTR((uint16_t) offsetR1); + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate3, mcuxClRandom_ncGenerate(session, pR1, 4u)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate3) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + /* Clear upper word and process lower word of R1 */ + p32R0[3u] = 0x00000000u; + if(MCUXCLMATH_SECMODEXP_OPTION_DIS_RERAND == secOption) + { + /* TODO CLNS-7824: analyze how to use the SecModExp in RsaKg MillerRabinTest, and remove secOption to always re-randomize */ + p32R0[2u] = 0x00000000u; + } + else + { + p32R0[2u] >>= 16u; + } + + /* Prepare base numbers for the first exponentiation: + * 1) Prepare M2 = m^2. + * 2) Prepare M0 = 1 in MR, M0 < N. */ + MCUXCLPKC_FP_CALCFUP(mcuxClMath_Fup_PrepareFirstExp, + mcuxClMath_Fup_PrepareFirstExp_LEN); + + /* Clear upper words of R2 and R2H to prepare operand re-randomization inside mcuxClMath_SecModExp_SqrMultAws. */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); + p32R0[5u] = 0x00000000u; /* Clear upper word of R2 */ + p32R0[7u] = 0x00000000u; /* Clear upper word of R2H */ + + /* Calculate 2-bit window exponentiation, A0 = m0 = m^q. */ + MCUX_CSSL_FP_FUNCTION_CALL(retSecModExp0, mcuxClMath_SecModExp_SqrMultAws(session, pExpTemp, wordLenExp, 2u, secOption)); + if (MCUXCLMATH_STATUS_OK != retSecModExp0) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + + /* Calculate double exponentiation, A0 = result = m^r * m0^b, with interleaved r and b. */ + MCUXCLPKC_FP_CALC_OP1_OR_CONST(SECMODEXP_M2, SECMODEXP_A0, 0u); + const uint32_t *p32TE = MCUXCLPKC_OFFSET2PTRWORD(pOperands[SECMODEXP_TE]); /* operand TE shall be PKC word aligned. */ + MCUX_CSSL_FP_FUNCTION_CALL(retSecModExp1, mcuxClMath_SecModExp_SqrMultAws(session, p32TE, 16u, 1u, secOption)); + if (MCUXCLMATH_STATUS_OK != retSecModExp1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_ERROR); + } + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + /* Clear the local UPTR table on stack. */ + for (uint32_t i = 0u; i < ((SECMODEXP_UPTRT_SIZE + 1u) / 2u); i++) + { + pOperands32[i] = 0u; + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_SecModExp, MCUXCLMATH_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), + /* Euclidean exponent splitting */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_LOOP_ITERATIONS(ExactDivideLoop, MCUXCLPKC_ROUNDUP_SIZE(expByteLength + 1u) / MCUXCLPKC_WORDSIZE), + /* Calculate q, interleave b and r, and export q */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + /* Exponentiation 1 */ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp_SqrMultAws), + /* Exponentiation 2 */ + MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp_SqrMultAws) ); +} diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp_FUP.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp_FUP.c new file mode 100644 index 000000000..362a13ec1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_SecModExp_FUP.c @@ -0,0 +1,137 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_SecModExp_FUP.c + * @brief mcuxClMath: FUP programs of secure modular exponentiation + */ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Init[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xb9u,0xa5u,0xecu,0xd4u},{0x80u,0x00u,0x02u,0x01u,0x07u,0x03u},{0x00u,0x09u,0x00u,0x00u,0x07u,0x04u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_Aws_Rerand[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xfcu,0xe9u,0xf6u,0xcbu},{0x00u,0x22u,0x0bu,0x07u,0x00u,0x00u},{0x00u,0x22u,0x0cu,0x07u,0x02u,0x02u},{0x00u,0x22u,0x0du,0x07u,0x01u,0x01u},{0x00u,0x22u,0x0eu,0x07u,0x03u,0x03u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_CalcQAndInterleave[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x15u,0xeau,0xe7u,0x3bu},{0x40u,0x0bu,0x00u,0x04u,0x05u,0x04u},{0x00u,0x04u,0x0bu,0x0bu,0x00u,0x0du},{0x00u,0x14u,0x00u,0x0du,0x10u,0x06u},{0x00u,0x14u,0x00u,0x0eu,0x10u,0x0au},{0x00u,0x06u,0x0cu,0x0cu,0x06u,0x06u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_1[8] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xa7u,0xbdu,0x6au,0x33u},{0xc0u,0x00u,0x04u,0x00u,0x0bu,0x01u},{0xc0u,0x00u,0x05u,0x00u,0x0bu,0x03u},{0x80u,0x33u,0x01u,0x00u,0x0bu,0x00u},{0x80u,0x33u,0x03u,0x00u,0x0bu,0x01u},{0x80u,0x2au,0x0bu,0x00u,0x0bu,0x00u},{0x80u,0x2au,0x0bu,0x01u,0x0bu,0x01u},{0x80u,0x2au,0x0bu,0x00u,0x01u,0x0cu}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_EuclideanSplit_2[7] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xa7u,0x4cu,0x47u,0x09u},{0x40u,0x09u,0x00u,0x00u,0x04u,0x04u},{0x40u,0x6au,0x00u,0x04u,0x01u,0x04u},{0x40u,0x6au,0x00u,0x04u,0x0cu,0x04u},{0x40u,0x09u,0x00u,0x00u,0x05u,0x05u},{0x40u,0x6au,0x00u,0x05u,0x01u,0x05u},{0x40u,0x3eu,0x00u,0x00u,0x0fu,0x00u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_ExactDivideLoop[9] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x26u,0xbfu,0x8au,0x8fu},{0x00u,0x00u,0x08u,0x0au,0x00u,0x0du},{0x00u,0x00u,0x0du,0x0bu,0x00u,0x00u},{0x40u,0x0au,0x00u,0x08u,0x00u,0x08u},{0x00u,0x1eu,0x00u,0x0du,0x0fu,0x08u},{0x00u,0x00u,0x09u,0x0au,0x00u,0x0du},{0x00u,0x00u,0x0du,0x0bu,0x00u,0x00u},{0x40u,0x0au,0x00u,0x09u,0x00u,0x09u},{0x00u,0x1eu,0x00u,0x0du,0x0fu,0x09u}}; +const mcuxClPkc_FUPEntry_t mcuxClMath_Fup_PrepareFirstExp[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xd2u,0xcbu,0x98u,0xf8u},{0x00u,0x22u,0x0cu,0x07u,0x02u,0x04u},{0x80u,0x00u,0x04u,0x04u,0x07u,0x01u},{0x80u,0x2au,0x07u,0x01u,0x07u,0x01u},{0x80u,0x33u,0x05u,0x00u,0x07u,0x00u}}; + + +/** + * [DESIGN] + * Prepare base number M3 and Accumulator (A0) of exponentiation. + */ +/* PS1 length = ( pkcLenN, pkcLenN) */ + +/** + * [DESIGN] + * Re-randomize base numbers M0, M1, M2 and M3, by adding in-place random multiples of the modulus. + * + * PKC MACC operation is used. It takes the carry into account, to calculate: R = X0 * Y + {c, Z}. + * The carry is written into the extra PKC word on top of pkcLenN. + * Thus, even the carry flag is 1, this will affect only the extra PKC word, and will not be used + * in the following MM on length pkcLenN. + * + * In addition, in order to ensure that the result does not overflow beyond pkcLenN, and given that + * operations are done in-place in each buffer in a loop, the following should hold: + * log2(iter) + bitLenR <= leadingZeroesN, + * where leadingZeroesN is the number of leading zero bits in N, iter is the total number of re-randomization + * iterations, and bitLenR is the bit length of the random number. + * + */ +/* PS1 length = ( pkcLenN, pkcLenN) */ + +/** + * [DESIGN] + * Euclidean splitting part #1: calculate "exponent mod b" on both shares of exponent. + * + * The modular reduction is implemented based on PKC MR (Modular Reduction). + * The two shares of exponent are converted to their Montgomery representation + * modulo b (length = MCUXCLPKC_WORDSIZE) by multiplying them with M0 = QDash. + * They are converted back to their normal representation by PKC MR, and + * results are in the range [0, b]. The PKC MS (Modular Subtraction) guarantees + * the proper results in the range [0, b-1]. + * + * CAUTION: + * According to PKC specification, when calculating MM (Modular Multiplication) + * with OPLEN = MCUXCLPKC_WORDSIZE, PKC will read the least significant PKC word + * of the result buffer in PKC workarea (M2[0] and M3[0] in this FUP program) + * before writing any intermediate result to it. + * This pre-fetch will not affect the result, but caller shall ensure that + * both PKC words M2[0] and M3[0] are initialized before this FUP program, + * if the platform requires explicit memory initialization. + * + * ps, M2[0] and M3[0] have been initialized (used as temp buffer) when calculating + * NDash and QDash before this FUP program. + */ +/* PS1 length = (MCUXCLPKC_WORDSIZE, MCUXCLPKC_WORDSIZE) */ +/* PS2 length = ( pkcLenExpPlus, MCUXCLPKC_WORDSIZE) */ + +/** + * [DESIGN] + * Euclidean splitting part #2: prepare to calculate exact division: + * "(exponent - (exponent mod b)) / b", on both shares of exponent. + * + * Exact division, x/b = q, assumes the dividend x must be exactly a multiple of + * divisor b. So there is the quotient q satisfying (-x) + b*q = 0. + */ +/* PS2 length = ( -, pkcLenExpPlus) */ + +/** + * [DESIGN] + * One iteration of exact division, where the divisor b is of the size, MCUXCLPKC_WORDSIZE. + * + * The algorithm of exact division q = x/b is to find q satisfying (-x) + b*q = 0. + * Let y = -x mod 256^(pkcLenExpPlus), and y[i] and q[i] are the i-th PKC word of y and q. + * + * y + b*q[0] \equiv 0 mod Q, where Q = 256^(MCUXCLPKC_WORDSIZE). + * q[0] = y * (-b)^(-1) mod Q = y[0] * NDash mod Q. + * Assume for i > 0, y + b*q[i-1 ~ 0] \equiv 0 mod Q^i. + * Then, q[i] = ((y + b*q[i-1 ~ 0])/(Q^i)) * NDash mod Q. + * + * In this implementation, the negative dividend (-x) will be overwritten by + * quotient q word-wisely. + */ +/* PS1 length = ( -, MCUXCLPKC_WORDSIZE) */ +/* PS2 length = ( -, remainLength) */ + +/** + * [DESIGN] + * Prepare q, and interleaved b and r. + * + * First part: calculate q, using PS2. + * A0 = q = A0 - A1 = ((expA - expB) - ((expA - expB) mod b)) / b = (exp - (exp mod b)) / b + * + * Second part: interleave R0 = b and R1 = r, using PS1. + * The interleaved data is written over two consecutive PKC words in TE and NDASH. + * The result space of MAC_GF2 takes one extra PKC word and thus also overwrites R0. + * The 2-FW buffer R2 is used as temp buffer. + */ +/* PS1 length = ( -, MCUXCLPKC_WORDSIZE) */ +/* PS2 length = ( -, pkcLenExpPlus) */ + +/** + * [DESIGN] + * Prepare base numbers for the first exponentiation. + * + * First part: randomized calculation of M2 = (m + (r16 * N))^2 mod N = m^2 mod N. + * PKC MACC operation is used to calculate A0 = R1 * N + M1. + * MACC takes the carry into account, which is written into the extra PKC word on top of pkcLenN. + * This extra PKC word is not used in the following MM on length pkcLenN. + * + * Second part: prepare M0 = 1 in MR, M0 < N, with a Montgomery reduction of QSquared. + */ +/* PS1 length = ( pkcLenN, pkcLenN) */ + diff --git a/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_Utils.c b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_Utils.c new file mode 100644 index 000000000..8d2e6a19c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMath/src/mcuxClMath_Utils.c @@ -0,0 +1,181 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMath_Utils.c + * @brief mcuxClMath: implementation of Math utility functions + */ + + +#include +#include +#include + +#include + +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_InitLocalUptrt) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_InitLocalUptrt(uint32_t i3_i2_i1_i0, uint32_t i7_i6_i5_i4, uint16_t *localPtrUptrt, uint8_t noOfIndices, const uint16_t **oldPtrUptrt) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_InitLocalUptrt); + + const uint16_t *pUptrt = MCUXCLPKC_GETUPTRT(); + + uint32_t indices = i3_i2_i1_i0; + + /* Support up to 8 indices. */ + uint32_t noOfIndicesSupported = (8u < noOfIndices) ? 8u : noOfIndices; + + for (uint32_t i = 0; i < noOfIndicesSupported; i++) + { + /* Copy PKC offset to new UPTRT. */ + uint32_t index = indices & 0xFFu; + localPtrUptrt[i] = pUptrt[index]; + + if (3u == i) + { + indices = i7_i6_i5_i4; + } + else + { + indices >>= 8; + } + } + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(localPtrUptrt); + + *oldPtrUptrt = pUptrt; + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_InitLocalUptrt); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_LeadingZeros) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_LeadingZeros(uint8_t iX, uint32_t *pNumLeadingZeros) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_LeadingZeros); + + const uint16_t *pUptrt = MCUXCLPKC_GETUPTRT(); + /* Assume pUptrt[iX] is exactly a multiple of MCUXCLPKC_WORDSIZE. */ + const uint32_t *pX = MCUXCLPKC_OFFSET2PTRWORD(pUptrt[iX]); + + uint32_t len = (uint32_t) MCUXCLPKC_PS1_GETOPLEN() / (sizeof(uint32_t)); /* Assume PS1 OPLEN is exactly a multiple of MCUXCLPKC_WORDSIZE. */ + uint32_t numLeadingZeros = 0u; + + do + { + len--; + uint32_t xi = pX[len]; + if (0u != xi) + { + *pNumLeadingZeros = numLeadingZeros + mcuxClMath_CountLeadingZerosWord(xi); + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_LeadingZeros); + } + + numLeadingZeros += ((sizeof(uint32_t)) * 8u); + } while (0u < len); + + *pNumLeadingZeros = numLeadingZeros; + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_LeadingZeros); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_TrailingZeros) +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClMath_TrailingZeros(uint8_t iX) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_TrailingZeros); + + const uint16_t *pUptrt = MCUXCLPKC_GETUPTRT(); + /* Assume pUptrt[iX] is exactly a multiple of MCUXCLPKC_WORDSIZE. */ + const uint32_t *pX = MCUXCLPKC_OFFSET2PTRWORD(pUptrt[iX]); + + uint32_t opWords = (uint32_t) MCUXCLPKC_PS1_GETOPLEN() / (sizeof(uint32_t)); /* Assume PS1 OPLEN is exactly a multiple of MCUXCLPKC_WORDSIZE. */ + uint32_t index = 0u; + uint32_t numTrailingZeroes = 0u; + + do + { + uint32_t xi = pX[index]; + if (0u != xi) + { + numTrailingZeroes = (index * (sizeof(uint32_t)) * 8u) + mcuxClMath_CountTrailingZeroesWord(xi); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_TrailingZeros, numTrailingZeroes); + } + + index++; + } while (index < opWords); + + numTrailingZeroes = index * (sizeof(uint32_t)) * 8u; + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClMath_TrailingZeros, numTrailingZeroes); +} + + +/** + * [DESIGN] + * Since the max shifting amount of PKC shift operation is (8 * MCUXCLPKC_WORDSIZE - 1), + * this function prepares the shifted modulus in the following steps: + * (1) ignore zero most significant PKC word(s) (if any) of modulus (iN), and + * shift-left non-zero PKC word(s) of modulus and store result in most significant + * PKC word(s) of shifted modulus (iNShifted), such that there is + * no leading zero bit in shifted modulus; + * (2) if there is any zero most significant PKC word(s) in modulus, then clean + * the same number of least significant PKC word(s) of shifted modulus. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMath_ShiftModulus) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMath_ShiftModulus(uint16_t iNShifted_iN) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMath_ShiftModulus); + + /* Unpack indices. */ + uint8_t iN = (uint8_t) (iNShifted_iN & 0xFFu); + uint8_t iNS = (uint8_t) ((iNShifted_iN >> 8) & 0xFFu); + + /* Count the number of leading zeros of modulus n. */ + MCUXCLPKC_WAITFORFINISH(); + uint32_t leadingZeroBits; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(iN, &leadingZeroBits)); + uint32_t leadingZeroPkcWords_InBytes = leadingZeroBits / (MCUXCLPKC_WORDSIZE * 8u) * MCUXCLPKC_WORDSIZE; + + /* Set PS2 LEN, to exclude leading zero PKC word(s). */ + uint32_t ps1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_PS2_SETLENGTH_REG(ps1LenReg - leadingZeroPkcWords_InBytes); + + const uint16_t * pUptrt = MCUXCLPKC_GETUPTRT(); + uint16_t offsetN = pUptrt[iN]; + uint16_t offsetNS = pUptrt[iNS]; + + /* Copy and shift nonzero PKC word(s) of modulus. */ + uint32_t shiftAmount = leadingZeroBits & ((MCUXCLPKC_WORDSIZE * 8u) - 1u); + MCUXCLPKC_PS2_SETMODE(MCUXCLPKC_OP_SHL); + MCUXCLPKC_PS2_SETXY(0, offsetN); + MCUXCLPKC_PS2_SETZR(shiftAmount, (offsetNS + leadingZeroPkcWords_InBytes) & 0xFFFFu); + MCUXCLPKC_PS2_START_L0(); + + /* Clear least significant PKC word(s) of iNShifted, if leadingZeroBits >= a PKC word. */ + if (0u != leadingZeroPkcWords_InBytes) + { + MCUXCLPKC_WAITFORREADY(); + /* MCLEN on higher 16 bits is not used. */ + MCUXCLPKC_PS2_SETLENGTH_REG(leadingZeroPkcWords_InBytes); + MCUXCLPKC_FP_CALC_OP2_CONST(iNS, 0); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMath_ShiftModulus, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUX_CSSL_FP_CONDITIONAL_IMPL((0u != leadingZeroPkcWords_InBytes), + MCUXCLPKC_FP_CALLED_CALC_OP2_CONST)); +} diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h b/components/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h new file mode 100644 index 000000000..bd914aca5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/internal/mcuxClMemory_Copy_Internal.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Copy_Internal.h + * @brief Internal memory header for copy functions. + * This header exposes functions that enable using memory copy function. + */ + +#ifndef MCUXCLMEMORY_COPY_INTERNAL_H_ +#define MCUXCLMEMORY_COPY_INTERNAL_H_ + +#include // Exported features flags header +#include + +/** + * @ingroup mcuxClMemory_Copy + * @{ + */ + + + +/** + * @} + */ + +#endif /* MCUXCLMEMORY_COPY_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h new file mode 100644 index 000000000..0cc3fdda2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory.h @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClMemory.h + * @brief Top-level include file for the memory operations. + * + * @defgroup mcuxClMemory mcuxClMemory + * @brief Basic memory operations + * + * This component provides memory functions similar to the ones found in the C standard library. + * + * @{ + */ + +#ifndef MCUXCLMEMORY_H +#define MCUXCLMEMORY_H + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * @} + */ +#endif diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h new file mode 100644 index 000000000..9893478f4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Clear.h @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Clear.h + * @brief Memory header for clear functions. + * This header exposes functions that enable using memory clear function. + */ + + +/** + * @defgroup mcuxClMemory_Clear mcuxClMemory_Clear + * @brief This function clears a memory region. + * @ingroup mcuxClMemory + * @{ + */ + + +#ifndef MCUXCLMEMORY_CLEAR_H_ +#define MCUXCLMEMORY_CLEAR_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * Overwrites a memory buffer with null bytes. + * + * If the destination buffer is too small, i.e. if bufLength < length, + * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection). + * + * @param[out] pDst Pointer to the buffer to be cleared. + * @param[in] length size (in bytes) to be cleared. + * @param[in] bufLength buffer size (if bufLength < length, only bufLength bytes are cleared). + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_clear) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength); + + +/********************************************** + * MACROS + **********************************************/ + +/** Helper macro to call #mcuxClMemory_clear with flow protection. */ +#define MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, byteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, byteLen)) + +/** Helper macro to call #mcuxClMemory_clear with flow protection with buffer. */ +#define MCUXCLMEMORY_FP_MEMORY_CLEAR_WITH_BUFF(pTarget, byteLen, buffLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear((uint8_t *) (pTarget), byteLen, buffLen)) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMEMORY_CLEAR_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h new file mode 100644 index 000000000..3649246a8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Copy.h + * @brief Memory header for copy functions. + * This header exposes functions that enable using memory copy function. + */ + +/** + * @defgroup mcuxClMemory_Copy mcuxClMemory_Copy + * @brief This function copies a memory region from @p src to @p dst. + * @ingroup mcuxClMemory + * @{ + */ + +#ifndef MCUXCLMEMORY_COPY_H_ +#define MCUXCLMEMORY_COPY_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * Copies a memory buffer to another location. + * + * The two buffers must not overlap. + * + * If the destination buffer is too small, i.e. if bufLength < length, + * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection). + * + * @param[out] pDst pointer to the buffer to be copied to. + * @param[in] pSrc pointer to the buffer to copy. + * @param[in] length size (in bytes) to be copied. + * @param[in] bufLength buffer size (if bufLength < length, only bufLength bytes are copied). + * + */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength); + + +/********************************************** + * MACROS + **********************************************/ + +/** Helper macro to call #mcuxClMemory_copy with flow protection. */ +#define MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, byteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen)) + +/** Helper macro to call #mcuxClMemory_copy with flow protection with buffer. */ +#define MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pTarget, pSource, byteLen, buffLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, buffLen)) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMEMORY_COPY_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h new file mode 100644 index 000000000..3e3e04c7b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Copy_Reversed.h @@ -0,0 +1,74 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Copy_Reversed.h + * @brief Memory header for reversed copy functions. + * This header exposes functions that enable using memory reversed copy function. + */ + +/** + * @defgroup mcuxClMemory_Copy_Reversed mcuxClMemory_Copy_Reversed + * @brief This function copies a memory region from @p src to @p dst reversely. + * @ingroup mcuxClMemory + * @{ + */ + +#ifndef MCUXCLMEMORY_COPY_REVERSED_H_ +#define MCUXCLMEMORY_COPY_REVERSED_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * Copies a memory buffer to another location reversely. + * + * If the destination buffer is too small, i.e. if bufLength < length, + * then only bufLength bytes are copied reversely. + * + * @param[out] pDst pointer to the buffer to be copied to. + * @param[in] pSrc pointer to the buffer to copy. + * @param[in] length size (in bytes) to be copied. + * @param[in] bufLength buffer size (if bufLength < length, only bufLength bytes are copied reversely). + * + */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_copy_reversed) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength); + + +/********************************************** + * MACROS + **********************************************/ + +/** Helper macro to call #mcuxClMemory_copy_reversed with flow protection. */ +#define MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pTarget, pSource, byteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy_reversed((uint8_t *) (pTarget), (const uint8_t *) (pSource), byteLen, byteLen)) + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMEMORY_COPY_REVERSED_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h new file mode 100644 index 000000000..b29e47b27 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Endianness.h @@ -0,0 +1,116 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Endianness.h + * @brief Memory header for endianness support functions. + * This header exposes macros that enable using endianness support functions. + */ + +/** + * @defgroup mcuxClMemory_Endianness mcuxClMemory_Endianness + * @brief These macros implement endianess management on integers + * @ingroup mcuxClMemory + * @{ + */ + +#ifndef MCUXCLMEMORY_ENDIANNESS_H_ +#define MCUXCLMEMORY_ENDIANNESS_H_ + +#include +#include // Exported features flags header + + +/********************************************** + * MACROS + **********************************************/ + +/** + * @brief Converts a 32-bit unsigned integer to a little-endian order @c uint8_t array . + * + * @note Implementation is platform independent. + * + * @param[out] destination pointer to a 4 byte buffer were 32-bit integer in little-endian will be encoded. + * @param[in] value pointer to the 32-bit integer to be encoded. + * + */ +#define mcuxClMemory_StoreLittleEndian32( destination, value ) \ +do \ +{ \ + (destination)[0] = (uint8_t) (((value) & 0x000000FFU) >> 0u); \ + (destination)[1] = (uint8_t) (((value) & 0x0000FF00U) >> 8u); \ + (destination)[2] = (uint8_t) (((value) & 0x00FF0000U) >> 16u); \ + (destination)[3] = (uint8_t) (((value) & 0xFF000000U) >> 24u); \ +} while (false) + +/** + * @brief Converts a 32-bit unsigned integer to a big-endian order @c uint8_t array. + * + * @note Implementation is platform independent. + * + * @param[in] source pointer to a 4 byte big-endian order @c uint8_t buffer that will be converted to an unsigned integer + * + */ +#define mcuxClMemory_StoreBigEndian32( destination, value ) \ +do \ +{ \ + (destination)[0] = (uint8_t) (((value) & 0xFF000000U) >> 24u); \ + (destination)[1] = (uint8_t) (((value) & 0x00FF0000U) >> 16u); \ + (destination)[2] = (uint8_t) (((value) & 0x0000FF00U) >> 8u); \ + (destination)[3] = (uint8_t) (((value) & 0x000000FFU) >> 0u); \ +} while (false) + +/** + * @brief Converts a little-endian order @c uint8_t array to a 32-bit unsigned integer. + * + * @note Implementation is platform independent. + * + * @param[in] source pointer to a 4 byte little-endian order @c uint8_t buffer that will be converted to an unsigned integer + * + */ +#define mcuxClMemory_LoadLittleEndian32( source ) \ + ( (((uint32_t) (source)[0]) << 0u) | \ + (((uint32_t) (source)[1]) << 8u) | \ + (((uint32_t) (source)[2]) << 16u) | \ + (((uint32_t) (source)[3]) << 24u) ) + + +/** + * @brief Converts a big-endian order @c uint8_t array to a 32-bit unsigned integer. + * + * @param[in] destination pointer to a 4 byte buffer were 32-bit integer in big-endian will be decoded. + * + * @return a 32-bit unsigned integer + */ +#define mcuxClMemory_LoadBigEndian32( source ) \ + ( (((uint32_t) (source)[0]) << 24u) | \ + (((uint32_t) (source)[1]) << 16u) | \ + (((uint32_t) (source)[2]) << 8u) | \ + (((uint32_t) (source)[3]) << 0u) ) + +/** + * @brief MACRO that switches byte endianness of given CPU word. + * + * @param[in] input a 32-bit unsigned integer whose endianness will be reversed. + * + */ + +#ifdef __REV +#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input) __REV(input) +#else +#define MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(input) ((((input) & 0xffu) << 24u) | (((input) & 0xff00u) << 8u) | (((input) & 0xff0000u) >> 8u) | (((input) & 0xff000000u) >> 24u)) +#endif + +#endif /* MCUXCLMEMORY_ENDIANNESS_H_ */ +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h new file mode 100644 index 000000000..e156b700e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Set.h @@ -0,0 +1,77 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Set.h + * @brief Memory header for set function. + * This header exposes functions that enable using memory set functions. + */ + +/** + * @defgroup mcuxClMemory_Set mcuxClMemory_Set + * @brief This function sets all bytes in a memory region to a specified value. + * @ingroup mcuxClMemory + * @{ + */ + +#ifndef MCUXCLMEMORY_SET_H_ +#define MCUXCLMEMORY_SET_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * Sets all bytes of a memory buffer to a specified value. + * + * If the destination buffer is too small, i.e. if bufLength < length, + * (length-bufLength) is added to the Flow Protection token (see @ref mcuxCsslFlowProtection). + * + * @param[out] pDst pointer to the buffer to be set. + * @param[in] val byte value to be set. + * @param[in] length size (in bytes) to be set. + * @param[in] bufLength buffer size (if bufLength < length, only bufLength bytes are set). + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClMemory_set) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength); + +/********************************************** + * MACROS + **********************************************/ + +/** Helper macro to call #mcuxClMemory_set with flow protection. */ +#define MCUXCLMEMORY_FP_MEMORY_SET(pTarget, val, byteLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, byteLen)) + +/** Helper macro to call #mcuxClMemory_set with flow protection with buffer. */ +#define MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pTarget, val, byteLen, buffLen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set((uint8_t *) (pTarget), val, byteLen, buffLen)) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLMEMORY_SET_H_ */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h new file mode 100644 index 000000000..c37f727ae --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/inc/mcuxClMemory_Types.h @@ -0,0 +1,84 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClMemory_Types.h + * @brief Memory type header. + * This header exposes types used by the @ref mcuxClMemory functions. */ + +/** + * @defgroup mcuxClMemory_Types mcuxClMemory_Types + * @brief Defines all types used by the @ref mcuxClMemory functions. + * @ingroup mcuxClMemory + * @{ + */ + +#ifndef MCUXCLMEMORY_TYPES_H +#define MCUXCLMEMORY_TYPES_H + +#include +#include +#include // Exported features flags header +#include +#include + +/********************************************** + * MACROS + **********************************************/ +/** + * @defgroup mcuxClMemory_Types_Macros mcuxClMemory_Types_Macros + * @brief Defines all macros of @ref mcuxClMemory_Types + * @ingroup mcuxClMemory_Types + * @{ + */ +#define MCUXCLMEMORY_API extern ///< Marks a function as a public API function of the mcuxClMemory component + +/** + * @defgroup MCUXCLMEMORY_STATUS_ MCUXCLMEMORY_STATUS_ + * @brief Defines valid mcuxClMemory function return codes + * @ingroup mcuxClMemory_Types_Macros + * @{ + */ + +#define MCUXCLMEMORY_STATUS_OK ((mcuxClMemory_Status_t) 0x09992E03u) ///< Memory operation successful + +/** + * @} + */ + +#define MCUXCLMEMORY_ERRORCODE_OK MCUXCLMEMORY_STATUS_OK ///< Memory operation successful + ///< @deprecated Please use #MCUXCLMEMORY_STATUS_OK instead + +/** + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @brief Type for error codes of mcuxClMemory component functions. + * + * Type returned by mcuxClMemory functions. See @ref MCUXCLMEMORY_STATUS_ for possible options. + */ +typedef uint32_t mcuxClMemory_Status_t; + +/** + * @brief Deprecated type for error codes used by code-flow protected mcuxClMemory component functions. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClMemory_Status_t) mcuxClMemory_Status_Protected_t; + +#endif /* #MCUXCLMEMORY_TYPES_H */ + +/** + * @} + */ diff --git a/components/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c b/components/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c new file mode 100644 index 000000000..78026558f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClMemory/src/mcuxClMemory.c @@ -0,0 +1,271 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy); + + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "modular arithmetic, mod 4") + uint32_t unalignedBytes = (0u - (uint32_t)pDst) % (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_copy_loop); + + // Loop on unaligned bytes if any. + // Loop on words + // Start at first aligned address, increment by 4 bytes. To understand the loop condition, consider without loss of generality a + // byte array b_i of length=4 and bufLength=4. + // + // |0 3|4 4| + // +-------+-------+-------+-------+-------+ + // | b_0 | b_1 | b_2 | b_3 | | + // +-------+-------+-------+-------+-------+ + // + // In order to determine whether a full word can be copied, check with regard to the copying position i: + // * Starting from i=0, a full word can be copied. i+4 is the first position that is outside of the valid range, + // and it is equal to length. + // Therefore, checking that i+4 <= length and i+4 <= bufLength is a valid condition to check whether a full word can be + // copied. + // Loop on remaining bytes. + + //copy unaligned bytes first, if any + size_t i = 0u; + for(i = 0u; (i < length) && (i < bufLength) && (i < unalignedBytes); i++) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].") + *pDst = *pSrc; + pDst++; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("The pointer is CPU word aligned. So, it's safe to cast it to uint32_t*") + uint32_t* p32Dst = (uint32_t *) pDst; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + //loop on words + for (; ((i + sizeof(uint32_t)) <= length) && ((i + sizeof(uint32_t)) <= bufLength); i += sizeof(uint32_t)) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p32Dst will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].") + /* Volatile keyword is added to avoid any chance of optimization (i.e. full word read) */ + uint32_t crtWordVal = (uint32_t)*(volatile const uint8_t *)pSrc; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrc << 8u; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrc << 16u; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + crtWordVal |= (uint32_t)*(volatile const uint8_t *)pSrc << 24u; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + *p32Dst++ = crtWordVal; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + pDst = (uint8_t *) p32Dst; + //loop on remaining bytes + for (; (i < length) && (i < bufLength); i++) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].") + *pDst = *pSrc; + pDst++; + pSrc++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_loop); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_copy, + length - i, + MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_copy_loop, + ((length <= bufLength) ? length : bufLength))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_copy_reversed) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_copy_reversed (uint8_t *pDst, uint8_t const *pSrc, size_t length, size_t bufLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_copy_reversed); + uint32_t len = length; + uint32_t diff; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("diff is non-negative distance between pSrc and pDst, caculated according to platform architecture.") + if (pDst > pSrc) + { + diff = (uint32_t)pDst - (uint32_t)pSrc; + } + else + { + diff = (uint32_t)pSrc - (uint32_t)pDst; + } + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + if (bufLength < length) + { + length = bufLength; + } + + MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_copy_reversed_loop); + + //non-overlap case + if (diff >= length) + { + diff = length; + } + + uint8_t *pDstBt; + const uint8_t *pSrcBt; + if (pSrc > pDst) + { + // first copy the non-overlop part + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].") + pSrcBt = pSrc + len - 1U; + pDstBt = (uint8_t *)pDst; + + while (len > length - diff) + { + *pDstBt = *pSrcBt; + pDstBt++; + pSrcBt--; + len--; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + } + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + //then swap the overlap part + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt2 will be in the valid range pDst[0 ~ bufLength].") + uint8_t *pDstBt2 = pDstBt + len - 1u; + while (len > 1U) + { + uint8_t tempByte = *pDstBt2; + *pDstBt2 = *pDstBt; + pDstBt2--; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + *pDstBt = tempByte; + pDstBt++; + len -= 2U; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + } + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } + else + { + // first copy the non-overlop part + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt will be in the valid range pDst[0 ~ bufLength].") + pDstBt = (uint8_t *)pDst + len - 1U; + pSrcBt = pSrc; + + while (len > length - diff) + { + *pDstBt = *pSrcBt; + pDstBt--; + pSrcBt++; + len--; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + } + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + //then swap the overlap part + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pDstBt2 will be in the valid range pDst[0 ~ bufLength], pDstBt will be in the valid range pDst[0 ~ bufLength].") + uint8_t *pDstBt2 = pDstBt - len + 1u; + while (len > 1U) + { + uint8_t tempByte = *pDstBt2; + *pDstBt2 = *pDstBt; + pDstBt2++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + *pDstBt = tempByte; + pDstBt--; + len -= 2U; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_copy_reversed_loop); + } + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_copy_reversed, + MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_copy_reversed_loop, (length - len))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_set) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_set (uint8_t *pDst, uint8_t val, size_t length, size_t bufLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_set); + + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "modular arithmetic, mod 4") + uint32_t unalignedBytes = (0u - (uint32_t)pDst) % (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_FP_LOOP_DECL(mcuxClMemory_set_loop); + uint32_t wordVal = ((uint32_t)val << 24) | ((uint32_t)val << 16) | ((uint32_t)val << 8) | (uint32_t)val; + + //clear unaligned bytes first, if any + size_t i = 0u; + for(i = 0u; (i < length) && (i < bufLength) && (i < unalignedBytes); i++) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength].") + *pDst = val; + pDst++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("The pointer is CPU word aligned. So, it's safe to cast it to uint32_t*") + uint32_t* p32Dst = (uint32_t *) pDst; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + //loop on words. See mcuxClMemory_copy for an explanation of the condition + while(((i + sizeof(uint32_t)) <= length) && ((i + sizeof(uint32_t)) <= bufLength)) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p32Dst will be in the valid range pDst[0 ~ bufLength] and pSrc will be in the valid range pSrc[0 ~ length].") + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + *p32Dst = wordVal; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + p32Dst++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + i += sizeof(uint32_t); + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + pDst = (uint8_t *) p32Dst; + //loop on remaining bytes + for(; (i < length) && (i < bufLength); i++) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ bufLength].") + *pDst = val; + pDst++; + MCUX_CSSL_FP_LOOP_ITERATION(mcuxClMemory_set_loop); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_set, + length - i, + MCUX_CSSL_FP_LOOP_ITERATIONS(mcuxClMemory_set_loop, + ((length <= bufLength) ? length : bufLength))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClMemory_clear) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClMemory_clear (uint8_t *pDst, size_t length, size_t bufLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClMemory_clear, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_set(pDst, 0U, length, bufLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClMemory_clear); +} diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_FupMacros.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_FupMacros.h new file mode 100644 index 000000000..64fd92439 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_FupMacros.h @@ -0,0 +1,111 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2018-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_FupMacros.h + * @brief Macros for PKC FUP program composing + */ + +#ifndef MCUXCLOSCCAPKC_FUPMACROS_H_ +#define MCUXCLOSCCAPKC_FUPMACROS_H_ + + +#include +#include +#include +#include +#include + +/**********************************************************/ +/* Macros to create FUP program */ +/**********************************************************/ +/** + * @brief FUP programs data structure + */ +typedef struct mcuxClOsccaPkc_FUPEntry +{ + uint8_t a; + uint8_t b; + uint8_t x; + uint8_t y; + uint8_t z; + uint8_t r; +}mcuxClOsccaPkc_FUPEntry_t; + +/** + * Macro to create FUP program, e.g., a FUP program with 2 entries: + * MCUXCLPKC_FUP_EXT_ROM(FupProgram1, FUP_MC1_MMUL(0,1,1), FUP_MC1_MMUL(1,0,0)); + */ +#define MCUXCLOSCCAPKC_FUP_EXT_ROM(name, ...) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_FUP() \ + const mcuxClOsccaPkc_FUPEntry_t name[] __attribute__((aligned(4),section("PH_CL_FUP_PROGRAMS_MAGIC_AREA"))) = { __VA_ARGS__ } \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP() + +#define MCUXCLOSCCAPKC_FUP_LEN(pFupProgram) ((uint8_t) ((sizeof(pFupProgram)) / sizeof(mcuxClOsccaPkc_FUPEntry_t))) + +/**********************************************************/ +/* Macros for FUP CRC entry */ +/**********************************************************/ +/** + * Macro to reserve space for a CRC entry in FUP program. + * The CRC32 value is temporarily set to 0x00000000, and will be updated (filled) by build system. + */ +#define MCUXCLOSCCAPKC_FUP_DATA (0x0U) +#define MCUXCLOSCCAPKC_FUP_CRC (0x10U) +#define MCUXCLOSCCAPKC_CRC_ENTRY {MCUXCLOSCCAPKC_FUP_CRC, 0, 0, 0, 0, 0} + +/** Helper macro to pack CRC entry. */ +#define MCUXCLOSCCAPKC_FUP_CRC_ENTRY(crc32) {MCUXCLOSCCAPKC_FUP_CRC, 0, (crc32) & 0xFFu, ((crc32) >> 8) & 0xFFu, ((crc32) >> 16) & 0xFFu, ((crc32) >> 24) & 0xFFu} + +/**********************************************************/ +/* Helper macros for FUP program composing */ +/**********************************************************/ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "FUP operations are defined.") +/* L0 operation (OP) with parameter set 1, without repeating. */ +#define FUP_OP1_AND(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_AND, Y /* unused */, Y, Z, R} +#define FUP_OP1_OR(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_OR, Y /* unused */, Y, Z, R} +#define FUP_OP1_XOR(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_XOR, Y /* unused */, Y, Z, R} +#define FUP_OP1_SUB(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_SUB, Y /* unused */, Y, Z, R} +#define FUP_OP1_SBX0(R, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_SBX0, Z /* unused */, Z /* unused */, Z, R} +#define FUP_OP1_ROTL(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_ROTL, Y /* unused */, Y, Z, R} +#define FUP_OP1_SHL(R, Y, C) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_SHL, Y /* unused */, Y, C, R} +#define FUP_OP1_ADD(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_ADD, Y /* unused */, Y, Z, R} +#define FUP_OP1_ADD_CONST(R, Y, C) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_ADD_YC, Y /* unused */, Y, C, R} +#define FUP_OP1_NEG(R, Z) {MCUXCLOSCCAPKC_FUP_OP1, MCUXCLOSCCAPKC_FOP_NEG, Z /* unused */, Z /* unused */, Z, R} + +/* L1 microcode (MC) with parameter set 1, without repeating. */ +#define FUP_MC1_MMUL(R, X, Y, Z) {MCUXCLOSCCAPKC_FUP_MC1, MCUXCLOSCCAPKC_FMC_MMUL, X, Y, Z, R} +#define FUP_MC1_MADD(R, Y, Z, X) {MCUXCLOSCCAPKC_FUP_MC1, MCUXCLOSCCAPKC_FMC_MADD, X, Y, Z, R} +#define FUP_MC1_MSUB(R, Y, Z, X) {MCUXCLOSCCAPKC_FUP_MC1, MCUXCLOSCCAPKC_FMC_MSUB, X, Y, Z, R} +#define FUP_MC1_MRED(R, X, Z) {MCUXCLOSCCAPKC_FUP_MC1, MCUXCLOSCCAPKC_FMC_MRED, X, X /* unused */, Z, R} + +/* L0 operation (OP) with parameter set 2, without repeating. */ +#define FUP_OP2_AND(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_AND, Y /* unused */, Y, Z, R} +#define FUP_OP2_OR(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_OR, Y /* unused */, Y, Z, R} +#define FUP_OP2_XOR(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_XOR, Y /* unused */, Y, Z, R} +#define FUP_OP2_SUB(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_SUB, Y /* unused */, Y, Z, R} +#define FUP_OP2_SBX0(R, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_SBX0, Z /* unused */, Z /* unused */, Z, R} +#define FUP_OP2_ROTL(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_ROTL, Y /* unused */, Y, Z, R} +#define FUP_OP2_SHL(R, Y, C) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_SHL, Y /* unused */, Y, C, R} +#define FUP_OP2_ADD(R, Y, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_ADD, Y /* unused */, Y, Z, R} +#define FUP_OP2_ADD_CONST(R, Y, C) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_ADD_YC, Y /* unused */, Y, C, R} +#define FUP_OP2_NEG(R, Z) {MCUXCLOSCCAPKC_FUP_OP2, MCUXCLOSCCAPKC_FOP_NEG, Z /* unused */, Z /* unused */, Z, R} + +/* L1 microcode (MC) with parameter set 2, without repeating. */ +#define FUP_MC2_MMUL(R, X, Y, Z) {MCUXCLOSCCAPKC_FUP_MC2, MCUXCLOSCCAPKC_FMC_MMUL, X, Y, Z, R} +#define FUP_MC2_MADD(R, Y, Z, X) {MCUXCLOSCCAPKC_FUP_MC2, MCUXCLOSCCAPKC_FMC_MADD, X, Y, Z, R} +#define FUP_MC2_MSUB(R, Y, Z, X) {MCUXCLOSCCAPKC_FUP_MC2, MCUXCLOSCCAPKC_FMC_MSUB, X, Y, Z, R} +#define FUP_MC2_MRED(R, X, Z) {MCUXCLOSCCAPKC_FUP_MC2, MCUXCLOSCCAPKC_FMC_MRED, X, X /* unused */, Z, R} +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + +#endif /*MCUXCLOSCCAPKC_FUPMACROS_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Macros.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Macros.h new file mode 100644 index 000000000..2708861aa --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Macros.h @@ -0,0 +1,231 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2018-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_Macros.h + * @brief Macros for accessing PKC hardware IP + */ + + +#ifndef MCUXCLOSCCAPKC_MACROS_H_ +#define MCUXCLOSCCAPKC_MACROS_H_ + + +#include +#include +#include // Exported features flags header +#include +#include + +#include +#include + +/**********************************************************/ +/* Macros for UPTR table and offsets */ +/**********************************************************/ +#define MCUXCLOSCCAPKC_PKCOFFSETTOPTR(offset) (uint8_t *)(MCUXCLOSCCAPKC_PKC_RAM_BASEADDR + (offset)) +#define MCUXCLOSCCAPKC_PTRTOPKCOFFSET(ptr) (uint16_t)((uint32_t)(ptr) - MCUXCLOSCCAPKC_PKC_RAM_BASEADDR) + +/**********************************************************/ +/* Macros for parameter set */ +/**********************************************************/ +/** + * @def MCUXCLOSCCAPKC_WAITFORGOANY + * @brief busy wait until PKC GOANY status bit low + */ +#define MCUXCLOSCCAPKC_WAITFORGOANY() \ + do{} while(0u != MCUXCLOSCCAPKC_SFR_BITREAD(STATUS, GOANY)) + +/** + * @def MCUXCLOSCCAPKC_WAITFORFINISH + * @brief busy wait until PKC calculation finishes + */ +#define MCUXCLOSCCAPKC_WAITFORFINISH() \ + do{} while(0u != MCUXCLOSCCAPKC_SFR_BITREAD(STATUS, ACTIV)) + +/** + * @def MCUXCLOSCCAPKC_OPERANDS + * @brief set PKC operands XPTR, YPTR, ZPTR and RPTR + */ +#define MCUXCLOSCCAPKC_OPERANDS1(offset_x, offset_y, offset_z, offset_r) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(XYPTR1, ((uint32_t) (offset_y) << MCUXCLOSCCAPKC_SFR_BITPOS(XYPTR1, YPTR)) | (uint32_t) (offset_x)); \ + MCUXCLOSCCAPKC_SFR_WRITE(ZRPTR1, ((uint32_t) (offset_r) << MCUXCLOSCCAPKC_SFR_BITPOS(ZRPTR1, RPTR)) | (uint32_t) (offset_z)); \ + } while(0) + +#define MCUXCLOSCCAPKC_OPERANDS2(offset_x, offset_y, offset_z, offset_r) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(XYPTR2, ((uint32_t) (offset_y) << MCUXCLOSCCAPKC_SFR_BITPOS(XYPTR2, YPTR)) | (uint32_t) (offset_x)); \ + MCUXCLOSCCAPKC_SFR_WRITE(ZRPTR2, ((uint32_t) (offset_r) << MCUXCLOSCCAPKC_SFR_BITPOS(ZRPTR2, RPTR)) | (uint32_t) (offset_z)); \ + } while(0) + +/** + * @def MCUXCLOSCCAPKC_OPERANDX + * @brief set start address of X operand of selected parameter set + */ +#define MCUXCLOSCCAPKC_OPERANDX1(offset_x) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(XYPTR1, XPTR, (uint32_t)offset_x); \ + } while(0) +#define MCUXCLOSCCAPKC_OPERANDX2(offset_x) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(XYPTR2, XPTR, (uint32_t)offset_x); \ + } while(0) + +/** + * @def MCUXCLOSCCAPKC_OPERANDY + * @brief set start address of Y operand of selected parameter set + */ +#define MCUXCLOSCCAPKC_OPERANDY1(offset_y) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(XYPTR1, YPTR, (uint32_t)offset_y); \ + } while(0) +#define MCUXCLOSCCAPKC_OPERANDY2(offset_y) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(XYPTR2, YPTR, (uint32_t)offset_y); \ + } while(0) + +/** + * @def MCUXCLOSCCAPKC_OPERANDZ + * @brief set start address of Z operand in bytes or constant operand for ZFIX + */ +#define MCUXCLOSCCAPKC_OPERANDZ1(offset_z) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(ZRPTR1, ZPTR, (uint32_t)offset_z); \ + } while(0) +#define MCUXCLOSCCAPKC_OPERANDZ2(offset_z) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(ZRPTR2, ZPTR, (uint32_t)offset_z); \ + } while(0) + +/** + * @def MCUXCLOSCCAPKC_OPERANDR + * @brief set start address of calculation result R of selected parameter set in bytes + */ +#define MCUXCLOSCCAPKC_OPERANDR1(offset_r) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(ZRPTR1, RPTR, (uint32_t)offset_r); \ + } while(0) + +#define MCUXCLOSCCAPKC_OPERANDR2(offset_r) \ + do{ \ + MCUXCLOSCCAPKC_SFR_BITVALSET(ZRPTR2, RPTR, (uint32_t)offset_r); \ + } while(0) +/** + * @def MCUXCLOSCCAPKC_PS1_LEN + * @brief Sets MCLEN and (OP)LEN of parameter set 1. + */ +#define MCUXCLOSCCAPKC_PS1_SETLENGTH(mclen, oplen) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(LEN1, ((uint32_t) (mclen) << MCUXCLOSCCAPKC_SFR_BITPOS(LEN1, MCLEN)) | (uint32_t) (oplen) ); \ + } while(false) + + +/** + * @def MCUXCLOSCCAPKC_PS2_LEN + * @brief Sets MCLEN and (OP)LEN of parameter set 2. + */ +#define MCUXCLOSCCAPKC_PS2_SETLENGTH(mclen, oplen) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(LEN2, ((uint32_t) (mclen) << MCUXCLOSCCAPKC_SFR_BITPOS(LEN2, MCLEN)) | (uint32_t) (oplen) ); \ + } while(false) + + +/** + * @def MCUXCLOSCCAPKC_MODE + * @brief set PKC mode + */ +#define MCUXCLOSCCAPKC_MODE1(mode) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(MODE1, (uint32_t) mode); \ + } while(false) + +#define MCUXCLOSCCAPKC_MODE2(mode) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(MODE2, (uint32_t) mode); \ + } while(false) + +#define MCUXCLOSCCAPKC_SETUPTRT(pUptrt) \ + do{ \ + MCUXCLOSCCAPKC_SFR_WRITE(UPTRT, (uint32_t) pUptrt); \ + } while(false) + +#define MCUXCLOSCCAPKC_GETUPTRT() (uint16_t *)(MCUXCLOSCCAPKC_SFR_READ(UPTRT)) + +#define MCUXCLOSCCAPKC_SETWORDSIZE(redmul) \ + do { \ + MCUXCLOSCCAPKC_SFR_BITVALSET(CTRL, REDMUL, (uint32_t)redmul); \ + } while(0) + +#define MCUXCLOSCCAPKC_GETREDMUL() (MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, REDMUL)) + +/** + * @def MCUXCLOSCCAPKC_PS1_L0_Start + * @brief start PKC kernel operation with parameter set 1 + */ +#define MCUXCLOSCCAPKC_PS1_L0_START() \ + do { \ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, GOD1); \ + } while (0) + + +/** + * @def MCUXCLOSCCAPKC_PS2_L0_Start + * @brief start PKC kernel operation with parameter set 2 + */ +#define MCUXCLOSCCAPKC_PS2_L0_START() \ + do { \ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, GOD2); \ + } while (0) + +/** + * @def MCUXCLOSCCAPKC_PS1_L1_Start + * @brief execute PKC MC pattern with parameter set 1 + */ +#define MCUXCLOSCCAPKC_PS1_L1_START() \ + do { \ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, GOM1); \ + } while (0) + +/** + * @def MCUXCLOSCCAPKC_PS2_L1_Start + * @brief execute PKC MC pattern with parameter set 2 + */ +#define MCUXCLOSCCAPKC_PS2_L1_START() \ + do { \ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, GOM2); \ + } while (0) + +#define MCUXCLOSCCAPKC_START_FUP() \ + do { \ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, GOU); \ + } while (false) + +/** + * @def MCUXCLOSCCAPKC_GetCarry + * @brief retrieve PKCC carry flag + */ +#define MCUXCLOSCCAPKC_GETCARRY() (MCUXCLOSCCAPKC_SFR_BITREAD(STATUS, CARRY) == 1U) + +/** + * @def MCUXCLOSCCAPKC_GetZero + * @brief retrieve PKCC zero flag + */ +#define MCUXCLOSCCAPKC_GETZERO() (MCUXCLOSCCAPKC_SFR_BITREAD(STATUS, ZERO) == 1U) + +#define MCUXCLOSCCAPKC_PS1_GETOPLEN() (MCUXCLOSCCAPKC_SFR_BITREAD(LEN1, LEN)) +#define MCUXCLOSCCAPKC_PS1_GETMCLEN() (MCUXCLOSCCAPKC_SFR_BITREAD(LEN1, MCLEN)) +#define MCUXCLOSCCAPKC_PS2_GETOPLEN() (MCUXCLOSCCAPKC_SFR_BITREAD(LEN2, LEN)) +#define MCUXCLOSCCAPKC_PS2_GETMCLEN() (MCUXCLOSCCAPKC_SFR_BITREAD(LEN2, MCLEN)) + +#endif /*MCUXCLOSCCAPKC_MACROS_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Operations.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Operations.h new file mode 100644 index 000000000..660d2d264 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_Operations.h @@ -0,0 +1,145 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2018-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_Operations.h + * @brief Mnemonics and macros for PKC calculation + */ + + +#ifndef MCUXCLOSCCAPKC_OPERATIONS_H_ +#define MCUXCLOSCCAPKC_OPERATIONS_H_ + + +#include +#include +#include // Exported features flags header +#include +#include + +#include +#include + +/** + * In order to ease CLib programming, improve code readability and reduce maintenance cost, + * please use help macros, e.g., MCUXCLOSCCAPKC_FXIOP1_MUL(...) to start a PKC operation, + * and corresponding function identifiers, e.g., MCUXCLOSCCAPKC_FXIOP1_MUL in FP balancing. + */ + +/**********************************************************/ +/* Macros for encoding L0/L1 and parameter set 1/2 */ +/**********************************************************/ +#define MCUXCLOSCCAPKC_FUP_OP (0x00U) +#define MCUXCLOSCCAPKC_FUP_MC (0x80U) +#define MCUXCLOSCCAPKC_FUP_PS1 (0x00U) +#define MCUXCLOSCCAPKC_FUP_PS2 (0x40U) + +#define MCUXCLOSCCAPKC_FUP_OP_ZFIX (0x20U) + +#define MCUXCLOSCCAPKC_FUP_OP1 (0x00U) +#define MCUXCLOSCCAPKC_FUP_OP2 (0x40U) +#define MCUXCLOSCCAPKC_FUP_MC1 (0x80U) +#define MCUXCLOSCCAPKC_FUP_MC2 (0xc0U) + +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "PKC operations are defined.") +/**********************************************************/ +/* Mnemonic of PKC L0 operations (OP) */ +/**********************************************************/ +#define MCUXCLOSCCAPKC_FOP_MUL (0x0U) +#define MCUXCLOSCCAPKC_FOP_MAC (0x2U) +#define MCUXCLOSCCAPKC_FOP_NEG (0x9U) +#define MCUXCLOSCCAPKC_FOP_ADD (0xaU) +#define MCUXCLOSCCAPKC_FOP_SUB (0xbU) +#define MCUXCLOSCCAPKC_FOP_AND (0xdU) +#define MCUXCLOSCCAPKC_FOP_OR (0xeU) +#define MCUXCLOSCCAPKC_FOP_XOR (0xfU) +#define MCUXCLOSCCAPKC_FOP_SHL (0x14U) +#define MCUXCLOSCCAPKC_FOP_SHR (0x15U) +#define MCUXCLOSCCAPKC_FOP_ADD_YC (0x1aU) +#define MCUXCLOSCCAPKC_FOP_SUB_YC (0x1bU) +#define MCUXCLOSCCAPKC_FOP_AND_YC (0x1dU) +#define MCUXCLOSCCAPKC_FOP_OR_YC (0x1eU) +#define MCUXCLOSCCAPKC_FOP_SBX0 (0x38U) +#define MCUXCLOSCCAPKC_FOP_CMP_YZ (0x4bU) +#define MCUXCLOSCCAPKC_FOP_ROTL (0x16U) + +/**********************************************************/ +/* Mnemonic of PKC L1 microcodes (MC) */ +/**********************************************************/ +#define MCUXCLOSCCAPKC_FMC_MMUL (0x0U) +#define MCUXCLOSCCAPKC_FMC_MADD (0x21U) +#define MCUXCLOSCCAPKC_FMC_MSUB (0x2aU) +#define MCUXCLOSCCAPKC_FMC_MRED (0x33U) +#define MCUXCLOSCCAPKC_FMC_TMUL (0x13U) +#define MCUXCLOSCCAPKC_FMC_MONTINV (0x5DU) +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + +/**********************************************************/ +/* Helper macros to start specified PKC calculation, */ +/* with flow protection */ +/**********************************************************/ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "PKC operations are defined.") +/* L0 operation (OP) with parameter set 1. */ +#define MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z) (((uint32_t)(R) << 24) | ((uint32_t)(X) << 16) | ((uint32_t)(Y) << 8) | ((uint32_t)(Z))) +#define MCUXCLOSCCAPKC_FXIOP1_SBX0(R, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_SBX0), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, 0, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_MUL(R, X, Y) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_MUL), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, 0))) +#define MCUXCLOSCCAPKC_FXIOP1_MAC(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_MAC), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_SHL_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SHL), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_SHR_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SHR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_SUB_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SUB_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_ADD_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_ADD_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_OR_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_OR_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_AND(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_AND), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_AND_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_AND_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_OR(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_OR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_XOR(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_XOR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_NEG(R, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_NEG), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, 0, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_ADD(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_ADD), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_SUB(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_SUB), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_CMP_YZ(Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_CMP_YZ), MCUXCLOSCCAPKC_PKCPACKARGS(0, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP1_ROTL(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP1 << 8) | (MCUXCLOSCCAPKC_FOP_ROTL), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) + +/* L1 microcode (MC) with parameter set 1. */ +#define MCUXCLOSCCAPKC_FXIMC1_MMUL(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_MMUL), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC1_MADD(R, Y, Z, X) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_MADD), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC1_MSUB(R, Y, Z, X) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_MSUB), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC1_MRED(R, X, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_MRED), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, 0, Z))) +#define MCUXCLOSCCAPKC_FXIMC1_TMUL(R, X, Y) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_TMUL), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, 0))) +#define MCUXCLOSCCAPKC_FXIMC1_MONTINV(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC1 << 8) | (MCUXCLOSCCAPKC_FMC_MONTINV), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) + +/* L0 operation (OP) with parameter set 2. */ +#define MCUXCLOSCCAPKC_FXIOP2_SBX0(R, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_SBX0), ((R) << 24) | (Z))) +#define MCUXCLOSCCAPKC_FXIOP2_MUL(R, X, Y) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_MUL), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, 0))) +#define MCUXCLOSCCAPKC_FXIOP2_MAC(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_MAC), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_SHL_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SHL), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_SHR_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SHR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_SUB_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_SUB_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_ADD_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_ADD_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_OR_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_OR_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_AND(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_AND), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_AND_YC(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op((((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 | MCUXCLOSCCAPKC_FUP_OP_ZFIX) << 8) | (MCUXCLOSCCAPKC_FOP_AND_YC), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_OR(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_OR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_XOR(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_XOR), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_NEG(R, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_NEG), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, 0, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_ADD(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_ADD), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) +#define MCUXCLOSCCAPKC_FXIOP2_SUB(R, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_OP2 << 8) | (MCUXCLOSCCAPKC_FOP_SUB), MCUXCLOSCCAPKC_PKCPACKARGS(R, 0, Y, Z))) + +/* L1 microcode (MC) with parameter set 2. */ +#define MCUXCLOSCCAPKC_FXIMC2_MMUL(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC2 << 8) | (MCUXCLOSCCAPKC_FMC_MMUL), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC2_MADD(R, Y, Z, X) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC2 << 8) | (MCUXCLOSCCAPKC_FMC_MADD), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC2_MSUB(R, Y, Z, X) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC2 << 8) | (MCUXCLOSCCAPKC_FMC_MSUB), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +#define MCUXCLOSCCAPKC_FXIMC2_MRED(R, X, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC2 << 8) | (MCUXCLOSCCAPKC_FMC_MRED), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, 0, Z))) +#define MCUXCLOSCCAPKC_FXIMC2_MONTINV(R, X, Y, Z) MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaPkc_Op(((uint16_t)MCUXCLOSCCAPKC_FUP_MC2 << 8) | (MCUXCLOSCCAPKC_FMC_MONTINV), MCUXCLOSCCAPKC_PKCPACKARGS(R, X, Y, Z))) +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + +#endif /*MCUXCLOSCCAPKC_OPERATIONS_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_SfrAccess.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_SfrAccess.h new file mode 100644 index 000000000..1d83d17a5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/internal/mcuxClOsccaPkc_SfrAccess.h @@ -0,0 +1,88 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_SfrAccess.h + * @brief Macros for abstracting PKC hardware SFR access + */ + + +#ifndef MCUXCLOSCCAPKC_SFRACCESS_H_ +#define MCUXCLOSCCAPKC_SFRACCESS_H_ + +#include // Exported features flags header +#include + +/**** ****/ +/**** PKC Hardware Abstraction Layer ****/ +/**** ****/ + +/** + * 2 different PKC hardware definition headers are supported. + * Only one of them should be used/included. + */ + + +/** Special definitions of multi-bit bit field. */ +#define MCUXCLOSCCAPKC_SFR_CFG_RNDDLY_NODLY (((uint32_t)(((uint32_t)(0u)) << MCUXCLOSCCAPKC_SFR_BITPOS(CFG,RNDDLY))) & MCUXCLOSCCAPKC_SFR_BITMSK(CFG,RNDDLY)) +#define MCUXCLOSCCAPKC_SFR_CTRL_REDMUL_FULLSZ (((uint32_t)(((uint32_t)(0u)) << MCUXCLOSCCAPKC_SFR_BITPOS(CFG,RNDDLY))) & MCUXCLOSCCAPKC_SFR_BITMSK(CFG,RNDDLY)) + + +/** + * Definitions for accessing PKC SFRs via, e.g., IP_PKC->STATUS. + */ + +/** Helper macros for constructing SFR field name constants */ +#define MCUXCLOSCCAPKC_PASTE(a,b) a ## b +#define MCUXCLOSCCAPKC_CONCAT(a,b) MCUXCLOSCCAPKC_PASTE(a,b) +#define MCUXCLOSCCAPKC_SFR_FIELD(prefix,sfr,field) MCUXCLOSCCAPKC_CONCAT(prefix, sfr ## _ ## field) + +/** Helper macros to get the mask and shift values for a specific PKC SFR field */ +#define MCUXCLOSCCAPKC_SFR_BITMSK(sfr, field) MCUXCLOSCCAPKC_CONCAT(MCUXCLOSCCAPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field), PKC_SFR_SUFFIX_MSK) +#define MCUXCLOSCCAPKC_SFR_BITPOS(sfr, field) MCUXCLOSCCAPKC_CONCAT(MCUXCLOSCCAPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field), PKC_SFR_SUFFIX_POS) +#define MCUXCLOSCCAPKC_SFR_BITFMT(sfr, field, val) (MCUXCLOSCCAPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field) (val)) + + +/**********************************************************/ +/* Helper macros for PKC SFR access */ +/**********************************************************/ + +/** Read from PKC SFR */ +#define MCUXCLOSCCAPKC_SFR_READ(sfr) (PKC_SFR_BASE->PKC_SFR_NAME(sfr)) + +/** Write to PKC SFR */ +#define MCUXCLOSCCAPKC_SFR_WRITE(sfr, value) \ + do{ PKC_SFR_BASE->PKC_SFR_NAME(sfr) = (value); } while(false) + +/** Read from PKC SFR bit field */ +#define MCUXCLOSCCAPKC_SFR_BITREAD(sfr, bit) \ + ((PKC_SFR_BASE->PKC_SFR_NAME(sfr) & MCUXCLOSCCAPKC_SFR_BITMSK(sfr, bit)) >> MCUXCLOSCCAPKC_SFR_BITPOS(sfr, bit)) + +/** Set bit field of PKC SFR (read-modify-write) */ +#define MCUXCLOSCCAPKC_SFR_BITSET(sfr, bit) \ + do{ PKC_SFR_BASE->PKC_SFR_NAME(sfr) |= MCUXCLOSCCAPKC_SFR_BITMSK(sfr, bit); } while(false) + +/** Clear bit field of PKC SFR (read-modify-write) */ +#define MCUXCLOSCCAPKC_SFR_BITCLEAR(sfr, bit) \ + do{ PKC_SFR_BASE->PKC_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLOSCCAPKC_SFR_BITMSK(sfr, bit)); } while(false) + +/** Set value of multi-bit field of PKC SFR (read-modify-write) */ +#define MCUXCLOSCCAPKC_SFR_BITVALSET(sfr, bit, val) \ + do{ uint32_t temp = PKC_SFR_BASE->PKC_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLOSCCAPKC_SFR_BITMSK(sfr, bit)); \ + PKC_SFR_BASE->PKC_SFR_NAME(sfr) = (((val) << MCUXCLOSCCAPKC_SFR_BITPOS(sfr, bit)) & MCUXCLOSCCAPKC_SFR_BITMSK(sfr, bit)) | temp; \ + } while(false) + + +/**** ------------------------------ ****/ + +#endif /* MCUXCLOSCCAPKC_SFRACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc.h new file mode 100644 index 000000000..60539a542 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc.h + * @brief Top level header of mcuxClOsccaPkc component (PKC hardware driver) + * + * @defgroup mcuxClOsccaPkc mcuxClOsccaPkc + * @brief component of PKC hardware driver + */ + + +#ifndef MCUXCLOSCCAPKC_H_ +#define MCUXCLOSCCAPKC_H_ + +#include // Exported features flags header +#include +#include + + +#endif /* MCUXCLOSCCAPKC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Functions.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Functions.h new file mode 100644 index 000000000..4fd0e42df --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Functions.h @@ -0,0 +1,85 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2018-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_Functions.h + * @brief APIs of mcuxClOsccaPkc component + */ + + +#ifndef MCUXCLOSCCAPKC_FUNCTIONS_H_ +#define MCUXCLOSCCAPKC_FUNCTIONS_H_ + + +#include +#include +#include // Exported features flags header +#include +#include + +/** + * @defgroup mcuxClOsccaPkc_Functions mcuxClOsccaPkc_Functions + * @brief Defines all functions of @ref mcuxClOsccaPkc + * @ingroup mcuxClOsccaPkc + * @{ + */ + +/** + * @brief Structure of PKC state backup. + */ +typedef struct mcuxClOsccaPkc_State_t +{ + uint32_t cfg; + uint32_t ctrl; +}mcuxClOsccaPkc_State_t; + +/** @brief type of FUP program address. */ +typedef const struct mcuxClOsccaPkc_FUPEntry * mcuxClOsccaPkc_PtrFUPEntry_t; + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Reset) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Reset(mcuxClOsccaPkc_State_t *state) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Init) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Init(mcuxClOsccaPkc_State_t *state) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_SetWordSize) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetWordSize(uint32_t redmul) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_GetWordSize) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_GetWordSize(void) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_WaitforFinish) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_WaitforFinish(void) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_SetFupTable) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetFupTable(void *pUPTRT) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_Op) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Op(uint32_t mode, uint32_t iRiXiYiZ) ; +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_StartFupProgram) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_StartFupProgram(mcuxClOsccaPkc_PtrFUPEntry_t fupProgram, uint32_t fupProgramSize); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeNDash) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeNDash(uint32_t iNiTiXiX); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeQSquared) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeQSquared(uint32_t iQiMiTiX, uint16_t iMs); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_GeneratePointerTable) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_GeneratePointerTable(uint16_t *pOperandsBase, uint8_t *pBufferBase, uint32_t bufferSize, uint32_t bufferNums); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_MultipleShiftRotate_Index) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_MultipleShiftRotate_Index(uint32_t iModuluss, uint32_t iModulus, uint32_t leadingZeroBits, _Bool shiftLeft); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_LeadingZeros) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_LeadingZeros(uint8_t *pNum, uint32_t numLen); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_ComputeModInv) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeModInv(uint32_t iRiIiNiT, uint32_t iT2); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaPkc_CalcMontInverse) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_CalcMontInverse(uint32_t iIiRiNiT, uint32_t R2); + + +/** + * @} + */ /* mcuxClOsccaPkc_Functions */ + +#endif /*MCUXCLOSCCAPKC_FUNCTIONS_H_*/ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Types.h b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Types.h new file mode 100644 index 000000000..65d2bdb45 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/inc/mcuxClOsccaPkc_Types.h @@ -0,0 +1,48 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2018-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc_Types.h + * @brief Type definitions of mcuxClOsccaPkc component + */ + + +#ifndef MCUXCLOSCCAPKC_TYPES_H +#define MCUXCLOSCCAPKC_TYPES_H + + +#include +#include // Exported features flags header +#include +#include +#include + +/**********************************************************/ +/* Helper macros */ +/**********************************************************/ +/** @brief Macros for packing 2 8-bit parameters. */ +#define MCUXCLOSCCAPKC_PKCPACKARGS2(hi8, lo8) \ + ( ((uint16_t) (hi8) << 8u) | ((uint16_t) (lo8)) ) + + +/**********************************************************/ +/* PKC information */ +/**********************************************************/ +#define MCUXCLOSCCAPKC_PKC_RAM_BASEADDR ((uint32_t)PKC_RAM_ADDR) +#define MCUXCLOSCCAPKC_WORD_SIZE (PKC_WORD_SIZE) + +/** + * @} + */ /* mcuxClOsccaPkc_Types */ + +#endif /* #MCUXCLOSCCAPKC_TYPES_H */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaPkc/src/mcuxClOsccaPkc.c b/components/els_pkc/src/comps/mcuxClOsccaPkc/src/mcuxClOsccaPkc.c new file mode 100644 index 000000000..b0718715a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaPkc/src/mcuxClOsccaPkc.c @@ -0,0 +1,661 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaPkc.c + * @brief mcuxClOsccaPkc: implementation of PKC functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_Init) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Init( + mcuxClOsccaPkc_State_t *state +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_Init); +#define PKC_CTRL_DEFAULT_SETUP ( /* Reset and Clear Errors are excluded */ \ + ( (uint32_t)0U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, STOP)) | \ + ( (uint32_t)0U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, GF2CONV)) | \ + ( (uint32_t)0U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, REDMUL)) \ + ) +#define PKC_CFG_DEFAULT_SETUP ( \ + ( 1U << MCUXCLOSCCAPKC_SFR_BITPOS(CFG, IDLEOP) ) | \ + ( 1U << MCUXCLOSCCAPKC_SFR_BITPOS(CFG, CLKRND) ) | \ + ( 1U << MCUXCLOSCCAPKC_SFR_BITPOS(CFG, REDMULNOISE) ) | \ + ( 0U << MCUXCLOSCCAPKC_SFR_BITPOS(CFG, RNDDLY) ) /* no delay */ \ + ) + + /* clear STOP bit */ + MCUXCLOSCCAPKC_SFR_BITCLEAR(CTRL, STOP); + while( 0U != MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, STOP) ) + { + /* wait */ + } + + /* read current state */ + if(state != NULL) + { + state->cfg = MCUXCLOSCCAPKC_SFR_READ(CFG); + state->ctrl = MCUXCLOSCCAPKC_SFR_READ(CTRL); + } + + /* set reset bit */ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, RESET); + while( 0U == MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, RESET) ) + { + /* wait */ + } + + /* clear the error */ + MCUXCLOSCCAPKC_SFR_WRITE(ACCESS_ERR_CLR, 1U); + /* configure Pkc */ + /* MISRA Ex. 22, while(0) is allowed */ + MCUXCLOSCCAPKC_SFR_WRITE(CTRL, + ( (uint32_t)1U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, RESET) ) | + ( (uint32_t)1U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, CACHE_EN) ) | + ( (uint32_t)1U << MCUXCLOSCCAPKC_SFR_BITPOS(CTRL, CLRCACHE) ) | + PKC_CTRL_DEFAULT_SETUP ); + + MCUXCLOSCCAPKC_SFR_WRITE(CFG, PKC_CFG_DEFAULT_SETUP); + + /* clear reset bit */ + MCUXCLOSCCAPKC_SFR_BITCLEAR(CTRL, RESET); + while( 0U != MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, RESET) ) + { + /* wait */ + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_Init); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_Reset) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Reset( + mcuxClOsccaPkc_State_t *state /**< pointer to state as returned by mcuxClOsccaPkc_Init */ +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_Reset); + /* clear STOP bit */ + MCUXCLOSCCAPKC_SFR_BITCLEAR(CTRL, STOP); + while( 0U != MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, STOP) ) + { + /* wait */ + } + + /* sets reset bit and clear status implicitly */ + MCUXCLOSCCAPKC_SFR_BITSET(CTRL, RESET); + while( 0U == MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, RESET) ) + { + /* wait */ + } + + /* clears all mode, ptr and len registers */ + MCUXCLOSCCAPKC_SFR_WRITE(MODE1, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(MODE2, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(XYPTR1, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(XYPTR2, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(ZRPTR1, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(ZRPTR2, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(LEN1, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(LEN2, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(UPTRT, 0u); + MCUXCLOSCCAPKC_SFR_WRITE(ULEN, 0u); + + /* restores old CFG and CTRL states (including reset) */ + if(NULL != state) + { + MCUXCLOSCCAPKC_SFR_WRITE(CFG, state->cfg); + MCUXCLOSCCAPKC_SFR_WRITE(CTRL, state->ctrl); + } + + /* clear reset bit, because of possible STOP bit */ + MCUXCLOSCCAPKC_SFR_BITCLEAR(CTRL, RESET); + while( 0U != MCUXCLOSCCAPKC_SFR_BITREAD(CTRL, RESET) ) + { + /* wait */ + } + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_Reset); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_GetWordSize) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_GetWordSize(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_GetWordSize); + uint32_t redmul; + + redmul = MCUXCLOSCCAPKC_GETREDMUL(); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaPkc_GetWordSize, (uint32_t)(redmul > 0U ? (uint32_t)2U << redmul : (uint32_t)16U)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_SetWordSize) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetWordSize(uint32_t redmul) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_SetWordSize); + MCUXCLOSCCAPKC_SETWORDSIZE(redmul); + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_SetWordSize); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_WaitforFinish) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_WaitforFinish(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_WaitforFinish); + MCUXCLOSCCAPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_WaitforFinish); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_SetFupTable) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_SetFupTable(void *pUPTRT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_SetFupTable); + MCUXCLOSCCAPKC_WAITFORGOANY(); + /* MISRA Ex.2 - Rule 11.6 */ + MCUXCLOSCCAPKC_SETUPTRT(pUPTRT); + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_SetFupTable); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_Op) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_Op(uint32_t mode, uint32_t iRiXiYiZ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_Op); + uint32_t iR, iX, iY, iZ; + uint32_t mode0, mode1; + uint16_t pR, pX, pY, pZ; + uint16_t *pUPTR = (uint16_t*)MCUXCLOSCCAPKC_GETUPTRT(); + + iR = (iRiXiYiZ >> 24U) & 0xFFU; + iX = (iRiXiYiZ >> 16U) & 0xFFU; + iY = (iRiXiYiZ >> 8U) & 0xFFU; + iZ = (iRiXiYiZ) & 0xFFU; + + mode0 = (mode >> 8U) & 0xFFU; + mode1 = (mode) & 0xFFU; + + pR = pUPTR[iR]; + pX = pUPTR[iX]; + pY = pUPTR[iY]; + if (MCUXCLOSCCAPKC_FUP_OP_ZFIX == (mode0 & MCUXCLOSCCAPKC_FUP_OP_ZFIX)) + { + pZ = (uint16_t)iZ; + } + else + { + pZ = pUPTR[iZ]; + } + + MCUXCLOSCCAPKC_WAITFORGOANY(); + + if (MCUXCLOSCCAPKC_FUP_PS2 == (mode0 & MCUXCLOSCCAPKC_FUP_PS2)) + { + //Fill PS2 registers + MCUXCLOSCCAPKC_OPERANDS2(pX, pY, pZ, pR); + MCUXCLOSCCAPKC_MODE2(mode1); + + if (MCUXCLOSCCAPKC_FUP_MC == (mode0 & MCUXCLOSCCAPKC_FUP_MC)) + { + //Start layer MC + MCUXCLOSCCAPKC_PS2_L1_START(); + } + else + { + //Start layer OP + MCUXCLOSCCAPKC_PS2_L0_START(); + } + } + else + { + //Fill PS1 registers + MCUXCLOSCCAPKC_OPERANDS1(pX, pY, pZ, pR); + MCUXCLOSCCAPKC_MODE1(mode1); + + if (MCUXCLOSCCAPKC_FUP_MC == (mode0 & MCUXCLOSCCAPKC_FUP_MC)) + { + //Start layer MC + MCUXCLOSCCAPKC_PS1_L1_START(); + } + else + { + //Start layer OP + MCUXCLOSCCAPKC_PS1_L0_START(); + } + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_Op); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_GeneratePointerTable) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_GeneratePointerTable(uint16_t *pOperandsBase, + uint8_t *pBufferBase, + uint32_t bufferSize, + uint32_t bufferNums) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_GeneratePointerTable); + uint32_t i; + + for (i = 0U; i < bufferNums; i++) + { + pOperandsBase[i] = + MCUXCLOSCCAPKC_PTRTOPKCOFFSET(pBufferBase + i * bufferSize); + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_GeneratePointerTable); +} + +/* + * be careful, this function will corrupt the buffer behind operand iT + * because of the MAC_Const + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_ComputeNDash) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeNDash(uint32_t iNiTiXiX) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_ComputeNDash, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_GetWordSize), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + uint32_t NdashWordSizeByte; + uint32_t NdashWordSizeBit; + uint16_t *pUPTRT; + uint8_t *pN, *pTmp, *pNDash; + uint32_t iN, iT; + + iN = (iNiTiXiX >> 24U) & 0xffU; + iT = (iNiTiXiX >> 16U) & 0xffU; + + MCUX_CSSL_FP_FUNCTION_CALL(NdashByte,mcuxClOsccaPkc_GetWordSize()); + NdashWordSizeByte = NdashByte; + NdashWordSizeBit = NdashWordSizeByte*8U; + + pUPTRT = MCUXCLOSCCAPKC_GETUPTRT(); + pN = MCUXCLOSCCAPKC_PKCOFFSETTOPTR(pUPTRT[iN]); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_ARRAY_OUT_OF_BOUNDS("pN is allocated such that pNDash is in front of it, as required by the PKC") + pNDash = pN - NdashWordSizeByte; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ARRAY_OUT_OF_BOUNDS() + pTmp = MCUXCLOSCCAPKC_PKCOFFSETTOPTR(pUPTRT[iT]); + + MCUXCLMEMORY_FP_MEMORY_CLEAR(pNDash, NdashWordSizeByte); + + *pNDash = 1U; + + MCUXCLOSCCAPKC_WAITFORFINISH(); + MCUXCLOSCCAPKC_PS2_SETLENGTH(0u, NdashWordSizeByte); + + /* R = (-X)^(-1) (mod 2^i) ==> R*X + 1 = 0 (mod 2^i) */ + /* (RX + 1)^2 = 0 (mod 2^(2i)) */ + /* (RX + 2)R * X + 1 = 0 (mod 2^(2i)) */ + + MCUXCLOSCCAPKC_OPERANDX2(pNDash); + + uint32_t i = 1U; + while(NdashWordSizeBit > i) + { + /* T := R * X + 2 */ + MCUXCLOSCCAPKC_WAITFORGOANY(); + MCUXCLOSCCAPKC_OPERANDY2(pN); + MCUXCLOSCCAPKC_OPERANDZ2(0x0002U); + MCUXCLOSCCAPKC_OPERANDR2(pTmp); + MCUXCLOSCCAPKC_MODE2(0x12U); /* 0x12 MAC_CONST, R := X[0] * Y + CONST */ /* lenT = lenY + 2FW (= 3 FW here) */ + MCUXCLOSCCAPKC_PS2_L0_START(); + + /* T := R * T = (RX + 2) * R */ + MCUXCLOSCCAPKC_WAITFORGOANY(); + MCUXCLOSCCAPKC_OPERANDY2(pTmp); + MCUXCLOSCCAPKC_MODE2(0x00U); /* 0x00 MUL, R := X[0] * Y */ + MCUXCLOSCCAPKC_PS2_L0_START(); + + /* R := T */ + MCUXCLOSCCAPKC_WAITFORGOANY(); + MCUXCLOSCCAPKC_OPERANDZ2(0x0000U); + MCUXCLOSCCAPKC_OPERANDR2(pNDash); + MCUXCLOSCCAPKC_MODE2(0x1eU); /* 0x1e OR_CONST, R := Y OR CONST||CONST||...||CONST */ + MCUXCLOSCCAPKC_PS2_L0_START(); + + i <<= 1; + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_ComputeNDash); +} + +/* + * Count leading zeros of non-zero value. + * If the value is 0, the result is undefined. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_CountLeadingZerosWord) +static inline MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_CountLeadingZerosWord(uint32_t value) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_CountLeadingZerosWord); +#ifdef __CLZ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaPkc_CountLeadingZerosWord, __CLZ(value)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaPkc_CountLeadingZerosWord, (uint32_t)__builtin_clz(value)); +#endif +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_LeadingZeros) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClOsccaPkc_LeadingZeros(uint8_t *pNum, uint32_t numLen) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_LeadingZeros); + uint32_t zeros = 0U; + uint32_t temp; + uint32_t numLenByWord = numLen / (sizeof(uint32_t)) ; + /* MISRA Ex.24 - Rule 11.3 */ + uint32_t *pBigNum = (uint32_t *)pNum; + uint32_t loopTimes = 0U; + + while(numLenByWord > 0U) + { + temp = pBigNum[numLenByWord - 1U]; + if (0U == temp) + { + zeros += sizeof(uint32_t) * 8U; + } + else + { + loopTimes++; + MCUX_CSSL_FP_FUNCTION_CALL(zeroWords, mcuxClOsccaPkc_CountLeadingZerosWord(temp)); + zeros += zeroWords; + break; + } + numLenByWord--; + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaPkc_LeadingZeros, zeros, loopTimes * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_CountLeadingZerosWord)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_MultipleShiftRotate_Index) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_MultipleShiftRotate_Index(uint32_t iModuluss, uint32_t iModulus, + uint32_t leadingZeroBits, _Bool shiftLeft) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_MultipleShiftRotate_Index, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_GetWordSize)); + uint32_t pkcWordSizeByte; + uint32_t pkcWordSizeBit; + uint32_t shiftBits; + uint32_t shiftTimes = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(NdashByte,mcuxClOsccaPkc_GetWordSize()); + pkcWordSizeByte = NdashByte; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pkcWordSizeByte * 8U cannot overflow.") + pkcWordSizeBit = pkcWordSizeByte * 8U; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iModuluss, iModulus, 0); + while(leadingZeroBits > 0U) + { + if (leadingZeroBits >= pkcWordSizeBit) + { + shiftBits = pkcWordSizeBit - 1U; + } + else + { + shiftBits = leadingZeroBits; + } + + if (shiftLeft) + { + MCUXCLOSCCAPKC_FXIOP1_SHL_YC(iModuluss, iModuluss, shiftBits); + } + else + { + MCUXCLOSCCAPKC_FXIOP1_SHR_YC(iModuluss, iModuluss, shiftBits); + } + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("leadingZeroBits cannot be less than shiftBits.") + leadingZeroBits -= shiftBits; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("The size of shiftTimes is big enough, it cannot overflow.") + shiftTimes++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + } + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_MultipleShiftRotate_Index, ((shiftTimes + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_Op))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_ComputeQSquared) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeQSquared(uint32_t iQiMiTiX, uint16_t iMs) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_ComputeQSquared); + uint32_t j = 0U; + bool msb_found = false; + uint32_t opByteLen; + uint32_t exponent, expBitLen; + uint32_t iQ, iM, iT, iX; + + iQ = (iQiMiTiX >> 24U) & 0xffU; + iM = (iQiMiTiX >> 16U) & 0xffU; + iT = (iQiMiTiX >> 8U) & 0xffU; + iX = (iQiMiTiX) & 0xffU; + + opByteLen = MCUXCLOSCCAPKC_PS1_GETOPLEN(); + + /* 1 in MR */ + MCUXCLOSCCAPKC_FXIOP1_NEG(iT, iM); + /* 2 in MR */ + MCUXCLOSCCAPKC_FXIMC1_MADD(iX, iT, iT, iMs); + + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iQ, iX, 0); + + exponent = opByteLen * 8U; + expBitLen = sizeof(exponent) * 8U - 1U; + j = expBitLen; + uint32_t loopTimes = 0U; + do + { + if (((exponent & ((uint32_t)1U << j)) == 0U) && (msb_found == false)) + { + continue; + } + else if (msb_found == false) + { + /* ignore the msb, because we have get 2 by MADD */ + msb_found = true; + } + else + { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("The size of loopTimes is big enough, it cannot overflow.") + loopTimes++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + /* square */ + MCUXCLOSCCAPKC_FXIMC1_MMUL(iT, iQ, iQ, iM); + if (0U != (exponent & ((uint32_t)1U << j))) + { + /* mutliply */ + MCUXCLOSCCAPKC_FXIMC1_MMUL(iQ, iT, iX, iM); + } + else + { + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iQ, iT, 0U); + } + + } + }while ((j--) != 0U); + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_ComputeQSquared, ((3U + loopTimes * 2U) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_Op))); +} + +/* note: iR is R in MR, output iI is R's inverse in MR */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_ComputeModInv) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_ComputeModInv(uint32_t iRiIiNiT, uint32_t iT2) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_ComputeModInv); + uint32_t i, j, loopTimes = 0U, loopTimes1 = 0U; + bool msb_found = false; + uint32_t iR, iI, iN, iT; + uint16_t *pOperands; + uint16_t *pExp; + uint32_t operandSize = MCUXCLOSCCAPKC_PS1_GETOPLEN(); + + + iR = (iRiIiNiT >> 24U) & 0xffU; + iI = (iRiIiNiT >> 16U) & 0xffU; + iN = (iRiIiNiT >> 8U) & 0xffU; + iT = iRiIiNiT & 0xffU; + + pOperands = MCUXCLOSCCAPKC_GETUPTRT(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Reinterpret pointer type to uint16_t* types.") + pExp = (uint16_t *)MCUXCLOSCCAPKC_PKCOFFSETTOPTR(pOperands[iT2]); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + /* the initial value is 1 in MR */ + MCUXCLOSCCAPKC_FXIOP1_NEG(iT, iN); + + MCUXCLOSCCAPKC_FXIOP1_SUB_YC(iT2, iN, 2U); + MCUXCLOSCCAPKC_WAITFORFINISH(); + i = (operandSize >> 1U) - 1U; + + do + { + j = 15U; + do + { + if ((0U == (pExp[i] & ((uint16_t)1U << j))) && (false == msb_found)) + { + continue; + } + else + { + msb_found = true; + } + + /* square */ + MCUXCLOSCCAPKC_FXIMC1_MMUL(iI, iT, iT, iN); + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iT, iI, 0); + + if(0U != (pExp[i] & ((uint16_t)1U << j))) + { + loopTimes1++; + /* multiply */ + MCUXCLOSCCAPKC_FXIMC1_MMUL(iI, iR, iT, iN); + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iT, iI, 0); + } + else + { + // Do nothing, just balance to avoid misra violation. + } + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("The size of loopTimes is big enough, it cannot overflow.") + loopTimes++; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + }while ((j--) != 0U); + }while ((i--) != 0U); + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_ComputeModInv,((loopTimes * 2U + loopTimes1 * 2U + 2U) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_Op))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_CalcMontInverse) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_CalcMontInverse(uint32_t iIiRiNiT, uint32_t R2) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_CalcMontInverse); + uint32_t iN, iI, iT, iR; + uint32_t exponent, shiftBits; + uint32_t len = MCUXCLOSCCAPKC_PS1_GETOPLEN(); + MCUX_CSSL_FP_FUNCTION_CALL(pkcWordSize, mcuxClOsccaPkc_GetWordSize()); + uint16_t *pOperands = MCUXCLOSCCAPKC_GETUPTRT(); + + iI = (iIiRiNiT >> 24U) & 0xFFU; + iR = (iIiRiNiT >> 16U) & 0xFFU; + iN = (iIiRiNiT >> 8U) & 0xFFU; + iT = (iIiRiNiT) & 0xFFU; + + /* set PS1 Lens to (len + pkcWordSize, len + pkcWordSize) */ + MCUXCLOSCCAPKC_WAITFORGOANY(); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("len is PKC operand length, len + pkcWordSize cannot overflow.") + MCUXCLOSCCAPKC_PS1_SETLENGTH(len + pkcWordSize, len + pkcWordSize); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + /* set T := 0, with extra pkcWordSize (len + pkcWordSize) */ + MCUXCLOSCCAPKC_FXIOP1_AND_YC(iT, iT, 0x00U); + + /* set R := T + 1 = 1 */ + MCUXCLOSCCAPKC_FXIOP1_ADD_YC(iR, iT, 0x01U); + + /* set the loop counter LC = 31, for almostMontgomeryInverse */ + MCUXCLOSCCAPKC_WAITFORGOANY(); + MCUXCLOSCCAPKC_PS1_SETLENGTH(31, len); + + if(pkcWordSize > 16u) + { + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_CalcMontInverse); + } + if((pOperands[iT] + pkcWordSize) > ((uint16_t) - 1)) + { + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_CalcMontInverse); + } + pOperands[iT] = pOperands[iT] + (uint16_t)pkcWordSize; + /* perform almostMontgomeryInverse using MC code */ + /* T (upper part) = almostMontgomeryInverse(X) = - X^(-1) * 2^exp */ + /* T (lower fWord) = exp */ + MCUXCLOSCCAPKC_FXIMC1_MONTINV(iT, iN, iI, iR); + /* save the result of almostMontgomeryInverse to iI */ + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iI, iT, 0x00U); + MCUXCLOSCCAPKC_WAITFORFINISH(); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("PKC operand buffers are 32 bit aligned.") + exponent = *(volatile uint32_t *)MCUXCLOSCCAPKC_PKCOFFSETTOPTR((uint32_t)pOperands[iT] - pkcWordSize); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + + /* recover the modulus */ + MCUXCLOSCCAPKC_FXIOP1_OR_YC(iN, iR, 0x00U); /* N = R = n, because N*R = n and N = gcd(i,n) = 1. */ + + pOperands[iT] = pOperands[iT] - (uint16_t)pkcWordSize; + MCUXCLOSCCAPKC_FXIOP1_XOR(iT, iT, iT); + MCUXCLOSCCAPKC_PS1_SETLENGTH(len, len); + if (exponent <= len * 8U) + { + shiftBits = len * 8U - exponent; + *MCUXCLOSCCAPKC_PKCOFFSETTOPTR(pOperands[iT] + (shiftBits >> 3U)) |= (1U << (shiftBits & 7U)); + MCUXCLOSCCAPKC_FXIMC1_MMUL(iR, iI, iT, iN); + MCUXCLOSCCAPKC_FXIMC1_MSUB(iI, iN, iR, iN); + MCUXCLOSCCAPKC_FXIMC1_MMUL(iR, iI, R2, iN); + } + else + { + if(2U * len * 8U < exponent) + { + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_CalcMontInverse); + } + shiftBits = 2U * len * 8U - exponent; + *MCUXCLOSCCAPKC_PKCOFFSETTOPTR(pOperands[iT] + (shiftBits >> 3U)) |= (1U << (shiftBits & 7U)); + MCUXCLOSCCAPKC_FXIMC1_MMUL(iR, iI, iT, iN); + MCUXCLOSCCAPKC_FXIMC1_MSUB(iR, iN, iR, iN); + } + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_CalcMontInverse, 8U * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_Op), + MCUX_CSSL_FP_CONDITIONAL((exponent <= len * 8U), MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_Op)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaPkc_GetWordSize)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaPkc_StartFupProgram) /* No semicolon */ +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaPkc_StartFupProgram(mcuxClOsccaPkc_PtrFUPEntry_t fupProgram, + uint32_t fupProgramSize) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaPkc_StartFupProgram); + MCUXCLOSCCAPKC_WAITFORFINISH(); + uint32_t pkc_ctrl = MCUXCLOSCCAPKC_SFR_READ(CTRL) | MCUXCLOSCCAPKC_SFR_BITMSK(CTRL, GOU) | MCUXCLOSCCAPKC_SFR_BITMSK(CTRL, CLRCACHE); + MCUXCLOSCCAPKC_SFR_WRITE(ULEN, fupProgramSize); + /* MISRA Ex.2 - Rule 11.6 */ + MCUXCLOSCCAPKC_SFR_WRITE(UPTR, (uint32_t)fupProgram); + /* Clear PKC UPTRT cache and start calculation of the FUP program. */ + MCUXCLOSCCAPKC_SFR_WRITE(CTRL, pkc_ctrl); + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaPkc_StartFupProgram); +} diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Core_sm3.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Core_sm3.h new file mode 100644 index 000000000..ba9744927 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Core_sm3.h @@ -0,0 +1,61 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_Core_sm3.h + * @brief Internal definitions and declarations of the *CORE* layer dedicated to SAFO SM3 + */ + +#ifndef MCUXCLOSCCASM3_CORE_SM3_H_ +#define MCUXCLOSCCASM3_CORE_SM3_H_ + +#include +#include +#include + +/********************************************************** + * Type declarations + **********************************************************/ + +/* + * \brief Function SM3 Process Message on HW Norm mode + * + * \return void + * + * \param[out] workArea Pointer to buffer after processing + * \param[in] data Pointer to buffer of message that needs to be processed + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaSm3_Safo_Hash_Norm) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_Norm(uint32_t *workArea, uint32_t *data); + +/* + * \brief Function SM3 Process Message on HW Auto mode + * + * \return void + * + * \param[out] workArea Pointer to buffer after processing + * \param[in] data Pointer to buffer of message that needs to be processed + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaSm3_Safo_Hash_Auto) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_Auto(uint32_t *workArea, uint32_t *data); + + /* + * \brief Function SM3 PreLoad IV or Hash + * + * \return void + * + * \param[in] workArea Pointer to buffer for IV + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClOsccaSm3_Safo_Hash_PreLoad) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_PreLoad(uint32_t *workArea); + +#endif /* MCUXCLOSCCASM3_CORE_SM3_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal.h new file mode 100644 index 000000000..2f7af128d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal.h @@ -0,0 +1,62 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_Internal.h + * @brief Definitions and declarations of the *INTERNAL* layer of the + * @ref mcuxClOsccaSm3 component + */ + +#ifndef MCUXCLOSCCASM3_INTERNAL_H_ +#define MCUXCLOSCCASM3_INTERNAL_H_ + +#include +#include +#include +#include +#include +#include +#ifdef MCUXCL_FEATURE_HASH_HW_SM3 +#include +#endif /* MCUXCL_FEATURE_HASH_HW_SM3 */ + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClOsccaSm3_Internal mcuxClOsccaSm3_Internal + * @brief Defines all internal of @ref mcuxClOsccaSm3 component + * @ingroup mcuxClOsccaSm3 + * @{ + */ +#define MCUXCLOSCCASM3_WACPU_SIZE_SM3 (128u) + +#define MCUXCLOSCCASM3_BLOCK_SIZE_SM3 (64U) ///< SM3 block size: 512 bit (64 bytes) + +#define MCUXCLOSCCASM3_STATE_SIZE_SM3 (32U) ///< SM3 state size: 256 bit (32 bytes) + +#define MCUXCLOSCCASM3_COUNTER_SIZE_SM3 (8U) ///< Counter size for SM3 padding + +#define MCUXCLOSCCASM3_CONTEXT_SIZE_SM3 (sizeof(mcuxClHash_ContextDescriptor_t) + MCUXCLOSCCASM3_BLOCK_SIZE_SM3 + MCUXCLOSCCASM3_STATE_SIZE_SM3) ///< Context size for SM3 mulit-part + +/**********************************************************/ +/* Internal APIs of mcuxClOsccaSm3 */ +/**********************************************************/ +/** + * @defgroup mcuxClOsccaSm3_Internal_Functions mcuxClOsccaSm3_Internal_Functions + * @brief Defines all internal functions of @ref mcuxClOsccaSm3 component + * @ingroup mcuxClOsccaSm3 + * @{ + */ +/**@}*/ + +#endif /* MCUXCLOSCCASM3_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal_sm3.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal_sm3.h new file mode 100644 index 000000000..895dcbfcf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_Internal_sm3.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_Internal_sm3.h + * @brief Internal definitions and declarations of the *INTERNAL* layer dedicated to OSCCA SM3 + */ + +#ifndef MCUXCLOSCCASM3_INTERNAL_SM3_H_ +#define MCUXCLOSCCASM3_INTERNAL_SM3_H_ + +#include // Exported features flags header +#include + +/********************************************************** + * Type declarations + **********************************************************/ +/** \brief Definition of HW SM3 message size for the mcuxClOscca_SM3_*_Sgi function in bytes */ +#define MCUXCLOSCCASM3_SGI_LOOP_SIZE ( 8U ) + +#endif /* MCUXCLOSCCASM3_INTERNAL_SM3_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_SfrAccess.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_SfrAccess.h new file mode 100644 index 000000000..1e7260236 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/internal/mcuxClOsccaSm3_SfrAccess.h @@ -0,0 +1,79 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_SfrAccess.h + * @brief Provide macros for mcuxClOsccaSm3 internal use. + * This header declares internal macros to deduplicate code and support for internal use only. */ + +#ifndef MCUXCLOSCCASM3_SFRACCESS_H_ +#define MCUXCLOSCCASM3_SFRACCESS_H_ + +#include // Exported features flags header +#include +#include +#include + + +/**** ****/ +/**** SAFO SM3 Hardware Abstraction Layer ****/ +/**** ****/ + +/** + * Definitions for accessing SAFO SM3 SFRs via, e.g., ID_SAFO_SGI->STATUS. + */ + +/** Helper macros for constructing SFR field name constants */ +#define MCUXCLOSCCASM3_SAFO_SGI_PASTE(a,b) a ## b +#define MCUXCLOSCCASM3_SAFO_SGI_CONCAT(a,b) MCUXCLOSCCASM3_SAFO_SGI_PASTE(a,b) +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD(prefix,sfr,field) MCUXCLOSCCASM3_SAFO_SGI_CONCAT(prefix, sfr ## _ ## field) + +/** Helper macros to get the mask and shift values for a specific SAFO SM3 SFR field */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, field) MCUXCLOSCCASM3_SAFO_SGI_CONCAT(MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD(SAFO_SFR_PREFIX,sfr,field), _MASK) +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_SHIFT(sfr, field) MCUXCLOSCCASM3_SAFO_SGI_CONCAT(MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD(SAFO_SFR_PREFIX,sfr,field), _SHIFT) +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(sfr, field, val) (MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD(SAFO_SFR_PREFIX,sfr,field) (val)) + +/**********************************************************/ +/* Helper macros for SAFO SM3 SFR access */ +/**********************************************************/ + +/** Read from SAFO SM3 SFR */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(sfr) (SAFO_SFR_BASE->SAFO_SFR_NAME(sfr)) + +/** Write to SAFO SM3 SFR */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(sfr, value) \ + do{ SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) = (value); } while(false) + +/** Read from SAFO SM3 SFR bit field */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_BITREAD(sfr, bit) \ + ((SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) & MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, bit)) >> MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_SHIFT(sfr, bit)) + +/** Set bit field of SAFO SM3 SFR (read-modify-write) */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_BITSET(sfr, bit) \ + do{ SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) |= MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, bit); } while(false) + +/** Clear bit field of SAFO SM3 SFR (read-modify-write) */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_BITCLEAR(sfr, bit) \ + do{ SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, bit)); } while(false) + +/** Set value of multi-bit field of SAFO SM3 SFR (read-modify-write) */ +#define MCUXCLOSCCASM3_SAFO_SGI_SFR_BITVALSET(sfr, bit, val) \ + do{ uint32_t temp = SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, bit)); \ + SAFO_SFR_BASE->SAFO_SFR_NAME(sfr) = ((val) << MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_SHIFT(sfr, bit)) & MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(sfr, bit); \ + } while(false) + +/**** ------------------------------ ****/ + +/** Sets SAFO_SGI_SM3_FIFO input buffer from the input value*/ +#define MCUXCLOSCCASM3_SET_FIFO_FIELD(value) MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_FIFO, (value)) + +#endif /* MCUXCLOSCCASM3_SFRACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3.h new file mode 100644 index 000000000..a659fd8d1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3.h @@ -0,0 +1,50 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3.h + * @brief Top-level include file for the @ref mcuxClOsccaSm3 component + * + * This includes headers for all of the functionality provided by the @ref mcuxClOsccaSm3 component. + * + * @defgroup mcuxClOsccaSm3 mcuxClOsccaSm3 + * @brief Hash component + * + * The mcuxClOsccaSm3 component implements the Hash functionality supported by CLNS. + * + * An example of how to use the @ref mcuxClOsccaSm3 component can be found in /mcuxClOsccaSm3/ex. + * + * The @ref mcuxClOsccaSm3 component supports interfaces to either hash a message in one shot + * (mcuxClOsccaSm3_compute) or to hash it in parts (mcuxClOsccaSm3_init, mcuxClOsccaSm3_process, + * and mcuxClOsccaSm3_finish). In case of hashing a message in parts, first an initialization + * has to be performed (mcuxClOsccaSm3_init), followed by zero, one, or multiple updates + * (mcuxClOsccaSm3_process), followed by a finalization (mcuxClOsccaSm3_finish). The finalization + * generates the output data (digest) and destroys the context. After the finalization step, + * no further updates are possible. + * + * The targeted hash algorithm is selected by passing one of the offered algorithm mode + * descriptors (@ref mcuxClOsccaSm3_Modes), which are listed in file mcuxClOsccaSm3_Algorithms.h + * + * Note: In case the hashing functionality is based on a hardware co-processor, it might + * be necessary to initialize the co-processor, before it's use in the @ref mcuxClOsccaSm3 + * component. Please refer to the example for further information on this. + * + * */ + +#ifndef MCUXCLOSCCASM3_H_ +#define MCUXCLOSCCASM3_H_ + +#include +#include +#include + +#endif /* MCUXCLOSCCASM3_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Algorithms.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Algorithms.h new file mode 100644 index 000000000..2753dfb96 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Algorithms.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_Algorithms.h + * @brief Algorithm/mode definitions for the mcuxClOsccaSm3 component + */ + +#ifndef MCUXCLOSCCASM3_ALGORITHMS_H_ +#define MCUXCLOSCCASM3_ALGORITHMS_H_ + +#include +#include + +/** +* @defgroup mcuxClOsccaSm3_Modes mcuxClOsccaSm3_Modes +* @brief Hashing modes of the @ref mcuxClOsccaSm3 component +* @ingroup mcuxClOsccaSm3_Constants +* @{ +*/ + +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user / customer. Hence, it is declared but never referenced. ") + +#if defined(MCUXCL_FEATURE_HASH_HW_SM3) +/** + * @brief SM3 algorithm descriptor + * SM3 hash calculation using the Hash functionality OSCCA SM3. + */ +extern const mcuxClHash_AlgorithmDescriptor_t mcuxClOsccaSm3_AlgorithmDescriptor_Sm3; + +/** + * @brief SM3 algorithm descriptor + * SM3 hash calculation using the Hash functionality OSCCA SM3. + */ +static mcuxClHash_Algo_t mcuxClOsccaSm3_Algorithm_Sm3 = &mcuxClOsccaSm3_AlgorithmDescriptor_Sm3; + +#endif /* MCUXCL_FEATURE_HASH_HW_SM3 */ + +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +/**@}*/ + +#endif /* MCUXCLOSCCASM3_ALGORITHMS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Constants.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Constants.h new file mode 100644 index 000000000..9a4a1a664 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_Constants.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClOsccaSm3_Constants.h + * @brief Constants for use with the mcuxClOsccaSm3 component */ + +#ifndef MCUXCLOSCCASM3_CONSTANTS_H_ +#define MCUXCLOSCCASM3_CONSTANTS_H_ + +/** + * @defgroup MCUXCLOSCCASM3_OUTPUT_SIZE_ MCUXCLOSCCASM3_OUTPUT_SIZE_ + * @brief Defines for digest sizes + * @ingroup mcuxClOsccaSm3_Constants + * @{ + */ +#define MCUXCLOSCCASM3_OUTPUT_SIZE_SM3 (32U) ///< SM3 output size: 256 bit (32 bytes) +/**@}*/ + +/**@}*/ + +#endif /* MCUXCLOSCCASM3_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_MemoryConsumption.h new file mode 100644 index 000000000..9e2601f1b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/inc/mcuxClOsccaSm3_MemoryConsumption.h @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClOsccaSm3_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClOsccaSm3 component + */ + +#ifndef MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_ +#define MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_ + +/** + * @defgroup MCUXCLOSCCASM3_WA MCUXCLOSCCASM3_WA + * @brief Definitions of workarea sizes for the mcuxClOsccaSm3 functions. + * @ingroup mcuxClOsccaSm3_Constants + * @{ + */ + +/****************************************************************************/ +/* Definitions of workarea buffer sizes for the mcuxClOsccaSm3 functions. */ +/****************************************************************************/ +#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_SM3 (160u) ///< Defines the workarea size required for mcuxClOsccaSm3_compute on SM3 +#define MCUXCLOSCCASM3_COMPUTE_CPU_WA_BUFFER_SIZE_MAX (160u) ///< Defines the max workarea size required for mcuxClOsccaSm3_compute + + +#define MCUXCLOSCCASM3_INIT_CPU_WA_BUFFER_SIZE (0u) ///< Defines the max workarea size required for mcuxClOsccaSm3_init + +#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_SM3 (32u) ///< Defines the workarea size required for mcuxClOsccaSm3_process on SM3 +#define MCUXCLOSCCASM3_PROCESS_CPU_WA_BUFFER_SIZE_MAX (32u) ///< Defines the max workarea size required for mcuxClOsccaSm3_process + +#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_SM3 (64u) ///< Defines the workarea size required for mcuxClOsccaSm3_finish on SM3 +#define MCUXCLOSCCASM3_FINISH_CPU_WA_BUFFER_SIZE_MAX (64u) ///< Defines the max workarea size required for mcuxClOsccaSm3_finish + +#define MCUXCLOSCCASM3_MAX_CPU_WA_BUFFER_SIZE (160u) ///< Defines the max workarea size required this component + +/** @} */ + +/** + * @defgroup MCUXCLOSCCASM3_CONTEXT MCUXCLOSCCASM3_CONTEXT + * @brief Definitions of context sizes for the mcuxClOsccaSm3 multi-part functions. + * @ingroup mcuxClOsccaSm3_Constants + * @{ + */ + +/****************************************************************************/ +/* Definitions of context sizes for the mcuxClOsccaSm3 multi-part functions. */ +/****************************************************************************/ + +#define MCUXCLOSCCASM3_CONTEXT_SIZE (120u) +#define MCUXCLOSCCASM3_CONTEXT_SIZE_IN_WORDS (120u / sizeof(uint32_t)) ///< Defines the context size for streaming hashing interfaces + +/********************************************************************************************/ +/* Definitions of state buffer sizes for mcuxClHash_export_state and mcuxClHash_import_state */ +/********************************************************************************************/ + +#define MCUXCLOSCCASM3_EXPORT_IMPORT_CPU_WA_BUFFER_SIZE (40u) ///< Defines the state size required for SM3 + +/** + * @} + */ /* mcuxClOsccaSm3_MemoryConsumption */ + +#endif /* MCUXCLOSCCASM3_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_core_sm3.c b/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_core_sm3.c new file mode 100644 index 000000000..6ba94e2ae --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_core_sm3.c @@ -0,0 +1,236 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +static void mcuxClOsccaSm3_SafoWaitforFinish(void) +{ + do{ + + } while(0u != MCUXCLOSCCASM3_SAFO_SGI_SFR_BITREAD(STATUS, BUSY)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_Safo_Hash_PreLoad) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_PreLoad(uint32_t *workArea) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_Safo_Hash_PreLoad); + uint32_t i; + + //step1:Setup the SM3 control SFRs for Loading partial HASH into SGI + //SM3_MODE = 1'b1 (AUTO mode) + //SM3_LOW_LIM = 4'b0000 + //SM3_HIGH_LIM = 4'b1111 + //SM3_COUNT_EN = 1'b0 + //HASH_RELOAD =1'b1 + //SM3_STOP = 1'b0 + //NO_AUTO_INIT = 1'b1 + //SM3_EN = 1'b1 + //SM3_SGI_SM3_CTRL =0x0001AF02; + uint32_t sgi_sm3_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_MODE, 1u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_LOW_LIM, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_HIGH_LIM, 15u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_COUNT_EN, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, HASH_RELOAD, 1u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_STOP, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, NO_AUTO_INIT, 1u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_EN, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_CTRL, sgi_sm3_ctrl); + + //Step2:Setup the SGI Control SFRs + // START = 1'b1 + //CRYPTO_OP = 3'b111 + //DATOUT_RES = 2'b00 (END_UP) + //SM3_SGI_CTRL = 0x00000071; + uint32_t sgi_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(CTRL,START) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, CRYPTO_OP, 7u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, DATOUT_RES, 0u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL, sgi_ctrl); + + uint32_t sgi_ctrl2 = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(CTRL2); + sgi_ctrl2 &= ~MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL2, BYTES_ORDER, 1); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL2, sgi_ctrl2); + + //Step3: Load partial Hash + for(i=0u;i<=7u;i++) + { + /* MISRA Ex. 12 - Rule 11.8 */ + MCUXCLOSCCASM3_SET_FIFO_FIELD(0u); + } + for(i=8u;i<=15u;i++) + { + /* MISRA Ex. 12 - Rule 11.8 */ + MCUXCLOSCCASM3_SET_FIFO_FIELD(workArea[15u - ((i) & 15u)]); + } + + //Step4:Configure SGI_SM3_CTRL SFRs to stop AUTO mode + // SM3_STOP = 1'b1 + sgi_sm3_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(SM3_CTRL); + sgi_sm3_ctrl |= MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_STOP, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_CTRL, sgi_sm3_ctrl); + + //Step5:Wait for the SM3 operation to complete + mcuxClOsccaSm3_SafoWaitforFinish(); + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaSm3_Safo_Hash_PreLoad); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_Safo_Hash_Norm) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_Norm(uint32_t *workArea, uint32_t *data) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_Safo_Hash_Norm); + + //step1:Setup the SM3 control SFRs + //SM3_MODE = 1'b0 (NORM mode) + //SM3_LOW_LIM = 4'b0000 + //SM3_HIGH_LIM = 4'b1111 + //SM3_COUNT_EN = 1'b0 + //SM3_STOP = 1'b0 + //NO_AUTO_INIT = 1'b0 + //SM3_EN = 1'b1 + uint32_t sgi_sm3_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_MODE, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_LOW_LIM, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_HIGH_LIM, 15u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_COUNT_EN, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_STOP, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, NO_AUTO_INIT, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_EN, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_CTRL, sgi_sm3_ctrl); + + //Step2:Load message into SFRs + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN0A, data[15]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN0B, data[14]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN0C, data[13]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN0D, data[12]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN1A, data[11]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN1B, data[10]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN1C, data[9]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(DATIN1D, data[8]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY0A, data[7]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY0B, data[6]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY0C, data[5]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY0D, data[4]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY1A, data[3]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY1B, data[2]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY1C, data[1]); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(KEY1D, data[0]); + + //Step3:Setup the SGI control SRFs + // START = 1'b1 + //CRYPTO_OP = 3'b111 + //DATOUT_RES = 2'b00 (END_UP) + //SM3_SGI_CTRL = 0x00000070; + uint32_t sgi_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(CTRL,START) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, CRYPTO_OP, 7u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, DATOUT_RES, 0u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL, sgi_ctrl); + + //Step4:Wait for the SM3 operation to complete + mcuxClOsccaSm3_SafoWaitforFinish(); + workArea[0] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTA); + workArea[1] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTB); + workArea[2] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTC); + workArea[3] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTD); + + //Step5:Set the DATOUT_RES to TRIGGER_UP mode,then get the upper 128bits output + //DATOUT_RES = 2'b10 (TRIGGER_UP) + //START = 1'b1 + sgi_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(CTRL); + sgi_ctrl |= MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, DATOUT_RES, 2u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL, sgi_ctrl); + + mcuxClOsccaSm3_SafoWaitforFinish(); + workArea[4] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTA); + workArea[5] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTB); + workArea[6] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTC); + workArea[7] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTD); + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaSm3_Safo_Hash_Norm); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_Safo_Hash_Auto) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_Safo_Hash_Auto(uint32_t *workArea, uint32_t *data) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_Safo_Hash_Auto); + + //step1:Setup the SM3 control SFRs + //SM3_MODE = 1'b1 (AUTO mode) + //SM3_LOW_LIM = 4'b0000 + //SM3_HIGH_LIM = 4'b1111 + //SM3_COUNT_EN = 1'b0 + //HASH_RELOAD =1'b0 + //SM3_STOP = 1'b0 + //NO_AUTO_INIT = 1'b1 + //SM3_EN = 1'b1 + //SM3_SGI_SM3_CTRL =0x00018F02; + uint32_t sgi_sm3_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_MODE, 1u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_LOW_LIM, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_HIGH_LIM, 15u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_COUNT_EN, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, HASH_RELOAD, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_STOP, 0u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, NO_AUTO_INIT, 1u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_EN, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_CTRL, sgi_sm3_ctrl); + + //Step2:Setup the SGI Control SFRs + // START = 1'b1 + //CRYPTO_OP = 3'b111 + //DATOUT_RES = 2'b00 (END_UP) + //SM3_SGI_CTRL = 0x00000071; + uint32_t sgi_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_MASK(CTRL,START) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, CRYPTO_OP, 7u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, DATOUT_RES, 0u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL, sgi_ctrl); + + //Step3:Load message into SGI_SM3_FIFO SFRs + for(uint32_t i=0u;i<=15u;i++) + { + /* MISRA Ex. 12 - Rule 11.8 */ + MCUXCLOSCCASM3_SET_FIFO_FIELD(data[15u - ((i) & 15u)]); + } + + //Step4:Configure SGI_SM3_CTRL SFRs to stop AUTO mode + // SM3_STOP = 1'b1 + sgi_sm3_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(SM3_CTRL); + sgi_sm3_ctrl |= MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(SM3_CTRL, SM3_STOP, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(SM3_CTRL, sgi_sm3_ctrl); + + //Step5:Wait for the SM3 operation to complete + mcuxClOsccaSm3_SafoWaitforFinish(); + workArea[0] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTA); + workArea[1] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTB); + workArea[2] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTC); + workArea[3] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTD); + + //Step6:Set the DATOUT_RES to TRIGGER_UP mode,then get the upper 128bits output + //DATOUT_RES = 2'b10 (TRIGGER_UP) + //START = 1'b1 + sgi_ctrl = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(CTRL); + sgi_ctrl |= MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, DATOUT_RES, 2u) + | MCUXCLOSCCASM3_SAFO_SGI_SFR_FIELD_FORMAT(CTRL, START, 1u); + MCUXCLOSCCASM3_SAFO_SGI_SFR_WRITE(CTRL, sgi_ctrl); + + mcuxClOsccaSm3_SafoWaitforFinish(); + workArea[4] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTA); + workArea[5] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTB); + workArea[6] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTC); + workArea[7] = MCUXCLOSCCASM3_SAFO_SGI_SFR_READ(DATOUTD); + + /* update SC and return */ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaSm3_Safo_Hash_Auto); +} diff --git a/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_internal_sm3.c b/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_internal_sm3.c new file mode 100644 index 000000000..fceffb955 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClOsccaSm3/src/mcuxClOsccaSm3_internal_sm3.c @@ -0,0 +1,393 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const uint32_t gkmcuxClOsccaSm3_SM3_IV[8] = {0xb0fb0e4eU, + 0xe38dee4dU, + 0x163138aaU, + 0xa96f30bcU, + 0xda8a0600U, + 0x172442d7U, + 0x4914b2b9U, + 0x7380166fU}; + +/********************************************************** + * Helper functions + **********************************************************/ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi) +static MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(uint32_t *workArea, uint32_t *stateBuff) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi); + + for(uint32_t i = 0; i < MCUXCLOSCCASM3_SGI_LOOP_SIZE; i++) + { + workArea[i] = (uint32_t)stateBuff[i]; + } + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_Safo_Hash_PreLoad(workArea)); + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_Safo_Hash_PreLoad)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_ProcessMessageBlock_Sgi) +static MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClOsccaSm3_ProcessMessageBlock_Sgi(uint32_t *workArea, uint32_t *stateBuff, uint32_t *pInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_ProcessMessageBlock_Sgi); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_Safo_Hash_Auto(workArea, pInput)); + + for(uint32_t i = 0u; i < MCUXCLOSCCASM3_SGI_LOOP_SIZE; i++) + { + stateBuff[i] = (uint32_t)workArea[i]; + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi, MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_Safo_Hash_Auto)); +} + +/********************************************************** + * *INTERNAL* layer functions + **********************************************************/ + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_sm3_oneShotSkeleton, mcuxClHash_AlgoSkeleton_OneShot_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClOsccaSm3_sm3_oneShotSkeleton ( + mcuxClSession_Handle_t session, + mcuxClHash_Algo_t algorithm, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_sm3_oneShotSkeleton); + + uint8_t *stateBuffer = NULL; + /* MISRA Ex. 9 to Rule 11.3 */ + stateBuffer = (uint8_t*)mcuxClSession_allocateWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + if(NULL == stateBuffer) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_oneShotSkeleton, MCUXCLHASH_STATUS_FAILURE); + } + uint8_t *accumulationBuffer = NULL; + /* MISRA Ex. 9 to Rule 11.3 */ + accumulationBuffer = (uint8_t*)mcuxClSession_allocateWords_cpuWa(session, MCUXCLOSCCASM3_BLOCK_SIZE_SM3 / sizeof(uint32_t)); + if(NULL == accumulationBuffer) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_oneShotSkeleton, MCUXCLHASH_STATUS_FAILURE); + } + uint32_t *workArea = NULL; + /* MISRA Ex. 9 to Rule 11.3 */ + workArea = mcuxClSession_allocateWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + if(NULL == workArea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_oneShotSkeleton, MCUXCLHASH_STATUS_FAILURE); + } + + /************************************************************************************** + * Step 1: Initialize SAFO to perform Hash operation + **************************************************************************************/ + + /** \brief Global standard initialization vectors for SM3 */ + MCUXCLMEMORY_FP_MEMORY_COPY(stateBuffer, (const uint8_t*)gkmcuxClOsccaSm3_SM3_IV, MCUXCLOSCCASM3_STATE_SIZE_SM3); + + //Load initial IV to HW SM3 + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)stateBuffer)); + + /************************************************************************************** + * Step 2: Process full blocks of input data + **************************************************************************************/ + uint32_t inputLen = inSize; + uint32_t updateLoopCount = 0u; //for flow protection + const uint8_t *pInput = pIn; + while((0U != inputLen) && (inputLen >= MCUXCLOSCCASM3_BLOCK_SIZE_SM3)) + { + MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(accumulationBuffer, pInput, MCUXCLOSCCASM3_BLOCK_SIZE_SM3); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)stateBuffer, (uint32_t *)accumulationBuffer)); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)stateBuffer)); + + pInput += MCUXCLOSCCASM3_BLOCK_SIZE_SM3; + inputLen -= MCUXCLOSCCASM3_BLOCK_SIZE_SM3; + updateLoopCount++; + } + + /************************************************************************************** + * Step 3: Pad the input data and process last block + **************************************************************************************/ + if(0U != inputLen) + { + MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(&accumulationBuffer[MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - inputLen], pInput, inputLen); + } + + /* get the accumulation buffer index */ + uint32_t accumulationBufferIndex = inSize & (MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - 1U); + + /* Padding the last block, it's big endian */ + /* Set the first byte to 0x80*/ + accumulationBuffer[(MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - 1U) - (accumulationBufferIndex)] = (uint8_t) (0x80U); + accumulationBufferIndex++; + + /* then fill with zeros */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(accumulationBuffer, MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - accumulationBufferIndex); + + /* check if we can put the byte counter into this block */ + if((accumulationBufferIndex + 8U ) > MCUXCLOSCCASM3_BLOCK_SIZE_SM3) + { + /* need another block */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)stateBuffer, (uint32_t *)accumulationBuffer)); + MCUXCLMEMORY_FP_MEMORY_CLEAR(accumulationBuffer,MCUXCLOSCCASM3_BLOCK_SIZE_SM3); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)stateBuffer)); + } + + /* Perform padding by adding data counter - length is added from end of the array; byte-length is converted to bit-length */ + accumulationBuffer[0u] = (uint8_t)(inSize << 3u); + accumulationBuffer[1u] = (uint8_t)(inSize >> 5u); + accumulationBuffer[2u] = (uint8_t)(inSize >> 13u); + accumulationBuffer[3u] = (uint8_t)(inSize >> 21u); + accumulationBuffer[4u] = (uint8_t)(inSize >> 29u); + + /* Process the data in the accumulation buffer */ + /* Return code will be handled by Exit-Gate functionality within processMessageBlock */ + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)stateBuffer, (uint32_t *)accumulationBuffer)); + + /************************************************************************************** + * Step 4: Copy result to output buffers + **************************************************************************************/ + MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pOut, stateBuffer, algorithm->hashSize); + + mcuxClSession_freeWords_cpuWa(session, (MCUXCLOSCCASM3_BLOCK_SIZE_SM3 + 2u * MCUXCLOSCCASM3_STATE_SIZE_SM3) / sizeof(uint32_t)); + *pOutSize = algorithm->hashSize; + /* Check the security counter value and the return code */ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClOsccaSm3_sm3_oneShotSkeleton, MCUXCLHASH_STATUS_OK, MCUXCLHASH_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi), + updateLoopCount * (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi)), + (0U != inputLen ? 1u : 0u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi), + ((accumulationBufferIndex + 8U ) > MCUXCLOSCCASM3_BLOCK_SIZE_SM3 ? 1u : 0u) * + (MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_sm3_processSkeleton, mcuxClHash_AlgoSkeleton_Process_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClOsccaSm3_sm3_processSkeleton ( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_InputBuffer_t pIn, + uint32_t inSize) +{ + mcuxClHash_Context_t pSM3Ctx = pContext; + int32_t processedLengthNotZero = mcuxClHash_processedLength_cmp(pSM3Ctx->processedLength, 0, 0); + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_sm3_processSkeleton, + (((processedLengthNotZero == 0) && (pContext->unprocessedLength == 0u)) ? (uint32_t)1u : (uint32_t)0u) + * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi)); + + /* Retrieve buffer information */ + uint32_t *workArea = (uint32_t*)mcuxClSession_allocateWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + if(NULL == workArea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_processSkeleton, MCUXCLHASH_STATUS_FAILURE); + } + + /************************************************************************************** + * Step 1: Initialization - Calculate sizes, set pointers, and set initial IV, + continuation from external state, or from internal state + **************************************************************************************/ + /* MISRA Ex. 9 to Rule 11.3 */ + uint8_t *pInput = (uint8_t *)pIn; + uint32_t inLength = inSize; + uint8_t *pUnprocessed = (uint8_t *)mcuxClHash_getUnprocessedPtr(pSM3Ctx); + uint8_t *pState = (uint8_t *)mcuxClHash_getStatePtr(pSM3Ctx); + const size_t algoBlockSize = MCUXCLOSCCASM3_BLOCK_SIZE_SM3; + + /* Initialize state with IV */ + if((processedLengthNotZero == 0) && (pSM3Ctx->unprocessedLength == 0u)) + { + /** \brief Global standard initialization vectors for SM3 */ + MCUXCLMEMORY_FP_MEMORY_COPY(pState, (const uint8_t*)gkmcuxClOsccaSm3_SM3_IV, MCUXCLOSCCASM3_STATE_SIZE_SM3); + + } + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)pState)); + + /**************************************************************************************/ + /* Process all whole blocks of input data */ + /**************************************************************************************/ + uint32_t loopTimes = 0u; + uint32_t loopTimes1 = 0u; + while(0u < inLength) + { + /* Take into account something might be already in unprocessed buffer */ + uint32_t dataToCopyLength = (inLength < (algoBlockSize - pSM3Ctx->unprocessedLength)) ? inLength : (algoBlockSize - pSM3Ctx->unprocessedLength); + /* Copy input to accumulation buffer */ + /* Copy input to accumulation buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pUnprocessed + algoBlockSize - pSM3Ctx->unprocessedLength - dataToCopyLength, pInput, dataToCopyLength); + + /* Update counter / pSM3Ctx data / input pointer */ + inLength -= dataToCopyLength; + pInput += dataToCopyLength; + pSM3Ctx->unprocessedLength += dataToCopyLength; + loopTimes++; + /* When whole unprocessed buffer filled, process block and update pSM3Ctx data*/ + if(pSM3Ctx->unprocessedLength == algoBlockSize) + { + /* Switch endianess in accumulation buffer */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)pState, (uint32_t *)pUnprocessed)); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)pState)); + + /*Data processed, nothing in the buffer, state buffer updated*/ + pSM3Ctx->unprocessedLength = 0u; + /* Update byteCounter by adding algoBlockSize to it */ + mcuxClHash_processedLength_add(pSM3Ctx->processedLength, algoBlockSize); + loopTimes1++; + } + } + + /**************************************************************************************/ + /* Exit + FP balancing */ + /**************************************************************************************/ + /* Recover session info */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_processSkeleton, MCUXCLHASH_STATUS_OK, + loopTimes * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed), + loopTimes1 * ( MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi))); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClOsccaSm3_sm3_finishSkeleton, mcuxClHash_AlgoSkeleton_Finish_t) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClHash_Status_t) mcuxClOsccaSm3_sm3_finishSkeleton ( + mcuxClSession_Handle_t session, + mcuxClHash_Context_t pContext, + mcuxCl_Buffer_t pOut, + uint32_t *const pOutSize + ) +{ + mcuxClHash_Context_t pSM3Ctx = pContext; + int32_t processedLengthNotZero = mcuxClHash_processedLength_cmp(pSM3Ctx->processedLength, 0, 0); + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClOsccaSm3_sm3_finishSkeleton, + ((((processedLengthNotZero == 0) && (pSM3Ctx->unprocessedLength == 0u)) ? (uint32_t)1u : (uint32_t)0u) + * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi)); + + /* No further input to be added, processedLength can be updated now. Will be used for final length value attached inside padding */ + /* Retrieve buffer information */ + uint32_t *workArea = (uint32_t*)mcuxClSession_allocateWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + if(NULL == workArea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_finishSkeleton, MCUXCLHASH_STATUS_FAILURE); + } + + uint8_t *pState = (uint8_t *)mcuxClHash_getStatePtr(pSM3Ctx); + /* Initialize state with IV */ + if((processedLengthNotZero == 0) && (pSM3Ctx->unprocessedLength == 0u)) + { + /** \brief Global standard initialization vectors for SM3 */ + MCUXCLMEMORY_FP_MEMORY_COPY(pState, (const uint8_t*)gkmcuxClOsccaSm3_SM3_IV, MCUXCLOSCCASM3_STATE_SIZE_SM3); + } + + /* need preload Update phase prehash into HW SM3 */ + /* MISRA Ex. 9 to Rule 11.3 - re-interpreting the memory */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)pState)); + + mcuxClHash_processedLength_add(pSM3Ctx->processedLength, pSM3Ctx->unprocessedLength); + + uint8_t *pUnprocessed = (uint8_t *)mcuxClHash_getUnprocessedPtr(pSM3Ctx); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("the max value of pSM3Ctx->unprocessedLength is MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - 1U.") + pUnprocessed[(MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - 1U) - (pSM3Ctx->unprocessedLength)] = 0x80u; //set first bit of padding + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + pSM3Ctx->unprocessedLength++; + + uint32_t remainingBlockLength = MCUXCLOSCCASM3_BLOCK_SIZE_SM3 - (pSM3Ctx->unprocessedLength); + uint32_t loopTimes = 0U; + if(MCUXCLOSCCASM3_COUNTER_SIZE_SM3 > remainingBlockLength) // need room for 64 bit counter + { + loopTimes++; + /* Set remaining bytes in accumulation buffer to zero */ + MCUXCLMEMORY_FP_MEMORY_SET(pUnprocessed, 0x00u, remainingBlockLength); + + /* Call core function */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)pState, (uint32_t *)pUnprocessed)); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi(workArea, (uint32_t *)pState)); + + remainingBlockLength = MCUXCLOSCCASM3_BLOCK_SIZE_SM3; + pSM3Ctx->unprocessedLength = 0u; + } + + /* Set remaining bytes in accumulation buffer to zero */ + MCUXCLMEMORY_FP_MEMORY_SET(pUnprocessed, 0x00u, remainingBlockLength); + + /* Perform padding by adding data counter - length is added from start of the array; byte-length is converted to bit-length */ + pUnprocessed[0u] = (uint8_t)(pSM3Ctx->processedLength[0] << 3u); + pUnprocessed[1u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 5u); + pUnprocessed[2u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 13u); + pUnprocessed[3u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 21u); + pUnprocessed[4u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 29u); + pUnprocessed[5u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 37u); + pUnprocessed[6u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 45u); + pUnprocessed[7u] = (uint8_t)(pSM3Ctx->processedLength[0] >> 53u); + + /* Call core function to process last block */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClOsccaSm3_ProcessMessageBlock_Sgi(workArea, (uint32_t *)pState, (uint32_t *)pUnprocessed)); + + /* Switch endianess of words in state buffer */ + /* Copy hash digest to output buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY_REVERSED(pOut, pState, MCUXCLOSCCASM3_OUTPUT_SIZE_SM3); + *pOutSize += pSM3Ctx->algo->hashSize; + + /* Recover session info */ + mcuxClSession_freeWords_cpuWa(session, MCUXCLOSCCASM3_STATE_SIZE_SM3 / sizeof(uint32_t)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClOsccaSm3_sm3_finishSkeleton, MCUXCLHASH_STATUS_OK, + loopTimes * ( MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi) + + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_SetMessagePreLoadIV_Sgi)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_ProcessMessageBlock_Sgi), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy_reversed)); + +} + +/********************************************************** + * Algorithm descriptor implementations + **********************************************************/ + +#ifdef MCUXCL_FEATURE_HASH_HW_SM3 +const mcuxClHash_AlgorithmDescriptor_t mcuxClOsccaSm3_AlgorithmDescriptor_Sm3 = { + .oneShotSkeleton = mcuxClOsccaSm3_sm3_oneShotSkeleton, + .protection_token_oneShotSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_sm3_oneShotSkeleton), + .processSkeleton = mcuxClOsccaSm3_sm3_processSkeleton, + .protection_token_processSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_sm3_processSkeleton), + .finishSkeleton = mcuxClOsccaSm3_sm3_finishSkeleton, + .protection_token_finishSkeleton = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClOsccaSm3_sm3_finishSkeleton), + .blockSize = MCUXCLOSCCASM3_BLOCK_SIZE_SM3, + .hashSize = MCUXCLOSCCASM3_OUTPUT_SIZE_SM3, + .stateSize = MCUXCLOSCCASM3_STATE_SIZE_SM3, + .counterSize = MCUXCLOSCCASM3_COUNTER_SIZE_SM3, +}; +#endif /* MCUXCL_FEATURE_HASH_HW_SM3 */ diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Functions_Internal.h b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Functions_Internal.h new file mode 100644 index 000000000..147166499 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Functions_Internal.h @@ -0,0 +1,228 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPadding_Functions_Internal.h + * @brief Functions of the padding component. + */ + +#ifndef MCUXCLPADDING_FUNCTIONS_INTERNAL_H +#define MCUXCLPADDING_FUNCTIONS_INTERNAL_H + +#include // Exported features flags header + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +/** + * @brief No-padding function, which adds no padding at all + * @api + * + * This function throws an error if @p lastBlockLength is anything other than zero, + * and does nothing (adding no padding) and returns OK otherwise. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes + * in @p pIn. Must be 0. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_None, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_None( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); + + +/** + * @brief Zero-padding function, which pads a block with zeroes in the end. + * @api + * + * This function copies @p lastBlockLength bytes to @p pOut and fills the + * remainder with zeroes. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes + * in @p pIn. Must be smaller than @p blockLength. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_ISO9797_1_Method1, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_ISO9797_1_Method1( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); + +/** + * @brief ISO/IEC 9797-1 padding method 2 function. + * @api + * + * This function adds a single bit with value 1 after the data and fills the + * remaining block with zeroes. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes + * in @p pIn. Must be smaller than @p blockLength. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_ISO9797_1_Method2, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_ISO9797_1_Method2( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); + +/** + * @brief ISO/IEC 9797-1 padding method 2 function. + * @api + * + * This function adds a single bit with value 1 after the data and fills the + * remaining block with zeroes for CMAC and XCBCMAC mode using. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes + * in @p pIn. Must be smaller than or equal to @p blockLength. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_MAC_ISO9797_1_Method2( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); +/** + * @brief PKCS7 padding function. + * @api + * + * This function adds PKCS7 padding according to rfc2315, it adds the remaning + * bytes in the block with the value equal to the total number of added bytes. + * The random masking byte depends on a call to @ref mcuxClRandom_ncInit. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes + * in @p pIn. Must be smaller than @p blockLength. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_PKCS7, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_PKCS7( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); + +/** + * @brief Random-padding function, which pads a block with random bytes in the end. + * @api + * + * This function copies @p lastBlockLength bytes to @p pOut and fills the + * remainder with random bytes. + * The random bytes depend on a call to @ref mcuxClRandom_ncInit. + * + * @param[in] blockLength The block length of the used block cipher. + * + * @param[in] pIn Pointer to the input buffer of the block that will + * be padded. + * @param[in] lastBlockLength Number of bytes in the last block, i.e. the number of bytes in + * @p pIn. Must be greater than 0 and less than or equal to @p blockLength. + * @param[in] totalInputLength Total number of plaintext/ciphertext bytes. + * + * @param[out] pOut Pointer to the output buffer where the padded data + * needs to be written. + * @param[out] pOutLength Length of the data written to @p pOut, including the padding. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPadding_addPadding_Random, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_Random( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPADDING_FUNCTIONS_INTERNAL_H */ + diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Internal.h b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Internal.h new file mode 100644 index 000000000..e457595c7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Internal.h @@ -0,0 +1,24 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClPadding_Internal.h + * @brief Internal top-level header for the padding component + */ + +#ifndef MCUXCLPADDING_INTERNAL_H_ +#define MCUXCLPADDING_INTERNAL_H_ + +#include +#include + +#endif /* MCUXCLPADDING_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Types_Internal.h b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Types_Internal.h new file mode 100644 index 000000000..0d52e15d5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/internal/mcuxClPadding_Types_Internal.h @@ -0,0 +1,73 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClPadding_Types_Internal.h + * @brief Internal type definitions for the mcuxClPadding component + */ + +#ifndef MCUXCLPADDING_TYPES_INTERNAL_H_ +#define MCUXCLPADDING_TYPES_INTERNAL_H_ + +#include +#include // Exported features flags header +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Function type for a padding function + * + * A padding function padds the last block of a message. It will copy the incomplete last + * block of the message @p pIn into the output buffer @p pOut and apply padding to it. + * The function will return an error in case the input block does not meet the requirements + * for the padding mode. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPadding_addPaddingMode_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) (*mcuxClPadding_addPaddingMode_t)( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength +)); + +/** + * @brief Function type for a padding removal function + * + * A padding removal function checks and removes padding in the input @p pIn, if possible, + * and only copies the remaining bytes of the block to the output buffer @p pOut. + * The function will return an error in case the input block does not meet the requirements + * for the padding mode, or NOT_OK if the padding is incorrect. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPadding_removePaddingMode_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) (*mcuxClPadding_removePaddingMode_t)( + uint32_t blockLength, + uint8_t * const pIn, + uint32_t lastBlockLength, + uint8_t * const pOut, + uint32_t * const pOutLength +)); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPADDING_TYPES_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding.h b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding.h new file mode 100644 index 000000000..43c989c95 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding.h @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPadding.h + * @brief Top-level include file for the padding component. + */ + +#ifndef MCUXCLPADDING_H +#define MCUXCLPADDING_H + +#include +#include + +#include +#include + +#endif /* MCUXCLPADDING_H */ + diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Constants.h b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Constants.h new file mode 100644 index 000000000..959060fba --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Constants.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClPadding_Constants.h + * @brief Constants definitions for the mcuxClPadding component + */ + +#ifndef MCUXCLPADDING_CONSTANTS_H_ +#define MCUXCLPADDING_CONSTANTS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup clPadding Constants definitions + * @brief Constants used by the Padding component. + * @ingroup mcuxClPadding + * @{ + */ + +/********************************************** + * CONSTANTS + **********************************************/ + +/** + * @brief Return codes + */ +#define MCUXCLPADDING_STATUS_OK ((mcuxClPadding_Status_t) 0x0FF42E03u) ///< Padding operation successful +#define MCUXCLPADDING_STATUS_NOT_OK ((mcuxClPadding_Status_t) 0x0FF453FCu) ///< Incorrect padding +#define MCUXCLPADDING_STATUS_ERROR ((mcuxClPadding_Status_t) 0x0FF45330u) ///< Error occurred during Padding operation +#define MCUXCLPADDING_STATUS_FAULT_ATTACK ((mcuxClPadding_Status_t) 0x0FF4F0F0u) ///< Fault attack (unexpected behaviour) detected + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPADDING_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Types.h b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Types.h new file mode 100644 index 000000000..cb940acd5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/inc/mcuxClPadding_Types.h @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPadding_Types.h + * @brief Type definitions for the mcuxClPadding component + */ + + +#ifndef MCUXCLPADDING_TYPES_H_ +#define MCUXCLPADDING_TYPES_H_ + +#include +#include // Exported features flags header + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup clPaddingTypes Padding type definitions + * @brief Types used by the Padding component. + * @ingroup mcuxClPadding + * @{ + */ + + +/** + * @brief Padding status code + * + * This type provides information about the status of the Padding operation that + * has been performed. + */ +typedef uint32_t mcuxClPadding_Status_t; + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPADDING_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPadding/src/mcuxClPadding.c b/components/els_pkc/src/comps/mcuxClPadding/src/mcuxClPadding.c new file mode 100644 index 000000000..f0804214c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPadding/src/mcuxClPadding.c @@ -0,0 +1,215 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClPadding.c + * @brief implementation of padding functions for different components */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MCUXCLPADDING_ISO_PADDING_BYTE (0x80u) + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_None, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_None( + uint32_t blockLength UNUSED_PARAM, + const uint8_t * const pIn UNUSED_PARAM, + uint32_t lastBlockLength, + uint32_t totalInputLength UNUSED_PARAM, + uint8_t * const pOut UNUSED_PARAM, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_None); + + if(0u != lastBlockLength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPadding_addPadding_None, MCUXCLPADDING_STATUS_ERROR); + } + + *pOutLength = 0u; + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_None, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK); +} + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_ISO9797_1_Method1, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_ISO9797_1_Method1( +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_ISO9797_1_Method1); + + if((0u != totalInputLength) /* special case for zero-padding: add a padding block if totalInputLength is 0 */ + && (0u == lastBlockLength)) + { + /* No padding needed */ + *pOutLength = 0; + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_ISO9797_1_Method1, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK); + } + + uint32_t paddingBytes = blockLength - lastBlockLength; + + MCUXCLMEMORY_FP_MEMORY_SET(pOut + lastBlockLength, 0x00u, paddingBytes); + + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOut, pIn, lastBlockLength, blockLength); + + *pOutLength = blockLength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_ISO9797_1_Method1, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); +} + + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_ISO9797_1_Method2, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_ISO9797_1_Method2 ( +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength UNUSED_PARAM, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_ISO9797_1_Method2); + + uint8_t *pOutPtr = (uint8_t *) pOut; + + pOutPtr += lastBlockLength; + + *pOutPtr = MCUXCLPADDING_ISO_PADDING_BYTE; + pOutPtr++; + + uint32_t paddingBytes = blockLength - lastBlockLength - 1u; + + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *) pOutPtr, 0x00u, paddingBytes); + + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOut, pIn, lastBlockLength, blockLength); + + *pOutLength = blockLength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_ISO9797_1_Method2, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_MAC_ISO9797_1_Method2( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2); + if(blockLength == lastBlockLength) + { + /* No padding needed */ + *pOutLength = 0; + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(padResult, mcuxClPadding_addPadding_ISO9797_1_Method2(blockLength, pIn, lastBlockLength, totalInputLength, pOut, pOutLength)); + + if(MCUXCLPADDING_STATUS_OK != padResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2, MCUXCLPADDING_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method2)); + } + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_MAC_ISO9797_1_Method2, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPadding_addPadding_ISO9797_1_Method2)); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_PKCS7, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_PKCS7 ( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength UNUSED_PARAM, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_PKCS7); + + if((blockLength <= 1u ) || (blockLength > 255u)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPadding_addPadding_PKCS7, MCUXCLPADDING_STATUS_ERROR); + } + + uint32_t paddingBytes = blockLength - lastBlockLength; + + MCUXCLMEMORY_FP_MEMORY_SET(pOut + lastBlockLength, (uint8_t)paddingBytes, paddingBytes); + + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOut, pIn, lastBlockLength, blockLength); + + *pOutLength = blockLength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_PKCS7, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPadding_addPadding_Random, mcuxClPadding_addPaddingMode_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPadding_Status_t) mcuxClPadding_addPadding_Random( + uint32_t blockLength, + const uint8_t * const pIn, + uint32_t lastBlockLength, + uint32_t totalInputLength, + uint8_t * const pOut, + uint32_t * const pOutLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPadding_addPadding_Random); + + /* Empty input - return */ + if(0u == totalInputLength) + { + *pOutLength = 0u; + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPadding_addPadding_Random, MCUXCLPADDING_STATUS_OK); + } + + uint32_t paddingBytes = blockLength - lastBlockLength; + + if(0u != paddingBytes) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_generate, mcuxClPrng_generate(pOut + lastBlockLength, paddingBytes)); + if(MCUXCLPRNG_STATUS_OK != ret_Prng_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPadding_addPadding_Random, MCUXCLPADDING_STATUS_NOT_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_generate)); + } + } + + MCUXCLMEMORY_FP_MEMORY_COPY_WITH_BUFF(pOut, pIn, lastBlockLength, blockLength); + + *pOutLength = blockLength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClPadding_addPadding_Random, MCUXCLPADDING_STATUS_OK, MCUXCLPADDING_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_generate)); +} + diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_FupMacros.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_FupMacros.h new file mode 100644 index 000000000..f9f1f269c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_FupMacros.h @@ -0,0 +1,226 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_FupMacros.h + * @brief Macros for PKC FUP program composing + */ + + +#ifndef MCUXCLPKC_FUPMACROS_H_ +#define MCUXCLPKC_FUPMACROS_H_ + + +#include +#include +#include + + +/**********************************************************/ +/* Macros to create FUP program */ +/**********************************************************/ +/** + * @brief FUP programs data structure + */ +typedef struct mcuxClPkc_FUPEntry +{ + uint8_t CALCparam0; + uint8_t CALCparam1; + uint8_t XPTRind; + uint8_t YPTRind; + uint8_t TOPPind; + uint8_t RPTRind; +} mcuxClPkc_FUPEntry_t; + + +/** + * Macro to declare external constant FUP program. + */ +#define MCUXCLPKC_FUP_EXT_ROM_DECLARE(name) \ + extern const mcuxClPkc_FUPEntry_t name[] + +/** + * Macro to create FUP program, e.g., a FUP program with 2 entries: + * MCUXCLPKC_FUP_EXT_ROM(FupProgram1, FUP_OP1_MUL(0,1,1), FUP_OP1_MUL(1,0,0)); + */ +#define MCUXCLPKC_FUP_EXT_ROM(name, ...) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_FUP() \ + const mcuxClPkc_FUPEntry_t name[] __attribute__((aligned(4),section("PH_CL_FUP_PROGRAMS_MAGIC_AREA"))) = { __VA_ARGS__ } \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP() + +#define MCUXCLPKC_FUP_LEN(pFupProgram) ((uint8_t) ((sizeof(pFupProgram)) / 6u)) + + +/**********************************************************/ +/* Macros to pack parameters of FUP entry */ +/**********************************************************/ +/** + * Macro to pack 6 parameters: CALCparam0, CALCparam1, XPTRind, YPTRind, ZPTRind, RPTRind, + * of a PKC calculation to an entry in FUP program. + */ +#define MCUXCLPKC_FUP_PACKARGS6(calcP0, calcP1, iX, iY, iZ, iR) \ + {calcP0, calcP1, iX, iY, iZ, iR} + + +/** Helper macro to pack parameters of L0 operation (OP) with parameter set 1. */ +#define MCUXCLPKC_FUP_OP1(symbol, iR, iX, iY, iZ, repeat) MCUXCLPKC_FUP_PACKARGS6(MCUXCLPKC_PARAM_OP1 | ((repeat) & 0x0Fu), MCUXCLPKC_OP_ ## symbol, iX, iY, iZ, iR) +/** Helper macro to pack parameters of L1 microcode (MC) with parameter set 1. */ +#define MCUXCLPKC_FUP_MC1(symbol, iR, iX, iY, iZ, repeat) MCUXCLPKC_FUP_PACKARGS6(MCUXCLPKC_PARAM_MC1 | ((repeat) & 0x0Fu), MCUXCLPKC_MC_ ## symbol, iX, iY, iZ, iR) +/** Helper macro to pack parameters of L0 operation (OP) with parameter set 2. */ +#define MCUXCLPKC_FUP_OP2(symbol, iR, iX, iY, iZ, repeat) MCUXCLPKC_FUP_PACKARGS6(MCUXCLPKC_PARAM_OP2 | ((repeat) & 0x0Fu), MCUXCLPKC_OP_ ## symbol, iX, iY, iZ, iR) +/** Helper macro to pack parameters of L1 microcode (MC) with parameter set 2. */ +#define MCUXCLPKC_FUP_MC2(symbol, iR, iX, iY, iZ, repeat) MCUXCLPKC_FUP_PACKARGS6(MCUXCLPKC_PARAM_MC2 | ((repeat) & 0x0Fu), MCUXCLPKC_MC_ ## symbol, iX, iY, iZ, iR) + + +/**********************************************************/ +/* Macros for FUP CRC entry */ +/**********************************************************/ +#define MCUXCLPKC_PARAM_CRC 0x10u ///< CALCparam0 of CRC entry +/** Helper macro to pack CRC entry. */ +#define FUP_CRC_ENTRY(crc32) MCUXCLPKC_FUP_PACKARGS6(MCUXCLPKC_PARAM_CRC, 0, (crc32) & 0xFFu, ((crc32) >> 8) & 0xFFu, ((crc32) >> 16) & 0xFFu, ((crc32) >> 24) & 0xFFu) + +/** + * Macro to reserve space for a CRC entry in FUP program. + * The CRC32 value is temporarily set to 0x00000000, and will be updated (filled) by build system. + */ +#define PH_CLNS_UTILS_FAME_CRC_ENTRY {MCUXCLPKC_PARAM_CRC,0, 0,0,0,0} + + +/**********************************************************/ +/* Helper macros for FUP program composing */ +/**********************************************************/ +/* R, X, Y and Z/C are 8-bit constant indices of UPTRT[]. */ +/* Argument(s) (index) not used is set to 0. */ /* TODO: CLNS-916, replace by other used index, e.g., R, to avoid PKC loading UPTRT[0] into UPTRT cache. */ +/* For PKC operations with a constant, e.g., ADD_CONST and SHL, */ +/* the constant parameter shall be stored in UPTRT[C]. */ + +/* L0 operation (OP) with parameter set 1, without repeating. */ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all FUP operations are defined.") +#define FUP_OP1_MUL(R,X,Y) MCUXCLPKC_FUP_OP1(MUL, R,X,Y,0, 0) +#define FUP_OP1_MAC(R,X,Y,Z) MCUXCLPKC_FUP_OP1(MAC, R,X,Y,Z, 0) +#define FUP_OP1_MAC_NEG(R,X,Y,Z) MCUXCLPKC_FUP_OP1(MAC_NEG, R,X,Y,Z, 0) +#define FUP_OP1_MUL_GF2(R,X,Y) MCUXCLPKC_FUP_OP1(MUL_GF2, R,X,Y,0, 0) +#define FUP_OP1_MAC_GF2(R,X,Y,Z) MCUXCLPKC_FUP_OP1(MAC_GF2, R,X,Y,Z, 0) +#define FUP_OP1_NEG(R,Z) MCUXCLPKC_FUP_OP1(NEG, R,0,0,Z, 0) +#define FUP_OP1_ADD(R,Y,Z) MCUXCLPKC_FUP_OP1(ADD, R,0,Y,Z, 0) +#define FUP_OP1_SUB(R,Y,Z) MCUXCLPKC_FUP_OP1(SUB, R,0,Y,Z, 0) +#define FUP_OP1_AND(R,Y,Z) MCUXCLPKC_FUP_OP1(AND, R,0,Y,Z, 0) +#define FUP_OP1_OR(R,Y,Z) MCUXCLPKC_FUP_OP1(OR, R,0,Y,Z, 0) +#define FUP_OP1_XOR(R,Y,Z) MCUXCLPKC_FUP_OP1(XOR, R,0,Y,Z, 0) +#define FUP_OP1_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_FUP_OP1(MAC_CONST_GF2, R,X,Y,C, 0) +#define FUP_OP1_MAC_CONST(R,X,Y,C) MCUXCLPKC_FUP_OP1(MAC_CONST, R,X,Y,C, 0) +#define FUP_OP1_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_FUP_OP1(MAC_NEG_CONST, R,X,Y,C, 0) +#define FUP_OP1_SHL(R,Y,C) MCUXCLPKC_FUP_OP1(SHL, R,0,Y,C, 0) +#define FUP_OP1_SHR(R,Y,C) MCUXCLPKC_FUP_OP1(SHR, R,0,Y,C, 0) +#define FUP_OP1_ROTL(R,Y,C) MCUXCLPKC_FUP_OP1(ROTL, R,0,Y,C, 0) +#define FUP_OP1_ROTR(R,Y,C) MCUXCLPKC_FUP_OP1(ROTR, R,0,Y,C, 0) +#define FUP_OP1_ADD_CONST(R,Y,C) MCUXCLPKC_FUP_OP1(ADD_CONST, R,0,Y,C, 0) +#define FUP_OP1_SUB_CONST(R,Y,C) MCUXCLPKC_FUP_OP1(SUB_CONST, R,0,Y,C, 0) +#define FUP_OP1_AND_CONST(R,Y,C) MCUXCLPKC_FUP_OP1(AND_CONST, R,0,Y,C, 0) +#define FUP_OP1_OR_CONST(R,Y,C) MCUXCLPKC_FUP_OP1(OR_CONST, R,0,Y,C, 0) +#define FUP_OP1_XOR_CONST(R,Y,C) MCUXCLPKC_FUP_OP1(XOR_CONST, R,0,Y,C, 0) +#define FUP_OP1_MUL1(X,Y) MCUXCLPKC_FUP_OP1(MUL1, 0,X,Y,0, 0) +#define FUP_OP1_MACC(R,X,Y,Z) MCUXCLPKC_FUP_OP1(MACC, R,X,Y,Z, 0) +#define FUP_OP1_MUL1_GF2(X,Y) MCUXCLPKC_FUP_OP1(MUL1_GF2, 0,X,Y,0, 0) +#define FUP_OP1_MACC_GF2(R,X,Y,Z) MCUXCLPKC_FUP_OP1(MACC_GF2, R,X,Y,Z, 0) +#define FUP_OP1_ADDC(R,Y,Z) MCUXCLPKC_FUP_OP1(ADDC, R,0,Y,Z, 0) +#define FUP_OP1_SUBC(R,Y,Z) MCUXCLPKC_FUP_OP1(SUBC, R,0,Y,Z, 0) +#define FUP_OP1_LSB0s(Z) MCUXCLPKC_FUP_OP1(LSB0s, 0,0,0,Z, 0) +#define FUP_OP1_MSB0s(Z) MCUXCLPKC_FUP_OP1(MSB0s, 0,0,0,Z, 0) +#define FUP_OP1_CONST(R,C) MCUXCLPKC_FUP_OP1(CONST, R,0,0,C, 0) +#define FUP_OP1_CMP(Y,Z) MCUXCLPKC_FUP_OP1(CMP, 0,0,Y,Z, 0) +#define FUP_OP1_MACCR(R,Y,Z) MCUXCLPKC_FUP_OP1(MACCR, R,0,Y,Z, 0) +#define FUP_OP1_MACCR_GF2(R,Y,Z) MCUXCLPKC_FUP_OP1(MACCR_GF2, R,0,Y,Z, 0) +#define FUP_OP1_ADD_Z0(R,Y,Z) MCUXCLPKC_FUP_OP1(ADD_Z0, R,0,Y,Z, 0) +#define FUP_OP1_XOR_Z0(R,Y,Z) MCUXCLPKC_FUP_OP1(XOR_Z0, R,0,Y,Z, 0) + +/* L1 microcode (MC) with parameter set 1, without repeating. */ +#define FUP_MC1_MM(R,X,Y,N) MCUXCLPKC_FUP_MC1(MM, R,X,Y,N, 0) +#define FUP_MC1_MM_GF2(R,X,Y,N) MCUXCLPKC_FUP_MC1(MM_GF2, R,X,Y,N, 0) +#define FUP_MC1_PM(R,X,Y) MCUXCLPKC_FUP_MC1(PM, R,X,Y,0, 0) +#define FUP_MC1_PM_GF2(R,X,Y) MCUXCLPKC_FUP_MC1(PM_GF2, R,X,Y,0, 0) +#define FUP_MC1_PMA(R,X,Y,Z) MCUXCLPKC_FUP_MC1(PMA, R,X,Y,Z, 0) +#define FUP_MC1_PMA_GF2(R,X,Y,Z) MCUXCLPKC_FUP_MC1(PMA_GF2, R,X,Y,Z, 0) +#define FUP_MC1_MA(R,Y,Z,N) MCUXCLPKC_FUP_MC1(MA, R,N,Y,Z, 0) +#define FUP_MC1_MS(R,Y,Z,N) MCUXCLPKC_FUP_MC1(MS, R,N,Y,Z, 0) +#define FUP_MC1_MR(R,X,N) MCUXCLPKC_FUP_MC1(MR, R,X,0,N, 0) +#define FUP_MC1_MR_GF2(R,X,N) MCUXCLPKC_FUP_MC1(MR_GF2, R,X,0,N, 0) +#define FUP_MC1_MMP2(R,X,Y) MCUXCLPKC_FUP_MC1(MMP2, R,X,Y,0, 0) +#define FUP_MC1_MMAP2(R,X,Y,Z) MCUXCLPKC_FUP_MC1(MMAP2, R,X,Y,Z, 0) +#define FUP_MC1_MI(R,Y,N,Z) MCUXCLPKC_FUP_MC1(MI, R,N,Y,Z, 0) /* Z buffer needs to be initialized to 1 */ +#define FUP_MC1_MI_GF2(R,Y,N,Z) MCUXCLPKC_FUP_MC1(MI_GF2, R,N,Y,Z, 0) /* Z buffer needs to be initialized to 1 */ +#define FUP_MC1_PM_PATCH(R,X,Y) MCUXCLPKC_FUP_MC1(PM_PATCH, R,X,Y,0, 0) +#define FUP_MC1_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_FUP_MC1(PM_PATCH_GF2, R,X,Y,0, 0) +#define FUP_MC1_GCD(Y,Z) MCUXCLPKC_FUP_MC1(GCD, Z,Y,Y,Z, 0) /* X = Y, R = Z (result in-place) */ + +/* L0 operation (OP) with parameter set 2, without repeating. */ +#define FUP_OP2_MUL(R,X,Y) MCUXCLPKC_FUP_OP2(MUL, R,X,Y,0, 0) +#define FUP_OP2_MAC(R,X,Y,Z) MCUXCLPKC_FUP_OP2(MAC, R,X,Y,Z, 0) +#define FUP_OP2_MAC_NEG(R,X,Y,Z) MCUXCLPKC_FUP_OP2(MAC_NEG, R,X,Y,Z, 0) +#define FUP_OP2_MUL_GF2(R,X,Y) MCUXCLPKC_FUP_OP2(MUL_GF2, R,X,Y,0, 0) +#define FUP_OP2_MAC_GF2(R,X,Y,Z) MCUXCLPKC_FUP_OP2(MAC_GF2, R,X,Y,Z, 0) +#define FUP_OP2_NEG(R,Z) MCUXCLPKC_FUP_OP2(NEG, R,0,0,Z, 0) +#define FUP_OP2_ADD(R,Y,Z) MCUXCLPKC_FUP_OP2(ADD, R,0,Y,Z, 0) +#define FUP_OP2_SUB(R,Y,Z) MCUXCLPKC_FUP_OP2(SUB, R,0,Y,Z, 0) +#define FUP_OP2_AND(R,Y,Z) MCUXCLPKC_FUP_OP2(AND, R,0,Y,Z, 0) +#define FUP_OP2_OR(R,Y,Z) MCUXCLPKC_FUP_OP2(OR, R,0,Y,Z, 0) +#define FUP_OP2_XOR(R,Y,Z) MCUXCLPKC_FUP_OP2(XOR, R,0,Y,Z, 0) +#define FUP_OP2_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_FUP_OP2(MAC_CONST_GF2, R,X,Y,C, 0) +#define FUP_OP2_MAC_CONST(R,X,Y,C) MCUXCLPKC_FUP_OP2(MAC_CONST, R,X,Y,C, 0) +#define FUP_OP2_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_FUP_OP2(MAC_NEG_CONST, R,X,Y,C, 0) +#define FUP_OP2_SHL(R,Y,C) MCUXCLPKC_FUP_OP2(SHL, R,0,Y,C, 0) +#define FUP_OP2_SHR(R,Y,C) MCUXCLPKC_FUP_OP2(SHR, R,0,Y,C, 0) +#define FUP_OP2_ROTL(R,Y,C) MCUXCLPKC_FUP_OP2(ROTL, R,0,Y,C, 0) +#define FUP_OP2_ROTR(R,Y,C) MCUXCLPKC_FUP_OP2(ROTR, R,0,Y,C, 0) +#define FUP_OP2_ADD_CONST(R,Y,C) MCUXCLPKC_FUP_OP2(ADD_CONST, R,0,Y,C, 0) +#define FUP_OP2_SUB_CONST(R,Y,C) MCUXCLPKC_FUP_OP2(SUB_CONST, R,0,Y,C, 0) +#define FUP_OP2_AND_CONST(R,Y,C) MCUXCLPKC_FUP_OP2(AND_CONST, R,0,Y,C, 0) +#define FUP_OP2_OR_CONST(R,Y,C) MCUXCLPKC_FUP_OP2(OR_CONST, R,0,Y,C, 0) +#define FUP_OP2_XOR_CONST(R,Y,C) MCUXCLPKC_FUP_OP2(XOR_CONST, R,0,Y,C, 0) +#define FUP_OP2_MUL1(X,Y) MCUXCLPKC_FUP_OP2(MUL1, 0,X,Y,0, 0) +#define FUP_OP2_MACC(R,X,Y,Z) MCUXCLPKC_FUP_OP2(MACC, R,X,Y,Z, 0) +#define FUP_OP2_MUL1_GF2(X,Y) MCUXCLPKC_FUP_OP2(MUL1_GF2, 0,X,Y,0, 0) +#define FUP_OP2_MACC_GF2(R,X,Y,Z) MCUXCLPKC_FUP_OP2(MACC_GF2, R,X,Y,Z, 0) +#define FUP_OP2_ADDC(R,Y,Z) MCUXCLPKC_FUP_OP2(ADDC, R,0,Y,Z, 0) +#define FUP_OP2_SUBC(R,Y,Z) MCUXCLPKC_FUP_OP2(SUBC, R,0,Y,Z, 0) +#define FUP_OP2_LSB0s(Z) MCUXCLPKC_FUP_OP2(LSB0s, 0,0,0,Z, 0) +#define FUP_OP2_MSB0s(Z) MCUXCLPKC_FUP_OP2(MSB0s, 0,0,0,Z, 0) +#define FUP_OP2_CONST(R,C) MCUXCLPKC_FUP_OP2(CONST, R,0,0,C, 0) +#define FUP_OP2_CMP(Y,Z) MCUXCLPKC_FUP_OP2(CMP, 0,0,Y,Z, 0) +#define FUP_OP2_MACCR(R,Y,Z) MCUXCLPKC_FUP_OP2(MACCR, R,0,Y,Z, 0) +#define FUP_OP2_MACCR_GF2(R,Y,Z) MCUXCLPKC_FUP_OP2(MACCR_GF2, R,0,Y,Z, 0) +#define FUP_OP2_ADD_Z0(R,Y,Z) MCUXCLPKC_FUP_OP2(ADD_Z0, R,0,Y,Z, 0) +#define FUP_OP2_XOR_Z0(R,Y,Z) MCUXCLPKC_FUP_OP2(XOR_Z0, R,0,Y,Z, 0) + +/* L1 microcode (MC) with parameter set 2, without repeating. */ +#define FUP_MC2_MM(R,X,Y,N) MCUXCLPKC_FUP_MC2(MM, R,X,Y,N, 0) +#define FUP_MC2_MM_GF2(R,X,Y,N) MCUXCLPKC_FUP_MC2(MM_GF2, R,X,Y,N, 0) +#define FUP_MC2_PM(R,X,Y) MCUXCLPKC_FUP_MC2(PM, R,X,Y,0, 0) +#define FUP_MC2_PM_GF2(R,X,Y) MCUXCLPKC_FUP_MC2(PM_GF2, R,X,Y,0, 0) +#define FUP_MC2_PMA(R,X,Y,Z) MCUXCLPKC_FUP_MC2(PMA, R,X,Y,Z, 0) +#define FUP_MC2_PMA_GF2(R,X,Y,Z) MCUXCLPKC_FUP_MC2(PMA_GF2, R,X,Y,Z, 0) +#define FUP_MC2_MA(R,Y,Z,N) MCUXCLPKC_FUP_MC2(MA, R,N,Y,Z, 0) +#define FUP_MC2_MS(R,Y,Z,N) MCUXCLPKC_FUP_MC2(MS, R,N,Y,Z, 0) +#define FUP_MC2_MR(R,X,N) MCUXCLPKC_FUP_MC2(MR, R,X,0,N, 0) +#define FUP_MC2_MR_GF2(R,X,N) MCUXCLPKC_FUP_MC2(MR_GF2, R,X,0,N, 0) +#define FUP_MC2_MMP2(R,X,Y) MCUXCLPKC_FUP_MC2(MMP2, R,X,Y,0, 0) +#define FUP_MC2_MMAP2(R,X,Y,Z) MCUXCLPKC_FUP_MC2(MMAP2, R,X,Y,Z, 0) +#define FUP_MC2_MI(R,Y,N,Z) MCUXCLPKC_FUP_MC2(MI, R,N,Y,Z, 0) /* Z buffer needs to be initialized to 1 */ +#define FUP_MC2_MI_GF2(R,Y,N,Z) MCUXCLPKC_FUP_MC2(MI_GF2, R,N,Y,Z, 0) /* Z buffer needs to be initialized to 1 */ +#define FUP_MC2_PM_PATCH(R,X,Y) MCUXCLPKC_FUP_MC2(PM_PATCH, R,X,Y,0, 0) +#define FUP_MC2_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_FUP_MC2(PM_PATCH_GF2, R,X,Y,0, 0) +#define FUP_MC2_GCD(Y,Z) MCUXCLPKC_FUP_MC2(GCD, Z,Y,Y,Z, 0) /* X = Y, R = Z (result in-place) */ +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +#endif /* MCUXCLPKC_FUPMACROS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_ImportExport.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_ImportExport.h new file mode 100644 index 000000000..029fd2154 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_ImportExport.h @@ -0,0 +1,315 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_ImportExport.h + * @brief Declaration of PKC internal import/export functions of mcuxClPkc component + */ + + +#ifndef MCUXCLPKC_IMPORTEXPORT_H_ +#define MCUXCLPKC_IMPORTEXPORT_H_ + + +#include +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Import/export function declaration */ +/**********************************************************/ + +/** + * \brief Function to switch the endianness of the data in a buffer + * + * This function switches the endianness of a data buffer of a specified length. + * + * \param[in/out] ptr pointer to data buffer of which endianness is switched + * \param[in] length length of data buffer pointed to by ptr + * + *
+ *
Parameter properties
+ *
+ *
@p ptr
+ *
pointer shall be CPU word aligned.
+ *
@p length
+ *
if length is not a multiple of CPU wordsize, this function will: + *
cause unaligned word access and sometimes byte access, on platform supporting unaligned access; + *
switch endianness byte-wisely, on platform not supporting unaligned access.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_SwitchEndianness) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_SwitchEndianness(uint32_t *ptr, uint32_t length); + +/** Helper macro to call #mcuxClPkc_SwitchEndianness with flow protection. */ +#define MCUXCLPKC_FP_SWITCHENDIANNESS(ptr, length) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_SwitchEndianness(ptr, length)) + + +/** + * \brief Function to import an operand, which is provided in big-endian order + * + * This function imports an integer stored as a big-endian octet string with specified length + * and stores it as an integer in PKC workarea according PKC specification. + * + * \param[out] iTarget index of PKC operand, where the imported integer will be stored + * \param[in] pSource address of the octet string to be imported + * \param[in] length length of the octet string to be imported + * + *
+ *
Parameter properties
+ *
+ *
@p iTarget
+ *
index of the PKC operand, size = PKC PS1LEN. + *
The offset (UPTRT[iTarget]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_ImportBigEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ImportBigEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length); + +/** Helper macro to call #mcuxClPkc_ImportBigEndianToPkc with flow protection. */ +#define MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(indexTarget, ptrSource, length) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_ImportBigEndianToPkc(indexTarget, ptrSource, length)) + + +/** + * \brief Function to import an operand, which is provided in little-endian order + * + * This function imports an integer stored as a little-endian octet string with specified length + * and stores it as an integer in PKC workarea according PKC specification. + * + * \param[out] iTarget index of PKC operand, where the imported integer will be stored + * \param[in] pSource address of the octet string to be imported + * \param[in] length length of the octet string to be imported + * + *
+ *
Parameter properties
+ *
+ *
@p iTarget
+ *
index of the PKC operand, size = PKC PS1LEN.
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ImportLittleEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ImportLittleEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length); + +/** Helper macro to call #mcuxClPkc_ImportLittleEndianToPkc with flow protection. */ +#define MCUXCLPKC_FP_IMPORTLITTLEENDIANTOPKC(indexTarget, pSource, length) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_ImportLittleEndianToPkc(indexTarget, pSource, length)) + + +/** + * \brief Function to export an operand to a big-endian integer + * + * This function exports a PKC integer in PKC workarea and stores it as a big-endian octet string + * in a buffer specified by the given address and length. + * + * \param[out] pTarget address of operand, where the exported integer will be stored + * \param[in] iSource index of PKC operand to be exported + * \param[in] length length of the octet string to be exported + * + *
+ *
Parameter properties
+ *
+ *
@p iSource
+ *
index of the PKC operand, size = PKC PS1LEN. + *
The offset (UPTRT[iSource]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
PKC integer stored in source buffer will be destroyed after calling this function.
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_ExportBigEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ExportBigEndianFromPkc(uint8_t * pTarget, uint8_t iSource, uint32_t length); + +/** Helper macro to call #mcuxClPkc_ExportBigEndianFromPkc with flow protection. */ +#define MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(ptrTarget, indexSource, length) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_ExportBigEndianFromPkc(ptrTarget, indexSource, length)) + + +/** + * \brief Function to export an operand to a little-endian integer + * + * This function exports a PKC integer in PKC workarea and stores it as a little-endian octet string + * in a buffer specified by the given address and length. + * + * \param[out] pTarget address of operand, where the exported integer will be stored + * \param[in] iSource index of PKC operand to be exported + * \param[in] length length of the octet string to be exported + * + *
+ *
Parameter properties
+ *
+ *
@p iSource
+ *
index of the PKC operand, size = PKC PS1LEN.
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_ExportLittleEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ExportLittleEndianFromPkc(uint8_t * pTarget, uint8_t iSource, uint32_t length); + +/** Helper macro to call #mcuxClPkc_ExportLittleEndianFromPkc with flow protection. */ +#define MCUXCLPKC_FP_EXPORTLITTLEENDIANFROMPKC(ptrTarget, indexSource, length) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_ExportLittleEndianFromPkc(ptrTarget, indexSource, length)) + + +/** + * \brief Function to securely import an operand, which is provided in big-endian order + * + * This function imports an integer stored as a big-endian octet string with specified length + * and stores it as an integer in PKC workarea according PKC specification, in a secure manner. + * + * \param[in] pSession handle for the current CL session. + * \param[out] iTarget_iTemp indices of PKC operands (Target and Temp) + * \param[in] pSource address of the octet string to be imported + * \param[in] length length of the octet string to be imported + * + *
+ *
Parameter properties
+ *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function.
+ *
@p iTarget_iTemp
+ *
iTemp (bits 0~7): index of temporary buffer (PKC operand), size = PKC PS1LEN. + *
The offset (UPTRT[iTemp]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE. + *
iTarget (bits 8~15): index of Target (PKC operand), size = PKC PS1LEN, + * where the imported integer will be stored. + *
The offset (UPTRT[iTarget]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ * + * @return Status of the mcuxClPkc_SecureImportBigEndianToPkc operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t)) + * @retval #MCUXCLPKC_STATUS_OK The function executed successfully + * @retval #MCUXCLPKC_STATUS_NOK The function execution failed + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_SecureImportBigEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureImportBigEndianToPkc(mcuxClSession_Handle_t pSession, uint16_t iTarget_iTemp, const uint8_t * pSource, uint32_t length); + + +/** + * \brief Function to securely import an operand, which is provided in little-endian order + * + * This function imports an integer stored as a little-endian octet string with specified length + * and stores it as an integer in PKC workarea according PKC specification, in a secure manner. + * + * \param[out] iTarget index of PKC operand, where the imported integer will be stored + * \param[in] pSource address of the octet string to be imported + * \param[in] length length of the octet string to be imported + * + *
+ *
Parameter properties
+ *
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ *
+ * + * @return Status of the mcuxClPkc_SecureImportLittleEndianToPkc operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t)) + * @retval #MCUXCLPKC_STATUS_OK The function executed successfully + * @retval #MCUXCLPKC_STATUS_NOK The function execution failed + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_SecureImportLittleEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureImportLittleEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length); + + +/** + * \brief Function to securely export an operand to a big-endian integer + * + * This function exports a PKC integer in PKC workarea and stores it as a big-endian octet string + * in a buffer specified by the given address and length, in a secure manner. + * + * \param[in] pSession handle for the current CL session. + * \param[out] pTarget address of operand, where the exported integer will be stored + * \param[in] iSource_iTemp indices of PKC operands (Source and Temp) + * \param[in] length length of the octet string to be exported + * + *
+ *
Parameter properties
+ *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function.
+ *
@p iSource_iTemp
+ *
iTemp (bits 0~7): index of temporary buffer (PKC operand), size = PKC PS1LEN. + *
The offset (UPTRT[iTemp]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
iSource (bits 8~15): index of Source (PKC operand) to be exported, size = PKC PS1LEN. + *
The offset (UPTRT[iSource]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
PKC integer stored in source buffer will be destroyed after calling this function, + * but it is not cleared and is still sensitive. + *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN.
+ *
+ * + * + * @return Status of the mcuxClPkc_SecureExportBigEndianFromPkc operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t)) + * @retval #MCUXCLPKC_STATUS_OK The function executed successfully + * @retval #MCUXCLPKC_STATUS_NOK The function execution failed + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_SecureExportBigEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureExportBigEndianFromPkc(mcuxClSession_Handle_t pSession, uint8_t * pTarget, uint16_t iSource_iTemp, uint32_t length); + + +/** + * \brief Function to securely export an operand to a little-endian integer + * + * This function exports a PKC integer in PKC workarea and stores it as a little-endian octet string + * in a buffer specified by the given address and length, in a secure manner. + * + * \param[out] pTarget address of operand, where the exported integer will be stored + * \param[in] iSource index of PKC operand to be exported + * \param[in] length length of the octet string to be exported + * + *
+ *
Parameter properties
+ *
+ *
@p length
+ *
it shall be equal to or smaller than PKC PS1LEN. + *
+ *
+ * + * @return Status of the mcuxClPkc_SecureExportLittleEndianFromPkc operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t)) + * @retval #MCUXCLPKC_STATUS_OK The function executed successfully + * @retval #MCUXCLPKC_STATUS_NOK The function execution failed + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_SecureExportLittleEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureExportLittleEndianFromPkc(uint8_t * pTarget, uint8_t iSource, uint32_t length); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPKC_IMPORTEXPORT_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Inline_Functions.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Inline_Functions.h new file mode 100644 index 000000000..beb0bddc9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Inline_Functions.h @@ -0,0 +1,183 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Inline_Functions.h + * @brief Inline functions for accessing PKC hardware IP + */ + + +#ifndef MCUXCLPKC_INLINE_FUNCTIONS_H_ +#define MCUXCLPKC_INLINE_FUNCTIONS_H_ + + +#include + +#include +#include +#include + +#include +#include + + +/**********************************************************/ +/* Inline functions for UPTR table and offsets */ +/**********************************************************/ +/** Inline function to set the address of UPTRT (Universal pointer FUP table). */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_setUptrt) +static inline void mcuxClPkc_inline_setUptrt(const uint16_t * pUptrt) +{ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, "Convert pointer to address.") + uint32_t uptrtAddr = (uint32_t) pUptrt; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4) + + MCUXCLPKC_SFR_WRITE(UPTRT, uptrtAddr); +} + +/** Inline function to get the address of UPTRT (Universal pointer FUP table). */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_getUptrt) +static inline uint16_t * mcuxClPkc_inline_getUptrt(void) +{ + uint32_t uptrtAddr = MCUXCLPKC_SFR_READ(UPTRT); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("Convert UPTRT address to pointer.") + return (uint16_t *) uptrtAddr; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() +} + +/** Inline function to convert CPU pointer to PKC offset. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ptr2Offset) +static inline uint16_t mcuxClPkc_inline_ptr2Offset(const uint8_t * cpuPointer) +{ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, "calculate PKC operand offset.") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_STR30_C, "it's a pointer to PKC operand, but not string literal.") + + uint32_t maskedAddress = (uint32_t) cpuPointer & MCUXCLPKC_RAM_OFFSET_MASK; + + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_STR30_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4) + + return (uint16_t) maskedAddress; +} + +/** Inline function to convert PKC offset to CPU pointer. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_offset2Ptr) +static inline uint8_t * mcuxClPkc_inline_offset2Ptr(uint16_t pkcOffset) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("convert PKC operand offset to pointer.") + + uint32_t address = (uint32_t) pkcOffset | (uint32_t) MCUXCLPKC_RAM_START_ADDRESS; + uint8_t * ptr = (uint8_t *) address; + + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() + + return ptr; +} + +/** Inline function to convert PKC offset to CPU word-aligned pointer. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_offset2PtrWord) +static inline uint32_t * mcuxClPkc_inline_offset2PtrWord(uint16_t pkcOffset) +{ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("convert PKC operand offset (PKC-word aligned) to pointer.") + + uint32_t address = (uint32_t) pkcOffset | (uint32_t) MCUXCLPKC_RAM_START_ADDRESS; + uint32_t * ptrWord = (uint32_t *) address; + + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() + + return ptrWord; +} + + +/**********************************************************/ +/* Inline functions for parameter set 1 and 2 */ +/**********************************************************/ +/** Inline function to set packed MCLEN and (OP)LEN of parameter set 1. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps1_setLengthReg) +static inline void mcuxClPkc_inline_ps1_setLengthReg(uint32_t mclen_oplen) +{ + MCUXCLPKC_SFR_WRITE(LEN1, mclen_oplen); +} + +/** Inline function to set packed MCLEN and (OP)LEN of parameter set 2. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps2_setLengthReg) +static inline void mcuxClPkc_inline_ps2_setLengthReg(uint32_t mclen_oplen) +{ + MCUXCLPKC_SFR_WRITE(LEN2, mclen_oplen); +} + +/** Inline function to get packed MCLEN and (OP)LEN of parameter set 1. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps1_getLengthReg) +static inline uint32_t mcuxClPkc_inline_ps1_getLengthReg(void) +{ + uint32_t lengths = MCUXCLPKC_SFR_READ(LEN1); + return lengths; +} + +/** Inline function to get packed MCLEN and (OP)LEN of parameter set 2. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps2_getLengthReg) +static inline uint32_t mcuxClPkc_inline_ps2_getLengthReg(void) +{ + uint32_t lengths = MCUXCLPKC_SFR_READ(LEN2); + return lengths; +} + +/** Inline function to get (OP)LEN of parameter set 1. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps1_getOplen) +static inline uint16_t mcuxClPkc_inline_ps1_getOplen(void) +{ + uint32_t opLen = MCUXCLPKC_SFR_BITREAD(LEN1, LEN); + return (uint16_t) opLen; +} + +/** Inline function to get MCLEN of parameter set 1. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_ps1_getMclen) +static inline uint16_t mcuxClPkc_inline_ps1_getMclen(void) +{ + uint32_t mcLen = MCUXCLPKC_SFR_BITREAD(LEN1, MCLEN); + return (uint16_t) mcLen; +} + + +/**********************************************************/ +/* Inline functions to wait PKC computations */ +/**********************************************************/ +/** Inline function to wait until PKC finishes both on-going and pending calculations (if there is any). */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_waitForFinish) +static inline void mcuxClPkc_inline_waitForFinish(void) +{ + do{} while(0u != MCUXCLPKC_SFR_BITREAD(STATUS, ACTIV)); +} + +/** Inline function to wait until PKC is ready to accept next calculation (i.e., no pending calculation). */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_waitForReady) +static inline void mcuxClPkc_inline_waitForReady(void) +{ + do{} while(0u != MCUXCLPKC_SFR_BITREAD(STATUS, GOANY)); +} + +/** Inline function to wait PKC calculation and then get PKC status. */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_inline_waitForFinishGetStatus) +static inline uint32_t mcuxClPkc_inline_waitForFinishGetStatus(void) +{ + uint32_t pkc_status; + do { + pkc_status = MCUXCLPKC_SFR_READ(STATUS); + } while (0u != (pkc_status & MCUXCLPKC_SFR_BITMSK(STATUS, ACTIV))); + + return pkc_status; +} + + +#endif /* MCUXCLPKC_INLINE_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Macros.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Macros.h new file mode 100644 index 000000000..f6f39d26a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Macros.h @@ -0,0 +1,196 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Macros.h + * @brief Macros for accessing PKC hardware IP + */ + + +#ifndef MCUXCLPKC_MACROS_H_ +#define MCUXCLPKC_MACROS_H_ + + +#include +#include +#include +#include + +#include +#include + + +/**********************************************************/ +/* Internal PKC definitions */ +/**********************************************************/ +#define MCUXCLPKC_RAM_SIZE 0x00001000u ///< PKC workarea size = 4 KByte +#define MCUXCLPKC_RAM_OFFSET_MASK 0x00000FFFu ///< Mask to extract PKC offset from CPU pointer +#define MCUXCLPKC_LOG2_WORDSIZE 3u ///< log2(PKC wordsize in byte) + + +/* Included intentionally after the above PKC definitions. */ +#include + + +/**********************************************************/ +/* Macros for UPTR table and offsets */ +/**********************************************************/ +/** Sets the address of UPTRT (Universal pointer FUP table). */ +#define MCUXCLPKC_SETUPTRT(pUptrt) mcuxClPkc_inline_setUptrt(pUptrt) +/** Gets the address of UPTRT (Universal pointer FUP table). */ +#define MCUXCLPKC_GETUPTRT() mcuxClPkc_inline_getUptrt() + +/** Converts CPU pointer to PKC offset. + * **CAUTION** This macro does not guarantee the returned offset is PKC-word aligned. */ +#define MCUXCLPKC_PTR2OFFSET(cpuPointer) mcuxClPkc_inline_ptr2Offset(cpuPointer) +/** Converts PKC offset to CPU pointer. */ +#define MCUXCLPKC_OFFSET2PTR(pkcOffset) mcuxClPkc_inline_offset2Ptr(pkcOffset) +/** Converts PKC offset to CPU word-aligned pointer. + * **CAUTION** This macro assumes the offset provided is PKC-word aligned. */ +#define MCUXCLPKC_OFFSET2PTRWORD(pkcOffset) mcuxClPkc_inline_offset2PtrWord(pkcOffset) + + +/**********************************************************/ +/* Macros for parameter set 1 */ +/**********************************************************/ +/** Sets either mode of L0 operation or address of L1 microcode of parameter set 1. */ +#define MCUXCLPKC_PS1_SETMODE(mode) MCUXCLPKC_SFR_WRITE(MODE1, mode) +/** Sets packed offsets to buffers of operands Y and X of parameter set 1. */ +#define MCUXCLPKC_PS1_SETXY_REG(offsetY_offsetX) MCUXCLPKC_SFR_WRITE(XYPTR1, offsetY_offsetX) +/** Sets packed offsets to buffers of result R and operand Z of parameter set 1. */ +#define MCUXCLPKC_PS1_SETZR_REG(offsetR_offsetZ) MCUXCLPKC_SFR_WRITE(ZRPTR1, offsetR_offsetZ) +/** Sets packed MCLEN and (OP)LEN of parameter set 1. */ +#define MCUXCLPKC_PS1_SETLENGTH_REG(mclen_oplen) mcuxClPkc_inline_ps1_setLengthReg(mclen_oplen) + +/** Sets two offsets to buffers of operands Y and X of parameter set 1. */ +#define MCUXCLPKC_PS1_SETXY(offsetX, offsetY) \ + MCUXCLPKC_PS1_SETXY_REG( ((uint32_t) (offsetY) << MCUXCLPKC_SFR_BITPOS(XYPTR1, YPTR)) | (uint32_t) (offsetX) ) +/** Sets two offsets to buffers of result R and operand Z of parameter set 1. */ +#define MCUXCLPKC_PS1_SETZR(offsetZ, offsetR) \ + MCUXCLPKC_PS1_SETZR_REG( ((uint32_t) (offsetR) << MCUXCLPKC_SFR_BITPOS(ZRPTR1, RPTR)) | (uint32_t) (offsetZ) ) +/** Sets MCLEN and (OP)LEN of parameter set 1. */ +#define MCUXCLPKC_PS1_SETLENGTH(mclen, oplen) \ + MCUXCLPKC_PS1_SETLENGTH_REG( ((uint32_t) (mclen) << MCUXCLPKC_SFR_BITPOS(LEN1, MCLEN)) | (uint32_t) (oplen) ) + +/** Gets packed MCLEN and (OP)LEN of parameter set 1. */ +#define MCUXCLPKC_PS1_GETLENGTH_REG() mcuxClPkc_inline_ps1_getLengthReg() +/** Gets (OP)LEN of parameter set 1. */ +#define MCUXCLPKC_PS1_GETOPLEN() mcuxClPkc_inline_ps1_getOplen() +/** Gets MCLEN of parameter set 1. */ +#define MCUXCLPKC_PS1_GETMCLEN() mcuxClPkc_inline_ps1_getMclen() + +#define MCUXCLPKC_PS1_UNPACK_OPLEN(lenRegValue) \ + ( ((lenRegValue) & MCUXCLPKC_SFR_BITMSK(LEN1, LEN)) >> MCUXCLPKC_SFR_BITPOS(LEN1, LEN) ) +#define MCUXCLPKC_PS1_UNPACK_MCLEN(lenRegValue) \ + ( ((lenRegValue) & MCUXCLPKC_SFR_BITMSK(LEN1, MCLEN)) >> MCUXCLPKC_SFR_BITPOS(LEN1, MCLEN) ) + +/** Macro to start PKC L0 operation with parameter set 1. */ +#define MCUXCLPKC_PS1_START_L0() \ + do{ MCUXCLPKC_SFR_BITSET(CTRL, GOD1); MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); } while(false) +/** Macro to start PKC L1 microcode with parameter set 1. */ +#define MCUXCLPKC_PS1_START_L1() \ + do{ MCUXCLPKC_SFR_BITSET(CTRL, GOM1); MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); } while(false) + + +/**********************************************************/ +/* Macros for parameter set 2 */ +/**********************************************************/ +/** Sets either mode of L0 operation or address of L1 microcode of parameter set 2. */ +#define MCUXCLPKC_PS2_SETMODE(mode) MCUXCLPKC_SFR_WRITE(MODE2, mode) +/** Sets packed offsets to buffers of operands Y and X of parameter set 2. */ +#define MCUXCLPKC_PS2_SETXY_REG(offsetY_offsetX) MCUXCLPKC_SFR_WRITE(XYPTR2, offsetY_offsetX) +/** Sets packed offsets to buffers of result R and operand Z of parameter set 2. */ +#define MCUXCLPKC_PS2_SETZR_REG(offsetR_offsetZ) MCUXCLPKC_SFR_WRITE(ZRPTR2, offsetR_offsetZ) +/** Sets packed MCLEN and (OP)LEN of parameter set 2. */ +#define MCUXCLPKC_PS2_SETLENGTH_REG(mclen_oplen) mcuxClPkc_inline_ps2_setLengthReg(mclen_oplen) + +/** Sets two offsets to buffers of operands Y and X of parameter set 2. */ +#define MCUXCLPKC_PS2_SETXY(offsetX, offsetY) \ + MCUXCLPKC_PS2_SETXY_REG( ((uint32_t) (offsetY) << MCUXCLPKC_SFR_BITPOS(XYPTR2, YPTR)) | (uint32_t) (offsetX) ) +/** Sets two offsets to buffers of result R and operand Z of parameter set 2. */ +#define MCUXCLPKC_PS2_SETZR(offsetZ, offsetR) \ + MCUXCLPKC_PS2_SETZR_REG( ((uint32_t) (offsetR) << MCUXCLPKC_SFR_BITPOS(ZRPTR2, RPTR)) | (uint32_t) (offsetZ) ) +/** Sets MCLEN and (OP)LEN of parameter set 2. */ +#define MCUXCLPKC_PS2_SETLENGTH(mclen, oplen) \ + MCUXCLPKC_PS2_SETLENGTH_REG( ((uint32_t) (mclen) << MCUXCLPKC_SFR_BITPOS(LEN2, MCLEN)) | (uint32_t) (oplen) ) + +/** Gets packed MCLEN and (OP)LEN of parameter set 2. */ +#define MCUXCLPKC_PS2_GETLENGTH_REG() mcuxClPkc_inline_ps2_getLengthReg() +/** Gets (OP)LEN of parameter set 2. */ +#define MCUXCLPKC_PS2_GETOPLEN() MCUXCLPKC_SFR_BITREAD(LEN2, LEN) +/** Gets MCLEN of parameter set 2. */ +#define MCUXCLPKC_PS2_GETMCLEN() MCUXCLPKC_SFR_BITREAD(LEN2, MCLEN) + +/** Macro to start PKC L0 operation with parameter set 2. */ +#define MCUXCLPKC_PS2_START_L0() \ + do{ MCUXCLPKC_SFR_BITSET(CTRL, GOD2); MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); } while(false) +/** Macro to start PKC L1 microcode with parameter set 2. */ +#define MCUXCLPKC_PS2_START_L1() \ + do{ MCUXCLPKC_SFR_BITSET(CTRL, GOM2); MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); } while(false) + + +/**********************************************************/ +/* Other macros */ +/**********************************************************/ +/** Sets the SFR Data Mask. */ +#define MCUXCLPKC_SETSFRMASK(sfrMask) MCUXCLPKC_SFR_WRITE(SFR_MASK, (uint32_t) (sfrMask)) +/** Wait until PKC finishes both on-going and pending calculations (if there is any). */ +#define MCUXCLPKC_WAITFORFINISH() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_2, "this function checks PKC SFR.") \ + mcuxClPkc_inline_waitForFinish() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_2) + +/** Wait until PKC is ready to accept next calculation (i.e., no pending calculation). */ +#define MCUXCLPKC_WAITFORREADY() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_2, "this function checks PKC SFR.") \ + mcuxClPkc_inline_waitForReady() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_2) + +/** Wait PKC calculation and then get PKC status. */ +#define MCUXCLPKC_WAITFORFINISH_GETSTATUS() mcuxClPkc_inline_waitForFinishGetStatus() + +/* Macros to enable and disable GF2 calculation mode. */ +#define MCUXCLPKC_ENABLEGF2() MCUXCLPKC_SFR_BITSET(CTRL, GF2CONV) ///< Enable GF2 calculation mode. +#define MCUXCLPKC_DISABLEGF2() MCUXCLPKC_SFR_BITCLEAR(CTRL, GF2CONV) ///< Disable GF2 calculation mode. + +/* Macros to get PKC carry and zero flags. */ +#define MCUXCLPKC_GETCARRY() MCUXCLPKC_SFR_BITREAD(STATUS, CARRY) ///< Get PKC carry flag. +#define MCUXCLPKC_GETZERO() MCUXCLPKC_SFR_BITREAD(STATUS, ZERO) ///< Get PKC zero flag. +#define MCUXCLPKC_FLAG_ZERO 1u ///< PKC zero flag: result is zero +#define MCUXCLPKC_FLAG_NONZERO 0u ///< PKC zero flag: result is nonzero +#define MCUXCLPKC_FLAG_CARRY 1u ///< PKC carry flag: carry occurred +#define MCUXCLPKC_FLAG_NOCARRY 0u ///< PKC carry flag: carry not occurred + +/** Macro to wait PKC calculation and then get carry flag. */ +#define MCUXCLPKC_WAITFORFINISH_GETCARRY() \ + ((MCUXCLPKC_WAITFORFINISH_GETSTATUS() & MCUXCLPKC_SFR_BITMSK(STATUS, CARRY)) >> MCUXCLPKC_SFR_BITPOS(STATUS, CARRY)) + +/** Macro to wait PKC calculation and then get zero flag. */ +#define MCUXCLPKC_WAITFORFINISH_GETZERO() \ + ((MCUXCLPKC_WAITFORFINISH_GETSTATUS() & MCUXCLPKC_SFR_BITMSK(STATUS, ZERO)) >> MCUXCLPKC_SFR_BITPOS(STATUS, ZERO)) + + +/**********************************************************/ +/* Other macros */ +/**********************************************************/ +/** PW_READY check is not required. */ +#define MCUXCLPKC_PKC_WAIT_PW_READY() do{} while(false) + +/** Workaround disabled. */ +#define MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND() do{} while(false) + +/** Workaround disabled. */ +#define MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND() do{} while(false) + + +#endif /* MCUXCLPKC_MACROS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Operations.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Operations.h new file mode 100644 index 000000000..dd06ef1eb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Operations.h @@ -0,0 +1,530 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Operations.h + * @brief Mnemonics and macros for PKC calculation + */ + + +#ifndef MCUXCLPKC_OPERATIONS_H_ +#define MCUXCLPKC_OPERATIONS_H_ + + +#include +#include +#include + +#include +#include + + +/** + * In order to ease CLib programming, improve code readability and reduce maintenance cost, + * please use help macros, e.g., MCUXCLPKC_FP_CALC_OP1_MUL(...) to start a PKC operation, + * and corresponding function identifiers, e.g., MCUXCLPKC_FP_CALLED_CALC_OP1_MUL in FP balancing. + */ + + +/**********************************************************/ +/* Mnemonic of PKC L0 operations (OP) */ +/**********************************************************/ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all PKC operations are defined.") +#define MCUXCLPKC_OP_MUL 0x00u ///< Pure multiplication of a PKC word X0 by a MPI Y +#define MCUXCLPKC_OP_MAC 0x02u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a MPI Z +#define MCUXCLPKC_OP_MAC_NEG 0x03u ///< Multiply-Subtract of a PKC word X0 with a MPI Y and a MPI Z +#define MCUXCLPKC_OP_MUL_GF2 0x04u ///< Pure multiplication of a PKC word X0 by a MPI Y over GF(2) +#define MCUXCLPKC_OP_MAC_GF2 0x06u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a MPI Z over GF(2) +#define MCUXCLPKC_OP_NEG 0x09u ///< Two's complement of MPI Z +#define MCUXCLPKC_OP_ADD 0x0Au ///< Addition of a MPI Y with a MPI Z +#define MCUXCLPKC_OP_SUB 0x0Bu ///< Subtraction of a MPI Y with a MPI Z +#define MCUXCLPKC_OP_AND 0x0Du ///< Logical AND of a MPI Y with a MPI Z +#define MCUXCLPKC_OP_OR 0x0Eu ///< Logical OR of a MPI Y with a MPI Z +#define MCUXCLPKC_OP_XOR 0x0Fu ///< Logical XOR of a MPI Y with a MPI Z +#define MCUXCLPKC_OP_MAC_CONST_GF2 0x10u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a CONST over GF(2) +#define MCUXCLPKC_OP_MAC_CONST 0x12u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a CONST +#define MCUXCLPKC_OP_MAC_NEG_CONST 0x13u ///< Multiply-Subtract of a PKC word X0 with a MPI Y and a CONST +#define MCUXCLPKC_OP_SHL 0x14u ///< Shift left of a MPI Y by CONST positions +#define MCUXCLPKC_OP_SHR 0x15u ///< Shift right of a MPI Y by CONST positions +#define MCUXCLPKC_OP_ROTL 0x16u ///< Rotate left of a MPI Y by CONST positions +#define MCUXCLPKC_OP_ROTR 0x17u ///< Rotate right of a MPI Y by CONST positions +#define MCUXCLPKC_OP_ADD_CONST 0x1Au ///< Addition of a MPI Y with a CONST +#define MCUXCLPKC_OP_SUB_CONST 0x1Bu ///< Subtraction of a MPI Y with a CONST +#define MCUXCLPKC_OP_AND_CONST 0x1Du ///< Logical AND of a MPI Y with a CONST +#define MCUXCLPKC_OP_OR_CONST 0x1Eu ///< Logical OR of a MPI Y with a CONST +#define MCUXCLPKC_OP_XOR_CONST 0x1Fu ///< Logical XOR of a MPI Y with a CONST +#define MCUXCLPKC_OP_MUL1 0x20u ///< Plain multiplication of 1 PKC word modulo word size +#define MCUXCLPKC_OP_MACC 0x22u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a MPI Z extended by carry overhead +#define MCUXCLPKC_OP_MUL1_GF2 0x24u ///< Plain multiplication of 1 PKC word modulo word size over GF(2) +#define MCUXCLPKC_OP_MACC_GF2 0x26u ///< Multiply-Accumulate of a PKC word X0 with a MPI Y and a MPI Z over GF(2) +#define MCUXCLPKC_OP_ADDC 0x2Au ///< Addition of a MPI Y incl. carry overhead with a MPI Z +#define MCUXCLPKC_OP_SUBC 0x2Bu ///< Subtraction of a MPI Y incl. carry overhead with a MPI Z +#define MCUXCLPKC_OP_LSB0s 0x2Du ///< Determines the number of consecutive zero bits (up to 8) of MPI Z starting from LSB +#define MCUXCLPKC_OP_MSB0s 0x2Fu ///< Determines the number of consecutive zero bits (up to 8) of MPI Z starting from MSB +#define MCUXCLPKC_OP_CONST 0x3Eu ///< Initializes memory with a CONST +#define MCUXCLPKC_OP_CMP 0x4Bu ///< Compares two MPIs by subtracting MPI Z from MPI Y +#define MCUXCLPKC_OP_MACCR 0x62u ///< Multiply-Accumulate of the internal register Reg_i with a MPI Y and a MPI Z extended by carry +#define MCUXCLPKC_OP_MACCR_GF2 0x66u ///< Multiply-Accumulate of the internal register Reg_i with a MPI Y and a MPI Z over GF(2) +#define MCUXCLPKC_OP_ADD_Z0 0x6Au ///< Addition of a MPI Y with a single PKC word Z0 +#define MCUXCLPKC_OP_XOR_Z0 0x6Fu ///< XOR of a MPI Y with a single PKC word Z0 +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +/**********************************************************/ +/* Mnemonic of PKC L1 microcodes (MC) */ +/**********************************************************/ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all PKC operations are defined.") +#define MCUXCLPKC_MC_MM 0x00u ///< Modular Multiplication of a MPI X with a MPI Y modulo a MPI Z (Montgomery Reduction) +#define MCUXCLPKC_MC_MM_GF2 0x00u ///< Modular Multiplication of a MPI X with a MPI Y modulo a MPI Z (Montgomery Reduction) over GF(2) +#define MCUXCLPKC_MC_PM 0x13u ///< Plain Multiplication of a MPI X with a MPI Y +#define MCUXCLPKC_MC_PM_GF2 0x13u ///< Plain Multiplication of a MPI X with a MPI Y over GF(2) +#define MCUXCLPKC_MC_PMA 0x1Du ///< Plain Multiplication with Addition of a MPI X with a MPI Y and a MPI Z +#define MCUXCLPKC_MC_PMA_GF2 0x1Du ///< Plain Multiplication with Addition of a MPI X with a MPI Y and a MPI Z over GF(2) +#define MCUXCLPKC_MC_MA 0x21u ///< Modular Addition of a MPI Y with a MPI Z modulo a MPI X +#define MCUXCLPKC_MC_MS 0x2Au ///< Modular Subtraction of a MPI Y with a MPI Z modulo a MPI X +#define MCUXCLPKC_MC_MR 0x33u ///< Modular Reduction of a MPI X and a MPI Z +#define MCUXCLPKC_MC_MR_GF2 0x33u ///< Modular Reduction of a MPI X and a MPI Z over GF(2) + +#define MCUXCLPKC_MC_MMP2 0x53u ///< Modular Multiplication of a MPI X and a MPI Y modulo 2^LEN(Y) +#define MCUXCLPKC_MC_MMAP2 0x5Au ///< Modular Multiplication with Addition of a MPI X with a MPI Y and a MPI Z modulo 2^LEN(Y) +#define MCUXCLPKC_MC_MI 0x5Du ///< Modular Inversion of a MPI Y module a MPI X +#define MCUXCLPKC_MC_MI_GF2 0x5Du ///< Modular Inversion of a MPI Y module a MPI X over GF(2) +#define MCUXCLPKC_MC_PM_PATCH 0x9Du ///< Plain Multiplication of a MPI X with a MPI Y (patched version) +#define MCUXCLPKC_MC_PM_PATCH_GF2 0x9Du ///< Plain Multiplication of a MPI X with a MPI Y over GF(2) (patched version) +#define MCUXCLPKC_MC_GCD 0xA7u ///< Greatest common divider (GCD) of MPI Y and MPI Z +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +/**********************************************************/ +/* Macros for encoding L0/L1 and parameter set 1/2 */ +/**********************************************************/ +#define MCUXCLPKC_PARAM_L0 0x00u +#define MCUXCLPKC_PARAM_L1 0x80u +#define MCUXCLPKC_PARAM_PS1 0x00u +#define MCUXCLPKC_PARAM_PS2 0x40u +#define MCUXCLPKC_PARAM_OP1 ((uint16_t) MCUXCLPKC_PARAM_L0 | (uint16_t) MCUXCLPKC_PARAM_PS1) +#define MCUXCLPKC_PARAM_OP2 ((uint16_t) MCUXCLPKC_PARAM_L0 | (uint16_t) MCUXCLPKC_PARAM_PS2) +#define MCUXCLPKC_PARAM_MC1 ((uint16_t) MCUXCLPKC_PARAM_L1 | (uint16_t) MCUXCLPKC_PARAM_PS1) +#define MCUXCLPKC_PARAM_MC2 ((uint16_t) MCUXCLPKC_PARAM_L1 | (uint16_t) MCUXCLPKC_PARAM_PS2) + +#define MCUXCLPKC_PARAMMODE_OP1(symbo) ((MCUXCLPKC_PARAM_OP1 << 8) | MCUXCLPKC_OP_ ## symbo) +#define MCUXCLPKC_PARAMMODE_OP2(symbo) ((MCUXCLPKC_PARAM_OP2 << 8) | MCUXCLPKC_OP_ ## symbo) +#define MCUXCLPKC_PARAMMODE_MC1(symbo) ((MCUXCLPKC_PARAM_MC1 << 8) | MCUXCLPKC_MC_ ## symbo) +#define MCUXCLPKC_PARAMMODE_MC2(symbo) ((MCUXCLPKC_PARAM_MC2 << 8) | MCUXCLPKC_MC_ ## symbo) + + +/**********************************************************/ +/* Macros to start PKC calculation w/o flow protection */ +/**********************************************************/ +#define MCUXCLPKC_CALC_OP1Z(symbo,R,X,Y,Z) mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_OP1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z)) +#define MCUXCLPKC_CALC_OP2Z(symbo,R,X,Y,Z) mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_OP2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z)) +#define MCUXCLPKC_CALC_MC1Z(symbo,R,X,Y,Z) mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_MC1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z)) +#define MCUXCLPKC_CALC_MC2Z(symbo,R,X,Y,Z) mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_MC2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z)) +#define MCUXCLPKC_CALC_OP1C(symbo,R,X,Y,C) mcuxClPkc_CalcConst(MCUXCLPKC_PARAMMODE_OP1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,C)) +#define MCUXCLPKC_CALC_OP2C(symbo,R,X,Y,C) mcuxClPkc_CalcConst(MCUXCLPKC_PARAMMODE_OP2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,C)) + + +/**********************************************************/ +/* Macros to start PKC calculation with flow protection */ +/**********************************************************/ +#define MCUXCLPKC_FP_CALC_OP1Z(symbo,R,X,Y,Z) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_OP1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z))) +#define MCUXCLPKC_FP_CALC_OP2Z(symbo,R,X,Y,Z) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_OP2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z))) +#define MCUXCLPKC_FP_CALC_MC1Z(symbo,R,X,Y,Z) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_MC1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z))) +#define MCUXCLPKC_FP_CALC_MC2Z(symbo,R,X,Y,Z) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Calc(MCUXCLPKC_PARAMMODE_MC2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,Z))) +#define MCUXCLPKC_FP_CALC_OP1C(symbo,R,X,Y,C) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcConst(MCUXCLPKC_PARAMMODE_OP1(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,C))) +#define MCUXCLPKC_FP_CALC_OP2C(symbo,R,X,Y,C) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcConst(MCUXCLPKC_PARAMMODE_OP2(symbo), MCUXCLPKC_PACKARGS4(R,X,Y,C))) + + +/**********************************************************/ +/* Helper macros to start specified PKC calculation, */ +/* without flow protection */ +/**********************************************************/ +/* Argument(s) not used is set to R (or other index provided). */ +/* Or if Z is not used, call mcuxClPkc_CalcConst(...). */ + +/* L0 operation (OP) with parameter set 1. */ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all PKC operations are defined.") +#define MCUXCLPKC_CALC_OP1_MUL(R,X,Y) MCUXCLPKC_CALC_OP1C(MUL, R,X,Y,0) /* Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP1_MAC(R,X,Y,Z) MCUXCLPKC_CALC_OP1Z(MAC, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP1_MAC_NEG(R,X,Y,Z) MCUXCLPKC_CALC_OP1Z(MAC_NEG, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP1_MUL_GF2(R,X,Y) MCUXCLPKC_CALC_OP1C(MUL_GF2, R,X,Y,0) /* Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP1_MAC_GF2(R,X,Y,Z) MCUXCLPKC_CALC_OP1Z(MAC_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP1_NEG(R,Z) MCUXCLPKC_CALC_OP1Z(NEG, R,R,R,Z) /* X and Y not used */ +#define MCUXCLPKC_CALC_OP1_ADD(R,Y,Z) MCUXCLPKC_CALC_OP1Z(ADD, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_SUB(R,Y,Z) MCUXCLPKC_CALC_OP1Z(SUB, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_AND(R,Y,Z) MCUXCLPKC_CALC_OP1Z(AND, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_OR(R,Y,Z) MCUXCLPKC_CALC_OP1Z(OR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_XOR(R,Y,Z) MCUXCLPKC_CALC_OP1Z(XOR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_CALC_OP1C(MAC_CONST_GF2, R,X,Y,C) +#define MCUXCLPKC_CALC_OP1_MAC_CONST(R,X,Y,C) MCUXCLPKC_CALC_OP1C(MAC_CONST, R,X,Y,C) +#define MCUXCLPKC_CALC_OP1_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_CALC_OP1C(MAC_NEG_CONST, R,X,Y,C) +#define MCUXCLPKC_CALC_OP1_SHL(R,Y,C) MCUXCLPKC_CALC_OP1C(SHL, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_SHR(R,Y,C) MCUXCLPKC_CALC_OP1C(SHR, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_ROTL(R,Y,C) MCUXCLPKC_CALC_OP1C(ROTL, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_ROTR(R,Y,C) MCUXCLPKC_CALC_OP1C(ROTR, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_ADD_CONST(R,Y,C) MCUXCLPKC_CALC_OP1C(ADD_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_SUB_CONST(R,Y,C) MCUXCLPKC_CALC_OP1C(SUB_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_AND_CONST(R,Y,C) MCUXCLPKC_CALC_OP1C(AND_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_OR_CONST(R,Y,C) MCUXCLPKC_CALC_OP1C(OR_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_XOR_CONST(R,Y,C) MCUXCLPKC_CALC_OP1C(XOR_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP1_MUL1(X,Y) MCUXCLPKC_CALC_OP1C(MUL1, Y,X,Y,0) /* R and Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP1_MACC(R,X,Y,Z) MCUXCLPKC_CALC_OP1Z(MACC, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP1_MUL1_GF2(X,Y) MCUXCLPKC_CALC_OP1C(MUL1_GF2, Y,X,Y,0) /* R and Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP1_MACC_GF2(R,X,Y,Z) MCUXCLPKC_CALC_OP1Z(MACC_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP1_ADDC(R,Y,Z) MCUXCLPKC_CALC_OP1Z(ADDC, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_SUBC(R,Y,Z) MCUXCLPKC_CALC_OP1Z(SUBC, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_LSB0s(Z) MCUXCLPKC_CALC_OP1Z(LSB0s, Z,Z,Z,Z) /* R, X and Y not used */ +#define MCUXCLPKC_CALC_OP1_MSB0s(Z) MCUXCLPKC_CALC_OP1Z(MSB0s, Z,Z,Z,Z) /* R, X and Y not used */ +#define MCUXCLPKC_CALC_OP1_CONST(R,C) MCUXCLPKC_CALC_OP1C(CONST, R,R,R,C) /* X and Y not used */ +#define MCUXCLPKC_CALC_OP1_CMP(Y,Z) MCUXCLPKC_CALC_OP1Z(CMP, Y,Z,Y,Z) /* R and X not used */ +#define MCUXCLPKC_CALC_OP1_MACCR(R,Y,Z) MCUXCLPKC_CALC_OP1Z(MACCR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_MACCR_GF2(R,Y,Z) MCUXCLPKC_CALC_OP1Z(MACCR_GF2, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_ADD_Z0(R,Y,Z) MCUXCLPKC_CALC_OP1Z(ADD_Z0, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP1_XOR_Z0(R,Y,Z) MCUXCLPKC_CALC_OP1Z(XOR_Z0, R,R,Y,Z) /* X not used */ + +/* L1 microcode (MC) with parameter set 1. */ +#define MCUXCLPKC_CALC_MC1_MM(R,X,Y,N) MCUXCLPKC_CALC_MC1Z(MM, R,X,Y,N) +#define MCUXCLPKC_CALC_MC1_MM_GF2(R,X,Y,N) MCUXCLPKC_CALC_MC1Z(MM_GF2, R,X,Y,N) +#define MCUXCLPKC_CALC_MC1_PM(R,X,Y) MCUXCLPKC_CALC_MC1Z(PM, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC1_PM_GF2(R,X,Y) MCUXCLPKC_CALC_MC1Z(PM_GF2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC1_PMA(R,X,Y,Z) MCUXCLPKC_CALC_MC1Z(PMA, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC1_PMA_GF2(R,X,Y,Z) MCUXCLPKC_CALC_MC1Z(PMA_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC1_MA(R,Y,Z,N) MCUXCLPKC_CALC_MC1Z(MA, R,N,Y,Z) +#define MCUXCLPKC_CALC_MC1_MS(R,Y,Z,N) MCUXCLPKC_CALC_MC1Z(MS, R,N,Y,Z) +#define MCUXCLPKC_CALC_MC1_MR(R,X,N) MCUXCLPKC_CALC_MC1Z(MR, R,X,R,N) /* Y not used */ +#define MCUXCLPKC_CALC_MC1_MR_GF2(R,X,N) MCUXCLPKC_CALC_MC1Z(MR_GF2, R,X,R,N) /* Y not used */ +#define MCUXCLPKC_CALC_MC1_MMP2(R,X,Y) MCUXCLPKC_CALC_MC1Z(MMP2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC1_MMAP2(R,X,Y,Z) MCUXCLPKC_CALC_MC1Z(MMAP2, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC1_MI(R,Y,N,Z) MCUXCLPKC_CALC_MC1Z(MI, R,N,Y,Z) /* Z buffer needs to be initialized to 1 */ +#define MCUXCLPKC_CALC_MC1_MI_GF2(R,Y,N,Z) MCUXCLPKC_CALC_MC1Z(MI_GF2, R,N,Y,Z) /* Z buffer needs to be initialized to 1 */ +#define MCUXCLPKC_CALC_MC1_PM_PATCH(R,X,Y) MCUXCLPKC_CALC_MC1Z(PM_PATCH, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC1_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_CALC_MC1Z(PM_PATCH_GF2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC1_GCD(Y,Z) MCUXCLPKC_CALC_MC1Z(GCD, Z,Y,Y,Z) /* X = Y, R = Z (result in-place) */ + +/* L0 operation (OP) with parameter set 2. */ +#define MCUXCLPKC_CALC_OP2_MUL(R,X,Y) MCUXCLPKC_CALC_OP2C(MUL, R,X,Y,0) /* Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP2_MAC(R,X,Y,Z) MCUXCLPKC_CALC_OP2Z(MAC, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP2_MAC_NEG(R,X,Y,Z) MCUXCLPKC_CALC_OP2Z(MAC_NEG, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP2_MUL_GF2(R,X,Y) MCUXCLPKC_CALC_OP2C(MUL_GF2, R,X,Y,0) /* Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP2_MAC_GF2(R,X,Y,Z) MCUXCLPKC_CALC_OP2Z(MAC_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP2_NEG(R,Z) MCUXCLPKC_CALC_OP2Z(NEG, R,R,R,Z) /* X and Y not used */ +#define MCUXCLPKC_CALC_OP2_ADD(R,Y,Z) MCUXCLPKC_CALC_OP2Z(ADD, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_SUB(R,Y,Z) MCUXCLPKC_CALC_OP2Z(SUB, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_AND(R,Y,Z) MCUXCLPKC_CALC_OP2Z(AND, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_OR(R,Y,Z) MCUXCLPKC_CALC_OP2Z(OR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_XOR(R,Y,Z) MCUXCLPKC_CALC_OP2Z(XOR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_CALC_OP2C(MAC_CONST_GF2, R,X,Y,C) +#define MCUXCLPKC_CALC_OP2_MAC_CONST(R,X,Y,C) MCUXCLPKC_CALC_OP2C(MAC_CONST, R,X,Y,C) +#define MCUXCLPKC_CALC_OP2_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_CALC_OP2C(MAC_NEG_CONST, R,X,Y,C) +#define MCUXCLPKC_CALC_OP2_SHL(R,Y,C) MCUXCLPKC_CALC_OP2C(SHL, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_SHR(R,Y,C) MCUXCLPKC_CALC_OP2C(SHR, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_ROTL(R,Y,C) MCUXCLPKC_CALC_OP2C(ROTL, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_ROTR(R,Y,C) MCUXCLPKC_CALC_OP2C(ROTR, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_ADD_CONST(R,Y,C) MCUXCLPKC_CALC_OP2C(ADD_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_SUB_CONST(R,Y,C) MCUXCLPKC_CALC_OP2C(SUB_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_AND_CONST(R,Y,C) MCUXCLPKC_CALC_OP2C(AND_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_OR_CONST(R,Y,C) MCUXCLPKC_CALC_OP2C(OR_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_XOR_CONST(R,Y,C) MCUXCLPKC_CALC_OP2C(XOR_CONST, R,R,Y,C) /* X not used */ +#define MCUXCLPKC_CALC_OP2_MUL1(X,Y) MCUXCLPKC_CALC_OP2C(MUL1, Y,X,Y,0) /* R and Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP2_MACC(R,X,Y,Z) MCUXCLPKC_CALC_OP2Z(MACC, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP2_MUL1_GF2(X,Y) MCUXCLPKC_CALC_OP2C(MUL1_GF2, Y,X,Y,0) /* R and Z not used, use CalcConst */ +#define MCUXCLPKC_CALC_OP2_MACC_GF2(R,X,Y,Z) MCUXCLPKC_CALC_OP2Z(MACC_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_OP2_ADDC(R,Y,Z) MCUXCLPKC_CALC_OP2Z(ADDC, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_SUBC(R,Y,Z) MCUXCLPKC_CALC_OP2Z(SUBC, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_LSB0s(Z) MCUXCLPKC_CALC_OP2Z(LSB0s, Z,Z,Z,Z) /* R, X and Y not used */ +#define MCUXCLPKC_CALC_OP2_MSB0s(Z) MCUXCLPKC_CALC_OP2Z(MSB0s, Z,Z,Z,Z) /* R, X and Y not used */ +#define MCUXCLPKC_CALC_OP2_CONST(R,C) MCUXCLPKC_CALC_OP2C(CONST, R,R,R,C) /* X and Y not used */ +#define MCUXCLPKC_CALC_OP2_CMP(Y,Z) MCUXCLPKC_CALC_OP2Z(CMP, Y,Z,Y,Z) /* R and X not used */ +#define MCUXCLPKC_CALC_OP2_MACCR(R,Y,Z) MCUXCLPKC_CALC_OP2Z(MACCR, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_MACCR_GF2(R,Y,Z) MCUXCLPKC_CALC_OP2Z(MACCR_GF2, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_ADD_Z0(R,Y,Z) MCUXCLPKC_CALC_OP2Z(ADD_Z0, R,R,Y,Z) /* X not used */ +#define MCUXCLPKC_CALC_OP2_XOR_Z0(R,Y,Z) MCUXCLPKC_CALC_OP2Z(XOR_Z0, R,R,Y,Z) /* X not used */ + +/* L1 microcode (MC) with parameter set 2. */ +#define MCUXCLPKC_CALC_MC2_MM(R,X,Y,N) MCUXCLPKC_CALC_MC2Z(MM, R,X,Y,N) +#define MCUXCLPKC_CALC_MC2_MM_GF2(R,X,Y,N) MCUXCLPKC_CALC_MC2Z(MM_GF2, R,X,Y,N) +#define MCUXCLPKC_CALC_MC2_PM(R,X,Y) MCUXCLPKC_CALC_MC2Z(PM, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC2_PM_GF2(R,X,Y) MCUXCLPKC_CALC_MC2Z(PM_GF2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC2_PMA(R,X,Y,Z) MCUXCLPKC_CALC_MC2Z(PMA, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC2_PMA_GF2(R,X,Y,Z) MCUXCLPKC_CALC_MC2Z(PMA_GF2, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC2_MA(R,Y,Z,N) MCUXCLPKC_CALC_MC2Z(MA, R,N,Y,Z) +#define MCUXCLPKC_CALC_MC2_MS(R,Y,Z,N) MCUXCLPKC_CALC_MC2Z(MS, R,N,Y,Z) +#define MCUXCLPKC_CALC_MC2_MR(R,X,N) MCUXCLPKC_CALC_MC2Z(MR, R,X,R,N) /* Y not used */ +#define MCUXCLPKC_CALC_MC2_MR_GF2(R,X,N) MCUXCLPKC_CALC_MC2Z(MR_GF2, R,X,R,N) /* Y not used */ +#define MCUXCLPKC_CALC_MC2_MMP2(R,X,Y) MCUXCLPKC_CALC_MC2Z(MMP2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC2_MMAP2(R,X,Y,Z) MCUXCLPKC_CALC_MC2Z(MMAP2, R,X,Y,Z) +#define MCUXCLPKC_CALC_MC2_MI(R,Y,N,Z) MCUXCLPKC_CALC_MC2Z(MI, R,N,Y,Z) /* Z buffer needs to be initialized to 1 */ +#define MCUXCLPKC_CALC_MC2_MI_GF2(R,Y,N,Z) MCUXCLPKC_CALC_MC2Z(MI_GF2, R,N,Y,Z) /* Z buffer needs to be initialized to 1 */ +#define MCUXCLPKC_CALC_MC2_PM_PATCH(R,X,Y) MCUXCLPKC_CALC_MC2Z(PM_PATCH, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC2_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_CALC_MC2Z(PM_PATCH_GF2, R,X,Y,R) /* Z not used */ +#define MCUXCLPKC_CALC_MC2_GCD(Y,Z) MCUXCLPKC_CALC_MC2Z(GCD, Z,Y,Y,Z) /* X = Y, R = Z (result in-place) */ +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +/**********************************************************/ +/* Helper macros to start specified PKC calculation, */ +/* with flow protection */ +/**********************************************************/ +/* Argument(s) not used is set to R (or other index provided). */ +/* Or if Z is not used, call mcuxClPkc_CalcConst(...). */ + +/* L0 operation (OP) with parameter set 1, supporting flow protection. */ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all PKC operations are defined.") +#define MCUXCLPKC_FP_CALC_OP1_MUL(R,X,Y) MCUXCLPKC_FP_CALC_OP1C(MUL, R,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP1_MAC(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MAC, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MAC_NEG(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MAC_NEG, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MUL_GF2(R,X,Y) MCUXCLPKC_FP_CALC_OP1C(MUL_GF2, R,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP1_MAC_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MAC_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_NEG(R,Z) MCUXCLPKC_FP_CALC_OP1Z(NEG, R,R,R,Z) +#define MCUXCLPKC_FP_CALC_OP1_ADD(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(ADD, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_SUB(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(SUB, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_AND(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(AND, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_OR(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(OR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_XOR(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(XOR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_FP_CALC_OP1C(MAC_CONST_GF2, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_MAC_CONST(R,X,Y,C) MCUXCLPKC_FP_CALC_OP1C(MAC_CONST, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_FP_CALC_OP1C(MAC_NEG_CONST, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_SHL(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(SHL, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_SHR(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(SHR, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_ROTL(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(ROTL, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_ROTR(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(ROTR, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_ADD_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(ADD_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_SUB_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(SUB_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_AND_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(AND_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_OR_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(OR_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_XOR_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP1C(XOR_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP1_MUL1(X,Y) MCUXCLPKC_FP_CALC_OP1C(MUL1, Y,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP1_MACC(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MACC, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MUL1_GF2(X,Y) MCUXCLPKC_FP_CALC_OP1C(MUL1_GF2, Y,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP1_MACC_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MACC_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_ADDC(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(ADDC, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_SUBC(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(SUBC, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_LSB0s(Z) MCUXCLPKC_FP_CALC_OP1Z(LSB0s, Z,Z,Z,Z) +#define MCUXCLPKC_FP_CALC_OP1_MSB0s(Z) MCUXCLPKC_FP_CALC_OP1Z(MSB0s, Z,Z,Z,Z) +#define MCUXCLPKC_FP_CALC_OP1_CONST(R,C) MCUXCLPKC_FP_CALC_OP1C(CONST, R,R,R,C) +#define MCUXCLPKC_FP_CALC_OP1_CMP(Y,Z) MCUXCLPKC_FP_CALC_OP1Z(CMP, Y,Z,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MACCR(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MACCR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_MACCR_GF2(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(MACCR_GF2, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_ADD_Z0(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(ADD_Z0, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP1_XOR_Z0(R,Y,Z) MCUXCLPKC_FP_CALC_OP1Z(XOR_Z0, R,R,Y,Z) + +/* L1 microcode (MC) with parameter set 1, supporting flow protection. */ +#define MCUXCLPKC_FP_CALC_MC1_MM(R,X,Y,N) MCUXCLPKC_FP_CALC_MC1Z(MM, R,X,Y,N) +#define MCUXCLPKC_FP_CALC_MC1_MM_GF2(R,X,Y,N) MCUXCLPKC_FP_CALC_MC1Z(MM_GF2, R,X,Y,N) +#define MCUXCLPKC_FP_CALC_MC1_PM(R,X,Y) MCUXCLPKC_FP_CALC_MC1Z(PM, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC1_PM_GF2(R,X,Y) MCUXCLPKC_FP_CALC_MC1Z(PM_GF2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC1_PMA(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC1Z(PMA, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_PMA_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC1Z(PMA_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_MA(R,Y,Z,N) MCUXCLPKC_FP_CALC_MC1Z(MA, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_MS(R,Y,Z,N) MCUXCLPKC_FP_CALC_MC1Z(MS, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_MR(R,X,N) MCUXCLPKC_FP_CALC_MC1Z(MR, R,X,R,N) +#define MCUXCLPKC_FP_CALC_MC1_MR_GF2(R,X,N) MCUXCLPKC_FP_CALC_MC1Z(MR_GF2, R,X,R,N) +#define MCUXCLPKC_FP_CALC_MC1_MMP2(R,X,Y) MCUXCLPKC_FP_CALC_MC1Z(MMP2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC1_MMAP2(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC1Z(MMAP2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_MI(R,Y,N,Z) MCUXCLPKC_FP_CALC_MC1Z(MI, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_MI_GF2(R,Y,N,Z) MCUXCLPKC_FP_CALC_MC1Z(MI_GF2, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC1_PM_PATCH(R,X,Y) MCUXCLPKC_FP_CALC_MC1Z(PM_PATCH, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC1_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_FP_CALC_MC1Z(PM_PATCH_GF2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC1_GCD(Y,Z) MCUXCLPKC_FP_CALC_MC1Z(GCD, Z,Y,Y,Z) + +/* L0 operation (OP) with parameter set 2, supporting flow protection. */ +#define MCUXCLPKC_FP_CALC_OP2_MUL(R,X,Y) MCUXCLPKC_FP_CALC_OP2C(MUL, R,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP2_MAC(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MAC, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MAC_NEG(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MAC_NEG, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MUL_GF2(R,X,Y) MCUXCLPKC_FP_CALC_OP2C(MUL_GF2, R,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP2_MAC_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MAC_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_NEG(R,Z) MCUXCLPKC_FP_CALC_OP2Z(NEG, R,R,R,Z) +#define MCUXCLPKC_FP_CALC_OP2_ADD(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(ADD, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_SUB(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(SUB, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_AND(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(AND, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_OR(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(OR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_XOR(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(XOR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MAC_CONST_GF2(R,X,Y,C) MCUXCLPKC_FP_CALC_OP2C(MAC_CONST_GF2, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_MAC_CONST(R,X,Y,C) MCUXCLPKC_FP_CALC_OP2C(MAC_CONST, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_MAC_NEG_CONST(R,X,Y,C) MCUXCLPKC_FP_CALC_OP2C(MAC_NEG_CONST, R,X,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_SHL(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(SHL, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_SHR(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(SHR, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_ROTL(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(ROTL, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_ROTR(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(ROTR, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_ADD_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(ADD_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_SUB_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(SUB_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_AND_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(AND_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_OR_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(OR_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_XOR_CONST(R,Y,C) MCUXCLPKC_FP_CALC_OP2C(XOR_CONST, R,R,Y,C) +#define MCUXCLPKC_FP_CALC_OP2_MUL1(X,Y) MCUXCLPKC_FP_CALC_OP2C(MUL1, Y,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP2_MACC(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MACC, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MUL1_GF2(X,Y) MCUXCLPKC_FP_CALC_OP2C(MUL1_GF2, Y,X,Y,0) +#define MCUXCLPKC_FP_CALC_OP2_MACC_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MACC_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_ADDC(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(ADDC, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_SUBC(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(SUBC, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_LSB0s(Z) MCUXCLPKC_FP_CALC_OP2Z(LSB0s, Z,Z,Z,Z) +#define MCUXCLPKC_FP_CALC_OP2_MSB0s(Z) MCUXCLPKC_FP_CALC_OP2Z(MSB0s, Z,Z,Z,Z) +#define MCUXCLPKC_FP_CALC_OP2_CONST(R,C) MCUXCLPKC_FP_CALC_OP2C(CONST, R,R,R,C) +#define MCUXCLPKC_FP_CALC_OP2_CMP(Y,Z) MCUXCLPKC_FP_CALC_OP2Z(CMP, Y,Z,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MACCR(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MACCR, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_MACCR_GF2(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(MACCR_GF2, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_ADD_Z0(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(ADD_Z0, R,R,Y,Z) +#define MCUXCLPKC_FP_CALC_OP2_XOR_Z0(R,Y,Z) MCUXCLPKC_FP_CALC_OP2Z(XOR_Z0, R,R,Y,Z) + +/* L1 microcode (MC) with parameter set 2, supporting flow protection. */ +#define MCUXCLPKC_FP_CALC_MC2_MM(R,X,Y,N) MCUXCLPKC_FP_CALC_MC2Z(MM, R,X,Y,N) +#define MCUXCLPKC_FP_CALC_MC2_MM_GF2(R,X,Y,N) MCUXCLPKC_FP_CALC_MC2Z(MM_GF2, R,X,Y,N) +#define MCUXCLPKC_FP_CALC_MC2_PM(R,X,Y) MCUXCLPKC_FP_CALC_MC2Z(PM, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC2_PM_GF2(R,X,Y) MCUXCLPKC_FP_CALC_MC2Z(PM_GF2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC2_PMA(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC2Z(PMA, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_PMA_GF2(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC2Z(PMA_GF2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_MA(R,Y,Z,N) MCUXCLPKC_FP_CALC_MC2Z(MA, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_MS(R,Y,Z,N) MCUXCLPKC_FP_CALC_MC2Z(MS, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_MR(R,X,N) MCUXCLPKC_FP_CALC_MC2Z(MR, R,X,R,N) +#define MCUXCLPKC_FP_CALC_MC2_MR_GF2(R,X,N) MCUXCLPKC_FP_CALC_MC2Z(MR_GF2, R,X,R,N) +#define MCUXCLPKC_FP_CALC_MC2_MMP2(R,X,Y) MCUXCLPKC_FP_CALC_MC2Z(MMP2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC2_MMAP2(R,X,Y,Z) MCUXCLPKC_FP_CALC_MC2Z(MMAP2, R,X,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_MI(R,Y,N,Z) MCUXCLPKC_FP_CALC_MC2Z(MI, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_MI_GF2(R,Y,N,Z) MCUXCLPKC_FP_CALC_MC2Z(MI_GF2, R,N,Y,Z) +#define MCUXCLPKC_FP_CALC_MC2_PM_PATCH(R,X,Y) MCUXCLPKC_FP_CALC_MC2Z(PM_PATCH, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC2_PM_PATCH_GF2(R,X,Y) MCUXCLPKC_FP_CALC_MC2Z(PM_PATCH_GF2, R,X,Y,R) +#define MCUXCLPKC_FP_CALC_MC2_GCD(Y,Z) MCUXCLPKC_FP_CALC_MC2Z(GCD, Z,Y,Y,Z) +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +/**********************************************************/ +/* Helper macros of function identifier, */ +/* for function called by helper macros */ +/**********************************************************/ + +/* Function identifier of L0 operation (OP) with parameter set 1. */ +MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_5, "For completeness, all PKC operations are defined.") +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MUL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC_NEG MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MUL_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_NEG MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ADD MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_SUB MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_AND MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_OR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_XOR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC_CONST_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MAC_NEG_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_SHL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_SHR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ROTL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ROTR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ADD_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_AND_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_OR_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_XOR_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MUL1 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MACC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MUL1_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MACC_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ADDC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_SUBC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_LSB0s MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MSB0s MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_CMP MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MACCR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_MACCR_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_ADD_Z0 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP1_XOR_Z0 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) + +/* Function identifier of L1 microcode (MC) with parameter set 1. */ +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MM MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MM_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PM MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PM_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PMA MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PMA_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MA MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MS MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MR_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MMP2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MMAP2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MI MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_MI_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PM_PATCH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_PM_PATCH_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC1_GCD MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) + +/* Function identifier of L0 operation (OP) with parameter set 2. */ +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MUL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC_NEG MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MUL_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_NEG MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ADD MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_SUB MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_AND MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_OR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_XOR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC_CONST_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MAC_NEG_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_SHL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_SHR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ROTL MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ROTR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ADD_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_SUB_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_AND_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_OR_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_XOR_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MUL1 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MACC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MUL1_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MACC_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ADDC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_SUBC MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_LSB0s MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MSB0s MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_CONST MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcConst) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_CMP MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MACCR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_MACCR_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_ADD_Z0 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_OP2_XOR_Z0 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) + +/* Function identifier of L1 microcode (MC) with parameter set 2. */ +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MM MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MM_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PM MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PM_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PMA MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PMA_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MA MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MS MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MR_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MMP2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MMAP2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MI MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_MI_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PM_PATCH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_PM_PATCH_GF2 MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +#define MCUXCLPKC_FP_CALLED_CALC_MC2_GCD MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Calc) +MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_5) + + +#endif /* MCUXCLPKC_OPERATIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Resource.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Resource.h new file mode 100644 index 000000000..f7caff4b0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_Resource.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Resource.h + * @brief Macros for requesting/releasing PKC + */ + + +#ifndef MCUXCLPKC_RESOURCE_H_ +#define MCUXCLPKC_RESOURCE_H_ + +#include +#include +#include +#include +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/** Macro to only initialize PKC (for platforms not supporting requesting resource) */ +#define MCUXCLPKC_FP_REQUEST_INITIALIZE(session, pPkcStateBackup, callerName, errorReturnCode) \ + MCUXCLPKC_FP_INITIALIZE(pPkcStateBackup) + +/** Macro to only deinitialize PKC (for platforms not supporting releasing resource) */ +#define MCUXCLPKC_FP_DEINITIALIZE_RELEASE(session, pPkcStateBackup, callerName, errorReturnCode) \ + MCUXCLPKC_FP_DEINITIALIZE(pPkcStateBackup) + +#define MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Initialize) +#define MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_Deinitialize) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPKC_RESOURCE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_SfrAccess.h b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_SfrAccess.h new file mode 100644 index 000000000..92734e23f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/internal/mcuxClPkc_SfrAccess.h @@ -0,0 +1,132 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_SfrAccess.h + * @brief Macros for abstracting PKC hardware SFR access + */ + + +#ifndef MCUXCLPKC_SFRACCESS_H_ +#define MCUXCLPKC_SFRACCESS_H_ + +#include +#include +#include + + +/**** ****/ +/**** PKC Hardware Abstraction Layer ****/ +/**** ****/ + +/** + * 2 different PKC hardware definition headers are supported. + * Only one of them should be used/included. + */ + + +/** Special definitions of multi-bit bit field. */ +#define MCUXCLPKC_SFR_CFG_RNDDLY_NODLY (((uint32_t)(((uint32_t)(0u)) << MCUXCLPKC_SFR_BITPOS(CFG,RNDDLY))) & MCUXCLPKC_SFR_BITMSK(CFG,RNDDLY)) +#define MCUXCLPKC_SFR_CTRL_REDMUL_FULLSZ (((uint32_t)(((uint32_t)(0u)) << MCUXCLPKC_SFR_BITPOS(CFG,RNDDLY))) & MCUXCLPKC_SFR_BITMSK(CFG,RNDDLY)) + + +/** + * Definitions for accessing PKC SFRs via, e.g., IP_PKC->STATUS. + */ + +/** Helper macros for constructing SFR field name constants */ +#define MCUXCLPKC_PASTE(a,b) a ## b +#define MCUXCLPKC_CONCAT(a,b) MCUXCLPKC_PASTE(a,b) +#define MCUXCLPKC_SFR_FIELD(prefix,sfr,field) MCUXCLPKC_CONCAT(prefix, sfr ## _ ## field) + +/** Helper macros to get the mask and shift values for a specific PKC SFR field */ +#define MCUXCLPKC_SFR_BITMSK(sfr, field) MCUXCLPKC_CONCAT(MCUXCLPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field), PKC_SFR_SUFFIX_MSK) +#define MCUXCLPKC_SFR_BITPOS(sfr, field) MCUXCLPKC_CONCAT(MCUXCLPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field), PKC_SFR_SUFFIX_POS) +#define MCUXCLPKC_SFR_BITFMT(sfr, field, val) (MCUXCLPKC_SFR_FIELD(PKC_SFR_PREFIX,sfr,field) (val)) + + +/**********************************************************/ +/* Helper macros for PKC SFR access */ +/**********************************************************/ + +/** Read from PKC SFR */ +#define MCUXCLPKC_SFR_READ(sfr) \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + (PKC_SFR_BASE->PKC_SFR_NAME(sfr)) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() + +/** Write to PKC SFR */ +#define MCUXCLPKC_SFR_WRITE(sfr, value) \ + do{ \ + uint32_t tmp_ = (value); \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + PKC_SFR_BASE->PKC_SFR_NAME(sfr) = tmp_; \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "`false` does have the Boolean type.") \ + } while(false) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4) + +/** Read from PKC SFR bit field */ +#define MCUXCLPKC_SFR_BITREAD(sfr, bit) \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, "External header outside our control: signed shifting amount") \ + ((PKC_SFR_BASE->PKC_SFR_NAME(sfr) & MCUXCLPKC_SFR_BITMSK(sfr, bit)) >> MCUXCLPKC_SFR_BITPOS(sfr, bit)) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() + +/** Set bit field of PKC SFR (read-modify-write) */ +#define MCUXCLPKC_SFR_BITSET(sfr, bit) \ + do{ \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, "External header outside our control: signed shifting amount") \ + PKC_SFR_BASE->PKC_SFR_NAME(sfr) |= MCUXCLPKC_SFR_BITMSK(sfr, bit); \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "`false` does have the Boolean type.") \ + } while(false) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4) + +/** Clear bit field of PKC SFR (read-modify-write) */ +#define MCUXCLPKC_SFR_BITCLEAR(sfr, bit) \ + do{ \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, "External header outside our control: signed shifting amount") \ + PKC_SFR_BASE->PKC_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLPKC_SFR_BITMSK(sfr, bit)); \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "`false` does have the Boolean type.") \ + } while(false) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4) + +/** Set value of multi-bit field of PKC SFR (read-modify-write) */ +#define MCUXCLPKC_SFR_BITVALSET(sfr, bit, val) \ + do{ \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, "External header outside our control: signed shifting amount") \ + uint32_t tmp_ = PKC_SFR_BASE->PKC_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLPKC_SFR_BITMSK(sfr, bit)); \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT13_C, "External header outside our control: signed shifting amount") \ + tmp_ |= (((val) << MCUXCLPKC_SFR_BITPOS(sfr, bit)) & MCUXCLPKC_SFR_BITMSK(sfr, bit)); \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT13_C) \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("PKC SFR address") \ + PKC_SFR_BASE->PKC_SFR_NAME(sfr) = tmp_; \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "`false` does have the Boolean type.") \ + } while(false) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4) + + +/**** ------------------------------ ****/ + +#endif /* MCUXCLPKC_SFRACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc.h b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc.h new file mode 100644 index 000000000..c759485ab --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc.h + * @brief Top level header of mcuxClPkc component (PKC hardware driver) + * + * @defgroup mcuxClPkc mcuxClPkc + * @brief component of PKC hardware driver + */ + + +#ifndef MCUXCLPKC_H_ +#define MCUXCLPKC_H_ + +#include +#include +#include + + +#endif /* MCUXCLPKC_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Functions.h b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Functions.h new file mode 100644 index 000000000..87d20ce4b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Functions.h @@ -0,0 +1,370 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Functions.h + * @brief APIs of mcuxClPkc component + */ + + +#ifndef MCUXCLPKC_FUNCTIONS_H_ +#define MCUXCLPKC_FUNCTIONS_H_ + + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClPkc_Functions mcuxClPkc_Functions + * @brief Defines all functions of @ref mcuxClPkc + * @ingroup mcuxClPkc + * @{ + */ + + +/**********************************************************/ +/* PKC initialization and deinitialization */ +/**********************************************************/ +/** + * @addtogroup mcuxClPkc_Functions_Init + * mcuxClPkc functions of PKC initialization and deinitialization + * @{ + */ + +/** + * @brief Structure of PKC state backup. + */ +typedef struct +{ + uint16_t ctrl; ///< backup of PKC CTRL bits + uint16_t cfg; ///< backup of PKC CFG bits +} mcuxClPkc_State_t; + + +/** +* @brief Function type for PKC initialization engine +* +* Generic function pointer to PKC initialization function +* +* @param[out] pState pointer to PKC state backup structure. If it's not a NULL pointer, PKC state before initialization will be stored in this structure. +*/ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcInitializeEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(void) (* mcuxClPkc_PkcInitializeEngine_t)(mcuxClPkc_State_t *pState)); + +/** +* @brief Function type for PKC deinitialization engine +* +* Generic function pointer to PKC deinitialization function +* +* @param[in] pState pointer to PKC state backup structure. If it's not a NULL pointer, PKC state will be restored from this structure. +*/ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClPkc_PkcDeInitializeEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(void) (* mcuxClPkc_PkcDeInitializeEngine_t)(const mcuxClPkc_State_t *pState)); + +/** + * @brief initialize PKC hardware + * + * This function initializes PKC hardware, and optionally backups the original PKC configuration (except STOP bit). + * + * @param[out] pState pointer to PKC state backup structure. If it's not a NULL pointer, PKC state before initialization will be stored in this structure. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Initialize, mcuxClPkc_PkcInitializeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Initialize( + mcuxClPkc_State_t *pState + ); +/** Helper macro to call #mcuxClPkc_Initialize with flow protection. */ +#define MCUXCLPKC_FP_INITIALIZE(pState) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Initialize(pState)) + +/** + * @brief deinitialize PKC hardware + * + * This function deinitializes PKC hardware, and optionally restores PKC configuration (except STOP bit). + * + * @param[in] pState pointer to PKC state backup structure. If it's not a NULL pointer, PKC state will be restored from this structure. + * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Deinitialize, mcuxClPkc_PkcDeInitializeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Deinitialize( + const mcuxClPkc_State_t *pState + ); +/** Helper macro to call #mcuxClPkc_Deinitialize with flow protection. */ +#define MCUXCLPKC_FP_DEINITIALIZE(pState) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_Deinitialize(pState)) + + +/** + * @} + */ /* mcuxClPkc_Functions_Init */ + + +/**********************************************************/ +/* UPTR table */ +/**********************************************************/ +/** + * @addtogroup mcuxClPkc_Functions_UPTRT + * mcuxClPkc functions of PKC UPTR table setup + * @{ + */ + +/** + * @brief Initialize UPTR table. + * + * This function initializes elements in UPTR table. + * UPTR table contains the address (16-bit offset in PKC workarea) of each buffer (PKC operand). + * Each element of the table will be initialized with a 16-bit offset, associated with a buffer allocated in sequence in PKC workarea. + * When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements. + * + * @param[out] pUPTRT pointer to the first element to be initialized in UPTR table. + * @param[in] pBaseBuffer address of the buffer in PKC workarea, with which the first element will be associated. + * @param[in] bufferLength byte length of each buffer in PKC workarea. + * @param[in] noOfBuffer number of elements to be initialized. + * + *
+ *
Parameter properties
+ *
+ *
@p pUPTRT
+ *
this pointer shall be 2-byte aligned. + *
@p pBaseBuffer
+ *
this address shall be MCUXCLPKC_WORDSIZE aligned. + *
@p bufferLength
+ *
this length shall be a multiple of MCUXCLPKC_WORDSIZE. + *
+ *
+ */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_GenerateUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_GenerateUPTRT( + uint16_t *pUPTRT, + const uint8_t *pBaseBuffer, + uint16_t bufferLength, + uint8_t noOfBuffer + ); +/** Helper macro to call #mcuxClPkc_GenerateUPTRT with flow protection. */ +#define MCUXCLPKC_FP_GENERATEUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_GenerateUPTRT(pUPTRT, pBaseBuffer, bufferSize, noOfBuffer)) + +/** + * @brief Randomize UPTR table + * + * This function randomly permutes offsets stored in UPTR table. + * It randomizes the buffer allocation (physical address in PKC workarea). + * When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements. + * + * @param[in] pSession handle for the current CL session. + * @param[in,out] pUPTRT pointer to the first element to be randomized in UPTR table. + * @param[in] noOfBuffer number of elements to be randomized. + * + *
+ *
Parameter properties
+ *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
@p pUPTRT
+ *
this pointer shall be 2-byte aligned. + *
+ *
+ * + * @attention Only the buffer allocation will be randomized, existing operands stored in each buffer will not be moved accordingly. + * @attention This function uses PRNG. Caller needs to check if PRNG is ready. + * + * @return A flow-protected status code (see @ref mcuxCsslFlowProtection). + * @retval #MCUXCLPKC_STATUS_OK if UPTR table is randomized successfully. + * @retval #MCUXCLPKC_STATUS_NOK if the operation failed. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_RandomizeUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_RandomizeUPTRT( + mcuxClSession_Handle_t pSession, + uint16_t *pUPTRT, + uint8_t noOfBuffer + ); + +/** + * @brief Randomize UPTR table and operands in PKC workarea. + * + * This function randomly permutes offsets stored in UPTR table, together with operands stored in each buffer in PKC workarea. + * It randomizes the buffer allocation (physical address in PKC workarea) and moves operands stored accordingly. + * When calling this function, there shall be no on-going and pending PKC calculations using the specified UPTR table elements. + * + * @param[in] pSession handle for the current CL session. + * @param[in,out] pUPTRT pointer to the first element to be randomized in UPTR table. + * @param[in] bufferLength byte length of each buffer in PKC workarea. + * @param[in] noOfBuffer number of elements to be randomized. + * + *
+ *
Parameter properties
+ *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
@p pUPTRT
+ *
this pointer shall be 2-byte aligned. + *
All offsets (pUPTRT[0~(noOfBuffer-1)]) shall be exactly a multiple of MCUXCLPKC_WORDSIZE.
+ *
@p bufferLength
+ *
this length shall be a multiple of MCUXCLPKC_WORDSIZE. + *
+ *
+ * + * @attention This function uses PRNG. Caller needs to check if PRNG is ready. + * + * @return A flow-protected status code (see @ref mcuxCsslFlowProtection). + * @retval #MCUXCLPKC_STATUS_OK if UPTR table is randomized successfully. + * @retval #MCUXCLPKC_STATUS_NOK if the operation failed. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_ReRandomizeUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_ReRandomizeUPTRT( + mcuxClSession_Handle_t pSession, + uint16_t *pUPTRT, + uint16_t bufferLength, + uint8_t noOfBuffer + ); + +/** + * @} + */ /* mcuxClPkc_Functions_UPTRT */ + + +/**********************************************************/ +/* PKC calculation */ +/**********************************************************/ +/** + * @addtogroup mcuxClPkc_Functions_Calculation + * mcuxClPkc functions of PKC calculation + * @{ + */ + +/** + * @brief Start a PKC calculation + * + * This function performs one specified PKC calculation, of which the operand(s) and result are specified by the indices of UPTR table. + * + * @param[in] param_mode param (the higher 8 bits) indicates the type of the calculation (L0 or L1) and the parameter set (PS1 or PS2). + *
mode (the lower 8 bits) indicates the calculation, either an L0 operation or L1 microcode. + * @param[in] iR_iX_iY_iZ indices of the operand(s) and the result in UPTR table. + * + * + * @attention The PKC calculation might be still on-going when returning to caller, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_Calc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Calc( + uint16_t param_mode, + uint32_t iR_iX_iY_iZ + ); + +/** + * @brief Start a PKC calculation with one constant parameter + * + * This function performs one specified PKC calculation, of which the operand(s) and result are specified by the indices of UPTR table, + * and a 8-bit constant parameter is directly provided. + * This function can also be used to perform an L0 operation without using Z operand, e.g., OP_MUL, R = X0 * Y. + * + * @param[in] param_mode param (the higher 8 bits) indicates the type of the calculation (always L0) and the parameter set (PS1 or PS2). +
mode (the lower 8 bits) indicates the calculation, an L0 operation. + * @param[in] iR_iX_iY_C indices of the operand(s) and the result in UPTR table, and a direct 8-bit constant. + * + * + * @attention The PKC calculation might be still on-going when returning to caller, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_CalcConst) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcConst( + uint16_t param_mode, + uint32_t iR_iX_iY_C + ); + +/** @brief type of FUP program address. */ +typedef const struct mcuxClPkc_FUPEntry * mcuxClPkc_PtrFUPEntry_t; + +/** + * @brief Start a PKC FUP program calculation + * + * This function triggers PKC to start the calculation of a FUP program. + * + * @param[in] pUPTR 2-byte aligned address of the FUP program. + * @param[in] uLength length (number of calculation) of the FUP program. + * + * @attention The PKC calculation might be still on-going when returning to caller, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_CalcFup) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcFup( + mcuxClPkc_PtrFUPEntry_t pUPTR, + uint8_t uLength + ); +/** Helper macro to call #mcuxClPkc_CalcFup with flow protection. */ +#define MCUXCLPKC_FP_CALCFUP(pUPTR, ulen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcFup(pUPTR, ulen)) + +/** Helper macro to call #mcuxClPkc_CalcFup (skipping first skipLen calculation(s)) with flow protection. */ +#define MCUXCLPKC_FP_CALCFUP_OFFSET(pUPTR, skipLen, ulen) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_CalcFup(&((mcuxClPkc_PtrFUPEntry_t) (pUPTR))[(skipLen)], ulen)) + +/** + * @} + */ /* mcuxClPkc_Functions_Calculation */ + + +/**********************************************************/ +/* PKC wait functions */ +/**********************************************************/ +/** + * @addtogroup mcuxClPkc_Functions_Wait + * mcuxClPkc functions for waiting PKC computation + * @{ + */ + +/** + * @brief Wait until PKC finishes calculations + * + * This function waits until PKC finishes on-going and pending calculations (if there is any). + * When returning to caller, PKC is in idle state, and result in PKC workarea is ready. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_WaitForFinish) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForFinish(void); +/** Helper macro to call #mcuxClPkc_WaitForFinish with flow protection. */ +#define MCUXCLPKC_FP_WAITFORFINISH() \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_WaitForFinish()) + +/** + * @brief Wait until PKC is ready to accept new calculation + * + * This function waits until PKC is ready to accept next calculation (i.e., no pending calculation). + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPkc_WaitForReady) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForReady(void); +/** Helper macro to call #mcuxClPkc_WaitForReady with flow protection. */ +#define MCUXCLPKC_FP_WAITFORREADY() \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClPkc_WaitForReady()) + + +/** + * @} + */ /* mcuxClPkc_Functions_Wait */ + +/** + * @} + */ /* mcuxClPkc_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPKC_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Types.h b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Types.h new file mode 100644 index 000000000..11240f859 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/inc/mcuxClPkc_Types.h @@ -0,0 +1,106 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Types.h + * @brief Type definitions of mcuxClPkc component + */ + + +#ifndef MCUXCLPKC_TYPES_H +#define MCUXCLPKC_TYPES_H + + +#include +#include +#include +#include + + +/** + * @defgroup mcuxClPkc_Macros mcuxClPkc_Macros + * @brief Defines all macros of @ref mcuxClPkc + * @ingroup mcuxClPkc + * @{ + */ + + +/********************************************** + * CONSTANTS + **********************************************/ +/* None */ + + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @addtogroup MCUXCLPKC_STATUS_ + * mcuxClPkc return code definitions + * @{ + */ +/** + * @brief Type for error codes used by PKC component functions. + */ +typedef uint32_t mcuxClPkc_Status_t; + +/** + * @brief Deprecated type for error codes used by code-flow protected PKC component functions. + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_Status_Protected_t; + +#define MCUXCLPKC_STATUS_OK ((mcuxClPkc_Status_t) 0x0AAA2E03u) ///< PKC operation successful +#define MCUXCLPKC_STATUS_NOK ((mcuxClPkc_Status_t) 0x0AAA53FCu) ///< PKC operation not successful +/** + * @} + */ /* MCUXCLPKC_STATUS_ */ + + +/**********************************************************/ +/* Helper macros */ +/**********************************************************/ +/** + * @addtogroup MCUXCLPKC_MISC_ + * mcuxClPkc misc macros and definitions + * @{ + */ +/** @brief Round-up a length to a multiple of PKC wordsize. */ +#define MCUXCLPKC_ROUNDUP_SIZE(byteLen) \ + (((uint32_t) (byteLen) + (uint32_t)MCUXCLPKC_WORDSIZE - (uint32_t)1u) & (~((uint32_t) MCUXCLPKC_WORDSIZE - (uint32_t)1u))) + +/** @brief Macros for packing 4 8-bit parameters. */ +#define MCUXCLPKC_PACKARGS4(byte3_MSByte, byte2, byte1, byte0_LSByte) \ + ( ((uint32_t) (byte3_MSByte) << 24) | ((uint32_t) (byte2) << 16) \ + | ((uint32_t) (byte1) << 8) | ((uint32_t) (byte0_LSByte)) ) + +/** @brief Macros for packing 2 8-bit parameters. */ +#define MCUXCLPKC_PACKARGS2(hi8, lo8) \ + ( ((uint16_t) (hi8) << 8) | ((uint16_t) (lo8)) ) + + +/**********************************************************/ +/* PKC information */ +/**********************************************************/ +#define MCUXCLPKC_RAM_START_ADDRESS PKC_RAM_ADDR ///< PKC workarea address +#define MCUXCLPKC_WORDSIZE 8u ///< PKC wordsize in byte + + +/** + * @} + */ /* MCUXCLPKC_MISC_ */ + +/** + * @} + */ /* mcuxClEcc_Macros */ + +#endif /* #MCUXCLPKC_TYPES_H */ diff --git a/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Calculate.c b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Calculate.c new file mode 100644 index 000000000..e83661bad --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Calculate.c @@ -0,0 +1,161 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Calculate.c + * @brief PKC L0(OP)/L1(MC)/L2(FUP) calculation functions + */ + + +#include +#include +#include +#include + +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_Calc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Calc(uint16_t param_mode, uint32_t iR_iX_iY_iZ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_Calc); + + const volatile uint16_t * pUPTRT = MCUXCLPKC_GETUPTRT(); + + uint32_t iZ = 0xFFu & iR_iX_iY_iZ; + uint32_t iY = 0xFFu & (iR_iX_iY_iZ >> 8); + uint32_t iX = 0xFFu & (iR_iX_iY_iZ >> 16); + uint32_t iR = 0xFFu & (iR_iX_iY_iZ >> 24); + + uint16_t offsetZ = pUPTRT[iZ]; + uint16_t offsetY = pUPTRT[iY]; + uint16_t offsetX = pUPTRT[iX]; + uint16_t offsetR = pUPTRT[iR]; + + /* Pre-calculate pkc_ctrl according to: */ + /* L0-PS1: param_mode = 0x00xy => PKC_CTRL_GOD1_Pos = 2; */ + /* L0-PS2: param_mode = 0x40xy => PKC_CTRL_GOD2_Pos = 3; */ + /* L1-PS1: param_mode = 0x80xy => PKC_CTRL_GOM1_Pos = 4; */ + /* L1-PS2: param_mode = 0xC0xy => PKC_CTRL_GOM2_Pos = 5. */ +#if ( (MCUXCLPKC_SFR_BITPOS(CTRL, GOD1) != 2) | (MCUXCLPKC_SFR_BITPOS(CTRL, GOD2) != 3) \ + | (MCUXCLPKC_SFR_BITPOS(CTRL, GOM1) != 4) | (MCUXCLPKC_SFR_BITPOS(CTRL, GOM2) != 5) ) +#error update implementation according to the PKC spec +#endif + uint32_t pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL) | ((uint32_t) MCUXCLPKC_SFR_BITMSK(CTRL, GOD1) << (((uint32_t) param_mode >> 14u) & 0x3u)); + + MCUXCLPKC_WAITFORREADY(); + + if (0u == ((uint32_t) param_mode & ((uint32_t) MCUXCLPKC_PARAM_PS2 << 8))) + { + MCUXCLPKC_PS1_SETMODE(param_mode); /* Only mode in least significant 8 bits */ + MCUXCLPKC_PS1_SETXY(offsetX, offsetY); + MCUXCLPKC_PS1_SETZR(offsetZ, offsetR); + } + else + { + MCUXCLPKC_PS2_SETMODE(param_mode); /* Only mode in least significant 8 bits */ + MCUXCLPKC_PS2_SETXY(offsetX, offsetY); + MCUXCLPKC_PS2_SETZR(offsetZ, offsetR); + } + + MCUXCLPKC_SFR_WRITE(CTRL, pkc_ctrl); + MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_Calc); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_CalcConst) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcConst(uint16_t param_mode, uint32_t iR_iX_iY_C) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_CalcConst); + + const volatile uint16_t * pUPTRT = MCUXCLPKC_GETUPTRT(); + + uint32_t C = 0xFFu & iR_iX_iY_C; + uint32_t iY = 0xFFu & (iR_iX_iY_C >> 8); + uint32_t iX = 0xFFu & (iR_iX_iY_C >> 16); + uint32_t iR = 0xFFu & (iR_iX_iY_C >> 24); + + uint16_t offsetY = pUPTRT[iY]; + uint16_t offsetX = pUPTRT[iX]; + uint16_t offsetR = pUPTRT[iR]; + + uint32_t pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL); + + MCUXCLPKC_WAITFORREADY(); + + if (0u == ((uint32_t) param_mode & ((uint32_t) MCUXCLPKC_PARAM_PS2 << 8u))) + { + pkc_ctrl |= MCUXCLPKC_SFR_BITMSK(CTRL, GOD1); + MCUXCLPKC_PS1_SETMODE(param_mode); /* Only mode in least significant 8 bits */ + MCUXCLPKC_PS1_SETXY(offsetX, offsetY); + MCUXCLPKC_PS1_SETZR(C, offsetR); + } + else + { + pkc_ctrl |= MCUXCLPKC_SFR_BITMSK(CTRL, GOD2); + MCUXCLPKC_PS2_SETMODE(param_mode); /* Only mode in least significant 8 bits */ + MCUXCLPKC_PS2_SETXY(offsetX, offsetY); + MCUXCLPKC_PS2_SETZR(C, offsetR); + } + + MCUXCLPKC_SFR_WRITE(CTRL, pkc_ctrl); + MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_CalcConst); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_CalcFup) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_CalcFup(mcuxClPkc_PtrFUPEntry_t pUPTR, uint8_t uLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_CalcFup); + + uint32_t pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL) | MCUXCLPKC_SFR_BITMSK(CTRL, GOU) | MCUXCLPKC_SFR_BITMSK(CTRL, CLRCACHE); + MCUXCLPKC_WAITFORREADY(); + + MCUXCLPKC_SFR_WRITE(UPTR, (uint32_t) pUPTR); + MCUXCLPKC_SFR_WRITE(ULEN, (uint32_t) uLength); + + /* Clear PKC UPTRT cache and start calculation of the FUP program. */ + MCUXCLPKC_SFR_WRITE(CTRL, pkc_ctrl); + MCUXCLPKC_PKC_BLOCK_CPU_WORKAROUND(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_CalcFup); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_WaitForFinish) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForFinish(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_WaitForFinish); + + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_WaitForFinish); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_WaitForReady) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_WaitForReady(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_WaitForReady); + + MCUXCLPKC_WAITFORREADY(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_WaitForReady); +} diff --git a/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_ImportExport.c b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_ImportExport.c new file mode 100644 index 000000000..cbeba8f86 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_ImportExport.c @@ -0,0 +1,557 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_ImportExport.c + * @brief mcuxClPkc: implementation of PKC internal import/export functions + */ + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include + + +/** + * [Design] + * This function reverses a byte string in-place (switches the endianness). + * + * The buffer address shall be CPU word (4-byte) aligned. + * + * For platforms not supporting unaligned access to PKC workarea, this function + * accesses to the byte string word-wisely if length is a multiple of CPU wordsize, + * and byte-wisely if length is not a multiple of CPU wordsize. + * + * For platforms supporting unaligned access to PKC workarea, this function + * intentionally declares some memory accesses as UNALIGNED. + * When length = 0, this function does nothing. + * When length = 8n+t, this function accesses the first 4n bytes and the last 4n + * bytes word-wisely. Accesses to the last 4n bytes are declared as UNALIGNED. + * For the t bytes in between, there are 2 scenarios: + * when t = 1~3, this function accesses these t-byte byte-wisely; + * when t = 4~7, this function accesses these t-byte word-wisely. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_SwitchEndianness) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_SwitchEndianness(uint32_t *ptr, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_SwitchEndianness); + if(0u == length) + { + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_SwitchEndianness); + } +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + if (0u != (length % (sizeof(uint32_t)))) + { + uint8_t *ptrL = (uint8_t *) ptr; + uint8_t *ptrH = & ((uint8_t *) ptr)[length]; + + uint32_t remainLength = length / 2u; + while (0u < remainLength) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "ptrH will be in the valid range [ptr+length-(length/2), ptr+length] and ptrL will be in the valid range [ptr, ptr+length/2].") + ptrH--; + uint8_t byteH = *ptrH; + uint8_t byteL = *ptrL; + + *ptrL = byteH; + *ptrH = byteL; + ptrL++; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + remainLength--; + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_SwitchEndianness); + } + + /* When the length is a multiple of CPU word size, fall down to the original implementation. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("ptr is CPU word aligned, and length is a multiple of CPU word size.") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "ptrH32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t *ptrH32 = (uint32_t *) & ((uint8_t *) ptr)[length - 4u]; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() +#else + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("use of UNALIGNED keyword") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "ptrH32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t UNALIGNED *ptrH32 = (uint32_t UNALIGNED *) & ((uint8_t *) ptr)[length - 4u]; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() +#endif + uint32_t *ptrL32 = ptr; + + /* While there are >= 4 bytes to switch the endianness. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3, "both ptrH32 and ptrL32 point into ptr[].") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_ARR36_C, "both ptrH32 and ptrL32 point into ptr[].") + while (ptrH32 >= ptrL32) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_ARR36_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "ptrH32 and ptrL32 will not be dereferenced outside the range [ptr, ptr+length-1] because of the condition (ptrH32 >= ptrL32).") + uint32_t wordL = *ptrL32; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("UNALIGNED keyword is used for ptrH32 definition") + uint32_t wordH = *ptrH32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() + + wordL = MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(wordL); + wordH = MCUXCLMEMORY_SWITCH_4BYTE_ENDIANNESS(wordH); + + *ptrH32 = wordL; + ptrH32--; + *ptrL32 = wordH; + ptrL32++; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + /* Now, ptrH32 = phtL32 - 4 or ptrL32 - 8, nothing more to do. */ +#else + /* If ptrH <= ptrL - 4, nothing more to do. */ + /* If ptrH == ptrL - 3, swap ptrL[0] with ptrH[3] = ptrL[0], i.e., nothing to do. */ + /* If ptrH == ptrL - 2, swap ptrL[0] with ptrH[3] = ptrL[1]. */ + /* If ptrH == ptrL - 1, swap ptrL[0] with ptrH[3] = ptrL[2], and leave ptrL[1] unchanged. */ + uint8_t *ptrL8 = (uint8_t *) ptrL32; + uint8_t *ptrH8 = & ((uint8_t *) ptrH32)[3u]; + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3, "both ptrH8 and ptrL8 point into ptr[].") + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(CERT_ARR36_C, "both ptrH32 and ptrL32 point into ptr[].") + if (ptrH8 > ptrL8) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(CERT_ARR36_C) + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_18_3) + { + uint8_t byteL = *ptrL8; + uint8_t byteH = *ptrH8; + + *ptrH8 = byteL; + *ptrL8 = byteH; + } +#endif + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_SwitchEndianness); +} + + +/** + * [Design] + * This function imports an integer stored as a big-endian octet string to PKC workarea. + * + * (1) clear the target PKC buffer by PKC if the passed length is not equal to (PS1 OPLEN); + * (2) copy the string to the target PKC buffer with offset, (pTarget+offset)[], + * where offset = (0 - length) % (CPU word size); + * (3) switch the endianness of the string (with the offset zero byte(s) in the beginning) + * in-place in the target PKC buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ImportBigEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ImportBigEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_ImportBigEndianToPkc); + + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t * p32Target = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iTarget]); /* Caller shall provide PKC-word aligned operand iTarget. */ + + if (operandSize != length) + { + MCUXCLPKC_FP_CALC_OP1_CONST(iTarget, 0u); + } + + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, "modular arithmetic.") + uint32_t offset = (0u - length) % (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C) + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("offset in range [0,3], and length <= alignedLength <= PKC PS1LEN.") + uint32_t alignedLength = length + offset; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + MCUXCLPKC_WAITFORFINISH(); + + /* PKC buffer size is a multiple of MCUXCLPKC_WORDSIZE (also CPU wordsize). */ + /* When length is not a multiple of CPU word size (i.e., offset != 0), */ + /* there will be offset bytes beyond the specified length of the target. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "offset in range [0,3], and length <= alignedLength <= PKC PS1LEN.") + MCUXCLMEMORY_FP_MEMORY_COPY(& ((uint8_t *) p32Target)[offset], pSource, length); + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Target, alignedLength); /* PKC buffer is CPU word aligned. */ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_ImportBigEndianToPkc, + MCUX_CSSL_FP_CONDITIONAL((operandSize != length), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness) ); +} + + +/** + * [Design] + * This function imports an integer stored as a little-endian octet string to PKC workarea. + * + * (1) clear the target PKC buffer by PKC if the passed length is not equal to (PS1 OPLEN); + * (2) copy the string to the target PKC buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ImportLittleEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ImportLittleEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_ImportLittleEndianToPkc); + + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t * pTarget = MCUXCLPKC_OFFSET2PTR(pOperands[iTarget]); + + if (operandSize != length) + { + MCUXCLPKC_FP_CALC_OP1_CONST(iTarget, 0u); + } + MCUXCLPKC_WAITFORFINISH(); + + MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, length); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_ImportLittleEndianToPkc, + MCUX_CSSL_FP_CONDITIONAL((operandSize != length), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) ); +} + + +/** + * [Design] + * This function exports a PKC operand (with specified length) and stores it as + * a big-endian octet string in the target buffer. + * + * (0) the PKC operand is stored as a little-endian octet string in PKC workarea; + * (1) switch the endianness of the string of "aligned length" in-place in the PKC operand buffer, + * where "aligned length" is equal to length rounding up to a multiple of CPU word size; + * (2) copy the result (a big-endian octet string of the specified length, at + * (pSource+offset)[], where offset = "aligned length" - length) to the target buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ExportBigEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ExportBigEndianFromPkc(uint8_t * pTarget, uint8_t iSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_ExportBigEndianFromPkc); + + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t * p32Source = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iSource]); /* Caller shall provide PKC-word aligned operand iSource. */ + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("modular arithmetic.") + uint32_t offset = (0u - length) % (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("offset in range [0,3], and length <= alignedLength <= PKC PS1LEN.") + uint32_t alignedLength = length + offset; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + MCUXCLPKC_WAITFORFINISH(); + + /* PKC buffer size is a multiple of MCUXCLPKC_WORDSIZE (also CPU wordsize). */ + /* When length is not a multiple of CPU word size (i.e., offset != 0), */ + /* there will be offset bytes beyond the specified length of the source. */ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "offset in range [0,3], and length <= alignedLength <= PKC PS1LEN.") + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Source, alignedLength); /* PKC buffer is CPU word aligned. */ + MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, & ((uint8_t *) p32Source)[offset], length); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_ExportBigEndianFromPkc, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) ); +} + + +/** + * [Design] + * This function exports a PKC operand (with specified length) and stores it as + * a little-endian octet string in the target buffer. + * + * (0) the PKC operand is stored as a little-endian octet string in PKC workarea; + * (1) copy the little-endian octet string of the specified length to the target buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ExportLittleEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_ExportLittleEndianFromPkc(uint8_t *pTarget, uint8_t iSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_ExportLittleEndianFromPkc); + + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + const uint8_t * pSource = MCUXCLPKC_OFFSET2PTR(pOperands[iSource]); + + MCUXCLPKC_WAITFORFINISH(); + MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, length); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_ExportLittleEndianFromPkc, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) ); +} + + +/** + * [Design] + * This function imports an integer stored as a big-endian octet string to PKC workarea, + * in a secure manner. + * + * (1) clear the extra space (from the passed length to (PS1 OPLEN)) of the target PKC buffer by CPU; + * (2) securely copy the string to the target PKC buffer; + * (3) generate a random string (its length = (PS1 OPLEN)) in the temp PKC buffer; + * (4) mask (XOR) the target PKC operand with the temp PKC operand; + * (5) switch the endianness of both strings (target and temp) in-place in the PKC buffers; + * (6) unmask (XOR) the target PKC operand. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_SecureImportBigEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureImportBigEndianToPkc(mcuxClSession_Handle_t pSession, uint16_t iTarget_iTemp, const uint8_t * pSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_SecureImportBigEndianToPkc); + + uint8_t iTemp = (uint8_t) (iTarget_iTemp & 0xFFu); + uint8_t iTarget = (uint8_t) (iTarget_iTemp >> 8); + + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t *p32Temp = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iTemp]); /* Caller shall provide PKC-word aligned operand iTemp. */ + uint32_t *p32Target = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iTarget]); /* Caller shall provide PKC-word aligned operand iTarget. */ + uint8_t *pTarget = (uint8_t* ) p32Target; + + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("length <= operandSize = PKC PS1LEN.") + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear(&pTarget[length], operandSize - length, operandSize - length)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CsslMemoryCopy, + mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Protect(4u, pSource, pTarget, length, length), + pSource, pTarget, length, length) ); + if (MCUXCSSLMEMORY_STATUS_OK != ret_CsslMemoryCopy) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureImportBigEndianToPkc, MCUXCLPKC_STATUS_NOK); + } + +#define MCUXCLPKC_SECIMPORTBE_FP_CALLED_MEMCOPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) + + /* Caution: the whole temp buffer needs to be initialized before PKC XOR */ + /* if the platform requests an explicit memory initialization. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate, mcuxClRandom_ncGenerate(pSession, (uint8_t *) p32Temp, operandSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureImportBigEndianToPkc, MCUXCLPKC_STATUS_NOK); + } + + MCUXCLPKC_FP_CALC_OP1_XOR(iTarget, iTarget, iTemp); + +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + uint32_t alignedLength = (length + (sizeof(uint32_t)) - 1u) & (~ ((sizeof(uint32_t)) - 1u)); + + MCUXCLPKC_WAITFORFINISH(); + + /* Switch endianness of Temp and Target with aligned length. */ + /* Few (0~3) extra bytes will be moved to the beginning of the strings. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Temp, alignedLength); /* PKC buffer is CPU word aligned. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Target, alignedLength); /* PKC buffer is CPU word aligned. */ + + MCUXCLPKC_FP_CALC_OP1_XOR(iTarget, iTarget, iTemp); + + /* Clear the extra byte(s) by right-shifting. */ + MCUXCLPKC_FP_CALC_OP1_SHR(iTarget, iTarget, (alignedLength - length) * 8u); + +#define MCUXCLPKC_SECIMPORTBE_FP_CALLED_REV \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR +#else + MCUXCLPKC_WAITFORFINISH(); + + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Temp, length); /* PKC buffer is CPU word aligned. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Target, length); /* PKC buffer is CPU word aligned. */ + + MCUXCLPKC_FP_CALC_OP1_XOR(iTarget, iTarget, iTemp); + +#define MCUXCLPKC_SECIMPORTBE_FP_CALLED_REV \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR +#endif /* MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS */ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureImportBigEndianToPkc, MCUXCLPKC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLPKC_SECIMPORTBE_FP_CALLED_MEMCOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR, + MCUXCLPKC_SECIMPORTBE_FP_CALLED_REV ); +} + + +/** + * [Design] + * This function imports an integer stored as a little-endian octet string to PKC workarea, + * in a secure manner. + * + * (1) clear the extra space (from the passed length to (PS1 OPLEN)) of the target PKC buffer by CPU; + * (2) securely copy the string to the target PKC buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_SecureImportLittleEndianToPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureImportLittleEndianToPkc(uint8_t iTarget, const uint8_t * pSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_SecureImportLittleEndianToPkc); + + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint8_t *pTarget = MCUXCLPKC_OFFSET2PTR(pOperands[iTarget]); + + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("length <= operandSize = PKC PS1LEN.") + MCUXCLMEMORY_FP_MEMORY_CLEAR(&pTarget[length], operandSize - length); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CsslMemoryCopy, + mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Protect(4u, pSource, pTarget, length, length), + pSource, pTarget, length, length) ); + if (MCUXCSSLMEMORY_STATUS_OK != ret_CsslMemoryCopy) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureImportLittleEndianToPkc, MCUXCLPKC_STATUS_NOK); + } + +#define MCUXCLPKC_SECIMPORTLE_FP_CALLED_MEMCOPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureImportLittleEndianToPkc, MCUXCLPKC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLPKC_SECIMPORTLE_FP_CALLED_MEMCOPY ); +} + + +/** + * [Design] + * This function exports a PKC operand (with specified length) and stores it as + * a big-endian octet string in the target buffer, in a secure manner. + * + * (0) the source PKC operand is stored as a little-endian octet string in PKC workarea; + * (1) generate a random byte string of the specified length in the temp PKC operand; + * (2) mask (XOR) the source PKC operand with the temp PKC operand; + * (3) switch the endianness of both strings (source and temp) in-place in the PKC buffers; + * (4) unmask (XOR) the source PKC operand; + * (5) securely copy the result (a big-endian octet string, of the specified length) + * to the target buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_SecureExportBigEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureExportBigEndianFromPkc(mcuxClSession_Handle_t pSession, uint8_t * pTarget, uint16_t iSource_iTemp, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_SecureExportBigEndianFromPkc); + + uint8_t iTemp = (uint8_t) (iSource_iTemp & 0xFFu); + uint8_t iSource = (uint8_t) (iSource_iTemp >> 8); + + const uint32_t operandSize = MCUXCLPKC_PS1_GETOPLEN(); + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + uint32_t *p32Temp = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iTemp]); /* Caller shall provide PKC-word aligned operand iTemp. */ + uint32_t *p32Source = MCUXCLPKC_OFFSET2PTRWORD(pOperands[iSource]); /* Caller shall provide PKC-word aligned operand iSource. */ + + MCUXCLPKC_WAITFORFINISH(); + + /* Caution: the whole temp buffer needs to be initialized before PKC XOR */ + /* if the platform requests an explicit memory initialization. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate, mcuxClRandom_ncGenerate(pSession, (uint8_t *) p32Temp, operandSize)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureExportBigEndianFromPkc, MCUXCLPKC_STATUS_NOK); + } + + MCUXCLPKC_FP_CALC_OP1_XOR(iSource, iSource, iTemp); + +#ifdef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + uint32_t alignedLength = (length + (sizeof(uint32_t)) - 1u) & (~ ((sizeof(uint32_t)) - 1u)); + + MCUXCLPKC_WAITFORFINISH(); + + /* Switch endianness of Temp and Source with aligned length. */ + /* Few (0~3) extra bytes will be moved to the beginning of the strings. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Temp, alignedLength); /* PKC buffer is CPU word aligned. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Source, alignedLength); /* PKC buffer is CPU word aligned. */ + + MCUXCLPKC_FP_CALC_OP1_XOR(iSource, iSource, iTemp); + + /* Clear the extra byte(s) by right-shifting. */ + MCUXCLPKC_FP_CALC_OP1_SHR(iSource, iSource, (alignedLength - length) * 8u); + +#define MCUXCLPKC_SECEXPORTBE_FP_CALLED_REV \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR, \ + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR +#else + MCUXCLPKC_WAITFORFINISH(); + + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Temp, length); /* PKC buffer is CPU word aligned. */ + MCUXCLPKC_FP_SWITCHENDIANNESS(p32Source, length); /* PKC buffer is CPU word aligned. */ + + MCUXCLPKC_FP_CALC_OP1_XOR(iSource, iSource, iTemp); + +#define MCUXCLPKC_SECEXPORTBE_FP_CALLED_REV \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness), \ + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR +#endif + + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CsslMemoryCopy, + mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Protect(4u, (const uint8_t *) p32Source, pTarget, length, length), + (const uint8_t *) p32Source, pTarget, length, length) ); + if (MCUXCSSLMEMORY_STATUS_OK != ret_CsslMemoryCopy) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureExportBigEndianFromPkc, MCUXCLPKC_STATUS_NOK); + } + +#define MCUXCLPKC_SECEXPORTBE_FP_CALLED_MEMCOPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureExportBigEndianFromPkc, MCUXCLPKC_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_XOR, + MCUXCLPKC_SECEXPORTBE_FP_CALLED_REV, + MCUXCLPKC_SECEXPORTBE_FP_CALLED_MEMCOPY ); +} + + +/** + * [Design] + * This function exports a PKC operand (with specified length) and stores it as + * a little-endian octet string in the target buffer, in a secure manner. + * + * (0) the PKC operand is stored as a little-endian octet string in PKC workarea; + * (1) securely copy the little-endian octet string of the specified length to the target buffer. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_SecureExportLittleEndianFromPkc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_SecureExportLittleEndianFromPkc(uint8_t * pTarget, uint8_t iSource, uint32_t length) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_SecureExportLittleEndianFromPkc); + + const uint16_t * pOperands = MCUXCLPKC_GETUPTRT(); + const uint8_t * pSource = MCUXCLPKC_OFFSET2PTR(pOperands[iSource]); + + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_CsslMemoryCopy, + mcuxCsslMemory_Copy(mcuxCsslParamIntegrity_Protect(4u, pSource, pTarget, length, length), + pSource, pTarget, length, length) ); + if (MCUXCSSLMEMORY_STATUS_OK != ret_CsslMemoryCopy) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureExportLittleEndianFromPkc, MCUXCLPKC_STATUS_NOK); + } + +#define MCUXCLPKC_SECEXPORTLE_FP_CALLED_MEMCOPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy) + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_SecureExportLittleEndianFromPkc, MCUXCLPKC_STATUS_OK, + MCUXCLPKC_SECEXPORTLE_FP_CALLED_MEMCOPY ); +} diff --git a/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Initialize.c b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Initialize.c new file mode 100644 index 000000000..cc933d740 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_Initialize.c @@ -0,0 +1,164 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2014-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_Initialize.c + * @brief PKC initialize and deinitialize functions + */ + + +#include +#include +#include +#include +#include + +#include +#include +#include + + + + +/** + * [Design] + * This function initializes PKC hardware in the following steps: + * (1) if PKC is in STOP, clear STOP bit according to PKC specification; + * (2) backup PKC state (except STOP bit) if required (pState != NULL); + * (3) if PKC is not in RESET, wait any on-going calculation; + * (4) initialize and set PKC according to PKC specification. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_Initialize, mcuxClPkc_PkcInitializeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Initialize(mcuxClPkc_State_t *pState) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_Initialize); + + /* Clear STOP bit if it has been set. */ + uint32_t pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL); + if (0u != (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, STOP))) + { + MCUXCLPKC_SFR_WRITE(CTRL, pkc_ctrl & (~ MCUXCLPKC_SFR_BITMSK(CTRL, STOP))); + + /* Poll the STOP bit until it is cleared. */ + do + { + pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL); + } while(0u != (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, STOP))); + } + + /* Backup PKC settings except STOP bit. */ + if (NULL != pState) + { + pState->ctrl = (uint16_t) pkc_ctrl; + pState->cfg = (uint16_t) MCUXCLPKC_SFR_READ(CFG); + } + + /* Wait any on-going calculation and then set RESET bit, if RESET bit is not set. */ + if (0u == (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, RESET))) + { + MCUXCLPKC_WAITFORFINISH(); + + /* Set PKC RESET bit. */ + MCUXCLPKC_SFR_WRITE(CTRL, MCUXCLPKC_SFR_BITMSK(CTRL, RESET)); + + /* Poll the RESET bit until it is set. */ + while (0u == (MCUXCLPKC_SFR_BITREAD(CTRL, RESET))) + {} + } + + /* Configure PKC. */ + const uint32_t pkcCfg = MCUXCLPKC_SFR_BITMSK(CFG, IDLEOP) + | MCUXCLPKC_SFR_BITMSK(CFG, CLKRND) + | MCUXCLPKC_SFR_BITMSK(CFG, REDMULNOISE) + | MCUXCLPKC_SFR_CFG_RNDDLY_NODLY; + + MCUXCLPKC_SFR_WRITE(CFG, pkcCfg); + + + /* Configure PKC and clear RESET bit. */ + MCUXCLPKC_SFR_WRITE(CTRL, MCUXCLPKC_SFR_BITMSK(CTRL, CLRCACHE) + | MCUXCLPKC_SFR_BITMSK(CTRL, CACHE_EN) + | MCUXCLPKC_SFR_CTRL_REDMUL_FULLSZ ); + + /* Poll the RESET bit until it is cleared. */ + while (0u != (MCUXCLPKC_SFR_BITREAD(CTRL, RESET))) + {} + + /* Poll the PW_READY bit until it is set, on supported platforms. */ + MCUXCLPKC_PKC_WAIT_PW_READY(); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_Initialize); +} + + +/** + * [Design] + * This function deinitializes PKC hardware in the following steps: + * (1) if PKC is in STOP, clear STOP bit according to PKC specification; + * (2) if PKC is not in RESET, wait any on-going calculation, and then set PKC RESET bit; + * (3) clear PKC SFRs; + * (4) restore PKC state (except STOP bit) if it is provided (pState != NULL). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_Deinitialize, mcuxClPkc_PkcDeInitializeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_Deinitialize(const mcuxClPkc_State_t *pState) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_Deinitialize); + + /* Clear STOP bit if it has been set. */ + uint32_t pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL); + if (0u != (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, STOP))) + { + MCUXCLPKC_SFR_WRITE(CTRL, pkc_ctrl & (~ MCUXCLPKC_SFR_BITMSK(CTRL, STOP))); + + /* Poll the STOP bit until it is cleared. */ + do + { + pkc_ctrl = MCUXCLPKC_SFR_READ(CTRL); + } while(0u != (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, STOP))); + } + + /* Wait any on-going calculation and then set RESET bit, if RESET bit is not set. */ + if (0u == (pkc_ctrl & MCUXCLPKC_SFR_BITMSK(CTRL, RESET))) + { + MCUXCLPKC_WAITFORFINISH(); + + /* Set PKC RESET bit. */ + MCUXCLPKC_SFR_WRITE(CTRL, MCUXCLPKC_SFR_BITMSK(CTRL, RESET)); + + /* Poll the RESET bit until it is set. */ + while (0u == (MCUXCLPKC_SFR_BITREAD(CTRL, RESET))) + {} + } + + /* Clear SFRs. */ + MCUXCLPKC_SFR_WRITE(MODE1, 0u); + MCUXCLPKC_SFR_WRITE(XYPTR1, 0u); + MCUXCLPKC_SFR_WRITE(ZRPTR1, 0u); + MCUXCLPKC_SFR_WRITE(LEN1, 0u); + MCUXCLPKC_SFR_WRITE(MODE2, 0u); + MCUXCLPKC_SFR_WRITE(XYPTR2, 0u); + MCUXCLPKC_SFR_WRITE(ZRPTR2, 0u); + MCUXCLPKC_SFR_WRITE(LEN2, 0u); + MCUXCLPKC_SFR_WRITE(UPTR, 0u); + MCUXCLPKC_SFR_WRITE(UPTRT, 0u); + MCUXCLPKC_SFR_WRITE(ULEN, 0u); + + /* Restore configuration if provided, except STOP bit. */ + if (NULL != pState) + { + MCUXCLPKC_SFR_WRITE(CFG, (uint32_t) pState->cfg); + MCUXCLPKC_SFR_WRITE(CTRL, (uint32_t) pState->ctrl); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_Deinitialize); +} diff --git a/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_UPTRT.c b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_UPTRT.c new file mode 100644 index 000000000..b07763611 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPkc/src/mcuxClPkc_UPTRT.c @@ -0,0 +1,140 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPkc_UPTRT.c + * @brief PKC UPTRT (Universal pointer FUP table) generation function + */ + + +#include +#include +#include + +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_GenerateUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClPkc_GenerateUPTRT( + uint16_t *pUPTRT, + const uint8_t *pBaseBuffer, + uint16_t bufferLength, + uint8_t noOfBuffer) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_GenerateUPTRT); + + uint32_t offset = MCUXCLPKC_PTR2OFFSET(pBaseBuffer); + + for (uint32_t idx = 0; idx < noOfBuffer; idx++) + { + pUPTRT[idx] = (uint16_t) offset; + offset += bufferLength; // TODO-9364: Open violaation to INT30-C for rt700 and s540 + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClPkc_GenerateUPTRT); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_RandomizeUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_RandomizeUPTRT( + mcuxClSession_Handle_t pSession, + uint16_t *pUPTRT, + uint8_t noOfBuffer) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_RandomizeUPTRT); + + MCUX_CSSL_FP_LOOP_DECL(Loop); + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_LOOP_ITERATIONS(Loop, ((uint32_t)noOfBuffer - 1U))); + + /* Randomize entries in UPTRT by Knuth shuffle. */ + for (uint32_t idx = noOfBuffer; idx > 1u; idx--) + { + MCUX_CSSL_FP_LOOP_ITERATION(Loop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + + + /* Generate a random number in the range [0, idx-1], where idx <= noOfBuffer <= 255. */ + uint32_t random32; + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate, mcuxClRandom_ncGenerate(pSession, (uint8_t *) &random32, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_RandomizeUPTRT, MCUXCLPKC_STATUS_NOK); + } + uint32_t random8 = random32 >> 8; + random8 *= idx; + random8 >>= 24; + + /* Swap. */ + uint16_t temp0 = pUPTRT[idx - 1u]; + uint16_t temp1 = pUPTRT[random8]; + pUPTRT[random8] = temp0; + pUPTRT[idx - 1u] = temp1; + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_RandomizeUPTRT, MCUXCLPKC_STATUS_OK); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPkc_ReRandomizeUPTRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPkc_Status_t) mcuxClPkc_ReRandomizeUPTRT( + mcuxClSession_Handle_t pSession, + uint16_t *pUPTRT, + uint16_t bufferLength, + uint8_t noOfBuffer) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPkc_ReRandomizeUPTRT); + + MCUX_CSSL_FP_LOOP_DECL(Loop); + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_LOOP_ITERATIONS(Loop, ((uint32_t)noOfBuffer - 1U))); + + /* Randomize entries in UPTRT by Knuth shuffle. */ + for (uint32_t idx = noOfBuffer; idx > 1u; idx--) + { + MCUX_CSSL_FP_LOOP_ITERATION(Loop, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate)); + /* Generate a random number in the range [0, idx-1], where idx <= noOfBuffer <= 255. */ + uint32_t random32; + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate, mcuxClRandom_ncGenerate(pSession, (uint8_t *) &random32, sizeof(uint32_t))); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_ReRandomizeUPTRT, MCUXCLPKC_STATUS_NOK); + } + uint32_t random8 = random32 >> 8u; + random8 *= idx; + random8 >>= 24u; + + /* Swap. */ + uint16_t offset0 = pUPTRT[idx - 1u]; + uint16_t offset1 = pUPTRT[random8]; + pUPTRT[random8] = offset0; + pUPTRT[idx - 1u] = offset1; + + /* Caller shall provide UPTR table with all offsets being exactly a multiple of MCUXCLPKC_WORDSIZE. */ + uint32_t *ptr0 = MCUXCLPKC_OFFSET2PTRWORD(offset0); + uint32_t *ptr1 = MCUXCLPKC_OFFSET2PTRWORD(offset1); + + /* Swap contents of the two buffers, of which the size is a multiple of CPU word. */ + for (uint32_t i = 0u; i < ((uint32_t) bufferLength / 4u); i++) + { + uint32_t temp0 = ptr0[i]; + uint32_t temp1 = ptr1[i]; + ptr1[i] = temp0; + ptr0[i] = temp1; + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPkc_ReRandomizeUPTRT, MCUXCLPKC_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal.h b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal.h new file mode 100644 index 000000000..b2648f7a1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPrng_Internal.h + * @brief Top level header of mcuxClPrng component + * + * @defgroup mcuxClPrng mcuxClPrng + * @brief component of Prng generation + */ + +#ifndef MCUXCLPRNG_INTERNAL_H_ +#define MCUXCLPRNG_INTERNAL_H_ + +#include +#include +#include +#include + +#endif /* MCUXCLPRNG_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Constants.h new file mode 100644 index 000000000..ceae2317c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Constants.h @@ -0,0 +1,56 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPrng_Internal_Constants.h + * @brief Constant definitions of mcuxClPrng component + */ + + +#ifndef MCUXCLPRNG_INTERNAL_CONSTANTS_H_ +#define MCUXCLPRNG_INTERNAL_CONSTANTS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Constants of mcuxClPrng */ +/**********************************************************/ +/** + * @defgroup mcuxClPrng_Internal_Constants mcuxClPrng_Internal_Constants + * @brief Defines all contstants of @ref mcuxClPrng + * @ingroup mcuxClPrng + * @{ + */ + +/** @addtogroup MCUXCLPRNG_STATUS_ + * mcuxClPrng return code definitions + * @{ */ +#define MCUXCLPRNG_STATUS_ERROR ((mcuxClPrng_Status_t) 0x0FF55330u) ///< An error occurred during the PRNG operation +#define MCUXCLPRNG_STATUS_OK ((mcuxClPrng_Status_t) 0x0FF52E03u) ///< PRNG operation returned successfully +#define MCUXCLPRNG_STATUS_FAULT_ATTACK ((mcuxClPrng_Status_t) 0x0FF5F0F0u) ///< A fault attack is detected +/** @} */ + + +/** + * @} + */ /* mcuxClPrng_Constants */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPRNG_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_ELS.h b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_ELS.h new file mode 100644 index 000000000..a89d69599 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_ELS.h @@ -0,0 +1,49 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPrng_Internal_ELS.h + * @brief Functionality required to draw pseudorandom data from ELS + */ + + +#ifndef MCUXCLPRNG_INTERNAL_ELS_H_ +#define MCUXCLPRNG_INTERNAL_ELS_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Non-cryptographic PRNG data word generation function. + * + * This function returns a non-cryptographic random data word + * + * @return 32-bit random data + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPrng_generate_word) +static inline uint32_t mcuxClPrng_generate_word(void) +{ + return mcuxClEls_readPrngOut(); // read from PRNG SFR +} + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPRNG_INTERNAL_ELS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Functions.h new file mode 100644 index 000000000..b90e39c56 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Functions.h @@ -0,0 +1,73 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPrng_Internal_Functions.h + * @brief Top level APIs of mcuxClPrng component + */ + +#ifndef MCUXCLPRNG_INTERNAL_FUNCTIONS_H_ +#define MCUXCLPRNG_INTERNAL_FUNCTIONS_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* APIs of mcuxClPrng */ +/**********************************************************/ +/** + * @brief Non-cryptographic PRNG initialization function. + * + * This function performs the initialization of the non-cryptographic random number + * generator. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPrng_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPrng_Status_t) mcuxClPrng_init( + void +); + +/** + * @brief Non-cryptographic PRNG data generation function. + * + * This function generates non-cryptographic random data + * + * @param [out] pOut Buffer in which the generated random data must be + * written. + * @param [in] outLength Number of random data bytes that must be written in the + * @p pOut buffer. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClPrng_generate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPrng_Status_t) mcuxClPrng_generate( + uint8_t * pOut, + uint32_t outLength +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/** + * @} + */ /* mcuxClPrng_Internal_Functions */ + +#endif /* MCUXCLPRNG_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Types.h b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Types.h new file mode 100644 index 000000000..fcba7b731 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/inc/internal/mcuxClPrng_Internal_Types.h @@ -0,0 +1,56 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClPrng_Internal_Types.h + * @brief Type definitions of mcuxClPrng component + */ + + +#ifndef MCUXCLPRNG_INTERNAL_TYPES_H_ +#define MCUXCLPRNG_INTERNAL_TYPES_H_ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Types of mcuxClPrng */ +/**********************************************************/ +/** + * @defgroup mcuxClPrng_Internal_Types mcuxClPrng_Internal_Types + * @brief Defines all types of @ref mcuxClPrng + * @ingroup mcuxClPrng + * @{ + */ + +/** + * @brief Type for status codes of mcuxClPrng component functions. + * + * This type provides information about the status of the Prng operation + * that has been performed. + */ +typedef uint32_t mcuxClPrng_Status_t; + +/** + * @} + */ /* mcuxClPrng_Internal_Types */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLPRNG_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClPrng/src/mcuxClPrng_ELS.c b/components/els_pkc/src/comps/mcuxClPrng/src/mcuxClPrng_ELS.c new file mode 100644 index 000000000..0795f8471 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClPrng/src/mcuxClPrng_ELS.c @@ -0,0 +1,182 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClPrng_ELS.c + * @brief Implementation of the non-cryptographic PRNG functions using ELS. */ + +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPrng_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPrng_Status_t) mcuxClPrng_init( + void +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPrng_init); + +#ifdef MCUXCL_FEATURE_ELS_PRND_INIT + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_Init, mcuxClEls_Prng_Init_Async()); + if(MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_Prng_Init) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_Init_Async)); + } + else if(MCUXCLELS_STATUS_OK_WAIT != ret_Prng_Init) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Wait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_LEVEL1_ERROR(ret_Wait)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_Init_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK != ret_Wait) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_Init_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + +#else /* MCUXCL_FEATURE_ELS_PRND_INIT */ + + /* Check whether the current security strength is sufficient. */ + mcuxClEls_HwState_t hwState = {0}; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_GetHwState, mcuxClEls_GetHwState(&hwState)); + if(MCUXCLELS_STATUS_OK != ret_GetHwState) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + + /* If the security strength is already sufficient, finish here. */ + if((uint8_t)MCUXCLELS_STATUS_DRBGENTLVL_NONE != hwState.bits.drbgentlvl) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState)); + } + + /** + * If the current security strength is not sufficient, do the init procedure: + * Loop through the key slots until an unused slot is found. + * Delete that key in order to force PRNG initialization. + */ + mcuxClEls_KeyProp_t keyProp = {0}; + uint32_t keyIdx = 0u; + + for(keyIdx = 0u; keyIdx < MCUXCLELS_KEY_SLOTS; keyIdx++) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_GetKeyProperties, mcuxClEls_GetKeyProperties(keyIdx, &keyProp)); + if(MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_GetKeyProperties) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState), + (keyIdx + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties)); + } + else if(MCUXCLELS_STATUS_OK != ret_GetKeyProperties) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + if ((uint8_t)MCUXCLELS_KEYPROPERTY_ACTIVE_FALSE == keyProp.bits.kactv) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_KeyDelete_Async, mcuxClEls_KeyDelete_Async(keyIdx)); + if(MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_KeyDelete_Async) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState), + (keyIdx + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async)); + } + else if(MCUXCLELS_STATUS_OK_WAIT != ret_KeyDelete_Async) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Wait2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_LEVEL1_ERROR(ret_Wait2)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState), + (keyIdx + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if(MCUXCLELS_STATUS_OK != ret_Wait2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Assume PRNG is properly initialized. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState), + (keyIdx + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + } + } + + /* PRNG could not be properly initialized. No free key slot? */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_init, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetHwState), + MCUXCLELS_KEY_SLOTS * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties)); + +#endif /* MCUXCL_FEATURE_ELS_PRND_INIT */ +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClPrng_generate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClPrng_Status_t) mcuxClPrng_generate( + uint8_t * pOut, + uint32_t outLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClPrng_generate); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom, mcuxClEls_Prng_GetRandom(pOut, outLength)); + if(MCUXCLELS_STATUS_HW_PRNG == ret_Prng_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_generate, MCUXCLPRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom)); + } + else if (MCUXCLELS_STATUS_OK != ret_Prng_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_generate, MCUXCLPRNG_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClPrng_generate, MCUXCLPRNG_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Prng_GetRandom)); + } +} diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Memory.h b/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Memory.h new file mode 100644 index 000000000..531ac0058 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Memory.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom_Internal_Memory.h + * @brief Provides macros for usage and FP balancing of memory options depneding on the platform + */ + +#ifndef MCUXCLRANDOM_INTERNAL_MEMORY_H_ +#define MCUXCLRANDOM_INTERNAL_MEMORY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#define MCUXCLRANDOM_SECURECOPY(callerID, errorReturn, pTarget, pSource, length) \ + do{ \ + MCUXCLMEMORY_FP_MEMORY_COPY(pTarget, pSource, length); \ + } while(false) + +#define MCUXCLRANDOM_SECURECLEAR(callerID, errorReturn, pTarget, length) \ + do{ \ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pTarget, length); \ + } while(false) + +#define MCUXCLRANDOM_FP_CALLED_SECURECOPY MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) + +#define MCUXCLRANDOM_FP_CALLED_SECURECLEAR MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Types.h b/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Types.h new file mode 100644 index 000000000..7863710a0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/internal/mcuxClRandom_Internal_Types.h @@ -0,0 +1,111 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom_Internal_Types.h + * @brief Internal type definitions of mcuxClRandom component + */ + +#ifndef MCUXCLRANDOM_INTERNAL_TYPES_H_ +#define MCUXCLRANDOM_INTERNAL_TYPES_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Function prototype for init function pointer in OperationMode structure. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandom_initFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandom_initFunction_t)( + mcuxClSession_Handle_t session +)); + +/** + * @brief Function prototype for reseed function pointer in OperationMode structure. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandom_reseedFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (*mcuxClRandom_reseedFunction_t)( + mcuxClSession_Handle_t session +)); + +/** + * @brief Function prototype for generate function pointer in OperationMode structure. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandom_generateFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (*mcuxClRandom_generateFunction_t)( + mcuxClSession_Handle_t session, + uint8_t * pOut, + uint32_t outLength +)); + +/** + * @brief Function prototype for selftest function pointer in OperationMode structure. + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandom_selftestFunction_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (*mcuxClRandom_selftestFunction_t)( + mcuxClSession_Handle_t session, + mcuxClRandom_Mode_t mode +)); + +/** + * @brief Random operation mode descriptor structure + * + * This structure is used to store all information needed in the top level Random DRBG functions, + * determines which mode the DRBG shall be operated in (normal, test or patch mode) and specifies + * pointers to functions implementing the DRBG in the chosen operation mode. + */ +typedef struct +{ + /* Function pointers for DRBG functions */ + mcuxClRandom_initFunction_t initFunction; ///< Function to be called for DRBG instantiation depending on the chosen operationMode + mcuxClRandom_reseedFunction_t reseedFunction; ///< Function to be called for DRBG reseeding depending on the chosen operationMode + mcuxClRandom_generateFunction_t generateFunction; ///< Function to be called for DRBG random number generation depending on the chosen operationMode + mcuxClRandom_selftestFunction_t selftestFunction; ///< Function to be called for DRBG self testing depending on the chosen operationMode + + /* Protection tokens for DRBG functions */ + uint32_t protectionTokenInitFunction; ///< Protection token of DRBG init function + uint32_t protectionTokenReseedFunction; ///< Protection token of DRBG reseed function + uint32_t protectionTokenGenerateFunction; ///< Protection token of DRBG generate function + uint32_t protectionTokenSelftestFunction; ///< Protection token of DRBG selftest function + + /* Operation mode definition */ + uint32_t operationMode; ///< operationMode +} mcuxClRandom_OperationModeDescriptor_t; + +/** + * @brief Random mode descriptor structure + * + * This structure stores all information needed to operate a DRBG in the chosen mode. + */ +struct mcuxClRandom_ModeDescriptor +{ + const mcuxClRandom_OperationModeDescriptor_t *pOperationMode; ///< pointer to top level information about the DRBG mode operated in (NORMALMODE, TESTMODE, ELSMODE, PATCHMODE) + const void *pDrbgMode; ///< pointer to DRBG specific information depending on the chosen mode + uint32_t auxParam; ///< auxiliary parameter depending on the chosen mode + uint32_t contextSize; ///< size of context + uint16_t securityStrength; ///< supported security strength of DRBG +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom.h b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom.h new file mode 100644 index 000000000..6e194512e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom.h + * @brief Top level header of mcuxClRandom component + * + * @defgroup mcuxClRandom mcuxClRandom + * @brief component of random number generation + */ + +#ifndef MCUXCLRANDOM_H_ +#define MCUXCLRANDOM_H_ + +#include // Exported features flags header + +#include +#include +#include + +#endif /* MCUXCLRANDOM_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Constants.h b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Constants.h new file mode 100644 index 000000000..fca1fe61d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Constants.h @@ -0,0 +1,58 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom_Constants.h + * @brief Constant definitions of mcuxClRandom component + */ + + +#ifndef MCUXCLRANDOM_CONSTANTS_H_ +#define MCUXCLRANDOM_CONSTANTS_H_ + + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Constants of mcuxClRandom */ +/**********************************************************/ +/** + * @defgroup mcuxClRandom_Constants mcuxClRandom_Constants + * @brief Defines all contstants of @ref mcuxClRandom + * @ingroup mcuxClRandom + * @{ + */ + +/** @addtogroup MCUXCLRANDOM_STATUS_ + * mcuxClRandom return code definitions + * @{ */ +#define MCUXCLRANDOM_STATUS_ERROR 0x0BBB5330u ///< Random function returned error +#define MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH 0x0BBB5334u ///< Security strength of given RNG lower than requested +#define MCUXCLRANDOM_STATUS_INVALID_PARAM 0x0BBB53F8u ///< Random function parameter invalid +#define MCUXCLRANDOM_STATUS_OK 0x0BBB2E03u ///< Random function returned successfully +#define MCUXCLRANDOM_STATUS_FAULT_ATTACK 0x0BBBF0F0u ///< Random function returned fault attack +/** @} */ + +/** + * @} + */ /* mcuxClRandom_Constants */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Functions.h b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Functions.h new file mode 100644 index 000000000..2fa876df0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Functions.h @@ -0,0 +1,190 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom_Functions.h + * @brief Top level APIs of mcuxClRandom component + */ + +#ifndef MCUXCLRANDOM_FUNCTIONS_H_ +#define MCUXCLRANDOM_FUNCTIONS_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Public APIs of mcuxClRandom */ +/**********************************************************/ +/** + * @defgroup mcuxClRandom_Functions mcuxClRandom_Functions + * @brief Defines all functions of @ref mcuxClRandom + * @ingroup mcuxClRandom + * @{ + */ + +/** + * @brief Random data generator initialization function. + * + * This function performs the initialization of a random data generator. This + * operation initializes the Random context referenced in the session handle. + * + * @param [in] pSession Handle for the current CL session. + * @param [in] pContext Pointer to a Random data context buffer large enough + * to hold the context for the selected @p mode + * @param [in] mode Mode of operation for random data generator. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_init( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Context_t pContext, + mcuxClRandom_Mode_t mode +); /* init */ + +/** + * @brief Random data generator reseed function. + * + * This function performs the reseeding of a random data generator. This + * operation fetches a fresh seed from a TRNG and updates the state in the + * Random context referenced in the session handle. + * + * @param [in] pSession Handle for the current CL session. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_reseed) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_reseed( + mcuxClSession_Handle_t pSession +); /* reseed */ + +/** + * @brief Random data generation function. + * + * This function generates random data based on the information contained in + * the Random context referenced in the session handle. + * + * @param [in] pSession Handle for the current CL session. + * @param [out] pOut Buffer in which the generated random data must be + * written. + * @param [in] outLength Number of random data bytes that must be written in the + * @p pOut buffer. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_generate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_generate( + mcuxClSession_Handle_t pSession, + uint8_t * pOut, + uint32_t outLength +); /* generate */ + +/** + * @brief Random data generator uninitialization function. + * + * This function performs the cleanup of a random data generator. This + * operation cleans up the Random context referenced in the session handle. + * + * @param [in] pSession Handle for the current CL session. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_uninit) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_uninit( + mcuxClSession_Handle_t pSession +); /* uninit */ + +/** + * @brief Random data generator self-test function. + * + * This function performs a series of selft-tests on the random data + * generator. These tests are performed on the random data generator defined + * by Random context referenced in the session handle. + * + * @param [in] pSession Handle for the current CL session. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_selftest) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_selftest( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Mode_t mode +); /* health test */ + +/** + * @brief Random data generator security strength check. + * + * This function reports whether the the random data generator can provide the + * requested security strength. + * + * @param [in] pSession Handle for the current CL session. + * @param [in] securityStrength Requested security strength in bits. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_checkSecurityStrength) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_checkSecurityStrength( + mcuxClSession_Handle_t pSession, + uint32_t securityStrength +); /* security strength check */ + +/** + * @brief Non-cryptographic PRNG initialization function. + * + * This function performs the initialization of the non-cryptographic random number + * generator. + * + * @param [in] pSession Handle for the current CL session. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_ncInit) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncInit( + mcuxClSession_Handle_t pSession +); /* LE init */ + +/** + * @brief Non-cryptographic PRNG data generation function. + * + * This function generates non-cryptographic random data + * + * @param [in] pSession Handle for the current CL session. + * @param [out] pOut Buffer in which the generated random data must be + * written. + * @param [in] outLength Number of random data bytes that must be written in the + * @p pOut buffer. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandom_ncGenerate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncGenerate( + mcuxClSession_Handle_t pSession, + uint8_t * pOut, + uint32_t outLength +); /* LE generate */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/** + * @} + */ /* mcuxClRandom_Functions */ + +#endif /* MCUXCLRANDOM_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Types.h b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Types.h new file mode 100644 index 000000000..7c0bdd197 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/inc/mcuxClRandom_Types.h @@ -0,0 +1,120 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandom_Types.h + * @brief Type definitions of mcuxClRandom component + */ + + +#ifndef MCUXCLRANDOM_TYPES_H_ +#define MCUXCLRANDOM_TYPES_H_ + +#include // Exported features flags header + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Types of mcuxClRandom */ +/**********************************************************/ +/** + * @defgroup mcuxClRandom_Types mcuxClRandom_Types + * @brief Defines all types of @ref mcuxClRandom + * @ingroup mcuxClRandom + * @{ + */ + +/** + * @brief Type for status codes of mcuxClRandom component functions. + * + * This type provides information about the status of the Random operation + * that has been performed. + */ +typedef uint32_t mcuxClRandom_Status_t; + +/** + * @brief Random context structure + * + * This structure is used to store the information about the current random + * data generator and the relevant internal state. + */ +struct mcuxClRandom_Context; + +/** + * @brief Random context type + * + * This type is used to store the information about the current random data + * generator and the relevant internal state. + */ +typedef struct mcuxClRandom_Context mcuxClRandom_ContextDescriptor_t; + +/** + * @brief Random context type + * + * This type is used to refer to a Random context. + */ +typedef mcuxClRandom_ContextDescriptor_t * mcuxClRandom_Context_t; + +/** + * @brief Random data generation mode/algorithm descriptor structure + * + * This structure captures all the information that the Random interfaces need + * to know about a particular Random data generation mode/algorithm. + */ +struct mcuxClRandom_ModeDescriptor; + +/** + * @brief Random data generation mode/algorithm descriptor type + * + * This type captures all the information that the Random interfaces need to + * know about a particular Random data generation mode/algorithm. + */ +typedef struct mcuxClRandom_ModeDescriptor mcuxClRandom_ModeDescriptor_t; + +/** + * @brief Random data generation mode/algorithm type + * + * This type is used to refer to a Random data generation mode/algorithm. + */ +typedef const mcuxClRandom_ModeDescriptor_t * mcuxClRandom_Mode_t; + +/** + * @brief Random config structure + * + * This structure is used to store context and mode pointers. + */ +struct mcuxClRandom_Config { + mcuxClRandom_Mode_t mode; ///< Random data generation mode/algorithm + mcuxClRandom_Context_t ctx; ///< Context for the Rng +}; + +/** + * @brief Random config type + * + * This type is used to store context and mode. + */ +typedef struct mcuxClRandom_Config mcuxClRandom_Config_t; + +/** + * @} + */ /* mcuxClRandom_Types */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_DRBG.c b/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_DRBG.c new file mode 100644 index 000000000..573849345 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_DRBG.c @@ -0,0 +1,219 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRandom_DRBG.c + * @brief Implementation of the Random component which provides APIs for + * handling of DRBG random number generators. This file implements the functions + * declared in mcuxClRandom.h. */ + +#include +#include +#include + +#include +#include + +/** + * @brief This function verifies a Random mode + * + * @param mode[in] Random mode to be verified + * + * @return Status of the operation: + * @retval #MCUXCLRANDOM_STATUS_OK if the Random mode is valid + * @retval #MCUXCLRANDOM_STATUS_INVALID_PARAM if the Random mode is invalid + * @retval #MCUXCLRANDOM_STATUS_FAULT_ATTACK if a fault attack is detected. + * + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_verifyMode) +static inline mcuxClRandom_Status_t mcuxClRandom_verifyMode(mcuxClRandom_Mode_t mode) +{ + // TODO CLNS-7923: Need to be discussed whether INVALID_PARAM or FAULT_ATTACK should be returned + if(mode == NULL) + { + return MCUXCLRANDOM_STATUS_INVALID_PARAM; + } + return MCUXCLRANDOM_STATUS_OK; +} + +/** + * @brief This function verifies a Random context + * + * @param pRngCtx[in] Random context to be verified + * + * @return Status of the operation: + * @retval #MCUXCLRANDOM_STATUS_OK if the Random context is valid + * @retval #MCUXCLRANDOM_STATUS_FAULT_ATTACK if the Random context is invalid or a fault attack is detected. + * + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_verifyContext) +static inline mcuxClRandom_Status_t mcuxClRandom_verifyContext(mcuxClRandom_Context_t pRngCtx UNUSED_PARAM) +{ + // TODO CLNS-7390: To be implemented + return MCUXCLRANDOM_STATUS_OK; +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_init( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Context_t pContext, + mcuxClRandom_Mode_t mode +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_init); + + /* Verify passed mode parameter */ + mcuxClRandom_Status_t retCode_verifyMode = mcuxClRandom_verifyMode(mode); + if(MCUXCLRANDOM_STATUS_OK != retCode_verifyMode) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_init, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Store context in session. */ + pSession->randomCfg.ctx = pContext; + + /* Store mode in session. */ + pSession->randomCfg.mode = mode; + + /* Call internal init function */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_initFunction, mode->pOperationMode->initFunction(pSession)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_init, retCode_initFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + mode->pOperationMode->protectionTokenInitFunction); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_reseed) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_reseed( + mcuxClSession_Handle_t pSession +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_reseed); + + /* Verify context integrity */ + mcuxClRandom_Context_t pRngCtx = pSession->randomCfg.ctx; + mcuxClRandom_Status_t retCode_verifyContext = mcuxClRandom_verifyContext(pRngCtx); + if(MCUXCLRANDOM_STATUS_OK != retCode_verifyContext) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_reseed, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + + /* Call internal reseed function */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_reseedFunction, sessionMode->pOperationMode->reseedFunction(pSession)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_reseed, retCode_reseedFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + sessionMode->pOperationMode->protectionTokenReseedFunction); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_generate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_generate( + mcuxClSession_Handle_t pSession, + uint8_t * pOut, + uint32_t outLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_generate); + + /* Verify context integrity */ + mcuxClRandom_Context_t pRngCtx = pSession->randomCfg.ctx; + mcuxClRandom_Status_t retCode_verifyContext = mcuxClRandom_verifyContext(pRngCtx); + if(MCUXCLRANDOM_STATUS_OK != retCode_verifyContext) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_generate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + + /* Call internal generate function */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_generateFunction, sessionMode->pOperationMode->generateFunction(pSession, pOut, outLength)); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_generate, retCode_generateFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + sessionMode->pOperationMode->protectionTokenGenerateFunction); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_uninit) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_uninit( + mcuxClSession_Handle_t pSession +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_uninit); + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + /* In patch mode the context is not used so the context integrity check and clearing needs to be skipped */ + if(0u == sessionMode->contextSize) + { + /* Clear pointers stored in the session. */ + pSession->randomCfg.ctx = NULL; + pSession->randomCfg.mode = NULL; + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_uninit, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Verify context integrity */ + mcuxClRandom_Context_t pRngCtx = pSession->randomCfg.ctx; + mcuxClRandom_Status_t retCode_verifyContext = mcuxClRandom_verifyContext(pRngCtx); + if(MCUXCLRANDOM_STATUS_OK != retCode_verifyContext) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_uninit, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Clear the context */ + MCUXCLRANDOM_SECURECLEAR(mcuxClRandom_uninit, MCUXCLRANDOM_STATUS_ERROR, (uint8_t *) pSession->randomCfg.ctx, sessionMode->contextSize); + + /* Clear pointers stored in the session. */ + pSession->randomCfg.ctx = NULL; + pSession->randomCfg.mode = NULL; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_uninit, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUXCLRANDOM_FP_CALLED_SECURECLEAR); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_selftest) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_selftest( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Mode_t mode +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_selftest); + + /* Verify passed mode parameter */ + mcuxClRandom_Status_t retCode_verifyMode = mcuxClRandom_verifyMode(mode); + if(MCUXCLRANDOM_STATUS_OK != retCode_verifyMode) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_selftest, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Call internal selftest function. */ + MCUX_CSSL_FP_FUNCTION_CALL(retCode_selftestFunction, mode->pOperationMode->selftestFunction(pSession, mode)); + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_selftest, retCode_selftestFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + mode->pOperationMode->protectionTokenSelftestFunction); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_checkSecurityStrength) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_checkSecurityStrength( + mcuxClSession_Handle_t pSession, + uint32_t securityStrength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_checkSecurityStrength); + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + + if (securityStrength > sessionMode->securityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_checkSecurityStrength, MCUXCLRANDOM_STATUS_LOW_SECURITY_STRENGTH); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_checkSecurityStrength, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } +} diff --git a/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_PRNG.c b/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_PRNG.c new file mode 100644 index 000000000..1bb213f99 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandom/src/mcuxClRandom_PRNG.c @@ -0,0 +1,71 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRandom_PRNG.c + * @brief Implementation of the non-cryptographic PRNG functions. */ + +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_ncInit) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncInit( + mcuxClSession_Handle_t pSession UNUSED_PARAM +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_ncInit); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_Init, mcuxClPrng_init()); + if(MCUXCLPRNG_STATUS_ERROR == ret_Prng_Init) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_ncInit, MCUXCLRANDOM_STATUS_ERROR, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_init)); + } + else if(MCUXCLPRNG_STATUS_OK != ret_Prng_Init) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_ncInit, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_ncInit, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_init)); + } +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandom_ncGenerate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandom_ncGenerate( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint8_t * pOut, + uint32_t outLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandom_ncGenerate); + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Prng_GetRandom, mcuxClPrng_generate(pOut, outLength)); + if(MCUXCLPRNG_STATUS_ERROR == ret_Prng_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_ncGenerate, MCUXCLRANDOM_STATUS_ERROR, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_generate)); + } + else if(MCUXCLPRNG_STATUS_OK != ret_Prng_GetRandom) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandom_ncGenerate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandom_ncGenerate, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPrng_generate)); + } +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Internal_SizeDefinitions.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Internal_SizeDefinitions.h new file mode 100644 index 000000000..d87cb5a21 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Internal_SizeDefinitions.h @@ -0,0 +1,361 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: mcuxClRandomModes_Internal_SizeDefinitions.h + * @brief: This file contains size definitions to share them with other components + * + */ + +#ifndef MCUXCLRANDOMMODES_INTERNAL_SIZEDEFINITIONS_H_ +#define MCUXCLRANDOMMODES_INTERNAL_SIZEDEFINITIONS_H_ + +#define MCUXCLRANDOMMODES_MAX( x, y ) ( ( x ) > ( y ) ? ( x ) : ( y ) ) + +#include // Exported features flags header +#if defined(MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION) +#include +#endif +#include +#include +#ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +#include +#include +#include +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + + +/**************************************************************************************************/ +/* */ +/* Definition of max workarea sizes allocated by internal DRBG algorithm related helper functions */ +/* */ +/**************************************************************************************************/ +#ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_bcc uses + */ +#define MCUXCLRANDOMMODES_CTRDRBG_BCC_CPUWA_SIZE MCUXCLAES_BLOCK_SIZE + +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_df uses at most, i.e. for the AES-256 CTR_DRBG case + * + * cpuWa | IV | L | N | Seed | 0x80 | Padding over (L,N,Seed,0x80) | K | X | additionBlock | + * size in byte | 16 | 4 | 4 | 64 | 1 | 0-7 => max=7 | 256 \ 8 = 32 | 16 | 16 | + * + */ +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_IV MCUXCLAES_BLOCK_SIZE +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_L (4) +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_N (4) +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_SEED MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_INIT_CTR_DRBG_AES256 +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_0X80 (1) +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_MAXPADDING (7) +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_K_MAXSIZE MCUXCLAES_AES256_KEY_SIZE +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_X MCUXCLAES_BLOCK_SIZE + +#define MCUXCLRANDOMMODES_CTRDRBG_DERIVATIONFUNCTION_CPUWA_MAXSIZE (\ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_IV + \ + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE( \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_L + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_N + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_SEED + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_0X80 + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_MAXPADDING) * sizeof(uint32_t) + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_K_MAXSIZE + \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_DF_X + \ + MCUXCLRANDOMMODES_CTRDRBG_BCC_CPUWA_SIZE \ + ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION */ + +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_UpdateState uses at most, i.e. for the AES-256 CTR_DRBG case + * + * cpuWa | Seed | + * size in byte | entropy_input size for AES-256 for the init case | + * + */ +#define MCUXCLRANDOMMODES_CTRDRBG_UPDATESTATE_CPUWA_MAXSIZE (MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256)) +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + + +#if defined(MCUXCL_FEATURE_RANDOMMODES_NORMALMODE) || defined(MCUXCL_FEATURE_RANDOMMODES_TESTMODE) +/*********************************************************************************************/ +/* */ +/* Definition of max workarea sizes allocated by function pointer functions */ +/* - instantiateAlgorithm */ +/* - reseedAlgorithm */ +/* - generateAlgorithm */ +/* - selftestAlgorithm */ +/* */ +/*********************************************************************************************/ +#ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_INIT_SEEDMATERIAL_SIZE (MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_INIT_CTR_DRBG_AES256, MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256)) * sizeof(uint32_t)) +#if defined(MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION) +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_instantiateAlgorithm uses at most + * + * cpuWa | Seed | cpuWa used by called functions | + * size in byte | entropy_input size for the init case | Max(cpuWaDF, cpuWaUpdateState) | + * + */ +#define MCUXCLRANDOMMODES_CTRDRBG_INSTANTIATEALGO_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_INIT_SEEDMATERIAL_SIZE + \ + MCUXCLRANDOMMODES_MAX( \ + MCUXCLRANDOMMODES_CTRDRBG_DERIVATIONFUNCTION_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_CTRDRBG_UPDATESTATE_CPUWA_MAXSIZE \ + ) \ + ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION */ + +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_RESEED_SEEDMATERIAL_SIZE (MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_RESEED_CTR_DRBG_AES256, MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256)) * sizeof(uint32_t)) +#if defined(MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION) +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_reseedAlgorithm uses at most + * + * cpuWa | Seed | cpuWa used by called functions | + * size in byte | entropy_input size for the reseed case | Max(cpuWaDF, cpuWaUpdateState) | + * + */ +#define MCUXCLRANDOMMODES_CTRDRBG_RESEEDALGO_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_RESEED_SEEDMATERIAL_SIZE + \ + MCUXCLRANDOMMODES_MAX( \ + MCUXCLRANDOMMODES_CTRDRBG_DERIVATIONFUNCTION_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_CTRDRBG_UPDATESTATE_CPUWA_MAXSIZE \ + ) \ + ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION */ + +#define MCUXCLRANDOMMODES_CTRDRBG_AES256_GENERATE_ADDITIONALINPUT_SIZE (MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256) * sizeof(uint32_t)) +/* + * Description of how much cpuWa mcuxClRandomModes_CtrDrbg_generateAlgorithm uses at most + * + * cpuWa | additional input | cpuWa used by called functions | + * size in byte | seedlen | cpuWaUpdateState | + * + */ +#define MCUXCLRANDOMMODES_CTRDRBG_GENERATEALGO_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_CTRDRBG_AES256_GENERATE_ADDITIONALINPUT_SIZE + \ + MCUXCLRANDOMMODES_CTRDRBG_UPDATESTATE_CPUWA_MAXSIZE \ + ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ +#endif /* MCUXCL_FEATURE_RANDOMMODES_NORMALMODE || MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ + + +/*********************************************************************************************/ +/* */ +/* Definition of max workarea sizes allocated by function pointer functions in test mode */ +/* - initFunction */ +/* - reseedFunction */ +/* - generateFunction */ +/* */ +/*********************************************************************************************/ + +#ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE +/* + * Description of how much cpuWa mcuxClRandomModes_TestMode_initFunction uses at most + * + * cpuWa | Call to instantiateAlgo | + * size in byte | cpuWaInstantiateAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_TESTMODE_INIT_CPUWA_MAXSIZE ( MCUXCLRANDOMMODES_CTRDRBG_INSTANTIATEALGO_CPUWA_MAXSIZE ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + +/* + * Description of how much cpuWa mcuxClRandomModes_TestMode_reseedFunction uses at most + * + * cpuWa | Call to reseedAlgo | + * size in byte | cpuWaReseedAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_TESTMODE_RESEED_CPUWA_MAXSIZE ( MCUXCLRANDOMMODES_CTRDRBG_RESEEDALGO_CPUWA_MAXSIZE ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + +/* + * Description of how much cpuWa mcuxClRandomModes_generateFunction_PrDisabled/PTG3 uses at most + * + * cpuWa | Call(s) to reseedFunc | Call(s) to generateAlgo | + * size in byte | cpuWaReseedFunc | cpuWaGenerateAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_TESTMODE_GENERATE_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_MAX( \ + MCUXCLRANDOMMODES_TESTMODE_RESEED_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_CTRDRBG_GENERATEALGO_CPUWA_MAXSIZE) \ + ) +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + +/* + * Description of how much cpuWa mcuxClRandomModes_TestMode_selftestFunction uses at most + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_TESTMODE_SELFTEST_CPUWA_MAXSIZE 0u +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ +#else /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ +#define MCUXCLRANDOMMODES_TESTMODE_INIT_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_TESTMODE_RESEED_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_TESTMODE_GENERATE_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_TESTMODE_SELFTEST_CPUWA_MAXSIZE 0u +#endif /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ + +/*********************************************************************************************/ +/* */ +/* Definition of max workarea sizes allocated by function pointer functions in normal mode */ +/* - initFunction */ +/* - reseedFunction */ +/* - generateFunction */ +/* - selftestFunction */ +/* */ +/*********************************************************************************************/ + +#ifdef MCUXCL_FEATURE_RANDOMMODES_NORMALMODE +/* + * Description of how much cpuWa mcuxClRandomModes_NormalMode_initFunction uses at most + * + * cpuWa | Seed | Call to instantiateAlgo | + * size in byte | entropy_input size for the init case | cpuWaInstantiateAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_NORMALMODE_INIT_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_INIT_CTR_DRBG_AES256) * sizeof(uint32_t) + \ + MCUXCLRANDOMMODES_CTRDRBG_INSTANTIATEALGO_CPUWA_MAXSIZE \ + ) +#endif + +/* + * Description of how much cpuWa mcuxClRandomModes_NormalMode_reseedFunction uses at most + * + * cpuWa | Seed | Call to reseedAlgo | + * size in byte | entropy_input size for the reseed case | cpuWaReseedAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_NORMALMODE_RESEED_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_RESEED_CTR_DRBG_AES256) * sizeof(uint32_t) + \ + MCUXCLRANDOMMODES_CTRDRBG_RESEEDALGO_CPUWA_MAXSIZE \ + ) +#endif + +/* + * Description of how much cpuWa mcuxClRandomModes_generateFunction_PrDisabled/PTG3 uses at most + * + * cpuWa | Call(s) to reseedFunc | Call(s) to generateAlgo | + * size in byte | cpuWaReseedFunc | cpuWaGenerateAlgo | + * + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_NORMALMODE_GENERATE_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_MAX( \ + MCUXCLRANDOMMODES_NORMALMODE_RESEED_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_CTRDRBG_GENERATEALGO_CPUWA_MAXSIZE) \ + ) +#endif + +/* + * Description of how much cpuWa mcuxClRandomModes_NormalMode_selftestFunction uses at most + * + * cpuWa | Call(s) to initFunc | Call(s) to reseedFunc | Call(s) to generateFunc | + * size in byte | cpuWaInitFunc | cpuWaReseedFunc | cpuWaGenerateFunc | + */ +#if defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) +#define MCUXCLRANDOMMODES_NORMALMODE_SELFTEST_CPUWA_MAXSIZE ( \ + sizeof(mcuxClRandom_ModeDescriptor_t) + \ + sizeof(mcuxClRandomModes_Context_CtrDrbg_Aes256_t) + \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_INIT_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_RESEED_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_TESTMODE_GENERATE_CPUWA_MAXSIZE \ + ) \ + ) \ + ) +#endif +#else /* MCUXCL_FEATURE_RANDOMMODES_NORMALMODE */ +#define MCUXCLRANDOMMODES_NORMALMODE_INIT_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_NORMALMODE_RESEED_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_NORMALMODE_GENERATE_CPUWA_MAXSIZE 0u +#define MCUXCLRANDOMMODES_NORMALMODE_SELFTEST_CPUWA_MAXSIZE 0u +#endif /* MCUXCL_FEATURE_RANDOMMODES_NORMALMODE */ + + +/*********************************************************************************************/ +/* */ +/* Definition of workarea sizes for API functions */ +/* - init */ +/* - reseed */ +/* - generate */ +/* - selftest */ +/* */ +/*********************************************************************************************/ + +/* + * Maximum cpuWa size for init + */ +#define MCUXCLRANDOMMODES_INIT_WACPU_SIZE_MAX ( \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_NORMALMODE_INIT_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_INIT_CPUWA_MAXSIZE, \ + 4u \ + ) \ + ) \ + ) + +/* + * Maximum cpuWa size for reseed + */ +#define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE_MAX ( \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_NORMALMODE_RESEED_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_RESEED_CPUWA_MAXSIZE, \ + 4u \ + ) \ + ) \ + ) + +/* + * Maximum cpuWa size for generate + */ +#define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE_MAX ( \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_NORMALMODE_GENERATE_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_GENERATE_CPUWA_MAXSIZE, \ + 4u \ + ) \ + ) \ + ) + +/* + * Maximum cpuWa size for selftest + */ +#define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE_MAX ( \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_NORMALMODE_SELFTEST_CPUWA_MAXSIZE, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_TESTMODE_SELFTEST_CPUWA_MAXSIZE, \ + 4u \ + ) \ + ) \ + ) + +/* + * Maximum cpuWa size over all API functions + */ +#define MCUXCLRANDOMMODES_CPUWA_MAXSIZE ( \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_INIT_WACPU_SIZE_MAX, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_RESEED_WACPU_SIZE_MAX, \ + MCUXCLRANDOMMODES_MAX(MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE_MAX, \ + MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE_MAX \ + )\ + )\ + ) \ + ) + +#endif /* MCUXCLRANDOMMODES_INTERNAL_SIZEDEFINITIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg.h new file mode 100644 index 000000000..af7f30e16 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg.h @@ -0,0 +1,120 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_H_ +#define MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_H_ + +#include // Exported features flags header + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Mode descriptor related defines for CTR_DRBGs */ + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +#define MCUXCLRANDOMMODES_SECURITYSTRENGTH_CTR_DRBG_AES256 (256u) +#define MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256 (48u) +#define MCUXCLRANDOMMODES_RESEED_INTERVAL_CTR_DRBG_AES256 (0x0001000000000000u) +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +#if defined(MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION) + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +#define MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_INIT_CTR_DRBG_AES256 (71u) +#define MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_RESEED_CTR_DRBG_AES256 (55u) +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +#endif // MCUXCL_FEATURE_RANDOMMODES_NO_DERIVATION_FUNCTION + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +/* Internal structure of a CTR_DRBG AES256 random context */ +#define MCUXCLRANDOMMODES_CONTEXT_CTR_DRBG_AES256_SIZE_KEY_IN_WORDS (8u) +typedef struct +{ + MCUXCLRANDOMMODES_CONTEXT_DRBG_ENTRIES + uint32_t key[MCUXCLRANDOMMODES_CONTEXT_CTR_DRBG_AES256_SIZE_KEY_IN_WORDS]; + uint32_t counterV[MCUXCLAES_BLOCK_SIZE_IN_WORDS]; +} mcuxClRandomModes_Context_CtrDrbg_Aes256_t; +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +#define MCUXCLRANDOMMODES_CONTEXT_CTR_DRBG_MAX_SIZE_KEY_IN_WORDS (8u) +typedef struct +{ + MCUXCLRANDOMMODES_CONTEXT_DRBG_ENTRIES + uint32_t state[MCUXCLRANDOMMODES_CONTEXT_CTR_DRBG_MAX_SIZE_KEY_IN_WORDS + MCUXCLAES_BLOCK_SIZE_IN_WORDS]; +} mcuxClRandomModes_Context_CtrDrbg_Generic_t; + +/* Internal function prototypes */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, mcuxClRandomModes_instantiateAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_instantiateAlgorithm( + mcuxClSession_Handle_t pSession, + uint8_t *pEntropyInput); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, mcuxClRandomModes_reseedAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_reseedAlgorithm( + mcuxClSession_Handle_t pSession, + uint8_t *pEntropyInput); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_generateAlgorithm, mcuxClRandomModes_generateAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_generateAlgorithm( + mcuxClSession_Handle_t pSession, + uint8_t *pOut, + uint32_t outLength); + +/* Refer to the NIST SP 800-90A 10.3.2 Derivation function using a block cipher algorithm */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_df) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_df( + mcuxClSession_Handle_t pSession, + uint8_t *pInputString, + uint32_t inputStringLen, + uint32_t outputLen); + +/* Refer to the NIST SP 800-90A 10.3.3 BCC and Block_Encrypt */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_bcc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_bcc( + mcuxClSession_Handle_t pSession, + uint32_t const *pKey, + uint32_t * const pData, + uint32_t dataLen, + uint32_t *pOut); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_UpdateState) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_UpdateState( + mcuxClSession_Handle_t pSession, + uint32_t *pProvidedData +); + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_generateOutput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_generateOutput( + mcuxClSession_Handle_t pSession, + uint8_t *pOut, + uint32_t outLength); + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +extern const mcuxClRandomModes_DrbgVariantDescriptor_t mcuxClRandomModes_DrbgVariantDescriptor_CtrDrbg_AES256; +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg_BlockCipher.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg_BlockCipher.h new file mode 100644 index 000000000..22223a7c2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_CtrDrbg_BlockCipher.h @@ -0,0 +1,39 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_BLOCKCIPHER_H_ +#define MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_BLOCKCIPHER_H_ + +#include // Exported features flags header + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_DRBG_AES_Internal_blockcipher) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_DRBG_AES_Internal_blockcipher( + uint32_t const *pV, + uint32_t const *pKey, + uint8_t *pOut, + uint32_t keyLength +); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_CTRDRBG_BLOCKCIPHER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_Drbg.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_Drbg.h new file mode 100644 index 000000000..90beb87a9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_Drbg.h @@ -0,0 +1,130 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_DRBG_H_ +#define MCUXCLRANDOMMODES_PRIVATE_DRBG_H_ + +#include // Exported features flags header + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUXCLRANDOMMODES_SELFTEST_RANDOMDATALENGTH (64u) + +/* + * Takes a byte size and returns a number of words + */ +#define MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(bytesize) \ + (((bytesize) + sizeof(uint32_t) - 1U ) / (sizeof(uint32_t))) + +/* + * Takes a byte size and returns the next largest multiple of MCUXCLAES_BLOCK_SIZE + */ +#define MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(bytesize) \ + ((((bytesize) + MCUXCLAES_BLOCK_SIZE - 1U) / MCUXCLAES_BLOCK_SIZE) * MCUXCLAES_BLOCK_SIZE) + +/** + * @brief Defines to specify which mode a DRBG is operated in + */ +#define MCUXCLRANDOMMODES_NORMALMODE (0xa5a5a5a5u) +#define MCUXCLRANDOMMODES_TESTMODE (0x5a5a5a5au) +#define MCUXCLRANDOMMODES_ELSMODE (0xd3d3d3d3u) +#define MCUXCLRANDOMMODES_PATCHMODE (0x3d3d3d3du) + +/* Shared generic internal structure of a random context used by DRBGs: + * - reseedCounter This value is used to count the number of generateAlgorithm function calls since the last reseedAlgorithm call. + * - reseedSeedOffset For PTG.3 in test mode, the reseedSeedOffset counts the number of entropy input bytes already drawn from the entropy input buffer + * for reseeding during an mcuxClRandom_generate call. Otherwise it's set to zero. + * This value is not taken into account during reseeding in normal mode. It is only used to determine the right offset + * in the entropy buffer during mcuxClRandom_generate calls for PTG.3 in test mode. */ +#define MCUXCLRANDOMMODES_CONTEXT_DRBG_ENTRIES \ + uint64_t reseedCounter; \ + uint32_t reseedSeedOffset; + +typedef struct +{ + MCUXCLRANDOMMODES_CONTEXT_DRBG_ENTRIES +} mcuxClRandomModes_Context_Generic_t; + +/* Signatures for internal functions */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandomModes_instantiateAlgorithm_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandomModes_instantiateAlgorithm_t)( + mcuxClSession_Handle_t pSession, + uint8_t *pEntropyInput +)); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandomModes_reseedAlgorithm_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandomModes_reseedAlgorithm_t)( + mcuxClSession_Handle_t pSession, + uint8_t *pEntropyInput +)); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandomModes_generateAlgorithm_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandomModes_generateAlgorithm_t)( + mcuxClSession_Handle_t pSession, + uint8_t *pOut, + uint32_t outLength +)); + +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRandomModes_selftestAlgorithm_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandomModes_selftestAlgorithm_t)( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Context_t testCtx, + mcuxClRandom_ModeDescriptor_t *mode +)); + +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) (* mcuxClRandomModes_generatePrHandler_t)( + mcuxClSession_Handle_t pSession +); + +typedef struct +{ + /* Function pointers for DRBG algorithms */ + mcuxClRandomModes_instantiateAlgorithm_t instantiateAlgorithm; ///< DRBG instantiation algorithm depending on the chosen DRBG variant + mcuxClRandomModes_reseedAlgorithm_t reseedAlgorithm; ///< DRBG reseeding algorithm depending on the chosen DRBG variant + mcuxClRandomModes_generateAlgorithm_t generateAlgorithm; ///< DRBG random number generation algorithm depending on the chosen DRBG variant + mcuxClRandomModes_selftestAlgorithm_t selftestAlgorithm; ///< DRBG self-test handler depending on the chosen DRBG variant + + /* Protection tokens of DRBG algorithm function pointers */ + uint32_t protectionTokenInstantiateAlgorithm; ///< Protection token of DRBG instantiate algorithm + uint32_t protectionTokenReseedAlgorithm; ///< Protection token of DRBG reseed algorithm + uint32_t protectionTokenGenerateAlgorithm; ///< Protection token of DRBG generate algorithm + uint32_t protectionTokenSelftestAlgorithm; ///< Protection token of DRBG generate algorithm +} mcuxClRandomModes_DrbgAlgorithmsDescriptor_t; + +typedef struct +{ + uint64_t reseedInterval; ///< reseed interval of chosen DRBG variant + uint16_t seedLen; ///< seedLen parameter defined in NIST SP 800-90A + uint16_t initSeedSize; ///< Size of entropy input used for instantiating the DRBG + uint16_t reseedSeedSize; ///< Size of entropy input used for reseeding the DRBG +} mcuxClRandomModes_DrbgVariantDescriptor_t; + +typedef struct +{ + const mcuxClRandomModes_DrbgAlgorithmsDescriptor_t *pDrbgAlgorithms; + const mcuxClRandomModes_DrbgVariantDescriptor_t *pDrbgVariant; + const uint32_t * const *pDrbgTestVectors; + uint32_t continuousReseedInterval; +} mcuxClRandomModes_DrbgModeDescriptor_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_DRBG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_NormalMode.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_NormalMode.h new file mode 100644 index 000000000..4be71ec96 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_NormalMode.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_NORMALMODE_H_ +#define MCUXCLRANDOMMODES_PRIVATE_NORMALMODE_H_ + +#include // Exported features flags header + +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Internal function prototypes */ + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_NormalMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_initFunction(mcuxClSession_Handle_t pSession); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_NormalMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_reseedFunction(mcuxClSession_Handle_t pSession); + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, mcuxClRandom_generateFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_generateFunction_PrDisabled(mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength); + +extern const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_NormalMode_PrDisabled; +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_NormalMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_selftestFunction(mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_selftest_VerifyArrays) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_selftest_VerifyArrays(uint32_t wordLength, const uint32_t * const expected, uint32_t *actual); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_NORMALMODE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PatchMode.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PatchMode.h new file mode 100644 index 000000000..994361848 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PatchMode.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_PATCHMODE_H_ +#define MCUXCLRANDOMMODES_PRIVATE_PATCHMODE_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Internal function prototypes */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_PatchMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_initFunction(mcuxClSession_Handle_t session); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_PatchMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_reseedFunction(mcuxClSession_Handle_t session); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_PatchMode_generateFunction, mcuxClRandom_generateFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_generateFunction(mcuxClSession_Handle_t session, uint8_t *pOut, uint32_t outLength); +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_PatchMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_selftestFunction(mcuxClSession_Handle_t session, mcuxClRandom_Mode_t mode); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_PATCHMODE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PrDisabled.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PrDisabled.h new file mode 100644 index 000000000..e4d23ee5a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_PrDisabled.h @@ -0,0 +1,44 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_PRIVATE_PRDISABLED_H_ +#define MCUXCLRANDOMMODES_PRIVATE_PRDISABLED_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUXCLRANDOMMODES_TESTVECTORS_INDEX_ENTROPY_PRDISABLED ( 0u) +#define MCUXCLRANDOMMODES_TESTVECTORS_INDEX_ENTROPY_RESEED_PRDISABLED ( 1u) +#define MCUXCLRANDOMMODES_TESTVECTORS_INDEX_RANDOMDATA_PRDISABLED ( 2u) +#define MCUXCLRANDOMMODES_NO_OF_TESTVECTORS_PRDISABLED (MCUXCLRANDOMMODES_TESTVECTORS_INDEX_RANDOMDATA_PRDISABLED + 1u) + +#ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +extern const mcuxClRandomModes_DrbgAlgorithmsDescriptor_t mcuxClRandomModes_DrbgAlgorithmsDescriptor_CtrDrbg_PrDisabled; +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + +/* Internal function prototypes */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_PrDisabled_selftestAlgorithm, mcuxClRandomModes_selftestAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PrDisabled_selftestAlgorithm(mcuxClSession_Handle_t pSession, mcuxClRandom_Context_t pTestCtx, mcuxClRandom_ModeDescriptor_t *pTestMode); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_PRIVATE_PRDISABLED_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_TestMode.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_TestMode.h new file mode 100644 index 000000000..0c2649730 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/internal/mcuxClRandomModes_Private_TestMode.h @@ -0,0 +1,49 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOM_PRIVATE_TESTMODE_H_ +#define MCUXCLRANDOM_PRIVATE_TESTMODE_H_ + +#include // Exported features flags header + +#include +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Internal function prototypes */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_TestMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_initFunction(mcuxClSession_Handle_t pSession); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_TestMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_reseedFunction(mcuxClSession_Handle_t pSession); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_TestMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_selftestFunction(mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode); + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +extern const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_TestMode_PrDisabled; +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_PRIVATE_TESTMODE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes.h new file mode 100644 index 000000000..90c6a258a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes.h @@ -0,0 +1,33 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandomModes.h + * @brief Top level header of mcuxClRandomModes component + * + * @defgroup mcuxClRandom mcuxClRandom + * @brief component of random number generation + */ + +#ifndef MCUXCLRANDOMMODES_H_ +#define MCUXCLRANDOMMODES_H_ + +#include // Exported features flags header +#ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE +#include +#endif /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ +#include +#include +#include + +#endif /* MCUXCLRANDOMMODES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Constants.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Constants.h new file mode 100644 index 000000000..af60d1b22 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Constants.h @@ -0,0 +1,115 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandomModes_Constants.h + * @brief Mode definitions of mcuxClRandomModes component + */ + +#ifndef MCUXCLRANDOMMODES_CONSTANTS_H_ +#define MCUXCLRANDOMMODES_CONSTANTS_H_ + +#include // Exported features flags header + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Values for reseeds */ +/**********************************************************/ + + +/**********************************************************/ +/* Types of mcuxClRandom */ +/**********************************************************/ +/** + * @defgroup mcuxClRandomModes_Constants mcuxClRandom_Constants + * @brief Defines all modes of @ref mcuxClRandomModes + * @ingroup mcuxClRandom + * @{ + */ + + +/** + * @brief Mode for a DRBG implemented by the ELS + * + * This mode provides a function to get random values from a DRBG implemented by the ELS. The provided security strength + * is HW dependent and can be determined using the function mcuxClRandom_checkSecurityStrength + */ +extern const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg; +static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_ELS_Drbg = + &mcuxClRandomModes_mdELS_Drbg; + + +#if defined(MCUXCL_FEATURE_RANDOMMODES_NORMALMODE) && defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +/** + * @brief Mode for a NIST SP800-90A CTR_DRBG based on AES-256 configured to not provide prediction resistance and realize a DRG.3 at 256 bit security level. + * + * This mode realizes a NIST SP800-90A CTR_DRBG based on AES-256 which does not provide prediction resistance. It is designed in a way + * to comply to FIPS 140-3 on the one hand and realize a DRG.3 at 256 bit security level on the other. + * For an up to date list of evaluations and certifications one should refer to the product (HW) documentation. + */ +extern const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdCtrDrbg_AES256_DRG3; +static const mcuxClRandom_Mode_t mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 = + &mcuxClRandomModes_mdCtrDrbg_AES256_DRG3; + +/** + * @brief Mode for a NIST SP800-90A CTR_DRBG based on AES-256 configured to not provide prediction resistance and realize a DRG.4 at 256 bit security level. + * + * This mode realizes a NIST SP800-90A CTR_DRBG based on AES-256 which does not provide prediction resistance. It is designed in a way + * to comply to FIPS 140-3 on the one hand and realize a DRG.4 at 256 bit security level on the other. + * For an up to date list of evaluations and certifications one should refer to the product (HW) documentation. + * +* NOTE: This mode is an alias of mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 and does not perform any internal reseeding. +* To realize the desired DRG.4 functionality by on-demand reseeding, the mcuxClRandom_reseed function is provided. + */ +#define mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG4 mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 + +/** + * @brief Mode for a NIST SP800-90A CTR_DRBG based on AES-256 configured to not provide prediction resistance. + * + * This mode realizes a NIST SP800-90A CTR_DRBG based on AES-256 which does not provide prediction resistance and + * is designed in a way to comply to FIPS 140-3. + * For an up to date list of evaluations and certifications one should refer to the product (HW) documentation. + * + * This is an alias of mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3, as both modes offer the same functionality. + */ +#define mcuxClRandomModes_Mode_CtrDrbg_AES256 mcuxClRandomModes_Mode_CtrDrbg_AES256_DRG3 + +#endif /* MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 */ + +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + + + +#endif /* defined(MCUXCL_FEATURE_RANDOMMODES_NORMALMODE) && defined(MCUXCL_FEATURE_RANDOMMODES_CTRDRBG) */ + +/** + * @} + */ /* mcuxClRandom_Types */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_PatchMode.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_PatchMode.h new file mode 100644 index 000000000..653e42cdc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_PatchMode.h @@ -0,0 +1,79 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_ +#define MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup mcuxClAPI MCUX CL -- API + * + * \defgroup mcuxClRandomPatchMode Random PATCH_MODE API + * \brief Random operations in PATCH_MODE. + * \ingroup mcuxClAPI + */ + +/** + * \defgroup clRandomPatchMode Random interfaces + * \brief Interfaces to perform Random handling operations. + * \ingroup mcuxClRandom + */ + +/* Interface definition for a custom RNG function */ +typedef mcuxClRandom_Status_t (* mcuxClRandomModes_CustomGenerateAlgorithm_t)( + mcuxClSession_Handle_t session, + mcuxClRandom_Context_t pCustomCtx, + uint8_t *pOut, + uint32_t outLength +); + +/** + * \brief This function creates a PATCH_MODE descriptor + * \api + * \ingroup clRandom + * + * This function creates a PATCH_MODE descriptor. + * The function expects as input a custom function to be used inside the CL functions for random number generation as well as + * a pointer to a context buffer which can be used by the custom generate function. + * The custom generate function may also use all CPU workarea allocated for the mcuxClRandom_generate function. + * The function shall be called prior to an mcuxClRandom_init call. + * + * \param patchMode[out] Pointer to PATCH_MODE descriptor to be initialized + * \param customGenerateAlgorithm[in] Pointer to the custom generate function + * \param pEntropyInput[in] Pointer to a custom context which shall be used by the passed custom generate function + * \param securityStrength[in] Security level for which the patch DRBG shall be used + * + * \return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_createPatchMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createPatchMode( + mcuxClRandom_ModeDescriptor_t * patchMode, + mcuxClRandomModes_CustomGenerateAlgorithm_t customGenerateAlgorithm, + mcuxClRandom_Context_t pCustomCtx, + uint32_t securityStrength +); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOMMODES_FUNCTIONS_PATCHMODE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_TestMode.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_TestMode.h new file mode 100644 index 000000000..cc58ae44c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_Functions_TestMode.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_ +#define MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_ + +#include // Exported features flags header + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup mcuxClAPI MCUX CL -- API + * + * \defgroup mcuxClRandomTestMode Random TEST_MODE API + * \brief Random operations in TEST_MODE. + * \ingroup mcuxClAPI + */ + +/** + * \defgroup clRandomTestMode Random interfaces + * \brief Interfaces to perform Random handling operations. + * \ingroup mcuxClRandom + */ + +/** + * \brief This function creates a TEST_MODE descriptor from an existing NORMAL_MODE one + * \api + * \ingroup clRandom + * + * This function creates a TEST_MODE descriptor from an existing NORMAL_MODE one. + * The function expects as input a pointer to a buffer to which the user of the CL shall write entropy input to be used for (re)seeding the DRBG. + * The function shall be called prior to an mcuxClRandom_init call. + * + * \param testMode[out] Pointer to TEST_MODE descriptor to be initialized + * \param normalMode[in] Pointer to NORMAL_MODE descriptor to be used as basis for the initialization + * \param pEntropyInput[in] Pointer to memory buffer containing entropy input for DRBG (re)seeding + * + * \return status + */ +// TODO: Create defines for entropy input sizes using object size filler +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_createTestFromNormalMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createTestFromNormalMode( + mcuxClRandom_ModeDescriptor_t *pTestMode, + mcuxClRandom_Mode_t normalMode, + const uint32_t * const pEntropyInput +); + +/** + * \brief This function updates the entropy input pointer in a TEST_MODE descriptor + * + * \param testMode[in] Pointer to TEST_MODE descriptor + * \param pEntropyInput[in] Pointer to memory buffer containing entropy input for DRBG (re)seeding + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the TEST_MODE descriptor generation was successful + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_updateEntropyInput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_updateEntropyInput( + mcuxClRandom_ModeDescriptor_t *pTestMode, + const uint32_t * const pEntropyInput +); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRANDOM_FUNCTIONS_TESTMODE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_MemoryConsumption.h new file mode 100644 index 000000000..b565dbc5e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/inc/mcuxClRandomModes_MemoryConsumption.h @@ -0,0 +1,95 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRandomModes_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClRandom component + */ + +#ifndef MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_ +#define MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_ + +/** + * @defgroup mcuxClRandomModes_MemoryConsumption mcuxClRandomModes_MemoryConsumption + * @brief Defines the memory consumption for the @ref mcuxClRandom component + * @ingroup mcuxClRandom + * @{ + */ + +#define MCUXCLRANDOMMODES_PATCHMODE_DESCRIPTOR_SIZE (20u) + +#ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE +#define MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE (20u) +#endif + +#ifdef MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG + +#define MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE (4u) + +#define MCUXCLRANDOMMODES_INIT_WACPU_SIZE (4u) +#define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE (4u) +#define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE (4u) +#define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE (4u) +#define MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE (0u) + +#else + +#define MCUXCLRANDOMMODES_MAX_CPU_WA_BUFFER_SIZE (324u) + +#define MCUXCLRANDOMMODES_INIT_WACPU_SIZE (312u) +#define MCUXCLRANDOMMODES_RESEED_WACPU_SIZE (280u) +#define MCUXCLRANDOMMODES_GENERATE_WACPU_SIZE (280u) +#define MCUXCLRANDOMMODES_SELFTEST_WACPU_SIZE (324u) +#define MCUXCLRANDOMMODES_UNINIT_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CHECKSECURITYSTRENGTH_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_NCINIT_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_NCGENERATE_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CREATEPATCHMODE_WACPU_SIZE (0u) +#define MCUXCLRANDOMMODES_CREATETESTMODEFROMNORMALMODE_WACPU_SIZE (0u) + +#endif + +#ifdef MCUXCL_FEATURE_RANDOMMODES_CTRDRBG + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +#define MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE (64u) +#define MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE_IN_WORDS ((MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE + sizeof(uint32_t) - 1u) / sizeof(uint32_t)) +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +#ifdef MCUXCL_FEATURE_PLATFORM_RW61X +#define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE (71u) +#define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE (55u) +#else +#define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_INIT_ENTROPY_SIZE (72u) +#define MCUXCLRANDOMMODES_TESTMODE_CTR_DRBG_AES256_RESEED_ENTROPY_SIZE (56u) +#endif +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +#endif /* MCUXCL_FEATURE_RANDOMMODES_CTRDRBG */ + + +/** + * @} + */ /* mcuxClRandomModes_MemoryConsumption */ + +#endif /* MCUXCLRANDOMMODES_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg.c new file mode 100644 index 000000000..5c00ad066 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg.c @@ -0,0 +1,914 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * \brief This function increments the counter V of the CTR_DRBG. + * + * This function increments the counter V considered as a big endian integer. + * + * \param pV Pointer to the counter V + * + * \return + * - The function returns the least significant word, i.e. highest word, of the counter V for integrity protection + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_CtrDrbg_incV) +static MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) mcuxClRandomModes_CtrDrbg_incV(uint32_t *pV) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_incV); + + /* Back up the least significant word of V for later return */ + const uint32_t beforeIncrement = pV[MCUXCLAES_BLOCK_SIZE_IN_WORDS - 1u]; + uint8_t *pVByte = (uint8_t *)pV; + + /* To increment the counter V considered as a big endian integer, increment the highest byte and propagate + * a possible carry bit from right to left */ + for(int32_t i = (int32_t)MCUXCLAES_BLOCK_SIZE - 1; i >= 0; i--) + { + pVByte[i] += 1u; + + /* If incrementing the current byte of V resulted in a zero byte, we continue propagating the carry. + * Otherwise, we leave the for loop early. */ + if(0u != pVByte[i]) + { + break; + } + } + + /* Exit the function and return the highest word of V for integrity checking in the calling function */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_incV, beforeIncrement); +} + +#if defined(MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION) +/** + * \brief This function implements the BCC function as specified in NIST SP800-90A. + * + * \param pSession Handle for the current CL session + * \param pKey[in] Pointer to the block encryption key K + * \param pData[in] Pointer to input data + * \param dataLen[in] Byte length of input data + * \param pOut[out] Pointer to output buffer + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the CTR_DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if there was an RNG error or if a memory allocation error occured + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_bcc) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_bcc( + mcuxClSession_Handle_t pSession, + uint32_t const *pKey, + uint32_t * const pData, + uint32_t dataLen, + uint32_t *pOut) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_bcc); + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + uint32_t keyLen = (uint32_t)(pMode->securityStrength) / 8u; + + /* Initialize buffer in CPU workarea for the input block for the block cipher operations */ + uint32_t *pInputBlock = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS); + if(NULL == pInputBlock) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_bcc, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Initialize the chaining value in the output buffer with zeros */ + uint32_t *pChainingValue = pOut; + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *)pChainingValue, 0u, MCUXCLAES_BLOCK_SIZE); + + /* Get number of input blocks to be processed */ + uint32_t numBlocks = dataLen / MCUXCLAES_BLOCK_SIZE; + uint32_t i, j; + uint32_t blkSizeInWords = MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t); + + for (i = 0; i < numBlocks; i++) + { + /* XOR chaining value to current input data block */ + for (j = 0; j < blkSizeInWords; j++) + { + /* TODO CLNS-7837 Replace with SecureXOR */ + pInputBlock[j] = pData[j + (i * blkSizeInWords)] ^ pChainingValue[j]; + } + + /* Encrypt the input block to obtain the new chaining value */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_blockcipher, + mcuxClRandomModes_DRBG_AES_Internal_blockcipher(pInputBlock, + pKey, + (uint8_t *)pChainingValue, + keyLen)); + if(MCUXCLRANDOM_STATUS_ERROR == ret_blockcipher) + { + /* Free CPU workarea used by this function (pInputBlock) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_bcc, MCUXCLRANDOM_STATUS_ERROR, + (i + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_bcc, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + /* Free CPU workarea used by this function (pInputBlock) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_bcc, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher)); +} + + +/** + * \brief This function implements the Block_Cipher_df function as specified in NIST SP800-90A. + * + * This function instantiates a CTR_DRBG in following the lines of the function CTR_DRBG_Instantiate_algorithm as specified in NIST SP800-90A. + * The function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession Handle for the current CL session + * \param pInputString[in/out] Pointer to the input string and the output of the derivation function + * \param inputStringLen[in] Byte length of the input string + * \param outputLen[in] Byte length of the output + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the CTR_DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if there was an RNG error or if a memory allocation error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the CTR_DRBG instantiation failed due to other unexpected reasons + */ +#define MCUXCLRANDOM_MAX_DF_BITS 512u + +static uint32_t const mcuxClRandomModes_CtrDrbg_df_key[8u] = { + 0x03020100u, 0x07060504u, 0x0b0a0908u, 0x0f0e0d0cu, + 0x13121110u, 0x17161514u, 0x1b1a1918u, 0x1f1e1d1cu +}; + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_df) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_df( + mcuxClSession_Handle_t pSession, + uint8_t *pInputString, + uint32_t inputStringLen, + uint32_t outputLen) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_df); + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + uint32_t seedLen = pDrbgMode->pDrbgVariant->seedLen; + uint32_t keyLen = (uint32_t)(pMode->securityStrength) / 8u; + + /* + * Step 1 specified in NIST SP800-90A: + * + * Verify that seedLen is valid. Invalid values should not occur and will trigger a FAULT_ATTACK. + */ + if (MCUXCLRANDOM_MAX_DF_BITS < seedLen * 8u) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* + * Steps 2-7 specified in NIST SP800-90A: + * + * Prepare values S and IV (input for BCC function) in CPU workarea: + * layout: IV || L || N || input_string || 0x80 || 0 padding + * length: 16 4 4 seed size 1 (16-(4+4+seedSize+1)%16)%16 + */ + + /* Allocate space for IV */ + uint32_t *pIV = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS); + if(NULL == pIV) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Determine the byte length of S: (4+4+seedSize+1 + ((16-(4+4+seedSize+1)%16)%16)) */ + uint32_t lenOfS = sizeof(uint32_t)+sizeof(uint32_t)+inputStringLen; + uint32_t tempLen = lenOfS; + /* add 1 for 0x80 */ + lenOfS += 1u; + /* pad with zeros if to align with the block size */ + if (0u != (lenOfS % MCUXCLAES_BLOCK_SIZE)) + { + lenOfS += (MCUXCLAES_BLOCK_SIZE - (lenOfS % MCUXCLAES_BLOCK_SIZE)); + } + + /* Allocate space for S */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pS is always valid in work area.") + uint32_t *pS = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(lenOfS)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + if(NULL == pS) + { + /* Free workarea (pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Pre-initialize the IV value with zeros to take care of the padding with zeros */ + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t*)pIV, 0u, MCUXCLAES_BLOCK_SIZE); + + /* Pre-initialize S with zeros to take care of cases where padding with 0 is needed at the end */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pSByte will be in the valid range pS[0 ~ lenOfS]."); + uint8_t *pSByte = (uint8_t *) pS; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUXCLMEMORY_FP_MEMORY_SET(pSByte, 0u, lenOfS); + + /* Calculate (big integer) values L and N and initialize value S as specified in NIST SP800-90A */ + uint32_t L = inputStringLen << 24; + uint32_t S = outputLen << 24; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pS is always valid in work area.") + pS[0] = L; + pS[1] = S; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("pSByte+tempLen will be in the valid range pS[0 ~ lenOfS]."); + pSByte[tempLen] = 0x80; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_df, + MCUXCLRANDOM_STATUS_FAULT_ATTACK, + (uint8_t *)&pS[2], + (uint8_t const *)pInputString, + inputStringLen); + + + /* + * Steps 8-11 specified in NIST SP800-90A: + * + * Call BCC function in a loop to determine intermediate values K and X. + */ + + /* Allocate space for a temp buffer (temp1) in CPU workarea for the output of the BCC loop. + * This buffer will later contain the values K and X concatenated: + * layout: K || X || unused + * length: keylen 16 (keylen % 16) + * + * NOTE: Additional space is reserved behind K and X for the case keyLen is not a multiple of the block size + */ + uint32_t temp1Len = MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(keyLen) + MCUXCLAES_BLOCK_SIZE; + uint32_t *pTemp1 = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(temp1Len)); + if(NULL == pTemp1) + { + /* Free workarea (pS + pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(lenOfS)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, + MCUXCLRANDOM_STATUS_ERROR, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUXCLRANDOM_FP_CALLED_SECURECOPY); + } + + /* Call BCC function in a loop */ + uint32_t outBlocks = temp1Len / MCUXCLAES_BLOCK_SIZE; + uint32_t i; + for (i = 0; i < outBlocks; i++) + { + /* Update IV value with the next loop counter converted to a (big endian) 32 bit integer padded with zeros */ + pIV[0] = i << 24; + + /* Call BCC function */ + MCUX_CSSL_FP_FUNCTION_CALL(result_bcc, + mcuxClRandomModes_CtrDrbg_bcc( + pSession, + mcuxClRandomModes_CtrDrbg_df_key, + pIV, + MCUXCLAES_BLOCK_SIZE + lenOfS, + &pTemp1[i*MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)])); + + if(MCUXCLRANDOM_STATUS_ERROR == result_bcc) + { + /* Free allocated memory (pTemp1 + pS + pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(temp1Len + lenOfS)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + (i + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_bcc)); + } + else if (MCUXCLRANDOM_STATUS_OK != result_bcc) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + /* Initialize pointers to K and X */ + uint32_t *pK = pTemp1; + uint32_t *pX = &pTemp1[keyLen/sizeof(uint32_t)]; + + + /* + * Steps 12-15 specified in NIST SP800-90A: + * + * Compute and return the output of the derivation function. + */ + + /* Reuse CPU workarea buffer IV || S for value temp2, the result of the upcoming block encryption loop */ + uint32_t *pTemp2 = pIV; + + /* Execute first block encryption and store the result directly in temp2 */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_blockcipher1, + mcuxClRandomModes_DRBG_AES_Internal_blockcipher( + pX, + pK, + (uint8_t *)pTemp2, + keyLen)); + + if(MCUXCLRANDOM_STATUS_ERROR == ret_blockcipher1) + { + /* Free CPU workarea allocated by this function (pTemp1 + pS + pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(temp1Len + lenOfS)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_bcc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_blockcipher1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Execute the remaining block encryption operations. + * + * NOTE: Different to the specification in NIST SP800-90A, input and output of the block encryption + * are stored directly in the temp2 buffer. */ + uint32_t j; + outBlocks = (uint32_t) ((outputLen + MCUXCLAES_BLOCK_SIZE - 1U) / MCUXCLAES_BLOCK_SIZE); + for (j = 1u; j < outBlocks; j++) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_blockcipher2, + mcuxClRandomModes_DRBG_AES_Internal_blockcipher( + &pTemp2[(j-1u)*MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)], + pK, + (uint8_t *)&pTemp2[j*MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)], + keyLen)); + + if (MCUXCLRANDOM_STATUS_ERROR == ret_blockcipher2) + { + /* Free CPU workarea allocated by this function (pTemp1 + pS + pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(temp1Len + lenOfS)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_bcc), + (j + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_blockcipher2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + /* Copy the result to the output buffer */ + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_FAULT_ATTACK, pInputString, (uint8_t const *)pIV, outputLen); + + /* Free CPU workarea allocated by this function (pTemp1 + pS + pIV) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLAES_BLOCK_SIZE_IN_WORDS + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(temp1Len + lenOfS)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_df, MCUXCLRANDOM_STATUS_OK, + 2u * MCUXCLRANDOM_FP_CALLED_SECURECOPY, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_bcc), + j * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher)); +} +#endif + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +/* MISRA Ex. 20 - Rule 5.1 */ +const mcuxClRandomModes_DrbgVariantDescriptor_t mcuxClRandomModes_DrbgVariantDescriptor_CtrDrbg_AES256 = +{ + .reseedInterval = MCUXCLRANDOMMODES_RESEED_INTERVAL_CTR_DRBG_AES256, + .seedLen = MCUXCLRANDOMMODES_SEEDLEN_CTR_DRBG_AES256, + .initSeedSize = MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_INIT_CTR_DRBG_AES256, + .reseedSeedSize = MCUXCLRANDOMMODES_ENTROPYINPUT_SIZE_RESEED_CTR_DRBG_AES256 +}; +#endif // MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 + +/** + * \brief This function instantiates a CTR_DRBG following the lines of the function CTR_DRBG_Instantiate_algorithm as specified in NIST SP800-90A + * + * This function instantiates a CTR_DRBG in following the lines of the function CTR_DRBG_Instantiate_algorithm as specified in NIST SP800-90A. + * The function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession Handle for the current CL session + * \param pEntropyInput[in] Pointer to entropy input + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the CTR_DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if a memory allocation error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the CTR_DRBG instantiation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, mcuxClRandomModes_instantiateAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_instantiateAlgorithm( + mcuxClSession_Handle_t pSession, uint8_t *pEntropyInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_CtrDrbg_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_CtrDrbg_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + uint32_t seedLen = pDrbgMode->pDrbgVariant->seedLen; + uint32_t initSeedSize = pDrbgMode->pDrbgVariant->initSeedSize; + + /* This max is needed as initSeedSize might be smaller than seedlen, but the df uses this buffer both for input and output. */ + uint32_t dfBufferSize = MCUXCLRANDOMMODES_MAX(initSeedSize, seedLen); + uint32_t *pSeedMaterial = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + if(NULL == pSeedMaterial) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Securely copy the seed to the seedMaterial buffer */ + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK, (uint8_t *)pSeedMaterial, (uint8_t const *)pEntropyInput, initSeedSize); + +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + /* pSeedMaterial use as both input and output */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_df, mcuxClRandomModes_CtrDrbg_df(pSession, (uint8_t *)pSeedMaterial, + initSeedSize, seedLen)); + if(MCUXCLRANDOM_STATUS_ERROR == ret_df) + { + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_df) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } +#endif + + /* Set to 0 counter V and key K in context + * According to sp800-90A, V and Key need to be initialized with zeros. + * + * NOTE: V and K lie next to each other in the context */ + uint32_t *pState = pRngCtxGeneric->state; + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *)pState, 0u, seedLen); + + /* Update the CTR_DRBG state + * + * NOTE: The size of the provided DRBG seed equals seedLen, so no padding with zeros is needed to derive the seedMaterial from the entryopInput + */ + MCUX_CSSL_FP_FUNCTION_CALL(result_updatestate, mcuxClRandomModes_CtrDrbg_UpdateState(pSession, pSeedMaterial)); + if(MCUXCLRANDOM_STATUS_ERROR == result_updatestate) + { + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#endif + } + else if (MCUXCLRANDOM_STATUS_OK != result_updatestate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Initialize the reseed counter */ + pRngCtxGeneric->reseedCounter = 1u; + + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + } +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_OK, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, MCUXCLRANDOM_STATUS_OK, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#endif +} + + +/** + * \brief This function reseeds a CTR_DRBG following the lines of the function CTR_DRBG_Reseed_algorithm as specified in NIST SP800-90A + * + * This function reseeds a CTR_DRBG following the lines of the function CTR_DRBG_Instantiate_algorithm as specified in NIST SP800-90A. + * The function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession[in] Handle for the current CL session + * \param pEntropyInput[in] Pointer to entropy input + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the CTR_DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if a memory allocation error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the CTR_DRBG instantiation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, mcuxClRandomModes_reseedAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_reseedAlgorithm(mcuxClSession_Handle_t pSession, uint8_t *pEntropyInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_reseedAlgorithm); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_CtrDrbg_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_CtrDrbg_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + uint32_t seedLen = pDrbgMode->pDrbgVariant->seedLen; + uint32_t reseedSeedSize = pDrbgMode->pDrbgVariant->reseedSeedSize; + + /* This max is needed as reseedSeedSize might be smaller than seedlen, but the df uses this buffer both for input and output. */ + uint32_t dfBufferSize = MCUXCLRANDOMMODES_MAX(reseedSeedSize, seedLen); + uint32_t *pSeedMaterial = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + if(NULL == pSeedMaterial) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Securely copy the seed to the seedMaterial buffer */ + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK, (uint8_t *)pSeedMaterial, (uint8_t const *)pEntropyInput, reseedSeedSize); + +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + /* pSeedMaterial use as both input and output */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_df, mcuxClRandomModes_CtrDrbg_df(pSession, (uint8_t *)pSeedMaterial, + reseedSeedSize, seedLen)); + if(MCUXCLRANDOM_STATUS_ERROR == ret_df) + { + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_df) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } +#endif + + /* Update the CTR_DRBG state */ + MCUX_CSSL_FP_FUNCTION_CALL(result_updatestate, mcuxClRandomModes_CtrDrbg_UpdateState(pSession, pSeedMaterial)); + if(MCUXCLRANDOM_STATUS_ERROR == result_updatestate) + { + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#endif + } + else if (MCUXCLRANDOM_STATUS_OK != result_updatestate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Reset the reseed counter */ + pRngCtxGeneric->reseedCounter = 1u; + + /* Free workarea (pSeedMaterial) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(dfBufferSize)); + } + +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_OK, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_df), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_reseedAlgorithm, MCUXCLRANDOM_STATUS_OK, + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); +#endif +} + + +/** + * \brief This function generates random numbers from a CTR_DRBG following the lines of the function CTR_DRBG_Generate_algorithm as specified in NIST SP800-90A + * + * \param pSession Handle for the current CL session + * \param pOut[out] Output buffer to which the generated randomness will be written + * \param outLength[in] Number of requested random bytes + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the random number generation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if a memory allocation error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the random number generation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_generateAlgorithm, mcuxClRandomModes_generateAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_generateAlgorithm(mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_generateAlgorithm); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_CtrDrbg_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_CtrDrbg_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + uint32_t seedLen = pDrbgMode->pDrbgVariant->seedLen; + + MCUX_CSSL_FP_FUNCTION_CALL(result_generate, + mcuxClRandomModes_CtrDrbg_generateOutput(pSession, pOut, outLength)); + if(MCUXCLRANDOM_STATUS_ERROR == result_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_generateOutput)); + } + else if(MCUXCLRANDOM_STATUS_OK != result_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Init additionalInput for state update in CPU workarea to all zeros and update the CTR_DRBG state */ + uint32_t *pAdditionalInput = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(seedLen)); + if(NULL == pAdditionalInput) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_generateOutput)); + } + + MCUXCLMEMORY_FP_MEMORY_SET((uint8_t *)pAdditionalInput, 0u, seedLen); + + MCUX_CSSL_FP_FUNCTION_CALL(result_updatestate, mcuxClRandomModes_CtrDrbg_UpdateState(pSession, pAdditionalInput)); + if(MCUXCLRANDOM_STATUS_ERROR == result_updatestate) + { + /* Free workarea (pAdditionalInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(seedLen)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_generateOutput), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set)); + } + else if (MCUXCLRANDOM_STATUS_OK != result_updatestate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Increment the reseed counter */ + pRngCtxGeneric->reseedCounter += 1u; + + /* Free workarea (pAdditionalInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(seedLen)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateAlgorithm, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_generateOutput), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_UpdateState)); + } +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_UpdateState) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_UpdateState( + mcuxClSession_Handle_t pSession, + uint32_t *pProvidedData +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_UpdateState); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_CtrDrbg_Generic_t *pCtx = (mcuxClRandomModes_Context_CtrDrbg_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + uint32_t seedLen = pDrbgMode->pDrbgVariant->seedLen; + uint32_t securityStrength = (uint32_t)(pMode->securityStrength); + uint32_t *pState = pCtx->state; + uint32_t *pKey = pState; + uint32_t *pV = &pState[securityStrength/32u]; + + /* produce the new Key and V */ + uint32_t *pTemp = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(seedLen) / sizeof(uint32_t)); + if(NULL == pTemp) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_UpdateState, MCUXCLRANDOM_STATUS_ERROR); + } + + uint32_t seedLenInBlkSize = MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(seedLen) / MCUXCLAES_BLOCK_SIZE; + uint32_t i, j; + + for (i = 0u; i < seedLenInBlkSize; i++) + { + MCUX_CSSL_FP_FUNCTION_CALL(checkIncrement, mcuxClRandomModes_CtrDrbg_incV(pV)); + if(checkIncrement == pV[(MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)) - 1u]) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_UpdateState, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + MCUX_CSSL_FP_FUNCTION_CALL(ret_blockcipher, mcuxClRandomModes_DRBG_AES_Internal_blockcipher(pV, pKey, + (uint8_t *)&pTemp[(i * MCUXCLAES_BLOCK_SIZE_IN_WORDS)], + securityStrength/8u)); + if(MCUXCLRANDOM_STATUS_ERROR == ret_blockcipher) + { + /* Free workarea (pTemp) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(seedLen) / sizeof(uint32_t)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_UpdateState, MCUXCLRANDOM_STATUS_ERROR, + (i + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + (i + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_UpdateState, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + MCUX_CSSL_FP_LOOP_DECL(xorLoop); + for (j = 0; j < (seedLen / sizeof(uint32_t)); j++) + { + /* TODO CLNS-7837 Replace with SecureXOR */ + pTemp[j] = pTemp[j] ^ pProvidedData[j]; + MCUX_CSSL_FP_LOOP_ITERATION(xorLoop); + } + + /* update the key V in context */ + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_UpdateState, + MCUXCLRANDOM_STATUS_FAULT_ATTACK, + (uint8_t *)pKey, + (uint8_t const *)pTemp, + securityStrength/8u + MCUXCLAES_BLOCK_SIZE); + + /* Free workarea (pTemp) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUND_UP_TO_AES_BLOCKSIZE(seedLen) / sizeof(uint32_t)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_UpdateState, MCUXCLRANDOM_STATUS_OK, + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV), + MCUX_CSSL_FP_LOOP_ITERATIONS(xorLoop, (seedLen / sizeof(uint32_t))), + MCUXCLRANDOM_FP_CALLED_SECURECOPY); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_CtrDrbg_generateOutput) +/* MISRA Ex. 20 - Rule 5.1 */ +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_CtrDrbg_generateOutput( + mcuxClSession_Handle_t pSession, + uint8_t *pOut, uint32_t outLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_CtrDrbg_generateOutput); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_CtrDrbg_Generic_t *pCtx = (mcuxClRandomModes_Context_CtrDrbg_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + uint32_t securityStrength = (uint32_t)(pMode->securityStrength); + + uint32_t *pState = pCtx->state; + uint32_t *pKey = pState; + uint32_t *pV = &pState[securityStrength/32u]; + const uint32_t requestSizeRemainingBytes = outLength % MCUXCLAES_BLOCK_SIZE; + uint32_t requestSizeFullBlocksBytes = outLength - requestSizeRemainingBytes; + MCUX_CSSL_FP_COUNTER_STMT(uint32_t requestSizeFullBlocks = requestSizeFullBlocksBytes / MCUXCLAES_BLOCK_SIZE); + uint32_t outIndex = 0u; + + /* Request as many random bytes as possible with full word size. */ + while (requestSizeFullBlocksBytes > 0u) + { + MCUX_CSSL_FP_FUNCTION_CALL(checkIncrement, mcuxClRandomModes_CtrDrbg_incV(pV)); + if(checkIncrement == pV[(MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)) - 1u]) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Internal_blockcipher, + mcuxClRandomModes_DRBG_AES_Internal_blockcipher(pV, pKey, &pOut[outIndex], securityStrength/8u)); + if (MCUXCLRANDOM_STATUS_ERROR == ret_Internal_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_ERROR, + (outIndex/MCUXCLAES_BLOCK_SIZE + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + (outIndex/MCUXCLAES_BLOCK_SIZE + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_Internal_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + outIndex += MCUXCLAES_BLOCK_SIZE; + requestSizeFullBlocksBytes -= MCUXCLAES_BLOCK_SIZE; + } + + /* If requested size is not a multiple of block size, request one (additional) block and use it only partially. */ + if (requestSizeRemainingBytes > 0u) + { + uint8_t requestRemainingBuffer[MCUXCLAES_BLOCK_SIZE] = {0u}; + + MCUX_CSSL_FP_FUNCTION_CALL(checkIncrement, mcuxClRandomModes_CtrDrbg_incV(pV)); + if(checkIncrement == pV[(MCUXCLAES_BLOCK_SIZE/sizeof(uint32_t)) - 1u]) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_Internal_blockcipher, + mcuxClRandomModes_DRBG_AES_Internal_blockcipher(pV, pKey, requestRemainingBuffer, securityStrength/8u)); + if(MCUXCLRANDOM_STATUS_ERROR == ret_Internal_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_ERROR, + (requestSizeFullBlocks + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + (requestSizeFullBlocks + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV)); + } + else if (MCUXCLRANDOM_STATUS_OK != ret_Internal_blockcipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Copy the remaining bytes from the buffer to output. */ + MCUXCLRANDOM_SECURECOPY(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_FAULT_ATTACK, &pOut[outIndex], requestRemainingBuffer, requestSizeRemainingBytes); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_CtrDrbg_generateOutput, MCUXCLRANDOM_STATUS_OK, + (requestSizeFullBlocks) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + (requestSizeFullBlocks) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV), + MCUX_CSSL_FP_CONDITIONAL((requestSizeRemainingBytes > 0u), + MCUXCLRANDOM_FP_CALLED_SECURECOPY, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_DRBG_AES_Internal_blockcipher), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_CtrDrbg_incV)) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_Els.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_Els.c new file mode 100644 index 000000000..e8b2a284d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_Els.c @@ -0,0 +1,93 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_DRBG_AES_Internal_blockcipher) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_DRBG_AES_Internal_blockcipher( + uint32_t const *pV, + uint32_t const *pKey, + uint8_t *pOut, + uint32_t keyLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_DRBG_AES_Internal_blockcipher); + + uint8_t elsOut[MCUXCLAES_BLOCK_SIZE]; + + mcuxClEls_CipherOption_t cipher_options = {0}; + cipher_options.bits.cphmde = MCUXCLELS_CIPHERPARAM_ALGORITHM_AES_ECB; + cipher_options.bits.dcrpt = MCUXCLELS_CIPHER_ENCRYPT; + cipher_options.bits.extkey = MCUXCLELS_CIPHER_EXTERNAL_KEY; + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(result_cipher, mcuxClEls_Cipher_Async( + cipher_options, + (mcuxClEls_KeyIndex_t)0U, + (uint8_t const *)pKey, + keyLength, + (uint8_t const *)pV, + MCUXCLAES_BLOCK_SIZE, + NULL, + elsOut)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + if (MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == result_cipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_DRBG_AES_Internal_blockcipher, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async)); + } + else if (MCUXCLELS_STATUS_OK_WAIT != result_cipher) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_DRBG_AES_Internal_blockcipher, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(result_wait, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_LEVEL1_ERROR(result_wait)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_DRBG_AES_Internal_blockcipher, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async)); + } + else if (MCUXCLELS_STATUS_OK != result_wait) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_DRBG_AES_Internal_blockcipher, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Copy the bytes from the buffer to output. */ + MCUXCLMEMORY_FP_MEMORY_COPY(pOut, elsOut, MCUXCLAES_BLOCK_SIZE); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_DRBG_AES_Internal_blockcipher, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Cipher_Async)); +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_PrDisabled.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_PrDisabled.c new file mode 100644 index 000000000..74fc773c7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_CtrDrbg_PrDisabled.c @@ -0,0 +1,150 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +#include +#include +#include +#include +#ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE +#include +#endif /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ +#include +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClRandomModes_DrbgAlgorithmsDescriptor_t mcuxClRandomModes_DrbgAlgorithmsDescriptor_CtrDrbg_PrDisabled = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + .instantiateAlgorithm = mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, + .reseedAlgorithm = mcuxClRandomModes_CtrDrbg_reseedAlgorithm, + .generateAlgorithm = mcuxClRandomModes_CtrDrbg_generateAlgorithm, + .selftestAlgorithm = mcuxClRandomModes_PrDisabled_selftestAlgorithm, + .protectionTokenInstantiateAlgorithm = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_instantiateAlgorithm, + .protectionTokenReseedAlgorithm = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_reseedAlgorithm, + .protectionTokenGenerateAlgorithm = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_CtrDrbg_generateAlgorithm, + .protectionTokenSelftestAlgorithm = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PrDisabled_selftestAlgorithm +}; + +#ifdef MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION +/* Constants for RNG health testing + * This data originates from NIST DRBG test vectors (NIST SP 800-90A DRBGVS) + * Use DF, + * No PR, + * NonceLen = 0, + * PersonalizationStringLen = 0, + * AdditionalInputLen = 0 + * Random data is read after second generate call + * + * Data has been adapted from BE Byte Order to LE Byte Order + */ +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +/* EntropyInput = 04e6975d5082bf4593c1fd93c2020624ee887666cec3fec73d6bcd376cba3f0f18c07c7ef6773a145a7f9e926cb3cd2c42cc66b30a52ec1c7a75964712933985f5e8b42d4af007 */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const uint32_t mcuxClRandomModes_TestVectors_Entropy_Init_Aes256_PrDisabled[] = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + 0x5d97e604u, 0x45bf8250u, 0x93fdc193u, 0x240602c2u, 0x667688eeu, 0xc7fec3ceu, 0x37cd6b3du, 0x0f3fba6cu, + 0x7e7cc018u, 0x143a77f6u, 0x929e7f5au, 0x2ccdb36cu, 0xb366cc42u, 0x1cec520au, 0x4796757au, 0x85399312u, + 0x2db4e8f5u, 0x0007f04au +}; +#endif + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +/* EntropyInputReseed = 41e7cf20e5b487d9d981ed7a0186872d774e610b4e246c5a899da1f4a0538c05c6d43b9726575560d3a6c4117f39cba6ba9eef65a8469d */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const uint32_t mcuxClRandomModes_TestVectors_Entropy_Reseed_Aes256_PrDisabled[] = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + 0x20cfe741u, 0xd987b4e5u, 0x7aed81d9u, 0x2d878601u, 0x0b614e77u, 0x5a6c244eu, 0xf4a19d89u, 0x058c53a0u, + 0x973bd4c6u, 0x60555726u, 0x11c4a6d3u, 0xa6cb397fu, 0x65ef9ebau, 0x009d46a8u +}; +#endif + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +/* ReturnedBits = 8e929981e59b246182c93b161a0f7900b1a65bff6579ab3dbf13ac040e9eb7964c23e17ece53d5e68adcae46c9feb06f4d48601f3483dbce99c314aa77a95f92 */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const uint32_t mcuxClRandomModes_TestVectors_RandomData_Aes256_PrDisabled[] = { +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + 0x8199928eu, 0x61249be5u, 0x163bc982u, 0x00790f1au, 0xff5ba6b1u, 0x3dab7965u, 0x04ac13bfu, 0x96b79e0eu, + 0x7ee1234cu, 0xe6d553ceu, 0x46aedc8au, 0x6fb0fec9u, 0x1f60484du, 0xcedb8334u, 0xaa14c399u, 0x925fa977u +}; +#endif + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const uint32_t * const mcuxClRandomModes_TestVectors_Aes256_PrDisabled[MCUXCLRANDOMMODES_NO_OF_TESTVECTORS_PRDISABLED] = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + mcuxClRandomModes_TestVectors_Entropy_Init_Aes256_PrDisabled, + mcuxClRandomModes_TestVectors_Entropy_Reseed_Aes256_PrDisabled, + mcuxClRandomModes_TestVectors_RandomData_Aes256_PrDisabled +}; +#endif + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const mcuxClRandomModes_DrbgModeDescriptor_t mcuxClRandomModes_DrbgModeDescriptor_CtrDrbg_AES256_PrDisabled = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + .pDrbgAlgorithms = &mcuxClRandomModes_DrbgAlgorithmsDescriptor_CtrDrbg_PrDisabled, + .pDrbgVariant = &mcuxClRandomModes_DrbgVariantDescriptor_CtrDrbg_AES256, + .pDrbgTestVectors = mcuxClRandomModes_TestVectors_Aes256_PrDisabled, + .continuousReseedInterval = 0u +}; +#endif +#else +/* Constants for RNG health testing + * This data originates from NIST DRBG test vectors (NIST SP 800-90A DRBGVS) + * No DF, + * No PR, + * NonceLen = 0, + * PersonalizationStringLen = 0, + * AdditionalInputLen = 0 + * Random data is read after second generate call + * + * Data has been adapted from BE Byte Order to LE Byte Order + */ + +// TODO: Add test vectors for the "no derivation function case" + +#endif /* MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION */ + + + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER("Const must be discarded to initialize the generic structure member.") +const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdCtrDrbg_AES256_DRG3 = { +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + .pOperationMode = &mcuxClRandomModes_OperationModeDescriptor_NormalMode_PrDisabled, + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST("Casts to void* are allowed") + .pDrbgMode = (void *) &mcuxClRandomModes_DrbgModeDescriptor_CtrDrbg_AES256_PrDisabled, + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST() + .contextSize = MCUXCLRANDOMMODES_CTR_DRBG_AES256_CONTEXT_SIZE, +#ifdef MCUXCL_FEATURE_RANDOMMODES_TESTMODE + .auxParam = (uint32_t) &mcuxClRandomModes_OperationModeDescriptor_TestMode_PrDisabled, +#else + .auxParam = 0u, +#endif /* MCUXCL_FEATURE_RANDOMMODES_TESTMODE */ + .securityStrength = MCUXCLRANDOMMODES_SECURITYSTRENGTH_CTR_DRBG_AES256 +}; +MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() +#endif + diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_ElsMode.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_ElsMode.c new file mode 100644 index 000000000..45957d3cd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_ElsMode.c @@ -0,0 +1,221 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRandomModes_ElsMode.c + * @brief Implementation of the Random component which provides APIs for + * handling of random number generators. This file implements the functions + * declared in mcuxClRandom.h. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_ElsMode_init) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_init( + mcuxClSession_Handle_t pSession +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_ElsMode_reseed) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_reseed( + mcuxClSession_Handle_t pSession +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_ElsMode_selftest) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_selftest( + mcuxClSession_Handle_t pSession, + mcuxClRandom_Mode_t mode +); + +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRandomModes_ElsMode_generate) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_generate( + mcuxClSession_Handle_t pSession, + uint8_t * pOut, + uint32_t outLength +); + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_ElsMode_init) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_init( + mcuxClSession_Handle_t pSession UNUSED_PARAM +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_ElsMode_init); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_init, MCUXCLRANDOM_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_ElsMode_reseed) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_reseed( + mcuxClSession_Handle_t pSession UNUSED_PARAM +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_ElsMode_reseed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_reseed, MCUXCLRANDOM_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_ElsMode_selftest) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_selftest( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + mcuxClRandom_Mode_t mode +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_ElsMode_selftest); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_selftest, MCUXCLRANDOM_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_ElsMode_generate) +static MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_ElsMode_generate( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint8_t * pOut, + uint32_t outLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_ElsMode_generate); + + /** + * ELS DRBG output size must be a multiple of 4. + * We first request as much as possible directly, and then use a small buffer + * to copy up to 3 remaining bytes. + */ + + /** + * Note: writing to pOut could be unaligned. + * This could be improved by: - requesting a single word + * - copying as many bytes as needed to achieve alignment + * - requesting the following words to aligned addresses + * - possibly requesting another single word to fill the remaining bytes + */ + + uint32_t requestSizeMin = MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE; + uint32_t requestSizeRemainingBytes = outLength % requestSizeMin; + uint32_t requestSizeFullWordsBytes = outLength - requestSizeRemainingBytes; + + /* Request as many random bytes as possible with full word size. */ + if (requestSizeFullWordsBytes > 0u) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_GetRandom1, mcuxClEls_Rng_DrbgRequest_Async(pOut, requestSizeFullWordsBytes)); + if (MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_DRBG_GetRandom1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async)); + } + else if(MCUXCLELS_STATUS_OK_WAIT != ret_DRBG_GetRandom1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_Wait1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_LEVEL1_ERROR(ret_DRBG_Wait1)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK != ret_DRBG_Wait1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + /* If requested size is not a multiple of 4, request one (additional) word and use it only partially. */ + if (requestSizeRemainingBytes > 0u) + { + uint8_t requestRemainingBuffer[MCUXCLELS_RNG_DRBG_TEST_EXTRACT_OUTPUT_MIN_SIZE] = {0u}; + + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_GetRandom2, mcuxClEls_Rng_DrbgRequest_Async(requestRemainingBuffer, + requestSizeMin)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + if (MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_DRBG_GetRandom2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_ERROR, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK_WAIT != ret_DRBG_GetRandom2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_Wait2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if(MCUXCLELS_LEVEL1_ERROR(ret_DRBG_Wait2)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_ERROR, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK != ret_DRBG_Wait2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Copy the remaining bytes from the buffer to output. */ + for(uint32_t i = 0u; i < requestSizeRemainingBytes; i++) + { + pOut[requestSizeFullWordsBytes + i] = requestRemainingBuffer[i]; + } + + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_ElsMode_generate, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((requestSizeFullWordsBytes > 0u), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)), + MCUX_CSSL_FP_CONDITIONAL((requestSizeRemainingBytes > 0u), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequest_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation))); +} + + +static const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_ELS_Drbg = { + .initFunction = mcuxClRandomModes_ElsMode_init, + .reseedFunction = mcuxClRandomModes_ElsMode_reseed, + .generateFunction = mcuxClRandomModes_ElsMode_generate, + .selftestFunction = mcuxClRandomModes_ElsMode_selftest, + .protectionTokenInitFunction = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_ElsMode_init), + .protectionTokenReseedFunction = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_ElsMode_reseed), + .protectionTokenGenerateFunction = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_ElsMode_generate), + .protectionTokenSelftestFunction = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_ElsMode_selftest), + .operationMode = MCUXCLRANDOMMODES_ELSMODE +}; + + +const mcuxClRandom_ModeDescriptor_t mcuxClRandomModes_mdELS_Drbg = { + .pOperationMode = &mcuxClRandomModes_OperationModeDescriptor_ELS_Drbg, + .pDrbgMode = NULL, + .contextSize = 0u, + .auxParam = 0u, + .securityStrength = 128u +}; diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_NormalMode.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_NormalMode.c new file mode 100644 index 000000000..42d25c0d5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_NormalMode.c @@ -0,0 +1,382 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_NormalMode_PrDisabled = { +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + .initFunction = mcuxClRandomModes_NormalMode_initFunction, + .reseedFunction = mcuxClRandomModes_NormalMode_reseedFunction, + .generateFunction = mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, + .selftestFunction = mcuxClRandomModes_NormalMode_selftestFunction, + .protectionTokenInitFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_initFunction, + .protectionTokenReseedFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_reseedFunction, + .protectionTokenGenerateFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, + .protectionTokenSelftestFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_selftestFunction, + .operationMode = MCUXCLRANDOMMODES_NORMALMODE, +}; +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + + +/** + * \brief This function instantiates a DRBG in NORMAL_MODE following the lines of the function Instantiate_function specified in NIST SP800-90A + * + * This function instantiates a DRBG in NORMAL_MODE following the lines of the function Instantiate_function specified in NIST SP800-90A. + * The function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession[in] Handle for the current CL session + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if a memory allocation error or non-critical TRNG error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the DRBG instantiation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_NormalMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_initFunction(mcuxClSession_Handle_t pSession) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_NormalMode_initFunction); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) sessionMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + /* Initialize buffer in CPU workarea for the entropy input to derive the DRBG seed */ + uint32_t *pEntropyInput = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->initSeedSize)); + if(NULL == pEntropyInput) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Call TRNG initialization function to ensure it's properly configured for upcoming TRNG accesses */ + MCUX_CSSL_FP_FUNCTION_CALL(result_trngInit, mcuxClTrng_Init()); + if (MCUXCLTRNG_STATUS_OK != result_trngInit) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Generate entropy input using the TRNG */ + MCUX_CSSL_FP_FUNCTION_CALL(result_trng, + mcuxClTrng_getEntropyInput(pSession, pEntropyInput, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->initSeedSize)*sizeof(uint32_t)) + ); + if(MCUXCLTRNG_STATUS_ERROR == result_trng) + { + /* Free workarea (pEntropyInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->initSeedSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_Init), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_getEntropyInput)); + } + else if (MCUXCLTRNG_STATUS_OK != result_trng) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Derive the initial DRBG state from the generated entropy input */ + MCUX_CSSL_FP_FUNCTION_CALL(result_instantiate, pDrbgMode->pDrbgAlgorithms->instantiateAlgorithm(pSession, (uint8_t *) pEntropyInput)); + if(MCUXCLRANDOM_STATUS_ERROR == result_instantiate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_Init), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_getEntropyInput), + pDrbgMode->pDrbgAlgorithms->protectionTokenInstantiateAlgorithm); + } + else if (MCUXCLRANDOM_STATUS_OK != result_instantiate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Initialize the reseedSeedOffset field of the context */ + pRngCtxGeneric->reseedSeedOffset = 0u; + + /* Free workarea (pEntropyInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->initSeedSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_initFunction, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_Init), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_getEntropyInput), + pDrbgMode->pDrbgAlgorithms->protectionTokenInstantiateAlgorithm); + } +} + + +/** + * \brief This function reseeds a DRBG in NORMAL_MODE following the lines of the function Reseed_function specified in NIST SP800-90A + * + * This function reseed a DRBG in NORMAL_MODE following the lines of the function Reseed_function specified in NIST SP800-90A. + * The function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession[in] Handle for the current CL session + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the DRBG reseeding finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if a memory allocation error or non-critical TRNG error occured + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the DRBG reseeding failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_NormalMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_reseedFunction(mcuxClSession_Handle_t pSession) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_NormalMode_reseedFunction); + + mcuxClRandom_Mode_t sessionMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) sessionMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + /* Initialize buffer in CPU workarea for the entropy input to derive the DRBG seed */ + uint32_t *pEntropyInput = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->reseedSeedSize)); + if(NULL == pEntropyInput) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Generate entropy input using the TRNG */ + MCUX_CSSL_FP_FUNCTION_CALL(result_trng, + mcuxClTrng_getEntropyInput(pSession, pEntropyInput, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->reseedSeedSize) * sizeof(uint32_t)) + ); + if(MCUXCLTRNG_STATUS_ERROR == result_trng) + { + /* Free workarea (pEntropyInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->reseedSeedSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_ERROR); + } + else if (MCUXCLTRNG_STATUS_OK != result_trng) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Derive the initial DRBG state from the generated entropy input */ + MCUX_CSSL_FP_FUNCTION_CALL(result_reseed, pDrbgMode->pDrbgAlgorithms->reseedAlgorithm(pSession,(uint8_t *) pEntropyInput)); + if(MCUXCLRANDOM_STATUS_ERROR == result_reseed) + { + /* Free workarea (pEntropyInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->reseedSeedSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_getEntropyInput), + pDrbgMode->pDrbgAlgorithms->protectionTokenReseedAlgorithm); + } + else if (MCUXCLRANDOM_STATUS_OK != result_reseed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Free workarea (pEntropyInput) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pDrbgMode->pDrbgVariant->reseedSeedSize)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_reseedFunction, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_getEntropyInput), + pDrbgMode->pDrbgAlgorithms->protectionTokenReseedAlgorithm); + } +} + + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +/** + * \brief This function generates random numbers from a DRBG in NORMAL_MODE following the lines of the function Generate_function specified in NIST SP800-90A + * and reseeds according to the DRG.3 security level. + * + * This function generates random numbers from a DRBG in NORMAL_MODE following the lines of the function Generate_function specified in NIST SP800-90A. + * If reseedCounter overflowed, the DRBG will be reseeded before the randomness generation. + * If so, the function obtains entropy input for the DRBG seed from the TRNG. + * + * \param pSession[in] Handle for the current CL session + * \param pOut[out] Output buffer to which the generated randomness will be written + * \param outLength Number of requested random bytes + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the random number generation finished successfully + * - MCUXCLRANDOM_STATUS_ERROR if the DRBG could not be reseeded or if the generation failed because a non-critical HW error occurred + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the random number generation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, mcuxClRandom_generateFunction_t) +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_generateFunction_PrDisabled(mcuxClSession_Handle_t pSession, uint8_t *pOut, uint32_t outLength) +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_Context_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t pMode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, + MCUX_CSSL_FP_CONDITIONAL((pRngCtxGeneric->reseedCounter >= pDrbgMode->pDrbgVariant->reseedInterval), + pMode->pOperationMode->protectionTokenReseedFunction)); + + + /* Reseed the DRBG state if the reseed counter overflowed */ + if (pRngCtxGeneric->reseedCounter >= pDrbgMode->pDrbgVariant->reseedInterval) + + { + MCUX_CSSL_FP_FUNCTION_CALL(result_reseed, pMode->pOperationMode->reseedFunction(pSession)); + if(MCUXCLRANDOM_STATUS_ERROR == result_reseed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, MCUXCLRANDOM_STATUS_ERROR); + } + else if (MCUXCLRANDOM_STATUS_OK != result_reseed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + + /* Generate random bytes */ + MCUX_CSSL_FP_FUNCTION_CALL(result_generate, pDrbgMode->pDrbgAlgorithms->generateAlgorithm(pSession, pOut, outLength)); + if(MCUXCLRANDOM_STATUS_ERROR == result_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, MCUXCLRANDOM_STATUS_ERROR, + pDrbgMode->pDrbgAlgorithms->protectionTokenGenerateAlgorithm); + } + else if (MCUXCLRANDOM_STATUS_OK != result_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, MCUXCLRANDOM_STATUS_OK, + pDrbgMode->pDrbgAlgorithms->protectionTokenGenerateAlgorithm); + } +} +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + + + +/** + * \brief This function performs a selftest of a DRBG in NORMAL_MODE + * + * The specific test pattern depends on the drbgMode. + * + * @param pSession[in] Handle for the current CL session + * @param mode[in] Mode of operation for random data generator. + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the selftest executed finished successfully + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the selftest failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_NormalMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_NormalMode_selftestFunction(mcuxClSession_Handle_t pSession, mcuxClRandom_Mode_t mode) +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_NormalMode_selftestFunction); + /* Back up Random configuration of current session */ + mcuxClRandom_Mode_t modeBackup = pSession->randomCfg.mode; + mcuxClRandom_Context_t ctxBackup = pSession->randomCfg.ctx; + + /* Allocate space for new testMode */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING("Return pointer is 32-bit aligned and satisfies the requirement of mcuxClRandom_ModeDescriptor_t") + mcuxClRandom_ModeDescriptor_t *pTestModeDesc = (mcuxClRandom_ModeDescriptor_t *)mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE)); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() + if(NULL == pTestModeDesc) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_selftestFunction, MCUXCLRANDOM_STATUS_ERROR); + } + + /* Derive testMode from passed mode */ + MCUX_CSSL_FP_FUNCTION_CALL(result_create, mcuxClRandomModes_createTestFromNormalMode(pTestModeDesc, mode, NULL)); + if (MCUXCLRANDOM_STATUS_OK != result_create) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_selftestFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Allocate space for ctxBuffer according to the contextSize */ + uint32_t *ctxBuffer = mcuxClSession_allocateWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pTestModeDesc->contextSize)); + if(NULL == ctxBuffer) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_selftestFunction, MCUXCLRANDOM_STATUS_ERROR); + } + mcuxClRandom_Context_t pTestCtx = (mcuxClRandom_Context_t) ctxBuffer; + + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) mode->pDrbgMode; + + /* Call function executing the DRBG mode specific selftest algorithm */ + MCUX_CSSL_FP_FUNCTION_CALL(result_selftest, pDrbgMode->pDrbgAlgorithms->selftestAlgorithm(pSession, pTestCtx, pTestModeDesc)); + if(MCUXCLRANDOM_STATUS_OK != result_selftest) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_selftestFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Restore Random configuration of session */ + pSession->randomCfg.mode = modeBackup; + pSession->randomCfg.ctx = ctxBackup; + + /* Free workarea (pTestModeDesc and ctxBuffer) */ + mcuxClSession_freeWords_cpuWa(pSession, MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(MCUXCLRANDOMMODES_TESTMODE_DESCRIPTOR_SIZE) + MCUXCLRANDOMMODES_ROUNDED_UP_CPU_WORDSIZE(pTestModeDesc->contextSize)); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_NormalMode_selftestFunction, MCUXCLRANDOM_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_createTestFromNormalMode), + pDrbgMode->pDrbgAlgorithms->protectionTokenSelftestAlgorithm); +} + + +/** + * \brief This function performs a comparison of two arrays + * + * @param wordLength[in] Length of arrays to compare in word size + * @param expected[in] Input buffer with expected value + * @param actual[in] Input buffer with actual value, to be compared with expected value + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the arrays are equal + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the arrays are not equal + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_selftest_VerifyArrays) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_selftest_VerifyArrays(uint32_t wordLength, const uint32_t * const expected, uint32_t *actual) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_selftest_VerifyArrays); + + for (uint32_t i = 0u; i < wordLength; i++) + { + if (expected[i] != actual[i]) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_selftest_VerifyArrays, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_selftest_VerifyArrays, MCUXCLRANDOM_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PatchMode.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PatchMode.c new file mode 100644 index 000000000..6281139a5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PatchMode.c @@ -0,0 +1,126 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +#include +#include +#include + +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +static const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_PatchMode = { +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + .initFunction = mcuxClRandomModes_PatchMode_initFunction, + .reseedFunction = mcuxClRandomModes_PatchMode_reseedFunction, + .generateFunction = mcuxClRandomModes_PatchMode_generateFunction, + .selftestFunction = mcuxClRandomModes_PatchMode_selftestFunction, + .protectionTokenInitFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_initFunction, + .protectionTokenReseedFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_reseedFunction, + .protectionTokenGenerateFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_generateFunction, + .protectionTokenSelftestFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_PatchMode_selftestFunction, + .operationMode = MCUXCLRANDOMMODES_PATCHMODE, +}; + +/** + * \brief This function creates a PATCH_MODE descriptor + * + * This function creates a PATCH_MODE descriptor. + * The function expects as input a custom function to be used inside the CL functions for random number generation as well as + * a pointer to a context buffer which can be used by the custom generate function. + * The custom generate function may also use all CPU workarea allocated for the mcuxClRandom_generate function. + * The function shall be called prior to an mcuxClRandom_init call. + * + * \param patchMode[out] Pointer to PATCH_MODE descriptor to be initialized + * \param customGenerateAlgorithm[in] Pointer to the custom generate function + * \param pCustomCtx[in] Pointer to a custom context which shall be used by the passed custom generate function + * \param securityStrength[in] Pointer to the supported security strength of DRBG + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the PATCH_MODE descriptor generation was successful + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_createPatchMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createPatchMode(mcuxClRandom_ModeDescriptor_t *patchMode, mcuxClRandomModes_CustomGenerateAlgorithm_t customGenerateAlgorithm, mcuxClRandom_Context_t pCustomCtx, uint32_t securityStrength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_createPatchMode); + + patchMode->pOperationMode = &mcuxClRandomModes_OperationModeDescriptor_PatchMode; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_STRUCT("As pDrbgMode is used for multiple purposes due to memory saving it must be a void pointer.") + patchMode->pDrbgMode = (void*)customGenerateAlgorithm; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_STRUCT() + patchMode->contextSize = 0u; + patchMode->auxParam = (uint32_t) pCustomCtx; + patchMode->securityStrength = (uint16_t) securityStrength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandomModes_createPatchMode, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK); +} + + +/** + * \brief Empty function called during mcuxClRandom_init when PATCH_MODE is activated + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_PatchMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_initFunction(mcuxClSession_Handle_t session UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_PatchMode_initFunction); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PatchMode_initFunction, MCUXCLRANDOM_STATUS_OK); +} + +/** + * \brief Empty function called during mcuxClRandom_reseed when PATCH_MODE is activated + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_PatchMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_reseedFunction(mcuxClSession_Handle_t session UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_PatchMode_reseedFunction); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PatchMode_reseedFunction, MCUXCLRANDOM_STATUS_OK); +} + +/** + * \brief Function called during mcuxClRandom_generate when PATCH_MODE is activated in order to call the custom generate function + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_PatchMode_generateFunction, mcuxClRandom_generateFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_generateFunction(mcuxClSession_Handle_t session, uint8_t *pOut, uint32_t outLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_PatchMode_generateFunction); + + mcuxClRandom_Mode_t mode = (mcuxClRandom_Mode_t) session->randomCfg.mode; + mcuxClRandom_Context_t pCustomCtx = (mcuxClRandom_Context_t) mode->auxParam; + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_STRUCT("As pDrbgMode is used for multiple purposes due to memory saving it must be a void pointer.") + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST("Type is a function pointer. const qualifier is meaningless on cast type") + mcuxClRandomModes_CustomGenerateAlgorithm_t pCustomAlg = (mcuxClRandomModes_CustomGenerateAlgorithm_t) mode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST() + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_STRUCT() + + mcuxClRandom_Status_t result_customAlg = pCustomAlg(session, pCustomCtx, pOut, outLength); + if(MCUXCLRANDOM_STATUS_OK != result_customAlg) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PatchMode_generateFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PatchMode_generateFunction, MCUXCLRANDOM_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_PatchMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PatchMode_selftestFunction(mcuxClSession_Handle_t session UNUSED_PARAM, mcuxClRandom_Mode_t mode UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_PatchMode_selftestFunction); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PatchMode_selftestFunction, MCUXCLRANDOM_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PrDisabled.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PrDisabled.c new file mode 100644 index 000000000..2e760742b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_PrDisabled.c @@ -0,0 +1,167 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + + +/** + * \brief This function performs a selftest of a DRBG if prediction resistance is disabled + * + * This function performs a selftest of a DRBG if prediction resistance is disabled. More precisely, it implements a CAVP like known answer test as specified in + * + * https://csrc.nist.gov/CSRC/media/Projects/Cryptographic-Algorithm-Validation-Program/documents/drbg/DRBGVS.pdf + * + * i.e. known answer tests for the following flow are executed + * + * (initialize entropy input) + * init + * (update entropy input) + * reseed + * generate + * generate + * uninit + * + * @param [in] pSession Handle for the current CL session. + * @param [in] testCtx Pointer to a Random data context buffer large enough + * to hold the context for the selected @p pTestMode + * @param [in] pTestMode Mode of operation for random data generator. + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the selftest finished successfully + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the selftest failed + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_PrDisabled_selftestAlgorithm, mcuxClRandomModes_selftestAlgorithm_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_PrDisabled_selftestAlgorithm(mcuxClSession_Handle_t pSession, mcuxClRandom_Context_t pTestCtx, mcuxClRandom_ModeDescriptor_t *pTestMode) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_PrDisabled_selftestAlgorithm); + + /* Set entropy input pointer in pTestMode */ + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) pTestMode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + const uint32_t *const * testVectors = pDrbgMode->pDrbgTestVectors; + MCUX_CSSL_FP_FUNCTION_CALL(ret_updateIn, mcuxClRandomModes_updateEntropyInput(pTestMode, + testVectors[MCUXCLRANDOMMODES_TESTVECTORS_INDEX_ENTROPY_PRDISABLED])); + (void)ret_updateIn; + + /*********************************************** + * Initialize DRBG with known entropy using * + * mcuxClRandom_init function * + ************************************************/ + + /* Call Random_init */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_init, mcuxClRandom_init(pSession, (mcuxClRandom_Context_t)pTestCtx, pTestMode)); + if(MCUXCLRANDOM_STATUS_OK != ret_init) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + + /*********************************************** + * Reseed with known entropy using * + * mcuxClRandom_reseed function * + ************************************************/ + + /* Input new entropy to be used for reseeding by updating pTestMode */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_updateIn2, mcuxClRandomModes_updateEntropyInput(pTestMode, + testVectors[MCUXCLRANDOMMODES_TESTVECTORS_INDEX_ENTROPY_RESEED_PRDISABLED])); + (void)ret_updateIn2; + + MCUX_CSSL_FP_FUNCTION_CALL(ret_reseed, mcuxClRandom_reseed(pSession)); + /* Call Random_reseed */ + if(MCUXCLRANDOM_STATUS_OK != ret_reseed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + + /*********************************************** + * Generate first value using * + * mcuxClRandom_generate function * + ***********************************************/ + + uint32_t randomBytes[MCUXCLRANDOMMODES_SELFTEST_RANDOMDATALENGTH/sizeof(uint32_t)]; + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(ret_generate, + mcuxClRandom_generate(pSession, (uint8_t*)randomBytes, MCUXCLRANDOMMODES_SELFTEST_RANDOMDATALENGTH)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + if(MCUXCLRANDOM_STATUS_OK != ret_generate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + + /*********************************************** + * Generate second value using * + * mcuxClRandom_generate function * + ***********************************************/ + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(ret_generate2, + mcuxClRandom_generate(pSession, (uint8_t*)randomBytes, MCUXCLRANDOMMODES_SELFTEST_RANDOMDATALENGTH)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + if(MCUXCLRANDOM_STATUS_OK != ret_generate2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Verify generated random bytes */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_verifyOutput, mcuxClRandomModes_selftest_VerifyArrays(MCUXCLRANDOMMODES_SELFTEST_RANDOMDATALENGTH/(sizeof(uint32_t)), + testVectors[MCUXCLRANDOMMODES_TESTVECTORS_INDEX_RANDOMDATA_PRDISABLED], + randomBytes)); + if(MCUXCLRANDOM_STATUS_OK != ret_verifyOutput) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /*********************************************** + * Clean up using mcuxClRandom_uninit function * + ***********************************************/ + + uint32_t contextSizeInWords = pTestMode->contextSize / sizeof(uint32_t); + MCUX_CSSL_FP_FUNCTION_CALL(ret_uninit, mcuxClRandom_uninit(pSession)); + if(MCUXCLRANDOM_STATUS_OK != ret_uninit) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Verify whether context is clear */ + for (uint32_t i = 0u; i < contextSizeInWords; i++) + { + if(((uint32_t *) pTestCtx)[i] != 0u) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandomModes_PrDisabled_selftestAlgorithm, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_updateEntropyInput), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_init), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_updateEntropyInput), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_reseed), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandomModes_selftest_VerifyArrays), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_uninit) ); +} diff --git a/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_TestMode.c b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_TestMode.c new file mode 100644 index 000000000..1ad30a65b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRandomModes/src/mcuxClRandomModes_TestMode.c @@ -0,0 +1,161 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#ifdef MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +const mcuxClRandom_OperationModeDescriptor_t mcuxClRandomModes_OperationModeDescriptor_TestMode_PrDisabled = +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() +{ + .initFunction = mcuxClRandomModes_TestMode_initFunction, + .reseedFunction = mcuxClRandomModes_TestMode_reseedFunction, + .generateFunction = mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, + .selftestFunction = mcuxClRandomModes_TestMode_selftestFunction, + .protectionTokenInitFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_initFunction, + .protectionTokenReseedFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_reseedFunction, + .protectionTokenGenerateFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_NormalMode_generateFunction_PrDisabled, + .protectionTokenSelftestFunction = MCUX_CSSL_FP_FUNCID_mcuxClRandomModes_TestMode_selftestFunction, + .operationMode = MCUXCLRANDOMMODES_TESTMODE, +}; +#endif /* MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED */ + + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_createTestFromNormalMode) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_createTestFromNormalMode(mcuxClRandom_ModeDescriptor_t *pTestMode, mcuxClRandom_Mode_t normalMode, const uint32_t * const pEntropyInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_createTestFromNormalMode); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER("For a normal mode, auxParam contains a pointer to mcuxClRandom_OperationModeDescriptor_t") + pTestMode->pOperationMode = (mcuxClRandom_OperationModeDescriptor_t *) normalMode->auxParam; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() + pTestMode->pDrbgMode = normalMode->pDrbgMode; + pTestMode->auxParam = (uint32_t) pEntropyInput; + pTestMode->contextSize = normalMode->contextSize; + pTestMode->securityStrength = normalMode->securityStrength; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandomModes_createTestFromNormalMode, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_updateEntropyInput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_updateEntropyInput(mcuxClRandom_ModeDescriptor_t *pTestMode, const uint32_t * const pEntropyInput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_updateEntropyInput); + + pTestMode->auxParam = (uint32_t) pEntropyInput; + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRandomModes_updateEntropyInput, MCUXCLRANDOM_STATUS_OK, MCUXCLRANDOM_STATUS_FAULT_ATTACK); +} + + +/** + * \brief This function instantiates a DRBG in TEST_MODE following the lines of the function Instantiate_function specified in NIST SP800-90A + * + * This function instantiates a DRBG in TEST_MODE following the lines of the function Instantiate_function specified in NIST SP800-90A. + * The function reads entropy input for the DRBG seed from a buffer provided by the user of the CL. + * + * \param session[in] Handle for the current CL session + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the DRBG instantiation finished successfully + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the DRBG instantiation failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_TestMode_initFunction, mcuxClRandom_initFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_initFunction(mcuxClSession_Handle_t pSession) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_TestMode_initFunction); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + mcuxClRandomModes_Context_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t mode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) mode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + /* Derive the initial DRBG state from the generated entropy input */ + MCUX_CSSL_FP_FUNCTION_CALL(result_instantiate, pDrbgMode->pDrbgAlgorithms->instantiateAlgorithm(pSession, (uint8_t *) mode->auxParam)); + if (MCUXCLRANDOM_STATUS_OK != result_instantiate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_TestMode_initFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + /* Initialize the reseedSeedOffset field of the context */ + pRngCtxGeneric->reseedSeedOffset = 0u; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_TestMode_initFunction, MCUXCLRANDOM_STATUS_OK, + pDrbgMode->pDrbgAlgorithms->protectionTokenInstantiateAlgorithm); +} + + +/** + * \brief This function reseeds a DRBG in TEST_MODE following the lines of the function Reseed_function specified in NIST SP800-90A + * + * This function reseeds a DRBG in TEST_MODE following the lines of the function Reseed_function specified in NIST SP800-90A. + * The function reads entropy input for the DRBG seed from a buffer provided by the user of the CL. + * + * \param session[in] Handle for the current CL session + * + * \return + * - MCUXCLRANDOM_STATUS_OK if the DRBG reseeding finished successfully + * - MCUXCLRANDOM_STATUS_FAULT_ATTACK if the DRBG reseeding failed due to other unexpected reasons + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_TestMode_reseedFunction, mcuxClRandom_reseedFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_reseedFunction(mcuxClSession_Handle_t pSession) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_TestMode_reseedFunction); + + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_Context_Generic_t *pRngCtxGeneric = (mcuxClRandomModes_Context_Generic_t *) pSession->randomCfg.ctx; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + mcuxClRandom_Mode_t mode = pSession->randomCfg.mode; + MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() + const mcuxClRandomModes_DrbgModeDescriptor_t *pDrbgMode = (const mcuxClRandomModes_DrbgModeDescriptor_t *) mode->pDrbgMode; + MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() + + /* Derive the initial DRBG state from the user-defined entropy input */ + MCUX_CSSL_FP_FUNCTION_CALL(result_reseed, pDrbgMode->pDrbgAlgorithms->reseedAlgorithm(pSession, (((uint8_t *) mode->auxParam) + pRngCtxGeneric->reseedSeedOffset))); + if (MCUXCLRANDOM_STATUS_OK != result_reseed) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_TestMode_reseedFunction, MCUXCLRANDOM_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_TestMode_reseedFunction, MCUXCLRANDOM_STATUS_OK, + pDrbgMode->pDrbgAlgorithms->protectionTokenReseedAlgorithm); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRandomModes_TestMode_selftestFunction, mcuxClRandom_selftestFunction_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRandom_Status_t) mcuxClRandomModes_TestMode_selftestFunction(mcuxClSession_Handle_t pSession UNUSED_PARAM, mcuxClRandom_Mode_t mode UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRandomModes_TestMode_selftestFunction); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRandomModes_TestMode_selftestFunction, MCUXCLRANDOM_STATUS_OK); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_ComputeD_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_ComputeD_FUP.h new file mode 100644 index 000000000..798f5d9fb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_ComputeD_FUP.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_ComputeD_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_ComputeD +*/ +#ifndef MCUXCLRSA_COMPUTED_FUP_H_ +#define MCUXCLRSA_COMPUTED_FUP_H_ +#include // Exported features flags header +#include + +#define mcuxClRsa_ComputeD_Steps123_FUP_LEN 6u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_ComputeD_Steps123_FUP[mcuxClRsa_ComputeD_Steps123_FUP_LEN]; + +#endif /* MCUXCLRSA_COMPUTED_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Functions.h new file mode 100644 index 000000000..8f7b7b5f5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Functions.h @@ -0,0 +1,1053 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Internal_Functions.h + * @brief Internal functions of the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_INTERNAL_FUNCTIONS_H_ +#define MCUXCLRSA_INTERNAL_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClRsa_Internal_Functions mcuxClRsa_Internal_Functions + * @brief Defines all internal functions of @ref mcuxClRsa + * @ingroup mcuxClRsa + * @{ + */ + +/** + * \brief RSA public operation + * + * This function performs an RSA public key operation according to PKCS #1 v2.2. + * The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8. + * The public exponent is limited to 2 <= e < N. + * + * \param[in] pSession Pointer to #mcuxClSession_Descriptor + * \param[in] pKey Pointer to key structure of type @ref mcuxClRsa_Key + * \param[in] pInput Pointer to input + * \param[out] pOutput Pointer to result + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pKey:
+ *
The key entries meet the following conditions: + * - Entry keytype must be set to #MCUXCLRSA_KEY_PUBLIC. In case of passing another key type, the function + * returns #MCUXCLRSA_STATUS_INVALID_INPUT. The functions checks, internally, whether the required key entries + * are not set to NULL. If so, the function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8; + * - It is required that e is greater or equal to 2 and smaller than n. + *
pInput:
+ *
The input must meet the following conditions: + * - It is provided in big-endian byte order; + * - The input length is determined by the modulus length. + *
pOutput:
+ *
The output meets the following conditions: + * - It is located in PKC RAM; + * - A buffer of modulus length bytes has to be allocated; + * - The result is stored in little-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_public operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_public, mcuxClRsa_PublicExpEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_public( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pInput, + mcuxCl_Buffer_t pOutput +); + + +/** + * \brief RSA private plain operation + * + * This function performs an RSA private plain key operation according to PKCS #1 v2.2. + * The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8. + * The private exponent is limited to d < N. + * + * \param[in] pSession Pointer to #mcuxClSession_Descriptor + * \param[in] pKey Pointer to key structure of type @ref mcuxClRsa_Key + * \param[in] pInput Pointer to input + * \param[out] pOutput Pointer to result + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pKey:
+ *
The key entries meet the following conditions: + * - Entry keytype must be set to #MCUXCLRSA_KEY_PRIVATEPLAIN. In case of passing another key type, the function + * returns #MCUXCLRSA_STATUS_INVALID_INPUT. The functions checks, internally, whether the required key entries + * are not set to NULL. If so, the function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8; + * - It is required that d is smaller than n. + *
pInput:
+ *
The input meets the following conditions: + * - It is located in PKC RAM; + * - It is provided in little-endian byte order; + * - The input buffer length should be: + * MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(modulus length) = MCUXCLRSA_PKC_ROUNDUP_SIZE(modulus length) + 2*MCUXCLRSA_PKC_WORDSIZE. + * Inside this buffer, the input has the same byte length as the modulus, while upper bytes are used as temporary buffer for internal operations. + * - It is overwritten by the function. + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated; + * - The result is stored in big-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_privatePlain operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_privatePlain) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_privatePlain( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_Buffer_t pInput, + mcuxCl_Buffer_t pOutput +); + + +/** + * \brief RSA private CRT operation + * + * This function performs an RSA private CRT key operation according to PKCS #1 v2.2. + * The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8. + * The length of the primes is limited to: size(p) = size(q) = 1/2 size(n). + * The private exponent is limited to d < N. + * + * \param[in] pSession Pointer to #mcuxClSession_Descriptor + * \param[in] pKey Pointer to key structure of type @ref mcuxClRsa_Key + * \param[in] pInput Pointer to input + * \param[out] pOutput Pointer to result + * + **
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pKey:
+ *
The key entries meet the following conditions: + * - Entry keytype must be set to #MCUXCLRSA_KEY_PRIVATECRT or #MCUXCLRSA_KEY_PRIVATECRT_DFA. In case of passing + * another key type, the function returns #MCUXCLRSA_STATUS_INVALID_INPUT. The functions checks, internally, + * whether the required key entries are not set to NULL. If so, the function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - The supported bit-lengths of the modulus range from 512 to 8192 in multiples of 8; + * - The length of the primes is limited to: size(p) = size(q) = 1/2 size(n); + * - It is required that d is smaller than n. + *
pInput:
+ *
The input meets the following conditions: + * - It is located in PKC RAM; + * - It is provided in little-endian byte order; + * - The input length is determined by the modulus length. + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated; + * - The result is stored in big-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_privateCRT operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_privateCRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_privateCRT( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pInput, + mcuxCl_Buffer_t pOutput +); + + +/** + * @brief No encoding operation + * + * This function is used to implement the RSASP1 primitive of PKCS #1 v2.2, i.e. signature + * generation, without prior padding. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput Pointer to input + * @param[in] inputLength RFU: please set to zero + * @param[in] pVerificationInput RFU: please set to NULL + * @param[in] pHashAlgo RFU: please set to NULL + * @param[in] pLabel RFU: please set to NULL + * @param[in] saltlabelLength RFU: please set to zero + * @param[in] keyBitLength Bit-length of modulus (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8 + * @param[in] options RFU: please set to zero + * @param[out] pOutput Pointer to buffer, which contains the result + * @param[out] pOutLength RFU: please set to NULL + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pInput:
+ *
The input meets the following conditions: + * - It is provided in big-endian byte order; + * - The input length is determined by the BYTE_LENGTH(keyBitLength). + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated in PKC RAM; + * - The result is stored in little-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_noEncode operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK The function executed successfully. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_noEncode, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_noEncode( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief No verify operation + * + * This function is used to implement the RSAVP1 primitive of PKCS #1 v2.2, i.e. signature + * a call to the public exponentiation, without padding verification and digest comparison. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput RFU: please set to NULL + * @param[in] inputLength RFU: please set to zero + * @param[in] pVerificationInput Pointer to input + * @param[in] pHashAlgo RFU: please set to NULL + * @param[in] pLabel RFU: please set to NULL + * @param[in] saltlabelLength RFU: please set to zero + * @param[in] keyBitLength Bit-length of modulus (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8 + * @param[in] options RFU: please set to zero + * @param[out] pOutput Pointer to buffer, which contains the result + * @param[out] pOutLength RFU: please set to NULL + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pVerificationInput:
+ *
The input meets the following conditions: + * - It is located in PKC RAM; + * - It is provided in little-endian byte order; + * - The input length is determined by the BYTE_LENGTH(keyBitLength). + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated; + * - The result is stored in big-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_noVerify operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK The function executed successfully. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_noVerify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_noVerify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief RSA mask generation function + * + * This function is used to implement the mask generation function MGF1 of PKCS #1 v2.2. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pHashAlgo Pointer to hash algorithm information + * @param[in] pInput Pointer to seed, of which the mask is generated + * @param[in] inputLength Length of seed, of which mask is generated + * @param[in] outputLength Length of mask to be generated + * @param[out] pOutput Pointer to result + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pHashAlgo:
+ *
Specifies the targeted hash algorithm, to be used for the mask generation function operation. + *
pInput:
+ *
The input meets the following conditions: + * - It is located in PKC RAM. + *
inputLength:
+ *
Byte-length of the seed, of which the mask is generated. + *
outputLength:
+ *
Byte-length of mask, which is generated. + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of outputLength bytes has to be allocated. + *
+ *
+ * + * @return Status of the mcuxClRsa_mgf1 operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_MGF_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_mgf1) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_mgf1( + mcuxClSession_Handle_t pSession, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pInput, + const uint32_t inputLength, + const uint32_t outputLength, + uint8_t * pOutput +); + + +/** + * @brief RSA PSS Encoding operation + * + * This function performs an RSA PSS encoding operation according to EMSA-PSS-ENCODE of PKCS #1 v2.2. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput Pointer to buffer, which contains the message or message digest to be encoded + * @param[in] inputLength Size of Input + * @param[in] pVerificationInput RFU: please set to NULL + * @param[in] pHashAlgo Pointer to hash algorithm information + * @param[in] pLabel RFU: please set to NULL + * @param[in] saltlabelLength Byte-length of salt + * @param[in] keyBitLength Bit-length of key (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8 + * @param[in] options Options field + * @param[out] pOutput Pointer to result + * @param[out] pOutLength RFU: please set to NULL + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pInput:
+ *
The input meets the following conditions: + * - It is provided in big-endian byte order. + *
inputLength:
+ *
Specifies the size of the buffer pointed to by pInput in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, + * this buffer size is specified by the targeted hash algorithm. Thus for MCUXCLRSA_OPTION_MESSAGE_DIGEST, please set inputLength to zero. + *
pHashAlgo:
+ *
Specifies the targeted hash algorithm, to be used for the mask generation function operation. + *
saltlabelLength:
+ *
Byte-length salt. + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pInput is provided as plain message (MCUXCLRSA_OPTION_MESSAGE_PLAIN) to be hashed + * internally by the mcuxClRsa_pssEncode function, or as message digest (MCUXCLRSA_OPTION_MESSAGE_DIGEST). + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated in PKC RAM; + * - The result is stored in little-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_pssEncode operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_pssEncode, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pssEncode( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief RSA PSS verification operation + * + * This function performs an RSA PSS verification operation according to EMSA-PSS-VERIFY of PKCS #1 v2.2. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput Pointer to buffer, which contains the message or message digest to be verified + * @param[in] inputLength Size of Input + * @param[in] pVerificationInput Pointer to buffer, which contains the encoded message digest to be verified + * @param[in] pHashAlgo Pointer to hash algorithm information + * @param[in] pLabel RFU: please set to NULL + * @param[in] saltlabelLength Byte-length of salt + * @param[in] keyBitLength Bit-length of key (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8. + * @param[in] options Options field + * @param[out] pOutput RFU: please set to NULL + * @param[out] pOutLength RFU: please set to NULL + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pInput:
+ *
The input meets the following conditions: + * - It is provided in big-endian byte order. + *
inputLength:
+ *
Specifies the size of the buffer pointed to by pInput in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, + * this buffer size is specified by the targeted hash algorithm. Thus for MCUXCLRSA_OPTION_MESSAGE_DIGEST, please set inputLength to zero. + *
pVerificationInput:
+ *
The padded message meets the following conditions: + * - It is located in PKC RAM; + * - It is provided in little-endian byte order. + *
pHashAlgo:
+ *
Specifies the targeted hash algorithm, to be used for the mask generation function operation. + *
saltlabelLength:
+ *
Byte-length salt. + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pInput is provided as plain message (MCUXCLRSA_OPTION_MESSAGE_PLAIN) to be hashed + * internally by the mcuxClRsa_pssVerify function, or as message digest (MCUXCLRSA_OPTION_MESSAGE_DIGEST). + * + *
+ *
+ * + * @return Status of the mcuxClRsa_pssVerify operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_VERIFY_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_VERIFY_FAILED The verification failed. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_pssVerify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pssVerify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief RSA PKCS1-v1_5 Encoding operation for signature generation + * + * This function performs an RSA PKCS1-v1_5 encoding operation according to EMSA-PKCS1-v1_5-ENCODE of PKCS #1 v2.2. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput Pointer to buffer, which contains the message or message digest to be encoded + * @param[in] inputLength Size of Input + * @param[in] pVerificationInput RFU: please set to NULL + * @param[in] pHashAlgo Pointer to hash algorithm information + * @param[in] pLabel RFU: please set to NULL + * @param[in] saltlabelLength RFU: please set to zero + * @param[in] keyBitLength Bit-length of key (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8 + * @param[in] options Options field + * @param[out] pOutput Pointer to result + * @param[out] pOutLength RFU: please set to NULL + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pInput:
+ *
The input meets the following conditions: + * - It is provided in big-endian byte order. + *
inputLength:
+ *
Specifies the size of the buffer pointed to by pInput in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, + * this buffer size is specified by the targeted hash algorithm. Thus for MCUXCLRSA_OPTION_MESSAGE_DIGEST, please set inputLength to zero. + *
pHashAlgo:
+ *
Specifies the targeted hash algorithm, to be used for the mask generation function operation. + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pInput is provided as plain message (MCUXCLRSA_OPTION_MESSAGE_PLAIN) to be hashed + * internally by the mcuxClRsa_pkcs1v15Encode_sign function, or as message digest (MCUXCLRSA_OPTION_MESSAGE_DIGEST). + *
pOutput:
+ *
The output meets the following conditions: + * - A buffer of modulus length bytes has to be allocated in PKC RAM; + * - The result is stored in little-endian byte order in the buffer pointed to by pOutput. + *
+ *
+ * + * @return Status of the mcuxClRsa_pkcs1v15Encode_sign operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_pkcs1v15Encode_sign, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pkcs1v15Encode_sign( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief RSA PKCS1-v1_5 verification operation + * + * This function performs an RSA PKCS1-v1_5 verification operation according to PKCS #1 v2.2. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pInput Pointer to buffer, which contains the message or message digest to be verified + * @param[in] inputLength Size of Input + * @param[in] pVerificationInput Pointer to buffer, which contains the encoded message digest to be verified + * @param[in] pHashAlgo Pointer to hash algorithm information + * @param[in] pLabel RFU: please set to NULL. + * @param[in] saltlabelLength RFU: please set to zero. + * @param[in] keyBitLength Bit-length of key (bit-length of encoded message). Note: This function only supports moduli, whose bit-length is a multiple of 8 + * @param[in] options Options field + * @param[out] pOutput RFU: please set to NULL + * @param[out] pOutLength RFU: please set to NULL + * + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pInput:
+ *
The input meets the following conditions: + * - It is provided in big-endian byte order. + *
inputLength:
+ *
Specifies the size of the buffer pointed to by pInput in case of option MCUXCLRSA_OPTION_MESSAGE_PLAIN. In case of option MCUXCLRSA_OPTION_MESSAGE_DIGEST, + * this buffer size is specified by the targeted hash algorithm. Thus for MCUXCLRSA_OPTION_MESSAGE_DIGEST, please set inputLength to zero. + *
pVerificationInput:
+ *
The padded message meets the following conditions: + * - It is provided in little-endian byte order. + * - It is located in PKC RAM; + *
pHashAlgo:
+ *
Specifies the targeted hash algorithm, to be used for the mask generation function operation. + *
keyBitLength:
+ *
The key bit-length meets the following conditions: + * - This function only supports moduli, whose bit-length is a multiple of 8. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pInput is provided as plain message (MCUXCLRSA_OPTION_MESSAGE_PLAIN) to be hashed + * internally by the mcuxClRsa_pkcs1v15Verify function, or as message digest (MCUXCLRSA_OPTION_MESSAGE_DIGEST). + * + *
+ *
+ * + * @return Status of the mcuxClRsa_pkcs1v15Verify operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_VERIFY_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_VERIFY_FAILED The verification failed. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_pkcs1v15Verify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pkcs1v15Verify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength +); + + +/** + * @brief Remove modulus blinding operation + * + * This function removes modulus blinding from the result of the exponentiation. + * + * @param[in] iR_iX_iNb_iB indices of PKC operands + * @param[in] iT2_iT1 indices of PKC operands + * @param[in] nbPkcByteLength length of Nb aligned to PKC word + * @param[in] bPkcByteLength length of B aligned to PKC word + * + *
+ *
Parameter properties
+ * + *
+ *
iR_iX_iNb_iB:
+ *
iB (bits 0~7): index of blinding value with size bPkcByteLength (PKC operand). + *
Its size shall be at least bPkcByteLength. + *
The most significant PKC word of B shall be nonzero. + *
iNb (bits 8~15): index of blinded modulus Nb (PKC operand). + *
Its size shall be at least nbPkcByteLength. + *
The NbDash of modulus shall be stored in the PKC word before modulus. + *
iX (bits 16~23): index of input X in Montgomery representation (PKC operand). + *
Its size shall be at least nbPkcByteLength. + *
iR (bits 16~23: index of result R in normal representation (PKC operand) + *
Its buffer size shall be at least (nbPkcByteLength - bPkcByteLength + 2 * MCUXCLRSA_PKC_WORDSIZE). + *
The result fits in size = (nbPkcByteLength - bPkcByteLength + MCUXCLRSA_PKC_WORDSIZE).
+ *
iT2_iT1:
+ *
iT1 (bits 0~7): index of temp1 (PKC operand). + *
Its buffer size shall be at least (nbPkcByteLength + MCUXCLRSA_PKC_WORDSIZE). + *
iT2 (bits 8~15): index of temp2 (PKC operand). + *
Its buffer size shall be at least MAX(nbPkcByteLength, 3 * MCUXCLRSA_PKC_WORDSIZE).
+ *
@p nbPkcByteLength
+ *
Length of modulus Nb. It shall be a multiple of MCUXCLRSA_PKC_WORDSIZE.
+ *
@p bPkcByteLength
+ *
Length of blinding value B. It shall be a multiple of MCUXCLRSA_PKC_WORDSIZE.
+ *
+ *
+ * + *
+ *
PKC properties
+ *
+ *
PS1 lengths
+ *
PS1 OPLEN = MCLEN defines operandSize = nbPkcByteLength (length of modulus Nb).
+ *
PS2 lengths
+ *
PS2 OPLEN and MCLEN will be modified, and original values will not be restored.
+ *
ACTIV/GOANY
+ *
#mcuxClPkc_WaitForReady will be called before returning to caller. + *
The PKC calculation might be still on-going, + * call #mcuxClPkc_WaitForFinish before CPU accesses to the result.
+ *
+ *
+ * + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_RemoveBlinding) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClRsa_RemoveBlinding(uint32_t iR_iX_iNb_iB, + uint16_t iT2_iT1, + uint32_t nbPkcByteLength, + uint32_t bPkcByteLength); + + + + + + + + + +/** + * @brief RSA key generation of probable prime number p or q + * + * This function performs a generation of probable prime number based on the method specified in the FIPS 186-4, Appendix B.3.3. + * The provided RNG (through the session) should be initialized (i.e., set the value of security_strength in accordance with + * the key size as specified in SP 800-57, Part 1) before this function call. + * + * The main differences in comparison to method specified in the FIPS 186-4, Appendix B.3.3: + * - Primes p and q are chosen to be congruent 3 mod 4 (this deviation has been approved). + * - Check preformed in step 4.4 and 5.5 of this method is done using only 64 most significant bits + * of sqrt(2)(2^(nlen/2)–1) rounded up, this is 0xb504f333f9de6485 (this deviation has been approved). + * - There is no check if (|p–q| <= 2((nlen/2)–100) when generating prime q (check preformed in + * step 5.4 of this method). Instead of this check shall be done after generating p and q. + * Rationale: This inequality occurs with a very small probability and it's usually treated + * as a hardware failure. As an alternative to generating new prime q number error code + * shall be returned (this deviation has been approved). + * - The pre-check against products of small primes was added before the Miller-Rabin test. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pE Pointer to data, which contains public exponent e + * @param[out] pProbablePrime Pointer to data, which contains the generated probable prime number + * @param[in] keyBitLength Bit-length of key + * + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized + * with the entropy level (security strength) in accordance with the value of keyBitLength, as specified in SP 800-57, Part 1. + *
pE:
+ *
The public exponent e meets the following conditions: + * - The public exponent e shall be FIPS 186-4 compliant; + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - Data in this buffer shall be stored in little-endian byte order; + * - The keyEntryLength shall be exact length of e (without leading zeros). + *
pProbablePrime:
+ *
Pointer to data, which contains the generated probable prime number. It meets the following conditions: + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - One additional PKC word shall be reserved before pPrimeCandidate->pKeyEntryData for the NDash calculated in the mcuxClRsa_GenerateProbablePrime + * - Probable prime number will be stored in little-endian byte order; + * - Length of the probable prime number will be keyBitLength/2. + *
keyBitLength:
+ *
Specifies the size of the generated key, it shall be even value. + *
+ *
+ * + * @return Status of the mcuxClRsa_GenerateProbablePrime operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The function executed successfully. + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED The function exceeds the limit of iterations to generate a prime. + * @retval #MCUXCLRSA_STATUS_RNG_ERROR An error occurred during random nubmer generation. + * + * @attention This function uses DRBG and PRNG (directly and indirectly) which have to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_GenerateProbablePrime) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_GenerateProbablePrime( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pPrimeCandidate, + const uint32_t keyBitLength +); + +/** + * @brief Test prime candidate for RSA key generation + * + * This function performs a test of probable prime number based on the method specified in the FIPS 186-4, Appendix B.3.3. + * + * The main differences in comparison to method specified in the FIPS 186-4, Appendix B.3.3: + * - Primes p and q are chosen to be congruent 3 mod 4 (this deviation has been approved). + * - Check preformed in step 4.4 and 5.5 of this method is done using only 64 most significant bits + * of sqrt(2)(2^(nlen/2)–1) rounded up, this is 0xb504f333f9de6485 (this deviation has been approved). + * - There is no check if |p - q| <= 2^(nlen/2 - 100) when generating prime q (check preformed in + * step 5.4 of this method). Instead of this check shall be done after generating p and q. + * Rationale: This inequality occurs with a very small probability and it's usually treated + * as a hardware failure. As an alternative to generating new prime q number error code + * shall be returned (this deviation has been approved). + * - The pre-check against products of small primes was added before the Miller-Rabin test. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pE Pointer to data, which contains public exponent e + * @param[out] pProbablePrime Pointer to data, which contains the generated probable prime number + * @param[in] keyBitLength Bit-length of key + * + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized + * with the entropy level (security strength) in accordance with the value of keyBitLength, as specified in SP 800-57, Part 1. + *
pE:
+ *
The public exponent e meets the following conditions: + * - The public exponent e shall be FIPS 186-4 compliant; + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - Data in this buffer shall be stored in little-endian byte order; + * - The keyEntryLength shall be exact length of e (without leading zeros). + *
pProbablePrime:
+ *
Pointer to data, which contains the generated probable prime number. It meets the following conditions: + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - One additional PKC word shall be reserved before pPrimeCandidate->pKeyEntryData for the NDash calculated in this function; + * - Probable prime number will be stored in little-endian byte order; + * - Length of the probable prime number will be keyBitLength/2. + *
keyBitLength:
+ *
Specifies the size of the generated key, it shall be even value. + *
iNumToCmp_iA0:
+ *
iNumToCmp: index of the buffer to store 0xb504f333f9de6485, which is 64 most significant bits of sqrt(2)(2^(nlen/2)-1) rounded up. + *
iA0: index of the buffer to store 0xC0CFD797, which is the product of the first 9 prime numbers starting from 3. + *
+ *
+ * + * @return Status of the mcuxClRsa_TestPrimeCandidate operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_CMP_FAILED prime candidate < sqrt(2)(2^((nlen/2)-1)), only 64 most significant bits are compared. + * @retval #MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDA0_FAILED prime candidate is not coprime to A0 - product of the first 9 prime numbers. + * @retval #MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDE_FAILED prime candidate - 1 is not coprime to the public exponent e. + * @retval #MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_MRT_FAILED The prime candidate did not pass the Miller-Rabin test. + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The prime candidate is probably prime. + * @retval #MCUXCLRSA_STATUS_RNG_ERROR Random number (DRBG / PRNG) error (unexpected behavior). + * + * @attention This function uses DRBG and PRNG (indirectly) which have to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_TestPrimeCandidate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_TestPrimeCandidate( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pPrimeCandidate, + const uint32_t keyBitLength, + const uint32_t iNumToCmp_iA0 +); + +/** + * @brief RSA Miller-Rabin probabilistic primality test function + * + * This function is used to test prime candidate for primality using Miller-Rabin + * probabilistic primality tests described in FIPS 186-4, Appendices C.3.1. + * + *
Assumptions:
+ * - Prime candidate is congruent 3 mod 4. Taking this into account, the Miller-Rabin + * algorithm gets simplified (due to fact that a=1 the step 4.5 is skipped); + * - The number of iterations of the Miller-Rabin test will be determined only for + * supported key length (2048, 3072 and 4096); + * - The number of iterations of the Miller-Rabin test will be determined for error + * probability 2^(-125). + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] iP_iT Pointer table indices of parameters + * @param[in] keyBitLength Bit-length of key + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized + * with the entropy level (security strength) in accordance with the value of primeLength, as specified in SP 800-57, Part 1. + *
iP_iT:
+ *
iP: index of prime candidate buffer, of which the size should be at least MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPrimeCandidate). + * Additionally one PKC word shall be reserved before P for the NDash calculated in mcuxClRsa_MillerRabinTest. + * Prime candidate length shall be keyBitLength/2. + *
iT: index of temp buffer, of which the size should be at least 9 * MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPrimeCandidate) + 10 * PKC wordsize. + *
keyBitLength:
+ *
Specifies the size of the generated key, it shall be even value. + *
+ *
+ * + * @return Status of the mcuxClRsa_MillerRabinTest operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The prime candidate is probably prime. + * @retval #MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_MRT_FAILED The prime candidate did not pass the Miller-Rabin test. + * @retval #MCUXCLRSA_STATUS_RNG_ERROR Random number (DRBG / PRNG) error (unexpected behavior) + * + * @attention This function uses DRBG and PRNG which have to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_MillerRabinTest) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_MillerRabinTest( + mcuxClSession_Handle_t pSession, + uint32_t iP_iT, + uint32_t keyBitLength +); + + +/** + * @brief RSA function which computes private exponent d compliant with FIPS 186-4 + * + * This function is used to compute private exponent d for given p, q and e. + * The d is calculated as d = e^(–1) mod (LCM(p–1, q–1)), + * where: LCM(a,b) = (ab)/gcd(a,b). + * + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pE Pointer to buffer, which contains public exponent e + * @param[in] pP Pointer to buffer, which contains prime p + * @param[in] pQ Pointer to buffer, which contains prime q + * @param[out] pD Pointer to buffer, which contains the computed private exponent d + * @param[in] keyBitLength Bit-length of key + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pE:
+ *
The public exponent e meets the following conditions: + * - The public exponent e shall be FIPS 186-4 compliant; + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - Data in this buffer shall be stored in little-endian byte order; + * - The keyEntryLength shall be exact length of e (without leading zeros). + *
pP:
+ *
The prime p meets the following conditions: + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - Data in this buffer shall be stored in little-endian byte order; + * - Prime p length shall be keyBitLength/2. + *
pQ:
+ *
The prime q meets the following conditions: + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * - Data in this buffer shall be stored in little-endian byte order; + * - Prime q length shall be keyBitLength/2. + *
pD:
+ *
The private exponent d meets the following conditions: + * - A buffer pointed by pKeyEntryData shall be located in PKC RAM, its address and length shall be aligned to FAME word; + * Size of the buffer should be at least keyBitLength/8 + PKC wordsize. + * - Data in this buffer shall be stored in little-endian byte order; + * - The private exponent d length is not greater than keyBitLength. + *
keyBitLength:
+ *
Specifies the size of the generated key, it shall be even value. + *
+ *
+ * + * @return Status of the mcuxClRsa_ComputeD operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The prime candidate is probably prime. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT For a given input (it means p, q and e) the computed D does not meet + * the requirements specified in the FIPS 186-4, Appendix B.3.1. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_ComputeD) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_ComputeD( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pP, + mcuxClRsa_KeyEntry_t * pQ, + mcuxClRsa_KeyEntry_t * pD, + const uint32_t keyBitLength +); + +/** + * @brief RSA function which test if |p–q| <= 2^(nlen/2–100). + * + * This function is used to test if |p–q| <= 2^(nlen/2–100). + * This is a verification required by FIPS 186-4 (Appendix B.3.3, step 5.4). + * + * @param[in] iP_iQ_iT1 Pointer table indices of parameters + * @param[in] primeByteLength Bytelength of parameters p and q + * + *
+ *
Parameter properties
+ * + *
+ *
iP_iQ_iT1:
+ *
iP: index of p prime buffer. The size shall be a multiple of PKC word and at least primeByteLength. + *
iQ: index of q prime buffer. The size shall be a multiple of PKC word and at least primeByteLength. + *
iT: index of temporary buffer. The size shall be at least 2 * MCUXCLRSA_PKC_ROUNDUP_SIZE(16). + *
primeByteLength:
+ *
The length of primes p and q. It must be a multiple of the PKC word. + *
+ *
+ * + * @return Status of the mcuxClRsa_TestPQDistance operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The p and q primes meet the FIPS requirements. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The p and q primes pass this test, it means does not meet the FIPS requirements. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_TestPQDistance) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_TestPQDistance(uint32_t iP_iQ_iT, uint32_t primeByteLength); + + +/** + * @brief RSA function which calculates modular inversion, X^(-1) mod N + * + * @param[in] iR_iX_iN_iT Pointer table indices of parameters + * + *
Assumptions:
+ * - If X and N are not coprime, the result will be incorrect. + * - The N shall be congruent 2 mod 4 + * - Both ps1 (OP)LEN and MCLEN need to be initialized (MCLEN = OPLEN = operandSize). + * - The size of X must be <= operandSize + * - The offsets (UPTRT[iR] and UPTRT[iT]) must be initialized properly (equal to a multiple of PKC wordsize). + * - The PKC calculation might be still on-going, call #mcuxClPkc_WaitForFinish before CPU accesses to the result. + * + *
+ *
Parameter properties
+ * + *
+ *
iR_iX_iN_iT:
+ *
iR: index of result buffer, of which the size should be at least operandSize + PKC wordsize. + *
iX: index of X buffer, of which the content (X) will be destroyed. + *
iN: index of modulus buffer, of which the content (N) will be destroyed. One PKC word shall be reserved before N, + * for the NDash calculated in mcuxClRsa_ModInv. + *
iT: index of temp buffer, of which the size should be at least operandSize + PKC wordsize. + *
+ *
+ * + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_ModInv) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClRsa_ModInv(uint32_t iR_iX_iN_iT); + + +/** + * @brief RSA function which verifies whether RSA public exponent is FIPS compliant (i.e., is odd value + * in the range 2^16 < e < 2^256) and determines its length without leading zeros. + * + * @param[in] pE Pointer to buffer, which contains public exponent e + * @param[out] exactLength Pointer to data were the exact length of public exponent e will be set + * + *
+ *
Parameter properties
+ * + *
+ *
pE:
+ *
The public exponent e in a big endian order + *
exactLength:
+ *
Exact length of public exponent e + *
+ *
+ * + * @return Status of the mcuxClRsa_VerifyE operation (see @ref mcuxClRsa_Status_Protected_t) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK The prime candidate is probably prime. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The public exponent e does not meet the requirements + * specified in the FIPS 186-4, Appendix B.3.1. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_VerifyE) +mcuxClRsa_Status_Protected_t mcuxClRsa_VerifyE(mcuxClRsa_KeyEntry_t *pE, uint32_t *exactLength); + + + +/** + * @} + */ /* mcuxClRsa_Internal_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_FUNCTIONS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Macros.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Macros.h new file mode 100644 index 000000000..4426d3060 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Macros.h @@ -0,0 +1,95 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Internal_Macros.h + * @brief Internal macros of the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_INTERNAL_MACROS_H_ +#define MCUXCLRSA_INTERNAL_MACROS_H_ + +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup MCUXCLRSA_INTERNAL_DEFINES_ MCUXCLRSA_INTERNAL_DEFINES_ + * @brief Internal macros of the mcuxClRsa component. + * @ingroup mcuxClRsa_Internal_Defines + * @{ + */ +#define MCUXCLRSA_PSS_PADDING1_LEN (8u) + ///< Define for the PSS padding1 length. + +#define MCUXCLRSA_HASH_MAX_SIZE (64u) + ///< Defines the maximum sizes of the hash algorithms + +#define MCUXCLRSA_MAX_MODLEN (512u) +/** @} */ + + +/** + * @defgroup MCUXCLRSA_INTERNAL_MACROS_ MCUXCLRSA_INTERNAL_MACROS_ + * @brief Internal macros of the mcuxClRsa component. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_MAX(value0, value1) \ + ((value0) > (value1) ? (value0) : (value1)) + ///< Macro computing the maximum value of value0 and value1. + +#define MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(size) \ + ((((size) + sizeof(uint32_t) - 1U ) / (sizeof(uint32_t))) * (sizeof(uint32_t))) + ///< Round up a size (in bytes) to a multiple of the CPU wordsize (4 bytes). + +#define MCUXCLRSA_CALC_MODLEN_FROM_CRTKEY(pKey, keyBitLength) \ + do { \ + uint32_t pBitLength = ((pKey)->pMod1->keyEntryLength - 1u) * 8u; /* Lengths without first byte */ \ + uint32_t qBitLength = ((pKey)->pMod2->keyEntryLength - 1u) * 8u; \ + uint8_t tmpByte = (uint8_t) (pKey)->pMod1->pKeyEntryData[0]; \ + while (tmpByte != 0u) /* Iterate through first byte of p and add to bit length */ \ + { \ + ++pBitLength; \ + tmpByte = (uint8_t) (tmpByte >> 1u); \ + } \ + tmpByte = (uint8_t) (pKey)->pMod2->pKeyEntryData[0]; \ + while (tmpByte != 0u) /* Iterate through first byte of q and add to bit length */ \ + { \ + ++qBitLength; \ + tmpByte = (uint8_t) (tmpByte >> 1u); \ + } \ + (keyBitLength) = (pBitLength + qBitLength); \ + } while(false) + ///< Obtain bit-length of modulus by counting leading zeroes of P and Q (CRT key). + ///< Note that the most significant byte of P and Q should be non-zero. + +#define MCUXCLRSA_GET_MINIMUM_SECURITY_STRENGTH(keyBitLength) \ + (((keyBitLength) <= 2048u) ? 112u : \ + (((keyBitLength) <= 3072u) ? 128u : \ + 152u)) ///< Macro to determine the minimal security strength that + ///< needs to be provided by the RNG for RSA keys with + ///< lengths from 2048 bits to 4096 bits. + ///< Numbers taken from NIST SP 800-56B REV. 2, Table 2 + +/** @} */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_MACROS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_MemoryConsumption.h new file mode 100644 index 000000000..05bf843b2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_MemoryConsumption.h @@ -0,0 +1,690 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Internal_MemoryConsumption.h + * @brief Internal memory consumption definitions of the mcuxClRsa component */ + +#ifndef MCUXCLRSA_INTERNAL_MEMORY_CONSUMPTION_H_ +#define MCUXCLRSA_INTERNAL_MEMORY_CONSUMPTION_H_ + +#include // Exported features flags header +#include +#include +#include + +#include +#include +#include + + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_privatePlain function. */ +/****************************************************************************/ +#define MCUXCLRSA_INTERNAL_PRIVATEPLAIN_BLINDING_SIZE (4UL) + +/** + * @defgroup MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WA MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WA + * @brief Workarea size macros of mcuxClRsa_privatePlain. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) + 2U * MCUXCLRSA_PKC_WORDSIZE) + ///< Size of the input buffer for mcuxClRsa_privatePlain, that is allocated in PKC RAM. + +#define MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WACPU_SIZE(keyByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_PRIVPLAIN_UPTRT_SIZE * sizeof(uint16_t))) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(keyByteLength)) + ///< Definition of CPU workarea size for the mcuxClRsa_privatePlain function depending on the key byte-length. + ///< Internally, it depends on the byte-length of the exponent, and it is rounded up here, based on the fact that d < n. + +#define MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WAPKC_SIZE(keyByteLength) \ + (6U * (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) + MCUXCLRSA_PKC_ROUNDUP_SIZE(MCUXCLRSA_INTERNAL_PRIVATEPLAIN_BLINDING_SIZE)) + 12U * MCUXCLRSA_PKC_WORDSIZE \ + + MCUXCLRSA_PKC_ROUNDUP_SIZE(MCUXCLRSA_INTERNAL_PRIVATEPLAIN_BLINDING_SIZE)) + ///< Definition of PKC workarea size for the mcuxClRsa_privatePlain function depending on the key byte-length. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_privateCRT function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PRIVATECRT_WA MCUXCLRSA_INTERNAL_PRIVATECRT_WA + * @brief Workarea size macros of mcuxClRsa_privateCRT. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PRIVATECRT_BLINDING_SIZE (4UL) + +#define MCUXCLRSA_INTERNAL_PRIVATECRT_WACPU_SIZE(primeByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_PRIVCRT_UPTRT_SIZE * sizeof(uint16_t))) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(primeByteLength)) + ///< Definition of CPU workarea size for the mcuxClRsa_privateCRT function depending on the byte-length of p (equal to the byte-length of q). + ///< Internally, it depends on the byte-lengths of the exponents dp and dq, and it is rounded up here, based on the fact that dp and dq are smaller than p and q. + +#define MCUXCLRSA_INTERNAL_PRIVATECRT_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(MCUXCLRSA_INTERNAL_PRIVATECRT_BLINDING_SIZE) \ + + MCUXCLRSA_MAX((8U * MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength)) + (8U * MCUXCLRSA_PKC_ROUNDUP_SIZE(MCUXCLRSA_INTERNAL_PRIVATECRT_BLINDING_SIZE)) + (14U * MCUXCLRSA_PKC_WORDSIZE), \ + (6U * MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength * 2u)) + (8U * MCUXCLRSA_PKC_WORDSIZE))) + ///< Definition of PKC workarea size for the mcuxClRsa_privateCRT function depending on the byte-length of p. +/** @} */ + + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_public function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PUBLIC_WA MCUXCLRSA_INTERNAL_PUBLIC_WA + * @brief Workarea size macros of mcuxClRsa_public. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PUBLIC_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_PUBLIC_UPTRT_SIZE * sizeof(uint16_t)))) + ///< Definition of CPU workarea size for the mcuxClRsa_public function. + +#define MCUXCLRSA_INTERNAL_PUBLIC_WAPKC_SIZE(keyByteLength) \ + (5U * MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) + 4U * MCUXCLRSA_PKC_WORDSIZE) + ///< Definition of PKC workarea size for the mcuxClRsa_public function depending on the key byte-length. +/** @} */ + + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_noEncode function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_NOENCODE_WA MCUXCLRSA_INTERNAL_NOENCODE_WA + * @brief Workarea size macros of mcuxClRsa_noEncode. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_NOENCODE_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_NOENCODE_UPTRT_SIZE * sizeof(uint16_t)))) + ///< Definition of CPU workarea size for the mcuxClRsa_noEncode function. + +#define MCUXCLRSA_INTERNAL_NOENCODE_WAPKC_SIZE \ + 0u + ///< Definition of PKC workarea size for the mcuxClRsa_noEncode function. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_noVerify function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_NOVERIFY_WA MCUXCLRSA_INTERNAL_NOVERIFY_WA + * @brief Workarea size macros of mcuxClRsa_noVerify. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_NOVERIFY_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_NOVERIFY_UPTRT_SIZE * sizeof(uint16_t)))) + ///< Definition of CPU workarea size for the mcuxClRsa_noVerify function. + +#define MCUXCLRSA_INTERNAL_NOVERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_noVerify function depending on the key byte-length. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_Mgf1 function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_MGF1_WA MCUXCLRSA_INTERNAL_MGF1_WA + * @brief Workarea size macros of mcuxClRsa_Mgf1. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_MGF1_WACPU_SIZE \ + (MCUXCLHASH_INTERNAL_WACPU_MAX) + ///< Definition of CPU workarea size for the mcuxClRsa_Mgf1 function. + +#define MCUXCLRSA_INTERNAL_MGF1_WAPKC_SIZE(inputLen, hashLen) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE((inputLen) + 4U + (hashLen))) + ///< Definition of PKC workarea size for the mcuxClRsa_Mgf1 function. + +/* + * Definitions of maximum size of PKC workarea for the mcuxClRsa_Mgf1 function + * for PSSENCODE and PSSVERIFY. + * This function allocate space for Input, Hash output and 4B of the counter. + * This macro takes into account the fact that: + * inputLength = hashLen <= MCUXCLRSA_HASH_MAX_SIZE + */ + #define MCUXCLRSA_INTERNAL_PSS_MGF1_MAX_WAPKC_SIZE \ + (MCUXCLRSA_INTERNAL_MGF1_WAPKC_SIZE(MCUXCLRSA_HASH_MAX_SIZE, MCUXCLRSA_HASH_MAX_SIZE)) + ///< Definition of PKC workarea size for the mcuxClRsa_Mgf1 function. + +/* + * Definitions of maximum size of PKC workarea for the mcuxClRsa_Mgf1 function + * for OAEPENCODE and OAEPDECODE. + * This function allocate space for Input, Hash output and 4B of the counter. + * This macro takes into account the fact that: + * a. inputLength = keyByteLength - hLen - 1 or inputLength = hLen + * b. keyByteLength >= mLen + 2*hLen + 2 which means, that keyByteLength - hLen - 1 >= mLen + hLen + 1 > hLen + */ + #define MCUXCLRSA_INTERNAL_OAEP_MGF1_MAX_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength + 3u)) + + ///< Definition of PKC workarea size for the mcuxClRsa_Mgf1 function. + +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pssEncode function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PSSENCODE_WA MCUXCLRSA_INTERNAL_PSSENCODE_WA + * @brief Workarea size macros of mcuxClRsa_pssEncode. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(((keyByteLength) - 2U) + MCUXCLRSA_PSS_PADDING1_LEN)) + ///< Maximum size for the temp buffer in mcuxClRsa_pssEncode, based on the fact that emLen >= hLen + sLen + 2. + +#define MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WACPU_SIZE \ + MCUXCLRSA_MAX(MCUXCLHASH_INTERNAL_WACPU_MAX, MCUXCLRSA_INTERNAL_MGF1_WACPU_SIZE) + ///< Definitions of maximum size of CPU workarea for the mcuxClRsa_pssEncode function. + +#define MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + + MCUXCLRSA_INTERNAL_PSS_MGF1_MAX_WAPKC_SIZE) + ///< Definitions of maximum size of PKC workarea for the mcuxClRsa_pssEncode function. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pssVerify function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PSSVERIFY_WA MCUXCLRSA_INTERNAL_PSSVERIFY_WA + * @brief Workarea size macros of mcuxClRsa_pssVerify. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WACPU_SIZE \ + (MCUXCLRSA_MAX(MCUXCLHASH_INTERNAL_WACPU_MAX, MCUXCLRSA_INTERNAL_MGF1_WACPU_SIZE)) + ///< Definition of CPU workarea size for the mcuxClRsa_pssVerify function. + +/* + * Definitions of maximum size of PKC workarea for the mcuxClRsa_pssVerify function without workarea size for MGF1 function. + * This macro specifies the size of the space allocated for Hash (size hLen), salt (sLen) and padding1. + * It takes into account the condition that emLen >= hLen + sLen + 2 => hLen + sLen <= emLen - 2, + * where emLen = keyByteLength (only byte-level granularity of keys is supported, thus keyBitLength is a multiple of 8). + * Having sLen rounding up to CPU word additionally 3B must be added. + */ +#define MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE((((keyByteLength) - 2U /* hLen + sLen */ + 3U /* round up sLen to CPU word */) + MCUXCLRSA_PSS_PADDING1_LEN) \ + + ((keyByteLength) - 1U) /* maskedDB + H' */)) + ///< Definitions of maximum size of PKC workarea for the mcuxClRsa_pssVerify function without workarea size for MGF1 function. + +#define MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + + MCUXCLRSA_INTERNAL_PSS_MGF1_MAX_WAPKC_SIZE) \ + ///< Definitions of maximum size of PKC workarea for the mcuxClRsa_pssVerify function. + +/** @} */ + +/*********************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pkcs1v15Encode_sign function. */ +/*********************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WA MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WA + * @brief Workarea size macros of mcuxClRsa_pkcs1v15Encode_sign. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WACPU_SIZE \ + MCUXCLHASH_INTERNAL_WACPU_MAX + ///< Definition of CPU workarea size for the mcuxClRsa_pkcs1v15Encode_sign function. + +#define MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_pkcs1v15Encode_sign function. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pkcs1v15Verify function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WA MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WA + * @brief Workarea size macros of mcuxClRsa_pkcs1v15Verify. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WACPU_SIZE \ + MCUXCLHASH_INTERNAL_WACPU_MAX + ///< Definition of CPU workarea size for the mcuxClRsa_pkcs1v15Verify function. + +#define MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)) + \ + MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WAPKC_SIZE(keyByteLength) + ///< Definition of PKC workarea size for the mcuxClRsa_pkcs1v15Verify function. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_oaepEncode function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_OAEPENCODE_WA MCUXCLRSA_INTERNAL_OAEPENCODE_WA + * @brief Workarea size macros of mcuxClRsa_oaepEncode. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_OAEPENCODE_WACPU_SIZE \ + MCUXCLRSA_MAX(MCUXCLHASH_INTERNAL_WACPU_MAX, MCUXCLRSA_INTERNAL_MGF1_WACPU_SIZE) + ///< Definition of CPU workarea size for the mcuxClRsa_oaepEncode function. + +#define MCUXCLRSA_INTERNAL_OAEPENCODE_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + (2u * MCUXCLRSA_PKC_ROUNDUP_SIZE((keyByteLength)-1u)) + ///< Definition of PKC workarea size for the mcuxClRsa_oaepEncode function, without taking into account the PKC WA usage of the MGF1 + +#define MCUXCLRSA_INTERNAL_OAEPENCODE_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_OAEPENCODE_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + + MCUXCLRSA_INTERNAL_OAEP_MGF1_MAX_WAPKC_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_oaepEncode function. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_oaepDecode function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_OAEPDECODE_WA MCUXCLRSA_INTERNAL_OAEPDECODE_WA + * @brief Workarea size macros of mcuxClRsa_oaepDecode. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_OAEPDECODE_WACPU_SIZE \ + MCUXCLRSA_MAX(MCUXCLHASH_INTERNAL_WACPU_MAX, MCUXCLRSA_INTERNAL_MGF1_WACPU_SIZE) + ///< Definition of CPU workarea size for the mcuxClRsa_oaepDecode function. + +#define MCUXCLRSA_INTERNAL_OAEPDECODE_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_oaepDecode function, without taking into account the PKC WA usage of the MGF1 + +#define MCUXCLRSA_INTERNAL_OAEPDECODE_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_OAEPDECODE_WAPKC_SIZE_WO_MGF1(keyByteLength) \ + + MCUXCLRSA_INTERNAL_OAEP_MGF1_MAX_WAPKC_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_oaepDecode function. +/** @} */ + +/****************************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pkcs1v15Encode_encrypt function. */ +/****************************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_ENCRYPT_WA MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_ENCRYPT_WA + * @brief Workarea size macros of mcuxClRsa_pkcs1v15Encode_encrypt. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_ENCRYPT_WACPU_SIZE (0u) + ///< Definition of CPU workarea size for the mcuxClRsa_pkcs1v15Encode_encrypt function. + +#define MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_ENCRYPT_WAPKC_SIZE (0u) + ///< Definition of PKC workarea size for the mcuxClRsa_pkcs1v15Encode_encrypt function. +/** @} */ + +/****************************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_pkcs1v15Decode_decrypt function. */ +/****************************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_PKCS1V15DECODE_DECRYPT_WA MCUXCLRSA_INTERNAL_PKCS1V15DECODE_DECRYPT_WA + * @brief Workarea size macros of mcuxClRsa_pkcs1v15Decode_decrypt. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_PKCS1V15DECODE_DECRYPT_WACPU_SIZE (0u) + ///< Definition of CPU workarea size for the mcuxClRsa_pkcs1v15Decode_decrypt function. + +#define MCUXCLRSA_INTERNAL_PKCS1V15DECODE_DECRYPT_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_pkcs1v15Decode_decrypt function. +/** @} */ + + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_verify function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_VERIFY_WA MCUXCLRSA_VERIFY_WA + * @brief Workarea size macros of mcuxClRsa_verify. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_SIZEOF_PKCSTATEBACKUP (sizeof(mcuxClPkc_State_t)) + +#define MCUXCLRSA_INTERNAL_VERIFY_NOVERIFY_WACPU_SIZE \ + (MCUXCLRSA_INTERNAL_SIZEOF_PKCSTATEBACKUP \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_NOVERIFY_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PUBLIC_WACPU_SIZE)) + ///< Definition of CPU workarea size for the mcuxClRsa_verify function using NOVERIFY option. + +#define MCUXCLRSA_INTERNAL_VERIFY_PKCS1V15VERIFY_WACPU_SIZE \ + (MCUXCLRSA_INTERNAL_SIZEOF_PKCSTATEBACKUP \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PUBLIC_WACPU_SIZE)) + ///< Definition of CPU workarea size for the mcuxClRsa_verify function using PKCS1V15VERIFY option. + + +#define MCUXCLRSA_INTERNAL_VERIFY_PSSVERIFY_WACPU_SIZE \ + (MCUXCLRSA_INTERNAL_SIZEOF_PKCSTATEBACKUP \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PUBLIC_WACPU_SIZE)) + ///< Definition of CPU workarea size for the mcuxClRsa_verify function using PSSVERIFY option. + +#define MCUXCLRSA_INTERNAL_VERIFY_NOVERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PUBLIC_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_NOVERIFY_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Verify function using NOVERIFY option depending on the key byte-length. + +#define MCUXCLRSA_INTERNAL_VERIFY_PKCS1V15VERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PUBLIC_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_PKCS1V15VERIFY_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Verify function using PKCS1V15VERIFY option depending on the key byte-length. + +#define MCUXCLRSA_INTERNAL_VERIFY_PSSVERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PUBLIC_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Verify function using PSSVERIFY option. + +#define MCUXCLRSA_INTERNAL_VERIFY_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_MAX(MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_VERIFY_PKCS1V15VERIFY_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_VERIFY_PSSVERIFY_WAPKC_SIZE(keyByteLength)), \ + MCUXCLRSA_INTERNAL_VERIFY_NOVERIFY_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Verify function depending on the key byte-length. + + +/** @} */ + + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_sign function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_SIGN_WA MCUXCLRSA_SIGN_WA + * @brief Workarea size macros of mcuxClRsa_sign. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_NOENCODE_WACPU_SIZE(keyByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_NOENCODE_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WACPU_SIZE(keyByteLength))) + ///< Definition of CPU workarea size for the mcuxClRsa_sign function using NOENCODE option and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE(keyByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WACPU_SIZE(keyByteLength))) + ///< Definition of CPU workarea size for the mcuxClRsa_sign function with pkcs1v15 encoding and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_PSSENCODE_WACPU_SIZE(keyByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WACPU_SIZE(keyByteLength))) + ///< Definitions of CPU workarea size for the mcuxClRsa_sign function with pss encoding and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_NOENCODE_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_NOENCODE_WAPKC_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Sign function using NOENCODE option and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_PSSENCODE_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function with pss encoding and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_PKCS1V15ENCODE_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function with pkcs1v15 encoding and a private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_PLAIN_WAPKC_SIZE(keyByteLength) \ + (MCUXCLRSA_MAX(MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_SIGN_PLAIN_PKCS1V15ENCODE_WAPKC_SIZE(keyByteLength), \ + MCUXCLRSA_INTERNAL_SIGN_PLAIN_PSSENCODE_WAPKC_SIZE(keyByteLength)), \ + MCUXCLRSA_INTERNAL_SIGN_PLAIN_NOENCODE_WAPKC_SIZE(keyByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function keyByteLength private plain key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_NOENCODE_WACPU_SIZE(primeByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_NOENCODE_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATECRT_WACPU_SIZE(primeByteLength))) + ///< Definition of CPU workarea size for the mcuxClRsa_sign function using NOENCODE option and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE(primeByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATECRT_WACPU_SIZE(primeByteLength))) + ///< Definition of CPU workarea size for the mcuxClRsa_sign function with pkcs1v15 encoding and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_PSSENCODE_WACPU_SIZE(primeByteLength) \ + (sizeof(mcuxClPkc_State_t) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WACPU_SIZE, \ + MCUXCLRSA_INTERNAL_PRIVATECRT_WACPU_SIZE(primeByteLength))) + ///< Definitions of CPU workarea size for the mcuxClRsa_sign function with pss encoding and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_NOENCODE_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(2u * primeByteLength) + \ + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_NOENCODE_WAPKC_SIZE, MCUXCLRSA_INTERNAL_PRIVATECRT_WAPKC_SIZE(primeByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_Sign function using NOENCODE option and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_PSSENCODE_WAPKC_SIZE(primeByteLength) \ + ((MCUXCLRSA_PKC_ROUNDUP_SIZE(2u * primeByteLength) + \ + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE(2u * primeByteLength), MCUXCLRSA_INTERNAL_PRIVATECRT_WAPKC_SIZE(primeByteLength)))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function with pss encoding and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_PKCS1V15ENCODE_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(2u * primeByteLength) + \ + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_PKCS1V15ENCODE_SIGN_WAPKC_SIZE(2u * primeByteLength), MCUXCLRSA_INTERNAL_PRIVATECRT_WAPKC_SIZE(primeByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function with pkcs1v15 encoding and a private CRT key. + +#define MCUXCLRSA_INTERNAL_SIGN_CRT_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_MAX(MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_SIGN_CRT_PKCS1V15ENCODE_WAPKC_SIZE(primeByteLength), \ + MCUXCLRSA_INTERNAL_SIGN_CRT_PSSENCODE_WAPKC_SIZE(primeByteLength)), \ + MCUXCLRSA_INTERNAL_SIGN_CRT_NOENCODE_WAPKC_SIZE(primeByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_sign function keyByteLength CRT key. + +/** @} */ + + + +/*****************************************************************************************/ +/* Definitions of workarea size for the mcuxClRsa_MillerRabinTest function. */ +/*****************************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_MILLERRABINTEST_WA MCUXCLRSA_INTERNAL_MILLERRABINTEST_WA + * @brief Workarea size macros of mcuxClRsa_MillerRabinTest + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#define MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE_WO_RNG(primeByteLength) \ + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(primeByteLength) +///< Definition of CPU workarea size for the mcuxClRsa_MillerRabinTest function depending on the byte-length of primeByteLength. +#else +//The parameters are just to keep the API consistent +#define MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE_WO_RNG(primeByteLength) \ + (0u) +///< Definition of CPU workarea size for the mcuxClRsa_MillerRabinTest function depending on the byte-length of primeByteLength. +#endif + +#define MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE(primeByteLength) \ + (MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE_WO_RNG(primeByteLength) + MCUXCLRANDOMMODES_CPUWA_MAXSIZE) + +#define MCUXCLRSA_INTERNAL_MILLERRABINTEST_T_BUFFER_SIZE(primeByteLength) \ + (9u * MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength) + 11u * MCUXCLRSA_PKC_WORDSIZE) + ///< Definition of PKC workarea size for the mcuxClRsa_MillerRabinTest function depending on the byte-length of primeByteLength. +/** @} */ + +/*****************************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_TestPrimeCandidate function. */ +/*****************************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WA MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WA + * @brief Workarea size macros of mcuxClRsa_TestPrimeCandidate + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WACPU_SIZE_WO_MILLERRABIN \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_TESTPRIME_UPTRT_SIZE * sizeof(uint16_t)))) +///< Definition of CPU workarea size for the mcuxClRsa_TestPrimeCandidate function depending on the byte-length of primeByteLength without mcuxClRsa_MillerRabinTest + +#define MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WACPU_SIZE(primeByteLength) \ + ((MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WACPU_SIZE_WO_MILLERRABIN) \ + + MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE(primeByteLength)) + +#define MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_MAX(2u * MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength), \ + MCUXCLRSA_INTERNAL_MILLERRABINTEST_T_BUFFER_SIZE(primeByteLength))) + ///< Definition of PKC workarea size for the mcuxClRsa_TestPrimeCandidate function depending on the byte-length of primeByteLength. +/** @} */ + +/*****************************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_GenerateProbablePrime function. */ +/*****************************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WA MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WA + * @brief Workarea size macros of mcuxClRsa_GenerateProbablePrime + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#ifndef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +//The parameters are just to keep the API consistent +#define MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE_WO_TESTPRIME_AND_MILLERRABIN(primeByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_GENPRIME_UPTRT_SIZE * sizeof(uint16_t)))) + ///< Definition of CPU workarea size for the mcuxClRsa_GenerateProbablePrime function depending on the byte-length of primeByteLength without mcuxClRsa_TestPrimeCandidate and mcuxClRsa_MillerRabinTest +#else +#define MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE_WO_TESTPRIME_AND_MILLERRABIN(primeByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_GENPRIME_UPTRT_SIZE * sizeof(uint16_t))) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(primeByteLength)) + ///< Definition of CPU workarea size for the mcuxClRsa_GenerateProbablePrime function depending on the byte-length of primeByteLength without mcuxClRsa_TestPrimeCandidate and mcuxClRsa_MillerRabinTest +#endif + +#define MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE(primeByteLength) \ + (MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE_WO_TESTPRIME_AND_MILLERRABIN(primeByteLength) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WACPU_SIZE(primeByteLength), \ + MCUXCLRANDOMMODES_CPUWA_MAXSIZE)) + ///< Definition of CPU workarea size for the mcuxClRsa_GenerateProbablePrime function depending on the byte-length of primeByteLength. + + +#define MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WAPKC_SIZE(primeByteLength) \ + ((2u * MCUXCLRSA_PKC_WORDSIZE) \ + + MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WAPKC_SIZE(primeByteLength)) + ///< Definition of PKC workarea size for the mcuxClRsa_GenerateProbablePrime function depending on the byte-length of primeByteLength. +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_ComputeD function. */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_COMPD_WA MCUXCLRSA_COMPD_WA + * @brief Workarea size macros of mcuxClRsa_ComputeD + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_COMPUTED_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_COMPD_UPTRT_SIZE * sizeof(uint16_t)))) + +#define MCUXCLRSA_INTERNAL_COMPUTED_WAPKC_SIZE(primeByteLength) \ + ((2u * (MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength))) \ + + (3u * MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength * 2u)) + (2u * MCUXCLRSA_PKC_WORDSIZE)) + ///< Definition of PKC workarea size for the mcuxClRsa_ComputeD function depending on the byte-length of p. +/** @} */ + +/*************************************************************************************************************************/ +/* Definitions of generated key data size for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. */ +/*************************************************************************************************************************/ +#ifndef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#define MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_UPTRT_SIZE * sizeof(uint16_t))) \ + + MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE(0)) +#else +#define MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_WACPU_SIZE(primeByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_UPTRT_SIZE * sizeof(uint16_t))) \ + + MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE(primeByteLength)) +#endif + +#define MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_WAPKC_SIZE(primeByteLength) \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength) \ + + (2u * (MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength) + MCUXCLRSA_PKC_WORDSIZE)) \ + + MCUXCLRSA_MAX(MCUXCLRSA_MAX(MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength * 2u) + 3u * ((MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength) + MCUXCLRSA_PKC_WORDSIZE)) , \ + (6u * (MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength) + MCUXCLRSA_PKC_WORDSIZE) + MCUXCLRSA_PKC_WORDSIZE)), \ + MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WAPKC_SIZE(primeByteLength))) + +#ifndef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_WACPU_SIZE \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_UPTRT_SIZE * sizeof(uint16_t)) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE(0), MCUXCLRSA_INTERNAL_COMPUTED_WACPU_SIZE)) +#else +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_WACPU_SIZE(primeByteLength) \ + (MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) \ + + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_UPTRT_SIZE * sizeof(uint16_t)) \ + + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE(primeByteLength), MCUXCLRSA_INTERNAL_COMPUTED_WACPU_SIZE)) +#endif + +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_WAPKC_SIZE(keyByteLength) \ + ((2u * (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength / 2u) + MCUXCLRSA_PKC_WORDSIZE)) \ + + MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) \ + + MCUXCLRSA_MAX((2u * MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength)), /* D and N */ \ + MCUXCLRSA_MAX(MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WAPKC_SIZE(keyByteLength / 2u), \ + (MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) + MCUXCLRSA_PKC_WORDSIZE) /* D + FW */ \ + + MCUXCLRSA_INTERNAL_COMPUTED_WAPKC_SIZE(keyByteLength / 2u)))) + +/** + * @defgroup MCUXCLRSA_INTERNAL_KEYGENERATION_KEY_DATA_SIZE MCUXCLRSA_INTERNAL_KEYGENERATION_KEY_DATA_SIZE + * @brief Definitions of bufer sizes for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ + +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_KEY_DATA_SIZE(keyByteLength) \ + (sizeof(mcuxClRsa_Key) + (2u * (sizeof(mcuxClRsa_KeyEntry_t) + keyByteLength))) + ///< Definition of buffer size for the key generation functions for private plain key (key type and key entries followed by the key data, i.e.: n, d). + +#define MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_KEY_DATA_SIZE(keyByteLength) \ + (sizeof(mcuxClRsa_Key) + (5U * (sizeof(mcuxClRsa_KeyEntry_t) + ((keyByteLength + 1u) / 2u)))) + ///< Definition of buffer size for the key generation functions for private CRT key (key type and key entries followed by the key data, i.e.: p, q, qInv, dp, dq). + +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PUBLIC_KEY_DATA_SIZE(keyByteLength) \ + (sizeof(mcuxClRsa_Key) + (2u * (sizeof(mcuxClRsa_KeyEntry_t) + keyByteLength))) + ///< Definition of buffer size for the key generation functions for public key (key type and key entries followed by the key data, i.e.: n, e). + + +/** @} */ + + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_MEMORY_CONSUMPTION_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcDefs.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcDefs.h new file mode 100644 index 000000000..58c1ac22f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcDefs.h @@ -0,0 +1,303 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Internal_PkcDefs.h + * @brief Internal definitions of the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_INTERNAL_PKCDEFS_H_ +#define MCUXCLRSA_INTERNAL_PKCDEFS_H_ + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_public */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_ MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_ + * @brief UPTR table defines for function mcuxClRsa_public. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X (0u) ///< UPTR table index for buffer x +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R (1u) ///< UPTR table index for buffer r +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N (2u) ///< UPTR table index for buffer n +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1 (3u) ///< UPTR table index for buffer t1 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2 (4u) ///< UPTR table index for buffer t2 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_OUTPUT (5u) ///< UPTR table index for buffer output +#define MCUXCLRSA_INTERNAL_PUBLIC_UPTRT_SIZE (6u) ///< UPTR table size of function mcuxClRsa_public +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_privatePlain */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_ MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_ + * @brief UPTR table defines for function mcuxClRsa_privatePlain. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X (0u) ///< UPTR table index for buffer x +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R (1u) ///< UPTR table index for buffer r +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N (2u) ///< UPTR table index for buffer n +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0 (3u) ///< UPTR table index for buffer t0 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T1 (4u) ///< UPTR table index for buffer t1 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2 (5u) ///< UPTR table index for buffer t2 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T3 (6u) ///< UPTR table index for buffer t3 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_TE (7u) ///< UPTR table index for buffer te +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_RAND (8u) ///< UPTR table index for the buffer with random data used for bliding +#define MCUXCLRSA_INTERNAL_PRIVPLAIN_UPTRT_SIZE (9u) ///< UPTR table size of function mcuxClRsa_privatePlain + +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_privateCRT */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_ MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_ + * @brief UPTR table defines for function mcuxClRsa_privateCRT. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_INPUT (0u) ///< UPTR table index for the input buffer +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND (1u) ///< UPTR table index for the buffer with random data used for bliding +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B (2u) ///< UPTR table index for buffer pq_b +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 (3u) ///< UPTR table index for buffer primeT0 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 (4u) ///< UPTR table index for buffer primeT1 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 (5u) ///< UPTR table index for buffer primeT2 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET3 (6u) ///< UPTR table index for buffer primeT3 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 (7u) ///< UPTR table index for buffer primeT4 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_TE (8u) ///< UPTR table index for buffer primeTE +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R (9u) ///< UPTR table index for buffer r +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 (10u) ///< UPTR table index for buffer primeT5 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_M (11u) ///< UPTR table index for buffer m +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 (12u) ///< UPTR table index for buffer modT1 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 (13u) ///< UPTR table index for buffer modT2 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3 (14u) ///< UPTR table index for buffer modT3 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 (15u) ///< UPTR table index for buffer modT4 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N (16u) ///< UPTR table index for buffer n +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_CONST0 (17u) ///< UPTR table index for constant 0 +#define MCUXCLRSA_INTERNAL_PRIVCRT_UPTRT_SIZE (18u) ///< UPTR table size of function mcuxClRsa_privateCRT +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_noEncode */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_NOENCODE_ MCUXCLRSA_INTERNAL_UPTRTINDEX_NOENCODE_ + * @brief UPTR table defines for function mcuxClRsa_noEncode. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_NOENCODE_OUT (0u) ///< UPTR table index for buffer input +#define MCUXCLRSA_INTERNAL_NOENCODE_UPTRT_SIZE (1u) ///< UPTR table size of function mcuxClRsa_noEncode +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_noVerify */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_ MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_ + * @brief UPTR table defines for function mcuxClRsa_noVerify. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_IN (0u) ///< UPTR table index for buffer input +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_TMP (1u) ///< UPTR table index for buffer tmp +#define MCUXCLRSA_INTERNAL_NOVERIFY_UPTRT_SIZE (2u) ///< UPTR table size of function mcuxClRsa_noVerify +/** @} */ + + + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_KeyGeneration_Plain */ +/****************************************************************************/ +/** +* @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_ MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_ +* @brief UPTR table defines for function mcuxClRsa_KeyGeneration_Plain. +* @ingroup mcuxClRsa_Internal_Macros +* @{ +*/ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P (0u) ///< UPTR table index for buffer p +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_Q (1u) ///< UPTR table index for buffer q +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_E (2u) ///< UPTR table index for buffer e +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N (3u) ///< UPTR table index for buffer n +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_D (4u) ///< UPTR table index for buffer d +#define MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_UPTRT_SIZE (5u) ///< UPTR table size of function mcuxClRsa_KeyGeneration_Plain +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_KeyGeneration_Crt */ +/****************************************************************************/ +/** +* @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_ MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_ +* @brief UPTR table defines for function mcuxClRsa_KeyGeneration_Crt. +* @ingroup mcuxClRsa_Internal_Macros +* @{ +*/ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E (0u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P (1u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q (2u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DP (3u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DQ (4u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_QINV (5u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_N (6u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1 (7u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2 (8u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3 (9u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0 (10u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT1 (11u) +#define MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_UPTRT_SIZE (12u) ///< UPTR table size of function mcuxClRsa_KeyGeneration_Crt +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_TestPrimeCandidate */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_ MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_ + * @brief UPTR table defines for function mcuxClRsa_TestPrimeCandidate. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_E (0u) ///< UPTR table index for buffer e +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE (1u) ///< UPTR table index for buffer with prime candidate +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE_64MOST (2u) ///< UPTR table index for 64 most significant bits of prime candidate +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_NUMTOCOMPARE (3u) ///< UPTR table index for buffer with number to compare +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_A0 (4u) ///< UPTR table index for buffer A0 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1 (5u) ///< UPTR table index for the first gcd operand +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2 (6u) ///< UPTR table index for the second gcd operand +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0 (7u) ///< UPTR table index for the constant 0 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT1 (8u) ///< UPTR table index for the constant 1 +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT2 (9u) ///< UPTR table index for the constant 2 +#define MCUXCLRSA_INTERNAL_TESTPRIME_UPTRT_SIZE (10u) ///< UPTR table size of function mcuxClRsa_TestPrimeCandidate +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_GenerateProbablePrime */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_ MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_ + * @brief UPTR table defines for function mcuxClRsa_GenerateProbablePrime. + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_NUMTOCOMPARE (0u) ///< UPTR table index for buffer with number to compare +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_A0 (1u) ///< UPTR table index for buffer A0 +#define MCUXCLRSA_INTERNAL_GENPRIME_UPTRT_SIZE (2u) ///< UPTR table size of function mcuxClRsa_GenerateProbablePrime +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_MillerRabinTest */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_ MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_ + * @brief UPTR table defines for function mcuxClRsa_MillerRabinTest + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE (0u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_QSQUARED (1u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT (2u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X (3u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0 (4u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T1 (5u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T2 (6u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T3 (7u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_TE (8u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_CONSTANT (9u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_UPTRT_SIZE (10u) +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_ComputeD */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_ MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_ + * @brief UPTR table defines for function mcuxClRsa_ComputeD + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_P (0u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_Q (1u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_D (2u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_E (3u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PSUB1 (4u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1 (5u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI (6u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_LCM (7u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_T (8u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_CONSTANT (9u) +#define MCUXCLRSA_INTERNAL_COMPD_UPTRT_SIZE (10u) +/** @} */ + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_TestPQDistance */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPQDISTANCE_ MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPQDISTANCE_ + * @brief UPTR table defines for function mcuxClRsa_ComputeD + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P128MSB (0u) +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q128MSB (1u) +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P100MSB (2u) +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q100MSB (3u) +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_CONSTANT28 (4u) +#define MCUXCLRSA_INTERNAL_TESTPQDISTANCE_UPTRT_SIZE (5u) + + +/****************************************************************************/ +/* Indices of operands in PKC workarea and UPTR table for */ +/* the mcuxClRsa_RemoveBlinding */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_ MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_ + * @brief UPTR table defines for function mcuxClRsa_RemoveBlinding + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_B (0u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_NB (1u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_X (2u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_R (3u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T1 (4u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2 (5u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_ZERO (6u) +#define MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_UPTRT_SIZE (7u) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_PKCDEFS_H_ */ + + diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcTypes.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcTypes.h new file mode 100644 index 000000000..8d77dc68d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_PkcTypes.h @@ -0,0 +1,45 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * + * @file: mcuxClRsa_Internal_PkcTypes.h + * @brief: Redefinition of types related to PKC. + * + */ + +#ifndef MCUXCLRSA_INTERNAL_PKCTYPES_H_ +#define MCUXCLRSA_INTERNAL_PKCTYPES_H_ + +#include +#include + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include +/** @brief PKC wordsize in byte */ +#define MCUXCLRSA_PKC_WORDSIZE MCUXCLPKC_WORDSIZE +/** @brief Round-up a length to a multiple of PKC wordsize. */ +#define MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLen) MCUXCLPKC_ROUNDUP_SIZE(byteLen) + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_PKCTYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Types.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Types.h new file mode 100644 index 000000000..82247165c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Internal_Types.h @@ -0,0 +1,113 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Internal_Types.h + * @brief Internal type definitions for the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_INTERNAL_TYPES_H_ +#define MCUXCLRSA_INTERNAL_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include + + + +#ifdef __cplusplus +extern "C" { +#endif + + /** + * @defgroup mcuxClRsa_Internal_Macros mcuxClRsa_Internal_Macros + * @brief Defines all internal macros of the @ref mcuxClRsa component + * @ingroup mcuxClRsa + * @{ + */ + +/** + * @defgroup MCUXCLRSA_STATUS_INTERNAL_ MCUXCLRSA_STATUS_INTERNAL_ + * @brief Internal return code definitions + * @ingroup mcuxClRsa_Internal_Macros + * @{ + */ +#define MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK ((mcuxClRsa_Status_t) 0xB2B25A5Au ) ///< RSA key operation successful +#define MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK ((mcuxClRsa_Status_t) 0xB2B29A9Au ) ///< RSA encoding operation successful +#define MCUXCLRSA_STATUS_INTERNAL_MGF_OK ((mcuxClRsa_Status_t) 0xB2B2AAAAu ) ///< RSA mask generation function operation successful +#define MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_CMP_FAILED ((mcuxClRsa_Status_t) 0xB2B2ABABu ) ///< RSA key generation test failed at comparison stage +#define MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDA0_FAILED ((mcuxClRsa_Status_t) 0xB2B2ADADu ) ///< RSA key generation test failed at the stage of GCD with A0 +#define MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDE_FAILED ((mcuxClRsa_Status_t) 0xB2B2AEAEu ) ///< RSA key generation test failed at the stage of GCD with E +#define MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_MRT_FAILED ((mcuxClRsa_Status_t) 0xB2B2AFAFu ) ///< RSA key generation test failed at the stage of Miller Rabin Test +/** @} */ + +/** + * @} + */ + +/*********************************************************** + * TYPES RELATED TO PADDING FUNCTIONALITY + **********************************************************/ + + /** + * @brief Function type for padding engine + * + * Generic function pointer to padding function declarations + * + * @param[in] pSession Pointer to session. + * @param[in] pInput Pointer to input message or message digest to padding function. + * @param[in] inputLength Length of input in bytes. + * @param[in] pVerificationInput Pointer to encoded message that is verified. + * @param[in] pHashAlgo Pointer to hash algorithm used in padding function. + * @param[in] pLabel Pointer to label in case of OAEP padding. + * @param[in] saltlabelLength Length of salt in case of PSS padding, or label in case of OAEP padding. + * @param[in] keyBitLength Bitlength of public modulus n. + * @param[in] options Options. + * @param[out] pOutput Output of padding or verification function. + * @param[out] pOutLength Length of output in bytes. + * + * @return Status of the padding operation + */ +MCUX_CSSL_FP_FUNCTION_POINTER(mcuxClRsa_PadVerModeEngine_t, +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) (* mcuxClRsa_PadVerModeEngine_t)( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength)); + + +/** + * @brief Structure type for RSA-specific padding modes, i.e. required information to execute a selected padding mode. + */ +struct mcuxClRsa_SignVerifyMode_t +{ + uint32_t EncodeVerify_FunId; ///< Flow protection function identifier of encoding or verify function. + mcuxClHash_Algo_t pHashAlgo1; ///< Pointer to hashing functionality. + mcuxClHash_Algo_t pHashAlgo2; ///< RFU + mcuxClRsa_PadVerModeEngine_t pPaddingFunction; ///< Pointer to padding functionality. +}; + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_KeyGeneration_Crt_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_KeyGeneration_Crt_FUP.h new file mode 100644 index 000000000..8e164d783 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_KeyGeneration_Crt_FUP.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_KeyGeneration_Crt_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_KeyGeneration_Crt +*/ +#ifndef MCUXCLRSA_KEYGENERATION_CRT_FUP_H_ +#define MCUXCLRSA_KEYGENERATION_CRT_FUP_H_ +#include // Exported features flags header +#include + +#define mcuxClRsa_KeyGeneration_Crt_Steps10_FUP_LEN 3u +#define mcuxClRsa_KeyGeneration_Crt_Steps11_FUP_LEN 3u +#define mcuxClRsa_KeyGeneration_Crt_Steps12_FUP_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps10_FUP[mcuxClRsa_KeyGeneration_Crt_Steps10_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps11_FUP[mcuxClRsa_KeyGeneration_Crt_Steps11_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps12_FUP[mcuxClRsa_KeyGeneration_Crt_Steps12_FUP_LEN]; + +#endif /* MCUXCLRSA_KEYGENERATION_CRT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_MillerRabinTest_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_MillerRabinTest_FUP.h new file mode 100644 index 000000000..4da5e5608 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_MillerRabinTest_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_MillerRabbinTest_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_MillerRabbinTest +*/ +#ifndef MCUXCLRSA_MILLERRABINTEST_FUP_H_ +#define MCUXCLRSA_MILLERRABINTEST_FUP_H_ +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP_LEN 4u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP[mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_MILLERRABINTEST_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_PrivateCrt_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_PrivateCrt_FUP.h new file mode 100644 index 000000000..36e5ad664 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_PrivateCrt_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_PrivateCrt_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_PrivateCrt +*/ +#ifndef MCUXCLRSA_PRIVATECRT_FUP_H_ +#define MCUXCLRSA_PRIVATECRT_FUP_H_ +#include // Exported features flags header +#include + +#define mcuxClRsa_PrivateCrt_T1mb_FUP_LEN 3u +#define mcuxClRsa_PrivateCrt_T2T3T4mb_FUP_LEN 6u +#define mcuxClRsa_PrivateCrt_CalcM_b_FUP_LEN 5u +#define mcuxClRsa_PrivateCrt_CalcM1_FUP_LEN 4u +#define mcuxClRsa_PrivateCrt_ReductionME_FUP_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_T2T3T4mb_FUP[mcuxClRsa_PrivateCrt_T2T3T4mb_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_T1mb_FUP[mcuxClRsa_PrivateCrt_T1mb_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_CalcM1_FUP[mcuxClRsa_PrivateCrt_CalcM1_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_CalcM_b_FUP[mcuxClRsa_PrivateCrt_CalcM_b_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_ReductionME_FUP[mcuxClRsa_PrivateCrt_ReductionME_FUP_LEN]; + +#endif /* MCUXCLRSA_PRIVATECRT_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Public_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Public_FUP.h new file mode 100644 index 000000000..dcdbe4b16 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_Public_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Public_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_Public +*/ +#ifndef MCUXCLRSA_PUBLIC_FUP_H_ +#define MCUXCLRSA_PUBLIC_FUP_H_ +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define mcuxClRsa_Public_ReductionME_FUP_LEN 3u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_Public_ReductionME_FUP[mcuxClRsa_Public_ReductionME_FUP_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_PUBLIC_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_RemoveBlinding_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_RemoveBlinding_FUP.h new file mode 100644 index 000000000..b534f1c01 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_RemoveBlinding_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_RemoveBlinding_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_RemoveBlinding +*/ +#ifndef MCUXCLRSA_REMOVEBLINDING_FUP_H_ +#define MCUXCLRSA_REMOVEBLINDING_FUP_H_ +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define mcuxClRsa_RemoveBlinding_FUP_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_RemoveBlinding_FUP[mcuxClRsa_RemoveBlinding_FUP_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_REMOVEBLINDING_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPQDistance_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPQDistance_FUP.h new file mode 100644 index 000000000..852527684 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPQDistance_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_TestPQDistance_FUP.h +* @brief defines FUP programs byte arrays mcuxClRsa_TestPQDistance +*/ +#ifndef MCUXCLRSA_TESTPQDISTANCE_FUP_H_ +#define MCUXCLRSA_TESTPQDISTANCE_FUP_H_ +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define mcuxClRsa_TestPQDistance_FUP_LEN 4u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPQDistance_FUP[mcuxClRsa_TestPQDistance_FUP_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_TESTPQDISTANCE_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPrimeCandidate_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPrimeCandidate_FUP.h new file mode 100644 index 000000000..5a1a5f7ff --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/internal/mcuxClRsa_TestPrimeCandidate_FUP.h @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_TestPrimeCandidate_FUP.h +* @brief defines FUP programs byte arrays for mcuxClRsa_TestPrimeCandidate +*/ +#ifndef MCUXCLRSA_TESTPRIMECANDIDATE_FUP_H_ +#define MCUXCLRSA_TESTPRIMECANDIDATE_FUP_H_ +#include // Exported features flags header +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define mcuxClRsa_TestPrimeCandidate_Steps2_FUP_LEN 6u +#define mcuxClRsa_TestPrimeCandidate_Steps3_FUP_LEN 5u + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPrimeCandidate_Steps2_FUP[mcuxClRsa_TestPrimeCandidate_Steps2_FUP_LEN]; +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPrimeCandidate_Steps3_FUP[mcuxClRsa_TestPrimeCandidate_Steps3_FUP_LEN]; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_TESTPRIMECANDIDATE_FUP_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa.h new file mode 100644 index 000000000..96e9eb9e5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa.h @@ -0,0 +1,66 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa.h + * @brief Top-level include file for the mcuxClRsa component + * + * This includes headers for all of the functionality provided by the mcuxClRsa component. + * + * @defgroup mcuxClRsa mcuxClRsa + * @brief RSA component + * + * The mcuxClRsa component implements the RSA functionality supported by CLNS. + * This includes RSA signature generation and verification according to PKCS#1 v2.2. + * @if (MCUXCL_FEATURE_RSA_KEYGENERATION) + * It also provides RSA key generation functionality. + * @endif + * The RSA component relies on the mcuxClMath component for modular arithmetic operations as well as the secure and non-secure exponentiation. + * It further relies on the mcuxHash component for the execution of hashing operations. + * The component offers the following functionality: + * - RSA signature generation and verification: + *
    + *
  1. RSA signature generation using RSA keys in private plain or private CRT format together with the PKCS#1 v1.5 padding or PSS + * padding functionality, according to to RSASSA-PSS-SIGN or RSASSA-PKCS1-v1_5-SIGN of PKCS #1 v2.2. + *
  2. RSA signature verification using RSA keys public format together with the PKCS#1 v1.5 padding or PSS + * verification functionality, according to to RSASSA-PSS-VERIFY or RSASSA-PKCS1-v1_5-VERIFY of PKCS #1 v2.2. + *
  3. RSA signature generation primitive RSASP1 (exponentiation with public exponent) according to PKCS #1 v2.2. + *
  4. RSA signature verification primitive RSAVP1 (exponentiation with RSA keys in private plain or private CRT format) according to PKCS #1 v2.2. + *
  5. The bit-length of the modulus can vary from 512 bits to 4096 bits in multiples of 8. + *
  6. The bit-length of the public exponent is limited to: of 2 <= e < N. + *
  7. The bit-length of the private exponent is limited to: d < N. + *
+ * @if (MCUXCL_FEATURE_RSA_KEYGENERATION) + * - RSA key generation + *
    + *
  1. Generation of an RSA key in CRT format {p, q, dp, dq, qInv} and n. + *
  2. Generation of an RSA key in Plain format {d, n}. + *
  3. Primes p and q are generated based on the method specified in the FIPS 186-4, Appendix B.3.3. + *
  4. Private exponent d is computed with the requirements specified in the FIPS 186-4, Appendix B.3.1. + *
  5. Primes p and q are generated using probabilistic primality test with the probability of not being prime less than 2^(-125). + *
  6. The bit-length of the key size is limited to 2048, 3072 and 4096. + *
  7. The public exponent is restricted to (FIPS compliant) odd values in the range 2^16 < e < 2^256 (i.e. including 0x10001). + *
  8. User shall ensure that if FIPS 186-4 compliance is claimed, the key generation functions are used to generate keys of 2048 or 3072 bits only. + *
+ * @endif + */ + +#ifndef MCUXCLRSA_H_ +#define MCUXCLRSA_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#endif /* MCUXCLRSA_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_ComputeD_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_ComputeD_FUP.h new file mode 100644 index 000000000..a9201fa6d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_ComputeD_FUP.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_ComputeD_Steps123_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Compute p' = p-1 */ + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PSUB1, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_CONSTANT), + /* Compute q' = q-1 */ + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_CONSTANT), + /* Compute phi = (p−1)(q−1) */ + FUP_MC1_PM(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PSUB1, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1), + + /* Compute qsub1 = gcd(p-1,q−1) */ + FUP_MC1_GCD(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PSUB1, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1), + /* for both operand are congruent 2 mod 4, the result should be left shift by 1 bit */ + FUP_OP1_SHL(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_CONSTANT) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Constants.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Constants.h new file mode 100644 index 000000000..e552740c5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Constants.h @@ -0,0 +1,158 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Constants.h + * @brief Constant definitions for the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_CONSTANTS_H_ +#define MCUXCLRSA_CONSTANTS_H_ + +#include // Exported features flags header + +#ifdef __cplusplus +extern "C" { +#endif + +/* TODO: + * Using defines for SGI Hashes is a workaround to enable testing of internal padding functions. This should not be in the CL, as mode constructors are used for S5xy. + * CL artifact to remove this workaround: CLNS-6116 + * TT artifact to adapt the tests: CLNS-6117 + */ + +/** + * @defgroup mcuxClRsa_Constants mcuxClRsa_Constants + * @brief Constants of @ref mcuxClRsa component + * @ingroup mcuxClRsa + * @{ + */ + +/** +* @defgroup mcuxClRsa_Sign_Modes mcuxClRsa_Sign_Modes +* @brief Signing modes of the @ref mcuxClRsa component +* @ingroup mcuxClRsa_Constants +* @{ +*/ + +/** + * @brief Mode definition for RSASP1 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/224 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/256 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/384 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-SIGN using SHA-2/512 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512; + +/** + * @brief Mode definition for RSASSA-PSS-SIGN using SHA-2/224 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224; + +/** + * @brief Mode definition for RSASSA-PSS-SIGN using SHA-2/256 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256; + +/** + * @brief Mode definition for RSASSA-PSS-SIGN using SHA-2/384 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384; + +/** + * @brief Mode definition for RSASSA-PSS-SIGN using SHA-2/512 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512; + +/** + * @} + */ + +/** +* @defgroup mcuxClRsa_Verify_Modes mcuxClRsa_Verify_Modes +* @brief Verify modes of the @ref mcuxClRsa component +* @ingroup mcuxClRsa_Constants +* @{ +*/ + +/** + * @brief Mode definition for RSAVP1 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/224 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/256 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/384 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384; + +/** + * @brief Mode definition for RSASSA-PKCS1-v1_5-VERIFY using SHA-2/512 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512; + +/** + * @brief Mode definition for RSASSA-PSS-VERIFY using SHA-2/224 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224; + +/** + * @brief Mode definition for RSASSA-PSS-VERIFY using SHA-2/256 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256; + +/** + * @brief Mode definition for RSASSA-PSS-VERIFY using SHA-2/384 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384; + +/** + * @brief Mode definition for RSASSA-PSS-VERIFY using SHA-2/512 + */ +extern const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512; + +/** + * @} + * @} + */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Functions.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Functions.h new file mode 100644 index 000000000..154d23876 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Functions.h @@ -0,0 +1,388 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Functions.h + * @brief Top-level API of the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_FUNCTIONS_H_ +#define MCUXCLRSA_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mcuxClRsa_Functions mcuxClRsa_Functions + * @brief Defines all functions of @ref mcuxClRsa + * @ingroup mcuxClRsa + * @{ + */ + +/** + * @brief RSA sign operation + * + * This function performs an RSA signature generation according to RSASP1, RSASSA-PSS-SIGN or RSASSA-PKCS1-v1_5-SIGN + * of PKCS #1 v2.2. Based on the passed key type, it is selected, whether to perform this operation using a private + * plain, a private CRT key, or whether to use a private CRT key and protect the operation against perturbation attacks. + * Based on the selection of the padding mode, it is determined, whether to perform no padding, or whether to perform + * one of the supported paddings based on one of the supported hash functions. + * The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8. + * The private exponent is limited to d < n. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pKey Pointer to key structure of type @ref mcuxClRsa_Key + * @param[in] pMessageOrDigest Pointer to buffer, which contains the input to the sign operation + * @param[in] messageLength Byte-length of MessageOrDigest + * @param[in] pPaddingMode Pointer to signing mode of type @ref mcuxClRsa_SignVerifyMode_t + * @param[in] saltLength Byte-length of salt + * @param[in] options Options field + * @param[out] pSignature Pointer to buffer, which contains the result (signature) + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pKey:
+ *
The key entries must meet the following conditions: + * - Entry keytype can be set to #MCUXCLRSA_KEY_PRIVATEPLAIN to perform the secure exponentiation with + * a private plain key, #MCUXCLRSA_KEY_PRIVATECRT to perform the secure exponentiation with a private CRT key, + * or #MCUXCLRSA_KEY_PRIVATECRT_DFA to perform the secure exponentiation with a private CRT key, + * protecting the operation against perturbation attacks. In case of specifying another key type, the + * function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8; + * - In case of type #MCUXCLRSA_KEY_PRIVATEPLAIN, the exponent + * d must be smaller than modulus n; in case of type #MCUXCLRSA_KEY_PRIVATECRT or #MCUXCLRSA_KEY_PRIVATECRT_DFA, + * the d from which dp and dq are derived must be smaller than (p * q); + * - In case of type #MCUXCLRSA_KEY_PRIVATECRT + * or #MCUXCLRSA_KEY_PRIVATECRT_DFA it is required that: bitlength(p) == bitlength(q) == 1/2 * bitlength(n). + *
pMessageOrDigest:
+ *
The input must meet the following conditions: + * - It must be given in big-endian byte order; + * - In case of key type #MCUXCLRSA_KEY_PRIVATEPLAIN and mode #mcuxClRsa_Mode_Sign_NoEncode, the input must + * be smaller than n, otherwise the function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - In case of type #MCUXCLRSA_KEY_PRIVATECRT or #MCUXCLRSA_KEY_PRIVATECRT_DFA and mode + * #mcuxClRsa_Mode_Sign_NoEncode, the input must be smaller than (p * q), otherwise the function + * returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - In case of option #MCUXCLRSA_OPTION_MESSAGE_DIGEST the length of pMessageOrDigest is determined by the selected + * hash algorithm; + * - In case of mode #mcuxClRsa_Mode_Sign_NoEncode the length of pMessageOrDigest is determined by the length of n; + * - The signature length is determined by the modulus length (bytelength(n)). + *
messageLength:
+ *
This value is only regarded in case of option #MCUXCLRSA_OPTION_MESSAGE_PLAIN. + * In case of option #MCUXCLRSA_OPTION_MESSAGE_DIGEST, or mode RSASP1, please set to zero. + *
pPaddingMode:
+ *
The mode specifies the targeted padding and hashing algorithms. + * Please set to one of @ref mcuxClRsa_Sign_Modes. + *
saltLength:
+ *
This value is only regarded in case of performing a RSASSA-PSS-SIGN operation. Otherwise, please set to zero. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pMessageOrDigest points to a plain message (#MCUXCLRSA_OPTION_MESSAGE_PLAIN) + * to be hashed internally by the sign function, or to a message digest (#MCUXCLRSA_OPTION_MESSAGE_DIGEST). + * In case of mode RSASP1, please set to zero. + *
pSignature:
+ *
The output is returned in in big-endian byte order. + *
+ *
+ * + * @return Status of the mcuxClRsa_sign operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_SIGN_OK Sign operation executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_sign) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_sign( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pMessageOrDigest, + const uint32_t messageLength, + const mcuxClRsa_SignVerifyMode pPaddingMode, + const uint32_t saltLength, + const uint32_t options, + mcuxCl_Buffer_t pSignature +); + +/** + * @brief RSA verify operation + * + * This function performs an RSA signature verification according to RSAVP1, RSASSA-PSS-VERIFY or RSASSA-PKCS1-v1_5-VERIFY + * of PKCS #1 v2.2. Based on the selection of the padding mode, it is determined, whether to perform no padding verification, + * or whether to perform one of the supported padding verifications based on one of the supported hash functions. + * The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8. The public + * exponent is limited to 2 <= e < N. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] pKey Pointer to key structure of type @ref mcuxClRsa_Key + * @param[in] pMessageOrDigest Pointer to buffer, which contains the input to the verify operation + * @param[in] messageLength Byte-length of MessageOrDigest + * @param[in] pSignature Pointer to buffer, which contains the signature + * @param[in] pVerifyMode Pointer to verification mode of type @ref mcuxClRsa_SignVerifyMode_t + * @param[in] saltLength Byte-length of salt + * @param[in] options Options field + * @param[out] pOutput Pointer to output buffer + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. + *
pKey:
+ *
The key entries must meet the following conditions: + * - Entry keytype must be set to #MCUXCLRSA_KEY_PUBLIC. In case of passing another key type, the function + * returns #MCUXCLRSA_STATUS_INVALID_INPUT. The functions checks, internally, whether the required key entries + * are not set to NULL. If so, the function returns #MCUXCLRSA_STATUS_INVALID_INPUT; + * - The supported bit-lengths of the modulus range from 512 to 4096 in multiples of 8; + * - It is required that e is greater or equal to 2 and smaller than n. + *
pMessageOrDigest:
+ *
The input must meet the following conditions: + * - It must be provided in big-endian byte order; + * - In case of mode RSAVP1, please set to NULL. + *
messageLength:
+ *
This value is only regarded in case of option #MCUXCLRSA_OPTION_MESSAGE_PLAIN. + * In case of option #MCUXCLRSA_OPTION_MESSAGE_DIGEST, or mode RSAVP1, please set to zero. + *
pSignature:
+ *
The signature must meet the following conditions: + * - It must be given in big-endian byte order; + * - The signature length is determined by the modulus length (bytelength(n)); + * - The signature value must be smaller than n. If it is bigger the function returns #MCUXCLRSA_STATUS_INVALID_INPUT. + *
pVerifyMode:
+ *
The mode specifies the targeted padding verification and hashing algorithms. + * Please set to one of @ref mcuxClRsa_Verify_Modes. + *
saltLength:
+ *
This value is only regarded in case of performing a RSASSA-PSS-VERIFY operation. Otherwise, please set to zero. + *
options:
+ *
This field is used to select options of the sign operation: + * - bits 31-8: RFU; please set to zero + * - bits 7-0: Specify, whether pMessageOrDigest points to a plain message (#MCUXCLRSA_OPTION_MESSAGE_PLAIN) + * to be hashed internally by the verify function, or to a message digest (#MCUXCLRSA_OPTION_MESSAGE_DIGEST). + * In case of mode RSAVP1, please set to zero. + *
pOutput:
+ *
In case of mode RSAVP1 this pointer points to the buffer, where the result will be stored in big-endian byte + * order. This buffer must have the same byte-length as the modulus. In case of modes RSASSA-PSS-VERIFY and + * RSASSA-PKCS1-v1_5-VERIFY please set to NULL. + *
+ *
+ * + * @return Status of the mcuxClRsa_verify operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_VERIFY_OK Verify operation executed successfully. + * @retval #MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK Verification primitive operation executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_VERIFY_FAILED The signature verification failed. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for the flow protection are not balanced. + * + * @attention This function uses PRNG which has to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_verify( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pMessageOrDigest, + const uint32_t messageLength, + mcuxCl_Buffer_t pSignature, + const mcuxClRsa_SignVerifyMode pVerifyMode, + const uint32_t saltLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput +); + + + + +/** + * @brief Generates an RSA key in CRT format + * + * This function for given public exponent and key size generates an RSA private key + * in CRT representation (p, q, dp, dq, qInv) and computes the modulus n. + * + * Primes p and q are generated based on the method specified in the FIPS 186-4, Appendix B.3.3 using probabilistic + * primality test with the probability of not being prime less than 2^(-125). + * The public exponent is restricted to (FIPS compliant) odd values in the range 2^16 < e < 2^256 (i.e. including 0x10001). + * The bit-length of the key size is limited to 2048, 3072 and 4096. + * The keys generated by this function are FIPS 186-4 compliant provided their length is either 2048 or 3072 bits + * and the exponent value is an odd integer between 2^16 and 2^256. + * + * The two key handles are linked with each other using mcuxClKey_linkKeyPair. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] type Type of the key + * @param[in] protection Protection and flush mechanism that must be applied to the generated key. + * @param[out] privKey Key handle for the generated private key + * @param[out] pPrivData Pointer to the buffer where the generated private CRT key data needs to be written + * @param[out] pPrivDataLength Will be set by the number of bytes of data that have been written to the \p pPrivData buffer + * @param[out] pubKey Key handle for the generated public key + * @param[out] pPubData Pointer to the buffer where the generated public key data needs to be written + * @param[out] pPubDataLength Will be set by the number of bytes of data that have been written to the \p pPubData buffer + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized + * with the entropy level (security strength) in accordance with the value of type.size, as specified in SP 800-57, Part 1. + *
type:
+ *
Type of the key. It contains information about the input parameters: + * - type.size - length of the generated key + * - type.info - pointer to key entry i.e. public exponent. It points to data type mcuxClRsa_KeyEntry_t* (i.e. pointer to buffer containing + * the public exponent data and byte-length of the public exponent). + *
protection :
+ *
Protection and flush mechanism that must be applied to the generated key. + *
privKey:
+ *
Key handle for the generated private key. + *
pPrivData:
+ *
Pointer to the buffer where the generated private CRT key (p, q, qInv, dp, dq) data needs to be written. + * This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: p, q, qInv, dp, dq. + * Buffer is allocated by the caller. + *
pPrivDataLength:
+ *
Number of bytes of data that have been written to the \p pPrivData buffer. + *
pubKey:
+ *
Key handle for the generated public key. + *
pPubData:
+ *
Pointer to the buffer where the generated public key (n, e) data needs to be written. + * This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, e. + * Buffer is allocated by the caller. + *
pPubDataLength:
+ *
Number of bytes of data that have been written to the \p pPubData buffer. + *
+ *
+ * + * @return Status of the mcuxClRsa_KeyGeneration_Crt operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK RSA key generation operation executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED RSA key generation exceeds the limit of iterations to generate a prime. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for + * the flow protection are not balanced. + * + * @attention This function uses DRBG and PRNG which have to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_KeyGeneration_Crt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Crt( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength + ); + + +/** + * @brief RSA key generation of private plain key operation. + * + * This function for given public exponent and key size generates RSA private key in in plain from (d, n). + * + * Private exponent d is computed with the requirements specified in the FIPS 186-4, Appendix B.3.1. + * Primes p and q are generated based on the method specified in the FIPS 186-4, Appendix B.3.3 using probabilistic + * primality test with the probability of not being prime less than 2^(-125). + * The public exponent is restricted to (FIPS compliant) odd values in the range 2^16 < e < 2^256 (i.e. including 0x10001). + * The bit-length of the key size is limited to 2048, 3072 and 4096. + * The keys generated by this function are FIPS 186-4 compliant provided their length is either 2048 or 3072 bits + * and the exponent value is an odd integer between 2^16 and 2^256. + * + * The two key handles are linked with each other using mcuxClKey_linkKeyPair. + * + * @param[in] pSession Pointer to #mcuxClSession_Descriptor + * @param[in] type Type of the key + * @param[in] protection Protection and flush mechanism that must be applied to the generated key + * @param[out] privKey Key handle for the generated private key + * @param[out] pPrivData Pointer to the buffer where the generated private plain key data needs to be written + * @param[out] pPrivDataLength Will be set by the number of bytes of data that have been written to the \p pPrivData buffer + * @param[out] pubKey Key handle for the generated public key + * @param[out] pPubData Pointer to the buffer where the generated public key data needs to be written + * @param[out] pPubDataLength Will be set by the number of bytes of data that have been written to the \p pPubData buffer + * + *
+ *
Parameter properties
+ * + *
+ *
pSession:
+ *
The session pointed to by pSession has to be initialized prior to a call to this function. The RNG shall be initialized + * with the entropy level (security strength) in accordance with the value of type.size, as specified in SP 800-57, Part 1. + *
type:
+ *
Type of the key. It contains information about the input parameters: + * - type.size - length of the generated key + * - type.info - pointer to key entry i.e. public exponent. It points to data type mcuxClRsa_KeyEntry_t*(i.e. pointer to buffer containing + * the public exponent data and byte-length of the public exponent). + *
protection :
+ *
Protection and flush mechanism that must be applied to the generated key. + *
privKey:
+ *
Key handle for the generated private key. + *
pPrivData:
+ *
Pointer to the buffer where the generated private plain key (n, d) data needs to be written. + * This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, d. + * Buffer is allocated by the caller. + *
pPrivDataLength:
+ *
Number of bytes of data that have been written to the \p pPrivData buffer. + *
pubKey:
+ *
Key handle for the generated public key. + *
pPubData:
+ *
Pointer to the buffer where the generated public key (n, e) data needs to be written. + * This buffer contains key type and key entries (mcuxClRsa_Key data type) followed by the key data, i.e.: n, e. + * Buffer is allocated by the caller. + *
pPubDataLength:
+ *
Number of bytes of data that have been written to the \p pPubData buffer. + *
+ *
+ * + * @return Status of the mcuxClRsa_KeyGeneration_Plain operation (see @ref MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t)) + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_OK RSA key generation operation executed successfully. + * @retval #MCUXCLRSA_STATUS_INVALID_INPUT The input parameters are not valid. + * @retval #MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED RSA key generation exceeds the limit of iterations to generate a prime. + * @retval #MCUXCLRSA_STATUS_ERROR An error occurred during the execution. In that case, expectations for + * the flow protection are not balanced. + * + * @attention This function uses DRBG and PRNG which have to be initialized prior to calling the function. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClRsa_KeyGeneration_Plain) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Plain( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength + ); + + +/** + * @} + */ /* mcuxClRsa_Functions */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLRSA_FUNCTIONS_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_KeyGeneration_Crt_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_KeyGeneration_Crt_FUP.h new file mode 100644 index 000000000..1b93d2d3e --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_KeyGeneration_Crt_FUP.h @@ -0,0 +1,46 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_KeyGeneration_Crt_Steps10_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT1), + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_KeyGeneration_Crt_Steps11_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT1), + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_KeyGeneration_Crt_Steps12_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0), + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MemoryConsumption.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MemoryConsumption.h new file mode 100644 index 000000000..920c2f9b4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MemoryConsumption.h @@ -0,0 +1,249 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_MemoryConsumption.h + * @brief Defines the memory consumption for the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_MEMORYCONSUMPTION_H_ +#define MCUXCLRSA_MEMORYCONSUMPTION_H_ + + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa Sign */ +/****************************************************************************/ + +/** + * @defgroup MCUXCLRSA_SIGN_WA MCUXCLRSA_SIGN_WA + * @brief Definitions of workarea sizes for the mcuxClRsa Sign + * @ingroup mcuxClRsa_Macros + * @{ + */ +#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE (152u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. +#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE (280u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. +#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE (408u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. +#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE (536u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_NoEncode. + +#define MCUXCLRSA_SIGN_PLAIN_NOENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_NOENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_PLAIN_NOENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. + +#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE (280u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE (408u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE (536u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PSSENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PSSENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_PLAIN_PSSENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. + +#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE (280u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE (408u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE (536u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*. +#define MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_PLAIN_PKCS1V15ENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. + +#define MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE (1064u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private plain keys. +#define MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE (1960u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private plain keys. +#define MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE (2856u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private plain keys. +#define MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE (3752u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private plain keys. +#define MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_4096_WAPKC_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_3072_WAPKC_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_PLAIN_2048_WAPKC_SIZE : \ + MCUXCLRSA_SIGN_PLAIN_1024_WAPKC_SIZE))) ///< Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATEPLAIN. + +#define MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE (104u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 1024-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE (168u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 2048-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE (232u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 3072-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE (296u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_NoEncode, for 4096-bit private CRT keys. + +#define MCUXCLRSA_SIGN_CRT_NOENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_NOENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_CRT_NOENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. + +#define MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 1024-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 2048-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE (232u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 3072-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE (296u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_Pss_Sha2_*, for 4096-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PSSENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PSSENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_CRT_PSSENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. + +#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 1024-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 2048-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE (232u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 3072-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE (296u) ///< Definition of CPU workarea size for the mcuxClRsa_sign function using mode mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_*, for 4096-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_3072_WACPU_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_2048_WACPU_SIZE : \ + MCUXCLRSA_SIGN_CRT_PKCS1V15ENCODE_1024_WACPU_SIZE))) ///< Macro to extract CPU workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. + +#define MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE (968u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 1024-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE (1864u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 2048-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE (2760u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 3072-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE (3656u) ///< Definition of PKC workarea size for the mcuxClRsa_sign function for 4096-bit private CRT keys. +#define MCUXCLRSA_SIGN_CRT_WAPKC_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_4096_WAPKC_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_3072_WAPKC_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_SIGN_CRT_2048_WAPKC_SIZE : \ + MCUXCLRSA_SIGN_CRT_1024_WAPKC_SIZE))) ///< Macro to extract PKC workarea size to be used with a non-standard key length, with a key of type MCUXCLRSA_KEY_PRIVATECRT or MCUXCLRSA_KEY_PRIVATECRT_DFA. + +/** @} */ + +/****************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa Verify */ +/****************************************************************************/ +/** + * @defgroup MCUXCLRSA_VERIFY_WA MCUXCLRSA_VERIFY_WA + * @brief Definitions of workarea sizes for the mcuxClRsa Verify + * @ingroup mcuxClRsa_Macros + * @{ + */ + + +#define MCUXCLRSA_VERIFY_NOVERIFY_WACPU_SIZE (16u) ///< Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_NoVerify. +#define MCUXCLRSA_VERIFY_PSSVERIFY_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PssVerify. +#define MCUXCLRSA_VERIFY_PKCS1V15VERIFY_WACPU_SIZE (196u) ///< Definition of CPU workarea size for the mcuxClRsa_verify function using mode mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_*. + +#define MCUXCLRSA_VERIFY_1024_WAPKC_SIZE (800u) ///< Definition of PKC workarea size for the mcuxClRsa_verify function for 1024-bit keys. +#define MCUXCLRSA_VERIFY_2048_WAPKC_SIZE (1568u) ///< Definition of PKC workarea size for the mcuxClRsa_verify function for 2048-bit keys. +#define MCUXCLRSA_VERIFY_3072_WAPKC_SIZE (2336u) ///< Definition of PKC workarea size for the mcuxClRsa_verify function for 3072-bit keys. +#define MCUXCLRSA_VERIFY_4096_WAPKC_SIZE (3104u) ///< Definition of PKC workarea size for the mcuxClRsa_verify function for 4096-bit keys. +#define MCUXCLRSA_VERIFY_WAPKC_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_VERIFY_4096_WAPKC_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_VERIFY_3072_WAPKC_SIZE : \ + ((1024u < (keyBitLength)) ? MCUXCLRSA_VERIFY_2048_WAPKC_SIZE : \ + MCUXCLRSA_VERIFY_1024_WAPKC_SIZE))) ///< Macro to extract PKC workarea size to be used with a non-standard key length. + + + +/** @} */ + + +/**********************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function. */ +/**********************************************************************************/ +/** + * @defgroup MCUXCLRSA_KEYGENERATION_CRT_WA MCUXCLRSA_KEYGENERATION_CRT_WA + * @brief Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Crt function. + * @ingroup mcuxClRsa_Macros + * @{ + */ + +#ifdef MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG + +#define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE (56u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE (56u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE (56u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys + +#else + +#define MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE (632u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE (760u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE (888u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys + +#endif + +#define MCUXCLRSA_KEYGENERATION_CRT_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_3072_WACPU_SIZE : \ + MCUXCLRSA_KEYGENERATION_CRT_2048_WACPU_SIZE)) ///< Macro to extract CPU workarea size (in bytes) for the given key length. + +#define MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE (1656u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE (2424u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE (3192u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Crt function for 4096-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_4096_WAPKC_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_CRT_3072_WAPKC_SIZE : \ + MCUXCLRSA_KEYGENERATION_CRT_2048_WAPKC_SIZE)) ///< Macro to extract PKC workarea size (in bytes) for the given key length. + +/** @} */ + +/********************************************************************************/ +/* Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function. */ +/********************************************************************************/ +/** + * @defgroup MCUXCLRSA_KEYGENERATION_PLAIN_WA MCUXCLRSA_KEYGENERATION_PLAIN_WA + * @brief Definitions of workarea sizes for the mcuxClRsa_KeyGeneration_Plain function. + * @ingroup mcuxClRsa_Macros + * @{ + */ + +#ifdef MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG + +#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE (44u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE (44u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE (44u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys + +#else + +#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE (620u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE (748u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE (876u) ///< Definition of CPU workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys + +#endif + +#define MCUXCLRSA_KEYGENERATION_PLAIN_WACPU_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_4096_WACPU_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_3072_WACPU_SIZE : \ + MCUXCLRSA_KEYGENERATION_PLAIN_2048_WACPU_SIZE)) ///< Macro to extract CPU workarea size for the given key length. + +#define MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE (1832u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE (2728u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE (3624u) ///< Definition of PKC workarea size (in bytes) for the mcuxClRsa_KeyGeneration_Plain function for 4096-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE(keyBitLength) \ + ((3072u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_4096_WAPKC_SIZE : \ + ((2048u < (keyBitLength)) ? MCUXCLRSA_KEYGENERATION_PLAIN_3072_WAPKC_SIZE : \ + MCUXCLRSA_KEYGENERATION_PLAIN_2048_WAPKC_SIZE)) ///< Macro to extract PKC workarea size for the given key length. + +/** @} */ + +/*************************************************************************************************************************/ +/* Definitions of generated key data size for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. */ +/*************************************************************************************************************************/ +/** + * @defgroup MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE MCUXCLRSA_KEYGENERATION_KEY_DATA_SIZE + * @brief Definitions of bufer sizes for the mcuxClRsa_KeyGeneration_Crt and mcuxClRsa_KeyGeneration_Plain functions. + * @ingroup mcuxClRsa_Macros + * @{ + */ +#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_2048_SIZE (556u) ///< Definition of bufer size (in bytes) for the private plain key data for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_3072_SIZE (812u) ///< Definition of bufer size (in bytes) for the private plain key data for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_PLAIN_KEY_DATA_4096_SIZE (1068u) ///< Definition of bufer size (in bytes) for the private plain key data for 4096-bit keys + +#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_2048_SIZE (708u) ///< Definition of bufer size (in bytes) for the private CRT key data for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_3072_SIZE (1028u) ///< Definition of bufer size (in bytes) for the private CRT key data for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_CRT_KEY_DATA_4096_SIZE (1348u) ///< Definition of bufer size (in bytes) for the private CRT key data for 4096-bit keys + +#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_2048_SIZE (556u) ///< Definition of bufer size (in bytes) for the public key data for 2048-bit keys +#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_3072_SIZE (812u) ///< Definition of bufer size (in bytes) for the public key data for 3072-bit keys +#define MCUXCLRSA_KEYGENERATION_PUBLIC_KEY_DATA_4096_SIZE (1068u) ///< Definition of bufer size (in bytes) for the public key data for 4096-bit keys + +/** @} */ + + +#endif /* MCUXCLRSA_MEMORYCONSUMPTION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MillerRabinTest_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MillerRabinTest_FUP.h new file mode 100644 index 000000000..de146ebfb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_MillerRabinTest_FUP.h @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_MillerRabinTest_FUP.h +* @brief defines FUP programs byte arrays +*/ +#ifndef MCUXCLRSA_MILLERRABINTEST_FUP_H_ +#define MCUXCLRSA_MILLERRABINTEST_FUP_H_ +#include + +extern const mcuxClPkc_FUPEntry_t mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP[4]; + +#endif /* MCUXCLRSA_MILLERRABINTEST_FUP*/ diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_PrivateCrt_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_PrivateCrt_FUP.h new file mode 100644 index 000000000..1b67b5428 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_PrivateCrt_FUP.h @@ -0,0 +1,107 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_PrivateCrt_T1mb_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Calculate Mq_bm = Mq_b * QDash mod p_b */ + FUP_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* Mq_bm */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* QDash */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET3 /* Mq_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */), + /* Calculate T1_mb = Mp_bm - Mq_bm mod p_b */ + FUP_MC2_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* T1_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* Mp_bm */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* Mq_bm */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_PrivateCrt_T2T3T4mb_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Calculate T2_mb = QDash*qInv_b mod p_b */ + FUP_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* T2_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* QDash */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* qInv_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */), + /* Calculate T3_mb = QDash*R_qInv mod p_b */ + FUP_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* T3_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* QDash */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* R_qInv */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */), + /* Calculate qInv_bm = T2_mb-T3_mb mod p_b */ + FUP_MC2_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* qInv_bm */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* T2_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* T3_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */), + /* Calculate T4_mb = T1_mb*qInv_bm mod p_b */ + FUP_MC2_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* T4_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* T1_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* qInv_bm */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */), + /* Convert back into normal representation: T4_b = T4_mb mod p_b */ + FUP_MC2_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* T4_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* T4_mb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_PrivateCrt_CalcM_b_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Calculate T5_b = T4_b*q in MODT4 which has a size of + * (primeAlignLen + blindedPrimeAlignLen = blindedMessageAlignLen) + */ + FUP_MC1_PM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* T5_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* q */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* T4_b */), + /* For the following addition, move Mq_b to the bigger buffer N, + * which is used as a temporary buffer + */ + FUP_OP2_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_CONST0), + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* Mq_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET3 /* Mq_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_CONST0), + /* Calculate masked message M_b = T5_b + Mq_b */ + FUP_OP2_ADD(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3 /* M_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* T5_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* Mq_b */) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_PrivateCrt_CalcM1_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Calculate reduction M_br of M_b mod N */ + FUP_MC2_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* M_br */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3 /* M_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */), + /* Calculate message M1 = M_br * QDash mod N */ + FUP_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3 /* M1 */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 /* QDash */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* M_br */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */), + /* Normalize result (case if M1 > N) */ + FUP_MC1_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_M /* M */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3 /* M1 */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_PrivateCrt_ReductionME_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Convert from Montgomery to normal representation */ + FUP_MC1_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */), + /* Normalize the result (case if R > N) and copy to the temp buffer for C' */ + FUP_MC1_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* C' */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Public_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Public_FUP.h new file mode 100644 index 000000000..50412e0ec --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Public_FUP.h @@ -0,0 +1,29 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_Public_ReductionME_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + //Convert from Montgomery to normal representation + FUP_MC1_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N), + //Normalize the result (case if R > N) and copy to the output buffer + FUP_MC1_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_OUTPUT, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_RemoveBlinding_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_RemoveBlinding_FUP.h new file mode 100644 index 000000000..89384b306 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_RemoveBlinding_FUP.h @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_RemoveBlinding_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* Set T2 = 0 */ + FUP_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_ZERO), + /* Compute T1 = T2 + B */ + FUP_OP1_ADD_Z0(MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T1, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_B), + /* Compute T2 = T1 * X mod Nb (X in Montgomery representation, T2 and T1 in normal representation) */ + FUP_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T1, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_X, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_NB), + /* Normalize the result T1 = (T2 – Nb) mod Nb */ + FUP_MC1_MS(MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T1, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_NB, MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_NB) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPQDistance_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPQDistance_FUP.h new file mode 100644 index 000000000..ef574de7b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPQDistance_FUP.h @@ -0,0 +1,35 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_TestPQDistance_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + /* 1. Copy 100 MSbits of p in to buffer in PKC RAM */ + FUP_OP1_SHR(MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P100MSB, + MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P128MSB, + MCUXCLRSA_INTERNAL_TESTPQDISTANCE_CONSTANT28), + /* 2. Copy 100 MS bits of q into buffer in PKC RAM */ + FUP_OP1_SHR(MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q100MSB, + MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q128MSB, + MCUXCLRSA_INTERNAL_TESTPQDISTANCE_CONSTANT28), + /* + * 3. Compare 100 MSbits of p and q + * If they are equal, then function returns MCUXCLRSA_STATUS_INVALID_INPUT error code + * (primes do not meet the FIPS requirements). + */ + FUP_OP1_CMP(MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P100MSB, + MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q100MSB), +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPrimeCandidate_FUP.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPrimeCandidate_FUP.h new file mode 100644 index 000000000..d547137ff --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_TestPrimeCandidate_FUP.h @@ -0,0 +1,49 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +#include + +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_TestPrimeCandidate_Steps2_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0), + FUP_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0), //clear GCD2 + FUP_OP2_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_A0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0), //copy A0 to GCD2 + FUP_MC1_GCD(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2), + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT2) +); +MCUXCLPKC_FUP_EXT_ROM(mcuxClRsa_TestPrimeCandidate_Steps3_FUP, + PH_CLNS_UTILS_FAME_CRC_ENTRY, + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT1), + FUP_OP1_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_E, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0), + FUP_MC1_GCD(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2), + FUP_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT2) +); diff --git a/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Types.h b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Types.h new file mode 100644 index 000000000..cbdd24169 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/inc/mcuxClRsa_Types.h @@ -0,0 +1,192 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClRsa_Types.h + * @brief Type definitions for the mcuxClRsa component + */ + +#ifndef MCUXCLRSA_TYPES_H_ +#define MCUXCLRSA_TYPES_H_ + +#include +#include +#include +#include // Exported features flags header +#include +#include +#include + +/*********************************************************** + * MACROS + **********************************************************/ + +/** + * @defgroup mcuxClRsa_Macros mcuxClRsa_Macros + * @brief Defines all macros of @ref mcuxClRsa + * @ingroup mcuxClRsa + * @{ + */ + +/*********************************************************** + * MACROS RELATED TO FUNCTION STATUS + **********************************************************/ + +/** + * @defgroup MCUXCLRSA_STATUS_ MCUXCLRSA_STATUS_ + * @brief Return code definitions + * @ingroup mcuxClRsa_Macros + * @{ + */ +#define MCUXCLRSA_STATUS_SIGN_OK ((mcuxClRsa_Status_t) 0x0FF62E03u ) ///< RSA sign operation successful +#define MCUXCLRSA_STATUS_VERIFY_OK ((mcuxClRsa_Status_t) 0x0FF62E07u ) ///< RSA verify operation successful +#define MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK ((mcuxClRsa_Status_t) 0x0FF62E0Bu ) ///< RSA verify primitive operation (RSAVP1) successful +#define MCUXCLRSA_STATUS_ERROR ((mcuxClRsa_Status_t) 0x0FF65330u ) ///< Error occurred during RSA operation +#define MCUXCLRSA_STATUS_INVALID_INPUT ((mcuxClRsa_Status_t) 0x0FF653F8u ) ///< Input data cannot be processed +#define MCUXCLRSA_STATUS_VERIFY_FAILED ((mcuxClRsa_Status_t) 0x0FF68930u ) ///< Signature verification failed +#define MCUXCLRSA_STATUS_FAULT_ATTACK ((mcuxClRsa_Status_t) 0x0FF6F0F0u ) ///< Fault attack detected +#define MCUXCLRSA_STATUS_KEYGENERATION_OK ((mcuxClRsa_Status_t) 0x0FF62E0Fu ) ///< RSA key generation operation executed successfully +#define MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED ((mcuxClRsa_Status_t) 0x0FF68934u ) ///< RSA key generation exceeds the limit of iterations to generate a prime +#define MCUXCLRSA_STATUS_RNG_ERROR ((mcuxClRsa_Status_t) 0x0FF65338u ) ///< Random number (DRBG / PRNG) error (unexpected behavior) + +/** @} */ + + +/*********************************************************** + * MACROS RELATED TO RSA KEY + **********************************************************/ +/** + * @defgroup MCUXCLRSA_KEY_ MCUXCLRSA_KEY_ + * @brief Key type definitions + * @ingroup mcuxClRsa_Macros + * @{ + */ +#define MCUXCLRSA_KEY_PUBLIC (0xA5A5A5A5U) ///< RSA key type public +#define MCUXCLRSA_KEY_PRIVATEPLAIN (0x5A5A5A5AU) ///< RSA key type private plain +#define MCUXCLRSA_KEY_PRIVATECRT (0xB4B4B4B4U) ///< RSA key type private CRT +#define MCUXCLRSA_KEY_PRIVATECRT_DFA (0x4B4B4B4BU) ///< RSA key type private CRT, with which a fault-protected CRT operation is executed +/** @} */ + + +/*********************************************************** + * MACROS RELATED TO PUBLIC FUNCTIONS' OPTIONS + **********************************************************/ +/** + * @defgroup MCUXCLRSA_OPTION_ MCUXCLRSA_OPTION_ + * @brief Function options definitions + * @ingroup mcuxClRsa_Macros + * @{ + */ +#define MCUXCLRSA_OPTION_MESSAGE_PLAIN (0XA5U) ///< Option passing a plain message as input to the sign or verify operation. +#define MCUXCLRSA_OPTION_MESSAGE_DIGEST (0X5AU) ///< Option passing a message digest as input to the sign or verify operation. +#define MCUXCLRSA_OPTION_MESSAGE_MASK (MCUXCLRSA_OPTION_MESSAGE_PLAIN | MCUXCLRSA_OPTION_MESSAGE_DIGEST) ///< Mask to set option MESSAGE_PLAIN or MESSAGE_DIGEST +/** + * @} + * @} + */ + +/********************************************** + * TYPEDEFS + **********************************************/ + /** + * @defgroup mcuxClRsa_Types mcuxClRsa_Types + * @brief Defines all types of the @ref mcuxClRsa component + * @ingroup mcuxClRsa + * @{ + */ + +/*********************************************************** + * TYPES RELATED TO FUNCTION STATUS + **********************************************************/ + +/** + * @brief Type for RSA status codes + */ +typedef uint32_t mcuxClRsa_Status_t; + +/** + * @brief Deprecated type for RSA protected status codes + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_Status_Protected_t; + +/*********************************************************** + * TYPES RELATED TO RSA KEY + **********************************************************/ +/** + * @brief Structure type for Rsa key entries, specifying key entry length and data. + */ +typedef struct +{ + uint8_t* pKeyEntryData; ///< Pointer to buffer containing the key entry data in big-endian byte order + uint32_t keyEntryLength; ///< Byte-length of the buffer pointed to by pKeyEntryData +}mcuxClRsa_KeyEntry_t; + +/** + * @brief Pointer type to Rsa key entries. + */ +// TODO CLNS-6135: replace all occurrences of "mcuxClRsa_KeyEntry" by "mcuxClRsa_KeyEntry_t *", which is more explicit for a type +typedef mcuxClRsa_KeyEntry_t * mcuxClRsa_KeyEntry; + +/** + * @brief Structure type for Rsa key, specifying key type and key entries. + */ +typedef struct mcuxClRsa_Key +{ + uint32_t keytype; ///< Key type specifier: + ///< In case of an RSA public key this shall be set to @ref MCUXCLRSA_KEY_PUBLIC. + ///< In case of an RSA private plain key this shall be set to @ref MCUXCLRSA_KEY_PRIVATEPLAIN. + ///< In case of an RSA private CRT key this shall be set to @ref MCUXCLRSA_KEY_PRIVATECRT. + ///< In case of an RSA private CRT key, with which a fault-protected CRT operation is executed, this shall be set to @ref MCUXCLRSA_KEY_PRIVATECRT_DFA + mcuxClRsa_KeyEntry_t * pMod1; ///< Pointer to first key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC and @ref MCUXCLRSA_KEY_PRIVATEPLAIN the first key entry points to the public parameter modulus N. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT and @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the first key entry points to the private parameter prime factor P. + mcuxClRsa_KeyEntry_t * pMod2; ///< Pointer to second key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC and @ref MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT and @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the second key entry points to the private parameter prime factor Q. + mcuxClRsa_KeyEntry_t * pQInv; ///< Pointer to third key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC and @ref MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT and @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the third key entry points to the private parameter QInv = (1 / (Q % P)). + mcuxClRsa_KeyEntry_t * pExp1; ///< Pointer to fourth key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC the first exponent entry points to the public parameter exponent E. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATEPLAIN the first exponent entry points to the private parameter exponent D. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT and @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the first exponent entry points to the private parameter DP = D % (P-1). + mcuxClRsa_KeyEntry_t * pExp2; ///< Pointer to fifth key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC and @ref MCUXCLRSA_KEY_PRIVATEPLAIN this pointer shall be set to NULL. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT and @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the second exponent entry points to the private parameter DQ = D % (Q-1). + mcuxClRsa_KeyEntry_t * pExp3; ///< Pointer to sixth key entry: + ///< In case of @ref MCUXCLRSA_KEY_PUBLIC, @ref MCUXCLRSA_KEY_PRIVATEPLAIN, and @ref MCUXCLRSA_KEY_PRIVATECRT this pointer shall be set to NULL. + ///< In case of @ref MCUXCLRSA_KEY_PRIVATECRT_DFA the third exponent entry points to the public parameter exponent E. +} mcuxClRsa_Key; + + +/*********************************************************** + * TYPES RELATED TO SIGN / VERIFY FUNCTIONALITY + **********************************************************/ + +/** + * @brief Forward declaration of Sign/Verify mode struct. + */ +typedef struct mcuxClRsa_SignVerifyMode_t mcuxClRsa_SignVerifyMode_t; + +/** + * @brief Pointer type to Sign/Verify mode. + */ +typedef mcuxClRsa_SignVerifyMode_t * mcuxClRsa_SignVerifyMode; + +/** + * @} + */ + + +#endif /* MCUXCLRSA_TYPES_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD.c new file mode 100644 index 000000000..4ff39beb4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD.c @@ -0,0 +1,197 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_ComputeD.c + * @brief mcuxClRsa: function, which is called to compute private exponent d + * compliant with FIPS 186-4. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_ComputeD) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_ComputeD( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pP, + mcuxClRsa_KeyEntry_t * pQ, + mcuxClRsa_KeyEntry_t * pD, + const uint32_t keyBitLength + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_ComputeD); + + /* + * Initialization: + * - allocate buffers in PKC RAM + * - update session (PKC workarea used...) + */ + /* Size definitions */ + const uint32_t byteLenPQ = pP->keyEntryLength; // P and Q have the same byte length + const uint32_t primePQAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPQ); + + const uint32_t keyLen = byteLenPQ * 2u; // LCM have 2 times length of PQ + const uint32_t keyAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(keyLen); + + /* Memory layout: | PSub1 (primePQAlignLen) | QSub1 (primePQAlignLen) | nDash (FW) | Lcm (keyAlignLen) | Phi (keyAlignLen) | T (keyAlignLen+FW) */ + uint32_t bufferSizeTotal = (primePQAlignLen * 2u) /* PSub1, QSub1 */ + + (keyAlignLen * 3u) + 2u * MCUXCLRSA_PKC_WORDSIZE /* Ndsah+Lcm, Phi, T */; + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, bufferSizeTotal / (sizeof(uint32_t))); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_ComputeD, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + uint8_t *pPSub1 = pPkcWorkarea; + uint8_t *pQSub1 = pPSub1 + primePQAlignLen; + uint8_t *pLcm = pQSub1 + primePQAlignLen + MCUXCLRSA_PKC_WORDSIZE /* offset for Ndsah */; + uint8_t *pPhi = pLcm + keyAlignLen; + uint8_t *pT = pPhi + keyAlignLen; + + /* Setup UPTR table */ + const uint32_t cpuWaSizeWord = MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(MCUXCLRSA_INTERNAL_COMPD_UPTRT_SIZE * (sizeof(uint16_t))) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_ComputeD, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_P] = MCUXCLPKC_PTR2OFFSET(pP->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_Q] = MCUXCLPKC_PTR2OFFSET(pQ->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_D] = MCUXCLPKC_PTR2OFFSET(pD->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_E] = MCUXCLPKC_PTR2OFFSET(pE->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PSUB1] = MCUXCLPKC_PTR2OFFSET(pPSub1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1] = MCUXCLPKC_PTR2OFFSET(pQSub1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_LCM] = MCUXCLPKC_PTR2OFFSET(pLcm); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI] = MCUXCLPKC_PTR2OFFSET(pPhi); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_T] = MCUXCLPKC_PTR2OFFSET(pT); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_CONSTANT] = 1u; + + /* Backup Ps1 length and UPTRT to recover in the end */ + uint16_t *pUptrtBak = MCUXCLPKC_GETUPTRT(); + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + /* Set UPTRT table */ + MCUXCLPKC_WAITFORFINISH(); + MCUXCLPKC_SETUPTRT(pOperands); + + /* + * call the FUP code to do the below steps + * 1. Compute p' = p-1 + * 2. Compute q' = q-1 + * 3. Compute lcm(p-1, q-1)=|(p-1)(q-1)|/gcd(p-1,q-1) + * 3.1 Compute a = (p-1)(q-1) + * 3.2 Compute b = gcd(p-1,q-1) + */ + MCUXCLPKC_PS1_SETLENGTH(primePQAlignLen, primePQAlignLen); + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_ComputeD_Steps123_FUP, + mcuxClRsa_ComputeD_Steps123_FUP_LEN); + MCUXCLPKC_WAITFORFINISH(); + uint32_t leadingZeroN; + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1, &leadingZeroN)); + uint32_t realGcdByteLen = primePQAlignLen - (leadingZeroN >> 3u); + + /* + * 3.3 Compute lcm(p-1, q-1)= a/b + * + * Used functions: mcuxClMath_ExactDivide + */ + MCUXCLPKC_PS1_SETLENGTH(keyAlignLen, keyAlignLen); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_LCM, 0u); + MCUXCLPKC_WAITFORFINISH(); + MCUXCLMATH_FP_EXACTDIVIDE(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_LCM, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_QSUB1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_T, + MCUXCLRSA_PKC_ROUNDUP_SIZE(keyLen), + MCUXCLRSA_PKC_ROUNDUP_SIZE(realGcdByteLen)); + + /* + * 4. Compute d := e^(-1) mod lcm(p-1, q-1) + * + * Used functions: mcuxClRsa_ModInv + */ + + MCUXCLPKC_PS1_SETLENGTH(keyAlignLen, keyAlignLen); + const uint32_t eAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(pE->keyEntryLength); + MCUXCLPKC_PS2_SETLENGTH(0, eAlignLen); + /* Clear the PHI buffer */ + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, 0u); + /* Copy e to the PHI buffer (the content pointed by pE should not be destroyed) */ + MCUXCLPKC_FP_CALC_OP2_OR_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_E, 0u); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClRsa_ModInv(MCUXCLPKC_PACKARGS4(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_D, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_LCM, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_T))); + //don't need check the return value, it always return ok + + /* + * 5. Determine the length of d without leading zeros + */ + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_LeadingZeros(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_D, &leadingZeroN)); + pD->keyEntryLength = keyAlignLen - (leadingZeroN >> 3u); + + /* + * 6. Verify FIPS 186-4 condition on lower bound of d + * If d <= 2^(nlen/2), then function returns MCUXCLRSA_STATUS_INVALID_INPUT error. + * + * Used functions: FAME operation. + */ + /* Clear buffers phi, its length is nlen */ + MCUXCLPKC_PS1_SETLENGTH(0u, keyAlignLen); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, 0u); + MCUXCLPKC_WAITFORFINISH(); + + uint32_t idx = (keyBitLength >> 1u) >> 3u; + uint32_t lowBoundByte = ((uint32_t)1u << ((keyBitLength >> 1u) & 7u)); + pPhi[idx] = (uint8_t)lowBoundByte; + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_PHI, MCUXCLRSA_INTERNAL_UPTRTINDEX_COMPD_D); + MCUXCLPKC_WAITFORFINISH(); + + /* Recover session, Ps1 length and Uptrt */ + mcuxClSession_freeWords_pkcWa(pSession, bufferSizeTotal / (sizeof(uint32_t))); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + MCUXCLPKC_SETUPTRT(pUptrtBak); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_ComputeD, + ((MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) ? MCUXCLRSA_STATUS_INVALID_INPUT : MCUXCLRSA_STATUS_KEYGENERATION_OK), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivide), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP2_OR_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_ModInv), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_LeadingZeros), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP + ); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD_FUP.c new file mode 100644 index 000000000..daacc9022 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ComputeD_FUP.c @@ -0,0 +1,28 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_ComputeD_Steps123_FUP[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x3bu,0x6du,0xecu,0xd6u},{0x00u,0x1bu,0x00u,0x00u,0x09u,0x04u},{0x00u,0x1bu,0x00u,0x01u,0x09u,0x05u},{0x80u,0x13u,0x04u,0x05u,0x00u,0x06u},{0x80u,0xa7u,0x04u,0x04u,0x05u,0x05u},{0x00u,0x14u,0x00u,0x05u,0x09u,0x05u}}; + + +/* + * FUP code to do the below steps + * 1. Compute p' = p-1 + * 2. Compute q' = q-1 + * 3. Compute lcm(p−1, q−1)=|(p−1)(q−1)|/gcd(p-1,q−1) + * 3.1 Compute a = (p−1)(q−1) + * 3.2 Compute b = gcd(p-1,q−1) + */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_GenerateProbablePrime.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_GenerateProbablePrime.c new file mode 100644 index 000000000..ce4735c79 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_GenerateProbablePrime.c @@ -0,0 +1,191 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_GenerateProbablePrime.c + * @brief mcuxClRsa: function, which is called to generates probably prime number + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_GenerateProbablePrime) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_GenerateProbablePrime( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pPrimeCandidate, + const uint32_t keyBitLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_GenerateProbablePrime, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)); + + mcuxClRsa_Status_t status = MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED; + uint32_t loopCounter = 0u; + const uint32_t loopMax = 5u * (keyBitLength / 2u); + uint32_t cntRandomGen = 0u; + uint32_t cntTestPrime = 0u; + + /* Little-endian representation of 0xb504f333f9de6485u, which is 64 most significant bits of sqrt(2)(2^(nlen/2)-1) rounded up */ + static const uint8_t numToCompare[] = {0x85u, 0x64u, 0xDEu, 0xF9u, 0x33u, 0xF3u, 0x04u, 0xB5u}; + /* Little-endian representation of 0xC0CFD797u, which is the product of the first 9 prime numbers starting from 3*/ + static const uint8_t a0[] = {0x97u, 0xD7u, 0xCFu, 0xC0u}; + + /* + * Initialization: + * - allocate buffers in PKC RAM + * - copy 0xb504f333f9de6485u value into buffer located in PKC RAM + * - copy A0 value into buffer located in PKC RAM + * - update session (PKC workarea used...) + */ + + const uint32_t pkcWaSizeWord = (2u * MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t)); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_GenerateProbablePrime, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + uint8_t *pNumToCompare = pPkcWorkarea; + uint8_t *pA0 = pPkcWorkarea + MCUXCLRSA_PKC_WORDSIZE; + + /* Setup UPTR table */ + const uint32_t cpuWaSizeWord = MCUXCLRSA_INTERNAL_GENERATEPROBABLEPRIME_WACPU_SIZE_WO_TESTPRIME_AND_MILLERRABIN(keyBitLength/8u/2u) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_GenerateProbablePrime, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_NUMTOCOMPARE] = MCUXCLPKC_PTR2OFFSET(pNumToCompare); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_A0] = MCUXCLPKC_PTR2OFFSET(pA0); + const uint32_t iNumToCmp_iA0 = ((uint32_t)MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_NUMTOCOMPARE << 8u) | MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_A0; + + /* Backup Ps1 length and UPTRT, restore them when returning */ + uint16_t *bakUPTRT = MCUXCLPKC_GETUPTRT(); + uint32_t bakPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + uint32_t bakPs2LenReg = MCUXCLPKC_PS2_GETLENGTH_REG(); + + /* Set UPTRT table */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(pOperands); + + MCUXCLPKC_PS1_SETLENGTH(0u, MCUXCLRSA_PKC_WORDSIZE); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_NUMTOCOMPARE, 0u); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_GENPRIME_A0, 0u); + MCUXCLPKC_WAITFORFINISH(); + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy(pNumToCompare + MCUXCLRSA_PKC_WORDSIZE - sizeof(numToCompare), + numToCompare, sizeof(numToCompare), sizeof(numToCompare))); + + MCUXCLMEMORY_FP_MEMORY_COPY(pA0, a0, sizeof(a0)); + + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + uint8_t * pPrimeKeyDataCpu = (uint8_t*) pOperands + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_GENPRIME_UPTRT_SIZE * sizeof(uint16_t))); +#endif + + do + { + /* + * Generate a random prime candidate for given key size using DRBG: + * - Ensure that prime candidate is odd; + * - Ensure that prime candidate is congruent 3 mod 4 (this deviation from FIPS 186-4 has been approved). + * + * The session pointed to by pSession shall be initialized with the entropy level (security strength) + * in accordance with the value of keyBitLength, as specified in SP 800-57, Part 1. + * + * Used functions: RNG provided through the pSession + */ + cntRandomGen++; +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + MCUX_CSSL_FP_FUNCTION_CALL(retRandomGen, mcuxClRandom_generate(pSession, pPrimeKeyDataCpu, pPrimeCandidate->keyEntryLength)); + if(MCUXCLRANDOM_STATUS_OK != retRandomGen) + { + status = MCUXCLRSA_STATUS_RNG_ERROR; + break; + } + MCUXCLMEMORY_FP_MEMORY_COPY(pPrimeCandidate->pKeyEntryData, pPrimeKeyDataCpu, pPrimeCandidate->keyEntryLength); + +#else + MCUX_CSSL_FP_FUNCTION_CALL(retRandomGen, mcuxClRandom_generate(pSession, pPrimeCandidate->pKeyEntryData, pPrimeCandidate->keyEntryLength)); + if (MCUXCLRANDOM_STATUS_OK != retRandomGen) + { + status = MCUXCLRSA_STATUS_RNG_ERROR; + break; + } +#endif + pPrimeCandidate->pKeyEntryData[0] |= 0x03u; + + cntTestPrime++; + MCUX_CSSL_FP_FUNCTION_CALL(retTest, mcuxClRsa_TestPrimeCandidate(pSession, pE, pPrimeCandidate, keyBitLength, iNumToCmp_iA0)); +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + if ((MCUXCLRSA_STATUS_KEYGENERATION_OK == retTest) || (MCUXCLRSA_STATUS_RNG_ERROR == retTest) || (MCUXCLRSA_STATUS_ERROR == retTest)) +#else + if ((MCUXCLRSA_STATUS_KEYGENERATION_OK == retTest) || (MCUXCLRSA_STATUS_RNG_ERROR == retTest)) +#endif + { + status = retTest; + break; + } + else if (MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_CMP_FAILED != retTest) + { + loopCounter++; + } + else + { + /* Do nothing to meet MISRA */ + } + } while(loopCounter < loopMax); + + /* Recover session, Ps1 length and Uptrt */ + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + MCUXCLPKC_PS1_SETLENGTH_REG(bakPs1LenReg); + MCUXCLPKC_PS2_SETLENGTH_REG(bakPs2LenReg); + MCUXCLPKC_SETUPTRT(bakUPTRT); + +/* Check define outside of macro so the MISRA rule 20.6 does not get violated */ +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_GenerateProbablePrime, status, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) * cntRandomGen, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) * cntRandomGen, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_TestPrimeCandidate) * cntTestPrime); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_GenerateProbablePrime, status, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) * cntRandomGen, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_TestPrimeCandidate) * cntTestPrime); +#endif + +} + diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt.c new file mode 100644 index 000000000..a6708d5f6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt.c @@ -0,0 +1,638 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_KeyGeneration_Crt.c + * @brief mcuxClRsa: implementation of RSA key generation function + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifdef MCUXCL_FEATURE_RSA_STRENGTH_CHECK +#define MCUXCLRSA_KEYGEN_CRT_FP_SECSTRENGTH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) +#else +#define MCUXCLRSA_KEYGEN_CRT_FP_SECSTRENGTH (0u) +#endif + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_KeyGeneration_Crt) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Crt( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_KeyGeneration_Crt); + + const uint32_t backup_cpuWaUsed = mcuxClSession_getUsage_cpuWa(pSession); + const uint32_t backup_pkcWaUsed = mcuxClSession_getUsage_pkcWa(pSession); + + /* + * 1. Check the key type, i.e.: + * - algorithm IDs + * - key sizes (it should be 1024, 2048, 3072, 4096, 6144 or 8192). + * + * If did not pass verification, function returns MCUXCLRSA_STATUS_INVALID_INPUT error. + * + */ + const uint32_t bitLenKey = type->size; + if(((MCUXCLKEY_ALGO_ID_RSA | MCUXCLKEY_ALGO_ID_KEY_PAIR) != type->algoId) + || ((MCUXCLKEY_SIZE_2048 != bitLenKey) + && (MCUXCLKEY_SIZE_3072 != bitLenKey) + && (MCUXCLKEY_SIZE_4096 != bitLenKey) + )) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /* + * 2. Check entropy provided by RNG + * If the RNG does not provide an appropriate level of entropy (security strength) + * for the given key size, this function returns MCUXCLRSA_STATUS_RNG_ERROR error. + */ +#ifdef MCUXCL_FEATURE_RSA_STRENGTH_CHECK + uint32_t securityStrength = MCUXCLRSA_GET_MINIMUM_SECURITY_STRENGTH(bitLenKey); + MCUX_CSSL_FP_FUNCTION_CALL(ret_checkSecurityStrength, mcuxClRandom_checkSecurityStrength(pSession, securityStrength)); + if(MCUXCLRANDOM_STATUS_OK != ret_checkSecurityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength)); + } +#endif + + /* + * 3. Check if E is FIPS compliant, i.e., is odd values in the range 2^16 < e < 2^256, + * determine the length without leading zeros. + * If did not pass verification, function returns MCUXCLRSA_STATUS_INVALID_INPUT error. + */ + mcuxClRsa_KeyEntry_t * pPublicExponent = (mcuxClRsa_KeyEntry_t *) type->info; + uint32_t byteLenE; + MCUX_CSSL_FP_FUNCTION_CALL(retVal_VerifyE, mcuxClRsa_VerifyE(pPublicExponent, &byteLenE)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_VerifyE) + { +#if defined(MCUXCL_FEATURE_RSA_STRENGTH_CHECK) + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE)); +#endif + } + + /* 4. Initialize PKC. */ + const uint32_t cpuWaSizeWord = MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + /* Session buffer is 32 bit aligned */ + mcuxClPkc_State_t * pPkcStateBackup = (mcuxClPkc_State_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + if (NULL == pPkcStateBackup) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, pPkcStateBackup, mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + /* + * 5. Allocate buffers in PKC RAM + * - size aligned to FAME word + * - they are be stored in little-endian byte order + */ + const uint32_t byteLenKey = bitLenKey / 8u; + const uint32_t pkcByteLenKey = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenKey); + const uint32_t byteLenPrime = byteLenKey / 2u; + const uint32_t pkcByteLenPrime = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPrime); + + const uint16_t bufferSizePQb = (uint16_t)pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE; + + /* Allocate space in session for p, q and e for now */ + const uint32_t pkcWaSizeWord = (pkcByteLenPrime + (pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE) * 2u) / (sizeof(uint32_t)); + uint8_t * pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + uint8_t * pPkcBufferE = pPkcWorkarea; + uint8_t * pPkcBufferP = pPkcBufferE + pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE /* offset for Ndash before p */; + uint8_t * pPkcBufferQ = pPkcBufferP + pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE /* offset for Ndash before q */; + /* dp, dq, qinv should be operand size add one PCK word */ + uint8_t * pPkcBufferDp = pPkcBufferQ + pkcByteLenPrime; + uint8_t * pPkcBufferDq = pPkcBufferDp + bufferSizePQb; + uint8_t * pPkcBufferQinv = pPkcBufferDq + bufferSizePQb; + uint8_t * pPkcBufferT1 = pPkcBufferQinv + bufferSizePQb; + uint8_t * pPkcBufferT2 = pPkcBufferT1 + bufferSizePQb; + uint8_t * pPkcBufferT3 = pPkcBufferT2 + MCUXCLRSA_PKC_WORDSIZE + bufferSizePQb; /* offset for Ndash before modulus */ + + /* Setup UPTR table. */ + const uint32_t uptrtSizeWord = MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(MCUXCLRSA_INTERNAL_KEYGENERATION_CRT_UPTRT_SIZE * (sizeof(uint16_t))) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, uptrtSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_SETUPTRT(pOperands); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P] = MCUXCLPKC_PTR2OFFSET(pPkcBufferP); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q] = MCUXCLPKC_PTR2OFFSET(pPkcBufferQ); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DP] = MCUXCLPKC_PTR2OFFSET(pPkcBufferDp); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DQ] = MCUXCLPKC_PTR2OFFSET(pPkcBufferDq); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E] = MCUXCLPKC_PTR2OFFSET(pPkcBufferE); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_QINV] = MCUXCLPKC_PTR2OFFSET(pPkcBufferQinv); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1] = MCUXCLPKC_PTR2OFFSET(pPkcBufferT1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2] = MCUXCLPKC_PTR2OFFSET(pPkcBufferT2); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3] = MCUXCLPKC_PTR2OFFSET(pPkcBufferT3); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT0] = 0u; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_CONSTANT1] = 1u; + + /* + * 6. Copy E to PKC RAM. + * It is stored in little-endian byte order (copied with reverse order and without leading zeros). + * + * Used functions: mcuxClPkc_ImportBigEndianToPkc + */ + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenPrime, pkcByteLenPrime); + uint32_t leadingZerosE = pPublicExponent->keyEntryLength - byteLenE; + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E, pPublicExponent->pKeyEntryData + leadingZerosE, byteLenE); + + mcuxClRsa_KeyEntry_t e; + e.keyEntryLength = byteLenE; + e.pKeyEntryData = pPkcBufferE; + + /* + * 7. Generate prime p. + * Continuation if mcuxClRsa_GenerateProbablePrime returns MCUXCLRSA_STATUS_KEYGENERATION_OK, + * otherwise function ends with MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED or error. + * + * Used functions: mcuxClRsa_GenerateProbablePrime + */ + mcuxClRsa_KeyEntry_t p; + p.pKeyEntryData = pPkcBufferP; + p.keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(retVal_GenerateProbablePrime_P, mcuxClRsa_GenerateProbablePrime(pSession, &e, &p, bitLenKey)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_GenerateProbablePrime_P) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + + if(MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED == retVal_GenerateProbablePrime_P) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, + MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED, + MCUXCLRSA_KEYGEN_CRT_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, retVal_GenerateProbablePrime_P); + } + } + + /* + * 8. Generate prime q. + * Continuation if mcuxClRsa_GenerateProbablePrime returns MCUXCLRSA_STATUS_KEYGENERATION_OK, + * otherwise function ends with MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED or error. + * + * Used functions: mcuxClRsa_GenerateProbablePrime + */ + mcuxClRsa_KeyEntry_t q; + q.pKeyEntryData = pPkcBufferQ; + q.keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(retVal_GenerateProbablePrime_Q, mcuxClRsa_GenerateProbablePrime(pSession, &e, &q, bitLenKey)); + + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_GenerateProbablePrime_Q) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + if(MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED == retVal_GenerateProbablePrime_Q) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, + MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED, + MCUXCLRSA_KEYGEN_CRT_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, retVal_GenerateProbablePrime_Q); + } + } + + /* + * 9. Check if |p - q| <= 2^(nlen/2 - 100) + * Continuation if mcuxClRsa_TestPQDistance function returns MCUXCLRSA_STATUS_KEYGENERATION_OK + * otherwise function ends with MCUXCLRSA_STATUS_ERROR error code. + * + * Used functions: mcuxClRsa_TestPQDistance + * + * NOTE: This is a deviation from the method specified in the FIPS 186-4, where this check is performed while generating the prime q + * (see step 5.4 in Appendix B.3.3). + * The @ref mcuxClRsa_GenerateProbablePrime function does not perform this check, it is done after generating p and q. + * For this reason, if p and q does not meet this FIPS requirements, no new prime q number will be generated. Instead + * of function ends with error. + * Rationale of this deviation: + * This check will fail if at least 100 most significant bits of p and q are identical. This can happen + * with very low probability and it's usually treated as a hardware failure. + */ + MCUX_CSSL_FP_FUNCTION_CALL( + retVal_TestPQDistance, + mcuxClRsa_TestPQDistance( + MCUXCLPKC_PACKARGS4( + 0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pkcByteLenPrime)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_TestPQDistance) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + + + /* + * 10. Compute dp := e^(-1) mod (p-1) + * + * Used functions: mcuxClRsa_ModInv + */ + + /* Update session about space for dp, dq, qInv, T1, T2, and T3 buffers */ + if (NULL == mcuxClSession_allocateWords_pkcWa(pSession, + (6u * (pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE) + MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t))) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_KeyGeneration_Crt_Steps10_FUP, + mcuxClRsa_KeyGeneration_Crt_Steps10_FUP_LEN); + MCUXCLPKC_WAITFORREADY(); + MCUX_CSSL_FP_FUNCTION_CALL_VOID( + mcuxClRsa_ModInv( + MCUXCLPKC_PACKARGS4( + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DP, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1))); + + /* + * 11. Compute dq := e^(-1) mod (q-1) + * + * Used functions: mcuxClRsa_ModInv + */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_KeyGeneration_Crt_Steps11_FUP, + mcuxClRsa_KeyGeneration_Crt_Steps11_FUP_LEN); + MCUXCLPKC_WAITFORREADY(); + MCUX_CSSL_FP_FUNCTION_CALL_VOID( + mcuxClRsa_ModInv( + MCUXCLPKC_PACKARGS4( + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DQ, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1))); + + /* + * 12. Compute qInv := q^(-1) mod p + * + * Used functions: mcuxClMath_ModInv + */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_KeyGeneration_Crt_Steps12_FUP, + mcuxClRsa_KeyGeneration_Crt_Steps12_FUP_LEN); + MCUXCLPKC_WAITFORREADY(); + /* Calculate NDash of p */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1); + MCUX_CSSL_FP_FUNCTION_CALL_VOID( + mcuxClMath_ModInv( + MCUXCLPKC_PACKARGS4( + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_QINV, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1))); + + /* + * 13. Compute n := p*q + * + * Used functions: FAME Plain Multiplication + */ + + /* Free up space for T1, T2, and T3 buffers */ + mcuxClSession_freeWords_pkcWa(pSession, (3u * (pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE) + MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t))); + /* Update session about space for N buffer */ + if (NULL == mcuxClSession_allocateWords_pkcWa(pSession, + pkcByteLenKey / (sizeof(uint32_t))) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* Set buffer and operand for N */ + uint8_t * pPkcBufferN = pPkcBufferQinv + bufferSizePQb; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_N] = MCUXCLPKC_PTR2OFFSET(pPkcBufferN); + + /* Compute n := p*q */ + MCUXCLPKC_FP_CALC_MC1_PM( + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_N, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q); + MCUXCLPKC_WAITFORFINISH(); + + /* + * 14. Write public key (computed n, e) to the buffer pointed by pPubData. + * This buffer contains RSA key (mcuxClRsa_Key data type, i.e.: key type and key entries) + * followed by the key data, i.e.: n, e. + * Key entries stored in big-endian byte order (copy with reverse order). + * + * Used functions: mcuxClPkc_ExportBigEndianFromPkc (to export n and e). + */ + + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClRsa_Key *pRsaPubKey = (mcuxClRsa_Key *) pPubData; + pRsaPubKey->keytype = MCUXCLRSA_KEY_PUBLIC; + *pPubDataLength = sizeof(mcuxClRsa_Key); + + pRsaPubKey->pMod1 = (mcuxClRsa_KeyEntry_t *) (pPubData + *pPubDataLength); + *pPubDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPubKey->pMod2 = NULL; + pRsaPubKey->pQInv = NULL; + + pRsaPubKey->pExp1 = (mcuxClRsa_KeyEntry_t *) (pPubData + *pPubDataLength); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + *pPubDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPubKey->pExp2 = NULL; + pRsaPubKey->pExp3 = NULL; + + pRsaPubKey->pMod1->pKeyEntryData = pPubData + *pPubDataLength; + pRsaPubKey->pMod1->keyEntryLength = byteLenKey; + + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC( + pRsaPubKey->pMod1->pKeyEntryData, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_N, + pRsaPubKey->pMod1->keyEntryLength); + *pPubDataLength += pRsaPubKey->pMod1->keyEntryLength; + + pRsaPubKey->pExp1->pKeyEntryData = pPubData + *pPubDataLength; + pRsaPubKey->pExp1->keyEntryLength = e.keyEntryLength; + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC( + pRsaPubKey->pExp1->pKeyEntryData, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_E, + pRsaPubKey->pExp1->keyEntryLength); + *pPubDataLength += pRsaPubKey->pExp1->keyEntryLength; + + /* + * 15. Write RSA CRT key (p, q, qInv, dp, dq) to the buffer pointed by pPrivData. + * This buffer contains RSA key (mcuxClRsa_Key data type, i.e.: key type and key entries) + * followed by the key data, i.e.: p, q, qInv, dp, dq. + * Key entries stored in big-endian byte order (copy with reverse order). + * + * Used functions: mcuxClPkc_SecureExportBigEndianFromPkc + */ + + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClRsa_Key *pRsaPrivCrtKey = (mcuxClRsa_Key *) pPrivData; + + pRsaPrivCrtKey->keytype = MCUXCLRSA_KEY_PRIVATECRT; + *pPrivDataLength = sizeof(mcuxClRsa_Key); + + + pRsaPrivCrtKey->pMod1 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivCrtKey->pMod2 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivCrtKey->pQInv = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivCrtKey->pExp1 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivCrtKey->pExp2 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivCrtKey->pExp3 = NULL; + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + pRsaPrivCrtKey->pMod1->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivCrtKey->pMod1->keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportP, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivCrtKey->pMod1->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pRsaPrivCrtKey->pMod1->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportP) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivCrtKey->pMod1->keyEntryLength; + + pRsaPrivCrtKey->pMod2->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivCrtKey->pMod2->keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportQ, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivCrtKey->pMod2->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pRsaPrivCrtKey->pMod2->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportQ) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivCrtKey->pMod2->keyEntryLength; + + pRsaPrivCrtKey->pQInv->pKeyEntryData = pPrivData + *pPrivDataLength;; + pRsaPrivCrtKey->pQInv->keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportQinv, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivCrtKey->pQInv->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_QINV, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pRsaPrivCrtKey->pQInv->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportQinv) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivCrtKey->pQInv->keyEntryLength; + + pRsaPrivCrtKey->pExp1->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivCrtKey->pExp1->keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportDp, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivCrtKey->pExp1->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DP, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pRsaPrivCrtKey->pExp1->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportDp) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivCrtKey->pExp1->keyEntryLength; + + pRsaPrivCrtKey->pExp2->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivCrtKey->pExp2->keyEntryLength = byteLenPrime; + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportDq, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivCrtKey->pExp2->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_DQ, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_T1), + pRsaPrivCrtKey->pExp2->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportDq) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivCrtKey->pExp2->keyEntryLength; + + /* + * 16. Initialization of key handles for public and private key + * a. copy key protection into handle + * b. initialize the key type in handle: + * -set type->algoId to RSA + public/private + * -set length of the key in type->size + * -set type->info to NULL + * c. set pSrcKeyData to point to the start of the provided buffer + * d. set dstKey.loadLocation to MCUXCLKEY_LOADSTATUS_NOTLOADED + * e. set other fields of dstKey to zero + */ + mcuxClKey_Descriptor_t * pPubKey = (mcuxClKey_Descriptor_t *) pubKey; + mcuxClKey_setProtectionType(pPubKey, protection); + // TODO CLNS-5165: move the generation of these types into the key component - TBD with architects, is this still what we want to do? + mcuxClKey_TypeDescriptor_t keyType_public = { MCUXCLKEY_ALGO_ID_RSA ^ MCUXCLKEY_ALGO_ID_PUBLIC_KEY, type->size, NULL }; + mcuxClKey_setTypeDescriptor(pPubKey, keyType_public); + mcuxClKey_setKeyData(pPubKey, pPubData); + mcuxClKey_setLoadStatus(pPubKey, MCUXCLKEY_LOADSTATUS_NOTLOADED); + mcuxClKey_setLoadedKeyData(pPubKey, NULL); + mcuxClKey_setLoadedKeySlot(pPubKey, 0u); + + mcuxClKey_Descriptor_t * pPrivKey = (mcuxClKey_Descriptor_t *) privKey; + mcuxClKey_setProtectionType(pPrivKey, protection); + // TODO CLNS-5165: move the generation of these types into the key component + mcuxClKey_TypeDescriptor_t keyType_private = { MCUXCLKEY_ALGO_ID_RSA ^ MCUXCLKEY_ALGO_ID_PRIVATE_KEY, type->size, NULL }; + mcuxClKey_setTypeDescriptor(pPrivKey, keyType_private); + mcuxClKey_setKeyData(pPrivKey, pPrivData); + mcuxClKey_setLoadStatus(pPrivKey, MCUXCLKEY_LOADSTATUS_NOTLOADED); + mcuxClKey_setLoadedKeyData(pPrivKey, NULL); + mcuxClKey_setLoadedKeySlot(pPrivKey, 0u); + + /* Create link between private and public key handles */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_linkKeyPair, mcuxClKey_linkKeyPair(pSession, privKey, pubKey)); + if (MCUXCLKEY_STATUS_OK != ret_linkKeyPair) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_ERROR); + } + + /* Clear PKC workarea. */ + uint32_t pkcWaSize = MCUXCLRSA_KEYGENERATION_CRT_WAPKC_SIZE(bitLenKey); + MCUXCLPKC_PS1_SETLENGTH(0u, pkcWaSize); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_CRT_P, 0u); + + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Crt, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRsa_KeyGeneration_Crt, + MCUXCLRSA_STATUS_KEYGENERATION_OK, + MCUXCLRSA_STATUS_FAULT_ATTACK, + MCUXCLRSA_KEYGEN_CRT_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_TestPQDistance), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_ModInv), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + MCUXCLPKC_FP_CALLED_CALC_MC1_PM, + 5u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportBigEndianFromPkc), + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_linkKeyPair), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt_FUP.c new file mode 100644 index 000000000..1b0c97b34 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Crt_FUP.c @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps10_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xc4u,0xd2u,0x1du,0xf3u},{0x00u,0x1bu,0x00u,0x01u,0x0bu,0x09u},{0x00u,0x1eu,0x00u,0x00u,0x0au,0x08u}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps11_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xc4u,0xd2u,0x1du,0xf0u},{0x00u,0x1bu,0x00u,0x02u,0x0bu,0x09u},{0x00u,0x1eu,0x00u,0x00u,0x0au,0x08u}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_KeyGeneration_Crt_Steps12_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xfbu,0xe7u,0x09u,0x32u},{0x00u,0x1eu,0x00u,0x01u,0x0au,0x09u},{0x00u,0x1eu,0x00u,0x02u,0x0au,0x08u}}; + + +/* + * FUP to compute p - 1 and copy E + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* + * FUP to compute q - 1 and copy E + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* + * FUP to copy p and q + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Plain.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Plain.c new file mode 100644 index 000000000..5abc3b28c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_KeyGeneration_Plain.c @@ -0,0 +1,517 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_KeyGeneration_Plain.c + * @brief mcuxClRsa: implementation of RSA key generation function + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +#ifdef MCUXCL_FEATURE_RSA_STRENGTH_CHECK +#define MCUXCLRSA_KEYGEN_PLAIN_FP_SECSTRENGTH MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength) +#else +#define MCUXCLRSA_KEYGEN_PLAIN_FP_SECSTRENGTH (0u) +#endif + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_KeyGeneration_Plain) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_KeyGeneration_Plain( + mcuxClSession_Handle_t pSession, + mcuxClKey_Type_t type, + mcuxClKey_Protection_t protection, + mcuxClKey_Handle_t privKey, + uint8_t * pPrivData, + uint32_t * const pPrivDataLength, + mcuxClKey_Handle_t pubKey, + uint8_t * pPubData, + uint32_t * const pPubDataLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_KeyGeneration_Plain); + + const uint32_t backup_cpuWaUsed = mcuxClSession_getUsage_cpuWa(pSession); + const uint32_t backup_pkcWaUsed = mcuxClSession_getUsage_pkcWa(pSession); + + /* + * 1. Check the key type, i.e.: + * - algorithm IDs + * - key sizes (it should be 1024, 2048, 3072, 4096, 6144 or 8192). + * + * If did not pass verification, function returns MCUXCLRSA_STATUS_INVALID_INPUT error. + * + */ + const uint32_t bitLenKey = type->size; + if(((MCUXCLKEY_ALGO_ID_RSA | MCUXCLKEY_ALGO_ID_KEY_PAIR) != type->algoId) + || ((MCUXCLKEY_SIZE_2048 != bitLenKey) + && (MCUXCLKEY_SIZE_3072 != bitLenKey) + && (MCUXCLKEY_SIZE_4096 != bitLenKey) + )) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /* + * 2. Check entropy provided by RNG + * If the RNG does not provide an appropriate level of entropy (security strength) + * for the given key size, this function returns MCUXCLRSA_STATUS_RNG_ERROR error. + */ + // TODO CLNS-6350 - this check is disabled by default for S5xy for now. Align with SA whether this would be needed. +#ifdef MCUXCL_FEATURE_RSA_STRENGTH_CHECK + uint32_t securityStrength = MCUXCLRSA_GET_MINIMUM_SECURITY_STRENGTH(bitLenKey); + MCUX_CSSL_FP_FUNCTION_CALL(ret_checkSecurityStrength, mcuxClRandom_checkSecurityStrength(pSession, securityStrength)); + if(MCUXCLRANDOM_STATUS_OK != ret_checkSecurityStrength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_RNG_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength)); + } +#endif + + /* + * 3. Check if E is FIPS compliant, i.e., is odd values in the range 2^16 < e < 2^256, + * determine the length without leading zeros. + * If did not pass verification, function returns MCUXCLRSA_STATUS_INVALID_INPUT error. + */ + mcuxClRsa_KeyEntry_t * pPublicExponent = (mcuxClRsa_KeyEntry_t *) type->info; + uint32_t byteLenE; + MCUX_CSSL_FP_FUNCTION_CALL(retVal_VerifyE, mcuxClRsa_VerifyE(pPublicExponent, &byteLenE)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_VerifyE) + { +#if defined(MCUXCL_FEATURE_RSA_STRENGTH_CHECK) + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_checkSecurityStrength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE)); +#else + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE)); +#endif + } + + /* 4. Initialize PKC. */ + const uint32_t cpuWaSizeWord = MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sizeof(mcuxClPkc_State_t)) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClPkc_State_t * pPkcStateBackup = (mcuxClPkc_State_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + if (NULL == pPkcStateBackup) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, pPkcStateBackup, mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + /* + * 5. Allocate buffers in PKC RAM + * - size aligned to FAME word + * - they are be stored in little-endian byte order + * Memory layout: | nDash (FW) | P (pkcByteLenPrime) | nDash (FW) | Q (pkcByteLenPrime) | E (pkcByteLenKey) | + */ + const uint32_t byteLenKey = bitLenKey / 8u; + const uint32_t pkcByteLenKey = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenKey); + const uint32_t byteLenPrime = byteLenKey / 2u; + const uint32_t pkcByteLenPrime = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPrime); + + /* Allocate space in session for p, q and e for now */ + const uint32_t pkcWaSizeWord = (2u * (pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE) + pkcByteLenKey) / (sizeof(uint32_t)); + uint8_t * pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + uint8_t * pPkcBufferP = pPkcWorkarea + MCUXCLRSA_PKC_WORDSIZE; /* offset for NDash */ + uint8_t * pPkcBufferQ = pPkcBufferP + pkcByteLenPrime + MCUXCLRSA_PKC_WORDSIZE; /* offset for NDash */ + uint8_t * pPkcBufferE = pPkcBufferQ + pkcByteLenPrime; + uint8_t * pPkcBufferD = pPkcBufferE + pkcByteLenKey; + uint8_t * pPkcBufferN = pPkcBufferD + pkcByteLenKey; + + mcuxClRsa_KeyEntry_t e; + e.keyEntryLength = byteLenE; + e.pKeyEntryData = pPkcBufferE; + mcuxClRsa_KeyEntry_t p; + p.keyEntryLength = byteLenPrime; + p.pKeyEntryData = pPkcBufferP; + mcuxClRsa_KeyEntry_t q; + q.keyEntryLength = byteLenPrime; + q.pKeyEntryData = pPkcBufferQ; + mcuxClRsa_KeyEntry_t d; + d.keyEntryLength = 0; /* it will be computed by mcuxClRsa_ComputeD */ + d.pKeyEntryData = pPkcBufferD; + + /* Setup UPTR table. */ + const uint32_t uptrtSizeWord = MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(MCUXCLRSA_INTERNAL_KEYGENERATION_PLAIN_UPTRT_SIZE * (sizeof(uint16_t))) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, uptrtSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_SETUPTRT(pOperands); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P] = MCUXCLPKC_PTR2OFFSET(pPkcBufferP); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_Q] = MCUXCLPKC_PTR2OFFSET(pPkcBufferQ); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_E] = MCUXCLPKC_PTR2OFFSET(pPkcBufferE); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N] = MCUXCLPKC_PTR2OFFSET(pPkcBufferN); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_D] = MCUXCLPKC_PTR2OFFSET(pPkcBufferD); + + /* + * 6. Copy E to PKC RAM. + * It is stored in little-endian byte order (copied with reverse order and without leading zeros). + * + * Used functions: mcuxClPkc_ImportBigEndianToPkc + */ + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenPrime, pkcByteLenPrime); + uint32_t leadingZerosE = pPublicExponent->keyEntryLength - byteLenE; + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_E, pPublicExponent->pKeyEntryData + leadingZerosE, byteLenE); + + /* + * 7. Generate prime p. + * Continuation if mcuxClRsa_GenerateProbablePrime returns MCUXCLRSA_STATUS_KEYGENERATION_OK, + * otherwise function ends with MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED or error. + * + * Used functions: mcuxClRsa_GenerateProbablePrime + */ + MCUX_CSSL_FP_FUNCTION_CALL(retVal_GenerateProbablePrime_P, mcuxClRsa_GenerateProbablePrime(pSession, &e, &p, bitLenKey)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_GenerateProbablePrime_P) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + if(MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED == retVal_GenerateProbablePrime_P) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, + MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED, + MCUXCLRSA_KEYGEN_PLAIN_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, retVal_GenerateProbablePrime_P); + } + } + + uint32_t loopCounter = 0; + + do{ + ++loopCounter; + + /* + * 8. Generate prime q. + * Continuation if mcuxClRsa_GenerateProbablePrime returns MCUXCLRSA_STATUS_KEYGENERATION_OK, + * otherwise function ends with MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED or error. + * + * Used functions: mcuxClRsa_GenerateProbablePrime + */ + MCUX_CSSL_FP_FUNCTION_CALL(retVal_GenerateProbablePrime_Q, mcuxClRsa_GenerateProbablePrime(pSession, &e, &q, bitLenKey)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_GenerateProbablePrime_Q) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + if(MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED == retVal_GenerateProbablePrime_Q) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, + MCUXCLRSA_STATUS_KEYGENERATION_ITERATIONSEXCEEDED, + MCUXCLRSA_KEYGEN_PLAIN_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + loopCounter * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + (loopCounter - 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_TestPQDistance), + (loopCounter - 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_ComputeD), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, retVal_GenerateProbablePrime_Q); + } + } + + /* + * 9. Check if |p - q| <= 2^(nlen/2 - 100). + * Continuation if mcuxClRsa_TestPQDistance function returns MCUXCLRSA_STATUS_KEYGENERATION_OK + * otherwise function ends with MCUXCLRSA_STATUS_ERROR error code. + * + * Used functions: mcuxClRsa_TestPQDistance + * + * NOTE: This is a deviation from the method specified in the FIPS 186-4, where this check is performed while generating the prime q + * (see step 5.4 in Appendix B.3.3). + * The @ref mcuxClRsa_GenerateProbablePrime function does not perform this check, it is done after generating p and q. + * For this reason, if p and q does not meet this FIPS requirements, no new prime q number will be generated. Instead + * of function ends with error. + * Rationale of this deviation: + * This check will fail if at least 100 most significant bits of p and q are identical. This can happen + * with very low probability and it's usually treated as a hardware failure. + */ + MCUX_CSSL_FP_FUNCTION_CALL( + retVal_TestPQDistance, + mcuxClRsa_TestPQDistance( + MCUXCLPKC_PACKARGS4( + 0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_Q, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N /* used as a temporary buffer, it is > 2 * MCUXCLRSA_PKC_ROUNDUP_SIZE(16) */), + pkcByteLenPrime)); + if(MCUXCLRSA_STATUS_KEYGENERATION_OK != retVal_TestPQDistance) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_ERROR); + } + + /* + * 10. Compute d := e^(-1) mod lcm(p-1, q-1) + * If mcuxClRsa_ComputeD function returns MCUXCLRSA_STATUS_INVALID_INPUT, then go to step 7 (new q must be generated). + * + * Used functions: mcuxClRsa_ComputeD + * Memory layout: | nDash (FW) | P (pkcByteLenPrime) | nDash (FW) | Q (pkcByteLenPrime) | E (pkcByteLenKey) | D (pkcByteLenKey + FW) | + */ + if (NULL == mcuxClSession_allocateWords_pkcWa(pSession, (pkcByteLenKey + MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t)))) // allocate space for the D (additional FW for D is required by mcuxClRsa_ComputeD) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + MCUX_CSSL_FP_FUNCTION_CALL(retVal_ComputeD, mcuxClRsa_ComputeD(pSession, &e, &p, &q, &d, bitLenKey)); + + if(MCUXCLRSA_STATUS_KEYGENERATION_OK == retVal_ComputeD) + { + break; + } + else + { + mcuxClSession_freeWords_pkcWa(pSession, (pkcByteLenKey + MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t))); // free up space used for the D + } + + }while(true); + + /* + * 11. Compute n := p*q. + * + * Used functions: FAME Plain Multiplication + * + * Memory layout: | nDash (FW) | P (pkcByteLenPrime) | nDash (FW) | Q (pkcByteLenPrime) | E (pkcByteLenKey) | D (pkcByteLenKey) | N (pkcByteLenKey) | + */ + if (NULL == mcuxClSession_allocateWords_pkcWa(pSession, (pkcByteLenKey - MCUXCLRSA_PKC_WORDSIZE) / (sizeof(uint32_t)))) // allocate space for the N and release additional FW need to compute D + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + MCUXCLPKC_PS1_SETLENGTH(pkcByteLenPrime, pkcByteLenPrime); + MCUXCLPKC_FP_CALC_MC1_PM( + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_Q); + MCUXCLPKC_WAITFORFINISH(); + + /* + * 12. Write public key (computed n, e) to the buffer pointed by pPubData. + * This buffer contains RSA key (mcuxClRsa_Key data type, i.e.: key type and key entries) + * followed by the key data, i.e.: n, e. + * Key entries stored in big-endian byte order (copy with reverse order). + * + * Used functions: mcuxClPkc_ExportBigEndianFromPkc (to export n and e). + */ + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClRsa_Key *pRsaPubKey = (mcuxClRsa_Key *) pPubData; + pRsaPubKey->keytype = MCUXCLRSA_KEY_PUBLIC; + *pPubDataLength = sizeof(mcuxClRsa_Key); + + pRsaPubKey->pMod1 = (mcuxClRsa_KeyEntry_t *) (pPubData + *pPubDataLength); + *pPubDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPubKey->pMod2 = NULL; + pRsaPubKey->pQInv = NULL; + + pRsaPubKey->pExp1 = (mcuxClRsa_KeyEntry_t *) (pPubData + *pPubDataLength); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + *pPubDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPubKey->pExp2 = NULL; + pRsaPubKey->pExp3 = NULL; + + pRsaPubKey->pMod1->pKeyEntryData = pPubData + *pPubDataLength; + pRsaPubKey->pMod1->keyEntryLength = byteLenKey; + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC( + pRsaPubKey->pMod1->pKeyEntryData, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N, + pRsaPubKey->pMod1->keyEntryLength); + *pPubDataLength += pRsaPubKey->pMod1->keyEntryLength; + + pRsaPubKey->pExp1->pKeyEntryData = pPubData + *pPubDataLength; + pRsaPubKey->pExp1->keyEntryLength = e.keyEntryLength; + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC( + pRsaPubKey->pExp1->pKeyEntryData, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_E, + pRsaPubKey->pExp1->keyEntryLength); + *pPubDataLength += pRsaPubKey->pExp1->keyEntryLength; + + /* + * 13. Write RSA plain key (d, n) to the buffer pointed by pPrivData. + * This buffer contains RSA key (mcuxClRsa_Key data type, i.e.: key type and key entries) + * followed by the key data, i.e.: n, d. + * Key entries stored in big-endian byte order (copy with reverse order). + * + * Used functions: mcuxClPkc_ExportBigEndianFromPkc (to export n); + * mcuxClPkc_SecureExportBigEndianFromPkc (to export d). + */ + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClRsa_Key *pRsaPrivatePlainKey = (mcuxClRsa_Key *) pPrivData; + pRsaPrivatePlainKey->keytype = MCUXCLRSA_KEY_PRIVATEPLAIN; + *pPrivDataLength = sizeof(mcuxClRsa_Key); + + pRsaPrivatePlainKey->pMod1 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivatePlainKey->pMod2 = NULL; + pRsaPrivatePlainKey->pQInv = NULL; + + pRsaPrivatePlainKey->pExp1 = (mcuxClRsa_KeyEntry_t *) (pPrivData + *pPrivDataLength); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + + *pPrivDataLength += sizeof(mcuxClRsa_KeyEntry_t); + pRsaPrivatePlainKey->pExp2 = NULL; + pRsaPrivatePlainKey->pExp3 = NULL; + + pRsaPrivatePlainKey->pMod1->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivatePlainKey->pMod1->keyEntryLength = byteLenKey; + MCUXCLMEMORY_FP_MEMORY_COPY( + pRsaPrivatePlainKey->pMod1->pKeyEntryData, + pRsaPubKey->pMod1->pKeyEntryData, + pRsaPrivatePlainKey->pMod1->keyEntryLength); + + *pPrivDataLength += pRsaPrivatePlainKey->pMod1->keyEntryLength; + + pRsaPrivatePlainKey->pExp1->pKeyEntryData = pPrivData + *pPrivDataLength; + pRsaPrivatePlainKey->pExp1->keyEntryLength = d.keyEntryLength; + MCUXCLPKC_PS1_SETLENGTH(0u, pkcByteLenKey); /* set operand len for mcuxClPkc_SecureExportBigEndianFromPkc */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExportD, + mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + pRsaPrivatePlainKey->pExp1->pKeyEntryData, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_D, + MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_N /* used as a temp */), + pRsaPrivatePlainKey->pExp1->keyEntryLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExportD) + { + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_ERROR); + } + *pPrivDataLength += pRsaPrivatePlainKey->pExp1->keyEntryLength; + + /* + * 14. Initialization of key handles for public and private key + * a. copy key protection into handle + * b. initialize the key type in handle: + * -set type->algoId to RSA + public/private + * -set length of the key in type->size + * -set type->info to NULL + * c. set pSrcKeyData to point to the start of the provided buffer + * d. set dstKey.loadLocation to mcuxClKey_LoadLocation_NOTLOADED + * e. set other fields of dstKey to zero + */ + mcuxClKey_Descriptor_t * pPubKey = (mcuxClKey_Descriptor_t *) pubKey; + mcuxClKey_setProtectionType(pPubKey, protection); + // TODO CLNS-5165: move the generation of these types into the key component + mcuxClKey_TypeDescriptor_t keyType_public = { MCUXCLKEY_ALGO_ID_RSA ^ MCUXCLKEY_ALGO_ID_PUBLIC_KEY, type->size, NULL }; + mcuxClKey_setTypeDescriptor(pPubKey, keyType_public); + mcuxClKey_setKeyData(pPubKey, pPubData); + mcuxClKey_setLoadStatus(pPubKey, MCUXCLKEY_LOADSTATUS_NOTLOADED); + mcuxClKey_setLoadedKeyData(pPubKey, NULL); + mcuxClKey_setLoadedKeySlot(pPubKey, 0u); + + mcuxClKey_Descriptor_t * pPrivKey = (mcuxClKey_Descriptor_t *) privKey; + mcuxClKey_setProtectionType(pPrivKey, protection); + // TODO CLNS-5165: move the generation of these types into the key component + mcuxClKey_TypeDescriptor_t keyType_private = { MCUXCLKEY_ALGO_ID_RSA ^ MCUXCLKEY_ALGO_ID_PRIVATE_KEY, type->size, NULL }; + mcuxClKey_setTypeDescriptor(pPrivKey, keyType_private); + mcuxClKey_setKeyData(pPrivKey, pPrivData); + mcuxClKey_setLoadStatus(pPrivKey, MCUXCLKEY_LOADSTATUS_NOTLOADED); + mcuxClKey_setLoadedKeyData(pPrivKey, NULL); + mcuxClKey_setLoadedKeySlot(pPrivKey, 0u); + + /* Create link between private and public key handles */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_linkKeyPair, mcuxClKey_linkKeyPair(pSession, privKey, pubKey)); + if (MCUXCLKEY_STATUS_OK != ret_linkKeyPair) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* Clear PKC workarea. */ + uint32_t pkcWaSize = MCUXCLRSA_KEYGENERATION_PLAIN_WAPKC_SIZE(bitLenKey); + MCUXCLPKC_PS1_SETLENGTH(0u, pkcWaSize); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_KEYGENERATION_PLAIN_P, 0u); + + mcuxClSession_setUsage_pkcWa(pSession, backup_pkcWaUsed); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pPkcStateBackup, + mcuxClRsa_KeyGeneration_Plain, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, backup_cpuWaUsed); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRsa_KeyGeneration_Plain, + MCUXCLRSA_STATUS_KEYGENERATION_OK, + MCUXCLRSA_STATUS_FAULT_ATTACK, + MCUXCLRSA_KEYGEN_PLAIN_FP_SECSTRENGTH, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_VerifyE), + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + loopCounter * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_GenerateProbablePrime), + loopCounter * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_TestPQDistance), + loopCounter * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_ComputeD), + MCUXCLPKC_FP_CALLED_CALC_MC1_PM, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportBigEndianFromPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClKey_linkKeyPair), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Mgf1.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Mgf1.c new file mode 100644 index 000000000..c9b0545df --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Mgf1.c @@ -0,0 +1,110 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Mgf1.c + * @brief mcuxClRsa: function, which is called to execute the mask generation function MGF1 of PKCS #1 v2.2. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_mgf1) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_mgf1( + mcuxClSession_Handle_t pSession, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pInput, + const uint32_t inputLength, + const uint32_t outputLength, + uint8_t * pOutput) +{ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_mgf1); + + const uint32_t hLen = pHashAlgo->hashSize; + + /* Update PKC workarea */ + const uint32_t wordSizePkcWa = (MCUXCLRSA_INTERNAL_MGF1_WAPKC_SIZE(inputLength, hLen) / (sizeof(uint32_t))); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordSizePkcWa); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_mgf1, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* Pointer to the hash output */ + uint8_t * pHashOutput = pPkcWorkarea; + + /* Set up hash input */ + uint8_t * pHashInput = pHashOutput + hLen; + + MCUXCLMEMORY_FP_MEMORY_COPY(pHashInput, pInput, inputLength); + + /* counter = UPPER_BOUND(outputLength / pHashAlgo->hashSize) */ + const uint32_t mxCounter = ((outputLength + hLen - 1U) / hLen); + + /* concatenated size of T */ + uint32_t tLen = 0U; + + for(uint32_t counter = 0U; counter < mxCounter; counter++) + { + /* Convert counter to a byte string C of length 4. */ + pHashInput[inputLength] = (uint8_t) (counter >> 24); + pHashInput[inputLength + 1U] = (uint8_t) (counter >> 16); + pHashInput[inputLength + 2U] = (uint8_t) (counter >> 8); + pHashInput[inputLength + 3U] = (uint8_t) (counter); + + /* Append Hash(pInput || C) to T */ + + /* Compute Hash */ + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result, mcuxClHash_compute(pSession, + pHashAlgo, + pHashInput, + inputLength + 4U, + pHashOutput, + &hashOutputSize) ); + if(MCUXCLHASH_STATUS_OK != hash_result) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_mgf1, MCUXCLRSA_STATUS_ERROR); + } + + /* Concatenate the hash of the seed pInput and C to the T */ + uint32_t concatenateLen = (tLen + hLen > outputLength) ? (outputLength - tLen) : hLen; + MCUXCLMEMORY_FP_MEMORY_COPY((uint8_t *) pOutput + tLen, pHashOutput, concatenateLen); + + tLen += concatenateLen; + } + + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + +/* Check define outside of macro so the MISRA rule 20.6 does not get violated */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_mgf1, MCUXCLRSA_STATUS_INTERNAL_MGF_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute) * mxCounter, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) * mxCounter); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest.c new file mode 100644 index 000000000..e133f47d5 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest.c @@ -0,0 +1,333 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_MillerRabinTest.c + * @brief mcuxClRsa: function, which is called to perform the Miller-Rabin + * probabilistic primality tests. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_MillerRabinTest) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_MillerRabinTest( + mcuxClSession_Handle_t pSession, + uint32_t iP_iT, + uint32_t keyBitLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_MillerRabinTest); + + /* Set init status to FAILED */ + mcuxClRsa_Status_t status = MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_MRT_FAILED; + + /* + * Initialization + */ + + /* Backup Uptrt to recover in the end */ + const uint16_t *backupPtrUptrt = MCUXCLPKC_GETUPTRT(); + + /* Create and set local Uptrt table. */ + uint32_t pOperands32[(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_UPTRT_SIZE + 1u) / 2u]; + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t *pOperands = (uint16_t *) pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /* Get iP and iT indices */ + uint32_t uptrtIndexTmp = (iP_iT) & 0xFFu; + uint32_t uptrtIndexPrimeCandidate = (iP_iT >> 8) & 0xFFu; + + /* PKC buffer sizes */ + const uint32_t byteLenPrime = (keyBitLength / 2u) / 8u; /* keyBitLength is multiple of 8 */ + const uint32_t pkcOperandSize = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPrime); + const uint32_t bufferSizeQSquared = pkcOperandSize; // size of temp buffer QSquared + const uint32_t bufferSizeResult = pkcOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of the result of the exponentiation + const uint32_t bufferSizeX = pkcOperandSize; // size of the base number of the exponentiation + const uint32_t bufferSizeT0 = pkcOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T0 + const uint32_t bufferSizeT1 = pkcOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T1 + const uint32_t bufferSizeT2 = pkcOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T2 + const uint32_t bufferSizeT3 = pkcOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T3 + const uint32_t bufferSizeTE = 6u * MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer TE + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE] = backupPtrUptrt[uptrtIndexPrimeCandidate]; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_QSQUARED] = backupPtrUptrt[uptrtIndexTmp]; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_QSQUARED] + (uint16_t)bufferSizeQSquared; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT] + (uint16_t)bufferSizeResult; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X] + (uint16_t)bufferSizeX; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T1] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0] + (uint16_t)bufferSizeT0; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T2] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T1] + (uint16_t)bufferSizeT1; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T3] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T2] + (uint16_t)bufferSizeT2; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_TE] = pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T3] + (uint16_t)bufferSizeT3; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_CONSTANT] = 1u; + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(pOperands); + + /* + * 1. Determine the number of iterations of the test to be performed. + * + * NOTE: The values will be determined only for the supported key lengths 2048, 3072, 4096 + * for error probability 2^(-125) (according to assumptions). In the future, if there + * is a need to support other lengths, it will be possible to provide a more accurate + * granulation of the number of iterations. + */ + + uint32_t numberMRrounds = 6; /* init value for 1024b prime */ + if(192u == byteLenPrime) + { + numberMRrounds = 4; + } + else if(256u == byteLenPrime) + { + numberMRrounds = 3; + } + else + { + /* intentionally do nothing */ + } + + /* get pointer to the witness */ + uint8_t * pWitness = MCUXCLPKC_OFFSET2PTR(pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT]); + + /* + * 2. Compute m (exp) = (PrimeCandidate-1) / 2^a + * NOTE: a=1 since the PrimeCandidate is congruent 3 mod 4 + */ + MCUXCLPKC_PS1_SETLENGTH(pkcOperandSize, pkcOperandSize); + MCUXCLPKC_FP_CALC_OP1_SHR(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, 1); + + /* Revert exponent to big-endian - keep it in FXRAM memory */ + uint8_t * pExp = MCUXCLPKC_OFFSET2PTR(pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_TE]) + bufferSizeTE; //allocate space for it in the FXRAM, if there is not enough memory it can be in CPU + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pExp, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X, byteLenPrime); + /* Allocate space for the temporary buffer for exponent (aligned to CPU word, ength shall be a multiple of CPU word and greater than @p byteLenExp) */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("Cast to CPU word aligned") + uint32_t * pExpTemp = (uint32_t *) pExp + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(byteLenPrime) / sizeof(uint32_t); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /* Calculate Ndash of w (primeCandidate) */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0); + + /* + * Calculate QSquared + * Due to fact that the most significant bit of prime candidate is 1 (this is because for FIPS) do not need computed shifted modulus, + * can directly use the prime candidate as a shifted modulus. + */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() + MCUXCLMATH_FP_QSQUARED(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_QSQUARED /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() + + /* + * 3. Set iteration counter, and start loop + */ + uint32_t counter = 0; + + /* Variables related to flow protection to count execution of loops */ + uint32_t witnessLoopCounterMain = 0; + + uint32_t zeroFlag_check = MCUXCLPKC_FLAG_NONZERO; + + MCUX_CSSL_FP_LOOP_DECL(mainLoopFp); + + do + { + uint32_t carryFlag_check = MCUXCLPKC_FLAG_CARRY; + do{ + /* + * 4. Get random integer b of length equal to prime candidate from an RBG. + */ + ++witnessLoopCounterMain; + +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + const uint32_t cpuWaSizeWord = MCUXCLRSA_INTERNAL_MILLERRABINTEST_WACPU_SIZE_WO_RNG(byteLenPrime) / sizeof(uint32_t); + uint8_t * pWitnessCpu = (uint8_t*) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + if (NULL == pWitnessCpu) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_MillerRabinTest, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUX_CSSL_FP_FUNCTION_CALL(randomGenerateResult, mcuxClRandom_generate(pSession, + pWitnessCpu, + byteLenPrime)); + if(MCUXCLRANDOM_STATUS_OK != randomGenerateResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_MillerRabinTest, MCUXCLRSA_STATUS_RNG_ERROR); + } + MCUXCLMEMORY_FP_MEMORY_COPY(pWitness, pWitnessCpu, byteLenPrime); + + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); +#else + MCUX_CSSL_FP_FUNCTION_CALL(randomGenerateResult, mcuxClRandom_generate(pSession, + pWitness, + byteLenPrime)); + if(MCUXCLRANDOM_STATUS_OK != randomGenerateResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_MillerRabinTest, MCUXCLRSA_STATUS_RNG_ERROR); + } +#endif /* MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND */ + + /* + * 5. If ((b <= 1) or (b >= PrimeCandidate - 1)), then go to step 4. + */ + + /* Compute PrimeCandidate-2 */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, 2); + + /* Compare PrimeCandidate-2 and b */ + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT); + carryFlag_check = MCUXCLPKC_WAITFORFINISH_GETCARRY(); + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_NOCARRY == carryFlag_check), MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST)); + if(MCUXCLPKC_FLAG_NOCARRY == carryFlag_check) + { + /* Compare 2 and b */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT, 2); + carryFlag_check = MCUXCLPKC_WAITFORFINISH_GETCARRY(); + } + }while(MCUXCLPKC_FLAG_NOCARRY != carryFlag_check); + + /* + * 6. Compute z = b^m mod w (using secure exponentiation) + */ + + /* Convert b to Montgomery representation i.e. bm = b*QSquared mod primeCand */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X /* bm */, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT /* b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_QSQUARED /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE); + MCUXCLPKC_WAITFORFINISH(); + + /* + * Perform secure exponentiation z = b^m mod w. + * LEN and MCLEN was already initialized OPLEN = MCLEN = pkcPrimeByteLength, + */ + MCUX_CSSL_FP_FUNCTION_CALL(secModExpResult, + MCUXCLMATH_SECMODEXP_WITHOUT_RERANDOMIZATION( + pSession, + pExp, + pExpTemp, + byteLenPrime, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT, /* Result */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X, /* Montgomery representation of base number */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, /* Modulus, NDash of the modulus should be stored in front of it */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_TE, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_T3) ); + if (MCUXCLMATH_STATUS_OK != secModExpResult) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_MillerRabinTest, MCUXCLRSA_STATUS_ERROR); + } + + /* + * call the FUP to do the below steps + * Convert from Montgomery to normal representation + * Normalize the result (case if R > N) + * 7. If ((z = 1), test passed, then go to step 9 + */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP, + mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP_LEN); + + MCUX_CSSL_FP_LOOP_ITERATION(mainLoopFp, MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)); + + zeroFlag_check = MCUXCLPKC_WAITFORFINISH_GETZERO(); + + MCUX_CSSL_FP_EXPECT(MCUX_CSSL_FP_CONDITIONAL((MCUXCLPKC_FLAG_ZERO != zeroFlag_check), MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST, MCUXCLPKC_FP_CALLED_CALC_OP1_CMP)); + + if(MCUXCLPKC_FLAG_ZERO != zeroFlag_check) + { + /* Need to check the second condition */ + /* + * 8. If ((z = PrimeCandidate-1), test passed, then continue. Otherwise, it means + * that PrimeCandidate is composite, function returns MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_MRT_FAILED error code + */ + + /* Comput PrimeCandidate-1 */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT /* PrimeCandidate-1 */, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_PRIMECANDIDATE, 1); + /* Compare PrimeCandidate-1 and z */ + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_RESULT /* PrimeCandidate-1 */, MCUXCLRSA_INTERNAL_UPTRTINDEX_MILLERRABIN_X /* z */); + zeroFlag_check = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if(MCUXCLPKC_FLAG_ZERO != zeroFlag_check) + { + /* Did not pass test, it is not prime, stop MillerRabin test. */ + break; + } + } + + /* + * 9. Increment counter. + */ + ++counter; + + /* + * 10. If i == iterations, the PrimeCandidate is probably prime, function returns MCUXCLRSA_STATUS_KEYGENERATION_OK. + * Otherwise, continue the test in loop, go to step 4. + */ + }while(counter < numberMRrounds); + + if((counter == numberMRrounds) && (MCUXCLPKC_FLAG_ZERO == zeroFlag_check) /* double checking of passing the zero flag */ ) + { + /* This means all rounds have passed test */ + status = MCUXCLRSA_STATUS_KEYGENERATION_OK; + } + + /* Recover Uptrt */ + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + MCUX_CSSL_FP_COUNTER_STMT(uint32_t mainLoopCounter = (counter == numberMRrounds) ? numberMRrounds : (counter + 1u)); + +/* Use temporary define to avoid preprocessor directive inside the function exit macro below, + as this would violate the MISRA rule 20.6 otherwise. */ +#ifdef MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND + #define TMP_PKCRAM_WORKAROUND \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) * witnessLoopCounterMain, \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy) * witnessLoopCounterMain +#else + #define TMP_PKCRAM_WORKAROUND \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_generate) * witnessLoopCounterMain +#endif + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_MillerRabinTest, + status, + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + TMP_PKCRAM_WORKAROUND, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST * witnessLoopCounterMain, + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP * witnessLoopCounterMain, + MCUX_CSSL_FP_LOOP_ITERATIONS(mainLoopFp, mainLoopCounter)); + +#undef TMP_PKCRAM_WORKAROUND +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest_FUP.c new file mode 100644 index 000000000..7e27ca122 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_MillerRabinTest_FUP.c @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_MillerRabinTest_FUP.c + * @brief mcuxClRsa: FUP programs for implementation of Rsa Miller-Rabin test + */ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_MillerRabinTest_ReducAndCheck_FUP[4] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xefu,0x27u,0xb1u,0xf6u},{0x80u,0x33u,0x02u,0x00u,0x00u,0x03u},{0x80u,0x2au,0x00u,0x03u,0x00u,0x03u},{0x00u,0x1bu,0x00u,0x03u,0x09u,0x02u}}; + + +/* + * FUP to do Montgoery reduction and check the result + */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ModInv.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ModInv.c new file mode 100644 index 000000000..f0bcf4069 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_ModInv.c @@ -0,0 +1,85 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_ModInv.c + * @brief mcuxClRsa: function, which is called to compute modular inversion X^(-1) mod N + * + * The implementation assumes that: + * - N is congruent 2 mod 4 + * - size of X <= OPLEN = operandSize + * - content of N will be destroyed + */ + +#include +#include + +#include +#include + +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_ModInv) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClRsa_ModInv(uint32_t iR_iX_iN_iT) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_ModInv); + + /* Get iR, iX, iN, and iT indices */ + uint32_t uptrtIndexR = (iR_iX_iN_iT >> 24) & 0xFFu; + uint32_t uptrtIndexX = (iR_iX_iN_iT >> 16) & 0xFFu; + uint32_t uptrtIndexN = (iR_iX_iN_iT >> 8) & 0xFFu; + uint32_t uptrtIndexT = (iR_iX_iN_iT) & 0xFFu; + + /* + * 1. Compute odd part of the N + * Nodd = N >> 1 + * Nodd should be placed in N buffer (there is one PKC word is reserved before N for NDash computed in step 2) + */ + MCUXCLPKC_FP_CALC_OP1_SHR(uptrtIndexN, uptrtIndexN, 1); + + /* + * 2. Calculate NDash of Nodd + * + * Used functions: mcuxClMath_NDash + */ + MCUXCLMATH_FP_NDASH(uptrtIndexN, uptrtIndexT); + + /* + * 3. Preform modular inversion of the odd part of the N + * Yodd = X^(-1) mod Nodd + */ + MCUXCLMATH_FP_MODINV(uptrtIndexR, uptrtIndexX, uptrtIndexN, uptrtIndexT); + + /* + * 4. Compute R = X^(-1) mod * N = (1 - Yodd mod 2) * Nodd + Yodd + * Check the LSbit of Yodd: + * if LSbit(Yodd) == 1 -> (1 - Yodd mod 2) = 0 + * R = Yodd + * else LSbit(Yodd) == 0 -> (1 - Yodd mod 2) = 1 -> + * R = Nodd + Yodd + */ + const uint16_t *pUptrt = MCUXCLPKC_GETUPTRT(); + uint8_t *Yodd = (uint8_t *) MCUXCLPKC_OFFSET2PTR(pUptrt[uptrtIndexR]); + MCUXCLPKC_WAITFORFINISH(); + const uint8_t lsbYodd = (Yodd[0] & 0x01u); + if(0u == lsbYodd) + { + MCUXCLPKC_FP_CALC_OP1_ADD(uptrtIndexR, uptrtIndexR, uptrtIndexN); + } + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClRsa_ModInv, + MCUXCLPKC_FP_CALLED_CALC_OP1_SHR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModInv), + ((lsbYodd == 0u) ? MCUXCLPKC_FP_CALLED_CALC_OP1_ADD : 0u)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoEncode.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoEncode.c new file mode 100644 index 000000000..4ec9fb023 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoEncode.c @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_NoEncode.c + * @brief mcuxClRsa: function, which is called in case of no encoding + */ + + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + + +/**********************************************************/ +/* Specification of no-encode mode structure */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_NoEncode = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_noEncode), + .pHashAlgo1 = NULL, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_noEncode +}; + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_noEncode, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_noEncode( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength UNUSED_PARAM, + mcuxCl_Buffer_t pVerificationInput UNUSED_PARAM, + mcuxClHash_Algo_t pHashAlgo UNUSED_PARAM, + const uint8_t * pLabel UNUSED_PARAM, + const uint32_t saltlabelLength UNUSED_PARAM, + const uint32_t keyBitLength, + const uint32_t options UNUSED_PARAM, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_noEncode); + + /* Setup UPTR table. */ + const uint32_t cpuWaSizeWord = (((sizeof(uint16_t)) * MCUXCLRSA_INTERNAL_NOENCODE_UPTRT_SIZE) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_noEncode, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_NOENCODE_OUT] = MCUXCLPKC_PTR2OFFSET(pOutput); + + /* Set UPTRT table */ + MCUXCLPKC_SETUPTRT(pOperands); + + /* Export message of size BYTE_LENGTH(keyBitLength) from pInput to pOutput in reverse order. */ + + uint32_t keyByteLength = keyBitLength / 8U; /* keyBitLength is a multiple of 8 */ + const uint32_t ps1OpLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength); /* PS1 length = key byte length rounded up to PKC word size */ + MCUXCLPKC_PS1_SETLENGTH(0u, ps1OpLen); + + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_NOENCODE_OUT, (const uint8_t *)pInput, keyByteLength); + + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + /* Return error code MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_noEncode, MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoVerify.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoVerify.c new file mode 100644 index 000000000..d684a9c08 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_NoVerify.c @@ -0,0 +1,103 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_NoVerify.c + * @brief mcuxClRsa: function, which is called in case of no verification + */ + + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/**********************************************************/ +/* Specification of no-verify mode structure */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_NoVerify = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_noVerify), + .pHashAlgo1 = NULL, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_noVerify +}; + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_noVerify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_noVerify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput UNUSED_PARAM, + const uint32_t inputLength UNUSED_PARAM, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo UNUSED_PARAM, + const uint8_t * pLabel UNUSED_PARAM, + const uint32_t saltlabelLength UNUSED_PARAM, + const uint32_t keyBitLength, + const uint32_t options UNUSED_PARAM, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_noVerify); + + /* Setup UPTR table. */ + const uint32_t cpuWaSizeWord = (((sizeof(uint16_t)) * MCUXCLRSA_INTERNAL_NOVERIFY_UPTRT_SIZE) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + const uint32_t keyByteLength = keyBitLength / 8U; /* keyBitLength is a multiple of 8 */ + const uint32_t pkcWaSizeWord = MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength) / (sizeof(uint32_t)); + uint8_t *pPkcWa = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if ((NULL == pOperands) || (NULL == pPkcWa)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_noVerify, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_IN] = MCUXCLPKC_PTR2OFFSET(pVerificationInput); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_TMP] = MCUXCLPKC_PTR2OFFSET(pPkcWa); + + /* Set UPTRT table */ + MCUXCLPKC_SETUPTRT(pOperands); + + /* Export result of size BYTE_LENGTH(keyBitLength) from pInput to pOutput in reverse order. */ + const uint32_t ps1OpLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength); /* PS1 length = key byte length rounded up to PKC word size */ + MCUXCLPKC_PS1_SETLENGTH(0u, ps1OpLen); + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecExport, mcuxClPkc_SecureExportBigEndianFromPkc(pSession, + (uint8_t * )pOutput, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_IN, + MCUXCLRSA_INTERNAL_UPTRTINDEX_NOVERIFY_TMP), + keyByteLength)); + if (MCUXCLPKC_STATUS_OK != ret_SecExport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_noVerify, MCUXCLRSA_STATUS_ERROR); + } + + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + /* Return error code MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK. */ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_noVerify, MCUXCLRSA_STATUS_VERIFYPRIMITIVE_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureExportBigEndianFromPkc)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Encode_sign.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Encode_sign.c new file mode 100644 index 000000000..9a809674b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Encode_sign.c @@ -0,0 +1,243 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Pkcs1v15Encode_sign.c + * @brief mcuxClRsa: function, which is called to execute EMSA-PKCS1-v1_5-ENCODE + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/**********************************************************/ +/* Hash algorithm identifiers as DigestInfo types */ +/**********************************************************/ +static const uint8_t mcuxClRsa_oidSha2_224[] = {0x30, 0x2d, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x04, 0x05, + 0x00, 0x04, 0x1c}; + +static const uint8_t mcuxClRsa_oidSha2_256[] = {0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, + 0x00, 0x04, 0x20}; + +static const uint8_t mcuxClRsa_oidSha2_384[] = {0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, + 0x00, 0x04, 0x30}; + +static const uint8_t mcuxClRsa_oidSha2_512[] = {0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, + 0x00, 0x04, 0x40}; + +struct mcuxClRsa_oid_t { + size_t length; + const uint8_t * value; +}; + +static const struct mcuxClRsa_oid_t mcuxClRsa_oidTable[] = { + { sizeof(mcuxClRsa_oidSha2_224), mcuxClRsa_oidSha2_224 }, + { sizeof(mcuxClRsa_oidSha2_256), mcuxClRsa_oidSha2_256 }, + { sizeof(mcuxClRsa_oidSha2_384), mcuxClRsa_oidSha2_384 }, + { sizeof(mcuxClRsa_oidSha2_512), mcuxClRsa_oidSha2_512 } +}; + +#define DIGESTSIZE_TO_INDEX(len) (((len) - 16u) / 16u) + ///< Formula for calculating the OID table index from the digest size + +/**********************************************************/ +/* Specifications of PKCS#1 v1.5 mode structures */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_224 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha224, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Encode_sign +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_256 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha256, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Encode_sign +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_384 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha384, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Encode_sign +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_PKCS1v15_Sha2_512 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha512, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Encode_sign +}; + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_pkcs1v15Encode_sign, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pkcs1v15Encode_sign( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput UNUSED_PARAM, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel UNUSED_PARAM, + const uint32_t saltlabelLength UNUSED_PARAM, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_pkcs1v15Encode_sign); + /*****************************************************/ + /* Initialization */ + /*****************************************************/ + + /* Length of the encoded message. */ + const uint32_t emLen = (keyBitLength + 7u) / 8u; /* byte length, rounded up */ + /* Length of the output of hash function. */ + const uint32_t hLength = pHashAlgo->hashSize; + + /* Length of the T-padding containing the hash algorithm identifier. */ + uint8_t const * phashAlgorithmIdentifier = mcuxClRsa_oidTable[DIGESTSIZE_TO_INDEX(hLength)].value; + /* Length of the T-padding DigestInfo containing the hash algorithm identifier. */ + const uint32_t hashAlgorithmIdentifierLength = mcuxClRsa_oidTable[DIGESTSIZE_TO_INDEX(hLength)].length; + + /* Number of required padding bytes */ + const uint32_t paddingLength = emLen - hashAlgorithmIdentifierLength - hLength - 3u; + + /*****************************************************/ + /* If emLen < tLen + 11, return 'invalid input'. */ + /*****************************************************/ + if(emLen < (hashAlgorithmIdentifierLength + hLength + 11u)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Encode_sign, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /*****************************************************/ + /* Prepare the padding */ + /*****************************************************/ + /* Setup session. */ + const uint32_t wordSizePkcWa = (emLen + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordSizePkcWa); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Encode_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* + * Set buffers in PKC workarea + * PKC = | 0x00 || 0x01 || PS || 0x00 | T || H | + */ + /* General pointer to encoded message at the beginning of the buffer */ + mcuxCl_Buffer_t pEm = pPkcWorkarea; + /* Pointer to the buffer for the padding bytes PS */ + mcuxCl_Buffer_t pPs = pEm + 2u; + /* Pointer to the buffer for the algorithm identifier T */ + mcuxCl_Buffer_t pT = pPs + paddingLength + 1u; + + /* Pointer to the buffer for the hash H */ + mcuxCl_Buffer_t pH = pT + hashAlgorithmIdentifierLength; + + + /* Write 0x00 0x01 prefix */ + *(pEm) = (uint8_t) 0x00; + *(pEm + 1u) = (uint8_t) 0x01; + + /* Write padding bytes */ + MCUXCLMEMORY_FP_MEMORY_SET_WITH_BUFF(pPs, 0xFFU, paddingLength, emLen - 2u); + + /* Write 0x00 divider */ + *(pPs + paddingLength) = (uint8_t) 0x00; + + /* Write DigestInfo T */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_copy(pT, + phashAlgorithmIdentifier, + hashAlgorithmIdentifierLength, + hashAlgorithmIdentifierLength)); + + /*****************************************************/ + /* Perform hash operation or just copy the digest */ + /*****************************************************/ + if(MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Call hash function on pInput and store the result in the buffer at pH */ + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result, mcuxClHash_compute(pSession, + pHashAlgo, + pInput, + inputLength, + pH, + &hashOutputSize + + )); + if(MCUXCLHASH_STATUS_OK != hash_result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Encode_sign, MCUXCLRSA_STATUS_ERROR); + } + } + else if (MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Copy pInput to buffer at pH (located at the end of the buffer) */ + MCUXCLMEMORY_FP_MEMORY_COPY(pH, pInput, hLength); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Encode_sign, MCUXCLRSA_STATUS_ERROR); + } + + /*****************************************************/ + /* Prepare the encoded message for output */ + /*****************************************************/ + + /* Copy encoded message to beginning of PKC workarea and switch the endianness */ + MCUXCLMEMORY_FP_MEMORY_COPY(pOutput, pPkcWorkarea, emLen); + + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("the pOutput PKC buffer is CPU word aligned.") + MCUXCLPKC_FP_SWITCHENDIANNESS((uint32_t *) pOutput, emLen); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Encode_sign, MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Verify.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Verify.c new file mode 100644 index 000000000..d7104256a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Pkcs1v15Verify.c @@ -0,0 +1,148 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Pkcs1v15Verify.c + * @brief mcuxClRsa: function, which is called to execute EMSA-PKCS1-v1_5-VERIFY + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + + +/**********************************************************/ +/* Specifications of PKCS#1 v1.5 mode structures */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_224 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Verify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha224, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Verify +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_256 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Verify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha256, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Verify +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_384 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Verify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha384, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Verify +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_PKCS1v15_Sha2_512 = { + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Verify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha512, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pkcs1v15Verify +}; + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_pkcs1v15Verify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pkcs1v15Verify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput UNUSED_PARAM, + uint32_t * const pOutLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_pkcs1v15Verify); + /*****************************************************/ + /* Initialization */ + /*****************************************************/ + + /* Length of the encoded message. */ + const uint32_t emLen = (keyBitLength + 7u) / 8u; /* byte length, rounded up */ + const uint32_t wordSizePkcWa = (emLen + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + + /* Setup session with buffer for encoding result. */ + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordSizePkcWa); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /*****************************************************/ + /* Perform pkcs1v15Encode */ + /*****************************************************/ + MCUX_CSSL_FP_FUNCTION_CALL(encode_result, mcuxClRsa_pkcs1v15Encode_sign(pSession, + pInput, + inputLength, + NULL, + pHashAlgo, + pLabel, + saltlabelLength, + keyBitLength, + options, + pPkcWorkarea, + NULL)); + if(MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK != encode_result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Verify, MCUXCLRSA_STATUS_ERROR); + } + + /*****************************************************/ + /* Compare results */ + /*****************************************************/ + MCUX_CSSL_FP_FUNCTION_CALL(compare_result, mcuxCsslMemory_Compare( + mcuxCsslParamIntegrity_Protect(3u, pPkcWorkarea, pVerificationInput, emLen), + pPkcWorkarea, + pVerificationInput, + emLen + )); + + if(MCUXCSSLMEMORY_STATUS_EQUAL != compare_result) + { + if(MCUXCSSLMEMORY_STATUS_NOT_EQUAL == compare_result) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Verify, MCUXCLRSA_STATUS_VERIFY_FAILED, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare)); + } + else + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Verify, MCUXCLRSA_STATUS_ERROR); + } + } + + /*****************************************************/ + /* Cleanup & Exit */ + /*****************************************************/ + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pkcs1v15Verify, MCUXCLRSA_STATUS_VERIFY_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pkcs1v15Encode_sign), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt.c new file mode 100644 index 000000000..98b6f4612 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt.c @@ -0,0 +1,658 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_PrivateCrt.c + * @brief mcuxClRsa: implementation of RSA private CRT key operation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_privateCRT) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_privateCRT( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pInput, + mcuxCl_Buffer_t pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_privateCRT); + + /************************************************************************************************/ + /* Check the key type and key data; */ + /* if they are incorrect, MCUXCLRSA_STATUS_INVALID_INPUT is returned */ + /************************************************************************************************/ + if((MCUXCLRSA_KEY_PRIVATECRT != pKey->keytype) && (MCUXCLRSA_KEY_PRIVATECRT_DFA != pKey->keytype)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pMod1->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pMod2->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pQInv->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pExp1->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pExp2->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if((MCUXCLRSA_KEY_PRIVATECRT_DFA == pKey->keytype) && (NULL == pKey->pExp3->pKeyEntryData)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /************************************************************************************************/ + /* Check that 64 < modulus length < 512 or 1024; otherwise return MCUXCLRSA_STATUS_INVALID_INPUT.*/ + /************************************************************************************************/ + /* Ensure the length won't overflow */ + if((pKey->pMod1->keyEntryLength < 32U) || (pKey->pMod1->keyEntryLength > ((MCUXCLRSA_MAX_MODLEN / 2U) + 1U)) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + if((pKey->pMod2->keyEntryLength < 32U) || (pKey->pMod2->keyEntryLength > ((MCUXCLRSA_MAX_MODLEN / 2U) + 1U)) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /* Obtain modulus length by counting leading zeroes in P and Q */ + uint32_t keyBitLength; + MCUXCLRSA_CALC_MODLEN_FROM_CRTKEY(pKey, keyBitLength); + const uint32_t exactModByteLength = keyBitLength / 8u; + + if((exactModByteLength < 64U) || (exactModByteLength > MCUXCLRSA_MAX_MODLEN) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /************************************************************************************************/ + /* Initialization - Prepare buffers in PKC workarea and clear PKC workarea */ + /************************************************************************************************/ + + /* Size definitions */ + const uint32_t byteLenPQ = pKey->pMod1->keyEntryLength; // P and Q have the same byte length + const uint32_t byteLenQInv = pKey->pQInv->keyEntryLength; + const uint32_t byteLenCeilN = 2u * byteLenPQ; // rounded up byte length of N, necessary for calculations as N is obtained by multiplying P and Q + const uint32_t blindLen = MCUXCLRSA_INTERNAL_PRIVATECRT_BLINDING_SIZE; // length in bytes of the random value used for blinding + const uint32_t blindAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(blindLen); + const uint32_t blindSquaredAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(blindLen * 2u); + const uint32_t primeAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenPQ); + const uint32_t modAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenCeilN); + const uint32_t qInvAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenQInv); + const uint32_t blindedPrimeAlignLen = primeAlignLen + blindAlignLen; + const uint32_t blindedMessageAlignLen = modAlignLen + blindAlignLen; + const uint32_t blindedModAlignLen = 2u * blindedPrimeAlignLen; + + /* PKC buffer sizes */ + const uint16_t bufferSizePrimeRand = (uint16_t)blindAlignLen; // size of buffer for random multiplicative blinding + const uint16_t bufferSizePrimePQb = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of buffer for blinded P or Q, including PKW word for NDash + const uint16_t bufferSizePrimeT0 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT0 + const uint16_t bufferSizePrimeT1 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT1 + const uint16_t bufferSizePrimeT2 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT2 + const uint16_t bufferSizePrimeT3 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT3 + const uint16_t bufferSizePrimeT4 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT4 + const uint16_t bufferSizePrimeTE = (uint16_t)6u*MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeTE + const uint16_t bufferSizePrimeR = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer R (result of the internal exponentiation) + const uint16_t bufferSizePrimeT5 = (uint16_t)blindedPrimeAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer primeT5 + const uint16_t bufferSizeModM = (uint16_t)modAlignLen; // size of buffer for result M + const uint16_t bufferSizeModT1 = (uint16_t)modAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer modT1 + const uint16_t bufferSizeModT2 = (uint16_t)modAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of temporary buffer modT2 + const uint16_t bufferSizeModT3 = (uint16_t)blindedMessageAlignLen; // size of blinded message modT3: blindedMessageAlignLen=modAlignLen + MCUXCLRSA_PKC_WORDSIZE + const uint16_t bufferSizeModT4 = (uint16_t)blindedModAlignLen; // size of temporary buffer modT4: blindedModAlignLen = 2*blindedPrimeAlignLen = modAlignLen + 2*MCUXCLRSA_PKC_WORDSIZE + const uint16_t bufferSizeModN = (uint16_t)blindedModAlignLen + MCUXCLRSA_PKC_WORDSIZE; // size of buffer for modulus N: blindedModAlignLen for the division, and one extra PKW word for NDash + + /* Setup session. */ + const uint16_t bufferSizeTotal = bufferSizePrimeRand + + MCUXCLRSA_MAX(bufferSizePrimePQb + bufferSizePrimeT0 + bufferSizePrimeT1 + bufferSizePrimeT2 + bufferSizePrimeT3 + bufferSizePrimeT4 + bufferSizePrimeTE + bufferSizePrimeR + bufferSizePrimeT5, + bufferSizeModM + bufferSizeModT1 + bufferSizeModT2 + bufferSizeModT3 + bufferSizeModT4 + bufferSizeModN); + const uint32_t pkcWaSizeWord = (uint32_t) bufferSizeTotal / (sizeof(uint32_t)); + uint32_t *pPkcWorkarea = mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* PKC buffers used for operations modulo P,Q and modulo N */ + uint32_t *pBlind = pPkcWorkarea; + + /* PKC buffers for exponentiations and operations modulo primes P,Q */ + uint8_t *pPQ_b = (uint8_t *) pBlind + bufferSizePrimeRand + MCUXCLRSA_PKC_WORDSIZE; // one extra PKC word for NDash + uint8_t *pPrimeT0 = pPQ_b + bufferSizePrimePQb - MCUXCLRSA_PKC_WORDSIZE; // size of NDash is included in bufferSizePrimePQb + uint8_t *pPrimeT1 = pPrimeT0 + bufferSizePrimeT0; + uint8_t *pPrimeT2 = pPrimeT1 + bufferSizePrimeT1; + uint8_t *pPrimeT3 = pPrimeT2 + bufferSizePrimeT2; + uint8_t *pPrimeT4 = pPrimeT3 + bufferSizePrimeT3; + uint8_t *pPrimeTE = pPrimeT4 + bufferSizePrimeT4; + uint8_t *pPrimeR = pPrimeTE + bufferSizePrimeTE; + uint8_t *pPrimeT5 = pPrimeR + bufferSizePrimeR; + + /* PKC buffers for operations modulo modulus N */ + uint8_t *pM = pPQ_b - MCUXCLRSA_PKC_WORDSIZE; // buffer M overwrites buffer PQb, including NDash of PQb + uint8_t *pModT1 = pM + bufferSizeModM; + uint8_t *pModT2 = pModT1 + bufferSizeModT1; + uint8_t *pModT3 = pModT2 + bufferSizeModT2; + uint8_t *pModT4 = pModT3 + bufferSizeModT3; + uint8_t *pN = pModT4 + bufferSizeModT4 + MCUXCLRSA_PKC_WORDSIZE; // one extra PKC word for NDash + + /* Setup UPTR table */ + const uint32_t cpuWaSizeWord = (((sizeof(uint16_t)) * MCUXCLRSA_INTERNAL_PRIVCRT_UPTRT_SIZE) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + uint32_t * pOperands32 = mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_INPUT] = MCUXCLPKC_PTR2OFFSET(pInput); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND] = MCUXCLPKC_PTR2OFFSET((uint8_t *) pBlind); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B] = MCUXCLPKC_PTR2OFFSET(pPQ_b); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0] = MCUXCLPKC_PTR2OFFSET(pPrimeT0); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1] = MCUXCLPKC_PTR2OFFSET(pPrimeT1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2] = MCUXCLPKC_PTR2OFFSET(pPrimeT2); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET3] = MCUXCLPKC_PTR2OFFSET(pPrimeT3); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4] = MCUXCLPKC_PTR2OFFSET(pPrimeT4); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_TE] = MCUXCLPKC_PTR2OFFSET(pPrimeTE); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R] = MCUXCLPKC_PTR2OFFSET(pPrimeR); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5] = MCUXCLPKC_PTR2OFFSET(pPrimeT5); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_M] = MCUXCLPKC_PTR2OFFSET(pM); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1] = MCUXCLPKC_PTR2OFFSET(pModT1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2] = MCUXCLPKC_PTR2OFFSET(pModT2); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT3] = MCUXCLPKC_PTR2OFFSET(pModT3); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4] = MCUXCLPKC_PTR2OFFSET(pModT4); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N] = MCUXCLPKC_PTR2OFFSET(pN); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_CONST0] = 0u; + + + /* Set UPTRT table */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(pOperands); + + /* Clear PKC workarea after the input */ + MCUXCLPKC_PS2_SETLENGTH(0u, bufferSizeTotal); + MCUXCLPKC_PS1_SETLENGTH(0u, primeAlignLen); + MCUXCLPKC_FP_CALC_OP2_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND, 0u); + + /* Prepare expTemp buffer in CPU workarea - aligned to CPU word, length=MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(byteLenExp) */ + uint32_t * pExpTemp = pOperands32 + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_PRIVCRT_UPTRT_SIZE * sizeof(uint16_t)))/sizeof(uint32_t); + + /************************************************************************************************/ + /* Securely import and blind q */ + /************************************************************************************************/ + + /* Securely import q */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImport, mcuxClPkc_SecureImportBigEndianToPkc(pSession, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */), + pKey->pMod2->pKeyEntryData, + byteLenPQ)); + if (MCUXCLPKC_STATUS_OK != ret_SecImport) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /* Generate random number used for blinding and set LSB to 1, to ensure it is odd and non-null */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate1, mcuxClRandom_ncGenerate(pSession, (uint8_t *) pBlind, blindLen)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + pBlind[0] |= 0x1u; + + /* Blind q to obtain q_b */ + MCUXCLPKC_FP_CALC_OP1_MUL(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND /* blind */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* q */); + + /************************************************************************************************/ + /* Prepare Montgomery parameters and convert parameters to Montgomery representation. */ + /************************************************************************************************/ + + /* Calculate Ndash of q_b */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */); + + /* Calculate input Cq_b = C mod q_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(blindedPrimeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(modAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_FP_CALC_MC2_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* Cq_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_INPUT /* C */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */); + + /* Calculate QDash */ + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */); + MCUXCLMATH_FP_QDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */, (uint16_t)(modAlignLen + blindedPrimeAlignLen)); + + /* Convert input to Montgomery representation i.e. Cq_bm = Cq_b*QDash mod q_b */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* Cq*QDash mod q_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* Cq_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */); + + /************************************************************************************************/ + /* Perform secure exponentiation: Mq_bm = (Cq_bm^dq) mod q_b */ + /************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecModExpDQ, + MCUXCLMATH_SECMODEXP(pSession, + pKey->pExp2->pKeyEntryData, /* dq */ + pExpTemp, + pKey->pExp2->keyEntryLength, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R, /* Result */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, /* Montgomery representation of base number: Cq*QDash mod q_b */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B, /* Modulus q_b (blinded q) */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_TE, /* Temporary buffers */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1) ); + if (MCUXCLMATH_STATUS_OK != ret_SecModExpDQ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /************************************************************************************************/ + /* Convert result back to normal representation Mq_b */ + /************************************************************************************************/ + + /* Convert from Montgomery to normal representation */ + MCUXCLPKC_FP_CALC_MC1_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET3 /* Mq_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* result of the exponentiation */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* q_b */); + + /************************************************************************************************/ + /* Securely import and blind p */ + /************************************************************************************************/ + + /* Clear PKC buffer before the import */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, primeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(0u, (uint32_t) bufferSizePrimeT0); + MCUXCLPKC_FP_CALC_OP2_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, 0u); + + /* Securely import p */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImportP, mcuxClPkc_SecureImportBigEndianToPkc(pSession, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */), + pKey->pMod1->pKeyEntryData, + byteLenPQ)); + if (MCUXCLPKC_STATUS_OK != ret_SecImportP) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /* Generate random number used for blinding and set LSB to 1, to ensure it is odd and non-null */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate2, mcuxClRandom_ncGenerate(pSession, (uint8_t *) pBlind, blindLen)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + pBlind[0] |= 0x1u; + + /* Blind p */ + MCUXCLPKC_FP_CALC_OP1_MUL(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0); + + /************************************************************************************************/ + /* Prepare Montgomery parameters and convert parameters to Montgomery representation. */ + /************************************************************************************************/ + + /* Calculate Ndash of p */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */); + + /* Calculate input Cp_b = C mod p_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(blindedPrimeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(modAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_FP_CALC_MC2_MR(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* Cp */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_INPUT /* C */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */); + + /* Calculate QDash */ + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */); + MCUXCLMATH_FP_QDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */, (uint16_t)(modAlignLen + blindedPrimeAlignLen)); + + /* Convert input to Montgomery representation i.e. Cp_bm = Cp_b*QDash mod p_b */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* Cp_bm */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* Cp_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */); + + /************************************************************************************************/ + /* Perform secure exponentiation: Mp_bm = (Cp_bm^dq) mod p_b */ + /************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecModExpDP, + MCUXCLMATH_SECMODEXP(pSession, + pKey->pExp1->pKeyEntryData, /* dp */ + pExpTemp, + pKey->pExp1->keyEntryLength, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_R, /* Result */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, /* Montgomery representation of base number: Cp*QDash mod p_b */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B, /* Modulus p_b (blinded p) */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_TE, /* Temporary buffers */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1) ); + if (MCUXCLMATH_STATUS_OK != ret_SecModExpDP) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /************************************************************************************************/ + /* Calculate QDash for p_b */ + /************************************************************************************************/ + + const uint32_t qDashAlignLen = MCUXCLRSA_MAX(blindedPrimeAlignLen, qInvAlignLen + MCUXCLRSA_PKC_WORDSIZE); + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */); + MCUXCLMATH_FP_QDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET5 /* shifted modulus */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* temp */, (uint16_t)qDashAlignLen); + + /************************************************************************************************/ + /* call the FUP to do the below steps */ + /* Calculate Mq_bm = Mq_b * QDash mod p_b */ + /* Calculate T1_mb = Mp_bm - Mq_bm mod p_b */ + /************************************************************************************************/ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(qDashAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(blindedPrimeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_PrivateCrt_T1mb_FUP, + mcuxClRsa_PrivateCrt_T1mb_FUP_LEN); + /************************************************************************************************/ + /* Securely import qInv and convert to Montgomery form with additive blinding */ + /************************************************************************************************/ + + /* Clear buffers T0, T1 and T2 */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, qInvAlignLen); + MCUXCLPKC_PS2_SETLENGTH(0u, (uint32_t) bufferSizePrimeT0 + bufferSizePrimeT1 + bufferSizePrimeT2); + MCUXCLPKC_FP_CALC_OP2_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, 0u); + + /* Securely import qInv */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImportQInv, mcuxClPkc_SecureImportBigEndianToPkc(pSession, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* temp */), + pKey->pQInv->pKeyEntryData, + byteLenQInv)); + if (MCUXCLPKC_STATUS_OK != ret_SecImportQInv) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /* Generate random number R_qInv */ + MCUXCLPKC_PKC_CPU_ARBITRATION_WORKAROUND(); // avoid CPU accessing to PKC workarea when PKC is busy + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate3, mcuxClRandom_ncGenerate(pSession, pPrimeT1, qInvAlignLen)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate3) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /* Blind qInv with additive blinding: qInv_b = qInv + R_qInv */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, qInvAlignLen + MCUXCLRSA_PKC_WORDSIZE /* size of output qInv_b */); + MCUXCLPKC_FP_CALC_OP1_ADD(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET2 /* qInv_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* qInv */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* R_qInv */); + + /* Calculate T2_mb = QDash*qInv_b mod p_b */ + /* Calculate T3_mb = QDash*R_qInv mod p_b */ + /* Calculate qInv_bm = T2_mb-T3_mb mod p_b */ + /* Calculate T4_mb = T1_mb*qInv_bm mod p_b */ + /* Convert back into normal representation: T4_b = T4_mb mod p_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(qDashAlignLen, blindedPrimeAlignLen); /* LEN = blindedPrimeAlignLen is OK as buffer T1 has been cleared */ + MCUXCLPKC_PS2_SETLENGTH(blindedPrimeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_PrivateCrt_T2T3T4mb_FUP, + mcuxClRsa_PrivateCrt_T2T3T4mb_FUP_LEN); + + /************************************************************************************************/ + /* Calculate Garner CRT recombination */ + /************************************************************************************************/ + + /* Clear PKC buffer before the import of q */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, primeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(0u, (uint32_t) bufferSizePrimeT0); + MCUXCLPKC_FP_CALC_OP2_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, 0u); + + /* Securely import q */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecImportQ, mcuxClPkc_SecureImportBigEndianToPkc(pSession, + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET4 /* temp */), + pKey->pMod2->pKeyEntryData, + byteLenPQ)); + if (MCUXCLPKC_STATUS_OK != ret_SecImportQ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + + /* Calculate T5_b = T4_b*q in MODT4 which has a size of (primeAlignLen + blindedPrimeAlignLen = blindedMessageAlignLen) */ + /* Calculate masked message M_b = T5_b + Mq_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(primeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_PS2_SETLENGTH(0u, blindedMessageAlignLen); + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_PrivateCrt_CalcM_b_FUP, + mcuxClRsa_PrivateCrt_CalcM_b_FUP_LEN); + + /************************************************************************************************/ + /* Calculate modulus N from P and Q */ + /************************************************************************************************/ + + /* Blind q with same random as p, to obtain q_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, primeAlignLen); + MCUXCLPKC_FP_CALC_OP1_MUL(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* q_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND /* blind */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* q */); + + /* Calculate blinded modulus: N_b = p_b*q_b */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, blindAlignLen); + MCUXCLPKC_PS2_SETLENGTH(blindedPrimeAlignLen, blindedPrimeAlignLen); + MCUXCLPKC_FP_CALC_MC2_PM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* N_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PQ_B /* p_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /*q_b */); + + /* Calculate square of blinding value (blind)^2 */ + MCUXCLPKC_FP_CALC_OP1_MUL(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* (blind)^2 */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND /* blind */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_RAND /* blind */); + + /* Calculate modulus N = N_b / ((blind)^2). Note that (blind)^2 is non-null and odd. */ + MCUXCLMATH_FP_EXACTDIVIDEODD(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* N_b */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET0 /* (blind)^2 */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_PRIMET1 /* temp buffer */, + blindedModAlignLen, /* size of N_b */ + blindSquaredAlignLen /* size of (blind)^2: one PKC word */); + + /************************************************************************************************/ + /* Check that modulus is odd; otherwise return MCUXCLRSA_STATUS_INVALID_INPUT. */ + /************************************************************************************************/ + + MCUXCLPKC_WAITFORFINISH(); + if(0U == (pN[0u] & 0x01U)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT, + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_MUL, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + 3u * MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), + 2u * MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD, + MCUXCLPKC_FP_CALLED_CALC_MC1_PM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivideOdd)); + } + + /************************************************************************************************/ + /* Check that input C < N */ + /************************************************************************************************/ + + /* Compare C and N */ + MCUXCLPKC_PS1_SETLENGTH(0u, modAlignLen); + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_INPUT /* C */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */); + + uint32_t carryFlag = MCUXCLPKC_WAITFORFINISH_GETCARRY(); + if(MCUXCLPKC_FLAG_CARRY != carryFlag) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INVALID_INPUT, + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_MUL, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + 3u * MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), + 2u * MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD, + MCUXCLPKC_FP_CALLED_CALC_MC1_PM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivideOdd), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP); + + } + + /************************************************************************************************/ + /* Calculate message M from M_b */ + /************************************************************************************************/ + + /* Calculate Ndash of N */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* temp */); + + /* Calculate QDash of N */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(modAlignLen, modAlignLen); + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* shifted modulus */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */); + MCUXCLMATH_FP_QDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 /* QDash */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* shifted modulus */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* temp */, (uint16_t)blindedMessageAlignLen /* size of M_b */); + + /* Calculate reduction M_br of M_b mod N */ + /* Calculate message M1 = M_br * QDash mod N */ + /* Normalize result (case if M1 > N) */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS2_SETLENGTH(blindedMessageAlignLen /* size of M_b */, modAlignLen); + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_PrivateCrt_CalcM1_FUP, + mcuxClRsa_PrivateCrt_CalcM1_FUP_LEN); + MCUXCLPKC_WAITFORFINISH(); + + /************************************************************************************************/ + /* Protection against FA: in case of key type MCUXCLRSA_KEY_PRIVATECRT_DFA, */ + /* use obtained message M and public exponent to calculate C', and compare with input C */ + /************************************************************************************************/ + + if(MCUXCLRSA_KEY_PRIVATECRT != pKey->keytype) + { + /************************************************************************************************/ + /* Prepare Montgomery parameters and convert parameters to Montgomery representation. */ + /************************************************************************************************/ + + /* Calculate QSquared */ + MCUXCLMATH_FP_QSQUARED(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* shifted modulus */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* temp */); + + /* Convert input to Montgomery representation i.e. M*QSquared mod N */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* M*QSquared mod N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_M /* M */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */); + + /************************************************************************************************/ + /* Calculate (M^e) mod N in Montgomery representation: call mcuxClMath_ModExp_SqrMultL2R */ + /* Return checking is unnecessary, because it always returns OK. */ + /************************************************************************************************/ + + /* mcuxClMath_ModExp_SqrMultL2R(pExp, byteLenExp, iR_iX_iN_iT); */ + MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pKey->pExp3->pKeyEntryData, pKey->pExp3->keyEntryLength, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT1 /* result: (M^e) mod N in MR */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT2 /* M*QSquared mod N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_N /* N */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_MODT4 /* temp */); + + /* Convert from Montgomery to normal representation */ + /* Normalize the result (case if R > N) and copy to the temp buffer for C' */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_PrivateCrt_ReductionME_FUP, + mcuxClRsa_PrivateCrt_ReductionME_FUP_LEN); + MCUXCLPKC_WAITFORFINISH(); + MCUX_CSSL_FP_FUNCTION_CALL(compare_result, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pInput, pModT2, exactModByteLength), + pInput /* input C */, + pModT2 /* calculated C' */, + exactModByteLength)); + + if(compare_result != MCUXCSSLMEMORY_STATUS_EQUAL) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_ERROR); + } + } + + /************************************************************************************************/ + /* Export result */ + /************************************************************************************************/ + + /* Copy result to the output buffer */ + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pOutput, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVCRT_M /* M */, exactModByteLength); + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privateCRT, MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK, + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SecureImportBigEndianToPkc), + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + 4u * MCUXCLPKC_FP_CALLED_CALC_OP1_MUL, + 3u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + 3u * MCUXCLPKC_FP_CALLED_CALC_MC1_MR, + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QDash), + 2u * MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + 2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp), + 4u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUXCLPKC_FP_CALLED_CALC_OP1_ADD, + MCUXCLPKC_FP_CALLED_CALC_MC1_PM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivideOdd), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_KEY_PRIVATECRT != pKey->keytype), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) + ), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt_FUP.c new file mode 100644 index 000000000..f874618dc --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivateCrt_FUP.c @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_CalcM1_FUP[4] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x10u,0x7du,0x59u,0x78u},{0xc0u,0x33u,0x0eu,0x00u,0x10u,0x0fu},{0x80u,0x00u,0x0cu,0x0fu,0x10u,0x0eu},{0x80u,0x2au,0x10u,0x0eu,0x10u,0x0bu}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_CalcM_b_FUP[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x34u,0x74u,0x47u,0xddu},{0x80u,0x13u,0x03u,0x04u,0x00u,0x0fu},{0x40u,0x3eu,0x00u,0x00u,0x11u,0x10u},{0x00u,0x1eu,0x00u,0x06u,0x11u,0x10u},{0x40u,0x0au,0x00u,0x0fu,0x10u,0x0eu}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_ReductionME_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x74u,0xc2u,0xe3u,0xbdu},{0x80u,0x33u,0x0cu,0x00u,0x10u,0x0fu},{0x80u,0x2au,0x10u,0x0fu,0x10u,0x0du}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_T1mb_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xf7u,0x3au,0x71u,0x0au},{0x80u,0x00u,0x07u,0x06u,0x02u,0x03u},{0xc0u,0x2au,0x02u,0x09u,0x03u,0x0au}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_PrivateCrt_T2T3T4mb_FUP[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xf7u,0xc6u,0x6cu,0x8eu},{0x80u,0x00u,0x07u,0x05u,0x02u,0x03u},{0x80u,0x00u,0x07u,0x04u,0x02u,0x05u},{0xc0u,0x2au,0x02u,0x03u,0x05u,0x04u},{0xc0u,0x00u,0x0au,0x04u,0x02u,0x03u},{0xc0u,0x33u,0x03u,0x00u,0x02u,0x04u}}; + + +/* + * FUP to calculate Mp_bm - Mq_bm mod p_b + * PS1 len: (qDashAlignLen, blindedPrimeAlignLen) + * PS2 len: (blindedPrimeAlignLen, blindedPrimeAlignLen) + */ + +/* + * FUP to calculate T2_mb, T3_mb, qInv_bm, T4_mb, T4_b + * PS1 len: (qDashAlignLen, blindedPrimeAlignLen) + * PS2 len: (blindedPrimeAlignLen, blindedPrimeAlignLen) + */ + +/* + * FUP to calculate the masked message M_b + * PS1 len: (primeAlignLen, blindedPrimeAlignLen) + * PS2 len: (0u, blindedMessageAlignLen) + */ + +/* + * FUP to calculate and normalized the message M1 + * PS1 len: (modAlignLen, modAlignLen) + * PS2 len: (blindedMessageAlignLen, modAlignLen) + */ + +/* + * FUP to montgomery reduction on M^E + * PS1 len: (modAlignLen, modAlignLen) + * PS2 len: (blindedMessageAlignLen, modAlignLen) + */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivatePlain.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivatePlain.c new file mode 100644 index 000000000..fc356a1c7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PrivatePlain.c @@ -0,0 +1,293 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_PrivatePlain.c + * @brief mcuxClRsa: implementation of RSA private plain key operation + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_privatePlain) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_privatePlain( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_Buffer_t pInput, + mcuxCl_Buffer_t pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_privatePlain); + + /************************************************************************************************/ + /* Check the key type and key data; */ + /* if they are incorrect, MCUXCLRSA_STATUS_INVALID_INPUT is returned */ + /************************************************************************************************/ + if(MCUXCLRSA_KEY_PRIVATEPLAIN != pKey->keytype) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pMod1->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + const uint8_t* const pExp = pKey->pExp1->pKeyEntryData; + if(NULL == pExp) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /************************************************************************************************/ + /* Check that modulus is odd and that 64 < pKey->pMod1->keyEntryLength < 512 or 1024; */ + /* otherwise return MCUXCLRSA_STATUS_INVALID_INPUT. */ + /************************************************************************************************/ + + const uint32_t byteLenN = pKey->pMod1->keyEntryLength; + const uint32_t byteLenD = pKey->pExp1->keyEntryLength; + + if((byteLenN < 64U) || (byteLenN > MCUXCLRSA_MAX_MODLEN) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(0U == (pKey->pMod1->pKeyEntryData[byteLenN - 1U] & 0x01U)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + + /************************************************************************************************/ + /* Initialization */ + /************************************************************************************************/ + + /* Prepare buffers in PKC workarea and clear PKC workarea */ + const uint32_t blindLen = MCUXCLRSA_INTERNAL_PRIVATEPLAIN_BLINDING_SIZE; // length in bytes of the random value used for blinding + const uint32_t operandSize = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenN); + const uint32_t blindAlignLen = MCUXCLRSA_PKC_ROUNDUP_SIZE(blindLen); + const uint32_t blindOperandSize = operandSize + blindAlignLen; + + const uint16_t bufferSizeR = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of the result of the exponentiation + const uint16_t bufferSizeN = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of N + PKC word in front of the modulus buffer for NDash + const uint16_t bufferSizeT0 = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T0 + const uint16_t bufferSizeT1 = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T1 + const uint16_t bufferSizeT2 = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T2 + const uint16_t bufferSizeT3 = (uint16_t)blindOperandSize + MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer T3 + const uint16_t bufferSizeTE = (uint16_t)6u*MCUXCLRSA_PKC_WORDSIZE; // size of temp buffer TE + const uint16_t bufferSizeRand = (uint16_t)blindAlignLen; // size of buffer for random multiplicative blinding + + /* Setup session. */ + const uint16_t bufferSizeTotal = bufferSizeR + bufferSizeN + bufferSizeT0 + bufferSizeT1 + bufferSizeT2 + bufferSizeT3 + bufferSizeTE + bufferSizeRand; + const uint32_t pkcWaSizeWord = (uint32_t) bufferSizeTotal / (sizeof(uint32_t)); + uint32_t *pPkcWorkarea = mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + uint8_t *pPkcWorkarea8 = (uint8_t *)pPkcWorkarea; + + /* Setup UPTR table. */ + const uint32_t cpuWaSizeWord = (((sizeof(uint16_t)) * MCUXCLRSA_INTERNAL_PRIVPLAIN_UPTRT_SIZE) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + uint32_t * pOperands32 = mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) pOperands32; + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X] = MCUXCLPKC_PTR2OFFSET(pInput); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + MCUXCLRSA_PKC_WORDSIZE /* for NDash stored in the PKC word in front of the modulus */); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + bufferSizeN); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T1] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + bufferSizeN + bufferSizeT0); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + bufferSizeN + bufferSizeT0 + bufferSizeT1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T3] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + bufferSizeN + bufferSizeT0 + bufferSizeT1 + bufferSizeT2); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_TE] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea8 + bufferSizeR + bufferSizeN + bufferSizeT0 + bufferSizeT1 + bufferSizeT2 + bufferSizeT3); + uint32_t *pBlind = (pPkcWorkarea + ((size_t)bufferSizeR + bufferSizeN + bufferSizeT0 + bufferSizeT1 + bufferSizeT2 + bufferSizeT3 + bufferSizeTE)/sizeof(uint32_t)); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_RAND] = MCUXCLPKC_PTR2OFFSET((uint8_t *) pBlind); + + /* Set UPTRT table */ + MCUXCLPKC_SETUPTRT(pOperands); + + /* Clear PKC workarea after input */ + // TODO CLNS-6350: analyze what should be cleared + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear(pInput + byteLenN, MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(byteLenN) - byteLenN, + MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(byteLenN) - byteLenN)); + + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSizeTotal); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R, 0u); + MCUXCLPKC_WAITFORREADY(); + + /* Prepare expTemp buffer in CPU workarea - aligned to CPU word, length=MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(byteLenExp) */ + uint32_t * pExpTemp = pOperands32 + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE((MCUXCLRSA_INTERNAL_PRIVPLAIN_UPTRT_SIZE * sizeof(uint16_t)))/sizeof(uint32_t); /* Cast to CPU word aligned. */ + /************************************************************************************************/ + /* Copy (with reverse order) key material to target buffer in PKC workarea */ + /************************************************************************************************/ + + /* Import N. */ + MCUXCLPKC_PS1_SETLENGTH(0u, operandSize); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0, pKey->pMod1->pKeyEntryData, byteLenN); + + /************************************************************************************************/ + /* Check that Input < pKey->pMod1; otherwise return MCUXCLRSA_STATUS_INVALID_INPUT */ + /* If input is zero or one, return zero or one respectively */ + /************************************************************************************************/ + + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0); + MCUXCLPKC_WAITFORFINISH(); + + uint32_t carryFlag = MCUXCLPKC_GETCARRY(); + + if(MCUXCLPKC_FLAG_CARRY != carryFlag) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST); + } + + /* Compare input to 1. Note that in order to do that in one operation, result has to be written to a temporary buffer */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X, 1u); + MCUXCLPKC_WAITFORFINISH(); + + carryFlag = MCUXCLPKC_GETCARRY(); + uint32_t zeroFlag = MCUXCLPKC_GETZERO(); + + /* CARRY=1 ==> input=0, and ZERO=1 ==> input=1. In both cases, return input */ + if((MCUXCLPKC_FLAG_CARRY == carryFlag) || (MCUXCLPKC_FLAG_ZERO == zeroFlag)) + { + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pOutput, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X, byteLenN); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc)); + } + + /* Generate random number used for blinding */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate1, mcuxClRandom_ncGenerate(pSession, (uint8_t *) pBlind, blindLen)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_ERROR); + } + /* Make it odd */ + pBlind[0] |= 0x1u; + + /* Blind modulus n */ + MCUXCLPKC_FP_CALC_OP1_MUL( MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N /* n_b */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_RAND /* blind */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0 /* n */); + + /************************************************************************************************/ + /* Prepare Montgomery parameters and convert parameters to Montgomery representation. */ + /************************************************************************************************/ + + /* Calculate Ndash of N */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(blindOperandSize, blindOperandSize); + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0); + + /* Calculate QSquared */ + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T3, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N); //shift modulus + MCUXCLMATH_FP_QSQUARED(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T3, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0); + + /* Convert input to Montgomery representation i.e. M*QSquared mod N */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2 /* Mm */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X /* M */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N); + + MCUXCLPKC_WAITFORFINISH(); + + /************************************************************************************************/ + /* Perform secure exponentiation. */ + /************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(ret_SecModExp, + MCUXCLMATH_SECMODEXP(pSession, + pExp, + pExpTemp, + byteLenD, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R, /* Result */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2, /* Montgomery representation of base number */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N, /* Modulus */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_TE, /* Temporary buffers */ + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T0, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T3) ); + if (MCUXCLMATH_STATUS_OK != ret_SecModExp) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_ERROR); + } + + /************************************************************************************************/ + /* Convert result back to normal representation and store result in pOutput. */ + /************************************************************************************************/ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClRsa_RemoveBlinding( + MCUXCLPKC_PACKARGS4(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X /* R */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_R /* Rb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_N /* Nb */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_RAND /* b */), + MCUXCLPKC_PACKARGS2(MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T2, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_T1), + blindOperandSize, + blindAlignLen)); + + /* Copy result to the output buffer */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_PS1_SETLENGTH(0u, operandSize); + MCUXCLPKC_FP_EXPORTBIGENDIANFROMPKC(pOutput, MCUXCLRSA_INTERNAL_UPTRTINDEX_PRIVPLAIN_X, byteLenN); + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_privatePlain, MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), + MCUXCLPKC_FP_CALLED_CALC_OP1_MUL, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_SecModExp), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_RemoveBlinding), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ExportBigEndianFromPkc)); + +} + diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssEncode.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssEncode.c new file mode 100644 index 000000000..07c9d58a2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssEncode.c @@ -0,0 +1,280 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_PssEncode.c + * @brief mcuxClRsa: function, which is called to execute EMSA-PSS-ENCODE + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/**********************************************************/ +/* Specification of PSS-sign mode structures */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_224 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssEncode), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha224, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssEncode +}; +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_256 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssEncode), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha256, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssEncode +}; +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_384 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssEncode), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha384, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssEncode +}; +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Sign_Pss_Sha2_512 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssEncode), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha512, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssEncode +}; + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_pssEncode, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pssEncode( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput UNUSED_PARAM, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel UNUSED_PARAM, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput, + uint32_t * const pOutLength UNUSED_PARAM) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_pssEncode); + + /* Length of the encoded message. */ + const uint32_t emLen = keyBitLength / 8U; /* only byte-level granularity of keys is supported, thus keyBitLength is a multiple of 8 */ + /* Length of padding with 8 zero bytes. */ + const uint32_t padding1Length = MCUXCLRSA_PSS_PADDING1_LEN; + /* Length of the output of hash function. */ + const uint32_t hLen = pHashAlgo->hashSize; + /* Length of the EMSA-PSS salt. */ + const uint32_t sLen = saltlabelLength; + /* Length of M' */ + const uint32_t mprimLen = padding1Length + hLen + sLen; + /* Length of DB (and maskedDB). */ + const uint32_t dbLen = emLen - hLen - 1u; + /* Length of PS padding */ + const uint32_t padding2Length = emLen - hLen - sLen - 2u; + /* Length of PS padding plus one 0x01 byte */ + const uint32_t padding3Length = padding2Length + 1u; + + /* + * Set buffers in the PKC workarea + * M' = | M'= (padding | mHash | salt) | + */ + const uint32_t wordSizePkcWa = MCUXCLRSA_INTERNAL_PSSENCODE_MAX_WAPKC_SIZE_WO_MGF1(emLen) / sizeof(uint32_t); + mcuxCl_Buffer_t pMprim = (mcuxCl_Buffer_t) mcuxClSession_allocateWords_pkcWa(pSession, wordSizePkcWa); + if (NULL == pMprim) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + /* Pointer to the buffer for the mHash in the M'*/ + mcuxCl_Buffer_t pMHash = pMprim + padding1Length; + /* Pointer to the buffer for the salt in the M'*/ + mcuxCl_Buffer_t pSalt = pMHash + hLen; + + /* Pointer to the encoded message */ + mcuxCl_Buffer_t pEm = pOutput; + /* Pointer to the hash */ + mcuxCl_Buffer_t pH = pEm + dbLen; + + /* Note: Step 1 from EMSA-PSS-VERIFY in PKCS #1 v2.2 can be avoided because messageLength + * of function mcuxClRsa_sign is of type uint32_t and thus limited to 32 bits. + */ + + /* Step 3: If emLen < hLen + sLen + 2, output "encoding error" and stop. */ + /* + * Here: If BYTE_LENGTH(keyBitLength) < (pHashAlgo->hashSize + saltlabelLength + 2) + * return MCUXCLRSA_STATUS_INVALID_INPUT else continue operation. + * + * Note: The check in Step 3 is moved before Step 2, since all lengths are already known. + * Thus, no unnecessary hashing is performed in case of invalid input. + * + * Note: Additional checks on salt-length for FIPS 186-4 compliance are also done here. + */ + + if((emLen < (hLen + sLen + 2u)) || (hLen < sLen) || ((1024u == keyBitLength) && (512u == (8u * hLen)) && ((hLen - 2u) < sLen))) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /* Step 2: Let mHash = Hash(M), an octet string of length hLen. */ + + if(MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Call hash function on pInput (Hash(pInput)) and store result in buffer mHash */ + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result1, mcuxClHash_compute(pSession, + pHashAlgo, + pInput, + inputLength, + pMHash, + &hashOutputSize + )); + + if(MCUXCLHASH_STATUS_OK != hash_result1) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_ERROR); + } + } + else if (MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Copy pInput to buffer mHash */ + MCUXCLMEMORY_FP_MEMORY_COPY(pMHash, pInput, hLen); + } + else + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 4: Generate a random octet string salt of length sLen; if sLen = 0, then salt is the empty string. */ + MCUX_CSSL_FP_FUNCTION_CALL(ret_Random_ncGenerate, mcuxClRandom_ncGenerate(pSession, pSalt, sLen)); + if (MCUXCLRANDOM_STATUS_OK != ret_Random_ncGenerate) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 5: Let M' = (0x)00 00 00 00 00 00 00 00 || mHash || salt; */ + /* M' is an octet string of length 8 + hLen + sLen with eight initial zero octets. */ + + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear(pMprim, padding1Length, padding1Length)); + + /* Step 6: Let H = Hash(M'), an octet string of length hLen. */ + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result_2, mcuxClHash_compute(pSession, + pHashAlgo, + pMprim, + mprimLen, + pH, + &hashOutputSize + )); + + + if(MCUXCLHASH_STATUS_OK != hash_result_2) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 9: Let dbMask = MGF(H, emLen - hLen - 1). */ + /* Note: Step 9 has been moved up. Compute the MGF first and store the resulting mask directly in the + * output buffer, where it is adjusted afterwards. This saves temporary buffer space and copy operations. + */ + MCUX_CSSL_FP_FUNCTION_CALL(retVal_mcuxClRsa_mgf1, mcuxClRsa_mgf1(pSession, pHashAlgo, pH, hLen, dbLen, pEm)); + + if(MCUXCLRSA_STATUS_INTERNAL_MGF_OK != retVal_mcuxClRsa_mgf1) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 7: Generate an octet string PS consisting of emLen - sLen - hLen - 2 zero octets. */ + /* The length of PS may be 0. */ + /* Step 8: Let DB = PS || 0x01 || salt; DB is an octet string of length emLen - hLen - 1. */ + /* Step 10: Let maskedDB = DB \xor dbMask. */ + + /* PS consists of zeros only, so the first len(PS) bytes in the output buffer can be left as + * they are because XOR with zero does not change the values. + * The other items in DB, 0x01 and the salt, will be XORed directly onto the output buffer. + */ + + /* XOR 0x01 to the output buffer at the corresponding position. */ + *(pEm + padding2Length) ^= 0x01u; + + /* XOR the salt to the output buffer at the corresponding positions. */ + MCUX_CSSL_FP_LOOP_DECL(loop1); + for(uint32_t i = 0u; i < sLen; ++i) + { + *(pEm + padding3Length + i) ^= *(pSalt + i); + MCUX_CSSL_FP_LOOP_ITERATION(loop1); + } + + /* Step 11: Set the leftmost 8emLen - emBits bits of the leftmost octet in maskedDB to zero. */ + /* Since we assume the key length to be a multiple of 8, this becomes simply the leftmost bit. */ + + *(pEm) &= 0x7fu; + + /* Step 12: Let EM = maskedDB || H || 0xbc. */ + + *(pEm + emLen - 1U) = 0xbcu; + + /* Step 13: Output EM. */ + /* Switch endianess of EM buffer in-place to little-endian byte order. */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("the pEm PKC buffer is CPU word aligned.") + MCUXCLPKC_FP_SWITCHENDIANNESS((uint32_t *) pEm, emLen); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + +/* Use temporary defines to avoid preprocessor directives inside the function exit macro below, + as this would violate the MISRA rule 20.6 otherwise. */ + #define TMP_FEATURE_ELS_RNG \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRandom_ncGenerate), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssEncode, MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + TMP_FEATURE_ELS_RNG, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_mgf1), + MCUX_CSSL_FP_LOOP_ITERATIONS(loop1, sLen), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness)); + +#undef TMP_FEATURE_ELS_RNG +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssVerify.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssVerify.c new file mode 100644 index 000000000..9af1d568a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_PssVerify.c @@ -0,0 +1,370 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_PssVerify.c + * @brief mcuxClRsa: function, which is called to execute EMSA-PSS-VERIFY + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + + +/**********************************************************/ +/* Specification of PSS-verify mode structures */ +/**********************************************************/ +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_224 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssVerify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha224, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssVerify +}; + +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_256 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssVerify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha256, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssVerify +}; +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_384 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssVerify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha384, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssVerify +}; +const mcuxClRsa_SignVerifyMode_t mcuxClRsa_Mode_Verify_Pss_Sha2_512 = +{ + .EncodeVerify_FunId = MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_pssVerify), + .pHashAlgo1 = &mcuxClHash_AlgorithmDescriptor_Sha512, + .pHashAlgo2 = NULL, + .pPaddingFunction = mcuxClRsa_pssVerify +}; + +/* Define to avoid preprocessor directives inside the function exit macro, + as this would violate the MISRA rule 20.6 otherwise. */ +#define FP_RSA_PSSVERIFY_SWITCHENDIANNESS \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_SwitchEndianness) + +/* Macros to switch endianness */ +#define MCUXCLRSA_INTERNAL_SWITCHENDIANNESS(ptr, length) MCUXCLPKC_FP_SWITCHENDIANNESS(ptr, length) + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_pssVerify, mcuxClRsa_PadVerModeEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_pssVerify( + mcuxClSession_Handle_t pSession, + mcuxCl_InputBuffer_t pInput, + const uint32_t inputLength, + mcuxCl_Buffer_t pVerificationInput, + mcuxClHash_Algo_t pHashAlgo, + const uint8_t * pLabel UNUSED_PARAM, + const uint32_t saltlabelLength, + const uint32_t keyBitLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput UNUSED_PARAM, + uint32_t * const pOutLength UNUSED_PARAM) +{ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_pssVerify); + + /* Setup session. */ + + /* Length of the encoded message. */ + const uint32_t emLen = keyBitLength / 8U; /* only byte-level granularity of keys is supported, thus keyBitLength is a multiple of 8 */ + /* Length of padding with 8 zero bytes. */ + const uint32_t padding1Length = MCUXCLRSA_PSS_PADDING1_LEN; + /* Length of the output of hash function. */ + const uint32_t hLen = pHashAlgo->hashSize; + /* Length of the EMSA-PSS salt. */ + const uint32_t sLen = saltlabelLength; + /* Length of DB (and maskedDB). */ + const uint32_t dbLen = emLen - hLen - 1U; + + const uint16_t wordSizePkcWa = (uint16_t)(MCUXCLRSA_INTERNAL_PSSVERIFY_MAX_WAPKC_SIZE_WO_MGF1(emLen) / sizeof(uint32_t)); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, wordSizePkcWa); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* + * Set buffers in PKC workarea + * PKC = | M'= (padding | mHash | salt) || dbMask (and DB) || H' | + */ + /* Pointer to the encoded message */ + mcuxCl_Buffer_t pEm = pVerificationInput; + /* Pointer to the buffer for the M' = | padding_1 | mHash | salt | */ + mcuxCl_Buffer_t pMprim = pPkcWorkarea; + /* Pointer to the buffer for the mHash in the M'*/ + mcuxCl_Buffer_t pMHash = pMprim + padding1Length; + /* Pointer to the buffer for the salt in the M'*/ + mcuxCl_Buffer_t pSalt = pMHash + hLen; + + /* Pointer to the buffer for the dbMask'*/ + mcuxCl_Buffer_t pDbMask = pSalt + MCUXCLRSA_ROUND_UP_TO_CPU_WORDSIZE(sLen); + /* Pointer to the buffer for the H' */ + mcuxCl_Buffer_t pHprim = pDbMask + dbLen; + + const uint32_t mprimLen = padding1Length + hLen + sLen; + + /* Step 2: Let mHash = Hash(M), an octet string of length hLen. */ + if(MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Call hash function on pInput (Hash(pInput)) and store result in buffer mHash */ + uint32_t hashOutputSize = 0u; + + MCUX_CSSL_FP_FUNCTION_CALL(hash_result1, mcuxClHash_compute(pSession, + pHashAlgo, + pInput, + inputLength, + pMHash, + &hashOutputSize + )); + + if(MCUXCLHASH_STATUS_OK != hash_result1) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_ERROR); + } + } + else if (MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)) + { + /* Copy pInput to buffer mHash */ + MCUXCLMEMORY_FP_MEMORY_COPY(pMHash, pInput, hLen); + } + else + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 3: If BYTE_LENGTH(keyBitLength) < (pHashAlgo->hashSize + saltlabelLength + 2) + * return MCUXCLRSA_STATUS_VERIFY_FAILED else continue operation. */ + /* Additional checks on salt-length for FIPS 186-4 compliance */ + /* The constraint on sLen for FIPS186.5 is always met, so no additional check is needed. In step 10, we check that the zero-padding has the expected length w.r.t. sLen. */ + /* Step 4: Check if the leftmost octet of Em (before endianess switch) has hexadecimal value 0xbc.*/ + if((((1024U == keyBitLength) && (512U == (8U * hLen)) && ((hLen - 2U) < sLen)) || (hLen < sLen)) + || (emLen < (hLen + sLen + 2U)) || (0xbcU != *pEm)) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_VERIFY_FAILED, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy))); + } + + /* Switch endianess of EM buffer to big-endian byte order in place */ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("the pEm PKC buffer is CPU word aligned.") + MCUXCLRSA_INTERNAL_SWITCHENDIANNESS((uint32_t *) pEm, emLen); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + + /* Step 5: Let maskedDB be the leftmost emLen-hLen-1 octets of EM and let H be the next hLen octets. */ + mcuxCl_Buffer_t maskedDB = pEm; + mcuxCl_Buffer_t pH = pEm + dbLen; + + /* Step 6: Check if 8*emLen-emBits leftmost bits equal to zero. Note that, as keyBitLength is a multiple of 8, 8 * emLen - emBits = 1 bit.*/ + if(0U != ((*maskedDB) & 0x80u)) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_VERIFY_FAILED, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + FP_RSA_PSSVERIFY_SWITCHENDIANNESS); + } + + /* Step 7: dbMask = MGF(H, BYTE_LENGTH(keyBitLength) - pHashAlgo->hashSize - 1) */ + + MCUX_CSSL_FP_FUNCTION_CALL(retVal_mcuxClRsa_mgf1, mcuxClRsa_mgf1(pSession, pHashAlgo, pH, hLen, dbLen, pDbMask)); + + if(MCUXCLRSA_STATUS_INTERNAL_MGF_OK != retVal_mcuxClRsa_mgf1) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 8: DB = pOutput(0 : BYTE_LENGTH(keyBitLength) - pHashAlgo->hashSize - 1) XOR dbMask.*/ + mcuxCl_Buffer_t pDB = pDbMask; // reuse the space of DbMask + + MCUX_CSSL_FP_LOOP_DECL(loop1); + for(uint32_t i = 0u; i < dbLen; ++i) + { + *(pDB + i) = *(maskedDB + i) ^ *(pDbMask + i); + MCUX_CSSL_FP_LOOP_ITERATION(loop1); + } + + /* Step 9: Set the leftmost 8emLen - emBits bits of the leftmost octet in DB to zero. */ + pDB[0] &= 0x7Fu; + + /* Step 10 */ + /* Check (DB(0 : BYTE_LENGTH(keyBitLength) - pHashAlgo->hashSize - saltlabelLength - 2) == [0x00, ..., 0x00]) + * and that (DB(BYTE_LENGTH(keyBitLength) - pHashAlgo->hashSize - saltlabelLength - 1) == 0x01) ? */ + uint32_t counterZeros = 0u; + const uint32_t padding2Length = emLen - hLen - sLen - 2u; + + MCUX_CSSL_FP_LOOP_DECL(loop2); + for(uint32_t i = 0u; i < padding2Length; ++i) + { + if(0u == pDB[i]) + { + ++counterZeros; + } + MCUX_CSSL_FP_LOOP_ITERATION(loop2); + } + if((counterZeros != padding2Length) || (0x01u != pDB[padding2Length])) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_VERIFY_FAILED, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + FP_RSA_PSSVERIFY_SWITCHENDIANNESS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_mgf1), + MCUX_CSSL_FP_LOOP_ITERATIONS(loop1, dbLen), + MCUX_CSSL_FP_LOOP_ITERATIONS(loop2, padding2Length)); + } + + /* Step 11: Copy salt to mPrime buffer */ + MCUXCLMEMORY_FP_MEMORY_COPY(pSalt, pDB + dbLen - sLen, sLen); + + /* Step 12 */ + /* mPrime = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 || mHash || DB(BYTE_LENGTH(keyBitLength) - saltlabelLength: BYTE_LENGTH(keyBitLength))] */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMemory_clear(pMprim, padding1Length, padding1Length)); + + /* Step 13: HPrime = Hash(mPrime) */ + uint32_t hashOutputSize = 0u; + MCUX_CSSL_FP_FUNCTION_CALL(hash_result_2, mcuxClHash_compute(pSession, + pHashAlgo, + pMprim, + mprimLen, + pHprim, + &hashOutputSize + )); + + if(MCUXCLHASH_STATUS_OK != hash_result_2) + { + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, MCUXCLRSA_STATUS_ERROR); + } + + /* Step 14 verify5 = (HPrime == H) ? true : false. */ +#ifndef MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS + MCUX_CSSL_FP_FUNCTION_CALL(compare_result, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pH, pHprim, hLen), + pH, + pHprim, + hLen)); + + mcuxClRsa_Status_t pssVerifyStatus = MCUXCLRSA_STATUS_VERIFY_FAILED; + if(compare_result == MCUXCSSLMEMORY_STATUS_EQUAL) + { + pssVerifyStatus = MCUXCLRSA_STATUS_VERIFY_OK; + } +#else + /* Becasue pH and pHprim are unaligned and taking into account the properties: + * - dbLen = emLen - hLen - 1U + * - emLen % CpuWord = 0 + * - hLen % CpuWord = 0 + * - pEm % CpuWord = 0 + * - pDbMask % CpuWord = 0 + * - pH % CpuWord = CpuWord-unalignedBytes + * - pHprim % CpuWord = CpuWord-unalignedBytes + * - unalignedBytes = (CpuWord - dbLen) & (CpuWord - 1) <- it is unaligned part of pH and pHprim + * , the first unalignedBytes bytes will be compared separately (byte-wise) then the rest will be compared with aligned address. + */ + uint32_t unalignedBytes = ((sizeof(uint32_t)) - dbLen) & ((sizeof(uint32_t)) - 1u); + MCUX_CSSL_FP_FUNCTION_CALL(compare_result1, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pH, pHprim, unalignedBytes), + pH, + pHprim, + unalignedBytes)); + + mcuxClRsa_Status_t pssVerifyStatus = MCUXCLRSA_STATUS_VERIFY_FAILED; + if(compare_result1 == MCUXCSSLMEMORY_STATUS_EQUAL) + { + pssVerifyStatus = MCUXCLRSA_STATUS_VERIFY_OK; + } + + MCUX_CSSL_FP_FUNCTION_CALL(compare_result2, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pH + unalignedBytes, + pHprim + unalignedBytes, hLen - unalignedBytes), + pH + unalignedBytes, + pHprim + unalignedBytes, + hLen - unalignedBytes)); + + if(compare_result2 == MCUXCSSLMEMORY_STATUS_EQUAL) + { + pssVerifyStatus = MCUXCLRSA_STATUS_VERIFY_OK; + } +#endif + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + mcuxClSession_freeWords_pkcWa(pSession, wordSizePkcWa); + +/* Use temporary defines to avoid preprocessor directives inside the function exit macro below, + as this would violate the MISRA rule 20.6 otherwise. */ +#if defined(MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS) + #define FP_RSA_PSSVERIFY_COMPARISON \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) +#else + #define FP_RSA_PSSVERIFY_COMPARISON \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare), \ + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear) +#endif + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_pssVerify, pssVerifyStatus, + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_PLAIN == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_OPTION_MESSAGE_DIGEST == (options & MCUXCLRSA_OPTION_MESSAGE_MASK)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy)), + FP_RSA_PSSVERIFY_SWITCHENDIANNESS, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_mgf1), + MCUX_CSSL_FP_LOOP_ITERATIONS(loop1, dbLen), + MCUX_CSSL_FP_LOOP_ITERATIONS(loop2, padding2Length), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_copy), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClHash_compute), + FP_RSA_PSSVERIFY_COMPARISON + ); + +#undef FP_RSA_PSSVERIFY_COMPARISON + +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public.c new file mode 100644 index 000000000..d213a5486 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public.c @@ -0,0 +1,245 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Public.c + * @brief mcuxClRsa: implementation of RSA Public function + */ + +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_public, mcuxClRsa_PublicExpEngine_t) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_public( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pInput, + mcuxCl_Buffer_t pOutput) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_public); + + /************************************************************************************************/ + /* Check the key type and key data; */ + /* if they are incorrect, MCUXCLRSA_STATUS_INVALID_INPUT is returned */ + /************************************************************************************************/ + if(MCUXCLRSA_KEY_PUBLIC != pKey->keytype) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(NULL == pKey->pMod1->pKeyEntryData) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + const uint8_t* const pExp = pKey->pExp1->pKeyEntryData; + if(NULL == pExp) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + + /************************************************************************************************/ + /* Check that modulus is odd and that 64 < pKey->pMod1->keyEntryLength < 512 or 1024; */ + /* otherwise return MCUXCLRSA_STATUS_INVALID_INPUT. */ + /************************************************************************************************/ + const uint32_t byteLenN = pKey->pMod1->keyEntryLength; + + if((byteLenN < 64U) || (byteLenN > MCUXCLRSA_MAX_MODLEN) ) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + if(0U == (pKey->pMod1->pKeyEntryData[byteLenN - 1U] & 0x01U)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT); + } + + /************************************************************************************************/ + /* Initialization */ + /************************************************************************************************/ + + /* Prepare buffers in PKC workarea and clear PKC workarea */ + const uint32_t operandSize = MCUXCLRSA_PKC_ROUNDUP_SIZE(byteLenN); + const uint16_t bufferSizeX = (uint16_t)operandSize; + const uint16_t bufferSizeR = (uint16_t)operandSize + MCUXCLRSA_PKC_WORDSIZE; + const uint16_t bufferSizeN = (uint16_t)operandSize + MCUXCLRSA_PKC_WORDSIZE; // PKC word in front of the modulus buffer for NDash + const uint16_t bufferSizeT1 = (uint16_t)operandSize + MCUXCLRSA_PKC_WORDSIZE; + const uint16_t bufferSizeT2 = (uint16_t)operandSize + MCUXCLRSA_PKC_WORDSIZE; + + /* Setup session. */ + const uint16_t bufferSizeTotal = bufferSizeX + bufferSizeN + bufferSizeR + bufferSizeT1 + bufferSizeT2; + const uint32_t pkcWaSizeWord = (uint32_t) bufferSizeTotal / (sizeof(uint32_t)); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* Setup UPTR table. */ + const uint32_t cpuWaSizeWord = (((sizeof(uint16_t)) * MCUXCLRSA_INTERNAL_PUBLIC_UPTRT_SIZE) + (sizeof(uint32_t)) - 1u) / (sizeof(uint32_t)); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t *pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea + bufferSizeX); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea + bufferSizeX + bufferSizeR + MCUXCLRSA_PKC_WORDSIZE /* for NDash stored in the PKC word in front of the modulus */); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea + bufferSizeX + bufferSizeR + bufferSizeN); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2] = MCUXCLPKC_PTR2OFFSET(pPkcWorkarea + bufferSizeX + bufferSizeR + bufferSizeN + bufferSizeT1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_OUTPUT] = MCUXCLPKC_PTR2OFFSET(pOutput); + + /* Set UPTRT table */ + MCUXCLPKC_SETUPTRT(pOperands); + + /* Clear PKC workarea after the input, which is located at the beginning of the workarea and has a size of byteLenN */ + MCUXCLMEMORY_FP_MEMORY_SET(pPkcWorkarea + byteLenN, 0x00U, bufferSizeTotal - byteLenN); + + /************************************************************************************************/ + /* Copy (with reverse order) input and key material to respective buffers in PKC workarea */ + /************************************************************************************************/ + + /* Import N. */ + MCUXCLPKC_PS1_SETLENGTH(0u, operandSize); + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N, pKey->pMod1->pKeyEntryData, byteLenN); + /* Import input. */ + MCUXCLPKC_FP_IMPORTBIGENDIANTOPKC(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X, pInput, byteLenN); + + /************************************************************************************************/ + /* Check that pInput < pKey->pMod1; otherwise return MCUXCLRSA_STATUS_INVALID_INPUT */ + /************************************************************************************************/ + MCUXCLPKC_FP_CALC_OP1_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N); + MCUXCLPKC_WAITFORFINISH(); + uint32_t carryFlag = MCUXCLPKC_GETCARRY(); + + if(1U != carryFlag) + { + /* Clear PKC workarea. */ + MCUXCLPKC_PS1_SETLENGTH(0u, bufferSizeTotal); + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X, 0u); + + MCUXCLPKC_WAITFORFINISH(); + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST); + } + + /* Compare input to 0. Note that in order to do that in one operation, result has to be written to a temporary buffer */ + MCUXCLPKC_FP_CALC_OP1_SUB_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X, 1U); + MCUXCLPKC_WAITFORFINISH(); + + carryFlag = MCUXCLPKC_GETCARRY(); + + /* CARRY=1 ==> input=0, return input */ + if(MCUXCLPKC_FLAG_CARRY == carryFlag) + { + MCUXCLPKC_FP_CALC_OP1_CONST(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_OUTPUT, 0u); + + MCUXCLPKC_WAITFORFINISH(); + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST, + MCUXCLPKC_FP_CALLED_CALC_OP1_CONST); + } + + /************************************************************************************************/ + /* Prepare Montgomery parameters and convert parameters to Montgomery representation. */ + /************************************************************************************************/ + + /* Calculate Ndash of N */ + MCUXCLMATH_FP_NDASH(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1); + + /* Calculate QSquared */ + MCUXCLPKC_PS1_SETLENGTH(operandSize, operandSize); + MCUXCLMATH_FP_SHIFTMODULUS(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N); //shift modulus + MCUXCLMATH_FP_QSQUARED(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2); + + /* Convert input to Montgomery representation i.e. M*QSquared mod N */ + MCUXCLPKC_FP_CALC_MC1_MM(MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1 /* Mm */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_X /* M */, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R /* QSquared */, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N); + + /************************************************************************************************/ + /* Call mcuxClMath_ModExp_SqrMultL2R */ + /* Return checking is unnecessary, because it always returns OK. */ + /************************************************************************************************/ + + //mcuxClMath_ModExp_SqrMultL2R(pExp, byteLenExp, iR_iX_iN_iT); + //R -> size lenN + PKC wordsize + //X -> size lenX + //N -> size lenN + PKC word in front of the modulus buffer for NDash + //T -> size lenN + PKC wordsize + uint32_t byteLenExp = pKey->pExp1->keyEntryLength; + MCUXCLMATH_FP_MODEXP_SQRMULTL2R(pExp, byteLenExp, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T2, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_T1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_N, MCUXCLRSA_INTERNAL_UPTRTINDEX_PUBLIC_R); + + /* Montgomery reduction and normalize the result */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_Public_ReductionME_FUP, + mcuxClRsa_Public_ReductionME_FUP_LEN); + MCUXCLPKC_WAITFORFINISH(); + + /************************************************************************************************/ + /* Function exit */ + /************************************************************************************************/ + + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_public, MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_set), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_ImportBigEndianToPkc), + MCUXCLPKC_FP_CALLED_CALC_OP1_CMP, + MCUXCLPKC_FP_CALLED_CALC_OP1_SUB_CONST, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_NDash), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ShiftModulus), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_QSquared), + MCUXCLPKC_FP_CALLED_CALC_MC1_MM, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ModExp_SqrMultL2R), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public_FUP.c new file mode 100644 index 000000000..e30620a30 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Public_FUP.c @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_Public_ReductionME_FUP[3] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x60u,0x2du,0x26u,0xfdu},{0x80u,0x33u,0x04u,0x00u,0x02u,0x01u},{0x80u,0x2au,0x02u,0x01u,0x02u,0x05u}}; + + +/* + * FUP to do montgomery reduction and normalize the result + */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding.c new file mode 100644 index 000000000..9216a1e62 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding.c @@ -0,0 +1,68 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_RemoveBlinding.c + * @brief mcuxClRsa: function, which is called to remove modulus blinding + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_RemoveBlinding) +MCUX_CSSL_FP_PROTECTED_TYPE(void) mcuxClRsa_RemoveBlinding(uint32_t iR_iX_iNb_iB, + uint16_t iT2_iT1, + uint32_t nbPkcByteLength, + uint32_t bPkcByteLength) +{ + + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_RemoveBlinding); + + /* Prepare local UPTRT. */ + uint16_t pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_UPTRT_SIZE]; + const uint16_t *backupPtrUptrt; + /* mcuxClMath_InitLocalUptrt always returns _OK. */ + MCUX_CSSL_FP_FUNCTION_CALL_VOID(mcuxClMath_InitLocalUptrt(iR_iX_iNb_iB, (uint32_t) iT2_iT1, pOperands, 6u, &backupPtrUptrt)); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_ZERO] = 0x0u; + + /* Call the FUP program to convert result of the exponentiation to normal representation modulo Nb */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_RemoveBlinding_FUP, + mcuxClRsa_RemoveBlinding_FUP_LEN); + + /* Calculate R=T1/b */ + MCUXCLMATH_FP_EXACTDIVIDE(MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_R, + MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T1, + MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_B, + MCUXCLRSA_INTERNAL_UPTRTINDEX_REMOVEBLINDING_T2, + nbPkcByteLength, + bPkcByteLength); + + /* Restore pUptrt. */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + MCUX_CSSL_FP_FUNCTION_EXIT_VOID(mcuxClRsa_RemoveBlinding, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_InitLocalUptrt), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMath_ExactDivide)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding_FUP.c new file mode 100644 index 000000000..e6132771d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_RemoveBlinding_FUP.c @@ -0,0 +1,23 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_RemoveBlinding_FUP[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x6cu,0x62u,0x79u,0x15u},{0x00u,0x3eu,0x00u,0x00u,0x06u,0x05u},{0x00u,0x6au,0x00u,0x05u,0x00u,0x04u},{0x80u,0x00u,0x04u,0x02u,0x01u,0x05u},{0x80u,0x2au,0x01u,0x05u,0x01u,0x04u}}; + + +/* + * FUP program to convert result of the exponentiation to normal representation modulo Nb. + */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Sign.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Sign.c new file mode 100644 index 000000000..a32d51f13 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Sign.c @@ -0,0 +1,258 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Sign.c + * @brief mcuxClRsa: implementation of RSA Sign function + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_sign) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_sign( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pMessageOrDigest, + const uint32_t messageLength, + const mcuxClRsa_SignVerifyMode pPaddingMode, + const uint32_t saltLength, + const uint32_t options, + mcuxCl_Buffer_t pSignature + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_sign); + + /*****************************************************/ + /* Initialization */ + /*****************************************************/ + + /* Initialize PKC */ + uint32_t cpuWaUsedBackup = mcuxClSession_getUsage_cpuWa(pSession); + MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() + mcuxClPkc_State_t * pkcStateBackup = (mcuxClPkc_State_t *) mcuxClSession_allocateWords_cpuWa(pSession, (sizeof(mcuxClPkc_State_t)) / (sizeof(uint32_t))); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() + if (NULL == pkcStateBackup) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + /*****************************************************/ + /* Perform padding operation */ + /*****************************************************/ + uint32_t pkcWaTotalSize = 0u; + + uint32_t keyBitLength = 0u; + + if(MCUXCLRSA_KEY_PRIVATEPLAIN == pKey->keytype) + { + keyBitLength = 8u * (pKey->pMod1->keyEntryLength); + pkcWaTotalSize = MCUXCLRSA_SIGN_PLAIN_WAPKC_SIZE(keyBitLength); + } + else if((MCUXCLRSA_KEY_PRIVATECRT == pKey->keytype) || (MCUXCLRSA_KEY_PRIVATECRT_DFA == pKey->keytype)) + { + MCUXCLRSA_CALC_MODLEN_FROM_CRTKEY(pKey, keyBitLength); + pkcWaTotalSize = MCUXCLRSA_SIGN_CRT_WAPKC_SIZE(keyBitLength); + } + else + { + /* De-initialize PKC */ + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + + /* Locate paddedMessage buffer at beginning of PKC WA and update session info */ + uint32_t keyByteLength = keyBitLength / 8u; + uint32_t pkcWaUsedByte = (MCUXCLRSA_KEY_PRIVATEPLAIN == pKey->keytype) ? MCUXCLRSA_INTERNAL_PRIVATEPLAIN_INPUT_SIZE(keyByteLength) : MCUXCLRSA_PKC_ROUNDUP_SIZE(keyByteLength); + uint32_t pkcWaUsedBackup = mcuxClSession_getUsage_pkcWa(pSession); + uint8_t * const pPkcWorakarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaUsedByte / (sizeof(uint32_t))); + if (NULL == pPkcWorakarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + uint8_t * pPaddedMessage = pPkcWorakarea; + + /* Call the padding function */ + MCUX_CSSL_FP_FUNCTION_CALL(retVal_PaddingOperation, pPaddingMode->pPaddingFunction( + /* mcuxClSession_Handle_t pSession, */ pSession, + /* mcuxCl_InputBuffer_t pInput, */ pMessageOrDigest, + /* const uint32_t inputLength, */ messageLength, + /* mcuxCl_Buffer_t pVerificationInput, */ NULL, + /* mcuxClHash_Algo_t pHashAlgo, */ pPaddingMode->pHashAlgo1, + /* const uint8_t * pLabel, */ NULL, + /* const uint32_t saltlabelLength, */ saltLength, + /* const uint32_t keyBitLength, */ keyBitLength, + /* const uint32_t options, */ options, + /* mcuxCl_Buffer_t pOutput */ pPaddedMessage, + /* uint32_t * const pOutLength */ NULL + )); + + if(MCUXCLRSA_STATUS_INVALID_INPUT == retVal_PaddingOperation) + { + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + pPaddingMode->EncodeVerify_FunId, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + } + else if(MCUXCLRSA_STATUS_INTERNAL_ENCODE_OK != retVal_PaddingOperation) + { + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_ERROR); + } + else + { + if (pkcWaUsedByte > keyByteLength) + { + /* Clear PKC workarea after the input */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPaddedMessage + keyByteLength, pkcWaUsedByte - keyByteLength); + } + + /*****************************************************/ + /* Perform RSA private operation */ + /*****************************************************/ + uint32_t retVal_RsaPrivate = MCUXCLRSA_STATUS_ERROR; + + if(MCUXCLRSA_KEY_PRIVATEPLAIN == pKey->keytype) + { + MCUX_CSSL_FP_FUNCTION_CALL(retVal_RsaPrivatePlain, mcuxClRsa_privatePlain(pSession, pKey, pPaddedMessage, pSignature)); + retVal_RsaPrivate = retVal_RsaPrivatePlain; + } + else if((MCUXCLRSA_KEY_PRIVATECRT == pKey->keytype) || (MCUXCLRSA_KEY_PRIVATECRT_DFA == pKey->keytype)) + { + MCUX_CSSL_FP_FUNCTION_CALL(retVal_RsaPrivateCrt, mcuxClRsa_privateCRT(pSession, pKey, pPaddedMessage, pSignature)); + retVal_RsaPrivate = retVal_RsaPrivateCrt; + } + else /* Key type has already been tested: any other type here is a fault */ + { + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_ERROR); + } + + /* Check return value */ + if(MCUXCLRSA_STATUS_INVALID_INPUT == retVal_RsaPrivate) + { + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + pPaddingMode->EncodeVerify_FunId, + MCUX_CSSL_FP_CONDITIONAL((pkcWaUsedByte > keyByteLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_KEY_PRIVATEPLAIN == pKey->keytype), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_privatePlain)), + MCUX_CSSL_FP_CONDITIONAL(((MCUXCLRSA_KEY_PRIVATECRT == pKey->keytype) || (MCUXCLRSA_KEY_PRIVATECRT_DFA == pKey->keytype)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_privateCRT)), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + } + else if(MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK != retVal_RsaPrivate) + { + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_sign, MCUXCLRSA_STATUS_ERROR); + } + else + { + /*****************************************************/ + /* Exit */ + /*****************************************************/ + + /* De-initialize PKC */ + mcuxClSession_setUsage_pkcWa(pSession, pkcWaUsedBackup); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_sign, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_setUsage_cpuWa(pSession, cpuWaUsedBackup); + + /* Clear pkcWa */ + MCUXCLMEMORY_FP_MEMORY_CLEAR(pPkcWorakarea,pkcWaTotalSize); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRsa_sign, MCUXCLRSA_STATUS_SIGN_OK, + MCUXCLRSA_STATUS_FAULT_ATTACK, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + pPaddingMode->EncodeVerify_FunId, + MCUX_CSSL_FP_CONDITIONAL((pkcWaUsedByte > keyByteLength), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)), + MCUX_CSSL_FP_CONDITIONAL((MCUXCLRSA_KEY_PRIVATEPLAIN == pKey->keytype), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_privatePlain)), + MCUX_CSSL_FP_CONDITIONAL(((MCUXCLRSA_KEY_PRIVATECRT == pKey->keytype) || (MCUXCLRSA_KEY_PRIVATECRT_DFA == pKey->keytype)), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_privateCRT)), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + } + } +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance.c new file mode 100644 index 000000000..c6b0c17dd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance.c @@ -0,0 +1,99 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_TestPQDistance.c + * @brief mcuxClRsa: function, which is called to test |p - q| <= 2^(nlen/2 - 100). + * This is a verification required by FIPS 186-4 (Appendix B.3.3, step 5.4). + * Verification is done by checking the 100 MSbits of p and q. If they are equal, + * test fail. + * + * The implementation assumes that: + * - pLen = qLen = nlen/2 = primeByteLength + * - primeByteLength is a multiple of PKC wordsize. + * - PKC wordsize is not greater than 128 bits + * + * NOTE: This function will require adaptation if need to support primeByteLength + * that is not multiple of FAME word. + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_TestPQDistance) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_TestPQDistance(uint32_t iP_iQ_iT, uint32_t primeByteLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_TestPQDistance); + + /* Set init status to ERROR */ + mcuxClRsa_Status_t status = MCUXCLRSA_STATUS_INVALID_INPUT; + + /* Backup Uptrt to recover in the end */ + const uint16_t *backupPtrUptrt = MCUXCLPKC_GETUPTRT(); + + /* Backup Ps1 length to recover in the end */ + uint32_t backupPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + + /* Create and set local Uptrt table. */ + uint16_t pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_UPTRT_SIZE]; + + const uint32_t pkcOperandLen = 128 / 8; + const uint32_t pkcPrimeLen = primeByteLength; + + /* Get iP, iQ and iT indices */ + uint32_t uptrtIndexP = (iP_iQ_iT >> 16) & 0xFFu; + uint32_t uptrtIndexQ = (iP_iQ_iT >> 8) & 0xFFu; + uint32_t uptrtIndexT = (iP_iQ_iT) & 0xFFu; + + pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P128MSB] = backupPtrUptrt[uptrtIndexP] + (uint16_t)(pkcPrimeLen - pkcOperandLen) /* ofset to the 128 MSbits */; + pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q128MSB] = backupPtrUptrt[uptrtIndexQ] + (uint16_t)(pkcPrimeLen - pkcOperandLen) /* ofset to the 128 MSbits */; + pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P100MSB] = backupPtrUptrt[uptrtIndexT]; + pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_Q100MSB] = pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_P100MSB] + (uint16_t)pkcOperandLen; + /* Set shift value (128b-100b = 27b) */ + pOperands[MCUXCLRSA_INTERNAL_TESTPQDISTANCE_CONSTANT28] = 28u; + + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(pOperands); + + /* Set Ps1 length */ + MCUXCLPKC_PS1_SETLENGTH_REG(pkcOperandLen); /* Don't care mclen @hi16. */ + + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_TestPQDistance_FUP, + mcuxClRsa_TestPQDistance_FUP_LEN); + uint32_t zeroFlag_check = MCUXCLPKC_WAITFORFINISH_GETZERO(); + if(MCUXCLPKC_FLAG_NONZERO == zeroFlag_check) + { + /* 100 MS bits of p and q are not equal */ + status = MCUXCLRSA_STATUS_KEYGENERATION_OK; + } + + /* Recover Ps1 length and Uptrt*/ + MCUXCLPKC_PS1_SETLENGTH_REG(backupPs1LenReg); + MCUXCLPKC_SETUPTRT(backupPtrUptrt); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_TestPQDistance, + status, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) + ); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance_FUP.c new file mode 100644 index 000000000..a2120666f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPQDistance_FUP.c @@ -0,0 +1,21 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPQDistance_FUP[4] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x1au,0xedu,0x1au,0x57u},{0x00u,0x15u,0x00u,0x00u,0x04u,0x02u},{0x00u,0x15u,0x00u,0x01u,0x04u,0x03u},{0x00u,0x4bu,0x00u,0x02u,0x03u,0x00u}}; + + +/* FUP to check the distance between P and Q */ diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate.c new file mode 100644 index 000000000..c72cea6ff --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate.c @@ -0,0 +1,167 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_TestPrimeCandidate.c + * @brief mcuxClRsa: function, which is called to test a prime candidate + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_TestPrimeCandidate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_TestPrimeCandidate( + mcuxClSession_Handle_t pSession, + mcuxClRsa_KeyEntry_t * pE, + mcuxClRsa_KeyEntry_t * pPrimeCandidate, + const uint32_t keyBitLength, + const uint32_t iNumToCmp_iA0) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_TestPrimeCandidate, + MCUXCLPKC_FP_CALLED_CALC_OP2_CMP); + + mcuxClRsa_Status_t status = MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_CMP_FAILED; + + const uint32_t primeByteLength = keyBitLength/8u/2u; + const uint32_t pkcOperandSize = MCUXCLRSA_PKC_ROUNDUP_SIZE(primeByteLength); + + /* Backup Ps1 length and UPTRT, resore them when returning */ + uint16_t *bakUPTRT = MCUXCLPKC_GETUPTRT(); + uint32_t bakPs1LenReg = MCUXCLPKC_PS1_GETLENGTH_REG(); + uint32_t bakPs2LenReg = MCUXCLPKC_PS2_GETLENGTH_REG(); + + /* Get iNumToCmp and iA0 indices */ + const uint32_t uptrtIndexNumToCmp = (iNumToCmp_iA0 >> 8u) & 0xFFu; + const uint32_t uptrtIndexA0 = iNumToCmp_iA0 & 0xFFu; + + /* Share the area with mcuxClRsa_MillerRabinTest*/ + const uint32_t pkcWaSizeWord = MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WAPKC_SIZE(primeByteLength) / (sizeof(uint32_t)); + uint8_t *pPkcWorkarea = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPkcWorkarea) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_TestPrimeCandidate, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + uint8_t *pGCD1 = pPkcWorkarea; + uint8_t *pGCD2 = pGCD1 + pkcOperandSize; + + /* Setup UPTR table */ + const uint32_t cpuWaSizeWord = MCUXCLRSA_INTERNAL_TESTPRIMECANDIDATE_WACPU_SIZE_WO_MILLERRABIN / sizeof(uint32_t); + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES("16-bit UPTRT table is assigned in CPU workarea") + uint16_t * pOperands = (uint16_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() + if (NULL == pOperands) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_TestPrimeCandidate, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_E] = MCUXCLPKC_PTR2OFFSET(pE->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE] = MCUXCLPKC_PTR2OFFSET(pPrimeCandidate->pKeyEntryData); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE_64MOST] = MCUXCLPKC_PTR2OFFSET(pPrimeCandidate->pKeyEntryData + pkcOperandSize - MCUXCLRSA_PKC_WORDSIZE); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_NUMTOCOMPARE] = bakUPTRT[uptrtIndexNumToCmp]; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_A0] = bakUPTRT[uptrtIndexA0]; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1] = MCUXCLPKC_PTR2OFFSET(pGCD1); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD2] = MCUXCLPKC_PTR2OFFSET(pGCD2); + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT0] = 0u; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT1] = 1u; + pOperands[MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CONSTANT2] = 2u; + + /* Set UPTRT table */ + MCUXCLPKC_WAITFORREADY(); + MCUXCLPKC_SETUPTRT(pOperands); + + MCUXCLPKC_PS1_SETLENGTH(pkcOperandSize, pkcOperandSize); + MCUXCLPKC_PS2_SETLENGTH(0u, MCUXCLRSA_PKC_WORDSIZE); + + do + { + /* + * 1. Check if prime candidate < sqrt(2)(2^((nlen/2)-1)) + * This check is done using only 64 most significant bits of sqrt(2)(2^(nlen/2)-1) + * rounded up, this is 0xb504f333f9de6485u. + * This deviation from FIPS 186-4 has been approved. + * + * Used functions: FAME operations (MCUXCLPKC_OP_CMP) + */ + MCUXCLPKC_FP_CALC_OP2_CMP(MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE_64MOST, MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_NUMTOCOMPARE); + if (MCUXCLPKC_FLAG_CARRY == MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + status = MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_CMP_FAILED; + MCUX_CSSL_FP_EXPECT(0u - (2u * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup)) - MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_MillerRabinTest)); + break; + } + + /* + * 2. Pre-check the prime candidate: GCD(prime candidate, A0) + * where: A0 - product of the first 9 prime numbers (hardcoded value). + */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_TestPrimeCandidate_Steps2_FUP, + mcuxClRsa_TestPrimeCandidate_Steps2_FUP_LEN); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + status = MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDA0_FAILED; + MCUX_CSSL_FP_EXPECT(0u - MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup) - MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_MillerRabinTest)); + break; + } + + /* + * 3. Check if prime_candidate - 1 is coprime to the public exponent e: + * GCD(prime_candidate - 1, e)) + */ + MCUXCLPKC_FP_CALCFUP(mcuxClRsa_TestPrimeCandidate_Steps3_FUP, + mcuxClRsa_TestPrimeCandidate_Steps3_FUP_LEN); + if (MCUXCLPKC_FLAG_CARRY != MCUXCLPKC_WAITFORFINISH_GETCARRY()) + { + status = MCUXCLRSA_STATUS_INTERNAL_TESTPRIME_GCDE_FAILED; + MCUX_CSSL_FP_EXPECT(0u - MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_MillerRabinTest)); + break; + } + + /* + * 4. Run Miller-Rabin test + * + * Used functions: mcuxClRsa_MillerRabinTest + */ + uint32_t iP_iT = (MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_CANDIDATE << 8u) | MCUXCLRSA_INTERNAL_UPTRTINDEX_TESTPRIME_GCD1; + MCUX_CSSL_FP_FUNCTION_CALL(retTest, mcuxClRsa_MillerRabinTest(pSession, iP_iT, keyBitLength)); + status = (mcuxClRsa_Status_t) retTest; + }while (false); + + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + MCUXCLPKC_PS1_SETLENGTH_REG(bakPs1LenReg); + MCUXCLPKC_PS2_SETLENGTH_REG(bakPs2LenReg); + MCUXCLPKC_SETUPTRT(bakUPTRT); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_TestPrimeCandidate, status, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClPkc_CalcFup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_MillerRabinTest)); +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate_FUP.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate_FUP.c new file mode 100644 index 000000000..a8220bc12 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_TestPrimeCandidate_FUP.c @@ -0,0 +1,35 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include + +#include + +const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPrimeCandidate_Steps2_FUP[6] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0xd1u,0x20u,0xd8u,0x0bu},{0x00u,0x1eu,0x00u,0x01u,0x07u,0x05u},{0x00u,0x3eu,0x00u,0x00u,0x07u,0x06u},{0x40u,0x1eu,0x00u,0x04u,0x07u,0x06u},{0x80u,0xa7u,0x05u,0x05u,0x06u,0x06u},{0x00u,0x1bu,0x00u,0x06u,0x09u,0x05u}}; +const mcuxClPkc_FUPEntry_t mcuxClRsa_TestPrimeCandidate_Steps3_FUP[5] MCUX_FUP_ATTRIBUTE = {{0x10u,0x00u,0x5fu,0x25u,0x45u,0x45u},{0x00u,0x1bu,0x00u,0x01u,0x08u,0x05u},{0x00u,0x1eu,0x00u,0x00u,0x07u,0x06u},{0x80u,0xa7u,0x05u,0x05u,0x06u,0x06u},{0x00u,0x1bu,0x00u,0x06u,0x09u,0x05u}}; + + +/* + * FUP to check the candidate is coprime with the product of first 9 + * prime. + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() + +/* + * FUP to check the candidate is coprime with the public E + */ +MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() +MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Verify.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Verify.c new file mode 100644 index 000000000..b44134845 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_Verify.c @@ -0,0 +1,142 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_Verify.c + * @brief mcuxClRsa: implementation of RSA Verify function + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_verify) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClRsa_Status_t) mcuxClRsa_verify( + mcuxClSession_Handle_t pSession, + const mcuxClRsa_Key * const pKey, + mcuxCl_InputBuffer_t pMessageOrDigest, + const uint32_t messageLength, + mcuxCl_Buffer_t pSignature, + const mcuxClRsa_SignVerifyMode pVerifyMode, + const uint32_t saltLength, + const uint32_t options, + mcuxCl_Buffer_t pOutput + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_verify); + + /*****************************************************/ + /* Initialization */ + /*****************************************************/ + + /* Locate paddedMessage buffer at beginning of PKC WA and update session info */ + const uint32_t modulusByteLength = pKey->pMod1->keyEntryLength; + const uint32_t pkcWaSizeWord = MCUXCLRSA_PKC_ROUNDUP_SIZE(modulusByteLength) / (sizeof(uint32_t)); + + uint8_t * pPaddedMessage = (uint8_t *) mcuxClSession_allocateWords_pkcWa(pSession, pkcWaSizeWord); + if (NULL == pPaddedMessage) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + /* Initialize PKC */ + const uint32_t cpuWaSizeWord = (sizeof(mcuxClPkc_State_t)) / (sizeof(uint32_t)); + mcuxClPkc_State_t * pkcStateBackup = (mcuxClPkc_State_t *) mcuxClSession_allocateWords_cpuWa(pSession, cpuWaSizeWord); + if (NULL == pkcStateBackup) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + } + + MCUXCLPKC_FP_REQUEST_INITIALIZE(pSession, pkcStateBackup, mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + + /*****************************************************/ + /* Perform RSA_public */ + /*****************************************************/ + + MCUX_CSSL_FP_FUNCTION_CALL(retVal_RsaPublic, mcuxClRsa_public(pSession, pKey, pSignature, pPaddedMessage)); + + if(MCUXCLRSA_STATUS_INVALID_INPUT == retVal_RsaPublic) + { + /* De-initialize PKC */ + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_verify, MCUXCLRSA_STATUS_INVALID_INPUT, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_public), + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } + else if(MCUXCLRSA_STATUS_INTERNAL_KEYOP_OK != retVal_RsaPublic) + { + + /* De-initialize PKC */ + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_verify, MCUXCLRSA_STATUS_ERROR); + } + else + { + + /*****************************************************/ + /* Perform padding operation */ + /*****************************************************/ + + const uint32_t keyBitLength = 8u * modulusByteLength; + + + MCUX_CSSL_FP_FUNCTION_CALL(retVal_PaddingOperation, pVerifyMode->pPaddingFunction(pSession, + pMessageOrDigest, + messageLength, + pPaddedMessage, + pVerifyMode->pHashAlgo1, + NULL, + saltLength, + keyBitLength, + options, + pOutput, + NULL)); + + /*****************************************************/ + /* Exit */ + /*****************************************************/ + + /* De-initialize PKC */ + mcuxClSession_freeWords_pkcWa(pSession, pkcWaSizeWord); + MCUXCLPKC_FP_DEINITIALIZE_RELEASE(pSession, pkcStateBackup, mcuxClRsa_verify, MCUXCLRSA_STATUS_FAULT_ATTACK); + + mcuxClSession_freeWords_cpuWa(pSession, cpuWaSizeWord); + + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(mcuxClRsa_verify, retVal_PaddingOperation, + MCUXCLRSA_STATUS_FAULT_ATTACK, + MCUXCLPKC_FP_CALLED_REQUEST_INITIALIZE, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClRsa_public), + pVerifyMode->EncodeVerify_FunId, + MCUXCLPKC_FP_CALLED_DEINITIALIZE_RELEASE); + } +} diff --git a/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_VerifyE.c b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_VerifyE.c new file mode 100644 index 000000000..251f42a0b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClRsa/src/mcuxClRsa_VerifyE.c @@ -0,0 +1,57 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClRsa_VerifyE.c + * @brief mcuxClRsa: function, which is called to check if E is FIPS compliant + * (i.e., is odd values in the range 2^16 < e < 2^256) and determines its + * length without leading zeros.. + */ + + +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClRsa_VerifyE) +mcuxClRsa_Status_Protected_t mcuxClRsa_VerifyE(mcuxClRsa_KeyEntry_t *pE, uint32_t *exactLength) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClRsa_VerifyE); + + mcuxClRsa_Status_t status = MCUXCLRSA_STATUS_INVALID_INPUT; + + /* Determine the exact length of e */ + uint32_t eLength = pE->keyEntryLength; + while(eLength > 0u) + { + if(0u != pE->pKeyEntryData[pE->keyEntryLength - eLength]) + { + break; + } + --eLength; + } + + /* Check if it is the range 2^16 < e < 2^256 */ + if((eLength > 2u) && (eLength < 33u)) + { + /* Check if E is odd */ + if(0x1u == (pE->pKeyEntryData[pE->keyEntryLength - 1u] % 2u)) + { + /* Set exact length of E */ + *exactLength = eLength; + status = MCUXCLRSA_STATUS_KEYGENERATION_OK; + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClRsa_VerifyE, status); +} diff --git a/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal.h b/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal.h new file mode 100644 index 000000000..9804c3230 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal.h @@ -0,0 +1,326 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClSession_Internal.h + * @brief Internal definitions of the mcuxClSession component + */ + +#ifndef MCUXCLSESSION_INERNAL_H_ +#define MCUXCLSESSION_INERNAL_H_ + +#include +#include +#include // Exported features flags header +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** + * @brief Allocate a CPU buffer in the CPU workarea of a session. + * + * This function allocates a new CPU buffer in the given \p session, + * and sets the given \p buffer accordingly. + * + * @param pSession Session handle. + * @param buffer A pointer to the buffer that we want to allocate. + * @param bufferLength The size of the buffer. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_allocateCpuBuffer) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_allocateCpuBuffer( + mcuxClSession_Handle_t pSession, + uint32_t **buffer, + uint32_t bufferLength +); + +/** + * @brief Free all CPU buffers of a session. + * + * This function will free all allocated CPU buffers of the given \p session. + * + * @param pSession Session handle. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_freeAllCpuBuffers) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_freeAllCpuBuffers( + mcuxClSession_Handle_t pSession +); + + +/** + * @brief (inline) function to allocate CPU buffer. + * + * This function allocates a buffer in CPU workarea specified in @p pSession. + * + * @param[in] pSession Session handle. + * @param[in] wordsToAllocate The size of buffer to be allocated, in number of CPU words (uint32_t). + * + * @return pointer to the buffer if it is allocated successfully; + * NULL if the buffer cannot be allocated. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_allocateWords_cpuWa) +static inline uint32_t* mcuxClSession_allocateWords_cpuWa( + mcuxClSession_Handle_t pSession, + uint32_t wordsToAllocate) +{ + uint32_t * pCpuBuffer = NULL; + const uint32_t usedWords = pSession->cpuWa.used; + const uint32_t expectedUsed = usedWords + wordsToAllocate; + /* TODO: CLNS-5886 [DEV][Session] enable size checking when allocating buffers */ +#if 0 /* checking disabled before all components/tests allocate workarea properly */ + if (expectedUsed <= pSession->cpuWa.size) + { +#endif + pCpuBuffer = & (pSession->cpuWa.buffer[usedWords]); + pSession->cpuWa.used = expectedUsed; + + if (expectedUsed > pSession->cpuWa.dirty) + { + pSession->cpuWa.dirty = expectedUsed; + } +#if 0 + } +#endif + + return pCpuBuffer; +} + +/** + * @brief (inline) function to allocate PKC buffer. + * + * This function allocates a buffer in PKC workarea specified in @p pSession. + * + * The PKC workarea is assumed to be initialized to be PKC-word aligned. + * However, size of each buffer (allocated from PKC workarea) is in number of CPU words, + * and address of each buffer is CPU-word aligned, but might be not PKC-word aligned. + * Callers need to take care if a buffer is PKC-word aligned, if it is used as a PKC operand. + * For example, the total size of buffer(s) allocated before a PKC operand buffer shall + * be a multiple of PKC wordsize. + * + * @param[in] pSession Session handle. + * @param[in] wordsToAllocate The size of buffer to be allocated, in number of CPU words (uint32_t). + * + * @return pointer to the buffer if it is allocated successfully; + * NULL if the buffer cannot be allocated. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_allocateWords_pkcWa) +static inline uint32_t* mcuxClSession_allocateWords_pkcWa( + mcuxClSession_Handle_t pSession, + uint32_t wordsToAllocate) +{ + uint32_t * pPkcBuffer = NULL; + const uint32_t usedWords = pSession->pkcWa.used; + const uint32_t expectedUsed = usedWords + wordsToAllocate; + /* TODO: CLNS-5886 [DEV][Session] enable size checking when allocating buffers */ +#if 0 /* checking disabled before all components/tests allocate workarea properly */ + if (expectedUsed <= pSession->pkcWa.size) + { +#endif + pPkcBuffer = & (pSession->pkcWa.buffer[usedWords]); + pSession->pkcWa.used = expectedUsed; + + if (expectedUsed > pSession->pkcWa.dirty) + { + pSession->pkcWa.dirty = expectedUsed; + } +#if 0 + } +#endif + + return pPkcBuffer; +} + +/** + * @brief (inline) function to free CPU workarea. + * + * This function frees specified words from the tail of used CPU workarea. + * The space is freed but **not** erased (zeroed). + * + * @param[in] pSession Session handle. + * @param[in] wordsToFree The size of CPU workarea to be freed, in number of CPU words (uint32_t) + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_freeWords_cpuWa) +static inline void mcuxClSession_freeWords_cpuWa( + mcuxClSession_Handle_t pSession, + uint32_t wordsToFree) +{ + if(wordsToFree > pSession->cpuWa.used) + { + pSession->cpuWa.used = 0u; + } + else + { + pSession->cpuWa.used -= wordsToFree; + } +} + +/** + * @brief (inline) function to free PKC workarea. + * + * This function frees specified words from the tail of used PKC workarea. + * The space is freed but **not** erased (zeroed). + * + * @param[in] pSession Session handle. + * @param[in] wordsToFree The size of PKC workarea to be freed, in number of CPU words (uint32_t) + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_freeWords_pkcWa) +static inline void mcuxClSession_freeWords_pkcWa( + mcuxClSession_Handle_t pSession, + uint32_t wordsToFree) +{ + if(wordsToFree > pSession->pkcWa.used) + { + pSession->pkcWa.used = 0u; + } + else + { + pSession->pkcWa.used -= wordsToFree; + } +} + +/** + * @brief (inline) function to get number of used words in CPU workarea + * + * This function returns the number of used words in CPU workarea. + * + * @param[in] pSession Session handle. + * + * @return The number of CPU words (uint32_t) of used part of CPU workarea. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_getUsage_cpuWa) +static inline uint32_t mcuxClSession_getUsage_cpuWa( + mcuxClSession_Handle_t pSession) +{ + return pSession->cpuWa.used; +} + +/** + * @brief (inline) function to get number of used words in PKC workarea + * + * This function returns the number of used words in PKC workarea. + * + * @param[in] pSession Session handle. + * + * @return The number of CPU words (uint32_t) of used part of PKC workarea. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_getUsage_pkcWa) +static inline uint32_t mcuxClSession_getUsage_pkcWa( + mcuxClSession_Handle_t pSession) +{ + return pSession->pkcWa.used; +} + +/** + * @brief (inline) function to set number of used words in CPU workarea + * + * This function sets (restores) the number of used word(s) in CPU workarea. + * It frees all space allocated after the corresponding call to #mcuxClSession_getUsage_cpuWa. + * The space is freed but **not** erased (zeroed). + * + * @param[in] pSession Session handle. + * @param[in] backupUsedCpuWa backup of the number of used word(s). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_setUsage_cpuWa) +static inline void mcuxClSession_setUsage_cpuWa( + mcuxClSession_Handle_t pSession, + uint32_t backupUsedCpuWa) +{ + if(backupUsedCpuWa > pSession->cpuWa.size) + { + pSession->cpuWa.used = pSession->cpuWa.size; + } + else + { + pSession->cpuWa.used = backupUsedCpuWa; + } +} + +/** + * @brief (inline) function to set number of used words in PKC workarea + * + * This function sets (restores) the number of used word(s) in PKC workarea. + * It frees all space allocated after the corresponding call to #mcuxClSession_getUsage_pkcWa. + * The space is freed but **not** erased (zeroed). + * + * @param[in] pSession Session handle. + * @param[in] backupUsedPkcWa backup of the number of used word(s). + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_setUsage_pkcWa) +static inline void mcuxClSession_setUsage_pkcWa( + mcuxClSession_Handle_t pSession, + uint32_t backupUsedPkcWa) +{ + if(backupUsedPkcWa > pSession->pkcWa.size) + { + pSession->pkcWa.used = pSession->pkcWa.size; + } + else + { + pSession->pkcWa.used = backupUsedPkcWa; + } +} + + +/** + * @brief Set the Security options in a Crypto Library session. + * + * @param session Handle for the current CL session. + * @param securityOptions Security options that will be set + * + * @return void + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_setSecurityOptions_Internal) +static inline void mcuxClSession_setSecurityOptions_Internal( + mcuxClSession_Handle_t session, + mcuxClSession_SecurityOptions_t securityOptions +) +{ +/* Unused params*/ + (void) session; + (void) securityOptions; +} + +/** + * @brief Get the Security options from a Crypto Library session. + * + * @param session Handle for the current CL session. + * + * @return securityOptions Security options that will be returned + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_getSecurityOptions_Internal) +static inline mcuxClSession_SecurityOptions_t mcuxClSession_getSecurityOptions_Internal( + mcuxClSession_Handle_t session +) +{ +/* Unused param*/ + (void) session; + return 0u; +} + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLSESSION_INERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal_Functions.h new file mode 100644 index 000000000..d80d0bdc6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/inc/internal/mcuxClSession_Internal_Functions.h @@ -0,0 +1,27 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClSession_Internal_Functions.h + * @brief Internal functions of the mcuxClSession component + */ + +#ifndef MCUXCLSESSION_INTERNAL_FUNCTIONS_H_ +#define MCUXCLSESSION_INTERNAL_FUNCTIONS_H_ + +#include +#include +#include + + +#endif /* MCUXCLSESSION_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession.h b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession.h new file mode 100644 index 000000000..92ec616c1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession.h @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClSession.h + * @brief Top-level include file for the mcuxClSession component + * + * @defgroup mcuxClSession mcuxClSession + * + * This component provides functions for managing a session. A session groups references to all + * the resources that a function to perform its operation needs into one structure. It contains + * references to buffers for working memory, random number generation, configuration data (e.g. + * for security features), etc... + * + * The library exposes the following functionality: + *
    + *
  1. Initialization, cleanup and destruction + *
    • #mcuxClSession_init
    + *
    • #mcuxClSession_cleanup
    + *
    • #mcuxClSession_destroy
    + *
  2. Configuration + *
    • #mcuxClSession_setRtf
    + *
+ */ + +#ifndef MCUXCLSESSION_H_ +#define MCUXCLSESSION_H_ + +#include // Exported features flags header +#include +#include + +#endif /* MCUXCLSESSION_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Functions.h b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Functions.h new file mode 100644 index 000000000..c03e928d6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Functions.h @@ -0,0 +1,149 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClSession_Functions.h + * @brief Top-level API of the mcuxClSession component + */ + +#ifndef MCUXCLSESSION_FUNCTIONS_H_ +#define MCUXCLSESSION_FUNCTIONS_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************** + * FUNCTIONS + **********************************************/ +/** + * @defgroup mcuxClSession_Functions mcuxClSession_Functions + * @brief Defines all functions of @ref mcuxClSession + * @ingroup mcuxClSession + * @{ + */ + +/** + * @brief Initialize a Crypto Library session. + * + * @param pSession Session to be initialized. + * @param pCpuWaBuffer Pointer to buffer to be used as workarea for CPU operations. + * This pointer shall be CPU-word aligned. + * @param cpuWaLength Size (in bytes) of the workarea for CPU operations. + * The size shall be a multiple of CPU wordsize. + * @param pPkcWaBuffer Pointer to buffer to be used as workarea for PKC operations. + * This pointer shall be PKC-word aligned. + * @param pkcWaLength Size (in bytes) of the workarea for PKC operations. + * The size shall be a multiple of **CPU** wordsize. + * + * @return status + * @retval #MCUXCLSESSION_STATUS_OK Session has been initialized successfully + * @retval #MCUXCLSESSION_STATUS_ERROR Error occurred during session initializing. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_init( + mcuxClSession_Handle_t pSession, + uint32_t * const pCpuWaBuffer, + uint32_t cpuWaLength, + uint32_t * const pPkcWaBuffer, + uint32_t pkcWaLength + /* TBD: sclRandom_Context_t * const rngCtx */ +); + +/** + * @brief Set the RTF option in a Crypto Library session. + * + * @param pSession Session to be initialized. + * @param pRtf buffer to store the rtf result. + * @param RtfOptions Options to define RTF processing. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_setRtf) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRtf( + mcuxClSession_Handle_t pSession, + uint8_t * const pRtf, + mcuxClSession_Rtf_t RtfOptions +); + + + + + + + +/** + * @brief Clean up a Crypto Library session. + * + * This function will (securely) cleanup the session, which will still be usable afterwards. + * + * @param pSession Session to be cleaned. + * + * @return status + * @retval #MCUXCLSESSION_STATUS_OK Session operation successful + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_cleanup) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_cleanup( + mcuxClSession_Handle_t pSession +); + +/** + * @brief Destroy a Crypto Library session. + * + * This function will (securely) cleanup the session, including uninitialization etc. + * The session will no longer be usable afterwards. + * + * @param pSession Session to be destroyed. + * + * @return status + * @retval #MCUXCLSESSION_STATUS_OK Session operation successful + * @retval #MCUXCLSESSION_STATUS_ERROR Error occurred during Session operation + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_destroy) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_destroy( + mcuxClSession_Handle_t pSession +); + +#ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM +/** + * @brief Function to switch to another random configuration. + * + * @param session Session to set the new random configuration. + * @param randomMode Random data generation mode/algorithm. It should be the same mode used to initialize randomCtx. + * @param randomCtx Random context. + * + * @return status + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClSession_setRandom) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRandom( + mcuxClSession_Handle_t session, + mcuxClRandom_Mode_t randomMode, + mcuxClRandom_Context_t randomCtx +); +#endif // MCUXCL_FEATURE_SESSION_HAS_RANDOM + +/** + * @} + */ /* mcuxClSession_Functions */ + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLSESSION_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Types.h b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Types.h new file mode 100644 index 000000000..1f2d54742 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/inc/mcuxClSession_Types.h @@ -0,0 +1,140 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClSession_Types.h + * @brief Type definitions for the mcuxClSession component + */ + +#ifndef MCUXCLSESSION_TYPES_H_ +#define MCUXCLSESSION_TYPES_H_ + +#include +#include +#include + +#ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM +#include +#endif /* MCUXCL_FEATURE_SESSION_HAS_RANDOM */ + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxClSession_Constants mcuxClSession_Constants + * @brief Defines all constants of @ref mcuxClSession + * @ingroup mcuxClSession + * @{ + */ + +/** + * @defgroup mcuxClSessionStatusValues Session Status values + * @{ + */ +#define MCUXCLSESSION_STATUS_OK ((mcuxClSession_Status_t) 0x0EEE2E03u) ///< Session operation successful +#define MCUXCLSESSION_STATUS_ERROR ((mcuxClSession_Status_t) 0x0EEE5330u) ///< Error occurred during Session operation +#define MCUXCLSESSION_STATUS_HW_UNAVAILABLE ((mcuxClSession_Status_t) 0x0EEE5334u) ///< Required HW is unavailable +/**@}*/ + +/** + * @defgroup mcuxClSessionRtfValues Session RTF configuration values + * @{ + */ +#define MCUXCLSESSION_RTF_UPDATE_TRUE ((mcuxClSession_Rtf_t) 0xF0F00F0Fu ) ///< RTF will be updated +#define MCUXCLSESSION_RTF_UPDATE_FALSE ((mcuxClSession_Rtf_t) 0x0F0F0F0Fu ) ///< RTF will not be updated +/**@}*/ + + + + +/** + * @} + */ +/* mcuxClSession_Constants */ + +/********************************************** + * TYPEDEFS + **********************************************/ +/** + * @defgroup mcuxClSession_Types mcuxClSession_Types + * @brief Defines all types of @ref mcuxClSession + * @ingroup mcuxClSession + * @{ + */ + +/** + * @brief Type for mcuxClSession status codes + */ +typedef uint32_t mcuxClSession_Status_t; + +/** + * @brief Deprecated type for mcuxClSession protected status codes + */ +typedef MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_Status_Protected_t; + +/** + * @brief Type for mcuxClSession RTF configuration flags + */ +typedef uint32_t mcuxClSession_Rtf_t; + +/** + * @brief Type for mcuxClSession workareas flags + */ +typedef struct mcuxClSession_WorkArea +{ + uint32_t * buffer; ///< Pointer to the starting address of the workarea buffer + uint32_t size; ///< Size of the workarea buffer in words (uint32_t) + uint32_t used; ///< Used portion of the workarea buffer in words (uint32_t) + uint32_t dirty; ///< Maximum used portion of the workarea buffer in words (uint32_t) +} mcuxClSession_WorkArea_t; + +/** + * @brief Type for mcuxClSession security context + */ +typedef struct mcuxClSession_SecurityContext +{ + uint32_t securityCounter; ///< Security counter +} mcuxClSession_SecurityContext_t; + +/** + * @brief Type for Session security options + */ +typedef uint32_t mcuxClSession_SecurityOptions_t; + + + +/** + * @brief Type for mcuxClSession Descriptor + */ +typedef struct mcuxClSession_Descriptor +{ + mcuxClSession_WorkArea_t cpuWa; ///< Workarea for the CPU + mcuxClSession_WorkArea_t pkcWa; ///< Workarea for the PKC +#ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM + mcuxClRandom_Config_t randomCfg; ///< Configuration of the Rng (contexts and mode) +#endif /* MCUXCL_FEATURE_SESSION_HAS_RANDOM */ + mcuxClSession_Rtf_t rtf; ///< Configuration of the RTF + uint8_t *pRtf; +} mcuxClSession_Descriptor_t; + +/** + * @brief Type for mcuxClSession Handle + */ +typedef mcuxClSession_Descriptor_t * const mcuxClSession_Handle_t; + + +/** + * @} + */ /* mcuxClSession_Types */ + +#endif /* MCUXCLSESSION_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClSession/src/mcuxClSession.c b/components/els_pkc/src/comps/mcuxClSession/src/mcuxClSession.c new file mode 100644 index 000000000..838f87ec7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClSession/src/mcuxClSession.c @@ -0,0 +1,161 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClSession.c + * @brief Implementation of the Session component to deal with session-based + * configurations. This file implements the functions declared in + * mcuxClSession.h and mcuxClSession_Internal.h */ + +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_init( + mcuxClSession_Handle_t pSession, + uint32_t * const pCpuWaBuffer, + uint32_t cpuWaLength, + uint32_t * const pPkcWaBuffer, + uint32_t pkcWaLength + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_init); + + + /* Set CPU Wa in session handle */ + pSession->cpuWa.buffer = pCpuWaBuffer; + pSession->cpuWa.size = cpuWaLength / (sizeof(uint32_t)); + pSession->cpuWa.used = 0u; + pSession->cpuWa.dirty = 0u; + + /* Set PKC Wa in session handle */ + pSession->pkcWa.buffer = pPkcWaBuffer; + pSession->pkcWa.size = pkcWaLength / (sizeof(uint32_t)); + pSession->pkcWa.used = 0u; + pSession->pkcWa.dirty = 0u; + + /* Set default RTF handling */ + pSession->rtf = MCUXCLSESSION_RTF_UPDATE_FALSE; + pSession->pRtf = NULL; + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_init, MCUXCLSESSION_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_setRtf) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRtf( + mcuxClSession_Handle_t pSession, + uint8_t *const pRtf, + mcuxClSession_Rtf_t RtfOptions + ) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_setRtf); + + pSession->rtf = RtfOptions; + pSession->pRtf = pRtf; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_setRtf, MCUXCLSESSION_STATUS_OK); +} + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_cleanup) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_cleanup( + mcuxClSession_Handle_t pSession +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_cleanup, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + + //TODO: Replace the functional memory clear function with a secure one + MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *) pSession->cpuWa.buffer,(sizeof(uint32_t)) * pSession->cpuWa.dirty); + + /* Reset dirty to used, in case not all memory has been freed (and gets used again). */ + pSession->cpuWa.dirty = pSession->cpuWa.used; + + MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *) pSession->pkcWa.buffer,(sizeof(uint32_t)) * pSession->pkcWa.dirty); + + /* Reset dirty to used, in case not all memory has been freed (and gets used again). */ + pSession->pkcWa.dirty = pSession->pkcWa.used; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_cleanup, MCUXCLSESSION_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_destroy) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_destroy( + mcuxClSession_Handle_t pSession UNUSED_PARAM +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_destroy, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClSession_cleanup), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClMemory_clear)); + + MCUX_CSSL_FP_FUNCTION_CALL(cleanupStatus, mcuxClSession_cleanup(pSession) ); + if (MCUXCLSESSION_STATUS_OK != cleanupStatus) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_destroy, MCUXCLSESSION_STATUS_ERROR); + } + + MCUXCLMEMORY_FP_MEMORY_CLEAR((uint8_t *) pSession,sizeof(mcuxClSession_Descriptor_t)); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_destroy, MCUXCLSESSION_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_allocateCpuBuffer) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_allocateCpuBuffer( + mcuxClSession_Handle_t pSession, + uint32_t **buffer, + uint32_t bufferLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_allocateCpuBuffer); + + uint32_t * pBuffer = mcuxClSession_allocateWords_cpuWa(pSession, bufferLength); + mcuxClSession_Status_t retCode = ((NULL == pBuffer) ? MCUXCLSESSION_STATUS_ERROR : MCUXCLSESSION_STATUS_OK); + *buffer = pBuffer; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_allocateCpuBuffer, retCode); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_freeAllCpuBuffers) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_freeAllCpuBuffers( + mcuxClSession_Handle_t pSession +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_freeAllCpuBuffers); + + pSession->cpuWa.used = 0u; + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_freeAllCpuBuffers, MCUXCLSESSION_STATUS_OK); +} + + + + +#ifdef MCUXCL_FEATURE_SESSION_HAS_RANDOM +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClSession_setRandom) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClSession_Status_t) mcuxClSession_setRandom( + mcuxClSession_Handle_t session, + mcuxClRandom_Mode_t randomMode, + mcuxClRandom_Context_t randomCtx +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClSession_setRandom); + session->randomCfg.ctx = randomCtx; + session->randomCfg.mode = randomMode; + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClSession_setRandom, MCUXCLSESSION_STATUS_OK); +} + +#endif /* MCUXCL_FEATURE_SESSION_HAS_RANDOM */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal.h new file mode 100644 index 000000000..9ac8fccdf --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal.h @@ -0,0 +1,30 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClTrng_Internal.h + * @brief Top level header of mcuxClTrng component + * + * @defgroup mcuxClTrng mcuxClTrng + * @brief component of trng generation + */ + +#ifndef MCUXCLTRNG_INTERNAL_H_ +#define MCUXCLTRNG_INTERNAL_H_ + +#include // Exported features flags header +#include +#include +#include + +#endif /* MCUXCLTRNG_INTERNAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Constants.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Constants.h new file mode 100644 index 000000000..3c487e119 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Constants.h @@ -0,0 +1,66 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClTrng_Internal_Constants.h + * @brief Constant definitions of mcuxClTrng component + */ + + +#ifndef MCUXCLTRNG_INTERNAL_CONSTANTS_H_ +#define MCUXCLTRNG_INTERNAL_CONSTANTS_H_ + +#include // Exported features flags header +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Constants of mcuxClTrng */ +/**********************************************************/ +/** + * @defgroup mcuxClTrng_Internal_Constants mcuxClTrng_Internal_Constants + * @brief Defines all contstants of @ref mcuxClTrng + * @ingroup mcuxClTrng + * @{ + */ + +/** @addtogroup MCUXCLTRNG_STATUS_ + * mcuxClTrng return code definitions + * @{ */ +#define MCUXCLTRNG_STATUS_ERROR ((mcuxClTrng_Status_t) 0x0FF15330u) ///< An error occurred during the TRNG operation +#define MCUXCLTRNG_STATUS_OK ((mcuxClTrng_Status_t) 0x0FF12E03u) ///< TRNG operation returned successfully +#define MCUXCLTRNG_STATUS_FAULT_ATTACK ((mcuxClTrng_Status_t) 0x0FF1F0F0u) ///< A fault attack is detected +/** @} */ + +#ifdef MCUXCL_FEATURE_TRNG_ELS +/** + * @brief Defines all macros of @ref mcuxClTrng_ELS + * @ingroup mcuxClTrng_ELS + * @{ + */ +#define MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE (32u) ///< output byte size of #mcuxClEls_Rng_DrbgRequestRaw_Async +#endif + +/** + * @} + */ /* mcuxClTrng_Constants */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLTRNG_INTERNAL_CONSTANTS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Functions.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Functions.h new file mode 100644 index 000000000..d23589a36 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Functions.h @@ -0,0 +1,94 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClTrng_Internal_Functions.h + * @brief Top level APIs of mcuxClTrng component + */ + +#ifndef MCUXCLTRNG_INTERNAL_FUNCTIONS_H_ +#define MCUXCLTRNG_INTERNAL_FUNCTIONS_H_ + +#include // Exported features flags header +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* APIs of mcuxClTrng */ +/**********************************************************/ +/** + * @defgroup mcuxClTrng_Internal_Functions mcuxClTrng_Internal_Functions + * @brief Defines all internal functions of @ref mcuxClTrng + * @ingroup mcuxClTrng + * @{ + */ + +/** + * @brief Function to draw an entropy input string from the TRNG + * + * @param[in] pSession Handle for the current CL session. + * @param[out] pEntropyInput Pointer to where entropy input string shall be written. Must be word-aligned. + * @param[in] entropyInputLength Number of entropy input bytes to be drawn. Must be a multiple of word size. + * + * @return Status of the operation: + * @retval #MCUXCLTRNG_STATUS_OK The operation was successful + * @retval #MCUXCLTRNG_STATUS_ERROR The operation failed + * @retval #MCUXCLTRNG_STATUS_FAULT_ATTACK A fault attack is detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClTrng_getEntropyInput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_getEntropyInput( + mcuxClSession_Handle_t pSession, + uint32_t *pEntropyInput, + uint32_t entropyInputLength + ); + +/** + * @brief Function to init TRNG before use + * + * @return Status of the operation: + * @retval #MCUXCLTRNG_STATUS_OK The init operation was successful + * @retval #MCUXCLTRNG_STATUS_FAULT_ATTACK A fault attack is detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClTrng_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_Init(void); + +#ifdef MCUXCL_FEATURE_TRNG_SA_TRNG +/** + * @brief Function to check that TRNG is properly configured + * + * @return Status of the operation: + * @retval #MCUXCLTRNG_STATUS_OK The check operation was successful + * @retval #MCUXCLTRNG_STATUS_ERROR TRNG is not properly configured + * @retval #MCUXCLTRNG_STATUS_FAULT_ATTACK A fault attack is detected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxClTrng_checkConfig) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_checkConfig(void); +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/** + * @} + */ /* mcuxClTrng_Internal_Functions */ + +#endif /* MCUXCLTRNG_INTERNAL_FUNCTIONS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_SA_TRNG.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_SA_TRNG.h new file mode 100644 index 000000000..b602226dd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_SA_TRNG.h @@ -0,0 +1,60 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClTrng_Internal_SA_TRNG.h + * @brief Provide macros for mcuxClTrng internal use. + * This header declares internal macros to deduplicate code and support for internal use only. */ + +#ifndef MCUXCLTRNG_INTERNAL_SA_TRNG_H_ +#define MCUXCLTRNG_INTERNAL_SA_TRNG_H_ + +#include // Exported features flags header +#include +#include +#include + +#define MCUXCLTRNG_ERROR_LIMIT (4u) +#define MCUXCLTRNG_SA_TRNG_HW_DUAL_OSCILLATOR_MODE (1u) + +#ifdef MCUXCL_FEATURE_TRNG_SA_TRNG_256 +#define MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS (8u) +#else +#error "Build configuration issue: SA_TRNG component included but neither DTRNG_256 nor DTRNG_512 are defined" +#endif + +#define MCUXCLTRNG_SA_TRNG_WAITFORREADY(noOfTrngErrors) \ + do \ + { \ + /* Check whether a TRNG error occurred */ \ + if (0u != (MCUXCLTRNG_SFR_BITREAD(MCTL, ERR))) \ + { \ + /* TRNG hardware error detected (ERR bit == 1): */ \ + /* Check how many errors occurred so far */ \ + if (MCUXCLTRNG_ERROR_LIMIT >= (noOfTrngErrors)) \ + { \ + /* Increase TRNG error counter */ \ + (noOfTrngErrors) += 1u; \ + /* Write 1 to clear ERR flag. */ \ + /* TODO: check behavior is correct */ \ + MCUXCLTRNG_SFR_BITSET(MCTL, ERR); \ + } \ + else \ + { \ + /* Number of TRNG errors exceeded the limit, */ \ + /* trigger Fault Attack. */ \ + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); \ + } \ + } \ + } while(0u == (MCUXCLTRNG_SFR_BITREAD(MCTL, ENT_VAL))) \ + +#endif /* MCUXCLTRNG_INTERNAL_SA_TRNG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Types.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Types.h new file mode 100644 index 000000000..b13b015b2 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_Internal_Types.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClTrng_Internal_Types.h + * @brief Type definitions of mcuxClTrng component + */ + + +#ifndef MCUXCLTRNG_INTERNAL_TYPES_H_ +#define MCUXCLTRNG_INTERNAL_TYPES_H_ + +#include // Exported features flags header +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************************************************/ +/* Types of mcuxClTrng */ +/**********************************************************/ +/** + * @defgroup mcuxClTrng_Internal_Types mcuxClTrng_Internal_Types + * @brief Defines all types of @ref mcuxClTrng + * @ingroup mcuxClTrng + * @{ + */ + +/** + * @brief Type for status codes of mcuxClTrng component functions. + * + * This type provides information about the status of the Trng operation + * that has been performed. + */ +typedef uint32_t mcuxClTrng_Status_t; + +/** + * @} + */ /* mcuxClTrng_Internal_Types */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* MCUXCLTRNG_INTERNAL_TYPES_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_SfrAccess.h b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_SfrAccess.h new file mode 100644 index 000000000..ffeddb245 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/inc/internal/mcuxClTrng_SfrAccess.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxClTrng_SfrAccess.h + * @brief Macros for abstracting TRNG hardware SFR access + */ + + +#ifndef MCUXCLTRNG_SFRACCESS_H_ +#define MCUXCLTRNG_SFRACCESS_H_ + +#include // Exported features flags header +#include + +/**** ****/ +/**** TRNG Hardware Abstraction Layer ****/ +/**** ****/ + +/** + * 2 different TRNG hardware definition headers are supported. + * Only one of them should be used/included. + */ + + +/** + * Definitions for accessing TRNG SFRs via, e.g., IP_TRNG->STATUS. + */ + +/** Helper macros for constructing SFR field name constants */ +#define MCUXCLTRNG_PASTE(a,b) a ## b +#define MCUXCLTRNG_CONCAT(a,b) MCUXCLTRNG_PASTE(a,b) +#define MCUXCLTRNG_SFR_FIELD(prefix,sfr,field) MCUXCLTRNG_CONCAT(prefix, sfr ## _ ## field) + +/** Helper macros to get the mask and shift values for a specific TRNG SFR field */ +#define MCUXCLTRNG_SFR_BITMSK(sfr, field) MCUXCLTRNG_CONCAT(MCUXCLTRNG_SFR_FIELD(TRNG_SFR_PREFIX,sfr,field), TRNG_SFR_SUFFIX_MSK) +#define MCUXCLTRNG_SFR_BITPOS(sfr, field) MCUXCLTRNG_CONCAT(MCUXCLTRNG_SFR_FIELD(TRNG_SFR_PREFIX,sfr,field), TRNG_SFR_SUFFIX_POS) + + +/**********************************************************/ +/* Helper macros for TRNG SFR access */ +/**********************************************************/ + +/** Read from TRNG SFR */ +#define MCUXCLTRNG_SFR_READ(sfr) (TRNG_SFR_BASE->TRNG_SFR_NAME(sfr)) + +/** Write to TRNG SFR */ +#define MCUXCLTRNG_SFR_WRITE(sfr, value) \ + do{ TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) = (value); } while(false) + +/** Read from TRNG SFR bit field */ +#define MCUXCLTRNG_SFR_BITREAD(sfr, bit) \ + ((TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) & MCUXCLTRNG_SFR_BITMSK(sfr, bit)) >> MCUXCLTRNG_SFR_BITPOS(sfr, bit)) + +/** Set bit field of TRNG SFR (read-modify-write) */ +#define MCUXCLTRNG_SFR_BITSET(sfr, bit) \ + do{ TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) |= MCUXCLTRNG_SFR_BITMSK(sfr, bit); } while(false) + +/** Clear bit field of TRNG SFR (read-modify-write) */ +#define MCUXCLTRNG_SFR_BITCLEAR(sfr, bit) \ + do{ TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) &= (~ (uint32_t) MCUXCLTRNG_SFR_BITMSK(sfr, bit)); } while(false) + +/** Set value of multi-bit field of TRNG SFR (read-modify-write) */ +#define MCUXCLTRNG_SFR_BITVALSET(sfr, bit, val) \ + do{ uint32_t temp = TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) & (~ (uint32_t) MCUXCLTRNG_SFR_BITMSK(sfr, bit)); \ + TRNG_SFR_BASE->TRNG_SFR_NAME(sfr) = ((val) << MCUXCLTRNG_SFR_BITPOS(sfr, bit)) & MCUXCLTRNG_SFR_BITMSK(sfr, bit) | temp; \ + } while(false) + + +/**** ------------------------------ ****/ + +#endif /* MCUXCLTRNG_SFRACCESS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_ELS.c b/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_ELS.c new file mode 100644 index 000000000..d215762c1 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_ELS.c @@ -0,0 +1,167 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClTrng_ELS.c + * @brief Implementation of the Trng component which provides APIs for + * handling of Trng random number. This file implements the functions + * declared in mcuxClTrng_Internal_Functions.h. */ + +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClTrng_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_Init(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClTrng_Init); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_Init, MCUXCLTRNG_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClTrng_getEntropyInput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_getEntropyInput( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint32_t *pEntropyInput, + uint32_t entropyInputLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClTrng_getEntropyInput); + + /** + * ELS DTRNG output size must be 32 bytes. + * We first request as much as possible directly, and then use a small buffer + * to copy up to 32 remaining bytes. + */ + + /** + * Note: writing to pEntropyInput could be unaligned. + * This could be improved by: - requesting a 32 bytes + * - copying as many bytes as needed to achieve alignment + * - requesting the following 32 bytes to aligned addresses + * - possibly requesting another 32 bytes to fill the remaining bytes + */ + + /* Check if entropyInputLength is word aligned and pEntropyInput is not NULL*/ + if((0u != (entropyInputLength % sizeof(uint32_t))) || (NULL == pEntropyInput)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR); + } + + uint32_t requestSizeELSrawRequest = MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE; + uint32_t remainingNonFullELSblockBytes = entropyInputLength % requestSizeELSrawRequest; + uint32_t fullELSblocksBytes = entropyInputLength - remainingNonFullELSblockBytes; + uint32_t fullELSblocks = fullELSblocksBytes/requestSizeELSrawRequest; + + /* Request as many random bytes as possible with full 32 bytes size. */ + if (fullELSblocksBytes > 0u) + { + for(uint32_t i = 0; i < fullELSblocks; i++) + { + MCUX_CSSL_FP_FUNCTION_CALL(ret_DTRNG_GetTrng1, mcuxClEls_Rng_DrbgRequestRaw_Async((uint8_t *)&pEntropyInput[i*MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE/sizeof(uint32_t)])); + if(MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_DTRNG_GetTrng1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR, + (i+1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + i * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK_WAIT != ret_DTRNG_GetTrng1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_Wait1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if((MCUXCLELS_STATUS_HW_OPERATIONAL == ret_DRBG_Wait1) || (MCUXCLELS_STATUS_HW_ALGORITHM == ret_DRBG_Wait1) || (MCUXCLELS_STATUS_HW_BUS == ret_DRBG_Wait1)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR, + (i+1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + (i+1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK != ret_DRBG_Wait1) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + } + } + + /* If requested size is not a multiple of 32, request one (additional) 32 bytes and use it only partially. */ + if (remainingNonFullELSblockBytes > 0u) + { + uint8_t requestRemainingBuffer[MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE] = {0u}; + + MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + MCUX_CSSL_FP_FUNCTION_CALL(ret_DTRNG_GetTrng2, mcuxClEls_Rng_DrbgRequestRaw_Async(requestRemainingBuffer)); + MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() + if(MCUXCLELS_STATUS_SW_CANNOT_INTERRUPT == ret_DTRNG_GetTrng2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR, + (fullELSblocks + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + fullELSblocks * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK_WAIT != ret_DTRNG_GetTrng2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + MCUX_CSSL_FP_FUNCTION_CALL(ret_DRBG_Wait2, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if((MCUXCLELS_STATUS_HW_OPERATIONAL == ret_DRBG_Wait2) || (MCUXCLELS_STATUS_HW_ALGORITHM == ret_DRBG_Wait2) || (MCUXCLELS_STATUS_HW_BUS == ret_DRBG_Wait2)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR, + (fullELSblocks + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + (fullELSblocks + 1u) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)); + } + else if (MCUXCLELS_STATUS_OK != ret_DRBG_Wait2) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); + } + else + { + /* Intentionally left empty */ + } + + /* Copy the remaining bytes from the buffer to output. */ + MCUX_CSSL_FP_FUNCTION_CALL(copy_result, mcuxCsslMemory_Copy( + mcuxCsslParamIntegrity_Protect(4u, requestRemainingBuffer, &pEntropyInput[fullELSblocksBytes/sizeof(uint32_t)], remainingNonFullELSblockBytes, remainingNonFullELSblockBytes), + requestRemainingBuffer, + &pEntropyInput[fullELSblocksBytes/sizeof(uint32_t)], + remainingNonFullELSblockBytes, + remainingNonFullELSblockBytes) + ); + if(MCUXCSSLMEMORY_STATUS_OK != copy_result) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_FAULT_ATTACK); + } + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_OK, + MCUX_CSSL_FP_CONDITIONAL((fullELSblocksBytes > 0u), + (entropyInputLength/MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + (entropyInputLength/MCUXCLTRNG_ELS_TRNG_OUTPUT_SIZE) * MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)), + MCUX_CSSL_FP_CONDITIONAL((remainingNonFullELSblockBytes > 0u), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Rng_DrbgRequestRaw_Async), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation), + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Copy))); +} diff --git a/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_SA_TRNG.c b/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_SA_TRNG.c new file mode 100644 index 000000000..bca0aa24d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxClTrng/src/mcuxClTrng_SA_TRNG.c @@ -0,0 +1,129 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxClTrng_SA_TRNG.c + * @brief Implementation of the Trng component which provides APIs for + * handling of Trng random number. This file implements the functions + * declared in mcuxClTrng_Internal_Functions.h. */ + +#include +#include +#include +#include +#include +#include + +/** + * @brief Initialization function for the SA_TRNG + * + * This function performs all required steps to be done before SA_TRNG data can be requested via the function + * mcuxClTrng_getEntropyInput. + * + * NOTES: + * - Enabling and configuration of the SA_TRNG shall be done before calling the Crypto Library. + * The Crypto Library requires the TRNG to be configured in dual oscillator mode. Therefore, + * this function simply verifies that the TRNG is configured in dual oscillator mode. + * - For performance it is recommended to put the TRNG in running mode immediately after configuration. + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClTrng_Init) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_Init(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClTrng_Init); + + MCUX_CSSL_FP_FUNCTION_CALL(retVal_checkConfig, mcuxClTrng_checkConfig()); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_Init, retVal_checkConfig, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_checkConfig)); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClTrng_checkConfig) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_checkConfig(void) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClTrng_checkConfig); + + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_checkConfig, MCUXCLTRNG_STATUS_OK); +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxClTrng_getEntropyInput) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxClTrng_Status_t) mcuxClTrng_getEntropyInput( + mcuxClSession_Handle_t pSession UNUSED_PARAM, + uint32_t *pEntropyInput, + uint32_t entropyInputLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxClTrng_getEntropyInput); + + /* Call check configuration function to ensure the TRNG is properly configured for upcoming TRNG accesses */ + MCUX_CSSL_FP_FUNCTION_CALL(result_trngCheckConfig, mcuxClTrng_checkConfig()); + if(MCUXCLTRNG_STATUS_OK != result_trngCheckConfig) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, result_trngCheckConfig, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_checkConfig)); + } + + if ((NULL == pEntropyInput) || ((entropyInputLength % sizeof(uint32_t)) != 0u)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_ERROR, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_checkConfig)); + } + + /* Write 1 to clear ERR flag. */ + MCUXCLTRNG_SFR_BITSET(MCTL, ERR); + + /* Put TRNG in running mode (clear PRGM bit) in case it has not been done before. */ + MCUXCLTRNG_SFR_BITCLEAR(MCTL, PRGM); + + /* Count the observed number of TRNG errors */ + uint32_t noOfTrngErrors = 0u; + + /*****************************************************************************/ + /* Entropy generation process has finished successfully (ENT_VAL bit == 1). */ + /* Copy out as much entropy as requested */ + /*****************************************************************************/ + + /* Copy full words of entropy. + * NOTE: Memory_copy is not used since it copies byte-wise from SFR while only word-wise SFR access is allowed. + */ + uint32_t entropyInputWordLength = (entropyInputLength >> 2u); + uint32_t *pDest = pEntropyInput; + + /* The subsequent loop to draw TRNG words is started with an offset to ensure that the last TRNG word drawn within the loop + * is the last word in the TRNG entropy register. This will trigger another TRNG entropy generation and reduces the time to wait + * for the TRNG to be ready when this function is called the next time. + */ + uint32_t offset = MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS - (entropyInputWordLength % MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS); + + /* Wait until TRNG entropy generation is ready. + * If TRNG hardware error detected return with MCUXCLTRNG_STATUS_FAULT_ATTACK. + */ + MCUXCLTRNG_SA_TRNG_WAITFORREADY(noOfTrngErrors); + + for(uint32_t i = offset; i < (entropyInputWordLength + offset); i++) + { + /* When i is a multiple of the TRNG output buffer size (MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS) wait until new entropy words have been generated. */ + if((i % MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS) == 0u) + { + /* Wait until TRNG entropy generation is ready, If TRNG hardware error detected return with MCUXCLTRNG_STATUS_FAULT_ATTACK. */ + MCUXCLTRNG_SA_TRNG_WAITFORREADY(noOfTrngErrors); + } + /* Copy word of entropy into destination buffer. */ + *pDest = MCUXCLTRNG_SFR_READ(ENT)[i % MCUXCLTRNG_SA_TRNG_NUMBEROFENTREGISTERS]; + /* Increment pDest to point to the next word. */ + ++pDest; + } + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxClTrng_getEntropyInput, MCUXCLTRNG_STATUS_OK, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClTrng_checkConfig)); +} + diff --git a/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h b/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h new file mode 100644 index 000000000..b3415e867 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslAnalysis.h @@ -0,0 +1,416 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2022-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUX_CSSL_ANALYSIS_H_ +#define MCUX_CSSL_ANALYSIS_H_ + +#define MCUX_CSSL_ANALYSIS_STR(a) #a +#define MCUX_CSSL_ANALYSIS_EMPTY() +#define MCUX_CSSL_ANALYSIS_DEFER(id) id MCUX_CSSL_ANALYSIS_EMPTY() +#define MCUX_CSSL_ANALYSIS_EXPAND(...) __VA_ARGS__ + +#define MCUX_CSSL_ANALYSIS_PRAGMA(x) _Pragma(#x) + +/* Compiler defines TODO: decide proper placement for those */ +#if defined ( __CC_ARM ) +/* Arm Compiler 4/5 */ +#define MCUX_CSSL_COMPILER_ARMCC +#define MCUX_CSSL_COMPILER_ARM_COMPILER + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +/* Arm Compiler 6.6 LTM (armclang) */ +#define MCUX_CSSL_COMPILER_ARMCLANG_LTM +#define MCUX_CSSL_COMPILER_ARM_COMPILER + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +/* Arm Compiler above 6.10.1 (armclang) */ +#define MCUX_CSSL_COMPILER_ARMCLANG +#define MCUX_CSSL_COMPILER_ARM_COMPILER + +#elif defined (_clang_) +#define MCUX_CSSL_COMPILER_ARM_COMPILER /* i.e. Version 6.01 build 0019 */ +#endif // defined ( __CC_ARM ) + +/* Example of common patterns, with either just predefined rationale, or a combination of discards. */ +#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_READ() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Read from a HW peripheral") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_READ() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_HW_WRITE() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE("Write to a HW peripheral") + /*MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_TO_OBJECT("Write to a HW peripheral")*/ +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_HW_WRITE() \ + /*MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_TO_OBJECT()*/ \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_API_DECLARATIONS() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED("Consumed by user, it is declared but never referenced. ") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_API_DECLARATIONS() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_DESCRIPTIVE_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER("Identifiers longer than 31 characters are allowed for more descriptive naming") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DESCRIPTIVE_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_REINTERPRET_MEMORY_OF_OPAQUE_TYPES() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("explicit pointer casts reinterpreting opaque types of workarea-like buffer objects are allowed.") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_REINTERPRET_MEMORY() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() +/* Rule 11.3: applies to casts between ctx structs +* e.g. cast from Aead_Context_t to more specific type AeadModes_Context_t +*/ +#define MCUX_CSSL_ANALYSIS_START_CAST_TO_MORE_SPECIFIC_TYPE() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY("Cast to a more specific type is allowed") +#define MCUX_CSSL_ANALYSIS_STOP_CAST_TO_MORE_SPECIFIC_TYPE() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_HEADER() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION("External header outside our control") \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE("External header outside our control") \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER("External header outside our control") \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY("External header outside our control") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_HEADER() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_OBJ_SIZES() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE("Variables used to determine object sizes") \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("Variables used to determine object sizes") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_OBJ_SIZES() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_FUP() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION("External declarations are generated by the FUP processing tool") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_FUP() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for security counter variables per design") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED("Return instead of break statement as terminator is allowed") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_SWITCH_STATEMENT_RETURN_TERMINATION() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT("Invariant expression is allowed in workarea calculation macros") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_INVARIANT_EXPRESSION_WORKAREA_CALCULATIONS() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS("Address in SFR is for internal use only and does not escape") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_ADDRESS_IN_SFR_IS_NOT_REUSED_OUTSIDE() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS() + + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_INTEGER_OVERFLOW() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("Integer overflows are allowed/expected for DI variables per design") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_INTEGER_OVERFLOW() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() + +#define MCUX_CSSL_ANALYSIS_START_PATTERN_DI_CAST_POINTERS() \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER("Typecast pointer to integer for DI record/expunge") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_6, "Typecast pointer (void *) to integer for DI record/expunge") +#define MCUX_CSSL_ANALYSIS_STOP_PATTERN_DI_CAST_POINTERS() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_6) \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() + +/* Example of basic violation suppression */ +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DEAD_CODE(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_1, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DEAD_CODE() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_1) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TEXT_IN_COMMENTS(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_3_1, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TEXT_IN_COMMENTS() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_3_1) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_CASTING(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP36_C, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_CASTING() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP36_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_VOLATILE(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \ + MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_VOLATILE() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \ + MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_OUT_OF_BOUNDS_ACCESS(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_1, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_OUT_OF_BOUNDS_ACCESS() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_1) \ + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wcast-qual, rationale) \ + MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(1836, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) \ + MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(1836) \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wcast-qual) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DISCARD_CONST_QUALIFIER(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_8, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DISCARD_CONST_QUALIFIER() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_8) + + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_NULL_POINTER_CONSTANT(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_9, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_NULL_POINTER_CONSTANT() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_9) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY_BETWEEN_INAPT_ESSENTIAL_TYPES() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_MEMORY(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_3, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_MEMORY() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_3) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ARRAY_OUT_OF_BOUNDS(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_ARR30_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ARRAY_OUT_OF_BOUNDS() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_ARR30_C) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_4, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT36_C, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_MSC15_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_MSC15_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT36_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_4) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_INTEGER_TO_POINTER(rationale) \ + MCUX_CSSL_ANALYSIS_START_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER(rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_INTEGER_TO_POINTER() \ + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TYPECAST_BETWEEN_INTEGER_AND_POINTER() + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_AMBIGUOUS_IDENTIFIER(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_1, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_5_4, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_AMBIGUOUS_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_1) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_5_4) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_REINTERPRET_STRUCT(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_11_1, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_REINTERPRET_STRUCT() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_11_1) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_2_2, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_DECLARED_BUT_NEVER_REFERENCED() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_2_2) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(INTEGER_OVERFLOW, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_12_4, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_12_4) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(INTEGER_OVERFLOW) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_WRAP(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT30_C, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_INT08_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_WRAP() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT08_C) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_INT30_C) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_POINTER_INCOMPATIBLE(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(CERT_EXP39_C, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_POINTER_INCOMPATIBLE() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(CERT_EXP39_C) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_1, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_3, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_16_6, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_SWITCH_STATEMENT_NOT_WELL_FORMED() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_1) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_3) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_16_6) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CONTROLLING_EXPRESSION_IS_INVARIANT() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_ESCAPING_LOCAL_ADDRESS(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_18_6, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_ESCAPING_LOCAL_ADDRESS() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_18_6) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4, "Conditional expression does have a boolean type.") +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_BOOLEAN_TYPE_FOR_CONDITIONAL_EXPRESSION() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_14_4) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_C11_EXTENSION(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wc11-extensions, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_C11_EXTENSION() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wc11-extensions) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNDEFINED_VALUE(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wundef, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNDEFINED_VALUE() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wundef) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_IDENTIFIER(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-identifier, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-identifier) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_RESERVED_MACRO_IDENTIFIER(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wreserved-macro-identifier, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_RESERVED_MACRO_IDENTIFIER() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wreserved-macro-identifier) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_MISSING_VARIABLE_DECLARATION(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wmissing-variable-declarations, rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_8_4, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_MISSING_VARIABLE_DECLARATION() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_8_4) \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wmissing-variable-declarations) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_10_8, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_CAST_OF_COMPOSITE_EXPRESSION() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_10_8) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_UNUSED_VARIABLE(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wunused-variable, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_UNUSED_VARIABLE() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wunused-variable) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY(rationale) \ + MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(-Wpadded, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_PADDED_TO_ALIGNMENT_BOUNDARY() \ + MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(-Wpadded) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_HARDWARE_ACCESS(rationale) \ + MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(-Warray-bounds, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_HARDWARE_ACCESS() \ + MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(-Warray-bounds) + +#define MCUX_CSSL_ANALYSIS_START_SUPPRESS_TAINTED_EXPRESSION(rationale) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Directive_4_14, rationale) +#define MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_TAINTED_EXPRESSION() \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Directive_4_14) + +/* Tool specific handling: Coverity checkers */ +#if defined(__COVERITY__) + +#define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block deviate checker_identifier rationale)) +#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier)) + +#define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance block fp checker_identifier rationale)) +#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(coverity compliance end_block checker_identifier)) + +#else +#define MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(checker_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(checker_identifier) + +#define MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(checker_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(checker_identifier) +#endif + +/* Tool specific handling: Clang warnings */ +#if defined(__clang__) +#define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier))) +#define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop)) +#else +#define MCUX_CSSL_ANALYSIS_CLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_CLANG_STOP_SUPPRESS_WARNING(warning_identifier) +#endif + +/* Tool specific handling: GHS warnings */ +#if defined(__ghs__) +#define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale) \ + _Pragma("ghs nowarning " ## warning_identifier) +#define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier) \ + _Pragma("ghs endnowarning") +#else +#define MCUX_CSSL_ANALYSIS_GHS_START_SUPPRESS_WARNING(warning_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_GHS_STOP_SUPPRESS_WARNING(warning_identifier) +#endif + +/* Tool specific handling: GCC warnings */ +#if defined(__GNUC__) +#define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic push)) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier))) +#define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(GCC diagnostic pop)) +#else +#define MCUX_CSSL_ANALYSIS_GCC_START_SUPPRESS_WARNING(warning_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_GCC_STOP_SUPPRESS_WARNING(warning_identifier) +#endif + +/* Arm Compiler 4/5 */ +#if defined(MCUX_CSSL_COMPILER_ARMCC) +#define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(push)) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(diag_suppress MCUX_CSSL_ANALYSIS_STR(warning_identifier))) +#define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(pop)) +#else +#define MCUX_CSSL_ANALYSIS_ARMCC_START_SUPPRESS_WARNING(warning_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_ARMCC_STOP_SUPPRESS_WARNING(warning_identifier) +#endif + +/* Arm Compiler 6 / Arm Compiler for Embedded 6 */ +#if defined(MCUX_CSSL_COMPILER_ARMCLANG) || defined(MCUX_CSSL_COMPILER_ARMCLANG_LTM) +#define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic push)) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic ignored MCUX_CSSL_ANALYSIS_STR(warning_identifier))) +#define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier) \ + MCUX_CSSL_ANALYSIS_EXPAND(MCUX_CSSL_ANALYSIS_DEFER(MCUX_CSSL_ANALYSIS_PRAGMA)(clang diagnostic pop)) +#else +#define MCUX_CSSL_ANALYSIS_ARMCLANG_START_SUPPRESS_WARNING(warning_identifier, rationale) +#define MCUX_CSSL_ANALYSIS_ARMCLANG_STOP_SUPPRESS_WARNING(warning_identifier) +#endif + +#endif /* MCUX_CSSL_ANALYSIS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h b/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h new file mode 100644 index 000000000..cb7253527 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslCPreProcessor/inc/mcuxCsslCPreProcessor.h @@ -0,0 +1,198 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2019-2020 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUX_CSSL_C_PRE_PROCESSOR_H_ +#define MCUX_CSSL_C_PRE_PROCESSOR_H_ + +/** + * @file mcuxCsslCPreProcessor.h + * @brief The default implementation is based on standard C preprocessor + * functionality + */ + +#define MCUX_CSSL_CPP_STR(a) #a + +#define MCUX_CSSL_CPP_ADD(a) + (a) + +#define MCUX_CSSL_CPP_CAT_IMPL(a, b) a##b + +#define MCUX_CSSL_CPP_CAT(a, b) \ + MCUX_CSSL_CPP_CAT_IMPL(a, b) + +#define MCUX_CSSL_CPP_CAT3(a, b, c) \ + MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), c) + +#define MCUX_CSSL_CPP_CAT4(a, b, c, d) \ + MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_CAT(a, b), MCUX_CSSL_CPP_CAT(c, d)) + +#define MCUX_CSSL_CPP_CAT6(a, b, c, d, e, f) \ + MCUX_CSSL_CPP_CAT3( \ + MCUX_CSSL_CPP_CAT(a, b), \ + MCUX_CSSL_CPP_CAT(c, d), \ + MCUX_CSSL_CPP_CAT(e, f)) + +#define MCUX_CSSL_CPP_SEQUENCE_32TO0() \ + 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, \ + 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0() \ + n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \ + n, n, n, n, n, n, n, n, n, n, n, n, n, 3, 2, 1, 0 + +#define MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0() \ + n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, \ + n, n, n, n, n, n, n, n, n, n, n, n, n, n, 2, 1, 0 + +#define MCUX_CSSL_CPP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, \ + _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, \ + N, ...) \ + N + +#define MCUX_CSSL_CPP_ARGCOUNT_IMPL(...) \ + MCUX_CSSL_CPP_ARG_N(__VA_ARGS__) + +#define MCUX_CSSL_CPP_ARGCOUNT(...) \ + MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_32TO0()) + +#define MCUX_CSSL_CPP_ARGCOUNT_2N(...) \ + MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_2TO0()) + +#define MCUX_CSSL_CPP_ARGCOUNT_3N(...) \ + MCUX_CSSL_CPP_ARGCOUNT_IMPL(__VA_ARGS__,MCUX_CSSL_CPP_SEQUENCE_N_UNTIL_3TO0()) + +#define MCUX_CSSL_CPP_OVERLOADED_IMPL(name, n) MCUX_CSSL_CPP_CAT_IMPL(name, n) + +#define MCUX_CSSL_CPP_OVERLOADED(name, ...) \ + MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_OVERLOADED_IMPL)()(name, MCUX_CSSL_CPP_ARGCOUNT(__VA_ARGS__)) + +#define MCUX_CSSL_CPP_OVERLOADED1(name, ...) \ + MCUX_CSSL_CPP_IF_ELSE(MCUX_CSSL_CPP_HAS_ONE_ARG(__VA_ARGS__))( \ + /* If only one arg, use the 1 version */ \ + MCUX_CSSL_CPP_CAT(name,1)(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure extra argument: */ 0)) \ + )( \ + /* Otherwise the n version */ \ + MCUX_CSSL_CPP_CAT(name,n)(__VA_ARGS__) \ + ) + +#define MCUX_CSSL_CPP_OVERLOADED2(name, ...) \ + MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_2N(__VA_ARGS__))(__VA_ARGS__) + +#define MCUX_CSSL_CPP_OVERLOADED3(name, ...) \ + MCUX_CSSL_CPP_OVERLOADED_IMPL(name, MCUX_CSSL_CPP_ARGCOUNT_3N(__VA_ARGS__))(__VA_ARGS__) + + + +/***************************************************************************** + * Helper macros * + *****************************************************************************/ + +/* Apply a macro to all arguments */ +#define MCUX_CSSL_CPP_MAP(__macro, ...) \ + MCUX_CSSL_CPP_EVAL(MCUX_CSSL_CPP_MAP_IMPL(__macro, __VA_ARGS__)) + +/* Evaluate a complex macro (which needs multiple expansions to be processed) */ +#define MCUX_CSSL_CPP_EVAL(...) MCUX_CSSL_CPP_EVAL1024(__VA_ARGS__) +#define MCUX_CSSL_CPP_EVAL1024(...) MCUX_CSSL_CPP_EVAL512(MCUX_CSSL_CPP_EVAL512(__VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL512(...) MCUX_CSSL_CPP_EVAL256(MCUX_CSSL_CPP_EVAL256(__VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL256(...) MCUX_CSSL_CPP_EVAL128(MCUX_CSSL_CPP_EVAL128(__VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL128(...) MCUX_CSSL_CPP_EVAL64( MCUX_CSSL_CPP_EVAL64( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL64(...) MCUX_CSSL_CPP_EVAL32( MCUX_CSSL_CPP_EVAL32( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL32(...) MCUX_CSSL_CPP_EVAL16( MCUX_CSSL_CPP_EVAL16( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL16(...) MCUX_CSSL_CPP_EVAL8( MCUX_CSSL_CPP_EVAL8( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL8(...) MCUX_CSSL_CPP_EVAL4( MCUX_CSSL_CPP_EVAL4( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL4(...) MCUX_CSSL_CPP_EVAL2( MCUX_CSSL_CPP_EVAL2( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL2(...) MCUX_CSSL_CPP_EVAL1( MCUX_CSSL_CPP_EVAL1( __VA_ARGS__)) +#define MCUX_CSSL_CPP_EVAL1(...) __VA_ARGS__ + +/* Recursive definition of map macro, assumes at least one argument */ +#define MCUX_CSSL_CPP_MAP_IMPL(__macro, ...) \ + /* Apply the macro to the first argument from the list */\ + __macro(MCUX_CSSL_CPP_FIRST(__VA_ARGS__, /* ensure second argument: */ 0)) \ + /* Only proceed if there are additional arguments */\ + MCUX_CSSL_CPP_IF(MCUX_CSSL_CPP_HAS_MORE_ARGS(__VA_ARGS__))( \ + /* Recursive call for remaining arguments */\ + MCUX_CSSL_CPP_DEFER2(MCUX_CSSL_CPP_MAP_IMPL_)()(__macro, \ + MCUX_CSSL_CPP_NEXT(__VA_ARGS__)) \ + ) +#define MCUX_CSSL_CPP_MAP_IMPL_() MCUX_CSSL_CPP_MAP_IMPL + +/* Extract first argument (requires at least two arguments to be present) */ +#define MCUX_CSSL_CPP_FIRST(a, ...) a +/* Extract second argument (requires at least three arguments to be present) */ +#define MCUX_CSSL_CPP_SECOND(a, b, ...) b +/* Extract second argument (requires at least four arguments to be present) */ +#define MCUX_CSSL_CPP_THIRD(a, b, c, ...) c +/* Extract second argument (requires at least five arguments to be present) */ +#define MCUX_CSSL_CPP_FOURTH(a, b, c, d, ...) d +/* Remove the first argument from the list (requires at least two arguments to be present) */ +#define MCUX_CSSL_CPP_NEXT(...) MCUX_CSSL_CPP_NEXT_()(__VA_ARGS__) +#define MCUX_CSSL_CPP_NEXT_() MCUX_CSSL_CPP_NEXT__ +#define MCUX_CSSL_CPP_NEXT__(x, ...) __VA_ARGS__ + +/* Check whether there is more then one argument */ +#define MCUX_CSSL_CPP_HAS_MORE_ARGS(...) \ + MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER()))) + +#define MCUX_CSSL_CPP_HAS_ONE_ARG(...) \ + MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_SECOND(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER())) + +#define MCUX_CSSL_CPP_HAS_TWO_ARGS(...) \ + MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_THIRD(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER())) + +#define MCUX_CSSL_CPP_HAS_THREE_ARGS(...) \ + MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_FOURTH(__VA_ARGS__, MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER(), MCUX_CSSL_CPP_MARKER())) + + +/* Check whether the argument is MCUX_CSSL_CPP_MARKER(), return 1 if it is */ +#define MCUX_CSSL_CPP_IS_MARKER(...) \ + MCUX_CSSL_CPP_SECOND(__VA_ARGS__, 0, 0) +#define MCUX_CSSL_CPP_MARKER() \ + ~, 1 + +/* Convert any argument into a bool (either 0 or 1), by double negation */ +#define MCUX_CSSL_CPP_BOOL(x) MCUX_CSSL_CPP_NOT(MCUX_CSSL_CPP_NOT(x)) + +/* Boolean negation (map value 0 to the marker, and check if we have the marker) */ +#define MCUX_CSSL_CPP_NOT(x) MCUX_CSSL_CPP_IS_MARKER(MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_NOT_BOOL_, x)) +#define MCUX_CSSL_CPP_NOT_BOOL_0 MCUX_CSSL_CPP_MARKER() + +/* Convert condition to bool */ +#define MCUX_CSSL_CPP_IF(condition) MCUX_CSSL_CPP_IF_(MCUX_CSSL_CPP_BOOL(condition)) +/* Convert bool to decision defines */ +#define MCUX_CSSL_CPP_IF_(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IF_BOOL_, condition) +/* If 0, do nothing*/ +#define MCUX_CSSL_CPP_IF_BOOL_0(...) +/* If 1, perform action */ +#define MCUX_CSSL_CPP_IF_BOOL_1(...) __VA_ARGS__ + +/* Convert condition to bool */ +#define MCUX_CSSL_CPP_IF_ELSE(condition) MCUX_CSSL_CPP_IF_ELSE_IMPL(MCUX_CSSL_CPP_BOOL(condition)) +/* Convert bool to decision defines */ +#define MCUX_CSSL_CPP_IF_ELSE_IMPL(condition) MCUX_CSSL_CPP_CAT(MCUX_CSSL_CPP_IFE_BOOL_, condition) +/* If 0, ignore action */ +#define MCUX_CSSL_CPP_IFE_BOOL_0(...) MCUX_CSSL_CPP_IFE_BOOL_0_ELSE +/* Else 0, perform action */ +#define MCUX_CSSL_CPP_IFE_BOOL_0_ELSE(...) __VA_ARGS__ +/* If 1, perform action */ +#define MCUX_CSSL_CPP_IFE_BOOL_1(...) __VA_ARGS__ MCUX_CSSL_CPP_IFE_BOOL_1_ELSE +/* Else 1, ignore action */ + +#define MCUX_CSSL_CPP_IFE_BOOL_1_ELSE(...) + +/* Defer macro expansion */ +#define MCUX_CSSL_CPP_EMPTY() +#define MCUX_CSSL_CPP_DEFER1(macro) macro MCUX_CSSL_CPP_EMPTY() +#define MCUX_CSSL_CPP_DEFER2(macro) macro MCUX_CSSL_CPP_EMPTY MCUX_CSSL_CPP_EMPTY()() + +#endif /* MCUX_CSSL_C_PRE_PROCESSOR_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h new file mode 100644 index 000000000..12a823f16 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity.h @@ -0,0 +1,149 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslDataIntegrity.h + * @brief Provides the API for the CSSL data integrity mechanism. + */ + +#ifndef MCUXCSSLDATAINTEGRITY_H_ +#define MCUXCSSLDATAINTEGRITY_H_ + +/* Include the actual implementation of the data integrity mechanism. */ +#include + +/* Include the Secure Counter definitions */ +#include + +/** + * @addtogroup mcuxCsslAPI MCUX CSSL -- API + * + * @defgroup mcuxCsslDataIntegrity Data Integrity API + * @brief Data integrity mechanism. + * @ingroup mcuxCsslAPI + */ + + +/** + * @defgroup diCore Data integrity core functionality + * @brief Data integrity handling core functionality. + * @ingroup mcuxCsslDataIntegrity + */ + +/****************************************************************************/ +/* Constants */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_DI_CHECK_PASSED + * @brief Positive comparison result value. + * @api + * @ingroup diCore + */ +#define MCUX_CSSL_DI_CHECK_PASSED \ + MCUX_CSSL_DI_CHECK_PASSED_IMPL + +/** + * @def MCUX_CSSL_DI_CHECK_FAILED + * @brief Negative comparison result value. + * @api + * @ingroup diCore + */ +#define MCUX_CSSL_DI_CHECK_FAILED \ + MCUX_CSSL_DI_CHECK_FAILED_IMPL + +/** + * @def MCUX_CSSL_DI_INIT_DEFAULT_VALUE + * @brief Default value use for the initialization of the data integrity mechanism. + * @api + * @ingroup diCore + */ +#define MCUX_CSSL_DI_INIT_DEFAULT_VALUE \ + (0x96969696u) + +/****************************************************************************/ +/* Initialization */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_DI_ALLOC + * @brief Allocation operation for the data integrity register. + * @api + * @ingroup diCore + */ +#define MCUX_CSSL_DI_ALLOC() \ + MCUX_CSSL_DI_ALLOC_IMPL() + +/** + * @def MCUX_CSSL_DI_INIT + * @brief Initialization operation for the data integrity mechanism. + * @api + * @ingroup diCore + * + * @param value Value with which the data integrity register must be initialized. + */ +#define MCUX_CSSL_DI_INIT(value) \ + MCUX_CSSL_DI_INIT_IMPL(value) + +/****************************************************************************/ +/* Check */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_DI_CHECK + * @brief Comparison operation for the data integrity. + * @api + * @ingroup diCore + * + * @param reference Reference value to compare the data integrity value against. + * @return Either #MCUX_CSSL_DI_CHECK_PASSED, if the value matches, or + * #MCUX_CSSL_DI_CHECK_FAILED if the value is different. + */ +#define MCUX_CSSL_DI_CHECK(reference) \ + MCUX_CSSL_DI_CHECK_IMPL(reference) + +/****************************************************************************/ +/* Updates */ +/****************************************************************************/ + +/** + * @defgroup diUpdate Data integrity record + * @brief Support for recording a value in the data integrity register + * @ingroup mcuxCsslDataIntegrity + */ + +/** + * @def MCUX_CSSL_DI_RECORD + * @brief Record the @p value for data integrity checking. + * @api + * @ingroup diUpdate + * + * @param identifier Identifier for the @p value that will be recorded. + * @param value Value which needs to be recorded for the given @p identifier. + */ +#define MCUX_CSSL_DI_RECORD(identifier, value) \ + MCUX_CSSL_DI_RECORD_IMPL(identifier, value) + +/** + * @def MCUX_CSSL_DI_EXPUNGE + * @brief Expunge the record for @p value. + * @api + * @ingroup diUpdate + * + * @param identifier Identifier for the @p value that will be expunged. + * @param value Expected value that was recorded for the given @p identifier. + */ +#define MCUX_CSSL_DI_EXPUNGE(identifier, value) \ + MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value) + +#endif /* MCUXCSSLDATAINTEGRITY_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h new file mode 100644 index 000000000..91af47389 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Cfg.h @@ -0,0 +1,47 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslDataIntegrity_Cfg.h + * \brief Configuration of the implementation for the data integrity mechanism. + */ + +#ifndef MCUXCSSLDATAINTEGRITY_CFG_H_ +#define MCUXCSSLDATAINTEGRITY_CFG_H_ + +/** + * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations + * + * \defgroup mcuxCsslDataIntegrity_CFG Data Integrity Configuration + * \brief Configuration options for the data integrity mechanism. + * \ingroup mcuxCsslCFG + */ + +/** + * \def MCUX_CSSL_DI_USE_SECURE_COUNTER + * \brief If set to 1, use the data integrity mechanism implementation based on + * the CSSL secure counter mechanism. + * \ingroup mcuxCsslDataIntegrity_CFG + */ + #define MCUX_CSSL_DI_USE_SECURE_COUNTER 0 + +/** + * \def MCUX_CSSL_DI_USE_NONE + * \brief If set to 1, do not use the data integrity mechanism. + * \ingroup mcuxCsslDataIntegrity_CFG + */ + #define MCUX_CSSL_DI_USE_NONE 1 + +/* Basic configuration sanity check */ + +#endif /* MCUXCSSLDATAINTEGRITY_CFG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h new file mode 100644 index 000000000..ed2e83076 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_Impl.h @@ -0,0 +1,34 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslDataIntegrity_Impl.h + * \brief Selection of the implementation for the data integrity mechanism. + */ + +#ifndef MCUXCSSLDATAINTEGRITY_IMPL_H_ +#define MCUXCSSLDATAINTEGRITY_IMPL_H_ + +/* Include the configuration for the data integrity mechanism. */ +#include + +/* Include the selected implementation of the data integrity mechanism. */ +#if defined(MCUX_CSSL_DI_USE_SECURE_COUNTER) && (1 == MCUX_CSSL_DI_USE_SECURE_COUNTER) +# include +#elif defined(MCUX_CSSL_DI_USE_NONE) && (1 == MCUX_CSSL_DI_USE_NONE) +# include +#else +# error "No data integrity implementation found/configured." +#endif + +#endif /* MCUXCSSLDATAINTEGRITY_IMPL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h new file mode 100644 index 000000000..03cdd74d9 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslDataIntegrity/inc/mcuxCsslDataIntegrity_None.h @@ -0,0 +1,125 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslDataIntegrity_None.h + * \brief Implementation that disables the CSSL data integrity mechanism. + */ + +#ifndef MCUXCSSLDATAINTEGRITY_NONE_H_ +#define MCUXCSSLDATAINTEGRITY_NONE_H_ + +/** + * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations + * + * \defgroup mcuxCsslDataIntegrity_None Data Integrity: Disabled + * \brief Disable the data integrity mechanism. + * \ingroup mcuxCsslIMPL + */ + + +/** + * \defgroup diNoneCore Data integrity core functionality + * \brief Data integrity handling core functionality, when data integrity is disabled. + * \ingroup mcuxCsslDataIntegrity_None + */ + +/****************************************************************************/ +/* Constants */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_DI_CHECK_PASSED_IMPL + * \brief Positive comparison result value. + * \ingroup diNoneCore + */ +#define MCUX_CSSL_DI_CHECK_PASSED_IMPL (MCUX_CSSL_SC_CHECK_PASSED) + +/** + * \def MCUX_CSSL_DI_CHECK_FAILED_IMPL + * \brief Negative comparison result value. + * \ingroup diNoneCore + */ +#define MCUX_CSSL_DI_CHECK_FAILED_IMPL (MCUX_CSSL_SC_CHECK_FAILED) + +/****************************************************************************/ +/* Initialization */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_DI_ALLOC_IMPL + * \brief Allocation operation implementation for the data integrity. + * \ingroup diNoneCore + */ +#define MCUX_CSSL_DI_ALLOC_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_DI_INIT_IMPL + * \brief Initialization operation implementation for the data integrity. + * \ingroup diNoneCore + * + * \param value Value with which the data integrity must be initialized. + */ +#define MCUX_CSSL_DI_INIT_IMPL(value) \ + /* intentionally empty */ + +/****************************************************************************/ +/* Check */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_DI_CHECK_IMPL + * \brief Comparison operation implementation for the data integrity. + * \ingroup diNoneCore + * + * \param reference Reference value to compare the data integrity value against. + * \return Always #MCUX_CSSL_DI_CHECK_PASSED. + */ +#define MCUX_CSSL_DI_CHECK_IMPL(reference) \ + (MCUX_CSSL_DI_CHECK_PASSED_IMPL) + +/****************************************************************************/ +/* Updates */ +/****************************************************************************/ + +/** + * \defgroup diNoneUpdate Data integrity record + * \brief Support for recording a value in the data integrity register, when data integrity is disabled. + * \ingroup mcuxCsslDataIntegrity_None + */ + +/** + * \def MCUX_CSSL_DI_RECORD_IMPL + * \brief Implementation: Record the value for data integrity checking. + * \ingroup diNoneUpdate + * + * \param identifier Identifier for the value that will be recorded. + * \param value Value which needs to be recorded for the given identifier. + */ +#define MCUX_CSSL_DI_RECORD_IMPL(identifier, value) \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_DI_EXPUNGE_IMPL + * \brief Implementation: Expunge the record for value. + * \ingroup diNoneUpdate + * + * \param identifier Identifier for the value that will be expunged. + * \param value Expected value that was recorded for the given identifier. + */ +#define MCUX_CSSL_DI_EXPUNGE_IMPL(identifier, value) \ + /* intentionally empty */ + + +#endif /* MCUXCSSLDATAINTEGRITY_NONE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h new file mode 100644 index 000000000..864ee211f --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection.h @@ -0,0 +1,1436 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslFlowProtection.h + * @brief Provides the API for the CSSL flow protection mechanism. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_H_ +#define MCUX_CSSL_FLOW_PROTECTION_H_ + +/* Include the actual implementation of the flow protection mechanism. */ +#include + +/** + * @addtogroup mcuxCsslAPI MCUX CSSL -- API + * + * @defgroup mcuxCsslFlowProtection Flow Protection API + * @brief Flow protection mechanism. + * @ingroup mcuxCsslAPI + */ + + +/** + * @defgroup csslFpCore Flow protection core functionality + * @brief Flow protection handling core functionality. + * @ingroup mcuxCsslFlowProtection + * + * @todo Extend this description of the core functionality which relies + * basically on the function calling flow protection. + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @event{MCUX_CSSL_FP_FUNCTION_CALL} + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED} + */ + +/** + * @defgroup csslFpFunction Function calling flow protection + * @brief Support for flow protected functions. + * @ingroup mcuxCsslFlowProtection + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @event{MCUX_CSSL_FP_FUNCTION_CALL} + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED} + */ + + +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_3_1 "Comments outline example sequences. For more readability, additional inner comments might be added." +#endif +/** + * @def MCUX_CSSL_FP_PROTECTED_TYPE + * @brief Based on a given base type, builds a return type with flow + * protection. + * @ingroup csslFpFunction + * + * This macro must be used to wrap the function return type. For example: + * @code + * MCUX_CSSL_FP_FUNCTION_DECL(someFunction) + * MCUX_CSSL_FP_PROTECTED_TYPE(uint32_t) someFunction(void); + * @endcode + * + * Note that depending on the selected flow protection mechanism, the width of + * the result type may be limited to 32 bits or less to allow encoding a + * protection token in the other half of a 64-bit return value. + * + * @see MCUX_CSSL_FP_FUNCTION_DEF + * + * @param resultType The type to be converted into a protected type. + */ +#define MCUX_CSSL_FP_PROTECTED_TYPE(resultType) \ + MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType) + +/** + * @def MCUX_CSSL_FP_COUNTER_STMT + * @brief A statement which is only evaluated if a secure counter is used. + * @api + * @ingroup csslFpFunction + * + * This macro can be used to create counting variables that are only present if + * the active configuration uses a secure counter, to avoid warnings about + * unused variables. + * + * @param statement The statement to be conditionally included. + */ +#define MCUX_CSSL_FP_COUNTER_STMT(statement) \ + MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement) + + +/** + * @def MCUX_CSSL_FP_FUNCTION_DECL + * @brief Declaration of a flow protected function. + * @api + * @ingroup csslFpFunction + * + * This declaration must be placed just in front of the actual function + * declaration. For example: + * @code + * MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here + * uint32_t someFunction(void); + * @endcode + * + * @event{MCUX_CSSL_FP_FUNCTION_CALL} + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED} + * + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_POINTER + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * + * @param id Identifier for the function that is flow protected. + * @param ptrType Optional, pointer type matching this function. + */ +#define MCUX_CSSL_FP_FUNCTION_DECL(...) \ + MCUX_CSSL_FP_FUNCTION_DECL_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_DEF + * @brief Definition of a flow protected function. + * @api + * @ingroup csslFpFunction + * + * This definition macro must be placed just in front of the actual function + * definition, that has been previously declared as flow protected using + * #MCUX_CSSL_FP_FUNCTION_DECL. For example: + * @code + * // someHeader.h + * MCUX_CSSL_FP_FUNCTION_DECL(someFunction) // Note: no semicolon here + * uint32_t someFunction(void); + * + * // someFile.c + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * // some function body + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_POINTER + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * + * @param id Identifier for the function that is flow protected. + * @param ptrType Optional, pointer type matching this function. + */ +#define MCUX_CSSL_FP_FUNCTION_DEF(...) \ + MCUX_CSSL_FP_FUNCTION_DEF_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_POINTER + * @brief Definition of a flow protected function pointer. + * @api + * @ingroup csslFpFunction + * + * This definition macro must be placed around a function pointer + * definition. For example: + * @code + * // someHeader.h + * MCUX_CSSL_FP_FUNCTION_POINTER(ptrType, + * typedef void (*ptrType)(void)); + * + * MCUX_CSSL_FP_FUNCTION_DECL(someFunction, ptrType) // Note: no semicolon here + * uint32_t someFunction(void); + * + * // someFile.c + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction, ptrType) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * // some function body + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * + * @param type Identifier for the function pointer type that is flow protected. + * @param definition Actual type definition of the function pointer type. + */ +#define MCUX_CSSL_FP_FUNCTION_POINTER(type, definition) \ + MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition) + +/** + * @def MCUX_CSSL_FP_FUNCTION_ENTRY + * @brief Flow protection handler for the function entry point. + * @api + * @ingroup csslFpFunction + * + * This entry macro should be placed at the start of the function body that + * needs to be protected. The function must have been declared before as flow + * protected using #MCUX_CSSL_FP_FUNCTION_DECL. For example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // remainder of the function body + * } + * @endcode + * + * The only statements that should be placed before this one, are declarations + * for flow protected operations that are already used as expectations in this + * macro. For example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(uint32_t count) + * { + * MCUX_CSSL_FP_LOOP_DECL(someLoop); + * MCUX_CSSL_FP_LOOP_DECL(otherLoop); + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction, + * MCUX_CSSL_FP_LOOP_ITERATIONS(someLoop, count), + * MCUX_CSSL_FP_LOOP_ITERATIONS(otherLoop, 2u * count) + * ); + * // Remainder of the function body, where someLoop makes count iterations, + * // and otherLoop 2*count iterations. + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the function that has just been entered.
+ * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTRY(...) \ + MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_FUNCTION_EXIT + * @brief Flow protection handler for the function exit point. + * @api + * @ingroup csslFpFunction + * + * This exit macro must replace the regular \c return statements of a protected + * function. Given the following unprotected example: + * @code + * uint32_t someFunction(void) + * { + * // some function body + * return 0; + * } + * @endcode + * The protected version would become: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // remainder of the function body + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0); + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the function from which we will exit. + * - result: Result that should be encoded in the return value. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior. + * @return A value in which both \p result and a flow protection token + * are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT(...) \ + MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @brief Flow protection handler for the function exit point which includes + * an actual check of the code flow. + * @api + * @ingroup csslFpFunction + * + * This exit macro must replace the regular \c return statements of a protected + * function. In addition to #MCUX_CSSL_FP_FUNCTION_EXIT it also checks the flow + * protection, and selects the return value accordingly. For example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // remainder of the function body + * MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(someFunction, 0, 0xFAu); + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the function from which we will exit. + * - pass: Result that should be encoded in the return value if the flow + * protection check passed. + * - fail: Result that should be encoded in the return value if the flow + * protection check failed. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior. + * @return A value in which both the result (either \p pass or \p fail) + * and a flow protection token are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK(...) \ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_FUNCTION_EXIT_VOID + * @brief Flow protection handler for the exit point of functions with the + * return type \c void. + * @api + * @ingroup csslFpFunction + * + * This exit macro must replace the regular \c return statements of a protected + * void function. Given the following unprotected example: + * @code + * void someFunction(void) + * { + * // some function body + * return 0; + * } + * @endcode + * The protected version would become: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * void someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // remainder of the function body + * MCUX_CSSL_FP_FUNCTION_EXIT_VOID(someFunction); + * } + * @endcode + * + * @see MCUX_CSSL_FP_FUNCTION_DECL + * @see MCUX_CSSL_FP_FUNCTION_DEF + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the function from which we will exit. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior. + * @return A protected return value of type void. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID(...) \ + MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_RESULT + * @brief Extract the result value from a protected \p return value. + * @ingroup csslFpFunction + * + * @param return The protected return value which contains the result. + */ +#define MCUX_CSSL_FP_RESULT(return) \ + MCUX_CSSL_FP_RESULT_IMPL(return) + +/** + * @def MCUX_CSSL_FP_PROTECTION_TOKEN + * @brief Extract the protection token value from a protected \p return value. + * @ingroup csslFpFunction + * + * Note that this macro is only used with a local security counter, + * e.g. for configuration CSSL_SC_USE_SW_LOCAL + * + * @param return The protected return value which contains the protection token. + */ +#define MCUX_CSSL_FP_PROTECTION_TOKEN(return) \ + MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL + * @brief Call a flow protected function. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a function. In particular it takes care of extracting the flow + * protection token from the return value (which has been inserted by + * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and + * incorporating that in the flow protection of the current function. For + * example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction()); + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) + * ); + * } + * @endcode + * + * For functions returning void, the macro #MCUX_CSSL_FP_FUNCTION_CALL_VOID + * exists. + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED} + * + * @param ... The following parameters need to be passed (comma separated): + * - result: Fresh variable name to store the result of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID + * @brief Call a flow protected void function. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a void function. In particular it takes care of extracting the + * flow protection token from the return value (which has been inserted by + * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK) and + * incorporating that in the flow protection of the current function. For + * example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_VOID(otherFunction()); + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) + * ); + * } + * @endcode + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED} + * + * @param ... The following parameters need to be passed (comma separated): + * - call: The (protected) void function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED + * @brief Call a flow protected function from unprotected code. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a function from within a function which does not have local + * flow protection, or which uses a different flow protection mechanism than + * the one provided by CSSL. In particular it takes care of extracting the + * protection token and result from the return value (which has been inserted + * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). + * For example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED( + * result, + * token, + * otherFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * // ... The following code may use result as a variable ... + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - result: Fresh variable name to store the result of \p call. + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(__VA_ARGS__) + + /** + * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED + * @brief Call a flow protected void function from unprotected code. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a void function from within a function which does not have flow + * protection, or which uses a different flow protection mechanism than the one + * provided by CSSL. In particular it takes care of extracting the protection + * token and result from the return value (which has been inserted by + * #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). + * For example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED( + * token, + * protectedVoidFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * // ... + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_BEGIN + * @brief Call a flow protected function and check the protection token. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a function from within a function which does not have local + * flow protection, or which uses a different flow protection mechanism than + * the one provided by CSSL. In particular it takes care of extracting the + * protection token and result from the return value (which has been inserted + * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). + * For example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + * result, + * token, + * otherFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * // ... The following code may use result as a variable ... + * MCUX_CSSL_FP_FUNCTION_CALL_END(); + * // ... result is invalid here ... + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - result: Fresh variable name to store the result of \p call. + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_END + * @brief End a function call section started by + * #MCUX_CSSL_FP_FUNCTION_CALL_BEGIN. + * @api + * @ingroup csslFpFunction + * + * Example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + * result, + * token, + * otherFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * // ... The following code may use result as a variable ... + * MCUX_CSSL_FP_FUNCTION_CALL_END(); + * // ... result is invalid here ... + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - result: Fresh variable name to store the result of \p call. + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_END(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN + * @brief Call a flow protected void function and check the protection token. + * @api + * @ingroup csslFpFunction + * + * This function call macro encapsulates the flow protection handling needed + * for calling a void function from within a function which does not have local + * flow protection, or which uses a different flow protection mechanism than + * the one provided by CSSL. In particular it takes care of extracting the + * protection token from the return value (which has been inserted + * by #MCUX_CSSL_FP_FUNCTION_EXIT or #MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK). + * For example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN( + * token, + * otherFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALL_VOID_END + * @brief End a void function call section started by + * #MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN. + * @api + * @ingroup csslFpFunction + * + * Example: + * @code + * uint32_t someUnprotectedFunction(void) + * { + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN( + * token, + * otherFunction()); + * // Check the protection token + * if(MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) != token) + * { + * return FAULT; + * } + * MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(); + * } + * @endcode + * + * @param ... The following parameters need to be passed (comma separated): + * - token: Fresh variable name to store the protection token of \p call. + * - call: The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END(...) \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_FUNCTION_CALLED + * @brief Expectation of a called function. + * @api + * @ingroup csslFpFunction + * + * This expectation macro indicates to the flow protection mechanism that a + * function call is expected to happen (if placed before the actual call), for + * example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction, + * MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) + * ); + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction()); + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0); + * } + * @endcode + * Or that a function call has happened (if placed after the actual call), for + * example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // ... + * MCUX_CSSL_FP_FUNCTION_CALL(result, otherFunction()); + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_FUNCTION_CALLED(otherFunction) + * ); + * } + * @endcode + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @event{MCUX_CSSL_FP_FUNCTION_CALL} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * + * @param ... The following parameters need to be passed (comma separated): + * -id: Identifier of the function that is expected to be called. + */ +#define MCUX_CSSL_FP_FUNCTION_CALLED(...) \ + MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(__VA_ARGS__) + + +/** + * @def MCUX_CSSL_FP_FUNCTION_ENTERED + * @brief Expectation implementation of an entered (but not exited) function. + * @ingroup csslFpFunction + * + * This expectation macro indicates to the flow protection mechanism that a + * function entry has happened, for example: + * @code + * MCUX_CSSL_FP_FUNCTION_DEF(someFunction) // Note: no semicolon here + * uint32_t someFunction(void) + * { + * MCUX_CSSL_FP_FUNCTION_ENTRY(someFunction); + * // ... + * MCUX_CSSL_FP_ASSERT(MCUX_CSSL_FP_FUNCTION_ENTERED(someFunction); + * // ... + * } + * @endcode + * + * @declaration{MCUX_CSSL_FP_FUNCTION_DECL} + * @event{MCUX_CSSL_FP_FUNCTION_CALL} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * @see MCUX_CSSL_FP_FUNCTION_CALLED + * @see MCUX_CSSL_FP_ASSERT + * + * @param id Identifier of the function that is expected to be entered. + * @return Counter value for the given function. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTERED(id) \ + MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id) + + +/** + * @defgroup csslFpLoop Looping flow protection + * @brief Support for flow protected loops. + * @ingroup mcuxCsslFlowProtection + * + * @declaration{MCUX_CSSL_FP_LOOP_DECL} + * @event{MCUX_CSSL_FP_LOOP_ITERATION} + * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS} + */ + +/** + * @def MCUX_CSSL_FP_LOOP_DECL + * @brief Declaration of a flow protected loop. + * @api + * @ingroup csslFpLoop + * + * To inform the flow protection mechanism about a loop that needs to be + * protected, a loop identifier needs to be declared. This identifier can then + * be used in the event and expectation macros. For example: + * @code + * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier); + * for (uint32_t i = 0; i < 8; ++i) + * { + * MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8) + * ); + * @endcode + * + * @event{MCUX_CSSL_FP_LOOP_ITERATION} + * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS} + * + * @param id Identifier for the loop that is flow protected. + */ +#define MCUX_CSSL_FP_LOOP_DECL(id) \ + MCUX_CSSL_FP_LOOP_DECL_IMPL(id) + +/** + * @def MCUX_CSSL_FP_LOOP_ITERATION + * @brief Perform a loop iteration. + * @api + * @ingroup csslFpLoop + * + * This loop iteration macro informs the flow mechanism that an iteration event + * is performed for the loop declared by #MCUX_CSSL_FP_LOOP_DECL with the given + * \p id. For example: + * @code + * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier); + * for (uint32_t i = 0; i < 8; ++i) + * { + * MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier); + * } + * @endcode + * + * @declaration{MCUX_CSSL_FP_LOOP_DECL} + * @expectation{MCUX_CSSL_FP_LOOP_ITERATIONS} + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier for the loop that is flow protected. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_LOOP_ITERATION(...) \ + MCUX_CSSL_FP_LOOP_ITERATION_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_LOOP_ITERATIONS + * @brief Expected number of loop iterations. + * @api + * @ingroup csslFpLoop + * + * This expectation macro indicates to the flow protection mechanism that the + * loop declared by #MCUX_CSSL_FP_LOOP_DECL with the given \p id has made + * \p count iterations. For example: + * @code + * MCUX_CSSL_FP_LOOP_DECL(someLoopIdentifier); + * for (uint32_t i = 0; i < 8; ++i) + * { + * MCUX_CSSL_FP_LOOP_ITERATION(someLoopIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_LOOP_ITERATIONS(someLoopIdentifier, 8) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_LOOP_DECL} + * @event{MCUX_CSSL_FP_LOOP_ITERATION} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * + * @param id Identifier of the flow protected loop. + * @param count Number of expected iterations. + */ +#define MCUX_CSSL_FP_LOOP_ITERATIONS(id, count) \ + MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count) + + + +/** + * @defgroup csslFpBranch Branching flow protection + * @brief Support for flow protected branches. + * @ingroup mcuxCsslFlowProtection + * + * @declaration{MCUX_CSSL_FP_BRANCH_DECL} + * @event{MCUX_CSSL_FP_BRANCH_POSITIVE,MCUX_CSSL_FP_BRANCH_NEGATIVE} + * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE} + */ + +/** + * @def MCUX_CSSL_FP_BRANCH_DECL + * @brief Declaration of a flow protected branch. + * @api + * @ingroup csslFpBranch + * + * To inform the flow protection mechanism about a branch that needs to be + * protected, a branch identifier needs to be declared. This identifier can + * then be used in the events and expectation macros. For example: + * @code + * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier); + * if (condition) + * { + * MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier); + * } + * else + * { + * MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_BRANCH_TAKEN(someBranchIdentifier, + * MCUX_CSSL_FP_BRANCH_POSITIVE_SCENARIO, condition) + * ); + * @endcode + * + * @event{MCUX_CSSL_FP_BRANCH_POSITIVE,MCUX_CSSL_FP_BRANCH_NEGATIVE} + * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE} + * + * @param id Identifier for the branch that is flow protected. + */ +#define MCUX_CSSL_FP_BRANCH_DECL(id) \ + MCUX_CSSL_FP_BRANCH_DECL_IMPL(id) + +/** + * @def MCUX_CSSL_FP_BRANCH_POSITIVE + * @brief Positive scenario for a branch is executed. + * @api + * @ingroup csslFpBranch + * + * This branch event macro informs the flow mechanism that the positive scenario + * of the branch is executed for the branch declared by + * #MCUX_CSSL_FP_BRANCH_DECL with the given \p id. For example: + * @code + * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier); + * if (condition) + * { + * MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier); + * } + * else + * { + * MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition, + * MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_BRANCH_DECL} + * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE} + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier for the branch for which the positive scenario is + * executed. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_POSITIVE(...) \ + MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_BRANCH_NEGATIVE + * @brief Negative scenario of a branch is executed. + * @api + * @ingroup csslFpBranch + * + * This branch event macro informs the flow mechanism that the positive scenario + * of the branch is executed for the branch declared by + * #MCUX_CSSL_FP_BRANCH_DECL with the given \p id. For example: + * @code + * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier); + * if (condition) + * { + * MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier); + * } + * else + * { + * MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * MCUX_CSSL_FP_CONDITIONAL_IMPL(!condition, + * MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_BRANCH_DECL} + * @expectation{MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE} + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier for the branch for which the negative scenario is + * executed. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_NEGATIVE(...) \ + MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE + * @brief Expectation that positive branch has been taken. + * @api + * @ingroup csslFpBranch + * + * This expectation macro indicates to the flow protection mechanism that the + * branch declared by #MCUX_CSSL_FP_BRANCH_DECL with the given \p id has + * executed the positive scenario (under the given \p condition). For example: + * @code + * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier); + * if (condition) + * { + * MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier); + * } + * else + * { + * MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * // Providing the condition as part of the branch expectation. + * // Alternatively, the expectation can be placed in a conditional block. + * MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(someBranchIdentifier, condition) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_BRANCH_DECL} + * @event{MCUX_CSSL_FP_BRANCH_POSITIVE} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * @see MCUX_CSSL_FP_CONDITIONAL + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected branch. + * - condition: Optional, condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE(...) \ + MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE + * @brief Expectation that negative branch has been taken. + * @api + * @ingroup csslFpBranch + * + * This expectation macro indicates to the flow protection mechanism that the + * branch declared by #MCUX_CSSL_FP_BRANCH_DECL with the given \p id has + * executed the negative scenario (under the given \p condition). For example: + * @code + * MCUX_CSSL_FP_BRANCH_DECL(someBranchIdentifier); + * if (condition) + * { + * MCUX_CSSL_FP_BRANCH_POSITIVE(someBranchIdentifier); + * } + * else + * { + * MCUX_CSSL_FP_BRANCH_NEGATIVE(someBranchIdentifier); + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, 0, + * // Providing the branch expectation as part of a conditional block. + * // Alternatively, the condition can be provided in the branch expectation. + * MCUX_CSSL_FP_CONDITIONAL(!condition, + * MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(someBranchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_BRANCH_DECL} + * @event{MCUX_CSSL_FP_BRANCH_NEGATIVE} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * @see MCUX_CSSL_FP_CONDITIONAL + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected branch. + * - condition: Optional, condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE(...) \ + MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(__VA_ARGS__) + + + +/** + * @defgroup csslFpSwitch Switching flow protection + * @brief Support for flow protected switches. + * @ingroup mcuxCsslFlowProtection + * + * @declaration{MCUX_CSSL_FP_SWITCH_DECL} + * @event{MCUX_CSSL_FP_SWITCH_CASE,MCUX_CSSL_FP_SWITCH_DEFAULT} + * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT} + */ + +/** + * @def MCUX_CSSL_FP_SWITCH_DECL + * @brief Declaration of a flow protected switch. + * @api + * @ingroup csslFpSwitch + * + * To inform the flow protection mechanism about a switch that needs to be + * protected, a switch identifier needs to be declared. This identifier can + * then be used in the events and expectation macros. For example: + * @code + * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier); + * switch (arg) + * { + * case 0xC0DEu: + * { + * result = 0xC0DEu; + * MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu); + * break; + * } + * default: + * { + * result = 0; + * MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier); + * break; + * } + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result, + * // Option 1: provide the condition as part of the switch expectation. + * MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg), + * // Option 2: place the switch expectation in a conditional block. + * MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg), + * MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier) + * ) + * ); + * @endcode + * + * @event{MCUX_CSSL_FP_SWITCH_CASE,MCUX_CSSL_FP_SWITCH_DEFAULT} + * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT} + * + * @param id Identifier for the switch that is flow protected. + */ +#define MCUX_CSSL_FP_SWITCH_DECL(id) \ + MCUX_CSSL_FP_SWITCH_DECL_IMPL(id) + +/** + * @def MCUX_CSSL_FP_SWITCH_CASE + * @brief Case that is being handled from a switch. + * @api + * @ingroup csslFpSwitch + * + * This switch event macro informs the flow mechanism that the given \p case of + * the switch is executed for the switch declared by #MCUX_CSSL_FP_SWITCH_DECL + * with the given \p id. For example: + * @code + * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier); + * switch (arg) + * { + * case 0xC0DEu: + * { + * result = 0xC0DEu; + * MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu); + * break; + * } + * default: + * { + * result = 0; + * MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier); + * break; + * } + * } + * // ... + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result, + * // Option 1: provide the condition as part of the switch expectation. + * MCUX_CSSL_FP_SWITCH_TAKEN(someSwitchIdentifier, 0xC0DEu, 0xC0DEu == arg), + * // Option 2: place the switch expectation in a conditional block. + * MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg), + * MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_SWITCH_DECL} + * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN} + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected switch. + * - case: Case value that is chosen in the switch. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_CASE(...) \ + MCUX_CSSL_FP_SWITCH_CASE_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_SWITCH_DEFAULT + * @brief Case that is being handled from a switch. + * @api + * @ingroup csslFpSwitch + * + * This switch event macro informs the flow mechanism that the default case of + * the switch is executed for the switch declared by #MCUX_CSSL_FP_SWITCH_DECL + * with the given \p id. For example: + * @code + * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier); + * switch (arg) + * { + * case 0xC0DEu: + * { + * result = 0xC0DEu; + * MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu); + * break; + * } + * default: + * { + * result = 0; + * MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier); + * break; + * } + * } + * + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result, + * // Option 1: provide the condition as part of the switch expectation. + * MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg), + * // Option 2: place the switch expectation in a conditional block. + * MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg), + * MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_SWITCH_DECL} + * @expectation{MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT} + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected switch. + * - expect: Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_DEFAULT(...) \ + MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_SWITCH_TAKEN + * @brief Expected that a specific case is handled from a switch. + * @api + * @ingroup csslFpSwitch + * + * This expectation macro indicates to the flow protection mechanism that the + * switch declared by #MCUX_CSSL_FP_SWITCH_DECL with the given \p id has + * executed the \p case (under the given \p condition). For example: + * @code + * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier); + * switch (arg) + * { + * case 0xC0DEu: + * { + * result = 0xC0DEu; + * MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu); + * break; + * } + * default: + * { + * result = 0; + * MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier); + * break; + * } + * } + * + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result, + * // Option 1: provide the condition as part of the switch expectation. + * MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg), + * // Option 2: place the switch expectation in a conditional block. + * MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg), + * MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_SWITCH_DECL} + * @event{MCUX_CSSL_FP_SWITCH_CASE} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected switch. + * - case: Value of the case that is expected to be chosen in the + * switch. + * - condition: Optional, condition under which the \p case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN(...) \ + MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(__VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT + * @brief Expected that default case is handled from a switch. + * @api + * @ingroup csslFpSwitch + * + * This expectation macro indicates to the flow protection mechanism that the + * switch declared by #MCUX_CSSL_FP_SWITCH_DECL with the given \p id has + * executed the default case (under the given \p condition). For example: + * @code + * MCUX_CSSL_FP_SWITCH_DECL(someSwitchIdentifier); + * switch (arg) + * { + * case 0xC0DEu: + * { + * result = 0xC0DEu; + * MCUX_CSSL_FP_SWITCH_CASE(someSwitchIdentifier, 0xC0DEu); + * break; + * } + * default: + * { + * result = 0; + * MCUX_CSSL_FP_SWITCH_DEFAULT(someSwitchIdentifier); + * break; + * } + * } + * + * MCUX_CSSL_FP_FUNCTION_EXIT(someFunction, result, + * // Option 1: provide the condition as part of the switch expectation. + * MCUX_CSSL_FP_SWITCH_TAKEN(argCheck, 0xC0DEu, 0xC0DEu == arg), + * // Option 2: place the switch expectation in a conditional block. + * MCUX_CSSL_FP_CONDITIONAL(0xC0DEu != arg), + * MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(someSwitchIdentifier) + * ) + * ); + * @endcode + * + * @declaration{MCUX_CSSL_FP_SWITCH_DECL} + * @event{MCUX_CSSL_FP_SWITCH_DEFAULT} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * + * @param ... The following parameters need to be passed (comma separated): + * - id: Identifier of the flow protected switch. + * - condition: Optional, condition under which the default case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT(...) \ + MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(__VA_ARGS__) + + + +/** + * @defgroup csslFpExpect Expectation handling + * @brief Expectation handling support functionality. + * + * @ingroup mcuxCsslFlowProtection + */ + +/** + * @def MCUX_CSSL_FP_EXPECT + * @brief Declaration(s) of expected code flow behavior. + * @api + * @ingroup csslFpExpect + * + * This macro can be used to indicate expectations in the function body at + * another location than the function entry or exit. + * + * @note In general the use of this macro is discouraged, to avoid a potential + * security and/or code-size impact. However, it may be usefull for complex + * code, where an intermediate update can actually save code, since conditions + * for expectations can than be locallized. + * + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED,MCUX_CSSL_FP_LOOP_ITERATIONS,MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE,MCUX_CSSL_FP_SWITCH_TAKEN} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_CONDITIONAL + * + * @param ... The following parameters need to be passed (comma separated): + * - expect: One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_EXPECT(...) \ + MCUX_CSSL_FP_EXPECT_IMPL(__VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +/** + * @def MCUX_CSSL_FP_CONDITIONAL + * @brief Handling of conditionally expected code flow behavior. + * @api + * @ingroup csslFpExpect + * + * This macro can be used to indicate expectations that are only true under a + * given \p condition. + * + * @expectation{MCUX_CSSL_FP_FUNCTION_CALLED,MCUX_CSSL_FP_LOOP_ITERATIONS,MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE,MCUX_CSSL_FP_SWITCH_TAKEN} + * + * @see MCUX_CSSL_FP_FUNCTION_ENTRY + * @see MCUX_CSSL_FP_FUNCTION_EXIT + * @see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK + * @see MCUX_CSSL_FP_EXPECT + * + * @param condition Condition under which the given expectations apply. + * @param ... One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_CONDITIONAL(condition, ...) \ + MCUX_CSSL_FP_CONDITIONAL_IMPL((condition), __VA_ARGS__, MCUX_CSSL_FP_VOID_EXPECTATION_IMPL()) + +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_3_1 +#endif + +/** + * @def MCUX_CSSL_FP_ASSERT + * @brief Assert an expected state of the code flow. + * @api + * @ingroup csslFpExpect + * + * This macro can be used to check whether the code flow up to this point + * matches the expected state. Unlike the #MCUX_CSSL_FP_EXPECT macro, it will + * not update the expectations, but merely perform a check on the recorded + * events against the already recorded expectations plus the ones provided as + * parameters. + * + * If the check fails, the code defined in #MCUX_CSSL_FP_ASSERT_CALLBACK() will + * be executed. + * + * @note #MCUX_CSSL_FP_ASSERT_CALLBACK() must be defined before including the + * CSSL flow protection headers, otherwise a default implementation could be + * used. + * + * @see MCUX_CSSL_FP_EXPECT + * + * @param ... The following parameters need to be passed (comma separated): + * - expect: One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_ASSERT(...) \ + MCUX_CSSL_FP_ASSERT_IMPL(__VA_ARGS__) + +#endif /* MCUX_CSSL_FLOW_PROTECTION_H_ */ + diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h new file mode 100644 index 000000000..a12c8994a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Cfg.h @@ -0,0 +1,55 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslFlowProtection_Cfg.h + * \brief Configuration of the implementation for the flow protection mechanism. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_CFG_H_ +#define MCUX_CSSL_FLOW_PROTECTION_CFG_H_ + +/** + * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations + * + * \defgroup mcuxCsslFlowProtection_CFG Flow Protection Configuration + * \brief Configuration options for the flow protection mechanism. + * \ingroup mcuxCsslCFG + */ + +/** + * \def MCUX_CSSL_FP_USE_CODE_SIGNATURE + * \brief If set to 1, use the flow protection mechanism implementation based on + * the Zen-V code signature HW mechanism. + * \ingroup mcuxCsslFlowProtection_CFG + */ + #define MCUX_CSSL_FP_USE_CODE_SIGNATURE 0 + +/** + * \def MCUX_CSSL_FP_USE_SECURE_COUNTER + * \brief If set to 1, use the flow protection mechanism implementation based on + * the CSSL secure counter mechanism. + * \ingroup mcuxCsslFlowProtection_CFG + */ + #define MCUX_CSSL_FP_USE_SECURE_COUNTER 1 + +/** + * \def MCUX_CSSL_FP_USE_NONE + * \brief If set to 1, do not use the flow protection mechanism. + * \ingroup mcuxCsslFlowProtection_CFG + */ + #define MCUX_CSSL_FP_USE_NONE 0 + +/* Basic configuration sanity check */ + +#endif /* MCUX_CSSL_FLOW_PROTECTION_CFG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h new file mode 100644 index 000000000..6c8ada833 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_FunctionIdentifiers.h @@ -0,0 +1,129 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslFlowProtection_FunctionIdentifiers.h + * @brief Definition of function identifiers for the flow protection mechanism. + * + * @note This file might be post-processed to update the identifier values to + * proper/secure values. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ +#define MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ + +/* Flow Protection example values: */ +#define MCUX_CSSL_FP_FUNCID_functionOnly0 (0x50DDu) +#define MCUX_CSSL_FP_FUNCID_functionOnly1 (0x5595u) +#define MCUX_CSSL_FP_FUNCID_functionOnly2 (0x6B52u) +#define MCUX_CSSL_FP_FUNCID_functionCall (0x50BBu) +#define MCUX_CSSL_FP_FUNCID_functionCalls (0x4E71u) +#define MCUX_CSSL_FP_FUNCID_functionLoop (0x4AF2u) +#define MCUX_CSSL_FP_FUNCID_functionBranch (0x0D3Bu) +#define MCUX_CSSL_FP_FUNCID_functionSwitch (0x22AFu) +#define MCUX_CSSL_FP_FUNCID_functionComplex (0x781Bu) +#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_compare (0x562Bu) +#define MCUX_CSSL_FP_FUNCID_data_invariant_memory_copy (0x4AA7u) +#define MCUX_CSSL_FP_FUNCID_functionAssert (0x21DEu) +/* Values for production use: */ +#define MCUX_CSSL_FP_FUNCID_mcuxCsslParamIntegrity_Validate (0x1AA7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Compare (0x696Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Copy (0x7D21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Clear (0x42D7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Set (0x44F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureClear (0x29BCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCopy (0x27AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureSet (0x5B58u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureCompare (0x79C2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_CopyPow2 (0x3761u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecCopyPow2 (0x4A5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecComp (0x187Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecClear (0x2C3Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_Int_SecSet (0x6655u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXOR (0x3366u) +#define MCUX_CSSL_FP_FUNCID_mcuxCsslMemory_SecureXORWithConst (0x4A97u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_11 (0x629Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_12 (0x5AF0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_13 (0x53C3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_14 (0x17C5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_15 (0x1E8Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_16 (0x26A7u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_17 (0x14F9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_18 (0x43E9u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_19 (0x533Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_20 (0x2EC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_21 (0x7D44u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_22 (0x2AE3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_23 (0x7274u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_24 (0x7CE0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_25 (0x4DC5u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_26 (0x3E94u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_27 (0x75A4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_28 (0x35E4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_29 (0x63F0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_30 (0x62BAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_31 (0x7549u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_32 (0x77C0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_33 (0x662Eu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_34 (0x521Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_35 (0x6671u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_36 (0x711Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_37 (0x684Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_38 (0x52EAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_39 (0x1EACu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_40 (0x4D66u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_41 (0x4557u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_42 (0x25F2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_43 (0x278Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_44 (0x3C55u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_45 (0x1796u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_46 (0x6732u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_47 (0x67D0u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_48 (0x5627u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_49 (0x6AB1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_50 (0x5927u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_51 (0x51CEu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_52 (0x7585u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_53 (0x78B1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_54 (0x0B5Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_55 (0x6A87u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_56 (0x19ABu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_57 (0x57C1u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_58 (0x589Du) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_59 (0x61E3u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_60 (0x0D2Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_61 (0x5B1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_62 (0x3CD4u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_63 (0x0C6Fu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_64 (0x21BDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_65 (0x1D9Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_66 (0x5674u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_67 (0x60DDu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_68 (0x78AAu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_69 (0x0F36u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_70 (0x6B2Au) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_71 (0x2D63u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_72 (0x2F16u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_73 (0x4F1Cu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_74 (0x5B83u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_75 (0x7833u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_76 (0x3B26u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_77 (0x34DCu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_78 (0x6E46u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_79 (0x6F21u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_80 (0x2937u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_81 (0x1BE2u) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_82 (0x2A9Bu) +#define MCUX_CSSL_FP_FUNCID_mcuxCssl_unused_83 (0x78A3u) + +#endif /* MCUX_CSSL_FLOW_PROTECTION_FUNCTION_IDENTIFIERS_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h new file mode 100644 index 000000000..c87bb78cb --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_Impl.h @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslFlowProtection_Impl.h + * \brief Selection of the implementation for the flow protection mechanism. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_IMPL_H_ +#define MCUX_CSSL_FLOW_PROTECTION_IMPL_H_ + +/* Include the configuration for the flow protection mechanism. */ +#include + +/* Include the selected implementation of the flow protection mechanism. */ +#if defined(MCUX_CSSL_FP_USE_CODE_SIGNATURE) && (1 == MCUX_CSSL_FP_USE_CODE_SIGNATURE) +# include +#elif defined(MCUX_CSSL_FP_USE_SECURE_COUNTER) \ + && (1 == MCUX_CSSL_FP_USE_SECURE_COUNTER) +# include +# include +# if defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL) +# include +# else +# include +# endif +#elif defined(MCUX_CSSL_FP_USE_NONE) && (1 == MCUX_CSSL_FP_USE_NONE) +# include +#else +# error "No flow protection implementation found/configured." +#endif + +#endif /* MCUX_CSSL_FLOW_PROTECTION_IMPL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h new file mode 100644 index 000000000..1a873b5d8 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Common.h @@ -0,0 +1,1061 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslFlowProtection_SecureCounter_Common.h + * \brief Counter based implementation for the flow protection mechanism, for a local security counter. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_ +#define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_ + +/* Include the CSSL C pre-processor support functionality. */ +#include +#include + +/* Include the CSSL secure counter mechanism as basic building block. */ +#include + +/* Include the C99 standard integer types. */ +#include + +/** + * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations + * + * \defgroup mcuxCsslFlowProtection_SecureCounter Flow Protection: Secure Counter + * \brief Secure counter based implementation for the flow protection mechanism. + * \ingroup mcuxCsslIMPL + */ + + +/** + * \defgroup csslFpCntCore Flow protection core functionality + * \brief Flow protection handling core functionality. + * \ingroup mcuxCsslFlowProtection_SecureCounter + * + * \todo Extend this description of the core functionality which relies + * basically on the function calling flow protection. + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL} + * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL} + */ + +/** + * \def MCUX_CSSL_FP_DECL_NAME + * \brief Construct a name based on type and id. + * \ingroup csslFpCntCore + * + * \param type Indicator for the type of declaration. + * \param id Identifier for the flow protected entity. + * \return CSSL flow protection entity name for given \p type and \p id. + */ +#define MCUX_CSSL_FP_DECL_NAME(type, id) \ + MCUX_CSSL_CPP_CAT4(mcuxCsslFlowProtection_, type, _, id) + +/** + * \def MCUX_CSSL_FP_DECL_IMPL + * \brief Generic flow protected entity declaration implementation. + * \ingroup csslFpCntCore + * + * \param type Indicator for the type of declaration. + * \param id Identifier for the flow protected entity. + * \return CSSL flow protection entity declaration. + */ +#define MCUX_CSSL_FP_DECL_IMPL(type, id) \ + MCUX_CSSL_SC_VALUE_TYPE MCUX_CSSL_FP_DECL_NAME(type, id) = \ + MCUX_CSSL_CPP_CAT3(MCUX_CSSL_FP_, type, _ID)(id) + +/** + * \def MCUX_CSSL_FP_ID_IMPL + * \brief Generic identifier generator based on current line number. + * \ingroup csslFpCntCore + * + * \return Counter value based on the current line number. + */ +#define MCUX_CSSL_FP_ID_IMPL() \ + MCUX_CSSL_CPP_CAT(__LINE__, u) + + + +/** + * \defgroup csslFpCntExpect Expectation handling + * \brief Expectation handling support functionality. + * \ingroup mcuxCsslFlowProtection_SecureCounter + */ + +/** + * \def MCUX_CSSL_FP_EXPECTATIONS + * \brief Expectation aggregation. + * \ingroup csslFpCntExpect + * + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + * \return Aggregated counter value for the given expectations. + */ +#define MCUX_CSSL_FP_EXPECTATIONS(...) \ + ((uint32_t) 0u + (MCUX_CSSL_CPP_MAP(MCUX_CSSL_CPP_ADD, __VA_ARGS__))) + +/** + * @def MCUX_CSSL_FP_COUNTER_STMT + * @brief A statement which is only evaluated if a secure counter is used. + * @api + * @ingroup csslFpCntCore + * + * This macro can be used to create counting variables that are only present if + * the active configuration uses a secure counter, to avoid warnings about + * unused variables. + * + * @param statement The statement to be conditionally included. + */ +#define MCUX_CSSL_FP_COUNTER_STMT_IMPL(statement) \ + statement + +/** + * \def MCUX_CSSL_FP_CONDITIONAL_IMPL + * \brief Conditional expectation aggregation. + * \ingroup csslFpCntCore + * + * \param condition Condition under which the given expectations apply + * \param expect One or more (comma separated) declarations of expected code + * code flow behavior. + * \return Aggregated counter value for the given expectations, if + * condition is satisfied. Otherwise 0. + */ +#define MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, ...) \ + (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) & ((condition) ? ((uint32_t) UINT32_MAX) : ((uint32_t) 0))) + +/** + * @def MCUX_CSSL_FP_VOID_EXPECTATION_IMPL + * @brief Implementation of expectation of nothing + * @api + * @ingroup csslFpCntExpect + * + * This expectation macro indicates to the flow protection mechanism that nothing + * is expected to happen. This is mainly intended for internal use (to ensure at + * least one expectation is passed). + */ +#define MCUX_CSSL_FP_VOID_EXPECTATION_IMPL() \ + (0u) + +/** + * \def MCUX_CSSL_FP_EXPECT_IMPL + * \brief Declaration(s) of expected code flow behavior. + * \ingroup csslFpCntExpect + * + * This macro can be used to indicate expectations in the function body at + * another location than the function entry or exit. + * + * \see MCUX_CSSL_FP_EXPECTATIONS + * + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_EXPECT_IMPL(...) \ + MCUX_CSSL_SC_SUB( \ + MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ) + + + +/** + * \defgroup csslFpCntFunction Function calling flow protection + * \brief Support for flow protected functions. + * \ingroup mcuxCsslFlowProtection_SecureCounter + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL} + * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL} + */ + +/** + * \def MCUX_CSSL_FP_FUNCTION_ID + * \brief Generator for function identifiers. + * \ingroup csslFpCntFunction + * + * \param id Identifier for the flow protected function. + */ +#define MCUX_CSSL_FP_FUNCTION_ID(id) \ + MCUX_CSSL_CPP_CAT(MCUX_CSSL_FP_FUNCID_, id) + +/** + * \def MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK + * \brief Mask to be used to derive entry part from a function identifier + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK \ + (0x5A5A5A5Au) + +/** + * \def MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART + * \brief Part of the function identifier to be used at function entry. + * \ingroup csslFpCntFunction + * + * \param id Identifier for the flow protected function. + */ +#define MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id) \ + (MCUX_CSSL_FP_FUNCTION_VALUE(id) & MCUX_CSSL_FP_FUNCTION_ID_ENTRY_MASK) + +/** + * \def MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART + * \brief Part of the function identifier to be used at function exit. + * \ingroup csslFpCntFunction + * + * \param id Identifier for the flow protected function. + */ +#define MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \ + (MCUX_CSSL_FP_FUNCTION_VALUE(id) - MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id)) + +/** + * \def MCUX_CSSL_FP_FUNCTION_DECL_IMPL + * \brief Declaration implementation of a flow protected function. + * \ingroup csslFpCntFunction + * + * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL} + * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL} + * + * @param id Identifier for the function that is flow protected. + * @param ptrType Optional, pointer type matching this function. + */ +#define MCUX_CSSL_FP_FUNCTION_DECL_IMPL(...) \ + /* Intentionally empty */ + +/** + * \def MCUX_CSSL_FP_FUNCTION_VALUE + * \brief Macro to get the value for a given function. + * \ingroup csslFpCntFunction + * + * \param id Identifier for the function that is flow protected. + * \return The counter value for the given function \p id. + */ +#define MCUX_CSSL_FP_FUNCTION_VALUE(id) \ + ((uint32_t) MCUX_CSSL_FP_FUNCTION_ID(id)) + +/** + * \def MCUX_CSSL_FP_FUNCTION_DEF_IMPL + * \brief Definition implementation of a flow protected function. + * \ingroup csslFpCntFunction + * + * Not used in the current implementation. + * + * @param id Identifier for the function that is flow protected. + * @param ptrType Optional, pointer type matching this function. + */ +#define MCUX_CSSL_FP_FUNCTION_DEF_IMPL(...) \ + /* Intentionally empty. */ + +/** + * \def MCUX_CSSL_FP_FUNCTION_POINTER_IMPL + * \brief Definition implementation of a flow protected function pointer. + * \ingroup csslFpNoneFunction + * + * @param type Identifier for the function pointer type that is flow protected. + * @param definition Actual type definition of the function pointer type. + */ +#define MCUX_CSSL_FP_FUNCTION_POINTER_IMPL(type, definition) \ + definition + +/** + * \def MCUX_CSSL_FP_RESULT_OFFSET + * \brief Offset of the result in the return value. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_RESULT_OFFSET \ + (0u) + +/** + * \def MCUX_CSSL_FP_RESULT_MASK + * \brief Bitmask of the result in the return value. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_RESULT_MASK \ + (0xFFFFFFFFuLL) + +/** + * \def MCUX_CSSL_FP_RESULT_VALUE + * \brief Encode a result value for a protected return value. + * \ingroup csslFpCntFunction + * + * \param result The result that needs to be encoded. + */ +#define MCUX_CSSL_FP_RESULT_VALUE(result) \ + (((uint64_t)(result) & MCUX_CSSL_FP_RESULT_MASK) << MCUX_CSSL_FP_RESULT_OFFSET) + +/** + * \def MCUX_CSSL_FP_RESULT_IMPL + * \brief Extract the result value from a protected \p return value. + * \ingroup csslFpCntFunction + * + * \param return The protected return value which contains the result. + */ +#define MCUX_CSSL_FP_RESULT_IMPL(return) \ + (uint32_t)(((return) >> MCUX_CSSL_FP_RESULT_OFFSET) & MCUX_CSSL_FP_RESULT_MASK) + +/** + * \def MCUX_CSSL_FP_PROTECTION_OFFSET + * \brief Offset of the protection token in the return value. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_PROTECTION_OFFSET \ + (32u) + +/** + * \def MCUX_CSSL_FP_PROTECTION_MASK + * \brief Bitmask of the protection token in the return value. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_PROTECTION_MASK \ + ((uint64_t) 0xFFFFFFFFuLL) + +/** + * \def MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE + * \brief Encode a protection token for a protected return value. + * \ingroup csslFpCntFunction + * + * Note that this macro is only used with a local security counter, + * e.g. for configuration CSSL_SC_USE_SW_LOCAL + * + * \param token The protection token that needs to be encoded. + */ +#define MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(token) \ + ((((uint64_t)(token) & MCUX_CSSL_FP_PROTECTION_MASK)) << MCUX_CSSL_FP_PROTECTION_OFFSET) + +/** + * \def MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL + * \brief Extract the protection token value from a protected \p return value. + * \ingroup csslFpCntFunction + * + * Note that this macro is only used with a local security counter, + * e.g. for configuration CSSL_SC_USE_SW_LOCAL + * + * \param return The protected return value which contains the protection token. + */ +#define MCUX_CSSL_FP_PROTECTION_TOKEN_IMPL(return) \ + (uint32_t)(((return) >> MCUX_CSSL_FP_PROTECTION_OFFSET) & MCUX_CSSL_FP_PROTECTION_MASK) + +/** + * \def MCUX_CSSL_FP_COUNTER_COMPRESSED + * \brief Compressed version of the secure counter that can be used as a + * protection token. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_COUNTER_COMPRESSED() \ + MCUX_CSSL_SC_VALUE() + + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALLED_IMPL + * \brief Expectation implementation of a called function. + * \ingroup csslFpCntFunction + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL} + * + * \see MCUX_CSSL_FP_FUNCTION_VALUE + * + * \param id Identifier of the function that is expected to be called. + * \return Counter value for the given function. + */ +#define MCUX_CSSL_FP_FUNCTION_CALLED_IMPL(id) \ + MCUX_CSSL_FP_FUNCTION_VALUE(id) + + +/** + * \def MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL + * \brief Expectation implementation of an entered (but not exited) function. + * \ingroup csslFpCntFunction + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \event{MCUX_CSSL_FP_FUNCTION_CALL_IMPL} + * + * \see MCUX_CSSL_FP_FUNCTION_VALUE + * + * \param id Identifier of the function that is expected to be entered. + * \return Counter value for the given function. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTERED_IMPL(id) \ + MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(id) + + +/** + * \defgroup csslFpCntLoop Looping flow protection + * \brief Support for flow protected loops. + * \ingroup mcuxCsslFlowProtection_SecureCounter + * + * \declaration{MCUX_CSSL_FP_LOOP_DECL_IMPL} + * \event{MCUX_CSSL_FP_LOOP_ITERATION_IMPL} + * \expectation{MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL} + */ + +/** + * \def MCUX_CSSL_FP_LOOP_ID + * \brief Generator for loop identifiers. + * \ingroup csslFpCntLoop + * + * \param id Identifier for the flow protected loop. + * \return Counter value for the given loop. + */ +#define MCUX_CSSL_FP_LOOP_ID(id) \ + MCUX_CSSL_FP_ID_IMPL() + +/** + * \def MCUX_CSSL_FP_LOOP_DECL_IMPL + * \brief Declaration implementation of a flow protected loop. + * \ingroup csslFpCntLoop + * + * \param id Identifier for the loop that is flow protected. + */ +#define MCUX_CSSL_FP_LOOP_DECL_IMPL(id) \ + MCUX_CSSL_FP_DECL_IMPL(LOOP, id) + +/** + * \def MCUX_CSSL_FP_LOOP_VALUE + * \brief Macro to get the value for a given loop. + * \ingroup csslFpCntLoop + * + * \param id Identifier for the loop that is flow protected. + * \return The counter value for the given loop \p id. + */ +#define MCUX_CSSL_FP_LOOP_VALUE(id) \ + MCUX_CSSL_FP_DECL_NAME(LOOP, id) + +/** + * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPLn + * \brief Event implementation of a loop iteration (with expectations). + * \ingroup csslFpCntLoop + * + * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL + * + * \param id Identifier for the loop that is flow protected. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, ...) \ + MCUX_CSSL_SC_ADD( \ + MCUX_CSSL_FP_LOOP_VALUE(id) \ + - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ) + +/** + * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPL1 + * \brief Event implementation of a loop iteration (without expectations). + * \ingroup csslFpCntLoop + * + * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL + * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPLn + * + * \param id Identifier for the loop that is flow protected. + */ +#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL1(id) \ + MCUX_CSSL_FP_LOOP_ITERATION_IMPLn(id, 0u) + +/** + * \def MCUX_CSSL_FP_LOOP_ITERATION_IMPL + * \brief Event implementation of a loop iteration. + * \ingroup csslFpCntLoop + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPL1 + * \see MCUX_CSSL_FP_LOOP_ITERATION_IMPLn + * + * \param id Identifier for the loop that is flow protected. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_LOOP_ITERATION_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_LOOP_ITERATION_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL + * \brief Expectation implementation of a number of loop iterations. + * \ingroup csslFpCntLoop + * + * \param id Identifier of the flow protected loop. + * \param count Number of expected iterations. + */ +#define MCUX_CSSL_FP_LOOP_ITERATIONS_IMPL(id, count) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + ((count) * MCUX_CSSL_FP_LOOP_VALUE(id)) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + + + +/** + * \defgroup csslFpCntBranch Branching flow protection + * \brief Support for flow protected branches. + * \ingroup mcuxCsslFlowProtection_SecureCounter + * + * \declaration{MCUX_CSSL_FP_BRANCH_DECL_IMPL} + * \event{MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL,MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL} + * \expectation{MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL,MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL} + */ + +/** + * \def MCUX_CSSL_FP_BRANCH_ID + * \brief Generator for branch identifiers. + * \ingroup csslFpCntBranch + * + * \param id Identifier for the flow protected branch. + * \return Counter value for the given branch. + */ +#define MCUX_CSSL_FP_BRANCH_ID(id) \ + MCUX_CSSL_FP_ID_IMPL() + +/** + * \def MCUX_CSSL_FP_BRANCH_DECL_IMPL + * \brief Declaration implementation of a flow protected branch. + * \ingroup csslFpCntBranch + * + * \param id Identifier for the branch that is flow protected. + */ +#define MCUX_CSSL_FP_BRANCH_DECL_IMPL(id) \ + MCUX_CSSL_FP_DECL_IMPL(BRANCH, id) + +/** + * \def MCUX_CSSL_FP_BRANCH_VALUE + * \brief Macro to get the value for a given branch. + * \ingroup csslFpCntBranch + * + * \param id Identifier for the branch that is flow protected. + * \return The counter value for the given branch \p id. + */ +#define MCUX_CSSL_FP_BRANCH_VALUE(id) \ + MCUX_CSSL_FP_DECL_NAME(BRANCH, id) + +/** + * \def MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE + * \brief Value to use for the positive scenario. + * \ingroup csslFpCntBranch + */ +#define MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE 0x5u + +/** + * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE + * \brief Value to use for the negative scenario. + * \ingroup csslFpCntBranch + */ +#define MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE 0xAu + +/** + * \def MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL + * \brief Event implementation for the execution of a specified branch scenario. + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL + * + * \param id Identifier for the branch for which the given \p scenario is + * executed. + * \param scenario The scenario for a branch is either positive or negative. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, scenario, ...) \ + MCUX_CSSL_SC_ADD( \ + (MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \ + - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ) + +/** + * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn + * \brief Event implementation for the execution of a positive branch scenario + * (with expectations). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1 + * + * \param id Identifier for the branch for which the positive scenario is + * executed. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn(id, ...) \ + MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, \ + __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1 + * \brief Event implementation for the execution of a positive branch scenario + * (without expectations). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn + * + * \param id Identifier for the branch for which the positive scenario is + * executed. + */ +#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1(id) \ + MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, 0u) + +/** + * \def MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL + * \brief Event implementation for the execution of a positive branch scenario. + * \ingroup csslFpCntBranch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL1 + * \see MCUX_CSSL_FP_BRANCH_POSITIVE_IMPLn + * + * \param id Identifier for the branch for which the positive scenario is + * executed. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_POSITIVE_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn + * \brief Event implementation for the execution of a negative branch scenario + * (with expectations). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1 + * + * \param id Identifier for the branch for which the negative scenario is + * executed. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn(id, ...) \ + MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, \ + __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1 + * \brief Event implementation for the execution of a negative branch scenario + * (without expectations). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn + * + * \param id Identifier for the branch for which the negative scenario is + * executed. + */ +#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1(id) \ + MCUX_CSSL_FP_BRANCH_SCENARIO_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, 0u) + +/** + * \def MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL + * \brief Event implementation for the execution of a negative branch scenario. + * \ingroup csslFpCntBranch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL1 + * \see MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPLn + * + * \param id Identifier for the branch for which the negative scenario is + * executed. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_BRANCH_NEGATIVE_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_IMPL + * \brief Expectation implementation of an executed specified branch scenario. + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL + * + * \param id Identifier of the flow protected branch. + * \param scenario The scenario for a branch is either positive or negative. + * \param condition Condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, scenario, condition) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \ + MCUX_CSSL_FP_BRANCH_VALUE(id) * (scenario)) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2 + * \brief Expectation implementation of an executed positive branch (with + * condition). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1 + * + * \param id Identifier of the flow protected branch. + * \param condition Condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2(id, condition) \ + MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, condition) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1 + * \brief Expectation implementation of an executed positive branch (without + * condition). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2 + * + * \param id Identifier of the flow protected branch. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1(id) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \ + MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_POSITIVE_VALUE, true) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL + * \brief Expectation implementation of an executed positive branch. + * \ingroup csslFpCntBranch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL1 + * \see MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL2 + * + * \param id Identifier of the flow protected branch. + * \param condition Optional, condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_POSITIVE_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2 + * \brief Expectation implementation of an executed negative branch (with + * condition). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1 + * + * \param id Identifier of the flow protected branch. + * \param condition Condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2(id, condition) \ + MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, condition) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1 + * \brief Expectation implementation of an executed negative branch (without + * condition). + * \ingroup csslFpCntBranch + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2 + * + * \param id Identifier of the flow protected branch. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1(id) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \ + MCUX_CSSL_FP_BRANCH_TAKEN_IMPL(id, MCUX_CSSL_FP_BRANCH_NEGATIVE_VALUE, true) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8) + +/** + * \def MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL + * \brief Expectation implementation of an executed negative branch. + * \ingroup csslFpCntBranch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL1 + * \see MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL2 + * + * \param id Identifier of the flow protected branch. + * \param condition Optional, condition under which this branch is taken. + */ +#define MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_BRANCH_TAKEN_NEGATIVE_IMPL, __VA_ARGS__) + + + +/** + * \defgroup csslFpCntSwitch Switching flow protection + * \brief Support for flow protected switches. + * \ingroup mcuxCsslFlowProtection_SecureCounter + * + * \declaration{MCUX_CSSL_FP_SWITCH_DECL_IMPL} + * \event{MCUX_CSSL_FP_SWITCH_CASE_IMPL,MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL} + * \expectation{MCUX_CSSL_FP_SWITCH_TAKEN_IMPL,MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL} + */ + +/** + * \def MCUX_CSSL_FP_SWITCH_ID + * \brief Generator for switch identifiers. + * \ingroup csslFpCntSwitch + * + * \param id Identifier for the flow protected switch. + * \return Counter value for the given loop. + */ +#define MCUX_CSSL_FP_SWITCH_ID(id) \ + MCUX_CSSL_FP_ID_IMPL() + +/** + * \def MCUX_CSSL_FP_SWITCH_DECL_IMPL + * \brief Declaration implementation of a flow protected switch. + * \ingroup csslFpCntSwitch + * + * \param id Identifier for the switch that is flow protected. + */ +#define MCUX_CSSL_FP_SWITCH_DECL_IMPL(id) \ + MCUX_CSSL_FP_DECL_IMPL(SWITCH, id) + +/** + * \def MCUX_CSSL_FP_SWITCH_VALUE + * \brief Macro to get the value for a given switch. + * \ingroup csslFpCntSwitch + * + * \param id Identifier for the switch that is flow protected. + * \return The counter value for the given switch \p id. + */ +#define MCUX_CSSL_FP_SWITCH_VALUE(id) \ + MCUX_CSSL_FP_DECL_NAME(SWITCH, id) + +/** + * \def MCUX_CSSL_FP_SWITCH_CASE_IMPLn + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL2 + * + * \param id Identifier of the flow protected switch. + * \param case Case value that is chosen in the switch. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, ...) \ + MCUX_CSSL_SC_ADD( \ + (MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \ + - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ) + +/** + * \def MCUX_CSSL_FP_SWITCH_CASE_IMPL2 + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPLn + * + * \param id Identifier of the flow protected switch. + * \param case Case value that is chosen in the switch. + */ +#define MCUX_CSSL_FP_SWITCH_CASE_IMPL2(id, case) \ + MCUX_CSSL_FP_SWITCH_CASE_IMPLn(id, case, 0u) + +/** + * \def MCUX_CSSL_FP_SWITCH_CASE_IMPL + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPL2 + * \see MCUX_CSSL_FP_SWITCH_CASE_IMPLn + * + * \param id Identifier of the flow protected switch. + * \param case Case value that is chosen in the switch. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_CASE_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_CASE_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE + * \brief Value to use for default case. + * \ingroup csslFpCntSwitch + */ +#define MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE \ + (0xDEFAu) + +/** + * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1 + * + * \param id Identifier of the flow protected switch. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, ...) \ + MCUX_CSSL_FP_SWITCH_CASE_IMPLn( \ + id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1 + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn + * + * \param id Identifier of the flow protected switch. + */ +#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1(id) \ + MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn(id, 0u) \ + +/** + * \def MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL + * \brief Case that is being handled from a switch. + * \ingroup csslFpCntSwitch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL1 + * \see MCUX_CSSL_FP_SWITCH_DEFAULT_IMPLn + * + * \param id Identifier of the flow protected switch. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior related to this event. + */ +#define MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_SWITCH_DEFAULT_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3 + * \brief Expected that a specific case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2 + * + * \param id Identifier of the flow protected switch. + * \param case Value of the case that is expected to be chosen in the + * switch. + * \param condition Optional, condition under which the \p case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, condition) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_FP_CONDITIONAL_IMPL(condition, \ + MCUX_CSSL_FP_SWITCH_VALUE(id) * (case)) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2 + * \brief Expected that a specific case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3 + * + * \param id Identifier of the flow protected switch. + * \param case Value of the case that is expected to be chosen in the switch. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2(id, case) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \ + MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, case, true) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8) + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_IMPL + * \brief Expected that a specific case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL2 + * \see MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3 + * + * \param id Identifier of the flow protected switch. + * \param case Value of the case that is expected to be chosen in the + * switch. + * \param condition Optional, condition under which the \p case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_SWITCH_TAKEN_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2 + * \brief Expected that default case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1 + * + * \param id Identifier of the flow protected switch. + * \param condition Condition under which the default case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, condition) \ + MCUX_CSSL_FP_SWITCH_TAKEN_IMPL3(id, MCUX_CSSL_FP_SWITCH_DEFAULT_VALUE, condition) + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1 + * \brief Expected that default case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2 + * + * \param id Identifier of the flow protected switch. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1(id) \ + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8, "The macro does not contain a composite expression.") \ + MCUX_CSSL_ANALYSIS_COVERITY_START_DEVIATE(MISRA_C_2012_Rule_14_3, "The usage of an invariant condition here is intended to keep the macro structures more clear.") \ + MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2(id, true) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_DEVIATE(MISRA_C_2012_Rule_14_3) \ + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(MISRA_C_2012_Rule_10_8) + +/** + * \def MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL + * \brief Expected that default case is handled from a switch. + * \ingroup csslFpCntSwitch + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL1 + * \see MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL2 + * + * \param id Identifier of the flow protected switch. + * \param condition Optional, condition under which the default case is taken. + */ +#define MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_SWITCH_TAKEN_DEFAULT_IMPL, __VA_ARGS__) + +/** + * @def MCUX_CSSL_FP_ASSERT_CALLBACK + * @brief Fallback assert callback implementation. + * @api + * @ingroup csslFpCntExpect + * + * This macro will be executed if an #MCUX_CSSL_FP_ASSERT fails. In general this + * behavior should be defined by the user. This implementation is only in place + * to ensure that an implementation is always available. + * + * This is implemented a division by 0, which should trigger a compiler warning + * when used, to inform the user that the default implementation is used. + * Additionally, when still used at run-time it should trigger some system + * exception. + * + * \see MCUX_CSSL_FP_ASSERT + */ +#ifndef MCUX_CSSL_FP_ASSERT_CALLBACK + #define MCUX_CSSL_FP_ASSERT_CALLBACK() \ + return 1/0 /* Fallback ASSERT callback is used, please provide your own. */ +#endif + +#endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_COMMON_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h new file mode 100644 index 000000000..8bc82528b --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslFlowProtection/inc/mcuxCsslFlowProtection_SecureCounter_Local.h @@ -0,0 +1,474 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslFlowProtection_SecureCounter_Local.h + * \brief Counter based implementation for the flow protection mechanism, for a local security counter. + */ + +#ifndef MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_ +#define MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_ + +/* Include the CSSL C pre-processor support functionality. */ +#include + +/* Include the CSSL secure counter mechanism as basic building block. */ +#include + +/* Include the C99 standard integer types. */ +#include + +/* Include standard boolean types */ +#include + + +/** + * \def MCUX_CSSL_FP_PROTECTED_TYPE_IMPL + * \brief Based on a given base type, builds a return type with flow + * protection. + * \ingroup csslFpCntFunction + * + * \see MCUX_CSSL_FP_FUNCTION_DEF_IMPL + * + * \param resultType The type to be converted into a protected type. + */ +#define MCUX_CSSL_FP_PROTECTED_TYPE_IMPL(resultType) \ + uint64_t + +/** + * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn + * \brief Flow protection handler implementation for the function entry point. + * \ingroup csslFpCntFunction + * + * Initialize the counter with the entry part of the function identifier, and + * include expectations in the initialization value. + * + * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL + * + * \param id Identifier of the function that has just been entered. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, ...) \ + MCUX_CSSL_SC_INIT( \ + MCUX_CSSL_FP_FUNCTION_ID_ENTRY_PART(function) \ + - (MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__)) \ + ) + +/** + * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1 + * \brief Flow protection handler implementation for the function entry point. + * \ingroup csslFpCntFunction + * + * Initialize the counter with the entry part of the function identifier, + * without any potential expectations. + * + * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL + * + * \param id Identifier of the function that has just been entered. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1(function) \ + MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn(function, 0u) + +/** + * \def MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL + * \brief Flow protection handler implementation for the function entry point. + * \ingroup csslFpCntFunction + * + * Initialize the counter with entry part of the function identifier, and + * include potential expectations in the initialization value. + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL1 + * \see MCUX_CSSL_FP_FUNCTION_ENTRY_IMPLn + * + * \param id Identifier of the function that has just been entered. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_ENTRY_IMPL, __VA_ARGS__) + + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn + * \brief Flow protection handler implementation for the function exit point. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, and + * include potential expectations in the adjustment value. Return the counter + * value together with the \p result via the function return value. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL + * + * \param id Identifier of the function from which we will exit. + * \param result Result that should be encoded in the return value. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + * \return A value in which both \p result and a flow protection token + * are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, ...) \ + MCUX_CSSL_SC_ADD( \ + MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \ + - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ); \ + return (MCUX_CSSL_FP_RESULT_VALUE(result) \ + | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED())) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1 + * \brief Flow protection handler implementation for the function exit point. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, without + * any potential expectations in the adjustment value. Return the counter value + * via the function return value. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL + * + * \param id Identifier of the function from which we will exit. + * \return A value in which a flow protection token is encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1(id) \ + MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, 0u, 0u) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2 + * \brief Flow protection handler implementation for the function exit point. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, without + * any potential expectations in the adjustment value. Return the counter value + * together with the \p result via the function return value. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL + * + * \param id Identifier of the function from which we will exit. + * \param result Result that should be encoded in the return value. + * \return A value in which both \p result and a flow protection token + * are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2(id, result) \ + MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn(id, result, 0u) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_IMPL + * \brief Flow protection handler implementation for the function exit point. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, and + * include potential expectations in the adjustment value. Return the counter + * value together with the \p result via the function return value. + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL1 + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPL2 + * \see MCUX_CSSL_FP_FUNCTION_EXIT_IMPLn + * + * \param id Identifier of the function from which we will exit. + * \param result Result that should be encoded in the return value. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior. + * \return A value in which both \p result and a flow protection token + * are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED2(MCUX_CSSL_FP_FUNCTION_EXIT_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn + * \brief Flow protection handler implementation for the function exit point + * which includes an actual check of the code flow. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, and + * include potential expectations in the adjustment value. Check whether the + * counter matches the expected value, and choose the result from \p pass and + * \p fail and return it together with the counter value via the function + * return value. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3 + * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn + * + * \param id Identifier of the function from which we will exit. + * \param pass Result that should be encoded in the return value if the flow + * protection check passed. + * \param fail Result that should be encoded in the return value if the flow + * protection check failed. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + * \return A value in which both the result (either \p pass or \p fail) + * and a flow protection token are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, ...) \ + MCUX_CSSL_SC_ADD( \ + MCUX_CSSL_FP_FUNCTION_ID_EXIT_PART(id) \ + - MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__) \ + ); \ + return (MCUX_CSSL_FP_RESULT_VALUE( \ + (MCUX_CSSL_SC_CHECK_PASSED == \ + MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_FUNCTION_VALUE(id))) \ + ? pass : fail) \ + | MCUX_CSSL_FP_PROTECTION_TOKEN_VALUE(MCUX_CSSL_FP_COUNTER_COMPRESSED())) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3 + * \brief Flow protection handler implementation for the function exit point + * which includes an actual check of the code flow. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier. Check + * whether the counter matches the expected value, and choose the result from + * \p pass and \p fail and return it together with the counter value via the + * function return value. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL + * + * \param id Identifier of the function from which we will exit. + * \param pass Result that should be encoded in the return value if the flow + * protection check passed. + * \param fail Result that should be encoded in the return value if the flow + * protection check failed. + * \return A value in which both the result (either \p pass or \p fail) + * and a flow protection token are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3(id, pass, fail) \ + MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn(id, pass, fail, 0u) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL + * \brief Flow protection handler implementation for the function exit point + * which includes an actual check of the code flow. + * \ingroup csslFpCntFunction + * + * Adjust the counter with the exit part of the function identifier, and + * include potential expectations in the adjustment value. Check whether the + * counter matches the expected value, and choose the result from \p pass and + * \p fail and return it together with the counter value via the function + * return value. + * + * Implemented as an overloaded macro to simplify the use of the API. + * + * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL3 + * \see MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPLn + * + * \param id Identifier of the function from which we will exit. + * \param pass Result that should be encoded in the return value if the flow + * protection check passed. + * \param fail Result that should be encoded in the return value if the flow + * protection check failed. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior. + * \return A value in which both the result (either \p pass or \p fail) + * and a flow protection token are encoded. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED3(MCUX_CSSL_FP_FUNCTION_EXIT_WITH_CHECK_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1 + * \brief Flow protection handler for the exit point of functions with the + * return type \c void. + * \ingroup csslFpCntFunction + * + * \param id Identifier of the function from which we will exit. + * \return A protected return value of type void. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL1(id) \ + MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL2 + * \brief Flow protection handler for the exit point of functions with the + * return type \c void. + * \ingroup csslFpCntFunction + * + * \param id Identifier of the function from which we will exit. + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + * \return A protected return value of type void. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPLn(id, ...) \ + MCUX_CSSL_FP_FUNCTION_EXIT_IMPL(id, 0U, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL + * \brief Flow protection handler for the exit point of functions with the + * return type \c void. + * \ingroup csslFpCntFunction + * + * \param id Identifier of the function from which we will exit. + * \param expect Zero or more (comma separated) declarations of expected code + * flow behavior. + * \return A protected return value of type void. + */ +#define MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL(...) \ + MCUX_CSSL_CPP_OVERLOADED1(MCUX_CSSL_FP_FUNCTION_EXIT_VOID_IMPL, __VA_ARGS__) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_IMPL + * \brief Event implementation of a flow protected function call. + * \ingroup csslFpCntFunction + * + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL} + * + * \param result Fresh variable name to store the result of \p call. + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_IMPL(result, call) \ + const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \ + MCUX_CSSL_SC_ADD_ON_CALL( \ + MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \ + const uint32_t result = MCUX_CSSL_FP_RESULT( \ + MCUX_CSSL_CPP_CAT(result, _protected)) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL + * \brief Event implementation of a flow protected void function call. + * \ingroup csslFpNoneFunction + * + * \declaration{MCUX_CSSL_FP_FUNCTION_DECL_IMPL} + * \expectation{MCUX_CSSL_FP_FUNCTION_CALLED_IMPL} + * + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_IMPL(call) \ + { \ + const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \ + MCUX_CSSL_SC_ADD_ON_CALL( \ + MCUX_CSSL_FP_PROTECTION_TOKEN(MCUX_CSSL_CPP_CAT(result, _protected))); \ + } + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL + * \brief Implementation of a flow protected function call meant to be used + * from within an unprotected function + * \ingroup csslFpCntFunction + * + * + * \param result Fresh variable name to store the result of \p call. + * \param token Fresh variable name to store the protection token of \p call. + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call) \ + const uint64_t MCUX_CSSL_CPP_CAT(result, _protected) = (call); \ + const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \ + MCUX_CSSL_CPP_CAT(result, _protected)); \ + const uint32_t result = MCUX_CSSL_FP_RESULT( \ + MCUX_CSSL_CPP_CAT(result, _protected)) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL + * \brief Implementation of a flow protected void function call meant to be + * used from within an unprotected function + * \ingroup csslFpCntFunction + * + * + * \param token Fresh variable name to store the protection token of \p call. + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call) \ + const uint64_t MCUX_CSSL_CPP_CAT(token, _protected) = (call); \ + const uint32_t token = MCUX_CSSL_FP_PROTECTION_TOKEN( \ + MCUX_CSSL_CPP_CAT(token, _protected)); + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL + * \brief Implementation of a flow protected function call meant to be used + * from within an unprotected function, that must be terminated by + * #MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL. + * \ingroup csslFpCntFunction + * + * + * \param result Fresh variable name to store the result of \p call. + * \param token Fresh variable name to store the protection token of \p call. + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL(result, token, call) \ +do \ +{ \ + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED_IMPL(result, token, call) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL + * \brief Implementation of the end of a section started by + * #MCUX_CSSL_FP_FUNCTION_CALL_BEGIN_IMPL. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_END_IMPL() \ +} while (false) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL + * \brief Implementation of a flow protected void function call meant to be used + * from within an unprotected function, that must be terminated by + * #MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL. + * \ingroup csslFpCntFunction + * + * + * \param token Fresh variable name to store the protection token of \p call. + * \param call The (protected) function call that must be performed. + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL(token, call) \ +do \ +{ \ + MCUX_CSSL_FP_FUNCTION_CALL_VOID_PROTECTED_IMPL(token, call) + +/** + * \def MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL + * \brief Implementation of the end of a section started by + * #MCUX_CSSL_FP_FUNCTION_CALL_VOID_BEGIN_IMPL. + * \ingroup csslFpCntFunction + */ +#define MCUX_CSSL_FP_FUNCTION_CALL_VOID_END_IMPL() \ +} while (false) + +/** + * @def MCUX_CSSL_FP_ASSERT_IMPL + * @brief Assert an expected state of the code flow. + * @api + * @ingroup csslFpCntExpect + * + * This macro can be used to check whether the code flow up to this point + * matches the expected state. Unlike the #MCUX_CSSL_FP_EXPECT macro, it will + * not update the expectations, but merely perform a check on the recorded + * events against the already recorded expectations plus the ones provided as + * parameters. + * + * If the check fails, the code defined in MCUX_CSSL_FP_ASSERT_CALLBACK will be + * executed. + * + * \see MCUX_CSSL_FP_EXPECTATIONS + * + * \param expect One or more (comma separated) declarations of expected code + * flow behavior. + */ +#define MCUX_CSSL_FP_ASSERT_IMPL(...) \ + if (MCUX_CSSL_SC_CHECK_PASSED != \ + MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \ + { \ + MCUX_CSSL_FP_ASSERT_CALLBACK(); \ + } \ + else if (MCUX_CSSL_SC_CHECK_PASSED != \ + MCUX_CSSL_SC_CHECK(MCUX_CSSL_FP_EXPECTATIONS(__VA_ARGS__))) \ + { \ + MCUX_CSSL_FP_ASSERT_CALLBACK(); \ + } \ + else {/*empty*/} + +#endif /* MCUX_CSSL_FLOW_PROTECTION_SECURE_COUNTER_LOCAL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h new file mode 100644 index 000000000..2a1effa59 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Compare_asm.h @@ -0,0 +1,171 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Internal_Compare_asm.h + * @brief Internal header of mcuxCsslMemory_Compare inline-asm macro + */ + + +#ifndef MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_ +#define MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_ + +#include +#include + + +#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__) + + +#define MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval_, cur_lhs_, cur_rhs_, nwords_, cnt_, notValid_, result_) \ +do{ \ + uint32_t dat_lhs, dat_rhs; \ + __asm volatile ( \ + "EOR %[_retval], %[_result], %[_notValid]\n" /* retval should now be 0xFFFFFFFF */\ + "LSRS %[_nwords], %[_cnt], #2\n" \ + "CMP %[_nwords], #0\n" \ + "BGT mcuxCsslMemory_Compare_word_loop\n" \ + "BEQ mcuxCsslMemory_Compare_word_loop_end\n" \ + "B mcuxCsslMemory_Compare_fault\n" \ + "mcuxCsslMemory_Compare_word_loop:\n" \ + "LDR %[_dat_lhs], [%[_cur_lhs]], #+4\n" \ + "LDR %[_dat_rhs], [%[_cur_rhs]], #+4\n" \ + "SUBS %[_cnt], %[_cnt], #+4\n" \ + "EORS %[_dat_lhs], %[_dat_lhs], %[_dat_rhs]\n" \ + "BICS %[_retval], %[_retval], %[_dat_lhs]\n" \ + "SUBS %[_nwords], %[_nwords], #+1\n" \ + "MVN %[_dat_rhs], %[_dat_lhs]\n" \ + "AND %[_retval], %[_retval], %[_dat_rhs]\n" \ + "BNE mcuxCsslMemory_Compare_word_loop\n" \ + "mcuxCsslMemory_Compare_word_loop_end:\n" \ + "MOVS %[_dat_lhs], #0\n" \ + "MOVS %[_dat_rhs], #0\n" \ + "CMP %[_cnt], #0\n" \ + "BGT mcuxCsslMemory_Compare_byte_loop\n" \ + "BEQ mcuxCsslMemory_Compare_fault\n" \ + "mcuxCsslMemory_Compare_byte_loop:\n" \ + "LDRB %[_dat_lhs], [%[_cur_lhs]], #+1\n" \ + "LDRB %[_dat_rhs], [%[_cur_rhs]], #+1\n" \ + "EORS %[_dat_lhs], %[_dat_lhs], %[_dat_rhs]\n" \ + "BICS %[_retval], %[_retval], %[_dat_lhs]\n" \ + "SUBS %[_cnt], %[_cnt], #+1\n" \ + "MVN %[_dat_rhs], %[_dat_lhs]\n" \ + "AND %[_retval], %[_retval], %[_dat_rhs]\n" \ + "BNE mcuxCsslMemory_Compare_byte_loop\n" \ + "mcuxCsslMemory_Compare_fault:\n" \ + : [_retval] "=r" (retval_), \ + [_cur_lhs] "+r" (cur_lhs_), \ + [_cur_rhs] "+r" (cur_rhs_), \ + [_cnt] "+r" (cnt_), \ + [_nwords] "+r" (nwords_), \ + [_dat_lhs] "=r" (dat_lhs), \ + [_dat_rhs] "=r" (dat_rhs) \ + : [_notValid] "r" (notValid_), \ + [_result] "r" (result_) \ + ); \ + (void)dat_lhs; \ + (void)dat_rhs; \ + (void)cnt_; \ + (void)notValid_; \ +}while(false) + + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +#define MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval_, cur_lhs_, cur_rhs_, nwords_, cnt_, notValid_, result_) \ +do{ \ + uint32_t dat_lhs, dat_rhs; \ + __asm { \ + EOR retval_, result_, notValid_; \ + LSRS nwords_, cnt_, 2; \ + CMP nwords_, 0; \ + BGT mcuxCsslMemory_Compare_word_loop; \ + BEQ mcuxCsslMemory_Compare_word_loop_end; \ + B mcuxCsslMemory_Compare_fault; \ +mcuxCsslMemory_Compare_word_loop: \ + LDR dat_lhs, [cur_lhs_], +4; \ + LDR dat_rhs, [cur_rhs_], +4; \ + SUBS cnt_, cnt_, 4; \ + EORS dat_lhs, dat_lhs, dat_rhs; \ + BICS retval_, retval_, dat_lhs; \ + SUBS nwords_, nwords_, 1; \ + MVN dat_rhs, dat_lhs; \ + AND retval_, retval_, dat_rhs; \ + BNE mcuxCsslMemory_Compare_word_loop; \ +mcuxCsslMemory_Compare_word_loop_end: \ + MOVS dat_lhs, 0; \ + MOVS dat_rhs, 0; \ + CMP cnt_, 0; \ + BGT mcuxCsslMemory_Compare_byte_loop; \ + BEQ mcuxCsslMemory_Compare_fault; \ +mcuxCsslMemory_Compare_byte_loop: \ + LDRB dat_lhs, [cur_lhs_], +1; \ + LDRB dat_rhs, [cur_rhs_], +1; \ + EORS dat_lhs, dat_lhs, dat_rhs; \ + BICS retval_, retval_, dat_lhs; \ + SUBS cnt_, cnt_, 1; \ + MVN dat_rhs, dat_lhs; \ + AND retval_, retval_, dat_rhs; \ + BNE mcuxCsslMemory_Compare_byte_loop; \ +mcuxCsslMemory_Compare_fault: \ + } \ + (void)dat_lhs; \ + (void)dat_rhs; \ + (void)cnt_; \ + (void)notValid_; \ +}while(false) + +#else + #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax. +#endif + + +/* If the binary representation of retval contains a zero, + * this sequence of instructions will turn retval to zero completely. + * If retval is 0xFFFFFFFF, it will remain untouched. + */ +#if defined(__ghs__) || defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__) +#define MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval_, errCode_) \ +do{ \ + __asm volatile ( \ + "and %[_retval], %[_retval], %[_retval], ror #1\n" \ + "and %[_retval], %[_retval], %[_retval], ror #2\n" \ + "and %[_retval], %[_retval], %[_retval], ror #4\n" \ + "and %[_retval], %[_retval], %[_retval], ror #8\n" \ + "and %[_retval], %[_retval], %[_retval], ror #16\n" \ + "eor %[_retval], %[_retval], %[_errCode]\n" \ + : [_retval] "+r" (retval_) \ + : [_errCode] "r" (errCode_) \ + ); \ + (void)errCode_; \ +}while(false) + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +#define MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval_, errCode_) \ +do{ \ + __asm { \ + AND retval_, retval_, retval_, ror 1; \ + AND retval_, retval_, retval_, ror 2; \ + AND retval_, retval_, retval_, ror 4; \ + AND retval_, retval_, retval_, ror 8; \ + AND retval_, retval_, retval_, ror 16; \ + EOR retval_, retval_, errCode_; \ + } \ + (void)errCode_; \ +}while(false) + +#else + #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax. +#endif + + +#endif /* MCUXCSSLMEMORY_INTERNAL_COMPARE_ASM_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h new file mode 100644 index 000000000..d2dac4623 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_Copy_asm.h @@ -0,0 +1,298 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Internal_Copy_asm.h + * @brief Internal header of mcuxCsslMemory_Copy inline-asm macro + */ + + +#ifndef MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_ +#define MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_ + + +#if defined( __ICCARM__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success) \ +do{ \ + __asm ( \ + "MOV %[_word], #0\n" \ + "MOV %[_datareg], #0\n" \ + "MOV %[_xorword], #0\n" \ + "CMP %[_word], %[_nwords]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "BGE mcuxCsslMemory_Copy_word_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_word_loop:\n" \ + "LDR %[_datareg], [%[_src], %[_word], LSL #2]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + "STR %[_datareg], [%[_dst], %[_word], LSL #2]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_word], %[_word], #+1\n" \ + "EORS %[_xorword], %[_xorword], %[_word]\n" \ + "CMP %[_word], %[_nwords]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "mcuxCsslMemory_Copy_word_loop_end:\n" \ + "LSLS %[_byte], %[_word], #2\n" \ + "MOV %[_datareg], #0\n" \ + "CMP %[_byte], %[_nbytes]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "BGE mcuxCsslMemory_Copy_byte_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_byte_loop:\n" \ + "LDRB %[_datareg], [%[_src], %[_byte]]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + "STRB %[_datareg], [%[_dst], %[_byte]]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_byte], %[_byte], #+1\n" \ + "CMP %[_byte], %[_nbytes]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "mcuxCsslMemory_Copy_byte_loop_end:\n" \ + "MOV %[_datareg], #0\n" \ + "EORS %[_retval], %[_retval], %[_success]\n" \ + "mcuxCsslMemory_Copy_fault:\n" \ + : [_word] "+&r" (word) \ + , [_byte] "+&r" (byte) \ + , [_cha] "+&r" (cha) \ + , [_chb] "+&r" (chb) \ + , [_xorword] "+&r" (xorword) \ + , [_retval] "+r" (retval) \ + , [_datareg] "+&r" (datareg) \ + : [_src] "r" (src) \ + , [_dst] "r" (dst) \ + , [_nwords] "r" (nwords) \ + , [_nbytes] "r" (cnt) \ + , [_success] "r" (success) \ + : "cc", "memory" \ + ); \ + (void)datareg; \ + (void)success; \ +}while(false) + +#elif defined (__ghs__) +#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success) \ +do{ \ + /* GHS compiler can only handle 10 registers for the usecase of this inline asm block. */ \ + /* Store retval and success in registers of word and datareg. */ \ + (word) = (retval); \ + (datareg) = (success); \ + __asm ( \ + /* store retval and success on stack. */ \ + "SUB sp, #8\n" \ + "STR %[_word], [sp, #0]\n" \ + "STR %[_datareg], [sp, #4]\n" \ + /* original asm macro. */ \ + "MOV %[_word], #0\n" \ + "MOV %[_datareg], #0\n" \ + "MOV %[_xorword], #0\n" \ + "CMP %[_word], %[_nwords]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "BGE mcuxCsslMemory_Copy_word_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_word_loop:\n" \ + "LDR %[_datareg], [%[_src], %[_word], LSL #2]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + "STR %[_datareg], [%[_dst], %[_word], LSL #2]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_word], %[_word], #+1\n" \ + "EORS %[_xorword], %[_xorword], %[_word]\n" \ + "CMP %[_word], %[_nwords]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "mcuxCsslMemory_Copy_word_loop_end:\n" \ + "LSLS %[_byte], %[_word], #2\n" \ + "MOV %[_datareg], #0\n" \ + "CMP %[_byte], %[_nbytes]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "BGE mcuxCsslMemory_Copy_byte_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_byte_loop:\n" \ + "LDRB %[_datareg], [%[_src], %[_byte]]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + "STRB %[_datareg], [%[_dst], %[_byte]]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_byte], %[_byte], #+1\n" \ + "CMP %[_byte], %[_nbytes]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "mcuxCsslMemory_Copy_byte_loop_end:\n" \ + /* load retval and success from stack. */ \ + "LDR %[_datareg], [sp, #0]\n" \ + /* use byte as temp. */ \ + "STR %[_byte], [sp, #0]\n" \ + "LDR %[_byte], [sp, #4]\n" \ + /* set datareg = retval ^ success, instead of datareg = 0 in the original design. */ \ + "EORS %[_datareg], %[_datareg], %[_byte]\n" \ + "LDR %[_byte], [sp, #0]\n" \ + "mcuxCsslMemory_Copy_fault:\n" \ + "ADD sp, #8\n" \ + : [_word] "+&r" (word) \ + , [_byte] "+&r" (byte) \ + , [_cha] "+&r" (cha) \ + , [_chb] "+&r" (chb) \ + , [_xorword] "+&r" (xorword) \ + , [_datareg] "+&r" (datareg) \ + : [_src] "r" (src) \ + , [_dst] "r" (dst) \ + , [_nwords] "r" (nwords) \ + , [_nbytes] "r" (cnt) \ + : "cc", "memory" \ + ); \ + (retval) = (datareg); \ +}while(false) + +#elif defined (__GNUC__) +#define MCUXCSSLMEMORY_COPY_SUCCESS_IMPL ((uint32_t)MCUXCSSLMEMORY_STATUS_OK ^ (uint32_t)MCUXCSSLMEMORY_STATUS_FAULT) +#define MCUXCSSLMEMORY_COPY_DST_STACK_OFFSET (0) +#define MCUXCSSLMEMORY_COPY_SRC_STACK_OFFSET (4) +#define MCUXCSSLMEMORY_COPY_RETVAL_STACK_OFFSET (8) +#define MCUXCSSLMEMORY_COPY_CNT_STACK_OFFSET (12) +#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success) \ +do{ \ + /* [DESIGN] + * GNU compiler can only handle 7 registers for the usecase of this inline asm block, when building with optimization level 0. + * Thus, 5 registers need to be saved compared to the original asm macro. + * success is a constant, so it is defined as an immediatte instead of an input register. + * 4 registers can be used as temporary registers to push data to the stack: store retval, cnt, src, dst in registers of word, datareg, xorword, byte. */ \ + uint32_t nwords_cnt = (nwords); \ + (word) = (retval); \ + (datareg) = (cnt); \ + (xorword) = (uint32_t)(src); \ + (byte) = (uint32_t)(dst); \ + __asm ( \ + /* [DESIGN] store retval, success, src, dst on stack. */ \ + "SUB sp, #16\n" \ + "STR %[_word], [sp, %[_RETVAL_OFFSET]]\n" \ + "STR %[_datareg], [sp, %[_CNT_OFFSET]]\n" \ + "STR %[_byte], [sp, %[_DST_OFFSET]]\n" \ + "STR %[_xorword], [sp, %[_SRC_OFFSET]]\n" \ + /* [DESIGN] original asm macro. */ \ + "MOV %[_word], #0\n" \ + "MOV %[_datareg], #0\n" \ + "MOV %[_xorword], #0\n" \ + "CMP %[_word], %[_nwords_cnt]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "BGE mcuxCsslMemory_Copy_word_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_word_loop:\n" \ + /* [DESIGN] get src from the stack, _datareg is used as a temporary register */ \ + "LDR %[_datareg], [sp, %[_SRC_OFFSET]]\n" \ + "LDR %[_datareg], [%[_datareg], %[_word], LSL #2]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + /* [DESIGN] _byte already contains the value of dst */ \ + "STR %[_datareg], [%[_byte], %[_word], LSL #2]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_word], %[_word], #+1\n" \ + "EORS %[_xorword], %[_xorword], %[_word]\n" \ + "CMP %[_word], %[_nwords_cnt]\n" \ + "BLT mcuxCsslMemory_Copy_word_loop\n" \ + "mcuxCsslMemory_Copy_word_loop_end:\n" \ + "LSLS %[_byte], %[_word], #2\n" \ + "MOV %[_datareg], #0\n" \ + "LDR %[_nwords_cnt], [sp, %[_CNT_OFFSET]]\n" \ + /* [DESIGN] store word to the stack, at the offset of cnt which is not needed on stack anymore */ \ + "STR %[_word], [sp, %[_CNT_OFFSET]]\n" \ + /* [DESIGN] get dst from the stack, _word is used as a temporary register */ \ + "LDR %[_word], [sp, %[_DST_OFFSET]]\n" \ + "CMP %[_byte], %[_nwords_cnt]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "BGE mcuxCsslMemory_Copy_byte_loop_end\n" \ + "B mcuxCsslMemory_Copy_fault\n" \ + "mcuxCsslMemory_Copy_byte_loop:\n" \ + /* [DESIGN] get src from the stack, _datareg is used as a temporary register */ \ + "LDR %[_datareg], [sp, %[_SRC_OFFSET]]\n" \ + "LDRB %[_datareg], [%[_datareg], %[_byte]]\n" \ + "EORS %[_cha], %[_cha], %[_datareg]\n" \ + /* [DESIGN] _word already contains the value of dst */ \ + "STRB %[_datareg], [%[_word], %[_byte]]\n" \ + "EORS %[_chb], %[_chb], %[_datareg]\n" \ + "ADDS %[_byte], %[_byte], #+1\n" \ + "CMP %[_byte], %[_nwords_cnt]\n" \ + "BLT mcuxCsslMemory_Copy_byte_loop\n" \ + "mcuxCsslMemory_Copy_byte_loop_end:\n" \ + /* [DESIGN] load retval from stack. */ \ + "LDR %[_datareg], [sp, %[_RETVAL_OFFSET]]\n" \ + /* [DESIGN] use _byte as temp. */ \ + "STR %[_byte], [sp, %[_RETVAL_OFFSET]]\n" \ + "LDR %[_byte], =%[_SUCCESS]\n" \ + /* [DESIGN] set datareg = retval ^ success, instead of datareg = 0 in the original design. */ \ + "EORS %[_datareg], %[_datareg], %[_byte]\n" \ + "LDR %[_byte], [sp, %[_RETVAL_OFFSET]]\n" \ + "LDR %[_word], [sp, %[_CNT_OFFSET]]\n" \ + "mcuxCsslMemory_Copy_fault:\n" \ + "ADD sp, #16\n" \ + : [_word] "+&r" (word) \ + , [_byte] "+&r" (byte) \ + , [_cha] "+&r" (cha) \ + , [_chb] "+&r" (chb) \ + , [_xorword] "+&r" (xorword) \ + , [_datareg] "+&r" (datareg) \ + , [_nwords_cnt] "+&r" (nwords_cnt) \ + : [_SUCCESS] "i" MCUXCSSLMEMORY_COPY_SUCCESS_IMPL \ + , [_DST_OFFSET] "i" MCUXCSSLMEMORY_COPY_DST_STACK_OFFSET \ + , [_SRC_OFFSET] "i" MCUXCSSLMEMORY_COPY_SRC_STACK_OFFSET \ + , [_RETVAL_OFFSET] "i" MCUXCSSLMEMORY_COPY_RETVAL_STACK_OFFSET \ + , [_CNT_OFFSET] "i" MCUXCSSLMEMORY_COPY_CNT_STACK_OFFSET \ + : "cc", "memory" \ + ); \ + (retval) = (datareg); \ + (void) success; \ +}while(false) + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +#define MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, src, dst, nwords, cnt, success) \ +do{ \ + __asm { \ + MOV word, 0; \ + MOV datareg, 0; \ + MOV xorword, 0; \ + CMP word, nwords; \ + BLT mcuxCsslMemory_Copy_word_loop; \ + BGE mcuxCsslMemory_Copy_word_loop_end; \ + B mcuxCsslMemory_Copy_fault; \ +mcuxCsslMemory_Copy_word_loop: \ + LDR datareg, [src, word, LSL 2]; \ + EORS cha, cha, datareg; \ + STR datareg, [dst, word, LSL 2]; \ + EORS chb, chb, datareg; \ + ADDS word, word, +1; \ + EORS xorword, xorword, word; \ + CMP word, nwords; \ + BLT mcuxCsslMemory_Copy_word_loop; \ +mcuxCsslMemory_Copy_word_loop_end: \ + LSLS byte, word, 2; \ + MOV datareg, 0; \ + CMP byte, cnt; \ + BLT mcuxCsslMemory_Copy_byte_loop; \ + BGE mcuxCsslMemory_Copy_byte_loop_end; \ + B mcuxCsslMemory_Copy_fault; \ +mcuxCsslMemory_Copy_byte_loop: \ + LDRB datareg, [src, byte]; \ + EORS cha, cha, datareg; \ + STRB datareg, [dst, byte]; \ + EORS chb, chb, datareg; \ + ADDS byte, byte, +1; \ + CMP byte, cnt; \ + BLT mcuxCsslMemory_Copy_byte_loop; \ +mcuxCsslMemory_Copy_byte_loop_end: \ + MOV datareg, 0; \ + EORS retval, retval, success; \ +mcuxCsslMemory_Copy_fault: \ + } \ + (void)datareg; \ + (void)success; \ +}while(false) + +#else + #error Unsupported compiler. The above section must be manually adapted to support your compiler inline assembly syntax. +#endif /* Compiler selection */ + + +#endif /* MCUXCSSLMEMORY_INTERNAL_COPY_ASM_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h new file mode 100644 index 000000000..c30fd2781 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/internal/mcuxCsslMemory_Internal_SecureCompare.h @@ -0,0 +1,55 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Internal_SecureCompare.h + * @brief Internal header of mcuxCsslMemory_SecureCompare + */ + + +#ifndef MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H_ +#define MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H_ + +#include +#include +#include + +/** + * @brief Securely compares the two memory regions @p lhs and @p rhs - internal use only + * + * The implementation is secure in the following aspects: + * + * * Constant execution time: The execution sequence of the code is always identical for equal @p length parameters, + * i.e. no branches are performed based on the data in @p pLhs or @p pRhs. + * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation. + * * Random order memory access: an attacker shall not be able to distinguish the position of the difference between the two compared buffers. + * * Blinded word compare: SPA protection. + * * Integrity of the result is ensured. The accumulator of differences is checked twice when generating the return status (EQUAL or NOT_EQUAL). + * * Data Integrity: Record(pLhs + pRhs + length) + * + * @param pLhs The left-hand side data to compare. Must not be NULL. + * @param pRhs The right-hand side data to compare. Must not be NULL. + * @param length The number of bytes to compare. Must be different from zero. + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLMEMORY_STATUS_EQUAL If the contents of @p lhs and @p rhs are equal. + * @retval #MCUXCSSLMEMORY_STATUS_NOT_EQUAL If the contents of @p lhs and @p rhs are not equal. + * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Int_SecComp) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Int_SecComp( + const uint8_t * pLhs, + const uint8_t * pRhs, + uint32_t length +); + +#endif /* MCUXCSSLMEMORY_INTERNAL_SECURECOMPARE_H */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h new file mode 100644 index 000000000..9fac4d1f6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory.h @@ -0,0 +1,40 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory.h + * @brief Top-level include file for the CSSL memory functions + */ + +#ifndef MCUXCSSLMEMORY_H +#define MCUXCSSLMEMORY_H + +/** + * @defgroup mcuxCsslMemory mcuxCssl Memory API + * @brief Control Flow Protected Memory Functions + * + * @ingroup mcuxCsslAPI + */ +#include + + +#include + +#include + +#include + +#include + + +#endif diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h new file mode 100644 index 000000000..a07b6c7a7 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Clear.h @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Clear.h + * @brief header file of memory clear function + */ + + +#ifndef MCUXCSSLMEMORY_CLEAR_H_ +#define MCUXCSSLMEMORY_CLEAR_H_ + +#include +#include +#include +#include +#include + +/** + * @defgroup mcuxCsslMemory_Clear mcuxCssl Memory Clear + * @brief Control Flow Protected Memory Clear Function + * + * @ingroup mcuxCsslMemory + * @{ + */ + +/** + * @defgroup mcuxCsslMemory_Clear_Functions mcuxCsslMemory_Clear Function Definitions + * @brief mcuxCsslMemory_Clear Function Definitions + * + * @ingroup mcuxCsslMemory_Clear + * @{ + */ + +/** + * @brief Clear @p length bytes of data at @p pDst + * + * The implementation is secure in the following aspects: + * Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum. + * Code flow protection: the function call is protected. + * Buffer overflow protection: no data is written to @p pDst beyond @p dstLength bytes. + * + * @param[in] chk The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect. + * @param[in] pDst The destination pointer to buffer to be cleared. Must not be NULL. + * @param[in] dstLength The size of the destination data buffer in bytes. + * @param[in] length The number of bytes to clear. Must be different from zero. + * + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLMEMORY_STATUS_OK If the contents in buffer at @p pDst is cleared. + * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters is invalid. + * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected, included invalid checksum @p chk. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Clear) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Clear +( + mcuxCsslParamIntegrity_Checksum_t chk, + void * pDst, + size_t dstLength, + size_t length +); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MCUXCSSLMEMORY_CLEAR_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h new file mode 100644 index 000000000..0e255210d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Compare.h @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Compare.h + * @brief Include file for constant time memory compare function + */ + +#ifndef MCUXCSSLMEMORY_COMPARE_H +#define MCUXCSSLMEMORY_COMPARE_H + +#include +#include +#include +#include + +/** + * @defgroup mcuxCsslMemory_Compare mcuxCssl Memory Compare + * @brief Control Flow Protected Memory Compare Function + * + * @ingroup mcuxCsslMemory + * @{ + */ + +/** + * @defgroup mcuxCsslMemory_Compare_Functions mcuxCsslMemory_Compare Function Definitions + * @brief mcuxCsslMemory_Compare Function Definitions + * + * @ingroup mcuxCsslMemory_Compare + * @{ + */ + +/** + * @brief Compares the two memory regions @p lhs and @p rhs + * + * The implementation is secure in the following aspects: + * + * * Constant execution time: The execution sequence of the code is always identical for equal @p length parameters, + * i.e. no branches are performed based on the data in @p pLhs or @p pRhs. + * * Parameter integrity protection: An incorrect parameter checksum makes the function return immediately. + * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation. + * + * @param chk The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect. + * @param pLhs The left-hand side data to compare. Must not be NULL. + * @param pRhs The right-hand side data to compare. Must not be NULL. + * @param length The number of bytes to compare. Must be different from zero. + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLMEMORY_STATUS_EQUAL If the contents of @p lhs and @p rhs are equal. + * @retval #MCUXCSSLMEMORY_STATUS_NOT_EQUAL If the contents of @p lhs and @p rhs are not equal. + * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters was invalid (i.e. @p lhs or @p rhs was NULL or @p length was zero). + * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Compare) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Compare +( + mcuxCsslParamIntegrity_Checksum_t chk, + void const * pLhs, + void const * pRhs, + size_t length +); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h new file mode 100644 index 000000000..cef6a8b65 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Copy.h @@ -0,0 +1,77 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Copy.h + * @brief Include file for memory copy function + */ + +#ifndef MCUXCSSLMEMORY_COPY_H_ +#define MCUXCSSLMEMORY_COPY_H_ + +/** + * @defgroup mcuxCsslMemory_Copy mcuxCssl Memory Copy + * @brief Control Flow Protected Memory Copy Function + * + * @ingroup mcuxCsslMemory + * @{ + */ + +/** + * @defgroup mcuxCsslMemory_Copy_Functions mcuxCsslMemory_Copy Function Definitions + * @brief mcuxCsslMemory_Copy Function Definitions + * + * @ingroup mcuxCsslMemory_Copy + * @{ + */ + +/** + * @brief Copies @p length bytes of data from @p pSrc to @p pDst + * + * The implementation is secure in the following aspects: + * + * * Constant execution time: If @p pSrc and @p pDst have the same offset to the nearest 16-byte boundary, and if @p length + * is the same, the execution sequence of the code is always identical. + * * Parameter integrity protection: An incorrect parameter checksum makes the function return immediately. + * * Code flow protection: The function call is protected. Additionally, the result depends on all steps of the calculation. + * * Buffer overflow protection: No data is written to @p pDst beyond @p dstLength bytes. + * + * @param[in] chk The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect. + * @param[in] pSrc The data to be copied. Must not be NULL. Must not overlap with @p pDst. + * @param[out] pDst The destination pointer. Must not be NULL. Must not overlap with @p pSrc. + * @param[in] dstLength The size of the destination data buffer in bytes. + * @param[in] length The number of bytes to copy. Must be different from zero. + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLMEMORY_STATUS_OK If the operation was successful. + * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters was invalid (i.e. @p pSrc or @p pDst was NULL or @p length was zero). + * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Copy) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Copy +( + mcuxCsslParamIntegrity_Checksum_t chk, + void const * pSrc, + void * pDst, + size_t dstLength, + size_t length +); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MCUXCSSLMEMORY_COPY_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h new file mode 100644 index 000000000..0dbefb2ec --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Set.h @@ -0,0 +1,82 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021, 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Set.h + * @brief header file of memory set function + */ + + +#ifndef MCUXCSSLMEMORY_SET_H_ +#define MCUXCSSLMEMORY_SET_H_ + +#include +#include +#include +#include +#include + +/** + * @defgroup mcuxCsslMemory_Set mcuxCssl Memory Set + * @brief Control Flow Protected Memory Set Function + * + * @ingroup mcuxCsslMemory + * @{ + */ + +/** + * @defgroup mcuxCsslMemory_Set_Functions mcuxCsslMemory_Set Function Definitions + * @brief mcuxCsslMemory_Set Function Definitions + * + * @ingroup mcuxCsslMemory_Set + * @{ + */ + +/** + * @brief Set @p length bytes of data at @p pDst + * + * The implementation is secure in the following aspects: + * Parameter integrity protection: the function returns immediately in case of an incorrect parameter checksum. + * Code flow protection: the function call is protected. + * Buffer overflow protection: no data is written to @p pDst beyond @p bufLength bytes. + * + * @param[in] chk The parameter checksum, generated with #mcuxCsslParamIntegrity_Protect. + * @param[in] pDst The destination pointer to buffer to be set. Must not be NULL. + * @param[in] val The byte value to be set. + * @param[in] length The size in bytes to set. Must be different from zero. + * @param[in] bufLength The buffer size (if bufLength < length, only bufLength bytes are set). + * + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLMEMORY_STATUS_OK If @p val set @p length times at @p pDst. + * @retval #MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER If one of the parameters is invalid. + * @retval #MCUXCSSLMEMORY_STATUS_FAULT If a fault was detected, included invalid checksum @p chk. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslMemory_Set) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Set +( + mcuxCsslParamIntegrity_Checksum_t chk, + void * pDst, + uint8_t val, + size_t length, + size_t bufLength +); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MCUXCSSLMEMORY_SET_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h new file mode 100644 index 000000000..114804a9a --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/inc/mcuxCsslMemory_Types.h @@ -0,0 +1,74 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Types.h + * @brief Type definitions for the mcuxCsslMemory component + */ + +#ifndef MCUXCSSLMEMORY_TYPES_H +#define MCUXCSSLMEMORY_TYPES_H + +#include + +/** + * @defgroup mcuxCsslMemory_Types mcuxCsslMemory_Types + * @brief Defines common macros and types of @ref mcuxCsslMemory + * @ingroup mcuxCsslMemory + * @{ + */ + +/********************************************** + * CONSTANTS + **********************************************/ +/** + * @defgroup mcuxCsslMemory_Types_Macros mcuxCsslMemory_Types_Macros + * @brief Defines all macros of @ref mcuxCsslMemory_Types + * @ingroup mcuxCsslMemory_Types + * @{ + */ +#define MCUXCSSLMEMORY_STATUS_OK ((mcuxCsslMemory_Status_t) 0xE1E11E1Eu) ///< The operation was successful +#define MCUXCSSLMEMORY_STATUS_EQUAL ((mcuxCsslMemory_Status_t) 0xE1E1E1E1u) ///< The two contents of the Memory Compare are equal +#define MCUXCSSLMEMORY_STATUS_NOT_EQUAL ((mcuxCsslMemory_Status_t) 0x1E1E1E1Eu) ///< The two contents of the Memory Compare are not equal +#define MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER ((mcuxCsslMemory_Status_t) 0x69696969u) ///< A parameter was invalid +#define MCUXCSSLMEMORY_STATUS_FAULT ((mcuxCsslMemory_Status_t) 0x96969696u) ///< A fault occurred in the execution + +#define MCUXCSSLMEMORY_KEEP_ORDER ((uint32_t) 0xE1E139A5u) ///< Data storing in destination buffer in original order. +#define MCUXCSSLMEMORY_REVERSE_ORDER ((uint32_t) 0xE1E1395Au) ///< Data storing in destination buffer with reversed order. +/** + * @} + */ + + +/********************************************** + * TYPEDEFS + **********************************************/ + +/** + * @defgroup mcuxCsslMemory_Types_Types mcuxCsslMemory_Types_Types + * @brief Defines all types of @ref mcuxCsslMemory_Types + * @ingroup mcuxCsslMemory_Types + * @{ + */ + +/** + * @brief Type for CSSL Memory status codes. + */ +typedef uint32_t mcuxCsslMemory_Status_t; +/** + * @} + * + * @} + */ + +#endif /* MCUXCSSLMEMORY_TYPES_H */ diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c new file mode 100644 index 000000000..f7e0e8bb0 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Clear.c @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Clear.c + * @brief mcuxCsslMemory: implementation of secure memory clear function + */ + + +#include +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Clear) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Clear +( + mcuxCsslParamIntegrity_Checksum_t chk, + void * pDst, + size_t dstLength, + size_t length +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Clear, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate) ); + + MCUX_CSSL_FP_FUNCTION_CALL(retCode_paramIntegrityValidate, mcuxCsslParamIntegrity_Validate(chk, 3u, pDst, dstLength, length)); + if ((retCode_paramIntegrityValidate != MCUXCSSLPARAMINTEGRITY_CHECK_VALID)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, MCUXCSSLMEMORY_STATUS_FAULT); + } + + if (length > dstLength) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER); + } + + MCUX_CSSL_FP_FUNCTION_CALL(retCode_memSet, mcuxCsslMemory_Set(mcuxCsslParamIntegrity_Protect(4u, pDst, 0u, length, dstLength), pDst, 0u, length, dstLength) ); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Clear, retCode_memSet, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Set )); +} diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c new file mode 100644 index 000000000..0c4ccef51 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Compare.c @@ -0,0 +1,72 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Compare) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Compare +( + mcuxCsslParamIntegrity_Checksum_t chk, + void const * pLhs, + void const * pRhs, + size_t length +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Compare, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate) + ); + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxCsslParamIntegrity_Validate(chk, 3u, pLhs, pRhs, length)); + + if( (result != MCUXCSSLPARAMINTEGRITY_CHECK_VALID)) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_FAULT); + } + + if((NULL == pLhs) || (NULL == pRhs) || (0u == length)) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER); + } + + uint32_t nwords = 0u; + uint32_t retval = 0u; + uint8_t const * cur_lhs = pLhs; + uint8_t const * cur_rhs = pRhs; + uint32_t const notValid = ~(MCUXCSSLPARAMINTEGRITY_CHECK_VALID); + uint32_t const errCode = (uint32_t)MCUXCSSLMEMORY_STATUS_NOT_EQUAL; + + /* Pre-calculate end pointers */ + uint8_t const * end_lhs = &cur_lhs[length]; + uint8_t const * end_rhs = &cur_rhs[length]; + +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_11_3 "Exception 9: re-interpreting the memory for word access" +#endif + MCUXCSSLMEMORY_COMPARE_ASM_COMPARISON(retval, cur_lhs, cur_rhs, nwords, length, notValid, result); +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_11_3 +#endif + + MCUXCSSLMEMORY_COMPARE_ASM_CALC_RETVAL(retval, errCode); + + /* Check that the pointers reached the end */ + if((end_lhs != cur_lhs) || (end_rhs != cur_rhs)) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, MCUXCSSLMEMORY_STATUS_FAULT); + } + + MCUX_CSSL_SC_ADD(nwords); // -> should be 0 + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Compare, retval); +} diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c new file mode 100644 index 000000000..eb040f7bd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Copy.c @@ -0,0 +1,76 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Copy) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Copy +( + mcuxCsslParamIntegrity_Checksum_t chk, + void const * pSrc, + void * pDst, + size_t dstLength, + size_t length +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Copy, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate) + ); + + MCUX_CSSL_FP_FUNCTION_CALL(result, mcuxCsslParamIntegrity_Validate(chk, 4u, pSrc, pDst, dstLength, length)); + + if(result != MCUXCSSLPARAMINTEGRITY_CHECK_VALID) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, MCUXCSSLMEMORY_STATUS_FAULT); + } + + if((NULL == pSrc) || (NULL == pDst) || (length > dstLength) || (0u == length)) { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER); + } + + uint32_t retval = (uint32_t) MCUXCSSLMEMORY_STATUS_FAULT; + + const uint32_t nwords = length / 4U; + const uint32_t success = (uint32_t)MCUXCSSLMEMORY_STATUS_OK ^ (uint32_t)MCUXCSSLMEMORY_STATUS_FAULT; + uint32_t word = 0U; + uint32_t xorword = 0U; + uint32_t byte = 0U; + uint32_t cha = nwords; + uint32_t chb = 0xFFFFFFFFU; + uint32_t datareg = 0U; + + MCUX_CSSL_SC_ADD(word); // -> should be 0 + MCUX_CSSL_SC_ADD(xorword); // -> should be 0 + MCUX_CSSL_SC_SUB(2U * nwords); // -> corresponds to `~(cha ^ chb) + word` after the below assembly has executed + // The following value is essentially a precalculation of the function xorchain(n) = 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ ... ^ n (a chain of XOR operations), where n is substituted by nwords. + // If n % 4 == 0, then xorchain(n) == n. + // If n % 4 == 1, then xorchain(n) == 1. + // If n % 4 == 2, then xorchain(n) == n + 1. + // If n % 4 == 3, then xorchain(n) == 0. + // The following is just a branchless way to do the case distinction. + // In the loop afterwards, this value is calculated by actually cumulatively XORing the value of the variable "word" in each loop iteration, which starts at 0 and increments up to nwords. + MCUX_CSSL_SC_SUB(nwords - (nwords % 2U) * nwords + ((nwords % 2U) ^ ((nwords % 4U) >> 1U))); // -> precalculation of xorword + MCUX_CSSL_SC_SUB(length); // -> corresponds to `byte` after the below assembly has executed + + MCUXCSSLMEMORY_COPY_ASM(word, byte, cha, chb, xorword, retval, datareg, pSrc, pDst, nwords, length, success); + + MCUX_CSSL_SC_ADD(~(cha ^ chb)); + MCUX_CSSL_SC_ADD(xorword); + MCUX_CSSL_SC_ADD(word); + MCUX_CSSL_SC_ADD(byte); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Copy, retval); +} diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c new file mode 100644 index 000000000..5386b31e6 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Internal_SecureCompare_Stub.c @@ -0,0 +1,66 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Internal_SecureCompare_Stub.c + * @brief C file that contains the stub implementation of the secure compare in C + */ + +#include +#include +#include +#include +#include +#ifdef CSSL_MEMORY_ENABLE_COMPARE +#include +#include +#endif /* CSSL_MEMORY_ENABLE_COMPARE */ +#include + + +/** + * @brief Stub comparison of the two memory regions @p lhs and @p rhs - internal use only + * + * The implementation calls mcuxCsslMemory_Compare when possible (function defined and pointers aligned) + * else a code that contains no security countermeasure inside is called. + * + */ +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Int_SecComp) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Int_SecComp +( + const uint8_t * pLhs, + const uint8_t * pRhs, + uint32_t length +) +{ +#ifdef CSSL_MEMORY_ENABLE_COMPARE + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Int_SecComp, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslMemory_Compare) + ); + + const uint32_t cpuWordSize = sizeof(uint32_t); + if ((0u == ((uint32_t) pLhs & (cpuWordSize - 1u))) && (0u == ((uint32_t) pRhs & (cpuWordSize - 1u)))) { + MCUX_CSSL_FP_FUNCTION_CALL(retval, mcuxCsslMemory_Compare(mcuxCsslParamIntegrity_Protect(3u, pLhs, pRhs, length), pLhs, pRhs, length)); + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Int_SecComp, retval); + } +#endif /* CSSL_MEMORY_ENABLE_COMPARE */ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Int_SecComp); + + mcuxCsslMemory_Status_t retval = MCUXCSSLMEMORY_STATUS_EQUAL; + for (uint32_t i = 0u; i < length; ++i) { + if (pLhs[i] != pRhs[i]) { + retval = MCUXCSSLMEMORY_STATUS_NOT_EQUAL; + } + } + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Int_SecComp, retval); +} diff --git a/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c new file mode 100644 index 000000000..88de2bf04 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslMemory/src/mcuxCsslMemory_Set.c @@ -0,0 +1,135 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2021-2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslMemory_Set.c + * @brief mcuxCsslMemory: implementation of memory set function + */ + + +#include +#include +#include +#include +#include +#include +#include + + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslMemory_Set) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslMemory_Status_t) mcuxCsslMemory_Set +( + mcuxCsslParamIntegrity_Checksum_t chk, + void * pDst, + uint8_t val, + size_t length, + size_t bufLength +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslMemory_Set, + MCUX_CSSL_FP_FUNCTION_CALLED(mcuxCsslParamIntegrity_Validate)); + + MCUX_CSSL_FP_FUNCTION_CALL(retCode_paramIntegrityValidate, mcuxCsslParamIntegrity_Validate(chk, 4u, pDst, val, length, bufLength)); + + if (MCUXCSSLPARAMINTEGRITY_CHECK_VALID != retCode_paramIntegrityValidate) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_FAULT); + } + + if ((NULL == pDst) || (0u == length)) + { + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_INVALID_PARAMETER); + } + + size_t copyLen = bufLength < length ? bufLength : length; + uint32_t remainLength = (uint32_t) copyLen; + uint32_t wordVal = ((uint32_t)val << 24) | ((uint32_t)val << 16) | ((uint32_t)val << 8) | (uint32_t)val; + const uint32_t cpuWordSize = sizeof(uint32_t); + + volatile uint8_t *p8Dst = (volatile uint8_t *) pDst; // needs to be aligned + +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_11_6 "Exception 6: casting void pointer to security counter type" +#endif + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "pDst will be in the valid range pDst[0 ~ copyLen].") + MCUX_CSSL_SC_ADD((uint32_t) pDst + copyLen); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_11_6 +#endif + + MCUX_CSSL_FP_LOOP_DECL(FirstByteLoop); + MCUX_CSSL_FP_LOOP_DECL(SecondByteLoop); + MCUX_CSSL_FP_LOOP_DECL(WordLoop); + + while ((0u != ((uint32_t) p8Dst & (cpuWordSize - 1u))) && (0u != remainLength)) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p8Dst will be in the valid range pDst[0 ~ copyLen].") + MCUX_CSSL_FP_LOOP_ITERATION(FirstByteLoop); + *p8Dst = val; + p8Dst++; + remainLength--; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_11_3 "Exception 9: re-interpreting the memory" +#endif + volatile uint32_t *p32Dst = (volatile uint32_t *) p8Dst; /* p8Dst is CPU word-aligned after the previous loop. */ +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_11_3 +#endif + while (cpuWordSize <= remainLength) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p32Dst will be in the valid range pDst[0 ~ copyLen].") + MCUX_CSSL_FP_LOOP_ITERATION(WordLoop); + *p32Dst = wordVal; + p32Dst++; + remainLength -= cpuWordSize; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + p8Dst = (volatile uint8_t *) p32Dst; + while (0u != remainLength) + { + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "p8Dst will be in the valid range pDst[0 ~ copyLen].") + MCUX_CSSL_FP_LOOP_ITERATION(SecondByteLoop); + *p8Dst = val; + p8Dst++; + remainLength--; + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) + } + + MCUX_CSSL_SC_SUB((uint32_t) p8Dst); +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_11_6 "Exception 6: casting void pointer to security counter type" +#endif + MCUX_CSSL_ANALYSIS_COVERITY_START_FALSE_POSITIVE(INTEGER_OVERFLOW, "modular arithmetic, mod 4") + MCUX_CSSL_FP_COUNTER_STMT(uint32_t noOfBytesToAlignment = ((0u - ((uint32_t) pDst)) % cpuWordSize)); + MCUX_CSSL_ANALYSIS_COVERITY_STOP_FALSE_POSITIVE(INTEGER_OVERFLOW) +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_11_6 +#endif + MCUX_CSSL_FP_COUNTER_STMT(uint32_t firstByteIteration = (copyLen > noOfBytesToAlignment) + ? noOfBytesToAlignment + : copyLen); + MCUX_CSSL_FP_COUNTER_STMT(uint32_t wordIteration = (copyLen > firstByteIteration) + ? ((copyLen - firstByteIteration) / cpuWordSize) + : 0u); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslMemory_Set, MCUXCSSLMEMORY_STATUS_OK, + MCUX_CSSL_FP_LOOP_ITERATIONS(FirstByteLoop, firstByteIteration), + MCUX_CSSL_FP_LOOP_ITERATIONS(WordLoop, wordIteration), + MCUX_CSSL_FP_LOOP_ITERATIONS(SecondByteLoop, copyLen - (wordIteration * cpuWordSize) - firstByteIteration)); +} diff --git a/components/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h b/components/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h new file mode 100644 index 000000000..40811c4fa --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslParamIntegrity/inc/mcuxCsslParamIntegrity.h @@ -0,0 +1,116 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2021 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/// @file mcuxCsslParamIntegrity.h +/// @brief Top-level include file for the parameter integrity protection mechanism +/// +/// The library exposes the following functions: +///
    +///
  1. Generation of parameter checksums: #mcuxCsslParamIntegrity_Protect +///
  2. Validation of parameter checksums: #mcuxCsslParamIntegrity_Validate +///
+ +#ifndef MCUXCSSLPARAMINTEGRITY_H +#define MCUXCSSLPARAMINTEGRITY_H + +#include +#include +#include +#include +#include + +/** + * @defgroup mcuxCsslParamIntegrity Parameter Integrity API + * @brief Functionality to ensure parameter integrity during function calls + * + * @ingroup mcuxCsslAPI + * @{ + */ + +/** + * @defgroup mcuxCsslParamIntegrity_Macros mcuxCsslParamIntegrity Macro Definitions + * @brief Macros of mcuxCsslParamIntegrity component + * @ingroup mcuxCsslParamIntegrity + * @{ + */ + +#define MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM ((mcuxCsslParamIntegrity_Checksum_t)0xb7151628u) ///< First eight hex digits of Eulers number + +#define MCUXCSSLPARAMINTEGRITY_CHECK_VALID ((mcuxCsslParamIntegrity_Checksum_t)0x6969u) ///< Return value of #mcuxCsslParamIntegrity_Validate if the parameter checksum was correct + +#define MCUXCSSLPARAMINTEGRITY_CHECK_INVALID ((mcuxCsslParamIntegrity_Checksum_t)0x9696u) ///< Return value of #mcuxCsslParamIntegrity_Validate if the parameter checksum was incorrect + +/** + * @} + */ + +/** + * @defgroup mcuxCsslParamIntegrity_Types mcuxCsslParamIntegrity Type Definitions + * @brief Types of mcuxCsslParamIntegrity component + * @ingroup mcuxCsslParamIntegrity + * @{ + */ + +/** +* @brief Build time assertion to ensure CPU word size of 32 bit +*/ +typedef void * mcuxCsslParamIntegrity_AssertionCpuWordSize_t[(4u == sizeof(size_t)) ? (+1) : (-1)]; + +/** +* @brief Type of a parameter checksum. +*/ +typedef uint32_t mcuxCsslParamIntegrity_Checksum_t; + +/** + * @} + */ + +/** + * @defgroup mcuxCsslParamIntegrity_Functions mcuxCsslParamIntegrity Function Definitions + * @brief Functions of mcuxCsslParamIntegrity component + * @ingroup mcuxCsslParamIntegrity + * @{ + */ + +/** + * @brief Calculates a parameter checksum. + * + * @param nargs The number of parameters to be protected. + * @param ... The parameters that should be protected. Note that parameters bigger than a single machine word are not supported. + * @return checksum over the input parameters to be protected + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Protect) +mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect(size_t nargs, ...); + +/** + * @brief Verifies the correctness of a parameter checksum. + * + * @param chk The parameter checksum. + * @param nargs The number of parameters to be protected. + * @param ... The parameters that were used to calculate the parameter checksum. Note that parameters bigger than a single machine word are not supported. + * @return A status code encapsulated in a flow-protection type. + * @retval #MCUXCSSLPARAMINTEGRITY_CHECK_VALID The parameter checksum was correct. + * @retval #MCUXCSSLPARAMINTEGRITY_CHECK_INVALID The parameter checksum was incorrect. + */ +MCUX_CSSL_FP_FUNCTION_DECL(mcuxCsslParamIntegrity_Validate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslParamIntegrity_Checksum_t) mcuxCsslParamIntegrity_Validate(mcuxCsslParamIntegrity_Checksum_t chk, size_t nargs, ...); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/components/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c b/components/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c new file mode 100644 index 000000000..52e82b275 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslParamIntegrity/src/mcuxCsslParamIntegrity.c @@ -0,0 +1,99 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include + +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_17_1 "Usage of stdarg.h feature has been analyzed and approved, compiler error has been added for exceptions (when CPU word size > 32 bit)" +#endif + +MCUX_CSSL_FP_FUNCTION_DEF(rotate_right) +static uint32_t rotate_right(uint32_t val, uint32_t shift_amt) { + MCUX_CSSL_ANALYSIS_START_SUPPRESS_INTEGER_OVERFLOW("shift_amt will be always less than 32.") + return ((val) >> (shift_amt) % 32u) | ((val) << (32u - (shift_amt)) % 32u); + MCUX_CSSL_ANALYSIS_STOP_SUPPRESS_INTEGER_OVERFLOW() +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_InternalProtect) +static mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_InternalProtect(size_t nargs, va_list args) { + mcuxCsslParamIntegrity_Checksum_t result = MCUXCSSLPARAMINTEGRITY_BASE_CHECKSUM; + for(size_t i = 0; i < nargs; i++) { +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_10_1 "This is third party code. va_arg macro from stdarg.h contains two violations to MISRA rule 10.1" +#pragma coverity compliance block deviate MISRA_C_2012_Rule_10_4 "This is third party code. va_arg macro from stdarg.h contains two violations to MISRA rule 10.4" +#pragma coverity compliance block deviate MISRA_C_2012_Rule_20_7 "This is third party code. va_arg macro from stdarg.h contains a violation to MISRA rule 20.7" +#endif + result += rotate_right(va_arg(args, uint32_t), i); +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_10_1 +#pragma coverity compliance end_block MISRA_C_2012_Rule_10_4 +#pragma coverity compliance end_block MISRA_C_2012_Rule_20_7 +#endif + } + return result; +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_Protect) +mcuxCsslParamIntegrity_Checksum_t mcuxCsslParamIntegrity_Protect +( + size_t nargs, + ... +) +{ + va_list args; +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_20_7 "This is third party code. va_start macro from stdarg.h contains a violation to MISRA rule 20.7" +#endif + va_start(args, nargs); +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_20_7 +#endif + mcuxCsslParamIntegrity_Checksum_t result = mcuxCsslParamIntegrity_InternalProtect(nargs, args); + va_end(args); + return result; +} + +MCUX_CSSL_FP_FUNCTION_DEF(mcuxCsslParamIntegrity_Validate) +MCUX_CSSL_FP_PROTECTED_TYPE(mcuxCsslParamIntegrity_Checksum_t) mcuxCsslParamIntegrity_Validate +( + mcuxCsslParamIntegrity_Checksum_t chk, + size_t nargs, + ... +) +{ + MCUX_CSSL_FP_FUNCTION_ENTRY(mcuxCsslParamIntegrity_Validate); + + va_list args; +#ifdef __COVERITY__ +#pragma coverity compliance block deviate MISRA_C_2012_Rule_20_7 "This is third party code. va_start macro from stdarg.h contains a violation to MISRA rule 20.7" +#endif + va_start(args, nargs); +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_20_7 +#endif + mcuxCsslParamIntegrity_Checksum_t recalculatedChecksum = mcuxCsslParamIntegrity_InternalProtect(nargs, args); + va_end(args); + + MCUX_CSSL_FP_FUNCTION_EXIT(mcuxCsslParamIntegrity_Validate, + (recalculatedChecksum == chk) ? MCUXCSSLPARAMINTEGRITY_CHECK_VALID : MCUXCSSLPARAMINTEGRITY_CHECK_INVALID + ); +} + +#ifdef __COVERITY__ +#pragma coverity compliance end_block MISRA_C_2012_Rule_17_1 +#endif diff --git a/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h new file mode 100644 index 000000000..6d39e35e4 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter.h @@ -0,0 +1,304 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * @file mcuxCsslSecureCounter.h + * @brief Provides the API for the CSSL secure counter mechanism. + */ + +#ifndef MCUXCSSLSECURECOUNTER_H_ +#define MCUXCSSLSECURECOUNTER_H_ + +/* Include the actual implementation of the secure counter mechanism. */ +#include + +/** + * @addtogroup mcuxCsslAPI MCUX CSSL -- API + * + * @defgroup mcuxCsslSecureCounter Secure Counter API + * @brief Secure counter mechanism. + * @ingroup mcuxCsslAPI + */ + + +/** + * @defgroup scCore Secure counter core functionality + * @brief Secure counter handling core functionality. + * @ingroup mcuxCsslSecureCounter + * + * @todo Extend this description of the core functionality. + */ + +/****************************************************************************/ +/* Constants */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_SC_CHECK_PASSED + * @brief Positive comparison result value. + * @api + * @ingroup scCore + */ +#define MCUX_CSSL_SC_CHECK_PASSED \ + MCUX_CSSL_SC_CHECK_PASSED_IMPL + +/** + * @def MCUX_CSSL_SC_CHECK_FAILED + * @brief Negative comparison result value. + * @api + * @ingroup scCore + */ +#define MCUX_CSSL_SC_CHECK_FAILED \ + MCUX_CSSL_SC_CHECK_FAILED_IMPL + +/** + * @def MCUX_CSSL_SC_VALUE_TYPE + * @brief Data type used for the secure counter values. + * @api + * @ingroup scCore + */ +#define MCUX_CSSL_SC_VALUE_TYPE \ + MCUX_CSSL_SC_VALUE_TYPE_IMPL + +/****************************************************************************/ +/* Initialization */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_SC_ALLOC + * @brief Allocation operation for the secure counter. + * @api + * @ingroup scCore + */ +#define MCUX_CSSL_SC_ALLOC() \ + MCUX_CSSL_SC_ALLOC_IMPL() + +/** + * @def MCUX_CSSL_SC_INIT + * @brief Initialization operation for the secure counter. + * @api + * @ingroup scCore + * + * @param value Value with which the secure counter must be initialized. + */ +#define MCUX_CSSL_SC_INIT(value) \ + MCUX_CSSL_SC_INIT_IMPL(value) + +/****************************************************************************/ +/* Check */ +/****************************************************************************/ + +/** + * @def MCUX_CSSL_SC_CHECK + * @brief Comparison operation for the secure counter. + * @api + * @ingroup scCore + * + * @param reference Reference value to compare the secure counter value against. + * @return Either #MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or + * #MCUX_CSSL_SC_CHECK_FAILED if the value is different. + */ +#define MCUX_CSSL_SC_CHECK(reference) \ + MCUX_CSSL_SC_CHECK_IMPL(reference) + +/****************************************************************************/ +/* Counter increment */ +/****************************************************************************/ +/** + * @defgroup scInc Secure counter increment + * @brief Support for incrementing the secure counter. + * @ingroup mcuxCsslSecureCounter + */ + +/** + * @def MCUX_CSSL_SC_ADD + * @brief Increment the secure counter with @p value. + * @api + * @ingroup scInc + * + * @see MCUX_CSSL_SC_ADD_0x1 + * @see MCUX_CSSL_SC_ADD_0x10 + * @see MCUX_CSSL_SC_ADD_0x100 + * @see MCUX_CSSL_SC_SUB + * + * @param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD(value) \ + MCUX_CSSL_SC_ADD_IMPL(value) + +/** + * @def MCUX_CSSL_SC_ADD_ON_CALL + * @brief Increment the secure counter with @p value in case of function call. + * @api + * @ingroup scInc + * + * @see MCUX_CSSL_SC_ADD + * + * @param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD_ON_CALL(value) \ + MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) + +/** + * @def MCUX_CSSL_SC_ADD_0x1 + * @brief Increment the secure counter with 0x1. + * @api + * @ingroup scInc + * + * @see MCUX_CSSL_SC_ADD + * @see MCUX_CSSL_SC_ADD_0x10 + * @see MCUX_CSSL_SC_ADD_0x100 + * @see MCUX_CSSL_SC_SUB_0x1 + */ +#define MCUX_CSSL_SC_ADD_0x1() \ + MCUX_CSSL_SC_ADD_0x1_IMPL() + +/** + * @def MCUX_CSSL_SC_ADD_0x10 + * @brief Increment the secure counter with 0x10. + * @api + * @ingroup scInc + * + * @see MCUX_CSSL_SC_ADD + * @see MCUX_CSSL_SC_ADD_0x1 + * @see MCUX_CSSL_SC_ADD_0x100 + * @see MCUX_CSSL_SC_SUB_0x10 + */ +#define MCUX_CSSL_SC_ADD_0x10() \ + MCUX_CSSL_SC_ADD_0x10_IMPL() + +/** + * @def MCUX_CSSL_SC_ADD_0x100 + * @brief Increment the secure counter with 0x100. + * @api + * @ingroup scInc + * + * @see MCUX_CSSL_SC_ADD + * @see MCUX_CSSL_SC_ADD_0x1 + * @see MCUX_CSSL_SC_ADD_0x10 + * @see MCUX_CSSL_SC_SUB_0x100 + */ +#define MCUX_CSSL_SC_ADD_0x100() \ + MCUX_CSSL_SC_ADD_0x100_IMPL() + +/****************************************************************************/ +/* Counter decrement */ +/****************************************************************************/ +/** + * @defgroup scDec Secure counter decrement + * @brief Support for decrementing the secure counter. + * @ingroup mcuxCsslSecureCounter + */ + +/** + * @def MCUX_CSSL_SC_SUB + * @brief Decrement the secure counter with @p value. + * @api + * @ingroup scDec + * + * @see MCUX_CSSL_SC_SUB_0x1 + * @see MCUX_CSSL_SC_SUB_0x10 + * @see MCUX_CSSL_SC_SUB_0x100 + * @see MCUX_CSSL_SC_ADD + * + * @param value Value with which the secure counter must be decremented. + */ +#define MCUX_CSSL_SC_SUB(value) \ + MCUX_CSSL_SC_SUB_IMPL(value) + +/** + * @def MCUX_CSSL_SC_SUB_0x1 + * @brief Decrement the secure counter with 0x1. + * @api + * @ingroup scDec + * + * @see MCUX_CSSL_SC_SUB + * @see MCUX_CSSL_SC_SUB_0x10 + * @see MCUX_CSSL_SC_SUB_0x100 + * @see MCUX_CSSL_SC_ADD_0x1 + */ +#define MCUX_CSSL_SC_SUB_0x1() \ + MCUX_CSSL_SC_SUB_0x1_IMPL() + +/** + * @def MCUX_CSSL_SC_SUB_0x10 + * @brief Decrement the secure counter with 0x10. + * @api + * @ingroup scDec + * + * @see MCUX_CSSL_SC_SUB + * @see MCUX_CSSL_SC_SUB_0x1 + * @see MCUX_CSSL_SC_SUB_0x100 + * @see MCUX_CSSL_SC_ADD_0x10 + */ +#define MCUX_CSSL_SC_SUB_0x10() \ + MCUX_CSSL_SC_SUB_0x10_IMPL() + +/** + * @def MCUX_CSSL_SC_SUB_0x100 + * @brief Decrement the secure counter with 0x100. + * @api + * @ingroup scDec + * + * @see MCUX_CSSL_SC_SUB + * @see MCUX_CSSL_SC_SUB_0x1 + * @see MCUX_CSSL_SC_SUB_0x10 + * @see MCUX_CSSL_SC_ADD_0x100 + */ +#define MCUX_CSSL_SC_SUB_0x100() \ + MCUX_CSSL_SC_SUB_0x100_IMPL() + +/****************************************************************************/ +/* Direct access (optional) */ +/****************************************************************************/ +/** + * @defgroup scDirect Secure counter direct access + * @brief Support for directly accessing the secure counter. + * @ingroup mcuxCsslSecureCounter + * + * @warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. + */ + +/** + * @def MCUX_CSSL_SC_VALUE + * @brief Access operation for the current secure counter value. + * @api + * @ingroup scDirect + * + * @warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. For portable code it is best to only rely on + * the check operation to verify the secure counter value. + * + * @return The current value of the secure counter. + */ +#define MCUX_CSSL_SC_VALUE() \ + MCUX_CSSL_SC_VALUE_IMPL() + +/** + * @def MCUX_CSSL_SC_ASSIGN + * @brief Assignment operation for the secure counter. + * @api + * @ingroup scDirect + * + * @warning Access to the secure counter is generally restricted, and generic + * assignment might not be allowed. For portable code it is best to only rely + * on the initialization, increment and decrement operations to change the + * secure counter value. + * + * @param value Value that needs to be assigned to the secure counter. + */ +#define MCUX_CSSL_SC_ASSIGN(value) \ + MCUX_CSSL_SC_ASSIGN_IMPL(value) + +#endif /* MCUXCSSLSECURECOUNTER_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h new file mode 100644 index 000000000..d62ec41fd --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Cfg.h @@ -0,0 +1,103 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslSecureCounter_Cfg.h + * \brief Configuration of the implementation for the secure counter mechanism. + */ + +#ifndef MCUXCSSLSECURECOUNTER_CFG_H_ +#define MCUXCSSLSECURECOUNTER_CFG_H_ + +/** + * \addtogroup mcuxCsslCFG MCUX CSSL -- Configurations + * + * \defgroup mcuxCsslSecureCounter_CFG Secure Counter Configuration + * \brief Configuration options for the secure counter mechanism. + * \ingroup mcuxCsslCFG + */ + +/** + * \def MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG + * \brief If set to 1, use the hybrid secure counter mechanism implementation based on + * a SW counter stored in a local variable and the code watchdog (CDOG) HW IP block. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG 0 + +/** + * \def MCUX_CSSL_SC_USE_HW_CDOG + * \brief If set to 1, use the secure counter mechanism implementation based on + * the code watchdog (CDOG) HW IP block. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_HW_CDOG 0 + +/** + * \def MCUX_CSSL_SC_USE_HW_SCM + * \brief If set to 1, use the secure counter mechanism implementation based on + * the subsystem control module (SCM) HW IP block. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_HW_SCM 0 + +/** + * \def MCUX_CSSL_SC_USE_HW_S3SCM + * \brief If set to 1, use the secure counter mechanism implementation based on + * the subsystem control module (S3SCM) HW IP block. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_HW_S3SCM 0 + +/** + * \def MCUX_CSSL_SC_USE_SW_LOCAL + * \brief If set to 1, use the secure counter mechanism implementation based on + * a SW counter stored in a local variable. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_SW_LOCAL 1 + +/** + * \def MCUX_CSSL_SC_USE_SW_CONTEXT + * \brief If set to 1, use the secure counter mechanism implementation based on + * a SW counter stored in a context structure. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_SW_CONTEXT 0 + +/** + * \def MCUX_CSSL_SC_USE_SW_CALLBACK + * \brief If set to 1, use the secure counter mechanism implementation based on + * a SW counter pointed to through a callback function. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_SW_CALLBACK 0 + +/** + * \def MCUX_CSSL_SC_USE_SW_GLOBAL + * \brief If set to 1, use the secure counter mechanism implementation based on + * a SW counter stored in a global variable. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_SW_GLOBAL 0 + +/** + * \def MCUX_CSSL_SC_USE_NONE + * \brief If set to 1, do not use the secure counter mechanism. + * \ingroup mcuxCsslSecureCounter_CFG + */ + #define MCUX_CSSL_SC_USE_NONE 0 + +/* Basic configuration sanity check */ + +#endif /* MCUXCSSLSECURECOUNTER_CFG_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h new file mode 100644 index 000000000..745d9d414 --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_Impl.h @@ -0,0 +1,48 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslSecureCounter_Impl.h + * \brief Selection of the implementation for the secure counter mechanism. + */ + +#ifndef MCUXCSSLSECURECOUNTER_IMPL_H_ +#define MCUXCSSLSECURECOUNTER_IMPL_H_ + +/* Include the configuration for the secure counter mechanism. */ +#include + +/* Include the selected implementation of the secure counter mechanism. */ +#if defined(MCUX_CSSL_SC_USE_HW_CDOG) && (1 == MCUX_CSSL_SC_USE_HW_CDOG) +# include +#elif defined(MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG) && (1 == MCUX_CSSL_SC_USE_HYBRID_LOCAL_CDOG) +# include +#elif defined(MCUX_CSSL_SC_USE_HW_S3SCM) && (1 == MCUX_CSSL_SC_USE_HW_S3SCM) +# include +#elif defined(MCUX_CSSL_SC_USE_HW_SCM) && (1 == MCUX_CSSL_SC_USE_HW_SCM) +# include +#elif defined(MCUX_CSSL_SC_USE_SW_LOCAL) && (1 == MCUX_CSSL_SC_USE_SW_LOCAL) +# include +#elif defined(MCUX_CSSL_SC_USE_SW_CONTEXT) && (1 == MCUX_CSSL_SC_USE_SW_CONTEXT) +# include +#elif defined(MCUX_CSSL_SC_USE_SW_CALLBACK) && (1 == MCUX_CSSL_SC_USE_SW_CALLBACK) +# include +#elif defined(MCUX_CSSL_SC_USE_SW_GLOBAL) && (1 == MCUX_CSSL_SC_USE_SW_GLOBAL) +# include +#elif defined(MCUX_CSSL_SC_USE_NONE) && (1 == MCUX_CSSL_SC_USE_NONE) +# include +#else +# error "No secure counter implementation found/configured." +#endif + +#endif /* MCUXCSSLSECURECOUNTER_IMPL_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h new file mode 100644 index 000000000..a25e7481d --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_None.h @@ -0,0 +1,274 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslSecureCounter_None.h + * \brief Implementation that disables the CSSL secure counter mechanism. + */ + +#ifndef MCUXCSSLSECURECOUNTER_NONE_H_ +#define MCUXCSSLSECURECOUNTER_NONE_H_ + +/** + * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations + * + * \defgroup mcuxCsslSecureCounter_None Secure Counter: Disabled + * \brief Disable the secure counter mechanism. + * \ingroup mcuxCsslIMPL + */ + + +/** + * \defgroup scNoneCore Secure counter core functionality + * \brief Secure counter handling core functionality. + * \ingroup mcuxCsslSecureCounter_None + * + * \todo Extend this description of the core functionality. + */ + +/****************************************************************************/ +/* Constants */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_CHECK_PASSED_IMPL + * \brief Positive comparison result value. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u) + +/** + * \def MCUX_CSSL_SC_CHECK_FAILED_IMPL + * \brief Negative comparison result value. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL) + +/** + * \def MCUX_CSSL_SC_COUNTER_TYPE_IMPL + * \brief Data type used for the secure counter. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \ + uint32_t + +/** + * \def MCUX_CSSL_SC_VALUE_TYPE_IMPL + * \brief Data type used for the secure counter values. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_VALUE_TYPE_IMPL \ + static const uint32_t + +/** + * \def MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL + * \brief Data type used for properly casting the secure counter balancing values. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \ + uint32_t + +/****************************************************************************/ +/* Initialization */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_ALLOC_IMPL + * \brief Allocation operation implementation for the secure counter. + * \ingroup scNoneCore + */ +#define MCUX_CSSL_SC_ALLOC_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_INIT_IMPL + * \brief Initialization operation implementation for the secure counter. + * \ingroup scNoneCore + * + * \param value Value with which the secure counter must be initialized. + */ +#define MCUX_CSSL_SC_INIT_IMPL(value) \ + /* intentionally empty */ + +/****************************************************************************/ +/* Check */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_CHECK_IMPL + * \brief Comparison operation implementation for the secure counter. + * \ingroup scNoneCore + * + * \param reference Reference value to compare the secure counter value against. + * \return Always #MCUX_CSSL_SC_CHECK_PASSED. + */ +#define MCUX_CSSL_SC_CHECK_IMPL(value) \ + (MCUX_CSSL_SC_CHECK_PASSED_IMPL) + +/****************************************************************************/ +/* Counter increment */ +/****************************************************************************/ +/** + * \defgroup scNoneInc Secure counter increment + * \brief Support for incrementing the secure counter. + * \ingroup mcuxCsslSecureCounter_None + */ + +/** + * \def MCUX_CSSL_SC_ADD_IMPL + * \brief Increment the secure counter with \p value. + * \ingroup scNoneInc + * + * \see MCUX_CSSL_SC_SUB_IMPL + * + * \param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD_IMPL(value) \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_ADD_ON_CALL_IMPL + * \brief Increment the secure counter with \p value in case of function call. + * \ingroup scNoneInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + * + * \param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_ADD_0X1_IMPL + * \brief Increment the secure counter with 0x1. + * \ingroup scNoneInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X1_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_ADD_0X10_IMPL + * \brief Increment the secure counter with 0x10. + * \ingroup scNoneInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X10_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_ADD_0X100_IMPL + * \brief Increment the secure counter with 0x100. + * \ingroup scNoneInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X100_IMPL() \ + /* intentionally empty */ + +/****************************************************************************/ +/* Counter decrement */ +/****************************************************************************/ +/** + * \defgroup scNoneDec Secure counter decrement + * \brief Support for decrementing the secure counter. + * \ingroup mcuxCsslSecureCounter_None + */ + +/** + * \def MCUX_CSSL_SC_SUB_IMPL + * \brief Decrement the secure counter with \p value. + * \ingroup scNoneDec + * + * \see MCUX_CSSL_SC_ADD_IMPL + * + * \param value Value with which the secure counter must be decremented. + */ +#define MCUX_CSSL_SC_SUB_IMPL(value) \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_SUB_0X1_IMPL + * \brief Decrement the secure counter with 0x1. + * \ingroup scNoneDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X1_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_SUB_0X10_IMPL + * \brief Decrement the secure counter with 0x10. + * \ingroup scNoneDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X10_IMPL() \ + /* intentionally empty */ + +/** + * \def MCUX_CSSL_SC_SUB_0X100_IMPL + * \brief Decrement the secure counter with 0x100. + * \ingroup scNoneDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X100_IMPL() \ + /* intentionally empty */ + +/****************************************************************************/ +/* Direct access (optional) */ +/****************************************************************************/ +/** + * \defgroup scNoneDirect Secure counter direct access + * \brief Support for directly accessing the secure counter. + * \ingroup mcuxCsslSecureCounter_None + * + * \warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. + */ + +/** + * \def MCUX_CSSL_SC_VALUE_IMPL + * \brief Access operation for the current secure counter value. + * \ingroup scNoneDirect + * + * \warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. For portable code it is best to only rely on + * the check operation to verify the secure counter value. + * + * \return The current value of the secure counter. + */ +#define MCUX_CSSL_SC_VALUE_IMPL() \ + 1/0 /* not supported */ + +/** + * \def MCUX_CSSL_SC_ASSIGN_IMPL + * \brief Assignment operation for the secure counter. + * \ingroup scNoneDirect + * + * \warning Access to the secure counter is generally restricted, and generic + * assignment might not be allowed. For portable code it is best to only rely + * on the initialization, increment and decrement operations to change the + * secure counter value. + * + * \param value Value that needs to be assigned to the secure counter. + */ +#define MCUX_CSSL_SC_ASSIGN_IMPL(value) \ + /* intentionally empty */ + + +#endif /* MCUXCSSLSECURECOUNTER_NONE_H_ */ diff --git a/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h new file mode 100644 index 000000000..a8cbb361c --- /dev/null +++ b/components/els_pkc/src/comps/mcuxCsslSecureCounter/inc/mcuxCsslSecureCounter_SW_Local.h @@ -0,0 +1,293 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** + * \file mcuxCsslSecureCounter_SW_Local.h + * \brief SW implementation of the CSSL secure counter mechanism (using a local + * variable). + */ + +#ifndef MCUXCSSLSECURECOUNTER_SW_LOCAL_H_ +#define MCUXCSSLSECURECOUNTER_SW_LOCAL_H_ + +/** + * \addtogroup mcuxCsslIMPL MCUX CSSL -- Implementations + * + * \defgroup mcuxCsslSecureCounter_SwLocal Secure Counter: SW Local + * \brief Secure counter mechanism implementation using a local variable. + * \ingroup mcuxCsslIMPL + */ + + +/** + * \defgroup scSwlCore Secure counter core functionality + * \brief Secure counter handling core functionality. + * \ingroup mcuxCsslSecureCounter_SwLocal + * + * \todo Extend this description of the core functionality. + */ + +/** + * \def MCUX_CSSL_SC_COUNTER_NAME + * \brief Variable name to use for storing the secure counter value. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_COUNTER_NAME \ + mcuxCsslSecureCounter + +/****************************************************************************/ +/* Constants */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_CHECK_PASSED_IMPL + * \brief Positive comparison result value. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_CHECK_PASSED_IMPL (0xA5A5A5A5u) + +/** + * \def MCUX_CSSL_SC_CHECK_FAILED_IMPL + * \brief Negative comparison result value. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_CHECK_FAILED_IMPL (~ MCUX_CSSL_SC_CHECK_PASSED_IMPL) + +/** + * \def MCUX_CSSL_SC_COUNTER_TYPE_IMPL + * \brief Data type used for the secure counter. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_COUNTER_TYPE_IMPL \ + uint32_t + +/** + * \def MCUX_CSSL_SC_VALUE_TYPE_IMPL + * \brief Data type used for the secure counter values. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_VALUE_TYPE_IMPL \ + static const uint32_t + +/** + * \def MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL + * \brief Data type used for properly casting the secure counter balancing values. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL \ + uint32_t + +/****************************************************************************/ +/* Initialization */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_ALLOC_IMPL + * \brief Allocation operation implementation for the secure counter. + * \ingroup scSwlCore + */ +#define MCUX_CSSL_SC_ALLOC_IMPL() \ + MCUX_CSSL_SC_COUNTER_TYPE_IMPL MCUX_CSSL_SC_COUNTER_NAME + +/** + * \def MCUX_CSSL_SC_INIT_IMPL + * \brief Initialization operation implementation for the secure counter. + * \ingroup scSwlCore + * + * \param value Value with which the secure counter must be initialized. + */ +#define MCUX_CSSL_SC_INIT_IMPL(value) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_SC_ALLOC_IMPL() = ((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/****************************************************************************/ +/* Check */ +/****************************************************************************/ + +/** + * \def MCUX_CSSL_SC_CHECK_IMPL + * \brief Comparison operation implementation for the secure counter. + * \ingroup scSwlCore + * + * \param value Reference value to compare the secure counter value against. + * \return Either #MCUX_CSSL_SC_CHECK_PASSED, if the value matches, or + * #MCUX_CSSL_SC_CHECK_FAILED if the value is different. + */ +#define MCUX_CSSL_SC_CHECK_IMPL(value) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + (MCUX_CSSL_SC_CHECK_FAILED_IMPL ^ (MCUX_CSSL_SC_COUNTER_NAME - (((MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value)) + 1u))) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/****************************************************************************/ +/* Counter increment */ +/****************************************************************************/ +/** + * \defgroup scSwlInc Secure counter increment + * \brief Support for incrementing the secure counter. + * \ingroup mcuxCsslSecureCounter_SwLocal + */ + +/** + * \def MCUX_CSSL_SC_ADD_IMPL + * \brief Increment the secure counter with \p value. + * \ingroup scSwlInc + * + * \see MCUX_CSSL_SC_SUB_IMPL + * + * \param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD_IMPL(value) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_SC_COUNTER_NAME += (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/** + * \def MCUX_CSSL_SC_ADD_ON_CALL_IMPL + * \brief Increment the secure counter with \p value in case of function call. + * \ingroup scSwlInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + * + * \param value Value with which the secure counter must be incremented. + */ +#define MCUX_CSSL_SC_ADD_ON_CALL_IMPL(value) \ + MCUX_CSSL_SC_ADD_IMPL(value) + +/** + * \def MCUX_CSSL_SC_ADD_0X1_IMPL + * \brief Increment the secure counter with 0x1. + * \ingroup scSwlInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X1_IMPL() \ + MCUX_CSSL_SC_ADD_IMPL(0x1u) + +/** + * \def MCUX_CSSL_SC_ADD_0X10_IMPL + * \brief Increment the secure counter with 0x10. + * \ingroup scSwlInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X10_IMPL() \ + MCUX_CSSL_SC_ADD_IMPL(0x10u) + +/** + * \def MCUX_CSSL_SC_ADD_0X100_IMPL + * \brief Increment the secure counter with 0x100. + * \ingroup scSwlInc + * + * \see MCUX_CSSL_SC_ADD_IMPL + */ +#define MCUX_CSSL_SC_ADD_0X100_IMPL() \ + MCUX_CSSL_SC_ADD_IMPL(0x100u) + +/****************************************************************************/ +/* Counter decrement */ +/****************************************************************************/ +/** + * \defgroup scSwlDec Secure counter decrement + * \brief Support for decrementing the secure counter. + * \ingroup mcuxCsslSecureCounter_SwLocal + */ + +/** + * \def MCUX_CSSL_SC_SUB_IMPL + * \brief Decrement the secure counter with \p value. + * \ingroup scSwlDec + * + * \see MCUX_CSSL_SC_ADD_IMPL + * + * \param value Value with which the secure counter must be decremented. + */ +#define MCUX_CSSL_SC_SUB_IMPL(value) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_SC_COUNTER_NAME -= (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +/** + * \def MCUX_CSSL_SC_SUB_0X1_IMPL + * \brief Decrement the secure counter with 0x1. + * \ingroup scSwlDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X1_IMPL() \ + MCUX_CSSL_SC_SUB_IMPL(0x1u) + +/** + * \def MCUX_CSSL_SC_SUB_0X10_IMPL + * \brief Decrement the secure counter with 0x10. + * \ingroup scSwlDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X10_IMPL() \ + MCUX_CSSL_SC_SUB_IMPL(0x10u) + +/** + * \def MCUX_CSSL_SC_SUB_0X100_IMPL + * \brief Decrement the secure counter with 0x100. + * \ingroup scSwlDec + * + * \see MCUX_CSSL_SC_SUB_IMPL + */ +#define MCUX_CSSL_SC_SUB_0X100_IMPL() \ + MCUX_CSSL_SC_SUB_IMPL(0x100u) + +/****************************************************************************/ +/* Direct access (optional) */ +/****************************************************************************/ +/** + * \defgroup scSwlDirect Secure counter direct access + * \brief Support for directly accessing the secure counter. + * \ingroup mcuxCsslSecureCounter_SwLocal + * + * \warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. + */ + +/** + * \def MCUX_CSSL_SC_VALUE_IMPL + * \brief Access operation for the current secure counter value. + * \ingroup scSwlDirect + * + * \warning Access to the secure counter is generally restricted, and generic + * access might not be allowed. For portable code it is best to only rely on + * the check operation to verify the secure counter value. + * + * \return The current value of the secure counter. + */ +#define MCUX_CSSL_SC_VALUE_IMPL() \ + MCUX_CSSL_SC_COUNTER_NAME + +/** + * \def MCUX_CSSL_SC_ASSIGN_IMPL + * \brief Assignment operation for the secure counter. + * \ingroup scSwlDirect + * + * \warning Access to the secure counter is generally restricted, and generic + * assignment might not be allowed. For portable code it is best to only rely + * on the initialization, increment and decrement operations to change the + * secure counter value. + * + * \param value Value that needs to be assigned to the secure counter. + */ +#define MCUX_CSSL_SC_ASSIGN_IMPL(value) \ + MCUX_CSSL_ANALYSIS_START_PATTERN_SC_INTEGER_OVERFLOW() \ + MCUX_CSSL_SC_COUNTER_NAME = (MCUX_CSSL_SC_BALANCING_VALUE_TYPE_IMPL) (value) \ + MCUX_CSSL_ANALYSIS_STOP_PATTERN_SC_INTEGER_OVERFLOW() + +#endif /* MCUXCSSLSECURECOUNTER_SW_LOCAL_H_ */ diff --git a/components/els_pkc/src/inc/impl/mcuxCl_clns_impl.h b/components/els_pkc/src/inc/impl/mcuxCl_clns_impl.h new file mode 100644 index 000000000..995d09316 --- /dev/null +++ b/components/els_pkc/src/inc/impl/mcuxCl_clns_impl.h @@ -0,0 +1,31 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020, 2022 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file impl/mcuxCl_clns_impl.h + * @brief Implementation header for component-independent CLNS functionality. */ + +#ifndef MCUXCL_CLNS_IMPL_H_ +#define MCUXCL_CLNS_IMPL_H_ + +#include // Exported features flags header + +MCUXCL_API char const* mcuxCl_GetVersion( + void) +{ +#ifndef MCUXCL_VERSION +#error "Missing definition of MCUXCL_VERSION" +#endif /* ndef MCUXCL_VERSION */ + return MCUXCL_VERSION; +} + +#endif /* MCUXCL_CLNS_IMPL_H_ */ diff --git a/components/els_pkc/src/inc/mcuxCl_clns.h b/components/els_pkc/src/inc/mcuxCl_clns.h new file mode 100644 index 000000000..eb233e1c2 --- /dev/null +++ b/components/els_pkc/src/inc/mcuxCl_clns.h @@ -0,0 +1,47 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file mcuxCl_clns.h + * @brief CLNS header for component-independent functionality */ + +#ifndef MCUXCL_CLNS_H_ +#define MCUXCL_CLNS_H_ + +#include // Exported features flags header + +/** @def MCUXCL_API + * @brief Marks a function as a public API function of the CLNS */ + +#define MCUXCL_API static inline + +/********************************************** + * CONSTANTS + **********************************************/ + +#define MCUXCL_VERSION_MAX_SIZE ((size_t) 16U) ///< Maximum size of the CLNS version string, in bytes (including zero-terminator) + +#define MCUXCL_VERSION "SDK_1.7.0" ///< String literal for the version string of CLNS release that this header is part of + +/********************************************** + * FUNCTIONS + **********************************************/ + +/** Gets the CLNS version string that uniquely identifies this release of the CLNS. */ +/** + * @return Zero-terminated ASCII string that identifies this release of the CLNS. + * Maximum size in bytes (including zero-terminator) is #MCUXCL_VERSION_MAX_SIZE. */ +MCUXCL_API char const* mcuxCl_GetVersion( + void); + +#include // Implementation header +#endif /* MCUXCL_CLNS_H_ */ diff --git a/components/els_pkc/src/platforms/mcxn/inc/ip_css_constants.h b/components/els_pkc/src/platforms/mcxn/inc/ip_css_constants.h new file mode 100644 index 000000000..50c37a652 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/inc/ip_css_constants.h @@ -0,0 +1,52 @@ +/**********************************************************************************/ +/* Copyright 2019-2020 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may only */ +/* be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, activating */ +/* and/or otherwise using the software, you are agreeing that you have read, */ +/* and that you agree to comply with and are bound by, such license terms. */ +/* If you do not agree to be bound by the applicable license terms, then you */ +/* may not retain, install, activate or otherwise use the software. */ +/**********************************************************************************/ +/* Security Classification: Company Confidential */ +/**********************************************************************************/ + +/** + * @file ip_css_constants.h + * + * @brief Additional register count constants for ip_css. + * + * @version $Revision: $ + * @date 29. April 2021 + * + * @note Generated with csv2a_create_cmsis_cheader V1.61 + * + * @note This File is NOT CMSIS compliant. + */ + +#ifndef ip_css_CONSTANTS_H +#define ip_css_CONSTANTS_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ================================================================================ */ +/* ================ 'ip_css' register names counting ================ */ +/* ================================================================================ */ + +#define CSS_DMA_SRC_CNT 3UL +#define CSS_KIDX_CNT 3UL +#define CSS_KS_CNT 20UL +#define CSS_SHA2_DOUT_CNT 16UL + + + +#ifdef __cplusplus +} +#endif + + +#endif /* ip_css_CONSTANTS_H */ diff --git a/components/els_pkc/src/platforms/mcxn/inc/ip_css_design_configuration.h b/components/els_pkc/src/platforms/mcxn/inc/ip_css_design_configuration.h new file mode 100644 index 000000000..af8d8f497 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/inc/ip_css_design_configuration.h @@ -0,0 +1,402 @@ +#define ID_CFG_CFGNAME nva +#define SHA_512 1 +#define ID_CFG_SGI_EOS_TMP_MODS 1 +#define ID_CFG_SGI_O_IRQ_DRIVEN_FROM_SGI_INT_STATUS 0 +#define ID_CFG_SGI_ENA_DBG_MODE 0 +#define ID_CFG_ROW 1 +#define ID_CFG_CHINA 0 +#define ID_CFG_CC 0 +#define ID_CFG_SGI_AUTO_MODE 1 +#define ID_CFG_SPB_SUPPORT 0 +#define ID_CFG_SPB2 0 +#define ID_CFG_SGI_SPB_MASKING 0 +#define ID_CFG_SGI_USE_SFR_SW_MASK 0 +#define ID_CFG_SGI_SPB_EDC 0 +#define ID_CFG_SGI_SPB_EDC_WIDTH 8 +#define ID_CFG_SGI_INT_EDC_WIDTH 12 +#define ID_CFG_SGI_SPB_EDC_COMPLEXITY 1 +#define ID_CFG_SGI_SPB_MODEDC 0 +#define ID_CFG_SGI_REGBANK_CLOCK_GATER_PARITY 0 +#define ID_CFG_SGI_ALL_SFRS 0 +#define ID_CFG_SGI_AES 1 +#define ID_CFG_SGI_2_KERNEL_EDC 0 +#define ID_CFG_SGI_USE_AES_APOLLO 0 +#define ID_CFG_SGI_USE_AES_AEGIS 0 +#define ID_CFG_SGI_USE_AES_ATHENIUM 0 +#define ID_CFG_SGI_USE_AES_AYNA 0 +#define ID_CFG_SGI_AES_K128_ONLY 0 +#define ID_CFG_SGI_DES 0 +#define ID_CFG_SGI_USE_DES_DAKAR 0 +#define ID_CFG_SGI_USE_DES_DANUBE 0 +#define ID_CFG_SGI_USE_DES_DEPICTA 0 +#define ID_CFG_SGI_USE_DES_DIGI 0 +#define ID_CFG_SGI_GCM 1 +#define ID_CFG_GCM_STEP_POWER 3 +#define ID_CFG_SGI_SHA2 0 +#define ID_CFG_SGI_SHA_256_ONLY 1 +#define ID_CFG_SGI_CMAC 1 +#define ID_CFG_SGI_MOVEM 0 +#define ID_CFG_SGI_EXT_PRNG 1 +#define ID_CFG_SGI_BUS_WIDTH 32 +#define ID_CFG_SGI_NUM_DATIN 3 +#define ID_CFG_SGI_NUM_KEY 3 +#define ID_CFG_SGI_NO_FA 1 +#define ID_CFG_SGI_NO_MST 1 +#define ID_CFG_SGI_NO_KEYCHECKSUM 1 +#define ID_CFG_SGI_NO_SELFCHECK 0 +#define ID_CFG_SGI_SIMU_CLKPER 10.0 +#define ID_CFG_SGI_SYNTH_CLKPER 9.0 +#define ID_CFG_DFT_SYN 1 +//#define DEBUG 0 +#define ID_CFG_APBD_WIDTH 32 +#define ID_CFG_APBA_WIDTH 12 +#define ID_CFG_SPB_ADDITIONAL_SIGNALS 1 +#define ID_CFG_CRNG_MILESTONE 0 +#define ID_CFG_CRNG_VER_X 1 +#define ID_CFG_CRNG_VER_Y1 0 +#define ID_CFG_CRNG_VER_Y2 2 +#define ID_CFG_CRNG_VER_Z 0 +#define ID_CFG_CRNG_USE_GLOBAL 0 +#define ID_CFG_CRNG_USE_PRNG_SCA 1 +#define ID_CFG_CRNG_USE_PRNG 1 +#define ID_CFG_CRNG_USE_RHC 0 +#define ID_CFG_CRNG_USE_DRBG 0 +#define ID_CFG_CRNG_USE_DTRNG 0 +#define ID_CFG_CRNG_USE_INT 0 +#define ID_CFG_CRNG_USE_ACC_ERR 0 +#define ID_CFG_CRNG_USE_SOFT_RST 0 +#define ID_CFG_CRNG_PRNG_SCA_RND_OUT_WIDTH 216 +#define ID_CFG_CRNG_PRNG_SCA_INIT_DELAY 25 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_WIDTH 8 +#define ID_CFG_CRNG_PRNG_SCA_RESEED_COUNT_WIDTH 16 +#define ID_CFG_CRNG_PRNG_SCA_RESEED_COUNT_VAL 65535 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_EXTERNAL 0 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_PRNG_SCA 1 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_PRNG 0 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_DRBG 0 +#define ID_CFG_CRNG_PRNG_SCA_HW_FEED_DTRNG 0 +#define ID_CFG_CRNG_PRNG_INIT_DELAY 5 +#define ID_CFG_CRNG_PRNG_RESEED_COUNT_WIDTH 16 +#define ID_CFG_CRNG_PRNG_RESEED_COUNT_VAL 65535 +#define ID_CFG_CRNG_PRNG_SW_READOUT 1 +#define ID_CFG_CRNG_PRNG_HW_FEED_OUT 0 +#define ID_CFG_CRNG_PRNG_SW_READOUT_WIDTH 32 +#define ID_CFG_CRNG_PRNG_SW_READOUT_TOP 1 +#define ID_CFG_CRNG_PRNG_HW_FEED_OUT_CONSUMERS 2 +#define ID_CFG_CRNG_PRNG_HW_FEED_OUT_WIDTH 8 +#define ID_CFG_CRNG_DEFINE_CDC 0 +#define ID_CFG_RTN_NUM 2 +#define ID_CFG_PRN_NUM 2 +#define ID_CFG_GPK_NUM 16 +#define ID_CFG_KEYSTORE_CHK_HWO_KEY_SLOT 1 +#define ID_CFG_KEYSTORE_USG_POS 11 +#define ID_CFG_KEYSTORE_UKPUK_POS 11 +#define ID_CFG_KEYSTORE_UTECDH_POS 12 +#define ID_CFG_KEYSTORE_UCMAC_POS 13 +#define ID_CFG_KEYSTORE_UKSK_POS 14 +#define ID_CFG_KEYSTORE_URTF_POS 15 +#define ID_CFG_KEYSTORE_UCKDF_POS 16 +#define ID_CFG_KEYSTORE_UHKDF_POS 17 +#define ID_CFG_KEYSTORE_UECSG_POS 18 +#define ID_CFG_KEYSTORE_UECDH_POS 19 +#define ID_CFG_KEYSTORE_UAES_POS 20 +#define ID_CFG_KEYSTORE_UHMAC_POS 21 +#define ID_CFG_KEYSTORE_UKWK_POS 22 +#define ID_CFG_KEYSTORE_UKUOK_POS 23 +#define ID_CFG_KEYSTORE_UTLSPMS_POS 24 +#define ID_CFG_KEYSTORE_UTLSMS_POS 25 +#define ID_CFG_KEYSTORE_UKGSRC_POS 26 +#define ID_CFG_KEYSTORE_UHWO_POS 27 +#define ID_CFG_KEYSTORE_UWRPOK_POS 28 +#define ID_CFG_KEYSTORE_UDUK_POS 29 +#define ID_CFG_KEYSTORE_CMDCFG_TLS_FINAL_POS 10 +#define ID_CFG_KEYSTORE_CMDCFG_TLS_FINAL_FIN 1 +#define ID_CFG_KEYSTORE_CMDCFG_KEYIN_KFMT_POS 6 +#define ID_CFG_KEYSTORE_CMDCFG_KEYIN_KFMT_PUF 2 +#define ID_CFG_KEYSTORE_CMDCFG_KEYIN_KFMT_UDF 0 +#define ID_CFG_KEYSTORE_CMDCFG_KEYIN_KFMT_RFC 1 +#define ID_CFG_KEYSTORE_CMDCFG_KEYIN_KFMT_PBK 3 +#define ID_CFG_KEYSTORE_CMD_KEYGEN_KGSIGN 0 +#define ID_CFG_KEYSTORE_CMD_KEYGEN_KGTYPEDH 1 +#define ID_CFG_KEYSTORE_CMD_KEYGEN_KGSRC 2 +#define ID_CFG_KEYSTORE_CMD_ECSIGN_CFG_ECHASHCHL 0 +#define ID_CFG_KEYSTORE_CMD_ECSIGN_CFG_SIGNRTF 1 +#define ID_CFG_KEYSTORE_CMDCFG_EXTKEY 13 +#define ID_CFG_SYNTH_CLKPER 7.273 +#define IP_CFG_CSS_KS 1 +#define ID_CFG_SPB_MASKING 1 +#define ID_CFG_USE_SFR_SW_MASK 0 +#define ID_CFG_SPB_EDC 0 +#define ID_CFG_SPB_EDC_WIDTH 8 +#define ID_CFG_SPB_EDC_COMPLEXITY 1 +#define ID_CFG_SPB_MODEDC 0 +#define ID_CFG_CSS_USE_SEMAPHORE 1 +#define ID_CFG_CSS_MST_ID_WIDTH 5 +#define ID_CFG_CSS_PBK_IMPORT 1 +#define ID_CFG_CSS_ASSETPROT_PORT 1 +#define ID_CFG_CSS_CMD_CIPHER 0 +#define ID_CFG_CSS_CMD_AUTH_CIPHER 1 +#define ID_CFG_CSS_CMD_RFU_0 2 +#define ID_CFG_CSS_CMD_CHAL_RESP_GEN 3 +#define ID_CFG_CSS_CMD_ECSIGN 4 +#define ID_CFG_CSS_CMD_ECVFY 5 +#define ID_CFG_CSS_CMD_ECKXH 6 +#define ID_CFG_CSS_CMD_RFU_2 7 +#define ID_CFG_CSS_CMD_KEYGEN 8 +#define ID_CFG_CSS_CMD_KEYIN 9 +#define ID_CFG_CSS_CMD_KEYOUT 10 +#define ID_CFG_CSS_CMD_KDELETE 11 +#define ID_CFG_CSS_CMD_KEYPROV 12 +#define ID_CFG_CSS_CMD_RFU_4 13 +#define ID_CFG_CSS_CMD_RFU_5 14 +#define ID_CFG_CSS_CMD_RFU_6 15 +#define ID_CFG_CSS_CMD_CKDF 16 +#define ID_CFG_CSS_CMD_HKDF 17 +#define ID_CFG_CSS_CMD_TLS 18 +#define ID_CFG_CSS_CMD_RFU_7 19 +#define ID_CFG_CSS_CMD_HASH 20 +#define ID_CFG_CSS_CMD_HMAC 21 +#define ID_CFG_CSS_CMD_CMAC 22 +#define ID_CFG_CSS_CMD_RFU_9 23 +#define ID_CFG_CSS_CMD_RND_REQ 24 +#define ID_CFG_CSS_CMD_DRBG_TEST 25 +#define ID_CFG_CSS_CMD_DTRNG_PRVL_CFG_LOAD 26 +#define ID_CFG_CSS_CMD_RFU_12 27 +#define ID_CFG_CSS_CMD_DTRNG_CFG_LOAD 28 +#define ID_CFG_CSS_CMD_DTRNG_EVAL 29 +#define ID_CFG_CSS_CMD_GDET_CFG_LOAD 30 +#define ID_CFG_CSS_CMD_GDET_TRIM 31 +#define ID_CFG_CSS_CMD_EEM_GDET_WR 16 +#define ID_CFG_CSS_CMD_EEM_GDET_RD 17 +#define ID_CFG_CSS_CMD_CIPHER_DCRYPT 1 +#define ID_CFG_CSS_CMD_CIPHER_CPHMDE0 2 +#define ID_CFG_CSS_CMD_CIPHER_CPHMDE1 3 +#define ID_CFG_CSS_CMD_CIPHER_CPHSOE 4 +#define ID_CFG_CSS_CMD_CIPHER_CPHSIE 5 +#define ID_CFG_CSS_CMD_CIPHER_EXTKEY 13 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_DCRYPT 1 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_ACPMOD0 2 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_ACPMOD1 3 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_CPHSIE 5 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW0 6 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW1 7 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW2 8 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_MSGENDW3 9 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_LASTINIT 10 +#define ID_CFG_CSS_CMD_AUTH_CIPHER_EXTKEY 13 +#define ID_CFG_CSS_CMD_ECSIGN_CFG_ECHASHCHL 0 +#define ID_CFG_CSS_CMD_ECSIGN_CFG_SIGNRTF 1 +#define ID_CFG_CSS_CMD_ECSIGN_CFG_REVF 4 +#define ID_CFG_CSS_CMD_ECVFY_CFG_ECHASHCHL 0 +#define ID_CFG_CSS_CMD_ECVFY_CFG_REVF 4 +#define ID_CFG_CSS_CMD_ECC_EXTKEY 13 +#define ID_CFG_CSS_CMD_ECKXH_REVF 4 +#define ID_CFG_CSS_CMD_KEYGEN_KGSIGN 0 +#define ID_CFG_CSS_CMD_KEYGEN_KGTYPEDH 1 +#define ID_CFG_CSS_CMD_KEYGEN_KGSRC 2 +#define ID_CFG_CSS_CMD_KEYGEN_SKIP_PBK 3 +#define ID_CFG_CSS_CMD_KEYGEN_REVF 4 +#define ID_CFG_CSS_CMD_KEYGEN_KGSIGN_RND 5 +#define ID_CFG_CSS_CMD_KEYIN_KFMT0 6 +#define ID_CFG_CSS_CMD_KEYIN_KFMT1 7 +#define ID_CFG_CSS_CMD_KEYIN_REVF 4 +#define ID_CFG_CSS_CMD_KEYPROV_ICEN 0 +#define ID_CFG_CSS_CMD_KEYPROV_DUK_UPDATE 1 +#define ID_CFG_CSS_CMD_CKDF_CKDF_ALGO0 12 +#define ID_CFG_CSS_CMD_CKDF_CKDF_ALGO1 13 +#define ID_CFG_CSS_CMD_HKDF_RTFDRVDAT 0 +#define ID_CFG_CSS_CMD_HKDF_HKDF_ALGO 1 +#define ID_CFG_CSS_CMD_HKDF_SINGLE_STEP 2 +#define ID_CFG_CSS_CMD_TLS_FINALIZE 10 +#define ID_CFG_CSS_CMD_HASH_HASHINI 2 +#define ID_CFG_CSS_CMD_HASH_HASHLD 3 +#define ID_CFG_CSS_CMD_HASH_HASHMD0 4 +#define ID_CFG_CSS_CMD_HASH_HASHMD1 5 +#define ID_CFG_CSS_CMD_HASH_HASHOE 6 +#define ID_CFG_CSS_CMD_HASH_RTFUPD 7 +#define ID_CFG_CSS_CMD_HASH_RTFOE 8 +#define ID_CFG_CSS_CMD_HMAC_EXTKEY 13 +#define ID_CFG_CSS_CMD_CMAC_INIT 0 +#define ID_CFG_CSS_CMD_CMAC_FINALIZE 1 +#define ID_CFG_CSS_CMD_CMAC_SOE 2 +#define ID_CFG_CSS_CMD_CMAC_SIE 3 +#define ID_CFG_CSS_CMD_CMAC_EXTKEY 13 +#define ID_CFG_CSS_CMD_RND_REQ_LOW_ENT_INIT 0 +#define ID_CFG_CSS_CMD_RND_REQ_RND_RAW 1 +#define ID_CFG_CSS_CMD_DRBG_TEST_MODE0 0 +#define ID_CFG_CSS_CMD_DRBG_TEST_MODE1 1 +#define ID_CFG_CSS_SGI 1 +#define ID_CFG_CSS_CRNG 1 +#define ID_CFG_CSS_SHA2 1 +#define ID_CFG_CSS_ECDSA 1 +#define ID_CFG_CSS_UDF 1 +#define ID_CFG_CSS_GDET 0 +#define ID_CFG_CSS_PRNG 1 +#define ID_CFG_CSS_KEYSTORE 1 +#define CSS_CNTRL__ADD_SHIFT 0 +#define ID_CFG_CSS_CHAL_RESP 0 +#define ID_CFG_DTRNG_FAST_CFG 1 +#define ID_CFG_CSS_DTRNG_SIMU_CFG 0 +#define ID_CFG_CSS_HAS_INT_KEYS 1 +#define ID_CFG_CSS_DRBG 1 +#define ID_CFG_CSS_CIPHER 1 +#define ID_CFG_CSS_AUTH_CIPHER 1 +#define ID_CFG_CSS_ECSIGN 1 +#define ID_CFG_CSS_ECVFY 1 +#define ID_CFG_CSS_ECKXCH 1 +#define ID_CFG_CSS_KEYGEN 1 +#define ID_CFG_CSS_KEYIN 1 +#define ID_CFG_CSS_KEYOUT 1 +#define ID_CFG_CSS_KDELETE 1 +#define ID_CFG_CSS_KEYPROV 1 +#define ID_CFG_CSS_CKDF 1 +#define ID_CFG_CSS_HKDF 1 +#define ID_CFG_CSS_TLS_INIT 1 +#define ID_CFG_CSS_HASH 1 +#define ID_CFG_CSS_HMAC 1 +#define ID_CFG_CSS_CMAC 1 +#define ID_CFG_CSS_RND_REQ 1 +#define ID_CFG_CSS_DRBG_TEST 1 +#define ID_CFG_CSS_DTRNG_CFG_LOAD 1 +#define ID_CFG_CSS_DTRNG_EVAL 1 +#define ID_CFG_CSS_GDET_CFG_LOAD 0 +#define ID_CFG_CSS_GDET_TRIM 0 +#define ID_CFG_CSS_CHAL_RESP_GEN 0 +#define ID_CFG_SW_VERSION 1 +#define ID_CFG_CSS_SW_VER 0x0000000000002040 // converted from 16'h2040 +#define ID_CFG_CSS_VER_X 3 +#define ID_CFG_CSS_VER_Y1 0 +#define ID_CFG_CSS_VER_Y2 4 +#define ID_CFG_CSS_VER_Z 0 +#define ID_CFG_CSS_MMU_NB_SLV 12 +#define ID_CFG_CSS_HW_EEM_KEY_WIDTH 128 +#define ID_CFG_CSS_SYNTH_CLKPER 7.5 +#define ID_CFG_CSS_SLV_SEL_WID 4 +#define ID_CFG_CSS_CSS_SELECT 0 +#define ID_CFG_CSS_DMA_SELECT 1 +#define ID_CFG_CSS_TDRND_SELECT 2 +#define ID_CFG_CSS_ECDSA_SELECT 3 +#define ID_CFG_CSS_SGI_SELECT 6 +#define ID_CFG_CSS_SHA_SELECT 4 +#define ID_CFG_CSS_UDF_SELECT 5 +#define ID_CFG_CSS_DRBG_SELECT 7 +#define ID_CFG_CSS_KEYSTORE_SELECT 8 +#define ID_CFG_CSS_CRNG_SELECT 9 +#define ID_CFG_CSS_GDET_SELECT 10 +#define ID_CFG_SPBD_WIDTH 32 +#define ID_CFG_SPBA_WIDTH 12 +#define ID_CFG_AHBD_WIDTH 32 +#define ID_CFG_AHBA_WIDTH 32 +#define ID_CFG_AHB_VIP 1 +#define ID_CFG_ECDSA_SYNTH_CLKPER 100 +#define ECDSA_LOW_POWER_SWIZZLER 1 +#define ECDSA_LADDINIT_RND_CNT 20 +#define ECDSA_SCALAR_RND_CNT 80 +#define ID_CFG_ECDSA_PKXOR 0 +#define ID_CFG_ECDSA_KEY_XCH 1 +#define ID_CFG_ECDSA_KEY_GEN 1 +#define ID_CFG_ECDSA_VERIFY 1 +#define ID_CFG_ECDSA_SIGN 1 +#define ID_CFG_ECDSA_128_BIT_MUL 1 +#define ID_CFG_ECDSA_RST_SECRETS 1 +#define IP_ECDSA_PROPS_OFF 1 +#define SHA2_SA 1 +#define SHA2_WAIT_OUT 1 +#define SHA2_SA_LITTLE_ENDIAN 1 +#define TRNG_CONFIG_CLN40ULPEF 0 +#define RNG4_RTL_BEHAVIORAL_OSC 0 +#define ID_CFG_DTRNG_SYNTH_CLKPER 1000 +#define ID_CFG_DTRNG_FAST_CONFIG 0 +#define ID_CFG_CSS_SYNTH 1 +#define ID_CFG_NO_CMODEL 1 +#define ID_CFG_ECDSA_NO_CMODEL 1 +#define ID_CFG_GDET_DEFINE_CDC 0 +#define ID_CFG_GDET_DEFINE_SCP_SPB_IF 0 +#define ID_CFG_DMA_AHB_BURST 0 +#define ID_CFG_DMA_STRM_CIRC_EN 0 +#define ID_CFG_DMA_SW_BYTE_SWAP 0 +#define ID_CFG_DMA_FA 1 +#define ID_CFG_UDF_IO_32_BIT 1 +#define ID_CFG_UDF_DFT_SYN 0 +#define ID_CFG_UDF_GTECH 1 +#define ID_CFG_UDF_OUTPUT_WIDTH 32 +#define ID_CFG_UDF_INPUT_WIDTH 32 +#define ID_CFG_UDF_INIT_CYCLES 9 +#define ID_CFG_UDF_APBA_WIDTH 12 +#define ID_CFG_UDF_APBD_WIDTH 32 +#define ID_CFG_UDF_SECURE_SCAN 1 +#define ID_CFG_UDF_MANGLED_RTL 0 +#define ID_CFG_UDF_MANGLED_WRAP 1 +#define ID_CFG_UDF_APB_WRAP 1 +#define ID_CFG_UDF_OUTPUT_IRQ 1 +#define ID_CFG_UDF_CUSTOM 1 +#define NETLIST_RELEASE 0 +#define ID_CFG_UDF_NO_CSV2A 1 +#define ID_CFG_DTRNG_CLN40ULPEF_9T 1 +#define ID_CFG_OSC_CLK_SYNTH_CLKPER 13.62 +#define ID_CFG_OSC2_CLK_SYNTH_CLKPER 17.30 +#define ID_CFG_FIXED_CLOCK 0 +#define ASM_FILE cssv2_riscv_boot.S +#define LINK_FILE link.ld +#define ID_CFG_CSS_INTERNAL_ROM 0 +#define ID_CFG_CSS_DTRNG_WRAP 1 +#define ID_CFG_CSS_UDF_NVA 1 +#define ID_CFG_CSS_APB2ROM 1 +#define ID_CFG_CSS_HAS_CMDCRC 1 +#define ID_CFG_CSS_NUM_ROM_LUTS 1 +#define ID_CFG_CSS_LUT_ROM 1 +#define ID_CFG_CSS_PUF_BEHAVIOURAL 0 +#define ID_CFG_CSS_CLKOP_SEL3 1 +#define ID_CFG_CSS_IS_NVA 1 +#define ID_CFG_CSS_ROM_SCRAMBLING 1 +#define ID_CFG_CSS_ROM_SCRAMBLER_NFR 2 +#define ID_CFG_CSS_36KB_ROM 1 +#define ID_CFG_CSS_ECDSA_ROM_SIZE 0x00000000000000000000000000000800 // converted from 32'h00000800 +#define ID_CFG_CSS_CPU_ROM_SIZE 0x00000000000000000000000000006FFC // converted from 32'h00006FFC +#define ID_CFG_CSS_RODATA_BASE_ADDR 0x00000000000000000000000000006DFC // converted from 32'h00006DFC +#define ID_CFG_CSS_TOTAL_ROM_SIZE 0x00000000000000000000000000009000 // converted from 32'h00009000 +#define ID_CFG_CSS_HW_EEM_EN 1 +#define ID_CFG_CSS_EEM_BOOT_ADDR 0x00000000000000000000000030010000 // converted from 32'h30010000 +#define ID_CFG_CSS_SFR_ACCESS_HACK 1 +#define ID_CFG_CSS_DTRNG_OSC_CLK_PERIOD 1.5 +#define ID_CFG_CSS_DTRNG_REF_CLK_PERIOD 9 +#define ID_CFG_CSS_ROM_SELECT 11 +#define ID_CFG_RISCV_MEM_SIZE 36 +#define RV32E_REGS 8 +#define ID_CFG_DMA_ENA_CRC 1 +#define ID_CFG_DMA_CRC_WIDTH 32 +#define ID_CFG_ECDSA_DH_STORE_PK 1 +#define ID_CFG_ECDSA_PKINT_DISABLE 1 +#define ID_CFG_ECDSA_USE_HQ_RND 1 +#define ID_CFG_ECDSA_USE_HASH_GEN_IRQ 1 +#define ID_CFG_ECDSA_USE_SCALAR_REQ_IRQ 1 +#define ID_CFG_ECDSA_OUTPUT_ERR 1 +#define ID_CFG_ECDSA_EXTLUT 1 +#define ID_CFG_ECDSA_EXTLUT_PHY 1 +#define ID_CFG_ECDSA_VFY_STATUS_OUT 1 +#define ID_CFG_ECDSA_SKIP_PBK 1 +#define ID_CFG_CSS_ECDSA_ROM_IMG ECDSA_LUT_ROM.v +#define ID_CFG_CSS_ATT_DATA_PTR 0x00000000000000000000000000000100 // converted from 32'h00000100 +#define ID_CFG_CSS_ATT_DATA_LEN 0x00000000000000000000000000000020 // converted from 32'h00000020 +#define ID_CFG_SHA2_DIRECT 1 +#define ID_CFG_CSS_SHA2_WAIT 1 +#define ID_CFG_SGI_TMP_CSS_MODS 1 +#define ID_CFG_SGI_AUTO_CMAC 1 +#define KERNEL_INPUT_E2E_EDC_ENABLE 0 +#define ID_CFG_SGI_USE_AES_AEGIS_HS 1 +#define ID_CFG_AEGIS_DUMMY 1 +#define ID_CFG_SGI_USE_AES_ATHENIUM_HS 0 +#define ID_CFG_AES_KEEP_KEY 1 +#define ID_CFG_SGI_INTERRUPT 1 +#define ID_CFG_SGI_NO_SC 0 +#define ID_CFG_CRNG_PRNG_SCA_PURE_LFSR_A_WIDTH 41 +#define ID_CFG_CRNG_PRNG_SCA_PURE_LFSR_B_WIDTH 52 +#define ID_CFG_CRNG_PRNG_SCA_TRICKLE_LFSR_A_WIDTH 279 +#define ID_CFG_CRNG_PRNG_SCA_TRICKLE_LFSR_B_WIDTH 329 +#define ID_CFG_RNG4_INV_CHAIN_LENGTH_INST 16 +#define ID_CFG_RNG4_WIN_INV_CHAIN_LENGTH_INST 24 +#define ID_CFG_RNG4_ENT_DLY_DEFAULT_INST 3200 +#define ID_CFG_RNG4_FREQ_CNT_MIN_DEFAULT_INST 1600 +#define ID_CFG_RNG4_FREQ_CNT_MAX_DEFAULT_INST 25600 +#define ID_CFG_CSS_PHY_ROM gf40rfnv_nxp_hrom_009216x032bw1c08_ss_pt_m7 +#define ID_CFG_CSS_PHY_ROM_MEM_FILE gf40rfnv_nxp_hrom_008192x032bw1c08_ss_pt_m7_rniobe4a.cde diff --git a/components/els_pkc/src/platforms/mcxn/inc/ip_platform.h b/components/els_pkc/src/platforms/mcxn/inc/ip_platform.h new file mode 100644 index 000000000..a0d8e4284 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/inc/ip_platform.h @@ -0,0 +1,89 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2020-2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +/** @file ip_platform.h + * @brief Include file for the IP. + * + * This includes the CMSIS for all of the functionality provided by the ELS IP and provides support for external base address linking. */ + +#ifndef IP_PLATFORM_H +#define IP_PLATFORM_H + +#include "fsl_device_registers.h" + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +// Define base address of ELS +#define ELS_SFR_BASE ELS ///< base of ELS SFRs +#define ELS_SFR_NAME(sfr) sfr ///< full name of SFR +#define ELS_SFR_PREFIX S50_ ///< sfr field name prefix + +// Define base address of PKC +#define PKC_SFR_BASE PKC0 ///< base of PKC SFRs +#define PKC_SFR_NAME(sfr) PKC_ ## sfr ///< full name of SFR +#define PKC_SFR_PREFIX PKC_PKC_ ///< sfr field name prefix +#define PKC_SFR_SUFFIX_MSK _MASK ///< sfr field name suffix for mask +#define PKC_SFR_SUFFIX_POS _SHIFT ///< sfr field name suffix for bit position + +// PKC_RAM base address is not defined in any header file +#define PKC_RAM_ADDR ((uint32_t)0x400B3000u) +#define PKC_WORD_SIZE 8u +#define PKC_RAM_SIZE ((uint32_t)0x1000u) + +// Define base address of TRNG +#define TRNG_SFR_BASE TRNG0 ///< base of TRNG SFRs +#define TRNG_SFR_NAME(sfr) sfr ///< full name of SFR +#define TRNG_SFR_PREFIX TRNG_ ///< sfr field name prefix +#define TRNG_SFR_SUFFIX_MSK _MASK ///< sfr field name suffix for mask +#define TRNG_SFR_SUFFIX_POS _SHIFT ///< sfr field name suffix for bit position + +// Define base address of SAFO +#define SAFO_SFR_BASE SM3_0 ///< base of SAFO SFRs +#define SAFO_SFR_NAME(sfr) sfr ///< full name of SFR +#define SAFO_SFR_PREFIX SM3_ ///< sfr field name prefix + +// ELS interrupt definitions +#define CSS_INTERRUPT_ERR_NUMBER ELS_ERR_IRQn +#define CSS_INTERRUPT_IRQ_NUMBER ELS_IRQn +#define CSS_INTERRUPT_BUSY_NUMBER ELS_IRQn + + +#define IP_PUF_BASE 0x5002C000UL +#define PUF_SRAM_CFG *(volatile uint32_t *) (IP_PUF_BASE + 0x300) +#define PUF_SR *(volatile uint32_t *) (IP_PUF_BASE + 0x8) +#define PUF_OR *(volatile uint32_t *) (IP_PUF_BASE + 0x4) +#define PUF_CR *(volatile uint32_t *) (IP_PUF_BASE + 0x0) +#define PUF_KEY_DEST *(volatile uint32_t *) (IP_PUF_BASE + 0x20) +#define PUF_DIR *(volatile uint32_t *) (IP_PUF_BASE + 0xA0) +#define PUF_DOR *(volatile uint32_t *) (IP_PUF_BASE + 0xA8) + +// ELS version +#define ELS_HW_VERSION_REVISION 0 +#define ELS_HW_VERSION_MINOR 4 +#define ELS_HW_VERSION_MAJOR 3 +#define ELS_HW_VERSION_FW_REVISION 0 +#define ELS_HW_VERSION_FW_MINOR 4 +#define ELS_HW_VERSION_FW_MAJOR 2 + +#ifdef NXPCL_FEATURE_ELS_LINK_BASE_ADDRESS +/* If we are supposed to determine the CSSv2 base address at link time, do not use the definitions from the platform header file + * Redefine IP_CSS as an extern pointer. + */ +#undef ELS_SFR_BASE +extern void * ip_css_base; +#define ELS_SFR_BASE ((S50_Type *) ip_css_base) +#endif /* NXPCL_FEATURE_ELS_LINK_BASE_ADDRESS */ + +#endif diff --git a/components/els_pkc/src/platforms/mcxn/mcuxClConfig.h b/components/els_pkc/src/platforms/mcxn/mcuxClConfig.h new file mode 100644 index 000000000..1bf64d7c2 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/mcuxClConfig.h @@ -0,0 +1,778 @@ +/*--------------------------------------------------------------------------*/ +/* Copyright 2023 NXP */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may */ +/* only be used strictly in accordance with the applicable license terms. */ +/* By expressly accepting such terms or by downloading, installing, */ +/* activating and/or otherwise using the software, you are agreeing that */ +/* you have read, and that you agree to comply with and are bound by, such */ +/* license terms. If you do not agree to be bound by the applicable license */ +/* terms, then you may not retain, install, activate or otherwise use the */ +/* software. */ +/*--------------------------------------------------------------------------*/ + +#ifndef MCUXCL_CONFIG_H_ +#define MCUXCL_CONFIG_H_ + +//commented defines for all available features +//#define MCUXCL_FEATURE_EXPORTED_FEATURE_HEADER +//#define MCUXCL_FEATURE_EXPORTED_PLATFORM_HEADERS +//#define MCUXCL_FEATURE_PLATFORM_RW61X +//#define MCUXCL_FEATURE_PROJECT_NIRVANA +//#define MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG +//#define MCUXCL_FEATURE_PROJECT_VOLTA_ON_NIRVANA +//#define MCUXCL_FEATURE_PROJECT_RT700 +//#define MCUXCL_FEATURE_PROJECT_BLACKBIRD +//#define MCUXCL_FEATURE_PROJECT_CSSL +//#define MCUXCL_FEATURE_PROJECT_NCCL +//#define MCUXCL_FEATURE_PROJECT_QUANTUM +//#define MCUXCL_FEATURE_HW_ELS +//#define MCUXCL_FEATURE_HW_GDET +//#define MCUXCL_FEATURE_HW_GLIKEY +//#define MCUXCL_FEATURE_HW_PKC +//#define MCUXCL_FEATURE_HW_ROPUF +//#define MCUXCL_FEATURE_HW_SAFO_SM3 +//#define MCUXCL_FEATURE_HW_SAFO_SM4 +//#define MCUXCL_FEATURE_HW_SGI +//#define MCUXCL_FEATURE_HW_TRNG +//#define MCUXCL_FEATURE_HW_RISCV_ZBB +//#define MCUXCL_FEATURE_HW_RISCV_CSW +//#define MCUXCL_FEATURE_HW_CACHE_ENABLED +//#define MCUXCL_FEATURE_ELS +//#define MCUXCL_FEATURE_ELS_AEAD +//#define MCUXCL_FEATURE_ELS_API_INPUT_PARAM_CHECKS +//#define MCUXCL_FEATURE_ELS_CKDF +//#define MCUXCL_FEATURE_ELS_CKDF_SP80056C +//#define MCUXCL_FEATURE_ELS_CMAC +//#define MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE +//#define MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD_EVEN +//#define MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD +//#define MCUXCL_FEATURE_ELS_GLITCHDETECTOR +//#define MCUXCL_FEATURE_ELS_HKDF +//#define MCUXCL_FEATURE_ELS_HMAC +//#define MCUXCL_FEATURE_ELS_HWCONFIG +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT +//#define MCUXCL_FEATURE_ELS_KEY_EXPORT_SW_DFA_PROTECTION +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_TEST +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM_TEST +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE_TEST +//#define MCUXCL_FEATURE_ELS_RNG +//#define MCUXCL_FEATURE_ELS_SHA_224 +//#define MCUXCL_FEATURE_ELS_SHA_256 +//#define MCUXCL_FEATURE_ELS_SHA_384 +//#define MCUXCL_FEATURE_ELS_SHA_512 +//#define MCUXCL_FEATURE_ELS_SHA_DIRECT +//#define MCUXCL_FEATURE_ELS_SHA_DIRECT_MODE_FLAG +//#define MCUXCL_FEATURE_ELS_AES_WITH_SIDE_CHANNEL_PROTECTION +//#define MCUXCL_FEATURE_ELS_TLS +//#define MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +//#define MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS_CMAC +//#define MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT +//#define MCUXCL_FEATURE_ELS_PUK_INTERNAL +//#define MCUXCL_FEATURE_ELS_RND_RAW +//#define MCUXCL_FEATURE_ELS_PRND_INIT +//#define MCUXCL_FEATURE_ELS_DTRNG_PRV_CONFIG_LOAD +//#define MCUXCL_FEATURE_ELS_LOCKING +//#define MCUXCL_FEATURE_ELS_CMD_CRC +//#define MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK +//#define MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +//#define MCUXCL_FEATURE_ELS_RANDOMIZE_RFC3394_OUT +//#define MCUXCL_FEATURE_ELS_RESP_GEN +//#define MCUXCL_FEATURE_ELS_GET_FW_VERSION +//#define MCUXCL_FEATURE_ELS_CACHE_MAINTENANCE +//#define MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +//#define MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND_M2 +//#define MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +//#define MCUXCL_FEATURE_ELS_HW_OUT_SLOTS +//#define MCUXCL_FEATURE_ELS_LINK_BASE_ADDRESS +//#define MCUXCL_FEATURE_GLIKEY +//#define MCUXCL_FEATURE_GLIKEY_STEPS_4 +//#define MCUXCL_FEATURE_GLIKEY_STEPS_8 +//#define MCUXCL_FEATURE_DMA +//#define MCUXCL_FEATURE_DMA_SGI_HANDSHAKE +//#define MCUXCL_FEATURE_SGI +//#define MCUXCL_FEATURE_SGI_AUTOMODE +//#define MCUXCL_FEATURE_SGI_HAS_EXTERNAL_KEYBANKS +//#define MCUXCL_FEATURE_AEAD_CRYPT +//#define MCUXCL_FEATURE_AEAD_ENCRYPT_DECRYPT +//#define MCUXCL_FEATURE_AEAD_ONESHOT +//#define MCUXCL_FEATURE_AEAD_MULTIPART +//#define MCUXCL_FEATURE_AEAD_SELFTEST +//#define MCUXCL_FEATURE_AEADMODES_GCM +//#define MCUXCL_FEATURE_AEADMODES_CCM +//#define MCUXCL_FEATURE_AEADMODES_CCM_STAR +//#define MCUXCL_FEATURE_AES128 +//#define MCUXCL_FEATURE_AES192 +//#define MCUXCL_FEATURE_AES256 +//#define MCUXCL_FEATURE_CIPHER_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_CIPHER_CRYPT +//#define MCUXCL_FEATURE_CIPHER_ENCRYPT_DECRYPT +//#define MCUXCL_FEATURE_CIPHER_ONESHOT +//#define MCUXCL_FEATURE_CIPHER_MULTIPART +//#define MCUXCL_FEATURE_CIPHER_SELFTEST +//#define MCUXCL_FEATURE_CIPHERMODES_ECB +//#define MCUXCL_FEATURE_CIPHERMODES_CBC +//#define MCUXCL_FEATURE_CIPHERMODES_CTR +//#define MCUXCL_FEATURE_CIPHERMODES_CFB +//#define MCUXCL_FEATURE_CIPHERMODES_OFB +//#define MCUXCL_FEATURE_CIPHERMODES_XTS +//#define MCUXCL_FEATURE_CIPHERMODES_DMA_BLOCKING +//#define MCUXCL_FEATURE_CIPHERMODES_DMA_NONBLOCKING +//#define MCUXCL_FEATURE_CRC_HW +//#define MCUXCL_FEATURE_CRC_SW +//#define MCUXCL_FEATURE_CRC_CRC32 +//#define MCUXCL_FEATURE_ECC +//#define MCUXCL_FEATURE_ECC_VERIFY_P384 +//#define MCUXCL_FEATURE_ECC_WEIERSTRASS +//#define MCUXCL_FEATURE_ECC_MONTDH +//#define MCUXCL_FEATURE_ECC_CONSTANTS +//#define MCUXCL_FEATURE_ECC_EDDSA +//#define MCUXCL_FEATURE_ECC_WEIERECC_DECODEPOINT +//#define MCUXCL_FEATURE_ECC_WEIERECC_GENERATEKEYPAIR +//#define MCUXCL_FEATURE_ECC_ECDH_KEYAGREEMENT +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTADD +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTSUB +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SCALARMULT +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SECURESCALARMULT +//#define MCUXCL_FEATURE_ECC_STRENGTH_CHECK +//#define MCUXCL_FEATURE_EXAMPLE_PKC_ENABLED +//#define MCUXCL_FEATURE_HASH +//#define MCUXCL_FEATURE_HASH_MULTIPART +//#define MCUXCL_FEATURE_HASH_ONESHOT +//#define MCUXCL_FEATURE_HASH_COMPARE +//#define MCUXCL_FEATURE_HASH_COMPUTE +//#define MCUXCL_FEATURE_HASH_IMPORT_EXPORT_STATE +//#define MCUXCL_FEATURE_HASH_SELFTEST +//#define MCUXCL_FEATURE_HASHMODES +//#define MCUXCL_FEATURE_HASH_C_MD5 +//#define MCUXCL_FEATURE_HASH_C_SHA_1 +//#define MCUXCL_FEATURE_HASH_C_SHA_224 +//#define MCUXCL_FEATURE_HASH_C_SHA_256 +//#define MCUXCL_FEATURE_HASH_C_SHA_384 +//#define MCUXCL_FEATURE_HASH_C_SHA_512 +//#define MCUXCL_FEATURE_HASH_C_SHA_512_224 +//#define MCUXCL_FEATURE_HASH_C_SHA_512_256 +//#define MCUXCL_FEATURE_HASH_C_SHA3_SHAKE +//#define MCUXCL_FEATURE_HASH_C_SHA3 +//#define MCUXCL_FEATURE_HASH_ELS +//#define MCUXCL_FEATURE_HASH_SGI +//#define MCUXCL_FEATURE_HASH_SGI_SHA_224 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_256 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_384 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512_224 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512_256 +//#define MCUXCL_FEATURE_HASH_SGI_MIYAGUCHI_PRENEEL +//#define MCUXCL_FEATURE_HASH_LTC +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_224 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_256 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_384 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_512 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_128 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_256 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_128 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_256 +//#define MCUXCL_FEATURE_HASH_RANGER5_LIB +//#define MCUXCL_FEATURE_HASH_DMA_BLOCKING +//#define MCUXCL_FEATURE_HASH_SECSHA +//#define MCUXCL_FEATURE_HASH_SECSHA_1 +//#define MCUXCL_FEATURE_HASH_SECSHA_224 +//#define MCUXCL_FEATURE_HASH_SECSHA_256 +//#define MCUXCL_FEATURE_HASH_SECSHA_384 +//#define MCUXCL_FEATURE_HASH_SECSHA_512 +//#define MCUXCL_FEATURE_HASH_SECSHA_512_224 +//#define MCUXCL_FEATURE_HASH_SECSHA_512_256 +//#define MCUXCL_FEATURE_HASH_SECSHA3 +//#define MCUXCL_FEATURE_HASH_SECSHA3_224 +//#define MCUXCL_FEATURE_HASH_SECSHA3_256 +//#define MCUXCL_FEATURE_HASH_SECSHA3_384 +//#define MCUXCL_FEATURE_HASH_SECSHA3_512 +//#define MCUXCL_FEATURE_HASH_SGI_COUNT_WORKAROUND +//#define MCUXCL_FEATURE_KEY_DERIVATION +//#define MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_108 +//#define MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_56C +//#define MCUXCL_FEATURE_KEY_DERIVATION_ISOIEC_18033_2 +//#define MCUXCL_FEATURE_KEY_DERIVATION_ANSI_X9_63 +//#define MCUXCL_FEATURE_KEY_DERIVATION_RFC5246_PRF +//#define MCUXCL_FEATURE_KEY_DERIVATION_HKDF +//#define MCUXCL_FEATURE_KEY_GENERATION +//#define MCUXCL_FEATURE_KEY_AGREEMENT +//#define MCUXCL_FEATURE_KEY_PROTECT +//#define MCUXCL_FEATURE_KEY_SELFTEST +//#define MCUXCL_FEATURE_KEY_VALIDATION +//#define MCUXCL_FEATURE_KYBER +//#define MCUXCL_FEATURE_LTC +//#define MCUXCL_FEATURE_MAC +//#define MCUXCL_FEATURE_MAC_COMPARE +//#define MCUXCL_FEATURE_MAC_COMPUTE +//#define MCUXCL_FEATURE_MAC_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_MAC_MULTIPART +//#define MCUXCL_FEATURE_MAC_ONESHOT +//#define MCUXCL_FEATURE_MAC_SELFTEST +//#define MCUXCL_FEATURE_MACMODES_CBCMAC +//#define MCUXCL_FEATURE_MACMODES_CMAC +//#define MCUXCL_FEATURE_MACMODES_SGI_CMAC_SUB_KEYS +//#define MCUXCL_FEATURE_MACMODES_GMAC +//#define MCUXCL_FEATURE_MACMODES_KMAC +//#define MCUXCL_FEATURE_MACMODES_XCBCMAC +//#define MCUXCL_FEATURE_MACMODES_DMA_BLOCKING +//#define MCUXCL_FEATURE_MACMODES_DMA_NONBLOCKING +//#define MCUXCL_FEATURE_MAC_SIPHASH +//#define MCUXCL_FEATURE_HMAC_ELS +//#define MCUXCL_FEATURE_HMAC_SW +//#define MCUXCL_FEATURE_MATH_PKC +//#define MCUXCL_FEATURE_MATH_SECMODEXP_RISCV_SFRMASKING +//#define MCUXCL_FEATURE_PADDING_ISO9797_1_M1 +//#define MCUXCL_FEATURE_PADDING_ISO9797_1_M2 +//#define MCUXCL_FEATURE_PADDING_PKCS7 +//#define MCUXCL_FEATURE_PADDING_REMOVAL +//#define MCUXCL_FEATURE_PKC_CRR_HEADER +//#define MCUXCL_FEATURE_PKC_RAM_4KB +//#define MCUXCL_FEATURE_PKC_RAM_8KB +//#define MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS +//#define MCUXCL_FEATURE_PKC_PKCRAM_EXPLICIT_INIT_WORKAROUND +//#define MCUXCL_FEATURE_PKC_BLOCK_CPU_WORKAROUND +//#define MCUXCL_FEATURE_PKC_CPUPKC_ARBITRATION_WORKAROUND +//#define MCUXCL_FEATURE_PKC_FLEX_MC +//#define MCUXCL_FEATURE_PKC_PW_READY +//#define MCUXCL_FEATURE_PRNG +//#define MCUXCL_FEATURE_PRNG_ELS +//#define MCUXCL_FEATURE_PRNG_SCM +//#define MCUXCL_FEATURE_PRNG_NONE +//#define MCUXCL_FEATURE_RANDOM +//#define MCUXCL_FEATURE_RANDOMMODES_ELSMODE +//#define MCUXCL_FEATURE_RANDOMMODES_NORMALMODE +//#define MCUXCL_FEATURE_RANDOMMODES_PATCHMODE +//#define MCUXCL_FEATURE_RANDOMMODES_TESTMODE +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +//#define MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +//#define MCUXCL_FEATURE_RANDOMMODES_PTG3 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_128 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_192 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +//#define MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION +//#define MCUXCL_FEATURE_RANDOMMODES_NO_DERIVATION_FUNCTION +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_SGI +//#define MCUXCL_FEATURE_RSA_ENCRYPT +//#define MCUXCL_FEATURE_RSA_DECRYPT +//#define MCUXCL_FEATURE_RSA_SIGN +//#define MCUXCL_FEATURE_RSA_VERIFY +//#define MCUXCL_FEATURE_RSA_INTERNAL +//#define MCUXCL_FEATURE_RSA_KEYGENERATION +//#define MCUXCL_FEATURE_RSA_NOHWACC_2K +//#define MCUXCL_FEATURE_RSA_NOHWACC_3K +//#define MCUXCL_FEATURE_RSA_VERIFY_SWONLY +//#define MCUXCL_FEATURE_RSA_STRENGTH_CHECK +//#define MCUXCL_FEATURE_RSA_RSASSA_PSS +//#define MCUXCL_FEATURE_RSA_RSASSA_PKCS1v15 +//#define MCUXCL_FEATURE_RSA_RSAES_OAEP +//#define MCUXCL_FEATURE_RSA_RSAES_PKCS1v15 +//#define MCUXCL_FEATURE_RSA_NOENCODE +//#define MCUXCL_FEATURE_RSA_8K_KEYS +//#define MCUXCL_FEATURE_SESSION_HAS_RANDOM +//#define MCUXCL_FEATURE_SESSION_HAS_RTF +//#define MCUXCL_FEATURE_SESSION_PKCWA_CHECK +//#define MCUXCL_FEATURE_SESSION_JOBS +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DUMMYCYCLES +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_ADDITIONAL_SWCOMP +//#define MCUXCL_FEATURE_SIGNATURE_ECDSA +//#define MCUXCL_FEATURE_SIGNATURE_EDDSA +//#define MCUXCL_FEATURE_SIGNATURE_MULTIPART +//#define MCUXCL_FEATURE_SIGNATURE_ONESHOT +//#define MCUXCL_FEATURE_SIGNATURE_RSASSA_PKCS1v15 +//#define MCUXCL_FEATURE_SIGNATURE_RSASSA_PSS +//#define MCUXCL_FEATURE_SIGNATURE_SIGN +//#define MCUXCL_FEATURE_SIGNATURE_VERIFY +//#define MCUXCL_FEATURE_SIGNATURE_SELFTEST +//#define MCUXCL_FEATURE_SIGNATURE_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_SIGNATURE_FAST_VERIFICATION +//#define MCUXCL_FEATURE_SIGNATURE_DILITHIUM +//#define MCUXCL_FEATURE_TRNG_CRR_HEADER +//#define MCUXCL_FEATURE_TRNG_ELS +//#define MCUXCL_FEATURE_TRNG_SA_TRNG +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_256 +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_512 +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_DUAL_OSCILLATOR_MODE +//#define MCUXCL_FEATURE_XOF_ONESHOT +//#define MCUXCL_FEATURE_XOF_MULTIPART +//#define MCUXCL_FEATURE_XOF_C_SHAKE_128 +//#define MCUXCL_FEATURE_XOF_C_SHAKE_256 +//#define MCUXCL_FEATURE_XOF_LTC +//#define MCUXCL_FEATURE_XOF_LTC_SHAKE_128 +//#define MCUXCL_FEATURE_XOF_LTC_SHAKE_256 +//#define MCUXCL_FEATURE_XOF_LTC_CSHAKE_128 +//#define MCUXCL_FEATURE_XOF_LTC_CSHAKE_256 +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_CODE_SIGNATURE +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_NONE +//#define MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_FP_USE_CODE_SIGNATURE +//#define MCUXCL_FEATURE_CSSL_FP_USE_NONE +//#define MCUXCL_FEATURE_CSSL_FP_EXCLUDE_COVERITY_PRAGMAS +//#define MCUXCL_FEATURE_CSSL_ARM_M0 +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COPY +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_XOR +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SET +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COMPARE +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_CLEAR +//#define MCUXCL_FEATURE_CSSL_MEMORY_C_FALLBACK +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_NORMAL_OPERATION_RISCV +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SECURE_OPERATION_RISCV +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HYBRID_LOCAL_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_SCM +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_S3SCM +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_LOCAL +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CALLBACK +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CONTEXT +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_GLOBAL +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_NONE +//#define MCUXCL_FEATURE_CSSL_SC_USE_HYBRID_LOCAL_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_SCM +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_S3SCM +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_CALLBACK +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_CONTEXT +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_GLOBAL +//#define MCUXCL_FEATURE_CSSL_SC_USE_NONE +//#define MCUXCL_FEATURE_CSSL_SC_RISCV_ASM +//#define MCUXCL_FEATURE_CSSL_DI_USE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_DI_USE_NONE +//#define MCUXCL_FEATURE_CSSL_MEMORY_PRNG_STUB +//#define MCUXCL_FEATURE_SM4_CCM +//#define MCUXCL_FEATURE_CIPHERMODES_SM4 +//#define MCUXCL_FEATURE_HASH_HW_SM3 +//#define MCUXCL_FEATURE_HASH_SW_SM3 +//#define MCUXCL_FEATURE_HASH_SM3_RISCV +//#define MCUXCL_FEATURE_MACMODES_HMAC_SM3 +//#define MCUXCL_FEATURE_MACMODES_CBCMAC_SM4 +//#define MCUXCL_FEATURE_MACMODES_CMAC_SM4 +//#define MCUXCL_FEATURE_RANDOMMODES_OSCCA_TRNG +//#define MCUXCL_FEATURE_OSCCA_RNG_256 +//#define MCUXCL_FEATURE_OSCCA_RNG_512 +//#define MCUXCL_FEATURE_OSCCA_RNG_2_SOURCES +//#define MCUXCL_FEATURE_SM2_INTERNAL +//#define MCUXCL_FEATURE_SM2_KEYGEN +//#define MCUXCL_FEATURE_SM2_CIPHER +//#define MCUXCL_FEATURE_SM2_SIGNATURE +//#define MCUXCL_FEATURE_SM2_KEYAGREEMENT +//#define MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_32 +//#define MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_64 +//#define MCUXCL_FEATURE_PROJECT_CLNS +//#define MCUXCL_FEATURE_SB3 +//#define MCUXCL_FEATURE_SB3_384 +//#define MCUXCL_FEATURE_RSA_ADAPTERCHECKS +//#define MCUXCL_FEATURE_BINARY_DELIVERY +//#define MCUXCL_FEATURE_SOURCE_DELIVERY +//#define MCUXCL_FEATURE_KEEP_ECLIPSE_FORMATTER_CONTROL +//#define MCUXCL_FEATURE_KEEP_INTERNAL_COMMENTS +//#define MCUXCL_FEATURE_INTERNAL_INCLUDES_FLAG + +//commented defines for all enabled features +//#define MCUXCL_FEATURE_EXPORTED_FEATURE_HEADER +//#define MCUXCL_FEATURE_EXPORTED_PLATFORM_HEADERS +//#define MCUXCL_FEATURE_PLATFORM_RW61X +//#define MCUXCL_FEATURE_PROJECT_NIRVANA +//#define MCUXCL_FEATURE_PROJECT_NIOBE4ANALOG +//#define MCUXCL_FEATURE_PROJECT_VOLTA_ON_NIRVANA +//#define MCUXCL_FEATURE_PROJECT_RT700 +//#define MCUXCL_FEATURE_PROJECT_BLACKBIRD +//#define MCUXCL_FEATURE_PROJECT_CSSL +//#define MCUXCL_FEATURE_PROJECT_NCCL +//#define MCUXCL_FEATURE_PROJECT_QUANTUM +//#define MCUXCL_FEATURE_HW_ELS +//#define MCUXCL_FEATURE_HW_GDET +//#define MCUXCL_FEATURE_HW_GLIKEY +//#define MCUXCL_FEATURE_HW_PKC +//#define MCUXCL_FEATURE_HW_ROPUF +//#define MCUXCL_FEATURE_HW_SAFO_SM3 +//#define MCUXCL_FEATURE_HW_SAFO_SM4 +//#define MCUXCL_FEATURE_HW_SGI +//#define MCUXCL_FEATURE_HW_TRNG +//#define MCUXCL_FEATURE_HW_RISCV_ZBB +//#define MCUXCL_FEATURE_HW_RISCV_CSW +//#define MCUXCL_FEATURE_HW_CACHE_ENABLED +//#define MCUXCL_FEATURE_ELS +//#define MCUXCL_FEATURE_ELS_AEAD +//#define MCUXCL_FEATURE_ELS_API_INPUT_PARAM_CHECKS +//#define MCUXCL_FEATURE_ELS_CKDF +//#define MCUXCL_FEATURE_ELS_CKDF_SP80056C +//#define MCUXCL_FEATURE_ELS_CMAC +//#define MCUXCL_FEATURE_ELS_ECC_KEY_EXCHANGE +//#define MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD_EVEN +//#define MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD +//#define MCUXCL_FEATURE_ELS_GLITCHDETECTOR +//#define MCUXCL_FEATURE_ELS_HKDF +//#define MCUXCL_FEATURE_ELS_HMAC +//#define MCUXCL_FEATURE_ELS_HWCONFIG +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_DELETE +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_EXPORT +//#define MCUXCL_FEATURE_ELS_KEY_EXPORT_SW_DFA_PROTECTION +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_TEST +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM_TEST +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE +//#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE_TEST +//#define MCUXCL_FEATURE_ELS_RNG +//#define MCUXCL_FEATURE_ELS_SHA_224 +//#define MCUXCL_FEATURE_ELS_SHA_256 +//#define MCUXCL_FEATURE_ELS_SHA_384 +//#define MCUXCL_FEATURE_ELS_SHA_512 +//#define MCUXCL_FEATURE_ELS_SHA_DIRECT +//#define MCUXCL_FEATURE_ELS_SHA_DIRECT_MODE_FLAG +//#define MCUXCL_FEATURE_ELS_AES_WITH_SIDE_CHANNEL_PROTECTION +//#define MCUXCL_FEATURE_ELS_TLS +//#define MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS +//#define MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS_CMAC +//#define MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT +//#define MCUXCL_FEATURE_ELS_PUK_INTERNAL +//#define MCUXCL_FEATURE_ELS_RND_RAW +//#define MCUXCL_FEATURE_ELS_PRND_INIT +//#define MCUXCL_FEATURE_ELS_DTRNG_PRV_CONFIG_LOAD +//#define MCUXCL_FEATURE_ELS_LOCKING +//#define MCUXCL_FEATURE_ELS_CMD_CRC +//#define MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK +//#define MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK +//#define MCUXCL_FEATURE_ELS_RANDOMIZE_RFC3394_OUT +//#define MCUXCL_FEATURE_ELS_RESP_GEN +//#define MCUXCL_FEATURE_ELS_GET_FW_VERSION +//#define MCUXCL_FEATURE_ELS_CACHE_MAINTENANCE +//#define MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND +//#define MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND_M2 +//#define MCUXCL_FEATURE_ELS_ITERATIVE_SEEDING +//#define MCUXCL_FEATURE_ELS_HW_OUT_SLOTS +//#define MCUXCL_FEATURE_ELS_LINK_BASE_ADDRESS +//#define MCUXCL_FEATURE_GLIKEY +//#define MCUXCL_FEATURE_GLIKEY_STEPS_4 +//#define MCUXCL_FEATURE_GLIKEY_STEPS_8 +//#define MCUXCL_FEATURE_DMA +//#define MCUXCL_FEATURE_DMA_SGI_HANDSHAKE +//#define MCUXCL_FEATURE_SGI +//#define MCUXCL_FEATURE_SGI_AUTOMODE +//#define MCUXCL_FEATURE_SGI_HAS_EXTERNAL_KEYBANKS +//#define MCUXCL_FEATURE_AEAD_CRYPT +//#define MCUXCL_FEATURE_AEAD_ENCRYPT_DECRYPT +//#define MCUXCL_FEATURE_AEAD_ONESHOT +//#define MCUXCL_FEATURE_AEAD_MULTIPART +//#define MCUXCL_FEATURE_AEAD_SELFTEST +//#define MCUXCL_FEATURE_AEADMODES_GCM +//#define MCUXCL_FEATURE_AEADMODES_CCM +//#define MCUXCL_FEATURE_AEADMODES_CCM_STAR +//#define MCUXCL_FEATURE_AES128 +//#define MCUXCL_FEATURE_AES192 +//#define MCUXCL_FEATURE_AES256 +//#define MCUXCL_FEATURE_CIPHER_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_CIPHER_CRYPT +//#define MCUXCL_FEATURE_CIPHER_ENCRYPT_DECRYPT +//#define MCUXCL_FEATURE_CIPHER_ONESHOT +//#define MCUXCL_FEATURE_CIPHER_MULTIPART +//#define MCUXCL_FEATURE_CIPHER_SELFTEST +//#define MCUXCL_FEATURE_CIPHERMODES_ECB +//#define MCUXCL_FEATURE_CIPHERMODES_CBC +//#define MCUXCL_FEATURE_CIPHERMODES_CTR +//#define MCUXCL_FEATURE_CIPHERMODES_CFB +//#define MCUXCL_FEATURE_CIPHERMODES_OFB +//#define MCUXCL_FEATURE_CIPHERMODES_XTS +//#define MCUXCL_FEATURE_CIPHERMODES_DMA_BLOCKING +//#define MCUXCL_FEATURE_CIPHERMODES_DMA_NONBLOCKING +//#define MCUXCL_FEATURE_CRC_HW +//#define MCUXCL_FEATURE_CRC_SW +//#define MCUXCL_FEATURE_CRC_CRC32 +//#define MCUXCL_FEATURE_ECC +//#define MCUXCL_FEATURE_ECC_VERIFY_P384 +//#define MCUXCL_FEATURE_ECC_WEIERSTRASS +//#define MCUXCL_FEATURE_ECC_MONTDH +//#define MCUXCL_FEATURE_ECC_CONSTANTS +//#define MCUXCL_FEATURE_ECC_EDDSA +//#define MCUXCL_FEATURE_ECC_WEIERECC_DECODEPOINT +//#define MCUXCL_FEATURE_ECC_WEIERECC_GENERATEKEYPAIR +//#define MCUXCL_FEATURE_ECC_ECDH_KEYAGREEMENT +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTADD +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_POINTSUB +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SCALARMULT +//#define MCUXCL_FEATURE_ECC_ARITHMETICOPERATION_SECURESCALARMULT +//#define MCUXCL_FEATURE_ECC_STRENGTH_CHECK +//#define MCUXCL_FEATURE_EXAMPLE_PKC_ENABLED +//#define MCUXCL_FEATURE_HASH +//#define MCUXCL_FEATURE_HASH_MULTIPART +//#define MCUXCL_FEATURE_HASH_ONESHOT +//#define MCUXCL_FEATURE_HASH_COMPARE +//#define MCUXCL_FEATURE_HASH_COMPUTE +//#define MCUXCL_FEATURE_HASH_IMPORT_EXPORT_STATE +//#define MCUXCL_FEATURE_HASH_SELFTEST +//#define MCUXCL_FEATURE_HASHMODES +//#define MCUXCL_FEATURE_HASH_C_MD5 +//#define MCUXCL_FEATURE_HASH_C_SHA_1 +//#define MCUXCL_FEATURE_HASH_C_SHA_224 +//#define MCUXCL_FEATURE_HASH_C_SHA_256 +//#define MCUXCL_FEATURE_HASH_C_SHA_384 +//#define MCUXCL_FEATURE_HASH_C_SHA_512 +//#define MCUXCL_FEATURE_HASH_C_SHA_512_224 +//#define MCUXCL_FEATURE_HASH_C_SHA_512_256 +//#define MCUXCL_FEATURE_HASH_C_SHA3_SHAKE +//#define MCUXCL_FEATURE_HASH_C_SHA3 +//#define MCUXCL_FEATURE_HASH_ELS +//#define MCUXCL_FEATURE_HASH_SGI +//#define MCUXCL_FEATURE_HASH_SGI_SHA_224 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_256 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_384 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512_224 +//#define MCUXCL_FEATURE_HASH_SGI_SHA_512_256 +//#define MCUXCL_FEATURE_HASH_SGI_MIYAGUCHI_PRENEEL +//#define MCUXCL_FEATURE_HASH_LTC +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_224 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_256 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_384 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_512 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_128 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_SHAKE_256 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_128 +//#define MCUXCL_FEATURE_HASH_LTC_SHA3_CSHAKE_256 +//#define MCUXCL_FEATURE_HASH_RANGER5_LIB +//#define MCUXCL_FEATURE_HASH_DMA_BLOCKING +//#define MCUXCL_FEATURE_HASH_SECSHA +//#define MCUXCL_FEATURE_HASH_SECSHA_1 +//#define MCUXCL_FEATURE_HASH_SECSHA_224 +//#define MCUXCL_FEATURE_HASH_SECSHA_256 +//#define MCUXCL_FEATURE_HASH_SECSHA_384 +//#define MCUXCL_FEATURE_HASH_SECSHA_512 +//#define MCUXCL_FEATURE_HASH_SECSHA_512_224 +//#define MCUXCL_FEATURE_HASH_SECSHA_512_256 +//#define MCUXCL_FEATURE_HASH_SECSHA3 +//#define MCUXCL_FEATURE_HASH_SECSHA3_224 +//#define MCUXCL_FEATURE_HASH_SECSHA3_256 +//#define MCUXCL_FEATURE_HASH_SECSHA3_384 +//#define MCUXCL_FEATURE_HASH_SECSHA3_512 +//#define MCUXCL_FEATURE_HASH_SGI_COUNT_WORKAROUND +//#define MCUXCL_FEATURE_KEY_DERIVATION +//#define MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_108 +//#define MCUXCL_FEATURE_KEY_DERIVATION_NIST_SP800_56C +//#define MCUXCL_FEATURE_KEY_DERIVATION_ISOIEC_18033_2 +//#define MCUXCL_FEATURE_KEY_DERIVATION_ANSI_X9_63 +//#define MCUXCL_FEATURE_KEY_DERIVATION_RFC5246_PRF +//#define MCUXCL_FEATURE_KEY_DERIVATION_HKDF +//#define MCUXCL_FEATURE_KEY_GENERATION +//#define MCUXCL_FEATURE_KEY_AGREEMENT +//#define MCUXCL_FEATURE_KEY_PROTECT +//#define MCUXCL_FEATURE_KEY_SELFTEST +//#define MCUXCL_FEATURE_KEY_VALIDATION +//#define MCUXCL_FEATURE_KYBER +//#define MCUXCL_FEATURE_LTC +//#define MCUXCL_FEATURE_MAC +//#define MCUXCL_FEATURE_MAC_COMPARE +//#define MCUXCL_FEATURE_MAC_COMPUTE +//#define MCUXCL_FEATURE_MAC_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_MAC_MULTIPART +//#define MCUXCL_FEATURE_MAC_ONESHOT +//#define MCUXCL_FEATURE_MAC_SELFTEST +//#define MCUXCL_FEATURE_MACMODES_CBCMAC +//#define MCUXCL_FEATURE_MACMODES_CMAC +//#define MCUXCL_FEATURE_MACMODES_SGI_CMAC_SUB_KEYS +//#define MCUXCL_FEATURE_MACMODES_GMAC +//#define MCUXCL_FEATURE_MACMODES_KMAC +//#define MCUXCL_FEATURE_MACMODES_XCBCMAC +//#define MCUXCL_FEATURE_MACMODES_DMA_BLOCKING +//#define MCUXCL_FEATURE_MACMODES_DMA_NONBLOCKING +//#define MCUXCL_FEATURE_MAC_SIPHASH +//#define MCUXCL_FEATURE_HMAC_ELS +//#define MCUXCL_FEATURE_HMAC_SW +//#define MCUXCL_FEATURE_MATH_PKC +//#define MCUXCL_FEATURE_MATH_SECMODEXP_RISCV_SFRMASKING +//#define MCUXCL_FEATURE_PADDING_ISO9797_1_M1 +//#define MCUXCL_FEATURE_PADDING_ISO9797_1_M2 +//#define MCUXCL_FEATURE_PADDING_PKCS7 +//#define MCUXCL_FEATURE_PADDING_REMOVAL +//#define MCUXCL_FEATURE_PKC_CRR_HEADER +//#define MCUXCL_FEATURE_PKC_RAM_4KB +//#define MCUXCL_FEATURE_PKC_RAM_8KB +//#define MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS +//#define MCUXCL_FEATURE_PKC_PKCRAM_EXPLICIT_INIT_WORKAROUND +//#define MCUXCL_FEATURE_PKC_BLOCK_CPU_WORKAROUND +//#define MCUXCL_FEATURE_PKC_CPUPKC_ARBITRATION_WORKAROUND +//#define MCUXCL_FEATURE_PKC_FLEX_MC +//#define MCUXCL_FEATURE_PKC_PW_READY +//#define MCUXCL_FEATURE_PRNG +//#define MCUXCL_FEATURE_PRNG_ELS +//#define MCUXCL_FEATURE_PRNG_SCM +//#define MCUXCL_FEATURE_PRNG_NONE +//#define MCUXCL_FEATURE_RANDOM +//#define MCUXCL_FEATURE_RANDOMMODES_ELSMODE +//#define MCUXCL_FEATURE_RANDOMMODES_NORMALMODE +//#define MCUXCL_FEATURE_RANDOMMODES_PATCHMODE +//#define MCUXCL_FEATURE_RANDOMMODES_TESTMODE +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG +//#define MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED +//#define MCUXCL_FEATURE_RANDOMMODES_PTG3 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_128 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_192 +//#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 +//#define MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION +//#define MCUXCL_FEATURE_RANDOMMODES_NO_DERIVATION_FUNCTION +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS +//#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_SGI +//#define MCUXCL_FEATURE_RSA_ENCRYPT +//#define MCUXCL_FEATURE_RSA_DECRYPT +//#define MCUXCL_FEATURE_RSA_SIGN +//#define MCUXCL_FEATURE_RSA_VERIFY +//#define MCUXCL_FEATURE_RSA_INTERNAL +//#define MCUXCL_FEATURE_RSA_KEYGENERATION +//#define MCUXCL_FEATURE_RSA_NOHWACC_2K +//#define MCUXCL_FEATURE_RSA_NOHWACC_3K +//#define MCUXCL_FEATURE_RSA_VERIFY_SWONLY +//#define MCUXCL_FEATURE_RSA_STRENGTH_CHECK +//#define MCUXCL_FEATURE_RSA_RSASSA_PSS +//#define MCUXCL_FEATURE_RSA_RSASSA_PKCS1v15 +//#define MCUXCL_FEATURE_RSA_RSAES_OAEP +//#define MCUXCL_FEATURE_RSA_RSAES_PKCS1v15 +//#define MCUXCL_FEATURE_RSA_NOENCODE +//#define MCUXCL_FEATURE_RSA_8K_KEYS +//#define MCUXCL_FEATURE_SESSION_HAS_RANDOM +//#define MCUXCL_FEATURE_SESSION_HAS_RTF +//#define MCUXCL_FEATURE_SESSION_PKCWA_CHECK +//#define MCUXCL_FEATURE_SESSION_JOBS +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_DUMMYCYCLES +//#define MCUXCL_FEATURE_SESSION_SECURITYOPTIONS_ADDITIONAL_SWCOMP +//#define MCUXCL_FEATURE_SIGNATURE_ECDSA +//#define MCUXCL_FEATURE_SIGNATURE_EDDSA +//#define MCUXCL_FEATURE_SIGNATURE_MULTIPART +//#define MCUXCL_FEATURE_SIGNATURE_ONESHOT +//#define MCUXCL_FEATURE_SIGNATURE_RSASSA_PKCS1v15 +//#define MCUXCL_FEATURE_SIGNATURE_RSASSA_PSS +//#define MCUXCL_FEATURE_SIGNATURE_SIGN +//#define MCUXCL_FEATURE_SIGNATURE_VERIFY +//#define MCUXCL_FEATURE_SIGNATURE_SELFTEST +//#define MCUXCL_FEATURE_SIGNATURE_CONTEXT_INTEGRITY_PROTECTION +//#define MCUXCL_FEATURE_SIGNATURE_FAST_VERIFICATION +//#define MCUXCL_FEATURE_SIGNATURE_DILITHIUM +//#define MCUXCL_FEATURE_TRNG_CRR_HEADER +//#define MCUXCL_FEATURE_TRNG_ELS +//#define MCUXCL_FEATURE_TRNG_SA_TRNG +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_256 +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_512 +//#define MCUXCL_FEATURE_TRNG_SA_TRNG_DUAL_OSCILLATOR_MODE +//#define MCUXCL_FEATURE_XOF_ONESHOT +//#define MCUXCL_FEATURE_XOF_MULTIPART +//#define MCUXCL_FEATURE_XOF_C_SHAKE_128 +//#define MCUXCL_FEATURE_XOF_C_SHAKE_256 +//#define MCUXCL_FEATURE_XOF_LTC +//#define MCUXCL_FEATURE_XOF_LTC_SHAKE_128 +//#define MCUXCL_FEATURE_XOF_LTC_SHAKE_256 +//#define MCUXCL_FEATURE_XOF_LTC_CSHAKE_128 +//#define MCUXCL_FEATURE_XOF_LTC_CSHAKE_256 +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_CODE_SIGNATURE +//#define MCUXCL_FEATURE_CSSL_FP_INCLUDE_NONE +//#define MCUXCL_FEATURE_CSSL_FP_USE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_FP_USE_CODE_SIGNATURE +//#define MCUXCL_FEATURE_CSSL_FP_USE_NONE +//#define MCUXCL_FEATURE_CSSL_FP_EXCLUDE_COVERITY_PRAGMAS +//#define MCUXCL_FEATURE_CSSL_ARM_M0 +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COPY +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_XOR +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SET +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_COMPARE +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_CLEAR +//#define MCUXCL_FEATURE_CSSL_MEMORY_C_FALLBACK +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_NORMAL_OPERATION_RISCV +//#define MCUXCL_FEATURE_CSSL_MEMORY_ENABLE_SECURE_OPERATION_RISCV +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HYBRID_LOCAL_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_SCM +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_HW_S3SCM +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_LOCAL +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CALLBACK +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_CONTEXT +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_SW_GLOBAL +//#define MCUXCL_FEATURE_CSSL_SC_INCLUDE_NONE +//#define MCUXCL_FEATURE_CSSL_SC_USE_HYBRID_LOCAL_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_CDOG +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_SCM +//#define MCUXCL_FEATURE_CSSL_SC_USE_HW_S3SCM +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_LOCAL +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_CALLBACK +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_CONTEXT +//#define MCUXCL_FEATURE_CSSL_SC_USE_SW_GLOBAL +//#define MCUXCL_FEATURE_CSSL_SC_USE_NONE +//#define MCUXCL_FEATURE_CSSL_SC_RISCV_ASM +//#define MCUXCL_FEATURE_CSSL_DI_USE_SECURE_COUNTER +//#define MCUXCL_FEATURE_CSSL_DI_USE_NONE +//#define MCUXCL_FEATURE_CSSL_MEMORY_PRNG_STUB +//#define MCUXCL_FEATURE_SM4_CCM +//#define MCUXCL_FEATURE_CIPHERMODES_SM4 +//#define MCUXCL_FEATURE_HASH_HW_SM3 +//#define MCUXCL_FEATURE_HASH_SW_SM3 +//#define MCUXCL_FEATURE_HASH_SM3_RISCV +//#define MCUXCL_FEATURE_MACMODES_HMAC_SM3 +//#define MCUXCL_FEATURE_MACMODES_CBCMAC_SM4 +//#define MCUXCL_FEATURE_MACMODES_CMAC_SM4 +//#define MCUXCL_FEATURE_RANDOMMODES_OSCCA_TRNG +//#define MCUXCL_FEATURE_OSCCA_RNG_256 +//#define MCUXCL_FEATURE_OSCCA_RNG_512 +//#define MCUXCL_FEATURE_OSCCA_RNG_2_SOURCES +//#define MCUXCL_FEATURE_SM2_INTERNAL +//#define MCUXCL_FEATURE_SM2_KEYGEN +//#define MCUXCL_FEATURE_SM2_CIPHER +//#define MCUXCL_FEATURE_SM2_SIGNATURE +//#define MCUXCL_FEATURE_SM2_KEYAGREEMENT +//#define MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_32 +//#define MCUXCL_FEATURE_CAAM_POINTER_SIZE_BITS_64 +//#define MCUXCL_FEATURE_PROJECT_CLNS +//#define MCUXCL_FEATURE_SB3 +//#define MCUXCL_FEATURE_SB3_384 +//#define MCUXCL_FEATURE_RSA_ADAPTERCHECKS +//#define MCUXCL_FEATURE_BINARY_DELIVERY +//#define MCUXCL_FEATURE_SOURCE_DELIVERY +//#define MCUXCL_FEATURE_KEEP_ECLIPSE_FORMATTER_CONTROL +//#define MCUXCL_FEATURE_KEEP_INTERNAL_COMMENTS +//#define MCUXCL_FEATURE_INTERNAL_INCLUDES_FLAG + +//defines for exported features +#define MCUXCL_FEATURE_PROJECT_NIRVANA 1 +#define MCUXCL_FEATURE_HW_SAFO_SM3 1 +#define MCUXCL_FEATURE_HW_TRNG 1 +#define MCUXCL_FEATURE_ELS_ECC_ECKXCH_ODD_EVEN 1 +#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_ROM_TEST 1 +#define MCUXCL_FEATURE_ELS_KEY_MGMT_KEYPROV_DUK_UPDATE_TEST 1 +#define MCUXCL_FEATURE_ELS_AES_WITH_SIDE_CHANNEL_PROTECTION 1 +#define MCUXCL_FEATURE_ELS_NO_INTERNAL_STATE_FLAGS 1 +#define MCUXCL_FEATURE_ELS_PUK_INTERNAL_BIT 1 +#define MCUXCL_FEATURE_ELS_PUK_INTERNAL 1 +#define MCUXCL_FEATURE_ELS_RND_RAW 1 +#define MCUXCL_FEATURE_ELS_PRND_INIT 1 +#define MCUXCL_FEATURE_ELS_LOCKING 1 +#define MCUXCL_FEATURE_ELS_CMD_CRC 1 +#define MCUXCL_FEATURE_ELS_DMA_ADDRESS_READBACK 1 +#define MCUXCL_FEATURE_ELS_DMA_FINAL_ADDRESS_READBACK 1 +#define MCUXCL_FEATURE_ELS_GET_FW_VERSION 1 +#define MCUXCL_FEATURE_ELS_ACCESS_PKCRAM_WORKAROUND 1 +#define MCUXCL_FEATURE_ECC_STRENGTH_CHECK 1 +#define MCUXCL_FEATURE_PKC_PKCRAM_NO_UNALIGNED_ACCESS 1 +#define MCUXCL_FEATURE_RANDOMMODES_NORMALMODE 1 +#define MCUXCL_FEATURE_RANDOMMODES_TESTMODE 1 +#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG 1 +#define MCUXCL_FEATURE_RANDOMMODES_PR_DISABLED 1 +#define MCUXCL_FEATURE_RANDOMMODES_SECSTRENGTH_256 1 +#define MCUXCL_FEATURE_RANDOMMODES_DERIVATION_FUNCTION 1 +#define MCUXCL_FEATURE_RANDOMMODES_CTRDRBG_ELS 1 +#define MCUXCL_FEATURE_RSA_STRENGTH_CHECK 1 +#define MCUXCL_FEATURE_SESSION_HAS_RANDOM 1 +#define MCUXCL_FEATURE_SESSION_HAS_RANDOM 1 +#define MCUXCL_FEATURE_TRNG_ELS 1 + +#if defined(FSL_FEATURE_SOC_SM3_COUNT) && FSL_FEATURE_SOC_SM3_COUNT +#define MCUXCL_FEATURE_HASH_HW_SM3 +#endif /* defined(FSL_FEATURE_SOC_SM3_COUNT) && FSL_FEATURE_SOC_SM3_COUNT */ + +#endif diff --git a/components/els_pkc/src/platforms/mcxn/mcux_els.c b/components/els_pkc/src/platforms/mcxn/mcux_els.c new file mode 100644 index 000000000..3d0aa8aab --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/mcux_els.c @@ -0,0 +1,134 @@ +/* + * Copyright 2021 - 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcux_els.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t ELS_PRNG_KickOff(void); +static status_t ELS_check_key(uint8_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief ELS Init after power down. + * + * This function enable all ELS related clocks, enable ELS and start ELS PRNG. + * Normally all of these actions are done automatically by boot ROM, but if an application uses Power Down mode + * this function must be called before using ELS after wake-up. + * + * param base ELS peripheral address. + * + * return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t ELS_PowerDownWakeupInit(S50_Type *base) +{ + status_t status = kStatus_Fail; + + /* Enable GDET and DTRNG clocks */ + SYSCON->REF_CLK_CTRL_SET = + SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK | SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK; + + /* Enable ELS clock */ + CLOCK_EnableClock(kCLOCK_Css); + + /* Enable ELS */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_Enable_Async()); // Enable the ELS. + // mcuxClEls_Enable_Async is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_Enable_Async) != token) || (MCUXCLELS_STATUS_OK_WAIT != result)) + { + return kStatus_Fail ; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClEls_Enable_Async operation to complete. + // mcuxClEls_WaitForOperation is a flow-protected function: Check the protection token and the return value + if((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation) != token) || (MCUXCLELS_STATUS_OK != result)) + { + return kStatus_Fail; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Kick-off ELS PRNG */ + status = ELS_PRNG_KickOff(); + if (status != kStatus_Success) + { + return status; + } + + return kStatus_Success; +} + +static status_t ELS_check_key(uint8_t keyIdx, mcuxClEls_KeyProp_t *pKeyProp) +{ + /* Check if ELS required keys are available in ELS keystore */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, + mcuxClEls_GetKeyProperties(keyIdx, pKeyProp)); // Get key properties from the ELS. + // mcuxClEls_GetKeyProperties is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_GetKeyProperties) != token) || (MCUXCLELS_STATUS_OK != result)) + return kStatus_Fail; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return kStatus_Success; +} + +static status_t ELS_PRNG_KickOff(void) +{ + mcuxClEls_KeyProp_t key_properties; + status_t status = kStatus_Fail; + mcuxClEls_KeyIndex_t keyIdx = 0U; + + /* Check if PRNG already ready */ + if ((ELS->ELS_STATUS & S50_ELS_STATUS_PRNG_RDY_MASK) == 0u) + { + /* Get free ELS key slot */ + for(keyIdx = 0U; keyIdx < MCUXCLELS_KEY_SLOTS; keyIdx++) + { + /* find a free key slot in ELS keystore */ + status = ELS_check_key(keyIdx, &key_properties); + if (status != kStatus_Success) + { + return kStatus_SlotUnavailable; + } + + /* Found free key slot */ + if(key_properties.bits.kactv == 0U) + { + break; + } + } + + /* Free key slot found */ + if(keyIdx < MCUXCLELS_KEY_SLOTS) + { + /* delete empty temp keyslot; */ + /* Even if KDELETE is requested to delete an inactive key, the els entropy level will be raised to low and the + * PRNG will go ready, */ + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(result0, token0, mcuxClEls_KeyDelete_Async(keyIdx)); + if ((token0 != MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_KeyDelete_Async)) || + (result0 != MCUXCLELS_STATUS_OK_WAIT)) + { + return kStatus_Fail; + } + /* mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value */ + MCUX_CSSL_FP_FUNCTION_CALL_PROTECTED(result1, token1, mcuxClEls_WaitForOperation(MCUXCLELS_ERROR_FLAGS_CLEAR)); + if ((token1 != MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClEls_WaitForOperation)) || (result1 != MCUXCLELS_STATUS_OK)) + { + return kStatus_Fail; + } + } + else + { + return kStatus_SlotUnavailable; + } + } + return kStatus_Success; +} diff --git a/components/els_pkc/src/platforms/mcxn/mcux_els.h b/components/els_pkc/src/platforms/mcxn/mcux_els.h new file mode 100644 index 000000000..ede8bf173 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/mcux_els.h @@ -0,0 +1,61 @@ +/* + * Copyright 2021 - 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _MCUX_ELS_H_ +#define _MCUX_ELS_H_ + +#include +#include + +#include "fsl_common.h" +#include // Interface to the entire nxpClEls component +#include // Code flow protection +#include +#include + +/*! + * @addtogroup els_pkc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +enum +{ + kStatus_SlotUnavailable = + MAKE_STATUS(kStatusGroup_ELS_PKC, 0), /*!< Key slot is not available to be used as PRNG kick-off. */ +}; +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief ELS Init after power down. + * + * This function enable all ELS related clocks, enable ELS and start ELS PRNG. + * Normally all of these actions are done automatically by boot ROM, but if an application uses Power Down mode + * this function must be called before using ELS after wake-up. + * + * @param base ELS peripheral address. + * + * @return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t ELS_PowerDownWakeupInit(S50_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _MCUX_ELS_H_ */ diff --git a/components/els_pkc/src/platforms/mcxn/mcux_pkc.c b/components/els_pkc/src/platforms/mcxn/mcux_pkc.c new file mode 100644 index 000000000..8beef2396 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/mcux_pkc.c @@ -0,0 +1,68 @@ +/* + * Copyright 2021 - 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mcux_pkc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief PKC Init after power down. + * + * This function enables RAM interleave, clocks, zeroize the PKC RAM and reset PKC peripheral. + * Normally all of these actions are done automatically by boot ROM, but if an application uses Power Down mode + * this function must be called before using PKC after wake-up. + * + * param base PKC peripheral address. + * + * return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t PKC_PowerDownWakeupInit(PKC_Type *base) +{ + /* set PKC RAM to interleave mode */ + SYSCON->RAM_INTERLEAVE = SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK; + + /* Reset PKC */ + RESET_PeripheralReset(kPKC_RST_SHIFT_RSTn); + /* enable PKC clock */ + CLOCK_EnableClock(kCLOCK_Pkc); + + /* Zeroize the PKC RAM */ + for (uint32_t i = 0; i < PKC_RAM_SIZE / sizeof(uint32_t); i++) + { + ((uint32_t *)PKC_RAM_ADDR)[i] = 0x0; + } + + return kStatus_Success; +} + +/*! + * brief PKC Init after power down. + * + * This function enables RAM interleave, clocks and reset PKC peripheral. + * + * param base PKC peripheral address. + * + * return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t PKC_InitNoZeroize(PKC_Type *base) +{ + SYSCON->RAM_INTERLEAVE = SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK; + + /* Reset PKC */ + RESET_PeripheralReset(kPKC_RST_SHIFT_RSTn); + /* enable PKC clock */ + CLOCK_EnableClock(kCLOCK_Pkc); + + return kStatus_Success; +} diff --git a/components/els_pkc/src/platforms/mcxn/mcux_pkc.h b/components/els_pkc/src/platforms/mcxn/mcux_pkc.h new file mode 100644 index 000000000..3e85714ae --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/mcux_pkc.h @@ -0,0 +1,64 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _MCUX_PKC_H_ +#define _MCUX_PKC_H_ + +#include +#include + +#include "fsl_common.h" +#include + +/*! + * @addtogroup els_pkc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief PKC Init after power down. + * + * This function enables RAM interleave, clocks, zeroize the PKC RAM and reset PKC peripheral. + * Normally all of these actions are done automatically by boot ROM, but if an application uses Power Down mode + * this function must be called before using PKC after wake-up. + * + * @param base PKC peripheral address. + * + * @return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t PKC_PowerDownWakeupInit(PKC_Type *base); + +/*! + * @brief PKC Init after power down. + * + * This function enables RAM interleave, clocks and reset PKC peripheral. + * + * @param base PKC peripheral address. + * + * @return kStatus_Success upon success, kStatus_Fail otherwise + */ +status_t PKC_InitNoZeroize(PKC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _MCUX_PKC_H_ */ diff --git a/components/els_pkc/src/platforms/mcxn/platform_specific_headers.h b/components/els_pkc/src/platforms/mcxn/platform_specific_headers.h new file mode 100644 index 000000000..b15e72f85 --- /dev/null +++ b/components/els_pkc/src/platforms/mcxn/platform_specific_headers.h @@ -0,0 +1,27 @@ + /*--------------------------------------------------------------------------*/ + /* Copyright 2021 NXP */ + /* */ + /* NXP Confidential. This software is owned or controlled by NXP and may */ + /* only be used strictly in accordance with the applicable license terms. */ + /* By expressly accepting such terms or by downloading, installing, */ + /* activating and/or otherwise using the software, you are agreeing that */ + /* you have read, and that you agree to comply with and are bound by, such */ + /* license terms. If you do not agree to be bound by the applicable license */ + /* terms, then you may not retain, install, activate or otherwise use the */ + /* software. */ + /*--------------------------------------------------------------------------*/ + + #ifndef PLATFORM_SPECIFIC_HEADERS_H_ + #define PLATFORM_SPECIFIC_HEADERS_H_ + #pragma once + + #include "mcuxClConfig.h" + #include "mcuxCsslAnalysis.h" + + MCUX_CSSL_ANALYSIS_START_PATTERN_EXTERNAL_HEADER() + #include "ip_platform.h" + #include "ip_css_constants.h" + #include "ip_css_design_configuration.h" + MCUX_CSSL_ANALYSIS_STOP_PATTERN_EXTERNAL_HEADER() + + #endif /*PLATFORM_SPECIFIC_HEADERS_H_*/ diff --git a/components/els_pkc/static_library/mcxn/libclns.a b/components/els_pkc/static_library/mcxn/libclns.a new file mode 100644 index 0000000000000000000000000000000000000000..6a6718d7e22d5f1208c5a173f34488ad69373c7b GIT binary patch literal 1856008 zcmeFa3t(KubvHh{l2)=T%d#y%HioPpfQ*s#mTdw-Z`r{QSu)@dlJ#n}(k@=@%DXE+ zC?O^_uQW}7(iBsYP(lbKX#;7TG;JIkN)pJw4VX9$AxY!3(kGpg4 z-d)|@h5Vu4j&yhK%sKO$GtWEs&Y78Im-yp>(7P%dy=K$gvA(UNrKxr8dat*Mlf-XF zTN`(^GAH`y()WHVx9g?{Sm|f4W2H~L|9{n0w(57R?D8e7 zY}cT;Zn}n*eag$q{^kW%cH-Yy*?;^q^UQmQc~(6muFaP)4_%>qnCC<9XP(biG0#6N zO?MN9jjbB!z#D4)V23!R!P^LrL6L+|Hdkxjk3zqd)VAF zPO-Ti3)$SkXT^102b+6WwYa`?lFj{9CBLfNFS4pFEvzbZE~`4YgH?U5n^is0#;RV5 zvw5}8q+cx?*t{(sHZSyBHt+Uoaee+HY~GWM&HKffteRcOs?T|ZRj(ft*LK{~mAH>p z-(JP4Ket_6-}(is{@F9E`gdPu^XqU#75Tl}MwY)Q!|TXN1)wq*SXTQXe1 zmc;5ZUw7_dOX&K>b8N};-(pK`??bQqXDLQ$0jEI@nG+Szds!HN48ESC#RBKqoeU)BB8PM zh7UT6!>r0JDl_P&6(;FlxefuV3 z@$}LHW#a@<2B&tV#bprFC|yDSsE>CR;p@_)8m|>y3|$4+VEm z1rvbXny4qCjlw4d+Y7 zk+hyzbSymHx5poua>BSNW>a_qV=5l(iA_wP>+Kop(efQ-Ve2nSdnh<&W*4pg%7lr) zt4AQde=;e7xyM*I8cu|CA9$EJCgZU{>RHDFNiUxtRnf19-NXAL&1W;7atYt?E^2zQ zC>2~_A{%+YhTIhykHy2u&_r)A5r~H;lQEP%Pyyu|4XS4~2_|C8#ve4E?J54g=y*69 z6tZC;po!-rKt0yJVP8+rW?yfgDjc328Mykk%*Hj~2#dJPSlQEwJj^Lyh(Bw-fWe$E zBL1|hBfKs3M|h@JB9nhwO%l`$)k&|!=!SjU_fMKiDVS((StpAz1ATogMoG2lvjeJ^}04x+g_6TH&GFNsTMB^R$yieWy;|^!)MCxHx{m? zFgRWoxk79o$}t300Q3lXges&UEY&Wpx5!hR4CR_@L0F{ARuJN;o~p%o_40K`!qL&- z=y1Rv@y9n$MbtQlXvP}~yu*``Z~!l`dxAVfs+YBSno!uyv1qb)gRf^Qz9-ny-rl_4 z2gX5vShY$A!P?r^IS4e`JKW{#8x?U3#>0DL!?ugS%sVwQJ1fcH43u+bgS;vj4#xX> zdVC{se>gfBi$w;TJDTFnv*2eAmV0E${34@Zxkk3WC9jl;V7W(@SIXA6%PVE;cqPs;vi9b@dJq{b_sH@|86tCB8xz66B>MYZj=NwjfTPrK{`D<6Mj!&@ z5`ptRLP|sd97lkzE4LKL0J%hvTM7_CZYgN*$T0;Xfb$gO(oa(v;MF~+6v*Bo>sZPd zmQVz_bSK2$-qM^~8OQ)e7SRY3pZ9}tyyxu+Zr>Xd<5%^e%1jnCIo2am-)L{buf~jn z@mMkzh(%H#AJRD0IG6^47*^VH_FplmNu)s#0berl-6pvqHnBa{HHNPw#>^F@8H|Oa z$(~R!uuG7(sF!>al|u8ZHnW*{1RYZ}QhsPIuVTO<9MU2vhZ*z`llih%!O&v z4+STK{v;>%#-_B{Jd#-GE}szYYTsa!Z%};_GM9-p>`-uY zDiHMTX!gCQ*#`uCAQ;p#GZm?<5Td}jgud-Dl?@Il-6UY#gBKwAu!AbQE%bZOq49=8jZF7Q^Fg`dES{4}u2_FW~JcEM~yj;nKs>MPx zg_<*!2Yd>##~%qyMNsdCH6Afzpn0SM36g5oz5%KbGB)5PhSN+e?wsA%+EUCRYLN$~YS7gjx1W@EzV0*ys}EinP5KAkvW zG~GjJgGk<-`fq6D$8tw77p6r;Mjb23@vCWotLgTLmv!gkvR~(Io=nl|kuSp@P>$r4S#i<}LAtb}MR2Jyj~;m4Qat8|y-lP#q|DtNJy4+ulcJPO zBzZvOB!jGVP%5Lso=B-^qC(FSw-!{+@@S=%OIWkOq8L>(%lZ*u``*4$pLnlG#)qM{ z6G(2}qzS?4SNdgpx4fm2geIDgx`{o|szpC%yzgpg=>guOb#eCHR!TxsR2nMh=nwBp z^_&`!q7)GHDdI|hgsO?As)|BN#b5&Avu+wvifvG370O%9v#Ga2&b2wbFF498G+xf_ zOEx8w_;`@cv_+9rgA0^Er-Yn zFip3Re5fMmvUm4v?&?X?cFN3|LD4{sXLAmyihI_8K3zk{jvMKar2wj^?`at(ysfz= ze9c)W{L=DIc-vK8==EgC$yvk9o~QXjXu0bY!kW(_oY3|lT-R$#|;4fU*gC z*-)UmIv9_s7jqtBI20bE*TE?~Lyg7*{_Rj0!h!60;X^<+jO5*_^yV$> zt!n(p{l&{4!20$Wa}p{5y@#HyrM7EtA}z(re+XXyqNZFT z3cdPm!|;&5;qm!LJtE@hn+jkE9rQ=}$8Vo0xi<7vkB@xg^nF-_(Hq_a49apVynG|- z562TpON#nZA-5XycszG3xS;wn$6$u>@mlpBT?~yudGn!~FQ6&jiqRW}K$EH$(R_Sy ztm=y=Qk77I#{f?P$|o$;;78SMn&zc*R+YyJN<-z35Q_$Q7Itk|XalB?cx=d~)kA~3 z0+_U-z8b5WQjccxrhX{RlPaD{F?h&{dBlW~VbTvJt#Qer*0fLz(tikDkt!YX zRxiX?3~nFVuE7YwA!HgMn306KiG^a_SO$a-5B?}$-nL6mfneAaP9`J4Og!Rk%mCRQ zgOr+Ff~-SWImB1MS!L1Lbhvb>1?Mbs=}bCYnsj@^$v{XX9wRH&?eleG<8pzZN-nLd zqS_+eBHw)h(j4H?g_HY-lX3mgC|N8((l;Fn>vw}jgOpr}U}OyQ@s>!ZqUoWd0aba- z0!9NHtwN(K#$u%{vG{~PLiau;VgFQ=zrW$FO|BkR-LDWQEg*@Z0-2&s;}nT=#;X#Y zh1*!qOA%?qAuUl^)1ab|GsIo-xPQMYeLbyM)kn(&So9j%vK~+7VR| z7$Yg0>{P-iUa|5!3u8F7SkMWsD5Gqglo$BMh3*7Pu#Kf}O0KTH;nW~fPvoEHDo+n&iWlId} zS#z1rj8UNVPAKQsyx*WI8Pp86QJu;Y*j?7SBd@TRwZ~)3SRK3QKqi?=ePNBqdD^ zk|!45(+F>KGfj|a#b%}ZMlv(-cP08By16ei)Ar_xED+mUwzqC?OXHBD^H~v1IIRLD zu*NxS-7y%_GoM%TLB(K`>t+T^b|(^PtwV1L2Chx5R;8(;)}AJ+0a{sXq_eW5$(LRe zpjsI=9^F(6xCiEnpipRAfJ1m+N?VIX^~X%G6uYJ6?9tbzQ(z%jpH`yy=0kI{y*6G# znXkE})e;Hyim0U%L1V^I3!F|AFfFr!NZmmTpBi%x#$zM&X^2Ox#fMKxk_FAchgOx1 zCR5a8i6ad|@>!c^CO&K0%zSBWC>)6d<3s+DaFjAjlXtV3B5DV|L~!L{i_AQqw_y;C z%^CvwgThR(ghD$>eYKH$jQIQ!j4h~3nw%2aBvK?rr+5CS@zSY$F~Y|aPrX|z-!Z67 zbVVWtlp69XIz7xS@c1MkhH^IkNi~bJonDSMrUG;KIQG#=d+a6>5&0Q{sy04@30U1* zeXr2`QlB+ao=_67hQ)A9{o!2>6F5T7AZFOdE~C zU%*5RwqgHR%qQmbrjlwp&4x-Nmds)Cg^70L&>4LF*cnK?)$WMJO_T(GhsAyg^p>x^ z#PVqAqXK`9K}!c!i$3}2fjL=pF{Zkg3M+{Emrg6q@;TEW8(jmOr$UV!4JtJngK?|+K4bU{(UwovY(e$H zryN_ULCPdG-Voyy4*lUclxMA=^x0=D7MGuc8ZBFx&bEVT`&zkysds0kwjCIM>sS+O z)cyEWf!U9$rP&7^;bwmnszjtoWhT)sB4!`@&Tsaije1f(+U_NoGZ%Z8WT9dQk4#kT zq9SGs0FsG^Mid!|v^$8}K_w#quP!L8Obl|yK_@3j4W1@Xw3zj+2rNSBqz%Cc=FC%I zIt^1ylwX;NHi;o!4&&uBZ4r42%EYHyq--jd1?A>I=_w^B8u)S5vdux-QY@U9(8M;y z#f3w+tuGHU$6$z`VioE!8Q3ftpCLASqGkY)t3J{>gi^I34_8Cs4|Ow8Mz&cI(P5Yt z2if4#%5*~l2mC2!p~SR;5_14nZ>9ut2BZo6H;b??BS?Q*+t7=vN9Bacu}wmB`BF>G|Ip(s6osS z+EhhVU!pH^umPPlOfGSmmVuZf<1;b%Dw(M}%HEd1bGkZDtl~p)~ZP?<{CHhKjZw zpQ?l4BQ0$QEa@p!G0N|_vp(Pizlzyl&lb1Alqq)6W(_tomXUwFd5V`N(woi%X7FdP znU-|ZI|2<5F@)J-jz0_ItRm=o&{BIeE4Y~-8pDpc)B4E_ln83NNan>04(obFQI4d{36{bcavUbcWmTjo4 z@nqC1&Kip1(e#VWa`6{@|76%VpxQ87`VUnC5n4mgy()pvE^-nE8$#`4C`@mKmKJS6@SXlT;$xJ>swiP zr4E+<(!qHl7QVMwn1!bevPr8dJrL9Z0nNnhp;JNW zQxZM6h2D(WpPnv!fw$S4E3=rrgkFbG7ttv6c@Z;oDIf7k5>uPq18JUvLtD~3c`eaY z9;|@`T~3_Z6O9RBd$O8zHC1QRB)FkdksTm4?P||QUyw;$dn%&05NYNFGnpDYeAE=C z)z|uB!KcL1r~k~sQ1pC$&^E9!pJoYT_?s)3HV4O_#geO>IDs{aW3-IJw$xYZwpROdwmR0gvcn8%D$NYkImH zdbV8k?&03c2Zwrwni{&d?AR{I*F?kdJ(wmK9^D14Vbt$L@S4duG7~|sNyG!!pim|g z*BBEL+|O{yLrm5Ln9qm&^(FS>go}y9%9SX)DV$Ei3$KIeg|VKkOe@Z{Y~?5mPx=B- z4H$t0a$<##H}z9e*v76QZ`YRLjozNdp4F?p)TF|g&-GrpZcSU$n&vev%`J^rwYGRM z3*$xkvWDI*y?xzR3|!jmZRqt4ZSV8(yDb~HcK5Y)(fvlA(#G^$XjHk-h+Jr##0EA1 zok(b$je&_om@gniwed~(+VR)i7>))Uqw>6MG;%ZVurxbUP+%HVBnm*tKdhK4$vbLo zrX_z2ynW>z7@y(u54+DlfjP~*!_!MXc;Dh0`au}UG~`MS|U5Y&jJ03q=Gu^pX%p4MA_i*3fm{hK9ZV zI93&pCw$P!_XX)Z-~@c3Q$FrXOikibS0ZugV6eFZU&I;$lT(*sMj9Wr8aB7Ku8GEc zqlroQ3mx=JBYa6Y++*OQ9hq>O3{6dpP|%44IS~Y0*x(`Jqoa6)&lK&EGae0&`uqWU zm4Pq+9IG~e!d!&c*~d8RXEXXhXM996K1l)}>6#SpO_`BnBiCZ*sYIg{)Y}m0$|qDT z_dsc~$M89In14#$6vo!V*rlr%H}D*dghzaPpUWX}R?(3@;&ci3{a#y*#yriPEqO8JGQC?9|F{h%k zVs3d=MfG9|CJlYi?ppK*2g`0My}9HT_eWh#@Nkzh)<$-TIcn&u`}mR4JtXF>VqIVJO43tS6J>s*UnOH0lzy~ssz<1;mL(N}f1yVOOX|>u=7mx zg{%$kD-{{xFEP<;+2wFwuhEB1^fTEA+;xVZhh1yjlYDh-KinOLpNDU58+OQ@vwg}(U-HA;Qoc- z=V8A!?kW6AHV2LQwBhGr3st9sJSjo1wG8e`!_UJmH13IB&(_1e)bR7LZsVTl7qV?| zuQB{Q>}unl=ohgt+|-W>~Q!_UK>HSUSt!F~q!X~WOMUNr8BzK;DD+?B?|$dh`0^8CA)Eih=r zU(S|mZklx_)5?FTUlqOEdW(CTEFVR0*XZYIc=UX2hI=k9FYam9dI#>Qzdv8PuZ8EAgnn!$Er8VcHW5q?k70pi zFfy81H-MBde61#>0qlayRSA4;W^Xt-ce~je8VB6lta;G9PI|93akn%{Z;&-Dk`@)^ zdb78R65~!2yNa{9+3c?(r6g$Ztt!@Lb4puPw9V$E;#eP%rebB9@sb8gN=GQ0QVHIa@gm$i;ph8{ik+6QQ#QQ@Yq}?Lmn_YvFG}m2eO-zDQMI82 zDX9!#Ej+zb_dtz8<5u3Aup3{*?7v|z))FTz%p3MXi!g!rU^6e~r9`~_5&yU@AMiI} z;W(0!E<4e%X^|O8e9J`4acuAu@vHpMMWdgEQ^Xp_&k&l8U+|a6cvq(m0{*JQQ8v`*;G_C%3Tu>i!RfhVf$C`&HUi)RrXJDp$!J<$J zl!Z#Tve4u}isth6PXDB9kSh}LFs$Y#%GR49($QBSnz1ybW_`fC&_ipMXt%V72MUyUF+JGa@PUw zYHK?KuBW)#(5Pf(~%j*)Du;CyUZGcfkGxlTfsQHs%3UwWKmb4?F4yG{;FU)kmD z=d!sEPzv0OLeEDYfBD9Rl{<-R%k=d_ul@4C;Z({Ogq|vY^#sv2O$Xdh&%7SrR#$q& z-GAV4ML#<^bneKbig#{kF?j!z^Zvzje0S-QzUi+wk=j-N%nMzml=loVGFQm8yfRo3 zI`;AbEUy0Tag}QW)AJXIJm-1qstPRwUdi`szD7!36`wCZMVb6)!#Yo>b$Z0z~Oo*mYr@|^sJJZ zh1{WMrMg+g3AVgu#j)wvTdJD$Qtz7H+RRfaYuIs=^_(u3QJ?yzzb(^;TtE%HBg$5} zcJ|KvVp$bpd!>o;L6@_C`g;p*9}~4rDFg?>>bq$W2 zd}g-!7sa@b8z?C6in{)pOO`E(eW<(k=!Ti58WArhXSq^bg^N_<*qi)Y;TDnET0Cwc zhvXCDm>lU6&O$Z^s7G?0YW|UOn=&+s-?iw5gG%QQbK5k}PP%{Gz{XTJDJo#*9R}(N zTtfkq;Z@{@Qr0}Od&GP?gMuB02c7f@$jucEK_~qIa=(M@P6kaA7`V?Pdns}lM1<@T#wN&y0z{PTF6c6ly@|0T*~kpi zg(KmvBOCNTAo~odV>Hazjne-^WS_;@ACe9JTc!IpvcdOJvXPk|Bm3Qq-9)7e!PpncMt*;pY!uF6 zvXS3^OZEkf{T{iB3l8titIoa*d$srr%QV+{%Rp)h-!oe)WMRm$uA?tW~{#Z2% zt5Rak$sdbkInqy-?~Tf8OW7rhI4c$8(+Ycf%(B?Xbr#7K+-$ ze~t9N7B(r@UJsl64@iGf3a{KG6tl_yT(}A6BJ%G-dSQ>fld*NMiB3x2MBf0L=v-kN z^ifFH59X9@X(pA@Lc-z)tulK!32zgPP2giZ01!Zh*kk^ZD0P416N_am?=KS?o~{J$do zA18mrM+(v8|D^PPf&9TwiqPawO3ozT4Ea-fr2p@ve+6Wq@+Db_zZy32*ONbRn9H5f zfJ%#3z{y`OaLeB-%E-o8$U`>9F&M7#@plE;=#PDof*8Jo5QC7DE6&e#IjjX_N0YXwry+ zk5iYBjizKZ)WqxzYJfo~ZdncZ?gkU_@wz5$YrGGkuAn8P z8Ed>RfKSD%9)*N!#e2meUQ>MvkJoKr+2M79&xw53Yk0hEWWf7~L%b(7Jl?i4;5`Sv z9?-1Dntx}bEvo$EZ4&`1a9Q(jHTaz1MKwI$wlm<}0KP7(aBy4YJF4OFZyp)&o_2^= zgJG6RFYjA2;CaE<37XYd<=d&@EtSl6`8NqZC+U4u!=tw^GIn^6fzL_(`yUO@%hBxd z=B;*CzJuUX`L{d^-cIm2k?&p&Z)Fy|FF3^em4-*dAToCOciJId8-~&1Y{|UYwM6{SgaL>{FHe<|IBcJDdED0LneHxcO-gqCzbTme?nn&TGS%h#7@4nu2@@Ylv-?T^31s3Z^0{-??5S}O7x}IKP%m$^?3M~>jm(mrvj~1=pwo-DivNglPvOsF{{T0=P%HZPjeDYBz+Qm+TZW&9{kw5b z^i}-jS%oe^o18~Y&@iHnmdG$_W$Yr&O}&6JR1fGS`zY*QT(q+EU2uO8_np%HKDhC{ zg(g)veJ|Ya0N$0-{V}+|4fmLIe*x|(xQC?sEwnO}x+F)-LitfpOu;LoL;u<{j>O*~d&3sqL6xZP8 zw>^Dvvu`>PLEHUbotBVMCsrx7=UY>iMtk1ji)-+TYw(Jjee>fxvZ<=)+rIdg+rtyB zd93J$IK?%1#Wi>VTK&ZbBn7Nm!XUknbyGMFke@+PfCR|ELU8E_rGAXZ~lGx?YIDs1b4dn4y&j5nxloGnvrcId~H_= z)*zLf9Xdw4q@Fs>+^-yn*Yq6P*?Fpj?btavP`hgKaNE(^3u*P$Vp@HLRdcNL{7_ry z1-bgF`b60$O7Cs)@Am(-zip)RRE_I!z_q->D^_BORbkyTf9jt+Qd_^yz*_Vy(ZzP* z^G+z-m7#k7!z0)FdtYJO_3(YuBfHyp_)Ct~uByGz{XM=K>|{oa@oW7n(=e{t)<$dI zcnZ!7U4#@&4t(D4THXtpJ>J)TNog(Z7c0%qrL>kIt!4EgkFl}&q7&dPb@@-0mmVtn z`b)hZN4j;XduBSiCXbv3CSg_d6WXfKoX~e=&Yf|B(n*LvD=+_) z2Y5C8i#c9BR^%<~zj@@AK$$5Y`)1}gzjCDE*QdJX_188iSyzy(d=vJj5DPsf(d$ki z2L@3d6}}grob(*3xR>ND|CErp2{Cl_-!gJAaMQRsj{fPtTz2GFr*6a)kYTJV&@c~0 zUNwASn9Z*wbIT28!SAkfGyEf@ysJk9`7DH?DafGaLRkq)~0oY_k@=_G4XvduWUu1usyLmd^oX8so-Rjlo~M|FRjjny<*rH{NKjry zniDRU*M&*k`LDmm+(S+7p=S3`i+iZmJ=EqNYIhHHxQEudht|1=)|U)5H{oi=)q<-P zR~xUQ?pm=f(1ofiE3dS9Mb%vQeX{Fx;q& zE64`D19na^oMnmuIbjl#aA0PY5`=ccloOK&N;Rkd?;!dzzb zdvDfy4@y_#O5TOCCfHOl$z2PZ+?~?hE8P*;m8ICoo@{iUcM~1e?Ovk8{sQ@l&d?s1FocmQ*{X*~mEVd#JW&!3qH4kqqpbT5=4{8@_jSwVDEORlhjdIVPf z%t9Y8S4q=N%23(a8Hgt0ltkj2wqYb(h;5kj5%3Xski5tmZm7KISi}%3 zBOkz}^W6x(3J6Smyv|5IYrMCiy*r8bo8VLNQcq8Y;jCr?~4xcey!ml=?0!Py$e=2OYau& zsr2GDBi{Q#bkdGKqv2sllo9VR_%=$qZduFYH4X0q$!J%;)#$J<*Ma1{74JRZQ|Vo$ z;e8eNC7ObE7<@Zy@V*T{y?s0ezEkjX<5JH6lJ7V!7cONUMP^hfhi3m2_d4DY@D0L` z@ERl^;Z-)aHIcftVP@0N?pUvmlbZc>sOK;!fiX0+t4Z`cHMGsDgKvapc1E3RF0}rm zXE>eybSH=@zn5NrNMk0Q=`WhxbJ!8hO~rXkbJJ-zRH!LaE_MNt9t&Wf#6|JljEi(~ z-$FXHG{2friI(e!niXB4^9jXRb75vV41?f{DwqC5Fta9C@z{gnu?J43pENb22sJCA z6OhZKl#WnTxh$$&M*YL1vrqj-melEB_IKSc6!Zp%8@`odT z7&y4IbNbT@y7CYzXPLG|{Yx#pI%F@PH*OIjzbD&%y6LT$Dr=9Zeotl?_NCV+Q_K zV^ubYVpiwpYW7xR#vGD1PXWa~?UEMZIKFlm|vmbm^G|JGV5t+5PQu7`ta`2(J z45RL8LQm%_!90+{Hkfg9m4$B(_$aK^jKV{o%o+rrnru`4l#kY33wLUKDxb-|4VOMC zHwnHS@Uxmj@KE?fds4$w=^?z-E=QM-jyc-pXkB{?pK+Ug4z2Wjia9lh)=oK_=N#Jq zd%GMhN7m7PGN=di2e7ai*_yg4@H7aGkC9RZc=Lc zAGkw?pNABb4O4osIbJK{k69HKp%aguR38HYuXbi?n^zTEUim&mwF|Bp8fMiY%KKVb>!OQTpaZ z!XNuLX)(4T?E;XtPclzy((Fnw6E(}Z%^bw z+dBej)a{W3Ha!Z){mI~FeKMZcm&2$xz;zUfAqqM19iEbM}*OA&_@i`k0+>;Nm2F-g%ey={nCc zNdIn~KTu)S7?KS7u$nKO~%zDN1y z9H|i&C*j4x+Qog3G!4Q0=lqJ3@Ys6^W0eAOQ1bArQq$c)lANX%QBXjm1g$ zc+mFk8Ka1T>v{T+CjXL38`Ts9Wggh%50x6*@sC+^uyXfBWCMq<1_j6(a$hKS7lJ=mdcacZcJf~>S0%&$o#aL& zd^J7zyQI6DZ1C~2I7c2e5Bg^EhkJ{p=aPp!Z4?fMrs8Phk- zwlSa}c?_WE9K!F~(K&|C5pw?PzP41fkVOp0LEF!UjW!w8kuPrp&YpyNWf`NnD zNSF~9$%MYrJY0i|8h&UHHvq7S3;8LPBlkKD~%=a*{OVN4NZW4_orLKn8 z1hjrrT|+D9`_>j*QAH5342i=+_PU`{n#$r>br7|;+h#Z6!O>cosW}s_(12Q8W zUuA|B{|(3t)K-}p*gb{U3`Fu~Dc4cOX*^%ZrY`Y>U|@$t2$vf!M>9GOK@5< z*`VJg-4DX1@SlU-1p9GG|1SBX);~-BuzyAV2v55nRjz~@2JA+3g=fNUg1v|Cb|bdX7=qmdn+^;kzMW))kJMBs{tpoyw!X^|T%-U8F20iyZn^Rap7Q)r z>>(SOjXsz+o(i&2u1GC^gjSM`thX8}5<3G4L|l?ce9+rWGw6|_^^`KSxzRCrkerkP zGE@hs&)~9?2h1yY&SHTbAJDWC9o2bznD zmuxb2c>UmWg7-%n9-ge+5Z)cQ^!oSb;6pc_W~_W)1z&d>7i0Is&y+9Vqj)G^Y9+s2 zye_Y^&3WDlzIxyg9(o>b?C=6!XLz3gpTa};!Hpf>H^FzYr0bS7y|05$;i2hqLwG)1 zdOlyU%-Lo?qu^8Z09A||JG>npg@$LXe=+c_lXTs>9}d0#eHMJGJkHC4_q0R2atNjH@E*X8U3weAcd4Z7mNow( z;8W$hN-`3jHNDq^&q;c}tjUMr3^#UoKX!;$yE2vD1`W?zpDzKQll1NfpGt3|hWAz6 zmuQKkN z!(PDs0$gaSoc`ail_AY@cM1%3X%4H=+*CX0Y*xY&#>39m=p}e+UkG=LB7?uhM6YID za7Q)zMiae;?ST79jlR=FU&vx`uQB{QY_D-ob-$L~40md*=F#qnekS__=*!Vagz>P? zn8MdtG{MW+H#Itql%LexGzR#g=B9l8jm52NeiQ#9Y829td$q+qU~!LF+zGf>Kz{1S zNR#`ca8nzjaTvKDg8O5T;VxX{ejM(nKpT_vpTZr({ngU_R?_?q?%(W>`p1J4!D!Nf z4mi$U9gPH`3f#AEG8Rwv(aJ$>txF=9%=utkvHcg`FuF^H?YeW2<`HX`NI*WdyG%{ zw2Pm78eNq2NB-kJEk0-P&918MGOj`YivxK?IA5Qki;#((4$vYg2N;olt>I0sJ zkGN5MSac2MWH_it4gcO?B$y1QX@eUDZb#WTK~-UJYFB2Wq!d-fZ6~`U#r@if`?VGK zYukedk)z$i_{np*s1RtoRSEU0yaNX(V)49HV~eWd!9>35z>(s9ZPqPL@~p%u)vEjf zimKw)2f5Ux$}>xaA{QxAeBv-{!5OQ9;#hc_Uscc z-*|?rq2egJ(0!b%r=J8OKbp27w8l7^cJ7JQ{;+=mKR%WYkDX&e?wbCy=1Dp@cA(oYr&k_0)PE<(qr+mKS$6Dn{q4t2H{Eya zblrhI|H1KF0_HfnXa1@S2glyh@axk(kkB)a4!rd=hf4cz?`LMoc3Rf~zQf;F8iy&GY7T|V>E z3u;c4%y-`njQ3U@^`75!zK{m-?cLFL=5dkNBwfvM_aV=pcY2Zkhgx`ES1sPrSEg|w zmU~=xH}_w5nou$78C!#$_d%`*K9)Ot+p<+BEWCUu)|kw!Kt?$JrZ+`z_MBG+c)UYP0U3WH@* zNedbQT&Zh0O*q29pA`4VlPfDh8GtJVl}e>3(76)Me0gvpChk`dKj`O^4LVl}!E7p} z1+%td4FEt$J_^j03ZMkmL2j?u_>Usx${hgXN)*89Bs%2kAsce^lMTF$WG|B^3qP;xpYh^sBcex}2C1x0^uN>=4iG{lMrs_FEn-0y4HNi$1 zutwNO26w+py1S+O8rYR+L$^!+yQKdY$R8kIk@O!+`bpS?`#bUno$E6rJSl)QEuY^AhyK*Vyc8l;Al8tzp z$VLTxxAY$+dl_TbN%#F^FK6saWP|TXve74;knUfQjlKa-VJ=q%?n#bn*d#|CY?ALH z@`oHv~Qif`=ok0eO zI3$typ0Hs=)C`F+%xT>1ga^rogm6Q(03w+1c7WlxdO*RNre-~aw7yE!$6{8(O)@I8 z5xI1}a%grl?uidD+{D0lHP1ZZRwAs0Q^$J>wT9=dU^DIqEPVe+wM+8o7WL*j-YV3F zOLPW#KMI?djdTaWNBKo^DSs-%Db0;rHbs1hfcSVBOWPXnO zd|mLj8f!WhE=%Fj(hxFsc+0^@d1^IQys(Bxa+0yb+Ydheq!ld2uNCh}4Udl~GT_k} zsGALx)QuJIyydC%s_JSdUpx4Aq+pCYE8ZV#c<8vfvBUcW_?*3% zDjV0edv!CbK4*Jdb1M%pyFTYn8hJd1KIc{v{Vk)<2?Z=&-z%lKsVRZ6H5pIvH0yZg zq4jwuGAC7(;)G9fi*CZhzK(l5VGQ>(xL<|~H3-G%VZVf}3~7D-hjPFst7A$u>}9>dSW0>(Yb zTg&#C+-I=cOzyMU-Eh|$ejaw8aZllwu`j|+3$KLnu&)~TM8AN23vL?7DEiaJJ<(UO ze}?-Z!w>n3`>$*6Q@Fo`+7CA#_Fo2#!nZTL0J1L_ejc{K;3fJy>1EI`CG0ZR2zQ6! z=V9xNd*UBpx)x~(UU#lE(aYJm=9U8zqfFKQ!)Hi&l>0o3`(cawFD>r1G7c5~QH_4B z7C+U~J#b%&>mJ;b)++5!+=F}SdddA)aDNu}JEi++xLbj@N4oz5?jvwtC*5x$tyY?i zcA(5^tF0F-a2)zSx&7OT|@`yFc?Vhhw>xel#a z&$Shrw%psS=h|v)fec^`rOnuD*|<>v&1Nm!cEjJiiE_I+q7H-2tlPWREd5%r+34Md zCw+lL!Z(65aJ5pRLihEDqy9+vx^xXzPTd#{C)1QvIRy$W$*@0?nc<4bQS6`Gg($ib z`=bGCyn;;o`V>`Ni$@dlb6~AU8uo-IL&11qhn8~9lDt)fa13DHVfXnbCL_VT!;?Zt zL4ga)H&P|ZH|eBDQb5?k1TU((<}i7hkXvj_Z@tykZsNu>bFF>(XDY^!>1yVcro*g>I z7P{G~)6D(Kfp|^Np`D$lO4yE_lLMseN$P?%U#o4Xe75vtP2$xW9R%B5xg`coINPV6O2K2UPxDuVsfH@Jktr?WU} zwK%HN;;27W=Ij)kyQbwU5>sX+B4j=d2TzpZLjX@9mVni$lx$ zH}s#$Wmz98d#Q%Gmft!8`B>+vQkR|soip#*O%l4iuhF5;<&dj<9pripa*;CcoO>VO z@hv#6WLn2%B8*C|_PYFJjg;;cd64u^PG598m*qa_3;wvMw~|r5cxO`Hdqt z1%xyeCTY57?)8&`@8bR%o)f3KDCa2Gn*Oe~Vb!y9KFKcd9AYcW?_N8(ck;`VPq9}g z=U1=YJ-=%2?)jBp-Tl(;ws^{#TFTLOBwq^vO&L4Q_%ZB2ML_2V@#q(kht9F;TTx?Etg;~v)XBjesl$+cO zerASUFDZA@r$JSNbs#o~0^XOyhm>9|%F1Co=2*kW7e#;h5H zE{dXY7nVWUVp17ojp+@@AkQ;^u=#L24#y$Wso(dHz0#j zH3-i$o66a(Fp;KRh{>{s0ucO3Ya17yq&zM>i7#~+ zSDlLMk6hKBgPxnpZZ5s0~&Y4?Yxx@DtxZF)R~90sWwVrpH7>0z^39@D2k4be5RqKwtYEjfN>7}n4obKpOVL{8&Qi45x)Q(` zhBWaqE&suYns+9sqB#_{hj%7@SqmHEu{WTwMN9*;6t*=kt*|da;+-^d6pn~1k)?2~ z@nk6+r|pi~b0-E$%#E&s7X>1**3fJvjb>_?dvMpi=sLaM;Ls~2H2Q}(bxqS6{&v8c zU{hmhgk1}p++OL1DBRr-yAtnj5welq>&Y%*>;T!Tu=a@T3&mLu#PDQAE^{me08uXz9!gXrBG9aUAdaEIN2A8Ga4xTUF0Tw;=?Nzsr*uSTH{3FpCdZL zy+$^|Rl0E@+;XxJ?qb-4e-Ji>`w00r0FP|&KTbCIn9FT8@S;u}P+YYi5VNmL!a!>d z@nJksNj4r{w4#V!6|2ZbYsVOyKZvTyUd|Yvv;`j+@giYZ48@D28HUu$JCPVl53+$9 zDto+Lh%^c>_I@OEK2NmtkQP;6Kp1ACoUxx%rLmZmaO-?S=&{bX@Q@QD3C>6Dip)On z{gWoJx?KyJj<*GQ$jgFR|hI_pp+yy>VnKWbNdjx#lX9N-u6R;=K<JaZ44G+V|jPjiZU$3O=77g*{Xdag!)0BMl z>?2cw%bMO%@O5#j`NxX)84VA^Xl@A4T3`MVd`{{Mje%5sY1i(?E8b5uyp0;(7ja*rtvLR7 z@a?d{I|{!!ntvY#;q(sVhM!0JQ+l7m1#iQ=51kLC!)ks24;^m;e3S4ayv>rC@G2Xd zo5TWQuQ0Q%IPO@tRvangoqfgegZO|7W2`u?CehzAD~>a+CFVlwKYE7K2{H6ioAMKD zg%v-o{iQ-zhSvTbQ4Vf<*fGsrg4xyMnww@@PiXE1xIc-D;v2$6Yd7CQYcWYNG~-%K zz6jB7F{R^Ge*|A#a#vh(S6p&uU2j-iau;x{%}Dx)YDq(J$z5^DU89q|T2+Nn>gu_# zq!Q}x+i8dEJOg80S&jLAQI+DN7#D9d1`AS^kaDG0+dq$vn%I2f3U2YX^u(PS`QK%pbY&3g&tFI8$g zfxIx}jskgw71f`gZjnb{kjt>!cEMb6$(?UBF^MH?!RTn%AH6gZP9`HbwxVHda_Z7( zEK0Y@(A2~T?7&2VoY9yMTsW#W;+u@cBEn~i_U#&v21kAV0KLk8hsZLl>{!I_#6rJ$#@XZJgSViv5{->Hk2@pMG4Z|5b4S+P3BOs+yhx8ce>>6 z)ZwyEocHLlmpj{5eyw(u`+IZ>Lmi#y;KAZ9Pe*92aSFq{6YQd@qs{)7fag%_$kfQA zfk$?BPJg~;a;IAG)I0OD=2QF&HLYr@bBTwENRikcsi`>SPx)w7om!*useC5; zHeASin%&~&UEtfH9GZOy_X?l9Kd#}a^blTSb4#;*3~vMyxm^ zR=|W-aYoEKp{0Gb8J=j(BWvX+qkOwG<9kuQ0LAmxBgGjp`Ef?>ja|U!ORlR^VEBS3 zNQ>vK7dN3SZbGR(9T#WBiknatFu7Ko5#!$M@GT7Mu^nLDQSa(gd^5mhC!Z+abkuvQ z0-GgPFoY~+7uCXDN}DH=yNz8`eRP%o!oaRT$)U18FTH2g$h9M%ANhRXA{(S#vuD^2z%cY7yKB)04wl^X|KrSA6@;LfGn$Pl&YUquGiOvV%4C{3 zdlh_Ywv2eyy>;g7zrm+wniMA4SK-oU*j$(;Qj6SlKI_a`zcz!VX0~Vs%Q|y*rN&2e zGGtq4&c?vEgHz2v)|sSq4%d91{9MkrDKfUq}WKOCEz4ZELrCZFadf4B=O)JTk|Pw6{{eFW~*Dm$ExXrjM^ zeH!kChM$Lh-nggm=dr(qd%5A~VSjJj6a51AEZiv>J?uwt4;efj_JVOw{LSoTle?9< zRab)q&}o)*dgbE=kB2QW(buw7aMOvHD!nZx`lYN3?%!#2I?`JiI{orJa9?EjdDw_? zPw{uL-Ed!H_<8sd;HmIE>^9Jz*XVZ|_Z0qe_7`x!VEB3X_ByHXo7vY48u6F2?`Upy zn&u)YzdHT$DG8w5TP^gLEbgC6OvV2r&HayBeAG^UsJR!y{W9F|!=>h%tDtbu0Cy8; zH2=H`?*Bo2%H0EZ0yL~{=JYYRX&HW}bl(j3F!+0=`(e0Oz^(ZI0q*aE_AW`sM%jFq zR;*stkJL0g; zty9U#sigK0dAl9V$&cJ@#-Wzl*_tit%uUM)o$91b^TC;|>O9Y8^9h})lRH(oX7d4@ zZDyQy^Ff=bV>`{~akk@hPa(AVn9mL)7W3lW)VZFJQ%hurfn!c(hmjn!cxx3uop7q* ztOdX0rNKi%)S13`JQnYd_{S4ky`h6vd;`IxIO{DV;i_1C)Jn8HArv*(*Bc)h9}4cC z3MK%%H|>;A3rj}&c7(@Dm7ZjLHkQ7?NLH4C%)vYPhr6e6Tf&0YJMx5i>IJE z`X;HXz7#fd9~tzIj)wDJ-5a454f(dT;wh+kFJg`qmt^Z}9{I86THJk;_Nw+3*kg@w0&`iINXc|9j8MhI6&?VGuv ztMte*pw0*(U!(5?? z&@m~S=L9B*Ev3;j^8``{epe0gBd5PJ;okXV1PVtr-bYFPO*3DudF_|oGbQ}&+Mbzj zEvq@=?nj7{n!^iv5vF7zrUK_Yvo!R=g!{DX@|Bh3c0Kdq?pMEeYsK7?FH8{1%1ZuQ z#eb`bZ)xaDzd11f|9tPm-DS_7q>yu2<%hd}`@Oo*F)jAZGf%Ko?7cJJTY%Vk=ocm? z2cDjJeX?&l+16FZmLHqGVte=a3smaGXnar#KmmbTC$u8+@zC zhMT5@iH;4PxtrvpEx+5zMkF0%V~cPE;qmg*Oc2?nqA^oo;8{ytdHvF$48~pDh8{tRDhJS!;_>Yo}$irmA|5~z<=v`#P zf0AtMov@p12)Bo9@a-kri<4l;?qci%WW)akvX?XVL9!9wLFvAUZ18=U?3IlD5!n~Z zLsAirRA%VtnLEi|FAqswD-TIU1tFy;I&t=sWW)bcWFxchBOCsoAsh4c50Z`WpO@}0 zkPUjibqq-nb!?8TW2j5HV3GQQGM%{TU39}oT~sOPBvoE%EAt0LdRdPFI8Oqi_U0=g zGE@VcF9A{Q>p*a!nLzH+YL~le9vW1+tK3~)QeK5phQ<+eh~~NHzy2C?4>h@mn%zS! z?x9xqP@8+G-96Od9$M=jTIU{GUozC(gsT}>3$9jNZM>1v@trM%gvN_s`hg)^-5WP2 z=BYE^=2oji{E%pB>TWbah|5n+MXO@&cgjQjKra9tkhbWZ5*_pc(9yhX(b3#iP#QqD z7O2yM(2#7)`K!nvE0`+EiqeX*3Qt9OMMcG&ipq+)PSs!Zl)V0;Q_CUk z;+(;AjB-Qm=V?b_naT}aAx}H#1)xJVTXb}g936CPW;o4RR0?aZsr3iM{9+*Hn5(Y2h-S@w4r=twy)H!C`7 zATKx2=|SqGuUMeY{#;vKD)hM#kU!#VW56Si$ACwmwJ@F53_Q(b%{WIEB$8nT%T_ax zw}$D(UDu-PHBIz$C8&*r*+BJ%Y_4wakbpMbj8nihkTO+&mq|cxPW88nAAgzZ(N!J5 z6WCOLwK|YP4YQ&{HeUW#^e$Qcpj(T~Y5Ax6T+}4qkP(R$%xTWjP$8AG=Se^epmG63 z$r?ri9#jh(E|8Gt=MQ-U!0}u#ATbu^$%cqzJ87l!Jva-J&O&dkb`uU47vXssVN_zO z0T|BlHkuFq`ZpQ>vfS{krRcPd;jt+DnAI|~kx5ptY;|lQ&tdU{CppuK4`<@=;zKX- zW^D>b@iw9dr>?RIHa$$qT`S%1hFyu8dL`KF%yHPnw~yS-I3HB{e^UBCApO5W zHhPCAVH5tpksElY$p#(`C5cW-<%D-8Y~ouk-StFo#S0nP;2VTZ=aP;{`WS5DKPc&> z+)g<6k{fc-d8Z`rb5sG{9S7B;{ z)ByP_G)f9A{8bijM41my#nTDzBmC8o+Aj0T!&8^bl?yAy3J7}TTS#=&UEWKf8dD|U zs@G&|hUB+1$U`B!Bog0?HjH@TV#o)>&>^c$NGzordCUz}M3RH&h45lqkT>HzQ>2Hq z@KiTmNyzIkGUQ*m@RC7VNUDkNZal$}>@iIhx;j3eI0y{N*>+1%EC8+GQ#jX&5Xi_m${@o3_i*)l1uqh-I&tcxMg1hUmci;kJlY( zTjM>BjB*n1JUj(ey!5OkL%3GFbHLZdspcPRI^M70@w%D;FX|BQiy9uuNybjTqYm+? zvZ(a(wj%LvgN-U|m>Te**`*mPA04jQoyL`Z$Z8aPBsZ0ts@CMT;_U&SYCk%x_0YI4 zfUjQSoh2FV@J=|yqXVoJ9tMlt*x|K+&xw2?4UgJ38N##HtJ}ec*Mu}gb z6X3=U?;|5-Jl25ENqR@Yhksta=o&KOeZ(Q&;~L%y4bPf?FM`iW z{#~#tm0mOzLq03sTJSl^zkM1WvfRM4=HIR0bCQ4G0H4Y~+-Ai4g+sihc=jngjOsGt z^@7ideAj7s7}I6MyB~b`5}RhM?f1tT9{;?J5EZzr|gAVb2tl_;=!%Hh)R3=B|3qF-z#cx+0+rZ}}|LE{fg@?~f+}PpW z5568r*DY&(`MHLt;(GY zq=q*jW4FVrK;w2IUnlsKd>b`9YkdiUPnEx9E* zkW5H`fPj;PM^N()FO`}X1E>fFA82WZAqmVtNa7?Y*jKb_!D^d;&;X)nwbi!U;TkY1C)LLz~?muq#-&W{$leExuyZ`e4edpdYbMBoiG4A9&<7oYups zl@tG7#z($?U&mo4zrxc{+3UEF>HQXX{U{@P*K0^bFJkfJZwNQbcKa~Xk7u{PtY+yl zZnkeC2JC%vct;Vt{TVd!B<=RY9W8MH-WH{PIH*y`L!m=2R?<&=@7^U!kiJR%D-&~f(sAVxa zu_m!>fxz8>CcD)vi&4`y`ZCW|R}87yg;NZ?WS31?TO`}wvKX~2MmMzV@P}L5TE~e! zg6+OD`M}Dmt!gR;;g-vC%VoKUglD-d-?h7;4Uth&v9O8+R!PNkJEAqEHiqtCO6^;B zc7*q&LP7YrNP!8K#i;r-#R}pJ|4^D4F?>Z>L3}5Cp5S}N3gVlXhn%>6!SK+Jn69aK z7JHXk(=R5=WjPl@{ExI4<3~OZnAjPFgCQ?;c(o}Z31i09j)wK^_OQ+o96I=LRv`> zT7W&ND=@2LI6X~#lm$&Agv zd6mXtJ91GFV_RQ4`mO8bvEXGt`}&-3JKC?fJN;)18m9c>c1PZh9sfAvZ`a;8D{cL% zxzGK(dqK|d%SAu^>HXz_f4b(SwH_uM|}KVr|QSv7iX4F9PV8Hpj2u^=R|2c&x3a*)&pZ4UgQgq*}8qzlMJeJ)M? z5qeNrR1P`b6w0S->We7nB0rD8f)IsVB@5-rj*&z$e2kC{@-bp8iO`Z&!fpVqy1d=d zsL;W@4{_QV8g0xg5!$LWkr<(hh;+1VjT&)qiVqx|dq)+DA@HL0t3Y0ayc{`H$v9j~ zFa%&ef{_y=GV)b(#0)IXLs~t_W2yeT1Vc!CieTiVAWV3g0xd46D^&1(LA}zJNTZzZ z54wmZnti-PTa44tDhclgaS$_6MpEKPLc>mcs4WeO66HqC)lM`TpiT_QsJU8>37FAb zoeDKO;;1oIqJX+_Y8A_XN7}U_iLsN`3l$6aCft8L0tq?iBXW{3O3m3%fhXz+U0km- z;QbtU@|GlAN`8D~dVd67JWbO!;9(gfsTzzTzS4Mchwy~EkQ=+ocn!eYh;qUc<%DPK z_bBkp^!vKhFF$5LD;~XH1MgbY8B@$Wa0ZBZt8=rsUOXiCU5jr4jYdbnA5B6@xJ zU{7|cB{0qf9`VJP9z%iP6V;6YFNmD@C-xB0`yxK_x^2edih5K<((|~I>1_p`7iC0G zXkrjO^@krx_n=k*m5E6sB2+J5zJ#k*Odb)T5n5nK5zUGSR z_KV0h)n~K+(7`#(hQVY-1_a}y$Ti{5U^4-~6lvpRg}VBgtU?E0#I6FoI#T9jt8h(5 zB5HCn@`g`FAp$173z6(_9xf*_c$Tt{>fq(7=e6ykcQ3HHNf`@QTAgw9s zoltZD;sHG>5^Tq<+luQZ4bB7nGOimncmd!kz`s(1uLArG;LA1mzfCWN4wp@cg}q5S zYsS+`;p!uL?UChCRTRDFdh#&OwN0R*Vz`-MKp#^iT)OM2SH;(7snV;rR0%)vA{S2c zEA@WtYlL5Vy_c;nPV*(Te;5uG1!w$8SWa%)kMM3W^^KPliSgJC# zFD8pUD61bt{g)=I0AM*+x16iD2PRPgP!Dlc*ClCH6-!m7b-ns+*%3~biLuh9B=36= zN=@Sn1T5$3Mx9qnRmO6zF5F35&efw2Cn@My(DO+O%`H_Kan7f}L`zksp-p~zNr9D? zs*I&7li-g$OI5~Fm01_O6Q0KJ2!z`amaEGj_$za+&R>1e`>^QS!jxRAb9&y=wmPr+ zgdXRWO2?M%tn!)?7kEEzUfD%9dqx`KjJ!=cg(qe>XEdA zxyKy)JxA;ZbB@{eXCF}xvi%E!MZOcOl(W6{v#OedwzI71coiwP*tm*I#?YG4m7N4< z54e3$ieV>5b3M7fj1!$NRy=#}iP^raqnXDX2QrS@52hcp9dI87%>z#ci+xXl=0o+r z1VvBNV+M*J^u$t3J5ljsu5aaNMGZO1&dn!B*`2FC{H*I(md|+@RQnbL3w_Uqo?108 zsGL33X+MXXY-q;&Y>P?c56mQxJz~YI(+y=;tuPZ58iZg zZvmugv&^n)+^E?y?#0{7|Eg}l3)BivY<+=@#jn*8nZ|fH8dbGg_gC#l6qP{uV^#}D zRudp0R9)VO?s42}zYo3#>+-@Kc^|GoA*lnAPKHe=X&{G?iMtp)2{4yGqaG>;T!;^mJwr%x=A|6M{X)v2RDmMKpy)x9AOOx9xX`|wa?s;C zBoN{+CK&Wc(nUi3D=0_%TFL>}QI7UL4PHh0JWWpk^<2J>PDrvwZk;wz4*Fb95BL^> zLH~o41122?qEAdBxRr9y->$(sCCvk{Gb zNEyLLlC^N?>*Fe`xp ztIpszjI%}YWkVgiHGYT%XFqQ*Whz!t@Z)V3%d#A;|ep%deNpU6?NeCE^EHlF#@HL~DS zB4p7llIVNM@J&*nQAO{GP?ZNu4~WLWLNAx|06ivfo2tIkU4}&y8w1Z|y4y6ljS;^O zu`!H&T!4*%M*wYO;AxOE1)Zd*o=(q|P*!3JDPr4f4g_4vuw^OPO1?r)pfcvF3Tzn{ zt8siXyz1jEmDA%bl^>@Z<-esI<)g^A;y1#WRz6Qr%P*lE_%)ORKS+5I9no2VVO`Im=-a<``6t{rSF)8G*r_Z3cR{>;yH zrLh-*!k^)Z*OHqof_Ngf$4eNK+P79oc&Fna5`8HCMH1-galVCl856d+`a4jocnezx=Xy-4L;zO2Vw|IQ709% z|2I3T<4)~3|BA;^0K8RNy_~fGkiU=eFgQVP`2_Tef#;J6Y1c-2A&K4<6VTfOJTv1v zDbW-Baf7b${x}6ZGwYFsn+&M@`|>Jjd`5aTz%xUyQ=(TV(KD_`Kk&r(H8h?X`S%*| z#CkMH^uB^?yJY9~e}Q+aOh~&PK%Op@Uv-K4fNw*YQ!6L_y^N2d!Ib?U;NdYlCcTal znci=Kw-IGTPplu&E3d3x&dt`eKf=y!G292o^B`PVQ&DBs&TaHEbRgNeT}30e?A*W- z@-O@Z^5{yAoPU9Mr6sa+`?dg(BXThNkp$D8_%Y!3iLC+n=Tbe{x&6Bi#vX}w26`8< z9KhE~?Puuf3%S4GO;UZCu6`j~0k}=7U#Y7vWj6rcE!A(*)h}l|bg+wkSb~Ke*=<^T zVK;V_0p4SPKVX2@8sME0{4uFNygXoi2KaFU{Ja5v127fQ8ju~@f2$oCchG1sCgWv( zc$f3nwRSZ$?;O|V@ubFOMk_MdT^Wn?CTJ16FujxH>i9-w)xv5_Z-Q1MEYo1uWv~(( z*UU@R`Sv$=bnekiwzQJ2R?Vy{q8RRPfTk7{O;o%Xb#Fg(*}I`ZAz6N@4BfB;t^~U~ z+Eu1n)?TefCGn`LNU~M{Tv3H{I|T|UcqI;X23wOhVbGizrZ#-bF|y?t*>a3LzRy;!3y!MWE zy6g__+PQ_A?(8BEO@P%J4z&3@J389bl3neAw$Qfr))s%DncO^~RE@m`A5Zl14<3KV zx0UJ)Pw?tXef^_1`BL8>$}eQmAE;;!rN-}RJXt{@8f3__eGD?4u7iWsLxaEDPo1Lk$H^UD|z=e?hdGB%eV#8-o|f? zcyfA%7vFtx|38i7C@=qQ&)ix!tY`Yzk^F($LRMIJ`lRysh?0@^(AA*6{I;~i@Auv6 z+pV=eKkt0;y5XFxnf>grXXpnbIoaz@|1jHrn%T04bFz#6GkerE;>gY(%ko}i`_hP# z_3aUl?V**Ye?GJK&9SVL>0VneD|GZLeXQ>nV~&$F#-Ua8w|4lqcV$1%ytzXa8Gm>7 zW9#fcUUu6@Z?k#RhyGHy=eDZs%B(AId*QY}-L@?J(Xi7i=Hwb_JC*2}*&!THyRf?wU zKZ)_u4Dx)i<7y-dyF+^$9Vl(6R|;)s>>2mWWayt}1Gm+^j(!`>fWzC@H zvVvDRhS$}r&UoGF{ENh_*PYJHYw|7ksWYz{%s7)d>xna&`QLm-@j82peMP?OePXpf z9LO3{iVA(%`>&i+?W^*6BV(#4*d3txD?4s4a5g^|y01QWaCd0;GfH7rAC1QTF#V;E z;P4f9vEmN}Wl@u zQ=XEZ;Rkz^Lbt|u8}0HU*GP@s0UDUg0a^u&y=7<>Syb+AJYL^DcxT8{3>>9`J3gOt zg!Wlp@b3%qHrtPQLOsu`J4^vbXpgb|;KOF3b7B>>zhQ93(C!f0!`CM5**sqb-x<`3 zun3#ew=IWNDYdv_kQLn-z-e;IU0N{UDJ|louNWk3`@`y(ub3l7{1b4U+RsCKb^ly6 zn1goiQs?01+voN#pOeSOy|>X*I&<)f?Q;)bKF97QTIw}j?QJ|U^43)ur(jE3U<5SZS2t@S3i4ZwaT~U%a)hp487t^@!YY=o)B4i(XKAIL zUdR5N(iymWUm0`vvSQnT7e-i4#?kzNt9|fbeQExH(x)8AJZgXD8ejUuj%Tub_D6i@ zKDY4AG4IflkW!X4@J%{Vv%ZB^1p`0CS-X1hI^Ps3%K+a_&=~(2`72|r=gqO%J?wNQ z+t}FC=)@}e8`)_$dvh$m$96i?b}LF9{mW`?kJdIWt7VTao25K@dE@;Bvud->Tw}MN z{m+JJ)sGispSIg)HCEN$(s=i*beyHv&suZQ)#rZTdF)Jv?MLU%cX}Fy1#8v-xsxZW zUeA!D)ID&W&vA+^aF?Dq<-vMkeCcfd7k|y>`_8q^divMkA}oJ%PQ3V=;ZKV@g6@XS zRSMsE+8XZfTtz$MN~{zsTCUhJOYF-C z{9l-@slwJ&X=|#oHC5Z1YHUr5ZB0vTO-pS}%WO@{?M;;x_*CLkg-PyjJYrJCs3xo3gu8py{;qa+m*ZXS?(KKC zyFaJBtFwDLJ(cc^H-6$qaJYlXQo)A(n83bMO``tKC)Bma}bsroK@%~VOITYa#rCOykM*vbWO^t3A#(2RZ#NctU@OVuu8S3`sL)T0-r7b ztJLn^o}5(^beAlvz!+^;;VYA~3Z3{+XySY3dd2Y*eAT$Qt@K@!f7MJd{A7Ckr^&x< zE^v>}On&1}&|?A{P&?KpXDJQ^^vGGml~t}@k8pv+We+vhqiQ^;Ip98*Hl_{~85b}fI3 zay-EO7v=fjq=FpgJ++hrk90Pv{#MFiclxjff0uIL|B!Ov|Cg2*K%JQIE42Iu%4eWG z<#Z`+uVx?dTzx@Gqkr{a;Nv#@R$U==V^L zaXvvg=)XWY@P9x#9)y2N`D~ax;(K;3+TBAr>LVtMxP&q+{pV`dKt}`3dJ%^O(D|0b zhEvtMDVGwhR=foEs5G@o!aE%YF`iZ8FdEZ%Xqc2}%g_ToA0rhYWdj(aP7DcCWOA`H z4PIry7h{@dz`F>YEifVhCd&+>$N7M~4tRS702s^2(^CAE`+eCPwL~NY&R68C@R9Le z@iHc?HBc2vH{(jiBiA>#L~5fKEx44m+;0IM@r%YK%H6o$CBe94A>j2QCp@aBMEO2^ z*HYF)yn79Pmnz6FvST5P3X$ zKQu{iT5*&f4k(`D(OUsLGvm8QqQ`%fjx)Y5nWXo7iJsWj@y2%%Hn^GbZ2_L(AC8@I z=X<|NdV>-@{-ax)uW>*B33z6#N|xZ4x!BKiZ&QjlUmx(y%$Kak#C&l)@)VEWvnJ{N zmqd@hRM5s}obNmwE@tK%0G^mHZoP5GcN_4`%=bCqiTPsdj7x9GB)x?Tqx3NK2tDI` z*8$JWd>;Uwm@h6P^o-}r!>C-P)ytXjJoqK>#C#WNi1F4p6G&$0H33i1ldTes^Su*D zX6E~K;EDP2mr59;8z19*zX!al<%w$7#`)%Al0fC>U%7@8kKS_NnW6V_i5`9TQHn?J zizexvmFS7@xp?&ETw-oLT7W0!yI37w-0?kNlHRKly`>U8CWWqjoC=@%|j*GWT(WUu2&ruQA- zRiKRMiTMz{a+tj(WCd4Uz1XZ3oH5$lavHg11qZHQC@Z)((m;%-M6KZRxE0)Qr1p9% zxP{yb?wnMww}LC>R&WlnHL*waR&dq)7nK;D9k0n-Be^(Wvz8sMKv zFgbG(iC+Kjkzjg)`=kU@{V@alWdr;(15Ce0M56XNxOJ$Ac>dnEdRz6bTD?^YJ2r#W zn<&;tJBygN>8;)tBUD-(^ESUaX;#ZS4+rv{Xi{;xu}x8_QuWEMvI|G=`E;&^M^yq(H$kmMdK| zt}E?v6}?vO4(#k~YfYN(q*9(zV^tF?5p_b?baV=hb}KZR6&lS7jn=ZmAD+z6@P-r& z4J~82^6?H(%UCXQ7IQN_GAl{;Fo#-kDsiNEXowWz{!n}M+bAU>Db1llwcAf&04jx) z=V66Lvy9~|V>$7dX&K8|#&X7B;P~eEwRPN~`PhM(O$y&#pryW~NR5Ue+H3OPA~8=j zDUs590Z5)yTf`ASQZzJQ07&-ny1}bSsr}h6FhAx#baS?_T=`g12tq%>Z8}?>QeM;$_el)GW zat`a8HEU6Uha0$X%yWMTlgY)6gH!uGB~!Q&%`_M|f!g}2Ih6>yM)ZB0ifVpW!42r9 z!<58R{2eyhJ-wgsYST~Psy4He{!Xc&zd6HQR}Z_Htyg)7Jp{9q<9v+kRf=;4=MH&_ zvx*k^RC+btQ+(asU+Y#1N4niG{-9oA`qM+SPx3jfok>PF>1Wa~tJ>k4?(#g8Q=apX z6O3I$@r)zOggl zDajdBytRc+m}zOf)lzTA`HWu~{O(x(iO!B2d{3XrNC*D5b*E=~{HNJ0&nd|?>Es6A zB{PZZMB%H0z$e< zg3ihJ`=&;Cv8o_vRPQWM*ca@?zKB>Qgjsb$0A+q!l2%(a?#| zZ5?+P^wrM?zX~v$Y|bxrKCDok4?Ac-w(bu-on*2$jhm~z#!bJ7bL#qBF*yHlXDA~G z1GvqsC>+QshY49ZOvuXTfbQmR*pDf_>;AxQtC};78>&%z7?c!=_And+w!7RpxbWx# z+)J~B;aK@BDmh%G8IGyfw0f%HSmr7B+5Givq%a)@WEC)ia+BfH8sE={()wW{Tf<6V zI_8}^kogdUq2kmdo=dU^GH{)-fBNC9MRu6GrSEt5+J@2}V#V$QIps5OF1T>*I)E^S z&lLJ{U{;3RId$rQ^C33hd2p&Sbs!B_X$KwL;LHJYGY_t&4%kp?J4h64<+v;7D+jZV z*q$l!O*zUg#VY1a9bgYZb@0$dO7^k*fnpyk{sv6U@(1qbre$f*%=hJ#Zy#LXTj;xo zO0qGpjqZ^`_nTvvov=Urld&wANjAddtfVLNbb6+8I$d#}PItf2_~zKW6YjHfSGz|# z+?l7{nJ{GQsVlIZPPb9r>=Q3Frl0*uqgvD0(^K%dny0WQ-W)6FVMpwz)9qv)OeSld z+JXY2Scg`gp7o9MYw60}Q&Lb->ptz^<&GZL>2w#h_~IEwanCw=(eX1`?D&~%`0}E7hwenA$@|4?7v4!9Cee%}}eP8pzTy5@NGFO{A)93Nw z+_vW(!MSaJb&MTvTB-0ecm_9PtHthzsVMGAc4At8XXG^2%-YnG@FbnEovUE{cU+u} zkx+}S9@t{_D7LsCvSI5{xDi`SMw%qa*sqc7w?1!Itf|#17;wI2o5X%?juz|#YP(!z z5o)|#H4yr8Gf2`rOAW3854EbD8uTx{R1P6|A?0WfEhny~OA{ctjB@Bxaup!JTr~!o z;!Cu8bn)J@S5sBc|Iwc9jb$Q@nUrNnDS+&QbQ)aYzq3L7OMlwC^j*q+`#xAgofmgL%hfD{~>cdu;NJa3Q;U?cMF} z8UL11nt7vkd<82O45aJo_pt zmJ=;cyoA}Qw6sdXI~@lx6J?lLBvG`tA$({YG&)N3V1k+H==}wa%H@WHh-9>@D#bL- z*j3eIsTZgubbl)W(Ol>mk5UkLQw0E63}Gp*2~VUuy-`~#D&zb_PP+Uu-bcOhqoCYu zzM2pa4A*8%_ply#C7?p|_>UCi@#yU~NpC=+M@I!EqGw!>UjuIi zuhsuCt_MW}6MFWvhbhGyUk&ig%=bgU6Z6Gs!BaeXpEXJEv_uc5!npLN&NDZ@TYx9V zhtp|XdUu(m_mV`9?rlo(<~wYX-qQKe@!=;LPx0vafoEntJ}1$W?W&CT#}7@?n}$P3 z@DI1txZ_&^JTv3FN1}(N9+%#iOwyC1cVS8qddB;MqIa3OKQ;nS+#k4%&@=Kch{{!3 zy__8ZkS-N`1$csgi?s51>-)M%dUHWc(1VE!Peji+UmuXn%=hEK6Z4(OuId2rd|H2U zW}NTOfQSG5{NpcGaP7v&$Ug3s#) zcFE4@Mc{4J>gCL6XEf~+)Zz<@&U>eZNaK51E!Il#osY$GMWE=#>$pshf^0VM#C(@( zJgI#Q`1k*mcXFDZW?B~yGWx^KeK?D353GS5IaC=YRxLJq4N;iQtzF@V^+~G`c;tMEG6}#_uD<&~>x*I@rZ}022vXqxZP262fz> zY{y1!MO3Lo;&fG3vU#{G=-%+dyvT5O!I@f2k=_WY3f4xvvEB$N62D6ydW+(BsW;zJ zHm{|u8gal>aGCL_SdMy~iPD5NOA+N!zahAmsyRX)b5+eue_hv}_GT?47cbr!XpSvZ z1A8^@4ERED@VjnTcjvC|x|WtOJp4*+Zw`dIeI4O-op1_Fo_=E@ebu#X>p<*{;LgU@ zuI6y4v%4cqq160XEPqR@7)EsP6XCZ;h8@L^tT?THTbE@WWm!jso6BVj9a$ea5j`j! zjgD~g7D_9dQ_x7atfP`KDq9<9PR*=~N9ag)x2z3xCvTFbsbMDDw`Po*vjSk_TmSke@9 z`g%U$NHOo56 zvW~K>qmqjDj0YtBgG~y@p=BLqCXQQN`zo*5U%9EZrbmcSTWgqNbRlo=_Ld^9*Sg@H zD7YgKZih#sE`K20>TeB)JHiyo3!%Zb`MY*?!u>#3*NXM6l}r8#t)ujBj{n+hq;#`0 zYbixmQe-1l`u5nmy*?#){|Vc?^u9O77+W`7kg4p*3B574+p~AOvv?M-AzR5S6dI_4 ztUBsPKY#rPh6J8Ff>$I_pFQX)Bn*|t>XrF}*NlFD{t4II*M9W8pqnA#J0hc*a>{Ww z{|3j%liZSo&7&UY4=J!*DDkmV%sb+`cHo-Py#ZGEw=VXY>lyF@_)pf%o7FOF?YWKK zmW#;#fz1@*dLHvd1NIOtHg65LZb%o_4L$Xmbweh%ZlH0iL3Wfr$I-MS&cm#?gsfl& z^7~y!P^Z{?-LRce_KVt$yjBzQuk7Hihh zfpA44$&oMb_E;tThP*c0HzqN3@M^N;8Ja8&3Qt@&2?`?6)#R0=QpvoU0R-wvl12J) zTn7i`Pz&SAXIw`Gjk(Sg$_uF+mC)FG7YrNfsh2eBQgEDdaUHq%3Dik5cyxphW#`AT zjM|fMp5*H>b`9R7>>AYG_SsVD&bT$q+BIO6QnG7MZ8DB3la3u7=`?SXW0l(7->1}F zvaBLajTm+A1UA)NzNuO#<&;sqIyp|Mz5RZ2PEF8VvYbLVDveW;HupQFql~^-IZhA< z@(Sdek&~`*8|65pZl@e4(ILvGGxjYl|GrlLbINfd{f=_9`%kUhfs=vSkvag;C*5VD ze>aumFx-!PF4{d#IZn2dl=G7g2LrVGXgoGA{vhdK#YTyWag5+UKT8N(Rw*V>PBk(h zU87T#hE_&+f063NrBRi*3JpCN1oe-}@I)Kjs7hQ9gva<`H6$&gqn!E{>6bWI3x&?5 zC`1m;Lmi$24WUgJlPWblp|*4h@cu#SKn#J@kf>O|zY||K8b!`WTpRIh*a=wNND_Eg zp+xG2O$VN+BV=*C&VV-yctwO@NPfUFy(@vY(SSoB?M_+M>LK6>RWMpBN^X2Uf{%>% z1n@dhM)Rk$n-bym;Uo8(k9&}R%@Tr?jCd8mtC#A<<>R=J`wat+`k{XL*FExh{oV;Y zAL@+BNbe-@N`OT4ay8_5^nL@pc&d3udgahB74&3PV&i(;47?S_!2yn058#RQ5ZgN5 z_?`fsnem+go*19F-{R5B^O~b~EARw8S(Vt2xybwAZs3`j?*Q<`eCgh%6mNV#@|s)U zX@$}8VaxIqkKPL4nc?3(5t$@kF6h;@!Wb zR43mb*B3=Yv4}H_<~wM>dkc7?Ul;E|<+BlQM8YFFlqi1_AB6xdDaG33xhT-`Gsxxf zxq#gi@j2U3;CKQRTb4WD2=Dfxpetb4S#Z7&X1`lP(+tAmxi9O zE~lg?>A!tzt3L=IeXZeGEzWq_mRegrUHOm9Leio9EGnaABj=x&kV%K~I}%I`e@TML zAG*HY#g|>6kj|pM-p%NtLnJ#EN?)JOekm%E+i}pJm0&vf$0V4J&ywii`Ek0@0Pi)x z&q*-pApXz*|6c?Ap9XlUEjj>dUtxe(X)ryG zri#+~>o(q?R&Qz#g>Mh&Jj8Ait~@s(wEZS7)!U@LzmKT3@ft&!pLF%Oyl8yoMs>$6 z(JK~0|1hFqs9wOCIb(ME( zN7##Vjg>ZD*SNC&##Jlu>bKF~bi+zNzq)SCy84whb#!gg?|0mn*UdY-LS6pmjxcm+ z{X6}O@vkyzH5$@UNLIgrmN%uwsi~YnD>mugHLtD7&fHRwOqO#|AFat!upG!+4&-%@ z2jhDBZfgp(w{+}G`jAkYr*=p+bp?{{e*?Zr$xCUncZ#JVX{ktVm^jh^9;SDuu)`wm zRg>MKmWrgMB3Z8f91wABQqZTdR3zIXh8(G|5%z7VscFKTBZdA`cC0OejioXOOGQ$> zE$IO!g|!sVFe#AWk1@%&hr(XN`fw|}zSEnDj&KUI0V&IY{N#~~EEUPb>=)y{<-rqG zd1~*8-lf)-ilp`c6Mfq$y?Fj>(~VT$r<+xZB(cM8&6m{&FCmDr*P)d`X_qGW{j?^a zelDz*)8F@Uo4PA8z(8wYONc2|xNN8@gESxw;g|3}wsdWEby<6dzon~_IdffW)9q7~ zTxF`GK$)q`wqK@@uojX8rqJYN-+lR9WMhMLh~#`WRCBo_gxSO{8J zDkvu;$`fs;tx3Y|w6#jO9oIcn$147kuqj?5M%bka!XvF9V>0TcwRxE{LA!stb7XoQ1B6 z5%2RR@&4H)UJfP}uixd`_{4Y{fG5U8W#W2`0dEyCDo(luW#DtCs3N?0viJ}XWLfv4 zz*~kg;*%_kH{!i6;mNXiBVG=~*n%G2OOz-#;;oYK#CQk~GWI1kl8D_Kk+Cn0FJrH) zTvoM=H<(<;{(!nuA~N<$+9CH$}BswzGWb~I*%>5;`NcDPuNsHbUe@U%c|H5C=jRyGr5}c~Pq*KxvNxB554RB_J z7v%qlu}ci_)du)B1N?vn=c6t8SNf(7cCp_ArY>ns-{bz3AZCwv+ZkU4fo^8KBczo5 zD?x#QsQUF}tKo%-7wi2i)xaB*s^#!5_*Vi;Gyy(6BhwSJpSw#6-Ps!BQHj^CftEr1 z8u&Zt4h7oAN4T*Q$_A}<=)&m0iBndq$(Apso&@|b>Uzg~IbA4yjmYkzoo4xR5^6$5 z%honp@1&(@)HpR6prxpgl%;K(kO(9zT;k$@R2rwY?3SW}rKn&jDoiYYR%Hy9qJpKU zU@0newT`dJ6nzLuUJ!=IAS=@SE_lDOd^zzr@s=+q?sqbU8_H5tXb?JrmvuzomsU7*_Tr`_vKV~&JAx) z&veZ9kq0OD_O#x;AxCdT@YGmE&l_VNR?FD1jnxi&)5)h(`QVyAuv?}-3V%-9;m>IY z`EtVN{p8PS#_+P7Yfrg`mnn;ez0AF6{@`6aJ~w$(YAx8fvYLBQa`^W8))zYAeQ70+ zg1#0$oTi*gJDY!F+Q^fx2jR=A@a?n^qmNi_oise%m}^{{;9ltHZ;0)jLre>9CwkAD>k3}L@gNt zpKb0-s3vP*-8m>_cxMb(AX50%qc;??!aJSU4qScix-G1T=8!*d?YX`UtoWO0*W&7t zMmF#G;?h|=XZ_8rf1h>j=*_jI+$&XW#4A;~(JR&b<&syb*}=!_)ri}wPb%)UYd~F7 zaBo265Uo#?L#usid~JxgSmidxp1OjrqDhnqksJI?xz-CGRPu%15fz6N(i<`Bj%rb~ zPcCR1&mEQhVr3G4RK=Q5A6^u=kR3`3aACv!OK}|(2;oUeNCCCEt_2)OkirW^;pUDK zpb>y3+))#EB;aKX|G77fLdrp(i_}rc4dp?cCQ9W*M}bBHR0|y0iY;pjEWcff%jUAX zvff8^idSJ%Y&qxu!fZ_ywx&v3Q^rr)&riNG7qYwG zr_^1tD}x!N>YtZ`aBn zq8wjak7(szq8$BP4xJTpPF9PYoRg6*3^^ye3He+vW1A@l9;JvAGCKK<@O#E78O;RW zN)tLI3j<*aAsG@Df@|`K;*a5+Gvk!(I2tYxjig*CQqplr>AS%DFvcg6xLk??EC>^D zJywvkjYJZPk4C(k#=*M^4T+ve+kq!&P?@+kIwfldUa4p#<$het^o|0Llq-#?4Fy7R zk?Q^cJW_b2c}?V$%z+)YSHq(NjFKClK78bU9{?V1ikM`?dkT2*yqZF^-QQ)mot95^k^p<<0POEY?%y{$yz%xVdDT$t@n;v(3r%ckDQ5YSc&?AmF zzN>&|W_*KL~8c|_lQy!gCJmRDAr)Hi>-igy&zHxJOr zlhilYd%$`x=$TXG(MaT79tv1jqVYJI$*V?wx6M#R7Ycj7Q_))3{!d4A_ z5%3&*Hf!*E+0Wmuw(by=w!0Hiv`4^T5yu!oh9x_hN(33^s`7|sEEfah#c`q@L)V@T z9~oPy;S)8fJQC;Fpq^ii*u`|l2HM*@x_NNmdGophp|<8gTU%6fpZAZ@#}Yx(;Fm$n zg=4{Mp;WwB6vJ9kR}M6e4zmNfe5nD9G}p6gX{5QHSIdO8L8U(U^Ky`-Sw?+>lG%ae z)sHLP`rkFDgO+nY?v>NhnHRbfx`>0xYLCMj*ouE_(#a(`5YY5i+AN)UOK0BFnYVQ2 z6TJ(d$z{bqHhz&?&iypQy%e-cEuDGIJD(N*m`n#Ooq0=V9^sS2?b}jtBWLN%M<4ht z=YHc^t;asnB>y!AS{quMcZFLUI(D^px2EU=k$fhs0hw*#PM7){!&i$fqo6#liU@gAM_?>lZ*^cpa z$#%ZnErsf0z+2i@mwelfWSgpwb`jfBHDFF;YG$?N5%IWg--#@r=Wy<^sgLA6`sUdB zlf|1K-^Pl575IGMAI7{Vw`^02-3MM7n|;!`KW%@n@0Br6kNq>sp-X+X{cQjIUBRPfZMljbQm$0b3M7f z42t`E*YLA6jweG~JHA|BIPg|z?aW7JK3nhjG2u6i4h9wuvH7lp*~i!d=OM>I`ytyQ zN1?kf=df~s?N93?tm2?@wzp}06~-_+e=3#OPSM|tq3h1wUrSf|e$!73zo_=w+VNQE z12do2daFD4x>C%0a~@1P=s2hxWCv~N%YMMNU-WabsR{kuTczt|w4^hBFBB2Er$9tR z?p!rL2%X@fvK@uKrNL#ZU}+HeY!JN2{qd~5^_{C|Ohm`QM_+sH(}8(IZuCEYyMy_tr)g5Ovq9oR zlnboLbby+Lq!x1P@vdw2trH~@Z%`!= z#hKOOF9NPeB=W1z+jEce-n9E1pRn(>eM+gz>$KJ8-C2Pen?v;xNE+rmAtym0tJG8* zpx?k%C7@0K3i!}#NtQx1GmVqjhvi%^d7{SD<_ z#=cBB>c2`kw!+saNBieB_yx*QpU95lYe?;oXx?>sAG#;)UdMg*Pw@Q|-ktX$^uTP` zE1=9M;&!s+Nd|2s->H#@HV-H7R(G4ickMf70$YX{RVS4Qlq2H11k#99L zCk+CK*ufOsE2REt%haqpux7;sqyBQ_X8M^X`f1J1jxGQi^Dg4{f}O~FL1n_d+!)gf zI3Kqc>~G!+>J#o|T}&^y3*z>I#pk`C-nhNY+EjSJs#?BRu@-zYVObIwayDP)hL|B^ zynM(w&~%HO9Q)N?7RU4=*l+AbVt=xXp;4=h0gE_e&`AP}QTKoBjuDKRdO;YY_OfzZ z#u$5%7?bc^R>bs@r!BIv7wjj#FHxT?`=k3ZUt>QyF%lDYY;K1;&Fyr%+-`TeJHwsn z%5rDRM>Ktv8PCvm?F@xRGGAScH35#OwmoxVI3iYe`UP2CwU=ozy@+jZ>?OI?ReQ;a z=|!xru@`A|6XsZKFXC)7_JT!8^=!jQrrp9&6X%PJP7)sSrQNI868l{#ZZu;r$?Ye#m)Nfav7d~+T!8(AqglJrU?;=( z6FN!uu-*(}#>0B2c398R$YU-Etgia>kRG$Tg75fIq1!{r@qN5r1mBIlTmZgDpHc8_ z$N7#<5`ISizyvq3*T9ppyjlj5_4Pm?4Wj zgCCL?V9$)#i(rhgmkY`me7*8LgHGz+2X+P2SRPcCKrD~BjtQfA&|8U&1*+jn#zMxz z1mkFUobpAChosNAgz?bw8F=+EMCF&kow|nSQB=GN%7Ir)Iq-ax18+U$pw~}%sb*>l zx+e%OW9$XW%NhFtI2@1j5!d$s?+a4D;&Q2mCkT|` zMC5Cs6^QFq2D~cZ4TwfkPH)BJ@r?klNvao@Ex6!osTDMMqefMtoYs7o0dE8FhS33y zpYI7RH}>05#9+V?n~eSL2Og~x(c^mvIng!Jd)y?w5s4n(gBrbk$Ys7LI7P4|G0BKG z2YB@{STH+5ncx#u`+-N}rg_kOC=qO=w+(o;RB1>?dY=bg32=xW?O{ss==}(IbO;)g zk=~SfQF>xq$D_9xcxLEzN%UrDoyVhh)Fi#1N%Z)eXV4^i#(kjRwet$&WC6F}Bd^E% zfG749-P@Gnjqf_(nVIhcz$*a_S`R$U@f45V*G$qImFVFXjnFgBcNPv8GxNO}cw)YV z61|xH2Rt+LeG+(LzSv@s@fqp8Vv=4azLNw!OnqE>)xa||zS|^vxQx&<^6xMz&G7H1 zz!UsiGy%O|0ng02wiuHY^zii^8K04VD}iTbz8?pk;2*yJ$EEj0ll0z}=;5(pTza`+ zhMDoL1D+TkefLpv<71rf9VY2LE77aw)Z(89ZvxNE`p&{Lm{^a+5(@b9-0y{je|Up}5;&CqKCo)}-<1oZASN$)v{p5RZs`3{++Hy1ap7~e{1e8%e%z5>%61_DNJ>&f`3OqCGQGwqiV!qc*KyM@P%+Na| z(OWCgGxG0Sz%#?YKLbzjPw*$+`ex#AtkwFHGvobn4e-Q#ub0MWKwwWrpdfXELpw`ekLeQ9=)($eX@>tlbAw7f6sW6 zsB2nV7U=E{hqmnMZtc=|B4sk0$@{~TsEd}3od1S|OWq&8ql44=@KH`%SQFwTq)U()#w~ak6RAzk@OG{ z*(2Gu8(zd3(3F6gJQQ>qC=8UQ7P9 z8Ci>oC1PUj@J;jWJ8?YtlQGsa%g078&UT;aVLutm>hT<%`p9=z=ELxM^T~f0a}O;W z_^$6C#H9*h`d&tgSn%EO1sMEW2E z4}TGWl#?n`ROX?odCm~}ToN9%sdRWT2|x;AYI?A+4PQ5x8W@9|B$ zcea%hqc`!_)uk<=@TP|P(uV79zIsFBHS3!inkq``uiJQoTD>Xy?BWl%wzUSjS~rR3 z)=lt5vWdUd-6SMOUA!y;`SGjyhCQ9FUE{mJRu_E<94?nt^1sz^O|2HfS+#lr-_m-i z9=v1=|IFyYPhB*&b~T4Xo!uQ_KOE#$RxQ)~H;+@lylTSws>Mqz`CzLhA8eLiHCt|& zla^Un^1)`)zuWkUs`+@b}e^ z=?9V092!EM!IZpS>YheYn1>}Fj6R&Cz(z|xXvqgH`Jg2qRNs+|>&X?5Bii#!@@Gx# zBTY)QEH}(8(xZ|3?ke(xlOSgkc_4}_-LvF_{+6yz2-jNM-;-{byZBa#_kuGefnXPe z!fgrrTc%bCds-GpG~SX%U(cGA`YAb4TOhjj(tBwnx>jWXDqKgdZ!|9^Rk%#Ri^+sO zOjPR8zljL5wnv*qu8hL0M^NLz>vR%aWouaRgjrt(&T8$odxRJ+jKZvQkm~$ z&qF3R|K%jYEFrW?2b1Zwzeqw%0aGqcPvA{6iB~ud9@*>4<0}Q8=!^Om*J})TmB5Ra z$o@?hQW4(9IEWeQou&RbD(fisMx<0ry2dA@dNwAQTMdh7{tSi-1SRmK_}|>Zh_o9h}E%07r40>`GnzOm+?6s65)qHt6aXvMoAz z5xWiW4UsY@+Y`B_@mR=Z;EWtuzJfe+XM9w{LfN#{=i2An;^~57eRR1t=37vRO zwtQa!kb{p;ga01a8*qKK2EPXQ7_P6?;Qux$p?Y&mft`(Gp~;&l0JKW96rj1mCyHUyha_(-LGhQ$$?;ppwEyvILoyAXB_0w+tP_ z<9_>Ff=rck-W|{XIzvb8p)DFrRxK#QD~+UM$7(ba z7i2~nCMe6)+R1N5%ghQgcR%}y6P`!%gRc3AhI%OHSoR~1gHw*#4`n@KJID?whw^+B z1C|v&wMsdAswohhT4g(XDohbS(+95`U8}`iEzsh<7J2{j>tRrw9fULQ1w_$th+?@; zc_izYa)=#V2=hhd>=X6-X9t3|v!15Acr4NM!PVzJ>`|kL8YyK3ZS$u*GB4;nn01UT z1igdGXV_;bR;wCimB!UmUtdM^98K!D)|{KU*+?zd=R!Q#C#qmN+1xbic87Byr% zTxmsee>H+y;}Y~^)<$y{4N6NSFQK3|j(hF*@eq;S6(|`u+~^!lb^{NY-0JRPO)v}q zGH=GbjB#Vd3?4&*G1QX~m;z34XZ)xyBp6cLBFaH;p$5|o2p|4ud3_n>ULKK?!(6yM zR|_+mtHw;B_E!-e;9APjo;%+KOp+gJ&z;i(CP@#4>AaqD43HW z>H+&HM|~okl>-itq{$F2NaZa|(r7M;#@>`^(_G@xPS$MO^P!8b3#!^CD%@l6U`i{l)gu21y)Jq!vaKWC)6}q4#E`Ab;wYfAqD>`hB12)if zY}jt3zhIl9MfCJ)!MISr4CQ8e$rBMhE76N~x1cHCN^$$Z)+t7{4O`8)6p6>cgw_RT zJ|=Pnh?*EMg+s%b)!7HY_?Z z?*55_W6EDmKJ36aUrn&2=eI(f`)VS}s%K=7M55{Ah|})k`n(VG?>u~Qal-lN_I<#3 zN5W3Qkd|fO{H&!MV_J`VD`wq8Fv{=O%8yVvj^!T`jHCYzt^8r+^p$!!jz21Iq#Sg( zZU=EM8U~6maUxh4UqKY48_zL0Qf0W6IcoQ$tIn4Xe zDhcm&97LmX83lCmKtqe#;#TDe$6So3gfbwUp-v2mzO&@wnV6UvQj1a{2DqKs=+5Nz4;S}_LjGhvH2fVBGC>)};d~LM4 zWmtXU7mZ7l(;DuQU|h1*z@vc>9$#ZEH}<<4i$Kp6#$@dGA>fIAv3+ z(WCR5QapO}EXJSZRFueH z&$w=%1m21`^o)Fd33!6f;&6>OzBhn(RUCT8@y+l?$4B=zrFitN^5T5vwfa9sdOg4s z^Tih9DIUG2fMFooane*>eiQb|K#`jC$tJ)9S1m3Lzkn#as%jdx%;B7{k4IlBHLi2qY9|a$g&H)c!$1&-3l*sfb zGGQ&sh+a89l!#t=wTKU4@MJTNj_~qj)yvF!vhiWBAVoac6w=5O))7w9lMUDA)!Oo5 z$bV!GQmly2qB2@Ga{hS@nK-0?|3ezAW={4i2_`Q#`g#}FzZEEU@L6B)W@DlfxgG1I zuTN)6bTFvTFw|$TOkI7Zp+1vM)757g>a*Czy80=G`YCLYu0GpPpUtXu^*M(69JWGN z?=jSS*eYFpuAx4cU9YR3%9=T(7w*N)!y6r?2&2Z27g0+gTJx0*$>-)otm=Bl8IWaY;X2o z*P&_gCD~qUy=KF@7Es0w7VHWrqB#;#CXi{!I>awVtKJan~br)kn_PJY~zU2Q86l@*AJ|KN%` zW=V1@#d>8)o{-)pOY(Fq`wYuILw$lzMTb=Sb)OQMj&N%#?N>G@9Iit)4_Uc8u(Pu* zr4jHalN6M3qYo!35V0K1S@s#0eTMk4VA*F__8F;ssYHToCUqiP_8De=D#mqmmykR3 z|E2aBTr?s%oRc2JgbXQVdkwXZWQ{gN>!d6<)W)*7iMvvO&6jC(=9V z&dye%j@SlyEQw5Q^9=BO1H8Zh7aQP(1{hjZlp^#sRh|g!<<-&pLIbR+5=HQf)Oz`E zBASx7%MG<_qo(8+P+kjukce7nGLfc=F{adMAbe4i`)Z_kM%q-8IGr7Yx`~;XQeOgZ zH1^8mBASvy#QtO8k=$7%P1GHO_j8kY|7sHNv`M^ClX(AW63^x}H{T4CcvDT{%`%Bs zWD@U^aqyNi{eGzeo>)^_fgcRKlZsn^HWyUwNbB zlQnCN^F1fw!J>tyc=Vh&y98fk%~~V9=@K5a>c^$GK*A%sl;ZWfM8YFo9ZG~(UQ=1E zYMzMujwp4)F16< z@}u}3)*D*g+Sb_`9#?T_Tt|s|#U1Wp(C_EQ9{!!JJDc0WI>ER05Z1c00pZ@lmiNH; z{tw!C5RxQc&GW|U<8Sg5l6UH*y%J8gYw2f5(sDP;d!Xe#FnoKUJ+Pr=hY105!15lL zuvFd(gJy+6+bOhaEa|ir293PE$P!U{f>9qrl6v{AzPN)LY%1^HwMUT@1|UC;q(a7$ zPDAf5oqp%#%a(LH;a`^WBbU*Ip!)Vu zys7+a6i;h&GcBK9R4@Qfc>|rR@Pe6p#)EjL1ea!=*9pN0HK&)<75I$nt`5>0E;xep z;hl5oL!z;{B;PQkM8v@Kn%|g=VqkIsbQ~Xu(zrMU85i#u#lXAq{ysMDZ1P5bnp~|H;6nQR8gRiRIV^O7!<3U{$h_NZRrba}^|zp&P-u+raVZ`Q;Qe@OlDHU;#}88jhRKn}Dq+lT*hys7FU2CG$YpV5 zfIR-7zd5+WzcmnQL;SU9!M0t2aEm4vRPDR`%^jV4;z$Z*gJ{c?)iPz(zhso36_XY? z(!0528Z7cZMEQ&!8A)iPym4Rp1d2*;85iLTjt zB;HV!lkr!1saUGxu`!ibiCkSN1^JjIEbNE~)7z|2W0ona6>2Q<-~s;|DV!|)xg~}6 znx0e26jGLbQ>@e!Mq!z>o>5XbB5jLV@-bZK3Y&wpNJVws!7X(caNcm)*f# zJGUTj-q}T9dxsxbt>HkMzq6yGO)c5g9%u_~Yj17w2b!B(ySh-Sz7OmScXYRM7o^_A zf0oKGfZ_`aBQHeJA++?+8}EJGt~$1C$7s5Ax@>YU?xNlo!GNpmiot8Yx-sY~v-Qp#oF63ZN$qc=$A5r z5ujyBur6rpLp-Y@TUpwE$9@{m_Q6-i3XTVZ$G@r+ruB6M(?&d5b-wS7cw9HH+}yZ# z;AWqv_;Mdn2?qByE-MIb_LN*S_~w}Vr2Vksb@Z~nUyQMnR6n!|LCdya3`P4Id+XZ= zXY?yUPo=WiewcZc5s%HjKe+k1#xI<4Wn>KJxLz3XHqV$5VeP0Z25B7w#p3eOtOyiz9=<2WiDvgNn`0RRU zb|-bS%Q%%j`s6L&_Yv2zvgyS6>wR|)xsKTTiSHhT+RQlO>fhIx7ySEzyv?pM=iu?+ z#+5Y#%zOMyCOf`4ufJ}zqj25u`5IQ@=qGyl0|;SPq?Ap^sEd7wKU9*|pFc3)$L6z= z{DCKY=qZc%cG@xu>6a@i)Vt=De`c zdPc zUc3DsCGU<2WUiBC+3bqKK55II8arvu6%3X{-4wTtCSik^4w7eP!(@snM}5NGy=_mWJLBS- zjVnfLQp*<*t3+xFG^Z4-`sX@kf(T@4Od)Bc&E`~696F?RT67#JyG7?V)}<8vT%kqHHiZ{uEBU?c{(5+CY@cueWn zz`KMqLxnkiaJdv8c{sVV%_(3^10E@t7?V)}qXc+l<84ev1&q6ZNBp932?Yt!;1Rg1?7?Uvq zO*`;PfJF4Lm3fLs?~qA)Z%XuJyK3Wlq`}9<3avjmGpQ){%;z0^UaCG+(hNiQdcj$m>Q?I)%~?sv_xiT*>qtz!T$}pl>pe_L1YHrSrK8J_4PiDIbyG6K;> zI{UK(Qw$Y-eFi<@M3S9l8tOAyj;=n-P@lzS>guN$>Zh<`U46EpKAV;5>T?YBIc%w} z-eaiuusU6RuAx4cU8Ad?%03{$q}Q`qf=TP=HVLNl;o}la^+ycww+*lybA|AKXQ-b^ zH@23jzR>`0F~E0e@I2sBjFhkI;4Jn>9Xy5kwC^qzKbsxY!8z;=9h}QDv_nM2&t$ba z*u{Euu$%oz2dA^S{J~IFcmy>T08CS+@9zHrT2m|Aq5syJpzc&v1)J9`!kCcn11W6E zGEx36MN5$ttR~dBqPGU>D-C~L*PeC}41pIz4iyNuHtr1gLU>`bZdZ5buI{>)mN4Gf zXxdqXc5@)q?du4ygTsgb1&FoACyC2gAvzXBzHU%h8JE zXvJWlEx*)GR`0}ew33_(q7?=tVY4tR3`jywZH4-Ts=uIWA0&I1lj=dTZH3-Jvh8mO zw_A=@BD!IgqZP~1isfi!0u@|Kchb_Gv~(xMmp^HQr=T-v=}xNJ_2L;O1y=IMnB?2z zd%t0QxOKg%ywnj+VO2rO*Vb_dNNHMEsnOCN%Tt=#`an3abIk>CX@a@wgPWx^EPZ^l zwt?w;pOtSR*x4ZXeZg(Bn8%jIu>`m)m6S9S_W6oilb3d~UXW6DVeE0Wv zu@leuhCNQDWa^-@C~GkDjGG;YW}c_mQ8O3AV9LlmXhvqJHR(ga`ccP>o(Gi@ z_kiyY>?ZpuTS>*>0$e#pyv%XP*6Td#I^sU;=znD_>-Z~Uj-FS>*a@Okf6ldK?aY&- zH#YUw&lps^YMFg2FT3eP{glD9BkQ55m>05L>KGtuo@46K0a~aMct6TUbg#YC}$K1J} z@ArEQwv@HKhp~G*gru7_kVNJUA`#}zI`Ho~VB-*Q({#BFf5#yn@LXXI) zwHUL|O?Bc!^_0YzRg91YhQ=()gbpDK42@ZojfbHz6NWwlL%B#a9!i3V78s!yCIgvU zT}=MJ9B``^l7tnBSmL%>JI5LeHqYvIJv@nlBn~sTkb%Vvw|Max7DvT~rBDem&`68Y z4qP;@Wge+7H!N`~koQ5(MSrxyK(3FmpHhx-;LgEvF|K*oU#j1NoZ4+ePVIWB9Q#4Z zh5aIu-DQ}o#pT7kI#Itwk(Vj5+Fq5@(5Ls5_?wEA;NyvA@h#O#@Xx4efTaTdGh8ud(siE7R;e@qvGJQXm za4@juDH-lp5>B>eRr@_A;b^`oCDZpha8ypmjjYuukz8I|QJb*s^!X;U?yO%~QKjQ2 zx9)rd7PLrl>rN*s8lMmRp{QsNAWvNRL!;jpmB`5+^amz6hett66lJkrK&Xl<$YQ@u zRHA(z8#2jLnLCap{j=CClbmgedM2WxRT~(JindI`)6-JDB-0snp(Im%Op$LlA;?bF}X9uPsBwtz+1qQBjPqu3*>3&OkU2T{jT!KZ63P(T=PR z_L50nkcJ-W3x_&kp0_i|_X?Ir!b}efp7`I7`1~lkJQ$4#%Ram=_BRK@!X8kF&5_<% zzcBtoA7kdoF)nh9iyY&kI7uIN0<+n(igE(8If2>AdqdV&?h?eDV_YdiV*`CStz)tC+k=%WD^c2sfNOXJ!9oqC>#D2E5M`|^)`#+7?`ddUM1k=W0of*d z$BMnczS@e-MjfRdlTB|G89(A&vM_Me$kIDwt7b%GJ_J*uDKK`K^3o~ho7Q&2Lz!)j zBWy;-9S29eGcMq!Inz<%ZG_x-5tpC$UNp?y*&~-N`@yiw?dv|6{l709cx8}PJbdBs zQw?N*vu31b<_C{xpP660oCiaLF;3`t82q%XZ5rO?S<_l`_zxl1gPQODM+oh@hxypP zXO90<#>p$R{m*-sbk8fPY_?cyfw8QAD>6#K_5-|ZEM>yK1*}*X~O_0lN$h$sSx9R$3t{w)n~AJ zm+3#n>Z;e4gKMy3i9-BDQ!-1GHM63wTPLwZ0R_w1OHhQIO$4>a**#Eq#F-E^$Bhpl z%pn;R>s-pwt^k>qLBiV^!mEjT;dTHNV#qVnaG z{|#eyHK2bwO$7^1tTb63@KYB#r4NIK{+IYkrI*oP)f(q)OvVfg);Q;3Hmz9WYz6KD zsb36(Ct+n{i0s~Z2}=$t6BZs6he~SBz5raZm{^+?-1mV?W?ezYP*^iylg+^d(0tLj zL^+)Y1CoqQwiLKE$O%XFlqlbWk37C!;F66`#oY{C6Dd*B-H^pNsOl%cQ9snLYz?96 zdjYsMYM>-l-#iR%IWVM8wsKJQH34TO2G|}+A92!@XuRt2co;YX=3&w;8j`yfE0?8mo&BTK*%?H`!x6hRQ_Q z(CEKNV6w;fnMuxJM6NZ$icwz%md8J1$#l*?xtS#rPEhk>rJ0=XtzlY;K#Hn9ojtPTf!XR$7 zjtPTf!r+)Nh^xUdVbJL;$AlsAGzyyEiH~xnKN<{AxY#YG$uVK*wf-Y9sR4px!f=L~ zFiiY1u?(lh8Enrm$-0@ZAd_^4d;bROmCX{RCIKsiSAS;{e@Zy5R0 zMvlysXwQ-*+C#C!R8P43X+ufqn)7U;_}{Q`2p?)o92q4VtIAD3fDS0ihMH)X<>EO| zbdCjXx)FvOR=DXMz|mnA$z^QRA(#7Ii}OO}2F13@O|Juv_D@ZlQ6TI45O8Z%5acd= z_}OFBeaX;A;}YdGk199)ZQv?UPB<~ol<&a@Q`U!!r#}IAxe%oME^G_^RNMf*u^u_; zlR4A!+Ew~8Lx%f$+;e@^IO`Ivs;x&A(&V1&zoC;?;yACO8B3Ytw7McuW5>F(K!1NU zv~8e27{jt4!El+;mJdVzBOf_pE$>8SqHJjNYZ91POJX$>DT{pG$^x{Eitg$*b5`OmYqTg-Nbun(-4#Z@-eA zW0LFGCX?)Cx0vJtcF-g*W2a2=QdVaC)YA1AvY<(x$L=x7XS1J~Uba3@jj~KeN@N$sEPMc6YrxYz8^L5K5F89)WrL!iT6XuLt7T)Oza`QW2=(&FDlrsQ)z;#u zCEN&;f@(1A1Y}*Lx4&hLSyA&qbZ1c2H7?MsZ*wpdjGEPLi(-s@xcu5HS5`zTrOqb< z_ge?As!Bogsw(T6tEy_OYX&$4&9y62&|JIHy5{Pt6y_P=6g1bTFdNnNDa=M~WeP_S z;K{}u3wHM5e7kazQ;5S>Rat~hcDzU%&H*dhESy(dTkT3q+9p4jNE?obm0hT$OEZU>25g&)B7KqzWl-WHnS#$llmzt0)BHh+6GBwRL|svTAQ2w%KdH<{o^-Fy|eyGTb)s}R6C>lt&Ps~W~p~(YtQI5pYopZ z>oWB{Gn%EiXJ}<-&x~fNc1HII8+)cVOT9B&dq!V#DIYWbeV6*48O>7MGyZ*Pt1~-$ zMmKC5o$1X|-81^Ww$+)9J>%c^sdr{HOL5Qm^Mb9;EbkeAkf7%ctKCQqEbR@))00X{ z9q0{G>A?E=W{ij$SndF~uGIFxXpl+=sqFzeNNo@3i7b_4P^CApz6Yt?r|B4=gOv7w zKLw_;2Sx+Sd%&L`Q|Z8HfDRmA+2lStjR>i3+X;>ur?*UZV=!jB_vTPvcQBe}^Yn(# zT~ku`Zi>Gqu|4?KYXUue;h^pIj<2kBGicfE(+T(Og!@j($5@2Qw0o1_aWZW-hQEV( z1z!7l6!#MQiX30r^#>Z+z_=##CpbGi-eH zR=r&_Zq);wlIdHHp=5|Q9j;&Ss72e&9zMy}rR37gO<%3dr zgV;uSye;&cuH($QFmX(?ZkD!DzRK7aDi_rzhAi@L8?wkBH)N5+4}t3u`9B)6$e%D|k$=aKMGikk-d^NiG-Q!~ z*^ov4pdpL=tA;G{uN$(+ziG%Kf7p;k{v|^e`2&V5@~;@O$iHUDBL9XVi~J!&7WpHF zEb`AAvdF(+$Rhs-L%tseM@cn`EJX7Bk*xcP`=dqN zkVV{IE#h+UAZq1$JIf-j*dngfB5svMT&qRg#TIcNvWN>=#0^-)?Xrlw)gtaLi?}aZ z#64^g_oPMKvlekb9|uRz%JOr>?|>7}1oUViw%01SKLVF5eE@}c_URLKgu6@#QXax~ zjwGLtf$(QmlnJjvl2u%*gfqMWc{>%iPQsBMO3CzHBH_e%lHooi;c|6#N%aLK96cLS zN~W(z!ioDwGTeZKo2sizs_&x`&hUauin~$58QyG3akol1dVZypY!z1B%FB9kPP>#gcI*slHvX;;fnNbllGf=o<1J>ow0BN z+*AqYn*eu~gu_oIo|27kfrKlW0JlWKEt&vVD&gq27^P(W)=Ib~IxH#fd#(G_uS+=b4kMYq$0S_s1p1zoaQLao zQ!;%&kZ^cJ9vAnVgcFYn$@KkP!r>MY*OyzqvZ}%eUdFS@BABhLuBg`WlSeSC)9>8z zRhn|>5h&#dW@ZQ0vFkG_k;{yoOJwq67ey=kJgO39L!V-=lP9wY3mAmpqd z-C~=E)tfC#OXp6sLQh6eAtfJoqR?$gcGMiI})$)i&}^DEkRMYEo?@AHhH}1gR^5 ziH}RXNN4OZ5W0d>lVAu~YsS3t6*D78>I z7Fv_lg%Ka0&V$=Pg~Br~iqL+Kw39WL~@ zLaHb8ie^bBGm1+fQxT16CK=A0KAh0n-u_^;HxTyo4XlW`Gq~yM$i~hW7FV5O!-@ApsXX4x zydAmB+igq!@@ce9?|?hxmBk-^^3it4D~G&t$g2rgn+`kVmEC)~LtZ7`%sS+i^l*|! zKpQ8dj}y|TIn1A1(m0Dc0=-?4o^)ao=^E0G@8pnIiCd&YUOD8I#osWgJdrr$)w_Va zn&fThnMh+zyh~OItUEI({xSQK@ zM=sB$tqNwxOE7H6 z`AdIzYvTPrWAN_eJOKo9sKK)6Jb;kK@hfM}XeV^dwzN8eS-SH{&5_}N&Df#A97T6VQ0u4$A$e^L^$fenZ=R?@4o$)AFvxfa;uufUym zsia423N{&sho?ipeM3|t=ktS{yyoQLd<;iJFwF!P+jOsyan}PU_LFcTZN`R-yA8N? zqEgDcuq`~?src8x(R|UkL^<711|%7q?9af_$xAq@r$qT4eB^#-&tpt@5)(!w6;}aV zlc<#PyRj|CLB&zvs2}PVryNho`n}GgzV89I99l>p?ln9m)At99`j+AZ68h*mqLfVE zdf=?=?>QJS3SP30w<2IIIU@X-^2%}I$gp%W#XVEvr>2pwes=! z5ODPMQGOb>!rppEJ-YQrtSiOG8iD^D}OXAd$*C4K3R`NF4MTVjb~iOikiY z4vjv^CrkfB))D_?l5^P4B$-Z%pF{q1yey0TCcaIlTpl}NlBcqaL}#d<#b%o1Y_>>} zg>}Sd3>{=0u~e$3OYnV?Ox6*2j^z78V>8N(kkIx43ex4E<{dN2_4AEDq#zi!zy9B zQGdEyA@oS}6o$+bNLq<1F{u@ zYBlgt;H+2;{9GE}L{{N0=ihI9;$kC+R@j$8t4zUM?*W|1tcNa+QtrF~=bYnf#tX(!I2iR^ zT3=REQC3-2RasTOxw^`?Jrecd^kAhe>swlzE?Ip(egm}lJ2tiY`PTZi8=6{c8fn|2 z9ePsR^3I-EDCX~sL}78@@A22-U!`ro=+JL;{h{k20BrBM z6G6c4L31Jq*dyAxSDxKTPcLq8xINI-g*P6yuNHdMWOwKeSMG4-4p;7QONgC7WL=bQy2sjZ0gki12l}D3XnuAbwxN<+Dl3IMWv2{mwxbjfA zYf`)Bq;HulzoVj;I{a-|X=x03Z@;fJ=qugO{eP7!H{NBQ(FD1^4^~<6%aKekp%vkD z42XS&GDZ?r7v_6W_7Fbg!Ys%xBE!^x*z56zy*lxV9|%2xGm+l>GqwvX)ob)xUP&r> zcpaFNr3!{b;leCP!ux=uxB4Opf=0zX0G!;dz^y_0`UKGzG2X;s7#fucA0mi;$@fV7$%+#^R6+#N|A;D{XR~2LCSLw@ zC46{r5*~EgkND2xJ5^3_AUGXVuO5zxgGW0|&IIpK?7pIPm>g#z)0CbT#cx9=7W9CX z$8(uAb(kDmXPO*M(e7=ILMhs9E8c?GZO`2WY&IU_D_~!b;wWHWQF^B__DFFNus;&B ze}H{GX6FE#dJ>)isVgvEb)?=g#zQ}LK-!_!HA&mRA~oCTl{+}Yj(vobSTA+`%$g$-vhZ?^luEVr9^5h&PO zXpjY`BiHkB(+hH4P`RE*Q9OtbaXkom%u_P1hj^a6#M^oU$uKSQOMJvS1W7Z+f}_}l z;47?fJ$=B@3w@CUH?tlE@^C&2oTwwL*#5ABBkm|!>P4Z<;Seq;7$LMHHq-Rs4ar^dAZ_o)}ncS!-?6~C6E1*;!+2o&k+yd5aJn^o?t_Fw5afqB=ON$GIjg_(No@ow|1OL=WCt}P*qIT~Vct79}Imy32 zF*WA*9d^%CXHiePGncR?N%1|6{6*fF9uMRYIr=Lz@mP|^k#LBdFqSP(o0)XNS32P< z`1+J? z?;AM3H_}U+{oMmS+mItj4T-%GKTwFP6ZZE-B4NE`0OU$&M=$K^1D*6!2BmyqCVwBI z^aMNmLy=yeZl~NEitY?p{AEe+U+B;ok1m~^2_nbzrV_n@g+*7q>v8*uY`X$OiIvNb zmDGi=G~77;=*DjqNxjh|dt#l!S^wh8?;m8|IjnGS1(=G$L00HvUTk}r58K7YcCr2v z`u_rjGb8b`KK|xirEpq6;bdB%aMpsZutMQPfU`p3+yk7TZD?>}TcvRRKbBf^~BaBlHhR0Tgk1iveGh#a}NUjA;meIX}0`u-maD0lo)Pha6>KQeTg}Y z=kj?%(cIpOHQ0o5B7XiP1fFNJqmoPk1E)#@pf%Hq6`A-*D!Lw@(`*g3&B0JGnz#wK zM?$^*&E3JyE5~>D8E*}>NtZ#>`$}{HnrMB85#kN@U;gGmxD($3v3{kjZJSl~qGt*ujY@s#NJT1IVfX}d z58bb!w4vrnybfoX8gu2l82&GZB(I~D&9b#@S9XTS?aB0Hd9pnoPmU+oGbKCEGfifE z=&gG5tiQV<(-nvuOOCu6EML!0R?(7f9Gj3W2B8WAXX@69x#0bDM(=5gh^^0aB304PV? zHwyh$fj@c3bJ1T5<-BujNQwGRmPiq~JBdWN`-LFos;kt$q3!@a)Rx9TDVeL(espj# zAFYlNe^s9CD0nt2Yidzww~2T*KL6;Xs6eMfM1N4vQyu=w!?_PQ!L1QMY^!T(-47h5 zcTC!h5?S9jfNLFtVyp{g@?m)eIGQgSmnf%sRM*tXz!~5(aAKY*--D0rqO}OP%TT7K zyHFtXQ{6`-ePXUiA9%pJ6yx#LSL&?c(C9PL z5g=OV$0j+4{hK5cO=LCXA2lOSFR3#w&rWpC<#QGJJ&N3+$X6)x9!0(vG8O#_e@<^t zvW>z1fxgz>ouO!?mzLyu3;oIH_mqEqOCZ*5xP|e8i#J|15Qql5O_W5MzyU%LEuiN_HqLgM7l zunv>vFllE*ghYi&Q(q#M;bq5}7c6nIowCZNl^z}5aKl4cZEHfew;gyT`y6&+RGZ%B zZ`E$E>8^ju-!{5n)U)B(TJ}iyC@ZgUAHUw6J>K+@VLeeyXYdsab80 zgkITN8`|T!r6BY8^`7C-qXE5~o%>3l;Hk%l*z~N!TliM;;E<~y!KYj z=c&AQ@bN)b{Mw*hNrOIEw1Jn z-5=Rq(9F8Eh9717UfA0GaA;Rk%~Q3tDj(akF-4A!S4xg$bC%iafYs>KC zaM63SuhGkvw8Ay7?TDB6p`iu)OvA7@pV~in)TM1WIoQr!{Ms6aHD2oVO>a9moWGSy z-TSAuX?JVgdh2Pxu)x7#Z}Enctbyv;{@)yREz<7JXj#Hp=Zx9ToPSdoZ2X_~e3hMXHcH)Ve^ zYj@@z_sto%z;&>3R@C+Ktg9;kbb-_(Pdk@zy+cm43%P`GuPnG^ajz}>A(+1kx0$wd!eq8vT{lyda^2P2<@ zUC71A)=-W;xYWqEQI0(b8~HVqW6y4)9PPmH1FM!XNJ_aC8=lBpBp66iCJFnRy9z zn6QE=R(%)$891Gf6&m$?GcsASTOO(?*4oEUK*+sy$ zBPX1gXUg~BgDLAn#?w8(T`mMESA7>>1+E+Qq)*Hh=>wC!(qN`7GTD_i^;UfszsHRt z626P?7AE^4OkCpN4~_m1vPi^aKPLp_892-@Nit3UZzY)=9{)#@$>9;-ChA0DI8=xpzKOk)&(MR zhktuC&=Xw67WcC<0`J@&^mhjXUBPG_TP%2GVslmX68lRrOeIn0ir>#;aF3;n-dfCwcdI z#`41x@0V4IxbLyNHlic7SNC0tn52Q+m7qf#cQ<7p${JoWN07ReZGBHJ*&PUZeJeP6 zuUDlr_j*4cTG6JHmu(~8tk?_kaBxR2s87B;Vq-Ma-`x}J4|S&Qc1z1U`m0SRab=Z$=KE{( zb6q+qE0Yw}ni^MCsuzsHrnX(uZurNxL*P5v92=)a7{W?aXSQW;V#3Tzw zwhe^CX2rTXK3#@Rhj4WWS7#YX5g(F=rnO5lIB{)z9l|x0h2b5-wb%Bw=6K^e-nbhl zcH4FcSBG#F+=xTCI)p1<$#P9kx=UI1cc(+Lr0t~`HxWyNHzzBxbefZ)SQ_n(ko;+D zNITYmvy5cI&m1OFZQ;n(?a@eou(LlD=}qGZLs#18IdmwY`t6@D&}B9wOG}m6lFYuU zaNL;8mJZ|b##US1sGRq2<6e-8?VCfmR)UJ`>>D^Ak09pd^-vz<(e%y_b6*L_+kxwi z^aion-#yT?jhgnvNJJD{pb(oc?C*<2!g|TyGOn%sx)q~=V}4&W(ix1!eEJKuBtL{B z+pfT^B_{uH3Bw%(+3UhIRK97^~3wRZ{HIs+84O} z6H|`ND$W`zVnp4p8~$Shk*$pddESo~Y2`!zmLIRn^SWPkZ@Qu8>qVFP*c)fHUN}-T z1K6w9dYSL!lch&btVd5-=qc;!a7DbIYi@h}HjFj%@#`_#%-65aEMCsXn%A~wctuXb zaBkzlk^IUvysUAA&CBzy8Lpm!MK9-F+;$l+y>NI-JNd7U_PM<@Mvu3$`^Q)^6BKh7 z$l#WPuMBF}K9SWny*M+z7uD^8G-gZNj=9;&BQ#@EF6Mm=7wh}#6+Nuude?a?;!AOE zefa&ubMyI3c-M^7%w$W5b|xR*8Al%PKCAfg0QLz!%J7WEh}I5&seK(Eq3-GHX7H=s zyWxblnD5t9;4;X=Rx5DvRXBYvhW}K6jOaeA-nC%!;)w{7##z_hka?r~ri@Qc##+xd z90ftaa1IAvgPdQ4rzht*LER8PNe*bl;!q_vxhLpc%2AlgKo?RQBN4OHH0zohJU3?F zl=aED6L1BpT^LIZd>nk#QA2C6Shnw>{WhiaNnV^dwzN8eSOs#N zl`I$M*-|6F)X1Yo{t)tV_*s7&c?I$VM)?bro5Rs(-(cQ}AD^ zzX3V*zZ*IA|Myf5{MV2d(Rr`AkdPDE&d)_0Ms6cOBUTbkRdc>|Qkb1$Ck%)yAR)1NU06vG@=U7aagKRic2p!4&ZH3E&=* z`W0iZL#au+_h>f&iXa5P^uE>TX0 zO|`Lj0JwGoCk`v+YQLv|+kkR4sr{~oN4e;iTLPg0>Dz;kydRr^OXhs8;$i?bshvW; z8y~S>RQ(um)DP`1-GV43>-S0ETJ&nuUsa#BAYpq#*8-(v`pyO}*}}f6zFtWm1r(q} z`qX*86S(tvt@)2S&;JUXm}hZXlfG}_gKMTwwEhp^E)#;3)3>lZfA4{v%6%xK`4i_j z>3bF*`MA9V9RJ2Zxtv~vAnQ8<9G%akPkd36KG@pSRwuEwsjf{PU4G@N8q`pld_Cci z-cdZd{1h5_%Ch0fhO;5PAE6^Xu_nwv_S*KfXXW6MSD z9nBpTrA_NE+oV@-8TnU+7kK1IED|gug6S=*wm9?LQ+@YSa~>B9*&iVm;uMi!?E%Z=YkDpSAN*z)~RW*%Z`;t z{PzZbjIlqJ__{U+2ue$pW92dVVn3L1^Mj538BaXh*wSG<-q>oZzs_>3JjT8X9J`J{ zC>)H!j3I`+x8GL^lZy@A*P-C*K(sg1yCdeuGK>CTG#ZJ

LApJN&VMKD<$k#m;XJ zRwCBxyWGk{f9Hw4e3w~zq_~dp@$%upL6()p*D=n*I>yZ7Wx0bar;ts_XCHa=kIxLQ z$j_Woh`;XKDL_sE15w1h8CipD3bqHCo8!Gxn0t_Ax*0Hqh0ME)@NTS%?Do3RHrJhr zT9jkkJ0&xpedhC7e;8!bvU$H=HhqvypHAB|v7OK6Pkn9QAj`|+>ncw#^zJIo_ZE7g zZR%8vuy7h%fH5qfF%(Y4ddtQ63$VsA%PV9Hu>!M~xvBSs)bBz!l`LfFy>J2VJ=2Tc zKX&_)e6*TA9j&lp^K`thKcm-VCgy|4T|pY!d)iSi_P5f%E}5kyTvunAui>Eicb|1!@I1WRj zWH})cxtEjWL?UIeUnT_1ceY}vkj?(fs6Q7uv1g|*TLy}1d>8BqsIQe^y2|QR{ws;+ z^d)`Z0fQF?IwRXcf!^jwB-$0~MM=zATsV0gO=odoXK~?_*SSr+OG^E%tp3x(SzI{f zNq6E$`$}!|Wa+V+;E_MU=+}1|@4^~`u{7M;!p)(+ zZUiAuV*t8_wD-etXHGnvq;WKy_|Z=MXeWNO;0whwOd1!ILv#rn<8s&-Py9$@f11ab z@1&*5A-YlsTjjVjzx#+T{<`vAKy1-|San;@XJ3B)VfP>_DFGeC7L*VXw0HqqI>?qR zWXnJnEy@77cRhbP_q!>M4u;T5KYxXvF_xlBY6P982}H z*bK;b#LK{M$G558%a)tu?6~umu2#Rc_81t7Moj5blKft&J^3_VuE-yeWcUHIn-%$9 zMJE4ODx!Tp1ELeJ8wmH0Pm0k=ooq!`5to<(TT7=j#U@sZl<38)648sLhE)htjE0gI zVG?#tU#30%=(tEeh zUzpi_IZrWaY`488(9;(V+HOzpxzcK!-n=;sp2Ohv1}0%9^!vYI?``)&(VM4twmJ-+ z8pF@#(ZCy~^oVFEP@?zQABj11pM5>%7hN{>B+R)}SKzp+Ij(BrWxK=RISiiTswS=m z$5qXEhJp!_eKH3@Zey|ZBKL+J2G3#es_mVFj;orL@D@oK#FT6v9apua;kooTtnUII zkB1`Wdt;T&D?NH@0|Nd|LBQWBFP&=X+uhbWlAl|5DxbBqHJli1XgFDY_Wea$b3Sm& z$J{3tYPmz}bAQy3eVg)Q0i-G&j? z`1G((E8?YjZICa1dboIoE;kQ1R`Gzq(V1RtiR(CGn7;b6z75AN^Q_zzE6BY4}JU_ zBlNKbjoUEpl6-c1ZX1pL#|^F%87@KrpZom)0{`Yd{jk0lCHYxx?QN?9vx})-Te5C= zq#^4_76oY5!we4#y}P~a+y@WcUql*<&dxY2`e1jV#C5n~#)%B=_lGVV`PZ2=?l}d} zpV2daVKh8->@RYoG_qiNR88**;++?4&vtlj2#zF-K6Omz|SNeMa8 zB@E;xCuhL1aPK#8vOHAgY$NV??+=uw3}hj!-!)5&joB#Xp{ji!&D&nh!bQ z7n2Npm~!BE8uiy3InkpP!0km|L>K6|@shFAYN8!amY|C+m3SiDvAC4jP^~N|Uh-Ca zs4ZDnP@O@JZmBnh@yrx>Pve<;fu~gATVkJJ*4K59yt^@8qsbAqj zTZdYyn9ajLgk=Ra6x(zImvKeF%_D%4Hba(i^}t=MU`Xu3N4Or7yaza%FB+F9#~pA? zyyUxpYd3IIPl@t9_{jYp1#Ui7DoMp<0@S2nNL1qoQ(R^0hsMXhERZMbcLQ+z%MSH& zQuW;l+;RX&ANM6ko=o5OE$YieoME94*91?bPdy%`z@2Z@%b9vSt^iIP5B?~luLq7EI!GU;h$qqq zYo)qm9_Qm)E7erhakC{0)=I~HyqmbSl9xuFvd8(m)mrI0n4H9s92z~uCrkfB)=Dp$ z!Fnws~Z&w8T`O%~ndXu=M-5p`WagM5t-% z2H(=`LJ3cIj4g`%aYepQk$D;Rx;Eu4~=GWq?n{y^uI{?6_z{o4bfFp~>*3# zfl5C#fERC9jHnbbVN*qhSRFx~PY+!eyrg|o$0h@;7y5fUR|k8smQ;UG8jLao#}Lag z#BvO=uttE0eeD=xrSz6MK5w+(YU;KUIv?i547VK%!SjqmV zHtZv_Bo_>ZT(i1A`4G&vTv?xj0hjBNaP6rXeUHH;>Sv+VCk9tHo)~Pr;}Pu+LaaVn zy{z$Mbur;)b^jVGuWNU+ePrykVPr?g^CNFYFD<}Y?12L#->ux;blu?xhBOa)Vbg_S z(kM)`@;9IIHBcKMx9#-;TeYvL>#(ma^T-23K97L_!}ym&YhVoZ(CdRko94OiLjSqw zH+R=D<{@LTgsIqbM_pRxPz&4D-5q{#E4H+kx31}?J$NAS@@)@(;;iDAKS86wzH&3H zTev}%CqAa%9Ca;f7%o740lUZh!IqyEOyLGxd%Ta7xZapOV|&h{K8*EB_Qsq!80~wu z9HHJCcOTuQ?Z*D^rx~JIp?%uxy{z@B!_?dCxPDO{gqhc7n3B2o4<6GzY`?oC^FdL! z`Ecfb_uWqnxpKN+&l&QaaI?mSZLjCNcKfj$O>2JaIQY#4-k~))o`w&=v}+Lc$oKu~ z6!z+s1DLDV4nGJ3wiWCLr}FpBM9(Yup6>P1Nan{!ve&!m(KRDOj8?PnD!R!FW3!wm zh89kL{BZMdMLU(=X!JR&5_6B*KFWZjL~&Y0hQV7R4WRofSuv_qsL`=KXaK5-k{zt`(7anrsNb4zAu znGG%`|0l~d$jeb{)imvFQe`Bfv6^OGJ=Pj)^{l>(8g16q6#%;2@~_yI}^1$Zg=%bZCd`=NujY5&rUl%#zYM} zwTQ}5-;CU%MV#K}zB z2va$j-6)kK-$~^-ORlFJBm6PtII(bfayzUMpXdcBB3ZqrR7N^hMnF{Av1QGU`W zufP?RixdCD$Z3DOkkkJ5Q#me_n~)blFVoyEZ1VF7r;KqW(MBTGBsNW3=!#Cmcp{ut z^RGcPrnVRgPngOv=3n<>U^no=86YErwGvHtJe9yEq*mC;#7kilhiw_Rd7d@%ua5$E zv(zu{J3Q4X`m$kLBI*brwpH`5DZoMHn6w!s^7xhj_kl5}vF2YN1CHj4hRAPt$jQ8A zK$5Y^_5#8nI9N`NNhG6#wg6|v z9O@R}mO}^W<2Uqi^gU`(-|Lb-T#`J|_|)T30yCoXje0rjf*|Id%KgBJ;~|@WeG_#! z$NLCFDFU1obEtnNeK_~CQ=5DSc@dn5nOG^4**0fc+htPrEBn+f&RW^ z$Q4}15p6ziOJ`?itTc9YX@4XVj&0c%=-C#Dlm>QSk*Y1%^n^>X4n{y<@E&VYMYl9J zl{T;6eBs8Hi`qMyJ1R<>)?cLye$X6=wwSW!eWaY-2SSg`j|f9bvD z<~(d|V~4MC{l>Mv=JMuq&ha%zdiuC;*QNDkH5Fx*WmT0`<(sRkeA^>YUt`BQR@$<@ zrM2mj)#oDyV~f9IQ>&kEtzWyLskNq&wk@*7Nqx{ddt#xOzcUhr&7!}@UyFa0wkf98 zaLjhw#$cc;t;XpE5uq62HrZMcAUwV1=?&kBbku42I*@rlC(@A<>Bxz6)HV6qsCtM1 zo3}WSB<7`T?dwrEDf^0?NJrcFrLRORPmoZlPp!c~rQT3~;*2j@YgYk1e%PYU^#1u1 zNSf{SZ}GI0q_q#uS|$3iY&8Nfrg0>A48}Cur+qp&Yn3=_l{jma2s(Lmb5Qqp21?~@p=YVumv6};fvfeZ%$4=JM`P?vr+D*a!`SVXjPbzjnz@G4Wt`w zb$l_)%qaviGY7~_FU#4rf_Xh&j&wu6+v~m_dYBs+k9*-DTeyH_aymbei1=)W%df4>@Ji%L*l#Jm}c_?j(VwDL0a zSmMRlR$#0c;bJetc$O4mEf?$^Ta3R8*^+$r!y9``2ia0yyG+zB<+aQ5+2@v?_|{-G zm}6)I26~nel5`Sg0b3^Zg5iP6e=q)=p=-e$!O)4OrU)jKh~^`TkIF=%RV$7dRE#L2 zT&1aFXmq{>n))Faqb!vb8QYb}sT-mNDg6RCqJ~5g^s|clm{+HaCc}*YM^utXLLZq( z$h)@`%$}$ttl0jrf?JV{^9H6DA52A@7A0IVS`_T$s$|g`s%w+4EmK!jWtp95gRC5G&S5@IhuX~^etIh%dUkm>F)1O2~b$Sqt3e|_4rnOLG^XE55&0|5L@ z$;%0dPps!+j&^|Mx5ni*`R+7s-yZ4>>N~Y5a$%q|vMm(o9fu87Tf}&aiNH{}DWdl= z5lr-NARW##`MXw!^Xy88c8x^sudqT!?Y7@DJFB}`wK0_Gs@8+h@8S6(G&#=^b=ubr&b7!1!-H&AxYbZ|L#&f~hNTI8SGF7eP-r zK?R(k0!~l?aWyzW1$0vcdVop8jKJYM$N%;>Y`E;tE_hQXsDM8j3#O9>)Ce!#W`lDtTUP)eDGp6$b56y z;z3qChb_UoeDV>dzu@QcS^nQI*$ysm4)cM_o5PCrnnAXlw>Ue|0@!n2*bp9M-Z{kk z70w|J(93zk1zxa-%t!2KHE1N_5*PFS78)hs6(9N0z%ApqT}*A+l7-Mr8hnG*;LnPo z$A|3|7*#RGi*zQliR9Er%;7{%ug?IJB`7|=$NC?YO?(!L3N5gSf3V0V=F+4~{Rvi2 zWfNBbM-+}o3qKT#Eo97dVx5`~`5Lj^JWjWgUM7T(YFHj)Y6jI#yR3 zG@_4^@QJLgO3pe~R@BwjapczAkGHNhU|x!;t?ze&uAbUrO~9BmU1Oc`6$<$+Orrbbhzg zeokUA=-Jf&L|`KyxLF14Ql?0_PFR*~t> zArc}Gu%9dPe=D*U-xobT#wQJOTyJpxrBCY6{S zC&Ybn8)6v^r2d?9RJApB}e5N{V zv~4Ee@xV>?c9XxL$JFRSKSVHCoA*NKaoA|b1K07ubv$t4#3Wcy7`>&#{>5$P(qLe? z*<2d!9S>Z`16Q2R4jb*T(dpdJ;+A%{?ne$A?S#1h+l06m?~>mI9JH}3R+;D0qo+0? z2z>VLhY$un`}($zhEIj2wVj;5>yhkzuG_nJ-|uNSG1$;>vf9Uv-=JN5%AMCZ!nA`U z1sX!gpV-y*?C}`YvJQ`_a~n{q;|{ zhi`1zFnj`G@LL*++ipIhwNVIo3VcsN?@4zag4<^tB3yCX!Xw%}8F#t&&*L+~_UCyA zyB|7!=k%JV*wXus-itc9e2D~F0HD76X)KA*w_5JowZD(YBt}I0TrgY{ z{HK`rYc%=qaWee_M{>ZovaRJuB@#q7f-kF1F(vFBE05X*_)XEv{)Z z$4)A5iNO*BJ0^U-&sO++y}Pfb)t!3sSPh>)4ZATWe0~!OtxVN|ESArw>f@8n6b?Ui z<;vz~7<1X1DZRHRGScbJ?o5&MzCKfM=ci!xF6>hZCzU?-(aFb-E8{Jjsu$gpPSph6 zr9V}$RpL{HP8#V_HUc?NS#wnxyoxhHkbH<6?Gf=b(G^^-9$O=MihrT7k96d zl;c+8!X;1TwAMl{l<_qca2H!@$RDE|ceDMJqgV1YCwp^nSY-e({hm&VaQgLVDjBOf&8oTPkX5gqF>Q|gj$@-<$ z3iuO_qVsOZV!x>BOTaBhPWt$B1oCA1eri$QS-ylmx&u%med_Tz-)C*rh3kM5$3vXY z$;NjxaBb*EP3rz0@+HP6PU~d)P620S{@z!d(1)7{Ps#Ro2XN;b^>U`3fA<3?_Lpv@ zl#-3_TfkWv-y72S_;cVm`WBT~({}}M%b|nL7hHNgCEMRSfU~l{&jTm+7pGWU-#4*^ zTU4J>#Qq()%Y-21Phnd=pX(MOOb^OveBz!%<9ik#4Ih!_E>6^oGRj}XN7lChI3LPL zA5`;1`mm}-bzLfPYgVqRso(~rzR4{}->V<_xCQAMu&TzFF(--n9U6U7pDO;B%sO9^ zWSaRSl1y=H%=OvqO;bJM#z-<<5%UwB;XKJ z!DSrL(>4x`Vc3UND#kZeoFGKZJGy*^u%UZf%n+R@F;0}2&T`q{N9WShvoCX2#;|8r z=-A~sc6p9np0hGWs#n2Smuma=bdFt~ZcF8?jB!mf+!LIYF$ORX6uHip^@L-W=h)@R zPuFQj&p_;quC5Tm%cXHT+K3Dx?*or+mqz!7OF`Ni^xr7ysBxmi#EoY02%#+VWq)F! zEA8`q>?2KD<1s(gq@~L2aA03mV%0BOIvl$^$1d-0X_u#m?|#?V=B2pS#kS(leeD37 zKUbSK$mY$}c4Pfz?cb>@+T#kSg0QofOdJy+Z zBn03*5y>VO*Fn*A!895e%7}=NacwYpn210p0*X=?I3M5A|G159L9`3p-vdW|h%_FK z)}bI0L?nS*j{zE^~RoG3Xhp$sKid?^ZQtEViMC)HErmO{u0Q;96L$W%X#RYCp^U6wp$vGYvz z`KCxL86f$#n(F7W2;`@w_E($gi`h+(e=ODSHPtU;pM(4hss4+m`qKDP7c@MgG=Ct~ zi^wqFHQI~FFwZFRi;Da&iu|M`|47nLrWV7B>=U;F)RAfEDn-6jk^2<+c18XNMgB)c z{-GlON|FDp$Qj1IU}$`Nixs(9k+&%FCm@pv!oA2(%SbcADS-L?v`Rpy1rrQzjzqg+{?5LE&4F=i`>yOnEe{y8(iAUd6pP@Y`tLFhSvL?CF=`T_2{#7&2l`rjcZQ;o-kxBu0E`ni=i-f54FsaWE~5im(Qv3y zOEAJJ6Nq3gscMa8Yx^ub`WDYT=tw+jorv_&I5D3&@~+hYQ3ikPeQ7a!1hN&BXb zO;S637A90rQ=%URCzg&AODF1Z_Hl1-Czg&qV*_Vpm$lByE~%_)BmB^9a?9aOX{?Ha z*TK#0(O`Qt(ix1!B2l|B)5gB$wz)Tncii?BC}Gg;D>A>`wy($hYTKrs#Cz@36&NqI zQ*Y>S_VMpShqI6W_DF{$6(Rm?ku&-T_>)PR?b9YX@uMM~X>elcq|aqKoIOlv^dG-z zpU%$8E(wF0u@5u$Z#IeNnY45$k2GoNGC$R%rONzZV_#L`*~XR*hqHG$`*)PH*WVbH z;RQh{7Ax)3e?9re{n;DYc15tWKW6d=A=5`+X}Hl&t4QjN;?HjW&B0JGYP|C-vl=<) z`tF;X5SOL+;(5Ea_N~4?6qf>ht4oi*zV7CS+->)D7k4B2i>Gz?RIPS=(52n+yKahW z(=@zz^X?{Wwbno7X*;s@zEE+9>a*_nU1&F=$Dk~bdsjh;PmhfA>J4oa8Ry&c(V}s8 zQ}&?;ni@`MyVea~#VD3e&k;oMVTj+u8p0X-JSA+XLDO4Oq?NshsPdJPeQ5EW!G>XP z{=wlHeH5cbv^fyk>m7W=Q<1qZcYi~Oofy>)yprv6Lvr2jy8B@FQXUT`cmG~5Ny~gQ zc;uc8$Opr_wvwjxBXeDQy+0WKO2@vY+{08NJ`KYge9w=(**E_PMsfv4e_?xT%VGCj zzBWYpsU;LfhgoQEorZm?GqqhkvKejv+PBNQyshMS6ip_(m?F*Str~|};OXI|jT=rf z9+_sZS1(z1aiXMYm{mSKyr?pV@4;SgLrFogJ}-N{4>VOBYH$7U;SDF|RhII4((B=| zW)8eEIOV%TY7#qF{4tQs3kiNZqWjVZEo%1!y-k5FE(NfmGDjOFuj<{@n;$3OAuv)a@e^* z6))tbCucKOO)@H1QhpA|YRb=L>^#abi1$#AMh%o>T#c0H8!;15zM5oA%o@sPQaC9j zl&`0JHe(wMc@yOrf7){hCviT9n5$HD@p+&zAQ5p*0iirMX5W3g!VxwC3c>n?A9L(c3koev)5V(W1D!6gI1;<41?0L8S z&g@PTE)3&RL97-&P1vIprYVsHjQnxRiy8ZgAs?a~j}f$h8R1|;DpXs{zFptfW; zM+w6i6B_JI06rskz>)eR9`!BKr?3OBCK)%*E&XxQ0Pe;lVm`+tVX@5T1GV1(?ugW{ z7<(P+gIZm^U{ud45A;HXSZ>VEuG(nsGmlt|wm zeB}B2EpRv_W0Hz{9k`}3sIj5T-n&Te#|13y52a-NwgA_vSDXHleX^K$s@MbEa^$2B zUpG7@)Az7NeIt@S{__SJNuN5;ML5CF*Sj;AS;H=D_4>v=hkNc$1Li5UD79q22+nm z32rV{j)xyOaXfH|@|0|R5#X%s@3(*x^M_MsTz$W`sIM4bVnQEwJ+4pP-?hM5+25Oh z6Z?zJxIXpzy%UvI_V*>=#Q4shKwkzxR`jg_PUypPNql_j{`LW6Wq-d8oY-Id#*FLx zCblvp&yy#CyUeJUGc}alS=h;L+z{z{%QAo-+G-zPtchm0JfUd~>GAeY|+Ts_K2 zAAR>xB7N|9NxBwsb!~EwmzA{wKDo!sskywHxW`K_jXY(K7kbg{k8ImM5bF%|2fO^+ z2m1W6;0|u&tXOdChU2mRKnIHo`HRFWIYy{Ju; z4UK+FLX(@x&m@@+3{A60`$>(=O7RPJHM-isQHnlud91M1VJo zmh?t%N$lgD_-amkHOE#vZky)VYCE>t<*C>l!-2-Gsc)FaDY0ux>a2U}ta~a4M^Ox$ zY@SxIvNBsW+1Fz>X|ky&Vb7Gh0>@U{SbW`$@nf<%?AU5M zw%Tz^>vXOs$5y+X-1t?je&DZ}Tei~0_aul>d z>;ZTayi(T_aVx~LQkh8AcvC+w@wQ$Rk6A`+9Y~MATCf$k5PSvbvN1{63J`ZfsSh}M zp)Zo#*jSHT9?oZh6Lka;+iKLZ`+!T9dQm8IM}$kp9f8AHxsrmA87UsMtR^{!Q@OIL z0`v~jl_n;|mdGWhUC!o9gq~ zMJ9O$`>;v&vL48JQu_f@{X%vFVKlhzg1*7QvCnyy$4`a#r8iwy9r4M0YVX2 zLfOzk(+dPe(`g1m=!hmuvXDSX;wGW^L<35Rg=Pz20R;;_1r!xUr968=ggV8ckkYrIb%OazBI#IN+NuT>UK-G zzksh4aJGPN67YQjep$dD19yj>W4KlRS4LGEUofkv(VeiQS2Taqm}&@z)=*5fC^=ah zQ!Q3W7GkO?q1HfEx8*oRHnwtAr^hQ&qHv<(9}K8-KslvYZ)i4Zx$G26VQzULrV)%+ zg;w(hWJ6Foj{>qeDJ{Jr$u7zrZY{Ff;CYqfsY$#++Pp#9yg}OR189Zbfq(D7zjxqY z@7`|Mm!#?Av6{y;x66Bjw5g*X;B~Zj;9s1<=N4*Zu&17wAKr&qVeSG)uNjzCU@ zcx&#-c&&Hf-#hT{9r(xhl6|5ve~fYezT_SF*E?FTozCcy$GrppMf!gvmf&^Y%wpTz zQq`|2dgw>2E}dbm8NpW$Zlv4he4*W|m-=X<$8lsKc zuXnKDd4RUsv3G3uPv4cFkS_&h`#oO@ymmHcS3v>~#^%5FcR3i_SxXRtu?>-fv29PK zU~HS^U~EAL5!@}Bf_tq-h_(JpM%DeANWs7irs!`GR>}`yrTj_?jdEBvNd^VDO04O$ zL>-Q;rXa|~`c^#CVs${I-|8Sa6r1lF1Y-+jYkckrs`9l5V+*PZLZC56Fg7EwIv87! z9E^?C{BtpE&4qO-Rmrof**Zx-(q;rv;I-sO(#h(7E>^;+k!80b$QcD!>pxBk#1&xB z22xv*PJz@UNfek1;ms0KYRi+yr>3O7i?CdOA}m)ol0I@oTG&B*Ag;7QLa;T2Sqpp# zVbD78uy2o~2Q?5}?UCS?CMmR<;dm=whTv*LU-(52yyNw8Pa1>lTn)Ye0xMgCWr#j0~2tG+wF# zYhDv;Dk_4i*oNdM#F8#PYsrJ;i12gdByG^OJ+f`L8q93nCX}Z#P3#8-D)f+2Flj{uJ07z15IX`?T%; z)H_mr)@@GRnVMk=s@>FWZns%xcJ7kbM|8^%HJl61q&_^Vc6x3wdb2vPTo8qon}L9i z#-t-YRV`8?xPQq?1L{pQqwc*N3R-AD(7&_MU5-%bKk43ZNi~&duPSjn52QGvHVv)w zX9+vr%Ajyxa->!5rjV)Wosam|Zt4hq%!i*LKN8XsL(_wgFtgu}B-xN2oZj+?ZxyTE z6l_Q*+nAZsgHu{lu)9@;{2@HlU6M?tkau#B#66k-hrD*UFYs`YCBx}Dp%8#2!!e#* zFBBf)xaj;(G4R0ZlJNL=Qw&(%{r@IB-e5UA9t_~|Bd~tF3)LL!zIl8FEOJL&96oU= zlqeRd_aPcChsTSM!{bHD;qjv7of$Fzhfe`Qpcft;CC`Ry; zh+@K4GEt=S7Ql%92*T~<@OVfcLl~2*#uCN+tW2UvpGXvTO(NP!jw^!n>2mtDL{T}K zM@9U(L=hw?PsSd%0T#}qy380L#R$+F?hr1wA2fr3!t1qM8nDcNx!;NwmG%I8vwcd8 z9p=N&%!nvCTv4FZSkm+hqi-97F{m}BzWE#cjs8CVL05v;U@#k4Yh&As7nm_C(wG%x z%!)Q<#Tc_ir}~vZ86H)Li$xEBWJicSv`BBls8o~H9S-aaaW;E=}6Ski7EV{ zy&oTS-H)5oTR*y1hZ|wDHBPnb#%WGFJK}t?+Z}U7nQ zlYgzcNBlggo#!osM-SdIaA6Z#rVWq0c$be$+wm~a4A+dL?w1yxsB_m39gbtY%X=(tMKU946c&YZFB9a=2Z8B z>+8Ka)t&K3ox2?Y50dgVgI_YdBcM+IR}o9Ipo}7w-b)n9))U1qr>#Wsqv=zk_(k-C zOlyha$-fgGq61OGSfYp+mn_o>M8g^15S$`{R>_!0BsD`W;ZVk2mD4{b3OmCDCDOTg}i*C_>opf6n5WAG#&viiIUw!@ng@|2NZfc zf=2Ym?oZy`Iixe{-H!spHW1ihes%do)W^4M^n6s-X`a-B#QivGTu)#nlYN% zO|+IM^#4J$7h@NQ_C_o%{9vNUuz5uLq8>z%ULvR8E2poQ(;t@81MzEyBA~V>inK1E zJ@BK_OceHp%hVAe)%_r;_+7|Um^!wO;5Z^I7a-5J{ zG?V?H;HecTNM+Fl_<^U@dJCc+ME$>0E0B5V1pw(*jwJz%o#?0_2knDXHD4*_;w$`?f50Ak#`jB4HNB$a!xM@)OvpeUxA&=aWYxp%j~T$i0K{R zBY%-yybVF&f_lMI?*|_(ks&_Hr-P`d_hUHf3ZAR|lLx5Cr<~xv4!!t^$B%~OQ83J@ za=w~~@)oM(wUHS~UL`(i|5bv|u`I|TQRLeKzGO$X{fzE;>U#VLKGH*eAwSa5klx?G z$6xkHEcU;mym)k~0mvnJ9b~SC z-aR_y{aYmumq4TPeDS@mr+r6*Pq7b8XqP9pM=AL9w8wVvDeVDM?eZ#droM0N)oGvq zr4IXW+Nit;Wa_E!Je53k@Kn*h2X)H(UL_BY8g~0c|Fy>RjUNAv0-xePJX+Z0iS|tc zpPu?|0-w^pcywx1-rG9m1;c5IJUsf@<%#tj0zN(UEeD@c-@z(*Vtto_PfvZ{Q`wi` zMBXW#@-D}7ol;*u_yCy!_=xq*1)rY!ZUmoFUxlCKiS^wMK0Wn4qq6TRC-v=#&Z$S< zOz!b{rA~RDsN|(Mk@u%gd8v^O`_feM#P%ozpWj3h4*EAbN|&5lD^iBB<;rF7|Ud@Ppc@~H8tqcgKovLeHh$4r?Z zWlygkZF4&28S$diOKrK+`K-z5_Sx7x&5q3axIJ z_b#N=KSx$QA$-JKi~Eh1VJXXZyTvlBbBk>Y-7cPK$;-oZSoh0&BPi>h)U56>a=Z(- z{q9{z>0L{cp?H1EuIv&;epA6^77^n z9!v1}u8@UD5FS{eJi~Y(!n=@Cd0P^Jw-`>R&H3o3)zmlb&jE10>nArx_wd-d*B!9sf(x>tm@>(;${ z1?$?~U_wf7LrDRm7MW&SSbT%I(^fa!oxA-K96t|9^??iQO;>)keY8N_!>Hj zkftQU#ZFO%N_t;pvvE($q!>YftRTAU)JQOuy=uPQ{{iG$sfs%0J2Kv+ICA zR^`vqV6w*lOT9RsK3nekFSX_<}0`8BP8wwjVgiUujW4_O2%XKK2E0 z7ghdun*2@d6tG#9|EDJZ71kQJC*`0aQJS9XIHZED1d>nCJ;6?{>^p#uLcLcU4J ze?-XtM8JClyg|SV1$;)plLb6Sz{drAyMQMOI7G1jS|NX%3Wuuvi6v(2DghS@_)!5L z67YEe_g21=Ae-c0t-|erX}Ys=5WYpg8wLD=fIkxODFHj8zf0?bmFVQ8lk^R2L1)rI z_;LYf3Aj|iYX$s-fZqb9hovF#`F~|Z?@3l$!OVq?4%kcYdj6&{yn$szIg<2 zA*QzyyjvU7J6_=yVtNl&bc!*(mC)c((VAG_3HBJ^D5#179u;ZNh!ryInqir`M3h~1 zypUnnt&L(H6|K}QN?YeByDy@&wZ>-YvXi21>I3yR7z$_vZ1=~i2z)iTdIVSe%WTuY(FR;tS8MN;yu zxpS2Ii<#-=g@szbXIV?EmNH&aY8F+I$<_j^EqlDRth^+xXkLM>xQOpkFTXFw*myQx zbdD^VCl|pB8}1wdq9IF_N+>Mp_N)X~HxnNcrkLr|e zE1rvFRk_CFwBx;+^gbKiXl@AtN=c>ag>^*}6_;6a74tBdB6lip9CvRVckOH6LiK=O zQ(iQxCl`39AGtS+hvKBV>vIZ{>Ooo0=9_t^AL)!rsJ=?P8@RhaImA2t$oW{En|FeG z19k4p(S|#9Q;uVk)20jXPCxR-aree?S3E!yt395t;f>?Yr%E?*xL*C8@11^>Qs|w2 zXt(_Y?W?#)Es2eS&opWi;hc%sc()eHs+&JEF0hG2)#bP-R$SnB9X%-wu#s zUe6AZV{s$GwPjzOVVo2hT#5^Q{$q-low$QyL@S^4x-r2~M`Uh`lA8FUaz-?*wr65b z;)#O9>m9MiwUScmYI1^(DCHJtBqZ1E3;v+)Ldl4_$o2*v^WFE`fT{pQAir!QtIA4$ zyI_eBfqY5YB_CbCLWy7=kQ(eF_BgCdf^|s_>x`?BHf~>C$hZ-;F^uf8M;ebLB*h{3 zv&SJ1GQsBt_}mbXzaJ5&jqAu;i<4U%^sU{(+bcA^&$n!SQe9W}A@f<=jz{%I?Dpfn zEfM)Vk7BalSAjOMN605F6dzyl$>M?ms`G*T-0wsxTY~8SE&Ua)HumV;l)|c(q$SnW zMSf6su4Kp_)~EXsME{w>6VAlx3=dfr90OvJ-T)jqJjUxOJ5bTkH-XO z{V6*4@MA`{`%&Sg06kC^xBa*?YlQ)_PVL4@F>W$NnWuJ#(ki++?#J~LL4x7ZHW z->-H{dVI*$wf!^eLdc7Yxd-+iAFRa3M*5e z$*IW!GK|Q7{%mS6dP}SAmdI5*Zb6@Eg}PQH29Qjtu2gDY{`D3^0eIOCUT*v15&0cM zBQ4~qz4%Dngj(7?S&5kNUAZ@mRh6lUyNM^Va66S}hWrybiTRQIDjiW5+n(BxJaCD| z0|WCD)2Yr>k~}fGZa3P$j<B-v@QSqaEmO zz@x;cFE~QijS{~<05x~S@2^ay`27xh&VO7H&|)>WCzbA!erxDHdGIV-oqg=>>;L$8 z$Ep;hzE<0c8B%=Kpf<)1mFR~lz8eg6W?4FS>2*)pZ|zG z*~dnf4EiJhvH$ypR`A&WD^0{lAL-1|yC^NA?z~*1GbN*Hr$sHJog%KUG%c=~7PaHV zmaBNQ{v0WKKK-SZL7fw$(p&P#_|&T)XAgN&+7IIQ>XPBqzdw-o&nOvA<)}=_@D?Wm z7;)2ev#+jqJ0*fX?sRl-jv7t1+tZG&wmkvp`@4Bhh!3d?p-B4L`x~`aL#c^K{lG-M zi0%p(ex%kgtS=c(z9vsI#N#g+j=PWrHYKe{CK<$i;l~30mnNZ5n0>@{R{pjfVPyLM zQ!#LJ!exw5|CKW|`3Dc+{s5 ztA_U}^qr>k&w-?0K4`vHa)# z%Sd;}=L{}e29E>H&@z&`!+)*1i+`=U4aUFJnb-rs)fZ`Vw%uK>ud3!$x77bHt=)3h z7jbjeZcX4{TD$LCd7{qUTU3Dk7KNucev5(&n{bN?=9`dgas9m5rCDxKlDciKJAxB+ z?z##OAoATD(Wtqrpri?|l5Veey1oJ7$6B-9%}=}T#7@+?>ncaD!mn!XDky1!tNeJc zde`+=1AfOggR3NUr(O4|=2Z8+>y~LwbvpW8bE?zP@0_S}x8KpbAL&;^ce&p|Nt65C zD%bt4M>F=jO|G92np542f33RjU4Jz=sh#H?0g?3i4G2n_&=I8Xna5mTqUL7l2$H(r zT|WUhQRl9!9A9gAzS+PYA5R4brl|szmGoS>&b6yxU^BQ%Qn%%=Rk!1>Rrj{*FRkWu=3$T2x!dmo z?EMZy82rW$NloZ?(mT&BuJ2}pnx)@K>W;hqN_L{oU02a%BVD4G%C3TvWF+bt=ID<2 zDEw{~=khxX!(YvCg-Y69aQ$+oIn{mP`qz^ab?!Ed=zWi&|-QxNIpgC*zkVop=?Fa$(D-^r0@Q#2wrR%#wHG_F~y1s0jc*`A)>s;T` znpxv<*FQ9zXl%meCB0bL;kv&^Hp}HDsr%%wRd?>MRd=83%d0t^S?&74t2x!Ja{UC} zoaz?4zSx^n9d>|s^{cfx)!pg(#?qYXzHxn5aiY%M8^53Z#vdi$_@U(gYMbL!C<~l` zcvM93Ekkpc0x?JGQKE5-Jx_EJV=ohpXY4JagBg2|=n%%YZVJR+Zr>6fDsP8;Ib%P| zd^IxPDWc#Dz@#>kNAdLnufVi0qL9b8O@_R#gu&N`=rGJ%A_{roG9Sg+BfarN!IwuA z_TEc$GVCS_`FuNN$fr1Wgx?{Gxo!tRBT(5-K_fx=Hp^2OJ5TvnV%nM!G!xUdh(c~8 zQS99|ged%Rg^W|>e9SZC`I&M)#i0vKWNZe}BzYTV)Q@k&47*DxJ(;oliH^he$THuf zM8UU}DERm`&B=^?MHqI`cFhqZ;aAW|&>BjI-GM$x9|1ptMuK(%rF4o97m)!!Qab1W zIX#{z<_KOvGzINW6n>jd6n@Gfiux83Mg95q&cHVkM*Wu&MW?AE3VZJ-3VSyb#e}~D zMA47_0~#@!v0p(WLHTyiu&b9Z@-YW-08uBu>=E&)@ ziNgLeqA0(DXcl4<5`{gq^)dG!QRseyXbNK=5=HwT0*x32zk)`BeoN`l_cPH{*hv)j zpC<~x2ekl2zwSd6@&^z_eItpcVeTW*;pm4%;V+v^ZzPIxONhoZb_Y@P=QoI6i+)IS zI`k2p#@Jb+kbj;i^KEV+hO;> zq*0=Mh@wuK?XR%|wsIhcK{Yt}7K+5l0(lajZwhIAN++c7shj~sJIcG^b>gg=ov?!_ zzneTo6)&pW5H?F8I%%q9FyTH@C_I{4iTOS7t-K2`eu+XfpE`L7Q9QXp1$<6_vMKe*$Qd6lI#cVuw5hj0lkqQWGm(&Y2>wmBR&V8c!VHQFRU9m!ZxB;&T6^j1PR*k2iuON3k6}MR!)MT>2 z_Z9eXH?4Q%A*H1%wJX|={6%&t>C{)sRT!si5cmSXM0~t2$yC%EeVIPJMc`BP^1j!I zyqmy>tEb)}*5fmkJl=O@d6l5*_Wcoj=;rkfkZ10VT={6h7i zgRm$s1ANq$;vver8+-%6MDnN))6tN;mvzeX!L_K!nw9OWZwetjjAWDzW?^C>@zu$cMN=b{1=7a-b#Jx+NPr+`=)|VkGzd4dEF&(T%PE^ zx4@^ze=Q;%{=>K+KN_;{67cDoygm!Q(m1)-asevdPM89&k8=pKD?;q2eq&0zdOOF$A9mD zFBs+Net=7!A0$uo-{(5*3ypEuhc4TwypiD3(;ll;^5Duw?;DF(jIY6|!wy``w+ ziPzgA@ad`VYv5DtOLHRcXPxq5@KZyPr|75ln2eA5Ip-Si>8WoO_>}sNbYkD*;8XO; zY@CSCFTbhm!>>qwkbR>6I-|4ek#`;Vl=^0<8bBp@G14Z)``5AbjmZJ5{kTRC-Me@Pmg^i zDtQ(s@~U*o`&uP0S0zup-u&^Z1+4WB@qU^LKBYaZDtTgiOaPyr`fdQ9;=fr=vdB5tE7nkU$Z?Q_ASl?^G zr>DN_!Kc*sdX+q}zFWbkr@kk^r?f|@6L}_l+3S&)13pDwxk{c`-xc7~Q{UIYr_^`8 zN}gEXPjuSX4KEoK`xZKpmkK^T^}Sss?;k38VttO|hlI_3G`AyV<*a+N%> zeJ=%{p7zZLpVGe6rgQ}0Bew4X@ad`V9+iE!b7>9B`%$O7@N`Fg?^MYX>pKa2dg^-@ z_>}stQppqR`v~~(zuvJPDJ@m0KY>YUk2P|7L;hA|9%sR)r#<5El2z%?n^f{Dac+n>c^|t9OiFzpk;?~w zit=92DbIi(fr`8>PUH;)pC0>4Rq`HlB5wou^z^@PRq~#2A}{c2ee%YEPpR*dPUJ1r zDQ~Yz-cwHG{YR%f8e&%L+vY^xWboqK50`1II!qe|X$ zPULOYDet&S-V09Tb->F7J@!olpVA&LI+3?Tr@XgS@^-7_iT9Ti;L~$|3D0!gUtUqk z+lF%=%r=md*p=X$q5u`$gY%Xud@uNFP|%1pKRG=B^lg09_p4)g<$!2r*>b4v?KvvaYnnRP+--0V2~i*kE&qO`(Nx63ABM`e!+d$ui7lGT0FrG2>E zHr~69S5v~2OCi1iEZM>8>R*gQ`*MFpOzsJ?voYW&x+6No=MLD)8bxQ`G73LNfdGeLu z-NsAL4^93yEG(=Pw5ZG+W;KV6&A$O#SLB!HmHIP z?8GjmfiCm>vbqWu(utWWn5h#B!FdSlUctJXSkDS(?#}vE#Pq``LB$}96!fWJp*>mO zia~}xhJL}U=iSw>RIuKih_h#JUaB{p_v=oa{lOW`<|Gu>@$swP6|7r`p-Tnp5n|{H z30?W$E`~1P$$Tdca#RwyUeeW{Y+TnV<6;Ht)r)KBMH>2$U92zixs9@2*h!Y8;KXS3H3S#~jX{PshK>d#Xb!BAXz(CLjQ!aU;=9?7948oF z;RAX~3JnC8pfHtfCnpAjk|k<+y)j6$RvxI4**GE7)kZ$&%h;bC)g00}4gRS4o-sLJ zTsLLn;8gv=+C1xw@>$t4ZI-!K7LILC!|NsB z!U``fv*gYxFU0_&B%whjO`Y}fNtSf@v9_vw8qTF<-QARI z@b}Z?w_$O>6j4AaKTMM!EDRsFW4W6A&ddh9L{^_5yH~Du0hAKY<+prpO11{LeJ`N$dyUM^*X1Y4V4&3mWXt+A6mgF3_L@H`c64}6z^pAzr^0Ur_Y2?49W21tHK z)z<>yegYmQV2Y-p9K>HPV2YZd9F)ILz=wgmBYg^d(w_YN-!?rUv$&wBETg=ztkKy4 z($Lpib#(>w`NZrDw-zGB9>8 zCC6%$0XcVEy}Mr&B-8Cnb?=M9WCRtAh6-L-YeS5ZtmTfyd;-pmISVQwv6!U5lR;I< zaVX4_X_kU2JsyTi=@6$%A6##?!r;axE2I<`&9mCdc-v%8C{CI=v!KW-yBaSl>DgAE z-C=LO?C~Xq1!d!NErk|awz_9*pz+VT>c6D5*@?4sP^)*`D7v$SL#)Hn|Rd8c0RSxym{suWRg;KSV!bQ(30UUR!I z!8`Rr?;IX=vngX7?)se%aClPKvu5{Bz3@)G(9ET5^v!gkJbvMBUzLh`)?2emE$$A@ z7s}6SZkL~6bAP@J-o&S5+N_zj;#@p27Ter40&>y|i|0d5nKiczPo5qK%COEYwk`BP zK&Ayh(MJ}QS!dY_$~+O|oq8cXGTH|w+`YtT=BHbODw2Nh)C-!VW&mm1H+vxZa5uOY(0^j@`pT$8}wtQ!;!>fgM>&hKK$1 z$LM9-ebYDQhvtv1tqIs$n>xa9yuxT$`%V6ex~;udCl^(pDcJLj|A_$RyV`eMVy!87Uv0aR zw@sDLkUqaE!|@g^6AM_)MZ?~c{^k~|{i=*>jO+Im^fOEOm8pdKo7<%lW>uA``wAE5 z(D|6U&c@ekw`LiRw`{RG`I2fw6{XV0P?cdKIr3@WJ7#2eeM5DW zYB;evsg4=;)papYi3}5vWnWzn3n2zMDYdMXVdZPJty+yfW-vtN@Ap6dae(YC;z_JI zP=TETLdVvyD+hRf`Qv3LL&9PfE2+tchBT(a`litIX-6kNI$$Ny2W_!jQDDu3OS2Tt3yK zTPW2dP{zb{zIymE|HK*#wF6^&@fm*1Fg!5y%nZuSFh%9Rh1&V7?_%D6vX$|vvq5Ix z_3WJS_kAZT*jqb@$51tvdsaGco&GCFBkFwN=RZmon?}^dwrBmw&*|{<*GCe2bqST~ zkyaZ!7=5BPb@;C2*n`wVh--E7J=J4tx<-Y`Rz~LUg9Uq`&v*6S7ZYo{wu6sCTk+f{ z(_5z})%G>)uMHkIqIMADHrHjCN1Aw#>|!|HszrRUBU_xPFhE=4 zeMg{o4$ekTNxKH#W&?uuB-TDTob?Ye@2l(0+v1my3=?^$RVev~bVxNmU(Kova?g9m zG$pOYK_jHHUdhJ-*qkGNRh`p~>lf#nxTStoADCLKHxz_$^nqz?jVW|AKY!meIR7ka zh}MeQhmVxHCm_Ql)%*|t#7`3aulxj8!G`2olhH8SoDQ33@w(C#)qhuVM75L~(w=fn zyzgY7uDz?JR%y$xWIBKUC!;~SD!#eNcDS_JQd$)2Q08@r%fBrPr8lshJk@ z?1?Q`4NMQ%b0|GA-S-Iji}g)I%>uT+@}HX9-#FWC^($wC7+V*Bd0JOeP4-0Q?>)H} z0T)V!8}iNR7k*6Qe+^Xuk(5jAOLu_X(W{e7c<_c62F!Xe*#EXpG%`K^sX!tx2JZSm zPE)cd{KG{YKFoMyoA#}-INjgiZ}j&G@C|4Y;1}Q@5D?HZATXene^5XhRL6eM{E0|> zXy*Z%No8yyXMytR0T`3!Bmanpz-I(tY?_x3l*9bT$zl94tLzdg3PZXO9mp8Xm|}yl z8v#+wj0+`tnLH~gjL}3i9_Ak`+z2EwhUrdZ4~u3jhA93ZiYqs6Fi|Myvx}g27-3A| zLX7$5Zrq*Z~XA(ud#u4qrSQb(6O(u%^@mWNu#8f$*W+br) z#+-_WHNa|4H z)8E)(0dHE&gyU+^WYjbUR2>cN+s0rFa`AabL@U^cMU#ZFl zF=oXYv*L_d@y4vd#;hU6tOTE|s7QRG@QKDJ2A^2oQHZ!)oQa}$Qyx*HJ@|&z|X@L96#Ad>M0#g_R>Ro05 zxXfUy{UGC|jTbTDi8lsn)C9|=9l`!(bYVFzhGuY+q^$a{ROYe+G-u6Rb^s^J-0c9= zi=_^LnM}L`KuHriKp@|FbB~XU4uHE}Gjsq+8TNB`eo;23vM>GISLSY;;N~H>3FZLv zHbIS=&?eG#vc}bQ(y>|EL{j#$Iyj!P9Otw27qboU1P{C(7J)6B#dk?c&D>cN3KS zU+t3Zn4KMxyZ7(=vUDDC8ZKX&upM)C<3Th;}0i zJNpoYodbx%&S;{rlh5%FW$aeq9;pAlpfe%kexmq1OzHT2r`aVBusOHJBXR13`eH)| znvQ;&+7IHR{v#f(kN|hv4_fPxgMw5RuH^@wFzc;ux(Riq-5JG0T-{WN8_crJ7_vb(Q==+?GJHfXTx|Kt*oqp4+8B6@2Q|QVM$>PShbFe*ho(%cx3+3+ioQR|h`2PKl55=^!fV?a@b{-f7@d^agQh z4a=JiKGGo`Vmg}5sqZ7;Q|gOvbbd4>?_Hhpf^i>Jh+v-y)SfT*{5w zw?(JCV=8&LRomr>?a>~U(9<4c!KbuGs7jvLpR>WIr@ouPhyT3)^>!lfJ)QE}4Rpvu zSL8u>om3Dce{~iUO9{(K$pW;89+T~T^Onu)tiA+8A4Z-)l;=fCs z$jbqr9(h|-^6(YTkB0pBzD{}VVU%JYef85p@&2pB=3|?c?o!aQtFGBr;W<9fKQKokE-MiR>>3ncL02P{MQPNs`xKKB~R>s zA>h+vUk><``d;ot-U^-a-dD*}>eEnroYpCCD4u&2`>s;iC;D#&_!NCI8z-< z{FkJXC;D$2`1JVil*+yoC-S=C;?X0|0zRd_3P1TztZyaw^wjqa@G12juCi|%&hdC# zA}6s=!8b(#D!K>fEmb%?62ro{(b4mUpPWwiy^W9h{`V^`?jSi|O+Euq%liX-nMfmf zqh&^t7ZDX78N*kXOMhHN6pxP^EVH{_jouxv0C3n>qX&}ZO<7D<)QX@Hcl6PdRHHMS08HEU8?8%ySwm$ zPxg1WFwIYMyQ~~x(cSXi)ra~gma12Mj+kq4ztQ-Nes^2Uvt?U_-oVf9FLU;;KJ>0W zv>`YV#cCH;?_*hnc9Ookmp5MnIDT%78{Y`HKT%{vk2E9VgWCeUs}JS1gPttUQ9q5i zzhAG!=}?G5~_E7VMb z8-#gRABG{=Zg~+xp3N%4?vIvS3Z#NXfjkUoHr55o0Z|%Xucz!0C_cIu()$;BoNsjD z-rqg;v*XPu1+mt<3Ne^H^X8YgAs}*RL)X2mTUUc=FYD3O5K=(_q5JTF(0%zxK<|n{ z?Ltf;6)_>qU_x+alc6iUoc=q9Pp*LdG4IM>D zR1Yu_Uqb^-*gH0!wu!YL%1BQf#&a5sI~*CCAPx1n9_cCX!%ee~^mKP?q=y1e@}QWi zaRezyraFqSDk|mQB<}D|ILFcCCoaAt<2Ila$M!#q=o>t*@z&L8h60O!Ap@DjBLvCc=vEl~bbrzMgBfD0$J`P>!x=^*?C;si({3DrH1_5w|D9l zxTaMVV!94Rl-rhu{EB=Y+jSJ;+8SC{8P>4=i}PDoU0ru%itn0zI77tGkuBC3aE6GN z3;fm?3R+kBuSvq+fHj7jd=|EvRh}f{3J$EY%8DHSJ$qD_*e3Hp}zKbp({g=JnOr?broAPE!|Mig~$GE zUA59gsH=G@kJ)Knxzc1_ylJInF-f6lwku5(&vtckH^j0{%5TNv*~$?$6M08u*xGpPs6joMUonAu`PUXn95!GLw9kMa7#)laO45%jmwXoZ0E?jBanB#jQ zl^OEC$w|(C*uqw9yd`wiH@C2=y(}?+EDABNH0`VF#iOE1bqutZUuiNPF%C$qd9Whr zA^#JphN-FkC$3-%a$d|~RsJWgHsE8Nl4?l(J%_EsxsT8BL?6TP(T2d(p_YGGD7V$| zL`FHmsXoV(e0EvRSy~-W;we*8d75F!jD<5EJIl7Ssy}B8%Uw{hAb(NrE4i&s1Q`=-t0-NG%(?*S)6z{mXBR*3AeH9lUHJKs z*~HV8pSLkd{_9`8VD_~1K0Ix~Y--28p;LG(t~42{z!NC8mjSJ@nP)$Y8$6}%lHZ9ItysVGV=dVwN0^y~Qrf)k@m;U3W9E5XKd3ujvW&N` zFU3?Xpq~6}I_ozg9qs88xE?WTeLgzNR!>bIm1a0dUTI4aTUTvQT~RY_$Sy>6Z7}+3 zP>zwg{7=zVa|{D8r1<|Nq-v-%tVz=h_yh?|QQ#{(G1Y>HasWV-8^#bP0<1hFDW4C3 zOdbjVW6xLx&&Ncu8ksX=bt_{%<&dgoDHIZ|W93W1A;jalV(lx1sxe}XYg1$mB)jB; zhHsNQl-}BMX}~i7<$fz#RQle=gPEpx$oE-g=rEruVQeKU3jC{rnWjLio?xau{8$hV z()gIMO_%zW;FW~Yw79rlI8(GhZ%RjglhrNt^F*E4Sb77R(i-Uc0Zp$&szurwo_a$Q zwubNFdzpdao?yh78EBG$dUJR)a0G%8Q7?}KT?QJ6*;LOHMQ?wZ@)476KjnkILFt$g z@D))r0v^fqJW*Ud9Sxwks+0g+g9xMdT}c!(8gf7*aOuqijRc)d>5#XQD6FIj7lF9i zHiAZA{?DVJk)T^C9em-Kus{K*Xai%SBV;;3rZb4bt|A%pKwIEb0&K07(;t;75445+ z*9gPz_lV*azyoi=?r!*y-I1W=r+85EQ!1s?1TBM+4xBg(X+_!UBUTMm=cuG+#uxD& zQ{^kCxKbI{DJRgh88Z@Kls%+RLo>*(1Vaun2?yQ#NVjr4h)Zc8zd3=hx|wNp`#(acYsd` zDIsx5e?@s8fo}k^NFH5ebTlOIoKAVky&UqCZcXyUcAE{pVO*Q`kLc&ez^AlZXPK4c zi6Jsx0AE8h825lz?Z39Y8A~)s^;NDJlJ_<~NVXqi`#3^q*b{N`89r)x6TxRjnh_tm zw&@^wG;?yu5c|AIvssxrNz*ACnmHLiBr-~3cRh3RFn^MA#K>qxrvG=x$k+v+IQ)C! z;sJ7$e9&~opB2EVA3LGKG(Aw8@6XyggyCKsz{5{EiUhFUa=saf6hmW*jLCEDXzuTS z*|zj9e~Eh>YJ=W=H4+j9`?_ll6 z(ZKF!jV^KWWLdv=CYE<579SIHta5G2AeU-VpLZr!0~e?_YDbp*#K!kVC@CLrPm1iPha=H6%t~bBjBT?EZ=I)E~M(yxM?f74siS;)R=ArK$ zu-+M2!R(1$6&LtmMQ{GMR|V_BqkDAiM7!$*vuC#)Xjc)_lNmZ!uuh#=PdcZqWdGjr zJ+{Ms8UR&BX=wC_Mz&OgqAVAq0k^A05RlCeadh@q4C_QG!&nLvCjb{VYGK4EA4Q<> zONoMsZ;Ap`6r)*#V`Cc_&1x(T2*$n=^p0kIBN=Cp1JatR*yPcy|EoA4Nm&`;ma;Ni z!Hn`UYpKd7@~OHxeA$VM&mrBBcH-i@svceHikgoP#6Mgv8JQya#!a8mk^e*&wCp>~TD7^buxi=`hHz>R} zD12k@#|phc;k`lOmB^~zh5p`!{yZqX$HB6_!%K)5Aq`M@hnFyJl9Fk&X4;A=CUmjQ zgOM(XN-r#)4^eVBY0qSN+|TRJm~np~$2+{#(8fK|@Rl1x%}x1X?_KC0MXU9(fFJwP z;00b-ModgNR_*7N{!c9Q*St&&$JEsSrIr5L%IO_gs(EhT$yUCJwJqoEOg5Yfy=NZ%udisYPIaK)>bM9z5h%>)E-S)b4cs4#6w(jNNZ(Q<3p9AwMBF^G^%wSED5b=jkGRF zoqRKfnJ(2asWf{&U*Ih0YX!AMZ+?TCRMG?4vJ&c!u{UBIWvwlm{o zGCpc~J-|0o%^;uWfhwbalr#%`tbBjo z6xt#qJEOR$EOkV73MEI!#YH6`NWN>%?AX{LjWY6Kne0+)Zb?)^v@J>xUwq^oU3>}A zy7;1_V|D2TpFVkU@%rS&#p{w6Gen<#anVsO_0F&%4m$ z;V%bwOmtK1*5f;e?6@e`JkjL0+#w9Vhuf@$dTvdMCHlDK8(HJb^>1dnc;y?KE?)Vj zriWL#40ZDIn~^SF`GVESt6Q#evFeel-0WQOsxCnJhS!7=@=Z^F3B4Y7SQV|)myQz3 z4N$*Tdj0Cqq1*`d>rifnO(-GX5cQW(Zi-DPA>SDFmr!nwO(-GXAoZ6}Zj$yA(pE!_ zJV`0HL)W(|g_CZa^$zs|G0i`^4;+rP6BnP7OLXMv{n(2d+@HO!!2|5`lO+Cu>}xsS z3~IoU?Bl0Av+Yfbs9*e@D=dyAQE@DeGxR|Yy@zuQi9JWD&XS2s-d@Iklu@_{V%JKE= zbqy|IAIVs{AI)RmYw&z_MuQiyz!ngML*ie^y31I)KFV2y2A8oU8B6VXBb%%#e*>GN z!T(@4Yw$~KjRx;#k7)4A?0F4-g}p6fN#CpNYZ*)TlL~f1gBLR&`OS)yzl3$t;9J;0 z8JkgO1G|}BuE9643>i!PWf{xWlwZo`Yw)e?b`9Rk9?;-@Y?}t}XZtnyU+fbZOZr}8 z$7L+}|2Fog2H(!wBDM=1QvMyRmj>U-;$++hJO;el8Lq)A*i;!y{eLwp)|6kxZqeYC z>^=>CgFT_aZ?fGQ{1!W)!Edu~WGv}>hn>d`P!S}Lo4Ze>h z$#?+gzl)96;I+&u<3ygnp8Z3{W{%gfRT^By9?{_U*mD~EK6_Jx53tWQ_yhKfj3s>s znUDMiZUEQ!AiG3^A7cGAcq1FC!JAlyjHUkY0L#|k``Ps}&gAkpv*nudkFX6I{4m?5 z!5^}H8vGIaNP|CSKWOkL>~|SU`aWfC5&n=4$-c)~s0Kg5Vl;RwOV{8h*;E-z{oye- zM}r?_i)5Sw9R~I^yGv94DfXBK|C8<3;6vbl5E&;T z)xe%%VH*4_yGnz1vMddLj#*_qf|uXH=4ar+fKD=&`b#I)OM^SJa2Y3Z{$O^c2DfEn zH2fV{o(6Yh^ECJpwnBs3vwJnT9osBp$-d)kn+E^PUXroopYPe*8vGqQq~ZUS{i?zL zVHY*{Cl=fW6{7>sg$9Ih>?30{k__xe7Nx;Iuq!qA7dAcE7jn$>_!U*#Vk{K|?^ zVfxjT04zW9!HZJ<6?T7iVOOd6eGsi!Tizs;m+~FuO@cjL1so#aZUXKu;2r|*DPXgJ zLj~N6&DPYXw@{znLVbD*<@*S@uYmgrxW9l02za1?2MPF60bj=M*4Q5=*dHd?A10I! z7jT4tBLy5K;AjEI2sl>2aRQEKuWIZcEZ9F-uz#>neu#h*1Uyv0mkam`0S^=Kl>)v> zz=`ZX8vBz3`;!FwlZ5ig0!|Tds({l3oG#$u0v;jYkpdpY+6UV&ZVc*<7VIA_*gsk* zf3<)!1UyE-V+EWk;Bf-Z67YBdPheMQ?4KyuKT)uMqELR4fF}!hih!pIc$$E(5%6>Y zUn}72*i4Q6*@FGqg8kV-`5XaT1Uy5)xdP4;uvNe_1w2c@`E0eu{sO`N0>SL;9CW}RKUwvXNn6iA3kikVE=N#{^dgX z6#}jl@NELVUBGt;_)Y<@6!0nmuVy1O_OB7_UnAJRMkv2lz;_AwZUNsT;ClsppMa|b zyiUOD*+Px|8wC3|2=;Ff%HJ>G2L$|}fFBa@MgeaU@WTRrM8KQbR*n5z1pBuL_HPl& zKPuqI1pK&wpAhg?0Y53=e+u|10YA;Y(Ad9Cuz#Ci|2Cogb^-4Y@G}B_R=_(2{G5QF z7w`)L-o=8jMS*hoU^Gqpd*DUE{uhPvF9~?JfL|8yD*}F%4b$k~Bk12F=-(rh-z(sK z0^Tp+e+l?CR;1DYx}g7cLI3MQ`8NdorhwlP@Y@1@hdrdx|E{3_T|xi5LizUu{Jww> z2>1g5A7lqL`l|)~)q?(Nq5Ove{z$+d3-}WOf65Fr|5QGF5RP8k|2`A+e9PDTBH9?$4L2(_bF0-s@*|v&W4NDc@CKHn!PV?e4c@|D z(%{e7j~cv<>#_iey(VhfUK1RSr$K6OUiU;<#~3kGP3h# zskGwUt`+AFtpw~^0qk0Fu9l?HiaeE8jwD{pSF_huI+wIc=dxBANLnQzX_d~^k{nv4 zJVmR5?7Xl+YFFgo+^!Yp4y^?2S^?}@ajur6(TY5kR*q!exOhih`MIo>pDS7=AZz77 z*2>S-l2lrGo?WYq?7Xl+u4`O8&h1)p?$AoWt`)$p73XS68m-7vY2`@b#e7O2Nvm`& zX_d}ptum0bN=R3pmG#qv(q+^-8ZM*=wjxEem68No zkyOtPniZ^-&r>w=d5TuPl%$c*lQi|=DVo|yDf}*{su52Wd?BX^rBMToFKE`S))zcQ zw6&fuIG5-P++PG=NGWPxNGTfma+2B?Qj*#iQi{4Za*E&!DOKwWB~2(T_ySylFQgRF zR?!y{S3O_QOm2;@`P^=eucZ{Nd|ph`?<6jbFF2E?Hd2b{3!W6-U!PgaNd?BT%eIcc2SEmN?%Tz#vEOKX!OMX`ud9QH^EQst#*WQ=l}>Nu56QE~{X z%3Ph4nwplCoicXJ_z8|Oc0-g>cF))oY}Qf?xfbgFr9lBIj6N7BCbZVCj zyJBU#`s9T-zRb7Y%Hil(>>U^$6;FR-q8nZIt1d^&@1o-xWfd0R#pvRsAHlJ@IBDTs zoE}a*9@wJdb#l&$8mxW_1+ctL&l@nz-sX zDghgJHnO@*x@a64__J+vWQ_g-^Z*zg*?1%XQ3HQUif%$*;!hXR(fTXRzm=n-8?Uso zP>z4sM#nW?S%s0`cw)s>$SAJe|5Rd6wdNvbFu%Rp*E%=!WnTYl-}QIC%t4z!W+xTS zDz+7r<xStUol52vaHIi5ZA zFlyyVy+R|-(FytM29-=#%vf^naIkY`y3I6!S-)g{Khi6iUuC+P>BiLrX8ktvJDgt0 z{JPc6Ot-=&FzdIO-!t_}=63?;%slc4Ux4ql3&{aWu$Em9o2$B$H1q*I(scAIE{z8h zacLWWwcxr6{L#QQ8-FbDM$Y#}&bN6tX0~q~=-rsvyD_tOW9A~u_`EsUh{9vFlv*Q7 z8i|fx=#88&2Age4Oi|UY7l`aCN1AnCfUt|9`+~+>5jf78Qe0kCX0^GycM58x-M`RH zdmNh=HeG;sV`lHh%*vL)2wQ9QAQUvkPxPp`H*&r=a=tfmzPyiwcVlMz?+x$9%#A%= zdL!q%cm|grZ`|Kcz#BPV*Dt+-LaPlC;Y&e_%FJO_bJ*DY8;~&HVk;^rnpK)@v01aN zHe0c+6sdUymRZ@Qy3UN^3I$A+cv$t>=z1J z-}rHJ$W0U4KhpiV4}baS^z^Q|?WcTt|Cxus`u!_;Hor7y9e;y2%kjDFDZ+`N?ft1o z+xcxCe%I3c$3og1w7z<}^M|EB9~ibi^2U&)bxJrTp_Bt2{^-C>55NA?z-KHs&b=vP z*xIYBN6f$M%N|E|F59?klj&)5@)vSILPrtJncrMFAeAQ70i2hnm?qNExT`K+yx=7B z_1o7x-8S_VpOdLmo?N?sLGOvHUcb|}zc6%l{HITk{9?>&KlOg+MkmFulEVc$3|5`V zq3~2Gj?30tlM^7nwvZ}Cd$LV|8U)y`pqcfa&rcrhF_H3M^ z;T$uMSk!Qyt5hF$fepbwcMl`mL(%g2q4X88&qaLjMQeXszZFpfKHRzE?KvIe&wjN| z;U#)r24cA#FQ)JN`Kw(QMn?9rJ^9mPZGWt||9ex5(7g7+7nl4Qc<~flu_@)adC!e? zt0T9!dHl{U?M5u@v1$JArJuatXU;F}f^!#q{?^5NE;acl9^JI}Q0}@Nty)%BoccI& z_~183bve9v%eXD=*ZmMR>-C>IU6miP@xa$N7Cp54$hSQXU8B@TX+;HFrat@CdoRsA z@avqRyRSKRZ~DWFTO6A|>D2*Uc!W{+Jeb!1$(~_72gle-O4H+-1g6;2aS*4-ep_f=iTpp{`tvYU%Bw{FNY3H z8S|v=?&XTkCw8ZXbbU;+W!nw;ZDQ`ewe3^4-Ift??a{BFy!3jwxfDW z_t;Y}R2Ua+@AvdillQhcG4_iGBCb2UV(XH`*k!L?axgdP*2e}+x_@p&#D;x7L#}u$ zC2-WJ!apCq^v3(!MNNGEr$DPMoUQ@yu)C-AtjgJ?U5SC3Vr!W2C)clysuU_xGG# zlKkzb!v;;Co;L8y4p-LfI`VKQHHX&kYTpvq&WjU!rzEuM|I(p7pS`d>HFHvQ(&;Ck z^$l7Y*kWgB_v!6Et%#28)o%Z!kM{YDdU17!=$rTKobyUhn-^klVoTR8{vulh7<>czL7oHXM4!#8GE z&$cZ5X~)riPZr*rs^Ko6Lf^IyTWn(?XdHRM9cbWn>uAMgbd##_yZskbWxG&Y1^+(E? z9S_aB{)w7*ZngaU;eYFAkH&%LuGIrgQSe|ae2rj5rQ`uSX+1F@$A>pBHQ zAG!Uz=!?5oys~81rDv{Mr`BH(x!>3?PHW?`uhSnXC z={I9vX1{KItNOiheRI$6f9J)Mw?5eUv8Vp{;bo;9m7#OxJBQ92k~2Ez!~R!Zap3a0 z?c?9u?$_P=^0KOV6JI(0?2mU1-FhhQjcNDpuR4^Lu<6vsnB!rK7x~PuP28OO{SPmn z9iDvIH?`HB=bRq5XK;Sv^Y0$GE^5x?m;;w~da&({qmKW$a>LDCFMOMPbgXg@BK_y^ zQTq6wIHxtb5C6LG)qAe)bIYT}uZ+BZ;kxvxKhL=|;hD4n=1GT7-W~SM%%!hXe)jg* zw6x5$4G=LsVSf54*Pd3{05_ctK|ponXz%=KX?E8 z_nT(Ex^UOW!RJ;T9DcuP!qP`a?CkvK;{om3oIkhuTI*|%^qc?r&=H$fw_y)MiPFc^ zvgtgr`m#kG2 z4jX)GaYpW&BEN#^x@n4@-v<5s(JyZ;9rQqT_-%J4OnPJ5@(!7+0y_G%Pg;DT=>G0q zOkrn_&S|l->boDW{PwYksApdYoM#(y-Grfq11Ijew$?at$e;;JjwGF#TD9S^+h<(f zy{POd^T{4>?pQgv#qF>5dT068>^8?%-`G9nh6fhk)cwGYoWQ-iYM$#5_4!XXc3eN; zmF}m`4*d7pwR@@_yteqVe)o?0s&hQ~ihM(LP@eD9SnLB&wA^Xxvmq+Xw7Kio-!C3^ zarnSp=ZB8C^5xgNJvplL$krdcM?Ucf9q(>utl9OgWVB z!`!X;+iH*3#Z|xa=Dy!=m~`}5eh>+R<*Ke(mknGuHfZk}^*#GYH0FB|uV zD*OWRuDize`NO{^E`5Gu=>NywcYrmKeQ!@f3y27U3W^vM6$>2&J2jw)B3Q7j z5FrpWK%`i9Envlt9n^L0Z7tZlg1YvGeQk@o_6n$oW#v0(G6Ta9bRggUp56a5SCc#U z-uIr{W+ubD=bXD_UZW+Jv!(kxFYE;(q7FYg<}_~H$E99FC+F<+ce%fzWL5K=hF@*_ zKY259aKOp~odSo2Z?i47-rYr~U25bquU!k9M4jur{K7MB?Y+9QC!YivK~cHCj973a z&Er_Yswv8jZKQfzx(N0M{pQi^-QdiG*Na<6b#7ko@V0t#pQZh}`n=Ehy}{VlyTYaq z($4O%WYo|W?ab*#qLS}+hN!-28amjnVa^GG$6#Zy}H1_;J-#W%8 zKe+p_rT14}U%K7Udf(NiQ+pj;F#Aipc84Qo`}^FNudZXft!ix9XD$tDd zm|wkF`Tf|czIPT)%3C~S!-H7Ai*xqQ%AM~hS-t*3+m`biz7rllYI#37te|6j&gK(K zgauCr4x77txdWs8jqQ??k390u=1iXQ)hWB(vIlwFM|jkmJM>J`qw!|%#+^O1$fu`v z!-Tu5&)bdxtmHr7b?K>N4`Nkm#CY>mN2_ z-@wB|r=;&OtH0w^LQHqRKV!Zg7fSq(x)}Go`np-K#(RpN>OD*uldvm)TgcHL{_b|P zm2tw8WlKk7ba(F)cU?j3YTjq}?uPNhMDy$yTP+rL8ri*xnPaEf6Pzy|bB&5~{e5+s z_C>)U>G%{){-zS-bbTWIJ`n9VM-H#18R5v%{^W}0F?_aK*?cY*6>sCwi9=&RWu_&eK*zDS`|BkcjUhl8&%V(Y(yJ1HY zk?Xrb<63WNkzVtH&}_ujqSa?Jmj|@5*?ghL@_i?5;uEqHKJ?ubS`yl6*wHheJLu%j zEt0(cIO5^WzebMfw|3k;k4~++4!f17GvdZu>tXv3=o!4re=s~`b#v3uUG=`Y25+{E zHut~RZFHN4zeqLSQ&KlhKK#z zuddm4hcx+{YX7vqFQ)fde{y6aT+n)q|NK~(2M8(*)y)9>@f zXGXiu9X?X>d3|61#S@II(m$+|?q2<4yP3mTxZig>zV!*{_DnJ8ZnK;|DW9K|{OIYJ zT=cr1W9u);`UA%9(VJOfe)s&aiw`~wYEgI6!lPqu9%R-T;(T$*;Sitp$C@1e>p}DT z`?u{){o>#s(E41zap(4Ly)t8QjJCt6-VF!!p8d+s)OX~uGYzF?^(DoN|2}d1c$?yJ zy%hr`>wfy<>&(EOfzoE(FAmZ>U4Phx+b>sc7{Bn5^`?4$>%P=>xqs`{gB1^5O@`L{ z;ceESRK=5~KFab0R|b#j_+W3(Lv6)=gRj=|8uF#hBd=JK`M>!L z>@#=Dv(PE8Puct1t*$+1&ssJ3T}D&JZcKhV@7>0d$yr7gQMX6GcyHQf{i=N(y2M_4 zaeiWP)`2;FYy8!DUBUJ_n|BS4Pi^O$cHyqm`6au0FLd?n@*sY?++&KxmaATe{{DHv zL{YGb?w{>y&e~>tDs!!IORK3*_KXu5 z!BEAwaPyJlZRUIYdfM`(Z=cJ5n|%!KkTm^ikIXltV$x?# z_d7OX&u@;6(z-Xga>ML#cT_Qrhl~fIa){lAg=*&e6Ie9DccS? z?ws;9J)(zAo0@<1+)g;3n)=e|kmaN?xmTKu{Iv3fY0ITj@vUE8?Hv-3<5`krb9M2U z6K+?B1VwLMmeXO=gCoAL-5b9cxqfy}1L119{>jER=D!VG^Jw+bVSD2Pl?(3fc#`+5 z;Y?csJ-t^iG(Elixng77l8~2rPNsz4)Zz6Trngvsb#oJwz2hxzZ?CKBUY-8P5Pq5lQbN<2IgIeDEI!GqdekOEI>tK9*{IG3%+Fx4VRC}``u5P29 zmDFoyd$IAoQya8jTx%cHEp_emS|8^gcq5x@I<@(Zp0igSIksY(&P4-JLPx_oGdrD} zaQr8e?m?dxP1)Oi!I?V?h3$5Yxjy7Y=e0&@_Uo?P)q5~@ufrIh{JOn&x0^xBwc2*g z@6R1m-)xfHXzQBS?CDeE!-ikaj=%F)&w_DJR{Nz5>yooKwf(wPCBB#B`H_|l>x6V{ z=BYKo%OrK~NNb72$hO7Yk3DskJ%|i_`L#ujy+eYpUs^c(#r8pKj(rp-H#{=^e!w1& zk~d>Svfsyda-A3)k||nnX4yyE+1sw0XU-Lv4QZ`2Zf%D*C$D=I&#E_3ezfgu%aQk2 zUG1?sZdfY^agSzh)8)d94&&yvEb+e?d@iY5zdK=dWoKg3<{VqxLt1~qQ$y{5%)qRm z_roL`eM1g~tQI!^a7t+R!}JH*cN-l%e>?DxjBTm2<-3!n6=aTSx93hwlgZtK%nqhK zFv{6s81&e?z&q-qtIM;qo)_kP^3p4iC)VDOA2u&}YS#RowL5HTxZN*alfN5&doyjU z*m>#1xBl%z`-X3_oqTeFokK~g?cX`aw)MiaO`lAi}LKUh#N*%&g|Sd z%kiAvmoqL~A7AS-h62De-Nc!-QLj8c=LD* z=@d_kW*fVE4(i-T`5ifD7kn8RxH;#^{!@jm*4Hx`zx(u(8D|RY4OX^qx?#W%uj~#* zWIR9X>AJzV?#E8E?wwokTlXfLeTO^$IjuwZ45!tOqndoEn-XzY-}c_41B3Sld1OR) z7Tv9i%*Mt059v2meO><<$Ls zxAK=)ljjfZzRcd)dO+mw_O}i{+?qO1bgO+Ws|%xad*^R(XmvJsYee(uw*t-%9PA&~ zt?T`}J4{j=r49UzSW*9{wXg}Ce&OGZM_t-@^m+D6=ZL;PxZfYEQy41kX11lP&geSL z9k+KGeYIpj`k{||Lz;H$HF4yUoV(&}2+rr4F|U-uPzSlEk$B1<;v z{M^0c@VXl=Sjkskx!1{dVd&l|qVYrax?B!8+4-rS(BYJ0;kv(Sj_%Ox{KuPr9IWfG z%B^EUU;6-y?hXD}n58#q_|VV=>vzA2dec1B=j__Cn?=2sng49f7danMmyvFN7e>EPH`DWgN(*rMl z9-FT*`I6_bphY$us+cN}kn6|1_<+eQ){aV@KL_*meJ-+)6&`<)`@T zrY%yX?}~={v|iuk-N7e~>}?%87EPG>=vn(Sg7ahU?|ig(67jRo+1)ME+c!QI-M95P z{Ti}%_tTC#cPMIp_3pFD(+V#IEge0w{)%liv*Qk2xjrzZ=I*y$J$_cYO}gGAdY>rJ zPm^cpFW-1}o|P6py&&@7PEq%jHLqB`GAwG){LN1nv_0pKbqPqhzNvm~uQmpvVL ze!`SS2J2*|rXJ%K^hvjhei+|3T-j>q4+F!`7rNd%bH+ota^!`c6Hcx;>G-phl(;_X>zW?798XAFN4?WAweLH3 z<>*$2w*7d*Yvs1CQd#>Qri~N#KDm_B@x{~CN6s`I`1a|q4Tn#@UY}ze962ueI8wJFy%?ZuJ$&XJTuyGd{zw6a&7$X>#p4w{nqXq|6x-~ z^q4E-3N5loKM;{Su4GlWk}uM&?WRUu=y7oUn4LT2qA4{eNoL20&pQm;FFipt+tgzJJG`rPc!{PN?miHQeUXu&q#c^?tjojQi%cEkc(M zJeu5W?v7)Dp`rznujfUp_7tXdINRvQfqwJHC$+sgAodp$VUQ z&L389_liD2($(1q|5|@zd+3j@!B;x3th3l4q`{FEhLioWhqvqG^T03pV2vS~JhS9$ z_^i^|E84u@DkJl0ZAZvR}$B>BU1^SHgAEPXy6IymNboAghMnr&*ZTQ~mCu)@_JBHJ&xv3}&H%r%|w3`*>E zU_vK&c`_?``_K1de+#vlH2J{Sb;r)>9?02WZ|bPpgDx6HI`1qdtoCF)*gWH4?8i%S zj?LFi`QvtB!<)mb-yE4_J^%M-7qzx7tK(#n?OJ!Qg=3F{4>nIyxXnAgs@Asm3$F)+ z4BUQTv|-M|Hjic)_cNPbf4|n?Hz5XAA14fYGi|Ct$EF*v?0k1IIN*zy`)8B+#a5x~ zMh_bJa_){+`o}LlTmSL5o6QVwKAt<{m?A4D{nxvnJ!ImyTV7|KXx`=CMyFLV*6x8@ z2KSAc?He3@-}!N#{hH>rhd%DHF(#*d`~LQy>b(=&IGcoP@*Dkc(*vu2z3H5AyS`_3 ztZ%w7{8a0hL3eNb?eyoG?5`nl7p}IAu?~&;cIaOJOi(+=&h75ZfS+KW@!PJId?;ua zFevZI=USGt4v!tvadMrpFRiEQ7uLIf`;4IR-lSKfgmpWIEx5O!b*H=LN2E9AUd@hQ z)3!(G;&aN$dXCR;*U;JLf2>>oq_bms{uTYQq1$kWS1o=`Hw>9J)v(KBY1-6Z77V`S zS~$C5+U0@c$0-HQb9O(si0k%lntyWp2Oe4D?4G{cZa>Ik$>8S)6Gs2-+fmCdG_hb+ zz?Spw$=g;vx$Y44#(r#+nXIta(mtNWEq=AG7qn#2^2j{_jiYy43^lm+DE*n~R-;oZ zecGj6ZlANFp7_IYGP#N??{a?DZd2r&R;r@$u^Mdxwmld9~tL1s=`o2SYr@DB35)FA6 zmNe&Q6KnIjcUyn`_}Tl@fxrG((qf2U(Tt(3>NnUOFsE>mqjaWcz)F)2Ij7&gmgF5B z_i^CnvFCPV2wtisElM-TuO8Lk^ladZ-jdIlOOiHxVCM~?P5H8b&Re5=CN` zM%|h>czt5jLx(N8=H3qLZ+`BSNd&g4@kdV26q|{yHtDr>o>sHb?c86d9FA_W>RqOz z#QDYjXV(rnwFGiHzDr0{c;U7d!FU)6jy z?4;77r`adR!hxej8Cy=@?9tlv@ZTrejd^TYa<%=L$!Zg?>B2hmuahK+aGG!N-@W8 zcH@l+^MCzvc*Vm@BVT{IJwiBEF(BvC&$m7R1^KR-)zIiJ>zkk2MJ=-tS`+98VJcIc&YKC_;+`4|F?HWP-y6=-h zjD~-VXePN9+b-70GPP}Sc)j%#AMHqeaz0G^w=bK``n|vGaB_f7{G7}}JKflTfhC_> z4gO7R+9*@Ycad|`mGeJD#f+9sa!a?rcQStM)L*`Q8a#i+L4|C+XZ+ix`aApV$-mTj zSAy}AU0rpt^*Ri+esXTmfdO~_?EI#1Q19GT_WhIk z$==P{?YAWG{Gy%7E#}60bsA$7J9xp6>pHnM%@;4eeQUyz1(z1h2zBpOXGB7FbREBG z5w>soahFywFVU4y6QY`u~*<%+@W zE)I@@+seb^N{;NCr&u&Ddd{-_Nw)%Y-D8^exZm-w51}VhhwgnToBw#$%B+P)FLk=O zzWo9DuZBKjikj-auGv0V`Nm_w-fqX<-k%-zlb(OKweBJDk)b=g>5tm`sZcp^K~i2| z+>7DAM7(No%&K3*59`hx(B1PyJjJzZowm2;c1Y`YX~gj0hKc7!*ETq?RVViR?x*Vx zg#L7S#?Itu>&8nv_G;&#ydN~xa#wz@`TA+`N1I>v`(<&?U5ldF_^w|q?yuNk)xGVo z^=7hk#fVm0*Ss6tvTv*Le-HM`=`^R_%!7#=;!-*{+O|nP=k9=h7d#Rhjp-LL`N`U6 zHW3CLt~wX@2%LK8y?fNky`CI#_xz`K9~WMb4F7zk?!h9H zyDe@#ov-&g=C|3`+}bLCTR;8o{%iGG`EJ;)V-jfQzh>p8?PG7}My16kr#v5Y@5Oyf z-A%SS0UyrQ^WE0>lKsBv*%$7Gw=Y_FT&ZS;w)jquM+k9pXse->Ul3pl`IA z8zGhTt^1+h#=*W}wT}ig&eHwlKKyZ+%dfR&pL1^;#7$HCn--=fcHBXXM^%T z#z$3qiwpPR?vs$-uiCp>co^pt(nkpL4Z84k2NI+Iz{%UGbIO<707XUQgS>fIqfJp?I}4OC^;P|IbA3@ zpx;RL$CZ-fPRVhjLCOrhjVrsRyH8FDLIoUIddsF>6DxWl$`mLoSBrI zS(KdFl$<$~oOzU-Unn`tDLJbsIV&kSODH)@DLKn1IX_c!R#0-bP;xd?atfAzrrR1!m@Jso%AW1koDh?;%L-L*ZV6aHZ04t0XY(gYh+jfLj>+ zehG>0R2+n{xsZTc5FxxyjrVt|U$>}!{XzBXKGm-qRKIRg{klW->n_!=dsM$}6DqlR zAecViyU<}`;@L|f!up@}i=Bje$ zcLPXZ+jN)@zY%ZD=u}yZ_c;evDLhzsS28^sZq!4bEw5*$nexgPX9-vXS6nt5U4%;6r(1s4i9yoTtYO&zf1 zrE|oc=7=NU-p{37caAtEN8E-=aP0Fm4{#pzq(EHRyolkqOC4?!)WPdW2pR$c5@j3#I%Q*Zw;=%#fk!}=XdR{ie zF>^hZ0nU;GZXe*p9B{V)$Gn|Z*6vG=I6}%zo*74+E#TDMpV{*g#8F-(;MA=fTizJJ zsaub0FsB0e(AUR4z=44b9C02TaiM^7qz4OeW#dib zC~pNv+&;jmTaPc$2LXJ9RG;1f&W1Y1i0&U7XCA=~*AZ}*9OQ*^#3gaWrE|n>=7>AZ z5%&;q?i|Kz8L56fY+x~%>k$e#b?d>#jRBmx>zs{S12}c-!Nz5C#NFkHE9QtZgTLLy zYUYpKKUctU8AlM{)U5|wUK-#!s%f`7YduZ?PTf4SaW6UI%%aqfmo3kgBd#|`ToOmz z0*<&{9C6nG=fPo~&EOq?y7fq6tw#{x)U5{_H;N-}1>nSL`p1@+%@LQ!5l6_mwJYX` z^WcaJ2b{X~V2^hN;MA?hGS+(B1)RF;jg2#dcX(WI-2tcW_mVAd3`g8%j<~xVafU;= z^{*pGoC0v+YR*6Qc+Ue)-Flp0t%qnBLB12AMQT$AY+P@SxD|l&p@l(QnY@P_akdI> z@)R6#SsZciIO5#l-Qpw;<2?j8b?fnxwI0QQvs5FGjWdIHnOty=fK&JP2V0&GM_edJ zoPr}Rg(GeON8AR$*>ae_%Yak29`K5ifF&t?-Zg}G#bPz`*tpglaoquD&Ou%zN8A{W zxCI<>n>pf6aKzmOoVxond;ScS>es`cwI2R}vr#jDY@C84E*)^{t|PX*%^Y#3IpQ92 z#1X@}_0N(c&K+>-eplJ!RRT`k^)Z6A9-9HD?s{Y6u5rYD0i3$)jV;fT;^630f&QIg z<2rK04dRF!!x6WPBkmC3Jm^6{T-i9j08ZU{tYNK(d!qX5jg6CY#AN_Z-TJcSWpl(m z<%ly*;?}M^M_f2ZTpHkl)T{@4yte?SZauEB*24@qMs?R48`qs9ZW7=e)%1@oZx=`0 zLykBz;JCT8>%$S3#1Xd!aN!)rt36WvdLRkL{5|&ooWB}*Y+M>g+-1OdaFAy_iW@G7 zBQBjI?lMQ5F>u{n#t{U#6b|FP3^;YyhdpaO41rrWQzMU!6LZA5a>V&_#0>(Ry89oy zf0F>GZoGq78$b21e~Rs@v?Cn zIO0xl#N~0seF2<1hyJ;aQ9s^&tnn%VCsremjZ5c<%i@T;%n_FlI1di}a~!LFypLJq zRRB)i^})t1;D|fK5%-WI&TyRi-*a~V1_7?4nt3sU2QudGM+V^3T_0@RX^yyJjyT)# z+}aHVTsVhu>;s&-@p`ew`wnm(YUHtTt|{DbNgQ#zIO5&`4*r)0=sp?P{Yy$!KVBtk zyjg%#cRsUmw>aX63F_|$Y>GxxD>#pz&)D|FdbxI z_m7y)tzCDHI3-8i2Ed8v&OuD~?*MDvvN+=QRf1!m&)I+rSJN(gUc@uh(TDXxZI z`EhidQ`Wz!3|uD`ZW04Gmw}6C;m$K~OBuM8ESy<-S-Wc)xT`GOAO>z51E&L%!#q#d zFmU@BI5!sVB?EVqfs0|`Tw##@P>$#QZw%a07H$j!caDL(z`~ti;Bpzb5*E&IURk?0 z88{~xEOWfQ8Mu24Tm%cZjDh=$fm_JJJp>$dg&gnaZ{S`sa9l`MJh0GC0@`Sn$T_FR4yE|-sLxymJ@xI+9 z0)c>%hQH6Y@F@#2EAm*!l@P;$Eztl=?GxpRNeM~PA#gN0Ruxle-1`W2<00(97Rx>% zDK|QY@C&A!?UP z>k&;DX@Y>;1B5338`>kh+YgF} zh)A?c9BG#nAFoIpG(;LZBtG5_);lg~(5P62U8FQgI%r68j3N?tXi6C5?PcfPqhGfW zpMaoX?_fteuO6YjRmFqiViHD3%WZ%=h~A=XP+~&FAadK*L8W`OlX<17u&%giYMfLN z79vYZR{F+`h)IZ#!&B8hf(Q$PWe-anotPwxO|-FrlQvlary!mqZOfgO?FbtY zMRoo%&ORsSidleSAe@~@1mhxbBWxlW8^TNa1Xbu?m^W-v|L``-x_k_Q!G_9|?zBSmq))Q_I8dUd=QOacrnoH1l9Q@Ao_++E;GzQ2wg7!^_3S*(IWh z@)E+qN$15x9lZjP!8FlD^W$>SXM@5i;mZMQC7Bp=GJKxM@Wn*^8|KGjrbtz}gxyK0 z`O*CaL@nLio`v~DcA<}lci|k9VR?Sf_550d4-MBT5D@`|gl@@)uO+_~3Uxn74cpX` zcuN|6nqJsdqEjFyup~M1l7;Q8m{}r6+Z2&gOo~9fA%(Dhmf}%J5IWY`@QtWT7JBbf z`Wd)6%5(I-ToWv{o#hRZrE-zWiNYFW3&aw^3q6s1)=Ig^*;L}_jkRV-1WPx}dLYN+ zS`uRE(^=LrcznyJrljY)l%Rb+nA+fz=Hpo?FverwLUB-<&!wWTO0OcVA;b%jfM^0E z^YVT!B($;)Kh2+0UnQF)Cv^mbj-!xZ{)a39q-}wbK$nbKgm8>e?V7-g=n3?MdRiiF zk&Z}Lq$d)I^hE}u8hVBzqo#nR1F{%irb(0ZCyS=&P1Q})nWjBmYld*PK)B9yq$8k& zpa9^CF=z{r0b-;-(Blt~9|U1U5s|f2PK?l_9vl(`a4$%=;1@tiFsXP82~r^dK&U_f zei6r!E9M zC<{0qbpb@E>QIGd^2%p0SEsp zgnlgCLjchVH%xFOB;Zsl4eek8aK5l#bUvPx$&54{5?uio1To^U90SJF;KS@+Cg3cw zkQLat-GK9AVKBJ_K6F1Y{Q+>;4z>%YBpKATTLL(oD|TSZlR)Qe0fh3%`!U4o)Rc0oygY8f3eqh8sO;lrB7?@-!}NbHKU|! zX97;0q8t9cGS{O3aN&@L^GBcKDDMn>nCC$+P#&SrVJIpMH{pmWuMgnp{*k|bP>%8p zK(nPyJC&*m`AuuKxVWj;Y-!tuyJm}tN=2_!v&8_rUS-V|WJbc`heRbOMgX5485WhS z3`>+nm+HVUxc-U?FD%8B()pnem~)BhCci>KSzbX&4h@7D)lL3jq;X{)GSXV`*z=x| zM)iaI z*R1;_*HGOKfRawNm(6#SG*+pQRl7c~{J<+eeD{SKlbq$1AF6l4@X8O2vxrxIDEGpe zF*7O^1YY@p<1-a==I{wdW3HH2exM#D;h97Ox|e<|(Le5R&k0LF!=(DFC|!>sdAFR04ydt z4&KvBBT$bUa!GT-FlDJewwRla2;;(2;QJTUK`wprsa*L%_4e}rlmY}fB(6#j#)LzM z1_A=OP2e5yTXkHQJg%pD9qri>Vv6~6hQlf_pWoaDP$j+WyDBW?__AuHM{E{yCzPbX z2U$qqzR7^B1~NF9M+X;ph2OO7H9nmUrnSts`@qBiy;6^+Yf4cSS;%;pw{NkK$kJd~ z2skl$r23+nnI4d2c4s%>=rTmo$Aek8{nUCPh8f}@0pl%Yl@O8r0Alj}Tv$cR^`<+pal+ay98Y!Vyj5MCM`HVEGsMIKHj8s{v&q{ZMG-gG@ z=U-;=8yFv#RCXu!k!x=Fi&nyA2J9@`UAB0JSuGmiGLl_mmB80@k4Z{W$b91>W2AAt z|-pkU@Fd9rHZ+TnUFF#K{@#GUvKK(n$r|-Y_ z{4erP-yIcK3d((VO$l0;3f?d90lQMExhvR|dZu}aE^EIhdZYEMc7e43Eofa2w@lkO z)IyACLkrJBLYh-(Vcqi`;ej~;g?eH`i%Uf%N`VDwpK61)sXkzv>UtPoqJ#0Nma&jf z{kMe-t|q8V$_HPodzy}!q%|4LP8}gpsmUp@QKTsj*v*ipHSk56N*QQuN{GA^X-bGh z7Soi_On}so0knuTodLAugE7;x2htd-Lba_?RVnw)rrK^nX*PV2RzpJ}4C<)144@{$ z7>tDqNmQWPJ^)A7kU8%Z&<0{=bu+LT`WDqjt^m|&54cFWF^Fjj&W$B+IpDMzIQp1v z@V5$Zv|%FyPV{5R+XgsaCV)D|zA%^N9pG@juwQgO&SNqo4Tpp_uxPdrBaWVDjHkhe zN%6G?+yKa9hfK(z8bfu`ha&}&A+NihlYUk*pa%C+3J`>ndj4czT zOrY6+g9#)ZD3^L7CK*Dw2&>?mcr^^V?A$FV*-uV`>I<2|>~d*+;vyrB_mW&l`kX4cKmLFsW|BXJ75gz7R&hasL9KiFLO`e8@skCn*UD6SAcTgOM`U7MM@uiNK z(LpniG+pCHP)PVIp6nGX=^Y=Jn8eB}@2i_pK?u88#IXYLZ`_g zsS8re947-!94UBj-iv4qRIyJpC$Hz)gz@38y8)>U&Xu*B$OZF-X)40mND?C@yiSrrg`kwWE@~qd{5+c^uWjU0RrGZ;q^~7FU$>L2^%7i0id!oy z|FGS&FMiNJ149Y)(BO74VVo+dBN5CMlO%eYWI=I9W6vTYJg3MiT;N@Y>~Wfpm9@W$ zWPc$N3g4#$!^q{K&d`Fthp*mcVPR7*-$GYMNPCz_rsbhyYII8NBEO|qe60n@S4j`F z_z)8#5s)&8C4m-4cMNE9?8PZzeM)+ug@V(lnD22QJ2%n>x1=utztYR=jw=GMWMs@|eJ(Pf>&roIjmR0JTJVh`Q( zK%PlXk+q3`p$mcY5@^vg-@@9zuqBmJIl|6DxK#AF($B)b$h9^p!OItB zwN9S3IH$I%1w5MrJr{@?Lb5cA^;6LRBS`7VgFd~SS5IaI_53vEv zRX5Cs1?z$N5F@E?01Jc)1n4z-55_RZ_c4Ywc@8n+;aVZ_$bcHaxlk8lSOYP}ux5iX zhPA{EW>L;KjA0Gasdx>>fWJtki!g?Ew1Gs$xGl!8#vLJc0GGX95IaIF!F=eq9AoGY z>3tfGN%aKO4#BgM)T$uQM$9M+ILYb)v`uQ3&}E1_K_?h7TPvj)%Cev`wu^ni0AsIU z0KNe_xQ6T`2`T+z8-RBQ$LxAADePba8Q4cUguq2ZUL14=6+1zUIG6%5j0T*N(Jp=H z2Bl1S&%jMFIcHQo`k1Yi@(OV6C=4^|$CB3!t}1UPfI5zZn5i8S12~*7>=&Jn%a+VY z!yz#ma2p^-9KEaae$-SrPocJym5f*$rc7_w!8}rd2nr!0p(4D z51boHRSrSi16(MbV8oelOphP4+rW+E7Q{GSdM#1jYWOhMt)>`$ARvz&wnGL}UTtxi z77kpCWI%bKh2!p`#vZ>?Z_94Zl==SmwQ#1x#SfuW3#SJ5{NL?uc|G*EYvdVa4&$DuOi5Z;}$%HIup4^7^pp0}v4D*Il>DpcjA z5W})o!K*y*Di3ke@0il4H18f1+VhJt2`vAp8^HHm$ic0SwaI^ zhN*z5iJ15VnI`NIx;WIJdET8fY0l2?Wv$@dIeYW&oXb3Y@G1|y$^)JJr6s)0#`oC}{>yHjv!MUT^3kjcvPVd3V;&tM;Pri9 z_^<<;<=YRm4wublPXi76EtU`2Aq=kpCnk?nUo?A1vw<|u2pAc4IHZ1=-L?lDEdwRe z$AeioXBESPka8goQcTthaiQf9s)U2HBTXl9vjK1G%Gn0|nwV^(lznQ1Bdjv}^iO$% zM!Rl?4Xw(DbcM`HeMW0+DZU>jr)S(&e|}_DRmOUo02bt_S_le$X|A4q(P^E7|2S`W26zk zl9k@gN}pn-|9~`R;TZqbmfYX8SgyW(H|tbH8*g@&OF46I=QeD*j`WqywC?6)?)}a2 zgsBX%Ly}}lmi;s<`E3(x)r;V;xCq)foMko*PPo5i2F~+`JbxJBz~r!)Z|thePVgSN zd5_!)-~6kPdB%}uNYy>nc$4WW8352OYI*)p7L*W=dnm;xRM#6k*ah?ap?dO+H<|Y4 z`9p7>Kcx3mqjss+fPzHjBuyyHGUX->I>DPv^Cr{0$u#{8#e3wgM0Ey!{Wa#vK}L`? zK^j};b*1|EEs&*p3*sH03{G4UG`Npec(AE{ugbQ%ua*q>3o4d3nU0J3_TQO2e^_OW z+=|=5mM7f4`9kskf+6*{2gsFUw0lg!Qq)#@1f>DPCUhTpA1K>63=Ph7u@oI#$@kNo5FZXrcW+-6zNuas|f< zZ9E6qS>&QQZY{+1I#$@Um#W?wi*AM51bX)NG#9+k7J>2du-+1)d3Mpk4uVClc{=$e z#9CX!vbrW%7bTsskQDwF^x%nhp-%6nqzN$^5Vw%5&ckuwC=j)&KtN3L61))U1{7vF zHax1G-$>A?MbCUf)bpKiRCL>QFGM12J;jG;-T!i=)$hdwk)!wdnyMb4buFnnwQ~g- z+Ksg~qSQ2>P+zxP;gWEDt<2zJv9d>D3uBbh(<8+PQQD;_n_TS-Vu{w$Jyy}5bPL4! z+JvV^#3$XN;T{6-y7h^MK5a!FPN6A~-!>H6R++Vb%$+MGGF4;0C^bA<*V@#2{u5E* zTJs!oq}YEPZC6R_Jk^Sb1*(3jR>9f?Q&>OEXMk-JFw#EhNLY&sbwW41Acz$&1fpm$ z@wxu=fI{=(mx{g)7rZd2fqvCNt^vsP>IO#C{qcMd>MVnq6q?GHd5LoM^9V7>)LCnH zE7!a5h4qam*ot1(;ivg?tne&23d9ZCOY3+D3Fd#aq=vLDlyWr=Zh@kxfLsvT@9Iw$ zP0^dGo2D~Od%D&Pu;BGKRch4{n2vM=V5QF5!J?Hk?27H^2Tv}Q%O zwqEc*ZEpAfwz)G}|I^Xk)TlZ3g(M`G87rXXI2k#J1w`(XBbz~Ovh7wLSoqGnsGuLfKYg~M_T7*B%_v)#9VgZ~u*8&?ag-@PiJ z2x1B3(fz>UUVy`Puz%!_3&iT$?GHE!l(7R_-Yq$RmF=E0MRBqr8_4dGu+mu774=ozJCz0|7^m7k~ILpgi{Z zHxY21$kOs(?DH=haP;{{J`_;$wm}Tnw34oU8F1?Kt&ReKdA`_+2_ggXaDC}(5c_uq zKFsqpTU@3C21TXeCLA&4oe-Dx4^9a(pghp?a%)Fwc&Wae+O~6T>+Iv?^{4xO#nqSAyRH!Vm`lt#-4dzP9O*&pT?b1Jn7l~;kXyn>Re z3@|ER6)@7cFhz_sDog2=RfZBh!hlLof)siY_}6+3_~u`U8v7Ce1ts=w6Dqq=+ztVq z0eri8hHeqB;lpeA@ESg)PD)80t-8u4Wh7d4CGZ{ss{B5Z*YM#re5&Zm16UgGpafpS z2d9nY8K(jlR?RzE1tP4Pa>`h+stcefu&P&7JxZ0j46d#K-a`Pd;lpeAlvm}|$j<^e z7*M&isTL!yx~lzSr5g4jNh3uojWr)Y?;#TRM~ zWmvl5Q?>4AyoL{#$9`VJr^={*Yg(ib z78XRql$LPZ0Q?6uAR46*4I2@LkkhbH!xW-+L!u@i8`V_hjtDo!hhN$K?=O?M6bhr7oZk!n?A8WFWQcnX7 ztHnV5U-dMw3MQv)#S2RIQEBAm(X#(G#CSG>iUgT1hL{dWhLz9>h_!%itXU=ua&*Z( z=24a^=o03Pa`Z&d9MZ_a(&Y~2%8iK5kgiXkwjfVZuH2aDUoLGzD9WYl5kHkn>k%^< zY5Ll1K*`7P&S8|J!q;|I8udu%faSMY>6fguR%zc!9WtUhE8UBgPGY5}L%IdDQwVbZ zjh+sCjyidCx%5Rllw_2BY*1eldz}+S-Dbj z4|~nGyvNHpOyvuK>EOc&B(ohTfP-^}3lL}Ur|?Y%lk|1&4T zUhg|f8K02UJtiqhA@hxkjFHAk65?Z_gi%%XQ1Cq@<#QoIE{hmO)__f6Ly{6?anVU~ zN*D!+mc_{uD(+<;#yS!Bo$J+`kt%pM?z|g!E`J0vUtaMfZS|Z_@NO8osx(EuXH&#H z*;M!W>Ut2MT&ePI+<7+)D%Q*2IPqZb8Ds%)@Xn)Oc!Jl8Fg`=dw)!WD~2L1 zDWp8Liw0DD)A6BL|_e9Cm_tgAzYt4!wuHcDf+LGmXfYM!HMD`Z||=i*7lA zJA>i+7It}0EmK5V=>iFnfn{OOi5kN%6B#Wf{mDJ&G0*&{_WOCm&B4(@D+!%%XrTpt z!csxTu^76xp~XIMBj8gwP>IeG1mKO@=eZs+B9HEGnwNL(y<(57mJ&21O0`uuG9led=Q557`zIor za62K&%{;uI6Eaya_Vv=;LAV7|d zt5*fuHWhg;J%NVFm+Qj3vo2f>C5uWFbFC2juCzOh=aOBCqm6;c1%eX{r>yH62AZ1eV`qLoi7=8UL`? z2pFFyw!*<{grzQFM0$;wg^m?Oll7+PPSr`H9BGhagf8QH3t`?#P8bZ;VW|iq%zqP% zp}fkC9oC>R_Cj&>a)6yzc{u>nX>u`OL>hWIz!MrsLPCIg9zvluxLYs~8VZaAW`c0Y zF`!f-&@aJeOvAaHg)v+p=c)3$7=xTVD*qkEa7}#07_J>OCN(f4h>jS;H8B8VIEOZ1 z3>VmajA22ZV+?pgAjAL%xDh#YfV@(%fPj@E&j=VdJK%h%3m{Y_gDOPab2UJ9o((QT zWo#ek27@tt*!nQ9p`)9~&XSPQFPvCxn+_S!aUBl&Fh9c#H=`>tVp<=DymLYRalqL! z+NBTOpp4n>3pmTkxuay!$9QLE;@$ub>#{>X$YA1{ff;s3HVD#@@L^hR4*?v`7xs(J zhnrLd&jtyA%b;*rjsatKy9RK}<SzTPy#?9>+F@JiGugpuB1D zVb04@z`+z&2yEOPzl#3OHX?ak=j$kfP@u3x)#D7Gjh~ zpU>*#&EqKVCPN;5TBAJnx|IN~6Xdf4d!9Rr%hs(P1x9&nPXyfoH-IWQRHFUEO|u6DsE}P_+1f(A&$YR2&M+o@DfqlI_2P-W8)-q`~0Y@vz@cf7L&hi|ZF zs;3Fs@pv^o4e-tu`0Z3c4T#s{;q`bJS_|MUK@+Vo-q}JjTvNQW1zHnGW6vAGiBe6@ zN8Z^2?`%Pn^M`k~z~#YRGff=LYV&$Lib`G_{@2xbO5cETcA8-KtR%olvVHneiBFM^ zOD5>%Y>y#Y=;sROnMkHj_lLYCkT(tT%Jg+4MJ^^Y^7JJ6F{rJBnjeC6?X-RJc5<&m zYYV}P6d^J1qdX1tfkcwxa6x9>#_ps}i{O2_FX)CyYqvoSo-{AFTqk*Bi6yzo3gkxx zqBcykEU#9%!c2FGfn1P@nkS&w;|wLRbw|3FR<8aF9f7f=JL=U8QRNw4_AW{cLaiH5 z3*W*dXQC_&-vQJ7- znlD5~pv8VUQC1QjP&mpFwi8iyEj%yvwLlG`t`@WoOp9_lFxsdCGXuB+a=Q>mA;J7_ z3)x&XTAH8?Dj@IRWtvo`+%S#YB}BM^(#-%)7in$W{elb-BVBc;_d$PFkkdzjsEAGIhk_t2n)zfvZQz($eITeha3SWe=1W8v-rjwX5;@CpQNKHx%_0O~jrVkQCV4GIS|u}u__E5SIXLU(0`v4k{&owL zmgNkR~B@MJCKMf&Co5!*P@4w^6u$t68dG0!6{@~j=x3zw*{k| z_K*=x$wvvVB)uINqz{6{d{NjSCpjynmm zs|uNPgiO^phDQf)sUpHVJ}!~zTSEPSc=DDfZ+Y^z%qWWYlwUp8nRGx~O`=D^J7M6R zFmQQ|!}LKxS}#`fgyYFup1chM^+}mDQC8_psC@K;_FJ|6obaCVdGeO`l+V0r^W?39 zcfvqZubR+aDi2gVd0XL0rdmGNNd*%SB~iqW3`&Skl0_teqfQOh2V`k{o`Z}aX@WEs zUvoq!fU`->`cqydO`~b@ktRw1fAp$s7oci&2X3sf8m&^<6HXP|ugYV$TJjVGIB-@u zRV(3tRGTMnN%Ho)Z$-s+cAyTbOo)$=B_@h1^(YuWWGLKQ5*?V&1n8GvY^U(7PObQ= zSE7{Zz}fEi2F2AigWa=y&wxTg$4COM5p?QFG9)nyBtab|PQ}LJdSZiAk3xZGcA>T> z<{C=&ewtc%te}z5Q{qSxwT2ej?~nDyvaUt(KzpJ?10-At8>Ci!fLaBLGu2j}{Wcqz znNPW;M*c!`Ap!rK-plmINxGADrf5&qN)yf&I6{^XXfCxJ zClHysSP!^Pk~IPwO_EH6Ok@C&=mcWzpSD*Af(wmPx!9}M(58k-9BC{uM9MH5Uzd6nA|a_jtsNPN*&gNTrwEUKSwW{L32nex5OCc z45!BcP6i2;Pg;}1F-|S~S8ME96{`6;%3uXH)og`i5`3^d=n5IsQO#DsX^urKE3m2N zr68yQ2dWu&u5QMXg-N#U_+7vyFmRPo%{@3$&B1`f@v%cc$Y2g{2;c(PAV{;R<}H*w z>=#W1!xdJ6YCa4&^5y_#SdIbXY4BmT`wDPeY_s)&YW6}Qtgr;qbU&~t0C3n2_76{Y z4C>lND%^uCE&s)qHy?1e06}@AVg|(OpW3NXOIMKM+W`_d~*BARo zs}!KTZSa9pQwb3nlz)KdxXz*H z{~8Se7WYqfmHEY-Wn}a>Kw(*4K}mTFY+d3vMrGVH<0>PKYj}f^Mn?V#BaMta-ZfD^ zxCQyQG3>sPJ|Uj)@D-C3ln^rltQEV)DU*}%Px-2o>&V29h?0fLWm2H%-3XgViUdcE z!^#`tNpGI?=1Fg!^rkmnt;+ih=AW)S>0J%pn%ri!x--u2JP=)7IHRY7O7_Pbi>aB3qE2>_M@jDOjI}en42*+2mRip-( zKac#*1N_bds=JEDWFT*`47Vko^j2xpRCto9{ynPV!;D60c+QYYSs8cB& z4K%bZyl&=7LeoSJR3Tqelf+VGtTV6+{~V=>Jz$2a(34A;6{%x3J$VuG)8T{kB+?`p zklsOR2lMDK7~a?$m$3qLHtGJBnH>i_jtK{Pay)P|T~ zWIvS#VilHMWx)!EWI&78Kj{R-$dBbS(s=T{g*4Vx1zqAZeF!mHyrPf%&863#E@>1` zL$p8@q-j}a0AGu6FPE-ETD0zC)bClYydHso`qZ}<}Coem1H7>t)nd?3GfLs>cUI_d^sW`H zh1F!iuJw${&Q4TiR<`chfR4^a{FVPR3y7zNllmt{mJOB0yXsu%1^A1RAe*&PQa zE0}i1s`>iHCijv)K@>O3n$)l$P$85i$ihM>78i{%VW0b0;D_lw?P31mkuYu;wGI?e z^>-IQm7~951&w~L(K1?+tYn}nah>fuitP$pk`NzT<_sH!ss6nB9#ZvZdsu{A7BP&h z0lLf~NeQyJ=p;GS4+;`3i-Tv~(y^A2*sO`7YE@buhQ5<|lA9;Fd6Jtaxp|U1u6icz znwWm_BzIhOd1?i3+0C?%sQ5;>DlZ}#bQ}mO|2nw(a>~C8uBM!_7r|8*K)nU7dPUYN z;OYwCExUQkZu(8}C~2%xA=88>CwrJvoiqMo%R9)*M;8$Jf| zX<4Fq2ALj3x{aqz&v{!zlX$(T?Hl>0kTj=U#%3JSUz z0O>A;T+g2QgnpWr6SU(F8^-UQqdnI|uDzs0q&s&~>jiSbi-kHm;lfN+E~27yeTp8`1`G6rc|HbtJ7B|kkNig| zo^s(_q6LwkmtydK>QJzBC&12~@KKERS~2GWjL{=M#lz#Bi&*3XWdbOJIl8L%<(l3` z!CWF;xTHYQL858{t=h8-qlQfPN%zveZ1CPJh$s;2?#auVvuaMkoIS-JL91R|)>`%A zy3nIRlhh%p-KRK)p|m4!)y^s&&IX|r-#655W3c|9t4hZx{njp0=h5P#kupE z?z6~Clxt9EUB9mcavjfNuE&);#GB`OfvjVNVnJup9r|=1NShohv^FVA3&?bRs$2(M zppz;OQ@jRZZR=x&jjeqOJ5%ke>NmEwqVT(lJqT}TV^^_{_(Wk1fymp$yB*GtR#z(+ zfmVI_6__D|QN*YYl2;AAo@dv7CBii`Pzp13VRgVYyAAeKH)Fa_ONphmyN_y|E4(ao zb(g-fXfLs{4z-~3YUk=eoyOLLT$Q7<#DH2=)r^l!z!}%QteTCpl5XIVJupuz<4&=; zahXH*bH(O_7Uhy%3);O?EHW;0%6_g`L}+JZ!5LN~x92-OrRtp3J?dS!-#NQbAS4>= zLZ_^8c@TkAyh0s7!^u^;+(cj8|q6MBoKIqh4;6pog*OiM2i zj&_8P5H=l|SGM6d6c| z1xTG@0`|Hl2r$03#uyqTbq=7gIi|rP8;$mfh6G`UF@Ui@1Z)`Xg0WcDFI2H;gK22L zJ;q>B-vMI~>VYxj+d{;34q9LxDj>b5(o`z!qn&q^n`j^dWM~`Odu8zHHEcGz7oP>>o=7Cp7a53Z=oyNPP``-|Nc4M}j+;cg7lFAUMZ(FYp<)-D?gZEY z69UwG5DK;78Z{6a3XB9|NIO6u@FH-8cpStAa4s#v7%rYG7{kf`n9Bcxv6vvjVc`ux zHEAov4xktH|JeH)z^ICI?b%JT*@O@Rp_(NGHX$OS`G-KPKlx(;`8BAZ(J0NP%(ojAXGgQ}T!qd@HzTEe;Cn-A zmyZ|97vLkyyALaZj~!J)632^iEc4wDzB4Z;;L(>qrO{_!+mTdUty$O+~+)zyzThN*Lw;0uqb1anJ)~!`WP<8cB4#g z_j}-@cIZ0jK}jiIyFUUSjlDUU<)suwe0tE6fKohpXM)d)ys#vX)-WZKXCCL>;Irb> z;}!7H{ouq$EbDmk-UMF*c+AN>Z*ylw z+%qKaIeZ-Wh;&_X&`U*a>ygu-GQAYCU-ljzI$||cW<3$mv8b!yldj9w=_XnMplQ*hdIqM9p0rH}!V6Ko_UAc~ftwxjV4ABhcAnj>w>CWpO>J-fsV9 zgn>xZ5y<~Re50XM6Z+f2V&7t_m18do+hs=s*gxfR}$#^$Dr7B%yul}lIEFPc|J#}=*P<8FV!@}a#O znrva{{WW(q&&R)tq@i@eDU-!G>)=zxR%H#6O1}BzyRL@}PPS>Sy1nj`242#mN46-* zc3v3WCR<+xz(`J8NcjS>_|%h;Yo#Wo)THHYtYEnE{mkrej+ddMMnv_zLQfgAc*0R{`m{EgS;r%LF`8)X= zSgA=R_Q!eLT^_uWDPJHboi7lRZc#JeyM$8`Y=WL#p)cavH1o@`sxFno?);b9=W3_2 zR97A}4f33MwWs1c71%~vdLDEX^4uIPsw3>nAMkH%XO2o7HdK~Yl(RH!k70kaWJOg~ zDU{t>yF<)1IekS&%0$Ox$CT7OhsQBJzb{x=Sz{H~`KbmV8NT1AB!%mcA-x$dhy`#Y19~k~drSdE@*V^7;lbgJ zwn~jC??%vgqeP6ULFI`fuNZr9CQ>$d>=}cTCdI{Gh{|X1IPZ}n7yD0St~Ux?T+=~h z$qU9&kpU$z$rWh~CFxOd;0e>8CY>jY)g0&jeCa&#Ux+*vQ6I>wLk}{a#__Xy{)7Xk zjF3QU;9$z%(;E(~2(+~MJKMWEx<^N;XtKu&{VuH_J?y*LX}#=gVNB->aXcc#`aX#D z3qaLiOt7haON{FP6m$C_7#R?NsnD?ayKo8(YYo@{R$g@$` z9{j1$FolLCvOj^{iSBNSIhyQ>RZatB&xbDn3^7_DI82U-RJvVET)arD*u3Vn}HCxho59@o*F zOI(B3I>^ME%_ehb9}gA(-i>H`70jnIVLYArn-R9*ragE2vhR9*t%DZA01^4;}W2PYmXdIJ3W&fLJfN8S`B+7-V4ev_^)jhlG`CE(`TULND# z342QXpMyfHrpGX<1Tk3+T{ zd<#K|kIqvfYHs&w@U7!#qrc4UdNA;!U9*8HrXVD0p8>vj@^*ni^p|+Ig0CEu`X`nh z_3!KWNW;$_2A>#PoHEkGIFjXkU+N$AlM=}TqCKxdi&L)Q)CQtGilt&j)%^Kdl!);y z6^GB_?HGu56?HvfOGN`^mhi;mfoK!LErFIA4jxlzGIczTxc4_OIFYFwJoY5=XW)Y; zGN#?dUenKG1@in~K{1QQc~7J=9v3d=jml@RQYlZ1r~-MCr6m`uk;xzbI zN1e}R&B#|v=Ql^4&tX?1ztdQYF7}zI^HbPuQTbeUUsT@19!36css58u=L^~M$louW zm!m1?aQ+9<`M0C$mv9dTqWh!=kRhI3yiikrc}%ZQ<4@@UQ~own{wq>GOOi)= z0R>W?9&u$-p3W~b<=ag8&zti1OL>y_swqE-elzq$@(WG*3RAw(lwWJgZ!+btGv(>0 zMI>tP>!$qAO!@yc<ns`0jZoD)b!-5 z(5#N5gw#aItb{CHc|lZh6(Vo&VhE6WP=(68I9kX&2tmuzqn#T!TUHezEs*i!bWl7D zuK&^1x^g_-5N$3Z+9e6a_%N0Vf>ZE-9!8W85*TZ!9pP^ZwDz_H^jIU2Zt^v?sU5mG zB8mntL4k-y!t=UfrhaWgStb~O#~AH;D3Aw@f+>ro+ARbLmg5{aWNC*v#K=WmXiD#h z9uuUqMQEMs<&p6hCyb#|+B+)bhsk9yhoRvvVFM!<$; zSh90Yo8L*-B@`^#$~pvQuev>zt)^~&(%o0uJJKQs2xo5@EA1WORftFA)rJ<|%9fpU zaBaZkN_)rn6UNRk3Ku&zW`bTW>~taWa$=(s%9dT(vNr^|4;~wM~{gqB*>(-}SN#|_YjnYWh} zUN~(lf`B-D?kl#pyYuqO``i=~WMtJ;3Q^!JKv)Up%x$}4&m>>&m#({V;_Xk|LZLwr z7$oIO^^Uz0?|GC0gJj*YDC^++?Y|zGzHeikkRY`Kzu%g+Qwyn(wev6SX$S=3x{Wkp z97iem#}Wz-!GnKntDkak^8Fciup-CK8M`Lmo^yLff6jx>+u3b5w7GVr^`FUgb*N_T zz_+%#`Vn#>4FM<8`hrxJ>T~t)<3~5uyZYzt-51o#C+wVny2Rn$>FVEl>vQhZZRxlD zYNT<`8wGE;pBy=dy}?ok-7Y=U#~DjlwI_3D#k5S{5+0ahTjN5sjy`UlwDaMSTCc00 z6~0vPk~{nMDYxAabVD|DhBlM@ZH~*inS-z!=?J-zUemA#dQE*! zHmiOl^_;Z+@C=ebpW1<`TkD2B{{Pvi$$WC8I;W{|$U@%Bc{ zG0QXpjcjYAF(%GPppk6|G{Ods^dTrkF0`;3?x{D27ujYCFG6`ayvVjjIlM^ML4*~_ z6d^`d>(>_@U}Rh4lOv5e>ARmCsbw_{nT-n@E}U^@+ix%`6A)6Q;qboP389=_llxO| zo45;MW!f@!Id4Y|=Gwim!Lifbp0SJVOzZy-ef;Tq<{cC(fO4x2H)hlgv%;T_oVD}m z;c11U7bx>TJv_rN@=uP;!^q8P+mDvh`X3l{IH@*$HXfYRpS~-5x1&)DiGsDU5kXCg zwjmJ7u@ygpUCodkQm-IC;pG z%zmu74OzREw59FZ-oBOYRIhtl+OBQ>EIout7C0Pj+H7HNawr7I&Gqi1-}6&nc;FHQ z;QwH!gs6r6;IHIcukY;m$A{*x?J`}uCgPkvQasy5^z-n;M`oR0D3uG+WVdN$FsQ? z$Df%onzKJMQ}vlaBMHn*wll@yV0*`(89bVf!^~*SeSQ3)8l$;nhl;vi%O8aZ+QXkJ zXe8mG`i5iNRfVVaaT}^%j=zYu@(w z{35?ZbQWX3CW@c+!$eaU4{1TviKjEsETZ(QLKMH$L82IeKBD;P>DTFlI^9nczx3}A z#V_>$(dmqRKolkdna~!bcuZcSE>kK|Tt_xh{M1Y#igxA@g`9;tT}>4Ix`-(H)k+lWm$VA0e|6F{aS*xxDi_lTPSek=hn%3oc*+`fpCfD3JMX#4KPz#3W1_=fjZk z^Z@vNBDE{}zCh>G*;ogy4v_&B$BRvTSAj1e@rlE=Cca;TkM1sWYDEE`8~wzTSrJuy zQBHH%YvL;cUmga4`p@TBr{;FgF1FV0)!?IfB6)bFfw-$Ut-l=-yB+oo=p9SB!`gxg{$N5L# z6XWcW@>jCZ}C1fP}by+M+PTbZYL@*cD(Z%~pao>%e4&ojr` z_+0`%F@A+(^luaRtX%JRz=!{Qz2KJT$&GLGeEiCyyy<5|%~wS^346a4SZIv_f_zT>&4-y^62k>EAkeDPspPmQc5&_=IiYOpOx$VHu%K#;)k6l zlJ{MF@S7LXN*MbQ_~MyL?FB=IU;>?rPSM*CJr7)ZImvqtANjfVZM=gQ$h3No_1 zAAqkGWh9S&`zVn-SW3;W(2S(`x3H8NHKyCbO3hHpJHDmVJG38wSCDzk3o-|Wd&Mh6g43i-(@IY)Hfl9iwo@|8kik`fFG-E6b5)3f+TI0TF_OThK zItuo&X{S17_OZNE9r=B89r^fX`2`M7U!lV@-Gk$qjslc>3Orl!?eOHVDgU;2H9HTe zNj{WMQ=O^cft)^8U`T-Ee3I%RqQ) z0bp=_6o{ae6NV}m{~kb3t^krX7XA%bJ&JGW)Uov=2rr_P2P}s`36WCu1EEJD_%0fS zZzcHU{_O;xkU^rv@#QAIJ2VW5SfWxVax$()eCwh(v<&dAn#wr%*8GKDuLfjk-_`Rp ze}NS>l@%KQ`1saEXY)1;eCtZO!i4cH@*ic!IW)&ra-=%R>6FFTc0f*KS5+UmC%~^` za3V84cJ+I-kQM;5{OiDeB92VG49WZjIv4WnYWRd)ULs z@00335p{khdlva$Naqhkoj;BJ9{Jx%=iiJve^Rj2Z6jsO11Ak7M7(f?W994f6qcE9y()s47^J`fr^0TG$*F>EUFxfL8 zL8<-Hd0lUfovzmxo(w0O@^9+>7w3!$pRru@^U{G+D4M{55rslTKV^ld3W z8To&g@^t>Uru_S+d_MgY=!xo|W6E!k@+5DIDgSv>{w`DgJEr_kO!+?{zW{Qt$2Fgj zo(wMugxfb=YrJ!fT`m5eC|`uyOTXYSdnz35Z0O3Clh2P~MSMSoK-%N^ zF%(`85%*XAEtx0W9#%k{^vg8gD6fnvuNF=fDI5D>{yQWqBQ~% zcdV$rvVVxq6IXY&cfws}N5~&;@9yec($!&7S-9w$MXk-8YfbOQp0J-IBsvedwP;?B zcu%lszAO;#>ekDJA45|%X;+71J1~qmDm2|>%1xniQ>fe&M$i-P3@BL~N@+#3B;)`> zKvvxKPqKq<4^CEY3T-&mRBj5DRzx`d?Un3liaYuu2dNyHO{iO#VzI9svbMCa;_8h63lygA1cO&W> zdYZw-St!i|=Vz6yn4G5F`v*^drq9us=OvCTPu;M?@iacmc%I7ky<5xro{;6#4^_kY z8p&BQTs}pUbNwISxX=N|g^uUjUl=Lglkot%o$5R_0(Wiw2u->t%d_vuewMzo_saCU z@``?iP@)ySTHm3?#8o@6Yir8C!eyQ#`zw^6?K9@p)8 zyI&ab?s4Ac*vW2Bx$D6;l0w|{`OU$BVEPq(?LYJ6E!gX>(a*SdW$sSB&9y7#cF%6q zyZwyzN*}xJNSi~d`P4zd?b=n@QSRHx`;~W4NG5vKmEn#hZA*ryPJVIt?^hL1yKmY= z8p#Si0(D>YH6C`bv;QFGV_W@~4$^f$#;^C4sO!D?AUV!E#c)$N$s(BCG zL@M?b>~rs9hc@mXnpFWugWQ?kiyqCr;H(PGS>Lms&B3(0;7Bp;u@Rs5v60#wI8;oV z+mPFMM#E(@X0`nm?*4MOWVEIF^1Ka)pPoE9l(yT$T{+T>&%%t)ikk60=G@8V)DC>D z@5>|Su^;Ym6taPtY-{Z&8qNp}+)7t9t*CaoW9Rp;blg?pqq(g0;kpBd7Gsu&8W-JP zzwjW7Xk-;vtX`k@-E+rNgE9J(KY zXsPvIk1RaoxNBO`e;T8j<+;E9>VxTnKDPB=YPRnGm(0TJwz3_MZ>4eGhY$6Hk21p= zWvuP#^pThMy$cPcC&di^-1FK9%c=FH4t@0^ZMJE3YyG*Zqj=h$EAKl}ms;1hYUo++ zdhn}9wmPyrX&zSG2*-ox9olncPe=ODgKO*B&dI-E=+}(6UmX4*l*+GPwBqc4^h!1- zbY)#zs3U7{?a+fwtf+O`rESI277Y!Rw_;7bIQ+NJ1;dv+Q$4uH!c#mq3|v5+Q%{_OABTFVdVCPU21sG4fS><{J9RS>X^X{PFN7wY9aER@#q;&o1OEZSRkV zYbI+)S^9W=@Fse-k=L##SBF`&mZeb+EzW?GPF(+9QG@#Z!JDs*q++x`c$2{HxXuu> zfOT(hj`N>tZs6Vy!OAmniN+D1kJLjx6eo#*(zy{oEb?K~&9$AlGZlErfrmNnrDqCJ zWJuwQ)Za)o26`Eqb3{P!g_MW3RWZ>j-8mw>@4%k`WAkJ z-8tg9hyzUga0G-R-cBu1G+IX#?fQs)bOd>c`C*l5@Dq}WB8W?e*a(cE(a>h)3{@~$R2 zi?M5nqWpTIP{T-e?nwQp93LmVD3CKFC+5huEKDw!h51cH7O6jpL~0lHxjnId3m50M zrBs~^&KEUDa(AX==fz$Gze=ojx+`LwFJe|P!HGIw)S7!Y%}#UX$+GHvkrt8Ww+^>4 zpLyJ24Jfqer&8^g2k_51OMYK-RW57jC9P@$0ohANXgj{KMLhYCySI1H86+-u_x)fmksJ5=NXN4o)` z2h49kG*WNz1}t#Fks$flY#I0d!w=kX8>w$O>@;V8q^9X3g=G*5-cs6(JqiycL$Nz~O`%_uW}4w0uKc3QT_Gt7XtpOI}XcSYi_G++?hF^ z&AmDP%#6`ovNIETR2S(pgGLg5{(NfOk(zZ}CPsVye0}`q&+%;TuJM=M@oerd<3E3n zXLElaf0ZB4=6*l^Dj%b{WLJ6Q`GY+!{tk~uJ}i&s*s+4|OZ=>ZmV>SYB@gABh|Xv1 zi$qUnY$s7%(H%swKl1~k=Q8#TQEan4PZWD_FB1j-t3<*7JEGusJ3z55S4tEu|0bE4~b%H=ozAAjQyM_+9hi-YWHQL z*w32b1cjVp(6R-ZNAz;gQY!x>W0w=fAdpoS(ff(wx*jKr>-rHl;;s8 zIiNI83%B5Ht6%9Gtlo>b^2dA{U6Xx_)Nu?;0$ad7K2j$ETZ^G9@EKdx)Ybl zccIV?Zg>mUg#4z{AD*=BiJd;a&54~qzP*XPExxTuk8aw=#D0*rt3^~ww9extOe5|7 z8j1K08@b2A7$%-_@QqEDD0$f!i*$am8jtwK-vE-;CU$_a9h#19 z2XiVm@lD5@@oX~_^3(^q7TV~eR1dyVng>0JzGG=dwHulhu?Z$t(bdH!z8>&>nix!J zE%MZ^NQ2IQwfi>s zM7w+qjUw+a7Uj*yWC(eD4UQsj5%?~}Idd|P%RQ1jl1quMcRN1vI6nkF{5=_y%zV#- zuRew=*3Wtto(a?rjq?j^4u-&o$7@V7k8>G1C*}>06`tbt?|kqrj*%8Sem8>;|M~UOy-g{eyoW5xJ1WU5 z(8R^P-hwl%UGHV!6W5DBH+YKIzbn9J<$50mAG*k|w{Q%3uUVAm#c!aHherrc)Ian5 zE&-pF`TZRD#P#A=`#Y(BSYo5fOU1i@6?x0RC$1MmWXLmLZ#Vd? zT<;$6iR;CoAZ6GSNTLe!Tg(0(|1U-Yh5P=gY&AyrpCG?=_3^y!e|%^l#Z1@|J+lO8;(^ z;Ipz`-UD9_au)zr7*#PrR4Mlb3~ux0U%=13q!R zpVGP)w}1a^QQm$@-am~Y@32LA71$dP{c9dW-lgEPa=rIT^891Sd)A`7Ned$VYmwxc z*UJL%Sy?YV;1la5Aj$hKj#H#KF*kv4oqk>>dy&bI3VsK^5xh9k{p-@pX}vs$kNiIQ zGJZ^{U2}Q`1+u(1z!yRp$!ph{NnTmy{K^I1NHXHYjN(VDdj5j>8u$2qv}OXcM>70q zWm3-*_M=7W=O0;|ma{#nn{76rwD zIf3H7EbZ(GgggB~&0|T#uZiuzFL4~XL`(=Mv`ZXEDk>;Td}r`vyjzy6ON5B!Z}Jkl zlWtv$s$#Rc=I}V#?sFgL$yO%wm!#`%@ppuRfu!pz_an)95LwdUPkz#r`;n#EL#VSo ze6?Q%Wf|M-Qu|5c-prGHO2D$UVRblwU@9$v?(VK|vQG=hQ9)Uh`;k#>u!D<~`w{(B z#DBiE?nlUX#&~}+g@XQ`O_UmEcni!iE>Xq%Bu>X(%3f_*4tcj z=wuG9(uaL@z$=>dJt#pTxq2B0PgU5^_e3`JMKQm4xp+CSkxzWWIBgt2BT&Kw81tVx zwn`*HER;SEK3O#}RV(Hy$#T0t2A?=bEaLcb9Lsz^17EzY51D z;}uxXd;mc4Vx}ypsIIn(_58xayJlcL+0^xfv7QerW=dVtic)`1Pq=+!Z%?3G3z@>( ziWyINz*E`avG0H*QZ{(($5IUfgr1MeXK+37NRbu|MdS$}dPih9O=tfr<)`2{GtwB> ziRIQRmg|;jYe(KxfaWaU6Jrg6gOM0yV5SCUy>w z2oM31%;HTB^rfs-m-sOf6)2@Zsg^Rl;6{S#wujmRVFgMhjuS-O&L+8A&V9}%TX%&m zSg6I`gey=g30#S9?j$?i`p%BM>h>mG`NUVC)F_Aywv?1ld<9A=P)dK9*L7u*-{%c- zbs3xWZSUeMpZLlrzVeB$eBzG|mGI{se*G0FH5Q8MH$;8mcM0;QnZ z-oCjr(Aw;8A^keQLp<(wb12-^6X2may@_vQjOG)6j9t%@5tq_psg8b8R-viT_p@{_ z_I;O-*Ypdj;cdHaTfO^$>uBmF@OIB!gIgUas|`JM+BSc?$2*tv@9=!JeXcK`d#Io2 zs~cker-wX+tKMU^-<0~fl$)J99OcM5f!4sZi#Z8}q6Esf@F(bYJ20~0 zb~yOTqVt)yecuph2OA6KAfU_XOm(=Ona(UnwqvS;prcH*NIl9#OSL*}B8nbt(kVz( zBK~-Zu0&iIohQEg=)jb4vD~sq6u*jtefUsavNEC+51Q*o0~DX#oahqe;-kRS@-0Af zIj}gIZ5D<+j5@hImwv7qd^byc0{BY}?O##Mmy_!bsHWue$=BXqK| zP)yFyk2YJAh4&N~T#^hR>u+sshr)fbqfW~HN!KM!|70sGFgWS4!(OGbP>lb(hoM;$ zXz2|H8oGMPkwUV|Q-Q$^%0jUrsK8(a21|N|^on8w&qj6Ia5mRkv(<;5He1&a=;#Vx zYe&Lr{f))OMJNkJ?Y1OsHXFmJ0;G?w3Z}qd1qM@;?YI_#_?ySNm0(;6mTe5})g~o* zWuZ9M?&ZlGCfxvni6w) zJ9qX5=j^B*=&P-LugaUU^Uv*jA4wl{PawdT-R8KXZkSDeX5_3rPY-)0iy+yz_*h}; zZLf_i_p)7%e&Tc-$xKZ>df*~Jz*nrBw{K|E6{{DWelX`QI$zJB%H_%sC_g+;Y zaXi`RKrrORhbJuF_wEEXhli*B^Tu=|5csm8%ko5cA@X?dM$u+IuGDnZiEdFEq3zjL2Dch0%YT=Mdj%K6e+ouheO5*!U(Mb-oz^s zp&<3SSI5SAU6LDe{%h_vVDD#b7F^z^P;ab7EXL+6HV9Sykd-IQ6A?TK&`YkL$vn44m-`6 zmxR@jxTM6O#mvK`l0E=kQv!Y0B68j}e%~?e$6=_n<`6V*yqOuJxnze5BK4tyegq#X zl=!So^MwxQ%a~~`=GOOZb^pT(wL}ZL3>Ye{h;mT6@iH-Gmk`Ar+(s04_ANwl(|(yK z?)4`g zg#ZF2)d&3Nw;b2lpouUgnvQr0vb4JTN#di9nUh)Lh2rzvix0I+I5j0)TZ}RKze80c z6CZOjYrH&*j_2~nVl-zlveZYBev2o_Y>|;@1&)c2CW(?`8bY>96-5^o&^gYbef<+U z!pBT66USza7eDxBN%h3xS{%soZUWyraZ;kKIF>a}eg{4pFY1>lcjLHM%Hxo|13p?< z#7E~T5#5fD-0nsA>EOQ}#2_UzUkFU~(s^-c_8ED?%BG)UHbv$`%z-L9?Zb=@VH9W<;-u>XSa=pjEC$1N_lp)W&UM9^%Y&ZS9Ow99f zDfs4qf#w%WmM7}pck#h9BBYftwiSHw?hksi6ZZk}z6QRXpd?S+(3)t)&a& zY6j{1{VgrzZ+xsjoHex{<%>c2Vo<&q3`Z2oL3na{L&_IJGO9mH{U%xUj-YZ7E<4bH zwu{M|W|CT6O8v(8Dd3ipcC_o1gK(vOQ>N5!l=_YA>CCoTf^rbPr6H&sgli8L{9H#X z5+|=r1W~4FC$?nSUgxo|G`9K^tyFAFRJ4<+9sP*@=w&bz8GX} z6)mda$G{gu%tcxC#gN0EdF;+<OX-*)*2wOzmU&r#cGuvAhCDzINO<*HPfmcInwa zf?IHcl+B6I8oBtN0FhYnJ+K8Z)NHdb~y@0sBh zyo|0;+4f^l$hLnEXk^9*k3GW&OZy_*{uiS18SJ-Go>0L5M1F=?R>((#Pg(3Q5`PN( zQ)ERN!^+5I`N+?f>d%TgU&tzvFO|-p9d-T;wlpfA&MuSk!uJ1ky}q#hFEiz5n(~EG zUiJ(^nD)Jre9HgUls{FkOP3A(5H`=0Z!qOAHs!A|Q^DAmb$Lq-SKc2hwyqg`85%QS1`xJB`T$o(efN|Bz!h2rq9*uP}w2 z0-~sc_aYm6!^&}iLQWNODsM~MMwAqCs*qD7gdc&aO^6>}l)m*a+Iv(M{RT zu4Zrr!v0`$sH-cemGu7q@nRomAMs=1zaZXqS;bE^HwNFh)#HWpg7m{~GWLh_g7jBL z8v7cCSmsZLCS*Q7Qt8e1ts3wYUU1mybRPMYbD4L_h~wPXGuWLe1D{RF4NCe}c<&!^vmG9Cq@cMIczndS zT9X$kqx=Pj)6#Z$=%{ep9NnLO;kMI?_7BZ;ihOj9FLLgE@AkQt49(3r?@>5gr~tP^ zc-NoErL5pw%ZKjwF6Ex~>+-UAN&V1$%W8+_pH@3`#nQU;vwy|<*_;IjSZUT?cG{`| zmT}slx?#_!o*rhOqCQRJbu?LMk24d>Wp#N;IlSVx)%Z$_ipj7t?t)b zYmuC3Xrr}u+_}NRgS&u;GYva)0~ZV9ErsLR+#f&M=I$DQ>W=5t{mNEz_7}S3ZX>LAhHJ{Gi=U$C_z_A`(t?G~b%+Y@BCx)(IQ_|H1m7Q?vnpF{q$PA4LXW+7feBcwHEB;q@4 zn6>V{fsPjnM-dWhF^;K^B0Ynd=5HCI zK&KU;#OKoU?|^Ti)UG&Op!4Z$tQh_*gr*&piDR?>6Y|S(x~L@4wK$ghw+eh0O6SF4 zD-L9T4EKVM#*6wT%H25bmGU@bd%(8^l=$d8C8FE$k=va!!5L4QXyyyp= zx*2@b4z(+mQ@nO}fX|Bmj$eUqjxKL3|0jR9D6bJtEQCDVG(1uN%<~Zh-?{pEnV9F} z0q}|W7|Z|36X3f*7Nj4W$1lYj>7Q8E@y72=@X?dYoXqmB@8BdAq=8Wj+pp zPmCXbyNASh^4x{iD)b?I4`uHzoPSy_H&8EPrp#~o+lFJA28+rDCJ3;nJ+!P0_7*sQq&XWh2}IB zQQoZWd^z|@Bwh2#q|H2U-olSqmpM)xGt2tH&?k=3PR14JYQ7(#ZgQm26HqgmI;ZrK z&FW0rB2xj?R6w;vO(99CS&R6Q2y!bU#VVj$!uF^36gmwppJZoD=_Mzp$S#7BBs=cP zqm!&+66^jT$#IR*;7MLiwBv&$?o5Rj9F52Sn z2n7RnL~x5K8#5VsIk6#x-cM{)R{_<8{fUi1Q~}kLM<-!Nsq~VSUh)?EmRAWrjS_hk zQ+ml2q+ASrV+5IpABK_@RaK=>GXD7JCG(wOTw@6C9Ku~KaERd5w$wV?!&mz|qi)cy zjaLL(db;I5U4rC5%3BhwOQu#=;+2f|IkUI>Xsu+rD(gDQe_KY{$fSo19pnt?AZNII zKNvZu&*NQn_*EzA!CoJ99Nn|%viTc!EG0#bBd;>(%PxfG>XNz{?k#3-~GOs&C`pnC?rtAeCO}~}2mTR9_K6JF4Yc1!oqI%T1 z@sQJ-Uidv|C3|_;Gj=;dnQ>iQ*1r@w$?iP1Gg|MM^}F-VZaWB#S+=u6*Hvcyq^Vr& zByOYZ9;!#upgYaOtkIR_Jh61>^_)qD&Mun}D9UJ_jHpu7?3-2OM%Go+zzf)XPJ$BZW?Wm{Hg2 zs1<1cM9@7#t?0v(ICy!wi)C}Y)MKPeX&M5~imuY7I`NfFG+ht6hD!k|&2@MaZj5VE zCfS&InyqT^Qs-kdct0%lIWHO`^|K&REDlmUDMJtL1uX}?kIJz^9-(rqn8&Fc^hbL6 z0iw_VBRG}R+31;52DQKc0WAj|rgGGOpD0$|6ig_!!`0%DuhsLdI_2tZ;3ds6zV_mv z^&f^Z+Xl2x?V-y&;ZkCh***hEb*lu!>a0BA52_pKSSmso3auZbl(AwQ%Y4(PSyN`K z2j7EIMbU)?CV3Pr3r!nI9MjWCs?G+$CzO5+W*nH6IWnd*wn}Euk6S@yWr=m*qw%7C ziE>hw=#}y~WNqME0!n;zo)XdR_{ja+13vtZNoKyEgQ-4-OIyRDA9Ok!8bs6%waXuV zpz+#01$>Ke&Yb9;kmY>}d~;An^7um(G@iU0Ey{aVl80M^Cz5BLj{)$VtDl#Nc|J;@ zL?`A$R%ZJyDq)R>MBQ`2XGOW@PVntSCAwa5J5v9i!$+RC)9_;@)*Mb5=@lHw<97!5 zME_3Jxkz3nv}UzT3HS|(9O7J7In=_s- z?e6inT-n?0-yC42bxkWu{XIS5_Kk38)@=-raUhQ+sl0p}XCh^T$MzeXG>qn7Wzri zuzsNDi+LW=v!c$sStTtvB#l3Vbw=egq4RR~`j(cK?vn0nN_t>J*}ZPs3{uDxJQ=JFBh)+E?($=%?hR;BtWg{nYSi0B1v68@%o1{C zs8nAh4Fe!p_B6PZ>Pws_69!nRz9`if@_88q?qo~xgz%XJ0Yd5i4l30bJ_}0qMLg$i ztRPu@PZ<{d+y~*Ex5EZS{o4lxqT5nP^^w*oD>S~*V$|Yay#%k=2PC zhGs`MXlIYN1pe_>wOxmTYy9EP_Rh`S%?RJo90-TI!rdrEJdDlF-Mt~ak9K#TyE;%& z{qa_P;XBA5GsPFWCaY>MIjr^0?1ny8;AJ!W*vy%1Rv(*{&kFhqa|%2KeXRHtmVd)s zR)BxNm1^?0zZr*jF6ZT3IqdaWFr+6)s;G~7PGN<8tgw)IaEvHPeRFd>MIHwHHgy)s zE4j{h3R=o9%16*NYLyk_Q$IX2`SDDshA=Nmhi6nOz>Hex7H%xjid0bL`URt`7ZcGpQw-G_;M59 zqu`5|I#G!EFz{aDi--3DcU?#jtC0lmIv<7cV!|ybpQnX{^N#P;pb3+KWD|F#z*1&J zDi&as!cMW$a3Cnhq0$Oq>pd1E%PaA=c&Ftrd145heE=sTWrN4|O3Vb#J`JZWfUqcLjlW_(Uad;Z0NPI$BJ39M<~-0AP>4F||VHE~n^ zF|F|zwKlG)YZfh$rOE1WU{m`R2~><`Ssm``>1yc;HU_#|!tJ4+uCOvh*FbHB#)&`h zf(`AVwm{gPK{em}NI+UrE>1ExwYi&&|E;RJJ#6$`D-{qDQOl$3YpiKc$-x z0kW$j=^I6>Zf~_Vb^DWUU!if*BTu1mqb_s4W3;BDDv5=rZ&xMzG&lCDk`=HhXwwGV z-)aW|B7Gw5{#QcIGm;o(aE2fox4&6$P!qZol%tEUTi$w=mo|`b@2{k zLj?DylYD)=I5gmIe*9fe2B2MG8&?BSzF^liv_$}0(RM_ZwAC%!>m2J~Nio=z>{h2zqZ>lfj9{29l!Ksb{AG@u} zcLom@)o(n18TEF8%e6dMb!@ve&hUaY?$p&-3ys*B&pUn*_X2CskcH~XV4@%TYF}6*Ztj7tWKFpG`wt!oIM@%^U=l zIi0Bvw=>h3<;ZqSb&$PvCfUK6QX=NA_nGQa)*QRxRg~R}4?%UJxp?s17QhW>6Xak@ zX87(A;BL7V;Jcr~)^D~+7G(u2$440XBjBSM5=p>%3s4|;=PC@CfW(Mb94|KU^@1;* z7))s`^0K_^!MEJRL)lh*Wb?&m!AIjo{SxIgj%IV$SHXw>oKK81(e3!iu-pKcE<>3) z?LvW&PvVrhqpE zyjh4f9#kHnWjAWEyHrU&fgmV)iz<0J(c0ok%896oCoVt%Zwh$pF4KTBWd;{{IZ1v4 zJE(v+1-vx`SBE<{+kj<)y3UY|b*O+h?YV}ZYX!Vr*$l1nfWJEsYr>>I{$t*1l3#id z75!q9yr{^#O;R%S*PEp3Dl@oIofOBYfGOaudAxnflM#Cx=bEg-Z#myTSPSpZPI!NI zt_hOg;*=v>+0uG^J8lX-7tCqf_wGJ;rhNb4Ykt6H8}9Z4IIC?O-gRNlQ`nH^pqbk- z2S-+&4-4m!RGap+>vBJH(|8Vtfk=FK5E*quPKiKcyXA`du^Afs1JU z;A@Z>^kXwLHXm@26=-ac#77VoC8B0%?BY?NF<7kCRO+rjIr1ee)~W$`#lyU6YUb&V zMaRdyHWc#y7#3@@PAJTaEZAb~++qq%u0|tvZKcGzDeT|e-npqOViRYS@JpA!*0W4dh%*qKrJbasxE7dY_0>17nB zm(rb5UUqUy&UiOS^(lXwDgRR`Pj-5*nDT!z<=;2uv&21&x>Uaud19e4I-xPdOZ?$A zE&iZCyrMVQlQ@7#m~eBIX2U71=ZebMB5=tZ@Lb9(&xbyD-?pe~+aZy*@rcLdg0m*U@Ch5&l7uDPpXz2of^Sb7SuC8!vJM0?Au5jsP zE4n&+mit@Le6vQ@^aMhBBO)^I($1^(5(IT@Ztw?NOj&fZyT?@K>lI?C($bC)qI@iG z@97B!7InfQLgz(YDA((dZ&d!$5p_8VfK>pj0$@7~vrlFDm|R3v<%cu@U0Q((@QuvG zfhA@62*-j7fK>qOnz5031;8o*Ry=AI0IL94ZoA1}RBV723V>Artazv>%SSyJj@fSz zP)cR_I4&%#09Z@fwsC{_TDD!ZR~xU8AqBvi0NAJv#8T`RoP5!DqtVys3$hBmmc0GJ zs#G7qS2po0fL~c{@D^YF5GyPnnZo*g2wz)QJJ45K`(D)<6pS{TpW8ol+J%(c;Q{C5 z{X?_;My_!G(CJrE?uR23;x@0E?flKioE)dm!^7^@4Y4bCc%B~eoJl;ldK`DG^fmfc z4X})9hbS;^K_P|4rE|}E?jLkG@2Kx;E7+SlFf(Q5nXIsO=+ViSl-ExCS^kQlTWiU_ z@@Jl@kAjc2&bX-_T+Zpl>zH{)>cI^emyCFKrVl-Os-yqRwxz!Q#V=B5TLO;jw$(p- zAbsc?YhllcP`r(`HNN^o0)EbIdo_LJWw!e_BU5v-?$&z!qKA6)3k1vsHfr>6hbQ&D z&o+MVXs9{oV7~Y1;i4SkqOiIEV_7)@z0|krJyr{8duPz7asP_|i&D!|Sh-XGPj;fn=p+&7`!ql> zA`ui*pWAa&#^>BOr+?nHEp2=1Ej;qB^O@Xh%E2|N-6-HoZovm2J&UBBqB~3loJue$ z!B2!Kk(nS)@hH4F1v601a*)couUJ@D;_xGg##>LVq)`_HOhr^28wW2JxL78S#{22) ztk`j(`h=kqx)u|T7Z);%%5k0`Wh<@C5UqX7X{R~!{96ski`j?`$eX}Ox%fzxjoWp! zlT9N7V^vxOPHChPZtdKUw6$d)X=|6-X)W1BKxB?kZW9Emdrs9 z0ofRQF7laJ3k!AX)9FPzy@Dv#$QGh-!F&s7*%VE8r5yAQD#sJWi#wP2W)lV9S)gTT ztP->ww3^Dnx11;*QcZLoPo{Nr9(28aemCfhsW2NSN~YcpClV;#<@nEUb*^NBK`|#9 ztau5sw7U99;yWCN(X6C10~L4TL+$dXs7^^+iT6d9@en$=oOe<$(1}?|=Y4eCiv9Y; zY1WiQoiYx@;GFdgKr%u@zHroL`g|UZubY^!~d9M=6eZD^)Xzr;hLx7Cy&~p zcKNR+XuNi(gO6?ub0S4Aab0w7BlzZkl04zAJf6H;z(-?mPG)%rC3*bU8x=@i%zS|F zT(dCbTk(I@d5a(%*Q9ak@>(B@t4<_( zc6H4H-Rb-II&rsX6J_YcO`x79><5C-%#SR3_IEHO=%k(okNsF2f|7&wKS+6+m_JE* za_$g)KAojTgrUBheL~99gy!k_^^il+t(WTgJv@(hx)Uc_^%#E=H-EU{s-rcu7RG95 zMg4t#{1mX*(z+&Z-O4pfy$xjzXP)V85Su-hEG(T@URqIFSy5TGwyM&*sVnS-@+2#1 zT-ms&{^G^wBD73nbJInOn)%VnrK{=}&8wqhi%I}-H>FxSy4$;(TcE-f*wWn5JRkom zlJNJcX$O$k)nqjbR0w7jf?0)NRw00Tzj8c8-OnU5;>XTA^QmRj5*xLq` z(|5ee3M~bt`lM8!lXV)O$OveY)V-*DPgwc;Jnk-& z#OY zo-&idDCZU+r1IRH!XlJ=3#h!9m!CEh<;-(B=bw#ogkzpbbqko6(3Y0R_V4dw*%L|j zq%4w+P|K4j?6Qa2@vv-O;z7xz>`4@&c@j7aCsDblhzD)X&&F|~hw4r$f*kPVPwHb? zT-rn~88Wj_E@V#BWr8z{_$PW$GKC}*=49m)XU;@Oo089^WuYhF$)Bj<1SfOwW`ZOL zDHo^`p^s+tyan*ZXLJZdyJGE|5H`8^4}i7u1a|y@^am+ zdXz_s(Y&xPsI0W?k>YW!ZwC67LsytE`WEhL_4oKS<9V~Kyk>OY-Q#b$vbWp6IS^%9 zZzGnnXp@35b1(4bVT+n8@-OiaI3n{mce5OF&2@C73CLixnKVqXgY0z;b;WdEQ zl)S??`&I*}E3JZS2AabKQH!IZoE67}<~9L){5Qxfb!=Y+@wyasG0K~P@@AmC8AP`J zls5zA&7iEaT}1pE-y%stddV#qu^pDI%7udT6r`shJq77m48EZtJq770NKZj}E%L8s zP{nbMXg$CKfr{g7$uqrjC*NuPoj)$5hL?Wpv6SOVunfxCtF0itIFKISf{fZl{5ZHY zh;vm|K|SnYvt26~JMa6hufQTd6@CR$9e1!h$wuFCbWc6`0$5$Cc>_p4;5?esMBV@< z7mz=I)I-jr15Jx7-8?dL`BNl|4DIt0i_1)wOd`>qdR^{yH>G?IUgkICe!3iavL7eQ zP^U1B0_9uuFb%{h9^UxFGQ%bDWadklQ5irW!XV&YfLrTjl3A)LC1UCNxT!8>&6ck3 zpzHuXgw>%NJjKK6euM$Jjt`2?q!Tk%R}Dc07O=WCm=r5m-L>GOF%gNziBb(d)Ez!Q zpj*L5b1Ra-`p!pz-0h!&Psku%alFdJ_Z;|uyu_qt6W;;wEs5b`EQm6JebVVX;A=Fl z)Gsm4bX}juN9LOYK8WOeqMZ0{!v{kf0^z9^eCtF;qF=?as7J;9;G_D~t{5xIlj)kw zcdyj0xNhPD<~VTI;pXP< z-Vj1wcXyw=I#5v!4_YNHq26=x3WAN>k`+}|rJY^Pt=%D%2Y5uobAvp*A@ZBR*V)w> zz+q2YZ^uTe+R;r}Q~_5Y><>1Fy1If|NpB~%0XKIBTATeXEocv=+_I%P6z=K?wDh!h zb$YD_Gi?Nk=)wGfxgDZ_o|AWZNE(a+soc9b5rXNr)^{d4(8ms=rA0tzt~!|edBU-40(Xk;fRvHxeeP9<`!Xi^mibbP&hXXx2&jb1@*(EfKjd|s$2oZ(4%Z7O zXGHRFxn5K#-~tXMNMbtEan5|MbfjMsoUI7-2hKfRq;?g?V%COu6HE-;KU0 zhgkolU9~fASad;K&aP>Dr{rPD>9AuN`9bo+r4yI;i z4$MqrGjCXw2X5EFl>SwRFPoe`GPzjP(e|QeuJ2Ocp2aR- zcK?eWXWLH6eft;d-FtW7v#tKA0|0HE%u9VvAN+xVBdbR1${R``tt=TE!OeK*{)Pwf$I*;}VI4E0_3;_zRu%J8t_M$B0n zcgs%L24LW{g(+;IGxC29imiqnCtf1~2C2`zCf3JzU2fR<*Kyph10v=y8n7}P@(gzX z3yhDT7s6X@LdOJ>aSzU9J}G-}p6a*=C7Ec63gn_c1)X)O+9d0pU(2jaGZ zPX=dy20j5Ei*g#rUK8Id;44QN^>5)wd(J_&Y+ufSsY_ZzeXTLLsRNNfmqL%JZsrTPh?~A*oi} zcSgUeDI`@PslY7%VUbjB(_!AY#DD-i27=2G-BID&u8mg!;q8txmM7%aTN11r9rPW& zR#)PcMgxfBU6xf;HHU3}Bd52IrKXaH)U-76a+;dPTzzw~1MPy3QV%?<7UmS>7r+Or zhy1S2)V!7!cnUabAUv*C6)^I?%4Xsp(#h<_v=99UaAH^j#sjUYu=DSY?EZsWOJ>k& z4N#Ps7Azyf7QLAEgO30LkpvjE5(RR1-T|LDN4(rmuHkU)_?J5m{3 zE>cxk-@9p) zhDzo9`4u%*U7W6H-x6r$59GSm)rl|&v#BfG(JlQ|MStBZ@2e-Rfh6CKjNMB7IG9R~c4=1OJ=)T5 zIFG&=JFFWgJ(Nv;StDLqQwMX>-1D4wvO6^ItbN=&Yo_j<)eY~gsoXoObMQ2W@Xxxh zsrq>OXC+j?@Xy++`)38TK_+QV;g}MXg9?B_xLFb`?`#^`c_5w}*-fT)oT(1CGt-&n z$mY#BVbMqEiW6}e33+j1*vKTR41Qv%{c_M#Kr^`oAP%IIh$-FUQay2KHl=$9Cvwm$ zLM26W)F+xzDii5%;F(69G$k`Cc?#gb(=DKq=VF9rn`BW|n9_-+TEM3naB0i}ZLC3- z29wVh=s$yRxyHi3Mg8-U(vzgs}d%$Z(p@5nEA2i0LtWsJ&b8IidZp#-e+pf}cEWV|7&6 z#+o=$8zm>K_)AaroN9PUjcrsRfeHyUwoY{vkGnV1wp^YorYPl6@qTt5w^;i9!Mu z5*R@Xg7ki31H@8DpfKdNF^CEYYzS(8;%z_O6cQM@xA6|5;xMW>j8=frMBYe33JHYm z+sDdPYV0oJ#|8w9G8QSdivJy~bqq{$I0hWf{YUmYZ#aCR6Yf$|Lf^k(Al(V4sVUAQ z_0HPihXR)ei!1Zm_Px80u{rM_bRDT@&TZiv8@4^4{^*T;+Xikt<>iTmPY)MdsJTp? z=$nMx%&W9q_||uCUEvAe`0kBqkOb$RUUrCi&zMFIJvHZ`ISs8(Vb_~Sam-09ilYot z(a!nu-0MG=ax)16eKDo z0s`I_Ra48DLBLm0d@nw9u>|^1iU$I2!4MQhkPVFy-)0bSH_$69K^q@~>EBo&pa861 z2Omw5NCMnjfC9NYn}M7OK#zFE@nRF-mEaQ~7x9U-76-DtF!&aUlM-#ku>j|&_%ZNt zAXh4`(I&6KXeshU~=lr}+bnNn~CJkNsR4Qv&1;OL@A#|5wTr z02h5eolT4g!@RlK3@J}{P@$ghfgJL;xm3?@;CZaPhO^hVw6t`WbYD}_10Ues>o@v4 zHgT!X120}ZI#5Tl zM)8bV&0tcvkd=8Xs5i7V)yp{2gEYipX72KEXlPU5NVgp-HaG&w#fE}Dm8UAr+nhNey za3AbH^`Oo+9!m=DE91{4yf`$h4hL3iZuGkB#GqAhpS(>}HrfjbhDrJJRQ^2w;r)5m z#oq}1n7H+fe|1*jzZ~}J`3INxv00PIyC?VGS(r0(=1h3>%$_)_Z!W&cyJw--gX2PP zVIT9%A`hU21>i5tDJm*LdA^5u@;$^;G&7&dA%PX-GcUY>dKhXIc-X8ymOqmf5!BI{ za?yYEF|U`}EG#5>MMaty(E_bC@XneAZ=r=bo_y-X%vt0`RBOQlp1CZ^>%k91oK5>rN#j)87=?CD8mpV}>LvF;k zE)FA*w8ZS+7S0F8MrnNew=dD4OZIP5=?W7@(h!Qa#|)zId?}A0+uIFLDawwDm4*Ys z(pG>1o0~U<{T(<<1;C=CYScBYDE0UBgxfdv_5`{$9;2;NRNUO&xv48s*C>e@MS0#* z+2FB9z!51MJoc1!oTx8D-jh*|*sw;TynH{AJ>CsCKMS-NAF{{$Ch}B;`g~&B z=aFyCnBRrbp+8y<@oe;{ytyiB(N$D3ZqnC0FS;06YeD*K;D6fohOiIx^@b#Tkp}=A zM|LDgpu!bf$JZ9*&|uPTEhAfc$!`iOT(Kkx%Pg^hm+ZJJhoZ^BM9PdXiN&fMiYkYq zVtddYJdWKiMZFLO5$s4n_HUi)~cU4oWq&C2CfOT^o9csUA>(>0h{ov!W9*+sBlFyuK2MqC5*p!Y!y$0(@>W4{hY#mpyVtR zCVs7sqdPBTMQ{w-_)^6OZ)zO52FJ?bYuSs#$3nzem#6X7A5LXChC!g)$?XCKailqz z!|j-ZUHD^2Da?6&_LPa(?@xE6JJVC#sqQql%bo6ayEELG?g{Bx?rhz!DQalD_YJw9 zxoJELK_CL$7Hg6YB_KmKS!AdMf1iw@9R5CeAr8qvh)vb=9B%_(vRx#=LGB`;3^EmT zq6>+LBn(3&x)kZ60WETgxFVb8k7PwQs)y7vj1Uc4IVgE0&BRD~K{p{oC`uVdaxQ2& zXelV2=ZFw7JDfRaqC=+lsoqi2`G+xv%QBKolwxoO;e5-XnF|9<+ z?be`kR@%KDe4<@iLzLpl`y%-2wbN1G=Ii){B#+5n_(MP2`{fN**MI`)MuzYF8Y4S=;`SX#dqI>W; zvGL|`poQCOF6{_)g?s8cTlEmify6OqYbY{rEfS|$2ZFT?t zGBj0&rpm8uN2pudUjpr*5l%0Hiyf`RB)A7~2F-!^&ZjJB6gZ_X? zZ~-RrMxy-6R($OI%8t65_^|+mN549&z;Mai11sTKHWfZ)Qv*S7+cW8Zd%0nVW$gBy z;!8VHm%eb@PlhIBH2ErgOW~%GpyMsuzTjKqYx22{WI9CI!flQt6I^q)Uc0S*>*L$9 z3-8}baIyfKcX(V!@ALg&y0`6VNZLK5= zfTZhld{4bKumd~ngfTn4PKN(;kh2Oc&!nn)qK*3c+$}e`KbL;9>+@;bQ*TN6!gw$< zkVg�oCEaPUeS)$Z~`gjS%pa2}*!f8PKBjpyi+&s2uH^QzGE%edfx@o59srQML~s z0B9Pd4oaY%*~YaW;KvmbCIS|o%;2gMf~?rMmH{c7Erdwa46a@bKAK9A2&|)I23Ow& zU#fPBe~V)?xcX=C#TnKZkkbJ$bd@Ae9Jb*%B@?LuB|_f_!CL75r61lCxyP&1b0-{X3zt*+MD$G5G$9%F}OV2zoCh$U=W zORuJ*_%=1$EykMMnha=pf8;NDg_2q99-NGn4IX<&VkWcLH>5n>{BKKnf(_r7@&p_H zUC-YHN?vGBY_GFxdN=lj{VhH1U7gKv<~lk6IL4d^f3pc-fl{*yzEkj>g6|Z3=WnqW z2UOW}Dtpd^U{A62mB?0r1b7AczE_f!V>Z2#mt%^gl)NAX-zoU6rA%Jo1ivM^v1YDs zJ8+tU?-YC|fmbRlq=N4hd?$4M#5+ua=!g7}R`A^z4p~huDv}>&1>f=T8;Fb)^@hP! zqZE7>6-O%8Cb&Hq2m^uZ2JP(emIS;dtJ<#nhqvdH_7JtLONyoL}m3SrNjV@jwF!Oa;h3sG<{*&gf&)XTX;$ytq!A zj_>LD;Lj@nKbtX~LGqMokO1$l)8WxI&qIHM0?+L=itj9@NaBqj!GOhRF+nh zv$O`7ngq6#tf;Cg?d)o9?G7>5C93IE?l(QTJ7IFJTLYJJ*REOJ{ z>CAFuJElhV=y8TpA~@G)wJK5HW}NF$obAJha4wi|@)Qr}szOg>-;_FQOgP4i0lXAi zFe1GA)Uk0c!fzCsC`%KmTe0v=j$eJ{!n{!M{lsFJ@o(B`xd~cimU&* zcQ>0&2oMO>1Q0hoG$?_*2*LVDHpzyEJPatPv|*Dh?1sF$2|ik_sG#7ZO;Fo_kE+$y zXA8Er+LnT?{j^ULwf(HE{nGyXP-y!nsid*(C;#7>duMm<%_h0KOaJxjcLz4-o|!Xe zX3or=y?f7N{NYYGk5R;|(bZOQ#!4Mkg~gi=wT3!%Pc@F~Up2M{%hq6-o@?!s4ikJ2 z&Ar!>Qv}&39oi=yj`M>`ygt#73rcjY$}znX=F#C#IB2tY`;%zfwgyZ75r|hbrq?|Q z%5}uMp2YbW19v6J$3E#W;XBNBK$BE2_yr$GMjc2mSrUJP+AIR4C&7ZA+LP%5)lXWX zX=|`-4VJCJ5|3cw877Il+SXv%8m!{Pwsr0GQDSwqm-w~@D~5_?#CrT+r@`V+8l>&i zRtbMy82im-5?U+XNc?Imy;_`lD_(27(OA`0F^}8-0z4^Rct>R`{BZ8td}MIT=BmNA zDeX07&rbA(LTvub!*>MP0;Tu+!NTXO2ZsxYqI#%9DLFLX_h3y^NI7w!vZMIb;Qr|= z2Jh%VOwx{fvu{3rMe$b#9=&LaZ{}gRkipe#%jS|uWKzask!CvL@)#3w3GptRzaTFF zRH0KL^%J==@dU_U;KOeS9v}PiL@qd1z0+iE5xsn`$hvN)W0&wr14rH{T1YYq z=vZ1disMN`z>xUp_;@HIn&Q#C$+`@|!K``vGYXF2L+uIAt5}-1FG0q+T+SerlG(%T z6%1g4EK8ksE}&ff&2cnuk)cBaMp`kEghtNnVb%&dp=~2tac%Z63xiICDHS{kZoo(G z-wmK6WvV$fB187{`X=Z|Ueqs+80e~bsqv4w-2!Oo zM7!cPA%1)C!CbbB+U20TLLd^{hiiGf`#~pUCXul(0uke){0F3Vc`#q(QM=GcmKDbE zY#U7@Sz1=CsVFU+8u@_HB#f{0-SS*$z!j2yGk`6 z(4a`8LWwjy=2(v(#ZcelrN%#IP22{kn$j$2;x%pB|S7SPdTh(ww!N=xvG z>N6N4&7Q1D64z!;+^;|fwd#np!Nl)(prg9x)QAjOGqu2?ChmNRPRN;{S#x$V=wfNk z78NfpTpX9CtEgBbAK&-xbN^PFu16u&=*k#4`AumGNz?Tm1D?iuC7d)}uSqy*x_&F+ zw08agocOQ6=L4zfGWg2@b&*{UvE)n%)?;`TqRwVmMXFpjam zKk=fatZ`t(}3b;ZWzb z$$Y~{PMA$-N4A~dLd}iihK`SU3Y@L#8beR5okTyL6P)%+@_(|jYvdbNtLm<@XD<%1 z1yFc}Na58ODv3C{RSdrIv64fN)hH*Pt9_$r_0ZXlX){R4H6us3xaG!laf{QrO;*j& z8*HP)8MG$Ia<_r>}XE>Po1-NOfg)Hd`#wjiutM9!15K4jtFxnBH8-j2U0D zaIxic%Kif$WJnQju1PdiA5?EH9#N8ej`2>*f8+&5eqCQgVKi^xBv*dx6-e9lqEy)d z%_T*Sj3yWRX%vADIFr*dX;RR!Rp4pyfw&&Rht7cmrSJ{k5v}9h^+3Gl39cQcKWH0Yk!e}U=*VlSX zsuq7z(M4@_oUM+t)p52u&Q`~bdT^E@s$)!b7=9jG_x_5>!LmXvx!UyY^S{#bOnd!f z)XBws=b5BJPHQKz*p#Af0s$(us?jKwv4&< z3N>8VJCxe6A-j68pybHlrRxx7va!dT(wjP%a{5wV^-(9A(yw@k{s%dTZMhXR8=mv3 zgDF#|_?(B4(?~TuKDNI&xZkVv66L$XPtB37GVOmJUXojl9I5FuPyvZvu9LS~$}Z8AKnEDju%HT@1(lZ- zRbUn9Xfj0_O%?c6&}6Vpm?4?YlCWQab{ZA6|q?L&s(Ph}MUQSjqy7kR`F8pAUEh&k@;R#>{U zq_n7@xD=VOG=@csi_5h9@x9`HbTPFY)fj#{35{X6t@~af1O*W49ad3GA=|pUD0K{J&85LVSqdT=0Dw*U*h|yaxCu zaE*MN%?=yzIqX#fKA-&> zc$HNDsGcq5LE4b>L@7 z3v8`vL#7fIzO4CNt~l7f3hDxU;gBnN9_vw&YLm7i@W-_Di*zd|Z6HIN2JsNw@?1yRqDir?G1c^ywygGd_XcWT4M5(VOv!><$C{BoqB4_8CL@ zWcHYZGp5BU{x5yK(0)W|sXhk+|E{V0c@y4e!mrfjDe4!S@Uu<$DigldgwHVHlTG+V zCfp(6PfFt@TaRx^I6VRWM8c{3gbB~m$A%(qJ93r@FEioGb$kKnr(k`w8Sr#=j{(nM z-!$OZwJXot)X>n-k>7E3erH=-bH}E7e@lH^TfToQj@jOHO-pk=eNAuTzlZZ1L*Y%8 z-u%kd8&<5VTDi8ivbG@KyL#h#t$5SOLl8EJpUd3Bgum|GWcpze)AnRJ-av#~{mtXs zpP0DSk?Dx$j9s^mOh96lBQVE0ihDdNfqtfGY=TJNDw?;p!Du5FL0w@XlOGm~3PgU9F&`)~ zsw*ru=9h?kTu9HCMWrHtu`$0)FOIak#F!sx7Zptpw#8`DoMmjS1cTFhz0|<9 z1cTuDG+e0{B}-wF1(tRG*4DO8ZecZdZYM0Y8X$L3#VD}FXi;Nj6j*5_Khl;_LQ9N- zToR!-4xvm8fg~z*wG497+BFJnX{0#_Orl>3325|2Q4|)4hG`0<3Wc;Xc#UG?hzqfN z^aA6M3yVbC#m2D}7A<9S8y6OXT>D*tu4xxI6JA_J3JbMqm3|ZzE=F~OvD~=UbCr0v z=MM*}TKv8c_R%%lJ7Hq3-`LU(sl6Ja8#-z8Fs?asEm8xXjHV@vE>!Do{H7$mU}7}Ri1mUhXli4dR|txu%uvN;liTA zqD32ui#%J}!XEr4WcgLAtE#=1)?85N$*-!bU0+?tuU0Q#2%n0`Q}Z30Mlgm79&Vr!vY zEt%?J_)H{Gzt-Q{*w&If2hETpnT{Z&SQ6FkW2wWj9q8=f^W!|4Xz!5hh#dd?m>MzP zGFg5{Mc+QQ2_U|7BHoR45mgOWb8y$^e@JNyN2>Z`r)sC%9pI9VDRIJxA=JL=Z@>}?fC-eGeNy?y-VvS$@v-#cpc zlisPXDQ`UNo%|a36x{DsQTJ}|q}Seh$2q4DT%Ythk@K)uc~$Wg9lGD^L@C2nMJT-~ zvnsowy+-wQ1+#)_+1;BR$9AySg8RH>hjV;=o7-z{3f|@|Im~h|nSLX%@}bG$R|b!( zU0!#eJ6L{v2Xk*02W+?392l53YCBUfargSp-; zAL{toY?v-yvfJzG#bMe`GFtS)xY5xs_~rOA4?#9-x_vN}RQLN}EU9J%SNJLi71yo< zRYOzfr5{tBFAh#{Iq!PR_f@a^wW>kp0PfiD-CObMWOc97&*rFiW%!h?hnkfAtovp3 zY?)GV+^IOa9Nk?_j>oBQ^l|l4Z|Okqs-a?k)vq54edF%~L#r!S_NqO*zoPW)akI0D zj@|#(u=4=xQu-eZy_EBH@AOw64zZrJW2s7(kIHvf0pI87`ROn_!shhXIQH+ZqOs0C z?o`3u@7TNB`|IB9{)a*veS6$gUtjx-aGSEDt`;@KOA!O{BoEb*i+Tz zV{_*F*x7IJ-cVnVhrXl@<}P3EI~eH;)qF6d97{`GbMyyF`K}8TybANw{sx#Hz_Nn`w z`_g(a7n>&xWIGP<)ra+(N-Hq+#NG{E-VJ?kVq~)qQVsg7=}YTT_j!(Iu(U4Xmo|M* zmAX&s3(NiCaAu~86_!6eZMvhI`&_n%PMzICWK-}iWx)}GcwM^E(($32do@`KcO2bY7R=an4vo28%?r$<|NSZ8xw zJ*kK39?yWB*xU!Q-A7$1?C&YV>I2itpZojJa8=ct!_#)SpJ!(|``tYR-Tjk%Dpq-R z*RpEmRd)}2p5g6s#sCy$7pFNe^~; z)xJF6QlHXKr4#u2OYKpbFnX3*>s74`!b2x+``6`M#+BVm;Cyi z(817-IcdXc!Jg^0GndbD?p3-EhT5CX33&$}%ubuWd{(#jEWRr~6MAddedH$J?LK8M z?t&g?H}=Q!6wEx$`|Y&D*Vk3ih|kAf?e0^tBb|4!un82bi?56F<9F|%UeG5aXMX7G zA+3i$#W(p4vwB(Da4N&Ka>FdQp7w0ouls9m@;Q1ka%lgiy<5fJO_Ex1umF2E>(L~o_PUQbl^|bd zbhWoy?Y-Hz)>qf>xOYG5P3wDYc)^ix4Y0{6ebs}*MI`mi%C-G!&tF3~;k)34oGjmF zKI<7dgZM5^?Qwrj>*aaDseRO!w)lhWa?W0^fpF zRW~=aH?6GxO2~Z}_ulLo)32QMO|N?ImBA9+gC`4^=cC!K6R-QeP+CwvclvLqH%>1f z{A&3lbYM_>3OQ%gv$@p2s-r5K&!1vk_i1bYK7A)o<9CuSaiw-vdktN$r8%8L*UaPP z^V?oi*whuQ$adg6zr7|!-&<3<@kEB1=kvvDEB88kSnhP+vdEptJk$ezAJ%6??n*L) z`v?r(DUp#qrH^gWApI>~tzCbwRD%aPG*e|Vm-gTz4DG3u_)wlmR`_^8Odm5JWJP$5 z$7cs<3-Bq&M~nfNk#SKOB`bW&K}R2%Pm02nnF{^QL{uPG2djQSXMk2D zGA{RKUAr@Nm+O|4Tb;WddxS60R6VdCnPpM}R0zU3gd0gt(?iC=NRs;kou>PZ06|rl z@M|YRkx?ryxk)@a*5 zaPZ-l@u+_R;eKuE*%tUD5k4COBZzwBS_--Z$zPRL0CG`YRKS&Ur4C#0)LD01k%-5Y(Ku5kVY!PEu5k!B;qk!=12%`K( z9lwbnEY@!&h;_eP$GZrkpLY>NKR-hd{oF?o^0<#6LGn7>G(GZE`^n@j=w+PXF?{waz_VH4HKC*NmkZGl=_sMZ## zwZ&>}iCVi@tu0k+m#DR6YVA@-ZD9dEh4>WVQ;bgu-~LqWSy-|7GND!!`h!GJTt_Zm zpXFj1szXuOfI4Z?$U*R$9&J}uXY0N~a~Q*VJM%gx-1TXj3! zPIrpikVORk3&f5d`|vbnKW&bIRQHt2BV_$bhD|L2tFs6a$GVsk>>7qB-5N(j8^A_ z_AqTuAY6Vof>Ru#n#4u*!|_FhFT+zHDy_NK#uwEX%_S-->b@qb1-huvNZg{jQ5|=h z@qBQ~M1_rIyhVH}o7*$~%$&;R9!jdYUaSr)TmBhh%MXpa1>-r;unzEi z$afb{T+2@Tf_Z%WJJj5qw3)>{xHXfejbQN!kCjsY~D!;uh8OgMs+)ELbr zFRAl&NuiNAZa?kO^v>~jS-ciG1)|cL`)pFpB`PZFzV;-HpUiwy$C%<4)$_`@s|s(7 zPMN4~9e-7g(OmMPD%VAYM&b~a_NdV39QP@{!Xzr`=`HT&4m!u38FO=vQ~CIY{fVzC zG!jSOwL9YPkj<;8f>hU}c zSO9n(AVu5SL2w=3BomyBH@*b7;A{_qnK-jU)$)S`k-wYZdb}yt;Z+VjUx$wnM7>$~ zwL|UA1*G;C0;c=1?*Puio8uLF`C7gFOH_`h&0d0--ro{L|K28u{-xuFNWT>QA$S@1 z5Zu7nCV~?g+fNYvJD}&ktixXt1bx4bzfTbKQ}HW?_;nH7$XE{`_4ffl>hG5*AN~Ci z;H)i-{TYzT2LY+PAQk24UkO3fGY;~l1a$m24+aiaO7q&8{_IT6=}V(_3@rb5PG z#Z;_?Jc5uJCCl`XL0t6ID3WFV7z(GszOP7IxA2*gBc9f*&sbNKsbJ{Y``=bfCX zt4Q$#&C*Wqv-8-6-uQ8}KA z(FLxn`4B-o)1WI{H*-2cd>cX2z;!UR1@QfrppyiA(QH$HWqyMY&~Nma*Qm6=GXSV$9$6DOHGf=UU zPlCor^c|w)`~=>;P>U|6QR(vx#7y@z=oSbfK)xPg(EZ#ZzY`Yuu z?a9C_Kg2JIj2GK4PqFxwgAQM?Ba)flK8c@4rzU>g_{jUvUj-wol?2oea7fy<7%newTqR4+JVc^K`;k{61-sADI{lerHSk%=gis zK!@LvBa&Ip=U{^s>vaAY{LTZNm3g~M;&-mZ&paQW2b~r99R-~jFTSREiY33PW!Csz z4m!aPTVaHsS$;Qy&WilL4LTveLW!Swyg#wnzYi^q_77W9q8@MV*kp|i;fpnM&%a-ot5!^S>lJsvr+l|r$v6Vz(lMU zA)i?5&j&gy{kv1*cahXT^L#uDI?^T62Iy(`uATJ`!^3l5&aYGQ~%8JTLn5R^1BU0LVnAo{+aph2i@g* zxeUzn@fV5TN{OF&J{%WXliv!^iSdf(u~_pFw#e^!i61>1Qi>(NUxUty{AOVh3;A85 zvE%&A<6Q_kF<&|v2j=y+9du&6>&D=BzeRq(mH1sM@vFnN{2Y-{Zf(5FK_|w$LE>i~ z@8zJgGTsM4C&nw*SFHJc*&@Hm*aQT>E2aLK$GZe{R_3=8bYi?8k@%U%yAyO)_Lm<> z{i8lniZ$Lr&{>h+Qg3v;evMts_3Q_omGM3RIx*e`iJy7AUjm(#@xCkd4=-|fiZ$Mu z*lewgw*howez!{e%=3FY=&X$QWzdQ7h9rLG@xEcPe`i)j`?qZjel?)8GTu)~{8}V_ z=J9?FbXLau7to3Ewn_ZV<8|Q6%1ZxMfKJTE$Hw3nw#e^!iC>4r&ph5=gU-r$XJL_w z@oty+na8^jbXLZ@9du&6SC7H(evABmEAhKl;%6Rj20CYDyvso+#`_70pLx8OgU-r$ z9|VyY@AYHwd)Xqt$;+brZjkty$GZe{R>s>2Ix*fGC4OJWwL>?Jr|g}eyG$>a!An5o z-@k8yZlkLGUUlh&ZoobhT@fB`M7ybD(0M`UK{;6ReVIsO@vE2kiT=c*3rqaOYsFY} zdnJAos8OU?bPr4XGBmQ7bl;KqO&o*nRf*puiS8|2D>_bK5OmWeTwET*g&05OWn7H+ zyMQFWJMp1J z^n77Qu%k2F>95DtwJjRdaf$$jFx^@h;BaS4TVp^E)BDdjS7Y=OGbjr2mau zMe)WB6?NH9+ z#7m?fa&{G>oHDbgcKa@CU_0e?_Qst68PW=IsA6N1w z_kAN&*2Lyc;Q~L^$6@- ztDKm66@p>*UOebWPYyfFhXBtr`xOt-EgyWZ;kF!a)K4zkp=(KsNE89DU_^MnOf9ya1{~Qc)BY1N zQ}R&FYN)W;)P|l&wd2j|-09wxdW-AUl-Uktxw2VkNYv@zx88?!_2{SQp&P zKokw*;y5Z(ztC@cweC`1UkFAb6L2m*GTn6C!e>e4 z;<8Yu*b@M%R?Tm7jZ8T zzt7_%ujgApC)YzUPY3Z=&i^#%=v#vL@o!H+;+MXtxU{HHGaBN5BQ{3JEZ{lX-_nv2 zj+GTGDbvWuw=tT9MUND*F*=R9o}i79c8ImvQb99E>gdGT@!LE6TVZP<8BJ*BK_fEA zUP!Jnx~&mT&eV_0*4jzN?x+WXh)&$V$uDuyXn)A==vf0k!L)h1*h?s<3DlB{y&^6F z$*$;E20WGhLBi>4UBc-GoFU<42b3@2RKC)LZ!zK5 z=s4ZfQ_!FL40tL#0(>dT?!braetrR*NJs{Re{k%6BvY4oOn`9ad&CCFWYq&>A8oml zA&&7ZccY;Wo%J5)VeQ)*x74j`FDoc0EGV;T&olBgcKm#mhAmn6RD!=`RTF)0CecV% zK*R^XpF8pUxNZwR4aVwnQ7hRF*+;BvZyD%CgluDB+vV7HIksKSRep;He%p3A%SU}% zi8q?D_ZZtQr!`@_9@{QQ{ZGy851DM8jWoemRkB#RQ|#HT9Aisb6fUlx+> zNai77DN;SOGB@+k@UyVzNmb~8v}mTj)WyUouf*Ae@19Ra8J|h;0|ul!scmQ z%P%9FmOv?4wGj6%ud{boX`!zgZDjRp)+`qf{ix_uWX%%prh`AXXtpd)It&*_JYU`E z@v;3M4(`{F{e1TjUhMO<@(OXK!B20D;$*1e=4UoWjaNubX4RO38q6sDO1u$}Zsl>>N-= zx=t=XE-}i8CK^MmL_!uar*fiugDyf8{f2WN0>B z=)eLPAVHYYT;Ou`M$Fh*CK^HubviNh+d%iCL`SMuO2TwO;H#mJrGATqZt!HL`{*ci z7lB&tUn}SY4`L*)*O=(Spo=lw5mDA|0bM0AGNoqVvWofpdjDu#G*^`9M!6mzneOMH zD@PvD!SaPCqN~G49!Cx)Xt`Ew_-k&r9&{u>;wRPt@$1G1Yoi^2r!eTGtwdzAhj1nL z?+2hOKpycEb4mQ3G|~MHbd*nYd}9ENMW;dwF6anSBKUQD5m_+=4c_KX!4gJS=HpzTp&d>`5&U5C#cCcsxbc<8hq05C!?#s6GM&8 zOky!YqB}(F7$FyOfzqGYF+!p%)x`!Pw6vlz_tDM)Pi0dioYvwr;FLvuAYJ)cKrY8M zZaj`J0e&{Fvvu4DoOTgW{x8$5WAREcHE1dSYhr2`m#7pD16``4r|j*WkvJB}*@7q) zk*F0!B1NqrRJRbfwb!F)mTc{{t-ZGL+gi4Gu%k*O8q>m#DzQD@#b!s9NH`(~-as0C zF%t}JG4h3P;*4~yM&b-??X}rN#MWNh+G`Ou$&M-!eK<)%-(qX8SNZLz65Q%8iB+UO zx+KlP)?SZzl1W^qBOhjx;+3?O2Kr-qq)DnjMw`5(SQ*Xo5@!{)%u9%e{&rjv$Ht>d`tWG3&^Pimz}}wE%ks6Eggj7 z)K^d;rfqXwds|zxmb1Op-yGW78fdKZH}H55`T5+7O!%*a+FD1C%P^XK2DdSbMwQ@i zJkeaDQ6*46fv6H%tvI7fP$fy@057COJoJmCw9*;^zBgDgxMJRd z89lu8Zhy(4_Gc#stA{dO&7u5I$&AM+fAFEITwgmcsT$ho`eW$nNQttZO7L2n$3pPP zkq?w;9E3cSTh$(G?u^7yd$(SZbxl-Ndr8(OxYh_N9MWLYNvu2p(z|$4O&Qe3c#Y4s zRZ!hP(aH~2Bt4nR^N$HVk=&QAM7$^l~P+~v4MXr`f- z;$y`aP9?70OFe?wOU?6c$|$%`Vu|0QvIL zGq!?}75{rL)<{%ECAf`LVh2GNjuvxeC!s<)EsEX*ovgeR*EJxJ`}Zr*$+wZHzrjTJ zH_%-y3MJTxYgrlUgOZ)(MM_wakLerXe}5V1%5^#_r$o@)?q@(}#UK3_Qo9+PTWo&E zKu0n#C-XRpaC?byh;#}zdiV1iL?_=X&>mW&@K&s_W_gV?JuCi z?J**K5jjHcRQMj~Jb*MG+!_Xu+9f~p68&%ru5=#P&%Cfqb3C_jmc>7`6&2A=XHnPV z)=pdXFpuRguGhstjY$?Eoj!3tilcc0C%+<*lNb26B%B2P9SJ8*udzIp{m@YEHkG^C z>xS|)Q+XPD%TS(fDo;0fi92A`@t#CaRv!P5aF_?Ng6QD*Nx|~z5mf#)Q~94w_-V9m z^h93d`6j&5gv%jGh`v=XUx4c=kXMfZce6eN4zG57&(`SES(yRHg0DPpQ$s^TM}EiE z`JH$a?ATQAZ>eu<%SWt%*3M1Wv^3{8!f|L5e;u0N7z%Hy^yXKt-mqd_)ylQCm9+)= z-qjn|YsH&Jh6dXto(s9wo2$1rMINg7FK(kcoM+YXzoTo$wY6AkbREY@5L!OYe$XzK zii^Smb5sR#O&141;5kogwW4`z8+^5bEs`g9rMGfbMP=RUHr>iUYJ)Ov9lgf#b!(O` zS-PaIux?eLGuYNxm^_Q3_*vAgU0JzqiKTiNubGbK&0r9q4c=@Opye7(1GGG09}t;( zKE;;gJPPIb(v7d8B-61gnk6}cn&fAD@tf5r+RWQ_5VjpeysGJ_sv({?Mf|HK8p<*O zch$&Vl}uf}{Uyx6_Tsm__+!Oe6%SQBT&uj&MP%wk?-bjM-}d4kCxkVYn|-q!zf`*@Z-q1+8=HWwQlXG^M?abf2m0!HXPRuw$ z>zF4$ehUe$X5>|gJRGZ@{iFrisP}fk7OUDf~Eb!AOV_bfu3ZwSN z>mRAKOoB=i!OmtVpAT%2wJOP?sRHnN6FuAPE1_&RA=4^x9fX>@&fY1la zi4@rwMW-WqOUgd>GboD3GCPW_?~koXC@Jaohg-Fl03J1o*YH45EQ zy?=Ul*&Cn}eWyHez1&3iOVGtimm?G6#~rUFqT47C35IYjE96UNYPLBfC!xS6g}j+= zlSG%Q^NU5dQ=+4CO0npklITQ#V$r=W(FuDSqJzCa=~B%--DodR6gw_`X;E3RRd4n= z*awgz_5x`M*$Wt*gh%?Zo9qO5lky+=ZXnx$&!RAzH*oT4iI{8yDE3A)eK2*?qidy& z(jx7&tp>E+p-o}TDc1XuCt(?$AO4Q5&TsUL4!*(6$=T zRs)J#%2or8a!gJ1c_#6_##RH`YCvv07}KHJlW+0&R&uq;BFa_+R+5J_e?RbVqX1kO zkLvHAsUC~IOxFBWWn5g-3u#&FLu#dZQ7A#PTIn+=TZ<3X<-W9lq#ZM>m41)B@8Dxj zqy>q-3}@^yAn!q4W=?ZWbPqw*H{`-elogjG?Du$jLV64s2y_ZxFtaDvNUg?*<8()4;7z~9^L2?bnK-?VViKZ@ zWZ>jCrI{j)iM+5J@aFE5%1Imcx`dN=rR)t!-unLshUnk6hDYn8;27 zza^6AGMu67fOhpXboLRcd{(scs6WMUhAy4ad!bZLTDA%aC)MyJCcIw4NyXd=oU*9T z6bJZrASAO{I{pxF(gOU%y_y^MavAVgV&bPg_p%W1$I!4zw(W)*r90v_QM>=p< z^L`X3>*9P}ctjF$9Zubq)^cI7o^3jt7bvGT@rHk;QNvZH9nH%v8|qpDEe*}#66;6x ziZ8v9!G<*(lK6cKZJ)c?FZpbrJKN{Z_PMi9&K>6Pc%MX{0wYmo2_gU@5Sxd!?v=G`^<5xpu|-GcWR=5+w zxloT&HhP%jw)&<(LuZE^B_yK1`#|{K8HZ(65tskY@EV+xn{pGKlbezk>^kt)aPYwC zzR6vmY})Os7u1B+U03?l$JhE^ zu9>_)Bj?FWzV~^X;W~;=IOx&GrD-}W9RzZ zGbs9TMzDNnnJdur$KcaJJ^t|tC!!|rQYZp)MzDHtBTA*{$ULU~Y@axE+CoYqGY4vaT*b zu?pP_=^ICcQidLoyA(mkkwGk>3*jg6B9q5Xg)WY(3Zazbo@j9Q;a*iBg0~URjHlbO zHyf!+jG>j`w8T4!#^YhCxgb$*H2sS?v@!<9*KJ<>sX2OTV@6Ik75v- z71X2{+kp?&r4dkyrJ&vc$GIOpg?KM6WfMvTPu8eGf$y9so&iNKW1r}I7nx(y~8LYwj7 zH>Y0qchHesslT#+-}NTC2@vR7olewu12?yOCFrV=Z%*cR9|WCfS1hMk{0@Mw#>@=3 zncrU}e!@>S7Qa;NFjn}j2A$}iSbxN?8z0%Q;G>|6WmxbK=!Beb$-V|U46cj&+b^?l$JC5@|+n#}}79>S6G|GWyQvMnIr*EF45~upBlI_{Fp&d2*R79A>cdQQjNbzFn*u_%9`VwSnI}_7MYqHfsj{w%E!r zp6!P6e6|z#ajE=HL-|s6AMp33@<$EjE7@0pyZKiV4Zy_?8OkqVKQiE{?57e=79+oq zaI)wymb=++4drR3@-+4*LwUNXJl$}vJ;movi^!V#OW%2neOKq9qW_cz^zjP(m6DYh3s)t z`RgY9qzOMGvi7w4=j(VLcu_p@b_4EaUoqfmY{-D8vxOM@Tgc169FPUhdf>0&`s2KR zE_M}gnjX3bsr+8xtI#J}w}gLSEpRI98(QK!o*M==WPZbqXEbXWdBZG(J&kD(Ed-Uc z&lU-T9N6o~*}@* zJuW2rGPG{AJkn9?@!0F?wDX1} zOqdiSa8Ol?-xtDZMr*crB5rv_VjNfjdPnuZ_|1-_kZj7_0_FgL#=^2JxD*F z^3cbH*di8YMylnlAu*YwP^@VUbOhVRA-c33$07vm2oH9I2Rp(;OS@1`+YufTJG0)7 z@LK>@inxaPGoVTGoe`ccd|Is$7I#q45nrbhGvY+&L;Yl;B5z{`O>b0`Fy;FKu4VAH1hEBHMnzO23&2t~lMGp@3f_nitGw;v? z72EpVk1O3N_oWQDRacK=-;akq2iV@!{jU#ub|_UVeVLvkHN^8%IY)-x4R?8`_qlsS zUovy47PUqnwbwN?;LGk8IBGRMkaJ}4()AB|oxQFTnU}c+cBZEFQ(uYZQ#lWMUA?Zs zotG`~v9o+f)7jj9chB0RX=!Tjhk7z|mCa7H6bK7zc3EP4^1@H4Jz0~FeZpa6tzr8ny)TSGo z-flwf;j(8Z`k3c2v@ySdW&)#PM4jQ&<|SodCdZczzFVG=L#;S-fDCX5UsH~sk zQ}U+tt>Lq~V({Bs;?A6%$FC^)>cFEHWgJF7H?J8y&K#J7KS!jW<10B7T}#K;Ou|~) zb%4!vb{`1s^___|pw44?t-UYgWX|9A+L3`w)ivODX8A7hdH784=2Bd9TuGz8D#zR@ zDJQPG)H{?~f7fElSwk z>}BSW{nn`Fz}RV6QKwy9jb{ zvwglxn%HdTUPrg%J}2%O)>XXinb5o@lqs2>$7+-lJLyjGXD-3WO4vNyFCX&`&fSPM zox8oK_t9#e!&jk@+$&uA>0CBio@3j8(Hvd5v0CkQA4^S3<#*F7kejPFb#Ui~=Y8z# znxjrOyMHZTn>0UEGjk54Q~Uj4RzM?h_FR(f*#Aln%Uj!2Q#I`{30|8b4UbI@dbbT2=oK zTmeELlLJSY%C!HyNTI)F{BJq^b(T9=IYh|+a|*38st|^Jo@uV87|R7iGGVZ4s7tgW zk!gZ2mZ5HCR{g4SroQ&Vd!hsvVfeuEyu>W8%Dnf##U^c-E zU?M^g^kjKU=DueVyhuC1gMshagrnX$1dA9ummths`62+{LLEmDug7i7P+ms(`Me3< zDUfp9M-Y6M69nIj38L~Uf>Rk=O%TNE2!i=~g2=y=Ao_I$LF8Xa5c!)3q8&d$>UbML)axV&;cO>}axxuZkmDx^BL6yqpu3SE@^2yt;oVFS^t*L@ z4?)n8Tost4z*NvVNl`NmYBqj7J|_f9rj*i z3asMpiH9lCibRG-zO1W9&O~KaSpB+ww_`}W9o&s^2tI?)^W)R<-0129zjkSj5sf{(j|pPeAe!iOB9v%U>6rw_xO9Tx%<){oJfn0j=vj>(PFjr zF=9i|#`uYG?-_H0(mfN$Za0Zb^!D*3I?c5HB#Fk|+`jR}IYx7du0Ohcv~M+hJ@Fj@ zjaXg{PFjEITv}gDN?MjzgX?vy2JMFZ$hg~sSzgliV0nlx8lu)99&^U~LOR7Q{xGQ) z6A|k6ac?p65T#ozjvZcGG}n(SP&_1`f*oFK?f;H1%~RRjXO(efX>LxEWuiAU`Dtl4 zG=7Yg0HFgEh6~NQdO#L-csH!RdDbrWY}G8^QUE?InnM zj}XMK^e+*_uk>dKqTLq>E&zYM-0c7k`l$p#pGOe%3kZU~lpyHC1kug`Kx+SMfYjgr zpnUX~{D>&OU(de~z7^CTFG29Xm>~Gq5`?@iBMAPj1i`qY;1Mycv1tKzV~0 z$YlA)v`#qJM5ml-&0F_u(9K2LB8k3pu_II9E71U!SR{$An&~<$(%oy3?z^MVVVN4_ zatw6NNbjQ8YfN z1KopI3nWi0Q=W*f8y{LCBJIL{N1L-bndu$^o!3kR{9%0LcK;9Ps2ysT`bjBPyT?FR zqZJ$en)wywY3qRa(Hf={i{BNXv%>EoiJw^3#Lqk*-v=GGo)O7BAFlb)`M@&(PqFx& z2D<7I+(vp&Un%j!SLLYuwt>#ddik!zkM3-6BIe_wG5S{l zIxGBcm-tnT!S5@evohX)Nc<|t;5Qe~|5o;wCeVrTitoc%^4kkKE9>v)5u1?(24P0BJuk=uJN0sUC&~_2VJc1x0gU5%kM&L zQsOz*CGqPs(fta)7lm9>$DngzlM-|^50nU+`7M;_M1Nw@T_(|`b8Z^Hw{R^#XMYlO z8G5-4jsX$;DgQRmtp%j@ayexnQM-sHQ=&zO;UQu?g{4bNN{b4LOBat4O=fZFViX~b zA5EqX_YhJ_3G)Et;W-sOx1-6BO!Oqrq>~Mtd=UB3yn&Nn6NG>iP3DjRPiH@paC&F( z3h*wPVxC;=KgA^=osVi%j_32I3Z2HO1lZ(xab`JcevvYwzCearg z%4adJ0r&9pa(*BAdFx`A8_LgOLEv(ITFJ%8^z;Patgwwm4KT9}8n>i`r+Wp4Z{kptF z^prD8k zP5475oZdK6%EO1Exx5LSqT%F0P84nBec%)^hAb-xpM|wYBBV7CcDacF#TOfnFtF{E{g7AF| zg!KcSJ{U1sngfW$s9V#IAEqT@a9`29wJjX#47OASIvT>E_Rh9&UFE8ZO2JA$da+K# z2tiTZcyUCCW~?Y8R6b4&5hAf8i1<4KBZCwR?|%E(D*M=~cwKLzCqu;V?yl`EbOw8( zb+PFrQ&)2~PqcA6f`}bKB(C@d;(YZ)7u@=A>()eZt*uWjOdjE=Sm@`-xc#?L@^v5mi?wiibZbx4!} zA_6W-$TwJPpFe>lS>KKzq6a;&kFAP6oFuWP==mgx>hy?`T=k?Ew0&&VHI@9V%_Qc* zjv%7#(Bc^;2~qOLn8fRkc#=tqmFZz7DPH!mRraw}9f(aDGlB=6sBl`5#a~P@IsAXB zO@TG+W2;QZR#E8dg$OkI?{i`mACcAQA^Gq8W6flWO`#wnfifX@>w&64HP3aI`#$$R zL=f3NH*KzxHpAI{ZP4et{kHG^WrE{LZ*?D{G2DN1Fh7`mM#{099gh1`?s{yqSK~ev3Q~7a)4cFg(r*iJxzVdh3+Tr?c-_-lrf{S~dJ=xDw zxr%c29_8*I53{b@L+MR>nuaM324X~{*6*$&Pk*1U3(-SdLw~;PAjKjnxW8XL*L~On zZvPpHU*Q|P`D3s4^B4gXU7~@<2w2zSbtCG?;;9seKt1M4quQVBzw}^cZXSrI+1BUWkMYb&L+l6Ym2%9L?tCDn$GPu61~Og6KE#$t zQ)chTUB>y{Ru!I=g~$(S0}7APG2EmaOLw8w^R#g~_oeK=CWz5?6EDO);PF(%Xhly_ zd0d8PJYP8Gc2RtfDbaCl=UxU6B!fD(5+G8seQy zL%fq4(TOE%F2$QGp_`3D%hF3H%~l>_$I+M$4?fr1x`deN%!G| zpZsZumk(7oR1T(A9vM^|Trvk)E^)oFR6Xi;Qy+55mk(XXu9{9g-jTE8_!R{Q5O3t5 zFB)-#+GS@gr}gG==`k=w^ouke<-z&<8$OLIqBiJJQHGn^YeY;G5dkH3M3kDLZ$~1c zu-U=j(RwA9qTTE&(PE-_2NmU=`V~X%JaR|8F;U*douUMHA|{HX`?(M#nLf)$Gx&L5 z=JQp98}nB5&&bX^_r0Gx_fd3|R305gi;Yq<v1Y*_Ql7A z)v6YP_G5^kk~R_Zjujf>Yi01#%Xe2Tt4{4*F}R$^)OpOe46!$M@|YY{vaIiKP2UO~ z^4Gd+*&_p)>~HnAOwpn_n>p* z3%)nd({#27yTMg67UXF6*k=wp_dORX^5s@RS`Lzyr)uaK>cw-R-BqR8-}YAwws}}T z^AL~6jxlBB(C2w98+VmhTYJFSiHIPMCYpz}d|f&8brp@P^8Oz(b0KpcB}6}*FLmbu z?02bU!AZVupQGz|)4kYNGV|yjJzjqxl$rOTS9c(?h+Cbq{y=DQ-lSKL3`|x_vgyut z4y5rrd-Y&byO>ig_K4d3Oo*b7u)7p}&u%>mC|(zu=pt%_z@@l&;uawYJ*X zyJ~Q$m#8Kq8j&8) zhneSgU&-u}+yb7ndgwn2Zm)V}=>7JMRm+B&YRhqrJ+SJg<5v_tgZuJE-(#BW8mSGB z&$0i*!R3)72DMl;yav``dktn8F=Wt39)CrfU#dqjSQyf$Yw0iCj5x;FJz)*Md8-D+ zU&J7BEmN84KSd^4#v_wxf3+winLK2PGZOYhk5r-omz=F#6Bn&!jK79pD59KH`*LK4 zu^iFoiy;7#ir<^HeWW{mO;)Sp0%e>qC$MtkW)5hbTRoklTSdV%crrBtYhkiyV6bN8 z*7>mVghw5(bUH!Q=iUnG(QqfTDIfS8g1R*uxkm6#7jafFpW^@dK|cjL9k+f(KgtM4 zKe%-$+J^%Yuf(k}GZ`x<9DKR8BKqkg9G&E|U8sjW0iQLLkMdfA;BzTKSPgS4H;m^> z!qJaS1gA0f5rW`buj35_!7oS}M5kz?>!E8Ou3ChU^gZlpoJ^wm_pu3SE z@^2zIT@P~t`rSIdhal*{iYc(wfX&$lBg}~wkK%sEq^Tnp8FiEF2x$?i_%n%MsvhP9 zi-Q(HoMBG1=3YpuIZVIdX0jTPAOrPAggL21rj^hgFrd=B8Is30`(V=5YGlgOundHHM(U zbnsDNr!tFVET(WLizKqH8YL!3n07gJvfc&;7RREBgcumj|6a%mo1Bekw=*ehaweY(3He#__IB_cxucGzE0% z|7L=77;7Xrm$7RIqP^P)&SUH|1X2G*f@tq&1o0bU8YY6;;WqbZXCd%e=r1L;NV8a1 zvAy8ii>X*-^h~efao7;a0J7uH&KNu2@X$AKjUFTpp8N+A9;Z1cH$g17G=lg-0jVLB zK?dPieC9;kT&#pSrbqWkB08%f4G6H zAU~Yx1(*-XsRIV@_@#-tACVwmPRHei>(kFbNDzSl=W+&wCl99+_?2_C?|o$R#O04G z`k^WJ?`F`6G9nb$YfN;vg6>m9U`l4!tq);f!j(uSZ3e>UR?ln&9bZ7e`CJ3i8n_-G zneLOIdk`I_afy7Q>&8bO$1DgBA{>#-bmxK2JA!ItXo2fMN9|C%cxvV;R=YbvSEHB9 z;9(%5zm)$&(B%OVKN>fsSp5ECk>7c^F$F)`r700V^L*5U?gCzF{9~Sv&w)^j+26R^DmqIQG`QertmER)JS&`q( z5+rDZfh4S()D*pcC_pXA+)b$*&7^KD}H9=KJ?&Qvc{#fl@4f z?_1u1{=)`!-B!1@g@;vCQjQ6C}zw^f6cQzg*t?+9Bofz-= z5Xc*BD%Nmk)JpI2D*t+?U!_h<{Lupeh;Z)wv?$mubXql+{OAO%A%^NuRc$5?i$;A#B@N{-q!s(aGcYwbf zVc=pvkjlw>`scuZCYAr%P(GO*2mV{BeArM9f7eJEE$mbt4=_rS%1$$syV=wI;HxB@$~#T?9uxkE3IDbUe?`ahz>B)*I!Uk4XM?R$;*LHLUS~}*=ZE0)V-W<@p zV2!S_aB`j7sk_G-U2n;4m3z&?^;U9&Efk)(CO&Y?J=I>VutD>O163`4?ispfduRLh z&WgsyFnm{ZKT-^~j*q&c`W}bYIRk$_tKgR3O)H%b+zlO>-g2` z#;>Q(+$|GLI) z;~QVo#+LBCw#wfbOuRDRV-v2v*5B9|O5FL8JAWkV(q^A|pRkW-v+c3ENIIv|_E^R9 zS3N)7liVaU$>48G;$Fm>uk6}wiEnH4_>s8RPqXc@x*g7Sm7(@vAe^+LqV2J2d#v&^ z>-mF95_ctkR!OG5_PCM+2l2#`3=8aP$yBFk5lPgq^|v;*wIt6W>0P0=!=FqqY>(BE zU%LFI5gtcukJa&iH1U`i>spEvTZ8)JO%nHEBqm3kJmUGi6Vu<+_E@cJ>}ZG2XP~t) z$N900zheftHiZLM_K8Qk7d4~REngtoTTfeJ4ko9o)!+M2bT?XCXi(AL&K zW1YW&g6|+#3-H$-38LfCo{C#T;rM>b(_^&x1u)ptYfdfD&*+TX>YEV2r$hdI(#*eh zJ^9TQ2~}%Lpq8og*8NeBuep)@xY$e|JhYetXOK_yIq&*>+9Stq&T{Ofv$@O8C4Wlt z_*!uIy8}BM-yJA-sCS*7qs&p@hpCiR!R&UFC$DiRF{akG{avVfB1<*m0dY?92!S zy@Q_9zw6t5r;?Y|x6CI_nuqThd72LGcHq4AjXm(R^bOq|rZzsCa}my0S9%ZUe7Ilj zd26_=%WrIqc<45@y@EDYq`&$GC%t;oBQpY z(iykroYo)lZ-v)t#o&=;wW8GSW3E)q8}yuhI+c8KuSfS$B@aE}Y3fA( z*jeNi`l0^GJszBLPi<>lsMfT@zM=Cy%tP&$PS<#%{$`ArPV0`GWWLmNiaB`&5>4gc z&nvk17{`2rU+}|U%#*!YlvfSqU!r-C{ajaXe_;!>GD!KWG}r`7138fgS!~}g*b~D8 zO#CH9kX7F={H4^VZn}(={t>vT2NGT)b_nk3@Jcp9z z1(h=Ah5jbWixhOcUlVj*80$aPlo#4Zl1l+#6<|6h;4&RPMGzD7Ez(Eh12ypb5mcc;e9Q?0!|fGKCFuA& zkd8T#os>*>1|)EnnFx5HPRH*UTvvjQj)@aVbir&xx)iqvtu~RI`o%?nQg!ABohTy` zalOVw7clW7T1sXckvl=RQ7bb1Z3ZUWR{Rchd<7t1Oe?L7>rHegK-Z2u8mFjFbmn#g z*b2@^zB!rOeF$`-U10+fi{C+u{Qe~I+2Sqd|mNQ#_KFq-X5L6J^AzU|B(=8)rg%VCTK_zg?qCS!x%4I-q#WmI}$AiEx!8P^@j$Z@31=sYgLi8Uf zI~CvdRvtPuE^C#gQDYTYr$|e!Py}Z;*{}eOWy1p7730EQ!sa%@XvSj9b#5C%nhRKc z$;KXALam{WpqzsYgF%V@iwp+Ywk-$g?4v3m?MI+(%VFDc*tQ(;z5j{l9iOId)$TRh zmcyd?n=CY4A(E)fwd$HSBw-#tCBdY=*cPx@xUEPrm6|m)z+_V%VEXD;eTE9ac*~EvgMFo zlKxM%=!g!%s$IwMv#=IOfkj8kg5c99rd~hG*K=?8-5Z*!2D2yqBc$$ibnoByrDIN~ z(!FoL`Z(KLb0d*yC!WZ<{`jG?XD0+vcixpvn}RDgPY*7b z(NzP=6R&=(1Z5e)K+_+CPX}K-ad*{Ylt1|Bv|L}wp>~v152|McnwmrTp^_QA>_p~z z=RmH~eh6>W87v6Yey0OLjkJKVnGVWQq96}MR?P}L#8FT5e!n8?<2zG!Id5^?s(wnT z$$I;fby=S%K)wpiBq?!Kt{KJ!An621TSiJ;(%oke#Or>p*n=X0l(wXG;`&!0qz@o% zBUckau@Fx`xhVqGMYR}&^lAT(y>9`Gsyg#O_s(Qy@*o5PnjqpN zL=8&F*=FH6`nTJ~J-UBn={m%K$cg{WM+&ee-_kG{t zXN)t5r>ERVg1U)B2ni{*-fX!AK)s-8WL)uqWBifO7Ft9y zV*I1Xb7Sq$N}^6t!YUdQCkhrc?4S4=<07FiBgRib!cNA3@qZ^LHjMv2A@@M2H4Q^0 zR$%<1=rgdUz*P}S;&>Ty*l6x3(SPFdn=t`nQ`o4mXJipIEPLz|3 zNRQ({*7qaGIgv;6A(kuY114WtQV~MrozBTH`HIR#F~_s`Uo?soif1vMy8eFvlm8-4 zIy^~3r@qFALHi<1{u>c|DtlJqX*!<+Um41?v7d&HX)$H6-$w9u_D6{)O#ROiPnf#Y z8N_}7E*|b2=PM z2?6+|Aa%TFtB&0IG=v-&1H4!BKg#H}tF+(v`W<>L&A|cnf)hu3 zXzK9$y8QGUPMSoM6jXz3silw+CVFpl;MAtaMDI=X-bC+B^xog<_jUS<$9uKCVCHl^RVY)g2OTPRd?cwBHwc-t|#&(cY=DtZ@A-EpugUZzoOyYcA^T* zNDO)$g=7#06TLUldjUGH*8ZAF%ASNn6GrD_elD3LmjZ4C3|bM-{r) z`yVTAPx~$dxmT>-!nuX{!0-7U*!?Za$$P8*qa?r4Iy7Iszj0;*VgfX?e0cm@J=l}D z{2A=CTa9|Q42t4lE5WYGGrgAm|I(5N#NSisF1Ekwo_mp3+k<;gO{F)#kL9a(s9#O< zDhH@N_Jxb7CU1>mEF2x)+(bJPPr+WfZ#PnW1=^8zUk!6on^j(RuCuzJ&*?mhSP-+Y zOK)Kf#eBH81-mHQ?ZXc&a~D$71IVfekMMnk^B8tkeq`N}Su2LGT6-hkvziUqQ`z~; z`c<~VYq_g5@Oh8I_t@rp;eH11`ZZGkZC6^C%0mAOQ5369fDDTho)8I(TgNd307}78 zFyPIA<2gg<7SIUIAOOHWN9AB0zzqW+$30V#8Bga5NT;3%-0)=Y+-<+vc1y~w);*RU zZnV&)UY&it3uST~fe*@GAH%_l0bde=>B1L*Gif+C@`f%3^zEU1&;~ufi}C@VevXh|GTqa?5o&evROmsIlE2 zK<*0U8&fkfgnlZ^#lVYpv7~q+eLeVK3W8b=wpxbVM!`tbh)-b*pt4m;3Ew` z`!(dm*h=cy<6z|ey(aaK`bmlO5%OJD84dX^kG_*bg{vGTlqUB^|0EU*QV98;LS2s= z`Ih!lsNcTXUmx)Mn*AMP{n4X&m+N(TH{>sQ2+4o^3n&cd4W0U`BurTKHzl4Xs&>iH5;$ciZ_k5>D(m#O5s}+5Ng{gZB$^~w}AW1j1NU?bGQg@+6&6y z>n*k#Ft~A7k{h=U6%%e74Nx`&=#M56LXMMn^p-j^F-XmuG9uW^t4iyEe%CKuwcd0Y z9}_iL8(R}}HbG|-bT&a}6LcOQaHr_G@w|ZIKh`>iB3{@gTHkaTH(kaj*_gxxotydN zZ!(y#=`yZ84lZp<%E@-=PT$sGt3R2UAS2ae>nFV&u(Me*eE@2lWc8%azyzJKr-tb= zu3gn;_40)xgDFJ^WO#N%zt+mz`ppSxdDLI z{a7JqdSQO4jtKp0HF1nRxKg8Yw`){2t+=D+$>b4x}rJivk{1V z8ZwXZv*T()Uo;eQb_*2!?~G7!=zz{!miyQwK%@X1KM6TPH$)O3m;fw=+yjs!)I%g8 zw-_06yDvgcl##4BUSW_s4!LOQSBtcB4dHj`G-4kXeus05O!90IX4i}2aNf|VuS?>D*?n8$ z3A3Zf4PsV_|GrdC7+$2j-5_r__@6r1Yf^ohi$0wv_?Iv@tKK<{Kg}>V{E>LY^+Epx zA($oDtt1Zc4T|eYv*e9Qf6hhta*iWYzuni-;%jX6ukyET=?a*zmkE1?wh7h#7L>gk z5`8JnHVqL27aOkYdwcQ6!3Fu^%#HGM5jUrQb2H(@XCoMysa$-@Dy=C0S(t@6`LoQ`6$?Trb0 znXp%!wvBi|iVPx=#PTzDy^dw@qXK6!$9GAtHr*`DNXfAD55LO%s3KpXGl&)Zf(IgV z>aUyWSWX`#fF-vR58!l-Tv0zZ0#0`$|3!QVaH29w(Euk3!&n-A@2?5s+Xy(_3q<9u z7yzdOXHM+-CV-^xK#pGJizJ`~BjEIdapa7E(=o^i9i&qnufVZM)M!jd**M|-Hx>0Z0_)FX=&Ts9##~}88cJzR1#`+2PDFI zL#H0ndH5Lu1GKRpgVItaXIA3h02PT)Ejg;G1umlRi9$|oOo4LJr6n6n4L62MYYNK& zUnq*9&lyoZm64~}r$c!*RuMX;OLH3Yf+x&Z=wA~$rt)m|58&Y&9V+)nl+R>4Blt7e zZ4tba9Rfcn)xSTYJfA%t!P}+2P?L7Pb+u^S0#xppB(EW+j1B1eX?%}M<>Wa0dx;D!ZQ$n{_$3B@oq=!Ed76`H=>Kl;-$k3`1WZw6?*~5*Wwhff@&5{b z2%nwEBmUPoz7b_)wm|%8<=Kb(O%wK3rRcDo*LQaLw{{j3Y;AAe)+$1*>K+F5zSh?E zCPZM}(B9G9S!8+^JmpODzx;g2Zgo4aB&SLtp5JB zZT`+c`#6PH2H~U1Rhm(G&8WOhvagN)b~icT&_s$8i&bhO#c?C1x+Qj^aE^HIns9w= zPnU3Aif)%^Wphv6gvSnV`>NM=m`E|br!(xtY9htLVML1uOs+(UUZEyZY$C-bQY<5L zCQ@u7#qiJ6A6=5b*i582y6re z%x#-UadoSJzdo|wkp$i0Rr-4V8huquV~4NfdRBu2WHz_9G}dqTcXYP2x3NV`_3jH~ z2U2tPH&_O`*~@{0p2{P+-eV2HWj6)(ddiQmymhm7fh&4*uoh8t)4M5#Zu)OW8N2oH z6t8XHyuhAo)PUP-z2iVjOF%uK-o3ZQa>vN*jBCE-DDhInTsyNJs~sL>h?L8!Mpmx7 zzEAD797OEgYY>6=nyQh@Q}=kXUSiIahg0?```MQ)cUlkTd)>TlPt7Xt+NFz+Ih~F^ zi#N@i=dBFoTYA+)EN}X(Y;R=_wWHpdk-OMC%bRlY$3fy#hBDYg4cMvokfLkL$X&ZM z`xtY+HtN`C?OVKQ*We;$@fGgb%a@M6{BU5U_aaFyjmPP=4l7rj@1@?e0_y*)KGJOI zrF@G1yK5=M|2;n<{%^soH6y86&4~Z|UeKP)3Tl9GE%v@Pn$wL@bM9NJMF6%Re&&tA z+q0hR36MtR7V`=-H7>Mk7hdQQH4U%-0u#~oqWna9|j_XR`?R6FC? zeStdf#d@0;1=yXda}RkON0u*5*Wx6fWLKsP71;R&jE9;XxJ!<+o!#0B8f)lD#mBmQ z>9k|j-cs*6J)ZP0&{xN?^gGiI$vL(c?Zdk_EcQ}_XDdtZ^Ny6FSEqu{YP~w2dPT9H zpLyfmTY0{MI4Se(rOze6 zQIq50s)1VP5RVZd0GpkoZNAK$`rf;Fnv*ljXAD)jGHyL^K4TXW@6;W2fqWMcUjRD~ zqA&9Ov$ z+=eLI%d>;(J=r^WJ205x?O<-=X@{J-MIr#XD*MyB#U|O9W3Cc&9*;`7>x5yC)AbJZ zpY*OHP&aP}V@AtIA^RU(@0p64F$H+IU9qcni#>y;T2Y(|o1#uV^&V5}Txwm3T34#p zm8o^*YTZJ$ZjoA7q1IKZb&D-^B`$nQ@F~To44-ns#+iy0TTPl$@TDztouaE+5(mfU z*qBYVz@FkSN@mvB;pfsAZ>|<=jOJX0#Q>PT_e9CnApk?Kfuq&qSknfxZjXGuE^H@{M_ zvTPdKJuFVy4G&5VQ3q0I@S|SRNtYt{IW|_<~u2kKFE3$cZwN700y(xfPJRiUbU) z9=xpYE0DXyAVX{`KCH9W57AdsOC6J4D z9sLM$@_P9^qrEmNOR#f>NRwG&SC*BOYO<4CVmt85j})@RK7+a*cdQ;VQRJqKk_n<_ z+Su9UYr1w@C-#SkFkp<)0(*ShYBIwPSx+zMfTeXr4nHaROP-KecJ833A(1SYrlW%4 zREq+%Jd|f+KM5VvqRU{v0lzntXJfC2j;TD84T1l8D9^_J8ak%(EIglvGbqYXuEf)F zGw$?JB$ZD?)g=;-KVH~+@RUV;CVStlU{>JRqw_a|{{@b}sq4wVugvgS06)c%suMBo|M3k(;t~D)fTdwkVw0Fui)(2WPcfn3^ zTkE!n{3|+qEv=ynrh%(z;A$GUhOC;*P)Lbc=9;09R%rK;c%m8c?VA%dpEC_yO#@ds ze76}2$@oJK>x8ZCZ3)|_nxT+ji)QWsqWP_vJAm+5M&y8#xD8#aY2a!axS9s8vdK5! z$Sm5Tu+QhMLW9p7}9ed&EF8o&n3x=a7~s@of{LF=6ne$!m5v#7Nyp=#|3)Ed+M zSj}7=7Y;tTa+q0vFsxel9C6I`x3crn`qqqmM^E=LRcERYej0S7p;kUa7t+^Sf?H>94x-71N>hHg%WHc))JHYa*2D_`O zPL$=HWnG85h2N>0{lvh5+R>NSDk**Y-oAH`G_V0r7Rz%Ff4VHUnv8MZt%9MW17?nn zS4UYE&dg@_D*IE?pxNdMe9!*w@fPps6Q`cgjZ16T!NC?!c~9yK%sp$cG1$uPbd8?r zbdAnrmcb>K8Rt84s{2`WMdNg9N8>jdg8}!Tg9RJ*Kkf>R!%*WqYgK=WuV(l%2AW5j zGjhGd2O3x(b6QVYuTT!%TaMni3T8bp^7|{8GtYZSH^77el&+WT>~_bCs4o}6gWi#_-s0W2cRT_ z@*TRVB8(*nJ0Yt84p`%h1HQ=Q1{p94;eaU6$9Os{z;9Ab_)E29J_jI?>_f=9G9Hz@ z+oTVPAR8AxD!@gq3#Sv0E`DmH2#MezPxj8;wwqIKvEFLgBSsXqDqJ;2=7X|VdI?Pz z!;XRMkX)dnplKNSI!s*}M*Ie%m;v362L}Mo=s%xSOgW!N*!A%FBO)j2eY8aDLM#(1 zC%Nb7z>qKi9H zkil=dplH0PUm_ptmTi-G9I`CPZ3HDbDyKx$*lqxF)x0$F%h>K$rFO+d6iwfEAs5Y< z$f)lxl0LBxqUp24GGk?A*Ena?R|h#UE<`Djz8-wAM1sUqYJ?n(i!mKUh8RyOdm3_u zpfrABZIHgN;3LoP>yQ)WC<>*=aU|<|19DE}k-i!DP$GTBWs6<$*eq0(mMxCeX5mb% zDWs6iLMHY6^tV~yotD4k@qWK-5`=!T88|K&PVMX!iKpMSHzb~H2HuuBkjm#t zJe5}(_{+gl*8TYWO=F7D)2PvAU`-9;RgD`~jHCV0YzC5n`zL|+d5`M7+k!f-FRTL$ zY*>Kn=MAIuI(^LR@Wk~P z-i0TwD7gS^I3p9-H-Y_#H>p)H_|)Q0CXV))z`h7Qg?$&37)EoCBXf@YI_PLWaa9un(Zn_`}Vwl(COAiLW^5irl#|DOKhkM{TkHk!S+@ zB|yWmp}?hx<_%AvqSa+(3xLvp#DIPMrRPT#*w?xrE3l6!NCbta018i;7r5oH^0k!x z?DOhe^%2G)YW1s|_OSd}yB-*F*d86tXiy6XEPr$~)1BcZu-q}%J*?!t)p&GR&8rzs zWg4ta;JWqX^e**$g4k2?v=~Mixi>O*@n2pJgW^hWusP-61%dq@+p$$6^)8A@gkTI# zg-0o}QH-ZucrQ-Cx7DSx(0>ABVnw?1Nr9f|CA%m41{s<4W_PK}vTtyqM78PwEifXU zK>6ExU{V~`0Y<}N900f+_QDr1R*rjrP=GGF#EQ`?XM+@_9==^F>uue zP#0)`^5GcYOOz@ZQalju1BSZ98X??QkvE7B4Vh>z3&#Z4i($kedmaP1i4P`m;RNJQ z8)H4I0F`2aaHr+O2H{pfj%HmXRX;F7xW9%RjkQSP*a+di201!EV=_Xi{|mV~qY(IJ zd}Jta2_R%3Hw-$0PT~3TM(H?v-WI+&~ZiL)M!AR5yX}$tEH_EA90a=nh z_)RY^jfO#%yQ1%4wWz#uQLGr`56?sk5(b%;5C%z)O!e)Jo40k+E;h~eo3{n)JN;X> z`rBe~r#3i8^Zv+R@)9L@k;W~YH+1STNtm{X`kBPjNWLWT1SkHN#FN3y|LD9EbQ+C( z^+lVSnwmO`I(HOx!HTVOQ=@NdV|#lMoWI+;HtpQnT7->Pe4F@lV^MQU$EIpeQT3V) zm#?o`xwfvl&Q;`Dv+)Y8c+=RIxtqizCr9@9d%;a%Be1A&U%mIrwc|s66Ab<$xb-g3 z_Un;6+PSlDxXJo3fM@#IM*U*|@1cCn3A^Zo--IRjewM!mOSEovOEBQ?NVxM_b#o&b zZC#ALnv2ENY}|x_V|mGqo4JvUxsgnpZ+-LR_WmLod!jc9ITU-sIy!v`-(~b&?h>wV z!f`V8GWOk7f^$0N#Z}^ZBHvmis7Kq*W&PH&1Qv?vXKTW7ojRPxceYFXC2XtdXKVV| z>WCtokdjzPy4gh%8caA&Y(#@eGrM3KNbS@2{z`k2Hx7^O&caq*O&d z*d(qh{A`nu4*l^ap}N|upim@{ICaGHEN8-Te?M@X_EPdA4axCSh!vL0Vr4TIt#dOK z@1EW8+_BKhdc3Q5!*$Y1@9dGPF2R=`^Sl&?al|~IuMqA6Hw~r`P$Ne?m;F~zgcJ{C zbfZ=!;@b!reFLT4_z*k<&rO~P0x?2HWjObD^>UdQA){i9$4TKvB?%VbIQ;4!drSa* zI8Q1Uhr;VmA69lb{xqLm}fhD%npw+CJ07nMxxxW@HF)LwtxHeZLo*>q-$ zZc1mOXYI}Y&IDdrYR~2TWmP;6*^;XXe^Zrk-JQOz!B&659XFlXVz*P2=gf>!YeuP! z%L!1tc}ny`H_yNRCtU7%= za;9}ZR@6*)X0z?_!tKmf5^`s=hTPd${uD2q)7YbfDr*-AiXJtnGi^ zUVEauz}jzT%??DbeR1{hZ``yc{nFg?Jt@birdG?^7d|GJx7E4LjyI0MHBNz3oZ`@< zzK$GIdY3n+94ZSu_4b~@L!Q)QEAy0h*pOd?PkgcZ6zK~fgQwyZU-f~ZxMykpA)4sq>Yq82mvG@ zR2xw`2&Z^}*XP33LPtj6brdBo06)|oogXE1Z4B^Qh>m>&a>ir?UVjTkvH0pe4_`PM zKVvFE1~r5A!qcB1*QXy75rAw3j^*zB9KLG;Y$Z8yZ1mN8335?z;W1%P{|9n)q{xr} zvV?r{sHhS^JdGFiYa(C0<&bmha^zD-iRcD=CtnbT^6XQaZ66qsf!bQ=L z>v4SvD_t?iGyM)03sNYaX$EyYZsd9bcQ)g$m1DPN{jhxrBYh3+-0zkT0=_I5@yK!q z%akUQwqrd<;%Nr+b)K#f@(a@X2eo6VktL@3BMFga4C&_ zBbvCP$k<+q>xuLvNKjAMjUavnCdg}oyaM7hT_jDAm%BJ}YqTVQ5fkLCZspG{NsOTx zu{8AehUp?{x=5BKX6~Rr-Xw7ynl6&D1VCzO^>+Z=>;!G=au#7<(AvNa$k^fQXlrTP z(pe8@iF$uWM|%ft1&Xajx72rT3u0M!c3!&HU$W@$2ju-|yGVv#=f(>5Vn5HHo?#~- zLSfx`z%qbFWwF=l4*o+ovsm!znp`D$-hDrqY1Q(C9KALFD7#Pgq5n8F9*q+uDvEai zL(r+e!6zA!j3}NBiehn}d zOWzl9QsK!OI`uVvn%WnI(IlT>kqD}KRxq5}B6brcf68A*l-t>>5+k(i-rvnq)`XJN(IYQe^Xbd9I&O8o0vF@TB{PO z)}BBu?Jh07FI^BTLM+p;VLKjM6!WYMQjyl zr>z1%gO~B#KeAF~+W$gi#OfGXK(+Nmuk}6I*YCF9Y`Z1pR_h*1kNP=fS$2oIHT!xO z%EsL(5FUTrqYBP4+(Qa(cHCnt6L{lgsHlf)CC|P%!nMw^&d08ZdcanKE98K!gmcL| z1QJF^o`zRYK3o7dfzr-^4U~_5+(G&1R4?U&-c39_8vmJi(5FF3?th4q8rpfc4J&1K=(7!LMT$n2s<49SRRejJMaJi{OamgZNkzC34Q zJd@8O>a;L|ux||qiqCNOv$buj|y#u+8f|2M!91H!Fy&h0y11PmC#)|Z%6_>k8 zuvuUz34C;XufNg?O?dKnwLigRAcgSJkATg%m zj4Zdap@?#aq1?fyh8x4Yrs57MRRBL%=jS7vy#6lIdAek#p}o2Y9y5A6dHo4s@U(UN z6CF$h=rq0kOm9Ea+b?8&YkK>c-hPw*VJyKOZ(H5zx_+FGTv!b zukG-!)&3N3Pk8TG=rKe=OT0sR2(-i%to3#HwytRF@^9&A>AF5q=xfaDzQj8e`K~WP zJ>eI9@hi~Z^2J|KTVWwv_(T;fZA}UQBoH#0_v0pr8ID)jYI^&b-hQUHpYVN6AdF+g zGfzj`mSpZsrng_{?+p{gG(k+$+i$yXf?eQ~gCUcvO?N#L#0-I$A8mI(@tPFxabpED zv)EY&9(KEdq5*9H_K;%f{s%?1SmEbqu_=u5E!`I=3T=;=#a>u=_{{=t5Ya=iK?Yxb+*?Snbzr=u>os7{B@GL+zgfWOD@URkOP5^Xpz&Y z;a}SKqVjSMZ!IpV&<>oF<6L*2!&?mDTxZcK#vR>~9K9wFW7!Pfp)K{B@yf!__*RNz zGO&f-g3c~q)3w_=eOn+zd{m)`Ohb4~t~%7C1!!+eOWWpltx3`t${91*^7LBS(5Wv& zBAhpLD$;w<#vyE>gdniz1;eSfTjOX*fe~`c;Lx|IVgXqDSHXZ<*i7aK)g|7}awT5u zY5G?^PsQzOwp2bHI*KHo;QS>LPvsvs@Yfi4MIh}|C)jSu7Uprc*>$NIPJU_ z>-^2zn*8{ISi0Tc7QYjt*agzCMoUV^EZdUEy&_9XjF(CUh4iei=PSRyDR6E5W?xHd zM8+2E#TXIwllFmJ)!yW5y)xL<5wRoW8j1%h`#5rscR6Eypk;Fx&U;(ywoWJo)7^tW`$RZnixY0ITV+cyD5>6I;DJriJzZs@~dzV%zn5?E*^z-WdO6}MUw zU^D?n6JQiqg9$KdHYDbrkzpH*vDQ)v`R?(74L{E$rNdw|m6R^iOR~AR)9{ym$b>4+ zk&Wk>KPtcn1;sIYDn`}tA=Nek#%k`}SRe7y@T2Q28F?D9!i?}xRN;}R7QH!In;qDD z82*yh)C2IAw7%YA`MPq)Id9+ec5VOkVNUM# zs5q(Yv$;0!k_FJ2^-o8Z)+R+f#B$F-n4;KeE`nB=1IeMcRW(^-NxG zbuKIJ$9|L6AZht_>gwD_27Z)A$Cvk~xqmps($fc*q^tYXgYIE_!|!}lq70;@J~Z$n zg=+OYadgjndDXAHr!*kIO z7kC%s`_t2(8=Zac$GzIP{2~{!-Rxk^@JzivwPxwvK4(dOL$h-5Tki}H+fQ0I{LZ)J z?B+b^u_*6M-;sLgD2}`%kGN+CelhZH@JHBpbFue+kMbhbPAA{d+npg_(;#{5ksqmJ zt;(YQr)@XaDus}W)wz^pMIzM2o4tK^>dlT@?6=zXr1V(#T5f}bsVBQt9nRk2g5bCg zrf2BRcJLtN&UkP*g%2l3w{gh#+9U)Bunur4BzRGBoD&Eu0lt(unWtt(UO%GJ7sYTY8Wu0pM= zRO=R7>PlSrl;Bf}PZ>Vt)DTl0@FF8kDfkK@cZ5LEhbM7xe2$G}0Jc}yeM;txv17!A z0nc)^_{v0vYG(|fG*fXhbBUrn?&er5GG*&F~QhcPgw0%XY5yD(el8HK??vnbC+O4vj9)ccUZ1ynIJU<7yXr>m;s3W@`&&Dl`#*6wT@^On9+^P#vO8WR+9yFRhALL@u z_mHHIu3Jjc^t~9PzBA{9`-e-LC(>t}-zAW{R4+f= ze}de{1S8QSIF{$*b;v!0JQ_c-#!24`_{i&EFRX6F8b(nly@DfI-{&AF`bRfFN~8}K zL5s>le(z4F@O&T7BB-LQB4*F``(W~h6tW2Vdx;EwA5JPf2Sca6%}-PNBKP=zi{MlF z??O1s#(oiIxGhef#FH(~e@Q$&8J&=LTKg~^3?(X;BZCt^59K7X24AP0tqfVo>_{*L%eUShRE8PiSE62-JcF}$DBVr(XdQFGuY zo)=aUEZa)4F%z!4)3-I)>QA`7>FS=C=dx*uVp^ia6(Yd2M3HWJVdN&k`yLb+V4K7h zMPfFI>oHy3O;>j_UbhB$FV!DQ;)ML9TZFcgNRsunhq@$`tn^=>jF0nbUsICRlRg9f zppwK0m>b)g8`}zl9`Ov5#BwrS-Az|_)79N{b?@qG#g4f}n}gdfZEJ6%!>+)#t&N~f zTRVwuYp-u@>GF5@TI+-D?X6nQwl-gD%a%5ObG@&L2hhg;yW|~OkAT`;2$+q{1jY|@ zJ>G?<1=c33CGFWo#Je`W-$WOn;v*Tl+i)teTBIO~ckNz^yRE>AK}iqXdYBd14zRpO zh7?PRcY5C&o7m&IUa!M8c%`lTEH+qX?{?su9nEEfcAIS=>x@s#DbHmW_Wv@l>5&1& zaz^Iix4Q?A4t$@T;ZpV$?2C8p8oVk z<>X=a^8WNHPk-uMProg{c2IF#Tzyfs<&LWU)cmUc^gQ*zMb*|jrdFqXDaZA!_hVk= zp4ojjdDVy3juvLso?vd$)iLM(fmhV~PX6;cWgv|`yvaUjxBS|z3@Xa5{?ybxgBE2) zzvB3pfmAyy?)znZ|3=0BB0HGko#UhyNW=2n*X``2buHO;tUBTyKF|ng@$B|I<((PU z6(d`-$kOA1S++xDVWZ^E4lt*%^WZVUZ>N|2u-~w_Ri^zfL`EWJ90Uk>vUiL%QCOB8 zRPUO^j03132cm!)abQWr2?tXALB$ED_9#v`nqn@{PlBeQz2}J{GY#iM{28Dmw*Zvn zXe-nYD-QUJ=nH}31g23Ukc|LE$`k1!^k*49#$*J={|vM*MWBb0Z~>0x>L<>O4HTaR zI~kgDkqAtrRDq9_%>o3T^Ahb#92-ILR>;Y=8KTMtgTCt_7YitU3~~aL#I*55IN>65`#ijN>RKIWKc2n_}187)3S zNqK3xhMrCyAK|-XP9mY9i)jkX_y`yhijP236kd`;rwBKvDwza5D~Kr1WEBzoRCaj;Ka!P`2Fa^x9~abFnPSl z*6{9ev3ThLHzX`D{Hh&th=-Oo1b*<>@9?#BdD}bc0MTF17L2!jw}^Zp1!1A67d*Rs zZ1jsLSqqsQ)`bFM@XCg4gw5dDkz0tDRp{BEQV+_7bY(>L!uKQC26hv#$9UCK&<#0Y zhRCnO-z{ws;W?;;!e*?iYQq-k_`9an@7wM-)?K=-skNoq?`vBh#2-KP5j&QX219x2 znEE??O^uzR^O8__wxq zTwmYR9=u*}IR+~ZA%e4)Dru0-imk!+jxJBjmZfdYExxuZ+99k9X>RNFZB5JkZJ3L$ zh>;F0ebX4kGzKw^LCmluW>}I0cdf?_H(|>oz6olAXnU&}mL%bjE-;-i_dSUIyN99C zo-C@{x6w0NqH7y^Ok)t!7{oLNF^xgOkq-bfnZ_XePrzhMV%GYan-P&RDHV8VNy37` z+`L`8s!d~%j&YwN^e}6Qud=cBtx4&Me5y%GRpf(B;;O=XIwhn7mV#T`+mgAC&9EeG zEgcgYqL4MFx$gn?JqW!p{OE=x37C-Itt)+fLKc^VV*2TYBApAZpf+iDVV$Viffe4nJZZ<$`y9i0%b)cw9d@~N z$>6{rsOMTp6lm&Lp94KUoJC1*%^nY}y_2=13G32Ey08Xqw;!G!nChL?d)C22-ZTW0 zsqKH&nt6xy(f?-b3y!%dJV?%9%M|Z=ue$GqZ))#FSfeRCOw5X0>ZNk>-m0S`kK`*u z8`JlB79LA^w7q9)Z@zcgVD~cW4Sg;+R+*bMs?1gfZ&VPsel}@9Xql=sZld&1&uul1 ze20q-IqYn}?zSVu4ci~UoI6U6Ji!JOx1)r#rSDUmg}bNrzR3gTkY4xTbKMsQb_S{k z70bm9?m_0>*+BWVgO030pL;}c5qDdSd&J_p4?%U(8Szdl1xynGg`pZ$rzOQ&!4?n+_=I5py((=R6`G-mN2cud0EO(@a?2PF zSjJO^>x4OPtJ&!r^(lv@V&$`a>fCi+%;y%Wk5#whwwk9rGZ4gxRUI8xrfJ4xG*cvN zt)AMe%+1Qr(|h=o$Npma$p`$j7Ew1i&wEB6>9O`A*M}A52sXQi7iY0|a&lG;Z>vHW zpX(H?a$2{``|WH6-S^bjMk@~=_pl5i>cKkwD#!wybaf9 zDCiGD`@p=xD#!iN!u{ZT3JfS>`A-!Bq(*_X#*oELtX5_sWCW^kGYc0e1!^fLD$Eu@ zxs?FSi?{&-OnB^60nj+FkNl~`BgDjXqD6W@pkf~L2PR!w%p8)32oI!#Xb&*?(nED1 z|6JlxNPQ>fLZatspV=n-Q0ufxS@(- zXs!^=%99mqs3Od_9;#@HJ|Q?KqcRbw${6>^j<`qi%#)#rCwtpiTg?^On=Na^%;S3D zGmnvrW016HRc|Vpv&O2&Iq-?#bApu~F(+8bd`=Q+4s-HhHutj+x4FN3xXpdn@}Umq zkTsd+jF&*H*Ax9HxUuAz3JWp5%&{Il;A6Sx{M%;odZSTUZ6sIxB6QsNOu>Js8X-JofBs38;SG(2p*O%x9+WGkDNgRSp~ zf-l$k&7j4I8`TQx0;TwGRKJ@j>OVyk@(xwwF9)Ue@gU0E@1T4L%-=*54|QZ?nTChDdqIoy82e{X7bw|U zQa=w9h5R?EJfE?DrE<`tdikq*c^{R}g$*mH3lx9X^7<6flIq()i=8l42X%qYpnT|e z6UD=$mnh`wh~hWAfhZ;+NEGAKMHJ`tInd$)j0dO-v=@~0e3K~J{3%g9e7>&p?-GUH z3-I7f<5~(z^Lhy=jq66xIna-IfL4_!95ZA>7dMngeMs`G&~G{!-1Dby+#wuPjs1eqTqp9=oIw}{pJbX7~?0g03ANcJFg4r1Y;l>ha(Uo zPT*veeis@P)fz1UW0KHiH{o?qn|`47LO<+S#eB%70}p-v;%Ti z2}YtuKZ#?IyF@A%hs`*^GkqvcnH!s*#MzLej?mcixz(w$-Lng@VP8ml_`ulicF55@ zkv{q{rbK#s@R85=7RZTtB^i;7a`!{dBMK#Y2*>jI{x{^P9cq{Epp>Gu`$x#p*c+2k zU)j0ZO_B7Gu{ot^`aS`6<8c;Ey49sn%S?cQZKoeC=4IVw}n8ffDu4IB#b{ zE|z%{^QE_q50e2nX5*1Xu( z-v-Eu^@kNvw?`p|F7olikn{d)l)c|LBy!=hYI7iF*DK+gXREE)|-xkBR$cF8U z^)n9>c`Reul=xV0nJc0^%}}1kY9q?i z4dv;qEuuWbP@cg)8&N)m-6Qej*?Pau)1&1yobS^*@8rCl9oKn0cA(tBMs(iA`BZiW zEjT1BXOyS0MLJJwaT-f!SL(cz^BH(&chRP%rl!uK&K*Tvh*i+JsnNH!vAw+rTUNJq zZQ8lDwW!(G<=e!!o-1l@>DW~5DXLzx;qvu0E7#Ul*SU&3Yc^h?6>k~~%5M^Z3pOD} z!6qIeX;avdi)V(}Fjigf#TNHX*ff~ptae`C+2!BbSx~T*cKO9d+7m3$Mc90J0i32L z5P_%F1f>(#T|8mk64%7V@ZOrBWqq$@DXc8ETEv!-UL=gMW5mN<)Q>g%pp zTF;Nxtf=)YEw7^E7y~*+-6#h^J6by7+SLL7y!x&63-PZcQS0f}r7#^%)G?q6o{C9T z)&g!N-hAR+*Ug0!ZQ2ZDo9M`e_bg0Q1BHo8v@V$iCs8-K^=gK(jq$F>e|Gf%L8j+Y zTf!@r$A3$3xtpF##o|%WxXGUBxfB#Z3PX0i39d5!_>quJvi6k8pFonVuiey>Qqq}> zZM5mRq|K!n##aBsDJhQ`JmDn0pv^G0_yd;Qt&_MZn4U}8Rc(4MnVw6@Tu1x~WBpb$ zjO~QpLs8!oCHIyo=Gvy`lK!?cG9bTdS*ja7 zuv*>MFss79Gpv-8l7gHRCB=Q2W;LJ1&O5UAcHnSn6ryuVI%DoMKokx(hfSFZ@GDi$ zPsLeLKJ;X)`;>6x1^p>o=EF~%WTuJ8IecSXm|8H z)!W6Ov9sX81oS~M1D{z5agLoz;7_{-3Ik*~Xu!waK zS6?QA9WP4`#%IE<&T1^nR*`EXs-QJP-exl}Hrg8m| zDnJVp1di4GBm#)lgFz*V^qAo*6Wjb&yg*HK+)WU;SX#zoV?8A}t|kao0%Z62?FZ|#Af(P5qUd_>q(2!pYskR9M>mYFCTf>iT3`@g##0mo!y*WyO z1Jg4oRAu^a5pZtrVG1Icx}QP_4z=v_S{_sOvoBfaS|4G2r%!|hbhDvZsm~zXqV+K~ zAHn^U#k+3U#qu5_HGihLCfXbv2KU z&dzd_xR*XUIwuR-Q!hI55b8QEVFiBdIGUaRJI7`xduLkyGoxp$MXRanyx&{8=SUR~ zYWJyKLq7G6l)UAfTRnV&hu(86eBg0c;92z76*z(Nqi?wtXbv77wlyf#vv@C7jJ%vh zy>VRf6nc4_hXAzn2Ah?GL%!5IF?Q~+cx=a(4>vmL%y#7fVBx{?w6KjT-}|&GXKzk$ znH=~I00sr4OOZp{;h5snt>wY$)+&V%k%M(j6km&EMIvCtlf8Xx0IcQNt?I**?1h@6 z`>6s<287N*TzK>GaCK9Oo}ovuJ5$G<;nd1;Uex3M^J$E6=n_2sGlhfEsx?zlGo}D_ z2mY?wE%ppR`%F;)MNLtso_dd|buP88M6D}T>&n!+aw>rQwqK~C?qHWL_CRu<8y3G3l7#ZegrjimaD~ACTgoNh`@O= z6=yP+D9Yn*?#ZN@Gp>R7159BS%c<`;r?~rmaQxVI7z#dAnD6&(s3r)d_dzuG?Bp{u z!PzB0GqCC4GlNDxsJKaFUQi5B7ELf0=mO9*T(8ZP4_lE|$_MSDd@S|P6UBVqPZaSw zz6V+ikoI*@7wDh#@^^_s-ipgB4flmYqPR7Xn=|p35QUxwqGXq%P!JzbhKa;~zIeFp z1NF?1Xi%ah=+f%yg(TM>MbKy~Los^x;Y00GUnmhZ+RA(#9h}NL$wfk6Mq8O@(D73< zLdBtj0vu5vMf%rCY-Q;Bq4YZBZjvgBE>xgQ%4W^z2p=->L0j>e1nCGv6O9kZA5pLKmCN9B}=_TVF*$1()ei6y2^6NEgZ z#E=ew7yY232O&r8P`muM3N%`~k3x>d%9xD$PC%{@LZpxX=7C1jHyZ(2V$s(GIiZgX zBq)(S<9yr(xmaRUJP$cBAGC%kMeEx^Iq}GcJY#wV8M3|&PVL!=^g%UGq>pU6Dqy}9O2VdVyci#gDoRQ< z;mK{fy6I^R{VQiqkV2SiqU&+nbkRG(4=u*W{pe_Te1}dw1zsdFw31_b(9HZ+6oOKW zkH~U6`)fqG1Ao0p8Mwm4#@bF~Qw)todO3~UG_oi?onl@@{$cn52fm23Fsh6aUc%6w zc+H2*&<;FMiqXZ@wCZU$t$JEon~TRr$Qjoyy44KrkeG!BSsNzo$?rJ(V~jZf;5ojMTL1F|B&GhD=9Is~*#;#|-UYhIZ)cYV{*t!sg(%OWWGp z=&&oWZEGVaf}IizXZhBaE`NuwwLXZbzgo_=HeYMYmNtZZ_BA#6J3Eof{dMbu9qnEI zrmmLuHmCM_E1uUF{LgVj|J4H!M)3vwXvcRjyfLN7#j#rVWU*h~=I?Vm2|#cYEMaxe zVOB>9Ya|?&z>nMax)!?W?YY%Gi^4j%L%`xkIUvGeoG*dA0!$&0#|ZK^;idhih!^`1 zLLwkY&OU;1vI{hfOK4w4koSi`xXzQx#bF5!NFUVj^hd}!^zfj@{_P$i&seFTh zZ#VFJ4E$Z-DT~hOboTrI5S{)@5&At6drQE(Kk|o0_S9d6z~L=zTdwkVw0Fw+S9JJV zS`7ulJ74zLH~uD@&iSTuJ|5WQ7wl$)_C#O&nlPRT6{_UWv^xj7LR5-)q&^Ld7x}?iE6z={c>%8y4&5K-tgeS z^C`dg;mBz{%23$+xzEoZ709?F(-G9w?C}4Vn4Je*S3%KF1f&R&~oRVBaTZ` zGnM_BHg7+3TLw>AF7T3`e;IgQ$*CrndE1v~I9KPc<2|(ZuFhRjIOA1E-tQVOb2=N9 zgKF>M(P_@7bEeO7luoza-$*qY0`5TvYiOWjwRg#^tcpK0D!tI}#pgV0udTYoTQfY9 zQ8~_(tsD~qtm*nJf#;SsbVD6KA+=YcHkhn>5shG@Qac6f>pV~ zO+WSUGj9yu?hG7#>nQx5-aZ!OE^g$Szg%VVe{#)Vt`q`+NW>|hPzz7?j{!q_ z5GqM0OAhPsAZ98YtAL#{6(=*7D9Wor=$0 z4!Q_@8rI<+qF9G_5ykraDN!uaSM~h&h+^@Qa~;tOh(i8yonH$|danR=fd(lb>z;d% zgV6H8fBk}>gK+vF9LL>gpW34?P>N<#a5X^wZ$i$Pj5Y<+0oeaF2FLOA7#+t;Aa{$@ zuCO(zKu4r(_H9Juh-NE5cRE?_yO0wOw(_}bFvuN;Tr^vOX2=QK3#vaK13=?N{Sx`) z$huA9amX%#+;UKoqjE|_d+?F_w;OWs%^s7Ca`!^cGe(LrqoeohkfU~}U4B0Wjn-~I z9^9^u2(Oybe~uZbV+sBuD8Le8f5d$=YSNlY006UpEfovAKb1N2XNBiIT||k zFdqi(i>y@+NARia-z1)H=Ffuf4&`aqD}p6!75e>{9csYF`a~h91rG{;1`S(`*bLSz zS=^fC4yk@-=$PtHXJ<$7cD6v`g|$nMo=4U$v}?uzeCT#g)+jYNrs8g${}`BEIKE5g zuLDnQwCeod&RLwl6WoM9&o@O}2TiQLo@_}vukY;gZ|y87*xKH_tra`4Otw{pwA%!2 zQxRno3PfwtvKL0|O;LgkFt~K&Mi?cPQH@&U&ek`f0t>DVj80uUQwCGDDk{(lV9$c#weySifN4Eo5a;u`w26B%B4F8z>?%bBaB6E z61<0vfo&4k6B$rBK|QUZEp_8pU>c*C#wfyy0$Z8-lktW&cZ%R!J($KQrZGx&D>tHz z6Tp^!?M!17(->vKU@-g%aqJ^a;wx^wxB(eEd>w6Y|LUywb@=Q39Ubi*g>F9 zt-oYZ338j@D?Vm7b>yF(#weP-q~ul3GmOA0$LrEl7(@{ebiZ=cOTzv!tva<^y3OJDcA_3|_- zxwfmE%JKP$x8Hsq=zzCB1BM!zo86<C;m`a zScF8D;;%N5OiMT|p!907l~JoL})>ESPheckr2PZ<@FJNwEjV{_B|2`V1fhzEQ*s zzEMOL|JIJ>Z->gkzF3V_1VBd0yYZ>Y{>R-ZH(PJ9+^T*~aUnys>hbD1{EiGz02~4m@uZdL`7 z&_h@wwB>-d1ptMg;44Sia9~k!ke3I>#xU@e#Fq~hgcEfI8Um_nDz!=*O8wM(%%TYNcqQ-XH#<8(5w)-UHM7v^{MAP>J$i;FVnXsJ@`e1Iv zQ#5^ZAh%pEmx-}|n+1o^#^f(4B|oO{_KQ-&gRF*UMta@w++l<@7ihS)Utng~%g)XXt{YPka2( zWabBFiSY#tPIxAVPJLCM6(VGb@k9il%8p7rt%>i0$70fxjr~L%f|4c1Z$Nj3@@#x> z7{QVy#t@hviwx-dYv`EjXR(ZM=fF>6=YYQ^lxO36$%rZzJRww|?6}B)z9k`9(wE29 zfd6-?oGdRyvaor~5B^Ug1NFB?lwZg`3BDneXJfl@{9}p#Z0MNUD`OOgL?jDa$i5oE zSFooecsu)v#EWanr{|F+38i1^3I#95T=1_+HH_all4r8&hG_JDrgOm{6pZcMMi_p{|G#t(>|U5n_05xHy6p2Mci&aBwH54 zMNRfB#;gk6#HGX)Vfs=EOPDC8FJ)zVHmXUtkaC21;nJ{-k+X&LV$lfXr1FIZ7UFU# zx`5tFL6dmw82Qh}C^j`@IHTX%JKDC?Z}GPw*jtxhc&^Lc4hVYit&rJy?IS@A=6yQG#3iLz9);H zgoBow=0c{qP%JN?1%_?Lt}$cR@TU&IS*E#A^sS&wbD{X{q_ij5Dug*SW7p_$ludJ? z@WV+G0JCW>WSR?^=0f86O_)3>B+YCl7U`zZBJ8fF@-y zB(%nFF%+&Dr^%407G0io!DU5nj(X4V zrrvY$Cnwr94*5%HeNv$yFnZ zcpRBa8>V?Pj*#Zs;Xy{)pLyfNEu`CVmknCZ^rn8fFSk4It+U7w=M!^gL8qp%%zF{n zxMJi%9y4am$kMq~vLLEPWgu1k#mK2(aM?Pqlj(W^ zLbYy@T34agRjPH1Ep;U>d`j>s#itCPa*i>pSfpGNH?&fyDI}ueICOA4*T&LRi=wb4 znU2Uo;gzs*@t>(!akNrZm{yVPor;;oe{NtGcS{SSwuF(1+7i|jZwcjbw^SXqC9Jln zEn)TXmQaob7jZ|3H7pZ`iMjbL0i(qy9651x+rg)zB5JqARN&%$AErWUsVHhoVk(R+ zB{mgWOBY9NNlb;YrT1Yfa1#1dWa(3ZM&g)?>3k}dMeVkj3fwQ>hpEt7x-@D_Vk(R+ zB{mgWODm(cB&NdH()%zKWVxbU6*%Ho1sXA4V&W#~z~*HRo5SvKI8q&Hj&ys5Ba?2K zB9ZAzRrU?LEjQ!Fy(9Zm{A!z_>%|XJ98;{__+~~O4l%{}sTyyJ7ojJyM5dc2Zn4uc zZCbbaxuCE7He_r8Ka%`5gmQO`Eu1A<$i=xhZnocIyESEx{@cde!VhWGwlE32EtDJQ zBmP?+ei-=V;)IOKCYoIN2ebjbjs63QCBT(Oxj9dyoEw?*A<&GNNV#Ev_yU6EH&>5= z_~6W?>Dep|4~;cM^R#EDG@Sm&h@ZpQ)kM+bFY4v@5=Hq#L{Wa2D9T?2o#SNeZQ`LX z4L|E?xFdX#DD>V-l97M*sPmu@ZIQ(VQrL z%xD?W^P`<8E@Kq&=Rj^JikYWhKzg3TgF@Iyl#ca8qZ}=vOIn+HA<6Ye5hT65k9yf0 zRNRLQ>aSDJ!wr9oZTHt9@P=Gbm!;=wYFnf);soECA-FKb@J7h>pyGMq;?PlvF2~0S z$B#koDydy@SfR^_im8|h795&-Xw&^_zIT|nO zm&m6%-6rukWG_N4fPo@8KIb|$wp;1c|29CmoQ&<>>@3|IVEoK3}@FDMiz_8gjAdyIsw_GomNi!Jveo%!U1)=XkNuO~()9MpY~TMGfwcd;%=`mnce*+OSH zP3EIhQCd-^Nl)&h^Q?B`4*BRzqn@8OJ~~G48#3G9+~M2O(zdxh?64Ec(Z?)I0r~ zp%#Uae?&J-%YM_c-?Z#EE&F{rhM9(UP< z&)c-@H!b^3%YMJF(_cKEeP1|OR{R&J83@$0>=#D3re(ir+0R3nE~f{TBuueQ%YM_c zU))qo%l?k&e?5mi6%)VG%s`-%1k^VJfznR9lX+4{-4)kav_kVEovb#6FaAFl2$cS$ z4Mzc`*NF0KON1}Q!+Nlzy$O*{;|tD7iW4yG=e6QB>PIErpg*$zvD)=x?^y*q&nlM( z4%kzEnLntimp9PyyT`L0SG#WuRCm8?B&zu>X5zc=>?jcDXfn$^i zz?0j(4OV7WUZQ=8V_J5y-0hH)SCgo+!60`hme5n%shxvd0ZZaoES5`DkuMfZ*g9f z@wn9PR4$>NM;cJdg^R-=Wq7y7aUuyWUR)M4O8KOdw-iDt&!?`RHYlYbm{=H?l<+UM zz=&m1xIu~*rUfGlVVI#XgrOXLki$ftHbOPOgracX(5XkmqF4$x_RR=Bm3>d*=^pa~ z@Rx`3Z0u*DV_HfXJZj(GP@awbcj%bPGYxwh9{}9aUW|@NWVqO)v~nIsK1;{{`1r z0shgnyp_S$#%-l9h&ATEYy>U`& z9iK0~q}Dn=QN#nj{fB+zTLmmU3J1yWt>PcI%mGM}RwuMbtd{Y2Nq(6|0_)X6S>r+Y%vfu{ASQK0X7edo z{{~$-VtYThn&%d=FY@yGy32dNgm~x#ltUubgCPfAd$|`h)63fM^yg68MFOcYDhHfm z2;E;P5}Z=!3kbCZS6Wz<>EOiGjnFlY6zT8`!*zgs&pXmd&p|}IP#|zWz;V838j%Hr zkK!)HxRbPt35PCoHbLlfjB2-`shnn_GMB z_?j8(VL9A!(Y#S9(IY)kMXu1LP9PU#kQ;MCAv>NR8Zez8+OQaKSfxxIPzs8OSqfyz zOF<&3xKww0c0JAHAfM?*2=)hjoS`YhsPZ^2n1NMB!+Di4+Ae@#%u*%|Dj2<#3m_QM z5t@R*Y~q4JA-a@@vW(%A4ooOeJ{%)@r*w-4{XAz0(F}(rY7hxjKbntD_>1AZFi+#< zMbnM*LY+A;%<=cnm}VkMOGou-bxFr;*&y&Hfk!>(AOd=5`p-ubRzkjT1Gif!Atu^U<)SO1ivk!i8$7ax3UaUQ{m`PkpCb=G+Imy@HPSEv^ab z<3K06AHh4g`e)O;~mhg6X_~A z0z{o3YkiF2Kkr|@rsJCG_cDI!yzKH>^C6jspWv^`?-n0pWr(Bk0uM7h5I?enD=Qv` zC0tq20`qWP-}(J@Y{2A2h*-kqP}TooEaBci8@C71=x8UMKKBe4gZYPS+zwgrH1b}6i76WhxN!rK(cZBvjxYaK(sPQNo6htr)Ps41*gSxrh-%Y z6~HNq>O?kWbQ&(kF?&Mb?Z9aOe@o#1K%POau3cNV_JZ4sDYlZrR!l$gw7%Z__R<*I zQok|S(#q6`P1}OuCSikRo&;Lo)>xw*dkQNq8O0l+*ld}3;O%5ULbH~{mR8jHDpsyp z>Z_brIeWIRQf|DsrfhC$(Om!BVt?_xYfFlK8{5M^Ob9loYGqY*;Od&o{k}O>^>u5j z>-p8nrK0Ynjk(OK+co6MeD1}+jBv05SC6khCv)|Lro6`j z|L-*zXZ3xsBJ=Q^x8AEL?`7^3<0$_6Lc4GTsAF$MpVM*cluLc=-Erea^|1ZklQj;1 zzw;87zP*x-D(lZID(uhn-8Ln^-+7sH-jvte(^`x|emLcdzV)3rkg{{#1Uj(uk=&zw zFZg!_-aO{%z3ZAo1|4Y0W*+VPoUg)g9Go6H7)b9P(F4i`N@qT#O!FI=m8XuAY1rXE zymve5S3~u?BT~QWzS?}p-VaY{@>TY-)CUZz<7DGIy*SINr?!7u(dzzbM=Jo!0qgRf zJ$YdCUtZff#W82r�EQqLz1s>DbIQyq1rPT4r^#gWi+Xu9ALd#+dZYm1EG-F`0$^ zV^~?`^nPdFqDnUH$HzUrZeyXrW>Q;HdL%|ii&BfIZHtV90mm`Xf_tDI;O1l8G)$a{ zi9c&B4Zl`L^2twe=lNa7X-8`6vckdzm6m=M>b;SW?IT%E`@-uQzgu7)NJ zBdOWA1{r_Ipd?}(HcZ15sr4ilPvA!DvjC_#H!>1%+fwpvJ@s)V;E|DV^xPLl;`mjaK@R?n7qE z%ZCCW4FMWmDnFd=%I>8?v_M^~M*lN19naB-fEH+Udtf0mb08VFAtZi$m;xRG-A<(d zRD*|w_^U*-qKWp5R!TvK{{w<<)UXmnl>?|4)0OBCfKDpqrLq}gZGh3rlc1|bJk_7l zDG=1lJq^0$Jk|O~FZVJCUY0BSEf&A4K)1@uieoyzM-_g$F$%i0L$dfh=&qB90uSI? zwx6P1(0i8yQhQ}zQvLoJKegW~LB|cZ5U++W15x=c0Ud?{=O=Bsh~K=@k|KXB-F=zQ zSH$DZzY9uDmA!vK$s+S?j`Qp8UFKwq=8Hal$)eyA*myq%7ipCCjwn6>KW-UWFcyFOlHF8P*Fecq&_>;L?lF z3Q-5?#pg*4ZxQX0>AOXF5`RnZl=xq?^pi^Za;1D)K|ZYE9U6X{hCis`pV#ms8vaY* zA3}SoP!?H?oC8jMS}gGCXj==eZx(m}`0sE{bAsrbfOq0I4tWT_7uWZreN7_$Ip9A- z8a+->`pkVVSUtsSs`sNPP0-*3Yd?%xP5inQg@5BEfRl+`s+ zF?V9dym41GN9{!vZJ_``9qOwsW7A1ZmxIs#~WsmuB#nemJH)88!SXk!BsP>K>imeW9 zH_}kmS<@iqKM|E-ePx8*fKO)i!qT-DOm)!IB5 zjX6RiOxCtrS(wQx3!TFJ8h75hsAMX;fweX%&r>gzNM$#mb~ms9isrl`qH(nu;kCr11TgyDQVS4>1&lV>&A)EB5iGjE=88!07?q>^5*$R3fLvMa-C zfI2bGISoEmU1FSkqKd@fGeEPFMp9(zJWL&^G8~d#uY||{q>&Uq=_qL=l{At{8c8LM zq>^5*;1bkyFPgy3l^ZFo*;*3c4O%?jBwBvbNUAM3cp6)iB9L+w>c~N-Ae-}Tn%~YpsAWx890&MP~PvJeS6^7uQHe}JrgW~ z@l}82SOeauQsIp%)n&Zba#QOrqq;A1W^sSE@2O|~M&Q)WK;Z3?Szib^xk1tO6G8!Y z%EgS_#dNyU>!Xd?#>Ga3v80O3jeeNxHbow@4map5loDo*XJsCc`i z(8Wu3oEaA`3H=mh<{LS@)N)=@M(&pa?lU=SWl05-3ns4Yd!Uxea^#*p?r>L}U_t!y zukfLcN2pxhW+%#Zu4!!#q@Hr6mh@+B*pW+Z$PT@MGTcTH=e~=VbUN2(VpX5*d#|j* zpcb6Ez3jPcsz2wmwzU*Kz(kGnb3(rZkBK}_y78&rha0kxrUQJKLoYpxd@0Vo zs6omfT1KbCkjydlot^K5TAh!n_7}fIU)Ttm7rA*A;zJ8XPCR?jQ92dW`#wr)zIuM7QI>5~Ge&lEGUB8J!jH z4Wu3;>5(y6a55Q>`FqOTvI)-@072|{bAqPj*46=lg%IlyXq58mU0LZynnSZ zn)gZnbK|)rGsxSUv%6(YYe|3RhTYE+kIc}wQR2&!(v4HRe?}VY6PFsrMm{f3yrjeY2nKME|(ZFD`%ogbjWeG46YIN@e8oo9HPWBlv6n2i1W;=*BjlAPh8}#IpN;K_T%qGIYwEfbFcFN)yA9a zc||w_sw;iSGy*-d$&io6@0g$GYIhp#O zasww&#K9oBIS)5TBL9_~qBN6%tdoe8RVaiK+^$)n^h<**Tyb8JeaoG$yQHlmH0op$ zMDE*o03;1Nd0XK&PWZ#kDi;V_I>d9c%DJYkR>Z6l#%tWH67l0HKb+2yZ4-G@;*MR4 zgzpQ)b2~@S7f?FlXAp#e)=Yw^%xr=v2dwy?c?2^}zg=|Z+I)e7HK)InAj}_-g(p@J zMCJfN*zHvkT+G-Kf*|6yXmiX%{HXlZ6z^wjEkT$vTul&-xrQL}eUKn3v7R8}KSZ#M zu?B*OZzKp)O0r^Ls0>*^Fz|0B2!2}$!p5wPAle7jB*(i5f_{gwg5dvu1pYih&<$shO6Nb6^=ACY ztTy#7&)q5axOcgB%fT9_VJ&1I2_eq>rU5p)Fw8^OaQB7~{rl~b5$26oP$?<+W6n1L z`P@?@U(fZxOv&YNu#!<;t4N59CMnHRC+5{Cf+K`m#syJ_i5NPzN*XUq@{jVU@avW<1Y7r;m1Q|wFdZ{Irc?nL$cTze$kXof-ko}nXIIK@_a4{1m`Z`{ zu=9@W8?llwCu+fmeU70M)YaC*_6axSXzLR4r|B_eHzYPG}p`XmqYaB1B#DkEymZ*~M16;_*=qQb(=MTK-4 z(>9CClf`}B5r28QtcIFIrR190(S-JQjE}hv>{Ys6Lfy^}n*5S`ozDzx z)!{{8sM0f+jiLJbWI0aj&%1`;iNw;+${I3^el{oJrGxgfUW(Gs6*k)xnS0&mn|pd; z7)f%j4`Wc7O`1K(pwi2@0E3DKtGO2XM31A8;S4G)p^?ypD_ShXgx~`yU$Di%A4b<^ z@TKDVLAw@@sFnewbnP&tZI<$(L8PshaRH=FTVPCSV{GvGg+dbC@P$Rd-0+3x3#M-P z%5l)!Li$Ye6x{T=rYFL5EZFoILGgtI5l?#vHeQ4sGk{ajYkbQW2EpBw4*G`#9p8rl zI?jp#OZG2OWQm=Fj|CpJ_JHz~ryjnda6hdX2@K z2!Cy*C7fP2@kGyGFKIl`Yvf3RSZa}#zpmlQmcO2X1%DkQpavQ`u>$(VteZ$Ax)U)7 zseIlRk;Z*Oi*`ZoJW$y*qFmf!hqm z;edd?<#b%0xV{K-izyP3XV&58R%+3M0Au+f#9|HsdD)kgtCGXwV;>#GtkL$`B(ydEPii+Zn?&b zP@P{XCb#6r$D-i38&IuZ73lJaffjVS4WJ8XG=v_+Ps)k#Pl1l=O>&{~DG;vn`$etklAnCZBYt|n-3+43t*khv%lUcGNjb|KXe@p& zgU(LB<;;rm!&58|vG^5$Zkb3|fnL8hg&)mr3bFXz3OYOU9%8jO zcecIpat-L@c$uN_)7!fdbavYNMbOFiVyZ;yr}O&}=$43d73lJtOgCE)ko?evJj7~m zHRzU#bQS3Rdmrdzdr<`*h@W1+$3a(aCR_gM_4}n#KY4$P#m|GpD=eH$MCVrpI@w-4 zx9|{)Un}VFTrwc&{64GjqkA6(;-{}K$3SOieHn>|Gbukj=kO4V-(=9O5$P(>`=dkQ zH(wCOYVS_a87d=jt+)4kpesZgjhBUjCKkUxfzD2UT!K!J{P390Lo9x4K^JSi((89X z;dki}{9Xi|o&Nos!cX=e)lcu=8AbN`w*hprf3H;Pr}GPgF4lUW_wVxxzY2w)KHpvj zot^$j#UPgbQ8@&^d7!f+zby(s*?+O*_aNw`d_}Pw=*MCErc=(Zz{_$?QN#1Cfx zloT)YMT39AqS6J$MI{Rc@gq>SXrbSvKEEG=aFxr*z zofPmC7cl*aeNw=ml=Pm+H4Vv8>@OC4H1k9&gY>a%tOZZCoD3lMu}dCuANrpKPr_#@ z`SHfe0vaCmLBJKW>_((N4Z3Cc@qORGDGRlc@c+7f+~KxO>#Pn!C*1PGT!?Bw=Y=OILkG=Z-eHNtjZu4YqU{ z?cr4&&EX)OWH0v*6Q@nuF$EOY0w&2_w8>qx)_qj1>S^u6-@0T@wB%6(@oh#;9yO3W zYT!IZ-Es>@au@BUc()K^i)UqRIJt{9xr?^5dEQ{Ij*~|XY};O$+(nz*MXPSAPVS;j z?xIcZqLq(e$)g6svEQEYfF(`{N!L3U#zNwaD3ZV`Kv8h zS>1!g-@>SekhpjxchTB8l`iH{2euC?pnKo{zFoBVILN*0=pRiJ**;4=eREnXd<}!W z;kP$zZf@-ARDJri(pOMqYmXzBR(ZQSXZxSyJJZfQg?(m+{DB44y+!kn_FldEXy2J_ z*!$M~=`%lG&1M=WQrO#v1AVE%RlTR&BE2in>mI)=;6CXBa;o!R%m-oV08oL*}^O}0h+52Pwb!3z`%P2*iT@APnXBx9iENIps zvTIJ+(v~SU%JF@1nT|qy&9}QLO&Xpc3)cb+G#hsdqerONcmU*D23U%5tr=8fTnh&M zLpl*4asO&bm@(-F#==0%zSq zXI+`IZjr0bUxc3@zheAK@GIp_r@cO;XtrZ#JTpH#{@MDHsyH39qn03M$3}t}1A7RLh7B%3OrURy z_@6-()var zR=H1rPTIwoROVlu->*Pdh$Q02?<|0^_@$x|i%k}mzdFAP&`EwYhA9v~UCu3_vty_7 zY0ybI%ez&q`h5*_6}&X-AH9BmRq8ihkjCOS6@xTZ{d9ioK_}ZQZ~w$kx1+febnC2D z}X2O^EFKC znDg1uEL!A;g$;%C+tKv-csUU}ni*8}q#X@}LUuI!0i#`c`rN;8VVQsEJdWoqcpCe* zg43Y*9&mc*GJ}WxKwbjUc^q#7h9YquepZ1*$&RL9B7iRVJ-{hr?50SZhh;}AhxGAm zng!2ge&A0j^ouO%lh_jAXO(oiy~#l5ZPWv=io|)?rpPtbXDYkFf~T^36kOWzvd78J_^6tvSBaQp)2X+52R zj$s(i@diRLjiKhoE⋘OV^GyUE$`oOgF&aX_Ska8L#N)NFq0HvV(eZQWjJtHxMkvATiB&&oVw5y73f~a4 zX)Tj<)SqT9t9}i`c4(i<3`O4L5uSLI*eejOG(n z&;Jzijk4{wrGC8O~B4b zFdn|8Q6%FqZH+`e%NJ7K3cChJna|}gPq%5J^FmQoZ`l1Xr+`=DTZ(Jw?fOFXTA*$z6R46iE8^^ zR_5Uio3l(;>eCt;rZueSE#+?dm&4GgVgeaG)lInL)VktlQEJ8!a?s69rutqe^%fHyI6!7Tx|Xz~iXCQ8T@>88b#z?h>DiVnLbPg2K=EL@>dk$vl((nqFy z5Mw7OW?)*x^_!%MB==ujl??=D8eDP1Ef|1vl`qmsmqU7FTynQzK7z2N$R`NB>qP{? zq>v!=obVFD?SAGGg#LIQL8yM`6NHk8On^u)O7!tGm2^dFQ~&O!QeZ@PCxYKC`|G*duUu2Zxc z)r}NPW7Kdcrs_N+MWj0TFll%_#rU^7p4EC9oTcik8O9)-DJIWw8ZT{OsPQyui|})z z@|+h$`~I1K(Ns?#XIl9Xd`RHmBS@wm4%30*&@K$cz@oK;uTf||x}UEZ1k^xHiWO*% zVFpD4(b+Wx>p^D9D@{{S`~Xw1v(QIhMD`q7ptaGQ-)6!L*oXWzM z`S)BO45=Kkr)s^>Y6Wbau)eiTe%p6Y-P7pZM;^PZ1ZJ3_7qJ5OlglpbHG3 z8t5|cBcP*ls9X$J9%7aIQP7o%bQK%~BIQK!FMzHPkoXN{3icbD{K)i3@{`L~tol`g zZZTCr3wr%-QTWNVi}>mN_B7}&*LV@CkC*=oI@xdI1$``jy`ZyW61Z?`l%Hw}rq{0q zbauwo9)%yK01vV1cMx=T>h~*!AG&Z*et!ntWg=Y#y8LGQqU}W%9;kl0>D#3~d!}y> zgAV`s_@kRU1>*NIe(F4W&SxFBNao=u_^XcRZ~CI9bkj`|&JUJv3l?xoHuKNJ1^ zi(FIwOg35>W-hFOR?D~X-16;EB#(z#E#D?{%eSLSy4CV+I=6f~rleaf-)3>kx9F3C zhuvza&usQ_3!cgzS8!<=*Dd%<4_7a0I9ak$km)B)G=hIw!~aRapH#}D$K>ZU{JX$c zA-)zrvXpxhIFV4F{X<&L)z+=N@RoCm@f-HGnC5ISg411N!5&VJ(rn>iNXKpAG|M?@ zB4?#8k#=@g%ehim&T%HlrBtjGyazR?<6gKl!#Ex{&@8U4vBv6SOMKF5Yh0T2vo*Mv zjieDAopT?r{y%91mo$P)8o`}MRcP)aj(3WQ5B!N`Pt4S{t}__-3L$+|#9RNQ5uCaq zeV|i{IORIPBSrjtl16YzBejo^|-aOZil#ZyGm&sKf-JW@&;!P&CUO3aKcvE2VF{cMRhOB_!ioQ#SuhUTZ( z|L#U`ycPD1;JCLd!*S-Jz|!7JGt-L+PwQUZ+ck!+a=PKus`My~#zqUjSkB(t16jt| zj|)8x0J&ljevu@QcmoS*xc^9-wVp1#X* z_Bd#+w{mnCWU2YF($x-LCB$ znXj0(Z_-Q+jTlB{Gr6f@Wej0J5*I)iCjT0RzZ8bf{{jdDQ%eX#F|Zr9F!Ghk%8>!i z7fcw_75-8fI{ynQ444M-$%sORA&iN9WQvp;Kqh)1S;YztMDj93BGH|QL5Rf}rVr6T{`h=|puA`(4;bkK zj4-bNK`#}e1v1o9ql?fmJ4TonL3%SaUWEDuKQ0$suK-;yC5RyFz7V)t?vJIV(kT$s%Y6f* z$WFQBuT7RqcQFdF_{{@dz)ZIM)!T8s!jG0G3dC+~c65S*iz}-&73ZLJ$!@`Op@NUk&K&@VianHCieL?KrF-nLo4OR%cR_NqphdVj11ot^f6OyP$i%LCOu1QtGGkn*_RmNLPVAKR%@J zo2~HEjcm7qZk@_VTps~UQ{ul5x(?t@{Nz1_+WRto4*X#5kCCi3$POE?ZqT*s7h4Wk4{+#ZL_>xe{d;o>8IYiatw6YDiHwC+bx;30> zo7dSDY}~S~Gq|bQVm!y@;^V7oO=m`sHJ_S8v+j!$DRy{lZbjXSxxucka7)8B_>wb; zWSyuOGTt+5voRdp)Y7)GJ<2E&L(;GWwJXW;_OnQh#+^R*O@ZTS0$t}}J%F^l@h5TM zXK^h9`J}{d!ANjnVB{z`4W#kFiI*8XY^sv(Vk6mH3!cgrDmXptT@JiZW(U7&C7pa! zt_40Z66ay+S*&EKy9H@~Qqnsk*Yqft&F%pHb|lW~Gm_4ZC7+QpxY#&$$b#pwBf!m# zLqz3a-v|BnC?3jhVfc*+MzHUX*$;afy3Vzx`kH>DLJn7TjPffq%mlt2@gTjNQq}Uj4wxse!$ZCb`FJc8)m$+#$jGUDv%@5OJ za{*h(3YzAY6h}>8VYLRuC{ih^7@4FAG>2rBt)!Qr z3TAwfyg(Baf>O|%1Tdyn;^#-=tpzU7P^(4u!bm9)fx>Mea#>BX%OF3CZ&9bOx4t&Jo#UIDyQO?x5D6Hx84Z^)_OpoIL^X=LYEoD&%ym12c3&qiVPImSh6jik)XNukoDDPh~Sn29A9=gS(rgWS~YPcw0<~oF*&$vRwh! zF#~m5WX$ck7(9K(n$T5!lNO>yH}0=-JbquU2mJCE)K;f)F0(>QS{6(+&-8}6SG3S? z&>7!emcj8^kyb@%oy>LU@E=ayg)$evnzzrpkD*RSUe4R?J$u}g?+gB2*b#s>6oICw zqsDBxNkQ`1W273FZQj0luMrG6A6Oddev3^%_7-y-2&BB``03t&^R-o{&drC$ddBPh z>}YlGME4v0IU8O9MW&H!%rAcv^v#pdb`Q#+-4hG&!!Cqz$bCm3`?WXv-ABueo|+Z8 zP9vo^rQBgK-=_lJBfiR+$56vYP?sDGjO}(l8ZcHHlR{<2YyIAxM{AblI(t(BPXt`u z&I6-DhgwE*8MuyRA%9V&x5s%PBlJWII5bgtSrdKOr!nWPb1PDeQO2yz&IdMcPRV!d z<9jTa*;7@$S6{!phdsik`FYPf&fHnyI9)qpL~qJ93k`7E%w~#Fy%;>pYO5z4A?bU% ze;q31IVSLVvB)UwVFw*Xp>b_!nsI69m!U&7j*}xi9`LEHb{~_yHnzvPzp%k^pwMV( z_;rXRzH~CxXK`pr-{M-D1>G$-OuU_+-wkH zej(6z4E4h4>Ms;k_hqjxqFo{z{(2m`QcJk07@HL?V{GbL#;&e`5*L98$n`MH-{oIt zp^FuoJ3(+o(SitC0?>UAl1X7xWL{hI^U~Z!E>fSH|A|qCgDes3ZYGh&hSV^! zfGEPx3CkKXICXNXR$KsbWj8d++~@`tGO36r3r(IMe_(LWtv$I>-CPD61O%94j3)>| za$_-AQo#<6(@iG`oHW*yPTFq5FD8geaATY?W_`$tbUwu+asffaFC>V3=pP=>jhj&D z6@-Jnk|63^MG*1T1VO)yAmaHh62xCcc!}6Wg7`YZVR^TPAoyG-@DC6~{tpYho*?Sk zL=YB~%>+TeS>Rg;g1$rG*AqlJHxPsnZX^i$n+ZaWw-7}9tpt(pqXZFuCqZ<~T?A3y zy#yiDj}ZjFhX|tHpCAbOg9NeV=23#vaOgHc2ru3-K^8SAmLEjV#{~L*IJ|hjQyma` z@e5?%aA)dWp1V`-aqn{Nk*>Dob`1=qc$vRGDD%-`G@~iQVJ^)Pspd55^@>+y@8E*T z66`boF1vej%pq=P_f4*cjpExDJ~S%bDsyTQ&0K1hbBr*X$`<>4Fes-}JkqZK99Bss zF-wBrW0r(r&P$5XF?M(S(C{qh-GGIMk54pb7}fT00p-T5wiFOn2`Yx%Kx5)DXM6%O zOBx%qBq<=hBt<~wDA`U|O!6?Zq~NHGJH2t5+R9Zle!p_hfVgm(tg z^;u%KGl;L*852ZjppYwVR(zs|nS0TWIAY33_6FAG!FprZMSUrDQL;PqqLl6!c2Qr6 zT@+S!-Wz&R7}C5qkRESuKwzRbU>V7$1_~L*)JW%3BY()wz>ROP&KPz{lVg@7`$8{C z>5FokBMei+Y}3^9Obxv(Woit&tWEKk6>rCr-Lp9jar5OJj|L5+JIrZ#^^n~$MeBH_ zJBB?q9*sRUWY1s7q6S%8Y!nr5XGCY=RM8n|Plde^yV~J-9XD}vJ>M3yKjf;Y3rV?0 z1?(4wHP|fd7qPp9(}c+Al|+H zFG0L}ofY^5yzgzqhK-8>DSt6Rv!jKn>KH zu>x9c)*#N9z%%fKH|n zF0WVNTCLx&K=&jOXrUgsO1E=bY~TN_pyPcl@_z$#Bv-00?|VR+I=A4b()|bMUP1vx zC*z4uFZUq`l%|><^m31ZPL|8Z7Ba-**8{p0Iy2xpzd19a{P3E~Lo9xmgU$}WJqo|9 zA^05x9rckO^!mM}@T0|x0@d#U{M3H?f1tzk8xVB5u^6O*0aT2A3URW3DEV5@Q90Ca za`?w8x85edCqY*z_~G4#hgkexw#jb}|%S?oyKCVhYcezMcfiC9`(8+Nn5B2;Wtg;r_1js=og;@N4W0T)Z+ZaD@_Q6?cE;bEpp*5((+Ur<+M9w$2Rr;~KqvVX4Z*J+bauwy zR}_AD>Ke3uzp%+~DugEMC!Z;(y?TGtfX+^T+zC3_9}9-4-$S6YBflRj^(z~K-&xRA zigXp|^P>U}H?qBphv3%&Iy?NnpzxFT;aKu}9dvf&mxVzm<#)vp^~(ocwc1c|t+#h0 z=wy4#hv0V~=nNbDURU_Z{)^S#_dvHI2ESIsr77`C@rW+lE60B5cHoK1jyjen?mh?I765x+3>GLh=^I4Sz_p%iVPIGn*aGGgm@Ujm8|ANA=L7{g+ zyL>(HLvBg$Vd{=<7kn1(M*4oGz56WruVhaGe_Tob9PnLo2|@pS1^9R5(gXY(mi$+< ze+T|KCI9P|^m_Ii3m#;>z;9Og)9!E?Tx=5?5os&+R|}g2{Ig2=^ua|27u&*0f&Yt= zez_(6dbR@izbfhUp+*K5+rdBfMDdTX8!YK*>>dS|Yvkued*u%Mf6{Q8V-#fiXbpcx z)JLY@BIF_Qe-dR%{D6i(tld8zA0MRHqY9n{{EG@s z=|?pDn1)9_oq(3;Q!#dTqy0X}h&%|)0bYanmw38|EeAdwX<>{LN)G{l4(*fa4*~x! z>RTrA9|lf!atr*Az`u;&9|XT~LN=MevuLJOE?(c**w{Iz^Ts({?d`3d>l=bw8`|6F zz#BSTj!ADlJyO=D{xLzOL%={U{2-AYnQF5T3%aMSywbCu=2XKX7c*B7X7@O z_41T@?p1(q8eBiX*l!Sz1C?Fjs&K=m^SB#OjRr-I`lgNbTbg&o*cvVgVEuZHNS4kB zE{wYZf7D%pb=!U9h&Ig;fpiLBJ!Q==eF?;HM1Xz$F?VBAl&~Tx4aqC{mDBIQ}AQMg2vRA31(dTHr5|95nY2erhV0 zZ?VQo=RoOJ4-AXQ14Dg1_v%yM7}`?5G1$^-iP*F)7?w^N%wq| zp{g!WQ(sZN2F@C~n!|0u*7^oG=GfB6x2UtN&0AwSY#buB zY2y%y@&v$&)=llvob;WisA#2^z24S{!wV>8^_?mtqhN7gE=$c@-1xyvk z53)Fjw|G8Y;Fng^`6^bfS?a5tS2=sOud;n>M@wsS*mq6Y+|r`C{<+2e;(6DW6#F)| zhkfwK#O743tf~%NU30nLH>aw;Zf$ivzgoF;RiL`Gg02&>&~Mz@*#gfiTzgf&wSGSS z`QzSYU5$f);@v2nJclrO4j~>N<_&y47<3nOYxJm}ct>5*lS9&zLtD_+HZb!cGVb+F zc?ON2NAes(ZS!NC^FF%sF@6TM!EkUZJuhv-6UmNv`!wmvA+mWt>B%AK$ssZrlAaur zo*a^%9Fm?K)Wd&Ulb#&HvHc)MpJx*CETKKpB*be?bK|yfb7lKB`l6JWlM3qr%kkGL zc@Ckim%XGXhh}(7fE9OZ3x+Pfg?2#aVa9C3r_q*8ZOu*f!A9;#Va^=$gDe~?2!AYt z`&N)@j(Oy*LG_KOz8c2%q8G&;X>{Ri_Z*Z$(!5zjB3(*Glt zU*7knZ0yai38pS^1b&ny4n6a1G8RbK6dg>$GZM}-v|4Bnaj$T^!t3} zdG5l$yyiIYu6LbL&Uugri2HJz@~~^YcyHjB+{*#&ey4c9k<~*x+C69PAa4mp=H7lv zUD~^DHFm~dzdILu+_?vbOzi6i-3`@!`!}$6b2fI=P%CJ!|EX2?9NKC8wBN_}7~>7c zo=1(By^aUULlq(K?($wo{!z9o;C)T*oUiEpoj;ZK*x&EYH){wfqY07lQd;PF|75eK6@4c%$zQ;W@QP8yPpv#~oXxz$aPfY*w)=*>ubmt_^`ck( zjv~))@5}u#59 zKg=zdyu9y=lhB(bu7{kDfWt@j2fW>`17@kt{Z~#LaWd8M_;JcPzuUdP%2;*Ek;YDs zPWOD${rH>xIXm6FH5YZKopz)>e{$l~i(g%JA}w>L*L!lO^O@7|6!0iJz#JUsvLjBv z$|dpCCn^PwK4BTl9{e3kCw)H*o|78&pTzQiatD&W0=^8YZG{yO&~ zf3Upw$8}dubiA8;BV-*W&l26a>>}b+gVQv7e(!=858`$9IQ7C0;oXErw&_R3ZEV;) z(s1t0-@GJL9&+qv57g}T8utVWkCYil^LBb2d+B^nD$66hQ3QI=D>;L{+Zq{@sYuNi;Qx3rYM(wN76y*$8T|<_i6ZMaUWy8 zw{pwjnPgrMd(^p~A)gmxcwe}VJu`v) zn`HDj4?29`dW(6e7DPiHC{SL}BE$4QGUu)LYRH#NhC$wBNCt=C#p6(a#@0*L~)RD#&5+b>vlKaV=y( zxmWZZ^U+*z2yZYYQU>IWhGf8fuei_byPg${>miRalq)@VS?@(_k+19N39JBKIyf)# zCS$gg&Su?rJ$aKE(c?f{pZB7*ZndSejKhC;@1EzqMOb^#dYsa#dscxAmZun@&8YJt zq%LyooxS}afex-W@7j?783yr?KFLN1T zZ5rY1UfP>el!YFo{-gXq%>6)Q+%Bme(QVQO`q~&tlvHIE^<5w?w2|r$T7?n@!Iapg_)OO7N1N_|LvE}_4KDg zMoS^1I%BE0L*18qUG?v}sq`z;?p$yiU!@mvA3`Hobr0K*TBZhi?_A3Y=O3fHz3a2Q zjl9j0qYoTipHn%ec7Hl|YhLQRV>e!B5H}yqIDT*58%XPhCD1dqhB-d(%dP4AnlF{h z-*fs-_)6lv(DUhB%Dr$Rn~9u!-5|N79yBGh$oN#iag1t`#_!MAE9Y{jcv8J-=_4{m zjvAerH6}Y}?6~n0awks8n>=MIEOrnaaPv`Px>W&2j${-cH|Dj=;%CNmNrNcvy@mr% zxsz%CDG^Z|kPjOVb^vPs5$jf?h!!{jvy5`Z5svCr$4p(qQ-y;Zg_6e%V65jJ2%8Ca-7+3L4i`;N6UDzfA$)I@r8A%XUS7hNu zrlx#PRjuiGgf=^p1uD6;;d^#qV9fg#CRsj;2i**UIbyFLaBNQ?V^Q<0X2j1SypB7d z;qfJeW5W~QldxKx)r@kujXm;RN$KDdAh=xEa-;kugroeW1Yy>?j3Dx_B8Ys*!Z&;& zipO6=FyB13j85rXPdLh<{SQRnKoG>u1i>Uk5an$li1JzqPG@W@!K-1_MiBY85k$W2 z1d;C}1d;D%f-{8I9njxFILi4b!Ha~~9aM6+!1oXYpZf*Ammuo-u)rT72tJPr{4s)% z)VmSZLO!bWx?^pdj4~LW^Miyo8Hlts2;3wsF=bqTCux~p+YUR=TU_1+ z=^V4Td(PiELlhTp=S0`e$zmL%5S`gjGe*5z(o@9%A2QBcg`d7@q5$L=P67N8nokLH zvjY{NtUM7Hh6RE>mYH&UgNs%(b7XC?t}eurmk3^b63)>28Bc*Ncm9EjEigeE!AkLKgS4go>lrOdG59>k%J0S=?;=3~_KK?Q}?fmeO@;0whSHpey`!I`Bk zjOhqY4sE?8WoVb%EGgnAasGL3OL|$#$R4%~mk%mKIoR~ll))Bn_eUQMFA?33LUd+B zJ$ei9gZpp_poK;Tn$fZNS7hJFJG)pE z;g6%UpC0_R9M$D(2|lM`S&6=pDf3|1W9xS3d8geF#pwbZes`lQcyFK(18uT#kEhr2 z$ouO(j`Q9$^y;sP-ZX|GEpz34^8B4M|AKUmS=`?eDlXp6iLQwYMCYJQI-N;*L#g%tp+{4S>XVuYivcMEutXg8z2} z{4K%dVB$3C(+Pquk073Iq3+`KFaYPdpb7xQxen|aim!!F8-nF6K7P5CoqFfwvL_pSuZG zfgd2%?^VJvb>Ab1-x$PEJ@8h`^A{4VhL>Z4$loCFE`pHncL*Zi4+x?@CkTSBpCIa# znF>hqB50sL2-aYn5JbIqig>7Cc|7;zfpPFH;8eet0Ou`3e*hK%dcB|n|2%@=UrZ4E z4T4LczaqGju{MH8zmp)+pCyR$dH{*v?*WNlFU3Re0ab3yfE0$J(OaP7ni8%qM2q=) zgc@@HNg(0sKXBtJgEWE@c^1@FxIfJo>c;6p-8jQs(nu{fn&@Y9R$T2w(~Q(fV+a-s zb)=sc!PP!vDIUuQ9(%+IA9N87H0@&r%oejPB9Z8NV-Su&97cR3%tXcxG@9f<(xQ-w zUp9VRHWY#I2n4c{3&+Ie-$}TjvSs)!3Yf$jA!AHf0HD&H^VxHsIwK!LmnoPy|~UZdNNF@RNa zKxjn_A5$Xbt75EBJE^ZIP#tf^h%OyJ3Ph)un=#K`xl2Gtav^^7tVAIe zzw2!Bdr09YM6i9x0{YsFyili2&@w?t(muJ!uCFJGj+6+`eV1Rb982Lzp8o5HVh2!4-%&dzv#Q{gA&9jm=5 zctx?p?<&w0qFzq?Bz-J?T{ii>pzvEdM0w39{z>5%6g08M z-+1ivZe_U3OR=p?^pgc+ep?iN`h0r~bawjVH=vX9+d2fl5twXt_|<_< z@@rT4>HTpN=pp)|3F$BLR&|N3eRiKaOZz%jeqVW4Vu3d`T z^#2%y-}gbM_D2D3(l0s9=M9g-uN&76ffM*6I%B+o%gbNkLgnXL0w=_X150+BAfoDMDU{_bTrD0oFbEioo%OnOD#_RcK zAc|;llfi}E zEEfUCw+InZ**r`7Xm$nga+wT%h9y0VT@8G*lKvq}dNymd;9ho%g43;bC-4g7zZkzU z;QvM7GjL5G4GAZ&=k($!aR){!E#wlP3mhc;6lOq%0^m1y=k+F1(tFechU8}EK z@)8`w!)v6f_0k`#v8}C<+B76_OIu5qEke`7t1Z&b=GKjv%R}*P3^&8GY^2Uf$FH$n z*R&=bza|~OCLO=t5VYxrbjj9WW4z8LTUP|TLh)yA-r63H+tFofZLq1SrEOE(#n*0$ zzumRr1PV?%evP}+;FqkjHr!krZYOU^?csPkAAFLIUt`}tAsVZHv^YK5MxCP#p8=d% zZEbIhw{y*s6Pe!RcRm5PaQq1*!Tj`8onR#r%3jHjYDh#1CWnOEfrGG{6RAeh@oUoY zYtr#+(($XsLt@hLYtr#+A~zN8T7J#elK6Ot$D0J65F)Pahsk3&k76<1wt~UD#107h zJLM*SsQeftcvJ;!>+;Qk7uHpwo8Wl$#$dP&Z;qYy!EkeZb2!`{?nG=;OK?+t=e7>G zRqgD&ytdiD07oIsY3$f`IUYgq^>NOMl9IXb;@Z^Nf%xV&(6?O^e2dCVnE2 z;-w<{);r}UL}=__XULo>A{~%)7i68!m3h#-L4(1q zK_(I$Ybt5&R+00jdM)$<#^g0Z@Iw8E!%Gz%>4Q|!jT9_V-f&pP ztlntB3vGYDwmYHr%!&5638MQTRpvyuQGJ}~E@-XzHY4hG+GZrTmEelJeNhbMq3kpY z_<%uPK1!&|v_L%emA2XtEnwo zm;{`UY!Uwo8Zs5l)&ortmF|xi)-!b?;C?|TiyDJrPkCkFassjlKjO#b1h@cn+W}>e z`L9HTTJFDqPVyjHc}*riD&4c7n@R*)s0Xgnb%U-_qam~vKUMvn13^i119USFG*oWE zPo*mWT`l6M{xY8E^m4mE2aB}2g&$_up!_oO?8#*n=%ie- zhTvBZIy>!sRN*IA8EP+?v0yxRh$7hMK^M!c<4F)mxf87m77RW>>JK^Ah~F3SQ|YFI zPPT)u>_{g%GXGG=O9|*?I+7ycySP&MEe2g7;;7sSf{OUTT4Q0X)9V)?GM2T*!udF= zl85tKYtR@)h*)ckrkW4iTEn!KkoFT+#qs-Pt-;IWl~@0$a(A=S=bk}gH171dBMLE{ z8~;5Eo^E<@jKp~?>nT}e{5q0G7pbNPM-k^j@Aq5Mz5E<|8AWR?t-UhP*q@@{ls;d> zYc;$9I7N-YA39h1AJ`&79!VaN595KWYMhgRv>Q&Bzs2}=d-sEAj{LJwICu$^Z3X(PjNt=SC zO+j;ObFi~{@B@SsQ934V3gXxJu1&xmBWY7G=y--`tjDem=lij8B306+pt3b-Q_z~U zDcH(2(be07TRU14vTC4{>f=*BnN^6MbU#cDk}|7X>9G3*vaf*QVPe@6HZI}Dj|tTQ z_K%6=H%%ZD;2^Ca6JY^E$V9T!y*GjU!W=ST4hav2y3SxC?MT`bBy9>389zyz0y}Tm zF|87kHU(s5@LznGY(4*03WEn2P~iAlew?lOHLa~BtbaOaZ`j=2*wtw<%2Ga4!p5Yv zV(^o1&!4+J{>V2+KDQe#F7B)z!U+{1fKm$hrkbd#_%N!|E2S zI>pj<1zg=v_g%eho-qRl#H9xL@rGu4=}X40KtZ>|M~A#s_m&l}$VJY&y@4q>ezmj& z*K79k>&yJa5y!T6FYoIuqC*X9a@mY(xIdi2k9jmxQ;wya*}IA2-8jCn%%I~}-Omv3 zWqlvbTtSCgA|GrT8rTffuDBXU8G0Y1_AW9W5=YIY(@}HxNX-GP7~Juml{Ql{5n2Q~ z14VQBzXaYxZ^_TQ8U+2IxqCBm?Oi zDJ;Z~q9y(V=m4c4qD7-odovvU1G3ZDRdeHUUzX#nlIuYS?XIvfvfaBwSj>Bri0Z)%Py zKZrK9v~6sU?$?jR@TRMOl);NpdHUREkr<6TeeRnIF==^8(=LMxefgS1IP~!I`reMj zdH9MUQ5V*=(-Hxsef92WVZgIlwgpdR1qv>8|7QdbC+b7{@?{{cZ<&H;0bi!zlpfab zPiQ#ptCxZ3k7)R78h#u&MNymo!L`V>;i{I-U_)zj({Pl?i=w;ZOUwbTj6{F&z$j3u z6a%)ulOmeg);OzAK5|=n{WZ#+Wf+R6 zwDQep@n)u-XmRHipN!+p&%YNZlG*&a7B2_-QXFqy`b?Za-oz@N+#SDk(06#e=f}2| zNoul_nr!|R1$tl88ZF)l3uTPF8++WVNK%vC(JA(TM)r=yyQn5L*-1^d z7)wb_w%A&pkOmb`I0-8+lbY=9m91ocmw+CbKer^1KdH%%++?^xUi_lO?b_<+Cm~jv ztDl5;iRYPwcxaC_3GuSp=Ox6->h>poR#DGCaq&p*j(`94;K|+b;YRTYqkis;eo_1% zx;;MnJ=(q=`!B1Yw;pjj>9I%r0$ao$I5f`4+#3!R8PNJ}{zM46XD>9rix-9Pw~REy zBaJZ!ij5@(U0;>!KJ!G?#8Nh+wt8;&4&cTmjyPoxnYia|L}E87W6;(>o5~!d>xHs>l*5@Z659e( z9jVS#S84_hG++*g&%s7IN1r>(oOMOcI={27*jZQNtSfca&3D!34~OI;2@c^$cUeX=~qx@A<}K+zxz*Gp5|o%ln$&7Ihr zN^PQ@>(dFMEyFIYGm+Bt5n%VATT=R#bImULu#~EfCcR&q{<+lwl#F;<^B?M*knB*T&vN&3%XdA z08OA%EdkajJL6?M<|^B!(KUjO_)+~SodUt#_^I`K0d#y>Ap#}nbUy)IKuMRE2XP_m zL2}mW{-7Q7G=8amWNkx%_Trd*zpKJT+n^ zQO0pE`?8=f=Xe_XW0W~YgNL0_aOz(xo~q$q4NueXbPXTD-c|UM6^WI921~)PqPCeK zgN>kJCIVTROjdAOpM45W4<}b?_(wGSX$7a*^@fJ$DYpztU#H;2f49JWxXyxnzAtdx zynv$@Di^PBY;5eD(|O~ZuJ-oU&h-t!tqtw%b8sd{Ti5#STU+PQAs*|wh6}#I!s{yo zb1GL}yKGI>^4hw}x}rIOmDjB`lh+S4a9uBzW9vJ^jqCZQne_tF_z|ceK*J(0KF8 zO`-ATPdc_xw}>Upf#hq2;-O0D%isK4}h=GzT(ALc(Se zktde8YzWLsB+Y@u%XQMR#a3yVghz;^Inb7R91}dGCp(BKX%5uZn3!V;Jd!03%lL16 zScd$N82#S(KhrEIMmz1A2SJ-+31_A;cJpc&1_T)U*R@bA{{9mms=eb#^@A_|?ZIz3 zJq3T-b;HIVeEaP8FW>UY!q$Jia`c3wH{aTK`eE^((Jj68MjeUrDd~W8O{M z9;q4g;G(9-@XI4|L)O(;2ketI&R|V9qh}W z{@}Uh9iPAaNcI=pqaOeIBUerT^{qcx^P}JIdE;M}*43wj`fj97sxq-fo^5z7rR2zA4a&w=I`GE-hs z$59|vBDGlMcN0{8r_=}{L?96fQFDAV+UmDqxbY}5&g40)fBb@<)G)pXI-f!!L^a^3 zhhKwki4D40FaRL6t_*|m3xcj(5&;fI_ax|~K?IQxM)yU~MOCze(;Wt#><5+KA|R@q zyFn+*Qt6gzbYvJ2D|`Tv=*|wAMs%?Z8CpP~8XnAn5r7YI)IaEI9%!uUbSprI;mqmC z(1}7Ux@Lur#wLYWbhjvUQr<+D4vUAf(pVM`gZau>u*h%M;^F_Z_a%T)RagIa-b`jD z3n46Of`Ai13~FE|37d7vG8sSxLO?}J9VW?yiDokkVwbN0H>j-*ZcTt%YHR=2+7`8T z)eo$#U9CjzSGCo~ZYud~NzgQHt^9xIzISKtdzmC}W~kME@50M@=iYPAUEebA{O-A# zKv^I}5f91v$`FW$sE3N+*7|TT5)Rdc+fIbfjB$_>WKB)UAI6u^{MfV`JpL%}5cQAI z9|lc`pXt(F>=_-OF>2R?KOlWhRK~^rH+oLfa}wY6fNtAra4~zVGDx4yz0bsMb1pVR zmp+9p0RLT)9dJsYE`1s+)$wk&PU2}IZjkt?(DNycpNDfoGW-lY44TZ3V=D9?1Anc= z6Y}DF;0Yc{>8rq#3TiX)9pLBUoNf)ozlV_!!n{1T_Y8w&pXU2gy*CVXM+Qm=mgrO9 zHiJhm)<=Wo(T1HJpq57))Q@tu!MAtNes_nO>sp$~KHeUbEbRh75a?{K?PzFe{#Tmb zMGpqahlVIHj@3LWr$P|SND7}DwR)^r=Ia$-1WwST^{Y>t2X+>7jU2oa!ji0%boW%GLoZ2+DZ1$GT z9vEmD#=)JC@z>&1jP91rUj3CpZpBhCl3F%<%Vw`mB+F)B(P+8w5Qg$b%Y{dr2RFY` zM!(V|fB%Ip%Y{ds1ZPz5MNw2@f<2qaTW;K~BrKbKu&(`mY_k_1GXFCz_0iTPYoC7+ z*0-N-!dCGc7<=dfO;3i7g3AyDR_DF6zgguh`D1e=nt3@O?xx#GCE%z|iz?#hc zbR<$mVV0zLx=1^rwXB2x6BLBlW}0Aspp1ScQ{I+!Ui(NT>EkiorRXpS&2Avkma zG7hAW=M6qrAj>BR)!Y!M0r3J&EExtta=(ZpNVaU)_M$;S#%>&xmkfy%Xp+#F$og(W zraf{-5=5Y$;FFqjjGc`J%#vq`7C+A*w+b_QzLq8vBhI1)a+FsD-cMiz?tu3b_}d}( zV<7}8s%qTI`_B0o(bW4UvHi#QkY#$YV>O2~>-0J+t|CLgm8ASc6E~-{fU2o$k=Y{}Yrh2f>ryA&hjCFVmFK zt;|OFikNatODFq?j?ZMDka(JSgztzw4V>&wDcz2gFM`Jvrv)c_K$o7wz6btHkqmuL z=+dXMXTWcZ#yQ!G(Q~?Nrn5J6Jnrw}{tBITJOn0#zac8))cI1fvwSvRlBWyhY>Bty zg4d_J*hLw4K+y!t+OKP_ z)jE{YFAD+H)6y30Pu2wQFk$_sI_ju2)kQnk!qr%~8ofPEUBAjFO41g0Yipe35GIx{ z49gcrb7+0t#B1_|aVn8-+!n4zb@L1}i{7DplAQ=WhUKHlE3$Ak@t?!djnEVCTFVzk zo%$3{&}=5(CM;Zy`m@Qx)o@@8y`Q8on`rmG)Uu~Mp{=cPtgUgPs1^bSr!XIdKd%&2 zShyMsS5uta9MoQKQkZ-eu4c5a=0&6CV?$%O%~M#|4%*z|DGYlG*G4{!h-*V_*o=Bh zdoa`%4u;#>;3XNcbq%2{!S>EpsA+FMuPW?Y;zMk0Yv*~Rmi!|=+zk2V^BNmEIvSz4 zupV;FEzNY=5$SBIp{)3Z2h!XUgjBdK)EI1qhiWyZvpLk*u%#I;l0&t%C=ao4F^@PN#K69y`7Ah=a}NC8QrtA4qcn@1wBO(T1YRBMQswXZcExqkq1_JZ#bQgSG(6cYcR?R{NV~ESf=m$a8wpV|Lpf^qGBTWO?8oZDSrg z-d_D=LSU6|K$#SKVE%Vt<5Dhv;k=fL|?RtOZuNU&E5~EP|X)=UrMv3@xN$ zhWKBHS7FirB;nrD38@B-C;MQiK zEqH#I_PKQ*iDa%KTO_xB!{klg4%lfLbSNLKCVmdKF(C@WFiy#aMW@_EPIad(ffh)7 zN^L;}d0SBDl=}r8#C4&uiRj{OqV^z=2{$lp>*%e6DyDTP`?Ot^V0+}{pdYFKZ0JXf z#=mO!BMemqm4eaK##y6$%;m`EW;~U(QP1E8hn~03I>(iqcI~0YCzi_ z(I6{GPq?_(Q!36lR%Z7dfS^s~h&0nx*eEKScUA3#J%#Ch0(wd0q z)HuZ@+f!71wWokF<5L%fq=<4OH$NQZhECVH86qUXA`c)WpkB~M&&kaqFU>;MRx#98KvairGxl zgHVo(dn%7a&u>;IAyz*LvMt}*E&?t;;K$}mEQ}1~OxfW!cuUEx6 zpC+eu9lH~9w^8G?AgZtwJVgus42%_(Ap(sD1*67$z>g?Rn^c~AUZyo~+)GUUWOplh2#y!QUt6Mxq-V|z>TW9`M1po#5yg`nQ3^y~!XdZUt;tck90tJ1^~-^r7jdNT3{8;q z0pnSsZENPC;9Ii1WJ!^?c*z((!ImyvzJv>UCdPPvQJqLpjOSFUd6F1UJoMiMUtlU~ zli*eLZJ{j<&GjuY$Y(T0>%AC}$Ak7%yA4UPxWVK1X*}Iu2?_XQEGy=klRc&5)7h^j zo@Ud_;KjX}_&-VMe2+67?_$na;Ye|@bcv^XsOU|Ty2(?e&!TPpv__CI^y7pk})wP!aE=+^1$Lay-1~@SX-@(b2 z1eC*`TZY}XmL`OWBR4idGFEnWh|SMbD>@=uuMIc5RflI=NiftfNc z$O5`qKsWr95H@fN=*HhwQUI4&4x}sxQql!w0o_Ici?n+U-XN+%ZK0-B%^l$_Z4Di% zAZ($_av)_nkZRi+;;V?vZ#YGt(f;oN-2ne3Z=@Q)E&AmXFgjeUz|e6_-I%{vTWYQX z#;#rG%#?m9dI}rM#)jREovS7BOop19g{B!KuC%-0{;6W>og0fCpP3!#4#2!}`qX|$@6?{3 z!`fKBM#&WS^PkZdG~~WR&CY z_Ex2rd7f%@ec840J8d;?(&};Zo*I>^Pmh{WnH@FAk4-(Zx`ZP6gkS0F~NUq9q%+>GHeM96Z(kc)@EsDqqrmo0*m zDC#fjQxT7e$2uh*r>q=urJy87=@f_>%iRIFc=l>zxi3oPVyf{#`gY;K5RfUGha-@? zR4@|l#kr_2MVDeAt3auK{3-?|eP6&K_e(eAMBgGQ8Xm-%tnUuUiGCqUf%L&%4VZc? zOlYt6EjGP}RSU)pA!@JAp_(UbuNK~jqPFCB!EP z_ydwO*`yzlcpA~~NxU8R=kM$I432Y%MY;GrOYr1P=Z}Kn)XiR#c)F{*w93#}({538 zkE5uqIR3r6J&m$CuW6}lt{u;Pjpj{diEyq$Gr_R^lDfN-9@HT1z=R#3gR7caTiQCx z8@5#Pl@}XY5Gh%T=`&(*J(g5pizc-`Qev}+vV5k*U#o5HMP%(oWbH+y{q~-4SM5f= z6ggR=hh<8(Ov#B}Yy2B*k`oSJ7A>DCW14{VA6=90V#}1=*q+>KX!T1Ne*;OuXl0p_ zC6f(z;+8^ZT0T=OpDEgQO4v6sg^6UDk}XrRbYHSe$(AYE@|iO3&&;^H8JXUHHMQK9 zDY+3=;OGa$)SRUJyUfYr^QUPqD4!(TiWHVT;t1@=UOweB@7WA9hr z{Z7QkQ}YI!wV83>Ci^4URjADE zb3a%*d;jK(hc;{`uOq95_slEHWpiL^omUR;BPEYf1;{@~j*^fSlUqKu%G0-T{cbm~ zypZ8;)b>8G@NlCHRt%@O03T+Vv9_5ZGm?To7lLMpwaGXaAraH#w?!t28cmP?i?qWy z$n+?RBlCgL^!O<32+K6{0+OSFnj%NP3ER~hCQOg7oHD-YkxXC|TrfQf(-rZ;?6n-{ zRIV_SodP);N)bf<3lJgK?^BQyI!IQWuQkZ+h8#DblaLgQOJ#c?S1F~7(?*=grnr|N zN9~|`iGC(i+{X-ZZ$J+Jxtz#Pa=UTJCdD+E*{(pGF?=2oA|Is%AxHVCT+vs=e-(!; zw?&c@?ItI}x zc+c4iFAcXf)L%E|8r2hHD^x$~Rc_N+3u07YK8F7S5I_SLoLd(8d_FEYo~?i z3JY38n)ISRYXPdY05uVpmQ`)dTaun^+BV=xT6MII8q@`9N$bGxz-03ZFU85`x2%RT z!h7^;jU@YZ)KZP)^;lLz%W9}Pvq;6tBD=##!B}Hi4P!4SDRiT?0M%N6TG7bgTT+-s z+N(>-8d6?fZ|$@YGhpJ$Z`d{}`SF3Sl&#~VUujaRj~)w^k}Ca+P4cQ5qs}#w(qZki zU= z+(^!$FT-}YAn=SEOHn&t+5D?nSc=-2cH}c@pKoZ+%^KKldv0Xrp)ZB%E0-Ot53qti zg>nzF1Mp0<1!fc-8oob&XSw^Z@)oP6MWD*y4K`W^`sQQ%8}6eew5L~|x<7JnNVQ8ULwDDd z4`*&Bi7A0Mqt?jW#H^935k&13`ubir?ZY>u-RQW~ zTD)ltMvLS-FnyV^NDi2^NKVl#d7@llL0paqs*bR-6o4av~Tll7ENXDv>BrqeZd;^UjP#ay{grazcyb)sQn|k^CX#%vdC!lH^3Y zHH+j@@8a0v#i+O4u`H6yi%U$eUYzCOJr=b{&ZHsz4_&?Zc{DY4{R|%e7H_)hsoREW zEIjIxHQ$D*_j_HsoBd74r!!$u^ld+S;_O zsj;vw)Dham&4$=mt8G(7d11wx%Pw5+zo@FZqS{+nzGmYFHF?u$YrrOflH}fv36<8q zDe5o7;PDt1-FDwr-(q#mXRsYBK*uyLM|A{S8tT?ZLPf!%q7upA8;xDOBu;GcvUswK z;R{)(cSESAF-%KcY5nTLVt7hcS0np;(X&__+$w9SC90!k-(tO^Whj9QX8pogAFZTi z!JxWfSZ(C$V11~eQ5UhLGt^e6)r&rA18zDsC-CPGUW=1uJMydd6C?0t;5KzV7Pr+$3n<-IKj1Mz=Rk zRsnW`O~s&YEk^FdUh@{LKzg}IWje)PPLeWWsXs3*Sb+sAuwVtk%e#O^rf@-7i;=}= zHg3t3eoa}h0&}l7DNMfT8%}~c5_uttYu1MX^S-6yYOod~7dE#9JDWp|_|_b*3x;aB zv+2S@^?NLwPj|q%bVEz?*iNCxy6|ZEu>n>P_xtwy(am+dhL{B#cniIgoaviyT4@X0 z9f~83Ic74iPmaTG;|>q=mdSBg_UrI6?>afoj<{03B$n(Ov^182k^Z_$jTe6tFJPCl!3?X)g!)~ zU_{x=c25e}_Iz-Lt#{81W$)^|XJ%(E{t93el|v)msn4bb?rV5?=2;Ejbo+8?dA7ZK zpyA7*UZm#*UJu!OVvDpZhkk9lw*RG(s{JhA)@tvy&1C~h`bDkEUU=?4bUc6W?5shB zk&kOOCwJzv7Ce8Ap#R8~tU0d(S+r&vC!) zwv52sKu#|l5qCT8D2RIEep>UyeNx{^`;@)*UJrCp3HLQTop*p>7xQmAb#ng|XQuVp z_NpmQ=e_=_YjAre_tbp`0WfCve=VdSC*^xO59P9Z3ug9}58q$K^0zO&U`EC8vpFB1 zLCeV5fGZPA$>*>$$Y=Ko`0T!%e4#68`>0Q+MfR1a_hs}m4|HUFckqhIFZY!VwdDVX z`}KCoe!bI56(;{Lz{s0*>P@mDkb$gx+SbvIv;)&xm7i&jv`^MBAY$!0D7XJX5l0-r z#V}vb>(Ly3=W7nX=V%VU=cc@B9rpP6+r|@OA-Zil7%~{s>Una>P1qHl4hGBGnS%Oq zewKm9R@S=o)Aalzz&hN>?**m4TLehJLgGOm0Htl`e?S!N9wO?|wx0)IfR3X008#YA zM?p#74p7p!pW@Mf#z2^xcmd*ky}U>xxo-<`R(E{Cu ziVggQ2EIY#>DDj>c(vU+-p#(F+f*9$98BJKZ7*5buC~!bZxd@ z*WM9sYM(c+sim$H_#yS1ZvuO@`-(YINWHdbH+Bhnv`nCkmWvagSKHU!;D;akzw_ibx*O8wDq1R|+}9Gnn}6kl#M7%8q?95_;3x%hx2Rn)>FSy&`&rzU*^)>;1& z`Rb_C(b5)98fHLFh?6b2a$BgWwK4g!>28&D;W2Yxvemb+NC_{<($-QY+v8QCy1IrG zJdNP7p7eaNut*jbN&mW$>{J@{Vv>R){bJxGuPanYzY;h}J+WoLi7UVZsi`IT85XtF zC0?@n=4)Y*w0DVAAT$;h$-*KD><7@+Dq=c8+qwK^%0bg9Nmspr=t_Y_jj`hq#X^PAoNQ9x*6L;tt$#&e|yEw13iJ0_PPS+H9S9S?UBP7-)_hl zw5PLyUI)29adkf$`e(xfK;@hrcst~hP&ws8ldrkB-?fi~ySVccUm$~UF*mP0(ra55c<0s0XTXFag+zJEO4~Xx8~)l?Dop)PQ8+6=s#%zg zF#D25vW_6N@4u%U>SCq3M5$h^R4-AgmnzlE zlVjLyB4-_=8j5MLI@R$A|5EbXqljmkSnOm{LdU?>6J=NF(o)1-~ zj#bcM+_;KfgtHZ!%s5JJ=C-*Nx83b4+h4a4+dKFuiFcR=BI+Orb$eF#d*v$9SQ=w6G2c2tynjbIF{NQ=DM3Q?aj-U}7RfLSC zD4g=r{HA~@KMEYx27$S90bG(XBRJ|#%(%Z{n2cc_BBFB`=eJG(j^cL&$bAEHvIU>_ z6XKU@`UL*~I-Ke)0`EUCM!82#%KhA=+;7H^y8va&?fqZKi8@go#rax;+)>C0kQ&K} z5X6bBk0#W)B2l7^IG4da0mxCmP(O)lims=R8RRa7T$LtA6PW_Z8O!|=H8KaF4tC(yBBg- z2u7km!nxdk$0U9HX^eELpHa^4iIq#~6ynKE^TgytIq~G?N^&v??OEs*`EbgLA?F39 z@fG(7()SV$d0y3e@GgTmV;De$tS{n;x!KCsgh?MTV@sCA!;E2<9Tgm={#{a1!ljBz ze8p`jq;xwT(y!?FN$gD>e+sjs@Jprq znX$^C{8?-U_Y+8Q8+fjH-YmeZM8ThXo_)`t}KW#|A%)o!vz+Z3R zw;1>z8TbW;@_uPZ|D%DQWRU-sA$_gH-zD`AJ#h~h_@@l~%Le{02Hq~cWs<&J1MfBP z7Z~{U20m=yZ!+*-G4M}FJbq`e-y3*`cy&V>r7tk>D-3*t#8Z2^4E*Q7(dhyF6ZDz4o!s1G$S+-{?v?7kdm?&f#sRuWlfF-fRRV* zovsyw<di$#%okmO=fBq1;*@g>oClp@716?K7|IXQlr zs0?tQx_D6={Q8&Umq+#J+v@X*dcv!moWWNVEkWO2Us1FOeT#j?QC0dj`-;KqUn&To zs(~fRk`@GBtG2`6u(hEsytYo40!ttEaSN`$rfqd+W5>ls)pE8qe&Dp^h;^eP)?Wix zcwwDN*Z@?ma?bUUhWZXfcQ$qke{%R#7_102)@ovct!Qa(m%Y)ENT9P-k{Wm8IZ~rq zAyzf%_NUv>f+S6g>is|1T)QINjE}t?0uW4S)vD+f#A~T!Phj7iVZ~@iZ_(V5>c~H;;7kHt!>pCEJSL2o0{bvuf_6?XL-jPcMtVZ zK#xQ$m2zf|@<=*!xT&Qrd7pw7BDFnP^dfhoknFGtG)J=eE$?{pGJ?_YjU@YZ6m}zd zJ$m3ql6qpOjl>mbkd4GM8t@v)DzFf#79v%HlZu5h2||D5ha_JslVbjq@tl@-JPVO( zAyO?wYPc~RY7Z|O%fVLk(}aac9jBLK?>0%@*0tB0r1Bcxa1zv!$P1B$Nc9n{6i8F- z`->0Qg{zB;7Xn^d*ZzJ&q(;AmzE9DpvHF`uqLOd9yAJFMyfDJ5T!BXhzi~nC!AAx! zx?ok`3nPvkcZ3zpKKR0jyVQfT3l6_9lI6|S;&L{7akdz7({Z-*ValaIHn*w(@e2;G zj@&!wVZSRl|6qOOOZ@D#XCkxL9y#Q0rN0@_y^R$p{q8}VyENw?eJFwR8H2VA;t%`R z9(mr8ea9CEOIhjA&hhJ8XAk-FIMw^-sPV9_a1^ z!g8R(k<&BZ&-U$l=+Nqhuz`I}$3Pc+=>2zSq~Ru@b)A8C;6pFxVd(Iu^<>;`zngsQvAxbgcV^~* z+qpHjBRBo7FZr_v-OkRu>32RBIX?o)!E}dn;6~@8oBtW{7Hg>A%}c(scIYT0k9L9K zXQl*xH|4hPAInsVy6pRYa4gf&(PiJG4CXlK{2N^vdnj!PG;QB>KgE@7r*mb%uOKC@ zbNl3dhd}4}N$#QTZ*6CLupOe~q9K-+<3|ef?&#QI>-iZ{u{mN|E{{8~19fIYJ9zr_ z={-bSLEUQV^}hgr^!n*NET2oI!Wt0`v+bNrS(qkVFP9CwVKNVVq9>Qvy=8_ z57V89ixxC+&GWHx_q*x3zT0;rrpp%&tR2Y3njPv64`Bk2C+Z8c~;6 z%H@2dXyhr5j$61UM{gO%>-A7pPnsd$WNlQb&uwLD-#yLa+@9Ca#*2rhvDZ=3=58KfA5peojo$=&~Z-ONz!`hT6w*ubp>D% zv?3w9%ciho4qCd=h!vR zq=1c-AOm>-uKh)!j!mMHQ!5Jmh|M5i-$HBrQ0LlmA{ z+cbU~QMBtiqPdKHm?-4Bh@w5)i2`-KgDB#65(O%Gm&SjZDB9mm6hPnIL?QPXq8`S2 zh=RYH=p4pAr}6g^oyXXhH2wji^BE)0g(UwlQOuHWXgsR+uU=r{R!7Io0+ZQdfywn5 z*`Co}a;eS)F~+!ace5BjrT{lasAdI?n@bew6`%q$DD~oxf~6(At58S+U6sYVs(0e9LO-2=uF{H|xU0q~ zF4?X^$7o$OS?ekkl0a8w^RD_^+JsjGrtb;pDz&)lC+@0oic7YusQT)xnxb_T3Q3@= zrt+@3bK+TrH;EI_Ra$Wqchxw>CEHa{sdd#ft*a1|Kv$^?NS~T`R^jF91ay^J-0KsM z%s9m*+g0vpS78|!zgMA<1iH$}XVt;<2`@mrcbG3p9m-Z`K~KdO0Gp^yZ+N`2$)o4Bj+&UFI1N-gf@ ziEl6C6qjsQ;c2dQ)hw;6P)Gt@r4I8iC+;fzQa=G*r55*9_k=h86It9X6OYU|#U(p3 zu}O?CLVOaVkc3C(TNB?JJtuHvemn6*IFZFYKJi2tr?}KdCSMyF6q3Nms6Tyv@0f5B za>t$TLjZ+<7TxPPQn zT(TE&>>I#b?IK2-61a%fC(-VSM+TpqPrya27WZIE#U33t`6Cw>y) zYy1i8s$Wff0~)8e)Vm618~)HnAqjLhl#>S_di6vjJ-+J2QN-UF`ij=&?0zKAqq>}bfOsVnM4=E4n=ecV?{*$ z*dmPRQrO3cqWp`AE`z;}=yLeDAc}fiK@|0kQ_;|`*z$3CK{$9|%y$D>3m82dTVQpTPkigvvSx@a|HFN1nPk5GI7dn6G>c{vVH z)OQ|H^j85<)OQ(C80*d@iu#rlh5QDhezZg5>p>T-fl(0D3))Qa(BDB6{qbR<(7%Hy z`r{^|(EmxI=fH>ux(JradqBOQU!r*Ae?UwBE>T!M4-rNA&lB}C_9rcVgeWYb?+`r~ z_P{hXy?`kAl|<3MYltF$9nlK7>LH4L+N#Ch0J`Wx7$ZTwpr538)Z;dy&~p#bG8hku zqWm8aJ)g0kf-brk^9j@o`W(e0--|?%?@vUl(BDMYqQ9M>F!I)b&PMtFMYJ47O`_0y zzec&w5w!c;#8)!*eWDnTexevB#@(2aD>Eq|nrwvl&kcp>5)`I+=E>4L_+)DaYy2*B zQ#w9j!brspy7U2p47sqxaKkOKa6|1RqBGU|5gBChO`RKJp@JJ==~^ViD^ziVE543$ zLn{$E(Cso_upyGySxY3jBXI<&UbsA?VKy>)(65x28^b}VPE@|E?|k&xBfK+^AO(Co zU{tmU$It8HIVzRP$tpK407%Q#x9rA#c3T*_*iQZA;?jGQN2Vw&52Hl$0@r8az92#ksPH{ zAi4{O+<(i@jPG5{D0d0u%1MbK>;W(8K}ny19F;@m^0^2auiVc;j{3?NjQairxdI50 zK0b#*%mq6x<9zxyC(W<35P)h}-xeW&2LX-40bkQ3uU*EWTC?Y#+dX4?A% zi>zSBdu<(caU?(bohyGwuC`r0)z#pRv8aft;E4=6Pf7T_EW*ws!&K%+#+Ha-zMs zM0toezC9-O{Z`V4DHhddY_AIs9y9IrLoNqe=>CT;;vruBHbBlyd-p<4v=^si>U+YZ zK6=j;`tYh7)n{yP5#-FYw*_*dy?9lQ>NAe-$028?y-!N@TRM)uKbzDCM@Z53;*~gB zKVy481UWP9-2*w%Uc5R+^%>iHKjh4`cTlRIC_mnO$-@hq8GV}}C&m}AO#l5|s-KXL zr*95^4~lfHSWb-ZLk*AHFX~`lg;^u6~z8 zPSo#1l0IYqZHJth{`+spiT(>p`i%Ye3zPLb2{(CBztA}P&V!tp@wh?KS38cr2TbZa zCg}@H`i%W|D!!AL>A#JT6aBYE(r4_y2;|JP_v?@o{ns##zF(QtHye!*`mP>FUjTAu z>h~#0U(-1H9xyT@5+W-fPCuce_b_FG~8_$I++Y<-tt-RzXhG zuX7xI*O=7zZAss?l0M^n?uQ(@dQ>pJAIvI^&FAYhX*Z~GJ{LmHOnW;ZC))dwarEso zsqgoazK==zjP1?D%a@tS}roBIv>UZ-v`i4yETaK4p(O#+(1vd_3dqa>j)84xw zC)#@p*QVcp| zS2$#S^xeH1aZt%Vje`Q|gZKI6syBJn1-);{@{%P*-r|y?_}=H27Wt4uVPfy|Z|Cu1 zqTc7TspbiLpC{iB!Iql(&h}b(Jgp1XceV!G!&{od%^gPnv8u!0_Kr~P)t&93En&8> zta|mrP)A2wLrrH#Slm~6t<*nqSCUKkeTa_54IY0;k|me$hb5kj3cr+iJA8@j(_QSC zF5PWNce5$6!Z1zJ4e9A@kuE*Mke zyqo<*$EUMbHGUpX&w#o2oK3a0we5xN*A{kQr?K`;HKC@OmX<>Fc5}z3ZB31Zb)k;X zrW)F*yRfdIZBs>gVa1xuE?n=wsH(c6+FMw@X5$7mc~f&ko55k@CgGuFQ+r$OChksZ zlj{2eE^c{Tl#?Ca!qe^8ZllMUKTF_mcp=;sk0S!F#^a=ppBMg($H_~sp7rjJeZH9g z{VGqzqKdQ5@>H}mwKg<{+dP*pTUg><=v#>U#G=cJi#+u$Z5~{O ztkA#4Us-<1iu2%K#2>8QP#NTBYgVl-uPiB}^HqG(EE+v4^nQEddT7Bucn$5rTJEwW z*c4ohf4-#sM3N)CM101`ZqLfXp}LeZt3J%gNWgBa(cxEkC?w@3`{) zO?5$^+Mwgvmh`Y$et4zPi21Ec@)ClAs!&^~X;pJacuQMDN78o@DAMntoP32WKfHMT zNYKNbG$+)Z08-4aUf(GxNvRFmt4InJkl#j9Q9~~zDdeYjl2o#5uO%s{u>9~gM&D9W z>Bc6!CZ&+y^22NS;kEqmT7Gz=FIp+wOV+m6)`r$M6(@H;!n;CKOLKC0>2p?v>IWFR zQYES*k$1wlUwNQlQEK0b-lg31KE}U>6&ALGHg|Xm!=A#mkq^VS?zN$|=7#1i?Llln z77VwwwY0S(wyq(xCD`8CiVvXe?dMg6eM|nM{P5B?V()ifyu1x&{qg3ooR3|;?ND(x z%bDE8vL@$bcb%D&os*fvN;+1&)HTiSV3SK>^PQ4|RRzu|Ii(p4GGs&Q`2O!7>nhHo zd}roN&Y47Ue?8}#j4tMatBylwD(QB7hezC#jkh8$O|j#zLrFu5J6%#p(OLk^EN&n{*uSEIK)Tl_FACF8Ac5Jk;|ZHtU5BJj=zLs(EMSICt>&I4YAvE(*Dj*KuO zj3pN_Dfdyx%@fK%g}ya7m-}TuXy@^B5=Vh zlueMt#}(2=8Vr>S+ro`}|4_9C(LJqsJZX%^h>nj^d34F7xd$n+xWVHGqLMUnPWCMw zpU!?L@nqusG5FZdxOx*P?Q;ElN#4#Tv0)v561hT+1~QSJEb-cUES9HT(zL5_o|HZn zInOlk=NtI-2L5UTFYj7S`e@f`5s3f1f&adNf5pK6&A?B^rA|@QNAJyDb*maf4b5X4 zNNM8hcX>^9UtR1Gi#ZzHS|1KZU=Ito88>zvy+dmX8?vtEU-E;s*yE#3+HRFLU^TGD zJz6K+ku}M^SgTQ^t>N;`aKhkh@I1@g{A`v$ir#9;;!QP#Xh{E!S4HwRD8}PUXqYLd%3IAa{!Z zxzjz3qMsQP`EIA)AMlsHF(#hT@PRQ|1=d!k)>fw0R;IdVb*kn|4d|7E*@9!eQpj(a zP%RUxWkR(~sFn#e1)#iTLVaIuWvYF`g`pU)>#c1qwXhO<#+(K%HCN$RQM>MKo_;ZU z3LDFk$<>m0CiO*LTE(Kaz^wU{wlm#%U}xa@5tegDU~k~T!7DDv>wA90QJNoN3r;)u z{76pgIgzy6*qPafKN5Lv#IYY+i=N`T{rMYo`rC-){I`=nL2mbZ+1up^XndicLOiXMJz8bKnNYJCTPGUmWBMSZ=$Y^#6W4 z+iM?KlWp63w_n-Y?$7gkeY@OjU^`Xh8iuh-o3)ZP=jAY46xb#q4NTQ`JgbHV+3&yp~l?ogGKW$35 z(pCWRWcCOoyVe+c1UB1mwoR}{AZ+A(`6^%xd^u{i=FSc_eQwr=O`nW#Se(dCA_|6^ z)nVr+6F%9*XA?zYKGBmkv-T;BolZQIb8|g1Q9c_tBr1+_EFdkI z&E~PONy_Bo?=Yp>t5o}x>LR7OSg9^isuwHOOO)!RO7$|Odbz#Y=f&Z}QG}xyM+t9* zf)%qBq$v%5qDEDlbRLa-4tv_EzR7pnv!^DwryW`{7fKa0CgI|K<#<<%JC>G8amG1m zc9Xd*^p5IY7n6!0B?{(2itcsC0lPF~h%+!lcM!$Q{3KD-fmY9EU}io<6f^fVEj=41 z;S9{&c|b5)kKl6hA6IxMxwX^K1>u>#wUqF&o_zU@_3CXX8NCrBH!CY2_-@f zP(cWJf&bbiMkldAy%H~=ifSG$k>rlV5i|mF$l+)=4k`~-=K)n81;`<%!)Nl!X+jz? z0&>Wi?OW6qLzoAi>L|if0F>}6TtsM80BtbvJRF1EJl+{9FRHKpSuv0cNeaLV z*2nAQPKDfABwz@aftU3KAa}VzhS)kB@&f$NL5}*1>LucFI~nD0^y`q@rpZw{1){rf z$mO1a+u}@0Gz6nu1?0*NGQ<)rMAU=$8zD#KQ2prgq7bj#PeG3Q${39Lo`YNggh(I1 z(}Tv-_qIuW6{p4Y;Zo!wp1!LgXQqA+N%{y>MuGGh$M;3ZoySx4e~jaMiYGR{{7D9J z()V>7n3k;|Je=Wy18MDCCI`XD3=a@KFI+@$@rjXHUz^Lzi6XPkpsFW{%xY^P&jLnd$-ft& zCF*qI&|05ChsB0>@c36X9#02cN>27O-l6IrLT^2z<0r9KB%YoNe~@@WU%esmguXf^ z@pepDeY%^ytxHcgq^BFuT^WXSfLhTQs=FGT?37sJa9QNA`QWSQ9>If?E!3q?Wo0^k z8rz`bXGI-cP{@<@JCwC*Zj zEb*j2VBjw|@K+o7n+*Kj2L7uWPnYr(jNdPGyqo<+$ER~2{t)Gt{uDSw_u*bdx8rii zz1Prc?d_G#wJmkwF`;VeM+I#OaIn5D9KNijt*$-TdUfq(xHF6fviXYHJb*gY%alN9 z3yX^c3*Q}TJlu4sC*+ZXbOhn_Ljq^|0FL9)$YB6;`r<@Eos_uSO-P+Oe_8>97m!Lr6JEm)o#Y4V5LYug%HJ6hU;>m#9}q7pMwixhe19n1Qew-|b!9wy`NIs*3EWIlvy@B6yhLSLXQGMbhjZ?Cmp@f0JBU@BU zTe6)90G@^9i~syY*I3R_EN3W|GZgiAU!~;?g;w8_zqXW6bQY2iIJ!_BEzL@$Ba?7| zAiu9wwWU_P_Ue+tOpxDRQc(k7NebD8L$?%EY)Gvu@tCcsYLnh%lCR3>mzk7wX$x#p z(qZuLmXa>Li?@_i>0fM;SEV{5v7Dida;2>QrP$gS>VPNSrgmw8*SqCPh3YK&z?P&N!dC5VRzi!6%Q0odp^mP%wi~(20K6$_y$=jQG*Yj?r`{bUN zMmF#NVZ;6Yj6ncEx|N>NQv9?&n8l9{BM{?&d2immRz^@Z*u0o9#V09ErE9U%5MDP{{!L&T(nw zyo0$tH)_hkGuPFd%iOJdY}dgjYW9Dmj0JUBKymS<^{@z%QG{M z9%uI!T-wLxX55!?yRCa#fZdT1IJvhpK=K^#HB?`7i@&@4oW9L@xqH&OZ2>6_*fdHz zyU*Tp>OS`zcRuC1#qaE8bJA}M%HMj{v+dD* zcJ$-S)2j4%av89dO0UpLI@LZpt*?Ce{wkJ#rGLqctuqEZ>>nqER}I}70&4G?wRx+C z_sn6ZQ>`n30bEXVL3wH9>@Lg)Wm=@CGQBUOpLw7ul)7aoLz_qryi2r)0zyK+-H=P9P>oJDEGZI25472wkH(;=u`^ zCfu3`6CAhb!w%;{G!?}21NKFxIRd5u_=z>x$V4HK8IVdCa!m^c{MA;RsB5aD__ zCJy=&srv%Ts|7L(#s&KYrd?$}MS%TaeB=#7ZBgfcHRulLj0!5n9Ow={l595iWn1>i zV}R~ZY3h9i)?02=M^~RhJh}`W$`qt0T-+`qQq)fbak>-{q)+he7#OOz2)zHm80D@vDR;X`xi5?%cLB=mMcYa>jCd zA$K`X)&DV;J0z7W#)b6l#v%8M;)xH5G|J6}TsiU@!##+Q+p*cB)|=YFAIPBb%8fuS z9^}xd@9U5&fDY0pLj;ZW`;|$3v-4y6aBtutUi|`)GgH4$N&0Ya8B^aQCiT57=_B|r z1*)HM9?Y8)A7W{o2O-Fb`GCKK`NzO8S5RU9yxTI@Lc>1ZZ)5-+aE}`{pq2-DAK`3Yf4;nN2GdIR4n@dqV+^prU) z@l(LlE1(F(yXo@P0`UtCJiQ8vK{8X)Nbf+eS z>S7)5W*c>UI{S!@&tP|h$4e`Joqg{iR4)y;HPm1CAB9j|tifCLz|~?AO{iE2&{`6W zhnGhwelg-Lplhu;psNnh3Zsz*ldZs)a(D$-ajuBg+itMqA@_D=gu$v)a$F$nD3Q@n zSffZBFsxBz6dYC+u;8%q;XLZjJjtR#X=B0EJVTa+llM2LVNjB-yak6%w&$$90h0p( zb7xV>cDiPFPd2*%mn5AZTWchpm#`4YX13t4N%!3-5J{3_Fd9LUyrR^m@u>HYWTzDr z>4783w@8l~Nm5S?GLpCgU>PjOmUVcMNCB}!?;$Bhdg=k+9&fZSj9S<1NC1!v^7KA{=TD>%pBetUT(pJE==qd%a02uR8sC z`AOUh5_uJi3uc9acMH%OxBP@Qov`4r^tn>~T(}TF@ZX1CEu+;>77lxK?JR;o+5vyG z&y0Nfz>dI6BaPkJcjWf0J@P{4QzO$4JkgNWleSN}y_8M%{$WP#Z0GHO!M59vblWrT zu;2b7K(H^4o*BJevv-zfK1*ji%kvMW z^|*R>&D>e8JX^5s(SrFLyh;$#S$*t`EB#*@a65tLnZI(_oAbSX)C3?_SD&)i(K939 z_LAH!{vYdLtbyT&ri}Dc%FBH(zna!tz-w2q?H0e{%=sn7)8UG0zj*kvoZ(Zed5$;x z-h9>B z*1e6*xg$UTS$Atj&y2lK%-B2I)jwqf=$G$Q&&(Vg%*-0JW$mkc>)BTTicLQ{c>0Gb zT-|%hop(A8{&Ab%Kxz4c-1HvG=jge`FJQ*ZlXZVqx9zrD{Or!my$-Z(^w?z`wjeu=24A@#t;goK z?RFe2A9h_$ajZw_O&eh87X~KHu=Sp$X`r(UxrUcUa=IyBRbZFj-W$tDb)jQA`eO}u zP`Y|(zK8nbpRG6L`2rjHwUfO^y?X8`cl4$4UU{|eRX#f=bI7o356vfM@9?SLoYA@h zv&pgcD05$NHa`cbyLAP%{he1IYJkB}3W@TRH3}+D->k5){*%yVLLTe?zKdYvA`O$J zSy@@WhHW}S!z2}G*u4cB*!WBhYz$v`5M>N_4#MBTaIRuVU}EMNGw6i~SHdA5;C;jc zn1oaQXDLwti$0UpbzT{{}*yJA|ze&726tenlk%3p9~=Z ztK;#8Blzi%TQo;~N%DgJ9DD{|p7_cRpps_-u1707{6z7#axqcFUr7`|cD~XBFI8K$ zc!DRAJo#3p^sf=co78N;>L}kFqDViRs0aFpLavS|^tTd4&+jCPdfY?Q&e)Sg@sf6! z=-Ge`B93^1=Mle`9syESm_zeb)tu)d6P@@wOty^ru z0m-iXTTJSEM$(5%AX-1;c>Eo5X2xSFZfauQV+f=AjQzI)a%S3lE969bQH3$}ebc1A ze@gn!7)RgfNHkNwM#zc!;qf|V{q8WS@7Iz(Jl3Q7jN@TPp=QRT6mnub@Hmg^Gmb|U zA!lY$+Jlll7b!y^eLupHPK*{Fm*gm&LOi)XNlxUC zC-;gZm!YcT`izUx1|jFh1CO2`PD$=1oXgL_zhSbAdTC;u4B)S*2SwQMF6sp(eHTy! z0_CH936^`Y#!Q6hsS#(ueD*F=X7d`xY_ah)TW^yhf5N#4v?swE zf&sN-u>T?PG->EHo^+|f$(*smAfLrf0v~&Ya(D75) z6*@kTHGprF@?WD%&u3ja-ovK9?R;rP~~A?(ks?#taC-4aGa)h2s^ zMIp7xDyX!4=v#}1tVKiCq9OU2pYmb~%ZENTW3YVaFXA^AJohah`d3f5JZIEW=;T-0 zK$U(qbn>cV3!;KJL%y|KqG3fj8W5urzqx|H?zB{k`k$tO2{zIZ)~RT3+swZ$9*( zo9)&X8Fi=UVrfxM`alws-wm+hqyNB0YmeF3sr-9GM*pO%)a7-}f{@BZ5ZhmK_`8C~Dc{XQrgu%}vi7va}K5((}qhpya@b()2&$`xbr<99^m@8xZ4~G=jb#+Cj!W(}+%cG?t{|uoQ z*sj2wfGwhUC}x*`PT=wY)6Ul(Ri<3T&#`F6;dpDme`U$C$m6cJpIa6=bgYye_|7{a zmVZ8%$l@AF$BN<0Tj9UH)s}}|D`N9d|29AT*I(Ih%Re;aC_9zQXXgn`mBUxegOB@p zq_OKkEbv-)Xee!+s`b{W*0SLz8EIYGUwI_0vUEsYSaWOMKSQNM3SZ__I^^(tD(}#c zJ%?(sIuG$vu-L`7_DxnwF&JmI2C=p|Wf3g58nTyD?5&7_(G4}jk_yh#UpmT%o-3ur zGu!jn{J;?hv-1Tq_Iz6YqSl@9r7&bjiY{frIu)F!dlfd;e-cHSMhcKQC71cIC=<|+ zT<7xu%8g&Jq;q34EW_L=?$AJ8uvBvpm`4Lg0aDIEO+X@%r&IdFK|eqe0prLR0H*mw z5eXa*H#43=6y`A4wYd-nX#g<>yEJ1SZ50d3FCre6ehxxF{4(NEkCfXCYdCK++Lnl} z`Bc6Z$dXq+tz+~e5_`T_29v3kf*zxuv7triXGgY8$(n>db=h2s%kIh|sGiN{v0-EL z$;aPeO0`$1_9@jxN_DYPU7}PkR;rgM)k~G?WlHsOd$rGt!-t~?M=_2PK28eEyA`B~ zk0T#J;V_^F67ac30o)5Y2py1%E=r%y*bPK+BPHLr z8HgvJv_uK1KDW1jZ(Hy-QQTuQa37-W2xbz6-Xfy7CocnCbQ*xbpkB~&ipM>7 zB~j?(pmvmZ6?g)dZzYO*tGbREF}RRXk9!Mr=7@>u=(f)`T=dk0L5tgm0h$ucP_KK#wL_ z?z0#=`F1bleVQC^KhB?k+%~CPaZ0!}S>FfH^}G)?MdEygLGA*`E!SjZa+yJH8|2QF z1+?=zP#Np>4aiY{QN2Vwo_efP;&IA;0J-}>NsiJf5H*(Dh$(EQ-1{IW%BAa$LOgxn zhTNrUvhJ_39od+|LZ1LKk-l9xG`qx+F$PVXXz?L_bmTMTKBHb=s&u)Da7kP+E~GizUL%;xCD5Jr;j#PFr%+x zPON?y!l*uD|6L8a^R#rC82j%&$ccH6D)2z{`#KKX@>9U0- z-i5w}MZTg%mlYRzura3xL&ysKYy6evm#jF?=PC3Dt2a~z`PrIPYs)K3%IJKRxvzzB z9Te3zwKuc}Yk}1ZZwodB7vrBVX@n7(l#?|_lPBwxGFxu2lkIv7(PsJ@(%DL}<$AJR z4*!&?&DWJpDV5%lJd7|k|G`oFaI!r|UgVO_Yq`Nry6^aQ>PdF|C_8ZSdIF6t*J?Xn z05+a%Yfz!orZE)gx8X>kCYBp)^~KCWv;jI|xxrQ^1HF@^fE^G(`xI1gtbL04)n|MP zN-hdtmr6I_H6z9BDYt;XsHD&Xe9Mkh@`syR+EVI7%MG@LXcLa*N4?1;KQp1q@G_H< zu9T6RqhD!Ks*nDyCM8uCqOIBd%B8qpdGNk%xxsFQN9k~LT|=n(yvBx(j>a(f`qs|# znp>Lbv?J2lR0E1HV#GGL1R)h}3pEB?@v%~k>1+-)Hf(9em)KBkZMeN1vF#n9+N*=D z>Lz^nN#Zg0F;4!FfUkv%XkAGB?~^D4Up7$yFK|rlEj3q#YdhK(85Mg98_UM7)7ZIM z63-O3{$`PFIc#&`{C{>8JD6hYI#aO;uumD8@`y|^G+f+xcEzdU7ezuLwFIYy+Y-Gn$6o<{NWGGp-Y}@qMhi;@$ zNW?1qaW#wXuhA;}FjBj4zycDrQjnE|YC>@$6r(1tQMFM4N^fa?Ls?^e=5^a0xiLEiG!32&FwZ>#8WsQmY(HPh4BCX3uh-{v+aeZwLm}hed7V>R^4Sp^?cETi~BT=biySVQV}54O<)P zw5?wox!;FX%?%wFx73CjFKO*)8`}p1S)lYyFgRGyCt8jcMy=0OpJtX>%5t>O&{(%< zw7q%k-F7TT3+8{W$giu`?yM#)`EsXOjutFO3znmW@zz-4YO!`_wRUF(l&+!?pAEvP zSVSzd6z@jMEM=LcDjKbR{z{s|EU-XwS} zCxYU#%u)bq7s4a$d7~^Bh<~4$rS#tn-=7W_3~exLo;vynme8l29KaI#v@;_&A2==G zyv_CiyTdtGxt|u&v$p5v`;jPX?Gns`WQZu(}H@3yyl*k zwU}L5FP8d{9{S#1Hti!fq}}Ma$$qnPt8K-!j&0LE;zhIq0}t846k((ST4jV5KErH3!2NRuOaNU$sz`Y*vdxzJD1 zzlB^WD3vSviu92!atSsRhz4Pc9CKyZVqdW;Jh3hE71dB0wMD)UR)+0IpTx#>@c1{u zi$G?^=LEy4lf5AEWLDI#qIN~M0`NfYJ+?AT|9Bvq+1RE(vJj22I?vP!vC(B&W;n|X z7j+P;8X#34rKv3z;$OWId0Ur%9ayWwtkq#{TSLvE^>q`wGE8wrA+& z*31_F7gmmC#y-pATe=#I)+BPTY7>qZg%IdG9CG#xV3;toa*S4lc_cl;N@QF)b|d6O z8i|W@vorJD*k^%XE|rsqWRWazHhCxT z2C001MEN4_N%?B2{IQ7gBK9=!PO1Ebi1G^dS_BS3n}iFq(^kE{h)LaOz%Mc2T?TxM z0bg&xt0ep_seQ8d!Jmu4i&a-X+*SY9!WZyJt5sf>OO>c)M$b?71@WP0zEr2dUX*{P7P<6 z(k-W01hrlsk-bzffdRKnz6@NVm`iGtsQI<1Yi#zzj$6y3pwyNAAPgacFvq_^m`74J zSw}`>k{x7Qd+=JgPpzoER1Pq$W!5zNf-O>Z2bR^8!kSW8Qwke0Drz>PPA6v1X!__( zz@E{JI-Rgr%VtvwYf51!(b6!bu%;AN2uw_4$grn|B);35#*n5I)|A4En~EugZIAx; z45_E-qjMrZ4U!ae-PWSS%z{lRY%I=-q8ekyrR8i&Ve7OHz#m8NoV@3;N?JXLIKA_* z)4K!lraeLZ+}E~Z(VNGrZ$FsgeJIfD-R({7IXB>$^GLmAusiKV_n{s%*B zn(b)y@G(a5oy$i)TYl~9j@=u)WYXy9RZjF>x}lgM8nsehHlnCFya$J_{8aW)M{h;o z(}CZzKRO=w*nU|y^3c`qpE=?fVHwMo_TTBrKU_AFf8L3gZub-)u73NLtE=BWarHmm zI5_m3Ph}lGICRmcR-nG)zOuk8qmI6c01NzX)Y|sxxoq2wbAQWD!q`&j|MZ-)jQ5WI zZWNM*ZG_**@prSRy*X%arQY7dLFeuTL1pkBrVegb?7QC#KIGepu{ped^Vxg*pR^9= zRf^H&cpa~6eS2=fAN9Vq-%$Pbn^(X3291}F@{y4mGVCnqXD(Zhz1QPiyRSx`!%0~h5e4bsewaiEAuGJo4KD2=ar$qzS#lv_?qt7)T7iav|P+wXt~o>aaBLK zIu2oN-#BszYx`eE|LYCJ($>f0L~o}bp<2qlVkWdv(Ol$stA^c$G-Ky+BU+h)dhFQy zJx^*t>o@i347pDY+0>`@GTx`P!#5RYWMSnx^RjL}c4hH*5M4d}uxG^5fYnzWp+5eR z_wlz!fBOcts(3TJX*{0xfx%REU=WstXSA)LKEMCQ??>6eeDCd*se9jlBRxBn=PA9c zhhH0q?Y*_$OK2S^G@dc;whaQw8a3iS#o4Z*nA{2qCIb0j7puK+SnjIHV7cKXtR%@O zRygOSSgTy*2l*T~pu`w?NIuB=d3_k+lKhwA?{N(To^(vk}km#f)FB7zli@*g6PLGf-s&fA&7kPA58f?l;JEyo7M9x z2>&MRH2bLrplpO6ooyZPP)vvL!W}F(we({@=bgyo7+42 z%1qE)qATMFZDRbA@|8g&ajcA!ugp!8Z({sLo`RLpn)}}5Q#Cz}D2E2Xp z{eCK&`|{+Ic`BPboK$nkUtZA7`w8{T_mN zd)TMve?`xKfFQgb{f6K?#)b*v#bO4O35k9dK^J4Q3FhDhgdpfW1kV9~f}m?An9JA$ z1o6W05J9y6O@e6uAVJjoiC+E!LGb+rLGXP^FQ=Ce;&UnBCh(~zh$EoGHo&=f5xIfj zJi1G%p#+THu~5Q23!yf6@htw1L=QIfZp7cY@Iy_%5%lhZR}YMnlgbLRl*TC{|j z(%RAsiEbbYq0s@-TvY7AaH*d(0!rxCm|!R020;LH#$;4kpM`<_1>-O#%#x&U%-Fk# z>wy&;lL~Y?K0i3mK?9%Tlcw7jaj7ouB)~0 z@ip?>vJZ!tCn{T% zqqRfxLgS$nt=*-dqqQ_9BfrmrE+0h1j{^2kipKB382JrK{P=eeou6@@GjsLt6uiao zALBgNfKII2={i}o{?&snmhpZabYi@uZ%rv0zZYZVHw!lb!H=$OO40aT2)bDMcZtnN2d|MIDZ466Z3~lil=D(dnd;JmFI=Wi=`fyUl4S$jQ60#4_yfH zGmiIF(8V&|)9~{t#*5PsKjZawHVR|uUo+^$`hH>pes{&l@3#`a`4jN7;AS67|5k%e z^zU4WpK<=$K^M#XJqkK8e~To3#`!xOWB+WJG|@l)9TPmG?Z3sKi)FlB5*X>q-cO4$STSDyofgE=#=8+jvGDshiC@VC{rg3X z{Iam=K+5m;%O~Jh2D%k`xeScsy;b7($qD#98Y90EiJw?M2l(#7p-3H>yCAmy`9UYf z`>6@~_r)0by)5x7m-rd?-+Q1F{g=8u=6Ps2E?TkwDkOf7;@l!RdRzs%D`iId`C-6R zDgUdWI|f|EVbk+z{+`Dn&)=O38B5d4W$+3Rncr7Hw-R~8PwWTcw`8fiAe!IE5@bfT zLf&w1b$m6&&I9^om2fB)*XS{*=`9JmVmeGdBPI#CIfzpgx@9A$BQNVh5_$0 z;75U<3A#;yA2Cb4%l+-aP1nb0tGB7$?_b~A-qaD*ST9`q(YDru5#P85b#YtIbu}~x z8zmFDYx#VdMsm^B{F=>(fo8KHNM7V>L%x#)-;kc zjpX8rt|=7E6W#5mk(_BHXBx?M_{Wc5OHVMSt5V&oplKu*emF6W

H(@4%Vk~59u z{P5#5!EcXgBsa;UiD@LaBxXak0;4j9T6A7(k1 z%-#-Dxg9W-(=l!=H@bG$L7R7)cUxelcdxfR;MiRleD2I@m_7Yy#5 zzXrRRy=ORh$hRAYX4AbxFf|--f$S6zV?-hYEcF=Pt`rC;&a zy3#`0ecFG@#hDKBL7j-T56OhwI8=xgNn0*%%c$A9Wz^}qq8?N!xyB6CaJW1PYFQ*# zVW5NZ4HtiMjSz@Oq5Q$~=M%JQ65XW601+o214Nne%m# zw^?pSe97|67WLbi+xSdDz{*>3Y9m%4(8au2rz&dt6lgNq6}xJ;*wZgWuA;aUHbtFw z@_nY(y4BhOwYE^LEmCWX)!Lj@fTT@*2SMBfh4wVgV$qx?GC9$mDOv(|$l1e*=%{PPMA{>y6(SO8MjymMbiGUk5qx(SDBQ+rUUSi-^gO1Sb ziX_fS`$ekGE(P5JK_tQT2D;CIE*8z`?}Lu!i~1!raOm#UCE++_FMw_vAkk4dC4$Cw zJ@`?LrQOegPPB`=Jx|g2-2uAG^>P_B0TKPB{69X>Wbot05eiLa%|1?H^>CliD{BZU2 zMEx_aTQTS^(930DoabvmC)VwBoiN&Xw}Wn_%t${sj`w+~f4Ee5ipFmUbg|6eGN>Ep zgA2_cwk%K4_+16MSonQa;)f|8m*3A~{en@V`FkFRd>ySoV|FSuq*s8;{MLd_tjF0pE%AdU zUr{`oe9KCfm2ySC7&Q3;_!&eBY4S~>o_}OC`3%tlcvs~=@+_0)-Q6e*=MA0whD1!7 zb@T%-5^2`;34}u%`;mlGu;`a1oYs(5jQD$Sd?Yo?s>W3<8`qipxXM}Nu3Y=>fQx@s zd9AB_?YdR2iX|22p6jX*pOh{yU0m#5T(G#Xpm520?9xrG?JleuTU5EWvdVMWiVF%{ ziz@4CFRiNMXKPngd#Z}d={!bNgQ%ar8n<=?p%vHK4u|h`TkDqMUqQlZBUQ~E3D-3h ztV{(fQ^6|ch|H#fRg8B%Ss~B#LT-8?=c2Z-Kr%snGcc&}wfnZNYU%WEZVz@QtfmP@ z>->#f?f#0^F7Rqk^!F2dB10x7IIwWM#P}KDQrp^^_znw2N{qi{O@2y`A4#Zk@F$QY z>zfKzrh=6|1Ezu%kLAoCRFb%=Oa&`b!OB#yG8L>s4_ZmwOZXFp>4iMlKH+O-)bB*e zePxQdwy9v%EPX8ecm{yhzjQ8+RmJMq6RP*JKsx+7kGe_esA~9F!MWa90oMQNxn~?2 znElvBw&0&f{y2B;lGK;lvuBJd3x8#|{>n2lt$toT(I0z?zAcl+&rF3r`p2p)BLqKG zn?6IAXMX19lv}Kyx7-TV7B@0fh(k#ttO^k^Apa%~QNjl&Qb&UkiFyz%QBOq2sGR6X z&SgwS+4V0#(1U~Ol1zjW$#O{UC-b`s4MdZLlYEQM0w5)5Td~2J+PVBU4~R@x1i@V_ zvg<2AN6R4+*z;6^zcRo5pu+-%k~lZYuI~e#kST?Tak3tV%dH)FKkez8)6{Aj!U-mT=l@&jP0y z$6B(n{}iWy|Uvy`2UB5Q~A$PAt{ntg(c03{X&~`-wMh;j#MIQS>-4vE z6ciTKc`vJx%JFGyRm-(fhNxhQG)~;rg?n_OVxMMHq?x$D z$@Cdv`iz*wFcaUSOpzujCMEIJwLH1%6~VRuyzn)@OzcSRPe``#Op(IsG_FbU(?>&=%gkh-`E+1E>Ke4G6O4{ft5S(Wg)6S5=vsG&xkg7VDPsz1$`|SGzU97oBhBy zwRK(4(%M3&oq?{c4S-PcC$y!t4pjbjUvphsYiqNX)79c@4sLGoH`VzX=>~vY?ZaeS z=qh$Kbj7QgO?O3FI!!T;M4IAj;m1>^8R~tkLQM*!Z1t86Gj{92KKx|?TTe~kCuf$i zzBBtAeQd;`^mKbim}77ydwDdYj}3Ym8_IAV2&NBqr?bI*_Wt0lp0E2#58J(O`2GVv zA*LTmAA!-r6#LJ`U{nu5M9=^`|M!ow<5xCepvMlGf{p#-N zfsFf}KAxs1-LnJ#c|6VX%<(kU)4e=EdE2|yz0N@TpiLo+N}lO1-~MAj%l2osrwlq2 zwi_kt4xF##G)nG8!;rM@@a*{Uu$uC#(aM8w1}(c61diI@d)Yf+^8}h`!~;HC4vm?- zP$(zvDp!VPq~-^n0Zq!oDK4Ii(77uI9II0Hf&Q8wkIw0__Wax6OSZmY`!yGG3Tv+; zOXF+p897tgJK`uCcGL{BzF}J%aj<@cYN@?SL3~mkR{41fIIZ$NG%(zTh{u88!NGmg5Vrala~>Gn=R6R2b~NiiNg0F=uShmX;rQ8uQV2ybOkFS9sG8lkl5F+9c3s=U_}0+dj;pWlrD$kHWol z*m=<5JF>N!Z6xL-p|`zEWn=%7G`uV>Y508NrzaBJL=8||nb~H^69H-=aE&S*hxs;_ zx5AAAmyg0hJGZrk&=jYPL1Z+8ApUUMPzav6=^PL)l1Js)R1Q9r{{efFz$H~dt)x(s zLXbsJoQF;*fS?xt@L|i;jBx_rLb6MPC&wY&X#uPiAqQqE1~ZQ!%HwYCXCH2JZza`S zK1L~PV8rUY!ijpC;{t3NzOOKaNorZpc7o`QDI}#-RjcAqooc!=RiPzXg7u+&=>{An zoOBql=x#tOpcDIYHbLy$^9f?VZX}3J+^yq#ba;Ru_V0rP!StI1QSTYO{3m+;p9!Kf zf79^`aiLK^DgmhT2a~ox(2i@k~l3v zhRpBJ=m?q)C2?-l3;7%9G&P72DL+|{zcN2N4EL{yB;i;S{_^{qURE#p0ucG6?_tyn zX#?E`qM|O) zH1dyeeg7SFbUn~``R^7W@p}{pu9-Ffo}L38t*w$hNv$v&Hcmw$nBa zPw&vlgM0+qA5!l5g@n_>{8GY68RyRuPRclM=y)FBbXv%Y^ENg%Hg+uPxNcD=-m*G2 zHu$zSw6-onZ(BMyZrj?tsL9vq+sNOk7BvOiH&%ESRjggVdR^s3HMJGB?nR!p8!pv~ zH@1vX)!o?Eu4x-=#Ou{Yh$q@QHillZcwPt#y>gKv$M^~_6U_cHme;hn)VKyE$c>@~ z5~(+0nz?H)&GZt?S4n>rHqG2kGxvBuri8^ViCRXQaYW+&f~9|aPISg=d`+a8m$+Vs zsS}crE{%|sD(@3Y*DNQn@s`{Cs><_W6AcL8cVqw4!ivft#g_ zS#V~XZeNpXnW9WrW>~Y7Y-NsRp+e#~F8d_ehb;S?8UFf>5=!w%5^vP1MEo^M5+6rt zHx7~{+Hp`K$prO;OEW10sR%uRj>(urU6->z2@%PO7$k{qNFyeaB$A|s(&eC|&-Ef% z^^>)La=SNxPLvUeIKRq3_c=`pLL?EX1(+-uBD!djp(RTT+yzl2G$qB+B{ZeWN;JVu z3|@&xAXP&ONocYYlF*Rxt5FOvRut0&$;9TmO>m0`xlFsiSvHE*GRSyV7Typ(rq-BD zgNTQ-4)tg;+S?p#+0+_tA(X?1F8`5Nm%JPwKw&s<=;U`LViE>D6@jO+pGi0ghe%jN zvVJYu*ssMYAX$398G%n>??vF5EG<-*=hglMc;d172ppuat0- zsqQe~j{v7E8pB7-Qu|VWM`ulYaI3!pn%+T(%>3hvuxK+ZWAaW~&hoHfDZdWZ*oGZ7 zxy^RLa^r57gkHj=T9<(dG}4-SO|ZGy-(HJ*cMFX~l9!Dgm?k+ZG}v2@M`yIl9!qB$ zWSa)r2C<`T0u|3=w)EoE%)fOdTDht*aT`}SKiJyV>`z#hLZ7ITs+^o%vnhNtg>Nms zNeoT(R|?IlDbb5eHfc(j2VSKTtt&oUC0gGUzR7R3W4}}-IIm+qQzgzP@*7oxe8L~7 z;%8tA-nFV(OyQg9W7_mFE$rIGGfWa! zr73(fg>OZP{j!+Cw^)>8qYD4xQWp&3;~ZH!1GaR!7Qs5YI&cFruJg6GKy9<5&e!g* z^S8IRwv$0L46HZTb#%31TX%F^P~$IH_J2V5Huk&W$I~=B$~a;b#4URB{pv4x_j{`c z&X^9vW_$X*&z}jyX8X?_uZ&i9zs24Up6gx3QU-sVlA5aCvtenf^8VFd^eFc{d)z)h z|L}b8E=P)&?Y15}IrX97!rDzGV;lSd+ z#bh`A6V8$S?N(y}q2AYgdo-6_DBQiz6qm+1dZQQC9Zs@ic3C_ly8cvaPc# z9p_!#O~%=`b(fB2yI#QGxi07SKIE+4o>d8m81g%}zp!0#skx3Ft9O(J`i}R(HtU_E z6$6%v>zf?8@A}GyEjjNr^x<#i@I{Qwn(rU}OF6-;L&}L|<#`2#{ps9XJ#4z2Q%U8e zPp%&M)|JW$XE}}N@q)SiyEt7+$i#bBWogKmnW(>gb?S*9a%xY3z5hy3r%cc12HC4B zcX%HOvfdpYm`3N$nEg=T5ntuV_S}?wjJ;hmmwu>T?Y$&x)TivP@xI&eQ>=r98$OqE z19CE$4w*h%+$z)llex27$%iCEHa!(l=N(o@io@oxI~k#S1P&PtH{BAZ&Qo>MI@rT;6G{{!i<>%U0eqxPnbTDZ91Y*1PE8*> zaOyLOE@^OMOqnt0d6bXx3cwgGr?uw3mQ-`b1&-CWn9LnNG~41)G^W|`0;1&%?5-sc zf6oGR19F>U>s7}#Y-BH&FpWLr!h=t$#%`X%zo7PCvjamua%T`3^Z zQ8^`oyKu}XZFe6;f5X!|bn^Rr1lk``*LYRJX<>dZ;iO&>S#D?VMwB~PdYCy% z9Bi77=K&+z-Vz;maU7~mA01oYu}{HCTm8~U(s9hPON{CfrI9wlQF_C@%EzbUVA>EH zO^>wi)}{@yX+s>#XA)Uh5jN9_U*@LmI#Z3oRAVsJ7@D?B?vvA0V=&biCQ)fh}Q z1|e}YZHU7UCrLtftkpfE4$ffwMjr4K0J3fg1lhjg3S4iq(v^#FZXZ-qzPyHZ5g78cdFEI8a zh<8$BkXrsHL^kJe4v~KfbbcfyqBIOT5+#TvBtu5JS&+=Q1QDR1TZ?nK+si;F%7|Q? z8|{X*+#Q%mOQIBJvTv8gl2iaUm@Q_0G$Vf6c84%XP;~EWXAGIkmNz{7ho#%5)M!VzCv~+E~w6y|1 z#84O1%#9<>km0TYcF573=t=@J?QyiOv9;}bgGsR*v{|$5s)G|@K1iu=V}CWI!l)fL z4TMbtVbeg^jM!{OY;I|cOKn_yT`?mzCpK^5t5l*gXj8IgO4dxtT8Dqhcm`I@q#Km9 zMW|^Yti2tW2EyFQu_;+IC2OW+O+5RFXP6{J)uw^)c)wp`eV!yf&12l2B*iMy^GV{Y z!p=_;;-M=JB~(}YQ8T^sj*Y4{_Ib*btVRDW`th_8j`|gJajbH+MQ@H)@AR%5DW3j? zgD}*+X0A7N_a5&x4wkFHoY(4g>``{x_t^I21`h<)!EU>9W`FR0-*y=JD&E(9UpnMY z?K`vEq4wkk4g}P__8~_as8Uk1`UCgZ>s0ks+!WX|@`55vfq&HhQ<(PVcmE83VVtZ4 zx?!5EtZYu{c_C=s^ZeD8-N`oc7rmgon@A>^`UXSC;zemjE-y`m^&3i-O3a^XPc}6S^h_^iQ zgF?rU;^^@d9laq?iqcG8S{k?`+c~5-)oq?*7FBIiT+aPzds)wUq1w}U?UD8#&s;=E zE-k{`boBCbHGwDf~|IVi4Q>3tyh)j+w| zx`3M;pY?!G-FGLMAJ5xA`>XZV{g^QoGp7F1XSw(0WiL0R>|fWka^y?x>bui@<-`AN zvAjEb`V?+}d`r_G{#kU~`ox!Bc@dM%V=r3~C^_^$A9=A_9}}%eBuVjPUOUzZw=(l; z^GW*&YtV@@$`j|+2D;yXj^@Fb>X0E%!vN@_Nrjt1C#3Ae!-I(;e$-zI=1hsC zn*V}BrmF>=8+k-0@`-LY4p|z#19Z{ay zab?=vU2@2WHutto978#L=<*+Vw~);HJ`{%YhE6`AWK2GT;^RS zs)OJ5i1G~91N>sCyf>nJ2KzejcCi&v|Ivu@nLH}EsBS?l;a^3RpT#Ij_zhD1zekjx z&E5sRLn^n3TLhR|SP`26e5X`?Mnw51*#h7XNaaNl<*S$n_(M|pMG@tfu`45RJKG}R zxHs~leO0ed>q+S*1O6EUzRQ3=Y`{AtyhUn{bQErsaIzNPE#XxDbp!sS0e``Ozh=PS zGTNq(G#^-V!$sq;9Cs%9s~Y_0sobR)A;_!fS)aH@hGG6H4;w!xypcFXTWy> zUjw>xFvlM;oeq3@)Sumhtu1vG?VXe8bLbyu>U_=3trSdpeQSGDM;*eXtoP|k5z#5y zwlt2R=nK^U%Lo4jlEFU9BkPFSmO(}>+4CM zX6qpFSk-c^oU^tPPQUdG;i2Dv%Gx!8B<#eWaw`47mSAVl*BrdTFIBGE)`plnp5W#x zL?-aHc-vdIf?6V2wKam^(pE!pG^Sc0sR>!@DnN|^f8!QT9_+k+U1z($Wpk$(>bUw$ zdhe)w%r&J)?sgjj5R6Ax5F?$@*gs;Cs3Tl)>5|GI*1x4uOfVH(?r#rny1r_nKAS2` zrV5j(!epv2nJP@C3RB#E8Soop#yDub4vNy92&IQ7>qKV*A~xNaEaf<@18(U}tADf+sB6gh1pitu1ug8R**D0NA*-gHXgI2Ni4Y#-Q41Ds`EASXx|9M(CKU3Qitf@`YXx!QMt#{9pq8KJMd8`Y}z^I6XwTLeQE44 zVpUyIy*+`m@)x~%vbvl5{)dVXl#cE^IAiy#qYl^1UUko_qgfdjkEjjG?()FQUh8gU=Wb8x zQETtP6Rb7;$iWk3t!en%UFSSfH9YDj6{o6^8Q1*wPi;ABe|HY+@69RWDnZJL?^Ke~ z(2QbI8tU<+AGvtst?3jQVM;bsdJ0({>b6%7sO+pi&FtMCNZp;wlvlQ zFWATarQ$ZPU+gL-`BHc>xg0U8-|C6us1Mjm~mS_p*J{k()MX zQ+b{3X@g#c?SGn=&vgA}JKMJ_8<;YEM;er|l)=wi*xnxTj_w+sKU&?qS{b8;Dn7xKI**i$h z?R1)B9M|os%HVTFb?NwimGx-(@X?wVN8WGC=}$Rvz*pn_=j*n;mR{@rsk^83OqID^ zy(Zh{1(zExubLUb<%b@}(drS4`^Ay}X{*X+d6ffpR{A<|b9-NUy=>U-%JD)`jYp|i zlU-Al8mfJ9wz?N9a^ir0_UpDBUqzX>v|yKmddBk0k3e~iSwc}MD7SCe;U>5yJ8D_k zcx9AdHe%1f4jFdT5QhDY9Z_jrlkF-#IC$4ID3IkH7`)5++-O#r6MfQpv67VdRE)&W zTr`LCy%`n3*Pj}l$=KeV+slS2wua(cIh@JIMtejVOmUJ5pBgx7fA8gaU(UNP=PRyz ztB-xnonJpEXL)_f&>Z#Z`aD-@J+t<*|YKeBVNp1p-(59`U6NEmV|x$KF5y z*Ugr`kw?xgM~N-R6JP=A`PG5jDwhXp0_9n#ku^W)sGrh1Ke)0!KgdEf=LXLM)rLUz zvF{XEhvryzWSv)^Q$HuSu)Yy(yX&n(dCL9u3xQjQ7P9{O;+z7U6|1?v^Lgp{iqBVx zQsz3~s}ER*Diy5a45i+(w?0r_U(frY3_9%_s+JyY2o#__Wv}yq&~B8=6x$i)aGr02T%Vx*l!h-hh-=Z(&^LTt`)!pyo|Gfh9`*SVZ&|-}-($F!?mS#J zvaQVa>SMUOeu2(2s^5OG9{WkbUQ(X(JvBNDJ8oq+cDfY^Mt*y1g zJJ`Quzc}&^uEo{EZz+#d(%trw%I(LlEI2guwNL%hOJhtwjQc}9b~nSmZo7hh1uQf6 z_2KWFzyltI&(P^yO|m?zpuRqI{5EzAXL0pk&e`jUfx+5cL zUek15*bDLSnoskhCsOh8WOj^IHeQigZ*f?3ZDS}A@lI!Go9zP*TQoDSI6@8{w&+)m zsjjhu;Dbb`>55XZ12Iud&1CF!g4iK+g{Ua6093F8!)l6jErzu0#L3HZZA@$KpC4{> zUrzl{NB3VzHD}z4u?A&wV9Lw*HFBE1-LPVDugp!>Nv8_8o>R6Fo=>W|2-fbf`i3RXsI?&-;IK&P^~lOJw#-<$jfbV^6};Wqcv$!|atj4sh_9=-vcsc&;M z62~@o@*B|M$sZQ+)^ZBAxz^lYKHTPZO}-IM<>d?tCHAU=!aB9Gwb37*5)y#(>i<(oR* zr{hO-{Lec6wvN9~Fcib%bB+UdE9YX2 zn;__B5Ck1wS~=YYKw9Uk0BM~Al#di18vA!yjQn;>{D?25X#DO6-4$AK#9!k)za#O(=MSEU z-!2^T`a0*w76AAh(0MdA5r6jq6YEF?0nkx9v~FTsM{BnYbhOuu$;j_}pu_x*Mls%b5&~hb%`IIiN@vkVvPJ|fr;oJ{q|9!^)>F73qcple)$aO#D2juDNn?2 z7Y_M8c{}K08ShI{|M2X~Q#5|>#K^DQ9UgDV1pI=ai=}@DC4P8T4fW4Bf3Jcrmiapk zi;w{>bic0dMG^1+4piT0!MyDLV1zm@oLc_jEo<7dH(M=bqY4LZ@k zaz5JV{MuvW_oT$HVgi1z$H*@qn^^R(Y65;Wpo?X^Uy}FaGzCXW*7xXDoJ#qR9PGo+mxam>5#7{g&6F(=s`V_%| zPbdkmK1Fcp6V0p7veJ?gjd*geKL3LkR-{lYnsn-V++KZ1`?RjLVN+KJIiP5&+tk%o z*Wus1)!))-^nWnc*^j{~5ATosN1n^^!pjJHa+O2#8csI$yD)-vwj0Xr?45{mhoRiT zvZM}>>m51V46Wcoy?iG4Oh@~dM&Ne#*$5mfT5;aS#>U2uMIF~I>V$f5$HoTV)`r&B zMew`P(z$Wl*5*YN(`RD?*?2B$3bt>o@GPoWyMFb$%8P1hD{9?~JZm>xsugb>>(_Ck z&=uYYz2J=$F|A``NIRJ4g|H}Y5qKOixT7Ga6&=@ibo#e;sL-{kwcUjc%obIyt*r7~w&H>U*P_b0+DohI_}SW3)t;*2aynnd z*K^6(1&egV88tv2^vZ*9=>iWN{%v(z>z3kQL8A7n%~j1E3D+f8>q%AC{Ith!AFAzH za?+k?-HKpaz~7!^_2jzG4I2~fKRISkxb8OJ*0yGU!u81>F{#SQ%^R-$gj-+ZOMKc; zH@S{;1I9!bjXPjZxUzq1YkT6eR^w}G3bt%cc-G%6n{m~_94oTk?Oiv5+(IoVXZFrbTe0{>6qmtrL<7@YA zUDeX*-`oyom`Ut7^e57PR8rlFe6UHJRoIJELOgUwQVG@7J~EiWVkY}WMNhP5u$U;H zB>C41SSa@~dULMB%>et$EH5}1($gc<7n}cgnbNTp=AjYrN8h<5izeoSNN<)d& z<3a{|_N6nA!@s?fmP(p#PJHC%dB>2a%6ad;ky;1}#YuE3(NQWVwI-k6*AQe1go&)8 za54NYr{L)n-#ZtrDJohFj~Y!KZOk^^z9!W&MVYS5ux2UQ${fo=g;ZPc<(Mg%I8jxr z;!vGxx-wOnDSfv`5fTJrQ4@2%g ze$a`ws7Y~tm4WVSpo^ATkcp`XN#uxbLli=ijFo5-FiqYiBx5BImqn9|6}U@EHPP7Q zlCef@hC`CEtb`oTvjHix!E1nY%?bQnoI|1;iey3JvT_Mu8fJz?wXyRf@Km;1!by<2 z1~~E7l8s#^l~W{(Cg9-<*~Xe9%BQl=0522O!SAMs@(i{I_{CEBzKHS}?BNL9&b}|< zq!;{@gwFtKk@cmI0XVx_Pf-Pq3ggOMV+3Kg*36b*EQxb@POBo=T zY`b0x1yJE@mLmfYYK%MZ@r*J+QsAymf2HK4KWdacsXSqS|9tnF9{){`|B(`eX8Fr+ zqQXH_4&4~DK87T{X*T81al4&Q&Q*G|DThv6;l-3gn{w#!ef~y%u1)lpB;*x0eg^u7 z+W0FPzS1VjfYjiU_)2Wbp}XLmTz(o!VlquRv?+%+<lshA%B$N%-$ zAIlS;-LXN8lHz5`p_`T%bOkjzcmg^p@jMVkwKf2QB{9DrN9FJ#)i&kObdNO1q4m$+ zAAc#dHjr3l(5Kex|NGS`lGp!x4xYCAk-)58+n$Gmc=sjbgIXE1rbhbw@A%WK-t>o$j5@l7pX_Ok>Dll|-O=lD zz~}${Gsx$^%Il4~XT$5i)&}|IKcD-kR(e72u)z^tnzXbbJL_}wF%_Qu z74G?8tLZ?^vyP~H8KMBFz3KZ3DwQFJ-MZI4$Wo{7NgY(2EcfT5#XUbCtvQ%^&(B9! z9-RKAj6FXeJ^z43Z`;CS0vz2g{9mtZvh@Dsc$y79|LwMJ%iiaYr=?bRTY3+ST6?VU zq<={z`S*VsIfxP9JTU4wpzbXnP|BP=&QMf=r+w-BULCc%Umax`s%!u3>`Li!?iJ-Bojsr0mt_qL*lYk!{m)`1_v@nrn7eIpEvBD}#Ld-{8Pq1>=O3A``yF4&SO3NA933YQ=MR=}&TY%RH@-gKi(SWQ zG)nTtE@;u`8R$W~bLc_m-JWSjFB+-KVDHX)Wc5hHHRwNfjx&wCmaiUA*%jU^UeEVl z;=TO!RCpSve!!6Sm}C32hZt7PdSLoDXwI|}>S5Wj|LFda*LIh6Z_3>pypH9&96!hS zsNVVBLtd&o*zN4aYC7O+-SOP$9ES11%Q`C%e*GQUSQpn(`@1in{pEA+o%fa8`{2*N zU_Sim=aN5v%a;1QoSb@=`$#>T2Y>#`VEugGLX-sqTYTRjfBveo-o7swSY5v*kk)f$ zAS+dy^obgD+TKR56*c=}%nfBsh% z>;Ua@?#tgkG>2{D{`^_alW5^zo$eebrw9B(=Del=?C z^B|7E@37A@`P|(QNYB3v()a`?>8=v@w<`PN>VjnW|ba^JwIDUt_WpO57B zc(SkqwOqz`U^;f-21M6*FqOtetMBPg?WH&(+dT^pJ7zQ2um1YVXh#39M_FIqzCXaT ze%9X8_t#gt;aPvySIDz|+c=)}XGM6{pQd}(kLVG6>-TtUN54;TNnR@($*-T*e?IRE zdAMg3W2EhZ{_pGF^&fIozx|hb8k?invbXPe8gq2BoC{sl?YneR%e9{9&eA>KyL8X@IlAZj zT*fw2`8>^1KdCu`0u`xssLsTBrK7%^c);AA^Fl_VYZ>A-P3JW=K3?i7)=v58+Ih)w&B4lf6-6Px^Ig4neC z2!ihcf@tsC1kv6s98O#m)`xV@|{u8JoJOmOdCtAvA39}lZFGzIHMj<2}L(EVpjpD2Z8JLBTo?kTm!<8Vo ziiiw})VQc^k;pBg1;aI_JY>jp52NBaMk3%suMli_dJ%N}d{Q)A^t}YA%UpuXdpqbvyL6wS6pi2h82P;-@xyJ3r)d1%h>_nsEV$?&K}ym16@l&wtvKRu6EHEK zRPY6fAE}g4B7VDYSR_5qdqEdX&vP&6WPWdht_%xK>ml|U@%t(cc^?#Glj1TRlMW$A z=J!d^P8k-I45cg5wJT)))4bQ!0gT)(spn+hqUUwRgGJ#Nn{A)U{< zYd87p0&vgZZ$B0KrKE2fRS7jB^Mlhu{W7K|yp%&HN!3~;(jxu7Kmf@p%X1P=o8o7{ ze?#lZla2jSoC1;->0cx8DeRvScqVh8@xMv+Gs2xg{cLtt1a4<;2^X90O}##8%~JZU zgcnKlbV*c7IQ?p0F5y(Z*?^Olt4LJdW56FU;D-$Oj}7=M27J_jPYullIk|zyUf@JR zbNmt00$meqZuYm=!kVCkwC~2%09{Pi&N3!%bNHNrwl?M06=_$IwA~8|$7X>_rdY05 zE{@19T$-HjB{_nqTU!Yq9J*p5&$wjWHC?`TzwnX6^Y9rR)_+yo+5};u`kAD&>FpA1 z@DaKWOks}U32v@xp)jc4_SUV)7MhN}mZsLNb?{$=pr@UFk&ADWhQ+9>^*41jmbWxj z1pEkn3L}&8X-(xvQ~A+UehgWnHk(d(64Tl=o$$oydQ4Vz<;LvsND}4BrW2loJtsk~ zUQyHTuhFbWTNCzI20jM6^#m6ajFQvg9jhsjcuykL1QO?CDnFXakERnIO_8=r_YIi1 z{*Lx!l4Sj)y_S%1MiPA>KY__rPkIFWK_#g^bOw?dgXS|Zi5>`ZjbvDuPI$N`tm%Zu zbixDw&y)HKmY%!uq!syKlf-2hGVDl*2RgO2wI!K*k?DlTbi#w(Z`6sUyCUUkw{|NG_F=uc-vI3CFk@C z`;gmWz0`wbzV7sUEu;P8Q{s%*B8awu-Zp*$ayqbC-sceDI z$PWs8JY~mvx-I)1y;pc=^S1BEemKB-Nj)odHp>C8oW5ae`5CUpg5-%RKLy2DCdrBSKw*;doQDwr))R{^WjiY z`x<2r+YJ>uw`IS5pLMU=6WP<_Q01y3Ud)QNpsWN=-jQ9da7zz8sh~v7(R#6R_`))+ zjQVV${^f-GyzOOzTNPs^=Q^1C_P>cWw0AkdaJAIo8}z8an6(8tbW^x1Dn}7 zq$)O*pK~QuQi*K$LgCP+my=2xDUvPsPVX-pxx$TFoBBv;-H!$p4(qH}pOBz0Wg z4+l|DE8`)yRht-kdusQ4wha=VD zbfh`b9aH7VF4TQ3m^)URlz3=Nar8ZdPt~24Nv8_yeF~;ZYwl1|%_TZjq*kI$m8AFg zL8-mb_F4j|HKvWZ0iOdTb+JDY#I^MvL0pI=^mpRg^bo|gb`?Qfm^Tmv{cQwsjov{J z3-A>^|C>7gL%sa(1feeWKHw7QKv{7UaRZX;CsJRVMG!ZDJc8hRAwlrvVTF<32b}s# zVS=f@Ts@9vjH{mk(lvws{KCP#2es)>WQs@GY#_2K$BfEmb1|4BIH+Br6hsj7rS*l^ zV(cI2^kq1V3FFspih4l>ZXfSrl8gzuJrQ&lVj<2k5&1c5&HGytaYFC_=pbXs( zrH#;QcL(UM2p5OWnsCN%`g+bApriSseu;eCNyjLg z{Xfuk>vU93iQq0Aa=X{zmjSoPG08}GC+Iw5sGuW>Jkbv-{uSt`9qON~lxF1jd(iP8 zV5%e~BfmW8mFA<=imiXupcCWeKj!1`yDmn4Ka}|49>G(z@%|Nbv5a?KPI$by=Y{w^iZfi(ZF&|f z0^J6INboSu<^6Iy=$=C!t*^KSsejMokoW1jTs*5G&zN38hRkmR=;+~v_~8=ZiTFVW z4{?^lN$B7e6-4*(xD3(KH0sH9@CLPs4e8)HspoO);L*$IhZg4Jl zY{mqOH5#EjYeKk}=uRhB1_{?SV}d0-cb6tHcMvI=>PXSma4|KeI+FJM6cW}YdU>0^ z*mO^7$%stlr;&uDw%THvzSvA(Y^EA~x5xwYD~EIbAKj=HTWQe^Z^Wk;mm) zw1|h(sY9HuPQ>8~wziBPKWn@j0ryZjp*oWG&GP?%N)jJPtZGRa?7u&8Xr#LcpYko; z3-DRmf`~zuRQj_2v5xiCjsBDP(~g5uH1Q`HcApXcK(7(vuTlKDmL^BYi9%G63FBO@ zehEYr6Nx|hq@vDsprdd2B3bp5wSY3ee+8W=BNB0bm4WU~O*BFz5vc{3EG{CtXyPLB zov;jHxI#(DZAyxx%WX;uN=jpu+x$ioV1?v1QxlTgd{Dj<#`TI2F_DDG3u9$NC-05O z8#?)zRD*;&Pe$OW?57e=Qn(i+oP<5Um2ld&e~@reJo;}5Cz+}ub%@F{C7jC1%K>G5 z2ggUu>OV5j&iHbo@r?eX2#4zGw4aE^z?QmAzF;$xGd9EcUfAA~eSDOq&W{=Ar^UCfY0Km4@99+;-?rm1@@;tfe4ga;(k)V(Eke`rx9LwGnf$0WDZ-yUFOLxN?GTjm9hL=qiROU zXhz1jMy(kc1>YLAWz2zDyCcILGGPD7XyuWNT(rc7ePPpT`1BuGtOm%iObR9X)b7c= z_Ga5HDWA9AYT2pYp{SQ<-rz>I3fT==`H_VzPk{V`JDMv_#_&!=iGcdyq~H$!MkcD$0-Gpt_>D zXkxmD(7FmO3;vY-2@q-j`c{C5~<6D2Zb)njFcR$i@ zJ#i@~See#dlWW4661n)iTbL5L0url1(guTbDCI9&Q&hAVrdv%NA6tps$Jf|v?Dx;b zu}bDL*zC7vuP67l@N#(?Q>+$*64xbC<>%wGvd@o5j7%xSX&hm!7b+x)fl&ri$T^=J z#Cm4<12{@3k#HzlB0{4O>BcC8Mj_JUpy}4@PG;+sHl{aYZN139rxJs$*QX{CB9U-} zk{@*R#a<*K95UK^{R`+s8PSS!qpjC=O%Nj3g`m;ai|C>Wb71RLTo|9NS0SvxC`~S< zc@UBzq>z;6|B9{GT^Lk&?+l$J38_dV$~hzuK#Fin{ujf^#-0fyD7QyMxFylfucdOb z<@%ce|EB>b=eHse{T$$w^&pOqn5`F{Z&$TkdrEA)^p_8cu&QwtkyDK^SA~t2UM|pz z)|QS=Ifg0knkhXprAMap$dn%WC>%3%_Y?h6YD$kx>5(ZtO7!x^~xA%8mY z-5(Zt5|*;2Jy*zRm@B~~et$NlM=?1+z%)gA zKu&7LO?$35R18h&(fV5XOeSY;oYI*rUs?U1tr1LZv&T`J4YJK}g zYxyxnp)i)K2U1;AdFai5&0cIPuBaSH&09TSQ4S???<7(Fec z{8)E+`P)S~YT%c!&vIEk!-wX80ch5qLwFIKB95wwW-&_{Dm=C+&dx7a?Pa;tThNvkC-IoExpSz6iPuiB6oZ$BEp(FN1E4D3o9m&SmSV0i7T9OXQRF zl+kMI9nkSzh%zdtL~s`l*=lP6WNuedp&{)BF8EW?&7gAuQoCZVh@Wwyt4$WBHF}pr=-;awS%U-;x-M2Z|vZ<9VhR5T`96l)dkGv1a zH{{(Y4Cf7<{DwqK^1{a=@Kn|(;j}tG0$v!(v$3Cr&S~w_d7!Y$P@atk#}udq;YNpm zd|qULpDaJLU^kQe@CB(nBivc=pTW)o{=QWHiHP!wIeTYYimMtnN$m@zDvw?EzrIFdo^lU(xNvWP)5|Lf#*0WJ8Q5T}gDDF7rH~qRs zI1F!(ywBA6nwwi2eVzV_wk}WCrcHihIn`4to zYzYdnuRi~E9sW-372H5d`JJ0gk+3NeHbugwNZ1q!$MKm%vgG34vf`IkX+Ih@NrXVt zb?OrpLPn_MC)$7Vkd<=XR%yxY&!1qK)l@cRNE6NoaUn8M`xhC{n9M(@`1wV z8CGmNJ(eQ{*;T{tLPx(l*PWBkY16X{vO(1Vs)h`2+fx}&SOYf&tb;dMU&{JXU`PEv zPwC;=UbgU=dhbYTNBUu^FX+?jGrZZ}jHg)6_Il*$qx-hfw!+h(ghsbwOus|<<$`X zO(A@iCMjW%!gBVIB6EQ(B&n#%%jXb8CKsHeG8gQ@OmZIOPt|;ElAYsx!XYkQKyWsT z%atnc6V*c^$qko&qQfK=QqlK#rU_jSC6XeQXMXl(>n)bgi>ZQSl(WSYB+8bAQAV~9 zmUFh4!Fbrpi%Rw7Ma2qnmYAJ*SVo;pXeV%9Sg@pdP1kv0u|GIvhf6UT&Y6rsB*Wot z1hHMetK&>j^@I!(i{n4v>{fyfT!{p+8hrm_PWb-E@KF?1tWVPuEs=DQ^VSQA?%61W z*Z^F@E{aBRLefgAi*fLT8ROTP%q*D$c-f{{d=hjZ$qNdJio_Z)#p z(5Njj47yyYqUeHATVf_U!sk@yCC=$~Csk)zpj#rfCr*vp5-UJgAqpkfgmYPI;Wp6G zd{MtdKCPWmTVfyRcItF|ZE;S}*lsRvWMt`XOvZMv0-b1ATuRaSwSbQ1z?h8uo{;!q z`|%Ww-;ZPDmyR2;=pR8!(fG{)T`colC-I|uFQsVwT0wWdRvhuyINona{KR&R#_tC) z^80@hKV1Jj5x-qHa2>U2Ik>*@!xW1)j1P1!RHA*w?+t*&@2fcE{k$D?V&9=Cln&uc z&c6+GrN|?G_}Sx$_`%w~II6Y%vgnaj3kr(d1u6S)bn;<7S=t}c!8sU#r?MYPIPHn2fr~4Z@aLs+(!qHZ z_-LpB8|#lKpURF$;M15bL`ysNG`l@~noMFKKsn-$Z)1~qji67lDZj^958?fCHPUYV*;4d2R z|1#ieXl&ZkAcdqR5?T||>B$C8+Li;zB>aC(r-uv}B!wPA>#8nZ7r)DcNi=#47gPbX zdW>0-3O#EsrOS1CQ%f8_PH$^_bsJ*AQ-F7^C?o=`t7vW0)qao{8Mv>mMhgqi zwnA^pFEoAlGOP+~{&0M=zq6_Z8boc^uWD)Q>NNFyOg$e{&&SmBG4*^*J)gLvD4Tjd zMqiupNI)d{dFV$zQMIWtPXtLYiZqf;d_<8Jk_qzB+;^|rT9m+mFu|tdaPsGqghqfF z%2yK-Rhh0Iy5O+c)bm*bPkYH+P^RN>;r2V3Su`DoYx;-y-8UVF$K>rh@~I~AUqsA! z#L7Yb#m) z1xKonv9vS#$$7-Oql$|l9dn^=Q(V+HeA&8Q51pT1fb&asdd@n+HE@P6tL^c8^61aJ z->91NQuV+^8Ql)&U^jO&LABF{l++&2%STzSw^H59-p$@bxyrj|Z2Dxsw{q3+o;J!W z>Ss$XKjO+|IhKd0T>DFBDMLzHk0&)${|vqUX`8g3dSd8l+ELMxR{L=;JI6bqvUB?} z0-rXTxkr^=_N7mHdGAvecr6cG`3z7VVbquMk+}_bWdCCL^%*@L8`0;_JY0S3WC6=@ z^g9M^Y1PBWAlRoFzrs5UBcjoHD`y`rAAa1^H>{{Ew<)!wp6RV<=kh-G^m-)B>$Bm+lD9l`ni$7e$!=-CDK_iJ| zL?n_W85C(gL1_sNvvsHJkSZgKt1}^si-3{Emq1jTvivbGY6>_Y&yNm-vZOqr%=)Nx=?3&^$Tt*QjVY z7j!+yr~XqpC4$CwzYV$#yfpHUv0WSXEUgpqqn}qw#BUc4dAzeghoOu~M!G`KdB#vN zwhwt?TvXf%I%E^6 zoaZY+cL8rL@{e(zzXUol&-@X1oc?_sblyl-95ashEvbK}>-5padzve@`P&FOF<#tm zc#1aOn?V=Lc%KHH7%zXs2ghjrI|{m3);B9B+&^q>o}%$916?fqZk709D#zvbXpHK{ z1uoz#IFb2%8FX&s5x+$`5%HsVUdxKO#<2D$30~jEYIpLcO?^yL zAJf#wH1#n}eN0my)6~a|-v@^w_IW&#YEvJxX>v`9u+BpKQ)}vDnxVKv^dCe~_a~zO zX6j>dM^&airm2rv(ainDCZPvrhT<|qan&KjgWuQTUoxJ@)iIwklDK_?m#L50#C7bX zr%vtJ%GAefnK+zVu-V@ZO~eksmQL3qziUx-;09z|=WA~XwruXG!xy|de|vjtdk1ox zg1*gl9bIkM)*T%e)c6aQecbdhL!T$ZI+>xY@E6O(bu&ZEmc*@}DOZh8M>AYgd?(cm zBSHg;RbO+_oA0ei_nzjR>t*+x>&^9Aa!7|z^(rTdFS)DIcj?&S zx%ensm~|NPgCnz^3>>@1?d@MRd`}C@{c3i~pe-Gq)IQfeFqJ*#U<;JrO*=BL|I$(G zH!d5s4lX-u-@sI-d%($R=e7kNJvyrv75~UHj-r5Bq;WwXhA_MMQbfkZLPKKZS4cJ+}3+V(7)E&Y6Y>ak8(@3 zttH&{CINC&ZQ=j@%{jA~J=wr!S6e^5XW;Db{APaho0;FtIXUP29+SyH)px+($I@_Q zvRUjmkUJfzY~Wm3x^Yjdws8sIre_H%DO+; z*XC-2rK56qS?ce=2J)y8Lo%90+zb6vs?Z-xw9rmT8WpJ9p%b1im5WoOS;Rij$=VaE zPB_oN?<=tB5M@Ln&Pi1$cl#00*@?iAmIIgRz74us0}Y`qIApck5a>u=q;?beBuArJ zgaeu~ka9X9XM&q?K=xSpT5^K!8i7b~JI)1v%KjwisJ>Bs2yNf|1!K|nm6Vif! zR$cB>NEM|g1(($@#@IHriS#e0?RyY|8Xjl=DKecBiL`xB3Ix!CS$ILh>0a0%~kVf z&2h~tnN?a+I(vCpsdH7R%ZU(CthjP%WtI2J>PzwbQt7Y1qRP+Dme$mItLAv z-Q+sHup_C~;me$G*IPS6U5QIg>{gIy^YogWa9wh6OSH27u`Idj$xXT$cg2jm(iPiI z2Jh9;?#YR+Q*(c%L?vhLuQa@QNV}=$qbD2fcAtcX#?iH@nS~4E|Ihk#iBAh-VN|9fHbIl-&^3MP z{-?d{-~~@MLEG01?ONU8+TJgvGUvjR%LWUy~ zhh<@v@>a&11<(RI4{z(ubW{P}*PE%j^DEp7tB$>O8>f8ItGt!|X69k&|2S0&AW_xi zKj}UG7V&zZH_evXr&xbK+4_F!OPhPIw%*?BP+zUEBJaCLt=4zXJ*V=wc`xL>l9zte zuDE;_9+Lzg&$;%`H8$;^@GYb2^a0+R-7_*Qg?h6dR|9G!(xjDhEmEBhYoN{oI1cCf{vz2B%#|g>HxnF1)C@%T5)dF0X`18 zcyxeIg6>Mus03SZF6-hlp%;rs2RIpY@#p~Of-W8%;8xJZ)&Z6ar5;!9o!R4WUfeps zFxo`=m(u}0gh352?fz3w@L_5{qyzkqC_I&iRT$2)v7Zkk&=K0%ZzP;n+ixYDbbtc} ze8O0!YHom16300b}kKKn+E)4Hn<2zHgg~o-;u?mdJs}qO}%35 z@1oeS+|(;3q1q&K{X{>AntH`Cz4wT(9Hw4zEN_cKYNlQ>@vGd_E1G&mQ?D3hEG3)g zlUY;ZpNzF9kR5k9{TxUFre4w1D~e}FQ?EGsU;m`{EgA74BZbTaYkgJd5RdO+4_x9a@ael3;G9h<@R8@?;=#|AF3E!* zVb`)eP$9v8&yuS$?SBz6;`QRw^bo{C`$+D|{^W*~jn+FXcOo>t3z?(t1ppT~p}XT+ z9Q^RWvIuI3K>m04w1l~C!=n!9dtsUM+D;BsM`yJPL9a0aT^&H_cNfY5rq;o>h^vD zx_ESZzXBaCU+TY@R)U*x$o_pNK^Kp1Zw1yjNMrc-m6y#Oi+`WX)a`v4avWaT{ik*T z7m0LxKNbie`S<-q!s%Y|qJ)!f?@b9O-QFPyC*9uPaZr2Y_xF+2-9g3nfokpyYP!+% zaHQEYz56s@M0(JfZs$zE*UEI+M^%no&GwceV-5+~~7qdiP1*ef&%1zlsiy1{1Fa?&NMqOwT^$ zL=OD=c4cG?e9fB;-J0g#r}_1zXnuXOtOtZPZsFk{d8hg|?VabFW%c!@tQyK)-~*h# zp>kG*^>9Xib%u3Fxwd99c5P?&{p`XM2Pn5DqjJc)CiQ&lg+s5h3n^!zPWRUX*Lt@( zzJ7GQu}|7l}Twd$QLJ>;2S@>`$Fm_m?`X`}^>8eL3jXKT5av zFxonkZjWMj%Kk;D!jnt=$2?hjQTa|_WlUEcyxP%pu_(&>h{PFFdp4r5Oky)BzbU6G$7%#%gf8>k3qLL zcm5nb)aRLFcakq7Qp9g>9BHU#bqBk9x_SalIJ>z+gE~%s=@CJi%|d+ISzSFHh#T0> zW+DEemgT>3RjWS;uc6j1jikFL(7a}CcVKlZo7IBvGpqfpx&j?Q5IKEh1~HXuAcW(r zKu=FsThrQ})^6U@sGni&9jy+{J8w9z|5UVw&c^mjwMnBVuR@af@1n}>QQmm8#!jG| z_!r^$$ZGIvI(u5XIs@%~VeQ5D$n!V!tZn*0HGA4)wI9tx9JmiNqdH=(cWZ@Z#Av zJLWDhV|rsUHF%N+@3dbk|5Y@5ryFFv8o%)F+P>eFu|nJ7l#NFEtb5Ba71^OrO+4ZcwOe8j)^3y=gI!`2J1%49cOZwgKpx(QDaGXlApMZ`gL!{A^WPbsjP>d0+ zI5#TE20$m2N`fcBzXqL?brPI^IRJFnYCY&C-eS9v|s0aq_kh84I7~|8x33q;m4#`<#SN0R9!=Wq?y~kT!4+@GEgXSI1e!#Vebeo4bpuvcg+jv2^*OhRVft^%eE5V(-!wS7^m6N16w% z6fu`p!eMMB9^k^=EBV_!4Bn%??l?j0qER)1vB^o>$CZmB+$LB3&W+OTE?|XF2GbJs zmqitnlT*qGEG_vGa5gOXl6g^;OVI=n4Rp1zQ3famHcD~Cf6;VSG@TWr-85zQfJBubrmE9ab(*TqGnjO@*O^-pCh8~H z&iC+1@b-iUi|7q}66a$&E5%p0u*o zbXG*%Q`$c{A@z#3n)!1}67}_6l#}L=^kN`ett5J3syaH5~@o^ClP*~r1h{$LunQ={th z3=}o??f&_|Sz$JH+~H+I*2R{-^Hcs`ztdj$Udo`o?|l1H?l~3C+-vi{;QgP2eS0#0 zn7f;Thg!bP?jy*yPYK@ZRrb^Q#HX$s%6dQJhx0i_iqGL=_gTM9CI9ASJEjIR_QE+b zt7hPVM$h243U=tV=Ac%_`|bf|-G^gJFw7NU2t}&oDEL*iXrxhRN-mY)mvnXUDqP{` z6-lHJsm%V=u&<&E8ET5Yzo5|O0dnO7G-h0h2W17R|eryVciKeWXikdMF0JrYQ0OXFH!4D)%r5EevVpSuGY_0>*uNU^VRwVmiiJGjuITD zILdI$;X+ptKa^TiFgf_8A0&d}JaY2dcpJ-5EsDZYGi@7EwrJA`5zyqR5OyX(%p8=h zOvNNjC5UnwYCQZWMDgEf-NHvs(;l-0Oe=2z<;F>HFo)t$9Ttbxk>ap9><)(`)sf~% zcVsv+<$$TQ%-me)=sOoWhLNQDpOz$)H%y_ms;X9WBu&jwG8Ga-8Zv3((lE3|1hIBk z==m*r{(3#1w1Ts<8QTKr0%VFx2`8iv=dyut`7A&LeE!gTW1>;TN;JKie6>=d>y1H3 zEQOk$iYKFDBMz#I&htc9Cv{NfcMB^0S7Z%obo6WV!(E91T!^VOrb1-M)i*+}(~U&H zOLRJZ2f_JcpnE`~6Mdhj(}^MvE^{tBJwu#V8|bP)7pq;PiNPAs)d=PiY{5CECz5^$ zI+7RlOXTBr!q!SSPT6yy3j-1zl~W>UYN-N2jjP2e6I?*n_yP`rYep^5nk3aES z5A!T5;5`k>62?pIFw!&p2<{_+xNs6ekTa&RZSm#JruO(-XfR z;K21pON6IJ(9xa5nD!z=mfw#-=SCilS6nm1??oK)ybXa)l%pt;evLDk-$~Fpkw^S6 z)jSbDSh$qwCM(=TE=T6^W+E0YS5eOs^zZHp zk-36V->zxsWv^{Xfgh)zw?W50Y^)N+YII8%aweC0H*Dj=tzn3J{8lfILSVzQ+kfgm zxB#`8Q}9snD)3L?NW(!^BL4$O^t9p$&jfM_&fPj*4Ez?=#!qeFT38!`Y zG2qm9E!kM5RBi#+2H>9*#h|}7syvHb4}61E-W63ok=+LTD^fW{lMu;*2heR2PEWO8 z0sdVWvXRCxt^0=P>me=4fHhW#A)e5w4ksPbC& zP89Ai%%6k(cT{;Q`@4jT`{Czx`Otc&w9$ayW5Dk;;Jb95qJD|qUx6<$;O86g3uN5N zyTE_wDJ|Q8Pcz_d1HR0FhYa{u9lr>?C(z%^f09*LB*fRSHCQCe-=>>&`MW#HMl}gr zy+-?tEk3{b8S9HE;8J&w_CYmOLKf|B)QnYK#if*k8!{Z$)c3F4Zp$BY~%Vb*QVY zC)iQh+TGmM7VZgk`5QXQ%+M~e?KRBME@o(#u__AqpS$FOWtf{Yj9KW~%`{=VIdgLc zb90777Y~$WroChAzn`YPqiOF5!z$C>QF{k4?H&2f2ryVo#y-fjcO;`x@x+pZp`K~) zs9lz(y(4*-&gQ}x`7o3C0s}Aou{Nvu0& zXqOM)T9Ul4|F4C18D5qVJI6?tL7|X%ESCt!u^TzcRmW!BI9yY^{YMlYQEHNSgSQkP z>8q&iJ2iLz5mv>f&hy8qX}c+*}l+WSqf{nhfZ0oJb37cb?O0deave`&Ldvs zRmEAl=OM2Zr3`1DwzTWBDsx@oYSp(jm>o>by|>YFbUiy5-0q#fH_vyVF`3wf*K`R^-v_7jg*FPg_5 ztnFit@rT`0-BT{~x%4t>iH=wD+~w|%Iru(a?^e=uPCw0al)H=5->~a^-Ba8JS{qdRr+IAqxUU`>a_#&X zD-E+Rm-?5B%YU&19dc= z_A9B1?-@w^bKXsR$NSvgy2=;&Sw>^!CBBP&9?a73&;4;FaVcuMyYjN!*#YQXW)0M2{I?vhv{iZG0Lt<7O|7D;62IA1iy8zp;H%Di1vd7(S94jBF3&Kh;~9c&J7R2pX^qt{6>N>3?wTuHiNNG z>-cR1(f$U4X#Y-vX#XyPX#XC9Xn!j~wEqQyXrJ5gqWv!s4&iMh2>uTdoTXb|0slJT zm5e<~5awv#Ac%f_halwp7(wKJmmuhO5k&su1ThIu5Cr{?b^J+!pu>>jUW~%dld8IL zP^>x2MzIL7lDKI(7TZ{uqK}aTxof6&IXW+_%0zi#&1$^P)_I}#iSnZB3bKV0iOvfb z$XIwmB#|@)XK;wvqHu;VCFMdxZ^yz=o(bX;JrlTTaHhJ6ZoK!J!bl%A14eK5+6}22 z9e3F8v~5b+Y`x2JH>TQ?-NQSM`vGqQmpX)^8{U0r-Ww1au9djFE6%eq2lw9iRA$D= z?(-p{&$vRF>eLM{3v^!&EWfFgk8)g*akVyCwDz)+OmoJ$kJquofo{6_e4yieJ}@R< ze0^W0sIQ^>HZH8Y)nvLq=DE4`jICiY(p9H^5OZ_r%yV;^=8~VAY5Lrtk*fIT1`Ao6 zo2!!%ma+H3vC8N&WQWTTWF1LlvFy$68F>Zq)pmhCqUmG1ZPC>w5?z6@_Ox+Y5cbN)ia9<&u~#UvcwjG*4%0S$OuuLrny8#m4+)- z`y(@37Zn;A^DVz@)Jq085q`uuKgYq%ARz7NLLQuxmqzV8N_0V? zkuh{Vldq}PQM)b#g~$01Ku}t1*N)nn5R|dC4?s}Vdu>IP>4HKdAC^Dr(`YQs$Jnn3 z;_q)7{wk#5ts_^5g*yBg;A{&Xp8#Eems37wub$w1#ySb&4$(t!0pk&9)9_BdP0#-^ zK@Vd;(aT@e@m~=HomB;dbJ5uZ!N*AuZ-%!6uKF0>6ba(Z@IHcAO5dk)To}(1yp*xu z6SOjRoZ!b9`x`+oUMkU7+L_i%5PYv82tGkQe;vUT#x@Z|d)&VT?frsq@c$!0@Xr8m z;+sPdd?yjaYx!h?;6H;P__zq-s3YixHy%OIk%ud_+oa>y6GXjR2!ie>dj5WbpgT;k z0^=Zve&vHV$>Acv$(3-YCLHrb{wy>vZa|tBN-FM2V9njJvj}2Q>VCuAd06})mo61v z3ol`4iGS$;C+;qf(ep=t^oD=rAeQt|gSgR047&3%Cx36|A0f~i{?P%wE$>mZK&U#uGiM$4Xc!T3_`-qB|Lb5O+p~*^i`BR9uh2(KtPN zF7*Yk&r$py$H0Hgg`gAZ0B@n%2O}N79s|#o-!b+4LId4r@D?~-FOvaof1DqeFV4RX zIv*FhMkV?_Pp1?35j5b`NcgYls*x^rn*O0lrxkQqg;C=u2c0M*QgL2upj!aCr-{Ij z{J?2WMEYOQEfI(W+i}jbmx#Vk2r!%&@p-BHA zhH^O>+kFvqqFuf=K}_u$`Mm);Txlbck>6Pt4)Y_vlw$Fl2D*6o1tfm_+8Bl34RP}O zp2RPQ_bzt-_JB@Y7djaS#_^t%_~Ek=PqD_EiEF+}FPDLlUjyjGe9%`CO0oDggYF8g zIO^BP??)0p`o2Yp_}z;`UZ*dB4!5xp$w>DO=)5DS7<&YHsZ#zlyem;Vbe#&mvDz&L zolmMKPL2G!L06>nJ6|V?#qZ0Ys}@WoXyo^{#IHc&XI%Gb7sYl)H_EvhbYkA7O8kuS zTMoKKQoqEhv439!oft1}Aw0zz?~9;|M}FgrhxuJ_8h-OY7mxgIk@(>fi1g1Wzi)yL zPYNSaJ96ap@($>P{4g~<#TxH1(ADVWGBC>TWB8jYs0bLR5 zt2oLzx7hcM{{>w<>*eFFVSe{nvH1NmPJa2A1TkJbaYy(W z*Gnbn;#tqPfi4SNNPdDoR{!n=T|DD`UFzRuTK8hgj}$lY@T&%$7_ay{NBuL7Hv~G- zf4x}_jO+QkpcCV*I8Fba0$n`oPsJh@{S$vTW65s@=;GlQmiP(z#2W85(8V*}UxH4I zSKNC@b2}nWC~RC@yqRE~pJeB=i!fEmR0{AB)c{cvlMxeCM z&>w&dhz!vGIdV=*H=qK=fi3AG^3?CMtygfo=W1h%4(Vxfa zqHsG4NH|yQgPF(^5iL4&8p2y}ehf67IB4IY+kw+%e7}xA44lYG22}o$j5yI8>S{f0 zvlblA=Q^iKFoLtPz45B%Y}!bRWQYslPd z$lPm4IG}L%`9xiDP2c;@#CBNXTa_oc--~eaNwm7~WJ|a{!uBUz*W7C;VcD5`4V^w@ zc7kgXu4U0)YKilyL_kN{(s4CH{@k4KJPZGr1Q_VfX$g)%bJQU()kGPXdkvYs_nKd; zxz~{P4rBV>i^r8DJa)wsOEN6Xy@q%!2-El8^u3SAftzoD9SKno{a};CWf*z3Nr;E( zdmqo#nR^Y5IhtK$S;p|aAO5uZui|$f8Bx4G_ntvkzi3ds!L|GO0q!-eEDPK)HM?+?qp;FI}G> zxaa!o0+(O^U|`(!hXOCP<+t3^c3sQmZ4b7LYdh5PQZT>up5S$@mj@qgO%1-$dc#!k z^<+1Kladj92km(V_Gx^B*2e3CRgDh@H#8m!KHr!VtUS)RZ*9fk+Y_D*FsIh1g@bB$ znD^<1!kk7#D(@Sg(&1H(ZnXY!&9(XCXFhA~MfEu9xkX7PpeFgETN(o4>YT>3;A`NK7gPe*1igXn!P^3F zN_!_|aGzD}SM#-vbzTHzMZ8{SvRNT1IjXWhBRLVmLJzu0rjjKiB|y@K&_+mHv4|f# z;oy=%5ZbR4f1@E8ab&T(~kqK)Nhj&({*nLr>PfK0R|T1SzIv5gNvCbaG}nT*$E zf<}@w+$ZB>DCL+!8h?2ssT?JU9NIeS_XJV=Hy!6D`9!X56-DZQx>N8A0?UD$`C{hz z(#53F3gO}=C?%TIScz6R=cN}CU2hD+bmZ~2^)lKsDvX2bLfAZ!nFaM!=C=ivo{d~a z8Xf%_&9KSBJ{?z!G0~k%u6`|Uanp@Nz+q*?>G=3@ejDgENEJoj`J$HUr=TNThI*bj zCsP}#I!guJ45^+tU2dQ&16`FUlwb?aWpj>opc7^(A|KN@V$Y~epd%X<>OYlJB4})P zD9&~-g-xqym;Y56h2Ij;kqnHVIgv;6EAA20zZY@H z>+~_u@ux22%jwrZWPXo>PROr7CnSEb#+pChIh-QaSmm+z$eLHCZ89v@%$%QD`{V8jQisFD?%L|q0ZWHYgeGBE!5dP z>c%)@HB~yj{gB@m=EaCd5 zX^?3e)X=g9+nQkqwC>i~F>Wrp?kv$2%Ac4_)1dCef`)6hAm+9lnjFk+Im~T2bnB?r zj!@Ul$y`&WX;4MG{PdELU4=ForfHCA8WfLx37#Z`^N6`E$JlJ8W18mRkqp~0#QD+_ zlfyr#HckBhp=~+zCuW05P>k=G3E2hd+?~bk9_OgA*Tbp~j^_QDSmALoc&}(S- zckQERh4C|NyhcE--EB{Jb0_p!#;5MDaV&UZ;*he$vaV(_8&Vc$hX>!CaQ?Z6)nIxs zN3|Zm)r!#nEoY^r9KW^dqKeAii7k^<_4uu-XUJOP?X@)Jr-7z&N`<#KyU9Idoq3!0 zcds(1ckq0VYfs;9n{T}DexG$_-odOsi`BXpZKh1b*~A0Oh6?NIhYAm$d;XT*loU6x zmVE2XW3SqdZm`*pZm?$@-H=hSi#Zpp%pYRTW$uzI-1*zQ|9g-*eS_tmzCHLT&V$Tr zCNnuo5%5IJWa#UNtJk_hf%+L&`?$9hN(V4GOrD zHk@oXK0LKQSL;(Bpw!}ebD^A~JUxv?cQ0#2M17;~{x2xlhlARK)OaFY8|giHAG9p? zeW*KT536AG+>yHbLr|)n5JmtID$VLhuKp?%m(!(kacb1v4}tDEQ3yynJ4*9#$o!sy ziH4PzXg}hd^wu)nKF|qWw?sZd7yAocYrRIPINoy3<1ENEr?O`yoNk-X18<7t+1SgGb6QCm>^H#oMe=OiC`q6cdEyw5KZy+R zdp~kc^|N@~(cuo-*u>$^qI@DN0Dg8P&&Do{oKyWAHXk?zdeoAQxg+OPem1KGzAutz zW6LAwRG!OL0e?G^XJetrIh9Xhw*Y@y+*Z*4JEO|;*^VguJoddPd>VTS_|K&J&qtNd zWUm2#Qz}0cRbI^g8+cCSR%>G?qRMCU_^Ioq@^KMf)c+Ee4}4wZ(zUT^QRQW94)6!L zNf=4c#x9L2U%)O0{#~j3%BXS=YXMFHG__=79Z}^K?9;%X<9~ID!p1g6mDljNtG|%S zABrkp!oC}Y+u0ro7xouF*YiYVk-Y}|dwTyw`9lW$=X(31{CNrAC$$HgJ9ZHG6R1BC zkaYV4fHyjSe|;K5MlF!=^u0+eT$M`t5sN{rAcCG+*{c~R7* zERY>8N3_+@ z+T&Xrj@fGzjn?aioiePUt4DzUOlxYYQiC7c;B$K#R6doZA4>L*e(w}FN;$e8CNs3qWQ%zE=%ossqcu9*;B41->f0_R`K!C!O{L*LE}kHg|Lr+8OeL3Li7u{ozokUCUY9 z8E9`?-PzjW4>Z%O405}B0?lju;m9k==q5KYOy>;`z6OIJt`tBMs0jYNy*TZ841C98 z3N)f>+$KSWn$hU2c#VM;4_MW#-HPw|0aeWkI{Q?X)tD9BcgziK(t8K;cGU$PjoHD) z$aD88D4P)csr_%iTs-((w^D#Qmb^yyfa1z(%qzSCWi^f(HUYHH@TfqZfyV+_d#DBC zJ|S4prz#Ub^~^CSSTB6hC_XW))VM9&<%%{hOUTA;kg`dEQya7lAsMYuZ4i8Dmw0i6Om zB`w%^?CvRPjW8q{*meWuGrhhR$;dO%v5e>HeSYQ`6u;LcU8VJcq*(+xxMn@a0#u0*N!)ZuYdA!mf`7z&b%PpbkSj=b@w{l;ijF}L$hyn zV@2)6`TED*y{YbB?beY0c!eUDl(w zvAQ8^1}hreUp?TtkrnKGZ+%}$#qGIka<`wGS;l;gm4|Yc?WWIsz=Z5$S>UWl=q^&w@jYy z>wPz^|KT*unv=bM)^}jk=G*h9g!Eig_%>&3Z^=Jz3J1b{qfWnW#K>pZ|4_z=wl<>3i%dz2N3U|kZ5WLhq^wWw{O6% z+E46XuJ%5!Ugdjv$hxzB9-DTbueR^}^p}SmTW7qN{#SqRi(&TKMNecrsT58*tZV}} zPe(pxG*Ek-xjlSz#PO9pPPtv#=J+K_J?ajvT*c@uhmpfu7nJGjv3@1}7Y91nt>^tY zUmx{N%xT%V0ORh%xQA*t`7q)t8nu#%v9e7&Ss_+xs`dVRhOBOkI`xgA{IKO-b?X~L zl}!E0WmeZvE}Ltk(X;;bZg!$}U6;Y*)A0cGUJMsl=0QbL85$v#o+ZYPgo=mU%PwXZljMTR`dPR~%HjCC|Q{ z;O4xR{32h~WLEUbfpwE#Mq3!&RyOWAD>dpc#Ba$-7 zctXYEUPU?iF3s-AcZ-h<)Iv(uO*?IL53(L^JO91)?@>$2*4B1cX3Ex|9J9METa^>{ zdvWGe`yHw3R$JdGn=^8iDck1R>MGs1Y7Ymhdu>kpR>kKXIFGL<%Qod`s-w1-wbfw7 zdj}>#o(h+za@4^JaG%xgh>MO7P550v*)d_p`o4SDmk*uoRJPX+p8E9Nxy@B4UcW1M z8gdQ|Io79a|E#aN*HLZRhWp+H?p`}q?sdGS6tt9X$Eebo&9>FHeTC117HK3u&6^TD zfcuNa6?ZB-?osyoN&mTmZM9%NtY1h~X@wFkr`dLBi0zy>iQ2ro(!PDXv!sH`7WJkf z&RaUG?fseM?Eq$S$HIXb={3DdWhGjgPyqvs`!M_alqtmL2ZBd6%xM>`g74QIX=iI85_FoNe2dy4jLTE`IM9|e z<%IRh!t&xt?!kt}R|fwch8Z7L3SCQZeRF4hJ9n$!Ivo5!zf2;SS0)lzZ% z;qC_f#qbQAkH5#T$>6554jz9FA-5EUf3bgahGW#JPL=jmCORk2)qZ*8I<-h;_)lfn zbCtltD4>^VnJPeZv13f;yJR*hQWH)pvTxZSY-nM3!fj|_zrqtB*}+f<7;fl_A8wZ8 zF~qq07}=>H!910-uh3)M!R!&nh}=vQH`d`8cV5lbh0HRiQNCM`)&wRq2}ejA7eQF5 zlC>#YphbM6&^9>b2-)J0fec7_rkmg-*!~g(k&hq@ZmJ1>9D8OHL?@OIyo|AWg5Y;0 zK{sPp5p-(So@D5=l5jU;*Abke@B9QSN3!do{1$?RjI|O({`CaijIAL!U9%0Mc5Wct z%~%&f>=plbhg0jNMJJ zQnOu(*Mb|<5=o!H8Od73#PYev9FrYXBD|;`=as7SawN_xSMW;Ld0}lO+Ap%B;{6(@ z^MU{p<%K1s@sh&KjfGbp>Wf77Vih9{*(d0o%oalz8WDY$W9Nm(-$HDerZ8FmHFQ5Jg! zu0t5MITbce9e?U1Q|n!7eTiCMs@9jO^>ftvaDc)~O0i|~wJR5BgLu2U!J9)l&%R4kHAg6Hsk*O`iY$W+2nKIX>0@sDim z#UvUtu7$Bjpu~FSGY|2(A+C7lsw2&jZqIOJVl76}#W?dA;;x>jv&BtmENlxROtrsL z-s~GUq;7QFVZYP1DP^C3E7)A@JtGj^9A=Fc7s` z=j%6+M4EdispgDR74KC&yk0SZTvQm7H%?KVXJa;gRTpHYjUp+mA}*=v21(&DiQj5b zK8A_WT6_M?k}@`z*u-ef9ZjmaL??!%=H}PR1^UEbOh#s>yOCVTSE}}dm$ul~N=0_3 zMOE~R1vU5zKr3UIlQg~pwp&KMSip`3qvDA+>SDo@EnfnOG{i@;Dv<_d>;dHB3PGO3P z?pYnauEUE`kY9%PFoMKS$3LOt-vL}j{B`(K%16I5v37}Hkq+1C@IDP8Hj#*anA6aA^8{&1OSS?m@F zZ3@Co8jBNxUFGHh)3zd$G2@!k<9zh@Y%*%fufRF z?ni$1AfqJP@JHG;5k~7lY7MJjLR78R+8ScZbApp2W{MAKwREJnQ8s=!E?6RdLk* zy$?E{UM>UUcs+Px731aV4-m&1ZyV_18ShSspBPUpey_*L?|e+E=pSC~c_MyB`Bj5X zw5OACU|cU7Kqutq(FtSmyB~B{%Z&7MBfmdO{KWH9tnvOGbn(cq5)ZOsyyAWoi(fnF z;^Fs%#81%28t+@6i${LBxG04DY9#p?@6Sb`TNFcn#`V_)Ix*hG5CBdmb$BJiklHZFssAGoX7Id31kShJzCEOVez|;L(gA{-N2<;fN{-n-VLc%G{FjQYTMmj;Qjm*0V@N zl~n5bm?Nr0J7a6^>f8iyZFgWb0-+dUp75c`KeD(elF6+o9M0=M^+k!8BAI+s!ugA7 z#l}>10G0+*1;`^=?Mv6Q@0qhZ1%2U$J{C*NZ_s!istsUKk zg&m=mwQ%q@xTw!%g;(Vs^#MnNCCp(?YymHGkF|*Q}CRr6r}amzR|~ zSB1KqkQytlTv}P>y|Vh!5@&Ixzy69UKR;VqQ|qmo z@9>x7UrADqMhW_RnHwIM8y=V&9vE*svBHXLHy+c^InKMD?DkdH)tRubt{(F@;d`U( zDU|3v(%kUC=o*xuB;jLZ`Z>prHxk*HdF-OarH1{c623yr4G-Xw=xH@KJXi}kR5dpz z&)fMU@KV$49y4v5pHjEE+-QAbg zwU*4q7qQ}I_%B!Rk6Oh`%F1TJY561O=REAvtbNsO9-}{Ve6GvR;yApNJgD<49Hn>Mg zRD!M{W}>gb_(&f~MAsC-hELLQN*~ZgdH^SNIH+!lo=HlIY&}oUVt>TRcLX9qqfyUR zbmXf!5`lhN2sr%38d1>kUHz<)WZch4rmF;(B5 F{|^;PxBLJA literal 0 HcmV?d00001 diff --git a/components/els_pkc/static_library/mcxn/libclns.a.libsize b/components/els_pkc/static_library/mcxn/libclns.a.libsize new file mode 100644 index 000000000..b5b9e8e07 --- /dev/null +++ b/components/els_pkc/static_library/mcxn/libclns.a.libsize @@ -0,0 +1,3 @@ +delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a +TEXT RO RW ZI TOTAL_CONSUMPTION +72506 19752 0 0 92258 diff --git a/components/els_pkc/static_library/mcxn/libclns.a.objsize b/components/els_pkc/static_library/mcxn/libclns.a.objsize new file mode 100644 index 000000000..8016f4d7d --- /dev/null +++ b/components/els_pkc/static_library/mcxn/libclns.a.objsize @@ -0,0 +1,196 @@ + +======================================================================== + +** Object/Image Component Sizes + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 126 0 0 0 0 73 mcuxClEls_Cipher.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 810 0 0 0 0 1552 mcuxClEls_Common.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 556 0 8 0 0 670 mcuxClEls_Ecc.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 134 0 0 0 0 71 mcuxClEls_Hash.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 398 0 16 0 0 584 mcuxClEls_Kdf.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 858 0 0 0 0 560 mcuxClEls_KeyManagement.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 726 0 0 0 0 931 mcuxClEls_Aead.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 82 0 0 0 0 73 mcuxClEls_Hmac.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 126 0 0 0 0 69 mcuxClEls_Cmac.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 762 0 0 0 0 1214 mcuxClEls_Rng.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 286 0 128 0 0 273 mcuxClEls_Crc.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 502 0 0 0 0 750 mcuxClAead.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1672 0 0 0 0 394 mcuxClAeadModes_Els_AesCcm.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1554 0 0 0 0 333 mcuxClAeadModes_Els_AesGcm.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 452 0 40 0 0 271 mcuxClAeadModes_Els_CcmEngineAes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 208 0 0 0 mcuxClAeadModes_Els_Modes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 636 0 40 0 0 272 mcuxClAeadModes_Els_GcmEngineAes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 682 0 0 0 0 947 mcuxClAeadModes_Els_Multipart.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 210 0 0 0 0 82 mcuxClAeadModes_Els_Oneshot.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 36 0 0 0 mcuxClAes_KeyTypes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 346 0 0 0 0 570 mcuxClCipher.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 96 0 0 0 mcuxClCipherModes_Modes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 10 0 0 0 0 60 mcuxClCipherModes_Helper.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 810 0 0 0 0 150 mcuxClCipherModes_Els_Aes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 376 0 396 0 0 88 mcuxClCipherModes_Els_EngineAes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 318 0 0 0 0 149 mcuxClEcc_Internal_BlindedScalarMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 226 0 0 0 0 73 mcuxClEcc_Internal_GenerateMultiplicativeBlinding.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 624 0 0 0 mcuxClEcc_KeyTypes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 0 0 0 0 mcuxClEcc_SignatureMechanisms.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 174 0 0 0 0 138 mcuxClEcc_Internal_InterleaveTwoScalars.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 160 0 0 0 0 138 mcuxClEcc_Internal_InterleaveScalar.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 28 0 0 0 mcuxClEcc_Internal_Types.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 44 0 0 0 mcuxClEcc_Internal_Interleave_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 44 0 0 0 mcuxClEcc_Internal_Convert_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 130 0 0 0 0 69 mcuxClEcc_Weier_Internal_PointCheck.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 60 0 0 0 mcuxClEcc_Weier_Internal_PointCheck_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 474 0 0 0 0 88 mcuxClEcc_Weier_Internal_SetupEnvironment.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 112 0 0 0 0 71 mcuxClEcc_WeierECC_Internal_SetupEnvironment.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 432 0 0 0 0 213 mcuxClEcc_Weier_Internal_PointArithmetic.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 264 0 0 0 mcuxClEcc_Weier_Internal_PointArithmetic_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 44 0 0 0 mcuxClEcc_Weier_Internal_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 416 0 0 0 0 203 mcuxClEcc_Weier_Internal_PointMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 650 0 0 0 0 150 mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 336 0 0 0 mcuxClEcc_Weier_Internal_SecurePointMult_CoZMontLadder_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 204 0 0 0 mcuxClEcc_Weier_Internal_ConvertPoint_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 698 0 0 0 0 272 mcuxClEcc_Weier_Internal_KeyGen.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 116 0 0 0 mcuxClEcc_Weier_Internal_KeyGen_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 992 0 0 0 0 451 mcuxClEcc_Weier_KeyGen.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 44 0 0 0 mcuxClEcc_Weier_KeyGen_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1354 0 0 0 0 636 mcuxClEcc_Weier_Sign.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 80 0 0 0 mcuxClEcc_Weier_Sign_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1830 0 0 0 0 1307 mcuxClEcc_Weier_Verify.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 252 0 0 0 mcuxClEcc_Weier_Verify_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1204 0 0 0 0 634 mcuxClEcc_Weier_PointMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 60 0 0 0 mcuxClEcc_Weier_PointMult_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 858 0 0 0 0 270 mcuxClEcc_WeierECC_Internal_GenerateDomainParams.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 56 0 0 0 mcuxClEcc_WeierECC_Internal_GenerateDomainParams_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 68 0 0 0 0 73 mcuxClEcc_WeierECC_Internal_GenerateCustomKeyType.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 12248 0 0 0 mcuxClEcc_Constants.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 348 0 0 0 0 146 mcuxClEcc_Internal_SetupEnvironment.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 32 0 0 0 mcuxClEcc_Internal_SetupEnvironment_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 100 0 0 0 0 69 mcuxClEcc_Mont_Internal_DhSetupEnvironment.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 624 0 0 0 0 223 mcuxClEcc_Mont_Internal_MontDhX.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 64 0 0 0 mcuxClEcc_Mont_Internal_MontDhX_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 584 0 0 0 0 150 mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 132 0 0 0 mcuxClEcc_Mont_Internal_SecureScalarMult_XZMontLadder_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 552 0 0 0 0 270 mcuxClEcc_Mont_DhKeyGeneration.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 344 0 0 0 0 83 mcuxClEcc_Mont_DhKeyAgreement.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 114 0 0 0 0 136 mcuxClEcc_Internal_RecodeAndReorderScalar.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 22 0 0 0 0 60 mcuxClEcc_EdDSA_InitPrivKeyInputMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 996 0 0 0 0 277 mcuxClEcc_EdDSA_GenerateKeyPair.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 36 0 0 0 mcuxClEcc_EdDSA_GenerateKeyPair_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 324 0 0 0 0 165 mcuxClEcc_EdDSA_Internal_SignatureMechanisms.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1220 0 0 0 0 513 mcuxClEcc_EdDSA_GenerateSignature.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 120 0 0 0 mcuxClEcc_EdDSA_GenerateSignature_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1326 0 0 0 0 879 mcuxClEcc_EdDSA_VerifySignature.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 60 0 0 0 mcuxClEcc_Internal_PointComparison_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 134 0 0 0 0 71 mcuxClEcc_EdDSA_Internal_SetupEnvironment.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 348 0 0 0 0 210 mcuxClEcc_EdDSA_Internal_CalcHashModN.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 44 0 0 0 mcuxClEcc_EdDSA_Internal_CalcHashModN_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 568 0 0 0 0 264 mcuxClEcc_EdDSA_Internal_DecodePoint_Ed25519.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 426 0 0 0 0 140 mcuxClEcc_EdDSA_Internal_DecodePoint_Ed448.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 212 0 0 0 mcuxClEcc_EdDSA_Internal_DecodePoint_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 134 0 0 0 0 76 mcuxClEcc_EdDSA_GenerateSignatureMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 60 0 0 0 0 67 mcuxClEcc_TwEd_Internal_PlainPtrSelectML.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 420 0 0 0 0 207 mcuxClEcc_TwEd_Internal_VarScalarMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 268 0 0 0 mcuxClEcc_TwEd_Internal_VarScalarMult_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 68 0 8 0 0 72 mcuxClEcc_TwEd_Internal_PlainVarScalarMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 512 0 0 0 0 88 mcuxClEcc_TwEd_Internal_FixScalarMult.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 84 0 0 0 mcuxClEcc_TwEd_Internal_PointValidation_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 76 0 24 0 0 72 mcuxClEcc_TwEd_Internal_PlainFixScalarMult25519.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 138 0 0 0 0 69 mcuxClEcc_TwEd_Internal_PlainPtrSelectComb.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 212 0 0 0 mcuxClEcc_TwEd_Internal_PointArithmeticEd25519_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 76 0 0 0 0 200 mcuxClEcc_TwEd_Internal_PointArithmeticEd25519.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 158 0 0 0 0 79 mcuxClEcc_TwEd_Internal_PrecPointImportAndValidate.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 132 0 0 0 mcuxClEcc_TwEd_Internal_PointSubtraction_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 110 0 0 0 0 129 mcuxClHash_api_multipart_common.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 84 0 0 0 0 71 mcuxClHash_api_oneshot_compute.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 74 0 0 0 0 69 mcuxClHash_api_multipart_compute.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 112 0 0 0 0 73 mcuxClHashModes_Core_els_sha2.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 2676 0 288 0 0 1574 mcuxClHashModes_Internal_els_sha2.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 444 0 0 0 0 475 mcuxClKey.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 196 0 32 0 0 140 mcuxClKey_Protection.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 114 0 0 0 0 287 mcuxClMac.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 220 0 0 0 mcuxClMacModes_Modes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 0 0 0 0 mcuxClMacModes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 194 0 52 0 0 298 mcuxClMacModes_Els_Functions.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1316 0 160 0 0 699 mcuxClMacModes_Els_Cbcmac.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1604 0 40 0 0 775 mcuxClMacModes_Els_Cmac.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 502 0 40 0 0 268 mcuxClHmac_Els.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 164 0 0 0 0 289 mcuxClHmac_Functions.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 266 0 0 0 0 153 mcuxClHmac_Helper.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 84 0 0 0 mcuxClHmac_Modes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 24 0 0 0 mcuxClHmac_KeyTypes.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 872 0 40 0 0 503 mcuxClHmac_Sw.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 386 0 0 0 0 275 mcuxClMath_Utils.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 162 0 0 0 0 82 mcuxClMath_NDash.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 32 0 0 0 mcuxClMath_NDash_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 224 0 0 0 0 147 mcuxClMath_QDash.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 60 0 0 0 mcuxClMath_QDash_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 240 0 0 0 0 84 mcuxClMath_ModInv.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 84 0 0 0 mcuxClMath_ModInv_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 516 0 0 0 0 149 mcuxClMath_ReduceModEven.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 334 0 0 0 0 88 mcuxClMath_ModExp_SqrMultL2R.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1386 0 0 0 0 482 mcuxClMath_SecModExp.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 268 0 0 0 mcuxClMath_SecModExp_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 386 0 0 0 0 210 mcuxClMath_ExactDivideOdd.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 56 0 0 0 mcuxClMath_ExactDivideOdd_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 390 0 0 0 0 149 mcuxClMath_ExactDivide.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 422 0 0 0 0 354 mcuxClMemory.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 602 0 0 0 0 686 mcuxClPadding.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 168 0 0 0 0 120 mcuxClPkc_Initialize.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 266 0 0 0 0 455 mcuxClPkc_Calculate.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 384 0 0 0 0 221 mcuxClPkc_UPTRT.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1278 0 0 0 0 1059 mcuxClPkc_ImportExport.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 250 0 0 0 0 203 mcuxClPrng_ELS.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 350 0 0 0 0 460 mcuxClRandom_DRBG.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 242 0 0 0 0 510 mcuxClRandom_PRNG.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1000 0 36 0 0 887 mcuxClRandomModes_NormalMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 2300 0 48 0 0 1452 mcuxClRandomModes_CtrDrbg.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 120 0 36 0 0 314 mcuxClRandomModes_PatchMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 274 0 4 0 0 86 mcuxClRandomModes_CtrDrbg_Els.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 254 0 0 0 0 149 mcuxClRandomModes_PrDisabled.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 272 0 0 0 mcuxClRandomModes_CtrDrbg_PrDisabled.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 200 0 36 0 0 323 mcuxClRandomModes_TestMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 402 0 56 0 0 390 mcuxClRandomModes_ElsMode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 376 0 0 0 0 148 mcuxClRsa_Mgf1.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 118 0 16 0 0 69 mcuxClRsa_NoEncode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 206 0 16 0 0 73 mcuxClRsa_NoVerify.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 426 0 176 0 0 88 mcuxClRsa_Pkcs1v15Encode_sign.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 248 0 64 0 0 207 mcuxClRsa_Pkcs1v15Verify.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1856 0 0 0 0 1126 mcuxClRsa_PrivateCrt.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 132 0 0 0 mcuxClRsa_PrivateCrt_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 804 0 0 0 0 150 mcuxClRsa_PrivatePlain.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 598 0 64 0 0 210 mcuxClRsa_PssEncode.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 924 0 64 0 0 393 mcuxClRsa_PssVerify.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 632 0 0 0 0 328 mcuxClRsa_Public.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 20 0 0 0 mcuxClRsa_Public_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 130 0 0 0 0 79 mcuxClRsa_RemoveBlinding.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 32 0 0 0 mcuxClRsa_RemoveBlinding_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 894 0 0 0 0 575 mcuxClRsa_Sign.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 400 0 0 0 0 328 mcuxClRsa_Verify.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 66 0 0 0 0 73 mcuxClRsa_VerifyE.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 610 0 0 0 0 150 mcuxClRsa_ComputeD.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 36 0 0 0 mcuxClRsa_ComputeD_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 440 0 0 0 0 146 mcuxClRsa_TestPrimeCandidate.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 68 0 0 0 mcuxClRsa_TestPrimeCandidate_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 518 0 12 0 0 88 mcuxClRsa_GenerateProbablePrime.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1714 0 0 0 0 695 mcuxClRsa_KeyGeneration_Crt.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 60 0 0 0 mcuxClRsa_KeyGeneration_Crt_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1504 0 0 0 0 329 mcuxClRsa_KeyGeneration_Plain.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 760 0 0 0 0 211 mcuxClRsa_MillerRabinTest.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 24 0 0 0 mcuxClRsa_MillerRabinTest_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 180 0 0 0 0 79 mcuxClRsa_TestPQDistance.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 24 0 0 0 mcuxClRsa_TestPQDistance_FUP.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 164 0 0 0 0 77 mcuxClRsa_ModInv.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 290 0 0 0 0 456 mcuxClSession.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 552 0 0 0 0 392 mcuxClTrng_ELS.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 222 0 0 0 0 79 mcuxCsslMemory_Compare.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 250 0 0 0 0 85 mcuxCsslMemory_Copy.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 98 0 0 0 0 73 mcuxCsslMemory_Clear.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 222 0 0 0 0 77 mcuxCsslMemory_Set.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 40 0 0 0 0 71 mcuxCsslMemory_Internal_SecureCompare_Stub.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 150 0 0 0 0 285 mcuxCsslParamIntegrity.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 1350 0 76 0 0 1155 mcuxClOsccaSm3_internal_sm3.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 388 0 0 0 0 331 mcuxClOsccaSm3_core_sm3.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 196 0 0 0 0 142 mcuxClOscca_CommonOperations.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 2034 0 0 0 0 1374 mcuxClOsccaPkc.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) + 0 0 0 0 0 0 mcuxCl_clns.o (from delivery/nirvanaSdk_release/static_library/nirvanaSdk/libclns.a) diff --git a/components/els_pkc/static_library/mcxn/libclns.stripped.a b/components/els_pkc/static_library/mcxn/libclns.stripped.a new file mode 100644 index 0000000000000000000000000000000000000000..0f2c9e62956d2028fea21e5a0f294e5517b3792b GIT binary patch literal 628136 zcmdqK3w%`NnLqx{WRgrm2m?e72sYtnP#_n=O{wNOfN}`|Ewy&TB$+UgkPJycXx%m{ zT54?@5G^1o?b@zw-Th%Jy~;ve+uCj~ptOJ6ZFjT(x?2m~{fAW3wA;1+@AtjTymRJ~ z38KH_j#W8dY<=k&M96V=xzz!kXu?5dz3F;R=K#MY~hk+MMY(jr2ZFI zR!Xd*eDT7i@@jLg5bilbYz+(1^~&3G-g8=rMCblIAs)Fa{`_l%InQT9LO9PKZx-U^ zBSO65N&g%=D1?3f@hKq^oUTbngloYr;ab@nJvXfsF8d6W2$wl`JSkkx^AW^7{EO)M zM1yeI=ifdjT^gzL3g!u9Vj{;xXSGv*2RwX=kKVU;?U;QG3! zh5Lr(!d+V?-2St|y*4D=8(P)*e&9TtpA_yk@O0-1_lKT~o_lr)w|zd~6Yj&uqURHk z^%b1o@Cf%mt`zQn79wL_YvOZZp~%>9m&kZerO0TzU7dIA5gDD~ckJ|tX~L6xT6pp| z3(w@0(etVT;o&)>NO(%07M_Jq3D1qM2#>!`c-Afzp7pP*Gte(Q!CC6udRBPu9aQJu zO~UgfpYR+%COqGGQFy+K^B-D;=bv5^o^z1vJO}%P=MCr@`IE@Zo~O>d5|KHvPGlCA ziOefs6Pd+FMCKgOcwY00I?F~x=Hh80^E$6OZ+Jmu);ujT{d+~`%?D%8dp#mE+4-@v zBGWz}Iw~^l^N&$ZdggkSWi!7e` z1L~ags>pJlvx-EPeO|jqWR*`7S(OLWdHr6IWzHL46IuSk=y?-(Z+%c?-43{GW%BdG zi1Q$1^6Z}{vJU?#_WVqh$Vzm6^=XmC^SP(u&+iV3EOY*NmdG0I{P#SO#q;;iCOos< zuLyZgd|G5DIu{Ix>{Ms#G?DE*x2_i1+mDIt59)KzpG0<|^T8KI_Td8}`_o}{e(s3K z=K1uz`15P8i)`ol?OzD5SRQ|7z9_ttH^-l|rU|d}ym6NBt`oxBxJ!69d4>0VdxdxB zQ^LE)C%hkdRd^3n3h$?$6W&k1pw7=C>~A3FCkLbF&x?fjH>ZVn1abf56FIKiMULmJ z$jS92KPSE*a(K=x6FDUXB4i08+rr1K`XGnGtk@-j1y7U z-otQ<5kl*`ySut;yIK*EG)W)`!MN1biOH7ne7cFjy zqi*czL8h?o236)Gm;Bvb+Zwu~c&bPnP#UQ9h}FYr5gBoDz=4_+?2XT1P*!aVcXh|- zY=qLVV{0OT^}7;ALv=yShVCx3$=>#$U0bSyf!3x~o$c|uB&7lMy*<#8oZ*&mD{`tD zLY#e(jIYRbf!;u3x~!t@ABfL`mD>XGWmB6du(5MXQ(brSmd4=r9l@UXbU5gZfji?& zF)SMqe^qBsZ=e&2PEas5U;VD$?m$a&b(B>d?5S^QPN@zowY~8jxzyC#jil9fb+)x{ zS>2T&hn-CII|Cg%64~8AK?%!HQX(DLd%C*q{wJ1bbxg{p9o<3nHQUfJ);88!RESF$ zu3Gr5J&nP(*a)hU#01OA)6%^=+^Yr4fOgbV8xMDPwM08V$)bar0;rY&o3{;-dqQ@| zPT3b(A!~4h>uK7sm94U?lO@x#Efsl10&;c7magvh-q5zXU{6bTd$_j?g$t<=)zlg^ z_iCD|w58$?M(*uV{`$@>?VUko8yo@4ye0~?wbpNFs;ynqR99~bM`lnGuKKm3aji&8 z7P(?&rA{aEa7_6^{*?IwhS+>j`W;nA1;*E(nDDqtq^NNC_SptZHVb4#q9NhC9d=3lj8-LfUimNb<&tqJyqx?0QMssNLdquZ=4Xt=p{!;;ap zZfqQtr@po(txO}|*fPz;xadq9MZoBp<`58{X{w2=32v)}@7o=dSBhlyx(TQWdr9_h zsvj;y_{sA7(u%8iYvN>Cj8(+O#xcfV1wfB*5wYG%K{%>iTyJra z<|HZCu@;2Gx>N&j8G8V9`0yw!AN^& zP{xS%vI*`cjJu|*v$t+#Q|*rKoxzGli^`WZacmH1H?1;_XqA;q(}>hsx1qYJzE$aH z=x*Ps8+IZEvAjE)M`xuC=?RsbsYJdf*dFYzudQur?hdqfhP%2t8p;=!b(fDKKY6sV zE9<>DWsEjfWy>lqDrG9#*p*#W%9d4JM9L~EDlaBwI@%ahhFBMqG97KK$`&oYsFbN_ zV^?-jDOkXPWfzk&C`-FG_5@qP=l)hBNEun(3bSLCrR8c;*GSCqs zSws&LllZ}IjPrH|H{RK${8uwk6-!n$?dy?L-&)rbFg{~LcUNy$OIJs9@*$4X_`!4p z;Z`Q(^xx88S!9VI0W+DHx9MHkwQXZpbsMHXA}d_5rlG67v$r-BY}u+vYt0~^rZTq7 z>R7fI9!1A8&W><>=g#)-uFh@2PTP-($(A^=&bF+%rI7ydZTLx(9XpgX_sSkvLV=lx#2{VXr|S6 z-6k1e+J>0Q6J>FTfj1uH!q#oo+PK@A8p@g)%#=`UnKj>=G9**a!pd}H^+YBdDJ_K!iiC*)G|yl|2L@NVp;}tFQfQ&kJdjI>wSkV7 z9UZ858!R5RkYEKwBPo(;)=eu|X(d^X}deZO%Be6@^HtFo`wprn#SHl<)cIk z?`Yl{+`S&LOdUz4Xcg8jZj&N!DZiz{Ha=>MYILx=w@VrxQ@7*TjP8c=rVm*1Qn$MZ z6^o}G?Y*i8Hu)uq6)`D@^iZa&t?Syxatw3_w%MIJiy#q;5iJviJc<#XG?H$vjTLK~ z8Y}FE8fQ-Jj-KAGZK!CRSGRHjcM{A#*v6XM%4kfOF0feiY)Oou=+sF%jIr`ew;atx z=d6Pzb2R2&yMm-<=I}jj$sB&C%PgI+F))uoGM%HeC3EVMhqp9 z8fDldZ(r*6Xp3NUB$7^_vWfm+)27=Pz8VXE!ET4Xl)OzU3Y``!n$%GjQXYk4XBnK3 zD7kt|cQEL1vm0fORCl&E2I0pByW?_B-7R>F)(*<5PHdXuDw1V_Vlp>5Si(tj>4uHQ zWYL+Mi3Mr*w#oK%VmY}H3S4dNyDWi<1;M1Q!ET7amgGj$rwa6cptbVo(B7G!Df;r%h%>too?c za&(G~ak4TSP7Vm-tyL{TT9w>;kaf%O#NO-^D78iE+}%`*Ei~=iMwLLxMTi)a4Z7B0 z;}{EjTXfqf8r3Met*CmH$11I{#Emsr6{BfpDJKCo-dW$;q{bD!-5aoNr=@qzYRd>o zzcrxSyJM6}3u9?U?%S1tOv$avS179ZigRu`AJ+lpEkqso#hIsEOrqCKZYq)H`% zQxUfYI#^AtJ+&yLsD>CJa@Ea}6lH5LS%va8>uhFJD7n_O?+Uic3XQ>e;*yQpq$UsI zxzgkqMVFF-A)GWvZHh!Ut~0{fi$!%}N>hW~W$)K1` zF$__=3xe2&-GVWAQ%@*h#&eQC(YAvP;HfZ!>y%uPv2`jg_$ju9Ni@P`)Lgh(*@-8L z)#a`F9%eE11aSxK>P16}W}W25{zL5E=;}5bpG{zG7c$Wj(1ua8*=0u_2m}C6?AB9~ zqKcyPc1_&ZYl%z9v$iWTO-DHpPJ^4;aCRmqwL~Sa!QRr?f@X+SJBUK8wYiWXF%^LU ztO&O4HMMK1YvXo1CFe}C(ZKk#V~%Kwd(?9Ghz@EH3L* zurvQuXrjuCeLYEXa@07Z=jp|YuyQwD5zc&8@zib)ZeC&{*L4PaLS1H7IFjA5Omt11 z1rp1l=8jVH`1wEpc3V5S5*9&%Dqu9GVK!M(8BKa>lgZ&QSZxYVu){XGb4IdgJ9W-l zyMSyetxH1E^Kgl!8k?MPW7~(+WVH>6$F>U@6w@YTNJ}@S`-8k>ZP7)gqss~KmB<bzGVa5|SgxcFUPTYapUZhn)(Aqlq32^~U{vBpaE5)vNa;@L6 zeFv5}%vw&Ai7{i_6O_p4lCrw1D_mx)izP*GD2N4XS9O}bSW<%up`Zke3|?q<(mU7} z8vjv-tHB?H)$fd~Ntg&6Uu@Vex3R6RXtXWGTmYl&ipdzJw))PVxD=c4M$7=DNsQoy;AFTu_^mYls!2s@Z#OGb{!ZEZsKvJ7LphC`V3)Gw@gkg4bj6kTDsClD4??Q;_JuqR*v}Q-?RAD>4Pf zU^5`TrD0>^MoWw`9A?H5f=Njm?riUE3DslPACl`#!Hza8z#Gjvw1xWUyF0Mkv=G~LK68jk9W)_45gd8e3lH;=&{SQ& zA?h{R(F{X#i)mMhsF6W%B4T^=5ygmil^`KTlgik1I8C;u!>gP!`=RngrW%RrDdYr3 zDsQ(Tfc}VeCjm!nBQGq#a?ZM78f!xzD;4q4y-HcPZQDwpLRoRP}7CYh1A~fl?q zXkU;((GL0aaD8Vl=7)C6HJ1cT5v`;2B@w<+i$B6?vOGnBZfnH|Nj_j~Ov4VfZCl!m z@7M@b=84>|vbGD)vsm>Q#LoC2$*(t{tnE@4mh{f}pr{7=G37hU7d3HQ))bvojJ3nT z6&b&!;)+fxrs9fDDv~R_wWWvFs8l!gL^tz9WaxA{EQ(Bqj=~pjc|v&!Y){CS*!s8< z2xG$%2H~|4Pm5M^X^??g3N zSQ*EmO_!@8mT^`E>cKP4DeF#zAwKhEC2uec335G_!I9lPJ#nqWZVC~(32L<|O{3bn zxta#(WJzG1lO@i+_?mznm+g@|HEV$kz*-SD6ecXdMhv0ip2cGQi6uCS-O+M(+Rvsl zvNEjRDpAb&aBa3OL6F+aS6;Eup@jV&YU#FMWW~{n98XkYDn=Ee_YOMvR%oZVp}VV@ zQ$td*r4Lg{ngz|E39Tv>O{b{Lp(9R)=5sd9WPHxF#q!0qq4tiBV0UAnxxJH_W!bwX zmZEA0W+LR~VTa8!pVz~C#%m^8A`TCVIF{gug?191wbAbwu}2st2qX8#UbBK?0$VV8 z?~DvSO(;Bl+;`0w(}V^(;IFWo3-3@nRCF>8y$#zdsyjL&WaAneIt{?wOl0YPqj~p) zmLu^kc*#%PO~0q7L(fdGYGWEq#ju0T6owTRotTIQZZOjq(IB{E+@eCs5wUU;BmJ~3 zcw<9kJt`U5vFNz2r==yZVcWu{h&yI^V+hyDjj(M9v~@MfH9gD{@pT@_8R#-4r&jOi zH4AQ1cvFuY&Eu^Ij^Vtb`thD1HMHH-)on|aqy6Z(P;xV@k*{EKGUA;cd^yO5=yXVg zADNwu#Hoz7uI`vA4m%zuL^fJ4n~IRunR${(NTf62I(V=m{ds|65}jE5dYQX=0DV&0&VRDi4x zD34?edR4(D_i!6L7f&qB_NxdSM%kp5!49mAM}^rmtUxipk`ogohI=_8gU`5!$fKfS z_)PoKZNc$Cd2FQklu{HOKe@GRO^`1RYwy`+nH{4`8i#J%emp2vL&W?jtJ)rugw2uh zNwo2fnnZwp-XfkuZK{sgBe$W*n|iFEq->)~MDH2%a8Lrdd@?;^K^pu~X0?e&zK$r^ z+itZ;=1?M=t0TOl8XlLKiR7_5B}h@!LUm`7c9ItxudFRq7awy}>ti0U87(QwD@ehL5}d(g;EQS{w>CEtCrxoM%D1iEPnM#AoUt__#|u4VL&68jX4$ zchno4;y0Qj?5T7|n38E%Z8pLdD=U(JvU#dO6ZcIg6Bgl5T{9i&=3EyYM7S_(WA&$C z9MuGSAGF>*no@WyKXweK%^lZICMhSnXt6@&e$q&$IrkZ-;*Httn>J&7rX{c-ZP78? zfm7KaYfp4Gl<|u(`{YWZ9Kx#r8fSVov2Zz5snxkoa~F`k%J1jOxT0W&B#5N)J?V^deU1q9JPb5lfpjE8+qh8rQ}J%36X=+h%KnGm@g~h10~u z$Z~RGvRQPEsm}Ild34b>wSdw1ID<@c6H9@52N9FbYp{}Ou_MGRVLC&d0}Ht%7Qg%# z8x2J-*9Q|uj;yCS;zYt@E10zgC-23MSY~l4E;ylXxr*apRVzC&{zCk^O>CU_HJw;G zJ-679MAoRV`dCIi+gO)4G(KzO@iep&>P&!jkXIro- zgehx0giL%vckedzkR1Yy-MxWkz}?#v4CxTd2z~kPn4m0iT@0QXgJpVpD6I0W(8{dQ2)-!7s60rkc>6q0k zX0?i@rVTQDbvxc*iAS{RaDl+qj`rrJo%(Aai^bsatj9e5zj@}e!3h&4oq6GRRb{@f z7t9_1l4rno?X;7H*A`uyjnKQZG8SaKN$XgGW2 z$@-yVWfRY4J}ydbX#UIQ{FBQ9*R_1GCHtWF(AS!)hBAC#Z+UL>uFW;W*_%%d-O^A! z^poAI{Y}3_u=v$b%|82AO#V?`X+>;DGg?1Wxnvo78y=(g zGtW{Xs;22@#?w04&#<>>>ki<3`)ytScY2=nrXZz>Sz>Jr&K!y!?01%eZt_-$3x6h+ zxXM$-uaZlO!e{VO9ty88sHQK}xLf0k9QZN^&bFowCGS>)>iGDWp*|G7Fk-O67d!9< z2fkk8#-2?M`hyPqOAh?s9QcR>&yD13I2R`D!b0Zy5 zrYHuDecU8@W(u~enYd<|^1kv0(!xHZP~*P>{vKSj4r!2c50?5Bu73w#RBt2BNH z*Gq6t)%cybelJe84f4Mq*B{4e{vtv!VYB@aY!* z_rObm*J*v91?&M{r16IUAF^bbk0s z?gdE@4&4Y%{Mjw&NlKIQ;=hNJ^rK&+e=sb?x5Qwi{BD`^17#-M@jbKn51%FZLK@<) zyc1a*^EEXYh;f|!^4eSX)qKZ2p+i*@s}9r_*Sa?QPQU|m!2@&UhWtZqM!4@Px!n*9=iyH2u%NfAh~KX5CO{ zAgarEJU6s%XwU;6ZsWwzw|>{>5_3yWpXvD4@5IE3&(sfgtLrQC1vzhdL^GIE{BX=m97EU(n^i463-dh<{Da2?iyGz zbZd2yU)tvGV+!1pLqG3${&#mz%H2$^wL^C`zWM9E>E^bLq}&_p`# z{lqy2;J_6>iO(jSC&V=xzm{-5#!(tCCtM)JVvR2$#DHVD#^so~LWmlT*Al{+T&eL@ zgt#HE)i}Q5DFmF$jT*m&5W;WM`1=T|$ya}QAQNqiV?*5 zX9+8X_!%K8#m@;B3GvT_MM4Y^qFnx!uvmzHBSg8pU1N9@i6~tvvr?1+76EU|Q9d5S zk<~JM1|SEM9DgvpMu%?%Y{P)`Rvmu34yUh}i+o~vlfO@gXSooL^5VFJ;a34t?>vS> zStVc_8r4!wU#{sZHC>KhKyTIbkf!%)I>#rJ+pohpJ|X@!jh_XiT^y${{G1LS25id} zg5wp2bL>sK(0j=I;JAh1`G5?c%5d;={KD`e9X?NoSLyIN9ljZmdO4mU|4tpw@eJ`t zG=2<_`N?q&!@r`#pJzDqaeTw@7j^in32Plb!cmSK_mDpy zkm)I5IOGVIJJ}&1LiUYdl^vspFk3bU*{5X@N8f=U*=KkO^Yt7A`UIFG`v9t8n+L0G z+vr|o1q7>X!(f$dmUWYD6|Az2qS$5IM0X(DWC0=CAey~wduZme%^`|xYlVbpW3n$U zQsXYRsdSG{Fv_&*2xzuqmlYXRL>_JUmwBV{rvdvBk#T3>WIi!1e}U7Mw;Y6xRzxFj zJ^0KuE=4~w7EL2^7#h>bYnktWU%|ySmI5QXTJr(OV*uqZ%TD9w8r@io-dDkQUh@zb zz34V$=9NyPU=KnW^|9 zpGHMN@kb6rBedoH7JTfNX&>vJu`jxl8yhw;;Xc~D7oK?16J?{%dkxCU9-a4^O3N>5 z-m5j(ykkofX3Dk&qXJS*!*_Sdk8@u1biDW}@+f+E#px)5t1Jhet?qRZ9+pz{$dEa1 z;Ic1GydHu^pjJvTzYsTx5FsX_a2YmHIF=&KcdnDjv^bIo zz-p+bq!{)uSXhz%LXE)aO^$gcg?!EHo8{Ot17o0!D?_KmB)1qG5$@Ofx_z~WHdhU1 zh)tWrD+=a@k5`^7xQ3&@DIEP_)Gj=8LY1Lc_2@7EZ02L0BNc(|fiDLto2v$WuH!AP z8Qvl_5>%ton&F27;S&WVOCz!-zeKuP@fm;C$ek4`34Ff!jzHb(Vxt|ueyDkSrHsG) zWWn5mYuqo((da-@8C&iM%!-q7`}#_bxn&Awhvp##;T2yDxMtMB=B%POf6cUd{A#3o z71NrDv}TrsvLb6!lh1?g7y&*z^a<&|JYpxA$Z^G8}TWAd?ncwG7GC+7cV zuzI||V7{?+CT*4LXk{T0`j(bncosR(fb#G*oqI8yb;x^!_GUk!EG~nFYX3)?_q5!% zC02)j=x>Toyf%0@noQ(yj(~BGVvtV`OcVTTvIK50D}HyOTi}P7`bx>i4NJCD+@R$B z-14Jjj|u09?V4j1=?4Lkeh}_$(hq`@BmEpW8W^s~Ke#@!!50yNIGYe1z#Kv_T}ucd z^9Vub{hvx?Ux{$`N#t9q!2O9`MXFoNYRGlMwVV>$t+91Lc@d2g*b0 z0DTNP@?<&|I&_$HpsX)JI+Ttj4jm>PP90V{-mbANib9lLrTo1zK$s$Nwin`68fSea z-T|14diWqA8reb8;m{r-9q?&}Bl2lY{{`uAbO!*-00$WkI(-M~F2}eG zFVo>00drCRn+ZYRrRg8i^d~j_SxtXM(|@7qS#A{{y@`w;Gj@Y5bb@7b%2Rp3LYCED zmpe0r{yO^v`s?fqq~DA-F5TD5mA@=2H|c2{9|Monsd?G%9=77aba~v1f0!LPet;{k zpEEA|0S``=*9URh@}5JapCQZ~MqVcZ%r$8bBhnnhWYO48$;YV59Bnd(xpwmXHVNOYh-lk4n1s*o;Cmf>?=ea(S`DscS!vp8B*+T|w3p$uk7dd} z-PXGi1&*#cau}MEFAP5FFo)rrj{sZmv*4p1>P1yfs`okY$@>O)cqEfI0=^Q^DUW?p zvUC(dX*%+52cMD0`jkxGo;2m1vgGkToJ`(pY08_0%ry3~Uo!HXW9QZ2+XT8fO#Y$C z#+1jC;A20;{6p1=$m6w%gG+G$4IJG<bmphsyb z$71psh3cN&oh{gC_EvYM(Vu_eckok7rk$BIc;kf2u@CLkWnzBeNm1fE<9Yqmj^l6i zeR$eQ&+A8beg#)qr`;umCo@XMf&0S~yr((Jm^vUzekEi7{>;B}byTj|iBM+f-?gWm zbJo>d(|m99y)An-R}KBu#A>-J%5}c_;a4VxPpE8C4zs#u$1d{&mGkZL0UDu-d(_zf z{&(A>c7x6a0#h&OQ=4ms-vne1FZ5w(radER@(6>#I%W>lgphUwm^h?yew%%aIm|W3 z3N|0-zm0728XD)@?Eb+6MeJ9p4_$Ypzu~Y@+5J~^uI}d6 zwlwDIDl3*@mn@Ib=jwWCtkvJlU~2z|%+>veG~N8=ir37ggjo(e+ktx>c#c|kipXFI zM2`#((ySvx-l3xbqtE5>&JjH_VoIL%B~$zuWK-AdxxN_)$Dmn8=CwK$9x|w=f6jsb zwZ={SuQ=#`bl}cCa@_x^4yCV0<3=9+b({WSi~bAEzsb8K~x8!NMR=r3Kc=o+7v5o-_b*)m5s zH#hV3zQCjyduoUGZ14RN~1HX(?T;t|A_fTR@C?- zI-h1{(&V&Qq6sxc&|5hSus4M0Yo!E@Mz#~@I2SiB>GL97_GD;49Aj`mL_eDQ7U+X> zf=#X|f*;cq66bx7d_{zy7ZbuspF@a9S8IG8A>_;_gpdV<81pYAM7Z>6FPBUHa&1zM zVGw>j=@^`{os+*><28i1Im;}>{L)I|psyhWzLpSl`sOa&aM4S?eRF5%z86!E>;`2H z6VoSv&UV1$b7ycC=vTOrhs=9-ww^mf2D6`ZgZ`Fvpj;E`K>0}>ppRL{M8~`q$~>VC z)Cs8rbe45Gc{L#mTa7u-I6L3H$ILRK?nwEl6EXROvX}Bfe@pUF2NTLiU6S%aAA@`~ zPdYJy{ivgt!2Wpo#(t-K%l@}(Oo3t*rA5luEdwkAo{J8IZMPK8Y!zS`;H?Zt+ulhC z`T>o94v_J`0Lb{y1CstDz*3C2Ut&1mYYazxxn~9)5!W0`;j3N_SOz#1Fc%Gf79sd* z2*I}&uoN9#BVZZetqcd>W1TRKEJ_Z)4OS7`hJ#0mTiSoD?|89Lv@B^HHV*tw4%g zJNfpe$@gHIeEmuISQqW|9!SFHckmqq-v%Z?A4WzEa9QR$ob#R|xMun}oMPHpH_CCE zIJgwAA|ufaM-D@C^09(ZhdB%%@2j@nI`B~s^`hD))w>#e@?Hxb9?9hG1z!p1l*js% zEFH(vl=oXp9-2>5c?C#BI`%by&)A1%m{i^_@GS-19Ldsq%#w#LHL1K;(v;^z;TZeS zBP5I)s&AucIAdeC7Z88X;$v#KEN~LZe{2Fo&TLLRI9L2d0(4D6a^ov9EN|Qch+>j?v~@7gkj22&2z` zJS98r=zQycr)TtTHW`Jy;N6G&K%)n9IeKvZpaS$LOM1`f;r5ntuMqDQ>QMS#G^n~O ziUkpcie3tQGkDDWK=gj0=rd5!)R8Io!7cmkvB&;pAWCz}erLgLIze;5E#M9FnFc>hzn2 zdm^v8K7m5j)t`1gJagC z;1Gow5xkZm_A{C^TJBKdH+SOZFF;W*O=;M%H90X61<#HJ@fO@mHNTIM{aE)im6&H) zCUMt{d@>~`lpA@LCHt%wJAy>{A z-jm`Q^*sCK1CS{949yQMi0l~}clO#qdtjp6*TY>sIWdx}hdxyv=8m2f-XjI`t~;6g zSiyYG%gl)E=~)uGG4yA>(s0GuaZmhmWLDoH|9&ZtyLe6)pBgFYKQ&Tz^wdaUUwvTD zmXEZ=>Zlq1+iL9S`N;g=jMT!ytnu85lvN(``1}20pG(>^!CxgM{&>o@{%icAxJY6* z4}W&EIP&8uc*-ffC?w8j=is?5x40T>8;vWl;d+(-=^EE*&a0ew?e%--|K`Fv$d~IQ z8KL`+Wj>U3u%P6+lkR;5a;_dg#YHpQ;&mI^!T?;k^RQc~h9SMN?KGb#(*o zgPzZmvTFGH<{uBgDdRjZ!lwm`ygbzFYjd0oU%E} z8tA)oQ~l*FztVgSgkpG7&WM1b@*;JotaX`yq*THiCyQfgbTz?+Yr=&eq zgY>#4ouqCtd)2vd0{NPec^IXdF)j2NT_V}XQ0AX3C{eR&6PfqAtxU$ul-hZhb=G~p zPn;fUDCRRyxtn2k!;0a8fSI?7&QoDHA9*~<+R;_y=Kg<>JnAZf=Tx~xvY(PFJ5TiA zvLD6m0q(K8N5DEFBQ(TZ2x2hJ!Io7s!r( zCL!d{Aq4$uLiif=)i^08`*{c}BM!%n_aq8kOo##25<(aueKr{JZsL$rMF_iU31Nqy z5c1@G1V*kV4!P?HF_>y3gxp&Q;m~nh!U=-+5Q6`09kav1r9V{$2vbEVAoGv-4H~b} z`0aqXNMFAWKcK^(W;pWkE1LcbO&F`!U4h6qVbb; zn0d{?8L~sxRav)DCtE{TT=ToP&QcE3rIOdX{M1q-VKB{}}jcakk>*nC%Y0zs9*) z<2M5?g#4WvzZUQW@DFI5zQDU7@36)rrT}L-C3)W!zY`JpZ<;UMqQB=H_ZYloeM@u|GWl~I91GB!#GAV2 z=kiTmrFc_UX;G=?OwOT+&rHOdyxem4)8zx?Qr@EPtoLB<fk5s<1A~ z5c6Ix|ImkAYCMphjsiby!8})HjQpyhrgF;f^N;uM^S{ggBHlPA)9ir<>?y)C z5YJ=fwJ4Nz!RKD)zo&Vn|IJ@By?y?C$%`~EkZIO$CqtT#6g*Q9N%M5eo-5AgKK9Fz zqJF0DIy~jE(to+MWmzcmf={?+>}`g9qH56NvU8wn_`Ta{p$kuypsccCSN2l*Y({tm z$9g$Oo|O6~o-sBpl{QgEt{fH3h`c-Pb-fGimm~A~r7cIvbv$h&jzSUxo~X@*5u1M^ zZT1a#kC3{QB?0>~16j>?`afi17CjB3$}t zMfzO|2yfQmErdu^h!ElJgy83WfH%=DLWGA2;Y@BPEK>Ia;&&29{JRK&%Q-#7yN5V3 z@m@mE_Y%VXj}l^x@c?0wewPB$+fN+f`v}4R2qD5hMTqc&gpm6fA;KRgg!A|WA;MXH zt_&h?j_yZWLWq9;&unJW3uqby<0MV|sbG-sL%a zh1te*OQKvfdFa%2ae0^}+gJT4d5C-1CCEdiYsDye=+tH9;qvtIkQu0S^(4qZlYdS< zR{mA95(X~)dwwBRl%k?@ex?i%UBAT9oF!hQ@mU)819GmhgAfB!`YD{F>?4Hpx1SJm zhhHEB-)Tbd4G@CwRYLF$5rU6%0n|^Allsd5`3{@SfSgP1CY+}BH8K7H;*?K5_)#3& zGd|~18UGd15${bx#LIQ#M7$Yr!CI|+ zx4}2ZFj+MEVC0ke1Nd9;{nRqVT;6KM!KHWs5o8_{!C|ibxVH7a2)-vJhx#+L8lW=o zHLZgM17+05OUh#zmE$yVa49+v3DqES7@CuBFZig#9ENW`0&KlM075;~%kX4+&!#D_ z5EZFJ%VQl%Ca(&7>Daf&lE*rjOy1LJ%Hz9njD4(6$>bHHA*5s9?cg)=;Jzi5wZUcSF&y+_I_>$ST3w-IM_c=@6 zj1=--1z$SpEkOrw?3i?=^gai^bkfV4fU%D-nY42{t4@9zR1ji9_ToJL-0dD+4u>lkg_tGuit?RBq}R0i{T?`P@# zZ+ND<5h>yNiOFZC3`Lb}{X>4B>{9Ky8a$r)*z9Lc{jREV7QXVK-o#YMolo)&M2ka9 zBDBMTCxr;Y~IoQOv|y&RYPC&g(J^L*A4%R{(=Vz2-CZfwJ%gwnKo3k zx68NZ{fN&;v)}*U{(Lm+i#b$tK-v*t*Pj=Fusxc?Tw}TN*R*(u$7F|0i*N=(^UdUd3 zvS`qY^);_ROplmX0Nlg%HsY0HUjE6sfooc}wqzX2eAIJzZu1?@Uu^zj%TwrQzU&J{ z`kCsXhqjlUP`Sr`CeKvbcc7nvD=PaL*4_W@{S51tIg<4=gUEZ+w~*IdJNuc}!Iw@y z!}m3qej!yqlLv#+>1Viq%*eC*ndpjtW9ODM-ovnXN&0(pcG2;&e3W_YasQj|&G|A+ zj2>BXjwy;W=b}eCdvgv$UR30zd48cgVuG^gaR>gQ1OJ}JvG^;m&N}FmA_gk@WQ`mC z84h}MFP-9F=iqO2@N@5@Iu!r&4xDYrreDyw(a*ME)90B+sMB-11OK@L|3{4*d9OO? z|7y`c09^~AtO_UZC+`8y`7w?=i1S&HCveSi4e@cne}d~9H2xakOoSQ!Zv)=|yiU`P z0)EP(-wFKhfiKYX_XGYH@G^~80nUeg2EQ8k`+=ML9sLt?&{sy($bn%AUhLnpV^?hl zpL~#ClaZfzQBPjjPgg{_8u*1+JU^j6eq%+CCA_B#PhdD=S-XLv6m%<1b-ff?+tu0D zzNLO=pkoI<1{1fT$jP|6E5WuT$<*Dvgg^7+#P4si zHLdEzlO~r&%=pt@|DDHT3?d{+2Uo?T^ZR*Sg{V>ghXv zxW@g`MDFRA9!b8nGsr8y>w?_?#f3%oZkD>?BkR>yPx_8CT9GZ$}U*zs7 zeE-I_x4(HGEY66DTQ&SCe9>hJb~PU%pmq3>^VZ+@`@o~Ezp8QQ;k_^ZA* zf6Zql_@qSb@OO%R`0@{I%kUkaSO={clknc;oYT`nuWoaXxNe@6OWbw(ftugHyw^K! z;MHxEGAmd9=gI$k@=XhU>3rXW|L^4oYBFCMV9aqM_ko%}zFZhOWochC{DO#TuN!`O zBDBlcuWk#k;4?b)L%o&Ng<=M*+gNkXBYc+6i^XSnzVhFV_lV#}+yF_`pO~?)HJ2Tv zu4AJs43DK#rg|Z;k(@w6qPVfTP0x(mpzNpN*hyc|tJjb)Fr;72H6~1v$~`=?4+kHX z;N`%P<9qHU;u;J0?8tQs#N%8TBVR>0Q>`si$SmUEn@b3s_bt*nPA1O#3O8UaBE)>* zVnRfc<1*-7P8^Qoy9tZ+d?N5#;^13J2qRY!&enUX;P z@Y@Ly&ifwYHxnYfg%IJbgmd(sDumxb9GS6IhldG~DccE=j-7L5E4gl|kg~-FsC*J(<*FJOx5?9l1C=-You)%a3lH z7^mv18}$ZL-_iY6s9z{*;RgLJ$w&QVdx(<{;Zi>6Z%IDtNkaLkH&Q<6W00@*VobO4 zCs)fy`-sUOv>PcO^tU7*?Ni$Cl#li#<%2#3`D#CoZNJHXw7VGlAzaEITmCEgDFZ7FZ%ID-L}|ZMKKedc#-MXeA)P$JdyaDDzMX~EdxFpxO8MyfV(dpBC*^}a zX8FtBX8AXcP5#?8caLlrrSsI>Q5hhbxx@@i9_B9A>^_5C!O;FlqcUy1jz9}@e(9)R&V-Y4DdR`^sv#^bo3;T1Z(j^Vi1 zt_Ex?!gGI`-lpjfkPe5aU&BWuzk=+K@{l#u)OJeph%>zfv!M0c<5@RFTr|1 zA0pl3UNB1Ab%aX5k6V$E&GPsl{$*M<{sQ0t0vNX#rw1o(>%nQudlJZ3j1bVwWt(-4 zOK}_W5ZzH_@^4*1urcLHB*M0=pe0|`1#xPm58eGdV z(zHq-eCIy(u`DT%Wm%5XmbV%OiS8?M7@CtW1U~98hv7q&i_!Zu_^5|^X-_h}&w`Kl zEpsH3_gnClfQj;0*OJLA05KhTtHEdFv92bQ*PEuir!9G`Ps!w+O;et|&xLIznLO@u zNhiG>;4|rETT3SIK$`M?V9C2Yg}m3(ls6BBVC=)~JE?se!Iw^YAGGA9+9&iZ_^yLK zb0n*OgO)tDlVtf6u`?w#*q?hB`Wb$^UDessiuPBAQSHQOvbaNz2uMd^j*f#^r z$?RJSzI5b;EqSw2$UB&(ywjFE_P@qHxMu9f!vOLa0pBKr0GjmjzGL^34Y)Dw0+Ia- zy6T8LUYj_$6fdGN!VQibhDK=18vx%ygi+o#IE{VL$>ZAYbiU(PQC61rzL_U!thFYU zPs=ZAP3rCYWZ!XVqWQ~K-?B9*yz8eU*St^(GC_PE{1G4~&&~7Tr1!~ib+=`ESBHv! zgF&^t{T99p*ObRNT=Uorh^Y`cw?upeu5ZM-5hw97z=v=?sBzn6VLy%TE^?qsS+*wF z?_Vspp*=gKf2qwbtr{`V8K!J#hrAbJTWi+ZO0-jg6p|Dt2@SEozGS`Z2xA z8uP09%i(py7pi@2X5KZtf?q%%Df4pHS#xaY%#h#y=Dcjx@T2A76>svJ?U^3F>j>X) zgKOR|_J`z~cEmx~8wacJEJxT-X7y3L&j)WC!tSM8ZWUM8oXZj!14fhU@U@}C`h7YX z#|BSGnetuI(?ae8lcW_32G&fdKX)o~<@k?}WQdQCcp6sbtQq$`TnXRDM_ht7etg8; z;3|S8E`QDV^I4e%p>4aXrrme0Ah;mMb^iXm%)tqnzZj_suOFG+&{g%3bDpcSO0L-a z+RL=VeHc%1GgU)>x8Ame72~VZzvbz?{+^tl&8Z##i=CdyTep7uiZ89Xe`;pKimSf% z@7_5R2ERAsr$2q5H1H2MU)%a<-lCW9|6zIV(N8Qtablh9X2btDarMAgW*+R{R&n;u z@cot9U;NarPkraJPyc%QvjhJzkk|hB_0wnP-&%U%Lm$84#G(EN-v67MADy^+&gZ|K z^Iu>4DD_8Xl=ZxFkz2nG$b~C&ptF)~3{JjmQE(jPH~>Bv+!yKC$$Acib)Iv!vQNZ4 z@^a$n25`8@T*D^rft4aZRPas}J9QQmwaX_|Xe#hzoLfCac)7e*( z{vF~-^l9RN94C@bjiXe5PGxeefJ~uYI=Zr_v2OqjPjT!7P0G+bm4JQvn!xmNow$w` zjQZxc4@Ac07>xRnO!>||TORj@eGTE}F!J7u0CP`~hCA`3$KF1Vdw(xps~>>OkN<-5kb*`3SJHyA^z!5Jo#t98w;k(;s+F z^MND}BhTp%6reyu;GjH~E$yQ`UYj_$6n7y2)g*El8li0;-?3YSFv?>aGV+u^z&BE0 zg9ED%0*-^nx?OeC{X;XG;ZSG>Y#Jq z1rI~#+>$y}{Kp;m6ApgPHQD_9F1(GOxA+4f5M`R_zp%XqaW-n4zR~w^)@gh;;CMt> zu5q@DEx>v6VSLKs`(-$0BCb6VR^XtV5fPH2Yz*b3Jh{WVi7T0-tOMB~v4t^vE{8x(T~Rt?pMiRYj6`r(n_ zO^FkI6aBfz!Y9g(-*;@9Kkw0Tk9i)-eKh0YoX6Y`c^`$$hdvvc>3<3`57hh$5`B%I zc1ZjSU%bT3V`V2M`s;_vDg{=GCl+v}IK1Mn|Vb8?9HEK1xudr|Mwz6XvK6@jrW1IzdNXZwby4`Ph8e8soGGfu1;pzlZ z?}|(3T_=>Jzg3b@7P%F_y2JfOLF1(9)WFoO8oD6&6vURpT_>13V&81!js1Sar5H%S z{V7slsazc|lK*NQ9Pf{li{kNg^`;TcC1a=%TShV-Eme_Y{*@jRgoecfO^a=f4wdx1 z@W=ZP9V@ycL}d34dV$8J4+gp%|A5YM4BuZ^L^^G6ThAi@v8`dR}&(>U*jtXp?tN**AT)8_BAwm10m$|K24my2<88U#+wKsU-r+S zv!9~;I|zYqC4~I2#$Dl*)nb?q|4Wd$A zf_kNNR41udP8}Cluau5Oj=VDU%Bkbx>Xp(lKS{lE>bSUirF1ykhpAUi9T!)xl#Xj1 zd1dOAQ^&>CE47az+o8jx1NSMYiT3RmmyX0bOgfx8taQA^c^ya+7%K`FRAEirgWZj} z?mSn%e6EmV6Mk!)V-v2CuO)=j)33vMpJw<`9sXM#J_Oh{Nw58bpYPwKoNEZdUrC7Y z5FwnV4{18r_8IR1P5+Xne_zv2Yx++$J!WkkIyttd-}>hN2@5?xbA-lu!q3r4A1N2mn+xD^>@%j1Lim$qvB1;A4vGA>*LX*a4@ z+?x0vMEV56&0*xVA;4UdHVJ~}7$%E`?nv^n&*cF>Tnt+gjZL?LW(A8fWT4DT87q42 zckoq$?=zZ*z{selUl=GKFa2T4C?*RCy!yJZh zJ_2I&f{%Krm*L6u4uFs2Z*wG*Hx0r{z(jet6(^Nf2fpi!Fu-K;`Yd_uQr*m$dB}`(3FI)nXr@W!@jE=}r1xn{9-CP*`}i)CbnNq?jT`$+J3B@egRr1l+2Q{F3E&J! zBabkdyyw!CH)6@VCWX8rbUx|WcRTouee*1N&N=@*;JXcUbC~{*J_nk1hU=J3`3XmkEc#xUo9nu&t> zy!SJA{wK`&@0YfkzbrK$V^HNiMX+?{{C9)fl!=-1zri>iTHcKsH*@f-9rQI0`t1(- z`yKQS2Ys7^zTJWEa`5lA=&Y->pEh%jePtx|>b|$cffqUOXxbIOnnUmD>A*YB1KaQ& zs^FIH_TJr1_=Z$(utiU?gRDPSHC?U2o~8|3`L(F7 zPCmZavh5N~)eF4)dfg|FP4E{zwk%ZOpD;gn>$<@|FT4DtYyOLVd|}8tVSdK`j6?N9 zlV%hm?952sz>1+8x1SnvxwhAN&$(Ql{?D9ud9QrDYVZ?%kNSNxeRxVQ`@$?CXO4^Z z*6j+Yu%&V?d2ih}FZd?(4KBLpT?hZ+!UWg%zSMVBl@}AF`^4dblU2o{xcb~F*Jm!c zax)Ly1nJARXC8W=|2F?F9sAF-{ycNt;Do#>2gM=Zzz;4=$X|EvNBJ4&@EYI23HdYr zm_L+#!IPgql2>%4`{@g=yl>%s=LhP~{d`LQFGuoD5m**|t{*CQ_*uJ#;L)}?L zCQaEF>SQ|i)_r88?x?af`$D}Aqg+=Jc-(vIPTwhtC(O^^H-2CCzQU94`C0q&_U%3+ z7QFxTuJ)-%$_ssSZ+_V|WBmS8u$L*A?8l6H9VP5)-&^NFXl;$F*nK`Dch3|7{Y(vZ zZ}fW(x|xz=>{20gloxJtac=Nnxif`e2r%IbzzB^KI zGy|pm!x7I>@d)$6bI>=FWq#dslk($drXTbzc7=T9uFbxA*S=holTj>YWcIuFx%R6# zcz?!0#<|jUo6Ik)$24O#X41MrSMJ`r{+jolfi_p}*35(M^I}qN%k)Fz&WkIbJTD4z zLs{p=wB$yRe9H1=xLceFy&GC6*T1WRGq^gXrFR$ZylxIQ}}^E z?$#*>?tzi6(XRa97)sFaCqL_7dvcF8$48|fCxutx3Z9v7i{*0LMfdG1w)86@oCw=p0 zNbAeakUQguvibVy#^STcb;h5C_^SR~d1eCQdFN-Hx$cgu4lbKMS=zm~&NqL`nd|Sk z>dmdp7c<=tedB_dko#!C z$(#Jx7ISUEN!LEtL*pLJc;;q*&JoWudH#&Y{llNT8sAD7SlsSfkazMq_NaM(hggLt ze}ukv<(akk>HxxWk#EOn<39raa76U|a%5Vcz*o#R)%De7p%k0y1iozc%aMXU_qlQI z+YstGxU|asL{;6=D)Ge9sjerkt9zhuYE|C(n=>-r_+#y53qMnse=Z|qYF$Oud+Y9* znuES{{nS-g-ZcCJ->1*#y7^?Rug*w^%F+W^T?9o88eL*9kYvg+ToeehHW?{3dKtM51Ou)hDyd}q`5`J8u3pPJ+U z=QQ#Yjr$VRPo?kw@s6IpOR4W?X`~PR&LvCVne5TicWLygwT)k;kv{aFmmqyg-*3`L zUkZJG^lNGKpL~}+x=^oN{=Yj#7aHk9FR{*lNYRbHT{@ph(KOQ0Ifi?MZu==R*4&$L zue}6yN9nsSjlL~~zPEEtj`LZ3j`j`>pCW``@h3t!Gj81CbG<@T5rS_cA?UXeVr@%4 zFAMxT#KHd~Lh$psSi(a1Oyrl}2nF0o9L~~hgqXkPbFkcx&3C?$|7k+-4Qo7{q4510 z{(uniUnN95Hzwi8KaUXlZz6=9jf9ZjM+iHgB!v8L5Q6^)gz(RPN{BVX5FC=L5N{75 z=#jNRT(S;AU33i){WOB)!XEt?`e|@w)W&VXG>&`0BV}sdO2Cg>@sNG;NVK*W29a^$ zF3CAaRGqlBy-MWY!%~9!GxFMinrl+N2fjIqMgAL_b8U~`X5A|jtC)ex<5v8eI1Jc@ zyg`;m4s-2Ch|PBw_!dUEqO=->ffPB80qF-ueavIZLovp!!BnBFry<-NMwfGKkKYHS z4s#g3`3SJ}9t9uuP%p!i>3s@(D?m3#GI{oU=Q&nLCXer(Pe*`I`%by&!o2~ zg?)T}HXV7VEO|3h$m25=H-T=BWbL;Sjl$SB3(U##?{@H|Bkw6o9{b;9^7veAI`XFB z9%t+$OeU`meCg!hgOIoI}Pp|iLRbaR;U;4RtipZma92qODG z-iu9od2Qn0QXE7?FE8|AXoR-Bqu?t;808Tfd8Js)8_U|>;zi5Sex9eF9V5)=y`QDG zfR_I^f1YPR+G_r?#4pXIgwiXDgru{!_g!$CGBIm=+|Q#9b@4Neo3*{y9Q5Bf=)(^B z?;Uhc#E(&gOpR0iQ`#Qdz_q$h8B+jRT=!Wxs2#id#){KGmtxhwMd{4m}e`S7ul zCnoP(7!tE4lup@NH{_f9q91F7r5XD&4|opzm4DKKwllqf%MV@V&zswP+M6R>>jr(f znf((_b9O%S(aR409JBo8nBO~`chXa?{>vZDJXk(m?3+4uZlO=k z?n}<$*Sk62e9M_h2Yn^u-8b`jG1Pnc zLGo4Q9K%)BxG?|6m+^nXV9!l>ue!V6bwC`zocvK~V}p`7{mfMZzL|M5=K7Vq%HHw* z-ri?>UBwrAy_or?R;+vUQT8dBrZrQz;*fJb6RD~iy!CG1feED(4rD>{gZ)?qEZuP? z+&<&6d;H(O;LH7f{oa$`_m_OxRXkx|7FGa#GaLPL^%`IpYcmaX;efAX!WmalRdE*9 zsI;~!YC9@Z{KGTf87Vjx?%L@8{Q2A*@NZdnZi=tzoS5o6ZLQ0k+Tg!t3Ui$jzI+D! zl)dHa=W~UpKku{~Yq)c#s1$N0e|uLr;5k@bxP42w>zVewHCMvs7qQCc+sE1cMbmvV zMRAE)`#DOPEC=Rvv@G5)Et^m}>#-k>EXDdpCC;*AzZ}_f6f1zGRfCW8h1>5+*dOj z`BjM2$J>ubv$JV{x7v_51Wpb_VCvx43Ij73!`ZKc+h1+vOSpC~9W^@N8 zlw$p?6zgZD(;;{BH!~h{^{;zfY_FJpnOvn~d`#KTF!8Z!25xU@)|smxorAVC)vTJ8 zPG!iU3cYHku336&)ok2p?;8aT;zDr_R?o_?0_5eY&no}V2Qm+0e?X-u!Ma(|q?6+g z2&~dhI_$e9|70$%bN63wt2AD=EK#blWv5%AEpF%DO%-h*TZ>--OtSM zkAGBLi&C6C>7+P-0rMkQy7C_@I62cVW_}avYXv9ok?U%i&&>8uD81v%9RJn+Jq*c5 zx;A+)6npXQ@M9TA&W_|^jkpf$Z6$r<&gG1Aoy&1~&*gYusr%)~tYh9cu3G86(B&O> z&N~jPczxA{?sGYA(xx4Iu`cJ0vvrD6*VkA0xyq+dCw@6n*e4EWoXg4J-UzPO`Kk&F zDX|){e0>ddv#WUJ?JFrPtMZ=n$Z$_z_PLyF#`xlSm&-f#)Rjli=ZT}|^D|Zr|44AH zt}u43t{H1}ZmiXndQZ+#YjvfcIPEKSpB7g?=l|HRul7Id$6DQ0d%0FOiQhO!znwAp zF#7F`mq*0W#(J0RgRhWlcvYzVSSLrD6vr+*7>@MDdQDIDgs0fUhF4(a^Qh??)f0bM zjmz%Cf>)o*o$%ypU7t&?;Kc!XYsP(D`Wx{3F_e{aHn@~GYxYjk}mM+|ABYmpb1KBW&6_oL?LrPTN7G|KN%>ifw%tnZs? z)R#+{zGpJu+4B3tJFM@Gtamnj$FtvAeVSQ`B&?sLiV^DVAlam$Q+ri|ll`LbMc`=G|ZKnSMi2yuV^lg9bpk6aAWiwH4qyi?KSmtzJDUCqA^eU1mk|EPb0|}$ z^Lap~^GATWm>1M*RC3OWZvNSX2r#@~)MDpd4YHbSD zP0pdw%pROE@{k|Dk`mOPk=F*)T$6GIBF#}O^54*$Yg0FXZ<3zFAtS`g<5v8eI1Fe& zp2)nB)abR}!M727%QX*ykx_$dkRnGvkUn742e(klMm30Ao8ogs(-3YBBd;6*=9;v5 z;G+(67}|UU*m}d@qaNyIIMb9!?=JAI0L>i9d+!1tWp(C{pP5W%CLut$h?#J45^fQNT*1)VnuKHk*tNS@ZL3{fz`9+xKV3(r3O$#QKy<9^WH!BQF=3l=PuFrj%C+ zoEv%FhCFmTDdp{VDR01#hi)LHygc-|ZqnBXoaA@3y{R28QY`9otdOBJWBdj0Ouxse2+-v6^z^r8AV0JZ_qx?fVd`uI)rASX-@yme@&tdandp%G z$*@*p3?3bzVQ`<4Dn=QlU@aMPeXvF^;4*zc&{vO-T{(KT@ zQJ)TJo#UPa4f_f3gfI=R0X6O_A0uO>Jwpb#-j(s%~!X#FcF(?CRJTW{vxd zTRWmHiJz=Xy4_>F7^ZI+ZrBvPs$tZNZ{rf`wp`J=rNw%&47spV6ZfxfyP_R$wMDP4 zZP~i1v$dnE9cjTUX^5_&Wy_|t@XaloMtgTHtt)YPn=I~y!%6%%M%M0#c%pY4@XpEF z_38+|BQ=mW&U4ko)>lWa&E0XOzi0fFnfLE(Rdan0?6})gRNjY`^H0ea^b0N+!xb9RXY}P3 z5Mjw!Q8%^kqM;wpJrJ1n(^sAmx!DHZ7fa3fBfht%uJ;XoU9a1#IgD{`zX$8YMGGnlaG9u3MDR3hyN z)kEKD#<7hH&g^H{4Pv^d-Kkgc{SmzejX=6TfZPJQ0|ZeD%iu8Y<9i>-L=EH7-K&%a zsn}x{u1#3q*ZKT}si~HdIT*8CyeJgrpKHgQ%XyKn*`)AiKjP`Xe1DyoZ!}daxzUd_EaM>Zt95Q=fvFrTn)mC5!_NZ znDHJ0j`1*FRF{rizmCJsY@&*if zXm%;(<)KjAq^}V;$uH|ys`Tvu&Q19pG322eNGWdwI5+95!o!yIQFoB^oeevh4y&9t zQQ$TR11ishd*BK61xydzSYJ?OWAf0ICE)7O*YSA~hpLkj*J$AIXks|ZmNdYsxb{go zV#JTsOdr=i!*FA~<{D6OS^460&U2QPm6lofvF~S}VxI z+bkz{?YfVdj+rd=M=2!jmg(UA4nE-EgX(pJkBb<5?|GZym@o;w2KPy5EIy#ev^eiq zvQ}XEXX^bH9RNQZ$_9k7`9lt#^-K)$*9!y6w!6u}vriR6|0TkJl4t!FLq482%m0MA zE$9~bgp1WJXX}Ra_^s-eYpSU+4qm1;H71@@W4H28cIq9M z-@pu*6Z*PK8kR3x-B7niK7qppfK;g3y0K8pT*)GevQm5{r#Zd#0IMePy#$)SSYXkg z+m&n^J4Bd!I0(W#-Dy$&ewf2lpN|AKwKQ#PRh}|fmz6ClEm4`v+B>lVxo~xP`JyfD z4b59Slz&oSbymiB&m_-eU!EuAnUQg>hm+Qnw}7HgMpsj9K4~4?%u@5x1n3 z>3AJD{KbsexyNAQekUF_Qv6s|P!t^^fVd69fC`S()H7;P0F`iKIk7A#o^{)a<9B5Q zXX-&t9OoT^ljoaE-tPi>-P zES_ay$4oHcd$80hzn9=2P){cCe7bStX3yfw2p<<=?OE{sXUkafK4J5+C&BlkP5)0j z{P~`=>EB}bUu{Q*Zd31Bd@Ow`#PdQnoF@^HfrRJomKbiX} z6ZC#c^>7e7Do?b}jc^wwcx7hKj#gh!N%Y7_N%yNGxvC0N2Cu3b2xoC$rMPe9arLQb zU%{TrmDp3ciu)<}|1|eh&K#(mxavq?pwe^pKv)IOp4+!wzmdRQjh4I(b>(^|!xz~R zsW0$j2c%BF_puuLDC3W0zCHC5nS);s+>QN|S7Q4q%ZB%tKHtB-ZdzZs|M&jD9^XSN z4sMTB1{m6ly@nMBS03+f_3X0tB39_w7}I7Q6D2prY?t?4??24hc?t%J1a!_ z?Dz`;tNShA`nuY_sSlrd{LmK*j*Mjbe%jHRTa}}r zi*a_$HmmOkne%?ikQqJR`vzONKjPVSpp`o)@sQ(Uct7@t!a6rhT^3U3L+R`daGy!d zRSP=a?OE*x5qn-;J4uR3_)@S2UPka?JTaMkdxOVsRV zGgra(NUfT)ck#mftMk8|{~!6QhCW%fQ11*?#dd~@ojXHwml``mGop{$--xvKh4jwZ zLF<{K^bT4j#OD()p%t-j2(eo#y+Wz|AEhmB#7+7o?D+(&O(4f_;%1QMBn*`_ZAXWy zmj}?%Y5f6fx?0V|;*Op=U;&bSAQfS~+>29>u<4drRYcZ-YsjS}Anwb#cJ4w;M{)!a+_3O6#5Ggxz zbo30T_xRB1P9TqPg{1J;cP61TZ?@gH*zWg{qSNPhB8h*T6!ClndOG(At3bI&cp)hF z2rmVlh5o;hR1XShXHfb%2mG+_4IV9uYrqI0A6)B!=Zl z+lb#9@a9@WJ#ahV#`M#j@;LW*uIaoAoH@4=c~0DM;A#+FjNqJmgO!Mc@i1O4aixm4 z3ZUg83^bKI?tvA-pYqULQp!8vQXcofL>|||Ql&49LUWTo?tzIsG`E!Uc>dpwyjKl* ztT(CB#}`@L$XfxNq;IsnLGG2gk@vJAkGf*2^!2-xSA0|elN?tv1ZqnCl$YZ@u zCGQY$5%`NqRsVwMizR*L-k`I6lmO=@eb*ZD!iZebcQ)+k>tbt)dx6^^i364NIrmma zfI9?#whyini9Bv4pen@-?~-DDCysqxD%^_(E@0p&ThaildKEaz5hH%2X1x8th2h3{ z=iy)CEiNx9u~r@3tvyzjSJ?Qm_g0TvXJBG$kGKgw<=W$i<&5-Sqio{Ful_2|z~)>} zG)tKE293=yJOh0{czGsrSI!+Vj4dw)uz2UUsQK+@8d-1T`6J6%_|F;s*TaM7l1%@b z9sDf@o;d0(@romtpWsPtfM2{IVVVI0H{Xd`HhRmi)LL zVDW$Hz~AA(-|6sw(Bc1(;opLYm_0rduCJ~Jy%Yb}*nBal2Y}5s&%XA4@EdKOVP`^K zqs^bNF`Hr^I>qMkDQr($i+fF5wzPNYBjt1EbTzfMZE9+3OSNgrbwBuBa^2RhmaA8_ zZtQI8yiV1^0>|dI){Xp__*NcHU!qS=SKodhCz88o(w8ScGUY439H~DvyYbO0RN-%% zzS;D`NchmkD?GTzYVhy1%UclShI#$6T}U-CR~PQ<%g?VcOW)+lm4fQq6?^kmJ_fPn;n&*GOcYnqM-Uod6?!m-8o_p2q%w0sy#`n2< z*439G4MTG$(?z}|zGnE2suSbQIxz5@6>CfTS6e?5dd!Zkdidv_**Z4={kWCnetZM` zelOz6xYxT|;^Ei4XIyoQ{^E8lmZ74Kl*%(a|I?^w?7cQ3k%sW|Z)=!xlAKJ;|K?0%f`MmqdD9X_NZUh?~D@>udG ze8+vo@bVP0tu5_4@tixBe=W*#h?jyY4BVfw+q)ZIvDiIfk9Fe+dKw)0 zuF_YER2si0y4b$M4>l^)aE})itv}){AWlJexuEAB1QV5 zq{v(=Y1n=@2fS9)fM4J-9+Qt(=zfd7-^@erOOMfhiI{s*M+=kxMp zka-{94e(j-NV{3@J=3qOv+SRnkbATLmdsmyw`J^*k3pbbQs<1V6C&N5Z+pW!YkJ-H zBjDY{bB4szf^Rlw-r~D8<2H#!SN5dw;CZ45l^2a6?RY+sB%WZ3{Ggubc;KIQJZqE0 zgZh*-KY0E+9{8sbk9BX&vLx}KTy#8W&z!4!GwkPca^+^lvp7jSQf|(8PNm$EJs-&r zGIJX8W7X@rQS#%A=T!3Zu_W=JU)0aX84oIft_Sc>qaIl6-ZPWLBjtvE_cWB770($- z;*ombjOXOa&5CDYl6a)tobjAWxh0E7+Nm?1lWV6|e$E*sKNzsZo@x~x;`pRC)dYW z@m!Q79;w^TcuuZvTk$08v!!l3<2kvyV8xTHkCVFKjK`=8X*?fmY{*JdZjzsT$MZS4 z{G^UY^5cxh$j|xi>NYF3H8y-ENyV0W4V^BbzMWjXw&J-UNx4aWobed>N#prg@f0M9 zN1hLK(uDk+-1A8tkL1T0kCC5K+#|%UTI!R_weaLV-3HQ`N_CQETi>YXzTAuCF`4=W zDK@zJNui9tNeW!92NbvxQsAmcfs2p=$8){J^^zhbdOr~O1LQH;`T;365MClhxSxae2gMFZvsRsiF#g%XQtlM{lS{8wfhCJ4%RPui3Qr@{}Fp@qr-<0y!1Lr2c_Zjlg z{8P$%)}_364SCZ>kv9hq%T4;4fs_2AJ4%_pyIjh9$&iO`CZ)XNF6C9A!;xMuNgQu`Q2y8quf-__a)$#!Cy?O{v{WkfTV8$z^UX_0_P@u*BbK99Yx+=m-6}z zd5cDo$NRV3q;CaqlHZb1JDl8`;@10> zItlv6pKuP%*8F4M*o=yug|i$7-(y+w|0nq8p7#lR*48V`qr5GW&aSa9az^C#1AC)K z@y+u5h#EX=Lhx9(!dDf#b03=g$dBr#VlTPz&p55uKd> z=(uUogq>_JXzh%rew_i)aMefU+!EjPK_>){1QG-wl9B(uihV-AIdV zbXsAr$G=sbEstK1M*K6Zv`@Cf6}B6QHY4~gx9ub%@1usD?&rXRy}f z4h-v|7)jGyI7k@!@xErZaWP^?H;{lU0#46$ZJ@}&FqF`LlmN&4F+OwNMLf!YU5hqV z03_?*ip$e`XS1}V()GEiZYBzkLHe0-%;5?B4115!`WU&t;^cann{*Q7Cur@b3X2+| z_g7=Q-@ym;KCC<=)~L?`8|VEFKA@W5FVBkSq^fP%Q2()QoXIU*Z7ef0)Jt9hG&DhW4<`4SJ~j#iD$i>T>{gYvJnsWJgnx#WwFTxkV!MH8!|xK` zDh#N|TWZ+p{R?=^qs2CYD+Nz`EN)m>AH+y~bK-Jb;__193J`&$fpMkko7m@=IQC7Z z5kFFtRjkh;j{Ue8!C6&&nZDz5QG0QCEZwHOveLC~Q-XC5m{^|^X3A5%C;nkMs~MF7 z($ue75_pbcapUH@hHC+rvX--&>tZ4-c@I1I*B$&DHZNx(|I^|BUk?942meP0{ym33 z-%qiOl^(VslmCRxGk$g-WSIx*d7S57g8vI`o@3{i@xRLEiJgcawo^kdv?^Rf!ih!O z%|5PZcb>MRaaoS-a@zFCYrlKjf!s%?Mg#aBSmpy0zdYd)-~Hpiobf=;Bi{Sfy`BfA zM0n0n73^Q`dHcw^rs(7{@7qT@dEPCnZ_UtZ`)prc1mDKOeXxb$KmPjwB+iI>=Hj#< zB>EoUdBO3Ieq)Ra-4Z=IE{mBXP%r?g3t0M5PbD}ye(XdtkDY?cymubX4Ia>OU8v(yvA8C6oETT|K*w`<HnP`3n zDLe~EvDR5g3VHKwzK9g~g*MMM6ymk+3Va252<2GA4KU8Z8U6yBuOdbGI-6&kVEBt{ zo^6KVFDAv{ruzx-y5B~}|0%jd-d~V{Zy<#~$9In&RNvooUd)e+{rsb`^H=9h$T{Ks z6`q41a=a)n6jA&f5z1jUdH7eljAx4Mt(GDl-z^!p$|*0DUD7yERyq#&>$!#Q?$|@o zkcvHK;n@U4V{H|G)DaEqT+(>(jC4Hk{}`pZiwDJK#Z#W7*jTBP#)bN%#RIhDHRtOQcmoN*X+?fsm?FG2mv z#(qH+DLS}%(9M&T>Lw5OJ8bs{=?;DDpU6X@ebsi?x(D1pf~rsVT2jc-IsxRw_l9kq z7W%)C^>eg+VS2kUHvy#Mu)*wC?=}KTD^0e~+W}98MU~a*!{a$& zpSJ?K@Ks6VZHAl3ruSEXo0kOV+~@rfaD1m%3|MV0#joM4!YDAAKM)}HhyynV9?b;U zMr720=iEok4hn!L}dNPAleiGcbPDt@;ul#nDzN)FpY3yeMXgyrH^(A z1FQNCaOf&yM*K)kc>`do;6{0~@Gto-F0Wi-Y$LdsYgf3QYX_}_C7El>n%xI;=WG)T zEoLUEPbcu14&LwJ0}eju;IkZjwu2w%;By@Ocn3eh!B2GXxvCE7m**_=cV-V&74Dg8 zrky|XlQ6?L#)l1K@#ECD68Id|n!t}&6$$(Vm7Bols@Ls-(2|#>zL&uJ)wTpapehph zpn8v$FqWQd^^Z1BH%uYa?GB!IO^BiYv3TY+e!qi{zc*^ht8(}og{Q+mA;Li^f1`sx z%fTDsuzmnzE?Av#XIc{9q?hF4y4kvAH4SxJHZ{~YH8;0zxuX7}WtW`S5Wg_ZT4fmJ zp4}5gth{9H(({&{*HGH9x}_`H-duKi#g(3Lt1(doL5Gx{AAy6n|;!q#Q z#w1oB-4&!8DE&f{YGJodr+~2wO$4|vG`l8^vG3$|BVPB^-%l9djn4ZtS>Mn7D(^fi zk-XoT!>+f`!OwQ^a~ynugP-f*?MYWmJ{44$7*FNU9&#pZUzZ7_g>BQ@t@{MIu?vYxTdF<$ac z+y>xS&xylyKP8T5;RT23bV}T{29EKiig$;BgEb|t*T8YAmrCA#1BWH{l(?r2oVn)W zESDDz9G^j|cwaSe=9-IB-s=XA`!T8HjTktVx8RB^O4B-vw={O7X6&p_9__@;$(@w3?>^AU;g3IIUCCZ?jrsCC-Z|h{)|MH3k7Y)lb%pz`aX<1f z4GsDfNW;}FS8r)-BfYqfzU$ zp>eX^@#p)|G28NDCIe+T{ke^q%S|?e4{OU@vYRcLXH*U_WupaYSSjPHR!K_#Vu;iU(^E?m2{U_py zVLvn14oSj(hHI^2xZV?&ZTCagdJa09_Ri}XHnn$LhyF%)sAGRb*j%GAF3vv<9oE7( z2G;s`uekogZ)WuN1Gt;2`5qQ3aeGbWK~Ln@jb}VlH&jt_M!&aLUHOAQ3=FD2 zOxoM{jOrgBIj2#D-)xLF?r-$=9%_C1i79)w*ZA$*<_p7BL*Ku6$*(8xnet%n?99Qi z;&}_tAX0#kMbYZ0cNY#R6nYnB?)L3wdamqyc_eRdG`jamPeJCc_Gso{ZccUN9|m&+ zpR8-F-Er`fk=)rI(RXJ>qqo;q=0zKGi>CMeawK>tV~;27>ruO28&QWCOFwUj+KAI4 zg}2xC)NJWHv)2>NE%h{J?7`=|2JwpS?r7uFwck1x$j%;^82G_p?!;OD3{H7^w6tE& zLp2fALuqH@GL7H_wZ?A1{d@Snk zte&%& z))!^=PCYm`f~Hb5_29k;V#;B;oqO<6+Ot)$_bXEm?xcN!chR*`hTBUnsEPszIX{AD zUF3!BYjhpwTQma*HRsmop=f^9;;Pl5oHsKwv)}Y*f1>vG(6-vjs&Q|6JdYjodV_Ee z<~@2WGb>#6*fFK{zWx2C?E{yUK7o_z9_wWKMx0{u@@eO?_Gbk3_m<StMBTV`2! z`8;FedB%ziwZh9k4(==LR*vpM+t9J=z8wP-bxrIWtp12**qy8p)JdES-0 z56@PI2W5D^YaM&{95OI;SbCN<2GeCsa}y8{6EoD!?v8Qsr<&}Xz!BgWmi3al4|TJx z_&4S84$BU>i2uH{G8_m767-vhybiM&T|6mQ5K?)5g_&m>>``) z8-O#%SMjTXpKfmi!L$Ka0?PPUyp%`Xsucec23GYjaQ2cF*_fXb_cU;fLyX8+2nRFX zcYzZfPRco1ygq+&9oQ*v6>vp}gZV&}N|}!?m-4v(FY?Set8*XuH^A{3iIMy|_mR&> z;c`ua=|k3I>7!l3z^d*8PM#@w@gp_MuNOGhOUk1zCC{z6;=Hu(*M-XL`rD;bS+Ir< zT)@;Ne7p2dGavq#Szy>XJTHOwJNSTu4?6fP2cPZW$2s^M2S47yPjK)P9ei$VpI4Wz zt{s+*zns6%LVlzkaGzQBedoZR`^x+6e#7F&sZS;FIVwAWAFuv_l?KMbPrxOjCZDSs z68LO&Rs!!=N9@E{;R9-W0v}W#PvEokw+-lYEq*u;m}L7iR@UA3Xt51Pm)C^>rT<|E z{|yI!pM!68@a8!b$_qREjpXR~>;(_m8pS5CSk3JpaWlNvv~Oui9oV^xBkuqu5#)r* zhL1TFvL;8T=fh|Axq0h@W+yers@rl!>z0;N+9TJ6o8|_wV^7mrZvX!_dz(2CPIcZv zb_?yAcrp*dA>vdY#2DiKl-um1yr!JiM}cJpVc{DiYjf~TyPa4^Xxuw~S2%iaq&HF> ztsbtK|FKBsu3uxtKxN%=WpMYnD+BlLXwBT?@5$_4+3Iawqx=J2|8C_S$nj2F_M^A9 zs{>C&26FwLqRD-pvvc~!9Sf?xn3?9z&MnN^&-v+J=8YemgO!17%O|TpS~KK3vm0N? z3m%LdSC?iS@fMZz&4bN17*@UqygmMh0uKiF_os7#&_fkAvG5>>9YC# zzTQJfx2Gu3$5gJ25NY8ud%3z$-Re2pwjd%W$kK+EUb#b2h6pc{YiTTHJ z+AJe}=9odu4{&Z=Oe##5e)(f`Ig%dA7db*1QqnB((@*~CPa|n|VuTkA(=2WxLwLb3 z&El2{!!#4af5DK7VR~q6H6n%)xmXs+Z1nO|MX^6C02FVHnQpKDV*;XeVC;=+RTK-- z+$U0DOHbg-Ij6WkFv=_!b5tn*K15dn+5wu4_>M?1_{Y`Jy~86)95T3myDy2S3-rJHtEqQ;=uHH1=;45L?aEV9vKYjbO;WHjVg| zdO(N$_{US%VOeKb9;BQrneuq1po*Th5qTGZ7dyRHU|uxO#*l~~^-9_?UDIX@aMVY| zNSb6mCj9F`OHUS@B*BTxLB+I-T|-mhN?hXByTo1V68Er6+##1Zo_BVWU!Fa7gFDwH zu092hU5xQKRTpsb4ER9AevSioEpW-!N#+BGEXK@Tz*T}{y_k%D%0t!Acb%YWvOCa* z_r9_2ijg#NP1BS&1M6J%aHBldC6PzGiE9In?SVMf-Bh?63>>O2$A@P>M)+kY%-;E0!L|5ckBmNm6)TGqa0 zYnQ{#W>+_LMH^P(tKK+SepyRr`&Qe%ZqufQq1 z*1Cmg_q(5zr9-teU$UvGt*Mg&Ps`rt$Xd)>#zC_l_b($VJRx%Pfy_wtu$q*y`|xmR z(#ONp-6z5&R1LoRBF(=Nx@buG0>c~T|NW5H7mgkdynFP}TivSUi3^7gRx!ki;fl$h z?)Th3qo7FdJVNtteFd|N+Lbj!+k-3WD*ArY>V3=;-uE4%y$`9d>iOZZ7c!1t>FIqX zG&h=GSQ^>C9Q&sq(V;G^ubX}ZyH!5U2Wo3q)MXwC9t&it`O9$+(}MoB$2;m(&(B6m z`aQkj*}ua6V;;iyFMkDJtsYAGl{exGQU9}>5F~0}1@q+y2 zLl1?&n9uYej+)%a%1Fk;ER*}}*+!H3DwOxH;`@;xjr-g8fZf$~5;i2bq}#-p2_v<6bK$1F$jEm>>7 z>{GZGI_s9;t%2M8J2G$g-H~ypyp^rH1a@<$b-(OO-qaBy-DAb~e$6E~W^liY;|TY= z3PJf^Z5b(^E6-VQzpR-Q&;3SHK6ex?-HS*$*z#^>5GoK_SLVR)(%b}`4rAlf*&pMR zWmwiv=7rGjHTfDd;Ej_KYyt2a5 z>&8AKdcbM`F+J^1c}BE{g%vaYguU+*^)E|5lCq?JwFY6y|118fKRNXy)>knsUoM=8 zAs?5OpdYPk+S1&9b;FiTqUktvq_OlS96w#T<(hOfCY)Jl*s8xcxOL8)tJ|BmwY8`@ z>6}j;`EE|cPaVf|csS2vX*kel6m%H{O{Xm|ls|v`&boo_y1L`#b3M@?L%Z=6o*gL> zO=c5xlHtEC@2$x?vT}G*88m`Up7iRYep7Y)xdmA1rR@BIngLZ)GvM(qXq=_>rmCUo zxvzxaW8MCPGW8)l&NyAE_Sld={ulbfe3EgUcjL)2f?d}=Mr-}I{ET2+Sz;=_52*q?rusL%R2q7kAw=^x$3&=G2# z1RavrN#J;jV`Wli4i-NClhe50mpQU5gB|aW}o^y;7Z`e_{^~oDojG3KLZ8g z<{a;}z{#45lph|mDqg(Qez)D~dB?hUuC#1PnH6B{KKdv#kH^Jl%n`AJC6RE3;e&Y> zK2tXwoe2CaRqt^SjhRdb?|1M42ak8T6T)XX_-qG1&cWw6`0);Yf`gyv;Bgu=A^u4Y zezJp~;^3z`_%j^*GzWjCgU@sDAqSuD;HNwI84iA?gP-N#&vNkCvr5Q+frBq}@UtEK z90xzw!OwH>^BsJVgFoBBV+=@0-#HHcTnE3R+j}#N^FT+{cLX)77>Feu26mfj?UX z6Zl!`CtQz#VKkG}O!ZI#f39jt;LlNu68Ny6}__NgE1b&gaGl5^IxIY-j7phqa ze1ZCRDpD|(yb|?90$;4IPvGaM+5~>K8lS+Ish?Bfi^(fh-$>y7>Y4;TQ`IH#L3Ks~ zA5c6u8<#ghJ(a+ZS2rc_+3J!69%l*@_*^wa1ro-}??iPtfzMI968LedF@c|~N)mYJ zFZN(!$(yQPN#LibM-upHYD)rthFWR!Ow%O%&vWqqV@x>c|1$^wn1jE;!LN1jg%190 zD(SYN{1+YkLk@n6gRge*Qyu)j$2$w1zaKdGyB&O^gJ0_4xwa{W={+V4DESv0{Ffa( z=Y(R2Un>kK`635zM5q0YC52D6w6=6M)V5#U)Vig63rlq2y(rEiBVP%UKmo7DcbbGsQ<8_JeY?TGlu>$C7o<;;V-hBkRPNorojZZ6rt4h<0fcP{b zVBJqA0t=s31nK2~eRw)K&}}S@9N2jGIY5B4a$w`rh=3zVIytcL?jnfyFM8~88O;fy zP9ieb^(rAUhDtXwJ@%!YGdt8tM0OH6ORH;%7f3nB-t=>3g-SbT9J@~@vXgmcdhAa- zGCNedIZLOXju(Dfy|odHx<~psvqGhvvo!kege0EKGeggI5;?O&rJFMZJBiw8he|s# z>RxF-GbmvUbrO-COwOqBjS-opl4(V4^vomxM@_#VwPNQ^s0|%mEM}OtGAe3n1Jt?t zrdGL+DT#8&X{i~=ib#T`cyZ}uz9@$MzPsad>WtO)Sv1VC>CQbu8oKi=8V%jK*GEHl zo)e*=dzH3X?qRXR-Hn_X2EIz{kRKL1hhc}iybeWov1k4tJA)vm zovx>Ff5o|;QBD{HA=~?eecnpwcWhqhQ#LR3dp0lhNt+k?U7HvBeVZ5hw9N~B#^!~7 z&E|!E-R6aU)8>UfX7fV-%I1ZB+vbJ-jm-<)XY)e8Ve>-w+q}?k*}TxlZC>bK+q}>N zHZSxmHZOFq%?tgi%|D8VGT+eXr@>aaP!?;OE1CF8)zP z6XaE5F*s=K+l#!90Vj4?RTb*mJX&lceq3UvUE+=c$Mt0~jF-lV>vD*n={w&gZiP$SdY8CHm$){UxNBYFZgz?5afy4_C2qe<+*2-bhg{-bN`YI5 zv0ror>H)6;CprOnvBNn5_Zl4xBQnOr4f;@rcoDZj7*N5H+Q$d9Zw20G*E%sc>LQGn zyc2i6f#Y_3DqO9B<1v6#xK##@@ukA8H*idMD%|A;E_)PQvw?#em{MMwfnz&P6>pb; z<1b;6kI|UNdm{qu_pH;Gi<5jQ4j2 z4ntx}+;IcPt|3)E-ZgNrro{PhW?K3K9-mGnFUP=zN5M@sa0R2_W*E4_QE+n%-0V?s z=Nh;&Av_S~|D3wr|n5pTB== zmhp6tZd(Iy=bBhD9WVl%tV>biUHE4kVp#sOu2QG?xXpuT^DKTjwuzDQW4jVN{eFi3 zWNTst4&1xo8J8HbQ%^DFB{Fe8Vvybr2~S+I{1z`+T%Oi_9cAVA_c_OY$7mImW~k0= z<6Nbm#zcI`zZKA|(<(oH)g)F;tqh5ioBKL00+`RjGS;^O9u-#4DwO(~&GWtvjwi$u z!}m?8M~ZPid+MV0k*Iq6zKzJX4&!iEa%rK(}ga#LXJPUpL`yjo`m-3=~x9_ebxDWDj4K%@FT>XUWK! zDo{|e-S*LMe>UpdDAeq*mauC0(Om1siEIzw@BFu>Wq8B$xz~^15{@2v>kumAJAJWx zC_G{7M)q**IpHyDJ0?|}&&9sijY%8zKTZ;<7k?0UOR%4DbGJlD?v^N@5WG2Xi~rWl z+k87R?nvuiiL~Qt`2gek{K?04itprdYLoQFcj{_MzQKqq4` z{cBJ$GPbgeL^k~n!9&J4@?vM%nz$E$<643k@vDIY^CjjeaGX1UB)p^R9FN}xfOAMO zBF~A-L%}f)F@mFBZ^nB$aO@)(uaq-+r@UsD@_47UJp?Kb4GK1upG-$s&R`p15FB-1}QzM196A+Zu}EI*F6B9C?{b68a+9Ox%T{76lC z=L5%dQQlPii@f3`OVj$!cv(rQYrW@?m9UuJ^XKr5q(+oY-1yaJ;tXso{kUU6+SUe5C*z^4ijmxo z#-0D7s)xNrd3k|jYL%t&ynt`){Cayd`YE;S&5UK#d7_PHM&4+G-jj7~4t$l%*gHAS_aL!E}2PPDOR__HPI4`-hFpG`~g%^Tih0WIgIB8QfP zCy1N1!v9~=b4pEp;P&@d&$;U4<9fez56%;)TU-cA-GgU2sC!&acjy`%uj&6`*EKdF ziDIO`VA{n_KfYr(Pe6vBQ`eY)PJXX}W1mms)HM#k!yG%r?$kA&0?v)DL7ha#R7??K zV~lgm=e;3rbPe9|TccBM{YY6jb&XZP@exDpsJg~_m-2dnlYES(YaDVZ&xe8)d8V%6 z)D6xB&W&zxvmuWo2%j7CPrH;6tm<)i&`*r`k(#;z?-mo?z}(jTK=kYL_FtT#~Smb+HUpVz4Kl574d6Z=7(4k%N%i?~)?a;990b65?i$8}oaI>nC<#`_n zm2HNVw!ym1KFyTp!^7%=n;3a^OW`1P`dteqS)VI?n#8>qI6ikV((ar%e$$loMU3DI z-~g|fc@~WL(NXM^U^j7xOvdn|GxE!#(1y5VeM|9qOVV2RtgNuFzjM*X`CT`dSR2n` z%F}M+Y(x$18#iy;ira5nnj1E6>%iNPS6tn)rR!uHJ`%-!l(_N7&VgHQnR*S|Nh{XM(`;XCuiNl1M#^s!9HhAL1*M6)((kF+72sA(%Mt2 zTx@@)%|$!>ot3r^Wjp*B3pHl^3D1~4cp?1aMLT9Y#C?(2Z|hpoe)anH>dl++393|6 z+vY`Sw#PL;e|=TA3QbefyBDA}PVZLJ!zu)ONQGf9u8L)%X9K_39m6r*w)n|fH4QkCD$F2Jgk zzCqRVc6Tk;x`Gv4?JA1hVqf{pzM+@buNgiQH^P3az93TZoOSo=^wR127T27RV5?N) z6Dx=ImT-s8W8K0!hbvmOSiP!v&iD4z^|-TM`3CoK@2;xiITjbzue`Zlg+JS%GV3zM zqw>=U6K_4YgEIPlt+_CoVnjxLw*)i?lxr-tq@4J>G+d)G$9U=tn~ktiSJuNVmS5N( z#(xj~8P?SCSJ`eL+MEjkHwyzQ@-8s!^gaNOd9>I@aFk6uvZ&3^z_6Z+ku>oPl7yk( z26#xnL|*JTPLqJU95^gh#f-?{nLl%W9tAE8H^yhKtBeD0_GLQ&NYZ=GHLwekd4xx7rG?cy18pL zFT39+pBK{Z7hm$(ZB3mm%_eqDZPV7M?LdXg>dr1{>Dty&x8<7F&h{;O=_N&fmWD#5 z7QQjG_T~fr$colokwb3<&QSyJc_v00>O8wDqLl|5BJa(7FSz#2mFhdu_f&C-@7RsL zz+f=DJ9tyxP&Dfg*@I6u-dj_7a7yGmt#36hZoNHtXI|#98-qiwPc~WZ>fE=Q@(w;d zs3!XRs7X!e9Lzt^#Pl#N zo@2qxaP*02-OxxGHNqI8v3BTb=!<{ssOA?_p(jTALplzIQ1@32h4i-pUVg*tS$n*@ zp0aZIJpk<*3Qvq29?ET`tFL!_#PgshYK5KvjA}YO6e^H!2B_X&zTutic`&1PcI_YX z&Z+hFme;S)wT^`! zt*1cAp-xE!Q@>sfN47C4OJ|Tm@yR0vh`JItr%qAVr5Js-iSre&*XId(v%NW<37)A) z;2m(|_jbNPin#xY6mkE?rqh7o_jgv1A`h3^l;8NIUfgC=t|e1HzLgZ=dr6VE@7X-W zxiXgng`$g@boAzagko6spd6!e@xKcHro0=Fp8tTG7_izn_2yRSk@ExuDmcof9Yvu{ z4{+><#emhusWNFTi!-pXMB;{H z@@K(HS#nHXZSx(V9Fxo9aNWLVJNS6m6UR_JT&`;E>S}9AK4Ka}AV;wi#;^F^T3DALj;7X7c!5Um3_1Jb zouRL`E{IsYZ)EsyN_L|6eXnD?wQ4YrV?+d_L5HjnWLRqi@nr%wa9y5wOuAj-N7rqm zuYEuJP_||EjeO?jS^?W9dAH_N`o11S!saAxHy3ti-^VqByN$$19d!16&%k3|5*%eS zj4or)elV=>Vp8>e_3&UBi4nWA?^_QXhN75}^f~*!X5fl|Vtk|ZeRl!irtfp4o+bTxF_!~e1@>U};Mq6h!nR=S#9>c#*X`}IdYX3K zG_HS2fqxL+jDg<0dg$M(*mGCs<%GUC%Tqk~YHrLgC**tExBljeZ_m0ktp0FD-G#%m zCIS1|mDpiA{@lVh2G$@ZKVtHKuB{{%&$aiwa}Uy*`SguQZRR^SX4>CO&57V!Us+W{ z+4%BmZmD&K5?>a}&k3yzzgmXzsu?3o z?cuk&J=ZI6$C=EQ^bpPrLR z;jiBhgg@sVAH+K^Rg6bBX`OO%_CJW79nhoG{VLm=;qfS*&kWuYxYd7K;@4D>N9Ng! zyde3?i$Rci@gh&NN#S1&>L#uk64wtsDI$X)H}UZ$8~c0_b=x$~7tQjW>q+@83dhZ2 zJV-v%640rj{FW-mYEqsnBJH&40nlR1#l8nx0(!`HKT3+idef%wkV0Xafk(jbHKg!g zWz%(}@V^<9@$Ud-{CCkE_{TwKvGDD0wCY-kXG?vA<)z1aT@mRpwz&xq9oB}j4DU9A zAv$e7k6*h5X#NHM!joaq6m-1QgSh@>%6kDAmW>#Zw;2v%r(YL@vuwqPpYu%WgTQg0 zMU140&%x+!+)>~dhZvEu5DsR%d3d&rhw;)K!8Grb7Y42teqvI|YX+_eAj(5EO)2j#;Oaye zXexO}4SB4VlD?U+qaJjKhMgt5F{p#b_oNkIu0D&#E2iM zDeqn2_{Bm z>EQjU3Z7E7)Ef(J@U@`avl71^&7-iBX<=!oX(@EBw6?c$)v@BC?r!Dx>%A>M&)5V* zD!W@{O;_V`)#so5w;y&d$juyw6F9lP>~TPj!|9t@DwN^xR^wprRz8gnjZ?mEmFZK! zOrNeo+llvKr_2}fA#AoU6TWbVJv1&eSKa?r|8Kh0gn*7Wq$YN&i4$p`412DcG5+^G z-6|(X@3l>w9@<`z8=4-1wDIGS!s!##Or&8Z(=dHJ_TUO~XJX$?#dz{d$T7jO`?KR#Vq*Q-hiT8fR+pCi z_|*ks)ihI`4Ju{H{!8rV!ad2J`zJc^B0$T9O`F;`V)txWdwXYd>lV1Ae49V5jtOz* zs&BsXgs)o_7IK$;W+B@)?)jV7t>&JELr=5R>1{|NQ7-??>a1hz_M0+*VN?5bEXkD z+#BFrMV^VQYjMtG8B5;nHqUh|n%xfndkue{H783MT-W*}1K5UjV~H@JV|W(&l|~A zwGq6DTUB+u{Oo~!}vpm^@YqDRg${om1ZygB?uJBwu60WZqQUxDxdw!^} zAWQEGKi70et(v?3Z>xq?_47kvkM-61oCx@fpC2liWbw;}s>}3hQ|IK6XRh}c>c-nY z=~(;bhTxh4&mZ!FSA^FL_Z4FOYX?@OIv^>bqxO&DVBL%u_K7ttP?Y*6e1=;pG+R=YML(Y>P{Ff1xd-$zG9(DHb z<9D)T6nT~P$F(fjG?8|IW}&TE$AJc~7k6~ag9gbtA~$!j1feIsoa1o~OV@L_PbCkq zxu5<)tZ6Mnv~Jd!X308JpJzh$%~`huZw=h$-;ubi#cqN5=K2-$cfz_B{L_x_G4BTz z-vqs8_unq^hv#$}@@K_2=puik#CM8&gdsepq<6^F!-MN-n@LfBud(TmK)Igw5_v4B zpjqm(7Q=K$C4U!`>vogT5VBFP!=S{^ArCzD3ZBil#`eF_rgwmHeQqb{EQA|%T~0SD zU|g7+fPsDyGwH0$8#7Sk(X*+&RH&8mvbYp z)*oLtWPM7N-!|af$m4gJiy(*PN4-hpIoAze11_0f?OZpk2q@KU%R`o8@@SVbhgCfV z9Nol-AF26#p9L-tZcN`a{7d>U&pt2dJUfLxUtU`2`h6bz+uJdH{?B2bx>*VkWyDdm zDSHlJ`ZMr#@e5XbpjygTKq-E2#&KA9$O_wtzAup6y{h2~oFL|V&2g8_ zO|5N45*-OU9kUmO`OCoC9%|`cX!G7F(c2DSHskf*i}{TA6K#t}CUtxlGlZYCE+6P# zUOmuVz56?!-9#)uUOvD2czFSFQ=+d0-aYDhQ1wvvUpsuoI-IQSyflyJv-+W(dV-t_OcXu+JcKRFVvVi+Jd?hFB2)>G5m7mj51?;i}~%(6zHqx|n9D=;@W z@J{#O`h4FW#Gj3Lv$wygf}A_WXHGn?n>kpka2ZnDV~wzRUT<6xWe)Z?y?)PQH=R-N z`b|s)@~USgck1~`FqS5s)vX%JgMXfSDD>&tf65!D=QFp5zEkM^!_-Nevz`nityif( zOq+((e)RHw##X)KjqRQt$bTP=5q_w-;d<>Oh(KLbWV4Mn35T>l*8k==s!tw>sqckgzL&6C>8ma1cBFu7aR>0y6xZ^QrrQyF+Kz0#pB_xfK7V zyf7+>_|aeN5eIG#aBk*PRlwCFETd-eir!o5kkAMc9m#Z1_802(5k(5cyOf}z#1?zd)9pq`y%IAjq}l?4f6Pie7R*S90kXt5h$ zq(P3cq*^ISzt8{lV;8G#6`rQ%;FaZRYOYp6X6s+{V7V&yuDP4h+fCz5R`aLfFcejk z!fsWhL!2EC0qi+P*S6uL3-7^F)8)1a^s_TVJQEY<_)#9h1`PVjIXb?xY!~#r-+6J{ zovFj(JPrC>oTtI96_60tcUKfZP8jwDNL2w+1@q^8w&noR&n65_BV~Vkxkss2;4cQO zHqQR`9Q2QF`dhv;7Pe)ONWbUoZ#i#cTN0BBw--3JF)^uduK`ypAW*^aF-o539Y%qO zA9=Am`{g-S-$#fxB7+oOv3{AjqdZ}6OZJ?`N5IQZKfys4Woe6zz}#wR+{zu4iA zJ}zeHZzSK%o`by?aYf6PmQEaXw8t0QbrbJJ)AN?ruIn!8>TKC^MVH*_A^Q&}?nsPs zh-r1p)$N_vHEe3{xXzAAT<}pPxxiRoDq`(eV4tGynwBksZR(10>tf}WYf_AZoh`T# z8M`VCmvpssY+by>6|B6%4eUGv#Di40#Mq83)d-v3EhhRTRba;ftnCMGjQnNWNb7{i z@fq8{6X@~oitgAKw9iw8)v=p#ZpxQ~x9~iNhx0tx7Z}(c`Nw0mA%9QSV7KbdTKndq ztdHySLOUWrHT}cLxjl!6XEoIheO#}GuNZzUyrcH)om}Vc*57-2c|`3E7Fs8Za0iH& zdly*GuH^m&R<2ji$9$fef$o}`0E-I@1!?(_9#N0fe>&vR^?&-0*fkLu;RIRCvz zYKM+Yp3pz6J{x@E?d~tC-lBuJh2*p1?>ka8^xQ_Ir1PSF)vF%#JhDAHB|1FAbL;`7 z9?Uql-IKAar%~{zdtf4NSedu?*aLpmdu!uk_b^l@q)2F%(XaIG z&!mu=Q;RaXwBO(BckH@U4dv&0j`@OzhYR(6DhypSR5HG{ z))TCyA6*U&&A{`XRYm-c+RE6Qn}ObuChs2ZZ(yfEtyI6?7}Ps3#8tgnRV_Zh-a{nt?AJFUfk8Gj6RQju8!qq z+}_^UcfYb%c-1I>+{RepF@JTZh3;JUS6H9s+>sruUe`iLriVhT`%a`gHZRz>@t_(0 z^rn0sDHcwrlY*H=iq5cr6pNjOq)?D%lR|zGDTJSG^NUEa&aC@W_*0%o>jqxm1dlgo zJOT$i0dF89kn?f+dBPqw-aGNVKPvCK67RZF@47PYx^nNj3h%nb-gQg7>(2A8tMsm0 znz6351plS@FT;O1{<+@F{CT02ETb$vj7d*TD)yL#`xDk#t2@0DCa1d}g8VSwY3_$u z@%`1Q#aH7pe>45Kf0FN;eld0SxHziI4bP41u3kJJu9bUFE`L^h&t#;I@coGIJs0tz z9-g-R{oFTp{zi$fnw9;1c&Bz9#AahbENav1Nx8p6iuQVx6pi~hDcZdkO@i*+r{eyS z-j6~fooDl3AVquE_aC8uc#1saJxhvkzXIhx*S~^tpX;}DN97qNML+WnDLR>{(EGUm zw7{lSpvAeEbAXnBuAw`^ts@2gGWz3TaleZDWSeb&#dmUH$6vx8m7a&7{^}-=a(8QP z0ua?bX4r?^9pmCX#^>Rt9K=q)w;*Vq zfDAvjL*m#zY4VZL9~cP{>!t8BD_`b|YPtW_(8w8O`KJgt!B)c0fjp+qY&!1$2&V$ z&Fu8%c25bx6~Fmv27YI&{6h=!fvkc?k&&Y~UC#jT1+GhILd-DqJOSB?1B!TmkHe zDrTa?_R`^aTl>*Pt@ zwF#F)M>^ZDhNr!%Nm$B*=VM$eJ*MDM?w3w)^_c6w$!?oIVNE#2b<^<;S;t`?u_f(vtT5jgy@NMI z7hIgby|H8Yjjb`Rsbl%VH{Mx&#{pktZ?qtaRnj1Cj9%!_3`Y7J_qG^*sfVZC1JdHd!FSCGFq10nP+rTc5D20YtW z4}DgjxW2j{XV~#w6R)aj%jgLfDx9pgLUKitC*gUvx@zDD-MoqV@X(|Vu4PJ?L#;bQ z-QNk8WcFnDR<-iBZ`}GF_JQ;6@;-PtI!~{gX5(x%x%uHqdWAa!{Nc9kjg*A1s(5#X z@LiR4JvG_-TflVH>!m|$!@L)JMn6(=B~pK3eO+yzZ%;Ua)$qkcAay8(`nm~6_Sc-3 z5O(?SClU64aGPpTr0~~VbqyHj&3O~+^F#Bh+i{L+OwhfGaSugM;It9#tv;(qcxoVU-Pba*(wV4Oy% z2Y4g*T+j1ExfkOWKgAHMhu7rZ9#W5R?Y}w?=g%L^M;t%VevBp9_e=&L}%YNg6Li~mkvMz6;%^PQpkI^U6JLcHfM zsCM_`Y2m(e>)!C}Ue7Uqw(mhttMzT0J8F3+-$gnPeCl`9vaV!C-@y7azJgPF82>R} z|F?tM-*4Rt_-3Htr&WQ^{4~4Q_fYk4sAhX>yk@ap;l1w6o*Lf~6}~Q1g_Nw;DG3)G zYGum355D|H(39O;Q1HXn-aNY88Ohv}7p`75*yP`n(R=u3KH|Tvq<% z;Q!0sdw@l;G;N@>WDyk;8C-&Zi6kl*7g!cVQA~)60uls7LBx0v!H5YlV?3C%f?`Gy zb5_h*%vli?F>6&d3pf_{yq{&Nin9{h%=`tvz%9aCwKzYfLyXTzghd{g`iRV2!21 z{t4G#CA23~-g%WjRUYFbb&7!V2ltaos2@|_(cdf&W?=q{HJvc*K5!pTM+!HWY@~1> ze}NS4(_dIhui?PWR8Iuy@USpK3NM#pq%cwHiWF{A-PwFUHs7Dk$8U^mVG=eDs2$Le zm=4c{sYu~@v4o}Q9~JR#r0|?M!{Q4_;ic~liOAV?I(d*vo^Z+mJ%J7g+iQDLj|NaPQSL1%LG{?SvGbYraTfai%v? zXoqm5@Vq$)Gz^|w$AFrMVGRp0q%&(v^zsrt-wUs|^!yVpIH*82Uc-kh?l4IiKk?T$tQ1N`8!kkXzx|0gDE8SMCOfD|t$;K=V;OoKiAmMa! zg*ar%Lm+@+Kv*8OHOj-bwuc{g3`8kEI5(y9CZ%~KUmWmZ8C>9G;24Ns?rz}2aJ6TqsYT28{bmM1S!pu7`2d0fB8^FyBB0)g_J;J(1=$6t3M!dvWG6c#i=E=kN3{D>0p7Guk1B4D@xbOOL z04Uf0$aTAscz=dWygpRn$H~JucML?SeCV9~>y*nw%1?gs^*t@%!QAWOQ_rK)B(+k?5G^my7GuYy`kjb?ruFG-p#*qFKAD+z2U-^@8m9b<7 zkJa-t#%)Y&YC?&O5-B4+kx8PdNZ&{wzDm%8l!hWB=0B{G(c%B{T9*&h03WZ|Pw@xc z_aAFr-yqE!eq7+rQ71^?;+WSSz|WrP+`SF22@Em7hv%0ISS|)r`0?f8xR1-jd@f#- z;7jKp#LL5E{yhQtes)iQYZKjb%0opq|4xq0SoVr-{yp_T3FzoJ&cZvZ6V~v5d~K?r zOna(PughS(GnNJ+Yg5<}b(RZQKD@%o17e=K%v>b1P{V%J z@Ke7_%z{t_D_#Hp3YmNhrQcW~>lQI!Z~!{98Wsg#oOJtF>tZP5zh4zA>^wa~UA8;i zIh>(9gS21;%!yqA%aGy<*eZ4fOzQ%-2Wu*t8Cf zU+yCHYI_s!LY97mgX9nM=fN^hqV6i z6##r0uu_IvZ%X3Uuu!w9^j@#He#NYQXo$+LUM0(L^@@>%t0AzaqLNTfogDaP1@^NNwJ%-8TJ^GuiWco5s&pMo3wD{}R7x?iF%DnrBxF@MJ@ZFE(B|b|1cp0W7<4GIrdK&t z^sz6Qg=$&kkED28j7)#NLBlEQl0&~u86=@maMeO!S%RH$DQwbs&ycBl#MP_wih zlow%3jMGz|jV*|6G4{juE!Z=;^*-#G@ZAo(+NY&oy4r^_JHJTPD7(s6MPFqWv$_}X z;zTS3>wA)S3$b+RMo8(?}%yi>a}N~JDi>GG1SYdB96Ome$~R|hP`CE`6`9W>)^Ld%5)6!;aef8 z#8jr8Pl?r@qGXXwTUI4sC50)wcV=GU;K!|o#^#N7nU;XjO@yEPMK9@ zx_0<=5U$b3c;I!COMe%H4`BJqBeM!w9p+O7{^60pS|OnqC2@L~2`~nt<1hiIhAA-d zLeG1`3pY%+(DR}&twFCf)U1c1;pq%q=k8oL!Ry z&=7Hbc1_ZXU6X`~5PD6r0lOv%O!S&$BVtVwCQ2lDJSgXa6qIsB3h5q5L0?a#@N(52 zDWv1O6TU2UMheQ~dl;tEbCaMK&TryGYfm=aA1S2wMG6x~{g48GFjA;&2#c}aB4q^s zGv7He3x03atLv2aofFJu;`#l@nkLi_s!XqGx&alkh6>+RG3DLR__O6rtMaGHW7dez z3aB6SLzpfr{jTcYwI@?v$?ugX6L$V^jaYsPA1dfF@^#J1tm9J!1#*29uHi~+(>wuf zTAAgI7tlv5v%IBB6<-r@@2j--gl`)wyvI~#c`McaRC&y|n{$*aE)Sj=mC&9{d9PLf zYQn*zyTW3z5Q@RR;#UXlLMvl(U-vO507qKqwH? zVN9Eb6fkWU0h41J5W~Rt0Goc3<-5Q>2G3TtV@3r3+1{ZAIOs- z1$p>Qh$f76@mmhmdje7z^KLH#ZEv$tY0JQ^Zg6SZ?F;XbMB~qw| z7gBQ=`yz#M&^H>&OJM0#q~@^S22#jRXEAO zF~EHzaGwy|*A>%a*!1~q`XV-c1)Hu3?-^)^Q41-I)p1`|6BwI|k($GFJxk?w8qBA_ zxO_#go#1;3h=RiCq*6N#7@L6DGIkmuo*vf&D?N^fi=QCF##CRM;{lsXc#1Lam*V5b%!RB2QCk~3(cp-<}3p~ zFZgi*RG@<|{O69rglEtobQ{vSrEwX-_X_wTSRN#t3|ENLZOi8QLBl#hCYFci0A<5z z`p3F`D)blVvhu*mvxgKej+vW)56j>Jm)8Um_~oJ<0G5O0VtRSy76YFL<)MQS zPCpnLl`GF0_`D#W3+0`UIG#Khij*sF3GfN2?<1Z(e0MLe{j{KQg~;m;d|Z9G>s$lm zlKnYepu8hId3c?arytrq2+_|G?#G;d@aQR5ooj7An&$7c@{AK;qPpTu7wEx*}7sXfiW5gO8oeM6erqO(SFDM9RPzyaQ0C=AwEKuO|W@ z*)?$wbMUhY@usi?E#w*)V6J{W5q3xj|6j0ua$~AW|L4wSCqP^rGui>b`!N@|JbOsM zIMan0TSGkeT)^uGgDL#DV-W8Kz~v$4;_w(N!;z___^m21@X*+cebtf86%zB6p%_)zzr;WianW2J(g2KJ9_yOHWbd z*gkbvqm{#^r6WC9%-KHmB(Oih-!82lt=$Q9KwGn^y#9~(9`ujK1;pkAeplMrY1=gP zOTh)?Uqj$A1PSy1;IT0i$^W{>kVO5El)nD>S&wwuzrETP^|0^Z@N-eDp9p!OadQ9u-dz%8}!Cubzet`}=i*I}RA z=`)RmMrMp%lIUXwZAVkq4)08&S5aXMV}~~k?eJ)y6tbv;5n$n^p14gVRfFeYf=X4A zX{3o}i6WUD=rtHCrbxzT0c{r*1fB`HFt%QdrO&s^XaOb3MC%{!Cj$=*_W5Apgxo<~ zs$>rrL+V~wPf`zg(AU9`QtPp@lH7_40=4qF<3^T|;98Wcjh-w#i|lHNXe&OI2O4P_ zU{lsOol5H}I~g&KuqhkoUiZ?FWX>i{L#kbYH5q8<0@}HhYNwP6XT-K4Org@o zxw{k<*_|)?8sn5hSs0@)kbz(=)xpo*JP(epas&ESMj&^z?mv$1Q0N8rU0>*<+ZpE4 zR$i19+FN;YUM`a{o z%h?B&?xiVusSZ|*Fus!?XE$?-v|zk4*u0_KDRlcyk%Ao{*yowsGktanc$4Pu7>b-O zk(T22MfXQ=^>K-`0^2ZUx^_aE!b|w3iiO1 zH8<>7XysF6h^?4Jx4@x%uoHaBF!z*r>_Gj1vJoO~>W3zW_A!*B0eycT-4mJ{78#;#B(xUor$z3khx%En1X9oIV=uzH!jGqTHbjeJ zJh&$k1s0Yu9&i^50-eC063RgCA5SCb|I7fAu)VC|sn8!gk&6dI5>3i@Y3FB@$!9^C zH2#qlWt6@Zz$+6y=7o0*`n5)*92-u1X1tDzbuhI_8(QiiZOPhjwqk8KTeCKtZCD#l zSi`qMzILn)r-ZfPbYX2cU0EAWDQm;&&f0Lw*!^idC<;W;YqlT?Zo`ZZcbv$BLug|R zID}58*N3#hw;YS`M%UOng03@n^dTmIn)RJ?7*oNYLm*8ccsd2l?Po`NO@&!D32>} z7caM=tV-A%{ku9cHe<6iDy}1}-NIj~UFz?Ycjph6cUnP%a(za-66-fbwc_@yobni( zvBwJbGvMk6_q<9te@uDD1=O!H%X=)~8myf1m}`EAsN(Yn&x}fFPo}&Zf4IDoKV05o z1^bt9{j)OL6Kq7w-Jj*ZC~uB{>!C91H&Ol1)^D#s8FH%s%+*6(rEKUE&H-_2?P zV;C5FR>J*-DQ~NQ^H(|LG550>01z-hQ`AnR5_Z3X1{8Gyu^sF;fE0`qE+B0Jdru=ZWWVEw zMd4R0UjfVaf#uTx0|=C-h13-69FT%M`g?znXMh;wSs;b)-mQ^>JlwMm`5ce}Uvs3u zhkM=L+_fx?A4*Dal$@&ify=ngepmz+W*9U(E zNWrcmo#mtVR{*{Zh=GsxF93XZ5rbanXTY{8v@1|Mpaq!j3O{8?cYt;TY6nyYD5j&| z0oxYPj+hSAnoVzx)EVl5R2R-WQWuKyM+)r}h!pA@g%s*X`y~Jzj~MDd38@zJ6QrQ; z5~QH-Dx@~B$0t(gN6&!THiLaAfZ742{S<&+W-5^12J}H%1KJNL>faG4>hFW;z~_tU zPM{a20}W);BawpsaY*6#WTdUZuLM%iXBkp#KcrxXaSSQc^CD6>|JQ-qIzqbwwFCM9 z)1kaqNTFVZNJ0N^NTJ=)cP{p8^l6Lot&xI!JETzGwn*ziKSb&db}1~4M+(P{Lkic; zbfnOqk0JGdeuxwXM}zVkh;SjszA|?g9-eQS|A1clQMoA(02n9C?&|kPiWwD(I4$Y^`T()s~WJ00CDtS z1jGpP;Q&oZ+wZ`oK-=r!I0o%=;FQsJIoe3g@Vh?<7OcIKB}GA#LnG5}A!s`rXbRfC z29{Ca#Nj_-VLY(Wbz#}zR15YEkqDK?W5E=I{?-h29ST3bJSnu*6}r(N0|MMW=n%$> zV}icM&%cF(E=eClw=2XY$VWFW9##5{oG-*V*_a*<4M?9G1Q58m4B~vgDB#PaIhcQ3 z9(46G->{0IavD$%tO^#7@<0{3?%Xi|DeGFod_zcq56j>JCj)NPWy(zkJ}d{z#co+% zxv9YC0r^}gPu_Llvj!%VhkdU+dDy{($nyj~P9FB%^5n$;pBLnFp*;PvdGfG7l_&3! zK>ZrmDb)|EUaq|Ez$c`>OL+1iTCTh!0_ADJh0C=cUc2Sh*Ae)H=oinE2TP9S%3CE+ z-YcFwSduDN9)2?}L_dGv z`nFaeZ-PL1XL$19^|ajn_d%e%)^HQ$^phx%7Xo}j>br?2563&@-48AclxGBEd`>^9 z0(ny46QbXAo;(~ImZx8qKzZMI@;nvDvk(i@FADg$`r`PhJpJYhly{paucHEaDyG8p z>j-?Dew`G^ixVg>n#go@tfxJ2v!u0b8KJI+@E08xqpu96YdHoc~`yfzW>-weo z1uBpi0(?Tw$0nY<{tDz>7AVgM25DUTg(#3G1wJAAP3OrAQy?!(puBH9dEpA=Sy&0v zFADg$`bH{{Hy8M1kk17X8zJAPZ}a3u0gnp&G~kDG7~C-srBt9$4~(#Z%OmA=1U^o` z!N6Odyf}gKvU&1i6v%rdP+nu0Q{(iDRUofB@Cm8!5}v#`1@evvl&1xQdQQLL3gkHg zpAh}xdGbaokhco>yda+o<(=OGp1je(T;BQBgSk*4@cA7>H8q z;N=*mbmW1{Ls~_i3g4Rp-#Wl3Z$A7udEjHs(UEa>D9p!N^IzCs5(@$Kp=b!!U^@X? z*|>D|wh4-hi;d_%EG~2?WfKt;Ycn)1D0twop+N&eX&f*-EHofIG$Z$3&Ct*RgF*+#F$c%S4T=s4jiNwGY+O)(prZycG@MPL%P;$n@2d$v zu*UVx(x6IUH3F*>ScAY-2&_p}2l=H%yeqlO7A6LYz82TA7~j=v!s^a27F*C*o%xO% z;tbYc_5=bfrt@j9lMrL}_pONwMgPD5AoP30`VXocCzaZiW8CJiiIk-dB~GNQbSTqA z%36nNm`F9yq2T$bO^HXu6(v%JI+Q;6q12%aA#O++CsM}xRJ}w>Y)n}uHidz!MPfrZ zkrv?3vL00*_UyF~S!z@D=H~5Bq|9}Yvz|G9lsU#Njgiv|IJK#P&QV45Wo@2F85xT7 z5-AfykpW0Bp#STM^nl0bR5OsnlR%e?Wm%z)3w69p5-Bq?x&$*U!2O(%QBdZsz z4w@@tJr~8W1|*o&}BJ#|19h2@<$C=AD3>D4a!k z;PSY!J>Fw6piO|7jxqn3+hOTD0LP~dis5z7h4T2&HUO`GE|kZIHUdKU<^rFX69%+A zd0D`RbDUh@_)H;zt2^es0zNJeF&D21aXueD*Z6_ULkd|jTpsfM>{$uVtQNoW%yM#Q z$~yEF;1`s6n9847{}=W|{>U{T-EeADVHu1ghSDI!FX(MJzEniz_ytA#5GFAC3}Z1k zYoU|J5&7eZe6%a!A3uf2pH1Y?A@b9R{Dnk5+Ntp6|4rntA@bMq@=rix;W*C^(tfrF zGTKCO0j~uQ9jdl zJYYUgU7p{_sNdf6nAsS)LNAg3c57s5Xau-Fj0lQ~7|nThM5mQ*ustw%Qe+2ETne}) z9LjpUjN;N*7Vn_A@PIDTprPUXgkN_z$yAqiEa^QgiYu(bZI5MgkBIU^1G>dTMZ_^4 zCIeW9igcz!IldJ6JOSNVZ;iYmq+D_(xKF)l)mf?_S-&=@F*%{>RF*@3Z?K=Lf-lt7c-_3!3O-mOJ{Z z>e`I)SXHge{>Sf=yo%0(e?8c37Iri4l@ETd*d355b_Zle3htxo&F(ZhIPX(L&Ng-M z#-);~vXI*o`K11oZRitB4SWKsR*^(d1tlWb3t6n1s+OiSOKDMVgeC2LObtA0A>#Hz zrU3KzLPpPa;6F_jJ-dn0P$K?BY2LIavi60M^nR@_j3>YPP$yS+@Z>k=eyLBc9(mwt zPn27vC&DAWVV7JgD7T35+D3sK@Q_wjlmb4|s&;rG64`|xf<03;*w(@$Bn9UZ!JU#R z>`v^OIJ3hGxSj)D16_(tXqnaNT3{WSQVdKPe}0leLv8dcXF%`G%lN_jmZy^DQeK(CHQF3g_6SPvsptcND8 z0n;Ae@;qLsOA3PUJit3G{5)QWJTy%|^=ImCAASOAr@Tl{eCT~urOm}!VwFYISEbLn z?-QvLnaCqb>n!*2CQ7R&dqX47A{E+iBKoOwtVLO3JIkP*@8#oO(o8*IciR@wCkmw= zyImb|-{}6xmFhZ=w{NsJyC*IB$5Tl?xTnniwIv&6)qb*vw70l@=^oOms<4N&SjOxj z?XADtRV@#9)m43$D1y=?3wRzO`#@_`)>^Pf?nV#Fs&r53*M{D-x69HUrI{Lk%Y)6i zqLKo!6;A1+CrBlbN}0L7(4Yq9tEK76l;mFd)Y8uDtIGFDKF`}H`K*46@M37=GG6FP zax}P_e^HmfF3D}Lz*T@dP%DWd#WHBC0nGV`k#zbK8_ftb4k z>~p}qhMC75dZYsJ|8=gNHFbgV6^Y zm{8FJ5j~_PtZzD4Cx$3RiCN!trtG_c8S9(QoHpyE zNh^BH50&Y~ruRc?K~Vunbtx(kDez-G|Ag;07c7S!rqX8w5&Hweo+hA|jnpXSJIRMC z)wL&ROjMtwHd!@UWs34Nr4;T+`L|2Zj@98HC3weyDp5*MA2<~h`fmH>@+NBhsq&a_ zmkujcTpsj`N~j-GUfv%rPssVJ%=!sAf0a`n9p+_m|2nZ=!(qgy%-3wdYF#?OB=S%@EL@ zl~W$`9rhFf?FrA@N@!1}yte|{vogyAzn&Fdf0a`n^L+m(pgrNCUJ32Vl=oG@{aR6Z zIDzvY>?MqLTDUiGI#L)noUdl&q;Q-W zQs8$$YRY~y2>dd@xaY7JP~3Ca7xQ88H5w_rB#c7}dQL(LdZr=;J+qL)MBjC!Ag_p} z_{|?;OQeubf4c|zg#flS0N=?#?SKx(d~^6#4k_r7h!ol-9VxWa7MAWs3i2+nv$prr6UD2g^z0u~U)tUcqHUkx#gK|l;Ww%0%k_k0jXkKuupegOg2vJ29P6@>ASN0-U+ zI0Bu);}@~rS$7KXxYv2pz4&vpxLY!_}Hg6U1;q`*$ z;WI|F!=u+~)<&k{PfDg;y0>{?`68PmdhJJ?SV7ZuHUb&9I=MMQ? zC{JEI@WG`@%Y$gS@>U6y_lhSE@3-aYR|op85dHjtkJAtPQ+e_x2$Xk*Cl4;oa^-yx zD6chClG6_^{c`1n0H2WhZsN&S4;NB}lzmCAi>1U=u zUYtOA**tj`3gkT!D6cVG6r6r||1Gcmx&xn(`Yz$gL%HS2J0eh?7L3C={TeEe=Lmd4 z^o!@oYpg)tDuMD|@#NVkkXHw87DDv%$MFQn!TY_P0(lbz$~(i8=fIN(!z6rm#{i+j z2jKJL08s9J0M#q=Ji@(-4?-sDrwTvr{9>Ft2BMS}Jh<`s!UZl5DgXJV2Yfz|hVq)j zkCSI>-`uY0FWANXzh%#09LJOfHM!jxlcq}VA67p85xN54^k!uB15pF(xEJ9tF8KU2QY^ngbnp!?_fjRJGh}pUxbgB z|I;>3*pG2MjC~k?+VJZGKTPAoH;B;l>TCjcE;|9{;+WL~z|Y3R_ADP>FBsy156?Xp zuv`qL@Z-z-b9)9iZ`%A9uG^+g4(!(8725{k*cyV|HmDBP@PB;IV6^2a4QkYlG8pfg zr9p^o&|x^fR7B<226d8mP)485EJoX)#ZVYND;yw=-t)DzaC+TqBoD)ogK{HqO#;6t ztuDU4QfGM>h6H7NbRbS8@)HO=h`@NgaRHB)asVh|F@bsNG3$7Y-LBx>Q#(e)#YKg> z4-Sb48Z3*A9s~!nb{i-{kcmrW*{@W%U8-AnXz)O8Cs3YsNvQ=3Ylq?$6#Nq-6lC)V z9UK}9X5iB3K|v9N>3wO326PP#85SHG(AA+6{Co((KRtpiCjiZZp)jzD2?(HV&;x?Q z2L=on78Dy&CM7H=B8n%M-mui&&F!b^RDy{N>=G%rius9+Oi5?X`au*vEknmlb5_+f z_rl_qU@=og6rLDPp`C~q*v*Kl!LFf{RZ@7hw2npjek!waAqIKvRcDDH2CL^I)nyVa)JLEvqTBXqpGI4y%3qJtgkW$SKvh-Q+*AZ`?#y*bu8*?kNe$q0;?G#dcV>M zkyN+~g%&YWw&fPpj6wbs+V((2zQbUOezmluhzrFk8P(FLS-oYV2xgbaYH2C@hz!KN z==FbbN{YTXX?aRe5=y~6@lx15@r=MO#wENeZ5zX`&a-v_A~qFm1H6h;Cm7<>>s6y|$ct6lJd_@qIoIc)k z=Kb+h+ClIHgc=!&Q}lC-%xG&DrjDAtIx6KW!H%HI61DzThdm>EN!8!ArbY(t38d20 z-*pthPsvXzl70@P7D8NE`K3fz^s<9UQ`$1G~QDb!k)_t_7{D z!{#_eXzAw4YVp$jII@ z3p#CNB%a6mrhfEUOwkvm0gonmzC>`gxwEzRov4O3So^qZ9|S{Hm%^+eRiX7BTu}Q+ z`KrBBtx8$SUR0s#=EJSh6w`(qH#g{5M2UwRoGQOSWb8-YD}yNt5*l)?E_ z)?5VkK+2b3Z^&LUFL%)eY?T^l{V_8`nq1J^X*XDiFqRy03l7GbLn}~;s_+kw3FL0p z@R*{bFcC-33u>_QqVQrtzjMG`9ZcuY|L~rV6L#?0Lce(6oCq!qz_c?xZ;EpU6ukSG zA_XQ3q%aXgwUq);fz{}VP5ZdeZexaJxK zDHoSVE}L+^oYyK<*PBpfqQ)fk$!f`}Q>%tRkSjupR%gpB>c49Md8Hm&==|_FLt- zw1tBIgEbQ|h_!_|C_K-0Kqmo3|8hH#!uig|d>EJ?+N@#qh) z4m7zY^gDWO1^P!r#L(Z`B8AR~ebyFU1j2yY0gc3TkcS2-xOT7zDfG8=ptjIi*8sHx zx&hOH&jtqin$X{9KZ`&;S=^na{gHxRgIP?kp#UGfb^>%Zo4$sn^co7JA3+RypFs+G z(`zcAw-Jo2TdJYZlD=I!*vU@=w<*Fj+_#4@|TSmKm?78N36b z8R+mA{0CL#;RwVILM9#y-BkX*H5B4}c@yBEdz=u++!R48$+fCv;q8@^hjH#0l(7o# z`COks%;g~kmE>U)@QDGTJbV^$@?d_;$>|r~lkM&7*iUXMeoywt!g%k=nyB6X$akOP zY1O!Y>dd~h9E286kjF8iMuo$Fu5EF?i+=7xnizgK-^Jy@tr9St5#D!~|LywvE^z0$6C`kP%v%A#l4IiKarZmsQh;v;fltii!|MW>$SMsWn9IXNE)GM6GJGnW0_>5T45ZKo*c5a?zMtKnZ0%e8()Z!ca_)-n z6Jka;`Fz^X?-Q}1Q5Ak89v3?DH$Db;;~IgcYLui5#$Hkyl%dx&1jw}`HwTVb3O}5q z;@t!OF;n0+Y-n8cpbnv_&Pw*Mv(xS*N1^cmf_?j+YyDsdU7Gw_HxWUp^xS!DbVyKKkWKKg*x{kHvj?{*{N~L)MB2>- z{yRE43F32T*390S&&iMfLppt32EfBHVsK1!bd*msdxtptUpk_xljE-*;b8ZRM>sTV z{;Nkg{Hj*=&c9l7SQ-6At)O*df4Oyk^#}*MUpxX@_g9Z_aQww1pml%sh~~oTF*Gzd zrkR7iAnC{p{Z%k8w9G&u=L_WuZAF^b!BMzefo+X)p_K*8h2ATix5BgM9X&Ws>KWjM zH?M$-ZdH6{_ICBF&T!CK&cE_^gZm_uh98t!8T^I7Un!$9`QM2AHJsu)39Lq7bpmS;xC((a30#%H zS_G~})JK=74}(kf*CURvPT(2@)+TUG0@osNZ35RJa9slH5c=y8`ZKsx|9Il~p#+X2 z@Gt@oC-4XYk0kIY0*@x}UxfbgwEm^~9w7Ml5O^OWpz-I`2mcZu-e4Z%p0#V*7f`2iAmk@Xd;9Ep_w~6w06Z~5VoI&7B0&gSmb^>P+cn5)Z5_lJ(?`}fh z2L%5e0^cR@Jp$(w_&!nI1ERdf1iv|fEeKqnz?KBIBCs`q8xXi5fg2I}HYW6KPVhG& zunmE232aATdjdNUxG8}h3EYg(w>hD&8NshlU;_dh64;2q#soGYa6JNx32aK}Yewkn zMew^2*pfiomT2+=jqy3EYm* zS3>C9kKpe?U|$0FB(NWWdl9%df%_2HpTKZpgudMgeZvX<00IXRIEcXg2^>t|5CVr1IE=sp2z|o|ePap!2m(hEcp!nJ2t0_u zg9#i>;1~iAA@qd>6PRD&=H+pXiF?;V+XoTPBOrsna@mxa&VNDRmvU@P=RYFwLpc`H z`L7B5l)%sA7#ABvJdcE8$PrObVmBF|Y#RTSfT!mr+a*E{MteJg8MbvOE8%-Y}e*}R?$}!p! ziKsXN50zu4J<&Rg35>i^9AxE>Ch#5t?%Lx28fz#!f=?_Z? zyjYHXASR+#$}v;k3IZ=Da2|m#68I8B{bei;2i|MLtwN{W`YEWh`PrjiehlS94A6dMBSHT=6+qDz?KBIA~5zc zCWwKEc;3#L`-eH3%h-B~(0L&n^ni-cSw9WkqBrw*J3C!`v9Axz|kz+B$MEJn~8^l0Gw8s=CfzhWP zo6CMbz>^`VOhomSV=;~W3EYRk-URMM;LZg0kz+=mjs)%?#}bH%sBUsB zrg2vScadYJzXcJvKY@b@93sa|{|F>-fE;6vh#DZrOnG4h4wYjm%|DR9Q3M`D;K6c? zEhC~L2^=BE6X^UQa?F$$L*QuYwhEIJ2&5*gPwy#%zf-9!meBdSR74r9N3~`#_UxKe zJXNC%K0rNCh71Ty{v>Kg8GM9FE`w94K4tJJ%BBon#C~JM$-6*ZR^rQFMXfD^uhPD? zO3U9ud6&t*O^M6k-PC&#U)}@iOc~smT3rS=rxMCwGpc79>_yp?!4j%U8QhP0z!b-} zPj_lx85~Z{ErVlAjp-o07W_)@SPU+GVlkL4j+Rmr|1);tp5Qe;z$I!xbZkUi_#kQM z(BRmJn7HWJfNtSIU^T_FB<()JJtV*<3JlhKgJK!i?u3{4QVvxg)vs^avCc)lF_+R2P z=DMY_e#*kgQRwZ(#=bdz%hJ?A_{S`8OEo+-(0c3g>`AXn6o#>e3EgY0G~RLX^`(#g z2En!bt}gks;_m0W_$t5;+N)Ig@Skx}jV02DHPu#m%$XRz*0B18&;uWJFAjZmuFWF5 zcte+k%2ob(NSTxym(C@uIQqQ7wxIYy3EpjHcg*t~(fE!@e%7S)-OKg2h+S{-pBiNj zrGeTY^?xSvQWPJJ;}#|;YAx80qTFzF+N>=#r2CcMOZ_&^J~Yz2$IPQMVh=@`rZ&I2 zrTwi=N1mIXiZA!zl9G1pBcG>nX_OsqlqT?Efr}Tb^qk%8;f;Bjxg8q6AKgpuMY8$b zuxd`%AN7kpue(JWe`IBc+$9EEV=g?}mEBd`V3&EZ^Li!64QV_fzYwjU8T5n`4SrPnF9LTyfAvr?CH~bzQk-oa*;qrsm zgBNC2t&*4c;j*1ai{oB;Htu|&|4mun>bW=$QS^tT; zbDHfKP%Ur!PMuSWHr~_uf=-y&P#WV>82Yn2%Dx2eJ0CwZw;R4pv}*S9(GMFtb!_#f zbL)b`O?A6X8h2>m>)SK!n|+=>=lJ@r$&XtEZ=e#FZQbOuOljRTy{#cPjpy&&+4El8 zQS0usY~a>uW9;0?T#4)VNevCwGWVgaqr5OvQz65 zZkk?RQQy}zieFOGzQ@k@+peA%Wirik*Txn7ojacUZgcU`iXnsTmOt#%BIIRW=hmXx z=B4*-PCq5}8uh2>8_6Cl=%*k1?n6Q5wj(x1`lgY;)34Y|s)XN9xHOKwJX9|-#`VF~ zHVys#-5cDg-L_zN{t6u~m!bUjU6F=(sP|4E=63eUJ+qEq z%|Go(4sNj@^+nm(HXP;3tvjYmK*Z>|4LY>DYTv8m#71AwAvfX!@*;yqJ_hrSI0T5fbfTKHaMYHMlWB?bEm|qpv0Pncnnr zkxqnBnXlcsGa`&Gu02CvGktdNL63jlKT&_@^jxV@*Dr3LGXEYvWPQP@2|=$eJ}c|g zOa2@$uT(|PFaK4$c2*BfsIh)n%%kT6Rz)ng{$_V?VS#tkKJLp`2My|RtHY@Wz4m7u z{G|Wz)77u1#<@D~9sBxkjfC_Uf4}-_anA9hW|5ADL;kc!4ki1N_mA7%=u^AW#STy? z!tRigB}{Mf`_ZI(GT)Z@whsP%TUh7yUuN59$z!px>oFBCgBznnd%PODT}fVSbA3#= zIBV&UGu4bkBgGTG{@CmH)rj^4R$eU?r*q|Fn{t7F1lMmmXH#!BoX9)VrGD_YL#Ot< zpRi1K?dC5}viZkgoO|YA{AY4H1YWdi+xlFqqKs~5GSrMivnQnu@3H^o_NQ}NZn)m; zSnv6V(yqHZFaMC<^ktKzG0GzfC98rTKgllkaBY0QFi&^j$1XW7!X-OTpX+BouxHbA zjdYgPi1&K=G-dHvgC7rEA960z=sx}xbm02LO%t@J$6waYTkP28(^jvR^OoA&e`D`5eq(*lCciUguy0oXqHz_c>$cE{oZi@u zWN4R}+#{@{S_c=G<`<^-yO`4|-E-@c+gtXM$MD<#XYrps)A)R8y2Uzuk_vm>us+x1 z*0;q<>QyJ7o7X?R$EJO^KPQA87`6Md_ScygJeKHppSZ>|OZWRajhfZJeO=Wz^vFuf z5jR_UE>Epat$;$fKE{`gaY^2_0d)$ari?6(uYPELow#G_XZt+*xZugr#mADa7!6o@ z^Wc$X9i@L6He1;?cBJq0XEr+Z(l+Nh&u$vfs_5dL@R{RE>iLYyX7L#f7hCpoL_ZSr@+u-`css5961Ilb{bkZnw!8~58YpG^t8Ja}k>qh})ZU%eW= zHp6pUH3PqUOMv5`jon5sO-e96ml>#eaCgCu+V(e}$Jbe8 zz2Eplaf92lXXm6X>l@wJa=zDH-R9U<*fv-PZhXhbWFJ^xB}?C8v3(Q$RR;GSC$%Z@ zXt4WROV761M~yam>9((Sd0x1s_2@ns?M!o=8;Rab(CW5ddBdU%>op^rd|c(%U2X4+ zJKEk;CO5b>ra{}OTkRWWjjH9U_Vn{7$q{`~V#lh>a$TmMcyhExlW~66ou3Ta5WcnW zWl^)dQ^#{ZkM@1|!ftfWq7i-S8SAG%7H#)c&iVdc$BywJ#hrp*qFmj$bNR0+2s%D* z{iw74w#HRLoMxHqir%-yW66}=CwH{Eu)4}8PtlpN1Lxc3jGsKI%a@7@0a^TeaYgJu z&Buzh^BH)#p8MN(j*Z(S-y7OYJtwo({)1h0{+g5Us*AI}@BJ$8Qf5ub+Wo%n_Jw_7 zZ?1SFnYc6EbkXd3i;Pl&_OzXcD;#0_A0M($Ncgo6cG=nIDk{6wQYIb)89rfoe-EE~AX#!K zcEzNa*3E*{H@6e*@i{87{LpVAAG0n;932$`n5$~}L2bnJn@!()_hPc(BqUF}8e%$)f{%)>NJ^cWev z-1CR!;p2bbzbwrOpE-D9_V>0TSKeCVueAWIqioOKyuD#pl^Xr)&Z~WW`@GG^?*-oO z6*DxztKakEn@9UU*mdDym2ZK|Bn^Bn&+1j0M;-q3Y(d|+n|p%}JcxUlxZ=TI)gAr% z4Y+<{-mCphHgv9C%h7e-#6^B4hi_%?|J3`Xy=?lN{+%P+z0lcu<$!7MO`YHcOTt_{ zK06&wF&OP}dVtQ6?23H&DXYKRZP&wt&_2pMit=zF?^^A{Ji?qM%)lJ{!*{|ck z#dnuqS)8e5y8BZ7$zAr%P5I{RygxX_Q+hXiWnJy9&68`Vq>f*s`_}>!?>e+q)UUP% z!++z@3g27vC*&{azwZ7Zk8?A3&B&W$CtJDpZ1aY5j6WzH&M~?>EZ|-1=-f?57Ad`Z z)@R_XWy@@N`ERWk9eXUvKb1Ri(hvKC&P(p+XAYO>&Wb!)KPS4*hlEqv^QE0tjAL)F zJYyXXyt1nSExLL7+iIp3WJDcpn$d0Ys+}7WLedY;T-@NxigqKOC{gWmtvv&#?e4Qb za#HHfItJU0$3}GYco6a9u#(I(r>S=5OK&W@nC&cnrv4}~J~pdhYqy-f-@S4gX~#ZY zvUqq}N2eZxuS8Kim-VaI+o=EsO<>rE(>VIcUzLqzvzMWpfNnvi58ys`5EpPEPYDDsp zfWPOgUA;2OSnaZ2GY=>$aI|IDYU? zXuP>WYPGXUb%tLmT6t>WvJTBGHl6LXZ1*vX=-7j?pL{p?mH4$8m~--LE7iPNMY1=a zhd;XZa7291)d_bbZ5p*7cs*Zr_|^BO1NZDz*Zfd$e@M5LR<-@IbbmN@-DEUC&-0Gg zsAk502aVG1^`?4<6W3N}EmX^1eRjJ?cdvc9iGhO$>`L~YzDB*(a-VBgB{uJWI38@0 z{X6eed!~Fpm)c|Pu@T({*E9C4Ew&b0UNJ9fH8^(0_@$|uVQsV5zgd2(=hyYmt7o0w zf1u>+T3^ovW94Y)=|c#<8$0aYOFMWykMh55ncE}r>(i3aE_TC;-t@F< z{B2m3-eY#EPcPBCeP-af`=9(9=uDWG6Mt)VT@7Z#3+JXob+vDAh{kx~UZc^KQ#G#YML3Ipd#S6Y4xp}x*aYFZ~KC(4` z-TN`!yR&zYWyf>=>L&~ap1t{M`MR<59-D5^^;q+*R@1xJuisC9p= z^~WymKfwI(o_F=Do{XLF(I|A_%hXV+=HgRSt);IgkF7b;Eo*Mn#8!3(>v-jLEw;Yu zzoe_K>Cm&`>C!9x&Uj2~Kh){T+ba)l#ym>;>vzVM5zD4FT(Q`sjg`&zcbT;=f3toy zXXL9rvpc`7_MvFa`I(5^El;5_LQ!>uXp>pC}F?b{S=#sJom1bjz@0V zFkjny;d`CWU0cOXeb#B=+mR8eGp2eR8ou+W zUA^Rv^)6nm^CV<_kM3P(H;MAv+iS(yN44wUYp`^HYWV$pL+bFXDn}-5&9>V<=|^gC zCyQp)9(K;89F9+ZWuI*{AwKV-`G_yekJN6sI7oc`@7KHfcgS@q$*{PzApS^;OZ|NY zY*~`qYQy~l?r)sTUXECs(pgh!Wq6fiW)^x!`>cAra`C`j(cUq0Z*O~=|J-=GHSG!S z-#rKFpIG)HYW?6v-Cn8N*QPus4>2%KZLs#zCi9xR#_He9td-^4{dJWgwsr5hJn>10 z?pwopkkiU>CVQsO*|)>L;hi7;p`j|zl^l{=X&)XtaO=*N=hxO(*%UQcr{4B*j4TjgxD#^|Hr!=m~Z*)nf89IAE(CNdf540!qb%=$phQv?n-L8W<`nn`S5}eBjdW=T3fm(k8`b= zG;4&ZOjg~x!K}}nRhQfk@q6{7LDgOTyIwgzFXd&X|Efcu#lwsbOugG-r=;XV1{l_4b{)>3uJ4Yf?)1j<_lB7REd8ycJbxlV}@unjXAX>_-gfwC%12(VRu^n z+sUR|o?LD>?a1?6yO-YCU=?Fnqh9y+n20705X?_uB~XO}S6^94~CNR=4KZ9VZq|JNeE=b9u}9>w5Qn-6T6W?Zqh< z$938|pWDp1b9(O4j^>-(hd4Z#(kgJ8{Ytx$=AU#DgZEdlzVmo*zg<3(v;l23ZvTo* zv*JD3Rm_@A3-1>x@$eZGA24RmoWH{Jd}ds}@L*)URwXG_E_`^?zg1SQ&W#;0f4`nM zC$i%b8wbQj}%?`9*xAK12zm=e&&s@SfXzu_6aFjue!8j>mfSp z&YFa;ym+UL^*p~_lQhQm-_`U&hhuG@sVmtYw<}!pu-d3rmS;X+ySGorc14TUvA#AP z^g9~fo0p+JVMwIk+_gL2hP|~)lAc;UW|KzuC3;IuTWAh#YU{J0)1H-^JZfw)44lw! z?&3D-XVMYj^FdCudVPi(}@tJv=|F z(}d_(79)~-W>>q_>FYY5BLQoD!yXkx+6B!zRqv3-F7XSK7gjA=_WIV@J;l3~gp&Nb zn;smc^^b?tB&3<#=G(BE`Rmuwq?-39-~K^mxLbLr22AiNP=_jTgSz%G8blU z&Oh1JbcCD51jB^|LHhCW(}rB#eBEi|~1ZgP%8 zt0JpQx1Ud(Qh45H@u(37>07HE9K849l|G5pcD!#dSsK$~!j(<~c58Th{LUEqn}V_P zjO4(n??U!%*XX#s+C`JsT1AFdZ~r>0;xcDU(+-JOvKj;)KR9)Ear@IY!|VJQ+sSpl zQ%U`E(ubLm9dF4D0`^B5RXcOS#iT>Ec<*-YE>8DtTj%5RIOPXRp7l91Zc;tXHKDa@ zOA_YxNHrPoDB3qLrcq?yK7nTn9q*hxDT!G=;(on$*)G?lMMD}CO)E-$WB5B`*tiPD zt}2b5{}3fTj;!C_cI%Osb8>bKui9ql+OQw1I$gIr64W^CgKBLX-&xB?HOk&P`iSfD zt?h$CTW+guHgwn1^SP~GK3jRV;ac^Y#zOt=rBXu*Ujv4iDlKt`NJs9+n*kl zJc=%vy{gCKD~6Mv8n?Hx_? zdCMbjd*Bt5mrnUXAJ=w$ZMedssAtoX=-Ow(N9HG-uF^S5d!vS9QVmgR`!Q|3zaHBv z`ue=j?86r`0^AQSHZ*){vNSDywd>{)8R>qVG~T?l+c)~{ts!AKZ9T0yPVOxQ2K3D83r4eB)+|zc01!dn5Rk_S`<}?yPEHojvYL=Q#s)ccl0530iq@ z-@~<6GyO(8cD>kkdEEt?-3$*j(33xr3`>OW;oiR(nZ;n;kx(?9mxuUw> zl;*=jv%1wk#f0!jsd|HV zeKC@L&fXV)vsvnw`IZ|Dcc?`_2q;|nDWv7xt7}JWSh%X~E&rii_Ks@Jprg(%eY;Nk?r)k9)nfLE6*abgoOh)|w?3JBM``8GYxa1W zcF#If4fZJad)rOZH>h!hdoMIEdHKY9dyqdMGQI*5z zpRfIV^qQsCwI{Qt9g51xP2G6=t0YwXe)F4*BUbJ1thZkgVd~_)xu0)XihI`qcO9PO z+pMyx75Svo`iR_?EqmE~(fuH{aHtvhJJ0Cr;*TjyKT;1MhxyY+I(r+3aB{PUlFtzk4{|CspJ z6YGw7WjeV^q3+$ACq-tv;$Dwb(rFto_s-nLZEouw2)a7!(!uCe%{%!mI2|)l-R{NB zs;av^4|(;9I~Cvg;ec1hEr!^>Zm=;`tJ{>xTJ4?$B~Si)Zolh}g(=3#7y67%h!Hu= z-0?zxu-Atvp2J$+mt-U~dG;aG#$SI?zZd&rM}2p1t=z8 zZN`Mv2`%ihxQ9z|gN>%TK8xlr3)$JhY`_lvNX^TSQ=iw~QvLXHsdMs$mbvM=;@2Cp zO1h=InY`M3$+%4Ev85XqgnjsHr=4A`A2nXtuFMTwd9P)=*H`s@soHj)>6cgOsg4^{ zH2jeL{-*yAdtU+=Rdu#~XOc{Y5FkN{8P*8|49Jp%070ov7KX4%3{(;MB!L7b5+H=2 z*rEnOjVKThZCF&asHoJUqT)gc)CIRnlv?UXZEXFjg4!@bjF!s(Jm;P>b90$VE}Ht; z|NjqU-m^UCJ^S{aW!fX5W2z z=4&^ecY!-*@dLXDXKsJ!&dPgsZWuN0!VYV%xb!y#GgCby58Ri#;i8vHZEJfj8j+EF zbljM?Up)Wsy^daeO;+`!vb_K5cHj8nAHMW;>~p^#ygu)lJB$5q4DOWq_8)e?82#$S zS>HHkeKfOT?LF~{30;p2`u6L8W`Fbi-~O^`z%1L{w_kmJx9(3*SnFSzQg}z^g!|(! z+;`y1FTC}8Z}|Gk9oN6{WR2~!kee0(%Nu{S^ony{pLA@=V}~;{C&iR$HJ@B}?RB14 z?^yip!t=iOgExFT8k4$y|9v+`V9-TWM!6EG;eJOX7>w zmO~&$Av7)RC;q3MBfP3M_SN&Z_wT>vPVM#&D=*BBFMej=SKS`(T(s@oUnTu*{?WPT zb{bn&+~wZ)N9^tM&`)~y`MksD^Ij=)P44ndivP;%oHf5b@W)FAowMg(FO6FE_a3L; zz2J}gw?_5avh-F@&96!qFFrb9)~l~wHqw1fRnm*kELh~dxa9bT0qcKuRp-KeaRZ`$ z^Tr1ES z{bl5?SrJbj-e=QhJ8t)0U*PUFyYGO9F1hD}M=$xGH@jB&m)*1R_=Ueo%1gd$N@JhH zdrl5`a_C*3_ls$m@N&B=M?U!50|)-`=iB#u_Ecu}l8+8xPt$q5JwN})`aee9 z{Kv!94Od)#)#MAdM1Q;gj`cBj-rk{LTN4&{w8MEnK_NKiDyU!j-4LIsdAc-RJb)7%}GV zw0`&B`PH0~>xx&7tRC{`R~9~a>wTxbx$4fXFO(KPoVoDJ&F!B0*)t7qU$m<{?&Dn- z=dAmB%$xge`s)3wyDvI=;M9gK<&U+CzVOP#kKdT_{PZJ#z33nQ8B^;X7;;6$<;5pf zKRtHSq&M$=YRQ0g^Rs@stmFKvHq81%R9(_}zx?I8)3WuiM{FLr~m!- z+wWNUZRZzn>(=AlTWj2rf4Opq{oLRACVhV2M^_~NCHwhbA6oIthtB`$^jZJP-gVWj z`yPL1-!1RNynpe~6x;h{du}-W+uiF+@4jK~+AYsj9G>9FDCu{}2c!S?)wEZZU;XT7 z#drRF_5C~V+WYoTfB*0W&-)&W%~{si&+$cv3-ZhU;hFyI`2Amgux92jqI1VTm@#Ex z(X^+=w_Ez`H~z9KH&oP5T5xR9eX~Cwu)o*kJ->SBwdWnreC)m@ecVq*9A0-})#Yzr zvnapk;y14A9P|9+QS;w?`jdyApZ1G`w?DOHZepL!qc0sbwCsbtTYKzkxb)6;RSWl? zcW~@|zub4k)i{6QxNlt_Y<;rV#1Zoz?owP`dd>NdZ#!|-z{}3R@n2VE?fdE4bMJUz z@%9Ck7xn(lqrSCAreFS+XL0Xkm(RZW;|D)YnjLfDyJ=0AOuF^OleSy7MqOXwdwodU z;o3K99=W{uj>11InSJEVZ%%xD*IV92|9q$G3ytwd1|0t6&gd^nUS4x(8dziv*|!X=eQXZ-ot2R$5*CPz*9>Wy>9{N}Q^hwNTe z`_`WeE@-^#cV!W8mMs48%8mzqyR_5Ie>t?g_VK*glMZ_Bc_?p+b5`ZVPcH6NUiaRt z=%(&Byua;@d4JoVw=~LgY{!kSr(FNVoZ)}JZi>1(bk;J1%jSmY2&Gj^{o&Y0t{U^s z=->VKh4)52ymrowLyK)s{pp6;!)7OZ{)gXQ`PZTw4>U~Qv-;?B`NRI}j?$mLy0gRI z^Zb>4cU2^dewv5*p@tUf(Veyo|UqXvgzNL$(Cp$0PaVNIqjEAAG!0#0MQV(`~PneDGkqhz~x#$x90M z7bPE@cI-j(ZzUgOWD?E$C7<6&K95U2Pf9*dNIv+;lStQNk`Er5chmo`C7+#=56%sX z_&h85yde2JFZnzr`QQP15uc|epJybW=OmwZC7*XBpZ6r6KS(~mmweuqd=5%Jb&}5^ z$>(*+=QYXaEy)L$1V#S5Ecv`5`MfIm;3FI&f8LOM{zvlpNbbjgrqdlF!$Y55Bu6${m+1MR}c&d`?O}O_I+f$!DVE zlPCF1mV9z0pK+4Uc*$piW`BNeJERlScNAk6d~T6^?v#AiOFnl?K6gnzYb2kwl25hdvrh8aAo<)c z`D~SZwn;v}l6wMLv{vrFkbIU&KG#b=H%LA=N$EqXSL+hTDkvH@~M%0HcCF5B%jTa&;6~G`-76tLz2(KlFxR@=MjAXwx6q?XtXET z^>L_=^FzDbgAKgqYh9M}5Vv_b3_d)mb5Lwhfq_--Z5oUG8C zLps2w<&wJW+C)k7NW0p_w~6cnWqOCmcny~EN|*5(CgXL!jMpF;uM`=tR2i={8Ly!> zo$qix{Rpa6H5rHLjrTv&;o}O!0ei)1EbP?zP%^ECd26EX_n!c9oab0`v58;Gd75^9 z2!3g>Q@qLVN@Qs8m6V{{VK636g}oBEWO|T_;Zm7#J1pW30p}JR^q+A2PFTcs!P6*K z_@!IKO|^)tu!!3b2KSgLpLYT036U>m+zE@gbUY!$wxN{DXEVQ2i@0qTaYroTx(u}z zzlj!cE5qQ-_4GyHJStN_!{y7VFt{5{~~61CDbmrBwXP{5Dv`?XZY@ z$s+CuaQGik;o=vYYAqc}7ICA28yyHWSZ-5H<*^hv&bgFQ@iXH#0OwX9&~Uh2z!@)g zhr=DPh&y5t*I*GBiN$QF{@I+~LBLr_hX=S&_0P<28gQY?<2+M&Yyd7)KAUm7EaDD@ ziJzI@XBKghcuFf&dd>WLSj43R7pi@j`4w5@x6C4L18||rwA#`4s^dsyu#WDvzze zh013$?tn#H18||zYvvb+C*!Q(QY_-~EaJ*6;;Jp;b^_I8 z6mF>UFyp3L#4Q6ZR6d*eZLx@Z(IW1MMcgTixE^@2&`LT+1Lp}AM_`^~PVX|{LY2n^ zQ+ezL4p9s!Rla6igGF5O1);}FGrwsTaa9&^yDj2Av4~5+6Op0DeRDc;fh!2)UU1%N z#%%{KRC)9^mB&ZGO$@=$j7tGCE4XFAGZi~2di@02ixEU64WfpNOfeY2& zo71}kxKQQsf~h<{0nQzwJj^(!#~LmfxC9IQJQi`&EaJ*6;;Jm-wpzsP1};>;X3oD) zfD2U~x0%W#DKqqZ*Nn@xh${syRC_b?tFnmOW)W9w5qHEQuE`>6lP3st^me$^InwH9#=7IE&e*5a3E5myOZL5T7& zr?(!sQ01}DR31HYHL=I1SVl^X8CPTxw*xqjVg?$H-)9zagYb~E6@H}_aXT#HKC_4$ zG+xsxEu?n`aG}ZrM+h|h56pKz0j^63erDV$i?}#E4R3{Cl0{qwaLE?pR{&h7^!}GA zy<30_HUBf?c3H%|X%Y94McgUiLiI1^_zl8hFjRW6_1&y|eZchyk$+~~N{hIy7I80H z#2p4MRKIJEU)-e7>HQjMGuG#cz_~-D*NiK*h`YlgZihwOo4|Q2#4q-e(CK{@evRqP z1uj(kFyqQB;%Y47YAxbE0WQ>dZjN8Z5axaq(Z zgeYHg{5Aj=s{PJ3rS~9ko)G-ZxVTHL;qolvsx9IU0#|7vetG$!(>oY`jrI8s;6l}B zGj5kf+!5g1A>wD|cgiBJ#}sS)Mq9+q04^{XL#yU5=J?I{nYD12S;TFzhKFmvp(caAyEl8KF`eEMIf{j!d`4 zugjIza1$-!Rs!b?MlVqR5bb8=c85jWhA=pDecl3GL5Oh8`En`@t`C5$S4z#85zJfK zse0Afgew5fs1y%7a44oS5;JTY|RR&zS0rx2i$e7-P2HY|O?pYHqp&%IU zEe71pCR~95S8c#eG2ylwaGMOcL=&#TfZJxk{R0)zn2wCXVEi68;P#ksl?L2y1MYSc z?tlUJTLTV9@tcJkH!B$KO9mW{1~zp@Sx*Gg{b3;Rp;=veuQZL&}Rwhu{*`kU8arb4wP?S*Y9K_Em*8Br|`~ zkiv?J@{(CgDvB2eu|>tRmdu?AAM=ZYmWwM2XU|)*xNt7)z;Na@bBbsBiVKU1%Y}JJ zdBuEunyOSAvbdtWqHq@Ib@O%VlQtq=&3{<8g36(BeGya~Re~y_Sq`(`j|nrVP?rJgz zf`&c)%MbSC&6_=Q+=7ydlETuGpBEb}#}+RrE-$Po{#oAC{HX@}?84I7-X&$yW>WF| zh2_`HoV~E@I%QK>;lszrO6F8dT3EECbjf0AKW6sqnckn}&74wPv7~Iwf@@037cQ7z zyr5!cc4={8dDfCSbBfE2STjxw^Sz&nv-rZ#;7`Au9P6$2_NkhDG}mTZZ@X`H)qPnR zdwYAeJEMH3dme0xt3B;p;XADjO^rIXA}ad0Gv+qu?-PFKbN(~Ne@nr=!1nU4D0!t| zy)*XMigxcM{I2AdLfuvy{7PZM-sg^Mog8(O{S8{JKgW~pUmHKKe(cfcu>%UOE{Hnr z)F${f$LX)WJ^ixZ?)a)Oc6cXmwzu~;tNi1Bhtn8z9En?@MPa4*C(|PY@m5Q=yQ7LxK_#aj_n59y4 zDRg8GTD6ybRV?1cqPc^ne_6bvtfQSY?Ht;pKM^uP_;b+=Fy}zHS_);4>}a#cb^s{a z7HyA?h>pF8ZZ@|~>tOG6`diJOpJLBXwdbeV^M~2<)9v}g?fE0@`6KQ58TR~95&5Yp z_)EoK8vcgikNpwWWy&Rg;9)V8rb6dyQmF;eJ-V%MQqblmQ z$W;-y+j0L&DDV+{ksc&bvm^eT^VyNEzNBzJ>+n|Ff7tLge!uWCSvc|@F7x>;?&0=| z9Asnhi<`LY6Ycg$o6{a+kF|BQac&iZ`m&W2nfoH>P;|@tK~q3qp*`x?C!`pNIcCP7 z9-&4Ha~DZ*Wl4)cy~GtEL2;E(>&41xv)e^IMj4^lM4cqDqE-MT{75j5+eyahX@6u&vJP30B+en-b_0hi zlL4jTbQx?6)>;=th;dR%>AkQp;u7G{O@Rz5%< z^njgG%FT@13LL{wO5p~>!WiyHz^S>J%I8qweg@oF#SAnYzjV}*WVkaOtUB-(G95F3 zv%-(xkyHHGZ-nFbrbT{TP|%8BoPl3Y=uxlAK!h3%+%#nXRq17)Y|Ot6z!kub=|vO* z@uOb(fmS;K9OJH(aw9eJYXXk(B0u)~D!rJq4j&bqvbtNFvt|rWljzpxte@$T3CvmB zG3IB?OF4gSY5K`87tUNbYtE9zvoUunnmK1l+04bob2-uZ9&^)Nr=2W^Q@vF8D}xmV)+fdu)9q|Z;u+qUtQl-=-J^wWsb(r zzu`>=!Q8^nJYbCdDEs9l27f9aXTy$lQK=o!u%Dt|)=mDgzCzU0j339C3HVb=@w)^T zN>8`3F!Wa-gPZElRM@zVtho(1)s_+se&~$r-ObvW!g0)mQ$TGn8Vqi*XwGMh`R zK$5un$ieC(eUF}LSYSlN*){#Y%12aQk%uT63?<@6j4zl}a6IN<{5|KP-N8l7Lpc^2 z=b@ZOvc1J1V3srInmMGL&{$M6fMegH6#Jz)$^feB$5iN5-$3Ur_^ZYr{jydv9_*JU z;?Kwr*V?t)VW*VhcQGuKo^H>=5UO7yZ{kGWf_?x4>$XxVPD5c~xsp-I+_)fC2w(t2KRT(AX=Fsr$gF!Kef{Oj# zI=BZRy38v#0MYS(H<%YoJTdGSFNJv=^!G~hMKFI1{VGtpI@y`7XihwjdE3` zXg;hApfvx+V5a|@OlG6Zjqb)Vk7mYADVm2X11QaXO=d&%gu9`a9%rc^4+`2;&z_Cv z5-SXR488p%O5PxJ8@J#Z2@p0DAsH=MFn4-!`9h<7jh#P)akH0{7f+d8SXx*O>tIf2}Ym=a}7XFFU7FpnTarlEU($W;SyQOG*tqxDZG7p9wJ)u8`f9(dMMM6k?wsY_ zyBB3qZZ~E5hUG!o9mcUD+sTAWwLTcja{8xc9gWoD_I&#^kdct@MfUaC?zC6wBVtEy ziB}V2;~JM%<2YIA%^Pv>i3$E58bZ`;K5bLw)weyl|JXjeXU(PUZ2de9l^)NDVeY)9 z#1wl&Z+p}?c7J}aZXQolqMKvue!t5W7+V{MyKVQZ5u4{`AyX#4je+ix|ed-=xJY_x{9dTjv&|e3f@Y)9AR&My+69W3K{R_D@8N zt8#iJ=IXP6V@|vMWMw{5?wgi|5OO_Zq7T~r{j$dR(^Fvf#Cvb6r)-pR(P6&B(M^X2 zfWOXtlIyFI60c40)HY3W?R|23-~Gp4wRe-;C%HUh&Z~Q{ue(oz!KPOo;$z#_m|(j| z_$(`(o*3J>*zAJ)fMqm0b*l zs!nVg;58e!T?_n&IVRbzweVl{PnZmdz6pb-7{j|raTdC0F&yDXjK7eZasI#`A%{gL zC-xP7qRTDmnd2n~QOXWD2)jw)U-X6W-=Ag(Ee4Q6J~xOI{5UsYr<_I#zM?NhAQ?0x zKHqbG7FJH^2K%9y1P%mE0UZJwgYd@F9uo(y%~C))Ux-0EIj@O9e4imjJU<{sx{iVp z-vCNHGn8|@uB1qZn-uB3iWK>AH7WSqK#F|e8jTcBYzh4DrMZz5;Y4B*LOOyJ`7|1I zC<-MDGzHX4d&JvEiufq`B#dJ6Bj$T3Pcg?5g-nOm)dE0-UkObIU25=#=m|9kzalJY z-T_(wNBTuJ1m>PsL2u+23s1jROyH)pmm2iYYR|!ws5>-3DV$kWSr1&9AtFkfY4Ah; zdB_7b-=taTQ=wP9X+IUXQPfDK+y=vpY93J4z-@<#;i>eZm_<8aloT)nj>dU};>Y&X zj301^VMl(PDKUQJN4@d`t>%Lz?UYh(q(**az$L(r{8&8|Kg?yh#T!tq&1FZ8luLFC zYj%&G`GL7?3}gNyk)d(lKB%Ibtp}K+#`OVv#T^u9-AFZ83mqIyB}-pk$#8%@0&z1a1}w_kgGrPjTx=Bm`( zF0FgzFs!TGl>;?5{t5M;ESF=$L;DkLgmoTW?iq5q9w@w7uvbczCHsD*ryKj~{t9Gp zQ+HDl?AzG;ZOd|0rA{jBpC5k6=)4v{d?d=#98fj0S@nt&M#UaiRL4 zp=l{;XCuEGmYyP)!L6@rJ$h#p=nJ|r=HF>u`@@|9`2zVCR1WP}&;XsW*Jb`1ds~`0 z2nQ9{!+(G=SVa1InB%vubbi^=%rhX{C7u|rcYmp%pqL6YlRL65u)ZoqGvzl*5r4ii zfYQuKky11V2Q(tjTsVFXMw(hgE z5^QA^+Xm9i!Jjrwc6d2kU(fZAX7}B)6RVYWQR}f@Y4@k59IdBUt4?W(cW3#v#Qpw0 ziCGPmSy?BB^|7ySCsrS^Ubv+0_xDZJS0k~m$dlDMdFimV?e`~TP9N;5roahLA* z_q$a0_nK?GKT@OoGc&<Xa$l?zUrEsto&Kn4+tK8=9;y0w3HTQ$L-un1>g7TJ!) zw5RkLd}F{jYdltRSFk?VqqZO??dSNmWI5~F)oX6>jCyeJ;ks=9vBdX2W+>6(luR$y zg1u~eSfoW^o@D&b<(!;45g^+ox);nUFu9lWI?Va8ToG$2EE~jHsxv7DII%Xv{1M9m z0T%7N;}3U6CJVt@IV024p*h4EnRy-K!X1%e`k8J!(t{*?-!n3Lcn{mc2l(#@@97^n zyw@Ur*!2DJ`-S)KTHCYUa81s3!ZrCtpgi-#aguBCIiy$@T_f!ukmj9|{vMRFfp>*G%LLqdSkd5z;z=)D&>|1vvCGC6}UXuF=%uh zf**<~Fb9WLD4wP1p$wpkU#dY*=UU(xhEfV=mIFjO^mRJJRrwq$+*sh4Hl@Pxqx>Nm zAo629X1;{tw+y(ka8oKAzn2XBSQW$Z`^+N0bY!lIAL~;%elvix62EN*ejLxj@q5!E zzb?ou6+e!Lir*P$n}7?oCNj%qHUL)xJ}eJZi2y(9Rh~nu4MO2FETxnisj;4>z`%SX zzXbfL_+c$J@@&pFjT#}3<6Dr+aGw+^uon9^&LCGz9*3bp{FmML(kqiH`utlYn^~pHXY-%3DsAh(t2qfBjB3YT}+YwpEyUw z@k1$9A1;A~($kIObAJUgxT(HfZw8QO1IPNKlxnw$urTsF1%q-UR_VFcHsVBMCO|6X zMvAevOxY6`s?QmkmYS|wGX=A)$z+G6sK(#A9Oe-EFQ`D<@4}e>$mKBUDg#B-9a?HL zGke~kvLc7!Ie{PxT@FJt=M|K@PzC20x*0N2ef=TbIi~1J;#Fmm?%k!C{CMtf0RH?4 zgmRqsrB4!$aj%-pPngX2naoutbCJn>fyvA{nNkcdnD$U|p1Ja-Pjl(dY+v#0dE$IP zNyT+jD$0u&%&qVl1VQ@IfiX+X$I-my3+FdKkY)vwQ(R)cgmmWBq6x*<&BT#|d7ycP zCC2j!;SU6yakwogrl+TwIX-ZcaxQ#|vMp{I*}c`ibA0U*))hn?tJL20ZN#l1m$$B< zZ0t?GRaxnKwZu!iEr$tGrAe{7Zr<6^n_4xoF)D3cR^;AAK5c;Gpt?WgX}lr+!+Ndy z37=L2JEv`3hbk?RQU!apZKGDxl_v;tX@-0Wr|e+LjBK19S(P=lZh}9@4(XIV&WAnr zk#HHStyQN3BCBmRnN?cNZ9)b_|4|3WG#*ZcjAl_g*Wmh3dQ>_is%>7ahHf*DYV8*t z)M^HLuMoTWv`g3#A*hv`=-`aJWs}+WEeLUUy=ia80XnY>su6 z`JV9IbVAG8bdzIKb)lnXUt!cnM~!W^W8=OiZD(4Q?p~So{7t(Hzb=fbxxkw-`_(3G zYy8Fz1zl>Q3LG+~GA#eK<<(hHIGebB5##67`q$fQw2dC$Z6(WDVs2+QZDUoTy~Zha z?(H?5yf}Ly(mKii4diqGDtpy6+O@6m#`xt8(^H=~{@}%l-pIY+?qdmgyiQ7iR;!e~ zkXD^lCMU-f{y=!5e%pJR%ZAQ03TcsS(ddeV4s&Bn-^D@!S~20|+JUkoEPurh`vESD zu%#{BIrn4-$9|6c^4J;@6VpUe3~))L@N^z2CdC6uF`?%AhfGpPyXxyJZZM|NjKIj( zCKj0g-g{Y@3`cauGA~3IPm0Bg39e@2dd7S{wE%WJtH6l~3EY)-jzJHtHV=&YQzMnanPnsEfy3#XfKpnsY~)2`gvb+#RC+JWiZ`8Vfg33? zB+4xddSYA-zt7sFN~B2jJaHBb-j=}Jj3#NH4gXzwbmpv={v;(qHM7*$?UR={~Q&C~G1dHD4~xX90|P39>k^8k}M z$h+A*n){;qbh!0Xz1FAAA*RIKOZ}cx-ORb=#l_+}TAS>Po}SRr`^2iv-kip$VH+`j zeWFAg(5}wDKHj@(RW9r{!R|KL1?RNh#$oZd*GGFBN;sqC?8sIfS+(0Y%9rI&blHwo z+O_px`>HT!c6yr%Y#Y1w$l=bgy8=PcbW_F#77;ylhwGhJi+6=}hf znxpEcdHZ12NiLIIJ25+?Z~a{6`Sr0ikp)`Kb0r?1njh{i)a2|?tC{3_&Zh-k3MTlM zrtl8^IRBf4V|dt0gC z8=ML~`$eU;K*RY9{i?o~WBNpC2O`u&F!+-)fGU0$8}xMMd%^vwkxJoIUydXTH4!-W zFG{I64TXilTHA(*>0PUiRQlc~+;-qNt|+B=un>%6!;8RWz>eV|y8~kbr%!My0}<*3 z457v@@-_0yLxhrHM}8{*SZqVnAea`TjQ-P_Y$`QyV6b)BRE?eq|536j9JA;J6!gg={Bx$A$ry` zZwI0mU7j4ciD6i4^V78W&qZ{Co>jQT!$7b*0!#Wj+Ks^qi%`3HKIyAHUj@lPfO=0&N`e4-z}Vf=lFwVrx;%b zlA@rPCXPd1X|K-3vr|J?sCSm67Ssx0gdd4LoAqU_^vk-$ZjNKoVrd5=)JhcTd}RPt zCCs+1^mN7{t&n4pd3}kBt(DV*RB9|TuP^U_gBpJbReI)`G2Ck47;mMNTNW%t8<7rM zfn&b}(rhd;uP+Y*&_ntmQT)s}o*~Ezfitf!Q&2b@qZqErXPV9YGJx~IUMUr>ncq_2 z)EL;(`f{s9e)R@^Ev+w|D1cC7H0J@vd@cgc4Lhcn-2=;w>7`z!30iF>9O$N$aw9eJ zs{)ASOMcDQmuZ2QGpwvHGt{+y3wzNGdSn7)e&{;_>aDnz?zHOf0AMisPIvk_-wP^7 zv$vG>91Xg1ZP_12m5*v4nr4W{#5gRsMmVO9Dax6WDPC2}D=)bQ`wQb1lr7IsjPx}ktz_L_I;fBM4dWUoL1ksW{x19nSya6Oy&zrX3k-hV)%yWiug3&mHv_LRa?6mVRc74w{Wo! zPioG`pkchg&TD1*(4y{T$c^xsdF91rh2_OFr<^eewXppyZtoWt1uy@f-OY=TF*zfA zb4;@rmbb+qsD{W z`km0n)x~Ujr>RF}6o0D^z|D4|Ec1zzm6Ib*lx074Qk(2JIL6;3?x^SZ=cTUtaD`Xj zfsd$;sTtIVGR#*>rr}mdPHw7{Q?AUk9UmVUac7`iRaPp($-tiRvuh*Q#rq;R zopw6bJ$Zck#eM6Z)24CnzKE+?-0DbQm9sVL=XL+;@rYC34YyZEVE5YQvmLuDDyqP~ zQMV;(Ze32}hn=zdEnlA#Q~xCPoIMTyQ<>?rufyS!hWg5wleb=tRknC3AgA=YtgUO` zLK@W>0A~)|Y*>FIkKV;y_~=J$>$Gb7rsJg-dV~A$wf;G?R^?P@MIMYf*(Faq?shy= zzjN&aYmcverpc4{z_Ei74;=f0-P67A@>$Er_u9HVzx!X8C*IW5v(`!OwG7*KU=~V4 zb0nfX#Cd~NIjJ%PN@pF+yR20?cjJ^mj6bp4WnR7s@H%Zh@6B{5#VOGC3wn7avS@T#0BN_fTW=$5Q2>08{%$?;z#!`J=yNffs-POr+@)#TCe zeyVL(Q;r+&r`nv^@!6x8KM~`4Aq5fLeD5HKVwP%4FZ6!iGwWz==g)Z)rzob(j#CF0 zcp-UCVoV)1t8#dbAw#^Q$};Lv=h*zY>jH1D#Az-fXxF)p=MnlOYT_MM#CB7RELHG? zT>9E_=D6dao*S=w$KyQ0r22@O|87c%3(A|{XiCr`q{KM_;r@4%GcG7|exu2$Mb_*@ z4QpRF`9yS?US}P9v;EKE{RNv{>l0lcxlwcTq(TD_w-$c!F~fWG7*aT3+Tne@nbbO!?JdH&2_+oyZj)A-HAa6qqP@8L!WR%&#&_e) zL)_EMg@q?}PMPGtD`|QH_*QI7SlKW=eHUU9@9nWyoqdVpW)2i3HR60k$2_}c@jw0K zi8B>WHEk1dU z;Fw4=CW%R;7|6~e1(>o3Ubf@(hJJI_4TqtqG%WuV&>KLx_i;BV>diZ(DEGfh`%|PS{{mz!--zH`Zzw9; zF3=Rv-LywN+E0r5_X#OvSxuy8^HV9;NI3~rp0632Q>^(b&3 z86vFWbQ#=?{Hjs687HNb-U|yOj&}+&70BS01-)@Cco?|duw!`atH=*lXUMmz;mL|z zZ3l1+Ln##}_EW}i8(?5K443xd!fk@%Shy<{j-Lm0EEyp3Q{@&a9X{Z!@Y`wN*OFZA zFmTgUej_m{h>A|YEFi%tnq1~+MDqXgH*6=dFr-rDbP3E# zPp5G(gz8IEC5~-@is$ZFu1c|OP$lBe$dB?ZKaHBQ4>@pCchzr#h zpiT1gCIQvz{`LqZ8gG4nyHt;KK-T?ZdfRcE${0Z%+WpPUVnh$vQ2u>8Ou?+ylur8K6qBPc+sQmMQyWrRW|EOU}pjjp;LGD9xlLXZ4Jr-j6_d zLKc&X7mF{-1oyw2cQeEQI;Ui58wl|=oc+)4;+=Uk!WnUJ*%P}@R^Axmh9AHKv|{R(fyCcJi+vMDRJu0wsF=YX$0zd&;z`&g|BQ@x*yHx;79x>Bz# zT82m`hlvoXeV4#ml;lN1IlwS<9l$Tm196?UDFL-q)NhNP9C zLos1k3CjDRzo$LsD%_h8XQepbh8;UFG3{*L9O)8PEr5&gBN3ciFEyY=p1?c@f5FVs z&w$s$j((Y6?7EmQSK-gduM`X(hMiK1-=(lndb*th=KU4O;AWm%UjST=!J~>(roj){ zR3Z|LlTu2r#usJ35;*oJN-5UnIc^Pb?2{NC>jn9-Ui8EtoC4#!6hG=!9H7;v!GUf{DK}E%9C8Lg%zyGj)d}z$nwFk=HfMiFq^8R4pw`E$YIeMc zzK~B~#@>f9|B>Gn9H}adh`K}Lnf;(@-f*n!@AQIyRVL~@7R^{rqbziO)ayz&V~MZJ zI;4BDa+c-+Cif90_v%1}(D|*CW)^N>8 z3npHyUH)V+vt9AKfJ(8tY&Dseo6H3!bBe)CeqSqQpfrDMFq8iuP3D(O<|j<%2TbNQ zCUbDkqR%UeP41Z{Gdp#qT9}u#^k$aTv*F+IqNKIWCxwz*G-@8jkFQB9F_9`OUpN~x zA)^&_no=?suP@_i>6!V(MN4L@7p4~$T_PE^<}F*_{W`lH zElcw`9)c9}z2=c=)7`K@^4nml7=EX#`E630*Ln4ACC-F|luD<#TROQ5rSkTk*h%3F zRU3A8@}6_&&*ybm|J*9>hG8!(;?6AF-VXOZ#l5iD4P#>KzA1UHsYmUs5W8TWhQBP2 zs@8WAVynL{iNfBOV;yIjwv*iN%H@8D*zc;s{zm-vb{n)lw(4FRb=VKP8ZGgip6@t2uJ63=rcx((W7ayC{HtG=lMd@h`3SW3w}0yLony4BeV9) z_S$3ET9>rz8*d_$EJ*ITeY*K-A1iCs^$%u|4dJMovHyeO+K2_4)1X% zzT7mZdS7EVc{do}Eo{X1LmGP(s#v|yl#ZNB7O#Cr)jV?CW~Xod&8q8E6TPwHCR>ia z3y8Wgi+7Hzu=jQqUWDrSf%g4m6@zNn4CTf|YgMI0-4?P7tj`Sj94*~D?j^Oh{<$z6qvi`c8fzB7hP zce`%ceg}5rzA3}-+)lo3mz9h4Tzoz7CA8tLsS~DmuCoQ~)Vc{@m#h!0A^o2$n$Xxj z`~H*Hmt*&B@#cgT4bz9kd!OR|G4}7y5xaOje8HW#2juJHKM|`g=5CHZhH2buJYlWp z-wSEXzp}Bygf*vb;`kZZ$J2N7^xw`)?b>(vPhRjQh}h;^Du2~LjcJsaW?*73)_$1S zbB@mmHs#M;>xs1=Ce|F&X({9n*gHv}8DP%oh!=Z(z$Ma*J(eU=fX*Yu1K#IMZsid&Kf)o>|>C!xt6p1R3W~S>$xtI7>M8{s?_7YJpEI&Ka-;oq+F|Hr& zNH4Nbv%@_b^sM$SUvvDh;r+=%`cRH-mc9?8T2EhFhWECG{A`=>^n3h!E#xQKK^x?! z9^S7kq^~W*d(hT;`Jr96S^D0!P+wXI@87kz&VF(z8aw;P6wo!G+*{v5ihlMTQuMp; zk#^C)$3Pj|37SFe7yw9PN#QSx6#XydS25_9D@onB7cc3flI|x(|IKrwG3bA}uf{hF zz9mJb$Jp@)!HgSpD1=4*K~q2n(jNUe zZ3V$J7x>fMf?5GLL@%Jyp<5j=$*~^hU*Hef8c;7mR}BmL#gHLnXvmr~&I>RvDTh=F zMJ?1E{3<;y)*xZXx`0w{$R>dk>4kn5a4#Xhlv1oOgN5=#x24D{11zBTnsCd2E2amj z6pt*JMP5q#kAO>nBg12!lQ;7`6@SVPwAv}O3si}KQf_7(_q!Q}QVKU17RGRA0LO3` zF73mGTLj!#xGNQo-wxnV#RWfT!}2?1kzWtgLB)^#X1Ms}0B0qBcNqAwK854A%Oby1 z27YMLVfiH?@>b$k3Y$v%fAYX{9ZKh z!;lb`-$xet4Pw6wKCI7dCn|pCy@9E~O@q5qsy<`5Y}P(@0LO8L{Ma`te$*>J&}um- zd^F*JQf{Qi_Lc{n2X^G=#-HMcy@BDWft_p%?}DU^u>3uTEey=CHxT;X7H?y%WR4F(6)n!;1xqtz(X#&XC~IpvG^z=w|fl!A;>a58(%decxZ!*%k*^ z;JId)i!;i8fac7xcYtc(K&x>gigJ zUz;mV>wMqdJn@C*?pV`C+9QDhAG}f;-~i6u$=TH%oCn%^3JyJci{a!y`7BHs%AWHC z)jrW=Lw+~r7T7DL+UF&(PhgPh1t*3i#f!W90< z_aJXp87QLe&~9pGW{nCeD|?V!qXb!4yJOZJL1381n4pKp@k>{_c>oMX_Yulj;-6HN zMVg0Jr{}oI{acg!X_I?gpcr&b zyfmxyC79e@Cing(_wx+y6H!Tl5Gv|As%aoDO{HDqL zn88f{x0=ig4QBc;FqtQs%omu5yq2Tz z)N98S&CFX^vY=whl35kyg|jR8erxlQS~znrv9P>k@xleU3+EdE`gUOpH{{NKKk+*p zKfA2BykyRGfl0&_IK(#e#^Zb^t)~`uatP; zo-((fTT9;hu|#n{jH|tosRVho8D@2@3gP8RpW~8=0|yx>FZyvTjn zJL{P4XGMDd*et!b)NvoHYhc%~lS}1Z@ax4?xS>!yb3X}nw7&+FiO#^R)Ao>xnXs%K35L6>thMw`$$YBqNhFKO(TJe@w5R_9dV zC1ma>@{VD=w|(GtV8Y%!Z9JgP5WKr1^Qjh zy}xT56))=C-dLGm-+s)!M&TQ8{FR{wpe`G7xom7Z?3p9|0UwO_w;%thDH6H;?Z+JY zLhen*7DP~p+wy<GAG zVvn>d5p&$i3e0lfM74kiNDI?@kNpLpy1+^!>#``r0PE82t@( z3+XfO6@It!)5H6dh4i%$UKZ++m9qi(E}{=ALgNLP(StXmOEO{&$bNjV+;A&LU?E0-meUwyg+-${JjnGQ*ZCTve4e!GQ7PuUO_qB!g-j?D0%R>EZ%kchUp?^H%SrhK~jW!h!jEv-iafh zB+#MQSmIf?6wo2GhrHk_((^TKfu!3>k*?jONY{&`NSAnb2Jwx<+K%z*t~2H&Yk0o_1%g!?!t@K2Hgzn>K8iNih&?Yoe|K7o{cKv_;a z%f@ozy}6h^$am0Qi2q?p|0?MhpmV^l3uH6BAZJJdrFjr(dku>Vo`W+eSaJId(GUls z;2iAQ3AdAEWRV-PBT!X}lS^LutJU_rl$_+xrdTxXo0<5|Kg#RTq3%lfbM&}yTRH)sw4rQDEI zfpbWgS-=g!pHeDLm%&2$p<6XFOyscyD!tc)+W_445<{YRWI>PO45%*1_%b*$JeCpp zIq{c@KjjBnZ6yi@)heKrn;EwiIEJB=!l5cP3-=@77!Jc_e8PqM8E|9au2eXF>8LPh zo`N5|gylB_I4k_N8ThddhKt{u7Ws7n6BR$!r*Qm617{_ED-Hb6t%T*b!y>;E27c(S z!t(2ZhG->zMZl@_q8ks(?+%On4jK5NTMo*1MrBt~3x68nf z?Ic|J9s$lu{v|<%rQ$~!cQ}3%fwRJIgMpvB1%5AD2r+ zSxN6U1HU0H@O#rDzb=p=s`#a}z;85gR^qqPz%Q)@emgAkJ7M6L-U7cK=*+CduLwAm z-VrVEyTc;CLk4~sE$};KkzWobAS!;G%ZIDarNCK9?=Azs(Jk;h0-TlloPArXC;0W27Wm$@Y`aM-$w?1%b= z3@GJBYMjR&0gjO%zlr!${D$JQ9%uFbpgJCI;kzDuM+7SHcFd3I{lTA#sHq=^c=tz{ znByF?RbCq3A7tAN@%~_lQ)O*&a+_t_aQyJKm0DyU%~h#I_0hUlYHo+tvrEZxMQ!P^nazT>`Vx(}~|B<~&C!<(3Ky z>e()+ieO-tDaCd|m54v(hvuy?C^wpw9@E2SxNSyH1~*z8`vu}c^$Td9BSyJ{s@1m$ z)6y+}*Of9Bs6hMt-~6uYts*Mw$06Q9Qzo`YqvG3x3t$n<+T*7uN%JkBJa5Z6k5ZWG zit`XgbI`ATzE&OrwRWC08xO`9PK~yDUi1t=n7-jGKA2bbbgX=1uQKq)9>0O=6mRVD zl?TW1vHLm+h270@Tvy>gYnSQ*D;ddoYKB0Md9_(?~8kcU@ zJyqF_^&cr%!}D8Z%UwKIrS<0tG`<{IwnxuV9CC_?vupZ)mC2}EB9BpY4%*>Ij7QN@ zhUG-x#EHwl>3imEkNgHH=c;@^&m(C*DdI3kQV>gO22gr)(c$Dv9!jbDG!+)AFQMBO z{8i(Re$_b6@tR|>k>4ONSOq(!6u*mMq4acn28R9$WN=gS0wh_eBf#Av^&~1zL!meF zD}saSyNFYIh|HVee854J6Htl=2N~l$18;By=0V72!4KK5QGSW^atb2UR^X;91E}Ih zYUFpyz)$5L`3+4QaaM2M4NFrKm)7r_@EhAufqt-w?$&>x{J;CUS`vtcf%p6nM{*ghA(;JIkfL^ zW5CFy4Xz9DE!xSEd@D>_$Fu*M-FM4QoS}6@t$z;hYT<1zM~%1EX|G;Vn!HARJtm_1 ztCGD>Mjv;!=SZThvu(i3OYyHX4cfV{(G{=GiLb)9aw6CLscE8H+h`N7QrV8hL`I%G zI2B{d)zi}P=GN7DW6r}1T6E76V^*vyZ%nVc_)X+XeL`L5fWC8Gm(Aw{OzrE^#5-FN zo9H|8G37)5)_COcM7(gD<4LOjbWLVMWoG7yVd6!n7jpQ9*4U%%$MOxWWN||Kt69;3 zv+xuAF)6Va0sn=!mLmBTpIQ11gB*;3$Rm5y7UU7$Q@hl=MZSv^EzU5f7``@Z7wJKK z_Oh~}bFpa-54<=3&*Q=#aV8iJxcwh-xxN-XLzDmp|p z;+rH8b%;$1h!h042Pr&bg&@p*NZ|=f`XA)%YZk*1U59FYq)H#q9KzW<{hK1$9pl0s zedS=v{IFw?=}3yfh3Vv(*S@51&jz&;Uf>%h|FDG*ux-QB&-!h)5FW~_4brEFhqFy# zGgPIoh48%A^7B%gou7r#k5@e1LXd$nY$43=IY)$)C-iq(Sa*gZW7&pMKsgoVJn=G8 zv>_iU1{%)ExG#M-X$vll|KZdVp7h7(9yf!=B|}u+}OOA(0pK z1f}#|=#4mj=eDmv=s(IW3r1r$a-W}N%jN|@4!%#}$ z2E)P_ZW(Z>CL&zgGaWRW`7H&GX;Ug3zgpmu0b)8-xrO5Q32_@iXWRzIDQ$x8Rv-M(!0{Y56v{dk7FdNW*LZ3JAex% zpW(dHSiX_S{A$>-Jdou9e$=ZtK&$b4KeSUyxse+AZ2^wsGx?FK^kV%pe0WeSdy~r1=YrmXsE2NoV!pm^kf~XYWcn^9_w!Eup7)e}nI7@ZAg+Fx3AGGTTe^ zq>5ivUbItsI`HgTe}T|{l$+`+*(RuXK8NM26x#?@BL0*gnzz89+-O$%c<7C|tww{v zjn>9Kfw)k8!qBvlDf-(MdIN2(ZKj{a_m-z&&Hxo?oBbK{AGvH|akKn%i1HGt(329> zLT5!bF&+GZEcLfAcpgz#dav4Bnw4xK(PZWueMbCwCU>4=G`bHpxQ~$GGfc`ZzEn_9 z)}`Gh^D>iproqfHEYD=-TvRE#8|NQls;C@6X*S3%rd(T6G21t0K~YKJf(5}x+pUYW z&lG$}?&9qQ$S3e3{mdzg$|o%;t(cgWZ;*lqpFs+Ar#Z#5@r8S_H>SSDMek#Z(uNOD z9rd03;^l_cx%0%2(s3Wfvk(iV7==Lxiq-H~LaB{Qh!!U6S(PT9+I0ljx&P zN+cjZiT-0#P9<)~$KY0c%bbF#t#H1ZlY0)u=c_b#NTo>>gwL(q=;gIMvy2|G^F|XykmqG?E zmU%b38!6VhVgniWZkoX)krZYzCIiRmiVXuIW~Y%IZT8p>SV=|OqV3TU(Xs5qY&N$| z>tOG6`diJOpJLBXwdbeV^M~2<)9v}g?fE0@`6KQ58TR~95&5Yp_)EoK8vcgikLy;Z z17FuW8##_Hba>6)F(#bg2>B%VBHc(zP;LYR*NtZ>H`2p<`}>9GMYtB^R8p?u5ZB_q zY#~T4ELuxrmbEY`i__D1dH5_1goirQW_b$1QLAOxmf`*F2M%v@3k9gkuPxK}haW6F zUDmk5LU`y?+MvGZ;obHFhxhgO3-8}0*Nj8E=J%f2r%;ZWPYO9D=b*H&0v!s_8qgF_ zA=ktJu!Z)RygopC(1$=Nx7|v3?RP;rJVB+DCL}oX%GAdq`)_kB7Dk2 zDd&vD;6&P$6z(~skZp+jNuZQH(tZIc2CfQH;KltU@Oh7B&^{RNdV%syZBqTd4f<_p z*$;`~2z|R)+oAoyN)CY3w60bFB6vt>I_PSHH$+3IQ1Vl*L+O`wn&Go77UQoOKScBz z#RP6jJIA1hR(lkl`cos7!kOi#{1#n?NW2bI+RI>6e(2(K1lPMXtF^BedLu3txbp~* zO1WjhY?Mo-1Gf}*3=i2Y_@NljkYnxu&bWS2{8E8cdT2Gu{}_f+%55+#jN!&2Fowf$ zY0q?o3bzYzW8tP$IDRvLO9qJiI8O@4k8(mQ{N6P1Q}rNJ{7wKjUPTTxT>L!ntm4P| z6fS-~;Jg<2?KJS?JTM$TerMcDdfg}l6+blpu>5j?v%-(xEm!=|-Gt@0+af>CV->%I z7WgFtXC;1R27a6;hs(bji~Q;h{Mb&y@pGbYv=YBO;8c2hwZLzwMSisger^LlvwZv$ z;HJS{DOI1@MWd(!%7aGM02A9A`(~A1>Xjd8wG{OI=n?`-xse+AWdP@f9r-2UPw|5c zE?qukErf8b$>7p5l*q1i`S`(T1Z0rGbz#hZHO}IX3F5wB%T<`%#JH4D5e|Y-m|izne!E;X#W2)v-I?g|22tO^RPq7 z%ZO+TY1yd>l#@|H2I*KkNXObayw5a^u5`I4A3ZF-)V8eDc5>&K>B9@wj5~^oaqO^$ zw*oUDQ_0Qjat{tnA& z$_tz~N8jSOHL5D|wusy9YXWHSVS4RI2j_r+vq?x#Uz*{bN$zJ8o{$%OkMJmv`|fA0 z!=9sYgDua$l#(K`n?Q$RF0d6e1#}zjQOHly9)-S}_Mk6H`-7w?_m4B^2q5cYFa5Jy{_6CisFp5-yOhNS^I4Vj$tUJ!W|3?W4NCI$8Z>~ z%I8qwo&au)Vg?$H-)J<_WXX^HQMhyz0cV9D*Sd-y+r8pvo+}>$&dOYQ5Hhz~#t%sf z@S|R(30mz%;8dB?tlUVA`Bw`Z>m~D#{jG{0=E|eg=@3qqTbnDV4$rWB$0%8kSYW@p z17kNNGk?;M!itLWl37bCiWh4`{&&6+bE(QGF6;&gcV~c?Zbr#Af7!l;UC_MpV!U@> ztZ%+HpUnN|Y}=kyyukeB zmef`2e$zl4wMOHQ(?)f_?c)&GfdVT~aoV5z#`hJ?wGVD`cGVIqwZuf;`E;Gb`0YUIXQ*1w?u>`4x6t>-Y)*5-hS>CPy5#bPD6zO9nuOmZ z5$7a{r49U{l0jvT#?OD~eNoOOFeHjGg53`Lx+|p}h)~PWAh~u`N@*{Fh0@dQAUetZ z3S@9gm3sD}R87#ZJu0Plcfqkx;ds}Q?OdsFxLn|@@T;(h+ZqO!h=>@|`zCNIPK=|{ zV`|n6M|rbRDITP7DpPL6g&O0ArezE}8@WtsYMSM-W`~~HfwAU)^FFIjWrU!PX5VU* zyAlBe@3T&ZN#!NaEwZlAd<*_4FA2KIwNkL}*Zcjk#S4ndalVCjiO}88DOqY59-2e) z$`@8FoV~C#r+D$~@{+QOh2?FqbjO{c8#0~VF5Y(cIyXfg?_%qTFIo)q4iINRY$t2; zv7#&-pN5;MPOQ~4xn8fzavZe#qdLcX_4Rhodd=-FC@6q$t-fGF<6x|GPnTWdPc6JD z0lG!EB`nAH1Nw~M*8?6b=wBGguMhah$>WXpM&Qm(*>Yr;I33|u4G;BDl0@e% z_+w+EUo|&me>YLufd~}~2J@5wRPnpmpr`Y-aOh8sR0^l&nkq^6!r>ML0#$Ju3cd0} zXTA%l`Vg9x9z#+y9M7*{S{hJ_2Q%3?cTE9~dCTyKCqK^pvBYfF@8kk79d=47exycz z+km5g@>BUoGy12IXLH|vRGR9|T9+H+f;3g2e+vD*#PZ_OR_DVN#Y-#nS#x;>jwBbC zYWT!rc}3wY(Cg;w)F*93n9Y7JXl8PV?^Fe?m>WUGz9|t#m5=I7HO-tVux~PSH2N2q zN()OC1BRxJN*l%nu2ik9bB7Hd znWjTqZ`&L6hz8nr52oTrz9-b585d9vt#324xgRi=1oIohIfG(9(EDFZ0Ytk+7>+*cVu zX%0k9nq@!teGXG+FI=#=!oY_Yx1~`XupYPI8bgQ5<@sfW|q_^7HgfBf7#FPVe@!%J%tBFrQKf`TL=K(JPm zNpch3LquiOmLw!N6A@yFid}XMiZv?L1hEY-TI^~UtL+c0?qXL9THD%gT@!V8?XK=- ze;>D1=&!$!LYi$|{eQpb-ZOJ^%}gc&-S+=G$(`ps=XuU^-k(-ZV+0xn= z*^Ggr!vkUljy8M`Z|#<{jT?_4~xdR(CPC&_y}*AL#vDNk3g@B(oOdn__kB9 zU}&=FHn3+>X1!ZJhdUq>B<A-g;OHL$8o^x>+gfhVrMIv{?Z zu@UiTK)9h>vsMhulV6RySMDU~g5&3YoJh7#Zyz(isl_INzSCXc5*UJ+|LjX)vj90@ z(0pZk!GKI^3ar_u(;W>7R=Kf5-A%>Kw#$JV&v#Ivb6uOBG6>-=mm-mws>Ks3d(^_Su;y9AznG97?|3oufqmI0_I{8q>X$K|FE+z_N{=6465)*@edgif z`SF8`rVr)CHSXx%mMwi_4)61S;P96Jfy4W=vkUJm$Eb1l?k+<4@tyV(3mO*WT$AqX zPkH8Y8zCk~_W|-9_D(>)!@h^^Xx{-e74mUBLB6?w^Rbu5Gao$1!*y`-aebY8d9|cN zIq=CguU38^Ih2;PY=MO>(YP`%~&l{#!I9;uc9Y1|l)+P~)uFVbwp zud>r&9z4yG6!S;Xocns*|9e~!!3y!xIQR92FrZdrYBDH0%hBdtdZACU0s2dFd#mWa76Ld@8-{^HqA;&!eih07$bPe5`-UsPf=Co4uaC z1-^rDWB#E^MCH-0{J<*O;E8U^C>o(%-gY1vaHG5|JSu*eFGk;*=R9z<`C?&F;i6>c zix^MQMCXemuLb?j?2GP@QByxD!_ML{N4G1IgkHH`sq&WVLuy`iJ?Px$RJ6kqM=u8 z?lWh=U1ZLd{IlSW9lsg$d!Y!h?Qi(omtSrd6UI~a#B|EWZr()h>}4{XOff;aWWr_Q zgo)e*oCwa~M7n44E?DgAO@KX^Nxu_$M=W@zO>7tGQrdVa88Xw!X~`UK$pmLQ`NwC% zWillM{pr)l=^qbilcz~(>F@=fY3Rpk{*?Czsc6{jl+K{;z0Pt2kR}_Ib*DlARoz`> zvy*%fgjuv$M)9dWi@Jp7RS?(?l%Z~+aq@A!ob5vy#TSHwl1%03BpJKx(X z0%U?wG(x-1CErLocm9Hcg0ZZFW1G%e2p@f|%!*r7_nBuxxbAJPYtz=c1utvYfAXYA zGOOd%nxAG}{0^B@>L*3quB;Mz%x?!r-Jr*8#)Vm59dMP;)PstQ?h5W6dB+s#6?i6t z-##W|za8^SI!sJYj<5jZAl5h+-AAG)y@Yegf+AdUf<>My<;^E6A`Pwet+$H`Sm4;W zDblbWt3_KQcolyUV=DHp#2s4Cc^|*Vphn>bRdarAI&G zujT5;qzk$J;qKGV^w(Au`Q#2>!Hbl|g@p`Ne^J3@zFoC zvD^v(sVDeOTCye#M(P=5ieYJ02%swGI@nb*Nj`+V2{&bw zyyb9EcG7+dWR_yG(YPK%J{5L95T;cbrBkRU$tUw2a0m$Nt}@EMb06U{5R?q^D*MH- zQ=T%V;A1+KQMB1`uxB^-^wju_@uWOL&YO@gEdbKgfo~*T#<`na-cj(;KR~oEAkOgZ ze8+9!G7nU^(2Zldd#P}7Vbc2uoYTQXb>si!8HOihRMd}Gz8k7AGv{I$*Z+3`Rb@#1 zw?*N|N3P$q4^@WxEl(kU#JMk|4Dpz(Vfv8k?_4)eu$ErAVZ(ZJE3&m|gS>xa=}j$L zTHDGtH(p)8N!|luQ?6VcZ)^gswh4>lP1a(&jX{bsBHLoC@aJIpd)^2AtM5MCZhXd= zVO(rXFbX-r+oS+TIjUKs$Cco>euV=nHRC4&;q00{X9}%-$-C}=Pv*_OcOiQ_TvQ+n; zG_<_JpFCrR#+ByRGr88>8LI8QHQRT|FW!7@$lw0jkm!63QeJ};5%53k+VfN6E@N_^ z=$^Q@bo!l@%fkM>S;w;Hi2&bBIIy@Rt37L3c*0)(-jnscQ(|IqkLdo^DR)|0{|t|q zac5-)xV^ou?$sx*os=>#X>rX^@bJWLE!N z+E(Oug?z^zz|#?Wu?PK*ZG^<_0wO5F1-axD;HZ3Yw1wfrR^!hC=b z?%abT{Ep@R4k6-r7?G#@aSOsZDZ{a{y{}{6xzXlR<_U1di~3uc1F#&#L%-~|s7Bd$ zuE1lLcNqj6f}1i*-W70AcG7rOf0kmh(I}gI$O>uF7ztZMlyyFw?efwQAyc)R{*--& zgOA^-;%fAHpq!M;TR?9HS^Z zY5bn@RUEWb3iblG!JLm5&*ge@~(AnO;$v4uNcm9IH;<21{ zDJ)L@{pS`_p+?*7AItpxXUx#3Ns-@Bj-qI@KZqf)DGhEqa{m5pSYz4#$@%-2Ejs%Y z&fg=ZSNY4nxYB{=I`Ek6VdL4@V3qozV#_TJo0`-GbR$jTqbKX|jzfcUl)5sqt*KFt zc*`0a<474kk{v0CVI1aVeQ}f(KUp*8#RB9@`Q>KjoUl5(?@ZwOL2UKFeai3g73&X+ zJ?1JxyIe&`vsMv&SVeHlRRsOiOiisL9IsuJ{5k?Ux3e5KWg-P~+{CtPKL^Z|>6mn~ z|J2dRQvc{_cmTPsz?#Q(1@47#jFhYigVAhyrVsX;tv1i9e$~Ov>{?CYA%Np}=vR#u z7$@htLKp&Ghr2RLo^xGcF@(=jOn{1y<5JpH*mbaQ-mZ+&b!>Y&h7*JU!rJ{1_gKf$|8Q>k99KVI&>vTvsSX1}k~?F%-kM zhr7wj`xf%Pe7ymH(b z!EL&ozPKr`C?k4S*?Tf1^p4iM$~%6V^4+`IJNobX z>|5i5FAZL}#+=KKHzop`akGiFKKPplS7x@}^_#mqkc3%hK=g^goGi{Xg`Bne%Nyki zDhe8FsD87|Wy6>Ghpc6N@zJzneS_HwlVx0v6k}_vA_iI52)NiWYv5q+BetZ{# z<2z+ko#I$u*-7L5!m|{UjYiqzlX(c(4uo}38I|3inEQdCbQO7(oda!qxGb-c^pZ1io?|=6( zFq=O5W7_|2mQhnbDW7C z-NjK}V|$_1FW$bQcLm;Ioyd8loGAwVGiJ=dp74b6x!3`oFrM?sV1PTu!9WoE&$*my z1}_AE(4UjT{qJdb^ObwoVKE zf7u-o`-nhkl+r!+!cHVDr{&ua8Gqa+`E3EF{a`8kdv~Vo-*MKT-)gEmE&uexu~$7{E}lFKUjnEM%hODE3{dC$frfa31 z9Z`cict!{v@7a;zG>UA_TJ z&NAFdMZVApw=mymGsk#7^Blec@=owiyyu3_T#i}Nt?>nlnf*H_CGuDg+%f%@Oq|1! zIMu@Co*ekja=e&uuFU&_7$4pjgs6x#`~(0urUQ4QP}9NZ^M7(~eZR^e3BB^Z=a`c{ z2U%VoxqhVblKnw7n2B>=kNSOP%(HxN$F9$*zhi!ft!aKzpRa7XX-n(v>o;s^xjpXq z*S0s}RLSx8@y}j0V<&zUX6tUu)7?#*0^uKFr=7PC?lV4Xcutn3lyvYO!dj!y;EjV^ zkKERAzj38eYj{tlY09mnLpwRno4@1sj>wLq9TS3wm85d>m334r3Ze& zqTqS&8TZxRQ$dZp&fdP218+!eZ{EGfJ!pO-qW=N205G4|1K68pJCO$UT;@HBRH`{N zM%fO~7|)lkmbw?=gb)Gl@v?n$J(Kfxu4mTKoys6db2jt+PK1Fhi0TaLTPR zk=2Ymii`c~AKPAUsf?5Q@ka06GF?m^sLIB^*Six83HN%hyrrS7wSGg}x!UYScz)5* z{#-xjy@5cx_*{<2Xcrk7oIfuKh^%&TshmY;O%vIe#b=A@;LM!Pxpd}q&eNA%nvLH; zaC*DQo-WU$&&bLKPxdtMXIuz=F+E#A^5iT?z)U+Ev+ImZN`}nf|3Bu{HONQm3D$c) z)E&-w^@ngP$D@oY|5b2McG9i@GLr64<14e;<6EQP+o^;BGF+M<9=p6>0Z}y4mEAda z;+ajmQ7EBZCy;L>oiHE6p%Kq@#2XJ4E=>9i<3UGTPiG28xC`Oa%#zRM=9ACcGYne& z(qT9?Va#xBlm}GhtC}lkM_D{_jzl`$)IJ2q!L=4{jdK!yE&l9BFSyaT{-qCucs-^EQ!lZ@xy4Q(&XL(UYO<%1Dla) zV3T=;&QkW5$WHcE{5i|<2)o00=hN_ps5Ku$_%brXi_wf*oZn`+#}a^ViU4o3@v5?K zfSYQ^Bp<@lj)#7kR<=>f;_DcqD%@>aq@*-4{r7)ggzS$r}-Vdn+Io9V$a zDo%@m+vR--MClE(D*J2)9}^|#|73zuGIC+Jj~BQv5r7-RW0_JOhk2X}AidG?N4)(8 z7KxG#tGEw>RGf$_8lgR0j(eD|443016)tpFNufD8lfR>nQ`9cT=;M@Z24)+ljJz+A z%zED0XezubETf@*ymI|RVdkhehEZ2d1*-B*F_t)+|+`5SL2;O8^fa3 z_UFyE53%= zE;Wp)V=`1@0+eY(GR~teiDl?0Huk3~YGkF}XrRS1svK&7o7KrAbOY4kpb-2?x78zH@GGm&(pHKs(qBo_V&v&z^eV)^#=Ko-WKKmI2@=ul~MBMFIZT(a4hZoPw+0bxhl~Tdc~Y! zIBQAFu$@!qs{FCH^JQ>%wsTzK6WJO*2hCiRJhvhu=AxxX*wPy##nDkj*}&U37r%I@ zN;`A3_U)oogR@;zr?GWU%T(is;E3ag=*R&TL8j;bp|;KS0%cTLI@|Va5Rz@%EPG|* zwe4=mQ|+0&%I<922f&w1+orBarftW)i){fu0X&AbU09U-*@A3SnMT(d{*>2askf2U zQdzQnm$UFJ!}V9rGnJwKjm=M}5A3?a#MRpCrmgF*sgJZ7TUuAQ@ZMN1QCMrPAjv69 z+1A@PZ-DmL+E%~e#`PP*H?F_omikt{6dH5cSRdJB8(QG|&`n#{H$lRNEv-%Kw}$JB z&Vl+F;<->SR#LsiVJt|?6QR|EKb{Od(;6B~*>FupC4@qw$Z#Jr}lJLJI)Tb>J+ z7?s#7o7AVtcbk678@O%&&oxIw=AEYt+OxKqz7;)Ar`cZ|X<}`)Hh1O_i^f^sC6M*94 zIF+gSB6D_x^%(nm_p~QI%h1@=aLWzrar)t=rkF6P8E)BHe*@ewXJ3Eo#-{b*rh2?o z`RT8#6*n^zqh^A*aTxA(;3*E==fG1Pc$xzr=fKk)_;@*Ak48tff*9tKyJU8pS~zAn zhU5KLu_VOaGobF)qBY*s<(iynoBmBYXTo+|Y91+%>sdUbK@(fsGI5SCO7STAmtZ%I zN&j;ol&t7GEvnhdg*^9>WuwRTK}`Q&2W^6l{O)R|2y!@ZS?GD2AT3N z1kQe4#jhmV$W8hZ3s>|C2fY$F+p?k`Rf@&RujehC^u-A4xP$((1OI`IpGoO)(0d*9 ze{<0P-9bO$pq~WJ`LBvE-yblInO>KLEBXWneWHV&<)BY<&}TX5vmNvz2YrEqez}8w zg@eArL0{>hU+bV>=b&$N&~LEOCs}o6E;48mwDd_Ur%XIm{BRgPPOz@hnDp_(`YE>7 z?UHK#a7=ZT4JV!JZORbOQwSh&KFZJ@t;(=VnmN$2cEq#)JwsKdGSWt(o;(i&+C-xT{) z!1^o0^$QD&Y_W;QwVP&=>0&id@3~gP3`S(geJZTIR%e|bokv9n(*ekAGmXSA@!+{8!q1n zX>VwOq8A?txj_}Ml||B;{S_GnEmgYF8J-eO&FHFgoop9xhWCa_j%6CXbuCqQhVKg% z9}~efSv!E04o+-+9VZ7mL%v>L7&qk#UmeD{bzIwTsXBaW;uS8q2jD*NON@^T27c*( zj^o=^gHtzfhJI~^J`fB|G2o|O;B47dYxq3|tn|A%CgwRaSD%uXY4~5{eFa?xM&kND z17mT0N_d%3KA?H;K3p+4d1l&4-HlTcUiU+XjAui>H!JY=18~>A(C)G~ChEJjK9Q?G zlx}F9k2P!iMAxf`S+!Qy@77$MuCC5z*OQDJA8!w1%T!bhE~u~gkH;e4`~9iGRprZj z^zM%DYTftx#BB13N8TNB9~PZj-@(X_GygV}^~N_MqC53uiZ(^wcF<7)e6OqfABV(o zk=s}0+SgIRwC41?bx5yw?d}NuM^8rIW07^ny*^5Ojq)D8pig`qHyh;sGyD}9OO3uN z_-eQ*1AZC~8J!_lk8dDYU1t2Y&($61M=o_f7GbO?!6Q<8Nqxy+8gRETzICy&?vlQ@ zhB6L+>!dg3QsX)!^`uuLZ+qaWlPTlgzpAcTJLyY(EOJNoQ>QdvYS#0i>^De%7vX;+ z;_7~9NF2VmqSFw$a||*2Z5bQJ1#XB->OgSmQsYQ8F7$aYqMb}lS$*QCTIuvTYfGo& zUWCaPnXu5pYcE<0*PHVzaH&hSYcIpP*eL5S)m&Y!Zr5Ifh}mcxN-}VCu3;_c77EBP_c0NbQk8b81Gu!8;aeDqWb11*?`A zb$wd*j^?G6<9d%bS0533-x|t3eqVSB&ex>N+;~0ne@7;C^Ja-D);B}`Wk>}2BCluC z|D72>1s2O^+{*9>+E<~-e>`$iIOUkg@fm4`2;jb`fh}|Y=J%%uryd)J97{jxnV_GT zpy!u*f3NFVrDFfOh_?UEjPB;@%Bq3w^1O}jSVP6ZN~BoM1@ZOJ;IS;vnYTjUESgk$ zN7fzFew--+OAIkHP>#Cqa_>XkcV&msg5_+{yvw272pJ;yekOAN7~6@P?L^$qb|SR! z{fE1Zw61?0@&{I*-hIv93>WNEMM~%L3UMl+wMTk~d1MDUD`}EYVP=AG4b4`xG zk<`6b(bDt++8vsT(~m?@fIG0;trVg4)rY8+nsWZZ9EKcbPF+uI(1|jW;$&jx_6CKMAv5u~vDyJiCuXN|%(*nen!(v%T39txFg5 zA|KM;G*AnlV$I8!<>ixkZrb&IJER-qEIJDihNWIZN!Y>KcXkUV|tHB9ZC_f zYj;c+?$YrVmb-0w?Kt`<9nas|iJ=oekY6LNP9=WrxK!w;^6B(f4L>f?9I0te&7b?` zU!Bs@Dfu5i(6wvft8{YePr73&jrfkC?d43%x^DX4 zh4lT`g^SS!KQ0h~FJ^epyk&fIQ9)^5)_YlvS)~KdmOjp%#uktHHRC+SkN5B3J|xt7 z?*X&!AFwoes%%MCj%&5kTdHWUVVUOAE&?H0zAaUS&7I-03>W(RmMV{>TRmMEk)h;e zc}d^ees{MBW*ODdmMHL!=Eeru4ja;OGm_aV&6&a%xbg?Xbv>G!uQwro7x2&#%n!}0 z_Qc_>LeAy69uUC8^&@2{C!i3(WaN;ak5dkuqOwMl(+=JOJf(P48ekPFU8K<@Bc~L6 zeC%>~+9caNb0UAu^CzGDHD84AmJGjAsRYwx2rxlPjZ4&^WQYHg4uS+Gca03FME;ug zYTDEAi9VcWjQ39gl5ezMdmzdK5>11JNsSPjeOLyNFJs6(8En?16UW5?a_tf?1xzNM zVZCRAvWHb3TosNpiNoE>BV&BH)7{=g6_d(`sQbgxL)U799N z=@TZz`^ZMXY!^D}om_JqXWrSM2Zi~K4baOeeJtTU<@!T~XMWS;zqJWd0+{?Km>E5EbRFHa`X9-QIX+WVN( zw|c_lc4ga?E&MjbC$jbJ@Ern^)o?uV@}_V@q>$| z597&mmcF}^D8F+Pp4q>DC5iTq@$orGpBdiQ{=nfquf;DwRbMdPKWFK?CyDYqH{qH6 zL$7=E@eAfH!_sH#|Hj-O9dVDIpU&_;U4LZOm)|E*er1mIolSU8B$2)Z;gwy60aJZb zeM3ZOMX;6^T~b&eJmt6~y=mLLl?xVJvU$t;#;q;FJ1J#ls%yM9Nt^7>&@!=GG~JDP zaJ-uj`#?%tiX{OJ)9PyTjCuj!cHn84FSiq3f_X9_cx$vmu9YF5Yz}oPuxF5h8wvE%#R~$ZwR9zt6%yA_V_r47ez-ldu%u zMh0a5JPOG8euwUe@6Q0IL+-CF`hZ2}nLoy_m=N(>Mu>RV5MpuWYC@#vi-aXuHz7p+ zK1zs#HGPC3q>m8%zp~u1*e&BX-3N&E#XQ1ddZDmR2Y7%i};r<{QHE6 zH_sw6oX-*>oofl<-e^I7lZ)}&Mu>9TMYtUC0%U&t8j$%hME5GBE6prFR4bt`GuH(5 z8N`4G%{5DXrsaGwStLXN`9zpw-u=xrw{+sOtTnBc$LiLhsPI8SAx|3?aTmYnHbn_rs&|ISi)y!O1 zvs|D8q`3#bGEXeL2e1$Al77qaz$(*l2cTUZ+hUs%0-Cb6+U&53JY*!YCu$U5E?j7r z`3=Z6)+RI8WL0ruK9Eo0$B~iQCX4)K{Aiqf?|^TvNs_Dj+&q|(?ZyoqT@T-jCTLK4rxCg+;a2PJzR=jW@2VWKF%EXiREAUBu z21d5Yc=D#Aq9r5mdhjWE5FJ^~@c=_kXxWE8inRxAE1^86_2;<3X179-feZeO0q6G5ZOEP|QQR!6tsHfw_ zZ!P$eiQfU6JPZNj%6lbAdFdEWs`z2(6jxp`_>zg=cALDS1o9qFQr@p@@;FwAmw!{y z7?X+L_25(KU6erH&Lrji%qFiSfxOe;OQt?whHI0QRy&Wl~~?%`z2fE^JTly z?hh#{RG+{a{aw3VEKu9KcCl~c{LkMNe1Xa+8AY#{It*tn#|+<7`v_=^#e7e#G0I}{ z-|E13Iq+8;_=gVs>1Y5R@qa-h$}sq@^UndBq}{|{g8eo;oV$?zG~ie8uekGtXm|99Xc3iH5SPq=eMWYHk`K|X>MtDgFb!&Z1>z1}A zdH0*`<(XAmHaA(`Digng4G|Sho0{61)|>BPM=R}myf6e}OY0WAxZM_M+G@#Tm>W0U zf(svFtedvfHJ2f>Or!&Pa*l|8n_%@8I`#2zGuBh8p*U|8myH{?g35(}< z)h|ENai9Nm%W6+=N915A<5=ZDae>y0)4zEC<+hgcfra&Mp69%0*@iV6lxyX{8Lg#C zbf;|?SO2Q@uFP#M#^7aT=1p01Zq#xs2SZ|4_^G=uYDf#ar|~TY_};+NnzwE34(UB2 z=c0yh-R(Z(UhBr${o)sS!`7S|^Nn5MZ#C#S-@1ET_?1)Z+}-k=y!6$|w=_P^6~U(( zo`k=t@E3$Xyd_XE(Kz}Q|MQI9Qod=^{P9eL@+B>QV(<4NCCwslk~}-Rd@!$or&wQX zD9d=^?urv>Vo{%-e@XArW}KnMTkp5E@$@X-gKxk)Jhj@H$+zO%bI*#wXA0r#=6f^6 zECcWIWcQix!7m;7uMPKQ^8KH^83=Qu$bqk`4~JaGUTpZ@-62Tln?IgD^L+MgEun#5 z)gvEwYSztS$lJl&nTs$y>R9lJ)0nu~g9H=A-l3RNeTs`b722K zN9uq6$aV&zT$`L=tvRBTllmWvI|1@R=?4kXuxAm%(;Py0noEd<%z1?9%s6l2;>`Ja zPajJOVm=f{0I&d%`ygDWuO>viS_qjKwH^#B`zH=K@GlpA*-tSKq=rS>Wga2TGLMi} z_VMPTFD;{+&0vwTEmqE@w%NQPO44k^uZ)X@Q@_@MNWZFor|$eB9=p7Bc*;^jKvUK= zHao2NVC=~2u2>$Deq=gfUje=sln~%5PGuG!fHXd2kjyI!SN1~SHt!-Gd;W4i%k9m!0DAU^lAPx6=)+q!~$z!qFEuKd6%s=;UX zr)Y$B_qE_Ffg9zi@?iYtFIZGm$bpPyMjOu*E=m3_74C<@MDGrm#F(G;-2vzRnt*hb zX)?M#;T?wKQ<%f>6yX|%vqWNsW1s&6G{$0%eVF&A@ra*THns=8bNs|G+$+BeME~@| zvBws`C3tpOINOji)Nv~m0?4t3)Kiul>8xAI5Rb)e#IcC&mhHsDjPe^BH?F_3rKF$$ z9}}~N8uklb622qMu>b}a9OkUwh-U+Y*#-}G(&pH}hrVKijgbdOad{ZuL_?1;z3z+e zG3@w?Hpkz4S40bo<}AJo+sNKjJM%ypd&b+^-YGP{xWHZ-cuVEr@}U1kc_U4V#`pVD zO2VS^)v$V_iDQow+PuE>$hh#m%{k$A*-ML=rqt4_*-tkuVoy!!ogsJ6-HQt4O*K>c z%pQ8h;LnO4U=Q8e#rIY=n*Fo7t>(720B)=Koa43{vt}&6)`aT!L7S3d_v@3d9K^b0 z$%m>h>k|4#see(SWj})->J};*bi=Y^W?kn24Oth__nxmll;iF+1jaS6`3SreumG@` z?g+n=5aEBHFdaWI>V5=%cTx7ObVS;qx2*)xGP?N^Sfn3|m3`$-n>W?&TH!`LtjtkZ z{2A0e%F&S1cX^6(`lF zDxBX%kmYCbnri)%dz5d*;adrRDh?F!9{7|D;>!Mc*zJ7pgOBB@jG|E&+WWQ-!B+}5 z#+UAt$9$ZF2c#ANX)Xi7R;{C9IoD$LfUf{PD397*$#eG6uYkaC$j3a5$M-WEpM7jV z*(y!2inqW=8OkUcp*_8CgNfzAa8Z?`;hJ-|mGv8vT$?CdP?+?0Dk_kXFwwsJkL6xw zdtb;>xK2h>{V<1PhJAA-P?fLhUglU^G5If#dNJ`>o$<)AApO%1`{q2r*?2N6oc-$+ zcsR!(oxFc$!>uk3g|yzfVli53><%~Zo{gA`oGi!Cb9ecw_~^N`M^YbM8`dB8J)(W} zl{24h!|es(qgCmd?lS`O%*Qm>;eO0e-wBVa+aE3)ST=L+v~Ee=Q(ydI%X8zym4klo zrpUZV@w7v9A9$=HXtYR5#o#*cuOi=$Qna}$@lPr=SyqPwDT0EgiqezGYbUb3yC;mcYgBTI(S zjZ?3)pJ=mrQ}wd}ZZb@Zb_nn|9){06VffSo?7C%~0BOPyP;Xl0uaf7~!#@EbR`+A= zq6)s~2T7Br9|-#_WmKFN!$HX=jrXF-Jh2#+eYS%y3_ff#Mvan@3m3bd<2No!;RY~l zPDMS8^hWjiD_~$AD5K=DT$G)(>F}h|L|oAb?cwHuF90`&i)t3tub3+pkL6BTd;v4* zZ|w3+A52ugPG;=nT&Z3jie=fqDgwh$Zh$fyQjt#?oqH7qQDz*;8J@T6hD*BuY z#nz0?xzY2AD8sYf>9pL)PhG7H@sL6QsoNPZWr$PnD?{9hj&vd(Q|9KyOP|p3rt@$` zZ@M}A2h&yc0nuK;bROxprSg?!<<9U&uZ*mU%7bf{+3?3ddcD? zi`N&fU)j_a-qNV9c|up0Ad16+c8Vw*Lo8NpvEm=|v!3DF=7_`d;}g_jQE}!%Vs2-| zZD}8yM_Y>Hc#Nep&gUN*$2N^c6@7YAhOG*}IHx;B_FPOC2_5Sq7YL%24lr$>veXbIu7{F{l`6%%b{wC88UA zc3llr8Yds;aLMrDvaY1~vJpTs@~Y$T%|k3z+8NjdhUk?N`ech$}*a~GZhJoL+lb%Cml^LV?w7l3nKu8hjR zLO3WpY5#<07A=-hv>1dsvz(~Z|qe*UE2{-&mz zHf(BDm#0R@-XqT?#xNOC(~dZ5hTr|Uq=Y{UitwAP(wX?uX_~)Y7 zu%i#r)i7CoWqrUxgzTR&225vY7~{!dBRW$#EX4X3hM}^Pmg{0*;_#K8vI)U_mg{4g zkb(v*H0n29cVkZ|O;6V*Xl#4)p>VlYQUEv?kb5m$o8?}Md0xTN*=Sx;CnMgn&7zZ+ zElws5yh)f_!DH9!Y+vm*f2#d#hMT>gcow+YXJK3!KB6l&;<3wn1p>YcH)WJOt_>(V zX9ZY#Y zuy80u>Gur>eMK}5CcOuh(=;aDYvIcOI}W;a9tB=Z{tsA@U=;sJ2hKU4X-xi84*D4f z{#ytBk;DJT4m!^u+2yBNIOEf9r8OT6To?WPFg!)R^G?4e-6vFDns};s1bN5oqdUha ze-8L2o-e_T_%*Pvgv^~5y%6wSQ^fA>3A~g3Qtx1v_xNB(8t!Wz=iMXnFX{=0^{=`1dgV>m9G@G#{N>%> ze)u(bdo4~EyBbW|p3tP8m4hYn=Jb0qSK=hH?^qBqc+tGIf3QP@1|KcEvCsFU*5x_i zIpx#6xb6G3p}=9WJ7wQnLxFa!V!7cD9G54gAILmDcp4|9vwCqCwiOqDkiHliAHByr zc*@9-cMw}KX?zr?v9DTt5ND^nXZ%-tPwh-e?PFX?e<1T9zGC1V*m?D0gD0QUL>}(m zt~rsKs`q@R+aJ{G+z83nJ@we~fsT3+^c|@lc->Dqo_#wP-I}$gnQ281>9=Mr%33;b zZ4J*}-y=^^>tcz#IXKmEbFg^_H|8?C?~3TnJDT5bMofIVVuA?g4FWuA${m>Rl~MciF)AWsbWuclKXf{4Bo8 zoX)$w>+rP(;X)bwI-2{LM)8ZWy41gV0_xJ;hee*d>u_YZF#~k~w`JsS?s+NGKj+3b zkDv1E-cvsJ6l0BfWBA7%G8b3(Yw})e-1P48oY{UAPpv()komi;x8O#90d0H`hx#wD zH1O?+&&ztl+*`?e@IPMI`)ou64%feO%I_|j=FeaBrbxxN9`?0_y{EFZ$y(Y;w@dHB zE#42Axz^u|P~}$?7@8?#3PO`#Be)S^TqjOyeiiZ;GS^kQWr!2HxTT-x z)(iR`Gk*9>-psD!y9n-+V(JT_DQ_H(TsjSDO`l>QWUWrt>t`aX2D@YlAIm7qxMJGM z%)hN?eR!UCT0`R0V;b)DKMKruOayMqdg3GowKJLX$m8g@08m@RQsW!Lz6h{lu&Rh> z_^!;rz0kI{&GPv2;oXL(s|fkv6MKy{%_7IW8{b_x;6|GfoeOS!CNi@bG|eC2cQtp) zd)xhsdD>shM0>e8G?2FrVY)j)7xc0==gKb;nB|dz``&3wlX+vhxo-S-meFKN%8y|De^~y(Yu8@AXWP zU(;MwG4&YoX_5$Dk@eRnwN#e6n9WvGh5NOUUfpB0k)?*ZUpqz4;tMv&Q;w*;DGg}- zI0wm_>HR^3$<}bptR4Owq~B3H%y$mT)|-QfFJEKA;u}o(C?~8ikJg%SG`^oKNRID& zaw3lT+bH3-EivU`8Ngj*yI-2i0=Q{ft`11x!X?z^za-i2m@cK=UFs60$U^yV^K4#S zt-*anZ`Re;if&$7U8)9Hn21Sh(3+FYwALRm(3IOu7n^fvp1Em%qCPhopQ(P(O%mYosD1N*?@#Bw#UR$8o7V5P{dhG(ewpg!S zsMjviYZvRaC3@`=S8ZVdoKzUY0kHzv4m z7J)AyfR`~Z^(Z_MetV}d{KeY0rKBc>1aU#1WAF@)!n_49`K z$z!3(@X+32jn&Ujm!D>M|B*y~CJ4_+uD-0%bT$dEOk!7pCdkFL5z`p7@)Yz>6Xp{M znnf~URwkcLGz~MIf1aS~urC-fowm9&hPE+5X6*e5GFIg)bpEiqW6ReuhqpIDrX~?y z(&gx8-7&9w|LX)vjFw}9G$vh+-nUSWW)t~Bf+iVllg==0Z8GU}dYMi$OmtImKNE1i z!o=0~XBFnB$=h3!X(P_OwY8Bk=vT7>{Y4UK#CT^|8?lw;7}|&#-v3RIsY;)p%kaLY z#m`ZtbDZIQy8O(RI;T8|{KPmhUVe_D{LJufh@ZTuPIZQ7OW*n0XGHfP=Fc+se+mFO z9#6w0;Z8zq41JjplaF15Q*qBKA;!_)AjGB|_x{MoyDP|t(Xr&qBg95v1tItk0WzHL z05Y7Tbf1aur2tOHJmMF`5$>P`xi3L}%+)0SPC(w*dLJS7k#-Zp-{XWBw10;Xn`X}t zBHUL9vmoE1`&_`mKba8x`Gnw~O9=i&gy3%_L^y{58UEh@GQK~eJL1dz54!hR?w7ma zj`)NKA%6uS|3ucvcSn#Exkrwq z$cE%4#F#pT5N(=i;+zp)3tej`D#nL^oxxg;Sl2iRBGb=0KzXbqT!T=4U=^=GDWl0njiNdE`oI^8a>ZmUf!nZf zQ70J=!$lP0hC3I0RiG=Q!gb1P10TzS@>rkZrQ<-7^4_z_Lvx8M58oY4Dt>Fhr{V_{ z6<6MN@EM>h6ED55*yM4YDqebjm1O*ip&L~EsORFzyB>VW#P4yNJgDHf@_v@2ys0Pz z6+hO)c=5Xoe96?8oi=$~$BQTLY49xrU72|0F=Ue$0CPNf0rY>#$lC-ymEN2L^7epl zsfrw6y!iFmy#Y4vSQKgPIt|w-)mw6|Oe{-*y{c zN&>#eZG652d_S}CG2SYEjH^l$tl~8IFw}_}MI*GQmxGrYxN&??fk(;1**ohjT|k=A z&ZIA1RAjwqG5XoNZnQO+=$Z6O81p}&vv)gGX3Auw$g@|{Du29U+c3Iqa1FXko}!I$ zyUZCz)Pd*M8{j`C!aTp;$pVtbl-Fh9JWED%z(Ie+LI1h~Kjh%giB2+1dB0#qkjBJ+ zY2hk7=h?XoHUb-eriCkhEXoa|&v4N59rQU4dXa;^z(&8+$}F}=o~7emmULpC@vPf# zVSf_#F98z&N5EX9_Z2V^KLVU*|MD&TAaG?cd>J-hz_3i*u84r7*E;aU4m{6+(~mN= zGp@==nsuIP^n+z1Trc@Ybk>Y79glX>j68|YnUN#WDKpZ?a>fk&czpo}-PdoueQR6O zO$Pe9K`hC$r{#@Zsu-Jolp=$1^T`&*6#zJ>UC~?|^SFPG{Ycmzt-g zPIGtN9yW~o@B6`T#<`vfRrcbf%OiJ%=Y=ya^qjoQ<$A>P(4jil{&&NNLM6xYjkoJO z-Tvo!XJt{}P;)6RXBcX@|0~+XdA+5lMa@t{mofPfF?U6eyF24~(sj`FhqXPg4T;YC zBWca|HV^TP5zgPFG<4u=_gB>#_}cv>oR#|Z)kk>FtKgA7{bJv-0HpnM^lXqZaM#Um z^qIFz;l#!UdH&+cZrm2Ra&X~fp7GF6dQ<89FZ-@K;t!hNVCUHmby8zfFJj{>MQq&N z6@x3P{m=8<){VXHeMnDkD$dm~R@zB#n)^{tw|no8PWinH44m6Z)pFW{)$(l7eHE?K zr{Gjg>M2d0e;R7mPNsPg>ZN8n-FrRzw&6|_t&6g7rbM1qQ>j%kNs(t>o(X*Oq|eK< zQb2Kzw@~jyAuL6_nqZWbmnWw^5_T3##;RBgRL#a4RHWg>dcBJx5m6*jd zJ)i5FB2SFDaDuHp?9MO786YvEqi*~WoE;0}tMi3ot{W%G(hQu8m^by<(!uf#EL#8tNbc`duDt8wFQT9mg|TSJI%###jK^QZ!YgX z)HqjmSe+~~zfkXf{%ymQiW4!`iL;?*^9EC%H&ds}Mm}v;HTeDLX)}=%4xebyf;>rh zcd>ciEHt2LA2ci*Y>}s;#(LiDG+K%l-ih;OuCAjIfYZqzYuw`zSdVO9zW$5ziaq% zCeNq&FRA|d!qjTTwOxI)H+EsAZnqoNaM6@3HlbuSrjBc^F$KD5ED)8=NH zZS1Q@+~8&@29Y zw$c8E!x4Y}XWnSXsV$#AY3Eqm2KbBiid^IVtS^-P2( zyTn79Rdf5L9%GtZJ-)#K-%G}HvqYska_QQRikeDy&&q)%A#zQ`Nl)vn*vF_}ZfHN8 zgsVZB`_5pHd+P2~v&{4R3d7Y#8qU#WYg44&@#p;gkOS0S2N*U+# z5J!2o%`9K~jo35U!3srR_ns?&vReZ^0=7!Yo77)%L8HV z=%F&}oR|r`c4yO0DW=a6ex)pRluXgBSYa$C$1s?4$YB{KRdS9IwB{f=)>$$vKFjgV zOzUo^S=L!HOn5MDmFw(W!{QK`Yv4Q^1+Nl^SLw(x9v4RE5Q3R&1YGEzPlz>E&hhDa zAtB;XLWp>Lju1lR*)fEF1#zrpmJ))$k`RFzgc#(>V!#5}3gVEnnh;VEPMkY`Lbz`y z1m6xqxZg>Lx$<3v;71Q3@p}ou2a-7NXUIIC;tUeLIUn~M&0gzV2kHfi6sO;;Gi0a_ z$aS(NjCUdS5IyGK?jyb$r;#ZgG zxe8}^pDulq<++h93BptL6CJ=gNS_(r?FqtD<>w5~mcFvfQGnK6O~tT|>AS*nHLT2z z{C+y?&HR8ICWr#SZs2L?8{Z&A<@t~>2V(_v5j@whf^Zi4Y72ge5SzSTCJe$qAqFtt zB7}e5H&6WE2qEWI-3)I#AjA7IU>e2<-y?+FpIVS>YK#}}wkKZ$Aj98Dh{f3sLJWL% z5h8WpB+SKm6vEG7eTvYJ2mK%8H-RvSbt*#e$@3oITSXjv@;nFR{{wJ_%ll>-ZXfB0 z-+O=?v5+m#b>v`;*y8)0#ka@CST-$UdnIkbLP0(Su;?tzL}% zAXZlD6hi2G%4PdP5y`O^SmhXt`}Q0&$#rlBmZW(Qd@^i{pLKPw%`d8fH22_F#?``m z09)Wdzgc(~Z>IGQJa&1dKz1r2pebvs%?_*J-Bl=#s8M{maG_o110bfcqCz3SRh&4c zCZEC!kRkcNm67=hqydkTP1-u}DH?HQ=h)ZIcRlzXAcJKTZ541?7MA<3z;_Tt#)D-= zd4!+Gqx`@scA;!hO`=B8oP3AC7m9MlWGsQ(uyDc0a2PJ@M7(fMgHMk4!9%0Mb;`SJ zLTt|mUgFAY1Ya`pp0>$DHI6Iqtt91TLkP>4=|yvhE3X24$;5A$O&<5Z;^p77;9Cm1 zGV$_{jX}i^Y9y|_eDEa`zZRQ3*7bPt>rPT$pG_XrUR-%TWNtF?s{x-%FV$SU_-#v4 z-f^2esL{Cc-cM3q0p_VHeo)(S<*fss0lG5r%J-m6UJ%Uj()((X^8BcDDt^>?@#K|& zFPZqY+vK6!iYxC>lJfd(@@CuQ&4C>%z6C&<42)^lDFjgEAM@OsAN7o%ejBi;(ya0sq;Ce-rqBN?w!xFmPqi49#^T z%K>V`T)(n#((QVVIO~Tp#Q7*gJA#TDNsF_WSRX$tu_cF(x>(mpjIx0# zJ=#BeC$GlXauWqr+*B|38&}`b)^bZ*Sz}`>uiH=Jb~Q7SQnYn>h1$1V5AjyS>|}Gx zG7gcum2pVcMx~QF(q$M7_}uMN_OIT-^?i}eo7jX4@BNQA+zfbP=3-s#KJn655Z&1uZG=JI3on+V=8sRpU!1mY#S?=tKHt`jBh8KIBf1 zghK;?3w~g9;I@h>z14=g-2uBG+<_eIaN&-Fb=}y3GY0pxay|WPnOERW1Fh#+=I8qK z?stbuI$itSnXe7GJH?)GnEopUe$lw2xm2#=+utNl$88onzEUxGyWC6C=42cbdEd`m zH0_?u&-O+4J+YfvHgLR}EA$9$TW84h7321u^ro1*gctSkCV+`O0c-D)J2z?v(vA3u zS==rBOy9)rKv1h=*rpWvntBXh77U00!(WtT%7p(qq?m8WM{f^U;M+jupDVK`Dd27s_g`acs0`tv{CY-m@gv}S5Q2laWVdNbFEDK^^K>bR7 zbP%$gV^GchhssCxCm27;xfT=&hJ;c%NF9Ia>Pd5~a9=kjrJTcA6DC-yCpzNfD;c1p)ve9xayR0X$KL9?y zSEG!IlXI@R6B)riPZ^m%Kv;ck-o?}4Q#A4_`{x~ehaK{i4Cfs0ZSb|gFXP2xpgh7k zco21xq~Sfr$&Bd^T6~lT(NTHMG2IaO0-%$Rd8NXo9~DB=Y?p?ypj0AB!Z zl!xjUm4`9ik_Ca78SPwO;liQTE zZ4)q+x9UE-nkWZLMMxgg$;7{GBKY;l?@Z7?{cxPN6mSh5>O10#0B^#>bt2+B+mCTnvk@Plh<^Ro8hhD4MkJlUqpsGMj!_B_E-#O`aYh8Qy=}(H?MaK6dhpW2wT^#0@ zhi2mYLh8QP@n@#|1;1N_`(6h=dEe_BH}k8z>0$Gx*H_N$sW87?^u*L4?mjYadevtQ zzvq7mBT_bT`TaHBld zWhHO^f|A0q-AlfBQPO>dnW=x2eMLX=AZEPsd#^EEwvs5yzT%&Osk~KvMM;#yBVM%V zbfd2SD?pAr-mvi9fXYzUw<`n?L(gH~z9L>_qmw_+hLcV=WoVDZ&7#GbldIFju@A(` zZUEO)-n3=2<6Apd-lk^7^;^U1RZn5fqvTpjpW*l68$}LgVs3r` zmS1ciDu+LBI%n73LY#8^jN$6~>qrniTqwVEe#+aWxtAK|nc0qt5+kQiRhrM)D0ua~$K*M{pukDUZ>_mP-dcEvJYyp)R> zkNu9iyI6l@$7h})E6_#s->h2D8M0nM!AKp0enxg3XdcvUMBpS5>UJs?*&o7D&H*u3 zI$!-CRm*&I#+;570J06FA>7O84#gLuJ7AsV-bQ!y&)ew^*iLuE_j`mCf`q0qQS3hf zsI>8Kb(pk_ZZ?BO`mtEY(pOR+(J%9vX=8pm`^p1|<8R=ujB4|1;GpcJJ%|L%QcO0Q zv#lQPO)2nU;YxtGl_lu@*KaIp79ywf0=zA_I1CDT`K zxA+);YHr4lMM=Ag1FWCw+pLbha)I?RK-mS3I9a&&WC!XB}ki}sE2I2?=0&c3y}tY|$t%Jr2iu2j7& zCB^HAo@mn2c=6$}>gfEnv@QLLn%)Qlw>NgQzKrvacjEeVseWMM^gYB7XZq$oh zbITxv9?v5rk#ICV*?F0~qy1hB2D3?;oYduwHczU~*TPNdO_ICu^x&airHdHnWtJO& zG+_w%twI2mJm;F$dI%p$mn+?-!tQ{DZB7~LKpH3CVeqjnDx>(Qqg5P8dk1`qMqJrB zpRx1xsR)n>M$ym}GY?v%BYwy?k}fB|y>BRiC#Hj9RsOMfoqTmRKGkQE5A&IYW6{w| z7Afx0*S@fJP7~G9X^hpFza6IZ`KQ~fY?Dz?KPl$fa)lztI0lIsuRM#c%8of21~G}r)O!lO9~f_;afx)lAJ$Q~@_H5Q_GYyQ zcqbnEr3z#DQKuMq?DFy;;5N7^qvUZOs_dlg2QrdQQR6uk_AB6HxhtdUjgzk@4qp%+ zL5iApfG8PsRCbO7?0kK8#73ht(i_t$a2QFa*mioayzP=L^G6$}6)#v=lsb5sj#kwB*-$xMJfN64S{(Bqlz5NK6+sB>q%~EYxX;*kTfgxy}<9BT}sc z7$ee_^8CecN}OSOoRRaG-vif;&hV6QYDQO`>twrlGrSjXa%UR7buCqQhVKjE-QeJw ztR2ASebCSE;f-tOYR|ZT9m1Xu&S7{v=Y%_&^>C@--u+M{64oEmAH6T)+C7+^-uySd zLV1!QMR?{?9DOE zQxNx7tT1XSm-Ge#zCM?cW&{oMGzZ;X-TFQeoSZeqD9JF-bEIc3F|rKLnV+^0_nb-> zhw88kvrn_6rDxVuPU#hacZYnP?!G10@91BoEm>QdU0pf!=9A&&#-%pCH2Ib_zgRKb zVC+R6JG) zx$9ruE>Fg!%abwuBF1jR-IWubVRSZYVXf;Y5v^NviAQ%tN{zv6y-StI`V;s{O0PO` zQ9f{aa6_L6xH=yTyPmq%$^+Lvbf{-KugY4uFQnt$Pgevni&R%G=+*W;hVo{tS7ugM zUX1+I_ows)GrETM1WU8;?7v>$0b6(I%$twln}@{VOx~g?z`V@$Cy)hG)c8o>O@#vIOvzhz>DcmcZ)48FkFxs!W!GAVsf~`HVWM zyB%LLG2dw|L?|Eq689cdd5rsv&l=q_4M^iPOkK@l<~8J`;&E43PUGtryvI~;%Q?}2`H7`4FE29j zx9kf{aI&9Ufjy;Ek9|HNY9|v8IRJPZ=U+$x8v!T)u6$jX|7LhxkdrzWlM7hoWQAie z?)Ax`0Oq8e>u@nb>SOT9b1+x{&7eDe3t_Lf#6?eI+3V zl&c64`6~(GkKQ!$?sO(Wo?4tDFCb-KN<->C0 z9s2l>y=RK_1KCDRA`nA7*)3EtsLBE0jp=Fj#p zAMKy*pa78T<6N`fM~KS#3?bUpj|kDO{>j4MCq(=3qY9;=ePj{hJQv4wgl&XqPj_1M zN+YcQnmBZOReH!xriaLVJIu9VkDI>P%k z;6}8|4~e5b=C}aS-iirPel$AV5wy_Z&N-iMwL_gsM(*{S`xOu&D+0Vq9VO>hsEe{0 zLAS7uP?t#Eg@!OMz{tlsuK4Ij$%a)t4L-X+MI*Gk9|a%B50uA#UCG1xX-T2E z7$Sd1TRSN%S&;PFNkA&2*!t-o)7imikq0s3mG{NPa5Lfx=XsF*KvdqU^B~oV!PL6q zJ_r5}HhhQWpMJQ`5CL3@CuHF@fcN96uyB^u>v$MX^3MiT23>?X=CmA~>uIE0OR+UK zVvDJM(}wabo42+le@J6xeOq|_mEp+7Hf&?vvgsD}x`cFJ+gcyl6xn>kwN0&Ch7ndY z)i;jh&bj-FEgR}LUDeXo%2bj`?z%Hi=njeWL&4 zl!ZeVw74$G8TxF?)MMzxja#!H4Gp{*2p|8=aWv%L^?JG+8jXR5n>}?R(EsA{fo$FX z9Hi(EHH*9jL;ixv;qw0W^77LQawofYr`Jxuawtaxo(~j@i-vmB>)d^Zf7jmc&P<2z z(!u{+UzBx0jWjUJ#t-UIV}R&(~%@bMm3pLvPk-p1#iC9qgwB zaWdo=!P0@hT##AL6@(AVFgx>M{lNG3knkgA-V_7h(@cY8Z$bFwln>vE7(>r|EboHC zjJQJV?T>_t?@j%QD9!3`XxSw87YtqS|B?4D@KIIQ{`fgFlbOjwm_VROh;fo21muwy z5YWnGlAMHR!lTMXTau9A1bKuI6kA(^&wy0}QX7yeda+fjSG3xzwOpdt_G(*iiP&EI z@P1-%TQ%vgHyKDeSNZAx``zd4nUg~XCJJ8r|LspEYp=c5UTeS3-s|kW&)(j=&^X23 zH{YHz*_~S2qm<668{=rM`$1h(z}M$inre1Gofj^L{<4sglhU-{ zy){a=;&lu-R;v3C79llx6Vne3{%NJ+jqKONTN|6Rc#BFAUlO<@-xJuqHoW)pPj~1f z#dCvBSd7(pv|Oa1b3&IS0y&Owa1!knMD~T;Tf%;dd@!{Hvv{9^Epxu?%{QQidn{>3 za*t&QkY@xeM+UfOM4TzWL<>7i?@Kud2(ttEVxP)PirzzHk^yITo4_Ju7_79lwwt1f z@&mpOKUu6KKY<^|62?XG3jH2H+R0{l+(+`y2$N3ATZRDXCv63UPm)X~nzW%r{UQ9T z;G^vL-P&Gn^`zFZ$x8k z;hdPq*h6|nhu0?(nL4pP(bBNJ<@D7`-gnQH$n&w-@Bs20aZWL2MsV>|gi(&Ew*ix7 z$uYIXz#j(Wn71~}t@jOVuhMbMn(;nrpVzHgi0Sgsj7`d78v?F&bjNljDcji$4Xo&8knt z?N;{Ma%_()qF=Xt|LQg+JAKEYez)_nC!Q%h*kXLZxWM-UK2YbY-{*5b6CDcs zk~~1ZfARglnh^T0ARURS0puRT0K<`<4nlLs0Q^kuY7q6uRp(+qzs?jvw$GIaV;>^j z0eCv`V_ZH(OfUQS#rT=!T@3*bAxt_ckMo1lPul+lGD$L-Xp~JpnWc$H1fNCeWSV9o zz%1`o5SS+Eq@R7dneP|iW4fi2G>-4)ew2Gr@(@OS=6;@iD)QR|AY2jzot=U|+Zrj$i*cDyBX5F@? zHCr35+1RiNUHd27P=b7O{Eay0ko`d{Axu@7>aG7{S*~7$bC2I?otWqrqnP#eGm1xG z*rRhdDPpYYr9XgYk#YcZB=j-q&$0Qel4X_#AK3lP3Pl@>&bbNU{j0 zy;hAMA6`12Wum%=#st)V&Ib7r1ot`OHE9`J~$p zMA8^0{Txfpd^egA6OF;hTlo1T-*C?-p1Y!1BbjrU6Z`jyhxJ5#P0!=j`q*jB?8DgW&4zl z^aT&ap(Et3Y+n#G$pH|3i7( zy;-10#W}RcoNdOJBhn&sge@{9TYQtEJQ?zM?OCv|#QDif(&7eM%hP97^}On;I@vnW z(c@C;-I%q&7bCy*as9MBZL&YE3znIp$8vN>{QA0cz5Bf`Sa&MyI@N8w?GJXT9hLQQ z`wIilf6&&q-yh$#C`QW%x-yX_nVfxh8_Z z7iYnp7TjfNpZy=pcYd}N+M;|{qtkI`xL$M|EyUO_#|iDB!^|fffzFMYi#C$=i}5Zt z9aU+~LIt9|dX%@9@B4DAVz;CIXzz-!hki27p@&I6=J)T}25v|Cku@Dhgi~6o3?V9wb2O zVxaUV!*Ax}UIVj}G(wbBlcbSvxPA@&OYz*1*wnLPzuW6FJ<*o_g)@nt{T$=VvLFO> zDo2Ol?6o6~HuPgaWm$5L@!JO82S^+F_6WO}Lu@hOtRwTERcVVlM|cdL)Vx{Uj4 zBlcj58OkFecWc#P==wQ6H%|MaRjlSH-X}w2@}3N(C>1BS+j?qwJIqe8tFyPx6}Fjo zmcUrh0}rrhgJ_;K6Zucr3@|icUW$L`)%L|ONSlUpo9ruTv#tc>oF?Za z!{1FKF?$#eL%D5zJ{N;ey!RLaW%{ghpI3t~7d+I5>Jsu;ceEuzY61|BcJ*-M0Og9dW$@7su7RKO zWcg9v%%Z$}!@!Jf-$!2TYf{_w!m^APBmJKF{LFo>McyOME!IjSc$@`yT5y;6j$PIr z#}nEQbkp#oJ(?!4*z8eLuRh}5{#=-$9%aJ4kNJF;i&l@h);N3XmsOkH0o&8=RJpy_ zX>XmXs+@QAD6cL1>K|Ga+)*HGQzzOLp2NZRH}$aALOeeRqx*lsHXW|-vf8E(qo{`K zYpgaW&wXY4kxup@R=$(qOOZ@~(fBwOGaO$Q;y^^$Wq?o0V4(EV?lJRu_2)SpPtpic z<>5Ywe8crg=xYi`^6p!h7yEqg)$GjBbUB`|=N!+JNBKVQ%+~5>_f6iPMOx)Qr}AIY zD$cS{72 zZQ*(oPP)166aSKh{zVHu(Snb&;Nheqobn6{SFX$Jd)J1p)timrsQb~PZD7+UdQB4p zVr}0n@>3bm%Ny#qt!+T(UVdG}rgLFO!)mp`O11H(zOjK_hhalI;_rn8?f65Z{h!o5 z7kzN^2UR^|DwX?OIgZCU4}2u#QATOb;Oa?kSkRe@S6IUOiMV&AIkovSAk*{Bqw}-! zwd>OpyB7?0i4%0o)8@|vrD^Zcx!U}!n_wxsn$*&9UVUy^nc0K6XGasUe~w?0_IU5V zCD6aHC&BmAekC!nZ+@b!-L}scbk)35ON!bX7yoGQzp0G1^O??|vznnh#mPo)Z+G40 zSy^?CCm(Ht)vtoj}qhAP^+!um)O(b%I~i23_9{F zgN0(wT@ULVbR|~?r-nn6tXD$Q+B<{x{IX!C2t_*bfaig~Co%DrP{zT3(DZWoWg2)} zm3?KwaYlSgWFA-NIdMQ-=NH6nwROknqS0FAPB^pC@z~!X|{>jz3|D zjwZw$ws_uvh-VT5dMd;5(9}pizt628znjz-Dt`u_wWnq>eI*m+yzP9r%7Y1CZ~B3klJlZYD%KYA3`C z5Z~wc{wdZ@(C&Ug9F_8h5$=IZ^7{#)Zj}Mo8?e=&?>C^h&k6j8i9_x$0GS@1zt8mi zmEjyR<=PDD8r84AToK0LZUK*oWAM_}xXTm|DunwQ{+msuSAcVko^kp7v5Zh8%2xc$ z@@Ut+k1*+^JdU%{PuklMK1ni}Xx6nE&Kt|U5@eTYy22EP;ck=#(qfsbY&^~!Q4 zZj~1TUj@RYizd&9&LS5~l*j&(pA;bJq|r#;rD?5&3&+6N1h|jso(b+4q&N99PRgdpt3A!zq3sdUy6UU&u2&2 z#dtl@grkcb@+}CuLX)i6?P>Ey)w6G1rE$BxY0Zi)%}cgzXjxpa{2Z9M{Azy}=Xcdk z{1O9q;8tO{i;1q8`J&X)ymUpn&x))eaYE6LFp@WwYu?N=}c4lTux`NXZ%%} zMQO?=MZJ(H0)#D6Q_BeenpKvWu+I>CoS@2D^^?jU} z>7~V1fO9_+>(qh6zRI4&5`Ry8j=#s5UDc<$FD;!{YTr}R6Q5nulbB_@cV4Mu&*;*) zZ>Q$Hq+Ow@4`y`Vtl1u|4&{1qvxSecnlm5n{SVti1K(YSyY7|8u6Fgg?7#7;eX6>n zCqBNd&#o@$QQhC`jdv+CyMMK&XO-$YrtFK;GQHG536*Joa47?hYTAp7kK((GI&{Go zZpOZi6vu+WjUJSd{ZP77++41vWds!O!^T;k`uPcLBAko%*^KYw89;}zL9{hALv%Od zpLllh%nI8O$oZO!ratbo<#5co=o)-wZ(V@jKDaYOeVp(!#M> z_Ji!l78_vz!f|b~)$kJl70x=>{9_O%88iaPC;L@V{s{jA2z=J1W4}pfoomkHxUQ4L zf9bc*HS>F7m|9^cMO){Z%fOclF6u)uhx=)mO)P^Z0O2+O8E#&Oaz)!Q_+9~@4}Qv% z<%eqJT=U$K%>T^ED>63Pp1t44@(^9P-=E4-{+!SMcw_~Oq&t-hhTtr@h>K# z4VxO8v7g*D&$gmr?Y8EI1sj_-H@Em3uPNVD-&nh8KQw2THnXhfQ`xN`#5KDkE*7ZR`uj>t?DUgcHSGe=SQLOc{p@uQmOG}uX3-w z{b0W>;q{RFu+ocgb5ZbA0io8Vbd&^k#;di;zE=aS@olxZ zf|_^@jxWhtR-<(60JZ~A$$E*ioJw4{yxPhf556689Iomq5;LXVB*o$DN%1Y}ag@0G z7r9@+ueiS5gN+P*_|gKGJg@yg>96}h>8m~Aa@Cv|J-PnG zMHMm~(A%VT{0JrI>v8yy0tG4Xl=OL2==a<-u==SbgNMaFVWrm{&-15v2VLjjiRMb2 zK!rTo5{&bw7H9|j30;ZZ?qF8sOB&DHGB}%h-(~6P^Pi}d<`q2Is}{M)?wBg3(!h3nb*|bkt?~6KzU?&(uj+Gq`f7cHY96sW%Y1|OyoWG@ zo~RJ_IygJtSBG%49Cx_o+$q`%!%mv^$f&)EwqN07w|~@@1YZ^BrQIyfh5Kn}+F|nk zB;;wg?}-mfvG0%Xcc<-2eX-x2_@^$BN+I!H%^Bvovuw)Fgnm12ty3JWZtS^nv?^Jp zYPCQ5gpI8sLv+M}k&uBb#S*6s*Uvbyl zp{91l8>)E$Pgus$=L1U8^OomC@!nasy*5;-Su~tJ?~H9 zZh6#{nykO&v8KrDC>`CQ=6JHRj1)facO6R{IMkq@{dS^hiZ;HRavU89twoD+H`V)s zb3Mw3si}*D+e$EJzXdll#IxO2VxRs3_IozmU3jr{Wez7sXFxj}{0WWWyZzR8%!$TyoHh@W`Y$F^|gu%&o z3lc9O%+%+G`Js0{aj)@>Q;xr@$vdu)4a#s2Rs4e8|T&%T#E7m zA;v8m256oyFpUs+k%6xR}>&kNln;4Gxt%QjGJR$hqHXUCGNd2%Rg#KoRV_e^B zgdZ@%Utu`L>E9AgLL%&dnE2#6V)&dwbjGWUaPCoMcncvK&CP@u-}ew=d_M>{6O$6( z1D0fHPsl>;=pN>|i+LJWB}s<`;w$F+XeI zrwAc;Y8>LRJ^@*;mjSX|R{>^1KGvEYIHl2s;>7$J9Kw+Wv4{u}U^ZsqjJ}1o460Aq zFc^OIO;?05xLd#@WE;FifOnbVp-Big+}d<2634h0Y89pnResvqH0OxNicEkAC*`d( z`5AsC^2nwmo#dmfNI&~fx>oS5$4@#@9zd?ZPsSnbFDN5PBQE_K{ARvB@U13;;Uvuu z+&nkE7|#md_L--UWP~0 z`z-h>K$k9>yi?#~e?ociMwK@aZ7LRd8^9;!p=n2zw>L(4zcEruIGa-s@i~c>zC+-PCBJ_$$-@v5RbC3l?^x1zHTYzHy=RbjEBInb z-!Dw^vd+e0nML{ebH$e;`oFWD6FNKgyYQ^v7mjAiKPTTW z{}p8raY;k=X|crLj}YN=T5y*IcU$my3!Y%X6UADStSheVy=drT-^K4u9x`yRz@6fp zWd^ZrC1a#pLj*1lzhsO=^93fqSBY1=2F^N9hG8OgF+7=H9sU1tJ!RPQM@M#0kw8yP3fzK-_`oCy=Ze)PZymZm{rh$)r zfppRM_>MPCG66>8YXcwq4(X!tb%M_;nE)kU7X0S&>js~skzM*Rybj^}Blyft${+-( zNz%wS+&GHytY{?npcfXz{{7?gc$VP8ds5DHXV~ZEo1~Mnzyx#-Y3m&4%r2HaDZfJm zStoK&3ioj9PM3GBfy+H3*IDS-o9HhY@+gCQLJmt&fP61_z=X4{n4f*()fW0}6VCXP zEjW83=|~SJ4SwRrxF|P4V8PxJa<;FQET0%zhFR0TgsS@bHR1!Mf3S|l7ADg+hLLR< z7%Jyn>>J>hN>~p|Oya%(-ihTAUoAP~cXPeAzp-7jKgAoZ9Qa;IKLG%1us)?f9bfT# z6vtDxY^A~YKYlnIh91g4sb2aa$p^Vn5K3jggml(blvc1rT6=MbKd-i2z zPlhr)?tEW4zL@erdi=bjk0P%7GG$@|_Faz6e#gDet9+Q8eIzu#8d~F*X)l+z9W47B{t+juRtD?DsRKJw6|a7>s=h{U6FWdlQg@{`RhU;9 z*+jAK7iV5Ygr7@+IEY;QCyRKrMcalo;3SSo1q}Hd^!4>XJUp}=*yu&O$AclB4cIth z{6ajj{|J%zeo2!t72tFEjnK|Btb3tLV*YK&7he4%>uktR4sp;+nJ>|G$=-la`oo^c zH%ZTZ#`^Z1VI5KC5A}4;@^_|n%k!b{r5MWd4EZ}>^Zc|?cs?BMN1hKi1CaCQ^$f?u zvw`7&EeyxQvzHLe4-?|~dKqvgD&-G=d4PX4=%)z5??4md{^(pnJcRtFh&cBlQ%(&b zo?Fa2pFZb|_AG2D@lb;&26qd1U^aza5qx)ru}F&_Zcf>Uv@k9n8=)7)aN3+QzfJnv zF!I(R4AH~xL+}k}OIzoZv!U>2Q$$1)&N`=j2n8X^!k|mP2HX@~c@zXJV}zZg`4M6+ z##g~d+miZF%tAIzzkK{;9C&eoV{CKETt}b|>7JnO&-6WilzM8!6(a)W1^I2 zozr_Be8atqa6C2FuLqUchA`F#swOOtep!d`Vsn{Jr=L#J2+i^if{$Y|qs z>=DfA%`KKE#+-d$ei@Y^dF(q_I-l(BbXvvd{`~9pB2Dt2OKFf^0pl#VQ>j9@EL*zSdm1QmGM0lr=?$|;Vje&`db#Gb}i^Duf;B zVb$;xKf?@$_+BCEK`YTN{yJ@9A#xeY*}pM0MLq{p68ySUe4C)+%^hEt?i8n}xWy?d z?=;5k&I$YmZ|Sx@_I6uGcdfmn^Mvb?RpMR#%}`l;RZn~BC~aRa3X>uMy^klD$7l9h2@Z7~^=jj`IsO;uf%) z8v1P=^V2w0V{tb+W+(>Vui@PaA~af@x#m}q-pk#FYrv^famCx_vn zmoi_XtB|EdDE(niWDeq<&sg6tKb^kw^^VSR<+&j2m3b}*=YP4Ei*`2e?ma+=cJ&KF zG_tph@Q(;#KZ|dZ0jHv<$-j^gcr_s9t^}mqCWceV|I&FQYyozt=V(Mbf%eW;{1_(P zE8zK|L;!&bx6b5e0PlI5Bq;hn$!C54J_x?sB@wLB4zj*~=ORJUcA-S+*WforSEhkr z{-#mV{NQ80q^ks9B@pVPc|m!olCYfxuW;=k#ImRB3Gh*ebW*SN{TrW2#q|Eod*dpk zFu-W?e0ZL7L1#YLzaiSN`3Qh77I}wF^3cSi%6ltDd0sp`GJR}MGJV$f+e+{aXIEO^ zZx4cx#whcPB!uPBFUtsC#e+(vF6ktV(A*AEz{hk^p85UTSW^)nq0ZPm(|guEE5&&+ zpSdp*Zn9@TPxs7RD+^3Or?}rB62wxDINGJlfy%O#c4=#vMd#-`lJ0c8&4TmYh)%BM z?J?1P2q)T#AMMzS0e9fXK9@M_>_RYXFmUqTi+>C!UA|8nUlZdy+UB7_TN}bR!$iI~ zUenxgT|@KM$Q>^c(mAjv`<^TJmjoA1jO(+ zNdw1|wf+9KqiNd3MGvPxlX{`|qjz`so1Pn|6&*d;t0q0vt0dj)FCX+xY&$wuOV`$7 zRjN+gpWf#G!W&b{7Gw&UjT@8~tk8f(%!8nEzVvPdQa&n?CSHZ~8Z~Z6Df86|a53vEm;xnvV26 zH_D;)sO!r8WrMbf@J$k>GR+8Vcy9L}#dxD=fCkG-ic7d7u z8QD>Zxnx9|NF3px(#C;79(}jWH$Ys6K~Oxefa07qCY<&NCVE6hkw;+<;L&n`#5{?o z8fh1KHg~S1pTTVc&1_o~0pD)o7i9^29e$BQ*6*(EMi}GLTw*%dhkpe>v%GIY0Ch+w z^vgLMJrwpL_}HIGCq-Lr zhLhk6fQkCpo+uC1bK2dtSA#Izes=2^`aJm9-YAcCC*{#E(*Un>3juotQv7Ws` zTEfeR%|B*KD@q2_r|v{~9@7d@W4R)aC4>9(XLpa+9NI$@+z*aD_Pmgebgk_i9N3!B ztGYY&UdA44+I-z@kmV+8C7AaUbm??HLm832WHu&4h$muVWxt>;2 za#{`d-GK)ij+2C#{K5~TxEbhS=Kn+K24-du{!}v|)l3!y8`R)Wcj($gw}zJzCqpo( zig6Vkj<5@1l?l5LgSr^j#v67a!VyIbwxVysKe0~=gD(v^UbgEc1fE5RL0$A|7=$Mi z2mdreM50Z>!FdKD;uR7iT#TOxpG6$;=NaLb5+YHT5kgLhf%^#&zrw&P2@!7zA?CK0 z62fp=K?uH;gfPy&LywqCuIth$x?~wzb$zlj93#rGB8o0qhIrP`K^f}0z8FQ9 zEJLfVPgaJyu0>IF$uhL+`ebFOpS>_HiY{4(=;xx9;cPt9vGg0svfoG^<-FB?Tcp20 z-zuIfs}6J;;<*Cd7o&~|Qb!u{Q1jj7yZ7d^1 z-@lX)1LYNjc;WvFAqx6FgMN?@^hXInKTHVvTY#AuBR(Jwd14&~ZS6jE*OYsZknso^ zj}Y0V;oO_9Ah3tOooV|9piuYmKj$!nR`~&j*h1I5nNH6PB#(`H^j0mC(iNHy}2EUoF z8hqCa4*j2``GJbEHE6GbF90I-u?{GYb&!vrj03Ndhd@+u*h!j|kLQw8hjfx}Is(jk z+rdXY)XVT_db$5D7J0u1U#=k!O*N`K2b9GkuM&Jx9-4Yoc}+3Od)6e6?I~J*e;=bf zFCGk;K6K$x8l5y%rAzfsPeuU zqr77#dF-;H)ki2sd6%Kl$@K9#i6*Zee6i&BQIovPGsrszzImWa7wvgV!uT%J=LK`L z^c8`xObP>xCU3h*Ubab|b-nT+_*M@i4@2XS{@@h&IuK^Vk7I*OAN?{7@G5)pFe1xg zCuxLubi(c+_^N?X-X#2_JnX+4(LHJT1^LGI-Lvnl-#GU~g`ztpmJaqYeW`h)9L$ zAIFA>bBg^f5nPPKVU%l?(}Brym1~tt!yIw?J0x(1aXyi}Rrs-2q#Zm+DNaZ_VU zW9^2oHxn;)bm)4I39X)-~5Q-=LJigTVR?jdg3d?%23_ z6E~UQoKh9vyr~NV_qyVKmEC8vEv%vc)SI5CZLN0(N?VV)TyG`>j`5qe?1eRzftOvU zewF5JtHC{1%?AFa;;jg#DSBxUYxG%~Y<1qe2;}^CN{+&nLQS3(+ z%@z9br$2OrF}U^M5pfJ&+Ey*5c(U!(AxwWHbmF4`t@tr6^U7zEV3~KlXjdZxeuUO<)+VkF@rEKLejk6C=tr5t{WL10TzkdNB-#^`h^a zHKM)8#RW0%JzmTVn)<#}rf!(N@9a04e|C37enTW#{&OmP7l=4(zi2LD)*nkY;@EFC z0F`wj`^|-67G2&h3x218V=`3u9UbBt2+VJJ5aZ#M)8&eXD;hIg0a9PiBc$ybNc)(bHs_56@3oZfm(-%UD4-uQ37t0sqH(G z8ou4UtVb==dg3&EK^z)a4M|#FXnallsJu|JXH7tiI(E-Xnwbto!4jo z!wnhDQnYDfUWFZ*c+}Csh&~V<8ca9w&d&D`c5v+9*a5NK@G-%3h@jJsB`)@AfIg8p zgj`IBd4#Ei5OxV6gt2{cqKNO96iRuj7%0x~y@>OuM?8-5X(p8Zu;8O|IP zcWc~jj@#{bMCPFopW}}W<$)|j=B-hV94ENXc*J@x8b%K)V^}>XU!e!|5$G8&@-v(s znIF{OImnN$XTllsW7T8I&v~?q#JUmB1!Y_0`II$;!0Qb>Jhug$<14#u(IipMVr)iz zBS^G!VSk`~i{}OH8YI2&2xD-!fJewScxh+dWr`nCs&`@Ocr&@lIepTU0g7N zZ+i3R#C}d6_r1e~_iKHg_B=l%k|zH-hnxpw^m>wrz9&w6_aVzx+QY&I5L~PkMfn%; zpa0^-3laIrLwoZ|K-vli4g4~|qxijS;KELTpN{QE*ck%TztxNA*6D^pdiotrF(2ha z8+UnwE&wwcU#ecYe5J|EjY^QWLFo}by@~62?xhonsxr~u?Zq86%Tntz4*37)IIPye zt4cgaroVrx1mBK1;&?KU!y9PBo*lKlWYDI5BlA-1<{dwNR5w0s@2ybtL$+y3!uC>S zRB_0YmmBhUZ_3OH*)Frq%slSMZq#zcZjvQ~S8wJ1n$_Z-nETRrQ%sxx?PJd1ZC4z| z%`&I*lu5YT#ap7O`*Q;O#jP{guTn?4;^nO``I@J+Pux0lX@#KcaD8;2YAzQ}WQYHJ>?>d7H zZH}f)VqW69CC0r#%n|c87rVpNW3>8_gFEy_M!Q?wf%{Rp}y z@rb}H1`T05!^YwG%+8+uDVbmfi%y9BP1tq@{ZraJd^9k5sHl{0KK(BnIKQo8Kg@5d z)&p{_?}vm)AD=bSUp43+WQg?bgrEz12tec+`Nf~er|8B+rWtT{w+SpFuE9!MXS*qy zC`aJy@C%nO{7>L_3_r$Y*-|gd@+$|J!GmHJk%%i>xSPtW)`C$RvEGgq&(}G$?vv&pi|zN z#!T*U)_ZI)!by3A<}s6docW$cd1yAKF|#l)e*|OZoLO^Yo_D`dJS>qha|ToQIiGtP zdX50jw3P*lG8%%a!aA1(Oea0H#c#K7fT)YTUH zK@0wng+H?AUzhimh5tP^3gLA6`vxxc^;+;g3x6Q|KZ@js8eFgq+$+9vyeG{S$Qf%6>2Kbh!P0RJ+6Wd^+fe%_&3VBiWP+i+xyODP-Uenyzas%#u+}zTz*7!6GWMhMOY2-S})6Fg8dk14)@Jxp| znm#8pe`vU7t?BzT+GP6Gnz(xsS8FbAY-!ohpx>^kHE-Ssy2(T{bA~VBjK-$l)oB)J zy{=Oica}RnV@a3JbA}Y1JuPQR#fs}2Th<2ja@o|db?Z6UjIQK8*Z2c}YI2`_bo{Xe z?zul06H=Ghw=c-V&hSNJn+D%azGyB;;7&@3GfqB!H(ZyVTz^whrH_U9!Xf&KnBs!N+RzV9|z3$7z`RbYX_nW!FwM zesx2eRzB#NRDd%f4n32v`TJV^{*#4Mp77g*m9`}{;OC|qEo~mx>E0ZT{q9q>60K6) z-uKJ2d`&+^@|S5(_+0~su1Vqj-!+PNe)^)|dpKj^XhPgv1OX;1kb z11T$|rim9$OkX;rhW9T>L}?^YVpgu+zUJNDD{dw^ZrHKiVd6nu0Fe~FqB+# zgV+&1Ht>7saAb>s-C)gVqlM8*B$)ovWNv zPbyXS=7qkXAmxdor0FMX zP^WS+-&)G?)j*s$Ut^gzTGUDCxi5&4Oyb&tt*ddxhQg4iX6G}M;R*aJ^8VU{1g%fh z&jp(D?MtyEU%&m(>|dB>8))?-=k==!knfa(_)@_(;8||#Kd2&qMfUE}!GF%9Or&C> zS37w`>uc4tlZBJ`Rl>(h?$o+Oy(qg=5?C`AX+4dN8{Q5nt*9S6>cyTPO0CJqo8g{k zGD}N))PyO4pCfJgBIoKr=W^t+){ieE_#Ow1#n6+Rdek=X#ulwh{q|%>MUUeer33#b zr)b5cwszY-rpBG79{6L%A@?C=iZ~xuY0olRpYlMpc6XYd)4S7jZnfj?w2A2zJ+ByL ze0Q3x6ZQVpn$oVHtD^1`*lr!WI}N2$i!w=W^T!=?B0WmBzsId4c5A^}JSiVFA?0g# zq$$}*aSnP7#liZy%OPs##^)TY9c3JANAYhcz_Y@1t9oj`b%~a(>1Cjp{OUmaa%%On zE`(lN@Q^=Q(`%wKcuP~HCT={!o?!>ygX<&f`AJ+iiM#`<@{L z|9b>aT(M0t|1lbHf;<7D#1=9fU#KW8t<2@!v#VZ?LEW~>% zUMldaCninBdn#Ux_-@5XPw}3Li5g*gBb@I?G*fB&^JRqZBYdgkTn@vbhi;Ay>}8Ky>}Br{yl^! z^mam|_gjQ0#QO*l{%u0&IY5Z;?+_yV0Yb?CM?!=jB1HHjgh*si<=}~pmsA%UL;TaJ5Lfge-5?OylTM_zJ}blK51AAB1HCM^@}#~Dsqg!06ooP98$mnKzmv!srkx}j`9j|@q~6en zh~va{+jm0d}U`3g5Y+~*mkrHgT4 z*nFW7MLD8vj-amed|eWyuB>@7)zt{fPQN2~%NfcJW5|#?GL_v3@}leca+JJSb(r$< zDd*ECpnAo8Iv$fD^XVxVg6=~Y=f=G3 zgq&S~nXoM$CJue#4p7iL4f>x6S+dxjI>fPz@x!zj=04#tW`kAOp~3`+*Pr|FcSNuo zF`SA929mG`QS8EaMfWM}Hn0f$48E$Q32IZMt!J8A&+&H zkDp8{yvh@(7?y{0l4j+56@1hoo#dO20JGjCR50~WFTMBoD)3RC$kr&nJZeMw9oRNgleWsPa7MXZbE7T{L;s;FI~q zuoP9^cJN&$g#kvB_pC{t>^I!t&o{-PnBRks&#H9M@mEc<~5kOgfP&1_eI}AP_h^$|ZnNlA8G7h{-AI4=gnXr>I zLUVuWz(ckjVU#xwKPhi!5pHqwM%>xXvMQK8JLYc;p3n!c@ZPAuhi?qNiL!|}r?NAG zz{k>$xLDSCw}M^PiQH3lC@eyk_g4%4-v*AUMBzJO!q>u2d6dC*$11=_@LOo$vjL^U zBRFJCCLT$PzHVqNwUuw!DnACOYHDb%ZQ-X{`Vt;V)jS%CAAzkY*?Pk!xjq-BR5Y~c ztA=vnZkUs#gb03Ib}rVjLeGhL;(1!Qy-+n>sR& zmIsUS8Mn<(|7C{X*5!xvgl_WKAV_{>L91tqfODVT0I5fIc(DevqztJHs+_p z^^2w>{IK7|V+cD$^amL4g>4OEPT1BkhA?!Bef**yaU1OdMB1PMSq{XM?L+;74ezx)AsWtUpWj1ozF@vdT@4yuIG|bjv;4P zpbUrAfwB@hK>uQFI+m#pPXFlBgx8*)8`1R)tIL$1xv}d)mULYgS+YbUe^@=HJe|*X zagI+stD>3^ZFLe#U3FDVizr!f{T2xuoap?iR3! zxCUzx;9aI@vK0>ZUdWcoxO}dtm(LaZf3rNEGky=kq?7WPPw6LZ1u`;8GMQ-B_d=dW z{(*^4p|2ESSFcJR?=kxtV52r%0d9pGDqFzQ1w3wh`&PP1ou zPDU*6g-J*dbx0@mTHgz+!ACvR%k(fG!|7cG!hF!AizcrFe7RtvJT&pB@;bpcPYMH! zChwF<9-47fc@xn_OJb16^UY=Y*q$JM*!;GGkA01F(b8wW*Npanl*c+pRW-@@yw@xi zJ9VWqvgaOA!t&^sX`oDg6TmR(B#qGAuJ(eD;|%L#Jbp5Luv3d>Man5+|Nr$*kR z^qLEVW9WFJflE8}s}}kp3;vM>FAFP-6YHf!sgri?^?-bSry6)IAp2a2FM z*s!jpVXHi6-3Z;bNm#kMd?UcFnjO@(6`_opu!+$~Q1%s48!Jx4sxIo4+d78;x#rSBImCueYc zA#GPPC+ua@382aNUbYxht7Z!|6(Okc~?Kb{^r!8BQm~n z0`g?~%-`u^E}nZhBoJTZ>fhz+=c;=Qx^AQ!n0(Uk7>Ra?fkJda_{Xt~liD0Rh`=il zwrApa-4}su*Tg3fVqowR;<3&m1U{J%hDa_U4112Fd?;oRVxXHzhyh?0;RU)a{8@gp z%f2=i+k3QA(a*yx9A&#zu2Z7iFif0o+oRBO7!LY~z&=5c^#~qm%O1nfwfY9ek7M zF`VSH+T16>_Z3M5uP7fttIfR<2@+*x$di5zxGB0qTlG?dhd|Q&@S8{Oz2NIW81>-{G9P~Ac=!jMU(dn@UdTF zKF(xwpNvu7G&DddPqu^M(nni$o=hBIwDh%`@UfgJkB_QMA8h2=Be}b_a86;&-|Teg2?*QBUZ(tW z{>{#Mlug7r^|P150WAH9i^WD>26kB|(neky7NN^~z=A($;L=7uWT8J|p&z!;pSI9D zE%cWx^kWu!mxbPAq4%2Te1ByAm?zrM7Xwz|S8d?QfYO~|E;%yOtJ}Z=AKn7qv{rs; zYuMw46})LJC!5d3OtDAI!rC=;V6T5c@KR4g0WH}0u0_F?G4!Q$VIH;!JFAOE8*{m~ z;1292{^(tBB$LCzv-RuA@zJ|(&GVdYmD;r>gM0GS{?#^J-jYFYGkxR2@;pMG13SeP z>=eIE{pelrY#Az1#Yy@e&i2+~ws*^&{-z38q+8-scl52!e_EWVPfK@9*wPhr+#ZmZ z-d5~awU4GQo&$6~=mNz=F~=hg zO6+%Oq>AAmFYxS-87S;n@Uy=nF6>zR6Lu_Y9bw0U=p`L^79r@92r)=ZCIo$&fpd%^ zy?_u(3JF0M;}3Aog_17bVbO_;xggNX7!JJLpf4muV_rlEI@>yNKI@F13ZM$(^jqbBn)GLxDO`mORmS^Cq(M%^!% zCysba0fnI!-VdkSXlH$QLc2r}iNY8CC(22f zTTF0_?iTQgZpz^2^LUpjuIx#MdxvTTk#SS-qb&*br@cd!p%6DBTskRl9Rj4Ew5P!* z`fP(y(yZ@LZ-Fmp@DKnM&iW3;yTq6#>7-vnfRs(zG4L_2bdu&rfZ2BDUdKL!Q6I~k z@>u5i_{li%DyeuTVtI!u0v~lqCuK}WfLZT$@KF!-GCZ2zR`7{23_NtvAB$-6SgEn3uNZtXzp~x4 zeyr`FCPsN3CVA*GqNcAiMtLEVywo$u^CHo)ylfN!Upmq51h(1;mFi%FD!0rVsD5#Ut6DG^Z%`^Pk^h#UuIb zD_J^4O!*n#X?YrI^XB^6mRe;-v{Ru!yYo=*mxU?P?^3=s1a~Tt`)0|&nu)m6*MKmf znH<-Icm_*Eq<%&Pakd}%J}c~Z5l@#-J6_ljhCa4A-RX4R?PtdSYQg26X(|7tg+5^5 zl5S&z5l)wHH*iVE%g+#cyoJuWLEY)`$64r^7WzdN`o$J}s)hdp3;yHqARVV%X5?ie z5|9iFdkpX?@N-<``}dy#Cm`%i1Ah|m639Dd;5Pw&2>fLOzY_2W{RI zy198{?FLeYyxHrla^Y;v6%Eae>uxA%Zmzvy>o9x~A!}q5ZQG``rp;;ke1R_2#4TqV zBsVs&l{Idyt=nK(ZaXcaz9c83ojFNdsyhQ`cpn{=lr?N!+uYdHvblMUDVe5Jo#BkJ z8HEM0AFgiG+5=+)@u|CO?7gkZ@xVUZDV(Nt)ihPy9N6VAI;vzXOWy%(`uiW1JGG|u zYJ2|rs=)R@$xi)T0;S#i0_P}7gI~?67c&_6-g+fxC{|;Zq<@P)=#6XRUNtx79g0(r zPDz{BwLPHh!<@uCzac~HY{Mx4{mtz-TPz~GB6zL1&reND?bhc!`nRLO9%STc zW3fV)lr|0f?-p&t%*VFsa#z>ffV**G`jj+fVp&gul5WhZWNF0R%9w6-pMsO&BU#v>)W;3fNl4JK-c?9 z&aw9ub)P@(xcXMR-*&vJ@8elYw{r2DA*HiCnC|#}D5d6gaCo#dZIsVK!c-Zeg>Mfmg3@OA7i7yuJ_mAtc z-S5|yX%hm)+VPOPwX*^zE(GKJ2mSUg+rCkO!;Ke+GO!=xX%~5=?rz(@q`<*OND%XK z$?0Cq*YTuK-xIrsy?Q7W~qdMcw$+3uoIgTphTzMD4FmObo_d zF-L=>^~xlpRnJ4JimS_0kFxZgUGD_+Q}t5Cb1_%T?ZyStIBD<7K(=;i;6DS0E7aaZ zrxS9j%N@sLt&Qupb>!Bm`*O9$x_1IB@dX!B@4P_e;5>1LNLS-^={Okyb(~h;kzZz7@#dnCfbkumt)`@ zUrFcKO8QhnudxP>_xU{H;Gac!v9T78@Hxa055+3NIX}*|^vemsUrLDdmJuSnoDlpA z2@$@C5aEjnvy3@KgfAzKd4m;%kh99b|A7$kzhdBP2))Lc1;}&*aqzDv1b!_c_-Tg| z-$DpI*Ab#nt|tWljf615zfOqoZxABhErbZal@Ny9ZG>Lq>;f2a-y{xsdkK;5Zxe!l zKOqYDenJ=(2MDu2qq)*Jz5HXDE5%s?qr_a-mq#VYyDHnvcU7WIv8~xq*TQCX=xxb{ zGGp7ZfqpsQh;$W3(S>$8tS;1p&;|Mkbm`v&r$x~v^M$r|4)Uez8W%;E%$HS{DPO)A z%P@S1Ky8#ytI;M!8CrFrjfye^eSVC((&aol&SV(2amX^na~iD-N383qD7s`BT6LMq zaKyTP5JeZBb5Vv?U0$OMK_5Xol;(aLbdx-J~Px;PFDtIJe|BWQzYrlYXoJeuN{5qEMVn}_N%5cQ(@ct<6P}bME)D`VnjzL#R zZ2iVE)yX4j^e%B*lwu6Gdu!e@Bjbucc75oobbY^zQk1diD`6w4ZK$nlR8-D)l@`p% z&r{+`aR6h(_UTIs3ukQFyrzC@lj2NvEs3{ZpeCzh9I0xWnqkj$OjFUbMn69RG=*a( zhEK(YwgOW@v3d1*X&asi+D|-ZfOZnsQpVGh<62%%q`tAOwW#1TKdM@~QdK+IjT69QS-uPhJN4NMkM80?>D ze+s)6HV4az_Mw;uMSo0@wBry(7$Ru4!Y&hbFKPfu96E_Z{0#0M&_r4c9@hIl6F-VY zxI6G4MG$t!;HyCZlQV8hM+idc~tNc3zOrpndk`IrEh$G4c z{*&N)&!j-6Da+uKIOm=x8nOtOKDs*mq-+s@f|WGl(!boo$2&$J5)t%&QpQrCqHYY@ zqd<732h+j2qdY>s7sxp9DovC4DvElljGC7FAvw z_{u<+E?W8h!XyumYgBnB!B;AU0Y;Noj0an$kIzK3`ltb4EbW_+qJ#8%^?L|Kf&R>+^9aMtSd<1=zJW_ZXR&%1d2F-h{y6|XFT!m2aV(SR zV_#$D}Ut?()}uu0IQ!%or&&GMSS7eE;G7T_o4%`7U)pX-gdvz_UX zUpUJ+)Zy&k%C)nBz@(uq!CJn8DL>{4B%R<13Iq+>)KdWOGK`7c?} zg2AP{4cx6WV~D>&*@ zmruX$be#P!y6rHX&zbIYI@>Tz@i0B|Jm~aM;RNXTXakq}GA#59E%b{lc(#RqFCHM> z>GHp2;8OlR3;uwG|3M4=2@Cx&8@X`0{0h5tnh{S_1aE~Bn6%;2@d zrECUX0spJ`alLst@ErV_(V-Bh|4Ed;1CaRtfbVIP|9b}i>wwQ88#4a)fbT?py$1g` zfd2&giw%4uaOuzm>u2^F0T^0_+#yW5d0z{0x4}z59Ad+cxU#WfwXG$xls+8emzuD(q+vx1{tdJAY!z3s;hN33(;=|&47~b!b}XEYn{b`^CfxGf z(hv)K{kk(~ty?RPh%x7qWpPDqb0f5vmcwPPP&);)W}j)x|BU?ESO=dmyNLhK$C~)d zfzer|S6`J;y7G6=B)+g9GxRGZ%QyJcSgduHiWT#!I4yVmPHm6o+LfU>vh;PqH9d-3 zUt=sET$#VL`|VKPVNZ@HTglSTub&vN4m_(Vd#jQ9*F%nWn^?=dxJ&7{)j#D8#jEt* zs;&-Yd9Mn2Jqvx6A+Oh$;mAF4T;2Dfd$p$DMZgvHyVL43unLHi_5V|>8gn&~;rUu} zH&+Oq12=Q^IZt0JC3Qh?^)h}>urm$on_@-WgLP8yT~|KXQKNjAvaYFux!~GqU)3Fl zTeY`BUS$_=AKP`m_L^JW?F*Cy+&g_iHLFu;^Sh7BmB^CdpYmPeqr9DSo5jtPIx_@O)B$Wff)?2>W0K7IV%*F&DeuZL0( z>Sd?j_OMIK!5Q$1QPRcE+#1LJU1hD_G0ych%Dzjrd0Jqlb6*_vi8bBtsJ#g;pEi2d z^!VwjXV&{zb#)EwxstTN3;7r7DJ>c7@t{<2Uj$2!w0-X?lWx}RqF%1-x-R2~z2h#L z{6@Z-=iKRjErfUO-W@h&4{ktHkr(?y-h!s;vKafny6V$-%6^t1-xYl13up;>xD)OA zMT7k%I0b*pYiX~(tKR>5D5X7a|1zzr=ia3HwAVw*LACdr${#Z*1u+V)C_UsxnhJlJ zHu1tmgHKLCZ5G=1+U|pduXXs{UG{ytR$IsX^u%75`hd8hZC00~qfD#nQ{$EX(FxA) zI39RAl+x-DxtZJ*->=5M(3^hI)HkYn;ytZycWwV=3xUs^keJ}WwXc-Fbit}Nm-zWERB!Dv?zj^-PBiQTWIHq{tPxE1werC6F zzpX>bO4pLaZ4bPaL{CTgpl#C6cy`ov|D38!@|8P<2BwgE2*!xIupfIYm23S;-M0Oz z_vQB$CsRQllnzdfdNFUVrtjzAeS6%SlZ0CU^F9%Cu#^XHOkUZ&NLy&!UxC{!_LTzDcl9hza||3TLpjV_#a$Zns!;}vy=3s1m(PM~ z?5-)4Wx(A%ECaEZ#WApFi!yP1H+SeTRzljs;N+Ev*YZfJG7-BTge>mP(R0dgp7w0v z?wrJK6?uKZjogY`xMfbKXuOs01$Q3$9)#iRC+kiXl)<7nEwCPGo(t++wf&Oys{*Ci zi;=NY*~?U52S>%~IhEyOxRay~ZPEcg-jPw%?w{PHJdmpmW;`v*2z^tct!qIrB`+B@ z$ogaaU#9&-xZPHkCwA$){=rQOOXMZA){35ZB}3F*9Qw3_DnlH~*lx80dt`D}W~}Z1 zxVZCurBaVs75oXx@*~7#dZ+<;yi>IKf(qPBqK_clfwW623A&vnfw)~Y>lX$Z@!TdQ zJ`-}cC!(LR?Wr0()g0eH+V!t^Zfrf@ws|#WkN(YBWTe3@JIk)={y%Q@TVK|SxW3|q%K>>9sX%==%df?LP_4c)7t$Lj;Z&%dtGCu7`LkMsk=MvCSyeT!;le$ z<*4stu_;B}&ViIG#Q4(xkP1rPCEZGPRnNZoTs-&j-MHy7Z*?fU+8MlX_O(9V`M5k| zVL3*x{horcqMYv*y#mX_7rZbZH|Q)!udohfEP93A*a5>j<4J6y_22W*Y;6!$>4#sy z=)}EK)XxzrRD~Ycj=tBP5okMX>l+>C+G}6$Tfcn5gk31Xc;#DH$H({H>i!-3&`Zk( z-Oh3G%4GFkNWav!J4Mrb#4Eczb3B*fDeiS8{PAhMKYhz6qXj6V<=O&cgt|LzRr#N~ zsC|C?t+Q_uy)^Hf)Or$?a@@y>RJ#1ZTURQ%vyO4Jw?8WKDDo^NdLhyNxLKmB>$_e|(p6zx}alO>dufr&SF8(CZTA@9e)7d(T8IbbmLEvFD^K zlMqw%8!Q*se!XPoY7ZOtUdD^@8EX`FN1W5;j!#HTx?t33Px6?tDdWa}AvG<1LdJ!e zoGyb?u?MC?-|qq}yjuvvMA&b~)*tV+4}qs!wZRz*T2UjGM6~g$2B<8=MzG%pYT#+{td)R z;?Tc<5R=dg2@$`F5b>%BF&VLp5aCx4Vv*xYLQDo-O$a?}2*F=R2)+iwIr=;m^<7IG z`Zf?^B5fn#EWC3PBK|f)#M@4YcwZw#yc-EoNM9!e|ILKZa|>aXv4;uy+G*gs2qEVl z18*lpI=^M$_Yp$Q{RV!35asxgfj>+L{ogb2M+xyl`XphFqWlvf^!>oVpCyF+7YzJI zgphyKz&i;c?-_T%iw+H1ewCCt~?P8t3%aqv4z2qof&gebpuLVVv2!gGwXS4jWg47{5V;r~f^ zuD%9K++ovk>HwIoG{T9Hi3#B^^hfv(yepp@>4q9~daxi`DE zIJYWq(V+d|lWBHyd}vSN`@uhKt-cs<(dhAsEmyroXd%9S)E9kk(l?!hGn3WN(~bP0 zQue5y=s!gM;NS1~UOBn=B38@Oc@Ry|s4|Y^S&Y9YG%$J8+x)ZkLJw+rmJ`_r}S^N4eI@_lxiQO}3dXC&{;iY$w_R{QJ=s^s;=;LR&DG2iZ}SC;a;z-=%|xC5;ab`|l# zzaR1GW9`@!`IBuO%zN~mN?V7RYpHHxW2qkB1^9fPJKcA=HamNqSCDnn9G6lzgBIh$ zUVA;R^Ltj6csDKkOmkdHz3g{6UY4R9Wj!&+r__@f7V`!HLT?A3+WH>P$C547i&R?mr;} zf3b%f@IB(t7hofcp!X4iE{E`Js5}VAV80jOBp>usfC0d(=#IX3G2t25BTk5LdkK-= zmkE*UHwnjRT9*O+4&7hu`9`?$#IulpLZssc1Lxjv=HowzBOiYtMEU#|A?Q9KL?1HJ z2?#pg0m^(`M~Jq!-f-VYi1>FK_#r~@YbDG>ITC^&-+Uv#(_MgP;w&K{_$)Q>6@=h( z7oi{g0GYm5iK88SLI}RYFeow|kk3WF&6wQv{vU{DX92hQ}p1UTtJd=J0?pw|mJ@XsLx z|H*{lA0a#s`a?ntq$>^oI}HE*gov*dko^7%NPeAkhu+DwM_)cu$Z91vl;CrTz4<6+ z(Wp^e$eb=iaBn`6C-kgfC-kamgkJ)0!jVGNhC~Y%VqSx+2|XqIT{>PzfL0li|+)RnXVmlqKpk%$@(hbG7Z8DM3M(_X^)uboS@_WCuyWL1P4(E z43B(#&{-%brkC#I$GBORG7PL5_iCb=#EtYb)7=9)#vzTQLlfu`Z!_o^5938MO&Txn zxS0umX_E2tqvGX*i2PW0ljUO;=&bOoQ~2?_B;)s#MSj%x$n>%8B;%J4IxFd`R`{Wa zlJbjLH8-w_z&W%~Rn_)Q0$6@GUp{Kll<_bBMX@Ruf8 ze%lp(c_2Z>%$pBI8oeh=m+8Nb^=XC-|vDEwxn;P-(=euWq`WcoNBCQIM7 zptCYw?o;^9Nx`ofbXM}4H8zpHxhePsL1%^E7KLA_!Vld9=M~ie!ZdGSN= z1w{d!y6>}7oa@8H&rS_t>QbJavU1-fw(T#waqXJ&>npU0P~|LHS6Q(nT2a0n2OEe_ zTwQY$E}&bXO)|=3=|;zc5*6BfALS1EGwhA{N%~$+GL)9rEQ|8uJ}VawCWz%pj}+GeCW!mIYcN6D$5n&+)r)cR zl!qw#b8rG>WH#ehLMP?dw1-z?TTd0X6v1RZi5-Y|UsrQF%Zkgi+~>+RmN_=c-HDOT zNyXxg1F=^z(lx%kdZzRXbso1>&*W=k!y~@P_oB(!(yo4kZ$jq}dTaoW%W9?58Fn@l1b!|MWY?MgPS>=u<_e z7@mPeD?>g+etmSbW^M(U;AN0gHoQX#D#{T!KEEEf;rA3FJQ-H%BQjyX0Y8=BQ=s_> zZqi78{{jbTr{52e;c=2k@yj*rEDxH4u;l4h@n7U0HcVp$KaqdfdB?|kL81SX;V(Dn zq*pZ(D|ygO+AlKE@jX?DVsRtWJ`FDFIK%Uh9RC;}zbW|&PlX;j2Rqz*qMtp z3?QG^*vDo*36XM`3II|cI|+^)a|3`uK;E~skr3(m10mAmMZ$SslU1`Egy?4DhGQGV znYfW{)PTXyBmyY;%~b64o(SgSXfceWlYO)7 zB^H8?{eUzwO_#ud&JvFzVN8=W(mn|eN^osO5;~4!Djml_jvdlSKd91rj0v@%3&4%( z;AddGgdG3jRSh6aBaq(4Hu6=+7%vzE;YNNe3(0R%;rRu|W6ol#)z_SC^7#SFbFv5Z z!j8|$MzADO&dCPsK8w#bIYYUKJ@|mS!ERakfrJA~E@7;^Yu66)1PlFMijU(gbbiMS z9H(Kl=L~w%aExk<)9Pc)9tGzZwNAk~2F*9&UpC?Am~bo+#Z8JaO+RbCq__8%lfJa9 zUSl6Wr{BwbaIH9*-^-2o>H&9oM}5z0?LX6CnYbA~J^@Xf%1<#?V(NFrEo*8jZkkiI zbanaaTeL7Na9qBkYUz@76|2`&ty+m=Bj>&U5l_>lZ{R4I{#Li9ZEHL|l3BMp8W4A3 ze>;k^W;_FW;j}3J7jfJf6d6`OIijD-*3XlUEY!{_Et%MI3qp}1BU|^)$Sy4zD^3*B zHac$0Zh1O-LnPC$)0UPDZRv{YA%5Z|CCO{C(Fyt7mtW6gW8s-kg>#-^%-5B;!CS&hBY>nY)mqz@?F0#yB`!oP-OGsnSz_ zfRzbjp}QJ~GJF1U1_>u=Q1wN-Kqn=-35-Fazrxrf#zqLjVr;}eAzNh{cT=O%a}AJ# z1?M3Q1ogd8IAj6X&>y0ga}KuIGX{akWAoTO4o?R4zBZfRrVX+W`SiGEUl6b_D6lV> zY+o?NzM#;);C%ansrCgI*cTMp7ff?3CYA|`8Zk( zBmGz>XlGraIUR{Tu3N=_nWn3N$uRU7fdny4(nxy*4k}$1JUAbgM*4-|AljwjQ3N{5 z8;p;|OMa9~3h4W@NSeQ`B`}>strcAah|79Ugn7I5moGBOb zpVSnXS~KuO z5)yZnk;bO)eiNjump0`q&Jws@s3a&7c%qXF3fvoio5~M-C~6Py@}(Jp-%!jTE>1)) z>Vmwdj5Mqpf1$-N#D6RiKy6r`FE=icI;mBVV`Fe0eLlwY5a#;}(NF#L+y7F!@j%Ir=l;3ldAmFBzqYKa z{M|2(|LUR}U%6n#&n_8~)pXm}yS{qih{d<>*}mfOS0;pBu6*3L;Del7*WN#K*p6v; z9y{{Hd9&L+TJhoE`~UL9<~QEh@ZqhtyEdQq)w$*AbMsa#-uj*IeZ2RIdtARf_~mbp z`^uGNuRZj_(A%f|_MxBc`M(wWBHz*O-Cn=pFAaI+8-M-f(?<@uMSJX_Yd)>G<%bs? z82+ep@SdOEKWFT_U;o_|umANMZ~r**>*I~9E}vC)X5pr{epmmC5s!TJ;U(LZrjgPb zq_5F%iYX8o_lZx2wIBD1_j#K*&*if3x1%!<<0%?A`x!fhXF|wh!XJZ}@E1Zj+|fA+ zcT5{@<1d{#80=RM9k|qWV_qa1G`%K19I2%8e zANR4#H|^jhi}!@Pa7Tf`I1(5}#w*8K8Fv_Ten|w#cxlXZ%i%Fg_Y(h;(NXqcA1+NY zy7%A_lth5Z=<<*d7Mn@TmV}>-6j%Q|SLYlbJQH|bQ_(M)$lq2nAS89xf) zk{|VPk`A&|QGaBqf@xDMuh*0@gNiIQn7K@%OG_qQamPbn5|+OD^V#IA3KnSGc(f%w zaF=#%4?H2qFbLOgBJfX;=yK7RI6s}9{h@AjJfZ*6@q~`pEp*tV&BKp!&^v(SPoCVX z@D$)!{MZ(V*8xt!FKpnIfL~Sc3t|5`ew6R!UI$o(K{qPbe^j-VB4WtVTJB#+{cd7h zvXP1}8LXGFJ5Jl@u7@~fADbR5spR_cC}lDUES{derHh*W-b|@~7xn*}=wW_yE!LJH zSM0wG=a^tJpS(NjD4P@ASQak(P4xM)v~SqryDMgP{u28lHk8R76(yb5LLdT!W2XC>MgIxf*-@K4MjFmQ;m0|@(L{uAq+=upKNfJ#4-?&v_dRzc<5N$QEn z1|5xNV?65lxDiGtaDps?hRQVZO|f40Xdo}_i z_#A>CA=kx_B(zA~JOMh&gVIQTtQ#u7Ong{B+{lmLnCT-w+GQA6HOe@NnQ_98G%CL$ z(B;F8{8+anze$Bt3;HvbPbs{>SVrr6uOioBVd8p`9HzXFv7BRf>YW*?3H{&+_i@ zD+Q+iqg=r@Dh>55VSWt2ET4+~JW>?Bh z%S+~5A(*AyHK|`c-7l>{d_?XVjS*R5;m*U@xhS#X&bNxIxnD)YIviHzI_KG<_j@-s z&OYmbw!7TeVR9pOpcG;+%7wOV-##PMdDf-a9dZpvXzWJu!oE1K*&drFR^MzLvt6Yn z_Lj>#x0VH47nRIv(f6WowQcl)lFr`tpx9excQ$99Bkm0iv}hAU%}(5885R7T2D}_A zbM_X551t0DqbzXswiI`LO}zB1?`&~u<3tQ;&1r2e4`dFz7T>dy-KyoVzKkc=K16Kys9j3yb^b$!U5GuW>=TeSA z=Pmks$Sp#SLE{y23>vy<1L%M_mQaDoxf>VRgdBrSsH2HPxXC4i;}}8&673B193R*? z&mlCz+Z;qb$8|p=e>IR9U$+Y zTznym`NKM@ey7*6{_{H2KRB;{jnj~4PVK2Z<(m}Ai-RN{$% zJS(~akoPX!L5O<1g%EnWM+s5spCLrOet{5lZxVv;4}_rOyCtOK{G5E30+R1ay0enN z@V#CqAsQ9O8`c}PGa-u;Qs~w9P3vp0AQDXkL=4A|B1T5zJF$I<_KNbeYQ6M0`8gMnvHb7}e2V~jGvt`8DR^&W} zcHOwdeb$^uaebM46^o=7AnWfq1?LzhL$GK zQ-P_3D5)jOqBkzNer@^c9AgF_gRfG<$SwakVxx{j}YDmy)(zcNtg+gs&mt4;T{ zY4+Bt2g)~wiVoN#e=7fZhc;wz3-6t8>guYV*|pwA$=hp4-VcPn)^c0xuR&l9lTYsK07%2v2f!*{?_>l-ZsF?F14=vp+B54?7l@)oZlWDsf%c5YiA8> zb=D7y{W^O~=<3LX1MhTa*6nTcqz#YpC5xgk=PvhV&kNs_Q&Mu?tM>Z*!Q(T$)%Msq zz7YOzsJ7Q@{#U9!58Jl68XUXa^&Z5dHJ&jl{;tN-d$9|@a%o-Yx6SkAn<2-vtK1!a z4`x;Y4Q~&0RZolTIIQ~mr-nNrg8U<^60a4A7j(XrJ-h3XG1|D_cJ3b&!A|?Xh?iH4 z8}>zQiO&yC++i;|GEtAvX|S*1KlUa3NBM*u73(NF8rC@~=OFTk0p%ptSw}mOiQc6% zUB=*^dya+F^;7~9Ut!=|0J+!xpaF&ag>>a1BR-@zWI!Q*v4fQR+R$m^&&Vh(eVdga z5n&8c_EYPXV501RGmY#wrFj&VCj1yy_RSpQt~1;KgjoRwH4*`o{N^imdbh%394&^C zbW+A~8}58ZI-yHRq^TJGG7L#;kubgM)dNa=u;AN69V z-SMF}w)8`7RGB7rmG6yWrK{Lm;C(DOdT-gB&V^+>Cv|DpuDs$bZ47$vyb#V)6+Wvc zfPHqRUVlUd7v+tHCB6n4!b#4JQ?4Dc-?t;K*?|2y!xRNQns?l=-mi{hi8@mTH<>kh z@58SSKZa%g*q&LJC{L;Uicko>@w*IkiTbE%j{q45H)*6F$1&Pv+}uaVc%+g2i0orz z&2I%A>#{U5{FmV%dDCwZJR}d|(ta-ND&4i9V;?Dv^gA04YM-?nbXjm?eC+$kkC1&n z%B31WnAkNB_`Y zxW4ihn?;^hk`%2as8rD1ZmHB}5{~dmP^p#gsEL*#} zqGWxK9y79f)lKF;^Qwx~Rh74x`%K*xy{6$kP`#$6?TI4sis=^p=2_9SUBx*r^qYT) zey{9ccV^SW=snMgyy}H~zxLg-{~QJRey!{1w_V?>TA7v6w!wC=JE!TP@=ClRR~gar z|5~1PKs(1Bm+&K9du$&+``kzAw)8#4wd`%t)7l)h=xJ@Adbce7R2xz@JYpLo-@UUP zs}uVHMq)p}Be{4X5--1L3n*FJJMO@1VO`Z9KfAYTALk`!m7K9R`u%dfXSR3lSsLm} z$BhtO)k7m6EB$d68x9Q`qWGq#xIf;AsK03a@ol0&^nbFRoBQJ@;9;ddej9XF`eW`t zXM2%Gein0o{0ux~A524vp>EdfUY-g z;%5(%^v6>s%cH7&%dQVHVT$aU%^ENCGXJx(>tQ4#VTNe$_Q2CjxX*;AoA3-1K1gF7 zOc<95cbjmJ3HNGm^a!8O_K>FonxJ36KS7dMdmjORdH)b;bv!Yi=y;-*>bU-qNbkpw zXC1y{FxSTypZ3)rc)B*f2cDsw+XEk@4FXOl%230Q-cMkchV%cU5&@)6>IDo&KxaJpt@m2*y+~-#i|=li8=#XV7}_+ zfLk!GbCtSRGkmL5RK@te{^IJ}p`)UAHExNFhz#H5x-YZ-)lsi{?c0A-W!wHhM<#Wf z_OvwUO6~Tx=Nt>V3o@5P?G4(tK@r=oYew4Yca5|+T%P^v==Ae{2q~+ivpX>CHCJR` z)gN-st-{OJS)9K*>e{LvF0Y4wcI5qXM=UXmE$MvA_Eo$NUb4I%W1pq4SaK1e_M24)$g+# zDV2@8>x?0-i^scKYz^{N-1iTAIyR&W?I_-B?yAmd{c*Y7c&YgJ*@##Betu3%sOynZ zEqB8OmyDdz^;+ibBRS8;o2u!UYmd>+rk->r^rTl)|7>^dW|$x)cd(OR&aj;`% z>7yQ?5MZ?u7VLy6!+(foakCFLKO7jA?V9DladQ!VDnH77MHhgmk&C>NRj?8S^8#yj^!myGCH0|u|mhQ!dB?k zC!vG0_%>2%+5!j4G1ACyZ=NRf1S zAKQvqZ^QQ|Sl6VH{L2kV??TeC z?I)v~pwMA^OPr4RQS&h!bWyl5eUywPze$A`Oeu=bVxVK6I<0W(+Qc5XH-4XxPM;>; z5N5ymC;YgE{wsqw0p}avGvQw|;a8gQ3ltnfndUd)MskEJ{dK8&&6*XZ<*UnYx^!ht z#r3PJYHq>dq*XN)%WC4@#w=t87U9cRtLqubCG}L3i-e?}iYg(gr=m(o>M5xpsp}IJ z%JVYSDOHVqPA&|UWKX(8qT>^XUg;9a?t`w6DMo)bPMh~Jd@^%OV=Qu7gC}xP)uB=I zjyC(As`7O>(zLdECpDj*x@XG&S@kF+?g^1k$~}t29qJr%^PE=CZq4tmbL?>KJUup| zVfgN0-*ML2ci48~d7QCDLQ)_oUM(EVAbgC zR!{vEkx;}TR+@A>rS)%QN4oxf9OU11KgnwBc=wWw=EjcEmpH|(N3*&DncmiivG&Au zC%4!Ija}VB?^zJh@8_F$wBA+}Ier+j$=OOnfVICkLvu|_>`ivek}uZN35a1ZScvw8 zK}n3^7<4eCi9wg+50!6h>%90@v^~hMVm!v6Bjg_-@DdBWAk{wiJ;oSYiW!gS)@08> zDD82}LA-6{6%Rij;G=Q9Jp_wj$RzX4J))vNMdm3p@XYyGLiqPPzSmANzKapDah9HP zbwAG1k9PKPnx5l7&(ZVS#?RGbb4d>zn-6;6C=iLSL^#e99w0&*Yo8?0OW`6A!`Ei~j`LUms{LX)o1BU8@|(#0w{uzHgwgrUGjKUqxyt1K6_bCZ$^Uwj|3;Jl zCX@fYCjW1l{CAuDzhm;}n}urn|IOt86O;c>P5#fA{GT=X|I+0DE0aIpLR8~_-Q@qC z$^S1V|4x(tM<)No!mIv$Y;5>2^7~{MxNLcYO#UNH{%4r{d3HcII{$MNf1gobSVuT_ zY)@1kAz!{`!k;(ckC||}_Qv?wZ*DR9SDWy16Mne~|FQ`mX~K``8592*-#aG!Sq0}@ zc()1vstLc^gkNC7{R+gc>DweNZR)ZU5FE2^XVn+FjWtT5W5r-fsP#Ki3T)yh2B`cTBtXNsG8fi7s zCe|Ot{+tv$8cCFL`wj^hWn^u&!j~>HR;^rPC=*slDud+m@|q}?@2V-aI3XD&>VBr89Bfu%-?s@k&ZjHRrt(AHrPj)|n?^Nxo3zt*xa-nm?)socoSaXKc?+D|bl*XB&X}*m z>&Vy<)G~Fu?aaS_quU#}W4~+Xke%92+s=%Ajon)7kUdya+vnQiY@6ZCjExIxySMJ& zlRYl%4LI7|8Q!*H_quTH{@vjpXJ>Q-GHSESN~TxsJ8(xNqr zQ8?=Uy}Y~XF6b!Sk>gku%zPX?!mgNahhq;{4YdY$hc`XF&Ffy5Rg;x=|3l%y9bWg^ z>=E}p8@)IR%8oRryX{W*GiCpb2BsLgjx^|BU)2(m=?e?~?9X_tL8;0y|0vr=2-Tn>7HfY>!>%6Q} zb7h9%qXjnBY_!FG3t#L8b7cv)#*Ij`*11vmZ%T_1Rs(u<-%Y;*-o9x>Ov@D%ciemj zH6|;Uzt}yY$-N6}gF~A-Z9|WihdVD8E1z2;?v6a$@NKAHT6#mU(^FuN>N*-*o7d?) zRu|@~=7K`(HXBnH3by}X1Nrf{w#5+xzb}K|xwa@mj-zWvw!E2|Sg_N+2rH3`f=9Jt z?>2AjNVzi>Jn9P$tJ7(NU3Q_{amH{Pb@)f!IU-H;;}5kuj$hmYUN~i*Rz9n9ig3-y z)??5LnmQc?I=wSaKTc?a=$eak+M=}eOq(}`*v~yuuKVcgy*f|2@b^Y{W}IKJef)+& zG3Oqw!|NRs^9J;qB|`-}UH-@RH+A}|b#DA0Jn9x_fslXgzskM!?=N-aCVU4OW#{Fh zcTR0nr)$2?pNI)@$K1I`mf~B9I}Z{*R|{PnzdYUeyIXK_))(V@yoQOev_ zte4&Ig`3xZ1bLj(Ib3@mF%2nh>ayQVj=#@FysUEtI+j_FbOyX*p6eVUV%0;Bh@n?O z9qX#Gt^bW@(SdO1KgtHbj@;~>*Pc1_GLajdvgsrAL{HD?d^z*?U4N^7E?YZ$CiHw8 zT8ldeDg0)mjum$faW{1hiX17Q_woEPJ@$$PccL)xyP^|}sIx9fh? zT)LaN>hC<}p3imv(XFS)2JcE2wS=)}WW#46(@@g2n0x8Rj65)->wzFjQ`7u;BQNWE z5_divtF~qHwsyPrC2{L|e)KudCkLx%KHHs>iB{=v>hfhG#sk`zrcN)?=9ppMZri5q z7`|&p)TX!f0~z>AX*UPETw|+e4#QWRg0EQ2+CiT#JHDT*z{vH1;&z+OR(5qn?EgRD zsCSMLHSqxZiHz)~u8&sNg{o(!8+F&C*WI`;dl7LPhoJrWWMcWzrjMF1Isbc$YIny} z%-I8TqbG6Iv#q?pRNgWHrR(5Yn_c@XKPqf%ZQ?mI2G>yuPs-T{oDvuUC`5T7dt%Nj z#QE{M{zg03&<{^A^up)q`crO9!1e|)$;Y+>aoP4*!pWL;HsKWUyuGGDkvEC>`T9L} zc#J?3GVpYqS*QC&`d#ac6jpJe#SB7BO~VF0n-K9{MwqT?a|n^n1%zOJ1tF9^3kl&a z^e00!@h%|oa=I7b>^mWZ_GN@{uOfu|4TQt>Hv;K?GjZrlR}%tXPl$ZoLI_3Rt%Pu| zB}9HU5N7M|)zEzlaTLy0Lg3#bME>gtN8#-SLb!jM5QP^raIw!XSJS?0;NK@ip+02b z)WvFNY1)qr{Bc4Q_7eu41^Bt^=b?Dv_pzd%#~mQLetwg0us_*j1E_bLzVd7g)XSRP zVd&>kKFGRwYoOop{pb|O_wDpko4-GvviLH^`pPzU-}y@$knd;2=Q&mJ<%s-!&qDst z?+ifwG~%<6zk!KQzZ0k4LjKTy4nY2l_$=gaVB*v7#QASm-}MFK!2sk>k8hKO{0&Te z!$keO&%*b^xHbU!Gvc$5zk!KQA0J+^@cl484?zC(_};fro&yt~TVJ0}>$`qJ-WY)V z>G8Fl;`pq5zk$r3mG3t&@#$|RJ#L|XLM|MD@2AK2mWBE`F!AaA+4n8P2l;jY@@K?n zp??{e_;h)q#X|lduMa@}^!PSgXnz9}pI)A?TgV^g9RrX*J-#1#`|i&MGQPVll;=Rk z_fre)9rLyUE6+b#_NiV&jvES zUs?Em0~y~RPjP%NT4?VBnZMU8=nDoizJHvu`1JmIn}za(vSk3;pB~?1r#Qa1EcDmV zn+;h0{?kHxADH;E#Qfn|3;h}NfCG>}J-+|8(B4zTcarz$K=SMT7PITHx5PIF`dC8f zW49ARuli#`C_ncT`mxWGa0K>-5<+kNAB5vH?PJ1ByirLQzzPR+jeM&UZ&GN!Vc73X zh(gRE%)lZCAvT*$CM>}DBf@;>r3n!~?^p3*6JseM&f;A~h;%F_L^_reA{{FTk&e}b zWAJ7uA<}UdA<}UVA<|Jth;-~EL^^o?7t^tq5b1b^5cDq-o~LQA5+Yx30#3RRcjp2I z0FTmr3eJcSBEC%MY?u`u~jZbgT~&B7UCb zWBh+L+`9?K@6>g3kkl6QNHh1pgNZ&&B&JfRm=7J^=;*57Hgs-Xui0zY<=A@+QQ(MkW;6zCx@w z0FFldUniUdJwGA%K4L(z4-NT#ia5&ec|v@TRziFyP2OFMCuHLW&e&Fky?QXvnWIR= zS_z!Q+6aP*wGeoTg&QPKta(5^E7mwr&BWS9Iw9tes9s|20_r%iX2Cv$YZOpliM0t- zQ?a>tDB)P+jKEpOS`hjGt7a1jMVgHOC?3mi*|s7e!(vH5{9t#Z0E40sNyWW$y15EKhM~(W6qxu1x_8_jG11Kd z-Omgf0?8u;yZAPSpBDwsed>&l(UUj7A*xM046Ir+3IRRtd3 z^wlZ+Fw`aG_mo9`T)&m+V>?Oqee*$QC4JQjKMZY2`Nb^qYgPF9Q}FZRV_8XGDd=Q= z$E4u5-Xgyyg0|$!?0YN%ot6CVRrrx_GJY>vy1)a<<<(*{x!Fr4QniPKF6#R}@P_bU8mrQr9HMShvk_saCmPQkATbXL+=tMHqXg5N%i{Mr?Mb5rok@>@$^ z8R%qwOH=UMVv%37!f!zee%%)N1#=VWTbP1h6m(X;N29{;sucVVS>)%3kRi)&Q3`&u zKxZX=bqc@5Dfm5Qkss%(GJV&k;Fk|NE9t9N_+6KRU(6!ER)t?#3Vz-^Yw0Tmoy_mj z6#Uj(6_|RVw_@eR3XO4Is=S(6K&AV>2w6mh_mfHi8cC%8B`< z3w}=gy!g>B!@#QTMWmQA#EtYLROj7KfUXX1U@7*4N`5$BIxP@CUE23OIt5dv8svSS zFP(*q!^H2=(cft)UU2!u@|v2}RZH=*$QrHB*Rgp(Y{{ynm21~5!`Z3jODfk^FIiJ@ z{Y@1sYxKaYYjFKv#R_fWnwr%$ZsNXtzrfw%js}wOTk<_hG#_Df+#BbG>Ii>)*~Gmn>iM=W z+6lNM7e+6i$V(b6J_Lhv+nN98>h(=i25Xr^YPF0ZnS*P`XAaIx&(sQQX1-H9+~L%Q z1TRLpWNM=|_t4CsPXi6~lv>U6e}1-hN(RG?&m58oC19rZw+nCf)oLE>Bx)LOPjf(F z2)AFZxEF3Ny9587b{BjcE@zYGbAoD$18)xUV-!!vKjU5t&H?&yuSFlXT9A9+=0=d{ zO-iRN1X!yCll5&G+}O^gc@&mr{1}#f2s4w3-!=HD{CKC{i*S=h@}oQ=?er@KbIx(4 zk$wempk2ltg@yH98c~Qq%yhM&^GhPYWORE$r}lNp=$^1h$90svUgFJ#o6HlvKLDMK zi@3ByW!Hm_{k3W&4?>i4d<-C6Z)3ou!lHtH-Dy@h*>Yd}fj$_-`{L7?@-O&V|M9W_ zMWMR2vwPqi2@}T3S^uF3pJ1WiLzWe906M>H1Ls-tzk@yLNyD?=?jVbp3IrG4w?#${7qpt1R_`%IziyrKD?#0R8FL`!6(h+n%6LP*fKRmSC zmh&5r{UA^JUeN06@YrAVzN*nP%R-2diz+=~S~T{i0HW$v~+oX4Y& z!+lERA7zE{)3w2_Tg%73ixzkPRqLgTKi77 z*0gm$PtEQQgW5fA16^!;cxHBYxH9}pxK$c%nUm@APPez|fi|CA_j_oAwr5J%wr5Ya zz2T#*HDSKN@aGL$gQIQkU|YkUu)SeTI6E9D*y`2VHb6v0I&8TcS1fnOhDJ)oduceQ zShtmDJ;mADi~T&`hcf6|d=72SdS}N7&0Y6?Ilh6mAYzN^X901yuzOy+!#Le|Z?=AJ zk7wb6TG`W=byb%BzUz4PhHQL=$r|rRTg`XSVy!lu;d9MDL&PFOofE|g!Myw^-`m;h zu^kM0e6KISOV0ZF)Z(t6X5O1kZfjdLd0y{Rp4Y=$ZCyNrcWDd0U{pWZhkW2ftv6SH z-^bSGPGc@`))!|&gPjil`{Kmx)-cZFmeGf9Tf24H za5#&&$B@V&jc3le?RKZl zYxmhRY=dnhP{iW>KNRdn*tv)09zqDs4-%qI?I%PiF(f%_a~!6k^U7 zzNz5If-qmhe?%8IFThp`Pljb1q`ZqPovG-Z9=!B&W;H*}R+-#W5d z^aU{Sd6}OnPdP8M@&e?kyN~TdS(qXlKCS0lJ8l#1G2vblo~FImgCDzCo?b3B~2o@)2r1s#Nz)|IgfT-LJ>7tJkba@jPkinl*jA zsv`+{x$#;&a2n^(%T?DVg3s}e>+X5A@!NUsX>>=k8`AGTM!WCN`mTM?ug*9ydVP+k4ln&x51NX1{;IX3_op4gEijlR~|?)0`= z%~6NdcE2cZJgR*I=${(Z>4r`F7aqhDWrW zzR2nIL2;Llm_gzFnY+Vvp$l8eva@!%>TD6k53@b`O~9Q^i;PR;PqCxDIKt?R3YS@YU+hH8}I7Zr)Bq&ZC-{?#IL8H5>8P z_tlZoR=%CHc)Yvi+{k$2P4K(J|0Z6cAsy#;GrB5^r?q+@GaETOnV|xm(P~^)foscroX? z@YIp(Mz;C2f1FlvY3IG=m_+STtO;dX zJN7oRUdQiI$Aqj0j!N1C2RDgRKAwci&w3mH+z-ez9e*N3`#4UBMv#RD85ba3Jui@`U<77PffQ%;s$a(TYz%R=E?3^%g+RDCx>z%UY@jt)$f>6ktm zGacU_vO;&QMY>Hqgm55tsG_u&Z>npzEz%=7LV0!|elIHQbngPOZof z-QWrLnrFeWx4Ha9pjG4Lz1$(VNhAHH!9k68J?Iz@9bon46 zKYo{F`DnMuuLy~i{5W0)M8D zvrd^l+GU-9RVza!)@P-}5`Ls1e`%tIOhJB>JtRNqE~Z|fDzs7`@oA8JUzrck1 zO}LUgMOShXcbngIePw~6a1obX*c%swANmI^oeTNz#ipMZO;#{jpJyY!?)A1<4x#M-t5i{o{`1<0?xWOyK{oS>COu1y9R#KofB{xT9g~1 z5%D(W?B=e3hVaOSSGw~WL!En1e=DcKo8GpGTAPNEv2fS0^j~Coc6g^a@q%vpj_>DR z(&GHCHg?bs55nR8+lVhRXkQkz9Hl4dPFA%%4V?_$$~_ye?k=()u*aH&cE;IakBzLa z9la%#{u*stLb(TAF;D&0oGrK+J%9Z(`QwECgF28=E!x@Fg&)EV<9|Ct8^?Fae%^|d zKo8<+u{StlBO~4b>Fy4{)I$>z>DoWEyOlnFX!*loSH1qWaQ^zc!*+M(>vZSO6X!ms z>noXEXDkpQK5qH=usi0hw>RWxx$4|8+cwv(ENE)<9IASn6)l?oo$jnUZ@s(KckQ{* zvAmnEYglHLbiL+XuZ`Imp^n8{?Td|U_{GSE(Vo_!xRY9YdO=QlM@M=_hb?1w$+6eo zg{I_Jn+)Bw)~OtQWz@I$rP7#{!v>eUM=37jnWvV#rHH6h_oMV zIeK_x1J?dsBO{rSVCbBzv>3xVV|Rz8rb_c?Jd#mo+kSUgyDz=LiM*Zo?J}AjaCNt( zdl*_9CpApdBA2)Ry2F{4#zXmau6hS_QTk2{t-)14UetlB!_IA5JyLfDbW&gA4b85Y zEo|H7#Qnvd8|kLS?DeiTEp2vW5ZydOWjze?%&VeK!@&~d#~TA5u-_D7;Jak+7i|8X$`0-zXk zAp23q<>Z_)Ebr>&Je?Du9{MW3p|8p{^i^XFebrb)UzKO+sOtl#z+XeMF!6Kz!y~CrQhZ9ug<|){ndA&d{JZ?-`1M}Xi>kW$M?AV zRK=&?74^Ek@A&XNp=#0Ws65m&*gsqT^!PSAPHlX@u<-o`GJkJa_p`wdKdx<36|7RnR-VZQs(*uVdT;kNBO@f|W=+gmT2JZ74`g3^ZV4&yzvoImX z?Ky;Szm5Go1Jq~xASXc97x*wj;1dZ!C+?I2|LMfRpLa+xf4oB~0JxOyOgACc z1$F_(_4&LE2>GXi3(lgDSe{g&xCqg|3V8?ZRLDE{-d4@GKqz<`0SW=@mB1(_VK(Ex zNP~el1F}pQ7RwOg`y%-#==p;nI9&-S`K<=6w8N@hg^UQ9iU^GKGwb&*Yk>%1`KJt)BEBsb~PVz(ZOUiGjMSgE9{LpPA<>y34W+i=d zKqu3u>iNyzt;Qn1XB2+yJCl{)dlvakz(i^Q}4 zeuOH&+dvn98~IJfPx8Y$SijD>7X|_Wec7zEd7MBa<;M)$C&U$S?Oz4%D&pt zwM$o2EnCw2YqVSk>f>zYjDEics~^T(Qz2iAO?ecvx0hhmQA;Q=jo{>Tkw)iXC%#j*10ndiNKe4c(v^Gux4{Qf1U^NeO$fjpxb7!|eOr=6GH zT!R-NpF0gNusVK-U7=~&Je~Pl<8)3F4y@8R8{fpa z(cfTw<<0JlMqArf+dJLPx;H@k252+t3gTxpXLeQ<|9k6>2+l*=eYMYL@fB08&5<^{ z_FbI+^zw~U`!{MGVMp5>`>#Gq_W*Y+4ga=w-Uj;Myr##u0cSKlw=AE026nOLYT_*4 zKgB7@t&uS}C#k;;x-~o|V!Sqp(}nZe?Z$~otQ6pV(!JqXg+=1U!y<8VvhnHTYQNY;=fK0Y@%%{(9Oqq5o%7 zj_dFB-KA*(yO!*ar0_F<><7@Li9P^>t(ePVaO1ek!3?4*CdK;vf^%K=R~*DS@1(As zaxNV)jTU=KDF^bvN-iOY@(3YZpG}AfCFKYPI+qY*)dWKDEg(dslL;YzP9cPQ5h2pS zc)nogBXu1YbWRz`boMAWmZu&0geaOgABlX8B@X`?%$FEaWG_r8?QsjwV;VX&$El6) zN$07GPuJPMZ=pO6QH0S0&>Y1f7-iZBh8KJ|*MVXpvvH!jEHmGJbv(u9fsfL6;9c zEI(B@Xa2r*7Wo}g_@R4=r;qa}RP|~A-Jp#xl6FA(ebLqQtS_K@3T{jv`vjR^+GQA6 zwM_IC_{4D|{RokyxXA*Y%&)4On^ZWhz?iIyDSKb%bBiX+TbBBs+aJ^u6QA3sG367@ z^LNhO*VL3RyK(KB^6M+awRB6?RaPvCR+KNVSglRu(Zzwk!|tMZ$dM zprvYsY^9&&vdEvPg@ktYcn{pD%!Zo-?dm(Q%d%vjYg=&wIa?M6N7V_7nG16bZe}r7Npy=B!#)zT(PiT&8Kz3ZIho z<;!ZqRqLvjS3q?mih0Sh=#5LRUt7MKH#sI;D$A=@C|yg>Bn*JsM{9o)GkDkO5$xu3 zjgM|_JTv0nZhKVQ=^kr;gfo0?Y=$^}{G;v>0T(n7nnu@*Y?uGSNC84Qh4vsL+j*=m z3{8n`Rv|PcHZL?BO&DPQ-eQZ*TJEkNAKeymx0H0g51qiL&~0dbo7gkxX>5O1FMQ1C zo$91txT4{R?}2Io@k{&@V;IJM$~YX*D5FwN{=DWD>@Ox^Kt+^V0FW}E5Ao*F9b@Q3 zx&uz8JJJy%1o5qeBGIr|FxP@c?e7YKS1RFTy<7-4*@w}4H-1g{F)UjT`zQ9FbMRC7 zT?+GS@Ko+T?@J(+{jOsANip_o;q3d z#QMKJ<)A534eGw-pttqR#rxwgk{qPYnfSF?4->{E&O^y>qsl>k5Siqlo}HEGF9%8n zTCwz&)3~+4?ZO4jF3nl1Iqf!A?Rf0(H7eNu5Ax7-l({tWo0#Pxo)zw`J)7mBGSK-Y zGeFr+b76;9+|&Y*esq*}vphuoifSZEh$dGp{YckaJ4O4O)*pFjYEhA8d5G(uF!A;` zl{x%^uQBeF1ty>yR}!j*Jy*h5S!1N$M}8BwV}>TqaaFDfiZPZRqG!}~=&FB~@Jsmf ztwY`D=_xUA$&dTiRR8%Vf9_{f{l8-J=RP;pf0@aj``=Xm8%_SJOn9pEek;HTYCLTM z!cfk<+TcvU>Ju{I)bB_`|3um7^og?8aYd-BUR|{gx3TNjsv36y;YuLGdB%c;ikL~6 zvZ{PV)vXnZW4NNq?A*)!KU^+cQ+54-+}s+%YT=dxzQ{(b6^5`@DC}aTuzlX$jjqVP zXe_cVl2&(aG?ep5nWL>X{YZ2p?oPEwj+XtrLmT35nb+B_@ivv>uG@;&z3bhk--zjr z*^V_WTvVuGCDB$K?6TSMi!_RRVZE^#(QBe_X@B%S9&*1H?Amw3@ljpgE-iEF`K>!b z`3Hhs`4=90^=_!oR1LYJHn_fJE%wsbB308ag+4Q@?*2baR{KSUW!X!X{oMS1t{@D?p^M1$6u7eso? zM@Et2n`=ihM`>Azxlr>X<{JNu>soo1=rMfT!_AN3+y1%b&xf%NYUIa<)D9J=x@^1E z($LEyH-b}ElUZUHiW!JX!4!Mze;P`Q>gi^h&QQ~|G@EH!9TaJr+qtPQGYem?CNJxb z_Qi!yU}Zc5r>GoD@%8QAcpCpG()d=(TZb8|4JXFZ#aigzwlr;T8)VHhs%J9I#}DH+ z;KuyO-Ql$Q$)ql&>i)i*W#R8?pR=jt$Em!d>)n=p-ql^PiYYV}g`R9E#2{gb>Wf z5`s9N5KPW7aL%2`pK}IIekRHSTGdMTkl4{e<|y zyA1a|hWi7A7_7w}8OT?7;y~OpHw;Qt((}v~_u`Bsgi=?WlLNij69f5B?up@^WA4Fu zfDm%vK0?I*C?Vo+Bt$rIP7eORAr8L3BLv@94Sy<>$Y&uS_tcaTLQdoz=!DgPqah#O zN{I9tdv3(ZIIs}1FT8{zS?IIy{Y5tf*;UBG7{kFv$fyvDg-nWQ#C}1L3Yn9@irEAr z5tl(+2>4AUAc|6$ui?K)n}NRo*a}aEr98`Yq6kjdm-8S3eH-r5NPd-Ykaqfg8H~nB zBE=8IE$BqPVW-aJ>q>%Unyym9z^b((fG9g6Fw!1@U5)oW&|M}d^ncPX1XPr%;m5U> zR@fOI%bxsL_67LKFtBQwa72}g8|i1Jn*ch-A&sOv4-RU))u3ZMjF;}o;^iH6GvO~y zGJZ{<%LftpaUPY7-w})a0!WnP$G$fiKb{e^lD@qPKh~#Y{9dxiFB1(yrjL5CWc-Ri zXC-~L3O_Xcr2KgIoE3iU3O@`dN%?Vqj1_)mpp*HP?Gm5zgnGKgBEM#ZpSmx{T%Wrw z@(ZHU$@HNsw&{@fEqr#8#{bc+OS>)$O-zwARPr+{%=&Yo#PT@Bu1;3|2Hyi%a zBx}D;G%}gKJP;?#?*!0U;kRDlH!cOgy%zbYX9StfWa&$GM({j@LDP;K^^D+nxF+M5 z?2Mq9pL#}cLJEG#&Ip?Msb>Tyrr?+CjG&pHdPXpy@Pqn_V{J8nFgzo;SR#P3zF=z6 zqx=GxzqP}S{XJy}S$?$3FtBQVbdG4kaU=Z*)$cI@bhF?_ev}m?ze(o@3i`7?J!Q%T z26^A>(=U4w5t7gNSo{AsoWYBVw90>OtwLG_6w+MW#mf5FJW$JTqOOmjS>jvh{AkyW zjzblq&xZ{Egj}Ng^Bp9Wev^Sqes`MiZ!Zjb)8j@m2bnE%+N>&)?}iOO^!B3;o~dL zX^%cuwgEo2NJrVvdaOi+y4KIXwN<~R&C@V!*PzI>NI=|_##NSiVwJ_ywa8N!8ZK5l zbV{xt%<0kQ6W4o=_nKl;ID0Hd~{s*Aej>0=!M{VAq;VlG9wiItL* zRNm_^+6_8K)^AR7IF54?FqROFE{_oI=MbW^WO$pHqkO(^&lNKs(UfItB9!*H@c(g{|dpzRk`o z>MHji*pp;&VDqO(cAtg(p)d!aJoWf~eTw62NLHBmFtR*T<&T4cu?L)EcR$|L9_{So zRqZWI0@~>PglMCW5@NvHPY9XkCxnpsTMhTW8tz98_sM7`r00Gl(qBwC2zMd@Qb%(y zAqAiQoQL9vwrDniPIM6lJ{H zNIU&jfsS&&G}6zkcex*Qyl+Yxpu(8-F8L4$DHBQ~?GZRA!L*2=u@LA&Wrg{F^47!ATlZeYq_W|e_hcq%xW;r~7ewAV;<7IjftXF+c5$H5w&omQljiPa05I z9U&8s4qRA~=o-36?nVIGA;Z+!{c^!Zba-TDN5?d_ium}Xgb!hQrM zt~)uMx%h(bE&hv0vi#>3?@mcfuTcriitglPkn>yUM&DbUco>c~RMW0DDhqWPPXi}C zY1n`4BY|N!mQm)EhIQd~i2&07dK1oeBn|z;5&B@DA z!;DooRj;k72rs#!rlNXH!Q?3^&xKKu!job%R;^qkPlQP~gQ++mHV0>2t5#mWxMKCH zHLCk(J~$?mIRG8;dGEK+bBZ%zn;Ur^OpChfN~6CV71WwWHF=w~F0ZYwHqxbe+h%D8 zyEB`#wg?7^OyAzBjJDbgt!)ZDjP?c0V%Gr#-XN9i_O?a1iMxUq+K^@M7t zMd`Mo)?V+6X0*9&#OU*UZSjT|0UaBj-{5M)4PD#dW8Vn-EJ0%%gVSp++s4pFoL_Uj z-W_gyzsj*~e6+>$$-&4`cPP3X=j61bQi@3eWS@%%etL~;w&&~R+JkFRmOXusX>l$UN@A3vay``O6Q>VL{+9c;5 zhO)=*#cexURdE#VRTukzJ?huqUu*9#y;Nv=gkJ%C%EO(b#fd!dsJ<8X_qatW$j9}t zek+j+oGy**YiqV&?7y`Pyld&p-_Uy7nCCtUX&ZxDEG;dx5O@BRH{o|#oX6g(##&U+;PPFh_w8x zBN+!cUUL-Y7_5y$o*eG@+W|JA74wMwu=i%`A**MiPEo1k3EH(2|2TjLjTVZoMA#t6 ziE#sSWFgZ*;HS*by{4FQ3Wb1Z<3NPY34=!#-QmdX031Xp^D!{pPlYaN2ICQ3q3mr4 zr9Ey*?8kZ7F*q~XUQzI2{_V&I=O*#Jl*rFm;_&Zxe7`-#@qKu5@tvgn#%dt;$FTpm z+nqMA-Dl6R4YsjddCrsdiRV0p3}p-wT4d0f*AgO7t$}Yh;9f%1 zy9Wu;=}|^uxaST3UmEW35#nPWF>u~1!*qlJnU1-DJZ~!WB>)usAp7*3><~|3Ho;GX zF=+au6A2()49oUL`HS+HSts%_XpX>L8lb{d;=i=h;cet)obb{ANk6krg!OtUXr+-> zvrc3=%7STKpFNbw87F8UF}Zwu%sQ!qX>vADch0K3Ys6?9f~BA&3Jzi2&2 zP1>F$Kz>{G$p8DD_npm~B^wrv9Q*&xC!1$xp67k$^3KfrJTuSC#HPClbaK!%8OGz+ z1iE~aAKNqQWiWnEC&-VLq4*6oCz21kMDkZ>;m7u*@)tWt&zj_8<(S%A+ZG>TkBee3n8+6PU`B~>gpij)3a~k?Y(QLJ|@ziq!90%Z{ z`otG$ukZqyHTBPF?9)&|)OZg3sxH+$0nvH*#q1SU^65Y^dU&=AQWIn{@95TTwSj&uA9$FTC_^ErU-cI!hH9HTMx*8xaJy21MY%sB<#g45`Sg>$^- z;YFwJhmT=Qgp2mWvCR1wT(5soW?B7n4!G0N7!ehY^=lpJ7^ZO1?>O)GFoONB$k6L4 zzZgz-A@R5wre1%$NlzN;^?$EO0V$8KiwQ4}2~V|zW7`VD7B&2mn#~Or_2Kn3CBY5V z;c9HBHAWJvI!<$icyxspwVia!!nL(E^(%r^;SGGmOi8Kg`gL_NF+*l$7?f_oGk9;; z@6*dWCuZ5D~D*H4p@lWq5`nv<-3vi1(YcF*CX zuBrJ4r|LW0NxImDd)P+q4^Iy->3j5oWO;kx!@)m=u@7|G1F(t6(LV^TI`D94Mri4m z9t$|JyY(-jClNne|5Kn?>fhykhYG02!Iogt_73co^&LK%>PTxG9fFSSm{97zU}+<@ z?VXK9ku1;4_&>>$vX$rVF4>w{3W&x0?OR{os(Ea=?rlr9@g&?s5F$QoFX^R@lcrx6&yo99i=J81_xP3C z@swhg=*I<38@A7!sM^xypfTl4bFNKm`4LjS1hXLt|BDYr#(Mu2HVby>St zooP$`mBKR}x{UOp>&f9o>943J%4hrs)j$fJl&{!DGXcI}`l+#3?A9U9Jw-WLzG2c& zjr4x_+0y&G^u-9uY3OBulo#=WXW}J}2lN6;JrVEMgD~-251)yb%k^+Cpr7%;*AlW3 za6KG=ZAI#8kZBWjH-k_ra4PN1B^`4Pc#DOU%&A_SNo ztC#%nYEII#_5+cKes>sjOhY-9ZmfRi#ye#?Ojp(OVCklVZlPiZ7?0m7(B+%_*mUBR zqcK5#FIo6;{89X3^)arE4SNSXE6n`iktjdmmQeUpU41^q55 z$?1f~=S)sY7nSFfl~MacufxWLfmoy9#Z+kjM$gc!L)JOgtA53Pag`YdAYC?I=tdO) zRPXmlmwMu-KWnpoBNUpT zJPG$xow?a8v!wpH#9hiOp;I&s2pa`ZQPlfxM4-RQ4ZV+eeycP{c2}BsCmIIzyhTKs zj^i@r4&@l;z9Hop?&occ<3o-!3JE=LL)$ZBm4aqnUsXpTZLGUNJqrbI zq4{7%{l=z9VB>Vx$+h*EeESzQ~hqAC35@Wu^1 zw&eT|BDgVSQQz#0+gqV8ZJMMf@7k?za*JFIT9re0@78v?b~|_HhWCYGm+sQO)DeCl zXxOE{9lZB|H~G+)8r`<0+|a&|tp&Hhr-CXeIkO}5fN8z{cA!jZWd6RFrTsWHvVZHq z?Ij|=@fY~dvp7SIJd1NtZBoP3C`*4sYH2p0GL zx845Hgp3h#Mf29`Km2vpQO8sF{>Q6_*xsS~Ibh=u{bL*lIobXpc;X8yJC&4i@Q*Sa zr(xt8CUk=0&t~5nca7^1lR9iOl>3&&QfKWJwm7i--R=Nd1uzboX z944{{$iYiN=S3Xz!7-Wq2>D8^-@|VJG1&Kzd}W&hq0e{zMG}2i7)v4>T>nsW!9Z?O;&p4zu51nwTAg#(19$D-`OJY zQ}3AaIMEDGz>o8(bo3j}2(v9%@%`Ug13w3Nwn_E84}QZL_+kXC_@xSMrdO{zff?Rx zh84dXWAI;(!EcMf-yDOdeY4?={OpLqKNy4mK@5I>4E|vYo_Dk?1M?|}qg;YpzoL$E z$6xy^o5zfaKU%`Xx5tDJ#e@&Ugzt|DtNnURl>9hOD#!53nDFeF@Yylph1mEFAYNt-mqH9XL4#i)`ae& znj1`M4AN6&NqvJ_1dN%Jk4IOKAe}dcZg3IMEP)|jt`60#UbnJl^>y{(h8tEk)Yojd zwjpGZH6^O1Y)jq7`UZda+A^#?1UKmQ8`nb+wU7;ZYUe3#9y}$}K{jM6@%QBQ39CS? zsLTvXgTuit9qc!BM9o*$hBvGOtO$ndA@KH}P=CrZ>rZ-ZLrK{Q3fMNiDKsXOoVkl< zi;5$m7OYZa>Fqd;6qxXsFfc)h37Z(4O&b5q(i7#4a-9HjEF|N*T1W4CBjWaqZMN-x z1Gf+^?Xy*ByNW|&n;pBf?YsQR?T+Tw<6>i4TkCP(##H=otW0T(TBY}m-t@b7>T+xy zjX9#DImajER_*wcrIc((&!%MCre;xL|DMsa-x=GyHI%$7xjFS= zu6c~eg6&*251pZ~jybK5p#FnxZ+KBD($aqhNF7{*~ zHnqzs?^;~4HML9E#C^2D#JvKZ-)f#NK3`kJdi=h&yDVMS70b`xzmz%Ji+kH~3hO6zIUPyI_XR8TzrO8ku{S&J8@X## z(?~0~wac=cI=I|;S=rbDT%Py4+spgxUfz0GhF!p=oi0)IHo1BA*WUK^x;#0!FF}(l zTFbI3%95i`FU_*G;Ef#LS2N*lXHKxhrxz9Ma5HBjzqkz=mas>yP8oZs*X|W-4ZD?od{7^-xI1^7~P7S*QBbuj%7X|XeB1&^!_ySO^3YB+1S>Wi& zwr|V4AdnNt&MgeAM%vzhqbE;$ATS+aN6&Q85tyA*0N-p|Zg7FbF3^I(QecH=Uoa4I z^pt9Ni=#DIy#_+Xfq=}1)|KK~RW_%+DpY{n0H4d;JrHsS?9C5^76tZ6s#mjCl}&Dc zP|>U)&D)aZZP0W?X)@a1Q8b05$w9g7%{eHSC(JPU^tattWxH|Vy%5LUHhByfdC=7n+STX zmmhmIfcB)JEom*C&R;_tEN{X_J{CB1*v z9x3H$yS#L3_mu^_!}f^IGV;9MQ2}*Y^A-FG*hj}$C!ZyC`QpriKp?Yj;WAn0pS-t- zY{M zD5B>PV)2Z+Fedj{y+&4ega10mvXB+L`y>xAQk_y!^3 zw-I9D@@6xC?iQ7*n$ z8zM^pHL0>Gt$ZOpZfjbyE_c^X{7f;0{wkB(>rm7)B8yR{e4)=cZSpZSpxli zc*Fr41{S9aN9zVnB9sO+SeO_y?D# z0j5B&`7c7~FKG~|Q=m`Lel!Jo59ZC}S}o80V|)tMG*X}!ag8zsdXS$GN|{cG37RE@ zP}&+y{B{$6yNPcy@y`-MZ~Au=|FVgHmk@f~p8#hx5Ok9WL6-+O^L(gofL_2EjGv6X`GlaGOX$IVM?&a{yxWWU z;63pvIYN9w2)!^DYn6oGBE&-2UP3IIK4yjwnPHw+MEtvE_?Q{~gb?+`J+iDX+FEig zdm175TtJBDbVATAAp{+5ElKwTA@o@{6sDA1l$#KAqX|I={YTQR0_1!CDj?r;i1E;e z8v)mV&n~^J<0<1E%9aJ_|Kcu2G|UPqHa~ z9R#M0C9wS(2OXOs`LV6UH{zOC*2W zE&SM?;_+)ukYB{Y55s0$eje!7iR3Q?I#pf_2XXl|CCKj$3qK5#artq9Hj(@-0-eeq zhOM~#>JsGlw1ppr&A9wJ66BW;omAzI{UqM|tpHsjgqw9E!^?0J=oVyWheO;!IqAZ3*(r#0N^{4`NVUem>A8lE3X1e%>MYwI;|fV&PXf z1V0Z3i$wAl0-Y-F>>>CyCCKj$3%|KT@S{wVNd6XqPUWv?2!3@5@_X9C?}8!tbtK3y zAA_jM--03dRe&y$@-|!e(VSHEH;AN^&FTQ8I|RB_DgdbD0}P7;ln)>Z zNBPmOo`F{sApwX)QKxW(R{3QS=$J0~`SDZvgYDt0Ii7xZO54K%uh*bHwe8{EObpp) z`($mWGUq3q!}!0mr{`{&C-u)QzN5SnCdGuEF=3au0d%UaX;Zk|d>)?#xyNVffUq-4 zYv5hhJwGQI@_ep#TEn(C=FsE_mT@ip+U=>gyXl} zM#cOs?+I!`5vXrb{b4_XXnWG0pap0g_aa_7)mAP>gz^)21Oa~Ul~cF^M9^<^A=ru| zz_z0t)1`~0OUDC=(B;LU%K=Z72lA)wtV)Yv<%hUDfNp`xD2d<{4?^qsN4mkrKa4~3 z%z;G?FQ*!ZX3d{tZZ16aI83tZoyIjTxhS63xqn^_WrFNz6IjR}v734fxP0h0e) zG2!Q9!VkxUx5b2|U4t1%eoJHUlueZ*p5JNZ7`9|j=I7Jd?ha`(i(OUf7$3#`Z`z7> zD4W@u^&9JNs9fE@r)(HaWGiZe;SIxJBrAs3O7@fTB#V{oJ+0$*JrWw~0 zu#g?!teFwo4n@_N~fZY*Dqn`QMMGI$X-bJ&;l2<|+w(@m;e8__(rupm zCS=J|P_+9-WsP}c#KT6;8+BT^y~^6DYb=}8mV{g7X)7n1`Ttj0PBYBCilEuFz03_; z*z3}13;XRXF-7mx#04D>%`Jdk-P3P7um^C|y8XJ_+vrYi5>xQR*PVNlu#?ZR54YDh zX&tZ}6)W`&q;I^N>$7RIII$fThQ0Q5rpfSvwyCC_-XfWsSF>`=Ff9TfnkPBe&DU>w zd#a9BCus~y+Abde-$~;Abl5XZ$Ata!S=QwuqAY3@Lz&1X?yEx*%HduixKzhh~tnS zcDFe1C*9bGd1ELo%djxD`)L`uC38M(Ow*g^!^YIn%-Sdl)ArHW`$@}p_RmMK<1!O1 z(1aKBDp;dGl+3d6?fW~Dn`w8y)j$29dxG%%`oI1olHT!~h&YtD=MS(%&1^aA zzCfuLmZ;;uM@!VYIF_j62UwzxGA&UDlv_{?UDL?j~0hZ0(Y;WONM(#$nS9XNXQccg2?Mn8nQM$9msT-*+$a-kD(KfS6 z7x&$PQSIYROL`aAr}0jv`q5e2y00vJ0ye1+;Iv$;J*voCEG<&UNsH7Y5z*)`GfvFS zk~XRQz7J|mYFL?$*$xBH;rdBg0s^v>BOpUjr{F(mi1J?=A#^4w!a|{^%)xajDTiRO zDU)FkVcJ6yVM$L;7)&MvlXD62+r%FuRZt%)dei<|TwsBo-24 zj_@Kv%*B-xVlHbXArilw5Q$$!h`9|ZPhsw2HN%)#zLpSk51;EgFV;vdLo!~#{eUUR z&%1<3SFZD-UgbJ3@-5eSQ7=3@F9q?~I3U+Wsc7-8=1fA=le}9Q<iI(xUIs;r_xapH zh4o5OlW?g6=TjOw`ZIfUKwAFdpr|TnAj|MyA2?byiC&BfLkn&$@Y%$8vJD1Chjr74j}m~+dT6@ z{rao;S^06D{W--1IOSb#@xvHJXBaM)o)Oc~((}EG(bu&r>n{iZ|mcP#3ap z7=Tm$0{E?Tmw+xLDU5##cRqr69Z~lz=-x+&b%5p}`JubZJK9j*I(Vgf2=8>23IHm8 zc;y55eGEDukmSeWFn{Dnzj_8h6J^psOLLTmm?L6?s>@&oHAznODpc~9popjq=0 zKNFI50vFZSGnw;GrLR}lR9$y%<(m57`kH`06vpn0g-#O*^WBp-E!$M>tXF}$J zUq4Gj&;Ko7f^-JI-hM=i%N|m%r2IFDh|2 zy@Oj9>;>aIlpYIrj@0crXO*~mymrT3*wNT5&V5?yD|X!Da45Uc?QC*1J6lB8R-0?L zLq6m1@a6|0wW~X`oX4Nk{d1koJU>M=?GK5TY1k?IaKP5pnEHOmIAi96z`x?&4bgpX zqkYd6x}g#FpS;rK_jNZl+Hnu*75W63_MKS|heR_a^5hBJv1h}MKS%LInL6*HuodIp zh~oZxBM!DB4m9=xgJyBxdT5j<>WVX2##UgtgUeP>eoXinb7z)E-Wq|Y{5XRX_2IVR z=}p>hv5UI~?f1F%I9hB?19N&5(t8Byy(D9+2v&?j#d4WqdoHg0x}2Jdc&4 z8_#2X36T28JA`QD9}}VyD2MPK4|yId+Vxi%MnAZb5cIs8oB9y%E#+BA-!tQR)-}V= zoA^HwLNWLRa3&g!19FWQkaz!4?-@@B!I$e?&ya2(9*}jx0G#sc z@LTB~0^JNrVf<4#KZ4e3d>wR+h+}%xN5~JaC%Uc)uXL9H3AH=w6u(%#i+5cx4doQw z`G~Nl`y}X?4%20PymX%h-9q4%i^tCaX89l@KQ^Oy{HB905q=F8ejGdE@#8(5iST>Z z!jJ7K9=|kHMk4$!0bM@$u)O@1DSnu8VLOfLt=|A$B6{oVpnJ*WN9{)OqhHlIykalL z0LCe&aD-qHbq|4#-$dpQ!%UPP^w!h5cl7@+cZw{E)(kyP`5o_%N)qfJsxGZ}im(o2 z?i7hpGzQVPhRw$0zt26;*EkFB(B3!=&B_kj5_>XV>HiaVid@8knohl&ixF0Sq81`B z#iSunI5jTH%0he{5PX-)v47F!;HREpnDe3v$FTC_6Fq?LcI!hH9HXuMpLB!ufAqt- zr)76mI6q-~k5$M3Ty*}(usf@-sh#oZ&x-wY)*V9JDzl>gImI^RmC!npvEGv8`3e11 z+jC+i=oo$yKhE3u<#WbAj=NqR5@!12EXefl21v3lg7Zn@Q{d}xO@tQ~Oq zz;I}j@?GGSL*$YFAwj)kC#gA)K%1_*31O^-X z$eVPkNLXr@{fE!csXWbu-^y7n{1 zKUBAr>rvjQj6~gIurZQ+t^D%w5c@m%srn;7jHUBWXD+^|&^&fKfxFaSHwqUWOTS3> zq|Ha!`<-*ZdDyHWj)m&ooI<7BqjVL2yi#>L7o44VrjN=zBbo-o)DsvP(?@ZEDJorClai>#q##6mBD@2FzxO#87{3{dueUotlSnDGipqs5T!fr?i@7QlyG5R!;d15bPt$@jFi!E2n$| z2#0}^|CK*hPH6;Px`j@q8!M+YflkR4sBX!7FgfKA=&l@uANgA4lx(yk58^4UFYsgCGdvxTndVr{@L0eMB%s34q)i&N@NKS{*VbTQ7|>QK zH`g?*kgNAG@oVa9YKm)XOX{xkU$B{{FfO+l@0;16u=IgCh4KcX{`yf)@k!U}^Bh z;MS@atFVq7IMnx-Kv~~YTKaR_s$Pi3_Z3tFzC3l$)jgFYX)fyhCu!+@NhWv&K@s%# zYR>I`ds_j{NA?!FJG{AG)BYOvsyIp6UInVEbiMAm^rsx5n?sJSn;oxZ{#$5UU=L1^ zo}i2AF9!6!zdbB5w`OCJ!pP!K0~1REw}g?|1_9Sp~rNJE_Ti951`9cNYJW06~k|d zmLD)#S0+E@FNmRY0Kspya*D_Kh_HSiXM=7#;+P)mn*3PTv1=#K0x{V4mhIEZFB31& zgE;czyHxz>S9yR}6d}U;oWc=W<4ZwTggEk3?}Pb+zBBuD^qtwW6W=S`!Gw@~wi$lE zbD8rmxXoXO%&Yq69IzM7>{SYhc5JO-w(Ef%i{Jg9fm*#2_1(wtV>-S~tkFgZjPPI0 zu(AQfEQ9F`e3BVfc#M<-@EI}q2{HJI7W_}}B$H#F_+8%%NPU3wYYg88zj7Q)Z%_e1 z41>}}TSXCnp$Y&pd~Qrwjz4A`@zJ8g&#+iuvmRe%VC9&VOdH4=CZQd&6Sr2!wvez`tmy7cgAbR49SD26&tRtEUmA)c16vm>mVqs z2!5@yc=HV#Rwq6wen~x8TwBvnwgF;B-3^O3)Lp0Uyp||lU@;8hgD}3HJ#`Cv+Y0Iy zavmEq=JK|*vAQjEdu#czZI`9)9@}jnWoxhO)KZ-7hAmZ3T?y`h{#D1d$q#icJgcPl znPR>7&D@TOT2ooF)@<7)cKdsOxJcyxT^siMq)zOh=DM<7^APgKyTE48I@EjVO5-lD z1qJXg-|j!VO@8BhFI~~(zp(um`lDspua$RRl-}r0>1vcZE}u^A(UP0|ueXb49Vev= z*lsaa`)J~t3p@1E#l5@h7&og!%)G44lPhxU`-wOH)0fnvr8eQ-2=)9#^Z9XWjGX!t z$Z2Z3O38To$2#|B*~EDrC;{x{Sei-gTC=$KLS5!QX_{_-*su>|97D`Yao;4|koK$I zw?}j53+VI5!Yc7Zfyi-pxN+Bm-1!2Fww}5x^zkSWOQ)AkI9S~KV?S)zY$CThxwItB zH+$j_p|RVm1a`^v)R!VB*wKZX(Ng!~joQY9_L^%A#!YBty{(0`QM_~oWTrlsncupF zl(P6deMKfkli!e{Ffu`Qk`k12mF3nn!%y5QDP0Zx&+f*Li|m7taipw(j~BmR?A%h8 zLZ{?-K*34&PfX;p`4;S9}(7cTS3Qkm@ebvrTaAK76Pwa zJbui4K8VN<%_T0se9$GrkM^C4ANy3i{56A42VS{&`RlOoQ|)T7dUhi+k^EJFPUVl? zDPI1zB*^cOg&&56xcuHvkRRT+4pYtpZ*-)m|_(4(K185ZRA7wr7roiXZ*z8FaoV#vNR4ykk5{&(!-mdmWDf4J*a zc_n16_B+mz6d|bUl5-?EX7~?)oP+4cnL3D6=TDv-xGY#3#_jLs1)9J|X9w2TVKd%v zDCN+;TF@h-;ZjW+;K_7@#v)yN7vl5 z_jHa-@ph(&6_Yl0VwVM|y4x#pLI-{$VTS+v5p825+N0wlT9=}{K1$is{sVt`_oTU^ zvkp@^t@wG<@$=y4YwW}|LkAx#bF_uJ!`?9TS*>Gv<_($8z5nsIjrT%*G5USPw^G(W zUK>6S^518ar>HK*T_@)FdZz5wP&ZP}P<=if;iYCAfOKgn{3R*?sM=!edT;=UDTC0d zF+|oK@U+EcyH<{4108i>#hc*}`m@3@to*U-!L^`sk-&6{2P@e+CN+SLV>yQj(yK8E zLlx_QRUsYs;14!GO}=m~jBpv-{r=vZt5Unt?3o9vFpjv*an9EEyk8tS_n9h;b*nM9RCJVg-kU5u zi~6>wly~1V7n346FX2AH6NTT>f7bi88!<`>{6^wuUsR_3F73BD7y~^W&7C9NWq`Xo zN7{VZCB8*vM}N0fQa#AQBn-ZUG(JyK-twiyiwKQU3}@TIG)&`)&bUB4Z!Nv_!_fhd`Ie z*vED;_}Dk6z!caL8~X~161IimcnkN182h%$tf+rZ@lEBGkY9s-$FVPjplUlD`&OFa zDnO2XK0xL8{m)SWKskL86OOkybdvm+*y7Pj%W{*F7^S_+XSW@UJe8)8*U#3)y|bdS zBFE9}OF4!8b98f60)CO3V_0(Z-Cnp%o`$tN z3si6zv+S8R9&?009dbRpFHIrRHoC8kA*~cAT6!;0sk0`FotAj zNOVbtL^s3HuEwNA9Y66;*0&#=r_XS}I(bbbbG}Y1r^A%UjG>M(GxoWXs=i_U#_F0{0rL8WU=`pE>kSw(V_5qG9re$C=d{=!Gxp?h zjq|Fi-Edr^pFe(UD6>UnFjHcJiB2U>!s4OU!!TaeJyqWQ_AHU->`1z1QnmR)H#3j;XRdsp^>hmF-fw zW_SYl@mcj9rW~`#j02D^g8xOPpFr`u(Bfx2Z7~Py>uO#?iDs99j_+7Gm8WwMp?DM5 zh=A(f3@bmDDF@I|=Tp2%r+8$*Z=FxN9SD|>=~??a=}`xD0MhM6#9)1W=A60FUYSTA zEnrmf{O;$M_AIW%bWFz;5s4{%(B}tZyuwSR8e@)d=%l7_R@0fqnE$3^z;vy=X< z$K%TTFsaYgeYWda-|P}k=2h8u`TzS!_j4nk%zR2($UQ7}6N;AH&@R(nZ1l6&MAAP> zd$LGUB~=`Ywf%mvXL2a*AlD+W-ViA6`^Ox$qkT4>O8W@*XAW4OIdVh&cKBmy zBW5$y$N@erQ(BK@ss@19E4}EbvTx%fD!=DYETwLVz$m^GEatLLv!ly*1ciokTqKtE z_rOnJ7|o4(4IlOpBAi1A`b+?ggW%_U2AY)PWwTXl&-lHIYv;ne(+=g! zgm`yL2vN{gW_-07-)P3~1mwBIcLMTUV#EFf^#CuszAO^zL{=X1Evp@Mm#DiLgsNKj z4By=y^q5Y)wXY+rzF$Ng=070$EZZs5XZzfYpOxQX(AE#?j8%B%F|_*XCxY#kac3xD!(2>hyCV*rt1eCsx#`QgN`3grpNwCeyH}7>`nH9 zj`E&zs*DAQP=4Z`1|8E-PT|f+gf-odLC18MF5}~+%e@tY$u6<{7Jx3_{aa z;Rvn#LZI^?j{NwoQ~V&~%sQR>l!^)xzfb91Hd9x5JPZ9T6jJf09&W|oYK9g5+c9CT%UJ2}h{1m+CVY1c{dW=0 zwxr*RamUK zY_X|Xx-qCut{#M-__~IT=HsUFAKkE{EN*z&Q)PY4_1L}Je+Kr+$7i3sIXIeJaqYDm zvEwJSzO-iZ>iTe9!^Zkbp*&u#kv+n^`U)32ZK{o;S}r@WDW z@E`oH*V;a??RdK9#N2StiFt=Uuw7e~xvu!o2VyeLg1WirDNS$xz*hFCfAkUUjR*as zj)0H%e!mUR-t8ZG8 zEws}=`=H2KK4EL1Zein7B6oQt*XzS?MYeld}dwvN-Yb+=sGuj~}bX>D3_ zx(qpm6aFYh?JVkD6DaFlvgyGN=nk5=+cVjd3k^au?iv~;*QQ?0avgtY;gWe`FV^AR zqdI((eYsP0uZd%>`Fl0XH^;YtXKr6|z&HI*uLb$;wffx5TdXl=ok`(qA zlx~fDMXb;MX^&4!F*&`I<(}g^KlM$Q$=8?b%Q4d6(=TO-mJ#27E8=Z^SrpcZ`wI1| zk~i0hmc^+D_YZl*oF}zB@Gi!{#Sn|_wcDTo|>S`9#oj8yBg|NT( z8+AODdVXN+!G(Rr*a74_pC?p*>tJ!8-Dd3dxqd=f-?E&4p1|9bmh?SkyHl>w?T+49 zQy_1wu?M(o=n(4illKadVuk+6d#`30khT{NeT3emw_wMTIQNwgaMen#m~5Qn?G*Nd z`C*a2xc4WiOM0hVC~K03UqFrD?%#fJlV$oqyG&#D+9<&kHvMgV&H;B8j_8Anv`9Nrggr^R0@@U735moeQzSMm(X2pnijPNL5=L^EK ziBwl6R}pH9QuoO)`CK{TolQo%X*&BPN@Dg&(Oe(iscWIOu-J1>X>n#ofOUSUd~?^7 z;wHL^KTqV{WyNy0zc`2WU52{;2(XSCX^%F$U*IHH+-MG$G)$6K4%Ut9{Ex0 zvcKH%$480^#y{)b_^@#9{Oy1E^UiwaiLr|}j&G!DC6-*y|3Y+`!tXyqDe)ofF@Kch zm81Plws8`G{BN8JVEymL=NLrT^a_v!TOI2kF$nhqw-sykOA?ucxBq`4)K>1%v`iLe zDWGi0?=6HkS!C$W)W4{7;!n&grl+jGaXPEONKu%&9$g>H@n&%PB z65QH2cD5>Ofo|lOg5za98>CQBCdJ1`8VLWC4e1v$e zj1YWvLMVrL)iQo5A@Z?|5ShA|&|}^mh4NCTWg)L1MER~JM7ouPc&>^Nd}|1ieuxn1 zhY53pSWAfXH=1EI70LfPGkiT^o)DCcIq@OqIT7BI6dsOjN9>tw|vH4+3zP%K8(Wy`oyPue@1#k zjWeozL!@`w?Q>TA>g4xRwoiOF29(cZwol+sJH0tWq^HUko1UdUPa{2JZ*I*H>8bMJ zdp8W_Gt#?ii1bwXV$-vf@AFzCc^>0Q3goii5EkNxPb=>-;hGs?o(UHK^1Np5;pM)) zrHqFhvVsu8-UdQ1_6`$ba&HSECZ?Os_@@bH;Eod$|C$-*IfJBg*Z?O M94dcFY6fLblmYmi2QNy1@|!f3BmVDLhuQh z@mmNXe{Cm3dUCEVSBPIR4F3N`2>xjfK=2()2)+{tr$Ejn1pjG-;NvAkJ}L+?`M-(~ zbXOB1-6}J@mJrW`O1b&!g`nvI0^FHT!zyj7X$LW_yGA{ z=qS%nH?eu7C?{-r2&lc(wx|=RA}Qdbi1KhHBqe2hu#yX*?BkT_U4&x{o|N5XGLUUh zTq%2}65`v4>XNdx)Dd!wzQYgJD8`>-+SW1}_#WEEDdQR=W0}`26lXNy*{KVmaxF(S;SBvB!}V5p!nzlhpr~e0dHJ>bwDmmfZx*=er!+i^49^nB?<7Gj*g=8$G#Dd z-zA_+q`Z4A{4mtS<#!l#iIg`Dg;e>&5EYl-Y|t%EpuCM1e$*%9m3Ker5-D%Dg&)_K z;_=JG0F+311E5poWxI~YZ+n9L+ARF=$&AY{k{~}H8i~rEX9#{F&?QpdRtvw}A^5$K zAU_Yj87hByL-1P!xBtT&@%t~$d48f#V1R*PkYwieL zQ?oR*wiQqmtJ9wXRzo|F!O_>`~|4gOV)|7awaZUe1yg zGo{qf?=2~PDU=krI#e3CKXhy0_o2gPN~PGvEZ3I$epbxX>Yl@sT!XZ)4Aw0i8%PPg z4jx${EqGas6mmbZDxwSwenvGK{f64hN9Kq>kb?_ozYc z!KX|PR&pEzp5q<|FH8|j#f9H#3ZHDtlr!_p@HvEdp7fvlJU9l-xlBiPLDc~Xl|Slv zJ!*$JYNY)Z`>i(KT`C0G0N6+)JVrIj$7^DQmLR` z2TcR@B+~$XUV>?ic4AYgUDL#E+Q5RSa^Rf|Lph8zYT}e5HVsQTKI420W;)`ZB@zOX za|!PfqQQP_hUHuf8?d3v%kL@MI%EOa!1-OJ!X%ps-m`4`RGboYH-k>{GU;an-eGxG zH6^ZL@msFkVS0e%v*>d2`wmfjQ2W#y5wD!$w+0c)PaN;ZouY^=IEWFFPL>P)YS3|? zhH@%Tmm$IuE#61QWZjsA%CE=J{RwoG+mus0{D`p1GnrsO;fv{UTp>SH`$_hx+kqHN zAEpeXc*83m0v*#(PT|f+gf-pwLC18MF5}~++YQ78z$+JzALo+tK}3FRR`K{<0=fl? z8DKnqO%{IaoALNP4Y~^x;CIZzkL@WQzic#!MDn)^bgH}@_Z2@(KMs(m8$oyFAo+`x zlYb9759nBb$ZC`y{i=@O6(56+?L;|+BecF>2Z&Vutok+NxqRCF_Qw zBuR3g2JwueY)XF^zpKr#Ri3QWgPR+$De$`bnpGRs^&e6Wt=#;zaKq|QWzB}_aB#y0 z+#WNOVIOcSZ`j;Wvwmr~sy^&(EwgV~JP8M^Uo@t!@4bw(CwACEsiCnp-r5AKqUv!eNyly~n~s~BMpsX;*^b?0 zD~>o8`#bGb*(snY%`NeFj;ZoR9OrHIzx|r<`1{T-_CD8*TRBGQck7PxvW}#8+Z~RB zNHb|Pe52c!NAfCGMDjW&o_%L$Qj!m$>TJh(M_+Sx-Qsk0-Qr5?x+SgTfbh(}Iy)jf z%Y6lx__CY*|M!US=zVjF`}Z;%5*lw#fer~Kz4!kRAkE=w8NBviP`2wTUh zEuixtj_L88lAjwtj*%!YKabKigJ7_+GjwGFd_^BCI{C*J={*{G( zKkA0nQ-vSDZ+9WE8h$kw!}Zt~5Y9L8Jp1Yc_}R2c??V{c7ER1#_#F7p!jJMR@nhhh zh2NcK_`d;PKseV79|8O$!oN4eKLPw5>X&jTpXYPqP@lDCcq8Cegd=8{-}@U-zg%x7 z{VarkjA|GS9t@8~_*IlQ&!h)g)JYxQxGKXm?B}gn13uimpK)bFu)YEJNaHS!YjHV; z^^32rZ(O!t)x~HiYYHYgUHB zYZ_K;Y`|Hcm5Vo2*KCR9v$Q5y9o}&5l{NJn)%9UfCOo158L-|U8O1HE*}yA9YAQB{ zapg$;CBdp%^EA=gC{1}?Y-%{81=TSqF>fMSv$0;sono6qgFJWn#`@}&;Tum%WMNH1 zJk*Ms{_PggObyeeBNz2LZ0XqFfE&4O=^;-yZs7`~<3?>C8vKXtSqCaY?!cJPMTqlt zYrtiMUUGf>>x=phZ`N|~j6Eyh>(#vJfvmhsfLrWdEHXg*f}E`@?tL_v{v1;v_l!_Z zw@u3c)eA?_XQqDGo)O|bni=5#CU}a;M*>HJV}fIdXULXnDXF zV#))#m-cNgu3HH10^Bh}_`=bxo}vS`9PLBV&GRCbt;Tr~3)4ODVU`SZ8tAl?P~hlo zxhVliU%kzn7;oItsb(09d)MO@HpH5Fe&OgLnb(SH;VJ3egL_$kvv)sbV~yEY)oR@* zlE$Wt9Qndg*FyYqY~3ep-pKfXH*!{;Hnl(b9&KcYH!`l`{r6U(uH7Q7qcV7Za6-`IbVz)`QCt~A$AkGhr?MzWiBVt+OkzwNE65Ba;@ zwtDQD>E}_0)OeF#Y2Su%4*fiwa^X zdUIqtzsf=$1ELA_o8#}rtZN==%KIYq-@%-pV}_dUx_$cSIiUV?8a%F zXQ#draW_r-F!isMoj&61QY*irCn zV2f>g47?4cw|5{$rmiSc#iO{_=U46P#Z6!ObGBLPuL+O6bw0}7jdDlIx9ccz8B49< zsN)l2d#lJpOHFp%eMiKBd4F5-o004~`z~A4n~_ps``%X^-bkjH>tyLgPoqy9pEWI6 zwhghXyfZZidBq)v6Gbt`8RjEJ7cI*(wc|O#H}SE2(e=^mJiF?qwDX;=du;b@nKaSn zyesLuqt1CNlHPcK#L?u^FNmDw(Wd;!SLk;iA zqaAnP4C%31)#4$uj>e7^p5)dXSx2m8)^SG3MV*@V$$NaepS*Ye2fgK}CCBzwC&wU1 zNBHay8$V=9T2oD}cVtr2zaMq^>`mJ7yZ!KaY(4H|Ta&ZuhXF^ie*`B^^Rn{)mIU*F2Wt9}22Jv?kF>`V4$U#Cr5g}pjx7xdagqk!mKCTDkTFL3hB~(>aFhOXVD1IXN(m5EJg_5uS^ABtlHQa(iegZQ;({5nDunz{kg*+dBXdP2l+CItN!Ld4%d zI8lfj3C}mrygwxuVj=G~!Wn07?T+=E$hsQlv5kAQzN?LN z-{QX2^)2VOleRl{*mtT0HZa2bbpqJ%9^vg@$HV(W6B0H=o_2aaJj3bz{IjL!Lpc+v z&xuZvF4qt@$Ei+Lm*@k-P?ttpEeVuui1bPlEE_fh8RjEz7)O`v?S>3zET zG}7xjW9b?DNLuXi+Y822S)Uj?2h=CVP+6bApGJKe=^g)U>FJ5Jm*tw1`{Nw4yYI5a zFCxDirz+#;xHch}FUcxCt z@az!6=S}#!38y%W_zDxgXu>y4$hBYI;l}*~lAjs=su_L+a1HsJ@Fm9QqFtc!m|ngK zx0rCZ37;o~;PP8DJR8Cf>2*RZv|eV0?>6CsX8bP!nVvX#p8_^4;JXGCrU8w$6wsm= za=`&na)AKJApuj?N;TFZC@Vp{k}?udvQYyiWgwuW>@$K8G7sB3#}j;3rA)&$2FfrP zs-?^#Wi|ABDXXCkfmF&E5PwYLAbL*iZUzZnQPjKWo_ z(=XqNNvQmK4BgY9YcgpF6c0cA@?DuY+UmCg$@G{!`ML2cz)w8`uZZA3c`w@_scFkb#% zx9~&vj?3@k1o@R>Kv4Ok{uVEPwV-2PP%d8np0x18FdvuS??IPHdGk(%Z{e2*VpZN) zo1t_xrYjXQK*bNQX~6hW3px*w9A7ZBM)}dNo`F}~j)9o%Q#pkrw2oH~fo>n-$dC1? z@@FiERj#hxuzAMDnWsJ*eC}*zVH8NYscfmPaWT+z8aVfdVE1nXqBcWrVoy37{8ZJDOzBUu$M00`CutHMGngtw${MuAr(m29lXDS_uN zn>B03hK-fgIE%@d;aZk#AE9MvqaB%AmX>Xwu0a-vZ^J%;qG0IQmpYUT^ b$|*mF{sDB|iok@52O;uXr_iJuti1mpW@Tyz literal 0 HcmV?d00001 diff --git a/components/flash/mflash/mcxnx4x/mflash_drv.c b/components/flash/mflash/mcxnx4x/mflash_drv.c new file mode 100644 index 000000000..0d8ef3965 --- /dev/null +++ b/components/flash/mflash/mcxnx4x/mflash_drv.c @@ -0,0 +1,84 @@ +/* + * Copyright 2017-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "mflash_drv.h" +#include "fsl_flash.h" +#include "pin_mux.h" + +static flash_config_t g_flash_instance = {0}; + +static uint32_t g_pflashBlockBase = 0; +static uint32_t g_pflashTotalSize = 0; +static uint32_t g_pflashSectorSize = 0; +static uint32_t g_pflashPageSize = 0; + +/* API - initialize 'mflash' */ +int32_t mflash_drv_init(void) +{ + status_t result; + + result = FLASH_Init(&g_flash_instance); + if (result != kStatus_Success) + return result; + + result = FLASH_GetProperty(&g_flash_instance, kFLASH_PropertyPflashBlockBaseAddr, &g_pflashBlockBase); + if (result != kStatus_Success) + return result; + + result = FLASH_GetProperty(&g_flash_instance, kFLASH_PropertyPflashSectorSize, &g_pflashSectorSize); + if (result != kStatus_Success) + return result; + + result = FLASH_GetProperty(&g_flash_instance, kFLASH_PropertyPflashTotalSize, &g_pflashTotalSize); + if (result != kStatus_Success) + return result; + + result = FLASH_GetProperty(&g_flash_instance, kFLASH_PropertyPflashPageSize, &g_pflashPageSize); + + return result; +} + +/* API - Erase single sector */ +int32_t mflash_drv_sector_erase(uint32_t sector_addr) +{ + if (0 == mflash_drv_is_sector_aligned(sector_addr)) + return kStatus_InvalidArgument; + + return FLASH_Erase(&g_flash_instance, sector_addr, MFLASH_SECTOR_SIZE, (uint32_t)kFLASH_ApiEraseKey); +} + +/* API - Page program */ +int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data) +{ + if (0 == mflash_drv_is_page_aligned(page_addr)) + return kStatus_InvalidArgument; + + return FLASH_Program(&g_flash_instance, page_addr, (uint8_t *)data, MFLASH_PAGE_SIZE); +} + +/* API - Read data */ +int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len) +{ + (void)memcpy(buffer, (void *)addr, len); + return kStatus_Success; +} + +/* API - Get pointer to FLASH region */ +void *mflash_drv_phys2log(uint32_t addr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return (void *)(addr); +} + +/* API - Get pointer to FLASH region */ +uint32_t mflash_drv_log2phys(void *ptr, uint32_t len) +{ + /* FLASH is directly mapped in the address space */ + return ((uint32_t)ptr); +} diff --git a/components/flash/mflash/mcxnx4x/mflash_drv.h b/components/flash/mflash/mcxnx4x/mflash_drv.h new file mode 100644 index 000000000..840091252 --- /dev/null +++ b/components/flash/mflash/mcxnx4x/mflash_drv.h @@ -0,0 +1,32 @@ +/* + * Copyright 2017-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MFLASH_DRV_H__ +#define __MFLASH_DRV_H__ + +#include "mflash_common.h" + +/* Flash constants */ +#ifndef MFLASH_SECTOR_SIZE +#define MFLASH_SECTOR_SIZE (8192) +#endif + +#ifndef MFLASH_PAGE_SIZE +#define MFLASH_PAGE_SIZE (128) +#endif + +#ifndef MFLASH_BASE_ADDRESS +#define MFLASH_BASE_ADDRESS (0) +#endif + +#define MFLASH_PAGE_INTEGRITY_CHECKS (1) + +static inline int32_t mflash_drv_is_readable(uint32_t addr) +{ + return kStatus_Success; +} + +#endif diff --git a/components/flash/nor/lpspi/fsl_lpspi_nor_flash.c b/components/flash/nor/lpspi/fsl_lpspi_nor_flash.c index 3fa2aaf26..ee9c7de89 100644 --- a/components/flash/nor/lpspi/fsl_lpspi_nor_flash.c +++ b/components/flash/nor/lpspi/fsl_lpspi_nor_flash.c @@ -463,3 +463,52 @@ status_t Nor_Flash_Is_Busy(nor_handle_t *handle, bool *isBusy) return status; } + +status_t Nor_Flash_Enter_Lowpower(nor_handle_t *handle) +{ + status_t status = kStatus_Fail; + bool busy; + + assert(handle); + + do + { + /* Make sure the flash is not busy */ + (void)Nor_Flash_Is_Busy(handle, &busy); + } while (busy == true); + + status = Nor_Flash_DeInit(handle); + + return status; +} + +status_t Nor_Flash_Exit_Lowpower(nor_handle_t *handle) +{ + assert(handle); + + uint32_t baudRate = BOARD_GetNorFlashBaudrate(); + status_t initStatus = kStatus_Fail; + + handle->bytesInSectorSize = 256U; + handle->bytesInPageSize = 256U; + handle->driverBaseAddr = BOARD_GetLpspiForNorFlash(); + + do + { + uint32_t spiClock_Hz = BOARD_GetLpspiClock(); + + spi_master_config_t spiMasterCfg; + spiMasterCfg.baudRate = baudRate; + spiMasterCfg.clockFreq = spiClock_Hz; + spiMasterCfg.whichPcs = 0; + status_t status = LPSPI_MemInit(&spiMasterCfg, handle->driverBaseAddr); + if (status != kStatus_Success) + { + break; + } + + initStatus = kStatus_Success; + } while (false); + + return initStatus; +} \ No newline at end of file diff --git a/components/flash/nor/lpspi/fsl_lpspi_nor_flash.h b/components/flash/nor/lpspi/fsl_lpspi_nor_flash.h index 1bd67a599..be0815fcb 100644 --- a/components/flash/nor/lpspi/fsl_lpspi_nor_flash.h +++ b/components/flash/nor/lpspi/fsl_lpspi_nor_flash.h @@ -55,6 +55,22 @@ status_t Nor_Flash_Erase_Block_32K(nor_handle_t *handle, uint32_t address); */ status_t Nor_Flash_Erase_Block_64K(nor_handle_t *handle, uint32_t address); +/*! + * @brief Prepare the NOR flash for low power entry + * + * @param handle The NOR Flash handler. + * @retval status_t execution status + */ +status_t Nor_Flash_Enter_Lowpower(nor_handle_t *handle); + +/*! + * @brief Prepare the NOR flash for low power exit + * + * @param handle The NOR Flash handler. + * @retval status_t execution status + */ +status_t Nor_Flash_Exit_Lowpower(nor_handle_t *handle); + #ifdef __cplusplus } #endif diff --git a/components/ft5406_rt/fsl_ft5406_rt.c b/components/ft5406_rt/fsl_ft5406_rt.c index c8ec4363e..7525b999f 100644 --- a/components/ft5406_rt/fsl_ft5406_rt.c +++ b/components/ft5406_rt/fsl_ft5406_rt.c @@ -26,10 +26,12 @@ typedef struct _ft5406_rt_touch_data ft5406_rt_touch_point_t TOUCH[FT5406_RT_MAX_TOUCHES]; } ft5406_rt_touch_data_t; -#define TOUCH_POINT_GET_EVENT(T) ((touch_event_t)((T).XH >> 6)) -#define TOUCH_POINT_GET_ID(T) ((T).YH >> 4) -#define TOUCH_POINT_GET_X(T) ((((T).XH & 0x0f) << 8) | (T).XL) -#define TOUCH_POINT_GET_Y(T) ((((T).YH & 0x0f) << 8) | (T).YL) +#define TOUCH_POINT_GET_EVENT(T) ((T).XH >> 6U) +#define TOUCH_POINT_GET_ID(T) ((T).YH >> 4U) +#define TOUCH_POINT_GET_X(T) ((((uint16_t)(T).XH & 0x0fU) << 8U) | (T).XL) +#define TOUCH_POINT_GET_Y(T) ((((uint16_t)(T).YH & 0x0fU) << 8U) | (T).YL) + +static status_t FT5406_RT_ReadTouchData(ft5406_rt_handle_t *handle); status_t FT5406_RT_Init(ft5406_rt_handle_t *handle, LPI2C_Type *base) { @@ -37,10 +39,7 @@ status_t FT5406_RT_Init(ft5406_rt_handle_t *handle, LPI2C_Type *base) status_t status; uint8_t mode; - assert(handle); - assert(base); - - if (!handle || !base) + if ((NULL == handle) || (NULL == base)) { return kStatus_InvalidArgument; } @@ -48,8 +47,8 @@ status_t FT5406_RT_Init(ft5406_rt_handle_t *handle, LPI2C_Type *base) handle->base = base; /* clear transfer structure and buffer */ - memset(xfer, 0, sizeof(*xfer)); - memset(handle->touch_buf, 0, FT5406_RT_TOUCH_DATA_LEN); + (void)memset(xfer, 0, sizeof(*xfer)); + (void)memset(handle->touch_buf, 0, FT5406_RT_TOUCH_DATA_LEN); /* set device mode to normal operation */ mode = 0; @@ -59,7 +58,7 @@ status_t FT5406_RT_Init(ft5406_rt_handle_t *handle, LPI2C_Type *base) xfer->subaddressSize = 1; xfer->data = &mode; xfer->dataSize = 1; - xfer->flags = kLPI2C_TransferDefaultFlag; + xfer->flags = (uint32_t)kLPI2C_TransferDefaultFlag; status = LPI2C_MasterTransferBlocking(handle->base, &handle->xfer); @@ -70,16 +69,14 @@ status_t FT5406_RT_Init(ft5406_rt_handle_t *handle, LPI2C_Type *base) xfer->subaddressSize = 1; xfer->data = handle->touch_buf; xfer->dataSize = FT5406_RT_TOUCH_DATA_LEN; - xfer->flags = kLPI2C_TransferDefaultFlag; + xfer->flags = (uint32_t)kLPI2C_TransferDefaultFlag; return status; } status_t FT5406_RT_Denit(ft5406_rt_handle_t *handle) { - assert(handle); - - if (!handle) + if (NULL == handle) { return kStatus_InvalidArgument; } @@ -88,11 +85,9 @@ status_t FT5406_RT_Denit(ft5406_rt_handle_t *handle) return kStatus_Success; } -status_t FT5406_RT_ReadTouchData(ft5406_rt_handle_t *handle) +static status_t FT5406_RT_ReadTouchData(ft5406_rt_handle_t *handle) { - assert(handle); - - if (!handle) + if (NULL == handle) { return kStatus_InvalidArgument; } @@ -111,22 +106,23 @@ status_t FT5406_RT_GetSingleTouch(ft5406_rt_handle_t *handle, touch_event_t *tou { ft5406_rt_touch_data_t *touch_data = (ft5406_rt_touch_data_t *)(void *)(handle->touch_buf); - if (touch_event == NULL) + touch_event_local = (touch_event_t)(uint8_t)TOUCH_POINT_GET_EVENT(touch_data->TOUCH[0]); + + if (touch_event != NULL) { - touch_event = &touch_event_local; + *touch_event = touch_event_local; } - *touch_event = TOUCH_POINT_GET_EVENT(touch_data->TOUCH[0]); /* Update coordinates only if there is touch detected */ - if ((*touch_event == kTouch_Down) || (*touch_event == kTouch_Contact)) + if ((touch_event_local == kTouch_Down) || (touch_event_local == kTouch_Contact)) { - if (touch_x) + if (NULL != touch_x) { - *touch_x = TOUCH_POINT_GET_X(touch_data->TOUCH[0]); + *touch_x = (int)(uint16_t)TOUCH_POINT_GET_X(touch_data->TOUCH[0]); } - if (touch_y) + if (NULL != touch_y) { - *touch_y = TOUCH_POINT_GET_Y(touch_data->TOUCH[0]); + *touch_y = (int)(uint16_t)TOUCH_POINT_GET_Y(touch_data->TOUCH[0]); } } } @@ -145,25 +141,25 @@ status_t FT5406_RT_GetMultiTouch(ft5406_rt_handle_t *handle, if (status == kStatus_Success) { ft5406_rt_touch_data_t *touch_data = (ft5406_rt_touch_data_t *)(void *)(handle->touch_buf); - int i; + unsigned int i; /* Check for valid number of touches - otherwise ignore touch information */ if (touch_data->TD_STATUS > FT5406_RT_MAX_TOUCHES) { - touch_data->TD_STATUS = 0; + touch_data->TD_STATUS = 0U; } /* Decode number of touches */ - if (touch_count) + if (NULL != touch_count) { - *touch_count = touch_data->TD_STATUS; + *touch_count = (int)touch_data->TD_STATUS; } /* Decode valid touch points */ for (i = 0; i < touch_data->TD_STATUS; i++) { touch_array[i].TOUCH_ID = TOUCH_POINT_GET_ID(touch_data->TOUCH[i]); - touch_array[i].TOUCH_EVENT = TOUCH_POINT_GET_EVENT(touch_data->TOUCH[i]); + touch_array[i].TOUCH_EVENT = (touch_event_t)(uint8_t)TOUCH_POINT_GET_EVENT(touch_data->TOUCH[i]); touch_array[i].TOUCH_X = TOUCH_POINT_GET_X(touch_data->TOUCH[i]); touch_array[i].TOUCH_Y = TOUCH_POINT_GET_Y(touch_data->TOUCH[i]); } diff --git a/components/gpio/fsl_adapter_gpio.c b/components/gpio/fsl_adapter_gpio.c index 1b21e2249..5bae1ff8a 100644 --- a/components/gpio/fsl_adapter_gpio.c +++ b/components/gpio/fsl_adapter_gpio.c @@ -8,7 +8,7 @@ #include "fsl_device_registers.h" #include "fsl_gpio.h" #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ - defined(FSL_FEATURE_SOC_PORT_COUNT) + defined(FSL_FEATURE_SOC_PORT_COUNT) #include "fsl_port.h" #endif #include "fsl_adapter_gpio.h" @@ -95,7 +95,7 @@ static void HAL_GpioInterruptHandle(uint8_t port) head = s_GpioHead; #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ - defined(FSL_FEATURE_SOC_PORT_COUNT) + defined(FSL_FEATURE_SOC_PORT_COUNT) pinInterruptSetFlag = GPIO_PortGetInterruptFlags(s_GpioPort[port]); /* Clear external interrupt flag. */ GPIO_PortClearInterruptFlags(s_GpioPort[port], pinInterruptSetFlag); @@ -508,6 +508,42 @@ void GPIO101_IRQHandler(void) } #endif +#if (FSL_FEATURE_SOC_GPIO_COUNT > 0U) +void GPIO0_IRQHandler(void); +void GPIO0_IRQHandler(void) +{ + HAL_GpioInterruptHandle(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_SOC_GPIO_COUNT > 1U) +void GPIO1_IRQHandler(void); +void GPIO1_IRQHandler(void) +{ + HAL_GpioInterruptHandle(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_SOC_GPIO_COUNT > 2U) +void GPIO2_IRQHandler(void); +void GPIO2_IRQHandler(void) +{ + HAL_GpioInterruptHandle(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_SOC_GPIO_COUNT > 3U) +void GPIO3_IRQHandler(void); +void GPIO3_IRQHandler(void) +{ + HAL_GpioInterruptHandle(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + #endif void HAL_GpioPreInit(void) @@ -624,7 +660,7 @@ hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_ hal_gpio_state_t *gpioState; #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ defined(FSL_FEATURE_SOC_PORT_COUNT) - PORT_Type *portList[] = PORT_BASE_PTRS; + PORT_Type *portList[] = PORT_BASE_PTRS; static const IRQn_Type irqNo[] = PORT_IRQS; port_interrupt_t pinInt; #else @@ -654,11 +690,11 @@ hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_ #else pinInt = kGPIO_InterruptLogicOne; #endif - break; + break; case kHAL_GpioInterruptRisingEdge: #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ defined(FSL_FEATURE_SOC_PORT_COUNT) - pinInt = kPORT_InterruptRisingEdge; + pinInt = kPORT_InterruptRisingEdge; #else pinInt = kGPIO_InterruptRisingEdge; #endif @@ -666,7 +702,7 @@ hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_ case kHAL_GpioInterruptFallingEdge: #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ defined(FSL_FEATURE_SOC_PORT_COUNT) - pinInt = kPORT_InterruptFallingEdge; + pinInt = kPORT_InterruptFallingEdge; #else pinInt = kGPIO_InterruptFallingEdge; #endif @@ -682,7 +718,7 @@ hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_ default: #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ defined(FSL_FEATURE_SOC_PORT_COUNT) - pinInt = kPORT_InterruptOrDMADisabled; + pinInt = kPORT_InterruptOrDMADisabled; #else pinInt = kGPIO_InterruptStatusFlagDisabled; #endif @@ -694,9 +730,9 @@ hal_gpio_status_t HAL_GpioSetTriggerMode(hal_gpio_handle_t gpioHandle, hal_gpio_ /* initialize port interrupt */ #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ defined(FSL_FEATURE_SOC_PORT_COUNT) - PORT_SetPinInterruptConfig(portList[gpioState->port], gpioState->pin, pinInt); + PORT_SetPinInterruptConfig(portList[gpioState->port], gpioState->pin, pinInt); #else - GPIO_SetPinInterruptConfig(s_GpioPort[gpioState->port], gpioState->pin, pinInt); + GPIO_SetPinInterruptConfig(s_GpioPort[gpioState->port], gpioState->pin, pinInt); #endif NVIC_SetPriority(irqNo[gpioState->port], HAL_GPIO_ISR_PRIORITY); NVIC_EnableIRQ(irqNo[gpioState->port]); diff --git a/components/i2c/fsl_adapter_i2c.h b/components/i2c/fsl_adapter_i2c.h index 99dc3bd39..e09437f05 100644 --- a/components/i2c/fsl_adapter_i2c.h +++ b/components/i2c/fsl_adapter_i2c.h @@ -232,7 +232,7 @@ extern "C" { * #HAL_I2C_MASTER_HANDLE_DEFINE(handle); * or * uint32_t handle[((HAL_I2C_MASTER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; - * @param config A pointer to the master configuration structure + * @param halI2cConfig A pointer to the master configuration structure * @retval kStatus_HAL_I2cError An error occurred. * @retval kStatus_HAL_I2cSuccess i2c master initialization succeed */ @@ -265,7 +265,7 @@ hal_i2c_status_t HAL_I2cMasterInit(hal_i2c_master_handle_t handle, const hal_i2c * #HAL_I2C_SLAVE_HANDLE_DEFINE(handle); * or * uint32_t handle[((HAL_I2C_SLAVE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; - * @param config A pointer to the slave configuration structure + * @param halI2cConfig A pointer to the slave configuration structure * @retval kStatus_HAL_I2cError An error occurred. * @retval kStatus_HAL_I2cSuccess i2c slave initialization succeed */ diff --git a/components/i2c/fsl_adapter_lpi2c.c b/components/i2c/fsl_adapter_lpi2c.c index e739f5060..53dd98e8f 100644 --- a/components/i2c/fsl_adapter_lpi2c.c +++ b/components/i2c/fsl_adapter_lpi2c.c @@ -93,7 +93,10 @@ static hal_i2c_status_t HAL_I2cGetStatus(status_t status) return returnStatus; } -static void HAL_I2cMasterCallback(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t status, void *callbackParam) +static void HAL_I2cMasterCallback(LPI2C_Type *lpi2cBase, + lpi2c_master_handle_t *handle, + status_t status, + void *callbackParam) { hal_i2c_master_t *i2cMasterHandle; assert(NULL != callbackParam); @@ -106,7 +109,7 @@ static void HAL_I2cMasterCallback(LPI2C_Type *base, lpi2c_master_handle_t *handl } } -static void HAL_I2cSlaveCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, void *callbackParam) +static void HAL_I2cSlaveCallback(LPI2C_Type *lpi2cBase, lpi2c_slave_transfer_t *xfer, void *callbackParam) { hal_i2c_slave_t *i2cSlaveHandle; assert(NULL != callbackParam); @@ -126,44 +129,44 @@ static void HAL_I2cSlaveCallback(LPI2C_Type *base, lpi2c_slave_transfer_t *xfer, } } -hal_i2c_status_t HAL_I2cMasterInit(hal_i2c_master_handle_t handle, const hal_i2c_master_config_t *config) +hal_i2c_status_t HAL_I2cMasterInit(hal_i2c_master_handle_t handle, const hal_i2c_master_config_t *halI2cConfig) { hal_i2c_master_t *i2cMasterHandle; lpi2c_master_config_t i2cConfig; assert(NULL != handle); - assert(NULL != config); + assert(NULL != halI2cConfig); assert(HAL_I2C_MASTER_HANDLE_SIZE >= sizeof(hal_i2c_master_t)); i2cMasterHandle = (hal_i2c_master_t *)handle; LPI2C_MasterGetDefaultConfig(&i2cConfig); - i2cConfig.enableMaster = config->enableMaster; - i2cConfig.baudRate_Hz = config->baudRate_Bps; - i2cMasterHandle->instance = config->instance; + i2cConfig.enableMaster = halI2cConfig->enableMaster; + i2cConfig.baudRate_Hz = halI2cConfig->baudRate_Bps; + i2cMasterHandle->instance = halI2cConfig->instance; - LPI2C_MasterInit(s_i2cBases[i2cMasterHandle->instance], &i2cConfig, config->srcClock_Hz); + LPI2C_MasterInit(s_i2cBases[i2cMasterHandle->instance], &i2cConfig, halI2cConfig->srcClock_Hz); return kStatus_HAL_I2cSuccess; } -hal_i2c_status_t HAL_I2cSlaveInit(hal_i2c_slave_handle_t handle, const hal_i2c_slave_config_t *config) +hal_i2c_status_t HAL_I2cSlaveInit(hal_i2c_slave_handle_t handle, const hal_i2c_slave_config_t *halI2cConfig) { hal_i2c_slave_t *i2cSlaveHandle; lpi2c_slave_config_t i2cConfig; assert(NULL != handle); - assert(NULL != config); + assert(NULL != halI2cConfig); assert(HAL_I2C_SLAVE_HANDLE_SIZE >= sizeof(hal_i2c_slave_t)); i2cSlaveHandle = (hal_i2c_slave_t *)handle; LPI2C_SlaveGetDefaultConfig(&i2cConfig); - i2cConfig.enableSlave = config->enableSlave; - i2cConfig.address0 = (uint8_t)config->slaveAddress; - i2cSlaveHandle->instance = config->instance; + i2cConfig.enableSlave = halI2cConfig->enableSlave; + i2cConfig.address0 = (uint8_t)halI2cConfig->slaveAddress; + i2cSlaveHandle->instance = halI2cConfig->instance; - LPI2C_SlaveInit(s_i2cBases[i2cSlaveHandle->instance], &i2cConfig, config->srcClock_Hz); + LPI2C_SlaveInit(s_i2cBases[i2cSlaveHandle->instance], &i2cConfig, halI2cConfig->srcClock_Hz); return kStatus_HAL_I2cSuccess; } diff --git a/components/i3c_bus/fsl_component_i3c.h b/components/i3c_bus/fsl_component_i3c.h index c832dd716..004f1d2dd 100644 --- a/components/i3c_bus/fsl_component_i3c.h +++ b/components/i3c_bus/fsl_component_i3c.h @@ -54,7 +54,7 @@ #define I3C_BUS_CCC_SETMRL(isDirect) I3C_BUS_CCC(0xaU, isDirect) /*!< Set Max Read Length Command. */ #define I3C_BUS_CCC_SETXTIME(isDirect) (isDirect) ? 0x98U : 0x28U /*!< Set Exchange Timing Information Command. */ #define I3C_BUS_CCC_VENDOR_EXT(cmdID, isDirect) \ - ((cmdID) + ((isDirect) ? 0xe0U : 0x61U)) /*!< Vendor Extension Command. */ + ((cmdID) + ((isDirect) ? 0xe0U : 0x61U)) /*!< Vendor Extension Command. */ /* CCC available only for broadcast access */ #define I3C_BUS_CCC_ENTDAA 0x7U /*!< Enter Dynamic Address Assignment Command. */ @@ -112,7 +112,7 @@ enum kStatus_I3CBus_Success = kStatus_Success, /*!< I3C Bus operation succeed*/ kStatus_I3CBus_AddrSlotInvalid = MAKE_STATUS(kStatusGroup_I3CBUS, 0U), /*!< I3C Bus address slot invalid */ kStatus_I3CBus_MasterOpsUnsupport = - MAKE_STATUS(kStatusGroup_I3CBUS, 1U), /*!< I3C Bus master operation unsupported */ + MAKE_STATUS(kStatusGroup_I3CBUS, 1U), /*!< I3C Bus master operation unsupported */ kStatus_I3CBus_NotCurrentMaster = MAKE_STATUS( kStatusGroup_I3CBUS, 2U), /*!< The Bus operation should be made on master but current device is not master */ kStatus_I3CBus_MasterOpsFailure = MAKE_STATUS(kStatusGroup_I3CBUS, 3U), /*!< Bus operation failure */ @@ -210,7 +210,7 @@ typedef struct i3c_device_hw_ops bool (*CheckSupportCCC)(i3c_device_t *master, i3c_ccc_cmd_t *cmd); /*!< CheckSupportCCC function, optional for I3C master device, not require for slave device.*/ status_t (*TransmitCCC)(i3c_device_t *master, - i3c_ccc_cmd_t *cmd); /*!< TransmitCCC function, only require for I3C master device.*/ + i3c_ccc_cmd_t *cmd); /*!< TransmitCCC function, only require for I3C master device.*/ status_t (*DoI3CTransfer)( i3c_device_t *dev, i3c_bus_transfer_t *xfer); /*!< DoI3CTransfer function, only require for I3C master device.*/ status_t (*DoI2CTransfer)( @@ -284,7 +284,7 @@ typedef struct _i3c_bus_config /*! @brief I3C bus structure, contains bus mandatory informations.*/ struct _i3c_bus { - i3c_device_t *volatile currentMaster; /*!< Pointer to current I3C master on bus. */ + i3c_device_t *volatile currentMaster; /*!< Pointer to current I3C master on bus. */ uint32_t addrSlots[((I3C_BUS_MAX_ADDR + 1U) * I3C_BUS_ADDR_SLOTWIDTH) / I3C_BUS_ADDR_SLOTDEPTH]; /*!< I3C bus address pool. */ i3c_bus_mode_t busMode; /*!< I3C bus mode. */ @@ -301,8 +301,8 @@ typedef struct _i3c_ccc_dev uint8_t dynamicAddr; /*!< Dynamic address for I3C device. */ union { - uint8_t dcr; /*!< Device Characteristics register value for I3C device. */ - uint8_t lvr; /*!< Legacy Virtual Register value for I2C device */ + uint8_t dcr; /*!< Device Characteristics register value for I3C device. */ + uint8_t lvr; /*!< Legacy Virtual Register value for I2C device */ }; uint8_t bcr; /*!< Bus characteristics register value. */ uint8_t staticAddr; /*!< Static address for I3C/I2C device. */ diff --git a/components/i3c_bus/fsl_component_i3c_adapter.c b/components/i3c_bus/fsl_component_i3c_adapter.c index fa8aea909..029d7b1f9 100644 --- a/components/i3c_bus/fsl_component_i3c_adapter.c +++ b/components/i3c_bus/fsl_component_i3c_adapter.c @@ -62,16 +62,16 @@ const i3c_device_hw_ops_t master_ops = {.Init = I3C_MasterAdapterIn .RequestIBI = I3C_SlaveAdapterRequestIBI}; const i3c_device_hw_ops_t slave_ops = {.Init = I3C_SlaveAdapterInit, - .Deinit = NULL, - .ProceedDAA = NULL, - .CheckSupportCCC = NULL, - .TransmitCCC = NULL, - .DoI3CTransfer = NULL, - .DoI2CTransfer = NULL, - .RegisterIBI = NULL, - .HotJoin = I3C_SlaveAdapterRequestHotJoin, - .RequestMastership = I3C_SlaveAdapterRequestMastership, - .RequestIBI = I3C_SlaveAdapterRequestIBI}; + .Deinit = NULL, + .ProceedDAA = NULL, + .CheckSupportCCC = NULL, + .TransmitCCC = NULL, + .DoI3CTransfer = NULL, + .DoI2CTransfer = NULL, + .RegisterIBI = NULL, + .HotJoin = I3C_SlaveAdapterRequestHotJoin, + .RequestMastership = I3C_SlaveAdapterRequestMastership, + .RequestIBI = I3C_SlaveAdapterRequestIBI}; static const i3c_master_transfer_callback_t masterCallback = {.slave2Master = i3c_slave2master_callback, .ibiCallback = i3c_master_ibi_callback, .transferComplete = i3c_master_callback}; @@ -264,16 +264,17 @@ static status_t I3C_MasterAdapterInit(i3c_device_t *master) static status_t I3C_MasterAdapterProcessDAA(i3c_device_t *master) { assert(master != NULL); + status_t result = kStatus_Success; i3c_device_control_info_t *masterControlInfo = master->devControlInfo; i3c_master_adapter_resource_t *masterResource = (i3c_master_adapter_resource_t *)masterControlInfo->resource; I3C_Type *base = masterResource->base; - status_t result = kStatus_Success; - uint32_t status; - uint32_t errStatus; - size_t rxCount; uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; - uint8_t rxSize = 0; i3c_bus_t *i3cBus = master->bus; + bool mctrlDone = false; + uint8_t rxSize = 0; + uint32_t errStatus; + uint32_t status; + size_t rxCount; /* Return an error if the bus is already in use not by us. */ result = I3C_CheckForBusyBus(base); @@ -295,55 +296,64 @@ static status_t I3C_MasterAdapterProcessDAA(i3c_device_t *master) do { - do + status = I3C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) { - status = I3C_MasterGetStatusFlags(base); - I3C_MasterGetFifoCounts(base, &rxCount, NULL); + return result; + } - /* Check for error flags. */ - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); - if (kStatus_Success != result) + if ((!mctrlDone) || (rxSize < 8U)) + { + I3C_MasterGetFifoCounts(base, &rxCount, NULL); + while (rxCount-- != 0U) { - return result; + rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); } - if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U)) + if ((status & (uint32_t)kI3C_MasterControlDoneFlag) != 0U) { - rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + mctrlDone = true; } - } while ((status & (uint32_t)kI3C_MasterControlDoneFlag) != (uint32_t)kI3C_MasterControlDoneFlag); - - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); - - if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && + } + else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) { - rxSize = 0; - uint8_t validAddr = I3C_BusGetValidAddrSlot(i3cBus, 0x0); if (validAddr < I3C_BUS_MAX_ADDR) { + /* Assign the dynamic address. */ + base->MWDATAB = validAddr; + /* Emit process DAA again. */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + i3c_device_t *newI3CDev = malloc(sizeof(i3c_device_t)); (void)memset(newI3CDev, 0, sizeof(i3c_device_t)); - newI3CDev->info.dynamicAddr = validAddr; newI3CDev->info.vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; newI3CDev->info.partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); newI3CDev->info.bcr = rxBuffer[6]; newI3CDev->info.dcr = rxBuffer[7]; - base->MWDATAB = validAddr; - I3C_BusAddI3CDev(i3cBus, newI3CDev); - /* Emit process DAA again. */ - I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + /* Ready to handle next device. */ + mctrlDone = false; + rxSize = 0; } else { return kStatus_I3CBus_AddrSlotInvalid; } } + else + { + /* Intentional empty */ + } } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); @@ -432,7 +442,7 @@ static status_t I3C_MasterAdapterTransmitCCC(i3c_device_t *master, i3c_ccc_cmd_t xfer.dataSize = cmd->dataSize; xfer.direction = cmd->isRead ? kI3C_Read : kI3C_Write; xfer.busType = kI3C_TypeI3CSdr; - xfer.flags = (uint32_t)kI3C_TransferDefaultFlag; + xfer.flags = (uint32_t)kI3C_TransferDisableRxTermFlag; result = I3CMasterAdapterTransfer(base, &xfer, transMode); if (result != kStatus_Success) { @@ -458,7 +468,7 @@ static status_t I3C_MasterAdapterTransmitCCC(i3c_device_t *master, i3c_ccc_cmd_t xfer.dataSize = cmd->dataSize; xfer.direction = cmd->isRead ? kI3C_Read : kI3C_Write; xfer.busType = kI3C_TypeI3CSdr; - xfer.flags = (uint32_t)kI3C_TransferRepeatedStartFlag; + xfer.flags = (uint32_t)kI3C_TransferRepeatedStartFlag | kI3C_TransferDisableRxTermFlag; result = I3CMasterAdapterTransfer(base, &xfer, transMode); if (result != kStatus_Success) { diff --git a/components/led/fsl_component_led.c b/components/led/fsl_component_led.c index 36ae5101e..d75ed3c35 100644 --- a/components/led/fsl_component_led.c +++ b/components/led/fsl_component_led.c @@ -19,16 +19,11 @@ ******************************************************************************/ #if defined(OSA_USED) #include "fsl_os_abstraction.h" -#if (defined(USE_RTOS) && (USE_RTOS > 0U)) #define LED_ENTER_CRITICAL() \ OSA_SR_ALLOC(); \ OSA_ENTER_CRITICAL() #define LED_EXIT_CRITICAL() OSA_EXIT_CRITICAL() #else -#define LED_ENTER_CRITICAL() -#define LED_EXIT_CRITICAL() -#endif -#else #define LED_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); #define LED_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); #endif @@ -36,8 +31,8 @@ /* LED control type enumeration */ typedef enum _led_control_type { - kLED_TurnOffOn = 0x01U, /*!< Turn Off or on*/ - kLED_Flash, /*!< Flash */ + kLED_TurnOffOn = 0x01U, /*!< Turn Off or on*/ + kLED_Flash, /*!< Flash */ #if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) kLED_TricolorCycleFlash, /*!< Tricolor Cycle Flash */ kLED_CycleFlash, /*!< Cycle Flash */ @@ -220,7 +215,7 @@ static void LED_TimerEvent(void *param) { switch (ledState->controlType) { - case (uint16_t)kLED_Flash: /*!< Flash */ + case (uint16_t)kLED_Flash: /*!< Flash */ #if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) case (uint16_t)kLED_TricolorCycleFlash: /*!< Tricolor Cycle Flash */ case (uint16_t)kLED_CycleFlash: /*!< Cycle Flash */ @@ -353,7 +348,7 @@ led_status_t LED_Init(led_handle_t ledHandle, const led_config_t *ledConfig) /* The configure parameters check only work on debug mode in order to reduce code size. */ #ifdef NDEBUG #else /* NDEBUG */ - uint8_t rgbFlag = 0; + uint8_t rgbFlag = 0; uint8_t rgbDimmingFlag = 0; #endif /* NDEBUG */ #endif @@ -435,19 +430,19 @@ led_status_t LED_Init(led_handle_t ledHandle, const led_config_t *ledConfig) hal_pwm_setup_config_t setupConfig; #if (defined(LED_USE_CONFIGURE_STRUCTURE) && (LED_USE_CONFIGURE_STRUCTURE > 0U)) #else - ledState->pins[i].config.dimmingEnable = ledRgbConfigPin[i].dimmingEnable; - ledState->pins[i].dimming.instance = ledRgbConfigPin[i].dimming.instance; - ledState->pins[i].dimming.channel = ledRgbConfigPin[i].dimming.channel; + ledState->pins[i].config.dimmingEnable = ledRgbConfigPin[i].dimmingEnable; + ledState->pins[i].dimming.instance = ledRgbConfigPin[i].dimming.instance; + ledState->pins[i].dimming.channel = ledRgbConfigPin[i].dimming.channel; ledState->pins[i].dimming.pinStateDefault = ledRgbConfigPin[i].dimming.pinStateDefault; #endif (void)HAL_PwmInit((hal_pwm_handle_t)ledState->pwmHandle[i], ledRgbConfigPin[i].dimming.instance, ledRgbConfigPin[i].dimming.sourceClock); setupConfig.dutyCyclePercent = 0; setupConfig.level = (0U != ledRgbConfigPin[i].dimming.pinStateDefault) ? - (hal_pwm_level_select_t)kHAL_PwmLowTrue : - (hal_pwm_level_select_t)kHAL_PwmHighTrue; - setupConfig.mode = kHAL_EdgeAlignedPwm; - setupConfig.pwmFreq_Hz = 1000U; + (hal_pwm_level_select_t)kHAL_PwmLowTrue : + (hal_pwm_level_select_t)kHAL_PwmHighTrue; + setupConfig.mode = kHAL_EdgeAlignedPwm; + setupConfig.pwmFreq_Hz = 1000U; (void)HAL_PwmSetupPwm(ledState->pwmHandle[i], ledRgbConfigPin[i].dimming.channel, &setupConfig); } else diff --git a/components/led/fsl_component_led.h b/components/led/fsl_component_led.h index f1e21de49..67ec0bcd6 100644 --- a/components/led/fsl_component_led.h +++ b/components/led/fsl_component_led.h @@ -111,8 +111,8 @@ typedef enum _led_flash_type { kLED_FlashOneColor = 0x00U, /*!< Fast with one color */ #if (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) - kLED_FlashColorWheel, /*!< Fast with color wheel */ -#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ + kLED_FlashColorWheel, /*!< Fast with color wheel */ +#endif /* (defined(LED_COLOR_WHEEL_ENABLEMENT) && (LED_COLOR_WHEEL_ENABLEMENT > 0U)) */ } led_flash_type_t; /*! @brief The color struct of LED */ diff --git a/components/lists/fsl_component_generic_list.c b/components/lists/fsl_component_generic_list.c index e09f38996..5644f385d 100644 --- a/components/lists/fsl_component_generic_list.c +++ b/components/lists/fsl_component_generic_list.c @@ -100,9 +100,9 @@ void LIST_Init(list_handle_t list, uint32_t max) * \remarks * ********************************************************************************** */ -list_handle_t LIST_GetList(list_element_handle_t element) +list_handle_t LIST_GetList(list_element_handle_t listElement) { - return element->list; + return listElement->list; } /*! ********************************************************************************* @@ -121,29 +121,29 @@ list_handle_t LIST_GetList(list_element_handle_t element) * \remarks * ********************************************************************************** */ -list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement) { LIST_ENTER_CRITICAL(); list_status_t listStatus = kLIST_Ok; - listStatus = LIST_Error_Check(list, element); + listStatus = LIST_Error_Check(list, listElement); if (listStatus == kLIST_Ok) /* Avoiding list status error */ { if (list->size == 0U) { - list->head = element; + list->head = listElement; } else { - list->tail->next = element; + list->tail->next = listElement; } #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) #else - element->prev = list->tail; + listElement->prev = list->tail; #endif - element->list = list; - element->next = NULL; - list->tail = element; + listElement->list = list; + listElement->next = NULL; + list->tail = listElement; list->size++; } @@ -167,30 +167,30 @@ list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) * \remarks * ********************************************************************************** */ -list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement) { LIST_ENTER_CRITICAL(); list_status_t listStatus = kLIST_Ok; - listStatus = LIST_Error_Check(list, element); + listStatus = LIST_Error_Check(list, listElement); if (listStatus == kLIST_Ok) /* Avoiding list status error */ { /* Links element to the head of the list */ if (list->size == 0U) { - list->tail = element; + list->tail = listElement; } #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) #else else { - list->head->prev = element; + list->head->prev = listElement; } - element->prev = NULL; + listElement->prev = NULL; #endif - element->list = list; - element->next = list->head; - list->head = element; + listElement->list = list; + listElement->next = list->head; + list->head = listElement; list->size++; } @@ -215,17 +215,17 @@ list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) ********************************************************************************** */ list_element_handle_t LIST_RemoveHead(list_handle_t list) { - list_element_handle_t element; + list_element_handle_t listElement; LIST_ENTER_CRITICAL(); if ((NULL == list) || (list->size == 0U)) { - element = NULL; /*LIST_ is empty*/ + listElement = NULL; /*LIST_ is empty*/ } else { - element = list->head; + listElement = list->head; list->size--; if (list->size == 0U) { @@ -235,15 +235,15 @@ list_element_handle_t LIST_RemoveHead(list_handle_t list) #else else { - element->next->prev = NULL; + listElement->next->prev = NULL; } #endif - element->list = NULL; - list->head = element->next; /*Is NULL if element is head*/ + listElement->list = NULL; + list->head = listElement->next; /*Is NULL if element is head*/ } LIST_EXIT_CRITICAL(); - return element; + return listElement; } /*! ********************************************************************************* @@ -281,9 +281,9 @@ list_element_handle_t LIST_GetHead(list_handle_t list) * \remarks * ********************************************************************************** */ -list_element_handle_t LIST_GetNext(list_element_handle_t element) +list_element_handle_t LIST_GetNext(list_element_handle_t listElement) { - return element->next; + return listElement->next; } /*! ********************************************************************************* @@ -301,12 +301,12 @@ list_element_handle_t LIST_GetNext(list_element_handle_t element) * \remarks * ********************************************************************************** */ -list_element_handle_t LIST_GetPrev(list_element_handle_t element) +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement) { #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) return NULL; #else - return element->prev; + return listElement->prev; #endif } @@ -325,53 +325,59 @@ list_element_handle_t LIST_GetPrev(list_element_handle_t element) * \remarks * ********************************************************************************** */ -list_status_t LIST_RemoveElement(list_element_handle_t element) +list_status_t LIST_RemoveElement(list_element_handle_t listElement) { list_status_t listStatus = kLIST_Ok; LIST_ENTER_CRITICAL(); - if (element->list == NULL) + if (listElement->list == NULL) { listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ } else { #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) - list_element_handle_t element_list = element->list->head; + list_element_handle_t element_list = listElement->list->head; + list_element_handle_t element_Prev = NULL; while (NULL != element_list) { - if (element->list->head == element) + if (listElement->list->head == listElement) { - element->list->head = element_list->next; + listElement->list->head = element_list->next; break; } - if (element_list->next == element) + if (element_list->next == listElement) { - element_list->next = element->next; + element_Prev = element_list; + element_list->next = listElement->next; break; } element_list = element_list->next; } + if (listElement->next == NULL) + { + listElement->list->tail = element_Prev; + } #else - if (element->prev == NULL) /*Element is head or solo*/ + if (listElement->prev == NULL) /*Element is head or solo*/ { - element->list->head = element->next; /*is null if solo*/ + listElement->list->head = listElement->next; /*is null if solo*/ } - if (element->next == NULL) /*Element is tail or solo*/ + if (listElement->next == NULL) /*Element is tail or solo*/ { - element->list->tail = element->prev; /*is null if solo*/ + listElement->list->tail = listElement->prev; /*is null if solo*/ } - if (element->prev != NULL) /*Element is not head*/ + if (listElement->prev != NULL) /*Element is not head*/ { - element->prev->next = element->next; + listElement->prev->next = listElement->next; } - if (element->next != NULL) /*Element is not tail*/ + if (listElement->next != NULL) /*Element is not tail*/ { - element->next->prev = element->prev; + listElement->next->prev = listElement->prev; } #endif - element->list->size--; - element->list = NULL; + listElement->list->size--; + listElement->list = NULL; } LIST_EXIT_CRITICAL(); @@ -396,56 +402,56 @@ list_status_t LIST_RemoveElement(list_element_handle_t element) * \remarks * ********************************************************************************** */ -list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement) { list_status_t listStatus = kLIST_Ok; LIST_ENTER_CRITICAL(); - if (element->list == NULL) + if (listElement->list == NULL) { listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ } else { - listStatus = LIST_Error_Check(element->list, newElement); + listStatus = LIST_Error_Check(listElement->list, newElement); if (listStatus == kLIST_Ok) { #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) - list_element_handle_t element_list = element->list->head; + list_element_handle_t element_list = listElement->list->head; while (NULL != element_list) { - if ((element_list->next == element) || (element_list == element)) + if ((element_list->next == listElement) || (element_list == listElement)) { - if (element_list == element) + if (element_list == listElement) { - element->list->head = newElement; + listElement->list->head = newElement; } else { element_list->next = newElement; } - newElement->list = element->list; - newElement->next = element; - element->list->size++; + newElement->list = listElement->list; + newElement->next = listElement; + listElement->list->size++; break; } element_list = element_list->next; } #else - if (element->prev == NULL) /*Element is list head*/ + if (listElement->prev == NULL) /*Element is list head*/ { - element->list->head = newElement; + listElement->list->head = newElement; } else { - element->prev->next = newElement; + listElement->prev->next = newElement; } - newElement->list = element->list; - element->list->size++; - newElement->next = element; - newElement->prev = element->prev; - element->prev = newElement; + newElement->list = listElement->list; + listElement->list->size++; + newElement->next = listElement; + newElement->prev = listElement->prev; + listElement->prev = newElement; #endif } } diff --git a/components/lists/fsl_component_generic_list.h b/components/lists/fsl_component_generic_list.h index aa468e2eb..3a16b390c 100644 --- a/components/lists/fsl_component_generic_list.h +++ b/components/lists/fsl_component_generic_list.h @@ -112,28 +112,28 @@ void LIST_Init(list_handle_t list, uint32_t max); * @brief Gets the list that contains the given element. * * - * @param element - Handle of the element. + * @param listElement - Handle of the element. * @retval NULL if element is orphan, Handle of the list the element is inserted into. */ -list_handle_t LIST_GetList(list_element_handle_t element); +list_handle_t LIST_GetList(list_element_handle_t listElement); /*! * @brief Links element to the head of the list. * * @param list - Handle of the list. - * @param element - Handle of the element. + * @param listElement - Handle of the element. * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. */ -list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement); /*! * @brief Links element to the tail of the list. * * @param list - Handle of the list. - * @param element - Handle of the element. + * @param listElement - Handle of the element. * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. */ -list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement); /*! * @brief Unlinks element from the head of the list. @@ -156,41 +156,41 @@ list_element_handle_t LIST_GetHead(list_handle_t list); /*! * @brief Gets next element handle for given element handle. * - * @param element - Handle of the element. + * @param listElement - Handle of the element. * * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. */ -list_element_handle_t LIST_GetNext(list_element_handle_t element); +list_element_handle_t LIST_GetNext(list_element_handle_t listElement); /*! * @brief Gets previous element handle for given element handle. * - * @param element - Handle of the element. + * @param listElement - Handle of the element. * * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. */ -list_element_handle_t LIST_GetPrev(list_element_handle_t element); +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement); /*! * @brief Unlinks an element from its list. * - * @param element - Handle of the element. + * @param listElement - Handle of the element. * * @retval kLIST_OrphanElement if element is not part of any list. * @retval kLIST_Ok if removal was successful. */ -list_status_t LIST_RemoveElement(list_element_handle_t element); +list_status_t LIST_RemoveElement(list_element_handle_t listElement); /*! * @brief Links an element in the previous position relative to a given member of a list. * - * @param element - Handle of the element. + * @param listElement - Handle of the element. * @param newElement - New element to insert before the given member. * * @retval kLIST_OrphanElement if element is not part of any list. * @retval kLIST_Ok if removal was successful. */ -list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement); /*! * @brief Gets the current size of a list. diff --git a/components/log/fsl_component_log.h b/components/log/fsl_component_log.h index b0a5aa192..c9c3d1017 100644 --- a/components/log/fsl_component_log.h +++ b/components/log/fsl_component_log.h @@ -79,10 +79,10 @@ typedef enum _log_status #define LOG_FILE_NAME_RECURSIVE(f, s, n) \ f(s, n) : f(s, n + 1) : f(s, n + 2) : f(s, n + 3) : f(s, n + 4) : f(s, n + 5) : f(s, n + 6) : f(s, n + 7) #define LOG_FILE_NAME_SET(f, f1, s, n) \ - f(f1, s, n) \ - : f(f1, s, n + 8) \ - : f(f1, s, n + 16) \ - : f(f1, s, n + 24) : f(f1, s, n + 32) : f(f1, s, n + 40) : f(f1, s, n + 48) : f(f1, s, n + 56) + f(f1, s, n) : \ + f(f1, s, n + 8) : \ + f(f1, s, n + 16) : \ + f(f1, s, n + 24) : f(f1, s, n + 32) : f(f1, s, n + 40) : f(f1, s, n + 48) : f(f1, s, n + 56) /*! * @brief Source file name definition * @details There is a macro \__BASE_FILE\__ could be used to get the current source file name in GCC. While diff --git a/components/mem_manager/fsl_component_mem_manager.h b/components/mem_manager/fsl_component_mem_manager.h index 57d417620..78070a500 100644 --- a/components/mem_manager/fsl_component_mem_manager.h +++ b/components/mem_manager/fsl_component_mem_manager.h @@ -1,5 +1,5 @@ /* - * Copyright 2018, 2020 NXP + * Copyright 2018, 2020, 2023 NXP * All rights reserved. * * @@ -36,10 +36,9 @@ * By Default, Minimal heap size is set to 4 bytes (unlikely enough to have application work correctly) */ #if !defined(MinimalHeapSize_c) -#define MinimalHeapSize_c (uint32_t)4 +#define MinimalHeapSize_c (uint32_t)4 #endif - /*! * @brief Configures the memory manager light enable. */ @@ -204,6 +203,29 @@ typedef enum mem_alloc_test_status } mem_alloc_test_status_t; #endif +#ifdef MEM_STATISTICS +#define MML_INTERNAL_STRUCT_SZ (2 * sizeof(uint32_t) + 48) +#else +#define MML_INTERNAL_STRUCT_SZ (2 * sizeof(uint32_t)) +#endif + +#define AREA_FLAGS_POOL_NOT_SHARED (1u << 0) +#define AREA_FLAGS_VALID_MASK (AREA_FLAGS_POOL_NOT_SHARED) +#define AREA_FLAGS_RFFU ~(AREA_FLAGS_VALID_MASK) + +/**@brief Memory user config. */ +typedef struct _mem_area_cfg_s memAreaCfg_t; +struct _mem_area_cfg_s +{ + memAreaCfg_t *next; /*< Next registered RAM area descriptor. */ + void *start_address; /*< Start address of RAM area. */ + void *end_address; /*< Size of registered RAM area. */ + uint16_t flags; /*< BIT(0) AREA_FLAGS_POOL_NOT_SHARED means not member of default pool, other bits RFFU */ + uint16_t reserved; /*< 16 bit padding */ + uint32_t low_watermark; /*< lowest level of number of free bytes */ + uint8_t internal_ctx[MML_INTERNAL_STRUCT_SZ]; /* Placeholder for internal allocator data */ +}; + /***************************************************************************** ****************************************************************************** * Public memory declarations @@ -323,6 +345,66 @@ void *MEM_BufferRealloc(void *buffer, uint32_t new_size); */ uint32_t MEM_GetHeapUpperLimit(void); +#if defined(gMemManagerLight) && (gMemManagerLight > 0) +/*! + * @brief Get the address after the last allocated block in area defined by id. + * + * @param[in] id 0 means memHeap, other values depend on number of registered areas + * + * @retval UpperLimit Return the address after the last allocated block if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetHeapUpperLimitByAreaId(uint8_t id); +#endif + +/*! + * @brief Get the free space low watermark. + * + * @retval FreeHeapSize Return the heap space low water mark free if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetFreeHeapSizeLowWaterMark(void); + +/*! + * @brief Get the free space low watermark. + * + * @param area_id Selected area Id + * + * @retval Return the heap space low water mark free if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetFreeHeapSizeLowWaterMarkByAreaId(uint8_t area_id); + +/*! + * @brief Reset the free space low watermark. + * + * @retval FreeHeapSize Return the heap space low water mark free at the time it was reset + * if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_ResetFreeHeapSizeLowWaterMark(void); + +/*! + * @brief Reset the free space low watermark. + * + * @param area_id Selected area Id + * + * @retval FreeHeapSize Return the heap space low water mark free at the time it was reset + * if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_ResetFreeHeapSizeLowWaterMarkByAreaId(uint8_t area_id); + +/*! + * @brief Get the free space in the heap for a area id. + * + * @param area_id area_id whose available size is requested (0 means generic pool) + * + * @retval FreeHeapSize Return the free space in the heap if MemManagerLight is used. + * @retval 0 Return 0 in case of the legacy MemManager. + */ +uint32_t MEM_GetFreeHeapSizeByAreaId(uint8_t area_id); + /*! * @brief Get the free space in the heap. * @@ -375,6 +457,35 @@ void MEM_Trace(void); void *MEM_CallocAlt(size_t len, size_t val); #endif /*gMemManagerLight == 1*/ +#if defined(gMemManagerLight) && (gMemManagerLight > 0) +/*! + * @brief Function to register additional areas to allocate memory from. + * + * @param[in] area_desc memAreaCfg_t structure defining start address and end address of area. + * This atructure may not be in rodata becasue the next field and internal private + * context are reserved in this structure. If NULL defines the default memHeap area. + * @param[out] area_id pointer to return id of area. Required if allocation from specific pool + * is required. + * @param[in] flags BIT(0) means that allocations can be performed in pool only explicitly and + * it is not a member of the default pool (id 0). Invalid for initial registration call. + * @return kStatus_MemSuccess if success, kStatus_MemInitError otherwise. + * + */ +mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *area_id, uint16_t flags); + +/*! + * @brief Function to unregister an extended area + * + * @param[in] area_id must be different from 0 (main heap). + * + * @return kStatus_MemSuccess if success, + * kStatus_MemFreeError if area_id is 0 or area not found or still has buffers in use. + * + */ +mem_status_t MEM_UnRegisterExtendedArea(uint8_t area_id); + +#endif + #if defined(__cplusplus) } #endif diff --git a/components/mem_manager/fsl_component_mem_manager_light.c b/components/mem_manager/fsl_component_mem_manager_light.c index a2bcfc463..697036b4a 100644 --- a/components/mem_manager/fsl_component_mem_manager_light.c +++ b/components/mem_manager/fsl_component_mem_manager_light.c @@ -1,6 +1,6 @@ /*! ********************************************************************************* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2022, 2023 NXP * All rights reserved. * * \file @@ -37,10 +37,17 @@ #endif #if defined(cMemManagerLightReuseFreeBlocks) && (cMemManagerLightReuseFreeBlocks > 0) -/* because a more restrictive on the size of the free blocks when cMemManagerLightReuseFreeBlocks - is set, we need to enable a garbage collector to clean up the free block when possible */ +/* Because a more restrictive on the size of the free blocks when cMemManagerLightReuseFreeBlocks + * is set, we need to enable a garbage collector to clean up the free block when possible . + * When set gMemManagerLightFreeBlocksCleanUp is used to select between 2 policies: + * 1: on each bufffer free, the allocator parses the free list in the forward direction and + * attempts to merge the freeed buffer with the top unused remainder of the region. + * 2: In addition to behaviour described in 1, allocator parses the list backwards to merge + * previous contiguous members of the free list (free blocks) if adjacent to the last block. + * In this case they meld in the top of the unused region. + */ #ifndef gMemManagerLightFreeBlocksCleanUp -#define gMemManagerLightFreeBlocksCleanUp 1 +#define gMemManagerLightFreeBlocksCleanUp 2 #endif #endif @@ -62,7 +69,7 @@ * with fsl_component_memory_manager_light, so this flag shall be kept to 0 */ #ifndef gMemManagerLightExtendHeapAreaUsage -#define gMemManagerLightExtendHeapAreaUsage 0 +#define gMemManagerLightExtendHeapAreaUsage 0 #endif /*! ********************************************************************************* @@ -70,6 +77,9 @@ * Private macros ************************************************************************************* ********************************************************************************** */ +#ifndef MAX_UINT16 +#define MAX_UINT16 0x00010000U +#endif #define MEMMANAGER_BLOCK_INVALID (uint16_t)0x0 /* Used to remove a block in the heap - debug only */ #define MEMMANAGER_BLOCK_FREE (uint16_t)0xBA00 /* Mark a previous allocated block as free */ @@ -87,7 +97,7 @@ #if defined(__IAR_SYSTEMS_ICC__) #define __mem_get_LR() __get_LR() #elif defined(__GNUC__) -#define __mem_get_LR() __builtin_return_address(0) +#define __mem_get_LR() __builtin_return_address(0U) #elif defined(__CC_ARM) || defined(__ARMCC_VERSION) #define __mem_get_LR() __return_address() #endif @@ -105,6 +115,17 @@ #define gMemManagerLightAddPostGuard 0 #endif +#if defined(__IAR_SYSTEMS_ICC__) && (defined __CORTEX_M) && \ + ((__CORTEX_M == 4U) || (__CORTEX_M == 7U) || (__CORTEX_M == 33U)) +#define D_BARRIER __asm("DSB"); /* __DSB() could not be used */ +#else +#define D_BARRIER +#endif +#define ENABLE_GLOBAL_IRQ(reg) \ + D_BARRIER; \ + EnableGlobalIRQ(reg) +#define KB(x) ((x) << 10u) + /************************************************************************************ ************************************************************************************* * Private type definitions @@ -117,6 +138,8 @@ typedef struct blockHeader_s uint8_t preguard[BLOCK_HDR_PREGUARD_SIZE]; #endif uint16_t used; + uint8_t area_id; + uint8_t reserved; #if defined(MEM_STATISTICS_INTERNAL) uint16_t buff_size; #endif @@ -145,6 +168,28 @@ typedef union void_ptr_tag void *void_ptr; blockHeader_t *block_hdr_ptr; } void_ptr_t; +typedef struct _memAreaPriv_s +{ + freeBlockHeaderList_t FreeBlockHdrList; +#ifdef MEM_STATISTICS_INTERNAL + mem_statis_t statistics; +#endif +} memAreaPriv_t; + +typedef struct _mem_area_priv_desc_s +{ + memAreaCfg_t *next; /*< Next registered RAM area descriptor. */ + void_ptr_t start_address; /*< Start address of RAM area. */ + void_ptr_t end_address; /*< End address of registered RAM area. */ + uint16_t flags; /*< BIT(0) means not member of default pool, other bits RFFU */ + uint16_t reserved; /*< alignment padding */ + uint32_t low_watermark; + union + { + uint8_t internal_ctx[MML_INTERNAL_STRUCT_SZ]; /* Placeholder for internal allocator data */ + memAreaPriv_t ctx; + }; +} memAreaPrivDesc_t; /*! ********************************************************************************* ************************************************************************************* @@ -185,7 +230,7 @@ extern uint32_t *memHeap; extern uint32_t memHeapEnd; #endif /* MEMORY_POOL_GLOBAL_VARIABLE_ALLOC */ -static freeBlockHeaderList_t FreeBlockHdrList; +static memAreaPrivDesc_t heap_area_list; #ifdef MEM_STATISTICS_INTERNAL static mem_statis_t s_memStatis; @@ -204,7 +249,7 @@ extern mem_alloc_test_status_t FSCI_MemAllocTestCanAllocate(void *pCaller); #ifdef MEM_STATISTICS_INTERNAL static void MEM_Inits_memStatis(mem_statis_t *s_memStatis_) { - (void)memset(s_memStatis_, 0, sizeof(mem_statis_t)); + (void)memset(s_memStatis_, 0U, sizeof(mem_statis_t)); SystemCoreClockUpdate(); } @@ -314,26 +359,39 @@ static void MEM_BufferFrees_memStatis(void *buffer) #endif /* MEM_STATISTICS_INTERNAL */ -#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp == 1) -static void MEM_BufferFreeBlocksCleanUp(blockHeader_t *BlockHdr) +#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp > 0) +static void MEM_BufferFreeBlocksCleanUp(memAreaPrivDesc_t *p_area, blockHeader_t *BlockHdr) { blockHeader_t *NextBlockHdr = BlockHdr->next; blockHeader_t *NextFreeBlockHdr = BlockHdr->next_free; - /* This function shouldn't be called on the last free block */ - assert(BlockHdr < FreeBlockHdrList.tail); + assert(BlockHdr < p_area->ctx.FreeBlockHdrList.tail); + /* Step forward and append contiguous free blocks if they can be merged with the unused top of heap */ while (NextBlockHdr == NextFreeBlockHdr) { if (NextBlockHdr == NULL) { +#if (gMemManagerLightFreeBlocksCleanUp == 2) + /* Step backwards to merge all preceeding contiguous free blocks */ + blockHeader_t *PrevFreeBlockHdr = BlockHdr->prev_free; + while (PrevFreeBlockHdr->next == BlockHdr) + { + assert(PrevFreeBlockHdr->next_free == BlockHdr); + assert(PrevFreeBlockHdr->used == MEMMANAGER_BLOCK_FREE); + PrevFreeBlockHdr->next_free = BlockHdr->next_free; + PrevFreeBlockHdr->next = BlockHdr->next; + BlockHdr = PrevFreeBlockHdr; + PrevFreeBlockHdr = BlockHdr->prev_free; + } +#endif assert(BlockHdr->next == BlockHdr->next_free); assert(BlockHdr->used == MEMMANAGER_BLOCK_FREE); /* pool is reached. All buffers from BlockHdr to the pool are free remove all next buffers */ - BlockHdr->next = NULL; - BlockHdr->next_free = NULL; - FreeBlockHdrList.tail = BlockHdr; + BlockHdr->next = NULL; + BlockHdr->next_free = NULL; + p_area->ctx.FreeBlockHdrList.tail = BlockHdr; break; } NextBlockHdr = NextBlockHdr->next; @@ -374,6 +432,16 @@ static void MEM_BlockHeaderSetGuards(blockHeader_t *BlockHdr) #endif +static memAreaPrivDesc_t *MEM_GetAreaByAreaId(uint8_t area_id) +{ + memAreaPrivDesc_t *p_area = &heap_area_list; + for (uint8_t i = 0u; i < area_id; i++) + { + p_area = (memAreaPrivDesc_t *)p_area->next; + } + return p_area; +} + /*! ********************************************************************************* ************************************************************************************* * Public functions @@ -411,16 +479,94 @@ static void MEM_Reports_memStatis(void) static bool initialized = false; -mem_status_t MEM_Init(void) +mem_status_t MEM_RegisterExtendedArea(memAreaCfg_t *area_desc, uint8_t *p_area_id, uint16_t flags) { - if (initialized == false) + mem_status_t st = kStatus_MemSuccess; + memAreaPrivDesc_t *p_area; + uint32_t regPrimask = DisableGlobalIRQ(); + assert(offsetof(memAreaCfg_t, internal_ctx) == offsetof(memAreaPrivDesc_t, ctx)); + assert(sizeof(memAreaCfg_t) >= sizeof(memAreaPrivDesc_t)); + do { - initialized = true; - /* union to solve Misra 11.3 */ void_ptr_t ptr; - ptr.address_ptr = memHeap; blockHeader_t *firstBlockHdr; - firstBlockHdr = ptr.block_hdr_ptr; + uint32_t initial_level; + + if (area_desc == NULL) + { + assert(flags == 0U); + p_area = &heap_area_list; + /* Area_desc can only be NULL in the case of the implicit default memHeap registration */ + if ((p_area->start_address.address_ptr != NULL) || (p_area->end_address.address_ptr != NULL)) + { + st = kStatus_MemInitError; + break; + } + /* The head of the area des list is necessarily the main heap */ + p_area->start_address.address_ptr = &memHeap[0]; + p_area->end_address.raw_address = memHeapEnd; + assert(p_area->end_address.raw_address > p_area->start_address.raw_address); + p_area->next = NULL; + if (p_area_id != NULL) + { + *p_area_id = 0u; + } + } + else + { + uint32_t area_sz; + + memAreaPrivDesc_t *new_area_desc = (memAreaPrivDesc_t *)area_desc; + assert((flags & AREA_FLAGS_RFFU) == 0U); + /* Registering an additional area : memHeap nust have been registered beforehand */ + uint8_t id = 0; + if (area_desc->start_address == NULL) + { + st = kStatus_MemInitError; + break; + } + if (heap_area_list.start_address.address_ptr == NULL) + { + /* memHeap must have been registered before */ + st = kStatus_MemInitError; + break; + } + area_sz = new_area_desc->end_address.raw_address - new_area_desc->start_address.raw_address; + if (area_sz <= KB(1)) + { + /* doesn't make sense to register an area smaller than 1024 bytes */ + st = kStatus_MemInitError; + break; + } + + for (p_area = &heap_area_list, id = 1; p_area->next != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + { + if (p_area == new_area_desc) + { + st = kStatus_MemInitError; + break; + } + id++; + } + if (st != kStatus_MemSuccess) + { + break; + } + if (p_area_id != NULL) + { + /* Determine the rank of the area in the list and return it as area_id */ + *p_area_id = id; + } + p_area->next = area_desc; /* p_area still points to previous area desc */ + p_area = new_area_desc; /* let p_area point to new element */ + p_area->flags = flags; + } + /* Here p_area points either to the implicit memHeap when invoked from MEM_Init or to the + * newly appended area configuration descriptor + */ + p_area->next = NULL; + ptr.address_ptr = p_area->start_address.address_ptr; + firstBlockHdr = ptr.block_hdr_ptr; /* MEM_DBG_LOG("%x %d\r\n", memHeap, heapSize_c/sizeof(uint32_t)); */ @@ -435,8 +581,11 @@ mem_status_t MEM_Init(void) #endif /* Init FreeBlockHdrList with firstBlockHdr */ - FreeBlockHdrList.head = firstBlockHdr; - FreeBlockHdrList.tail = firstBlockHdr; + p_area->ctx.FreeBlockHdrList.head = firstBlockHdr; + p_area->ctx.FreeBlockHdrList.tail = firstBlockHdr; + initial_level = p_area->end_address.raw_address - ((uint32_t)firstBlockHdr + BLOCK_HDR_SIZE - 1U); + + p_area->low_watermark = initial_level; #if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) MEM_BlockHeaderSetGuards(firstBlockHdr); @@ -444,22 +593,92 @@ mem_status_t MEM_Init(void) #if defined(MEM_STATISTICS_INTERNAL) /* Init memory statistics */ - MEM_Inits_memStatis(&s_memStatis); + MEM_Inits_memStatis(&p_area->ctx.statistics); #endif + + st = kStatus_MemSuccess; + } while (false); + ENABLE_GLOBAL_IRQ(regPrimask); + return st; +} + +static bool MEM_AreaIsEmpty(memAreaPrivDesc_t *p_area) +{ + bool res = false; + + blockHeader_t *FreeBlockHdr = p_area->ctx.FreeBlockHdrList.head; + blockHeader_t *NextFreeBlockHdr = FreeBlockHdr->next_free; + if ((FreeBlockHdr == (blockHeader_t *)p_area->start_address.raw_address) && (NextFreeBlockHdr == NULL)) + { + res = true; } - return kStatus_MemSuccess; + return res; } -static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) + +mem_status_t MEM_UnRegisterExtendedArea(uint8_t area_id) +{ + mem_status_t st = kStatus_MemUnknownError; + memAreaPrivDesc_t *prev_area; + memAreaPrivDesc_t *p_area_to_remove = NULL; + uint32_t regPrimask = DisableGlobalIRQ(); + + do + { + /* Cannot unregister main heap */ + if (area_id == 0U) + { + st = kStatus_MemFreeError; + break; + } + prev_area = MEM_GetAreaByAreaId(area_id - 1); /* Get previous area in list */ + if (prev_area == NULL) + { + st = kStatus_MemFreeError; + break; + } + + p_area_to_remove = (memAreaPrivDesc_t *)prev_area->next; + if (p_area_to_remove == NULL) + { + st = kStatus_MemFreeError; + break; + } + if (!MEM_AreaIsEmpty(p_area_to_remove)) + { + st = kStatus_MemFreeError; + break; + } + + /* Only unchain if no remaining allocated buffers */ + prev_area->next = p_area_to_remove->next; + p_area_to_remove->next = NULL; + + st = kStatus_MemSuccess; + } while (false); + + ENABLE_GLOBAL_IRQ(regPrimask); + + return st; +} + +mem_status_t MEM_Init(void) { + mem_status_t st = kStatus_MemSuccess; + uint8_t memHeap_id; if (initialized == false) { - (void)MEM_Init(); + initialized = true; + st = MEM_RegisterExtendedArea(NULL, &memHeap_id, 0U); /* initialized default heap area */ } + return st; +} +static void *MEM_BufferAllocateFromArea(memAreaPrivDesc_t *p_area, uint8_t area_id, uint32_t numBytes) +{ uint32_t regPrimask = DisableGlobalIRQ(); - blockHeader_t *FreeBlockHdr = FreeBlockHdrList.head; + blockHeader_t *FreeBlockHdr = p_area->ctx.FreeBlockHdrList.head; blockHeader_t *NextFreeBlockHdr = FreeBlockHdr->next_free; blockHeader_t *PrevFreeBlockHdr = FreeBlockHdr->prev_free; blockHeader_t *BlockHdrFound = NULL; @@ -484,7 +703,7 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) /* if a next block hdr exists, it means (by design) that a next free block exists too Because the last block header at the end of the heap will always be free So, the current block header can't be the tail, and the next free can't be NULL */ - assert(FreeBlockHdr < FreeBlockHdrList.tail); + assert(FreeBlockHdr < p_area->ctx.FreeBlockHdrList.tail); assert(FreeBlockHdr->next_free != NULL); if (available_size >= numBytes) /* enough space in this free buffer */ @@ -498,11 +717,13 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) /* To avoid waste of large blocks with small blocks, make sure the required size is big enough for the available block otherwise, try an other block ! Do not check if available block size is 4 bytes, take the block anyway ! */ - if ( (available_size <= 4u) || ((available_size - numBytes) < (available_size >> cMemManagerLightReuseFreeBlocks))) + if ((available_size <= 4u) || + ((available_size - numBytes) < (available_size >> cMemManagerLightReuseFreeBlocks))) #endif { /* Found a matching free block */ - FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; + FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; + FreeBlockHdr->area_id = area_id; #if defined(MEM_STATISTICS_INTERNAL) FreeBlockHdr->buff_size = (uint16_t)numBytes; #endif @@ -511,14 +732,14 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) /* In the current state, the current block header can be anywhere from list head to previous block of list tail */ - if (FreeBlockHdrList.head == FreeBlockHdr) + if (p_area->ctx.FreeBlockHdrList.head == FreeBlockHdr) { - FreeBlockHdrList.head = NextFreeBlockHdr; - NextFreeBlockHdr->prev_free = NULL; + p_area->ctx.FreeBlockHdrList.head = NextFreeBlockHdr; + NextFreeBlockHdr->prev_free = NULL; } else { - assert(FreeBlockHdrList.head->next_free <= FreeBlockHdr); + assert(p_area->ctx.FreeBlockHdrList.head->next_free <= FreeBlockHdr); NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; PrevFreeBlockHdr->next_free = NextFreeBlockHdr; @@ -532,28 +753,35 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) else { /* last block in the heap, check if available space to allocate the block */ - uint32_t available_size; + int32_t available_size; + uint32_t total_size; uint32_t current_footprint = (uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE - 1U; + int32_t remaining_bytes; /* Current allocation should never be greater than heap end */ - assert(current_footprint <= memHeapEnd); + available_size = p_area->end_address.raw_address - current_footprint; + assert(available_size >= 0); - available_size = memHeapEnd - current_footprint; - - assert(FreeBlockHdr == FreeBlockHdrList.tail); - - if (available_size >= (numBytes + BLOCK_HDR_SIZE)) /* need to keep the room for the next BlockHeader */ + assert(FreeBlockHdr == p_area->ctx.FreeBlockHdrList.tail); + total_size = (numBytes + BLOCK_HDR_SIZE); + remaining_bytes = (available_size - total_size); + if (remaining_bytes >= 0) /* need to keep the room for the next BlockHeader */ { + if (p_area->low_watermark > remaining_bytes) + { + p_area->low_watermark = remaining_bytes; + } /* Depending on the platform, some RAM banks could need some reinitialization after a low power * period, such as ECC RAM banks */ - MEM_ReinitRamBank((uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE, ROUNDUP_WORD(((uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE + numBytes))); + MEM_ReinitRamBank((uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE, + ROUNDUP_WORD(((uint32_t)FreeBlockHdr + total_size))); - FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; + FreeBlockHdr->used = MEMMANAGER_BLOCK_USED; + FreeBlockHdr->area_id = area_id; #if defined(MEM_STATISTICS_INTERNAL) FreeBlockHdr->buff_size = (uint16_t)numBytes; #endif - FreeBlockHdr->next = - (blockHeader_t *)ROUNDUP_WORD(((uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE + numBytes)); + FreeBlockHdr->next = (blockHeader_t *)ROUNDUP_WORD(((uint32_t)FreeBlockHdr + total_size)); FreeBlockHdr->next_free = FreeBlockHdr->next; PrevFreeBlockHdr = FreeBlockHdr->prev_free; @@ -567,13 +795,13 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) NextFreeBlockHdr->next_free = NULL; NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; - if (FreeBlockHdrList.head == FreeBlockHdr) + if (p_area->ctx.FreeBlockHdrList.head == FreeBlockHdr) { - assert(FreeBlockHdrList.head == FreeBlockHdrList.tail); + assert(p_area->ctx.FreeBlockHdrList.head == p_area->ctx.FreeBlockHdrList.tail); assert(PrevFreeBlockHdr == NULL); /* last free block in heap was the only free block available so now the first free block in the heap is the next one */ - FreeBlockHdrList.head = FreeBlockHdr->next_free; + p_area->ctx.FreeBlockHdrList.head = FreeBlockHdr->next_free; } else { @@ -583,7 +811,7 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) } /* new free block is now the tail of the free block list */ - FreeBlockHdrList.tail = NextFreeBlockHdr; + p_area->ctx.FreeBlockHdrList.tail = NextFreeBlockHdr; #if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) MEM_BlockHeaderSetGuards(NextFreeBlockHdr); @@ -595,7 +823,8 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) else if (UsableBlockHdr != NULL) { /* we found a free block that can be used */ - UsableBlockHdr->used = MEMMANAGER_BLOCK_USED; + UsableBlockHdr->used = MEMMANAGER_BLOCK_USED; + UsableBlockHdr->area_id = area_id; #if defined(MEM_STATISTICS_INTERNAL) UsableBlockHdr->buff_size = (uint16_t)numBytes; #endif @@ -604,14 +833,14 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) /* In the current state, the current block header can be anywhere from list head to previous block of list tail */ - if (FreeBlockHdrList.head == UsableBlockHdr) + if (p_area->ctx.FreeBlockHdrList.head == UsableBlockHdr) { - FreeBlockHdrList.head = NextFreeBlockHdr; - NextFreeBlockHdr->prev_free = NULL; + p_area->ctx.FreeBlockHdrList.head = NextFreeBlockHdr; + NextFreeBlockHdr->prev_free = NULL; } else { - assert(FreeBlockHdrList.head->next_free <= UsableBlockHdr); + assert(p_area->ctx.FreeBlockHdrList.head->next_free <= UsableBlockHdr); NextFreeBlockHdr->prev_free = PrevFreeBlockHdr; PrevFreeBlockHdr->next_free = NextFreeBlockHdr; @@ -653,9 +882,11 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) #endif buffer_ptr.raw_address = (uint32_t)BlockHdrFound + BLOCK_HDR_SIZE; buffer = buffer_ptr.void_ptr; - (void)memset(buffer, 0x0, numBytes); } - + else + { + /* TODO: Allocation failure try to merge free blocks together */ + } #ifdef MEM_STATISTICS_INTERNAL #ifdef MEM_MANAGER_BENCH MEM_BufferAllocates_memStatis(buffer, ALLOC_TIME, numBytes); @@ -663,7 +894,7 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) MEM_BufferAllocates_memStatis(buffer, 0, numBytes); #endif - if ((s_memStatis.nb_alloc % NB_ALLOC_REPORT_THRESHOLD) == 0U) + if ((p_area->ctx.statistics.nb_alloc % NB_ALLOC_REPORT_THRESHOLD) == 0U) { MEM_Reports_memStatis(); } @@ -674,6 +905,43 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) return buffer; } +static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId) +{ + memAreaPrivDesc_t *p_area; + void *buffer = NULL; + uint8_t area_id = 0U; + + if (initialized == false) + { + (void)MEM_Init(); + } + if (poolId == 0U) + { + area_id = 0U; + for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + { + if ((p_area->flags & AREA_FLAGS_POOL_NOT_SHARED) == 0U) + { + buffer = MEM_BufferAllocateFromArea(p_area, area_id, numBytes); + if (buffer != NULL) + { + break; + } + } + area_id++; + } + } + else + { + p_area = MEM_GetAreaByAreaId(poolId); /* Exclusively allocate from targeted pool */ + if (p_area != NULL) + { + buffer = MEM_BufferAllocateFromArea(p_area, poolId, numBytes); + } + } + return buffer; +} + void *MEM_BufferAllocWithId(uint32_t numBytes, uint8_t poolId) { #ifdef MEM_TRACKING @@ -707,6 +975,67 @@ void *MEM_BufferAllocWithId(uint32_t numBytes, uint8_t poolId) return buffer_ptr.void_ptr; } +static mem_status_t MEM_BufferFreeBackToArea(memAreaPrivDesc_t *p_area, void *buffer) +{ + void_ptr_t buffer_ptr; + buffer_ptr.void_ptr = buffer; + blockHeader_t *BlockHdr; + BlockHdr = (blockHeader_t *)(buffer_ptr.raw_address - BLOCK_HDR_SIZE); + + mem_status_t ret = kStatus_MemSuccess; + /* when allocating a buffer, we always create a FreeBlockHdr at + the end of the buffer, so the FreeBlockHdrList.tail should always + be at a higher address than current BlockHdr */ + assert(BlockHdr < p_area->ctx.FreeBlockHdrList.tail); + +#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) + MEM_BlockHeaderCheck(BlockHdr->next); +#endif + + /* MEM_DBG_LOG("%x %d", BlockHdr, BlockHdr->buff_size); */ + +#if defined(MEM_STATISTICS_INTERNAL) + MEM_BufferFrees_memStatis(buffer); +#endif /* MEM_STATISTICS_INTERNAL */ + + if (BlockHdr < p_area->ctx.FreeBlockHdrList.head) + { + /* BlockHdr is placed before FreeBlockHdrList.head so we can set it as + the new head of the list */ + BlockHdr->next_free = p_area->ctx.FreeBlockHdrList.head; + BlockHdr->prev_free = NULL; + p_area->ctx.FreeBlockHdrList.head->prev_free = BlockHdr; + p_area->ctx.FreeBlockHdrList.head = BlockHdr; + } + else + { + /* we want to find the previous free block header + here, we cannot use prev_free as this information could be outdated + so we need to run through the whole list to be sure to catch the + correct previous free block header */ + blockHeader_t *PrevFreeBlockHdr = p_area->ctx.FreeBlockHdrList.head; + while ((uint32_t)PrevFreeBlockHdr->next_free < (uint32_t)BlockHdr) + { + PrevFreeBlockHdr = PrevFreeBlockHdr->next_free; + } + /* insert the new free block in the list */ + BlockHdr->next_free = PrevFreeBlockHdr->next_free; + BlockHdr->prev_free = PrevFreeBlockHdr; + BlockHdr->next_free->prev_free = BlockHdr; + PrevFreeBlockHdr->next_free = BlockHdr; + } + + BlockHdr->used = MEMMANAGER_BLOCK_FREE; +#if defined(MEM_STATISTICS_INTERNAL) + BlockHdr->buff_size = 0U; +#endif + +#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp != 0) + MEM_BufferFreeBlocksCleanUp(p_area, BlockHdr); +#endif + return ret; +} + mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/) { mem_status_t ret = kStatus_MemSuccess; @@ -727,57 +1056,18 @@ mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/) /* assert checks */ assert(BlockHdr->used == MEMMANAGER_BLOCK_USED); assert(BlockHdr->next != NULL); - /* when allocating a buffer, we always create a FreeBlockHdr at - the end of the buffer, so the FreeBlockHdrList.tail should always - be at a higher address than current BlockHdr */ - assert(BlockHdr < FreeBlockHdrList.tail); + memAreaPrivDesc_t *p_area = MEM_GetAreaByAreaId(BlockHdr->area_id); -#if defined(gMemManagerLightGuardsCheckEnable) && (gMemManagerLightGuardsCheckEnable == 1) - MEM_BlockHeaderCheck(BlockHdr->next); -#endif - - /* MEM_DBG_LOG("%x %d", BlockHdr, BlockHdr->buff_size); */ - -#if defined(MEM_STATISTICS_INTERNAL) - MEM_BufferFrees_memStatis(buffer); -#endif /* MEM_STATISTICS_INTERNAL */ - - if (BlockHdr < FreeBlockHdrList.head) + if (p_area != NULL) { - /* BlockHdr is placed before FreeBlockHdrList.head so we can set it as - the new head of the list */ - BlockHdr->next_free = FreeBlockHdrList.head; - BlockHdr->prev_free = NULL; - FreeBlockHdrList.head->prev_free = BlockHdr; - FreeBlockHdrList.head = BlockHdr; + ret = MEM_BufferFreeBackToArea(p_area, buffer); } else { - /* we want to find the previous free block header - here, we cannot use prev_free as this information could be outdated - so we need to run through the whole list to be sure to catch the - correct previous free block header */ - blockHeader_t *PrevFreeBlockHdr = FreeBlockHdrList.head; - while ((uint32_t)PrevFreeBlockHdr->next_free < (uint32_t)BlockHdr) - { - PrevFreeBlockHdr = PrevFreeBlockHdr->next_free; - } - /* insert the new free block in the list */ - BlockHdr->next_free = PrevFreeBlockHdr->next_free; - BlockHdr->prev_free = PrevFreeBlockHdr; - BlockHdr->next_free->prev_free = BlockHdr; - PrevFreeBlockHdr->next_free = BlockHdr; + assert(p_area != NULL); + ret = kStatus_MemFreeError; } - BlockHdr->used = MEMMANAGER_BLOCK_FREE; -#if defined(MEM_STATISTICS_INTERNAL) - BlockHdr->buff_size = 0U; -#endif - -#if defined(gMemManagerLightFreeBlocksCleanUp) && (gMemManagerLightFreeBlocksCleanUp == 1) - MEM_BufferFreeBlocksCleanUp(BlockHdr); -#endif - EnableGlobalIRQ(regPrimask); } @@ -797,11 +1087,80 @@ mem_status_t MEM_BufferFreeAllWithId(uint8_t poolId) return status; } -uint32_t MEM_GetHeapUpperLimit(void) +uint32_t MEM_GetHeapUpperLimitByAreaId(uint8_t area_id) { /* There is always a free block at the end of the heap - and this free block is the tail of the list */ - return ((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE); + and this free block is the tail of the list */ + uint32_t upper_limit = 0U; + do + { + memAreaPrivDesc_t *p_area; + p_area = MEM_GetAreaByAreaId(area_id); + if (p_area == NULL) + { + break; + } + upper_limit = ((uint32_t)p_area->ctx.FreeBlockHdrList.tail + BLOCK_HDR_SIZE); + + } while (false); + + return upper_limit; +} + +uint32_t MEM_GetHeapUpperLimit(void) +{ + return MEM_GetHeapUpperLimitByAreaId(0u); +} + +uint32_t MEM_GetFreeHeapSizeLowWaterMarkByAreaId(uint8_t area_id) +{ + uint32_t low_watermark = 0U; + do + { + memAreaPrivDesc_t *p_area; + p_area = MEM_GetAreaByAreaId(area_id); + if (p_area == NULL) + { + break; + } + low_watermark = p_area->low_watermark; + + } while (false); + return low_watermark; +} + +uint32_t MEM_GetFreeHeapSizeLowWaterMark(void) +{ + return MEM_GetFreeHeapSizeLowWaterMarkByAreaId(0u); +} + +uint32_t MEM_ResetFreeHeapSizeLowWaterMarkByAreaId(uint8_t area_id) +{ + uint32_t current_level = 0U; + do + { + memAreaPrivDesc_t *p_area; + blockHeader_t *FreeBlockHdr; + uint32_t current_footprint; + p_area = MEM_GetAreaByAreaId(area_id); + if (p_area == NULL) + { + break; + } + FreeBlockHdr = p_area->ctx.FreeBlockHdrList.head; + current_footprint = (uint32_t)FreeBlockHdr + BLOCK_HDR_SIZE - 1U; + + /* Current allocation should never be greater than heap end */ + current_level = p_area->end_address.raw_address - current_footprint; + p_area->low_watermark = current_level; + + } while (false); + return current_level; +} + +uint32_t MEM_ResetFreeHeapSizeLowWaterMark(void) +{ + return MEM_ResetFreeHeapSizeLowWaterMarkByAreaId(0u); } uint16_t MEM_BufferGetSize(void *buffer) @@ -831,22 +1190,28 @@ void *MEM_BufferRealloc(void *buffer, uint32_t new_size) { void *realloc_buffer = NULL; uint16_t block_size = 0U; - - assert(new_size <= 0x0000FFFFU); /* size will be casted to 16 bits */ - - if (new_size == 0U) - { - /* new requested size is 0, free old buffer */ - (void)MEM_BufferFree(buffer); - realloc_buffer = NULL; - } - else if (buffer == NULL) - { - /* input buffer is NULL simply allocate a new buffer and return it */ - realloc_buffer = MEM_BufferAllocate(new_size, 0U); - } - else + do { + if (new_size >= MAX_UINT16) + { + realloc_buffer = NULL; + /* Bypass he whole procedure so keep original buffer that cannot be reallocated */ + break; + } + if (new_size == 0U) + { + /* new requested size is 0, free old buffer */ + (void)MEM_BufferFree(buffer); + realloc_buffer = NULL; + break; + } + if (buffer == NULL) + { + /* input buffer is NULL simply allocate a new buffer and return it */ + realloc_buffer = MEM_BufferAllocate(new_size, 0U); + break; + } + /* Current buffer needs to be reallocated */ block_size = MEM_BufferGetSize(buffer); if ((uint16_t)new_size <= block_size) @@ -858,7 +1223,7 @@ void *MEM_BufferRealloc(void *buffer, uint32_t new_size) else { /* not enough space in the current block, creating a new one */ - realloc_buffer = MEM_BufferAllocate(new_size, 0); + realloc_buffer = MEM_BufferAllocate(new_size, 0U); if (realloc_buffer != NULL) { @@ -869,29 +1234,59 @@ void *MEM_BufferRealloc(void *buffer, uint32_t new_size) (void)MEM_BufferFree(buffer); } } - } - + } while (false); return realloc_buffer; } - -uint32_t MEM_GetFreeHeapSize(void) +static uint32_t MEM_GetFreeHeapSpaceInArea(memAreaPrivDesc_t *p_area) { - uint32_t free_size = 0U; - blockHeader_t *freeBlockHdr = FreeBlockHdrList.head; + uint32_t free_sz = 0U; + /* skip unshared areas */ + blockHeader_t *freeBlockHdr = p_area->ctx.FreeBlockHdrList.head; /* Count every free block in the free space */ - while (freeBlockHdr != FreeBlockHdrList.tail) + while (freeBlockHdr != p_area->ctx.FreeBlockHdrList.tail) { - free_size += ((uint32_t)freeBlockHdr->next - (uint32_t)freeBlockHdr - BLOCK_HDR_SIZE); + free_sz += ((uint32_t)freeBlockHdr->next - (uint32_t)freeBlockHdr - BLOCK_HDR_SIZE); freeBlockHdr = freeBlockHdr->next_free; } /* Add remaining free space in the heap */ - free_size += memHeapEnd - (uint32_t)FreeBlockHdrList.tail - BLOCK_HDR_SIZE; + free_sz += p_area->end_address.raw_address - (uint32_t)p_area->ctx.FreeBlockHdrList.tail - BLOCK_HDR_SIZE + 1; + return free_sz; +} + +uint32_t MEM_GetFreeHeapSizeByAreaId(uint8_t area_id) +{ + memAreaPrivDesc_t *p_area; + uint32_t free_size = 0U; + if (area_id == 0U) + { + /* Iterate through all registered areas */ + for (p_area = &heap_area_list; p_area != NULL; p_area = (memAreaPrivDesc_t *)p_area->next) + { + if ((p_area->flags & AREA_FLAGS_POOL_NOT_SHARED) == 0U) + { + free_size += MEM_GetFreeHeapSpaceInArea(p_area); + } + } + } + else + { + p_area = MEM_GetAreaByAreaId(area_id); + if (p_area != NULL) + { + free_size = MEM_GetFreeHeapSpaceInArea(p_area); + } + } return free_size; } +uint32_t MEM_GetFreeHeapSize(void) +{ + return MEM_GetFreeHeapSizeByAreaId(0U); +} + __attribute__((weak)) void MEM_ReinitRamBank(uint32_t startAddress, uint32_t endAddress) { /* To be implemented by the platform */ @@ -915,10 +1310,10 @@ void *MEM_CallocAlt(size_t len, size_t val) blk_size = len * val; - void *pData = MEM_BufferAllocate(blk_size, 0); + void *pData = MEM_BufferAllocate(blk_size, 0U); if (NULL != pData) { - (void)memset(pData, 0, blk_size); + (void)memset(pData, 0U, blk_size); } return pData; diff --git a/components/osa/fsl_os_abstraction.h b/components/osa/fsl_os_abstraction.h index 69462e448..3dd0e70a1 100644 --- a/components/osa/fsl_os_abstraction.h +++ b/components/osa/fsl_os_abstraction.h @@ -64,7 +64,7 @@ typedef struct osa_task_def_tag uint32_t tpriority; /*!< initial thread priority*/ uint32_t instances; /*!< maximum number of instances of that thread function*/ uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ - uint32_t *tstack; /*!< stack pointer*/ + uint32_t *tstack; /*!< stack pointer, which can be used on freertos static allocation*/ void *tlink; /*!< link pointer*/ uint8_t *tname; /*!< name pointer*/ uint8_t useFloat; /*!< is use float*/ @@ -118,20 +118,56 @@ typedef enum _osa_status #undef USE_RTOS #endif +#if defined(SDK_OS_FREE_RTOS) +#include "fsl_os_abstraction_free_rtos.h" +#elif defined(FSL_RTOS_THREADX) +#include "fsl_os_abstraction_threadx.h" +#else +#include "fsl_os_abstraction_bm.h" +#endif + +extern const uint8_t gUseRtos_c; + #if defined(SDK_OS_MQX) #define USE_RTOS (1) #elif defined(SDK_OS_FREE_RTOS) #define USE_RTOS (1) #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_TASK_HANDLE_SIZE (132U) +#else #define OSA_TASK_HANDLE_SIZE (12U) +#endif #else #define OSA_TASK_HANDLE_SIZE (16U) #endif +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_EVENT_HANDLE_SIZE (40U) +#else #define OSA_EVENT_HANDLE_SIZE (8U) -#define OSA_SEM_HANDLE_SIZE (4U) +#endif +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_SEM_HANDLE_SIZE (84U) +#else +#define OSA_SEM_HANDLE_SIZE (4U) +#endif +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_MUTEX_HANDLE_SIZE (84U) +#else #define OSA_MUTEX_HANDLE_SIZE (4U) -#define OSA_MSGQ_HANDLE_SIZE (4U) +#endif +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_MSGQ_HANDLE_SIZE (84U) +#else +#define OSA_MSGQ_HANDLE_SIZE (4U) +#endif #define OSA_MSG_HANDLE_SIZE (0U) +#define OSA_TIMER_HANDLE_SIZE (4U) #elif defined(SDK_OS_UCOSII) #define USE_RTOS (1) #elif defined(SDK_OS_UCOSIII) @@ -206,7 +242,8 @@ typedef enum _osa_status * Converse the percent of the priority to the priority of the OSA. * The the range of the parameter x is 0-100. */ -#define OSA_TASK_PRIORITY_PERCENT(x) ((((OSA_TASK_PRIORITY_MIN - OSA_TASK_PRIORITY_MAX) * (100 - (x))) / 100 ) + OSA_TASK_PRIORITY_MAX) +#define OSA_TASK_PRIORITY_PERCENT(x) \ + ((((OSA_TASK_PRIORITY_MIN - OSA_TASK_PRIORITY_MAX) * (100 - (x))) / 100) + OSA_TASK_PRIORITY_MAX) #define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) @@ -251,10 +288,18 @@ typedef enum _osa_status static const osa_task_def_t os_thread_def_##name = { \ (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)} #else +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + uint32_t s_stackBuffer##name[(stackSz + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; \ + static const osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)} +#else #define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ const osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \ NULL, NULL, (uint8_t *)#name, (useFloat)} #endif +#endif /* Access a Thread defintion. * \param name name of the thread definition object. */ @@ -346,16 +391,33 @@ typedef enum _osa_status * @param msgSize Message size. * */ -#if defined(SDK_OS_FREE_RTOS) -/*< Macro For FREE_RTOS*/ +#if defined(SDK_OS_FREE_RTOS) && (defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0)) +/*< Macro For FREE_RTOS dynamic allocation*/ #define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] #else -/*< Macro For BARE_MATEL*/ +/*< Macro For BARE_MATEL and FREE_RTOS static allocation*/ #define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ uint32_t name[((OSA_MSGQ_HANDLE_SIZE + numberOfMsgs * msgSize) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] #endif +/*! + * @brief Defines the timer handle + * + * This macro is used to define a 4 byte aligned timer handle. + * Then use "(osa_timer_handle_t)name" to get the timer handle. + * + * The macro should be global and could be optional. You could also define timer handle by yourself. + * + * This is an example, + * @code + * OSA_TIMER_HANDLE_DEFINE(timerHandle); + * @endcode + * + * @param name The name string of the timer handle. + */ +#define OSA_TIMER_HANDLE_DEFINE(name) uint32_t name[(OSA_TIMER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + /*! * @brief Defines the TASK handle * @@ -373,16 +435,6 @@ typedef enum _osa_status */ #define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] -#if defined(SDK_OS_FREE_RTOS) -#include "fsl_os_abstraction_free_rtos.h" -#elif defined(FSL_RTOS_THREADX) -#include "fsl_os_abstraction_threadx.h" -#else -#include "fsl_os_abstraction_bm.h" -#endif - -extern const uint8_t gUseRtos_c; - #ifndef __DSB #define __DSB() #endif @@ -414,7 +466,7 @@ extern const uint8_t gUseRtos_c; * * @return Pointer to the reserved memory. NULL if memory can't be allocated. */ -void *OSA_MemoryAllocate(uint32_t length); +void *OSA_MemoryAllocate(uint32_t memLength); /*! * @brief Frees the memory previously reserved. @@ -884,14 +936,13 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle); * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg)); * @endcode * - * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel - * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle. - * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. - * You can define the handle in the following two ways: - * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); - * or - * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; - * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel, + * FreeRTOS static allocation allocated by the caller and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS dynamic allocation, + * message queue handle. The handle should be 4 byte aligned, because unaligned access doesn't be supported on some + * devices. You can define the handle in the following two ways: #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); or For bm and + * freertos static: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / + * sizeof(uint32_t))]; For freertos dynamic: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / + * sizeof(uint32_t))]; * @param msgNo :number of messages the message queue should accommodate. * @param msgSize :size of a single message structure. * @@ -973,6 +1024,16 @@ void OSA_EnableIRQGlobal(void); */ void OSA_DisableIRQGlobal(void); +/*! + * @brief Disable the scheduling of any task. + */ +void OSA_DisableScheduler(void); + +/*! + * @brief Enable the scheduling of any task. + */ +void OSA_EnableScheduler(void); + /*! * @brief Delays execution for a number of milliseconds. * diff --git a/components/osa/fsl_os_abstraction_bm.c b/components/osa/fsl_os_abstraction_bm.c index d06ff647f..ff1689963 100644 --- a/components/osa/fsl_os_abstraction_bm.c +++ b/components/osa/fsl_os_abstraction_bm.c @@ -82,7 +82,7 @@ typedef struct Semaphore uint32_t timeout; /*!< Timeout to wait in milliseconds */ #endif #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) - task_handler_t waitingTask; /*!< Handler to the waiting task */ + task_handler_t waitingTask; /*!< Handler to the waiting task */ #endif volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this object */ volatile uint8_t semCount; /*!< The count value of the object */ @@ -93,8 +93,8 @@ typedef struct Semaphore typedef struct Mutex { #if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) - uint32_t time_start; /*!< The time to start timeout */ - uint32_t timeout; /*!< Timeout to wait in milliseconds */ + uint32_t time_start; /*!< The time to start timeout */ + uint32_t timeout; /*!< Timeout to wait in milliseconds */ #endif volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this mutex */ volatile uint8_t isLocked; /*!< Is the object locked or not */ @@ -109,10 +109,10 @@ typedef struct Event uint32_t timeout; /*!< Timeout to wait in milliseconds */ volatile event_flags_t flags; /*!< The flags status */ #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) - task_handler_t waitingTask; /*!< Handler to the waiting task */ + task_handler_t waitingTask; /*!< Handler to the waiting task */ #endif - uint8_t autoClear; /*!< Auto clear or manual clear */ - volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this event */ + uint8_t autoClear; /*!< Auto clear or manual clear */ + volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this event */ } event_t; /*! @brief Type for a message queue */ @@ -125,11 +125,11 @@ typedef struct MsgQueue #if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) task_handler_t waitingTask; /*!< Handler to the waiting task */ #endif - uint8_t *queueMem; /*!< Points to the queue memory */ - uint16_t number; /*!< The number of messages in the queue */ - uint16_t max; /*!< The max number of queue messages */ - uint16_t head; /*!< Index of the next message to be read */ - uint16_t tail; /*!< Index of the next place to write to */ + uint8_t *queueMem; /*!< Points to the queue memory */ + uint16_t number; /*!< The number of messages in the queue */ + uint16_t max; /*!< The max number of queue messages */ + uint16_t head; /*!< Index of the next message to be read */ + uint16_t tail; /*!< Index of the next place to write to */ } msg_queue_t; /*! @brief Type for a message queue handler */ @@ -177,7 +177,6 @@ const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS ************************************************************************************* ********************************************************************************** */ static osa_state_t s_osaState; - /*! ********************************************************************************* ************************************************************************************* * Public functions @@ -189,13 +188,13 @@ static osa_state_t s_osaState; * Description : Reserves the requested amount of memory in bytes. * *END**************************************************************************/ -void *OSA_MemoryAllocate(uint32_t length) +void *OSA_MemoryAllocate(uint32_t memLength) { - void *p = (void *)malloc(length); + void *p = (void *)malloc(memLength); if (NULL != p) { - (void)memset(p, 0, length); + (void)memset(p, 0, memLength); } return p; @@ -261,6 +260,30 @@ void OSA_DisableIRQGlobal(void) s_osaState.interruptDisableCount++; } +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableScheduler + * Description : Disable the scheduling of any task + * This function will disable the scheduling of any task + * + *END**************************************************************************/ +void OSA_DisableScheduler(void) +{ + /* No need to do something in baremetal as preemption can not occur */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableScheduler + * Description : Enable the scheduling of any task + * This function will enable the scheduling of any task + * + *END**************************************************************************/ +void OSA_EnableScheduler(void) +{ + /* No need to do something in baremetal as preemption can not occur */ +} + /*FUNCTION********************************************************************** * * Function Name : OSA_TaskGetCurrentHandle @@ -651,9 +674,10 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t pSemStruct->waitingTask = OSA_TaskGetCurrentHandle(); #endif #endif + + OSA_EnterCritical(®Primask); if (0U != pSemStruct->semCount) { - OSA_EnterCritical(®Primask); pSemStruct->semCount--; pSemStruct->isWaiting = 0U; OSA_ExitCritical(regPrimask); @@ -664,6 +688,7 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t if (0U == millisec) { /* If timeout is 0 and semaphore is not available, return kStatus_OSA_Timeout. */ + OSA_ExitCritical(regPrimask); return KOSA_StatusTimeout; } #if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U)) @@ -674,7 +699,6 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t currentTime = OSA_TimeGetMsec(); if (pSemStruct->timeout < OSA_TimeDiff(pSemStruct->time_start, currentTime)) { - OSA_EnterCritical(®Primask); pSemStruct->isWaiting = 0U; OSA_ExitCritical(regPrimask); return KOSA_StatusTimeout; @@ -683,9 +707,7 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t else if (millisec != osaWaitForever_c) /* If don't wait forever, start the timer */ { /* Start the timeout counter */ - OSA_EnterCritical(®Primask); - pSemStruct->isWaiting = 1U; - OSA_ExitCritical(regPrimask); + pSemStruct->isWaiting = 1U; pSemStruct->time_start = OSA_TimeGetMsec(); pSemStruct->timeout = millisec; } @@ -698,7 +720,7 @@ osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t #endif } } - + OSA_ExitCritical(regPrimask); return KOSA_StatusIdle; } /*FUNCTION********************************************************************** @@ -718,7 +740,7 @@ osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) /* check whether max value is reached */ if (((KOSA_CountingSemaphore == pSemStruct->semaphoreType) && - (0xFFU == pSemStruct->semCount)) || /* For counting semaphore: the max value is 0xFF */ + (0xFFU == pSemStruct->semCount)) || /* For counting semaphore: the max value is 0xFF */ ((0x01U == pSemStruct->semCount) && (KOSA_BinarySemaphore == pSemStruct->semaphoreType))) /* For binary semaphore: the max value is 0x01 */ { @@ -1037,6 +1059,9 @@ osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, if (1U == pEventStruct->autoClear) { pEventStruct->flags &= ~flagsToWait; +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + pEventStruct->waitingTask->haveToRun = 0U; +#endif } retVal = KOSA_StatusSuccess; } @@ -1474,3 +1499,11 @@ void SysTick_Handler(void) s_osaState.tickCounter++; } #endif + +void OSA_UpdateSysTickCounter(uint32_t corr) +{ +#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE) + s_osaState.tickCounter += corr; +#else +#endif +} diff --git a/components/osa/fsl_os_abstraction_bm.h b/components/osa/fsl_os_abstraction_bm.h index 0f743a3fe..f9a64d6ad 100644 --- a/components/osa/fsl_os_abstraction_bm.h +++ b/components/osa/fsl_os_abstraction_bm.h @@ -76,6 +76,17 @@ void OSA_ProcessTasks(void); * */ uint8_t OSA_TaskShouldYield(void); + +/*! + * @brief Correct OSA tick counter for when exiting sleep + * + * This function allows the tick counter used by the OSA functions for time + * keeping to be corrected with the sleep duration (taken from a low power + * timer. This is available only in BM context and only if the systick is used + * as a time source for the OSA. + */ +void OSA_UpdateSysTickCounter(uint32_t corr); + /*! * @name Thread management * @{ diff --git a/components/osa/fsl_os_abstraction_free_rtos.c b/components/osa/fsl_os_abstraction_free_rtos.c index a214863c0..074ca7cdd 100644 --- a/components/osa/fsl_os_abstraction_free_rtos.c +++ b/components/osa/fsl_os_abstraction_free_rtos.c @@ -118,13 +118,13 @@ static osa_state_t s_osaState = {0}; * Description : Reserves the requested amount of memory in bytes. * *END**************************************************************************/ -void *OSA_MemoryAllocate(uint32_t length) +void *OSA_MemoryAllocate(uint32_t memLength) { - void *p = (void *)pvPortMalloc(length); + void *p = (void *)pvPortMalloc(memLength); if (NULL != p) { - (void)memset(p, 0, length); + (void)memset(p, 0, memLength); } return p; @@ -268,11 +268,40 @@ osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param) { osa_status_t status = KOSA_StatusError; - assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_freertos_task_t) + sizeof(StaticTask_t)) <= OSA_TASK_HANDLE_SIZE); +#else + assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); +#endif assert(NULL != taskHandle); +#if defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0) TaskHandle_t pxCreatedTask; +#endif osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + TaskHandle_t xHandle = NULL; +#endif OSA_InterruptDisable(); +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + xHandle = xTaskCreateStatic( + (TaskFunction_t)thread_def->pthread, /* pointer to the task */ + (const char *)thread_def->tname, /* task name for kernel awareness debugging */ + (uint32_t)((uint16_t)thread_def->stacksize / sizeof(portSTACK_TYPE)), /* task stack size */ + (task_param_t)task_param, /* optional task startup argument */ + PRIORITY_OSA_TO_RTOS((thread_def->tpriority)), /* initial priority */ + thread_def->tstack, /*Array to use as the task's stack*/ + (StaticTask_t *)((uint8_t *)(taskHandle) + sizeof(osa_freertos_task_t))/*Variable to hold the task's data structure*/ + ); + if(xHandle != NULL) + { + ptask->taskHandle = xHandle; + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link)); + status = KOSA_StatusSuccess; + } +#else if (xTaskCreate( (TaskFunction_t)thread_def->pthread, /* pointer to the task */ (char const *)thread_def->tname, /* task name for kernel awareness debugging */ @@ -288,6 +317,7 @@ osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t * status = KOSA_StatusSuccess; } +#endif OSA_InterruptEnable(); return status; } @@ -382,7 +412,12 @@ osa_status_t OSA_SemaphorePrecreate(osa_semaphore_handle_t semaphoreHandle, osa_ *END**************************************************************************/ osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) { +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_semaphore_handle_t) + sizeof(StaticQueue_t)) == OSA_SEM_HANDLE_SIZE); +#else assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE); +#endif assert(NULL != semaphoreHandle); union @@ -390,8 +425,12 @@ osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_ QueueHandle_t sem; uint32_t semhandle; } xSemaHandle; - +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + xSemaHandle.sem = xSemaphoreCreateCountingStatic(0xFF, initValue, (StaticQueue_t *)(void *)((uint8_t *)semaphoreHandle + sizeof(osa_semaphore_handle_t))); +#else xSemaHandle.sem = xSemaphoreCreateCounting(0xFF, initValue); +#endif if (NULL != xSemaHandle.sem) { *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle; @@ -409,7 +448,12 @@ osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_ *END**************************************************************************/ osa_status_t OSA_SemaphoreCreateBinary(osa_semaphore_handle_t semaphoreHandle) { +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_semaphore_handle_t) + sizeof(StaticQueue_t)) == OSA_SEM_HANDLE_SIZE); +#else assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE); +#endif assert(NULL != semaphoreHandle); union @@ -417,8 +461,12 @@ osa_status_t OSA_SemaphoreCreateBinary(osa_semaphore_handle_t semaphoreHandle) QueueHandle_t sem; uint32_t semhandle; } xSemaHandle; - +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + xSemaHandle.sem = xSemaphoreCreateBinaryStatic((StaticQueue_t *)(void *)((uint8_t *)semaphoreHandle + sizeof(osa_semaphore_handle_t))); +#else xSemaHandle.sem = xSemaphoreCreateBinary(); +#endif if (NULL != xSemaHandle.sem) { *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle; @@ -534,7 +582,12 @@ osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) *END**************************************************************************/ osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) { +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_mutex_handle_t) + sizeof(StaticQueue_t)) == OSA_MUTEX_HANDLE_SIZE); +#else assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE); +#endif assert(NULL != mutexHandle); union @@ -542,8 +595,12 @@ osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) QueueHandle_t mutex; uint32_t pmutexHandle; } xMutexHandle; - +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + xMutexHandle.mutex = xSemaphoreCreateRecursiveMutexStatic((StaticQueue_t *)(void *)((uint8_t *)mutexHandle + sizeof(osa_mutex_handle_t))); +#else xMutexHandle.mutex = xSemaphoreCreateRecursiveMutex(); +#endif if (NULL != xMutexHandle.mutex) { *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle; @@ -650,9 +707,20 @@ osa_status_t OSA_EventPrecreate(osa_event_handle_t eventHandle, osa_task_ptr_t t osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) { assert(NULL != eventHandle); - osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; - +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_event_struct_t) + sizeof(StaticEventGroup_t)) <= OSA_EVENT_HANDLE_SIZE); +#else + assert(sizeof(osa_event_struct_t) == OSA_EVENT_HANDLE_SIZE); +#endif + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + pEventStruct->handle = xEventGroupCreateStatic((StaticEventGroup_t *)(void *)((uint8_t *)(eventHandle) + sizeof(osa_event_struct_t))); +#else pEventStruct->handle = xEventGroupCreate(); +#endif if (NULL != pEventStruct->handle) { pEventStruct->autoClear = autoClear; @@ -869,7 +937,12 @@ osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) *END**************************************************************************/ osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) { +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + assert((sizeof(osa_msgq_handle_t) + sizeof(StaticQueue_t)) == OSA_MSGQ_HANDLE_SIZE); +#else assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE); +#endif assert(NULL != msgqHandle); union @@ -879,7 +952,14 @@ osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32 } xMsgqHandle; /* Create the message queue where the number and size is specified by msgNo and msgSize */ +#if (defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION > 0U)) && \ + !((defined(configSUPPORT_DYNAMIC_ALLOCATION) && (configSUPPORT_DYNAMIC_ALLOCATION > 0U))) + xMsgqHandle.msgq = xQueueCreateStatic(msgNo, msgSize, + (uint8_t *)((uint8_t *)msgqHandle + sizeof(osa_msgq_handle_t) + sizeof(StaticQueue_t)), + (StaticQueue_t *)(void *)((uint8_t *)msgqHandle + sizeof(osa_msgq_handle_t))); +#else xMsgqHandle.msgq = xQueueCreate(msgNo, msgSize); +#endif if (NULL != xMsgqHandle.msgq) { *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle; @@ -1076,6 +1156,30 @@ void OSA_DisableIRQGlobal(void) s_osaState.interruptDisableCount++; } +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableScheduler + * Description : Disable the scheduling of any task + * This function will disable the scheduling of any task + * + *END**************************************************************************/ +void OSA_DisableScheduler(void) +{ + vTaskSuspendAll(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableScheduler + * Description : Enable the scheduling of any task + * This function will enable the scheduling of any task + * + *END**************************************************************************/ +void OSA_EnableScheduler(void) +{ + (void)xTaskResumeAll(); +} + /*FUNCTION********************************************************************** * * Function Name : OSA_InstallIntHandler @@ -1146,4 +1250,4 @@ void OSA_Start(void) { vTaskStartScheduler(); } -#endif +#endif \ No newline at end of file diff --git a/components/osa/set_component_osa.cmake b/components/osa/set_component_osa.cmake index 299e70621..c73636aa6 100644 --- a/components/osa/set_component_osa.cmake +++ b/components/osa/set_component_osa.cmake @@ -124,27 +124,3 @@ endif() endif() - -if (CONFIG_USE_component_osa_thread) -# Add set(CONFIG_USE_component_osa_thread true) in config.cmake to use this component - -message("component_osa_thread component is included from ${CMAKE_CURRENT_LIST_FILE}.") - -if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists AND CONFIG_USE_component_osa_interface AND (CONFIG_USE_middleware_azure_rtos_tx OR CONFIG_USE_middleware_azure_rtos_tx_sp)) - -target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/./fsl_os_abstraction_threadx.c -) - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/./. -) - -else() - -message(SEND_ERROR "component_osa_thread dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") - -endif() - -endif() - diff --git a/components/p3t1755/fsl_p3t1755.c b/components/p3t1755/fsl_p3t1755.c new file mode 100644 index 000000000..8538e29ad --- /dev/null +++ b/components/p3t1755/fsl_p3t1755.c @@ -0,0 +1,63 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_p3t1755.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/******************************************************************************* + * Variables + ******************************************************************************/ +/******************************************************************************* + * Code + ******************************************************************************/ +status_t P3T1755_WriteReg(p3t1755_handle_t *handle, uint32_t regAddress, uint8_t *regData, size_t dataSize) +{ + status_t result; + result = handle->writeTransfer(handle->sensorAddress, regAddress, regData, dataSize); + + return (result == kStatus_Success) ? result : kStatus_Fail; +} + +status_t P3T1755_ReadReg(p3t1755_handle_t *handle, uint32_t regAddress, uint8_t *regData, size_t dataSize) +{ + status_t result; + result = handle->readTransfer(handle->sensorAddress, regAddress, regData, dataSize); + + return (result == kStatus_Success) ? result : kStatus_Fail; +} + +status_t P3T1755_Init(p3t1755_handle_t *handle, p3t1755_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(config->writeTransfer != NULL); + assert(config->readTransfer != NULL); + + handle->writeTransfer = config->writeTransfer; + handle->readTransfer = config->readTransfer; + handle->sensorAddress = config->sensorAddress; + + return kStatus_Success; +} + +status_t P3T1755_ReadTemperature(p3t1755_handle_t *handle, double *temperature) +{ + status_t result = kStatus_Success; + uint8_t data[2]; + + result = P3T1755_ReadReg(handle, P3T1755_TEMPERATURE_REG, &data[0], 2); + if (result == kStatus_Success) + { + *temperature = (double)((((uint16_t)data[0] << 8U) | (uint16_t)data[1]) >> 4U); + *temperature = *temperature * 0.0625; + } + + return result; +} diff --git a/components/p3t1755/fsl_p3t1755.h b/components/p3t1755/fsl_p3t1755.h new file mode 100644 index 000000000..0d99acef9 --- /dev/null +++ b/components/p3t1755/fsl_p3t1755.h @@ -0,0 +1,90 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_P3T1755_H_ +#define _FSL_P3T1755_H_ + +#include "fsl_common.h" + +/* Registers. */ +#define P3T1755_TEMPERATURE_REG (0x00U) +#define P3T1755_CONFIG_REG (0x01U) + +/*! @brief Define sensor access function. */ +typedef status_t (*sensor_write_transfer_func_t)(uint8_t deviceAddress, + uint32_t regAddress, + uint8_t *regData, + size_t dataSize); +typedef status_t (*sensor_read_transfer_func_t)(uint8_t deviceAddress, + uint32_t regAddress, + uint8_t *regData, + size_t dataSize); + +typedef struct _p3t1755_handle +{ + sensor_write_transfer_func_t writeTransfer; + sensor_read_transfer_func_t readTransfer; + uint8_t sensorAddress; +} p3t1755_handle_t; + +typedef struct _p3t1755_config +{ + sensor_write_transfer_func_t writeTransfer; + sensor_read_transfer_func_t readTransfer; + uint8_t sensorAddress; +} p3t1755_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Create handle for P3T1755, reset the sensor per user configuration. + * + * @param p3t1755_handle The pointer to #p3t1755_handle_t. + * + * @return kStatus_Success if success or kStatus_Fail if error. + */ +status_t P3T1755_Init(p3t1755_handle_t *handle, p3t1755_config_t *config); + +/*! + * @brief Write Register with register data buffer. + * + * @param handle The pointer to #p3t1755_handle_t. + * @param regAddress register address to write. + * @param regData The pointer to data buffer to be write to the reg. + * @param dataSize Size of the regData. + * + * @return kStatus_Success if success or kStatus_Fail if error. + */ +status_t P3T1755_WriteReg(p3t1755_handle_t *handle, uint32_t regAddress, uint8_t *regData, size_t dataSize); + +/*! + * @brief Read Register to speficied data buffer. + * + * @param handle The pointer to #p3t1755_handle_t. + * @param regAddress register address to read. + * @param regData The pointer to data buffer to store the read out data. + * @param dataSize Size of the regData to be read. + * + * @return kStatus_Success if success or kStatus_Fail if error. + */ +status_t P3T1755_ReadReg(p3t1755_handle_t *handle, uint32_t regAddress, uint8_t *regData, size_t dataSize); + +/*! + * @brief Read temperature data. + * + * @param handle The pointer to #p3t1755_handle_t. + * @param temperature The pointer to temperature data. + * + * @return kStatus_Success if success or kStatus_Fail if error. + */ +status_t P3T1755_ReadTemperature(p3t1755_handle_t *handle, double *temperature); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _FSL_P3T1755_H_ */ diff --git a/components/pf1550/fsl_pf1550_charger.h b/components/pf1550/fsl_pf1550_charger.h index 72b31b630..5ff2dd709 100644 --- a/components/pf1550/fsl_pf1550_charger.h +++ b/components/pf1550/fsl_pf1550_charger.h @@ -84,11 +84,11 @@ typedef enum _pf1550_charger_operation kPF1550_ChargerOperation_ChargerOffLinearOff = 0x0U, /* Charger = off, linear = off. The BATFET switch is on to allow the battery to support the system. */ kPF1550_ChargerOperation_ChargerOffLinearOn = - 0x1U, /* Charger = off, linear = on, When there is a valid input, - the linear regulator regulates the system voltage to be VCHGCV. */ - kPF1550_ChargerOperation_ChargerOnLinearOn = 0x2U, /* Charger = on, linear = on. When there is a valid input, - the battery is charging. VSYS is the larger of VMINSYS - and ~ VBATT + IBAT * RBATFET. */ + 0x1U, /* Charger = off, linear = on, When there is a valid input, + the linear regulator regulates the system voltage to be VCHGCV. */ + kPF1550_ChargerOperation_ChargerOnLinearOn = 0x2U, /* Charger = on, linear = on. When there is a valid input, + the battery is charging. VSYS is the larger of VMINSYS + and ~ VBATT + IBAT * RBATFET. */ } pf1550_charger_operation_t; /*! @brief PF1550 Thermaistor Configuration definition. */ diff --git a/components/pf3000/fsl_pf3000.h b/components/pf3000/fsl_pf3000.h index dc88cef67..aa15254a1 100644 --- a/components/pf3000/fsl_pf3000.h +++ b/components/pf3000/fsl_pf3000.h @@ -112,22 +112,22 @@ typedef enum _pf3000_module /*! @brief PF3000 Interrupt Source definition. */ enum _pf3000_interrupt_source { - kPF3000_IntSrcPwrOn = 0x1U, /* Power on. */ - kPF3000_IntSrcLowVoltage = 0x2U, /* Low-voltage. */ - kPF3000_IntSrcTherm110 = 0x4U, /* Die temperature crosses 110C interrupt source. */ - kPF3000_IntSrcTherm120 = 0x8U, /* Die temperature crosses 120C interrupt source. */ - kPF3000_IntSrcTherm125 = 0x10U, /* Die temperature crosses 125C interrupt source. */ - kPF3000_IntSrcTherm130 = 0x20U, /* Die temperature crosses 130C interrupt source. */ - - kPF3000_IntSrcSw1aCurrentLimit = 0x1U << 8U, /* Switch1A current limit interrupt source. */ - kPF3000_IntSrcSw1bCurrentLimit = 0x2U << 8U, /* Switch1B current limit interrupt source. */ - kPF3000_IntSrcSw2CurrentLimit = 0x8U << 8U, /* Switch2 current limit interrupt source. */ - kPF3000_IntSrcSw3CurrentLimit = 0x10U << 8U, /* Switch3 current limit interrupt source. */ - - kPF3000_IntSrcSwBstCurrentLimit = 0x1U << 16U, /* Switch Boost current limit interrupt source. */ - kPF3000_IntSrcVpwrVoltageLimit = 0x4U << 16U, /* VPWR overvoltage interrupt source. */ - kPF3000_IntSrcOtpAutoFuseDone = 0x40U << 16U, /* OTP auto fuse blow interrupt source. */ - kPF3000_IntSrcOtpError = 0x80U << 16U, /* OTP error interrupt source. */ + kPF3000_IntSrcPwrOn = 0x1U, /* Power on. */ + kPF3000_IntSrcLowVoltage = 0x2U, /* Low-voltage. */ + kPF3000_IntSrcTherm110 = 0x4U, /* Die temperature crosses 110C interrupt source. */ + kPF3000_IntSrcTherm120 = 0x8U, /* Die temperature crosses 120C interrupt source. */ + kPF3000_IntSrcTherm125 = 0x10U, /* Die temperature crosses 125C interrupt source. */ + kPF3000_IntSrcTherm130 = 0x20U, /* Die temperature crosses 130C interrupt source. */ + + kPF3000_IntSrcSw1aCurrentLimit = 0x1U << 8U, /* Switch1A current limit interrupt source. */ + kPF3000_IntSrcSw1bCurrentLimit = 0x2U << 8U, /* Switch1B current limit interrupt source. */ + kPF3000_IntSrcSw2CurrentLimit = 0x8U << 8U, /* Switch2 current limit interrupt source. */ + kPF3000_IntSrcSw3CurrentLimit = 0x10U << 8U, /* Switch3 current limit interrupt source. */ + + kPF3000_IntSrcSwBstCurrentLimit = 0x1U << 16U, /* Switch Boost current limit interrupt source. */ + kPF3000_IntSrcVpwrVoltageLimit = 0x4U << 16U, /* VPWR overvoltage interrupt source. */ + kPF3000_IntSrcOtpAutoFuseDone = 0x40U << 16U, /* OTP auto fuse blow interrupt source. */ + kPF3000_IntSrcOtpError = 0x80U << 16U, /* OTP error interrupt source. */ kPF3000_IntSrcLdo1CurrentLimit = 0x1U << 24U, /* LDO1 current limit interrupt source. */ kPF3000_IntSrcLdo2CurrentLimit = 0x2U << 24U, /* LDO2 current limit interrupt source. */ diff --git a/components/phy/device/phylan8741/fsl_phylan8741.c b/components/phy/device/phylan8741/fsl_phylan8741.c new file mode 100644 index 000000000..fa51d0852 --- /dev/null +++ b/components/phy/device/phylan8741/fsl_phylan8741.c @@ -0,0 +1,345 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_phylan8741.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the PHY LAN8741 vendor defined registers. */ +#define PHY_CONTROL_REG 0x11U /*!< The PHY control/status register. */ +#define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY special control/status register. */ + +/*! @brief Defines the PHY LAN8741 device ID information. */ +#define PHY_OUI 0x1F0U /*!< The PHY organizationally unique identifier. */ +#define PHY_MODEL_NUM 0x12U /*!< The PHY model number, 6-bit. */ +#define PHY_DEVICE_ID ((PHY_OUI << 10U) | (PHY_MODEL_NUM << 4U)) + +/*!@brief Defines the mask flag of operation mode in control register*/ +#define PHY_CTL_FARLOOPBACK_MASK 0x200U + +/*!@brief Defines the mask flag of operation mode in special control register*/ +#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */ +#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */ +#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */ +#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */ +#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_ALL_CAPABLE_MASK 0x1E0U + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 500000U + +/*! @brief Defines the PHY resource interface. */ +#define PHY_LAN8741_WRITE(handle, regAddr, data) \ + ((phy_lan8741_resource_t *)(handle)->resource)->write((handle)->phyAddr, regAddr, data) +#define PHY_LAN8741_READ(handle, regAddr, pData) \ + ((phy_lan8741_resource_t *)(handle)->resource)->read((handle)->phyAddr, regAddr, pData) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const phy_operations_t phylan8741_ops = {.phyInit = PHY_LAN8741_Init, + .phyWrite = PHY_LAN8741_Write, + .phyRead = PHY_LAN8741_Read, + .getAutoNegoStatus = PHY_LAN8741_GetAutoNegotiationStatus, + .getLinkStatus = PHY_LAN8741_GetLinkStatus, + .getLinkSpeedDuplex = PHY_LAN8741_GetLinkSpeedDuplex, + .setLinkSpeedDuplex = PHY_LAN8741_SetLinkSpeedDuplex, + .enableLoopback = PHY_LAN8741_EnableLoopback}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_LAN8741_Init(phy_handle_t *handle, const phy_config_t *config) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + status_t result = kStatus_Success; + uint16_t regValue = 0U; + uint32_t devId = 0U; + + /* Assign PHY address and operation resource. */ + handle->phyAddr = config->phyAddr; + handle->resource = config->resource; + + /* Check PHY ID. */ + do + { + result = PHY_LAN8741_READ(handle, PHY_ID1_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + devId = (uint32_t)regValue << 16U; + + result = PHY_LAN8741_READ(handle, PHY_ID2_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + devId += regValue; + + /* The default revision number field(4-bit) may vary dependent on the silicon revision number. */ + devId &= ~((uint32_t)0xF); + + counter--; + } while ((devId != PHY_DEVICE_ID) && (counter != 0U)); + + if (counter == 0U) + { + return kStatus_Fail; + } + counter = PHY_TIMEOUT_COUNT; + + /* Reset PHY and wait until completion. */ + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result != kStatus_Success) + { + return result; + } + do + { + result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + } while ((counter-- != 0U) && (regValue & PHY_BCTL_RESET_MASK) != 0U); + + if (counter == 0U) + { + return kStatus_Fail; + } + + if (config->autoNeg) + { + /* Set the ability. */ + result = + PHY_LAN8741_WRITE(handle, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | PHY_IEEE802_3_SELECTOR_MASK)); + if (result == kStatus_Success) + { + /* Start Auto negotiation and wait until auto negotiation completion */ + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* This PHY only supports 10/100M speed. */ + assert(config->speed <= kPHY_Speed100M); + + /* Disable isolate mode */ + result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, ®Value); + if (result != kStatus_Success) + { + return result; + } + regValue &= PHY_BCTL_ISOLATE_MASK; + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, regValue); + if (result != kStatus_Success) + { + return result; + } + + /* Disable the auto-negotiation and set user-defined speed/duplex configuration. */ + result = PHY_LAN8741_SetLinkSpeedDuplex(handle, config->speed, config->duplex); + } + + return result; +} + +status_t PHY_LAN8741_Write(phy_handle_t *handle, uint8_t phyReg, uint16_t data) +{ + return PHY_LAN8741_WRITE(handle, phyReg, data); +} + +status_t PHY_LAN8741_Read(phy_handle_t *handle, uint8_t phyReg, uint16_t *pData) +{ + return PHY_LAN8741_READ(handle, phyReg, pData); +} + +status_t PHY_LAN8741_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) +{ + assert(status); + + status_t result; + uint16_t regValue; + + *status = false; + + /* Check auto negotiation complete. */ + result = PHY_LAN8741_READ(handle, PHY_SEPCIAL_CONTROL_REG, ®Value); + if (result == kStatus_Success) + { + if ((regValue & PHY_SPECIALCTL_AUTONEGDONE_MASK) != 0U) + { + *status = true; + } + } + return result; +} + +status_t PHY_LAN8741_GetLinkStatus(phy_handle_t *handle, bool *status) +{ + assert(status); + + uint16_t regValue; + status_t result; + + /* Read the basic status register. */ + result = PHY_LAN8741_READ(handle, PHY_BASICSTATUS_REG, ®Value); + if (result == kStatus_Success) + { + if ((regValue & PHY_BSTATUS_LINKSTATUS_MASK) != 0U) + { + /* Link up. */ + *status = true; + } + else + { + /* Link down. */ + *status = false; + } + } + return result; +} + +status_t PHY_LAN8741_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(!((speed == NULL) && (duplex == NULL))); + + uint16_t regValue; + status_t result; + + /* Read the control register. */ + result = PHY_LAN8741_READ(handle, PHY_SEPCIAL_CONTROL_REG, ®Value); + if (result == kStatus_Success) + { + if (speed != NULL) + { + if ((regValue & PHY_SPECIALCTL_100SPEED_MASK) != 0U) + { + *speed = kPHY_Speed100M; + } + else + { + *speed = kPHY_Speed10M; + } + } + + if (duplex != NULL) + { + if ((regValue & PHY_SPECIALCTL_DUPLEX_MASK) != 0U) + { + *duplex = kPHY_FullDuplex; + } + else + { + *duplex = kPHY_HalfDuplex; + } + } + } + return result; +} + +status_t PHY_LAN8741_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) +{ + /* This PHY only supports 10/100M speed. */ + assert(speed <= kPHY_Speed100M); + + status_t result; + uint16_t regValue; + + result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) + { + /* Disable the auto-negotiation and set according to user-defined configuration. */ + regValue &= ~PHY_BCTL_AUTONEG_MASK; + if (speed == kPHY_Speed100M) + { + regValue |= PHY_BCTL_SPEED0_MASK; + } + else + { + regValue &= ~PHY_BCTL_SPEED0_MASK; + } + if (duplex == kPHY_FullDuplex) + { + regValue |= PHY_BCTL_DUPLEX_MASK; + } + else + { + regValue &= ~PHY_BCTL_DUPLEX_MASK; + } + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, regValue); + } + return result; +} + +status_t PHY_LAN8741_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + /* This PHY only supports local/remote loopback and 10/100M speed. */ + assert(mode <= kPHY_RemoteLoop); + assert(speed <= kPHY_Speed100M); + + status_t result; + uint16_t regValue; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + if (speed == kPHY_Speed100M) + { + regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, regValue); + } + else + { + result = PHY_LAN8741_READ(handle, PHY_CONTROL_REG, ®Value); + if (result == kStatus_Success) + { + result = PHY_LAN8741_WRITE(handle, PHY_CONTROL_REG, regValue | PHY_CTL_FARLOOPBACK_MASK); + } + } + } + else + { + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) + { + regValue &= ~PHY_BCTL_LOOP_MASK; + result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, regValue | PHY_BCTL_RESTART_AUTONEG_MASK); + } + } + else + { + result = PHY_LAN8741_READ(handle, PHY_CONTROL_REG, ®Value); + if (result == kStatus_Success) + { + result = PHY_LAN8741_WRITE(handle, PHY_CONTROL_REG, regValue & ~PHY_CTL_FARLOOPBACK_MASK); + } + } + } + return result; +} diff --git a/components/phy/device/phylan8741/fsl_phylan8741.h b/components/phy/device/phylan8741/fsl_phylan8741.h new file mode 100644 index 000000000..8493a1ba1 --- /dev/null +++ b/components/phy/device/phylan8741/fsl_phylan8741.h @@ -0,0 +1,166 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/***************************************************************************** + * PHY LAN8741 driver change log + *****************************************************************************/ + +/*! +@page driver_log Driver Change Log + +@section phylan8741 PHYLAN8741 + The current PHYLAN8741 driver version is 2.0.0. + + - 2.0.0 + - Initial version. +*/ + +#ifndef _FSL_PHYLAN8741_H_ +#define _FSL_PHYLAN8741_H_ + +#include "fsl_phy.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +typedef struct _phy_lan8741_resource +{ + mdioWrite write; + mdioRead read; +} phy_lan8741_resource_t; + +extern const phy_operations_t phylan8741_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * This function initializes PHY. + * + * @param handle PHY device handle. + * @param config Pointer to structure of phy_config_t. + * @retval kStatus_Success PHY initialization succeeds + * @retval kStatus_Fail PHY initialization fails + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_Init(phy_handle_t *handle, const phy_config_t *config); + +/*! + * @brief PHY Write function. + * This function writes data over the MDIO to the specified PHY register. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_Write(phy_handle_t *handle, uint8_t phyReg, uint16_t data); + +/*! + * @brief PHY Read function. + * This interface reads data over the MDIO from the specified PHY register. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param pData The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_Read(phy_handle_t *handle, uint8_t phyReg, uint16_t *pData); + +/*! + * @brief Gets the PHY auto-negotiation status. + * + * @param handle PHY device handle. + * @param status The auto-negotiation status of the PHY. + * - true the auto-negotiation is over. + * - false the auto-negotiation is on-going or not started. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link status. + * + * @param handle PHY device handle. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY gets link status success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_GetLinkStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @brief This function gets the speed and duplex mode of PHY. User can give one of speed + * and duplex address paramter and set the other as NULL if only wants to get one of them. + * + * @param handle PHY device handle. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY gets link speed and duplex success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex); + +/*! + * @brief Sets the PHY link speed and duplex. + * + * @param handle PHY device handle. + * @param speed Specified PHY link speed. + * @param duplex Specified PHY link duplex. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex); + +/*! + * @brief Enable PHY loopcback mode. + * + * @param handle PHY device handle. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * All loopback modes should not be set together, when one loopback mode is set + * another should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_Timeout PHY MDIO visit time out + */ +status_t PHY_LAN8741_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHYLAN8741_H_ */ diff --git a/components/rtt/RTT/SEGGER_RTT.c b/components/rtt/RTT/SEGGER_RTT.c index 40d10417c..8b1129487 100644 --- a/components/rtt/RTT/SEGGER_RTT.c +++ b/components/rtt/RTT/SEGGER_RTT.c @@ -67,7 +67,7 @@ Additional information: WrOff == (RdOff - 1): Buffer is full WrOff > RdOff: Free space includes wrap-around WrOff < RdOff: Used space includes wrap-around - (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): Buffer full and wrap-around after next byte @@ -76,7 +76,7 @@ Additional information: #include "SEGGER_RTT.h" -#include // for memcpy +#include // for memcpy /* * For CMSIS pack RTE. @@ -88,2000 +88,2271 @@ Additional information: #endif /********************************************************************* -* -* Configuration, default values -* -********************************************************************** -*/ + * + * Configuration, default values + * + ********************************************************************** + */ #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #ifdef SEGGER_RTT_CB_ALIGN - #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGN - #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_CB_SECTION - #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_BUFFER_SECTION - #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGNMENT - #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_ALIGNMENT - #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif +#ifdef SEGGER_RTT_CB_ALIGN +#error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif +#ifdef SEGGER_RTT_BUFFER_ALIGN +#error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif +#ifdef SEGGER_RTT_PUT_CB_SECTION +#error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif +#ifdef SEGGER_RTT_PUT_BUFFER_SECTION +#error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif +#ifdef SEGGER_RTT_BUFFER_ALIGNMENT +#error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif +#ifdef SEGGER_RTT_ALIGNMENT +#error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif #endif -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#ifndef BUFFER_SIZE_UP +#define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host #endif -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#ifndef BUFFER_SIZE_DOWN +#define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) #endif -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target #endif -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target #endif #ifndef SEGGER_RTT_BUFFER_SECTION - #if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION - #endif +#if defined(SEGGER_RTT_SECTION) +#define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION +#endif #endif -#ifndef SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#ifndef SEGGER_RTT_ALIGNMENT +#define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE #endif -#ifndef SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT +#define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE #endif -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#ifndef SEGGER_RTT_MODE_DEFAULT +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP #endif -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() +#ifndef SEGGER_RTT_LOCK +#define SEGGER_RTT_LOCK() #endif -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() +#ifndef SEGGER_RTT_UNLOCK +#define SEGGER_RTT_UNLOCK() #endif -#ifndef STRLEN - #define STRLEN(a) strlen((a)) +#ifndef STRLEN +#define STRLEN(a) strlen((a)) #endif -#ifndef STRCPY - #define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) +#ifndef STRCPY +#define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) #endif -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP +#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 #endif -#ifndef SEGGER_RTT_MEMCPY - #ifdef MEMCPY - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) - #else - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) - #endif +#ifndef SEGGER_RTT_MEMCPY +#ifdef MEMCPY +#define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) +#else +#define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) +#endif #endif -#ifndef MIN - #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) #endif -#ifndef MAX - #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif // // For some environments, NULL may not be defined until certain headers are included // #ifndef NULL - #define NULL 0 +#define NULL 0 #endif /********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ + * + * Defines, fixed + * + ********************************************************************** + */ #if (defined __ICCARM__) || (defined __ICCRX__) - #define RTT_PRAGMA(P) _Pragma(#P) +#define RTT_PRAGMA(P) _Pragma(#P) #endif #if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT - #if (defined __GNUC__) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #elif (defined __ICCARM__) || (defined __ICCRX__) - #define PRAGMA(A) _Pragma(#A) -#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #else - #error "Alignment not supported for this compiler." - #endif +#if (defined __GNUC__) +#define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__((aligned(Alignment))) +#elif (defined __ICCARM__) || (defined __ICCRX__) +#define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) \ + RTT_PRAGMA(data_alignment = Alignment) \ + Var +#elif (defined __CC_ARM) +#define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__((aligned(Alignment))) #else - #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#error "Alignment not supported for this compiler." +#endif +#else +#define SEGGER_RTT_ALIGN(Var, Alignment) Var #endif -#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) - #if (defined __GNUC__) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var - #elif (defined __ICCARM__) || (defined __ICCRX__) -#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var - #else - #error "Section placement not supported for this compiler." - #endif +#if defined(SEGGER_RTT_SECTION) || defined(SEGGER_RTT_BUFFER_SECTION) +#if (defined __GNUC__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__((section(Section))) Var +#elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) \ + RTT_PRAGMA(location = Section) \ + Var +#elif (defined __CC_ARM) +#define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__((section(Section), zero_init)) Var #else - #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#error "Section placement not supported for this compiler." +#endif +#else +#define SEGGER_RTT_PUT_SECTION(Var, Section) Var #endif #if SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) #else - #define SEGGER_RTT_CB_ALIGN(Var) Var +#define SEGGER_RTT_CB_ALIGN(Var) Var #endif #if SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) #else - #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#define SEGGER_RTT_BUFFER_ALIGN(Var) Var #endif - #if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) #else - #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#define SEGGER_RTT_PUT_CB_SECTION(Var) Var #endif #if defined(SEGGER_RTT_BUFFER_SECTION) - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) #else - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var #endif /********************************************************************* -* -* Static const data -* -********************************************************************** -*/ + * + * Static const data + * + ********************************************************************** + */ -static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; +static unsigned char _aTerminalId[16] = {'0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; /********************************************************************* -* -* Static data -* -********************************************************************** -*/ + * + * Static data + * + ********************************************************************** + */ // // RTT Control Block and allocate buffers for channel 0 // SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); -SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)])); -SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)])); +SEGGER_RTT_PUT_BUFFER_SECTION( + SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)])); +SEGGER_RTT_PUT_BUFFER_SECTION( + SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)])); static unsigned char _ActiveTerminal; /********************************************************************* -* -* Static functions -* -********************************************************************** -*/ + * + * Static functions + * + ********************************************************************** + */ /********************************************************************* -* -* _DoInit() -* -* Function description -* Initializes the control block an buffers. -* May only be called via INIT() to avoid overriding settings. -* -*/ -#define INIT() { \ - volatile SEGGER_RTT_CB* pRTTCBInit; \ - pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ - do { \ - if (pRTTCBInit->acID[0] == '\0') { \ - _DoInit(); \ - } \ - } while (0); \ - } + * + * _DoInit() + * + * Function description + * Initializes the control block an buffers. + * May only be called via INIT() to avoid overriding settings. + * + */ +#define INIT() \ + { \ + volatile SEGGER_RTT_CB *pRTTCBInit; \ + pRTTCBInit = (volatile SEGGER_RTT_CB *)((char *)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ + do \ + { \ + if (pRTTCBInit->acID[0] == '\0') \ + { \ + _DoInit(); \ + } \ + } while (0); \ + } -static void _DoInit(void) { - volatile SEGGER_RTT_CB* p; // Volatile to make sure that compiler cannot change the order of accesses to the control block - // - // Initialize control block - // - p = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly - p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; - p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; - // - // Initialize up buffer 0 - // - p->aUp[0].sName = "Terminal"; - p->aUp[0].pBuffer = _acUpBuffer; - p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; - p->aUp[0].RdOff = 0u; - p->aUp[0].WrOff = 0u; - p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Initialize down buffer 0 - // - p->aDown[0].sName = "Terminal"; - p->aDown[0].pBuffer = _acDownBuffer; - p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; - p->aDown[0].RdOff = 0u; - p->aDown[0].WrOff = 0u; - p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Finish initialization of the control block. - // Copy Id string in three steps to make sure "SEGGER RTT" is not found - // in initializer memory (usually flash) by J-Link - // - STRCPY((char*)&p->acID[7], "RTT"); - RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order - STRCPY((char*)&p->acID[0], "SEGGER"); - RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order - p->acID[6] = ' '; - RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order +static void _DoInit(void) +{ + volatile SEGGER_RTT_CB + *p; // Volatile to make sure that compiler cannot change the order of accesses to the control block + // + // Initialize control block + // + p = (volatile SEGGER_RTT_CB + *)((char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes + // dirty and all changes are visible in HW directly + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string in three steps to make sure "SEGGER RTT" is not found + // in initializer memory (usually flash) by J-Link + // + STRCPY((char *)&p->acID[7], "RTT"); + RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order + STRCPY((char *)&p->acID[0], "SEGGER"); + RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order + p->acID[6] = ' '; + RTT__DMB(); // Force order of memory accessed inside core for cores that allow to change the order } /********************************************************************* -* -* _WriteBlocking() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* The caller is responsible for managing the write chunk sizes as -* _WriteBlocking() will block until all data has been posted successfully. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* >= 0 - Number of bytes written into buffer. -*/ -static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { - unsigned NumBytesToWrite; - unsigned NumBytesWritten; - unsigned RdOff; - unsigned WrOff; - volatile char* pDst; - // - // Write data to buffer and handle wrap-around if necessary - // - NumBytesWritten = 0u; - WrOff = pRing->WrOff; - do { - RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime - if (RdOff > WrOff) { - NumBytesToWrite = RdOff - WrOff - 1u; - } else { - NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); - } - NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around - NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + * + * _WriteBlocking() + * + * Function description + * Stores a specified number of characters in SEGGER RTT ring buffer + * and updates the associated write pointer which is periodically + * read by the host. + * The caller is responsible for managing the write chunk sizes as + * _WriteBlocking() will block until all data has been posted successfully. + * + * Parameters + * pRing Ring buffer to post to. + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Return value + * >= 0 - Number of bytes written into buffer. + */ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP *pRing, const char *pBuffer, unsigned NumBytes) +{ + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; + volatile char *pDst; + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do + { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) + { + NumBytesToWrite = RdOff - WrOff - 1u; + } + else + { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - + WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesWritten += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; - while (NumBytesToWrite--) { - *pDst++ = *pBuffer++; - }; + NumBytesWritten += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + while (NumBytesToWrite--) + { + *pDst++ = *pBuffer++; + }; #else - SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite); - NumBytesWritten += NumBytesToWrite; - pBuffer += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; + SEGGER_RTT_MEMCPY((void *)pDst, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; #endif - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0u; - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - } while (NumBytes); - return NumBytesWritten; + if (WrOff == pRing->SizeOfBuffer) + { + WrOff = 0u; + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff; + } while (NumBytes); + return NumBytesWritten; } /********************************************************************* -* -* _WriteNoCheck() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* It is callers responsibility to make sure data actually fits in buffer. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking -*/ -static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { - unsigned NumBytesAtOnce; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - - WrOff = pRing->WrOff; - Rem = pRing->SizeOfBuffer - WrOff; - if (Rem > NumBytes) { - // - // All data fits before wrap around - // - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + * + * _WriteNoCheck() + * + * Function description + * Stores a specified number of characters in SEGGER RTT ring buffer + * and updates the associated write pointer which is periodically + * read by the host. + * It is callers responsibility to make sure data actually fits in buffer. + * + * Parameters + * pRing Ring buffer to post to. + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Notes + * (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking + */ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP *pRing, const char *pData, unsigned NumBytes) +{ + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; + volatile char *pDst; + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) + { + // + // All data fits before wrap around + // + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - WrOff += NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; + WrOff += NumBytes; + while (NumBytes--) + { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff; #else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; + SEGGER_RTT_MEMCPY((void *)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff + NumBytes; #endif - } else { - // - // We reach the end of the buffer, so need to wrap around - // + } + else + { + // + // We reach the end of the buffer, so need to wrap around + // #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = NumBytes - Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes - Rem; + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = Rem; + while (NumBytesAtOnce--) + { + *pDst++ = *pData++; + }; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = NumBytes - Rem; + while (NumBytesAtOnce--) + { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = NumBytes - Rem; #else - NumBytesAtOnce = Rem; - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce); - NumBytesAtOnce = NumBytes - Rem; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytesAtOnce; + NumBytesAtOnce = Rem; + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void *)pDst, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void *)pDst, pData + Rem, NumBytesAtOnce); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = NumBytesAtOnce; #endif - } + } } /********************************************************************* -* -* _PostTerminalSwitch() -* -* Function description -* Switch terminal to the given terminal ID. It is the caller's -* responsibility to ensure the terminal ID is correct and there is -* enough space in the buffer for this to complete successfully. -* -* Parameters -* pRing Ring buffer to post to. -* TerminalId Terminal ID to switch to. -*/ -static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { - unsigned char ac[2]; + * + * _PostTerminalSwitch() + * + * Function description + * Switch terminal to the given terminal ID. It is the caller's + * responsibility to ensure the terminal ID is correct and there is + * enough space in the buffer for this to complete successfully. + * + * Parameters + * pRing Ring buffer to post to. + * TerminalId Terminal ID to switch to. + */ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP *pRing, unsigned char TerminalId) +{ + unsigned char ac[2]; - ac[0] = 0xFFu; - ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit - _WriteBlocking(pRing, (const char*)ac, 2u); + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, (const char *)ac, 2u); } /********************************************************************* -* -* _GetAvailWriteSpace() -* -* Function description -* Returns the number of bytes that can be written to the ring -* buffer without blocking. -* -* Parameters -* pRing Ring buffer to check. -* -* Return value -* Number of bytes that are free in the buffer. -*/ -static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - if (RdOff <= WrOff) { - r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; - } else { - r = RdOff - WrOff - 1u; - } - return r; + * + * _GetAvailWriteSpace() + * + * Function description + * Returns the number of bytes that can be written to the ring + * buffer without blocking. + * + * Parameters + * pRing Ring buffer to check. + * + * Return value + * Number of bytes that are free in the buffer. + */ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP *pRing) +{ + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) + { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } + else + { + r = RdOff - WrOff - 1u; + } + return r; } /********************************************************************* -* -* Public code -* -********************************************************************** -*/ + * + * Public code + * + ********************************************************************** + */ /********************************************************************* -* -* SEGGER_RTT_ReadUpBufferNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Do not lock against interrupts and multiple access. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_UP* pRing; - volatile char* pSrc; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; + * + * SEGGER_RTT_ReadUpBufferNoLock() + * + * Function description + * Reads characters from SEGGER real-time-terminal control block + * which have been previously stored by the application. + * Do not lock against interrupts and multiple access. + * Used to do the same operation that J-Link does, to transfer + * RTT data via other channels, such as TCP/IP or UART. + * + * Parameters + * BufferIndex Index of Up-buffer to be used. + * pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. + * BufferSize Size of the target application buffer. + * + * Return value + * Number of bytes that have been read. + * + * Additional information + * This function must not be called when J-Link might also do RTT. + */ +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void *pData, unsigned BufferSize) +{ + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char *pBuffer; + SEGGER_RTT_BUFFER_UP *pRing; + volatile char *pSrc; + + INIT(); + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char *)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) + { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) + { + *pBuffer++ = *pSrc++; + }; #else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; + SEGGER_RTT_MEMCPY(pBuffer, (void *)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; #endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) + { + RdOff = 0u; + } + } // - // Handle wrap-around of buffer + // Read remaining items of buffer // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) + { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) + { + *pBuffer++ = *pSrc++; + }; #else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; + SEGGER_RTT_MEMCPY(pBuffer, (void *)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; #endif - } - // - // Update read offset of buffer - // - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; + } + // + // Update read offset of buffer + // + if (NumBytesRead) + { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; } /********************************************************************* -* -* SEGGER_RTT_ReadNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* Do not lock against interrupts and multiple access. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_DOWN* pRing; - volatile char* pSrc; - // - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; + * + * SEGGER_RTT_ReadNoLock() + * + * Function description + * Reads characters from SEGGER real-time-terminal control block + * which have been previously stored by the host. + * Do not lock against interrupts and multiple access. + * + * Parameters + * BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. + * BufferSize Size of the target application buffer. + * + * Return value + * Number of bytes that have been read. + */ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void *pData, unsigned BufferSize) +{ + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char *pBuffer; + SEGGER_RTT_BUFFER_DOWN *pRing; + volatile char *pSrc; + // + INIT(); + pRing = + (SEGGER_RTT_BUFFER_DOWN *)((char *)&_SEGGER_RTT.aDown[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char *)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) + { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) + { + *pBuffer++ = *pSrc++; + }; #else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; + SEGGER_RTT_MEMCPY(pBuffer, (void *)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; #endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) + { + RdOff = 0u; + } + } // - // Handle wrap-around of buffer + // Read remaining items of buffer // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) + { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) + { + *pBuffer++ = *pSrc++; + }; #else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; + SEGGER_RTT_MEMCPY(pBuffer, (void *)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; #endif - } - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; + } + if (NumBytesRead) + { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; } /********************************************************************* -* -* SEGGER_RTT_ReadUpBuffer -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the read operation, writing is also locked. -* If only one consumer reads from the up buffer, -* call sEGGER_RTT_ReadUpBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; + * + * SEGGER_RTT_ReadUpBuffer + * + * Function description + * Reads characters from SEGGER real-time-terminal control block + * which have been previously stored by the application. + * Used to do the same operation that J-Link does, to transfer + * RTT data via other channels, such as TCP/IP or UART. + * + * Parameters + * BufferIndex Index of Up-buffer to be used. + * pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. + * BufferSize Size of the target application buffer. + * + * Return value + * Number of bytes that have been read. + * + * Additional information + * This function must not be called when J-Link might also do RTT. + * This function locks against all other RTT operations. I.e. during + * the read operation, writing is also locked. + * If only one consumer reads from the up buffer, + * call sEGGER_RTT_ReadUpBufferNoLock() instead. + */ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void *pBuffer, unsigned BufferSize) +{ + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; } /********************************************************************* -* -* SEGGER_RTT_Read -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; + * + * SEGGER_RTT_Read + * + * Function description + * Reads characters from SEGGER real-time-terminal control block + * which have been previously stored by the host. + * + * Parameters + * BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. + * BufferSize Size of the target application buffer. + * + * Return value + * Number of bytes that have been read. + */ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void *pBuffer, unsigned BufferSize) +{ + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; } /********************************************************************* -* -* SEGGER_RTT_WriteWithOverwriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block. -* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application -* and overwrites data if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, data is overwritten. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link -* connection reads RTT data. -*/ -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - volatile char* pDst; - // - // Get "to-host" ring buffer and copy some elements into local variables. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Check if we will overwrite data and need to adjust the RdOff. - // - if (pRing->WrOff == pRing->RdOff) { - Avail = pRing->SizeOfBuffer - 1u; - } else if ( pRing->WrOff < pRing->RdOff) { - Avail = pRing->RdOff - pRing->WrOff - 1u; - } else { - Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; - } - if (NumBytes > Avail) { - pRing->RdOff += (NumBytes - Avail); - while (pRing->RdOff >= pRing->SizeOfBuffer) { - pRing->RdOff -= pRing->SizeOfBuffer; + * + * SEGGER_RTT_WriteWithOverwriteNoLock + * + * Function description + * Stores a specified number of characters in SEGGER RTT + * control block. + * SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application + * and overwrites data if the data does not fit into the buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Notes + * (1) If there is not enough space in the "Up"-buffer, data is overwritten. + * (2) For performance reasons this function does not call Init() + * and may only be called after RTT has been initialized. + * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. + * (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link + * connection reads RTT data. + */ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + const char *pData; + SEGGER_RTT_BUFFER_UP *pRing; + unsigned Avail; + volatile char *pDst; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pData = (const char *)pBuffer; + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) + { + Avail = pRing->SizeOfBuffer - 1u; + } + else if (pRing->WrOff < pRing->RdOff) + { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } + else + { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; } - } - // - // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds - // - Avail = pRing->SizeOfBuffer - pRing->WrOff; - do { - if (Avail > NumBytes) { - // - // Last round - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + if (NumBytes > Avail) + { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) + { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do + { + if (Avail > NumBytes) + { + // + // Last round + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - Avail = NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += Avail; + Avail = NumBytes; + while (NumBytes--) + { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff += Avail; #else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += NumBytes; + SEGGER_RTT_MEMCPY((void *)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff += NumBytes; #endif - break; - } else { - // - // Wrap-around necessary, write until wrap-around and reset WrOff - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + break; + } + else + { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; #if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytes -= Avail; - while (Avail--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; + NumBytes -= Avail; + while (Avail--) + { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff = 0; #else - SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail); - pData += Avail; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; - NumBytes -= Avail; + SEGGER_RTT_MEMCPY((void *)pDst, pData, Avail); + pData += Avail; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff = 0; + NumBytes -= Avail; #endif - Avail = (pRing->SizeOfBuffer - 1); - } - } while (NumBytes); + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); } /********************************************************************* -* -* SEGGER_RTT_WriteSkipNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteSkipNoLock does not lock the application and -* skips all data, if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* MUST be > 0!!! -* This is done for performance reasons, so no initial check has do be done. -* -* Return value -* 1: Data has been copied -* 0: No space, data has not been copied -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, all data is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ + * + * SEGGER_RTT_WriteSkipNoLock + * + * Function description + * Stores a specified number of characters in SEGGER RTT + * control block which is then read by the host. + * SEGGER_RTT_WriteSkipNoLock does not lock the application and + * skips all data, if the data does not fit into the buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * MUST be > 0!!! + * This is done for performance reasons, so no initial check has do be done. + * + * Return value + * 1: Data has been copied + * 0: No space, data has not been copied + * + * Notes + * (1) If there is not enough space in the "Up"-buffer, all data is dropped. + * (2) For performance reasons this function does not call Init() + * and may only be called after RTT has been initialized. + * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. + */ #if (RTT_USE_ASM == 0) -unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - unsigned RdOff; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - // - // Cases: - // 1) RdOff <= WrOff => Space until wrap-around is sufficient - // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) - // 3) RdOff < WrOff => No space in buf - // 4) RdOff > WrOff => Space is sufficient - // 5) RdOff > WrOff => No space in buf - // - // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - if (RdOff <= WrOff) { // Case 1), 2) or 3) - Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) - if (Avail >= NumBytes) { // Case 1)? -CopyStraight: - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - memcpy((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; - return 1; - } - Avail += RdOff; // Space incl. wrap-around - if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) - Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - memcpy((void*)pDst, pData, Rem); // Copy 1st chunk - NumBytes -= Rem; - // - // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used - // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element - // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks - // Therefore, check if 2nd memcpy is necessary at all - // - if (NumBytes) { - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - memcpy((void*)pDst, pData + Rem, NumBytes); - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes; - return 1; +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + const char *pData; + SEGGER_RTT_BUFFER_UP *pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + volatile char *pDst; + // + // Cases: + // 1) RdOff <= WrOff => Space until wrap-around is sufficient + // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) + // 3) RdOff < WrOff => No space in buf + // 4) RdOff > WrOff => Space is sufficient + // 5) RdOff > WrOff => No space in buf + // + // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough + // + pData = (const char *)pBuffer; + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) + { // Case 1), 2) or 3) + Avail = pRing->SizeOfBuffer - WrOff - + 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) + if (Avail >= NumBytes) + { // Case 1)? + CopyStraight: + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + memcpy((void *)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff = WrOff + NumBytes; + return 1; + } + Avail += RdOff; // Space incl. wrap-around + if (Avail >= NumBytes) + { // Case 2? => If not, we have case 3) (does not fit) + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + memcpy((void *)pDst, pData, Rem); // Copy 1st chunk + NumBytes -= Rem; + // + // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could + // not be used But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is + // not 0, so we can use the last element In this case, we may use a copy straight until buffer end anyway + // without needing to copy 2 chunks Therefore, check if 2nd memcpy is necessary at all + // + if (NumBytes) + { + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + memcpy((void *)pDst, pData + Rem, NumBytes); + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change + // the order of memory accesses + pRing->WrOff = NumBytes; + return 1; + } } - } else { // Potential case 4) - Avail = RdOff - WrOff - 1u; - if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) - goto CopyStraight; + else + { // Potential case 4) + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) + { // Case 4)? => If not, we have case 5) (does not fit) + goto CopyStraight; + } } - } - return 0; // No space in buffer + return 0; // No space in buffer } #endif /********************************************************************* -* -* SEGGER_RTT_WriteDownBufferNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block inside a buffer. -* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data from other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of "Down"-buffer to be used. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-target" ring buffer. - // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); + * + * SEGGER_RTT_WriteDownBufferNoLock + * + * Function description + * Stores a specified number of characters in SEGGER RTT + * control block inside a buffer. + * SEGGER_RTT_WriteDownBufferNoLock does not lock the application. + * Used to do the same operation that J-Link does, to transfer + * RTT data from other channels, such as TCP/IP or UART. + * + * Parameters + * BufferIndex Index of "Down"-buffer to be used. + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Return value + * Number of bytes which have been stored in the "Down"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + * (2) For performance reasons this function does not call Init() + * and may only be called after RTT has been initialized. + * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. + * + * Additional information + * This function must not be called when J-Link might also do RTT. + */ +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + unsigned Status; + unsigned Avail; + const char *pData; + SEGGER_RTT_BUFFER_UP *pRing; + // + // Get "to-target" ring buffer. + // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be + // modified by J-Link. + // + pData = (const char *)pBuffer; + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aDown[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) + { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) + { + Status = 0u; + } + else + { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; + // + // Finish up. + // + return Status; } /********************************************************************* -* -* SEGGER_RTT_WriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteNoLock does not lock the application. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-host" ring buffer. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); + * + * SEGGER_RTT_WriteNoLock + * + * Function description + * Stores a specified number of characters in SEGGER RTT + * control block which is then read by the host. + * SEGGER_RTT_WriteNoLock does not lock the application. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + * (2) For performance reasons this function does not call Init() + * and may only be called after RTT has been initialized. + * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. + */ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + unsigned Status; + unsigned Avail; + const char *pData; + SEGGER_RTT_BUFFER_UP *pRing; + // + // Get "to-host" ring buffer. + // + pData = (const char *)pBuffer; + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) + { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) + { + Status = 0u; + } + else + { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; + // + // Finish up. + // + return Status; } /********************************************************************* -* -* SEGGER_RTT_WriteDownBuffer -* -* Function description -* Stores a specified number of characters in SEGGER RTT control block in a buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the write operation, writing from the application is also locked. -* If only one consumer writes to the down buffer, -* call SEGGER_RTT_WriteDownBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; + * + * SEGGER_RTT_WriteDownBuffer + * + * Function description + * Stores a specified number of characters in SEGGER RTT control block in a buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Return value + * Number of bytes which have been stored in the "Down"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + * + * Additional information + * This function must not be called when J-Link might also do RTT. + * This function locks against all other RTT operations. I.e. during + * the write operation, writing from the application is also locked. + * If only one consumer writes to the down buffer, + * call SEGGER_RTT_WriteDownBufferNoLock() instead. + */ +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; } /********************************************************************* -* -* SEGGER_RTT_Write -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ -unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; + * + * SEGGER_RTT_Write + * + * Function description + * Stores a specified number of characters in SEGGER RTT + * control block which is then read by the host. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * pBuffer Pointer to character array. Does not need to point to a \0 terminated string. + * NumBytes Number of bytes to be stored in the SEGGER RTT control block. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + */ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes) +{ + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; } /********************************************************************* -* -* SEGGER_RTT_WriteString -* -* Function description -* Stores string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* s Pointer to string. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) String passed to this function has to be \0 terminated -* (3) \0 termination character is *not* stored in RTT buffer -*/ -unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { - unsigned Len; + * + * SEGGER_RTT_WriteString + * + * Function description + * Stores string in SEGGER RTT control block. + * This data is read by the host. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * s Pointer to string. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + * (2) String passed to this function has to be \0 terminated + * (3) \0 termination character is *not* stored in RTT buffer + */ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char *s) +{ + unsigned Len; - Len = STRLEN(s); - return SEGGER_RTT_Write(BufferIndex, s, Len); + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); } /********************************************************************* -* -* SEGGER_RTT_PutCharSkipNoLock -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* SEGGER_RTT_PutCharSkipNoLock does not lock the application and -* skips the byte, if it does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ + * + * SEGGER_RTT_PutCharSkipNoLock + * + * Function description + * Stores a single character/byte in SEGGER RTT buffer. + * SEGGER_RTT_PutCharSkipNoLock does not lock the application and + * skips the byte, if it does not fit into the buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * c Byte to be stored. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) If there is not enough space in the "Up"-buffer, the character is dropped. + * (2) For performance reasons this function does not call Init() + * and may only be called after RTT has been initialized. + * Either by calling SEGGER_RTT_Init() or calling another RTT API function first. + */ -unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - return Status; +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) +{ + SEGGER_RTT_BUFFER_UP *pRing; + unsigned WrOff; + unsigned Status; + volatile char *pDst; + // + // Get "to-host" ring buffer. + // + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) + { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) + { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } + else + { + Status = 0; + } + // + return Status; } /********************************************************************* -* -* SEGGER_RTT_PutCharSkip -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -*/ + * + * SEGGER_RTT_PutCharSkip + * + * Function description + * Stores a single character/byte in SEGGER RTT buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * c Byte to be stored. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) If there is not enough space in the "Up"-buffer, the character is dropped. + */ -unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return Status; +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) +{ + SEGGER_RTT_BUFFER_UP *pRing; + unsigned WrOff; + unsigned Status; + volatile char *pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) + { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) + { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } + else + { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; } - /********************************************************************* -* -* SEGGER_RTT_PutChar -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ +/********************************************************************* + * + * SEGGER_RTT_PutChar + * + * Function description + * Stores a single character/byte in SEGGER RTT buffer. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). + * c Byte to be stored. + * + * Return value + * Number of bytes which have been stored in the "Up"-buffer. + * + * Notes + * (1) Data is stored according to buffer flags. + */ -unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Wait for free space if mode is set to blocking - // - if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - while (WrOff == pRing->RdOff) { - ; +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) +{ + SEGGER_RTT_BUFFER_UP *pRing; + unsigned WrOff; + unsigned Status; + volatile char *pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) + { + WrOff = 0; } - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - return Status; + // + // Wait for free space if mode is set to blocking + // + if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) + { + while (WrOff == pRing->RdOff) + { + ; + } + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) + { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } + else + { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + return Status; } /********************************************************************* -* -* SEGGER_RTT_GetKey -* -* Function description -* Reads one character from the SEGGER RTT buffer. -* Host has previously stored data there. -* -* Return value -* < 0 - No character available (buffer empty). -* >= 0 - Character which has been read. (Possible values: 0 - 255) -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0. -*/ -int SEGGER_RTT_GetKey(void) { - char c; - int r; - - r = (int)SEGGER_RTT_Read(0u, &c, 1u); - if (r == 1) { - r = (int)(unsigned char)c; - } else { - r = -1; - } - return r; + * + * SEGGER_RTT_GetKey + * + * Function description + * Reads one character from the SEGGER RTT buffer. + * Host has previously stored data there. + * + * Return value + * < 0 - No character available (buffer empty). + * >= 0 - Character which has been read. (Possible values: 0 - 255) + * + * Notes + * (1) This function is only specified for accesses to RTT buffer 0. + */ +int SEGGER_RTT_GetKey(void) +{ + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) + { + r = (int)(unsigned char)c; + } + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_WaitKey -* -* Function description -* Waits until at least one character is avaible in the SEGGER RTT buffer. -* Once a character is available, it is read and this function returns. -* -* Return value -* >=0 - Character which has been read. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -* (2) This function is blocking if no character is present in RTT buffer -*/ -int SEGGER_RTT_WaitKey(void) { - int r; - - do { - r = SEGGER_RTT_GetKey(); - } while (r < 0); - return r; + * + * SEGGER_RTT_WaitKey + * + * Function description + * Waits until at least one character is avaible in the SEGGER RTT buffer. + * Once a character is available, it is read and this function returns. + * + * Return value + * >=0 - Character which has been read. + * + * Notes + * (1) This function is only specified for accesses to RTT buffer 0 + * (2) This function is blocking if no character is present in RTT buffer + */ +int SEGGER_RTT_WaitKey(void) +{ + int r; + + do + { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; } /********************************************************************* -* -* SEGGER_RTT_HasKey -* -* Function description -* Checks if at least one character for reading is available in the SEGGER RTT buffer. -* -* Return value -* == 0 - No characters are available to read. -* == 1 - At least one character is available. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -*/ -int SEGGER_RTT_HasKey(void) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned RdOff; - int r; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - if (RdOff != pRing->WrOff) { - r = 1; - } else { - r = 0; - } - return r; + * + * SEGGER_RTT_HasKey + * + * Function description + * Checks if at least one character for reading is available in the SEGGER RTT buffer. + * + * Return value + * == 0 - No characters are available to read. + * == 1 - At least one character is available. + * + * Notes + * (1) This function is only specified for accesses to RTT buffer 0 + */ +int SEGGER_RTT_HasKey(void) +{ + SEGGER_RTT_BUFFER_DOWN *pRing; + unsigned RdOff; + int r; + + INIT(); + pRing = + (SEGGER_RTT_BUFFER_DOWN *)((char *)&_SEGGER_RTT.aDown[0] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + if (RdOff != pRing->WrOff) + { + r = 1; + } + else + { + r = 0; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_HasData -* -* Function description -* Check if there is data from the host in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->WrOff; - return v - pRing->RdOff; + * + * SEGGER_RTT_HasData + * + * Function description + * Check if there is data from the host in the given buffer. + * + * Return value: + * ==0: No data + * !=0: Data in buffer + * + */ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) +{ + SEGGER_RTT_BUFFER_DOWN *pRing; + unsigned v; + + pRing = + (SEGGER_RTT_BUFFER_DOWN *)((char *)&_SEGGER_RTT.aDown[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + v = pRing->WrOff; + return v - pRing->RdOff; } /********************************************************************* -* -* SEGGER_RTT_HasDataUp -* -* Function description -* Check if there is data remaining to be sent in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->RdOff; - return pRing->WrOff - v; + * + * SEGGER_RTT_HasDataUp + * + * Function description + * Check if there is data remaining to be sent in the given buffer. + * + * Return value: + * ==0: No data + * !=0: Data in buffer + * + */ +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) +{ + SEGGER_RTT_BUFFER_UP *pRing; + unsigned v; + + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + v = pRing->RdOff; + return pRing->WrOff - v; } /********************************************************************* -* -* SEGGER_RTT_AllocDownBuffer -* -* Function description -* Run-time configuration of the next down-buffer (H->T). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) { - break; + * + * SEGGER_RTT_AllocDownBuffer + * + * Function description + * Run-time configuration of the next down-buffer (H->T). + * The next buffer, which is not used yet is configured. + * This includes: Buffer address, size, name, flags, ... + * + * Parameters + * sName Pointer to a constant name string. + * pBuffer Pointer to a buffer to be used. + * BufferSize Size of the buffer. + * Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). + * + * Return value + * >= 0 - O.K. Buffer Index + * < 0 - Error + */ +int SEGGER_RTT_AllocDownBuffer(const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags) +{ + int BufferIndex; + volatile SEGGER_RTT_CB *pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + BufferIndex = 0; + do + { + if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) + { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumDownBuffers); + if (BufferIndex < pRTTCB->MaxNumDownBuffers) + { + pRTTCB->aDown[BufferIndex].sName = sName; + pRTTCB->aDown[BufferIndex].pBuffer = (char *)pBuffer; + pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aDown[BufferIndex].RdOff = 0u; + pRTTCB->aDown[BufferIndex].WrOff = 0u; + pRTTCB->aDown[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumDownBuffers); - if (BufferIndex < pRTTCB->MaxNumDownBuffers) { - pRTTCB->aDown[BufferIndex].sName = sName; - pRTTCB->aDown[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aDown[BufferIndex].RdOff = 0u; - pRTTCB->aDown[BufferIndex].WrOff = 0u; - pRTTCB->aDown[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; + else + { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; } /********************************************************************* -* -* SEGGER_RTT_AllocUpBuffer -* -* Function description -* Run-time configuration of the next up-buffer (T->H). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) { - break; + * + * SEGGER_RTT_AllocUpBuffer + * + * Function description + * Run-time configuration of the next up-buffer (T->H). + * The next buffer, which is not used yet is configured. + * This includes: Buffer address, size, name, flags, ... + * + * Parameters + * sName Pointer to a constant name string. + * pBuffer Pointer to a buffer to be used. + * BufferSize Size of the buffer. + * Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). + * + * Return value + * >= 0 - O.K. Buffer Index + * < 0 - Error + */ +int SEGGER_RTT_AllocUpBuffer(const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags) +{ + int BufferIndex; + volatile SEGGER_RTT_CB *pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + BufferIndex = 0; + do + { + if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) + { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumUpBuffers); + if (BufferIndex < pRTTCB->MaxNumUpBuffers) + { + pRTTCB->aUp[BufferIndex].sName = sName; + pRTTCB->aUp[BufferIndex].pBuffer = (char *)pBuffer; + pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aUp[BufferIndex].RdOff = 0u; + pRTTCB->aUp[BufferIndex].WrOff = 0u; + pRTTCB->aUp[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumUpBuffers); - if (BufferIndex < pRTTCB->MaxNumUpBuffers) { - pRTTCB->aUp[BufferIndex].sName = sName; - pRTTCB->aUp[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aUp[BufferIndex].RdOff = 0u; - pRTTCB->aUp[BufferIndex].WrOff = 0u; - pRTTCB->aUp[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; + else + { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; } /********************************************************************* -* -* SEGGER_RTT_ConfigUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer (T->H). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 - O.K. -* < 0 - Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - if (BufferIndex) { - pUp->sName = sName; - pUp->pBuffer = (char*)pBuffer; - pUp->SizeOfBuffer = BufferSize; - pUp->RdOff = 0u; - pUp->WrOff = 0u; + * + * SEGGER_RTT_ConfigUpBuffer + * + * Function description + * Run-time configuration of a specific up-buffer (T->H). + * Buffer to be configured is specified by index. + * This includes: Buffer address, size, name, flags, ... + * + * Parameters + * BufferIndex Index of the buffer to configure. + * sName Pointer to a constant name string. + * pBuffer Pointer to a buffer to be used. + * BufferSize Size of the buffer. + * Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). + * + * Return value + * >= 0 - O.K. + * < 0 - Error + * + * Additional information + * Buffer 0 is configured on compile-time. + * May only be called once per buffer. + * Buffer name and flags can be reconfigured using the appropriate functions. + */ +int SEGGER_RTT_ConfigUpBuffer( + unsigned BufferIndex, const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_UP *pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) + { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + if (BufferIndex) + { + pUp->sName = sName; + pUp->pBuffer = (char *)pBuffer; + pUp->SizeOfBuffer = BufferSize; + pUp->RdOff = 0u; + pUp->WrOff = 0u; + } + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; } - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_ConfigDownBuffer -* -* Function description -* Run-time configuration of a specific down-buffer (H->T). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* -* Return value -* >= 0 O.K. -* < 0 Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - if (BufferIndex) { - pDown->sName = sName; - pDown->pBuffer = (char*)pBuffer; - pDown->SizeOfBuffer = BufferSize; - pDown->RdOff = 0u; - pDown->WrOff = 0u; + * + * SEGGER_RTT_ConfigDownBuffer + * + * Function description + * Run-time configuration of a specific down-buffer (H->T). + * Buffer to be configured is specified by index. + * This includes: Buffer address, size, name, flags, ... + * + * Parameters + * BufferIndex Index of the buffer to configure. + * sName Pointer to a constant name string. + * pBuffer Pointer to a buffer to be used. + * BufferSize Size of the buffer. + * Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). + * + * Return value + * >= 0 O.K. + * < 0 Error + * + * Additional information + * Buffer 0 is configured on compile-time. + * May only be called once per buffer. + * Buffer name and flags can be reconfigured using the appropriate functions. + */ +int SEGGER_RTT_ConfigDownBuffer( + unsigned BufferIndex, const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN *pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) + { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + if (BufferIndex) + { + pDown->sName = sName; + pDown->pBuffer = (char *)pBuffer; + pDown->SizeOfBuffer = BufferSize; + pDown->RdOff = 0u; + pDown->WrOff = 0u; + } + pDown->Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the + // order of memory accesses + SEGGER_RTT_UNLOCK(); + r = 0; } - pDown->Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_SetNameUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + * + * SEGGER_RTT_SetNameUpBuffer + * + * Function description + * Run-time configuration of a specific up-buffer name (T->H). + * Buffer to be configured is specified by index. + * + * Parameters + * BufferIndex Index of the buffer to renamed. + * sName Pointer to a constant name string. + * + * Return value + * >= 0 O.K. + * < 0 Error + */ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char *sName) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_UP *pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) + { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_SetNameDownBuffer -* -* Function description -* Run-time configuration of a specific Down-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + * + * SEGGER_RTT_SetNameDownBuffer + * + * Function description + * Run-time configuration of a specific Down-buffer name (T->H). + * Buffer to be configured is specified by index. + * + * Parameters + * BufferIndex Index of the buffer to renamed. + * sName Pointer to a constant name string. + * + * Return value + * >= 0 O.K. + * < 0 Error + */ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char *sName) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN *pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) + { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_SetFlagsUpBuffer -* -* Function description -* Run-time configuration of specific up-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer. -* Flags Flags to set for the buffer. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + * + * SEGGER_RTT_SetFlagsUpBuffer + * + * Function description + * Run-time configuration of specific up-buffer flags (T->H). + * Buffer to be configured is specified by index. + * + * Parameters + * BufferIndex Index of the buffer. + * Flags Flags to set for the buffer. + * + * Return value + * >= 0 O.K. + * < 0 Error + */ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_UP *pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) + { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_SetFlagsDownBuffer -* -* Function description -* Run-time configuration of specific Down-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* Flags Flags to set for the buffer. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; + * + * SEGGER_RTT_SetFlagsDownBuffer + * + * Function description + * Run-time configuration of specific Down-buffer flags (T->H). + * Buffer to be configured is specified by index. + * + * Parameters + * BufferIndex Index of the buffer to renamed. + * Flags Flags to set for the buffer. + * + * Return value + * >= 0 O.K. + * < 0 Error + */ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) +{ + int r; + volatile SEGGER_RTT_CB *pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN *pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) + { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } + else + { + r = -1; + } + return r; } /********************************************************************* -* -* SEGGER_RTT_Init -* -* Function description -* Initializes the RTT Control Block. -* Should be used in RAM targets, at start of the application. -* -*/ -void SEGGER_RTT_Init (void) { - _DoInit(); + * + * SEGGER_RTT_Init + * + * Function description + * Initializes the RTT Control Block. + * Should be used in RAM targets, at start of the application. + * + */ +void SEGGER_RTT_Init(void) +{ + _DoInit(); } /********************************************************************* -* -* SEGGER_RTT_SetTerminal -* -* Function description -* Sets the terminal to be used for output on channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* -* Return value -* >= 0 O.K. -* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) -* -* Notes -* (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { - unsigned char ac[2]; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - int r; - - INIT(); - r = 0; - ac[0] = 0xFFu; - if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels - ac[1] = _aTerminalId[TerminalId]; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing - if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - _ActiveTerminal = TerminalId; - _WriteBlocking(pRing, (const char*)ac, 2u); - } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes - Avail = _GetAvailWriteSpace(pRing); - if (Avail >= 2) { - _ActiveTerminal = TerminalId; // Only change active terminal in case of success - _WriteNoCheck(pRing, (const char*)ac, 2u); - } else { + * + * SEGGER_RTT_SetTerminal + * + * Function description + * Sets the terminal to be used for output on channel 0. + * + * Parameters + * TerminalId Index of the terminal. + * + * Return value + * >= 0 O.K. + * < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new + * terminal Id) + * + * Notes + * (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed + */ +int SEGGER_RTT_SetTerminal(unsigned char TerminalId) +{ + unsigned char ac[2]; + SEGGER_RTT_BUFFER_UP *pRing; + unsigned Avail; + int r; + + INIT(); + r = 0; + ac[0] = 0xFFu; + if (TerminalId < sizeof(_aTerminalId)) + { // We only support a certain number of channels + ac[1] = _aTerminalId[TerminalId]; + pRing = (SEGGER_RTT_BUFFER_UP + *)((char *)&_SEGGER_RTT.aUp[0] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side + // and all of our changes go into HW directly + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of + // free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) + { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, (const char *)ac, 2u); + } + else + { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) + { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, (const char *)ac, 2u); + } + else + { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } + else + { r = -1; - } } - SEGGER_RTT_UNLOCK(); - } else { - r = -1; - } - return r; + return r; } /********************************************************************* -* -* SEGGER_RTT_TerminalOut -* -* Function description -* Writes a string to the given terminal -* without changing the terminal for channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* s String to be printed on the terminal. -* -* Return value -* >= 0 - Number of bytes written. -* < 0 - Error. -* -*/ -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { - int Status; - unsigned FragLen; - unsigned Avail; - SEGGER_RTT_BUFFER_UP* pRing; - // - INIT(); - // - // Validate terminal ID. - // - if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + * + * SEGGER_RTT_TerminalOut + * + * Function description + * Writes a string to the given terminal + * without changing the terminal for channel 0. + * + * Parameters + * TerminalId Index of the terminal. + * s String to be printed on the terminal. + * + * Return value + * >= 0 - Number of bytes written. + * < 0 - Error. + * + */ +int SEGGER_RTT_TerminalOut(unsigned char TerminalId, const char *s) +{ + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP *pRing; // - // Need to be able to change terminal, write data, change back. - // Compute the fixed and variable sizes. + INIT(); // - FragLen = STRLEN(s); + // Validate terminal ID. // - // How we output depends upon the mode... - // - SEGGER_RTT_LOCK(); - Avail = _GetAvailWriteSpace(pRing); - switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother switching terminals at all. - // - if (Avail < (FragLen + 4u)) { - Status = 0; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode and there is not enough space for everything, - // trim the output but always include the terminal switch. If no room - // for terminal switch, skip that totally. - // - if (Avail < 4u) { + if (TerminalId < (char)sizeof(_aTerminalId)) + { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP + *)((char *)&_SEGGER_RTT.aUp[0] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side + // and all of our changes go into HW directly + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = STRLEN(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) + { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) + { + Status = 0; + } + else + { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) + { + Status = -1; + } + else + { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } + else + { Status = -1; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - break; - default: - Status = -1; - break; } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - } else { - Status = -1; - } - return Status; + return Status; } /********************************************************************* -* -* SEGGER_RTT_GetAvailWriteSpace -* -* Function description -* Returns the number of bytes available in the ring buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are free in the selected up buffer. -*/ -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - return _GetAvailWriteSpace(pRing); + * + * SEGGER_RTT_GetAvailWriteSpace + * + * Function description + * Returns the number of bytes available in the ring buffer. + * + * Parameters + * BufferIndex Index of the up buffer. + * + * Return value + * Number of bytes that are free in the selected up buffer. + */ +unsigned SEGGER_RTT_GetAvailWriteSpace(unsigned BufferIndex) +{ + SEGGER_RTT_BUFFER_UP *pRing; + + pRing = + (SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[BufferIndex] + + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the + // J-Link side and all of our changes go into HW directly + return _GetAvailWriteSpace(pRing); } - /********************************************************************* -* -* SEGGER_RTT_GetBytesInBuffer() -* -* Function description -* Returns the number of bytes currently used in the up buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are used in the buffer. -*/ -unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - volatile SEGGER_RTT_CB* pRTTCB; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRTTCB->aUp[BufferIndex].RdOff; - WrOff = pRTTCB->aUp[BufferIndex].WrOff; - if (RdOff <= WrOff) { - r = WrOff - RdOff; - } else { - r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); - } - return r; + * + * SEGGER_RTT_GetBytesInBuffer() + * + * Function description + * Returns the number of bytes currently used in the up buffer. + * + * Parameters + * BufferIndex Index of the up buffer. + * + * Return value + * Number of bytes that are used in the buffer. + */ +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) +{ + unsigned RdOff; + unsigned WrOff; + unsigned r; + volatile SEGGER_RTT_CB *pRTTCB; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + pRTTCB = (volatile SEGGER_RTT_CB + *)((unsigned char *)&_SEGGER_RTT + + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link + // side and all of our changes go into HW directly + RdOff = pRTTCB->aUp[BufferIndex].RdOff; + WrOff = pRTTCB->aUp[BufferIndex].WrOff; + if (RdOff <= WrOff) + { + r = WrOff - RdOff; + } + else + { + r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); + } + return r; } /*************************** End of file ****************************/ diff --git a/components/rtt/RTT/SEGGER_RTT.h b/components/rtt/RTT/SEGGER_RTT.h index a4ea70b35..678e16900 100644 --- a/components/rtt/RTT/SEGGER_RTT.h +++ b/components/rtt/RTT/SEGGER_RTT.h @@ -49,7 +49,7 @@ ---------------------------END-OF-HEADER------------------------------ File : SEGGER_RTT.h Purpose : Implementation of SEGGER real-time transfer which allows - real-time communication on targets which support debugger + real-time communication on targets which support debugger memory accesses while the CPU is running. Revision: $Rev: 20869 $ ---------------------------------------------------------------------- @@ -61,99 +61,99 @@ Revision: $Rev: 20869 $ #include "SEGGER_RTT_Conf.h" /********************************************************************* -* -* Defines, defaults -* -********************************************************************** -*/ + * + * Defines, defaults + * + ********************************************************************** + */ #ifndef RTT_USE_ASM - #if (defined __SES_ARM) // SEGGER Embedded Studio - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __CROSSWORKS_ARM) // Rowley Crossworks - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARMCC_VERSION) // ARM compiler - #if (__ARMCC_VERSION >= 6000000) // ARM compiler V6.0 and later is clang based - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #else - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif (defined __GNUC__) // GCC - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __clang__) // Clang compiler - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #else - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #endif - #if ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler - // - // IAR assembler / compiler - // - #if (__VER__ < 6300000) - #define VOLATILE - #else - #define VOLATILE volatile - #endif - #if (defined __ARM7M__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #endif - #endif - #if (defined __ARM7EM__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_BASELINE__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_MAINLINE__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #else - // - // GCC / Clang - // - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #endif - // - // If IDE and core support the ASM version, enable ASM version by default - // - #ifndef _CORE_HAS_RTT_ASM_SUPPORT - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores - #endif - #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) - #define RTT_USE_ASM (1) - #else - #define RTT_USE_ASM (0) - #endif +#if (defined __SES_ARM) // SEGGER Embedded Studio +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __CROSSWORKS_ARM) // Rowley Crossworks +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __ARMCC_VERSION) // ARM compiler +#if (__ARMCC_VERSION >= 6000000) // ARM compiler V6.0 and later is clang based +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#else +#define _CC_HAS_RTT_ASM_SUPPORT 0 +#endif +#elif (defined __GNUC__) // GCC +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __clang__) // Clang compiler +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#else +#define _CC_HAS_RTT_ASM_SUPPORT 0 +#endif +#if ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler +// +// IAR assembler / compiler +// +#if (__VER__ < 6300000) +#define VOLATILE +#else +#define VOLATILE volatile +#endif +#if (defined __ARM7M__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM7M__) // Cortex-M3 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#endif +#endif +#if (defined __ARM7EM__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm VOLATILE("DMB"); +#endif +#endif +#if (defined __ARM8M_BASELINE__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 +#define _CORE_HAS_RTT_ASM_SUPPORT 0 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm VOLATILE("DMB"); +#endif +#endif +#if (defined __ARM8M_MAINLINE__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm VOLATILE("DMB"); +#endif +#endif +#else +// +// GCC / Clang +// +#if (defined __ARM_ARCH_7M__) // Cortex-M3 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 +#define _CORE_HAS_RTT_ASM_SUPPORT 0 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#else +#define _CORE_HAS_RTT_ASM_SUPPORT 0 +#endif +#endif +// +// If IDE and core support the ASM version, enable ASM version by default +// +#ifndef _CORE_HAS_RTT_ASM_SUPPORT +#define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores +#endif +#if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) +#define RTT_USE_ASM (1) +#else +#define RTT_USE_ASM (0) +#endif #endif // @@ -162,44 +162,45 @@ Revision: $Rev: 20869 $ // Needed for: Cortex-M7, Cortex-M23, Cortex-M33 // #ifndef _CORE_NEEDS_DMB - #define _CORE_NEEDS_DMB 0 +#define _CORE_NEEDS_DMB 0 #endif #ifndef RTT__DMB - #if _CORE_NEEDS_DMB - #error "Don't know how to place inline assembly for DMB" - #else - #define RTT__DMB() - #endif +#if _CORE_NEEDS_DMB +#error "Don't know how to place inline assembly for DMB" +#else +#define RTT__DMB() +#endif #endif #ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE - #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here +#define SEGGER_RTT_CPU_CACHE_LINE_SIZE \ + (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here #endif #ifndef SEGGER_RTT_UNCACHED_OFF - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #else - #define SEGGER_RTT_UNCACHED_OFF (0) - #endif +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE +#error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#else +#define SEGGER_RTT_UNCACHED_OFF (0) +#endif #endif #if RTT_USE_ASM - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE +#error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" +#endif #endif -#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file +#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file #include #include /********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ + * + * Defines, fixed + * + ********************************************************************** + */ // // Determine how much we must pad the control block to make it a multiple of a cache line in size @@ -208,45 +209,55 @@ Revision: $Rev: 20869 $ // U32 = 4B // U8/U16/U32* = 4B // -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache +#define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) \ + (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * \ + SEGGER_RTT_CPU_CACHE_LINE_SIZE) #else - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) +#define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) #endif -#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) -#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) +#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) +#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) /********************************************************************* -* -* Types -* -********************************************************************** -*/ + * + * Types + * + ********************************************************************** + */ // // Description for a circular buffer (also called "ring buffer") // which is used as up-buffer (T->H) // -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - unsigned WrOff; // Position of next item to be written by either target. - volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. - unsigned Flags; // Contains configuration flags +typedef struct +{ + const char *sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char *pBuffer; // Pointer to start of buffer + unsigned + SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the + // buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned + RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags } SEGGER_RTT_BUFFER_UP; // // Description for a circular buffer (also called "ring buffer") // which is used as down-buffer (H->T) // -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. - unsigned RdOff; // Position of next item to be read by target (down-buffer). - unsigned Flags; // Contains configuration flags +typedef struct +{ + const char *sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char *pBuffer; // Pointer to start of buffer + unsigned + SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the + // buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned + WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags } SEGGER_RTT_BUFFER_DOWN; // @@ -254,165 +265,175 @@ typedef struct { // as well as the configuration for each buffer // // -typedef struct { - char acID[16]; // Initialized to "SEGGER RTT" - int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) - int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) - SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host - SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +typedef struct +{ + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via + // debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from + // host via debug probe to target #if SEGGER_RTT__CB_PADDING - unsigned char aDummy[SEGGER_RTT__CB_PADDING]; + unsigned char aDummy[SEGGER_RTT__CB_PADDING]; #endif } SEGGER_RTT_CB; /********************************************************************* -* -* Global data -* -********************************************************************** -*/ + * + * Global data + * + ********************************************************************** + */ extern SEGGER_RTT_CB _SEGGER_RTT; /********************************************************************* -* -* RTT API functions -* -********************************************************************** -*/ + * + * RTT API functions + * + ********************************************************************** + */ #ifdef __cplusplus - extern "C" { +extern "C" { #endif -int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_GetKey (void); -unsigned SEGGER_RTT_HasData (unsigned BufferIndex); -int SEGGER_RTT_HasKey (void); -unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); -void SEGGER_RTT_Init (void); -unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_WaitKey (void); -unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); -unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); +int SEGGER_RTT_AllocDownBuffer(const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer(const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer( + unsigned BufferIndex, const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer( + unsigned BufferIndex, const char *sName, void *pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey(void); +unsigned SEGGER_RTT_HasData(unsigned BufferIndex); +int SEGGER_RTT_HasKey(void); +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex); +void SEGGER_RTT_Init(void); +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void *pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void *pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char *sName); +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char *sName); +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey(void); +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_ASM_WriteSkipNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char *s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_GetAvailWriteSpace(unsigned BufferIndex); +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex); // // Function macro for performance optimization // -#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) +#define SEGGER_RTT_HASDATA(n) \ + (((SEGGER_RTT_BUFFER_DOWN *)((char *)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - \ + ((SEGGER_RTT_BUFFER_DOWN *)((char *)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) #if RTT_USE_ASM - #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock +#define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock #endif /********************************************************************* -* -* RTT transfer functions to send RTT data via other channels. -* -********************************************************************** -*/ -unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); - -#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + * + * RTT transfer functions to send RTT data via other channels. + * + ********************************************************************** + */ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void *pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void *pData, unsigned BufferSize); +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void *pBuffer, unsigned NumBytes); + +#define SEGGER_RTT_HASDATA_UP(n) \ + (((SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - \ + ((SEGGER_RTT_BUFFER_UP *)((char *)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF)) \ + ->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into + // HW directly /********************************************************************* -* -* RTT "Terminal" API functions -* -********************************************************************** -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId); -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); + * + * RTT "Terminal" API functions + * + ********************************************************************** + */ +int SEGGER_RTT_SetTerminal(unsigned char TerminalId); +int SEGGER_RTT_TerminalOut(unsigned char TerminalId, const char *s); /********************************************************************* -* -* RTT printf functions (require SEGGER_RTT_printf.c) -* -********************************************************************** -*/ -int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); -int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + * + * RTT printf functions (require SEGGER_RTT_printf.c) + * + ********************************************************************** + */ +int SEGGER_RTT_printf(unsigned BufferIndex, const char *sFormat, ...); +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char *sFormat, va_list *pParamList); #ifdef __cplusplus - } +} #endif #endif // ifndef(SEGGER_RTT_ASM) /********************************************************************* -* -* Defines -* -********************************************************************** -*/ + * + * Defines + * + ********************************************************************** + */ // // Operating modes. Define behavior if buffer is full (not enough space for entire message) // -#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) -#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. -#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. -#define SEGGER_RTT_MODE_MASK (3) +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3) // // Control sequences, based on ANSI. // Can be used to control color, and clear the screen // -#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors -#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left - -#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" -#define RTT_CTRL_TEXT_RED "\x1B[2;31m" -#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" -#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" -#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" -#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" -#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" -#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" - -#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" -#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" -#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" -#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" -#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" -#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" -#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" -#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" - -#define RTT_CTRL_BG_BLACK "\x1B[24;40m" -#define RTT_CTRL_BG_RED "\x1B[24;41m" -#define RTT_CTRL_BG_GREEN "\x1B[24;42m" -#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" -#define RTT_CTRL_BG_BLUE "\x1B[24;44m" -#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" -#define RTT_CTRL_BG_CYAN "\x1B[24;46m" -#define RTT_CTRL_BG_WHITE "\x1B[24;47m" - -#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" -#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" -#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" -#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" -#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" -#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" -#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" -#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" - +#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" +#define RTT_CTRL_TEXT_RED "\x1B[2;31m" +#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" +#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" +#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" +#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" + +#define RTT_CTRL_BG_BLACK "\x1B[24;40m" +#define RTT_CTRL_BG_RED "\x1B[24;41m" +#define RTT_CTRL_BG_GREEN "\x1B[24;42m" +#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" +#define RTT_CTRL_BG_BLUE "\x1B[24;44m" +#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" +#define RTT_CTRL_BG_CYAN "\x1B[24;46m" +#define RTT_CTRL_BG_WHITE "\x1B[24;47m" + +#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" #endif diff --git a/components/rtt/RTT/SEGGER_RTT_printf.c b/components/rtt/RTT/SEGGER_RTT_printf.c index af4846fee..2e341f57a 100644 --- a/components/rtt/RTT/SEGGER_RTT_printf.c +++ b/components/rtt/RTT/SEGGER_RTT_printf.c @@ -56,450 +56,548 @@ Revision: $Rev: 17697 $ #include "SEGGER_RTT_Conf.h" /********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ + * + * Defines, configurable + * + ********************************************************************** + */ #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE - #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64) +#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64) #endif #include #include - -#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) -#define FORMAT_FLAG_PAD_ZERO (1u << 1) -#define FORMAT_FLAG_PRINT_SIGN (1u << 2) -#define FORMAT_FLAG_ALTERNATE (1u << 3) +#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) +#define FORMAT_FLAG_PAD_ZERO (1u << 1) +#define FORMAT_FLAG_PRINT_SIGN (1u << 2) +#define FORMAT_FLAG_ALTERNATE (1u << 3) /********************************************************************* -* -* Types -* -********************************************************************** -*/ + * + * Types + * + ********************************************************************** + */ -typedef struct { - char* pBuffer; - unsigned BufferSize; - unsigned Cnt; +typedef struct +{ + char *pBuffer; + unsigned BufferSize; + unsigned Cnt; - int ReturnValue; + int ReturnValue; - unsigned RTTBufferIndex; + unsigned RTTBufferIndex; } SEGGER_RTT_PRINTF_DESC; /********************************************************************* -* -* Function prototypes -* -********************************************************************** -*/ + * + * Function prototypes + * + ********************************************************************** + */ /********************************************************************* -* -* Static code -* -********************************************************************** -*/ + * + * Static code + * + ********************************************************************** + */ /********************************************************************* -* -* _StoreChar -*/ -static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) { - unsigned Cnt; + * + * _StoreChar + */ +static void _StoreChar(SEGGER_RTT_PRINTF_DESC *p, char c) +{ + unsigned Cnt; - Cnt = p->Cnt; - if ((Cnt + 1u) <= p->BufferSize) { - *(p->pBuffer + Cnt) = c; - p->Cnt = Cnt + 1u; - p->ReturnValue++; - } - // - // Write part of string, when the buffer is full - // - if (p->Cnt == p->BufferSize) { - if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) { - p->ReturnValue = -1; - } else { - p->Cnt = 0u; + Cnt = p->Cnt; + if ((Cnt + 1u) <= p->BufferSize) + { + *(p->pBuffer + Cnt) = c; + p->Cnt = Cnt + 1u; + p->ReturnValue++; + } + // + // Write part of string, when the buffer is full + // + if (p->Cnt == p->BufferSize) + { + if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) + { + p->ReturnValue = -1; + } + else + { + p->Cnt = 0u; + } } - } } /********************************************************************* -* -* _PrintUnsigned -*/ -static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { - static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; - unsigned Div; - unsigned Digit; - unsigned Number; - unsigned Width; - char c; + * + * _PrintUnsigned + */ +static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC *pBufferDesc, + unsigned v, + unsigned Base, + unsigned NumDigits, + unsigned FieldWidth, + unsigned FormatFlags) +{ + static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + unsigned Div; + unsigned Digit; + unsigned Number; + unsigned Width; + char c; - Number = v; - Digit = 1u; - // - // Get actual field width - // - Width = 1u; - while (Number >= Base) { - Number = (Number / Base); - Width++; - } - if (NumDigits > Width) { - Width = NumDigits; - } - // - // Print leading chars if necessary - // - if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) { - if (FieldWidth != 0u) { - if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) { - c = '0'; - } else { - c = ' '; - } - while ((FieldWidth != 0u) && (Width < FieldWidth)) { - FieldWidth--; - _StoreChar(pBufferDesc, c); - if (pBufferDesc->ReturnValue < 0) { - break; - } - } - } - } - if (pBufferDesc->ReturnValue >= 0) { + Number = v; + Digit = 1u; // - // Compute Digit. - // Loop until Digit has the value of the highest digit required. - // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + // Get actual field width // - while (1) { - if (NumDigits > 1u) { // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned) - NumDigits--; - } else { - Div = v / Digit; - if (Div < Base) { // Is our divider big enough to extract the highest digit from value? => Done - break; - } - } - Digit *= Base; + Width = 1u; + while (Number >= Base) + { + Number = (Number / Base); + Width++; + } + if (NumDigits > Width) + { + Width = NumDigits; } // - // Output digits - // - do { - Div = v / Digit; - v -= Div * Digit; - _StoreChar(pBufferDesc, _aV2C[Div]); - if (pBufferDesc->ReturnValue < 0) { - break; - } - Digit /= Base; - } while (Digit); - // - // Print trailing spaces if necessary + // Print leading chars if necessary // - if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) { - if (FieldWidth != 0u) { - while ((FieldWidth != 0u) && (Width < FieldWidth)) { - FieldWidth--; - _StoreChar(pBufferDesc, ' '); - if (pBufferDesc->ReturnValue < 0) { - break; - } + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) + { + if (FieldWidth != 0u) + { + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) + { + c = '0'; + } + else + { + c = ' '; + } + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + _StoreChar(pBufferDesc, c); + if (pBufferDesc->ReturnValue < 0) + { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) + { + // + // Compute Digit. + // Loop until Digit has the value of the highest digit required. + // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + // + while (1) + { + if (NumDigits > 1u) + { // User specified a min number of digits to print? => Make sure we loop at least that often, before + // checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned) + NumDigits--; + } + else + { + Div = v / Digit; + if (Div < Base) + { // Is our divider big enough to extract the highest digit from value? => Done + break; + } + } + Digit *= Base; + } + // + // Output digits + // + do + { + Div = v / Digit; + v -= Div * Digit; + _StoreChar(pBufferDesc, _aV2C[Div]); + if (pBufferDesc->ReturnValue < 0) + { + break; + } + Digit /= Base; + } while (Digit); + // + // Print trailing spaces if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) + { + break; + } + } + } } - } } - } } /********************************************************************* -* -* _PrintInt -*/ -static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { - unsigned Width; - int Number; - - Number = (v < 0) ? -v : v; + * + * _PrintInt + */ +static void _PrintInt(SEGGER_RTT_PRINTF_DESC *pBufferDesc, + int v, + unsigned Base, + unsigned NumDigits, + unsigned FieldWidth, + unsigned FormatFlags) +{ + unsigned Width; + int Number; - // - // Get actual field width - // - Width = 1u; - while (Number >= (int)Base) { - Number = (Number / (int)Base); - Width++; - } - if (NumDigits > Width) { - Width = NumDigits; - } - if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) { - FieldWidth--; - } + Number = (v < 0) ? -v : v; - // - // Print leading spaces if necessary - // - if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) { - if (FieldWidth != 0u) { - while ((FieldWidth != 0u) && (Width < FieldWidth)) { + // + // Get actual field width + // + Width = 1u; + while (Number >= (int)Base) + { + Number = (Number / (int)Base); + Width++; + } + if (NumDigits > Width) + { + Width = NumDigits; + } + if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) + { FieldWidth--; - _StoreChar(pBufferDesc, ' '); - if (pBufferDesc->ReturnValue < 0) { - break; - } - } } - } - // - // Print sign if necessary - // - if (pBufferDesc->ReturnValue >= 0) { - if (v < 0) { - v = -v; - _StoreChar(pBufferDesc, '-'); - } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) { - _StoreChar(pBufferDesc, '+'); - } else { + // + // Print leading spaces if necessary + // + if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && + ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) + { + break; + } + } + } } - if (pBufferDesc->ReturnValue >= 0) { - // - // Print leading zeros if necessary - // - if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) { - if (FieldWidth != 0u) { - while ((FieldWidth != 0u) && (Width < FieldWidth)) { - FieldWidth--; - _StoreChar(pBufferDesc, '0'); - if (pBufferDesc->ReturnValue < 0) { - break; + // + // Print sign if necessary + // + if (pBufferDesc->ReturnValue >= 0) + { + if (v < 0) + { + v = -v; + _StoreChar(pBufferDesc, '-'); + } + else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) + { + _StoreChar(pBufferDesc, '+'); + } + else + { + } + if (pBufferDesc->ReturnValue >= 0) + { + // + // Print leading zeros if necessary + // + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && + ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + _StoreChar(pBufferDesc, '0'); + if (pBufferDesc->ReturnValue < 0) + { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) + { + // + // Print number without sign + // + _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); } - } } - } - if (pBufferDesc->ReturnValue >= 0) { - // - // Print number without sign - // - _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); - } } - } } /********************************************************************* -* -* Public code -* -********************************************************************** -*/ + * + * Public code + * + ********************************************************************** + */ /********************************************************************* -* -* SEGGER_RTT_vprintf -* -* Function description -* Stores a formatted string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") -* sFormat Pointer to format string -* pParamList Pointer to the list of arguments for the format string -* -* Return values -* >= 0: Number of bytes which have been stored in the "Up"-buffer. -* < 0: Error -*/ -int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) { - char c; - SEGGER_RTT_PRINTF_DESC BufferDesc; - int v; - unsigned NumDigits; - unsigned FormatFlags; - unsigned FieldWidth; - char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE]; + * + * SEGGER_RTT_vprintf + * + * Function description + * Stores a formatted string in SEGGER RTT control block. + * This data is read by the host. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") + * sFormat Pointer to format string + * pParamList Pointer to the list of arguments for the format string + * + * Return values + * >= 0: Number of bytes which have been stored in the "Up"-buffer. + * < 0: Error + */ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char *sFormat, va_list *pParamList) +{ + char c; + SEGGER_RTT_PRINTF_DESC BufferDesc; + int v; + unsigned NumDigits; + unsigned FormatFlags; + unsigned FieldWidth; + char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE]; - BufferDesc.pBuffer = acBuffer; - BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE; - BufferDesc.Cnt = 0u; - BufferDesc.RTTBufferIndex = BufferIndex; - BufferDesc.ReturnValue = 0; + BufferDesc.pBuffer = acBuffer; + BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE; + BufferDesc.Cnt = 0u; + BufferDesc.RTTBufferIndex = BufferIndex; + BufferDesc.ReturnValue = 0; - do { - c = *sFormat; - sFormat++; - if (c == 0u) { - break; - } - if (c == '%') { - // - // Filter out flags - // - FormatFlags = 0u; - v = 1; - do { - c = *sFormat; - switch (c) { - case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break; - case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO; sFormat++; break; - case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN; sFormat++; break; - case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE; sFormat++; break; - default: v = 0; break; - } - } while (v); - // - // filter out field with - // - FieldWidth = 0u; - do { + do + { c = *sFormat; - if ((c < '0') || (c > '9')) { - break; - } - sFormat++; - FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0'); - } while (1); - - // - // Filter out precision (number of digits to display) - // - NumDigits = 0u; - c = *sFormat; - if (c == '.') { sFormat++; - do { - c = *sFormat; - if ((c < '0') || (c > '9')) { + if (c == 0u) + { break; - } - sFormat++; - NumDigits = NumDigits * 10u + ((unsigned)c - '0'); - } while (1); - } - // - // Filter out length modifier - // - c = *sFormat; - do { - if ((c == 'l') || (c == 'h')) { - sFormat++; - c = *sFormat; - } else { - break; } - } while (1); - // - // Handle specifiers - // - switch (c) { - case 'c': { - char c0; - v = va_arg(*pParamList, int); - c0 = (char)v; - _StoreChar(&BufferDesc, c0); - break; - } - case 'd': - v = va_arg(*pParamList, int); - _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags); - break; - case 'u': - v = va_arg(*pParamList, int); - _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags); - break; - case 'x': - case 'X': - v = va_arg(*pParamList, int); - _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags); - break; - case 's': + if (c == '%') { - const char * s = va_arg(*pParamList, const char *); - do { - c = *s; - s++; - if (c == '\0') { - break; + // + // Filter out flags + // + FormatFlags = 0u; + v = 1; + do + { + c = *sFormat; + switch (c) + { + case '-': + FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; + sFormat++; + break; + case '0': + FormatFlags |= FORMAT_FLAG_PAD_ZERO; + sFormat++; + break; + case '+': + FormatFlags |= FORMAT_FLAG_PRINT_SIGN; + sFormat++; + break; + case '#': + FormatFlags |= FORMAT_FLAG_ALTERNATE; + sFormat++; + break; + default: + v = 0; + break; + } + } while (v); + // + // filter out field with + // + FieldWidth = 0u; + do + { + c = *sFormat; + if ((c < '0') || (c > '9')) + { + break; + } + sFormat++; + FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0'); + } while (1); + + // + // Filter out precision (number of digits to display) + // + NumDigits = 0u; + c = *sFormat; + if (c == '.') + { + sFormat++; + do + { + c = *sFormat; + if ((c < '0') || (c > '9')) + { + break; + } + sFormat++; + NumDigits = NumDigits * 10u + ((unsigned)c - '0'); + } while (1); } - _StoreChar(&BufferDesc, c); - } while (BufferDesc.ReturnValue >= 0); + // + // Filter out length modifier + // + c = *sFormat; + do + { + if ((c == 'l') || (c == 'h')) + { + sFormat++; + c = *sFormat; + } + else + { + break; + } + } while (1); + // + // Handle specifiers + // + switch (c) + { + case 'c': + { + char c0; + v = va_arg(*pParamList, int); + c0 = (char)v; + _StoreChar(&BufferDesc, c0); + break; + } + case 'd': + v = va_arg(*pParamList, int); + _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'u': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'x': + case 'X': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags); + break; + case 's': + { + const char *s = va_arg(*pParamList, const char *); + do + { + c = *s; + s++; + if (c == '\0') + { + break; + } + _StoreChar(&BufferDesc, c); + } while (BufferDesc.ReturnValue >= 0); + } + break; + case 'p': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u); + break; + case '%': + _StoreChar(&BufferDesc, '%'); + break; + default: + break; + } + sFormat++; } - break; - case 'p': - v = va_arg(*pParamList, int); - _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u); - break; - case '%': - _StoreChar(&BufferDesc, '%'); - break; - default: - break; - } - sFormat++; - } else { - _StoreChar(&BufferDesc, c); - } - } while (BufferDesc.ReturnValue >= 0); + else + { + _StoreChar(&BufferDesc, c); + } + } while (BufferDesc.ReturnValue >= 0); - if (BufferDesc.ReturnValue > 0) { - // - // Write remaining data, if any - // - if (BufferDesc.Cnt != 0u) { - SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt); + if (BufferDesc.ReturnValue > 0) + { + // + // Write remaining data, if any + // + if (BufferDesc.Cnt != 0u) + { + SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt); + } + BufferDesc.ReturnValue += (int)BufferDesc.Cnt; } - BufferDesc.ReturnValue += (int)BufferDesc.Cnt; - } - return BufferDesc.ReturnValue; + return BufferDesc.ReturnValue; } /********************************************************************* -* -* SEGGER_RTT_printf -* -* Function description -* Stores a formatted string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") -* sFormat Pointer to format string, followed by the arguments for conversion -* -* Return values -* >= 0: Number of bytes which have been stored in the "Up"-buffer. -* < 0: Error -* -* Notes -* (1) Conversion specifications have following syntax: -* %[flags][FieldWidth][.Precision]ConversionSpecifier -* (2) Supported flags: -* -: Left justify within the field width -* +: Always print sign extension for signed conversions -* 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision -* Supported conversion specifiers: -* c: Print the argument as one char -* d: Print the argument as a signed integer -* u: Print the argument as an unsigned integer -* x: Print the argument as an hexadecimal integer -* s: Print the string pointed to by the argument -* p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.) -*/ -int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) { - int r; - va_list ParamList; + * + * SEGGER_RTT_printf + * + * Function description + * Stores a formatted string in SEGGER RTT control block. + * This data is read by the host. + * + * Parameters + * BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") + * sFormat Pointer to format string, followed by the arguments for conversion + * + * Return values + * >= 0: Number of bytes which have been stored in the "Up"-buffer. + * < 0: Error + * + * Notes + * (1) Conversion specifications have following syntax: + * %[flags][FieldWidth][.Precision]ConversionSpecifier + * (2) Supported flags: + * -: Left justify within the field width + * +: Always print sign extension for signed conversions + * 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision + * Supported conversion specifiers: + * c: Print the argument as one char + * d: Print the argument as a signed integer + * u: Print the argument as an unsigned integer + * x: Print the argument as an hexadecimal integer + * s: Print the string pointed to by the argument + * p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.) + */ +int SEGGER_RTT_printf(unsigned BufferIndex, const char *sFormat, ...) +{ + int r; + va_list ParamList; - va_start(ParamList, sFormat); - r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList); - va_end(ParamList); - return r; + va_start(ParamList, sFormat); + r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList); + va_end(ParamList); + return r; } /*************************** End of file ****************************/ diff --git a/components/rtt/Syscalls/SEGGER_RTT_Syscalls_GCC.c b/components/rtt/Syscalls/SEGGER_RTT_Syscalls_GCC.c index 9f2e49752..12f56234b 100644 --- a/components/rtt/Syscalls/SEGGER_RTT_Syscalls_GCC.c +++ b/components/rtt/Syscalls/SEGGER_RTT_Syscalls_GCC.c @@ -49,7 +49,7 @@ ---------------------------END-OF-HEADER------------------------------ File : SEGGER_RTT_Syscalls_GCC.c Purpose : Low-level functions for using printf() via RTT in GCC. - To use RTT for printf output, include this file in your + To use RTT for printf output, include this file in your application. Revision: $Rev: 20755 $ ---------------------------------------------------------------------- @@ -62,18 +62,18 @@ Revision: $Rev: 20755 $ * printf, scanf are redirected to RTT. */ #if defined(SDK_DEBUGCONSOLE_UART) -#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) && !(defined __ARMCC_VERSION) && !(defined __CC_ARM) +#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) && !(defined __ARMCC_VERSION) && \ + !(defined __CC_ARM) -#include // required for _write_r +#include // required for _write_r #include "SEGGER_RTT.h" - /********************************************************************* -* -* Types -* -********************************************************************** -*/ + * + * Types + * + ********************************************************************** + */ // // If necessary define the _reent struct // to match the one passed by the used standard library. @@ -81,70 +81,72 @@ Revision: $Rev: 20755 $ struct _reent; /********************************************************************* -* -* Function prototypes -* -********************************************************************** -*/ -_ssize_t _write (int file, const void *ptr, size_t len); + * + * Function prototypes + * + ********************************************************************** + */ +_ssize_t _write(int file, const void *ptr, size_t len); _ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len); /********************************************************************* -* -* Global functions -* -********************************************************************** -*/ + * + * Global functions + * + ********************************************************************** + */ /********************************************************************* -* -* _write() -* -* Function description -* Low-level write function. -* libc subroutines will use this system routine for output to all files, -* including stdout. -* Write data via RTT. -*/ -_ssize_t _write(int file, const void *ptr, size_t len) { - (void) file; /* Not used, avoid warning */ - SEGGER_RTT_Write(0, ptr, len); - return len; + * + * _write() + * + * Function description + * Low-level write function. + * libc subroutines will use this system routine for output to all files, + * including stdout. + * Write data via RTT. + */ +_ssize_t _write(int file, const void *ptr, size_t len) +{ + (void)file; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; } /********************************************************************* -* -* _write_r() -* -* Function description -* Low-level reentrant write function. -* libc subroutines will use this system routine for output to all files, -* including stdout. -* Write data via RTT. -*/ -_ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len) { - (void) file; /* Not used, avoid warning */ - (void) r; /* Not used, avoid warning */ - SEGGER_RTT_Write(0, ptr, len); - return len; + * + * _write_r() + * + * Function description + * Low-level reentrant write function. + * libc subroutines will use this system routine for output to all files, + * including stdout. + * Write data via RTT. + */ +_ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len) +{ + (void)file; /* Not used, avoid warning */ + (void)r; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; } /********************************************************************* -* -* _read() -* -* Function description -* Low-level read function. -* Standard library subroutines will use this system routine -* for reading data via RTT. -*/ + * + * _read() + * + * Function description + * Low-level read function. + * Standard library subroutines will use this system routine + * for reading data via RTT. + */ _ssize_t _read(int handle, char *buffer, int size) { - (void) handle; /* Not used, avoid warning */ + (void)handle; /* Not used, avoid warning */ for (int i = 0; i < bufSize; i++) { - *buf = SEGGER_RTT_WaitKey() ; + *buf = SEGGER_RTT_WaitKey(); buf++; } @@ -152,12 +154,12 @@ _ssize_t _read(int handle, char *buffer, int size) } /********************************************************************* -* -* __sys_write() -* -* Function description -* Low-level write function used by REDLIB. -*/ + * + * __sys_write() + * + * Function description + * Low-level write function used by REDLIB. + */ int __sys_write(int handle, char *buffer, int size) { if (NULL == buffer) @@ -173,23 +175,23 @@ int __sys_write(int handle, char *buffer, int size) } /* Send data. */ - SEGGER_RTT_Write(0, (const char*)buffer, size); + SEGGER_RTT_Write(0, (const char *)buffer, size); return 0; } /********************************************************************* -* -* _read() -* -* Function description -* Low-level read function, used by REDLIB. -* Standard library subroutines will use this system routine -* for reading data via RTT. -*/ + * + * _read() + * + * Function description + * Low-level read function, used by REDLIB. + * Standard library subroutines will use this system routine + * for reading data via RTT. + */ int __sys_readc(void) { - return SEGGER_RTT_WaitKey() ; + return SEGGER_RTT_WaitKey(); } #endif diff --git a/components/rtt/Syscalls/SEGGER_RTT_Syscalls_SES.c b/components/rtt/Syscalls/SEGGER_RTT_Syscalls_SES.c index 599c68e1f..934316862 100644 --- a/components/rtt/Syscalls/SEGGER_RTT_Syscalls_SES.c +++ b/components/rtt/Syscalls/SEGGER_RTT_Syscalls_SES.c @@ -65,11 +65,11 @@ Revision: $Rev: 18539 $ #include "__vfprintf.h" /********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ + * + * Defines, configurable + * + ********************************************************************** + */ // // Select string formatting implementation. // @@ -85,8 +85,8 @@ Revision: $Rev: 18539 $ // #define PRINTF_USE_SEGGER_RTT_FORMATTING 0 // Use standard library formatting // #define PRINTF_USE_SEGGER_RTT_FORMATTING 1 // Use RTT formatting // -#ifndef PRINTF_USE_SEGGER_RTT_FORMATTING - #define PRINTF_USE_SEGGER_RTT_FORMATTING 0 +#ifndef PRINTF_USE_SEGGER_RTT_FORMATTING +#define PRINTF_USE_SEGGER_RTT_FORMATTING 0 #endif // // If using standard library formatting, @@ -95,157 +95,167 @@ Revision: $Rev: 18539 $ // #define PRINTF_BUFFER_SIZE 0 // Use character-wise output // #define PRINTF_BUFFER_SIZE 128 // Default maximum string length // -#ifndef PRINTF_BUFFER_SIZE - #define PRINTF_BUFFER_SIZE 128 +#ifndef PRINTF_BUFFER_SIZE +#define PRINTF_BUFFER_SIZE 128 #endif -#if PRINTF_USE_SEGGER_RTT_FORMATTING // Use SEGGER RTT formatting implementation +#if PRINTF_USE_SEGGER_RTT_FORMATTING // Use SEGGER RTT formatting implementation /********************************************************************* -* -* Function prototypes -* -********************************************************************** -*/ -int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + * + * Function prototypes + * + ********************************************************************** + */ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char *sFormat, va_list *pParamList); /********************************************************************* -* -* Global functions, printf -* -********************************************************************** -*/ + * + * Global functions, printf + * + ********************************************************************** + */ /********************************************************************* -* -* printf() -* -* Function description -* print a formatted string using RTT and SEGGER RTT formatting. -*/ -int printf(const char *fmt,...) { - int n; - va_list args; - - va_start (args, fmt); - n = SEGGER_RTT_vprintf(0, fmt, &args); - va_end(args); - return n; + * + * printf() + * + * Function description + * print a formatted string using RTT and SEGGER RTT formatting. + */ +int printf(const char *fmt, ...) +{ + int n; + va_list args; + + va_start(args, fmt); + n = SEGGER_RTT_vprintf(0, fmt, &args); + va_end(args); + return n; } #elif PRINTF_BUFFER_SIZE == 0 // Use standard library formatting with character-wise output /********************************************************************* -* -* Static functions -* -********************************************************************** -*/ -static int _putchar(int x, __printf_tag_ptr ctx) { - (void)ctx; - SEGGER_RTT_Write(0, (char *)&x, 1); - return x; + * + * Static functions + * + ********************************************************************** + */ +static int _putchar(int x, __printf_tag_ptr ctx) +{ + (void)ctx; + SEGGER_RTT_Write(0, (char *)&x, 1); + return x; } /********************************************************************* -* -* Global functions, printf -* -********************************************************************** -*/ + * + * Global functions, printf + * + ********************************************************************** + */ /********************************************************************* -* -* printf() -* -* Function description -* print a formatted string character-wise, using RTT and standard -* library formatting. -*/ -int printf(const char *fmt, ...) { - int n; - va_list args; - __printf_t iod; - - va_start(args, fmt); - iod.string = 0; - iod.maxchars = INT_MAX; - iod.output_fn = _putchar; - SEGGER_RTT_LOCK(); - n = __vfprintf(&iod, fmt, args); - SEGGER_RTT_UNLOCK(); - va_end(args); - return n; + * + * printf() + * + * Function description + * print a formatted string character-wise, using RTT and standard + * library formatting. + */ +int printf(const char *fmt, ...) +{ + int n; + va_list args; + __printf_t iod; + + va_start(args, fmt); + iod.string = 0; + iod.maxchars = INT_MAX; + iod.output_fn = _putchar; + SEGGER_RTT_LOCK(); + n = __vfprintf(&iod, fmt, args); + SEGGER_RTT_UNLOCK(); + va_end(args); + return n; } -#else // Use standard library formatting with static buffer +#else // Use standard library formatting with static buffer /********************************************************************* -* -* Global functions, printf -* -********************************************************************** -*/ + * + * Global functions, printf + * + ********************************************************************** + */ /********************************************************************* -* -* printf() -* -* Function description -* print a formatted string using RTT and standard library formatting. -*/ -int printf(const char *fmt,...) { - int n; - char aBuffer[PRINTF_BUFFER_SIZE]; - va_list args; - - va_start (args, fmt); - n = vsnprintf(aBuffer, sizeof(aBuffer), fmt, args); - if (n > (int)sizeof(aBuffer)) { - SEGGER_RTT_Write(0, aBuffer, sizeof(aBuffer)); - } else if (n > 0) { - SEGGER_RTT_Write(0, aBuffer, n); - } - va_end(args); - return n; + * + * printf() + * + * Function description + * print a formatted string using RTT and standard library formatting. + */ +int printf(const char *fmt, ...) +{ + int n; + char aBuffer[PRINTF_BUFFER_SIZE]; + va_list args; + + va_start(args, fmt); + n = vsnprintf(aBuffer, sizeof(aBuffer), fmt, args); + if (n > (int)sizeof(aBuffer)) + { + SEGGER_RTT_Write(0, aBuffer, sizeof(aBuffer)); + } + else if (n > 0) + { + SEGGER_RTT_Write(0, aBuffer, n); + } + va_end(args); + return n; } #endif /********************************************************************* -* -* Global functions -* -********************************************************************** -*/ + * + * Global functions + * + ********************************************************************** + */ /********************************************************************* -* -* puts() -* -* Function description -* print a string using RTT. -*/ -int puts(const char *s) { - return SEGGER_RTT_WriteString(0, s); + * + * puts() + * + * Function description + * print a string using RTT. + */ +int puts(const char *s) +{ + return SEGGER_RTT_WriteString(0, s); } /********************************************************************* -* -* __putchar() -* -* Function description -* Write one character via RTT. -*/ -int __putchar(int x, __printf_tag_ptr ctx) { - (void)ctx; - SEGGER_RTT_Write(0, (char *)&x, 1); - return x; + * + * __putchar() + * + * Function description + * Write one character via RTT. + */ +int __putchar(int x, __printf_tag_ptr ctx) +{ + (void)ctx; + SEGGER_RTT_Write(0, (char *)&x, 1); + return x; } /********************************************************************* -* -* __getchar() -* -* Function description -* Wait for and get a character via RTT. -*/ -int __getchar() { - return SEGGER_RTT_WaitKey(); + * + * __getchar() + * + * Function description + * Wait for and get a character via RTT. + */ +int __getchar() +{ + return SEGGER_RTT_WaitKey(); } #endif diff --git a/components/rtt/template/SEGGER_RTT_Conf.h b/components/rtt/template/SEGGER_RTT_Conf.h index 75a37c6e4..866271675 100644 --- a/components/rtt/template/SEGGER_RTT_Conf.h +++ b/components/rtt/template/SEGGER_RTT_Conf.h @@ -59,370 +59,395 @@ Revision: $Rev: 21386 $ #define SEGGER_RTT_CONF_H #ifdef __IAR_SYSTEMS_ICC__ - #include +#include #endif /********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ + * + * Defines, configurable + * + ********************************************************************** + */ // // Take in and set to correct values for Cortex-A systems with CPU cache // -//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system -//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current +// system #define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can +// be accessed uncached // // Most common case: // Up-channel 0: RTT // Up-channel 1: SystemView // -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) #endif // // Most common case: // Down-channel 0: RTT // Down-channel 1: SystemView // -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) #endif -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#ifndef BUFFER_SIZE_UP +#define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) #endif -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#ifndef BUFFER_SIZE_DOWN +#define BUFFER_SIZE_DOWN \ + (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) #endif -#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE - #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE +#define SEGGER_RTT_PRINTF_BUFFER_SIZE \ + (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) #endif -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#ifndef SEGGER_RTT_MODE_DEFAULT +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) #endif /********************************************************************* -* -* RTT memcpy configuration -* -* memcpy() is good for large amounts of data, -* but the overhead is big for small amounts, which are usually stored via RTT. -* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. -* -* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. -* This is may be required with memory access restrictions, -* such as on Cortex-A devices with MMU. -*/ -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop + * + * RTT memcpy configuration + * + * memcpy() is good for large amounts of data, + * but the overhead is big for small amounts, which are usually stored via RTT. + * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. + * + * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. + * This is may be required with memory access restrictions, + * such as on Cortex-A devices with MMU. + */ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP +#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop #endif // // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets // -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) -//#endif +// #endif // // Target is not allowed to perform other RTT operations while string still has not been stored completely. // Otherwise we would probably end up with a mixed string in the buffer. -// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and +// SEGGER_RTT_UNLOCK() function here. // // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. -// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. -// (Higher priority = lower priority number) -// Default value for embOS: 128u -// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC -// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to +// be adjusted accordingly. (Higher priority = lower priority number) Default value for embOS: 128u Default +// configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 +// - configPRIO_BITS) ) In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are +// implemented in NVIC or define SEGGER_RTT_LOCK() to completely disable interrupts. // -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY \ + (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) #endif /********************************************************************* -* -* RTT lock configuration for SEGGER Embedded Studio, -* Rowley CrossStudio and GCC -*/ -#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) - #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, primask \n\t" \ - "movs r1, #1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - - #elif defined(__ARM_ARCH_7A__) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #elif defined(__riscv) || defined(__riscv_xlen) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("csrr %0, mstatus \n\t" \ - "csrci mstatus, 8 \n\t" \ - "andi %0, %0, 8 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ - "or %0, %0, a1 \n\t" \ - "csrs mstatus, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "a1" \ - ); \ - } - #else - #define SEGGER_RTT_LOCK() - #define SEGGER_RTT_UNLOCK() - #endif + * + * RTT lock configuration for SEGGER Embedded Studio, + * Rowley CrossStudio and GCC + */ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || \ + defined(__clang__)) && \ + !defined(__CC_ARM) && !defined(WIN32)) +#if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile( \ + "mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r"(_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc"); + +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("msr primask, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ + } +#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#endif +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile( \ + "mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r"(_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc"); + +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("msr basepri, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ + } + +#elif defined(__ARM_ARCH_7A__) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile( \ + "mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r"(_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc"); + +#define SEGGER_RTT_UNLOCK() \ + __asm volatile( \ + "mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r"(_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc"); \ + } +#elif defined(__riscv) || defined(__riscv_xlen) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile( \ + "csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r"(_SEGGER_RTT__LockState) \ + : \ + :); + +#define SEGGER_RTT_UNLOCK() \ + __asm volatile( \ + "csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r"(_SEGGER_RTT__LockState) \ + : "a1"); \ + } +#else +#define SEGGER_RTT_LOCK() +#define SEGGER_RTT_UNLOCK() +#endif #endif /********************************************************************* -* -* RTT lock configuration for IAR EWARM -*/ + * + * RTT lock configuration for IAR EWARM + */ #ifdef __ICCARM__ - #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ - (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ - (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_BASEPRI(); \ - __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ - (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #endif +#if (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + +#define SEGGER_RTT_UNLOCK() \ + __set_PRIMASK(_SEGGER_RTT__LockState); \ + } +#elif (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#endif +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + +#define SEGGER_RTT_UNLOCK() \ + __set_BASEPRI(_SEGGER_RTT__LockState); \ + } +#elif (defined(__ARM7A__) && (__CORE__ == __ARM7A__)) || (defined(__ARM7R__) && (__CORE__ == __ARM7R__)) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile( \ + "mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r"(_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc"); + +#define SEGGER_RTT_UNLOCK() \ + __asm volatile( \ + "mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r"(_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc"); \ + } +#endif #endif /********************************************************************* -* -* RTT lock configuration for IAR RX -*/ + * + * RTT lock configuration for IAR RX + */ #ifdef __ICCRX__ - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } +#define SEGGER_RTT_LOCK() \ + { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + +#define SEGGER_RTT_UNLOCK() \ + __set_interrupt_state(_SEGGER_RTT__LockState); \ + } #endif /********************************************************************* -* -* RTT lock configuration for IAR RL78 -*/ + * + * RTT lock configuration for IAR RL78 + */ #ifdef __ICCRL78__ - #define SEGGER_RTT_LOCK() { \ - __istate_t _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } +#define SEGGER_RTT_LOCK() \ + { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + +#define SEGGER_RTT_UNLOCK() \ + __set_interrupt_state(_SEGGER_RTT__LockState); \ + } #endif /********************************************************************* -* -* RTT lock configuration for KEIL ARM -*/ + * + * RTT lock configuration for KEIL ARM + */ #ifdef __CC_ARM - #if (defined __TARGET_ARCH_6S_M) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ - _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ - _SEGGER_RTT__PRIMASK = 1u; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char BASEPRI __asm( "basepri"); \ - _SEGGER_RTT__LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #endif +#if (defined __TARGET_ARCH_6S_M) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm("primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + +#define SEGGER_RTT_UNLOCK() \ + _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } +#elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#endif +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm("basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + +#define SEGGER_RTT_UNLOCK() \ + BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } +#endif #endif /********************************************************************* -* -* RTT lock configuration for TI ARM -*/ + * + * RTT lock configuration for TI ARM + */ #ifdef __TI_ARM__ - #if defined (__TI_ARM_V6M0__) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ - } - #endif +#if defined(__TI_ARM_V6M0__) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + +#define SEGGER_RTT_UNLOCK() \ + __set_PRIMASK(_SEGGER_RTT__LockState); \ + } +#elif (defined(__TI_ARM_V7M3__) || defined(__TI_ARM_V7M4__)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#endif +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + +#define SEGGER_RTT_UNLOCK() \ + _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } +#endif #endif /********************************************************************* -* -* RTT lock configuration for CCRX -*/ + * + * RTT lock configuration for CCRX + */ #ifdef __RX - #include - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = get_psw() & 0x010000; \ - clrpsw_i(); - - #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ - } +#include +#define SEGGER_RTT_LOCK() \ + { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + +#define SEGGER_RTT_UNLOCK() \ + set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } #endif /********************************************************************* -* -* RTT lock configuration for embOS Simulation on Windows -* (Can also be used for generic RTT locking with embOS) -*/ + * + * RTT lock configuration for embOS Simulation on Windows + * (Can also be used for generic RTT locking with embOS) + */ #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) void OS_SIM_EnterCriticalSection(void); void OS_SIM_LeaveCriticalSection(void); -#define SEGGER_RTT_LOCK() { \ - OS_SIM_EnterCriticalSection(); +#define SEGGER_RTT_LOCK() \ + { \ + OS_SIM_EnterCriticalSection(); -#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ - } +#define SEGGER_RTT_UNLOCK() \ + OS_SIM_LeaveCriticalSection(); \ + } #endif /********************************************************************* -* -* RTT lock configuration fallback -*/ -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) + * + * RTT lock configuration fallback + */ +#ifndef SEGGER_RTT_LOCK +#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) #endif -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#ifndef SEGGER_RTT_UNLOCK +#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) #endif #endif diff --git a/components/serial_manager/fsl_component_serial_manager.c b/components/serial_manager/fsl_component_serial_manager.c index 7056f1fe8..d1570d9a0 100644 --- a/components/serial_manager/fsl_component_serial_manager.c +++ b/components/serial_manager/fsl_component_serial_manager.c @@ -22,11 +22,11 @@ * */ #if defined(OSA_USED) - +#include "fsl_os_abstraction.h" #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #include "fsl_component_common_task.h" #else -#include "fsl_os_abstraction.h" + #endif #endif @@ -285,69 +285,69 @@ static int32_t SerialManager_ReleaseLpConstraint(int32_t power_mode) #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle) +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle) { serial_manager_status_t status = kStatus_SerialManager_Error; serial_manager_write_handle_t *writeHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); if (writeHandle != NULL) { (void)SerialManager_SetLpConstraint(gSerialManagerLpConstraint_c); - switch (handle->serialPortType) + switch (serHandle->serialPortType) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) case kSerialPort_UartDma: - status = Serial_UartDmaWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_UartDmaWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) case kSerialPort_UsbCdc: - status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) case kSerialPort_Swo: - status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) case kSerialPort_Virtual: - status = Serial_PortVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) case kSerialPort_Rpmsg: - status = Serial_RpmsgWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) case kSerialPort_SpiMaster: - status = Serial_SpiMasterWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) case kSerialPort_SpiSlave: - status = Serial_SpiSlaveWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + status = Serial_SpiSlaveWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) case kSerialPort_BleWu: - status = Serial_PortBleWuWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - writeHandle->transfer.buffer, writeHandle->transfer.length); + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); break; #endif @@ -355,11 +355,15 @@ static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_ status = kStatus_SerialManager_Error; break; } + if (kStatus_SerialManager_Success != status) + { + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } } return status; } -static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, serial_manager_read_handle_t *readHandle, uint8_t *buffer, uint32_t length) @@ -369,48 +373,48 @@ static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_ if (NULL != readHandle) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - if (kSerialPort_Uart == handle->serialPortType) /* Serial port UART */ + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ { - status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - if (handle->serialPortType == kSerialPort_UsbCdc) + if (serHandle->serialPortType == kSerialPort_UsbCdc) { - status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) - if (handle->serialPortType == kSerialPort_Virtual) + if (serHandle->serialPortType == kSerialPort_Virtual) { - status = Serial_PortVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) - if (handle->serialPortType == kSerialPort_SpiMaster) + if (serHandle->serialPortType == kSerialPort_SpiMaster) { - status = Serial_SpiMasterRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) - if (handle->serialPortType == kSerialPort_SpiSlave) + if (serHandle->serialPortType == kSerialPort_SpiSlave) { - status = Serial_SpiSlaveRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SpiSlaveRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #if 0 #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) - if (handle->serialPortType == kSerialPort_Rpmsg) + if (serHandle->serialPortType == kSerialPort_Rpmsg) { - status = Serial_RpmsgRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) - if (handle->serialPortType == kSerialPort_BleWu) + if (serHandle->serialPortType == kSerialPort_BleWu) { - status = Serial_PortBleWuRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } #endif } @@ -419,7 +423,7 @@ static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_ #else /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ -static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle, +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle, serial_manager_write_handle_t *writeHandle, uint8_t *buffer, uint32_t length) @@ -427,51 +431,51 @@ static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_ serial_manager_status_t status = kStatus_SerialManager_Error; #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - if (kSerialPort_Uart == handle->serialPortType) /* Serial port UART */ + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ { - status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - if (kSerialPort_UsbCdc == handle->serialPortType) /* Serial port UsbCdc */ + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ { - status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - if (kSerialPort_Swo == handle->serialPortType) /* Serial port SWO */ + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ { - status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) - if (kSerialPort_Virtual == handle->serialPortType) /* Serial port UsbCdcVirtual */ + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ { - status = Serial_PortVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) - if (kSerialPort_Rpmsg == handle->serialPortType) /* Serial port Rpmsg */ + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port Rpmsg */ { - status = Serial_RpmsgWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) - if (kSerialPort_SpiMaster == handle->serialPortType) /* Serial port Spi Master */ + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ { - status = Serial_SpiMasterWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) - if (kSerialPort_BleWu == handle->serialPortType) /* Serial port BLE WU */ + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ { - status = Serial_PortBleWuWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif @@ -481,7 +485,7 @@ static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_ return status; } -static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, serial_manager_read_handle_t *readHandle, uint8_t *buffer, uint32_t length) @@ -489,51 +493,51 @@ static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_ serial_manager_status_t status = kStatus_SerialManager_Error; #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - if (kSerialPort_Uart == handle->serialPortType) /* Serial port UART */ + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ { - status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - if (kSerialPort_UsbCdc == handle->serialPortType) /* Serial port UsbCdc */ + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ { - status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - if (kSerialPort_Swo == handle->serialPortType) /* Serial port SWO */ + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ { - status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SwoRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) - if (kSerialPort_Virtual == handle->serialPortType) /* Serial port UsbCdcVirtual */ + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ { - status = Serial_PortVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) - if (kSerialPort_Rpmsg == handle->serialPortType) /* Serial port UsbCdcVirtual */ + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ { - status = Serial_RpmsgRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) - if (kSerialPort_SpiMaster == handle->serialPortType) /* Serial port Spi Master */ + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ { - status = Serial_SpiMasterRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) - if (kSerialPort_BleWu == handle->serialPortType) /* Serial port BLE WU */ + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ { - status = Serial_PortBleWuRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); } else #endif @@ -545,39 +549,39 @@ static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_ #endif /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static void SerialManager_IsrFunction(serial_manager_handle_t *handle) +static void SerialManager_IsrFunction(serial_manager_handle_t *serHandle) { uint32_t regPrimask = DisableGlobalIRQ(); - switch (handle->serialPortType) + switch (serHandle->serialPortType) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) case kSerialPort_UartDma: - Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) case kSerialPort_UsbCdc: - Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_UsbCdcIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) case kSerialPort_Swo: - Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_SwoIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) case kSerialPort_Virtual: - Serial_PortVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_PortVirtualIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) case kSerialPort_BleWu: - Serial_PortBleWuIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + Serial_PortBleWuIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif default: @@ -589,7 +593,7 @@ static void SerialManager_IsrFunction(serial_manager_handle_t *handle) static void SerialManager_Task(void *param) { - serial_manager_handle_t *handle = (serial_manager_handle_t *)param; + serial_manager_handle_t *serHandle = (serial_manager_handle_t *)param; serial_manager_write_handle_t *serialWriteHandle; serial_manager_read_handle_t *serialReadHandle; uint32_t primask; @@ -598,7 +602,7 @@ static void SerialManager_Task(void *param) uint32_t ringBufferLength; #endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ - if (NULL != handle) + if (NULL != serHandle) { #if defined(OSA_USED) @@ -607,7 +611,8 @@ static void SerialManager_Task(void *param) do { - if (KOSA_StatusSuccess == OSA_SemaphoreWait((osa_semaphore_handle_t)handle->serSemaphore, osaWaitForever_c)) + if (KOSA_StatusSuccess == + OSA_SemaphoreWait((osa_semaphore_handle_t)serHandle->serSemaphore, osaWaitForever_c)) { #endif #endif @@ -615,19 +620,19 @@ static void SerialManager_Task(void *param) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else - primask = DisableGlobalIRQ(); - uint8_t *ev = handle->serialManagerState; + primask = DisableGlobalIRQ(); + uint8_t *ev = serHandle->serialManagerState; EnableGlobalIRQ(primask); if (0U != (ev[SERIAL_EVENT_DATA_START_SEND])) #endif #endif { - (void)SerialManager_StartWriting(handle); + (void)SerialManager_StartWriting(serHandle); #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--; + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--; EnableGlobalIRQ(primask); #endif #endif @@ -642,12 +647,12 @@ static void SerialManager_Task(void *param) #endif { serialWriteHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); while (NULL != serialWriteHandle) { - SerialManager_RemoveHead(&handle->completedWriteHandleHead); - serialMsg.buffer = serialWriteHandle->transfer.buffer; - serialMsg.length = serialWriteHandle->transfer.soFar; + SerialManager_RemoveHead(&serHandle->completedWriteHandleHead); + serialMsg.buffer = serialWriteHandle->transfer.buffer; + serialMsg.length = serialWriteHandle->transfer.soFar; serialWriteHandle->transfer.buffer = NULL; if (NULL != serialWriteHandle->callback) { @@ -655,14 +660,14 @@ static void SerialManager_Task(void *param) serialWriteHandle->transfer.status); } serialWriteHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); } #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_SENT]--; + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]--; EnableGlobalIRQ(primask); #endif #endif @@ -677,7 +682,7 @@ static void SerialManager_Task(void *param) #endif { primask = DisableGlobalIRQ(); - serialReadHandle = handle->openedReadHandleHead; + serialReadHandle = serHandle->openedReadHandleHead; EnableGlobalIRQ(primask); if (NULL != serialReadHandle) @@ -686,8 +691,8 @@ static void SerialManager_Task(void *param) { if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) { - serialMsg.buffer = serialReadHandle->transfer.buffer; - serialMsg.length = serialReadHandle->transfer.soFar; + serialMsg.buffer = serialReadHandle->transfer.buffer; + serialMsg.length = serialReadHandle->transfer.soFar; serialReadHandle->transfer.buffer = NULL; if (NULL != serialReadHandle->callback) { @@ -701,7 +706,7 @@ static void SerialManager_Task(void *param) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]--; + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]--; EnableGlobalIRQ(primask); #endif #endif @@ -714,19 +719,19 @@ static void SerialManager_Task(void *param) #endif { primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] = 0; + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] = 0; ringBufferLength = - handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; EnableGlobalIRQ(primask); /* Notify there are data in ringbuffer */ if (0U != ringBufferLength) { serialMsg.buffer = NULL; serialMsg.length = ringBufferLength; - if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) { - handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, &serialMsg, + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, &serialMsg, kStatus_SerialManager_Notify); } } @@ -751,7 +756,7 @@ static void SerialManager_TxCallback(void *callbackParam, serial_manager_callback_message_t *message, serial_manager_status_t status) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_write_handle_t *writeHandle; #if (defined(OSA_USED)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) @@ -763,48 +768,51 @@ static void SerialManager_TxCallback(void *callbackParam, assert(NULL != callbackParam); assert(NULL != message); - handle = (serial_manager_handle_t *)callbackParam; + serHandle = (serial_manager_handle_t *)callbackParam; - writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); if (NULL != writeHandle) { - SerialManager_RemoveHead(&handle->runningWriteHandleHead); + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); #if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) /* Need to support common_task. */ -#else /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; EnableGlobalIRQ(primask); - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); #endif /* SERIAL_MANAGER_USE_COMMON_TASK */ #else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ - (void)SerialManager_StartWriting(handle); + if (kSerialManager_TransmissionBlocking == writeHandle->transfer.mode) + { + (void)SerialManager_StartWriting(serHandle); + } #endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ writeHandle->transfer.soFar = message->length; writeHandle->transfer.status = status; if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) { - SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle); + SerialManager_AddTail(&serHandle->completedWriteHandleHead, writeHandle); #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - handle->commontaskMsg.callback = SerialManager_Task; - handle->commontaskMsg.callbackParam = handle; - COMMON_TASK_post_message(&handle->commontaskMsg); + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); #else primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; EnableGlobalIRQ(primask); - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); #endif #else - SerialManager_Task(handle); + SerialManager_Task(serHandle); #endif } else @@ -822,7 +830,7 @@ void SerialManager_RxCallback(void *callbackParam, serial_manager_callback_message_t *message, serial_manager_status_t status) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; #if (!((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))) && \ !((defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)))) uint32_t ringBufferLength = 0; @@ -831,28 +839,28 @@ void SerialManager_RxCallback(void *callbackParam, assert(NULL != callbackParam); assert(NULL != message); - handle = (serial_manager_handle_t *)callbackParam; + serHandle = (serial_manager_handle_t *)callbackParam; #if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \ (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))) - handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; - handle->openedReadHandleHead->transfer.soFar = message->length; - handle->openedReadHandleHead->transfer.length = message->length; - handle->openedReadHandleHead->transfer.buffer = message->buffer; + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + serHandle->openedReadHandleHead->transfer.soFar = message->length; + serHandle->openedReadHandleHead->transfer.length = message->length; + serHandle->openedReadHandleHead->transfer.buffer = message->buffer; #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - handle->commontaskMsg.callback = SerialManager_Task; - handle->commontaskMsg.callbackParam = handle; - COMMON_TASK_post_message(&handle->commontaskMsg); + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); #else primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; EnableGlobalIRQ(primask); - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); #endif #else - SerialManager_Task(handle); + SerialManager_Task(serHandle); #endif #else status = kStatus_SerialManager_Notify; @@ -861,113 +869,115 @@ void SerialManager_RxCallback(void *callbackParam, /* If wrap around is expected copy byte one after the other. Note that this could also be done with 2 memcopy for * better efficiency. */ - if (handle->ringBuffer.ringHead + message->length >= handle->ringBuffer.ringBufferSize) + if (serHandle->ringBuffer.ringHead + message->length >= serHandle->ringBuffer.ringBufferSize) { for (uint32_t i = 0; i < message->length; i++) { - handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i]; + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead++] = message->buffer[i]; - if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize) + if (serHandle->ringBuffer.ringHead >= serHandle->ringBuffer.ringBufferSize) { - handle->ringBuffer.ringHead = 0U; + serHandle->ringBuffer.ringHead = 0U; } - if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail) + if (serHandle->ringBuffer.ringHead == serHandle->ringBuffer.ringTail) { status = kStatus_SerialManager_RingBufferOverflow; - handle->ringBuffer.ringTail++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) { - handle->ringBuffer.ringTail = 0U; + serHandle->ringBuffer.ringTail = 0U; } } } } else /*No wrap is expected so do a memcpy*/ { - (void)memcpy(&handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead], message->buffer, message->length); - handle->ringBuffer.ringHead += message->length; + (void)memcpy(&serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead], message->buffer, + message->length); + serHandle->ringBuffer.ringHead += message->length; } - ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; + ringBufferLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; - if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->transfer.buffer)) + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->transfer.buffer)) { - if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) { uint32_t remainLength = - handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar; + serHandle->openedReadHandleHead->transfer.length - serHandle->openedReadHandleHead->transfer.soFar; for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) { - handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] = - handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; - handle->ringBuffer.ringTail++; - handle->openedReadHandleHead->transfer.soFar++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + serHandle->openedReadHandleHead->transfer.buffer[serHandle->openedReadHandleHead->transfer.soFar] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + serHandle->openedReadHandleHead->transfer.soFar++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) { - handle->ringBuffer.ringTail = 0U; + serHandle->ringBuffer.ringTail = 0U; } } ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); } - if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) { } else { - if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode) + if (kSerialManager_TransmissionBlocking == serHandle->openedReadHandleHead->transfer.mode) { - handle->openedReadHandleHead->transfer.buffer = NULL; + serHandle->openedReadHandleHead->transfer.buffer = NULL; } else { - handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; #if defined(OSA_USED) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - handle->commontaskMsg.callback = SerialManager_Task; - handle->commontaskMsg.callbackParam = handle; - COMMON_TASK_post_message(&handle->commontaskMsg); + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); #else - handle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); #endif #else - SerialManager_Task(handle); + SerialManager_Task(serHandle); #endif } } } #if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) uint32_t ringBufferWaterMark = - handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - ringBufferWaterMark = ringBufferWaterMark % handle->ringBuffer.ringBufferSize; - if (ringBufferWaterMark < (uint32_t)(handle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) { - (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); } #else - (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); #endif if (0U != ringBufferLength) { #if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) - if (handle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] == 0) + if (serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] == 0) { - handle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY]++; - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); } (void)status; /* Fix "set but never used" warning. */ #else /* !SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ message->buffer = NULL; message->length = ringBufferLength; - if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) { - handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status); + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, message, status); } #endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ } @@ -975,14 +985,14 @@ void SerialManager_RxCallback(void *callbackParam, #if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) if (kSerialManager_Blocking == - handle->handleType) /* No need to check for (NULL != handle->openedReadHandleHead) condition as it is already - done in SerialManager_StartReading() */ + serHandle->handleType) /* No need to check for (NULL != serHandle->openedReadHandleHead) condition as it is + already done in SerialManager_StartReading() */ #else - if (NULL != handle->openedReadHandleHead) + if (NULL != serHandle->openedReadHandleHead) #endif { - ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength; - (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); + ringBufferLength = serHandle->ringBuffer.ringBufferSize - 1U - ringBufferLength; + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); } EnableGlobalIRQ(primask); #endif @@ -1017,7 +1027,7 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa serial_manager_transmission_mode_t mode) { serial_manager_write_handle_t *serialWriteHandle; - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; #if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) @@ -1037,8 +1047,8 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa assert(length > 0U); serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = serialWriteHandle->serialManagerHandle; - assert(NULL != handle); + serHandle = serialWriteHandle->serialManagerHandle; + assert(NULL != serHandle); assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); @@ -1054,11 +1064,11 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa serialWriteHandle->transfer.soFar = 0U; serialWriteHandle->transfer.mode = mode; - if (NULL == LIST_GetHead(&handle->runningWriteHandleHead)) + if (NULL == LIST_GetHead(&serHandle->runningWriteHandleHead)) { isEmpty = 1U; } - SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle); + SerialManager_AddTail(&serHandle->runningWriteHandleHead, serialWriteHandle); EnableGlobalIRQ(primask); if (0U != isEmpty) @@ -1066,21 +1076,21 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa #if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) /* Need to support common_task. */ -#else /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ primask = DisableGlobalIRQ(); - handle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; EnableGlobalIRQ(primask); - (void)OSA_SemaphorePost((osa_semaphore_handle_t)handle->serSemaphore); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); #endif /* SERIAL_MANAGER_USE_COMMON_TASK */ #else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ - status = SerialManager_StartWriting(handle); + status = SerialManager_StartWriting(serHandle); if ((serial_manager_status_t)kStatus_SerialManager_Success != status) { #if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) if (status == kStatus_SerialManager_NotConnected) { - SerialManager_RemoveHead(&handle->runningWriteHandleHead); + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); serialWriteHandle->transfer.buffer = 0U; serialWriteHandle->transfer.length = 0U; } @@ -1096,7 +1106,7 @@ static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHa { if (SerialManager_needPollingIsr()) { - SerialManager_IsrFunction(handle); + SerialManager_IsrFunction(serHandle); } else { @@ -1114,7 +1124,7 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl uint32_t *receivedLength) { serial_manager_read_handle_t *serialReadHandle; - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; uint32_t dataLength; uint32_t primask; @@ -1124,8 +1134,8 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = serialReadHandle->serialManagerHandle; - assert(NULL != handle); + serHandle = serialReadHandle->serialManagerHandle; + assert(NULL != serHandle); assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); @@ -1141,43 +1151,46 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.mode = mode; - /* This code is reached if (handle->handleType != kSerialManager_Blocking)*/ + /* This code is reached if (serHandle->handleType != kSerialManager_Blocking)*/ #if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) if (length == 1U) { - if (handle->ringBuffer.ringHead != handle->ringBuffer.ringTail) + if (serHandle->ringBuffer.ringHead != serHandle->ringBuffer.ringTail) { - buffer[serialReadHandle->transfer.soFar++] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; - handle->ringBuffer.ringTail++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + buffer[serialReadHandle->transfer.soFar++] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) { - handle->ringBuffer.ringTail = 0U; + serHandle->ringBuffer.ringTail = 0U; } } } else #endif /*(!defined(SERIAL_PORT_TYPE_USBCDC) && !defined(SERIAL_PORT_TYPE_VIRTUAL))*/ { - dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - dataLength = dataLength % handle->ringBuffer.ringBufferSize; + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); serialReadHandle->transfer.soFar++) { - buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; - handle->ringBuffer.ringTail++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + buffer[serialReadHandle->transfer.soFar] = serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) { - handle->ringBuffer.ringTail = 0U; + serHandle->ringBuffer.ringTail = 0U; } } - dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - dataLength = dataLength % handle->ringBuffer.ringBufferSize; - dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength; + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; + dataLength = serHandle->ringBuffer.ringBufferSize - 1U - dataLength; - (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength); + (void)SerialManager_StartReading(serHandle, readHandle, NULL, dataLength); } if (NULL != receivedLength) @@ -1199,7 +1212,8 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl serial_manager_callback_message_t serialMsg; serialMsg.buffer = buffer; serialMsg.length = serialReadHandle->transfer.soFar; - serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, kStatus_SerialManager_Success); + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, + kStatus_SerialManager_Success); } } } @@ -1218,11 +1232,12 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl } #if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) uint32_t ringBufferWaterMark = - handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - ringBufferWaterMark = ringBufferWaterMark % handle->ringBuffer.ringBufferSize; - if (ringBufferWaterMark < (uint32_t)(handle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) { - (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, serialReadHandle->transfer.length); + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, + serialReadHandle->transfer.length); } #endif return kStatus_SerialManager_Success; @@ -1233,62 +1248,62 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) { serial_manager_write_handle_t *serialWriteHandle; - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; assert(writeHandle); assert(buffer); assert(length); serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = serialWriteHandle->serialManagerHandle; + serHandle = serialWriteHandle->serialManagerHandle; - assert(handle); + assert(serHandle); - return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length); + return SerialManager_StartWriting(serHandle, serialWriteHandle, buffer, length); } static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) { serial_manager_read_handle_t *serialReadHandle; - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; assert(readHandle); assert(buffer); assert(length); serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = serialReadHandle->serialManagerHandle; + serHandle = serialReadHandle->serialManagerHandle; - assert(handle); + assert(serHandle); - return SerialManager_StartReading(handle, serialReadHandle, buffer, length); + return SerialManager_StartReading(serHandle, serialReadHandle, buffer, length); } #endif -serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *config) +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_status_t status = kStatus_SerialManager_Error; - assert(NULL != config); + assert(NULL != serialConfig); assert(NULL != serialHandle); assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - assert(NULL != config->ringBuffer); - assert(config->ringBufferSize > 0U); - (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); - handle->handleType = config->blockType; + assert(NULL != serialConfig->ringBuffer); + assert(serialConfig->ringBufferSize > 0U); + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); + serHandle->handleType = serialConfig->blockType; #else - (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); #endif - handle->serialPortType = config->type; + serHandle->serialPortType = serialConfig->type; #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - handle->ringBuffer.ringBuffer = config->ringBuffer; - handle->ringBuffer.ringBufferSize = config->ringBufferSize; + serHandle->ringBuffer.ringBuffer = serialConfig->ringBuffer; + serHandle->ringBuffer.ringBufferSize = serialConfig->ringBufferSize; #endif #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) @@ -1299,12 +1314,12 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s COMMON_TASK_init(); #else - if (KOSA_StatusSuccess != OSA_SemaphoreCreate((osa_semaphore_handle_t)handle->serSemaphore, 1U)) + if (KOSA_StatusSuccess != OSA_SemaphoreCreate((osa_semaphore_handle_t)serHandle->serSemaphore, 1U)) { return kStatus_SerialManager_Error; } - if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle)) + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId, OSA_TASK(SerialManager_Task), serHandle)) { return kStatus_SerialManager_Error; } @@ -1313,35 +1328,35 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #endif - - switch (config->type) + + switch (serialConfig->type) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = Serial_UartInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if ((serial_manager_status_t)kStatus_SerialManager_Success == status) { - (void)Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + (void)Serial_UartInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); - (void)Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + (void)Serial_UartInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } #endif break; #endif #if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) case kSerialPort_UartDma: - status = Serial_UartDmaInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = Serial_UartDmaInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if ((serial_manager_status_t)kStatus_SerialManager_Success == status) { - (void)Serial_UartDmaInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + (void)Serial_UartDmaInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); - (void)Serial_UartDmaInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + (void)Serial_UartDmaInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } #endif break; @@ -1349,17 +1364,17 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) case kSerialPort_UsbCdc: - status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = Serial_UsbCdcInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif @@ -1367,28 +1382,29 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) case kSerialPort_Swo: - status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = Serial_SwoInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_SwoInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); } #endif break; #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) case kSerialPort_Virtual: - status = Serial_PortVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = + Serial_PortVirtualInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif @@ -1396,16 +1412,16 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) case kSerialPort_Rpmsg: - status = Serial_RpmsgInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), (void *)config); + status = Serial_RpmsgInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), (void *)serialConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif @@ -1413,16 +1429,17 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) case kSerialPort_SpiMaster: - status = Serial_SpiMasterInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = + Serial_SpiMasterInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_SpiMasterInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_SpiMasterInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_SpiMasterInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_SpiMasterInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif @@ -1430,16 +1447,16 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) case kSerialPort_SpiSlave: - status = Serial_SpiSlaveInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = Serial_SpiSlaveInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_SpiSlaveInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_SpiSlaveInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_SpiSlaveInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_SpiSlaveInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif @@ -1447,21 +1464,22 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) case kSerialPort_BleWu: - status = Serial_PortBleWuInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); + status = + Serial_PortBleWuInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) if (kStatus_SerialManager_Success == status) { - status = Serial_PortBleWuInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); + status = Serial_PortBleWuInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); if (kStatus_SerialManager_Success == status) { - status = Serial_PortBleWuInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); + status = Serial_PortBleWuInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); } } #endif break; -#endif +#endif default: /*MISRA rule 16.4*/ break; @@ -1472,60 +1490,60 @@ serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const s serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; assert(NULL != serialHandle); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; - if ((NULL != handle->openedReadHandleHead) || (0U != handle->openedWriteHandleCount)) + if ((NULL != serHandle->openedReadHandleHead) || (0U != serHandle->openedWriteHandleCount)) { serialManagerStatus = kStatus_SerialManager_Busy; /*Serial Manager Busy*/ } else { - switch (handle->serialPortType) /*serial port type*/ + switch (serHandle->serialPortType) /*serial port type*/ { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_UartDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) case kSerialPort_UsbCdc: - (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_UsbCdcDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) case kSerialPort_Swo: - (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_SwoDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) case kSerialPort_Virtual: - (void)Serial_PortVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_PortVirtualDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) case kSerialPort_Rpmsg: - (void)Serial_RpmsgDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_RpmsgDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) case kSerialPort_SpiSlave: - (void)Serial_SpiSlaveDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_SpiSlaveDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) case kSerialPort_SpiMaster: - (void)Serial_SpiMasterDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_SpiMasterDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) case kSerialPort_BleWu: - (void)Serial_PortBleWuDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_PortBleWuDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif default: @@ -1538,8 +1556,8 @@ serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #else - (void)OSA_SemaphoreDestroy((osa_event_handle_t)handle->serSemaphore); - (void)OSA_TaskDestroy((osa_task_handle_t)handle->taskId); + (void)OSA_SemaphoreDestroy((osa_event_handle_t)serHandle->serSemaphore); + (void)OSA_TaskDestroy((osa_task_handle_t)serHandle->taskId); #endif #endif @@ -1551,7 +1569,7 @@ serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_write_handle_t *serialWriteHandle; uint32_t primask; @@ -1559,16 +1577,16 @@ serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHand assert(NULL != writeHandle); assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; primask = DisableGlobalIRQ(); - handle->openedWriteHandleCount++; + serHandle->openedWriteHandleCount++; EnableGlobalIRQ(primask); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if (handle->handleType == kSerialManager_Blocking) + if (serHandle->handleType == kSerialManager_Blocking) { - serialWriteHandle->serialManagerHandle = handle; + serialWriteHandle->serialManagerHandle = serHandle; return kStatus_SerialManager_Success; } else @@ -1577,7 +1595,7 @@ serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHand (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); } - serialWriteHandle->serialManagerHandle = handle; + serialWriteHandle->serialManagerHandle = serHandle; #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; @@ -1588,16 +1606,16 @@ serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHand serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serialHandle; serial_manager_write_handle_t *serialWriteHandle; uint32_t primask; assert(NULL != writeHandle); serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; - assert(NULL != handle); + assert(NULL != serialHandle); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); #endif @@ -1606,20 +1624,23 @@ serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t wri (void)SerialManager_CancelWriting(writeHandle); #endif primask = DisableGlobalIRQ(); - if (handle->openedWriteHandleCount > 0U) + if (serialHandle->openedWriteHandleCount > 0U) { - handle->openedWriteHandleCount--; + serialHandle->openedWriteHandleCount--; } EnableGlobalIRQ(primask); - +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); +#else + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE); +#endif return kStatus_SerialManager_Success; } serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_read_handle_t *serialReadHandle; /* read handle structure */ serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; uint32_t primask; @@ -1628,27 +1649,27 @@ serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandl assert(NULL != readHandle); assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; serialReadHandle = (serial_manager_read_handle_t *)readHandle; #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if (handle->handleType == kSerialManager_Blocking) + if (serHandle->handleType == kSerialManager_Blocking) { - serialReadHandle->serialManagerHandle = handle; + serialReadHandle->serialManagerHandle = serHandle; return kStatus_SerialManager_Success; } #endif primask = DisableGlobalIRQ(); - if (handle->openedReadHandleHead != NULL) + if (serHandle->openedReadHandleHead != NULL) { serialManagerStatus = kStatus_SerialManager_Busy; } else { - handle->openedReadHandleHead = serialReadHandle; + serHandle->openedReadHandleHead = serialReadHandle; (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); - serialReadHandle->serialManagerHandle = handle; + serialReadHandle->serialManagerHandle = serHandle; #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; #endif @@ -1659,16 +1680,16 @@ serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandl serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serialHandle; serial_manager_read_handle_t *serialReadHandle; uint32_t primask; assert(NULL != readHandle); serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; - assert((NULL != handle) && (handle->openedReadHandleHead == serialReadHandle)); + assert((NULL != serialHandle) && (serialHandle->openedReadHandleHead == serialReadHandle)); #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); #endif @@ -1677,11 +1698,14 @@ serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readH (void)SerialManager_CancelReading(readHandle); #endif - primask = DisableGlobalIRQ(); - handle->openedReadHandleHead = NULL; + primask = DisableGlobalIRQ(); + serialHandle->openedReadHandleHead = NULL; EnableGlobalIRQ(primask); - +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); +#else + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE); +#endif return kStatus_SerialManager_Success; } @@ -1843,7 +1867,7 @@ serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeH #if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) /* Need to support common_task. */ -#else /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ primask = DisableGlobalIRQ(); serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; EnableGlobalIRQ(primask); @@ -1881,8 +1905,8 @@ serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHan buffer = serialReadHandle->transfer.buffer; serialReadHandle->transfer.buffer = NULL; serialReadHandle->transfer.length = 0; - serialMsg.buffer = buffer; - serialMsg.length = serialReadHandle->transfer.soFar; + serialMsg.buffer = buffer; + serialMsg.length = serialReadHandle->transfer.soFar; EnableGlobalIRQ(primask); if (NULL != buffer) @@ -1944,23 +1968,23 @@ serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t rea serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_status_t status = kStatus_SerialManager_Error; assert(NULL != serialHandle); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; - switch (handle->serialPortType) + switch (serHandle->serialPortType) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - status = Serial_UartEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + status = Serial_UartEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) case kSerialPort_UartDma: - status = Serial_UartDmaEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + status = Serial_UartDmaEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) @@ -2000,24 +2024,24 @@ serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) { - serial_manager_handle_t *handle; + serial_manager_handle_t *serHandle; serial_manager_status_t status = kStatus_SerialManager_Error; assert(NULL != serialHandle); - handle = (serial_manager_handle_t *)serialHandle; + serHandle = (serial_manager_handle_t *)serialHandle; - switch (handle->serialPortType) + switch (serHandle->serialPortType) { #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) case kSerialPort_Uart: - status = Serial_UartExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + status = Serial_UartExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) case kSerialPort_UartDma: - status = Serial_UartDmaExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + status = Serial_UartDmaExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); break; #endif #if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) diff --git a/components/serial_manager/fsl_component_serial_manager.h b/components/serial_manager/fsl_component_serial_manager.h index f095b183d..16d7ef5a5 100644 --- a/components/serial_manager/fsl_component_serial_manager.h +++ b/components/serial_manager/fsl_component_serial_manager.h @@ -89,16 +89,6 @@ #endif #endif -/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */ -#ifndef SERIAL_MANAGER_TASK_HANDLE_TX -#define SERIAL_MANAGER_TASK_HANDLE_TX (0U) -#endif -#if (defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX > 0U)) -#ifndef OSA_USED -#error When SERIAL_MANAGER_TASK_HANDLE_TX=1, OSA_USED must be set. -#endif -#endif - /*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */ #ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE #define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U) @@ -270,6 +260,10 @@ #if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) #include "fsl_component_common_task.h" #endif +/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_TX +#define SERIAL_MANAGER_TASK_HANDLE_TX (1U) +#endif #endif #if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) @@ -283,7 +277,7 @@ #if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) #define SERIAL_MANAGER_HANDLE_SIZE \ (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE) -#else /*defined(OSA_USED)*/ +#else /*defined(OSA_USED)*/ #define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U) #endif /*defined(OSA_USED)*/ #define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U) @@ -397,10 +391,10 @@ typedef enum _serial_manager_type typedef struct _serial_manager_config { #if defined(SERIAL_MANAGER_NON_BLOCKING_MODE) - uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. - Besides, the memory space cannot be free during the lifetime of the serial - manager module. */ - uint32_t ringBufferSize; /*!< The size of the ring buffer */ + uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. + Besides, the memory space cannot be free during the lifetime of the serial + manager module. */ + uint32_t ringBufferSize; /*!< The size of the ring buffer */ #endif serial_port_type_t type; /*!< Serial port type */ serial_manager_type_t blockType; /*!< Serial manager port type */ @@ -507,11 +501,11 @@ extern "C" { * #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle); * or * uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; - * @param config Pointer to user-defined configuration structure. + * @param serialConfig Pointer to user-defined configuration structure. * @retval kStatus_SerialManager_Error An error occurred. * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. */ -serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *config); +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig); /*! * @brief De-initializes the serial manager module instance. diff --git a/components/serial_manager/fsl_component_serial_port_internal.h b/components/serial_manager/fsl_component_serial_port_internal.h index 702bf22a5..c2090348d 100644 --- a/components/serial_manager/fsl_component_serial_port_internal.h +++ b/components/serial_manager/fsl_component_serial_port_internal.h @@ -174,11 +174,11 @@ serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle); serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); + serial_manager_callback_t callback, + void *callbackParam); serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); + serial_manager_callback_t callback, + void *callbackParam); void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle); #endif diff --git a/components/serial_manager/fsl_component_serial_port_spi.c b/components/serial_manager/fsl_component_serial_port_spi.c index d5f29c8dd..a16745560 100644 --- a/components/serial_manager/fsl_component_serial_port_spi.c +++ b/components/serial_manager/fsl_component_serial_port_spi.c @@ -406,8 +406,8 @@ serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint serialSpiMasterHandle = (serial_spi_master_state_t *)serialHandle; - mastetTransfer.txData = buffer; - mastetTransfer.rxData = NULL; + mastetTransfer.txData = buffer; + mastetTransfer.rxData = NULL; mastetTransfer.dataSize = (size_t)length; return (serial_manager_status_t)HAL_SpiMasterTransferBlocking( ((hal_spi_master_handle_t)&serialSpiMasterHandle->spiMasterHandleBuffer[0]), &mastetTransfer); @@ -422,9 +422,9 @@ serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8 assert(buffer); assert(length); - serialSpiMasterHandle = (serial_spi_master_state_t *)serialHandle; - masterReceiver.txData = NULL; - masterReceiver.rxData = buffer; + serialSpiMasterHandle = (serial_spi_master_state_t *)serialHandle; + masterReceiver.txData = NULL; + masterReceiver.rxData = buffer; masterReceiver.dataSize = (size_t)length; return (serial_manager_status_t)HAL_SpiMasterTransferBlocking( ((hal_spi_master_handle_t)&serialSpiMasterHandle->spiMasterHandleBuffer[0]), &masterReceiver); diff --git a/components/serial_manager/fsl_component_serial_port_spi.h b/components/serial_manager/fsl_component_serial_port_spi.h index f3ae63781..f15b47e03 100644 --- a/components/serial_manager/fsl_component_serial_port_spi.h +++ b/components/serial_manager/fsl_component_serial_port_spi.h @@ -80,8 +80,8 @@ typedef struct _serial_spi_master_config bool enableMaster; /*!< Enable spi at initialization time */ uint32_t configFlags; /*!< Transfer config Flags */ #if (defined(HAL_SPI_MASTER_DMA_ENABLE) && (HAL_SPI_MASTER_DMA_ENABLE > 0U)) - bool enableDMA; /*!< Enable DMA at initialization time */ - void *dmaConfig; /*!< DMA configure pointer */ + bool enableDMA; /*!< Enable DMA at initialization time */ + void *dmaConfig; /*!< DMA configure pointer */ #endif } serial_spi_master_config_t; @@ -95,8 +95,8 @@ typedef struct _serial_spi_slave_config bool enableSlave; /*!< Enable spi at initialization time */ uint32_t configFlags; /*!< Transfer config Flags */ #if (defined(HAL_SPI_SLAVE_DMA_ENABLE) && (HAL_SPI_SLAVE_DMA_ENABLE > 0U)) - bool enableDMA; /*!< Enable DMA at initialization time */ - void *dmaConfig; /*!< DMA configure pointer */ + bool enableDMA; /*!< Enable DMA at initialization time */ + void *dmaConfig; /*!< DMA configure pointer */ #endif } serial_spi_slave_config_t; diff --git a/components/serial_manager/fsl_component_serial_port_uart.c b/components/serial_manager/fsl_component_serial_port_uart.c index 218e894e2..c2073f798 100644 --- a/components/serial_manager/fsl_component_serial_port_uart.c +++ b/components/serial_manager/fsl_component_serial_port_uart.c @@ -146,7 +146,8 @@ static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t stat { serialMsg.buffer = &serialUartHandle->rx.readBuffer[0]; serialMsg.length = sizeof(serialUartHandle->rx.readBuffer); - serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg, kStatus_SerialManager_Success); + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); } } else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) @@ -158,7 +159,8 @@ static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t stat { serialMsg.buffer = serialUartHandle->tx.buffer; serialMsg.length = serialUartHandle->tx.length; - serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, kStatus_SerialManager_Success); + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); } } } @@ -340,7 +342,8 @@ serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) { serialMsg.buffer = serialUartHandle->tx.buffer; serialMsg.length = serialUartHandle->tx.length; - serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, kStatus_SerialManager_Canceled); + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); } } return kStatus_SerialManager_Success; @@ -627,7 +630,8 @@ serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle) { serialMsg.buffer = serialUartHandle->tx.buffer; serialMsg.length = serialUartHandle->tx.length; - serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, kStatus_SerialManager_Canceled); + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); } } return kStatus_SerialManager_Success; diff --git a/components/serial_manager/fsl_component_serial_port_uart.h b/components/serial_manager/fsl_component_serial_port_uart.h index bce73a50d..a4221cbfe 100644 --- a/components/serial_manager/fsl_component_serial_port_uart.h +++ b/components/serial_manager/fsl_component_serial_port_uart.h @@ -64,12 +64,12 @@ typedef struct _serial_port_uart_config serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - uint8_t enableRx; /*!< Enable RX */ - uint8_t enableTx; /*!< Enable TX */ - uint8_t enableRxRTS; /*!< Enable RX RTS */ - uint8_t enableTxCTS; /*!< Enable TX CTS */ - uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information - please refer to the SOC corresponding RM. */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) uint8_t txFifoWatermark; @@ -84,12 +84,12 @@ typedef struct _serial_port_uart_dma_config serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - uint8_t enableRx; /*!< Enable RX */ - uint8_t enableTx; /*!< Enable TX */ - uint8_t enableRxRTS; /*!< Enable RX RTS */ - uint8_t enableTxCTS; /*!< Enable TX CTS */ - uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information - please refer to the SOC corresponding RM. */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) uint8_t txFifoWatermark; uint8_t rxFifoWatermark; diff --git a/components/serial_manager/fsl_component_serial_port_usb.c b/components/serial_manager/fsl_component_serial_port_usb.c index a4aa580ec..ca1134bc8 100644 --- a/components/serial_manager/fsl_component_serial_port_usb.c +++ b/components/serial_manager/fsl_component_serial_port_usb.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2020 NXP + * Copyright 2016 - 2020, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -122,7 +122,7 @@ typedef struct _serial_usb_cdc_state volatile uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */ uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */ volatile uint8_t - startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */ + startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */ uint8_t currentConfiguration; /* Current configuration value. */ uint8_t currentInterfaceAlternateSetting[USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */ @@ -491,9 +491,9 @@ static usb_status_t USB_DeviceCdcVcomCallback(class_handle_t handle, uint32_t ev acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_NOTIF_SERIAL_STATE; /* bNotification */ acmInfo->serialStateBuf[2] = 0x00; /* wValue */ acmInfo->serialStateBuf[3] = 0x00; - acmInfo->serialStateBuf[4] = 0x00; /* wIndex */ + acmInfo->serialStateBuf[4] = 0x00; /* wIndex */ acmInfo->serialStateBuf[5] = 0x00; - acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */ + acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */ acmInfo->serialStateBuf[7] = 0x00; /* Notifiy to host the line state */ acmInfo->serialStateBuf[4] = (uint8_t)acmReqParam->interfaceIndex; @@ -655,6 +655,7 @@ static usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, } #if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#ifndef SERIAL_PORT_USB_CDC_USB_OTG2_IRQ_HANDLER_DISABLE void USB_OTG2_IRQHandler(void); void USB_OTG2_IRQHandler(void) { @@ -669,9 +670,11 @@ void USB_OTG2_IRQHandler(void) serialUsbCdc = serialUsbCdc->next; } } +#endif /* SERIAL_PORT_USB_CDC_USB_OTG2_IRQ_HANDLER_DISABLE */ #endif #if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) +#ifndef SERIAL_PORT_USB_CDC_USBHS_IRQ_HANDLER_DISABLE void USBHS_IRQHandler(void); void USBHS_IRQHandler(void) { @@ -687,8 +690,10 @@ void USBHS_IRQHandler(void) } SDK_ISR_EXIT_BARRIER; } +#endif /* SERIAL_PORT_USB_CDC_USBHS_IRQ_HANDLER_DISABLE */ #if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 1U) #if defined(FSL_FEATURE_USBHS_EHCI_COUNT) && (FSL_FEATURE_USBHS_EHCI_COUNT > 1U) +#ifndef SERIAL_PORT_USB_CDC_USB1_IRQ_HANDLER_DISABLE void USB1_IRQHandler(void); void USB1_IRQHandler(void) { @@ -704,10 +709,12 @@ void USB1_IRQHandler(void) } SDK_ISR_EXIT_BARRIER; } +#endif /* SERIAL_PORT_USB_CDC_USB1_IRQ_HANDLER_DISABLE */ #endif #endif #endif #if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0U) +#ifndef SERIAL_PORT_USB_CDC_USB0_IRQ_HANDLER_DISABLE void USB0_IRQHandler(void); void USB0_IRQHandler(void) { @@ -723,8 +730,10 @@ void USB0_IRQHandler(void) } SDK_ISR_EXIT_BARRIER; } +#endif /* SERIAL_PORT_USB_CDC_USB0_IRQ_HANDLER_DISABLE */ #endif #if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) +#ifndef SERIAL_PORT_USB_CDC_USB0_IRQ_HANDLER_DISABLE void USB0_IRQHandler(void); void USB0_IRQHandler(void) { @@ -740,8 +749,10 @@ void USB0_IRQHandler(void) } SDK_ISR_EXIT_BARRIER; } +#endif /* SERIAL_PORT_USB_CDC_USB0_IRQ_HANDLER_DISABLE */ #endif #if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +#ifndef SERIAL_PORT_USB_CDC_USB1_IRQ_HANDLER_DISABLE void USB1_IRQHandler(void); void USB1_IRQHandler(void) { @@ -757,6 +768,7 @@ void USB1_IRQHandler(void) } SDK_ISR_EXIT_BARRIER; } +#endif /* SERIAL_PORT_USB_CDC_USB1_IRQ_HANDLER_DISABLE */ #endif static void USB_DeviceIsrEnable(serial_usb_cdc_state_t *serialUsbCdc) diff --git a/components/serial_manager/fsl_component_serial_port_usb.h b/components/serial_manager/fsl_component_serial_port_usb.h index 4c695a418..42340794c 100644 --- a/components/serial_manager/fsl_component_serial_port_usb.h +++ b/components/serial_manager/fsl_component_serial_port_usb.h @@ -64,7 +64,7 @@ typedef enum _serial_port_usb_cdc_controller_index kSerialManager_UsbControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved to be used in the future. */ - kSerialManager_UsbControllerOhci0 = 8U, /*!< OHCI 0U */ + kSerialManager_UsbControllerOhci0 = 8U, /*!< OHCI 0U */ kSerialManager_UsbControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved to be used in the future. */ diff --git a/components/serial_manager/fsl_component_serial_port_virtual.h b/components/serial_manager/fsl_component_serial_port_virtual.h index c7bb7bbf1..9c7ca4ee0 100644 --- a/components/serial_manager/fsl_component_serial_port_virtual.h +++ b/components/serial_manager/fsl_component_serial_port_virtual.h @@ -37,8 +37,8 @@ typedef enum _serial_port_virtual_controller_index kSerialManager_UsbVirtualControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ kSerialManager_UsbVirtualControllerLpcIp3511Hs1 = - 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which - have two IP3511 IPs, this is reserved to be used in the future. */ + 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which + have two IP3511 IPs, this is reserved to be used in the future. */ kSerialManager_UsbVirtualControllerOhci0 = 8U, /*!< OHCI 0U */ kSerialManager_UsbVirtualControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI diff --git a/components/ssd1963/fsl_ssd1963.h b/components/ssd1963/fsl_ssd1963.h index 891be4fff..7bef1e08d 100644 --- a/components/ssd1963/fsl_ssd1963.h +++ b/components/ssd1963/fsl_ssd1963.h @@ -198,9 +198,9 @@ typedef struct _ssd1963_config /*! @brief SSD1963 flip mode. */ typedef enum _ssd1963_flip_mode { - kSSD1963_FlipNone = 0U, /*!< No flip. */ - kSSD1963_FlipVertical = SSD1963_ADDR_MODE_FLIP_VERT, /*!< Flip vertical, set_address_mode A[0] */ - kSSD1963_FlipHorizontal = SSD1963_ADDR_MODE_FLIP_HORZ, /*!< Flip horizontal, set_address_mode A[1] */ + kSSD1963_FlipNone = 0U, /*!< No flip. */ + kSSD1963_FlipVertical = SSD1963_ADDR_MODE_FLIP_VERT, /*!< Flip vertical, set_address_mode A[0] */ + kSSD1963_FlipHorizontal = SSD1963_ADDR_MODE_FLIP_HORZ, /*!< Flip horizontal, set_address_mode A[1] */ kSSD1963_FlipBoth = SSD1963_ADDR_MODE_FLIP_VERT | SSD1963_ADDR_MODE_FLIP_HORZ, /*!< Flip both vertical and horizontal. */ } ssd1963_flip_mode_t; @@ -212,13 +212,13 @@ typedef enum _ssd1963_flip_mode */ typedef enum _ssd1963_orientation_mode_t { - kSSD1963_Orientation0 = 0U, /*!< Rotate 0 degree. */ + kSSD1963_Orientation0 = 0U, /*!< Rotate 0 degree. */ kSSD1963_Orientation90 = SSD1963_ADDR_MODE_PAGE_ADDR_ORDER | SSD1963_ADDR_MODE_PAG_COL_ADDR_ORDER, /*!< Rotate 90 degree. */ kSSD1963_Orientation180 = - SSD1963_ADDR_MODE_PAGE_ADDR_ORDER | SSD1963_ADDR_MODE_COL_ADDR_ORDER, /*!< Rotate 180 degree. */ + SSD1963_ADDR_MODE_PAGE_ADDR_ORDER | SSD1963_ADDR_MODE_COL_ADDR_ORDER, /*!< Rotate 180 degree. */ kSSD1963_Orientation270 = - SSD1963_ADDR_MODE_COL_ADDR_ORDER | SSD1963_ADDR_MODE_PAG_COL_ADDR_ORDER, /*!< Rotate 270 degree. */ + SSD1963_ADDR_MODE_COL_ADDR_ORDER | SSD1963_ADDR_MODE_PAG_COL_ADDR_ORDER, /*!< Rotate 270 degree. */ } ssd1963_orientation_mode_t; /******************************************************************************* diff --git a/components/st7796s/fsl_st7796s.c b/components/st7796s/fsl_st7796s.c new file mode 100644 index 000000000..d069104fc --- /dev/null +++ b/components/st7796s/fsl_st7796s.c @@ -0,0 +1,282 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_st7796s.h" + +#define ST7796S_ERROR_CHECK(x) \ + do \ + { \ + status_t ret = (x); \ + if (ret != kStatus_Success) \ + { \ + return ret; \ + } \ + } while (false) + +#define ST7796S_CMD_SWRESET (0x01U) +#define ST7796S_CMD_SLPIN (0x10U) +#define ST7796S_CMD_SLPOUT (0x11U) +#define ST7796S_CMD_INVOFF (0x20U) +#define ST7796S_CMD_INVON (0x21U) +#define ST7796S_CMD_DISPOFF (0x28U) +#define ST7796S_CMD_DISPON (0x29U) +#define ST7796S_CMD_CASET (0x2AU) +#define ST7796S_CMD_RASET (0x2BU) +#define ST7796S_CMD_RAMWR (0x2CU) +#define ST7796S_CMD_TEOFF (0x34U) +#define ST7796S_CMD_TEON (0x35U) +#define ST7796S_CMD_MADCTL (0x36U) +#define ST7796S_CMD_COLMOD (0x3AU) +#define ST7796S_CMD_CSCON (0xF0U) +#define ST7796S_CMD_INVTR (0xB4U) +#define ST7796S_CMD_FRMCTR1 (0xB1U) +#define ST7796S_CMD_BPC (0xB5U) +#define ST7796S_CMD_DFC (0xB6U) +#define ST7796S_CMD_PWR1 (0xC0U) +#define ST7796S_CMD_PWR2 (0xC1U) +#define ST7796S_CMD_PWR3 (0xC2U) +#define ST7796S_CMD_VCMPCTL (0xC5U) +#define ST7796S_CMD_DOCA (0xE8U) +#define ST7796S_CMD_PGC (0xE0U) +#define ST7796S_CMD_NGC (0xE1U) + +/* + * This is the panel-specific initialization parameters for driver section, + * including analog power/voltage control, gamma correction, scan timing, etc. + * Data format: | 1 Byte parameter length | 1 Byte command byte | N Bytes command parameter | + */ +static const uint8_t s_st7796s_driver_preset_pars035[] = { + /* clang-format off */ + 0x01, ST7796S_CMD_CSCON, 0xC3, // Enable command part 1 + 0x01, ST7796S_CMD_CSCON, 0x96, // Enable command part 2 + 0x01, ST7796S_CMD_INVTR, 0x01, // Display inversion + 0x02, ST7796S_CMD_FRMCTR1, 0x80, 0x10, // Frame rate control 1 + 0x04, ST7796S_CMD_BPC, 0x1F, 0x50, 0x00, 0x20, // Blanking porch control + 0x03, ST7796S_CMD_DFC, 0x8A, 0x07, 0x3B, // Display function control + 0x02, ST7796S_CMD_PWR1, 0x80, 0x64, // Power control 1 + 0x01, ST7796S_CMD_PWR2, 0x13, // Power control 2 + 0x01, ST7796S_CMD_PWR3, 0xA7, // Power control 3 + 0x01, ST7796S_CMD_VCMPCTL, 0x09, // VCOM control + 0x08, ST7796S_CMD_DOCA, 0x40, 0x8A, 0x00, 0x00, 0x29, 0x19, 0xA5, 0x33, // DOCA + 0x0E, ST7796S_CMD_PGC, 0xF0, 0x06, 0x0B, 0x07, 0x06, 0x05, 0x2E, 0x33, 0x47, 0x3A, 0x17, 0x16, 0x2E, 0x31, // PGC + 0x0E, ST7796S_CMD_NGC, 0xF0, 0x09, 0x0D, 0x09, 0x08, 0x23, 0x2E, 0x33, 0x46, 0x38, 0x13, 0x13, 0x2C, 0x32, // NGC + 0x01, ST7796S_CMD_CSCON, 0x3C, // Disable command part 1 + 0x01, ST7796S_CMD_CSCON, 0x69, // Disable command part 2 + /* clang-format on */ +}; + +static status_t ST7796S_WriteCommand(st7796s_handle_t *handle, + uint8_t command, + const uint8_t *params, + uint8_t param_len) +{ + ST7796S_ERROR_CHECK(handle->xferOps->writeCommand(handle->xferOpsData, command)); + + for (uint8_t i = 0; i < param_len; i++) + { + uint16_t param_data = params[i]; + + ST7796S_ERROR_CHECK(handle->xferOps->writeData(handle->xferOpsData, ¶m_data, 2U)); + } + + return kStatus_Success; +} + +static status_t ST7796S_PresetDriver(st7796s_handle_t *handle, st7796s_driver_preset_t preset) +{ + const uint8_t *preset_ptr; + uint16_t preset_len; + + if (kST7796S_DriverPresetLCDPARS035 == preset) + { + preset_ptr = s_st7796s_driver_preset_pars035; + preset_len = ARRAY_SIZE(s_st7796s_driver_preset_pars035); + } + else + { + return kStatus_InvalidArgument; + } + + uint16_t i = 0; + + while (i < preset_len) + { + uint8_t param_len = preset_ptr[i]; + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, preset_ptr[i + 1u], &preset_ptr[i + 2u], param_len)); + i += ((uint16_t)param_len + 2u); /* Next = parameter length + command byte + length itself */ + } + + return kStatus_Success; +} + +static status_t ST7796S_SoftwareReset(st7796s_handle_t *handle) +{ + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_SWRESET, NULL, 0)); + SDK_DelayAtLeastUs(5 * 1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + return kStatus_Success; +} + +static status_t ST7796S_SleepMode(st7796s_handle_t *handle, bool sleep) +{ + uint8_t slp_cmd; + if (sleep) + { + slp_cmd = ST7796S_CMD_SLPIN; + } + else + { + slp_cmd = ST7796S_CMD_SLPOUT; + } + + return ST7796S_WriteCommand(handle, slp_cmd, NULL, 0); +} + +status_t ST7796S_Init(st7796s_handle_t *handle, + const st7796s_config_t *config, + const dbi_xfer_ops_t *xferOps, + void *xferOpsData) +{ + handle->xferOps = xferOps; + handle->xferOpsData = xferOpsData; + + ST7796S_ERROR_CHECK(ST7796S_SoftwareReset(handle)); + ST7796S_ERROR_CHECK(ST7796S_PresetDriver(handle, config->driverPreset)); + ST7796S_ERROR_CHECK(ST7796S_SleepMode(handle, false)); + ST7796S_ERROR_CHECK(ST7796S_Config(handle, config)); + + return kStatus_Success; +} + +status_t ST7796S_InvertDisplay(st7796s_handle_t *handle, bool invert) +{ + uint8_t inv_cmd; + if (invert) + { + inv_cmd = ST7796S_CMD_INVON; + } + else + { + inv_cmd = ST7796S_CMD_INVOFF; + } + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, inv_cmd, NULL, 0U)); + + return kStatus_Success; +} + +status_t ST7796S_EnableDisplay(st7796s_handle_t *handle, bool enable) +{ + uint8_t disp_cmd; + if (enable) + { + disp_cmd = ST7796S_CMD_DISPON; + } + else + { + disp_cmd = ST7796S_CMD_DISPOFF; + } + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, disp_cmd, NULL, 0U)); + + return kStatus_Success; +} + +status_t ST7796S_SetPixelFormat(st7796s_handle_t *handle, st7796s_pixel_format_t pixelFormat) +{ + uint8_t pixel_fmt = (uint8_t)pixelFormat; + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_COLMOD, &pixel_fmt, 0x01U)); + + return kStatus_Success; +} + +status_t ST7796S_SetTEConfig(st7796s_handle_t *handle, st7796s_te_config_t teConfig) +{ + if (teConfig == kST7796S_TEDisabled) + { + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_TEOFF, NULL, 0U)); + } + else + { + uint8_t te_cfg = 0x00U; + if (teConfig == kST7796S_TEHVSync) + { + te_cfg |= 0x01U; /* Set TEM bit */ + } + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_TEON, &te_cfg, 1U)); + } + + return kStatus_Success; +} + +status_t ST7796S_SelectArea(st7796s_handle_t *handle, uint16_t startX, uint16_t startY, uint16_t endX, uint16_t endY) +{ + uint8_t tx_buf[4]; + + tx_buf[0] = (uint8_t)(startX >> 0x08U) & 0xFFU; + tx_buf[1] = (uint8_t)startX & 0xFFU; + tx_buf[2] = (uint8_t)(endX >> 0x08U) & 0xFFU; + tx_buf[3] = (uint8_t)endX & 0xFFU; + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_CASET, tx_buf, 4U)); + + tx_buf[0] = (uint8_t)(startY >> 0x08U) & 0xFFU; + tx_buf[1] = (uint8_t)startY & 0xFFU; + tx_buf[2] = (uint8_t)(endY >> 0x08U) & 0xFFU; + tx_buf[3] = (uint8_t)endY & 0xFFU; + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_RASET, tx_buf, 4U)); + + return kStatus_Success; +} + +status_t ST7796S_Config(st7796s_handle_t *handle, const st7796s_config_t *config) +{ + ST7796S_ERROR_CHECK(ST7796S_InvertDisplay(handle, config->invertDisplay)); + ST7796S_ERROR_CHECK(ST7796S_SetPixelFormat(handle, config->pixelFormat)); + ST7796S_ERROR_CHECK(ST7796S_SetTEConfig(handle, config->teConfig)); + + uint8_t tx_buf[1]; + + tx_buf[0] = (uint8_t)config->orientationMode; + if (!config->bgrFilter) + { + tx_buf[0] &= (uint8_t)(~0x08U); + } + + if (config->flipDisplay) + { + if ((config->orientationMode == kST7796S_Orientation90) || (config->orientationMode == kST7796S_Orientation270)) + { + tx_buf[0] ^= 0x80U; + } + else + { + tx_buf[0] ^= 0x40U; + } + } + + ST7796S_ERROR_CHECK(ST7796S_WriteCommand(handle, ST7796S_CMD_MADCTL, tx_buf, 1U)); + + handle->orientationMode = config->orientationMode; + + return kStatus_Success; +} + +status_t ST7796S_WritePixels(st7796s_handle_t *handle, uint16_t *pixels, uint32_t len) +{ + ST7796S_ERROR_CHECK(handle->xferOps->writeMemory(handle->xferOpsData, ST7796S_CMD_RAMWR, pixels, len * 2u)); + + return kStatus_Success; +} + +void ST7796S_SetMemoryDoneCallback(st7796s_handle_t *handle, dbi_mem_done_callback_t callback, void *userData) +{ + handle->xferOps->setMemoryDoneCallback(handle->xferOpsData, callback, userData); +} diff --git a/components/st7796s/fsl_st7796s.h b/components/st7796s/fsl_st7796s.h new file mode 100644 index 000000000..37e7738e0 --- /dev/null +++ b/components/st7796s/fsl_st7796s.h @@ -0,0 +1,248 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ST7796S_H_ +#define _FSL_ST7796S_H_ + +#include + +#include "fsl_dbi.h" + +/*! + * @addtogroup st7796s + * @{ + */ + +/* + * Change log: + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Panel driver preset. */ +typedef enum _st7796s_driver_preset +{ + kST7796S_DriverPresetLCDPARS035, /*!< Driving preset for LCD-PAR-S035. */ +} st7796s_driver_preset_t; + +/*! @brief Display Orientation. */ +typedef enum _st7796s_orientation_mode +{ + kST7796S_Orientation0 = 0x08U, /*!< Rotation 0 degrees */ + kST7796S_Orientation90 = 0x68U, /*!< Rotation 90 degrees */ + kST7796S_Orientation180 = 0xC8U, /*!< Rotation 180 degrees */ + kST7796S_Orientation270 = 0xA8U, /*!< Rotation 270 degrees */ +} st7796s_orientation_mode_t; + +/*! @brief Pixel format, does not affect interface width */ +typedef enum _st7796s_pixel_format +{ + kST7796S_PixelFormatRGB565 = 5U, /*!< Pixel format RGB565, 16bits per pixel */ + kST7796S_PixelFormatRGB666 = 6U, /*!< Pixel format RGB666, 18bits per pixel */ + kST7796S_PixelFormatRGB888 = 7U, /*!< Pixel format RGB888, 24bits per pixel, internally dithered to 18bits */ + kST7796S_PixelFormatRGB444 = 3U, /*!< Pixel format RGB444, 12bits per pixel */ +} st7796s_pixel_format_t; + +/*! @brief TE (tearing effect) output configuration */ +typedef enum _st7796s_te_config +{ + kST7796S_TEDisabled, /*!< TE output disabled (no output) */ + kST7796s_TEVSync, /*!< TE output enabled on VSync */ + kST7796S_TEHVSync, /*!< TE output enabled on both HSync and VSync */ +} st7796s_te_config_t; + +/*! @brief Panel configuration structure */ +typedef struct _st7796s_config +{ + st7796s_driver_preset_t driverPreset; /*!< Driver configuration preset */ + st7796s_pixel_format_t pixelFormat; /*!< Color format */ + st7796s_orientation_mode_t orientationMode; /*!< Display orientation */ + st7796s_te_config_t teConfig; /*!< TE line configuration */ + bool invertDisplay; /*!< Invert display color */ + bool flipDisplay; /*!< Mirror display image */ + bool bgrFilter; /*!< Use BGR color filter instead of RGB */ +} st7796s_config_t; + +/*! @brief ST7796S driver handle structure */ +typedef struct _st7796s_handle +{ + const dbi_xfer_ops_t *xferOps; /*!< Bus transfer operations. */ + void *xferOpsData; /*!< Data used for transfer operations. */ + st7796s_orientation_mode_t orientationMode; /*!< Current orientation mode */ +} st7796s_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ST7796S controller. + * + * This function performs a software reset and initialize the display driver using + * a preset configuration. This function does not turn on the display, application + * could perform the @ref ST7796S_EnableDisplay later after filling the frame buffer. + * + * @param handle ST7796S handle structure. + * @param config Pointer to the panel configuration structure. + * @param xferOps DBI interface transfer operation functions. + * @param xferOpsData Private data used by the DBI interface. + * + * @return This function returns kStatus_Success after successfully initialized. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_Init(st7796s_handle_t *handle, + const st7796s_config_t *config, + const dbi_xfer_ops_t *xferOps, + void *xferOpsData); + +/*! + * @brief Invert or restore display color. + * + * This function invert the display color to the panel. Invert is also related + * to the panel technology, for instance, an IPS panel will need the display color + * to be inverted, while traditional TFT panels will not. + * + * @param handle ST7796S handle structure. + * @param invert Whether to invert the display color. + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_InvertDisplay(st7796s_handle_t *handle, bool invert); + +/*! + * @brief Enable or disable the display output. + * + * This function enables or disables the panel driving output. When driving + * output is enabled, the panel will scanning out the frame buffer content. + * When driving output is disabled, the panel will display a blank screen + * depending the panel technology (un-driven state). + * + * @param handle ST7796S handle structure. + * @param enable Whether to enable driving output + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_EnableDisplay(st7796s_handle_t *handle, bool enable); + +/*! + * @brief Set display pixel format. + * + * This function set the pixel format of the controller. The controller supports one of the + * pixel formats defined in @ref st7796s_pixel_format_t. This does not affect the hardware interface selection. + * + * @param handle ST7796S handle structure. + * @param pixelFormat Pixel format to be set + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_SetPixelFormat(st7796s_handle_t *handle, st7796s_pixel_format_t pixelFormat); + +/*! + * @brief Configure the Tearing Effect (TE) line output. + * + * This function configures the TE line output to one of the following states: + * Disabled: No TE output + * VSync: TE asserts on the V-blanking periods only + * HVSync: TE asserts on both H-blanking periods and V-blanking periods + * Refer to @ref st7796s_te_config_t. + * + * @param handle ST7796S handle structure. + * @param teConfig TE line configuration to be set. + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_SetTEConfig(st7796s_handle_t *handle, st7796s_te_config_t teConfig); + +/*! + * @brief Set panel configurations. + * + * This function configures some vital parameters of the display panel. Please refer to + * @ref st7796s_config_t for available configuration items. + * + * @param handle ST7796S handle structure. + * @param config Pointer to the configuration structure. + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_Config(st7796s_handle_t *handle, const st7796s_config_t *config); + +/*! + * @brief Select draw area of the frame buffer. + * + * This function will set the internal write area to the rectangle specified by the coordinate. + * After the write area is set, pixels will be stored start from the top left of the area, and + * will be wrapped back to top left if more pixels are written to the frame memory. This function + * internally reset the write pointer to the start point. + * + * @param handle ST7796S handle structure. + * @param startX X start point + * @param startY Y start point + * @param endX X end point + * @param endY Y end point + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_SelectArea(st7796s_handle_t *handle, uint16_t startX, uint16_t startY, uint16_t endX, uint16_t endY); + +/*! + * @brief Write pixels to LCD frame buffer + * + * This function will perform a write to the internal frame buffer on the ST7796S controller. The start and end points + * are provided by previous call to the ST7796S, and will self-increment after each write. This function will return + * immediately after called, and user has to set a callback using @ref ST7796S_SetMemoryDoneCallback to check the + * result and get notified when the background DMA operation is completed. + * + * @param handle ST7796S handle structure. + * @param pixels buffer to be updated to the controller + * @param len pixel count. + * + * @return This function returns kStatus_Success after successfully executed. + * Appropriate kStatus_ prefixed errors will be given when an error occurred. + * Please refer to the corresponding modules for an specific error coding. + */ +status_t ST7796S_WritePixels(st7796s_handle_t *handle, uint16_t *pixels, uint32_t len); + +/*! + * @brief Set the memory access done callback. + * + * @param handle ST7796S handle structure. + * @param callback Callback function when the video memory operation finished. + * @ref ST7796S_WritePixels is non-blocking function, upper layer is notified + * by this callback function after transfer done. + * @param userData Parameter of @ref dbi_mem_done_callback_t. + */ +void ST7796S_SetMemoryDoneCallback(st7796s_handle_t *handle, dbi_mem_done_callback_t callback, void *userData); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif // _FSL_ST7796S_H_ \ No newline at end of file diff --git a/components/timer/fsl_adapter_ctimer.c b/components/timer/fsl_adapter_ctimer.c index 1ac2b5b7e..fd2a7d3df 100644 --- a/components/timer/fsl_adapter_ctimer.c +++ b/components/timer/fsl_adapter_ctimer.c @@ -153,7 +153,7 @@ uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle) assert(halTimerHandle); hal_timer_handle_struct_t *halTimerState = halTimerHandle; reserveCount = (uint32_t)MSEC_TO_COUNT((reserveMs), (halTimerState->timerClock_Hz)); - + retValue = COUNT_TO_USEC(((uint64_t)0xFFFFFFFF - (uint64_t)reserveCount), (uint64_t)halTimerState->timerClock_Hz); return (uint32_t)((retValue > 0xFFFFFFFFU) ? (0xFFFFFFFFU - reserveMs * 1000U) : (uint32_t)retValue); } diff --git a/components/timer/fsl_adapter_lptmr.c b/components/timer/fsl_adapter_lptmr.c index 7b930b215..8aba66842 100644 --- a/components/timer/fsl_adapter_lptmr.c +++ b/components/timer/fsl_adapter_lptmr.c @@ -113,6 +113,8 @@ hal_timer_status_t HAL_TimerInit(hal_timer_handle_t halTimerHandle, hal_timer_co irqId = mLptmrIrqId[halTimerState->instance]; LPTMR_GetDefaultConfig(&lptmrConfig); + + /* If the lptmr does not want to use the default clock source, clockSrcSelect need to be configured by users. */ lptmrConfig.prescalerClockSource = (lptmr_prescaler_clock_select_t)halTimerConfig->clockSrcSelect; #if (defined(LPTMR_USE_FREE_RUNNING) && (LPTMR_USE_FREE_RUNNING > 0)) @@ -180,7 +182,7 @@ uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle) assert(halTimerHandle); hal_timer_handle_struct_t *halTimerState = halTimerHandle; reserveCount = (uint32_t)MSEC_TO_COUNT((reserveMs), (halTimerState->timerClock_Hz)); - + retValue = COUNT_TO_USEC(((uint64_t)0xFFFFFFFF - (uint64_t)reserveCount), (uint64_t)halTimerState->timerClock_Hz); return (uint32_t)((retValue > 0xFFFFFFFFU) ? (0xFFFFFFFFU - reserveMs * 1000U) : (uint32_t)retValue); } @@ -189,28 +191,28 @@ uint32_t HAL_TimerGetCurrentTimerCount(hal_timer_handle_t halTimerHandle) { assert(halTimerHandle); hal_timer_handle_struct_t *halTimerState = halTimerHandle; - uint32_t flags = LPTMR_GetStatusFlags(s_LptmrBase[halTimerState->instance]); - uint32_t count = 0U; + uint32_t flags = LPTMR_GetStatusFlags(s_LptmrBase[halTimerState->instance]); + uint32_t count = 0U; #if !(defined(LPTMR_USE_FREE_RUNNING) && (LPTMR_USE_FREE_RUNNING > 0)) - if(flags != 0U) + if (flags != 0U) { /* If HAL_TimerGetCurrentTimerCount is called from masked interrupt * context, then it's possible the TCF flag is set, meaning the CNT * register is reset. In such case, the current count value is not * correct. We need to add the current compare value to the count * This is true only when TFC is not set (not free running) */ - count = (uint32_t)COUNT_TO_USEC((uint64_t)s_LptmrBase[halTimerState->instance]->CMR, - halTimerState->timerClock_Hz); + count = + (uint32_t)COUNT_TO_USEC((uint64_t)s_LptmrBase[halTimerState->instance]->CMR, halTimerState->timerClock_Hz); count += (uint32_t)COUNT_TO_USEC((uint64_t)LPTMR_GetCurrentTimerCount(s_LptmrBase[halTimerState->instance]), - halTimerState->timerClock_Hz); + halTimerState->timerClock_Hz); LPTMR_ClearStatusFlags(s_LptmrBase[halTimerState->instance], flags); } else #endif /* LPTMR_USE_FREE_RUNNING */ { count = (uint32_t)COUNT_TO_USEC((uint64_t)LPTMR_GetCurrentTimerCount(s_LptmrBase[halTimerState->instance]), - halTimerState->timerClock_Hz); + halTimerState->timerClock_Hz); } return count; diff --git a/components/timer/fsl_adapter_mrt.c b/components/timer/fsl_adapter_mrt.c index b5ad94016..076122cb0 100644 --- a/components/timer/fsl_adapter_mrt.c +++ b/components/timer/fsl_adapter_mrt.c @@ -140,7 +140,7 @@ uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle) assert(halTimerHandle); hal_timer_handle_struct_t *halTimerState = halTimerHandle; reserveCount = (uint32_t)MSEC_TO_COUNT((reserveMs), (halTimerState->timerClock_Hz)); - + retValue = COUNT_TO_USEC(((uint64_t)0xFFFFFFFF - (uint64_t)reserveCount), (uint64_t)halTimerState->timerClock_Hz); return (uint32_t)((retValue > 0xFFFFFFFFU) ? (0xFFFFFFFFU - reserveMs * 1000U) : (uint32_t)retValue); } diff --git a/components/timer/fsl_adapter_ostimer.c b/components/timer/fsl_adapter_ostimer.c index 5220ba91c..585e1b615 100644 --- a/components/timer/fsl_adapter_ostimer.c +++ b/components/timer/fsl_adapter_ostimer.c @@ -114,7 +114,7 @@ uint32_t HAL_TimerGetMaxTimeout(hal_timer_handle_t halTimerHandle) assert(halTimerHandle); hal_timer_handle_struct_t *halTimerState = halTimerHandle; reserveCount = (uint32_t)MSEC_TO_COUNT((reserveMs), (halTimerState->timerClock_Hz)); - + retValue = COUNT_TO_USEC(((uint64_t)0xFFFFFFFF - (uint64_t)reserveCount), (uint64_t)halTimerState->timerClock_Hz); return (uint32_t)((retValue > 0xFFFFFFFFU) ? (0xFFFFFFFFU - reserveMs * 1000U) : (uint32_t)retValue); } diff --git a/components/timer_manager/fsl_component_timer_manager.c b/components/timer_manager/fsl_component_timer_manager.c index 5be6108a1..5304cb0bd 100644 --- a/components/timer_manager/fsl_component_timer_manager.c +++ b/components/timer_manager/fsl_component_timer_manager.c @@ -107,11 +107,11 @@ typedef struct _timer_handle_struct_t /*! @brief State structure for timer manager. */ typedef struct _timermanager_state { - uint32_t mUsInTimerInterval; /*!< Timer intervl in microseconds */ - uint32_t mUsActiveInTimerInterval; /*!< Timer active intervl in microseconds */ - uint32_t previousTimeInUs; /*!< Previous timer count in microseconds */ - timer_handle_struct_t *timerHead; /*!< Timer list head */ - TIMER_HANDLE_DEFINE(halTimerHandle); /*!< Timer handle buffer */ + uint32_t mUsInTimerInterval; /*!< Timer intervl in microseconds */ + uint32_t mUsActiveInTimerInterval; /*!< Timer active intervl in microseconds */ + uint32_t previousTimeInUs; /*!< Previous timer count in microseconds */ + timer_handle_struct_t *timerHead; /*!< Timer list head */ + TIMER_HANDLE_DEFINE(halTimerHandle); /*!< Timer handle buffer */ #if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) TIME_STAMP_HANDLE_DEFINE(halTimeStampHandle); /*!< Time stamp handle buffer */ #endif @@ -314,9 +314,12 @@ TIMER_MANAGER_STATIC void TimersUpdate(bool updateRemainingUs, bool updateOnlyPo /*! ------------------------------------------------------------------------- * \brief Internal process of Timer Task + * \param[in] isInTaskContext TimerManagerTaskProcess can be called from other contexts than TimerManager task's, in + * such case, the active timers will be ignored as their callbacks must be called from + * TimerManager task context. * \return *---------------------------------------------------------------------------*/ -static void TimerManagerTaskProcess(void) +static void TimerManagerTaskProcess(bool isInTaskContext) { uint8_t timerType; timer_state_t state; @@ -342,8 +345,9 @@ static void TimerManagerTaskProcess(void) if (kTimerStateActive_c == state) { - /* This timer is active. Decrement it's countdown.. */ - if (0U >= th->remainingUs) + /* Active timers expiration will be processed only in the TimerManager task context + * this is to ensure the timers callbacks are called only in the task context */ + if ((0U >= th->remainingUs) && (isInTaskContext == true)) { /* If this is an interval timer, restart it. Otherwise, mark it as inactive. */ if (0U != (timerType & (uint32_t)(kTimerModeSingleShot))) @@ -447,7 +451,7 @@ static void TimersUpdateSyncTask(uint32_t remainingUs) static void TimersUpdateDirectSync(uint32_t remainingUs) { TimersCheckAndUpdate(remainingUs); - TimerManagerTaskProcess(); + TimerManagerTaskProcess(false); } /*! ------------------------------------------------------------------------- @@ -491,7 +495,7 @@ void TimerManagerTask(void *param) { #endif #endif - TimerManagerTaskProcess(); + TimerManagerTaskProcess(true); #if defined(OSA_USED) #if (defined(TM_COMMON_TASK_ENABLE) && (TM_COMMON_TASK_ENABLE > 0U)) @@ -648,12 +652,18 @@ void TM_Deinit(void) */ void TM_ExitLowpower(void) { + uint32_t remainingUs; + #if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) HAL_TimerExitLowpower((hal_timer_handle_t)s_timermanager.halTimerHandle); #endif #if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) HAL_TimeStampExitLowpower(s_timermanager.halTimerHandle); #endif + + remainingUs = HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle); + TimersUpdateSyncTask(remainingUs); + s_timermanager.previousTimeInUs = remainingUs; } /*! @@ -662,6 +672,15 @@ void TM_ExitLowpower(void) */ void TM_EnterLowpower(void) { + uint32_t remainingUs; + + /* Sync directly the timer manager ressources while bypassing the task + * This allows to update the timer manager ressources (timebase, timers, ...) under masked interrupts + * and make sure all timers are processed correctly */ + remainingUs = HAL_TimerGetCurrentTimerCount((hal_timer_handle_t)s_timermanager.halTimerHandle); + TimersUpdateDirectSync(remainingUs); + s_timermanager.previousTimeInUs = remainingUs; + #if (defined(TM_ENABLE_LOW_POWER_TIMER) && (TM_ENABLE_LOW_POWER_TIMER > 0U)) HAL_TimerEnterLowpower((hal_timer_handle_t)s_timermanager.halTimerHandle); #endif @@ -758,10 +777,24 @@ uint64_t TM_GetTimestamp(void) timer_status_t TM_Open(timer_handle_t timerHandle) { timer_handle_struct_t *timerState = timerHandle; + timer_handle_struct_t *th; assert(sizeof(timer_handle_struct_t) == TIMER_HANDLE_SIZE); assert(timerHandle); TIMER_ENTER_CRITICAL(); + th = s_timermanager.timerHead; + while (th != NULL) + { + /* Determine if timer element is already in list */ + if (th == timerState) + { + assert(0); + TIMER_EXIT_CRITICAL(); + return kStatus_TimerSuccess; + } + th = th->next; + } TimerSetTimerStatus(timerState, (uint8_t)kTimerStateInactive_c); + if (NULL == s_timermanager.timerHead) { timerState->next = NULL; diff --git a/components/timer_manager/fsl_component_timer_manager.h b/components/timer_manager/fsl_component_timer_manager.h index 3dfdef486..e9181f1fb 100644 --- a/components/timer_manager/fsl_component_timer_manager.h +++ b/components/timer_manager/fsl_component_timer_manager.h @@ -135,35 +135,31 @@ typedef enum _timer_status kStatus_TimerOutOfRange = 3, /*!< Out Of Range */ kStatus_TimerError = 4, /*!< Fail */ } timer_status_t; - #endif /**@brief Timer modes. */ -typedef enum _timer_mode -{ - kTimerModeSingleShot = 0x01U, /**< The timer will expire only once. */ - kTimerModeIntervalTimer = 0x02U, /**< The timer will restart each time it expires. */ - kTimerModeSetMinuteTimer = 0x04U, /**< The timer will one minute timer. */ - kTimerModeSetSecondTimer = 0x08U, /**< The timer will one second timer. */ - kTimerModeLowPowerTimer = 0x10U, /**< The timer will low power mode timer. */ - kTimerModeSetMicrosTimer = 0x20U, /**< The timer will low power mode timer with microsecond unit. */ -} timer_mode_t; +#define kTimerModeSingleShot 0x01U /**< The timer will expire only once. */ +#define kTimerModeIntervalTimer 0x02U /**< The timer will restart each time it expires. */ +#define kTimerModeSetMinuteTimer 0x04U /**< The timer will one minute timer. */ +#define kTimerModeSetSecondTimer 0x08U /**< The timer will one second timer. */ +#define kTimerModeLowPowerTimer 0x10U /**< The timer will low power mode timer. */ +#define kTimerModeSetMicrosTimer 0x20U /**< The timer will low power mode timer with microsecond unit. */ /**@brief Timer config. */ typedef struct _timer_config { - uint32_t srcClock_Hz; /**< The timer source clock frequency. */ - uint8_t instance; /*!< Hardware timer module instance, for example: if you want use FTM0,then the instance - is configured to 0, if you want use FTM2 hardware timer, then configure the instance - to 2, detail information please refer to the SOC corresponding RM. Invalid instance - value will cause initialization failure. */ + uint32_t srcClock_Hz; /**< The timer source clock frequency. */ + uint8_t instance; /*!< Hardware timer module instance, for example: if you want use FTM0,then the instance + is configured to 0, if you want use FTM2 hardware timer, then configure the instance + to 2, detail information please refer to the SOC corresponding RM. Invalid instance + value will cause initialization failure. */ uint8_t clockSrcSelect; /*!< Select clock source. It is timer clock select, if the lptmr does not to use the default clock source*/ #if (defined(TM_ENABLE_TIME_STAMP) && (TM_ENABLE_TIME_STAMP > 0U)) - uint32_t timeStampSrcClock_Hz; /**< The timer stamp source clock frequency. */ - uint8_t timeStampInstance; /**< Hardware timer module instance. This instance for time stamp */ + uint32_t timeStampSrcClock_Hz; /**< The timer stamp source clock frequency. */ + uint8_t timeStampInstance; /**< Hardware timer module instance. This instance for time stamp */ uint8_t timeStampClockSrcSelect; /*!< Select clock source. It is timer clock select, if the lptmr does not to use the default clock source*/ diff --git a/components/uart/fsl_adapter_lpuart.c b/components/uart/fsl_adapter_lpuart.c index fb0829c46..fb88ae374 100644 --- a/components/uart/fsl_adapter_lpuart.c +++ b/components/uart/fsl_adapter_lpuart.c @@ -681,7 +681,7 @@ static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_ lpuartConfig.rxIdleConfig = kLPUART_IdleCharacter2; #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ - status = LPUART_Init(s_LpuartAdapterBase[uart_config->instance], (const void *)&lpuartConfig, uart_config->srcClock_Hz); + status = LPUART_Init(s_LpuartAdapterBase[uart_config->instance], (const lpuart_config_t *)&lpuartConfig, uart_config->srcClock_Hz); if ((int32_t)kStatus_Success != status) { @@ -848,7 +848,7 @@ hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) #endif #else - HAL_UartInit(handle, &uartHandle->config); + (void)HAL_UartInit(handle, &uartHandle->config); #endif #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) @@ -1859,9 +1859,9 @@ hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, DMAMUX_Type *dmaMuxBases[] = DMAMUX_BASE_PTRS; DMAMUX_Init(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance]); DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel, - dmaMux->dma_dmamux_configure.tx_request); + (int32_t)dmaMux->dma_dmamux_configure.tx_request); DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel, - dmaMux->dma_dmamux_configure.rx_request); + (int32_t)dmaMux->dma_dmamux_configure.rx_request); DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel); DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel); #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) @@ -1871,10 +1871,10 @@ hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, /* Init the EDMA module */ #if defined(EDMA_BASE_PTRS) EDMA_Type *dmaBases[] = EDMA_BASE_PTRS; - IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL] = EDMA_CHN_IRQS; + IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; #elif (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U)) DMA_Type *dmaBases[] = DMA_BASE_PTRS; - IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL] = DMA_CHN_IRQS; + IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; #else DMA_Type *dmaBases[] = DMA_BASE_PTRS; IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; @@ -1885,7 +1885,9 @@ hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG edma_channel_config_t channelConfig = { .enableMasterIDReplication = true, +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) .securityLevel = kEDMA_ChannelSecurityLevelSecure, +#endif .protectionLevel = kEDMA_ChannelProtectionLevelPrivileged, }; @@ -1900,9 +1902,9 @@ hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, #if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure; EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel, - (dma_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux); + (int32_t)dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux); EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel, - (dma_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux); + (int32_t)dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux); #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) (void)memcpy(&uartDmaHandle->dma_channel_mux_configure, dmaConfig->dma_channel_mux_configure, sizeof(dma_channel_mux_configure_t)); diff --git a/components/uart/fsl_adapter_uart.h b/components/uart/fsl_adapter_uart.h index acfca7c50..5bb9f8269 100644 --- a/components/uart/fsl_adapter_uart.h +++ b/components/uart/fsl_adapter_uart.h @@ -299,7 +299,7 @@ extern "C" { * #UART_HANDLE_DEFINE(handle); * or * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; - * @param config Pointer to user-defined configuration structure. + * @param uart_config Pointer to user-defined configuration structure. * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. * @retval kStatus_HAL_UartSuccess UART initialization succeed */ @@ -395,7 +395,7 @@ hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, * The receive request is saved by the UART driver. * When the new data arrives, the receive request is serviced first. * When all data is received, the UART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. * * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking * cannot be used at the same time. @@ -414,7 +414,7 @@ hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, h * This function sends data using an interrupt method. This is a non-blocking function, which * returns directly without waiting for all data to be written to the TX register. When * all data is written to the TX register in the ISR, the UART driver calls the callback - * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. * * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking * cannot be used at the same time. @@ -516,7 +516,7 @@ hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, * The receive request is saved by the UART adapter. * When the new data arrives, the receive request is serviced first. * When all data is received, the UART adapter notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. * * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking * cannot be used at the same time. @@ -536,7 +536,7 @@ hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t * * This function sends data using an interrupt method. This is a non-blocking function, which * returns directly without waiting for all data to be written to the TX register. When * all data is written to the TX register in the ISR, the UART driver calls the callback - * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. * * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking * cannot be used at the same time. @@ -556,7 +556,7 @@ hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *dat * This function gets the number of bytes that have been received. * * @param handle UART handle pointer. - * @param count Receive bytes count. + * @param reCount Receive bytes count. * @retval kStatus_HAL_UartError An error occurred. * @retval kStatus_Success Get successfully through the parameter \p count. */ @@ -569,7 +569,7 @@ hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *re * register by using the interrupt method. * * @param handle UART handle pointer. - * @param count Send bytes count. + * @param seCount Send bytes count. * @retval kStatus_HAL_UartError An error occurred. * @retval kStatus_Success Get successfully through the parameter \p count. */ @@ -762,7 +762,7 @@ hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint3 * register by using the DMA method. * * @param handle UART handle pointer. - * @param count Send bytes count. + * @param seCount Send bytes count. * @retval kStatus_HAL_UartDmaError An error occurred. * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount. */ diff --git a/components/video/camera/device/fsl_camera_device.h b/components/video/camera/device/fsl_camera_device.h index 13c6cd9f2..2f0b722e6 100644 --- a/components/video/camera/device/fsl_camera_device.h +++ b/components/video/camera/device/fsl_camera_device.h @@ -32,9 +32,9 @@ typedef enum _camera_device_cmd #define CAMERA_LIGHT_MODE_HOME 4 #define CAMERA_LIGHT_MODE_NIGHT 5 - kCAMERA_DeviceSaturation, /*!< Saturation, pass in adjust value, such as -2, -1, 0, 1, 2... */ - kCAMERA_DeviceBrightness, /*!< Brightness, pass in adjust value, such as -2, -1, 0, 1, 2... */ - kCAMERA_DeviceContrast, /*!< Contrast, pass in adjust value, such as -2, -1, 0, 1, 2... */ + kCAMERA_DeviceSaturation, /*!< Saturation, pass in adjust value, such as -2, -1, 0, 1, 2... */ + kCAMERA_DeviceBrightness, /*!< Brightness, pass in adjust value, such as -2, -1, 0, 1, 2... */ + kCAMERA_DeviceContrast, /*!< Contrast, pass in adjust value, such as -2, -1, 0, 1, 2... */ kCAMERA_DeviceSpecialEffect, /*!< Special effect. */ #define CAMERA_SPECIAL_EFFECT_NORMAL 0 /* Normal. */ @@ -47,11 +47,11 @@ typedef enum _camera_device_cmd #define CAMERA_SPECIAL_EFFECT_OVER_EXPOSURE 7 /* OverExposure. */ #define CAMERA_SPECIAL_EFFECT_SOLARIZE 8 /* Solarize. */ - kCAMERA_DeviceNightMode, /*!< Night mode. */ -#define CAMERA_NIGHT_MODE_DISABLED 0 /* Disable. */ -#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY2 1 /* Use automatic frame rate, max reduction to 1/2 frame rate. */ -#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY4 4 /* Use automatic frame rate, max reduction to 1/4 frame rate. */ -#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY8 8 /* Use automatic frame rate, max reduction to 1/8 frame rate. */ + kCAMERA_DeviceNightMode, /*!< Night mode. */ +#define CAMERA_NIGHT_MODE_DISABLED 0 /* Disable. */ +#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY2 1 /* Use automatic frame rate, max reduction to 1/2 frame rate. */ +#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY4 4 /* Use automatic frame rate, max reduction to 1/4 frame rate. */ +#define CAMERA_NIGHT_MODE_AUTO_FR_DIVBY8 8 /* Use automatic frame rate, max reduction to 1/8 frame rate. */ } camera_device_cmd_t; /*! @brief Camera device operations. */ diff --git a/components/video/camera/device/ov7670/fsl_ov7670.c b/components/video/camera/device/ov7670/fsl_ov7670.c new file mode 100644 index 000000000..aae3f2b44 --- /dev/null +++ b/components/video/camera/device/ov7670/fsl_ov7670.c @@ -0,0 +1,761 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_video_common.h" +#include "fsl_camera.h" +#include "fsl_camera_device.h" +#include "fsl_ov7670.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define OV7670_SCCB_ADDR 0x21U + +#define OV7670_WriteReg(handle, reg, val) \ + SCCB_WriteReg(OV7670_SCCB_ADDR, kSCCB_RegAddr8Bit, (reg), (val), \ + ((ov7670_resource_t *)((handle)->resource))->i2cSendFunc) + +#define OV7670_ReadReg(handle, reg, val) \ + SCCB_ReadReg(OV7670_SCCB_ADDR, kSCCB_RegAddr8Bit, (reg), (val), \ + ((ov7670_resource_t *)((handle)->resource))->i2cReceiveFunc) + +#define OV7670_ModifyReg(handle, reg, clrMask, val) \ + SCCB_ModifyReg(OV7670_SCCB_ADDR, kSCCB_RegAddr8Bit, (reg), (clrMask), (val), \ + ((ov7670_resource_t *)((handle)->resource))->i2cReceiveFunc, \ + ((ov7670_resource_t *)((handle)->resource))->i2cSendFunc) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +status_t OV7670_Init(camera_device_handle_t *handle, const camera_config_t *config); + +status_t OV7670_Deinit(camera_device_handle_t *handle); + +status_t OV7670_Control(camera_device_handle_t *handle, camera_device_cmd_t cmd, int32_t arg); + +status_t OV7670_Start(camera_device_handle_t *handle); + +status_t OV7670_Stop(camera_device_handle_t *handle); + +status_t OV7670_InitExt(camera_device_handle_t *handle, const camera_config_t *config, const void *specialConfig); +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief OV7670 resolution options */ +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_VGA_DEFAULT = {140, 16}; +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QVGA_DEFAULT = {272, 16}; +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QQVGA_DEFAULT = {140, 16}; +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_CIF_DEFAULT = {140, 16}; +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QCIF_DEFAULT = {140, 16}; +ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QQCIF_DEFAULT = {140, 16}; + +/*! @brief Night mode initialization structure data */ +ov7670_output_format_config_t OV7670_FORMAT_RawBayerRGB = {0x01, 0x00, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_ProcessedBayerRGB = {0x05, 0x00, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_YUV422 = {0x00, 0x00, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_GRB422 = {0x04, 0x00, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_RGB565 = {0x04, 0xd0, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_RGB555 = {0x04, 0xf0, 0x00}; +ov7670_output_format_config_t OV7670_FORMAT_xRGB444 = {0x04, 0xd0, 0x2}; +ov7670_output_format_config_t OV7670_FORMAT_RGBx444 = {0x04, 0xd0, 0x3}; + +/*! @brief resolution initialization structure data */ +ov7670_resolution_config_t OV7670_RESOLUTION_VGA = {0x00, 0x00, 0x00, 0x3a, 0x35, 0x11, 0xf0, 0x02}; /*!< 640 x 480 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QVGA_ORIGINAL = {0x10, 0x00, 0x00, 0x3a, + 0x35, 0x11, 0xf0, 0x02}; /*!< 320 x 240 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QVGA = {0x10, 0x04, 0x19, 0x3a, 0x35, 0x11, 0xf1, 0x02}; /*!< 320 x 240 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QQVGA = {0x10, 0x04, 0x1A, 0x3a, 0x35, 0x22, 0xf2, 0x02}; /*!< 160 x 120 */ + +ov7670_resolution_config_t OV7670_RESOLUTION_CIF = {0x20, 0x08, 0x11, 0x3a, 0x35, 0x11, 0xf1, 0x02}; /*!< 352 x 288 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QCIF_ORIGINAL = {0x21, 0x08, 0x11, 0x3a, + 0x35, 0x11, 0xf1, 0x02}; /*!< 176 x 144 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QCIF = {0x28, 0x00, 0x11, 0x3a, 0x35, 0x11, 0xf1, 0x02}; /*!< 176 x 144 */ +ov7670_resolution_config_t OV7670_RESOLUTION_QQCIF = {0x28, 0x0c, 0x12, 0x3a, 0x35, 0x22, 0xf2, 0x02}; /*!< 88 x 72 */ + +/*! @brief Special effects configuration initialization structure data */ +ov7670_windowing_config_t OV7670_WINDOW_VGA = {0x36, 0x13, 0x01, 0x0a, 0x02, 0x7a}; +ov7670_windowing_config_t OV7670_WINDOW_QVGA = {0x80, 0x15, 0x03, 0x00, 0x03, 0x7b}; +ov7670_windowing_config_t OV7670_WINDOW_QQVGA = {0x64, 0x16, 0x04, 0x0a, 0x03, 0x7b}; +ov7670_windowing_config_t OV7670_WINDOW_CIF = {0x12, 0x15, 0x0b, 0x0a, 0x03, 0x7b}; +ov7670_windowing_config_t OV7670_WINDOW_QCIF = {0x80, 0x39, 0x03, 0x0a, 0x03, 0x7b}; +ov7670_windowing_config_t OV7670_WINDOW_QQCIF = {0x64, 0x3a, 0x03, 0x06, 0x03, 0x7b}; + +/*! @brief Frame rate initialization structure data */ +ov7670_frame_rate_config_t OV7670_30FPS_26MHZ_XCLK = {0x80, 0x0a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_25FPS_26MHZ_XCLK = {0x80, 0x0a, 0x00, 0x00, 0x99, 0x00}; +ov7670_frame_rate_config_t OV7670_15FPS_26MHZ_XCLK = {0x00, 0x0a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_14FPS_26MHZ_XCLK = {0x00, 0x0a, 0x00, 0x00, 0x46, 0x00}; + +ov7670_frame_rate_config_t OV7670_30FPS_24MHZ_XCLK = {0x80, 0x0a, 0x00, 0x00, 0x00, 0x00}; +ov7670_frame_rate_config_t OV7670_25FPS_24MHZ_XCLK = {0x80, 0x0a, 0x00, 0x00, 0x66, 0x00}; +ov7670_frame_rate_config_t OV7670_15FPS_24MHZ_XCLK = {0x00, 0x0a, 0x00, 0x00, 0x00, 0x00}; +ov7670_frame_rate_config_t OV7670_14FPS_24MHZ_XCLK = {0x00, 0x0a, 0x00, 0x00, 0x1a, 0x00}; + +ov7670_frame_rate_config_t OV7670_30FPS_13MHZ_XCLK = {0x00, 0x4a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_25FPS_13MHZ_XCLK = {0x00, 0x4a, 0x00, 0x00, 0x99, 0x00}; +ov7670_frame_rate_config_t OV7670_15FPS_13MHZ_XCLK = {0x01, 0x4a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_14FPS_13MHZ_XCLK = {0x01, 0x4a, 0x00, 0x00, 0x46, 0x00}; + +ov7670_frame_rate_config_t OV7670_30FPS_12MHZ_XCLK = {0x00, 0x4a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_25FPS_12MHZ_XCLK = {0x00, 0x4a, 0x00, 0x00, 0x66, 0x00}; +ov7670_frame_rate_config_t OV7670_15FPS_12MHZ_XCLK = {0x01, 0x4a, 0x00, 0x00, 0x2b, 0x00}; +ov7670_frame_rate_config_t OV7670_14FPS_12MHZ_XCLK = {0x01, 0x4a, 0x00, 0x00, 0x46, 0x00}; + +/*! @brief Night mode initialization structure data */ +ov7670_night_mode_config_t OV7670_NIGHT_MODE_DISABLED = {0x00}; +ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY2 = {0xa0}; +ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY4 = {0xc0}; +ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY8 = {0xe0}; + +/*! @brief Banding filter initialization structure data */ +ov7670_filter_config_t OV7670_FILTER_DISABLED = {0x00, 0x98, 0x7f, 0x02, 0x03, 0x02}; +ov7670_filter_config_t OV7670_FILTER_30FPS_60HZ = {0x20, 0x98, 0x7f, 0x02, 0x03, 0x02}; +ov7670_filter_config_t OV7670_FILTER_15FPS_60HZ = {0x20, 0x4c, 0x3f, 0x05, 0x07, 0x02}; +ov7670_filter_config_t OV7670_FILTER_25FPS_50HZ = {0x20, 0x98, 0x7f, 0x03, 0x03, 0x0a}; +ov7670_filter_config_t OV7670_FILTER_14FPS_50HZ = {0x20, 0x4c, 0x3f, 0x06, 0x07, 0x0a}; +ov7670_filter_config_t OV7670_FILTER_30FPS_60HZ_AUTO_LIGHT_FREQ_DETECT = {0x20, 0x98, 0x7f, 0x02, 0x03, 0x12}; +ov7670_filter_config_t OV7670_FILTER_15FPS_60HZ_AUTO_LIGHT_FREQ_DETECT = {0x20, 0x4c, 0x3f, 0x05, 0x07, 0x12}; +ov7670_filter_config_t OV7670_FILTER_25FPS_50HZ_AUTO_LIGHT_FREQ_DETECT = {0x20, 0x98, 0x7f, 0x03, 0x03, 0x1a}; +ov7670_filter_config_t OV7670_FILTER_14FPS_50HZ_AUTO_LIGHT_FREQ_DETECT = {0x20, 0x4c, 0x3f, 0x06, 0x07, 0x1a}; + +/*! @brief White balance initialization structure data */ +ov7670_white_balance_config_t OV7670_WHITE_BALANCE_DEFAULT = {0x02, 0x9a, 0xc0, 0x55, 0x02, 0x14, + 0xf0, 0x45, 0x61, 0x51, 0x79, 0x08}; +ov7670_white_balance_config_t OV7670_WHITE_BALANCE_DISABLED = {0x00, 0x9a, 0xc0, 0x55, 0x02, 0x14, + 0xf0, 0x45, 0x61, 0x51, 0x79, 0x00}; +ov7670_white_balance_config_t OV7670_WHITE_BALANCE_SIMPLE = {0x02, 0x9f, 0x10, 0x55, 0x02, 0x14, + 0xf0, 0x45, 0x61, 0x51, 0x79, 0x08}; + +/*! @brief Light mode configuration initialization structure data */ +ov7670_light_mode_config_t OV7670_LIGHT_MODE_DISABLED = {0x05, 0x0a, 0x08, 0x00, 0x08}; +ov7670_light_mode_config_t OV7670_LIGHT_MODE_AUTO = {0xc5, 0x3a, 0x08, 0x00, 0x08}; +ov7670_light_mode_config_t OV7670_LIGHT_MODE_SUNNY = {0xc5, 0x6a, 0x5a, 0x00, 0x5c}; +ov7670_light_mode_config_t OV7670_LIGHT_MODE_CLOUDY = {0xc5, 0x0a, 0x58, 0x00, 0x60}; +ov7670_light_mode_config_t OV7670_LIGHT_MODE_OFFICE = {0xc5, 0x2a, 0x84, 0x00, 0x4c}; +ov7670_light_mode_config_t OV7670_LIGHT_MODE_HOME = {0xc5, 0x1a, 0x96, 0x00, 0x40}; + +/*! @brief Color saturation configuration initialization structure data */ +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_4PLUS = {0xc0, 0xc0, 0x00, 0x33, 0x8d, 0xc0, 0x9e, 0x02}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_3PLUS = {0x99, 0x99, 0x00, 0x28, 0x71, 0x99, 0x9e, 0x02}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_2PLUS = {0xc0, 0xc0, 0x00, 0x33, 0x8d, 0xc0, 0x9e, 0x00}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_1PLUS = {0x99, 0x99, 0x00, 0x28, 0x71, 0x99, 0x9e, 0x00}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_0 = {0x80, 0x80, 0x00, 0x22, 0x5e, 0x80, 0x9e, 0x00}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_DEFAULT = {0x40, 0x34, 0x0c, 0x17, 0x29, 0x40, 0x1e, 0x00}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_1MINUS = {0x66, 0x66, 0x00, 0x1b, 0x4b, 0x66, 0x9e, 0x00}; +ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_2MINUS = {0x40, 0x40, 0x00, 0x11, 0x2f, 0x40, 0x9e, 0x00}; + +/*! @brief Special effects configuration initialization structure data */ +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_ANTIQUE = {0x18, 0, 255}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_SEPHIA = {0x18, 16, 146}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BLUISH = {0x18, 240, 146}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_GREENISH = {0x18, 0, 30}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_REDISH = {0x18, 90, 240}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BW = {0x18, 110, 110}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_NEGATIVE = {0x28, 0x80, 0x80}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BW_NEGATIVE = {0x38, 110, 110}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_NORMAL = {0x0c, 0x80, 0x80}; +ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_DISABLED = {0x08, 0x80, 0x80}; + +/*! @brief Special effects configuration initialization structure data */ +ov7670_gamma_curve_slope_config_t OV7670_GAMMA_CURVE_SLOPE_DEFAULT = {0x24, 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, + 0x60, 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe5}; +ov7670_gamma_curve_slope_config_t OV7670_GAMMA_CURVE_SLOPE1 = {0x20, 0x10, 0x1e, 0x35, 0x5a, 0x69, 0x76, 0x80, + 0x88, 0x8f, 0x96, 0xa3, 0xaf, 0xc4, 0xd7, 0xe8}; + +const camera_device_operations_t ov7670_ops = { + .init = OV7670_Init, + .deinit = OV7670_Deinit, + .start = OV7670_Start, + .stop = OV7670_Stop, + .control = OV7670_Control, + .init_ext = OV7670_InitExt, +}; +/******************************************************************************* + * Code + ******************************************************************************/ + +static void OV7670_DelayMs(uint32_t ms) +{ + VIDEO_DelayMs(ms); +} + +status_t OV7670_CameraInit(camera_device_handle_t *handle, const ov7670_config_t *config) +{ + uint8_t u8TempVal0, u8TempVal1; + + /* Reset Device */ + (void)OV7670_WriteReg(handle, OV7670_COM7_REG, 0x80); + /* wait for a least 1ms */ + OV7670_DelayMs(5); /* 5ms */ + /* Read product ID nuumber MSB */ + if (OV7670_ReadReg(handle, OV7670_PID_REG, &u8TempVal0) != kStatus_Success) + { + return kStatus_Fail; + } + /* Read product ID nuumber MSB */ + if (OV7670_ReadReg(handle, OV7670_VER_REG, &u8TempVal1) != kStatus_Success) + { + return kStatus_Fail; + } + if ((u8TempVal0 != OV7670_PID_NUM) && (u8TempVal1 != OV7670_VER_NUM)) + { + return kStatus_Fail; + } + + /* NULL pointer means default setting. */ + if (config == NULL) + { + /* Reset Device */ + (void)OV7670_WriteReg(handle, OV7670_COM7_REG, 0x80); + /* wait for a bit */ + OV7670_DelayMs(5); /* 5ms */ + } + else + { + (void)OV7670_Configure(handle, config); + } + /* MVFP */ + if (OV7670_ReadReg(handle, OV7670_MVFP_REG, &u8TempVal1) != kStatus_Success) + { + return kStatus_Fail; + } + if (0U == (u8TempVal1 & OV7670_MVFP_MIRROR_MASK)) + { + u8TempVal1 |= OV7670_MVFP_MIRROR_MASK; + (void)OV7670_WriteReg(handle, OV7670_MVFP_REG, u8TempVal1); + } + return kStatus_Success; +} + +status_t OV7670_ContrastAdjustment(camera_device_handle_t *handle, uint8_t val) +{ + status_t status = kStatus_Success; + + status = OV7670_WriteReg(handle, OV7670_CONTRAS_CENTER_REG, 0x80); + status = OV7670_ModifyReg(handle, OV7670_MTXS_REG, 0x80, 0x00); + status = OV7670_WriteReg(handle, OV7670_CONTRAS_REG, val); + return status; +} + +status_t OV7670_BrightnessAdjustment(camera_device_handle_t *handle, uint8_t val) +{ + status_t status = kStatus_Success; + + status = OV7670_WriteReg(handle, OV7670_BRIGHT_REG, val); + + return status; +} + +status_t OV7670_Configure(camera_device_handle_t *handle, const ov7670_config_t *config) +{ + status_t status = kStatus_Success; + + ov7670_windowing_config_t *windowConfig; + (void)OV7670_OutputFormat(handle, config->outputFormat); + (void)OV7670_Resolution(handle, config->resolution); + + switch ((video_resolution_t)config->resolution) + { + case kVIDEO_ResolutionVGA: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_VGA; + break; + case kVIDEO_ResolutionQVGA: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_QVGA; + break; + case kVIDEO_ResolutionQQVGA: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_QQVGA; + break; + case kVIDEO_ResolutionCIF: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_CIF; + break; + case kVIDEO_ResolutionQCIF: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_QCIF; + break; + case kVIDEO_ResolutionQQCIF: + windowConfig = (ov7670_windowing_config_t *)&OV7670_WINDOW_QQCIF; + break; + default: + status = kStatus_Fail; /* not supported resolution */ + break; + } + + if (kStatus_Success != status) + { + return status; + } + + (void)OV7670_SetWindow(handle, windowConfig); + (void)OV7670_FrameRateAdjustment(handle, config->frameRate); + + /* configure Hsync/Vsync for EZH */ + (void)OV7670_WriteReg(handle, OV7670_COM10_REG, 0x20); /* no PCLK toggle during Hblank, mandatory! */ + + if (config->advancedConfig == NULL) + { + (void)OV7670_BandingFilterSelection(handle, (ov7670_filter_config_t *)&OV7670_FILTER_25FPS_50HZ); + (void)OV7670_NightMode(handle, (ov7670_night_mode_config_t *)&OV7670_NIGHT_MODE_DISABLED); + (void)OV7670_WhiteBalance(handle, (ov7670_white_balance_config_t *)&OV7670_WHITE_BALANCE_SIMPLE); + (void)OV7670_LightMode(handle, (ov7670_light_mode_config_t *)&OV7670_LIGHT_MODE_DISABLED); + (void)OV7670_ColorSaturation(handle, (ov7670_color_saturation_config_t *)&OV7670_COLOR_SATURATION_2PLUS); + (void)OV7670_SpecialEffects(handle, (ov7670_special_effect_config_t *)&OV7670_SPECIAL_EFFECT_DISABLED); + (void)OV7670_GammaCurveSlope(handle, (ov7670_gamma_curve_slope_config_t *)&OV7670_GAMMA_CURVE_SLOPE_DEFAULT); + } + else + { + (void)OV7670_BandingFilterSelection(handle, config->advancedConfig->filter); + (void)OV7670_NightMode(handle, config->advancedConfig->nightMode); + (void)OV7670_WhiteBalance(handle, config->advancedConfig->whiteBalance); + (void)OV7670_LightMode(handle, config->advancedConfig->lightMode); + (void)OV7670_ColorSaturation(handle, config->advancedConfig->colorSaturation); + (void)OV7670_SpecialEffects(handle, config->advancedConfig->specialEffect); + (void)OV7670_GammaCurveSlope(handle, config->advancedConfig->gammaCurveSlope); + } + + (void)OV7670_ContrastAdjustment(handle, config->contrast); + (void)OV7670_BrightnessAdjustment(handle, config->brightness); + (void)OV7670_WriteReg(handle, 0xb0, 0x84); /*!< because of colors */ + (void)OV7670_WriteReg(handle, 0xff, 0xff); + + return kStatus_Success; +} + +status_t OV7670_OutputFormat(camera_device_handle_t *handle, const ov7670_output_format_config_t *outputFormatConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_COM7_REG, 0x05, outputFormatConfig->com7); + (void)OV7670_ModifyReg(handle, OV7670_RGB444_REG, 0x03, outputFormatConfig->rgb444); + (void)OV7670_ModifyReg(handle, OV7670_COM15_REG, 0x30, outputFormatConfig->com15); + + return kStatus_Success; +} + +status_t OV7670_Resolution(camera_device_handle_t *handle, uint32_t resolution) +{ + status_t status = kStatus_Success; + + ov7670_resolution_config_t *resolution_config; + switch ((video_resolution_t)resolution) + { + case kVIDEO_ResolutionVGA: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_VGA; + break; + case kVIDEO_ResolutionQVGA: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_QVGA; + break; + case kVIDEO_ResolutionQQVGA: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_QQVGA; + break; + case kVIDEO_ResolutionCIF: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_CIF; + break; + case kVIDEO_ResolutionQCIF: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_QCIF; + break; + case kVIDEO_ResolutionQQCIF: + resolution_config = (ov7670_resolution_config_t *)&OV7670_RESOLUTION_QQCIF; + break; + default: + status = kStatus_Fail; /*!< not supported resolution */ + break; + } + + if (kStatus_Success != status) + { + return status; + } + + (void)OV7670_ModifyReg(handle, OV7670_COM7_REG, 0x38, resolution_config->com7); + (void)OV7670_ModifyReg(handle, OV7670_COM3_REG, 0x0c, resolution_config->com3); + (void)OV7670_WriteReg(handle, OV7670_COM14_REG, resolution_config->com14); + (void)OV7670_WriteReg(handle, OV7670_SCALING_XSC_REG, resolution_config->scalingXsc); + (void)OV7670_WriteReg(handle, OV7670_SCALING_YSC_REG, resolution_config->scalingYsc); + (void)OV7670_ModifyReg(handle, OV7670_SCALING_DCWCTR_REG, 0x33, resolution_config->scalingDcwctr); + (void)OV7670_WriteReg(handle, OV7670_SCALING_PCLK_DIV_REG, resolution_config->scalingPclkDiv); + (void)OV7670_WriteReg(handle, OV7670_SCALING_PCLK_DELAY_REG, resolution_config->scalingPclkDelay); + + /* Autotomatically set output window after resolution change */ + (void)OV7670_ModifyReg(handle, OV7670_TSLB_REG, 0x01, 0x01); + + return kStatus_Success; +} + +status_t OV7670_SetWindow(camera_device_handle_t *handle, const ov7670_windowing_config_t *windowingConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_TSLB_REG, 0x01, 0x00); + + (void)OV7670_WriteReg(handle, OV7670_HREF_REG, windowingConfig->href); + (void)OV7670_WriteReg(handle, OV7670_HSTART_REG, windowingConfig->hstart); + (void)OV7670_WriteReg(handle, OV7670_HSTOP_REG, windowingConfig->hstop); + (void)OV7670_WriteReg(handle, OV7670_VREF_REG, windowingConfig->vref); + (void)OV7670_WriteReg(handle, OV7670_VSTART_REG, windowingConfig->vstart); + (void)OV7670_WriteReg(handle, OV7670_VSTOP_REG, windowingConfig->vstop); + + return kStatus_Success; +} + +status_t OV7670_FrameRateAdjustment(camera_device_handle_t *handle, const ov7670_frame_rate_config_t *frameRateConfig) +{ + (void)OV7670_WriteReg(handle, OV7670_CLKRC_REG, frameRateConfig->clkrc); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_DBLV_REG, frameRateConfig->dblv); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_EXHCH_REG, frameRateConfig->exhch); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_EXHCL_REG, frameRateConfig->exhcl); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_DM_LNL_REG, frameRateConfig->dm_lnl); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_DM_LNH_REG, frameRateConfig->dm_lnh); + OV7670_DelayMs(2); + + return kStatus_Success; +} + +status_t OV7670_NightMode(camera_device_handle_t *handle, const ov7670_night_mode_config_t *nightModeConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_COM11_REG, 0xe0, nightModeConfig->com11); + + OV7670_DelayMs(2); + + return kStatus_Success; +} + +status_t OV7670_BandingFilterSelection(camera_device_handle_t *handle, const ov7670_filter_config_t *filterConfig) +{ + (void)OV7670_WriteReg(handle, OV7670_BD50ST_REG, filterConfig->bd50st); /*!< 50Hz banding filter */ + (void)OV7670_WriteReg(handle, OV7670_BD60ST_REG, filterConfig->bd60st); /*!< 60Hz banding filter */ + (void)OV7670_WriteReg(handle, OV7670_BD50MAX_REG, filterConfig->bd50max); /*!< x step for 50hz */ + (void)OV7670_WriteReg(handle, OV7670_BD60MAX_REG, filterConfig->bd60max); /*!< y step for 60hz */ + (void)OV7670_ModifyReg(handle, OV7670_COM11_REG, 0x1a, filterConfig->com11); /*!< Automatic Detect banding filter */ + (void)OV7670_ModifyReg(handle, OV7670_COM8_REG, 0x20, filterConfig->com8); /*!< banding filter enable */ + + return kStatus_Success; +} + +status_t OV7670_WhiteBalance(camera_device_handle_t *handle, const ov7670_white_balance_config_t *whiteBalanceConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_COM8_REG, 0x02, whiteBalanceConfig->com8); /*!< AWB on/off */ + (void)OV7670_WriteReg(handle, OV7670_AWBCTR0_REG, whiteBalanceConfig->awbctr0); + (void)OV7670_WriteReg(handle, OV7670_AWBCTR1_REG, whiteBalanceConfig->awbctr1); + (void)OV7670_WriteReg(handle, OV7670_AWBCTR2_REG, whiteBalanceConfig->awbctr2); + (void)OV7670_WriteReg(handle, OV7670_AWBCTR3_REG, whiteBalanceConfig->awbctr3); + (void)OV7670_WriteReg(handle, OV7670_AWBC1_REG, whiteBalanceConfig->awbc1); + (void)OV7670_WriteReg(handle, OV7670_AWBC2_REG, whiteBalanceConfig->awbc2); + (void)OV7670_WriteReg(handle, OV7670_AWBC3_REG, whiteBalanceConfig->awbc3); + (void)OV7670_WriteReg(handle, OV7670_AWBC4_REG, whiteBalanceConfig->awbc4); + (void)OV7670_WriteReg(handle, OV7670_AWBC5_REG, whiteBalanceConfig->awbc5); + (void)OV7670_WriteReg(handle, OV7670_AWBC6_REG, whiteBalanceConfig->awbc6); + (void)OV7670_WriteReg(handle, 0x59, 0x91); + (void)OV7670_WriteReg(handle, 0x5a, 0x94); + (void)OV7670_WriteReg(handle, 0x5b, 0xaa); + (void)OV7670_WriteReg(handle, 0x5c, 0x71); + (void)OV7670_WriteReg(handle, 0x5d, 0x8d); + (void)OV7670_WriteReg(handle, 0x5e, 0x0f); + (void)OV7670_WriteReg(handle, 0x5f, 0xf0); + (void)OV7670_WriteReg(handle, 0x60, 0xf0); + (void)OV7670_WriteReg(handle, 0x61, 0xf0); + (void)OV7670_ModifyReg(handle, OV7670_COM16_REG, 0x08, whiteBalanceConfig->com16); /*!< AWB gain on */ + + return kStatus_Success; +} + +status_t OV7670_LightMode(camera_device_handle_t *handle, const ov7670_light_mode_config_t *lightModeConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_COM8_REG, 0xc5, lightModeConfig->com8); + (void)OV7670_ModifyReg(handle, OV7670_COM9_REG, 0x7a, lightModeConfig->com9); + (void)OV7670_WriteReg(handle, OV7670_RED_REG, lightModeConfig->red); + (void)OV7670_WriteReg(handle, OV7670_GGAIN_REG, lightModeConfig->green); + (void)OV7670_WriteReg(handle, OV7670_BLUE_REG, lightModeConfig->blue); + (void)OV7670_WriteReg(handle, OV7670_GAIN_REG, 0x00); + OV7670_DelayMs(2); + + /*!< Exposure value */ + (void)OV7670_WriteReg(handle, OV7670_AECH_REG, 0x00); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_AECHH_REG, 0x00); + OV7670_DelayMs(2); + (void)OV7670_ModifyReg(handle, OV7670_COM1_REG, 0x3, 0x00); + OV7670_DelayMs(2); + /*!< AGC/AEC stable operation region configuration */ + (void)OV7670_WriteReg(handle, OV7670_AEW_REG, 0x75); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_AEB_REG, 0x63); + OV7670_DelayMs(2); + (void)OV7670_WriteReg(handle, OV7670_VPT_REG, 0xd4); + OV7670_DelayMs(2); + + return kStatus_Success; +} + +status_t OV7670_ColorSaturation(camera_device_handle_t *handle, + const ov7670_color_saturation_config_t *colorSaturationConfig) +{ + (void)OV7670_WriteReg(handle, OV7670_MTX1_REG, colorSaturationConfig->mtx1); + (void)OV7670_WriteReg(handle, OV7670_MTX2_REG, colorSaturationConfig->mtx2); + (void)OV7670_WriteReg(handle, OV7670_MTX3_REG, colorSaturationConfig->mtx3); + (void)OV7670_WriteReg(handle, OV7670_MTX4_REG, colorSaturationConfig->mtx4); + (void)OV7670_WriteReg(handle, OV7670_MTX5_REG, colorSaturationConfig->mtx5); + (void)OV7670_WriteReg(handle, OV7670_MTX6_REG, colorSaturationConfig->mtx6); + (void)OV7670_WriteReg(handle, OV7670_MTXS_REG, colorSaturationConfig->mtxs); + (void)OV7670_ModifyReg(handle, OV7670_COM16_REG, 0x02, colorSaturationConfig->com16); + + return kStatus_Success; +} + +status_t OV7670_SpecialEffects(camera_device_handle_t *handle, + const ov7670_special_effect_config_t *specialEffectConfig) +{ + (void)OV7670_ModifyReg(handle, OV7670_TSLB_REG, 0xfe, specialEffectConfig->tslb); + (void)OV7670_WriteReg(handle, OV7670_MANU_REG, specialEffectConfig->manu); + (void)OV7670_WriteReg(handle, OV7670_MANV_REG, specialEffectConfig->manv); + + return kStatus_Success; +} + +status_t OV7670_SetWindowByCoordinates(camera_device_handle_t *handle, + ov7670_window_start_point_t *startPoint, + uint32_t resolution) +{ + uint16_t u16Temp, u16Href, u16Vref; + + (void)OV7670_ModifyReg(handle, OV7670_TSLB_REG, 0x01, 0x00); + + u16Temp = startPoint->hstartCoordinate + FSL_VIDEO_EXTRACT_WIDTH(resolution); + u16Href = (u16Temp & 0x07U); + u16Href = u16Href << 3; + u16Href |= (startPoint->hstartCoordinate & 0x07U); + u16Href |= 0xc0U; + (void)OV7670_WriteReg(handle, OV7670_HREF_REG, (uint8_t)u16Href); + u16Temp = u16Temp >> 3; + (void)OV7670_WriteReg(handle, OV7670_HSTOP_REG, (uint8_t)u16Temp); + u16Temp = ((startPoint->hstartCoordinate & 0x7f8U) >> 3); + (void)OV7670_WriteReg(handle, OV7670_HSTART_REG, (uint8_t)u16Temp); + + u16Temp = startPoint->vstartCoordinate + FSL_VIDEO_EXTRACT_HEIGHT(resolution); + u16Vref = (u16Temp & 0x03U); + u16Vref = u16Vref << 2; + u16Vref |= (startPoint->vstartCoordinate & 0x03U); + u16Vref &= 0xF0U; + (void)OV7670_ModifyReg(handle, OV7670_VREF_REG, 0xc0, (uint8_t)u16Vref); + u16Temp = u16Temp >> 2; + (void)OV7670_WriteReg(handle, OV7670_VSTOP_REG, (uint8_t)u16Temp); + u16Temp = ((startPoint->vstartCoordinate & 0x3fcU) >> 2); + (void)OV7670_WriteReg(handle, OV7670_VSTART_REG, (uint8_t)u16Temp); + + return kStatus_Success; +} + +status_t OV7670_GammaCurveSlope(camera_device_handle_t *handle, + const ov7670_gamma_curve_slope_config_t *gammaCurveSlopeConfig) +{ + (void)OV7670_WriteReg(handle, OV7670_SLOP_REG, gammaCurveSlopeConfig->slope); + (void)OV7670_WriteReg(handle, OV7670_GAM1_REG, gammaCurveSlopeConfig->gam1); + (void)OV7670_WriteReg(handle, OV7670_GAM2_REG, gammaCurveSlopeConfig->gam2); + (void)OV7670_WriteReg(handle, OV7670_GAM3_REG, gammaCurveSlopeConfig->gam3); + (void)OV7670_WriteReg(handle, OV7670_GAM4_REG, gammaCurveSlopeConfig->gam4); + (void)OV7670_WriteReg(handle, OV7670_GAM5_REG, gammaCurveSlopeConfig->gam5); + (void)OV7670_WriteReg(handle, OV7670_GAM6_REG, gammaCurveSlopeConfig->gam6); + (void)OV7670_WriteReg(handle, OV7670_GAM7_REG, gammaCurveSlopeConfig->gam7); + (void)OV7670_WriteReg(handle, OV7670_GAM8_REG, gammaCurveSlopeConfig->gam8); + (void)OV7670_WriteReg(handle, OV7670_GAM9_REG, gammaCurveSlopeConfig->gam9); + (void)OV7670_WriteReg(handle, OV7670_GAM10_REG, gammaCurveSlopeConfig->gam10); + (void)OV7670_WriteReg(handle, OV7670_GAM11_REG, gammaCurveSlopeConfig->gam11); + (void)OV7670_WriteReg(handle, OV7670_GAM12_REG, gammaCurveSlopeConfig->gam12); + (void)OV7670_WriteReg(handle, OV7670_GAM13_REG, gammaCurveSlopeConfig->gam13); + (void)OV7670_WriteReg(handle, OV7670_GAM14_REG, gammaCurveSlopeConfig->gam14); + (void)OV7670_WriteReg(handle, OV7670_GAM15_REG, gammaCurveSlopeConfig->gam15); + + return kStatus_Success; +} + +void OV7670_GetDefaultConfig(ov7670_config_t *config) +{ + config->outputFormat = (ov7670_output_format_config_t *)&OV7670_FORMAT_RGB565; + config->resolution = (uint32_t)kVIDEO_ResolutionQQVGA; + config->frameRate = (ov7670_frame_rate_config_t *)&OV7670_25FPS_12MHZ_XCLK; + config->contrast = 0x30; + config->brightness = 0x10; + config->advancedConfig = NULL; +} + +status_t OV7670_Init(camera_device_handle_t *handle, const camera_config_t *config) +{ + status_t status; + ov7670_resource_t *resource = (ov7670_resource_t *)(handle->resource); + ov7670_config_t cameraConfig; + + if ((kVIDEO_PixelFormatYUYV != config->pixelFormat) && (kVIDEO_PixelFormatRGB565 != config->pixelFormat) && + (kVIDEO_PixelFormatRGBX4444 != config->pixelFormat) && (kVIDEO_PixelFormatXRGB4444 != config->pixelFormat) && + (kVIDEO_PixelFormatXRGB1555 != config->pixelFormat)) + { + return kStatus_InvalidArgument; + } + + if ((15U != config->framePerSec) && (30U != config->framePerSec) && (25U != config->framePerSec) && + (14U != config->framePerSec)) + { + return kStatus_InvalidArgument; + } + + if ((kCAMERA_InterfaceNonGatedClock != config->interface) && (kCAMERA_InterfaceGatedClock != config->interface)) + { + return kStatus_InvalidArgument; + } + + OV7670_GetDefaultConfig(&cameraConfig); + cameraConfig.resolution = config->resolution; + switch (resource->xclock) + { + case kOV7670_InputClock24MHZ: + if (config->framePerSec == 30U) + { + cameraConfig.frameRate = &OV7670_30FPS_24MHZ_XCLK; + } + else if (config->framePerSec == 25U) + { + cameraConfig.frameRate = &OV7670_25FPS_24MHZ_XCLK; + } + else if (config->framePerSec == 15U) + { + cameraConfig.frameRate = &OV7670_15FPS_24MHZ_XCLK; + } + else if (config->framePerSec == 14U) + { + cameraConfig.frameRate = &OV7670_14FPS_24MHZ_XCLK; + } + else + { + assert(false); + } + break; + case kOV7670_InputClock12MHZ: + if (config->framePerSec == 30U) + { + cameraConfig.frameRate = &OV7670_30FPS_12MHZ_XCLK; + } + else if (config->framePerSec == 25U) + { + cameraConfig.frameRate = &OV7670_25FPS_12MHZ_XCLK; + } + else if (config->framePerSec == 15U) + { + cameraConfig.frameRate = &OV7670_15FPS_12MHZ_XCLK; + } + else if (config->framePerSec == 14U) + { + cameraConfig.frameRate = &OV7670_14FPS_12MHZ_XCLK; + } + else + { + assert(false); + } + break; + case kOV7670_InputClock26MHZ: + if (config->framePerSec == 30U) + { + cameraConfig.frameRate = &OV7670_30FPS_26MHZ_XCLK; + } + else if (config->framePerSec == 25U) + { + cameraConfig.frameRate = &OV7670_25FPS_26MHZ_XCLK; + } + else if (config->framePerSec == 15U) + { + cameraConfig.frameRate = &OV7670_15FPS_26MHZ_XCLK; + } + else if (config->framePerSec == 14U) + { + cameraConfig.frameRate = &OV7670_14FPS_26MHZ_XCLK; + } + else + { + assert(false); + } + break; + case kOV7670_InputClock13MHZ: + if (config->framePerSec == 30U) + { + cameraConfig.frameRate = &OV7670_30FPS_13MHZ_XCLK; + } + else if (config->framePerSec == 25U) + { + cameraConfig.frameRate = &OV7670_25FPS_13MHZ_XCLK; + } + else if (config->framePerSec == 15U) + { + cameraConfig.frameRate = &OV7670_15FPS_13MHZ_XCLK; + } + else if (config->framePerSec == 14U) + { + cameraConfig.frameRate = &OV7670_14FPS_13MHZ_XCLK; + } + else + { + assert(false); + } + break; + default: + assert(false); + break; + } + + switch (config->pixelFormat) + { + case kVIDEO_PixelFormatYUYV: + cameraConfig.outputFormat = &OV7670_FORMAT_YUV422; + break; + + case kVIDEO_PixelFormatXRGB1555: + cameraConfig.outputFormat = &OV7670_FORMAT_RGB555; + break; + + case kVIDEO_PixelFormatRGBX4444: + cameraConfig.outputFormat = &OV7670_FORMAT_RGBx444; + break; + + case kVIDEO_PixelFormatXRGB4444: + cameraConfig.outputFormat = &OV7670_FORMAT_xRGB444; + break; + + case kVIDEO_PixelFormatRGB565: + default: + cameraConfig.outputFormat = &OV7670_FORMAT_RGB565; + break; + } + + do + { + status = OV7670_CameraInit(handle, &cameraConfig); + } while (status != kStatus_Success); + + return status; +} + +status_t OV7670_Deinit(camera_device_handle_t *handle) +{ + return kStatus_Success; +} + +status_t OV7670_Start(camera_device_handle_t *handle) +{ + return kStatus_Success; +} + +status_t OV7670_Stop(camera_device_handle_t *handle) +{ + return kStatus_Success; +} + +status_t OV7670_InitExt(camera_device_handle_t *handle, const camera_config_t *config, const void *specialConfig) +{ + return OV7670_Init(handle, config); +} + +status_t OV7670_Control(camera_device_handle_t *handle, camera_device_cmd_t cmd, int32_t arg) +{ + return kStatus_InvalidArgument; +} diff --git a/components/video/camera/device/ov7670/fsl_ov7670.h b/components/video/camera/device/ov7670/fsl_ov7670.h new file mode 100644 index 000000000..4ce13a4f4 --- /dev/null +++ b/components/video/camera/device/ov7670/fsl_ov7670.h @@ -0,0 +1,817 @@ +/* + * Copyright 2017, 2020, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OV7670_H_ +#define _FSL_OV7670_H_ + +#include "fsl_common.h" +#include "fsl_sccb.h" +#include "fsl_camera_device.h" + +/* + * Change log: + * + * 1.0.2 + * - Fixed dummy line setting bug. + * - Disable PCLK during BLANK. + * + * 1.0.1 + * - Fixed MISRA-C 2012 issues. + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Register definitions for the OV7670.*/ + +#define OV7670_GAIN_REG 0x00U /*!< Gain lower 8 bits (rest in vref). */ + +#define OV7670_BLUE_REG 0x01U /*!< blue gain. */ + +#define OV7670_RED_REG 0x02U /*!< red gain. */ + +#define OV7670_VREF_REG 0x03U /*!< Pieces of GAIN, VSTART, VSTOP. */ + +#define OV7670_COM1_REG 0x04U /*!< Control 1. */ +#define OV7670_COM1_CCIR656_MASK 0x40U /*!< CCIR656 enable. */ + +#define OV7670_BAVE_REG 0x05U /*!< U/B Average level. */ + +#define OV7670_GbAVE_REG 0x06U /*!< Y/Gb Average level. */ + +#define OV7670_AECHH_REG 0x07U /*!< AEC MS 5 bits. */ + +#define OV7670_RAVE_REG 0x08U /*!< V/R Average level. */ + +#define OV7670_COM2_REG 0x09U /*!< Control 2. */ +#define OV7670_COM2_SSLEEP_MASK 0x10U /*!< Soft sleep mode. */ + +#define OV7670_PID_REG 0x0AU /*!< Product ID MSB register address. */ +#define OV7670_PID_NUM 0x76U /*!< Product ID. */ + +#define OV7670_VER_REG 0x0BU /*!< Product ID LSB register address. */ +#define OV7670_VER_NUM 0x73U /*!< Product VERION. */ + +#define OV7670_COM3_REG 0x0CU /*!< Control 3. */ +#define OV7670_COM3_SWAP_MASK 0x40U /*!< Byte swap. */ +#define OV7670_COM3_SCALEEN_MASK 0x08U /*!< Enable scaling. */ +#define OV7670_COM3_DCWEN_MASK 0x04U /*!< Enable downsamp/crop/window. */ + +#define OV7670_COM4_REG 0x0DU /*!< Control 4. */ + +#define OV7670_COM5_REG 0x0EU /*!< All "reserved". */ + +#define OV7670_COM6_REG 0x0FU /*!< Control 6. */ + +#define OV7670_AECH_REG 0x10U /*!< More bits of AEC value. */ + +#define OV7670_CLKRC_REG 0x11U /*!< Clocl control. */ +#define OV7670_CLK_EXT_MASK 0x40U /*!< Use external clock directly. */ +#define OV7670_CLK_SCALE_MASK 0x3FU /*!< Mask for internal clock scale. */ + +#define OV7670_COM7_REG 0x12U /*!< Control 7. */ +#define OV7670_COM7_RESET_MASK 0x80U /*!< Register reset. */ +#define OV7670_COM7_FMT_MASK_MASK 0x38U +#define OV7670_COM7_FMT_VGA_MASK 0x00U +#define OV7670_COM7_FMT_CIF_MASK 0x20U /*!< CIF format. */ +#define OV7670_COM7_FMT_QVGA_MASK 0x10U /*!< QVGA format. */ +#define OV7670_COM7_FMT_QCIF_MASK 0x08U /*!< QCIF format. */ +#define OV7670_COM7_RGB_MASK 0x04U /*!< bits 0 and 2 - RGB format. */ +#define OV7670_COM7_YUV_MASK 0x00U /*!< YUV. */ +#define OV7670_COM7_BAYER_MASK 0x01U /*!< Bayer format. */ +#define OV7670_COM7_PBAYER_MASK 0x05U /*!< "Processed bayer". */ + +#define OV7670_COM8_REG 0x13U /*!< Control 8. */ +#define OV7670_COM8_FASTAEC_MASK 0x80U /*!< Enable fast AGC/AEC. */ +#define OV7670_COM8_AECSTEP_MASK 0x40U /*!< Unlimited AEC step size. */ +#define OV7670_COM8_BFILT_MASK 0x20U /*!< Band filter enable. */ +#define OV7670_COM8_AGC_MASK 0x04U /*!< Auto gain enable. */ +#define OV7670_COM8_AWB_MASK 0x02U /*!< White balance enable. */ +#define OV7670_COM8_AEC_MASK 0x01U /*!< Auto exposure enable. */ + +#define OV7670_COM9_REG 0x14U /*!< Control 9 - gain ceiling. */ + +#define OV7670_COM10_REG 0x15U /*!< Control 10. */ +#define OV7670_COM10_HSYNC_MASK 0x40U /*!< HSYNC instead of HREF. */ +#define OV7670_COM10_PCLK_HB_MASK 0x20U /*!< Suppress PCLK on horiz blank. */ +#define OV7670_COM10_HREF_REV_MASK 0x08U /*!< Reverse HREF. */ +#define OV7670_COM10_VS_LEAD_MASK 0x04U /*!< VSYNC on clock leading edge. */ +#define OV7670_COM10_VS_NEG_MASK 0x02U /*!< VSYNC negative. */ +#define OV7670_COM10_HS_NEG_MASK 0x01U /*!< HSYNC negative. */ + +#define OV7670_RSVD_REG 0x16U /*!< reserved. */ + +#define OV7670_HSTART_REG 0x17U /*!< Horiz start high bits. */ + +#define OV7670_HSTOP_REG 0x18U /*!< Horiz stop high bits. */ + +#define OV7670_VSTART_REG 0x19U /*!< Vert start high bits. */ + +#define OV7670_VSTOP_REG 0x1AU /*!< Vert stop high bits. */ + +#define OV7670_PSHFT_REG 0x1BU /*!< Pixel delay after HREF. */ + +#define OV7670_MIDH_REG 0x1CU /*!< Manuf. ID high. */ + +#define OV7670_MIDL_REG 0x1DU /*!< Manuf. ID low. */ + +#define OV7670_MVFP_REG 0x1EU /*!< Mirror / vflip. */ +#define OV7670_MVFP_MIRROR_MASK 0x20U /*!< Mirror image. */ +#define OV7670_MVFP_FLIP_MASK 0x10U /*!< Vertical flip. */ + +#define OV7670_LAEC_REG 0x1FU /*!< reserved. */ + +#define OV7670_ADCCTR0_REG 0x20U /*!< ADC control. */ +#define OV7670_ADCCTR0_RANGE_ADJ_MASK 0x08U /*!< ADC range adjustment. */ + +#define OV7670_ADCCTR1_REG 0x21U /*!< reserved. */ + +#define OV7670_ADCCTR2_REG 0x22U /*!< reserved. */ + +#define OV7670_ADCCTR3_REG 0x23U /*!< reserved. */ + +#define OV7670_AEW_REG 0x24U /*!< AGC upper limit. */ + +#define OV7670_AEB_REG 0x25U /*!< AGC lower limit. */ + +#define OV7670_VPT_REG 0x26U /*!< AGC/AEC fast mode op region. */ + +#define OV7670_BBIAS_REG 0x27U /*!< B channel signal output bias. */ + +#define OV7670_GbBIAS_REG 0x28U /*!< Gb channel signal output bias. */ + +#define OV7670_RSVD1_REG 0x29U /*!< reserved 1. */ + +#define OV7670_EXHCH_REG 0x2AU /*!< dummy pixel insert MSB. */ + +#define OV7670_EXHCL_REG 0x2BU /*!< dummy pixel insert LSB. */ + +#define OV7670_HSYST_REG 0x30U /*!< HSYNC rising edge delay. */ + +#define OV7670_HSYEN_REG 0x31U /*!< HSYNC falling edge delay. */ + +#define OV7670_HREF_REG 0x32U /*!< HREF pieces. */ + +#define OV7670_CHLF_REG 0x33U /*!< array current control. */ + +#define OV7670_ARBLM_REG 0x34U /*!< array reference control. */ + +#define OV7670_RSVD2_REG 0x35U /*!< reserved 2. */ + +#define OV7670_RSVD3_REG 0x36U /*!< reserved 3. */ + +#define OV7670_ADC_REG 0x37U /*!< ADC control. */ + +#define OV7670_ACOM_REG 0x38U /*!< ADC and Analog common mode control. */ + +#define OV7670_OFON_REG 0x39U /*!< ADC offset control. */ + +#define OV7670_TSLB_REG 0x3AU /*!< lots of stuff. */ +#define OV7670_TSLB_YLAST_MASK 0x04U /*!< UYVY or VYUY - see com13. */ + +#define OV7670_COM11_REG 0x3BU /*!< Control 11. */ +#define OV7670_COM11_NIGHT_MASK 0x80U /*!< NIght mode enable. */ +#define OV7670_COM11_NMFR_MASK 0x60U /*!< Two bit NM frame rate. */ +#define OV7670_COM11_HZAUTO_MASK 0x10U /*!< Auto detect 50/60 Hz. */ +#define OV7670_COM11_50HZ_MASK 0x08U /*!< Manual 50Hz select. */ +#define OV7670_COM11_EXP_MASK 0x02U + +#define OV7670_COM12_REG 0x3CU /*!< Control 12. */ +#define OV7670_COM12_HREF_MASK 0x80U /*!< HREF always. */ + +#define OV7670_COM13_REG 0x3DU /*!< Control 13. */ +#define OV7670_COM13_GAMMA_MASK 0x80U /*!< Gamma enable. */ +#define OV7670_COM13_UVSAT_MASK 0x40U /*!< UV saturation auto adjustment. */ +#define OV7670_COM13_UVSWAP_MASK 0x01U /*!< V before U - w/TSLB. */ + +#define OV7670_COM14_REG 0x3EU /*!< Control 14. */ +#define OV7670_COM14_DCWEN_MASK 0x10U /*!< DCW/PCLK-scale enable. */ + +#define OV7670_EDGE_REG 0x3FU /*!< Edge enhancement factor. */ + +#define OV7670_COM15_REG 0x40U /*!< Control 15. */ +#define OV7670_COM15_R10F0_MASK 0x00U /*!< Data range 10 to F0. */ +#define OV7670_COM15_R01FE_MASK 0x80U /*!< 01 to FE. */ +#define OV7670_COM15_R00FF_MASK 0xC0U /*!< 00 to FF. */ +#define OV7670_COM15_RGB565_MASK 0x10U /*!< RGB565 output. */ +#define OV7670_COM15_RGB555_MASK 0x30U /*!< RGB555 output. */ + +#define OV7670_COM16_REG 0x41U /*!< Control 16. */ +#define OV7670_COM16_AWBGAIN_MASK 0x08U /*!< AWB gain enable. */ + +#define OV7670_COM17_REG 0x42U /*!< Control 17. */ +#define OV7670_COM17_AECWIN_MASK 0xc0U /*!< AEC window - must match COM4. */ +#define OV7670_COM17_CBAR_MASK 0x08U /*!< DSP Color bar. */ + +#define OV7670_AWBC1_REG 0x43U /*!< AWB control 1. */ + +#define OV7670_AWBC2_REG 0x44U /*!< AWB control 2. */ + +#define OV7670_AWBC3_REG 0x45U /*!< AWB control 3. */ + +#define OV7670_AWBC4_REG 0x46U /*!< AWB control 4. */ + +#define OV7670_AWBC5_REG 0x47U /*!< AWB control 5. */ + +#define OV7670_AWBC6_REG 0x48U /*!< AWB control 6. */ + +#define OV7670_MTX1_REG 0x4fU /*!< Matrix Coefficient 1. */ + +#define OV7670_MTX2_REG 0x50U /*!< Matrix Coefficient 2. */ + +#define OV7670_MTX3_REG 0x51U /*!< Matrix Coefficient 3. */ + +#define OV7670_MTX4_REG 0x52U /*!< Matrix Coefficient 4. */ + +#define OV7670_MTX5_REG 0x53U /*!< Matrix Coefficient 5. */ + +#define OV7670_MTX6_REG 0x54U /*!< Matrix Coefficient 6. */ + +#define OV7670_BRIGHT_REG 0x55U /*!< Brightness. */ + +#define OV7670_CONTRAS_REG 0x56U /*!< Contrast control. */ + +#define OV7670_CONTRAS_CENTER_REG 0x57U /*!< Contrast cetnter control. */ + +#define OV7670_MTXS_REG 0x58U /*!< Matrix Coefficient Sign. */ +#define OV7670_AWBC7_MASK 0x59U /*!< AWB Control 7. */ +#define OV7670_AWBC8_MASK 0x5AU /*!< AWB Control 8. */ +#define OV7670_AWBC9_MASK 0x5BU /*!< AWB Control 9. */ +#define OV7670_AWBC10_MASK 0x5CU /*!< AWB Control 10. */ +#define OV7670_AWBC11_MASK 0x5DU /*!< AWB Control 11. */ +#define OV7670_AWBC12_MASK 0x5EU /*!< AWB Control 12. */ + +#define OV7670_MANU_REG 0x67U /*!< Manual U value. */ + +#define OV7670_MANV_REG 0x68U /*!< Manual V value. */ + +#define OV7670_GFIX_REG 0x69U /*!< Fix gain control. */ + +#define OV7670_GGAIN_REG 0x6AU /*!< G Channel AWB Gain. */ + +#define OV7670_DBLV_REG 0x6BU + +#define OV7670_AWBCTR3_REG 0x6CU /*!< AWB Control 3. */ + +#define OV7670_AWBCTR2_REG 0x6DU /*!< AWB Control 2. */ + +#define OV7670_AWBCTR1_REG 0x6EU /*!< AWB Control 1. */ + +#define OV7670_AWBCTR0_REG 0x6FU /*!< AWB Control 0. */ + +#define OV7670_SCALING_XSC_REG 0x70U /*!< horizontal scale factor. */ + +#define OV7670_SCALING_YSC_REG 0x71U /*!< vertical scale factor. */ + +#define OV7670_SCALING_DCWCTR_REG 0x72U /*!< DCW control. */ + +#define OV7670_SCALING_PCLK_DIV_REG 0x73U /*!< clock divider control. */ + +#define OV7670_REG74_REG 0x74U /*!< register 74. */ + +#define OV7670_REG76_REG 0x76U /*!< OV's name. */ +#define OV7670_REG76_BLKPCOR_MASK 0x80U /*!< Black pixel correction enable. */ +#define OV7670_REG76_WHTPCOR_MASK 0x40U /*!< White pixel correction enable. */ + +#define OV7670_SLOP_REG 0x7AU /*!< gamma curve highest segment slop. */ + +#define OV7670_GAM1_REG 0x7BU /*!< gamma curve 1 segment slop. */ +#define OV7670_GAM2_REG 0x7CU /*!< gamma curve 2 segment slop. */ +#define OV7670_GAM3_REG 0x7DU /*!< gamma curve 3 segment slop. */ +#define OV7670_GAM4_REG 0x7EU /*!< gamma curve 4 segment slop. */ +#define OV7670_GAM5_REG 0x7FU /*!< gamma curve 5 segment slop. */ +#define OV7670_GAM6_REG 0x80U /*!< gamma curve 6 segment slop. */ +#define OV7670_GAM7_REG 0x81U /*!< gamma curve 7 segment slop. */ +#define OV7670_GAM8_REG 0x82U /*!< gamma curve 8 segment slop. */ +#define OV7670_GAM9_REG 0x83U /*!< gamma curve 9 segment slop. */ +#define OV7670_GAM10_REG 0x84U /*!< gamma curve 10 segment slop. */ +#define OV7670_GAM11_REG 0x85U /*!< gamma curve 11 segment slop. */ +#define OV7670_GAM12_REG 0x86U /*!< gamma curve 12 segment slop. */ +#define OV7670_GAM13_REG 0x87U /*!< gamma curve 13 segment slop. */ +#define OV7670_GAM14_REG 0x88U /*!< gamma curve 14 segment slop. */ +#define OV7670_GAM15_REG 0x89U /*!< gamma curve 15 segment slop. */ +#define OV7670_RGB444_REG 0x8cU /*!< RGB 444 control. */ +#define OV7670_R444_ENABLE_MASK 0x02U /*!< Turn on RGB444, overrides 5x5. */ +#define OV7670_R444_RGBX_MASK 0x01U /*!< Empty nibble at end. */ + +#define OV7670_DM_LNL_REG 0x92U /*!< dummy line low 8 bits. */ + +#define OV7670_DM_LNH_REG 0x93U /*!< dummy line high 8 bits. */ + +#define OV7670_BD50ST_REG 0x9dU /*!< 50Hz banding filter value. */ + +#define OV7670_BD60ST_REG 0x9eU /*!< 60Hz banding filter value. */ + +#define OV7670_HAECC1_REG 0x9fU /*!< Hist AEC/AGC control 1. */ + +#define OV7670_HAECC2_REG 0xa0U /*!< Hist AEC/AGC control 2. */ + +#define OV7670_SCALING_PCLK_DELAY_REG 0xa2U /*!< pixel clock delay. */ + +#define OV7670_BD50MAX_REG 0xa5U /*!< 50hz banding step limit. */ + +#define OV7670_HAECC3_REG 0xa6U /*!< Hist AEC/AGC control 3. */ + +#define OV7670_HAECC4_REG 0xa7U /*!< Hist AEC/AGC control 4. */ + +#define OV7670_HAECC5_REG 0xa8U /*!< Hist AEC/AGC control 5. */ + +#define OV7670_HAECC6_REG 0xa9U /*!< Hist AEC/AGC control 6. */ + +#define OV7670_HAECC7_REG 0xaaU /*!< Hist AEC/AGC control 7. */ + +#define OV7670_BD60MAX_REG 0xabU /*!< 60hz banding step limit. */ + +#define OV7670_STR_OPT_REG 0xacU /*!< strobe control. */ + +#define OV7670_STR_R_REG 0xadU /*!< R gain for LED output frame. */ + +#define OV7670_STR_G_REG 0xaeU /*!< G gain for LED output frame. */ + +#define OV7670_STR_B_REG 0xafU /*!< B gain for LED output frame. */ + +#define OV7670_ABLC1_REG 0xb1U /*!< ABLC function control. */ + +#define OV7670_THL_ST_REG 0xb3U /*!< ABLC target. */ + +/*! @} */ + +/*! @brief Configuration of window by setting the starting point configuration structure */ +typedef struct ov7670_window_startPoint +{ + uint16_t hstartCoordinate; + uint16_t vstartCoordinate; +} ov7670_window_start_point_t; + +/*! end of ov7670 handler configuration structure */ + +/*! @brief Output format configuration structure */ +typedef struct ov7670_output_format_config +{ + uint8_t com7; + uint8_t com15; + uint8_t rgb444; +} ov7670_output_format_config_t; +/*! end of Output format configuration structure */ + +/*! @brief Resolution configuration structure */ +typedef struct ov7670_resolution_config +{ + uint8_t com7; + uint8_t com3; + uint8_t com14; + uint8_t scalingXsc; + uint8_t scalingYsc; + uint8_t scalingDcwctr; + uint8_t scalingPclkDiv; + uint8_t scalingPclkDelay; +} ov7670_resolution_config_t; +/*! end of Output format configuration structure */ + +/*! @brief Frame rate configuration data structure */ +typedef struct ov7670_frame_rate_config +{ + uint8_t clkrc; + uint8_t dblv; + uint8_t exhch; + uint8_t exhcl; + uint8_t dm_lnl; + uint8_t dm_lnh; +} ov7670_frame_rate_config_t; +/*! end of Frame rate configuration data structure */ + +/*! @brief Night mode configuration data structure */ +typedef struct ov7670_night_mode_config +{ + uint8_t com11; +} ov7670_night_mode_config_t; +/*! end of night mode configuration data structure */ + +/*! @brief Banding filter selection data structure */ +typedef struct ov7670_filter_config +{ + uint8_t com8; + uint8_t bd50st; + uint8_t bd60st; + uint8_t bd50max; + uint8_t bd60max; + uint8_t com11; +} ov7670_filter_config_t; +/*! end of Banding filter selection data structure */ + +/*! @brief White balance configuration structure */ +typedef struct ov7670_white_balance_config +{ + uint8_t com8; + uint8_t awbctr0; + uint8_t awbctr1; + uint8_t awbctr2; + uint8_t awbctr3; + uint8_t awbc1; + uint8_t awbc2; + uint8_t awbc3; + uint8_t awbc4; + uint8_t awbc5; + uint8_t awbc6; + uint8_t com16; +} ov7670_white_balance_config_t; +/*! end of White balance configuration structure */ + +/*! @brief Light mode configuration structure */ +typedef struct ov7670_light_mode_config +{ + uint8_t com8; + uint8_t com9; + uint8_t red; + uint8_t green; + uint8_t blue; +} ov7670_light_mode_config_t; +/*! end of Light mode configuration structure */ + +/*! @brief Color saturation configuration structure */ +typedef struct ov7670_color_saturation_config +{ + uint8_t mtx1; + uint8_t mtx2; + uint8_t mtx3; + uint8_t mtx4; + uint8_t mtx5; + uint8_t mtx6; + uint8_t mtxs; + uint8_t com16; +} ov7670_color_saturation_config_t; +/*! end of Color saturation configuration structure */ + +/*! @brief Special effects configuration structure */ +typedef struct ov7670_special_effect_config +{ + uint8_t tslb; + uint8_t manu; + uint8_t manv; +} ov7670_special_effect_config_t; +/*! end of Special effects configuration structure */ + +/*! @brief Windowing configuration structure */ +typedef struct ov7670_windowing_config +{ + uint8_t href; + uint8_t hstart; + uint8_t hstop; + uint8_t vref; + uint8_t vstart; + uint8_t vstop; +} ov7670_windowing_config_t; + +/*! @brief Gamma curve slope configuration structure */ +typedef struct ov7670_gammaCurveSlopeConfig +{ + uint8_t slope; + uint8_t gam1; + uint8_t gam2; + uint8_t gam3; + uint8_t gam4; + uint8_t gam5; + uint8_t gam6; + uint8_t gam7; + uint8_t gam8; + uint8_t gam9; + uint8_t gam10; + uint8_t gam11; + uint8_t gam12; + uint8_t gam13; + uint8_t gam14; + uint8_t gam15; +} ov7670_gamma_curve_slope_config_t; +/*! end of Gamma curve slope configuration structure */ + +/*! @brief Advanced initialization structure of ov7670 */ +typedef struct ov7670_advanced_config +{ + ov7670_filter_config_t *filter; + ov7670_night_mode_config_t *nightMode; + ov7670_white_balance_config_t *whiteBalance; + ov7670_light_mode_config_t *lightMode; + ov7670_color_saturation_config_t *colorSaturation; + ov7670_special_effect_config_t *specialEffect; + ov7670_gamma_curve_slope_config_t *gammaCurveSlope; +} ov7670_advanced_config_t; + +/*! @brief Initialization structure of ov7670 */ +typedef struct ov7670_config +{ + ov7670_output_format_config_t *outputFormat; + uint32_t resolution; + ov7670_frame_rate_config_t *frameRate; + uint8_t contrast; + uint8_t brightness; + ov7670_advanced_config_t *advancedConfig; +} ov7670_config_t; + +/*! @brief ov7670 input clock. */ +typedef enum _ov7670_xclock +{ + kOV7670_InputClock24MHZ, /*!< Input clock 24MHZ. */ + kOV7670_InputClock26MHZ, /*!< Input clock 26MHZ. */ + kOV7670_InputClock12MHZ, /*!< Input clock 12MHZ. */ + kOV7670_InputClock13MHZ, /*!< Input clock 13MHZ. */ +} ov7670_xclock_t; + +/*! + * @brief OV7670 resource. + * + * Before initialize the OV7670, the resource must be initialized that the SCCB + * I2C could start to work. + */ +typedef struct _ov7670_resource +{ + sccb_i2c_send_func_t i2cSendFunc; /*!< I2C send function. */ + sccb_i2c_receive_func_t i2cReceiveFunc; /*!< I2C receive function. */ + ov7670_xclock_t xclock; /*!< Input clock for ov7670. */ +} ov7670_resource_t; + +/*! @brief OV7670 operation functions. */ +extern const camera_device_operations_t ov7670_ops; + +/*! @brief OV7670 resolution options */ +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_VGA_DEFAULT; +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QVGA_DEFAULT; +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QQVGA_DEFAULT; +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_CIF_DEFAULT; +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QCIF_DEFAULT; +extern ov7670_window_start_point_t OV7670_WINDOW_START_POINT_QQCIF_DEFAULT; + +/*! @brief Night mode initialization structure data */ +extern ov7670_output_format_config_t OV7670_FORMAT_RawBayerRGB; +extern ov7670_output_format_config_t OV7670_FORMAT_ProcessedBayerRGB; +extern ov7670_output_format_config_t OV7670_FORMAT_YUV422; +extern ov7670_output_format_config_t OV7670_FORMAT_GRB422; +extern ov7670_output_format_config_t OV7670_FORMAT_RGB565; +extern ov7670_output_format_config_t OV7670_FORMAT_RGB555; +extern ov7670_output_format_config_t OV7670_FORMAT_xRGB444; +extern ov7670_output_format_config_t OV7670_FORMAT_RGBx444; + +/*! @brief resolution initialization structure data */ +extern ov7670_resolution_config_t OV7670_RESOLUTION_VGA; +extern ov7670_resolution_config_t OV7670_RESOLUTION_QVGA; +extern ov7670_resolution_config_t OV7670_RESOLUTION_QQVGA; + +extern ov7670_resolution_config_t OV7670_RESOLUTION_CIF; +extern ov7670_resolution_config_t OV7670_RESOLUTION_QCIF; +extern ov7670_resolution_config_t OV7670_RESOLUTION_QQCIF; + +extern ov7670_resolution_config_t OV7670_RESOLUTION_QVGA_ORIGINAL; +extern ov7670_resolution_config_t OV7670_RESOLUTION_QCIF_ORIGINAL; + +/*! @brief Special effects configuration initialization structure data */ +extern ov7670_windowing_config_t OV7670_WINDOW_VGA; +extern ov7670_windowing_config_t OV7670_WINDOW_QVGA; +extern ov7670_windowing_config_t OV7670_WINDOW_QQVGA; +extern ov7670_windowing_config_t OV7670_WINDOW_CIF; +extern ov7670_windowing_config_t OV7670_WINDOW_QCIF; +extern ov7670_windowing_config_t OV7670_WINDOW_QQCIF; + +/*! @brief Frame rate initialization structure data */ +extern ov7670_frame_rate_config_t OV7670_30FPS_26MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_25FPS_26MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_15FPS_26MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_14FPS_26MHZ_XCLK; + +extern ov7670_frame_rate_config_t OV7670_30FPS_24MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_25FPS_24MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_15FPS_24MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_14FPS_24MHZ_XCLK; + +extern ov7670_frame_rate_config_t OV7670_30FPS_13MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_25FPS_13MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_15FPS_13MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_14FPS_13MHZ_XCLK; + +extern ov7670_frame_rate_config_t OV7670_30FPS_12MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_25FPS_12MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_15FPS_12MHZ_XCLK; +extern ov7670_frame_rate_config_t OV7670_14FPS_12MHZ_XCLK; + +/*! @brief Night mode initialization structure data */ +extern ov7670_night_mode_config_t OV7670_NIGHT_MODE_DISABLED; +extern ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY2; +extern ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY4; +extern ov7670_night_mode_config_t OV7670_NIGHT_MODE_AUTO_FR_DIVBY8; + +/*! @brief Banding filter initialization structure data */ +extern ov7670_filter_config_t OV7670_FILTER_DISABLED; +extern ov7670_filter_config_t OV7670_FILTER_30FPS_60HZ; +extern ov7670_filter_config_t OV7670_FILTER_15FPS_60HZ; +extern ov7670_filter_config_t OV7670_FILTER_25FPS_50HZ; +extern ov7670_filter_config_t OV7670_FILTER_14FPS_50HZ; +extern ov7670_filter_config_t OV7670_FILTER_30FPS_60HZ_AUTO_LIGHT_FREQ_DETECT; +extern ov7670_filter_config_t OV7670_FILTER_15FPS_60HZ_AUTO_LIGHT_FREQ_DETECT; +extern ov7670_filter_config_t OV7670_FILTER_25FPS_50HZ_AUTO_LIGHT_FREQ_DETECT; +extern ov7670_filter_config_t OV7670_FILTER_14FPS_50HZ_AUTO_LIGHT_FREQ_DETECT; + +/*! @brief White balance initialization structure data */ +extern ov7670_white_balance_config_t OV7670_WHITE_BALANCE_DEFAULT; +extern ov7670_white_balance_config_t OV7670_WHITE_BALANCE_DISABLED; +extern ov7670_white_balance_config_t OV7670_WHITE_BALANCE_SIMPLE; + +/*! @brief Light mode configuration initialization structure data */ +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_DISABLED; +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_AUTO; +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_SUNNY; +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_CLOUDY; +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_OFFICE; +extern ov7670_light_mode_config_t OV7670_LIGHT_MODE_HOME; + +/*! @brief Color saturation configuration initialization structure data */ +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_4PLUS; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_3PLUS; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_2PLUS; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_1PLUS; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_0; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_DEFAULT; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_1MINUS; +extern ov7670_color_saturation_config_t OV7670_COLOR_SATURATION_2MINUS; + +/*! @brief Special effects configuration initialization structure data */ +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_ANTIQUE; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_SEPHIA; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BLUISH; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_GREENISH; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_REDISH; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BW; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_NEGATIVE; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_BW_NEGATIVE; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_NORMAL; +extern ov7670_special_effect_config_t OV7670_SPECIAL_EFFECT_DISABLED; + +/*! @brief Special effects configuration initialization structure data */ +extern ov7670_gamma_curve_slope_config_t OV7670_GAMMA_CURVE_SLOPE_DEFAULT; +extern ov7670_gamma_curve_slope_config_t OV7670_GAMMA_CURVE_SLOPE1; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Get ov7670 default configuration. + * + * config.outputFormat = (ov7670_output_format_config_t *)&OV7670_FORMAT_RGB565; + * config.resolution = kVIDEO_ResolutionQQVGA; + * config.frameRate = (ov7670_frame_rate_config_t *)&OV7670_25FPS_12MHZ_XCLK, + * config.contrast = 0x30; + * config.brightness = 0x10; + * config.advancedConfig = NULL; + * @param config ov7670 configuration structure #ov7670_config_t. + */ +void OV7670_GetDefaultConfig(ov7670_config_t *config); + +/*! + * @brief ov7670 initialize function. + * + * This function will initialize ov7670 using the configuration user passed in. + * Note: If the config pointer is NULL, it would just simply reset ov7670 + * If config is not NULL but the config->advancedConfig is NULL, it will use the below advanced setting: + * advancedConfig = + * { \ + * .filter = (ov7670_filter_config_t *)&OV7670_FILTER_25FPS_50HZ, \ + * .nightMode = (ov7670_night_mode_config_t *)&OV7670_NIGHT_MODE_DISABLED, \ + * .whiteBalance = (ov7670_white_balance_config_t *)&OV7670_WHITE_BALANCE_SIMPLE, \ + * .lightMode = (ov7670_light_mode_config_t *)&OV7670_LIGHT_MODE_DISABLED, \ + * .colorSaturation = (ov7670_color_saturation_config_t *)&OV7670_COLOR_SATURATION_2PLUS, \ + * .specialEffect = (ov7670_special_effect_config_t *)&OV7670_SPECIAL_EFFECT_DISABLED, \ + * .gammaCurveSlope = (ov7670_gamma_curve_slope_config_t *)&OV7670_GAMMA_CURVE_SLOPE_DEFAULT, \ + * } + * @param handle Camera device handle. + * @param config ov7670 configuration structure #ov7670_config_t. + */ + +status_t OV7670_CameraInit(camera_device_handle_t *handle, const ov7670_config_t *config); +/*! + * @brief Write CONTRAST register to ov7670 using I2C. + * @param handle Camera device handle. + * @param val contrast value. + */ +status_t OV7670_ContrastAdjustment(camera_device_handle_t *handle, uint8_t val); + +/*! + * @brief Write BRIGHT register to ov7670 using I2C. + * @param handle Camera device handle. + * @param val brightness value. + */ +status_t OV7670_BrightnessAdjustment(camera_device_handle_t *handle, uint8_t val); + +/*! + * @brief OV7670 configuration. + * @param handle Camera device handle. + * @param config #ov7670_config_t structure. + */ +status_t OV7670_Configure(camera_device_handle_t *handle, const ov7670_config_t *config); + +/*! + * @brief OV7670 Output format configuration. + * @param handle Camera device handle. + * @param outputFormatConfig #ov7670_output_format_config_t structure. + */ +status_t OV7670_OutputFormat(camera_device_handle_t *handle, const ov7670_output_format_config_t *outputFormatConfig); + +/*! + * @brief OV7670 Resolution configuration. + * @param handle Camera device handle. + * @param resolution #video_resolution_t resolution . + */ +status_t OV7670_Resolution(camera_device_handle_t *handle, uint32_t resolution); + +/*! + * @brief OV7670 frame rate adjustment. + * @param handle Camera device handle. + * @param frameRateConfig #ov7670_frame_rate_config_t structure. + */ +status_t OV7670_FrameRateAdjustment(camera_device_handle_t *handle, const ov7670_frame_rate_config_t *frameRateConfig); + +/*! + * @brief OV7670 night mode configuration. + * @param handle Camera device handle. + * @param nightModeConfig #ov7670_night_mode_config_t structure. + */ +status_t OV7670_NightMode(camera_device_handle_t *handle, const ov7670_night_mode_config_t *nightModeConfig); + +/*! + * @brief OV7670 Bnading filter selection configuration. + * @param handle Camera device handle. + * @param filterConfig #ov7670_filter_config_t structure. + */ +status_t OV7670_BandingFilterSelection(camera_device_handle_t *handle, const ov7670_filter_config_t *filterConfig); + +/*! + * @brief OV7670 White balance configuration. + * @param handle Camera device handle. + * @param whiteBalanceConfig #ov7670_white_balance_config_t structure. + */ +status_t OV7670_WhiteBalance(camera_device_handle_t *handle, const ov7670_white_balance_config_t *whiteBalanceConfig); + +/*! + * @brief OV7670 Light mode configuration. + * @param handle Camera device handle. + * @param lightModeConfig #ov7670_light_mode_config_t structure. + */ +status_t OV7670_LightMode(camera_device_handle_t *handle, const ov7670_light_mode_config_t *lightModeConfig); + +/*! + * @brief OV7670 Color saturation configuration. + * @param handle Camera device handle. + * @param colorSaturationConfig #ov7670_color_saturation_config_t structure. + */ +status_t OV7670_ColorSaturation(camera_device_handle_t *handle, + const ov7670_color_saturation_config_t *colorSaturationConfig); + +/*! + * @brief OV7670 Special effects configuration. + * @param handle Camera device handle. + * @param specialEffectConfig #ov7670_special_effect_config_t structure. + */ +status_t OV7670_SpecialEffects(camera_device_handle_t *handle, + const ov7670_special_effect_config_t *specialEffectConfig); + +/*! + * @brief OV7670 Windowing configuration. + * @param handle Camera device handle. + * @param windowingConfig #ov7670_windowing_config_t structure. + */ +status_t OV7670_SetWindow(camera_device_handle_t *handle, const ov7670_windowing_config_t *windowingConfig); + +/*! + * @brief OV7670 Configure the window by setting initial coordinates and + * resolution. + * @param handle Camera device handle. + * @param startPoint #ov7670_window_start_point_t structure. + * @param resolution #ovideo_resolution_t resolution. + */ +status_t OV7670_SetWindowByCoordinates(camera_device_handle_t *handle, + ov7670_window_start_point_t *startPoint, + uint32_t resolution); + +/*! + * @brief OV7670 Gamma curve slope configuration. + * @param handle Camera device handle. + * @param gammaCurveSlopeConfig #ov7670_gamma_curve_slope_config_t structure. + */ +status_t OV7670_GammaCurveSlope(camera_device_handle_t *handle, + const ov7670_gamma_curve_slope_config_t *gammaCurveSlopeConfig); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_OV7670_H_ */ diff --git a/components/video/display/dbi/flexio/fsl_dbi_flexio_edma.c b/components/video/display/dbi/flexio/fsl_dbi_flexio_edma.c index b75761471..ef6806b19 100644 --- a/components/video/display/dbi/flexio/fsl_dbi_flexio_edma.c +++ b/components/video/display/dbi/flexio/fsl_dbi_flexio_edma.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2020,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -117,6 +117,7 @@ status_t DBI_FLEXIO_EDMA_WriteMemory(void *dbiXferHandle, uint32_t command, cons xfer.mode = kFLEXIO_MCULCD_WriteArray; xfer.dataAddrOrSameValue = (uint32_t)(const uint8_t *)data; xfer.dataSize = len_byte; + xfer.dataOnly = false; status = FLEXIO_MCULCD_TransferEDMA(flexioLCD, &xferHandle->flexioHandle, &xfer); } @@ -155,6 +156,7 @@ status_t DBI_FLEXIO_EDMA_ReadMemory(void *dbiXferHandle, uint32_t command, void xfer.mode = kFLEXIO_MCULCD_ReadArray; xfer.dataAddrOrSameValue = (uint32_t)(uint8_t *)data; xfer.dataSize = len_byte; + xfer.dataOnly = false; status = FLEXIO_MCULCD_TransferEDMA(flexioLCD, &xferHandle->flexioHandle, &xfer); } diff --git a/components/video/display/dbi/flexio/fsl_dbi_flexio_smartdma.c b/components/video/display/dbi/flexio/fsl_dbi_flexio_smartdma.c index f8b5799ac..fed3944a6 100644 --- a/components/video/display/dbi/flexio/fsl_dbi_flexio_smartdma.c +++ b/components/video/display/dbi/flexio/fsl_dbi_flexio_smartdma.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2020,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -113,6 +113,7 @@ status_t DBI_FLEXIO_SMARTDMA_WriteMemory(void *dbiXferHandle, uint32_t command, xfer.mode = kFLEXIO_MCULCD_WriteArray; xfer.dataAddrOrSameValue = (uint32_t)(const uint8_t *)data; xfer.dataSize = len_byte; + xfer.dataOnly = false; return FLEXIO_MCULCD_TransferSMARTDMA(flexioLCD, &xferHandle->flexioHandle, &xfer); } diff --git a/components/video/fsl_video_common.h b/components/video/fsl_video_common.h index e4097607f..5fe4eca62 100644 --- a/components/video/fsl_video_common.h +++ b/components/video/fsl_video_common.h @@ -65,11 +65,11 @@ typedef enum _video_pixel_format kVIDEO_PixelFormatXBGR8888 = FSL_VIDEO_FOURCC('X', 'B', '2', '4'), /*!< 32-bit XBGR8888. */ kVIDEO_PixelFormatBGRX8888 = FSL_VIDEO_FOURCC('B', 'X', '2', '4'), /*!< 32-bit BGRX8888. */ - kVIDEO_PixelFormatRGB888 = FSL_VIDEO_FOURCC('R', 'G', '2', '4'), /*!< 24-bit RGB888. */ - kVIDEO_PixelFormatBGR888 = FSL_VIDEO_FOURCC('B', 'G', '2', '4'), /*!< 24-bit BGR888. */ + kVIDEO_PixelFormatRGB888 = FSL_VIDEO_FOURCC('R', 'G', '2', '4'), /*!< 24-bit RGB888. */ + kVIDEO_PixelFormatBGR888 = FSL_VIDEO_FOURCC('B', 'G', '2', '4'), /*!< 24-bit BGR888. */ - kVIDEO_PixelFormatRGB565 = FSL_VIDEO_FOURCC('R', 'G', '1', '6'), /*!< 16-bit RGB565. */ - kVIDEO_PixelFormatBGR565 = FSL_VIDEO_FOURCC('B', 'G', '1', '6'), /*!< 16-bit BGR565. */ + kVIDEO_PixelFormatRGB565 = FSL_VIDEO_FOURCC('R', 'G', '1', '6'), /*!< 16-bit RGB565. */ + kVIDEO_PixelFormatBGR565 = FSL_VIDEO_FOURCC('B', 'G', '1', '6'), /*!< 16-bit BGR565. */ kVIDEO_PixelFormatXRGB1555 = FSL_VIDEO_FOURCC('X', 'R', '1', '5'), /*!< 16-bit XRGB1555. */ kVIDEO_PixelFormatRGBX5551 = FSL_VIDEO_FOURCC('R', 'X', '1', '5'), /*!< 16-bit RGBX5551. */ diff --git a/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW.h b/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW.h index b44acd64e..018b54036 100644 --- a/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW.h +++ b/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW.h @@ -29,8 +29,11 @@ #ifndef _WLAN_TXPWRLIMIT_CFG_WW_H_ #define _WLAN_TXPWRLIMIT_CFG_WW_H_ #include +#include -static wlan_chanlist_t chanlist_2g_cfg = {14, +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = {13, {[0] = { .chan_num = 1, @@ -109,12 +112,7 @@ static wlan_chanlist_t chanlist_2g_cfg = {14, .chan_freq = 2472, .passive_scan_or_radar_detect = true, }, - [13] = - { - .chan_num = 14, - .chan_freq = 2484, - .passive_scan_or_radar_detect = true, - }, + [13] = {0}, [14] = {0}, [15] = {0}, [16] = {0}, @@ -340,2040 +338,1810 @@ static wlan_chanlist_t chanlist_5g_cfg = {25, #endif #ifndef CONFIG_11AC -static wlan_txpwrlimit_t tx_pwrlimit_2g_cfg = +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { - (wifi_SubBand_t)0x00, - 14, - {[0] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 1, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [1] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 2, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [2] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 3, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [3] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 4, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [4] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 5, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [5] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 6, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [6] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 7, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [7] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 8, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [8] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 9, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [9] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 10, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [10] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 11, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [11] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 12, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [12] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 13, - }, - .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, - }, - [13] = - { - .num_mod_grps = 10, - .chan_desc = - { - .start_freq = 2414, - .chan_width = 20, - .chan_num = 14, - }, - .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, {7, 0}, {8, 0}, {9, 0}}, - }, - [14] = {0}, - [15] = {0}, - [16] = {0}, - [17] = {0}, - [18] = {0}, - [19] = {0}, - [20] = {0}, - [21] = {0}, - [22] = {0}, - [23] = {0}, - [24] = {0}, - [25] = {0}, - [26] = {0}, - [27] = {0}, - [28] = {0}, - [29] = {0}, - [30] = {0}, - [31] = {0}, - [32] = {0}, - [33] = {0}, - [34] = {0}, - [35] = {0}, - [36] = {0}, - [37] = {0}, - [38] = {0}, - [39] = {0}}}; + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; #ifdef CONFIG_5GHz_SUPPORT -static wlan_txpwrlimit_t tx_pwrlimit_5g_cfg = - { - (wifi_SubBand_t)0x00, - 39, - {[0] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 36, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [1] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 40, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [2] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 44, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [3] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 48, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [4] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 52, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [5] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 56, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [6] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 60, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [7] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 64, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [8] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 100, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [9] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 104, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [10] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 108, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [11] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 112, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [12] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 116, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [13] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 120, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [14] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 124, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [15] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 128, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [16] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 132, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [17] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 136, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [18] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 140, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [19] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 144, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [20] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 149, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [21] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 153, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [22] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 157, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [23] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 161, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [24] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 165, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [25] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 183, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [26] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 184, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [27] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 185, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [28] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 187, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [29] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 188, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [30] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 189, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [31] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 192, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [32] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 196, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [33] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 7, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [34] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 8, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [35] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 11, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [36] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 12, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [37] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 16, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [38] = - { - .num_mod_grps = 9, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 34, - }, - .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {0, 0}}, - }, - [39] = {0}}}; -#endif +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ #else -static wlan_txpwrlimit_t tx_pwrlimit_2g_cfg = {(wifi_SubBand_t)0x00, - 14, - {[0] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 1, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [1] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 2, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [2] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 3, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [3] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 4, - }, - .txpwrlimit_entry = - { - {0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [4] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 5, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [5] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 6, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [6] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 7, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [7] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 8, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [8] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 9, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [9] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 10, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [10] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 11, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [11] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 12, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [12] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2407, - .chan_width = 20, - .chan_num = 13, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [13] = - { - .num_mod_grps = 12, - .chan_desc = - { - .start_freq = 2414, - .chan_width = 20, - .chan_num = 14, - }, - .txpwrlimit_entry = {{0, 8}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}}, - }, - [14] = {0}, - [15] = {0}, - [16] = {0}, - [17] = {0}, - [18] = {0}, - [19] = {0}, - [20] = {0}, - [21] = {0}, - [22] = {0}, - [23] = {0}, - [24] = {0}, - [25] = {0}, - [26] = {0}, - [27] = {0}, - [28] = {0}, - [29] = {0}, - [30] = {0}, - [31] = {0}, - [32] = {0}, - [33] = {0}, - [34] = {0}, - [35] = {0}, - [36] = {0}, - [37] = {0}, - [38] = {0}, - [39] = {0}}}; +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, +}; #ifdef CONFIG_5GHz_SUPPORT -static wlan_txpwrlimit_t tx_pwrlimit_5g_cfg = {(wifi_SubBand_t)0x00, - 39, - {[0] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 36, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [1] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 40, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [2] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 44, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [3] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 48, - }, - .txpwrlimit_entry = - { - {0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [4] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 52, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [5] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 56, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [6] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 60, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [7] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 64, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [8] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 100, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [9] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 104, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [10] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 108, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [11] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 112, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [12] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 116, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [13] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 120, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [14] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 124, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [15] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 128, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [16] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 132, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [17] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 136, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [18] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 140, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [19] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 144, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [20] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 149, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [21] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 153, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [22] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 157, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [23] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 161, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [24] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 165, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [25] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 183, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [26] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 184, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [27] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 185, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [28] = - { - .num_mod_grps = 16, - .chan_desc = {.start_freq = 5000, - .chan_width = 20, - .chan_num = 187}, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [29] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 188, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [30] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 189, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [31] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 192, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [32] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 196, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [33] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 7, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [34] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 8, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [35] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 11, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [36] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 12, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [37] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 16, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [38] = - { - .num_mod_grps = 16, - .chan_desc = - { - .start_freq = 5000, - .chan_width = 20, - .chan_num = 34, - }, - .txpwrlimit_entry = {{0, 0}, - {1, 8}, - {2, 8}, - {3, 8}, - {4, 8}, - {5, 8}, - {6, 8}, - {7, 8}, - {8, 8}, - {9, 8}, - {10, 8}, - {11, 8}, - {12, 8}, - {13, 8}, - {14, 8}, - {15, 8}}, - }, - [39] = {0}}}; +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = {.start_freq = 5000, .chan_width = 20, .chan_num = 187}, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, +}; #endif /* CONFIG_5GHz_SUPPORT */ #endif /* CONFIG_11AC */ + +#ifdef CONFIG_11AX + +#define MAX_2G_RU_PWR_CHANNELS 26 +#define MAX_5G_RU_PWR_CHANNELS 69 + +static uint8_t rutxpowerlimit_cfg_set[] = { + 0x6d, 0x02, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0xfa, + 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, + 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, + 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, + 0x03, 0x06, 0x09, 0x0c, 0xfa, 0xfd, 0x00, 0x03, 0x06, 0x09, 0x0c, 0x14, 0x14, 0x14, 0x14, 0x14}; +#endif /* CONFIG_11AX */ #endif /* _WLAN_TXPWRLIMIT_CFG_WW_H_ */ diff --git a/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h b/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h index e0f954ae1..c49c5e167 100644 --- a/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h +++ b/components/wifi_bt_module/AzureWave/tx_pwr_limits/wlan_txpwrlimit_cfg_WW_rw610.h @@ -312,9 +312,24 @@ static wlan_chanlist_t chanlist_5g_cfg = { .chan_freq = 5825, .passive_scan_or_radar_detect = true, }, - .chan_info[25] = {0}, - .chan_info[26] = {0}, - .chan_info[27] = {0}, + .chan_info[25] = + { + .chan_num = 169, + .chan_freq = 5845, + .passive_scan_or_radar_detect = false, + }, + .chan_info[26] = + { + .chan_num = 173, + .chan_freq = 5865, + .passive_scan_or_radar_detect = false, + }, + .chan_info[27] = + { + .chan_num = 177, + .chan_freq = 5885, + .passive_scan_or_radar_detect = false, + }, .chan_info[28] = {0}, .chan_info[29] = {0}, .chan_info[30] = {0}, @@ -346,31 +361,80 @@ static wlan_chanlist_t chanlist_5g_cfg = { #ifdef CONFIG_COMPRESS_TX_PWTBL static const t_u8 rg_rw610[] = { - /* action */ - 0x01, 0x00, - /* tlv type, tlv length */ - 0xee, 0x01, 0x06, 0x00, - /* tlv body */ - 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, - /* tlv type, tlv length */ - 0x06, 0x02, 0xe2, 0x00, - /* tlv body */ - 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0x03, 0x0d, - 0x00, 0x02, 0x08, 0x07, 0x04, 0xc1, 0xc0, 0xf0, 0x08, 0x40, 0x04, 0x12, 0x02, 0x84, 0x60, 0xa0, - 0x10, 0x68, 0x04, 0x24, 0x02, 0x00, 0x00, 0x60, 0x90, 0x68, 0x44, 0x28, 0x21, 0x0c, 0x87, 0x44, - 0x22, 0x50, 0x50, 0x10, 0x44, 0x0b, 0x06, 0x86, 0x84, 0x63, 0x50, 0xd0, 0x80, 0x22, 0x08, 0x0c, - 0x8e, 0x44, 0x64, 0x91, 0xd8, 0xfc, 0x6e, 0x51, 0x22, 0x95, 0x41, 0x64, 0xc0, 0x19, 0x44, 0x18, - 0x00, 0x2b, 0x95, 0x83, 0xc0, 0x40, 0xe8, 0xe4, 0xea, 0x6b, 0x10, 0x23, 0xc3, 0x67, 0xd1, 0x89, - 0xe4, 0x10, 0x1c, 0x03, 0x94, 0x03, 0xa2, 0x02, 0xb0, 0x00, 0x10, 0x06, 0x0f, 0x00, 0x01, 0x50, - 0x01, 0x10, 0x18, 0x04, 0x00, 0x2a, 0x0a, 0x01, 0xc2, 0x60, 0x10, 0xa0, 0x10, 0x2a, 0x07, 0x0a, - 0x01, 0x40, 0x01, 0x10, 0xad, 0x72, 0xb5, 0x5c, 0xaf, 0x58, 0x2c, 0x56, 0x4a, 0xe0, 0x06, 0xb6, - 0x12, 0x85, 0xc2, 0xad, 0xf0, 0xbb, 0x98, 0x4c, 0x08, 0x12, 0x02, 0x45, 0xe1, 0xf0, 0x40, 0x6c, - 0x40, 0x23, 0x17, 0xac, 0xdc, 0x2b, 0xa1, 0x50, 0x58, 0x52, 0xad, 0x6c, 0xc0, 0xdb, 0x42, 0xa0, - 0x3a, 0xc8, 0x54, 0x09, 0x86, 0xb1, 0xe1, 0xae, 0x71, 0x68, 0x38, 0x06, 0x15, 0x04, 0xbc, 0x5c, - 0xe2, 0x80, 0x28, 0x24, 0x58, 0x03, 0x3c, 0x06, 0x5f, 0xa0, 0x80, 0x03, 0xf0, 0x40, 0x08, 0x0f, - 0x07, 0x83, 0x2d, 0x7a, 0x33, 0x48, 0x00, 0xd3, 0xa6, 0x07, 0x81, 0x01, 0xc0, 0xb0, 0x55, 0xae, - 0x79, 0xa4}; -static const t_u16 rg_rw610_len = 242; + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0xd8, 0x00, 0x88, 0x88, + 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0x63, 0x0c, 0x00, 0x02, 0x0c, 0x07, + 0x05, 0x41, 0xc1, 0x20, 0x08, 0x4c, 0x04, 0x15, 0x02, 0x84, 0xc0, 0x30, 0x40, 0x88, 0x04, 0x2a, 0x02, 0x00, + 0x42, 0xe0, 0xb0, 0x78, 0x4c, 0x4a, 0x1a, 0x14, 0x88, 0x44, 0xa1, 0x41, 0x20, 0x44, 0x34, 0x25, 0x19, 0x86, + 0xc1, 0xa3, 0x01, 0x50, 0x1c, 0x7e, 0x1b, 0x0f, 0x88, 0xc8, 0x40, 0x41, 0x40, 0x2c, 0x98, 0x03, 0x18, 0x94, + 0xc2, 0xc1, 0x31, 0xe8, 0x80, 0xac, 0x20, 0x0d, 0x00, 0x11, 0xc1, 0xe0, 0x10, 0x80, 0x04, 0x1e, 0x04, 0x08, + 0x00, 0xa7, 0x61, 0x00, 0x20, 0x00, 0x56, 0x0c, 0x02, 0x03, 0xc1, 0xe0, 0xc0, 0x42, 0x00, 0x1d, 0x3b, 0x00, + 0x0a, 0xa4, 0x70, 0x98, 0x38, 0x2c, 0x28, 0x03, 0x0a, 0xd1, 0x60, 0x32, 0xf8, 0xa4, 0x18, 0x2a, 0x0a, 0x0a, + 0x01, 0xa5, 0x15, 0xb0, 0x98, 0x0c, 0x29, 0x05, 0x02, 0x04, 0x80, 0x71, 0xb0, 0x15, 0x96, 0x09, 0x1b, 0xb5, + 0xc2, 0xeb, 0x50, 0xaa, 0x9d, 0x78, 0x24, 0x00, 0xad, 0xdd, 0x60, 0xf6, 0x0b, 0x14, 0x42, 0xb7, 0x6a, 0x09, + 0xda, 0x40, 0xb3, 0x4b, 0x64, 0x2a, 0x3c, 0x07, 0xbc, 0x42, 0x80, 0x07, 0xe0, 0x80, 0x0c, 0x22, 0x05, 0xa1, + 0x80, 0xe8, 0x60, 0x28, 0x68, 0x40, 0x10, 0x0f, 0x01, 0xde, 0x27, 0xa0, 0x03, 0x4e, 0x72, 0x7b, 0x43, 0xa4, + 0xcf, 0x27, 0xc0, 0x7a, 0x08, 0x3c, 0x04, 0x0e, 0x9f, 0x01, 0x01, 0xd9, 0x9a, 0x78, 0x07, 0x16}; +static const t_u16 rg_rw610_len = 232; + +static const t_u8 rg_rw610_qfn[] = { + 0x49, 0x02, 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, + 0x00, 0x01, 0x06, 0x02, 0xba, 0x00, 0x88, 0x88, 0x03, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, + 0x20, 0x10, 0x83, 0x0a, 0x00, 0x02, 0x0c, 0x07, 0x05, 0x41, 0xc1, 0x20, 0x08, 0x4c, 0x02, 0x14, 0x00, 0x85, + 0x40, 0xa1, 0x30, 0x10, 0x46, 0x12, 0x02, 0x00, 0x00, 0x60, 0x90, 0x68, 0x44, 0x2a, 0x19, 0x0e, 0x0a, 0xc4, + 0x22, 0x50, 0x50, 0x4c, 0x38, 0x29, 0x1a, 0x87, 0x44, 0xe0, 0xe0, 0x20, 0xa8, 0x0e, 0x0d, 0x04, 0x8c, 0x48, + 0x23, 0x71, 0x48, 0x5c, 0x6e, 0x3d, 0x20, 0x05, 0xc3, 0x00, 0x02, 0xb0, 0x88, 0x34, 0x00, 0x47, 0x08, 0x00, + 0x81, 0xe0, 0x79, 0xc8, 0x3e, 0x20, 0x2b, 0x06, 0x01, 0x01, 0xe0, 0xf0, 0x60, 0x21, 0x00, 0x0e, 0x07, 0x80, + 0x40, 0x02, 0xa8, 0xfc, 0x5a, 0x48, 0x12, 0x00, 0x40, 0x64, 0x74, 0xe0, 0xad, 0x42, 0xa4, 0x14, 0x02, 0x05, + 0x64, 0x61, 0x30, 0x1c, 0x7e, 0x19, 0x5e, 0x02, 0x05, 0x00, 0xf5, 0x19, 0x3c, 0x92, 0x5b, 0x04, 0xaa, 0xd4, + 0x6b, 0x41, 0x2b, 0x34, 0x9e, 0x13, 0x56, 0xb5, 0x80, 0x82, 0x92, 0xd0, 0x8c, 0xc6, 0xe4, 0x02, 0x09, 0x81, + 0x2a, 0x30, 0xe0, 0x01, 0xf8, 0x22, 0x08, 0x07, 0x82, 0xc2, 0x00, 0x8a, 0x8d, 0x24, 0x00, 0x69, 0xc3, 0x84, + 0x40, 0x72, 0x8a, 0x10, 0x0c, 0x20, 0x10, 0xa8, 0x84, 0x29, 0x47, 0xe0}; +static const t_u16 rg_rw610_len_qfn = 202; + +static const t_u8 rg_rw610_EU[] = { + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0xc0, 0x00, 0x88, 0x88, 0x03, + 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0xe3, 0x0a, 0x00, 0x02, 0x0c, 0x07, 0x04, 0xc1, + 0xa1, 0x50, 0x08, 0x4c, 0x06, 0x14, 0x03, 0xc1, 0x80, 0x10, 0x58, 0x3c, 0x24, 0x07, 0x0b, 0x09, 0x80, 0x82, 0x40, + 0xb8, 0x80, 0x08, 0x28, 0x09, 0x09, 0x80, 0x42, 0x40, 0x18, 0xac, 0x5e, 0x33, 0x1b, 0x85, 0x84, 0x81, 0xa0, 0x01, + 0x58, 0x42, 0x46, 0x47, 0x07, 0x80, 0x42, 0x00, 0x10, 0x78, 0x10, 0x20, 0x02, 0x94, 0x84, 0x00, 0x92, 0x40, 0x60, + 0x10, 0x1e, 0x0f, 0x06, 0x02, 0x10, 0x00, 0xe9, 0x48, 0x00, 0x55, 0x19, 0x0a, 0xc1, 0xc0, 0x71, 0x90, 0xa0, 0x2a, + 0x32, 0x0e, 0x04, 0x00, 0x20, 0x20, 0x2a, 0x08, 0x52, 0x86, 0x01, 0xa2, 0xc6, 0xe9, 0x14, 0xa8, 0xdc, 0x18, 0x29, + 0x05, 0x02, 0x04, 0xa9, 0xe1, 0x20, 0x14, 0x1a, 0xb9, 0x53, 0x07, 0x55, 0x40, 0x34, 0xda, 0x7d, 0x14, 0x22, 0x01, + 0xb0, 0x59, 0xe8, 0x14, 0x2a, 0x20, 0x2a, 0xcf, 0x69, 0x8d, 0x50, 0xeb, 0x20, 0x5b, 0x3d, 0x72, 0x3e, 0x02, 0xb7, + 0xd2, 0x41, 0xd6, 0x70, 0x01, 0xf8, 0x20, 0x03, 0x08, 0x81, 0x66, 0x20, 0x39, 0x8d, 0xe2, 0x54, 0x03, 0xb0, 0x4a, + 0xc0, 0x06, 0x9c, 0x5c, 0xae, 0x63, 0x36, 0x95, 0x4b, 0x00, 0xf2, 0xf0, 0x78, 0x0a, 0xc1, 0x3d, 0x3f, 0x00}; +static const t_u16 rg_rw610_EU_len = 208; + +static const t_u8 rg_rw610_JP[] = { + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0xce, 0x00, 0x88, 0x88, 0x03, + 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0xc3, 0x0b, 0x00, 0x02, 0x0c, 0x07, 0x04, 0xc1, + 0xe1, 0x50, 0x50, 0x48, 0x02, 0x11, 0x00, 0x80, 0x20, 0xe0, 0x18, 0x30, 0x54, 0x10, 0x12, 0x01, 0x42, 0x21, 0x50, + 0x80, 0x90, 0x2e, 0x25, 0x0b, 0x83, 0x05, 0x00, 0x61, 0x50, 0x2c, 0x42, 0x2f, 0x14, 0x00, 0x85, 0x21, 0xf1, 0x18, + 0x4c, 0x62, 0x2d, 0x09, 0x15, 0x84, 0x01, 0xa0, 0x02, 0x38, 0x3c, 0x02, 0x10, 0x00, 0x83, 0xc0, 0x81, 0x00, 0x14, + 0xb8, 0x20, 0x04, 0x00, 0x0a, 0xc1, 0x80, 0x40, 0x78, 0x3c, 0x18, 0x08, 0x40, 0x03, 0xa5, 0xc0, 0x01, 0x50, 0x54, + 0x08, 0x13, 0x02, 0x05, 0x41, 0x91, 0xaa, 0x30, 0x00, 0x1d, 0x1c, 0xa4, 0x05, 0x41, 0x61, 0x40, 0x30, 0x54, 0x05, + 0x4e, 0x0a, 0x80, 0x42, 0x60, 0x30, 0xa5, 0x68, 0x08, 0x12, 0x01, 0x84, 0xe1, 0x80, 0x2a, 0xdc, 0x1a, 0xc5, 0x60, + 0xb3, 0xce, 0x20, 0x20, 0x1a, 0x35, 0x44, 0x27, 0x58, 0x02, 0xd4, 0x6a, 0x75, 0x5a, 0xbd, 0x3e, 0x19, 0x61, 0xaf, + 0x81, 0x62, 0x96, 0x4b, 0x1d, 0x8a, 0x28, 0x07, 0xa7, 0x58, 0x80, 0x07, 0xe0, 0x80, 0x0c, 0x22, 0x05, 0x9b, 0x00, + 0xe6, 0xd2, 0x40, 0x80, 0x20, 0x1e, 0x03, 0xa7, 0x4c, 0x00, 0x06, 0x9c, 0x9c, 0xc2, 0x6d, 0x3c, 0x97, 0xcc, 0x40, + 0xf3, 0x40, 0x78, 0x08, 0x1d, 0x31, 0x02, 0x03, 0xb2, 0x14, 0x28, 0x49, 0xf8}; +static const t_u16 rg_rw610_JP_len = 222; + +static const t_u8 rg_rw610_CA[] = { + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x55, 0x53, 0x20, 0x10, 0x00, 0x01, 0x06, 0x02, 0xe4, 0x00, 0x88, 0x88, 0x03, + 0x01, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x53, 0x20, 0x10, 0x23, 0x0d, 0x00, 0x02, 0x0c, 0x07, 0x04, 0xc1, + 0x60, 0xe0, 0x08, 0x34, 0x02, 0x15, 0x00, 0x84, 0x81, 0x01, 0x10, 0x08, 0x40, 0x02, 0x0c, 0x00, 0x81, 0x40, 0x20, + 0x00, 0x14, 0x2a, 0x19, 0x0e, 0x88, 0x44, 0xa2, 0x91, 0x68, 0x6c, 0x3e, 0x23, 0x13, 0x01, 0x03, 0xe3, 0xa1, 0x10, + 0x34, 0x3a, 0x45, 0x19, 0x90, 0x48, 0xa1, 0xd2, 0x49, 0x34, 0x7a, 0x35, 0x21, 0x91, 0xc9, 0x40, 0x32, 0x78, 0xf8, + 0x00, 0x58, 0x10, 0x04, 0xcd, 0x23, 0x44, 0x89, 0x54, 0xcc, 0x08, 0x10, 0x90, 0x80, 0xa5, 0x13, 0x60, 0x60, 0x10, + 0x1e, 0x0f, 0x06, 0x02, 0x10, 0x00, 0xe9, 0x10, 0x00, 0x54, 0x15, 0x04, 0x05, 0x81, 0x50, 0x80, 0x90, 0x04, 0x28, + 0x03, 0x87, 0x05, 0x40, 0x60, 0x00, 0x70, 0x54, 0x29, 0x55, 0xab, 0xc3, 0x82, 0x90, 0x70, 0x15, 0x72, 0x10, 0x13, + 0x01, 0xd8, 0xc2, 0x60, 0x40, 0x90, 0x0c, 0x27, 0x09, 0x01, 0x5a, 0x2a, 0xb6, 0xfb, 0x6d, 0xbe, 0x1d, 0x6d, 0xae, + 0x5b, 0xea, 0x01, 0x60, 0x5d, 0xea, 0xb1, 0x07, 0xad, 0x83, 0x82, 0xd0, 0x70, 0x9d, 0xbe, 0xc3, 0x56, 0xb2, 0x59, + 0xa1, 0x36, 0xeb, 0x60, 0x16, 0x18, 0x12, 0xb8, 0xdc, 0x2d, 0xf8, 0xfb, 0xfd, 0xe2, 0x03, 0x13, 0x3f, 0x04, 0x00, + 0x61, 0x10, 0x2c, 0xa8, 0x07, 0x2a, 0x01, 0x45, 0xc1, 0x00, 0xfc, 0x0c, 0x38, 0x00, 0x69, 0xd3, 0xcb, 0x42, 0x14, + 0x68, 0xe8, 0x3c, 0x0f, 0x40, 0x07, 0x80, 0xa0, 0x80, 0xf0, 0x20, 0x3b, 0x03, 0x4d, 0x3f, 0x00}; +static const t_u16 rg_rw610_CA_len = 244; #endif #ifndef CONFIG_11AX @@ -535,31 +599,31 @@ static wifi_txpwrlimit_t .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}}, }, .txpwrlimit_config[14] = {0}, - .txpwrlimit_config[15] = {0}, - .txpwrlimit_config[16] = {0}, - .txpwrlimit_config[17] = {0}, - .txpwrlimit_config[18] = {0}, - .txpwrlimit_config[19] = {0}, - .txpwrlimit_config[20] = {0}, - .txpwrlimit_config[21] = {0}, - .txpwrlimit_config[22] = {0}, - .txpwrlimit_config[23] = {0}, - .txpwrlimit_config[24] = {0}, + .txpwrlimit_config[15] = {0}, + .txpwrlimit_config[16] = {0}, + .txpwrlimit_config[17] = {0}, + .txpwrlimit_config[18] = {0}, + .txpwrlimit_config[19] = {0}, + .txpwrlimit_config[20] = {0}, + .txpwrlimit_config[21] = {0}, + .txpwrlimit_config[22] = {0}, + .txpwrlimit_config[23] = {0}, + .txpwrlimit_config[24] = {0}, .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, }; #ifdef CONFIG_5GHz_SUPPORT @@ -843,21 +907,21 @@ static wifi_txpwrlimit_t }, .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, }, - .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[25] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, /* Rest of the channels listed below are not used and contains dummy power entries, * they belong to 4.9GHz Band for Public Safety. */ @@ -1334,32 +1398,32 @@ static wifi_txpwrlimit_t {10, 0}, {11, 0}}, }, - .txpwrlimit_config[14] = {0}, - .txpwrlimit_config[15] = {0}, - .txpwrlimit_config[16] = {0}, - .txpwrlimit_config[17] = {0}, - .txpwrlimit_config[18] = {0}, - .txpwrlimit_config[19] = {0}, - .txpwrlimit_config[20] = {0}, - .txpwrlimit_config[21] = {0}, - .txpwrlimit_config[22] = {0}, - .txpwrlimit_config[23] = {0}, - .txpwrlimit_config[24] = {0}, - .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[14] = {0}, + .txpwrlimit_config[15] = {0}, + .txpwrlimit_config[16] = {0}, + .txpwrlimit_config[17] = {0}, + .txpwrlimit_config[18] = {0}, + .txpwrlimit_config[19] = {0}, + .txpwrlimit_config[20] = {0}, + .txpwrlimit_config[21] = {0}, + .txpwrlimit_config[22] = {0}, + .txpwrlimit_config[23] = {0}, + .txpwrlimit_config[24] = {0}, + .txpwrlimit_config[25] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, }; #ifdef CONFIG_5GHz_SUPPORT @@ -2036,21 +2100,21 @@ static wifi_txpwrlimit_t {14, 0}, {15, 0}}, }, - .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[25] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, /* Rest of the channels listed below are not used and contains dummy power entries, * they belong to 4.9GHz Band for Public Safety. */ @@ -2623,32 +2687,32 @@ static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, }, - .txpwrlimit_config[14] = {0}, - .txpwrlimit_config[15] = {0}, - .txpwrlimit_config[16] = {0}, - .txpwrlimit_config[17] = {0}, - .txpwrlimit_config[18] = {0}, - .txpwrlimit_config[19] = {0}, - .txpwrlimit_config[20] = {0}, - .txpwrlimit_config[21] = {0}, - .txpwrlimit_config[22] = {0}, - .txpwrlimit_config[23] = {0}, - .txpwrlimit_config[24] = {0}, - .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[14] = {0}, + .txpwrlimit_config[15] = {0}, + .txpwrlimit_config[16] = {0}, + .txpwrlimit_config[17] = {0}, + .txpwrlimit_config[18] = {0}, + .txpwrlimit_config[19] = {0}, + .txpwrlimit_config[20] = {0}, + .txpwrlimit_config[21] = {0}, + .txpwrlimit_config[22] = {0}, + .txpwrlimit_config[23] = {0}, + .txpwrlimit_config[24] = {0}, + .txpwrlimit_config[25] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, }; #ifdef CONFIG_5GHz_SUPPORT @@ -2980,21 +3044,21 @@ static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { {7, 0}, {8, 0}, {9, 0}, {10, 12}, {11, 0}, {12, 0}, {13, 0}, {14, 0}, {15, 0}, {16, 10}, {17, 0}, {18, 0}, {19, 0}}, }, - .txpwrlimit_config[25] = {0}, - .txpwrlimit_config[26] = {0}, - .txpwrlimit_config[27] = {0}, - .txpwrlimit_config[28] = {0}, - .txpwrlimit_config[29] = {0}, - .txpwrlimit_config[30] = {0}, - .txpwrlimit_config[31] = {0}, - .txpwrlimit_config[32] = {0}, - .txpwrlimit_config[33] = {0}, - .txpwrlimit_config[34] = {0}, - .txpwrlimit_config[35] = {0}, - .txpwrlimit_config[36] = {0}, - .txpwrlimit_config[37] = {0}, - .txpwrlimit_config[38] = {0}, - .txpwrlimit_config[39] = {0}, + .txpwrlimit_config[25] = {0}, + .txpwrlimit_config[26] = {0}, + .txpwrlimit_config[27] = {0}, + .txpwrlimit_config[28] = {0}, + .txpwrlimit_config[29] = {0}, + .txpwrlimit_config[30] = {0}, + .txpwrlimit_config[31] = {0}, + .txpwrlimit_config[32] = {0}, + .txpwrlimit_config[33] = {0}, + .txpwrlimit_config[34] = {0}, + .txpwrlimit_config[35] = {0}, + .txpwrlimit_config[36] = {0}, + .txpwrlimit_config[37] = {0}, + .txpwrlimit_config[38] = {0}, + .txpwrlimit_config[39] = {0}, /* Rest of the channels listed below are not used and contains dummy power entries, * they belong to 4.9GHz Band for Public Safety. */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_CA.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_CA.h index fc1647234..48a6ac6a3 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_CA.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_CA.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "CA" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_EU.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_EU.h index 718c6ab91..04a52ee7a 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_EU.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_EU.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "EU" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_JP.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_JP.h index 6122bae34..cb595ca2e 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_JP.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_JP.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "JP" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_US.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_US.h index 976f4af55..70c972258 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_US.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_US.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "US" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h index bae42557c..de2acfb0b 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1XK_WW.h @@ -37,7 +37,9 @@ * SOFTWARE. */ -static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = { @@ -117,12 +119,7 @@ static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, .chan_freq = 2472, .passive_scan_or_radar_detect = true, }, - [13] = - { - .chan_num = 14, - .chan_freq = 2484, - .passive_scan_or_radar_detect = true, - }, + [13] = {0}, [14] = {0}, [15] = {0}, [16] = {0}, diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_CA.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_CA.h index edd4be6cb..d3bee95dc 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_CA.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_CA.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "CA" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_EU.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_EU.h index cdeb2dac3..b3eb46f52 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_EU.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_EU.h @@ -36,6 +36,9 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ + +#define WLAN_REGION_CODE "EU" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_JP.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_JP.h index cb678b682..12ebc92d8 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_JP.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_JP.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "JP" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_US.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_US.h index e34212d8b..809d16722 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_US.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_US.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "US" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h index 486065392..bf5999ca2 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_1ZM_WW.h @@ -37,7 +37,9 @@ * SOFTWARE. */ -static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = { @@ -117,12 +119,7 @@ static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, .chan_freq = 2472, .passive_scan_or_radar_detect = true, }, - [13] = - { - .chan_num = 14, - .chan_freq = 2484, - .passive_scan_or_radar_detect = true, - }, + [13] = {0}, [14] = {0}, [15] = {0}, [16] = {0}, diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_CA.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_CA.h index cfdf4e594..71173f84f 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_CA.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_CA.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "CA" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_EU.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_EU.h index bd05feba0..53e5e48d5 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_EU.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_EU.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "EU" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_JP.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_JP.h index e63c70af9..1f2a0a82e 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_JP.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_JP.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "JP" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_US.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_US.h index 5039b2917..8cc480eda 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_US.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_US.h @@ -37,6 +37,8 @@ * SOFTWARE. */ +#define WLAN_REGION_CODE "US" + static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 11, .chan_info = { [0] = diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h index 14e63d93f..c615d37fc 100644 --- a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2DS_WW.h @@ -37,7 +37,9 @@ * SOFTWARE. */ -static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 13, .chan_info = { [0] = { @@ -117,12 +119,7 @@ static wlan_chanlist_t chanlist_2g_cfg = {.num_chans = 14, .chan_freq = 2472, .passive_scan_or_radar_detect = true, }, - [13] = - { - .chan_num = 14, - .chan_freq = 2484, - .passive_scan_or_radar_detect = true, - }, + [13] = {0}, [14] = {0}, [15] = {0}, [16] = {0}, diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h new file mode 100644 index 000000000..d0c01eca4 --- /dev/null +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h @@ -0,0 +1,3136 @@ +/** @file wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h + * + * @brief This file provides Murata 2EL WLAN CA Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_2EL_CA_H_ +#define _WLAN_TXPWRLIMIT_CFG_2EL_CA_H_ +#include +#include + +#ifdef CONFIG_COMPRESS_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_TX_PWTBL in wifi_config.h" +#endif + +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_RU_TX_PWTBL in wifi_config.h" +#endif + +#define WLAN_REGION_CODE "CA" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 11, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 25, + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, + .chan_info[19] = + { + .chan_num = 144, + .chan_freq = 5720, + .passive_scan_or_radar_detect = false, + }, + .chan_info[20] = + { + .chan_num = 149, + .chan_freq = 5745, + .passive_scan_or_radar_detect = false, + }, + .chan_info[21] = + { + .chan_num = 153, + .chan_freq = 5765, + .passive_scan_or_radar_detect = false, + }, + .chan_info[22] = + { + .chan_num = 157, + .chan_freq = 5785, + .passive_scan_or_radar_detect = false, + }, + .chan_info[23] = + { + .chan_num = 161, + .chan_freq = 5805, + .passive_scan_or_radar_detect = false, + }, + .chan_info[24] = + { + .chan_num = 165, + .chan_freq = 5825, + .passive_scan_or_radar_detect = false, + }, +}; +#endif + +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15}, {3, 15}, {4, 13}, {5, 13}, {6, 13}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13}, {3, 13}, {4, 12}, {5, 12}, {6, 12}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 16}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 17}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 19}, {2, 19}, {3, 16}, {4, 18}, {5, 18}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 15}, {4, 21}, {5, 21}, {6, 14}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 21}, {5, 21}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; +#endif +#else +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, + {1, 12}, + {2, 12}, + {3, 12}, + {4, 11}, + {5, 11}, + {6, 11}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 13}, + {11, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 17}, + {2, 17}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 15}, + {5, 15}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 13}, + {2, 13}, + {3, 13}, + {4, 12}, + {5, 12}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 19}, + {1, 0}, + {2, 0}, + {3, 0}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 0}, + {11, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 16}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 17}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 19}, + {2, 19}, + {3, 16}, + {4, 18}, + {5, 18}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 15}, + {4, 21}, + {5, 21}, + {6, 14}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 21}, + {5, 21}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 20}, + {5, 20}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 18}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, {1, 12}, {2, 12}, {3, 12}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 11}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 17}, {1, 13}, {2, 13}, {3, 12}, {4, 12}, {5, 12}, {6, 12}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 12}, {17, 12}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 18}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 18}, {1, 15}, {2, 15}, {3, 15}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 18}, {1, 15}, {2, 15}, {3, 15}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 18}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 17}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 17}, {1, 12}, {2, 12}, {3, 12}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 11}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 11}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 11}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 12}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 12}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 13}, {8, 13}, {9, 13}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 13}, {8, 13}, {9, 13}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 13}, {2, 13}, {3, 13}, {4, 10}, {5, 10}, {6, 10}, + {7, 14}, {8, 14}, {9, 14}, {10, 10}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 10}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 11}, {8, 11}, {9, 11}, {10, 14}, {11, 11}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 11}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 11}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 10}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 18}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 18}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#ifdef CONFIG_11AX +#define MAX_2G_RU_PWR_CHANNELS 13 +#define MAX_5G_RU_PWR_CHANNELS 76 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {11, 11, 11, 10, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {12, 12, 12, 12, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {12, 12, 12, 15, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {12, 12, 12, 15, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {12, 12, 12, 12, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {0, 0, 0, 0, 0, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {8, 10, 11, 11, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {8, 10, 11, 11, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {8, 10, 13, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {8, 10, 11, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {7, 10, 10, 10, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 20, .chan_num = 169, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {8, 10, 11, 10, 7, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {8, 10, 11, 10, 7, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {8, 10, 11, 14, 14, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {8, 10, 11, 14, 14, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {10, 10, 10, 8, 3, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {10, 10, 10, 8, 3, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {13, 13, 13, 12, 13, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {13, 13, 13, 12, 13, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 40, .chan_num = 165, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 40, .chan_num = 169, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {8, 10, 11, 10, 7, 10}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {8, 10, 11, 10, 7, 10}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {8, 10, 11, 10, 7, 10}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {8, 10, 11, 10, 7, 10}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 132, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[69] = {.start_freq = 5000, .width = 80, .chan_num = 136, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[70] = {.start_freq = 5000, .width = 80, .chan_num = 140, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[71] = {.start_freq = 5000, .width = 80, .chan_num = 144, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[72] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[73] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[74] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[75] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {9, 9, 9, 9, 9, 9}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_2EL_CA_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h new file mode 100644 index 000000000..5ad56bb1a --- /dev/null +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h @@ -0,0 +1,3100 @@ +/** @file wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h + * + * @brief This file provides Murata 2EL WLAN EU Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_2EL_EU_H_ +#define _WLAN_TXPWRLIMIT_CFG_2EL_EU_H_ +#include +#include + +#ifdef CONFIG_COMPRESS_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_TX_PWTBL in wifi_config.h" +#endif + +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_RU_TX_PWTBL in wifi_config.h" +#endif + +#define WLAN_REGION_CODE "EU" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 13, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, + .chan_info[11] = + { + .chan_num = 12, + .chan_freq = 2467, + .passive_scan_or_radar_detect = false, + }, + .chan_info[12] = + { + .chan_num = 13, + .chan_freq = 2472, + .passive_scan_or_radar_detect = false, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 19, + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, +}; +#endif + +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15}, {3, 15}, {4, 13}, {5, 13}, {6, 13}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13}, {3, 13}, {4, 12}, {5, 12}, {6, 12}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 16}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 17}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 19}, {2, 19}, {3, 16}, {4, 18}, {5, 18}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 15}, {4, 21}, {5, 21}, {6, 14}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 21}, {5, 21}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; +#endif +#else +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, + {1, 12}, + {2, 12}, + {3, 12}, + {4, 11}, + {5, 11}, + {6, 11}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 13}, + {11, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 17}, + {2, 17}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 15}, + {5, 15}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 13}, + {2, 13}, + {3, 13}, + {4, 12}, + {5, 12}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 19}, + {1, 0}, + {2, 0}, + {3, 0}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 0}, + {11, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 16}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 17}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 19}, + {2, 19}, + {3, 16}, + {4, 18}, + {5, 18}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 15}, + {4, 21}, + {5, 21}, + {6, 14}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 21}, + {5, 21}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 20}, + {5, 20}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 18}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 13}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 12}, {17, 10}, {18, 10}, {19, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 12}, {17, 10}, {18, 10}, {19, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 15}, {2, 15}, {3, 15}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 14}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 12}, {17, 10}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 4}, {2, 4}, {3, 4}, {4, 4}, {5, 4}, {6, 4}, + {7, 4}, {8, 4}, {9, 4}, {10, 4}, {11, 4}, {12, 4}, {13, 4}, + {14, 4}, {15, 4}, {16, 4}, {17, 4}, {18, 4}, {19, 4}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 4}, {2, 4}, {3, 4}, {4, 4}, {5, 4}, {6, 4}, + {7, 4}, {8, 4}, {9, 4}, {10, 4}, {11, 4}, {12, 4}, {13, 4}, + {14, 4}, {15, 4}, {16, 4}, {17, 4}, {18, 4}, {19, 4}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 4}, {2, 4}, {3, 4}, {4, 4}, {5, 4}, {6, 4}, + {7, 4}, {8, 4}, {9, 4}, {10, 4}, {11, 4}, {12, 4}, {13, 4}, + {14, 4}, {15, 4}, {16, 4}, {17, 4}, {18, 4}, {19, 4}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 4}, {2, 4}, {3, 4}, {4, 4}, {5, 4}, {6, 4}, + {7, 4}, {8, 4}, {9, 4}, {10, 4}, {11, 4}, {12, 4}, {13, 4}, + {14, 4}, {15, 4}, {16, 4}, {17, 4}, {18, 4}, {19, 4}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 4}, {2, 4}, {3, 4}, {4, 4}, {5, 4}, {6, 4}, + {7, 4}, {8, 4}, {9, 4}, {10, 4}, {11, 4}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 4}, {17, 4}, {18, 4}, {19, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 18}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 18}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#ifdef CONFIG_11AX +#define MAX_2G_RU_PWR_CHANNELS 13 +#define MAX_5G_RU_PWR_CHANNELS 70 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {7, 9, 12, 14, 0, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {7, 9, 12, 14, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 20, .chan_num = 169, .ruPower = {4, 4, 4, 4, 0, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {7, 9, 12, 14, 14, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 165, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 40, .chan_num = 169, .ruPower = {4, 4, 4, 4, 4, 0}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {7, 9, 12, 14, 14, 14}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {4, 4, 4, 4, 4, 4}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {4, 4, 4, 4, 4, 4}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {4, 4, 4, 4, 4, 4}}, + + .rupwrlimit_config[69] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {4, 4, 4, 4, 4, 4}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_2EL_EU_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h new file mode 100644 index 000000000..22ab080e1 --- /dev/null +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h @@ -0,0 +1,3118 @@ +/** @file wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h + * + * @brief This file provides Murata 2EL WLAN JP Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_2EL_JP_H_ +#define _WLAN_TXPWRLIMIT_CFG_2EL_JP_H_ +#include +#include + +#ifdef CONFIG_COMPRESS_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_TX_PWTBL in wifi_config.h" +#endif + +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_RU_TX_PWTBL in wifi_config.h" +#endif + +#define WLAN_REGION_CODE "JP" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 14, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, + .chan_info[11] = + { + .chan_num = 12, + .chan_freq = 2467, + .passive_scan_or_radar_detect = false, + }, + .chan_info[12] = + { + .chan_num = 13, + .chan_freq = 2472, + .passive_scan_or_radar_detect = false, + }, + .chan_info[13] = + { + .chan_num = 14, + .chan_freq = 2484, + .passive_scan_or_radar_detect = false, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 20, + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, + .chan_info[19] = + { + .chan_num = 144, + .chan_freq = 5720, + .passive_scan_or_radar_detect = true, + }, +}; +#endif + +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15}, {3, 15}, {4, 13}, {5, 13}, {6, 13}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13}, {3, 13}, {4, 12}, {5, 12}, {6, 12}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 16}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 17}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 19}, {2, 19}, {3, 16}, {4, 18}, {5, 18}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 15}, {4, 21}, {5, 21}, {6, 14}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 21}, {5, 21}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; +#endif +#else +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, + {1, 12}, + {2, 12}, + {3, 12}, + {4, 11}, + {5, 11}, + {6, 11}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 13}, + {11, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 17}, + {2, 17}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 15}, + {5, 15}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 13}, + {2, 13}, + {3, 13}, + {4, 12}, + {5, 12}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 19}, + {1, 0}, + {2, 0}, + {3, 0}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 0}, + {11, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 16}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 17}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 19}, + {2, 19}, + {3, 16}, + {4, 18}, + {5, 18}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 15}, + {4, 21}, + {5, 21}, + {6, 14}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 21}, + {5, 21}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 20}, + {5, 20}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 18}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 15}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 13}, {5, 13}, {6, 13}, + {7, 13}, {8, 13}, {9, 13}, {10, 13}, {11, 12}, {12, 13}, {13, 13}, + {14, 13}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 18}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 18}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#ifdef CONFIG_11AX +#define MAX_2G_RU_PWR_CHANNELS 13 +#define MAX_5G_RU_PWR_CHANNELS 73 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {9, 10, 13, 15, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {9, 10, 13, 15, 0, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {4, 7, 10, 13, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {1, 4, 7, 10, 13, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 132, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 136, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 140, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 144, .ruPower = {-2, 1, 4, 7, 10, 13}}, + + .rupwrlimit_config[69] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[70] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[71] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[72] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {0, 0, 0, 0, 0, 0}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_2EL_JP_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h new file mode 100644 index 000000000..b59ab35cc --- /dev/null +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h @@ -0,0 +1,3136 @@ +/** @file wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h + * + * @brief This file provides Murata 2EL WLAN US Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_2EL_US_H_ +#define _WLAN_TXPWRLIMIT_CFG_2EL_US_H_ +#include +#include + +#ifdef CONFIG_COMPRESS_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_TX_PWTBL in wifi_config.h" +#endif + +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +#error "Please disable CONFIG_COMPRESS_RU_TX_PWTBL in wifi_config.h" +#endif + +#define WLAN_REGION_CODE "US" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 11, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 25, + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, + .chan_info[19] = + { + .chan_num = 144, + .chan_freq = 5720, + .passive_scan_or_radar_detect = true, + }, + .chan_info[20] = + { + .chan_num = 149, + .chan_freq = 5745, + .passive_scan_or_radar_detect = false, + }, + .chan_info[21] = + { + .chan_num = 153, + .chan_freq = 5765, + .passive_scan_or_radar_detect = false, + }, + .chan_info[22] = + { + .chan_num = 157, + .chan_freq = 5785, + .passive_scan_or_radar_detect = false, + }, + .chan_info[23] = + { + .chan_num = 161, + .chan_freq = 5805, + .passive_scan_or_radar_detect = false, + }, + .chan_info[24] = + { + .chan_num = 165, + .chan_freq = 5825, + .passive_scan_or_radar_detect = false, + }, +}; +#endif + +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 19}, {1, 15}, {2, 15}, {3, 15}, {4, 13}, {5, 13}, {6, 13}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, {1, 17}, {2, 17}, {3, 16}, {4, 16}, {5, 16}, {6, 16}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, {1, 13}, {2, 13}, {3, 13}, {4, 12}, {5, 12}, {6, 12}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, {1, 18}, {2, 18}, {3, 17}, {4, 16}, {5, 17}, {6, 16}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 7, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 19}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 16}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 17}, {4, 20}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 20}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 19}, {2, 19}, {3, 16}, {4, 18}, {5, 18}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 19}, {4, 20}, {5, 21}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 19}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 18}, {4, 21}, {5, 20}, {6, 18}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 21}, {2, 21}, {3, 16}, {4, 21}, {5, 20}, {6, 15}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 17}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 18}, {4, 21}, {5, 21}, {6, 16}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 15}, {4, 21}, {5, 21}, {6, 14}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 21}, {5, 21}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 13}, {4, 20}, {5, 20}, {6, 12}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; +#endif +#else +static wifi_txpwrlimit_t + tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, + {1, 12}, + {2, 12}, + {3, 12}, + {4, 11}, + {5, 11}, + {6, 11}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 13}, + {11, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 17}, + {2, 17}, + {3, 16}, + {4, 16}, + {5, 16}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 16}, + {2, 16}, + {3, 16}, + {4, 15}, + {5, 15}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 13}, + {2, 13}, + {3, 13}, + {4, 12}, + {5, 12}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 19}, + {1, 18}, + {2, 18}, + {3, 17}, + {4, 16}, + {5, 17}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 19}, + {1, 0}, + {2, 0}, + {3, 0}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 0}, + {11, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 16}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 17}, + {4, 20}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 20}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 19}, + {2, 19}, + {3, 16}, + {4, 18}, + {5, 18}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 19}, + {4, 20}, + {5, 21}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 19}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 18}, + {4, 21}, + {5, 20}, + {6, 18}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 21}, + {2, 21}, + {3, 16}, + {4, 21}, + {5, 20}, + {6, 15}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 15}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 17}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 18}, + {4, 21}, + {5, 21}, + {6, 16}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 15}, + {4, 21}, + {5, 21}, + {6, 14}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 21}, + {5, 21}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 13}, + {4, 20}, + {5, 20}, + {6, 12}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 12}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 18}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = + {{0, 0}, + {1, 20}, + {2, 20}, + {3, 20}, + {4, 20}, + {5, 20}, + {6, 19}, + {7, 0}, + {8, 0}, + {9, 0}, + {10, 16}, + {11, 0}, + {12, 0}, + {13, 0}, + {14, 0}, + {15, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 16}, {1, 12}, {2, 12}, {3, 12}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 11}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 17}, {1, 13}, {2, 13}, {3, 12}, {4, 12}, {5, 12}, {6, 12}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 12}, {17, 12}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 18}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 18}, {1, 15}, {2, 15}, {3, 15}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 18}, {1, 15}, {2, 15}, {3, 15}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 18}, {1, 16}, {2, 16}, {3, 16}, {4, 15}, {5, 15}, {6, 15}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 18}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 17}, {1, 14}, {2, 14}, {3, 14}, {4, 14}, {5, 14}, {6, 14}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 13}, {17, 13}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 17}, {1, 12}, {2, 12}, {3, 12}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 11}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, + {7, 0}, {8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 0}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 10}, {11, 10}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 10}, {11, 10}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 10}, {13, 10}, + {14, 10}, {15, 10}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 11}, {13, 11}, + {14, 11}, {15, 11}, {16, 11}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 11}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 10}, {8, 10}, {9, 10}, {10, 11}, {11, 10}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 11}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 12}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 7}, {13, 7}, + {14, 7}, {15, 7}, {16, 12}, {17, 10}, {18, 10}, {19, 7}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 13}, {8, 13}, {9, 13}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 13}, {8, 13}, {9, 13}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 13}, {2, 13}, {3, 13}, {4, 10}, {5, 10}, {6, 10}, + {7, 14}, {8, 14}, {9, 14}, {10, 10}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 10}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 14}, {13, 14}, + {14, 14}, {15, 12}, {16, 12}, {17, 10}, {18, 10}, {19, 10}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 14}, {8, 14}, {9, 14}, {10, 14}, {11, 12}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 16}, {2, 16}, {3, 16}, {4, 14}, {5, 14}, {6, 14}, + {7, 11}, {8, 11}, {9, 11}, {10, 14}, {11, 11}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 12}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 11}, {8, 11}, {9, 11}, {10, 11}, {11, 11}, {12, 9}, {13, 9}, + {14, 9}, {15, 9}, {16, 11}, {17, 10}, {18, 10}, {19, 9}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 14}, {2, 14}, {3, 14}, {4, 11}, {5, 11}, {6, 11}, + {7, 0}, {8, 0}, {9, 0}, {10, 11}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 11}, {17, 10}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 18}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 18}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 20}, {2, 20}, {3, 20}, {4, 20}, {5, 20}, {6, 19}, + {7, 0}, {8, 0}, {9, 0}, {10, 16}, {11, 0}, {12, 0}, {13, 0}, + {14, 0}, {15, 0}, {16, 16}, {17, 0}, {18, 0}, {19, 0}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#ifdef CONFIG_11AX +#define MAX_2G_RU_PWR_CHANNELS 13 +#define MAX_5G_RU_PWR_CHANNELS 76 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {11, 11, 11, 10, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {12, 12, 12, 12, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {12, 12, 12, 15, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {12, 12, 12, 15, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {12, 12, 12, 14, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {12, 12, 12, 12, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {0, 0, 0, 0, 0, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {14, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {7, 10, 10, 10, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {11, 14, 14, 14, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {11, 11, 11, 11, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 20, .chan_num = 169, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {10, 10, 10, 10, 7, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {10, 10, 10, 10, 7, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {10, 10, 10, 8, 3, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {10, 10, 10, 8, 3, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {14, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {14, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {14, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {14, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {13, 13, 13, 12, 13, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {13, 13, 13, 12, 13, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {11, 14, 14, 14, 14, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {11, 11, 11, 11, 11, 0}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 40, .chan_num = 165, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 40, .chan_num = 169, .ruPower = {0, 0, 0, 0, 0, 0}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {10, 10, 10, 10, 10, 7}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {10, 10, 10, 10, 10, 7}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {10, 10, 10, 10, 10, 7}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {10, 10, 10, 10, 10, 7}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {11, 11, 11, 11, 11, 11}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {7, 7, 7, 7, 7, 5}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 132, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[69] = {.start_freq = 5000, .width = 80, .chan_num = 136, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[70] = {.start_freq = 5000, .width = 80, .chan_num = 140, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[71] = {.start_freq = 5000, .width = 80, .chan_num = 144, .ruPower = {14, 14, 14, 14, 14, 14}}, + + .rupwrlimit_config[72] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[73] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[74] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {9, 9, 9, 9, 9, 9}}, + + .rupwrlimit_config[75] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {9, 9, 9, 9, 9, 9}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_2EL_US_H_ */ diff --git a/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_WW.h b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_WW.h new file mode 100644 index 000000000..71e934ace --- /dev/null +++ b/components/wifi_bt_module/Murata/tx_pwr_limits/wlan_txpwrlimit_cfg_murata_2EL_WW.h @@ -0,0 +1,2993 @@ +/** @file wlan_txpwrlimit_cfg_murata_2EL_WW.h + * + * @brief This file provides Murata 2EL WLAN World Wide Safe Mode Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_WW_H_ +#define _WLAN_TXPWRLIMIT_CFG_WW_H_ +#include +#include + +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 13, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, + .chan_info[11] = + { + .chan_num = 12, + .chan_freq = 2467, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 13, + .chan_freq = 2472, + .passive_scan_or_radar_detect = true, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 25, + + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, + .chan_info[19] = + { + .chan_num = 144, + .chan_freq = 5720, + .passive_scan_or_radar_detect = true, + }, + .chan_info[20] = + { + .chan_num = 149, + .chan_freq = 5745, + .passive_scan_or_radar_detect = false, + }, + .chan_info[21] = + { + .chan_num = 153, + .chan_freq = 5765, + .passive_scan_or_radar_detect = false, + }, + .chan_info[22] = + { + .chan_num = 157, + .chan_freq = 5785, + .passive_scan_or_radar_detect = false, + }, + .chan_info[23] = + { + .chan_num = 161, + .chan_freq = 5805, + .passive_scan_or_radar_detect = false, + }, + .chan_info[24] = + { + .chan_num = 165, + .chan_freq = 5825, + .passive_scan_or_radar_detect = false, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ + +#ifdef CONFIG_COMPRESS_TX_PWTBL + +static const t_u8 rg_table_fc[] = { + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x57, 0x57, 0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x5b, 0x00, 0xf0, 0xf0, + 0x04, 0x01, 0x0b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x57, 0x57, 0x00, 0x00, 0x93, 0x04, 0x00, 0x02, 0x08, 0x05, + 0x82, 0xc0, 0x48, 0x00, 0x08, 0x20, 0x1a, 0x00, 0x82, 0xc1, 0xe1, 0x30, 0x88, 0x34, 0x32, 0x15, 0x0d, 0x85, + 0xc4, 0x62, 0x11, 0x38, 0x7c, 0x1c, 0x73, 0x14, 0x87, 0x00, 0x01, 0xe0, 0x00, 0x20, 0x0e, 0x36, 0x05, 0x40, + 0x04, 0x40, 0x60, 0x10, 0x00, 0xa8, 0x10, 0x18, 0x00, 0x04, 0x41, 0x01, 0x99, 0x4c, 0xae, 0x5b, 0x2c, 0x95, + 0x4c, 0x25, 0xd3, 0x19, 0x7c, 0xd6, 0x69, 0x37, 0x99, 0xce, 0x66, 0x53, 0xb9, 0xb4, 0xea, 0x5a, 0x01}; +static const t_u16 rg_table_fc_len = 107; +#else +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = {.start_freq = 5000, .chan_width = 20, .chan_num = 187}, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = {.start_freq = 5000, .chan_width = 20, .chan_num = 187}, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ +#endif /* CONFIG_COMPRESS_TX_PWTBL */ + +#ifdef CONFIG_11AX +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +const static uint8_t rutxpowerlimit_cfg_set[] = { + 0x6d, 0x02, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c}; +#else +#define MAX_2G_RU_PWR_CHANNELS 26 +#define MAX_5G_RU_PWR_CHANNELS 69 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 2407, .width = 40, .chan_num = 1, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 2407, .width = 40, .chan_num = 2, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 2407, .width = 40, .chan_num = 3, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 2407, .width = 40, .chan_num = 4, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 2407, .width = 40, .chan_num = 5, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 2407, .width = 40, .chan_num = 6, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 2407, .width = 40, .chan_num = 7, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 2407, .width = 40, .chan_num = 8, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 2407, .width = 40, .chan_num = 9, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 2407, .width = 40, .chan_num = 10, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 2407, .width = 40, .chan_num = 11, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 2407, .width = 40, .chan_num = 12, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 2407, .width = 40, .chan_num = 13, .ruPower = {-4, -1, 2, 5, 8, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {-7, -4, -1, 2, 5, 8}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_COMPRESS_RU_TX_PWTBL */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_WW_H_ */ diff --git a/components/wifi_bt_module/incl/wifi_bt_module_config.h b/components/wifi_bt_module/incl/wifi_bt_module_config.h new file mode 100644 index 000000000..870a3b92d --- /dev/null +++ b/components/wifi_bt_module/incl/wifi_bt_module_config.h @@ -0,0 +1,352 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Wi-Fi boards configuration list */ + +/* AzureWave AW-NM191-uSD */ +#if defined(WIFI_88W8801_BOARD_AW_NM191_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8801 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ + } + +/* AzureWave AW-NM191MA */ +#elif defined(WIFI_88W8801_BOARD_AW_NM191MA) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8801 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ + } + +/* AzureWave AW-AM457-uSD */ +#elif defined(WIFI_IW416_BOARD_AW_AM457_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_USD_INTERFACE +#define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h" +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* AzureWave AW-AM457MA */ +#elif defined(WIFI_IW416_BOARD_AW_AM457MA) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_M2_INTERFACE +#define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h" +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* AzureWave AW-AM510-uSD */ +#elif defined(WIFI_IW416_BOARD_AW_AM510_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define CONFIG_BR_SCO_PCM_DIRECTION 1 +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* AzureWave AW-AM510MA */ +#elif defined(WIFI_IW416_BOARD_AW_AM510MA) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define CONFIG_BR_SCO_PCM_DIRECTION 1 +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* AzureWave AW-CM358-uSD */ +#elif defined(WIFI_88W8987_BOARD_AW_CM358_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8987 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* AzureWave AW-CM358MA */ +#elif defined(WIFI_88W8987_BOARD_AW_CM358MA) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8987 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* Murata 2DS + Murata uSD-M.2 adapter */ +#elif defined(WIFI_88W8801_BOARD_MURATA_2DS_USD) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h" +#define SD8801 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \ + } + +/* Murata 2DS */ +#elif defined(WIFI_88W8801_BOARD_MURATA_2DS_M2) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h" +#define SD8801 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \ + } + +/* Murata 1XK + Murata uSD-M.2 adapter */ +#elif defined(WIFI_IW416_BOARD_MURATA_1XK_USD) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ + } + +/* Murata 1XK */ +#elif defined(WIFI_IW416_BOARD_MURATA_1XK_M2) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ + } + +/* Murata 1ZM + Murata uSD-M.2 adapter */ +#elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_USD) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h" +#define SD8987 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ + } + +/* Murata 1ZM */ +#elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_M2) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h" +#define SD8987 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ + } + +/* USD Firecrest module */ +#elif defined(WIFI_IW612_BOARD_RD_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_3V3 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* RD Firecrest module with M2 interface */ +#elif defined(WIFI_IW612_BOARD_RD_M2) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* 2EL Firecrest module with uSD adapter */ +#elif defined(WIFI_IW612_BOARD_MURATA_2EL_USD) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* 2EL Firecrest module with M2 interface */ +#elif defined(WIFI_IW612_BOARD_MURATA_2EL_M2) +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h" +// #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h" +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* u-blox EVK-LILY-W131/-W132 */ +#elif defined(WIFI_88W8801_BOARD_UBX_LILY_W1_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8801 +#define SDMMCHOST_OPERATION_VOLTAGE_3V3 +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ + } + +/* u-blox EVK-JODY-W263 */ +#elif defined(WIFI_88W8987_BOARD_UBX_JODY_W2_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8987 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } +/* Murata 2DL + Murata uSD-M.2 adapter */ +#elif defined(WIFI_IW611_BOARD_MURATA_2DL_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* Murata 2DL */ +#elif defined(WIFI_IW611_BOARD_MURATA_2DL_M2) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* u-blox JODY W5 uSD */ +#elif defined(WIFI_AW611_BOARD_UBX_JODY_W5_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_jody_w5_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* u-blox JODY W5 M2 */ +#elif defined(WIFI_AW611_BOARD_UBX_JODY_W5_M2) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_jody_w5_WW.h" +#define SD9177 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define SD_TIMING_MAX kSD_TimingDDR50Mode +#define WIFI_BT_USE_M2_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ + } + +/* u-blox EVK-MAYA-W161/-W166 */ +#elif defined(WIFI_IW416_BOARD_UBX_MAYA_W1_USD) +#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" +#define SD8978 +#define SDMMCHOST_OPERATION_VOLTAGE_1V8 +#define WIFI_BT_USE_USD_INTERFACE +#define WLAN_ED_MAC_CTRL \ + { \ + .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ + } + +/* K32W061 transceiver */ +#elif defined(K32W061_TRANSCEIVER) +/* + * Wifi functions are not used with K32W061 but wifi files require to + * be built, so stub macro are defined. Wifi functions won't be used at + * link stage for k32w061 transceiver + * + */ +#define SD8987 + +#else +#error "Please define macro related to wifi board" +#endif diff --git a/components/wifi_bt_module/u-blox/tx_pwr_limits/wlan_txpwrlimit_cfg_jody_w5_WW.h b/components/wifi_bt_module/u-blox/tx_pwr_limits/wlan_txpwrlimit_cfg_jody_w5_WW.h new file mode 100644 index 000000000..5726d28f0 --- /dev/null +++ b/components/wifi_bt_module/u-blox/tx_pwr_limits/wlan_txpwrlimit_cfg_jody_w5_WW.h @@ -0,0 +1,2993 @@ +/** @file wlan_txpwrlimit_cfg_jody_w5_WW.h + * + * @brief This file provides WLAN World Wide Safe Mode Tx Power Limits. + * + * Copyright 2008-2021 NXP + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL NXP AND/OR ITS SUPPLIERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _WLAN_TXPWRLIMIT_CFG_WW_H_ +#define _WLAN_TXPWRLIMIT_CFG_WW_H_ +#include +#include + +#define WLAN_REGION_CODE "WW" + +static wlan_chanlist_t chanlist_2g_cfg = { + .num_chans = 13, + .chan_info[0] = + { + .chan_num = 1, + .chan_freq = 2412, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 2, + .chan_freq = 2417, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 3, + .chan_freq = 2422, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 4, + .chan_freq = 2427, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 5, + .chan_freq = 2432, + .passive_scan_or_radar_detect = false, + }, + .chan_info[5] = + { + .chan_num = 6, + .chan_freq = 2437, + .passive_scan_or_radar_detect = false, + }, + .chan_info[6] = + { + .chan_num = 7, + .chan_freq = 2442, + .passive_scan_or_radar_detect = false, + }, + .chan_info[7] = + { + .chan_num = 8, + .chan_freq = 2447, + .passive_scan_or_radar_detect = false, + }, + .chan_info[8] = + { + .chan_num = 9, + .chan_freq = 2452, + .passive_scan_or_radar_detect = false, + }, + .chan_info[9] = + { + .chan_num = 10, + .chan_freq = 2457, + .passive_scan_or_radar_detect = false, + }, + .chan_info[10] = + { + .chan_num = 11, + .chan_freq = 2462, + .passive_scan_or_radar_detect = false, + }, + .chan_info[11] = + { + .chan_num = 12, + .chan_freq = 2467, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 13, + .chan_freq = 2472, + .passive_scan_or_radar_detect = true, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wlan_chanlist_t chanlist_5g_cfg = { + .num_chans = 25, + + .chan_info[0] = + { + .chan_num = 36, + .chan_freq = 5180, + .passive_scan_or_radar_detect = false, + }, + .chan_info[1] = + { + .chan_num = 40, + .chan_freq = 5200, + .passive_scan_or_radar_detect = false, + }, + .chan_info[2] = + { + .chan_num = 44, + .chan_freq = 5220, + .passive_scan_or_radar_detect = false, + }, + .chan_info[3] = + { + .chan_num = 48, + .chan_freq = 5240, + .passive_scan_or_radar_detect = false, + }, + .chan_info[4] = + { + .chan_num = 52, + .chan_freq = 5260, + .passive_scan_or_radar_detect = true, + }, + .chan_info[5] = + { + .chan_num = 56, + .chan_freq = 5280, + .passive_scan_or_radar_detect = true, + }, + .chan_info[6] = + { + .chan_num = 60, + .chan_freq = 5300, + .passive_scan_or_radar_detect = true, + }, + .chan_info[7] = + { + .chan_num = 64, + .chan_freq = 5320, + .passive_scan_or_radar_detect = true, + }, + .chan_info[8] = + { + .chan_num = 100, + .chan_freq = 5500, + .passive_scan_or_radar_detect = true, + }, + .chan_info[9] = + { + .chan_num = 104, + .chan_freq = 5520, + .passive_scan_or_radar_detect = true, + }, + .chan_info[10] = + { + .chan_num = 108, + .chan_freq = 5540, + .passive_scan_or_radar_detect = true, + }, + .chan_info[11] = + { + .chan_num = 112, + .chan_freq = 5560, + .passive_scan_or_radar_detect = true, + }, + .chan_info[12] = + { + .chan_num = 116, + .chan_freq = 5580, + .passive_scan_or_radar_detect = true, + }, + .chan_info[13] = + { + .chan_num = 120, + .chan_freq = 5600, + .passive_scan_or_radar_detect = true, + }, + .chan_info[14] = + { + .chan_num = 124, + .chan_freq = 5620, + .passive_scan_or_radar_detect = true, + }, + .chan_info[15] = + { + .chan_num = 128, + .chan_freq = 5640, + .passive_scan_or_radar_detect = true, + }, + .chan_info[16] = + { + .chan_num = 132, + .chan_freq = 5660, + .passive_scan_or_radar_detect = true, + }, + .chan_info[17] = + { + .chan_num = 136, + .chan_freq = 5680, + .passive_scan_or_radar_detect = true, + }, + .chan_info[18] = + { + .chan_num = 140, + .chan_freq = 5700, + .passive_scan_or_radar_detect = true, + }, + .chan_info[19] = + { + .chan_num = 144, + .chan_freq = 5720, + .passive_scan_or_radar_detect = true, + }, + .chan_info[20] = + { + .chan_num = 149, + .chan_freq = 5745, + .passive_scan_or_radar_detect = false, + }, + .chan_info[21] = + { + .chan_num = 153, + .chan_freq = 5765, + .passive_scan_or_radar_detect = false, + }, + .chan_info[22] = + { + .chan_num = 157, + .chan_freq = 5785, + .passive_scan_or_radar_detect = false, + }, + .chan_info[23] = + { + .chan_num = 161, + .chan_freq = 5805, + .passive_scan_or_radar_detect = false, + }, + .chan_info[24] = + { + .chan_num = 165, + .chan_freq = 5825, + .passive_scan_or_radar_detect = false, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ + +#ifdef CONFIG_COMPRESS_TX_PWTBL + +static const t_u8 rg_table_fc[] = { + 0x01, 0x00, 0xee, 0x01, 0x06, 0x00, 0x57, 0x57, 0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x5b, 0x00, 0xf0, 0xf0, + 0x04, 0x01, 0x0b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x57, 0x57, 0x00, 0x00, 0x93, 0x04, 0x00, 0x02, 0x08, 0x05, + 0x82, 0xc0, 0x48, 0x00, 0x08, 0x20, 0x1a, 0x00, 0x82, 0xc1, 0xe1, 0x30, 0x88, 0x34, 0x32, 0x15, 0x0d, 0x85, + 0xc4, 0x62, 0x11, 0x38, 0x7c, 0x1c, 0x73, 0x14, 0x87, 0x00, 0x01, 0xe0, 0x00, 0x20, 0x0e, 0x36, 0x05, 0x40, + 0x04, 0x40, 0x60, 0x10, 0x00, 0xa8, 0x10, 0x18, 0x00, 0x04, 0x41, 0x01, 0x99, 0x4c, 0xae, 0x5b, 0x2c, 0x95, + 0x4c, 0x25, 0xd3, 0x19, 0x7c, 0xd6, 0x69, 0x37, 0x99, 0xce, 0x66, 0x53, 0xb9, 0xb4, 0xea, 0x5a, 0x01}; +static const t_u16 rg_table_fc_len = 107; +#else +#ifndef CONFIG_11AX +#ifndef CONFIG_11AC +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 10, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, {7, 0}, {8, 0}, {9, 0}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 187, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 9, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 12, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = + {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t + tx_pwrlimit_5g_cfg = + { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 16, + .chan_desc = {.start_freq = 5000, .chan_width = 20, .chan_num = 187}, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 16, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, + {1, 8}, + {2, 8}, + {3, 8}, + {4, 8}, + {5, 8}, + {6, 8}, + {7, 8}, + {8, 8}, + {9, 8}, + {10, 8}, + {11, 8}, + {12, 8}, + {13, 8}, + {14, 8}, + {15, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AC */ +#else +static wifi_txpwrlimit_t tx_pwrlimit_2g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 14, + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 1, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 2, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 3, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 4, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 5, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 6, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 9, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 10, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2407, + .chan_width = 20, + .chan_num = 13, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 2414, + .chan_width = 20, + .chan_num = 14, + }, + .txpwrlimit_entry = {{0, 8}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, +}; + +#ifdef CONFIG_5GHz_SUPPORT +static wifi_txpwrlimit_t tx_pwrlimit_5g_cfg = { + .subband = (wifi_SubBand_t)0x00, + .num_chans = 39, + + .txpwrlimit_config[0] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 36, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[1] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 40, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[2] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 44, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[3] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 48, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[4] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 52, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[5] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 56, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[6] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 60, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[7] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 64, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[8] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 100, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[9] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 104, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[10] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 108, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[11] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 112, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[12] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 116, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[13] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 120, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[14] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 124, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[15] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 128, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[16] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 132, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[17] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 136, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[18] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 140, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[19] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 144, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[20] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 149, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[21] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 153, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[22] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 157, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[23] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 161, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[24] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 165, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[25] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 183, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[26] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 184, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[27] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 185, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[28] = + { + .num_mod_grps = 20, + .chan_desc = {.start_freq = 5000, .chan_width = 20, .chan_num = 187}, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[29] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 188, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[30] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 189, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[31] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 192, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[32] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 196, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[33] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 7, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[34] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 8, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[35] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 11, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[36] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 12, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[37] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 16, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, + .txpwrlimit_config[38] = + { + .num_mod_grps = 20, + .chan_desc = + { + .start_freq = 5000, + .chan_width = 20, + .chan_num = 34, + }, + .txpwrlimit_entry = {{0, 0}, {1, 8}, {2, 8}, {3, 8}, {4, 8}, {5, 8}, {6, 8}, + {7, 8}, {8, 8}, {9, 8}, {10, 8}, {11, 8}, {12, 8}, {13, 8}, + {14, 8}, {15, 8}, {16, 8}, {17, 8}, {18, 8}, {19, 8}}, + }, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_11AX */ +#endif /* CONFIG_COMPRESS_TX_PWTBL */ + +#ifdef CONFIG_11AX +#ifdef CONFIG_COMPRESS_RU_TX_PWTBL +const static uint8_t rutxpowerlimit_cfg_set[] = { + 0x6d, 0x02, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x18, 0x01, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c}; +#else +#define MAX_2G_RU_PWR_CHANNELS 26 +#define MAX_5G_RU_PWR_CHANNELS 69 + +const static wlan_rutxpwrlimit_t rutxpowerlimit_2g_cfg_set = { + .num_chans = MAX_2G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 2407, .width = 20, .chan_num = 11, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 2407, .width = 20, .chan_num = 12, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 2407, .width = 20, .chan_num = 13, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 2407, .width = 40, .chan_num = 1, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 2407, .width = 40, .chan_num = 2, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 2407, .width = 40, .chan_num = 3, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 2407, .width = 40, .chan_num = 4, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 2407, .width = 40, .chan_num = 5, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 2407, .width = 40, .chan_num = 6, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 2407, .width = 40, .chan_num = 7, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 2407, .width = 40, .chan_num = 8, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 2407, .width = 40, .chan_num = 9, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 2407, .width = 40, .chan_num = 10, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 2407, .width = 40, .chan_num = 11, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 2407, .width = 40, .chan_num = 12, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 2407, .width = 40, .chan_num = 13, .ruPower = {-4, -1, 2, 5, 8, 0}}, +}; + +#ifdef CONFIG_5GHz_SUPPORT +const static wlan_rutxpwrlimit_t rutxpowerlimit_5g_cfg_set = { + .num_chans = MAX_5G_RU_PWR_CHANNELS, + .rupwrlimit_config[0] = {.start_freq = 5000, .width = 20, .chan_num = 36, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[1] = {.start_freq = 5000, .width = 20, .chan_num = 40, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[2] = {.start_freq = 5000, .width = 20, .chan_num = 44, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[3] = {.start_freq = 5000, .width = 20, .chan_num = 48, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[4] = {.start_freq = 5000, .width = 20, .chan_num = 52, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[5] = {.start_freq = 5000, .width = 20, .chan_num = 56, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[6] = {.start_freq = 5000, .width = 20, .chan_num = 60, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[7] = {.start_freq = 5000, .width = 20, .chan_num = 64, .ruPower = {-2, 1, 4, 7, 0, 0}}, + + .rupwrlimit_config[8] = {.start_freq = 5000, .width = 20, .chan_num = 100, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[9] = {.start_freq = 5000, .width = 20, .chan_num = 104, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[10] = {.start_freq = 5000, .width = 20, .chan_num = 108, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[11] = {.start_freq = 5000, .width = 20, .chan_num = 112, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[12] = {.start_freq = 5000, .width = 20, .chan_num = 116, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[13] = {.start_freq = 5000, .width = 20, .chan_num = 120, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[14] = {.start_freq = 5000, .width = 20, .chan_num = 124, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[15] = {.start_freq = 5000, .width = 20, .chan_num = 128, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[16] = {.start_freq = 5000, .width = 20, .chan_num = 132, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[17] = {.start_freq = 5000, .width = 20, .chan_num = 136, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[18] = {.start_freq = 5000, .width = 20, .chan_num = 140, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[19] = {.start_freq = 5000, .width = 20, .chan_num = 144, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[20] = {.start_freq = 5000, .width = 20, .chan_num = 149, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[21] = {.start_freq = 5000, .width = 20, .chan_num = 153, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[22] = {.start_freq = 5000, .width = 20, .chan_num = 157, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[23] = {.start_freq = 5000, .width = 20, .chan_num = 161, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[24] = {.start_freq = 5000, .width = 20, .chan_num = 165, .ruPower = {-1, 2, 5, 8, 0, 0}}, + + .rupwrlimit_config[25] = {.start_freq = 5000, .width = 40, .chan_num = 36, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[26] = {.start_freq = 5000, .width = 40, .chan_num = 40, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[27] = {.start_freq = 5000, .width = 40, .chan_num = 44, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[28] = {.start_freq = 5000, .width = 40, .chan_num = 48, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[29] = {.start_freq = 5000, .width = 40, .chan_num = 52, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[30] = {.start_freq = 5000, .width = 40, .chan_num = 56, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[31] = {.start_freq = 5000, .width = 40, .chan_num = 60, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[32] = {.start_freq = 5000, .width = 40, .chan_num = 64, .ruPower = {-5, -2, 1, 4, 7, 0}}, + + .rupwrlimit_config[33] = {.start_freq = 5000, .width = 40, .chan_num = 100, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[34] = {.start_freq = 5000, .width = 40, .chan_num = 104, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[35] = {.start_freq = 5000, .width = 40, .chan_num = 108, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[36] = {.start_freq = 5000, .width = 40, .chan_num = 112, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[37] = {.start_freq = 5000, .width = 40, .chan_num = 116, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[38] = {.start_freq = 5000, .width = 40, .chan_num = 120, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[39] = {.start_freq = 5000, .width = 40, .chan_num = 124, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[40] = {.start_freq = 5000, .width = 40, .chan_num = 128, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[41] = {.start_freq = 5000, .width = 40, .chan_num = 132, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[42] = {.start_freq = 5000, .width = 40, .chan_num = 136, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[43] = {.start_freq = 5000, .width = 40, .chan_num = 140, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[44] = {.start_freq = 5000, .width = 40, .chan_num = 144, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[45] = {.start_freq = 5000, .width = 40, .chan_num = 149, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[46] = {.start_freq = 5000, .width = 40, .chan_num = 153, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[47] = {.start_freq = 5000, .width = 40, .chan_num = 157, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[48] = {.start_freq = 5000, .width = 40, .chan_num = 161, .ruPower = {-4, -1, 2, 5, 8, 0}}, + + .rupwrlimit_config[49] = {.start_freq = 5000, .width = 80, .chan_num = 36, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[50] = {.start_freq = 5000, .width = 80, .chan_num = 40, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[51] = {.start_freq = 5000, .width = 80, .chan_num = 44, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[52] = {.start_freq = 5000, .width = 80, .chan_num = 48, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[53] = {.start_freq = 5000, .width = 80, .chan_num = 52, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[54] = {.start_freq = 5000, .width = 80, .chan_num = 56, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[55] = {.start_freq = 5000, .width = 80, .chan_num = 60, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[56] = {.start_freq = 5000, .width = 80, .chan_num = 64, .ruPower = {-8, -5, -2, 1, 4, 7}}, + + .rupwrlimit_config[57] = {.start_freq = 5000, .width = 80, .chan_num = 100, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[58] = {.start_freq = 5000, .width = 80, .chan_num = 104, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[59] = {.start_freq = 5000, .width = 80, .chan_num = 108, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[60] = {.start_freq = 5000, .width = 80, .chan_num = 112, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[61] = {.start_freq = 5000, .width = 80, .chan_num = 116, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[62] = {.start_freq = 5000, .width = 80, .chan_num = 120, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[63] = {.start_freq = 5000, .width = 80, .chan_num = 124, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[64] = {.start_freq = 5000, .width = 80, .chan_num = 128, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[65] = {.start_freq = 5000, .width = 80, .chan_num = 149, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[66] = {.start_freq = 5000, .width = 80, .chan_num = 153, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[67] = {.start_freq = 5000, .width = 80, .chan_num = 157, .ruPower = {-7, -4, -1, 2, 5, 8}}, + + .rupwrlimit_config[68] = {.start_freq = 5000, .width = 80, .chan_num = 161, .ruPower = {-7, -4, -1, 2, 5, 8}}, +}; +#endif /* CONFIG_5GHz_SUPPORT */ +#endif /* CONFIG_COMPRESS_RU_TX_PWTBL */ +#endif /* CONFIG_11AX */ + +#endif /* _WLAN_TXPWRLIMIT_CFG_WW_H_ */ diff --git a/devices/MCXN235/MCXN235.h b/devices/MCXN235/MCXN235.h new file mode 100644 index 000000000..18de84016 --- /dev/null +++ b/devices/MCXN235/MCXN235.h @@ -0,0 +1,70325 @@ +/* +** ################################################################### +** Processors: MCXN235VDF +** MCXN235VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240409 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN235 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN235.h + * @version 1.0 + * @date 2023-10-01 + * @brief CMSIS Peripheral Access Layer for MCXN235 + * + * CMSIS Peripheral Access Layer for MCXN235 + */ + +#if !defined(MCXN235_H_) +#define MCXN235_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + Reserved49_IRQn = 33, /**< Reserved interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + Reserved70_IRQn = 54, /**< Reserved interrupt */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + Reserved74_IRQn = 58, /**< Reserved interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + Reserved79_IRQn = 63, /**< Reserved interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + Reserved101_IRQn = 85, /**< Reserved interrupt */ + Reserved102_IRQn = 86, /**< Reserved interrupt */ + Reserved103_IRQn = 87, /**< Reserved interrupt */ + Reserved104_IRQn = 88, /**< Reserved interrupt */ + Reserved105_IRQn = 89, /**< Reserved interrupt */ + Reserved106_IRQn = 90, /**< Reserved interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + Reserved122_IRQn = 106, /**< Reserved interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + Reserved134_IRQn = 118, /**< Reserved interrupt */ + Reserved135_IRQn = 119, /**< Reserved interrupt */ + Reserved136_IRQn = 120, /**< Reserved interrupt */ + Reserved137_IRQn = 121, /**< Reserved interrupt */ + Reserved138_IRQn = 122, /**< Reserved interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + Reserved165_IRQn = 149, /**< Reserved interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + Reserved171_IRQn = 155 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN235.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kEIM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kEIM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kEIM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kEIM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kEIM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kEIM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kEIM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kEIM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ +} eim_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ + kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ + kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ + kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ + kEIM_MemoryChannelRAMDEnable = 0x8000000U, /**< Memory channel 4(RAMD) error injection enable */ + kEIM_MemoryChannelRAMEEnable = 0x4000000U, /**< Memory channel 5(RAME) error injection enable */ + kEIM_MemoryChannelRAMFEnable = 0x2000000U, /**< Memory channel 6(RAMF) error injection enable */ + kEIM_MemoryChannelLPCACRAMEnable = 0x1000000U, /**< Memory channel 7(LPCACRAM) error injection enable */ + kEIM_MemoryChannelPKCRAMEnable = 0x800000U, /**< Memory channel 8(PKCRAM) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ + +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kERM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kERM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kERM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kERM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kERM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kERM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kERM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kERM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ + kERM_MemoryChannelFLASH = 9U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[48]; + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_5[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_6[136]; + __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[196]; + __I uint32_t RESFIFO[2]; /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[248]; + __IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset: 0x400 */ + __IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset: 0x404 */ + __IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset: 0x408 */ + __IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset: 0x40C */ + __IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset: 0x410 */ + __IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset: 0x414 */ + __IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset: 0x418 */ + __IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset: 0x41C */ + __IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset: 0x420 */ + __IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset: 0x424 */ + __IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset: 0x428 */ + __IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset: 0x42C */ + __IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset: 0x430 */ + __IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset: 0x434 */ + __IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset: 0x438 */ + __IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset: 0x43C */ + __IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset: 0x440 */ + __IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset: 0x444 */ + __IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset: 0x448 */ + __IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset: 0x44C */ + __IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset: 0x450 */ + __IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset: 0x454 */ + __IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset: 0x458 */ + __IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset: 0x45C */ + __IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset: 0x460 */ + __IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset: 0x464 */ + __IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset: 0x468 */ + __IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset: 0x46C */ + __IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset: 0x470 */ + __IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset: 0x474 */ + __IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset: 0x478 */ + __IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset: 0x47C */ + __IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset: 0x480 */ + uint8_t RESERVED_9[124]; + __IO uint32_t CAL_GBR0; /**< Calibration General B-Side Registers, offset: 0x500 */ + __IO uint32_t CAL_GBR1; /**< Calibration General B-Side Registers, offset: 0x504 */ + __IO uint32_t CAL_GBR2; /**< Calibration General B-Side Registers, offset: 0x508 */ + __IO uint32_t CAL_GBR3; /**< Calibration General B-Side Registers, offset: 0x50C */ + __IO uint32_t CAL_GBR4; /**< Calibration General B-Side Registers, offset: 0x510 */ + __IO uint32_t CAL_GBR5; /**< Calibration General B-Side Registers, offset: 0x514 */ + __IO uint32_t CAL_GBR6; /**< Calibration General B-Side Registers, offset: 0x518 */ + __IO uint32_t CAL_GBR7; /**< Calibration General B-Side Registers, offset: 0x51C */ + __IO uint32_t CAL_GBR8; /**< Calibration General B-Side Registers, offset: 0x520 */ + __IO uint32_t CAL_GBR9; /**< Calibration General B-Side Registers, offset: 0x524 */ + __IO uint32_t CAL_GBR10; /**< Calibration General B-Side Registers, offset: 0x528 */ + __IO uint32_t CAL_GBR11; /**< Calibration General B-Side Registers, offset: 0x52C */ + __IO uint32_t CAL_GBR12; /**< Calibration General B-Side Registers, offset: 0x530 */ + __IO uint32_t CAL_GBR13; /**< Calibration General B-Side Registers, offset: 0x534 */ + __IO uint32_t CAL_GBR14; /**< Calibration General B-Side Registers, offset: 0x538 */ + __IO uint32_t CAL_GBR15; /**< Calibration General B-Side Registers, offset: 0x53C */ + __IO uint32_t CAL_GBR16; /**< Calibration General B-Side Registers, offset: 0x540 */ + __IO uint32_t CAL_GBR17; /**< Calibration General B-Side Registers, offset: 0x544 */ + __IO uint32_t CAL_GBR18; /**< Calibration General B-Side Registers, offset: 0x548 */ + __IO uint32_t CAL_GBR19; /**< Calibration General B-Side Registers, offset: 0x54C */ + __IO uint32_t CAL_GBR20; /**< Calibration General B-Side Registers, offset: 0x550 */ + __IO uint32_t CAL_GBR21; /**< Calibration General B-Side Registers, offset: 0x554 */ + __IO uint32_t CAL_GBR22; /**< Calibration General B-Side Registers, offset: 0x558 */ + __IO uint32_t CAL_GBR23; /**< Calibration General B-Side Registers, offset: 0x55C */ + __IO uint32_t CAL_GBR24; /**< Calibration General B-Side Registers, offset: 0x560 */ + __IO uint32_t CAL_GBR25; /**< Calibration General B-Side Registers, offset: 0x564 */ + __IO uint32_t CAL_GBR26; /**< Calibration General B-Side Registers, offset: 0x568 */ + __IO uint32_t CAL_GBR27; /**< Calibration General B-Side Registers, offset: 0x56C */ + __IO uint32_t CAL_GBR28; /**< Calibration General B-Side Registers, offset: 0x570 */ + __IO uint32_t CAL_GBR29; /**< Calibration General B-Side Registers, offset: 0x574 */ + __IO uint32_t CAL_GBR30; /**< Calibration General B-Side Registers, offset: 0x578 */ + __IO uint32_t CAL_GBR31; /**< Calibration General B-Side Registers, offset: 0x57C */ + __IO uint32_t CAL_GBR32; /**< Calibration General B-Side Registers, offset: 0x580 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential or 12-bit single-ended resolution supported. + * 0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for + * selecting the resolution of conversions for the associated command. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Not supported + * 0b1..Supported. CMDLn[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multiple Vref Implemented + * 0b0..Single VREFH input supported. + * 0b1..Multiple VREFH inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Not supported. + * 0b001..Supported with one-bit CSCALE control field. + * 0b110..Supported with six-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. + * 0b1..Range control required. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single-Ended Outputs Supported + * 0b0..One + * 0b1..Two + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..One + * 0b010..Two + * 0b011..Three + * 0b100..Four + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..2 + * 0b00000100..4 + * 0b00001000..8 + * 0b00010000..16 + * 0b00100000..32 + * 0b01000000..64 + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low-power mode. + * 0b1..ADC is disabled in low-power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request made. + * 0b1..Request has been made. + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgment. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or has not been run. + * 0b1..ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..ADC is idle. There are no pending triggers to service and no active commands are being processed. + * 0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..All disabled + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..All enabled + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..Current conversion is aborted and the new command specified by the trigger is started. + * 0b01..Current command is stopped after completing the current conversion. If averaging is enabled, the + * averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced. + * 0b10..Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b0x..Low power + * 0b1x..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Option 1 + * 0b01..Option 2 + * 0b10..Option 3 + * 0b11.. + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Not automatically resumed or restarted + * 0b1..Automatically resumed or restarted + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequence automatically restarted. + * 0b1..Trigger sequence resumed from the command that was executed prior to the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High-Priority Trigger Exception Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power-up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost + * of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this + * initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - Pause Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high-priority exception. + * 0b0001..Trigger 0 has been interrupted by a high-priority exception. + * 0b0010..Trigger 1 has been interrupted by a high-priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high-priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination for Channel A + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination for Channel B + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level. + * 0b11..Lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (4U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended mode. Only A-side channel is converted. + * 0b01..Single-Ended mode. Only B-side channel is converted. + * 0b10..Differential mode. A-B. + * 0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) + +#define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) +#define ADC_CMDL_ALTB_ADCH_SHIFT (16U) +/*! ALTB_ADCH - Alternate Channel B Input Channel Select + * 0b00000..Select CH0B + * 0b00001..Select CH1B + * 0b00010..Select CH2B + * 0b00011..Select CH3B + * 0b00100-0b11101..Select corresponding channel CHnB + * 0b11110..Select CH30B + * 0b11111..Select CH31B + */ +#define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) + +#define ADC_CMDL_ALTBEN_MASK (0x200000U) +#define ADC_CMDL_ALTBEN_SHIFT (21U) +/*! ALTBEN - Alternate Channel B Select Enable + * 0b0..ALTBEN_ADCH disabled. Channel-A and Channel-B inputs are selected based on ADCH settings. + * 0b1..ALTBEN_ADCH enabled. Channel-A inputs are selected by ADCH setting and Channel-B inputs are selected by ALTB_ADCH setting. + */ +#define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Disabled + * 0b01.. + * 0b10..Enabled. Store on true. + * 0b11..Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion Before Execution + * 0b0..Command executes automatically. + * 0b1..Active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..5.5 ADCK cycles + * 0b010..7.5 ADCK cycles + * 0b011..11.5 ADCK cycles + * 0b100..19.5 ADCK cycles + * 0b101..35.5 ADCK cycles + * 0b110..67.5 ADCK cycles + * 0b111..131.5 ADCK cycles + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes one time. + * 0b0001..Loop one time. Command executes two times. + * 0b0010..Loop two times. Command executes three times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..CMD1 + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..CMD15 + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (15U) + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 + * 0b01..Trigger source 1 + * 0b10..Trigger source 2 + * 0b11..Trigger source 3 + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state, + * prior to the storage of an ADC conversion result into a RESFIFO buffer. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO contains data. FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR0 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR0_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR1 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK (0xFFFU) +#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR1_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR2 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR2_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR3 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR3_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR4 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR4_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR5 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR5_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR6 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR6_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR7 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR7_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR8 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR8_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR9 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR9_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR10 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR10_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR11 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR11_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR12 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR12_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR13 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR13_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR14 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR14_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR15 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR15_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR16 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR16_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR17 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR17_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR18 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR18_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR19 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR19_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR20 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR20_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR21 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR21_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR22 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR22_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR23 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR23_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR24 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR24_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR25 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR25_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR26 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR26_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR27 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR27_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR28 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR28_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR29 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR29_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR30 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR30_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR31 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR31_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR32 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR32_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR0 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR0_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR0_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR0_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR1 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR1_CAL_GBR_VAL_MASK (0xFFFU) +#define ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR1_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR1_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR2 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR2_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR2_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR2_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR3 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR3_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR3_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR3_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR4 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR4_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR4_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR4_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR5 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR5_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR5_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR5_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR6 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR6_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR6_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR6_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR7 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR7_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR7_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR7_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR8 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR8_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR8_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR8_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR9 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR9_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR9_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR9_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR10 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR10_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR10_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR10_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR11 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR11_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR11_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR11_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR12 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR12_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR12_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR12_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR13 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR13_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR13_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR13_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR14 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR14_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR14_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR14_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR15 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR15_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR15_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR15_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR16 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR16_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR16_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR16_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR17 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR17_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR17_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR17_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR18 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR18_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR18_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR18_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR19 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR19_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR19_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR19_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR20 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR20_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR20_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR20_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR21 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR21_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR21_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR21_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR22 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR22_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR22_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR22_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR23 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR23_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR23_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR23_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR24 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR24_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR24_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR24_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR25 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR25_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR25_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR25_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR26 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR26_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR26_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR26_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR27 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR27_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR27_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR27_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR28 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR28_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR28_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR28_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR29 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR29_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR29_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR29_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR30 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR30_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR30_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR30_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR31 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR31_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR31_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR31_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR32 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR32_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR32_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR32_CAL_GBR_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHBSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Peripheral_Access_Layer AHBSC Peripheral Access Layer + * @{ + */ + +/** AHBSC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t FLASH00_MEM_RULE[4]; /**< Flash Memory Rule, array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t FLASH02_MEM_RULE; /**< Flash Memory Rule, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t FLASH03_MEM_RULE; /**< Flash Memory Rule, offset: 0x40 */ + uint8_t RESERVED_3[28]; + __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RAMX_MEM_RULE[3]; /**< RAMX Memory Rule, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t RAMA_MEM_RULE; /**< RAMA Memory Rule 0, offset: 0xA0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RAMB_MEM_RULE; /**< RAMB Memory Rule, offset: 0xC0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t RAMC_MEM_RULE[2]; /**< RAMC Memory Rule, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t RAMD_MEM_RULE[2]; /**< RAMD Memory Rule, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t RAME_MEM_RULE[2]; /**< RAME Memory Rule, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x1A0 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x1A4 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x1A8 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x1AC */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x1B0 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x1B4 */ + uint8_t RESERVED_11[4]; + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x1BC */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE0; /**< AIPS Bridge Group 0 Memory Rule 0, offset: 0x1C0 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE1; /**< AIPS Bridge Group 0 Memory Rule 1, offset: 0x1C4 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE2; /**< AIPS Bridge Group 0 Memory Rule 2, offset: 0x1C8 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE3; /**< AIPS Bridge Group 0 Memory Rule 3, offset: 0x1CC */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 0, offset: 0x1D0 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 1, offset: 0x1D4 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 2, offset: 0x1D8 */ + uint8_t RESERVED_12[4]; + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x1E0 */ + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x1E4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 0, offset: 0x1F0 */ + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 1, offset: 0x1F4 */ + uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 2, offset: 0x1F8 */ + uint8_t RESERVED_14[4]; + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE0; /**< AIPS Bridge Group 2 Rule 0, offset: 0x200 */ + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE1; /**< AIPS Bridge Group 2 Memory Rule 1, offset: 0x204 */ + uint8_t RESERVED_15[24]; + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE0; /**< AIPS Bridge Group 3 Rule 0, offset: 0x220 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE1; /**< AIPS Bridge Group 3 Memory Rule 1, offset: 0x224 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE2; /**< AIPS Bridge Group 3 Rule 2, offset: 0x228 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE3; /**< AIPS Bridge Group 3 Rule 3, offset: 0x22C */ + uint8_t RESERVED_16[16]; + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE0; /**< AIPS Bridge Group 4 Rule 0, offset: 0x240 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE1; /**< AIPS Bridge Group 4 Rule 1, offset: 0x244 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE2; /**< AIPS Bridge Group 4 Rule 2, offset: 0x248 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE3; /**< AIPS Bridge Group 4 Rule 3, offset: 0x24C */ + __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0; /**< AHB Secure Control Peripheral Rule 0, offset: 0x250 */ + uint8_t RESERVED_17[2988]; + __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ + __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ + uint8_t RESERVED_18[124]; + __IO uint32_t SEC_GPIO_MASK[2]; /**< GPIO Mask for Port 0..GPIO Mask for Port 1, array offset: 0xF80, array step: 0x4 */ + uint8_t RESERVED_19[72]; + __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ + uint8_t RESERVED_20[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */ + uint8_t RESERVED_21[8]; + __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ +} AHBSC_Type; + +/* ---------------------------------------------------------------------------- + -- AHBSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Register_Masks AHBSC Register Masks + * @{ + */ + +/*! @name FLASH00_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH00_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_FLASH00_MEM_RULE */ +#define AHBSC_FLASH00_MEM_RULE_COUNT (4U) + +/*! @name FLASH02_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH02_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE3_MASK) +/*! @} */ + +/*! @name FLASH03_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH03_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name ROM_MEM_RULE - ROM Memory Rule */ +/*! @{ */ + +#define AHBSC_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE0_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE1_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE2_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE3_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE4_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE5_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE6_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_ROM_MEM_RULE */ +#define AHBSC_ROM_MEM_RULE_COUNT (4U) + +/*! @name RAMX_MEM_RULE0_RAMX_MEM_RULE - RAMX Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_COUNT (3U) + +/*! @name RAMA_MEM_RULE - RAMA Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_RAMA_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMA_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMA_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMA_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMA_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMA_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMA_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMA_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMA_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMB_MEM_RULE - RAMB Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMB_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMB_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMB_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMB_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMB_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMB_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMB_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMB_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMB_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMC_MEM_RULE - RAMC Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMC_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMC_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMC_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMC_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMC_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMC_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMC_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMC_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMC_MEM_RULE */ +#define AHBSC_RAMC_MEM_RULE_COUNT (2U) + +/*! @name RAMD_MEM_RULE - RAMD Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMD_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMD_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMD_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMD_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMD_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMD_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMD_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMD_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMD_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMD_MEM_RULE */ +#define AHBSC_RAMD_MEM_RULE_COUNT (2U) + +/*! @name RAME_MEM_RULE - RAME Memory Rule */ +/*! @{ */ + +#define AHBSC_RAME_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAME_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAME_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAME_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAME_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAME_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAME_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAME_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAME_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAME_MEM_RULE */ +#define AHBSC_RAME_MEM_RULE_COUNT (2U) + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) +/*! SYSCON - SYSCON + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) +/*! PINT0 - PINT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT (24U) +/*! INPUTMUX - INPUTMUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (16U) +/*! CTIMER0 - CTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (20U) +/*! CTIMER1 - CTIMER1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT (24U) +/*! CTIMER2 - CTIMER2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT (28U) +/*! CTIMER3 - CTIMER3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT (0U) +/*! CTIMER4 - CTIMER4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT (4U) +/*! FREQME0 - FREQME0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT (8U) +/*! UTCIK0 - UTCIK0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT (12U) +/*! MRT0 - MRT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT (16U) +/*! OSTIMER0 - OSTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT (24U) +/*! WWDT0 - WWDT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT (28U) +/*! WWDT1 - WWDT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT (12U) +/*! CACHE64_POLSEL0 - CACHE64_POLSEL0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT (4U) +/*! I3C0 - I3C0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT (8U) +/*! I3C1 - I3C1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT (20U) +/*! GDET - GDET + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT (24U) +/*! ITRC - ITRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (12U) +/*! PKC - PKC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT (16U) +/*! PUF_ALIAS0 - PUF_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT (20U) +/*! PUF_ALIAS1 - PUF_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT (24U) +/*! PUF_ALIAS2 - PUF_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT (28U) +/*! PUF_ALIAS3 - PUF_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT (8U) +/*! COOLFLUX - COOLFLUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT (12U) +/*! SMARTDMA - SmartDMA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT (16U) +/*! PLU - PLU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE0 - AIPS Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT (0U) +/*! GPIO5_ALIAS0 - GPIO5_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT (4U) +/*! GPIO5_ALIAS1 - GPIO5_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT (8U) +/*! PORT5 - PORT5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT (12U) +/*! FMU0 - FMU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT (16U) +/*! SCG0 - SCG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT (20U) +/*! SPC0 - SPC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT (24U) +/*! WUU0 - WUU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE1 - AIPS Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT (8U) +/*! LPTMR0 - LPTMR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT (12U) +/*! LPTMR1 - LPTMR1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT (16U) +/*! RTC - RTC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT (24U) +/*! FMU_TEST - FMU_TEST + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE2 - AIPS Bridge Group 0 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT (0U) +/*! TSI - TSI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT (8U) +/*! CMP1 - CMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT (12U) +/*! CMP2 - CMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT (16U) +/*! ELS - ELS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT (20U) +/*! ELS_ALIAS1 - ELS_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT (24U) +/*! ELS_ALIAS2 - ELS_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT (28U) +/*! ELS_ALIAS3 - ELS_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE3 - AIPS Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT (0U) +/*! DIGTMP - DIGTMP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT (4U) +/*! VBAT - VBAT + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT (8U) +/*! TRNG - TRNG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT (12U) +/*! EIM0 - EIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT (16U) +/*! ERM0 - ERM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT (20U) +/*! INTM0 - INTM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT (4U) +/*! eDMA0_CH15 - eDMA0_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT (8U) +/*! SCT0 - SCT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT (12U) +/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT (16U) +/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT (20U) +/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT (24U) +/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT (28U) +/*! GPIO0_ALIAS0 - GPIO0_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT (0U) +/*! GPIO0_ALIAS1 - GPIO0_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT (4U) +/*! GPIO1_ALIAS0 - GPIO1_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT (8U) +/*! GPIO1_ALIAS1 - GPIO1_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT (12U) +/*! GPIO2_ALIAS0 - GPIO2_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT (16U) +/*! GPIO2_ALIAS1 - GPIO2_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT (20U) +/*! GPIO3_ALIAS0 - GPIO3_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT (24U) +/*! GPIO3_ALIAS1 - GPIO3_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT (28U) +/*! GPIO4_ALIAS0 - GPIO4_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT (0U) +/*! GPIO4_ALIAS1 - GPIO4_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE0 - AIPS Bridge Group 1 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT (0U) +/*! eDMA0_MP - eDMA0_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT (4U) +/*! eDMA0_CH0 - eDMA0_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT (8U) +/*! eDMA0_CH1 - eDMA0_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT (12U) +/*! eDMA0_CH2 - eDMA0_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT (16U) +/*! eDMA0_CH3 - FLEXSPI0 Registers + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT (20U) +/*! eDMA0_CH4 - eDMA0_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT (24U) +/*! eDMA0_CH5 - eDMA0_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT (28U) +/*! eDMA0_CH6 - eDMA0_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE1 - AIPS Bridge Group 1 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT (0U) +/*! eDMA0_CH7 - eDMA0_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT (4U) +/*! eDMA0_CH8 - eDMA0_CH8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT (8U) +/*! eDMA0_CH9 - eDMA0_CH9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT (12U) +/*! eDMA0_CH10 - eDMA0_CH10 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT (16U) +/*! eDMA0_CH11 - FLEXSPI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT (20U) +/*! eDMA0_CH12 - eDMA0_CH12 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT (24U) +/*! eDMA0_CH13 - eDMA0_CH13 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT (28U) +/*! eDMA0_CH14 - eDMA0_CH14 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT (4U) +/*! eDMA1_CH15 - eDMA1_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT (8U) +/*! SEMA42 - SEMA42 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT (12U) +/*! MAILBOX - MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT (16U) +/*! PKC_RAM - PKC_RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT (20U) +/*! FLEXCOMM4 - FLEXCOMM4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT (24U) +/*! FLEXCOMM5 - FLEXCOMM5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT (28U) +/*! FLEXCOMM6 - FLEXCOMM6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT (0U) +/*! FLEXCOMM7 - FLEXCOMM7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT (4U) +/*! FLEXCOMM8 - FLEXCOMM8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT (8U) +/*! FLEXCOMM9 - FLEXCOMM9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT (12U) +/*! USB_FS_OTG_RAM - USB FS OTG RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT (16U) +/*! CDOG0 - CDOG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT (20U) +/*! CDOG1 - CDOG1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT (24U) +/*! DEBUG_MAILBOX - DEBUG_MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT (28U) +/*! NPU - NPU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE0 - AIPS Bridge Group 2 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT (0U) +/*! eDMA1_MP - eDMA1_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT (4U) +/*! eDMA1_CH0 - eDMA1_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT (8U) +/*! eDMA1_CH1 - eDMA1_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT (12U) +/*! eDMA1_CH2 - eDMA1_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT (16U) +/*! eDMA1_CH3 - eDMA1_CH3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT (20U) +/*! eDMA1_CH4 - eDMA1_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT (24U) +/*! eDMA1_CH5 - eDMA1_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT (28U) +/*! eDMA1_CH6 - eDMA1_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE1 - AIPS Bridge Group 2 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT (0U) +/*! eDMA1_CH7 - eDMA1_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE0 - AIPS Bridge Group 3 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT (0U) +/*! EWM0 - EWM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT (4U) +/*! LPCAC - LPCAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT (8U) +/*! FLEXSPI_CMX - FLEXSPI_CMX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT (20U) +/*! SFA - SFA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT (28U) +/*! MBC - MBC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE1 - AIPS Bridge Group 3 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT (0U) +/*! FLEXSPI - FLEXSPI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT (4U) +/*! OTPC - OTPC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT (12U) +/*! CRC - CRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT (16U) +/*! NPX - NPX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT (24U) +/*! PWM - PWM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT (28U) +/*! QDC - QDC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE2 - AIPS Bridge Group 3 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT (0U) +/*! PWM1 - PWM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT (4U) +/*! QDC1 - QDC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT (8U) +/*! EVTG - EVTG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT (16U) +/*! CAN0_RULE0 - CAN0 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT (20U) +/*! CAN0_RULE1 - CAN0 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT (24U) +/*! CAN0_RULE2 - CAN0 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT (28U) +/*! CAN0_RULE3 - CAN0 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE3 - AIPS Bridge Group 3 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT (0U) +/*! CAN1_RULE0 - CAN1 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT (4U) +/*! CAN1_RULE1 - CAN1 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT (8U) +/*! CAN1_RULE2 - CAN1 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT (12U) +/*! CAN1_RULE3 - CAN1 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT (16U) +/*! USBDCD - USBDCD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT (20U) +/*! USBFS - USBFS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE0 - AIPS Bridge Group 4 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK (0xFU) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT (0U) +/*! ENET - ENET + * 0b0000..Non-secure and non-privilege user access allowed + * 0b0001..Non-secure and privilege access allowed + * 0b0010..Secure and non-privilege user access allowed + * 0b0011..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT (12U) +/*! EMVSIM0 - EMVSIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT (16U) +/*! EMVSIM1 - EMVSIM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT (20U) +/*! FLEXIO - FLEXIO + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT (24U) +/*! SAI0 - SAI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT (28U) +/*! SAI1 - SAI1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE1 - AIPS Bridge Group 4 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT (0U) +/*! SINC0 - SINC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT (4U) +/*! uSDHC0 - uSDHC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT (8U) +/*! USBHSPHY - USBHSPHY + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT (12U) +/*! USBHS - USBHS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT (16U) +/*! MICD - MICD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT (20U) +/*! ADC0 - ADC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT (24U) +/*! ADC1 - ADC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT (28U) +/*! DAC0 - DAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE2 - AIPS Bridge Group 4 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT (0U) +/*! OPAMP0 - OPAMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT (4U) +/*! VREF - VREF + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT (8U) +/*! DAC - DAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT (12U) +/*! OPAMP1 - OPAMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT (16U) +/*! HPDAC0 - HPDAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT (20U) +/*! OPAMP2 - OPAMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT (24U) +/*! PORT0 - PORT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT (28U) +/*! PORT1 - PORT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE3 - AIPS Bridge Group 4 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT (0U) +/*! PORT2 - PORT2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT (4U) +/*! PORT3 - PORT3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT (8U) +/*! PORT4 - PORT4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT (24U) +/*! MTR0 - MTR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT (28U) +/*! ATX0 - ATX0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK) +/*! @} */ + +/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) + +/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator + * 0b0..Read access + * 0b1..Write access + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access + * 0b0..Code + * 0b1..Data + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - Security violation master number + * 0b00000..M33 Code + * 0b00001..M33 System + * 0b00011..SMARTDMA Instruction + * 0b00101..SMARTDMA Data + * 0b00110..eDMA0 + * 0b00111..eDMA1 + * 0b01000..PKC + * 0b01001..ELS S50 + * 0b01010..PKC M0 + * 0b01011..NPU Operands + * 0b01100..DSP Instruction + * 0b01101..DSPX + * 0b01110..DSPY + * 0b10000..NPU Data + * 0b10010..Ethernet + * 0b10011..USB HS + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) + +/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) +/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) +/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) +/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) +/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) +/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) +/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) +/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 1 */ +/*! @{ */ + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (2U) + +/*! @name MASTER_SEC_LEVEL - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PKC_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - Master SEC Level Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master SEC Level Antipol Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */ +/*! @{ */ + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - LOCK_NS_VTOR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 + * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - LOCK_NS_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 + * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - LOCK_S_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - LOCK_SAU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_SAU is 1 + * 0b10..CM33 (CPU0) LOCK_SAU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK + * 0b00..Reserved + * 0b01..CM33_LOCK_REG_LOCK is 1 + * 0b10..CM33_LOCK_REG_LOCK is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of secure mode access. + * 0b10..Disables the privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of non-secure mode access. + * 0b10..Disables the privilege checking of non-secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master can access memories and peripherals at the same level or below that level. + * 0b10..Master can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - Secure Control */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of secure mode access. + * 0b10..Disables privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of non-secure mode access. + * 0b10..Disables privilege checking of non-secure mode access is disabled. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level + * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHBSC_Register_Masks */ + + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group AHBSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[32]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[21]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[12]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[7]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[32]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[4]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (32U) + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (32U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[2]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[88]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[8]; + __I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */ + __IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SRAMDIS[1]; /**< SRAM Disable, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[12]; + __IO uint32_t SRAMRET[1]; /**< SRAM Retention, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_6[12]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ + uint8_t RESERVED_8[8]; + __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..No clock gating + * 0b0001..Core clock is gated + * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock not gated + * 0b0001..Core clock was gated + * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode + * *.. + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/* The count of CMC_PMCTRL */ +#define CMC_PMCTRL_COUNT (2U) + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CPU1_MASK (0x10000U) +#define CMC_SRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CPU1_SHIFT)) & CMC_SRS_CPU1_MASK) + +#define CMC_SRS_VBAT_MASK (0x1000000U) +#define CMC_SRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK) + +#define CMC_SRS_WWDT1_MASK (0x2000000U) +#define CMC_SRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT1_SHIFT)) & CMC_SRS_WWDT1_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_CDOG1_MASK (0x8000000U) +#define CMC_SRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) + +#define CMC_SRS_SECVIO_MASK (0x40000000U) +#define CMC_SRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK) + +#define CMC_SRS_TAMPER_MASK (0x80000000U) +#define CMC_SRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CPU1_MASK (0x10000U) +#define CMC_SSRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset not generated from CPU1 reset source. + * 0b1..Reset generated from CPU1 reset source. + */ +#define CMC_SSRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CPU1_SHIFT)) & CMC_SSRS_CPU1_MASK) + +#define CMC_SSRS_VBAT_MASK (0x1000000U) +#define CMC_SSRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK) + +#define CMC_SSRS_WWDT1_MASK (0x2000000U) +#define CMC_SSRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT1_SHIFT)) & CMC_SSRS_WWDT1_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_CDOG1_MASK (0x8000000U) +#define CMC_SSRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) + +#define CMC_SSRS_SECVIO_MASK (0x40000000U) +#define CMC_SSRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK) + +#define CMC_SSRS_TAMPER_MASK (0x80000000U) +#define CMC_SSRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CPU1_MASK (0x10000U) +#define CMC_SRIE_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CPU1_SHIFT)) & CMC_SRIE_CPU1_MASK) + +#define CMC_SRIE_VBAT_MASK (0x1000000U) +#define CMC_SRIE_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_VBAT_SHIFT)) & CMC_SRIE_VBAT_MASK) + +#define CMC_SRIE_WWDT1_MASK (0x2000000U) +#define CMC_SRIE_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT1_SHIFT)) & CMC_SRIE_WWDT1_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) + +#define CMC_SRIE_CDOG1_MASK (0x8000000U) +#define CMC_SRIE_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CPU1_MASK (0x10000U) +#define CMC_SRIF_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CPU1_SHIFT)) & CMC_SRIF_CPU1_MASK) + +#define CMC_SRIF_VBAT_MASK (0x1000000U) +#define CMC_SRIF_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_VBAT_SHIFT)) & CMC_SRIF_VBAT_MASK) + +#define CMC_SRIF_WWDT1_MASK (0x2000000U) +#define CMC_SRIF_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT1_SHIFT)) & CMC_SRIF_WWDT1_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) + +#define CMC_SRIF_CDOG1_MASK (0x8000000U) +#define CMC_SRIF_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK) +/*! @} */ + +/*! @name RSTCNT - Reset Count Register */ +/*! @{ */ + +#define CMC_RSTCNT_COUNT_MASK (0xFFU) +#define CMC_RSTCNT_COUNT_SHIFT (0U) +/*! COUNT - Count */ +#define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/* The count of CMC_MR */ +#define CMC_MR_COUNT (1U) + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/* The count of CMC_FM */ +#define CMC_FM_COUNT (1U) + +/*! @name SRAMDIS - SRAM Disable */ +/*! @{ */ + +#define CMC_SRAMDIS_DIS0_MASK (0x1U) +#define CMC_SRAMDIS_DIS0_SHIFT (0U) +/*! DIS0 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) + +#define CMC_SRAMDIS_DIS1_MASK (0x2U) +#define CMC_SRAMDIS_DIS1_SHIFT (1U) +/*! DIS1 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) + +#define CMC_SRAMDIS_DIS2_MASK (0x4U) +#define CMC_SRAMDIS_DIS2_SHIFT (2U) +/*! DIS2 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) + +#define CMC_SRAMDIS_DIS3_MASK (0x8U) +#define CMC_SRAMDIS_DIS3_SHIFT (3U) +/*! DIS3 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) + +#define CMC_SRAMDIS_DIS4_MASK (0x10U) +#define CMC_SRAMDIS_DIS4_SHIFT (4U) +/*! DIS4 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) + +#define CMC_SRAMDIS_DIS5_MASK (0x20U) +#define CMC_SRAMDIS_DIS5_SHIFT (5U) +/*! DIS5 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) + +#define CMC_SRAMDIS_DIS6_MASK (0x40U) +#define CMC_SRAMDIS_DIS6_SHIFT (6U) +/*! DIS6 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) + +#define CMC_SRAMDIS_DIS7_MASK (0x80U) +#define CMC_SRAMDIS_DIS7_SHIFT (7U) +/*! DIS7 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) + +#define CMC_SRAMDIS_DIS8_MASK (0x100U) +#define CMC_SRAMDIS_DIS8_SHIFT (8U) +/*! DIS8 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) + +#define CMC_SRAMDIS_DIS9_MASK (0x200U) +#define CMC_SRAMDIS_DIS9_SHIFT (9U) +/*! DIS9 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) + +#define CMC_SRAMDIS_DIS10_MASK (0x400U) +#define CMC_SRAMDIS_DIS10_SHIFT (10U) +/*! DIS10 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) + +#define CMC_SRAMDIS_DIS11_MASK (0x800U) +#define CMC_SRAMDIS_DIS11_SHIFT (11U) +/*! DIS11 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) + +#define CMC_SRAMDIS_DIS12_MASK (0x1000U) +#define CMC_SRAMDIS_DIS12_SHIFT (12U) +/*! DIS12 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) + +#define CMC_SRAMDIS_DIS13_MASK (0x2000U) +#define CMC_SRAMDIS_DIS13_SHIFT (13U) +/*! DIS13 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) + +#define CMC_SRAMDIS_DIS14_MASK (0x4000U) +#define CMC_SRAMDIS_DIS14_SHIFT (14U) +/*! DIS14 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) + +#define CMC_SRAMDIS_DIS15_MASK (0x8000U) +#define CMC_SRAMDIS_DIS15_SHIFT (15U) +/*! DIS15 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) + +#define CMC_SRAMDIS_DIS16_MASK (0x10000U) +#define CMC_SRAMDIS_DIS16_SHIFT (16U) +/*! DIS16 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) + +#define CMC_SRAMDIS_DIS17_MASK (0x20000U) +#define CMC_SRAMDIS_DIS17_SHIFT (17U) +/*! DIS17 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) + +#define CMC_SRAMDIS_DIS18_MASK (0x40000U) +#define CMC_SRAMDIS_DIS18_SHIFT (18U) +/*! DIS18 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) + +#define CMC_SRAMDIS_DIS19_MASK (0x80000U) +#define CMC_SRAMDIS_DIS19_SHIFT (19U) +/*! DIS19 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) + +#define CMC_SRAMDIS_DIS20_MASK (0x100000U) +#define CMC_SRAMDIS_DIS20_SHIFT (20U) +/*! DIS20 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) + +#define CMC_SRAMDIS_DIS21_MASK (0x200000U) +#define CMC_SRAMDIS_DIS21_SHIFT (21U) +/*! DIS21 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) + +#define CMC_SRAMDIS_DIS22_MASK (0x400000U) +#define CMC_SRAMDIS_DIS22_SHIFT (22U) +/*! DIS22 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) + +#define CMC_SRAMDIS_DIS23_MASK (0x800000U) +#define CMC_SRAMDIS_DIS23_SHIFT (23U) +/*! DIS23 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) + +#define CMC_SRAMDIS_DIS24_MASK (0x1000000U) +#define CMC_SRAMDIS_DIS24_SHIFT (24U) +/*! DIS24 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) + +#define CMC_SRAMDIS_DIS25_MASK (0x2000000U) +#define CMC_SRAMDIS_DIS25_SHIFT (25U) +/*! DIS25 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) + +#define CMC_SRAMDIS_DIS26_MASK (0x4000000U) +#define CMC_SRAMDIS_DIS26_SHIFT (26U) +/*! DIS26 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) + +#define CMC_SRAMDIS_DIS27_MASK (0x8000000U) +#define CMC_SRAMDIS_DIS27_SHIFT (27U) +/*! DIS27 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) + +#define CMC_SRAMDIS_DIS28_MASK (0x10000000U) +#define CMC_SRAMDIS_DIS28_SHIFT (28U) +/*! DIS28 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) + +#define CMC_SRAMDIS_DIS29_MASK (0x20000000U) +#define CMC_SRAMDIS_DIS29_SHIFT (29U) +/*! DIS29 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) + +#define CMC_SRAMDIS_DIS30_MASK (0x40000000U) +#define CMC_SRAMDIS_DIS30_SHIFT (30U) +/*! DIS30 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) + +#define CMC_SRAMDIS_DIS31_MASK (0x80000000U) +#define CMC_SRAMDIS_DIS31_SHIFT (31U) +/*! DIS31 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) +/*! @} */ + +/* The count of CMC_SRAMDIS */ +#define CMC_SRAMDIS_COUNT (1U) + +/*! @name SRAMRET - SRAM Retention */ +/*! @{ */ + +#define CMC_SRAMRET_RET0_MASK (0x1U) +#define CMC_SRAMRET_RET0_SHIFT (0U) +/*! RET0 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) + +#define CMC_SRAMRET_RET1_MASK (0x2U) +#define CMC_SRAMRET_RET1_SHIFT (1U) +/*! RET1 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) + +#define CMC_SRAMRET_RET2_MASK (0x4U) +#define CMC_SRAMRET_RET2_SHIFT (2U) +/*! RET2 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) + +#define CMC_SRAMRET_RET3_MASK (0x8U) +#define CMC_SRAMRET_RET3_SHIFT (3U) +/*! RET3 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) + +#define CMC_SRAMRET_RET4_MASK (0x10U) +#define CMC_SRAMRET_RET4_SHIFT (4U) +/*! RET4 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) + +#define CMC_SRAMRET_RET5_MASK (0x20U) +#define CMC_SRAMRET_RET5_SHIFT (5U) +/*! RET5 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) + +#define CMC_SRAMRET_RET6_MASK (0x40U) +#define CMC_SRAMRET_RET6_SHIFT (6U) +/*! RET6 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) + +#define CMC_SRAMRET_RET7_MASK (0x80U) +#define CMC_SRAMRET_RET7_SHIFT (7U) +/*! RET7 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) + +#define CMC_SRAMRET_RET8_MASK (0x100U) +#define CMC_SRAMRET_RET8_SHIFT (8U) +/*! RET8 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) + +#define CMC_SRAMRET_RET9_MASK (0x200U) +#define CMC_SRAMRET_RET9_SHIFT (9U) +/*! RET9 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) + +#define CMC_SRAMRET_RET10_MASK (0x400U) +#define CMC_SRAMRET_RET10_SHIFT (10U) +/*! RET10 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) + +#define CMC_SRAMRET_RET11_MASK (0x800U) +#define CMC_SRAMRET_RET11_SHIFT (11U) +/*! RET11 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) + +#define CMC_SRAMRET_RET12_MASK (0x1000U) +#define CMC_SRAMRET_RET12_SHIFT (12U) +/*! RET12 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) + +#define CMC_SRAMRET_RET13_MASK (0x2000U) +#define CMC_SRAMRET_RET13_SHIFT (13U) +/*! RET13 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) + +#define CMC_SRAMRET_RET14_MASK (0x4000U) +#define CMC_SRAMRET_RET14_SHIFT (14U) +/*! RET14 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) + +#define CMC_SRAMRET_RET15_MASK (0x8000U) +#define CMC_SRAMRET_RET15_SHIFT (15U) +/*! RET15 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) + +#define CMC_SRAMRET_RET16_MASK (0x10000U) +#define CMC_SRAMRET_RET16_SHIFT (16U) +/*! RET16 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) + +#define CMC_SRAMRET_RET17_MASK (0x20000U) +#define CMC_SRAMRET_RET17_SHIFT (17U) +/*! RET17 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) + +#define CMC_SRAMRET_RET18_MASK (0x40000U) +#define CMC_SRAMRET_RET18_SHIFT (18U) +/*! RET18 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) + +#define CMC_SRAMRET_RET19_MASK (0x80000U) +#define CMC_SRAMRET_RET19_SHIFT (19U) +/*! RET19 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) + +#define CMC_SRAMRET_RET20_MASK (0x100000U) +#define CMC_SRAMRET_RET20_SHIFT (20U) +/*! RET20 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) + +#define CMC_SRAMRET_RET21_MASK (0x200000U) +#define CMC_SRAMRET_RET21_SHIFT (21U) +/*! RET21 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) + +#define CMC_SRAMRET_RET22_MASK (0x400000U) +#define CMC_SRAMRET_RET22_SHIFT (22U) +/*! RET22 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) + +#define CMC_SRAMRET_RET23_MASK (0x800000U) +#define CMC_SRAMRET_RET23_SHIFT (23U) +/*! RET23 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) + +#define CMC_SRAMRET_RET24_MASK (0x1000000U) +#define CMC_SRAMRET_RET24_SHIFT (24U) +/*! RET24 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) + +#define CMC_SRAMRET_RET25_MASK (0x2000000U) +#define CMC_SRAMRET_RET25_SHIFT (25U) +/*! RET25 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) + +#define CMC_SRAMRET_RET26_MASK (0x4000000U) +#define CMC_SRAMRET_RET26_SHIFT (26U) +/*! RET26 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) + +#define CMC_SRAMRET_RET27_MASK (0x8000000U) +#define CMC_SRAMRET_RET27_SHIFT (27U) +/*! RET27 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) + +#define CMC_SRAMRET_RET28_MASK (0x10000000U) +#define CMC_SRAMRET_RET28_SHIFT (28U) +/*! RET28 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) + +#define CMC_SRAMRET_RET29_MASK (0x20000000U) +#define CMC_SRAMRET_RET29_SHIFT (29U) +/*! RET29 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) + +#define CMC_SRAMRET_RET30_MASK (0x40000000U) +#define CMC_SRAMRET_RET30_SHIFT (30U) +/*! RET30 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) + +#define CMC_SRAMRET_RET31_MASK (0x80000000U) +#define CMC_SRAMRET_RET31_SHIFT (31U) +/*! RET31 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) +/*! @} */ + +/* The count of CMC_SRAMRET */ +#define CMC_SRAMRET_COUNT (1U) + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) +/*! @} */ + +/*! @name BSR - BootROM Status Register */ +/*! @{ */ + +#define CMC_BSR_STAT_MASK (0xFFFFFFFFU) +#define CMC_BSR_STAT_SHIFT (0U) +/*! STAT - Provides status information written by the BootROM. */ +#define CMC_BSR_STAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK) +/*! @} */ + +/*! @name BLR - BootROM Lock Register */ +/*! @{ */ + +#define CMC_BLR_LOCK_MASK (0x7U) +#define CMC_BLR_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b010..BootROM Status and Lock Registers can be written + * 0b101..BootROM Status and Lock Registers cannot be written + */ +#define CMC_BLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif +/* Backward compatibility for CMC */ +#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) +#define CMC_SRAMDIS_DIS_SHIFT (0U) +/*! DIS - SRAM Disable */ +#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) + +#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) +#define CMC_SRAMRET_RET_SHIFT (0U) +/*! RET - SRAM Retention */ +#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) + + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DIGTMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer + * @{ + */ + +/** DIGTMP - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t LR; /**< Lock, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t TSR; /**< Tamper Seconds, offset: 0x20 */ + __IO uint32_t TER; /**< Tamper Enable, offset: 0x24 */ + __IO uint32_t PDR; /**< Pin Direction, offset: 0x28 */ + __IO uint32_t PPR; /**< Pin Polarity, offset: 0x2C */ + __IO uint32_t ATR[2]; /**< Active Tamper, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t PGFR[8]; /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */ +} DIGTMP_Type; + +/* ---------------------------------------------------------------------------- + -- DIGTMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define DIGTMP_CR_SWR_MASK (0x1U) +#define DIGTMP_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect + * 0b1..Perform a software reset + */ +#define DIGTMP_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK) + +#define DIGTMP_CR_DEN_MASK (0x2U) +#define DIGTMP_CR_DEN_SHIFT (1U) +/*! DEN - Digital Tamper Enable + * 0b0..Disables TDET clock and prescaler + * 0b1..Enables TDET clock and prescaler + */ +#define DIGTMP_CR_DEN(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK) + +#define DIGTMP_CR_TFSR_MASK (0x4U) +#define DIGTMP_CR_TFSR_SHIFT (2U) +/*! TFSR - Tamper Force System Reset + * 0b0..Do not force chip reset + * 0b1..Force chip reset + */ +#define DIGTMP_CR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK) + +#define DIGTMP_CR_UM_MASK (0x8U) +#define DIGTMP_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..No effect + * 0b1..Allows the clearing of interrupts + */ +#define DIGTMP_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK) + +#define DIGTMP_CR_ATCS0_MASK (0x10U) +#define DIGTMP_CR_ATCS0_SHIFT (4U) +/*! ATCS0 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS0_SHIFT)) & DIGTMP_CR_ATCS0_MASK) + +#define DIGTMP_CR_ATCS1_MASK (0x20U) +#define DIGTMP_CR_ATCS1_SHIFT (5U) +/*! ATCS1 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS1_SHIFT)) & DIGTMP_CR_ATCS1_MASK) + +#define DIGTMP_CR_DISTAM_MASK (0x100U) +#define DIGTMP_CR_DISTAM_SHIFT (8U) +/*! DISTAM - Disable Prescaler On Tamper + * 0b0..No effect + * 0b1..Automatically disables the prescaler after tamper detection + */ +#define DIGTMP_CR_DISTAM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK) + +#define DIGTMP_CR_DPR_MASK (0xFFFE0000U) +#define DIGTMP_CR_DPR_SHIFT (17U) +/*! DPR - Digital Tamper Prescaler */ +#define DIGTMP_CR_DPR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define DIGTMP_SR_DTF_MASK (0x1U) +#define DIGTMP_SR_DTF_SHIFT (0U) +/*! DTF - Digital Tamper Flag + * 0b0..TDET tampering not detected + * 0b1..TDET tampering detected + */ +#define DIGTMP_SR_DTF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK) + +#define DIGTMP_SR_TAF_MASK (0x2U) +#define DIGTMP_SR_TAF_SHIFT (1U) +/*! TAF - Tamper Acknowledge Flag + * 0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set. + * 0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set. + */ +#define DIGTMP_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK) + +#define DIGTMP_SR_TIF0_MASK (0x4U) +#define DIGTMP_SR_TIF0_SHIFT (2U) +/*! TIF0 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK) + +#define DIGTMP_SR_TIF1_MASK (0x8U) +#define DIGTMP_SR_TIF1_SHIFT (3U) +/*! TIF1 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK) + +#define DIGTMP_SR_TIF2_MASK (0x10U) +#define DIGTMP_SR_TIF2_SHIFT (4U) +/*! TIF2 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK) + +#define DIGTMP_SR_TIF3_MASK (0x20U) +#define DIGTMP_SR_TIF3_SHIFT (5U) +/*! TIF3 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK) + +#define DIGTMP_SR_TIF4_MASK (0x40U) +#define DIGTMP_SR_TIF4_SHIFT (6U) +/*! TIF4 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK) + +#define DIGTMP_SR_TIF5_MASK (0x80U) +#define DIGTMP_SR_TIF5_SHIFT (7U) +/*! TIF5 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK) + +#define DIGTMP_SR_TIF6_MASK (0x100U) +#define DIGTMP_SR_TIF6_SHIFT (8U) +/*! TIF6 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK) + +#define DIGTMP_SR_TIF7_MASK (0x200U) +#define DIGTMP_SR_TIF7_SHIFT (9U) +/*! TIF7 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK) + +#define DIGTMP_SR_TIF8_MASK (0x400U) +#define DIGTMP_SR_TIF8_SHIFT (10U) +/*! TIF8 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK) + +#define DIGTMP_SR_TIF9_MASK (0x800U) +#define DIGTMP_SR_TIF9_SHIFT (11U) +/*! TIF9 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK) + +#define DIGTMP_SR_TPF0_MASK (0x10000U) +#define DIGTMP_SR_TPF0_SHIFT (16U) +/*! TPF0 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK) + +#define DIGTMP_SR_TPF1_MASK (0x20000U) +#define DIGTMP_SR_TPF1_SHIFT (17U) +/*! TPF1 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK) + +#define DIGTMP_SR_TPF2_MASK (0x40000U) +#define DIGTMP_SR_TPF2_SHIFT (18U) +/*! TPF2 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK) + +#define DIGTMP_SR_TPF3_MASK (0x80000U) +#define DIGTMP_SR_TPF3_SHIFT (19U) +/*! TPF3 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK) + +#define DIGTMP_SR_TPF4_MASK (0x100000U) +#define DIGTMP_SR_TPF4_SHIFT (20U) +/*! TPF4 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK) + +#define DIGTMP_SR_TPF5_MASK (0x200000U) +#define DIGTMP_SR_TPF5_SHIFT (21U) +/*! TPF5 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK) + +#define DIGTMP_SR_TPF6_MASK (0x400000U) +#define DIGTMP_SR_TPF6_SHIFT (22U) +/*! TPF6 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF6_SHIFT)) & DIGTMP_SR_TPF6_MASK) + +#define DIGTMP_SR_TPF7_MASK (0x800000U) +#define DIGTMP_SR_TPF7_SHIFT (23U) +/*! TPF7 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF7_SHIFT)) & DIGTMP_SR_TPF7_MASK) +/*! @} */ + +/*! @name LR - Lock */ +/*! @{ */ + +#define DIGTMP_LR_CRL_MASK (0x10U) +#define DIGTMP_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK) + +#define DIGTMP_LR_SRL_MASK (0x20U) +#define DIGTMP_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK) + +#define DIGTMP_LR_LRL_MASK (0x40U) +#define DIGTMP_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK) + +#define DIGTMP_LR_IEL_MASK (0x80U) +#define DIGTMP_LR_IEL_SHIFT (7U) +/*! IEL - Interrupt Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_IEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK) + +#define DIGTMP_LR_TSL_MASK (0x100U) +#define DIGTMP_LR_TSL_SHIFT (8U) +/*! TSL - Tamper Seconds Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TSL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK) + +#define DIGTMP_LR_TEL_MASK (0x200U) +#define DIGTMP_LR_TEL_SHIFT (9U) +/*! TEL - Tamper Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK) + +#define DIGTMP_LR_PDL_MASK (0x400U) +#define DIGTMP_LR_PDL_SHIFT (10U) +/*! PDL - Pin Direction Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PDL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PDL_SHIFT)) & DIGTMP_LR_PDL_MASK) + +#define DIGTMP_LR_PPL_MASK (0x800U) +#define DIGTMP_LR_PPL_SHIFT (11U) +/*! PPL - Pin Polarity Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PPL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK) + +#define DIGTMP_LR_ATL0_MASK (0x1000U) +#define DIGTMP_LR_ATL0_SHIFT (12U) +/*! ATL0 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL0_SHIFT)) & DIGTMP_LR_ATL0_MASK) + +#define DIGTMP_LR_ATL1_MASK (0x2000U) +#define DIGTMP_LR_ATL1_SHIFT (13U) +/*! ATL1 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL1_SHIFT)) & DIGTMP_LR_ATL1_MASK) + +#define DIGTMP_LR_GFL0_MASK (0x10000U) +#define DIGTMP_LR_GFL0_SHIFT (16U) +/*! GFL0 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK) + +#define DIGTMP_LR_GFL1_MASK (0x20000U) +#define DIGTMP_LR_GFL1_SHIFT (17U) +/*! GFL1 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK) + +#define DIGTMP_LR_GFL2_MASK (0x40000U) +#define DIGTMP_LR_GFL2_SHIFT (18U) +/*! GFL2 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK) + +#define DIGTMP_LR_GFL3_MASK (0x80000U) +#define DIGTMP_LR_GFL3_SHIFT (19U) +/*! GFL3 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK) + +#define DIGTMP_LR_GFL4_MASK (0x100000U) +#define DIGTMP_LR_GFL4_SHIFT (20U) +/*! GFL4 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK) + +#define DIGTMP_LR_GFL5_MASK (0x200000U) +#define DIGTMP_LR_GFL5_SHIFT (21U) +/*! GFL5 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK) + +#define DIGTMP_LR_GFL6_MASK (0x400000U) +#define DIGTMP_LR_GFL6_SHIFT (22U) +/*! GFL6 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL6_SHIFT)) & DIGTMP_LR_GFL6_MASK) + +#define DIGTMP_LR_GFL7_MASK (0x800000U) +#define DIGTMP_LR_GFL7_SHIFT (23U) +/*! GFL7 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL7_SHIFT)) & DIGTMP_LR_GFL7_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define DIGTMP_IER_DTIE_MASK (0x1U) +#define DIGTMP_IER_DTIE_SHIFT (0U) +/*! DTIE - Digital Tamper Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK) + +#define DIGTMP_IER_TIIE0_MASK (0x4U) +#define DIGTMP_IER_TIIE0_SHIFT (2U) +/*! TIIE0 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK) + +#define DIGTMP_IER_TIIE1_MASK (0x8U) +#define DIGTMP_IER_TIIE1_SHIFT (3U) +/*! TIIE1 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK) + +#define DIGTMP_IER_TIIE2_MASK (0x10U) +#define DIGTMP_IER_TIIE2_SHIFT (4U) +/*! TIIE2 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK) + +#define DIGTMP_IER_TIIE3_MASK (0x20U) +#define DIGTMP_IER_TIIE3_SHIFT (5U) +/*! TIIE3 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK) + +#define DIGTMP_IER_TIIE4_MASK (0x40U) +#define DIGTMP_IER_TIIE4_SHIFT (6U) +/*! TIIE4 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK) + +#define DIGTMP_IER_TIIE5_MASK (0x80U) +#define DIGTMP_IER_TIIE5_SHIFT (7U) +/*! TIIE5 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK) + +#define DIGTMP_IER_TIIE6_MASK (0x100U) +#define DIGTMP_IER_TIIE6_SHIFT (8U) +/*! TIIE6 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK) + +#define DIGTMP_IER_TIIE7_MASK (0x200U) +#define DIGTMP_IER_TIIE7_SHIFT (9U) +/*! TIIE7 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK) + +#define DIGTMP_IER_TIIE8_MASK (0x400U) +#define DIGTMP_IER_TIIE8_SHIFT (10U) +/*! TIIE8 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK) + +#define DIGTMP_IER_TIIE9_MASK (0x800U) +#define DIGTMP_IER_TIIE9_SHIFT (11U) +/*! TIIE9 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK) + +#define DIGTMP_IER_TPIE0_MASK (0x10000U) +#define DIGTMP_IER_TPIE0_SHIFT (16U) +/*! TPIE0 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK) + +#define DIGTMP_IER_TPIE1_MASK (0x20000U) +#define DIGTMP_IER_TPIE1_SHIFT (17U) +/*! TPIE1 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK) + +#define DIGTMP_IER_TPIE2_MASK (0x40000U) +#define DIGTMP_IER_TPIE2_SHIFT (18U) +/*! TPIE2 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK) + +#define DIGTMP_IER_TPIE3_MASK (0x80000U) +#define DIGTMP_IER_TPIE3_SHIFT (19U) +/*! TPIE3 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK) + +#define DIGTMP_IER_TPIE4_MASK (0x100000U) +#define DIGTMP_IER_TPIE4_SHIFT (20U) +/*! TPIE4 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK) + +#define DIGTMP_IER_TPIE5_MASK (0x200000U) +#define DIGTMP_IER_TPIE5_SHIFT (21U) +/*! TPIE5 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK) + +#define DIGTMP_IER_TPIE6_MASK (0x400000U) +#define DIGTMP_IER_TPIE6_SHIFT (22U) +/*! TPIE6 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE6_SHIFT)) & DIGTMP_IER_TPIE6_MASK) + +#define DIGTMP_IER_TPIE7_MASK (0x800000U) +#define DIGTMP_IER_TPIE7_SHIFT (23U) +/*! TPIE7 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE7_SHIFT)) & DIGTMP_IER_TPIE7_MASK) +/*! @} */ + +/*! @name TSR - Tamper Seconds */ +/*! @{ */ + +#define DIGTMP_TSR_TTS_MASK (0xFFFFFFFFU) +#define DIGTMP_TSR_TTS_SHIFT (0U) +/*! TTS - Tamper Time Seconds */ +#define DIGTMP_TSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK) +/*! @} */ + +/*! @name TER - Tamper Enable */ +/*! @{ */ + +#define DIGTMP_TER_TIE0_MASK (0x4U) +#define DIGTMP_TER_TIE0_SHIFT (2U) +/*! TIE0 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK) + +#define DIGTMP_TER_TIE1_MASK (0x8U) +#define DIGTMP_TER_TIE1_SHIFT (3U) +/*! TIE1 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK) + +#define DIGTMP_TER_TIE2_MASK (0x10U) +#define DIGTMP_TER_TIE2_SHIFT (4U) +/*! TIE2 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK) + +#define DIGTMP_TER_TIE3_MASK (0x20U) +#define DIGTMP_TER_TIE3_SHIFT (5U) +/*! TIE3 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK) + +#define DIGTMP_TER_TIE4_MASK (0x40U) +#define DIGTMP_TER_TIE4_SHIFT (6U) +/*! TIE4 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK) + +#define DIGTMP_TER_TIE5_MASK (0x80U) +#define DIGTMP_TER_TIE5_SHIFT (7U) +/*! TIE5 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK) + +#define DIGTMP_TER_TIE6_MASK (0x100U) +#define DIGTMP_TER_TIE6_SHIFT (8U) +/*! TIE6 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK) + +#define DIGTMP_TER_TIE7_MASK (0x200U) +#define DIGTMP_TER_TIE7_SHIFT (9U) +/*! TIE7 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK) + +#define DIGTMP_TER_TIE8_MASK (0x400U) +#define DIGTMP_TER_TIE8_SHIFT (10U) +/*! TIE8 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK) + +#define DIGTMP_TER_TIE9_MASK (0x800U) +#define DIGTMP_TER_TIE9_SHIFT (11U) +/*! TIE9 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK) + +#define DIGTMP_TER_TPE0_MASK (0x10000U) +#define DIGTMP_TER_TPE0_SHIFT (16U) +/*! TPE0 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK) + +#define DIGTMP_TER_TPE1_MASK (0x20000U) +#define DIGTMP_TER_TPE1_SHIFT (17U) +/*! TPE1 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK) + +#define DIGTMP_TER_TPE2_MASK (0x40000U) +#define DIGTMP_TER_TPE2_SHIFT (18U) +/*! TPE2 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK) + +#define DIGTMP_TER_TPE3_MASK (0x80000U) +#define DIGTMP_TER_TPE3_SHIFT (19U) +/*! TPE3 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK) + +#define DIGTMP_TER_TPE4_MASK (0x100000U) +#define DIGTMP_TER_TPE4_SHIFT (20U) +/*! TPE4 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK) + +#define DIGTMP_TER_TPE5_MASK (0x200000U) +#define DIGTMP_TER_TPE5_SHIFT (21U) +/*! TPE5 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK) + +#define DIGTMP_TER_TPE6_MASK (0x400000U) +#define DIGTMP_TER_TPE6_SHIFT (22U) +/*! TPE6 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE6_SHIFT)) & DIGTMP_TER_TPE6_MASK) + +#define DIGTMP_TER_TPE7_MASK (0x800000U) +#define DIGTMP_TER_TPE7_SHIFT (23U) +/*! TPE7 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE7_SHIFT)) & DIGTMP_TER_TPE7_MASK) +/*! @} */ + +/*! @name PDR - Pin Direction */ +/*! @{ */ + +#define DIGTMP_PDR_TPD0_MASK (0x1U) +#define DIGTMP_PDR_TPD0_SHIFT (0U) +/*! TPD0 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD0_SHIFT)) & DIGTMP_PDR_TPD0_MASK) + +#define DIGTMP_PDR_TPD1_MASK (0x2U) +#define DIGTMP_PDR_TPD1_SHIFT (1U) +/*! TPD1 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD1_SHIFT)) & DIGTMP_PDR_TPD1_MASK) + +#define DIGTMP_PDR_TPD2_MASK (0x4U) +#define DIGTMP_PDR_TPD2_SHIFT (2U) +/*! TPD2 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD2_SHIFT)) & DIGTMP_PDR_TPD2_MASK) + +#define DIGTMP_PDR_TPD3_MASK (0x8U) +#define DIGTMP_PDR_TPD3_SHIFT (3U) +/*! TPD3 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD3_SHIFT)) & DIGTMP_PDR_TPD3_MASK) + +#define DIGTMP_PDR_TPD4_MASK (0x10U) +#define DIGTMP_PDR_TPD4_SHIFT (4U) +/*! TPD4 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD4_SHIFT)) & DIGTMP_PDR_TPD4_MASK) + +#define DIGTMP_PDR_TPD5_MASK (0x20U) +#define DIGTMP_PDR_TPD5_SHIFT (5U) +/*! TPD5 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD5_SHIFT)) & DIGTMP_PDR_TPD5_MASK) + +#define DIGTMP_PDR_TPD6_MASK (0x40U) +#define DIGTMP_PDR_TPD6_SHIFT (6U) +/*! TPD6 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD6_SHIFT)) & DIGTMP_PDR_TPD6_MASK) + +#define DIGTMP_PDR_TPD7_MASK (0x80U) +#define DIGTMP_PDR_TPD7_SHIFT (7U) +/*! TPD7 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD7_SHIFT)) & DIGTMP_PDR_TPD7_MASK) + +#define DIGTMP_PDR_TPOD0_MASK (0x10000U) +#define DIGTMP_PDR_TPOD0_SHIFT (16U) +/*! TPOD0 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD0_SHIFT)) & DIGTMP_PDR_TPOD0_MASK) + +#define DIGTMP_PDR_TPOD1_MASK (0x20000U) +#define DIGTMP_PDR_TPOD1_SHIFT (17U) +/*! TPOD1 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD1_SHIFT)) & DIGTMP_PDR_TPOD1_MASK) + +#define DIGTMP_PDR_TPOD2_MASK (0x40000U) +#define DIGTMP_PDR_TPOD2_SHIFT (18U) +/*! TPOD2 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD2_SHIFT)) & DIGTMP_PDR_TPOD2_MASK) + +#define DIGTMP_PDR_TPOD3_MASK (0x80000U) +#define DIGTMP_PDR_TPOD3_SHIFT (19U) +/*! TPOD3 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD3_SHIFT)) & DIGTMP_PDR_TPOD3_MASK) + +#define DIGTMP_PDR_TPOD4_MASK (0x100000U) +#define DIGTMP_PDR_TPOD4_SHIFT (20U) +/*! TPOD4 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD4_SHIFT)) & DIGTMP_PDR_TPOD4_MASK) + +#define DIGTMP_PDR_TPOD5_MASK (0x200000U) +#define DIGTMP_PDR_TPOD5_SHIFT (21U) +/*! TPOD5 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD5_SHIFT)) & DIGTMP_PDR_TPOD5_MASK) + +#define DIGTMP_PDR_TPOD6_MASK (0x400000U) +#define DIGTMP_PDR_TPOD6_SHIFT (22U) +/*! TPOD6 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD6_SHIFT)) & DIGTMP_PDR_TPOD6_MASK) + +#define DIGTMP_PDR_TPOD7_MASK (0x800000U) +#define DIGTMP_PDR_TPOD7_SHIFT (23U) +/*! TPOD7 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD7_SHIFT)) & DIGTMP_PDR_TPOD7_MASK) +/*! @} */ + +/*! @name PPR - Pin Polarity */ +/*! @{ */ + +#define DIGTMP_PPR_TPP0_MASK (0x1U) +#define DIGTMP_PPR_TPP0_SHIFT (0U) +/*! TPP0 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK) + +#define DIGTMP_PPR_TPP1_MASK (0x2U) +#define DIGTMP_PPR_TPP1_SHIFT (1U) +/*! TPP1 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK) + +#define DIGTMP_PPR_TPP2_MASK (0x4U) +#define DIGTMP_PPR_TPP2_SHIFT (2U) +/*! TPP2 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK) + +#define DIGTMP_PPR_TPP3_MASK (0x8U) +#define DIGTMP_PPR_TPP3_SHIFT (3U) +/*! TPP3 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK) + +#define DIGTMP_PPR_TPP4_MASK (0x10U) +#define DIGTMP_PPR_TPP4_SHIFT (4U) +/*! TPP4 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK) + +#define DIGTMP_PPR_TPP5_MASK (0x20U) +#define DIGTMP_PPR_TPP5_SHIFT (5U) +/*! TPP5 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK) + +#define DIGTMP_PPR_TPP6_MASK (0x40U) +#define DIGTMP_PPR_TPP6_SHIFT (6U) +/*! TPP6 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP6_SHIFT)) & DIGTMP_PPR_TPP6_MASK) + +#define DIGTMP_PPR_TPP7_MASK (0x80U) +#define DIGTMP_PPR_TPP7_SHIFT (7U) +/*! TPP7 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP7_SHIFT)) & DIGTMP_PPR_TPP7_MASK) + +#define DIGTMP_PPR_TPID0_MASK (0x10000U) +#define DIGTMP_PPR_TPID0_SHIFT (16U) +/*! TPID0 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK) + +#define DIGTMP_PPR_TPID1_MASK (0x20000U) +#define DIGTMP_PPR_TPID1_SHIFT (17U) +/*! TPID1 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK) + +#define DIGTMP_PPR_TPID2_MASK (0x40000U) +#define DIGTMP_PPR_TPID2_SHIFT (18U) +/*! TPID2 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK) + +#define DIGTMP_PPR_TPID3_MASK (0x80000U) +#define DIGTMP_PPR_TPID3_SHIFT (19U) +/*! TPID3 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK) + +#define DIGTMP_PPR_TPID4_MASK (0x100000U) +#define DIGTMP_PPR_TPID4_SHIFT (20U) +/*! TPID4 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK) + +#define DIGTMP_PPR_TPID5_MASK (0x200000U) +#define DIGTMP_PPR_TPID5_SHIFT (21U) +/*! TPID5 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK) + +#define DIGTMP_PPR_TPID6_MASK (0x400000U) +#define DIGTMP_PPR_TPID6_SHIFT (22U) +/*! TPID6 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID6_SHIFT)) & DIGTMP_PPR_TPID6_MASK) + +#define DIGTMP_PPR_TPID7_MASK (0x800000U) +#define DIGTMP_PPR_TPID7_SHIFT (23U) +/*! TPID7 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID7_SHIFT)) & DIGTMP_PPR_TPID7_MASK) +/*! @} */ + +/*! @name ATR - Active Tamper */ +/*! @{ */ + +#define DIGTMP_ATR_ATSR_MASK (0xFFFFU) +#define DIGTMP_ATR_ATSR_SHIFT (0U) +/*! ATSR - Active Tamper Shift Register */ +#define DIGTMP_ATR_ATSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATSR_SHIFT)) & DIGTMP_ATR_ATSR_MASK) + +#define DIGTMP_ATR_ATP_MASK (0xFFFF0000U) +#define DIGTMP_ATR_ATP_SHIFT (16U) +/*! ATP - Active Tamper Polynomial */ +#define DIGTMP_ATR_ATP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATP_SHIFT)) & DIGTMP_ATR_ATP_MASK) +/*! @} */ + +/* The count of DIGTMP_ATR */ +#define DIGTMP_ATR_COUNT (2U) + +/*! @name PGFR - Pin Glitch Filter */ +/*! @{ */ + +#define DIGTMP_PGFR_GFW_MASK (0x3FU) +#define DIGTMP_PGFR_GFW_SHIFT (0U) +/*! GFW - Glitch Filter Width */ +#define DIGTMP_PGFR_GFW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK) + +#define DIGTMP_PGFR_GFP_MASK (0x40U) +#define DIGTMP_PGFR_GFP_SHIFT (6U) +/*! GFP - Glitch Filter Prescaler + * 0b0..512 Hz prescaler clock + * 0b1..32.768 kHz clock + */ +#define DIGTMP_PGFR_GFP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK) + +#define DIGTMP_PGFR_GFE_MASK (0x80U) +#define DIGTMP_PGFR_GFE_SHIFT (7U) +/*! GFE - Glitch Filter Enable + * 0b0..Bypasses + * 0b1..Enables + */ +#define DIGTMP_PGFR_GFE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK) + +#define DIGTMP_PGFR_TPSW_MASK (0x300U) +#define DIGTMP_PGFR_TPSW_SHIFT (8U) +/*! TPSW - Tamper Pin Sample Width + * 0b00..Continuous monitoring, pin sampling disabled + * 0b01..2 cycles for pull enable and 1 cycle for input buffer enable + * 0b10..4 cycles for pull enable and 2 cycles for input buffer enable + * 0b11..8 cycles for pull enable and 4 cycles for input buffer enable + */ +#define DIGTMP_PGFR_TPSW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK) + +#define DIGTMP_PGFR_TPSF_MASK (0xC00U) +#define DIGTMP_PGFR_TPSF_SHIFT (10U) +/*! TPSF - Tamper Pin Sample Frequency + * 0b00..Every 8 cycles + * 0b01..Every 32 cycles + * 0b10..Every 128 cycles + * 0b11..Every 512 cycles + */ +#define DIGTMP_PGFR_TPSF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK) + +#define DIGTMP_PGFR_TPEX_MASK (0x30000U) +#define DIGTMP_PGFR_TPEX_SHIFT (16U) +/*! TPEX - Tamper Pin Expected + * 0b00..Zero/passive tamper + * 0b01..Active Tamper 0 output + * 0b10..Active Tamper 1 output + * 0b11..Active Tamper 0 output XORed with Active Tamper 1 output + */ +#define DIGTMP_PGFR_TPEX(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPEX_SHIFT)) & DIGTMP_PGFR_TPEX_MASK) + +#define DIGTMP_PGFR_TPE_MASK (0x1000000U) +#define DIGTMP_PGFR_TPE_SHIFT (24U) +/*! TPE - Tamper Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_PGFR_TPE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK) + +#define DIGTMP_PGFR_TPS_MASK (0x2000000U) +#define DIGTMP_PGFR_TPS_SHIFT (25U) +/*! TPS - Tamper Pull Select + * 0b0..Asserts + * 0b1..Negates + */ +#define DIGTMP_PGFR_TPS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK) +/*! @} */ + +/* The count of DIGTMP_PGFR */ +#define DIGTMP_PGFR_COUNT (8U) + + +/*! + * @} + */ /* end of group DIGTMP_Register_Masks */ + + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/*! + * @} + */ /* end of group DIGTMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Peripheral_Access_Layer DM Peripheral Access Layer + * @{ + */ + +/** DM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DM_Type; + +/* ---------------------------------------------------------------------------- + -- DM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Register_Masks DM Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DM_CSW_RESYNCH_REQ_MASK (0x1U) +#define DM_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DM_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_RESYNCH_REQ_SHIFT)) & DM_CSW_RESYNCH_REQ_MASK) + +#define DM_CSW_REQ_PENDING_MASK (0x2U) +#define DM_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DM_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_REQ_PENDING_SHIFT)) & DM_CSW_REQ_PENDING_MASK) + +#define DM_CSW_DBG_OR_ERR_MASK (0x4U) +#define DM_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No DBGMB Overrun error + * 0b1..DBGMB overrun error. A DBGMB overrun occurred. + */ +#define DM_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_DBG_OR_ERR_SHIFT)) & DM_CSW_DBG_OR_ERR_MASK) + +#define DM_CSW_AHB_OR_ERR_MASK (0x8U) +#define DM_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No AHB Overrun Error + * 0b1..AHB Overrun Error. An AHB overrun occurred. + */ +#define DM_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_AHB_OR_ERR_SHIFT)) & DM_CSW_AHB_OR_ERR_MASK) + +#define DM_CSW_SOFT_RESET_MASK (0x10U) +#define DM_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset */ +#define DM_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_SOFT_RESET_SHIFT)) & DM_CSW_SOFT_RESET_MASK) + +#define DM_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DM_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request */ +#define DM_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_CHIP_RESET_REQ_SHIFT)) & DM_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DM_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DM_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DM_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DM_REQUEST_REQUEST_SHIFT)) & DM_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DM_RETURN_RET_MASK (0xFFFFFFFFU) +#define DM_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DM_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DM_RETURN_RET_SHIFT)) & DM_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DM_ID_ID_MASK (0xFFFFFFFFU) +#define DM_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DM_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DM_ID_ID_SHIFT)) & DM_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DM_Register_Masks */ + + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/*! + * @} + */ /* end of group DM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[16]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[3776]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000, irregular array, not all indices are valid */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + }; + uint8_t RESERVED_1[4032]; + } CH[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFFFU) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (16U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (16U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (16U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (16U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0x1FU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_SEC_MASK (0x4000U) +#define DMA_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define DMA_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (16U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (16U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (16U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (16U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (16U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (16U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (16U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (16U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (16U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (16U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (16U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0xF00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (16U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (16U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Peripheral_Access_Layer DMA0_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA0_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA0_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Register_Masks DMA0_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Register_Masks */ + + +/* DMA0_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x50080000u) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE_NS (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x50081000u) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE_NS (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x50082000u) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE_NS (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x50083000u) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE_NS (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x50084000u) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE_NS (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x50085000u) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE_NS (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x50086000u) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE_NS (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x50087000u) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE_NS (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x50088000u) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE_NS (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x50089000u) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE_NS (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x5008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE_NS (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x5008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE_NS (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x5008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE_NS (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x5008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE_NS (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x5008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE_NS (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x5008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE_NS (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x50090000u) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE_NS (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE_NS) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS_NS { DMA0_TEE_ALIAS0_BASE_NS, DMA0_TEE_ALIAS1_BASE_NS, DMA0_TEE_ALIAS2_BASE_NS, DMA0_TEE_ALIAS3_BASE_NS, DMA0_TEE_ALIAS4_BASE_NS, DMA0_TEE_ALIAS5_BASE_NS, DMA0_TEE_ALIAS6_BASE_NS, DMA0_TEE_ALIAS7_BASE_NS, DMA0_TEE_ALIAS8_BASE_NS, DMA0_TEE_ALIAS9_BASE_NS, DMA0_TEE_ALIAS10_BASE_NS, DMA0_TEE_ALIAS11_BASE_NS, DMA0_TEE_ALIAS12_BASE_NS, DMA0_TEE_ALIAS13_BASE_NS, DMA0_TEE_ALIAS14_BASE_NS, DMA0_TEE_ALIAS15_BASE_NS, DMA0_TEE_ALIAS16_BASE_NS } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS_NS { DMA0_TEE_ALIAS0_NS, DMA0_TEE_ALIAS1_NS, DMA0_TEE_ALIAS2_NS, DMA0_TEE_ALIAS3_NS, DMA0_TEE_ALIAS4_NS, DMA0_TEE_ALIAS5_NS, DMA0_TEE_ALIAS6_NS, DMA0_TEE_ALIAS7_NS, DMA0_TEE_ALIAS8_NS, DMA0_TEE_ALIAS9_NS, DMA0_TEE_ALIAS10_NS, DMA0_TEE_ALIAS11_NS, DMA0_TEE_ALIAS12_NS, DMA0_TEE_ALIAS13_NS, DMA0_TEE_ALIAS14_NS, DMA0_TEE_ALIAS15_NS, DMA0_TEE_ALIAS16_NS } +#else + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } +#endif + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Peripheral_Access_Layer DMA1_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA1_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA1_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Register_Masks DMA1_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Register_Masks */ + + +/* DMA1_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x500A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE_NS (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x500A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE_NS (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x500A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE_NS (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x500A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE_NS (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x500A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE_NS (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x500A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE_NS (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x500A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE_NS (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x500A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE_NS (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x500A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE_NS (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE_NS) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS_NS { DMA1_TEE_ALIAS0_BASE_NS, DMA1_TEE_ALIAS1_BASE_NS, DMA1_TEE_ALIAS2_BASE_NS, DMA1_TEE_ALIAS3_BASE_NS, DMA1_TEE_ALIAS4_BASE_NS, DMA1_TEE_ALIAS5_BASE_NS, DMA1_TEE_ALIAS6_BASE_NS, DMA1_TEE_ALIAS7_BASE_NS, DMA1_TEE_ALIAS8_BASE_NS } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS_NS { DMA1_TEE_ALIAS0_NS, DMA1_TEE_ALIAS1_NS, DMA1_TEE_ALIAS2_NS, DMA1_TEE_ALIAS3_NS, DMA1_TEE_ALIAS4_NS, DMA1_TEE_ALIAS5_NS, DMA1_TEE_ALIAS6_NS, DMA1_TEE_ALIAS7_NS, DMA1_TEE_ALIAS8_NS } +#else + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } +#endif + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ + uint8_t RESERVED_1[56]; + __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ + __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ + uint8_t RESERVED_2[56]; + __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ + __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ + uint8_t RESERVED_3[56]; + __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ + __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ + uint8_t RESERVED_4[56]; + __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ + __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ + uint8_t RESERVED_5[56]; + __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ + __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ + uint8_t RESERVED_6[56]; + __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ + __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ + uint8_t RESERVED_7[56]; + __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ + __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ + uint8_t RESERVED_8[56]; + __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ + __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH8EN_MASK (0x800000U) +#define EIM_EICHEN_EICH8EN_SHIFT (23U) +/*! EICH8EN - Error Injection Channel 8 Enable + * 0b0..Error injection is disabled on Error Injection Channel 8 + * 0b1..Error injection is enabled on Error Injection Channel 8 + */ +#define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) + +#define EIM_EICHEN_EICH7EN_MASK (0x1000000U) +#define EIM_EICHEN_EICH7EN_SHIFT (24U) +/*! EICH7EN - Error Injection Channel 7 Enable + * 0b0..Error injection is disabled on Error Injection Channel 7 + * 0b1..Error injection is enabled on Error Injection Channel 7 + */ +#define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) + +#define EIM_EICHEN_EICH6EN_MASK (0x2000000U) +#define EIM_EICHEN_EICH6EN_SHIFT (25U) +/*! EICH6EN - Error Injection Channel 6 Enable + * 0b0..Error injection is disabled on Error Injection Channel 6 + * 0b1..Error injection is enabled on Error Injection Channel 6 + */ +#define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) + +#define EIM_EICHEN_EICH5EN_MASK (0x4000000U) +#define EIM_EICHEN_EICH5EN_SHIFT (26U) +/*! EICH5EN - Error Injection Channel 5 Enable + * 0b0..Error injection is disabled on Error Injection Channel 5 + * 0b1..Error injection is enabled on Error Injection Channel 5 + */ +#define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) + +#define EIM_EICHEN_EICH4EN_MASK (0x8000000U) +#define EIM_EICHEN_EICH4EN_SHIFT (27U) +/*! EICH4EN - Error Injection Channel 4 Enable + * 0b0..Error injection is disabled on Error Injection Channel 4 + * 0b1..Error injection is enabled on Error Injection Channel 4 + */ +#define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) + +#define EIM_EICHEN_EICH3EN_MASK (0x10000000U) +#define EIM_EICHEN_EICH3EN_SHIFT (28U) +/*! EICH3EN - Error Injection Channel 3 Enable + * 0b0..Error injection is disabled on Error Injection Channel 3 + * 0b1..Error injection is enabled on Error Injection Channel 3 + */ +#define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) + +#define EIM_EICHEN_EICH2EN_MASK (0x20000000U) +#define EIM_EICHEN_EICH2EN_SHIFT (29U) +/*! EICH2EN - Error Injection Channel 2 Enable + * 0b0..Error injection is disabled on Error Injection Channel 2 + * 0b1..Error injection is enabled on Error Injection Channel 2 + */ +#define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) + +#define EIM_EICHEN_EICH1EN_MASK (0x40000000U) +#define EIM_EICHEN_EICH1EN_SHIFT (30U) +/*! EICH1EN - Error Injection Channel 1 Enable + * 0b0..Error injection is disabled on Error Injection Channel 1 + * 0b1..Error injection is enabled on Error Injection Channel 1 + */ +#define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ +/*! @{ */ + +#define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ +/*! @{ */ + +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ +/*! @{ */ + +#define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ +/*! @{ */ + +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ +/*! @{ */ + +#define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ +/*! @{ */ + +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ +/*! @{ */ + +#define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ +/*! @{ */ + +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ +/*! @{ */ + +#define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ +/*! @{ */ + +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ +/*! @{ */ + +#define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ +/*! @{ */ + +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ +/*! @{ */ + +#define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0x80000000U) +#define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (31U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ +/*! @{ */ + +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ +/*! @{ */ + +#define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xF0000000U) +#define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (28U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ +/*! @{ */ + +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[4]; + __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ + __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ + uint8_t RESERVED_3[4]; + __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120 */ + __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124 */ + __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ + uint8_t RESERVED_4[4]; + __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130 */ + __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134 */ + __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ + uint8_t RESERVED_5[4]; + __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140 */ + __I uint32_t SYN4; /**< ERM Memory 4 Syndrome Register, offset: 0x144 */ + __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ + uint8_t RESERVED_9[8]; + __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184 */ + __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE7_MASK (0x4U) +#define ERM_CR0_ENCIE7_SHIFT (2U) +/*! ENCIE7 - ENCIE7 + * 0b0..Interrupt notification of Memory 7 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 7 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) + +#define ERM_CR0_ESCIE7_MASK (0x8U) +#define ERM_CR0_ESCIE7_SHIFT (3U) +/*! ESCIE7 - ESCIE7 + * 0b0..Interrupt notification of Memory 7 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 7 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) + +#define ERM_CR0_ENCIE6_MASK (0x40U) +#define ERM_CR0_ENCIE6_SHIFT (6U) +/*! ENCIE6 - ENCIE6 + * 0b0..Interrupt notification of Memory 6 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 6 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) + +#define ERM_CR0_ESCIE6_MASK (0x80U) +#define ERM_CR0_ESCIE6_SHIFT (7U) +/*! ESCIE6 - ESCIE6 + * 0b0..Interrupt notification of Memory 6 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 6 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) + +#define ERM_CR0_ENCIE5_MASK (0x400U) +#define ERM_CR0_ENCIE5_SHIFT (10U) +/*! ENCIE5 - ENCIE5 + * 0b0..Interrupt notification of Memory 5 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 5 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) + +#define ERM_CR0_ESCIE5_MASK (0x800U) +#define ERM_CR0_ESCIE5_SHIFT (11U) +/*! ESCIE5 - ESCIE5 + * 0b0..Interrupt notification of Memory 5 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 5 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) + +#define ERM_CR0_ENCIE4_MASK (0x4000U) +#define ERM_CR0_ENCIE4_SHIFT (14U) +/*! ENCIE4 - ENCIE4 + * 0b0..Interrupt notification of Memory 4 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 4 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) + +#define ERM_CR0_ESCIE4_MASK (0x8000U) +#define ERM_CR0_ESCIE4_SHIFT (15U) +/*! ESCIE4 - ESCIE4 + * 0b0..Interrupt notification of Memory 4 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 4 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) + +#define ERM_CR0_ENCIE3_MASK (0x40000U) +#define ERM_CR0_ENCIE3_SHIFT (18U) +/*! ENCIE3 - ENCIE3 + * 0b0..Interrupt notification of Memory 3 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 3 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) + +#define ERM_CR0_ESCIE3_MASK (0x80000U) +#define ERM_CR0_ESCIE3_SHIFT (19U) +/*! ESCIE3 - ESCIE3 + * 0b0..Interrupt notification of Memory 3 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 3 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) + +#define ERM_CR0_ENCIE2_MASK (0x400000U) +#define ERM_CR0_ENCIE2_SHIFT (22U) +/*! ENCIE2 - ENCIE2 + * 0b0..Interrupt notification of Memory 2 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 2 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) + +#define ERM_CR0_ESCIE2_MASK (0x800000U) +#define ERM_CR0_ESCIE2_SHIFT (23U) +/*! ESCIE2 - ESCIE2 + * 0b0..Interrupt notification of Memory 2 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 2 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name CR1 - ERM Configuration Register 1 */ +/*! @{ */ + +#define ERM_CR1_ENCIE9_MASK (0x4000000U) +#define ERM_CR1_ENCIE9_SHIFT (26U) +/*! ENCIE9 - ENCIE9 + * 0b0..Interrupt notification of Memory 9 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 9 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) + +#define ERM_CR1_ESCIE9_MASK (0x8000000U) +#define ERM_CR1_ESCIE9_SHIFT (27U) +/*! ESCIE9 - ESCIE9 + * 0b0..Interrupt notification of Memory 9 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 9 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) + +#define ERM_CR1_ENCIE8_MASK (0x40000000U) +#define ERM_CR1_ENCIE8_SHIFT (30U) +/*! ENCIE8 - ENCIE8 + * 0b0..Interrupt notification of Memory 8 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 8 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) + +#define ERM_CR1_ESCIE8_MASK (0x80000000U) +#define ERM_CR1_ESCIE8_SHIFT (31U) +/*! ESCIE8 - ESCIE8 + * 0b0..Interrupt notification of Memory 8 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 8 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE7_MASK (0x4U) +#define ERM_SR0_NCE7_SHIFT (2U) +/*! NCE7 - NCE7 + * 0b0..No non-correctable error event on Memory 7 detected. + * 0b1..Non-correctable error event on Memory 7 detected. + */ +#define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) + +#define ERM_SR0_SBC7_MASK (0x8U) +#define ERM_SR0_SBC7_SHIFT (3U) +/*! SBC7 - SBC7 + * 0b0..No single-bit correction event on Memory 7 detected. + * 0b1..Single-bit correction event on Memory 7 detected. + */ +#define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) + +#define ERM_SR0_NCE6_MASK (0x40U) +#define ERM_SR0_NCE6_SHIFT (6U) +/*! NCE6 - NCE6 + * 0b0..No non-correctable error event on Memory 6 detected. + * 0b1..Non-correctable error event on Memory 6 detected. + */ +#define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) + +#define ERM_SR0_SBC6_MASK (0x80U) +#define ERM_SR0_SBC6_SHIFT (7U) +/*! SBC6 - SBC6 + * 0b0..No single-bit correction event on Memory 6 detected. + * 0b1..Single-bit correction event on Memory 6 detected. + */ +#define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) + +#define ERM_SR0_NCE5_MASK (0x400U) +#define ERM_SR0_NCE5_SHIFT (10U) +/*! NCE5 - NCE5 + * 0b0..No non-correctable error event on Memory 5 detected. + * 0b1..Non-correctable error event on Memory 5 detected. + */ +#define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) + +#define ERM_SR0_SBC5_MASK (0x800U) +#define ERM_SR0_SBC5_SHIFT (11U) +/*! SBC5 - SBC5 + * 0b0..No single-bit correction event on Memory 5 detected. + * 0b1..Single-bit correction event on Memory 5 detected. + */ +#define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) + +#define ERM_SR0_NCE4_MASK (0x4000U) +#define ERM_SR0_NCE4_SHIFT (14U) +/*! NCE4 - NCE4 + * 0b0..No non-correctable error event on Memory 4 detected. + * 0b1..Non-correctable error event on Memory 4 detected. + */ +#define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) + +#define ERM_SR0_SBC4_MASK (0x8000U) +#define ERM_SR0_SBC4_SHIFT (15U) +/*! SBC4 - SBC4 + * 0b0..No single-bit correction event on Memory 4 detected. + * 0b1..Single-bit correction event on Memory 4 detected. + */ +#define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) + +#define ERM_SR0_NCE3_MASK (0x40000U) +#define ERM_SR0_NCE3_SHIFT (18U) +/*! NCE3 - NCE3 + * 0b0..No non-correctable error event on Memory 3 detected. + * 0b1..Non-correctable error event on Memory 3 detected. + */ +#define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) + +#define ERM_SR0_SBC3_MASK (0x80000U) +#define ERM_SR0_SBC3_SHIFT (19U) +/*! SBC3 - SBC3 + * 0b0..No single-bit correction event on Memory 3 detected. + * 0b1..Single-bit correction event on Memory 3 detected. + */ +#define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) + +#define ERM_SR0_NCE2_MASK (0x400000U) +#define ERM_SR0_NCE2_SHIFT (22U) +/*! NCE2 - NCE2 + * 0b0..No non-correctable error event on Memory 2 detected. + * 0b1..Non-correctable error event on Memory 2 detected. + */ +#define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) + +#define ERM_SR0_SBC2_MASK (0x800000U) +#define ERM_SR0_SBC2_SHIFT (23U) +/*! SBC2 - SBC2 + * 0b0..No single-bit correction event on Memory 2 detected. + * 0b1..Single-bit correction event on Memory 2 detected. + */ +#define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name SR1 - ERM Status Register 1 */ +/*! @{ */ + +#define ERM_SR1_NCE9_MASK (0x4000000U) +#define ERM_SR1_NCE9_SHIFT (26U) +/*! NCE9 - NCE9 + * 0b0..No non-correctable error event on Memory 9 detected. + * 0b1..Non-correctable error event on Memory 9 detected. + */ +#define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) + +#define ERM_SR1_SBC9_MASK (0x8000000U) +#define ERM_SR1_SBC9_SHIFT (27U) +/*! SBC9 - SBC9 + * 0b0..No single-bit correction event on Memory 9 detected. + * 0b1..Single-bit correction event on Memory 9 detected. + */ +#define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) + +#define ERM_SR1_NCE8_MASK (0x40000000U) +#define ERM_SR1_NCE8_SHIFT (30U) +/*! NCE8 - NCE8 + * 0b0..No non-correctable error event on Memory 8 detected. + * 0b1..Non-correctable error event on Memory 8 detected. + */ +#define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) + +#define ERM_SR1_SBC8_MASK (0x80000000U) +#define ERM_SR1_SBC8_SHIFT (31U) +/*! SBC8 - SBC8 + * 0b0..No single-bit correction event on Memory 8 detected. + * 0b1..Single-bit correction event on Memory 8 detected. + */ +#define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name EAR1 - ERM Memory 1 Error Address Register */ +/*! @{ */ + +#define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR1_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) +/*! @} */ + +/*! @name SYN1 - ERM Memory 1 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN1_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN1_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + +/*! @name EAR2 - ERM Memory 2 Error Address Register */ +/*! @{ */ + +#define ERM_EAR2_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR2_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK) +/*! @} */ + +/*! @name SYN2 - ERM Memory 2 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN2_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN2_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) +/*! @} */ + +/*! @name EAR3 - ERM Memory 3 Error Address Register */ +/*! @{ */ + +#define ERM_EAR3_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR3_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK) +/*! @} */ + +/*! @name SYN3 - ERM Memory 3 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN3_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN3_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) +/*! @} */ + +/*! @name EAR4 - ERM Memory 4 Error Address Register */ +/*! @{ */ + +#define ERM_EAR4_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR4_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK) +/*! @} */ + +/*! @name SYN4 - ERM Memory 4 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN4_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN4_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN4_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN4_SYNDROME_SHIFT)) & ERM_SYN4_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) +/*! @} */ + +/*! @name SYN8 - ERM Memory 8 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN8_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN8_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EVTG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Peripheral_Access_Layer EVTG Peripheral Access Layer + * @{ + */ + +/** EVTG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT01; /**< AOI0 Boolean Function Term 0 and 1 Configuration, array offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT23; /**< AOI0 Boolean Function Term 2 and 3 Configuration, array offset: 0x2, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT01; /**< AOI1 Boolean Function Term 0 and 1 Configuration, array offset: 0x4, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT23; /**< AOI1 Boolean Function Term 2 and 3 Configuration, array offset: 0x6, array step: 0x10 */ + uint8_t RESERVED_0[2]; + __IO uint16_t EVTG_CTRL; /**< Control and Status, array offset: 0xA, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_FILT; /**< AOI0 Output Filter, array offset: 0xC, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_FILT; /**< AOI1 Output Filter, array offset: 0xE, array step: 0x10 */ + } EVTG_INST[4]; +} EVTG_Type; + +/* ---------------------------------------------------------------------------- + -- EVTG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Register_Masks EVTG Register Masks + * @{ + */ + +/*! @name EVTG_INST_EVTG_AOI0_BFT01 - AOI0 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_BFT23 - AOI0 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT01 - AOI1 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT23 - AOI1 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_CTRL - Control and Status */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK (0x1U) +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT (0U) +/*! FF_INIT - Flip flop Initial Value Configuration + * 0b0..0 + * 0b1..1 + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK (0x2U) +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT (1U) +/*! INIT_EN - Flip-Flop Initial Output Enable Control + * 0b0..Write 0 does not generate enable pulse + * 0b1..Write 1 generates enable pulse + */ +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK (0x1CU) +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT (2U) +/*! MODE_SEL - Flip-Flop Mode Selection + * 0b000..Bypass mode + * 0b001..RS Trigger mode + * 0b010..T-FF mode + * 0b011..D-FF mode + * 0b100..JK-FF mode + * 0b101..Latch mode + * 0b110..Reserved + * 0b111..Reserved + */ +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT (6U) +/*! FB_OVRD - EVTG Output Feedback Override Control + * 0b00..Replace An + * 0b01..Replace Bn + * 0b10..Replace Cn + * 0b11..Replace Dn + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK (0xF00U) +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT (8U) +/*! SYNC_CTRL - Synchronize Control + * 0bxxx1..EVTG input "An" will be synced by two bus clk cycles + * 0bxxx0..EVTG input "An" will not be synced + * 0bxx1x..EVTG input "Bn" will be synced by two bus clk cycles + * 0bxx0x..EVTG input "Bn" will not be synced + * 0bx1xx..EVTG input "Cn" will be synced by two bus clk cycles + * 0bx0xx..EVTG input "Cn" will not be synced + * 0b1xxx..EVTG input "Dn" will be synced by two bus clk cycles + * 0b0xxx..EVTG input "Dn" will not be synced + */ +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT (12U) +/*! FORCE_BYPASS - Force Bypass Control + * 0bx1..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_0(Filter_0) value directly to EVTG_OUTA + * 0bx0..Will not force the bypass + * 0b1x..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_1(Filter_1) value directly to EVTG_OUTB + * 0b0x..Will not force the bypass + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_CTRL */ +#define EVTG_EVTG_INST_EVTG_CTRL_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_FILT - AOI0 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_FILT - AOI1 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_COUNT (4U) + + +/*! + * @} + */ /* end of group EVTG_Register_Masks */ + + +/* EVTG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/*! + * @} + */ /* end of group EVTG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control, offset: 0x0 */ + __O uint8_t SERV; /**< Service, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +/*! EWMEN - EWM Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) + +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +/*! ASSIN - Assertion State Select + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) + +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +/*! INEN - Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) + +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +/*! INTEN - Interrupt Enable + * 0b1..Generates interrupt requests + * 0b0..Deasserts interrupt requests + */ +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service */ +/*! @{ */ + +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +/*! SERVICE - Service */ +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low */ +/*! @{ */ + +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +/*! COMPAREL - Compare Low */ +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High */ +/*! @{ */ + +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +/*! COMPAREH - Compare High */ +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control */ +/*! @{ */ + +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +/*! CLKSEL - Clock Select */ +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler */ +/*! @{ */ + +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +/*! CLK_DIV - Clock Divider */ +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[96]; + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[96]; + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[96]; + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (8U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (8U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + +/* The count of FMU_FCCOB */ +#define FMU_FCCOB_COUNT (8U) + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMUTEST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer + * @{ + */ + +/** FMUTEST - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + __I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */ + __IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */ + __IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */ + __IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */ + __IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */ + __IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */ + __IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */ + __IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */ + __IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */ + uint8_t RESERVED_0[208]; + __IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */ + __IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */ + __I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */ + __IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */ + __I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */ + __IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */ + __IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */ + __IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */ + __IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */ + __IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */ + __IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */ + __IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */ + __IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */ + __IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */ + __IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */ + __IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */ + __IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */ + __IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */ + __IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */ + __IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */ + __IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */ + __IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */ + __IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */ + __I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */ + __IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */ + __IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */ + __IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */ + __IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */ + __IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */ + __IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */ + __IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */ + __IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */ + __IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */ + __IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */ + __IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */ + __IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */ + __IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */ + __IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */ + __IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */ + __IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */ + __IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */ + __IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */ + __IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */ + __IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */ + __IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */ + __IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */ + __IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */ + __IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */ + __IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */ + __IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */ + __IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */ + __IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */ + __IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */ + __IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */ + __IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */ + __IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */ + uint8_t RESERVED_4[4]; + __IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */ + __IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */ + __IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */ + __IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */ + __IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */ + __IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */ + __IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */ + __IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */ + __IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */ + __O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */ + __I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */ + __I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */ + uint8_t RESERVED_5[8]; + __I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */ + __IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */ + __IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */ + __IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */ + __IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */ + __IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */ + __IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */ + __IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */ + __I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */ + __I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */ + __I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */ + __IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */ + __IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */ + __IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */ + __IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */ + uint8_t RESERVED_6[8]; + __I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */ + __I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */ + __I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */ + __I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */ + uint8_t RESERVED_7[132]; + __IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */ + uint8_t RESERVED_8[8]; + __IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */ + uint8_t RESERVED_9[12]; + __I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */ + uint8_t RESERVED_10[40]; + __I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */ + __I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */ + __I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */ + uint8_t RESERVED_11[4]; + __IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */ + __IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */ + __IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */ + uint8_t RESERVED_12[136]; + __IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */ + __IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */ + __IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */ + __IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */ + __IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */ + __IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */ + __IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */ + __IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */ + __IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */ + uint8_t RESERVED_13[220]; + __IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */ + __IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */ + __IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */ + __IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */ + uint8_t RESERVED_14[240]; + __IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */ + __IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */ + uint8_t RESERVED_15[4]; + __IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */ + __IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */ + __IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */ + __IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */ + __IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */ + __IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */ + __IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */ +} FMUTEST_Type; + +/* ---------------------------------------------------------------------------- + -- FMUTEST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMUTEST_FSTAT_FAIL_MASK (0x1U) +#define FMUTEST_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK) + +#define FMUTEST_FSTAT_CMDABT_MASK (0x4U) +#define FMUTEST_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK) + +#define FMUTEST_FSTAT_PVIOL_MASK (0x10U) +#define FMUTEST_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK) + +#define FMUTEST_FSTAT_ACCERR_MASK (0x20U) +#define FMUTEST_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK) + +#define FMUTEST_FSTAT_CWSABT_MASK (0x40U) +#define FMUTEST_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK) + +#define FMUTEST_FSTAT_CCIF_MASK (0x80U) +#define FMUTEST_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command or initialization in progress + * 0b1..Flash command or initialization has completed + */ +#define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK) + +#define FMUTEST_FSTAT_CMDPRT_MASK (0x300U) +#define FMUTEST_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command Protection Level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK) + +#define FMUTEST_FSTAT_CMDP_MASK (0x800U) +#define FMUTEST_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command Protection Status Flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK) + +#define FMUTEST_FSTAT_CMDDID_MASK (0xF000U) +#define FMUTEST_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command Domain ID */ +#define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK) + +#define FMUTEST_FSTAT_DFDIF_MASK (0x10000U) +#define FMUTEST_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access from the FMC + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC + */ +#define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK) + +#define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U) +#define FMUTEST_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during the last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK) + +#define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U) +#define FMUTEST_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK) + +#define FMUTEST_FSTAT_PERDY_MASK (0x80000000U) +#define FMUTEST_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program/Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation is not stalled + * 0b1..Program or sector erase command operation is stalled + */ +#define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMUTEST_FCNFG_CCIE_MASK (0x80U) +#define FMUTEST_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + */ +#define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK) + +#define FMUTEST_FCNFG_ERSREQ_MASK (0x100U) +#define FMUTEST_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase (Erase All) Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK) + +#define FMUTEST_FCNFG_DFDIE_MASK (0x10000U) +#define FMUTEST_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set + */ +#define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK) + +#define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK) + +#define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMUTEST_FCTRL_RWSC_MASK (0xFU) +#define FMUTEST_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control + * 0b0000..no additional wait-states are added (single cycle access) + * 0b0001..1 additional wait-state is added + * 0b0010..2 additional wait-states are added + * 0b0011..3 additional wait-states are added + * 0b0100..4 additional wait-states are added + * 0b0101..5 additional wait-states are added + * 0b0110..6 additional wait-states are added + * 0b0111..7 additional wait-states are added + * 0b1000..8 additional wait-states are added + * 0b1001..9 additional wait-states are added + * 0b1010..10 additional wait-states are added + * 0b1011..11 additional wait-states are added + * 0b1100..12 additional wait-states are added + * 0b1101..13 additional wait-states are added + * 0b1110..14 additional wait-states are added + * 0b1111..15 additional wait-states are added + */ +#define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK) + +#define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U) +#define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low Speed Active Mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK) + +#define FMUTEST_FCTRL_FDFD_MASK (0x10000U) +#define FMUTEST_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set + */ +#define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK) + +#define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMUTEST_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FTEST - Flash Test Register */ +/*! @{ */ + +#define FMUTEST_FTEST_TMECTL_MASK (0x1U) +#define FMUTEST_FTEST_TMECTL_SHIFT (0U) +/*! TMECTL - Test Mode Entry Control + * 0b0..FTEST register always reads 0 and writes to FTEST are ignored + * 0b1..FTEST register is readable and can be written to enable writability of TME + */ +#define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK) + +#define FMUTEST_FTEST_TMEWR_MASK (0x2U) +#define FMUTEST_FTEST_TMEWR_SHIFT (1U) +/*! TMEWR - Test Mode Entry Writable + * 0b0..TME bit is not writable + * 0b1..TME bit is writable + */ +#define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK) + +#define FMUTEST_FTEST_TME_MASK (0x4U) +#define FMUTEST_FTEST_TME_SHIFT (2U) +/*! TME - Test Mode Entry + * 0b0..Test mode entry not requested + * 0b1..Test mode entry requested + */ +#define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK) + +#define FMUTEST_FTEST_TMODE_MASK (0x8U) +#define FMUTEST_FTEST_TMODE_SHIFT (3U) +/*! TMODE - Test Mode Status + * 0b0..Test mode not active + * 0b1..Test mode active + */ +#define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK) + +#define FMUTEST_FTEST_TMELOCK_MASK (0x10U) +#define FMUTEST_FTEST_TMELOCK_SHIFT (4U) +/*! TMELOCK - Test Mode Entry Lock + * 0b0..FTEST register not locked from accepting writes + * 0b1..FTEST register locked from accepting writes + */ +#define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK) +/*! @} */ + +/*! @name FCCOB0 - Flash Command Control 0 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU) +#define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U) +/*! CMDCODE - Command code */ +#define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK) +/*! @} */ + +/*! @name FCCOB1 - Flash Command Control 1 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU) +#define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U) +/*! CMDOPT - Command options */ +#define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK) +/*! @} */ + +/*! @name FCCOB2 - Flash Command Control 2 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U) +/*! CMDADDR - Command starting address */ +#define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK) +/*! @} */ + +/*! @name FCCOB3 - Flash Command Control 3 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U) +/*! CMDADDRE - Command ending address */ +#define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK) +/*! @} */ + +/*! @name FCCOB4 - Flash Command Control 4 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U) +/*! CMDDATA0 - Command data word 0 */ +#define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK) +/*! @} */ + +/*! @name FCCOB5 - Flash Command Control 5 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U) +/*! CMDDATA1 - Command data word 1 */ +#define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK) +/*! @} */ + +/*! @name FCCOB6 - Flash Command Control 6 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U) +/*! CMDDATA2 - Command data word 2 */ +#define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK) +/*! @} */ + +/*! @name FCCOB7 - Flash Command Control 7 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U) +/*! CMDDATA3 - Command data word 3 */ +#define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK) +/*! @} */ + +/*! @name RESET_STATUS - FMU Initialization Tracking Register */ +/*! @{ */ + +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U) +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U) +/*! ARY_TRIM_DONE - Array Trim Complete + * 0b0..Recall register load operation has not been completed + * 0b1..Recall register load operation has completed + */ +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U) +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U) +/*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U) +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U) +/*! FMU_PARM_DONE - FMU Register Load Complete + * 0b0..FMU registers have not been loaded + * 0b1..FMU registers have been loaded + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U) +/*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U) +/*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings + * 0b0..C0DE_C0DEh check failed + * 0b1..C0DE_C0DEh check passed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U) +/*! SOC_TRIM_DONE - SoC Trim Complete + * 0b0..SoC Trim registers have not been updated + * 0b1..All SoC Trim registers have been updated + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U) +#define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U) +/*! RPR_DONE - Array Repair Complete + * 0b0..Repair registers have not been loaded + * 0b1..Repair registers have been loaded + */ +#define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK) + +#define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U) +#define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U) +/*! INIT_DONE - Initialization Done + * 0b0..All initialization steps did not complete + * 0b1..All initialization steps completed + */ +#define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U) +#define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U) +/*! RST_SF_ERR - ECC Single Fault during Reset Recovery + * 0b0..No single-bit faults detected during initialization + * 0b1..At least one single ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U) +#define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U) +/*! RST_DF_ERR - ECC Double Fault during Reset Recovery + * 0b0..No double-bit faults detected during initialization + * 0b1..Double-bit ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U) +/*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U) +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U) +/*! RST_PATCH_LD - Reset Patch Required + * 0b0..No patch required to be loaded during reset + * 0b1..Patch loaded during reset + */ +#define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK) + +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U) +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U) +/*! RECALL_DATA_MISMATCH - Recall Data Mismatch + * 0b0..Data read towards end of reset matched data read for Recall + * 0b1..Data read towards end of reset did not match data read for recall + */ +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK) +/*! @} */ + +/*! @name MCTL - FMU Control Register */ +/*! @{ */ + +#define FMUTEST_MCTL_COREHLD_MASK (0x1U) +#define FMUTEST_MCTL_COREHLD_SHIFT (0U) +/*! COREHLD - Core Hold + * 0b0..CPU access is allowed + * 0b1..CPU access must be blocked + */ +#define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK) + +#define FMUTEST_MCTL_LSACT_EN_MASK (0x4U) +#define FMUTEST_MCTL_LSACT_EN_SHIFT (2U) +/*! LSACT_EN - LSACTIVE Feature Enable + * 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. + * 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. + */ +#define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK) + +#define FMUTEST_MCTL_LSACTWREN_MASK (0x8U) +#define FMUTEST_MCTL_LSACTWREN_SHIFT (3U) +/*! LSACTWREN - LSACTIVE Write Enable + * 0b0..Unrestricted write access allowed + * 0b1..Write access while CMP set must match CMDDID and CMDPRT + */ +#define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK) + +#define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U) +#define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U) +/*! MASTER_REPAIR_EN - Master Repair Enable + * 0b0..Repair disabled + * 0b1..Repair enable determined by bit 0 of each REPAIR register + */ +#define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK) + +#define FMUTEST_MCTL_RFCMDEN_MASK (0x20U) +#define FMUTEST_MCTL_RFCMDEN_SHIFT (5U) +/*! RFCMDEN - RF Active Command Enable Control + * 0b0..Flash commands blocked (CCIF not writable) + * 0b1..Flash commands allowed + */ +#define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK) + +#define FMUTEST_MCTL_CWSABTEN_MASK (0x40U) +#define FMUTEST_MCTL_CWSABTEN_SHIFT (6U) +/*! CWSABTEN - Command Write Sequence Abort Enable + * 0b0..CWS abort feature is disabled + * 0b1..CWS abort feature is enabled + */ +#define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK) + +#define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U) +#define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U) +/*! MRGRDDIS - Margin Read Disable + * 0b0..Margin Read Settings are enabled + * 0b1..Margin Read Settings are disabled + */ +#define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK) + +#define FMUTEST_MCTL_MRGRD0_MASK (0xF00U) +#define FMUTEST_MCTL_MRGRD0_SHIFT (8U) +/*! MRGRD0 - Margin Read Setting for Program */ +#define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK) + +#define FMUTEST_MCTL_MRGRD1_MASK (0xF000U) +#define FMUTEST_MCTL_MRGRD1_SHIFT (12U) +/*! MRGRD1 - Margin Read Setting for Erase */ +#define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK) + +#define FMUTEST_MCTL_ERSAACK_MASK (0x10000U) +#define FMUTEST_MCTL_ERSAACK_SHIFT (16U) +/*! ERSAACK - Mass Erase (Erase All) Acknowledge + * 0b0..Mass Erase operation is not active (operation has completed or has not started) + * 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) + */ +#define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK) + +#define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U) +#define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U) +/*! SCAN_OBS - Scan Observability Control + * 0b0..Normal functional behavior + * 0b1..Enables observation of signals that may otherwise be ATPG untestable + */ +#define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK) + +#define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U) +#define FMUTEST_MCTL_BIST_CTL_SHIFT (20U) +/*! BIST_CTL - BIST IP Control + * 0b0..BIST IP disabled + * 0b1..BIST IP enabled + */ +#define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK) + +#define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U) +#define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U) +/*! SMWR_CTL - SMWR IP Control + * 0b0..SMWR IP disabled + * 0b1..SMWR IP enabled + */ +#define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK) + +#define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U) +#define FMUTEST_MCTL_SALV_DIS_SHIFT (24U) +/*! SALV_DIS - Salvage Disable + * 0b0..Salvage enabled (ECC used during erase verify) + * 0b1..Salvage disabled (ECC not used during erase verify) + */ +#define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK) + +#define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U) +#define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U) +/*! SOC_ECC_CTL - SOC ECC Control + * 0b0..ECC is enabled for SOC read access + * 0b1..ECC is disabled for SOC read access + */ +#define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK) + +#define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U) +#define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U) +/*! FMU_ECC_CTL - FMU ECC Control + * 0b0..ECC is enabled for FMU program operations + * 0b1..ECC is disabled for FMU program operations + */ +#define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK) + +#define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U) +#define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U) +/*! BIST_PWR_DIS - BIST Power Mode Disable + * 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) + * 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values + */ +#define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK) + +#define FMUTEST_MCTL_OSC_H_MASK (0x80000000U) +#define FMUTEST_MCTL_OSC_H_SHIFT (31U) +/*! OSC_H - Oscillator control + * 0b0..Use APB clock + * 0b1..Use a known fixed-frequency clock, e.g. 12 MHz + */ +#define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK) +/*! @} */ + +/*! @name BSEL_GEN - FMU Block Select Generation Register */ +/*! @{ */ + +#define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U) +#define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U) +/*! SBSEL_GEN - Generated SBSEL */ +#define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK) + +#define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U) +#define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U) +/*! MBSEL_GEN - Generated MBSEL */ +#define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK) +/*! @} */ + +/*! @name PWR_OPT - Power Mode Options Register */ +/*! @{ */ + +#define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU) +#define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U) +/*! PD_CDIV - Power Down Clock Divider Setting */ +#define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK) + +#define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U) +#define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U) +/*! SLM_COUNT - Sleep Recovery Timer Count */ +#define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK) + +#define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U) +#define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U) +/*! PD_TIMER_EN - Power Down BIST Timer Enable + * 0b0..BIST timer is not triggered during Power Down recovery + * 0b1..BIST timer is triggered during Power Down recovery (default behavior) + */ +#define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK) +/*! @} */ + +/*! @name CMD_CHECK - FMU Command Check Register */ +/*! @{ */ + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U) +/*! ALIGNFAIL_PHR - Phrase Alignment Fail + * 0b0..The address is phrase-aligned + * 0b1..The address is not phrase-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U) +/*! ALIGNFAIL_PG - Page Alignment Fail + * 0b0..The address is page-aligned + * 0b1..The address is not page-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U) +/*! ALIGNFAIL_SCR - Sector Alignment Fail + * 0b0..The address is sector-aligned + * 0b1..The address is not sector-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U) +/*! ALIGNFAIL_BLK - Block Alignment Fail + * 0b0..The address is block-aligned + * 0b1..The address is not block-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK) + +#define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U) +#define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U) +/*! ADDR_FAIL - Address Fail + * 0b0..The address is within the flash or IFR address space + * 0b1..The address is outside the flash or IFR address space + */ +#define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U) +#define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U) +/*! IFR_CMD - IFR Command + * 0b0..The command operates on a main flash address + * 0b1..The command operates on an IFR address + */ +#define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK) + +#define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U) +#define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U) +/*! ALL_CMD - All Blocks Command + * 0b0..The command operates on a single flash block + * 0b1..The command operates on all flash blocks + */ +#define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK) + +#define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U) +#define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U) +/*! RANGE_FAIL - Address Range Fail + * 0b0..The address range is valid + * 0b1..The address range is invalid + */ +#define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U) +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U) +/*! SCR_ALIGN_CHK - Sector Alignment Check + * 0b0..No sector alignment check + * 0b1..Sector alignment check + */ +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK) + +#define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U) +#define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U) +/*! OPTION_FAIL - Option Check Fail + * 0b0..Option check passes for read command or command is not a read command + * 0b1..Option check fails for read command + */ +#define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U) +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U) +/*! ILLEGAL_CMD - Illegal Command + * 0b0..Command is legal + * 0b1..Command is illegal + */ +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK) +/*! @} */ + +/*! @name BSEL - FMU Block Select Register */ +/*! @{ */ + +#define FMUTEST_BSEL_SBSEL_MASK (0x3U) +#define FMUTEST_BSEL_SBSEL_SHIFT (0U) +/*! SBSEL - Slave Block Select */ +#define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK) + +#define FMUTEST_BSEL_MBSEL_MASK (0x300U) +#define FMUTEST_BSEL_MBSEL_SHIFT (8U) +/*! MBSEL - Master Block Select */ +#define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK) +/*! @} */ + +/*! @name MSIZE - FMU Memory Size Register */ +/*! @{ */ + +#define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU) +#define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U) +/*! MAXADDR0 - Size of Flash Block 0 */ +#define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK) + +#define FMUTEST_MSIZE_MAXADDR1_MASK (0xFF00U) +#define FMUTEST_MSIZE_MAXADDR1_SHIFT (8U) +/*! MAXADDR1 - Size of Flash Block 1 */ +#define FMUTEST_MSIZE_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR1_SHIFT)) & FMUTEST_MSIZE_MAXADDR1_MASK) +/*! @} */ + +/*! @name FLASH_RD_ADD - Flash Read Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U) +/*! FLASH_RD_ADD - Flash Read Address */ +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK) +/*! @} */ + +/*! @name FLASH_STOP_ADD - Flash Stop Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U) +/*! FLASH_STOP_ADD - Flash Stop Address */ +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK) +/*! @} */ + +/*! @name FLASH_RD_CTRL - Flash Read Control Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U) +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U) +/*! FLASH_RD - Flash Read Enable + * 0b0..Manual flash read not enabled.(default) + * 0b1..Manual flash read enabled + */ +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U) +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U) +/*! WIDE_LOAD - Wide Load Enable + * 0b0..Wide load mode disabled (default) + * 0b1..Wide load mode enabled + */ +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U) +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U) +/*! SINGLE_RD - Single Flash Read + * 0b0..Normal UINT operation + * 0b1..UINT configured for single cycle reads + */ +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK) +/*! @} */ + +/*! @name MM_ADDR - Memory Map Address Register */ +/*! @{ */ + +#define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U) +/*! MM_ADDR - Memory Map Address */ +#define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK) +/*! @} */ + +/*! @name MM_WDATA - Memory Map Write Data Register */ +/*! @{ */ + +#define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U) +/*! MM_WDATA - Memory Map Write Data */ +#define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK) +/*! @} */ + +/*! @name MM_CTL - Memory Map Control Register */ +/*! @{ */ + +#define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U) +#define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U) +/*! MM_SEL - Register Access Enable */ +#define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK) + +#define FMUTEST_MM_CTL_MM_RD_MASK (0x2U) +#define FMUTEST_MM_CTL_MM_RD_SHIFT (1U) +/*! MM_RD - Register R/W Control + * 0b0..Write to register + * 0b1..Read register + */ +#define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK) + +#define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U) +#define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U) +/*! BIST_ON - BIST on + * 0b0..BIST enable not forced by user interface + * 0b1..BIST enable control by user interface + */ +#define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK) + +#define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U) +#define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U) +/*! FORCE_SW_CLK - Force Switch Clock + * 0b0..Switch clock not forced on (gated normally) + * 0b1..Switch clock forced on + */ +#define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK) +/*! @} */ + +/*! @name UINT_CTL - User Interface Control Register */ +/*! @{ */ + +#define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U) +#define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U) +/*! SET_FAIL - Set Fail On Exit + * 0b0..FAIL flag should not be set on command exit (no failure detected) + * 0b1..FAIL flag should be set on command exit + */ +#define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK) + +#define FMUTEST_UINT_CTL_DBERR_MASK (0x2U) +#define FMUTEST_UINT_CTL_DBERR_SHIFT (1U) +/*! DBERR - Double-Bit ECC Fault Detect + * 0b0..No double-bit fault detected during UINT-driven read sequence + * 0b1..Double-bit fault detected during UINT-driven read sequence + */ +#define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK) +/*! @} */ + +/*! @name RD_DATA0 - Read Data 0 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U) +/*! RD_DATA0 - Read Data 0 */ +#define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK) +/*! @} */ + +/*! @name RD_DATA1 - Read Data 1 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U) +/*! RD_DATA1 - Read Data 1 */ +#define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK) +/*! @} */ + +/*! @name RD_DATA2 - Read Data 2 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U) +/*! RD_DATA2 - Read Data 2 */ +#define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK) +/*! @} */ + +/*! @name RD_DATA3 - Read Data 3 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U) +/*! RD_DATA3 - Read Data 3 */ +#define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK) +/*! @} */ + +/*! @name PARITY - Parity Register */ +/*! @{ */ + +#define FMUTEST_PARITY_PARITY_MASK (0x1FFU) +#define FMUTEST_PARITY_PARITY_SHIFT (0U) +/*! PARITY - Read data [136:128] */ +#define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK) +/*! @} */ + +/*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */ +/*! @{ */ + +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU) +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U) +/*! RD_CAPT - Read Capture Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U) +/*! SE_SIZE - SE Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U) +/*! ECC_ENABLEB - ECC Decoder Control + * 0b0..ECC decoder enabled (default) + * 0b1..ECC decoder disabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U) +/*! MISR_EN - MISR Enable + * 0b0..MISR option disabled (default) + * 0b1..MISR option enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U) +/*! CPY_PAR_EN - Copy Parity Enable + * 0b0..Copy parity disabled + * 0b1..Copy parity enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U) +/*! BIST_MUX_TO_SMW - BIST Mux to SMW + * 0b0..BIST drives fields + * 0b1..SMW registers drive fields + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U) +/*! AD_SET - Multi-Cycle Address Setup Time */ +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U) +/*! WR_PATH_EN - Write Path Enable + * 0b0..Writes to BIST setting registers driven by MM_WDATA + * 0b1..Writes to BIST setting registers driven by SMW_DIN + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U) +/*! WR_PATH_ECC_EN - Write Path ECC Enable + * 0b0..ECC encoding disabled + * 0b1..ECC encoding enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U) +/*! DBERR_REG - Double-Bit Error + * 0b0..Double-bit fault not detected + * 0b1..Double-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U) +/*! SBERR_REG - Single-Bit Error + * 0b0..Single-bit fault not detected + * 0b1..Single-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U) +/*! CPY_PHRASE_EN - Copy Phrase Enable + * 0b0..Copy Flash read data disabled + * 0b1..Copy Flash read data enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U) +/*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL + * 0b0..Select block 0 + * 0b1..Select block 1 + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U) +/*! BIST_ECC_EN - BIST ECC Enable + * 0b0..ECC correction disabled + * 0b1..ECC correction enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U) +/*! LAST_READ - Last Read + * 0b0..Latest read not last in multi-address operation + * 0b1..Latest read last in multi-address operation + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK) +/*! @} */ + +/*! @name SMW_DIN0 - SMW DIN 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U) +/*! SMW_DIN0 - SMW DIN 0 */ +#define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK) +/*! @} */ + +/*! @name SMW_DIN1 - SMW DIN 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U) +/*! SMW_DIN1 - SMW DIN 1 */ +#define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK) +/*! @} */ + +/*! @name SMW_DIN2 - SMW DIN 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U) +/*! SMW_DIN2 - SMW DIN 2 */ +#define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK) +/*! @} */ + +/*! @name SMW_DIN3 - SMW DIN 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U) +/*! SMW_DIN3 - SMW DIN 3 */ +#define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK) +/*! @} */ + +/*! @name SMW_ADDR - SMW Address Register */ +/*! @{ */ + +#define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U) +/*! SMW_ADDR - SMW Address */ +#define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK) +/*! @} */ + +/*! @name SMW_CMD_WAIT - SMW Command and Wait Register */ +/*! @{ */ + +#define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U) +#define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U) +/*! CMD - SMW Command + * 0b000..IDLE + * 0b001..ABORT + * 0b010..SME2 to one-shot mass erase + * 0b011..SME3 to sector erase on selected array + * 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit + * 0b101..Reserved for SME4 (multi-sector erase) + * 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss + * 0b111..Reserved + */ +#define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U) +/*! WAIT_EN - SMW Wait Enable + * 0b0..Wait feature disabled + * 0b1..Wait feature enabled + */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U) +/*! WAIT_AUTO_SET - SMW Wait Auto Set */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK) +/*! @} */ + +/*! @name SMW_STATUS - SMW Status Register */ +/*! @{ */ + +#define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U) +#define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U) +/*! SMW_ERR - SMW Error + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK) + +#define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U) +#define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U) +/*! SMW_BUSY - SMW Busy + * 0b0..SMW command not active + * 0b1..SMW command is active + */ +#define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK) + +#define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U) +#define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U) +/*! BIST_BUSY - BIST Busy + * 0b0..BIST Command not active + * 0b1..BIST Command is active + */ +#define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK) +/*! @} */ + +/*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U) +/*! TRIM0_0 - TRIM0_0 */ +#define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK) +/*! @} */ + +/*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U) +/*! TRIM0_1 - TRIM0_1 */ +#define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK) +/*! @} */ + +/*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U) +/*! TRIM0_2 - TRIM0_2 */ +#define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK) +/*! @} */ + +/*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U) +/*! TRIM0_3 - TRIM0_3 */ +#define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK) +/*! @} */ + +/*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U) +/*! TRIM1_0 - TRIM1_0 */ +#define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK) +/*! @} */ + +/*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U) +/*! TRIM1_1 - TRIM1_1 */ +#define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK) +/*! @} */ + +/*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U) +/*! TRIM1_2 - TRIM1_2 */ +#define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK) +/*! @} */ + +/*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U) +/*! TRIM1_3 - TRIM1_3 */ +#define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK) +/*! @} */ + +/*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U) +/*! TRIM2_0 - TRIM2_0 */ +#define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK) +/*! @} */ + +/*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U) +/*! TRIM2_1 - TRIM2_1 */ +#define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK) +/*! @} */ + +/*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U) +/*! TRIM2_2 - TRIM2_2 */ +#define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK) +/*! @} */ + +/*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U) +/*! TRIM2_3 - TRIM2_3 */ +#define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK) +/*! @} */ + +/*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U) +/*! TRIM3_0 - TRIM3_0 */ +#define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK) +/*! @} */ + +/*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U) +/*! TRIM3_1 - TRIM3_1 */ +#define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK) +/*! @} */ + +/*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U) +/*! TRIM3_2 - TRIM3_2 */ +#define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK) +/*! @} */ + +/*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U) +/*! TRIM3_3 - TRIM3_3 */ +#define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK) +/*! @} */ + +/*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U) +/*! TRIM4_0 - TRIM4_0 */ +#define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK) +/*! @} */ + +/*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U) +/*! TRIM4_1 - TRIM4_1 */ +#define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK) +/*! @} */ + +/*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U) +/*! TRIM4_2 - TRIM4_2 */ +#define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK) +/*! @} */ + +/*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U) +/*! TRIM4_3 - TRIM4_3 */ +#define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK) +/*! @} */ + +/*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U) +/*! TRIM5_0 - TRIM5_0 */ +#define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK) +/*! @} */ + +/*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U) +/*! TRIM5_1 - TRIM5_1 */ +#define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK) +/*! @} */ + +/*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U) +/*! TRIM5_2 - TRIM5_2 */ +#define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK) +/*! @} */ + +/*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U) +/*! TRIM5_3 - TRIM5_3 */ +#define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK) +/*! @} */ + +/*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U) +/*! TRIM6_0 - TRIM6_0 */ +#define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK) +/*! @} */ + +/*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U) +/*! TRIM6_1 - TRIM6_1 */ +#define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK) +/*! @} */ + +/*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U) +/*! TRIM6_2 - TRIM6_2 */ +#define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK) +/*! @} */ + +/*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U) +/*! TRIM6_3 - TRIM6_3 */ +#define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK) +/*! @} */ + +/*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U) +/*! TRIM7_0 - TRIM7_0 */ +#define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK) +/*! @} */ + +/*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U) +/*! TRIM7_1 - TRIM7_1 */ +#define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK) +/*! @} */ + +/*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U) +/*! TRIM7_2 - TRIM7_2 */ +#define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK) +/*! @} */ + +/*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U) +/*! TRIM7_3 - TRIM7_3 */ +#define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK) +/*! @} */ + +/*! @name R_IP_CONFIG - BIST Configuration Register */ +/*! @{ */ + +#define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U) +#define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U) +/*! IPSEL0 - Block 0 Select Control + * 0b00..Unselect block 0 + * 0b01..not used, reserved + * 0b10..Enable block 0 test, repair off (default) + * 0b11..Enable block 0 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK) + +#define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU) +#define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U) +/*! IPSEL1 - Block 1 Select Control + * 0b00..Unselect block 1 + * 0b01..not used, reserved + * 0b10..Enable block 1 test, repair off (default) + * 0b11..Enable block 1 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U) +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U) +/*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK) + +#define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U) +#define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U) +/*! CDIVS - Number of clock cycles to generate short pulse */ +#define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U) +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U) +/*! BIST_TVFY - Timer adjust for verify */ +#define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK) + +#define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U) +#define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U) +/*! TSTCTL - BIST self-test control + * 0b00..Default, disable both BIST self-test and MISR + * 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. + * 0b10..Enable MISR + * 0b11..Enable both BIST self-test mode and MISR + */ +#define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U) +#define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U) +/*! DBGCTL - Debug feature control + * 0b0..Default + * 0b1..Enable debug feature to collect failure address and data. + */ +#define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U) +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U) +/*! BIST_CLK_SEL - BIST Clock Select */ +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK) + +#define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U) +#define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U) +/*! SMWTST - SMWR DOUT Function Control + * 0b00..Default + * 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0 + * 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1 + * 0b11..Reserved (unused) + */ +#define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK) + +#define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U) +#define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U) +/*! ECCEN - BIST ECC Control + * 0b0..Default mode (no ECC encode or decode) + * 0b1..Enable ECC encode/decode + */ +#define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK) +/*! @} */ + +/*! @name R_TESTCODE - BIST Test Code Register */ +/*! @{ */ + +#define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU) +#define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U) +/*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */ +#define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK) +/*! @} */ + +/*! @name R_DFT_CTRL - BIST DFT Control Register */ +/*! @{ */ + +#define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU) +#define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U) +/*! DFT_XADR - DFT XADR Pattern + * 0b0000..XADR fixed, no change at all + * 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of + * row. For PROG operation, XADR increases by 1 after NVSTR falls. + * 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. + * 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. + * 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word + * of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. + * 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. + * 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. + * 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. + */ +#define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U) +#define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U) +/*! DFT_YADR - DFT YADR Pattern + * 0b0000..YADR fixed, no change at all + * 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. + * 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. + * 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG + * operations, YADR increased by 1 after YE falls. + * 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. + * 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. + * 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. + * 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. + * 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. + * 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. + */ +#define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U) +/*! DFT_DATA - DFT Data Pattern + * 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. + * 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. + * 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. + * 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to + * R_ADR_CTRL[GRPSEL] for modules with multiple groups. + * 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ + * operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected + * groups. + * 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If + * more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. + * 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA + * when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals + * R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. + * 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data + * pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. + * 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 + * and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared + * against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only + * one flash block can be selected. + * 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK) + +#define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U) +#define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U) +/*! CMP_MASK - Data Compare Mask + * 0b00..Expected data is compared to DOUT + * 0b01..Expected data (only 0s are considered) are compared to DOUT + * 0b10..Expected data (only 1s are considered) are compared to DOUT + */ +#define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U) +/*! DFT_DATA_SRC - DFT Data Source + * 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + * 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK) +/*! @} */ + +/*! @name R_ADR_CTRL - BIST Address Control Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU) +#define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U) +/*! GRPSEL - Data Group Select + * 0b0000..Select no data + * 0b0001..Select data slice [34:0] + * 0b0010..Select data slice [69:35] + * 0b0100..Select data slice [104:70] + * 0b1000..Select data slice [136:105] + * 0b1111..Select data [136:0] + */ +#define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK) + +#define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U) +#define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U) +/*! XADR - BIST XADR */ +#define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK) + +#define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U) +#define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U) +/*! YADR - BIST YADR */ +#define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK) + +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U) +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U) +/*! PROG_ATTR - Program Attribute + * 0b000..One YE pulse will program one data slice group + * 0b001..One YE pulse will program two data slice groups + * 0b010..One YE pulse will program three data slice groups (reserved) + * 0b011..One YE pulse will program four data slice groups + * 0b100..One YE pulse will program five data slice groups (reserved) + * 0b101..One YE pulse will program six data slice groups (reserved) + * 0b110..One YE pulse will program seven data slice groups (reserved) + * 0b111..One YE pulse will program eight data slice groups (reserved) + */ +#define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U) +/*! DATA0 - BIST Data 0 Low */ +#define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK) +/*! @} */ + +/*! @name R_PIN_CTRL - BIST Pin Control Register */ +/*! @{ */ + +#define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U) +#define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U) +/*! MAS1 - Mass Erase */ +#define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U) +#define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U) +/*! IFREN - IFR Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U) +#define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U) +/*! IFREN1 - IFR1 Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK) + +#define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U) +#define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U) +/*! REDEN - Redundancy Block Enable */ +#define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK) + +#define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U) +#define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U) +/*! LVE - Low Voltage Enable */ +#define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK) + +#define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U) +#define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U) +/*! PV - Program Verify Enable */ +#define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK) + +#define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U) +#define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U) +/*! EV - Erase Verify Enable */ +#define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK) + +#define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U) +#define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U) +/*! WIPGM - Program Current */ +#define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK) + +#define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U) +#define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U) +/*! WHV - High Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK) + +#define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U) +#define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U) +/*! WMV - Medium Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK) + +#define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U) +#define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U) +/*! XE - X Address Enable */ +#define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK) + +#define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U) +#define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U) +/*! YE - Y Address Enable */ +#define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK) + +#define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U) +#define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U) +/*! SE - Sense Amp Enable */ +#define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK) + +#define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U) +#define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U) +/*! ERASE - Erase Mode */ +#define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK) + +#define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U) +#define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U) +/*! PROG - Program Mode */ +#define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK) + +#define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U) +#define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U) +/*! NVSTR - NVM Store */ +#define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK) + +#define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U) +#define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U) +/*! SLM - Sleep Mode Enable */ +#define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK) + +#define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U) +#define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U) +/*! RECALL - Recall Trim Code */ +#define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK) + +#define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U) +#define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U) +/*! HEM - HEM Control */ +#define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK) +/*! @} */ + +/*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */ +/*! @{ */ + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U) +/*! LOOPCNT - Loop Count Control */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U) +/*! LOOPOPT - Loop Option + * 0b000..Loop is disabled; selected BIST operation is run once + * 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U) +/*! LOOPUNIT - Loop Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U) +/*! LOOPDLY - Loop Time Delay Scalar */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL - BIST Timer Control Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U) +/*! TNVSUNIT - Tnvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U) +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U) +/*! TNVSDLY - Tnvs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U) +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U) +/*! TNVHUNIT - Tnvh Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U) +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U) +/*! TNVHDLY - Tnvh Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U) +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U) +/*! TPGSUNIT - Tpgs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U) +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U) +/*! TPGSDLY - Tpgs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U) +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U) +/*! TRCVUNIT - Trcv Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U) +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U) +/*! TRCVDLY - Trcv Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U) +/*! TLVSUNIT - Tlvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U) +/*! TLVSDLY_L - Tlvs Time Delay Scalar Low */ +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK) +/*! @} */ + +/*! @name R_TEST_CTRL - BIST Test Control Register */ +/*! @{ */ + +#define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U) +#define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U) +/*! BUSY - BIST Busy Status + * 0b0..BIST is idle + * 0b1..BIST is busy + */ +#define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U) +#define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U) +/*! DEBUG - BIST Debug Status */ +#define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U) +#define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U) +/*! STATUS0 - BIST Status 0 + * 0b0..BIST test passed on flash block 0 + * 0b1..BIST test failed on flash block 0 + */ +#define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U) +#define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U) +/*! STATUS1 - BIST status 1 + * 0b0..BIST test passed on flash block 1 + * 0b1..BIST test failed on flash block 1 + */ +#define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U) +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U) +/*! DEBUGRUN - BIST Continue Debug Run */ +#define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U) +#define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U) +/*! STARTRUN - Run New BIST Operation */ +#define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U) +#define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U) +/*! CMDINDEX - BIST Command Index (code) */ +#define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK) + +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U) +/*! DISABLE_IP1 - BIST Disable IP1 */ +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK) +/*! @} */ + +/*! @name R_ABORT_LOOP - BIST Abort Loop Register */ +/*! @{ */ + +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U) +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U) +/*! ABORT_LOOP - Abort Loop + * 0b0..No effect + * 0b1..Abort BIST loop commands and force the loop counter to return to 0x0 + */ +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK) +/*! @} */ + +/*! @name R_ADR_QUERY - BIST Address Query Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU) +#define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U) +/*! YADRFAIL - Failing YADR */ +#define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK) + +#define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U) +#define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U) +/*! XADRFAIL - Failing XADR */ +#define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U) +/*! DOUTFAIL - Failing DOUT Low */ +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK) +/*! @} */ + +/*! @name R_SMW_QUERY - BIST SMW Query Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU) +#define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U) +/*! SMWLOOP - SMW Total Loop Count */ +#define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK) + +#define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U) +#define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U) +/*! SMWLAST - SMW Last Voltage Setting */ +#define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU) +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U) +/*! SMWPARM0 - SMW Parameter Set 0 */ +#define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U) +/*! SMWPARM1 - SMW Parameter Set 1 */ +#define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK) +/*! @} */ + +/*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U) +/*! SMPWHV0 - SMP WHV Parameter Set 0 */ +#define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK) +/*! @} */ + +/*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U) +/*! SMPWHV1 - SMP WHV Parameter Set 1 */ +#define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK) +/*! @} */ + +/*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U) +/*! SMEWHV0 - SME WHV Parameter Set 0 */ +#define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK) +/*! @} */ + +/*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U) +/*! SMEWHV1 - SME WHV Parameter Set 1 */ +#define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU) +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U) +/*! SMWPARM2 - SMW Parameter Set 2 */ +#define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK) +/*! @} */ + +/*! @name R_D_MISR0 - BIST DIN MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U) +/*! DATASIG0 - Data Signature */ +#define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK) +/*! @} */ + +/*! @name R_A_MISR0 - BIST Address MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U) +/*! ADRSIG0 - Address Signature */ +#define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK) +/*! @} */ + +/*! @name R_C_MISR0 - BIST Control MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U) +/*! CTRLSIG0 - Control Signature */ +#define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU) +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U) +/*! SMWPARM3 - SMW Parameter Set 3 */ +#define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U) +/*! DATA1 - BIST Data 1 Low */ +#define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U) +/*! DATA2 - BIST Data 2 Low */ +#define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U) +/*! DATA3 - BIST Data 3 Low */ +#define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK) +/*! @} */ + +/*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - Control Repair 0 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - XADR for Repair 0 in Block 0 */ +#define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - Control Repair 1 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - XADR for Repair 1 in Block 0. */ +#define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - Control Repair 0 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - XADR for Repair 0 in Block 1. */ +#define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - Control Repair 1 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - XADR for Repair 1 in Block 1. */ +#define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U) +/*! DATA0X - BIST Data 0 High */ +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U) +/*! TLVSDLY_H - Tlvs Time Delay Scalar High */ +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U) +#define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U) +/*! DOUT - Failing DOUT High */ +#define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK) +/*! @} */ + +/*! @name R_D_MISR1 - BIST DIN MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU) +#define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U) +/*! DATASIG1 - MISR Data Signature High */ +#define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK) +/*! @} */ + +/*! @name R_A_MISR1 - BIST Address MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU) +#define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U) +/*! ADRSIG1 - MISR Address Signature High */ +#define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK) +/*! @} */ + +/*! @name R_C_MISR1 - BIST Control MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU) +#define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U) +/*! CTRLSIG1 - MISR Control Signature High */ +#define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U) +/*! DATA1X - BIST Data 1 High */ +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U) +/*! DATA2X - BIST Data 2 High */ +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U) +/*! DATA3X - BIST Data 3 High */ +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK) +/*! @} */ + +/*! @name SMW_TIMER_OPTION - SMW Timer Option Register */ +/*! @{ */ + +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU) +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U) +/*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK) + +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U) +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U) +/*! SMW_TVFY - Timer Adjust for Verify */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U) +/*! MV_INIT - Medium Voltage Level Select Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U) +/*! MV_END - Medium Voltage Level Select Final */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U) +/*! MV_MISC - Medium Voltage Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U) +/*! IPGM_INIT - Program Current Control Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U) +/*! IPGM_END - Program Current Control Final */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U) +/*! IPGM_MISC - Program Current Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U) +/*! THVS_CTRL - Thvs control */ +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U) +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U) +/*! TRCV_CTRL - Trcv Control */ +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U) +/*! XTRA_ERS - Number of Post Shots for SME */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U) +/*! XTRA_PGM - Number of Post Shots for SMP */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U) +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U) +/*! WHV_CNTR - WHV Counter */ +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U) +/*! POST_TERS - Post Ters Time + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U) +/*! POST_TPGM - Post Tpgm Time + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U) +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U) +/*! VFY_OPT - Verify Option + * 0b00..Skip verify for post shot only, verify for all other shots + * 0b01..Skip verify for the 1st and post shots + * 0b10..Skip the 1st, 2nd, and post shots + * 0b11..Skip verify for all shots + */ +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U) +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U) +/*! TPGM_OPT - Tpgm Option + * 0b00..Fixed Tpgm for all shots, except post shot + * 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec + * 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec + * 0b11..Unused + */ +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U) +/*! MASK0_OPT - MASK0_OPT + * 0b0..Mask programmed bits passing PV until extra shot + * 0b1..Always program bits even if they pass PV + */ +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U) +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U) +/*! DIS_PRER - Disable pre-PV Read before First Program Shot + * 0b0..Enable pre-PV read before first program shot + * 0b1..Disable pre-PV read before first program shot + */ +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U) +/*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U) +/*! HEM_MAX_ERS - HEM Max Erase Shot Count */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U) +/*! SMP_WHV_OPT0 - Smart Program WHV Option Low */ +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U) +/*! SME_WHV_OPT0 - Smart Erase WHV Option Low */ +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U) +/*! TERS_CTRL0 - Ters Control + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U) +/*! TPGM_CTRL - Tpgm Control + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U) +/*! TNVS_CTRL - Tnvs Control + * 0b000..5 usec + * 0b001..8 usec + * 0b010..11 usec + * 0b011..14 usec + * 0b100..17 usec + * 0b101..20 usec + * 0b110..23 usec + * 0b111..26 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U) +/*! TNVH_CTRL - Tnvh Control + * 0b000..2 usec + * 0b001..2.5 usec + * 0b010..3 usec + * 0b011..3.5 usec + * 0b100..4 usec + * 0b101..4.5 usec + * 0b110..5 usec + * 0b111..5.5 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U) +/*! TPGS_CTRL - Tpgs Control + * 0b000..1 usec + * 0b001..2 usec + * 0b010..3 usec + * 0b011..4 usec + * 0b100..5 usec + * 0b101..6 usec + * 0b110..7 usec + * 0b111..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U) +/*! MAX_ERASE - Number of Erase Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U) +/*! MAX_PROG - Number of Program Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U) +/*! SMP_WHV_OPT1 - Smart Program WHV Option High */ +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U) +/*! SME_WHV_OPT1 - Smart Erase WHV Option High */ +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK) +/*! @} */ + +/*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - RDIS0_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - RADR0_0 */ +#define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - RDIS0_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - RADR0_1 */ +#define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - RDIS1_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - RADR1_0 */ +#define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - RDIS1_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - RADR1_1 */ +#define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name SMW_HB_SIGNALS - SMW HB Signals Register */ +/*! @{ */ + +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U) +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U) +/*! SMW_ARRAY - SMW Region Select + * 0b000..Main array + * 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase + * 0b010..IFR1 space + * 0b100..REDEN space + */ +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U) +/*! USER_IFREN1 - IFR1 Enable + * 0b0..IFREN1 input to the flash array is driven LOW + * 0b1..IFREN1 input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U) +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U) +/*! USER_PV - Program Verify + * 0b0..PV input to the flash array is driven LOW + * 0b1..PV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U) +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U) +/*! USER_EV - Erase Verify + * 0b0..EV input to the flash array is driven LOW + * 0b1..EV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U) +/*! USER_IFREN - IFR Enable + * 0b0..IFREN input to the flash array is driven LOW + * 0b1..IFREN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U) +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U) +/*! USER_REDEN - Repair Read Enable + * 0b0..REDEN input to the flash array is driven LOW + * 0b1..REDEN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U) +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U) +/*! USER_HEM - High Endurance Enable + * 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW + * 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK) +/*! @} */ + +/*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */ +/*! @{ */ + +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U) +/*! BIST_DONE - BIST Done + * 0b0..The BIST (or data dump) is running + * 0b1..The BIST (or data dump) has completed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U) +/*! BIST_FAIL - BIST Fail + * 0b0..The last BIST operation completed successfully (or could not fail) + * 0b1..The last BIST operation failed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U) +/*! DATADUMP - Data Dump Enable */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U) +/*! DATADUMP_TRIG - Data Dump Trigger */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U) +/*! DATADUMP_PATT - Data Dump Pattern Select + * 0b00..All ones + * 0b01..All zeroes + * 0b10..Checkerboard + * 0b11..Inverse checkerboard + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U) +/*! DATADUMP_MRGEN - Data Dump Margin Enable + * 0b0..Normal read pulse shape + * 0b1..Margin read pulse shape + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U) +/*! DATADUMP_MRGTYPE - Data Dump Margin Type + * 0b0..DIN method used + * 0b1..TM method used + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK) +/*! @} */ + +/*! @name ATX_PIN_CTRL - ATX Pin Control Register */ +/*! @{ */ + +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU) +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U) +/*! TM_TO_ATX - TM to ATX + * 0b00000001..TM[0] to ATX0 + * 0b00000010..TM[1] to ATX0 + * 0b00000100..TM[2] to ATX0 + * 0b00001000..TM[3] to ATX0 + * 0b00010000..TM[0] to ATX1 + * 0b00100000..TM[1] to ATX1 + * 0b01000000..TM[2] to ATX1 + * 0b10000000..TM[3] to ATX1 + */ +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK) +/*! @} */ + +/*! @name FAILCNT - Fail Count Register */ +/*! @{ */ + +#define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU) +#define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U) +/*! FAILCNT - Fail Count */ +#define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U) +/*! PGM_CNT0 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U) +/*! PGM_CNT1 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK) +/*! @} */ + +/*! @name ERS_PULSE_CNT - Erase Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U) +/*! ERS_CNT0 - Block 0 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK) + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U) +/*! ERS_CNT1 - Block 1 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK) +/*! @} */ + +/*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU) +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U) +/*! LAST_PCNT - Last SMW Operation's Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U) +/*! MAX_ERS_CNT - Maximum Erase Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U) +/*! MAX_PGM_CNT - Maximum Program Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK) +/*! @} */ + +/*! @name PORT_CTRL - Port Control Register */ +/*! @{ */ + +#define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U) +#define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U) +/*! BDONE_SEL - BIST Done Select + * 0b00..Select internal bist_done signal from current module instantiation + * 0b01..Select ipt_bist_fail signal from current module instantiation + * 0b10..Select ipt_bist_done signal from other module instantiation + * 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK) + +#define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU) +#define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U) +/*! BSDO_SEL - BIST Serial Data Output Select + * 0b00..Select internal bist_sdo signal from current module instantiation + * 0b01..Select ipt_bist_done signal from current module instantiation + * 0b10..Select ipt_bist_sdo signal from other module instantiation + * 0b11..Select ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMUTEST_Register_Masks */ + + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/*! + * @} + */ /* end of group FMUTEST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GDET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer + * @{ + */ + +/** GDET - Register Layout Typedef */ +typedef struct { + __IO uint32_t GDET_CONF_0; /**< GDET Configuration 0 Register, offset: 0x0 */ + __IO uint32_t GDET_CONF_1; /**< GDET Configuration 1 Register, offset: 0x4 */ + __IO uint32_t GDET_ENABLE1; /**< GDET Enable Register, offset: 0x8 */ + __IO uint32_t GDET_CONF_2; /**< GDET Configuration 2 Register, offset: 0xC */ + __IO uint32_t GDET_CONF_3; /**< GDET Configuration 3 Register, offset: 0x10 */ + __IO uint32_t GDET_CONF_4; /**< GDET Configuration 4 Register, offset: 0x14 */ + __IO uint32_t GDET_CONF_5; /**< GDET Configuration 5 Register, offset: 0x18 */ + uint8_t RESERVED_0[4004]; + __IO uint32_t GDET_RESET; /**< GDET Reset Register, offset: 0xFC0 */ + __IO uint32_t GDET_TEST; /**< GDET Test Register, offset: 0xFC4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t GDET_DLY_CTRL; /**< GDET Delay Control Register, offset: 0xFCC */ +} GDET_Type; + +/* ---------------------------------------------------------------------------- + -- GDET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Register_Masks GDET Register Masks + * @{ + */ + +/*! @name GDET_CONF_0 - GDET Configuration 0 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) +#define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) +/*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ +#define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) + +#define GDET_GDET_CONF_0_SBZ_MASK (0x10U) +#define GDET_GDET_CONF_0_SBZ_SHIFT (4U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) + +#define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) +#define GDET_GDET_CONF_0_RFU_SHIFT (5U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_1 - GDET Configuration 1 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) +#define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) +/*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ +#define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) + +#define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) +#define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) +/*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ +#define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) + +#define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) +#define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) +/*! SBZ1 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) + +#define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) +#define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) +/*! SBZ2 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) + +#define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) +#define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) +/*! SBZ3 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) + +#define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) +#define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) +/*! FIELD_7 - GDET Configuration 1 Field 7 */ +#define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) + +#define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) +#define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) +/*! FIELD_8 - GDET Configuration 1 Field 8 */ +#define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) + +#define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) +#define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) +/*! SBZ4 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) + +#define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) +#define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) +/*! SBZ5 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) + +#define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) +#define GDET_GDET_CONF_1_RFU_SHIFT (11U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) +/*! @} */ + +/*! @name GDET_ENABLE1 - GDET Enable Register */ +/*! @{ */ + +#define GDET_GDET_ENABLE1_EN1_MASK (0x1U) +#define GDET_GDET_ENABLE1_EN1_SHIFT (0U) +/*! EN1 - If set, the detector will be clock gated */ +#define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) + +#define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_ENABLE1_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_2 - GDET Configuration 2 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ +#define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) +#define GDET_GDET_CONF_2_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) + +#define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) +#define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) +/*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ +#define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) + +#define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) +#define GDET_GDET_CONF_2_RFU2_SHIFT (22U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) + +#define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) +#define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) +/*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ +#define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) + +#define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) +#define GDET_GDET_CONF_2_RFU3_SHIFT (30U) +/*! RFU3 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) +/*! @} */ + +/*! @name GDET_CONF_3 - GDET Configuration 3 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ +#define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_3_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_4 - GDET Configuration 4 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ +#define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_4_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_5 - GDET Configuration 5 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) +#define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) +/*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ +#define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) + +#define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) +#define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) +/*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ +#define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) + +#define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) +#define GDET_GDET_CONF_5_RFU1_SHIFT (12U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) +/*! @} */ + +/*! @name GDET_RESET - GDET Reset Register */ +/*! @{ */ + +#define GDET_GDET_RESET_RFU1_MASK (0x7U) +#define GDET_GDET_RESET_RFU1_SHIFT (0U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) + +#define GDET_GDET_RESET_SFT_RST_MASK (0x8U) +#define GDET_GDET_RESET_SFT_RST_SHIFT (3U) +/*! SFT_RST - Soft Reset for the Core Reset */ +#define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) + +#define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) +#define GDET_GDET_RESET_RFU2_SHIFT (4U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) +/*! @} */ + +/*! @name GDET_TEST - GDET Test Register */ +/*! @{ */ + +#define GDET_GDET_TEST_SBZ_MASK (0x1U) +#define GDET_GDET_TEST_SBZ_SHIFT (0U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) + +#define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_TEST_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) +/*! @} */ + +/*! @name GDET_DLY_CTRL - GDET Delay Control Register */ +/*! @{ */ + +#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) +#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) +/*! VOL_SEL - GDET Delay Control of the Voltage Mode */ +#define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) + +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) +/*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) + +#define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) +#define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GDET_Register_Masks */ + + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif + +/*! + * @} + */ /* end of group GDET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LOCK; /**< Lock, offset: 0xC */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ + uint8_t RESERVED_1[32]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_2[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_3[24]; + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define GPIO_LOCK_PCNS_MASK (0x1U) +#define GPIO_LOCK_PCNS_SHIFT (0U) +/*! PCNS - Lock PCNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) + +#define GPIO_LOCK_ICNS_MASK (0x2U) +#define GPIO_LOCK_ICNS_SHIFT (1U) +/*! ICNS - Lock ICNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) + +#define GPIO_LOCK_PCNP_MASK (0x4U) +#define GPIO_LOCK_PCNP_SHIFT (2U) +/*! PCNP - Lock PCNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) + +#define GPIO_LOCK_ICNP_MASK (0x8U) +#define GPIO_LOCK_ICNP_SHIFT (3U) +/*! ICNP - Lock ICNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) +/*! @} */ + +/*! @name PCNS - Pin Control Nonsecure */ +/*! @{ */ + +#define GPIO_PCNS_NSE0_MASK (0x1U) +#define GPIO_PCNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) + +#define GPIO_PCNS_NSE1_MASK (0x2U) +#define GPIO_PCNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) + +#define GPIO_PCNS_NSE2_MASK (0x4U) +#define GPIO_PCNS_NSE2_SHIFT (2U) +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) + +#define GPIO_PCNS_NSE3_MASK (0x8U) +#define GPIO_PCNS_NSE3_SHIFT (3U) +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) + +#define GPIO_PCNS_NSE4_MASK (0x10U) +#define GPIO_PCNS_NSE4_SHIFT (4U) +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) + +#define GPIO_PCNS_NSE5_MASK (0x20U) +#define GPIO_PCNS_NSE5_SHIFT (5U) +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) + +#define GPIO_PCNS_NSE6_MASK (0x40U) +#define GPIO_PCNS_NSE6_SHIFT (6U) +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) + +#define GPIO_PCNS_NSE7_MASK (0x80U) +#define GPIO_PCNS_NSE7_SHIFT (7U) +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) + +#define GPIO_PCNS_NSE8_MASK (0x100U) +#define GPIO_PCNS_NSE8_SHIFT (8U) +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) + +#define GPIO_PCNS_NSE9_MASK (0x200U) +#define GPIO_PCNS_NSE9_SHIFT (9U) +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) + +#define GPIO_PCNS_NSE10_MASK (0x400U) +#define GPIO_PCNS_NSE10_SHIFT (10U) +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) + +#define GPIO_PCNS_NSE11_MASK (0x800U) +#define GPIO_PCNS_NSE11_SHIFT (11U) +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) + +#define GPIO_PCNS_NSE12_MASK (0x1000U) +#define GPIO_PCNS_NSE12_SHIFT (12U) +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) + +#define GPIO_PCNS_NSE13_MASK (0x2000U) +#define GPIO_PCNS_NSE13_SHIFT (13U) +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) + +#define GPIO_PCNS_NSE14_MASK (0x4000U) +#define GPIO_PCNS_NSE14_SHIFT (14U) +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) + +#define GPIO_PCNS_NSE15_MASK (0x8000U) +#define GPIO_PCNS_NSE15_SHIFT (15U) +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) + +#define GPIO_PCNS_NSE16_MASK (0x10000U) +#define GPIO_PCNS_NSE16_SHIFT (16U) +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) + +#define GPIO_PCNS_NSE17_MASK (0x20000U) +#define GPIO_PCNS_NSE17_SHIFT (17U) +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) + +#define GPIO_PCNS_NSE18_MASK (0x40000U) +#define GPIO_PCNS_NSE18_SHIFT (18U) +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) + +#define GPIO_PCNS_NSE19_MASK (0x80000U) +#define GPIO_PCNS_NSE19_SHIFT (19U) +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) + +#define GPIO_PCNS_NSE20_MASK (0x100000U) +#define GPIO_PCNS_NSE20_SHIFT (20U) +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) + +#define GPIO_PCNS_NSE21_MASK (0x200000U) +#define GPIO_PCNS_NSE21_SHIFT (21U) +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) + +#define GPIO_PCNS_NSE22_MASK (0x400000U) +#define GPIO_PCNS_NSE22_SHIFT (22U) +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) + +#define GPIO_PCNS_NSE23_MASK (0x800000U) +#define GPIO_PCNS_NSE23_SHIFT (23U) +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) + +#define GPIO_PCNS_NSE24_MASK (0x1000000U) +#define GPIO_PCNS_NSE24_SHIFT (24U) +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) + +#define GPIO_PCNS_NSE25_MASK (0x2000000U) +#define GPIO_PCNS_NSE25_SHIFT (25U) +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) + +#define GPIO_PCNS_NSE26_MASK (0x4000000U) +#define GPIO_PCNS_NSE26_SHIFT (26U) +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) + +#define GPIO_PCNS_NSE27_MASK (0x8000000U) +#define GPIO_PCNS_NSE27_SHIFT (27U) +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) + +#define GPIO_PCNS_NSE28_MASK (0x10000000U) +#define GPIO_PCNS_NSE28_SHIFT (28U) +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) + +#define GPIO_PCNS_NSE29_MASK (0x20000000U) +#define GPIO_PCNS_NSE29_SHIFT (29U) +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) + +#define GPIO_PCNS_NSE30_MASK (0x40000000U) +#define GPIO_PCNS_NSE30_SHIFT (30U) +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) + +#define GPIO_PCNS_NSE31_MASK (0x80000000U) +#define GPIO_PCNS_NSE31_SHIFT (31U) +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) +/*! @} */ + +/*! @name ICNS - Interrupt Control Nonsecure */ +/*! @{ */ + +#define GPIO_ICNS_NSE0_MASK (0x1U) +#define GPIO_ICNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) + +#define GPIO_ICNS_NSE1_MASK (0x2U) +#define GPIO_ICNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) +/*! @} */ + +/*! @name PCNP - Pin Control Nonprivilege */ +/*! @{ */ + +#define GPIO_PCNP_NPE0_MASK (0x1U) +#define GPIO_PCNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) + +#define GPIO_PCNP_NPE1_MASK (0x2U) +#define GPIO_PCNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) + +#define GPIO_PCNP_NPE2_MASK (0x4U) +#define GPIO_PCNP_NPE2_SHIFT (2U) +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) + +#define GPIO_PCNP_NPE3_MASK (0x8U) +#define GPIO_PCNP_NPE3_SHIFT (3U) +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) + +#define GPIO_PCNP_NPE4_MASK (0x10U) +#define GPIO_PCNP_NPE4_SHIFT (4U) +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) + +#define GPIO_PCNP_NPE5_MASK (0x20U) +#define GPIO_PCNP_NPE5_SHIFT (5U) +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) + +#define GPIO_PCNP_NPE6_MASK (0x40U) +#define GPIO_PCNP_NPE6_SHIFT (6U) +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) + +#define GPIO_PCNP_NPE7_MASK (0x80U) +#define GPIO_PCNP_NPE7_SHIFT (7U) +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) + +#define GPIO_PCNP_NPE8_MASK (0x100U) +#define GPIO_PCNP_NPE8_SHIFT (8U) +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) + +#define GPIO_PCNP_NPE9_MASK (0x200U) +#define GPIO_PCNP_NPE9_SHIFT (9U) +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) + +#define GPIO_PCNP_NPE10_MASK (0x400U) +#define GPIO_PCNP_NPE10_SHIFT (10U) +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) + +#define GPIO_PCNP_NPE11_MASK (0x800U) +#define GPIO_PCNP_NPE11_SHIFT (11U) +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) + +#define GPIO_PCNP_NPE12_MASK (0x1000U) +#define GPIO_PCNP_NPE12_SHIFT (12U) +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) + +#define GPIO_PCNP_NPE13_MASK (0x2000U) +#define GPIO_PCNP_NPE13_SHIFT (13U) +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) + +#define GPIO_PCNP_NPE14_MASK (0x4000U) +#define GPIO_PCNP_NPE14_SHIFT (14U) +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) + +#define GPIO_PCNP_NPE15_MASK (0x8000U) +#define GPIO_PCNP_NPE15_SHIFT (15U) +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) + +#define GPIO_PCNP_NPE16_MASK (0x10000U) +#define GPIO_PCNP_NPE16_SHIFT (16U) +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) + +#define GPIO_PCNP_NPE17_MASK (0x20000U) +#define GPIO_PCNP_NPE17_SHIFT (17U) +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) + +#define GPIO_PCNP_NPE18_MASK (0x40000U) +#define GPIO_PCNP_NPE18_SHIFT (18U) +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) + +#define GPIO_PCNP_NPE19_MASK (0x80000U) +#define GPIO_PCNP_NPE19_SHIFT (19U) +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) + +#define GPIO_PCNP_NPE20_MASK (0x100000U) +#define GPIO_PCNP_NPE20_SHIFT (20U) +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) + +#define GPIO_PCNP_NPE21_MASK (0x200000U) +#define GPIO_PCNP_NPE21_SHIFT (21U) +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) + +#define GPIO_PCNP_NPE22_MASK (0x400000U) +#define GPIO_PCNP_NPE22_SHIFT (22U) +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) + +#define GPIO_PCNP_NPE23_MASK (0x800000U) +#define GPIO_PCNP_NPE23_SHIFT (23U) +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) + +#define GPIO_PCNP_NPE24_MASK (0x1000000U) +#define GPIO_PCNP_NPE24_SHIFT (24U) +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) + +#define GPIO_PCNP_NPE25_MASK (0x2000000U) +#define GPIO_PCNP_NPE25_SHIFT (25U) +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) + +#define GPIO_PCNP_NPE26_MASK (0x4000000U) +#define GPIO_PCNP_NPE26_SHIFT (26U) +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) + +#define GPIO_PCNP_NPE27_MASK (0x8000000U) +#define GPIO_PCNP_NPE27_SHIFT (27U) +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) + +#define GPIO_PCNP_NPE28_MASK (0x10000000U) +#define GPIO_PCNP_NPE28_SHIFT (28U) +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) + +#define GPIO_PCNP_NPE29_MASK (0x20000000U) +#define GPIO_PCNP_NPE29_SHIFT (29U) +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) + +#define GPIO_PCNP_NPE30_MASK (0x40000000U) +#define GPIO_PCNP_NPE30_SHIFT (30U) +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) + +#define GPIO_PCNP_NPE31_MASK (0x80000000U) +#define GPIO_PCNP_NPE31_SHIFT (31U) +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) +/*! @} */ + +/*! @name ICNP - Interrupt Control Nonprivilege */ +/*! @{ */ + +#define GPIO_ICNP_NPE0_MASK (0x1U) +#define GPIO_ICNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) + +#define GPIO_ICNP_NPE1_MASK (0x2U) +#define GPIO_ICNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of GPIO_PDR */ +#define GPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_IRQS_MASK (0x100000U) +#define GPIO_ICR_IRQS_SHIFT (20U) +/*! IRQS - Interrupt Select + * 0b0..Interrupt, trigger output, or DMA request 0 + * 0b1..Interrupt, trigger output, or DMA request 1 + */ +#define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) + +#define GPIO_ICR_LK_MASK (0x800000U) +#define GPIO_ICR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Lock + * 0b1..Do not lock + */ +#define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of GPIO_ICR */ +#define GPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of GPIO_ISFR */ +#define GPIO_ISFR_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } + #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } + #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif +/* Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} +#define GPIO_IRQS_1 {GPIO01_IRQn, GPIO11_IRQn, GPIO21_IRQn, GPIO31_IRQn,GPIO41_IRQn,GPIO51_IRQn} + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __O uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[24]; + __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[24]; + __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[24]; + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ + uint8_t RESERVED_5[28]; + __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Data Lines */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - Transmit Control */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - Transmit Configuration 1 */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(TFW +1) + * 0b111..8 + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - Transmit Configuration 2 */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with receiver + * 0b10..Synchronous with another SAI transmitter + * 0b11..Synchronous with another SAI receiver + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - Transmit Configuration 3 */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0x30000U) +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +#define I2S_TCR3_CFR_MASK (0x3000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - Transmit Configuration 4 */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode + * 0b1..Output mode + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable FIFO packing + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - Transmit Configuration 5 */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - Transmit FIFO */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) + +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be written + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - Transmit Mask */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - Receive Control */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not full + * 0b1..Full + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Receive overflow detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable after completing the current frame + * 0b1..Enable + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - Receive Configuration 1 */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(RFW value + 1) + * 0b111..8 + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - Receive Configuration 2 */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with transmitter + * 0b10..Synchronous with another SAI receiver + * 0b11..Synchronous with another SAI transmitter + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - Receive Configuration 3 */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + * 0b00000..Word 1 + * 0b00001..Word 2 + * 0b00010-0b11110..Word (WDFL value + 1) + * 0b11111..Word 32 + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0x30000U) +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +#define I2S_RCR3_CFR_MASK (0x3000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - Receive Configuration 4 */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - Receive Configuration 5 */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - Receive FIFO */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - Receive Mask */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + +/*! @name MCR - MCLK Control */ +/*! @{ */ + +#define I2S_MCR_DIV_MASK (0xFFU) +#define I2S_MCR_DIV_SHIFT (0U) +/*! DIV - MCLK Post Divide */ +#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) + +#define I2S_MCR_DIVEN_MASK (0x800000U) +#define I2S_MCR_DIVEN_SHIFT (23U) +/*! DIVEN - MCLK Post Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) + +#define I2S_MCR_MSEL_MASK (0x3000000U) +#define I2S_MCR_MSEL_SHIFT (24U) +/*! MSEL - MCLK Select + * 0b00..Controller clock (MCLK) option 1 + * 0b01..Reserved + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) + +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..Input + * 0b1..Output + */ +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b1..Disabled, if configured + * 0b0..Enabled + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b1..Enable HDR OK + * 0b0..Disable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b1..Handled automatically + * 0b0..No CCC message handled + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b1..I3C bus in HDR-DDR mode + * 0b0..I3C bus not in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b1..Received message pending + * 0b0..No received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b1..Transmit buffer not full + * 0b0..Transmit buffer full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error + * 0b1..Overrun error + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Underrun error + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error + * 0b1..Terminated error + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error + * 0b1..Invalid start error + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error + * 0b1..Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error + * 0b1..Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b1..Full + * 0b0..Not full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b1..Empty + * 0b0..Not empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) +#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) +/*! I2CRST - I2C Software Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b1..Subscriber capable + * 0b0..Not subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b1..Write capable + * 0b0..Not write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + * *.. + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + * *.. + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Target Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10-Bit Static Address */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b1..I2C static address + * 0b0..I3C dynamic address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b1..NACKed (not acknowledged) + * 0b0..Not NACKed + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start + * 0b1..Target requesting START + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done + * 0b1..Done + * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete + * 0b1..Complete + * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b1..Receive message pending + * 0b0..No receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b1..Receive buffer or FIFO not full + * 0b0..Receive buffer or FIFO full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won + * 0b1..IBI arbitration won + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b1..Error or warning + * 0b0..No error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b1..Without mandatory IBI byte + * 0b0..With mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b1..Valid DA assigned + * 0b0..No valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + * *.. + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Target Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x20 */ + __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ + __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ + __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ + __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ + __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ + __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ + __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ + __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ + __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ + __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ + __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ + __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[160]; + __IO uint32_t FREQMEAS_REF; /**< Selection for Frequency Measurement Reference Clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for Frequency Measurement Target Clock, offset: 0x184 */ + uint8_t RESERVED_5[24]; + __IO uint32_t CTIMER3CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A0 */ + __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ + __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ + __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ + __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ + __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ + __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ + __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ + __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ + uint8_t RESERVED_7[140]; + __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ + uint8_t RESERVED_8[28]; + __IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[48]; + __IO uint32_t ADC1_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_10[144]; + struct { /* offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ + __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ + __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ + __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ + uint8_t RESERVED_0[12]; + } QDCN[2]; + __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ + __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ + uint8_t RESERVED_11[12]; + __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ + __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ + uint8_t RESERVED_13[24]; + __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ + uint8_t RESERVED_14[64]; + __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ + uint8_t RESERVED_15[188]; + __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ + uint8_t RESERVED_17[28]; + __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ + uint8_t RESERVED_18[28]; + __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ + uint8_t RESERVED_19[28]; + __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ + uint8_t RESERVED_20[28]; + __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ + uint8_t RESERVED_21[28]; + __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ + uint8_t RESERVED_22[28]; + __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ + uint8_t RESERVED_23[92]; + __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ + __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ + __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ + __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ + __O uint32_t DMA0_REQ_ENABLE0_TOG; /**< DMA0 Request Enable0, offset: 0x70C */ + __IO uint32_t DMA0_REQ_ENABLE1; /**< DMA0 Request Enable1, offset: 0x710 */ + __O uint32_t DMA0_REQ_ENABLE1_SET; /**< DMA0 Request Enable1, offset: 0x714 */ + __O uint32_t DMA0_REQ_ENABLE1_CLR; /**< DMA0 Request Enable1, offset: 0x718 */ + __O uint32_t DMA0_REQ_ENABLE1_TOG; /**< DMA0 Request Enable1, offset: 0x71C */ + __IO uint32_t DMA0_REQ_ENABLE2; /**< DMA0 Request Enable2, offset: 0x720 */ + __O uint32_t DMA0_REQ_ENABLE2_SET; /**< DMA0 Request Enable2, offset: 0x724 */ + __O uint32_t DMA0_REQ_ENABLE2_CLR; /**< DMA0 Request Enable2, offset: 0x728 */ + __O uint32_t DMA0_REQ_ENABLE2_TOG; /**< DMA0 Request Enable2, offset: 0x72C */ + __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ + __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ + __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ + uint8_t RESERVED_24[68]; + __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ + __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ + __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ + __O uint32_t DMA1_REQ_ENABLE0_TOG; /**< DMA1 Request Enable0, offset: 0x78C */ + __IO uint32_t DMA1_REQ_ENABLE1; /**< DMA1 Request Enable1, offset: 0x790 */ + __O uint32_t DMA1_REQ_ENABLE1_SET; /**< DMA1 Request Enable1, offset: 0x794 */ + __O uint32_t DMA1_REQ_ENABLE1_CLR; /**< DMA1 Request Enable1, offset: 0x798 */ + __O uint32_t DMA1_REQ_ENABLE1_TOG; /**< DMA1 Request Enable1, offset: 0x79C */ + __IO uint32_t DMA1_REQ_ENABLE2; /**< DMA1 Request Enable2, offset: 0x7A0 */ + __O uint32_t DMA1_REQ_ENABLE2_SET; /**< DMA1 Request Enable2, offset: 0x7A4 */ + __O uint32_t DMA1_REQ_ENABLE2_CLR; /**< DMA1 Request Enable2, offset: 0x7A8 */ + __O uint32_t DMA1_REQ_ENABLE2_TOG; /**< DMA1 Request Enable2, offset: 0x7AC */ + __IO uint32_t DMA1_REQ_ENABLE3; /**< DMA1 Request Enable3, offset: 0x7B0 */ + __O uint32_t DMA1_REQ_ENABLE3_SET; /**< DMA1 Request Enable3, offset: 0x7B4 */ + __O uint32_t DMA1_REQ_ENABLE3_CLR; /**< DMA1 Request Enable3, offset: 0x7B8 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMER0CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER0TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER1TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER2TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX - Inputmux Register for SMARTDMA Arch B Inputs */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) +/*! INP - Input number select to SmartDMA ARCHB input + * 0b0000000..FlexIO interrupt is selected as input + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..Reserved + * 0b0010001..Reserved + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..MRT0 MRT_CH0_IRQ input is selected + * 0b0010101..MRT0 MRT_CH1_IRQ input is selected + * 0b0010110..CTIMER4_MAT3 input is selected + * 0b0010111..CTIMER4_MAT2 input is selected + * 0b0011000..CTIMER3_MAT3 input is selected + * 0b0011001..CTIMER3_MAT2 input is selected + * 0b0011010..CTIMER1_MAT3 input is selected + * 0b0011011..CTIMER1_MAT2 input is selected + * 0b0011100..UTICK0 UTICK_IRQ input is selected + * 0b0011101..WWDT0 WDT0_IRQ input is selected + * 0b0011110..ADC0 ADC0_IRQ input is selected + * 0b0011111..CMP0_IRQ input is selected + * 0b0100000..Reserved + * 0b0100001..LP_FLEXCOMM7_IRQ input is selected + * 0b0100010..LP_FLEXCOMM6_IRQ input is selected + * 0b0100011..LP_FLEXCOMM5_IRQ input is selected + * 0b0100100..LP_FLEXCOMM4_IRQ input is selected + * 0b0100101..LP_FLEXCOMM3_IRQ input is selected + * 0b0100110..LP_FLEXCOMM2_IRQ input is selected + * 0b0100111..LP_FLEXCOMM1_IRQ input is selected + * 0b0101000..LP_FLEXCOMM0_IRQ input is selected + * 0b0101001..DMA0_IRQ input is selected + * 0b0101010..DMA1_IRQ input is selected + * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure + * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR + * operation. input is selected + * 0b0101100..RTC_COMBO_IRQ input is selected + * 0b0101101..ARM_TXEV input is selected + * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CMP0_OUT input is selected + * 0b0110010..usb0 start of frame input is selected + * 0b0110011..usb1 start of frame input is selected + * 0b0110100..OSTIMER0 OS_EVENT_TIMER_IRQ input is selected + * 0b0110101..ADC1_IRQ input is selected + * 0b0110110..CMP0_IRQ/CMP1_IRQ input is selected + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..PWM0_IRQ input is selected + * 0b0111010..PWM1_IRQ input is selected + * 0b0111011..QDC0_IRQ input is selected + * 0b0111100..QDC1_IRQ input is selected + * 0b0111101..EVTG_OUT0A input is selected + * 0b0111110..EVTG_OUT1A input is selected + * 0b0111111..Reserved + * 0b1000000..Reserved + * 0b1000001..GPIO1_alias0 GPIO1 Pin Event Trig 0 input is selected + * 0b1000010..GPIO1_alias1 GPIO1 Pin Event Trig 1 input is selected + * 0b1000011..GPIO2_alias0 GPIO2 Pin Event Trig 0 input is selected + * 0b1000100..GPIO2_alias1 GPIO2 Pin Event Trig 1 input is selected + * 0b1000101..GPIO3_alias0 GPIO3 Pin Event Trig 0 input is selected + * 0b1000110..GPIO3_alias1 GPIO3 Pin Event Trig 1 input is selected + * 0b1000111..FlexIO Shifter DMA Request 0 is selected + * 0b1001000..FlexIO Shifter DMA Request 1 is selected + * 0b1001001..FlexIO Shifter DMA Request 2 is selected + * 0b1001010..FlexIO Shifter DMA Request 3 is selected + * 0b1001011..FlexIO Shifter DMA Request 4 is selected + * 0b1001100..FlexIO Shifter DMA Request 5 is selected + * 0b1001101..FlexIO Shifter DMA Request 6 is selected + * 0b1001110..FlexIO Shifter DMA Request 7 is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_COUNT (8U) + +/*! @name INPUTMUX_GPIO_INT_PINTSEL - Pin Interrupt Select */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT (0U) +/*! INP - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INP = (x * + * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + * 0b0000000..GPIO P0_0 input is selected + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..GPIO P0_16 input is selected + * 0b0010001..GPIO P0_17 input is selected + * 0b0010010..GPIO P0_18 input is selected + * 0b0010011..GPIO P0_19 input is selected + * 0b0010100..GPIO P0_20 input is selected + * 0b0010101..GPIO P0_21 input is selected + * 0b0010110..GPIO P0_22 input is selected + * 0b0010111..GPIO P0_23 input is selected + * 0b0011000..GPIO P0_24 input is selected + * 0b0011001..GPIO P0_25 input is selected + * 0b0011010..GPIO P0_26 input is selected + * 0b0011011..GPIO P0_27 input is selected + * 0b0011100..GPIO P0_28 input is selected + * 0b0011101..GPIO P0_29 input is selected + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..GPIO P1_0 input is selected + * 0b0100001..GPIO P1_1 input is selected + * 0b0100010..GPIO P1_2 input is selected + * 0b0100011..GPIO P1_3 input is selected + * 0b0100100..GPIO P1_4 input is selected + * 0b0100101..GPIO P1_5 input is selected + * 0b0100110..GPIO P1_6 input is selected + * 0b0100111..GPIO P1_7 input is selected + * 0b0101000..GPIO P1_8 input is selected + * 0b0101001..GPIO P1_9 input is selected + * 0b0101010..GPIO P1_10 input is selected + * 0b0101011..GPIO P1_11 input is selected + * 0b0101100..GPIO P1_12 input is selected + * 0b0101101..GPIO P1_13 input is selected + * 0b0101110..GPIO P1_14 input is selected + * 0b0101111..GPIO P1_15 input is selected + * 0b0110000..GPIO P1_16 input is selected + * 0b0110001..GPIO P1_17 input is selected + * 0b0110010..GPIO P1_18 input is selected + * 0b0110011..GPIO P1_19 input is selected + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..GPIO P1_30 input is selected + * 0b0111111..GPIO P1_31 input is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT)) & INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_COUNT (8U) + +/*! @name FREQMEAS_REF - Selection for Frequency Measurement Reference Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function reference clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for Frequency Measurement Target Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER3TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER4TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) +/*! @} */ + +/*! @name CMP0_TRIG - CMP0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER0_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC1_tcomp[0] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT1 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT3 input is selected + * 0b00001001..CTIMER4_MAT3 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGN_ADC1_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC1 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT2 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT2 input is selected + * 0b00001001..CTIMER4_MAT1 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) + +/*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_TRIG */ +#define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) + +/*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) +/*! INP - QDC1 HOME input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_HOME */ +#define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) + +/*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 INDEX input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_INDEX */ +#define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) + +/*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 PHASEB input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEB */ +#define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) + +/*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) +/*! INP - QDC1 PHASEA input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEA */ +#define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) + +/*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA - PWM0 Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM0_EXTFORCE - PWM0 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM_FAULT_FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_COUNT (4U) + +/*! @name FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC - PWM1 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM1_EXTFORCE - PWM1 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_FAULT */ +#define INPUTMUX_FLEXPWM1_FAULT_COUNT (4U) + +/*! @name PWM0_EXT_CLK - PWM0 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM0 + * 0b000..FRO16K input is selected + * 0b001..OSC_32k input is selected + * 0b010..EVTG_OUT0A input is selected + * 0b011..EVTG_OUT1A input is selected + * 0b100..TRIG_IN0 input is selected + * 0b101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM1 + * 0b0000..FRO16K input is selected + * 0b0001..OSC_32k input is selected + * 0b0010..EVTG_OUT0A input is selected + * 0b0011..EVTG_OUT1A input is selected + * 0b0100..TRIG_IN0 input is selected + * 0b0101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) +/*! INP - EVTG trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT3 input is selected + * 0b000111..CTIMER1_MAT3 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER2_MAT2 input is selected + * 0b001010..CTIMER3_MAT2 input is selected + * 0b001011..CTIMER4_MAT2 input is selected + * 0b001100..Reserved + * 0b001101..PINT GPIO_INT_BMAT input is selected + * 0b001110..ADC0_IRQ input is selected + * 0b001111..ADC1_IRQ input is selected + * 0b010000..ADC0_tcomp[0] input is selected + * 0b010001..ADC0_tcomp[1] input is selected + * 0b010010..ADC0_tcomp[2] input is selected + * 0b010011..ADC0_tcomp[3] input is selected + * 0b010100..ADC1_tcomp[0] input is selected + * 0b010101..ADC1_tcomp[1] input is selected + * 0b010110..ADC1_tcomp[2] input is selected + * 0b010111..ADC1_tcomp[3] input is selected + * 0b011000..CMP0_OUT input is selected + * 0b011001..CMP1_OUT input is selected + * 0b011010..Reserved + * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected + * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected + * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected + * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101011..QDC0_CMP/POS_MATCH input is selected + * 0b101100..QDC1_CMP/POS_MATCH input is selected + * 0b101101..TRIG_IN0 input is selected + * 0b101110..TRIG_IN1 input is selected + * 0b101111..TRIG_IN2 input is selected + * 0b110000..TRIG_IN3 input is selected + * 0b110001..LPTMR0 input is selected + * 0b110010..LPTMR1 input is selected + * 0b110011..Reserved + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) + +/*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..ADC0_IRQ input is selected + * 0b000011..ADC1_IRQ input is selected + * 0b000100..ADC0_tcomp[0] input is selected + * 0b000101..ADC1_tcomp[0] input is selected + * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b001110..QDC0_CMP/POS_MATCH input is selected + * 0b001111..QDC1_CMP/POS_MATCH input is selected + * 0b010000..EVTG_OUT0A input is selected + * 0b010001..EVTG_OUT0B input is selected + * 0b010010..EVTG_OUT1A input is selected + * 0b010011..EVTG_OUT1B input is selected + * 0b010100..EVTG_OUT2A input is selected + * 0b010101..EVTG_OUT2B input is selected + * 0b010110..EVTG_OUT3A input is selected + * 0b010111..EVTG_OUT3B input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..LPTMR0 input is selected + * 0b011011..LPTMR1 input is selected + * 0b011100..Reserved + * 0b011101..Reserved + * 0b011110..Reserved + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..Reserved + * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected + * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected + * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected + * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected + * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected + * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected + * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected + * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..CMP0_OUT input is selected + * 0b101101..CMP1_OUT input is selected + * 0b101110..Reserved + * 0b101111..Reserved + * *.. + */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) + +/*! @name CMP1_TRIG - CMP1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP1 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT7 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER3_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[1] input is selected + * 0b001110..ADC1_tcomp[1] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM0 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM0_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM1_TRIG - LP_FLEXCOMM1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM1 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM1_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM2_TRIG - LP_FLEXCOMM2 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM2 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM2_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM3_TRIG - LP_FLEXCOMM3 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM3 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM3_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM3_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM4_TRIG - LP_FLEXCOMM4 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM4 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM4_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM4_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM5_TRIG - LP_FLEXCOMM5 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM5 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM5_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM5_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM6_TRIG - LP_FLEXCOMM6 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM6 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM6_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM6_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM7_TRIG - LP_FLEXCOMM7 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM7 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM7_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM7_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..PINT PIN_INT4 input is selected + * 0b0000001..PINT PIN_INT5 input is selected + * 0b0000010..PINT PIN_INT6 input is selected + * 0b0000011..PINT PIN_INT7 input is selected + * 0b0000100..Reserved + * 0b0000101..Reserved + * 0b0000110..Reserved + * 0b0000111..Reserved + * 0b0001000..Reserved + * 0b0001001..T0_MAT1 input is selected + * 0b0001010..T1_MAT1 input is selected + * 0b0001011..T2_MAT1 input is selected + * 0b0001100..T3_MAT1 input is selected + * 0b0001101..T4_MAT1 input is selected + * 0b0001110..LPTMR0 input is selected + * 0b0001111..LPTMR1 input is selected + * 0b0010000..Reserved + * 0b0010001..PINT GPIO_INT_BMAT input is selected + * 0b0010010..ADC0_tcomp[0] input is selected + * 0b0010011..ADC0_tcomp[1] input is selected + * 0b0010100..ADC0_tcomp[2] input is selected + * 0b0010101..ADC0_tcomp[3] input is selected + * 0b0010110..ADC1_tcomp[0] input is selected + * 0b0010111..ADC1_tcomp[1] input is selected + * 0b0011000..ADC1_tcomp[2] input is selected + * 0b0011001..ADC1_tcomp[3] input is selected + * 0b0011010..CMP0_OUT input is selected + * 0b0011011..CMP1_OUT input is selected + * 0b0011100..Reserved + * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected + * 0b0101101..EVTG_OUT0A input is selected + * 0b0101110..EVTG_OUT0B input is selected + * 0b0101111..EVTG_OUT1A input is selected + * 0b0110000..EVTG_OUT1B input is selected + * 0b0110001..EVTG_OUT2A input is selected + * 0b0110010..EVTG_OUT2B input is selected + * 0b0110011..EVTG_OUT3A input is selected + * 0b0110100..EVTG_OUT3B input is selected + * 0b0110101..TRIG_IN0 input is selected + * 0b0110110..TRIG_IN1 input is selected + * 0b0110111..TRIG_IN2 input is selected + * 0b0111000..TRIG_IN3 input is selected + * 0b0111001..TRIG_IN4 input is selected + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..Reserved + * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected + * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected + * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected + * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected + * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected + * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected + * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected + * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected + * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected + * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected + * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected + * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected + * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected + * 0b1001100..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) + +/*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_SET - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_CLR - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_TOG - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to RE9_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1 - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_SET - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_CLR - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_TOG - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2 - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_SET - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ876_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_CLR - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_TOG - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3 - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_SET - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_CLR - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0 - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_SET - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_CLR - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_TOG - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to RE9_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1 - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_SET - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_CLR - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_TOG - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2 - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_SET - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ876_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_CLR - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_TOG - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3 - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_SET - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_CLR - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3. */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif +/* Backward compatibility for INPUTMUX */ +#define INPUTMUX INPUTMUX0 + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer + * @{ + */ + +/** INTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t INTM_MM; /**< Monitor Mode, offset: 0x0 */ + __O uint32_t INTM_IACK; /**< Interrupt Acknowledge, offset: 0x4 */ + struct { /* offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_IRQSEL; /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_LATENCY; /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */ + __IO uint32_t INTM_TIMER; /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */ + __I uint32_t INTM_STATUS; /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */ + } MON[4]; +} INTM_Type; + +/* ---------------------------------------------------------------------------- + -- INTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Register_Masks INTM Register Masks + * @{ + */ + +/*! @name INTM_MM - Monitor Mode */ +/*! @{ */ + +#define INTM_INTM_MM_MM_MASK (0x1U) +#define INTM_INTM_MM_MM_SHIFT (0U) +/*! MM - Monitor Mode + * 0b1..Enable + * 0b0..Disable + */ +#define INTM_INTM_MM_MM(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK) +/*! @} */ + +/*! @name INTM_IACK - Interrupt Acknowledge */ +/*! @{ */ + +#define INTM_INTM_IACK_IRQ_MASK (0x3FFU) +#define INTM_INTM_IACK_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_INTM_IACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK) +/*! @} */ + +/*! @name MON_INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_IRQSEL_IRQ_MASK (0x3FFU) +#define INTM_MON_INTM_IRQSEL_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_MON_INTM_IRQSEL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_IRQSEL_IRQ_SHIFT)) & INTM_MON_INTM_IRQSEL_IRQ_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_IRQSEL */ +#define INTM_MON_INTM_IRQSEL_COUNT (4U) + +/*! @name MON_INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_LATENCY_LAT_MASK (0xFFFFFFU) +#define INTM_MON_INTM_LATENCY_LAT_SHIFT (0U) +/*! LAT - Latency */ +#define INTM_MON_INTM_LATENCY_LAT(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_LATENCY_LAT_SHIFT)) & INTM_MON_INTM_LATENCY_LAT_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_LATENCY */ +#define INTM_MON_INTM_LATENCY_COUNT (4U) + +/*! @name MON_INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_TIMER_TIMER_MASK (0xFFFFFFU) +#define INTM_MON_INTM_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer */ +#define INTM_MON_INTM_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_TIMER_TIMER_SHIFT)) & INTM_MON_INTM_TIMER_TIMER_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_TIMER */ +#define INTM_MON_INTM_TIMER_COUNT (4U) + +/*! @name MON_INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_STATUS_STATUS_MASK (0x1U) +#define INTM_MON_INTM_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Monitor status + * 0b1..Exceeded + * 0b0..Did not exceed + */ +#define INTM_MON_INTM_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_STATUS_STATUS_SHIFT)) & INTM_MON_INTM_STATUS_STATUS_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_STATUS */ +#define INTM_MON_INTM_STATUS_COUNT (4U) + + +/*! + * @} + */ /* end of group INTM_Register_Masks */ + + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/*! + * @} + */ /* end of group INTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ITRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer + * @{ + */ + +/** ITRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ + __IO uint32_t STATUS1; /**< ITRC IN16 to IN47 Status, offset: 0x4 */ + __IO uint32_t OUT_SEL[7][2]; /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t OUT_SEL_1[7][2]; /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t OUT_SEL_2[7][2]; /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_2[48]; + __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ + __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ +} ITRC_Type; + +/* ---------------------------------------------------------------------------- + -- ITRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Register_Masks ITRC Register Masks + * @{ + */ + +/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ +/*! @{ */ + +#define ITRC_STATUS_IN0_STATUS_MASK (0x1U) +#define ITRC_STATUS_IN0_STATUS_SHIFT (0U) +/*! IN0_STATUS - GDET0 & 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) + +#define ITRC_STATUS_IN1_STATUS_MASK (0x2U) +#define ITRC_STATUS_IN1_STATUS_SHIFT (1U) +/*! IN1_STATUS - TDET tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) + +#define ITRC_STATUS_IN2_STATUS_MASK (0x4U) +#define ITRC_STATUS_IN2_STATUS_SHIFT (2U) +/*! IN2_STATUS - Code Watchdog 0 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) + +#define ITRC_STATUS_IN3_STATUS_MASK (0x8U) +#define ITRC_STATUS_IN3_STATUS_SHIFT (3U) +/*! IN3_STATUS - VDD_MAIN volt tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) + +#define ITRC_STATUS_IN4_STATUS_MASK (0x10U) +#define ITRC_STATUS_IN4_STATUS_SHIFT (4U) +/*! IN4_STATUS - SPC VDD_CORE_LVD detect. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) + +#define ITRC_STATUS_IN5_STATUS_MASK (0x20U) +#define ITRC_STATUS_IN5_STATUS_SHIFT (5U) +/*! IN5_STATUS - Watch Dog timer event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) + +#define ITRC_STATUS_IN6_STATUS_MASK (0x40U) +#define ITRC_STATUS_IN6_STATUS_SHIFT (6U) +/*! IN6_STATUS - Flash ECC mismatch event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) + +#define ITRC_STATUS_IN7_STATUS_MASK (0x80U) +#define ITRC_STATUS_IN7_STATUS_SHIFT (7U) +/*! IN7_STATUS - AHB secure bus checkers detected illegal access. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) + +#define ITRC_STATUS_IN8_STATUS_MASK (0x100U) +#define ITRC_STATUS_IN8_STATUS_SHIFT (8U) +/*! IN8_STATUS - ELS error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) + +#define ITRC_STATUS_IN9_STATUS_MASK (0x200U) +#define ITRC_STATUS_IN9_STATUS_SHIFT (9U) +/*! IN9_STATUS - SPC VDD_CORE glitch detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN9_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK) + +#define ITRC_STATUS_IN10_STATUS_MASK (0x400U) +#define ITRC_STATUS_IN10_STATUS_SHIFT (10U) +/*! IN10_STATUS - PKC module detected an error event. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) + +#define ITRC_STATUS_IN11_STATUS_MASK (0x800U) +#define ITRC_STATUS_IN11_STATUS_SHIFT (11U) +/*! IN11_STATUS - Code Watchdog 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN11_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK) + +#define ITRC_STATUS_IN112_STATUS_MASK (0x1000U) +#define ITRC_STATUS_IN112_STATUS_SHIFT (12U) +/*! IN112_STATUS - Watchdog 1 timer event interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN112_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN112_STATUS_SHIFT)) & ITRC_STATUS_IN112_STATUS_MASK) + +#define ITRC_STATUS_IN113_STATUS_MASK (0x2000U) +#define ITRC_STATUS_IN113_STATUS_SHIFT (13U) +/*! IN113_STATUS - FREQME out of range status output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN113_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN113_STATUS_SHIFT)) & ITRC_STATUS_IN113_STATUS_MASK) + +#define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) +#define ITRC_STATUS_IN14_STATUS_SHIFT (14U) +/*! IN14_STATUS - Software event 0 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) + +#define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) +#define ITRC_STATUS_IN15_STATUS_SHIFT (15U) +/*! IN15_STATUS - Software event 1 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) + +#define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) +#define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) +/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) + +#define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) +#define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) +/*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) + +#define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) +#define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) +/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) + +#define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) +#define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) +/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) + +#define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) +#define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) +/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) + +#define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) +#define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) +/*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) + +#define ITRC_STATUS_OUT6_STATUS_MASK (0x400000U) +#define ITRC_STATUS_OUT6_STATUS_SHIFT (22U) +/*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK) +/*! @} */ + +/*! @name STATUS1 - ITRC IN16 to IN47 Status */ +/*! @{ */ + +#define ITRC_STATUS1_IN16_STATUS_MASK (0x1U) +#define ITRC_STATUS1_IN16_STATUS_SHIFT (0U) +/*! IN16_STATUS - SSPC VDD_SYS_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN16_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK) + +#define ITRC_STATUS1_IN17_STATUS_MASK (0x2U) +#define ITRC_STATUS1_IN17_STATUS_SHIFT (1U) +/*! IN17_STATUS - SPC VDD_IO_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN17_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK) + +#define ITRC_STATUS1_IN18_STATUS_MASK (0x4U) +#define ITRC_STATUS1_IN18_STATUS_SHIFT (2U) +/*! IN18_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN18_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK) + +#define ITRC_STATUS1_IN19_STATUS_MASK (0x8U) +#define ITRC_STATUS1_IN19_STATUS_SHIFT (3U) +/*! IN19_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN19_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK) + +#define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) +#define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) +/*! IN20_STATUS - VDD_MAIN clock tamper output event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN20_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK) + +#define ITRC_STATUS1_IN24_21_STATUS_MASK (0x1E0U) +#define ITRC_STATUS1_IN24_21_STATUS_SHIFT (5U) +/*! IN24_21_STATUS - INTM interrupt monitor error 3~0 event occurred. + * 0b0000..Output not triggered. + * 0b0001..Output has been triggered. + */ +#define ITRC_STATUS1_IN24_21_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_21_STATUS_SHIFT)) & ITRC_STATUS1_IN24_21_STATUS_MASK) + +#define ITRC_STATUS1_IN32_25_STATUS_MASK (0x1FE00U) +#define ITRC_STATUS1_IN32_25_STATUS_SHIFT (9U) +/*! IN32_25_STATUS - MSF SOCTRIM 7~0 ECC error event occurred. + * 0b00000000..Output not triggered. + * 0b00000001..Output has been triggered. + */ +#define ITRC_STATUS1_IN32_25_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_25_STATUS_SHIFT)) & ITRC_STATUS1_IN32_25_STATUS_MASK) + +#define ITRC_STATUS1_IN33_STATUS_MASK (0x20000U) +#define ITRC_STATUS1_IN33_STATUS_SHIFT (17U) +/*! IN33_STATUS - GDET0/1 SFR error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN33_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK) + +#define ITRC_STATUS1_IN34_STATUS_MASK (0x40000U) +#define ITRC_STATUS1_IN34_STATUS_SHIFT (18U) +/*! IN34_STATUS - SPC VDD_CORE high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN34_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK) + +#define ITRC_STATUS1_IN35_STATUS_MASK (0x80000U) +#define ITRC_STATUS1_IN35_STATUS_SHIFT (19U) +/*! IN35_STATUS - SPC VDD_SYS_HVD high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN35_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK) + +#define ITRC_STATUS1_IN36_STATUS_MASK (0x100000U) +#define ITRC_STATUS1_IN36_STATUS_SHIFT (20U) +/*! IN36_STATUS - SPC VDD_IO high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN36_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK) + +#define ITRC_STATUS1_IN37_STATUS_MASK (0x200000U) +#define ITRC_STATUS1_IN37_STATUS_SHIFT (21U) +/*! IN37_STATUS - FLEXSPI GCM error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN37_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK) + +#define ITRC_STATUS1_IN46_STATUS_MASK (0x40000000U) +#define ITRC_STATUS1_IN46_STATUS_SHIFT (30U) +/*! IN46_STATUS - SM3 SGI error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN46_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN46_STATUS_SHIFT)) & ITRC_STATUS1_IN46_STATUS_MASK) + +#define ITRC_STATUS1_IN47_STATUS_MASK (0x80000000U) +#define ITRC_STATUS1_IN47_STATUS_SHIFT (31U) +/*! IN47_STATUS - TRNG HW error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN47_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK) +/*! @} */ + +/*! @name OUTX_SEL_OUTX_SELY_OUT_SEL - Trigger Source IN0 to IN15 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT (0U) +/*! IN0_SELn - Selects digital glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT (2U) +/*! IN1_SELn - Selects TDET event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT (4U) +/*! IN2_SELn - Selects Code Watchdog 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) +/*! IN3_SELn - Selects VDD_MAIN voltage tamper event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT (8U) +/*! IN4_SELn - Selects low-voltage event on VDD_CORE rail as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT (10U) +/*! IN5_SELn - Selects Watchdog 0 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT (12U) +/*! IN6_SELn - Selects Flash ECC mismatch event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT (14U) +/*! IN7_SELn - Selects AHB secure bus or MBC bus illegal access event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT (16U) +/*! IN8_SELn - Selects ELS error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT (18U) +/*! IN9_SELn - Selects SPC VDD_CORE glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT (20U) +/*! IN10_SELn - Selects PKC error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT (22U) +/*! IN11_SELn - Selects Code Watchdog 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT (24U) +/*! IN12_SELn - Selects Watchdog 1 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT (26U) +/*! IN13_SELn - Selects FREQME out of range status output as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT (28U) +/*! IN14_SELn - Selects software event 0 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT (30U) +/*! IN15_SELn - Selects software event 1 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT2 (2U) + +/*! @name OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 - Trigger Source IN16 to IN31 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT (0U) +/*! IN16_SELn - Selects SPC VDD_SYS_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT (2U) +/*! IN17_SELn - Selects SPC VDD_IO_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT (4U) +/*! IN18_SELn - Reserved. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) +/*! IN19_SELn - Selects VDD_MAIN temperature tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) +/*! IN20_SELn - Selects VDD_MAIN clock tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT (10U) +/*! IN21_SELn - Selects INTM interrupt monitor error 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT (12U) +/*! IN22_SELn - Selects INTM interrupt monitor error 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT (14U) +/*! IN23_SELn - Selects INTM interrupt monitor error 2 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT (16U) +/*! IN24_SELn - Selects INTM interrupt monitor error 3 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT (18U) +/*! IN25_SELn - Selects MSF SOCTRIM 0 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT (20U) +/*! IN26_SELn - Selects MSF SOCTRIM 1 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT (22U) +/*! IN27_SELn - Selects MSF SOCTRIM 2 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT (24U) +/*! IN28_SELn - Selects MSF SOCTRIM 3 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT (26U) +/*! IN29_SELn - Selects MSF SOCTRIM 4 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT (28U) +/*! IN30_SELn - Selects MSF SOCTRIM 5 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT (30U) +/*! IN31_SELn - Selects MSF SOCTRIM 6 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT2 (2U) + +/*! @name OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 - Trigger source IN32 to IN47 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT (0U) +/*! IN32_SELn - Selects MSF SOCTRIM 7 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT (2U) +/*! IN33_SELn - Selects GDET0 & 1 SFR error detect as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT (4U) +/*! IN34_SELn - Selects SPC VDD_CORE_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT (6U) +/*! IN35_SELn - Selects VDD_SYS_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT (8U) +/*! IN36_SELn - Selects VDD_IO_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT (10U) +/*! IN37_SELn - Selects FLEXSPI GCM error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT (28U) +/*! IN46_SELn - Selects SM3 SGI error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT (30U) +/*! IN47_SELn - Selects TRNG HW Error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT2 (2U) + +/*! @name SW_EVENT0 - Software event 0 */ +/*! @{ */ + +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) +/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */ +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) +/*! @} */ + +/*! @name SW_EVENT1 - Software event 1 */ +/*! @{ */ + +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) +/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */ +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ITRC_Register_Masks */ + + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/*! + * @} + */ /* end of group ITRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ + uint8_t RESERVED_13[132]; + __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t MTDBR[253]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x7U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x70000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0xFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + +/*! @name MTCBR - Controller Transmit Command Burst */ +/*! @{ */ + +#define LPI2C_MTCBR_DATA_MASK (0xFFU) +#define LPI2C_MTCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) + +#define LPI2C_MTCBR_CMD_MASK (0x700U) +#define LPI2C_MTCBR_CMD_SHIFT (8U) +/*! CMD - Command */ +#define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) +/*! @} */ + +/* The count of LPI2C_MTCBR */ +#define LPI2C_MTCBR_COUNT (128U) + +/*! @name MTDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPI2C_MTDBR_DATA0_MASK (0xFFU) +#define LPI2C_MTDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data */ +#define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) + +#define LPI2C_MTDBR_DATA1_MASK (0xFF00U) +#define LPI2C_MTDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data */ +#define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) + +#define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) +#define LPI2C_MTDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data */ +#define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) + +#define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) +#define LPI2C_MTDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data */ +#define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPI2C_MTDBR */ +#define LPI2C_MTDBR_COUNT (253U) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + * *.. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ + __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ + __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ + __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ + __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ + __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ + __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_2[400]; + __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MSF_MASK (0x100U) +#define LPUART_STAT_MSF_SHIFT (8U) +/*! MSF - MODEM Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) + +#define LPUART_STAT_TSF_MASK (0x200U) +#define LPUART_STAT_TSF_SHIFT (9U) +/*! TSF - Timeout Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x700U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x7U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0xF00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x70000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0xF000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + +/*! @name MCR - MODEM Control */ +/*! @{ */ + +#define LPUART_MCR_CTS_MASK (0x1U) +#define LPUART_MCR_CTS_SHIFT (0U) +/*! CTS - Clear To Send + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) + +#define LPUART_MCR_DSR_MASK (0x2U) +#define LPUART_MCR_DSR_SHIFT (1U) +/*! DSR - Data Set Ready + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) + +#define LPUART_MCR_RIN_MASK (0x4U) +#define LPUART_MCR_RIN_SHIFT (2U) +/*! RIN - Ring Indicator + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) + +#define LPUART_MCR_DCD_MASK (0x8U) +#define LPUART_MCR_DCD_SHIFT (3U) +/*! DCD - Data Carrier Detect + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) + +#define LPUART_MCR_DTR_MASK (0x100U) +#define LPUART_MCR_DTR_SHIFT (8U) +/*! DTR - Data Terminal Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) + +#define LPUART_MCR_RTS_MASK (0x200U) +#define LPUART_MCR_RTS_SHIFT (9U) +/*! RTS - Request To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) +/*! @} */ + +/*! @name MSR - MODEM Status */ +/*! @{ */ + +#define LPUART_MSR_DCTS_MASK (0x1U) +#define LPUART_MSR_DCTS_SHIFT (0U) +/*! DCTS - Delta Clear To Send + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) + +#define LPUART_MSR_DDSR_MASK (0x2U) +#define LPUART_MSR_DDSR_SHIFT (1U) +/*! DDSR - Delta Data Set Ready + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) + +#define LPUART_MSR_DRI_MASK (0x4U) +#define LPUART_MSR_DRI_SHIFT (2U) +/*! DRI - Delta Ring Indicator + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) + +#define LPUART_MSR_DDCD_MASK (0x8U) +#define LPUART_MSR_DDCD_SHIFT (3U) +/*! DDCD - Delta Data Carrier Detect + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) + +#define LPUART_MSR_CTS_MASK (0x10U) +#define LPUART_MSR_CTS_SHIFT (4U) +/*! CTS - Clear To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) + +#define LPUART_MSR_DSR_MASK (0x20U) +#define LPUART_MSR_DSR_SHIFT (5U) +/*! DSR - Data Set Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) + +#define LPUART_MSR_RIN_MASK (0x40U) +#define LPUART_MSR_RIN_SHIFT (6U) +/*! RIN - Ring Indicator + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) + +#define LPUART_MSR_DCD_MASK (0x80U) +#define LPUART_MSR_DCD_SHIFT (7U) +/*! DCD - Data Carrier Detect + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) +/*! @} */ + +/*! @name REIR - Receiver Extended Idle */ +/*! @{ */ + +#define LPUART_REIR_IDTIME_MASK (0x3FFFU) +#define LPUART_REIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) +/*! @} */ + +/*! @name TEIR - Transmitter Extended Idle */ +/*! @{ */ + +#define LPUART_TEIR_IDTIME_MASK (0x3FFFU) +#define LPUART_TEIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) +/*! @} */ + +/*! @name HDCR - Half Duplex Control */ +/*! @{ */ + +#define LPUART_HDCR_TXSTALL_MASK (0x1U) +#define LPUART_HDCR_TXSTALL_SHIFT (0U) +/*! TXSTALL - Transmit Stall + * 0b0..No effect + * 0b1..Does not become busy + */ +#define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) + +#define LPUART_HDCR_RXSEL_MASK (0x2U) +#define LPUART_HDCR_RXSEL_SHIFT (1U) +/*! RXSEL - Receive Select + * 0b0..RXD + * 0b1..TXD + */ +#define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) + +#define LPUART_HDCR_RXWRMSK_MASK (0x4U) +#define LPUART_HDCR_RXWRMSK_SHIFT (2U) +/*! RXWRMSK - Receive FIFO Write Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) + +#define LPUART_HDCR_RXMSK_MASK (0x8U) +#define LPUART_HDCR_RXMSK_SHIFT (3U) +/*! RXMSK - Receive Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) + +#define LPUART_HDCR_RTSEXT_MASK (0xFF00U) +#define LPUART_HDCR_RTSEXT_SHIFT (8U) +/*! RTSEXT - RTS Extended */ +#define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) +/*! @} */ + +/*! @name TOCR - Timeout Control */ +/*! @{ */ + +#define LPUART_TOCR_TOEN_MASK (0xFU) +#define LPUART_TOCR_TOEN_SHIFT (0U) +/*! TOEN - Timeout Enable */ +#define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) + +#define LPUART_TOCR_TOIE_MASK (0xF00U) +#define LPUART_TOCR_TOIE_SHIFT (8U) +/*! TOIE - Timeout Interrupt Enable */ +#define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) +/*! @} */ + +/*! @name TOSR - Timeout Status */ +/*! @{ */ + +#define LPUART_TOSR_TOZ_MASK (0xFU) +#define LPUART_TOSR_TOZ_SHIFT (0U) +/*! TOZ - Timeout Zero */ +#define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) + +#define LPUART_TOSR_TOF_MASK (0xF00U) +#define LPUART_TOSR_TOF_SHIFT (8U) +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0001..Occurred + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) +/*! @} */ + +/*! @name TIMEOUT - Timeout N */ +/*! @{ */ + +#define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) +#define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) +/*! TIMEOUT - Timeout Value */ +#define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) + +#define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) +#define LPUART_TIMEOUT_CFG_SHIFT (30U) +/*! CFG - Idle Configuration + * 0b00..Becomes 1 after timeout characters are received + * 0b01..Becomes 1 when idle for timeout bit clocks + * 0b10..Becomes 1 when idle for timeout bit clocks following the next character + * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached + */ +#define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) +/*! @} */ + +/* The count of LPUART_TIMEOUT */ +#define LPUART_TIMEOUT_COUNT (4U) + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPUART_TCBR_DATA_MASK (0xFFFFU) +#define LPUART_TCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) +/*! @} */ + +/* The count of LPUART_TCBR */ +#define LPUART_TCBR_COUNT (128U) + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPUART_TDBR_DATA0_MASK (0xFFU) +#define LPUART_TDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data0 */ +#define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) + +#define LPUART_TDBR_DATA1_MASK (0xFF00U) +#define LPUART_TDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data1 */ +#define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) + +#define LPUART_TDBR_DATA2_MASK (0xFF0000U) +#define LPUART_TDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data2 */ +#define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) + +#define LPUART_TDBR_DATA3_MASK (0xFF000000U) +#define LPUART_TDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data3 */ +#define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPUART_TDBR */ +#define LPUART_TDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** LP_FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4084]; + __I uint32_t ISTAT; /**< Interrupt Status, offset: 0xFF4 */ + __IO uint32_t PSELID; /**< Peripheral Select and ID, offset: 0xFF8 */ +} LP_FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks + * @{ + */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define LP_FLEXCOMM_ISTAT_UARTTX_MASK (0x1U) +#define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT (0U) +/*! UARTTX - UART TX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTTX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK) + +#define LP_FLEXCOMM_ISTAT_UARTRX_MASK (0x2U) +#define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT (1U) +/*! UARTRX - UART RX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTRX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK) + +#define LP_FLEXCOMM_ISTAT_SPI_MASK (0x4U) +#define LP_FLEXCOMM_ISTAT_SPI_SHIFT (2U) +/*! SPI - SPI Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_SPI(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CM_MASK (0x10U) +#define LP_FLEXCOMM_ISTAT_I2CM_SHIFT (4U) +/*! I2CM - I2C Controller Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CM(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CS_MASK (0x20U) +#define LP_FLEXCOMM_ISTAT_I2CS_SHIFT (5U) +/*! I2CS - I2C Subordinate Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CS(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK) +/*! @} */ + +/*! @name PSELID - Peripheral Select and ID */ +/*! @{ */ + +#define LP_FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define LP_FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select + * 0b000..No peripheral selected + * 0b001..UART + * 0b011..I2C + * 0b111..UART and I2C + * 0b010..SPI + */ +#define LP_FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK) + +#define LP_FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define LP_FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock + * 0b0..PERSEL is writable + * 0b1..PERSEL is not writable + */ +#define LP_FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK) + +#define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK (0x10U) +#define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT (4U) +/*! UARTPRESENT - UART Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_UARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define LP_FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - LP_FLEXCOMM interface ID */ +#define LP_FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Register_Masks */ + + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - Time Interval Value */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time Interval Load Value. */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Force Load Enable + * 0b0..No force load + * 0b1..Force load + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - Timer */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Current Timer Value */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - Control */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Interrupt request + * 0b0..Disabled + * 0b1..Enabled + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - MRT Operating mode + * 0b00..Repeat Interrupt mode + * 0b01..One-Shot Interrupt mode + * 0b10..One-Shot Stall mode + * 0b11..Reserved + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - Status */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Timer n State + * 0b0..Idle state. + * 0b1..Running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel-In-Use flag + * 0b0..This timer channel is not in use. + * 0b1..This timer channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Number of Channels */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Number of Bits */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - MULTITASK + * 0b0..Hardware status mode. + * 0b1..Multitask mode + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle Channel */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle Channel */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global Interrupt Flag */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NPX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Peripheral_Access_Layer NPX Peripheral Access Layer + * @{ + */ + +/** NPX - Register Layout Typedef */ +typedef struct { + __IO uint32_t NPXCR; /**< NPX Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t NPXSR; /**< NPX Status Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __O uint32_t CACMSK; /**< Flash Cache Obfuscation Mask, offset: 0x10 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ + uint8_t RESERVED_3[28]; + struct { /* offset: 0x40, array step: 0x10 */ + __IO uint32_t VMAPCTX_WD[2]; /**< Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3, array offset: 0x40, array step: index*0x10, index2*0x4 */ + __O uint32_t BIVCTX_WD[2]; /**< Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3, array offset: 0x48, array step: index*0x10, index2*0x4 */ + } CTX_VALID_IV_ARRAY[4]; +} NPX_Type; + +/* ---------------------------------------------------------------------------- + -- NPX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Register_Masks NPX Register Masks + * @{ + */ + +/*! @name NPXCR - NPX Control Register */ +/*! @{ */ + +#define NPX_NPXCR_GEE_MASK (0x1U) +#define NPX_NPXCR_GEE_SHIFT (0U) +/*! GEE - Global Encryption Enable + * 0b1..Global encryption enabled. NPX on-the-fly encryption is enabled if the flash access hits in a valid + * memory context. Subsequent reads return 1. + * 0b0..Global encryption disabled. NPX on-the-fly encryption is disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GEE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GEE_SHIFT)) & NPX_NPXCR_GEE_MASK) + +#define NPX_NPXCR_GDE_MASK (0x4U) +#define NPX_NPXCR_GDE_SHIFT (2U) +/*! GDE - Global Decryption Enable + * 0b1..Global decryption enabled. NPX on-the-fly decryption is globally enabled. Subsequent reads return 1. + * 0b0..Global decryption disabled. NPX on-the-fly decryption is globally disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GDE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GDE_SHIFT)) & NPX_NPXCR_GDE_MASK) + +#define NPX_NPXCR_GLK_MASK (0x10U) +#define NPX_NPXCR_GLK_SHIFT (4U) +/*! GLK - Global Lock Enable + * 0b1..Lock enabled: cannot write to VMAPCTXn, NPXCR, or CACMSK. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GLK_SHIFT)) & NPX_NPXCR_GLK_MASK) + +#define NPX_NPXCR_MLK_MASK (0x40U) +#define NPX_NPXCR_MLK_SHIFT (6U) +/*! MLK - Mask Lock Enable + * 0b1..Lock enabled: cannot write to mask. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_MLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_MLK_SHIFT)) & NPX_NPXCR_MLK_MASK) + +#define NPX_NPXCR_CTX0LK_MASK (0x100U) +#define NPX_NPXCR_CTX0LK_SHIFT (8U) +/*! CTX0LK - Lock Enable for Context 0 + * 0b1..Lock enabled: cannot write to VMAPCTX0 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX0 remains read-write + */ +#define NPX_NPXCR_CTX0LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX0LK_SHIFT)) & NPX_NPXCR_CTX0LK_MASK) + +#define NPX_NPXCR_CTX1LK_MASK (0x400U) +#define NPX_NPXCR_CTX1LK_SHIFT (10U) +/*! CTX1LK - Lock Enable for Context 1 + * 0b1..Lock enabled: cannot write to VMAPCTX1 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX1 remains read-write + */ +#define NPX_NPXCR_CTX1LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX1LK_SHIFT)) & NPX_NPXCR_CTX1LK_MASK) + +#define NPX_NPXCR_CTX2LK_MASK (0x1000U) +#define NPX_NPXCR_CTX2LK_SHIFT (12U) +/*! CTX2LK - Lock Enable for Context 2 + * 0b1..Lock enabled: cannot write to VMAPCTX2 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX2 remains read-write + */ +#define NPX_NPXCR_CTX2LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX2LK_SHIFT)) & NPX_NPXCR_CTX2LK_MASK) + +#define NPX_NPXCR_CTX3LK_MASK (0x4000U) +#define NPX_NPXCR_CTX3LK_SHIFT (14U) +/*! CTX3LK - Lock Enable for Context 3 + * 0b1..Lock enabled: cannot write to VMAPCTX3 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX3 remains read-write + */ +#define NPX_NPXCR_CTX3LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX3LK_SHIFT)) & NPX_NPXCR_CTX3LK_MASK) +/*! @} */ + +/*! @name NPXSR - NPX Status Register */ +/*! @{ */ + +#define NPX_NPXSR_NUMCTX_MASK (0xFU) +#define NPX_NPXSR_NUMCTX_SHIFT (0U) +/*! NUMCTX - Number of implemented memory contexts + * 0b0000..No (zero) implemented memory contexts + * 0b0001..1 implemented memory contexts + * 0b0010..2 implemented memory contexts + * 0b0011..3 implemented memory contexts + * 0b0100..4 implemented memory contexts + */ +#define NPX_NPXSR_NUMCTX(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_NUMCTX_SHIFT)) & NPX_NPXSR_NUMCTX_MASK) + +#define NPX_NPXSR_V0_MASK (0x100U) +#define NPX_NPXSR_V0_SHIFT (8U) +/*! V0 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V0(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V0_SHIFT)) & NPX_NPXSR_V0_MASK) + +#define NPX_NPXSR_V1_MASK (0x200U) +#define NPX_NPXSR_V1_SHIFT (9U) +/*! V1 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V1(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V1_SHIFT)) & NPX_NPXSR_V1_MASK) + +#define NPX_NPXSR_V2_MASK (0x400U) +#define NPX_NPXSR_V2_SHIFT (10U) +/*! V2 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V2(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V2_SHIFT)) & NPX_NPXSR_V2_MASK) + +#define NPX_NPXSR_V3_MASK (0x800U) +#define NPX_NPXSR_V3_SHIFT (11U) +/*! V3 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V3(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V3_SHIFT)) & NPX_NPXSR_V3_MASK) +/*! @} */ + +/*! @name CACMSK - Flash Cache Obfuscation Mask */ +/*! @{ */ + +#define NPX_CACMSK_OBMASK_MASK (0xFFFFFFFFU) +#define NPX_CACMSK_OBMASK_SHIFT (0U) +/*! OBMASK - Obfuscation Mask */ +#define NPX_CACMSK_OBMASK(x) (((uint32_t)(((uint32_t)(x)) << NPX_CACMSK_OBMASK_SHIFT)) & NPX_CACMSK_OBMASK_MASK) +/*! @} */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define NPX_REMAP_REMAPLK_MASK (0x1U) +#define NPX_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b1..Lock enabled: cannot write to REMAP + * 0b0..Lock disabled: can write to REMAP + */ +#define NPX_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_REMAPLK_SHIFT)) & NPX_REMAP_REMAPLK_MASK) + +#define NPX_REMAP_LIM_MASK (0x1F0000U) +#define NPX_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) + +#define NPX_REMAP_LIMDP_MASK (0x1F000000U) +#define NPX_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) +/*! @} */ + +/*! @name CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD - Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT (0U) +/*! VAL0 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT (0U) +/*! VAL32 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT (1U) +/*! VAL1 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT (1U) +/*! VAL33 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT (2U) +/*! VAL2 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT (2U) +/*! VAL34 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT (3U) +/*! VAL3 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT (3U) +/*! VAL35 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT (4U) +/*! VAL4 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT (4U) +/*! VAL36 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT (5U) +/*! VAL5 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT (5U) +/*! VAL37 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT (6U) +/*! VAL6 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT (6U) +/*! VAL38 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT (7U) +/*! VAL7 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT (7U) +/*! VAL39 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT (8U) +/*! VAL8 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT (8U) +/*! VAL40 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT (9U) +/*! VAL9 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT (9U) +/*! VAL41 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT (10U) +/*! VAL10 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT (10U) +/*! VAL42 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT (11U) +/*! VAL11 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT (11U) +/*! VAL43 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT (12U) +/*! VAL12 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT (12U) +/*! VAL44 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT (13U) +/*! VAL13 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT (13U) +/*! VAL45 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT (14U) +/*! VAL14 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT (14U) +/*! VAL46 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT (15U) +/*! VAL15 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT (15U) +/*! VAL47 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT (16U) +/*! VAL16 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT (16U) +/*! VAL48 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT (17U) +/*! VAL17 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT (17U) +/*! VAL49 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT (18U) +/*! VAL18 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT (18U) +/*! VAL50 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT (19U) +/*! VAL19 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT (19U) +/*! VAL51 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT (20U) +/*! VAL20 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT (20U) +/*! VAL52 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT (21U) +/*! VAL21 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT (21U) +/*! VAL53 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT (22U) +/*! VAL22 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT (22U) +/*! VAL54 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT (23U) +/*! VAL23 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT (23U) +/*! VAL55 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT (24U) +/*! VAL24 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT (24U) +/*! VAL56 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT (25U) +/*! VAL25 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT (25U) +/*! VAL57 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT (26U) +/*! VAL26 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT (26U) +/*! VAL58 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT (27U) +/*! VAL27 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT (27U) +/*! VAL59 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT (28U) +/*! VAL28 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT (28U) +/*! VAL60 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT (29U) +/*! VAL29 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT (29U) +/*! VAL61 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT (30U) +/*! VAL30 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT (30U) +/*! VAL62 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT (31U) +/*! VAL31 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT (31U) +/*! VAL63 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT2 (2U) + +/*! @name CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD - Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT (0U) +/*! BIV_WD0 - Block Initial Vector Word0 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT (0U) +/*! BIV_WD1 - Block Initial Vector Word1 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT2 (2U) + + +/*! + * @} + */ /* end of group NPX_Register_Masks */ + + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/*! + * @} + */ /* end of group NPX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OTPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer + * @{ + */ + +/** OTPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameters, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RWC; /**< Read and Write Control, offset: 0x10 */ + __IO uint32_t RLC; /**< Reload Control, offset: 0x14 */ + __IO uint32_t PCR; /**< Power Control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t WDATA; /**< Write Data, offset: 0x20 */ + __I uint32_t RDATA; /**< Read Data, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t TIMING1; /**< Timing1, offset: 0x30 */ + __IO uint32_t TIMING2; /**< Timing2, offset: 0x34 */ + uint8_t RESERVED_3[456]; + __I uint32_t LOCK; /**< Lock, offset: 0x200 */ + __I uint32_t SECURE; /**< Secure, offset: 0x204 */ + __I uint32_t SECURE_INV; /**< Inverted Secure, offset: 0x208 */ + __I uint32_t DBG_KEY; /**< Debug and Key, offset: 0x20C */ + __IO uint32_t MISC_CFG; /**< MISC Config, offset: 0x210 */ + __IO uint32_t PHANTOM_CFG; /**< PHANTOM Config, offset: 0x214 */ + __IO uint32_t FLEX_CFG0; /**< Flexible Config 0, offset: 0x218 */ + __IO uint32_t FLEX_CFG1; /**< Flexible Config 1, offset: 0x21C */ +} OTPC_Type; + +/* ---------------------------------------------------------------------------- + -- OTPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Register_Masks OTPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OTPC_VERID_FEATURE_MASK (0xFFFFU) +#define OTPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define OTPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_FEATURE_SHIFT)) & OTPC_VERID_FEATURE_MASK) + +#define OTPC_VERID_MINOR_MASK (0xFF0000U) +#define OTPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OTPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MINOR_SHIFT)) & OTPC_VERID_MINOR_MASK) + +#define OTPC_VERID_MAJOR_MASK (0xFF000000U) +#define OTPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OTPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MAJOR_SHIFT)) & OTPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameters */ +/*! @{ */ + +#define OTPC_PARAM_NUM_FUSE_MASK (0xFFFFU) +#define OTPC_PARAM_NUM_FUSE_SHIFT (0U) +/*! NUM_FUSE - Number of fuse bytes */ +#define OTPC_PARAM_NUM_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PARAM_NUM_FUSE_SHIFT)) & OTPC_PARAM_NUM_FUSE_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define OTPC_SR_BUSY_MASK (0x1U) +#define OTPC_SR_BUSY_SHIFT (0U) +/*! BUSY - Busy status + * 0b0..Not busy (transaction complete) + * 0b1..Busy + */ +#define OTPC_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_BUSY_SHIFT)) & OTPC_SR_BUSY_MASK) + +#define OTPC_SR_ERROR_MASK (0x2U) +#define OTPC_SR_ERROR_SHIFT (1U) +/*! ERROR - Error flag + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ERROR_SHIFT)) & OTPC_SR_ERROR_MASK) + +#define OTPC_SR_ECC_SF_MASK (0x4U) +#define OTPC_SR_ECC_SF_SHIFT (2U) +/*! ECC_SF - ECC single fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_SF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_SF_SHIFT)) & OTPC_SR_ECC_SF_MASK) + +#define OTPC_SR_ECC_DF_MASK (0x8U) +#define OTPC_SR_ECC_DF_SHIFT (3U) +/*! ECC_DF - ECC double fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_DF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_DF_SHIFT)) & OTPC_SR_ECC_DF_MASK) + +#define OTPC_SR_TRI_F_MASK (0x10U) +#define OTPC_SR_TRI_F_SHIFT (4U) +/*! TRI_F - Triple voting fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_TRI_F(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_TRI_F_SHIFT)) & OTPC_SR_TRI_F_MASK) + +#define OTPC_SR_RD_FUSE_LOCK_MASK (0x100U) +#define OTPC_SR_RD_FUSE_LOCK_SHIFT (8U) +/*! RD_FUSE_LOCK - Read fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_FUSE_LOCK_SHIFT)) & OTPC_SR_RD_FUSE_LOCK_MASK) + +#define OTPC_SR_WR_FUSE_LOCK_MASK (0x200U) +#define OTPC_SR_WR_FUSE_LOCK_SHIFT (9U) +/*! WR_FUSE_LOCK - Write fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_FUSE_LOCK_SHIFT)) & OTPC_SR_WR_FUSE_LOCK_MASK) + +#define OTPC_SR_RD_REG_LOCK_MASK (0x400U) +#define OTPC_SR_RD_REG_LOCK_SHIFT (10U) +/*! RD_REG_LOCK - Read register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_REG_LOCK_SHIFT)) & OTPC_SR_RD_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_LOCK_MASK (0x800U) +#define OTPC_SR_WR_REG_LOCK_SHIFT (11U) +/*! WR_REG_LOCK - Write register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_LOCK_SHIFT)) & OTPC_SR_WR_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_BUSY_MASK (0x1000U) +#define OTPC_SR_WR_REG_BUSY_SHIFT (12U) +/*! WR_REG_BUSY - Write register when busy error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_BUSY_SHIFT)) & OTPC_SR_WR_REG_BUSY_MASK) + +#define OTPC_SR_WR_POWER_OFF_MASK (0x2000U) +#define OTPC_SR_WR_POWER_OFF_SHIFT (13U) +/*! WR_POWER_OFF - Write when power off error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_POWER_OFF_SHIFT)) & OTPC_SR_WR_POWER_OFF_MASK) + +#define OTPC_SR_FSM_MASK (0x10000U) +#define OTPC_SR_FSM_SHIFT (16U) +/*! FSM - Finite-state machine error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSM_SHIFT)) & OTPC_SR_FSM_MASK) + +#define OTPC_SR_FLC_MASK (0x20000U) +#define OTPC_SR_FLC_SHIFT (17U) +/*! FLC - Fuse load counter error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FLC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FLC_SHIFT)) & OTPC_SR_FLC_MASK) + +#define OTPC_SR_ADC_MASK (0x40000U) +#define OTPC_SR_ADC_SHIFT (18U) +/*! ADC - Address and data compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ADC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ADC_SHIFT)) & OTPC_SR_ADC_MASK) + +#define OTPC_SR_IRC_MASK (0x80000U) +#define OTPC_SR_IRC_SHIFT (19U) +/*! IRC - Inverted register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_IRC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_IRC_SHIFT)) & OTPC_SR_IRC_MASK) + +#define OTPC_SR_FSC_MASK (0x100000U) +#define OTPC_SR_FSC_SHIFT (20U) +/*! FSC - Fuse and shadow register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSC_SHIFT)) & OTPC_SR_FSC_MASK) +/*! @} */ + +/*! @name RWC - Read and Write Control */ +/*! @{ */ + +#define OTPC_RWC_ADDR_MASK (0x7FU) +#define OTPC_RWC_ADDR_SHIFT (0U) +/*! ADDR - EFUSE address */ +#define OTPC_RWC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_ADDR_SHIFT)) & OTPC_RWC_ADDR_MASK) + +#define OTPC_RWC_WR_ALL1S_MASK (0x1000U) +#define OTPC_RWC_WR_ALL1S_SHIFT (12U) +/*! WR_ALL1S - Write all 1s + * 0b0..Uses the WDATA value + * 0b1..Writes all 1s + */ +#define OTPC_RWC_WR_ALL1S(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK) + +#define OTPC_RWC_READ_EFUSE_MASK (0x2000U) +#define OTPC_RWC_READ_EFUSE_SHIFT (13U) +/*! READ_EFUSE - Read EFUSE + * 0b0..Starts program operation when the WR_UNLOCK value is 0x9527; otherwise, takes no action. + * 0b1..Starts read operation + */ +#define OTPC_RWC_READ_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_EFUSE_SHIFT)) & OTPC_RWC_READ_EFUSE_MASK) + +#define OTPC_RWC_READ_UPDATE_MASK (0x4000U) +#define OTPC_RWC_READ_UPDATE_SHIFT (14U) +/*! READ_UPDATE - Read update + * 0b0..Shadow register does not update + * 0b1..Shadow register updates + */ +#define OTPC_RWC_READ_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_UPDATE_SHIFT)) & OTPC_RWC_READ_UPDATE_MASK) + +#define OTPC_RWC_WR_UNLOCK_MASK (0xFFFF0000U) +#define OTPC_RWC_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write Unlock */ +#define OTPC_RWC_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_UNLOCK_SHIFT)) & OTPC_RWC_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name RLC - Reload Control */ +/*! @{ */ + +#define OTPC_RLC_RELOAD_SHADOWS_MASK (0x1U) +#define OTPC_RLC_RELOAD_SHADOWS_SHIFT (0U) +/*! RELOAD_SHADOWS - Reload shadow registers + * 0b0..No action (when writing) or reload complete (when reading) + * 0b1..Reload + */ +#define OTPC_RLC_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RLC_RELOAD_SHADOWS_SHIFT)) & OTPC_RLC_RELOAD_SHADOWS_MASK) +/*! @} */ + +/*! @name PCR - Power Control */ +/*! @{ */ + +#define OTPC_PCR_HVREQ_MASK (0x1U) +#define OTPC_PCR_HVREQ_SHIFT (0U) +/*! HVREQ - Strong switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_HVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_HVREQ_SHIFT)) & OTPC_PCR_HVREQ_MASK) + +#define OTPC_PCR_LVREQ_MASK (0x2U) +#define OTPC_PCR_LVREQ_SHIFT (1U) +/*! LVREQ - Weak switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_LVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_LVREQ_SHIFT)) & OTPC_PCR_LVREQ_MASK) + +#define OTPC_PCR_PDREQ_MASK (0x4U) +#define OTPC_PCR_PDREQ_SHIFT (2U) +/*! PDREQ - Power down request + * 0b0..PD pin is set to low when OTPC is in idle state. It means EFUSE hardmacro is in standby mode. Idle state + * means OTPC is not in read and program modes. + * 0b1..PD pin is set to high when OTPC is in idle state. It means EFUSE hardmacro is in power down mode. + */ +#define OTPC_PCR_PDREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_PDREQ_SHIFT)) & OTPC_PCR_PDREQ_MASK) +/*! @} */ + +/*! @name WDATA - Write Data */ +/*! @{ */ + +#define OTPC_WDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_WDATA_DAT_SHIFT (0U) +/*! DAT - Write data */ +#define OTPC_WDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_WDATA_DAT_SHIFT)) & OTPC_WDATA_DAT_MASK) +/*! @} */ + +/*! @name RDATA - Read Data */ +/*! @{ */ + +#define OTPC_RDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_RDATA_DAT_SHIFT (0U) +/*! DAT - Read data */ +#define OTPC_RDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RDATA_DAT_SHIFT)) & OTPC_RDATA_DAT_MASK) +/*! @} */ + +/*! @name TIMING1 - Timing1 */ +/*! @{ */ + +#define OTPC_TIMING1_TADDR_MASK (0xFU) +#define OTPC_TIMING1_TADDR_SHIFT (0U) +/*! TADDR - Address to STROBE setup and hold time */ +#define OTPC_TIMING1_TADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TADDR_SHIFT)) & OTPC_TIMING1_TADDR_MASK) + +#define OTPC_TIMING1_TRELAX_MASK (0xF0U) +#define OTPC_TIMING1_TRELAX_SHIFT (4U) +/*! TRELAX - CSB, PGENB and LOAD to STROBE setup and hold time */ +#define OTPC_TIMING1_TRELAX(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRELAX_SHIFT)) & OTPC_TIMING1_TRELAX_MASK) + +#define OTPC_TIMING1_TRD_MASK (0x3F00U) +#define OTPC_TIMING1_TRD_SHIFT (8U) +/*! TRD - Read strobe pulse width time */ +#define OTPC_TIMING1_TRD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRD_SHIFT)) & OTPC_TIMING1_TRD_MASK) + +#define OTPC_TIMING1_TPS_MASK (0x3F0000U) +#define OTPC_TIMING1_TPS_SHIFT (16U) +/*! TPS - PS to CSB setup and hold time between power switch and chip select assertion */ +#define OTPC_TIMING1_TPS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPS_SHIFT)) & OTPC_TIMING1_TPS_MASK) + +#define OTPC_TIMING1_TPD_MASK (0xFF000000U) +#define OTPC_TIMING1_TPD_SHIFT (24U) +/*! TPD - PD to CSB setup time between power down signal deassertion and chip select signal assertion */ +#define OTPC_TIMING1_TPD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK) +/*! @} */ + +/*! @name TIMING2 - Timing2 */ +/*! @{ */ + +#define OTPC_TIMING2_TPGM_MASK (0xFFFU) +#define OTPC_TIMING2_TPGM_SHIFT (0U) +/*! TPGM - Typical program strobe pulse width time */ +#define OTPC_TIMING2_TPGM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING2_TPGM_SHIFT)) & OTPC_TIMING2_TPGM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define OTPC_LOCK_NXP_PART_CFG_LOCK_MASK (0x7U) +#define OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT (0U) +/*! NXP_PART_CFG_LOCK - NXP Part Config Lock */ +#define OTPC_LOCK_NXP_PART_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT)) & OTPC_LOCK_NXP_PART_CFG_LOCK_MASK) + +#define OTPC_LOCK_NXP_EXT_LOCK_MASK (0x38U) +#define OTPC_LOCK_NXP_EXT_LOCK_SHIFT (3U) +/*! NXP_EXT_LOCK - NXP EXT Lock */ +#define OTPC_LOCK_NXP_EXT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_EXT_LOCK_SHIFT)) & OTPC_LOCK_NXP_EXT_LOCK_MASK) + +#define OTPC_LOCK_BOOT_CFG_LOCK_MASK (0xE00U) +#define OTPC_LOCK_BOOT_CFG_LOCK_SHIFT (9U) +/*! BOOT_CFG_LOCK - Boot config Lock */ +#define OTPC_LOCK_BOOT_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_BOOT_CFG_LOCK_SHIFT)) & OTPC_LOCK_BOOT_CFG_LOCK_MASK) + +#define OTPC_LOCK_PRINCE_CFG_LOCK_MASK (0x7000U) +#define OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT (12U) +/*! PRINCE_CFG_LOCK - Prince Config Lock */ +#define OTPC_LOCK_PRINCE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT)) & OTPC_LOCK_PRINCE_CFG_LOCK_MASK) + +#define OTPC_LOCK_OSCAA_KEY_LOCK_MASK (0x38000U) +#define OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT (15U) +/*! OSCAA_KEY_LOCK - OSCAA Key Lock */ +#define OTPC_LOCK_OSCAA_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT)) & OTPC_LOCK_OSCAA_KEY_LOCK_MASK) + +#define OTPC_LOCK_CUST_LOCK0_MASK (0x1C0000U) +#define OTPC_LOCK_CUST_LOCK0_SHIFT (18U) +/*! CUST_LOCK0 - CUST Lock 0 */ +#define OTPC_LOCK_CUST_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK0_SHIFT)) & OTPC_LOCK_CUST_LOCK0_MASK) + +#define OTPC_LOCK_CUST_LOCK1_MASK (0xE00000U) +#define OTPC_LOCK_CUST_LOCK1_SHIFT (21U) +/*! CUST_LOCK1 - CUST Lock 1 */ +#define OTPC_LOCK_CUST_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK1_SHIFT)) & OTPC_LOCK_CUST_LOCK1_MASK) + +#define OTPC_LOCK_CUST_LOCK2_MASK (0x7000000U) +#define OTPC_LOCK_CUST_LOCK2_SHIFT (24U) +/*! CUST_LOCK2 - CUST Lock 2 */ +#define OTPC_LOCK_CUST_LOCK2(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK2_SHIFT)) & OTPC_LOCK_CUST_LOCK2_MASK) + +#define OTPC_LOCK_CUST_LOCK3_MASK (0x38000000U) +#define OTPC_LOCK_CUST_LOCK3_SHIFT (27U) +/*! CUST_LOCK3 - CUST Lock 3 */ +#define OTPC_LOCK_CUST_LOCK3(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK3_SHIFT)) & OTPC_LOCK_CUST_LOCK3_MASK) +/*! @} */ + +/*! @name SECURE - Secure */ +/*! @{ */ + +#define OTPC_SECURE_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_DAT_SHIFT)) & OTPC_SECURE_DAT_MASK) +/*! @} */ + +/*! @name SECURE_INV - Inverted Secure */ +/*! @{ */ + +#define OTPC_SECURE_INV_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_INV_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_INV_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_INV_DAT_SHIFT)) & OTPC_SECURE_INV_DAT_MASK) +/*! @} */ + +/*! @name DBG_KEY - Debug and Key */ +/*! @{ */ + +#define OTPC_DBG_KEY_DAT_MASK (0xFFFFFFFFU) +#define OTPC_DBG_KEY_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_DBG_KEY_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_DBG_KEY_DAT_SHIFT)) & OTPC_DBG_KEY_DAT_MASK) +/*! @} */ + +/*! @name MISC_CFG - MISC Config */ +/*! @{ */ + +#define OTPC_MISC_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_MISC_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_MISC_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_MISC_CFG_DAT_SHIFT)) & OTPC_MISC_CFG_DAT_MASK) +/*! @} */ + +/*! @name PHANTOM_CFG - PHANTOM Config */ +/*! @{ */ + +#define OTPC_PHANTOM_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_PHANTOM_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_PHANTOM_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PHANTOM_CFG_DAT_SHIFT)) & OTPC_PHANTOM_CFG_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG0 - Flexible Config 0 */ +/*! @{ */ + +#define OTPC_FLEX_CFG0_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG0_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG0_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG0_DAT_SHIFT)) & OTPC_FLEX_CFG0_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG1 - Flexible Config 1 */ +/*! @{ */ + +#define OTPC_FLEX_CFG1_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG1_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG1_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG1_DAT_SHIFT)) & OTPC_FLEX_CFG1_DAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OTPC_Register_Masks */ + + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/*! + * @} + */ /* end of group OTPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer + * @{ + */ + +/** PDM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ + __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ + __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ + __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __I uint32_t DATACH[4]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_2[48]; + __I uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ + __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ + uint8_t RESERVED_4[4]; + __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ + __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ + __I uint32_t VERID; /**< Version ID, offset: 0x84 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ +} PDM_Type; + +/* ---------------------------------------------------------------------------- + -- PDM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Register_Masks PDM Register Masks + * @{ + */ + +/*! @name CTRL_1 - MICFIL Control 1 */ +/*! @{ */ + +#define PDM_CTRL_1_CH0EN_MASK (0x1U) +#define PDM_CTRL_1_CH0EN_SHIFT (0U) +/*! CH0EN - Channel 0 Enable */ +#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + +#define PDM_CTRL_1_CH1EN_MASK (0x2U) +#define PDM_CTRL_1_CH1EN_SHIFT (1U) +/*! CH1EN - Channel 1 Enable */ +#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + +#define PDM_CTRL_1_CH2EN_MASK (0x4U) +#define PDM_CTRL_1_CH2EN_SHIFT (2U) +/*! CH2EN - Channel 2 Enable */ +#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + +#define PDM_CTRL_1_CH3EN_MASK (0x8U) +#define PDM_CTRL_1_CH3EN_SHIFT (3U) +/*! CH3EN - Channel 3 Enable */ +#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + +#define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) +#define PDM_CTRL_1_FSYNCEN_SHIFT (16U) +/*! FSYNCEN - Frame Synchronization Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) + +#define PDM_CTRL_1_DECFILS_MASK (0x100000U) +#define PDM_CTRL_1_DECFILS_SHIFT (20U) +/*! DECFILS - Decimation Filter Enable in Stop + * 0b0..Stops decimation filter + * 0b1..Keeps decimation filter running + */ +#define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) + +#define PDM_CTRL_1_ERREN_MASK (0x800000U) +#define PDM_CTRL_1_ERREN_SHIFT (23U) +/*! ERREN - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + +#define PDM_CTRL_1_DISEL_MASK (0x3000000U) +#define PDM_CTRL_1_DISEL_SHIFT (24U) +/*! DISEL - DMA Interrupt Selection + * 0b00..Disables DMA and interrupt requests + * 0b01..Enables DMA requests + * 0b10..Enables interrupt requests + * 0b11..Reserved + */ +#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + +#define PDM_CTRL_1_DBGE_MASK (0x4000000U) +#define PDM_CTRL_1_DBGE_SHIFT (26U) +/*! DBGE - Module Enable in Debug + * 0b0..Disables after completing the current frame + * 0b1..Enables operation + */ +#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + +#define PDM_CTRL_1_SRES_MASK (0x8000000U) +#define PDM_CTRL_1_SRES_SHIFT (27U) +/*! SRES - Software Reset + * 0b0..No action + * 0b1..Software reset + */ +#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + +#define PDM_CTRL_1_DBG_MASK (0x10000000U) +#define PDM_CTRL_1_DBG_SHIFT (28U) +/*! DBG - Debug Mode + * 0b0..Normal + * 0b1..Debug + */ +#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + +#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) +#define PDM_CTRL_1_PDMIEN_SHIFT (29U) +/*! PDMIEN - MICFIL Enable + * 0b0..Stops MICFIL operation + * 0b1..Starts MICFIL operation + */ +#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + +#define PDM_CTRL_1_DOZEN_MASK (0x40000000U) +#define PDM_CTRL_1_DOZEN_SHIFT (30U) +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + +#define PDM_CTRL_1_MDIS_MASK (0x80000000U) +#define PDM_CTRL_1_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Normal mode + * 0b1..DLL mode + */ +#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) +/*! @} */ + +/*! @name CTRL_2 - MICFIL Control 2 */ +/*! @{ */ + +#define PDM_CTRL_2_CLKDIV_MASK (0xFFU) +#define PDM_CTRL_2_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ +#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + +#define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) +#define PDM_CTRL_2_CLKDIVDIS_SHIFT (15U) +/*! CLKDIVDIS - Clock Divider Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_CTRL_2_CLKDIVDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK) + +#define PDM_CTRL_2_CICOSR_MASK (0xF0000U) +#define PDM_CTRL_2_CICOSR_SHIFT (16U) +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ +#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + +#define PDM_CTRL_2_QSEL_MASK (0xE000000U) +#define PDM_CTRL_2_QSEL_SHIFT (25U) +/*! QSEL - Quality Mode + * 0b001..High-Quality mode + * 0b000..Medium-Quality mode + * 0b111..Low-Quality mode + * 0b110..Very-Low-Quality 0 mode + * 0b101..Very-Low-Quality 1 mode + * 0b100..Very-Low-Quality 2 mode + */ +#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) +/*! @} */ + +/*! @name STAT - MICFIL Status */ +/*! @{ */ + +#define PDM_STAT_CH0F_MASK (0x1U) +#define PDM_STAT_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + +#define PDM_STAT_CH1F_MASK (0x2U) +#define PDM_STAT_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + +#define PDM_STAT_CH2F_MASK (0x4U) +#define PDM_STAT_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + +#define PDM_STAT_CH3F_MASK (0x8U) +#define PDM_STAT_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + +#define PDM_STAT_BSY_FIL_MASK (0x80000000U) +#define PDM_STAT_BSY_FIL_SHIFT (31U) +/*! BSY_FIL - Busy Flag + * 0b1..MICFIL is running + * 0b0..MICFIL is stopped + */ +#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) +/*! @} */ + +/*! @name FIFO_CTRL - MICFIL FIFO Control */ +/*! @{ */ + +#define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) +#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) +/*! FIFOWMK - FIFO Watermark Control */ +#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) +/*! @} */ + +/*! @name FIFO_STAT - MICFIL FIFO Status */ +/*! @{ */ + +#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) +#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) +/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + +#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) +#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) +/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + +#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) +#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) +/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + +#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) +#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) +/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + +#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) +#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) +/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + +#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) +#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) +/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + +#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) +#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) +/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + +#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) +#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) +/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) +/*! @} */ + +/*! @name DATACHN_DATACH - MICFIL Output Result */ +/*! @{ */ + +#define PDM_DATACHN_DATACH_DATA_MASK (0xFFFFFFFFU) +#define PDM_DATACHN_DATACH_DATA_SHIFT (0U) +/*! DATA - Channel n Data */ +#define PDM_DATACHN_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACHN_DATACH_DATA_SHIFT)) & PDM_DATACHN_DATACH_DATA_MASK) +/*! @} */ + +/* The count of PDM_DATACHN_DATACH */ +#define PDM_DATACHN_DATACH_COUNT (4U) + +/*! @name DC_CTRL - MICFIL DC Remover Control */ +/*! @{ */ + +#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ +/*! @{ */ + +#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name RANGE_CTRL - MICFIL Range Control */ +/*! @{ */ + +#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) +#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) +/*! RANGEADJ0 - Channel 0 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) +#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) +/*! RANGEADJ1 - Channel 1 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) +#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) +/*! RANGEADJ2 - Channel 2 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) +#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) +/*! RANGEADJ3 - Channel 3 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) +/*! @} */ + +/*! @name RANGE_STAT - MICFIL Range Status */ +/*! @{ */ + +#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) +#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) +/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + +#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) +#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) +/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + +#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) +#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) +/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + +#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) +#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) +/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + +#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) +#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) +/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + +#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) +#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) +/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + +#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) +#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) +/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + +#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) +#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) +/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) +/*! @} */ + +/*! @name FSYNC_CTRL - Frame Synchronization Control */ +/*! @{ */ + +#define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) +#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) +/*! FSYNCLEN - Frame Synchronization Window Length */ +#define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) +/*! @} */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PDM_VERID_FEATURE_MASK (0xFFFFU) +#define PDM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) + +#define PDM_VERID_MINOR_MASK (0xFF0000U) +#define PDM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) + +#define PDM_VERID_MAJOR_MASK (0xFF000000U) +#define PDM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define PDM_PARAM_NPAIR_MASK (0xFU) +#define PDM_PARAM_NPAIR_SHIFT (0U) +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ +#define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) + +#define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) +#define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ +#define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) + +#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) +#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) +/*! FIL_OUT_WIDTH_24B - Filter Output Width + * 0b0..16 bits + * 0b1..24 bits + */ +#define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) + +#define PDM_PARAM_LOW_POWER_MASK (0x200U) +#define PDM_PARAM_LOW_POWER_SHIFT (9U) +/*! LOW_POWER - Low-Power Decimation Filter + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) + +#define PDM_PARAM_DC_BYPASS_MASK (0x400U) +#define PDM_PARAM_DC_BYPASS_SHIFT (10U) +/*! DC_BYPASS - Input DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) + +#define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) +#define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) +/*! DC_OUT_BYPASS - Output DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PDM_Register_Masks */ + + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/*! + * @} + */ /* end of group PDM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */ + __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */ + __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ + __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern-Match Interrupt Control, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Interrupt mode + * 0b00000000..In bit n configures the interrupt to be edge-sensitive + * 0b00000001..In bit n configures the interrupt to be level-sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables Interrupt + * 0b00000000..In bit n disables the corresponding interrupt + * 0b00000001..In bit n enables the corresponding interrupt + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Configures IENR + * 0b00000000..No operation for interrupt n + * 0b00000001..Enable rising edge or level interrupt for interrupt n + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Clear bits in IENR + * 0b00000000..No operation + * 0b00000001..Disable rising edge or level interrupt + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables Interrupt + * 0b00000000..Disable (set active interrupt level LOW) + * 0b00000001..Enable (set active interrupt level HIGH) + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF + * 0b00000000..Writes 0 to IENF. + * 0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Writes 0 to IENF + * 0b00000000..No operation + * 0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin Interrupt Rising Edge */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising-Edge Detect + * 0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin Interrupt Falling Edge */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling-Edge Detect + * 0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin Interrupt Status */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin Interrupt Status + * 0b00000000..Read 0- Interrupt is not requested, Write 0- No operation + * 0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection + * for this pin, Write 1 (level-sensitive)- switch the active level for this pin in + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern-Match Interrupt Control */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function + * or by the pattern-match function. If this value is 0b, interrupts are driven in response to the + * standard pin interrupt function. If this value is 1b, interrupts are driven in response to + * pattern matches. + * 0b0..Pin interrupt + * 0b1..Pattern match + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified + * Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If + * this value is 1b, RXEV output to the CPU is enabled. + * 0b0..Disabled + * 0b1..Enabled + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - Pattern Matches + * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is + * the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is + * the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is + * the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is + * the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is + * the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is + * the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is + * the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } +/* Backward compatibility */ +#define PINT PINT0 + + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PKC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer + * @{ + */ + +/** PKC - Register Layout Typedef */ +typedef struct { + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ + __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ + __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ + __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ + __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ + __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ + __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ + __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ + __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ + __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ + uint8_t RESERVED_4[3916]; + __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ + uint8_t RESERVED_5[12]; + __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_6[16]; + __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ + __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ + __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ + __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_7[12]; + __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} PKC_Type; + +/* ---------------------------------------------------------------------------- + -- PKC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Register_Masks PKC Register Masks + * @{ + */ + +/*! @name PKC_STATUS - Status Register */ +/*! @{ */ + +#define PKC_PKC_STATUS_ACTIV_MASK (0x1U) +#define PKC_PKC_STATUS_ACTIV_SHIFT (0U) +/*! ACTIV - PKC ACTIV */ +#define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) + +#define PKC_PKC_STATUS_CARRY_MASK (0x2U) +#define PKC_PKC_STATUS_CARRY_SHIFT (1U) +/*! CARRY - Carry overflow flag */ +#define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) + +#define PKC_PKC_STATUS_ZERO_MASK (0x4U) +#define PKC_PKC_STATUS_ZERO_SHIFT (2U) +/*! ZERO - Zero result flag */ +#define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) + +#define PKC_PKC_STATUS_GOANY_MASK (0x8U) +#define PKC_PKC_STATUS_GOANY_SHIFT (3U) +/*! GOANY - Combined GO status flag */ +#define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) + +#define PKC_PKC_STATUS_LOCKED_MASK (0x60U) +#define PKC_PKC_STATUS_LOCKED_SHIFT (5U) +/*! LOCKED - Parameter set locked */ +#define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) +/*! @} */ + +/*! @name PKC_CTRL - Control Register */ +/*! @{ */ + +#define PKC_PKC_CTRL_RESET_MASK (0x1U) +#define PKC_PKC_CTRL_RESET_SHIFT (0U) +/*! RESET - PKC reset control bit */ +#define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) + +#define PKC_PKC_CTRL_STOP_MASK (0x2U) +#define PKC_PKC_CTRL_STOP_SHIFT (1U) +/*! STOP - Freeze PKC calculation */ +#define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) + +#define PKC_PKC_CTRL_GOD1_MASK (0x4U) +#define PKC_PKC_CTRL_GOD1_SHIFT (2U) +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ +#define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) + +#define PKC_PKC_CTRL_GOD2_MASK (0x8U) +#define PKC_PKC_CTRL_GOD2_SHIFT (3U) +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ +#define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) + +#define PKC_PKC_CTRL_GOM1_MASK (0x10U) +#define PKC_PKC_CTRL_GOM1_SHIFT (4U) +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ +#define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) + +#define PKC_PKC_CTRL_GOM2_MASK (0x20U) +#define PKC_PKC_CTRL_GOM2_SHIFT (5U) +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ +#define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) + +#define PKC_PKC_CTRL_GOU_MASK (0x40U) +#define PKC_PKC_CTRL_GOU_SHIFT (6U) +/*! GOU - Control bit to start pipe operation */ +#define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) + +#define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) +#define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) +/*! GF2CONV - Convert to GF2 calculation modes */ +#define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) + +#define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) +#define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) +/*! CLRCACHE - Clear universal pointer cache */ +#define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) + +#define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) +#define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) +/*! CACHE_EN - Enable universal pointer cache */ +#define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) + +#define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) +#define PKC_PKC_CTRL_REDMUL_SHIFT (10U) +/*! REDMUL - Reduced multiplier mode + * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b01..Reserved - Error Generated if selected + * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b11..Reserved - Error Generated if selected + */ +#define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) +/*! @} */ + +/*! @name PKC_CFG - Configuration register */ +/*! @{ */ + +#define PKC_PKC_CFG_IDLEOP_MASK (0x1U) +#define PKC_PKC_CFG_IDLEOP_SHIFT (0U) +#define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) + +#define PKC_PKC_CFG_RFU1_MASK (0x2U) +#define PKC_PKC_CFG_RFU1_SHIFT (1U) +#define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) + +#define PKC_PKC_CFG_RFU2_MASK (0x4U) +#define PKC_PKC_CFG_RFU2_SHIFT (2U) +#define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) + +#define PKC_PKC_CFG_CLKRND_MASK (0x8U) +#define PKC_PKC_CFG_CLKRND_SHIFT (3U) +#define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) + +#define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) +#define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) +#define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) + +#define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) +#define PKC_PKC_CFG_RNDDLY_SHIFT (5U) +#define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) + +#define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) +#define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) +#define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) + +#define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) +#define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) +#define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) + +#define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) +#define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) +#define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) +/*! @} */ + +/*! @name PKC_MODE1 - Mode register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_MODE1_MODE_MASK (0xFFU) +#define PKC_PKC_MODE1_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) + +#define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) + +#define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN1 - Length register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN1_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) + +#define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN1_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_MODE2 - Mode register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_MODE2_MODE_MASK (0xFFU) +#define PKC_PKC_MODE2_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) + +#define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) +/*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) + +#define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN2 - Length register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN2_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) + +#define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN2_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_UPTR - Universal pointer FUP program */ +/*! @{ */ + +#define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTR_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP program */ +#define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) +/*! @} */ + +/*! @name PKC_UPTRT - Universal pointer FUP table */ +/*! @{ */ + +#define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTRT_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP table */ +#define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) +/*! @} */ + +/*! @name PKC_ULEN - Universal pointer length */ +/*! @{ */ + +#define PKC_PKC_ULEN_LEN_MASK (0xFFU) +#define PKC_PKC_ULEN_LEN_SHIFT (0U) +/*! LEN - Length of universal pointer calculation */ +#define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) +/*! @} */ + +/*! @name PKC_MCDATA - MC pattern data interface */ +/*! @{ */ + +#define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) +#define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) +/*! MCDATA - Microcode read/write data */ +#define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) +/*! @} */ + +/*! @name PKC_VERSION - PKC version register */ +/*! @{ */ + +#define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) +#define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) +/*! MULSIZE + * 0b01..32-bit multiplier + * 0b10..64-bit multiplier + * 0b11..128-bit multiplier + * 0b10..128-bit multiplier + * 0b01..64-bit multiplier + */ +#define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) + +#define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) +#define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) +#define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) + +#define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) +#define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) +#define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) + +#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) +#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) +#define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) + +#define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) +#define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) +#define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) + +#define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) +#define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) +#define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) + +#define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) +#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) +#define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) +#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) +#define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) +#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) +#define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) +#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) +#define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) + +#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) +#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) +#define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) +/*! @} */ + +/*! @name PKC_SOFT_RST - Software reset */ +/*! @{ */ + +#define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) +#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) +#define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) +/*! APB_NOTAV - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) +/*! APB_WRGMD - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) + +#define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) +#define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) +/*! AHB - AHB Error */ +#define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) + +#define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) +#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) +#define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) + +#define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) +#define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) +#define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) + +#define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) +#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) +#define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) + +#define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) +#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) +#define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) +/*! INT_PDONE - End-of-computation status flag */ +#define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) +/*! EN_PDONE - PDONE interrupt enable flag */ +#define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_STATUS - Interrupt status set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_MODULE_ID - Module ID */ +/*! @{ */ + +#define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) +#define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) +#define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) + +#define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) +#define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) +#define PKC_PKC_MODULE_ID_ID_SHIFT (16U) +#define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PKC_Register_Masks */ + + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/*! + * @} + */ /* end of group PKC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[28]; + __I uint32_t EDFR; /**< EFT Detect Flag, offset: 0x40 */ + __IO uint32_t EDIER; /**< EFT Detect Interrupt Enable, offset: 0x44 */ + __IO uint32_t EDCR; /**< EFT Detect Clear, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + uint8_t RESERVED_4[24]; + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name EDFR - EFT Detect Flag */ +/*! @{ */ + +#define PORT_EDFR_EDF0_MASK (0x1U) +#define PORT_EDFR_EDF0_SHIFT (0U) +/*! EDF0 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK) + +#define PORT_EDFR_EDF1_MASK (0x2U) +#define PORT_EDFR_EDF1_SHIFT (1U) +/*! EDF1 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK) + +#define PORT_EDFR_EDF2_MASK (0x4U) +#define PORT_EDFR_EDF2_SHIFT (2U) +/*! EDF2 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK) + +#define PORT_EDFR_EDF3_MASK (0x8U) +#define PORT_EDFR_EDF3_SHIFT (3U) +/*! EDF3 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK) + +#define PORT_EDFR_EDF4_MASK (0x10U) +#define PORT_EDFR_EDF4_SHIFT (4U) +/*! EDF4 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK) + +#define PORT_EDFR_EDF5_MASK (0x20U) +#define PORT_EDFR_EDF5_SHIFT (5U) +/*! EDF5 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK) + +#define PORT_EDFR_EDF6_MASK (0x40U) +#define PORT_EDFR_EDF6_SHIFT (6U) +/*! EDF6 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK) + +#define PORT_EDFR_EDF7_MASK (0x80U) +#define PORT_EDFR_EDF7_SHIFT (7U) +/*! EDF7 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF7_SHIFT)) & PORT_EDFR_EDF7_MASK) + +#define PORT_EDFR_EDF8_MASK (0x100U) +#define PORT_EDFR_EDF8_SHIFT (8U) +/*! EDF8 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) + +#define PORT_EDFR_EDF9_MASK (0x200U) +#define PORT_EDFR_EDF9_SHIFT (9U) +/*! EDF9 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) + +#define PORT_EDFR_EDF10_MASK (0x400U) +#define PORT_EDFR_EDF10_SHIFT (10U) +/*! EDF10 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) + +#define PORT_EDFR_EDF11_MASK (0x800U) +#define PORT_EDFR_EDF11_SHIFT (11U) +/*! EDF11 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) + +#define PORT_EDFR_EDF12_MASK (0x1000U) +#define PORT_EDFR_EDF12_SHIFT (12U) +/*! EDF12 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) + +#define PORT_EDFR_EDF13_MASK (0x2000U) +#define PORT_EDFR_EDF13_SHIFT (13U) +/*! EDF13 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) + +#define PORT_EDFR_EDF14_MASK (0x4000U) +#define PORT_EDFR_EDF14_SHIFT (14U) +/*! EDF14 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) + +#define PORT_EDFR_EDF15_MASK (0x8000U) +#define PORT_EDFR_EDF15_SHIFT (15U) +/*! EDF15 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) + +#define PORT_EDFR_EDF16_MASK (0x10000U) +#define PORT_EDFR_EDF16_SHIFT (16U) +/*! EDF16 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) + +#define PORT_EDFR_EDF17_MASK (0x20000U) +#define PORT_EDFR_EDF17_SHIFT (17U) +/*! EDF17 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) + +#define PORT_EDFR_EDF18_MASK (0x40000U) +#define PORT_EDFR_EDF18_SHIFT (18U) +/*! EDF18 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) + +#define PORT_EDFR_EDF19_MASK (0x80000U) +#define PORT_EDFR_EDF19_SHIFT (19U) +/*! EDF19 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) + +#define PORT_EDFR_EDF20_MASK (0x100000U) +#define PORT_EDFR_EDF20_SHIFT (20U) +/*! EDF20 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) + +#define PORT_EDFR_EDF21_MASK (0x200000U) +#define PORT_EDFR_EDF21_SHIFT (21U) +/*! EDF21 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) + +#define PORT_EDFR_EDF22_MASK (0x400000U) +#define PORT_EDFR_EDF22_SHIFT (22U) +/*! EDF22 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) + +#define PORT_EDFR_EDF23_MASK (0x800000U) +#define PORT_EDFR_EDF23_SHIFT (23U) +/*! EDF23 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) + +#define PORT_EDFR_EDF24_MASK (0x1000000U) +#define PORT_EDFR_EDF24_SHIFT (24U) +/*! EDF24 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) + +#define PORT_EDFR_EDF25_MASK (0x2000000U) +#define PORT_EDFR_EDF25_SHIFT (25U) +/*! EDF25 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) + +#define PORT_EDFR_EDF26_MASK (0x4000000U) +#define PORT_EDFR_EDF26_SHIFT (26U) +/*! EDF26 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) + +#define PORT_EDFR_EDF27_MASK (0x8000000U) +#define PORT_EDFR_EDF27_SHIFT (27U) +/*! EDF27 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) + +#define PORT_EDFR_EDF28_MASK (0x10000000U) +#define PORT_EDFR_EDF28_SHIFT (28U) +/*! EDF28 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) + +#define PORT_EDFR_EDF29_MASK (0x20000000U) +#define PORT_EDFR_EDF29_SHIFT (29U) +/*! EDF29 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) + +#define PORT_EDFR_EDF30_MASK (0x40000000U) +#define PORT_EDFR_EDF30_SHIFT (30U) +/*! EDF30 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) + +#define PORT_EDFR_EDF31_MASK (0x80000000U) +#define PORT_EDFR_EDF31_SHIFT (31U) +/*! EDF31 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) +/*! @} */ + +/*! @name EDIER - EFT Detect Interrupt Enable */ +/*! @{ */ + +#define PORT_EDIER_EDIE0_MASK (0x1U) +#define PORT_EDIER_EDIE0_SHIFT (0U) +/*! EDIE0 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK) + +#define PORT_EDIER_EDIE1_MASK (0x2U) +#define PORT_EDIER_EDIE1_SHIFT (1U) +/*! EDIE1 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK) + +#define PORT_EDIER_EDIE2_MASK (0x4U) +#define PORT_EDIER_EDIE2_SHIFT (2U) +/*! EDIE2 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK) + +#define PORT_EDIER_EDIE3_MASK (0x8U) +#define PORT_EDIER_EDIE3_SHIFT (3U) +/*! EDIE3 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK) + +#define PORT_EDIER_EDIE4_MASK (0x10U) +#define PORT_EDIER_EDIE4_SHIFT (4U) +/*! EDIE4 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK) + +#define PORT_EDIER_EDIE5_MASK (0x20U) +#define PORT_EDIER_EDIE5_SHIFT (5U) +/*! EDIE5 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK) + +#define PORT_EDIER_EDIE6_MASK (0x40U) +#define PORT_EDIER_EDIE6_SHIFT (6U) +/*! EDIE6 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK) + +#define PORT_EDIER_EDIE7_MASK (0x80U) +#define PORT_EDIER_EDIE7_SHIFT (7U) +/*! EDIE7 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE7_SHIFT)) & PORT_EDIER_EDIE7_MASK) + +#define PORT_EDIER_EDIE8_MASK (0x100U) +#define PORT_EDIER_EDIE8_SHIFT (8U) +/*! EDIE8 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) + +#define PORT_EDIER_EDIE9_MASK (0x200U) +#define PORT_EDIER_EDIE9_SHIFT (9U) +/*! EDIE9 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) + +#define PORT_EDIER_EDIE10_MASK (0x400U) +#define PORT_EDIER_EDIE10_SHIFT (10U) +/*! EDIE10 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) + +#define PORT_EDIER_EDIE11_MASK (0x800U) +#define PORT_EDIER_EDIE11_SHIFT (11U) +/*! EDIE11 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) + +#define PORT_EDIER_EDIE12_MASK (0x1000U) +#define PORT_EDIER_EDIE12_SHIFT (12U) +/*! EDIE12 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) + +#define PORT_EDIER_EDIE13_MASK (0x2000U) +#define PORT_EDIER_EDIE13_SHIFT (13U) +/*! EDIE13 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) + +#define PORT_EDIER_EDIE14_MASK (0x4000U) +#define PORT_EDIER_EDIE14_SHIFT (14U) +/*! EDIE14 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) + +#define PORT_EDIER_EDIE15_MASK (0x8000U) +#define PORT_EDIER_EDIE15_SHIFT (15U) +/*! EDIE15 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) + +#define PORT_EDIER_EDIE16_MASK (0x10000U) +#define PORT_EDIER_EDIE16_SHIFT (16U) +/*! EDIE16 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) + +#define PORT_EDIER_EDIE17_MASK (0x20000U) +#define PORT_EDIER_EDIE17_SHIFT (17U) +/*! EDIE17 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) + +#define PORT_EDIER_EDIE18_MASK (0x40000U) +#define PORT_EDIER_EDIE18_SHIFT (18U) +/*! EDIE18 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) + +#define PORT_EDIER_EDIE19_MASK (0x80000U) +#define PORT_EDIER_EDIE19_SHIFT (19U) +/*! EDIE19 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) + +#define PORT_EDIER_EDIE20_MASK (0x100000U) +#define PORT_EDIER_EDIE20_SHIFT (20U) +/*! EDIE20 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) + +#define PORT_EDIER_EDIE21_MASK (0x200000U) +#define PORT_EDIER_EDIE21_SHIFT (21U) +/*! EDIE21 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) + +#define PORT_EDIER_EDIE22_MASK (0x400000U) +#define PORT_EDIER_EDIE22_SHIFT (22U) +/*! EDIE22 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) + +#define PORT_EDIER_EDIE23_MASK (0x800000U) +#define PORT_EDIER_EDIE23_SHIFT (23U) +/*! EDIE23 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) + +#define PORT_EDIER_EDIE24_MASK (0x1000000U) +#define PORT_EDIER_EDIE24_SHIFT (24U) +/*! EDIE24 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) + +#define PORT_EDIER_EDIE25_MASK (0x2000000U) +#define PORT_EDIER_EDIE25_SHIFT (25U) +/*! EDIE25 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) + +#define PORT_EDIER_EDIE26_MASK (0x4000000U) +#define PORT_EDIER_EDIE26_SHIFT (26U) +/*! EDIE26 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) + +#define PORT_EDIER_EDIE27_MASK (0x8000000U) +#define PORT_EDIER_EDIE27_SHIFT (27U) +/*! EDIE27 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) + +#define PORT_EDIER_EDIE28_MASK (0x10000000U) +#define PORT_EDIER_EDIE28_SHIFT (28U) +/*! EDIE28 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) + +#define PORT_EDIER_EDIE29_MASK (0x20000000U) +#define PORT_EDIER_EDIE29_SHIFT (29U) +/*! EDIE29 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) + +#define PORT_EDIER_EDIE30_MASK (0x40000000U) +#define PORT_EDIER_EDIE30_SHIFT (30U) +/*! EDIE30 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) + +#define PORT_EDIER_EDIE31_MASK (0x80000000U) +#define PORT_EDIER_EDIE31_SHIFT (31U) +/*! EDIE31 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) +/*! @} */ + +/*! @name EDCR - EFT Detect Clear */ +/*! @{ */ + +#define PORT_EDCR_EDHC_MASK (0x1U) +#define PORT_EDCR_EDHC_SHIFT (0U) +/*! EDHC - EFT Detect High Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDHC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK) + +#define PORT_EDCR_EDLC_MASK (0x2U) +#define PORT_EDCR_EDLC_SHIFT (1U) +/*! EDLC - EFT Detect Low Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDLC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + __I uint32_t AR; /**< Allow, offset: 0xC */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DATA_DEST; /**< Data Destination, offset: 0x20 */ + __IO uint32_t DATA_SRC; /**< Data Source, offset: 0x24 */ + uint8_t RESERVED_1[120]; + __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ + uint8_t RESERVED_2[4]; + __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ + uint8_t RESERVED_3[20]; + __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ + uint8_t RESERVED_5[8]; + __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ + __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ + __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ + uint8_t RESERVED_6[12]; + __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ + __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ + __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; + __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ + __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ + uint8_t RESERVED_8[208]; + __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ + __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ + __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ + __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ + __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ + __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define PUF_CR_ZEROIZE_MASK (0x1U) +#define PUF_CR_ZEROIZE_SHIFT (0U) +/*! ZEROIZE - Zeroize operation */ +#define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) + +#define PUF_CR_ENROLL_MASK (0x2U) +#define PUF_CR_ENROLL_SHIFT (1U) +/*! ENROLL - Enroll operation */ +#define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) + +#define PUF_CR_START_MASK (0x4U) +#define PUF_CR_START_SHIFT (2U) +/*! START - Start operation */ +#define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) + +#define PUF_CR_RECONSTRUCT_MASK (0x8U) +#define PUF_CR_RECONSTRUCT_SHIFT (3U) +/*! RECONSTRUCT - Reconstruct operation */ +#define PUF_CR_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK) + +#define PUF_CR_STOP_MASK (0x20U) +#define PUF_CR_STOP_SHIFT (5U) +/*! STOP - Stop operation */ +#define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) + +#define PUF_CR_GET_KEY_MASK (0x40U) +#define PUF_CR_GET_KEY_SHIFT (6U) +/*! GET_KEY - Get Key operation */ +#define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) + +#define PUF_CR_UNWRAP_MASK (0x80U) +#define PUF_CR_UNWRAP_SHIFT (7U) +/*! UNWRAP - Unwrap operation */ +#define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) + +#define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation */ +#define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_CR_WRAP_MASK (0x200U) +#define PUF_CR_WRAP_SHIFT (9U) +/*! WRAP - Wrap operation */ +#define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) + +#define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_CR_GENERATE_RANDOM_SHIFT (15U) +/*! GENERATE_RANDOM - Generate Random operation */ +#define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) + +#define PUF_CR_TEST_MEMORY_MASK (0x40000000U) +#define PUF_CR_TEST_MEMORY_SHIFT (30U) +/*! TEST_MEMORY - Test memory operation */ +#define PUF_CR_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK) + +#define PUF_CR_TEST_PUF_MASK (0x80000000U) +#define PUF_CR_TEST_PUF_SHIFT (31U) +/*! TEST_PUF - Test PUF operation */ +#define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) +/*! @} */ + +/*! @name ORR - Operation Result */ +/*! @{ */ + +#define PUF_ORR_RESULT_CODE_MASK (0xFFU) +#define PUF_ORR_RESULT_CODE_SHIFT (0U) +/*! RESULT_CODE - Result code of last operation + * 0b00000000..Indicates that the last operation was successful or operation is in progress. + * 0b11110000..Indicates that the AC is not for the current product/version. + * 0b11110001..Indicates that the AC in the second phase is not for the current product/version. + * 0b11110010..Indicates that the AC is corrupted. + * 0b11110011..Indicates that the AC in the second phase is corrupted. + * 0b11110100..Indicates that the authentication of the provided AC failed. + * 0b11110101..Indicates that the authentication of the provided AC failed in the second phase. + * 0b11110110..Indicates that the SRAM PUF quality verification fails. + * 0b11110111..Indicates that the incorrect or unsupported context is provided. + * 0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state. + * 0b11111111..Indicates that the PUF SRAM access has failed. + */ +#define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) + +#define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) +#define PUF_ORR_LAST_OPERATION_SHIFT (24U) +/*! LAST_OPERATION - Last operation type + * 0b00000000..Indicates that the operation is in progress. + * 0b00000001..Indicates that the last operation was Enroll. + * 0b00000010..Indicates that the last operation was Start. + * 0b00000011..Indicates that the last operation was Reconstruct + * 0b00000101..Indicates that the last operation was Stop. + * 0b00000110..Indicates that the last operation was Get Key. + * 0b00000111..Indicates that the last operation was Unwrap. + * 0b00001000..Indicates that the last operation was Wrap Generated Random. + * 0b00001001..Indicates that the last operation was Wrap. + * 0b00001111..Indicates that the last operation was Generate Random. + * 0b00011110..Indicates that the last operation was Test Memory. + * 0b00011111..Indicates that the last operation was Test PUF. + * 0b00100000..Indicates that the last operation was Initialization. + * 0b00101111..Indicates that the last operation was Zeroize. + */ +#define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define PUF_SR_BUSY_MASK (0x1U) +#define PUF_SR_BUSY_SHIFT (0U) +/*! BUSY - Operation in progress */ +#define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) + +#define PUF_SR_OK_MASK (0x2U) +#define PUF_SR_OK_SHIFT (1U) +/*! OK - Last operation successful */ +#define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) + +#define PUF_SR_ERROR_MASK (0x4U) +#define PUF_SR_ERROR_SHIFT (2U) +/*! ERROR - Last operation failed */ +#define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) + +#define PUF_SR_ZEROIZED_MASK (0x8U) +#define PUF_SR_ZEROIZED_SHIFT (3U) +/*! ZEROIZED - Zeroized or Locked state */ +#define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) + +#define PUF_SR_REJECTED_MASK (0x10U) +#define PUF_SR_REJECTED_SHIFT (4U) +/*! REJECTED - Operation rejected */ +#define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) + +#define PUF_SR_DI_REQUEST_MASK (0x20U) +#define PUF_SR_DI_REQUEST_SHIFT (5U) +/*! DI_REQUEST - Indicates the request for data in transfer via the DIR register */ +#define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) + +#define PUF_SR_DO_REQUEST_MASK (0x40U) +#define PUF_SR_DO_REQUEST_SHIFT (6U) +/*! DO_REQUEST - Indicates the request for data out transfer via the DOR register */ +#define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) +/*! @} */ + +/*! @name AR - Allow */ +/*! @{ */ + +#define PUF_AR_ALLOW_ENROLL_MASK (0x2U) +#define PUF_AR_ALLOW_ENROLL_SHIFT (1U) +/*! ALLOW_ENROLL - Enroll operation + * 0b0..Indicates that the Enroll operation is not allowed + * 0b1..Indicates that the Enroll operation is allowed + */ +#define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) + +#define PUF_AR_ALLOW_START_MASK (0x4U) +#define PUF_AR_ALLOW_START_SHIFT (2U) +/*! ALLOW_START - Start operation + * 0b0..Indicates that the Start operation is not allowed + * 0b1..Indicates that the Start operation is allowed + */ +#define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) + +#define PUF_AR_ALLOW_RECONSTRUCT_MASK (0x8U) +#define PUF_AR_ALLOW_RECONSTRUCT_SHIFT (3U) +/*! ALLOW_RECONSTRUCT - Reconstruct operation + * 0b0..Indicates that the Reconstruct operation is not allowed + * 0b1..Indicates that the Reconstruct operation is allowed + */ +#define PUF_AR_ALLOW_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK) + +#define PUF_AR_ALLOW_STOP_MASK (0x20U) +#define PUF_AR_ALLOW_STOP_SHIFT (5U) +/*! ALLOW_STOP - Stop operation + * 0b0..Indicates that the Stop operation is not allowed + * 0b1..Indicates that the Stop operation is allowed + */ +#define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) + +#define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) +#define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) +/*! ALLOW_GET_KEY - Get Key operation + * 0b0..Indicates that the Get Key operation is not allowed + * 0b1..Indicates that the Get Key operation is allowed + */ +#define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) + +#define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) +#define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) +/*! ALLOW_UNWRAP - Unwrap operation + * 0b0..Indicates that the Unwrap operation is not allowed + * 0b1..Indicates that the Unwrap operation is allowed + */ +#define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) + +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation + * 0b0..Indicates that the Wrap Generated Random operation is not allowed + * 0b1..Indicates that the Wrap Generated Random operation is allowed + */ +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_AR_ALLOW_WRAP_MASK (0x200U) +#define PUF_AR_ALLOW_WRAP_SHIFT (9U) +/*! ALLOW_WRAP - Wrap operation + * 0b0..Indicates that the Wrap operation is not allowed + * 0b1..Indicates that the Wrap operation is allowed + */ +#define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) + +#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) +/*! ALLOW_GENERATE_RANDOM - Generate Random operation + * 0b0..Indicates that the Generate Random operation is not allowed + * 0b1..Indicates that the Generate Random operation is allowed + */ +#define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) + +#define PUF_AR_ALLOW_TEST_MEMORY_MASK (0x40000000U) +#define PUF_AR_ALLOW_TEST_MEMORY_SHIFT (30U) +/*! ALLOW_TEST_MEMORY + * 0b0..Indicates that the Test Memory operation is not allowed + * 0b1..Indicates that the Test Memory operation is allowed + */ +#define PUF_AR_ALLOW_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK) + +#define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) +#define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) +/*! ALLOW_TEST_PUF - Test PUF operation + * 0b0..Test PUF operation is not allowed + * 0b1..Test PUF operation is allowed + */ +#define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define PUF_IER_INT_EN_MASK (0x1U) +#define PUF_IER_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt enable + * 0b0..Disables all PUF interrupts + * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register + */ +#define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define PUF_IMR_INT_EN_BUSY_MASK (0x1U) +#define PUF_IMR_INT_EN_BUSY_SHIFT (0U) +/*! INT_EN_BUSY - Busy interrupt */ +#define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) + +#define PUF_IMR_INT_EN_OK_MASK (0x2U) +#define PUF_IMR_INT_EN_OK_SHIFT (1U) +/*! INT_EN_OK - Ok interrupt */ +#define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) + +#define PUF_IMR_INT_EN_ERROR_MASK (0x4U) +#define PUF_IMR_INT_EN_ERROR_SHIFT (2U) +/*! INT_EN_ERROR - Error interrupt */ +#define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) + +#define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) +#define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) +/*! INT_EN_ZEROIZED - Zeroized interrupt */ +#define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) + +#define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) +#define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) +/*! INT_EN_REJECTED - Rejected interrupt */ +#define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) + +#define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) +#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) +/*! INT_EN_DI_REQUEST - Data in request interrupt */ +#define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) + +#define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) +#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) +/*! INT_EN_DO_REQUEST - Data out request interrupt */ +#define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define PUF_ISR_INT_BUSY_MASK (0x1U) +#define PUF_ISR_INT_BUSY_SHIFT (0U) +/*! INT_BUSY - Negative edge occurred on Busy */ +#define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) + +#define PUF_ISR_INT_OK_MASK (0x2U) +#define PUF_ISR_INT_OK_SHIFT (1U) +/*! INT_OK - Positive edge occurred on Ok */ +#define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) + +#define PUF_ISR_INT_ERROR_MASK (0x4U) +#define PUF_ISR_INT_ERROR_SHIFT (2U) +/*! INT_ERROR - Positive edge occurred on Error */ +#define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) + +#define PUF_ISR_INT_ZEROIZED_MASK (0x8U) +#define PUF_ISR_INT_ZEROIZED_SHIFT (3U) +/*! INT_ZEROIZED - Positive edge occurred on Zeroized */ +#define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) + +#define PUF_ISR_INT_REJECTED_MASK (0x10U) +#define PUF_ISR_INT_REJECTED_SHIFT (4U) +/*! INT_REJECTED - Positive edge occurred on Rejected */ +#define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) + +#define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) +#define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) +/*! INT_DI_REQUEST - Positive edge occurred on di_request */ +#define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) + +#define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) +#define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) +/*! INT_DO_REQUEST - Positive edge occurred on do_request */ +#define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) +/*! @} */ + +/*! @name DATA_DEST - Data Destination */ +/*! @{ */ + +#define PUF_DATA_DEST_DEST_DOR_MASK (0x1U) +#define PUF_DATA_DEST_DEST_DOR_SHIFT (0U) +/*! DEST_DOR - Key available via the DOR register */ +#define PUF_DATA_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK) + +#define PUF_DATA_DEST_DEST_SO_MASK (0x2U) +#define PUF_DATA_DEST_DEST_SO_SHIFT (1U) +/*! DEST_SO - Key available to ELS */ +#define PUF_DATA_DEST_DEST_SO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK) +/*! @} */ + +/*! @name DATA_SRC - Data Source */ +/*! @{ */ + +#define PUF_DATA_SRC_SRC_DIR_MASK (0x1U) +#define PUF_DATA_SRC_SRC_DIR_SHIFT (0U) +/*! SRC_DIR - Data provided via the DIR register */ +#define PUF_DATA_SRC_SRC_DIR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_DIR_SHIFT)) & PUF_DATA_SRC_SRC_DIR_MASK) + +#define PUF_DATA_SRC_SRC_SI_MASK (0x2U) +#define PUF_DATA_SRC_SRC_SI_SHIFT (1U) +/*! SRC_SI - Data provided via the SI interface */ +#define PUF_DATA_SRC_SRC_SI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_SI_SHIFT)) & PUF_DATA_SRC_SRC_SI_MASK) +/*! @} */ + +/*! @name DIR - Data Input */ +/*! @{ */ + +#define PUF_DIR_DI_MASK (0xFFFFFFFFU) +#define PUF_DIR_DI_SHIFT (0U) +/*! DI - Input data */ +#define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) +/*! @} */ + +/*! @name DOR - Data Output */ +/*! @{ */ + +#define PUF_DOR_DO_MASK (0xFFFFFFFFU) +#define PUF_DOR_DO_SHIFT (0U) +/*! DO - Output data */ +#define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) +/*! @} */ + +/*! @name MISC - Miscellaneous */ +/*! @{ */ + +#define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) +#define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) +/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: + * 0b0..Little endian + * 0b1..Big endian (default) + */ +#define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) +/*! @} */ + +/*! @name IF_SR - Interface Status */ +/*! @{ */ + +#define PUF_IF_SR_APB_ERROR_MASK (0x1U) +#define PUF_IF_SR_APB_ERROR_SHIFT (0U) +/*! APB_ERROR - APB error */ +#define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) +/*! @} */ + +/*! @name PSR - PUF Score */ +/*! @{ */ + +#define PUF_PSR_PUF_SCORE_MASK (0xFU) +#define PUF_PSR_PUF_SCORE_SHIFT (0U) +/*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */ +#define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) +/*! @} */ + +/*! @name HW_RUC0 - Hardware Restrict User Context 0 */ +/*! @{ */ + +#define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) +#define PUF_HW_RUC0_LC_STATE_SHIFT (0U) +/*! LC_STATE - Life cycle state based restrictions + * 0b00000011..OEM Develop + * 0b00000111..OEM Develop 2 + * 0b00001111..OEM In-field + * 0b00011111..OEM Field return + * 0b00111111..NXP Field Return/Failure Analysis + * 0b11001111..In-field Locked + * 0b11111111..Bricked + */ +#define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) + +#define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) +#define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) +/*! BOOT_STATE - Temporal boot state */ +#define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) + +#define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) +#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) +/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up */ +#define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) + +#define PUF_HW_RUC0_COOLFLUX_DEBUG_MASK (0x2000000U) +#define PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT (25U) +/*! COOLFLUX_DEBUG - Disable key access when debugger is attached to COOLFLUX after power-up */ +#define PUF_HW_RUC0_COOLFLUX_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT)) & PUF_HW_RUC0_COOLFLUX_DEBUG_MASK) + +#define PUF_HW_RUC0_dsp_debug_MASK (0x4000000U) +#define PUF_HW_RUC0_dsp_debug_SHIFT (26U) +/*! dsp_debug - DSP debug status. */ +#define PUF_HW_RUC0_dsp_debug(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_dsp_debug_SHIFT)) & PUF_HW_RUC0_dsp_debug_MASK) + +#define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) +#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) +/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level */ +#define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) +/*! @} */ + +/*! @name HW_RUC1 - Hardware Restrict User Context 1 */ +/*! @{ */ + +#define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) +#define PUF_HW_RUC1_APP_CTX_SHIFT (0U) +/*! APP_CTX - Application customizable context */ +#define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) +/*! @} */ + +/*! @name HW_INFO - Hardware Information */ +/*! @{ */ + +#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) +#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) +/*! CONFIG_WRAP - Wrap configuration + * 0b0..Indicates that Wrap is not included + * 0b1..Indicates that Wrap is included + */ +#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) + +#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) +#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) +/*! CONFIG_TYPE - PUF configuration + * 0b0001..Indicates that PUF configuration is Safe. + * 0b0010..Indicates that PUF configuration is Plus. + */ +#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) +/*! @} */ + +/*! @name HW_ID - Hardware Identifier */ +/*! @{ */ + +#define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) +#define PUF_HW_ID_HW_ID_SHIFT (0U) +/*! HW_ID - Provides the hardware identifier */ +#define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) +/*! @} */ + +/*! @name HW_VER - Hardware Version */ +/*! @{ */ + +#define PUF_HW_VER_HW_REV_MASK (0xFFU) +#define PUF_HW_VER_HW_REV_SHIFT (0U) +/*! HW_REV - Provides the hardware version, patch part */ +#define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) + +#define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) +#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) +/*! HW_VERSION_MINOR - Provides the hardware version, minor part */ +#define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) + +#define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) +#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) +/*! HW_VERSION_MAJOR - Provides the hardware version, major part */ +#define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Security level lock */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Security Level + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + +/*! @name SRAM_CFG - SRAM Configuration */ +/*! @{ */ + +#define PUF_SRAM_CFG_ENABLE_MASK (0x1U) +#define PUF_SRAM_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - PUF SRAM Controller activation + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) + +#define PUF_SRAM_CFG_CKGATING_MASK (0x4U) +#define PUF_SRAM_CFG_CKGATING_SHIFT (2U) +/*! CKGATING - PUF SRAM Clock Gating control + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) +/*! @} */ + +/*! @name SRAM_STATUS - Status */ +/*! @{ */ + +#define PUF_SRAM_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_STATUS_READY_SHIFT (0U) +/*! READY - PUF SRAM Controller State */ +#define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status */ +#define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) + +#define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status */ +#define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) +/*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status clear */ +#define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) + +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Clear + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status set */ +#define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) + +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Set + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_1[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ + __IO uint16_t CAPTFILTA; /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */ + __IO uint16_t CAPTFILTB; /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */ + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ + +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +/*! FRACVAL1 - Fractional Value 1 */ +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ + +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +/*! FRACVAL2 - Fractional Value 2 */ +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ + +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +/*! FRACVAL3 - Fractional Value 3 */ +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ + +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +/*! FRACVAL4 - Fractional Value 4 */ +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ + +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +/*! FRACVAL5 - Fractional Value 5 */ +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ + +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) + +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) + +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) + +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +/*! TEST - Test Status Bit */ +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +/*! CFB0 - Capture Flag B0 */ +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) + +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +/*! CFB1 - Capture Flag B1 */ +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) + +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +/*! CFA0 - Capture Flag A0 */ +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) + +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +/*! CFA1 - Capture Flag A1 */ +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) + +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) + +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) + +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1] + * 0b1..Interrupt request enabled for STS[CFA1] + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +/*! CB0DE - Capture B0 FIFO DMA Enable */ +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) + +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +/*! CB1DE - Capture B1 FIFO DMA Enable */ +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) + +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +/*! CA0DE - Capture A0 FIFO DMA Enable */ +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) + +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +/*! CA1DE - Capture A1 FIFO DMA Enable */ +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which + * watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ + +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) + +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) + +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) + +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) + +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) + +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) + +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +/*! CFAWM - Capture A FIFOs Water Mark */ +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) + +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +/*! CA0CNT - Capture A0 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) + +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +/*! CA1CNT - Capture A1 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ + +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +/*! EDGCMPA - Edge Compare A */ +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) + +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +/*! EDGCNTA - Edge Counter A */ +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ + +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) + +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) + +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) + +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) + +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) + +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) + +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +/*! CFBWM - Capture B FIFOs Water Mark */ +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) + +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +/*! CB0CNT - Capture B0 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) + +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +/*! CB1CNT - Capture B1 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ + +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +/*! EDGCMPB - Edge Compare B */ +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) + +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +/*! EDGCNTB - Edge Counter B */ +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ + +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +/*! CAPTVAL2 - Capture Value 2 */ +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +/*! CVAL2CYC - Capture Value 2 Cycle */ +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ + +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +/*! CAPTVAL3 - Capture Value 3 */ +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +/*! CVAL3CYC - Capture Value 3 Cycle */ +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ + +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +/*! CAPTVAL4 - Capture Value 4 */ +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +/*! CVAL4CYC - Capture Value 4 Cycle */ +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ + +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +/*! CAPTVAL5 - Capture Value 5 */ +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +/*! CVAL5CYC - Capture Value 5 Cycle */ +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTA - Capture PWM_A Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) +/*! CAPTA_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) + +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) +/*! CAPTA_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTA */ +#define PWM_CAPTFILTA_COUNT (4U) + +/*! @name CAPTFILTB - Capture PWM_B Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) +/*! CAPTB_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) + +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) +/*! CAPTB_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTB */ +#define PWM_CAPTFILTB_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. + * 0b11..PWM3_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer + * @{ + */ + +/** QDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ + __IO uint16_t TST; /**< Test, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ +} QDC_Type; + +/* ---------------------------------------------------------------------------- + -- QDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Register_Masks QDC Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define QDC_CTRL_CMPIE_MASK (0x1U) +#define QDC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) + +#define QDC_CTRL_CMPIRQ_MASK (0x2U) +#define QDC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) + +#define QDC_CTRL_WDE_MASK (0x4U) +#define QDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) + +#define QDC_CTRL_DIE_MASK (0x8U) +#define QDC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) + +#define QDC_CTRL_DIRQ_MASK (0x10U) +#define QDC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) + +#define QDC_CTRL_XNE_MASK (0x20U) +#define QDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive and Negative Edge of INDEX Pulse + * 0b0..Use positive edge + * 0b1..Use negative edge + */ +#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) + +#define QDC_CTRL_XIP_MASK (0x40U) +#define QDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..Does not initialize + * 0b1..Initializes + */ +#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) + +#define QDC_CTRL_XIE_MASK (0x80U) +#define QDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) + +#define QDC_CTRL_XIRQ_MASK (0x100U) +#define QDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) + +#define QDC_CTRL_PH1_MASK (0x200U) +#define QDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. + * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; + * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. + */ +#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) + +#define QDC_CTRL_REV_MASK (0x400U) +#define QDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Counts normally + * 0b1..Counts in the reverse direction + */ +#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) + +#define QDC_CTRL_SWIP_MASK (0x800U) +#define QDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) + +#define QDC_CTRL_HNE_MASK (0x1000U) +#define QDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) + +#define QDC_CTRL_HIP_MASK (0x2000U) +#define QDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) + +#define QDC_CTRL_HIE_MASK (0x4000U) +#define QDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) + +#define QDC_CTRL_HIRQ_MASK (0x8000U) +#define QDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter */ +/*! @{ */ + +#define QDC_FILT_FILT_PER_MASK (0xFFU) +#define QDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) + +#define QDC_FILT_FILT_CNT_MASK (0x700U) +#define QDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) + +#define QDC_FILT_FILT_PRSC_MASK (0xE000U) +#define QDC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ +#define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout */ +/*! @{ */ + +#define QDC_WTR_WDOG_MASK (0xFFFFU) +#define QDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter */ +/*! @{ */ + +#define QDC_POSD_POSD_MASK (0xFFFFU) +#define QDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold */ +/*! @{ */ + +#define QDC_POSDH_POSDH_MASK (0xFFFFU) +#define QDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter */ +/*! @{ */ + +#define QDC_REV_REV_MASK (0xFFFFU) +#define QDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold */ +/*! @{ */ + +#define QDC_REVH_REVH_MASK (0xFFFFU) +#define QDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter */ +/*! @{ */ + +#define QDC_UPOS_POS_MASK (0xFFFFU) +#define QDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter */ +/*! @{ */ + +#define QDC_LPOS_POS_MASK (0xFFFFU) +#define QDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold */ +/*! @{ */ + +#define QDC_UPOSH_POSH_MASK (0xFFFFU) +#define QDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold */ +/*! @{ */ + +#define QDC_LPOSH_POSH_MASK (0xFFFFU) +#define QDC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization */ +/*! @{ */ + +#define QDC_UINIT_INIT_MASK (0xFFFFU) +#define QDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization */ +/*! @{ */ + +#define QDC_LINIT_INIT_MASK (0xFFFFU) +#define QDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor */ +/*! @{ */ + +#define QDC_IMR_HOME_MASK (0x1U) +#define QDC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME */ +#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) + +#define QDC_IMR_INDEX_MASK (0x2U) +#define QDC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX */ +#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) + +#define QDC_IMR_PHB_MASK (0x4U) +#define QDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) + +#define QDC_IMR_PHA_MASK (0x8U) +#define QDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) + +#define QDC_IMR_FHOM_MASK (0x10U) +#define QDC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM */ +#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) + +#define QDC_IMR_FIND_MASK (0x20U) +#define QDC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND */ +#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) + +#define QDC_IMR_FPHB_MASK (0x40U) +#define QDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB */ +#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) + +#define QDC_IMR_FPHA_MASK (0x80U) +#define QDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA */ +#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test */ +/*! @{ */ + +#define QDC_TST_TEST_COUNT_MASK (0xFFU) +#define QDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) + +#define QDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define QDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) + +#define QDC_TST_QDN_MASK (0x2000U) +#define QDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Positive quadrature decoder signal + * 0b1..Negative quadrature decoder signal + */ +#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) + +#define QDC_TST_TCE_MASK (0x4000U) +#define QDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) + +#define QDC_TST_TEN_MASK (0x8000U) +#define QDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define QDC_CTRL2_UPDHLD_MASK (0x1U) +#define QDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) + +#define QDC_CTRL2_UPDPOS_MASK (0x2U) +#define QDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action + * 0b1..Clear + */ +#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) + +#define QDC_CTRL2_MOD_MASK (0x4U) +#define QDC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) + +#define QDC_CTRL2_DIR_MASK (0x8U) +#define QDC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Down direction + * 0b1..Up direction + */ +#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) + +#define QDC_CTRL2_RUIE_MASK (0x10U) +#define QDC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) + +#define QDC_CTRL2_RUIRQ_MASK (0x20U) +#define QDC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) + +#define QDC_CTRL2_ROIE_MASK (0x40U) +#define QDC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) + +#define QDC_CTRL2_ROIRQ_MASK (0x80U) +#define QDC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..Did not occur + * 0b1..Occurred + */ +#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) + +#define QDC_CTRL2_REVMOD_MASK (0x100U) +#define QDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse + * 0b1..Use modulus counting roll-over or roll-under + */ +#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) + +#define QDC_CTRL2_OUTCTL_MASK (0x200U) +#define QDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) + +#define QDC_CTRL2_SABIE_MASK (0x400U) +#define QDC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) + +#define QDC_CTRL2_SABIRQ_MASK (0x800U) +#define QDC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change has occurred + * 0b1..A simultaneous change has occurred + */ +#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) + +#define QDC_CTRL2_INITPOS_MASK (0x1000U) +#define QDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initialize Position Registers + * 0b0..Don't initialize position counter + * 0b1..Initialize position counter + */ +#define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) + +#define QDC_CTRL2_EMIP_MASK (0x2000U) +#define QDC_CTRL2_EMIP_SHIFT (13U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_EMIP_SHIFT)) & QDC_CTRL2_EMIP_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus */ +/*! @{ */ + +#define QDC_UMOD_MOD_MASK (0xFFFFU) +#define QDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus */ +/*! @{ */ + +#define QDC_LMOD_MOD_MASK (0xFFFFU) +#define QDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare */ +/*! @{ */ + +#define QDC_UCOMP_COMP_MASK (0xFFFFU) +#define QDC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare */ +/*! @{ */ + +#define QDC_LCOMP_COMP_MASK (0xFFFFU) +#define QDC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time */ +/*! @{ */ + +#define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold */ +/*! @{ */ + +#define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter */ +/*! @{ */ + +#define QDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define QDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer */ +/*! @{ */ + +#define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold */ +/*! @{ */ + +#define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define QDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 */ +/*! @{ */ + +#define QDC_CTRL3_PMEN_MASK (0x1U) +#define QDC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period Measurement Function Enable + * 0b0..Not used + * 0b1..Used + */ +#define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) + +#define QDC_CTRL3_PRSC_MASK (0xF0U) +#define QDC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler */ +#define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group QDC_Register_Masks */ + + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/*! + * @} + */ /* end of group QDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ + __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ + __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ + __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ + __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ + __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ + __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ + __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ + __IO uint16_t CTRL; /**< Control, offset: 0x10 */ + __IO uint16_t STATUS; /**< Status, offset: 0x12 */ + __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ + __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ + uint8_t RESERVED_0[4]; + __I uint16_t RTC_TEST2; /**< Sub Second Counter, offset: 0x1C */ + uint8_t RESERVED_1[4]; + __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ + __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ + __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ + __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ + uint8_t RESERVED_2[2006]; + __IO uint32_t SUBSECOND_CTRL; /**< Subsecond Control, offset: 0x800 */ + __I uint32_t SUBSECOND_CNT; /**< Subsecond Counter, offset: 0x804 */ + uint8_t RESERVED_3[1016]; + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0xC00 */ + uint8_t RESERVED_4[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC0C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name YEARMON - Year and Month Counters */ +/*! @{ */ + +#define RTC_YEARMON_MON_CNT_MASK (0xFU) +#define RTC_YEARMON_MON_CNT_SHIFT (0U) +/*! MON_CNT - Month Counter + * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value + * 0b0001..January + * 0b0010..February + * 0b0011..March + * 0b0100..April + * 0b0101..May + * 0b0110..June + * 0b0111..July + * 0b1000..August + * 0b1001..September + * 0b1010..October + * 0b1011..November + * 0b1100..December + */ +#define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) + +#define RTC_YEARMON_YROFST_MASK (0xFF00U) +#define RTC_YEARMON_YROFST_SHIFT (8U) +/*! YROFST - Year Offset Count Value */ +#define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) +/*! @} */ + +/*! @name DAYS - Days and Day-of-Week Counters */ +/*! @{ */ + +#define RTC_DAYS_DAY_CNT_MASK (0x1FU) +#define RTC_DAYS_DAY_CNT_SHIFT (0U) +/*! DAY_CNT - Days Counter Value */ +#define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) + +#define RTC_DAYS_DOW_MASK (0x700U) +#define RTC_DAYS_DOW_SHIFT (8U) +/*! DOW - Day of Week Counter Value + * 0b000..Sunday + * 0b001..Monday + * 0b010..Tuesday + * 0b011..Wednesday + * 0b100..Thursday + * 0b101..Friday + * 0b110..Saturday + * 0b111.. + */ +#define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) +/*! @} */ + +/*! @name HOURMIN - Hours and Minutes Counters */ +/*! @{ */ + +#define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) +#define RTC_HOURMIN_MIN_CNT_SHIFT (0U) +/*! MIN_CNT - Minutes Counter Value */ +#define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) + +#define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) +#define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) +/*! HOUR_CNT - Hours Counter Value */ +#define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) +/*! @} */ + +/*! @name SECONDS - Seconds Counters */ +/*! @{ */ + +#define RTC_SECONDS_SEC_CNT_MASK (0x3FU) +#define RTC_SECONDS_SEC_CNT_SHIFT (0U) +/*! SEC_CNT - Seconds Counter Value */ +#define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) +/*! @} */ + +/*! @name ALM_YEARMON - Year and Months Alarm */ +/*! @{ */ + +#define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) +#define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) +/*! ALM_MON - Months Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) + +#define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) +#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) +/*! ALM_YEAR - Year Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) +/*! @} */ + +/*! @name ALM_DAYS - Days Alarm */ +/*! @{ */ + +#define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) +#define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) +/*! ALM_DAY - Days Value for Alarm */ +#define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) +/*! @} */ + +/*! @name ALM_HOURMIN - Hours and Minutes Alarm */ +/*! @{ */ + +#define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) +#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) +/*! ALM_MIN - Minutes Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) + +#define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) +#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) +/*! ALM_HOUR - Hours Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) +/*! @} */ + +/*! @name ALM_SECONDS - Seconds Alarm */ +/*! @{ */ + +#define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) +#define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) +/*! ALM_SEC - Seconds Alarm Value */ +#define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) + +#define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) +#define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) +/*! DEC_SEC - Decrement Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) + +#define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) +#define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) +/*! INC_SEC - Increment Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define RTC_CTRL_FINEEN_MASK (0x1U) +#define RTC_CTRL_FINEEN_SHIFT (0U) +/*! FINEEN - Fine Compensation Enable + * 0b1..Fine compensation is enabled. + * 0b0..Fine compensation is disabled + */ +#define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) + +#define RTC_CTRL_COMP_EN_MASK (0x2U) +#define RTC_CTRL_COMP_EN_SHIFT (1U) +/*! COMP_EN - Compensation Enable + * 0b0..Coarse compensation is disabled. + * 0b1..Coarse compensation is enabled. + */ +#define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) + +#define RTC_CTRL_ALM_MATCH_MASK (0xCU) +#define RTC_CTRL_ALM_MATCH_SHIFT (2U) +/*! ALM_MATCH - Alarm Match + * 0b00..Only seconds, minutes, and hours matched. + * 0b01..Only seconds, minutes, hours, and days matched. + * 0b10..Only seconds, minutes, hours, days, and months matched. + * 0b11..Only seconds, minutes, hours, days, months, and year (offset) matched. + */ +#define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) + +#define RTC_CTRL_DST_EN_MASK (0x40U) +#define RTC_CTRL_DST_EN_SHIFT (6U) +/*! DST_EN - Daylight Saving Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) + +#define RTC_CTRL_SWR_MASK (0x100U) +#define RTC_CTRL_SWR_SHIFT (8U) +/*! SWR - Software Reset + * 0b0..Software Reset cleared + * 0b1..Software Reset asserted + */ +#define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) + +#define RTC_CTRL_CLK_SEL_MASK (0x200U) +#define RTC_CTRL_CLK_SEL_SHIFT (9U) +/*! CLK_SEL - RTC Clock Select + * 0b0..16.384 kHz clock is selected + * 0b1..32.768 kHz clock is selected + */ +#define RTC_CTRL_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLK_SEL_SHIFT)) & RTC_CTRL_CLK_SEL_MASK) + +#define RTC_CTRL_CLKO_DIS_MASK (0x400U) +#define RTC_CTRL_CLKO_DIS_SHIFT (10U) +/*! CLKO_DIS - Clock Output Disable + * 0b0..The selected clock is output to other peripherals. + * 0b1..The selected clock is not output to other peripherals. + */ +#define RTC_CTRL_CLKO_DIS(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK) + +#define RTC_CTRL_CLKOUT_MASK (0x6000U) +#define RTC_CTRL_CLKOUT_SHIFT (13U) +/*! CLKOUT - RTC Clock Output Selection + * 0b00..No output clock + * 0b01..Fine 1 Hz clock with both precise edges + * 0b10..32.768 or 16.384 kHz clock + * 0b11..Coarse 1 Hz clock with both precise edges + */ +#define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define RTC_STATUS_INVAL_BIT_MASK (0x1U) +#define RTC_STATUS_INVAL_BIT_SHIFT (0U) +/*! INVAL_BIT - Invalidate CPU Read/Write Access + * 0b0..Time and date counters can be read or written. Time and date is valid. + * 0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written. + */ +#define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) + +#define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) +#define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) +/*! WRITE_PROT_EN - Write Protect Enable Status + * 0b0..Registers are unlocked and can be accessed. + * 0b1..Registers are locked and in read-only mode. + */ +#define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) + +#define RTC_STATUS_CMP_INT_MASK (0x20U) +#define RTC_STATUS_CMP_INT_SHIFT (5U) +/*! CMP_INT - Compensation Interval */ +#define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) + +#define RTC_STATUS_WE_MASK (0xC0U) +#define RTC_STATUS_WE_SHIFT (6U) +/*! WE - Write Enable + * 0b10..Enable Write Protection - Registers are locked. + */ +#define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) + +#define RTC_STATUS_BUS_ERR_MASK (0x100U) +#define RTC_STATUS_BUS_ERR_SHIFT (8U) +/*! BUS_ERR - Bus Error + * 0b0..Read and write accesses are normal. + * 0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted. + */ +#define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) + +#define RTC_STATUS_CMP_DONE_MASK (0x800U) +#define RTC_STATUS_CMP_DONE_SHIFT (11U) +/*! CMP_DONE - Compensation Done + * 0b0..Compensation busy or not enabled + * 0b1..Compensation completed + */ +#define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define RTC_ISR_ALM_IS_MASK (0x4U) +#define RTC_ISR_ALM_IS_SHIFT (2U) +/*! ALM_IS - Alarm Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) + +#define RTC_ISR_DAY_IS_MASK (0x8U) +#define RTC_ISR_DAY_IS_SHIFT (3U) +/*! DAY_IS - Days Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) + +#define RTC_ISR_HOUR_IS_MASK (0x10U) +#define RTC_ISR_HOUR_IS_SHIFT (4U) +/*! HOUR_IS - Hours Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) + +#define RTC_ISR_MIN_IS_MASK (0x20U) +#define RTC_ISR_MIN_IS_SHIFT (5U) +/*! MIN_IS - Minutes Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) + +#define RTC_ISR_IS_1HZ_MASK (0x40U) +#define RTC_ISR_IS_1HZ_SHIFT (6U) +/*! IS_1HZ - 1 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) + +#define RTC_ISR_IS_2HZ_MASK (0x80U) +#define RTC_ISR_IS_2HZ_SHIFT (7U) +/*! IS_2HZ - 2 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) + +#define RTC_ISR_IS_4HZ_MASK (0x100U) +#define RTC_ISR_IS_4HZ_SHIFT (8U) +/*! IS_4HZ - 4 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) + +#define RTC_ISR_IS_8HZ_MASK (0x200U) +#define RTC_ISR_IS_8HZ_SHIFT (9U) +/*! IS_8HZ - 8 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) + +#define RTC_ISR_IS_16HZ_MASK (0x400U) +#define RTC_ISR_IS_16HZ_SHIFT (10U) +/*! IS_16HZ - 16 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) + +#define RTC_ISR_IS_32HZ_MASK (0x800U) +#define RTC_ISR_IS_32HZ_SHIFT (11U) +/*! IS_32HZ - 32 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) + +#define RTC_ISR_IS_64HZ_MASK (0x1000U) +#define RTC_ISR_IS_64HZ_SHIFT (12U) +/*! IS_64HZ - 64 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) + +#define RTC_ISR_IS_128HZ_MASK (0x2000U) +#define RTC_ISR_IS_128HZ_SHIFT (13U) +/*! IS_128HZ - 128 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) + +#define RTC_ISR_IS_256HZ_MASK (0x4000U) +#define RTC_ISR_IS_256HZ_SHIFT (14U) +/*! IS_256HZ - 256 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) + +#define RTC_ISR_IS_512HZ_MASK (0x8000U) +#define RTC_ISR_IS_512HZ_SHIFT (15U) +/*! IS_512HZ - 512 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_ALM_IE_MASK (0x4U) +#define RTC_IER_ALM_IE_SHIFT (2U) +/*! ALM_IE - Alarm Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) + +#define RTC_IER_DAY_IE_MASK (0x8U) +#define RTC_IER_DAY_IE_SHIFT (3U) +/*! DAY_IE - Days Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) + +#define RTC_IER_HOUR_IE_MASK (0x10U) +#define RTC_IER_HOUR_IE_SHIFT (4U) +/*! HOUR_IE - Hours Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) + +#define RTC_IER_MIN_IE_MASK (0x20U) +#define RTC_IER_MIN_IE_SHIFT (5U) +/*! MIN_IE - Minutes Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) + +#define RTC_IER_IE_1HZ_MASK (0x40U) +#define RTC_IER_IE_1HZ_SHIFT (6U) +/*! IE_1HZ - 1 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) + +#define RTC_IER_IE_2HZ_MASK (0x80U) +#define RTC_IER_IE_2HZ_SHIFT (7U) +/*! IE_2HZ - 2 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) + +#define RTC_IER_IE_4HZ_MASK (0x100U) +#define RTC_IER_IE_4HZ_SHIFT (8U) +/*! IE_4HZ - 4 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) + +#define RTC_IER_IE_8HZ_MASK (0x200U) +#define RTC_IER_IE_8HZ_SHIFT (9U) +/*! IE_8HZ - 8 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) + +#define RTC_IER_IE_16HZ_MASK (0x400U) +#define RTC_IER_IE_16HZ_SHIFT (10U) +/*! IE_16HZ - 16 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) + +#define RTC_IER_IE_32HZ_MASK (0x800U) +#define RTC_IER_IE_32HZ_SHIFT (11U) +/*! IE_32HZ - 32 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) + +#define RTC_IER_IE_64HZ_MASK (0x1000U) +#define RTC_IER_IE_64HZ_SHIFT (12U) +/*! IE_64HZ - 64 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) + +#define RTC_IER_IE_128HZ_MASK (0x2000U) +#define RTC_IER_IE_128HZ_SHIFT (13U) +/*! IE_128HZ - 128 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) + +#define RTC_IER_IE_256HZ_MASK (0x4000U) +#define RTC_IER_IE_256HZ_SHIFT (14U) +/*! IE_256HZ - 256 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) + +#define RTC_IER_IE_512HZ_MASK (0x8000U) +#define RTC_IER_IE_512HZ_SHIFT (15U) +/*! IE_512HZ - 512 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) +/*! @} */ + +/*! @name RTC_TEST2 - Sub Second Counter */ +/*! @{ */ + +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK (0xFFFFU) +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT (0U) +/*! SUB_SECOND_COUNT - Sub Second Counter Value */ +#define RTC_RTC_TEST2_SUB_SECOND_COUNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK) +/*! @} */ + +/*! @name DST_HOUR - Daylight Saving Hour */ +/*! @{ */ + +#define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) +#define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) +/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */ +#define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) + +#define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) +#define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) +/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */ +#define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) +/*! @} */ + +/*! @name DST_MONTH - Daylight Saving Month */ +/*! @{ */ + +#define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) +#define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) +/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */ +#define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) + +#define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) +#define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) +/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */ +#define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) +/*! @} */ + +/*! @name DST_DAY - Daylight Saving Day */ +/*! @{ */ + +#define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) +#define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) +/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */ +#define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) + +#define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) +#define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) +/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */ +#define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) +/*! @} */ + +/*! @name COMPEN - Compensation */ +/*! @{ */ + +#define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) +#define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) +/*! COMPEN_VAL - Compensation Value */ +#define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) +/*! @} */ + +/*! @name SUBSECOND_CTRL - Subsecond Control */ +/*! @{ */ + +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) +/*! SUB_SECOND_CNT_EN - Subsecond Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) +/*! @} */ + +/*! @name SUBSECOND_CNT - Subsecond Counter */ +/*! @{ */ + +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) +/*! SUBSECOND_CNT - Current Subsecond Counter Value */ +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Not timed out + * 0b1..Timed out + */ +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect + * 0b1..Clear the wake timer counter + */ +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +/* Backward compatibility for RTC */ +#define RTC RTC0 + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- S50 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Peripheral_Access_Layer S50 Peripheral Access Layer + * @{ + */ + +/** S50 - Register Layout Typedef */ +typedef struct { + __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ + __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ + __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ + __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ + __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ + __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ + __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ + __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ + __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ + __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ + __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ + __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ + __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ + __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ + __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ + __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ + __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ + __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ + __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ + uint8_t RESERVED_3[4]; + __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ + __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ + __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ + uint8_t RESERVED_4[212]; + __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ + __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ + __I uint32_t ELS_KS2; /**< Status Register, offset: 0x158 */ + __I uint32_t ELS_KS3; /**< Status Register, offset: 0x15C */ + __I uint32_t ELS_KS4; /**< Status Register, offset: 0x160 */ + __I uint32_t ELS_KS5; /**< Status Register, offset: 0x164 */ + __I uint32_t ELS_KS6; /**< Status Register, offset: 0x168 */ + __I uint32_t ELS_KS7; /**< Status Register, offset: 0x16C */ + __I uint32_t ELS_KS8; /**< Status Register, offset: 0x170 */ + __I uint32_t ELS_KS9; /**< Status Register, offset: 0x174 */ + __I uint32_t ELS_KS10; /**< Status Register, offset: 0x178 */ + __I uint32_t ELS_KS11; /**< Status Register, offset: 0x17C */ + __I uint32_t ELS_KS12; /**< Status Register, offset: 0x180 */ + __I uint32_t ELS_KS13; /**< Status Register, offset: 0x184 */ + __I uint32_t ELS_KS14; /**< Status Register, offset: 0x188 */ + __I uint32_t ELS_KS15; /**< Status Register, offset: 0x18C */ + __I uint32_t ELS_KS16; /**< Status Register, offset: 0x190 */ + __I uint32_t ELS_KS17; /**< Status Register, offset: 0x194 */ + __I uint32_t ELS_KS18; /**< Status Register, offset: 0x198 */ + __I uint32_t ELS_KS19; /**< Status Register, offset: 0x19C */ +} S50_Type; + +/* ---------------------------------------------------------------------------- + -- S50 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Register_Masks S50 Register Masks + * @{ + */ + +/*! @name ELS_STATUS - Status Register */ +/*! @{ */ + +#define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) +#define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) +/*! ELS_BUSY + * 0b1..Crypto sequence executing + * 0b0..Crypto sequence not executing + */ +#define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) +#define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) +/*! ELS_IRQ + * 0b1..Active interrupt + * 0b0..No active interrupt + */ +#define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) + +#define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) +#define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) +/*! ELS_ERR + * 0b1..Internal error detected + * 0b0..Internal error not detected + */ +#define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) + +#define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) +#define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) +/*! PRNG_RDY + * 0b0..Internal PRNG not ready + * 0b1..Internal PRNG ready + */ +#define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) + +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) +/*! ECDSA_VFY_STATUS + * 0b11..Invalid, Error + * 0b00..No verify run + * 0b01..Signature verify failed + * 0b10..Signature verify passed + */ +#define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) + +#define S50_ELS_STATUS_PPROT_MASK (0xC0U) +#define S50_ELS_STATUS_PPROT_SHIFT (6U) +/*! PPROT + * 0b10..Non-secure, non-privileged + * 0b11..Non-secure, privileged + * 0b00..Secure, non-privileged + * 0b01..Secure, privileged + */ +#define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) + +#define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) +/*! DRBG_ENT_LVL + * 0b10..HIGH, DRBG generates random numbers of high quality entropy + * 0b01..LOW, DRBG generates random numbers of low quality entropy + * 0b00..NONE + * 0b11..RFU, Reserved for Future Use + */ +#define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) + +#define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) +#define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) +/*! DTRNG_BUSY + * 0b1..Gathering entropy + * 0b0..Not gathering entropy + */ +#define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) +#define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) +/*! ELS_LOCKED + * 0b1..Locked by master + * 0b0..Not locked by master + */ +#define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) +/*! @} */ + +/*! @name ELS_CTRL - Control Register */ +/*! @{ */ + +#define S50_ELS_CTRL_ELS_EN_MASK (0x1U) +#define S50_ELS_CTRL_ELS_EN_SHIFT (0U) +/*! ELS_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) + +#define S50_ELS_CTRL_ELS_START_MASK (0x2U) +#define S50_ELS_CTRL_ELS_START_SHIFT (1U) +#define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) + +#define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) +#define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) +#define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) + +#define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) +#define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) +/*! ELS_CMD - ELS Command ID */ +#define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) + +#define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) +#define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) +/*! BYTE_ORDER + * 0b1..Big endian + * 0b0..Little endian + */ +#define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) +/*! @} */ + +/*! @name ELS_CMDCFG0 - Command Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) +#define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) +/*! @} */ + +/*! @name ELS_CFG - Configuration Register */ +/*! @{ */ + +#define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) +#define S50_ELS_CFG_ADCTRL_SHIFT (16U) +#define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) +/*! @} */ + +/*! @name ELS_KIDX0 - Keystore Index 0 */ +/*! @{ */ + +#define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) +#define S50_ELS_KIDX0_KIDX0_SHIFT (0U) +#define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) +/*! @} */ + +/*! @name ELS_KIDX1 - Keystore Index 1 */ +/*! @{ */ + +#define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) +#define S50_ELS_KIDX1_KIDX1_SHIFT (0U) +#define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) +/*! @} */ + +/*! @name ELS_KPROPIN - Key Properties Request */ +/*! @{ */ + +#define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) +#define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) +#define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0 - DMA Source 0 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) +#define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC1 - DMA Source 1 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) +#define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2 - DMA Source 2 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) +#define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0 - DMA Result 0 */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) +#define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) +/*! @} */ + +/*! @name ELS_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) +#define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN + * 0b0..Disables + * 0b1..Enables + */ +#define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) +#define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS - Error Status */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) +/*! BUS_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) + +#define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) +#define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) +/*! OPN_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) +#define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) +/*! ALG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) +#define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) +/*! ITG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) +#define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) +/*! FLT_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) + +#define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) +#define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) +/*! PRNG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) +#define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) +#define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) + +#define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) +/*! DTRNG_ERR + * 0b0..No error + * 0b1..TRNG error occurred + */ +#define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) +/*! ERR_CLR + * 0b1..Clears ELS error state + * 0b0..Exits ELS error state + */ +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name ELS_VERSION - Version Register */ +/*! @{ */ + +#define S50_ELS_VERSION_Z_MASK (0xFU) +#define S50_ELS_VERSION_Z_SHIFT (0U) +#define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) + +#define S50_ELS_VERSION_Y2_MASK (0xF0U) +#define S50_ELS_VERSION_Y2_SHIFT (4U) +#define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) + +#define S50_ELS_VERSION_Y1_MASK (0xF00U) +#define S50_ELS_VERSION_Y1_SHIFT (8U) +#define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) + +#define S50_ELS_VERSION_X_MASK (0xF000U) +#define S50_ELS_VERSION_X_SHIFT (12U) +#define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) + +#define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) +#define S50_ELS_VERSION_SW_Z_SHIFT (16U) +#define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) + +#define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) +#define S50_ELS_VERSION_SW_Y2_SHIFT (20U) +#define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) + +#define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) +#define S50_ELS_VERSION_SW_Y1_SHIFT (24U) +#define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) + +#define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) +#define S50_ELS_VERSION_SW_X_SHIFT (28U) +#define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) +/*! @} */ + +/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ +/*! @{ */ + +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC_CTRL - CRC Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) +/*! CMDCRC_RST + * 0b1..Resets the CRC command to its default value + * 0b0..No effect + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) +/*! CMDCRC_EN + * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. + * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC - Command CRC Value */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) +#define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) +/*! @} */ + +/*! @name ELS_SESSION_ID - Session ID */ +/*! @{ */ + +#define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) +#define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) +#define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) +/*! @} */ + +/*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ +/*! @{ */ + +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) +/*! @} */ + +/*! @name ELS_MASTER_ID - Master ID */ +/*! @{ */ + +#define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) +#define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) +#define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) +/*! @} */ + +/*! @name ELS_KIDX2 - Keystore Index 2 */ +/*! @{ */ + +#define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) +#define S50_ELS_KIDX2_KIDX2_SHIFT (0U) +#define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) +/*! @} */ + +/*! @name ELS_KS0 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS0_KS0_KSIZE_MASK (0x3U) +#define S50_ELS_KS0_KS0_KSIZE_SHIFT (0U) +/*! KS0_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS0_KS0_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KSIZE_SHIFT)) & S50_ELS_KS0_KS0_KSIZE_MASK) + +#define S50_ELS_KS0_KS0_KACT_MASK (0x20U) +#define S50_ELS_KS0_KS0_KACT_SHIFT (5U) +#define S50_ELS_KS0_KS0_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KACT_SHIFT)) & S50_ELS_KS0_KS0_KACT_MASK) + +#define S50_ELS_KS0_KS0_KBASE_MASK (0x40U) +#define S50_ELS_KS0_KS0_KBASE_SHIFT (6U) +#define S50_ELS_KS0_KS0_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KBASE_SHIFT)) & S50_ELS_KS0_KS0_KBASE_MASK) + +#define S50_ELS_KS0_KS0_FGP_MASK (0x80U) +#define S50_ELS_KS0_KS0_FGP_SHIFT (7U) +#define S50_ELS_KS0_KS0_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FGP_SHIFT)) & S50_ELS_KS0_KS0_FGP_MASK) + +#define S50_ELS_KS0_KS0_FRTN_MASK (0x100U) +#define S50_ELS_KS0_KS0_FRTN_SHIFT (8U) +#define S50_ELS_KS0_KS0_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FRTN_SHIFT)) & S50_ELS_KS0_KS0_FRTN_MASK) + +#define S50_ELS_KS0_KS0_FHWO_MASK (0x200U) +#define S50_ELS_KS0_KS0_FHWO_SHIFT (9U) +#define S50_ELS_KS0_KS0_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FHWO_SHIFT)) & S50_ELS_KS0_KS0_FHWO_MASK) + +#define S50_ELS_KS0_KS0_UKPUK_MASK (0x800U) +#define S50_ELS_KS0_KS0_UKPUK_SHIFT (11U) +#define S50_ELS_KS0_KS0_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKPUK_SHIFT)) & S50_ELS_KS0_KS0_UKPUK_MASK) + +#define S50_ELS_KS0_KS0_UTECDH_MASK (0x1000U) +#define S50_ELS_KS0_KS0_UTECDH_SHIFT (12U) +#define S50_ELS_KS0_KS0_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTECDH_SHIFT)) & S50_ELS_KS0_KS0_UTECDH_MASK) + +#define S50_ELS_KS0_KS0_UCMAC_MASK (0x2000U) +#define S50_ELS_KS0_KS0_UCMAC_SHIFT (13U) +#define S50_ELS_KS0_KS0_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCMAC_SHIFT)) & S50_ELS_KS0_KS0_UCMAC_MASK) + +#define S50_ELS_KS0_KS0_UKSK_MASK (0x4000U) +#define S50_ELS_KS0_KS0_UKSK_SHIFT (14U) +#define S50_ELS_KS0_KS0_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKSK_SHIFT)) & S50_ELS_KS0_KS0_UKSK_MASK) + +#define S50_ELS_KS0_KS0_URTF_MASK (0x8000U) +#define S50_ELS_KS0_KS0_URTF_SHIFT (15U) +#define S50_ELS_KS0_KS0_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_URTF_SHIFT)) & S50_ELS_KS0_KS0_URTF_MASK) + +#define S50_ELS_KS0_KS0_UCKDF_MASK (0x10000U) +#define S50_ELS_KS0_KS0_UCKDF_SHIFT (16U) +#define S50_ELS_KS0_KS0_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCKDF_SHIFT)) & S50_ELS_KS0_KS0_UCKDF_MASK) + +#define S50_ELS_KS0_KS0_UHKDF_MASK (0x20000U) +#define S50_ELS_KS0_KS0_UHKDF_SHIFT (17U) +#define S50_ELS_KS0_KS0_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHKDF_SHIFT)) & S50_ELS_KS0_KS0_UHKDF_MASK) + +#define S50_ELS_KS0_KS0_UECSG_MASK (0x40000U) +#define S50_ELS_KS0_KS0_UECSG_SHIFT (18U) +#define S50_ELS_KS0_KS0_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECSG_SHIFT)) & S50_ELS_KS0_KS0_UECSG_MASK) + +#define S50_ELS_KS0_KS0_UECDH_MASK (0x80000U) +#define S50_ELS_KS0_KS0_UECDH_SHIFT (19U) +#define S50_ELS_KS0_KS0_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECDH_SHIFT)) & S50_ELS_KS0_KS0_UECDH_MASK) + +#define S50_ELS_KS0_KS0_UAES_MASK (0x100000U) +#define S50_ELS_KS0_KS0_UAES_SHIFT (20U) +#define S50_ELS_KS0_KS0_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UAES_SHIFT)) & S50_ELS_KS0_KS0_UAES_MASK) + +#define S50_ELS_KS0_KS0_UHMAC_MASK (0x200000U) +#define S50_ELS_KS0_KS0_UHMAC_SHIFT (21U) +#define S50_ELS_KS0_KS0_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHMAC_SHIFT)) & S50_ELS_KS0_KS0_UHMAC_MASK) + +#define S50_ELS_KS0_KS0_UKWK_MASK (0x400000U) +#define S50_ELS_KS0_KS0_UKWK_SHIFT (22U) +#define S50_ELS_KS0_KS0_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKWK_SHIFT)) & S50_ELS_KS0_KS0_UKWK_MASK) + +#define S50_ELS_KS0_KS0_UKUOK_MASK (0x800000U) +#define S50_ELS_KS0_KS0_UKUOK_SHIFT (23U) +#define S50_ELS_KS0_KS0_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKUOK_SHIFT)) & S50_ELS_KS0_KS0_UKUOK_MASK) + +#define S50_ELS_KS0_KS0_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS0_KS0_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS0_KS0_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSPMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSPMS_MASK) + +#define S50_ELS_KS0_KS0_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS0_KS0_UTLSMS_SHIFT (25U) +#define S50_ELS_KS0_KS0_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSMS_MASK) + +#define S50_ELS_KS0_KS0_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS0_KS0_UKGSRC_SHIFT (26U) +#define S50_ELS_KS0_KS0_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKGSRC_SHIFT)) & S50_ELS_KS0_KS0_UKGSRC_MASK) + +#define S50_ELS_KS0_KS0_UHWO_MASK (0x8000000U) +#define S50_ELS_KS0_KS0_UHWO_SHIFT (27U) +#define S50_ELS_KS0_KS0_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHWO_SHIFT)) & S50_ELS_KS0_KS0_UHWO_MASK) + +#define S50_ELS_KS0_KS0_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS0_KS0_UWRPOK_SHIFT (28U) +#define S50_ELS_KS0_KS0_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UWRPOK_SHIFT)) & S50_ELS_KS0_KS0_UWRPOK_MASK) + +#define S50_ELS_KS0_KS0_UDUK_MASK (0x20000000U) +#define S50_ELS_KS0_KS0_UDUK_SHIFT (29U) +#define S50_ELS_KS0_KS0_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UDUK_SHIFT)) & S50_ELS_KS0_KS0_UDUK_MASK) + +#define S50_ELS_KS0_KS0_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS0_KS0_UPPROT_SHIFT (30U) +#define S50_ELS_KS0_KS0_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UPPROT_SHIFT)) & S50_ELS_KS0_KS0_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS1 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS1_KS1_KSIZE_MASK (0x3U) +#define S50_ELS_KS1_KS1_KSIZE_SHIFT (0U) +/*! KS1_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS1_KS1_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KSIZE_SHIFT)) & S50_ELS_KS1_KS1_KSIZE_MASK) + +#define S50_ELS_KS1_KS1_KACT_MASK (0x20U) +#define S50_ELS_KS1_KS1_KACT_SHIFT (5U) +#define S50_ELS_KS1_KS1_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KACT_SHIFT)) & S50_ELS_KS1_KS1_KACT_MASK) + +#define S50_ELS_KS1_KS1_KBASE_MASK (0x40U) +#define S50_ELS_KS1_KS1_KBASE_SHIFT (6U) +#define S50_ELS_KS1_KS1_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KBASE_SHIFT)) & S50_ELS_KS1_KS1_KBASE_MASK) + +#define S50_ELS_KS1_KS1_FGP_MASK (0x80U) +#define S50_ELS_KS1_KS1_FGP_SHIFT (7U) +#define S50_ELS_KS1_KS1_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FGP_SHIFT)) & S50_ELS_KS1_KS1_FGP_MASK) + +#define S50_ELS_KS1_KS1_FRTN_MASK (0x100U) +#define S50_ELS_KS1_KS1_FRTN_SHIFT (8U) +#define S50_ELS_KS1_KS1_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FRTN_SHIFT)) & S50_ELS_KS1_KS1_FRTN_MASK) + +#define S50_ELS_KS1_KS1_FHWO_MASK (0x200U) +#define S50_ELS_KS1_KS1_FHWO_SHIFT (9U) +#define S50_ELS_KS1_KS1_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FHWO_SHIFT)) & S50_ELS_KS1_KS1_FHWO_MASK) + +#define S50_ELS_KS1_KS1_UKPUK_MASK (0x800U) +#define S50_ELS_KS1_KS1_UKPUK_SHIFT (11U) +#define S50_ELS_KS1_KS1_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKPUK_SHIFT)) & S50_ELS_KS1_KS1_UKPUK_MASK) + +#define S50_ELS_KS1_KS1_UTECDH_MASK (0x1000U) +#define S50_ELS_KS1_KS1_UTECDH_SHIFT (12U) +#define S50_ELS_KS1_KS1_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTECDH_SHIFT)) & S50_ELS_KS1_KS1_UTECDH_MASK) + +#define S50_ELS_KS1_KS1_UCMAC_MASK (0x2000U) +#define S50_ELS_KS1_KS1_UCMAC_SHIFT (13U) +#define S50_ELS_KS1_KS1_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCMAC_SHIFT)) & S50_ELS_KS1_KS1_UCMAC_MASK) + +#define S50_ELS_KS1_KS1_UKSK_MASK (0x4000U) +#define S50_ELS_KS1_KS1_UKSK_SHIFT (14U) +#define S50_ELS_KS1_KS1_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKSK_SHIFT)) & S50_ELS_KS1_KS1_UKSK_MASK) + +#define S50_ELS_KS1_KS1_URTF_MASK (0x8000U) +#define S50_ELS_KS1_KS1_URTF_SHIFT (15U) +#define S50_ELS_KS1_KS1_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_URTF_SHIFT)) & S50_ELS_KS1_KS1_URTF_MASK) + +#define S50_ELS_KS1_KS1_UCKDF_MASK (0x10000U) +#define S50_ELS_KS1_KS1_UCKDF_SHIFT (16U) +#define S50_ELS_KS1_KS1_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCKDF_SHIFT)) & S50_ELS_KS1_KS1_UCKDF_MASK) + +#define S50_ELS_KS1_KS1_UHKDF_MASK (0x20000U) +#define S50_ELS_KS1_KS1_UHKDF_SHIFT (17U) +#define S50_ELS_KS1_KS1_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHKDF_SHIFT)) & S50_ELS_KS1_KS1_UHKDF_MASK) + +#define S50_ELS_KS1_KS1_UECSG_MASK (0x40000U) +#define S50_ELS_KS1_KS1_UECSG_SHIFT (18U) +#define S50_ELS_KS1_KS1_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECSG_SHIFT)) & S50_ELS_KS1_KS1_UECSG_MASK) + +#define S50_ELS_KS1_KS1_UECDH_MASK (0x80000U) +#define S50_ELS_KS1_KS1_UECDH_SHIFT (19U) +#define S50_ELS_KS1_KS1_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECDH_SHIFT)) & S50_ELS_KS1_KS1_UECDH_MASK) + +#define S50_ELS_KS1_KS1_UAES_MASK (0x100000U) +#define S50_ELS_KS1_KS1_UAES_SHIFT (20U) +#define S50_ELS_KS1_KS1_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UAES_SHIFT)) & S50_ELS_KS1_KS1_UAES_MASK) + +#define S50_ELS_KS1_KS1_UHMAC_MASK (0x200000U) +#define S50_ELS_KS1_KS1_UHMAC_SHIFT (21U) +#define S50_ELS_KS1_KS1_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHMAC_SHIFT)) & S50_ELS_KS1_KS1_UHMAC_MASK) + +#define S50_ELS_KS1_KS1_UKWK_MASK (0x400000U) +#define S50_ELS_KS1_KS1_UKWK_SHIFT (22U) +#define S50_ELS_KS1_KS1_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKWK_SHIFT)) & S50_ELS_KS1_KS1_UKWK_MASK) + +#define S50_ELS_KS1_KS1_UKUOK_MASK (0x800000U) +#define S50_ELS_KS1_KS1_UKUOK_SHIFT (23U) +#define S50_ELS_KS1_KS1_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKUOK_SHIFT)) & S50_ELS_KS1_KS1_UKUOK_MASK) + +#define S50_ELS_KS1_KS1_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS1_KS1_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS1_KS1_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSPMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSPMS_MASK) + +#define S50_ELS_KS1_KS1_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS1_KS1_UTLSMS_SHIFT (25U) +#define S50_ELS_KS1_KS1_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSMS_MASK) + +#define S50_ELS_KS1_KS1_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS1_KS1_UKGSRC_SHIFT (26U) +#define S50_ELS_KS1_KS1_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKGSRC_SHIFT)) & S50_ELS_KS1_KS1_UKGSRC_MASK) + +#define S50_ELS_KS1_KS1_UHWO_MASK (0x8000000U) +#define S50_ELS_KS1_KS1_UHWO_SHIFT (27U) +#define S50_ELS_KS1_KS1_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHWO_SHIFT)) & S50_ELS_KS1_KS1_UHWO_MASK) + +#define S50_ELS_KS1_KS1_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS1_KS1_UWRPOK_SHIFT (28U) +#define S50_ELS_KS1_KS1_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UWRPOK_SHIFT)) & S50_ELS_KS1_KS1_UWRPOK_MASK) + +#define S50_ELS_KS1_KS1_UDUK_MASK (0x20000000U) +#define S50_ELS_KS1_KS1_UDUK_SHIFT (29U) +#define S50_ELS_KS1_KS1_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UDUK_SHIFT)) & S50_ELS_KS1_KS1_UDUK_MASK) + +#define S50_ELS_KS1_KS1_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS1_KS1_UPPROT_SHIFT (30U) +#define S50_ELS_KS1_KS1_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UPPROT_SHIFT)) & S50_ELS_KS1_KS1_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS2 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS2_KS2_KSIZE_MASK (0x3U) +#define S50_ELS_KS2_KS2_KSIZE_SHIFT (0U) +/*! KS2_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS2_KS2_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KSIZE_SHIFT)) & S50_ELS_KS2_KS2_KSIZE_MASK) + +#define S50_ELS_KS2_KS2_KACT_MASK (0x20U) +#define S50_ELS_KS2_KS2_KACT_SHIFT (5U) +#define S50_ELS_KS2_KS2_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KACT_SHIFT)) & S50_ELS_KS2_KS2_KACT_MASK) + +#define S50_ELS_KS2_KS2_KBASE_MASK (0x40U) +#define S50_ELS_KS2_KS2_KBASE_SHIFT (6U) +#define S50_ELS_KS2_KS2_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KBASE_SHIFT)) & S50_ELS_KS2_KS2_KBASE_MASK) + +#define S50_ELS_KS2_KS2_FGP_MASK (0x80U) +#define S50_ELS_KS2_KS2_FGP_SHIFT (7U) +#define S50_ELS_KS2_KS2_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FGP_SHIFT)) & S50_ELS_KS2_KS2_FGP_MASK) + +#define S50_ELS_KS2_KS2_FRTN_MASK (0x100U) +#define S50_ELS_KS2_KS2_FRTN_SHIFT (8U) +#define S50_ELS_KS2_KS2_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FRTN_SHIFT)) & S50_ELS_KS2_KS2_FRTN_MASK) + +#define S50_ELS_KS2_KS2_FHWO_MASK (0x200U) +#define S50_ELS_KS2_KS2_FHWO_SHIFT (9U) +#define S50_ELS_KS2_KS2_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FHWO_SHIFT)) & S50_ELS_KS2_KS2_FHWO_MASK) + +#define S50_ELS_KS2_KS2_UKPUK_MASK (0x800U) +#define S50_ELS_KS2_KS2_UKPUK_SHIFT (11U) +#define S50_ELS_KS2_KS2_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKPUK_SHIFT)) & S50_ELS_KS2_KS2_UKPUK_MASK) + +#define S50_ELS_KS2_KS2_UTECDH_MASK (0x1000U) +#define S50_ELS_KS2_KS2_UTECDH_SHIFT (12U) +#define S50_ELS_KS2_KS2_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTECDH_SHIFT)) & S50_ELS_KS2_KS2_UTECDH_MASK) + +#define S50_ELS_KS2_KS2_UCMAC_MASK (0x2000U) +#define S50_ELS_KS2_KS2_UCMAC_SHIFT (13U) +#define S50_ELS_KS2_KS2_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCMAC_SHIFT)) & S50_ELS_KS2_KS2_UCMAC_MASK) + +#define S50_ELS_KS2_KS2_UKSK_MASK (0x4000U) +#define S50_ELS_KS2_KS2_UKSK_SHIFT (14U) +#define S50_ELS_KS2_KS2_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKSK_SHIFT)) & S50_ELS_KS2_KS2_UKSK_MASK) + +#define S50_ELS_KS2_KS2_URTF_MASK (0x8000U) +#define S50_ELS_KS2_KS2_URTF_SHIFT (15U) +#define S50_ELS_KS2_KS2_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_URTF_SHIFT)) & S50_ELS_KS2_KS2_URTF_MASK) + +#define S50_ELS_KS2_KS2_UCKDF_MASK (0x10000U) +#define S50_ELS_KS2_KS2_UCKDF_SHIFT (16U) +#define S50_ELS_KS2_KS2_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCKDF_SHIFT)) & S50_ELS_KS2_KS2_UCKDF_MASK) + +#define S50_ELS_KS2_KS2_UHKDF_MASK (0x20000U) +#define S50_ELS_KS2_KS2_UHKDF_SHIFT (17U) +#define S50_ELS_KS2_KS2_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHKDF_SHIFT)) & S50_ELS_KS2_KS2_UHKDF_MASK) + +#define S50_ELS_KS2_KS2_UECSG_MASK (0x40000U) +#define S50_ELS_KS2_KS2_UECSG_SHIFT (18U) +#define S50_ELS_KS2_KS2_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECSG_SHIFT)) & S50_ELS_KS2_KS2_UECSG_MASK) + +#define S50_ELS_KS2_KS2_UECDH_MASK (0x80000U) +#define S50_ELS_KS2_KS2_UECDH_SHIFT (19U) +#define S50_ELS_KS2_KS2_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECDH_SHIFT)) & S50_ELS_KS2_KS2_UECDH_MASK) + +#define S50_ELS_KS2_KS2_UAES_MASK (0x100000U) +#define S50_ELS_KS2_KS2_UAES_SHIFT (20U) +#define S50_ELS_KS2_KS2_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UAES_SHIFT)) & S50_ELS_KS2_KS2_UAES_MASK) + +#define S50_ELS_KS2_KS2_UHMAC_MASK (0x200000U) +#define S50_ELS_KS2_KS2_UHMAC_SHIFT (21U) +#define S50_ELS_KS2_KS2_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHMAC_SHIFT)) & S50_ELS_KS2_KS2_UHMAC_MASK) + +#define S50_ELS_KS2_KS2_UKWK_MASK (0x400000U) +#define S50_ELS_KS2_KS2_UKWK_SHIFT (22U) +#define S50_ELS_KS2_KS2_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKWK_SHIFT)) & S50_ELS_KS2_KS2_UKWK_MASK) + +#define S50_ELS_KS2_KS2_UKUOK_MASK (0x800000U) +#define S50_ELS_KS2_KS2_UKUOK_SHIFT (23U) +#define S50_ELS_KS2_KS2_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKUOK_SHIFT)) & S50_ELS_KS2_KS2_UKUOK_MASK) + +#define S50_ELS_KS2_KS2_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS2_KS2_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS2_KS2_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSPMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSPMS_MASK) + +#define S50_ELS_KS2_KS2_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS2_KS2_UTLSMS_SHIFT (25U) +#define S50_ELS_KS2_KS2_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSMS_MASK) + +#define S50_ELS_KS2_KS2_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS2_KS2_UKGSRC_SHIFT (26U) +#define S50_ELS_KS2_KS2_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKGSRC_SHIFT)) & S50_ELS_KS2_KS2_UKGSRC_MASK) + +#define S50_ELS_KS2_KS2_UHWO_MASK (0x8000000U) +#define S50_ELS_KS2_KS2_UHWO_SHIFT (27U) +#define S50_ELS_KS2_KS2_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHWO_SHIFT)) & S50_ELS_KS2_KS2_UHWO_MASK) + +#define S50_ELS_KS2_KS2_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS2_KS2_UWRPOK_SHIFT (28U) +#define S50_ELS_KS2_KS2_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UWRPOK_SHIFT)) & S50_ELS_KS2_KS2_UWRPOK_MASK) + +#define S50_ELS_KS2_KS2_UDUK_MASK (0x20000000U) +#define S50_ELS_KS2_KS2_UDUK_SHIFT (29U) +#define S50_ELS_KS2_KS2_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UDUK_SHIFT)) & S50_ELS_KS2_KS2_UDUK_MASK) + +#define S50_ELS_KS2_KS2_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS2_KS2_UPPROT_SHIFT (30U) +#define S50_ELS_KS2_KS2_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UPPROT_SHIFT)) & S50_ELS_KS2_KS2_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS3 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS3_KS3_KSIZE_MASK (0x3U) +#define S50_ELS_KS3_KS3_KSIZE_SHIFT (0U) +/*! KS3_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS3_KS3_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KSIZE_SHIFT)) & S50_ELS_KS3_KS3_KSIZE_MASK) + +#define S50_ELS_KS3_KS3_KACT_MASK (0x20U) +#define S50_ELS_KS3_KS3_KACT_SHIFT (5U) +#define S50_ELS_KS3_KS3_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KACT_SHIFT)) & S50_ELS_KS3_KS3_KACT_MASK) + +#define S50_ELS_KS3_KS3_KBASE_MASK (0x40U) +#define S50_ELS_KS3_KS3_KBASE_SHIFT (6U) +#define S50_ELS_KS3_KS3_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KBASE_SHIFT)) & S50_ELS_KS3_KS3_KBASE_MASK) + +#define S50_ELS_KS3_KS3_FGP_MASK (0x80U) +#define S50_ELS_KS3_KS3_FGP_SHIFT (7U) +#define S50_ELS_KS3_KS3_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FGP_SHIFT)) & S50_ELS_KS3_KS3_FGP_MASK) + +#define S50_ELS_KS3_KS3_FRTN_MASK (0x100U) +#define S50_ELS_KS3_KS3_FRTN_SHIFT (8U) +#define S50_ELS_KS3_KS3_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FRTN_SHIFT)) & S50_ELS_KS3_KS3_FRTN_MASK) + +#define S50_ELS_KS3_KS3_FHWO_MASK (0x200U) +#define S50_ELS_KS3_KS3_FHWO_SHIFT (9U) +#define S50_ELS_KS3_KS3_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FHWO_SHIFT)) & S50_ELS_KS3_KS3_FHWO_MASK) + +#define S50_ELS_KS3_KS3_UKPUK_MASK (0x800U) +#define S50_ELS_KS3_KS3_UKPUK_SHIFT (11U) +#define S50_ELS_KS3_KS3_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKPUK_SHIFT)) & S50_ELS_KS3_KS3_UKPUK_MASK) + +#define S50_ELS_KS3_KS3_UTECDH_MASK (0x1000U) +#define S50_ELS_KS3_KS3_UTECDH_SHIFT (12U) +#define S50_ELS_KS3_KS3_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTECDH_SHIFT)) & S50_ELS_KS3_KS3_UTECDH_MASK) + +#define S50_ELS_KS3_KS3_UCMAC_MASK (0x2000U) +#define S50_ELS_KS3_KS3_UCMAC_SHIFT (13U) +#define S50_ELS_KS3_KS3_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCMAC_SHIFT)) & S50_ELS_KS3_KS3_UCMAC_MASK) + +#define S50_ELS_KS3_KS3_UKSK_MASK (0x4000U) +#define S50_ELS_KS3_KS3_UKSK_SHIFT (14U) +#define S50_ELS_KS3_KS3_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKSK_SHIFT)) & S50_ELS_KS3_KS3_UKSK_MASK) + +#define S50_ELS_KS3_KS3_URTF_MASK (0x8000U) +#define S50_ELS_KS3_KS3_URTF_SHIFT (15U) +#define S50_ELS_KS3_KS3_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_URTF_SHIFT)) & S50_ELS_KS3_KS3_URTF_MASK) + +#define S50_ELS_KS3_KS3_UCKDF_MASK (0x10000U) +#define S50_ELS_KS3_KS3_UCKDF_SHIFT (16U) +#define S50_ELS_KS3_KS3_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCKDF_SHIFT)) & S50_ELS_KS3_KS3_UCKDF_MASK) + +#define S50_ELS_KS3_KS3_UHKDF_MASK (0x20000U) +#define S50_ELS_KS3_KS3_UHKDF_SHIFT (17U) +#define S50_ELS_KS3_KS3_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHKDF_SHIFT)) & S50_ELS_KS3_KS3_UHKDF_MASK) + +#define S50_ELS_KS3_KS3_UECSG_MASK (0x40000U) +#define S50_ELS_KS3_KS3_UECSG_SHIFT (18U) +#define S50_ELS_KS3_KS3_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECSG_SHIFT)) & S50_ELS_KS3_KS3_UECSG_MASK) + +#define S50_ELS_KS3_KS3_UECDH_MASK (0x80000U) +#define S50_ELS_KS3_KS3_UECDH_SHIFT (19U) +#define S50_ELS_KS3_KS3_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECDH_SHIFT)) & S50_ELS_KS3_KS3_UECDH_MASK) + +#define S50_ELS_KS3_KS3_UAES_MASK (0x100000U) +#define S50_ELS_KS3_KS3_UAES_SHIFT (20U) +#define S50_ELS_KS3_KS3_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UAES_SHIFT)) & S50_ELS_KS3_KS3_UAES_MASK) + +#define S50_ELS_KS3_KS3_UHMAC_MASK (0x200000U) +#define S50_ELS_KS3_KS3_UHMAC_SHIFT (21U) +#define S50_ELS_KS3_KS3_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHMAC_SHIFT)) & S50_ELS_KS3_KS3_UHMAC_MASK) + +#define S50_ELS_KS3_KS3_UKWK_MASK (0x400000U) +#define S50_ELS_KS3_KS3_UKWK_SHIFT (22U) +#define S50_ELS_KS3_KS3_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKWK_SHIFT)) & S50_ELS_KS3_KS3_UKWK_MASK) + +#define S50_ELS_KS3_KS3_UKUOK_MASK (0x800000U) +#define S50_ELS_KS3_KS3_UKUOK_SHIFT (23U) +#define S50_ELS_KS3_KS3_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKUOK_SHIFT)) & S50_ELS_KS3_KS3_UKUOK_MASK) + +#define S50_ELS_KS3_KS3_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS3_KS3_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS3_KS3_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSPMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSPMS_MASK) + +#define S50_ELS_KS3_KS3_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS3_KS3_UTLSMS_SHIFT (25U) +#define S50_ELS_KS3_KS3_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSMS_MASK) + +#define S50_ELS_KS3_KS3_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS3_KS3_UKGSRC_SHIFT (26U) +#define S50_ELS_KS3_KS3_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKGSRC_SHIFT)) & S50_ELS_KS3_KS3_UKGSRC_MASK) + +#define S50_ELS_KS3_KS3_UHWO_MASK (0x8000000U) +#define S50_ELS_KS3_KS3_UHWO_SHIFT (27U) +#define S50_ELS_KS3_KS3_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHWO_SHIFT)) & S50_ELS_KS3_KS3_UHWO_MASK) + +#define S50_ELS_KS3_KS3_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS3_KS3_UWRPOK_SHIFT (28U) +#define S50_ELS_KS3_KS3_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UWRPOK_SHIFT)) & S50_ELS_KS3_KS3_UWRPOK_MASK) + +#define S50_ELS_KS3_KS3_UDUK_MASK (0x20000000U) +#define S50_ELS_KS3_KS3_UDUK_SHIFT (29U) +#define S50_ELS_KS3_KS3_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UDUK_SHIFT)) & S50_ELS_KS3_KS3_UDUK_MASK) + +#define S50_ELS_KS3_KS3_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS3_KS3_UPPROT_SHIFT (30U) +#define S50_ELS_KS3_KS3_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UPPROT_SHIFT)) & S50_ELS_KS3_KS3_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS4 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS4_KS4_KSIZE_MASK (0x3U) +#define S50_ELS_KS4_KS4_KSIZE_SHIFT (0U) +/*! KS4_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS4_KS4_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KSIZE_SHIFT)) & S50_ELS_KS4_KS4_KSIZE_MASK) + +#define S50_ELS_KS4_KS4_KACT_MASK (0x20U) +#define S50_ELS_KS4_KS4_KACT_SHIFT (5U) +#define S50_ELS_KS4_KS4_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KACT_SHIFT)) & S50_ELS_KS4_KS4_KACT_MASK) + +#define S50_ELS_KS4_KS4_KBASE_MASK (0x40U) +#define S50_ELS_KS4_KS4_KBASE_SHIFT (6U) +#define S50_ELS_KS4_KS4_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KBASE_SHIFT)) & S50_ELS_KS4_KS4_KBASE_MASK) + +#define S50_ELS_KS4_KS4_FGP_MASK (0x80U) +#define S50_ELS_KS4_KS4_FGP_SHIFT (7U) +#define S50_ELS_KS4_KS4_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FGP_SHIFT)) & S50_ELS_KS4_KS4_FGP_MASK) + +#define S50_ELS_KS4_KS4_FRTN_MASK (0x100U) +#define S50_ELS_KS4_KS4_FRTN_SHIFT (8U) +#define S50_ELS_KS4_KS4_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FRTN_SHIFT)) & S50_ELS_KS4_KS4_FRTN_MASK) + +#define S50_ELS_KS4_KS4_FHWO_MASK (0x200U) +#define S50_ELS_KS4_KS4_FHWO_SHIFT (9U) +#define S50_ELS_KS4_KS4_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FHWO_SHIFT)) & S50_ELS_KS4_KS4_FHWO_MASK) + +#define S50_ELS_KS4_KS4_UKPUK_MASK (0x800U) +#define S50_ELS_KS4_KS4_UKPUK_SHIFT (11U) +#define S50_ELS_KS4_KS4_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKPUK_SHIFT)) & S50_ELS_KS4_KS4_UKPUK_MASK) + +#define S50_ELS_KS4_KS4_UTECDH_MASK (0x1000U) +#define S50_ELS_KS4_KS4_UTECDH_SHIFT (12U) +#define S50_ELS_KS4_KS4_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTECDH_SHIFT)) & S50_ELS_KS4_KS4_UTECDH_MASK) + +#define S50_ELS_KS4_KS4_UCMAC_MASK (0x2000U) +#define S50_ELS_KS4_KS4_UCMAC_SHIFT (13U) +#define S50_ELS_KS4_KS4_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCMAC_SHIFT)) & S50_ELS_KS4_KS4_UCMAC_MASK) + +#define S50_ELS_KS4_KS4_UKSK_MASK (0x4000U) +#define S50_ELS_KS4_KS4_UKSK_SHIFT (14U) +#define S50_ELS_KS4_KS4_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKSK_SHIFT)) & S50_ELS_KS4_KS4_UKSK_MASK) + +#define S50_ELS_KS4_KS4_URTF_MASK (0x8000U) +#define S50_ELS_KS4_KS4_URTF_SHIFT (15U) +#define S50_ELS_KS4_KS4_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_URTF_SHIFT)) & S50_ELS_KS4_KS4_URTF_MASK) + +#define S50_ELS_KS4_KS4_UCKDF_MASK (0x10000U) +#define S50_ELS_KS4_KS4_UCKDF_SHIFT (16U) +#define S50_ELS_KS4_KS4_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCKDF_SHIFT)) & S50_ELS_KS4_KS4_UCKDF_MASK) + +#define S50_ELS_KS4_KS4_UHKDF_MASK (0x20000U) +#define S50_ELS_KS4_KS4_UHKDF_SHIFT (17U) +#define S50_ELS_KS4_KS4_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHKDF_SHIFT)) & S50_ELS_KS4_KS4_UHKDF_MASK) + +#define S50_ELS_KS4_KS4_UECSG_MASK (0x40000U) +#define S50_ELS_KS4_KS4_UECSG_SHIFT (18U) +#define S50_ELS_KS4_KS4_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECSG_SHIFT)) & S50_ELS_KS4_KS4_UECSG_MASK) + +#define S50_ELS_KS4_KS4_UECDH_MASK (0x80000U) +#define S50_ELS_KS4_KS4_UECDH_SHIFT (19U) +#define S50_ELS_KS4_KS4_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECDH_SHIFT)) & S50_ELS_KS4_KS4_UECDH_MASK) + +#define S50_ELS_KS4_KS4_UAES_MASK (0x100000U) +#define S50_ELS_KS4_KS4_UAES_SHIFT (20U) +#define S50_ELS_KS4_KS4_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UAES_SHIFT)) & S50_ELS_KS4_KS4_UAES_MASK) + +#define S50_ELS_KS4_KS4_UHMAC_MASK (0x200000U) +#define S50_ELS_KS4_KS4_UHMAC_SHIFT (21U) +#define S50_ELS_KS4_KS4_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHMAC_SHIFT)) & S50_ELS_KS4_KS4_UHMAC_MASK) + +#define S50_ELS_KS4_KS4_UKWK_MASK (0x400000U) +#define S50_ELS_KS4_KS4_UKWK_SHIFT (22U) +#define S50_ELS_KS4_KS4_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKWK_SHIFT)) & S50_ELS_KS4_KS4_UKWK_MASK) + +#define S50_ELS_KS4_KS4_UKUOK_MASK (0x800000U) +#define S50_ELS_KS4_KS4_UKUOK_SHIFT (23U) +#define S50_ELS_KS4_KS4_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKUOK_SHIFT)) & S50_ELS_KS4_KS4_UKUOK_MASK) + +#define S50_ELS_KS4_KS4_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS4_KS4_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS4_KS4_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSPMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSPMS_MASK) + +#define S50_ELS_KS4_KS4_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS4_KS4_UTLSMS_SHIFT (25U) +#define S50_ELS_KS4_KS4_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSMS_MASK) + +#define S50_ELS_KS4_KS4_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS4_KS4_UKGSRC_SHIFT (26U) +#define S50_ELS_KS4_KS4_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKGSRC_SHIFT)) & S50_ELS_KS4_KS4_UKGSRC_MASK) + +#define S50_ELS_KS4_KS4_UHWO_MASK (0x8000000U) +#define S50_ELS_KS4_KS4_UHWO_SHIFT (27U) +#define S50_ELS_KS4_KS4_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHWO_SHIFT)) & S50_ELS_KS4_KS4_UHWO_MASK) + +#define S50_ELS_KS4_KS4_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS4_KS4_UWRPOK_SHIFT (28U) +#define S50_ELS_KS4_KS4_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UWRPOK_SHIFT)) & S50_ELS_KS4_KS4_UWRPOK_MASK) + +#define S50_ELS_KS4_KS4_UDUK_MASK (0x20000000U) +#define S50_ELS_KS4_KS4_UDUK_SHIFT (29U) +#define S50_ELS_KS4_KS4_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UDUK_SHIFT)) & S50_ELS_KS4_KS4_UDUK_MASK) + +#define S50_ELS_KS4_KS4_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS4_KS4_UPPROT_SHIFT (30U) +#define S50_ELS_KS4_KS4_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UPPROT_SHIFT)) & S50_ELS_KS4_KS4_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS5 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS5_KS5_KSIZE_MASK (0x3U) +#define S50_ELS_KS5_KS5_KSIZE_SHIFT (0U) +/*! KS5_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS5_KS5_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KSIZE_SHIFT)) & S50_ELS_KS5_KS5_KSIZE_MASK) + +#define S50_ELS_KS5_KS5_KACT_MASK (0x20U) +#define S50_ELS_KS5_KS5_KACT_SHIFT (5U) +#define S50_ELS_KS5_KS5_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KACT_SHIFT)) & S50_ELS_KS5_KS5_KACT_MASK) + +#define S50_ELS_KS5_KS5_KBASE_MASK (0x40U) +#define S50_ELS_KS5_KS5_KBASE_SHIFT (6U) +#define S50_ELS_KS5_KS5_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KBASE_SHIFT)) & S50_ELS_KS5_KS5_KBASE_MASK) + +#define S50_ELS_KS5_KS5_FGP_MASK (0x80U) +#define S50_ELS_KS5_KS5_FGP_SHIFT (7U) +#define S50_ELS_KS5_KS5_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FGP_SHIFT)) & S50_ELS_KS5_KS5_FGP_MASK) + +#define S50_ELS_KS5_KS5_FRTN_MASK (0x100U) +#define S50_ELS_KS5_KS5_FRTN_SHIFT (8U) +#define S50_ELS_KS5_KS5_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FRTN_SHIFT)) & S50_ELS_KS5_KS5_FRTN_MASK) + +#define S50_ELS_KS5_KS5_FHWO_MASK (0x200U) +#define S50_ELS_KS5_KS5_FHWO_SHIFT (9U) +#define S50_ELS_KS5_KS5_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FHWO_SHIFT)) & S50_ELS_KS5_KS5_FHWO_MASK) + +#define S50_ELS_KS5_KS5_UKPUK_MASK (0x800U) +#define S50_ELS_KS5_KS5_UKPUK_SHIFT (11U) +#define S50_ELS_KS5_KS5_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKPUK_SHIFT)) & S50_ELS_KS5_KS5_UKPUK_MASK) + +#define S50_ELS_KS5_KS5_UTECDH_MASK (0x1000U) +#define S50_ELS_KS5_KS5_UTECDH_SHIFT (12U) +#define S50_ELS_KS5_KS5_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTECDH_SHIFT)) & S50_ELS_KS5_KS5_UTECDH_MASK) + +#define S50_ELS_KS5_KS5_UCMAC_MASK (0x2000U) +#define S50_ELS_KS5_KS5_UCMAC_SHIFT (13U) +#define S50_ELS_KS5_KS5_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCMAC_SHIFT)) & S50_ELS_KS5_KS5_UCMAC_MASK) + +#define S50_ELS_KS5_KS5_UKSK_MASK (0x4000U) +#define S50_ELS_KS5_KS5_UKSK_SHIFT (14U) +#define S50_ELS_KS5_KS5_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKSK_SHIFT)) & S50_ELS_KS5_KS5_UKSK_MASK) + +#define S50_ELS_KS5_KS5_URTF_MASK (0x8000U) +#define S50_ELS_KS5_KS5_URTF_SHIFT (15U) +#define S50_ELS_KS5_KS5_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_URTF_SHIFT)) & S50_ELS_KS5_KS5_URTF_MASK) + +#define S50_ELS_KS5_KS5_UCKDF_MASK (0x10000U) +#define S50_ELS_KS5_KS5_UCKDF_SHIFT (16U) +#define S50_ELS_KS5_KS5_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCKDF_SHIFT)) & S50_ELS_KS5_KS5_UCKDF_MASK) + +#define S50_ELS_KS5_KS5_UHKDF_MASK (0x20000U) +#define S50_ELS_KS5_KS5_UHKDF_SHIFT (17U) +#define S50_ELS_KS5_KS5_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHKDF_SHIFT)) & S50_ELS_KS5_KS5_UHKDF_MASK) + +#define S50_ELS_KS5_KS5_UECSG_MASK (0x40000U) +#define S50_ELS_KS5_KS5_UECSG_SHIFT (18U) +#define S50_ELS_KS5_KS5_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECSG_SHIFT)) & S50_ELS_KS5_KS5_UECSG_MASK) + +#define S50_ELS_KS5_KS5_UECDH_MASK (0x80000U) +#define S50_ELS_KS5_KS5_UECDH_SHIFT (19U) +#define S50_ELS_KS5_KS5_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECDH_SHIFT)) & S50_ELS_KS5_KS5_UECDH_MASK) + +#define S50_ELS_KS5_KS5_UAES_MASK (0x100000U) +#define S50_ELS_KS5_KS5_UAES_SHIFT (20U) +#define S50_ELS_KS5_KS5_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UAES_SHIFT)) & S50_ELS_KS5_KS5_UAES_MASK) + +#define S50_ELS_KS5_KS5_UHMAC_MASK (0x200000U) +#define S50_ELS_KS5_KS5_UHMAC_SHIFT (21U) +#define S50_ELS_KS5_KS5_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHMAC_SHIFT)) & S50_ELS_KS5_KS5_UHMAC_MASK) + +#define S50_ELS_KS5_KS5_UKWK_MASK (0x400000U) +#define S50_ELS_KS5_KS5_UKWK_SHIFT (22U) +#define S50_ELS_KS5_KS5_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKWK_SHIFT)) & S50_ELS_KS5_KS5_UKWK_MASK) + +#define S50_ELS_KS5_KS5_UKUOK_MASK (0x800000U) +#define S50_ELS_KS5_KS5_UKUOK_SHIFT (23U) +#define S50_ELS_KS5_KS5_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKUOK_SHIFT)) & S50_ELS_KS5_KS5_UKUOK_MASK) + +#define S50_ELS_KS5_KS5_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS5_KS5_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS5_KS5_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSPMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSPMS_MASK) + +#define S50_ELS_KS5_KS5_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS5_KS5_UTLSMS_SHIFT (25U) +#define S50_ELS_KS5_KS5_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSMS_MASK) + +#define S50_ELS_KS5_KS5_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS5_KS5_UKGSRC_SHIFT (26U) +#define S50_ELS_KS5_KS5_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKGSRC_SHIFT)) & S50_ELS_KS5_KS5_UKGSRC_MASK) + +#define S50_ELS_KS5_KS5_UHWO_MASK (0x8000000U) +#define S50_ELS_KS5_KS5_UHWO_SHIFT (27U) +#define S50_ELS_KS5_KS5_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHWO_SHIFT)) & S50_ELS_KS5_KS5_UHWO_MASK) + +#define S50_ELS_KS5_KS5_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS5_KS5_UWRPOK_SHIFT (28U) +#define S50_ELS_KS5_KS5_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UWRPOK_SHIFT)) & S50_ELS_KS5_KS5_UWRPOK_MASK) + +#define S50_ELS_KS5_KS5_UDUK_MASK (0x20000000U) +#define S50_ELS_KS5_KS5_UDUK_SHIFT (29U) +#define S50_ELS_KS5_KS5_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UDUK_SHIFT)) & S50_ELS_KS5_KS5_UDUK_MASK) + +#define S50_ELS_KS5_KS5_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS5_KS5_UPPROT_SHIFT (30U) +#define S50_ELS_KS5_KS5_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UPPROT_SHIFT)) & S50_ELS_KS5_KS5_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS6 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS6_KS6_KSIZE_MASK (0x3U) +#define S50_ELS_KS6_KS6_KSIZE_SHIFT (0U) +/*! KS6_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS6_KS6_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KSIZE_SHIFT)) & S50_ELS_KS6_KS6_KSIZE_MASK) + +#define S50_ELS_KS6_KS6_KACT_MASK (0x20U) +#define S50_ELS_KS6_KS6_KACT_SHIFT (5U) +#define S50_ELS_KS6_KS6_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KACT_SHIFT)) & S50_ELS_KS6_KS6_KACT_MASK) + +#define S50_ELS_KS6_KS6_KBASE_MASK (0x40U) +#define S50_ELS_KS6_KS6_KBASE_SHIFT (6U) +#define S50_ELS_KS6_KS6_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KBASE_SHIFT)) & S50_ELS_KS6_KS6_KBASE_MASK) + +#define S50_ELS_KS6_KS6_FGP_MASK (0x80U) +#define S50_ELS_KS6_KS6_FGP_SHIFT (7U) +#define S50_ELS_KS6_KS6_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FGP_SHIFT)) & S50_ELS_KS6_KS6_FGP_MASK) + +#define S50_ELS_KS6_KS6_FRTN_MASK (0x100U) +#define S50_ELS_KS6_KS6_FRTN_SHIFT (8U) +#define S50_ELS_KS6_KS6_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FRTN_SHIFT)) & S50_ELS_KS6_KS6_FRTN_MASK) + +#define S50_ELS_KS6_KS6_FHWO_MASK (0x200U) +#define S50_ELS_KS6_KS6_FHWO_SHIFT (9U) +#define S50_ELS_KS6_KS6_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FHWO_SHIFT)) & S50_ELS_KS6_KS6_FHWO_MASK) + +#define S50_ELS_KS6_KS6_UKPUK_MASK (0x800U) +#define S50_ELS_KS6_KS6_UKPUK_SHIFT (11U) +#define S50_ELS_KS6_KS6_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKPUK_SHIFT)) & S50_ELS_KS6_KS6_UKPUK_MASK) + +#define S50_ELS_KS6_KS6_UTECDH_MASK (0x1000U) +#define S50_ELS_KS6_KS6_UTECDH_SHIFT (12U) +#define S50_ELS_KS6_KS6_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTECDH_SHIFT)) & S50_ELS_KS6_KS6_UTECDH_MASK) + +#define S50_ELS_KS6_KS6_UCMAC_MASK (0x2000U) +#define S50_ELS_KS6_KS6_UCMAC_SHIFT (13U) +#define S50_ELS_KS6_KS6_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCMAC_SHIFT)) & S50_ELS_KS6_KS6_UCMAC_MASK) + +#define S50_ELS_KS6_KS6_UKSK_MASK (0x4000U) +#define S50_ELS_KS6_KS6_UKSK_SHIFT (14U) +#define S50_ELS_KS6_KS6_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKSK_SHIFT)) & S50_ELS_KS6_KS6_UKSK_MASK) + +#define S50_ELS_KS6_KS6_URTF_MASK (0x8000U) +#define S50_ELS_KS6_KS6_URTF_SHIFT (15U) +#define S50_ELS_KS6_KS6_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_URTF_SHIFT)) & S50_ELS_KS6_KS6_URTF_MASK) + +#define S50_ELS_KS6_KS6_UCKDF_MASK (0x10000U) +#define S50_ELS_KS6_KS6_UCKDF_SHIFT (16U) +#define S50_ELS_KS6_KS6_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCKDF_SHIFT)) & S50_ELS_KS6_KS6_UCKDF_MASK) + +#define S50_ELS_KS6_KS6_UHKDF_MASK (0x20000U) +#define S50_ELS_KS6_KS6_UHKDF_SHIFT (17U) +#define S50_ELS_KS6_KS6_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHKDF_SHIFT)) & S50_ELS_KS6_KS6_UHKDF_MASK) + +#define S50_ELS_KS6_KS6_UECSG_MASK (0x40000U) +#define S50_ELS_KS6_KS6_UECSG_SHIFT (18U) +#define S50_ELS_KS6_KS6_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECSG_SHIFT)) & S50_ELS_KS6_KS6_UECSG_MASK) + +#define S50_ELS_KS6_KS6_UECDH_MASK (0x80000U) +#define S50_ELS_KS6_KS6_UECDH_SHIFT (19U) +#define S50_ELS_KS6_KS6_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECDH_SHIFT)) & S50_ELS_KS6_KS6_UECDH_MASK) + +#define S50_ELS_KS6_KS6_UAES_MASK (0x100000U) +#define S50_ELS_KS6_KS6_UAES_SHIFT (20U) +#define S50_ELS_KS6_KS6_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UAES_SHIFT)) & S50_ELS_KS6_KS6_UAES_MASK) + +#define S50_ELS_KS6_KS6_UHMAC_MASK (0x200000U) +#define S50_ELS_KS6_KS6_UHMAC_SHIFT (21U) +#define S50_ELS_KS6_KS6_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHMAC_SHIFT)) & S50_ELS_KS6_KS6_UHMAC_MASK) + +#define S50_ELS_KS6_KS6_UKWK_MASK (0x400000U) +#define S50_ELS_KS6_KS6_UKWK_SHIFT (22U) +#define S50_ELS_KS6_KS6_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKWK_SHIFT)) & S50_ELS_KS6_KS6_UKWK_MASK) + +#define S50_ELS_KS6_KS6_UKUOK_MASK (0x800000U) +#define S50_ELS_KS6_KS6_UKUOK_SHIFT (23U) +#define S50_ELS_KS6_KS6_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKUOK_SHIFT)) & S50_ELS_KS6_KS6_UKUOK_MASK) + +#define S50_ELS_KS6_KS6_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS6_KS6_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS6_KS6_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSPMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSPMS_MASK) + +#define S50_ELS_KS6_KS6_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS6_KS6_UTLSMS_SHIFT (25U) +#define S50_ELS_KS6_KS6_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSMS_MASK) + +#define S50_ELS_KS6_KS6_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS6_KS6_UKGSRC_SHIFT (26U) +#define S50_ELS_KS6_KS6_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKGSRC_SHIFT)) & S50_ELS_KS6_KS6_UKGSRC_MASK) + +#define S50_ELS_KS6_KS6_UHWO_MASK (0x8000000U) +#define S50_ELS_KS6_KS6_UHWO_SHIFT (27U) +#define S50_ELS_KS6_KS6_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHWO_SHIFT)) & S50_ELS_KS6_KS6_UHWO_MASK) + +#define S50_ELS_KS6_KS6_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS6_KS6_UWRPOK_SHIFT (28U) +#define S50_ELS_KS6_KS6_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UWRPOK_SHIFT)) & S50_ELS_KS6_KS6_UWRPOK_MASK) + +#define S50_ELS_KS6_KS6_UDUK_MASK (0x20000000U) +#define S50_ELS_KS6_KS6_UDUK_SHIFT (29U) +#define S50_ELS_KS6_KS6_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UDUK_SHIFT)) & S50_ELS_KS6_KS6_UDUK_MASK) + +#define S50_ELS_KS6_KS6_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS6_KS6_UPPROT_SHIFT (30U) +#define S50_ELS_KS6_KS6_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UPPROT_SHIFT)) & S50_ELS_KS6_KS6_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS7 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS7_KS7_KSIZE_MASK (0x3U) +#define S50_ELS_KS7_KS7_KSIZE_SHIFT (0U) +/*! KS7_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS7_KS7_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KSIZE_SHIFT)) & S50_ELS_KS7_KS7_KSIZE_MASK) + +#define S50_ELS_KS7_KS7_KACT_MASK (0x20U) +#define S50_ELS_KS7_KS7_KACT_SHIFT (5U) +#define S50_ELS_KS7_KS7_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KACT_SHIFT)) & S50_ELS_KS7_KS7_KACT_MASK) + +#define S50_ELS_KS7_KS7_KBASE_MASK (0x40U) +#define S50_ELS_KS7_KS7_KBASE_SHIFT (6U) +#define S50_ELS_KS7_KS7_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KBASE_SHIFT)) & S50_ELS_KS7_KS7_KBASE_MASK) + +#define S50_ELS_KS7_KS7_FGP_MASK (0x80U) +#define S50_ELS_KS7_KS7_FGP_SHIFT (7U) +#define S50_ELS_KS7_KS7_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FGP_SHIFT)) & S50_ELS_KS7_KS7_FGP_MASK) + +#define S50_ELS_KS7_KS7_FRTN_MASK (0x100U) +#define S50_ELS_KS7_KS7_FRTN_SHIFT (8U) +#define S50_ELS_KS7_KS7_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FRTN_SHIFT)) & S50_ELS_KS7_KS7_FRTN_MASK) + +#define S50_ELS_KS7_KS7_FHWO_MASK (0x200U) +#define S50_ELS_KS7_KS7_FHWO_SHIFT (9U) +#define S50_ELS_KS7_KS7_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FHWO_SHIFT)) & S50_ELS_KS7_KS7_FHWO_MASK) + +#define S50_ELS_KS7_KS7_UKPUK_MASK (0x800U) +#define S50_ELS_KS7_KS7_UKPUK_SHIFT (11U) +#define S50_ELS_KS7_KS7_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKPUK_SHIFT)) & S50_ELS_KS7_KS7_UKPUK_MASK) + +#define S50_ELS_KS7_KS7_UTECDH_MASK (0x1000U) +#define S50_ELS_KS7_KS7_UTECDH_SHIFT (12U) +#define S50_ELS_KS7_KS7_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTECDH_SHIFT)) & S50_ELS_KS7_KS7_UTECDH_MASK) + +#define S50_ELS_KS7_KS7_UCMAC_MASK (0x2000U) +#define S50_ELS_KS7_KS7_UCMAC_SHIFT (13U) +#define S50_ELS_KS7_KS7_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCMAC_SHIFT)) & S50_ELS_KS7_KS7_UCMAC_MASK) + +#define S50_ELS_KS7_KS7_UKSK_MASK (0x4000U) +#define S50_ELS_KS7_KS7_UKSK_SHIFT (14U) +#define S50_ELS_KS7_KS7_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKSK_SHIFT)) & S50_ELS_KS7_KS7_UKSK_MASK) + +#define S50_ELS_KS7_KS7_URTF_MASK (0x8000U) +#define S50_ELS_KS7_KS7_URTF_SHIFT (15U) +#define S50_ELS_KS7_KS7_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_URTF_SHIFT)) & S50_ELS_KS7_KS7_URTF_MASK) + +#define S50_ELS_KS7_KS7_UCKDF_MASK (0x10000U) +#define S50_ELS_KS7_KS7_UCKDF_SHIFT (16U) +#define S50_ELS_KS7_KS7_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCKDF_SHIFT)) & S50_ELS_KS7_KS7_UCKDF_MASK) + +#define S50_ELS_KS7_KS7_UHKDF_MASK (0x20000U) +#define S50_ELS_KS7_KS7_UHKDF_SHIFT (17U) +#define S50_ELS_KS7_KS7_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHKDF_SHIFT)) & S50_ELS_KS7_KS7_UHKDF_MASK) + +#define S50_ELS_KS7_KS7_UECSG_MASK (0x40000U) +#define S50_ELS_KS7_KS7_UECSG_SHIFT (18U) +#define S50_ELS_KS7_KS7_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECSG_SHIFT)) & S50_ELS_KS7_KS7_UECSG_MASK) + +#define S50_ELS_KS7_KS7_UECDH_MASK (0x80000U) +#define S50_ELS_KS7_KS7_UECDH_SHIFT (19U) +#define S50_ELS_KS7_KS7_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECDH_SHIFT)) & S50_ELS_KS7_KS7_UECDH_MASK) + +#define S50_ELS_KS7_KS7_UAES_MASK (0x100000U) +#define S50_ELS_KS7_KS7_UAES_SHIFT (20U) +#define S50_ELS_KS7_KS7_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UAES_SHIFT)) & S50_ELS_KS7_KS7_UAES_MASK) + +#define S50_ELS_KS7_KS7_UHMAC_MASK (0x200000U) +#define S50_ELS_KS7_KS7_UHMAC_SHIFT (21U) +#define S50_ELS_KS7_KS7_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHMAC_SHIFT)) & S50_ELS_KS7_KS7_UHMAC_MASK) + +#define S50_ELS_KS7_KS7_UKWK_MASK (0x400000U) +#define S50_ELS_KS7_KS7_UKWK_SHIFT (22U) +#define S50_ELS_KS7_KS7_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKWK_SHIFT)) & S50_ELS_KS7_KS7_UKWK_MASK) + +#define S50_ELS_KS7_KS7_UKUOK_MASK (0x800000U) +#define S50_ELS_KS7_KS7_UKUOK_SHIFT (23U) +#define S50_ELS_KS7_KS7_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKUOK_SHIFT)) & S50_ELS_KS7_KS7_UKUOK_MASK) + +#define S50_ELS_KS7_KS7_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS7_KS7_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS7_KS7_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSPMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSPMS_MASK) + +#define S50_ELS_KS7_KS7_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS7_KS7_UTLSMS_SHIFT (25U) +#define S50_ELS_KS7_KS7_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSMS_MASK) + +#define S50_ELS_KS7_KS7_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS7_KS7_UKGSRC_SHIFT (26U) +#define S50_ELS_KS7_KS7_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKGSRC_SHIFT)) & S50_ELS_KS7_KS7_UKGSRC_MASK) + +#define S50_ELS_KS7_KS7_UHWO_MASK (0x8000000U) +#define S50_ELS_KS7_KS7_UHWO_SHIFT (27U) +#define S50_ELS_KS7_KS7_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHWO_SHIFT)) & S50_ELS_KS7_KS7_UHWO_MASK) + +#define S50_ELS_KS7_KS7_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS7_KS7_UWRPOK_SHIFT (28U) +#define S50_ELS_KS7_KS7_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UWRPOK_SHIFT)) & S50_ELS_KS7_KS7_UWRPOK_MASK) + +#define S50_ELS_KS7_KS7_UDUK_MASK (0x20000000U) +#define S50_ELS_KS7_KS7_UDUK_SHIFT (29U) +#define S50_ELS_KS7_KS7_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UDUK_SHIFT)) & S50_ELS_KS7_KS7_UDUK_MASK) + +#define S50_ELS_KS7_KS7_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS7_KS7_UPPROT_SHIFT (30U) +#define S50_ELS_KS7_KS7_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UPPROT_SHIFT)) & S50_ELS_KS7_KS7_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS8 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS8_KS8_KSIZE_MASK (0x3U) +#define S50_ELS_KS8_KS8_KSIZE_SHIFT (0U) +/*! KS8_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS8_KS8_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KSIZE_SHIFT)) & S50_ELS_KS8_KS8_KSIZE_MASK) + +#define S50_ELS_KS8_KS8_KACT_MASK (0x20U) +#define S50_ELS_KS8_KS8_KACT_SHIFT (5U) +#define S50_ELS_KS8_KS8_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KACT_SHIFT)) & S50_ELS_KS8_KS8_KACT_MASK) + +#define S50_ELS_KS8_KS8_KBASE_MASK (0x40U) +#define S50_ELS_KS8_KS8_KBASE_SHIFT (6U) +#define S50_ELS_KS8_KS8_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KBASE_SHIFT)) & S50_ELS_KS8_KS8_KBASE_MASK) + +#define S50_ELS_KS8_KS8_FGP_MASK (0x80U) +#define S50_ELS_KS8_KS8_FGP_SHIFT (7U) +#define S50_ELS_KS8_KS8_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FGP_SHIFT)) & S50_ELS_KS8_KS8_FGP_MASK) + +#define S50_ELS_KS8_KS8_FRTN_MASK (0x100U) +#define S50_ELS_KS8_KS8_FRTN_SHIFT (8U) +#define S50_ELS_KS8_KS8_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FRTN_SHIFT)) & S50_ELS_KS8_KS8_FRTN_MASK) + +#define S50_ELS_KS8_KS8_FHWO_MASK (0x200U) +#define S50_ELS_KS8_KS8_FHWO_SHIFT (9U) +#define S50_ELS_KS8_KS8_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FHWO_SHIFT)) & S50_ELS_KS8_KS8_FHWO_MASK) + +#define S50_ELS_KS8_KS8_UKPUK_MASK (0x800U) +#define S50_ELS_KS8_KS8_UKPUK_SHIFT (11U) +#define S50_ELS_KS8_KS8_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKPUK_SHIFT)) & S50_ELS_KS8_KS8_UKPUK_MASK) + +#define S50_ELS_KS8_KS8_UTECDH_MASK (0x1000U) +#define S50_ELS_KS8_KS8_UTECDH_SHIFT (12U) +#define S50_ELS_KS8_KS8_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTECDH_SHIFT)) & S50_ELS_KS8_KS8_UTECDH_MASK) + +#define S50_ELS_KS8_KS8_UCMAC_MASK (0x2000U) +#define S50_ELS_KS8_KS8_UCMAC_SHIFT (13U) +#define S50_ELS_KS8_KS8_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCMAC_SHIFT)) & S50_ELS_KS8_KS8_UCMAC_MASK) + +#define S50_ELS_KS8_KS8_UKSK_MASK (0x4000U) +#define S50_ELS_KS8_KS8_UKSK_SHIFT (14U) +#define S50_ELS_KS8_KS8_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKSK_SHIFT)) & S50_ELS_KS8_KS8_UKSK_MASK) + +#define S50_ELS_KS8_KS8_URTF_MASK (0x8000U) +#define S50_ELS_KS8_KS8_URTF_SHIFT (15U) +#define S50_ELS_KS8_KS8_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_URTF_SHIFT)) & S50_ELS_KS8_KS8_URTF_MASK) + +#define S50_ELS_KS8_KS8_UCKDF_MASK (0x10000U) +#define S50_ELS_KS8_KS8_UCKDF_SHIFT (16U) +#define S50_ELS_KS8_KS8_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCKDF_SHIFT)) & S50_ELS_KS8_KS8_UCKDF_MASK) + +#define S50_ELS_KS8_KS8_UHKDF_MASK (0x20000U) +#define S50_ELS_KS8_KS8_UHKDF_SHIFT (17U) +#define S50_ELS_KS8_KS8_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHKDF_SHIFT)) & S50_ELS_KS8_KS8_UHKDF_MASK) + +#define S50_ELS_KS8_KS8_UECSG_MASK (0x40000U) +#define S50_ELS_KS8_KS8_UECSG_SHIFT (18U) +#define S50_ELS_KS8_KS8_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECSG_SHIFT)) & S50_ELS_KS8_KS8_UECSG_MASK) + +#define S50_ELS_KS8_KS8_UECDH_MASK (0x80000U) +#define S50_ELS_KS8_KS8_UECDH_SHIFT (19U) +#define S50_ELS_KS8_KS8_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECDH_SHIFT)) & S50_ELS_KS8_KS8_UECDH_MASK) + +#define S50_ELS_KS8_KS8_UAES_MASK (0x100000U) +#define S50_ELS_KS8_KS8_UAES_SHIFT (20U) +#define S50_ELS_KS8_KS8_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UAES_SHIFT)) & S50_ELS_KS8_KS8_UAES_MASK) + +#define S50_ELS_KS8_KS8_UHMAC_MASK (0x200000U) +#define S50_ELS_KS8_KS8_UHMAC_SHIFT (21U) +#define S50_ELS_KS8_KS8_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHMAC_SHIFT)) & S50_ELS_KS8_KS8_UHMAC_MASK) + +#define S50_ELS_KS8_KS8_UKWK_MASK (0x400000U) +#define S50_ELS_KS8_KS8_UKWK_SHIFT (22U) +#define S50_ELS_KS8_KS8_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKWK_SHIFT)) & S50_ELS_KS8_KS8_UKWK_MASK) + +#define S50_ELS_KS8_KS8_UKUOK_MASK (0x800000U) +#define S50_ELS_KS8_KS8_UKUOK_SHIFT (23U) +#define S50_ELS_KS8_KS8_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKUOK_SHIFT)) & S50_ELS_KS8_KS8_UKUOK_MASK) + +#define S50_ELS_KS8_KS8_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS8_KS8_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS8_KS8_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSPMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSPMS_MASK) + +#define S50_ELS_KS8_KS8_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS8_KS8_UTLSMS_SHIFT (25U) +#define S50_ELS_KS8_KS8_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSMS_MASK) + +#define S50_ELS_KS8_KS8_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS8_KS8_UKGSRC_SHIFT (26U) +#define S50_ELS_KS8_KS8_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKGSRC_SHIFT)) & S50_ELS_KS8_KS8_UKGSRC_MASK) + +#define S50_ELS_KS8_KS8_UHWO_MASK (0x8000000U) +#define S50_ELS_KS8_KS8_UHWO_SHIFT (27U) +#define S50_ELS_KS8_KS8_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHWO_SHIFT)) & S50_ELS_KS8_KS8_UHWO_MASK) + +#define S50_ELS_KS8_KS8_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS8_KS8_UWRPOK_SHIFT (28U) +#define S50_ELS_KS8_KS8_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UWRPOK_SHIFT)) & S50_ELS_KS8_KS8_UWRPOK_MASK) + +#define S50_ELS_KS8_KS8_UDUK_MASK (0x20000000U) +#define S50_ELS_KS8_KS8_UDUK_SHIFT (29U) +#define S50_ELS_KS8_KS8_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UDUK_SHIFT)) & S50_ELS_KS8_KS8_UDUK_MASK) + +#define S50_ELS_KS8_KS8_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS8_KS8_UPPROT_SHIFT (30U) +#define S50_ELS_KS8_KS8_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UPPROT_SHIFT)) & S50_ELS_KS8_KS8_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS9 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS9_KS9_KSIZE_MASK (0x3U) +#define S50_ELS_KS9_KS9_KSIZE_SHIFT (0U) +/*! KS9_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS9_KS9_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KSIZE_SHIFT)) & S50_ELS_KS9_KS9_KSIZE_MASK) + +#define S50_ELS_KS9_KS9_KACT_MASK (0x20U) +#define S50_ELS_KS9_KS9_KACT_SHIFT (5U) +#define S50_ELS_KS9_KS9_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KACT_SHIFT)) & S50_ELS_KS9_KS9_KACT_MASK) + +#define S50_ELS_KS9_KS9_KBASE_MASK (0x40U) +#define S50_ELS_KS9_KS9_KBASE_SHIFT (6U) +#define S50_ELS_KS9_KS9_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KBASE_SHIFT)) & S50_ELS_KS9_KS9_KBASE_MASK) + +#define S50_ELS_KS9_KS9_FGP_MASK (0x80U) +#define S50_ELS_KS9_KS9_FGP_SHIFT (7U) +#define S50_ELS_KS9_KS9_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FGP_SHIFT)) & S50_ELS_KS9_KS9_FGP_MASK) + +#define S50_ELS_KS9_KS9_FRTN_MASK (0x100U) +#define S50_ELS_KS9_KS9_FRTN_SHIFT (8U) +#define S50_ELS_KS9_KS9_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FRTN_SHIFT)) & S50_ELS_KS9_KS9_FRTN_MASK) + +#define S50_ELS_KS9_KS9_FHWO_MASK (0x200U) +#define S50_ELS_KS9_KS9_FHWO_SHIFT (9U) +#define S50_ELS_KS9_KS9_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FHWO_SHIFT)) & S50_ELS_KS9_KS9_FHWO_MASK) + +#define S50_ELS_KS9_KS9_UKPUK_MASK (0x800U) +#define S50_ELS_KS9_KS9_UKPUK_SHIFT (11U) +#define S50_ELS_KS9_KS9_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKPUK_SHIFT)) & S50_ELS_KS9_KS9_UKPUK_MASK) + +#define S50_ELS_KS9_KS9_UTECDH_MASK (0x1000U) +#define S50_ELS_KS9_KS9_UTECDH_SHIFT (12U) +#define S50_ELS_KS9_KS9_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTECDH_SHIFT)) & S50_ELS_KS9_KS9_UTECDH_MASK) + +#define S50_ELS_KS9_KS9_UCMAC_MASK (0x2000U) +#define S50_ELS_KS9_KS9_UCMAC_SHIFT (13U) +#define S50_ELS_KS9_KS9_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCMAC_SHIFT)) & S50_ELS_KS9_KS9_UCMAC_MASK) + +#define S50_ELS_KS9_KS9_UKSK_MASK (0x4000U) +#define S50_ELS_KS9_KS9_UKSK_SHIFT (14U) +#define S50_ELS_KS9_KS9_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKSK_SHIFT)) & S50_ELS_KS9_KS9_UKSK_MASK) + +#define S50_ELS_KS9_KS9_URTF_MASK (0x8000U) +#define S50_ELS_KS9_KS9_URTF_SHIFT (15U) +#define S50_ELS_KS9_KS9_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_URTF_SHIFT)) & S50_ELS_KS9_KS9_URTF_MASK) + +#define S50_ELS_KS9_KS9_UCKDF_MASK (0x10000U) +#define S50_ELS_KS9_KS9_UCKDF_SHIFT (16U) +#define S50_ELS_KS9_KS9_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCKDF_SHIFT)) & S50_ELS_KS9_KS9_UCKDF_MASK) + +#define S50_ELS_KS9_KS9_UHKDF_MASK (0x20000U) +#define S50_ELS_KS9_KS9_UHKDF_SHIFT (17U) +#define S50_ELS_KS9_KS9_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHKDF_SHIFT)) & S50_ELS_KS9_KS9_UHKDF_MASK) + +#define S50_ELS_KS9_KS9_UECSG_MASK (0x40000U) +#define S50_ELS_KS9_KS9_UECSG_SHIFT (18U) +#define S50_ELS_KS9_KS9_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECSG_SHIFT)) & S50_ELS_KS9_KS9_UECSG_MASK) + +#define S50_ELS_KS9_KS9_UECDH_MASK (0x80000U) +#define S50_ELS_KS9_KS9_UECDH_SHIFT (19U) +#define S50_ELS_KS9_KS9_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECDH_SHIFT)) & S50_ELS_KS9_KS9_UECDH_MASK) + +#define S50_ELS_KS9_KS9_UAES_MASK (0x100000U) +#define S50_ELS_KS9_KS9_UAES_SHIFT (20U) +#define S50_ELS_KS9_KS9_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UAES_SHIFT)) & S50_ELS_KS9_KS9_UAES_MASK) + +#define S50_ELS_KS9_KS9_UHMAC_MASK (0x200000U) +#define S50_ELS_KS9_KS9_UHMAC_SHIFT (21U) +#define S50_ELS_KS9_KS9_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHMAC_SHIFT)) & S50_ELS_KS9_KS9_UHMAC_MASK) + +#define S50_ELS_KS9_KS9_UKWK_MASK (0x400000U) +#define S50_ELS_KS9_KS9_UKWK_SHIFT (22U) +#define S50_ELS_KS9_KS9_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKWK_SHIFT)) & S50_ELS_KS9_KS9_UKWK_MASK) + +#define S50_ELS_KS9_KS9_UKUOK_MASK (0x800000U) +#define S50_ELS_KS9_KS9_UKUOK_SHIFT (23U) +#define S50_ELS_KS9_KS9_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKUOK_SHIFT)) & S50_ELS_KS9_KS9_UKUOK_MASK) + +#define S50_ELS_KS9_KS9_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS9_KS9_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS9_KS9_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSPMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSPMS_MASK) + +#define S50_ELS_KS9_KS9_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS9_KS9_UTLSMS_SHIFT (25U) +#define S50_ELS_KS9_KS9_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSMS_MASK) + +#define S50_ELS_KS9_KS9_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS9_KS9_UKGSRC_SHIFT (26U) +#define S50_ELS_KS9_KS9_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKGSRC_SHIFT)) & S50_ELS_KS9_KS9_UKGSRC_MASK) + +#define S50_ELS_KS9_KS9_UHWO_MASK (0x8000000U) +#define S50_ELS_KS9_KS9_UHWO_SHIFT (27U) +#define S50_ELS_KS9_KS9_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHWO_SHIFT)) & S50_ELS_KS9_KS9_UHWO_MASK) + +#define S50_ELS_KS9_KS9_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS9_KS9_UWRPOK_SHIFT (28U) +#define S50_ELS_KS9_KS9_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UWRPOK_SHIFT)) & S50_ELS_KS9_KS9_UWRPOK_MASK) + +#define S50_ELS_KS9_KS9_UDUK_MASK (0x20000000U) +#define S50_ELS_KS9_KS9_UDUK_SHIFT (29U) +#define S50_ELS_KS9_KS9_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UDUK_SHIFT)) & S50_ELS_KS9_KS9_UDUK_MASK) + +#define S50_ELS_KS9_KS9_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS9_KS9_UPPROT_SHIFT (30U) +#define S50_ELS_KS9_KS9_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UPPROT_SHIFT)) & S50_ELS_KS9_KS9_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS10 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS10_KS10_KSIZE_MASK (0x3U) +#define S50_ELS_KS10_KS10_KSIZE_SHIFT (0U) +/*! KS10_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS10_KS10_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KSIZE_SHIFT)) & S50_ELS_KS10_KS10_KSIZE_MASK) + +#define S50_ELS_KS10_KS10_KACT_MASK (0x20U) +#define S50_ELS_KS10_KS10_KACT_SHIFT (5U) +#define S50_ELS_KS10_KS10_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KACT_SHIFT)) & S50_ELS_KS10_KS10_KACT_MASK) + +#define S50_ELS_KS10_KS10_KBASE_MASK (0x40U) +#define S50_ELS_KS10_KS10_KBASE_SHIFT (6U) +#define S50_ELS_KS10_KS10_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KBASE_SHIFT)) & S50_ELS_KS10_KS10_KBASE_MASK) + +#define S50_ELS_KS10_KS10_FGP_MASK (0x80U) +#define S50_ELS_KS10_KS10_FGP_SHIFT (7U) +#define S50_ELS_KS10_KS10_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FGP_SHIFT)) & S50_ELS_KS10_KS10_FGP_MASK) + +#define S50_ELS_KS10_KS10_FRTN_MASK (0x100U) +#define S50_ELS_KS10_KS10_FRTN_SHIFT (8U) +#define S50_ELS_KS10_KS10_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FRTN_SHIFT)) & S50_ELS_KS10_KS10_FRTN_MASK) + +#define S50_ELS_KS10_KS10_FHWO_MASK (0x200U) +#define S50_ELS_KS10_KS10_FHWO_SHIFT (9U) +#define S50_ELS_KS10_KS10_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FHWO_SHIFT)) & S50_ELS_KS10_KS10_FHWO_MASK) + +#define S50_ELS_KS10_KS10_UKPUK_MASK (0x800U) +#define S50_ELS_KS10_KS10_UKPUK_SHIFT (11U) +#define S50_ELS_KS10_KS10_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKPUK_SHIFT)) & S50_ELS_KS10_KS10_UKPUK_MASK) + +#define S50_ELS_KS10_KS10_UTECDH_MASK (0x1000U) +#define S50_ELS_KS10_KS10_UTECDH_SHIFT (12U) +#define S50_ELS_KS10_KS10_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTECDH_SHIFT)) & S50_ELS_KS10_KS10_UTECDH_MASK) + +#define S50_ELS_KS10_KS10_UCMAC_MASK (0x2000U) +#define S50_ELS_KS10_KS10_UCMAC_SHIFT (13U) +#define S50_ELS_KS10_KS10_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCMAC_SHIFT)) & S50_ELS_KS10_KS10_UCMAC_MASK) + +#define S50_ELS_KS10_KS10_UKSK_MASK (0x4000U) +#define S50_ELS_KS10_KS10_UKSK_SHIFT (14U) +#define S50_ELS_KS10_KS10_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKSK_SHIFT)) & S50_ELS_KS10_KS10_UKSK_MASK) + +#define S50_ELS_KS10_KS10_URTF_MASK (0x8000U) +#define S50_ELS_KS10_KS10_URTF_SHIFT (15U) +#define S50_ELS_KS10_KS10_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_URTF_SHIFT)) & S50_ELS_KS10_KS10_URTF_MASK) + +#define S50_ELS_KS10_KS10_UCKDF_MASK (0x10000U) +#define S50_ELS_KS10_KS10_UCKDF_SHIFT (16U) +#define S50_ELS_KS10_KS10_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCKDF_SHIFT)) & S50_ELS_KS10_KS10_UCKDF_MASK) + +#define S50_ELS_KS10_KS10_UHKDF_MASK (0x20000U) +#define S50_ELS_KS10_KS10_UHKDF_SHIFT (17U) +#define S50_ELS_KS10_KS10_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHKDF_SHIFT)) & S50_ELS_KS10_KS10_UHKDF_MASK) + +#define S50_ELS_KS10_KS10_UECSG_MASK (0x40000U) +#define S50_ELS_KS10_KS10_UECSG_SHIFT (18U) +#define S50_ELS_KS10_KS10_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECSG_SHIFT)) & S50_ELS_KS10_KS10_UECSG_MASK) + +#define S50_ELS_KS10_KS10_UECDH_MASK (0x80000U) +#define S50_ELS_KS10_KS10_UECDH_SHIFT (19U) +#define S50_ELS_KS10_KS10_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECDH_SHIFT)) & S50_ELS_KS10_KS10_UECDH_MASK) + +#define S50_ELS_KS10_KS10_UAES_MASK (0x100000U) +#define S50_ELS_KS10_KS10_UAES_SHIFT (20U) +#define S50_ELS_KS10_KS10_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UAES_SHIFT)) & S50_ELS_KS10_KS10_UAES_MASK) + +#define S50_ELS_KS10_KS10_UHMAC_MASK (0x200000U) +#define S50_ELS_KS10_KS10_UHMAC_SHIFT (21U) +#define S50_ELS_KS10_KS10_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHMAC_SHIFT)) & S50_ELS_KS10_KS10_UHMAC_MASK) + +#define S50_ELS_KS10_KS10_UKWK_MASK (0x400000U) +#define S50_ELS_KS10_KS10_UKWK_SHIFT (22U) +#define S50_ELS_KS10_KS10_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKWK_SHIFT)) & S50_ELS_KS10_KS10_UKWK_MASK) + +#define S50_ELS_KS10_KS10_UKUOK_MASK (0x800000U) +#define S50_ELS_KS10_KS10_UKUOK_SHIFT (23U) +#define S50_ELS_KS10_KS10_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKUOK_SHIFT)) & S50_ELS_KS10_KS10_UKUOK_MASK) + +#define S50_ELS_KS10_KS10_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS10_KS10_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS10_KS10_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSPMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSPMS_MASK) + +#define S50_ELS_KS10_KS10_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS10_KS10_UTLSMS_SHIFT (25U) +#define S50_ELS_KS10_KS10_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSMS_MASK) + +#define S50_ELS_KS10_KS10_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS10_KS10_UKGSRC_SHIFT (26U) +#define S50_ELS_KS10_KS10_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKGSRC_SHIFT)) & S50_ELS_KS10_KS10_UKGSRC_MASK) + +#define S50_ELS_KS10_KS10_UHWO_MASK (0x8000000U) +#define S50_ELS_KS10_KS10_UHWO_SHIFT (27U) +#define S50_ELS_KS10_KS10_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHWO_SHIFT)) & S50_ELS_KS10_KS10_UHWO_MASK) + +#define S50_ELS_KS10_KS10_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS10_KS10_UWRPOK_SHIFT (28U) +#define S50_ELS_KS10_KS10_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UWRPOK_SHIFT)) & S50_ELS_KS10_KS10_UWRPOK_MASK) + +#define S50_ELS_KS10_KS10_UDUK_MASK (0x20000000U) +#define S50_ELS_KS10_KS10_UDUK_SHIFT (29U) +#define S50_ELS_KS10_KS10_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UDUK_SHIFT)) & S50_ELS_KS10_KS10_UDUK_MASK) + +#define S50_ELS_KS10_KS10_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS10_KS10_UPPROT_SHIFT (30U) +#define S50_ELS_KS10_KS10_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UPPROT_SHIFT)) & S50_ELS_KS10_KS10_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS11 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS11_KS11_KSIZE_MASK (0x3U) +#define S50_ELS_KS11_KS11_KSIZE_SHIFT (0U) +/*! KS11_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS11_KS11_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KSIZE_SHIFT)) & S50_ELS_KS11_KS11_KSIZE_MASK) + +#define S50_ELS_KS11_KS11_KACT_MASK (0x20U) +#define S50_ELS_KS11_KS11_KACT_SHIFT (5U) +#define S50_ELS_KS11_KS11_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KACT_SHIFT)) & S50_ELS_KS11_KS11_KACT_MASK) + +#define S50_ELS_KS11_KS11_KBASE_MASK (0x40U) +#define S50_ELS_KS11_KS11_KBASE_SHIFT (6U) +#define S50_ELS_KS11_KS11_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KBASE_SHIFT)) & S50_ELS_KS11_KS11_KBASE_MASK) + +#define S50_ELS_KS11_KS11_FGP_MASK (0x80U) +#define S50_ELS_KS11_KS11_FGP_SHIFT (7U) +#define S50_ELS_KS11_KS11_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FGP_SHIFT)) & S50_ELS_KS11_KS11_FGP_MASK) + +#define S50_ELS_KS11_KS11_FRTN_MASK (0x100U) +#define S50_ELS_KS11_KS11_FRTN_SHIFT (8U) +#define S50_ELS_KS11_KS11_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FRTN_SHIFT)) & S50_ELS_KS11_KS11_FRTN_MASK) + +#define S50_ELS_KS11_KS11_FHWO_MASK (0x200U) +#define S50_ELS_KS11_KS11_FHWO_SHIFT (9U) +#define S50_ELS_KS11_KS11_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FHWO_SHIFT)) & S50_ELS_KS11_KS11_FHWO_MASK) + +#define S50_ELS_KS11_KS11_UKPUK_MASK (0x800U) +#define S50_ELS_KS11_KS11_UKPUK_SHIFT (11U) +#define S50_ELS_KS11_KS11_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKPUK_SHIFT)) & S50_ELS_KS11_KS11_UKPUK_MASK) + +#define S50_ELS_KS11_KS11_UTECDH_MASK (0x1000U) +#define S50_ELS_KS11_KS11_UTECDH_SHIFT (12U) +#define S50_ELS_KS11_KS11_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTECDH_SHIFT)) & S50_ELS_KS11_KS11_UTECDH_MASK) + +#define S50_ELS_KS11_KS11_UCMAC_MASK (0x2000U) +#define S50_ELS_KS11_KS11_UCMAC_SHIFT (13U) +#define S50_ELS_KS11_KS11_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCMAC_SHIFT)) & S50_ELS_KS11_KS11_UCMAC_MASK) + +#define S50_ELS_KS11_KS11_UKSK_MASK (0x4000U) +#define S50_ELS_KS11_KS11_UKSK_SHIFT (14U) +#define S50_ELS_KS11_KS11_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKSK_SHIFT)) & S50_ELS_KS11_KS11_UKSK_MASK) + +#define S50_ELS_KS11_KS11_URTF_MASK (0x8000U) +#define S50_ELS_KS11_KS11_URTF_SHIFT (15U) +#define S50_ELS_KS11_KS11_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_URTF_SHIFT)) & S50_ELS_KS11_KS11_URTF_MASK) + +#define S50_ELS_KS11_KS11_UCKDF_MASK (0x10000U) +#define S50_ELS_KS11_KS11_UCKDF_SHIFT (16U) +#define S50_ELS_KS11_KS11_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCKDF_SHIFT)) & S50_ELS_KS11_KS11_UCKDF_MASK) + +#define S50_ELS_KS11_KS11_UHKDF_MASK (0x20000U) +#define S50_ELS_KS11_KS11_UHKDF_SHIFT (17U) +#define S50_ELS_KS11_KS11_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHKDF_SHIFT)) & S50_ELS_KS11_KS11_UHKDF_MASK) + +#define S50_ELS_KS11_KS11_UECSG_MASK (0x40000U) +#define S50_ELS_KS11_KS11_UECSG_SHIFT (18U) +#define S50_ELS_KS11_KS11_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECSG_SHIFT)) & S50_ELS_KS11_KS11_UECSG_MASK) + +#define S50_ELS_KS11_KS11_UECDH_MASK (0x80000U) +#define S50_ELS_KS11_KS11_UECDH_SHIFT (19U) +#define S50_ELS_KS11_KS11_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECDH_SHIFT)) & S50_ELS_KS11_KS11_UECDH_MASK) + +#define S50_ELS_KS11_KS11_UAES_MASK (0x100000U) +#define S50_ELS_KS11_KS11_UAES_SHIFT (20U) +#define S50_ELS_KS11_KS11_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UAES_SHIFT)) & S50_ELS_KS11_KS11_UAES_MASK) + +#define S50_ELS_KS11_KS11_UHMAC_MASK (0x200000U) +#define S50_ELS_KS11_KS11_UHMAC_SHIFT (21U) +#define S50_ELS_KS11_KS11_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHMAC_SHIFT)) & S50_ELS_KS11_KS11_UHMAC_MASK) + +#define S50_ELS_KS11_KS11_UKWK_MASK (0x400000U) +#define S50_ELS_KS11_KS11_UKWK_SHIFT (22U) +#define S50_ELS_KS11_KS11_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKWK_SHIFT)) & S50_ELS_KS11_KS11_UKWK_MASK) + +#define S50_ELS_KS11_KS11_UKUOK_MASK (0x800000U) +#define S50_ELS_KS11_KS11_UKUOK_SHIFT (23U) +#define S50_ELS_KS11_KS11_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKUOK_SHIFT)) & S50_ELS_KS11_KS11_UKUOK_MASK) + +#define S50_ELS_KS11_KS11_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS11_KS11_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS11_KS11_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSPMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSPMS_MASK) + +#define S50_ELS_KS11_KS11_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS11_KS11_UTLSMS_SHIFT (25U) +#define S50_ELS_KS11_KS11_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSMS_MASK) + +#define S50_ELS_KS11_KS11_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS11_KS11_UKGSRC_SHIFT (26U) +#define S50_ELS_KS11_KS11_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKGSRC_SHIFT)) & S50_ELS_KS11_KS11_UKGSRC_MASK) + +#define S50_ELS_KS11_KS11_UHWO_MASK (0x8000000U) +#define S50_ELS_KS11_KS11_UHWO_SHIFT (27U) +#define S50_ELS_KS11_KS11_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHWO_SHIFT)) & S50_ELS_KS11_KS11_UHWO_MASK) + +#define S50_ELS_KS11_KS11_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS11_KS11_UWRPOK_SHIFT (28U) +#define S50_ELS_KS11_KS11_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UWRPOK_SHIFT)) & S50_ELS_KS11_KS11_UWRPOK_MASK) + +#define S50_ELS_KS11_KS11_UDUK_MASK (0x20000000U) +#define S50_ELS_KS11_KS11_UDUK_SHIFT (29U) +#define S50_ELS_KS11_KS11_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UDUK_SHIFT)) & S50_ELS_KS11_KS11_UDUK_MASK) + +#define S50_ELS_KS11_KS11_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS11_KS11_UPPROT_SHIFT (30U) +#define S50_ELS_KS11_KS11_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UPPROT_SHIFT)) & S50_ELS_KS11_KS11_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS12 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS12_KS12_KSIZE_MASK (0x3U) +#define S50_ELS_KS12_KS12_KSIZE_SHIFT (0U) +/*! KS12_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS12_KS12_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KSIZE_SHIFT)) & S50_ELS_KS12_KS12_KSIZE_MASK) + +#define S50_ELS_KS12_KS12_KACT_MASK (0x20U) +#define S50_ELS_KS12_KS12_KACT_SHIFT (5U) +#define S50_ELS_KS12_KS12_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KACT_SHIFT)) & S50_ELS_KS12_KS12_KACT_MASK) + +#define S50_ELS_KS12_KS12_KBASE_MASK (0x40U) +#define S50_ELS_KS12_KS12_KBASE_SHIFT (6U) +#define S50_ELS_KS12_KS12_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KBASE_SHIFT)) & S50_ELS_KS12_KS12_KBASE_MASK) + +#define S50_ELS_KS12_KS12_FGP_MASK (0x80U) +#define S50_ELS_KS12_KS12_FGP_SHIFT (7U) +#define S50_ELS_KS12_KS12_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FGP_SHIFT)) & S50_ELS_KS12_KS12_FGP_MASK) + +#define S50_ELS_KS12_KS12_FRTN_MASK (0x100U) +#define S50_ELS_KS12_KS12_FRTN_SHIFT (8U) +#define S50_ELS_KS12_KS12_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FRTN_SHIFT)) & S50_ELS_KS12_KS12_FRTN_MASK) + +#define S50_ELS_KS12_KS12_FHWO_MASK (0x200U) +#define S50_ELS_KS12_KS12_FHWO_SHIFT (9U) +#define S50_ELS_KS12_KS12_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FHWO_SHIFT)) & S50_ELS_KS12_KS12_FHWO_MASK) + +#define S50_ELS_KS12_KS12_UKPUK_MASK (0x800U) +#define S50_ELS_KS12_KS12_UKPUK_SHIFT (11U) +#define S50_ELS_KS12_KS12_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKPUK_SHIFT)) & S50_ELS_KS12_KS12_UKPUK_MASK) + +#define S50_ELS_KS12_KS12_UTECDH_MASK (0x1000U) +#define S50_ELS_KS12_KS12_UTECDH_SHIFT (12U) +#define S50_ELS_KS12_KS12_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTECDH_SHIFT)) & S50_ELS_KS12_KS12_UTECDH_MASK) + +#define S50_ELS_KS12_KS12_UCMAC_MASK (0x2000U) +#define S50_ELS_KS12_KS12_UCMAC_SHIFT (13U) +#define S50_ELS_KS12_KS12_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCMAC_SHIFT)) & S50_ELS_KS12_KS12_UCMAC_MASK) + +#define S50_ELS_KS12_KS12_UKSK_MASK (0x4000U) +#define S50_ELS_KS12_KS12_UKSK_SHIFT (14U) +#define S50_ELS_KS12_KS12_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKSK_SHIFT)) & S50_ELS_KS12_KS12_UKSK_MASK) + +#define S50_ELS_KS12_KS12_URTF_MASK (0x8000U) +#define S50_ELS_KS12_KS12_URTF_SHIFT (15U) +#define S50_ELS_KS12_KS12_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_URTF_SHIFT)) & S50_ELS_KS12_KS12_URTF_MASK) + +#define S50_ELS_KS12_KS12_UCKDF_MASK (0x10000U) +#define S50_ELS_KS12_KS12_UCKDF_SHIFT (16U) +#define S50_ELS_KS12_KS12_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCKDF_SHIFT)) & S50_ELS_KS12_KS12_UCKDF_MASK) + +#define S50_ELS_KS12_KS12_UHKDF_MASK (0x20000U) +#define S50_ELS_KS12_KS12_UHKDF_SHIFT (17U) +#define S50_ELS_KS12_KS12_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHKDF_SHIFT)) & S50_ELS_KS12_KS12_UHKDF_MASK) + +#define S50_ELS_KS12_KS12_UECSG_MASK (0x40000U) +#define S50_ELS_KS12_KS12_UECSG_SHIFT (18U) +#define S50_ELS_KS12_KS12_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECSG_SHIFT)) & S50_ELS_KS12_KS12_UECSG_MASK) + +#define S50_ELS_KS12_KS12_UECDH_MASK (0x80000U) +#define S50_ELS_KS12_KS12_UECDH_SHIFT (19U) +#define S50_ELS_KS12_KS12_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECDH_SHIFT)) & S50_ELS_KS12_KS12_UECDH_MASK) + +#define S50_ELS_KS12_KS12_UAES_MASK (0x100000U) +#define S50_ELS_KS12_KS12_UAES_SHIFT (20U) +#define S50_ELS_KS12_KS12_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UAES_SHIFT)) & S50_ELS_KS12_KS12_UAES_MASK) + +#define S50_ELS_KS12_KS12_UHMAC_MASK (0x200000U) +#define S50_ELS_KS12_KS12_UHMAC_SHIFT (21U) +#define S50_ELS_KS12_KS12_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHMAC_SHIFT)) & S50_ELS_KS12_KS12_UHMAC_MASK) + +#define S50_ELS_KS12_KS12_UKWK_MASK (0x400000U) +#define S50_ELS_KS12_KS12_UKWK_SHIFT (22U) +#define S50_ELS_KS12_KS12_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKWK_SHIFT)) & S50_ELS_KS12_KS12_UKWK_MASK) + +#define S50_ELS_KS12_KS12_UKUOK_MASK (0x800000U) +#define S50_ELS_KS12_KS12_UKUOK_SHIFT (23U) +#define S50_ELS_KS12_KS12_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKUOK_SHIFT)) & S50_ELS_KS12_KS12_UKUOK_MASK) + +#define S50_ELS_KS12_KS12_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS12_KS12_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS12_KS12_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSPMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSPMS_MASK) + +#define S50_ELS_KS12_KS12_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS12_KS12_UTLSMS_SHIFT (25U) +#define S50_ELS_KS12_KS12_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSMS_MASK) + +#define S50_ELS_KS12_KS12_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS12_KS12_UKGSRC_SHIFT (26U) +#define S50_ELS_KS12_KS12_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKGSRC_SHIFT)) & S50_ELS_KS12_KS12_UKGSRC_MASK) + +#define S50_ELS_KS12_KS12_UHWO_MASK (0x8000000U) +#define S50_ELS_KS12_KS12_UHWO_SHIFT (27U) +#define S50_ELS_KS12_KS12_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHWO_SHIFT)) & S50_ELS_KS12_KS12_UHWO_MASK) + +#define S50_ELS_KS12_KS12_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS12_KS12_UWRPOK_SHIFT (28U) +#define S50_ELS_KS12_KS12_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UWRPOK_SHIFT)) & S50_ELS_KS12_KS12_UWRPOK_MASK) + +#define S50_ELS_KS12_KS12_UDUK_MASK (0x20000000U) +#define S50_ELS_KS12_KS12_UDUK_SHIFT (29U) +#define S50_ELS_KS12_KS12_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UDUK_SHIFT)) & S50_ELS_KS12_KS12_UDUK_MASK) + +#define S50_ELS_KS12_KS12_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS12_KS12_UPPROT_SHIFT (30U) +#define S50_ELS_KS12_KS12_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UPPROT_SHIFT)) & S50_ELS_KS12_KS12_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS13 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS13_KS13_KSIZE_MASK (0x3U) +#define S50_ELS_KS13_KS13_KSIZE_SHIFT (0U) +/*! KS13_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS13_KS13_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KSIZE_SHIFT)) & S50_ELS_KS13_KS13_KSIZE_MASK) + +#define S50_ELS_KS13_KS13_KACT_MASK (0x20U) +#define S50_ELS_KS13_KS13_KACT_SHIFT (5U) +#define S50_ELS_KS13_KS13_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KACT_SHIFT)) & S50_ELS_KS13_KS13_KACT_MASK) + +#define S50_ELS_KS13_KS13_KBASE_MASK (0x40U) +#define S50_ELS_KS13_KS13_KBASE_SHIFT (6U) +#define S50_ELS_KS13_KS13_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KBASE_SHIFT)) & S50_ELS_KS13_KS13_KBASE_MASK) + +#define S50_ELS_KS13_KS13_FGP_MASK (0x80U) +#define S50_ELS_KS13_KS13_FGP_SHIFT (7U) +#define S50_ELS_KS13_KS13_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FGP_SHIFT)) & S50_ELS_KS13_KS13_FGP_MASK) + +#define S50_ELS_KS13_KS13_FRTN_MASK (0x100U) +#define S50_ELS_KS13_KS13_FRTN_SHIFT (8U) +#define S50_ELS_KS13_KS13_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FRTN_SHIFT)) & S50_ELS_KS13_KS13_FRTN_MASK) + +#define S50_ELS_KS13_KS13_FHWO_MASK (0x200U) +#define S50_ELS_KS13_KS13_FHWO_SHIFT (9U) +#define S50_ELS_KS13_KS13_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FHWO_SHIFT)) & S50_ELS_KS13_KS13_FHWO_MASK) + +#define S50_ELS_KS13_KS13_UKPUK_MASK (0x800U) +#define S50_ELS_KS13_KS13_UKPUK_SHIFT (11U) +#define S50_ELS_KS13_KS13_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKPUK_SHIFT)) & S50_ELS_KS13_KS13_UKPUK_MASK) + +#define S50_ELS_KS13_KS13_UTECDH_MASK (0x1000U) +#define S50_ELS_KS13_KS13_UTECDH_SHIFT (12U) +#define S50_ELS_KS13_KS13_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTECDH_SHIFT)) & S50_ELS_KS13_KS13_UTECDH_MASK) + +#define S50_ELS_KS13_KS13_UCMAC_MASK (0x2000U) +#define S50_ELS_KS13_KS13_UCMAC_SHIFT (13U) +#define S50_ELS_KS13_KS13_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCMAC_SHIFT)) & S50_ELS_KS13_KS13_UCMAC_MASK) + +#define S50_ELS_KS13_KS13_UKSK_MASK (0x4000U) +#define S50_ELS_KS13_KS13_UKSK_SHIFT (14U) +#define S50_ELS_KS13_KS13_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKSK_SHIFT)) & S50_ELS_KS13_KS13_UKSK_MASK) + +#define S50_ELS_KS13_KS13_URTF_MASK (0x8000U) +#define S50_ELS_KS13_KS13_URTF_SHIFT (15U) +#define S50_ELS_KS13_KS13_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_URTF_SHIFT)) & S50_ELS_KS13_KS13_URTF_MASK) + +#define S50_ELS_KS13_KS13_UCKDF_MASK (0x10000U) +#define S50_ELS_KS13_KS13_UCKDF_SHIFT (16U) +#define S50_ELS_KS13_KS13_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCKDF_SHIFT)) & S50_ELS_KS13_KS13_UCKDF_MASK) + +#define S50_ELS_KS13_KS13_UHKDF_MASK (0x20000U) +#define S50_ELS_KS13_KS13_UHKDF_SHIFT (17U) +#define S50_ELS_KS13_KS13_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHKDF_SHIFT)) & S50_ELS_KS13_KS13_UHKDF_MASK) + +#define S50_ELS_KS13_KS13_UECSG_MASK (0x40000U) +#define S50_ELS_KS13_KS13_UECSG_SHIFT (18U) +#define S50_ELS_KS13_KS13_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECSG_SHIFT)) & S50_ELS_KS13_KS13_UECSG_MASK) + +#define S50_ELS_KS13_KS13_UECDH_MASK (0x80000U) +#define S50_ELS_KS13_KS13_UECDH_SHIFT (19U) +#define S50_ELS_KS13_KS13_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECDH_SHIFT)) & S50_ELS_KS13_KS13_UECDH_MASK) + +#define S50_ELS_KS13_KS13_UAES_MASK (0x100000U) +#define S50_ELS_KS13_KS13_UAES_SHIFT (20U) +#define S50_ELS_KS13_KS13_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UAES_SHIFT)) & S50_ELS_KS13_KS13_UAES_MASK) + +#define S50_ELS_KS13_KS13_UHMAC_MASK (0x200000U) +#define S50_ELS_KS13_KS13_UHMAC_SHIFT (21U) +#define S50_ELS_KS13_KS13_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHMAC_SHIFT)) & S50_ELS_KS13_KS13_UHMAC_MASK) + +#define S50_ELS_KS13_KS13_UKWK_MASK (0x400000U) +#define S50_ELS_KS13_KS13_UKWK_SHIFT (22U) +#define S50_ELS_KS13_KS13_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKWK_SHIFT)) & S50_ELS_KS13_KS13_UKWK_MASK) + +#define S50_ELS_KS13_KS13_UKUOK_MASK (0x800000U) +#define S50_ELS_KS13_KS13_UKUOK_SHIFT (23U) +#define S50_ELS_KS13_KS13_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKUOK_SHIFT)) & S50_ELS_KS13_KS13_UKUOK_MASK) + +#define S50_ELS_KS13_KS13_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS13_KS13_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS13_KS13_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSPMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSPMS_MASK) + +#define S50_ELS_KS13_KS13_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS13_KS13_UTLSMS_SHIFT (25U) +#define S50_ELS_KS13_KS13_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSMS_MASK) + +#define S50_ELS_KS13_KS13_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS13_KS13_UKGSRC_SHIFT (26U) +#define S50_ELS_KS13_KS13_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKGSRC_SHIFT)) & S50_ELS_KS13_KS13_UKGSRC_MASK) + +#define S50_ELS_KS13_KS13_UHWO_MASK (0x8000000U) +#define S50_ELS_KS13_KS13_UHWO_SHIFT (27U) +#define S50_ELS_KS13_KS13_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHWO_SHIFT)) & S50_ELS_KS13_KS13_UHWO_MASK) + +#define S50_ELS_KS13_KS13_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS13_KS13_UWRPOK_SHIFT (28U) +#define S50_ELS_KS13_KS13_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UWRPOK_SHIFT)) & S50_ELS_KS13_KS13_UWRPOK_MASK) + +#define S50_ELS_KS13_KS13_UDUK_MASK (0x20000000U) +#define S50_ELS_KS13_KS13_UDUK_SHIFT (29U) +#define S50_ELS_KS13_KS13_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UDUK_SHIFT)) & S50_ELS_KS13_KS13_UDUK_MASK) + +#define S50_ELS_KS13_KS13_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS13_KS13_UPPROT_SHIFT (30U) +#define S50_ELS_KS13_KS13_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UPPROT_SHIFT)) & S50_ELS_KS13_KS13_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS14 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS14_KS14_KSIZE_MASK (0x3U) +#define S50_ELS_KS14_KS14_KSIZE_SHIFT (0U) +/*! KS14_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS14_KS14_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KSIZE_SHIFT)) & S50_ELS_KS14_KS14_KSIZE_MASK) + +#define S50_ELS_KS14_KS14_KACT_MASK (0x20U) +#define S50_ELS_KS14_KS14_KACT_SHIFT (5U) +#define S50_ELS_KS14_KS14_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KACT_SHIFT)) & S50_ELS_KS14_KS14_KACT_MASK) + +#define S50_ELS_KS14_KS14_KBASE_MASK (0x40U) +#define S50_ELS_KS14_KS14_KBASE_SHIFT (6U) +#define S50_ELS_KS14_KS14_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KBASE_SHIFT)) & S50_ELS_KS14_KS14_KBASE_MASK) + +#define S50_ELS_KS14_KS14_FGP_MASK (0x80U) +#define S50_ELS_KS14_KS14_FGP_SHIFT (7U) +#define S50_ELS_KS14_KS14_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FGP_SHIFT)) & S50_ELS_KS14_KS14_FGP_MASK) + +#define S50_ELS_KS14_KS14_FRTN_MASK (0x100U) +#define S50_ELS_KS14_KS14_FRTN_SHIFT (8U) +#define S50_ELS_KS14_KS14_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FRTN_SHIFT)) & S50_ELS_KS14_KS14_FRTN_MASK) + +#define S50_ELS_KS14_KS14_FHWO_MASK (0x200U) +#define S50_ELS_KS14_KS14_FHWO_SHIFT (9U) +#define S50_ELS_KS14_KS14_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FHWO_SHIFT)) & S50_ELS_KS14_KS14_FHWO_MASK) + +#define S50_ELS_KS14_KS14_UKPUK_MASK (0x800U) +#define S50_ELS_KS14_KS14_UKPUK_SHIFT (11U) +#define S50_ELS_KS14_KS14_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKPUK_SHIFT)) & S50_ELS_KS14_KS14_UKPUK_MASK) + +#define S50_ELS_KS14_KS14_UTECDH_MASK (0x1000U) +#define S50_ELS_KS14_KS14_UTECDH_SHIFT (12U) +#define S50_ELS_KS14_KS14_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTECDH_SHIFT)) & S50_ELS_KS14_KS14_UTECDH_MASK) + +#define S50_ELS_KS14_KS14_UCMAC_MASK (0x2000U) +#define S50_ELS_KS14_KS14_UCMAC_SHIFT (13U) +#define S50_ELS_KS14_KS14_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCMAC_SHIFT)) & S50_ELS_KS14_KS14_UCMAC_MASK) + +#define S50_ELS_KS14_KS14_UKSK_MASK (0x4000U) +#define S50_ELS_KS14_KS14_UKSK_SHIFT (14U) +#define S50_ELS_KS14_KS14_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKSK_SHIFT)) & S50_ELS_KS14_KS14_UKSK_MASK) + +#define S50_ELS_KS14_KS14_URTF_MASK (0x8000U) +#define S50_ELS_KS14_KS14_URTF_SHIFT (15U) +#define S50_ELS_KS14_KS14_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_URTF_SHIFT)) & S50_ELS_KS14_KS14_URTF_MASK) + +#define S50_ELS_KS14_KS14_UCKDF_MASK (0x10000U) +#define S50_ELS_KS14_KS14_UCKDF_SHIFT (16U) +#define S50_ELS_KS14_KS14_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCKDF_SHIFT)) & S50_ELS_KS14_KS14_UCKDF_MASK) + +#define S50_ELS_KS14_KS14_UHKDF_MASK (0x20000U) +#define S50_ELS_KS14_KS14_UHKDF_SHIFT (17U) +#define S50_ELS_KS14_KS14_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHKDF_SHIFT)) & S50_ELS_KS14_KS14_UHKDF_MASK) + +#define S50_ELS_KS14_KS14_UECSG_MASK (0x40000U) +#define S50_ELS_KS14_KS14_UECSG_SHIFT (18U) +#define S50_ELS_KS14_KS14_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECSG_SHIFT)) & S50_ELS_KS14_KS14_UECSG_MASK) + +#define S50_ELS_KS14_KS14_UECDH_MASK (0x80000U) +#define S50_ELS_KS14_KS14_UECDH_SHIFT (19U) +#define S50_ELS_KS14_KS14_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECDH_SHIFT)) & S50_ELS_KS14_KS14_UECDH_MASK) + +#define S50_ELS_KS14_KS14_UAES_MASK (0x100000U) +#define S50_ELS_KS14_KS14_UAES_SHIFT (20U) +#define S50_ELS_KS14_KS14_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UAES_SHIFT)) & S50_ELS_KS14_KS14_UAES_MASK) + +#define S50_ELS_KS14_KS14_UHMAC_MASK (0x200000U) +#define S50_ELS_KS14_KS14_UHMAC_SHIFT (21U) +#define S50_ELS_KS14_KS14_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHMAC_SHIFT)) & S50_ELS_KS14_KS14_UHMAC_MASK) + +#define S50_ELS_KS14_KS14_UKWK_MASK (0x400000U) +#define S50_ELS_KS14_KS14_UKWK_SHIFT (22U) +#define S50_ELS_KS14_KS14_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKWK_SHIFT)) & S50_ELS_KS14_KS14_UKWK_MASK) + +#define S50_ELS_KS14_KS14_UKUOK_MASK (0x800000U) +#define S50_ELS_KS14_KS14_UKUOK_SHIFT (23U) +#define S50_ELS_KS14_KS14_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKUOK_SHIFT)) & S50_ELS_KS14_KS14_UKUOK_MASK) + +#define S50_ELS_KS14_KS14_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS14_KS14_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS14_KS14_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSPMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSPMS_MASK) + +#define S50_ELS_KS14_KS14_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS14_KS14_UTLSMS_SHIFT (25U) +#define S50_ELS_KS14_KS14_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSMS_MASK) + +#define S50_ELS_KS14_KS14_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS14_KS14_UKGSRC_SHIFT (26U) +#define S50_ELS_KS14_KS14_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKGSRC_SHIFT)) & S50_ELS_KS14_KS14_UKGSRC_MASK) + +#define S50_ELS_KS14_KS14_UHWO_MASK (0x8000000U) +#define S50_ELS_KS14_KS14_UHWO_SHIFT (27U) +#define S50_ELS_KS14_KS14_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHWO_SHIFT)) & S50_ELS_KS14_KS14_UHWO_MASK) + +#define S50_ELS_KS14_KS14_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS14_KS14_UWRPOK_SHIFT (28U) +#define S50_ELS_KS14_KS14_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UWRPOK_SHIFT)) & S50_ELS_KS14_KS14_UWRPOK_MASK) + +#define S50_ELS_KS14_KS14_UDUK_MASK (0x20000000U) +#define S50_ELS_KS14_KS14_UDUK_SHIFT (29U) +#define S50_ELS_KS14_KS14_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UDUK_SHIFT)) & S50_ELS_KS14_KS14_UDUK_MASK) + +#define S50_ELS_KS14_KS14_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS14_KS14_UPPROT_SHIFT (30U) +#define S50_ELS_KS14_KS14_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UPPROT_SHIFT)) & S50_ELS_KS14_KS14_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS15 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS15_KS15_KSIZE_MASK (0x3U) +#define S50_ELS_KS15_KS15_KSIZE_SHIFT (0U) +/*! KS15_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS15_KS15_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KSIZE_SHIFT)) & S50_ELS_KS15_KS15_KSIZE_MASK) + +#define S50_ELS_KS15_KS15_KACT_MASK (0x20U) +#define S50_ELS_KS15_KS15_KACT_SHIFT (5U) +#define S50_ELS_KS15_KS15_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KACT_SHIFT)) & S50_ELS_KS15_KS15_KACT_MASK) + +#define S50_ELS_KS15_KS15_KBASE_MASK (0x40U) +#define S50_ELS_KS15_KS15_KBASE_SHIFT (6U) +#define S50_ELS_KS15_KS15_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KBASE_SHIFT)) & S50_ELS_KS15_KS15_KBASE_MASK) + +#define S50_ELS_KS15_KS15_FGP_MASK (0x80U) +#define S50_ELS_KS15_KS15_FGP_SHIFT (7U) +#define S50_ELS_KS15_KS15_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FGP_SHIFT)) & S50_ELS_KS15_KS15_FGP_MASK) + +#define S50_ELS_KS15_KS15_FRTN_MASK (0x100U) +#define S50_ELS_KS15_KS15_FRTN_SHIFT (8U) +#define S50_ELS_KS15_KS15_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FRTN_SHIFT)) & S50_ELS_KS15_KS15_FRTN_MASK) + +#define S50_ELS_KS15_KS15_FHWO_MASK (0x200U) +#define S50_ELS_KS15_KS15_FHWO_SHIFT (9U) +#define S50_ELS_KS15_KS15_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FHWO_SHIFT)) & S50_ELS_KS15_KS15_FHWO_MASK) + +#define S50_ELS_KS15_KS15_UKPUK_MASK (0x800U) +#define S50_ELS_KS15_KS15_UKPUK_SHIFT (11U) +#define S50_ELS_KS15_KS15_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKPUK_SHIFT)) & S50_ELS_KS15_KS15_UKPUK_MASK) + +#define S50_ELS_KS15_KS15_UTECDH_MASK (0x1000U) +#define S50_ELS_KS15_KS15_UTECDH_SHIFT (12U) +#define S50_ELS_KS15_KS15_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTECDH_SHIFT)) & S50_ELS_KS15_KS15_UTECDH_MASK) + +#define S50_ELS_KS15_KS15_UCMAC_MASK (0x2000U) +#define S50_ELS_KS15_KS15_UCMAC_SHIFT (13U) +#define S50_ELS_KS15_KS15_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCMAC_SHIFT)) & S50_ELS_KS15_KS15_UCMAC_MASK) + +#define S50_ELS_KS15_KS15_UKSK_MASK (0x4000U) +#define S50_ELS_KS15_KS15_UKSK_SHIFT (14U) +#define S50_ELS_KS15_KS15_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKSK_SHIFT)) & S50_ELS_KS15_KS15_UKSK_MASK) + +#define S50_ELS_KS15_KS15_URTF_MASK (0x8000U) +#define S50_ELS_KS15_KS15_URTF_SHIFT (15U) +#define S50_ELS_KS15_KS15_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_URTF_SHIFT)) & S50_ELS_KS15_KS15_URTF_MASK) + +#define S50_ELS_KS15_KS15_UCKDF_MASK (0x10000U) +#define S50_ELS_KS15_KS15_UCKDF_SHIFT (16U) +#define S50_ELS_KS15_KS15_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCKDF_SHIFT)) & S50_ELS_KS15_KS15_UCKDF_MASK) + +#define S50_ELS_KS15_KS15_UHKDF_MASK (0x20000U) +#define S50_ELS_KS15_KS15_UHKDF_SHIFT (17U) +#define S50_ELS_KS15_KS15_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHKDF_SHIFT)) & S50_ELS_KS15_KS15_UHKDF_MASK) + +#define S50_ELS_KS15_KS15_UECSG_MASK (0x40000U) +#define S50_ELS_KS15_KS15_UECSG_SHIFT (18U) +#define S50_ELS_KS15_KS15_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECSG_SHIFT)) & S50_ELS_KS15_KS15_UECSG_MASK) + +#define S50_ELS_KS15_KS15_UECDH_MASK (0x80000U) +#define S50_ELS_KS15_KS15_UECDH_SHIFT (19U) +#define S50_ELS_KS15_KS15_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECDH_SHIFT)) & S50_ELS_KS15_KS15_UECDH_MASK) + +#define S50_ELS_KS15_KS15_UAES_MASK (0x100000U) +#define S50_ELS_KS15_KS15_UAES_SHIFT (20U) +#define S50_ELS_KS15_KS15_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UAES_SHIFT)) & S50_ELS_KS15_KS15_UAES_MASK) + +#define S50_ELS_KS15_KS15_UHMAC_MASK (0x200000U) +#define S50_ELS_KS15_KS15_UHMAC_SHIFT (21U) +#define S50_ELS_KS15_KS15_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHMAC_SHIFT)) & S50_ELS_KS15_KS15_UHMAC_MASK) + +#define S50_ELS_KS15_KS15_UKWK_MASK (0x400000U) +#define S50_ELS_KS15_KS15_UKWK_SHIFT (22U) +#define S50_ELS_KS15_KS15_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKWK_SHIFT)) & S50_ELS_KS15_KS15_UKWK_MASK) + +#define S50_ELS_KS15_KS15_UKUOK_MASK (0x800000U) +#define S50_ELS_KS15_KS15_UKUOK_SHIFT (23U) +#define S50_ELS_KS15_KS15_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKUOK_SHIFT)) & S50_ELS_KS15_KS15_UKUOK_MASK) + +#define S50_ELS_KS15_KS15_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS15_KS15_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS15_KS15_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSPMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSPMS_MASK) + +#define S50_ELS_KS15_KS15_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS15_KS15_UTLSMS_SHIFT (25U) +#define S50_ELS_KS15_KS15_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSMS_MASK) + +#define S50_ELS_KS15_KS15_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS15_KS15_UKGSRC_SHIFT (26U) +#define S50_ELS_KS15_KS15_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKGSRC_SHIFT)) & S50_ELS_KS15_KS15_UKGSRC_MASK) + +#define S50_ELS_KS15_KS15_UHWO_MASK (0x8000000U) +#define S50_ELS_KS15_KS15_UHWO_SHIFT (27U) +#define S50_ELS_KS15_KS15_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHWO_SHIFT)) & S50_ELS_KS15_KS15_UHWO_MASK) + +#define S50_ELS_KS15_KS15_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS15_KS15_UWRPOK_SHIFT (28U) +#define S50_ELS_KS15_KS15_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UWRPOK_SHIFT)) & S50_ELS_KS15_KS15_UWRPOK_MASK) + +#define S50_ELS_KS15_KS15_UDUK_MASK (0x20000000U) +#define S50_ELS_KS15_KS15_UDUK_SHIFT (29U) +#define S50_ELS_KS15_KS15_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UDUK_SHIFT)) & S50_ELS_KS15_KS15_UDUK_MASK) + +#define S50_ELS_KS15_KS15_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS15_KS15_UPPROT_SHIFT (30U) +#define S50_ELS_KS15_KS15_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UPPROT_SHIFT)) & S50_ELS_KS15_KS15_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS16 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS16_KS16_KSIZE_MASK (0x3U) +#define S50_ELS_KS16_KS16_KSIZE_SHIFT (0U) +/*! KS16_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS16_KS16_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KSIZE_SHIFT)) & S50_ELS_KS16_KS16_KSIZE_MASK) + +#define S50_ELS_KS16_KS16_KACT_MASK (0x20U) +#define S50_ELS_KS16_KS16_KACT_SHIFT (5U) +#define S50_ELS_KS16_KS16_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KACT_SHIFT)) & S50_ELS_KS16_KS16_KACT_MASK) + +#define S50_ELS_KS16_KS16_KBASE_MASK (0x40U) +#define S50_ELS_KS16_KS16_KBASE_SHIFT (6U) +#define S50_ELS_KS16_KS16_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KBASE_SHIFT)) & S50_ELS_KS16_KS16_KBASE_MASK) + +#define S50_ELS_KS16_KS16_FGP_MASK (0x80U) +#define S50_ELS_KS16_KS16_FGP_SHIFT (7U) +#define S50_ELS_KS16_KS16_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FGP_SHIFT)) & S50_ELS_KS16_KS16_FGP_MASK) + +#define S50_ELS_KS16_KS16_FRTN_MASK (0x100U) +#define S50_ELS_KS16_KS16_FRTN_SHIFT (8U) +#define S50_ELS_KS16_KS16_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FRTN_SHIFT)) & S50_ELS_KS16_KS16_FRTN_MASK) + +#define S50_ELS_KS16_KS16_FHWO_MASK (0x200U) +#define S50_ELS_KS16_KS16_FHWO_SHIFT (9U) +#define S50_ELS_KS16_KS16_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FHWO_SHIFT)) & S50_ELS_KS16_KS16_FHWO_MASK) + +#define S50_ELS_KS16_KS16_UKPUK_MASK (0x800U) +#define S50_ELS_KS16_KS16_UKPUK_SHIFT (11U) +#define S50_ELS_KS16_KS16_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKPUK_SHIFT)) & S50_ELS_KS16_KS16_UKPUK_MASK) + +#define S50_ELS_KS16_KS16_UTECDH_MASK (0x1000U) +#define S50_ELS_KS16_KS16_UTECDH_SHIFT (12U) +#define S50_ELS_KS16_KS16_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTECDH_SHIFT)) & S50_ELS_KS16_KS16_UTECDH_MASK) + +#define S50_ELS_KS16_KS16_UCMAC_MASK (0x2000U) +#define S50_ELS_KS16_KS16_UCMAC_SHIFT (13U) +#define S50_ELS_KS16_KS16_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCMAC_SHIFT)) & S50_ELS_KS16_KS16_UCMAC_MASK) + +#define S50_ELS_KS16_KS16_UKSK_MASK (0x4000U) +#define S50_ELS_KS16_KS16_UKSK_SHIFT (14U) +#define S50_ELS_KS16_KS16_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKSK_SHIFT)) & S50_ELS_KS16_KS16_UKSK_MASK) + +#define S50_ELS_KS16_KS16_URTF_MASK (0x8000U) +#define S50_ELS_KS16_KS16_URTF_SHIFT (15U) +#define S50_ELS_KS16_KS16_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_URTF_SHIFT)) & S50_ELS_KS16_KS16_URTF_MASK) + +#define S50_ELS_KS16_KS16_UCKDF_MASK (0x10000U) +#define S50_ELS_KS16_KS16_UCKDF_SHIFT (16U) +#define S50_ELS_KS16_KS16_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCKDF_SHIFT)) & S50_ELS_KS16_KS16_UCKDF_MASK) + +#define S50_ELS_KS16_KS16_UHKDF_MASK (0x20000U) +#define S50_ELS_KS16_KS16_UHKDF_SHIFT (17U) +#define S50_ELS_KS16_KS16_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHKDF_SHIFT)) & S50_ELS_KS16_KS16_UHKDF_MASK) + +#define S50_ELS_KS16_KS16_UECSG_MASK (0x40000U) +#define S50_ELS_KS16_KS16_UECSG_SHIFT (18U) +#define S50_ELS_KS16_KS16_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECSG_SHIFT)) & S50_ELS_KS16_KS16_UECSG_MASK) + +#define S50_ELS_KS16_KS16_UECDH_MASK (0x80000U) +#define S50_ELS_KS16_KS16_UECDH_SHIFT (19U) +#define S50_ELS_KS16_KS16_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECDH_SHIFT)) & S50_ELS_KS16_KS16_UECDH_MASK) + +#define S50_ELS_KS16_KS16_UAES_MASK (0x100000U) +#define S50_ELS_KS16_KS16_UAES_SHIFT (20U) +#define S50_ELS_KS16_KS16_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UAES_SHIFT)) & S50_ELS_KS16_KS16_UAES_MASK) + +#define S50_ELS_KS16_KS16_UHMAC_MASK (0x200000U) +#define S50_ELS_KS16_KS16_UHMAC_SHIFT (21U) +#define S50_ELS_KS16_KS16_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHMAC_SHIFT)) & S50_ELS_KS16_KS16_UHMAC_MASK) + +#define S50_ELS_KS16_KS16_UKWK_MASK (0x400000U) +#define S50_ELS_KS16_KS16_UKWK_SHIFT (22U) +#define S50_ELS_KS16_KS16_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKWK_SHIFT)) & S50_ELS_KS16_KS16_UKWK_MASK) + +#define S50_ELS_KS16_KS16_UKUOK_MASK (0x800000U) +#define S50_ELS_KS16_KS16_UKUOK_SHIFT (23U) +#define S50_ELS_KS16_KS16_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKUOK_SHIFT)) & S50_ELS_KS16_KS16_UKUOK_MASK) + +#define S50_ELS_KS16_KS16_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS16_KS16_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS16_KS16_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSPMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSPMS_MASK) + +#define S50_ELS_KS16_KS16_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS16_KS16_UTLSMS_SHIFT (25U) +#define S50_ELS_KS16_KS16_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSMS_MASK) + +#define S50_ELS_KS16_KS16_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS16_KS16_UKGSRC_SHIFT (26U) +#define S50_ELS_KS16_KS16_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKGSRC_SHIFT)) & S50_ELS_KS16_KS16_UKGSRC_MASK) + +#define S50_ELS_KS16_KS16_UHWO_MASK (0x8000000U) +#define S50_ELS_KS16_KS16_UHWO_SHIFT (27U) +#define S50_ELS_KS16_KS16_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHWO_SHIFT)) & S50_ELS_KS16_KS16_UHWO_MASK) + +#define S50_ELS_KS16_KS16_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS16_KS16_UWRPOK_SHIFT (28U) +#define S50_ELS_KS16_KS16_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UWRPOK_SHIFT)) & S50_ELS_KS16_KS16_UWRPOK_MASK) + +#define S50_ELS_KS16_KS16_UDUK_MASK (0x20000000U) +#define S50_ELS_KS16_KS16_UDUK_SHIFT (29U) +#define S50_ELS_KS16_KS16_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UDUK_SHIFT)) & S50_ELS_KS16_KS16_UDUK_MASK) + +#define S50_ELS_KS16_KS16_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS16_KS16_UPPROT_SHIFT (30U) +#define S50_ELS_KS16_KS16_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UPPROT_SHIFT)) & S50_ELS_KS16_KS16_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS17 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS17_KS17_KSIZE_MASK (0x3U) +#define S50_ELS_KS17_KS17_KSIZE_SHIFT (0U) +/*! KS17_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS17_KS17_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KSIZE_SHIFT)) & S50_ELS_KS17_KS17_KSIZE_MASK) + +#define S50_ELS_KS17_KS17_KACT_MASK (0x20U) +#define S50_ELS_KS17_KS17_KACT_SHIFT (5U) +#define S50_ELS_KS17_KS17_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KACT_SHIFT)) & S50_ELS_KS17_KS17_KACT_MASK) + +#define S50_ELS_KS17_KS17_KBASE_MASK (0x40U) +#define S50_ELS_KS17_KS17_KBASE_SHIFT (6U) +#define S50_ELS_KS17_KS17_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KBASE_SHIFT)) & S50_ELS_KS17_KS17_KBASE_MASK) + +#define S50_ELS_KS17_KS17_FGP_MASK (0x80U) +#define S50_ELS_KS17_KS17_FGP_SHIFT (7U) +#define S50_ELS_KS17_KS17_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FGP_SHIFT)) & S50_ELS_KS17_KS17_FGP_MASK) + +#define S50_ELS_KS17_KS17_FRTN_MASK (0x100U) +#define S50_ELS_KS17_KS17_FRTN_SHIFT (8U) +#define S50_ELS_KS17_KS17_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FRTN_SHIFT)) & S50_ELS_KS17_KS17_FRTN_MASK) + +#define S50_ELS_KS17_KS17_FHWO_MASK (0x200U) +#define S50_ELS_KS17_KS17_FHWO_SHIFT (9U) +#define S50_ELS_KS17_KS17_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FHWO_SHIFT)) & S50_ELS_KS17_KS17_FHWO_MASK) + +#define S50_ELS_KS17_KS17_UKPUK_MASK (0x800U) +#define S50_ELS_KS17_KS17_UKPUK_SHIFT (11U) +#define S50_ELS_KS17_KS17_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKPUK_SHIFT)) & S50_ELS_KS17_KS17_UKPUK_MASK) + +#define S50_ELS_KS17_KS17_UTECDH_MASK (0x1000U) +#define S50_ELS_KS17_KS17_UTECDH_SHIFT (12U) +#define S50_ELS_KS17_KS17_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTECDH_SHIFT)) & S50_ELS_KS17_KS17_UTECDH_MASK) + +#define S50_ELS_KS17_KS17_UCMAC_MASK (0x2000U) +#define S50_ELS_KS17_KS17_UCMAC_SHIFT (13U) +#define S50_ELS_KS17_KS17_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCMAC_SHIFT)) & S50_ELS_KS17_KS17_UCMAC_MASK) + +#define S50_ELS_KS17_KS17_UKSK_MASK (0x4000U) +#define S50_ELS_KS17_KS17_UKSK_SHIFT (14U) +#define S50_ELS_KS17_KS17_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKSK_SHIFT)) & S50_ELS_KS17_KS17_UKSK_MASK) + +#define S50_ELS_KS17_KS17_URTF_MASK (0x8000U) +#define S50_ELS_KS17_KS17_URTF_SHIFT (15U) +#define S50_ELS_KS17_KS17_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_URTF_SHIFT)) & S50_ELS_KS17_KS17_URTF_MASK) + +#define S50_ELS_KS17_KS17_UCKDF_MASK (0x10000U) +#define S50_ELS_KS17_KS17_UCKDF_SHIFT (16U) +#define S50_ELS_KS17_KS17_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCKDF_SHIFT)) & S50_ELS_KS17_KS17_UCKDF_MASK) + +#define S50_ELS_KS17_KS17_UHKDF_MASK (0x20000U) +#define S50_ELS_KS17_KS17_UHKDF_SHIFT (17U) +#define S50_ELS_KS17_KS17_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHKDF_SHIFT)) & S50_ELS_KS17_KS17_UHKDF_MASK) + +#define S50_ELS_KS17_KS17_UECSG_MASK (0x40000U) +#define S50_ELS_KS17_KS17_UECSG_SHIFT (18U) +#define S50_ELS_KS17_KS17_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECSG_SHIFT)) & S50_ELS_KS17_KS17_UECSG_MASK) + +#define S50_ELS_KS17_KS17_UECDH_MASK (0x80000U) +#define S50_ELS_KS17_KS17_UECDH_SHIFT (19U) +#define S50_ELS_KS17_KS17_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECDH_SHIFT)) & S50_ELS_KS17_KS17_UECDH_MASK) + +#define S50_ELS_KS17_KS17_UAES_MASK (0x100000U) +#define S50_ELS_KS17_KS17_UAES_SHIFT (20U) +#define S50_ELS_KS17_KS17_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UAES_SHIFT)) & S50_ELS_KS17_KS17_UAES_MASK) + +#define S50_ELS_KS17_KS17_UHMAC_MASK (0x200000U) +#define S50_ELS_KS17_KS17_UHMAC_SHIFT (21U) +#define S50_ELS_KS17_KS17_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHMAC_SHIFT)) & S50_ELS_KS17_KS17_UHMAC_MASK) + +#define S50_ELS_KS17_KS17_UKWK_MASK (0x400000U) +#define S50_ELS_KS17_KS17_UKWK_SHIFT (22U) +#define S50_ELS_KS17_KS17_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKWK_SHIFT)) & S50_ELS_KS17_KS17_UKWK_MASK) + +#define S50_ELS_KS17_KS17_UKUOK_MASK (0x800000U) +#define S50_ELS_KS17_KS17_UKUOK_SHIFT (23U) +#define S50_ELS_KS17_KS17_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKUOK_SHIFT)) & S50_ELS_KS17_KS17_UKUOK_MASK) + +#define S50_ELS_KS17_KS17_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS17_KS17_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS17_KS17_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSPMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSPMS_MASK) + +#define S50_ELS_KS17_KS17_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS17_KS17_UTLSMS_SHIFT (25U) +#define S50_ELS_KS17_KS17_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSMS_MASK) + +#define S50_ELS_KS17_KS17_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS17_KS17_UKGSRC_SHIFT (26U) +#define S50_ELS_KS17_KS17_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKGSRC_SHIFT)) & S50_ELS_KS17_KS17_UKGSRC_MASK) + +#define S50_ELS_KS17_KS17_UHWO_MASK (0x8000000U) +#define S50_ELS_KS17_KS17_UHWO_SHIFT (27U) +#define S50_ELS_KS17_KS17_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHWO_SHIFT)) & S50_ELS_KS17_KS17_UHWO_MASK) + +#define S50_ELS_KS17_KS17_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS17_KS17_UWRPOK_SHIFT (28U) +#define S50_ELS_KS17_KS17_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UWRPOK_SHIFT)) & S50_ELS_KS17_KS17_UWRPOK_MASK) + +#define S50_ELS_KS17_KS17_UDUK_MASK (0x20000000U) +#define S50_ELS_KS17_KS17_UDUK_SHIFT (29U) +#define S50_ELS_KS17_KS17_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UDUK_SHIFT)) & S50_ELS_KS17_KS17_UDUK_MASK) + +#define S50_ELS_KS17_KS17_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS17_KS17_UPPROT_SHIFT (30U) +#define S50_ELS_KS17_KS17_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UPPROT_SHIFT)) & S50_ELS_KS17_KS17_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS18 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS18_KS18_KSIZE_MASK (0x3U) +#define S50_ELS_KS18_KS18_KSIZE_SHIFT (0U) +/*! KS18_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS18_KS18_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KSIZE_SHIFT)) & S50_ELS_KS18_KS18_KSIZE_MASK) + +#define S50_ELS_KS18_KS18_KACT_MASK (0x20U) +#define S50_ELS_KS18_KS18_KACT_SHIFT (5U) +#define S50_ELS_KS18_KS18_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KACT_SHIFT)) & S50_ELS_KS18_KS18_KACT_MASK) + +#define S50_ELS_KS18_KS18_KBASE_MASK (0x40U) +#define S50_ELS_KS18_KS18_KBASE_SHIFT (6U) +#define S50_ELS_KS18_KS18_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KBASE_SHIFT)) & S50_ELS_KS18_KS18_KBASE_MASK) + +#define S50_ELS_KS18_KS18_FGP_MASK (0x80U) +#define S50_ELS_KS18_KS18_FGP_SHIFT (7U) +#define S50_ELS_KS18_KS18_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FGP_SHIFT)) & S50_ELS_KS18_KS18_FGP_MASK) + +#define S50_ELS_KS18_KS18_FRTN_MASK (0x100U) +#define S50_ELS_KS18_KS18_FRTN_SHIFT (8U) +#define S50_ELS_KS18_KS18_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FRTN_SHIFT)) & S50_ELS_KS18_KS18_FRTN_MASK) + +#define S50_ELS_KS18_KS18_FHWO_MASK (0x200U) +#define S50_ELS_KS18_KS18_FHWO_SHIFT (9U) +#define S50_ELS_KS18_KS18_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FHWO_SHIFT)) & S50_ELS_KS18_KS18_FHWO_MASK) + +#define S50_ELS_KS18_KS18_UKPUK_MASK (0x800U) +#define S50_ELS_KS18_KS18_UKPUK_SHIFT (11U) +#define S50_ELS_KS18_KS18_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKPUK_SHIFT)) & S50_ELS_KS18_KS18_UKPUK_MASK) + +#define S50_ELS_KS18_KS18_UTECDH_MASK (0x1000U) +#define S50_ELS_KS18_KS18_UTECDH_SHIFT (12U) +#define S50_ELS_KS18_KS18_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTECDH_SHIFT)) & S50_ELS_KS18_KS18_UTECDH_MASK) + +#define S50_ELS_KS18_KS18_UCMAC_MASK (0x2000U) +#define S50_ELS_KS18_KS18_UCMAC_SHIFT (13U) +#define S50_ELS_KS18_KS18_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCMAC_SHIFT)) & S50_ELS_KS18_KS18_UCMAC_MASK) + +#define S50_ELS_KS18_KS18_UKSK_MASK (0x4000U) +#define S50_ELS_KS18_KS18_UKSK_SHIFT (14U) +#define S50_ELS_KS18_KS18_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKSK_SHIFT)) & S50_ELS_KS18_KS18_UKSK_MASK) + +#define S50_ELS_KS18_KS18_URTF_MASK (0x8000U) +#define S50_ELS_KS18_KS18_URTF_SHIFT (15U) +#define S50_ELS_KS18_KS18_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_URTF_SHIFT)) & S50_ELS_KS18_KS18_URTF_MASK) + +#define S50_ELS_KS18_KS18_UCKDF_MASK (0x10000U) +#define S50_ELS_KS18_KS18_UCKDF_SHIFT (16U) +#define S50_ELS_KS18_KS18_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCKDF_SHIFT)) & S50_ELS_KS18_KS18_UCKDF_MASK) + +#define S50_ELS_KS18_KS18_UHKDF_MASK (0x20000U) +#define S50_ELS_KS18_KS18_UHKDF_SHIFT (17U) +#define S50_ELS_KS18_KS18_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHKDF_SHIFT)) & S50_ELS_KS18_KS18_UHKDF_MASK) + +#define S50_ELS_KS18_KS18_UECSG_MASK (0x40000U) +#define S50_ELS_KS18_KS18_UECSG_SHIFT (18U) +#define S50_ELS_KS18_KS18_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECSG_SHIFT)) & S50_ELS_KS18_KS18_UECSG_MASK) + +#define S50_ELS_KS18_KS18_UECDH_MASK (0x80000U) +#define S50_ELS_KS18_KS18_UECDH_SHIFT (19U) +#define S50_ELS_KS18_KS18_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECDH_SHIFT)) & S50_ELS_KS18_KS18_UECDH_MASK) + +#define S50_ELS_KS18_KS18_UAES_MASK (0x100000U) +#define S50_ELS_KS18_KS18_UAES_SHIFT (20U) +#define S50_ELS_KS18_KS18_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UAES_SHIFT)) & S50_ELS_KS18_KS18_UAES_MASK) + +#define S50_ELS_KS18_KS18_UHMAC_MASK (0x200000U) +#define S50_ELS_KS18_KS18_UHMAC_SHIFT (21U) +#define S50_ELS_KS18_KS18_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHMAC_SHIFT)) & S50_ELS_KS18_KS18_UHMAC_MASK) + +#define S50_ELS_KS18_KS18_UKWK_MASK (0x400000U) +#define S50_ELS_KS18_KS18_UKWK_SHIFT (22U) +#define S50_ELS_KS18_KS18_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKWK_SHIFT)) & S50_ELS_KS18_KS18_UKWK_MASK) + +#define S50_ELS_KS18_KS18_UKUOK_MASK (0x800000U) +#define S50_ELS_KS18_KS18_UKUOK_SHIFT (23U) +#define S50_ELS_KS18_KS18_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKUOK_SHIFT)) & S50_ELS_KS18_KS18_UKUOK_MASK) + +#define S50_ELS_KS18_KS18_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS18_KS18_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS18_KS18_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSPMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSPMS_MASK) + +#define S50_ELS_KS18_KS18_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS18_KS18_UTLSMS_SHIFT (25U) +#define S50_ELS_KS18_KS18_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSMS_MASK) + +#define S50_ELS_KS18_KS18_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS18_KS18_UKGSRC_SHIFT (26U) +#define S50_ELS_KS18_KS18_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKGSRC_SHIFT)) & S50_ELS_KS18_KS18_UKGSRC_MASK) + +#define S50_ELS_KS18_KS18_UHWO_MASK (0x8000000U) +#define S50_ELS_KS18_KS18_UHWO_SHIFT (27U) +#define S50_ELS_KS18_KS18_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHWO_SHIFT)) & S50_ELS_KS18_KS18_UHWO_MASK) + +#define S50_ELS_KS18_KS18_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS18_KS18_UWRPOK_SHIFT (28U) +#define S50_ELS_KS18_KS18_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UWRPOK_SHIFT)) & S50_ELS_KS18_KS18_UWRPOK_MASK) + +#define S50_ELS_KS18_KS18_UDUK_MASK (0x20000000U) +#define S50_ELS_KS18_KS18_UDUK_SHIFT (29U) +#define S50_ELS_KS18_KS18_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UDUK_SHIFT)) & S50_ELS_KS18_KS18_UDUK_MASK) + +#define S50_ELS_KS18_KS18_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS18_KS18_UPPROT_SHIFT (30U) +#define S50_ELS_KS18_KS18_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UPPROT_SHIFT)) & S50_ELS_KS18_KS18_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS19 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS19_KS19_KSIZE_MASK (0x3U) +#define S50_ELS_KS19_KS19_KSIZE_SHIFT (0U) +/*! KS19_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS19_KS19_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KSIZE_SHIFT)) & S50_ELS_KS19_KS19_KSIZE_MASK) + +#define S50_ELS_KS19_KS19_KACT_MASK (0x20U) +#define S50_ELS_KS19_KS19_KACT_SHIFT (5U) +#define S50_ELS_KS19_KS19_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KACT_SHIFT)) & S50_ELS_KS19_KS19_KACT_MASK) + +#define S50_ELS_KS19_KS19_KBASE_MASK (0x40U) +#define S50_ELS_KS19_KS19_KBASE_SHIFT (6U) +#define S50_ELS_KS19_KS19_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KBASE_SHIFT)) & S50_ELS_KS19_KS19_KBASE_MASK) + +#define S50_ELS_KS19_KS19_FGP_MASK (0x80U) +#define S50_ELS_KS19_KS19_FGP_SHIFT (7U) +#define S50_ELS_KS19_KS19_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FGP_SHIFT)) & S50_ELS_KS19_KS19_FGP_MASK) + +#define S50_ELS_KS19_KS19_FRTN_MASK (0x100U) +#define S50_ELS_KS19_KS19_FRTN_SHIFT (8U) +#define S50_ELS_KS19_KS19_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FRTN_SHIFT)) & S50_ELS_KS19_KS19_FRTN_MASK) + +#define S50_ELS_KS19_KS19_FHWO_MASK (0x200U) +#define S50_ELS_KS19_KS19_FHWO_SHIFT (9U) +#define S50_ELS_KS19_KS19_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FHWO_SHIFT)) & S50_ELS_KS19_KS19_FHWO_MASK) + +#define S50_ELS_KS19_KS19_UKPUK_MASK (0x800U) +#define S50_ELS_KS19_KS19_UKPUK_SHIFT (11U) +#define S50_ELS_KS19_KS19_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKPUK_SHIFT)) & S50_ELS_KS19_KS19_UKPUK_MASK) + +#define S50_ELS_KS19_KS19_UTECDH_MASK (0x1000U) +#define S50_ELS_KS19_KS19_UTECDH_SHIFT (12U) +#define S50_ELS_KS19_KS19_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTECDH_SHIFT)) & S50_ELS_KS19_KS19_UTECDH_MASK) + +#define S50_ELS_KS19_KS19_UCMAC_MASK (0x2000U) +#define S50_ELS_KS19_KS19_UCMAC_SHIFT (13U) +#define S50_ELS_KS19_KS19_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCMAC_SHIFT)) & S50_ELS_KS19_KS19_UCMAC_MASK) + +#define S50_ELS_KS19_KS19_UKSK_MASK (0x4000U) +#define S50_ELS_KS19_KS19_UKSK_SHIFT (14U) +#define S50_ELS_KS19_KS19_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKSK_SHIFT)) & S50_ELS_KS19_KS19_UKSK_MASK) + +#define S50_ELS_KS19_KS19_URTF_MASK (0x8000U) +#define S50_ELS_KS19_KS19_URTF_SHIFT (15U) +#define S50_ELS_KS19_KS19_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_URTF_SHIFT)) & S50_ELS_KS19_KS19_URTF_MASK) + +#define S50_ELS_KS19_KS19_UCKDF_MASK (0x10000U) +#define S50_ELS_KS19_KS19_UCKDF_SHIFT (16U) +#define S50_ELS_KS19_KS19_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCKDF_SHIFT)) & S50_ELS_KS19_KS19_UCKDF_MASK) + +#define S50_ELS_KS19_KS19_UHKDF_MASK (0x20000U) +#define S50_ELS_KS19_KS19_UHKDF_SHIFT (17U) +#define S50_ELS_KS19_KS19_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHKDF_SHIFT)) & S50_ELS_KS19_KS19_UHKDF_MASK) + +#define S50_ELS_KS19_KS19_UECSG_MASK (0x40000U) +#define S50_ELS_KS19_KS19_UECSG_SHIFT (18U) +#define S50_ELS_KS19_KS19_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECSG_SHIFT)) & S50_ELS_KS19_KS19_UECSG_MASK) + +#define S50_ELS_KS19_KS19_UECDH_MASK (0x80000U) +#define S50_ELS_KS19_KS19_UECDH_SHIFT (19U) +#define S50_ELS_KS19_KS19_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECDH_SHIFT)) & S50_ELS_KS19_KS19_UECDH_MASK) + +#define S50_ELS_KS19_KS19_UAES_MASK (0x100000U) +#define S50_ELS_KS19_KS19_UAES_SHIFT (20U) +#define S50_ELS_KS19_KS19_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UAES_SHIFT)) & S50_ELS_KS19_KS19_UAES_MASK) + +#define S50_ELS_KS19_KS19_UHMAC_MASK (0x200000U) +#define S50_ELS_KS19_KS19_UHMAC_SHIFT (21U) +#define S50_ELS_KS19_KS19_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHMAC_SHIFT)) & S50_ELS_KS19_KS19_UHMAC_MASK) + +#define S50_ELS_KS19_KS19_UKWK_MASK (0x400000U) +#define S50_ELS_KS19_KS19_UKWK_SHIFT (22U) +#define S50_ELS_KS19_KS19_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKWK_SHIFT)) & S50_ELS_KS19_KS19_UKWK_MASK) + +#define S50_ELS_KS19_KS19_UKUOK_MASK (0x800000U) +#define S50_ELS_KS19_KS19_UKUOK_SHIFT (23U) +#define S50_ELS_KS19_KS19_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKUOK_SHIFT)) & S50_ELS_KS19_KS19_UKUOK_MASK) + +#define S50_ELS_KS19_KS19_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS19_KS19_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS19_KS19_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSPMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSPMS_MASK) + +#define S50_ELS_KS19_KS19_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS19_KS19_UTLSMS_SHIFT (25U) +#define S50_ELS_KS19_KS19_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSMS_MASK) + +#define S50_ELS_KS19_KS19_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS19_KS19_UKGSRC_SHIFT (26U) +#define S50_ELS_KS19_KS19_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKGSRC_SHIFT)) & S50_ELS_KS19_KS19_UKGSRC_MASK) + +#define S50_ELS_KS19_KS19_UHWO_MASK (0x8000000U) +#define S50_ELS_KS19_KS19_UHWO_SHIFT (27U) +#define S50_ELS_KS19_KS19_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHWO_SHIFT)) & S50_ELS_KS19_KS19_UHWO_MASK) + +#define S50_ELS_KS19_KS19_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS19_KS19_UWRPOK_SHIFT (28U) +#define S50_ELS_KS19_KS19_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UWRPOK_SHIFT)) & S50_ELS_KS19_KS19_UWRPOK_MASK) + +#define S50_ELS_KS19_KS19_UDUK_MASK (0x20000000U) +#define S50_ELS_KS19_KS19_UDUK_SHIFT (29U) +#define S50_ELS_KS19_KS19_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UDUK_SHIFT)) & S50_ELS_KS19_KS19_UDUK_MASK) + +#define S50_ELS_KS19_KS19_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS19_KS19_UPPROT_SHIFT (30U) +#define S50_ELS_KS19_KS19_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UPPROT_SHIFT)) & S50_ELS_KS19_KS19_UPPROT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group S50_Register_Masks */ + + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group S50_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */ + __IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */ + __IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */ + uint8_t RESERVED_9[228]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */ + uint8_t RESERVED_10[252]; + __IO uint32_t APLLCSR; /**< APLL Control Status Register, offset: 0x500 */ + __IO uint32_t APLLCTRL; /**< APLL Control Register, offset: 0x504 */ + __I uint32_t APLLSTAT; /**< APLL Status Register, offset: 0x508 */ + __IO uint32_t APLLNDIV; /**< APLL N Divider Register, offset: 0x50C */ + __IO uint32_t APLLMDIV; /**< APLL M Divider Register, offset: 0x510 */ + __IO uint32_t APLLPDIV; /**< APLL P Divider Register, offset: 0x514 */ + __IO uint32_t APLLLOCK_CNFG; /**< APLL LOCK Configuration Register, offset: 0x518 */ + uint8_t RESERVED_11[4]; + __I uint32_t APLLSSCGSTAT; /**< APLL SSCG Status Register, offset: 0x520 */ + __IO uint32_t APLLSSCG0; /**< APLL Spread Spectrum Control 0 Register, offset: 0x524 */ + __IO uint32_t APLLSSCG1; /**< APLL Spread Spectrum Control 1 Register, offset: 0x528 */ + uint8_t RESERVED_12[200]; + __IO uint32_t APLL_OVRD; /**< APLL Override Register, offset: 0x5F4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SPLLCSR; /**< SPLL Control Status Register, offset: 0x600 */ + __IO uint32_t SPLLCTRL; /**< SPLL Control Register, offset: 0x604 */ + __I uint32_t SPLLSTAT; /**< SPLL Status Register, offset: 0x608 */ + __IO uint32_t SPLLNDIV; /**< SPLL N Divider Register, offset: 0x60C */ + __IO uint32_t SPLLMDIV; /**< SPLL M Divider Register, offset: 0x610 */ + __IO uint32_t SPLLPDIV; /**< SPLL P Divider Register, offset: 0x614 */ + __IO uint32_t SPLLLOCK_CNFG; /**< SPLL LOCK Configuration Register, offset: 0x618 */ + uint8_t RESERVED_14[4]; + __I uint32_t SPLLSSCGSTAT; /**< SPLL SSCG Status Register, offset: 0x620 */ + __IO uint32_t SPLLSSCG0; /**< SPLL Spread Spectrum Control 0 Register, offset: 0x624 */ + __IO uint32_t SPLLSSCG1; /**< SPLL Spread Spectrum Control 1 Register, offset: 0x628 */ + uint8_t RESERVED_15[200]; + __IO uint32_t SPLL_OVRD; /**< SPLL Override Register, offset: 0x6F4 */ + uint8_t RESERVED_16[8]; + __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ + uint8_t RESERVED_17[252]; + __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ + uint8_t RESERVED_18[252]; + __IO uint32_t TROCSR; /**< TRO Control Status Register, offset: 0x900 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b1..SOSC clock source is present + * 0b0..SOSC clock source is not present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b1..SIRC clock source is present + * 0b0..SIRC clock source is not present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b1..FIRC clock source is present + * 0b0..FIRC clock source is not present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b1..ROSC clock source is present + * 0b0..ROSC clock source is not present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) + +#define SCG_PARAM_APLLCLKPRES_MASK (0x20U) +#define SCG_PARAM_APLLCLKPRES_SHIFT (5U) +/*! APLLCLKPRES - APLL Clock Present + * 0b1..APLL clock source is present + * 0b0..APLL clock source is not present + */ +#define SCG_PARAM_APLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_APLLCLKPRES_SHIFT)) & SCG_PARAM_APLLCLKPRES_MASK) + +#define SCG_PARAM_SPLLCLKPRES_MASK (0x40U) +#define SCG_PARAM_SPLLCLKPRES_SHIFT (6U) +/*! SPLLCLKPRES - SPLL Clock Present + * 0b1..SPLL clock source is present + * 0b0..SPLL clock source is not present + */ +#define SCG_PARAM_SPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK) + +#define SCG_PARAM_UPLLCLKPRES_MASK (0x80U) +#define SCG_PARAM_UPLLCLKPRES_SHIFT (7U) +/*! UPLLCLKPRES - UPLL Clock Present + * 0b1..UPLL clock source is present + * 0b0..UPLL clock source is not present + */ +#define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) + +#define SCG_PARAM_TROCLKPRES_MASK (0x100U) +#define SCG_PARAM_TROCLKPRES_SHIFT (8U) +/*! TROCLKPRES - TRO Clock Present + * 0b1..TRO clock source is present + * 0b0..TRO clock source is not present + */ +#define SCG_PARAM_TROCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_TROCLKPRES_SHIFT)) & SCG_PARAM_TROCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock register */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim registers are locked and not writable. + * 0b1..SCG Trim registers are unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status Register */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0xF000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control Register */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0xF000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status Register */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration Register */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. LDO can be disabled in this case. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 16-20 MHz. + * 0b01..Frequency range select of 20-30 MHz. + * 0b10..Frequency range select of 30-50 MHz. + * 0b11..Frequency range select of 50-66 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status Register */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC coarse auto-trim is not bypassed + * 0b1..SIRC coarse auto-trim is bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC (32.768 kHz) + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Predivider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status Register */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable + * 0b0..FIRC 48 MHz to peripherals is disabled + * 0b1..FIRC 48 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FIRC 144 MHz Clock to peripherals Enable + * 0b0..FIRC 144 MHz to peripherals is disabled + * 0b1..FIRC 144 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) +#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) +/*! FIRCTREN - FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1) + * 0b0..Disables trimming FIRC to an external clock source + * 0b1..Enables trimming FIRC to an external clock source + */ +#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) + +#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) +#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) +/*! FIRCTRUP - FIRC Trim Update + * 0b0..Disables FIRC trimming updates + * 0b1..Enables FIRC trimming updates + */ +#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) + +#define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - FIRC TRIM LOCK + * 0b0..FIRC auto trim not locked to target frequency range + * 0b1..FIRC auto trim locked to target frequency range + */ +#define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK) + +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..FIRC coarse auto trim is not bypassed + * 0b1..FIRC coarse auto trim is bypassed + */ +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz + * (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration Register */ +/*! @{ */ + +#define SCG_FIRCCFG_RANGE_MASK (0x1U) +#define SCG_FIRCCFG_RANGE_SHIFT (0U) +/*! RANGE - Frequency Range + * 0b0..48 MHz FIRC clock selected + * 0b1..144 MHz FIRC clock selected + */ +#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) +/*! @} */ + +/*! @name FIRCTCFG - FIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..USB0 Start of Frame (1 kHz). This option does not use TRIMDIV + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC + */ +#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) + +#define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - FIRC Trim Predivider */ +#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim Register */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP_MASK (0x30000U) +#define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) +/*! TRIMTEMP - Trim Temperature */ +#define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name FIRCSTAT - FIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) + +#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status Register */ +/*! @{ */ + +#define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) +#define SCG_ROSCCSR_ROSCCM_SHIFT (16U) +/*! ROSCCM - ROSC Clock Monitor + * 0b0..ROSC clock monitor is disabled + * 0b1..ROSC clock monitor is enabled + */ +#define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) + +#define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) +#define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) +/*! ROSCCMRE - ROSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock Monitor is disabled or has not detected an error + * 0b1..ROSC Clock Monitor is enabled and detected an RTC loss of clock error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + +/*! @name APLLCSR - APLL Control Status Register */ +/*! @{ */ + +#define SCG_APLLCSR_APLLPWREN_MASK (0x1U) +#define SCG_APLLCSR_APLLPWREN_SHIFT (0U) +/*! APLLPWREN - APLL Power Enable + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLLCSR_APLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLPWREN_SHIFT)) & SCG_APLLCSR_APLLPWREN_MASK) + +#define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) +#define SCG_APLLCSR_APLLCLKEN_SHIFT (1U) +/*! APLLCLKEN - APLL Clock Enable + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLLCSR_APLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK) + +#define SCG_APLLCSR_APLLSTEN_MASK (0x4U) +#define SCG_APLLCSR_APLLSTEN_SHIFT (2U) +/*! APLLSTEN - APLL Stop Enable + * 0b0..APLL is disabled in Deep Sleep mode + * 0b1..APLL is enabled in Deep Sleep mode + */ +#define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) + +#define SCG_APLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_APLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_APLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_APLLCSR_APLLCM_MASK (0x10000U) +#define SCG_APLLCSR_APLLCM_SHIFT (16U) +/*! APLLCM - APLL Clock Monitor + * 0b0..APLL Clock Monitor is disabled + * 0b1..APLL Clock Monitor is enabled + */ +#define SCG_APLLCSR_APLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCM_SHIFT)) & SCG_APLLCSR_APLLCM_MASK) + +#define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) +#define SCG_APLLCSR_APLLCMRE_SHIFT (17U) +/*! APLLCMRE - APLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_APLLCSR_APLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK) + +#define SCG_APLLCSR_LK_MASK (0x800000U) +#define SCG_APLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_APLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK) + +#define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) +#define SCG_APLLCSR_APLL_LOCK_SHIFT (24U) +/*! APLL_LOCK - APLL LOCK + * 0b0..APLL is not powered on or not locked + * 0b1..APLL is locked + */ +#define SCG_APLLCSR_APLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK) + +#define SCG_APLLCSR_APLLSEL_MASK (0x2000000U) +#define SCG_APLLCSR_APLLSEL_SHIFT (25U) +/*! APLLSEL - APLL Selected + * 0b0..APLL is not the system clock source + * 0b1..APLL is the system clock source + */ +#define SCG_APLLCSR_APLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK) + +#define SCG_APLLCSR_APLLERR_MASK (0x4000000U) +#define SCG_APLLCSR_APLLERR_SHIFT (26U) +/*! APLLERR - APLL Clock Error + * 0b0..APLL Clock Monitor is disabled or has not detected an error + * 0b1..APLL Clock Monitor is enabled and detected an error + */ +#define SCG_APLLCSR_APLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLERR_SHIFT)) & SCG_APLLCSR_APLLERR_MASK) + +#define SCG_APLLCSR_APLL_LOCK_IE_MASK (0x40000000U) +#define SCG_APLLCSR_APLL_LOCK_IE_SHIFT (30U) +/*! APLL_LOCK_IE - APLL LOCK Interrupt Enable + * 0b0..APLL_LOCK interrupt is not enabled + * 0b1..APLL_LOCK interrupt is enabled + */ +#define SCG_APLLCSR_APLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_IE_SHIFT)) & SCG_APLLCSR_APLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name APLLCTRL - APLL Control Register */ +/*! @{ */ + +#define SCG_APLLCTRL_SELR_MASK (0xFU) +#define SCG_APLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_APLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELR_SHIFT)) & SCG_APLLCTRL_SELR_MASK) + +#define SCG_APLLCTRL_SELI_MASK (0x3F0U) +#define SCG_APLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_APLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELI_SHIFT)) & SCG_APLLCTRL_SELI_MASK) + +#define SCG_APLLCTRL_SELP_MASK (0x7C00U) +#define SCG_APLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_APLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELP_SHIFT)) & SCG_APLLCTRL_SELP_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_APLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_APLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_APLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_LIMUPOFF_SHIFT)) & SCG_APLLCTRL_LIMUPOFF_MASK) + +#define SCG_APLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_APLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_APLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BANDDIRECT_SHIFT)) & SCG_APLLCTRL_BANDDIRECT_MASK) + +#define SCG_APLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_APLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider + * 0b0..Use the predivider. + * 0b1..Bypass of the predivider. + */ +#define SCG_APLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider + * 0b0..Use the postdivider. + * 0b1..Bypass of the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_APLLCTRL_FRM_MASK (0x400000U) +#define SCG_APLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_APLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_FRM_SHIFT)) & SCG_APLLCTRL_FRM_MASK) + +#define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_APLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name APLLSTAT - APLL Status Register */ +/*! @{ */ + +#define SCG_APLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_APLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider(N) ratio change acknowledge. + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL + * 0b1..The predivider (N) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_NDIVACK_SHIFT)) & SCG_APLLSTAT_NDIVACK_MASK) + +#define SCG_APLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_APLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback(M) divider ratio change acknowledge. + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL + * 0b1..The feedback (M) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_MDIVACK_SHIFT)) & SCG_APLLSTAT_MDIVACK_MASK) + +#define SCG_APLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_APLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider(P) ratio change acknowledge. + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) + +#define SCG_APLLSTAT_FRMDET_MASK (0x10U) +#define SCG_APLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_APLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_FRMDET_SHIFT)) & SCG_APLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name APLLNDIV - APLL N Divider Register */ +/*! @{ */ + +#define SCG_APLLNDIV_NDIV_MASK (0xFFU) +#define SCG_APLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_APLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NDIV_SHIFT)) & SCG_APLLNDIV_NDIV_MASK) + +#define SCG_APLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_APLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_APLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NREQ_SHIFT)) & SCG_APLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name APLLMDIV - APLL M Divider Register */ +/*! @{ */ + +#define SCG_APLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_APLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_APLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MDIV_SHIFT)) & SCG_APLLMDIV_MDIV_MASK) + +#define SCG_APLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_APLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_APLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name APLLPDIV - APLL P Divider Register */ +/*! @{ */ + +#define SCG_APLLPDIV_PDIV_MASK (0x1FU) +#define SCG_APLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_APLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PDIV_SHIFT)) & SCG_APLLPDIV_PDIV_MASK) + +#define SCG_APLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_APLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_APLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PREQ_SHIFT)) & SCG_APLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name APLLLOCK_CNFG - APLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked. */ +#define SCG_APLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name APLLSSCGSTAT - APLL SSCG Status Register */ +/*! @{ */ + +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name APLLSSCG0 - APLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV */ +#define SCG_APLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name APLLSSCG1 - APLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_APLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_APLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_APLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_APLLSSCG1_MF_MASK (0x1CU) +#define SCG_APLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_APLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MF_SHIFT)) & SCG_APLLSSCG1_MF_MASK) + +#define SCG_APLLSSCG1_MR_MASK (0xE0U) +#define SCG_APLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_APLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MR_SHIFT)) & SCG_APLLSSCG1_MR_MASK) + +#define SCG_APLLSSCG1_MC_MASK (0x300U) +#define SCG_APLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_APLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MC_SHIFT)) & SCG_APLLSSCG1_MC_MASK) + +#define SCG_APLLSSCG1_DITHER_MASK (0x400U) +#define SCG_APLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_APLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_DITHER_SHIFT)) & SCG_APLLSSCG1_DITHER_MASK) + +#define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_APLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_APLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_APLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_APLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_PD_SHIFT)) & SCG_APLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name APLL_OVRD - APLL Override Register */ +/*! @{ */ + +#define SCG_APLL_OVRD_APLLPWREN_OVRD_MASK (0x1U) +#define SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT (0U) +/*! APLLPWREN_OVRD - APLL Power Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLL_OVRD_APLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLPWREN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK (0x2U) +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT (1U) +/*! APLLCLKEN_OVRD - APLL Clock Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLL_OVRD_APLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLL_OVRD_EN_MASK (0x80000000U) +#define SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT (31U) +/*! APLL_OVRD_EN - APLL Override Enable + * 0b0..APLL override is disabled + * 0b1..APLL override is enabled + */ +#define SCG_APLL_OVRD_APLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT)) & SCG_APLL_OVRD_APLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name SPLLCSR - SPLL Control Status Register */ +/*! @{ */ + +#define SCG_SPLLCSR_SPLLPWREN_MASK (0x1U) +#define SCG_SPLLCSR_SPLLPWREN_SHIFT (0U) +/*! SPLLPWREN - SPLL Power Enable + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLLCSR_SPLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK) + +#define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) +#define SCG_SPLLCSR_SPLLCLKEN_SHIFT (1U) +/*! SPLLCLKEN - SPLL Clock Enable + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLLCSR_SPLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK) + +#define SCG_SPLLCSR_SPLLSTEN_MASK (0x4U) +#define SCG_SPLLCSR_SPLLSTEN_SHIFT (2U) +/*! SPLLSTEN - SPLL Stop Enable + * 0b0..SPLL is disabled in Deep Sleep mode + * 0b1..SPLL is enabled in Deep Sleep mode + */ +#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) + +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) +#define SCG_SPLLCSR_SPLLCM_SHIFT (16U) +/*! SPLLCM - SPLL Clock Monitor + * 0b0..SPLL Clock Monitor is disabled + * 0b1..SPLL Clock Monitor is enabled + */ +#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) + +#define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) +#define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) +/*! SPLLCMRE - SPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) + +#define SCG_SPLLCSR_LK_MASK (0x800000U) +#define SCG_SPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_MASK (0x1000000U) +#define SCG_SPLLCSR_SPLL_LOCK_SHIFT (24U) +/*! SPLL_LOCK - SPLL LOCK + * 0b0..SPLL is not powered on or not locked + * 0b1..SPLL is locked + */ +#define SCG_SPLLCSR_SPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK) + +#define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) +#define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) +/*! SPLLSEL - SPLL Selected + * 0b0..SPLL is not the system clock source + * 0b1..SPLL is the system clock source + */ +#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) + +#define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) +#define SCG_SPLLCSR_SPLLERR_SHIFT (26U) +/*! SPLLERR - SPLL Clock Error + * 0b0..SPLL Clock Monitor is disabled or has not detected an error + * 0b1..SPLL Clock Monitor is enabled and detected an error + */ +#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_IE_MASK (0x40000000U) +#define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT (30U) +/*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable + * 0b0..SPLL_LOCK interrupt is not enabled + * 0b1..SPLL_LOCK interrupt is enabled + */ +#define SCG_SPLLCSR_SPLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name SPLLCTRL - SPLL Control Register */ +/*! @{ */ + +#define SCG_SPLLCTRL_SELR_MASK (0xFU) +#define SCG_SPLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_SPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK) + +#define SCG_SPLLCTRL_SELI_MASK (0x3F0U) +#define SCG_SPLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_SPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK) + +#define SCG_SPLLCTRL_SELP_MASK (0x7C00U) +#define SCG_SPLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_SPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider. + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_SPLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_SPLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter. + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_SPLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK) + +#define SCG_SPLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_SPLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_SPLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK) + +#define SCG_SPLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider. + * 0b0..Use the predivider + * 0b1..Bypass of the predivider + */ +#define SCG_SPLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider. + * 0b0..Use the postdivider + * 0b1..Bypass of the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_SPLLCTRL_FRM_MASK (0x400000U) +#define SCG_SPLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) + +#define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_SPLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name SPLLSTAT - SPLL Status Register */ +/*! @{ */ + +#define SCG_SPLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_SPLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider (N) ratio change acknowledge + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL. + * 0b1..The predivider (N) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK) + +#define SCG_SPLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_SPLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback (M) divider ratio change acknowledge + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL. + * 0b1..The feedback (M) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK) + +#define SCG_SPLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_SPLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider (P) ratio change acknowledge + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) + +#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) +#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name SPLLNDIV - SPLL N Divider Register */ +/*! @{ */ + +#define SCG_SPLLNDIV_NDIV_MASK (0xFFU) +#define SCG_SPLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_SPLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK) + +#define SCG_SPLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_SPLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_SPLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name SPLLMDIV - SPLL M Divider Register */ +/*! @{ */ + +#define SCG_SPLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_SPLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_SPLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK) + +#define SCG_SPLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_SPLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_SPLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name SPLLPDIV - SPLL P Divider Register */ +/*! @{ */ + +#define SCG_SPLLPDIV_PDIV_MASK (0x1FU) +#define SCG_SPLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_SPLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK) + +#define SCG_SPLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_SPLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_SPLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */ +#define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name SPLLSSCGSTAT - SPLL SSCG Status Register */ +/*! @{ */ + +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV[31:0] */ +#define SCG_SPLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_SPLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_SPLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_SPLLSSCG1_MF_MASK (0x1CU) +#define SCG_SPLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_SPLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK) + +#define SCG_SPLLSSCG1_MR_MASK (0xE0U) +#define SCG_SPLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_SPLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK) + +#define SCG_SPLLSSCG1_MC_MASK (0x300U) +#define SCG_SPLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_SPLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK) + +#define SCG_SPLLSSCG1_DITHER_MASK (0x400U) +#define SCG_SPLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_SPLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK) + +#define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_SPLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_SPLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_SPLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_SPLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name SPLL_OVRD - SPLL Override Register */ +/*! @{ */ + +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK (0x1U) +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT (0U) +/*! SPLLPWREN_OVRD - SPLL Power Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK (0x2U) +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT (1U) +/*! SPLLCLKEN_OVRD - SPLL Clock Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK (0x80000000U) +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT (31U) +/*! SPLL_OVRD_EN - SPLL Override Enable + * 0b0..SPLL override is disabled + * 0b1..SPLL override is enabled + */ +#define SCG_SPLL_OVRD_SPLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT)) & SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name UPLLCSR - UPLL Control Status Register */ +/*! @{ */ + +#define SCG_UPLLCSR_UPLLCM_MASK (0x10000U) +#define SCG_UPLLCSR_UPLLCM_SHIFT (16U) +/*! UPLLCM - UPLL Clock Monitor + * 0b0..UPLL Clock Monitor is disabled + * 0b1..UPLL Clock Monitor is enabled + */ +#define SCG_UPLLCSR_UPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCM_SHIFT)) & SCG_UPLLCSR_UPLLCM_MASK) + +#define SCG_UPLLCSR_UPLLCMRE_MASK (0x20000U) +#define SCG_UPLLCSR_UPLLCMRE_SHIFT (17U) +/*! UPLLCMRE - UPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_UPLLCSR_UPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCMRE_SHIFT)) & SCG_UPLLCSR_UPLLCMRE_MASK) + +#define SCG_UPLLCSR_LK_MASK (0x800000U) +#define SCG_UPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_UPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_LK_SHIFT)) & SCG_UPLLCSR_LK_MASK) + +#define SCG_UPLLCSR_UPLLVLD_MASK (0x1000000U) +#define SCG_UPLLCSR_UPLLVLD_SHIFT (24U) +/*! UPLLVLD - UPLL Valid + * 0b0..UPLL is not enabled or clock is not valid + * 0b1..UPLL is enabled and output clock is valid + */ +#define SCG_UPLLCSR_UPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVLD_SHIFT)) & SCG_UPLLCSR_UPLLVLD_MASK) + +#define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) +#define SCG_UPLLCSR_UPLLSEL_SHIFT (25U) +/*! UPLLSEL - UPLL Selected + * 0b0..UPLL is not the system clock source + * 0b1..UPLL is the system clock source + */ +#define SCG_UPLLCSR_UPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK) + +#define SCG_UPLLCSR_UPLLERR_MASK (0x4000000U) +#define SCG_UPLLCSR_UPLLERR_SHIFT (26U) +/*! UPLLERR - UPLL Clock Error + * 0b0..UPLL Clock Monitor is disabled or has not detected an error + * 0b1..UPLL Clock Monitor is enabled and detected an error + */ +#define SCG_UPLLCSR_UPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLERR_SHIFT)) & SCG_UPLLCSR_UPLLERR_MASK) + +#define SCG_UPLLCSR_UPLLVOR_MASK (0x40000000U) +#define SCG_UPLLCSR_UPLLVOR_SHIFT (30U) +/*! UPLLVOR - USB PLL Valid Flag Override Value + * 0b0..Override to 0b + * 0b1..Override to 1b + */ +#define SCG_UPLLCSR_UPLLVOR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVOR_SHIFT)) & SCG_UPLLCSR_UPLLVOR_MASK) + +#define SCG_UPLLCSR_UPLLVORE_MASK (0x80000000U) +#define SCG_UPLLCSR_UPLLVORE_SHIFT (31U) +/*! UPLLVORE - USB PLL Valid Flag Override Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SCG_UPLLCSR_UPLLVORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVORE_SHIFT)) & SCG_UPLLCSR_UPLLVORE_MASK) +/*! @} */ + +/*! @name LDOCSR - LDO Control and Status Register */ +/*! @{ */ + +#define SCG_LDOCSR_LDOEN_MASK (0x1U) +#define SCG_LDOCSR_LDOEN_SHIFT (0U) +/*! LDOEN - LDO Enable + * 0b0..LDO is disabled + * 0b1..LDO is enabled + */ +#define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) + +#define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) +#define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) +/*! VOUT_SEL - LDO output voltage select + * 0b000..VOUT = 1V + * 0b001..VOUT = 1V + * 0b010..VOUT = 1V + * 0b011..VOUT = 1.05V + * 0b100..VOUT = 1.1V + * 0b101..VOUT = 1.15V + * 0b110..VOUT = 1.2V + * 0b111..VOUT = 1.25V + */ +#define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) + +#define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) +#define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) +/*! LDOBYPASS - LDO Bypass + * 0b0..LDO is not bypassed + * 0b1..LDO is bypassed + */ +#define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) + +#define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) +#define SCG_LDOCSR_VOUT_OK_SHIFT (31U) +/*! VOUT_OK - LDO VOUT OK Inform. + * 0b0..LDO output VOUT is not OK + * 0b1..LDO output VOUT is OK + */ +#define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) +/*! @} */ + +/*! @name TROCSR - TRO Control Status Register */ +/*! @{ */ + +#define SCG_TROCSR_TROCM_MASK (0x10000U) +#define SCG_TROCSR_TROCM_SHIFT (16U) +/*! TROCM - TRO Clock Monitor + * 0b0..TRO Clock Monitor is disabled + * 0b1..TRO Clock Monitor is enabled + */ +#define SCG_TROCSR_TROCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCM_SHIFT)) & SCG_TROCSR_TROCM_MASK) + +#define SCG_TROCSR_TROCMRE_MASK (0x20000U) +#define SCG_TROCSR_TROCMRE_SHIFT (17U) +/*! TROCMRE - TRO Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_TROCSR_TROCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCMRE_SHIFT)) & SCG_TROCSR_TROCMRE_MASK) + +#define SCG_TROCSR_TRO_REFCLK_SEL_MASK (0xC0000U) +#define SCG_TROCSR_TRO_REFCLK_SEL_SHIFT (18U) +/*! TRO_REFCLK_SEL - TRO reference clock selection + * 0b00..SOSC + * 0b01..SIRC + * 0b10..FIRC (144 MHz or 48 MHz, based on RANGE selection) + * 0b11..Reserved + */ +#define SCG_TROCSR_TRO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TRO_REFCLK_SEL_SHIFT)) & SCG_TROCSR_TRO_REFCLK_SEL_MASK) + +#define SCG_TROCSR_LK_MASK (0x800000U) +#define SCG_TROCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_TROCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_LK_SHIFT)) & SCG_TROCSR_LK_MASK) + +#define SCG_TROCSR_TROVLD_MASK (0x1000000U) +#define SCG_TROCSR_TROVLD_SHIFT (24U) +/*! TROVLD - TRO Valid + * 0b0..TRO is not enabled or clock is not valid + * 0b1..TRO is enabled and output clock is valid + */ +#define SCG_TROCSR_TROVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROVLD_SHIFT)) & SCG_TROCSR_TROVLD_MASK) + +#define SCG_TROCSR_TROSEL_MASK (0x2000000U) +#define SCG_TROCSR_TROSEL_SHIFT (25U) +/*! TROSEL - TRO Selected + * 0b0..TRO is not the system clock source + * 0b1..TRO is the system clock source + */ +#define SCG_TROCSR_TROSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROSEL_SHIFT)) & SCG_TROCSR_TROSEL_MASK) + +#define SCG_TROCSR_TROERR_MASK (0x4000000U) +#define SCG_TROCSR_TROERR_SHIFT (26U) +/*! TROERR - TRO Clock Error + * 0b0..TRO clock monitor is disabled or has not detected an error + * 0b1..TRO clock monitor is enabled and detected an error + */ +#define SCG_TROCSR_TROERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROERR_SHIFT)) & SCG_TROCSR_TROERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer + * @{ + */ + +/** SMARTDMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ + __IO uint32_t CTRL; /**< Control, offset: 0x24 */ + __I uint32_t PC; /**< Program Counter, offset: 0x28 */ + __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ + __IO uint32_t BREAK_ADDR; /**< Breakpoint Address, offset: 0x30 */ + __IO uint32_t BREAK_VECT; /**< Breakpoint Vector, offset: 0x34 */ + __IO uint32_t EMER_VECT; /**< Emergency Vector, offset: 0x38 */ + __IO uint32_t EMER_SEL; /**< Emergency Select, offset: 0x3C */ + __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ + __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ + __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ +} SMARTDMA_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks + * @{ + */ + +/*! @name BOOTADR - Boot Address */ +/*! @{ */ + +#define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ +#define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define SMARTDMA_CTRL_START_MASK (0x1U) +#define SMARTDMA_CTRL_START_SHIFT (0U) +/*! START - Start Bit Ignition */ +#define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) + +#define SMARTDMA_CTRL_EXF_MASK (0x2U) +#define SMARTDMA_CTRL_EXF_SHIFT (1U) +/*! EXF - External Flag */ +#define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) + +#define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) +#define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) +/*! ERRDIS - Error Disable */ +#define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) + +#define SMARTDMA_CTRL_BUFEN_MASK (0x8U) +#define SMARTDMA_CTRL_BUFEN_SHIFT (3U) +/*! BUFEN - Buffer Enable */ +#define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) + +#define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) +#define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) +/*! SYNCEN - Sync Enable */ +#define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) + +#define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) +#define SMARTDMA_CTRL_WKEY_SHIFT (16U) +/*! WKEY - Write Key */ +#define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) +/*! @} */ + +/*! @name PC - Program Counter */ +/*! @{ */ + +#define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) +#define SMARTDMA_PC_PC_SHIFT (0U) +/*! PC - Program Counter */ +#define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) +/*! @} */ + +/*! @name SP - Stack Pointer */ +/*! @{ */ + +#define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) +#define SMARTDMA_SP_SP_SHIFT (0U) +/*! SP - Stack Pointer */ +#define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) +/*! @} */ + +/*! @name BREAK_ADDR - Breakpoint Address */ +/*! @{ */ + +#define SMARTDMA_BREAK_ADDR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_ADDR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit address to swap to EZHB_BREAK_VECT location */ +#define SMARTDMA_BREAK_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_ADDR_ADDR_SHIFT)) & SMARTDMA_BREAK_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name BREAK_VECT - Breakpoint Vector */ +/*! @{ */ + +#define SMARTDMA_BREAK_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of user debug routine. */ +#define SMARTDMA_BREAK_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_VECT_VEC_SHIFT)) & SMARTDMA_BREAK_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_VECT - Emergency Vector */ +/*! @{ */ + +#define SMARTDMA_EMER_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_EMER_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of emergency code routine */ +#define SMARTDMA_EMER_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_VECT_VEC_SHIFT)) & SMARTDMA_EMER_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_SEL - Emergency Select */ +/*! @{ */ + +#define SMARTDMA_EMER_SEL_EN_MASK (0x100U) +#define SMARTDMA_EMER_SEL_EN_SHIFT (8U) +/*! EN - Emergency code routine */ +#define SMARTDMA_EMER_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_EN_SHIFT)) & SMARTDMA_EMER_SEL_EN_MASK) + +#define SMARTDMA_EMER_SEL_RQ_MASK (0x200U) +#define SMARTDMA_EMER_SEL_RQ_SHIFT (9U) +/*! RQ - Software emergency request */ +#define SMARTDMA_EMER_SEL_RQ(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_RQ_SHIFT)) & SMARTDMA_EMER_SEL_RQ_MASK) +/*! @} */ + +/*! @name ARM2EZH - ARM to EZH Interrupt Control */ +/*! @{ */ + +#define SMARTDMA_ARM2EZH_IE_MASK (0x3U) +#define SMARTDMA_ARM2EZH_IE_SHIFT (0U) +/*! IE - Interrupt Enable */ +#define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) + +#define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) +#define SMARTDMA_ARM2EZH_GP_SHIFT (2U) +/*! GP - General purpose register bits */ +#define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) +/*! @} */ + +/*! @name EZH2ARM - EZH to ARM Trigger */ +/*! @{ */ + +#define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) +#define SMARTDMA_EZH2ARM_GP_SHIFT (0U) +/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ +#define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) +/*! @} */ + +/*! @name PENDTRAP - Pending Trap Control */ +/*! @{ */ + +#define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) +#define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) +/*! STATUS - Status Flag or Pending Trap Request */ +#define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) + +#define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) +#define SMARTDMA_PENDTRAP_POL_SHIFT (8U) +/*! POL - Polarity */ +#define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) + +#define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) +#define SMARTDMA_PENDTRAP_EN_SHIFT (16U) +/*! EN - Enable Pending Trap */ +#define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SMARTDMA_Register_Masks */ + + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/*! + * @} + */ /* end of group SMARTDMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[2]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[188]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + uint8_t RESERVED_5[16]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ + uint8_t RESERVED_7[440]; + __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ + uint8_t RESERVED_8[252]; + __IO uint32_t SYSLDO_CFG; /**< LDO_SYS Configuration, offset: 0x400 */ + uint8_t RESERVED_9[252]; + __IO uint32_t DCDC_CFG; /**< DCDC Configuration, offset: 0x500 */ + __IO uint32_t DCDC_BURST_CFG; /**< DCDC Burst Configuration, offset: 0x504 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + * *.. + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000..Sleep mode with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x30000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name CNTRL - SPC Regulator Control */ +/*! @{ */ + +#define SPC_CNTRL_CORELDO_EN_MASK (0x1U) +#define SPC_CNTRL_CORELDO_EN_SHIFT (0U) +/*! CORELDO_EN - LDO_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) + +#define SPC_CNTRL_SYSLDO_EN_MASK (0x2U) +#define SPC_CNTRL_SYSLDO_EN_SHIFT (1U) +/*! SYSLDO_EN - LDO_SYS Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_SYSLDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK) + +#define SPC_CNTRL_DCDC_EN_MASK (0x4U) +#define SPC_CNTRL_DCDC_EN_SHIFT (2U) +/*! DCDC_EN - DCDC_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_DCDC_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U) +#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U) +/*! PWR_REQ_STATUS - Power Request Status Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000..SLEEP with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/* The count of SPC_PD_STATUS */ +#define SPC_PD_STATUS_COUNT (2U) + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1.0 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Reserved + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK (0x40U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT (6U) +/*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level + * 0b0..Normal voltage (1.8 V) + * 0b1..Overdrive voltage (2.5 V) + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b01..Low + * 0b10..Normal + * *.. + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Reserved + * 0b01..Midvoltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled + */ +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U) +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U) +/*! VDD_VD_DISABLE - VDD Voltage Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_ACTIVE_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK) + +#define SPC_ACTIVE_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_ACTIVE_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Retention voltage + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_LP_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b00..Pulse refresh + * 0b01..Low + * 0b10..Normal + * 0b11.. + */ +#define SPC_LP_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Retention voltage (0.7 V) + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_LP_CFG_COREVDD_IVS_EN_MASK (0x20000U) +#define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT (17U) +/*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_COREVDD_IVS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK) + +#define SPC_LP_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_LP_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_LP_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK) + +#define SPC_LP_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_LP_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) + +#define SPC_LP_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_LP_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_IOVDD_LVDF_MASK (0x4U) +#define SPC_VD_STAT_IOVDD_LVDF_SHIFT (2U) +/*! IOVDD_LVDF - IO VDD LVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK) + +#define SPC_VD_STAT_COREVDD_HVDF_MASK (0x10U) +#define SPC_VD_STAT_COREVDD_HVDF_SHIFT (4U) +/*! COREVDD_HVDF - Core VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) + +#define SPC_VD_STAT_IOVDD_HVDF_MASK (0x40U) +#define SPC_VD_STAT_IOVDD_HVDF_SHIFT (6U) +/*! IOVDD_HVDF - IO VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_CORE_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - Core VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK) + +#define SPC_VD_CORE_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_CORE_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - Core VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_IO_CFG - IO Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_IO_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_IO_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - IO VDD LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK) + +#define SPC_VD_IO_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_IO_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - IO VDD LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK) + +#define SPC_VD_IO_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_IO_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - IO VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK) + +#define SPC_VD_IO_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_IO_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - IO VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK) + +#define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - IO VDD Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) + +#define SPC_VD_IO_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_IO_CFG_LOCK_SHIFT (16U) +/*! LOCK - IO Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_IO_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0x3FU) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0x3F00U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0x3F0000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ +/*! @{ */ + +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +/*! CNT_SELECT - Counter Select + * 0b00..0 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) + +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +/*! TIMEOUT - Timeout */ +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) + +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset + */ +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) + +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt + */ +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) + +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) + +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit + * 0b0..Writes to RE are allowed. + * 0b1..Writes to RE are ignored. + */ +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) +/*! @} */ + +/*! @name CORELDO_CFG - LDO_CORE Configuration */ +/*! @{ */ + +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U) +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U) +/*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable + * 0b0..LDO_CORE pulldown in Deep Power Down not disabled + * 0b1..LDO_CORE pulldown in Deep Power Down disabled + */ +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK) +/*! @} */ + +/*! @name SYSLDO_CFG - LDO_SYS Configuration */ +/*! @{ */ + +#define SPC_SYSLDO_CFG_ISINKEN_MASK (0x1U) +#define SPC_SYSLDO_CFG_ISINKEN_SHIFT (0U) +/*! ISINKEN - Current Sink Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SYSLDO_CFG_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK) +/*! @} */ + +/*! @name DCDC_CFG - DCDC Configuration */ +/*! @{ */ + +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK (0x1U) +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT (0U) +/*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_CFG_FREQ_CNTRL_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK) + +#define SPC_DCDC_CFG_FREQ_CNTRL_MASK (0x3F00U) +#define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT (8U) +/*! FREQ_CNTRL - DCDC Burst Frequency Control */ +#define SPC_DCDC_CFG_FREQ_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK) + +#define SPC_DCDC_CFG_BLEED_EN_MASK (0x80000U) +#define SPC_DCDC_CFG_BLEED_EN_SHIFT (19U) +/*! BLEED_EN - DCDC Bleed Enable + * 0b0..Do not add + * 0b1..Add + */ +#define SPC_DCDC_CFG_BLEED_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_BLEED_EN_SHIFT)) & SPC_DCDC_CFG_BLEED_EN_MASK) +/*! @} */ + +/*! @name DCDC_BURST_CFG - DCDC Burst Configuration */ +/*! @{ */ + +#define SPC_DCDC_BURST_CFG_BURST_REQ_MASK (0x1U) +#define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT (0U) +/*! BURST_REQ - Software Burst Request + * 0b0..Do not generate + * 0b1..Generate + */ +#define SPC_DCDC_BURST_CFG_BURST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK) + +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK (0x2U) +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT (1U) +/*! EXT_BURST_EN - External Burst Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK) + +#define SPC_DCDC_BURST_CFG_BURST_ACK_MASK (0x8U) +#define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT (3U) +/*! BURST_ACK - Burst Acknowledge Flag + * 0b0..Did not complete + * 0b1..Completed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_DCDC_BURST_CFG_BURST_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) + +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U) +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U) +/*! PULSE_REFRESH_CNT - Refresh Count Value */ +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< Secure CPU0 System Tick Calibration, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + __IO uint32_t PRESETCTRL0; /**< Peripheral Reset Control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral Reset Control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral Reset Control 2, offset: 0x108 */ + __IO uint32_t PRESETCTRL3; /**< Peripheral Reset Control 3, offset: 0x10C */ + uint8_t RESERVED_4[16]; + __O uint32_t PRESETCTRLSET[4]; /**< Peripheral Reset Control Set, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral Reset Control Clear, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[176]; + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock Control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock Control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock Control 2, offset: 0x208 */ + __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ + uint8_t RESERVED_7[16]; + __O uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __O uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_9[16]; + __IO uint32_t SYSTICKCLKSEL0; /**< CPU0 System Tick Timer Source Select, offset: 0x260 */ + uint8_t RESERVED_10[4]; + __IO uint32_t TRACECLKSEL; /**< Trace Clock Source Select, offset: 0x268 */ + __IO uint32_t CTIMERCLKSEL[5]; /**< CTIMER Clock Source Select, array offset: 0x26C, array step: 0x4 */ + uint8_t RESERVED_11[8]; + __IO uint32_t CLKOUTSEL; /**< CLKOUT Clock Source Select, offset: 0x288 */ + uint8_t RESERVED_12[24]; + __IO uint32_t ADC0CLKSEL; /**< ADC0 Clock Source Select, offset: 0x2A4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t FCCLKSEL[8]; /**< LP_FLEXCOMM Clock Source Select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_14[48]; + __IO uint32_t SYSTICKCLKDIV[1]; /**< CPU0 System Tick Timer Divider, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_15[4]; + __IO uint32_t TRACECLKDIV; /**< TRACE Clock Divider, offset: 0x308 */ + uint8_t RESERVED_16[108]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + uint8_t RESERVED_17[4]; + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT Clock Divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ + __IO uint32_t WDT0CLKDIV; /**< WDT0 Clock Divider, offset: 0x38C */ + uint8_t RESERVED_18[4]; + __IO uint32_t ADC0CLKDIV; /**< ADC0 Clock Divider, offset: 0x394 */ + uint8_t RESERVED_19[44]; + __IO uint32_t PLLCLKDIV; /**< PLL Clock Divider, offset: 0x3C4 */ + uint8_t RESERVED_20[8]; + __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer Clock Divider, array offset: 0x3D0, array step: 0x4 */ + __IO uint32_t PLL1CLK0DIV; /**< PLL1 Clock 0 Divider, offset: 0x3E4 */ + __IO uint32_t PLL1CLK1DIV; /**< PLL1 Clock 1 Divider, offset: 0x3E8 */ + uint8_t RESERVED_21[4]; + __IO uint32_t UTICKCLKDIV; /**< UTICK Clock Divider, offset: 0x3F0 */ + __IO uint32_t CLKOUT_FRGCTRL; /**< CLKOUT FRG Control, offset: 0x3F4 */ + uint8_t RESERVED_22[4]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + __IO uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */ + uint8_t RESERVED_23[12]; + __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ + uint8_t RESERVED_24[76]; + __IO uint32_t ADC1CLKSEL; /**< ADC1 Clock Source Select, offset: 0x464 */ + __IO uint32_t ADC1CLKDIV; /**< ADC1 Clock Divider, offset: 0x468 */ + uint8_t RESERVED_25[4]; + __IO uint32_t RAM_INTERLEAVE; /**< Control PKC RAM Interleave Access, offset: 0x470 */ + uint8_t RESERVED_26[184]; + __IO uint32_t PLLCLKDIVSEL; /**< PLL Clock Divider Clock Selection, offset: 0x52C */ + __IO uint32_t I3C0FCLKSEL; /**< I3C0 Functional Clock Selection, offset: 0x530 */ + uint8_t RESERVED_27[12]; + __IO uint32_t I3C0FCLKDIV; /**< I3C0 Functional Clock FCLK Divider, offset: 0x540 */ + uint8_t RESERVED_28[4]; + __IO uint32_t MICFILFCLKSEL; /**< MICFIL Clock Selection, offset: 0x548 */ + __IO uint32_t MICFILFCLKDIV; /**< MICFIL Clock Division, offset: 0x54C */ + uint8_t RESERVED_29[16]; + __IO uint32_t FLEXIOCLKSEL; /**< FLEXIO Clock Selection, offset: 0x560 */ + __IO uint32_t FLEXIOCLKDIV; /**< FLEXIO Function Clock Divider, offset: 0x564 */ + uint8_t RESERVED_30[56]; + __IO uint32_t FLEXCAN0CLKSEL; /**< FLEXCAN0 Clock Selection, offset: 0x5A0 */ + __IO uint32_t FLEXCAN0CLKDIV; /**< FLEXCAN0 Function Clock Divider, offset: 0x5A4 */ + __IO uint32_t FLEXCAN1CLKSEL; /**< FLEXCAN1 Clock Selection, offset: 0x5A8 */ + __IO uint32_t FLEXCAN1CLKDIV; /**< FLEXCAN1 Function Clock Divider, offset: 0x5AC */ + uint8_t RESERVED_31[36]; + __IO uint32_t EWM0CLKSEL; /**< EWM0 Clock Selection, offset: 0x5D4 */ + __IO uint32_t WDT1CLKSEL; /**< WDT1 Clock Selection, offset: 0x5D8 */ + __IO uint32_t WDT1CLKDIV; /**< WDT1 Function Clock Divider, offset: 0x5DC */ + __IO uint32_t OSTIMERCLKSEL; /**< OSTIMER Clock Selection, offset: 0x5E0 */ + uint8_t RESERVED_32[12]; + __IO uint32_t CMP0FCLKSEL; /**< CMP0 Function Clock Selection, offset: 0x5F0 */ + __IO uint32_t CMP0FCLKDIV; /**< CMP0 Function Clock Divider, offset: 0x5F4 */ + __IO uint32_t CMP0RRCLKSEL; /**< CMP0 Round Robin Clock Selection, offset: 0x5F8 */ + __IO uint32_t CMP0RRCLKDIV; /**< CMP0 Round Robin Clock Divider, offset: 0x5FC */ + __IO uint32_t CMP1FCLKSEL; /**< CMP1 Function Clock Selection, offset: 0x600 */ + __IO uint32_t CMP1FCLKDIV; /**< CMP1 Function Clock Divider, offset: 0x604 */ + __IO uint32_t CMP1RRCLKSEL; /**< CMP1 Round Robin Clock Source Select, offset: 0x608 */ + __IO uint32_t CMP1RRCLKDIV; /**< CMP1 Round Robin Clock Division, offset: 0x60C */ + uint8_t RESERVED_33[508]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_35[40]; + __IO uint32_t FLEXCOMMCLKDIV[8]; /**< LP_FLEXCOMM Clock Divider, array offset: 0x850, array step: 0x4 */ + uint8_t RESERVED_36[8]; + __IO uint32_t UTICKCLKSEL; /**< UTICK Function Clock Source Select, offset: 0x878 */ + uint8_t RESERVED_37[4]; + __IO uint32_t SAI0CLKSEL; /**< SAI0 Function Clock Source Select, offset: 0x880 */ + __IO uint32_t SAI1CLKSEL; /**< SAI1 Function Clock Source Select, offset: 0x884 */ + __IO uint32_t SAI0CLKDIV; /**< SAI0 Function Clock Division, offset: 0x888 */ + __IO uint32_t SAI1CLKDIV; /**< SAI1 Function Clock Division, offset: 0x88C */ + uint8_t RESERVED_38[192]; + __IO uint32_t KEY_RETAIN_CTRL; /**< Key Retain Control, offset: 0x950 */ + uint8_t RESERVED_39[12]; + __IO uint32_t REF_CLK_CTRL; /**< FRO 48MHz Reference Clock Control, offset: 0x960 */ + __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ + __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ + __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ + __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ + __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ + __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ + __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ + __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ + uint8_t RESERVED_40[64]; + __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ + __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ + __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ + __I uint32_t ELS_AS_CFG3; /**< ELS AS Configuration3, offset: 0x9DC */ + __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ + __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ + __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ + __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ + __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ + __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ + __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ + __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ + uint8_t RESERVED_41[24]; + __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ + uint8_t RESERVED_42[276]; + __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ + uint8_t RESERVED_43[12]; + __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ + uint8_t RESERVED_44[28]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray code_gray[31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_45[660]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ + uint8_t RESERVED_46[36]; + __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ + uint8_t RESERVED_47[8]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ + __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ + uint8_t RESERVED_48[344]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_49[8]; + __IO uint32_t SWD_ACCESS_CPU[1]; /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ + uint8_t RESERVED_50[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_51[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) + +#define SYSCON_AHBMATPRIO_DMA1_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_DMA1_SHIFT (10U) +/*! DMA1 - DMA1 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA1_SHIFT)) & SYSCON_AHBMATPRIO_DMA1_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT (12U) +/*! PRI_PKC_ELS - PKC and ELS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC000000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (26U) +/*! PRI_USB_HS - USB-HS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b1..Enable. + * 0b0..Disable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_FMU_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL0_FMU_RST_SHIFT (9U) +/*! FMU_RST - Flash management unit reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_FMU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMU_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMU_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (12U) +/*! MUX_RST - INPUTMUX reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT0_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_PORT0_RST_SHIFT (13U) +/*! PORT0_RST - PORT0 controller reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT0_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT0_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT1_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_PORT1_RST_SHIFT (14U) +/*! PORT1_RST - PORT1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT1_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT1_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT2_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_PORT2_RST_SHIFT (15U) +/*! PORT2_RST - PORT2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT2_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT2_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT3_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_PORT3_RST_SHIFT (16U) +/*! PORT3_RST - PORT3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT3_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT4_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_PORT4_RST_SHIFT (17U) +/*! PORT4_RST - PORT4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT4_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT4_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (19U) +/*! GPIO0_RST - GPIO0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (20U) +/*! GPIO1_RST - GPIO1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (21U) +/*! GPIO2_RST - GPIO2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (22U) +/*! GPIO3_RST - GPIO3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO4_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT (23U) +/*! GPIO4_RST - GPIO4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO4_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (25U) +/*! PINT_RST - PINT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (26U) +/*! DMA0_RST - DMA0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_CRC_RST_SHIFT (27U) +/*! CRC_RST - CRC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC0_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL1_ADC0_RST_SHIFT (3U) +/*! ADC0_RST - ADC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC1_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL1_ADC1_RST_SHIFT (4U) +/*! ADC1_RST - ADC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_RTC_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_RTC_RST_SHIFT (6U) +/*! RTC_RST - RTC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL1_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - LP_FLEXCOMM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - LP_FLEXCOMM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - LP_FLEXCOMM2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - LP_FLEXCOMM3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - LP_FLEXCOMM4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - LP_FLEXCOMM5 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - LP_FLEXCOMM6 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - LP_FLEXCOMM7 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_MICFIL_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT (21U) +/*! MICFIL_RST - MICFIL reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MICFIL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT)) & SYSCON_PRESETCTRL1_MICFIL_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - CTIMER2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - CTIMER0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - CTIMER1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) + +#define SYSCON_PRESETCTRL1_SmartDMA_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT (31U) +/*! SmartDMA_RST - SmartDMA reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_SmartDMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT)) & SYSCON_PRESETCTRL1_SmartDMA_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral Reset Control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXIO_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT (4U) +/*! FLEXIO_RST - FLEXIO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI0_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_SAI0_RST_SHIFT (5U) +/*! SAI0_RST - SAI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI0_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI0_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI1_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_SAI1_RST_SHIFT (6U) +/*! SAI1_RST - SAI1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI1_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI1_RST_MASK) + +#define SYSCON_PRESETCTRL2_TRO_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_TRO_RST_SHIFT (7U) +/*! TRO_RST - TRO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TRO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRO_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRO_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - FREQME reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT (14U) +/*! FLEXCAN0_RST - CAN0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT (15U) +/*! FLEXCAN1_RST - CAN1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT (16U) +/*! USB_HS_RST - USB HS reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT (17U) +/*! USB_HS_PHY_RST - USB HS PHY reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - CTIMER3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - CTIMER4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) +/*! PKC_RST - PKC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL3 - Peripheral Reset Control 3 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) +/*! I3C0_RST - I3C0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) + +#define SYSCON_PRESETCTRL3_I3C1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL3_I3C1_RST_SHIFT (1U) +/*! I3C1_RST - I3C1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C1_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C1_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) +/*! QDC0_RST - QDC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) +/*! QDC1_RST - QDC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) +/*! PWM0_RST - PWM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (7U) +/*! PWM1_RST - PWM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) + +#define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (8U) +/*! AOI0_RST - AOI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) + +#define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (19U) +/*! VREF_RST - VREF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) + +#define SYSCON_PRESETCTRL3_EWM_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL3_EWM_RST_SHIFT (23U) +/*! EWM_RST - EWM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EWM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EWM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EWM_RST_MASK) + +#define SYSCON_PRESETCTRL3_EIM_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL3_EIM_RST_SHIFT (24U) +/*! EIM_RST - EIM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EIM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EIM_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLSET - Peripheral Reset Control Set */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (4U) + +/*! @name PRESETCTRLCLR - Peripheral Reset Control Clear */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (4U) + +/*! @name AHBCLKCTRL0 - AHB Clock Control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Enables the clock for the RAMB Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Enables the clock for the RAMC Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Enables the clock for the RAMD Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Enables the clock for the RAME Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_FMU_MASK (0x200U) +#define SYSCON_AHBCLKCTRL0_FMU_SHIFT (9U) +/*! FMU - Enables the clock for the Flash Management Unit + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMU_SHIFT)) & SYSCON_AHBCLKCTRL0_FMU_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x400U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (10U) +/*! FMC - Enables the clock for the Flash Memory Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (12U) +/*! MUX - Enables the clock for INPUTMUX + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT0_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_PORT0_SHIFT (13U) +/*! PORT0 - Enables the clock for PORT0 controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT0_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT0_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_PORT1_SHIFT (14U) +/*! PORT1 - Enables the clock for PORT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT1_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT1_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT2_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_PORT2_SHIFT (15U) +/*! PORT2 - Enables the clock for PORT2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT2_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT2_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT3_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_PORT3_SHIFT (16U) +/*! PORT3 - Enables the clock for PORT3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT3_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT3_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT4_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_PORT4_SHIFT (17U) +/*! PORT4 - Enables the clock for PORT4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT4_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT4_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (19U) +/*! GPIO0 - Enables the clock for GPIO0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (20U) +/*! GPIO1 - Enables the clock for GPIO1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (21U) +/*! GPIO2 - Enables the clock for GPIO2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (22U) +/*! GPIO3 - Enables the clock for GPIO3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO4_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_GPIO4_SHIFT (23U) +/*! GPIO4 - Enables the clock for GPIO4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO4_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (25U) +/*! PINT - Enables the clock for PINT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (26U) +/*! DMA0 - Enables the clock for DMA0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_CRC_SHIFT (27U) +/*! CRC - Enables the clock for CRC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRC_SHIFT)) & SYSCON_AHBCLKCTRL0_CRC_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT0_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL0_WWDT0_SHIFT (28U) +/*! WWDT0 - Enables the clock for WWDT0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT0_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT0_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT1_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL0_WWDT1_SHIFT (29U) +/*! WWDT1 - Enables the clock for WWDT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT1_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock Control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for MRT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC0_MASK (0x8U) +#define SYSCON_AHBCLKCTRL1_ADC0_SHIFT (3U) +/*! ADC0 - Enables the clock for ADC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC0_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC1_MASK (0x10U) +#define SYSCON_AHBCLKCTRL1_ADC1_SHIFT (4U) +/*! ADC1 - Enables the clock for ADC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC1_MASK) + +#define SYSCON_AHBCLKCTRL1_RTC_MASK (0x40U) +#define SYSCON_AHBCLKCTRL1_RTC_SHIFT (6U) +/*! RTC - Enables the clock for RTC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_RTC_SHIFT)) & SYSCON_AHBCLKCTRL1_RTC_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for UTICK + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for LP_FLEXCOMM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for LP_FLEXCOMM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for LP_FLEXCOMM2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for LP_FLEXCOMM3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for LP_FLEXCOMM4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for LP_FLEXCOMM5 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for LP_FLEXCOMM6 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for LP_FLEXCOMM7 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_MICFIL_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL1_MICFIL_SHIFT (21U) +/*! MICFIL - Enables the clock for MICFIL + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MICFIL_SHIFT)) & SYSCON_AHBCLKCTRL1_MICFIL_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for CTIMER2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for CTIMER0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for CTIMER1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) + +#define SYSCON_AHBCLKCTRL1_PKC_RAM_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT (29U) +/*! PKC_RAM - Enables the clock for PKC RAM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT)) & SYSCON_AHBCLKCTRL1_PKC_RAM_MASK) + +#define SYSCON_AHBCLKCTRL1_SmartDMA_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT (31U) +/*! SmartDMA - Enables the clock for SmartDMA + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_SmartDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT)) & SYSCON_AHBCLKCTRL1_SmartDMA_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock Control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for DMA1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXIO_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT (4U) +/*! FLEXIO - Enables the clock for Flexio + * 0b1..Enable clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXIO_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI0_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_SAI0_SHIFT (5U) +/*! SAI0 - Enables the clock for SAI0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI0_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI0_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI1_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_SAI1_SHIFT (6U) +/*! SAI1 - Enables the clock for SAI1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI1_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI1_MASK) + +#define SYSCON_AHBCLKCTRL2_TRO_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_TRO_SHIFT (7U) +/*! TRO - Enables the clock for TRO + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRO_SHIFT)) & SYSCON_AHBCLKCTRL2_TRO_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT (14U) +/*! FLEXCAN0 - Enables the clock for FLEXCAN0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT (15U) +/*! FLEXCAN1 - Enables the clock for FLEXCAN1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_SHIFT (16U) +/*! USB_HS - Enables the clock for USB HS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT (17U) +/*! USB_HS_PHY - Enables the clock for USB HS PHY + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_ELS_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_ELS_SHIFT (18U) +/*! ELS - Enables the clock for ELS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ELS_SHIFT)) & SYSCON_AHBCLKCTRL2_ELS_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for CTIMER3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for CTIMER4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for PUF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) +/*! PKC - Enables the clock for PKC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) + +#define SYSCON_AHBCLKCTRL2_SCG_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL2_SCG_SHIFT (26U) +/*! SCG - Enables the clock for SCG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SCG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SCG_SHIFT)) & SYSCON_AHBCLKCTRL2_SCG_MASK) + +#define SYSCON_AHBCLKCTRL2_GDET_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GDET_SHIFT (29U) +/*! GDET - Enables the clock for GDET0 and GDET1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GDET_SHIFT)) & SYSCON_AHBCLKCTRL2_GDET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) +/*! I3C0 - Enables the clock for I3C0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) + +#define SYSCON_AHBCLKCTRL3_I3C1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL3_I3C1_SHIFT (1U) +/*! I3C1 - Enables the clock for I3C1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C1_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C1_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) +/*! QDC0 - Enables the clock for QDC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) +/*! QDC1 - Enables the clock for QDC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) +#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) +/*! PWM0 - Enables the clock for PWM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x80U) +#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (7U) +/*! PWM1 - Enables the clock for PWM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) + +#define SYSCON_AHBCLKCTRL3_EVTG_MASK (0x100U) +#define SYSCON_AHBCLKCTRL3_EVTG_SHIFT (8U) +/*! EVTG - Enables the clock for EVTG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EVTG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EVTG_SHIFT)) & SYSCON_AHBCLKCTRL3_EVTG_MASK) + +#define SYSCON_AHBCLKCTRL3_VREF_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL3_VREF_SHIFT (19U) +/*! VREF - Enables the clock for VREF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) + +#define SYSCON_AHBCLKCTRL3_EWM_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL3_EWM_SHIFT (23U) +/*! EWM - Enables the clock for EWM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EWM_SHIFT)) & SYSCON_AHBCLKCTRL3_EWM_MASK) + +#define SYSCON_AHBCLKCTRL3_EIM_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL3_EIM_SHIFT (24U) +/*! EIM - Enables the clock for EIM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EIM_SHIFT)) & SYSCON_AHBCLKCTRL3_EIM_MASK) + +#define SYSCON_AHBCLKCTRL3_ERM_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL3_ERM_SHIFT (25U) +/*! ERM - Enables the clock for ERM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_ERM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ERM_SHIFT)) & SYSCON_AHBCLKCTRL3_ERM_MASK) + +#define SYSCON_AHBCLKCTRL3_INTM_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL3_INTM_SHIFT (26U) +/*! INTM - Enables the clock for INTM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_INTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_INTM_SHIFT)) & SYSCON_AHBCLKCTRL3_INTM_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLSET - AHB Clock Control Set */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (4U) + +/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (4U) + +/*! @name SYSTICKCLKSEL0 - CPU0 System Tick Timer Source Select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Selects the System Tick Timer for CPU0 source + * 0b000..SYSTICKCLKDIV0 output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name TRACECLKSEL - Trace Clock Source Select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the trace clock source. + * 0b000..TRACECLKDIV output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL - CTIMER Clock Source Select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL_SEL_MASK (0xFU) +#define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CTIMER clock source. + * 0b0000..FRO_1M clock + * 0b0001..PLL0 clock + * 0b0010..PLL1_clk0 clock + * 0b0011..FRO_HF clock + * 0b0100..FRO 12MHz clock + * 0b0101..SAI0 MCLK IN clock + * 0b0110..LP Oscillator clock + * 0b0111..No clock + * 0b1000..SAI1 MCLK IN clock + * 0b1001..SAI0 TX_BCLK clock + * 0b1010..SAI0 RX_BCLK clock + * 0b1011..SAI1 TX_BCLK clock + * 0b1100..SAI1 RX_BCLK clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSEL */ +#define SYSCON_CTIMERCLKSEL_COUNT (5U) + +/*! @name CLKOUTSEL - CLKOUT Clock Source Select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CLKOUT clock source. + * 0b0000..Main clock (main_clk) + * 0b0001..PLL0 clock (pll0_clk) + * 0b0010..CLKIN clock (clk_in) + * 0b0011..FRO_HF clock (fro_hf) + * 0b0100..FRO 12 MHz clock (fro_12m) + * 0b0101..PLL1_clk0 clock (pll1_clk) + * 0b0110..LP Oscillator clock (lp_osc) + * 0b0111..USB PLL clock (usb_pll_clk) + * 0b1000..No clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC0CLKSEL - ADC0 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC0 clock source. + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL - LP_FLEXCOMM Clock Source Select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the LP_FLEXCOMM clock source for Fractional Rate Divider. + * 0b000..No clock + * 0b001..PLL divided clock + * 0b010..FRO 12 MHz clock + * 0b011..fro_hf_div clock + * 0b100..clk_1m clock + * 0b101..USB PLL clock + * 0b110..LP Oscillator clock + * 0b111..No clock + */ +#define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSEL */ +#define SYSCON_FCCLKSEL_COUNT (8U) + +/*! @name SYSTICKCLKDIV - CPU0 System Tick Timer Divider */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset. + * 0b0..Divider is not reset + */ +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKDIV */ +#define SYSCON_SYSTICKCLKDIV_COUNT (1U) + +/*! @name TRACECLKDIV - TRACE Clock Divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT Clock Divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running, this bit is set to 0 when the register is written. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name WDT0CLKDIV - WDT0 Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT0CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_DIV_SHIFT)) & SYSCON_WDT0CLKDIV_DIV_MASK) + +#define SYSCON_WDT0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_RESET_SHIFT)) & SYSCON_WDT0CLKDIV_RESET_MASK) + +#define SYSCON_WDT0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_HALT_SHIFT)) & SYSCON_WDT0CLKDIV_HALT_MASK) + +#define SYSCON_WDT0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name ADC0CLKDIV - ADC0 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) + +#define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) + +#define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) + +#define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLLCLKDIV - PLL Clock Divider */ +/*! @{ */ + +#define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) + +#define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) + +#define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) + +#define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer Clock Divider */ +/*! @{ */ + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock has stopped + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Stable divider clock + * 0b1..Unstable clock frequency + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) + +/*! @name PLL1CLK0DIV - PLL1 Clock 0 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK0DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK0DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK0DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_DIV_SHIFT)) & SYSCON_PLL1CLK0DIV_DIV_MASK) + +#define SYSCON_PLL1CLK0DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK0DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK0DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_RESET_SHIFT)) & SYSCON_PLL1CLK0DIV_RESET_MASK) + +#define SYSCON_PLL1CLK0DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK0DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK0DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_HALT_SHIFT)) & SYSCON_PLL1CLK0DIV_HALT_MASK) + +#define SYSCON_PLL1CLK0DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK0DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK0DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLL1CLK1DIV - PLL1 Clock 1 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK1DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK1DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK1DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_DIV_SHIFT)) & SYSCON_PLL1CLK1DIV_DIV_MASK) + +#define SYSCON_PLL1CLK1DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK1DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK1DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_RESET_SHIFT)) & SYSCON_PLL1CLK1DIV_RESET_MASK) + +#define SYSCON_PLL1CLK1DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK1DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK1DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_HALT_SHIFT)) & SYSCON_PLL1CLK1DIV_HALT_MASK) + +#define SYSCON_PLL1CLK1DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK1DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK1DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name UTICKCLKDIV - UTICK Clock Divider */ +/*! @{ */ + +#define SYSCON_UTICKCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_UTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_UTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_DIV_SHIFT)) & SYSCON_UTICKCLKDIV_DIV_MASK) + +#define SYSCON_UTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_UTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_UTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_RESET_SHIFT)) & SYSCON_UTICKCLKDIV_RESET_MASK) + +#define SYSCON_UTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_UTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_UTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_HALT_SHIFT)) & SYSCON_UTICKCLKDIV_HALT_MASK) + +#define SYSCON_UTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_UTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_UTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_UTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUT_FRGCTRL - CLKOUT FRG Control */ +/*! @{ */ + +#define SYSCON_CLKOUT_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT (0U) +/*! DIV - Divider value */ +#define SYSCON_CLKOUT_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_DIV_MASK) + +#define SYSCON_CLKOUT_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT (8U) +/*! MULT - Numerator value */ +#define SYSCON_CLKOUT_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, xxxDIV, xxxSEL) + * 0b1..Freezes all clock configuration registers update + * 0b0..Updates are allowed to all clock configuration registers + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK (0x4U) +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT (2U) +/*! DIS_FLASH_CACHE - Flash cache control + * 0b0..Enables flash cache + * 0b1..Disables flash cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK (0x8U) +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT (3U) +/*! DIS_FLASH_INST - Flash instruction cache control + * 0b0..Enables flash instruction cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash instruction cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK (0x10U) +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT (4U) +/*! DIS_FLASH_DATA - Flash data cache control + * 0b0..Enables flash data cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash data cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK) + +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK (0x20U) +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT (5U) +/*! CLR_FLASH_CACHE - Clear flash cache control + * 0b0..No clear flash cache + * 0b1..Clears flash cache + */ +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name ROMCR - ROM Wait State */ +/*! @{ */ + +#define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) +#define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) +/*! ROM_WAIT - ROM waiting Arm core and other masters for one cycle + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) +/*! @} */ + +/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ +/*! @{ */ + +#define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) +#define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) +/*! INT0 - SmartDMA hijack NVIC IRQ1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) + +#define SYSCON_SMARTDMAINT_INT1_MASK (0x2U) +#define SYSCON_SMARTDMAINT_INT1_SHIFT (1U) +/*! INT1 - SmartDMA hijack NVIC IRQ17 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK) + +#define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) +#define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) +/*! INT2 - SmartDMA hijack NVIC IRQ18 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) + +#define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) +#define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) +/*! INT3 - SmartDMA hijack NVIC IRQ29 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) + +#define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) +#define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) +/*! INT4 - SmartDMA hijack NVIC IRQ30 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) + +#define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) +#define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) +/*! INT5 - SmartDMA hijack NVIC IRQ31 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) + +#define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) +#define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) +/*! INT6 - SmartDMA hijack NVIC IRQ32 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) + +#define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) +#define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) +/*! INT7 - SmartDMA hijack NVIC IRQ33 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) + +#define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) +#define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) +/*! INT8 - SmartDMA hijack NVIC IRQ34 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) + +#define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) +#define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) +/*! INT9 - SmartDMA hijack NVIC IRQ35 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) + +#define SYSCON_SMARTDMAINT_INT10_MASK (0x400U) +#define SYSCON_SMARTDMAINT_INT10_SHIFT (10U) +/*! INT10 - SmartDMA hijack NVIC IRQ36 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK) + +#define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) +#define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) +/*! INT11 - SmartDMA hijack NVIC IRQ37 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) + +#define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) +#define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) +/*! INT12 - SmartDMA hijack NVIC IRQ38 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) + +#define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) +#define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) +/*! INT13 - SmartDMA hijack NVIC IRQ39 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) + +#define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) +#define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) +/*! INT14 - SmartDMA hijack NVIC IRQ40 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) + +#define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) +#define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) +/*! INT15 - SmartDMA hijack NVIC IRQ41 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) + +#define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) +#define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) +/*! INT16 - SmartDMA hijack NVIC IRQ42 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) + +#define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) +#define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) +/*! INT17 - SmartDMA hijack NVIC IRQ45 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) + +#define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) +#define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) +/*! INT18 - SmartDMA hijack NVIC IRQ47 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) + +#define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) +#define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) +/*! INT19 - SmartDMA hijack NVIC IRQ50 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) + +#define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) +#define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) +/*! INT20 - SmartDMA hijack NVIC IRQ51 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) + +#define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) +#define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) +/*! INT21 - SmartDMA hijack NVIC IRQ66 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) + +#define SYSCON_SMARTDMAINT_INT22_MASK (0x400000U) +#define SYSCON_SMARTDMAINT_INT22_SHIFT (22U) +/*! INT22 - SmartDMA hijack NVIC IRQ67 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT22_SHIFT)) & SYSCON_SMARTDMAINT_INT22_MASK) + +#define SYSCON_SMARTDMAINT_INT23_MASK (0x800000U) +#define SYSCON_SMARTDMAINT_INT23_SHIFT (23U) +/*! INT23 - SmartDMA hijack NVIC IRQ77 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT23_SHIFT)) & SYSCON_SMARTDMAINT_INT23_MASK) +/*! @} */ + +/*! @name ADC1CLKSEL - ADC1 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC1 clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC1CLKDIV - ADC1 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) + +#define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) + +#define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) + +#define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name RAM_INTERLEAVE - Control PKC RAM Interleave Access */ +/*! @{ */ + +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Controls PKC RAM access for PKC RAM 0 and PKC RAM 1 + * 0b1..RAM access to PKC RAM 0 and PKC RAM 1 is interleaved. This setting is need for PKC L0 memory access. + * 0b0..RAM access to PKC RAM 0 and PKC RAM 1 is consecutive. + */ +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) +/*! @} */ + +/*! @name PLLCLKDIVSEL - PLL Clock Divider Clock Selection */ +/*! @{ */ + +#define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) +#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) +/*! SEL - Selects the PLL Clock Divider source clock + * 0b000..PLL0 clock + * 0b001..pll1_clk0 + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKSEL - I3C0 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the I3C0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKDIV - I3C0 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK) + +#define SYSCON_I3C0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKDIV_RESET_MASK) + +#define SYSCON_I3C0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKDIV_HALT_MASK) + +#define SYSCON_I3C0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MICFILFCLKSEL - MICFIL Clock Selection */ +/*! @{ */ + +#define SYSCON_MICFILFCLKSEL_SEL_MASK (0xFU) +#define SYSCON_MICFILFCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the MICFIL clock + * 0b0000..FRO_12M clock + * 0b0001..PLL0 clock + * 0b0010..CLKIN clock + * 0b0011..FRO_HF clock + * 0b0100..PLL1_clk0 clock + * 0b0101..SAI0_MCLK clock + * 0b0110..USB PLL clock + * 0b0111..No clock + * 0b1000..SAI1_MCLK clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_MICFILFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKSEL_SEL_SHIFT)) & SYSCON_MICFILFCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MICFILFCLKDIV - MICFIL Clock Division */ +/*! @{ */ + +#define SYSCON_MICFILFCLKDIV_DIV_MASK (0x7U) +#define SYSCON_MICFILFCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_MICFILFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_DIV_SHIFT)) & SYSCON_MICFILFCLKDIV_DIV_MASK) + +#define SYSCON_MICFILFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MICFILFCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_MICFILFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_RESET_SHIFT)) & SYSCON_MICFILFCLKDIV_RESET_MASK) + +#define SYSCON_MICFILFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MICFILFCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_MICFILFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_HALT_SHIFT)) & SYSCON_MICFILFCLKDIV_HALT_MASK) + +#define SYSCON_MICFILFCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_MICFILFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT)) & SYSCON_MICFILFCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXIOCLKSEL - FLEXIO Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXIO clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..FRO_12M clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKSEL_SEL_SHIFT)) & SYSCON_FLEXIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXIOCLKDIV - FLEXIO Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_DIV_SHIFT)) & SYSCON_FLEXIOCLKDIV_DIV_MASK) + +#define SYSCON_FLEXIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_RESET_SHIFT)) & SYSCON_FLEXIOCLKDIV_RESET_MASK) + +#define SYSCON_FLEXIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_HALT_SHIFT)) & SYSCON_FLEXIOCLKDIV_HALT_MASK) + +#define SYSCON_FLEXIOCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXIOCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXIOCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKSEL - FLEXCAN0 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKDIV - FLEXCAN0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKSEL - FLEXCAN1 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN1 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKDIV - FLEXCAN1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name EWM0CLKSEL - EWM0 Clock Selection */ +/*! @{ */ + +#define SYSCON_EWM0CLKSEL_SEL_MASK (0x1U) +#define SYSCON_EWM0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the EWM0 clock + * 0b0..clk_16k[2] + * 0b1..xtal32k[2] + */ +#define SYSCON_EWM0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EWM0CLKSEL_SEL_SHIFT)) & SYSCON_EWM0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKSEL - WDT1 Clock Selection */ +/*! @{ */ + +#define SYSCON_WDT1CLKSEL_SEL_MASK (0x3U) +#define SYSCON_WDT1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the WDT1 clock + * 0b00..FRO16K clock 2 + * 0b01..fro_hf_div clock + * 0b10..clk_1m clock + * 0b11..clk_1m clock + */ +#define SYSCON_WDT1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKSEL_SEL_SHIFT)) & SYSCON_WDT1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKDIV - WDT1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK) + +#define SYSCON_WDT1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_RESET_SHIFT)) & SYSCON_WDT1CLKDIV_RESET_MASK) + +#define SYSCON_WDT1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_HALT_SHIFT)) & SYSCON_WDT1CLKDIV_HALT_MASK) + +#define SYSCON_WDT1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name OSTIMERCLKSEL - OSTIMER Clock Selection */ +/*! @{ */ + +#define SYSCON_OSTIMERCLKSEL_SEL_MASK (0x3U) +#define SYSCON_OSTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the OS Event Timer clock + * 0b00..clk_16k[2] + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_OSTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OSTIMERCLKSEL_SEL_SHIFT)) & SYSCON_OSTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKSEL - CMP0 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKSEL_SEL_SHIFT)) & SYSCON_CMP0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKDIV - CMP0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_DIV_SHIFT)) & SYSCON_CMP0FCLKDIV_DIV_MASK) + +#define SYSCON_CMP0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_RESET_SHIFT)) & SYSCON_CMP0FCLKDIV_RESET_MASK) + +#define SYSCON_CMP0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_HALT_SHIFT)) & SYSCON_CMP0FCLKDIV_HALT_MASK) + +#define SYSCON_CMP0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP0RRCLKSEL - CMP0 Round Robin Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP0RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0RRCLKDIV - CMP0 Round Robin Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP0RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP0RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP0RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP0RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1FCLKSEL - CMP1 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKSEL_SEL_SHIFT)) & SYSCON_CMP1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1FCLKDIV - CMP1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP1FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_DIV_SHIFT)) & SYSCON_CMP1FCLKDIV_DIV_MASK) + +#define SYSCON_CMP1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_RESET_SHIFT)) & SYSCON_CMP1FCLKDIV_RESET_MASK) + +#define SYSCON_CMP1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_HALT_SHIFT)) & SYSCON_CMP1FCLKDIV_HALT_MASK) + +#define SYSCON_CMP1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1RRCLKSEL - CMP1 Round Robin Clock Source Select */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP1RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1RRCLKDIV - CMP1 Round Robin Clock Division */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP1RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP1RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP1RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP1RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b1..CPU is sleeping + * 0b0..CPU is not sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b1..CPU is in lockup + * 0b0..CPU is not in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) +/*! PARITY_MISS_EN - Enables parity miss. + * 0b0..Disabled + * 0b1..Enables parity, miss on parity error + */ +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b1..Disables write through buffer + * 0b0..Enables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + * 0b0..Write buffer enabled when transaction is bufferable. + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK (0x40U) +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT (6U) +/*! PARITY_FAULT_EN - Enable parity error report. + * 0b1..Enables parity error report + * 0b0..Disables parity error report + */ +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b1..Enabled. + * 0b0..Disabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) +/*! @} */ + +/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - LP_FLEXCOMM Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U) + +/*! @name UTICKCLKSEL - UTICK Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_UTICKCLKSEL_SEL_MASK (0x3U) +#define SYSCON_UTICKCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b00..clk_in + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_UTICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKSEL_SEL_SHIFT)) & SYSCON_UTICKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKSEL - SAI0 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKSEL_SEL_SHIFT)) & SYSCON_SAI0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI1CLKSEL - SAI1 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKSEL_SEL_SHIFT)) & SYSCON_SAI1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKDIV - SAI0 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_DIV_SHIFT)) & SYSCON_SAI0CLKDIV_DIV_MASK) + +#define SYSCON_SAI0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_RESET_SHIFT)) & SYSCON_SAI0CLKDIV_RESET_MASK) + +#define SYSCON_SAI0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_HALT_SHIFT)) & SYSCON_SAI0CLKDIV_HALT_MASK) + +#define SYSCON_SAI0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SAI1CLKDIV - SAI1 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_DIV_SHIFT)) & SYSCON_SAI1CLKDIV_DIV_MASK) + +#define SYSCON_SAI1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_RESET_SHIFT)) & SYSCON_SAI1CLKDIV_RESET_MASK) + +#define SYSCON_SAI1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_HALT_SHIFT)) & SYSCON_SAI1CLKDIV_HALT_MASK) + +#define SYSCON_SAI1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name KEY_RETAIN_CTRL - Key Retain Control */ +/*! @{ */ + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK (0x1U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT (0U) +/*! KEY_RETAIN_VALID - Indicates if the PUF key has been retained in the VBAT domain and has not + * been reset or otherwise invalidated by software. + * 0b0..PUF key is not retained in VBAT domain. + * 0b1..PUF key is retained in VBAT domain. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK (0x2U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT (1U) +/*! KEY_RETAIN_DONE - Indicates the successful completion of the key_save or key_load routine. Once + * set, to clear the key_retain_done flag, both key_save and key_load should be cleared by + * software. + * 0b0..Key save / load sequence has not completed. + * 0b1..Key save / load sequence has completed. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK (0x10000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT (16U) +/*! KEY_SAVE + * 0b0..Key save sequence is disabled. + * 0b1..Key save sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK (0x20000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT (17U) +/*! KEY_LOAD + * 0b0..Key load sequence is disabled. + * 0b1..Key load sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL - FRO 48MHz Reference Clock Control */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) +/*! GDET_REFCLK_EN - GDET reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK) + +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (1U) +/*! TRNG_REFCLK_EN - ELS TRNG reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_SET - FRO 48MHz Reference Clock Control Set */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) +/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) + +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (1U) +/*! TRNG_REFCLK_EN_SET - ELS TRNG reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_CLR - FRO 48MHz Reference Clock Control Clear */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) +/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) + +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (1U) +/*! TRNG_REFCLK_EN_CLR - ELS TRNG reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK) +/*! @} */ + +/*! @name GDETX_CTRL_GDET_CTRL - GDET Control Register */ +/*! @{ */ + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK (0x1U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT (0U) +/*! GDET_EVTCNT_CLR - Controls the GDET clean event counter + * 0b1..Clears event counter + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK (0x2U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT (1U) +/*! GDET_ERR_CLR - Clears GDET error status + * 0b1..Clears error status + * 0b0..Error status not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK (0xCU) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT (2U) +/*! GDET_ISO_SW - GDET isolation control + * 0b10..Isolation is enabled. When both GDET0_CTRL/GDET1_CTRL GDET_ISO_SW are "10", isolation_on is asserted. + * 0b00..Isolation is disabled + * 0b01..Isolation is disabled + * 0b11..Isolation is disabled + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK (0xFF00U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT (8U) +/*! EVENT_CNT - Event count value */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK (0x10000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT (16U) +/*! POS_SYNC - Positive glitch detected + * 0b1..Positive glitch detected + * 0b0..Positive glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK (0x20000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT (17U) +/*! NEG_SYNC - Negative glitch detected + * 0b1..Negative glitch detected + * 0b0..Negative glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK (0x40000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT (18U) +/*! EVENT_CLR_FLAG - Event counter cleared + * 0b1..Event counter cleared + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK) +/*! @} */ + +/* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) + +/*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ +/*! @{ */ + +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) +/*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the + * ELS module. Refer to the ELS chapter in the SRM for more details. + * 0b00..ELS asset is protected + * 0b10..ELS asset is protected + * 0b11..ELS asset is protected + * 0b01..ELS asset is not protected + */ +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL - ELS Lock Control */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - ELS Lock Control */ +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) +/*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name ELS_TEMPORAL_STATE - ELS Temporal State */ +/*! @{ */ + +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) +/*! TEMPORAL_STATE - Temporal state */ +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) +/*! @} */ + +/*! @name ELS_KDF_MASK - Key Derivation Function Mask */ +/*! @{ */ + +#define SYSCON_ELS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT (0U) +/*! KDF_MASK - Key derivation function mask */ +#define SYSCON_ELS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_ELS_KDF_MASK_KDF_MASK_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG0 - ELS AS Configuration */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) +/*! CFG_LC_STATE - LC state configuration bit */ +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK (0x200U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT (9U) +/*! CFG_LVD_CORE_RESET_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK (0x800U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT (11U) +/*! CFG_LVD_CORE_IRQ_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT (12U) +/*! CFG_WDT0_ENABLED - When WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK (0x2000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT (13U) +/*! CFG_CWDT0_ENABLED - When Code WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK (0x4000U) +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT (14U) +/*! CFG_ELS_GDET_ENABLED - When either GDET is enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK (0x8000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT (15U) +/*! CFG_ANA_GDET_RESET_ENABLED - When SPC analog glitch detect reset is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK (0x10000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT (16U) +/*! CFG_ANA_GDET_IRQ_ENABLED - When SPC analog glitch detect IRQ is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) +/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in TDET, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK (0x40000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT (18U) +/*! CFG_LVD_VSYS_RESET_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK (0x80000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT (19U) +/*! CFG_LVD_VDDIO_RESET_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK (0x100000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT (20U) +/*! CFG_LVD_VSYS_IRQ_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK (0x200000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT (21U) +/*! CFG_LVD_VDDIO_IRQ_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK (0x400000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT (22U) +/*! CFG_WDT1_ENABLED - When WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK (0x800000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT (23U) +/*! CFG_CWDT1_ENABLED - When Code WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK (0x1000000U) +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT (24U) +/*! CFG_TEMPTAMPER_DET_ENABLED - When temperature tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK (0x2000000U) +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT (25U) +/*! CFG_VOLTAMPER_DET_ENABLED - When voltage tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT (26U) +/*! CFG_LHTTAMPER_DET_ENABLED - When light tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U) +/*! CFG_CLKTAMPER_DET_ENABLED - When clk tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) +/*! CFG_QK_DISABLE_ENROLL - When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) +/*! CFG_QK_DISABLE_WRAP - When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG1 - ELS AS Configuration1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) +/*! CFG_SEC_DIS_STRICT_MODE - When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE + * bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this + * bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) +/*! CFG_SEC_DIS_VIOL_ABORT - When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) +/*! CFG_SEC_ENA_NS_PRIV_CHK - When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) +/*! CFG_SEC_ENA_S_PRIV_CHK - When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) +/*! CFG_SEC_ENA_SEC_CHK - When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) +/*! CFG_SEC_IDAU_ALLNS - When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB + * secure controller are equal to 01, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) +/*! CFG_SEC_LOCK_NS_MPU - When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) +/*! CFG_SEC_LOCK_NS_VTOR - When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) +/*! CFG_SEC_LOCK_S_MPU - When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) +/*! CFG_SEC_LOCK_S_VTAIRCR - When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure + * controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) +/*! CFG_SEC_LOCK_SAU - When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) + +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK (0x1FE000U) +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT (13U) +/*! METAL_VERSION - metal version */ +#define SYSCON_ELS_AS_CFG1_METAL_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK (0x1E00000U) +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT (21U) +/*! ROM_PATCH_VERSION - ROM patch version */ +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT (26U) +/*! CFG_HVD_CORE_RESET_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT (27U) +/*! CFG_HVD_CORE_IRQ_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT (28U) +/*! CFG_HVD_VSYS_RESET_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT (29U) +/*! CFG_HVD_VDDIO_RESET_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK (0x40000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT (30U) +/*! CFG_HVD_VSYS_IRQ_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK (0x80000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT (31U) +/*! CFG_HVD_VDDIO_IRQ_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG2 - ELS AS Configuration2 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT (0U) +/*! CFG_ELS_CMD_EN - ELS configuration command enable bit */ +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT)) & SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG3 - ELS AS Configuration3 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Device type identification data */ +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT)) & SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name ELS_AS_ST0 - ELS AS State Register */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) +/*! ST_TEMPORAL_STATE - TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register */ +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) +/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) +/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) +/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) +/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) +/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) +/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. */ +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) +/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK (0x10000U) +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT (16U) +/*! ST_XO40M_FAILED - When XO40M oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK (0x20000U) +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT (17U) +/*! ST_IFR_LOAD_FAILED - When IFR load fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK (0x3C0000U) +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT (18U) +/*! ST_GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output. */ +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT)) & SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK) +/*! @} */ + +/*! @name ELS_AS_ST1 - ELS AS State1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) +/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) +/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK) + +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) +/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK (0xC0U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) +/*! ST_DCDC_VOUT - VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK (0x300U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT (8U) +/*! ST_DCDC_DS - DCDC drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) +/*! ST_BOOT_MODE - ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP + * mode during boot, ISP pin should be pull down when out of reset. + */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) +/*! ST_BOOT_RETRY_CNT - BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK (0x30000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT (16U) +/*! ST_LDO_CORE_VOUT - VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK (0xC0000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT (18U) +/*! ST_LDO_CORE_DS - LDO_CORE drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG0 - Boot state captured during boot: Main ROM log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK (0xFU) +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT (0U) +/*! BOOT_IMAGE - Boot image source used during this boot. + * 0b0000..Internal flash image 0 + * 0b0001..Internal flash image 1 + * 0b0010..FlexSPI flash image 0 + * 0b0011..FlexSPI flash image 1 + * 0b0100..Recovery SPI flash image + * 0b0101..Serial boot image (write-memory and execute ISP command used) + * 0b0110..Receive SB3 containing SB_JUMP command is used. + * 0b0111..Customer SBL/recovery image (Bank1 IFR0). + * 0b1000..NXP MAD recovery image (Bank1 IFR0). + * 0b1001..NXP ROM extension (NMPA - Bank0 IFR0). + * 0b1010..Reserved. + * 0b1011..Reserved. + * 0b1100..Reserved. + * 0b1101..Reserved. + * 0b1110..Reserved. + * 0b1111..Reserved. + */ +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK (0x10U) +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT (4U) +/*! CMAC - CMAC verify is used instead of ECDSA verify on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK (0x40U) +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT (6U) +/*! ECDSA - ECDSA P-384 verification is done on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK (0x80U) +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT (7U) +/*! OFF_CHIP - Off-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK (0x100U) +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT (8U) +/*! ON_CHIP - On-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK (0x200U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT (9U) +/*! CDI_CSR - CDI based device keys are derived for CSR harvesting on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK (0x400U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT (10U) +/*! CDI_DICE - CDI per DICE specification is computed on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK (0x800U) +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT (11U) +/*! TRUSTZONE - TrustZone preset data is loaded during this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK (0x1000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT (12U) +/*! DEBUG_AUTH - Debug authentication done in this session prior to boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK (0x2000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT (13U) +/*! ITRC - ITRC zeroize event is handled in this session of boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK (0x4000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT (14U) +/*! DIG_GDET - Digital glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK (0x8000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT (15U) +/*! ANA_GDET - Analog glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK (0x10000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT (16U) +/*! DEEP_PD - Boot from deep-power down state. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK (0xF000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT (24U) +/*! LOW_POWER - Last low-power mode value. ROM copies SPC_LP_MODE field from SPC->SC[7:4]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK (0x80000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT (31U) +/*! ISP - ISP pin state at boot time. ROM copies CMC->MR0[0]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT (0U) +/*! RoTK - RoTK index used for this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK (0x3FCU) +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT (2U) +/*! FIPS - FIPS self-test is executed and PASS during this boot. When a bit is set, means self-test + * is executed and it FAILS. When a bit is clear, means corresponding self-test is executed and + * PASS or it is not executed. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK (0xC00U) +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT (10U) +/*! SB3 - SB3 type (valid after nboot_sb3_load_manifest()). + * 0b00..customer fw load/update file. + * 0b01..NXP Provisioning FW. + * 0b10..ELS signed OEM Provisioning FW. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_SB3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG2 - Boot state captured during boot: Hardware status signals log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK (0x3FU) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT (0U) +/*! CMC_SRS0 - CMC->SRS[5:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK (0xC0U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT (6U) +/*! VBAT_STATUS0 - VBAT->STATUSA[1:0] | ~VBAT->STATUSB[1:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK (0x1FF00U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT (8U) +/*! CMC_SRS1 - CMC->SRS[16:8] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK (0xFC0000U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT (18U) +/*! VBAT_STATUS1 - VBAT->STATUSA[11:6] | ~VBAT->STATUSB[11:6] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK (0xFF000000U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT (24U) +/*! CMC_SRS2 - CMC->SRS[31:24] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG3 - Boot state captured during boot: Security log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK (0xFFU) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT (0U) +/*! ERR_AUTH_FAIL_COUNT - CFPA->ERR_AUTH_FAIL_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK (0xFF00U) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) +/*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) +/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug + * access. The register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK (0x8U) +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT (3U) +/*! EFUSE_ATTACK_DETECT - OTPC can output attack_detect signal when it detects attack when load + * shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status + * can be recorded. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT)) & SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK (0x20U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT (5U) +/*! FLAG_LVD_CORE_OCCURED - This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK (0x100U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT (8U) +/*! FLAG_WDT0_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK (0x200U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT (9U) +/*! FLAG_CWDT0_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK (0x400U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT (10U) +/*! FLAG_WDT0_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK (0x800U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT (11U) +/*! FLAG_CWDT0_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) +/*! FLAG_QK_ERROR - This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK (0x2000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT (13U) +/*! FLAG_ELS_GLITCH_DETECTED - This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) +/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON + * block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) +/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set as 1 when tamper event is flagged from TDET. + * This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is + * cleared by software. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) +/*! FLAG_FLASH_ECC_INVALID - This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) +/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) +/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure code + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) +/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure data + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK (0x100000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT (20U) +/*! FLAG_LVD_VSYS_OCCURED - This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK (0x200000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT (21U) +/*! FLAG_LVD_VDDIO_OCCURED - This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK (0x400000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT (22U) +/*! FLAG_WDT1_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK (0x800000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT (23U) +/*! FLAG_CWDT1_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK (0x1000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT (24U) +/*! FLAG_WDT1_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK (0x2000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT (25U) +/*! FLAG_CWDT1_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U) +/*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when temperature temper IRQ is + * enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK (0x8000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT (27U) +/*! FLAG_VOLTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when voltage temper IRQ is enabled + * and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK (0x10000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT (28U) +/*! FLAG_LHTTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when light temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (29U) +/*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when clock temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG1 - ELS AS Flag1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT (29U) +/*! FLAG_HVD_CORE_OCCURED - This flag bit is set as 1 when HVD from VDD_CORE power domain is triggered. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK (0x40000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT (30U) +/*! FLAG_HVD_VSYS_OCCURED - This flag bit is set as 1 when HVD from VDD_SYS power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK (0x80000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT (31U) +/*! FLAG_HVD_VDDIO_OCCURED - This flag bit is set as 1 when HVD from VDD power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Clock Control */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) +/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT (2U) +/*! FRO1MHZ_ENA - Enables the FRO_1MHz clock for RTC module and for UTICK + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) +/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT (4U) +/*! FRO_HF_ENA - Enables FRO HF clock for the Frequency Measure module + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enables FRO_1MHz clock for clock muxing in clock gen + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +/*! @} */ + +/*! @name I3C1FCLKSEL - I3C1 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - I3C1 clock select + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C1FCLKDIV - I3C1 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C1FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKDIV_DIV_MASK) + +#define SYSCON_I3C1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKDIV_RESET_MASK) + +#define SYSCON_I3C1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKDIV_HALT_MASK) + +#define SYSCON_I3C1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray code_gray[31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray code_gray[41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control Automatic Clock Gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Controls automatic clock gating for the RAMB Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Controls automatic clock gating for the RAMC Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Controls automatic clock gating for the RAMD Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Controls automatic clock gating for the RAMD Controller. + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDEC - Control Automatic Clock Gating C */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK (0x40000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT (30U) +/*! RAMX - Controls automatic clock gating of the RAMX controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK (0x80000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT (31U) +/*! RAMA - Controls automatic clock gating of the RAMA controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM0 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM0 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM0 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM0 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM1 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM1 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM1 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM1 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name ECC_ENABLE_CTRL - RAM ECC Enable Control */ +/*! @{ */ + +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK (0x2U) +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT (1U) +/*! RAMB_RAMX_ECC_ENABLE - RAMB and RAMX ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK (0x4U) +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT (2U) +/*! RAMD_RAMC_ECC_ENABLE - RAMD and RAMC ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b1010..Enables write access to all registers + * 0b0000..Any other value than b1010: disables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) +/*! @} */ + +/* The count of SYSCON_SWD_ACCESS_CPU */ +#define SYSCON_SWD_ACCESS_CPU_COUNT (1U) + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Indicates DEVICE TYPE. */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip Revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) +#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) +/*! MINOR_REVISION - Chip minor revision */ +#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) + +#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) +#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) +/*! MAJOR_REVISION - Chip major revision */ +#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) +/*! MCO_NUM_IN_DIE_ID - Chip number */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif +/* Backward compatibility */ +#define SYSCON SYSCON0 + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer + * @{ + */ + +/** SYSPM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t PMCR; /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x18, array step: index*0x30, index2*0x8 */ + __I uint8_t HI; /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */ + uint8_t RESERVED_0[3]; + __I uint32_t LO; /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */ + } PMECTR[3]; + } PMCR[1]; +} SYSPM_Type; + +/* ---------------------------------------------------------------------------- + -- SYSPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Register_Masks SYSPM Register Masks + * @{ + */ + +/*! @name PMCR - Performance Monitor Control */ +/*! @{ */ + +#define SYSPM_PMCR_MENB_MASK (0x1U) +#define SYSPM_PMCR_MENB_SHIFT (0U) +/*! MENB - Module Is Enabled + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSPM_PMCR_MENB(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK) + +#define SYSPM_PMCR_SSC_MASK (0xEU) +#define SYSPM_PMCR_SSC_SHIFT (1U) +/*! SSC - Start and Stop Control + * 0b000..Idle or no-op + * 0b001..Local stop + * 0b010, 0b011..Local start + * 0b100.. + * 0b101.. + * 0b110, 0b111.. + */ +#define SYSPM_PMCR_SSC(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK) + +#define SYSPM_PMCR_CMODE_MASK (0x30U) +#define SYSPM_PMCR_CMODE_SHIFT (4U) +/*! CMODE - Count Mode + * 0b00..Counted in both User and Privileged modes + * 0b01.. + * 0b10..Counted only in User mode + * 0b11..Counted only in Privileged mode + */ +#define SYSPM_PMCR_CMODE(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK) + +#define SYSPM_PMCR_RECTR1_MASK (0x100U) +#define SYSPM_PMCR_RECTR1_SHIFT (8U) +/*! RECTR1 - Reset Event Counter 1 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK) + +#define SYSPM_PMCR_RECTR2_MASK (0x200U) +#define SYSPM_PMCR_RECTR2_SHIFT (9U) +/*! RECTR2 - Reset Event Counter 2 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK) + +#define SYSPM_PMCR_RECTR3_MASK (0x400U) +#define SYSPM_PMCR_RECTR3_SHIFT (10U) +/*! RECTR3 - Reset Event Counter 3 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK) + +#define SYSPM_PMCR_SELEVT1_MASK (0x3F800U) +#define SYSPM_PMCR_SELEVT1_SHIFT (11U) +/*! SELEVT1 - Select Event 1 */ +#define SYSPM_PMCR_SELEVT1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK) + +#define SYSPM_PMCR_SELEVT2_MASK (0x1FC0000U) +#define SYSPM_PMCR_SELEVT2_SHIFT (18U) +/*! SELEVT2 - Select Event 2 */ +#define SYSPM_PMCR_SELEVT2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK) + +#define SYSPM_PMCR_SELEVT3_MASK (0xFE000000U) +#define SYSPM_PMCR_SELEVT3_SHIFT (25U) +/*! SELEVT3 - Select Event 3 */ +#define SYSPM_PMCR_SELEVT3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR */ +#define SYSPM_PMCR_COUNT (1U) + +/*! @name PMCR_PMECTR_HI - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_HI_ECTR_MASK (0xFFU) +#define SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_HI_ECTR(x) (((uint8_t)(((uint8_t)(x)) << SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_HI_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT2 (3U) + +/*! @name PMCR_PMECTR_LO - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_LO_ECTR_MASK (0xFFFFFFFFU) +#define SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_LO_ECTR(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_LO_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT2 (3U) + + +/*! + * @} + */ /* end of group SYSPM_Register_Masks */ + + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } +#endif + +/*! + * @} + */ /* end of group SYSPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1CC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_0[224]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer + * @{ + */ + +/** USBHS - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USBHS_Type; + +/* ---------------------------------------------------------------------------- + -- USBHS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Register_Masks USBHS Register Masks + * @{ + */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define USBHS_ID_ID_MASK (0x3FU) +#define USBHS_ID_ID_SHIFT (0U) +/*! ID - Configuration Number */ +#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) + +#define USBHS_ID_NID_MASK (0x3F00U) +#define USBHS_ID_NID_SHIFT (8U) +/*! NID - Complement Version of ID */ +#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) + +#define USBHS_ID_REVISION_MASK (0xFF0000U) +#define USBHS_ID_REVISION_SHIFT (16U) +/*! REVISION - Revision Number of the Controller Core */ +#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ + +#define USBHS_HWGENERAL_PHYW_MASK (0x30U) +#define USBHS_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW - Data width of the transceiver connected to the controller core + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) + */ +#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK) + +#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) +#define USBHS_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM - Transceiver Type + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK) + +#define USBHS_HWGENERAL_SM_MASK (0x600U) +#define USBHS_HWGENERAL_SM_SHIFT (9U) +/*! SM - Serial interface mode capability + * 0b00..No Serial Engine, always use parallel signalling + * 0b01..Serial Engine present, always use serial signalling for FS/LS + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWHOST_HC_MASK (0x1U) +#define USBHS_HWHOST_HC_SHIFT (0U) +/*! HC - Host Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK) + +#define USBHS_HWHOST_NPORT_MASK (0xEU) +#define USBHS_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ +#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWDEVICE_DC_MASK (0x1U) +#define USBHS_HWDEVICE_DC_SHIFT (0U) +/*! DC - Device Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK) + +#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) +#define USBHS_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - Device Endpoint Number */ +#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) +#define USBHS_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - Default burst size for memory to TX buffer transfer */ +#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) + +#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ +#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) +#define USBHS_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - Default burst size for memory to RX buffer transfer */ +#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) + +#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) +#define USBHS_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ +#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ + +#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER0CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USBHS_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ + +#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER1CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USBHS_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ + +#define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) +#define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST - AHB master interface Burst configuration + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USBHS_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_SBUSCFG_AHBBRST_SHIFT)) & USBHS_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ + +#define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of + * the Operational Register. Default value is '40h'. + */ +#define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ + +#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - Host Controller Interface Version Number */ +#define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - Number of Downstream Ports */ +#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) + +#define USBHS_HCSPARAMS_PPC_MASK (0x10U) +#define USBHS_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - Port Power Control */ +#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) + +#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - Number of Ports per Companion Controller */ +#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) + +#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) +#define USBHS_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC - Number of Companion Controller + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported + */ +#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) + +#define USBHS_HCSPARAMS_PI_MASK (0x10000U) +#define USBHS_HCSPARAMS_PI_SHIFT (16U) +/*! PI - Port Indicators (P INDICATOR) */ +#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) + +#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - Number of Ports per Transaction Translator */ +#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) + +#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USBHS_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - Number of Transaction Translators */ +#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_HCCPARAMS_ADC_MASK (0x1U) +#define USBHS_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - 64-bit Addressing Capability */ +#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) + +#define USBHS_HCCPARAMS_PFL_MASK (0x2U) +#define USBHS_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - Programmable Frame List Flag */ +#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) + +#define USBHS_HCCPARAMS_ASP_MASK (0x4U) +#define USBHS_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - Asynchronous Schedule Park Capability */ +#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) + +#define USBHS_HCCPARAMS_IST_MASK (0xF0U) +#define USBHS_HCCPARAMS_IST_SHIFT (4U) +/*! IST - Isochronous Scheduling Threshold */ +#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) + +#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) +#define USBHS_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EHCI Extended Capabilities Pointer */ +#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ + +#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - Device Controller Interface Version Number */ +#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_DCCPARAMS_DEN_MASK (0x1FU) +#define USBHS_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - Device Endpoint Number */ +#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) + +#define USBHS_DCCPARAMS_DC_MASK (0x80U) +#define USBHS_DCCPARAMS_DC_SHIFT (7U) +/*! DC - Device Capable */ +#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) + +#define USBHS_DCCPARAMS_HC_MASK (0x100U) +#define USBHS_DCCPARAMS_HC_SHIFT (8U) +/*! HC - Host Capable */ +#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command */ +/*! @{ */ + +#define USBHS_USBCMD_RS_MASK (0x1U) +#define USBHS_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop + * 0b0..Stop + * 0b1..Run + */ +#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) + +#define USBHS_USBCMD_RST_MASK (0x2U) +#define USBHS_USBCMD_RST_SHIFT (1U) +/*! RST - Controller Reset */ +#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) + +#define USBHS_USBCMD_FS_1_MASK (0xCU) +#define USBHS_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - Frame List Size */ +#define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) + +#define USBHS_USBCMD_PSE_MASK (0x10U) +#define USBHS_USBCMD_PSE_SHIFT (4U) +/*! PSE - Periodic Schedule Enable + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule + */ +#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) + +#define USBHS_USBCMD_ASE_MASK (0x20U) +#define USBHS_USBCMD_ASE_SHIFT (5U) +/*! ASE - Asynchronous Schedule Enable + * 0b0..Do not process the Asynchronous Schedule + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule + */ +#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) + +#define USBHS_USBCMD_IAA_MASK (0x40U) +#define USBHS_USBCMD_IAA_SHIFT (6U) +/*! IAA - Interrupt on Async Advance Doorbell */ +#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) + +#define USBHS_USBCMD_ASP_MASK (0x300U) +#define USBHS_USBCMD_ASP_SHIFT (8U) +/*! ASP - Asynchronous Schedule Park Mode Count */ +#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) + +#define USBHS_USBCMD_ASPE_MASK (0x800U) +#define USBHS_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - Asynchronous Schedule Park Mode Enable */ +#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) + +#define USBHS_USBCMD_SUTW_MASK (0x2000U) +#define USBHS_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - Setup TripWire [device mode only] */ +#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) + +#define USBHS_USBCMD_ATDTW_MASK (0x4000U) +#define USBHS_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - Add dTD TripWire[device mode only] */ +#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) + +#define USBHS_USBCMD_FS_2_MASK (0x8000U) +#define USBHS_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 - Frame List Size [host mode only] */ +#define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) + +#define USBHS_USBCMD_ITC_MASK (0xFF0000U) +#define USBHS_USBCMD_ITC_SHIFT (16U) +/*! ITC - Interrupt Threshold Control + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status */ +/*! @{ */ + +#define USBHS_USBSTS_UI_MASK (0x1U) +#define USBHS_USBSTS_UI_SHIFT (0U) +/*! UI - USB Interrupt (USBINT) */ +#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) + +#define USBHS_USBSTS_UEI_MASK (0x2U) +#define USBHS_USBSTS_UEI_SHIFT (1U) +/*! UEI - USB Error Interrupt (USBERRINT) */ +#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) + +#define USBHS_USBSTS_PCI_MASK (0x4U) +#define USBHS_USBSTS_PCI_SHIFT (2U) +/*! PCI - Port Change Detect */ +#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) + +#define USBHS_USBSTS_FRI_MASK (0x8U) +#define USBHS_USBSTS_FRI_SHIFT (3U) +/*! FRI - Frame List Rollover */ +#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) + +#define USBHS_USBSTS_SEI_MASK (0x10U) +#define USBHS_USBSTS_SEI_SHIFT (4U) +/*! SEI - System Error */ +#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) + +#define USBHS_USBSTS_AAI_MASK (0x20U) +#define USBHS_USBSTS_AAI_SHIFT (5U) +/*! AAI - Interrupt on Async Advance */ +#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) + +#define USBHS_USBSTS_URI_MASK (0x40U) +#define USBHS_USBSTS_URI_SHIFT (6U) +/*! URI - USB Reset Received */ +#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) + +#define USBHS_USBSTS_SRI_MASK (0x80U) +#define USBHS_USBSTS_SRI_SHIFT (7U) +/*! SRI - SOF Received */ +#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) + +#define USBHS_USBSTS_SLI_MASK (0x100U) +#define USBHS_USBSTS_SLI_SHIFT (8U) +/*! SLI - DCSuspend */ +#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) + +#define USBHS_USBSTS_ULPII_MASK (0x400U) +#define USBHS_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPI Interrupt */ +#define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) + +#define USBHS_USBSTS_HCH_MASK (0x1000U) +#define USBHS_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCHaIted */ +#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) + +#define USBHS_USBSTS_RCL_MASK (0x2000U) +#define USBHS_USBSTS_RCL_SHIFT (13U) +/*! RCL - Reclamation */ +#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) + +#define USBHS_USBSTS_PS_MASK (0x4000U) +#define USBHS_USBSTS_PS_SHIFT (14U) +/*! PS - Periodic Schedule Status */ +#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) + +#define USBHS_USBSTS_AS_MASK (0x8000U) +#define USBHS_USBSTS_AS_SHIFT (15U) +/*! AS - Asynchronous Schedule Status */ +#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) + +#define USBHS_USBSTS_NAKI_MASK (0x10000U) +#define USBHS_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAK Interrupt Bit */ +#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) + +#define USBHS_USBSTS_TI0_MASK (0x1000000U) +#define USBHS_USBSTS_TI0_SHIFT (24U) +/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ +#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) + +#define USBHS_USBSTS_TI1_MASK (0x2000000U) +#define USBHS_USBSTS_TI1_SHIFT (25U) +/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ +#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable */ +/*! @{ */ + +#define USBHS_USBINTR_UE_MASK (0x1U) +#define USBHS_USBINTR_UE_SHIFT (0U) +/*! UE - USB Interrupt Enable */ +#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) + +#define USBHS_USBINTR_UEE_MASK (0x2U) +#define USBHS_USBINTR_UEE_SHIFT (1U) +/*! UEE - USB Error Interrupt Enable */ +#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) + +#define USBHS_USBINTR_PCE_MASK (0x4U) +#define USBHS_USBINTR_PCE_SHIFT (2U) +/*! PCE - Port Change Detect Interrupt Enable */ +#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) + +#define USBHS_USBINTR_FRE_MASK (0x8U) +#define USBHS_USBINTR_FRE_SHIFT (3U) +/*! FRE - Frame List Rollover Interrupt Enable */ +#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) + +#define USBHS_USBINTR_SEE_MASK (0x10U) +#define USBHS_USBINTR_SEE_SHIFT (4U) +/*! SEE - System Error Interrupt Enable */ +#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) + +#define USBHS_USBINTR_AAE_MASK (0x20U) +#define USBHS_USBINTR_AAE_SHIFT (5U) +/*! AAE - Async Advance Interrupt Enable */ +#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) + +#define USBHS_USBINTR_URE_MASK (0x40U) +#define USBHS_USBINTR_URE_SHIFT (6U) +/*! URE - USB Reset Interrupt Enable */ +#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) + +#define USBHS_USBINTR_SRE_MASK (0x80U) +#define USBHS_USBINTR_SRE_SHIFT (7U) +/*! SRE - SOF Received Interrupt Enable */ +#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) + +#define USBHS_USBINTR_SLE_MASK (0x100U) +#define USBHS_USBINTR_SLE_SHIFT (8U) +/*! SLE - Sleep Interrupt Enable */ +#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) + +#define USBHS_USBINTR_NAKE_MASK (0x10000U) +#define USBHS_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAK Interrupt Enable */ +#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) + +#define USBHS_USBINTR_UAIE_MASK (0x40000U) +#define USBHS_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - USB Host Asynchronous Interrupt Enable */ +#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) + +#define USBHS_USBINTR_UPIE_MASK (0x80000U) +#define USBHS_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - USB Host Periodic Interrupt Enable */ +#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) + +#define USBHS_USBINTR_TIE0_MASK (0x1000000U) +#define USBHS_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - General Purpose Timer #0 Interrupt Enable */ +#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) + +#define USBHS_USBINTR_TIE1_MASK (0x2000000U) +#define USBHS_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - General Purpose Timer #1 Interrupt Enable */ +#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ + +#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USBHS_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX - Frame Index + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ + +#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - Device Address Advance */ +#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) + +#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USBHS_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - Device Address */ +#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ + +#define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - Base Address (Low) */ +#define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ + +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - Link Pointer Low (LPL) */ +#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ + +#define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - Endpoint List Pointer (Low) */ +#define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ + +#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - Programmable RX Burst Size */ +#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) + +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - Programmable TX Burst Size */ +#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ + +#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - Scheduler Overhead */ +#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) + +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - Scheduler Health Counter */ +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) + +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - FIFO Burst Threshold */ +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ + +#define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) +#define USBHS_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - RX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) + +#define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USBHS_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - TX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ + +#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - RX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) + +#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - TX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag */ +/*! @{ */ + +#define USBHS_CONFIGFLAG_CF_MASK (0x1U) +#define USBHS_CONFIGFLAG_CF_SHIFT (0U) +/*! CF - Configure Flag + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller + * 0b1..Port routing control logic default-routes all ports to this host controller + */ +#define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ + +#define USBHS_PORTSC1_CCS_MASK (0x1U) +#define USBHS_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status + * 0b0..In Host mode: No device is present. In Device mode: Not attached + * 0b1..In Host mode: Device is present on port. In Device mode: Attached + */ +#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) + +#define USBHS_PORTSC1_CSC_MASK (0x2U) +#define USBHS_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change + * 0b0..No change + * 0b1..Change in current connect status + */ +#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) + +#define USBHS_PORTSC1_PE_MASK (0x4U) +#define USBHS_PORTSC1_PE_SHIFT (2U) +/*! PE - Port Enabled/Disabled + * 0b0..Disable + * 0b1..Enable + */ +#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) + +#define USBHS_PORTSC1_PEC_MASK (0x8U) +#define USBHS_PORTSC1_PEC_SHIFT (3U) +/*! PEC - Port Enable/Disable Change + * 0b0..No change + * 0b1..Port enabled/disabled status has changed + */ +#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) + +#define USBHS_PORTSC1_OCA_MASK (0x10U) +#define USBHS_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-Current Active + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition + */ +#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) + +#define USBHS_PORTSC1_OCC_MASK (0x20U) +#define USBHS_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current Change */ +#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) + +#define USBHS_PORTSC1_FPR_MASK (0x40U) +#define USBHS_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume + * 0b0..No resume (K-state) detected/driven on port + * 0b1..Resume detected/driven on port + */ +#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) + +#define USBHS_PORTSC1_SUSP_MASK (0x80U) +#define USBHS_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Port not in suspend state + * 0b1..Port in suspend state + */ +#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) + +#define USBHS_PORTSC1_PR_MASK (0x100U) +#define USBHS_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset + * 0b0..Port is not in reset + * 0b1..Port is in reset + */ +#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) + +#define USBHS_PORTSC1_HSP_MASK (0x200U) +#define USBHS_PORTSC1_HSP_SHIFT (9U) +/*! HSP - High-Speed Port */ +#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) + +#define USBHS_PORTSC1_LS_MASK (0xC00U) +#define USBHS_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK) + +#define USBHS_PORTSC1_PP_MASK (0x1000U) +#define USBHS_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power */ +#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) + +#define USBHS_PORTSC1_PO_MASK (0x2000U) +#define USBHS_PORTSC1_PO_SHIFT (13U) +/*! PO - Port Owner */ +#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) + +#define USBHS_PORTSC1_PIC_MASK (0xC000U) +#define USBHS_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK) + +#define USBHS_PORTSC1_PTC_MASK (0xF0000U) +#define USBHS_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved + */ +#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK) + +#define USBHS_PORTSC1_WKCN_MASK (0x100000U) +#define USBHS_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - Wake on Connect Enable (WKCNNT_E) */ +#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) + +#define USBHS_PORTSC1_WKDC_MASK (0x200000U) +#define USBHS_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ +#define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) + +#define USBHS_PORTSC1_WKOC_MASK (0x400000U) +#define USBHS_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - Wake on Over-current Enable (WKOC_E) */ +#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) + +#define USBHS_PORTSC1_PHCD_MASK (0x800000U) +#define USBHS_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK) + +#define USBHS_PORTSC1_PFSC_MASK (0x1000000U) +#define USBHS_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC - Port Force Full Speed Connect + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK) + +#define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) +#define USBHS_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) + +#define USBHS_PORTSC1_PSPD_MASK (0xC000000U) +#define USBHS_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD - Port Speed + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK) + +#define USBHS_PORTSC1_PTW_MASK (0x10000000U) +#define USBHS_PORTSC1_PTW_SHIFT (28U) +/*! PTW - Parallel Transceiver Width - Read/Write + * 0b0..Select the 8-bit UTMI interface [60 MHz] + * 0b1..Select the 16-bit UTMI interface [30 MHz] + */ +#define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) + +#define USBHS_PORTSC1_STS_MASK (0x20000000U) +#define USBHS_PORTSC1_STS_SHIFT (29U) +/*! STS - Serial Transceiver Select + * 0b0..Parallel Interface signals is selected + * 0b1..Serial Interface Engine is selected + */ +#define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) + +#define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USBHS_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & Control */ +/*! @{ */ + +#define USBHS_OTGSC_VD_MASK (0x1U) +#define USBHS_OTGSC_VD_SHIFT (0U) +/*! VD - VBUS Discharge */ +#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) + +#define USBHS_OTGSC_VC_MASK (0x2U) +#define USBHS_OTGSC_VC_SHIFT (1U) +/*! VC - VBUS Charge */ +#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) + +#define USBHS_OTGSC_OT_MASK (0x8U) +#define USBHS_OTGSC_OT_SHIFT (3U) +/*! OT - OTG Termination */ +#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) + +#define USBHS_OTGSC_DP_MASK (0x10U) +#define USBHS_OTGSC_DP_SHIFT (4U) +/*! DP - Data Pulsing */ +#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) + +#define USBHS_OTGSC_IDPU_MASK (0x20U) +#define USBHS_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - ID Pullup + * 0b0..Off + * 0b1..On + */ +#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) + +#define USBHS_OTGSC_ID_MASK (0x100U) +#define USBHS_OTGSC_ID_SHIFT (8U) +/*! ID - USB ID + * 0b0..A device + * 0b1..B device + */ +#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) + +#define USBHS_OTGSC_AVV_MASK (0x200U) +#define USBHS_OTGSC_AVV_SHIFT (9U) +/*! AVV - A VBus Valid */ +#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) + +#define USBHS_OTGSC_ASV_MASK (0x400U) +#define USBHS_OTGSC_ASV_SHIFT (10U) +/*! ASV - A Session Valid */ +#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) + +#define USBHS_OTGSC_BSV_MASK (0x800U) +#define USBHS_OTGSC_BSV_SHIFT (11U) +/*! BSV - B Session Valid */ +#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) + +#define USBHS_OTGSC_BSE_MASK (0x1000U) +#define USBHS_OTGSC_BSE_SHIFT (12U) +/*! BSE - B Session End */ +#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) + +#define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) +#define USBHS_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - 1 Millisecond Timer Toggle */ +#define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) + +#define USBHS_OTGSC_DPS_MASK (0x4000U) +#define USBHS_OTGSC_DPS_SHIFT (14U) +/*! DPS - Data Bus Pulsing Status */ +#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) + +#define USBHS_OTGSC_IDIS_MASK (0x10000U) +#define USBHS_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - USB ID Interrupt Status */ +#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) + +#define USBHS_OTGSC_AVVIS_MASK (0x20000U) +#define USBHS_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - A VBus Valid Interrupt Status */ +#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) + +#define USBHS_OTGSC_ASVIS_MASK (0x40000U) +#define USBHS_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - A Session Valid Interrupt Status */ +#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) + +#define USBHS_OTGSC_BSVIS_MASK (0x80000U) +#define USBHS_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - B Session Valid Interrupt Status */ +#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) + +#define USBHS_OTGSC_BSEIS_MASK (0x100000U) +#define USBHS_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - B Session End Interrupt Status */ +#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) + +#define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ +#define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) + +#define USBHS_OTGSC_DPIS_MASK (0x400000U) +#define USBHS_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - Data Pulse Interrupt Status */ +#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) + +#define USBHS_OTGSC_IDIE_MASK (0x1000000U) +#define USBHS_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - USB ID Interrupt Enable */ +#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) + +#define USBHS_OTGSC_AVVIE_MASK (0x2000000U) +#define USBHS_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - A VBus Valid Interrupt Enable */ +#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) + +#define USBHS_OTGSC_ASVIE_MASK (0x4000000U) +#define USBHS_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - A Session Valid Interrupt Enable */ +#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) + +#define USBHS_OTGSC_BSVIE_MASK (0x8000000U) +#define USBHS_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - B Session Valid Interrupt Enable */ +#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) + +#define USBHS_OTGSC_BSEIE_MASK (0x10000000U) +#define USBHS_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - B Session End Interrupt Enable */ +#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) + +#define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) +#define USBHS_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ +#define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) + +#define USBHS_OTGSC_DPIE_MASK (0x40000000U) +#define USBHS_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - Data Pulse Interrupt Enable */ +#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ + +#define USBHS_USBMODE_CM_MASK (0x3U) +#define USBHS_USBMODE_CM_SHIFT (0U) +/*! CM - Controller Mode + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK) + +#define USBHS_USBMODE_ES_MASK (0x4U) +#define USBHS_USBMODE_ES_SHIFT (2U) +/*! ES - Endian Select + * 0b0..Little Endian + * 0b1..Big Endian + */ +#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) + +#define USBHS_USBMODE_SLOM_MASK (0x8U) +#define USBHS_USBMODE_SLOM_SHIFT (3U) +/*! SLOM - Setup Lockout Mode + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off + */ +#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK) + +#define USBHS_USBMODE_SDIS_MASK (0x10U) +#define USBHS_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - Stream Disable Mode + * 0b0..Inactive + * 0b1..Active + */ +#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ + +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - Setup Endpoint Status */ +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ + +#define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) +#define USBHS_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - Prime Endpoint Receive Buffer */ +#define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) + +#define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USBHS_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - Prime Endpoint Transmit Buffer */ +#define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ + +#define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - Flush Endpoint Receive Buffer */ +#define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) + +#define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - Flush Endpoint Transmit Buffer */ +#define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ + +#define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - Endpoint Receive Buffer Ready */ +#define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) + +#define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - Endpoint Transmit Buffer Ready */ +#define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ + +#define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - Endpoint Receive Complete Event */ +#define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) + +#define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - Endpoint Transmit Complete Event */ +#define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control 0 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) + +#define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) + +#define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) + +#define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) + +#define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) + +#define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) + +#define USBHS_ENDPTCTRL_RXD_MASK (0x2U) +#define USBHS_ENDPTCTRL_RXD_SHIFT (1U) +/*! RXD - RX Endpoint Data Sink + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) + +#define USBHS_ENDPTCTRL_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) + +#define USBHS_ENDPTCTRL_RXI_MASK (0x20U) +#define USBHS_ENDPTCTRL_RXI_SHIFT (5U) +/*! RXI - RX Data Toggle Inhibit + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) + +#define USBHS_ENDPTCTRL_RXR_MASK (0x40U) +#define USBHS_ENDPTCTRL_RXR_SHIFT (6U) +/*! RXR - RX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) + +#define USBHS_ENDPTCTRL_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) + +#define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) + +#define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) +#define USBHS_ENDPTCTRL_TXD_SHIFT (17U) +/*! TXD - TX Endpoint Data Source + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) + +#define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) + +#define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) +#define USBHS_ENDPTCTRL_TXI_SHIFT (21U) +/*! TXI - TX Data Toggle Inhibit + * 0b0..PID sequencing enabled + * 0b1..PID sequencing disabled + */ +#define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) + +#define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) +#define USBHS_ENDPTCTRL_TXR_SHIFT (22U) +/*! TXR - TX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) + +#define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USBHS_ENDPTCTRL */ +#define USBHS_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USBHS_Register_Masks */ + + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USBHS_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USBHS_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USBHS_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USBHS_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USBHS_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USBHS_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USBHS_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USBHS_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USBHS_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USBHS_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USBHS_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USBHS_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USBHS_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USBHS_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USBHS_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USBHS_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USBHS_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USBHS_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USBHS_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USBHS_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USBHS_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USBHS_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USBHS_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USBHS_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USBHS_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USBHS_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USBHS_SBUSCFG_AHBBRST(x) +#define USBHS_USBCMD_FS_MASK USBHS_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USBHS_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USBHS_USBCMD_FS_1(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USBHS_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USBHS_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USBHS_ENDPTLISTADDR_EPBASE(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USBHS_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USBHS_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USBHS_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USBHS_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USBHS_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USBHS_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USBHS_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USBHS_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USBHS_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USBHS_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USBHS_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USBHS_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USBHS_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USBHS_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USBHS_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USBHS_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USBHS_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USBHS_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USBHS_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USBHS_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USBHS_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USBHS_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USBHS_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USBHS_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USBHS_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USBHS_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USBHS_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USBHS_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USBHS_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USBHS_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USBHS_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USBHS_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USBHS_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USBHS_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USBHS_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USBHS_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USBHS_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USBHS_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USBHS_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USBHS_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USBHS_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USBHS_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USBHS_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USBHS_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USBHS_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USBHS_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USBHS_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USBHS_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USBHS_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USBHS_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USBHS_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USBHS_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USBHS_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USBHS_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USBHS_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USBHS_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USBHS_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USBHS_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USBHS_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USBHS_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USBHS_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USBHS_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USBHS_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USBHS_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USBHS_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USBHS_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USBHS_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USBHS_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USBHS_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USBHS_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USBHS_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USBHS_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USBHS_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USBHS_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USBHS_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USBHS_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USBHS_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USBHS_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USBHS_ENDPTCTRL_COUNT +#define USBHS_PORTSC1_WKDS_MASK USBHS_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USBHS_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USBHS_PORTSC1_WKDC(x) +#define USBHS_IRQHandler USB1_HS_IRQHandler + + +/*! + * @} + */ /* end of group USBHS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer + * @{ + */ + +/** USBHSDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock, offset: 0x4 */ + __I uint32_t STATUS; /**< Status, offset: 0x8 */ + __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override, offset: 0xC */ + __IO uint32_t TIMER0; /**< TIMER0, offset: 0x10 */ + __IO uint32_t TIMER1; /**< TIMER1, offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11, offset: 0x18 */ + __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12, offset: 0x18 */ + }; +} USBHSDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks + * @{ + */ + +/*! @name CONTROL - Control */ +/*! @{ */ + +#define USBHSDCD_CONTROL_IACK_MASK (0x1U) +#define USBHSDCD_CONTROL_IACK_SHIFT (0U) +/*! IACK - Interrupt Acknowledge + * 0b0..Do not clear the interrupt. + * 0b1..Clear the IF field (interrupt flag). + */ +#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) + +#define USBHSDCD_CONTROL_IF_MASK (0x100U) +#define USBHSDCD_CONTROL_IF_SHIFT (8U) +/*! IF - Interrupt Flag + * 0b0..No interrupt is pending. + * 0b1..An interrupt is pending. + */ +#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) + +#define USBHSDCD_CONTROL_IE_MASK (0x10000U) +#define USBHSDCD_CONTROL_IE_SHIFT (16U) +/*! IE - Interrupt Enable + * 0b0..Disable interrupts to the system. + * 0b1..Enable interrupts to the system. + */ +#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) + +#define USBHSDCD_CONTROL_BC12_MASK (0x20000U) +#define USBHSDCD_CONTROL_BC12_SHIFT (17U) +/*! BC12 - Battery Charging Revision 1.2 Compatibility + * 0b0..Compatible with BC1.1 + * 0b1..Compatible with BC1.2 (default) + */ +#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) + +#define USBHSDCD_CONTROL_START_MASK (0x1000000U) +#define USBHSDCD_CONTROL_START_SHIFT (24U) +/*! START - Start Change Detection Sequence + * 0b0..Do not start the sequence. Writes of this value have no effect. + * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. + */ +#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) + +#define USBHSDCD_CONTROL_SR_MASK (0x2000000U) +#define USBHSDCD_CONTROL_SR_SHIFT (25U) +/*! SR - Software Reset + * 0b0..Do not perform a software reset. + * 0b1..Perform a software reset. + */ +#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) +/*! @} */ + +/*! @name CLOCK - Clock */ +/*! @{ */ + +#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) +#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed + * 0b0..kHz Speed (between 4 kHz and 1023 kHz) + * 0b1..MHz Speed (between 1 MHz and 1023 MHz) + */ +#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) + +#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) +#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) +/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ +#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) +#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) +/*! SEQ_RES - Charger Detection Sequence Results + * 0b00..No results to report. + * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. + * 0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached + * to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The + * charger type detection has completed.) + * 0b11..Attached to a DCP. + */ +#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) + +#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) +#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) +/*! SEQ_STAT - Charger Detection Sequence Status + * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. + * 0b01..Data pin contact detection is complete. + * 0b10..Charging port detection is complete. + * 0b11..Charger type detection is complete. + */ +#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) + +#define USBHSDCD_STATUS_ERR_MASK (0x100000U) +#define USBHSDCD_STATUS_ERR_SHIFT (20U) +/*! ERR - Error Flag + * 0b0..No sequence errors. + * 0b1..Error in the detection sequence. + */ +#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) + +#define USBHSDCD_STATUS_TO_MASK (0x200000U) +#define USBHSDCD_STATUS_TO_SHIFT (21U) +/*! TO - Timeout Flag + * 0b0..The detection sequence is not running for over 1 s. + * 0b1..It is over 1 s since the data pin contact was detected and debounced. + */ +#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) + +#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) +#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) +/*! ACTIVE - Active Status Indicator + * 0b0..The sequence is not running. + * 0b1..The sequence is running. + */ +#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) +/*! @} */ + +/*! @name SIGNAL_OVERRIDE - Signal Override */ +/*! @{ */ + +#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x7U) +#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) +/*! PS - Phase Selection + * 0b000..No overrides. Field must remain at this value during normal USB data communication to prevent + * unexpected conditions on USB_DP and USB_DM pins. (Default) + * 0b001..Reserved, not for customer use. + * 0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. + * 0b011..Reserved, not for customer use. + * 0b100..Enables VDM_SRC voltage source only. + * 0b101..Reserved, not for customer use. + * 0b110..Reserved, not for customer use. + * 0b111..Reserved, not for customer use. + */ +#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) +/*! @} */ + +/*! @name TIMER0 - TIMER0 */ +/*! @{ */ + +#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) +#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) +/*! TUNITCON - Unit Connection Timer Elapse (in ms) */ +#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) + +#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) +#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) +/*! TSEQ_INIT - Sequence Initiation Time + * 0b0000000000-0b1111111111..0 ms - 1023 ms + */ +#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) +/*! @} */ + +/*! @name TIMER1 - TIMER1 */ +/*! @{ */ + +#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) +/*! TVDPSRC_ON - Time Period Comparator Enabled + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) + +#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) +#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) +/*! TDCD_DBNC - Time Period to Debounce D+ Signal + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) +/*! @} */ + +/*! @name TIMER2_BC11 - TIMER2_BC11 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) +#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) +/*! CHECK_DM - Time Before Check of D- Line + * 0b0001-0b1111..1 ms - 15 ms + */ +#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) + +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) +/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) +/*! @} */ + +/*! @name TIMER2_BC12 - TIMER2_BC12 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) +/*! TVDMSRC_ON - TVDMSRC_ON + * 0b0000000000-0b0000101000..0 ms - 40 ms + */ +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) + +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) +/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSDCD_Register_Masks */ + + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A000u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif +/* Backward compatibility */ +#define USBHSDCD_IRQS { USB1_HS_PHY_IRQn } +#define USB1_HS_PHY_IRQS USBPHY_IRQS + + +/*! + * @} + */ /* end of group USBHSDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name CTRL1 - USB OTG Control 1 */ +/*! @{ */ + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - Disable Overcurrent Detection + * 0b1..Disables + * 0b0..Enables + */ +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - Polarity of Overcurrent + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - Power Polarity + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - Wake-up Interrupt Enable + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - Software Wake-up Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - Software Wake-up + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - Wake-up on ID Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable + * 0b1..DPDM changes wake-up to be enabled, it is for device only + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 + */ +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - Wake-up Interrupt Request + * 0b1..Request received + * 0b0..No request received + */ +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Source Select + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - Low Speed Enable + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI Clock Valid + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_CTRL - USB Host HSIC Control */ +/*! @{ */ + +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) +/*! HSIC_CLK_ON - HSIC Clock ON + * 0b1..Active + * 0b0..Inactive + */ +#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) + +#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) +#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) +/*! HSIC_EN - Host HSIC Enable + * 0b1..Enabled + * 0b0..Disabled + */ +#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) + +#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) +#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) +/*! CLK_VLD - Clock Valid + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif +/* Backward compatibility */ +#define USB_OTGn_CTRL CTRL1 +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) +#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT +#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) +#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT +#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) + + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ + __IO uint32_t TX; /**< TX Control, offset: 0x10 */ + __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ + __IO uint32_t RX; /**< RX Control, offset: 0x20 */ + __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ + __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ + __IO uint32_t STATUS; /**< Status, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ + uint8_t RESERVED_1[32]; + __I uint32_t VERSION; /**< Version, offset: 0x80 */ + uint8_t RESERVED_2[12]; + __IO uint32_t IP; /**< IP Block, offset: 0x90 */ + __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ + __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ + __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ + __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ + uint8_t RESERVED_3[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ + __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ + __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ + __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ + __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ + __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ + __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ + __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ + __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ + uint8_t RESERVED_4[32]; + __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ + __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ + __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ + __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ + __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ + __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ + __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ + __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers + * 0b0..Provide bias to enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - TX Control */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - TX Control */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - TX Control */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - TX Control */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +/*! @} */ + +/*! @name RX - RX Control */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point + * 0b000..0.1000 V + * 0b001..0.1125 V + * 0b010..0.1250 V + * 0b011..0.0875 V + * 0b1xx.. + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point + * 0b000..0.56875 V + * 0b001..0.55000 V + * 0b010..0.58125 V + * 0b011..0.60000 V + * 0b1xx.. + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_SET - RX Control */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_CLR - RX Control */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_TOG - RX Control */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +/*! @} */ + +/*! @name CTRL - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt + * 0b0..Connected + * 0b1..Disconnected + */ +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity + * 0b0..Plugged in + * 0b1..Unplugged + */ +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt + * 0b0..No ID change interrupt + * 0b1..ID change interrupt + */ +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky + * 0b0..During the resume or reset state signaling period + * 0b1..Until you write 0 to it + */ +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt + * 0b0..No resume interrupt + * 0b1..Resume interrupt + */ +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend + * 0b0..Not suspended + * 0b1..Suspended + */ +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate + * 0b0..Run clocks + * 0b1..Gate clocks + */ +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset + * 0b0..Release from reset + * 0b1..Soft-reset + */ +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +/*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status + * 0b0..Not powered + * 0b1..Powered + */ +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS - Host Disconnect Status + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection + * 0b0..No attachment detected + * 0b1..Cable attachment detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +/*! OTGID_STATUS - OTG ID Status + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +/*! RESUME_STATUS - Resume Status */ +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name DEBUG0 - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode + * 0b00..Disconnect + * 0b01..Connect + */ +#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode + * 0b00..Disable + * 0b01..Enable + */ +#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name VERSION - Version */ +/*! @{ */ + +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +/*! STEP - Step */ +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) + +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +/*! MINOR - Minor */ +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) + +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +/*! MAJOR - Major */ +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name IP - IP Block */ +/*! @{ */ + +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_SET - IP Block */ +/*! @{ */ + +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_CLR - IP Block */ +/*! @{ */ + +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_TOG - IP Block */ +/*! @{ */ + +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name PLL_SIC - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control + * 0b0..Power up PLL + * 0b1..Power down PLL + */ +#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control + * 0b0..Power down + * 0b1..Allow powerup + */ +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL + * 0b0..480 MHz output clock + * 0b1..Input reference clock + */ +#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control + * 0b0..PLL_POWER internal state signal + * 0b1..REFBIAS_PWD + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration + * 0b000..Configure for a 32 MHz input clock (divide by 15) + * 0b001..Configure for a 30 MHz input clock (divide by 16) + * 0b010..Configure for a 24 MHz input clock (divide by 20) + * 0b011..Reserved, not usable for USB operation (divide by 22) + * 0b100..Configure for a 20 MHz input clock (divide by 24) + * 0b101..Configure for a 19.2 MHz input clock (divide by 25) + * 0b110..Configure for a 16 MHz input clock (divide by 30) + * 0b111..Configure for a 12 MHz input clock (divide by 40) + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator + * 0b0..Not locked + * 0b1..Locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold + * 0b000..4.0 V + * 0b001..4.1 V + * 0b010..4.2 V + * 0b011..4.3 V + * 0b100..4.4 V + * 0b101..4.5 V + * 0b110..4.6 V + * 0b111..4.7 V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable + * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND + * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection + * 0b0..VBUS_VALID comparator result + * 0b1..VBUS_VALID_3V comparator result + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection + * 0b00..VBUS_VALID comparator result + * 0b01..Session valid comparator result + * 0b10..Session valid comparator result + * 0b11.. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override + * 0b0..Use ID pin detector or external override + * 0b1..Allow local override of ID pin detection status + */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable + * 0b0..Internal detector or local override + * 0b1..External ID signal value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable + * 0b0..Internal detector or local override + * 0b1..External VBUS_VALID value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection + * 0b0..VBUS_VALID comparator + * 0b1..Session valid detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable + * 0bxx0..Disable or power down the VBUS_VALID comparator + * 0bxx1..Enable the VBUS_VALID comparator + * 0bx0x..Disable or power down the session valid detector + * 0bx1x..Enable the session valid detector + * 0b0xx..Disable or power down the VBUS_VALID_3V detector + * 0b1xx..Enable the VBUS_VALID_3V detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator + * 0b0..Above threshold + * 0b1..Below threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection + * 0b0..Fields in USB1_CHRG_DETECT + * 0b1..Fields and state machines in the USBHSDCD module + */ +#define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_SET - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output + * 0b0..SDP detected + * 0b1..Charging port detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage + * 0b0..USB_DM pin voltage is <= 0.8 V + * 0b1..USB_DM pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage + * 0b0..USB_DP pin voltage is <= 0.8 V + * 0b1..USB_DP pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output + * 0b0..CDP detected + * 0b1..DCP detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) +/*! @} */ + +/*! @name ANACTRL - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection + * 0b00..USB1PFDCLK = USB PLL reference clock + * 0b01..USB1PFDCLK = pfd_clk / 4 + * 0b10..USB1PFDCLK frequency = pfd_clk / 2 + * 0b11..USB1PFDCLK = pfd_clk + */ +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value + * 0b0..TRIM_OVERRIDE_EN + * 0b1..PLL_SIC + */ +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_SET - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_CLR - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_TOG - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name PFDA - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal + * 0b0..Not stable + * 0b1..Stable + */ +#define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_SET - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_CLR - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_TOG - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STATUSA; /**< Status A, offset: 0x10 */ + __IO uint32_t STATUSB; /**< Status B, offset: 0x14 */ + __IO uint32_t IRQENA; /**< Interrupt Enable A, offset: 0x18 */ + __IO uint32_t IRQENB; /**< Interrupt Enable B, offset: 0x1C */ + __IO uint32_t WAKENA; /**< Wake-up Enable A, offset: 0x20 */ + __IO uint32_t WAKENB; /**< Wake-up Enable B, offset: 0x24 */ + __IO uint32_t TAMPERA; /**< Tamper Enable A, offset: 0x28 */ + __IO uint32_t TAMPERB; /**< Tamper Enable B, offset: 0x2C */ + __IO uint32_t LOCKA; /**< Lock A, offset: 0x30 */ + __IO uint32_t LOCKB; /**< Lock B, offset: 0x34 */ + __IO uint32_t WAKECFG; /**< Wake-up Configuration, offset: 0x38 */ + uint8_t RESERVED_1[196]; + __IO uint32_t OSCCTLA; /**< Oscillator Control A, offset: 0x100 */ + __IO uint32_t OSCCTLB; /**< Oscillator Control B, offset: 0x104 */ + __IO uint32_t OSCCFGA; /**< Oscillator Configuration A, offset: 0x108 */ + __IO uint32_t OSCCFGB; /**< Oscillator Configuration B, offset: 0x10C */ + uint8_t RESERVED_2[8]; + __IO uint32_t OSCLCKA; /**< Oscillator Lock A, offset: 0x118 */ + __IO uint32_t OSCLCKB; /**< Oscillator Lock B, offset: 0x11C */ + __IO uint32_t OSCCLKE; /**< Oscillator Clock Enable, offset: 0x120 */ + uint8_t RESERVED_3[220]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + __IO uint32_t FROCTLB; /**< FRO16K Control B, offset: 0x204 */ + uint8_t RESERVED_4[16]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + __IO uint32_t FROLCKB; /**< FRO16K Lock B, offset: 0x21C */ + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_5[220]; + __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ + __IO uint32_t LDOCTLB; /**< LDO_RAM Control B, offset: 0x304 */ + uint8_t RESERVED_6[16]; + __IO uint32_t LDOLCKA; /**< LDO_RAM Lock A, offset: 0x318 */ + __IO uint32_t LDOLCKB; /**< LDO_RAM Lock B, offset: 0x31C */ + __IO uint32_t LDORAMC; /**< RAM Control, offset: 0x320 */ + uint8_t RESERVED_7[12]; + __IO uint32_t LDOTIMER0; /**< Bandgap Timer 0, offset: 0x330 */ + uint8_t RESERVED_8[4]; + __IO uint32_t LDOTIMER1; /**< Bandgap Timer 1, offset: 0x338 */ + uint8_t RESERVED_9[196]; + __IO uint32_t MONCTLA; /**< CLKMON Control A, offset: 0x400 */ + __IO uint32_t MONCTLB; /**< CLKMON Control B, offset: 0x404 */ + __IO uint32_t MONCFGA; /**< CLKMON Configuration A, offset: 0x408 */ + __IO uint32_t MONCFGB; /**< CLKMON Configuration B, offset: 0x40C */ + uint8_t RESERVED_10[8]; + __IO uint32_t MONLCKA; /**< CLKMON Lock A, offset: 0x418 */ + __IO uint32_t MONLCKB; /**< CLKMON Lock B, offset: 0x41C */ + uint8_t RESERVED_11[224]; + __IO uint32_t TAMCTLA; /**< TAMPER Control A, offset: 0x500 */ + __IO uint32_t TAMCTLB; /**< TAMPER Control B, offset: 0x504 */ + uint8_t RESERVED_12[16]; + __IO uint32_t TAMLCKA; /**< TAMPER Lock A, offset: 0x518 */ + __IO uint32_t TAMLCKB; /**< TAMPER Lock B, offset: 0x51C */ + uint8_t RESERVED_13[224]; + __IO uint32_t SWICTLA; /**< Switch Control A, offset: 0x600 */ + __IO uint32_t SWICTLB; /**< Switch Control B, offset: 0x604 */ + uint8_t RESERVED_14[16]; + __IO uint32_t SWILCKA; /**< Switch Lock A, offset: 0x618 */ + __IO uint32_t SWILCKB; /**< Switch Lock B, offset: 0x61C */ + uint8_t RESERVED_15[224]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPB; /**< Wakeup 0 Register B, array offset: 0x704, array step: 0x8 */ + } WAKEUP[2]; + uint8_t RESERVED_16[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ + __IO uint32_t WAKLCKB; /**< Wakeup Lock B, offset: 0x7FC */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name STATUSA - Status A */ +/*! @{ */ + +#define VBAT_STATUSA_POR_DET_MASK (0x1U) +#define VBAT_STATUSA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect Flag + * 0b0..Not reset + * 0b1..Reset + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK) + +#define VBAT_STATUSA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_STATUSA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Not asserted + * 0b1..Asserted + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK) + +#define VBAT_STATUSA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_STATUSA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK) + +#define VBAT_STATUSA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_STATUSA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 1 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK) + +#define VBAT_STATUSA_LDO_RDY_MASK (0x10U) +#define VBAT_STATUSA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disabled (not ready) + * 0b1..Enabled (ready) + */ +#define VBAT_STATUSA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK) + +#define VBAT_STATUSA_OSC_RDY_MASK (0x20U) +#define VBAT_STATUSA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disabled (clock not ready) + * 0b1..Enabled (clock ready) + */ +#define VBAT_STATUSA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_OSC_RDY_SHIFT)) & VBAT_STATUSA_OSC_RDY_MASK) + +#define VBAT_STATUSA_CLOCK_DET_MASK (0x40U) +#define VBAT_STATUSA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Clock error not detected + * 0b1..Clock error detected + */ +#define VBAT_STATUSA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CLOCK_DET_SHIFT)) & VBAT_STATUSA_CLOCK_DET_MASK) + +#define VBAT_STATUSA_CONFIG_DET_MASK (0x80U) +#define VBAT_STATUSA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CONFIG_DET_SHIFT)) & VBAT_STATUSA_CONFIG_DET_MASK) + +#define VBAT_STATUSA_VOLT_DET_MASK (0x100U) +#define VBAT_STATUSA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_VOLT_DET_SHIFT)) & VBAT_STATUSA_VOLT_DET_MASK) + +#define VBAT_STATUSA_TEMP_DET_MASK (0x200U) +#define VBAT_STATUSA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Temperature error not detected + * 0b1..Temperature error detected + */ +#define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) + +#define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) +#define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Light error not detected + * 0b1..Light error detected + */ +#define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) + +#define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) +#define VBAT_STATUSA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Security input 0 not detected + * 0b1..Security input 0 detected + */ +#define VBAT_STATUSA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_SEC0_DET_SHIFT)) & VBAT_STATUSA_SEC0_DET_MASK) + +#define VBAT_STATUSA_IRQ0_DET_MASK (0x10000U) +#define VBAT_STATUSA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ0_DET_SHIFT)) & VBAT_STATUSA_IRQ0_DET_MASK) + +#define VBAT_STATUSA_IRQ1_DET_MASK (0x20000U) +#define VBAT_STATUSA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ1_DET_SHIFT)) & VBAT_STATUSA_IRQ1_DET_MASK) + +#define VBAT_STATUSA_IRQ2_DET_MASK (0x40000U) +#define VBAT_STATUSA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ2_DET_SHIFT)) & VBAT_STATUSA_IRQ2_DET_MASK) + +#define VBAT_STATUSA_IRQ3_DET_MASK (0x80000U) +#define VBAT_STATUSA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ3_DET_SHIFT)) & VBAT_STATUSA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name STATUSB - Status B */ +/*! @{ */ + +#define VBAT_STATUSB_INVERSE_MASK (0xFFFFFU) +#define VBAT_STATUSB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_STATUSB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSB_INVERSE_SHIFT)) & VBAT_STATUSB_INVERSE_MASK) +/*! @} */ + +/*! @name IRQENA - Interrupt Enable A */ +/*! @{ */ + +#define VBAT_IRQENA_POR_DET_MASK (0x1U) +#define VBAT_IRQENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK) + +#define VBAT_IRQENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_IRQENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK) + +#define VBAT_IRQENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_IRQENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK) + +#define VBAT_IRQENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_IRQENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK) + +#define VBAT_IRQENA_LDO_RDY_MASK (0x10U) +#define VBAT_IRQENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK) + +#define VBAT_IRQENA_OSC_RDY_MASK (0x20U) +#define VBAT_IRQENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_OSC_RDY_SHIFT)) & VBAT_IRQENA_OSC_RDY_MASK) + +#define VBAT_IRQENA_CLOCK_DET_MASK (0x40U) +#define VBAT_IRQENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CLOCK_DET_SHIFT)) & VBAT_IRQENA_CLOCK_DET_MASK) + +#define VBAT_IRQENA_CONFIG_DET_MASK (0x80U) +#define VBAT_IRQENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CONFIG_DET_SHIFT)) & VBAT_IRQENA_CONFIG_DET_MASK) + +#define VBAT_IRQENA_VOLT_DET_MASK (0x100U) +#define VBAT_IRQENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_VOLT_DET_SHIFT)) & VBAT_IRQENA_VOLT_DET_MASK) + +#define VBAT_IRQENA_TEMP_DET_MASK (0x200U) +#define VBAT_IRQENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) + +#define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) +#define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) + +#define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) +#define VBAT_IRQENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_SEC0_DET_SHIFT)) & VBAT_IRQENA_SEC0_DET_MASK) + +#define VBAT_IRQENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_IRQENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ0_DET_SHIFT)) & VBAT_IRQENA_IRQ0_DET_MASK) + +#define VBAT_IRQENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_IRQENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ1_DET_SHIFT)) & VBAT_IRQENA_IRQ1_DET_MASK) + +#define VBAT_IRQENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_IRQENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ2_DET_SHIFT)) & VBAT_IRQENA_IRQ2_DET_MASK) + +#define VBAT_IRQENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_IRQENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ3_DET_SHIFT)) & VBAT_IRQENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name IRQENB - Interrupt Enable B */ +/*! @{ */ + +#define VBAT_IRQENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_IRQENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_IRQENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENB_INVERSE_SHIFT)) & VBAT_IRQENB_INVERSE_MASK) +/*! @} */ + +/*! @name WAKENA - Wake-up Enable A */ +/*! @{ */ + +#define VBAT_WAKENA_POR_DET_MASK (0x1U) +#define VBAT_WAKENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK) + +#define VBAT_WAKENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_WAKENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wake-up Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK) + +#define VBAT_WAKENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_WAKENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK) + +#define VBAT_WAKENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_WAKENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK) + +#define VBAT_WAKENA_LDO_RDY_MASK (0x10U) +#define VBAT_WAKENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK) + +#define VBAT_WAKENA_OSC_RDY_MASK (0x20U) +#define VBAT_WAKENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32K Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_OSC_RDY_SHIFT)) & VBAT_WAKENA_OSC_RDY_MASK) + +#define VBAT_WAKENA_CLOCK_DET_MASK (0x40U) +#define VBAT_WAKENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CLOCK_DET_SHIFT)) & VBAT_WAKENA_CLOCK_DET_MASK) + +#define VBAT_WAKENA_CONFIG_DET_MASK (0x80U) +#define VBAT_WAKENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CONFIG_DET_SHIFT)) & VBAT_WAKENA_CONFIG_DET_MASK) + +#define VBAT_WAKENA_VOLT_DET_MASK (0x100U) +#define VBAT_WAKENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_VOLT_DET_SHIFT)) & VBAT_WAKENA_VOLT_DET_MASK) + +#define VBAT_WAKENA_TEMP_DET_MASK (0x200U) +#define VBAT_WAKENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) + +#define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) +#define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) + +#define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) +#define VBAT_WAKENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disabled + * 0b1..Enabled + */ +#define VBAT_WAKENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_SEC0_DET_SHIFT)) & VBAT_WAKENA_SEC0_DET_MASK) + +#define VBAT_WAKENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_WAKENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ0_DET_SHIFT)) & VBAT_WAKENA_IRQ0_DET_MASK) + +#define VBAT_WAKENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_WAKENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ1_DET_SHIFT)) & VBAT_WAKENA_IRQ1_DET_MASK) + +#define VBAT_WAKENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_WAKENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ2_DET_SHIFT)) & VBAT_WAKENA_IRQ2_DET_MASK) + +#define VBAT_WAKENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_WAKENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ3_DET_SHIFT)) & VBAT_WAKENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name WAKENB - Wake-up Enable B */ +/*! @{ */ + +#define VBAT_WAKENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_WAKENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_WAKENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENB_INVERSE_SHIFT)) & VBAT_WAKENB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMPERA - Tamper Enable A */ +/*! @{ */ + +#define VBAT_TAMPERA_POR_DET_MASK (0x1U) +#define VBAT_TAMPERA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_POR_DET_SHIFT)) & VBAT_TAMPERA_POR_DET_MASK) + +#define VBAT_TAMPERA_CLOCK_DET_MASK (0x40U) +#define VBAT_TAMPERA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CLOCK_DET_SHIFT)) & VBAT_TAMPERA_CLOCK_DET_MASK) + +#define VBAT_TAMPERA_CONFIG_DET_MASK (0x80U) +#define VBAT_TAMPERA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CONFIG_DET_SHIFT)) & VBAT_TAMPERA_CONFIG_DET_MASK) + +#define VBAT_TAMPERA_VOLT_DET_MASK (0x100U) +#define VBAT_TAMPERA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_VOLT_DET_SHIFT)) & VBAT_TAMPERA_VOLT_DET_MASK) + +#define VBAT_TAMPERA_TEMP_DET_MASK (0x200U) +#define VBAT_TAMPERA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) + +#define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) +#define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) + +#define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) +#define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_SEC0_DET_SHIFT)) & VBAT_TAMPERA_SEC0_DET_MASK) +/*! @} */ + +/*! @name TAMPERB - Tamper Enable B */ +/*! @{ */ + +#define VBAT_TAMPERB_INVERSE_MASK (0xFFFFU) +#define VBAT_TAMPERB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMPERB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERB_INVERSE_SHIFT)) & VBAT_TAMPERB_INVERSE_MASK) +/*! @} */ + +/*! @name LOCKA - Lock A */ +/*! @{ */ + +#define VBAT_LOCKA_LOCK_MASK (0x1U) +#define VBAT_LOCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Disables lock + * 0b1..Enables lock. Cleared by VBAT POR. + */ +#define VBAT_LOCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK) +/*! @} */ + +/*! @name LOCKB - Lock B */ +/*! @{ */ + +#define VBAT_LOCKB_LOCK_MASK (0x1U) +#define VBAT_LOCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Disables lock + * 0b0..Enables lock + */ +#define VBAT_LOCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKB_LOCK_SHIFT)) & VBAT_LOCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKECFG - Wake-up Configuration */ +/*! @{ */ + +#define VBAT_WAKECFG_OUT_MASK (0x1U) +#define VBAT_WAKECFG_OUT_SHIFT (0U) +/*! OUT - Output + * 0b0..Logic zero (asserted) + * 0b1..Logic one + */ +#define VBAT_WAKECFG_OUT(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKECFG_OUT_SHIFT)) & VBAT_WAKECFG_OUT_MASK) +/*! @} */ + +/*! @name OSCCTLA - Oscillator Control A */ +/*! @{ */ + +#define VBAT_OSCCTLA_OSC_EN_MASK (0x1U) +#define VBAT_OSCCTLA_OSC_EN_SHIFT (0U) +/*! OSC_EN - Crystal Oscillator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_EN_SHIFT)) & VBAT_OSCCTLA_OSC_EN_MASK) + +#define VBAT_OSCCTLA_OSC_BYP_EN_MASK (0x2U) +#define VBAT_OSCCTLA_OSC_BYP_EN_SHIFT (1U) +/*! OSC_BYP_EN - Crystal Oscillator Bypass Enable + * 0b0..Does not bypass + * 0b1..Bypass + */ +#define VBAT_OSCCTLA_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_BYP_EN_SHIFT)) & VBAT_OSCCTLA_OSC_BYP_EN_MASK) + +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) +/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external + * crystal ESR values See the device datasheet for the ranges supported by this device + * 0b00..ESR Range 0 + * 0b01..ESR Range 1 + * 0b10..ESR Range 2 + * 0b11..ESR Range 3 + */ +#define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) + +#define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) +#define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) +/*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_CAP_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_CAP_SEL_EN_SHIFT)) & VBAT_OSCCTLA_CAP_SEL_EN_MASK) + +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK (0xF00U) +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT (8U) +/*! EXTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_EXTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) +#define VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT (12U) +/*! XTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_XTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) +#define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) +/*! MODE_EN - Mode Enable + * 0b00..Normal mode + * 0b01..Startup mode + * 0b11..Low power mode + */ +#define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) + +#define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) +#define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) +/*! SUPPLY_DET - Supply Detector Trim + * 0b00..VBAT supply is less than 3V + * 0b01..VBAT supply is greater than 3V + */ +#define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) +/*! @} */ + +/*! @name OSCCTLB - Oscillator Control B */ +/*! @{ */ + +#define VBAT_OSCCTLB_INVERSE_MASK (0xFFFFFU) +#define VBAT_OSCCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLB_INVERSE_SHIFT)) & VBAT_OSCCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCCFGA - Oscillator Configuration A */ +/*! @{ */ + +#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) +#define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) +/*! CMP_TRIM - Comparator Trim + * 0b00..760 mV + * 0b01..770 mV + * 0b11..740 mV + */ +#define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) +#define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) +/*! CAP2_TRIM - CAP2_TRIM */ +#define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) + +#define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) +#define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) +/*! DLY_TRIM - Delay Trim + * 0b0000..P current 9(nA) and N Current 6(nA) + * 0b0001..P current 13(nA) and N Current 6(nA) + * 0b0011..P current 4(nA) and N Current 6(nA) + * 0b0100..P current 9(nA) and N Current 4(nA) + * 0b0101..P current 13(nA) and N Current 4(nA) + * 0b0111..P current 4(nA) and N Current 4(nA) + * 0b1000..P current 9(nA) and N Current 2(nA) + * 0b1001..P current 13(nA) and N Current 2(nA) + * 0b1011..P current 4(nA) and N Current 2(nA) + */ +#define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) +#define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) +/*! CAP_TRIM - Capacitor Trim + * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) + * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) + * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) + * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) + */ +#define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) + +#define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) +#define VBAT_OSCCFGA_INIT_TRIM_SHIFT (9U) +/*! INIT_TRIM - Initialization Trim + * 0b000..8 s + * 0b001..4 s + * 0b010..2 s + * 0b011..1 s + * 0b100..0.5 s + * 0b101..0.25 s + * 0b110..0.125 s + * 0b111..0.5 ms + */ +#define VBAT_OSCCFGA_INIT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_INIT_TRIM_SHIFT)) & VBAT_OSCCFGA_INIT_TRIM_MASK) +/*! @} */ + +/*! @name OSCCFGB - Oscillator Configuration B */ +/*! @{ */ + +#define VBAT_OSCCFGB_INVERSE_MASK (0xFFFU) +#define VBAT_OSCCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGB_INVERSE_SHIFT)) & VBAT_OSCCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCLCKA - Oscillator Lock A */ +/*! @{ */ + +#define VBAT_OSCLCKA_LOCK_MASK (0x1U) +#define VBAT_OSCLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_OSCLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKA_LOCK_SHIFT)) & VBAT_OSCLCKA_LOCK_MASK) +/*! @} */ + +/*! @name OSCLCKB - Oscillator Lock B */ +/*! @{ */ + +#define VBAT_OSCLCKB_LOCK_MASK (0x1U) +#define VBAT_OSCLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_OSCLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKB_LOCK_SHIFT)) & VBAT_OSCLCKB_LOCK_MASK) +/*! @} */ + +/*! @name OSCCLKE - Oscillator Clock Enable */ +/*! @{ */ + +#define VBAT_OSCCLKE_CLKE_MASK (0xFU) +#define VBAT_OSCCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_OSCCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCLKE_CLKE_SHIFT)) & VBAT_OSCCLKE_CLKE_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROCTLB - FRO16K Control B */ +/*! @{ */ + +#define VBAT_FROCTLB_INVERSE_MASK (0x1U) +#define VBAT_FROCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_FROCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLB_INVERSE_SHIFT)) & VBAT_FROCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROLCKB - FRO16K Lock B */ +/*! @{ */ + +#define VBAT_FROLCKB_LOCK_MASK (0x1U) +#define VBAT_FROLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_FROLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKB_LOCK_SHIFT)) & VBAT_FROLCKB_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0xFU) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name LDOCTLA - LDO_RAM Control A */ +/*! @{ */ + +#define VBAT_LDOCTLA_BG_EN_MASK (0x1U) +#define VBAT_LDOCTLA_BG_EN_SHIFT (0U) +/*! BG_EN - Bandgap Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK) + +#define VBAT_LDOCTLA_LDO_EN_MASK (0x2U) +#define VBAT_LDOCTLA_LDO_EN_SHIFT (1U) +/*! LDO_EN - LDO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_LDO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK) + +#define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) +#define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) +/*! REFRESH_EN - Refresh Enable + * 0b0..Refresh mode is disabled + * 0b1..Refresh mode is enabled for low power operation + */ +#define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) +/*! @} */ + +/*! @name LDOCTLB - LDO_RAM Control B */ +/*! @{ */ + +#define VBAT_LDOCTLB_INVERSE_MASK (0x7U) +#define VBAT_LDOCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_LDOCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLB_INVERSE_SHIFT)) & VBAT_LDOCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name LDOLCKA - LDO_RAM Lock A */ +/*! @{ */ + +#define VBAT_LDOLCKA_LOCK_MASK (0x1U) +#define VBAT_LDOLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_LDOLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK) +/*! @} */ + +/*! @name LDOLCKB - LDO_RAM Lock B */ +/*! @{ */ + +#define VBAT_LDOLCKB_LOCK_MASK (0x1U) +#define VBAT_LDOLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_LDOLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKB_LOCK_SHIFT)) & VBAT_LDOLCKB_LOCK_MASK) +/*! @} */ + +/*! @name LDORAMC - RAM Control */ +/*! @{ */ + +#define VBAT_LDORAMC_ISO_MASK (0x1U) +#define VBAT_LDORAMC_ISO_SHIFT (0U) +/*! ISO - Isolate SRAM + * 0b0..State follows the chip power modes + * 0b1..Isolates SRAM and places it in Low-Power Retention mode + */ +#define VBAT_LDORAMC_ISO(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK) + +#define VBAT_LDORAMC_SWI_MASK (0x2U) +#define VBAT_LDORAMC_SWI_SHIFT (1U) +/*! SWI - Switch SRAM + * 0b0..Supply follows the chip power modes + * 0b1..LDO_RAM powers the array + */ +#define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) + +#define VBAT_LDORAMC_RET0_MASK (0x100U) +#define VBAT_LDORAMC_RET0_SHIFT (8U) +/*! RET0 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) + +#define VBAT_LDORAMC_RET1_MASK (0x200U) +#define VBAT_LDORAMC_RET1_SHIFT (9U) +/*! RET1 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) + +#define VBAT_LDORAMC_RET2_MASK (0x400U) +#define VBAT_LDORAMC_RET2_SHIFT (10U) +/*! RET2 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) + +#define VBAT_LDORAMC_RET3_MASK (0x800U) +#define VBAT_LDORAMC_RET3_SHIFT (11U) +/*! RET3 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) +/*! @} */ + +/*! @name LDOTIMER0 - Bandgap Timer 0 */ +/*! @{ */ + +#define VBAT_LDOTIMER0_TIMCFG_MASK (0x7U) +#define VBAT_LDOTIMER0_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration + * 0b111..7.8125 ms + * 0b110..15.625 ms + * 0b101..31.25 ms + * 0b100..62.5 ms + * 0b011..125 ms + * 0b010..250 ms + * 0b001..500 ms + * 0b000..1 s + */ +#define VBAT_LDOTIMER0_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK) + +#define VBAT_LDOTIMER0_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER0_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER0_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK) +/*! @} */ + +/*! @name LDOTIMER1 - Bandgap Timer 1 */ +/*! @{ */ + +#define VBAT_LDOTIMER1_TIMCFG_MASK (0xFFFFFFU) +#define VBAT_LDOTIMER1_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration */ +#define VBAT_LDOTIMER1_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK) + +#define VBAT_LDOTIMER1_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER1_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER1_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK) +/*! @} */ + +/*! @name MONCTLA - CLKMON Control A */ +/*! @{ */ + +#define VBAT_MONCTLA_MON_EN_MASK (0x1U) +#define VBAT_MONCTLA_MON_EN_SHIFT (0U) +/*! MON_EN - CLKMON Enable + * 0b0..CLKMON is disabled + * 0b1..CLKMON is enabled + */ +#define VBAT_MONCTLA_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLA_MON_EN_SHIFT)) & VBAT_MONCTLA_MON_EN_MASK) +/*! @} */ + +/*! @name MONCTLB - CLKMON Control B */ +/*! @{ */ + +#define VBAT_MONCTLB_INVERSE_MASK (0x1U) +#define VBAT_MONCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLB_INVERSE_SHIFT)) & VBAT_MONCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name MONCFGA - CLKMON Configuration A */ +/*! @{ */ + +#define VBAT_MONCFGA_FREQ_TRIM_MASK (0x3U) +#define VBAT_MONCFGA_FREQ_TRIM_SHIFT (0U) +/*! FREQ_TRIM - Frequency Trim + * 0b00..Clock monitor asserts 2 cycle after expected edge + * 0b01..Clock monitor asserts 4 cycles after expected edge + * 0b10..Clock monitor asserts 6 cycles after expected edge + * 0b11..Clock monitor asserts 8 cycles after expected edge + */ +#define VBAT_MONCFGA_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_FREQ_TRIM_SHIFT)) & VBAT_MONCFGA_FREQ_TRIM_MASK) + +#define VBAT_MONCFGA_DIVIDE_TRIM_MASK (0x4U) +#define VBAT_MONCFGA_DIVIDE_TRIM_SHIFT (2U) +/*! DIVIDE_TRIM - Divide Trim + * 0b0..Clock monitor operates at 1 kHz + * 0b1..Clock monitor operates at 64 Hz + */ +#define VBAT_MONCFGA_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_DIVIDE_TRIM_SHIFT)) & VBAT_MONCFGA_DIVIDE_TRIM_MASK) + +#define VBAT_MONCFGA_RSVD_TRIM_MASK (0xF8U) +#define VBAT_MONCFGA_RSVD_TRIM_SHIFT (3U) +/*! RSVD_TRIM - Reserved Trim */ +#define VBAT_MONCFGA_RSVD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_RSVD_TRIM_SHIFT)) & VBAT_MONCFGA_RSVD_TRIM_MASK) +/*! @} */ + +/*! @name MONCFGB - CLKMON Configuration B */ +/*! @{ */ + +#define VBAT_MONCFGB_INVERSE_MASK (0xFFU) +#define VBAT_MONCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGB_INVERSE_SHIFT)) & VBAT_MONCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name MONLCKA - CLKMON Lock A */ +/*! @{ */ + +#define VBAT_MONLCKA_LOCK_MASK (0x1U) +#define VBAT_MONLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_MONLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKA_LOCK_SHIFT)) & VBAT_MONLCKA_LOCK_MASK) +/*! @} */ + +/*! @name MONLCKB - CLKMON Lock B */ +/*! @{ */ + +#define VBAT_MONLCKB_LOCK_MASK (0x1U) +#define VBAT_MONLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_MONLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKB_LOCK_SHIFT)) & VBAT_MONLCKB_LOCK_MASK) +/*! @} */ + +/*! @name TAMCTLA - TAMPER Control A */ +/*! @{ */ + +#define VBAT_TAMCTLA_VOLT_EN_MASK (0x1U) +#define VBAT_TAMCTLA_VOLT_EN_SHIFT (0U) +/*! VOLT_EN - Voltage Detect Enable + * 0b0..Voltage detect is disabled + * 0b1..Voltage detect is enabled + */ +#define VBAT_TAMCTLA_VOLT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_VOLT_EN_SHIFT)) & VBAT_TAMCTLA_VOLT_EN_MASK) + +#define VBAT_TAMCTLA_TEMP_EN_MASK (0x2U) +#define VBAT_TAMCTLA_TEMP_EN_SHIFT (1U) +/*! TEMP_EN - Temperature Detect Enable + * 0b0..Temperature detect is disabled + * 0b1..Temperature detect is enabled + */ +#define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) + +#define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) +#define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) +/*! LIGHT_EN - Light Detect Enable + * 0b0..Light detect is disabled + * 0b1..Light detect is enabled + */ +#define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) +/*! @} */ + +/*! @name TAMCTLB - TAMPER Control B */ +/*! @{ */ + +#define VBAT_TAMCTLB_INVERSE_MASK (0xFU) +#define VBAT_TAMCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLB_INVERSE_SHIFT)) & VBAT_TAMCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMLCKA - TAMPER Lock A */ +/*! @{ */ + +#define VBAT_TAMLCKA_LOCK_MASK (0x1U) +#define VBAT_TAMLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_TAMLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKA_LOCK_SHIFT)) & VBAT_TAMLCKA_LOCK_MASK) +/*! @} */ + +/*! @name TAMLCKB - TAMPER Lock B */ +/*! @{ */ + +#define VBAT_TAMLCKB_LOCK_MASK (0x1U) +#define VBAT_TAMLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_TAMLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKB_LOCK_SHIFT)) & VBAT_TAMLCKB_LOCK_MASK) +/*! @} */ + +/*! @name SWICTLA - Switch Control A */ +/*! @{ */ + +#define VBAT_SWICTLA_SWI_EN_MASK (0x1U) +#define VBAT_SWICTLA_SWI_EN_SHIFT (0U) +/*! SWI_EN - Switch Enable + * 0b0..VDD_BAT + * 0b1..VDD_SYS + */ +#define VBAT_SWICTLA_SWI_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_SWI_EN_SHIFT)) & VBAT_SWICTLA_SWI_EN_MASK) + +#define VBAT_SWICTLA_LP_EN_MASK (0x2U) +#define VBAT_SWICTLA_LP_EN_SHIFT (1U) +/*! LP_EN - Low Power Enable + * 0b0..VDD_BAT always supplies VBAT modules in low-power modes + * 0b1..VDD_SYS always supplies VBAT modules if SWI_EN is also 1 + */ +#define VBAT_SWICTLA_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_LP_EN_SHIFT)) & VBAT_SWICTLA_LP_EN_MASK) +/*! @} */ + +/*! @name SWICTLB - Switch Control B */ +/*! @{ */ + +#define VBAT_SWICTLB_INVERSE_MASK (0x3U) +#define VBAT_SWICTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_SWICTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLB_INVERSE_SHIFT)) & VBAT_SWICTLB_INVERSE_MASK) +/*! @} */ + +/*! @name SWILCKA - Switch Lock A */ +/*! @{ */ + +#define VBAT_SWILCKA_LOCK_MASK (0x1U) +#define VBAT_SWILCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_SWILCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKA_LOCK_SHIFT)) & VBAT_SWILCKA_LOCK_MASK) +/*! @} */ + +/*! @name SWILCKB - Switch Lock B */ +/*! @{ */ + +#define VBAT_SWILCKB_LOCK_MASK (0x1U) +#define VBAT_SWILCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_SWILCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKB_LOCK_SHIFT)) & VBAT_SWILCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKEUP_WAKEUPB - Wakeup 0 Register B */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPB_INVERSE_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_WAKEUP_WAKEUPB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT)) & VBAT_WAKEUP_WAKEUPB_INVERSE_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPB */ +#define VBAT_WAKEUP_WAKEUPB_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + +/*! @name WAKLCKB - Wakeup Lock B */ +/*! @{ */ + +#define VBAT_WAKLCKB_LOCK_MASK (0x1U) +#define VBAT_WAKLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_WAKLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKB_LOCK_SHIFT)) & VBAT_WAKLCKB_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VREF_VERID_FEATURE_MASK (0xFFFFU) +#define VREF_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) + +#define VREF_VERID_MINOR_MASK (0xFF0000U) +#define VREF_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) + +#define VREF_VERID_MAJOR_MASK (0xFF000000U) +#define VREF_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CSR - Control and Status */ +/*! @{ */ + +#define VREF_CSR_HCBGEN_MASK (0x1U) +#define VREF_CSR_HCBGEN_SHIFT (0U) +/*! HCBGEN - HC Bandgap Enabled + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) + +#define VREF_CSR_LPBGEN_MASK (0x2U) +#define VREF_CSR_LPBGEN_SHIFT (1U) +/*! LPBGEN - Low-Power Bandgap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) + +#define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) +#define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) +/*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) + +#define VREF_CSR_CHOPEN_MASK (0x8U) +#define VREF_CSR_CHOPEN_SHIFT (3U) +/*! CHOPEN - Chop Oscillator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) + +#define VREF_CSR_ICOMPEN_MASK (0x10U) +#define VREF_CSR_ICOMPEN_SHIFT (4U) +/*! ICOMPEN - Current Compensation Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) + +#define VREF_CSR_REGEN_MASK (0x20U) +#define VREF_CSR_REGEN_SHIFT (5U) +/*! REGEN - Regulator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) + +#define VREF_CSR_HI_PWR_LV_MASK (0x800U) +#define VREF_CSR_HI_PWR_LV_SHIFT (11U) +/*! HI_PWR_LV - High-Power Level + * 0b0..Low-power + * 0b1..High-power + */ +#define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) + +#define VREF_CSR_BUF21EN_MASK (0x10000U) +#define VREF_CSR_BUF21EN_SHIFT (16U) +/*! BUF21EN - Internal Buffer21 Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) + +#define VREF_CSR_VREFST_MASK (0x80000000U) +#define VREF_CSR_VREFST_SHIFT (31U) +/*! VREFST - Internal HC Voltage Reference Stable + * 0b0..Disabled and unstable + * 0b1..Stable + */ +#define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) +/*! @} */ + +/*! @name UTRIM - User Trim */ +/*! @{ */ + +#define VREF_UTRIM_TRIM2V1_MASK (0xFU) +#define VREF_UTRIM_TRIM2V1_SHIFT (0U) +/*! TRIM2V1 - VREF 2.1 V Trim */ +#define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) + +#define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) +#define VREF_UTRIM_VREFTRIM_SHIFT (8U) +/*! VREFTRIM - VREF Trim */ +#define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + * *.. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_WUPE0_MASK (0x3U) +#define WUU_PE1_WUPE0_SHIFT (0U) +/*! WUPE0 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK) + +#define WUU_PE1_WUPE1_MASK (0xCU) +#define WUU_PE1_WUPE1_SHIFT (2U) +/*! WUPE1 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_WUPE3_MASK (0xC0U) +#define WUU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) + +#define WUU_PE1_WUPE4_MASK (0x300U) +#define WUU_PE1_WUPE4_SHIFT (8U) +/*! WUPE4 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) + +#define WUU_PE1_WUPE5_MASK (0xC00U) +#define WUU_PE1_WUPE5_SHIFT (10U) +/*! WUPE5 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_WUPE13_MASK (0xC000000U) +#define WUU_PE1_WUPE13_SHIFT (26U) +/*! WUPE13 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) + +#define WUU_PE1_WUPE14_MASK (0x30000000U) +#define WUU_PE1_WUPE14_SHIFT (28U) +/*! WUPE14 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK) + +#define WUU_PE1_WUPE15_MASK (0xC0000000U) +#define WUU_PE1_WUPE15_SHIFT (30U) +/*! WUPE15 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_WUPE21_MASK (0xC00U) +#define WUU_PE2_WUPE21_SHIFT (10U) +/*! WUPE21 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_Reserved28_MASK (0x3000000U) +#define WUU_PE2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK) + +#define WUU_PE2_Reserved29_MASK (0xC000000U) +#define WUU_PE2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK) + +#define WUU_PE2_Reserved30_MASK (0x30000000U) +#define WUU_PE2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved30_SHIFT)) & WUU_PE2_Reserved30_MASK) + +#define WUU_PE2_Reserved31_MASK (0xC0000000U) +#define WUU_PE2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved31_SHIFT)) & WUU_PE2_Reserved31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME1_MASK (0x2U) +#define WUU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME3_MASK (0x8U) +#define WUU_ME_WUME3_SHIFT (3U) +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) + +#define WUU_ME_WUME4_MASK (0x10U) +#define WUU_ME_WUME4_SHIFT (4U) +/*! WUME4 - Module Interrupt Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) + +#define WUU_ME_WUME5_MASK (0x20U) +#define WUU_ME_WUME5_SHIFT (5U) +/*! WUME5 - Module Interrupt Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME7_MASK (0x80U) +#define WUU_ME_WUME7_SHIFT (7U) +/*! WUME7 - Module Interrupt Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) + +#define WUU_ME_WUME9_MASK (0x200U) +#define WUU_ME_WUME9_SHIFT (9U) +/*! WUME9 - Module Interrupt Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE0_MASK (0x1U) +#define WUU_DE_WUDE0_SHIFT (0U) +/*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) + +#define WUU_DE_WUDE1_MASK (0x2U) +#define WUU_DE_WUDE1_SHIFT (1U) +/*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) + +#define WUU_DE_WUDE2_MASK (0x4U) +#define WUU_DE_WUDE2_SHIFT (2U) +/*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) + +#define WUU_DE_WUDE3_MASK (0x8U) +#define WUU_DE_WUDE3_SHIFT (3U) +/*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE5_MASK (0x20U) +#define WUU_DE_WUDE5_SHIFT (5U) +/*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE7_MASK (0x80U) +#define WUU_DE_WUDE7_SHIFT (7U) +/*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) + +#define WUU_DE_WUDE9_MASK (0x200U) +#define WUU_DE_WUDE9_SHIFT (9U) +/*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_WUF0_MASK (0x1U) +#define WUU_PF_WUF0_SHIFT (0U) +/*! WUF0 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK) + +#define WUU_PF_WUF1_MASK (0x2U) +#define WUU_PF_WUF1_SHIFT (1U) +/*! WUF1 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_WUF3_MASK (0x8U) +#define WUU_PF_WUF3_SHIFT (3U) +/*! WUF3 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) + +#define WUU_PF_WUF4_MASK (0x10U) +#define WUU_PF_WUF4_SHIFT (4U) +/*! WUF4 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) + +#define WUU_PF_WUF5_MASK (0x20U) +#define WUU_PF_WUF5_SHIFT (5U) +/*! WUF5 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_WUF13_MASK (0x2000U) +#define WUU_PF_WUF13_SHIFT (13U) +/*! WUF13 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) + +#define WUU_PF_WUF14_MASK (0x4000U) +#define WUU_PF_WUF14_SHIFT (14U) +/*! WUF14 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK) + +#define WUU_PF_WUF15_MASK (0x8000U) +#define WUU_PF_WUF15_SHIFT (15U) +/*! WUF15 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_WUF21_MASK (0x200000U) +#define WUU_PF_WUF21_SHIFT (21U) +/*! WUF21 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_Reserved28_MASK (0x10000000U) +#define WUU_PF_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK) + +#define WUU_PF_Reserved29_MASK (0x20000000U) +#define WUU_PF_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK) + +#define WUU_PF_Reserved30_MASK (0x40000000U) +#define WUU_PF_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved30_SHIFT)) & WUU_PF_Reserved30_MASK) + +#define WUU_PF_Reserved31_MASK (0x80000000U) +#define WUU_PF_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved31_SHIFT)) & WUU_PF_Reserved31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_WUPDC0_MASK (0x3U) +#define WUU_PDC1_WUPDC0_SHIFT (0U) +/*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK) + +#define WUU_PDC1_WUPDC1_MASK (0xCU) +#define WUU_PDC1_WUPDC1_SHIFT (2U) +/*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_WUPDC3_MASK (0xC0U) +#define WUU_PDC1_WUPDC3_SHIFT (6U) +/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) + +#define WUU_PDC1_WUPDC4_MASK (0x300U) +#define WUU_PDC1_WUPDC4_SHIFT (8U) +/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) + +#define WUU_PDC1_WUPDC5_MASK (0xC00U) +#define WUU_PDC1_WUPDC5_SHIFT (10U) +/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_WUPDC13_MASK (0xC000000U) +#define WUU_PDC1_WUPDC13_SHIFT (26U) +/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) + +#define WUU_PDC1_WUPDC14_MASK (0x30000000U) +#define WUU_PDC1_WUPDC14_SHIFT (28U) +/*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK) + +#define WUU_PDC1_WUPDC15_MASK (0xC0000000U) +#define WUU_PDC1_WUPDC15_SHIFT (30U) +/*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_WUPDC21_MASK (0xC00U) +#define WUU_PDC2_WUPDC21_SHIFT (10U) +/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_Reserved28_MASK (0x3000000U) +#define WUU_PDC2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK) + +#define WUU_PDC2_Reserved29_MASK (0xC000000U) +#define WUU_PDC2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK) + +#define WUU_PDC2_Reserved30_MASK (0x30000000U) +#define WUU_PDC2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved30_SHIFT)) & WUU_PDC2_Reserved30_MASK) + +#define WUU_PDC2_Reserved31_MASK (0xC0000000U) +#define WUU_PDC2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_WUPMC0_MASK (0x1U) +#define WUU_PMC_WUPMC0_SHIFT (0U) +/*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK) + +#define WUU_PMC_WUPMC1_MASK (0x2U) +#define WUU_PMC_WUPMC1_SHIFT (1U) +/*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_WUPMC3_MASK (0x8U) +#define WUU_PMC_WUPMC3_SHIFT (3U) +/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) + +#define WUU_PMC_WUPMC4_MASK (0x10U) +#define WUU_PMC_WUPMC4_SHIFT (4U) +/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) + +#define WUU_PMC_WUPMC5_MASK (0x20U) +#define WUU_PMC_WUPMC5_SHIFT (5U) +/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_WUPMC13_MASK (0x2000U) +#define WUU_PMC_WUPMC13_SHIFT (13U) +/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) + +#define WUU_PMC_WUPMC14_MASK (0x4000U) +#define WUU_PMC_WUPMC14_SHIFT (14U) +/*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK) + +#define WUU_PMC_WUPMC15_MASK (0x8000U) +#define WUU_PMC_WUPMC15_SHIFT (15U) +/*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_WUPMC21_MASK (0x200000U) +#define WUU_PMC_WUPMC21_SHIFT (21U) +/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_Reserved28_MASK (0x10000000U) +#define WUU_PMC_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK) + +#define WUU_PMC_Reserved29_MASK (0x20000000U) +#define WUU_PMC_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK) + +#define WUU_PMC_Reserved30_MASK (0x40000000U) +#define WUU_PMC_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved30_SHIFT)) & WUU_PMC_Reserved30_MASK) + +#define WUU_PMC_Reserved31_MASK (0x80000000U) +#define WUU_PMC_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved31_SHIFT)) & WUU_PMC_Reserved31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) + +#define WWDT_MOD_DEBUG_EN_MASK (0x40U) +#define WWDT_MOD_DEBUG_EN_SHIFT (6U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN235_H_ */ + diff --git a/devices/MCXN235/MCXN235_features.h b/devices/MCXN235/MCXN235_features.h new file mode 100644 index 000000000..02210302f --- /dev/null +++ b/devices/MCXN235/MCXN235_features.h @@ -0,0 +1,900 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b240407 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN235_FEATURES_H_ +#define _MCXN235_FEATURES_H_ + +/* SOC module features */ + +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) + +/* CDOG module features */ + +/* @brief CDOG Has No Reset */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ + (((x) == DMA0) ? (16) : \ + (((x) == DMA1) ? (8) : (-1))) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _MCXN235_FEATURES_H_ */ + diff --git a/devices/MCXN235/drivers/fsl_clock.c b/devices/MCXN235/drivers/fsl_clock.c new file mode 100644 index 000000000..c9c30292d --- /dev/null +++ b/devices/MCXN235/drivers/fsl_clock.c @@ -0,0 +1,2695 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_NDIV_VAL_P (0U) /* NDIV is in bits 7:0 */ +#define PLL_NDIV_VAL_M (0xFFUL << PLL_NDIV_VAL_P) +#define PLL_MDIV_VAL_P (0U) /* MDIV is in bits 15:0 */ +#define PLL_MDIV_VAL_M (0xFFFFULL << PLL_MDIV_VAL_P) +#define PLL_PDIV_VAL_P (0U) /* PDIV is in bits 4:0 */ +#define PLL_PDIV_VAL_M (0x1FUL << PLL_PDIV_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (32000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDIV reg */ +#define PLL_NDIV_VAL_SET(value) (((unsigned long)(value) << PLL_NDIV_VAL_P) & PLL_NDIV_VAL_M) +/* PLL MDIV reg */ +#define PLL_MDIV_VAL_SET(value) (((unsigned long long)(value) << PLL_MDIV_VAL_P) & PLL_MDIV_VAL_M) +/* PLL PDIV reg */ +#define PLL_PDIV_VAL_SET(value) (((unsigned long)(value) << PLL_PDIV_VAL_P) & PLL_PDIV_VAL_M) + +/* PLL SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +#define PLL_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_FRACT_P) & PLL_SSCG_MD_FRACT_M) +#define PLL_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_INT_P) & PLL_SSCG_MD_INT_M) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; +/*! @brief External XTAL32K clock frequency. */ +volatile static uint32_t s_Xtal32_Freq = 32768U; +/*! @brief SAI MCLK clock frequency. */ +volatile static uint32_t s_Sai_Mclk_Freq[2] = {0U}; +/*! @brief SAI TX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Tx_Bclk_Freq[2] = {0U}; +/*! @brief SAI RX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Rx_Bclk_Freq[2] = {0U}; + +/*! @brief external UPLL clock frequency. */ +static uint32_t s_extUpllFreq = 0U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get CLK 48M Clk */ +static uint32_t CLOCK_GetClk48MFreq(void); +/* Get CLK 144M Clk */ +static uint32_t CLOCK_GetClk144MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get OSC 32K Clk */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id); +/* Get Systick Clk */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id); +/* Get CLOCK OUT Clk */ +static uint32_t CLOCK_GetClockOutClkFreq(void); +/* Get LP_OSC Clk */ +static uint32_t CLOCK_GetLposcFreq(void); + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void); +/* Get postdivider (P) from PLL1 PDIV setting */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL0 MDIV and SSCG settings */ +static float findPll0MMult(void); +/* Get multiplier (M) from PLL1 MDIV and SSCG settings */ +static float findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Set PLL0 output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup); +/* Get predivider (N) from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup); +/* Get postdivider (P) from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup); +/* Get multiplier (M) from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_48MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + if ((iFreq != 48000000U) && (iFreq != 144000000U)) + { + return kStatus_Fail; + } + + /* Select 48MHz or 144MHz for FIRC clock */ + SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable FIRC 48 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC 144 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /*Configure SOSC range */ + SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the OSC 32K. + * @param id : OSC 32 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id) +{ + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK | SCG_LDOCSR_VOUT_OK_MASK; + + VBAT0->OSCCTLA = + (VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) | + VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK; + VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E); + /* Wait for STATUSA[OSC_RDY] to set. */ + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + VBAT0->OSCLCKA = VBAT_OSCLCKA_LOCK_MASK; + VBAT0->OSCLCKB &= ~VBAT_OSCLCKA_LOCK_MASK; + + VBAT0->OSCCLKE |= VBAT_OSCCLKE_CLKE(id); + + /* De-initializes the SCG ROSC */ + SCG0->ROSCCSR = SCG_ROSCCSR_ROSCERR_MASK; + + /* Unlock ROSCCSR */ + SCG0->ROSCCSR &= ~SCG_ROSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable ROSC */ + SCG0->ROSCCSR |= SCG_ROSCCSR_ROSCCM_MASK; + + /* Wait for ROSC clock to be valid. */ + while ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) == 0U) + { + } + + s_Xtal32_Freq = 32768U; + + return kStatus_Success; +} + +/** + * @brief Initialize the CLK16K clock. + * @param id : CLK 16 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id) +{ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; + + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + VBAT0->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; + + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(id); + + return kStatus_Success; +} + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config) +{ + SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_FircTrimNonUpdate == config.trimMode) + { + SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); + } + + /* Set trim mode. */ + SCG0->FIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->ROSCCSR; + + reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->ROSCCSR = reg; +} + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode) +{ + uint32_t reg = SCG0->UPLLCSR; + + reg &= ~(SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->UPLLCSR = reg; +} + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode) +{ + uint32_t reg = SCG0->APLLCSR; + + reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->APLLCSR = reg; +} + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SPLLCSR; + + reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SPLLCSR = reg; +} + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ( mode ) + { + case kMD_Mode: + { + if (system_freq_hz > 50000000) + { + return kStatus_Fail; + } + if (system_freq_hz >24000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kSD_Mode: + { + if (system_freq_hz > 100000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kOD_Mode: + { + if (system_freq_hz > 150000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 100000000) + { + num_wait_states_added = 3U; + } + else if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + } + } + + /* additional wait-states are added */ + FMU0 -> FCTRL = (FMU0 -> FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL); + + return kStatus_Success; +} + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config) +{ + uint32_t tmp32; + + if (config->enableCrystalOscillatorBypass == true) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_BYP_EN_MASK; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } + else + { + tmp32 = base->OSCCTLA; + + if (config != NULL) + { + if (config->enableInternalCapBank) + { + tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); + tmp32 |= VBAT_OSCCTLA_EXTAL_CAP_SEL(config->extalCap) | VBAT_OSCCTLA_XTAL_CAP_SEL(config->xtalCap); + tmp32 |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + else + { + /* Disable the internal capacitance bank. */ + tmp32 &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + + tmp32 &= ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK); + tmp32 |= VBAT_OSCCTLA_COARSE_AMP_GAIN(config->coarseAdjustment); + } + base->OSCCTLA = tmp32; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } +} + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint16_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint16_t)GET_ID_ITEM_MUX(item); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_SCGRCCRSCSCLKSEL) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(sel)) + { + } + } + else + { + ((volatile uint32_t *)pClkSel)[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint16_t mux; + uint32_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint16_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_SCGRCCRSCSCLKSEL) + { + actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actualSel = (uint32_t)((volatile uint32_t *)pClkSel)[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + /* halt and reset clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 0x3UL << 29U; + + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } +} + +/* Get IP clock dividers */ +/** + * brief Get peripheral clock dividers. + * param div_name : Clock divider name + * return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name) +{ + uint32_t div; + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + if ((uint32_t)(((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & (0x3UL << 29U)) != 0UL) + { + div = 0U; + } + else + { + div = (uint32_t)((((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & 0xFFU) + 1U); + } + + return div; +} + +/* Halt IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param Halt : Clock divider name + * return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + /* halt clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + + return; +} + +/* enable system clocks */ +/** + * brief system clocks enable controls. + * param mask : system clocks enable value + * return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask) +{ + SYSCON->CLOCK_CTRL |= mask; + + return; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_SystickClk0: + freq = CLOCK_GetSystickClkFreq(0U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Clk1M: + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Clk48M: + freq = CLOCK_GetClk48MFreq(); + break; + case kCLOCK_Clk144M: + freq = CLOCK_GetClk144MFreq(); + break; + case kCLOCK_Clk16K0: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + case kCLOCK_Clk16K1: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVsys); + break; + case kCLOCK_Clk16K2: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case kCLOCK_Clk16K3: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToMain); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Osc32K0: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case kCLOCK_Osc32K1: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVsys); + break; + case kCLOCK_Osc32K2: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case kCLOCK_Osc32K3: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_UsbPllOut: + // freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_LpOsc: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetClk1MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + case 9U: + freq = CLOCK_GetSaiTxBclkFreq(0U); + break; + case 10U: + freq = CLOCK_GetSaiRxBclkFreq(0U); + break; + case 11U: + freq = CLOCK_GetSaiTxBclkFreq(1U); + break; + case 12U: + freq = CLOCK_GetSaiRxBclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->CTIMERCLKDIV[id] & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->ADC0CLKSEL) : (SYSCON->ADC1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->ADC0CLKDIV & SYSCON_ADC0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->ADC1CLKDIV & SYSCON_ADC1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get LPFLEXCOMM Clk */ +/*! brief Return Frequency of LPFLEXCOMM Clock + * return Frequency of LPFLEXCOMM Clock. + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSEL[id]) + { + case 1U: + freq = CLOCK_GetPllClkDivFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + // freq = CLOCK_GetUPllOutFreq(); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXCOMMCLKDIV[id] & 0xffU) + 1U); +} + + +/* Get SYSTEM PLL0 Clk */ +/*! brief Return Frequency of PLL0 + * return Frequency of PLL0 + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + /* If PLL0 is work */ + if (CLOCK_IsPLL0Locked() == true) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get SYSTEM PLL1 Clk */ +/*! brief Return Frequency of PLL1 + * return Frequency of PLL1 + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + /* If PLL1 is work */ + if (CLOCK_IsPLL1Locked() == true) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll1MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get PLLClkDiv Clk */ +/*! brief Return Frequency of PLLClkDiv + * return Frequency of PLLClkDiv + */ +uint32_t CLOCK_GetPllClkDivFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->PLLCLKDIVSEL) + { + case 0U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 1U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); +} + +/*! + * brief Gets the external UPLL frequency. + * + * This function gets the external UPLL frequency in Hz. + * + * return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void) +{ + return s_extUpllFreq; +} + +/*! + * brief Sets the external UPLL frequency. + * + * This function sets the external UPLL frequency in Hz. + * Call this function after the external PLL frequency is changed. + * Otherwise, the APIs, which are used to get the frequency, may return an incorrect value. + * + * param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq) +{ + s_extUpllFreq = freq; +} + +/* Get I3C function Clk */ +/*! brief Return Frequency of I3C function clock + * return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->I3C0FCLKSEL) : (SYSCON->I3C1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->I3C1FCLKDIV & SYSCON_I3C1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get MICFIL Clk */ +/*! brief Return Frequency of MICFIL + * return Frequency of MICFIL + */ +uint32_t CLOCK_GetMicfilClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MICFILFCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->MICFILFCLKDIV & SYSCON_MICFILFCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXIO Clk */ +/*! brief Return Frequency of FLEXIO + * return Frequency of FLEXIO + */ +uint32_t CLOCK_GetFlexioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->FLEXIOCLKSEL) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXIOCLKDIV & SYSCON_FLEXIOCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXCAN Clk */ +/*! brief Return Frequency of FLEXCAN + * return Frequency of FLEXCAN + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->FLEXCAN0CLKSEL) : (SYSCON->FLEXCAN1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->FLEXCAN0CLKDIV & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->FLEXCAN1CLKDIV & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get EWM0 Clk */ +/*! brief Return Frequency of EWM0 + * return Frequency of EWM0 + */ +uint32_t CLOCK_GetEwm0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->EWM0CLKSEL) + { + case 1U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Watchdog Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + if (id == 0U) + { + freq = CLOCK_GetClk1MFreq(); + } + else + { + switch (SYSCON->WDT1CLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + case 3U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + } + + div = ((id == 0U) ? ((SYSCON->WDT0CLKDIV & SYSCON_WDT0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get OSTIMER Clk */ +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->OSTIMERCLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CMP Function Clk */ +/*! brief Return Frequency of CMP Function + * return Frequency of CMP Function + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0FCLKSEL) : (SYSCON->CMP1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0FCLKDIV & SYSCON_CMP0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1FCLKDIV & SYSCON_CMP1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get CMP Round Robin Clk */ +/*! brief Return Frequency of CMP Round Robin + * return Frequency of CMP Round Robin + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0RRCLKSEL) : (SYSCON->CMP1RRCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0RRCLKDIV & SYSCON_CMP0RRCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1RRCLKDIV & SYSCON_CMP1RRCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get UTICK Clk */ +/*! brief Return Frequency of UTICK + * return Frequency of UTICK + */ +uint32_t CLOCK_GetUtickClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t div = ((SYSCON->UTICKCLKDIV & SYSCON_UTICKCLKDIV_DIV_MASK) + 1U); + + switch (SYSCON->UTICKCLKSEL) + { + case 0U: + freq = CLOCK_GetExtClkFreq(); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + return freq / div; +} + +/* Get SAI Clk */ +/*! brief Return Frequency of SAI + * return Frequency of SAI + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->SAI0CLKSEL) : (SYSCON->SAI1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->SAI0CLKDIV & SYSCON_SAI0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->SAI1CLKDIV & SYSCON_SAI1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get SAI MCLK */ +/*! brief Initialize the SAI MCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Mclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI TX BCLK */ +/*! brief Initialize the SAI TX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Tx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI RX BCLK */ +/*! brief Initialize the SAI RX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Rx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI MCLK */ +/*! brief Return Frequency of SAI MCLK + * return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id) +{ + return s_Sai_Mclk_Freq[id]; +} + +/* Get SAI TX BCLK */ +/*! brief Return Frequency of SAI TX BCLK + * return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id) +{ + return s_Sai_Tx_Bclk_Freq[id]; +} + +/* Get SAI RX BCLK */ +/*! brief Return Frequency of SAI RX BCLK + * return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id) +{ + return s_Sai_Rx_Bclk_Freq[id]; +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLLInClockRateFromSetup(pSetup); + + prediv = findPllPreDivFromSetup(pSetup); + postdiv = findPllPostDivFromSetup(pSetup); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPllMMultFromSetup(pSetup); + workRate /= (float)postdiv; + + return (uint32_t)workRate; +} + +/* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Get PLL Input Clock Rate */ + switch (pControl->inputSource) + { + case (uint32_t)kPll_ClkSrcSysOsc: + inRate = CLOCK_GetExtClkFreq(); + break; + case (uint32_t)kPll_ClkSrcFirc: + inRate = CLOCK_GetClk48MFreq(); + break; + case (uint32_t)kPll_ClkSrcRosc: + inRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + inRate = 0U; + break; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useSS); + pSetup->pllctrl |= (uint32_t)pControl->inputSource; + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SCG_APLLSSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL0 and disable PLL0 clock during setup changes */ + SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->APLLCTRL = pSetup->pllctrl; + SCG0->APLLNDIV = pSetup->pllndiv; + SCG0->APLLNDIV = pSetup->pllndiv | (1UL << SCG_APLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->APLLPDIV = pSetup->pllpdiv; + SCG0->APLLPDIV = pSetup->pllpdiv | (1UL << SCG_APLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->APLLMDIV = pSetup->pllmdiv; + SCG0->APLLMDIV = pSetup->pllmdiv | (1UL << SCG_APLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->APLLSSCG0 = pSetup->pllsscg[0]; + SCG0->APLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock APLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500us/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->APLLLOCK_CNFG = SCG_APLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL0 and enable PLL0 clock */ + SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL0Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll0OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL1 and disable PLL1 clock during setup changes */ + SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->SPLLCTRL = pSetup->pllctrl; + SCG0->SPLLNDIV = pSetup->pllndiv; + SCG0->SPLLNDIV = pSetup->pllndiv | (1UL << SCG_SPLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->SPLLPDIV = pSetup->pllpdiv; + SCG0->SPLLPDIV = pSetup->pllpdiv | (1UL << SCG_SPLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->SPLLMDIV = pSetup->pllmdiv; + SCG0->SPLLMDIV = pSetup->pllmdiv | (1UL << SCG_SPLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->SPLLSSCG0 = pSetup->pllsscg[0]; + SCG0->SPLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock SPLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->SPLLLOCK_CNFG = SCG_SPLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL1 and enable PLL1 clock */ + SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL1Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll1OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + // PMC->OSEVENTTIMER |= PMC_OSEVENTTIMER_CLOCKENABLE_MASK; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint32_t freq; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0UL) + { + freq = 0; + } + else if ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) != 0UL) + { + freq = 144000000U; + } + else + { + freq = 48000000U; + } + + return freq; +} + +/* Get CLK 48M Clk */ +/*! brief Return Frequency of CLK 48MHz + * return Frequency of CLK 48MHz + */ +static uint32_t CLOCK_GetClk48MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) ? 48000000U : 0U; +} + +/* Get CLK 144M Clk */ +/*! brief Return Frequency of CLK 144MHz + * return Frequency of CLK 144MHz + */ +static uint32_t CLOCK_GetClk144MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) != 0U) ? 144000000U : 0U; +} + +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? + (((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE(id)) != 0UL) ? 16000U : 0U) : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id) +{ + return ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) != 0UL) ? + (((VBAT0->OSCCLKE & VBAT_OSCCLKE_CLKE(id)) != 0UL) ? s_Xtal32_Freq : 0U) : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 5U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 6U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSEL0) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +static uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get LP_OSC Clk */ +/*! brief Return Frequency of LP_OSC + * return Frequency of LP_OSC + */ +static uint32_t CLOCK_GetLposcFreq(void) +{ + uint32_t freq = 0U; + + switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT) + { + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case 2U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_LIMUPOFF_MASK) == 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum and fractional mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->APLLNDIV & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->SPLLNDIV & SCG_SPLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get postdivider (P) from PLL1 PDIV setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->APLLMDIV & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->APLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->APLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static float findPll1MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->SPLLMDIV & SCG_SPLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->SPLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->SPLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndiv = s_PllSetupCacheStruct[i].pllndiv; + pSetup->pllmdiv = s_PllSetupCacheStruct[i].pllmdiv; + pSetup->pllpdiv = s_PllSetupCacheStruct[i].pllpdiv; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndiv = pSetup->pllndiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllmdiv = pSetup->pllmdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdiv = pSetup->pllpdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndiv", "pllpdiv", "pllmdiv" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllmdiv = (uint32_t)PLL_MDIV_VAL_SET(pllMultiplier); + pSetup->pllsscg[1] &= ~SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) | PLL_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndiv = PLL_NDIV_VAL_SET(pllPreDivider); + pSetup->pllpdiv = PLL_PDIV_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SCG_APLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SCG_APLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SCG_APLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (uplimoff << SCG_APLLCTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SCG_APLLCTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0U; + + switch ((pSetup->pllctrl & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get predivider (N) from from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = pSetup->pllndiv & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t postDiv = 1UL; + + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(pSetup->pllmdiv & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((pSetup->pllsscg[0]) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((pSetup->pllsscg[0]) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool err = false; + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); + if ((480000000UL % freq) != 0UL) + { + return false; + } + multiplier = (uint16_t)(480000000UL / freq); + + switch (multiplier) + { + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 22: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U); + break; + } + case 24: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + err = true; + break; + } + } + + if (err) + { + return false; + } + + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; + + USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD = 0x0U; + + while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void) +{ + USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void) +{ + USBHS1__USBC->USBCMD |= USBHS_USBCMD_RST_MASK; + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (uint32_t i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + return true; +} + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void) +{ + /* System OSC Clock Monitor is disabled */ + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); + + firc_trim_config_t fircAutoTrimConfig = { + .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ + .trimSrc = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */ + .trimDiv = 1U, /* Divided value */ + .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ + .trimFine = 0U, /* Trim value, see Reference Manual for more information */ + }; + CLOCK_FROHFTrimConfig(fircAutoTrimConfig); + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return (status_t)kStatus_Success; +} diff --git a/devices/MCXN235/drivers/fsl_clock.h b/devices/MCXN235/drivers/fsl_clock.h new file mode 100644 index 000000000..649eceb3e --- /dev/null +++ b/devices/MCXN235/drivers/fsl_clock.h @@ -0,0 +1,1726 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4, kCLOCK_Sram5, kCLOCK_Sram6, kCLOCK_Sram7 \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt0, kCLOCK_Wwdt1 \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for LP_FLEXCOMM. */ +#define LP_FLEXCOMM_CLOCKS \ + { \ + kCLOCK_LPFlexComm0, kCLOCK_LPFlexComm1, kCLOCK_LPFlexComm2, kCLOCK_LPFlexComm3, kCLOCK_LPFlexComm4, \ + kCLOCK_LPFlexComm5, kCLOCK_LPFlexComm6, kCLOCK_LPFlexComm7 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_LPUart0, kCLOCK_LPUart1, kCLOCK_LPUart2, kCLOCK_LPUart3, kCLOCK_LPUart4, kCLOCK_LPUart5, \ + kCLOCK_LPUart6, kCLOCK_LPUart7 \ + } +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_LPI2c0, kCLOCK_LPI2c1, kCLOCK_LPI2c2, kCLOCK_LPI2c3, kCLOCK_LPI2c4, kCLOCK_LPI2c5, kCLOCK_LPI2c6, \ + kCLOCK_LPI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LPSpi0, kCLOCK_LPSpi1, kCLOCK_LPSpi2, kCLOCK_LPSpi3, kCLOCK_LPSpi4, kCLOCK_LPSpi5, kCLOCK_LPSpi6, \ + kCLOCK_LPSpi7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \ + { \ + kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \ + } \ + } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ + { \ + kCLOCK_Qdc0, kCLOCK_Qdc1 \ + } +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_Flexio \ + } +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_Flexcan0, kCLOCK_Flexcan1 \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_I3c0, kCLOCK_I3c1 \ + } +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_uSdhc \ + } +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0, kCLOCK_Sai1 \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Micfil \ + } +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS \ + { \ + kCLOCK_Erm \ + } +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS \ + { \ + kCLOCK_Eim \ + } +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } +/*! @brief Clock ip name array for LPCMP. */ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_None, kCLOCK_None, kCLOCK_Cmp2 \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define AHB_CLK_CTRL3 3 +#define REG_PWM0SUBCTL 250 +#define REG_PWM1SUBCTL 251 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_None = 0U, /*!< None clock gate. */ + + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */ + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */ + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */ + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */ + kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */ + kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */ + kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */ + kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */ + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */ + kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */ + kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */ + kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */ + kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */ + kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */ + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */ + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */ + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */ + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */ + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */ + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */ + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */ + kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */ + kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */ + kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */ + kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */ + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */ + kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */ + kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */ + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */ + kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPFlexComm0. */ + kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPFlexComm1. */ + kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPFlexComm2. */ + kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPFlexComm3. */ + kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPFlexComm4. */ + kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPFlexComm5. */ + kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPFlexComm6. */ + kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPFlexComm7. */ + kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */ + kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */ + kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */ + kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */ + kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */ + kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */ + kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */ + kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */ + kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */ + kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */ + kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */ + kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */ + kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */ + kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */ + kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */ + kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */ + kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */ + kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */ + kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */ + kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */ + kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */ + kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */ + kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */ + kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */ + kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */ + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */ + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */ + kCLOCK_Smartdma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */ + + kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */ + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */ + kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */ + kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */ + kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */ + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */ + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */ + kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */ + kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */ + kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */ + kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */ + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */ + kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */ + kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */ + kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */ + + kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */ + kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */ + kCLOCK_Qdc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Qdc0. */ + kCLOCK_Qdc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Qdc1. */ + kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */ + kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */ + kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */ + kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */ + kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */ + kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */ + kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */ + kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */ + + kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */ + kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */ + kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */ + kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */ + + kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */ + kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */ + kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */ + kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */ + +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_SystickClk0, /*!< Systick clock0 */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_FroHf, /*!< FRO48/144 */ + kCLOCK_Clk48M, /*!< CLK48M */ + kCLOCK_Clk144M, /*!< CLK144M */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_Clk16K2, /*!< CLK16K[2] */ + kCLOCK_Clk16K3, /*!< CLK16K[3] */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Osc32K0, /*!< OSC32K[0] */ + kCLOCK_Osc32K1, /*!< OSC32K[1] */ + kCLOCK_Osc32K2, /*!< OSC32K[2] */ + kCLOCK_Osc32K3, /*!< OSC32K[3] */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_UsbPllOut, /*!< USB PLL Output */ + kCLOCK_LpOsc, /*!< lp_osc */ +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U) +#define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_TRACECLKSEL ((0x268 - 0x260) / 4) +#define CM_CTIMERCLKSEL0 ((0x26C - 0x260) / 4) +#define CM_CTIMERCLKSEL1 ((0x270 - 0x260) / 4) +#define CM_CTIMERCLKSEL2 ((0x274 - 0x260) / 4) +#define CM_CTIMERCLKSEL3 ((0x278 - 0x260) / 4) +#define CM_CTIMERCLKSEL4 ((0x27C - 0x260) / 4) +#define CM_CLKOUTCLKSEL ((0x288 - 0x260) / 4) +#define CM_ADC0CLKSEL ((0x2A4 - 0x260) / 4) +#define CM_FCCLKSEL0 ((0x2B0 - 0x260) / 4) +#define CM_FCCLKSEL1 ((0x2B4 - 0x260) / 4) +#define CM_FCCLKSEL2 ((0x2B8 - 0x260) / 4) +#define CM_FCCLKSEL3 ((0x2BC - 0x260) / 4) +#define CM_FCCLKSEL4 ((0x2C0 - 0x260) / 4) +#define CM_FCCLKSEL5 ((0x2C4 - 0x260) / 4) +#define CM_FCCLKSEL6 ((0x2C8 - 0x260) / 4) +#define CM_FCCLKSEL7 ((0x2CC - 0x260) / 4) +#define CM_ADC1CLKSEL ((0x464 - 0x260) / 4) +#define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4) +#define CM_I3C0FCLKSEL ((0x530 - 0x260) / 4) +#define CM_MICFILFCLKSEL ((0x548 - 0x260) / 4) +#define CM_FLEXIOCLKSEL ((0x560 - 0x260) / 4) +#define CM_FLEXCAN0CLKSEL ((0x5A0 - 0x260) / 4) +#define CM_FLEXCAN1CLKSEL ((0x5A8 - 0x260) / 4) +#define CM_EWM0CLKSEL ((0x5D4 - 0x260) / 4) +#define CM_WDT1CLKSEL ((0x5D8 - 0x260) / 4) +#define CM_OSTIMERCLKSEL ((0x5E0 - 0x260) / 4) +#define CM_CMP0FCLKSEL ((0x5F0 - 0x260) / 4) +#define CM_CMP0RRCLKSEL ((0x5F8 - 0x260) / 4) +#define CM_CMP1FCLKSEL ((0x600 - 0x260) / 4) +#define CM_CMP1RRCLKSEL ((0x608 - 0x260) / 4) +#define CM_UTICKCLKSEL ((0x878 - 0x260) / 4) +#define CM_SAI0CLKSEL ((0x880 - 0x260) / 4) +#define CM_SAI1CLKSEL ((0x884 - 0x260) / 4) +#define CM_I3C1FCLKSEL ((0xB30 - 0x260) / 4) + +#define CM_SCGRCCRSCSCLKSEL 0x3FEU + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */ + kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */ + kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */ + kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */ + kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */ + kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */ + kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */ + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */ + kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */ + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */ + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */ + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */ + kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */ + kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */ + kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */ + kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */ + kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */ + kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */ + kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */ + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */ + + kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */ + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */ + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */ + kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */ + kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */ + kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */ + kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */ + kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */ + kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */ + kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */ + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */ + + kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */ + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */ + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */ + kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */ + kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */ + kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */ + kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */ + kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */ + kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */ + kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */ + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */ + + kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */ + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */ + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */ + kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */ + kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */ + kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */ + kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */ + kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */ + kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */ + kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */ + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */ + + kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */ + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */ + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */ + kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */ + kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */ + kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */ + kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */ + kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */ + kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */ + kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */ + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */ + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */ + kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */ + kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */ + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */ + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */ + + kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ + kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ + kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */ + kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */ + kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */ + kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */ + kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ + + kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */ + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */ + kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */ + kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */ + kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */ + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */ + kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */ + kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */ + kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */ + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */ + kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */ + kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */ + kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */ + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */ + kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */ + kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */ + kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */ + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */ + kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */ + kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */ + kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */ + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */ + kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */ + kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */ + kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */ + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */ + kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */ + kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */ + kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */ + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */ + kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */ + kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */ + kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ + kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ + kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */ + kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */ + kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */ + kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */ + kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ + + kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ + kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */ + kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */ + + kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */ + kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */ + kCLK_1M_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLK. */ + kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */ + kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */ + kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */ + + kPLL0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKSTC. */ + kFRO_HF_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKSTC. */ + kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKSTC. */ + kPLL1_CLK0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKSTC. */ + kUSB_PLL_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKSTC. */ + kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */ + + kPLL0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKS. */ + kFRO_HF_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKS. */ + kCLK_1M_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKS. */ + kPLL1_CLK0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKS. */ + kUSB_PLL_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKS. */ + kNONE_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKS. */ + + kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */ + kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */ + kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */ + kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */ + kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */ + kSAI0_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */ + kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */ + kSAI1_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */ + kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */ + + kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */ + kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */ + kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */ + kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */ + kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */ + kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */ + kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */ + + kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */ + kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */ + kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */ + kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */ + kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */ + + kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */ + kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */ + kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */ + kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */ + kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */ + kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */ + + kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */ + kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */ + + kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */ + kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */ + kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */ + kCLK_1M_2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach clk_1m to WDT1. */ + + kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */ + kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */ + kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */ + kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */ + + kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */ + kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */ + kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */ + kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */ + kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */ + kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */ + kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */ + + kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */ + kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */ + kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */ + kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */ + kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */ + kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */ + kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */ + + kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */ + kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */ + kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */ + kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */ + kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */ + kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */ + kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */ + + kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */ + kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */ + kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */ + kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */ + kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */ + kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */ + kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */ + + kCLK_IN_to_UTICK = MUX_A(CM_UTICKCLKSEL, 0), /*!< Attach Clk_in to UTICK. */ + kXTAL32K2_to_UTICK = MUX_A(CM_UTICKCLKSEL, 1), /*!< Attach xtal32k[2] to UTICK. */ + kCLK_1M_to_UTICK = MUX_A(CM_UTICKCLKSEL, 2), /*!< Attach clk_1m to UTICK. */ + kNONE_to_UTICK = MUX_A(CM_UTICKCLKSEL, 3), /*!< Attach NONE to UTICK. */ + + kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */ + kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */ + kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */ + kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */ + kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */ + kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */ + + kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */ + kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */ + kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */ + kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */ + kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */ + kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */ + + kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */ + kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */ + kCLK_1M_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLK. */ + kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */ + kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */ + kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */ + + kPLL0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKSTC. */ + kFRO_HF_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKSTC. */ + kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKSTC. */ + kPLL1_CLK0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKSTC. */ + kUSB_PLL_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKSTC. */ + kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */ + + kPLL0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKS. */ + kFRO_HF_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKS. */ + kCLK_1M_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKS. */ + kPLL1_CLK0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKS. */ + kUSB_PLL_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKS. */ + kNONE_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKS. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + kCLOCK_DivTraceClk = ((0x308 - 0x300) / 4), /*!< Trace Clk Divider. */ + kCLOCK_DivSlowClk = ((0x378 - 0x300) / 4), /*!< SLOW CLK Divider. */ + kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clk Divider. */ + kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< ClkOut Clk Divider. */ + kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Clk Divider. */ + kCLOCK_DivWdt0Clk = ((0x38C - 0x300) / 4), /*!< Wdt0 Clk Divider. */ + kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clk Divider. */ + kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll Clk Divider. */ + kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clk Divider. */ + kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clk Divider. */ + kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clk Divider. */ + kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clk Divider. */ + kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clk Divider. */ + kCLOCK_DivPLL1Clk0 = ((0x3E4 - 0x300) / 4), /*!< PLL1 Clk0 Divider. */ + kCLOCK_DivPLL1Clk1 = ((0x3E8 - 0x300) / 4), /*!< Pll1 Clk1 Divider. */ + kCLOCK_DivUtickClk = ((0x3F0 - 0x300) / 4), /*!< Utick Clk Divider. */ + kCLOCK_DivFrg = ((0x3F4 - 0x300) / 4), /*!< CLKOUT FRG Clk Divider. */ + kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clk Divider. */ + kCLOCK_DivI3c0FClk = ((0x540 - 0x300) / 4), /*!< I3C0 FClk Divider. */ + kCLOCK_DivMicfilFClk = ((0x54C - 0x300) / 4), /*!< MICFILFCLK Divider. */ + kCLOCK_DivFlexioClk = ((0x564 - 0x300) / 4), /*!< Flexio Clk Divider. */ + kCLOCK_DivFlexcan0Clk = ((0x5A4 - 0x300) / 4), /*!< Flexcan0 Clk Divider. */ + kCLOCK_DivFlexcan1Clk = ((0x5AC - 0x300) / 4), /*!< Flexcan1 Clk Divider. */ + kCLOCK_DivWdt1Clk = ((0x5DC - 0x300) / 4), /*!< Wdt1 Clk Divider. */ + kCLOCK_DivCmp0FClk = ((0x5F4 - 0x300) / 4), /*!< Cmp0 FClk Divider. */ + kCLOCK_DivCmp0rrClk = ((0x5FC - 0x300) / 4), /*!< Cmp0rr Clk Divider. */ + kCLOCK_DivCmp1FClk = ((0x604 - 0x300) / 4), /*!< Cmp1 FClk Divider. */ + kCLOCK_DivCmp1rrClk = ((0x60C - 0x300) / 4), /*!< Cmp1rr Clk Divider. */ + kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clk Divider. */ + kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clk Divider. */ + kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clk Divider. */ + kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clk Divider. */ + kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clk Divider. */ + kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clk Divider. */ + kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clk Divider. */ + kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clk Divider. */ + kCLOCK_DivSai0Clk = ((0x888 - 0x300) / 4), /*!< Sai0 Clk Divider. */ + kCLOCK_DivSai1Clk = ((0x88C - 0x300) / 4), /*!< Sai1 Clk Divider. */ + kCLOCK_DivI3c1FClk = ((0xB40 - 0x300) / 4), /*!< I3C1 FClk Divider. */ +} clock_div_name_t; + +/*! @brief OSC32K clock gate */ +typedef enum _osc32k_clk_gate_id +{ + kCLOCK_Osc32kToVbat = 0x1, /*!< OSC32K[0] to VBAT domain. */ + kCLOCK_Osc32kToVsys = 0x2, /*!< OSC32K[1] to VSYS domain. */ + kCLOCK_Osc32kToWake = 0x4, /*!< OSC32K[2] to WAKE domain. */ + kCLOCK_Osc32kToMain = 0x8, /*!< OSC32K[3] to MAIN domain. */ + kCLOCK_Osc32kToAll = 0xF, /*!< OSC32K to VBAT,VSYS,WAKE,MAIN domain. */ +} osc32k_clk_gate_id_t; + +/*! @brief CLK16K clock gate */ +typedef enum _clk16k_clk_gate_id +{ + kCLOCK_Clk16KToVbat = 0x1, /*!< Clk16k[0] to VBAT domain. */ + kCLOCK_Clk16KToVsys = 0x2, /*!< Clk16k[1] to VSYS domain. */ + kCLOCK_Clk16KToWake = 0x4, /*!< Clk16k[2] to WAKE domain. */ + kCLOCK_Clk16KToMain = 0x8, /*!< Clk16k[3] to MAIN domain. */ + kCLOCK_Clk16KToAll = 0xF, /*!< Clk16k to VBAT,VSYS,WAKE,MAIN domain. */ +} clk16k_clk_gate_id_t; + +/*! @brief system clocks enable controls */ +typedef enum _clock_ctrl_enable +{ + kCLOCK_FRO1MHZ_CLK_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */ + kCLOCK_CLKIN_ENA = SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1, + SAI0/1, clkout */ + kCLOCK_FRO_HF_ENA = + SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK, /*!< Enables FRO HF clock for the Frequency Measure module. */ + kCLOCK_FRO12MHZ_ENA = SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK, /*!< Enables the FRO_12MHz clock for the Flash, + LPTIMER0/1, and Frequency Measurement modules. */ + kCLOCK_FRO1MHZ_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */ + kCLOCK_CLKIN_ENA_FM_USBH_LPT = + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK, /*!< Enables the clk_in clock for the Frequency Measurement, USB + HS and LPTIMER0/1 modules. */ +} clock_ctrl_enable_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*! + * @brief SCG status return codes. + */ +enum _scg_status +{ + kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ + kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ +}; + +/*! + * @brief firc trim mode. + */ +typedef enum _firc_trim_mode +{ + kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} firc_trim_mode_t; + +/*! + * @brief firc trim source. + */ +typedef enum _firc_trim_src +{ + kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */ + kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} firc_trim_src_t; + +/*! + * @brief firc trim configuration. + */ +typedef struct _firc_trim_config +{ + firc_trim_mode_t trimMode; /*!< Trim mode. */ + firc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} firc_trim_config_t; + +/*! + * @brief sirc trim mode. + */ +typedef enum _sirc_trim_mode +{ + kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} sirc_trim_mode_t; + +/*! + * @brief sirc trim source. + */ +typedef enum _sirc_trim_src +{ + kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_SircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} sirc_trim_src_t; + +/*! + * @brief sirc trim configuration. + */ +typedef struct _sirc_trim_config +{ + sirc_trim_mode_t trimMode; /*!< Trim mode. */ + sirc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} sirc_trim_config_t; + +/*! + * @brief SCG system OSC monitor mode. + */ +typedef enum _scg_sosc_monitor_mode +{ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ + kSCG_SysOscMonitorReset = + SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ +} scg_sosc_monitor_mode_t; + +/*! + * @brief SCG ROSC monitor mode. + */ +typedef enum _scg_rosc_monitor_mode +{ + kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ + kSCG_RoscMonitorReset = + SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */ +} scg_rosc_monitor_mode_t; + +/*! + * @brief SCG UPLL monitor mode. + */ +typedef enum _scg_upll_monitor_mode +{ + kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */ + kSCG_UpllMonitorReset = + SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK /*!< Reset when the UPLL error is detected. */ +} scg_upll_monitor_mode_t; + +/*! + * @brief SCG PLL0 monitor mode. + */ +typedef enum _scg_pll0_monitor_mode +{ + kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */ + kSCG_Pll0MonitorReset = + SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detected. */ +} scg_pll0_monitor_mode_t; + +/*! + * @brief SCG PLL1 monitor mode. + */ +typedef enum _scg_pll1_monitor_mode +{ + kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ + kSCG_Pll1MonitorReset = + SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */ +} scg_pll1_monitor_mode_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's XTAL pin. + */ +typedef enum _vbat_osc_xtal_cap +{ + kVBAT_OscXtal0pFCap = 0x0U, /*!< The internal capacitance for XTAL pin is 0pF. */ + kVBAT_OscXtal2pFCap = 0x1U, /*!< The internal capacitance for XTAL pin is 2pF. */ + kVBAT_OscXtal4pFCap = 0x2U, /*!< The internal capacitance for XTAL pin is 4pF. */ + kVBAT_OscXtal6pFCap = 0x3U, /*!< The internal capacitance for XTAL pin is 6pF. */ + kVBAT_OscXtal8pFCap = 0x4U, /*!< The internal capacitance for XTAL pin is 8pF. */ + kVBAT_OscXtal10pFCap = 0x5U, /*!< The internal capacitance for XTAL pin is 10pF. */ + kVBAT_OscXtal12pFCap = 0x6U, /*!< The internal capacitance for XTAL pin is 12pF. */ + kVBAT_OscXtal14pFCap = 0x7U, /*!< The internal capacitance for XTAL pin is 14pF. */ + kVBAT_OscXtal16pFCap = 0x8U, /*!< The internal capacitance for XTAL pin is 16pF. */ + kVBAT_OscXtal18pFCap = 0x9U, /*!< The internal capacitance for XTAL pin is 18pF. */ + kVBAT_OscXtal20pFCap = 0xAU, /*!< The internal capacitance for XTAL pin is 20pF. */ + kVBAT_OscXtal22pFCap = 0xBU, /*!< The internal capacitance for XTAL pin is 22pF. */ + kVBAT_OscXtal24pFCap = 0xCU, /*!< The internal capacitance for XTAL pin is 24pF. */ + kVBAT_OscXtal26pFCap = 0xDU, /*!< The internal capacitance for XTAL pin is 26pF. */ + kVBAT_OscXtal28pFCap = 0xEU, /*!< The internal capacitance for XTAL pin is 28pF. */ + kVBAT_OscXtal30pFCap = 0xFU, /*!< The internal capacitance for XTAL pin is 30pF. */ +} vbat_osc_xtal_cap_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's EXTAL pin. + */ +typedef enum _vbat_osc_extal_cap +{ + kVBAT_OscExtal0pFCap = 0x0U, /*!< The internal capacitance for EXTAL pin is 0pF. */ + kVBAT_OscExtal2pFCap = 0x1U, /*!< The internal capacitance for EXTAL pin is 2pF. */ + kVBAT_OscExtal4pFCap = 0x2U, /*!< The internal capacitance for EXTAL pin is 4pF. */ + kVBAT_OscExtal6pFCap = 0x3U, /*!< The internal capacitance for EXTAL pin is 6pF. */ + kVBAT_OscExtal8pFCap = 0x4U, /*!< The internal capacitance for EXTAL pin is 8pF. */ + kVBAT_OscExtal10pFCap = 0x5U, /*!< The internal capacitance for EXTAL pin is 10pF. */ + kVBAT_OscExtal12pFCap = 0x6U, /*!< The internal capacitance for EXTAL pin is 12pF. */ + kVBAT_OscExtal14pFCap = 0x7U, /*!< The internal capacitance for EXTAL pin is 14pF. */ + kVBAT_OscExtal16pFCap = 0x8U, /*!< The internal capacitance for EXTAL pin is 16pF. */ + kVBAT_OscExtal18pFCap = 0x9U, /*!< The internal capacitance for EXTAL pin is 18pF. */ + kVBAT_OscExtal20pFCap = 0xAU, /*!< The internal capacitance for EXTAL pin is 20pF. */ + kVBAT_OscExtal22pFCap = 0xBU, /*!< The internal capacitance for EXTAL pin is 22pF. */ + kVBAT_OscExtal24pFCap = 0xCU, /*!< The internal capacitance for EXTAL pin is 24pF. */ + kVBAT_OscExtal26pFCap = 0xDU, /*!< The internal capacitance for EXTAL pin is 26pF. */ + kVBAT_OscExtal28pFCap = 0xEU, /*!< The internal capacitance for EXTAL pin is 28pF. */ + kVBAT_OscExtal30pFCap = 0xFU, /*!< The internal capacitance for EXTAL pin is 30pF. */ +} vbat_osc_extal_cap_t; + +/*! + * @brief The enumerator of osc amplifier gain fine adjustment. + * Changes the oscillator amplitude by modifying the automatic gain control (AGC). + */ +typedef enum _vbat_osc_fine_adjustment_value +{ + kVBAT_OscCoarseAdjustment05 = 0U, + kVBAT_OscCoarseAdjustment10 = 1U, + kVBAT_OscCoarseAdjustment18 = 2U, + kVBAT_OscCoarseAdjustment33 = 3U, +} vbat_osc_coarse_adjustment_value_t; + +/*! + * @brief The structure of oscillator configuration. + */ +typedef struct _vbat_osc_config +{ + bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */ + + bool enableCrystalOscillatorBypass; /*!< enable/disable the crystal oscillator bypass. */ + + vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank, + only useful when the internal capacitance bank is enabled. */ + vbat_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank, only + useful when the internal capacitance bank is enabled. */ + vbat_osc_coarse_adjustment_value_t + coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */ +} vbat_osc_config_t; + +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Midvoltage (1.0 V). */ + kSD_Mode, /*!< Normal voltage (1.1 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x40U; + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x80U; + } + else + { + SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); + } +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x20U; + } + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x40U; + } + } + else + { + SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); + } +} + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_44MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/** + * @brief Initialize the XTAL32/EXTAL32 input clock to given frequency. + * @param id : OSC 32 kHz output clock to specified modules, it should use osc32k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id); + +/** + * @brief Initialize the FRO16K input clock to given frequency. + * @param id : FRO 16 kHz output clock to specified modules, it should use clk16k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id); + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode); + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode); + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode); + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode); + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config); + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access + * time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + * @return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name); + +/** + * @brief system clocks enable controls. + * @param mask : system clocks enable value, it should use clock_ctrl_enable_t value + * @return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPFlexComm Clock + * @return Frequency of LPFlexComm Clock + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id); + +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); + +/*! @brief Return Frequency of PLLCLKDIV + * @return Frequency of PLLCLKDIV Clock + */ +uint32_t CLOCK_GetPllClkDivFreq(void); + +/*! @brief Return Frequency of I3C function Clock + * @return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id); + +/*! @brief Return Frequency of MICFIL Clock + * @return Frequency of MICFIL. + */ +uint32_t CLOCK_GetMicfilClkFreq(void); + +/*! @brief Return Frequency of FLEXIO + * @return Frequency of FLEXIO Clock + */ +uint32_t CLOCK_GetFlexioClkFreq(void); + +/*! @brief Return Frequency of FLEXCAN + * @return Frequency of FLEXCAN Clock + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id); + +/*! @brief Return Frequency of EWM0 Clock + * @return Frequency of EWM0. + */ +uint32_t CLOCK_GetEwm0ClkFreq(void); + +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of UTICK Clock + * @return Frequency of UTICK Clock. + */ +uint32_t CLOCK_GetUtickClkFreq(void); + +/*! @brief Return Frequency of SAI Clock + * @return Frequency of SAI Clock. + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id); + +/** + * @brief Initialize the SAI MCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI TX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI RX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Return Frequency of SAI MCLK + * @return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI TX BCLK + * @return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI RX BCLK + * @return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Gets the external UPLL frequency. + * @return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void); + +/*! @brief Sets the external UPLL frequency. + * @param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq); + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SCG0->SPLLCSR & SCG_SPLLCSR_SPLL_LOCK_MASK) != 0UL); +} + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! + * @brief PLL clock source. + */ +typedef enum _pll_clk_src +{ + kPll_ClkSrcSysOsc = (0 << 25), /*!< System OSC. */ + kPll_ClkSrcFirc = (1 << 25), /*!< Fast IRC. */ + kPll_ClkSrcRosc = (2 << 25), /*!< RTC OSC. */ +} pll_clk_src_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 2), /*!< Nss = 512 (fm ~= 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 2), /*!< Nss ~= 384 (fm ~= 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 2), /*!< Nss = 256 (fm ~= 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 2), /*!< Nss = 128 (fm ~= 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 2), /*!< Nss = 64 (fm ~= 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 2), /*!< Nss = 32 (fm ~= 62.5 - 125 kHz) */ + kSS_MF_24 = (6 << 2), /*!< Nss ~= 24 (fm ~= 83.3 - 166.6 kHz) */ + kSS_MF_16 = (7 << 2) /*!< Nss = 16 (fm ~= 125 - 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 5), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 5), /*!< k ~= 1 */ + kSS_MR_K1_5 = (2 << 5), /*!< k ~= 1.5 */ + kSS_MR_K2 = (3 << 5), /*!< k ~= 2 */ + kSS_MR_K3 = (4 << 5), /*!< k ~= 3 */ + kSS_MR_K4 = (5 << 5), /*!< k ~= 4 */ + kSS_MR_K6 = (6 << 5), /*!< k ~= 6 */ + kSS_MR_K8 = (7 << 5) /*!< k ~= 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 8), /*!< no compensation */ + kSS_MC_RECC = (2 << 8), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 8), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputSource; /*!< PLL input source */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag + */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL Control register APLLCTRL */ + uint32_t pllndiv; /*!< PLL N Divider register APLLNDIV */ + uint32_t pllpdiv; /*!< PLL P Divider register APLLPDIV */ + uint32_t pllmdiv; /*!< PLL M Divider register APLLMDIV */ + uint32_t pllsscg[2]; /*!< PLL Spread Spectrum Control registers APLLSSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_OutputError = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL output rate error */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 8) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief Return PLL0 output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup); + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void); + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void); + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void); + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/devices/MCXN235/drivers/fsl_edma_soc.c b/devices/MCXN235/drivers/fsl_edma_soc.c new file mode 100644 index 000000000..2706eb37e --- /dev/null +++ b/devices/MCXN235/drivers/fsl_edma_soc.c @@ -0,0 +1,289 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void EDMA_0_CH0_DriverIRQHandler(void); +extern void EDMA_0_CH1_DriverIRQHandler(void); +extern void EDMA_0_CH2_DriverIRQHandler(void); +extern void EDMA_0_CH3_DriverIRQHandler(void); +extern void EDMA_0_CH4_DriverIRQHandler(void); +extern void EDMA_0_CH5_DriverIRQHandler(void); +extern void EDMA_0_CH6_DriverIRQHandler(void); +extern void EDMA_0_CH7_DriverIRQHandler(void); +extern void EDMA_0_CH8_DriverIRQHandler(void); +extern void EDMA_0_CH9_DriverIRQHandler(void); +extern void EDMA_0_CH10_DriverIRQHandler(void); +extern void EDMA_0_CH11_DriverIRQHandler(void); +extern void EDMA_0_CH12_DriverIRQHandler(void); +extern void EDMA_0_CH13_DriverIRQHandler(void); +extern void EDMA_0_CH14_DriverIRQHandler(void); +extern void EDMA_0_CH15_DriverIRQHandler(void); +extern void EDMA_1_CH0_DriverIRQHandler(void); +extern void EDMA_1_CH1_DriverIRQHandler(void); +extern void EDMA_1_CH2_DriverIRQHandler(void); +extern void EDMA_1_CH3_DriverIRQHandler(void); +extern void EDMA_1_CH4_DriverIRQHandler(void); +extern void EDMA_1_CH5_DriverIRQHandler(void); +extern void EDMA_1_CH6_DriverIRQHandler(void); +extern void EDMA_1_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void EDMA_0_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void EDMA_0_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void EDMA_0_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void EDMA_0_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void EDMA_0_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} + +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void EDMA_0_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void EDMA_0_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void EDMA_0_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} + +/*! + * brief DMA instance 0, channel 8 IRQ handler. + * + */ +void EDMA_0_CH8_DriverIRQHandler(void) +{ + /* Instance 0 channel 8 */ + EDMA_DriverIRQHandler(0U, 8U); +} + +/*! + * brief DMA instance 0, channel 9 IRQ handler. + * + */ +void EDMA_0_CH9_DriverIRQHandler(void) +{ + /* Instance 0 channel 9 */ + EDMA_DriverIRQHandler(0U, 9U); +} + +/*! + * brief DMA instance 0, channel 10 IRQ handler. + * + */ +void EDMA_0_CH10_DriverIRQHandler(void) +{ + /* Instance 0 channel 10 */ + EDMA_DriverIRQHandler(0U, 10U); +} + +/*! + * brief DMA instance 0, channel 11 IRQ handler. + * + */ +void EDMA_0_CH11_DriverIRQHandler(void) +{ + /* Instance 0 channel 11 */ + EDMA_DriverIRQHandler(0U, 11U); +} + +/*! + * brief DMA instance 0, channel 12 IRQ handler. + * + */ +void EDMA_0_CH12_DriverIRQHandler(void) +{ + /* Instance 0 channel 12 */ + EDMA_DriverIRQHandler(0U, 12U); +} + +/*! + * brief DMA instance 0, channel 13 IRQ handler. + * + */ +void EDMA_0_CH13_DriverIRQHandler(void) +{ + /* Instance 0 channel 13 */ + EDMA_DriverIRQHandler(0U, 13U); +} + +/*! + * brief DMA instance 0, channel 14 IRQ handler. + * + */ +void EDMA_0_CH14_DriverIRQHandler(void) +{ + /* Instance 0 channel 14 */ + EDMA_DriverIRQHandler(0U, 14U); +} + +/*! + * brief DMA instance 0, channel 15 IRQ handler. + * + */ +void EDMA_0_CH15_DriverIRQHandler(void) +{ + /* Instance 0 channel 15 */ + EDMA_DriverIRQHandler(0U, 15U); +} + +/*! + * brief DMA instance 1, channel 0 IRQ handler. + * + */ +void EDMA_1_CH0_DriverIRQHandler(void) +{ + /* Instance 1 channel 0 */ + EDMA_DriverIRQHandler(1U, 0U); +} + +/*! + * brief DMA instance 1, channel 1 IRQ handler. + * + */ +void EDMA_1_CH1_DriverIRQHandler(void) +{ + /* Instance 1 channel 1 */ + EDMA_DriverIRQHandler(1U, 1U); +} + +/*! + * brief DMA instance 1, channel 2 IRQ handler. + * + */ +void EDMA_1_CH2_DriverIRQHandler(void) +{ + /* Instance 1 channel 2 */ + EDMA_DriverIRQHandler(1U, 2U); +} + +/*! + * brief DMA instance 1, channel 3 IRQ handler. + * + */ +void EDMA_1_CH3_DriverIRQHandler(void) +{ + /* Instance 1 channel 3 */ + EDMA_DriverIRQHandler(1U, 3U); +} + +/*! + * brief DMA instance 1, channel 4 IRQ handler. + * + */ +void EDMA_1_CH4_DriverIRQHandler(void) +{ + /* Instance 1 channel 4 */ + EDMA_DriverIRQHandler(1U, 4U); +} + +/*! + * brief DMA instance 1, channel 5 IRQ handler. + * + */ +void EDMA_1_CH5_DriverIRQHandler(void) +{ + /* Instance 1 channel 5 */ + EDMA_DriverIRQHandler(1U, 5U); +} + +/*! + * brief DMA instance 1, channel 6 IRQ handler. + * + */ +void EDMA_1_CH6_DriverIRQHandler(void) +{ + /* Instance 1 channel 6 */ + EDMA_DriverIRQHandler(1U, 6U); +} + +/*! + * brief DMA instance 1, channel 7 IRQ handler. + * + */ +void EDMA_1_CH7_DriverIRQHandler(void) +{ + /* Instance 1 channel 7 */ + EDMA_DriverIRQHandler(1U, 7U); +} diff --git a/devices/MCXN235/drivers/fsl_edma_soc.h b/devices/MCXN235/drivers/fsl_edma_soc.h new file mode 100644 index 000000000..863542cff --- /dev/null +++ b/devices/MCXN235/drivers/fsl_edma_soc.h @@ -0,0 +1,68 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 1.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS \ + { \ + DMA0, DMA1 \ + } + +#define EDMA_CHN_IRQS \ + { \ + {EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, \ + EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, \ + EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn}, \ + { \ + EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, \ + EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/devices/MCXN235/drivers/fsl_inputmux_connections.h b/devices/MCXN235/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..629a6aa25 --- /dev/null +++ b/devices/MCXN235/drivers/fsl_inputmux_connections.h @@ -0,0 +1,3664 @@ +/* + * Copyright 2022 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 0x20U +#define TIMER0TRIGIN 0x30U +#define TIMER1CAPTSEL0 0x40U +#define TIMER1TRIGIN 0x50U +#define TIMER2CAPTSEL0 0x60U +#define TIMER2TRIGIN 0x70U +#define SMARTDMAARCHB_INMUX0 0xA0U +#define PINTSEL0 0xC0U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TAR_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER3TRIGIN 0x1B0U +#define TIMER4CAPTSEL0 0x1C0U +#define TIMER4TRIGIN 0x1D0U +#define CMP0_TRIG_REG 0x260U +#define ADC0_TRIG0 0x280U +#define ADC1_TRIG0 0x2C0U +#define QDC0_TRIG_REG 0x360U +#define QDC0_HOME_REG 0x364U +#define QDC0_INDEX_REG 0x368U +#define QDC0_PHASEB_REG 0x36CU +#define QDC0_PHASEA_REG 0x370U +#define QDC1_TRIG_REG 0x380U +#define QDC1_HOME_REG 0x384U +#define QDC1_INDEX_REG 0x388U +#define QDC1_PHASEB_REG 0x38CU +#define QDC1_PHASEA_REG 0x390U +#define FlexPWM0_SM0_EXTSYNC_REG 0x3A0U +#define FlexPWM0_SM1_EXTSYNC_REG 0x3A4U +#define FlexPWM0_SM2_EXTSYNC_REG 0x3A8U +#define FlexPWM0_SM3_EXTSYNC_REG 0x3ACU +#define FlexPWM0_SM0_EXTA_REG 0x3B0U +#define FlexPWM0_SM1_EXTA_REG 0x3B4U +#define FlexPWM0_SM2_EXTA_REG 0x3B8U +#define FlexPWM0_SM3_EXTA_REG 0x3BCU +#define FlexPWM0_EXTFORCE_REG 0x3C0U +#define FlexPWM0_FAULT0_REG 0x3C4U +#define FlexPWM0_FAULT1_REG 0x3C8U +#define FlexPWM0_FAULT2_REG 0x3CCU +#define FlexPWM0_FAULT3_REG 0x3D0U +#define FlexPWM1_SM0_EXTSYNC_REG 0x3E0U +#define FlexPWM1_SM1_EXTSYNC_REG 0x3E4U +#define FlexPWM1_SM2_EXTSYNC_REG 0x3E8U +#define FlexPWM1_SM3_EXTSYNC_REG 0x3ECU +#define FlexPWM1_SM0_EXTA_REG 0x3F0U +#define FlexPWM1_SM1_EXTA_REG 0x3F4U +#define FlexPWM1_SM2_EXTA_REG 0x3F8U +#define FlexPWM1_SM3_EXTA_REG 0x3FCU +#define FlexPWM1_EXTFORCE_REG 0x400U +#define FlexPWM1_FAULT0_REG 0x404U +#define FlexPWM1_FAULT1_REG 0x408U +#define FlexPWM1_FAULT2_REG 0x40CU +#define FlexPWM1_FAULT3_REG 0x410U +#define PWM0_EXT_CLK_REG 0x420U +#define PWM1_EXT_CLK_REG 0x424U +#define EVTG_TRIG0_REG 0x440U +#define EXT_TRIG0_REG 0x4C0U +#define CMP1_TRIG_REG 0x4E0U +#define FLEXCOMM0_TRIG_REG 0x5A0U +#define FLEXCOMM1_TRIG_REG 0x5C0U +#define FLEXCOMM2_TRIG_REG 0x5E0U +#define FLEXCOMM3_TRIG_REG 0x600U +#define FLEXCOMM4_TRIG_REG 0x620U +#define FLEXCOMM5_TRIG_REG 0x640U +#define FLEXCOMM6_TRIG_REG 0x660U +#define FLEXCOMM7_TRIG_REG 0x680U +#define FLEXIO_TRIG0_REG 0x6E0U + +#define DMA0_REQ_ENABLE0_REG 0x700U +#define DMA0_REQ_ENABLE1_REG 0x710U +#define DMA0_REQ_ENABLE2_REG 0x720U +#define DMA0_REQ_ENABLE3_REG 0x730U +#define DMA1_REQ_ENABLE0_REG 0x780U +#define DMA1_REQ_ENABLE1_REG 0x790U +#define DMA1_REQ_ENABLE2_REG 0x7A0U +#define DMA1_REQ_ENABLE3_REG 0x7B0U + +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Captsel = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Captsel = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Captsel = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Captsel = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Captsel = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Captsel = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Captsel = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Captsel = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Captsel = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Captsel = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 0U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Trigger = 50U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Trigger = 51U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 0U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Trigger = 50U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Trigger = 51U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 0U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Trigger = 50U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Trigger = 51U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 0U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Trigger = 50U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Trigger = 51U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 0U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Trigger = 50U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Trigger = 51U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< SMARTDMA arch B inputs. */ + kINPUTMUX_GpioPort0Pin0ToSmartDma = 0U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToSmartDma = 1U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToSmartDma = 2U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToSmartDma = 3U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToSmartDma = 4U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToSmartDma = 5U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToSmartDma = 6U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToSmartDma = 7U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToSmartDma = 12U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToSmartDma = 13U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToSmartDma = 14U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToSmartDma = 15U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh0IrqToSmartDma = 20U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh1IrqToSmartDma = 21U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToSmartDma = 22U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToSmartDma = 23U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToSmartDma = 24U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToSmartDma = 25U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToSmartDma = 26U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToSmartDma = 27U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_UtickIrqToSmartDma = 28U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Wdt0IrqToSmartDma = 29U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSmartDma = 30U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0IrqToSmartDma = 31U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm7IrqToSmartDma = 33U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm6IrqToSmartDma = 34U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm5IrqToSmartDma = 35U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm4IrqToSmartDma = 36U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3IrqToSmartDma = 37U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2IrqToSmartDma = 38U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1IrqToSmartDma = 39U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0IrqToSmartDma = 40U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0IrqToSmartDma = 41U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1IrqToSmartDma = 42U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SysIrqToSmartDma = 43U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_RtcComboIrqToSmartDma = 44U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSmartDma = 45U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToSmartDma = 46U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToSmartDma = 49U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameIrqToSmartDma = 50U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameIrqToSmartDma = 51U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OsEventTimerIrqToSmartDma = 52U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSmartDma = 53U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp01IrqToSmartDma = 54U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0IrqToSmartDma = 57U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1IrqToSmartDma = 58U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartDma = 59U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartDma = 60U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToSmartDma = 61U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToSmartDma = 62U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToSmartDma = 65U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig1ToSmartDma = 66U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToSmartDma = 67U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToSmartDma = 68U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToSmartDma = 69U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToSmartDma = 70U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest0ToSmartDma = 71U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest1ToSmartDma = 72U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest2ToSmartDma = 73U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest3ToSmartDma = 74U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest4ToSmartDma = 75U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest5ToSmartDma = 76U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest6ToSmartDma = 77U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest7ToSmartDma = 78U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 0U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasTar = 1u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasTar = 4u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_PinInt0ToCmp0Trigger = 0U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToCmp0Trigger = 1U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp0Trigger = 7U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 35U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp0Trigger = 36U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 37U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp0Trigger = 38U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_PinInt0ToCmp1Trigger = 0U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToCmp1Trigger = 1U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp1Trigger = 7U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 35U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp1Trigger = 36U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 37U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp1Trigger = 38U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + + + /*!< Adc0 Trigger. */ + kINPUTMUX_PinInt0ToAdc0Trigger = 0U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAdc0Trigger = 1U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc0Trigger = 5U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc0Trigger = 6U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc0Trigger = 7U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAdc0Trigger = 8U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAdc0Trigger = 9U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc0Trigger = 10U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc0Trigger = 11U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc0Trigger = 12U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc0Trigger = 13U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc0Trigger = 14U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc0Trigger = 15U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc0Trigger = 16U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 17U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 18U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 19U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 20U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 21U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 22U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc0Trigger = 24U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc0Trigger = 25U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc0Trigger = 26U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc0Trigger = 27U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc0Trigger = 28U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc0Trigger = 29U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc0Trigger = 30U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc0Trigger = 31U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc0Trigger = 32U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc0Trigger = 33U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc0Trigger = 34U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc0Trigger = 35U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc0Trigger = 36U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc0Trigger = 45U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc0Trigger = 46U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc0Trigger = 47U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc0Trigger = 48U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc0Trigger = 49U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 50U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc0Trigger = 51U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 52U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 53U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 54U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 55U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 61U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc0Trigger = 62U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 63U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc0Trigger = 64U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 65U + (ADC0_TRIG0 << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_PinInt0ToAdc1Trigger = 0U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToAdc1Trigger = 1U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc1Trigger = 5U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc1Trigger = 6U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc1Trigger = 7U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAdc1Trigger = 8U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 9U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc1Trigger = 10U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc1Trigger = 11U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc1Trigger = 12U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 13U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 14U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 15U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 16U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc1Trigger = 17U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc1Trigger = 18U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc1Trigger = 19U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc1Trigger = 20U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 21U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 22U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc1Trigger = 24U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc1Trigger = 25U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc1Trigger = 26U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc1Trigger = 27U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc1Trigger = 28U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc1Trigger = 29U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc1Trigger = 30U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc1Trigger = 31U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc1Trigger = 32U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc1Trigger = 33U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc1Trigger = 34U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc1Trigger = 35U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc1Trigger = 36U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc1Trigger = 45U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc1Trigger = 46U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc1Trigger = 47U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc1Trigger = 48U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc1Trigger = 49U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 50U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc1Trigger = 51U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 52U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 53U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 54U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 55U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 61U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc1Trigger = 62U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 63U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc1Trigger = 64U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 65U + (ADC1_TRIG0 << PMUX_SHIFT), + + /*!< QDC0 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Trigger = 0U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Trigger = 15U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 45U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 46U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 47U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 48U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< QDC0 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Home = 0U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Home = 15U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 45U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 46U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 47U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 48U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< QDC0 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Index = 0U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Index = 15U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 45U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 46U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 47U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 48U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< QDC0 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phaseb = 0U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phaseb = 15U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 45U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 46U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 47U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 48U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC0 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phasea = 0U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phasea = 15U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 45U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 46U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 47U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 48U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< QDC1 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Trigger = 0U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Trigger = 15U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 45U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 46U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 47U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 48U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< QDC1 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Home = 0U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Home = 15U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 45U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 46U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 47U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 48U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< QDC1 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Index = 0U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Index = 15U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 45U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 46U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 47U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 48U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< QDC1 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phaseb = 0U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phaseb = 15U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 45U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 46U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 47U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 48U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC1 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phasea = 0U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phasea = 15U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 45U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 46U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 47U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 48U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0ExtSync = 0U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0ExtSync = 1U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0ExtSync = 5U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0ExtSync = 6U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0ExtSync = 7U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0ExtSync = 8U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0ExtSync = 9U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0ExtSync = 11U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0ExtSync = 12U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0ExtSync = 13U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0ExtSync = 14U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0ExtSync = 15U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0ExtSync = 16U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0ExtSync = 17U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0ExtSync = 18U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0ExtSync = 19U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0ExtSync = 20U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0ExtSync = 21U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0ExtSync = 22U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0ExtSync = 24U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0ExtSync = 25U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0ExtSync = 26U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0ExtSync = 27U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0ExtSync = 28U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0ExtSync = 29U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0ExtSync = 30U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0ExtSync = 31U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0ExtSync = 32U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0ExtSync = 33U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0ExtSync = 34U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0ExtSync = 35U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0ExtSync = 36U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0ExtSync = 37U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0ExtSync = 38U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0ExtSync = 39U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0ExtSync = 40U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0ExtSync = 41U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0ExtSync = 42U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0ExtSync = 43U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0ExtSync = 44U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0ExtSync = 45U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0ExtSync = 46U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0ExtSync = 47U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0ExtSync = 48U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0ExtSync = 49U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0ExtSync = 50U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0ExtSync = 51U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0ExtSync = 57U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0ExtSync = 58U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0ExtSync = 59U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0ExtSync = 60U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1ExtSync = 0U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1ExtSync = 1U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1ExtSync = 5U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1ExtSync = 6U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1ExtSync = 7U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1ExtSync = 8U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1ExtSync = 9U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1ExtSync = 11U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1ExtSync = 12U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1ExtSync = 13U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1ExtSync = 14U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1ExtSync = 15U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1ExtSync = 16U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1ExtSync = 17U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1ExtSync = 18U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1ExtSync = 19U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1ExtSync = 20U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1ExtSync = 21U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1ExtSync = 22U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1ExtSync = 24U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1ExtSync = 25U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1ExtSync = 26U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1ExtSync = 27U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1ExtSync = 28U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1ExtSync = 29U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1ExtSync = 30U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1ExtSync = 31U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1ExtSync = 32U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1ExtSync = 33U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1ExtSync = 34U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1ExtSync = 35U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1ExtSync = 36U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1ExtSync = 37U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1ExtSync = 38U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1ExtSync = 39U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1ExtSync = 40U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1ExtSync = 41U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1ExtSync = 42U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1ExtSync = 43U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1ExtSync = 44U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1ExtSync = 45U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1ExtSync = 46U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1ExtSync = 47U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1ExtSync = 48U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1ExtSync = 49U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1ExtSync = 50U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1ExtSync = 51U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1ExtSync = 57U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1ExtSync = 58U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1ExtSync = 59U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1ExtSync = 60U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2ExtSync = 0U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2ExtSync = 1U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2ExtSync = 5U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2ExtSync = 6U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2ExtSync = 7U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2ExtSync = 8U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2ExtSync = 9U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2ExtSync = 11U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2ExtSync = 12U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2ExtSync = 13U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2ExtSync = 14U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2ExtSync = 15U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2ExtSync = 16U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2ExtSync = 17U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2ExtSync = 18U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2ExtSync = 19U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2ExtSync = 20U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2ExtSync = 21U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2ExtSync = 22U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2ExtSync = 24U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2ExtSync = 25U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2ExtSync = 26U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2ExtSync = 27U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2ExtSync = 28U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2ExtSync = 29U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2ExtSync = 30U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2ExtSync = 31U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2ExtSync = 32U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2ExtSync = 33U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2ExtSync = 34U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2ExtSync = 35U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2ExtSync = 36U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2ExtSync = 37U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2ExtSync = 38U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2ExtSync = 39U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2ExtSync = 40U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2ExtSync = 41U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2ExtSync = 42U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2ExtSync = 43U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2ExtSync = 44U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2ExtSync = 45U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2ExtSync = 46U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2ExtSync = 47U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2ExtSync = 48U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2ExtSync = 49U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2ExtSync = 50U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2ExtSync = 51U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2ExtSync = 57U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2ExtSync = 58U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2ExtSync = 59U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2ExtSync = 60U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3ExtSync = 0U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3ExtSync = 1U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3ExtSync = 5U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3ExtSync = 6U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3ExtSync = 7U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3ExtSync = 8U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3ExtSync = 9U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3ExtSync = 11U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3ExtSync = 12U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3ExtSync = 13U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3ExtSync = 14U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3ExtSync = 15U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3ExtSync = 16U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3ExtSync = 17U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3ExtSync = 18U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3ExtSync = 19U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3ExtSync = 20U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3ExtSync = 21U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3ExtSync = 22U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3ExtSync = 24U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3ExtSync = 25U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3ExtSync = 26U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3ExtSync = 27U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3ExtSync = 28U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3ExtSync = 29U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3ExtSync = 30U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3ExtSync = 31U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3ExtSync = 32U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3ExtSync = 33U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3ExtSync = 34U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3ExtSync = 35U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3ExtSync = 36U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3ExtSync = 37U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3ExtSync = 38U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3ExtSync = 39U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3ExtSync = 40U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3ExtSync = 41U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3ExtSync = 42U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3ExtSync = 43U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3ExtSync = 44U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3ExtSync = 45U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3ExtSync = 46U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3ExtSync = 47U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3ExtSync = 48U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3ExtSync = 49U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3ExtSync = 50U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3ExtSync = 51U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3ExtSync = 57U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3ExtSync = 58U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3ExtSync = 59U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3ExtSync = 60U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0Exta = 0U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0Exta = 1U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta = 5U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta = 6U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta = 7U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0Exta = 8U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0Exta = 9U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta = 11U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0Exta = 12U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0Exta = 13U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0Exta = 14U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0Exta = 15U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0Exta = 16U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0Exta = 17U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0Exta = 18U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0Exta = 19U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0Exta = 20U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta = 21U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta = 22U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0Exta = 24U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0Exta = 25U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0Exta = 26U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0Exta = 27U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0Exta = 28U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0Exta = 29U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0Exta = 30U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0Exta = 31U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0Exta = 32U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0Exta = 33U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0Exta = 34U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0Exta = 35U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0Exta = 36U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0Exta = 37U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0Exta = 38U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0Exta = 39U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0Exta = 40U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0Exta = 41U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta = 42U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta = 43U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta = 44U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta = 45U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta = 46U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta = 47U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta = 48U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta = 49U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta = 50U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta = 51U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta = 57U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0Exta = 58U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta = 59U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0Exta = 60U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1Exta = 0U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1Exta = 1U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta = 5U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta = 6U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta = 7U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1Exta = 8U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1Exta = 9U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta = 11U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1Exta = 12U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1Exta = 13U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1Exta = 14U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1Exta = 15U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1Exta = 16U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1Exta = 17U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1Exta = 18U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1Exta = 19U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1Exta = 20U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta = 21U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta = 22U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1Exta = 24U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1Exta = 25U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1Exta = 26U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1Exta = 27U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1Exta = 28U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1Exta = 29U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1Exta = 30U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1Exta = 31U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1Exta = 32U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1Exta = 33U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1Exta = 34U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1Exta = 35U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1Exta = 36U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1Exta = 37U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1Exta = 38U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1Exta = 39U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1Exta = 40U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1Exta = 41U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta = 42U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta = 43U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta = 44U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta = 45U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta = 46U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta = 47U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta = 48U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta = 49U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta = 50U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta = 51U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta = 57U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1Exta = 58U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta = 59U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1Exta = 60U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2Exta = 0U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2Exta = 1U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta = 5U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta = 6U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta = 7U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2Exta = 8U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2Exta = 9U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta = 11U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2Exta = 12U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2Exta = 13U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2Exta = 14U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2Exta = 15U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2Exta = 16U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2Exta = 17U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2Exta = 18U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2Exta = 19U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2Exta = 20U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta = 21U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta = 22U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2Exta = 24U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2Exta = 25U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2Exta = 26U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2Exta = 27U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2Exta = 28U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2Exta = 29U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2Exta = 30U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2Exta = 31U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2Exta = 32U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2Exta = 33U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2Exta = 34U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2Exta = 35U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2Exta = 36U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2Exta = 37U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2Exta = 38U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2Exta = 39U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2Exta = 40U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2Exta = 41U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta = 42U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta = 43U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta = 44U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta = 45U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta = 46U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta = 47U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta = 48U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta = 49U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta = 50U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta = 51U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta = 57U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2Exta = 58U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta = 59U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2Exta = 60U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3Exta = 0U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3Exta = 1U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta = 5U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta = 6U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta = 7U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3Exta = 8U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3Exta = 9U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta = 11U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3Exta = 12U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3Exta = 13U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3Exta = 14U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3Exta = 15U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3Exta = 16U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3Exta = 17U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3Exta = 18U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3Exta = 19U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3Exta = 20U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta = 21U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta = 22U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3Exta = 24U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3Exta = 25U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3Exta = 26U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3Exta = 27U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3Exta = 28U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3Exta = 29U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3Exta = 30U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3Exta = 31U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3Exta = 32U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3Exta = 33U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3Exta = 34U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3Exta = 35U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3Exta = 36U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3Exta = 37U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3Exta = 38U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3Exta = 39U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3Exta = 40U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3Exta = 41U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta = 42U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta = 43U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta = 44U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta = 45U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta = 46U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta = 47U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta = 48U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta = 49U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta = 50U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta = 51U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta = 57U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3Exta = 58U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta = 59U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3Exta = 60U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0ExtForce = 0U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0ExtForce = 1U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0ExtForce = 5U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0ExtForce = 6U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0ExtForce = 7U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0ExtForce = 8U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0ExtForce = 9U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0ExtForce = 11U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0ExtForce = 12U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0ExtForce = 13U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0ExtForce = 14U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0ExtForce = 15U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0ExtForce = 16U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0ExtForce = 17U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0ExtForce = 18U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0ExtForce = 19U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0ExtForce = 20U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0ExtForce = 21U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0ExtForce = 22U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0ExtForce = 24U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0ExtForce = 25U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0ExtForce = 26U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0ExtForce = 27U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0ExtForce = 28U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0ExtForce = 29U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0ExtForce = 30U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0ExtForce = 31U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0ExtForce = 32U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0ExtForce = 33U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0ExtForce = 34U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0ExtForce = 35U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0ExtForce = 36U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0ExtForce = 37U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0ExtForce = 38U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0ExtForce = 39U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0ExtForce = 40U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0ExtForce = 41U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0ExtForce = 42U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0ExtForce = 43U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0ExtForce = 44U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0ExtForce = 45U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0ExtForce = 46U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0ExtForce = 47U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0ExtForce = 48U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0ExtForce = 49U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0ExtForce = 50U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0ExtForce = 51U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0ExtForce = 57U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0ExtForce = 58U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0ExtForce = 59U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0ExtForce = 60U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault0 = 0U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault0 = 1U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault0 = 5U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault0 = 6U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault0 = 7U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault0 = 8U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault0 = 9U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault0 = 11U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault0 = 12U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault0 = 13U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault0 = 14U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault0 = 15U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault0 = 16U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault0 = 17U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault0 = 18U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault0 = 19U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault0 = 20U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault0 = 21U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault0 = 22U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault0 = 24U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault0 = 25U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault0 = 26U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault0 = 27U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault0 = 28U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault0 = 29U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault0 = 30U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault0 = 31U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault0 = 32U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault0 = 33U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault0 = 34U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault0 = 35U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault0 = 36U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault0 = 37U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault0 = 38U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault0 = 39U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault0 = 40U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault0 = 41U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault0 = 42U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault0 = 43U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault0 = 44U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault0 = 45U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault0 = 46U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault0 = 47U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault0 = 48U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault0 = 49U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault0 = 50U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault0 = 51U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault0 = 57U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault0 = 58U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault0 = 59U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault0 = 60U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault1 = 0U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault1 = 1U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault1 = 5U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault1 = 6U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault1 = 7U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault1 = 8U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault1 = 9U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault1 = 11U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault1 = 12U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault1 = 13U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault1 = 14U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault1 = 15U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault1 = 16U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault1 = 17U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault1 = 18U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault1 = 19U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault1 = 20U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault1 = 21U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault1 = 22U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault1 = 24U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault1 = 25U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault1 = 26U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault1 = 27U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault1 = 28U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault1 = 29U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault1 = 30U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault1 = 31U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault1 = 32U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault1 = 33U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault1 = 34U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault1 = 35U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault1 = 36U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault1 = 37U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault1 = 38U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault1 = 39U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault1 = 40U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault1 = 41U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault1 = 42U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault1 = 43U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault1 = 44U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault1 = 45U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault1 = 46U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault1 = 47U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault1 = 48U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault1 = 49U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault1 = 50U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault1 = 51U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault1 = 57U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault1 = 58U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault1 = 59U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault1 = 60U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault2 = 0U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault2 = 1U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault2 = 5U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault2 = 6U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault2 = 7U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault2 = 8U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault2 = 9U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault2 = 11U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault2 = 12U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault2 = 13U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault2 = 14U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault2 = 15U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault2 = 16U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault2 = 17U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault2 = 18U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault2 = 19U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault2 = 20U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault2 = 21U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault2 = 22U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault2 = 24U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault2 = 25U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault2 = 26U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault2 = 27U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault2 = 28U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault2 = 29U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault2 = 30U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault2 = 31U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault2 = 32U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault2 = 33U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault2 = 34U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault2 = 35U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault2 = 36U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault2 = 37U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault2 = 38U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault2 = 39U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault2 = 40U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault2 = 41U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault2 = 42U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault2 = 43U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault2 = 44U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault2 = 45U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault2 = 46U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault2 = 47U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault2 = 48U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault2 = 49U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault2 = 50U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault2 = 51U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault2 = 57U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault2 = 58U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault2 = 59U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault2 = 60U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault3 = 0U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault3 = 1U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault3 = 5U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault3 = 6U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault3 = 7U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault3 = 8U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault3 = 9U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault3 = 11U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault3 = 12U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault3 = 13U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault3 = 14U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault3 = 15U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault3 = 16U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault3 = 17U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault3 = 18U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault3 = 19U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault3 = 20U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault3 = 21U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault3 = 22U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault3 = 24U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault3 = 25U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault3 = 26U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault3 = 27U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault3 = 28U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault3 = 29U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault3 = 30U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault3 = 31U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault3 = 32U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault3 = 33U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault3 = 34U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault3 = 35U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault3 = 36U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault3 = 37U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault3 = 38U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault3 = 39U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault3 = 40U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault3 = 41U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault3 = 42U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault3 = 43U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault3 = 44U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault3 = 45U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault3 = 46U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault3 = 47U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault3 = 48U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault3 = 49U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault3 = 50U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault3 = 51U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault3 = 57U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault3 = 58U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault3 = 59U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault3 = 60U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0ExtSync = 0U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0ExtSync = 1U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0ExtSync = 5U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0ExtSync = 6U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0ExtSync = 7U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0ExtSync = 8U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0ExtSync = 9U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0ExtSync = 11U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0ExtSync = 12U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0ExtSync = 13U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0ExtSync = 14U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0ExtSync = 15U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0ExtSync = 16U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0ExtSync = 17U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0ExtSync = 18U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0ExtSync = 19U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0ExtSync = 20U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0ExtSync = 21U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0ExtSync = 22U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0ExtSync = 24U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0ExtSync = 25U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0ExtSync = 26U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0ExtSync = 27U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0ExtSync = 28U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0ExtSync = 29U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0ExtSync = 30U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0ExtSync = 31U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0ExtSync = 32U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0ExtSync = 33U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0ExtSync = 34U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0ExtSync = 35U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0ExtSync = 36U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0ExtSync = 37U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0ExtSync = 38U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0ExtSync = 39U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0ExtSync = 40U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0ExtSync = 41U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0ExtSync = 42U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0ExtSync = 43U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0ExtSync = 44U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0ExtSync = 45U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0ExtSync = 46U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0ExtSync = 47U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0ExtSync = 48U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0ExtSync = 49U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0ExtSync = 50U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0ExtSync = 51U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0ExtSync = 57U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0ExtSync = 58U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0ExtSync = 59U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0ExtSync = 60U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1ExtSync = 0U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1ExtSync = 1U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1ExtSync = 5U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1ExtSync = 6U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1ExtSync = 7U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1ExtSync = 8U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1ExtSync = 9U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1ExtSync = 11U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1ExtSync = 12U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1ExtSync = 13U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1ExtSync = 14U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1ExtSync = 15U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1ExtSync = 16U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1ExtSync = 17U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1ExtSync = 18U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1ExtSync = 19U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1ExtSync = 20U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1ExtSync = 21U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1ExtSync = 22U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1ExtSync = 24U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1ExtSync = 25U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1ExtSync = 26U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1ExtSync = 27U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1ExtSync = 28U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1ExtSync = 29U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1ExtSync = 30U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1ExtSync = 31U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1ExtSync = 32U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1ExtSync = 33U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1ExtSync = 34U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1ExtSync = 35U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1ExtSync = 36U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1ExtSync = 37U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1ExtSync = 38U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1ExtSync = 39U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1ExtSync = 40U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1ExtSync = 41U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1ExtSync = 42U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1ExtSync = 43U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1ExtSync = 44U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1ExtSync = 45U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1ExtSync = 46U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1ExtSync = 47U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1ExtSync = 48U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1ExtSync = 49U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1ExtSync = 50U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1ExtSync = 51U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1ExtSync = 57U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1ExtSync = 58U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1ExtSync = 59U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1ExtSync = 60U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2ExtSync = 0U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2ExtSync = 1U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2ExtSync = 5U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2ExtSync = 6U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2ExtSync = 7U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2ExtSync = 8U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2ExtSync = 9U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2ExtSync = 11U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2ExtSync = 12U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2ExtSync = 13U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2ExtSync = 14U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2ExtSync = 15U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2ExtSync = 16U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2ExtSync = 17U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2ExtSync = 18U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2ExtSync = 19U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2ExtSync = 20U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2ExtSync = 21U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2ExtSync = 22U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2ExtSync = 24U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2ExtSync = 25U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2ExtSync = 26U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2ExtSync = 27U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2ExtSync = 28U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2ExtSync = 29U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2ExtSync = 30U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2ExtSync = 31U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2ExtSync = 32U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2ExtSync = 33U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2ExtSync = 34U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2ExtSync = 35U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2ExtSync = 36U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2ExtSync = 37U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2ExtSync = 38U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2ExtSync = 39U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2ExtSync = 40U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2ExtSync = 41U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2ExtSync = 42U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2ExtSync = 43U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2ExtSync = 44U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2ExtSync = 45U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2ExtSync = 46U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2ExtSync = 47U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2ExtSync = 48U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2ExtSync = 49U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2ExtSync = 50U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2ExtSync = 51U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2ExtSync = 57U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2ExtSync = 58U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2ExtSync = 59U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2ExtSync = 60U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3ExtSync = 0U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3ExtSync = 1U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3ExtSync = 5U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3ExtSync = 6U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3ExtSync = 7U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3ExtSync = 8U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3ExtSync = 9U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3ExtSync = 11U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3ExtSync = 12U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3ExtSync = 13U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3ExtSync = 14U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3ExtSync = 15U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3ExtSync = 16U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3ExtSync = 17U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3ExtSync = 18U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3ExtSync = 19U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3ExtSync = 20U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3ExtSync = 21U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3ExtSync = 22U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3ExtSync = 24U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3ExtSync = 25U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3ExtSync = 26U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3ExtSync = 27U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3ExtSync = 28U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3ExtSync = 29U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3ExtSync = 30U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3ExtSync = 31U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3ExtSync = 32U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3ExtSync = 33U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3ExtSync = 34U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3ExtSync = 35U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3ExtSync = 36U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3ExtSync = 37U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3ExtSync = 38U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3ExtSync = 39U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3ExtSync = 40U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3ExtSync = 41U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3ExtSync = 42U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3ExtSync = 43U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3ExtSync = 44U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3ExtSync = 45U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3ExtSync = 46U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3ExtSync = 47U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3ExtSync = 48U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3ExtSync = 49U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3ExtSync = 50U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3ExtSync = 51U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3ExtSync = 57U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3ExtSync = 58U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3ExtSync = 59U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3ExtSync = 60U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0Exta = 0U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0Exta = 1U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta = 5U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta = 6U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta = 7U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0Exta = 8U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0Exta = 9U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta = 11U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0Exta = 12U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0Exta = 13U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0Exta = 14U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0Exta = 15U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0Exta = 16U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0Exta = 17U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0Exta = 18U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0Exta = 19U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0Exta = 20U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta = 21U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta = 22U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0Exta = 24U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0Exta = 25U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0Exta = 26U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0Exta = 27U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0Exta = 28U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0Exta = 29U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0Exta = 30U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0Exta = 31U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0Exta = 32U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0Exta = 33U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0Exta = 34U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0Exta = 35U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0Exta = 36U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0Exta = 37U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0Exta = 38U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0Exta = 39U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0Exta = 40U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0Exta = 41U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta = 42U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta = 43U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta = 44U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta = 45U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta = 46U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta = 47U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta = 48U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta = 49U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta = 50U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta = 51U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta = 57U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0Exta = 58U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta = 59U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0Exta = 60U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1Exta = 0U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1Exta = 1U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta = 5U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta = 6U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta = 7U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1Exta = 8U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1Exta = 9U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta = 11U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1Exta = 12U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1Exta = 13U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1Exta = 14U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1Exta = 15U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1Exta = 16U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1Exta = 17U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1Exta = 18U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1Exta = 19U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1Exta = 20U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta = 21U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta = 22U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1Exta = 24U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1Exta = 25U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1Exta = 26U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1Exta = 27U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1Exta = 28U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1Exta = 29U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1Exta = 30U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1Exta = 31U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1Exta = 32U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1Exta = 33U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1Exta = 34U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1Exta = 35U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1Exta = 36U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1Exta = 37U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1Exta = 38U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1Exta = 39U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1Exta = 40U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1Exta = 41U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta = 42U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta = 43U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta = 44U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta = 45U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta = 46U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta = 47U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta = 48U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta = 49U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta = 50U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta = 51U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta = 57U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1Exta = 58U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta = 59U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1Exta = 60U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2Exta = 0U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2Exta = 1U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta = 5U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta = 6U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta = 7U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2Exta = 8U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2Exta = 9U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta = 11U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2Exta = 12U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2Exta = 13U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2Exta = 14U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2Exta = 15U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2Exta = 16U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2Exta = 17U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2Exta = 18U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2Exta = 19U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2Exta = 20U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta = 21U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta = 22U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2Exta = 24U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2Exta = 25U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2Exta = 26U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2Exta = 27U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2Exta = 28U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2Exta = 29U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2Exta = 30U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2Exta = 31U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2Exta = 32U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2Exta = 33U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2Exta = 34U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2Exta = 35U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2Exta = 36U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2Exta = 37U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2Exta = 38U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2Exta = 39U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2Exta = 40U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2Exta = 41U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta = 42U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta = 43U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta = 44U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta = 45U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta = 46U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta = 47U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta = 48U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta = 49U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta = 50U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta = 51U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta = 57U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2Exta = 58U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta = 59U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2Exta = 60U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3Exta = 0U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3Exta = 1U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta = 5U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta = 6U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta = 7U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3Exta = 8U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3Exta = 9U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta = 11U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3Exta = 12U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3Exta = 13U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3Exta = 14U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3Exta = 15U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3Exta = 16U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3Exta = 17U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3Exta = 18U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3Exta = 19U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3Exta = 20U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta = 21U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta = 22U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3Exta = 24U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3Exta = 25U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3Exta = 26U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3Exta = 27U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3Exta = 28U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3Exta = 29U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3Exta = 30U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3Exta = 31U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3Exta = 32U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3Exta = 33U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3Exta = 34U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3Exta = 35U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3Exta = 36U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3Exta = 37U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3Exta = 38U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3Exta = 39U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3Exta = 40U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3Exta = 41U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta = 42U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta = 43U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta = 44U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta = 45U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta = 46U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta = 47U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta = 48U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta = 49U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta = 50U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta = 51U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta = 57U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3Exta = 58U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta = 59U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3Exta = 60U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1ExtForce = 0U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1ExtForce = 1U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1ExtForce = 5U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1ExtForce = 6U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1ExtForce = 7U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1ExtForce = 8U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1ExtForce = 9U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1ExtForce = 11U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1ExtForce = 12U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1ExtForce = 13U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1ExtForce = 14U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1ExtForce = 15U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1ExtForce = 16U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1ExtForce = 17U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1ExtForce = 18U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1ExtForce = 19U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1ExtForce = 20U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1ExtForce = 21U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1ExtForce = 22U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1ExtForce = 24U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1ExtForce = 25U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1ExtForce = 26U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1ExtForce = 27U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1ExtForce = 28U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1ExtForce = 29U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1ExtForce = 30U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1ExtForce = 31U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1ExtForce = 32U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1ExtForce = 33U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1ExtForce = 34U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1ExtForce = 35U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1ExtForce = 36U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1ExtForce = 37U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1ExtForce = 38U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1ExtForce = 39U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1ExtForce = 40U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1ExtForce = 41U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1ExtForce = 42U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1ExtForce = 43U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1ExtForce = 44U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1ExtForce = 45U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1ExtForce = 46U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1ExtForce = 47U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1ExtForce = 48U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1ExtForce = 49U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1ExtForce = 50U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1ExtForce = 51U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1ExtForce = 57U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1ExtForce = 58U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1ExtForce = 59U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1ExtForce = 60U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault0 = 0U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault0 = 1U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault0 = 5U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault0 = 6U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault0 = 7U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault0 = 8U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault0 = 9U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault0 = 11U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault0 = 12U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault0 = 13U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault0 = 14U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault0 = 15U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault0 = 16U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault0 = 17U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault0 = 18U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault0 = 19U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault0 = 20U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault0 = 21U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault0 = 22U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault0 = 24U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault0 = 25U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault0 = 26U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault0 = 27U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault0 = 28U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault0 = 29U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault0 = 30U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault0 = 31U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault0 = 32U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault0 = 33U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault0 = 34U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault0 = 35U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault0 = 36U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault0 = 37U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault0 = 38U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault0 = 39U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault0 = 40U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault0 = 41U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault0 = 42U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault0 = 43U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault0 = 44U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault0 = 45U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault0 = 46U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault0 = 47U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault0 = 48U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault0 = 49U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault0 = 50U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault0 = 51U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault0 = 57U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault0 = 58U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault0 = 59U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault0 = 60U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault1 = 0U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault1 = 1U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault1 = 5U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault1 = 6U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault1 = 7U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault1 = 8U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault1 = 9U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault1 = 11U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault1 = 12U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault1 = 13U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault1 = 14U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault1 = 15U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault1 = 16U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault1 = 17U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault1 = 18U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault1 = 19U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault1 = 20U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault1 = 21U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault1 = 22U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault1 = 24U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault1 = 25U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault1 = 26U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault1 = 27U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault1 = 28U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault1 = 29U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault1 = 30U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault1 = 31U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault1 = 32U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault1 = 33U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault1 = 34U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault1 = 35U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault1 = 36U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault1 = 37U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault1 = 38U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault1 = 39U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault1 = 40U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault1 = 41U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault1 = 42U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault1 = 43U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault1 = 44U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault1 = 45U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault1 = 46U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault1 = 47U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault1 = 48U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault1 = 49U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault1 = 50U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault1 = 51U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault1 = 57U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault1 = 58U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault1 = 59U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault1 = 60U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault2 = 0U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault2 = 1U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault2 = 5U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault2 = 6U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault2 = 7U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault2 = 8U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault2 = 9U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault2 = 11U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault2 = 12U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault2 = 13U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault2 = 14U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault2 = 15U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault2 = 16U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault2 = 17U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault2 = 18U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault2 = 19U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault2 = 20U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault2 = 21U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault2 = 22U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault2 = 24U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault2 = 25U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault2 = 26U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault2 = 27U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault2 = 28U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault2 = 29U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault2 = 30U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault2 = 31U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault2 = 32U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault2 = 33U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault2 = 34U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault2 = 35U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault2 = 36U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault2 = 37U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault2 = 38U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault2 = 39U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault2 = 40U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault2 = 41U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault2 = 42U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault2 = 43U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault2 = 44U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault2 = 45U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault2 = 46U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault2 = 47U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault2 = 48U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault2 = 49U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault2 = 50U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault2 = 51U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault2 = 57U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault2 = 58U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault2 = 59U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault2 = 60U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault3 = 0U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault3 = 1U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault3 = 5U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault3 = 6U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault3 = 7U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault3 = 8U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault3 = 9U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault3 = 11U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault3 = 12U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault3 = 13U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault3 = 14U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault3 = 15U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault3 = 16U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault3 = 17U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault3 = 18U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault3 = 19U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault3 = 20U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault3 = 21U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault3 = 22U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault3 = 24U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault3 = 25U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault3 = 26U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault3 = 27U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault3 = 28U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault3 = 29U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault3 = 30U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault3 = 31U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault3 = 32U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault3 = 33U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault3 = 34U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault3 = 35U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault3 = 36U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault3 = 37U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault3 = 38U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault3 = 39U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault3 = 40U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault3 = 41U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault3 = 42U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault3 = 43U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault3 = 44U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault3 = 45U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault3 = 46U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault3 = 47U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault3 = 48U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault3 = 49U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault3 = 50U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault3 = 51U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault3 = 57U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault3 = 58U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault3 = 59U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault3 = 60U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Fro16KToPwm0ExtClk = 0U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Fro16KToPwm1ExtClk = 0U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< EVTG trigger input connections. */ + kINPUTMUX_PinInt0ToEvtgTrigger = 0U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToEvtgTrigger = 1U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEvtgTrigger = 6U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEvtgTrigger = 7U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEvtgTrigger = 8U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToEvtgTrigger = 9U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToEvtgTrigger = 10U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToEvtgTrigger = 11U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToEvtgTrigger = 13U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToEvtgTrigger = 14U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToEvtgTrigger = 15U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEvtgTrigger = 16U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEvtgTrigger = 17U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEvtgTrigger = 18U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEvtgTrigger = 19U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEvtgTrigger = 20U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEvtgTrigger = 21U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEvtgTrigger = 22U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEvtgTrigger = 23U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToEvtgTrigger = 24U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToEvtgTrigger = 25U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToEvtgTrigger = 27U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToEvtgTrigger = 28U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToEvtgTrigger = 29U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToEvtgTrigger = 30U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToEvtgTrigger = 31U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToEvtgTrigger = 32U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToEvtgTrigger = 33U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToEvtgTrigger = 34U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToEvtgTrigger = 35U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToEvtgTrigger = 36U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToEvtgTrigger = 37U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToEvtgTrigger = 38U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToEvtgTrigger = 39U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToEvtgTrigger = 40U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToEvtgTrigger = 41U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToEvtgTrigger = 42U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToEvtgTrigger = 43U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToEvtgTrigger = 44U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToEvtgTrigger = 45U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToEvtgTrigger = 46U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToEvtgTrigger = 47U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToEvtgTrigger = 48U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToEvtgTrigger = 49U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToEvtgTrigger = 50U + (EVTG_TRIG0_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_PinInt0ToExtTrigger = 0U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToExtTrigger = 1U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToExtTrigger = 8U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToExtTrigger = 20U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToExtTrigger = 21U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToExtTrigger = 22U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToExtTrigger = 23U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToExtTrigger = 26U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToExtTrigger = 27U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig3ToExtTrigger = 34U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig3ToExtTrigger = 35U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig3ToExtTrigger = 36U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToExtTrigger = 37U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm4Trig3ToExtTrigger = 38U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm5Trig3ToExtTrigger = 39U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm6Trig3ToExtTrigger = 40U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm7Trig3ToExtTrigger = 41U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 44U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 45U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< FLEXCOMM0 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm0Trigger = 0U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm0Trigger = 1U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm0Trigger = 2U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm0Trigger = 6U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm0Trigger = 7U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm0Trigger = 8U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm0Trigger = 9U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm0Trigger = 10U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm0Trigger = 11U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm0Trigger = 12U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm0Trigger = 13U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm0Trigger = 14U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm0Trigger = 15U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm0Trigger = 16U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm0Trigger = 18U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm0Trigger = 19U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm0Trigger = 20U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm0Trigger = 21U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm0Trigger = 22U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm0Trigger = 23U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm0Trigger = 24U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm0Trigger = 25U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm0Trigger = 26U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm0Trigger = 27U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm0Trigger = 28U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm0Trigger = 29U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm0Trigger = 30U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm0Trigger = 31U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm0Trigger = 32U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm0Trigger = 33U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm0Trigger = 34U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm0Trigger = 35U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm0Trigger = 36U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm0Trigger = 37U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm0Trigger = 38U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm0Trigger = 39U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm0Trigger = 40U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm0Trigger = 41U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm0Trigger = 42U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM1 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm1Trigger = 0U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm1Trigger = 1U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm1Trigger = 2U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm1Trigger = 6U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm1Trigger = 7U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm1Trigger = 8U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm1Trigger = 9U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm1Trigger = 10U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm1Trigger = 11U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm1Trigger = 12U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm1Trigger = 13U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm1Trigger = 14U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm1Trigger = 15U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm1Trigger = 16U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm1Trigger = 18U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm1Trigger = 19U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm1Trigger = 20U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm1Trigger = 21U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm1Trigger = 22U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm1Trigger = 23U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm1Trigger = 24U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm1Trigger = 25U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm1Trigger = 26U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm1Trigger = 27U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm1Trigger = 28U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm1Trigger = 29U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm1Trigger = 30U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm1Trigger = 31U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm1Trigger = 32U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm1Trigger = 33U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm1Trigger = 34U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm1Trigger = 35U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm1Trigger = 36U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm1Trigger = 37U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm1Trigger = 38U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm1Trigger = 39U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm1Trigger = 40U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm1Trigger = 41U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm1Trigger = 42U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM2 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm2Trigger = 0U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm2Trigger = 1U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm2Trigger = 2U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm2Trigger = 6U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm2Trigger = 7U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm2Trigger = 8U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm2Trigger = 9U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm2Trigger = 10U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm2Trigger = 11U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm2Trigger = 12U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm2Trigger = 13U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm2Trigger = 14U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm2Trigger = 15U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm2Trigger = 16U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm2Trigger = 18U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm2Trigger = 19U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm2Trigger = 20U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm2Trigger = 21U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm2Trigger = 22U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm2Trigger = 23U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm2Trigger = 24U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm2Trigger = 25U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm2Trigger = 26U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm2Trigger = 27U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm2Trigger = 28U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm2Trigger = 29U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm2Trigger = 30U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm2Trigger = 31U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm2Trigger = 32U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm2Trigger = 33U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm2Trigger = 34U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm2Trigger = 35U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm2Trigger = 36U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm2Trigger = 37U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm2Trigger = 38U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm2Trigger = 39U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm2Trigger = 40U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm2Trigger = 41U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm2Trigger = 42U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM3 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm3Trigger = 0U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm3Trigger = 1U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm3Trigger = 2U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm3Trigger = 6U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm3Trigger = 7U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm3Trigger = 8U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm3Trigger = 9U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm3Trigger = 10U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm3Trigger = 11U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm3Trigger = 12U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm3Trigger = 13U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm3Trigger = 14U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm3Trigger = 15U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm3Trigger = 16U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm3Trigger = 18U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm3Trigger = 19U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm3Trigger = 20U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm3Trigger = 21U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm3Trigger = 22U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm3Trigger = 23U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm3Trigger = 24U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm3Trigger = 25U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm3Trigger = 26U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm3Trigger = 27U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm3Trigger = 28U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm3Trigger = 29U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm3Trigger = 30U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm3Trigger = 31U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm3Trigger = 32U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm3Trigger = 33U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm3Trigger = 34U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm3Trigger = 35U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm3Trigger = 36U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm3Trigger = 37U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm3Trigger = 38U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm3Trigger = 39U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm3Trigger = 40U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm3Trigger = 41U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm3Trigger = 42U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM4 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm4Trigger = 0U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm4Trigger = 1U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm4Trigger = 2U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm4Trigger = 6U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm4Trigger = 7U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm4Trigger = 8U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm4Trigger = 9U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm4Trigger = 10U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm4Trigger = 11U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm4Trigger = 12U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm4Trigger = 13U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm4Trigger = 14U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm4Trigger = 15U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm4Trigger = 16U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm4Trigger = 18U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm4Trigger = 19U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm4Trigger = 20U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm4Trigger = 21U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm4Trigger = 22U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm4Trigger = 23U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm4Trigger = 24U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm4Trigger = 25U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm4Trigger = 26U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm4Trigger = 27U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm4Trigger = 28U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm4Trigger = 29U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm4Trigger = 30U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm4Trigger = 31U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm4Trigger = 32U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm4Trigger = 33U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm4Trigger = 34U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm4Trigger = 35U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm4Trigger = 36U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm4Trigger = 37U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm4Trigger = 38U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm4Trigger = 39U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm4Trigger = 40U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm4Trigger = 41U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm4Trigger = 42U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM5 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm5Trigger = 0U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm5Trigger = 1U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm5Trigger = 2U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm5Trigger = 6U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm5Trigger = 7U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm5Trigger = 8U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm5Trigger = 9U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm5Trigger = 10U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm5Trigger = 11U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm5Trigger = 12U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm5Trigger = 13U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm5Trigger = 14U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm5Trigger = 15U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm5Trigger = 16U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm5Trigger = 18U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm5Trigger = 19U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm5Trigger = 20U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm5Trigger = 21U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm5Trigger = 22U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm5Trigger = 23U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm5Trigger = 24U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm5Trigger = 25U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm5Trigger = 26U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm5Trigger = 27U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm5Trigger = 28U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm5Trigger = 29U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm5Trigger = 30U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm5Trigger = 31U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm5Trigger = 32U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm5Trigger = 33U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm5Trigger = 34U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm5Trigger = 35U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm5Trigger = 36U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm5Trigger = 37U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm5Trigger = 38U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm5Trigger = 39U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm5Trigger = 40U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm5Trigger = 41U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm5Trigger = 42U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM6 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm6Trigger = 0U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm6Trigger = 1U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm6Trigger = 2U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm6Trigger = 6U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm6Trigger = 7U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm6Trigger = 8U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm6Trigger = 9U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm6Trigger = 10U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm6Trigger = 11U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm6Trigger = 12U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm6Trigger = 13U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm6Trigger = 14U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm6Trigger = 15U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm6Trigger = 16U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm6Trigger = 18U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm6Trigger = 19U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm6Trigger = 20U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm6Trigger = 21U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm6Trigger = 22U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm6Trigger = 23U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm6Trigger = 24U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm6Trigger = 25U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm6Trigger = 26U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm6Trigger = 27U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm6Trigger = 28U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm6Trigger = 29U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm6Trigger = 30U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm6Trigger = 31U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm6Trigger = 32U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm6Trigger = 33U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm6Trigger = 34U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm6Trigger = 35U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm6Trigger = 36U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm6Trigger = 37U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm6Trigger = 38U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm6Trigger = 39U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm6Trigger = 40U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm6Trigger = 41U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm6Trigger = 42U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM7 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm7Trigger = 0U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm7Trigger = 1U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm7Trigger = 2U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm7Trigger = 6U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm7Trigger = 7U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm7Trigger = 8U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm7Trigger = 9U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm7Trigger = 10U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm7Trigger = 11U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm7Trigger = 12U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm7Trigger = 13U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm7Trigger = 14U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm7Trigger = 15U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm7Trigger = 16U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm7Trigger = 18U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm7Trigger = 19U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm7Trigger = 20U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm7Trigger = 21U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm7Trigger = 22U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm7Trigger = 23U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm7Trigger = 24U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm7Trigger = 25U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm7Trigger = 26U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm7Trigger = 27U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm7Trigger = 28U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm7Trigger = 29U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm7Trigger = 30U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm7Trigger = 31U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm7Trigger = 32U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm7Trigger = 33U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm7Trigger = 34U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm7Trigger = 35U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm7Trigger = 36U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm7Trigger = 37U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm7Trigger = 38U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm7Trigger = 39U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm7Trigger = 40U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm7Trigger = 41U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm7Trigger = 42U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + + /*!< FlexIO trigger input connections. */ + kINPUTMUX_PinInt4ToFlexioTrigger = 0U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 19U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig0ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig1ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig2ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig0ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig1ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig2ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig0ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig1ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig0ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig1ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig2ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 76U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma0Ch3Ena = 3U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma0Ch4Ena = 4U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma0Ch5Ena = 5U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma0Ch6Ena = 6U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0Ch7Ena = 7U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0Ch8Ena = 8U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0Ch9Ena = 9U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0Ch10Ena = 10U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0Ch11Ena = 11U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0Ch12Ena = 12U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0Ch13Ena = 13U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0Ch14Ena = 14U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0Ch15Ena = 15U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0Ch16Ena = 16U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma0Ch17Ena = 17U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma0Ch18Ena = 18U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma0Ch21Ena = 21U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma0Ch22Ena = 22U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma0Ch23Ena = 23U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestoDma0Ch24Ena = 24U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma0Ch28Ena = 28U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma0Ch29Ena = 29U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma0Ch31Ena = 31U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma0Ch32Ena = 0U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma0Ch33Ena = 1U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma0Ch34Ena = 2U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma0Ch35Ena = 3U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma0Ch36Ena = 4U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma0Ch37Ena = 5U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma0Ch38Ena = 6U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma0Ch39Ena = 7U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma0Ch40Ena = 8U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma0Ch41Ena = 9U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma0Ch42Ena = 10U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma0Ch43Ena = 11U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma0Ch44Ena = 12U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma0Ch45Ena = 13U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma0Ch46Ena = 14U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma0Ch47Ena = 15U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma0Ch48Ena = 16U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma0Ch49Ena = 17U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma0Ch50Ena = 18U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma0Ch51Ena = 19U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma0Ch52Ena = 20U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma0Ch53Ena = 21U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma0Ch54Ena = 22U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma0Ch57Ena = 25U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma0Ch58Ena = 26U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma0Ch59Ena = 27U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma0Ch60Ena = 28U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena = 29U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma0Ch62Ena = 30U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma0Ch63Ena = 31U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma0Ch64Ena = 0U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma0Ch65Ena = 1U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma0Ch66Ena = 2U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma0Ch67Ena = 3U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma0Ch68Ena = 4U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma0Ch69Ena = 5U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma0Ch70Ena = 6U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma0Ch71Ena = 7U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma0Ch72Ena = 8U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma0Ch73Ena = 9U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma0Ch74Ena = 10U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma0Ch75Ena = 11U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma0Ch76Ena = 12U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma0Ch77Ena = 13U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma0Ch78Ena = 14U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma0Ch79Ena = 15U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma0Ch80Ena = 16U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma0Ch81Ena = 17U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma0Ch82Ena = 18U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma0Ch83Ena = 19U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma0Ch84Ena = 20U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma0Ch95Ena = 31U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma0Ch96Ena = 0U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma0Ch97Ena = 1U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma0Ch98Ena = 2U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma0Ch99Ena = 3U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma0Ch100Ena = 4U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma0Ch101Ena = 5U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma0Ch102Ena = 6U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma0Ch108Ena = 12U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma0Ch109Ena = 13U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma0Ch110Ena = 14U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma0Ch111Ena = 15U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma0Ch112Ena = 16U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma0Ch113Ena = 17U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma0Ch114Ena = 18U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma0Ch115Ena = 19U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma0Ch116Ena = 20U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma0Ch117Ena = 21U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma0Ch118Ena = 22U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma0Ch119Ena = 23U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma1Ch3Ena = 3U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma1Ch4Ena = 4U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma1Ch5Ena = 5U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma1Ch6Ena = 6U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1Ch7Ena = 7U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1Ch8Ena = 8U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma1Ch9Ena = 9U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma1Ch10Ena = 10U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1Ch11Ena = 11U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma1Ch12Ena = 12U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma1Ch13Ena = 13U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma1Ch14Ena = 14U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1Ch15Ena = 15U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma1Ch16Ena = 16U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma1Ch17Ena = 17U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma1Ch18Ena = 18U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma1Ch21Ena = 21U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma1Ch22Ena = 22U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma1Ch23Ena = 23U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestToDma1Ch24Ena = 24U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma1Ch28Ena = 28U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma1Ch29Ena = 29U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma1Ch31Ena = 31U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma1Ch32Ena = 0U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma1Ch33Ena = 1U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma1Ch34Ena = 2U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma1Ch35Ena = 3U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma1Ch36Ena = 4U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma1Ch37Ena = 5U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma1Ch38Ena = 6U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma1Ch39Ena = 7U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma1Ch40Ena = 8U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma1Ch41Ena = 9U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma1Ch42Ena = 10U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma1Ch43Ena = 11U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma1Ch44Ena = 12U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma1Ch45Ena = 13U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma1Ch46Ena = 14U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma1Ch47Ena = 15U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma1Ch48Ena = 16U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma1Ch49Ena = 17U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma1Ch50Ena = 18U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma1Ch51Ena = 19U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma1Ch52Ena = 20U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma1Ch53Ena = 21U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma1Ch54Ena = 22U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma1Ch57Ena = 25U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma1Ch58Ena = 26U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma1Ch59Ena = 27U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma1Ch60Ena = 28U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma1Ch61Ena = 29U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma1Ch62Ena = 30U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma1Ch63Ena = 31U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma1Ch64Ena = 0U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma1Ch65Ena = 1U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma1Ch66Ena = 2U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma1Ch67Ena = 3U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma1Ch68Ena = 4U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma1Ch69Ena = 5U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma1Ch70Ena = 6U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma1Ch71Ena = 7U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma1Ch72Ena = 8U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma1Ch73Ena = 9U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma1Ch74Ena = 10U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma1Ch75Ena = 11U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma1Ch76Ena = 12U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma1Ch77Ena = 13U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma1Ch78Ena = 14U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma1Ch79Ena = 15U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma1Ch80Ena = 16U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma1Ch81Ena = 17U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma1Ch82Ena = 18U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma1Ch83Ena = 19U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma1Ch84Ena = 20U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch0ToDma1Ch89Ena = 25U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch1ToDma1Ch90Ena = 26U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma1Ch95Ena = 31U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma1Ch96Ena = 0U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma1Ch97Ena = 1U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma1Ch98Ena = 2U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma1Ch99Ena = 3U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma1Ch100Ena = 4U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma1Ch101Ena = 5U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma1Ch102Ena = 6U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma1Ch108Ena = 12U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma1Ch109Ena = 13U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma1Ch110Ena = 14U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma1Ch111Ena = 15U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma1Ch112Ena = 16U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma1Ch113Ena = 17U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma1Ch114Ena = 18U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma1Ch115Ena = 19U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma1Ch116Ena = 20U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma1Ch117Ena = 21U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma1Ch118Ena = 22U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma1Ch119Ena = 23U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/devices/MCXN235/drivers/fsl_reset.c b/devices/MCXN235/drivers/fsl_reset.c new file mode 100644 index 000000000..58c059950 --- /dev/null +++ b/devices/MCXN235/drivers/fsl_reset.c @@ -0,0 +1,102 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (0u == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (bitMask == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/devices/MCXN235/drivers/fsl_reset.h b/devices/MCXN235/drivers/fsl_reset.h new file mode 100644 index 000000000..59922b4fd --- /dev/null +++ b/devices/MCXN235/drivers/fsl_reset.h @@ -0,0 +1,224 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */ + kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */ + kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */ + kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */ + kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */ + kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */ + kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */ + kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */ + kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */ + kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */ + kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */ + kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */ + + kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */ + kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */ + kQDC0_RST_SHIFT_RSTn = 196608 | 4U, /**< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = 196608 | 5U, /**< QDC1 reset control */ + kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */ + kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */ + kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */ + kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */ + kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */ + kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define LP_FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define FLASH_RSTS \ + { \ + kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define TRNG_RSTS \ + { \ + kTRNG_RST_SHIFT_RSTn \ + } /* Reset bits for TRNG peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \ + } /* Reset bits for I3C peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/devices/MCXN235/fsl_device_registers.h b/devices/MCXN235/fsl_device_registers.h new file mode 100644 index 000000000..12328358c --- /dev/null +++ b/devices/MCXN235/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN235VDF) || defined(CPU_MCXN235VNL)) + +#define MCXN235_SERIES + +/* CMSIS-style register definitions */ +#include "MCXN235.h" +/* CPU specific feature definitions */ +#include "MCXN235_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCXN235/gcc/MCXN235_flash.ld b/devices/MCXN235/gcc/MCXN235_flash.ld new file mode 100644 index 000000000..a7d03085d --- /dev/null +++ b/devices/MCXN235/gcc/MCXN235_flash.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: MCXN235VDF +** MCXN235VNL +** +** Compiler: GNU C Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0007FC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MCXN235/gcc/MCXN235_ram.ld b/devices/MCXN235/gcc/MCXN235_ram.ld new file mode 100644 index 000000000..83bb15b67 --- /dev/null +++ b/devices/MCXN235/gcc/MCXN235_ram.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: MCXN235VDF +** MCXN235VNL +** +** Compiler: GNU C Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x04000400, LENGTH = 0x00007C00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MCXN235/gcc/startup_MCXN235.S b/devices/MCXN235/gcc/startup_MCXN235.S new file mode 100644 index 000000000..a48b1d7bd --- /dev/null +++ b/devices/MCXN235/gcc/startup_MCXN235.S @@ -0,0 +1,1948 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MCXN235.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* MCXN235 */ +/* @version: 1.0 */ +/* @date: 2023-10-1 */ +/* @build: b240409 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2024 NXP */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long OR_IRQHandler /* OR IRQ*/ + .long EDMA_0_CH0_IRQHandler /* eDMA_0_CH0 error or transfer complete*/ + .long EDMA_0_CH1_IRQHandler /* eDMA_0_CH1 error or transfer complete*/ + .long EDMA_0_CH2_IRQHandler /* eDMA_0_CH2 error or transfer complete*/ + .long EDMA_0_CH3_IRQHandler /* eDMA_0_CH3 error or transfer complete*/ + .long EDMA_0_CH4_IRQHandler /* eDMA_0_CH4 error or transfer complete*/ + .long EDMA_0_CH5_IRQHandler /* eDMA_0_CH5 error or transfer complete*/ + .long EDMA_0_CH6_IRQHandler /* eDMA_0_CH6 error or transfer complete*/ + .long EDMA_0_CH7_IRQHandler /* eDMA_0_CH7 error or transfer complete*/ + .long EDMA_0_CH8_IRQHandler /* eDMA_0_CH8 error or transfer complete*/ + .long EDMA_0_CH9_IRQHandler /* eDMA_0_CH9 error or transfer complete*/ + .long EDMA_0_CH10_IRQHandler /* eDMA_0_CH10 error or transfer complete*/ + .long EDMA_0_CH11_IRQHandler /* eDMA_0_CH11 error or transfer complete*/ + .long EDMA_0_CH12_IRQHandler /* eDMA_0_CH12 error or transfer complete*/ + .long EDMA_0_CH13_IRQHandler /* eDMA_0_CH13 error or transfer complete*/ + .long EDMA_0_CH14_IRQHandler /* eDMA_0_CH14 error or transfer complete*/ + .long EDMA_0_CH15_IRQHandler /* eDMA_0_CH15 error or transfer complete*/ + .long GPIO00_IRQHandler /* GPIO0 interrupt 0*/ + .long GPIO01_IRQHandler /* GPIO0 interrupt 1*/ + .long GPIO10_IRQHandler /* GPIO1 interrupt 0*/ + .long GPIO11_IRQHandler /* GPIO1 interrupt 1*/ + .long GPIO20_IRQHandler /* GPIO2 interrupt 0*/ + .long GPIO21_IRQHandler /* GPIO2 interrupt 1*/ + .long GPIO30_IRQHandler /* GPIO3 interrupt 0*/ + .long GPIO31_IRQHandler /* GPIO3 interrupt 1*/ + .long GPIO40_IRQHandler /* GPIO4 interrupt 0*/ + .long GPIO41_IRQHandler /* GPIO4 interrupt 1*/ + .long GPIO50_IRQHandler /* GPIO5 interrupt 0*/ + .long GPIO51_IRQHandler /* GPIO5 interrupt 1*/ + .long UTICK0_IRQHandler /* Micro-Tick Timer interrupt*/ + .long MRT0_IRQHandler /* Multi-Rate Timer interrupt*/ + .long CTIMER0_IRQHandler /* Standard counter/timer 0 interrupt*/ + .long CTIMER1_IRQHandler /* Standard counter/timer 1 interrupt*/ + .long Reserved49_IRQHandler /* Reserved interrupt*/ + .long CTIMER2_IRQHandler /* Standard counter/timer 2 interrupt*/ + .long LP_FLEXCOMM0_IRQHandler /* LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM1_IRQHandler /* LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM2_IRQHandler /* LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM3_IRQHandler /* LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM4_IRQHandler /* LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM5_IRQHandler /* LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM6_IRQHandler /* LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM7_IRQHandler /* LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long Reserved60_IRQHandler /* Reserved interrupt*/ + .long ADC0_IRQHandler /* Analog-to-Digital Converter 0 - General Purpose interrupt*/ + .long ADC1_IRQHandler /* Analog-to-Digital Converter 1 - General Purpose interrupt*/ + .long PINT0_IRQHandler /* Pin Interrupt Pattern Match Interrupt*/ + .long PDM_EVENT_IRQHandler /* Microphone Interface interrupt */ + .long Reserved65_IRQHandler /* Reserved interrupt*/ + .long Reserved66_IRQHandler /* Reserved interrupt*/ + .long USB0_DCD_IRQHandler /* Universal Serial Bus - Device Charge Detect interrupt*/ + .long RTC_IRQHandler /* RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt)*/ + .long SMARTDMA_IRQHandler /* SmartDMA_IRQ*/ + .long Reserved70_IRQHandler /* Reserved interrupt*/ + .long CTIMER3_IRQHandler /* Standard counter/timer 3 interrupt*/ + .long CTIMER4_IRQHandler /* Standard counter/timer 4 interrupt*/ + .long OS_EVENT_IRQHandler /* OS event timer interrupt*/ + .long Reserved74_IRQHandler /* Reserved interrupt*/ + .long SAI0_IRQHandler /* Serial Audio Interface 0 interrupt*/ + .long SAI1_IRQHandler /* Serial Audio Interface 1 interrupt*/ + .long Reserved77_IRQHandler /* Reserved interrupt*/ + .long CAN0_IRQHandler /* Controller Area Network 0 interrupt*/ + .long Reserved79_IRQHandler /* Reserved interrupt*/ + .long Reserved80_IRQHandler /* Reserved interrupt*/ + .long Reserved81_IRQHandler /* Reserved interrupt*/ + .long USB1_HS_PHY_IRQHandler /* USBHS DCD or USBHS Phy interrupt*/ + .long USB1_HS_IRQHandler /* USB High Speed OTG Controller interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* AHB Secure Controller hypervisor call interrupt*/ + .long Reserved85_IRQHandler /* Reserved interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Freqme_IRQHandler /* Frequency Measurement interrupt*/ + .long SEC_VIO_IRQHandler /* Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt)*/ + .long ELS_IRQHandler /* ELS interrupt*/ + .long PKC_IRQHandler /* PKC interrupt*/ + .long PUF_IRQHandler /* Physical Unclonable Function interrupt*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long EDMA_1_CH0_IRQHandler /* eDMA_1_CH0 error or transfer complete*/ + .long EDMA_1_CH1_IRQHandler /* eDMA_1_CH1 error or transfer complete*/ + .long EDMA_1_CH2_IRQHandler /* eDMA_1_CH2 error or transfer complete*/ + .long EDMA_1_CH3_IRQHandler /* eDMA_1_CH3 error or transfer complete*/ + .long EDMA_1_CH4_IRQHandler /* eDMA_1_CH4 error or transfer complete*/ + .long EDMA_1_CH5_IRQHandler /* eDMA_1_CH5 error or transfer complete*/ + .long EDMA_1_CH6_IRQHandler /* eDMA_1_CH6 error or transfer complete*/ + .long EDMA_1_CH7_IRQHandler /* eDMA_1_CH7 error or transfer complete*/ + .long Reserved101_IRQHandler /* Reserved interrupt*/ + .long Reserved102_IRQHandler /* Reserved interrupt*/ + .long Reserved103_IRQHandler /* Reserved interrupt*/ + .long Reserved104_IRQHandler /* Reserved interrupt*/ + .long Reserved105_IRQHandler /* Reserved interrupt*/ + .long Reserved106_IRQHandler /* Reserved interrupt*/ + .long Reserved107_IRQHandler /* Reserved interrupt*/ + .long Reserved108_IRQHandler /* Reserved interrupt*/ + .long CDOG0_IRQHandler /* Code Watchdog Timer 0 interrupt*/ + .long CDOG1_IRQHandler /* Code Watchdog Timer 1 interrupt*/ + .long I3C0_IRQHandler /* Improved Inter Integrated Circuit interrupt 0*/ + .long I3C1_IRQHandler /* Improved Inter Integrated Circuit interrupt 1*/ + .long Reserved113_IRQHandler /* Reserved interrupt*/ + .long GDET_IRQHandler /* Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt*/ + .long VBAT0_IRQHandler /* VBAT interrupt( VBAT interrupt or digital tamper interrupt)*/ + .long EWM0_IRQHandler /* External Watchdog Monitor interrupt*/ + .long Reserved117_IRQHandler /* Reserved interrupt*/ + .long Reserved118_IRQHandler /* Reserved interrupt*/ + .long Reserved119_IRQHandler /* Reserved interrupt*/ + .long Reserved120_IRQHandler /* Reserved interrupt*/ + .long FLEXIO_IRQHandler /* Flexible Input/Output interrupt*/ + .long Reserved122_IRQHandler /* Reserved interrupt*/ + .long Reserved123_IRQHandler /* Reserved interrupt*/ + .long Reserved124_IRQHandler /* Reserved interrupt*/ + .long HSCMP0_IRQHandler /* High-Speed comparator0 interrupt*/ + .long HSCMP1_IRQHandler /* High-Speed comparator1 interrupt*/ + .long Reserved127_IRQHandler /* Reserved interrupt*/ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* FlexPWM0_reload_error interrupt*/ + .long FLEXPWM0_FAULT_IRQHandler /* FlexPWM0_fault interrupt*/ + .long FLEXPWM0_SUBMODULE0_IRQHandler /* FlexPWM0 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE1_IRQHandler /* FlexPWM0 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE2_IRQHandler /* FlexPWM0 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE3_IRQHandler /* FlexPWM0 Submodule 3 capture/compare/reload interrupt*/ + .long Reserved134_IRQHandler /* Reserved interrupt*/ + .long Reserved135_IRQHandler /* Reserved interrupt*/ + .long Reserved136_IRQHandler /* Reserved interrupt*/ + .long Reserved137_IRQHandler /* Reserved interrupt*/ + .long Reserved138_IRQHandler /* Reserved interrupt*/ + .long Reserved139_IRQHandler /* Reserved interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ + .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ + .long Reserved149_IRQHandler /* Reserved interrupt*/ + .long ELS_ERR_IRQHandler /* ELS error interrupt*/ + .long PKC_ERR_IRQHandler /* PKC error interrupt*/ + .long ERM_SINGLE_BIT_ERROR_IRQHandler /* ERM Single Bit error interrupt*/ + .long ERM_MULTI_BIT_ERROR_IRQHandler /* ERM Multi Bit error interrupt*/ + .long FMU0_IRQHandler /* Flash Management Unit interrupt*/ + .long Reserved155_IRQHandler /* Reserved interrupt*/ + .long Reserved156_IRQHandler /* Reserved interrupt*/ + .long Reserved157_IRQHandler /* Reserved interrupt*/ + .long Reserved158_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* Low Power Timer 0 interrupt*/ + .long LPTMR1_IRQHandler /* Low Power Timer 1 interrupt*/ + .long SCG_IRQHandler /* System Clock Generator interrupt*/ + .long SPC_IRQHandler /* System Power Controller interrupt*/ + .long WUU_IRQHandler /* Wake Up Unit interrupt*/ + .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ + .long Reserved165_IRQHandler /* Reserved interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ + .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ + .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ + .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + + .size __Vectors, . - __Vectors + + .text + .thumb + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 + +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ +#ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else +#define __START _start +#endif +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak OR_IRQHandler + .type OR_IRQHandler, %function +OR_IRQHandler: + ldr r0,=OR_DriverIRQHandler + bx r0 + .size OR_IRQHandler, . - OR_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH0_IRQHandler + .type EDMA_0_CH0_IRQHandler, %function +EDMA_0_CH0_IRQHandler: + ldr r0,=EDMA_0_CH0_DriverIRQHandler + bx r0 + .size EDMA_0_CH0_IRQHandler, . - EDMA_0_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH1_IRQHandler + .type EDMA_0_CH1_IRQHandler, %function +EDMA_0_CH1_IRQHandler: + ldr r0,=EDMA_0_CH1_DriverIRQHandler + bx r0 + .size EDMA_0_CH1_IRQHandler, . - EDMA_0_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH2_IRQHandler + .type EDMA_0_CH2_IRQHandler, %function +EDMA_0_CH2_IRQHandler: + ldr r0,=EDMA_0_CH2_DriverIRQHandler + bx r0 + .size EDMA_0_CH2_IRQHandler, . - EDMA_0_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH3_IRQHandler + .type EDMA_0_CH3_IRQHandler, %function +EDMA_0_CH3_IRQHandler: + ldr r0,=EDMA_0_CH3_DriverIRQHandler + bx r0 + .size EDMA_0_CH3_IRQHandler, . - EDMA_0_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH4_IRQHandler + .type EDMA_0_CH4_IRQHandler, %function +EDMA_0_CH4_IRQHandler: + ldr r0,=EDMA_0_CH4_DriverIRQHandler + bx r0 + .size EDMA_0_CH4_IRQHandler, . - EDMA_0_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH5_IRQHandler + .type EDMA_0_CH5_IRQHandler, %function +EDMA_0_CH5_IRQHandler: + ldr r0,=EDMA_0_CH5_DriverIRQHandler + bx r0 + .size EDMA_0_CH5_IRQHandler, . - EDMA_0_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH6_IRQHandler + .type EDMA_0_CH6_IRQHandler, %function +EDMA_0_CH6_IRQHandler: + ldr r0,=EDMA_0_CH6_DriverIRQHandler + bx r0 + .size EDMA_0_CH6_IRQHandler, . - EDMA_0_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH7_IRQHandler + .type EDMA_0_CH7_IRQHandler, %function +EDMA_0_CH7_IRQHandler: + ldr r0,=EDMA_0_CH7_DriverIRQHandler + bx r0 + .size EDMA_0_CH7_IRQHandler, . - EDMA_0_CH7_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH8_IRQHandler + .type EDMA_0_CH8_IRQHandler, %function +EDMA_0_CH8_IRQHandler: + ldr r0,=EDMA_0_CH8_DriverIRQHandler + bx r0 + .size EDMA_0_CH8_IRQHandler, . - EDMA_0_CH8_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH9_IRQHandler + .type EDMA_0_CH9_IRQHandler, %function +EDMA_0_CH9_IRQHandler: + ldr r0,=EDMA_0_CH9_DriverIRQHandler + bx r0 + .size EDMA_0_CH9_IRQHandler, . - EDMA_0_CH9_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH10_IRQHandler + .type EDMA_0_CH10_IRQHandler, %function +EDMA_0_CH10_IRQHandler: + ldr r0,=EDMA_0_CH10_DriverIRQHandler + bx r0 + .size EDMA_0_CH10_IRQHandler, . - EDMA_0_CH10_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH11_IRQHandler + .type EDMA_0_CH11_IRQHandler, %function +EDMA_0_CH11_IRQHandler: + ldr r0,=EDMA_0_CH11_DriverIRQHandler + bx r0 + .size EDMA_0_CH11_IRQHandler, . - EDMA_0_CH11_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH12_IRQHandler + .type EDMA_0_CH12_IRQHandler, %function +EDMA_0_CH12_IRQHandler: + ldr r0,=EDMA_0_CH12_DriverIRQHandler + bx r0 + .size EDMA_0_CH12_IRQHandler, . - EDMA_0_CH12_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH13_IRQHandler + .type EDMA_0_CH13_IRQHandler, %function +EDMA_0_CH13_IRQHandler: + ldr r0,=EDMA_0_CH13_DriverIRQHandler + bx r0 + .size EDMA_0_CH13_IRQHandler, . - EDMA_0_CH13_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH14_IRQHandler + .type EDMA_0_CH14_IRQHandler, %function +EDMA_0_CH14_IRQHandler: + ldr r0,=EDMA_0_CH14_DriverIRQHandler + bx r0 + .size EDMA_0_CH14_IRQHandler, . - EDMA_0_CH14_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH15_IRQHandler + .type EDMA_0_CH15_IRQHandler, %function +EDMA_0_CH15_IRQHandler: + ldr r0,=EDMA_0_CH15_DriverIRQHandler + bx r0 + .size EDMA_0_CH15_IRQHandler, . - EDMA_0_CH15_IRQHandler + + .align 1 + .thumb_func + .weak GPIO00_IRQHandler + .type GPIO00_IRQHandler, %function +GPIO00_IRQHandler: + ldr r0,=GPIO00_DriverIRQHandler + bx r0 + .size GPIO00_IRQHandler, . - GPIO00_IRQHandler + + .align 1 + .thumb_func + .weak GPIO01_IRQHandler + .type GPIO01_IRQHandler, %function +GPIO01_IRQHandler: + ldr r0,=GPIO01_DriverIRQHandler + bx r0 + .size GPIO01_IRQHandler, . - GPIO01_IRQHandler + + .align 1 + .thumb_func + .weak GPIO10_IRQHandler + .type GPIO10_IRQHandler, %function +GPIO10_IRQHandler: + ldr r0,=GPIO10_DriverIRQHandler + bx r0 + .size GPIO10_IRQHandler, . - GPIO10_IRQHandler + + .align 1 + .thumb_func + .weak GPIO11_IRQHandler + .type GPIO11_IRQHandler, %function +GPIO11_IRQHandler: + ldr r0,=GPIO11_DriverIRQHandler + bx r0 + .size GPIO11_IRQHandler, . - GPIO11_IRQHandler + + .align 1 + .thumb_func + .weak GPIO20_IRQHandler + .type GPIO20_IRQHandler, %function +GPIO20_IRQHandler: + ldr r0,=GPIO20_DriverIRQHandler + bx r0 + .size GPIO20_IRQHandler, . - GPIO20_IRQHandler + + .align 1 + .thumb_func + .weak GPIO21_IRQHandler + .type GPIO21_IRQHandler, %function +GPIO21_IRQHandler: + ldr r0,=GPIO21_DriverIRQHandler + bx r0 + .size GPIO21_IRQHandler, . - GPIO21_IRQHandler + + .align 1 + .thumb_func + .weak GPIO30_IRQHandler + .type GPIO30_IRQHandler, %function +GPIO30_IRQHandler: + ldr r0,=GPIO30_DriverIRQHandler + bx r0 + .size GPIO30_IRQHandler, . - GPIO30_IRQHandler + + .align 1 + .thumb_func + .weak GPIO31_IRQHandler + .type GPIO31_IRQHandler, %function +GPIO31_IRQHandler: + ldr r0,=GPIO31_DriverIRQHandler + bx r0 + .size GPIO31_IRQHandler, . - GPIO31_IRQHandler + + .align 1 + .thumb_func + .weak GPIO40_IRQHandler + .type GPIO40_IRQHandler, %function +GPIO40_IRQHandler: + ldr r0,=GPIO40_DriverIRQHandler + bx r0 + .size GPIO40_IRQHandler, . - GPIO40_IRQHandler + + .align 1 + .thumb_func + .weak GPIO41_IRQHandler + .type GPIO41_IRQHandler, %function +GPIO41_IRQHandler: + ldr r0,=GPIO41_DriverIRQHandler + bx r0 + .size GPIO41_IRQHandler, . - GPIO41_IRQHandler + + .align 1 + .thumb_func + .weak GPIO50_IRQHandler + .type GPIO50_IRQHandler, %function +GPIO50_IRQHandler: + ldr r0,=GPIO50_DriverIRQHandler + bx r0 + .size GPIO50_IRQHandler, . - GPIO50_IRQHandler + + .align 1 + .thumb_func + .weak GPIO51_IRQHandler + .type GPIO51_IRQHandler, %function +GPIO51_IRQHandler: + ldr r0,=GPIO51_DriverIRQHandler + bx r0 + .size GPIO51_IRQHandler, . - GPIO51_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved49_IRQHandler + .type Reserved49_IRQHandler, %function +Reserved49_IRQHandler: + ldr r0,=Reserved49_DriverIRQHandler + bx r0 + .size Reserved49_IRQHandler, . - Reserved49_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM0_IRQHandler + .type LP_FLEXCOMM0_IRQHandler, %function +LP_FLEXCOMM0_IRQHandler: + ldr r0,=LP_FLEXCOMM0_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM0_IRQHandler, . - LP_FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM1_IRQHandler + .type LP_FLEXCOMM1_IRQHandler, %function +LP_FLEXCOMM1_IRQHandler: + ldr r0,=LP_FLEXCOMM1_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM1_IRQHandler, . - LP_FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM2_IRQHandler + .type LP_FLEXCOMM2_IRQHandler, %function +LP_FLEXCOMM2_IRQHandler: + ldr r0,=LP_FLEXCOMM2_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM2_IRQHandler, . - LP_FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM3_IRQHandler + .type LP_FLEXCOMM3_IRQHandler, %function +LP_FLEXCOMM3_IRQHandler: + ldr r0,=LP_FLEXCOMM3_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM3_IRQHandler, . - LP_FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM4_IRQHandler + .type LP_FLEXCOMM4_IRQHandler, %function +LP_FLEXCOMM4_IRQHandler: + ldr r0,=LP_FLEXCOMM4_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM4_IRQHandler, . - LP_FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM5_IRQHandler + .type LP_FLEXCOMM5_IRQHandler, %function +LP_FLEXCOMM5_IRQHandler: + ldr r0,=LP_FLEXCOMM5_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM5_IRQHandler, . - LP_FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM6_IRQHandler + .type LP_FLEXCOMM6_IRQHandler, %function +LP_FLEXCOMM6_IRQHandler: + ldr r0,=LP_FLEXCOMM6_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM6_IRQHandler, . - LP_FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM7_IRQHandler + .type LP_FLEXCOMM7_IRQHandler, %function +LP_FLEXCOMM7_IRQHandler: + ldr r0,=LP_FLEXCOMM7_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM7_IRQHandler, . - LP_FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak PINT0_IRQHandler + .type PINT0_IRQHandler, %function +PINT0_IRQHandler: + ldr r0,=PINT0_DriverIRQHandler + bx r0 + .size PINT0_IRQHandler, . - PINT0_IRQHandler + + .align 1 + .thumb_func + .weak PDM_EVENT_IRQHandler + .type PDM_EVENT_IRQHandler, %function +PDM_EVENT_IRQHandler: + ldr r0,=PDM_EVENT_DriverIRQHandler + bx r0 + .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved65_IRQHandler + .type Reserved65_IRQHandler, %function +Reserved65_IRQHandler: + ldr r0,=Reserved65_DriverIRQHandler + bx r0 + .size Reserved65_IRQHandler, . - Reserved65_IRQHandler + + .align 1 + .thumb_func + .weak Reserved66_IRQHandler + .type Reserved66_IRQHandler, %function +Reserved66_IRQHandler: + ldr r0,=Reserved66_DriverIRQHandler + bx r0 + .size Reserved66_IRQHandler, . - Reserved66_IRQHandler + + .align 1 + .thumb_func + .weak USB0_DCD_IRQHandler + .type USB0_DCD_IRQHandler, %function +USB0_DCD_IRQHandler: + ldr r0,=USB0_DCD_DriverIRQHandler + bx r0 + .size USB0_DCD_IRQHandler, . - USB0_DCD_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak SMARTDMA_IRQHandler + .type SMARTDMA_IRQHandler, %function +SMARTDMA_IRQHandler: + ldr r0,=SMARTDMA_DriverIRQHandler + bx r0 + .size SMARTDMA_IRQHandler, . - SMARTDMA_IRQHandler + + .align 1 + .thumb_func + .weak Reserved70_IRQHandler + .type Reserved70_IRQHandler, %function +Reserved70_IRQHandler: + ldr r0,=Reserved70_DriverIRQHandler + bx r0 + .size Reserved70_IRQHandler, . - Reserved70_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved74_IRQHandler + .type Reserved74_IRQHandler, %function +Reserved74_IRQHandler: + ldr r0,=Reserved74_DriverIRQHandler + bx r0 + .size Reserved74_IRQHandler, . - Reserved74_IRQHandler + + .align 1 + .thumb_func + .weak SAI0_IRQHandler + .type SAI0_IRQHandler, %function +SAI0_IRQHandler: + ldr r0,=SAI0_DriverIRQHandler + bx r0 + .size SAI0_IRQHandler, . - SAI0_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQHandler + .type CAN0_IRQHandler, %function +CAN0_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_IRQHandler, . - CAN0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved79_IRQHandler + .type Reserved79_IRQHandler, %function +Reserved79_IRQHandler: + ldr r0,=Reserved79_DriverIRQHandler + bx r0 + .size Reserved79_IRQHandler, . - Reserved79_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak Reserved81_IRQHandler + .type Reserved81_IRQHandler, %function +Reserved81_IRQHandler: + ldr r0,=Reserved81_DriverIRQHandler + bx r0 + .size Reserved81_IRQHandler, . - Reserved81_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_PHY_IRQHandler + .type USB1_HS_PHY_IRQHandler, %function +USB1_HS_PHY_IRQHandler: + ldr r0,=USB1_HS_PHY_DriverIRQHandler + bx r0 + .size USB1_HS_PHY_IRQHandler, . - USB1_HS_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_IRQHandler + .type USB1_HS_IRQHandler, %function +USB1_HS_IRQHandler: + ldr r0,=USB1_HS_DriverIRQHandler + bx r0 + .size USB1_HS_IRQHandler, . - USB1_HS_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak ELS_IRQHandler + .type ELS_IRQHandler, %function +ELS_IRQHandler: + ldr r0,=ELS_DriverIRQHandler + bx r0 + .size ELS_IRQHandler, . - ELS_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved92_IRQHandler + .type Reserved92_IRQHandler, %function +Reserved92_IRQHandler: + ldr r0,=Reserved92_DriverIRQHandler + bx r0 + .size Reserved92_IRQHandler, . - Reserved92_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH0_IRQHandler + .type EDMA_1_CH0_IRQHandler, %function +EDMA_1_CH0_IRQHandler: + ldr r0,=EDMA_1_CH0_DriverIRQHandler + bx r0 + .size EDMA_1_CH0_IRQHandler, . - EDMA_1_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH1_IRQHandler + .type EDMA_1_CH1_IRQHandler, %function +EDMA_1_CH1_IRQHandler: + ldr r0,=EDMA_1_CH1_DriverIRQHandler + bx r0 + .size EDMA_1_CH1_IRQHandler, . - EDMA_1_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH2_IRQHandler + .type EDMA_1_CH2_IRQHandler, %function +EDMA_1_CH2_IRQHandler: + ldr r0,=EDMA_1_CH2_DriverIRQHandler + bx r0 + .size EDMA_1_CH2_IRQHandler, . - EDMA_1_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH3_IRQHandler + .type EDMA_1_CH3_IRQHandler, %function +EDMA_1_CH3_IRQHandler: + ldr r0,=EDMA_1_CH3_DriverIRQHandler + bx r0 + .size EDMA_1_CH3_IRQHandler, . - EDMA_1_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH4_IRQHandler + .type EDMA_1_CH4_IRQHandler, %function +EDMA_1_CH4_IRQHandler: + ldr r0,=EDMA_1_CH4_DriverIRQHandler + bx r0 + .size EDMA_1_CH4_IRQHandler, . - EDMA_1_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH5_IRQHandler + .type EDMA_1_CH5_IRQHandler, %function +EDMA_1_CH5_IRQHandler: + ldr r0,=EDMA_1_CH5_DriverIRQHandler + bx r0 + .size EDMA_1_CH5_IRQHandler, . - EDMA_1_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH6_IRQHandler + .type EDMA_1_CH6_IRQHandler, %function +EDMA_1_CH6_IRQHandler: + ldr r0,=EDMA_1_CH6_DriverIRQHandler + bx r0 + .size EDMA_1_CH6_IRQHandler, . - EDMA_1_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH7_IRQHandler + .type EDMA_1_CH7_IRQHandler, %function +EDMA_1_CH7_IRQHandler: + ldr r0,=EDMA_1_CH7_DriverIRQHandler + bx r0 + .size EDMA_1_CH7_IRQHandler, . - EDMA_1_CH7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved101_IRQHandler + .type Reserved101_IRQHandler, %function +Reserved101_IRQHandler: + ldr r0,=Reserved101_DriverIRQHandler + bx r0 + .size Reserved101_IRQHandler, . - Reserved101_IRQHandler + + .align 1 + .thumb_func + .weak Reserved102_IRQHandler + .type Reserved102_IRQHandler, %function +Reserved102_IRQHandler: + ldr r0,=Reserved102_DriverIRQHandler + bx r0 + .size Reserved102_IRQHandler, . - Reserved102_IRQHandler + + .align 1 + .thumb_func + .weak Reserved103_IRQHandler + .type Reserved103_IRQHandler, %function +Reserved103_IRQHandler: + ldr r0,=Reserved103_DriverIRQHandler + bx r0 + .size Reserved103_IRQHandler, . - Reserved103_IRQHandler + + .align 1 + .thumb_func + .weak Reserved104_IRQHandler + .type Reserved104_IRQHandler, %function +Reserved104_IRQHandler: + ldr r0,=Reserved104_DriverIRQHandler + bx r0 + .size Reserved104_IRQHandler, . - Reserved104_IRQHandler + + .align 1 + .thumb_func + .weak Reserved105_IRQHandler + .type Reserved105_IRQHandler, %function +Reserved105_IRQHandler: + ldr r0,=Reserved105_DriverIRQHandler + bx r0 + .size Reserved105_IRQHandler, . - Reserved105_IRQHandler + + .align 1 + .thumb_func + .weak Reserved106_IRQHandler + .type Reserved106_IRQHandler, %function +Reserved106_IRQHandler: + ldr r0,=Reserved106_DriverIRQHandler + bx r0 + .size Reserved106_IRQHandler, . - Reserved106_IRQHandler + + .align 1 + .thumb_func + .weak Reserved107_IRQHandler + .type Reserved107_IRQHandler, %function +Reserved107_IRQHandler: + ldr r0,=Reserved107_DriverIRQHandler + bx r0 + .size Reserved107_IRQHandler, . - Reserved107_IRQHandler + + .align 1 + .thumb_func + .weak Reserved108_IRQHandler + .type Reserved108_IRQHandler, %function +Reserved108_IRQHandler: + ldr r0,=Reserved108_DriverIRQHandler + bx r0 + .size Reserved108_IRQHandler, . - Reserved108_IRQHandler + + .align 1 + .thumb_func + .weak CDOG0_IRQHandler + .type CDOG0_IRQHandler, %function +CDOG0_IRQHandler: + ldr r0,=CDOG0_DriverIRQHandler + bx r0 + .size CDOG0_IRQHandler, . - CDOG0_IRQHandler + + .align 1 + .thumb_func + .weak CDOG1_IRQHandler + .type CDOG1_IRQHandler, %function +CDOG1_IRQHandler: + ldr r0,=CDOG1_DriverIRQHandler + bx r0 + .size CDOG1_IRQHandler, . - CDOG1_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak I3C1_IRQHandler + .type I3C1_IRQHandler, %function +I3C1_IRQHandler: + ldr r0,=I3C1_DriverIRQHandler + bx r0 + .size I3C1_IRQHandler, . - I3C1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved113_IRQHandler + .type Reserved113_IRQHandler, %function +Reserved113_IRQHandler: + ldr r0,=Reserved113_DriverIRQHandler + bx r0 + .size Reserved113_IRQHandler, . - Reserved113_IRQHandler + + .align 1 + .thumb_func + .weak GDET_IRQHandler + .type GDET_IRQHandler, %function +GDET_IRQHandler: + ldr r0,=GDET_DriverIRQHandler + bx r0 + .size GDET_IRQHandler, . - GDET_IRQHandler + + .align 1 + .thumb_func + .weak VBAT0_IRQHandler + .type VBAT0_IRQHandler, %function +VBAT0_IRQHandler: + ldr r0,=VBAT0_DriverIRQHandler + bx r0 + .size VBAT0_IRQHandler, . - VBAT0_IRQHandler + + .align 1 + .thumb_func + .weak EWM0_IRQHandler + .type EWM0_IRQHandler, %function +EWM0_IRQHandler: + ldr r0,=EWM0_DriverIRQHandler + bx r0 + .size EWM0_IRQHandler, . - EWM0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved117_IRQHandler + .type Reserved117_IRQHandler, %function +Reserved117_IRQHandler: + ldr r0,=Reserved117_DriverIRQHandler + bx r0 + .size Reserved117_IRQHandler, . - Reserved117_IRQHandler + + .align 1 + .thumb_func + .weak Reserved118_IRQHandler + .type Reserved118_IRQHandler, %function +Reserved118_IRQHandler: + ldr r0,=Reserved118_DriverIRQHandler + bx r0 + .size Reserved118_IRQHandler, . - Reserved118_IRQHandler + + .align 1 + .thumb_func + .weak Reserved119_IRQHandler + .type Reserved119_IRQHandler, %function +Reserved119_IRQHandler: + ldr r0,=Reserved119_DriverIRQHandler + bx r0 + .size Reserved119_IRQHandler, . - Reserved119_IRQHandler + + .align 1 + .thumb_func + .weak Reserved120_IRQHandler + .type Reserved120_IRQHandler, %function +Reserved120_IRQHandler: + ldr r0,=Reserved120_DriverIRQHandler + bx r0 + .size Reserved120_IRQHandler, . - Reserved120_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO_IRQHandler + .type FLEXIO_IRQHandler, %function +FLEXIO_IRQHandler: + ldr r0,=FLEXIO_DriverIRQHandler + bx r0 + .size FLEXIO_IRQHandler, . - FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved122_IRQHandler + .type Reserved122_IRQHandler, %function +Reserved122_IRQHandler: + ldr r0,=Reserved122_DriverIRQHandler + bx r0 + .size Reserved122_IRQHandler, . - Reserved122_IRQHandler + + .align 1 + .thumb_func + .weak Reserved123_IRQHandler + .type Reserved123_IRQHandler, %function +Reserved123_IRQHandler: + ldr r0,=Reserved123_DriverIRQHandler + bx r0 + .size Reserved123_IRQHandler, . - Reserved123_IRQHandler + + .align 1 + .thumb_func + .weak Reserved124_IRQHandler + .type Reserved124_IRQHandler, %function +Reserved124_IRQHandler: + ldr r0,=Reserved124_DriverIRQHandler + bx r0 + .size Reserved124_IRQHandler, . - Reserved124_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE0_IRQHandler + .type FLEXPWM0_SUBMODULE0_IRQHandler, %function +FLEXPWM0_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE0_IRQHandler, . - FLEXPWM0_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE1_IRQHandler + .type FLEXPWM0_SUBMODULE1_IRQHandler, %function +FLEXPWM0_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE1_IRQHandler, . - FLEXPWM0_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE2_IRQHandler + .type FLEXPWM0_SUBMODULE2_IRQHandler, %function +FLEXPWM0_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE2_IRQHandler, . - FLEXPWM0_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE3_IRQHandler + .type FLEXPWM0_SUBMODULE3_IRQHandler, %function +FLEXPWM0_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE3_IRQHandler, . - FLEXPWM0_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak Reserved134_IRQHandler + .type Reserved134_IRQHandler, %function +Reserved134_IRQHandler: + ldr r0,=Reserved134_DriverIRQHandler + bx r0 + .size Reserved134_IRQHandler, . - Reserved134_IRQHandler + + .align 1 + .thumb_func + .weak Reserved135_IRQHandler + .type Reserved135_IRQHandler, %function +Reserved135_IRQHandler: + ldr r0,=Reserved135_DriverIRQHandler + bx r0 + .size Reserved135_IRQHandler, . - Reserved135_IRQHandler + + .align 1 + .thumb_func + .weak Reserved136_IRQHandler + .type Reserved136_IRQHandler, %function +Reserved136_IRQHandler: + ldr r0,=Reserved136_DriverIRQHandler + bx r0 + .size Reserved136_IRQHandler, . - Reserved136_IRQHandler + + .align 1 + .thumb_func + .weak Reserved137_IRQHandler + .type Reserved137_IRQHandler, %function +Reserved137_IRQHandler: + ldr r0,=Reserved137_DriverIRQHandler + bx r0 + .size Reserved137_IRQHandler, . - Reserved137_IRQHandler + + .align 1 + .thumb_func + .weak Reserved138_IRQHandler + .type Reserved138_IRQHandler, %function +Reserved138_IRQHandler: + ldr r0,=Reserved138_DriverIRQHandler + bx r0 + .size Reserved138_IRQHandler, . - Reserved138_IRQHandler + + .align 1 + .thumb_func + .weak Reserved139_IRQHandler + .type Reserved139_IRQHandler, %function +Reserved139_IRQHandler: + ldr r0,=Reserved139_DriverIRQHandler + bx r0 + .size Reserved139_IRQHandler, . - Reserved139_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler + bx r0 + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler + bx r0 + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler + bx r0 + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler + bx r0 + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler + bx r0 + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler + bx r0 + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved149_IRQHandler + .type Reserved149_IRQHandler, %function +Reserved149_IRQHandler: + ldr r0,=Reserved149_DriverIRQHandler + bx r0 + .size Reserved149_IRQHandler, . - Reserved149_IRQHandler + + .align 1 + .thumb_func + .weak ELS_ERR_IRQHandler + .type ELS_ERR_IRQHandler, %function +ELS_ERR_IRQHandler: + ldr r0,=ELS_ERR_DriverIRQHandler + bx r0 + .size ELS_ERR_IRQHandler, . - ELS_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_SINGLE_BIT_ERROR_IRQHandler + .type ERM_SINGLE_BIT_ERROR_IRQHandler, %function +ERM_SINGLE_BIT_ERROR_IRQHandler: + ldr r0,=ERM_SINGLE_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_SINGLE_BIT_ERROR_IRQHandler, . - ERM_SINGLE_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_MULTI_BIT_ERROR_IRQHandler + .type ERM_MULTI_BIT_ERROR_IRQHandler, %function +ERM_MULTI_BIT_ERROR_IRQHandler: + ldr r0,=ERM_MULTI_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_MULTI_BIT_ERROR_IRQHandler, . - ERM_MULTI_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FMU0_IRQHandler + .type FMU0_IRQHandler, %function +FMU0_IRQHandler: + ldr r0,=FMU0_DriverIRQHandler + bx r0 + .size FMU0_IRQHandler, . - FMU0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved155_IRQHandler + .type Reserved155_IRQHandler, %function +Reserved155_IRQHandler: + ldr r0,=Reserved155_DriverIRQHandler + bx r0 + .size Reserved155_IRQHandler, . - Reserved155_IRQHandler + + .align 1 + .thumb_func + .weak Reserved156_IRQHandler + .type Reserved156_IRQHandler, %function +Reserved156_IRQHandler: + ldr r0,=Reserved156_DriverIRQHandler + bx r0 + .size Reserved156_IRQHandler, . - Reserved156_IRQHandler + + .align 1 + .thumb_func + .weak Reserved157_IRQHandler + .type Reserved157_IRQHandler, %function +Reserved157_IRQHandler: + ldr r0,=Reserved157_DriverIRQHandler + bx r0 + .size Reserved157_IRQHandler, . - Reserved157_IRQHandler + + .align 1 + .thumb_func + .weak Reserved158_IRQHandler + .type Reserved158_IRQHandler, %function +Reserved158_IRQHandler: + ldr r0,=Reserved158_DriverIRQHandler + bx r0 + .size Reserved158_IRQHandler, . - Reserved158_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR0_IRQHandler + .type LPTMR0_IRQHandler, %function +LPTMR0_IRQHandler: + ldr r0,=LPTMR0_DriverIRQHandler + bx r0 + .size LPTMR0_IRQHandler, . - LPTMR0_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR1_IRQHandler + .type LPTMR1_IRQHandler, %function +LPTMR1_IRQHandler: + ldr r0,=LPTMR1_DriverIRQHandler + bx r0 + .size LPTMR1_IRQHandler, . - LPTMR1_IRQHandler + + .align 1 + .thumb_func + .weak SCG_IRQHandler + .type SCG_IRQHandler, %function +SCG_IRQHandler: + ldr r0,=SCG_DriverIRQHandler + bx r0 + .size SCG_IRQHandler, . - SCG_IRQHandler + + .align 1 + .thumb_func + .weak SPC_IRQHandler + .type SPC_IRQHandler, %function +SPC_IRQHandler: + ldr r0,=SPC_DriverIRQHandler + bx r0 + .size SPC_IRQHandler, . - SPC_IRQHandler + + .align 1 + .thumb_func + .weak WUU_IRQHandler + .type WUU_IRQHandler, %function +WUU_IRQHandler: + ldr r0,=WUU_DriverIRQHandler + bx r0 + .size WUU_IRQHandler, . - WUU_IRQHandler + + .align 1 + .thumb_func + .weak PORT_EFT_IRQHandler + .type PORT_EFT_IRQHandler, %function +PORT_EFT_IRQHandler: + ldr r0,=PORT_EFT_DriverIRQHandler + bx r0 + .size PORT_EFT_IRQHandler, . - PORT_EFT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved165_IRQHandler + .type Reserved165_IRQHandler, %function +Reserved165_IRQHandler: + ldr r0,=Reserved165_DriverIRQHandler + bx r0 + .size Reserved165_IRQHandler, . - Reserved165_IRQHandler + + .align 1 + .thumb_func + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler + bx r0 + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler + + .align 1 + .thumb_func + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler + bx r0 + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler + + .align 1 + .thumb_func + .weak WWDT0_IRQHandler + .type WWDT0_IRQHandler, %function +WWDT0_IRQHandler: + ldr r0,=WWDT0_DriverIRQHandler + bx r0 + .size WWDT0_IRQHandler, . - WWDT0_IRQHandler + + .align 1 + .thumb_func + .weak WWDT1_IRQHandler + .type WWDT1_IRQHandler, %function +WWDT1_IRQHandler: + ldr r0,=WWDT1_DriverIRQHandler + bx r0 + .size WWDT1_IRQHandler, . - WWDT1_IRQHandler + + .align 1 + .thumb_func + .weak CMC0_IRQHandler + .type CMC0_IRQHandler, %function +CMC0_IRQHandler: + ldr r0,=CMC0_DriverIRQHandler + bx r0 + .size CMC0_IRQHandler, . - CMC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved171_IRQHandler + .type Reserved171_IRQHandler, %function +Reserved171_IRQHandler: + ldr r0,=Reserved171_DriverIRQHandler + bx r0 + .size Reserved171_IRQHandler, . - Reserved171_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler OR_DriverIRQHandler + def_irq_handler EDMA_0_CH0_DriverIRQHandler + def_irq_handler EDMA_0_CH1_DriverIRQHandler + def_irq_handler EDMA_0_CH2_DriverIRQHandler + def_irq_handler EDMA_0_CH3_DriverIRQHandler + def_irq_handler EDMA_0_CH4_DriverIRQHandler + def_irq_handler EDMA_0_CH5_DriverIRQHandler + def_irq_handler EDMA_0_CH6_DriverIRQHandler + def_irq_handler EDMA_0_CH7_DriverIRQHandler + def_irq_handler EDMA_0_CH8_DriverIRQHandler + def_irq_handler EDMA_0_CH9_DriverIRQHandler + def_irq_handler EDMA_0_CH10_DriverIRQHandler + def_irq_handler EDMA_0_CH11_DriverIRQHandler + def_irq_handler EDMA_0_CH12_DriverIRQHandler + def_irq_handler EDMA_0_CH13_DriverIRQHandler + def_irq_handler EDMA_0_CH14_DriverIRQHandler + def_irq_handler EDMA_0_CH15_DriverIRQHandler + def_irq_handler GPIO00_DriverIRQHandler + def_irq_handler GPIO01_DriverIRQHandler + def_irq_handler GPIO10_DriverIRQHandler + def_irq_handler GPIO11_DriverIRQHandler + def_irq_handler GPIO20_DriverIRQHandler + def_irq_handler GPIO21_DriverIRQHandler + def_irq_handler GPIO30_DriverIRQHandler + def_irq_handler GPIO31_DriverIRQHandler + def_irq_handler GPIO40_DriverIRQHandler + def_irq_handler GPIO41_DriverIRQHandler + def_irq_handler GPIO50_DriverIRQHandler + def_irq_handler GPIO51_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler Reserved49_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM0_DriverIRQHandler + def_irq_handler LP_FLEXCOMM1_DriverIRQHandler + def_irq_handler LP_FLEXCOMM2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM3_DriverIRQHandler + def_irq_handler LP_FLEXCOMM4_DriverIRQHandler + def_irq_handler LP_FLEXCOMM5_DriverIRQHandler + def_irq_handler LP_FLEXCOMM6_DriverIRQHandler + def_irq_handler LP_FLEXCOMM7_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler PINT0_DriverIRQHandler + def_irq_handler PDM_EVENT_DriverIRQHandler + def_irq_handler Reserved65_DriverIRQHandler + def_irq_handler Reserved66_DriverIRQHandler + def_irq_handler USB0_DCD_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler SMARTDMA_DriverIRQHandler + def_irq_handler Reserved70_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved74_DriverIRQHandler + def_irq_handler SAI0_DriverIRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler Reserved79_DriverIRQHandler + def_irq_handler Reserved80_DriverIRQHandler + def_irq_handler Reserved81_DriverIRQHandler + def_irq_handler USB1_HS_PHY_DriverIRQHandler + def_irq_handler USB1_HS_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler Freqme_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler ELS_DriverIRQHandler + def_irq_handler PKC_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler Reserved92_DriverIRQHandler + def_irq_handler EDMA_1_CH0_DriverIRQHandler + def_irq_handler EDMA_1_CH1_DriverIRQHandler + def_irq_handler EDMA_1_CH2_DriverIRQHandler + def_irq_handler EDMA_1_CH3_DriverIRQHandler + def_irq_handler EDMA_1_CH4_DriverIRQHandler + def_irq_handler EDMA_1_CH5_DriverIRQHandler + def_irq_handler EDMA_1_CH6_DriverIRQHandler + def_irq_handler EDMA_1_CH7_DriverIRQHandler + def_irq_handler Reserved101_DriverIRQHandler + def_irq_handler Reserved102_DriverIRQHandler + def_irq_handler Reserved103_DriverIRQHandler + def_irq_handler Reserved104_DriverIRQHandler + def_irq_handler Reserved105_DriverIRQHandler + def_irq_handler Reserved106_DriverIRQHandler + def_irq_handler Reserved107_DriverIRQHandler + def_irq_handler Reserved108_DriverIRQHandler + def_irq_handler CDOG0_DriverIRQHandler + def_irq_handler CDOG1_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler I3C1_DriverIRQHandler + def_irq_handler Reserved113_DriverIRQHandler + def_irq_handler GDET_DriverIRQHandler + def_irq_handler VBAT0_DriverIRQHandler + def_irq_handler EWM0_DriverIRQHandler + def_irq_handler Reserved117_DriverIRQHandler + def_irq_handler Reserved118_DriverIRQHandler + def_irq_handler Reserved119_DriverIRQHandler + def_irq_handler Reserved120_DriverIRQHandler + def_irq_handler FLEXIO_DriverIRQHandler + def_irq_handler Reserved122_DriverIRQHandler + def_irq_handler Reserved123_DriverIRQHandler + def_irq_handler Reserved124_DriverIRQHandler + def_irq_handler HSCMP0_DriverIRQHandler + def_irq_handler HSCMP1_DriverIRQHandler + def_irq_handler Reserved127_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE3_DriverIRQHandler + def_irq_handler Reserved134_DriverIRQHandler + def_irq_handler Reserved135_DriverIRQHandler + def_irq_handler Reserved136_DriverIRQHandler + def_irq_handler Reserved137_DriverIRQHandler + def_irq_handler Reserved138_DriverIRQHandler + def_irq_handler Reserved139_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler + def_irq_handler ITRC0_DriverIRQHandler + def_irq_handler Reserved149_DriverIRQHandler + def_irq_handler ELS_ERR_DriverIRQHandler + def_irq_handler PKC_ERR_DriverIRQHandler + def_irq_handler ERM_SINGLE_BIT_ERROR_DriverIRQHandler + def_irq_handler ERM_MULTI_BIT_ERROR_DriverIRQHandler + def_irq_handler FMU0_DriverIRQHandler + def_irq_handler Reserved155_DriverIRQHandler + def_irq_handler Reserved156_DriverIRQHandler + def_irq_handler Reserved157_DriverIRQHandler + def_irq_handler Reserved158_DriverIRQHandler + def_irq_handler LPTMR0_DriverIRQHandler + def_irq_handler LPTMR1_DriverIRQHandler + def_irq_handler SCG_DriverIRQHandler + def_irq_handler SPC_DriverIRQHandler + def_irq_handler WUU_DriverIRQHandler + def_irq_handler PORT_EFT_DriverIRQHandler + def_irq_handler Reserved165_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler + def_irq_handler WWDT0_DriverIRQHandler + def_irq_handler WWDT1_DriverIRQHandler + def_irq_handler CMC0_DriverIRQHandler + def_irq_handler Reserved171_DriverIRQHandler + + .end diff --git a/devices/MCXN235/mcuxpresso/startup_mcxn235.c b/devices/MCXN235/mcuxpresso/startup_mcxn235.c new file mode 100644 index 000000000..b76e4fb65 --- /dev/null +++ b/devices/MCXN235/mcuxpresso/startup_mcxn235.c @@ -0,0 +1,1409 @@ +//***************************************************************************** +// MCXN235 startup code for use with MCUXpresso IDE +// +// Version : 090424 +//***************************************************************************** +// +// Copyright 2016-2024 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void OR_IRQHandler(void); +WEAK void EDMA_0_CH0_IRQHandler(void); +WEAK void EDMA_0_CH1_IRQHandler(void); +WEAK void EDMA_0_CH2_IRQHandler(void); +WEAK void EDMA_0_CH3_IRQHandler(void); +WEAK void EDMA_0_CH4_IRQHandler(void); +WEAK void EDMA_0_CH5_IRQHandler(void); +WEAK void EDMA_0_CH6_IRQHandler(void); +WEAK void EDMA_0_CH7_IRQHandler(void); +WEAK void EDMA_0_CH8_IRQHandler(void); +WEAK void EDMA_0_CH9_IRQHandler(void); +WEAK void EDMA_0_CH10_IRQHandler(void); +WEAK void EDMA_0_CH11_IRQHandler(void); +WEAK void EDMA_0_CH12_IRQHandler(void); +WEAK void EDMA_0_CH13_IRQHandler(void); +WEAK void EDMA_0_CH14_IRQHandler(void); +WEAK void EDMA_0_CH15_IRQHandler(void); +WEAK void GPIO00_IRQHandler(void); +WEAK void GPIO01_IRQHandler(void); +WEAK void GPIO10_IRQHandler(void); +WEAK void GPIO11_IRQHandler(void); +WEAK void GPIO20_IRQHandler(void); +WEAK void GPIO21_IRQHandler(void); +WEAK void GPIO30_IRQHandler(void); +WEAK void GPIO31_IRQHandler(void); +WEAK void GPIO40_IRQHandler(void); +WEAK void GPIO41_IRQHandler(void); +WEAK void GPIO50_IRQHandler(void); +WEAK void GPIO51_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void Reserved49_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void LP_FLEXCOMM0_IRQHandler(void); +WEAK void LP_FLEXCOMM1_IRQHandler(void); +WEAK void LP_FLEXCOMM2_IRQHandler(void); +WEAK void LP_FLEXCOMM3_IRQHandler(void); +WEAK void LP_FLEXCOMM4_IRQHandler(void); +WEAK void LP_FLEXCOMM5_IRQHandler(void); +WEAK void LP_FLEXCOMM6_IRQHandler(void); +WEAK void LP_FLEXCOMM7_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void PINT0_IRQHandler(void); +WEAK void PDM_EVENT_IRQHandler(void); +WEAK void Reserved65_IRQHandler(void); +WEAK void Reserved66_IRQHandler(void); +WEAK void USB0_DCD_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved70_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved74_IRQHandler(void); +WEAK void SAI0_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved79_IRQHandler(void); +WEAK void Reserved80_IRQHandler(void); +WEAK void Reserved81_IRQHandler(void); +WEAK void USB1_HS_PHY_IRQHandler(void); +WEAK void USB1_HS_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Freqme_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void ELS_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void EDMA_1_CH0_IRQHandler(void); +WEAK void EDMA_1_CH1_IRQHandler(void); +WEAK void EDMA_1_CH2_IRQHandler(void); +WEAK void EDMA_1_CH3_IRQHandler(void); +WEAK void EDMA_1_CH4_IRQHandler(void); +WEAK void EDMA_1_CH5_IRQHandler(void); +WEAK void EDMA_1_CH6_IRQHandler(void); +WEAK void EDMA_1_CH7_IRQHandler(void); +WEAK void Reserved101_IRQHandler(void); +WEAK void Reserved102_IRQHandler(void); +WEAK void Reserved103_IRQHandler(void); +WEAK void Reserved104_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void I3C1_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void GDET_IRQHandler(void); +WEAK void VBAT0_IRQHandler(void); +WEAK void EWM0_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void Reserved124_IRQHandler(void); +WEAK void HSCMP0_IRQHandler(void); +WEAK void HSCMP1_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void Reserved135_IRQHandler(void); +WEAK void Reserved136_IRQHandler(void); +WEAK void Reserved137_IRQHandler(void); +WEAK void Reserved138_IRQHandler(void); +WEAK void Reserved139_IRQHandler(void); +WEAK void QDC0_COMPARE_IRQHandler(void); +WEAK void QDC0_HOME_IRQHandler(void); +WEAK void QDC0_WDG_SAB_IRQHandler(void); +WEAK void QDC0_IDX_IRQHandler(void); +WEAK void QDC1_COMPARE_IRQHandler(void); +WEAK void QDC1_HOME_IRQHandler(void); +WEAK void QDC1_WDG_SAB_IRQHandler(void); +WEAK void QDC1_IDX_IRQHandler(void); +WEAK void ITRC0_IRQHandler(void); +WEAK void Reserved149_IRQHandler(void); +WEAK void ELS_ERR_IRQHandler(void); +WEAK void PKC_ERR_IRQHandler(void); +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void); +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void Reserved155_IRQHandler(void); +WEAK void Reserved156_IRQHandler(void); +WEAK void Reserved157_IRQHandler(void); +WEAK void Reserved158_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void LPTMR1_IRQHandler(void); +WEAK void SCG_IRQHandler(void); +WEAK void SPC_IRQHandler(void); +WEAK void WUU_IRQHandler(void); +WEAK void PORT_EFT_IRQHandler(void); +WEAK void Reserved165_IRQHandler(void); +WEAK void Reserved166_IRQHandler(void); +WEAK void Reserved167_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void WWDT1_IRQHandler(void); +WEAK void CMC0_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void OR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH12_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH13_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH14_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO00_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO01_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO40_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO50_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO51_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved49_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PDM_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SMARTDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved77_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved79_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved80_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved81_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved85_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Freqme_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved92_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved101_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved102_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved103_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved104_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved105_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved106_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved107_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved108_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved113_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GDET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void VBAT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved117_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved118_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved119_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved120_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved122_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved124_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved127_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved134_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved135_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved136_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved137_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved138_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved139_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ITRC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved149_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_SINGLE_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_MULTI_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FMU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved155_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved156_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved157_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved158_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WUU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PORT_EFT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved165_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved166_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved167_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +extern void _vStackBase(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** + +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXN235 + OR_IRQHandler, // 16 : OR IRQ + EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete + EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete + EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete + EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete + EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete + EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete + EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete + EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete + EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete + EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete + EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete + EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete + EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete + EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete + EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete + EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete + GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 + GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 + GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 + GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 + GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 + GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 + GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 + GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 + GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 + GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 + GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 + GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 + UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt + MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt + CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt + Reserved49_IRQHandler, // 49 : Reserved interrupt + CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt + LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose interrupt + ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose interrupt + PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt + PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt + Reserved65_IRQHandler, // 65 : Reserved interrupt + Reserved66_IRQHandler, // 66 : Reserved interrupt + USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect interrupt + RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) + SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ + Reserved70_IRQHandler, // 70 : Reserved interrupt + CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + Reserved74_IRQHandler, // 74 : Reserved interrupt + SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt + SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt + Reserved79_IRQHandler, // 79 : Reserved interrupt + Reserved80_IRQHandler, // 80 : Reserved interrupt + Reserved81_IRQHandler, // 81 : Reserved interrupt + USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt + USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt + SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor call interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Freqme_IRQHandler, // 87 : Frequency Measurement interrupt + SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) + ELS_IRQHandler, // 89 : ELS interrupt + PKC_IRQHandler, // 90 : PKC interrupt + PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt + Reserved92_IRQHandler, // 92 : Reserved interrupt + EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete + EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete + EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete + EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete + EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete + EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete + EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete + EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete + Reserved101_IRQHandler, // 101: Reserved interrupt + Reserved102_IRQHandler, // 102: Reserved interrupt + Reserved103_IRQHandler, // 103: Reserved interrupt + Reserved104_IRQHandler, // 104: Reserved interrupt + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt + CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt + I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 + I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 + Reserved113_IRQHandler, // 113: Reserved interrupt + GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt + VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper interrupt) + EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + Reserved124_IRQHandler, // 124: Reserved interrupt + HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt + HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 capture/compare/reload interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + Reserved135_IRQHandler, // 135: Reserved interrupt + Reserved136_IRQHandler, // 136: Reserved interrupt + Reserved137_IRQHandler, // 137: Reserved interrupt + Reserved138_IRQHandler, // 138: Reserved interrupt + Reserved139_IRQHandler, // 139: Reserved interrupt + QDC0_COMPARE_IRQHandler, // 140: QDC0_Compare interrupt + QDC0_HOME_IRQHandler, // 141: QDC0_Home interrupt + QDC0_WDG_SAB_IRQHandler, // 142: QDC0_WDG_IRQ/SAB interrupt + QDC0_IDX_IRQHandler, // 143: QDC0_IDX interrupt + QDC1_COMPARE_IRQHandler, // 144: QDC1_Compare interrupt + QDC1_HOME_IRQHandler, // 145: QDC1_Home interrupt + QDC1_WDG_SAB_IRQHandler, // 146: QDC1_WDG_IRQ/SAB interrupt + QDC1_IDX_IRQHandler, // 147: QDC1_IDX interrupt + ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller interrupt + Reserved149_IRQHandler, // 149: Reserved interrupt + ELS_ERR_IRQHandler, // 150: ELS error interrupt + PKC_ERR_IRQHandler, // 151: PKC error interrupt + ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt + ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt + FMU0_IRQHandler, // 154: Flash Management Unit interrupt + Reserved155_IRQHandler, // 155: Reserved interrupt + Reserved156_IRQHandler, // 156: Reserved interrupt + Reserved157_IRQHandler, // 157: Reserved interrupt + Reserved158_IRQHandler, // 158: Reserved interrupt + LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt + LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt + SCG_IRQHandler, // 161: System Clock Generator interrupt + SPC_IRQHandler, // 162: System Power Controller interrupt + WUU_IRQHandler, // 163: Wake Up Unit interrupt + PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt + Reserved165_IRQHandler, // 165: Reserved interrupt + Reserved166_IRQHandler, // 166: Reserved interrupt + Reserved167_IRQHandler, // 167: Reserved interrupt + WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt + WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt + CMC0_IRQHandler, // 170: Core Mode Controller interrupt +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((naked, section(".after_vectors.reset"))) +void ResetISR(void) { + // Disable interrupts + __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void OR_IRQHandler(void) +{ OR_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH0_IRQHandler(void) +{ EDMA_0_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH1_IRQHandler(void) +{ EDMA_0_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH2_IRQHandler(void) +{ EDMA_0_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH3_IRQHandler(void) +{ EDMA_0_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH4_IRQHandler(void) +{ EDMA_0_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH5_IRQHandler(void) +{ EDMA_0_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH6_IRQHandler(void) +{ EDMA_0_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH7_IRQHandler(void) +{ EDMA_0_CH7_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH8_IRQHandler(void) +{ EDMA_0_CH8_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH9_IRQHandler(void) +{ EDMA_0_CH9_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH10_IRQHandler(void) +{ EDMA_0_CH10_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH11_IRQHandler(void) +{ EDMA_0_CH11_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH12_IRQHandler(void) +{ EDMA_0_CH12_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH13_IRQHandler(void) +{ EDMA_0_CH13_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH14_IRQHandler(void) +{ EDMA_0_CH14_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH15_IRQHandler(void) +{ EDMA_0_CH15_DriverIRQHandler(); +} + +WEAK void GPIO00_IRQHandler(void) +{ GPIO00_DriverIRQHandler(); +} + +WEAK void GPIO01_IRQHandler(void) +{ GPIO01_DriverIRQHandler(); +} + +WEAK void GPIO10_IRQHandler(void) +{ GPIO10_DriverIRQHandler(); +} + +WEAK void GPIO11_IRQHandler(void) +{ GPIO11_DriverIRQHandler(); +} + +WEAK void GPIO20_IRQHandler(void) +{ GPIO20_DriverIRQHandler(); +} + +WEAK void GPIO21_IRQHandler(void) +{ GPIO21_DriverIRQHandler(); +} + +WEAK void GPIO30_IRQHandler(void) +{ GPIO30_DriverIRQHandler(); +} + +WEAK void GPIO31_IRQHandler(void) +{ GPIO31_DriverIRQHandler(); +} + +WEAK void GPIO40_IRQHandler(void) +{ GPIO40_DriverIRQHandler(); +} + +WEAK void GPIO41_IRQHandler(void) +{ GPIO41_DriverIRQHandler(); +} + +WEAK void GPIO50_IRQHandler(void) +{ GPIO50_DriverIRQHandler(); +} + +WEAK void GPIO51_IRQHandler(void) +{ GPIO51_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void Reserved49_IRQHandler(void) +{ Reserved49_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM0_IRQHandler(void) +{ LP_FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM1_IRQHandler(void) +{ LP_FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM2_IRQHandler(void) +{ LP_FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM3_IRQHandler(void) +{ LP_FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM4_IRQHandler(void) +{ LP_FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM5_IRQHandler(void) +{ LP_FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM6_IRQHandler(void) +{ LP_FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM7_IRQHandler(void) +{ LP_FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void PINT0_IRQHandler(void) +{ PINT0_DriverIRQHandler(); +} + +WEAK void PDM_EVENT_IRQHandler(void) +{ PDM_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved65_IRQHandler(void) +{ Reserved65_DriverIRQHandler(); +} + +WEAK void Reserved66_IRQHandler(void) +{ Reserved66_DriverIRQHandler(); +} + +WEAK void USB0_DCD_IRQHandler(void) +{ USB0_DCD_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved70_IRQHandler(void) +{ Reserved70_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved74_IRQHandler(void) +{ Reserved74_DriverIRQHandler(); +} + +WEAK void SAI0_IRQHandler(void) +{ SAI0_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ Reserved77_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ CAN0_DriverIRQHandler(); +} + +WEAK void Reserved79_IRQHandler(void) +{ Reserved79_DriverIRQHandler(); +} + +WEAK void Reserved80_IRQHandler(void) +{ Reserved80_DriverIRQHandler(); +} + +WEAK void Reserved81_IRQHandler(void) +{ Reserved81_DriverIRQHandler(); +} + +WEAK void USB1_HS_PHY_IRQHandler(void) +{ USB1_HS_PHY_DriverIRQHandler(); +} + +WEAK void USB1_HS_IRQHandler(void) +{ USB1_HS_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Freqme_IRQHandler(void) +{ Freqme_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void ELS_IRQHandler(void) +{ ELS_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ PKC_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ Reserved92_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH0_IRQHandler(void) +{ EDMA_1_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH1_IRQHandler(void) +{ EDMA_1_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH2_IRQHandler(void) +{ EDMA_1_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH3_IRQHandler(void) +{ EDMA_1_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH4_IRQHandler(void) +{ EDMA_1_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH5_IRQHandler(void) +{ EDMA_1_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH6_IRQHandler(void) +{ EDMA_1_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH7_IRQHandler(void) +{ EDMA_1_CH7_DriverIRQHandler(); +} + +WEAK void Reserved101_IRQHandler(void) +{ Reserved101_DriverIRQHandler(); +} + +WEAK void Reserved102_IRQHandler(void) +{ Reserved102_DriverIRQHandler(); +} + +WEAK void Reserved103_IRQHandler(void) +{ Reserved103_DriverIRQHandler(); +} + +WEAK void Reserved104_IRQHandler(void) +{ Reserved104_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ Reserved108_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ CDOG0_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ CDOG1_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ I3C0_DriverIRQHandler(); +} + +WEAK void I3C1_IRQHandler(void) +{ I3C1_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ Reserved113_DriverIRQHandler(); +} + +WEAK void GDET_IRQHandler(void) +{ GDET_DriverIRQHandler(); +} + +WEAK void VBAT0_IRQHandler(void) +{ VBAT0_DriverIRQHandler(); +} + +WEAK void EWM0_IRQHandler(void) +{ EWM0_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ Reserved120_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ FLEXIO_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ Reserved122_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void Reserved124_IRQHandler(void) +{ Reserved124_DriverIRQHandler(); +} + +WEAK void HSCMP0_IRQHandler(void) +{ HSCMP0_DriverIRQHandler(); +} + +WEAK void HSCMP1_IRQHandler(void) +{ HSCMP1_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ Reserved127_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ Reserved134_DriverIRQHandler(); +} + +WEAK void Reserved135_IRQHandler(void) +{ Reserved135_DriverIRQHandler(); +} + +WEAK void Reserved136_IRQHandler(void) +{ Reserved136_DriverIRQHandler(); +} + +WEAK void Reserved137_IRQHandler(void) +{ Reserved137_DriverIRQHandler(); +} + +WEAK void Reserved138_IRQHandler(void) +{ Reserved138_DriverIRQHandler(); +} + +WEAK void Reserved139_IRQHandler(void) +{ Reserved139_DriverIRQHandler(); +} + +WEAK void QDC0_COMPARE_IRQHandler(void) +{ QDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC0_HOME_IRQHandler(void) +{ QDC0_HOME_DriverIRQHandler(); +} + +WEAK void QDC0_WDG_SAB_IRQHandler(void) +{ QDC0_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC0_IDX_IRQHandler(void) +{ QDC0_IDX_DriverIRQHandler(); +} + +WEAK void QDC1_COMPARE_IRQHandler(void) +{ QDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC1_HOME_IRQHandler(void) +{ QDC1_HOME_DriverIRQHandler(); +} + +WEAK void QDC1_WDG_SAB_IRQHandler(void) +{ QDC1_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC1_IDX_IRQHandler(void) +{ QDC1_IDX_DriverIRQHandler(); +} + +WEAK void ITRC0_IRQHandler(void) +{ ITRC0_DriverIRQHandler(); +} + +WEAK void Reserved149_IRQHandler(void) +{ Reserved149_DriverIRQHandler(); +} + +WEAK void ELS_ERR_IRQHandler(void) +{ ELS_ERR_DriverIRQHandler(); +} + +WEAK void PKC_ERR_IRQHandler(void) +{ PKC_ERR_DriverIRQHandler(); +} + +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void) +{ ERM_SINGLE_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void) +{ ERM_MULTI_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ FMU0_DriverIRQHandler(); +} + +WEAK void Reserved155_IRQHandler(void) +{ Reserved155_DriverIRQHandler(); +} + +WEAK void Reserved156_IRQHandler(void) +{ Reserved156_DriverIRQHandler(); +} + +WEAK void Reserved157_IRQHandler(void) +{ Reserved157_DriverIRQHandler(); +} + +WEAK void Reserved158_IRQHandler(void) +{ Reserved158_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ LPTMR0_DriverIRQHandler(); +} + +WEAK void LPTMR1_IRQHandler(void) +{ LPTMR1_DriverIRQHandler(); +} + +WEAK void SCG_IRQHandler(void) +{ SCG_DriverIRQHandler(); +} + +WEAK void SPC_IRQHandler(void) +{ SPC_DriverIRQHandler(); +} + +WEAK void WUU_IRQHandler(void) +{ WUU_DriverIRQHandler(); +} + +WEAK void PORT_EFT_IRQHandler(void) +{ PORT_EFT_DriverIRQHandler(); +} + +WEAK void Reserved165_IRQHandler(void) +{ Reserved165_DriverIRQHandler(); +} + +WEAK void Reserved166_IRQHandler(void) +{ Reserved166_DriverIRQHandler(); +} + +WEAK void Reserved167_IRQHandler(void) +{ Reserved167_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ WWDT0_DriverIRQHandler(); +} + +WEAK void WWDT1_IRQHandler(void) +{ WWDT1_DriverIRQHandler(); +} + +WEAK void CMC0_IRQHandler(void) +{ CMC0_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/devices/MCXN235/mcuxpresso/startup_mcxn235.cpp b/devices/MCXN235/mcuxpresso/startup_mcxn235.cpp new file mode 100644 index 000000000..b76e4fb65 --- /dev/null +++ b/devices/MCXN235/mcuxpresso/startup_mcxn235.cpp @@ -0,0 +1,1409 @@ +//***************************************************************************** +// MCXN235 startup code for use with MCUXpresso IDE +// +// Version : 090424 +//***************************************************************************** +// +// Copyright 2016-2024 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void OR_IRQHandler(void); +WEAK void EDMA_0_CH0_IRQHandler(void); +WEAK void EDMA_0_CH1_IRQHandler(void); +WEAK void EDMA_0_CH2_IRQHandler(void); +WEAK void EDMA_0_CH3_IRQHandler(void); +WEAK void EDMA_0_CH4_IRQHandler(void); +WEAK void EDMA_0_CH5_IRQHandler(void); +WEAK void EDMA_0_CH6_IRQHandler(void); +WEAK void EDMA_0_CH7_IRQHandler(void); +WEAK void EDMA_0_CH8_IRQHandler(void); +WEAK void EDMA_0_CH9_IRQHandler(void); +WEAK void EDMA_0_CH10_IRQHandler(void); +WEAK void EDMA_0_CH11_IRQHandler(void); +WEAK void EDMA_0_CH12_IRQHandler(void); +WEAK void EDMA_0_CH13_IRQHandler(void); +WEAK void EDMA_0_CH14_IRQHandler(void); +WEAK void EDMA_0_CH15_IRQHandler(void); +WEAK void GPIO00_IRQHandler(void); +WEAK void GPIO01_IRQHandler(void); +WEAK void GPIO10_IRQHandler(void); +WEAK void GPIO11_IRQHandler(void); +WEAK void GPIO20_IRQHandler(void); +WEAK void GPIO21_IRQHandler(void); +WEAK void GPIO30_IRQHandler(void); +WEAK void GPIO31_IRQHandler(void); +WEAK void GPIO40_IRQHandler(void); +WEAK void GPIO41_IRQHandler(void); +WEAK void GPIO50_IRQHandler(void); +WEAK void GPIO51_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void Reserved49_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void LP_FLEXCOMM0_IRQHandler(void); +WEAK void LP_FLEXCOMM1_IRQHandler(void); +WEAK void LP_FLEXCOMM2_IRQHandler(void); +WEAK void LP_FLEXCOMM3_IRQHandler(void); +WEAK void LP_FLEXCOMM4_IRQHandler(void); +WEAK void LP_FLEXCOMM5_IRQHandler(void); +WEAK void LP_FLEXCOMM6_IRQHandler(void); +WEAK void LP_FLEXCOMM7_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void PINT0_IRQHandler(void); +WEAK void PDM_EVENT_IRQHandler(void); +WEAK void Reserved65_IRQHandler(void); +WEAK void Reserved66_IRQHandler(void); +WEAK void USB0_DCD_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved70_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved74_IRQHandler(void); +WEAK void SAI0_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void Reserved79_IRQHandler(void); +WEAK void Reserved80_IRQHandler(void); +WEAK void Reserved81_IRQHandler(void); +WEAK void USB1_HS_PHY_IRQHandler(void); +WEAK void USB1_HS_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Freqme_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void ELS_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void EDMA_1_CH0_IRQHandler(void); +WEAK void EDMA_1_CH1_IRQHandler(void); +WEAK void EDMA_1_CH2_IRQHandler(void); +WEAK void EDMA_1_CH3_IRQHandler(void); +WEAK void EDMA_1_CH4_IRQHandler(void); +WEAK void EDMA_1_CH5_IRQHandler(void); +WEAK void EDMA_1_CH6_IRQHandler(void); +WEAK void EDMA_1_CH7_IRQHandler(void); +WEAK void Reserved101_IRQHandler(void); +WEAK void Reserved102_IRQHandler(void); +WEAK void Reserved103_IRQHandler(void); +WEAK void Reserved104_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void I3C1_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void GDET_IRQHandler(void); +WEAK void VBAT0_IRQHandler(void); +WEAK void EWM0_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void Reserved124_IRQHandler(void); +WEAK void HSCMP0_IRQHandler(void); +WEAK void HSCMP1_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void Reserved134_IRQHandler(void); +WEAK void Reserved135_IRQHandler(void); +WEAK void Reserved136_IRQHandler(void); +WEAK void Reserved137_IRQHandler(void); +WEAK void Reserved138_IRQHandler(void); +WEAK void Reserved139_IRQHandler(void); +WEAK void QDC0_COMPARE_IRQHandler(void); +WEAK void QDC0_HOME_IRQHandler(void); +WEAK void QDC0_WDG_SAB_IRQHandler(void); +WEAK void QDC0_IDX_IRQHandler(void); +WEAK void QDC1_COMPARE_IRQHandler(void); +WEAK void QDC1_HOME_IRQHandler(void); +WEAK void QDC1_WDG_SAB_IRQHandler(void); +WEAK void QDC1_IDX_IRQHandler(void); +WEAK void ITRC0_IRQHandler(void); +WEAK void Reserved149_IRQHandler(void); +WEAK void ELS_ERR_IRQHandler(void); +WEAK void PKC_ERR_IRQHandler(void); +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void); +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void Reserved155_IRQHandler(void); +WEAK void Reserved156_IRQHandler(void); +WEAK void Reserved157_IRQHandler(void); +WEAK void Reserved158_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void LPTMR1_IRQHandler(void); +WEAK void SCG_IRQHandler(void); +WEAK void SPC_IRQHandler(void); +WEAK void WUU_IRQHandler(void); +WEAK void PORT_EFT_IRQHandler(void); +WEAK void Reserved165_IRQHandler(void); +WEAK void Reserved166_IRQHandler(void); +WEAK void Reserved167_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void WWDT1_IRQHandler(void); +WEAK void CMC0_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void OR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH12_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH13_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH14_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO00_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO01_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO40_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO50_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO51_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved49_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PDM_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SMARTDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved77_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved79_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved80_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved81_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved85_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Freqme_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved92_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved101_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved102_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved103_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved104_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved105_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved106_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved107_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved108_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved113_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GDET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void VBAT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved117_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved118_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved119_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved120_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved122_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved124_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved127_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved134_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved135_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved136_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved137_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved138_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved139_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ITRC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved149_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_SINGLE_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_MULTI_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FMU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved155_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved156_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved157_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved158_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WUU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PORT_EFT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved165_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved166_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved167_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +extern void _vStackBase(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** + +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXN235 + OR_IRQHandler, // 16 : OR IRQ + EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete + EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete + EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete + EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete + EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete + EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete + EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete + EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete + EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete + EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete + EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete + EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete + EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete + EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete + EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete + EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete + GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 + GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 + GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 + GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 + GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 + GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 + GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 + GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 + GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 + GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 + GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 + GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 + UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt + MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt + CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt + Reserved49_IRQHandler, // 49 : Reserved interrupt + CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt + LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose interrupt + ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose interrupt + PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt + PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt + Reserved65_IRQHandler, // 65 : Reserved interrupt + Reserved66_IRQHandler, // 66 : Reserved interrupt + USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect interrupt + RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) + SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ + Reserved70_IRQHandler, // 70 : Reserved interrupt + CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + Reserved74_IRQHandler, // 74 : Reserved interrupt + SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt + SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt + Reserved79_IRQHandler, // 79 : Reserved interrupt + Reserved80_IRQHandler, // 80 : Reserved interrupt + Reserved81_IRQHandler, // 81 : Reserved interrupt + USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt + USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt + SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor call interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Freqme_IRQHandler, // 87 : Frequency Measurement interrupt + SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) + ELS_IRQHandler, // 89 : ELS interrupt + PKC_IRQHandler, // 90 : PKC interrupt + PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt + Reserved92_IRQHandler, // 92 : Reserved interrupt + EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete + EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete + EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete + EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete + EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete + EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete + EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete + EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete + Reserved101_IRQHandler, // 101: Reserved interrupt + Reserved102_IRQHandler, // 102: Reserved interrupt + Reserved103_IRQHandler, // 103: Reserved interrupt + Reserved104_IRQHandler, // 104: Reserved interrupt + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt + CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt + I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 + I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 + Reserved113_IRQHandler, // 113: Reserved interrupt + GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt + VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper interrupt) + EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + Reserved124_IRQHandler, // 124: Reserved interrupt + HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt + HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 capture/compare/reload interrupt + Reserved134_IRQHandler, // 134: Reserved interrupt + Reserved135_IRQHandler, // 135: Reserved interrupt + Reserved136_IRQHandler, // 136: Reserved interrupt + Reserved137_IRQHandler, // 137: Reserved interrupt + Reserved138_IRQHandler, // 138: Reserved interrupt + Reserved139_IRQHandler, // 139: Reserved interrupt + QDC0_COMPARE_IRQHandler, // 140: QDC0_Compare interrupt + QDC0_HOME_IRQHandler, // 141: QDC0_Home interrupt + QDC0_WDG_SAB_IRQHandler, // 142: QDC0_WDG_IRQ/SAB interrupt + QDC0_IDX_IRQHandler, // 143: QDC0_IDX interrupt + QDC1_COMPARE_IRQHandler, // 144: QDC1_Compare interrupt + QDC1_HOME_IRQHandler, // 145: QDC1_Home interrupt + QDC1_WDG_SAB_IRQHandler, // 146: QDC1_WDG_IRQ/SAB interrupt + QDC1_IDX_IRQHandler, // 147: QDC1_IDX interrupt + ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller interrupt + Reserved149_IRQHandler, // 149: Reserved interrupt + ELS_ERR_IRQHandler, // 150: ELS error interrupt + PKC_ERR_IRQHandler, // 151: PKC error interrupt + ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt + ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt + FMU0_IRQHandler, // 154: Flash Management Unit interrupt + Reserved155_IRQHandler, // 155: Reserved interrupt + Reserved156_IRQHandler, // 156: Reserved interrupt + Reserved157_IRQHandler, // 157: Reserved interrupt + Reserved158_IRQHandler, // 158: Reserved interrupt + LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt + LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt + SCG_IRQHandler, // 161: System Clock Generator interrupt + SPC_IRQHandler, // 162: System Power Controller interrupt + WUU_IRQHandler, // 163: Wake Up Unit interrupt + PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt + Reserved165_IRQHandler, // 165: Reserved interrupt + Reserved166_IRQHandler, // 166: Reserved interrupt + Reserved167_IRQHandler, // 167: Reserved interrupt + WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt + WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt + CMC0_IRQHandler, // 170: Core Mode Controller interrupt +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((naked, section(".after_vectors.reset"))) +void ResetISR(void) { + // Disable interrupts + __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void OR_IRQHandler(void) +{ OR_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH0_IRQHandler(void) +{ EDMA_0_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH1_IRQHandler(void) +{ EDMA_0_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH2_IRQHandler(void) +{ EDMA_0_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH3_IRQHandler(void) +{ EDMA_0_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH4_IRQHandler(void) +{ EDMA_0_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH5_IRQHandler(void) +{ EDMA_0_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH6_IRQHandler(void) +{ EDMA_0_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH7_IRQHandler(void) +{ EDMA_0_CH7_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH8_IRQHandler(void) +{ EDMA_0_CH8_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH9_IRQHandler(void) +{ EDMA_0_CH9_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH10_IRQHandler(void) +{ EDMA_0_CH10_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH11_IRQHandler(void) +{ EDMA_0_CH11_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH12_IRQHandler(void) +{ EDMA_0_CH12_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH13_IRQHandler(void) +{ EDMA_0_CH13_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH14_IRQHandler(void) +{ EDMA_0_CH14_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH15_IRQHandler(void) +{ EDMA_0_CH15_DriverIRQHandler(); +} + +WEAK void GPIO00_IRQHandler(void) +{ GPIO00_DriverIRQHandler(); +} + +WEAK void GPIO01_IRQHandler(void) +{ GPIO01_DriverIRQHandler(); +} + +WEAK void GPIO10_IRQHandler(void) +{ GPIO10_DriverIRQHandler(); +} + +WEAK void GPIO11_IRQHandler(void) +{ GPIO11_DriverIRQHandler(); +} + +WEAK void GPIO20_IRQHandler(void) +{ GPIO20_DriverIRQHandler(); +} + +WEAK void GPIO21_IRQHandler(void) +{ GPIO21_DriverIRQHandler(); +} + +WEAK void GPIO30_IRQHandler(void) +{ GPIO30_DriverIRQHandler(); +} + +WEAK void GPIO31_IRQHandler(void) +{ GPIO31_DriverIRQHandler(); +} + +WEAK void GPIO40_IRQHandler(void) +{ GPIO40_DriverIRQHandler(); +} + +WEAK void GPIO41_IRQHandler(void) +{ GPIO41_DriverIRQHandler(); +} + +WEAK void GPIO50_IRQHandler(void) +{ GPIO50_DriverIRQHandler(); +} + +WEAK void GPIO51_IRQHandler(void) +{ GPIO51_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void Reserved49_IRQHandler(void) +{ Reserved49_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM0_IRQHandler(void) +{ LP_FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM1_IRQHandler(void) +{ LP_FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM2_IRQHandler(void) +{ LP_FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM3_IRQHandler(void) +{ LP_FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM4_IRQHandler(void) +{ LP_FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM5_IRQHandler(void) +{ LP_FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM6_IRQHandler(void) +{ LP_FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM7_IRQHandler(void) +{ LP_FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void PINT0_IRQHandler(void) +{ PINT0_DriverIRQHandler(); +} + +WEAK void PDM_EVENT_IRQHandler(void) +{ PDM_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved65_IRQHandler(void) +{ Reserved65_DriverIRQHandler(); +} + +WEAK void Reserved66_IRQHandler(void) +{ Reserved66_DriverIRQHandler(); +} + +WEAK void USB0_DCD_IRQHandler(void) +{ USB0_DCD_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved70_IRQHandler(void) +{ Reserved70_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved74_IRQHandler(void) +{ Reserved74_DriverIRQHandler(); +} + +WEAK void SAI0_IRQHandler(void) +{ SAI0_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ Reserved77_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ CAN0_DriverIRQHandler(); +} + +WEAK void Reserved79_IRQHandler(void) +{ Reserved79_DriverIRQHandler(); +} + +WEAK void Reserved80_IRQHandler(void) +{ Reserved80_DriverIRQHandler(); +} + +WEAK void Reserved81_IRQHandler(void) +{ Reserved81_DriverIRQHandler(); +} + +WEAK void USB1_HS_PHY_IRQHandler(void) +{ USB1_HS_PHY_DriverIRQHandler(); +} + +WEAK void USB1_HS_IRQHandler(void) +{ USB1_HS_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Freqme_IRQHandler(void) +{ Freqme_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void ELS_IRQHandler(void) +{ ELS_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ PKC_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ Reserved92_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH0_IRQHandler(void) +{ EDMA_1_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH1_IRQHandler(void) +{ EDMA_1_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH2_IRQHandler(void) +{ EDMA_1_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH3_IRQHandler(void) +{ EDMA_1_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH4_IRQHandler(void) +{ EDMA_1_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH5_IRQHandler(void) +{ EDMA_1_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH6_IRQHandler(void) +{ EDMA_1_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH7_IRQHandler(void) +{ EDMA_1_CH7_DriverIRQHandler(); +} + +WEAK void Reserved101_IRQHandler(void) +{ Reserved101_DriverIRQHandler(); +} + +WEAK void Reserved102_IRQHandler(void) +{ Reserved102_DriverIRQHandler(); +} + +WEAK void Reserved103_IRQHandler(void) +{ Reserved103_DriverIRQHandler(); +} + +WEAK void Reserved104_IRQHandler(void) +{ Reserved104_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ Reserved108_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ CDOG0_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ CDOG1_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ I3C0_DriverIRQHandler(); +} + +WEAK void I3C1_IRQHandler(void) +{ I3C1_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ Reserved113_DriverIRQHandler(); +} + +WEAK void GDET_IRQHandler(void) +{ GDET_DriverIRQHandler(); +} + +WEAK void VBAT0_IRQHandler(void) +{ VBAT0_DriverIRQHandler(); +} + +WEAK void EWM0_IRQHandler(void) +{ EWM0_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ Reserved120_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ FLEXIO_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ Reserved122_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void Reserved124_IRQHandler(void) +{ Reserved124_DriverIRQHandler(); +} + +WEAK void HSCMP0_IRQHandler(void) +{ HSCMP0_DriverIRQHandler(); +} + +WEAK void HSCMP1_IRQHandler(void) +{ HSCMP1_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ Reserved127_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void Reserved134_IRQHandler(void) +{ Reserved134_DriverIRQHandler(); +} + +WEAK void Reserved135_IRQHandler(void) +{ Reserved135_DriverIRQHandler(); +} + +WEAK void Reserved136_IRQHandler(void) +{ Reserved136_DriverIRQHandler(); +} + +WEAK void Reserved137_IRQHandler(void) +{ Reserved137_DriverIRQHandler(); +} + +WEAK void Reserved138_IRQHandler(void) +{ Reserved138_DriverIRQHandler(); +} + +WEAK void Reserved139_IRQHandler(void) +{ Reserved139_DriverIRQHandler(); +} + +WEAK void QDC0_COMPARE_IRQHandler(void) +{ QDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC0_HOME_IRQHandler(void) +{ QDC0_HOME_DriverIRQHandler(); +} + +WEAK void QDC0_WDG_SAB_IRQHandler(void) +{ QDC0_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC0_IDX_IRQHandler(void) +{ QDC0_IDX_DriverIRQHandler(); +} + +WEAK void QDC1_COMPARE_IRQHandler(void) +{ QDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC1_HOME_IRQHandler(void) +{ QDC1_HOME_DriverIRQHandler(); +} + +WEAK void QDC1_WDG_SAB_IRQHandler(void) +{ QDC1_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC1_IDX_IRQHandler(void) +{ QDC1_IDX_DriverIRQHandler(); +} + +WEAK void ITRC0_IRQHandler(void) +{ ITRC0_DriverIRQHandler(); +} + +WEAK void Reserved149_IRQHandler(void) +{ Reserved149_DriverIRQHandler(); +} + +WEAK void ELS_ERR_IRQHandler(void) +{ ELS_ERR_DriverIRQHandler(); +} + +WEAK void PKC_ERR_IRQHandler(void) +{ PKC_ERR_DriverIRQHandler(); +} + +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void) +{ ERM_SINGLE_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void) +{ ERM_MULTI_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ FMU0_DriverIRQHandler(); +} + +WEAK void Reserved155_IRQHandler(void) +{ Reserved155_DriverIRQHandler(); +} + +WEAK void Reserved156_IRQHandler(void) +{ Reserved156_DriverIRQHandler(); +} + +WEAK void Reserved157_IRQHandler(void) +{ Reserved157_DriverIRQHandler(); +} + +WEAK void Reserved158_IRQHandler(void) +{ Reserved158_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ LPTMR0_DriverIRQHandler(); +} + +WEAK void LPTMR1_IRQHandler(void) +{ LPTMR1_DriverIRQHandler(); +} + +WEAK void SCG_IRQHandler(void) +{ SCG_DriverIRQHandler(); +} + +WEAK void SPC_IRQHandler(void) +{ SPC_DriverIRQHandler(); +} + +WEAK void WUU_IRQHandler(void) +{ WUU_DriverIRQHandler(); +} + +WEAK void PORT_EFT_IRQHandler(void) +{ PORT_EFT_DriverIRQHandler(); +} + +WEAK void Reserved165_IRQHandler(void) +{ Reserved165_DriverIRQHandler(); +} + +WEAK void Reserved166_IRQHandler(void) +{ Reserved166_DriverIRQHandler(); +} + +WEAK void Reserved167_IRQHandler(void) +{ Reserved167_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ WWDT0_DriverIRQHandler(); +} + +WEAK void WWDT1_IRQHandler(void) +{ WWDT1_DriverIRQHandler(); +} + +WEAK void CMC0_IRQHandler(void) +{ CMC0_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/devices/MCXN235/project_template/board.c b/devices/MCXN235/project_template/board.c new file mode 100644 index 000000000..30bda70e0 --- /dev/null +++ b/devices/MCXN235/project_template/board.c @@ -0,0 +1,24 @@ +/* + * Copyright 201, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file board.c + * @brief Board initialization file. + */ + +/* This is an empty template for board specific configuration.*/ + +#include +#include "board.h" + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + */ +void BOARD_InitDebugConsole(void) +{ + /* The user initialization should be placed here */ +} diff --git a/devices/MCXN235/project_template/board.h b/devices/MCXN235/project_template/board.h new file mode 100644 index 000000000..b3b5ef0f5 --- /dev/null +++ b/devices/MCXN235/project_template/board.h @@ -0,0 +1,36 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file board.h + * @brief Board initialization header file. + */ + +/* This is an empty template for board specific configuration.*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/** + * @brief The board name + */ +#define BOARD_NAME "board" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initialize board specific settings. + */ +void BOARD_InitDebugConsole(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/devices/MCXN235/project_template/clock_config.c b/devices/MCXN235/project_template/clock_config.c new file mode 100644 index 000000000..8e5b03871 --- /dev/null +++ b/devices/MCXN235/project_template/clock_config.c @@ -0,0 +1,32 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v4.0 +* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/** + * @file clock_config.c + * @brief Board clocks initialization file. + */ + +/* This is a empty template for board specific configuration.*/ + +#include "fsl_common.h" +#include "clock_config.h" + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + */ +void BOARD_InitBootClocks(void) +{ + /* The user initialization should be placed here */ + + /* Read core clock setting. */ + SystemCoreClockUpdate(); +} diff --git a/devices/MCXN235/project_template/clock_config.h b/devices/MCXN235/project_template/clock_config.h new file mode 100644 index 000000000..b706c0dd1 --- /dev/null +++ b/devices/MCXN235/project_template/clock_config.h @@ -0,0 +1,31 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file clock_config.h + * @brief Board clocks header file. + */ + +/* This is an empty template for board specific configuration.*/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initialize board clocks. + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/devices/MCXN235/project_template/peripherals.c b/devices/MCXN235/project_template/peripherals.c new file mode 100644 index 000000000..118cdef04 --- /dev/null +++ b/devices/MCXN235/project_template/peripherals.c @@ -0,0 +1,28 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 +* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/** + * @file peripherals.c + * @brief Peripherals initialization file. + */ + +/* This is an empty template for board specific configuration.*/ + +#include "peripherals.h" + +/** + * @brief Set up and initialize all required blocks and functions related to the peripherals hardware. + */ +void BOARD_InitBootPeripherals(void) +{ + /* The user initialization should be placed here */ +} diff --git a/devices/MCXN235/project_template/peripherals.h b/devices/MCXN235/project_template/peripherals.h new file mode 100644 index 000000000..9180d4d63 --- /dev/null +++ b/devices/MCXN235/project_template/peripherals.h @@ -0,0 +1,31 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file peripherals.h + * @brief Peripherals initialization header file. + */ + +/* This is an empty template for board specific configuration.*/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initialize peripherals specific settings. + */ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/devices/MCXN235/project_template/pin_mux.c b/devices/MCXN235/project_template/pin_mux.c new file mode 100644 index 000000000..ccf6fcc12 --- /dev/null +++ b/devices/MCXN235/project_template/pin_mux.c @@ -0,0 +1,27 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.0 +* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********/ + +/** + * @file pin_mux.c + * @brief Board pins file. + */ + +/* This is an empty template for board specific configuration.*/ + +#include "pin_mux.h" + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + */ +void BOARD_InitBootPins(void) { + /* The user initialization should be placed here */ +} diff --git a/devices/MCXN235/project_template/pin_mux.h b/devices/MCXN235/project_template/pin_mux.h new file mode 100644 index 000000000..24f971e82 --- /dev/null +++ b/devices/MCXN235/project_template/pin_mux.h @@ -0,0 +1,33 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file pin_mux.h + * @brief Board pins header file. + */ + +/* This is an empty template for board specific configuration.*/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initialize board pins. + */ +void BOARD_InitBootPins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PIN_MUX_H_ */ + + diff --git a/devices/MCXN235/set_device_MCXN235.cmake b/devices/MCXN235/set_device_MCXN235.cmake new file mode 100644 index 000000000..e0b9039f3 --- /dev/null +++ b/devices/MCXN235/set_device_MCXN235.cmake @@ -0,0 +1,2 @@ +include_guard(GLOBAL) + diff --git a/devices/MCXN235/system_MCXN235.c b/devices/MCXN235/system_MCXN235.c new file mode 100644 index 000000000..0d4d2a9d6 --- /dev/null +++ b/devices/MCXN235/system_MCXN235.c @@ -0,0 +1,128 @@ +/* +** ################################################################### +** Processors: MCXN235VDF +** MCXN235VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN235 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN235 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/devices/MCXN235/system_MCXN235.h b/devices/MCXN235/system_MCXN235.h new file mode 100644 index 000000000..1de253cd9 --- /dev/null +++ b/devices/MCXN235/system_MCXN235.h @@ -0,0 +1,106 @@ +/* +** ################################################################### +** Processors: MCXN235VDF +** MCXN235VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN235 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN235 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN235_H_ +#define _SYSTEM_MCXN235_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN235_H_ */ diff --git a/devices/MCXN235/template/RTE_Device.h b/devices/MCXN235/template/RTE_Device.h new file mode 100644 index 000000000..7313b556b --- /dev/null +++ b/devices/MCXN235/template/RTE_Device.h @@ -0,0 +1,230 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +#include "pin_mux.h" + +/* UART Select, UART0-UART7. */ +/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART + * instance. */ +#define RTE_USART0 0 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 +#define RTE_USART6 0 +#define RTE_USART6_DMA_EN 0 +#define RTE_USART7 0 +#define RTE_USART7_DMA_EN 0 + +/* USART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 +#define USART6_RX_BUFFER_ENABLE 0 +#define USART7_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_PIN_INIT USART0_InitPins +#define RTE_USART0_PIN_DEINIT USART0_DeinitPins +#define RTE_USART0_DMA_TX_CH 5 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 4 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_PIN_INIT USART1_InitPins +#define RTE_USART1_PIN_DEINIT USART1_DeinitPins +#define RTE_USART1_DMA_TX_CH 7 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 6 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_PIN_INIT USART2_InitPins +#define RTE_USART2_PIN_DEINIT USART2_DeinitPins +#define RTE_USART2_DMA_TX_CH 8 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 9 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_PIN_INIT USART3_InitPins +#define RTE_USART3_PIN_DEINIT USART3_DeinitPins +#define RTE_USART3_DMA_TX_CH 10 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 11 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_PIN_INIT USART4_InitPins +#define RTE_USART4_PIN_DEINIT USART4_DeinitPins +#define RTE_USART4_DMA_TX_CH 13 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 12 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_PIN_INIT USART5_InitPins +#define RTE_USART5_PIN_DEINIT USART5_DeinitPins +#define RTE_USART5_DMA_TX_CH 15 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 14 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART6_PIN_INIT USART6_InitPins +#define RTE_USART6_PIN_DEINIT USART6_DeinitPins +#define RTE_USART6_DMA_TX_CH 17 +#define RTE_USART6_DMA_TX_DMA_BASE DMA0 +#define RTE_USART6_DMA_RX_CH 16 +#define RTE_USART6_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART7_PIN_INIT USART7_InitPins +#define RTE_USART7_PIN_DEINIT USART7_DeinitPins +#define RTE_USART7_DMA_TX_CH 19 +#define RTE_USART7_DMA_TX_DMA_BASE DMA0 +#define RTE_USART7_DMA_RX_CH 18 +#define RTE_USART7_DMA_RX_DMA_BASE DMA0 + +/* I2C Select, I2C0 -I2C7*/ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 +#define RTE_I2C5 0 +#define RTE_I2C5_DMA_EN 0 +#define RTE_I2C6 0 +#define RTE_I2C6_DMA_EN 0 +#define RTE_I2C7 0 +#define RTE_I2C7_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 1 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 3 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 5 + +#define RTE_I2C3_Master_DMA_BASE DMA0 +#define RTE_I2C3_Master_DMA_CH 7 + +#define RTE_I2C4_Master_DMA_BASE DMA0 +#define RTE_I2C4_Master_DMA_CH 9 + +#define RTE_I2C5_Master_DMA_BASE DMA0 +#define RTE_I2C5_Master_DMA_CH 11 + +#define RTE_I2C6_Master_DMA_BASE DMA0 +#define RTE_I2C6_Master_DMA_CH 13 + +#define RTE_I2C7_Master_DMA_BASE DMA0 +#define RTE_I2C7_Master_DMA_CH 15 + +/* SPI select, SPI0 - SPI7.*/ +/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. + */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 +#define RTE_SPI3 0 +#define RTE_SPI3_DMA_EN 0 +#define RTE_SPI4 0 +#define RTE_SPI4_DMA_EN 0 +#define RTE_SPI5 0 +#define RTE_SPI5_DMA_EN 0 +#define RTE_SPI6 0 +#define RTE_SPI6_DMA_EN 0 +#define RTE_SPI7 0 +#define RTE_SPI7_DMA_EN 0 + +/* SPI configuration. */ +#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI0_PIN_INIT SPI0_InitPins +#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins +#define RTE_SPI0_DMA_TX_CH 1 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI1_PIN_INIT SPI1_InitPins +#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins +#define RTE_SPI1_DMA_TX_CH 3 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 2 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI2_PIN_INIT SPI2_InitPins +#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins +#define RTE_SPI2_DMA_TX_CH 5 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 4 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI3_PIN_INIT SPI3_InitPins +#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins +#define RTE_SPI3_DMA_TX_CH 7 +#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI3_DMA_RX_CH 6 +#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI4_PIN_INIT SPI4_InitPins +#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins +#define RTE_SPI4_DMA_TX_CH 9 +#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI4_DMA_RX_CH 8 +#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI5_PIN_INIT SPI5_InitPins +#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins +#define RTE_SPI5_DMA_TX_CH 11 +#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI5_DMA_RX_CH 10 +#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI6_PIN_INIT SPI6_InitPins +#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins +#define RTE_SPI6_DMA_TX_CH 13 +#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI6_DMA_RX_CH 12 +#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI7_PIN_INIT SPI7_InitPins +#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins +#define RTE_SPI7_DMA_TX_CH 15 +#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI7_DMA_RX_CH 14 +#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 + +#endif /* _RTE_DEVICE_H */ diff --git a/devices/MCXN236/MCXN236.h b/devices/MCXN236/MCXN236.h new file mode 100644 index 000000000..113e97967 --- /dev/null +++ b/devices/MCXN236/MCXN236.h @@ -0,0 +1,70367 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240409 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN236 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236.h + * @version 1.0 + * @date 2023-10-01 + * @brief CMSIS Peripheral Access Layer for MCXN236 + * + * CMSIS Peripheral Access Layer for MCXN236 + */ + +#if !defined(MCXN236_H_) +#define MCXN236_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + Reserved49_IRQn = 33, /**< Reserved interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + Reserved70_IRQn = 54, /**< Reserved interrupt */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + Reserved74_IRQn = 58, /**< Reserved interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 63, /**< Controller Area Network 1 interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + Reserved101_IRQn = 85, /**< Reserved interrupt */ + Reserved102_IRQn = 86, /**< Reserved interrupt */ + Reserved103_IRQn = 87, /**< Reserved interrupt */ + Reserved104_IRQn = 88, /**< Reserved interrupt */ + Reserved105_IRQn = 89, /**< Reserved interrupt */ + Reserved106_IRQn = 90, /**< Reserved interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + Reserved122_IRQn = 106, /**< Reserved interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 118, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 119, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 120, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + Reserved165_IRQn = 149, /**< Reserved interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + Reserved171_IRQn = 155 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN236.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kEIM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kEIM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kEIM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kEIM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kEIM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kEIM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kEIM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kEIM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ +} eim_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ + kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ + kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ + kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ + kEIM_MemoryChannelRAMDEnable = 0x8000000U, /**< Memory channel 4(RAMD) error injection enable */ + kEIM_MemoryChannelRAMEEnable = 0x4000000U, /**< Memory channel 5(RAME) error injection enable */ + kEIM_MemoryChannelRAMFEnable = 0x2000000U, /**< Memory channel 6(RAMF) error injection enable */ + kEIM_MemoryChannelLPCACRAMEnable = 0x1000000U, /**< Memory channel 7(LPCACRAM) error injection enable */ + kEIM_MemoryChannelPKCRAMEnable = 0x800000U, /**< Memory channel 8(PKCRAM) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ + +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kERM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kERM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kERM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kERM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kERM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kERM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kERM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kERM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ + kERM_MemoryChannelFLASH = 9U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[48]; + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_5[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_6[136]; + __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[196]; + __I uint32_t RESFIFO[2]; /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[248]; + __IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset: 0x400 */ + __IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset: 0x404 */ + __IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset: 0x408 */ + __IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset: 0x40C */ + __IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset: 0x410 */ + __IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset: 0x414 */ + __IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset: 0x418 */ + __IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset: 0x41C */ + __IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset: 0x420 */ + __IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset: 0x424 */ + __IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset: 0x428 */ + __IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset: 0x42C */ + __IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset: 0x430 */ + __IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset: 0x434 */ + __IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset: 0x438 */ + __IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset: 0x43C */ + __IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset: 0x440 */ + __IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset: 0x444 */ + __IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset: 0x448 */ + __IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset: 0x44C */ + __IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset: 0x450 */ + __IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset: 0x454 */ + __IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset: 0x458 */ + __IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset: 0x45C */ + __IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset: 0x460 */ + __IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset: 0x464 */ + __IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset: 0x468 */ + __IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset: 0x46C */ + __IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset: 0x470 */ + __IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset: 0x474 */ + __IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset: 0x478 */ + __IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset: 0x47C */ + __IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset: 0x480 */ + uint8_t RESERVED_9[124]; + __IO uint32_t CAL_GBR0; /**< Calibration General B-Side Registers, offset: 0x500 */ + __IO uint32_t CAL_GBR1; /**< Calibration General B-Side Registers, offset: 0x504 */ + __IO uint32_t CAL_GBR2; /**< Calibration General B-Side Registers, offset: 0x508 */ + __IO uint32_t CAL_GBR3; /**< Calibration General B-Side Registers, offset: 0x50C */ + __IO uint32_t CAL_GBR4; /**< Calibration General B-Side Registers, offset: 0x510 */ + __IO uint32_t CAL_GBR5; /**< Calibration General B-Side Registers, offset: 0x514 */ + __IO uint32_t CAL_GBR6; /**< Calibration General B-Side Registers, offset: 0x518 */ + __IO uint32_t CAL_GBR7; /**< Calibration General B-Side Registers, offset: 0x51C */ + __IO uint32_t CAL_GBR8; /**< Calibration General B-Side Registers, offset: 0x520 */ + __IO uint32_t CAL_GBR9; /**< Calibration General B-Side Registers, offset: 0x524 */ + __IO uint32_t CAL_GBR10; /**< Calibration General B-Side Registers, offset: 0x528 */ + __IO uint32_t CAL_GBR11; /**< Calibration General B-Side Registers, offset: 0x52C */ + __IO uint32_t CAL_GBR12; /**< Calibration General B-Side Registers, offset: 0x530 */ + __IO uint32_t CAL_GBR13; /**< Calibration General B-Side Registers, offset: 0x534 */ + __IO uint32_t CAL_GBR14; /**< Calibration General B-Side Registers, offset: 0x538 */ + __IO uint32_t CAL_GBR15; /**< Calibration General B-Side Registers, offset: 0x53C */ + __IO uint32_t CAL_GBR16; /**< Calibration General B-Side Registers, offset: 0x540 */ + __IO uint32_t CAL_GBR17; /**< Calibration General B-Side Registers, offset: 0x544 */ + __IO uint32_t CAL_GBR18; /**< Calibration General B-Side Registers, offset: 0x548 */ + __IO uint32_t CAL_GBR19; /**< Calibration General B-Side Registers, offset: 0x54C */ + __IO uint32_t CAL_GBR20; /**< Calibration General B-Side Registers, offset: 0x550 */ + __IO uint32_t CAL_GBR21; /**< Calibration General B-Side Registers, offset: 0x554 */ + __IO uint32_t CAL_GBR22; /**< Calibration General B-Side Registers, offset: 0x558 */ + __IO uint32_t CAL_GBR23; /**< Calibration General B-Side Registers, offset: 0x55C */ + __IO uint32_t CAL_GBR24; /**< Calibration General B-Side Registers, offset: 0x560 */ + __IO uint32_t CAL_GBR25; /**< Calibration General B-Side Registers, offset: 0x564 */ + __IO uint32_t CAL_GBR26; /**< Calibration General B-Side Registers, offset: 0x568 */ + __IO uint32_t CAL_GBR27; /**< Calibration General B-Side Registers, offset: 0x56C */ + __IO uint32_t CAL_GBR28; /**< Calibration General B-Side Registers, offset: 0x570 */ + __IO uint32_t CAL_GBR29; /**< Calibration General B-Side Registers, offset: 0x574 */ + __IO uint32_t CAL_GBR30; /**< Calibration General B-Side Registers, offset: 0x578 */ + __IO uint32_t CAL_GBR31; /**< Calibration General B-Side Registers, offset: 0x57C */ + __IO uint32_t CAL_GBR32; /**< Calibration General B-Side Registers, offset: 0x580 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential or 12-bit single-ended resolution supported. + * 0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for + * selecting the resolution of conversions for the associated command. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Not supported + * 0b1..Supported. CMDLn[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multiple Vref Implemented + * 0b0..Single VREFH input supported. + * 0b1..Multiple VREFH inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Not supported. + * 0b001..Supported with one-bit CSCALE control field. + * 0b110..Supported with six-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. + * 0b1..Range control required. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single-Ended Outputs Supported + * 0b0..One + * 0b1..Two + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..One + * 0b010..Two + * 0b011..Three + * 0b100..Four + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..2 + * 0b00000100..4 + * 0b00001000..8 + * 0b00010000..16 + * 0b00100000..32 + * 0b01000000..64 + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low-power mode. + * 0b1..ADC is disabled in low-power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request made. + * 0b1..Request has been made. + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgment. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or has not been run. + * 0b1..ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..ADC is idle. There are no pending triggers to service and no active commands are being processed. + * 0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..All disabled + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..All enabled + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..Current conversion is aborted and the new command specified by the trigger is started. + * 0b01..Current command is stopped after completing the current conversion. If averaging is enabled, the + * averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced. + * 0b10..Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b0x..Low power + * 0b1x..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Option 1 + * 0b01..Option 2 + * 0b10..Option 3 + * 0b11.. + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Not automatically resumed or restarted + * 0b1..Automatically resumed or restarted + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequence automatically restarted. + * 0b1..Trigger sequence resumed from the command that was executed prior to the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High-Priority Trigger Exception Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power-up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost + * of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this + * initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - Pause Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high-priority exception. + * 0b0001..Trigger 0 has been interrupted by a high-priority exception. + * 0b0010..Trigger 1 has been interrupted by a high-priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high-priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination for Channel A + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination for Channel B + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level. + * 0b11..Lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (4U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended mode. Only A-side channel is converted. + * 0b01..Single-Ended mode. Only B-side channel is converted. + * 0b10..Differential mode. A-B. + * 0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) + +#define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) +#define ADC_CMDL_ALTB_ADCH_SHIFT (16U) +/*! ALTB_ADCH - Alternate Channel B Input Channel Select + * 0b00000..Select CH0B + * 0b00001..Select CH1B + * 0b00010..Select CH2B + * 0b00011..Select CH3B + * 0b00100-0b11101..Select corresponding channel CHnB + * 0b11110..Select CH30B + * 0b11111..Select CH31B + */ +#define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) + +#define ADC_CMDL_ALTBEN_MASK (0x200000U) +#define ADC_CMDL_ALTBEN_SHIFT (21U) +/*! ALTBEN - Alternate Channel B Select Enable + * 0b0..ALTBEN_ADCH disabled. Channel-A and Channel-B inputs are selected based on ADCH settings. + * 0b1..ALTBEN_ADCH enabled. Channel-A inputs are selected by ADCH setting and Channel-B inputs are selected by ALTB_ADCH setting. + */ +#define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Disabled + * 0b01.. + * 0b10..Enabled. Store on true. + * 0b11..Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion Before Execution + * 0b0..Command executes automatically. + * 0b1..Active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..5.5 ADCK cycles + * 0b010..7.5 ADCK cycles + * 0b011..11.5 ADCK cycles + * 0b100..19.5 ADCK cycles + * 0b101..35.5 ADCK cycles + * 0b110..67.5 ADCK cycles + * 0b111..131.5 ADCK cycles + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes one time. + * 0b0001..Loop one time. Command executes two times. + * 0b0010..Loop two times. Command executes three times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..CMD1 + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..CMD15 + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (15U) + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 + * 0b01..Trigger source 1 + * 0b10..Trigger source 2 + * 0b11..Trigger source 3 + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state, + * prior to the storage of an ADC conversion result into a RESFIFO buffer. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO contains data. FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR0 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR0_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR1 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK (0xFFFU) +#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR1_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR2 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR2_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR3 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR3_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR4 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR4_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR5 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR5_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR6 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR6_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR7 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR7_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR8 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR8_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR9 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR9_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR10 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR10_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR11 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR11_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR12 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR12_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR13 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR13_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR14 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR14_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR15 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR15_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR16 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR16_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR17 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR17_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR18 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR18_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR19 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR19_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR20 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR20_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR21 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR21_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR22 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR22_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR23 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR23_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR24 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR24_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR25 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR25_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR26 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR26_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR27 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR27_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR28 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR28_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR29 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR29_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR30 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR30_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR31 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR31_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR32 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR32_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR0 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR0_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR0_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR0_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR1 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR1_CAL_GBR_VAL_MASK (0xFFFU) +#define ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR1_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR1_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR2 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR2_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR2_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR2_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR3 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR3_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR3_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR3_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR4 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR4_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR4_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR4_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR5 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR5_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR5_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR5_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR6 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR6_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR6_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR6_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR7 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR7_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR7_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR7_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR8 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR8_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR8_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR8_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR9 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR9_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR9_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR9_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR10 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR10_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR10_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR10_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR11 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR11_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR11_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR11_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR12 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR12_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR12_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR12_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR13 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR13_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR13_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR13_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR14 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR14_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR14_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR14_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR15 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR15_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR15_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR15_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR16 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR16_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR16_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR16_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR17 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR17_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR17_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR17_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR18 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR18_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR18_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR18_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR19 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR19_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR19_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR19_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR20 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR20_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR20_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR20_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR21 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR21_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR21_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR21_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR22 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR22_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR22_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR22_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR23 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR23_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR23_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR23_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR24 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR24_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR24_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR24_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR25 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR25_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR25_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR25_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR26 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR26_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR26_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR26_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR27 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR27_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR27_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR27_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR28 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR28_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR28_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR28_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR29 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR29_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR29_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR29_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR30 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR30_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR30_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR30_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR31 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR31_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR31_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR31_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR32 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR32_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR32_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR32_CAL_GBR_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHBSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Peripheral_Access_Layer AHBSC Peripheral Access Layer + * @{ + */ + +/** AHBSC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t FLASH00_MEM_RULE[4]; /**< Flash Memory Rule, array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t FLASH02_MEM_RULE; /**< Flash Memory Rule, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t FLASH03_MEM_RULE; /**< Flash Memory Rule, offset: 0x40 */ + uint8_t RESERVED_3[28]; + __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RAMX_MEM_RULE[3]; /**< RAMX Memory Rule, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t RAMA_MEM_RULE; /**< RAMA Memory Rule 0, offset: 0xA0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RAMB_MEM_RULE; /**< RAMB Memory Rule, offset: 0xC0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t RAMC_MEM_RULE[2]; /**< RAMC Memory Rule, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t RAMD_MEM_RULE[2]; /**< RAMD Memory Rule, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t RAME_MEM_RULE[2]; /**< RAME Memory Rule, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x1A0 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x1A4 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x1A8 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x1AC */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x1B0 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x1B4 */ + uint8_t RESERVED_11[4]; + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x1BC */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE0; /**< AIPS Bridge Group 0 Memory Rule 0, offset: 0x1C0 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE1; /**< AIPS Bridge Group 0 Memory Rule 1, offset: 0x1C4 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE2; /**< AIPS Bridge Group 0 Memory Rule 2, offset: 0x1C8 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE3; /**< AIPS Bridge Group 0 Memory Rule 3, offset: 0x1CC */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 0, offset: 0x1D0 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 1, offset: 0x1D4 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 2, offset: 0x1D8 */ + uint8_t RESERVED_12[4]; + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x1E0 */ + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x1E4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 0, offset: 0x1F0 */ + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 1, offset: 0x1F4 */ + uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 2, offset: 0x1F8 */ + uint8_t RESERVED_14[4]; + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE0; /**< AIPS Bridge Group 2 Rule 0, offset: 0x200 */ + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE1; /**< AIPS Bridge Group 2 Memory Rule 1, offset: 0x204 */ + uint8_t RESERVED_15[24]; + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE0; /**< AIPS Bridge Group 3 Rule 0, offset: 0x220 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE1; /**< AIPS Bridge Group 3 Memory Rule 1, offset: 0x224 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE2; /**< AIPS Bridge Group 3 Rule 2, offset: 0x228 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE3; /**< AIPS Bridge Group 3 Rule 3, offset: 0x22C */ + uint8_t RESERVED_16[16]; + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE0; /**< AIPS Bridge Group 4 Rule 0, offset: 0x240 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE1; /**< AIPS Bridge Group 4 Rule 1, offset: 0x244 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE2; /**< AIPS Bridge Group 4 Rule 2, offset: 0x248 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE3; /**< AIPS Bridge Group 4 Rule 3, offset: 0x24C */ + __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0; /**< AHB Secure Control Peripheral Rule 0, offset: 0x250 */ + uint8_t RESERVED_17[2988]; + __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ + __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ + uint8_t RESERVED_18[124]; + __IO uint32_t SEC_GPIO_MASK[2]; /**< GPIO Mask for Port 0..GPIO Mask for Port 1, array offset: 0xF80, array step: 0x4 */ + uint8_t RESERVED_19[72]; + __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ + uint8_t RESERVED_20[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */ + uint8_t RESERVED_21[8]; + __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ +} AHBSC_Type; + +/* ---------------------------------------------------------------------------- + -- AHBSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Register_Masks AHBSC Register Masks + * @{ + */ + +/*! @name FLASH00_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH00_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_FLASH00_MEM_RULE */ +#define AHBSC_FLASH00_MEM_RULE_COUNT (4U) + +/*! @name FLASH02_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH02_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE3_MASK) +/*! @} */ + +/*! @name FLASH03_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH03_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name ROM_MEM_RULE - ROM Memory Rule */ +/*! @{ */ + +#define AHBSC_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE0_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE1_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE2_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE3_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE4_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE5_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE6_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_ROM_MEM_RULE */ +#define AHBSC_ROM_MEM_RULE_COUNT (4U) + +/*! @name RAMX_MEM_RULE0_RAMX_MEM_RULE - RAMX Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_COUNT (3U) + +/*! @name RAMA_MEM_RULE - RAMA Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_RAMA_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMA_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMA_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMA_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMA_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMA_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMA_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMA_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMA_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMB_MEM_RULE - RAMB Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMB_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMB_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMB_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMB_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMB_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMB_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMB_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMB_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMB_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMC_MEM_RULE - RAMC Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMC_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMC_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMC_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMC_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMC_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMC_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMC_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMC_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMC_MEM_RULE */ +#define AHBSC_RAMC_MEM_RULE_COUNT (2U) + +/*! @name RAMD_MEM_RULE - RAMD Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMD_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMD_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMD_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMD_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMD_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMD_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMD_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMD_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMD_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMD_MEM_RULE */ +#define AHBSC_RAMD_MEM_RULE_COUNT (2U) + +/*! @name RAME_MEM_RULE - RAME Memory Rule */ +/*! @{ */ + +#define AHBSC_RAME_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAME_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAME_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAME_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAME_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAME_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAME_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAME_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAME_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAME_MEM_RULE */ +#define AHBSC_RAME_MEM_RULE_COUNT (2U) + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) +/*! SYSCON - SYSCON + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) +/*! PINT0 - PINT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT (24U) +/*! INPUTMUX - INPUTMUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (16U) +/*! CTIMER0 - CTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (20U) +/*! CTIMER1 - CTIMER1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT (24U) +/*! CTIMER2 - CTIMER2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT (28U) +/*! CTIMER3 - CTIMER3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT (0U) +/*! CTIMER4 - CTIMER4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT (4U) +/*! FREQME0 - FREQME0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT (8U) +/*! UTCIK0 - UTCIK0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT (12U) +/*! MRT0 - MRT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT (16U) +/*! OSTIMER0 - OSTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT (24U) +/*! WWDT0 - WWDT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT (28U) +/*! WWDT1 - WWDT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT (12U) +/*! CACHE64_POLSEL0 - CACHE64_POLSEL0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT (4U) +/*! I3C0 - I3C0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT (8U) +/*! I3C1 - I3C1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT (20U) +/*! GDET - GDET + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT (24U) +/*! ITRC - ITRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (12U) +/*! PKC - PKC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT (16U) +/*! PUF_ALIAS0 - PUF_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT (20U) +/*! PUF_ALIAS1 - PUF_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT (24U) +/*! PUF_ALIAS2 - PUF_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT (28U) +/*! PUF_ALIAS3 - PUF_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT (8U) +/*! COOLFLUX - COOLFLUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT (12U) +/*! SMARTDMA - SmartDMA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT (16U) +/*! PLU - PLU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE0 - AIPS Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT (0U) +/*! GPIO5_ALIAS0 - GPIO5_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT (4U) +/*! GPIO5_ALIAS1 - GPIO5_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT (8U) +/*! PORT5 - PORT5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT (12U) +/*! FMU0 - FMU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT (16U) +/*! SCG0 - SCG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT (20U) +/*! SPC0 - SPC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT (24U) +/*! WUU0 - WUU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE1 - AIPS Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT (8U) +/*! LPTMR0 - LPTMR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT (12U) +/*! LPTMR1 - LPTMR1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT (16U) +/*! RTC - RTC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT (24U) +/*! FMU_TEST - FMU_TEST + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE2 - AIPS Bridge Group 0 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT (0U) +/*! TSI - TSI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT (8U) +/*! CMP1 - CMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT (12U) +/*! CMP2 - CMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT (16U) +/*! ELS - ELS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT (20U) +/*! ELS_ALIAS1 - ELS_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT (24U) +/*! ELS_ALIAS2 - ELS_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT (28U) +/*! ELS_ALIAS3 - ELS_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE3 - AIPS Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT (0U) +/*! DIGTMP - DIGTMP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT (4U) +/*! VBAT - VBAT + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT (8U) +/*! TRNG - TRNG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT (12U) +/*! EIM0 - EIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT (16U) +/*! ERM0 - ERM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT (20U) +/*! INTM0 - INTM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT (4U) +/*! eDMA0_CH15 - eDMA0_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT (8U) +/*! SCT0 - SCT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT (12U) +/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT (16U) +/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT (20U) +/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT (24U) +/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT (28U) +/*! GPIO0_ALIAS0 - GPIO0_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT (0U) +/*! GPIO0_ALIAS1 - GPIO0_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT (4U) +/*! GPIO1_ALIAS0 - GPIO1_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT (8U) +/*! GPIO1_ALIAS1 - GPIO1_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT (12U) +/*! GPIO2_ALIAS0 - GPIO2_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT (16U) +/*! GPIO2_ALIAS1 - GPIO2_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT (20U) +/*! GPIO3_ALIAS0 - GPIO3_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT (24U) +/*! GPIO3_ALIAS1 - GPIO3_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT (28U) +/*! GPIO4_ALIAS0 - GPIO4_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT (0U) +/*! GPIO4_ALIAS1 - GPIO4_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE0 - AIPS Bridge Group 1 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT (0U) +/*! eDMA0_MP - eDMA0_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT (4U) +/*! eDMA0_CH0 - eDMA0_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT (8U) +/*! eDMA0_CH1 - eDMA0_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT (12U) +/*! eDMA0_CH2 - eDMA0_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT (16U) +/*! eDMA0_CH3 - FLEXSPI0 Registers + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT (20U) +/*! eDMA0_CH4 - eDMA0_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT (24U) +/*! eDMA0_CH5 - eDMA0_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT (28U) +/*! eDMA0_CH6 - eDMA0_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE1 - AIPS Bridge Group 1 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT (0U) +/*! eDMA0_CH7 - eDMA0_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT (4U) +/*! eDMA0_CH8 - eDMA0_CH8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT (8U) +/*! eDMA0_CH9 - eDMA0_CH9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT (12U) +/*! eDMA0_CH10 - eDMA0_CH10 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT (16U) +/*! eDMA0_CH11 - FLEXSPI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT (20U) +/*! eDMA0_CH12 - eDMA0_CH12 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT (24U) +/*! eDMA0_CH13 - eDMA0_CH13 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT (28U) +/*! eDMA0_CH14 - eDMA0_CH14 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT (4U) +/*! eDMA1_CH15 - eDMA1_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT (8U) +/*! SEMA42 - SEMA42 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT (12U) +/*! MAILBOX - MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT (16U) +/*! PKC_RAM - PKC_RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT (20U) +/*! FLEXCOMM4 - FLEXCOMM4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT (24U) +/*! FLEXCOMM5 - FLEXCOMM5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT (28U) +/*! FLEXCOMM6 - FLEXCOMM6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT (0U) +/*! FLEXCOMM7 - FLEXCOMM7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT (4U) +/*! FLEXCOMM8 - FLEXCOMM8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT (8U) +/*! FLEXCOMM9 - FLEXCOMM9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT (12U) +/*! USB_FS_OTG_RAM - USB FS OTG RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT (16U) +/*! CDOG0 - CDOG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT (20U) +/*! CDOG1 - CDOG1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT (24U) +/*! DEBUG_MAILBOX - DEBUG_MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT (28U) +/*! NPU - NPU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE0 - AIPS Bridge Group 2 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT (0U) +/*! eDMA1_MP - eDMA1_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT (4U) +/*! eDMA1_CH0 - eDMA1_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT (8U) +/*! eDMA1_CH1 - eDMA1_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT (12U) +/*! eDMA1_CH2 - eDMA1_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT (16U) +/*! eDMA1_CH3 - eDMA1_CH3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT (20U) +/*! eDMA1_CH4 - eDMA1_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT (24U) +/*! eDMA1_CH5 - eDMA1_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT (28U) +/*! eDMA1_CH6 - eDMA1_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE1 - AIPS Bridge Group 2 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT (0U) +/*! eDMA1_CH7 - eDMA1_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE0 - AIPS Bridge Group 3 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT (0U) +/*! EWM0 - EWM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT (4U) +/*! LPCAC - LPCAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT (8U) +/*! FLEXSPI_CMX - FLEXSPI_CMX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT (20U) +/*! SFA - SFA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT (28U) +/*! MBC - MBC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE1 - AIPS Bridge Group 3 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT (0U) +/*! FLEXSPI - FLEXSPI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT (4U) +/*! OTPC - OTPC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT (12U) +/*! CRC - CRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT (16U) +/*! NPX - NPX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT (24U) +/*! PWM - PWM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT (28U) +/*! QDC - QDC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE2 - AIPS Bridge Group 3 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT (0U) +/*! PWM1 - PWM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT (4U) +/*! QDC1 - QDC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT (8U) +/*! EVTG - EVTG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT (16U) +/*! CAN0_RULE0 - CAN0 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT (20U) +/*! CAN0_RULE1 - CAN0 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT (24U) +/*! CAN0_RULE2 - CAN0 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT (28U) +/*! CAN0_RULE3 - CAN0 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE3 - AIPS Bridge Group 3 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT (0U) +/*! CAN1_RULE0 - CAN1 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT (4U) +/*! CAN1_RULE1 - CAN1 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT (8U) +/*! CAN1_RULE2 - CAN1 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT (12U) +/*! CAN1_RULE3 - CAN1 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT (16U) +/*! USBDCD - USBDCD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT (20U) +/*! USBFS - USBFS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE0 - AIPS Bridge Group 4 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK (0xFU) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT (0U) +/*! ENET - ENET + * 0b0000..Non-secure and non-privilege user access allowed + * 0b0001..Non-secure and privilege access allowed + * 0b0010..Secure and non-privilege user access allowed + * 0b0011..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT (12U) +/*! EMVSIM0 - EMVSIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT (16U) +/*! EMVSIM1 - EMVSIM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT (20U) +/*! FLEXIO - FLEXIO + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT (24U) +/*! SAI0 - SAI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT (28U) +/*! SAI1 - SAI1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE1 - AIPS Bridge Group 4 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT (0U) +/*! SINC0 - SINC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT (4U) +/*! uSDHC0 - uSDHC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT (8U) +/*! USBHSPHY - USBHSPHY + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT (12U) +/*! USBHS - USBHS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT (16U) +/*! MICD - MICD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT (20U) +/*! ADC0 - ADC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT (24U) +/*! ADC1 - ADC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT (28U) +/*! DAC0 - DAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE2 - AIPS Bridge Group 4 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT (0U) +/*! OPAMP0 - OPAMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT (4U) +/*! VREF - VREF + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT (8U) +/*! DAC - DAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT (12U) +/*! OPAMP1 - OPAMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT (16U) +/*! HPDAC0 - HPDAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT (20U) +/*! OPAMP2 - OPAMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT (24U) +/*! PORT0 - PORT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT (28U) +/*! PORT1 - PORT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE3 - AIPS Bridge Group 4 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT (0U) +/*! PORT2 - PORT2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT (4U) +/*! PORT3 - PORT3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT (8U) +/*! PORT4 - PORT4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT (24U) +/*! MTR0 - MTR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT (28U) +/*! ATX0 - ATX0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK) +/*! @} */ + +/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) + +/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator + * 0b0..Read access + * 0b1..Write access + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access + * 0b0..Code + * 0b1..Data + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - Security violation master number + * 0b00000..M33 Code + * 0b00001..M33 System + * 0b00011..SMARTDMA Instruction + * 0b00101..SMARTDMA Data + * 0b00110..eDMA0 + * 0b00111..eDMA1 + * 0b01000..PKC + * 0b01001..ELS S50 + * 0b01010..PKC M0 + * 0b01011..NPU Operands + * 0b01100..DSP Instruction + * 0b01101..DSPX + * 0b01110..DSPY + * 0b10000..NPU Data + * 0b10010..Ethernet + * 0b10011..USB HS + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) + +/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) +/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) +/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) +/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) +/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) +/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) +/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) +/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 1 */ +/*! @{ */ + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (2U) + +/*! @name MASTER_SEC_LEVEL - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PKC_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - Master SEC Level Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master SEC Level Antipol Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */ +/*! @{ */ + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - LOCK_NS_VTOR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 + * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - LOCK_NS_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 + * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - LOCK_S_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - LOCK_SAU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_SAU is 1 + * 0b10..CM33 (CPU0) LOCK_SAU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK + * 0b00..Reserved + * 0b01..CM33_LOCK_REG_LOCK is 1 + * 0b10..CM33_LOCK_REG_LOCK is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of secure mode access. + * 0b10..Disables the privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of non-secure mode access. + * 0b10..Disables the privilege checking of non-secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master can access memories and peripherals at the same level or below that level. + * 0b10..Master can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - Secure Control */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of secure mode access. + * 0b10..Disables privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of non-secure mode access. + * 0b10..Disables privilege checking of non-secure mode access is disabled. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level + * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHBSC_Register_Masks */ + + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group AHBSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[32]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[21]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[12]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[7]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[32]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[4]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (32U) + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (32U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x500D8000u) + /** Peripheral CAN1 base address */ + #define CAN1_BASE_NS (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Peripheral CAN1 base pointer */ + #define CAN1_NS ((CAN_Type *)CAN1_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS, CAN1_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS, CAN1_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[2]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[88]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[8]; + __I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */ + __IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SRAMDIS[1]; /**< SRAM Disable, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[12]; + __IO uint32_t SRAMRET[1]; /**< SRAM Retention, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_6[12]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ + uint8_t RESERVED_8[8]; + __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..No clock gating + * 0b0001..Core clock is gated + * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock not gated + * 0b0001..Core clock was gated + * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode + * *.. + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/* The count of CMC_PMCTRL */ +#define CMC_PMCTRL_COUNT (2U) + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CPU1_MASK (0x10000U) +#define CMC_SRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CPU1_SHIFT)) & CMC_SRS_CPU1_MASK) + +#define CMC_SRS_VBAT_MASK (0x1000000U) +#define CMC_SRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK) + +#define CMC_SRS_WWDT1_MASK (0x2000000U) +#define CMC_SRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT1_SHIFT)) & CMC_SRS_WWDT1_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_CDOG1_MASK (0x8000000U) +#define CMC_SRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) + +#define CMC_SRS_SECVIO_MASK (0x40000000U) +#define CMC_SRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK) + +#define CMC_SRS_TAMPER_MASK (0x80000000U) +#define CMC_SRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CPU1_MASK (0x10000U) +#define CMC_SSRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset not generated from CPU1 reset source. + * 0b1..Reset generated from CPU1 reset source. + */ +#define CMC_SSRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CPU1_SHIFT)) & CMC_SSRS_CPU1_MASK) + +#define CMC_SSRS_VBAT_MASK (0x1000000U) +#define CMC_SSRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK) + +#define CMC_SSRS_WWDT1_MASK (0x2000000U) +#define CMC_SSRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT1_SHIFT)) & CMC_SSRS_WWDT1_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_CDOG1_MASK (0x8000000U) +#define CMC_SSRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) + +#define CMC_SSRS_SECVIO_MASK (0x40000000U) +#define CMC_SSRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK) + +#define CMC_SSRS_TAMPER_MASK (0x80000000U) +#define CMC_SSRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CPU1_MASK (0x10000U) +#define CMC_SRIE_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CPU1_SHIFT)) & CMC_SRIE_CPU1_MASK) + +#define CMC_SRIE_VBAT_MASK (0x1000000U) +#define CMC_SRIE_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_VBAT_SHIFT)) & CMC_SRIE_VBAT_MASK) + +#define CMC_SRIE_WWDT1_MASK (0x2000000U) +#define CMC_SRIE_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT1_SHIFT)) & CMC_SRIE_WWDT1_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) + +#define CMC_SRIE_CDOG1_MASK (0x8000000U) +#define CMC_SRIE_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CPU1_MASK (0x10000U) +#define CMC_SRIF_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CPU1_SHIFT)) & CMC_SRIF_CPU1_MASK) + +#define CMC_SRIF_VBAT_MASK (0x1000000U) +#define CMC_SRIF_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_VBAT_SHIFT)) & CMC_SRIF_VBAT_MASK) + +#define CMC_SRIF_WWDT1_MASK (0x2000000U) +#define CMC_SRIF_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT1_SHIFT)) & CMC_SRIF_WWDT1_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) + +#define CMC_SRIF_CDOG1_MASK (0x8000000U) +#define CMC_SRIF_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK) +/*! @} */ + +/*! @name RSTCNT - Reset Count Register */ +/*! @{ */ + +#define CMC_RSTCNT_COUNT_MASK (0xFFU) +#define CMC_RSTCNT_COUNT_SHIFT (0U) +/*! COUNT - Count */ +#define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/* The count of CMC_MR */ +#define CMC_MR_COUNT (1U) + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/* The count of CMC_FM */ +#define CMC_FM_COUNT (1U) + +/*! @name SRAMDIS - SRAM Disable */ +/*! @{ */ + +#define CMC_SRAMDIS_DIS0_MASK (0x1U) +#define CMC_SRAMDIS_DIS0_SHIFT (0U) +/*! DIS0 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) + +#define CMC_SRAMDIS_DIS1_MASK (0x2U) +#define CMC_SRAMDIS_DIS1_SHIFT (1U) +/*! DIS1 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) + +#define CMC_SRAMDIS_DIS2_MASK (0x4U) +#define CMC_SRAMDIS_DIS2_SHIFT (2U) +/*! DIS2 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) + +#define CMC_SRAMDIS_DIS3_MASK (0x8U) +#define CMC_SRAMDIS_DIS3_SHIFT (3U) +/*! DIS3 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) + +#define CMC_SRAMDIS_DIS4_MASK (0x10U) +#define CMC_SRAMDIS_DIS4_SHIFT (4U) +/*! DIS4 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) + +#define CMC_SRAMDIS_DIS5_MASK (0x20U) +#define CMC_SRAMDIS_DIS5_SHIFT (5U) +/*! DIS5 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) + +#define CMC_SRAMDIS_DIS6_MASK (0x40U) +#define CMC_SRAMDIS_DIS6_SHIFT (6U) +/*! DIS6 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) + +#define CMC_SRAMDIS_DIS7_MASK (0x80U) +#define CMC_SRAMDIS_DIS7_SHIFT (7U) +/*! DIS7 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) + +#define CMC_SRAMDIS_DIS8_MASK (0x100U) +#define CMC_SRAMDIS_DIS8_SHIFT (8U) +/*! DIS8 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) + +#define CMC_SRAMDIS_DIS9_MASK (0x200U) +#define CMC_SRAMDIS_DIS9_SHIFT (9U) +/*! DIS9 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) + +#define CMC_SRAMDIS_DIS10_MASK (0x400U) +#define CMC_SRAMDIS_DIS10_SHIFT (10U) +/*! DIS10 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) + +#define CMC_SRAMDIS_DIS11_MASK (0x800U) +#define CMC_SRAMDIS_DIS11_SHIFT (11U) +/*! DIS11 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) + +#define CMC_SRAMDIS_DIS12_MASK (0x1000U) +#define CMC_SRAMDIS_DIS12_SHIFT (12U) +/*! DIS12 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) + +#define CMC_SRAMDIS_DIS13_MASK (0x2000U) +#define CMC_SRAMDIS_DIS13_SHIFT (13U) +/*! DIS13 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) + +#define CMC_SRAMDIS_DIS14_MASK (0x4000U) +#define CMC_SRAMDIS_DIS14_SHIFT (14U) +/*! DIS14 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) + +#define CMC_SRAMDIS_DIS15_MASK (0x8000U) +#define CMC_SRAMDIS_DIS15_SHIFT (15U) +/*! DIS15 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) + +#define CMC_SRAMDIS_DIS16_MASK (0x10000U) +#define CMC_SRAMDIS_DIS16_SHIFT (16U) +/*! DIS16 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) + +#define CMC_SRAMDIS_DIS17_MASK (0x20000U) +#define CMC_SRAMDIS_DIS17_SHIFT (17U) +/*! DIS17 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) + +#define CMC_SRAMDIS_DIS18_MASK (0x40000U) +#define CMC_SRAMDIS_DIS18_SHIFT (18U) +/*! DIS18 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) + +#define CMC_SRAMDIS_DIS19_MASK (0x80000U) +#define CMC_SRAMDIS_DIS19_SHIFT (19U) +/*! DIS19 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) + +#define CMC_SRAMDIS_DIS20_MASK (0x100000U) +#define CMC_SRAMDIS_DIS20_SHIFT (20U) +/*! DIS20 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) + +#define CMC_SRAMDIS_DIS21_MASK (0x200000U) +#define CMC_SRAMDIS_DIS21_SHIFT (21U) +/*! DIS21 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) + +#define CMC_SRAMDIS_DIS22_MASK (0x400000U) +#define CMC_SRAMDIS_DIS22_SHIFT (22U) +/*! DIS22 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) + +#define CMC_SRAMDIS_DIS23_MASK (0x800000U) +#define CMC_SRAMDIS_DIS23_SHIFT (23U) +/*! DIS23 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) + +#define CMC_SRAMDIS_DIS24_MASK (0x1000000U) +#define CMC_SRAMDIS_DIS24_SHIFT (24U) +/*! DIS24 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) + +#define CMC_SRAMDIS_DIS25_MASK (0x2000000U) +#define CMC_SRAMDIS_DIS25_SHIFT (25U) +/*! DIS25 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) + +#define CMC_SRAMDIS_DIS26_MASK (0x4000000U) +#define CMC_SRAMDIS_DIS26_SHIFT (26U) +/*! DIS26 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) + +#define CMC_SRAMDIS_DIS27_MASK (0x8000000U) +#define CMC_SRAMDIS_DIS27_SHIFT (27U) +/*! DIS27 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) + +#define CMC_SRAMDIS_DIS28_MASK (0x10000000U) +#define CMC_SRAMDIS_DIS28_SHIFT (28U) +/*! DIS28 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) + +#define CMC_SRAMDIS_DIS29_MASK (0x20000000U) +#define CMC_SRAMDIS_DIS29_SHIFT (29U) +/*! DIS29 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) + +#define CMC_SRAMDIS_DIS30_MASK (0x40000000U) +#define CMC_SRAMDIS_DIS30_SHIFT (30U) +/*! DIS30 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) + +#define CMC_SRAMDIS_DIS31_MASK (0x80000000U) +#define CMC_SRAMDIS_DIS31_SHIFT (31U) +/*! DIS31 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) +/*! @} */ + +/* The count of CMC_SRAMDIS */ +#define CMC_SRAMDIS_COUNT (1U) + +/*! @name SRAMRET - SRAM Retention */ +/*! @{ */ + +#define CMC_SRAMRET_RET0_MASK (0x1U) +#define CMC_SRAMRET_RET0_SHIFT (0U) +/*! RET0 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) + +#define CMC_SRAMRET_RET1_MASK (0x2U) +#define CMC_SRAMRET_RET1_SHIFT (1U) +/*! RET1 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) + +#define CMC_SRAMRET_RET2_MASK (0x4U) +#define CMC_SRAMRET_RET2_SHIFT (2U) +/*! RET2 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) + +#define CMC_SRAMRET_RET3_MASK (0x8U) +#define CMC_SRAMRET_RET3_SHIFT (3U) +/*! RET3 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) + +#define CMC_SRAMRET_RET4_MASK (0x10U) +#define CMC_SRAMRET_RET4_SHIFT (4U) +/*! RET4 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) + +#define CMC_SRAMRET_RET5_MASK (0x20U) +#define CMC_SRAMRET_RET5_SHIFT (5U) +/*! RET5 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) + +#define CMC_SRAMRET_RET6_MASK (0x40U) +#define CMC_SRAMRET_RET6_SHIFT (6U) +/*! RET6 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) + +#define CMC_SRAMRET_RET7_MASK (0x80U) +#define CMC_SRAMRET_RET7_SHIFT (7U) +/*! RET7 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) + +#define CMC_SRAMRET_RET8_MASK (0x100U) +#define CMC_SRAMRET_RET8_SHIFT (8U) +/*! RET8 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) + +#define CMC_SRAMRET_RET9_MASK (0x200U) +#define CMC_SRAMRET_RET9_SHIFT (9U) +/*! RET9 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) + +#define CMC_SRAMRET_RET10_MASK (0x400U) +#define CMC_SRAMRET_RET10_SHIFT (10U) +/*! RET10 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) + +#define CMC_SRAMRET_RET11_MASK (0x800U) +#define CMC_SRAMRET_RET11_SHIFT (11U) +/*! RET11 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) + +#define CMC_SRAMRET_RET12_MASK (0x1000U) +#define CMC_SRAMRET_RET12_SHIFT (12U) +/*! RET12 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) + +#define CMC_SRAMRET_RET13_MASK (0x2000U) +#define CMC_SRAMRET_RET13_SHIFT (13U) +/*! RET13 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) + +#define CMC_SRAMRET_RET14_MASK (0x4000U) +#define CMC_SRAMRET_RET14_SHIFT (14U) +/*! RET14 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) + +#define CMC_SRAMRET_RET15_MASK (0x8000U) +#define CMC_SRAMRET_RET15_SHIFT (15U) +/*! RET15 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) + +#define CMC_SRAMRET_RET16_MASK (0x10000U) +#define CMC_SRAMRET_RET16_SHIFT (16U) +/*! RET16 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) + +#define CMC_SRAMRET_RET17_MASK (0x20000U) +#define CMC_SRAMRET_RET17_SHIFT (17U) +/*! RET17 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) + +#define CMC_SRAMRET_RET18_MASK (0x40000U) +#define CMC_SRAMRET_RET18_SHIFT (18U) +/*! RET18 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) + +#define CMC_SRAMRET_RET19_MASK (0x80000U) +#define CMC_SRAMRET_RET19_SHIFT (19U) +/*! RET19 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) + +#define CMC_SRAMRET_RET20_MASK (0x100000U) +#define CMC_SRAMRET_RET20_SHIFT (20U) +/*! RET20 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) + +#define CMC_SRAMRET_RET21_MASK (0x200000U) +#define CMC_SRAMRET_RET21_SHIFT (21U) +/*! RET21 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) + +#define CMC_SRAMRET_RET22_MASK (0x400000U) +#define CMC_SRAMRET_RET22_SHIFT (22U) +/*! RET22 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) + +#define CMC_SRAMRET_RET23_MASK (0x800000U) +#define CMC_SRAMRET_RET23_SHIFT (23U) +/*! RET23 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) + +#define CMC_SRAMRET_RET24_MASK (0x1000000U) +#define CMC_SRAMRET_RET24_SHIFT (24U) +/*! RET24 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) + +#define CMC_SRAMRET_RET25_MASK (0x2000000U) +#define CMC_SRAMRET_RET25_SHIFT (25U) +/*! RET25 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) + +#define CMC_SRAMRET_RET26_MASK (0x4000000U) +#define CMC_SRAMRET_RET26_SHIFT (26U) +/*! RET26 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) + +#define CMC_SRAMRET_RET27_MASK (0x8000000U) +#define CMC_SRAMRET_RET27_SHIFT (27U) +/*! RET27 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) + +#define CMC_SRAMRET_RET28_MASK (0x10000000U) +#define CMC_SRAMRET_RET28_SHIFT (28U) +/*! RET28 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) + +#define CMC_SRAMRET_RET29_MASK (0x20000000U) +#define CMC_SRAMRET_RET29_SHIFT (29U) +/*! RET29 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) + +#define CMC_SRAMRET_RET30_MASK (0x40000000U) +#define CMC_SRAMRET_RET30_SHIFT (30U) +/*! RET30 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) + +#define CMC_SRAMRET_RET31_MASK (0x80000000U) +#define CMC_SRAMRET_RET31_SHIFT (31U) +/*! RET31 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) +/*! @} */ + +/* The count of CMC_SRAMRET */ +#define CMC_SRAMRET_COUNT (1U) + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) +/*! @} */ + +/*! @name BSR - BootROM Status Register */ +/*! @{ */ + +#define CMC_BSR_STAT_MASK (0xFFFFFFFFU) +#define CMC_BSR_STAT_SHIFT (0U) +/*! STAT - Provides status information written by the BootROM. */ +#define CMC_BSR_STAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK) +/*! @} */ + +/*! @name BLR - BootROM Lock Register */ +/*! @{ */ + +#define CMC_BLR_LOCK_MASK (0x7U) +#define CMC_BLR_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b010..BootROM Status and Lock Registers can be written + * 0b101..BootROM Status and Lock Registers cannot be written + */ +#define CMC_BLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif +/* Backward compatibility for CMC */ +#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) +#define CMC_SRAMDIS_DIS_SHIFT (0U) +/*! DIS - SRAM Disable */ +#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) + +#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) +#define CMC_SRAMRET_RET_SHIFT (0U) +/*! RET - SRAM Retention */ +#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) + + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DIGTMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer + * @{ + */ + +/** DIGTMP - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t LR; /**< Lock, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t TSR; /**< Tamper Seconds, offset: 0x20 */ + __IO uint32_t TER; /**< Tamper Enable, offset: 0x24 */ + __IO uint32_t PDR; /**< Pin Direction, offset: 0x28 */ + __IO uint32_t PPR; /**< Pin Polarity, offset: 0x2C */ + __IO uint32_t ATR[2]; /**< Active Tamper, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t PGFR[8]; /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */ +} DIGTMP_Type; + +/* ---------------------------------------------------------------------------- + -- DIGTMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define DIGTMP_CR_SWR_MASK (0x1U) +#define DIGTMP_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect + * 0b1..Perform a software reset + */ +#define DIGTMP_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK) + +#define DIGTMP_CR_DEN_MASK (0x2U) +#define DIGTMP_CR_DEN_SHIFT (1U) +/*! DEN - Digital Tamper Enable + * 0b0..Disables TDET clock and prescaler + * 0b1..Enables TDET clock and prescaler + */ +#define DIGTMP_CR_DEN(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK) + +#define DIGTMP_CR_TFSR_MASK (0x4U) +#define DIGTMP_CR_TFSR_SHIFT (2U) +/*! TFSR - Tamper Force System Reset + * 0b0..Do not force chip reset + * 0b1..Force chip reset + */ +#define DIGTMP_CR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK) + +#define DIGTMP_CR_UM_MASK (0x8U) +#define DIGTMP_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..No effect + * 0b1..Allows the clearing of interrupts + */ +#define DIGTMP_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK) + +#define DIGTMP_CR_ATCS0_MASK (0x10U) +#define DIGTMP_CR_ATCS0_SHIFT (4U) +/*! ATCS0 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS0_SHIFT)) & DIGTMP_CR_ATCS0_MASK) + +#define DIGTMP_CR_ATCS1_MASK (0x20U) +#define DIGTMP_CR_ATCS1_SHIFT (5U) +/*! ATCS1 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS1_SHIFT)) & DIGTMP_CR_ATCS1_MASK) + +#define DIGTMP_CR_DISTAM_MASK (0x100U) +#define DIGTMP_CR_DISTAM_SHIFT (8U) +/*! DISTAM - Disable Prescaler On Tamper + * 0b0..No effect + * 0b1..Automatically disables the prescaler after tamper detection + */ +#define DIGTMP_CR_DISTAM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK) + +#define DIGTMP_CR_DPR_MASK (0xFFFE0000U) +#define DIGTMP_CR_DPR_SHIFT (17U) +/*! DPR - Digital Tamper Prescaler */ +#define DIGTMP_CR_DPR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define DIGTMP_SR_DTF_MASK (0x1U) +#define DIGTMP_SR_DTF_SHIFT (0U) +/*! DTF - Digital Tamper Flag + * 0b0..TDET tampering not detected + * 0b1..TDET tampering detected + */ +#define DIGTMP_SR_DTF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK) + +#define DIGTMP_SR_TAF_MASK (0x2U) +#define DIGTMP_SR_TAF_SHIFT (1U) +/*! TAF - Tamper Acknowledge Flag + * 0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set. + * 0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set. + */ +#define DIGTMP_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK) + +#define DIGTMP_SR_TIF0_MASK (0x4U) +#define DIGTMP_SR_TIF0_SHIFT (2U) +/*! TIF0 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK) + +#define DIGTMP_SR_TIF1_MASK (0x8U) +#define DIGTMP_SR_TIF1_SHIFT (3U) +/*! TIF1 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK) + +#define DIGTMP_SR_TIF2_MASK (0x10U) +#define DIGTMP_SR_TIF2_SHIFT (4U) +/*! TIF2 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK) + +#define DIGTMP_SR_TIF3_MASK (0x20U) +#define DIGTMP_SR_TIF3_SHIFT (5U) +/*! TIF3 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK) + +#define DIGTMP_SR_TIF4_MASK (0x40U) +#define DIGTMP_SR_TIF4_SHIFT (6U) +/*! TIF4 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK) + +#define DIGTMP_SR_TIF5_MASK (0x80U) +#define DIGTMP_SR_TIF5_SHIFT (7U) +/*! TIF5 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK) + +#define DIGTMP_SR_TIF6_MASK (0x100U) +#define DIGTMP_SR_TIF6_SHIFT (8U) +/*! TIF6 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK) + +#define DIGTMP_SR_TIF7_MASK (0x200U) +#define DIGTMP_SR_TIF7_SHIFT (9U) +/*! TIF7 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK) + +#define DIGTMP_SR_TIF8_MASK (0x400U) +#define DIGTMP_SR_TIF8_SHIFT (10U) +/*! TIF8 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK) + +#define DIGTMP_SR_TIF9_MASK (0x800U) +#define DIGTMP_SR_TIF9_SHIFT (11U) +/*! TIF9 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK) + +#define DIGTMP_SR_TPF0_MASK (0x10000U) +#define DIGTMP_SR_TPF0_SHIFT (16U) +/*! TPF0 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK) + +#define DIGTMP_SR_TPF1_MASK (0x20000U) +#define DIGTMP_SR_TPF1_SHIFT (17U) +/*! TPF1 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK) + +#define DIGTMP_SR_TPF2_MASK (0x40000U) +#define DIGTMP_SR_TPF2_SHIFT (18U) +/*! TPF2 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK) + +#define DIGTMP_SR_TPF3_MASK (0x80000U) +#define DIGTMP_SR_TPF3_SHIFT (19U) +/*! TPF3 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK) + +#define DIGTMP_SR_TPF4_MASK (0x100000U) +#define DIGTMP_SR_TPF4_SHIFT (20U) +/*! TPF4 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK) + +#define DIGTMP_SR_TPF5_MASK (0x200000U) +#define DIGTMP_SR_TPF5_SHIFT (21U) +/*! TPF5 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK) + +#define DIGTMP_SR_TPF6_MASK (0x400000U) +#define DIGTMP_SR_TPF6_SHIFT (22U) +/*! TPF6 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF6_SHIFT)) & DIGTMP_SR_TPF6_MASK) + +#define DIGTMP_SR_TPF7_MASK (0x800000U) +#define DIGTMP_SR_TPF7_SHIFT (23U) +/*! TPF7 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF7_SHIFT)) & DIGTMP_SR_TPF7_MASK) +/*! @} */ + +/*! @name LR - Lock */ +/*! @{ */ + +#define DIGTMP_LR_CRL_MASK (0x10U) +#define DIGTMP_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK) + +#define DIGTMP_LR_SRL_MASK (0x20U) +#define DIGTMP_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK) + +#define DIGTMP_LR_LRL_MASK (0x40U) +#define DIGTMP_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK) + +#define DIGTMP_LR_IEL_MASK (0x80U) +#define DIGTMP_LR_IEL_SHIFT (7U) +/*! IEL - Interrupt Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_IEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK) + +#define DIGTMP_LR_TSL_MASK (0x100U) +#define DIGTMP_LR_TSL_SHIFT (8U) +/*! TSL - Tamper Seconds Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TSL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK) + +#define DIGTMP_LR_TEL_MASK (0x200U) +#define DIGTMP_LR_TEL_SHIFT (9U) +/*! TEL - Tamper Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK) + +#define DIGTMP_LR_PDL_MASK (0x400U) +#define DIGTMP_LR_PDL_SHIFT (10U) +/*! PDL - Pin Direction Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PDL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PDL_SHIFT)) & DIGTMP_LR_PDL_MASK) + +#define DIGTMP_LR_PPL_MASK (0x800U) +#define DIGTMP_LR_PPL_SHIFT (11U) +/*! PPL - Pin Polarity Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PPL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK) + +#define DIGTMP_LR_ATL0_MASK (0x1000U) +#define DIGTMP_LR_ATL0_SHIFT (12U) +/*! ATL0 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL0_SHIFT)) & DIGTMP_LR_ATL0_MASK) + +#define DIGTMP_LR_ATL1_MASK (0x2000U) +#define DIGTMP_LR_ATL1_SHIFT (13U) +/*! ATL1 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL1_SHIFT)) & DIGTMP_LR_ATL1_MASK) + +#define DIGTMP_LR_GFL0_MASK (0x10000U) +#define DIGTMP_LR_GFL0_SHIFT (16U) +/*! GFL0 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK) + +#define DIGTMP_LR_GFL1_MASK (0x20000U) +#define DIGTMP_LR_GFL1_SHIFT (17U) +/*! GFL1 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK) + +#define DIGTMP_LR_GFL2_MASK (0x40000U) +#define DIGTMP_LR_GFL2_SHIFT (18U) +/*! GFL2 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK) + +#define DIGTMP_LR_GFL3_MASK (0x80000U) +#define DIGTMP_LR_GFL3_SHIFT (19U) +/*! GFL3 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK) + +#define DIGTMP_LR_GFL4_MASK (0x100000U) +#define DIGTMP_LR_GFL4_SHIFT (20U) +/*! GFL4 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK) + +#define DIGTMP_LR_GFL5_MASK (0x200000U) +#define DIGTMP_LR_GFL5_SHIFT (21U) +/*! GFL5 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK) + +#define DIGTMP_LR_GFL6_MASK (0x400000U) +#define DIGTMP_LR_GFL6_SHIFT (22U) +/*! GFL6 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL6_SHIFT)) & DIGTMP_LR_GFL6_MASK) + +#define DIGTMP_LR_GFL7_MASK (0x800000U) +#define DIGTMP_LR_GFL7_SHIFT (23U) +/*! GFL7 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL7_SHIFT)) & DIGTMP_LR_GFL7_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define DIGTMP_IER_DTIE_MASK (0x1U) +#define DIGTMP_IER_DTIE_SHIFT (0U) +/*! DTIE - Digital Tamper Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK) + +#define DIGTMP_IER_TIIE0_MASK (0x4U) +#define DIGTMP_IER_TIIE0_SHIFT (2U) +/*! TIIE0 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK) + +#define DIGTMP_IER_TIIE1_MASK (0x8U) +#define DIGTMP_IER_TIIE1_SHIFT (3U) +/*! TIIE1 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK) + +#define DIGTMP_IER_TIIE2_MASK (0x10U) +#define DIGTMP_IER_TIIE2_SHIFT (4U) +/*! TIIE2 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK) + +#define DIGTMP_IER_TIIE3_MASK (0x20U) +#define DIGTMP_IER_TIIE3_SHIFT (5U) +/*! TIIE3 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK) + +#define DIGTMP_IER_TIIE4_MASK (0x40U) +#define DIGTMP_IER_TIIE4_SHIFT (6U) +/*! TIIE4 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK) + +#define DIGTMP_IER_TIIE5_MASK (0x80U) +#define DIGTMP_IER_TIIE5_SHIFT (7U) +/*! TIIE5 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK) + +#define DIGTMP_IER_TIIE6_MASK (0x100U) +#define DIGTMP_IER_TIIE6_SHIFT (8U) +/*! TIIE6 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK) + +#define DIGTMP_IER_TIIE7_MASK (0x200U) +#define DIGTMP_IER_TIIE7_SHIFT (9U) +/*! TIIE7 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK) + +#define DIGTMP_IER_TIIE8_MASK (0x400U) +#define DIGTMP_IER_TIIE8_SHIFT (10U) +/*! TIIE8 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK) + +#define DIGTMP_IER_TIIE9_MASK (0x800U) +#define DIGTMP_IER_TIIE9_SHIFT (11U) +/*! TIIE9 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK) + +#define DIGTMP_IER_TPIE0_MASK (0x10000U) +#define DIGTMP_IER_TPIE0_SHIFT (16U) +/*! TPIE0 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK) + +#define DIGTMP_IER_TPIE1_MASK (0x20000U) +#define DIGTMP_IER_TPIE1_SHIFT (17U) +/*! TPIE1 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK) + +#define DIGTMP_IER_TPIE2_MASK (0x40000U) +#define DIGTMP_IER_TPIE2_SHIFT (18U) +/*! TPIE2 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK) + +#define DIGTMP_IER_TPIE3_MASK (0x80000U) +#define DIGTMP_IER_TPIE3_SHIFT (19U) +/*! TPIE3 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK) + +#define DIGTMP_IER_TPIE4_MASK (0x100000U) +#define DIGTMP_IER_TPIE4_SHIFT (20U) +/*! TPIE4 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK) + +#define DIGTMP_IER_TPIE5_MASK (0x200000U) +#define DIGTMP_IER_TPIE5_SHIFT (21U) +/*! TPIE5 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK) + +#define DIGTMP_IER_TPIE6_MASK (0x400000U) +#define DIGTMP_IER_TPIE6_SHIFT (22U) +/*! TPIE6 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE6_SHIFT)) & DIGTMP_IER_TPIE6_MASK) + +#define DIGTMP_IER_TPIE7_MASK (0x800000U) +#define DIGTMP_IER_TPIE7_SHIFT (23U) +/*! TPIE7 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE7_SHIFT)) & DIGTMP_IER_TPIE7_MASK) +/*! @} */ + +/*! @name TSR - Tamper Seconds */ +/*! @{ */ + +#define DIGTMP_TSR_TTS_MASK (0xFFFFFFFFU) +#define DIGTMP_TSR_TTS_SHIFT (0U) +/*! TTS - Tamper Time Seconds */ +#define DIGTMP_TSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK) +/*! @} */ + +/*! @name TER - Tamper Enable */ +/*! @{ */ + +#define DIGTMP_TER_TIE0_MASK (0x4U) +#define DIGTMP_TER_TIE0_SHIFT (2U) +/*! TIE0 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK) + +#define DIGTMP_TER_TIE1_MASK (0x8U) +#define DIGTMP_TER_TIE1_SHIFT (3U) +/*! TIE1 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK) + +#define DIGTMP_TER_TIE2_MASK (0x10U) +#define DIGTMP_TER_TIE2_SHIFT (4U) +/*! TIE2 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK) + +#define DIGTMP_TER_TIE3_MASK (0x20U) +#define DIGTMP_TER_TIE3_SHIFT (5U) +/*! TIE3 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK) + +#define DIGTMP_TER_TIE4_MASK (0x40U) +#define DIGTMP_TER_TIE4_SHIFT (6U) +/*! TIE4 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK) + +#define DIGTMP_TER_TIE5_MASK (0x80U) +#define DIGTMP_TER_TIE5_SHIFT (7U) +/*! TIE5 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK) + +#define DIGTMP_TER_TIE6_MASK (0x100U) +#define DIGTMP_TER_TIE6_SHIFT (8U) +/*! TIE6 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK) + +#define DIGTMP_TER_TIE7_MASK (0x200U) +#define DIGTMP_TER_TIE7_SHIFT (9U) +/*! TIE7 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK) + +#define DIGTMP_TER_TIE8_MASK (0x400U) +#define DIGTMP_TER_TIE8_SHIFT (10U) +/*! TIE8 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK) + +#define DIGTMP_TER_TIE9_MASK (0x800U) +#define DIGTMP_TER_TIE9_SHIFT (11U) +/*! TIE9 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK) + +#define DIGTMP_TER_TPE0_MASK (0x10000U) +#define DIGTMP_TER_TPE0_SHIFT (16U) +/*! TPE0 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK) + +#define DIGTMP_TER_TPE1_MASK (0x20000U) +#define DIGTMP_TER_TPE1_SHIFT (17U) +/*! TPE1 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK) + +#define DIGTMP_TER_TPE2_MASK (0x40000U) +#define DIGTMP_TER_TPE2_SHIFT (18U) +/*! TPE2 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK) + +#define DIGTMP_TER_TPE3_MASK (0x80000U) +#define DIGTMP_TER_TPE3_SHIFT (19U) +/*! TPE3 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK) + +#define DIGTMP_TER_TPE4_MASK (0x100000U) +#define DIGTMP_TER_TPE4_SHIFT (20U) +/*! TPE4 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK) + +#define DIGTMP_TER_TPE5_MASK (0x200000U) +#define DIGTMP_TER_TPE5_SHIFT (21U) +/*! TPE5 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK) + +#define DIGTMP_TER_TPE6_MASK (0x400000U) +#define DIGTMP_TER_TPE6_SHIFT (22U) +/*! TPE6 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE6_SHIFT)) & DIGTMP_TER_TPE6_MASK) + +#define DIGTMP_TER_TPE7_MASK (0x800000U) +#define DIGTMP_TER_TPE7_SHIFT (23U) +/*! TPE7 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE7_SHIFT)) & DIGTMP_TER_TPE7_MASK) +/*! @} */ + +/*! @name PDR - Pin Direction */ +/*! @{ */ + +#define DIGTMP_PDR_TPD0_MASK (0x1U) +#define DIGTMP_PDR_TPD0_SHIFT (0U) +/*! TPD0 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD0_SHIFT)) & DIGTMP_PDR_TPD0_MASK) + +#define DIGTMP_PDR_TPD1_MASK (0x2U) +#define DIGTMP_PDR_TPD1_SHIFT (1U) +/*! TPD1 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD1_SHIFT)) & DIGTMP_PDR_TPD1_MASK) + +#define DIGTMP_PDR_TPD2_MASK (0x4U) +#define DIGTMP_PDR_TPD2_SHIFT (2U) +/*! TPD2 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD2_SHIFT)) & DIGTMP_PDR_TPD2_MASK) + +#define DIGTMP_PDR_TPD3_MASK (0x8U) +#define DIGTMP_PDR_TPD3_SHIFT (3U) +/*! TPD3 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD3_SHIFT)) & DIGTMP_PDR_TPD3_MASK) + +#define DIGTMP_PDR_TPD4_MASK (0x10U) +#define DIGTMP_PDR_TPD4_SHIFT (4U) +/*! TPD4 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD4_SHIFT)) & DIGTMP_PDR_TPD4_MASK) + +#define DIGTMP_PDR_TPD5_MASK (0x20U) +#define DIGTMP_PDR_TPD5_SHIFT (5U) +/*! TPD5 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD5_SHIFT)) & DIGTMP_PDR_TPD5_MASK) + +#define DIGTMP_PDR_TPD6_MASK (0x40U) +#define DIGTMP_PDR_TPD6_SHIFT (6U) +/*! TPD6 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD6_SHIFT)) & DIGTMP_PDR_TPD6_MASK) + +#define DIGTMP_PDR_TPD7_MASK (0x80U) +#define DIGTMP_PDR_TPD7_SHIFT (7U) +/*! TPD7 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD7_SHIFT)) & DIGTMP_PDR_TPD7_MASK) + +#define DIGTMP_PDR_TPOD0_MASK (0x10000U) +#define DIGTMP_PDR_TPOD0_SHIFT (16U) +/*! TPOD0 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD0_SHIFT)) & DIGTMP_PDR_TPOD0_MASK) + +#define DIGTMP_PDR_TPOD1_MASK (0x20000U) +#define DIGTMP_PDR_TPOD1_SHIFT (17U) +/*! TPOD1 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD1_SHIFT)) & DIGTMP_PDR_TPOD1_MASK) + +#define DIGTMP_PDR_TPOD2_MASK (0x40000U) +#define DIGTMP_PDR_TPOD2_SHIFT (18U) +/*! TPOD2 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD2_SHIFT)) & DIGTMP_PDR_TPOD2_MASK) + +#define DIGTMP_PDR_TPOD3_MASK (0x80000U) +#define DIGTMP_PDR_TPOD3_SHIFT (19U) +/*! TPOD3 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD3_SHIFT)) & DIGTMP_PDR_TPOD3_MASK) + +#define DIGTMP_PDR_TPOD4_MASK (0x100000U) +#define DIGTMP_PDR_TPOD4_SHIFT (20U) +/*! TPOD4 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD4_SHIFT)) & DIGTMP_PDR_TPOD4_MASK) + +#define DIGTMP_PDR_TPOD5_MASK (0x200000U) +#define DIGTMP_PDR_TPOD5_SHIFT (21U) +/*! TPOD5 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD5_SHIFT)) & DIGTMP_PDR_TPOD5_MASK) + +#define DIGTMP_PDR_TPOD6_MASK (0x400000U) +#define DIGTMP_PDR_TPOD6_SHIFT (22U) +/*! TPOD6 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD6_SHIFT)) & DIGTMP_PDR_TPOD6_MASK) + +#define DIGTMP_PDR_TPOD7_MASK (0x800000U) +#define DIGTMP_PDR_TPOD7_SHIFT (23U) +/*! TPOD7 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD7_SHIFT)) & DIGTMP_PDR_TPOD7_MASK) +/*! @} */ + +/*! @name PPR - Pin Polarity */ +/*! @{ */ + +#define DIGTMP_PPR_TPP0_MASK (0x1U) +#define DIGTMP_PPR_TPP0_SHIFT (0U) +/*! TPP0 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK) + +#define DIGTMP_PPR_TPP1_MASK (0x2U) +#define DIGTMP_PPR_TPP1_SHIFT (1U) +/*! TPP1 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK) + +#define DIGTMP_PPR_TPP2_MASK (0x4U) +#define DIGTMP_PPR_TPP2_SHIFT (2U) +/*! TPP2 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK) + +#define DIGTMP_PPR_TPP3_MASK (0x8U) +#define DIGTMP_PPR_TPP3_SHIFT (3U) +/*! TPP3 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK) + +#define DIGTMP_PPR_TPP4_MASK (0x10U) +#define DIGTMP_PPR_TPP4_SHIFT (4U) +/*! TPP4 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK) + +#define DIGTMP_PPR_TPP5_MASK (0x20U) +#define DIGTMP_PPR_TPP5_SHIFT (5U) +/*! TPP5 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK) + +#define DIGTMP_PPR_TPP6_MASK (0x40U) +#define DIGTMP_PPR_TPP6_SHIFT (6U) +/*! TPP6 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP6_SHIFT)) & DIGTMP_PPR_TPP6_MASK) + +#define DIGTMP_PPR_TPP7_MASK (0x80U) +#define DIGTMP_PPR_TPP7_SHIFT (7U) +/*! TPP7 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP7_SHIFT)) & DIGTMP_PPR_TPP7_MASK) + +#define DIGTMP_PPR_TPID0_MASK (0x10000U) +#define DIGTMP_PPR_TPID0_SHIFT (16U) +/*! TPID0 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK) + +#define DIGTMP_PPR_TPID1_MASK (0x20000U) +#define DIGTMP_PPR_TPID1_SHIFT (17U) +/*! TPID1 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK) + +#define DIGTMP_PPR_TPID2_MASK (0x40000U) +#define DIGTMP_PPR_TPID2_SHIFT (18U) +/*! TPID2 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK) + +#define DIGTMP_PPR_TPID3_MASK (0x80000U) +#define DIGTMP_PPR_TPID3_SHIFT (19U) +/*! TPID3 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK) + +#define DIGTMP_PPR_TPID4_MASK (0x100000U) +#define DIGTMP_PPR_TPID4_SHIFT (20U) +/*! TPID4 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK) + +#define DIGTMP_PPR_TPID5_MASK (0x200000U) +#define DIGTMP_PPR_TPID5_SHIFT (21U) +/*! TPID5 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK) + +#define DIGTMP_PPR_TPID6_MASK (0x400000U) +#define DIGTMP_PPR_TPID6_SHIFT (22U) +/*! TPID6 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID6_SHIFT)) & DIGTMP_PPR_TPID6_MASK) + +#define DIGTMP_PPR_TPID7_MASK (0x800000U) +#define DIGTMP_PPR_TPID7_SHIFT (23U) +/*! TPID7 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID7_SHIFT)) & DIGTMP_PPR_TPID7_MASK) +/*! @} */ + +/*! @name ATR - Active Tamper */ +/*! @{ */ + +#define DIGTMP_ATR_ATSR_MASK (0xFFFFU) +#define DIGTMP_ATR_ATSR_SHIFT (0U) +/*! ATSR - Active Tamper Shift Register */ +#define DIGTMP_ATR_ATSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATSR_SHIFT)) & DIGTMP_ATR_ATSR_MASK) + +#define DIGTMP_ATR_ATP_MASK (0xFFFF0000U) +#define DIGTMP_ATR_ATP_SHIFT (16U) +/*! ATP - Active Tamper Polynomial */ +#define DIGTMP_ATR_ATP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATP_SHIFT)) & DIGTMP_ATR_ATP_MASK) +/*! @} */ + +/* The count of DIGTMP_ATR */ +#define DIGTMP_ATR_COUNT (2U) + +/*! @name PGFR - Pin Glitch Filter */ +/*! @{ */ + +#define DIGTMP_PGFR_GFW_MASK (0x3FU) +#define DIGTMP_PGFR_GFW_SHIFT (0U) +/*! GFW - Glitch Filter Width */ +#define DIGTMP_PGFR_GFW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK) + +#define DIGTMP_PGFR_GFP_MASK (0x40U) +#define DIGTMP_PGFR_GFP_SHIFT (6U) +/*! GFP - Glitch Filter Prescaler + * 0b0..512 Hz prescaler clock + * 0b1..32.768 kHz clock + */ +#define DIGTMP_PGFR_GFP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK) + +#define DIGTMP_PGFR_GFE_MASK (0x80U) +#define DIGTMP_PGFR_GFE_SHIFT (7U) +/*! GFE - Glitch Filter Enable + * 0b0..Bypasses + * 0b1..Enables + */ +#define DIGTMP_PGFR_GFE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK) + +#define DIGTMP_PGFR_TPSW_MASK (0x300U) +#define DIGTMP_PGFR_TPSW_SHIFT (8U) +/*! TPSW - Tamper Pin Sample Width + * 0b00..Continuous monitoring, pin sampling disabled + * 0b01..2 cycles for pull enable and 1 cycle for input buffer enable + * 0b10..4 cycles for pull enable and 2 cycles for input buffer enable + * 0b11..8 cycles for pull enable and 4 cycles for input buffer enable + */ +#define DIGTMP_PGFR_TPSW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK) + +#define DIGTMP_PGFR_TPSF_MASK (0xC00U) +#define DIGTMP_PGFR_TPSF_SHIFT (10U) +/*! TPSF - Tamper Pin Sample Frequency + * 0b00..Every 8 cycles + * 0b01..Every 32 cycles + * 0b10..Every 128 cycles + * 0b11..Every 512 cycles + */ +#define DIGTMP_PGFR_TPSF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK) + +#define DIGTMP_PGFR_TPEX_MASK (0x30000U) +#define DIGTMP_PGFR_TPEX_SHIFT (16U) +/*! TPEX - Tamper Pin Expected + * 0b00..Zero/passive tamper + * 0b01..Active Tamper 0 output + * 0b10..Active Tamper 1 output + * 0b11..Active Tamper 0 output XORed with Active Tamper 1 output + */ +#define DIGTMP_PGFR_TPEX(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPEX_SHIFT)) & DIGTMP_PGFR_TPEX_MASK) + +#define DIGTMP_PGFR_TPE_MASK (0x1000000U) +#define DIGTMP_PGFR_TPE_SHIFT (24U) +/*! TPE - Tamper Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_PGFR_TPE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK) + +#define DIGTMP_PGFR_TPS_MASK (0x2000000U) +#define DIGTMP_PGFR_TPS_SHIFT (25U) +/*! TPS - Tamper Pull Select + * 0b0..Asserts + * 0b1..Negates + */ +#define DIGTMP_PGFR_TPS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK) +/*! @} */ + +/* The count of DIGTMP_PGFR */ +#define DIGTMP_PGFR_COUNT (8U) + + +/*! + * @} + */ /* end of group DIGTMP_Register_Masks */ + + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/*! + * @} + */ /* end of group DIGTMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Peripheral_Access_Layer DM Peripheral Access Layer + * @{ + */ + +/** DM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DM_Type; + +/* ---------------------------------------------------------------------------- + -- DM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Register_Masks DM Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DM_CSW_RESYNCH_REQ_MASK (0x1U) +#define DM_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DM_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_RESYNCH_REQ_SHIFT)) & DM_CSW_RESYNCH_REQ_MASK) + +#define DM_CSW_REQ_PENDING_MASK (0x2U) +#define DM_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DM_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_REQ_PENDING_SHIFT)) & DM_CSW_REQ_PENDING_MASK) + +#define DM_CSW_DBG_OR_ERR_MASK (0x4U) +#define DM_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No DBGMB Overrun error + * 0b1..DBGMB overrun error. A DBGMB overrun occurred. + */ +#define DM_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_DBG_OR_ERR_SHIFT)) & DM_CSW_DBG_OR_ERR_MASK) + +#define DM_CSW_AHB_OR_ERR_MASK (0x8U) +#define DM_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No AHB Overrun Error + * 0b1..AHB Overrun Error. An AHB overrun occurred. + */ +#define DM_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_AHB_OR_ERR_SHIFT)) & DM_CSW_AHB_OR_ERR_MASK) + +#define DM_CSW_SOFT_RESET_MASK (0x10U) +#define DM_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset */ +#define DM_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_SOFT_RESET_SHIFT)) & DM_CSW_SOFT_RESET_MASK) + +#define DM_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DM_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request */ +#define DM_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_CHIP_RESET_REQ_SHIFT)) & DM_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DM_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DM_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DM_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DM_REQUEST_REQUEST_SHIFT)) & DM_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DM_RETURN_RET_MASK (0xFFFFFFFFU) +#define DM_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DM_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DM_RETURN_RET_SHIFT)) & DM_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DM_ID_ID_MASK (0xFFFFFFFFU) +#define DM_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DM_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DM_ID_ID_SHIFT)) & DM_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DM_Register_Masks */ + + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/*! + * @} + */ /* end of group DM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[16]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[3776]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000, irregular array, not all indices are valid */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + }; + uint8_t RESERVED_1[4032]; + } CH[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFFFU) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (16U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (16U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (16U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (16U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0x1FU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_SEC_MASK (0x4000U) +#define DMA_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define DMA_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (16U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (16U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (16U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (16U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (16U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (16U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (16U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (16U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (16U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (16U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (16U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0xF00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (16U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (16U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Peripheral_Access_Layer DMA0_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA0_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA0_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Register_Masks DMA0_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Register_Masks */ + + +/* DMA0_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x50080000u) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE_NS (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x50081000u) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE_NS (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x50082000u) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE_NS (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x50083000u) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE_NS (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x50084000u) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE_NS (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x50085000u) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE_NS (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x50086000u) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE_NS (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x50087000u) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE_NS (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x50088000u) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE_NS (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x50089000u) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE_NS (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x5008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE_NS (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x5008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE_NS (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x5008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE_NS (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x5008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE_NS (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x5008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE_NS (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x5008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE_NS (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x50090000u) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE_NS (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE_NS) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS_NS { DMA0_TEE_ALIAS0_BASE_NS, DMA0_TEE_ALIAS1_BASE_NS, DMA0_TEE_ALIAS2_BASE_NS, DMA0_TEE_ALIAS3_BASE_NS, DMA0_TEE_ALIAS4_BASE_NS, DMA0_TEE_ALIAS5_BASE_NS, DMA0_TEE_ALIAS6_BASE_NS, DMA0_TEE_ALIAS7_BASE_NS, DMA0_TEE_ALIAS8_BASE_NS, DMA0_TEE_ALIAS9_BASE_NS, DMA0_TEE_ALIAS10_BASE_NS, DMA0_TEE_ALIAS11_BASE_NS, DMA0_TEE_ALIAS12_BASE_NS, DMA0_TEE_ALIAS13_BASE_NS, DMA0_TEE_ALIAS14_BASE_NS, DMA0_TEE_ALIAS15_BASE_NS, DMA0_TEE_ALIAS16_BASE_NS } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS_NS { DMA0_TEE_ALIAS0_NS, DMA0_TEE_ALIAS1_NS, DMA0_TEE_ALIAS2_NS, DMA0_TEE_ALIAS3_NS, DMA0_TEE_ALIAS4_NS, DMA0_TEE_ALIAS5_NS, DMA0_TEE_ALIAS6_NS, DMA0_TEE_ALIAS7_NS, DMA0_TEE_ALIAS8_NS, DMA0_TEE_ALIAS9_NS, DMA0_TEE_ALIAS10_NS, DMA0_TEE_ALIAS11_NS, DMA0_TEE_ALIAS12_NS, DMA0_TEE_ALIAS13_NS, DMA0_TEE_ALIAS14_NS, DMA0_TEE_ALIAS15_NS, DMA0_TEE_ALIAS16_NS } +#else + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } +#endif + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Peripheral_Access_Layer DMA1_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA1_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA1_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Register_Masks DMA1_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Register_Masks */ + + +/* DMA1_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x500A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE_NS (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x500A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE_NS (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x500A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE_NS (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x500A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE_NS (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x500A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE_NS (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x500A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE_NS (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x500A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE_NS (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x500A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE_NS (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x500A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE_NS (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE_NS) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS_NS { DMA1_TEE_ALIAS0_BASE_NS, DMA1_TEE_ALIAS1_BASE_NS, DMA1_TEE_ALIAS2_BASE_NS, DMA1_TEE_ALIAS3_BASE_NS, DMA1_TEE_ALIAS4_BASE_NS, DMA1_TEE_ALIAS5_BASE_NS, DMA1_TEE_ALIAS6_BASE_NS, DMA1_TEE_ALIAS7_BASE_NS, DMA1_TEE_ALIAS8_BASE_NS } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS_NS { DMA1_TEE_ALIAS0_NS, DMA1_TEE_ALIAS1_NS, DMA1_TEE_ALIAS2_NS, DMA1_TEE_ALIAS3_NS, DMA1_TEE_ALIAS4_NS, DMA1_TEE_ALIAS5_NS, DMA1_TEE_ALIAS6_NS, DMA1_TEE_ALIAS7_NS, DMA1_TEE_ALIAS8_NS } +#else + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } +#endif + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ + uint8_t RESERVED_1[56]; + __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ + __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ + uint8_t RESERVED_2[56]; + __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ + __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ + uint8_t RESERVED_3[56]; + __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ + __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ + uint8_t RESERVED_4[56]; + __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ + __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ + uint8_t RESERVED_5[56]; + __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ + __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ + uint8_t RESERVED_6[56]; + __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ + __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ + uint8_t RESERVED_7[56]; + __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ + __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ + uint8_t RESERVED_8[56]; + __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ + __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH8EN_MASK (0x800000U) +#define EIM_EICHEN_EICH8EN_SHIFT (23U) +/*! EICH8EN - Error Injection Channel 8 Enable + * 0b0..Error injection is disabled on Error Injection Channel 8 + * 0b1..Error injection is enabled on Error Injection Channel 8 + */ +#define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) + +#define EIM_EICHEN_EICH7EN_MASK (0x1000000U) +#define EIM_EICHEN_EICH7EN_SHIFT (24U) +/*! EICH7EN - Error Injection Channel 7 Enable + * 0b0..Error injection is disabled on Error Injection Channel 7 + * 0b1..Error injection is enabled on Error Injection Channel 7 + */ +#define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) + +#define EIM_EICHEN_EICH6EN_MASK (0x2000000U) +#define EIM_EICHEN_EICH6EN_SHIFT (25U) +/*! EICH6EN - Error Injection Channel 6 Enable + * 0b0..Error injection is disabled on Error Injection Channel 6 + * 0b1..Error injection is enabled on Error Injection Channel 6 + */ +#define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) + +#define EIM_EICHEN_EICH5EN_MASK (0x4000000U) +#define EIM_EICHEN_EICH5EN_SHIFT (26U) +/*! EICH5EN - Error Injection Channel 5 Enable + * 0b0..Error injection is disabled on Error Injection Channel 5 + * 0b1..Error injection is enabled on Error Injection Channel 5 + */ +#define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) + +#define EIM_EICHEN_EICH4EN_MASK (0x8000000U) +#define EIM_EICHEN_EICH4EN_SHIFT (27U) +/*! EICH4EN - Error Injection Channel 4 Enable + * 0b0..Error injection is disabled on Error Injection Channel 4 + * 0b1..Error injection is enabled on Error Injection Channel 4 + */ +#define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) + +#define EIM_EICHEN_EICH3EN_MASK (0x10000000U) +#define EIM_EICHEN_EICH3EN_SHIFT (28U) +/*! EICH3EN - Error Injection Channel 3 Enable + * 0b0..Error injection is disabled on Error Injection Channel 3 + * 0b1..Error injection is enabled on Error Injection Channel 3 + */ +#define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) + +#define EIM_EICHEN_EICH2EN_MASK (0x20000000U) +#define EIM_EICHEN_EICH2EN_SHIFT (29U) +/*! EICH2EN - Error Injection Channel 2 Enable + * 0b0..Error injection is disabled on Error Injection Channel 2 + * 0b1..Error injection is enabled on Error Injection Channel 2 + */ +#define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) + +#define EIM_EICHEN_EICH1EN_MASK (0x40000000U) +#define EIM_EICHEN_EICH1EN_SHIFT (30U) +/*! EICH1EN - Error Injection Channel 1 Enable + * 0b0..Error injection is disabled on Error Injection Channel 1 + * 0b1..Error injection is enabled on Error Injection Channel 1 + */ +#define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ +/*! @{ */ + +#define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ +/*! @{ */ + +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ +/*! @{ */ + +#define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ +/*! @{ */ + +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ +/*! @{ */ + +#define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ +/*! @{ */ + +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ +/*! @{ */ + +#define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ +/*! @{ */ + +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ +/*! @{ */ + +#define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ +/*! @{ */ + +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ +/*! @{ */ + +#define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ +/*! @{ */ + +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ +/*! @{ */ + +#define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0x80000000U) +#define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (31U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ +/*! @{ */ + +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ +/*! @{ */ + +#define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xF0000000U) +#define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (28U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ +/*! @{ */ + +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[4]; + __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ + __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ + uint8_t RESERVED_3[4]; + __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120 */ + __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124 */ + __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ + uint8_t RESERVED_4[4]; + __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130 */ + __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134 */ + __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ + uint8_t RESERVED_5[4]; + __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140 */ + __I uint32_t SYN4; /**< ERM Memory 4 Syndrome Register, offset: 0x144 */ + __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ + uint8_t RESERVED_9[8]; + __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184 */ + __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE7_MASK (0x4U) +#define ERM_CR0_ENCIE7_SHIFT (2U) +/*! ENCIE7 - ENCIE7 + * 0b0..Interrupt notification of Memory 7 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 7 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) + +#define ERM_CR0_ESCIE7_MASK (0x8U) +#define ERM_CR0_ESCIE7_SHIFT (3U) +/*! ESCIE7 - ESCIE7 + * 0b0..Interrupt notification of Memory 7 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 7 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) + +#define ERM_CR0_ENCIE6_MASK (0x40U) +#define ERM_CR0_ENCIE6_SHIFT (6U) +/*! ENCIE6 - ENCIE6 + * 0b0..Interrupt notification of Memory 6 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 6 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) + +#define ERM_CR0_ESCIE6_MASK (0x80U) +#define ERM_CR0_ESCIE6_SHIFT (7U) +/*! ESCIE6 - ESCIE6 + * 0b0..Interrupt notification of Memory 6 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 6 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) + +#define ERM_CR0_ENCIE5_MASK (0x400U) +#define ERM_CR0_ENCIE5_SHIFT (10U) +/*! ENCIE5 - ENCIE5 + * 0b0..Interrupt notification of Memory 5 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 5 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) + +#define ERM_CR0_ESCIE5_MASK (0x800U) +#define ERM_CR0_ESCIE5_SHIFT (11U) +/*! ESCIE5 - ESCIE5 + * 0b0..Interrupt notification of Memory 5 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 5 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) + +#define ERM_CR0_ENCIE4_MASK (0x4000U) +#define ERM_CR0_ENCIE4_SHIFT (14U) +/*! ENCIE4 - ENCIE4 + * 0b0..Interrupt notification of Memory 4 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 4 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) + +#define ERM_CR0_ESCIE4_MASK (0x8000U) +#define ERM_CR0_ESCIE4_SHIFT (15U) +/*! ESCIE4 - ESCIE4 + * 0b0..Interrupt notification of Memory 4 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 4 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) + +#define ERM_CR0_ENCIE3_MASK (0x40000U) +#define ERM_CR0_ENCIE3_SHIFT (18U) +/*! ENCIE3 - ENCIE3 + * 0b0..Interrupt notification of Memory 3 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 3 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) + +#define ERM_CR0_ESCIE3_MASK (0x80000U) +#define ERM_CR0_ESCIE3_SHIFT (19U) +/*! ESCIE3 - ESCIE3 + * 0b0..Interrupt notification of Memory 3 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 3 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) + +#define ERM_CR0_ENCIE2_MASK (0x400000U) +#define ERM_CR0_ENCIE2_SHIFT (22U) +/*! ENCIE2 - ENCIE2 + * 0b0..Interrupt notification of Memory 2 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 2 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) + +#define ERM_CR0_ESCIE2_MASK (0x800000U) +#define ERM_CR0_ESCIE2_SHIFT (23U) +/*! ESCIE2 - ESCIE2 + * 0b0..Interrupt notification of Memory 2 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 2 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name CR1 - ERM Configuration Register 1 */ +/*! @{ */ + +#define ERM_CR1_ENCIE9_MASK (0x4000000U) +#define ERM_CR1_ENCIE9_SHIFT (26U) +/*! ENCIE9 - ENCIE9 + * 0b0..Interrupt notification of Memory 9 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 9 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) + +#define ERM_CR1_ESCIE9_MASK (0x8000000U) +#define ERM_CR1_ESCIE9_SHIFT (27U) +/*! ESCIE9 - ESCIE9 + * 0b0..Interrupt notification of Memory 9 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 9 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) + +#define ERM_CR1_ENCIE8_MASK (0x40000000U) +#define ERM_CR1_ENCIE8_SHIFT (30U) +/*! ENCIE8 - ENCIE8 + * 0b0..Interrupt notification of Memory 8 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 8 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) + +#define ERM_CR1_ESCIE8_MASK (0x80000000U) +#define ERM_CR1_ESCIE8_SHIFT (31U) +/*! ESCIE8 - ESCIE8 + * 0b0..Interrupt notification of Memory 8 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 8 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE7_MASK (0x4U) +#define ERM_SR0_NCE7_SHIFT (2U) +/*! NCE7 - NCE7 + * 0b0..No non-correctable error event on Memory 7 detected. + * 0b1..Non-correctable error event on Memory 7 detected. + */ +#define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) + +#define ERM_SR0_SBC7_MASK (0x8U) +#define ERM_SR0_SBC7_SHIFT (3U) +/*! SBC7 - SBC7 + * 0b0..No single-bit correction event on Memory 7 detected. + * 0b1..Single-bit correction event on Memory 7 detected. + */ +#define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) + +#define ERM_SR0_NCE6_MASK (0x40U) +#define ERM_SR0_NCE6_SHIFT (6U) +/*! NCE6 - NCE6 + * 0b0..No non-correctable error event on Memory 6 detected. + * 0b1..Non-correctable error event on Memory 6 detected. + */ +#define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) + +#define ERM_SR0_SBC6_MASK (0x80U) +#define ERM_SR0_SBC6_SHIFT (7U) +/*! SBC6 - SBC6 + * 0b0..No single-bit correction event on Memory 6 detected. + * 0b1..Single-bit correction event on Memory 6 detected. + */ +#define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) + +#define ERM_SR0_NCE5_MASK (0x400U) +#define ERM_SR0_NCE5_SHIFT (10U) +/*! NCE5 - NCE5 + * 0b0..No non-correctable error event on Memory 5 detected. + * 0b1..Non-correctable error event on Memory 5 detected. + */ +#define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) + +#define ERM_SR0_SBC5_MASK (0x800U) +#define ERM_SR0_SBC5_SHIFT (11U) +/*! SBC5 - SBC5 + * 0b0..No single-bit correction event on Memory 5 detected. + * 0b1..Single-bit correction event on Memory 5 detected. + */ +#define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) + +#define ERM_SR0_NCE4_MASK (0x4000U) +#define ERM_SR0_NCE4_SHIFT (14U) +/*! NCE4 - NCE4 + * 0b0..No non-correctable error event on Memory 4 detected. + * 0b1..Non-correctable error event on Memory 4 detected. + */ +#define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) + +#define ERM_SR0_SBC4_MASK (0x8000U) +#define ERM_SR0_SBC4_SHIFT (15U) +/*! SBC4 - SBC4 + * 0b0..No single-bit correction event on Memory 4 detected. + * 0b1..Single-bit correction event on Memory 4 detected. + */ +#define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) + +#define ERM_SR0_NCE3_MASK (0x40000U) +#define ERM_SR0_NCE3_SHIFT (18U) +/*! NCE3 - NCE3 + * 0b0..No non-correctable error event on Memory 3 detected. + * 0b1..Non-correctable error event on Memory 3 detected. + */ +#define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) + +#define ERM_SR0_SBC3_MASK (0x80000U) +#define ERM_SR0_SBC3_SHIFT (19U) +/*! SBC3 - SBC3 + * 0b0..No single-bit correction event on Memory 3 detected. + * 0b1..Single-bit correction event on Memory 3 detected. + */ +#define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) + +#define ERM_SR0_NCE2_MASK (0x400000U) +#define ERM_SR0_NCE2_SHIFT (22U) +/*! NCE2 - NCE2 + * 0b0..No non-correctable error event on Memory 2 detected. + * 0b1..Non-correctable error event on Memory 2 detected. + */ +#define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) + +#define ERM_SR0_SBC2_MASK (0x800000U) +#define ERM_SR0_SBC2_SHIFT (23U) +/*! SBC2 - SBC2 + * 0b0..No single-bit correction event on Memory 2 detected. + * 0b1..Single-bit correction event on Memory 2 detected. + */ +#define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name SR1 - ERM Status Register 1 */ +/*! @{ */ + +#define ERM_SR1_NCE9_MASK (0x4000000U) +#define ERM_SR1_NCE9_SHIFT (26U) +/*! NCE9 - NCE9 + * 0b0..No non-correctable error event on Memory 9 detected. + * 0b1..Non-correctable error event on Memory 9 detected. + */ +#define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) + +#define ERM_SR1_SBC9_MASK (0x8000000U) +#define ERM_SR1_SBC9_SHIFT (27U) +/*! SBC9 - SBC9 + * 0b0..No single-bit correction event on Memory 9 detected. + * 0b1..Single-bit correction event on Memory 9 detected. + */ +#define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) + +#define ERM_SR1_NCE8_MASK (0x40000000U) +#define ERM_SR1_NCE8_SHIFT (30U) +/*! NCE8 - NCE8 + * 0b0..No non-correctable error event on Memory 8 detected. + * 0b1..Non-correctable error event on Memory 8 detected. + */ +#define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) + +#define ERM_SR1_SBC8_MASK (0x80000000U) +#define ERM_SR1_SBC8_SHIFT (31U) +/*! SBC8 - SBC8 + * 0b0..No single-bit correction event on Memory 8 detected. + * 0b1..Single-bit correction event on Memory 8 detected. + */ +#define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name EAR1 - ERM Memory 1 Error Address Register */ +/*! @{ */ + +#define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR1_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) +/*! @} */ + +/*! @name SYN1 - ERM Memory 1 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN1_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN1_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + +/*! @name EAR2 - ERM Memory 2 Error Address Register */ +/*! @{ */ + +#define ERM_EAR2_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR2_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK) +/*! @} */ + +/*! @name SYN2 - ERM Memory 2 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN2_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN2_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) +/*! @} */ + +/*! @name EAR3 - ERM Memory 3 Error Address Register */ +/*! @{ */ + +#define ERM_EAR3_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR3_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK) +/*! @} */ + +/*! @name SYN3 - ERM Memory 3 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN3_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN3_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) +/*! @} */ + +/*! @name EAR4 - ERM Memory 4 Error Address Register */ +/*! @{ */ + +#define ERM_EAR4_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR4_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK) +/*! @} */ + +/*! @name SYN4 - ERM Memory 4 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN4_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN4_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN4_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN4_SYNDROME_SHIFT)) & ERM_SYN4_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) +/*! @} */ + +/*! @name SYN8 - ERM Memory 8 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN8_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN8_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EVTG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Peripheral_Access_Layer EVTG Peripheral Access Layer + * @{ + */ + +/** EVTG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT01; /**< AOI0 Boolean Function Term 0 and 1 Configuration, array offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT23; /**< AOI0 Boolean Function Term 2 and 3 Configuration, array offset: 0x2, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT01; /**< AOI1 Boolean Function Term 0 and 1 Configuration, array offset: 0x4, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT23; /**< AOI1 Boolean Function Term 2 and 3 Configuration, array offset: 0x6, array step: 0x10 */ + uint8_t RESERVED_0[2]; + __IO uint16_t EVTG_CTRL; /**< Control and Status, array offset: 0xA, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_FILT; /**< AOI0 Output Filter, array offset: 0xC, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_FILT; /**< AOI1 Output Filter, array offset: 0xE, array step: 0x10 */ + } EVTG_INST[4]; +} EVTG_Type; + +/* ---------------------------------------------------------------------------- + -- EVTG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Register_Masks EVTG Register Masks + * @{ + */ + +/*! @name EVTG_INST_EVTG_AOI0_BFT01 - AOI0 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_BFT23 - AOI0 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT01 - AOI1 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT23 - AOI1 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_CTRL - Control and Status */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK (0x1U) +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT (0U) +/*! FF_INIT - Flip flop Initial Value Configuration + * 0b0..0 + * 0b1..1 + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK (0x2U) +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT (1U) +/*! INIT_EN - Flip-Flop Initial Output Enable Control + * 0b0..Write 0 does not generate enable pulse + * 0b1..Write 1 generates enable pulse + */ +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK (0x1CU) +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT (2U) +/*! MODE_SEL - Flip-Flop Mode Selection + * 0b000..Bypass mode + * 0b001..RS Trigger mode + * 0b010..T-FF mode + * 0b011..D-FF mode + * 0b100..JK-FF mode + * 0b101..Latch mode + * 0b110..Reserved + * 0b111..Reserved + */ +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT (6U) +/*! FB_OVRD - EVTG Output Feedback Override Control + * 0b00..Replace An + * 0b01..Replace Bn + * 0b10..Replace Cn + * 0b11..Replace Dn + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK (0xF00U) +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT (8U) +/*! SYNC_CTRL - Synchronize Control + * 0bxxx1..EVTG input "An" will be synced by two bus clk cycles + * 0bxxx0..EVTG input "An" will not be synced + * 0bxx1x..EVTG input "Bn" will be synced by two bus clk cycles + * 0bxx0x..EVTG input "Bn" will not be synced + * 0bx1xx..EVTG input "Cn" will be synced by two bus clk cycles + * 0bx0xx..EVTG input "Cn" will not be synced + * 0b1xxx..EVTG input "Dn" will be synced by two bus clk cycles + * 0b0xxx..EVTG input "Dn" will not be synced + */ +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT (12U) +/*! FORCE_BYPASS - Force Bypass Control + * 0bx1..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_0(Filter_0) value directly to EVTG_OUTA + * 0bx0..Will not force the bypass + * 0b1x..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_1(Filter_1) value directly to EVTG_OUTB + * 0b0x..Will not force the bypass + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_CTRL */ +#define EVTG_EVTG_INST_EVTG_CTRL_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_FILT - AOI0 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_FILT - AOI1 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_COUNT (4U) + + +/*! + * @} + */ /* end of group EVTG_Register_Masks */ + + +/* EVTG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/*! + * @} + */ /* end of group EVTG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control, offset: 0x0 */ + __O uint8_t SERV; /**< Service, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +/*! EWMEN - EWM Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) + +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +/*! ASSIN - Assertion State Select + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) + +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +/*! INEN - Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) + +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +/*! INTEN - Interrupt Enable + * 0b1..Generates interrupt requests + * 0b0..Deasserts interrupt requests + */ +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service */ +/*! @{ */ + +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +/*! SERVICE - Service */ +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low */ +/*! @{ */ + +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +/*! COMPAREL - Compare Low */ +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High */ +/*! @{ */ + +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +/*! COMPAREH - Compare High */ +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control */ +/*! @{ */ + +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +/*! CLKSEL - Clock Select */ +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler */ +/*! @{ */ + +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +/*! CLK_DIV - Clock Divider */ +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[96]; + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[96]; + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[96]; + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (8U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (8U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + +/* The count of FMU_FCCOB */ +#define FMU_FCCOB_COUNT (8U) + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMUTEST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer + * @{ + */ + +/** FMUTEST - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + __I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */ + __IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */ + __IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */ + __IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */ + __IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */ + __IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */ + __IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */ + __IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */ + __IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */ + uint8_t RESERVED_0[208]; + __IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */ + __IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */ + __I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */ + __IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */ + __I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */ + __IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */ + __IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */ + __IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */ + __IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */ + __IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */ + __IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */ + __IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */ + __IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */ + __IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */ + __IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */ + __IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */ + __IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */ + __IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */ + __IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */ + __IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */ + __IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */ + __IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */ + __IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */ + __I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */ + __IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */ + __IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */ + __IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */ + __IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */ + __IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */ + __IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */ + __IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */ + __IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */ + __IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */ + __IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */ + __IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */ + __IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */ + __IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */ + __IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */ + __IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */ + __IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */ + __IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */ + __IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */ + __IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */ + __IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */ + __IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */ + __IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */ + __IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */ + __IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */ + __IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */ + __IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */ + __IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */ + __IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */ + __IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */ + __IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */ + __IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */ + __IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */ + uint8_t RESERVED_4[4]; + __IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */ + __IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */ + __IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */ + __IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */ + __IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */ + __IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */ + __IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */ + __IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */ + __IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */ + __O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */ + __I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */ + __I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */ + uint8_t RESERVED_5[8]; + __I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */ + __IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */ + __IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */ + __IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */ + __IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */ + __IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */ + __IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */ + __IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */ + __I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */ + __I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */ + __I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */ + __IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */ + __IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */ + __IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */ + __IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */ + uint8_t RESERVED_6[8]; + __I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */ + __I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */ + __I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */ + __I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */ + uint8_t RESERVED_7[132]; + __IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */ + uint8_t RESERVED_8[8]; + __IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */ + uint8_t RESERVED_9[12]; + __I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */ + uint8_t RESERVED_10[40]; + __I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */ + __I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */ + __I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */ + uint8_t RESERVED_11[4]; + __IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */ + __IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */ + __IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */ + uint8_t RESERVED_12[136]; + __IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */ + __IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */ + __IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */ + __IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */ + __IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */ + __IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */ + __IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */ + __IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */ + __IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */ + uint8_t RESERVED_13[220]; + __IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */ + __IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */ + __IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */ + __IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */ + uint8_t RESERVED_14[240]; + __IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */ + __IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */ + uint8_t RESERVED_15[4]; + __IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */ + __IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */ + __IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */ + __IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */ + __IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */ + __IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */ + __IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */ +} FMUTEST_Type; + +/* ---------------------------------------------------------------------------- + -- FMUTEST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMUTEST_FSTAT_FAIL_MASK (0x1U) +#define FMUTEST_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK) + +#define FMUTEST_FSTAT_CMDABT_MASK (0x4U) +#define FMUTEST_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK) + +#define FMUTEST_FSTAT_PVIOL_MASK (0x10U) +#define FMUTEST_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK) + +#define FMUTEST_FSTAT_ACCERR_MASK (0x20U) +#define FMUTEST_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK) + +#define FMUTEST_FSTAT_CWSABT_MASK (0x40U) +#define FMUTEST_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK) + +#define FMUTEST_FSTAT_CCIF_MASK (0x80U) +#define FMUTEST_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command or initialization in progress + * 0b1..Flash command or initialization has completed + */ +#define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK) + +#define FMUTEST_FSTAT_CMDPRT_MASK (0x300U) +#define FMUTEST_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command Protection Level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK) + +#define FMUTEST_FSTAT_CMDP_MASK (0x800U) +#define FMUTEST_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command Protection Status Flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK) + +#define FMUTEST_FSTAT_CMDDID_MASK (0xF000U) +#define FMUTEST_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command Domain ID */ +#define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK) + +#define FMUTEST_FSTAT_DFDIF_MASK (0x10000U) +#define FMUTEST_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access from the FMC + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC + */ +#define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK) + +#define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U) +#define FMUTEST_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during the last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK) + +#define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U) +#define FMUTEST_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK) + +#define FMUTEST_FSTAT_PERDY_MASK (0x80000000U) +#define FMUTEST_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program/Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation is not stalled + * 0b1..Program or sector erase command operation is stalled + */ +#define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMUTEST_FCNFG_CCIE_MASK (0x80U) +#define FMUTEST_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + */ +#define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK) + +#define FMUTEST_FCNFG_ERSREQ_MASK (0x100U) +#define FMUTEST_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase (Erase All) Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK) + +#define FMUTEST_FCNFG_DFDIE_MASK (0x10000U) +#define FMUTEST_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set + */ +#define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK) + +#define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK) + +#define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMUTEST_FCTRL_RWSC_MASK (0xFU) +#define FMUTEST_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control + * 0b0000..no additional wait-states are added (single cycle access) + * 0b0001..1 additional wait-state is added + * 0b0010..2 additional wait-states are added + * 0b0011..3 additional wait-states are added + * 0b0100..4 additional wait-states are added + * 0b0101..5 additional wait-states are added + * 0b0110..6 additional wait-states are added + * 0b0111..7 additional wait-states are added + * 0b1000..8 additional wait-states are added + * 0b1001..9 additional wait-states are added + * 0b1010..10 additional wait-states are added + * 0b1011..11 additional wait-states are added + * 0b1100..12 additional wait-states are added + * 0b1101..13 additional wait-states are added + * 0b1110..14 additional wait-states are added + * 0b1111..15 additional wait-states are added + */ +#define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK) + +#define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U) +#define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low Speed Active Mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK) + +#define FMUTEST_FCTRL_FDFD_MASK (0x10000U) +#define FMUTEST_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set + */ +#define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK) + +#define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMUTEST_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FTEST - Flash Test Register */ +/*! @{ */ + +#define FMUTEST_FTEST_TMECTL_MASK (0x1U) +#define FMUTEST_FTEST_TMECTL_SHIFT (0U) +/*! TMECTL - Test Mode Entry Control + * 0b0..FTEST register always reads 0 and writes to FTEST are ignored + * 0b1..FTEST register is readable and can be written to enable writability of TME + */ +#define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK) + +#define FMUTEST_FTEST_TMEWR_MASK (0x2U) +#define FMUTEST_FTEST_TMEWR_SHIFT (1U) +/*! TMEWR - Test Mode Entry Writable + * 0b0..TME bit is not writable + * 0b1..TME bit is writable + */ +#define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK) + +#define FMUTEST_FTEST_TME_MASK (0x4U) +#define FMUTEST_FTEST_TME_SHIFT (2U) +/*! TME - Test Mode Entry + * 0b0..Test mode entry not requested + * 0b1..Test mode entry requested + */ +#define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK) + +#define FMUTEST_FTEST_TMODE_MASK (0x8U) +#define FMUTEST_FTEST_TMODE_SHIFT (3U) +/*! TMODE - Test Mode Status + * 0b0..Test mode not active + * 0b1..Test mode active + */ +#define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK) + +#define FMUTEST_FTEST_TMELOCK_MASK (0x10U) +#define FMUTEST_FTEST_TMELOCK_SHIFT (4U) +/*! TMELOCK - Test Mode Entry Lock + * 0b0..FTEST register not locked from accepting writes + * 0b1..FTEST register locked from accepting writes + */ +#define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK) +/*! @} */ + +/*! @name FCCOB0 - Flash Command Control 0 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU) +#define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U) +/*! CMDCODE - Command code */ +#define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK) +/*! @} */ + +/*! @name FCCOB1 - Flash Command Control 1 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU) +#define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U) +/*! CMDOPT - Command options */ +#define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK) +/*! @} */ + +/*! @name FCCOB2 - Flash Command Control 2 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U) +/*! CMDADDR - Command starting address */ +#define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK) +/*! @} */ + +/*! @name FCCOB3 - Flash Command Control 3 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U) +/*! CMDADDRE - Command ending address */ +#define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK) +/*! @} */ + +/*! @name FCCOB4 - Flash Command Control 4 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U) +/*! CMDDATA0 - Command data word 0 */ +#define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK) +/*! @} */ + +/*! @name FCCOB5 - Flash Command Control 5 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U) +/*! CMDDATA1 - Command data word 1 */ +#define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK) +/*! @} */ + +/*! @name FCCOB6 - Flash Command Control 6 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U) +/*! CMDDATA2 - Command data word 2 */ +#define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK) +/*! @} */ + +/*! @name FCCOB7 - Flash Command Control 7 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U) +/*! CMDDATA3 - Command data word 3 */ +#define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK) +/*! @} */ + +/*! @name RESET_STATUS - FMU Initialization Tracking Register */ +/*! @{ */ + +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U) +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U) +/*! ARY_TRIM_DONE - Array Trim Complete + * 0b0..Recall register load operation has not been completed + * 0b1..Recall register load operation has completed + */ +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U) +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U) +/*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U) +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U) +/*! FMU_PARM_DONE - FMU Register Load Complete + * 0b0..FMU registers have not been loaded + * 0b1..FMU registers have been loaded + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U) +/*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U) +/*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings + * 0b0..C0DE_C0DEh check failed + * 0b1..C0DE_C0DEh check passed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U) +/*! SOC_TRIM_DONE - SoC Trim Complete + * 0b0..SoC Trim registers have not been updated + * 0b1..All SoC Trim registers have been updated + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U) +#define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U) +/*! RPR_DONE - Array Repair Complete + * 0b0..Repair registers have not been loaded + * 0b1..Repair registers have been loaded + */ +#define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK) + +#define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U) +#define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U) +/*! INIT_DONE - Initialization Done + * 0b0..All initialization steps did not complete + * 0b1..All initialization steps completed + */ +#define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U) +#define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U) +/*! RST_SF_ERR - ECC Single Fault during Reset Recovery + * 0b0..No single-bit faults detected during initialization + * 0b1..At least one single ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U) +#define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U) +/*! RST_DF_ERR - ECC Double Fault during Reset Recovery + * 0b0..No double-bit faults detected during initialization + * 0b1..Double-bit ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U) +/*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U) +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U) +/*! RST_PATCH_LD - Reset Patch Required + * 0b0..No patch required to be loaded during reset + * 0b1..Patch loaded during reset + */ +#define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK) + +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U) +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U) +/*! RECALL_DATA_MISMATCH - Recall Data Mismatch + * 0b0..Data read towards end of reset matched data read for Recall + * 0b1..Data read towards end of reset did not match data read for recall + */ +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK) +/*! @} */ + +/*! @name MCTL - FMU Control Register */ +/*! @{ */ + +#define FMUTEST_MCTL_COREHLD_MASK (0x1U) +#define FMUTEST_MCTL_COREHLD_SHIFT (0U) +/*! COREHLD - Core Hold + * 0b0..CPU access is allowed + * 0b1..CPU access must be blocked + */ +#define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK) + +#define FMUTEST_MCTL_LSACT_EN_MASK (0x4U) +#define FMUTEST_MCTL_LSACT_EN_SHIFT (2U) +/*! LSACT_EN - LSACTIVE Feature Enable + * 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. + * 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. + */ +#define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK) + +#define FMUTEST_MCTL_LSACTWREN_MASK (0x8U) +#define FMUTEST_MCTL_LSACTWREN_SHIFT (3U) +/*! LSACTWREN - LSACTIVE Write Enable + * 0b0..Unrestricted write access allowed + * 0b1..Write access while CMP set must match CMDDID and CMDPRT + */ +#define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK) + +#define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U) +#define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U) +/*! MASTER_REPAIR_EN - Master Repair Enable + * 0b0..Repair disabled + * 0b1..Repair enable determined by bit 0 of each REPAIR register + */ +#define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK) + +#define FMUTEST_MCTL_RFCMDEN_MASK (0x20U) +#define FMUTEST_MCTL_RFCMDEN_SHIFT (5U) +/*! RFCMDEN - RF Active Command Enable Control + * 0b0..Flash commands blocked (CCIF not writable) + * 0b1..Flash commands allowed + */ +#define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK) + +#define FMUTEST_MCTL_CWSABTEN_MASK (0x40U) +#define FMUTEST_MCTL_CWSABTEN_SHIFT (6U) +/*! CWSABTEN - Command Write Sequence Abort Enable + * 0b0..CWS abort feature is disabled + * 0b1..CWS abort feature is enabled + */ +#define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK) + +#define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U) +#define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U) +/*! MRGRDDIS - Margin Read Disable + * 0b0..Margin Read Settings are enabled + * 0b1..Margin Read Settings are disabled + */ +#define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK) + +#define FMUTEST_MCTL_MRGRD0_MASK (0xF00U) +#define FMUTEST_MCTL_MRGRD0_SHIFT (8U) +/*! MRGRD0 - Margin Read Setting for Program */ +#define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK) + +#define FMUTEST_MCTL_MRGRD1_MASK (0xF000U) +#define FMUTEST_MCTL_MRGRD1_SHIFT (12U) +/*! MRGRD1 - Margin Read Setting for Erase */ +#define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK) + +#define FMUTEST_MCTL_ERSAACK_MASK (0x10000U) +#define FMUTEST_MCTL_ERSAACK_SHIFT (16U) +/*! ERSAACK - Mass Erase (Erase All) Acknowledge + * 0b0..Mass Erase operation is not active (operation has completed or has not started) + * 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) + */ +#define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK) + +#define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U) +#define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U) +/*! SCAN_OBS - Scan Observability Control + * 0b0..Normal functional behavior + * 0b1..Enables observation of signals that may otherwise be ATPG untestable + */ +#define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK) + +#define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U) +#define FMUTEST_MCTL_BIST_CTL_SHIFT (20U) +/*! BIST_CTL - BIST IP Control + * 0b0..BIST IP disabled + * 0b1..BIST IP enabled + */ +#define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK) + +#define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U) +#define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U) +/*! SMWR_CTL - SMWR IP Control + * 0b0..SMWR IP disabled + * 0b1..SMWR IP enabled + */ +#define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK) + +#define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U) +#define FMUTEST_MCTL_SALV_DIS_SHIFT (24U) +/*! SALV_DIS - Salvage Disable + * 0b0..Salvage enabled (ECC used during erase verify) + * 0b1..Salvage disabled (ECC not used during erase verify) + */ +#define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK) + +#define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U) +#define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U) +/*! SOC_ECC_CTL - SOC ECC Control + * 0b0..ECC is enabled for SOC read access + * 0b1..ECC is disabled for SOC read access + */ +#define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK) + +#define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U) +#define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U) +/*! FMU_ECC_CTL - FMU ECC Control + * 0b0..ECC is enabled for FMU program operations + * 0b1..ECC is disabled for FMU program operations + */ +#define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK) + +#define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U) +#define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U) +/*! BIST_PWR_DIS - BIST Power Mode Disable + * 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) + * 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values + */ +#define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK) + +#define FMUTEST_MCTL_OSC_H_MASK (0x80000000U) +#define FMUTEST_MCTL_OSC_H_SHIFT (31U) +/*! OSC_H - Oscillator control + * 0b0..Use APB clock + * 0b1..Use a known fixed-frequency clock, e.g. 12 MHz + */ +#define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK) +/*! @} */ + +/*! @name BSEL_GEN - FMU Block Select Generation Register */ +/*! @{ */ + +#define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U) +#define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U) +/*! SBSEL_GEN - Generated SBSEL */ +#define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK) + +#define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U) +#define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U) +/*! MBSEL_GEN - Generated MBSEL */ +#define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK) +/*! @} */ + +/*! @name PWR_OPT - Power Mode Options Register */ +/*! @{ */ + +#define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU) +#define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U) +/*! PD_CDIV - Power Down Clock Divider Setting */ +#define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK) + +#define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U) +#define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U) +/*! SLM_COUNT - Sleep Recovery Timer Count */ +#define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK) + +#define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U) +#define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U) +/*! PD_TIMER_EN - Power Down BIST Timer Enable + * 0b0..BIST timer is not triggered during Power Down recovery + * 0b1..BIST timer is triggered during Power Down recovery (default behavior) + */ +#define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK) +/*! @} */ + +/*! @name CMD_CHECK - FMU Command Check Register */ +/*! @{ */ + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U) +/*! ALIGNFAIL_PHR - Phrase Alignment Fail + * 0b0..The address is phrase-aligned + * 0b1..The address is not phrase-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U) +/*! ALIGNFAIL_PG - Page Alignment Fail + * 0b0..The address is page-aligned + * 0b1..The address is not page-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U) +/*! ALIGNFAIL_SCR - Sector Alignment Fail + * 0b0..The address is sector-aligned + * 0b1..The address is not sector-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U) +/*! ALIGNFAIL_BLK - Block Alignment Fail + * 0b0..The address is block-aligned + * 0b1..The address is not block-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK) + +#define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U) +#define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U) +/*! ADDR_FAIL - Address Fail + * 0b0..The address is within the flash or IFR address space + * 0b1..The address is outside the flash or IFR address space + */ +#define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U) +#define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U) +/*! IFR_CMD - IFR Command + * 0b0..The command operates on a main flash address + * 0b1..The command operates on an IFR address + */ +#define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK) + +#define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U) +#define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U) +/*! ALL_CMD - All Blocks Command + * 0b0..The command operates on a single flash block + * 0b1..The command operates on all flash blocks + */ +#define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK) + +#define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U) +#define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U) +/*! RANGE_FAIL - Address Range Fail + * 0b0..The address range is valid + * 0b1..The address range is invalid + */ +#define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U) +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U) +/*! SCR_ALIGN_CHK - Sector Alignment Check + * 0b0..No sector alignment check + * 0b1..Sector alignment check + */ +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK) + +#define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U) +#define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U) +/*! OPTION_FAIL - Option Check Fail + * 0b0..Option check passes for read command or command is not a read command + * 0b1..Option check fails for read command + */ +#define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U) +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U) +/*! ILLEGAL_CMD - Illegal Command + * 0b0..Command is legal + * 0b1..Command is illegal + */ +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK) +/*! @} */ + +/*! @name BSEL - FMU Block Select Register */ +/*! @{ */ + +#define FMUTEST_BSEL_SBSEL_MASK (0x3U) +#define FMUTEST_BSEL_SBSEL_SHIFT (0U) +/*! SBSEL - Slave Block Select */ +#define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK) + +#define FMUTEST_BSEL_MBSEL_MASK (0x300U) +#define FMUTEST_BSEL_MBSEL_SHIFT (8U) +/*! MBSEL - Master Block Select */ +#define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK) +/*! @} */ + +/*! @name MSIZE - FMU Memory Size Register */ +/*! @{ */ + +#define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU) +#define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U) +/*! MAXADDR0 - Size of Flash Block 0 */ +#define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK) + +#define FMUTEST_MSIZE_MAXADDR1_MASK (0xFF00U) +#define FMUTEST_MSIZE_MAXADDR1_SHIFT (8U) +/*! MAXADDR1 - Size of Flash Block 1 */ +#define FMUTEST_MSIZE_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR1_SHIFT)) & FMUTEST_MSIZE_MAXADDR1_MASK) +/*! @} */ + +/*! @name FLASH_RD_ADD - Flash Read Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U) +/*! FLASH_RD_ADD - Flash Read Address */ +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK) +/*! @} */ + +/*! @name FLASH_STOP_ADD - Flash Stop Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U) +/*! FLASH_STOP_ADD - Flash Stop Address */ +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK) +/*! @} */ + +/*! @name FLASH_RD_CTRL - Flash Read Control Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U) +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U) +/*! FLASH_RD - Flash Read Enable + * 0b0..Manual flash read not enabled.(default) + * 0b1..Manual flash read enabled + */ +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U) +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U) +/*! WIDE_LOAD - Wide Load Enable + * 0b0..Wide load mode disabled (default) + * 0b1..Wide load mode enabled + */ +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U) +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U) +/*! SINGLE_RD - Single Flash Read + * 0b0..Normal UINT operation + * 0b1..UINT configured for single cycle reads + */ +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK) +/*! @} */ + +/*! @name MM_ADDR - Memory Map Address Register */ +/*! @{ */ + +#define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U) +/*! MM_ADDR - Memory Map Address */ +#define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK) +/*! @} */ + +/*! @name MM_WDATA - Memory Map Write Data Register */ +/*! @{ */ + +#define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U) +/*! MM_WDATA - Memory Map Write Data */ +#define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK) +/*! @} */ + +/*! @name MM_CTL - Memory Map Control Register */ +/*! @{ */ + +#define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U) +#define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U) +/*! MM_SEL - Register Access Enable */ +#define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK) + +#define FMUTEST_MM_CTL_MM_RD_MASK (0x2U) +#define FMUTEST_MM_CTL_MM_RD_SHIFT (1U) +/*! MM_RD - Register R/W Control + * 0b0..Write to register + * 0b1..Read register + */ +#define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK) + +#define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U) +#define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U) +/*! BIST_ON - BIST on + * 0b0..BIST enable not forced by user interface + * 0b1..BIST enable control by user interface + */ +#define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK) + +#define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U) +#define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U) +/*! FORCE_SW_CLK - Force Switch Clock + * 0b0..Switch clock not forced on (gated normally) + * 0b1..Switch clock forced on + */ +#define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK) +/*! @} */ + +/*! @name UINT_CTL - User Interface Control Register */ +/*! @{ */ + +#define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U) +#define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U) +/*! SET_FAIL - Set Fail On Exit + * 0b0..FAIL flag should not be set on command exit (no failure detected) + * 0b1..FAIL flag should be set on command exit + */ +#define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK) + +#define FMUTEST_UINT_CTL_DBERR_MASK (0x2U) +#define FMUTEST_UINT_CTL_DBERR_SHIFT (1U) +/*! DBERR - Double-Bit ECC Fault Detect + * 0b0..No double-bit fault detected during UINT-driven read sequence + * 0b1..Double-bit fault detected during UINT-driven read sequence + */ +#define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK) +/*! @} */ + +/*! @name RD_DATA0 - Read Data 0 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U) +/*! RD_DATA0 - Read Data 0 */ +#define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK) +/*! @} */ + +/*! @name RD_DATA1 - Read Data 1 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U) +/*! RD_DATA1 - Read Data 1 */ +#define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK) +/*! @} */ + +/*! @name RD_DATA2 - Read Data 2 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U) +/*! RD_DATA2 - Read Data 2 */ +#define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK) +/*! @} */ + +/*! @name RD_DATA3 - Read Data 3 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U) +/*! RD_DATA3 - Read Data 3 */ +#define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK) +/*! @} */ + +/*! @name PARITY - Parity Register */ +/*! @{ */ + +#define FMUTEST_PARITY_PARITY_MASK (0x1FFU) +#define FMUTEST_PARITY_PARITY_SHIFT (0U) +/*! PARITY - Read data [136:128] */ +#define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK) +/*! @} */ + +/*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */ +/*! @{ */ + +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU) +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U) +/*! RD_CAPT - Read Capture Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U) +/*! SE_SIZE - SE Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U) +/*! ECC_ENABLEB - ECC Decoder Control + * 0b0..ECC decoder enabled (default) + * 0b1..ECC decoder disabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U) +/*! MISR_EN - MISR Enable + * 0b0..MISR option disabled (default) + * 0b1..MISR option enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U) +/*! CPY_PAR_EN - Copy Parity Enable + * 0b0..Copy parity disabled + * 0b1..Copy parity enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U) +/*! BIST_MUX_TO_SMW - BIST Mux to SMW + * 0b0..BIST drives fields + * 0b1..SMW registers drive fields + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U) +/*! AD_SET - Multi-Cycle Address Setup Time */ +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U) +/*! WR_PATH_EN - Write Path Enable + * 0b0..Writes to BIST setting registers driven by MM_WDATA + * 0b1..Writes to BIST setting registers driven by SMW_DIN + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U) +/*! WR_PATH_ECC_EN - Write Path ECC Enable + * 0b0..ECC encoding disabled + * 0b1..ECC encoding enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U) +/*! DBERR_REG - Double-Bit Error + * 0b0..Double-bit fault not detected + * 0b1..Double-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U) +/*! SBERR_REG - Single-Bit Error + * 0b0..Single-bit fault not detected + * 0b1..Single-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U) +/*! CPY_PHRASE_EN - Copy Phrase Enable + * 0b0..Copy Flash read data disabled + * 0b1..Copy Flash read data enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U) +/*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL + * 0b0..Select block 0 + * 0b1..Select block 1 + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U) +/*! BIST_ECC_EN - BIST ECC Enable + * 0b0..ECC correction disabled + * 0b1..ECC correction enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U) +/*! LAST_READ - Last Read + * 0b0..Latest read not last in multi-address operation + * 0b1..Latest read last in multi-address operation + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK) +/*! @} */ + +/*! @name SMW_DIN0 - SMW DIN 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U) +/*! SMW_DIN0 - SMW DIN 0 */ +#define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK) +/*! @} */ + +/*! @name SMW_DIN1 - SMW DIN 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U) +/*! SMW_DIN1 - SMW DIN 1 */ +#define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK) +/*! @} */ + +/*! @name SMW_DIN2 - SMW DIN 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U) +/*! SMW_DIN2 - SMW DIN 2 */ +#define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK) +/*! @} */ + +/*! @name SMW_DIN3 - SMW DIN 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U) +/*! SMW_DIN3 - SMW DIN 3 */ +#define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK) +/*! @} */ + +/*! @name SMW_ADDR - SMW Address Register */ +/*! @{ */ + +#define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U) +/*! SMW_ADDR - SMW Address */ +#define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK) +/*! @} */ + +/*! @name SMW_CMD_WAIT - SMW Command and Wait Register */ +/*! @{ */ + +#define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U) +#define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U) +/*! CMD - SMW Command + * 0b000..IDLE + * 0b001..ABORT + * 0b010..SME2 to one-shot mass erase + * 0b011..SME3 to sector erase on selected array + * 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit + * 0b101..Reserved for SME4 (multi-sector erase) + * 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss + * 0b111..Reserved + */ +#define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U) +/*! WAIT_EN - SMW Wait Enable + * 0b0..Wait feature disabled + * 0b1..Wait feature enabled + */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U) +/*! WAIT_AUTO_SET - SMW Wait Auto Set */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK) +/*! @} */ + +/*! @name SMW_STATUS - SMW Status Register */ +/*! @{ */ + +#define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U) +#define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U) +/*! SMW_ERR - SMW Error + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK) + +#define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U) +#define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U) +/*! SMW_BUSY - SMW Busy + * 0b0..SMW command not active + * 0b1..SMW command is active + */ +#define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK) + +#define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U) +#define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U) +/*! BIST_BUSY - BIST Busy + * 0b0..BIST Command not active + * 0b1..BIST Command is active + */ +#define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK) +/*! @} */ + +/*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U) +/*! TRIM0_0 - TRIM0_0 */ +#define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK) +/*! @} */ + +/*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U) +/*! TRIM0_1 - TRIM0_1 */ +#define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK) +/*! @} */ + +/*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U) +/*! TRIM0_2 - TRIM0_2 */ +#define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK) +/*! @} */ + +/*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U) +/*! TRIM0_3 - TRIM0_3 */ +#define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK) +/*! @} */ + +/*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U) +/*! TRIM1_0 - TRIM1_0 */ +#define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK) +/*! @} */ + +/*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U) +/*! TRIM1_1 - TRIM1_1 */ +#define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK) +/*! @} */ + +/*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U) +/*! TRIM1_2 - TRIM1_2 */ +#define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK) +/*! @} */ + +/*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U) +/*! TRIM1_3 - TRIM1_3 */ +#define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK) +/*! @} */ + +/*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U) +/*! TRIM2_0 - TRIM2_0 */ +#define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK) +/*! @} */ + +/*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U) +/*! TRIM2_1 - TRIM2_1 */ +#define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK) +/*! @} */ + +/*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U) +/*! TRIM2_2 - TRIM2_2 */ +#define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK) +/*! @} */ + +/*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U) +/*! TRIM2_3 - TRIM2_3 */ +#define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK) +/*! @} */ + +/*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U) +/*! TRIM3_0 - TRIM3_0 */ +#define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK) +/*! @} */ + +/*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U) +/*! TRIM3_1 - TRIM3_1 */ +#define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK) +/*! @} */ + +/*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U) +/*! TRIM3_2 - TRIM3_2 */ +#define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK) +/*! @} */ + +/*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U) +/*! TRIM3_3 - TRIM3_3 */ +#define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK) +/*! @} */ + +/*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U) +/*! TRIM4_0 - TRIM4_0 */ +#define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK) +/*! @} */ + +/*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U) +/*! TRIM4_1 - TRIM4_1 */ +#define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK) +/*! @} */ + +/*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U) +/*! TRIM4_2 - TRIM4_2 */ +#define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK) +/*! @} */ + +/*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U) +/*! TRIM4_3 - TRIM4_3 */ +#define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK) +/*! @} */ + +/*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U) +/*! TRIM5_0 - TRIM5_0 */ +#define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK) +/*! @} */ + +/*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U) +/*! TRIM5_1 - TRIM5_1 */ +#define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK) +/*! @} */ + +/*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U) +/*! TRIM5_2 - TRIM5_2 */ +#define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK) +/*! @} */ + +/*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U) +/*! TRIM5_3 - TRIM5_3 */ +#define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK) +/*! @} */ + +/*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U) +/*! TRIM6_0 - TRIM6_0 */ +#define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK) +/*! @} */ + +/*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U) +/*! TRIM6_1 - TRIM6_1 */ +#define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK) +/*! @} */ + +/*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U) +/*! TRIM6_2 - TRIM6_2 */ +#define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK) +/*! @} */ + +/*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U) +/*! TRIM6_3 - TRIM6_3 */ +#define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK) +/*! @} */ + +/*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U) +/*! TRIM7_0 - TRIM7_0 */ +#define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK) +/*! @} */ + +/*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U) +/*! TRIM7_1 - TRIM7_1 */ +#define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK) +/*! @} */ + +/*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U) +/*! TRIM7_2 - TRIM7_2 */ +#define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK) +/*! @} */ + +/*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U) +/*! TRIM7_3 - TRIM7_3 */ +#define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK) +/*! @} */ + +/*! @name R_IP_CONFIG - BIST Configuration Register */ +/*! @{ */ + +#define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U) +#define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U) +/*! IPSEL0 - Block 0 Select Control + * 0b00..Unselect block 0 + * 0b01..not used, reserved + * 0b10..Enable block 0 test, repair off (default) + * 0b11..Enable block 0 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK) + +#define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU) +#define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U) +/*! IPSEL1 - Block 1 Select Control + * 0b00..Unselect block 1 + * 0b01..not used, reserved + * 0b10..Enable block 1 test, repair off (default) + * 0b11..Enable block 1 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U) +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U) +/*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK) + +#define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U) +#define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U) +/*! CDIVS - Number of clock cycles to generate short pulse */ +#define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U) +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U) +/*! BIST_TVFY - Timer adjust for verify */ +#define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK) + +#define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U) +#define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U) +/*! TSTCTL - BIST self-test control + * 0b00..Default, disable both BIST self-test and MISR + * 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. + * 0b10..Enable MISR + * 0b11..Enable both BIST self-test mode and MISR + */ +#define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U) +#define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U) +/*! DBGCTL - Debug feature control + * 0b0..Default + * 0b1..Enable debug feature to collect failure address and data. + */ +#define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U) +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U) +/*! BIST_CLK_SEL - BIST Clock Select */ +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK) + +#define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U) +#define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U) +/*! SMWTST - SMWR DOUT Function Control + * 0b00..Default + * 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0 + * 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1 + * 0b11..Reserved (unused) + */ +#define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK) + +#define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U) +#define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U) +/*! ECCEN - BIST ECC Control + * 0b0..Default mode (no ECC encode or decode) + * 0b1..Enable ECC encode/decode + */ +#define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK) +/*! @} */ + +/*! @name R_TESTCODE - BIST Test Code Register */ +/*! @{ */ + +#define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU) +#define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U) +/*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */ +#define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK) +/*! @} */ + +/*! @name R_DFT_CTRL - BIST DFT Control Register */ +/*! @{ */ + +#define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU) +#define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U) +/*! DFT_XADR - DFT XADR Pattern + * 0b0000..XADR fixed, no change at all + * 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of + * row. For PROG operation, XADR increases by 1 after NVSTR falls. + * 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. + * 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. + * 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word + * of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. + * 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. + * 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. + * 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. + */ +#define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U) +#define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U) +/*! DFT_YADR - DFT YADR Pattern + * 0b0000..YADR fixed, no change at all + * 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. + * 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. + * 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG + * operations, YADR increased by 1 after YE falls. + * 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. + * 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. + * 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. + * 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. + * 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. + * 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. + */ +#define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U) +/*! DFT_DATA - DFT Data Pattern + * 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. + * 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. + * 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. + * 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to + * R_ADR_CTRL[GRPSEL] for modules with multiple groups. + * 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ + * operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected + * groups. + * 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If + * more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. + * 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA + * when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals + * R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. + * 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data + * pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. + * 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 + * and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared + * against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only + * one flash block can be selected. + * 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK) + +#define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U) +#define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U) +/*! CMP_MASK - Data Compare Mask + * 0b00..Expected data is compared to DOUT + * 0b01..Expected data (only 0s are considered) are compared to DOUT + * 0b10..Expected data (only 1s are considered) are compared to DOUT + */ +#define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U) +/*! DFT_DATA_SRC - DFT Data Source + * 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + * 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK) +/*! @} */ + +/*! @name R_ADR_CTRL - BIST Address Control Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU) +#define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U) +/*! GRPSEL - Data Group Select + * 0b0000..Select no data + * 0b0001..Select data slice [34:0] + * 0b0010..Select data slice [69:35] + * 0b0100..Select data slice [104:70] + * 0b1000..Select data slice [136:105] + * 0b1111..Select data [136:0] + */ +#define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK) + +#define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U) +#define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U) +/*! XADR - BIST XADR */ +#define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK) + +#define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U) +#define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U) +/*! YADR - BIST YADR */ +#define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK) + +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U) +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U) +/*! PROG_ATTR - Program Attribute + * 0b000..One YE pulse will program one data slice group + * 0b001..One YE pulse will program two data slice groups + * 0b010..One YE pulse will program three data slice groups (reserved) + * 0b011..One YE pulse will program four data slice groups + * 0b100..One YE pulse will program five data slice groups (reserved) + * 0b101..One YE pulse will program six data slice groups (reserved) + * 0b110..One YE pulse will program seven data slice groups (reserved) + * 0b111..One YE pulse will program eight data slice groups (reserved) + */ +#define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U) +/*! DATA0 - BIST Data 0 Low */ +#define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK) +/*! @} */ + +/*! @name R_PIN_CTRL - BIST Pin Control Register */ +/*! @{ */ + +#define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U) +#define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U) +/*! MAS1 - Mass Erase */ +#define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U) +#define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U) +/*! IFREN - IFR Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U) +#define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U) +/*! IFREN1 - IFR1 Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK) + +#define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U) +#define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U) +/*! REDEN - Redundancy Block Enable */ +#define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK) + +#define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U) +#define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U) +/*! LVE - Low Voltage Enable */ +#define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK) + +#define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U) +#define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U) +/*! PV - Program Verify Enable */ +#define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK) + +#define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U) +#define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U) +/*! EV - Erase Verify Enable */ +#define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK) + +#define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U) +#define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U) +/*! WIPGM - Program Current */ +#define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK) + +#define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U) +#define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U) +/*! WHV - High Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK) + +#define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U) +#define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U) +/*! WMV - Medium Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK) + +#define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U) +#define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U) +/*! XE - X Address Enable */ +#define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK) + +#define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U) +#define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U) +/*! YE - Y Address Enable */ +#define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK) + +#define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U) +#define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U) +/*! SE - Sense Amp Enable */ +#define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK) + +#define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U) +#define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U) +/*! ERASE - Erase Mode */ +#define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK) + +#define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U) +#define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U) +/*! PROG - Program Mode */ +#define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK) + +#define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U) +#define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U) +/*! NVSTR - NVM Store */ +#define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK) + +#define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U) +#define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U) +/*! SLM - Sleep Mode Enable */ +#define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK) + +#define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U) +#define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U) +/*! RECALL - Recall Trim Code */ +#define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK) + +#define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U) +#define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U) +/*! HEM - HEM Control */ +#define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK) +/*! @} */ + +/*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */ +/*! @{ */ + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U) +/*! LOOPCNT - Loop Count Control */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U) +/*! LOOPOPT - Loop Option + * 0b000..Loop is disabled; selected BIST operation is run once + * 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U) +/*! LOOPUNIT - Loop Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U) +/*! LOOPDLY - Loop Time Delay Scalar */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL - BIST Timer Control Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U) +/*! TNVSUNIT - Tnvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U) +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U) +/*! TNVSDLY - Tnvs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U) +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U) +/*! TNVHUNIT - Tnvh Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U) +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U) +/*! TNVHDLY - Tnvh Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U) +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U) +/*! TPGSUNIT - Tpgs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U) +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U) +/*! TPGSDLY - Tpgs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U) +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U) +/*! TRCVUNIT - Trcv Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U) +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U) +/*! TRCVDLY - Trcv Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U) +/*! TLVSUNIT - Tlvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U) +/*! TLVSDLY_L - Tlvs Time Delay Scalar Low */ +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK) +/*! @} */ + +/*! @name R_TEST_CTRL - BIST Test Control Register */ +/*! @{ */ + +#define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U) +#define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U) +/*! BUSY - BIST Busy Status + * 0b0..BIST is idle + * 0b1..BIST is busy + */ +#define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U) +#define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U) +/*! DEBUG - BIST Debug Status */ +#define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U) +#define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U) +/*! STATUS0 - BIST Status 0 + * 0b0..BIST test passed on flash block 0 + * 0b1..BIST test failed on flash block 0 + */ +#define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U) +#define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U) +/*! STATUS1 - BIST status 1 + * 0b0..BIST test passed on flash block 1 + * 0b1..BIST test failed on flash block 1 + */ +#define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U) +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U) +/*! DEBUGRUN - BIST Continue Debug Run */ +#define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U) +#define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U) +/*! STARTRUN - Run New BIST Operation */ +#define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U) +#define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U) +/*! CMDINDEX - BIST Command Index (code) */ +#define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK) + +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U) +/*! DISABLE_IP1 - BIST Disable IP1 */ +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK) +/*! @} */ + +/*! @name R_ABORT_LOOP - BIST Abort Loop Register */ +/*! @{ */ + +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U) +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U) +/*! ABORT_LOOP - Abort Loop + * 0b0..No effect + * 0b1..Abort BIST loop commands and force the loop counter to return to 0x0 + */ +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK) +/*! @} */ + +/*! @name R_ADR_QUERY - BIST Address Query Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU) +#define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U) +/*! YADRFAIL - Failing YADR */ +#define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK) + +#define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U) +#define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U) +/*! XADRFAIL - Failing XADR */ +#define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U) +/*! DOUTFAIL - Failing DOUT Low */ +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK) +/*! @} */ + +/*! @name R_SMW_QUERY - BIST SMW Query Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU) +#define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U) +/*! SMWLOOP - SMW Total Loop Count */ +#define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK) + +#define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U) +#define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U) +/*! SMWLAST - SMW Last Voltage Setting */ +#define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU) +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U) +/*! SMWPARM0 - SMW Parameter Set 0 */ +#define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U) +/*! SMWPARM1 - SMW Parameter Set 1 */ +#define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK) +/*! @} */ + +/*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U) +/*! SMPWHV0 - SMP WHV Parameter Set 0 */ +#define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK) +/*! @} */ + +/*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U) +/*! SMPWHV1 - SMP WHV Parameter Set 1 */ +#define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK) +/*! @} */ + +/*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U) +/*! SMEWHV0 - SME WHV Parameter Set 0 */ +#define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK) +/*! @} */ + +/*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U) +/*! SMEWHV1 - SME WHV Parameter Set 1 */ +#define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU) +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U) +/*! SMWPARM2 - SMW Parameter Set 2 */ +#define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK) +/*! @} */ + +/*! @name R_D_MISR0 - BIST DIN MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U) +/*! DATASIG0 - Data Signature */ +#define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK) +/*! @} */ + +/*! @name R_A_MISR0 - BIST Address MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U) +/*! ADRSIG0 - Address Signature */ +#define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK) +/*! @} */ + +/*! @name R_C_MISR0 - BIST Control MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U) +/*! CTRLSIG0 - Control Signature */ +#define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU) +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U) +/*! SMWPARM3 - SMW Parameter Set 3 */ +#define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U) +/*! DATA1 - BIST Data 1 Low */ +#define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U) +/*! DATA2 - BIST Data 2 Low */ +#define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U) +/*! DATA3 - BIST Data 3 Low */ +#define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK) +/*! @} */ + +/*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - Control Repair 0 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - XADR for Repair 0 in Block 0 */ +#define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - Control Repair 1 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - XADR for Repair 1 in Block 0. */ +#define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - Control Repair 0 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - XADR for Repair 0 in Block 1. */ +#define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - Control Repair 1 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - XADR for Repair 1 in Block 1. */ +#define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U) +/*! DATA0X - BIST Data 0 High */ +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U) +/*! TLVSDLY_H - Tlvs Time Delay Scalar High */ +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U) +#define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U) +/*! DOUT - Failing DOUT High */ +#define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK) +/*! @} */ + +/*! @name R_D_MISR1 - BIST DIN MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU) +#define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U) +/*! DATASIG1 - MISR Data Signature High */ +#define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK) +/*! @} */ + +/*! @name R_A_MISR1 - BIST Address MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU) +#define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U) +/*! ADRSIG1 - MISR Address Signature High */ +#define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK) +/*! @} */ + +/*! @name R_C_MISR1 - BIST Control MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU) +#define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U) +/*! CTRLSIG1 - MISR Control Signature High */ +#define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U) +/*! DATA1X - BIST Data 1 High */ +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U) +/*! DATA2X - BIST Data 2 High */ +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U) +/*! DATA3X - BIST Data 3 High */ +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK) +/*! @} */ + +/*! @name SMW_TIMER_OPTION - SMW Timer Option Register */ +/*! @{ */ + +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU) +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U) +/*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK) + +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U) +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U) +/*! SMW_TVFY - Timer Adjust for Verify */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U) +/*! MV_INIT - Medium Voltage Level Select Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U) +/*! MV_END - Medium Voltage Level Select Final */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U) +/*! MV_MISC - Medium Voltage Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U) +/*! IPGM_INIT - Program Current Control Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U) +/*! IPGM_END - Program Current Control Final */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U) +/*! IPGM_MISC - Program Current Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U) +/*! THVS_CTRL - Thvs control */ +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U) +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U) +/*! TRCV_CTRL - Trcv Control */ +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U) +/*! XTRA_ERS - Number of Post Shots for SME */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U) +/*! XTRA_PGM - Number of Post Shots for SMP */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U) +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U) +/*! WHV_CNTR - WHV Counter */ +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U) +/*! POST_TERS - Post Ters Time + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U) +/*! POST_TPGM - Post Tpgm Time + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U) +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U) +/*! VFY_OPT - Verify Option + * 0b00..Skip verify for post shot only, verify for all other shots + * 0b01..Skip verify for the 1st and post shots + * 0b10..Skip the 1st, 2nd, and post shots + * 0b11..Skip verify for all shots + */ +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U) +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U) +/*! TPGM_OPT - Tpgm Option + * 0b00..Fixed Tpgm for all shots, except post shot + * 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec + * 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec + * 0b11..Unused + */ +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U) +/*! MASK0_OPT - MASK0_OPT + * 0b0..Mask programmed bits passing PV until extra shot + * 0b1..Always program bits even if they pass PV + */ +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U) +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U) +/*! DIS_PRER - Disable pre-PV Read before First Program Shot + * 0b0..Enable pre-PV read before first program shot + * 0b1..Disable pre-PV read before first program shot + */ +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U) +/*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U) +/*! HEM_MAX_ERS - HEM Max Erase Shot Count */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U) +/*! SMP_WHV_OPT0 - Smart Program WHV Option Low */ +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U) +/*! SME_WHV_OPT0 - Smart Erase WHV Option Low */ +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U) +/*! TERS_CTRL0 - Ters Control + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U) +/*! TPGM_CTRL - Tpgm Control + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U) +/*! TNVS_CTRL - Tnvs Control + * 0b000..5 usec + * 0b001..8 usec + * 0b010..11 usec + * 0b011..14 usec + * 0b100..17 usec + * 0b101..20 usec + * 0b110..23 usec + * 0b111..26 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U) +/*! TNVH_CTRL - Tnvh Control + * 0b000..2 usec + * 0b001..2.5 usec + * 0b010..3 usec + * 0b011..3.5 usec + * 0b100..4 usec + * 0b101..4.5 usec + * 0b110..5 usec + * 0b111..5.5 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U) +/*! TPGS_CTRL - Tpgs Control + * 0b000..1 usec + * 0b001..2 usec + * 0b010..3 usec + * 0b011..4 usec + * 0b100..5 usec + * 0b101..6 usec + * 0b110..7 usec + * 0b111..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U) +/*! MAX_ERASE - Number of Erase Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U) +/*! MAX_PROG - Number of Program Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U) +/*! SMP_WHV_OPT1 - Smart Program WHV Option High */ +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U) +/*! SME_WHV_OPT1 - Smart Erase WHV Option High */ +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK) +/*! @} */ + +/*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - RDIS0_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - RADR0_0 */ +#define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - RDIS0_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - RADR0_1 */ +#define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - RDIS1_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - RADR1_0 */ +#define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - RDIS1_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - RADR1_1 */ +#define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name SMW_HB_SIGNALS - SMW HB Signals Register */ +/*! @{ */ + +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U) +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U) +/*! SMW_ARRAY - SMW Region Select + * 0b000..Main array + * 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase + * 0b010..IFR1 space + * 0b100..REDEN space + */ +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U) +/*! USER_IFREN1 - IFR1 Enable + * 0b0..IFREN1 input to the flash array is driven LOW + * 0b1..IFREN1 input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U) +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U) +/*! USER_PV - Program Verify + * 0b0..PV input to the flash array is driven LOW + * 0b1..PV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U) +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U) +/*! USER_EV - Erase Verify + * 0b0..EV input to the flash array is driven LOW + * 0b1..EV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U) +/*! USER_IFREN - IFR Enable + * 0b0..IFREN input to the flash array is driven LOW + * 0b1..IFREN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U) +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U) +/*! USER_REDEN - Repair Read Enable + * 0b0..REDEN input to the flash array is driven LOW + * 0b1..REDEN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U) +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U) +/*! USER_HEM - High Endurance Enable + * 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW + * 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK) +/*! @} */ + +/*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */ +/*! @{ */ + +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U) +/*! BIST_DONE - BIST Done + * 0b0..The BIST (or data dump) is running + * 0b1..The BIST (or data dump) has completed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U) +/*! BIST_FAIL - BIST Fail + * 0b0..The last BIST operation completed successfully (or could not fail) + * 0b1..The last BIST operation failed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U) +/*! DATADUMP - Data Dump Enable */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U) +/*! DATADUMP_TRIG - Data Dump Trigger */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U) +/*! DATADUMP_PATT - Data Dump Pattern Select + * 0b00..All ones + * 0b01..All zeroes + * 0b10..Checkerboard + * 0b11..Inverse checkerboard + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U) +/*! DATADUMP_MRGEN - Data Dump Margin Enable + * 0b0..Normal read pulse shape + * 0b1..Margin read pulse shape + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U) +/*! DATADUMP_MRGTYPE - Data Dump Margin Type + * 0b0..DIN method used + * 0b1..TM method used + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK) +/*! @} */ + +/*! @name ATX_PIN_CTRL - ATX Pin Control Register */ +/*! @{ */ + +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU) +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U) +/*! TM_TO_ATX - TM to ATX + * 0b00000001..TM[0] to ATX0 + * 0b00000010..TM[1] to ATX0 + * 0b00000100..TM[2] to ATX0 + * 0b00001000..TM[3] to ATX0 + * 0b00010000..TM[0] to ATX1 + * 0b00100000..TM[1] to ATX1 + * 0b01000000..TM[2] to ATX1 + * 0b10000000..TM[3] to ATX1 + */ +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK) +/*! @} */ + +/*! @name FAILCNT - Fail Count Register */ +/*! @{ */ + +#define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU) +#define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U) +/*! FAILCNT - Fail Count */ +#define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U) +/*! PGM_CNT0 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U) +/*! PGM_CNT1 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK) +/*! @} */ + +/*! @name ERS_PULSE_CNT - Erase Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U) +/*! ERS_CNT0 - Block 0 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK) + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U) +/*! ERS_CNT1 - Block 1 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK) +/*! @} */ + +/*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU) +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U) +/*! LAST_PCNT - Last SMW Operation's Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U) +/*! MAX_ERS_CNT - Maximum Erase Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U) +/*! MAX_PGM_CNT - Maximum Program Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK) +/*! @} */ + +/*! @name PORT_CTRL - Port Control Register */ +/*! @{ */ + +#define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U) +#define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U) +/*! BDONE_SEL - BIST Done Select + * 0b00..Select internal bist_done signal from current module instantiation + * 0b01..Select ipt_bist_fail signal from current module instantiation + * 0b10..Select ipt_bist_done signal from other module instantiation + * 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK) + +#define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU) +#define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U) +/*! BSDO_SEL - BIST Serial Data Output Select + * 0b00..Select internal bist_sdo signal from current module instantiation + * 0b01..Select ipt_bist_done signal from current module instantiation + * 0b10..Select ipt_bist_sdo signal from other module instantiation + * 0b11..Select ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMUTEST_Register_Masks */ + + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/*! + * @} + */ /* end of group FMUTEST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GDET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer + * @{ + */ + +/** GDET - Register Layout Typedef */ +typedef struct { + __IO uint32_t GDET_CONF_0; /**< GDET Configuration 0 Register, offset: 0x0 */ + __IO uint32_t GDET_CONF_1; /**< GDET Configuration 1 Register, offset: 0x4 */ + __IO uint32_t GDET_ENABLE1; /**< GDET Enable Register, offset: 0x8 */ + __IO uint32_t GDET_CONF_2; /**< GDET Configuration 2 Register, offset: 0xC */ + __IO uint32_t GDET_CONF_3; /**< GDET Configuration 3 Register, offset: 0x10 */ + __IO uint32_t GDET_CONF_4; /**< GDET Configuration 4 Register, offset: 0x14 */ + __IO uint32_t GDET_CONF_5; /**< GDET Configuration 5 Register, offset: 0x18 */ + uint8_t RESERVED_0[4004]; + __IO uint32_t GDET_RESET; /**< GDET Reset Register, offset: 0xFC0 */ + __IO uint32_t GDET_TEST; /**< GDET Test Register, offset: 0xFC4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t GDET_DLY_CTRL; /**< GDET Delay Control Register, offset: 0xFCC */ +} GDET_Type; + +/* ---------------------------------------------------------------------------- + -- GDET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Register_Masks GDET Register Masks + * @{ + */ + +/*! @name GDET_CONF_0 - GDET Configuration 0 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) +#define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) +/*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ +#define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) + +#define GDET_GDET_CONF_0_SBZ_MASK (0x10U) +#define GDET_GDET_CONF_0_SBZ_SHIFT (4U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) + +#define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) +#define GDET_GDET_CONF_0_RFU_SHIFT (5U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_1 - GDET Configuration 1 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) +#define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) +/*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ +#define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) + +#define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) +#define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) +/*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ +#define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) + +#define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) +#define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) +/*! SBZ1 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) + +#define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) +#define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) +/*! SBZ2 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) + +#define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) +#define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) +/*! SBZ3 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) + +#define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) +#define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) +/*! FIELD_7 - GDET Configuration 1 Field 7 */ +#define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) + +#define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) +#define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) +/*! FIELD_8 - GDET Configuration 1 Field 8 */ +#define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) + +#define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) +#define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) +/*! SBZ4 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) + +#define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) +#define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) +/*! SBZ5 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) + +#define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) +#define GDET_GDET_CONF_1_RFU_SHIFT (11U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) +/*! @} */ + +/*! @name GDET_ENABLE1 - GDET Enable Register */ +/*! @{ */ + +#define GDET_GDET_ENABLE1_EN1_MASK (0x1U) +#define GDET_GDET_ENABLE1_EN1_SHIFT (0U) +/*! EN1 - If set, the detector will be clock gated */ +#define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) + +#define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_ENABLE1_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_2 - GDET Configuration 2 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ +#define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) +#define GDET_GDET_CONF_2_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) + +#define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) +#define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) +/*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ +#define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) + +#define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) +#define GDET_GDET_CONF_2_RFU2_SHIFT (22U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) + +#define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) +#define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) +/*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ +#define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) + +#define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) +#define GDET_GDET_CONF_2_RFU3_SHIFT (30U) +/*! RFU3 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) +/*! @} */ + +/*! @name GDET_CONF_3 - GDET Configuration 3 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ +#define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_3_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_4 - GDET Configuration 4 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ +#define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_4_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_5 - GDET Configuration 5 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) +#define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) +/*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ +#define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) + +#define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) +#define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) +/*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ +#define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) + +#define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) +#define GDET_GDET_CONF_5_RFU1_SHIFT (12U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) +/*! @} */ + +/*! @name GDET_RESET - GDET Reset Register */ +/*! @{ */ + +#define GDET_GDET_RESET_RFU1_MASK (0x7U) +#define GDET_GDET_RESET_RFU1_SHIFT (0U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) + +#define GDET_GDET_RESET_SFT_RST_MASK (0x8U) +#define GDET_GDET_RESET_SFT_RST_SHIFT (3U) +/*! SFT_RST - Soft Reset for the Core Reset */ +#define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) + +#define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) +#define GDET_GDET_RESET_RFU2_SHIFT (4U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) +/*! @} */ + +/*! @name GDET_TEST - GDET Test Register */ +/*! @{ */ + +#define GDET_GDET_TEST_SBZ_MASK (0x1U) +#define GDET_GDET_TEST_SBZ_SHIFT (0U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) + +#define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_TEST_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) +/*! @} */ + +/*! @name GDET_DLY_CTRL - GDET Delay Control Register */ +/*! @{ */ + +#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) +#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) +/*! VOL_SEL - GDET Delay Control of the Voltage Mode */ +#define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) + +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) +/*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) + +#define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) +#define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GDET_Register_Masks */ + + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif + +/*! + * @} + */ /* end of group GDET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LOCK; /**< Lock, offset: 0xC */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ + uint8_t RESERVED_1[32]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_2[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_3[24]; + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define GPIO_LOCK_PCNS_MASK (0x1U) +#define GPIO_LOCK_PCNS_SHIFT (0U) +/*! PCNS - Lock PCNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) + +#define GPIO_LOCK_ICNS_MASK (0x2U) +#define GPIO_LOCK_ICNS_SHIFT (1U) +/*! ICNS - Lock ICNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) + +#define GPIO_LOCK_PCNP_MASK (0x4U) +#define GPIO_LOCK_PCNP_SHIFT (2U) +/*! PCNP - Lock PCNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) + +#define GPIO_LOCK_ICNP_MASK (0x8U) +#define GPIO_LOCK_ICNP_SHIFT (3U) +/*! ICNP - Lock ICNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) +/*! @} */ + +/*! @name PCNS - Pin Control Nonsecure */ +/*! @{ */ + +#define GPIO_PCNS_NSE0_MASK (0x1U) +#define GPIO_PCNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) + +#define GPIO_PCNS_NSE1_MASK (0x2U) +#define GPIO_PCNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) + +#define GPIO_PCNS_NSE2_MASK (0x4U) +#define GPIO_PCNS_NSE2_SHIFT (2U) +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) + +#define GPIO_PCNS_NSE3_MASK (0x8U) +#define GPIO_PCNS_NSE3_SHIFT (3U) +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) + +#define GPIO_PCNS_NSE4_MASK (0x10U) +#define GPIO_PCNS_NSE4_SHIFT (4U) +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) + +#define GPIO_PCNS_NSE5_MASK (0x20U) +#define GPIO_PCNS_NSE5_SHIFT (5U) +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) + +#define GPIO_PCNS_NSE6_MASK (0x40U) +#define GPIO_PCNS_NSE6_SHIFT (6U) +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) + +#define GPIO_PCNS_NSE7_MASK (0x80U) +#define GPIO_PCNS_NSE7_SHIFT (7U) +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) + +#define GPIO_PCNS_NSE8_MASK (0x100U) +#define GPIO_PCNS_NSE8_SHIFT (8U) +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) + +#define GPIO_PCNS_NSE9_MASK (0x200U) +#define GPIO_PCNS_NSE9_SHIFT (9U) +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) + +#define GPIO_PCNS_NSE10_MASK (0x400U) +#define GPIO_PCNS_NSE10_SHIFT (10U) +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) + +#define GPIO_PCNS_NSE11_MASK (0x800U) +#define GPIO_PCNS_NSE11_SHIFT (11U) +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) + +#define GPIO_PCNS_NSE12_MASK (0x1000U) +#define GPIO_PCNS_NSE12_SHIFT (12U) +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) + +#define GPIO_PCNS_NSE13_MASK (0x2000U) +#define GPIO_PCNS_NSE13_SHIFT (13U) +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) + +#define GPIO_PCNS_NSE14_MASK (0x4000U) +#define GPIO_PCNS_NSE14_SHIFT (14U) +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) + +#define GPIO_PCNS_NSE15_MASK (0x8000U) +#define GPIO_PCNS_NSE15_SHIFT (15U) +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) + +#define GPIO_PCNS_NSE16_MASK (0x10000U) +#define GPIO_PCNS_NSE16_SHIFT (16U) +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) + +#define GPIO_PCNS_NSE17_MASK (0x20000U) +#define GPIO_PCNS_NSE17_SHIFT (17U) +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) + +#define GPIO_PCNS_NSE18_MASK (0x40000U) +#define GPIO_PCNS_NSE18_SHIFT (18U) +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) + +#define GPIO_PCNS_NSE19_MASK (0x80000U) +#define GPIO_PCNS_NSE19_SHIFT (19U) +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) + +#define GPIO_PCNS_NSE20_MASK (0x100000U) +#define GPIO_PCNS_NSE20_SHIFT (20U) +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) + +#define GPIO_PCNS_NSE21_MASK (0x200000U) +#define GPIO_PCNS_NSE21_SHIFT (21U) +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) + +#define GPIO_PCNS_NSE22_MASK (0x400000U) +#define GPIO_PCNS_NSE22_SHIFT (22U) +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) + +#define GPIO_PCNS_NSE23_MASK (0x800000U) +#define GPIO_PCNS_NSE23_SHIFT (23U) +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) + +#define GPIO_PCNS_NSE24_MASK (0x1000000U) +#define GPIO_PCNS_NSE24_SHIFT (24U) +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) + +#define GPIO_PCNS_NSE25_MASK (0x2000000U) +#define GPIO_PCNS_NSE25_SHIFT (25U) +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) + +#define GPIO_PCNS_NSE26_MASK (0x4000000U) +#define GPIO_PCNS_NSE26_SHIFT (26U) +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) + +#define GPIO_PCNS_NSE27_MASK (0x8000000U) +#define GPIO_PCNS_NSE27_SHIFT (27U) +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) + +#define GPIO_PCNS_NSE28_MASK (0x10000000U) +#define GPIO_PCNS_NSE28_SHIFT (28U) +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) + +#define GPIO_PCNS_NSE29_MASK (0x20000000U) +#define GPIO_PCNS_NSE29_SHIFT (29U) +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) + +#define GPIO_PCNS_NSE30_MASK (0x40000000U) +#define GPIO_PCNS_NSE30_SHIFT (30U) +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) + +#define GPIO_PCNS_NSE31_MASK (0x80000000U) +#define GPIO_PCNS_NSE31_SHIFT (31U) +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) +/*! @} */ + +/*! @name ICNS - Interrupt Control Nonsecure */ +/*! @{ */ + +#define GPIO_ICNS_NSE0_MASK (0x1U) +#define GPIO_ICNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) + +#define GPIO_ICNS_NSE1_MASK (0x2U) +#define GPIO_ICNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) +/*! @} */ + +/*! @name PCNP - Pin Control Nonprivilege */ +/*! @{ */ + +#define GPIO_PCNP_NPE0_MASK (0x1U) +#define GPIO_PCNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) + +#define GPIO_PCNP_NPE1_MASK (0x2U) +#define GPIO_PCNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) + +#define GPIO_PCNP_NPE2_MASK (0x4U) +#define GPIO_PCNP_NPE2_SHIFT (2U) +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) + +#define GPIO_PCNP_NPE3_MASK (0x8U) +#define GPIO_PCNP_NPE3_SHIFT (3U) +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) + +#define GPIO_PCNP_NPE4_MASK (0x10U) +#define GPIO_PCNP_NPE4_SHIFT (4U) +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) + +#define GPIO_PCNP_NPE5_MASK (0x20U) +#define GPIO_PCNP_NPE5_SHIFT (5U) +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) + +#define GPIO_PCNP_NPE6_MASK (0x40U) +#define GPIO_PCNP_NPE6_SHIFT (6U) +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) + +#define GPIO_PCNP_NPE7_MASK (0x80U) +#define GPIO_PCNP_NPE7_SHIFT (7U) +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) + +#define GPIO_PCNP_NPE8_MASK (0x100U) +#define GPIO_PCNP_NPE8_SHIFT (8U) +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) + +#define GPIO_PCNP_NPE9_MASK (0x200U) +#define GPIO_PCNP_NPE9_SHIFT (9U) +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) + +#define GPIO_PCNP_NPE10_MASK (0x400U) +#define GPIO_PCNP_NPE10_SHIFT (10U) +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) + +#define GPIO_PCNP_NPE11_MASK (0x800U) +#define GPIO_PCNP_NPE11_SHIFT (11U) +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) + +#define GPIO_PCNP_NPE12_MASK (0x1000U) +#define GPIO_PCNP_NPE12_SHIFT (12U) +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) + +#define GPIO_PCNP_NPE13_MASK (0x2000U) +#define GPIO_PCNP_NPE13_SHIFT (13U) +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) + +#define GPIO_PCNP_NPE14_MASK (0x4000U) +#define GPIO_PCNP_NPE14_SHIFT (14U) +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) + +#define GPIO_PCNP_NPE15_MASK (0x8000U) +#define GPIO_PCNP_NPE15_SHIFT (15U) +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) + +#define GPIO_PCNP_NPE16_MASK (0x10000U) +#define GPIO_PCNP_NPE16_SHIFT (16U) +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) + +#define GPIO_PCNP_NPE17_MASK (0x20000U) +#define GPIO_PCNP_NPE17_SHIFT (17U) +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) + +#define GPIO_PCNP_NPE18_MASK (0x40000U) +#define GPIO_PCNP_NPE18_SHIFT (18U) +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) + +#define GPIO_PCNP_NPE19_MASK (0x80000U) +#define GPIO_PCNP_NPE19_SHIFT (19U) +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) + +#define GPIO_PCNP_NPE20_MASK (0x100000U) +#define GPIO_PCNP_NPE20_SHIFT (20U) +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) + +#define GPIO_PCNP_NPE21_MASK (0x200000U) +#define GPIO_PCNP_NPE21_SHIFT (21U) +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) + +#define GPIO_PCNP_NPE22_MASK (0x400000U) +#define GPIO_PCNP_NPE22_SHIFT (22U) +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) + +#define GPIO_PCNP_NPE23_MASK (0x800000U) +#define GPIO_PCNP_NPE23_SHIFT (23U) +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) + +#define GPIO_PCNP_NPE24_MASK (0x1000000U) +#define GPIO_PCNP_NPE24_SHIFT (24U) +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) + +#define GPIO_PCNP_NPE25_MASK (0x2000000U) +#define GPIO_PCNP_NPE25_SHIFT (25U) +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) + +#define GPIO_PCNP_NPE26_MASK (0x4000000U) +#define GPIO_PCNP_NPE26_SHIFT (26U) +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) + +#define GPIO_PCNP_NPE27_MASK (0x8000000U) +#define GPIO_PCNP_NPE27_SHIFT (27U) +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) + +#define GPIO_PCNP_NPE28_MASK (0x10000000U) +#define GPIO_PCNP_NPE28_SHIFT (28U) +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) + +#define GPIO_PCNP_NPE29_MASK (0x20000000U) +#define GPIO_PCNP_NPE29_SHIFT (29U) +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) + +#define GPIO_PCNP_NPE30_MASK (0x40000000U) +#define GPIO_PCNP_NPE30_SHIFT (30U) +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) + +#define GPIO_PCNP_NPE31_MASK (0x80000000U) +#define GPIO_PCNP_NPE31_SHIFT (31U) +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) +/*! @} */ + +/*! @name ICNP - Interrupt Control Nonprivilege */ +/*! @{ */ + +#define GPIO_ICNP_NPE0_MASK (0x1U) +#define GPIO_ICNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) + +#define GPIO_ICNP_NPE1_MASK (0x2U) +#define GPIO_ICNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of GPIO_PDR */ +#define GPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_IRQS_MASK (0x100000U) +#define GPIO_ICR_IRQS_SHIFT (20U) +/*! IRQS - Interrupt Select + * 0b0..Interrupt, trigger output, or DMA request 0 + * 0b1..Interrupt, trigger output, or DMA request 1 + */ +#define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) + +#define GPIO_ICR_LK_MASK (0x800000U) +#define GPIO_ICR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Lock + * 0b1..Do not lock + */ +#define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of GPIO_ICR */ +#define GPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of GPIO_ISFR */ +#define GPIO_ISFR_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } + #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } + #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif +/* Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} +#define GPIO_IRQS_1 {GPIO01_IRQn, GPIO11_IRQn, GPIO21_IRQn, GPIO31_IRQn,GPIO41_IRQn,GPIO51_IRQn} + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __O uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[24]; + __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[24]; + __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[24]; + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ + uint8_t RESERVED_5[28]; + __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Data Lines */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - Transmit Control */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - Transmit Configuration 1 */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(TFW +1) + * 0b111..8 + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - Transmit Configuration 2 */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with receiver + * 0b10..Synchronous with another SAI transmitter + * 0b11..Synchronous with another SAI receiver + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - Transmit Configuration 3 */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0x30000U) +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +#define I2S_TCR3_CFR_MASK (0x3000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - Transmit Configuration 4 */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode + * 0b1..Output mode + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable FIFO packing + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - Transmit Configuration 5 */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - Transmit FIFO */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) + +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be written + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - Transmit Mask */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - Receive Control */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not full + * 0b1..Full + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Receive overflow detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable after completing the current frame + * 0b1..Enable + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - Receive Configuration 1 */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(RFW value + 1) + * 0b111..8 + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - Receive Configuration 2 */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with transmitter + * 0b10..Synchronous with another SAI receiver + * 0b11..Synchronous with another SAI transmitter + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - Receive Configuration 3 */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + * 0b00000..Word 1 + * 0b00001..Word 2 + * 0b00010-0b11110..Word (WDFL value + 1) + * 0b11111..Word 32 + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0x30000U) +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +#define I2S_RCR3_CFR_MASK (0x3000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - Receive Configuration 4 */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - Receive Configuration 5 */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - Receive FIFO */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - Receive Mask */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + +/*! @name MCR - MCLK Control */ +/*! @{ */ + +#define I2S_MCR_DIV_MASK (0xFFU) +#define I2S_MCR_DIV_SHIFT (0U) +/*! DIV - MCLK Post Divide */ +#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) + +#define I2S_MCR_DIVEN_MASK (0x800000U) +#define I2S_MCR_DIVEN_SHIFT (23U) +/*! DIVEN - MCLK Post Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) + +#define I2S_MCR_MSEL_MASK (0x3000000U) +#define I2S_MCR_MSEL_SHIFT (24U) +/*! MSEL - MCLK Select + * 0b00..Controller clock (MCLK) option 1 + * 0b01..Reserved + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) + +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..Input + * 0b1..Output + */ +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b1..Disabled, if configured + * 0b0..Enabled + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b1..Enable HDR OK + * 0b0..Disable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b1..Handled automatically + * 0b0..No CCC message handled + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b1..I3C bus in HDR-DDR mode + * 0b0..I3C bus not in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b1..Received message pending + * 0b0..No received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b1..Transmit buffer not full + * 0b0..Transmit buffer full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error + * 0b1..Overrun error + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Underrun error + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error + * 0b1..Terminated error + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error + * 0b1..Invalid start error + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error + * 0b1..Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error + * 0b1..Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b1..Full + * 0b0..Not full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b1..Empty + * 0b0..Not empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) +#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) +/*! I2CRST - I2C Software Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b1..Subscriber capable + * 0b0..Not subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b1..Write capable + * 0b0..Not write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + * *.. + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + * *.. + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Target Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10-Bit Static Address */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b1..I2C static address + * 0b0..I3C dynamic address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b1..NACKed (not acknowledged) + * 0b0..Not NACKed + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start + * 0b1..Target requesting START + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done + * 0b1..Done + * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete + * 0b1..Complete + * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b1..Receive message pending + * 0b0..No receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b1..Receive buffer or FIFO not full + * 0b0..Receive buffer or FIFO full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won + * 0b1..IBI arbitration won + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b1..Error or warning + * 0b0..No error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b1..Without mandatory IBI byte + * 0b0..With mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b1..Valid DA assigned + * 0b0..No valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + * *.. + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Target Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x20 */ + __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ + __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ + __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ + __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ + __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ + __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ + __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ + __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ + __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ + __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ + __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ + __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[160]; + __IO uint32_t FREQMEAS_REF; /**< Selection for Frequency Measurement Reference Clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for Frequency Measurement Target Clock, offset: 0x184 */ + uint8_t RESERVED_5[24]; + __IO uint32_t CTIMER3CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A0 */ + __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ + __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ + __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ + __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ + __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ + __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ + __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ + __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ + uint8_t RESERVED_7[140]; + __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ + uint8_t RESERVED_8[28]; + __IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[48]; + __IO uint32_t ADC1_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_10[144]; + struct { /* offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ + __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ + __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ + __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ + uint8_t RESERVED_0[12]; + } QDCN[2]; + __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ + __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ + uint8_t RESERVED_11[12]; + __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ + __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ + uint8_t RESERVED_13[24]; + __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ + uint8_t RESERVED_14[64]; + __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ + uint8_t RESERVED_15[188]; + __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ + uint8_t RESERVED_17[28]; + __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ + uint8_t RESERVED_18[28]; + __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ + uint8_t RESERVED_19[28]; + __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ + uint8_t RESERVED_20[28]; + __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ + uint8_t RESERVED_21[28]; + __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ + uint8_t RESERVED_22[28]; + __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ + uint8_t RESERVED_23[92]; + __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ + __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ + __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ + __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ + __O uint32_t DMA0_REQ_ENABLE0_TOG; /**< DMA0 Request Enable0, offset: 0x70C */ + __IO uint32_t DMA0_REQ_ENABLE1; /**< DMA0 Request Enable1, offset: 0x710 */ + __O uint32_t DMA0_REQ_ENABLE1_SET; /**< DMA0 Request Enable1, offset: 0x714 */ + __O uint32_t DMA0_REQ_ENABLE1_CLR; /**< DMA0 Request Enable1, offset: 0x718 */ + __O uint32_t DMA0_REQ_ENABLE1_TOG; /**< DMA0 Request Enable1, offset: 0x71C */ + __IO uint32_t DMA0_REQ_ENABLE2; /**< DMA0 Request Enable2, offset: 0x720 */ + __O uint32_t DMA0_REQ_ENABLE2_SET; /**< DMA0 Request Enable2, offset: 0x724 */ + __O uint32_t DMA0_REQ_ENABLE2_CLR; /**< DMA0 Request Enable2, offset: 0x728 */ + __O uint32_t DMA0_REQ_ENABLE2_TOG; /**< DMA0 Request Enable2, offset: 0x72C */ + __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ + __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ + __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ + uint8_t RESERVED_24[68]; + __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ + __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ + __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ + __O uint32_t DMA1_REQ_ENABLE0_TOG; /**< DMA1 Request Enable0, offset: 0x78C */ + __IO uint32_t DMA1_REQ_ENABLE1; /**< DMA1 Request Enable1, offset: 0x790 */ + __O uint32_t DMA1_REQ_ENABLE1_SET; /**< DMA1 Request Enable1, offset: 0x794 */ + __O uint32_t DMA1_REQ_ENABLE1_CLR; /**< DMA1 Request Enable1, offset: 0x798 */ + __O uint32_t DMA1_REQ_ENABLE1_TOG; /**< DMA1 Request Enable1, offset: 0x79C */ + __IO uint32_t DMA1_REQ_ENABLE2; /**< DMA1 Request Enable2, offset: 0x7A0 */ + __O uint32_t DMA1_REQ_ENABLE2_SET; /**< DMA1 Request Enable2, offset: 0x7A4 */ + __O uint32_t DMA1_REQ_ENABLE2_CLR; /**< DMA1 Request Enable2, offset: 0x7A8 */ + __O uint32_t DMA1_REQ_ENABLE2_TOG; /**< DMA1 Request Enable2, offset: 0x7AC */ + __IO uint32_t DMA1_REQ_ENABLE3; /**< DMA1 Request Enable3, offset: 0x7B0 */ + __O uint32_t DMA1_REQ_ENABLE3_SET; /**< DMA1 Request Enable3, offset: 0x7B4 */ + __O uint32_t DMA1_REQ_ENABLE3_CLR; /**< DMA1 Request Enable3, offset: 0x7B8 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMER0CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER0TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER1TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER2TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX - Inputmux Register for SMARTDMA Arch B Inputs */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) +/*! INP - Input number select to SmartDMA ARCHB input + * 0b0000000..FlexIO interrupt is selected as input + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..Reserved + * 0b0010001..Reserved + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..MRT0 MRT_CH0_IRQ input is selected + * 0b0010101..MRT0 MRT_CH1_IRQ input is selected + * 0b0010110..CTIMER4_MAT3 input is selected + * 0b0010111..CTIMER4_MAT2 input is selected + * 0b0011000..CTIMER3_MAT3 input is selected + * 0b0011001..CTIMER3_MAT2 input is selected + * 0b0011010..CTIMER1_MAT3 input is selected + * 0b0011011..CTIMER1_MAT2 input is selected + * 0b0011100..UTICK0 UTICK_IRQ input is selected + * 0b0011101..WWDT0 WDT0_IRQ input is selected + * 0b0011110..ADC0 ADC0_IRQ input is selected + * 0b0011111..CMP0_IRQ input is selected + * 0b0100000..Reserved + * 0b0100001..LP_FLEXCOMM7_IRQ input is selected + * 0b0100010..LP_FLEXCOMM6_IRQ input is selected + * 0b0100011..LP_FLEXCOMM5_IRQ input is selected + * 0b0100100..LP_FLEXCOMM4_IRQ input is selected + * 0b0100101..LP_FLEXCOMM3_IRQ input is selected + * 0b0100110..LP_FLEXCOMM2_IRQ input is selected + * 0b0100111..LP_FLEXCOMM1_IRQ input is selected + * 0b0101000..LP_FLEXCOMM0_IRQ input is selected + * 0b0101001..DMA0_IRQ input is selected + * 0b0101010..DMA1_IRQ input is selected + * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure + * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR + * operation. input is selected + * 0b0101100..RTC_COMBO_IRQ input is selected + * 0b0101101..ARM_TXEV input is selected + * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CMP0_OUT input is selected + * 0b0110010..usb0 start of frame input is selected + * 0b0110011..usb1 start of frame input is selected + * 0b0110100..OSTIMER0 OS_EVENT_TIMER_IRQ input is selected + * 0b0110101..ADC1_IRQ input is selected + * 0b0110110..CMP0_IRQ/CMP1_IRQ input is selected + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..PWM0_IRQ input is selected + * 0b0111010..PWM1_IRQ input is selected + * 0b0111011..QDC0_IRQ input is selected + * 0b0111100..QDC1_IRQ input is selected + * 0b0111101..EVTG_OUT0A input is selected + * 0b0111110..EVTG_OUT1A input is selected + * 0b0111111..Reserved + * 0b1000000..Reserved + * 0b1000001..GPIO1_alias0 GPIO1 Pin Event Trig 0 input is selected + * 0b1000010..GPIO1_alias1 GPIO1 Pin Event Trig 1 input is selected + * 0b1000011..GPIO2_alias0 GPIO2 Pin Event Trig 0 input is selected + * 0b1000100..GPIO2_alias1 GPIO2 Pin Event Trig 1 input is selected + * 0b1000101..GPIO3_alias0 GPIO3 Pin Event Trig 0 input is selected + * 0b1000110..GPIO3_alias1 GPIO3 Pin Event Trig 1 input is selected + * 0b1000111..FlexIO Shifter DMA Request 0 is selected + * 0b1001000..FlexIO Shifter DMA Request 1 is selected + * 0b1001001..FlexIO Shifter DMA Request 2 is selected + * 0b1001010..FlexIO Shifter DMA Request 3 is selected + * 0b1001011..FlexIO Shifter DMA Request 4 is selected + * 0b1001100..FlexIO Shifter DMA Request 5 is selected + * 0b1001101..FlexIO Shifter DMA Request 6 is selected + * 0b1001110..FlexIO Shifter DMA Request 7 is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_COUNT (8U) + +/*! @name INPUTMUX_GPIO_INT_PINTSEL - Pin Interrupt Select */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT (0U) +/*! INP - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INP = (x * + * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + * 0b0000000..GPIO P0_0 input is selected + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..GPIO P0_16 input is selected + * 0b0010001..GPIO P0_17 input is selected + * 0b0010010..GPIO P0_18 input is selected + * 0b0010011..GPIO P0_19 input is selected + * 0b0010100..GPIO P0_20 input is selected + * 0b0010101..GPIO P0_21 input is selected + * 0b0010110..GPIO P0_22 input is selected + * 0b0010111..GPIO P0_23 input is selected + * 0b0011000..GPIO P0_24 input is selected + * 0b0011001..GPIO P0_25 input is selected + * 0b0011010..GPIO P0_26 input is selected + * 0b0011011..GPIO P0_27 input is selected + * 0b0011100..GPIO P0_28 input is selected + * 0b0011101..GPIO P0_29 input is selected + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..GPIO P1_0 input is selected + * 0b0100001..GPIO P1_1 input is selected + * 0b0100010..GPIO P1_2 input is selected + * 0b0100011..GPIO P1_3 input is selected + * 0b0100100..GPIO P1_4 input is selected + * 0b0100101..GPIO P1_5 input is selected + * 0b0100110..GPIO P1_6 input is selected + * 0b0100111..GPIO P1_7 input is selected + * 0b0101000..GPIO P1_8 input is selected + * 0b0101001..GPIO P1_9 input is selected + * 0b0101010..GPIO P1_10 input is selected + * 0b0101011..GPIO P1_11 input is selected + * 0b0101100..GPIO P1_12 input is selected + * 0b0101101..GPIO P1_13 input is selected + * 0b0101110..GPIO P1_14 input is selected + * 0b0101111..GPIO P1_15 input is selected + * 0b0110000..GPIO P1_16 input is selected + * 0b0110001..GPIO P1_17 input is selected + * 0b0110010..GPIO P1_18 input is selected + * 0b0110011..GPIO P1_19 input is selected + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..GPIO P1_30 input is selected + * 0b0111111..GPIO P1_31 input is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT)) & INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_COUNT (8U) + +/*! @name FREQMEAS_REF - Selection for Frequency Measurement Reference Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function reference clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for Frequency Measurement Target Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER3TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER4TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) +/*! @} */ + +/*! @name CMP0_TRIG - CMP0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER0_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC1_tcomp[0] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT1 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT3 input is selected + * 0b00001001..CTIMER4_MAT3 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGN_ADC1_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC1 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT2 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT2 input is selected + * 0b00001001..CTIMER4_MAT1 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) + +/*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_TRIG */ +#define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) + +/*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) +/*! INP - QDC1 HOME input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_HOME */ +#define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) + +/*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 INDEX input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_INDEX */ +#define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) + +/*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 PHASEB input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEB */ +#define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) + +/*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) +/*! INP - QDC1 PHASEA input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEA */ +#define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) + +/*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA - PWM0 Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM0_EXTFORCE - PWM0 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM_FAULT_FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_COUNT (4U) + +/*! @name FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC - PWM1 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM1_EXTFORCE - PWM1 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_FAULT */ +#define INPUTMUX_FLEXPWM1_FAULT_COUNT (4U) + +/*! @name PWM0_EXT_CLK - PWM0 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM0 + * 0b000..FRO16K input is selected + * 0b001..OSC_32k input is selected + * 0b010..EVTG_OUT0A input is selected + * 0b011..EVTG_OUT1A input is selected + * 0b100..TRIG_IN0 input is selected + * 0b101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM1 + * 0b0000..FRO16K input is selected + * 0b0001..OSC_32k input is selected + * 0b0010..EVTG_OUT0A input is selected + * 0b0011..EVTG_OUT1A input is selected + * 0b0100..TRIG_IN0 input is selected + * 0b0101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) +/*! INP - EVTG trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT3 input is selected + * 0b000111..CTIMER1_MAT3 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER2_MAT2 input is selected + * 0b001010..CTIMER3_MAT2 input is selected + * 0b001011..CTIMER4_MAT2 input is selected + * 0b001100..Reserved + * 0b001101..PINT GPIO_INT_BMAT input is selected + * 0b001110..ADC0_IRQ input is selected + * 0b001111..ADC1_IRQ input is selected + * 0b010000..ADC0_tcomp[0] input is selected + * 0b010001..ADC0_tcomp[1] input is selected + * 0b010010..ADC0_tcomp[2] input is selected + * 0b010011..ADC0_tcomp[3] input is selected + * 0b010100..ADC1_tcomp[0] input is selected + * 0b010101..ADC1_tcomp[1] input is selected + * 0b010110..ADC1_tcomp[2] input is selected + * 0b010111..ADC1_tcomp[3] input is selected + * 0b011000..CMP0_OUT input is selected + * 0b011001..CMP1_OUT input is selected + * 0b011010..Reserved + * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected + * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected + * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected + * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101011..QDC0_CMP/POS_MATCH input is selected + * 0b101100..QDC1_CMP/POS_MATCH input is selected + * 0b101101..TRIG_IN0 input is selected + * 0b101110..TRIG_IN1 input is selected + * 0b101111..TRIG_IN2 input is selected + * 0b110000..TRIG_IN3 input is selected + * 0b110001..LPTMR0 input is selected + * 0b110010..LPTMR1 input is selected + * 0b110011..Reserved + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) + +/*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..ADC0_IRQ input is selected + * 0b000011..ADC1_IRQ input is selected + * 0b000100..ADC0_tcomp[0] input is selected + * 0b000101..ADC1_tcomp[0] input is selected + * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b001110..QDC0_CMP/POS_MATCH input is selected + * 0b001111..QDC1_CMP/POS_MATCH input is selected + * 0b010000..EVTG_OUT0A input is selected + * 0b010001..EVTG_OUT0B input is selected + * 0b010010..EVTG_OUT1A input is selected + * 0b010011..EVTG_OUT1B input is selected + * 0b010100..EVTG_OUT2A input is selected + * 0b010101..EVTG_OUT2B input is selected + * 0b010110..EVTG_OUT3A input is selected + * 0b010111..EVTG_OUT3B input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..LPTMR0 input is selected + * 0b011011..LPTMR1 input is selected + * 0b011100..Reserved + * 0b011101..Reserved + * 0b011110..Reserved + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..Reserved + * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected + * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected + * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected + * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected + * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected + * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected + * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected + * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..CMP0_OUT input is selected + * 0b101101..CMP1_OUT input is selected + * 0b101110..Reserved + * 0b101111..Reserved + * *.. + */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) + +/*! @name CMP1_TRIG - CMP1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP1 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT7 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER3_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[1] input is selected + * 0b001110..ADC1_tcomp[1] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM0 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM0_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM1_TRIG - LP_FLEXCOMM1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM1 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM1_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM2_TRIG - LP_FLEXCOMM2 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM2 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM2_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM3_TRIG - LP_FLEXCOMM3 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM3 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM3_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM3_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM4_TRIG - LP_FLEXCOMM4 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM4 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM4_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM4_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM5_TRIG - LP_FLEXCOMM5 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM5 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM5_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM5_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM6_TRIG - LP_FLEXCOMM6 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM6 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM6_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM6_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM7_TRIG - LP_FLEXCOMM7 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM7 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM7_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM7_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..PINT PIN_INT4 input is selected + * 0b0000001..PINT PIN_INT5 input is selected + * 0b0000010..PINT PIN_INT6 input is selected + * 0b0000011..PINT PIN_INT7 input is selected + * 0b0000100..Reserved + * 0b0000101..Reserved + * 0b0000110..Reserved + * 0b0000111..Reserved + * 0b0001000..Reserved + * 0b0001001..T0_MAT1 input is selected + * 0b0001010..T1_MAT1 input is selected + * 0b0001011..T2_MAT1 input is selected + * 0b0001100..T3_MAT1 input is selected + * 0b0001101..T4_MAT1 input is selected + * 0b0001110..LPTMR0 input is selected + * 0b0001111..LPTMR1 input is selected + * 0b0010000..Reserved + * 0b0010001..PINT GPIO_INT_BMAT input is selected + * 0b0010010..ADC0_tcomp[0] input is selected + * 0b0010011..ADC0_tcomp[1] input is selected + * 0b0010100..ADC0_tcomp[2] input is selected + * 0b0010101..ADC0_tcomp[3] input is selected + * 0b0010110..ADC1_tcomp[0] input is selected + * 0b0010111..ADC1_tcomp[1] input is selected + * 0b0011000..ADC1_tcomp[2] input is selected + * 0b0011001..ADC1_tcomp[3] input is selected + * 0b0011010..CMP0_OUT input is selected + * 0b0011011..CMP1_OUT input is selected + * 0b0011100..Reserved + * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected + * 0b0101101..EVTG_OUT0A input is selected + * 0b0101110..EVTG_OUT0B input is selected + * 0b0101111..EVTG_OUT1A input is selected + * 0b0110000..EVTG_OUT1B input is selected + * 0b0110001..EVTG_OUT2A input is selected + * 0b0110010..EVTG_OUT2B input is selected + * 0b0110011..EVTG_OUT3A input is selected + * 0b0110100..EVTG_OUT3B input is selected + * 0b0110101..TRIG_IN0 input is selected + * 0b0110110..TRIG_IN1 input is selected + * 0b0110111..TRIG_IN2 input is selected + * 0b0111000..TRIG_IN3 input is selected + * 0b0111001..TRIG_IN4 input is selected + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..Reserved + * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected + * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected + * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected + * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected + * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected + * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected + * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected + * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected + * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected + * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected + * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected + * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected + * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected + * 0b1001100..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) + +/*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_SET - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_CLR - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_TOG - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to RE9_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1 - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_SET - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_CLR - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_TOG - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2 - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_SET - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ876_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_CLR - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_TOG - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3 - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_SET - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_CLR - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0 - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_SET - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_CLR - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_TOG - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to RE9_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1 - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_SET - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_CLR - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_TOG - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2 - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_SET - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ876_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_CLR - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_TOG - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3 - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_SET - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_CLR - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3. */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif +/* Backward compatibility for INPUTMUX */ +#define INPUTMUX INPUTMUX0 + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer + * @{ + */ + +/** INTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t INTM_MM; /**< Monitor Mode, offset: 0x0 */ + __O uint32_t INTM_IACK; /**< Interrupt Acknowledge, offset: 0x4 */ + struct { /* offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_IRQSEL; /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_LATENCY; /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */ + __IO uint32_t INTM_TIMER; /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */ + __I uint32_t INTM_STATUS; /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */ + } MON[4]; +} INTM_Type; + +/* ---------------------------------------------------------------------------- + -- INTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Register_Masks INTM Register Masks + * @{ + */ + +/*! @name INTM_MM - Monitor Mode */ +/*! @{ */ + +#define INTM_INTM_MM_MM_MASK (0x1U) +#define INTM_INTM_MM_MM_SHIFT (0U) +/*! MM - Monitor Mode + * 0b1..Enable + * 0b0..Disable + */ +#define INTM_INTM_MM_MM(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK) +/*! @} */ + +/*! @name INTM_IACK - Interrupt Acknowledge */ +/*! @{ */ + +#define INTM_INTM_IACK_IRQ_MASK (0x3FFU) +#define INTM_INTM_IACK_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_INTM_IACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK) +/*! @} */ + +/*! @name MON_INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_IRQSEL_IRQ_MASK (0x3FFU) +#define INTM_MON_INTM_IRQSEL_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_MON_INTM_IRQSEL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_IRQSEL_IRQ_SHIFT)) & INTM_MON_INTM_IRQSEL_IRQ_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_IRQSEL */ +#define INTM_MON_INTM_IRQSEL_COUNT (4U) + +/*! @name MON_INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_LATENCY_LAT_MASK (0xFFFFFFU) +#define INTM_MON_INTM_LATENCY_LAT_SHIFT (0U) +/*! LAT - Latency */ +#define INTM_MON_INTM_LATENCY_LAT(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_LATENCY_LAT_SHIFT)) & INTM_MON_INTM_LATENCY_LAT_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_LATENCY */ +#define INTM_MON_INTM_LATENCY_COUNT (4U) + +/*! @name MON_INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_TIMER_TIMER_MASK (0xFFFFFFU) +#define INTM_MON_INTM_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer */ +#define INTM_MON_INTM_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_TIMER_TIMER_SHIFT)) & INTM_MON_INTM_TIMER_TIMER_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_TIMER */ +#define INTM_MON_INTM_TIMER_COUNT (4U) + +/*! @name MON_INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_STATUS_STATUS_MASK (0x1U) +#define INTM_MON_INTM_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Monitor status + * 0b1..Exceeded + * 0b0..Did not exceed + */ +#define INTM_MON_INTM_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_STATUS_STATUS_SHIFT)) & INTM_MON_INTM_STATUS_STATUS_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_STATUS */ +#define INTM_MON_INTM_STATUS_COUNT (4U) + + +/*! + * @} + */ /* end of group INTM_Register_Masks */ + + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/*! + * @} + */ /* end of group INTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ITRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer + * @{ + */ + +/** ITRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ + __IO uint32_t STATUS1; /**< ITRC IN16 to IN47 Status, offset: 0x4 */ + __IO uint32_t OUT_SEL[7][2]; /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t OUT_SEL_1[7][2]; /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t OUT_SEL_2[7][2]; /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_2[48]; + __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ + __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ +} ITRC_Type; + +/* ---------------------------------------------------------------------------- + -- ITRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Register_Masks ITRC Register Masks + * @{ + */ + +/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ +/*! @{ */ + +#define ITRC_STATUS_IN0_STATUS_MASK (0x1U) +#define ITRC_STATUS_IN0_STATUS_SHIFT (0U) +/*! IN0_STATUS - GDET0 & 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) + +#define ITRC_STATUS_IN1_STATUS_MASK (0x2U) +#define ITRC_STATUS_IN1_STATUS_SHIFT (1U) +/*! IN1_STATUS - TDET tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) + +#define ITRC_STATUS_IN2_STATUS_MASK (0x4U) +#define ITRC_STATUS_IN2_STATUS_SHIFT (2U) +/*! IN2_STATUS - Code Watchdog 0 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) + +#define ITRC_STATUS_IN3_STATUS_MASK (0x8U) +#define ITRC_STATUS_IN3_STATUS_SHIFT (3U) +/*! IN3_STATUS - VDD_MAIN volt tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) + +#define ITRC_STATUS_IN4_STATUS_MASK (0x10U) +#define ITRC_STATUS_IN4_STATUS_SHIFT (4U) +/*! IN4_STATUS - SPC VDD_CORE_LVD detect. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) + +#define ITRC_STATUS_IN5_STATUS_MASK (0x20U) +#define ITRC_STATUS_IN5_STATUS_SHIFT (5U) +/*! IN5_STATUS - Watch Dog timer event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) + +#define ITRC_STATUS_IN6_STATUS_MASK (0x40U) +#define ITRC_STATUS_IN6_STATUS_SHIFT (6U) +/*! IN6_STATUS - Flash ECC mismatch event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) + +#define ITRC_STATUS_IN7_STATUS_MASK (0x80U) +#define ITRC_STATUS_IN7_STATUS_SHIFT (7U) +/*! IN7_STATUS - AHB secure bus checkers detected illegal access. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) + +#define ITRC_STATUS_IN8_STATUS_MASK (0x100U) +#define ITRC_STATUS_IN8_STATUS_SHIFT (8U) +/*! IN8_STATUS - ELS error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) + +#define ITRC_STATUS_IN9_STATUS_MASK (0x200U) +#define ITRC_STATUS_IN9_STATUS_SHIFT (9U) +/*! IN9_STATUS - SPC VDD_CORE glitch detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN9_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK) + +#define ITRC_STATUS_IN10_STATUS_MASK (0x400U) +#define ITRC_STATUS_IN10_STATUS_SHIFT (10U) +/*! IN10_STATUS - PKC module detected an error event. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) + +#define ITRC_STATUS_IN11_STATUS_MASK (0x800U) +#define ITRC_STATUS_IN11_STATUS_SHIFT (11U) +/*! IN11_STATUS - Code Watchdog 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN11_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK) + +#define ITRC_STATUS_IN112_STATUS_MASK (0x1000U) +#define ITRC_STATUS_IN112_STATUS_SHIFT (12U) +/*! IN112_STATUS - Watchdog 1 timer event interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN112_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN112_STATUS_SHIFT)) & ITRC_STATUS_IN112_STATUS_MASK) + +#define ITRC_STATUS_IN113_STATUS_MASK (0x2000U) +#define ITRC_STATUS_IN113_STATUS_SHIFT (13U) +/*! IN113_STATUS - FREQME out of range status output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN113_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN113_STATUS_SHIFT)) & ITRC_STATUS_IN113_STATUS_MASK) + +#define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) +#define ITRC_STATUS_IN14_STATUS_SHIFT (14U) +/*! IN14_STATUS - Software event 0 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) + +#define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) +#define ITRC_STATUS_IN15_STATUS_SHIFT (15U) +/*! IN15_STATUS - Software event 1 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) + +#define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) +#define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) +/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) + +#define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) +#define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) +/*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) + +#define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) +#define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) +/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) + +#define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) +#define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) +/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) + +#define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) +#define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) +/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) + +#define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) +#define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) +/*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) + +#define ITRC_STATUS_OUT6_STATUS_MASK (0x400000U) +#define ITRC_STATUS_OUT6_STATUS_SHIFT (22U) +/*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK) +/*! @} */ + +/*! @name STATUS1 - ITRC IN16 to IN47 Status */ +/*! @{ */ + +#define ITRC_STATUS1_IN16_STATUS_MASK (0x1U) +#define ITRC_STATUS1_IN16_STATUS_SHIFT (0U) +/*! IN16_STATUS - SSPC VDD_SYS_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN16_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK) + +#define ITRC_STATUS1_IN17_STATUS_MASK (0x2U) +#define ITRC_STATUS1_IN17_STATUS_SHIFT (1U) +/*! IN17_STATUS - SPC VDD_IO_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN17_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK) + +#define ITRC_STATUS1_IN18_STATUS_MASK (0x4U) +#define ITRC_STATUS1_IN18_STATUS_SHIFT (2U) +/*! IN18_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN18_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK) + +#define ITRC_STATUS1_IN19_STATUS_MASK (0x8U) +#define ITRC_STATUS1_IN19_STATUS_SHIFT (3U) +/*! IN19_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN19_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK) + +#define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) +#define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) +/*! IN20_STATUS - VDD_MAIN clock tamper output event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN20_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK) + +#define ITRC_STATUS1_IN24_21_STATUS_MASK (0x1E0U) +#define ITRC_STATUS1_IN24_21_STATUS_SHIFT (5U) +/*! IN24_21_STATUS - INTM interrupt monitor error 3~0 event occurred. + * 0b0000..Output not triggered. + * 0b0001..Output has been triggered. + */ +#define ITRC_STATUS1_IN24_21_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_21_STATUS_SHIFT)) & ITRC_STATUS1_IN24_21_STATUS_MASK) + +#define ITRC_STATUS1_IN32_25_STATUS_MASK (0x1FE00U) +#define ITRC_STATUS1_IN32_25_STATUS_SHIFT (9U) +/*! IN32_25_STATUS - MSF SOCTRIM 7~0 ECC error event occurred. + * 0b00000000..Output not triggered. + * 0b00000001..Output has been triggered. + */ +#define ITRC_STATUS1_IN32_25_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_25_STATUS_SHIFT)) & ITRC_STATUS1_IN32_25_STATUS_MASK) + +#define ITRC_STATUS1_IN33_STATUS_MASK (0x20000U) +#define ITRC_STATUS1_IN33_STATUS_SHIFT (17U) +/*! IN33_STATUS - GDET0/1 SFR error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN33_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK) + +#define ITRC_STATUS1_IN34_STATUS_MASK (0x40000U) +#define ITRC_STATUS1_IN34_STATUS_SHIFT (18U) +/*! IN34_STATUS - SPC VDD_CORE high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN34_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK) + +#define ITRC_STATUS1_IN35_STATUS_MASK (0x80000U) +#define ITRC_STATUS1_IN35_STATUS_SHIFT (19U) +/*! IN35_STATUS - SPC VDD_SYS_HVD high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN35_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK) + +#define ITRC_STATUS1_IN36_STATUS_MASK (0x100000U) +#define ITRC_STATUS1_IN36_STATUS_SHIFT (20U) +/*! IN36_STATUS - SPC VDD_IO high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN36_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK) + +#define ITRC_STATUS1_IN37_STATUS_MASK (0x200000U) +#define ITRC_STATUS1_IN37_STATUS_SHIFT (21U) +/*! IN37_STATUS - FLEXSPI GCM error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN37_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK) + +#define ITRC_STATUS1_IN46_STATUS_MASK (0x40000000U) +#define ITRC_STATUS1_IN46_STATUS_SHIFT (30U) +/*! IN46_STATUS - SM3 SGI error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN46_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN46_STATUS_SHIFT)) & ITRC_STATUS1_IN46_STATUS_MASK) + +#define ITRC_STATUS1_IN47_STATUS_MASK (0x80000000U) +#define ITRC_STATUS1_IN47_STATUS_SHIFT (31U) +/*! IN47_STATUS - TRNG HW error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN47_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK) +/*! @} */ + +/*! @name OUTX_SEL_OUTX_SELY_OUT_SEL - Trigger Source IN0 to IN15 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT (0U) +/*! IN0_SELn - Selects digital glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT (2U) +/*! IN1_SELn - Selects TDET event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT (4U) +/*! IN2_SELn - Selects Code Watchdog 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) +/*! IN3_SELn - Selects VDD_MAIN voltage tamper event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT (8U) +/*! IN4_SELn - Selects low-voltage event on VDD_CORE rail as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT (10U) +/*! IN5_SELn - Selects Watchdog 0 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT (12U) +/*! IN6_SELn - Selects Flash ECC mismatch event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT (14U) +/*! IN7_SELn - Selects AHB secure bus or MBC bus illegal access event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT (16U) +/*! IN8_SELn - Selects ELS error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT (18U) +/*! IN9_SELn - Selects SPC VDD_CORE glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT (20U) +/*! IN10_SELn - Selects PKC error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT (22U) +/*! IN11_SELn - Selects Code Watchdog 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT (24U) +/*! IN12_SELn - Selects Watchdog 1 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT (26U) +/*! IN13_SELn - Selects FREQME out of range status output as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT (28U) +/*! IN14_SELn - Selects software event 0 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT (30U) +/*! IN15_SELn - Selects software event 1 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT2 (2U) + +/*! @name OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 - Trigger Source IN16 to IN31 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT (0U) +/*! IN16_SELn - Selects SPC VDD_SYS_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT (2U) +/*! IN17_SELn - Selects SPC VDD_IO_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT (4U) +/*! IN18_SELn - Reserved. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) +/*! IN19_SELn - Selects VDD_MAIN temperature tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) +/*! IN20_SELn - Selects VDD_MAIN clock tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT (10U) +/*! IN21_SELn - Selects INTM interrupt monitor error 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT (12U) +/*! IN22_SELn - Selects INTM interrupt monitor error 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT (14U) +/*! IN23_SELn - Selects INTM interrupt monitor error 2 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT (16U) +/*! IN24_SELn - Selects INTM interrupt monitor error 3 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT (18U) +/*! IN25_SELn - Selects MSF SOCTRIM 0 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT (20U) +/*! IN26_SELn - Selects MSF SOCTRIM 1 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT (22U) +/*! IN27_SELn - Selects MSF SOCTRIM 2 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT (24U) +/*! IN28_SELn - Selects MSF SOCTRIM 3 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT (26U) +/*! IN29_SELn - Selects MSF SOCTRIM 4 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT (28U) +/*! IN30_SELn - Selects MSF SOCTRIM 5 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT (30U) +/*! IN31_SELn - Selects MSF SOCTRIM 6 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT2 (2U) + +/*! @name OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 - Trigger source IN32 to IN47 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT (0U) +/*! IN32_SELn - Selects MSF SOCTRIM 7 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT (2U) +/*! IN33_SELn - Selects GDET0 & 1 SFR error detect as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT (4U) +/*! IN34_SELn - Selects SPC VDD_CORE_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT (6U) +/*! IN35_SELn - Selects VDD_SYS_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT (8U) +/*! IN36_SELn - Selects VDD_IO_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT (10U) +/*! IN37_SELn - Selects FLEXSPI GCM error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT (28U) +/*! IN46_SELn - Selects SM3 SGI error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT (30U) +/*! IN47_SELn - Selects TRNG HW Error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT2 (2U) + +/*! @name SW_EVENT0 - Software event 0 */ +/*! @{ */ + +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) +/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */ +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) +/*! @} */ + +/*! @name SW_EVENT1 - Software event 1 */ +/*! @{ */ + +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) +/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */ +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ITRC_Register_Masks */ + + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/*! + * @} + */ /* end of group ITRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ + uint8_t RESERVED_13[132]; + __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t MTDBR[253]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x7U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x70000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0xFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + +/*! @name MTCBR - Controller Transmit Command Burst */ +/*! @{ */ + +#define LPI2C_MTCBR_DATA_MASK (0xFFU) +#define LPI2C_MTCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) + +#define LPI2C_MTCBR_CMD_MASK (0x700U) +#define LPI2C_MTCBR_CMD_SHIFT (8U) +/*! CMD - Command */ +#define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) +/*! @} */ + +/* The count of LPI2C_MTCBR */ +#define LPI2C_MTCBR_COUNT (128U) + +/*! @name MTDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPI2C_MTDBR_DATA0_MASK (0xFFU) +#define LPI2C_MTDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data */ +#define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) + +#define LPI2C_MTDBR_DATA1_MASK (0xFF00U) +#define LPI2C_MTDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data */ +#define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) + +#define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) +#define LPI2C_MTDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data */ +#define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) + +#define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) +#define LPI2C_MTDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data */ +#define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPI2C_MTDBR */ +#define LPI2C_MTDBR_COUNT (253U) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + * *.. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ + __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ + __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ + __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ + __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ + __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ + __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_2[400]; + __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MSF_MASK (0x100U) +#define LPUART_STAT_MSF_SHIFT (8U) +/*! MSF - MODEM Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) + +#define LPUART_STAT_TSF_MASK (0x200U) +#define LPUART_STAT_TSF_SHIFT (9U) +/*! TSF - Timeout Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x700U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x7U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0xF00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x70000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0xF000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + +/*! @name MCR - MODEM Control */ +/*! @{ */ + +#define LPUART_MCR_CTS_MASK (0x1U) +#define LPUART_MCR_CTS_SHIFT (0U) +/*! CTS - Clear To Send + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) + +#define LPUART_MCR_DSR_MASK (0x2U) +#define LPUART_MCR_DSR_SHIFT (1U) +/*! DSR - Data Set Ready + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) + +#define LPUART_MCR_RIN_MASK (0x4U) +#define LPUART_MCR_RIN_SHIFT (2U) +/*! RIN - Ring Indicator + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) + +#define LPUART_MCR_DCD_MASK (0x8U) +#define LPUART_MCR_DCD_SHIFT (3U) +/*! DCD - Data Carrier Detect + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) + +#define LPUART_MCR_DTR_MASK (0x100U) +#define LPUART_MCR_DTR_SHIFT (8U) +/*! DTR - Data Terminal Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) + +#define LPUART_MCR_RTS_MASK (0x200U) +#define LPUART_MCR_RTS_SHIFT (9U) +/*! RTS - Request To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) +/*! @} */ + +/*! @name MSR - MODEM Status */ +/*! @{ */ + +#define LPUART_MSR_DCTS_MASK (0x1U) +#define LPUART_MSR_DCTS_SHIFT (0U) +/*! DCTS - Delta Clear To Send + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) + +#define LPUART_MSR_DDSR_MASK (0x2U) +#define LPUART_MSR_DDSR_SHIFT (1U) +/*! DDSR - Delta Data Set Ready + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) + +#define LPUART_MSR_DRI_MASK (0x4U) +#define LPUART_MSR_DRI_SHIFT (2U) +/*! DRI - Delta Ring Indicator + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) + +#define LPUART_MSR_DDCD_MASK (0x8U) +#define LPUART_MSR_DDCD_SHIFT (3U) +/*! DDCD - Delta Data Carrier Detect + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) + +#define LPUART_MSR_CTS_MASK (0x10U) +#define LPUART_MSR_CTS_SHIFT (4U) +/*! CTS - Clear To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) + +#define LPUART_MSR_DSR_MASK (0x20U) +#define LPUART_MSR_DSR_SHIFT (5U) +/*! DSR - Data Set Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) + +#define LPUART_MSR_RIN_MASK (0x40U) +#define LPUART_MSR_RIN_SHIFT (6U) +/*! RIN - Ring Indicator + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) + +#define LPUART_MSR_DCD_MASK (0x80U) +#define LPUART_MSR_DCD_SHIFT (7U) +/*! DCD - Data Carrier Detect + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) +/*! @} */ + +/*! @name REIR - Receiver Extended Idle */ +/*! @{ */ + +#define LPUART_REIR_IDTIME_MASK (0x3FFFU) +#define LPUART_REIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) +/*! @} */ + +/*! @name TEIR - Transmitter Extended Idle */ +/*! @{ */ + +#define LPUART_TEIR_IDTIME_MASK (0x3FFFU) +#define LPUART_TEIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) +/*! @} */ + +/*! @name HDCR - Half Duplex Control */ +/*! @{ */ + +#define LPUART_HDCR_TXSTALL_MASK (0x1U) +#define LPUART_HDCR_TXSTALL_SHIFT (0U) +/*! TXSTALL - Transmit Stall + * 0b0..No effect + * 0b1..Does not become busy + */ +#define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) + +#define LPUART_HDCR_RXSEL_MASK (0x2U) +#define LPUART_HDCR_RXSEL_SHIFT (1U) +/*! RXSEL - Receive Select + * 0b0..RXD + * 0b1..TXD + */ +#define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) + +#define LPUART_HDCR_RXWRMSK_MASK (0x4U) +#define LPUART_HDCR_RXWRMSK_SHIFT (2U) +/*! RXWRMSK - Receive FIFO Write Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) + +#define LPUART_HDCR_RXMSK_MASK (0x8U) +#define LPUART_HDCR_RXMSK_SHIFT (3U) +/*! RXMSK - Receive Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) + +#define LPUART_HDCR_RTSEXT_MASK (0xFF00U) +#define LPUART_HDCR_RTSEXT_SHIFT (8U) +/*! RTSEXT - RTS Extended */ +#define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) +/*! @} */ + +/*! @name TOCR - Timeout Control */ +/*! @{ */ + +#define LPUART_TOCR_TOEN_MASK (0xFU) +#define LPUART_TOCR_TOEN_SHIFT (0U) +/*! TOEN - Timeout Enable */ +#define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) + +#define LPUART_TOCR_TOIE_MASK (0xF00U) +#define LPUART_TOCR_TOIE_SHIFT (8U) +/*! TOIE - Timeout Interrupt Enable */ +#define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) +/*! @} */ + +/*! @name TOSR - Timeout Status */ +/*! @{ */ + +#define LPUART_TOSR_TOZ_MASK (0xFU) +#define LPUART_TOSR_TOZ_SHIFT (0U) +/*! TOZ - Timeout Zero */ +#define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) + +#define LPUART_TOSR_TOF_MASK (0xF00U) +#define LPUART_TOSR_TOF_SHIFT (8U) +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0001..Occurred + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) +/*! @} */ + +/*! @name TIMEOUT - Timeout N */ +/*! @{ */ + +#define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) +#define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) +/*! TIMEOUT - Timeout Value */ +#define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) + +#define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) +#define LPUART_TIMEOUT_CFG_SHIFT (30U) +/*! CFG - Idle Configuration + * 0b00..Becomes 1 after timeout characters are received + * 0b01..Becomes 1 when idle for timeout bit clocks + * 0b10..Becomes 1 when idle for timeout bit clocks following the next character + * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached + */ +#define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) +/*! @} */ + +/* The count of LPUART_TIMEOUT */ +#define LPUART_TIMEOUT_COUNT (4U) + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPUART_TCBR_DATA_MASK (0xFFFFU) +#define LPUART_TCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) +/*! @} */ + +/* The count of LPUART_TCBR */ +#define LPUART_TCBR_COUNT (128U) + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPUART_TDBR_DATA0_MASK (0xFFU) +#define LPUART_TDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data0 */ +#define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) + +#define LPUART_TDBR_DATA1_MASK (0xFF00U) +#define LPUART_TDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data1 */ +#define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) + +#define LPUART_TDBR_DATA2_MASK (0xFF0000U) +#define LPUART_TDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data2 */ +#define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) + +#define LPUART_TDBR_DATA3_MASK (0xFF000000U) +#define LPUART_TDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data3 */ +#define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPUART_TDBR */ +#define LPUART_TDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** LP_FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4084]; + __I uint32_t ISTAT; /**< Interrupt Status, offset: 0xFF4 */ + __IO uint32_t PSELID; /**< Peripheral Select and ID, offset: 0xFF8 */ +} LP_FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks + * @{ + */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define LP_FLEXCOMM_ISTAT_UARTTX_MASK (0x1U) +#define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT (0U) +/*! UARTTX - UART TX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTTX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK) + +#define LP_FLEXCOMM_ISTAT_UARTRX_MASK (0x2U) +#define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT (1U) +/*! UARTRX - UART RX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTRX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK) + +#define LP_FLEXCOMM_ISTAT_SPI_MASK (0x4U) +#define LP_FLEXCOMM_ISTAT_SPI_SHIFT (2U) +/*! SPI - SPI Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_SPI(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CM_MASK (0x10U) +#define LP_FLEXCOMM_ISTAT_I2CM_SHIFT (4U) +/*! I2CM - I2C Controller Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CM(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CS_MASK (0x20U) +#define LP_FLEXCOMM_ISTAT_I2CS_SHIFT (5U) +/*! I2CS - I2C Subordinate Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CS(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK) +/*! @} */ + +/*! @name PSELID - Peripheral Select and ID */ +/*! @{ */ + +#define LP_FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define LP_FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select + * 0b000..No peripheral selected + * 0b001..UART + * 0b011..I2C + * 0b111..UART and I2C + * 0b010..SPI + */ +#define LP_FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK) + +#define LP_FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define LP_FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock + * 0b0..PERSEL is writable + * 0b1..PERSEL is not writable + */ +#define LP_FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK) + +#define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK (0x10U) +#define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT (4U) +/*! UARTPRESENT - UART Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_UARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define LP_FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - LP_FLEXCOMM interface ID */ +#define LP_FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Register_Masks */ + + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - Time Interval Value */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time Interval Load Value. */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Force Load Enable + * 0b0..No force load + * 0b1..Force load + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - Timer */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Current Timer Value */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - Control */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Interrupt request + * 0b0..Disabled + * 0b1..Enabled + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - MRT Operating mode + * 0b00..Repeat Interrupt mode + * 0b01..One-Shot Interrupt mode + * 0b10..One-Shot Stall mode + * 0b11..Reserved + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - Status */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Timer n State + * 0b0..Idle state. + * 0b1..Running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel-In-Use flag + * 0b0..This timer channel is not in use. + * 0b1..This timer channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Number of Channels */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Number of Bits */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - MULTITASK + * 0b0..Hardware status mode. + * 0b1..Multitask mode + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle Channel */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle Channel */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global Interrupt Flag */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NPX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Peripheral_Access_Layer NPX Peripheral Access Layer + * @{ + */ + +/** NPX - Register Layout Typedef */ +typedef struct { + __IO uint32_t NPXCR; /**< NPX Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t NPXSR; /**< NPX Status Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __O uint32_t CACMSK; /**< Flash Cache Obfuscation Mask, offset: 0x10 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ + uint8_t RESERVED_3[28]; + struct { /* offset: 0x40, array step: 0x10 */ + __IO uint32_t VMAPCTX_WD[2]; /**< Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3, array offset: 0x40, array step: index*0x10, index2*0x4 */ + __O uint32_t BIVCTX_WD[2]; /**< Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3, array offset: 0x48, array step: index*0x10, index2*0x4 */ + } CTX_VALID_IV_ARRAY[4]; +} NPX_Type; + +/* ---------------------------------------------------------------------------- + -- NPX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Register_Masks NPX Register Masks + * @{ + */ + +/*! @name NPXCR - NPX Control Register */ +/*! @{ */ + +#define NPX_NPXCR_GEE_MASK (0x1U) +#define NPX_NPXCR_GEE_SHIFT (0U) +/*! GEE - Global Encryption Enable + * 0b1..Global encryption enabled. NPX on-the-fly encryption is enabled if the flash access hits in a valid + * memory context. Subsequent reads return 1. + * 0b0..Global encryption disabled. NPX on-the-fly encryption is disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GEE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GEE_SHIFT)) & NPX_NPXCR_GEE_MASK) + +#define NPX_NPXCR_GDE_MASK (0x4U) +#define NPX_NPXCR_GDE_SHIFT (2U) +/*! GDE - Global Decryption Enable + * 0b1..Global decryption enabled. NPX on-the-fly decryption is globally enabled. Subsequent reads return 1. + * 0b0..Global decryption disabled. NPX on-the-fly decryption is globally disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GDE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GDE_SHIFT)) & NPX_NPXCR_GDE_MASK) + +#define NPX_NPXCR_GLK_MASK (0x10U) +#define NPX_NPXCR_GLK_SHIFT (4U) +/*! GLK - Global Lock Enable + * 0b1..Lock enabled: cannot write to VMAPCTXn, NPXCR, or CACMSK. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GLK_SHIFT)) & NPX_NPXCR_GLK_MASK) + +#define NPX_NPXCR_MLK_MASK (0x40U) +#define NPX_NPXCR_MLK_SHIFT (6U) +/*! MLK - Mask Lock Enable + * 0b1..Lock enabled: cannot write to mask. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_MLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_MLK_SHIFT)) & NPX_NPXCR_MLK_MASK) + +#define NPX_NPXCR_CTX0LK_MASK (0x100U) +#define NPX_NPXCR_CTX0LK_SHIFT (8U) +/*! CTX0LK - Lock Enable for Context 0 + * 0b1..Lock enabled: cannot write to VMAPCTX0 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX0 remains read-write + */ +#define NPX_NPXCR_CTX0LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX0LK_SHIFT)) & NPX_NPXCR_CTX0LK_MASK) + +#define NPX_NPXCR_CTX1LK_MASK (0x400U) +#define NPX_NPXCR_CTX1LK_SHIFT (10U) +/*! CTX1LK - Lock Enable for Context 1 + * 0b1..Lock enabled: cannot write to VMAPCTX1 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX1 remains read-write + */ +#define NPX_NPXCR_CTX1LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX1LK_SHIFT)) & NPX_NPXCR_CTX1LK_MASK) + +#define NPX_NPXCR_CTX2LK_MASK (0x1000U) +#define NPX_NPXCR_CTX2LK_SHIFT (12U) +/*! CTX2LK - Lock Enable for Context 2 + * 0b1..Lock enabled: cannot write to VMAPCTX2 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX2 remains read-write + */ +#define NPX_NPXCR_CTX2LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX2LK_SHIFT)) & NPX_NPXCR_CTX2LK_MASK) + +#define NPX_NPXCR_CTX3LK_MASK (0x4000U) +#define NPX_NPXCR_CTX3LK_SHIFT (14U) +/*! CTX3LK - Lock Enable for Context 3 + * 0b1..Lock enabled: cannot write to VMAPCTX3 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX3 remains read-write + */ +#define NPX_NPXCR_CTX3LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX3LK_SHIFT)) & NPX_NPXCR_CTX3LK_MASK) +/*! @} */ + +/*! @name NPXSR - NPX Status Register */ +/*! @{ */ + +#define NPX_NPXSR_NUMCTX_MASK (0xFU) +#define NPX_NPXSR_NUMCTX_SHIFT (0U) +/*! NUMCTX - Number of implemented memory contexts + * 0b0000..No (zero) implemented memory contexts + * 0b0001..1 implemented memory contexts + * 0b0010..2 implemented memory contexts + * 0b0011..3 implemented memory contexts + * 0b0100..4 implemented memory contexts + */ +#define NPX_NPXSR_NUMCTX(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_NUMCTX_SHIFT)) & NPX_NPXSR_NUMCTX_MASK) + +#define NPX_NPXSR_V0_MASK (0x100U) +#define NPX_NPXSR_V0_SHIFT (8U) +/*! V0 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V0(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V0_SHIFT)) & NPX_NPXSR_V0_MASK) + +#define NPX_NPXSR_V1_MASK (0x200U) +#define NPX_NPXSR_V1_SHIFT (9U) +/*! V1 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V1(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V1_SHIFT)) & NPX_NPXSR_V1_MASK) + +#define NPX_NPXSR_V2_MASK (0x400U) +#define NPX_NPXSR_V2_SHIFT (10U) +/*! V2 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V2(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V2_SHIFT)) & NPX_NPXSR_V2_MASK) + +#define NPX_NPXSR_V3_MASK (0x800U) +#define NPX_NPXSR_V3_SHIFT (11U) +/*! V3 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V3(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V3_SHIFT)) & NPX_NPXSR_V3_MASK) +/*! @} */ + +/*! @name CACMSK - Flash Cache Obfuscation Mask */ +/*! @{ */ + +#define NPX_CACMSK_OBMASK_MASK (0xFFFFFFFFU) +#define NPX_CACMSK_OBMASK_SHIFT (0U) +/*! OBMASK - Obfuscation Mask */ +#define NPX_CACMSK_OBMASK(x) (((uint32_t)(((uint32_t)(x)) << NPX_CACMSK_OBMASK_SHIFT)) & NPX_CACMSK_OBMASK_MASK) +/*! @} */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define NPX_REMAP_REMAPLK_MASK (0x1U) +#define NPX_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b1..Lock enabled: cannot write to REMAP + * 0b0..Lock disabled: can write to REMAP + */ +#define NPX_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_REMAPLK_SHIFT)) & NPX_REMAP_REMAPLK_MASK) + +#define NPX_REMAP_LIM_MASK (0x1F0000U) +#define NPX_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) + +#define NPX_REMAP_LIMDP_MASK (0x1F000000U) +#define NPX_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) +/*! @} */ + +/*! @name CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD - Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT (0U) +/*! VAL0 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT (0U) +/*! VAL32 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT (1U) +/*! VAL1 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT (1U) +/*! VAL33 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT (2U) +/*! VAL2 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT (2U) +/*! VAL34 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT (3U) +/*! VAL3 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT (3U) +/*! VAL35 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT (4U) +/*! VAL4 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT (4U) +/*! VAL36 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT (5U) +/*! VAL5 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT (5U) +/*! VAL37 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT (6U) +/*! VAL6 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT (6U) +/*! VAL38 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT (7U) +/*! VAL7 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT (7U) +/*! VAL39 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT (8U) +/*! VAL8 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT (8U) +/*! VAL40 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT (9U) +/*! VAL9 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT (9U) +/*! VAL41 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT (10U) +/*! VAL10 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT (10U) +/*! VAL42 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT (11U) +/*! VAL11 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT (11U) +/*! VAL43 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT (12U) +/*! VAL12 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT (12U) +/*! VAL44 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT (13U) +/*! VAL13 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT (13U) +/*! VAL45 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT (14U) +/*! VAL14 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT (14U) +/*! VAL46 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT (15U) +/*! VAL15 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT (15U) +/*! VAL47 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT (16U) +/*! VAL16 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT (16U) +/*! VAL48 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT (17U) +/*! VAL17 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT (17U) +/*! VAL49 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT (18U) +/*! VAL18 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT (18U) +/*! VAL50 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT (19U) +/*! VAL19 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT (19U) +/*! VAL51 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT (20U) +/*! VAL20 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT (20U) +/*! VAL52 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT (21U) +/*! VAL21 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT (21U) +/*! VAL53 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT (22U) +/*! VAL22 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT (22U) +/*! VAL54 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT (23U) +/*! VAL23 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT (23U) +/*! VAL55 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT (24U) +/*! VAL24 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT (24U) +/*! VAL56 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT (25U) +/*! VAL25 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT (25U) +/*! VAL57 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT (26U) +/*! VAL26 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT (26U) +/*! VAL58 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT (27U) +/*! VAL27 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT (27U) +/*! VAL59 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT (28U) +/*! VAL28 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT (28U) +/*! VAL60 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT (29U) +/*! VAL29 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT (29U) +/*! VAL61 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT (30U) +/*! VAL30 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT (30U) +/*! VAL62 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT (31U) +/*! VAL31 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT (31U) +/*! VAL63 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT2 (2U) + +/*! @name CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD - Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT (0U) +/*! BIV_WD0 - Block Initial Vector Word0 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT (0U) +/*! BIV_WD1 - Block Initial Vector Word1 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT2 (2U) + + +/*! + * @} + */ /* end of group NPX_Register_Masks */ + + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/*! + * @} + */ /* end of group NPX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OTPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer + * @{ + */ + +/** OTPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameters, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RWC; /**< Read and Write Control, offset: 0x10 */ + __IO uint32_t RLC; /**< Reload Control, offset: 0x14 */ + __IO uint32_t PCR; /**< Power Control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t WDATA; /**< Write Data, offset: 0x20 */ + __I uint32_t RDATA; /**< Read Data, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t TIMING1; /**< Timing1, offset: 0x30 */ + __IO uint32_t TIMING2; /**< Timing2, offset: 0x34 */ + uint8_t RESERVED_3[456]; + __I uint32_t LOCK; /**< Lock, offset: 0x200 */ + __I uint32_t SECURE; /**< Secure, offset: 0x204 */ + __I uint32_t SECURE_INV; /**< Inverted Secure, offset: 0x208 */ + __I uint32_t DBG_KEY; /**< Debug and Key, offset: 0x20C */ + __IO uint32_t MISC_CFG; /**< MISC Config, offset: 0x210 */ + __IO uint32_t PHANTOM_CFG; /**< PHANTOM Config, offset: 0x214 */ + __IO uint32_t FLEX_CFG0; /**< Flexible Config 0, offset: 0x218 */ + __IO uint32_t FLEX_CFG1; /**< Flexible Config 1, offset: 0x21C */ +} OTPC_Type; + +/* ---------------------------------------------------------------------------- + -- OTPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Register_Masks OTPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OTPC_VERID_FEATURE_MASK (0xFFFFU) +#define OTPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define OTPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_FEATURE_SHIFT)) & OTPC_VERID_FEATURE_MASK) + +#define OTPC_VERID_MINOR_MASK (0xFF0000U) +#define OTPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OTPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MINOR_SHIFT)) & OTPC_VERID_MINOR_MASK) + +#define OTPC_VERID_MAJOR_MASK (0xFF000000U) +#define OTPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OTPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MAJOR_SHIFT)) & OTPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameters */ +/*! @{ */ + +#define OTPC_PARAM_NUM_FUSE_MASK (0xFFFFU) +#define OTPC_PARAM_NUM_FUSE_SHIFT (0U) +/*! NUM_FUSE - Number of fuse bytes */ +#define OTPC_PARAM_NUM_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PARAM_NUM_FUSE_SHIFT)) & OTPC_PARAM_NUM_FUSE_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define OTPC_SR_BUSY_MASK (0x1U) +#define OTPC_SR_BUSY_SHIFT (0U) +/*! BUSY - Busy status + * 0b0..Not busy (transaction complete) + * 0b1..Busy + */ +#define OTPC_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_BUSY_SHIFT)) & OTPC_SR_BUSY_MASK) + +#define OTPC_SR_ERROR_MASK (0x2U) +#define OTPC_SR_ERROR_SHIFT (1U) +/*! ERROR - Error flag + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ERROR_SHIFT)) & OTPC_SR_ERROR_MASK) + +#define OTPC_SR_ECC_SF_MASK (0x4U) +#define OTPC_SR_ECC_SF_SHIFT (2U) +/*! ECC_SF - ECC single fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_SF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_SF_SHIFT)) & OTPC_SR_ECC_SF_MASK) + +#define OTPC_SR_ECC_DF_MASK (0x8U) +#define OTPC_SR_ECC_DF_SHIFT (3U) +/*! ECC_DF - ECC double fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_DF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_DF_SHIFT)) & OTPC_SR_ECC_DF_MASK) + +#define OTPC_SR_TRI_F_MASK (0x10U) +#define OTPC_SR_TRI_F_SHIFT (4U) +/*! TRI_F - Triple voting fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_TRI_F(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_TRI_F_SHIFT)) & OTPC_SR_TRI_F_MASK) + +#define OTPC_SR_RD_FUSE_LOCK_MASK (0x100U) +#define OTPC_SR_RD_FUSE_LOCK_SHIFT (8U) +/*! RD_FUSE_LOCK - Read fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_FUSE_LOCK_SHIFT)) & OTPC_SR_RD_FUSE_LOCK_MASK) + +#define OTPC_SR_WR_FUSE_LOCK_MASK (0x200U) +#define OTPC_SR_WR_FUSE_LOCK_SHIFT (9U) +/*! WR_FUSE_LOCK - Write fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_FUSE_LOCK_SHIFT)) & OTPC_SR_WR_FUSE_LOCK_MASK) + +#define OTPC_SR_RD_REG_LOCK_MASK (0x400U) +#define OTPC_SR_RD_REG_LOCK_SHIFT (10U) +/*! RD_REG_LOCK - Read register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_REG_LOCK_SHIFT)) & OTPC_SR_RD_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_LOCK_MASK (0x800U) +#define OTPC_SR_WR_REG_LOCK_SHIFT (11U) +/*! WR_REG_LOCK - Write register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_LOCK_SHIFT)) & OTPC_SR_WR_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_BUSY_MASK (0x1000U) +#define OTPC_SR_WR_REG_BUSY_SHIFT (12U) +/*! WR_REG_BUSY - Write register when busy error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_BUSY_SHIFT)) & OTPC_SR_WR_REG_BUSY_MASK) + +#define OTPC_SR_WR_POWER_OFF_MASK (0x2000U) +#define OTPC_SR_WR_POWER_OFF_SHIFT (13U) +/*! WR_POWER_OFF - Write when power off error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_POWER_OFF_SHIFT)) & OTPC_SR_WR_POWER_OFF_MASK) + +#define OTPC_SR_FSM_MASK (0x10000U) +#define OTPC_SR_FSM_SHIFT (16U) +/*! FSM - Finite-state machine error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSM_SHIFT)) & OTPC_SR_FSM_MASK) + +#define OTPC_SR_FLC_MASK (0x20000U) +#define OTPC_SR_FLC_SHIFT (17U) +/*! FLC - Fuse load counter error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FLC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FLC_SHIFT)) & OTPC_SR_FLC_MASK) + +#define OTPC_SR_ADC_MASK (0x40000U) +#define OTPC_SR_ADC_SHIFT (18U) +/*! ADC - Address and data compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ADC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ADC_SHIFT)) & OTPC_SR_ADC_MASK) + +#define OTPC_SR_IRC_MASK (0x80000U) +#define OTPC_SR_IRC_SHIFT (19U) +/*! IRC - Inverted register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_IRC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_IRC_SHIFT)) & OTPC_SR_IRC_MASK) + +#define OTPC_SR_FSC_MASK (0x100000U) +#define OTPC_SR_FSC_SHIFT (20U) +/*! FSC - Fuse and shadow register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSC_SHIFT)) & OTPC_SR_FSC_MASK) +/*! @} */ + +/*! @name RWC - Read and Write Control */ +/*! @{ */ + +#define OTPC_RWC_ADDR_MASK (0x7FU) +#define OTPC_RWC_ADDR_SHIFT (0U) +/*! ADDR - EFUSE address */ +#define OTPC_RWC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_ADDR_SHIFT)) & OTPC_RWC_ADDR_MASK) + +#define OTPC_RWC_WR_ALL1S_MASK (0x1000U) +#define OTPC_RWC_WR_ALL1S_SHIFT (12U) +/*! WR_ALL1S - Write all 1s + * 0b0..Uses the WDATA value + * 0b1..Writes all 1s + */ +#define OTPC_RWC_WR_ALL1S(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK) + +#define OTPC_RWC_READ_EFUSE_MASK (0x2000U) +#define OTPC_RWC_READ_EFUSE_SHIFT (13U) +/*! READ_EFUSE - Read EFUSE + * 0b0..Starts program operation when the WR_UNLOCK value is 0x9527; otherwise, takes no action. + * 0b1..Starts read operation + */ +#define OTPC_RWC_READ_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_EFUSE_SHIFT)) & OTPC_RWC_READ_EFUSE_MASK) + +#define OTPC_RWC_READ_UPDATE_MASK (0x4000U) +#define OTPC_RWC_READ_UPDATE_SHIFT (14U) +/*! READ_UPDATE - Read update + * 0b0..Shadow register does not update + * 0b1..Shadow register updates + */ +#define OTPC_RWC_READ_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_UPDATE_SHIFT)) & OTPC_RWC_READ_UPDATE_MASK) + +#define OTPC_RWC_WR_UNLOCK_MASK (0xFFFF0000U) +#define OTPC_RWC_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write Unlock */ +#define OTPC_RWC_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_UNLOCK_SHIFT)) & OTPC_RWC_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name RLC - Reload Control */ +/*! @{ */ + +#define OTPC_RLC_RELOAD_SHADOWS_MASK (0x1U) +#define OTPC_RLC_RELOAD_SHADOWS_SHIFT (0U) +/*! RELOAD_SHADOWS - Reload shadow registers + * 0b0..No action (when writing) or reload complete (when reading) + * 0b1..Reload + */ +#define OTPC_RLC_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RLC_RELOAD_SHADOWS_SHIFT)) & OTPC_RLC_RELOAD_SHADOWS_MASK) +/*! @} */ + +/*! @name PCR - Power Control */ +/*! @{ */ + +#define OTPC_PCR_HVREQ_MASK (0x1U) +#define OTPC_PCR_HVREQ_SHIFT (0U) +/*! HVREQ - Strong switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_HVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_HVREQ_SHIFT)) & OTPC_PCR_HVREQ_MASK) + +#define OTPC_PCR_LVREQ_MASK (0x2U) +#define OTPC_PCR_LVREQ_SHIFT (1U) +/*! LVREQ - Weak switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_LVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_LVREQ_SHIFT)) & OTPC_PCR_LVREQ_MASK) + +#define OTPC_PCR_PDREQ_MASK (0x4U) +#define OTPC_PCR_PDREQ_SHIFT (2U) +/*! PDREQ - Power down request + * 0b0..PD pin is set to low when OTPC is in idle state. It means EFUSE hardmacro is in standby mode. Idle state + * means OTPC is not in read and program modes. + * 0b1..PD pin is set to high when OTPC is in idle state. It means EFUSE hardmacro is in power down mode. + */ +#define OTPC_PCR_PDREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_PDREQ_SHIFT)) & OTPC_PCR_PDREQ_MASK) +/*! @} */ + +/*! @name WDATA - Write Data */ +/*! @{ */ + +#define OTPC_WDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_WDATA_DAT_SHIFT (0U) +/*! DAT - Write data */ +#define OTPC_WDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_WDATA_DAT_SHIFT)) & OTPC_WDATA_DAT_MASK) +/*! @} */ + +/*! @name RDATA - Read Data */ +/*! @{ */ + +#define OTPC_RDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_RDATA_DAT_SHIFT (0U) +/*! DAT - Read data */ +#define OTPC_RDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RDATA_DAT_SHIFT)) & OTPC_RDATA_DAT_MASK) +/*! @} */ + +/*! @name TIMING1 - Timing1 */ +/*! @{ */ + +#define OTPC_TIMING1_TADDR_MASK (0xFU) +#define OTPC_TIMING1_TADDR_SHIFT (0U) +/*! TADDR - Address to STROBE setup and hold time */ +#define OTPC_TIMING1_TADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TADDR_SHIFT)) & OTPC_TIMING1_TADDR_MASK) + +#define OTPC_TIMING1_TRELAX_MASK (0xF0U) +#define OTPC_TIMING1_TRELAX_SHIFT (4U) +/*! TRELAX - CSB, PGENB and LOAD to STROBE setup and hold time */ +#define OTPC_TIMING1_TRELAX(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRELAX_SHIFT)) & OTPC_TIMING1_TRELAX_MASK) + +#define OTPC_TIMING1_TRD_MASK (0x3F00U) +#define OTPC_TIMING1_TRD_SHIFT (8U) +/*! TRD - Read strobe pulse width time */ +#define OTPC_TIMING1_TRD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRD_SHIFT)) & OTPC_TIMING1_TRD_MASK) + +#define OTPC_TIMING1_TPS_MASK (0x3F0000U) +#define OTPC_TIMING1_TPS_SHIFT (16U) +/*! TPS - PS to CSB setup and hold time between power switch and chip select assertion */ +#define OTPC_TIMING1_TPS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPS_SHIFT)) & OTPC_TIMING1_TPS_MASK) + +#define OTPC_TIMING1_TPD_MASK (0xFF000000U) +#define OTPC_TIMING1_TPD_SHIFT (24U) +/*! TPD - PD to CSB setup time between power down signal deassertion and chip select signal assertion */ +#define OTPC_TIMING1_TPD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK) +/*! @} */ + +/*! @name TIMING2 - Timing2 */ +/*! @{ */ + +#define OTPC_TIMING2_TPGM_MASK (0xFFFU) +#define OTPC_TIMING2_TPGM_SHIFT (0U) +/*! TPGM - Typical program strobe pulse width time */ +#define OTPC_TIMING2_TPGM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING2_TPGM_SHIFT)) & OTPC_TIMING2_TPGM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define OTPC_LOCK_NXP_PART_CFG_LOCK_MASK (0x7U) +#define OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT (0U) +/*! NXP_PART_CFG_LOCK - NXP Part Config Lock */ +#define OTPC_LOCK_NXP_PART_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT)) & OTPC_LOCK_NXP_PART_CFG_LOCK_MASK) + +#define OTPC_LOCK_NXP_EXT_LOCK_MASK (0x38U) +#define OTPC_LOCK_NXP_EXT_LOCK_SHIFT (3U) +/*! NXP_EXT_LOCK - NXP EXT Lock */ +#define OTPC_LOCK_NXP_EXT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_EXT_LOCK_SHIFT)) & OTPC_LOCK_NXP_EXT_LOCK_MASK) + +#define OTPC_LOCK_BOOT_CFG_LOCK_MASK (0xE00U) +#define OTPC_LOCK_BOOT_CFG_LOCK_SHIFT (9U) +/*! BOOT_CFG_LOCK - Boot config Lock */ +#define OTPC_LOCK_BOOT_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_BOOT_CFG_LOCK_SHIFT)) & OTPC_LOCK_BOOT_CFG_LOCK_MASK) + +#define OTPC_LOCK_PRINCE_CFG_LOCK_MASK (0x7000U) +#define OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT (12U) +/*! PRINCE_CFG_LOCK - Prince Config Lock */ +#define OTPC_LOCK_PRINCE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT)) & OTPC_LOCK_PRINCE_CFG_LOCK_MASK) + +#define OTPC_LOCK_OSCAA_KEY_LOCK_MASK (0x38000U) +#define OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT (15U) +/*! OSCAA_KEY_LOCK - OSCAA Key Lock */ +#define OTPC_LOCK_OSCAA_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT)) & OTPC_LOCK_OSCAA_KEY_LOCK_MASK) + +#define OTPC_LOCK_CUST_LOCK0_MASK (0x1C0000U) +#define OTPC_LOCK_CUST_LOCK0_SHIFT (18U) +/*! CUST_LOCK0 - CUST Lock 0 */ +#define OTPC_LOCK_CUST_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK0_SHIFT)) & OTPC_LOCK_CUST_LOCK0_MASK) + +#define OTPC_LOCK_CUST_LOCK1_MASK (0xE00000U) +#define OTPC_LOCK_CUST_LOCK1_SHIFT (21U) +/*! CUST_LOCK1 - CUST Lock 1 */ +#define OTPC_LOCK_CUST_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK1_SHIFT)) & OTPC_LOCK_CUST_LOCK1_MASK) + +#define OTPC_LOCK_CUST_LOCK2_MASK (0x7000000U) +#define OTPC_LOCK_CUST_LOCK2_SHIFT (24U) +/*! CUST_LOCK2 - CUST Lock 2 */ +#define OTPC_LOCK_CUST_LOCK2(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK2_SHIFT)) & OTPC_LOCK_CUST_LOCK2_MASK) + +#define OTPC_LOCK_CUST_LOCK3_MASK (0x38000000U) +#define OTPC_LOCK_CUST_LOCK3_SHIFT (27U) +/*! CUST_LOCK3 - CUST Lock 3 */ +#define OTPC_LOCK_CUST_LOCK3(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK3_SHIFT)) & OTPC_LOCK_CUST_LOCK3_MASK) +/*! @} */ + +/*! @name SECURE - Secure */ +/*! @{ */ + +#define OTPC_SECURE_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_DAT_SHIFT)) & OTPC_SECURE_DAT_MASK) +/*! @} */ + +/*! @name SECURE_INV - Inverted Secure */ +/*! @{ */ + +#define OTPC_SECURE_INV_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_INV_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_INV_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_INV_DAT_SHIFT)) & OTPC_SECURE_INV_DAT_MASK) +/*! @} */ + +/*! @name DBG_KEY - Debug and Key */ +/*! @{ */ + +#define OTPC_DBG_KEY_DAT_MASK (0xFFFFFFFFU) +#define OTPC_DBG_KEY_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_DBG_KEY_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_DBG_KEY_DAT_SHIFT)) & OTPC_DBG_KEY_DAT_MASK) +/*! @} */ + +/*! @name MISC_CFG - MISC Config */ +/*! @{ */ + +#define OTPC_MISC_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_MISC_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_MISC_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_MISC_CFG_DAT_SHIFT)) & OTPC_MISC_CFG_DAT_MASK) +/*! @} */ + +/*! @name PHANTOM_CFG - PHANTOM Config */ +/*! @{ */ + +#define OTPC_PHANTOM_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_PHANTOM_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_PHANTOM_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PHANTOM_CFG_DAT_SHIFT)) & OTPC_PHANTOM_CFG_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG0 - Flexible Config 0 */ +/*! @{ */ + +#define OTPC_FLEX_CFG0_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG0_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG0_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG0_DAT_SHIFT)) & OTPC_FLEX_CFG0_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG1 - Flexible Config 1 */ +/*! @{ */ + +#define OTPC_FLEX_CFG1_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG1_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG1_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG1_DAT_SHIFT)) & OTPC_FLEX_CFG1_DAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OTPC_Register_Masks */ + + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/*! + * @} + */ /* end of group OTPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer + * @{ + */ + +/** PDM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ + __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ + __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ + __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __I uint32_t DATACH[4]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_2[48]; + __I uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ + __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ + uint8_t RESERVED_4[4]; + __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ + __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ + __I uint32_t VERID; /**< Version ID, offset: 0x84 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ +} PDM_Type; + +/* ---------------------------------------------------------------------------- + -- PDM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Register_Masks PDM Register Masks + * @{ + */ + +/*! @name CTRL_1 - MICFIL Control 1 */ +/*! @{ */ + +#define PDM_CTRL_1_CH0EN_MASK (0x1U) +#define PDM_CTRL_1_CH0EN_SHIFT (0U) +/*! CH0EN - Channel 0 Enable */ +#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + +#define PDM_CTRL_1_CH1EN_MASK (0x2U) +#define PDM_CTRL_1_CH1EN_SHIFT (1U) +/*! CH1EN - Channel 1 Enable */ +#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + +#define PDM_CTRL_1_CH2EN_MASK (0x4U) +#define PDM_CTRL_1_CH2EN_SHIFT (2U) +/*! CH2EN - Channel 2 Enable */ +#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + +#define PDM_CTRL_1_CH3EN_MASK (0x8U) +#define PDM_CTRL_1_CH3EN_SHIFT (3U) +/*! CH3EN - Channel 3 Enable */ +#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + +#define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) +#define PDM_CTRL_1_FSYNCEN_SHIFT (16U) +/*! FSYNCEN - Frame Synchronization Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) + +#define PDM_CTRL_1_DECFILS_MASK (0x100000U) +#define PDM_CTRL_1_DECFILS_SHIFT (20U) +/*! DECFILS - Decimation Filter Enable in Stop + * 0b0..Stops decimation filter + * 0b1..Keeps decimation filter running + */ +#define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) + +#define PDM_CTRL_1_ERREN_MASK (0x800000U) +#define PDM_CTRL_1_ERREN_SHIFT (23U) +/*! ERREN - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + +#define PDM_CTRL_1_DISEL_MASK (0x3000000U) +#define PDM_CTRL_1_DISEL_SHIFT (24U) +/*! DISEL - DMA Interrupt Selection + * 0b00..Disables DMA and interrupt requests + * 0b01..Enables DMA requests + * 0b10..Enables interrupt requests + * 0b11..Reserved + */ +#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + +#define PDM_CTRL_1_DBGE_MASK (0x4000000U) +#define PDM_CTRL_1_DBGE_SHIFT (26U) +/*! DBGE - Module Enable in Debug + * 0b0..Disables after completing the current frame + * 0b1..Enables operation + */ +#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + +#define PDM_CTRL_1_SRES_MASK (0x8000000U) +#define PDM_CTRL_1_SRES_SHIFT (27U) +/*! SRES - Software Reset + * 0b0..No action + * 0b1..Software reset + */ +#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + +#define PDM_CTRL_1_DBG_MASK (0x10000000U) +#define PDM_CTRL_1_DBG_SHIFT (28U) +/*! DBG - Debug Mode + * 0b0..Normal + * 0b1..Debug + */ +#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + +#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) +#define PDM_CTRL_1_PDMIEN_SHIFT (29U) +/*! PDMIEN - MICFIL Enable + * 0b0..Stops MICFIL operation + * 0b1..Starts MICFIL operation + */ +#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + +#define PDM_CTRL_1_DOZEN_MASK (0x40000000U) +#define PDM_CTRL_1_DOZEN_SHIFT (30U) +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + +#define PDM_CTRL_1_MDIS_MASK (0x80000000U) +#define PDM_CTRL_1_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Normal mode + * 0b1..DLL mode + */ +#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) +/*! @} */ + +/*! @name CTRL_2 - MICFIL Control 2 */ +/*! @{ */ + +#define PDM_CTRL_2_CLKDIV_MASK (0xFFU) +#define PDM_CTRL_2_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ +#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + +#define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) +#define PDM_CTRL_2_CLKDIVDIS_SHIFT (15U) +/*! CLKDIVDIS - Clock Divider Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_CTRL_2_CLKDIVDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK) + +#define PDM_CTRL_2_CICOSR_MASK (0xF0000U) +#define PDM_CTRL_2_CICOSR_SHIFT (16U) +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ +#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + +#define PDM_CTRL_2_QSEL_MASK (0xE000000U) +#define PDM_CTRL_2_QSEL_SHIFT (25U) +/*! QSEL - Quality Mode + * 0b001..High-Quality mode + * 0b000..Medium-Quality mode + * 0b111..Low-Quality mode + * 0b110..Very-Low-Quality 0 mode + * 0b101..Very-Low-Quality 1 mode + * 0b100..Very-Low-Quality 2 mode + */ +#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) +/*! @} */ + +/*! @name STAT - MICFIL Status */ +/*! @{ */ + +#define PDM_STAT_CH0F_MASK (0x1U) +#define PDM_STAT_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + +#define PDM_STAT_CH1F_MASK (0x2U) +#define PDM_STAT_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + +#define PDM_STAT_CH2F_MASK (0x4U) +#define PDM_STAT_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + +#define PDM_STAT_CH3F_MASK (0x8U) +#define PDM_STAT_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + +#define PDM_STAT_BSY_FIL_MASK (0x80000000U) +#define PDM_STAT_BSY_FIL_SHIFT (31U) +/*! BSY_FIL - Busy Flag + * 0b1..MICFIL is running + * 0b0..MICFIL is stopped + */ +#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) +/*! @} */ + +/*! @name FIFO_CTRL - MICFIL FIFO Control */ +/*! @{ */ + +#define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) +#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) +/*! FIFOWMK - FIFO Watermark Control */ +#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) +/*! @} */ + +/*! @name FIFO_STAT - MICFIL FIFO Status */ +/*! @{ */ + +#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) +#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) +/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + +#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) +#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) +/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + +#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) +#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) +/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + +#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) +#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) +/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + +#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) +#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) +/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + +#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) +#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) +/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + +#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) +#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) +/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + +#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) +#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) +/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) +/*! @} */ + +/*! @name DATACHN_DATACH - MICFIL Output Result */ +/*! @{ */ + +#define PDM_DATACHN_DATACH_DATA_MASK (0xFFFFFFFFU) +#define PDM_DATACHN_DATACH_DATA_SHIFT (0U) +/*! DATA - Channel n Data */ +#define PDM_DATACHN_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACHN_DATACH_DATA_SHIFT)) & PDM_DATACHN_DATACH_DATA_MASK) +/*! @} */ + +/* The count of PDM_DATACHN_DATACH */ +#define PDM_DATACHN_DATACH_COUNT (4U) + +/*! @name DC_CTRL - MICFIL DC Remover Control */ +/*! @{ */ + +#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ +/*! @{ */ + +#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name RANGE_CTRL - MICFIL Range Control */ +/*! @{ */ + +#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) +#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) +/*! RANGEADJ0 - Channel 0 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) +#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) +/*! RANGEADJ1 - Channel 1 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) +#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) +/*! RANGEADJ2 - Channel 2 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) +#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) +/*! RANGEADJ3 - Channel 3 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) +/*! @} */ + +/*! @name RANGE_STAT - MICFIL Range Status */ +/*! @{ */ + +#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) +#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) +/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + +#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) +#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) +/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + +#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) +#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) +/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + +#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) +#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) +/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + +#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) +#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) +/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + +#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) +#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) +/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + +#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) +#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) +/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + +#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) +#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) +/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) +/*! @} */ + +/*! @name FSYNC_CTRL - Frame Synchronization Control */ +/*! @{ */ + +#define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) +#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) +/*! FSYNCLEN - Frame Synchronization Window Length */ +#define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) +/*! @} */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PDM_VERID_FEATURE_MASK (0xFFFFU) +#define PDM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) + +#define PDM_VERID_MINOR_MASK (0xFF0000U) +#define PDM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) + +#define PDM_VERID_MAJOR_MASK (0xFF000000U) +#define PDM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define PDM_PARAM_NPAIR_MASK (0xFU) +#define PDM_PARAM_NPAIR_SHIFT (0U) +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ +#define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) + +#define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) +#define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ +#define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) + +#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) +#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) +/*! FIL_OUT_WIDTH_24B - Filter Output Width + * 0b0..16 bits + * 0b1..24 bits + */ +#define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) + +#define PDM_PARAM_LOW_POWER_MASK (0x200U) +#define PDM_PARAM_LOW_POWER_SHIFT (9U) +/*! LOW_POWER - Low-Power Decimation Filter + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) + +#define PDM_PARAM_DC_BYPASS_MASK (0x400U) +#define PDM_PARAM_DC_BYPASS_SHIFT (10U) +/*! DC_BYPASS - Input DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) + +#define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) +#define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) +/*! DC_OUT_BYPASS - Output DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PDM_Register_Masks */ + + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/*! + * @} + */ /* end of group PDM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */ + __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */ + __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ + __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern-Match Interrupt Control, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Interrupt mode + * 0b00000000..In bit n configures the interrupt to be edge-sensitive + * 0b00000001..In bit n configures the interrupt to be level-sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables Interrupt + * 0b00000000..In bit n disables the corresponding interrupt + * 0b00000001..In bit n enables the corresponding interrupt + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Configures IENR + * 0b00000000..No operation for interrupt n + * 0b00000001..Enable rising edge or level interrupt for interrupt n + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Clear bits in IENR + * 0b00000000..No operation + * 0b00000001..Disable rising edge or level interrupt + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables Interrupt + * 0b00000000..Disable (set active interrupt level LOW) + * 0b00000001..Enable (set active interrupt level HIGH) + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF + * 0b00000000..Writes 0 to IENF. + * 0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Writes 0 to IENF + * 0b00000000..No operation + * 0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin Interrupt Rising Edge */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising-Edge Detect + * 0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin Interrupt Falling Edge */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling-Edge Detect + * 0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin Interrupt Status */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin Interrupt Status + * 0b00000000..Read 0- Interrupt is not requested, Write 0- No operation + * 0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection + * for this pin, Write 1 (level-sensitive)- switch the active level for this pin in + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern-Match Interrupt Control */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function + * or by the pattern-match function. If this value is 0b, interrupts are driven in response to the + * standard pin interrupt function. If this value is 1b, interrupts are driven in response to + * pattern matches. + * 0b0..Pin interrupt + * 0b1..Pattern match + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified + * Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If + * this value is 1b, RXEV output to the CPU is enabled. + * 0b0..Disabled + * 0b1..Enabled + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - Pattern Matches + * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is + * the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is + * the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is + * the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is + * the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is + * the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is + * the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is + * the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } +/* Backward compatibility */ +#define PINT PINT0 + + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PKC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer + * @{ + */ + +/** PKC - Register Layout Typedef */ +typedef struct { + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ + __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ + __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ + __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ + __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ + __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ + __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ + __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ + __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ + __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ + uint8_t RESERVED_4[3916]; + __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ + uint8_t RESERVED_5[12]; + __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_6[16]; + __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ + __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ + __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ + __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_7[12]; + __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} PKC_Type; + +/* ---------------------------------------------------------------------------- + -- PKC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Register_Masks PKC Register Masks + * @{ + */ + +/*! @name PKC_STATUS - Status Register */ +/*! @{ */ + +#define PKC_PKC_STATUS_ACTIV_MASK (0x1U) +#define PKC_PKC_STATUS_ACTIV_SHIFT (0U) +/*! ACTIV - PKC ACTIV */ +#define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) + +#define PKC_PKC_STATUS_CARRY_MASK (0x2U) +#define PKC_PKC_STATUS_CARRY_SHIFT (1U) +/*! CARRY - Carry overflow flag */ +#define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) + +#define PKC_PKC_STATUS_ZERO_MASK (0x4U) +#define PKC_PKC_STATUS_ZERO_SHIFT (2U) +/*! ZERO - Zero result flag */ +#define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) + +#define PKC_PKC_STATUS_GOANY_MASK (0x8U) +#define PKC_PKC_STATUS_GOANY_SHIFT (3U) +/*! GOANY - Combined GO status flag */ +#define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) + +#define PKC_PKC_STATUS_LOCKED_MASK (0x60U) +#define PKC_PKC_STATUS_LOCKED_SHIFT (5U) +/*! LOCKED - Parameter set locked */ +#define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) +/*! @} */ + +/*! @name PKC_CTRL - Control Register */ +/*! @{ */ + +#define PKC_PKC_CTRL_RESET_MASK (0x1U) +#define PKC_PKC_CTRL_RESET_SHIFT (0U) +/*! RESET - PKC reset control bit */ +#define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) + +#define PKC_PKC_CTRL_STOP_MASK (0x2U) +#define PKC_PKC_CTRL_STOP_SHIFT (1U) +/*! STOP - Freeze PKC calculation */ +#define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) + +#define PKC_PKC_CTRL_GOD1_MASK (0x4U) +#define PKC_PKC_CTRL_GOD1_SHIFT (2U) +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ +#define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) + +#define PKC_PKC_CTRL_GOD2_MASK (0x8U) +#define PKC_PKC_CTRL_GOD2_SHIFT (3U) +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ +#define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) + +#define PKC_PKC_CTRL_GOM1_MASK (0x10U) +#define PKC_PKC_CTRL_GOM1_SHIFT (4U) +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ +#define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) + +#define PKC_PKC_CTRL_GOM2_MASK (0x20U) +#define PKC_PKC_CTRL_GOM2_SHIFT (5U) +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ +#define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) + +#define PKC_PKC_CTRL_GOU_MASK (0x40U) +#define PKC_PKC_CTRL_GOU_SHIFT (6U) +/*! GOU - Control bit to start pipe operation */ +#define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) + +#define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) +#define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) +/*! GF2CONV - Convert to GF2 calculation modes */ +#define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) + +#define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) +#define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) +/*! CLRCACHE - Clear universal pointer cache */ +#define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) + +#define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) +#define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) +/*! CACHE_EN - Enable universal pointer cache */ +#define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) + +#define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) +#define PKC_PKC_CTRL_REDMUL_SHIFT (10U) +/*! REDMUL - Reduced multiplier mode + * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b01..Reserved - Error Generated if selected + * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b11..Reserved - Error Generated if selected + */ +#define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) +/*! @} */ + +/*! @name PKC_CFG - Configuration register */ +/*! @{ */ + +#define PKC_PKC_CFG_IDLEOP_MASK (0x1U) +#define PKC_PKC_CFG_IDLEOP_SHIFT (0U) +#define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) + +#define PKC_PKC_CFG_RFU1_MASK (0x2U) +#define PKC_PKC_CFG_RFU1_SHIFT (1U) +#define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) + +#define PKC_PKC_CFG_RFU2_MASK (0x4U) +#define PKC_PKC_CFG_RFU2_SHIFT (2U) +#define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) + +#define PKC_PKC_CFG_CLKRND_MASK (0x8U) +#define PKC_PKC_CFG_CLKRND_SHIFT (3U) +#define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) + +#define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) +#define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) +#define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) + +#define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) +#define PKC_PKC_CFG_RNDDLY_SHIFT (5U) +#define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) + +#define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) +#define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) +#define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) + +#define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) +#define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) +#define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) + +#define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) +#define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) +#define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) +/*! @} */ + +/*! @name PKC_MODE1 - Mode register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_MODE1_MODE_MASK (0xFFU) +#define PKC_PKC_MODE1_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) + +#define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) + +#define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN1 - Length register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN1_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) + +#define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN1_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_MODE2 - Mode register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_MODE2_MODE_MASK (0xFFU) +#define PKC_PKC_MODE2_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) + +#define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) +/*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) + +#define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN2 - Length register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN2_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) + +#define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN2_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_UPTR - Universal pointer FUP program */ +/*! @{ */ + +#define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTR_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP program */ +#define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) +/*! @} */ + +/*! @name PKC_UPTRT - Universal pointer FUP table */ +/*! @{ */ + +#define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTRT_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP table */ +#define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) +/*! @} */ + +/*! @name PKC_ULEN - Universal pointer length */ +/*! @{ */ + +#define PKC_PKC_ULEN_LEN_MASK (0xFFU) +#define PKC_PKC_ULEN_LEN_SHIFT (0U) +/*! LEN - Length of universal pointer calculation */ +#define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) +/*! @} */ + +/*! @name PKC_MCDATA - MC pattern data interface */ +/*! @{ */ + +#define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) +#define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) +/*! MCDATA - Microcode read/write data */ +#define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) +/*! @} */ + +/*! @name PKC_VERSION - PKC version register */ +/*! @{ */ + +#define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) +#define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) +/*! MULSIZE + * 0b01..32-bit multiplier + * 0b10..64-bit multiplier + * 0b11..128-bit multiplier + * 0b10..128-bit multiplier + * 0b01..64-bit multiplier + */ +#define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) + +#define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) +#define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) +#define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) + +#define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) +#define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) +#define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) + +#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) +#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) +#define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) + +#define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) +#define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) +#define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) + +#define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) +#define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) +#define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) + +#define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) +#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) +#define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) +#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) +#define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) +#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) +#define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) +#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) +#define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) + +#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) +#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) +#define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) +/*! @} */ + +/*! @name PKC_SOFT_RST - Software reset */ +/*! @{ */ + +#define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) +#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) +#define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) +/*! APB_NOTAV - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) +/*! APB_WRGMD - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) + +#define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) +#define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) +/*! AHB - AHB Error */ +#define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) + +#define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) +#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) +#define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) + +#define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) +#define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) +#define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) + +#define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) +#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) +#define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) + +#define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) +#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) +#define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) +/*! INT_PDONE - End-of-computation status flag */ +#define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) +/*! EN_PDONE - PDONE interrupt enable flag */ +#define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_STATUS - Interrupt status set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_MODULE_ID - Module ID */ +/*! @{ */ + +#define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) +#define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) +#define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) + +#define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) +#define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) +#define PKC_PKC_MODULE_ID_ID_SHIFT (16U) +#define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PKC_Register_Masks */ + + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/*! + * @} + */ /* end of group PKC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[28]; + __I uint32_t EDFR; /**< EFT Detect Flag, offset: 0x40 */ + __IO uint32_t EDIER; /**< EFT Detect Interrupt Enable, offset: 0x44 */ + __IO uint32_t EDCR; /**< EFT Detect Clear, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + uint8_t RESERVED_4[24]; + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name EDFR - EFT Detect Flag */ +/*! @{ */ + +#define PORT_EDFR_EDF0_MASK (0x1U) +#define PORT_EDFR_EDF0_SHIFT (0U) +/*! EDF0 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK) + +#define PORT_EDFR_EDF1_MASK (0x2U) +#define PORT_EDFR_EDF1_SHIFT (1U) +/*! EDF1 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK) + +#define PORT_EDFR_EDF2_MASK (0x4U) +#define PORT_EDFR_EDF2_SHIFT (2U) +/*! EDF2 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK) + +#define PORT_EDFR_EDF3_MASK (0x8U) +#define PORT_EDFR_EDF3_SHIFT (3U) +/*! EDF3 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK) + +#define PORT_EDFR_EDF4_MASK (0x10U) +#define PORT_EDFR_EDF4_SHIFT (4U) +/*! EDF4 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK) + +#define PORT_EDFR_EDF5_MASK (0x20U) +#define PORT_EDFR_EDF5_SHIFT (5U) +/*! EDF5 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK) + +#define PORT_EDFR_EDF6_MASK (0x40U) +#define PORT_EDFR_EDF6_SHIFT (6U) +/*! EDF6 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK) + +#define PORT_EDFR_EDF7_MASK (0x80U) +#define PORT_EDFR_EDF7_SHIFT (7U) +/*! EDF7 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF7_SHIFT)) & PORT_EDFR_EDF7_MASK) + +#define PORT_EDFR_EDF8_MASK (0x100U) +#define PORT_EDFR_EDF8_SHIFT (8U) +/*! EDF8 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) + +#define PORT_EDFR_EDF9_MASK (0x200U) +#define PORT_EDFR_EDF9_SHIFT (9U) +/*! EDF9 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) + +#define PORT_EDFR_EDF10_MASK (0x400U) +#define PORT_EDFR_EDF10_SHIFT (10U) +/*! EDF10 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) + +#define PORT_EDFR_EDF11_MASK (0x800U) +#define PORT_EDFR_EDF11_SHIFT (11U) +/*! EDF11 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) + +#define PORT_EDFR_EDF12_MASK (0x1000U) +#define PORT_EDFR_EDF12_SHIFT (12U) +/*! EDF12 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) + +#define PORT_EDFR_EDF13_MASK (0x2000U) +#define PORT_EDFR_EDF13_SHIFT (13U) +/*! EDF13 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) + +#define PORT_EDFR_EDF14_MASK (0x4000U) +#define PORT_EDFR_EDF14_SHIFT (14U) +/*! EDF14 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) + +#define PORT_EDFR_EDF15_MASK (0x8000U) +#define PORT_EDFR_EDF15_SHIFT (15U) +/*! EDF15 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) + +#define PORT_EDFR_EDF16_MASK (0x10000U) +#define PORT_EDFR_EDF16_SHIFT (16U) +/*! EDF16 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) + +#define PORT_EDFR_EDF17_MASK (0x20000U) +#define PORT_EDFR_EDF17_SHIFT (17U) +/*! EDF17 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) + +#define PORT_EDFR_EDF18_MASK (0x40000U) +#define PORT_EDFR_EDF18_SHIFT (18U) +/*! EDF18 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) + +#define PORT_EDFR_EDF19_MASK (0x80000U) +#define PORT_EDFR_EDF19_SHIFT (19U) +/*! EDF19 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) + +#define PORT_EDFR_EDF20_MASK (0x100000U) +#define PORT_EDFR_EDF20_SHIFT (20U) +/*! EDF20 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) + +#define PORT_EDFR_EDF21_MASK (0x200000U) +#define PORT_EDFR_EDF21_SHIFT (21U) +/*! EDF21 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) + +#define PORT_EDFR_EDF22_MASK (0x400000U) +#define PORT_EDFR_EDF22_SHIFT (22U) +/*! EDF22 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) + +#define PORT_EDFR_EDF23_MASK (0x800000U) +#define PORT_EDFR_EDF23_SHIFT (23U) +/*! EDF23 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) + +#define PORT_EDFR_EDF24_MASK (0x1000000U) +#define PORT_EDFR_EDF24_SHIFT (24U) +/*! EDF24 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) + +#define PORT_EDFR_EDF25_MASK (0x2000000U) +#define PORT_EDFR_EDF25_SHIFT (25U) +/*! EDF25 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) + +#define PORT_EDFR_EDF26_MASK (0x4000000U) +#define PORT_EDFR_EDF26_SHIFT (26U) +/*! EDF26 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) + +#define PORT_EDFR_EDF27_MASK (0x8000000U) +#define PORT_EDFR_EDF27_SHIFT (27U) +/*! EDF27 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) + +#define PORT_EDFR_EDF28_MASK (0x10000000U) +#define PORT_EDFR_EDF28_SHIFT (28U) +/*! EDF28 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) + +#define PORT_EDFR_EDF29_MASK (0x20000000U) +#define PORT_EDFR_EDF29_SHIFT (29U) +/*! EDF29 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) + +#define PORT_EDFR_EDF30_MASK (0x40000000U) +#define PORT_EDFR_EDF30_SHIFT (30U) +/*! EDF30 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) + +#define PORT_EDFR_EDF31_MASK (0x80000000U) +#define PORT_EDFR_EDF31_SHIFT (31U) +/*! EDF31 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) +/*! @} */ + +/*! @name EDIER - EFT Detect Interrupt Enable */ +/*! @{ */ + +#define PORT_EDIER_EDIE0_MASK (0x1U) +#define PORT_EDIER_EDIE0_SHIFT (0U) +/*! EDIE0 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK) + +#define PORT_EDIER_EDIE1_MASK (0x2U) +#define PORT_EDIER_EDIE1_SHIFT (1U) +/*! EDIE1 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK) + +#define PORT_EDIER_EDIE2_MASK (0x4U) +#define PORT_EDIER_EDIE2_SHIFT (2U) +/*! EDIE2 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK) + +#define PORT_EDIER_EDIE3_MASK (0x8U) +#define PORT_EDIER_EDIE3_SHIFT (3U) +/*! EDIE3 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK) + +#define PORT_EDIER_EDIE4_MASK (0x10U) +#define PORT_EDIER_EDIE4_SHIFT (4U) +/*! EDIE4 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK) + +#define PORT_EDIER_EDIE5_MASK (0x20U) +#define PORT_EDIER_EDIE5_SHIFT (5U) +/*! EDIE5 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK) + +#define PORT_EDIER_EDIE6_MASK (0x40U) +#define PORT_EDIER_EDIE6_SHIFT (6U) +/*! EDIE6 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK) + +#define PORT_EDIER_EDIE7_MASK (0x80U) +#define PORT_EDIER_EDIE7_SHIFT (7U) +/*! EDIE7 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE7_SHIFT)) & PORT_EDIER_EDIE7_MASK) + +#define PORT_EDIER_EDIE8_MASK (0x100U) +#define PORT_EDIER_EDIE8_SHIFT (8U) +/*! EDIE8 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) + +#define PORT_EDIER_EDIE9_MASK (0x200U) +#define PORT_EDIER_EDIE9_SHIFT (9U) +/*! EDIE9 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) + +#define PORT_EDIER_EDIE10_MASK (0x400U) +#define PORT_EDIER_EDIE10_SHIFT (10U) +/*! EDIE10 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) + +#define PORT_EDIER_EDIE11_MASK (0x800U) +#define PORT_EDIER_EDIE11_SHIFT (11U) +/*! EDIE11 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) + +#define PORT_EDIER_EDIE12_MASK (0x1000U) +#define PORT_EDIER_EDIE12_SHIFT (12U) +/*! EDIE12 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) + +#define PORT_EDIER_EDIE13_MASK (0x2000U) +#define PORT_EDIER_EDIE13_SHIFT (13U) +/*! EDIE13 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) + +#define PORT_EDIER_EDIE14_MASK (0x4000U) +#define PORT_EDIER_EDIE14_SHIFT (14U) +/*! EDIE14 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) + +#define PORT_EDIER_EDIE15_MASK (0x8000U) +#define PORT_EDIER_EDIE15_SHIFT (15U) +/*! EDIE15 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) + +#define PORT_EDIER_EDIE16_MASK (0x10000U) +#define PORT_EDIER_EDIE16_SHIFT (16U) +/*! EDIE16 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) + +#define PORT_EDIER_EDIE17_MASK (0x20000U) +#define PORT_EDIER_EDIE17_SHIFT (17U) +/*! EDIE17 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) + +#define PORT_EDIER_EDIE18_MASK (0x40000U) +#define PORT_EDIER_EDIE18_SHIFT (18U) +/*! EDIE18 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) + +#define PORT_EDIER_EDIE19_MASK (0x80000U) +#define PORT_EDIER_EDIE19_SHIFT (19U) +/*! EDIE19 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) + +#define PORT_EDIER_EDIE20_MASK (0x100000U) +#define PORT_EDIER_EDIE20_SHIFT (20U) +/*! EDIE20 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) + +#define PORT_EDIER_EDIE21_MASK (0x200000U) +#define PORT_EDIER_EDIE21_SHIFT (21U) +/*! EDIE21 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) + +#define PORT_EDIER_EDIE22_MASK (0x400000U) +#define PORT_EDIER_EDIE22_SHIFT (22U) +/*! EDIE22 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) + +#define PORT_EDIER_EDIE23_MASK (0x800000U) +#define PORT_EDIER_EDIE23_SHIFT (23U) +/*! EDIE23 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) + +#define PORT_EDIER_EDIE24_MASK (0x1000000U) +#define PORT_EDIER_EDIE24_SHIFT (24U) +/*! EDIE24 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) + +#define PORT_EDIER_EDIE25_MASK (0x2000000U) +#define PORT_EDIER_EDIE25_SHIFT (25U) +/*! EDIE25 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) + +#define PORT_EDIER_EDIE26_MASK (0x4000000U) +#define PORT_EDIER_EDIE26_SHIFT (26U) +/*! EDIE26 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) + +#define PORT_EDIER_EDIE27_MASK (0x8000000U) +#define PORT_EDIER_EDIE27_SHIFT (27U) +/*! EDIE27 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) + +#define PORT_EDIER_EDIE28_MASK (0x10000000U) +#define PORT_EDIER_EDIE28_SHIFT (28U) +/*! EDIE28 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) + +#define PORT_EDIER_EDIE29_MASK (0x20000000U) +#define PORT_EDIER_EDIE29_SHIFT (29U) +/*! EDIE29 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) + +#define PORT_EDIER_EDIE30_MASK (0x40000000U) +#define PORT_EDIER_EDIE30_SHIFT (30U) +/*! EDIE30 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) + +#define PORT_EDIER_EDIE31_MASK (0x80000000U) +#define PORT_EDIER_EDIE31_SHIFT (31U) +/*! EDIE31 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) +/*! @} */ + +/*! @name EDCR - EFT Detect Clear */ +/*! @{ */ + +#define PORT_EDCR_EDHC_MASK (0x1U) +#define PORT_EDCR_EDHC_SHIFT (0U) +/*! EDHC - EFT Detect High Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDHC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK) + +#define PORT_EDCR_EDLC_MASK (0x2U) +#define PORT_EDCR_EDLC_SHIFT (1U) +/*! EDLC - EFT Detect Low Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDLC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + __I uint32_t AR; /**< Allow, offset: 0xC */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DATA_DEST; /**< Data Destination, offset: 0x20 */ + __IO uint32_t DATA_SRC; /**< Data Source, offset: 0x24 */ + uint8_t RESERVED_1[120]; + __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ + uint8_t RESERVED_2[4]; + __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ + uint8_t RESERVED_3[20]; + __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ + uint8_t RESERVED_5[8]; + __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ + __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ + __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ + uint8_t RESERVED_6[12]; + __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ + __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ + __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; + __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ + __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ + uint8_t RESERVED_8[208]; + __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ + __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ + __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ + __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ + __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ + __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define PUF_CR_ZEROIZE_MASK (0x1U) +#define PUF_CR_ZEROIZE_SHIFT (0U) +/*! ZEROIZE - Zeroize operation */ +#define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) + +#define PUF_CR_ENROLL_MASK (0x2U) +#define PUF_CR_ENROLL_SHIFT (1U) +/*! ENROLL - Enroll operation */ +#define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) + +#define PUF_CR_START_MASK (0x4U) +#define PUF_CR_START_SHIFT (2U) +/*! START - Start operation */ +#define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) + +#define PUF_CR_RECONSTRUCT_MASK (0x8U) +#define PUF_CR_RECONSTRUCT_SHIFT (3U) +/*! RECONSTRUCT - Reconstruct operation */ +#define PUF_CR_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK) + +#define PUF_CR_STOP_MASK (0x20U) +#define PUF_CR_STOP_SHIFT (5U) +/*! STOP - Stop operation */ +#define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) + +#define PUF_CR_GET_KEY_MASK (0x40U) +#define PUF_CR_GET_KEY_SHIFT (6U) +/*! GET_KEY - Get Key operation */ +#define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) + +#define PUF_CR_UNWRAP_MASK (0x80U) +#define PUF_CR_UNWRAP_SHIFT (7U) +/*! UNWRAP - Unwrap operation */ +#define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) + +#define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation */ +#define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_CR_WRAP_MASK (0x200U) +#define PUF_CR_WRAP_SHIFT (9U) +/*! WRAP - Wrap operation */ +#define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) + +#define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_CR_GENERATE_RANDOM_SHIFT (15U) +/*! GENERATE_RANDOM - Generate Random operation */ +#define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) + +#define PUF_CR_TEST_MEMORY_MASK (0x40000000U) +#define PUF_CR_TEST_MEMORY_SHIFT (30U) +/*! TEST_MEMORY - Test memory operation */ +#define PUF_CR_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK) + +#define PUF_CR_TEST_PUF_MASK (0x80000000U) +#define PUF_CR_TEST_PUF_SHIFT (31U) +/*! TEST_PUF - Test PUF operation */ +#define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) +/*! @} */ + +/*! @name ORR - Operation Result */ +/*! @{ */ + +#define PUF_ORR_RESULT_CODE_MASK (0xFFU) +#define PUF_ORR_RESULT_CODE_SHIFT (0U) +/*! RESULT_CODE - Result code of last operation + * 0b00000000..Indicates that the last operation was successful or operation is in progress. + * 0b11110000..Indicates that the AC is not for the current product/version. + * 0b11110001..Indicates that the AC in the second phase is not for the current product/version. + * 0b11110010..Indicates that the AC is corrupted. + * 0b11110011..Indicates that the AC in the second phase is corrupted. + * 0b11110100..Indicates that the authentication of the provided AC failed. + * 0b11110101..Indicates that the authentication of the provided AC failed in the second phase. + * 0b11110110..Indicates that the SRAM PUF quality verification fails. + * 0b11110111..Indicates that the incorrect or unsupported context is provided. + * 0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state. + * 0b11111111..Indicates that the PUF SRAM access has failed. + */ +#define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) + +#define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) +#define PUF_ORR_LAST_OPERATION_SHIFT (24U) +/*! LAST_OPERATION - Last operation type + * 0b00000000..Indicates that the operation is in progress. + * 0b00000001..Indicates that the last operation was Enroll. + * 0b00000010..Indicates that the last operation was Start. + * 0b00000011..Indicates that the last operation was Reconstruct + * 0b00000101..Indicates that the last operation was Stop. + * 0b00000110..Indicates that the last operation was Get Key. + * 0b00000111..Indicates that the last operation was Unwrap. + * 0b00001000..Indicates that the last operation was Wrap Generated Random. + * 0b00001001..Indicates that the last operation was Wrap. + * 0b00001111..Indicates that the last operation was Generate Random. + * 0b00011110..Indicates that the last operation was Test Memory. + * 0b00011111..Indicates that the last operation was Test PUF. + * 0b00100000..Indicates that the last operation was Initialization. + * 0b00101111..Indicates that the last operation was Zeroize. + */ +#define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define PUF_SR_BUSY_MASK (0x1U) +#define PUF_SR_BUSY_SHIFT (0U) +/*! BUSY - Operation in progress */ +#define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) + +#define PUF_SR_OK_MASK (0x2U) +#define PUF_SR_OK_SHIFT (1U) +/*! OK - Last operation successful */ +#define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) + +#define PUF_SR_ERROR_MASK (0x4U) +#define PUF_SR_ERROR_SHIFT (2U) +/*! ERROR - Last operation failed */ +#define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) + +#define PUF_SR_ZEROIZED_MASK (0x8U) +#define PUF_SR_ZEROIZED_SHIFT (3U) +/*! ZEROIZED - Zeroized or Locked state */ +#define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) + +#define PUF_SR_REJECTED_MASK (0x10U) +#define PUF_SR_REJECTED_SHIFT (4U) +/*! REJECTED - Operation rejected */ +#define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) + +#define PUF_SR_DI_REQUEST_MASK (0x20U) +#define PUF_SR_DI_REQUEST_SHIFT (5U) +/*! DI_REQUEST - Indicates the request for data in transfer via the DIR register */ +#define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) + +#define PUF_SR_DO_REQUEST_MASK (0x40U) +#define PUF_SR_DO_REQUEST_SHIFT (6U) +/*! DO_REQUEST - Indicates the request for data out transfer via the DOR register */ +#define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) +/*! @} */ + +/*! @name AR - Allow */ +/*! @{ */ + +#define PUF_AR_ALLOW_ENROLL_MASK (0x2U) +#define PUF_AR_ALLOW_ENROLL_SHIFT (1U) +/*! ALLOW_ENROLL - Enroll operation + * 0b0..Indicates that the Enroll operation is not allowed + * 0b1..Indicates that the Enroll operation is allowed + */ +#define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) + +#define PUF_AR_ALLOW_START_MASK (0x4U) +#define PUF_AR_ALLOW_START_SHIFT (2U) +/*! ALLOW_START - Start operation + * 0b0..Indicates that the Start operation is not allowed + * 0b1..Indicates that the Start operation is allowed + */ +#define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) + +#define PUF_AR_ALLOW_RECONSTRUCT_MASK (0x8U) +#define PUF_AR_ALLOW_RECONSTRUCT_SHIFT (3U) +/*! ALLOW_RECONSTRUCT - Reconstruct operation + * 0b0..Indicates that the Reconstruct operation is not allowed + * 0b1..Indicates that the Reconstruct operation is allowed + */ +#define PUF_AR_ALLOW_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK) + +#define PUF_AR_ALLOW_STOP_MASK (0x20U) +#define PUF_AR_ALLOW_STOP_SHIFT (5U) +/*! ALLOW_STOP - Stop operation + * 0b0..Indicates that the Stop operation is not allowed + * 0b1..Indicates that the Stop operation is allowed + */ +#define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) + +#define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) +#define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) +/*! ALLOW_GET_KEY - Get Key operation + * 0b0..Indicates that the Get Key operation is not allowed + * 0b1..Indicates that the Get Key operation is allowed + */ +#define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) + +#define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) +#define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) +/*! ALLOW_UNWRAP - Unwrap operation + * 0b0..Indicates that the Unwrap operation is not allowed + * 0b1..Indicates that the Unwrap operation is allowed + */ +#define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) + +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation + * 0b0..Indicates that the Wrap Generated Random operation is not allowed + * 0b1..Indicates that the Wrap Generated Random operation is allowed + */ +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_AR_ALLOW_WRAP_MASK (0x200U) +#define PUF_AR_ALLOW_WRAP_SHIFT (9U) +/*! ALLOW_WRAP - Wrap operation + * 0b0..Indicates that the Wrap operation is not allowed + * 0b1..Indicates that the Wrap operation is allowed + */ +#define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) + +#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) +/*! ALLOW_GENERATE_RANDOM - Generate Random operation + * 0b0..Indicates that the Generate Random operation is not allowed + * 0b1..Indicates that the Generate Random operation is allowed + */ +#define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) + +#define PUF_AR_ALLOW_TEST_MEMORY_MASK (0x40000000U) +#define PUF_AR_ALLOW_TEST_MEMORY_SHIFT (30U) +/*! ALLOW_TEST_MEMORY + * 0b0..Indicates that the Test Memory operation is not allowed + * 0b1..Indicates that the Test Memory operation is allowed + */ +#define PUF_AR_ALLOW_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK) + +#define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) +#define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) +/*! ALLOW_TEST_PUF - Test PUF operation + * 0b0..Test PUF operation is not allowed + * 0b1..Test PUF operation is allowed + */ +#define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define PUF_IER_INT_EN_MASK (0x1U) +#define PUF_IER_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt enable + * 0b0..Disables all PUF interrupts + * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register + */ +#define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define PUF_IMR_INT_EN_BUSY_MASK (0x1U) +#define PUF_IMR_INT_EN_BUSY_SHIFT (0U) +/*! INT_EN_BUSY - Busy interrupt */ +#define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) + +#define PUF_IMR_INT_EN_OK_MASK (0x2U) +#define PUF_IMR_INT_EN_OK_SHIFT (1U) +/*! INT_EN_OK - Ok interrupt */ +#define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) + +#define PUF_IMR_INT_EN_ERROR_MASK (0x4U) +#define PUF_IMR_INT_EN_ERROR_SHIFT (2U) +/*! INT_EN_ERROR - Error interrupt */ +#define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) + +#define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) +#define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) +/*! INT_EN_ZEROIZED - Zeroized interrupt */ +#define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) + +#define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) +#define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) +/*! INT_EN_REJECTED - Rejected interrupt */ +#define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) + +#define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) +#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) +/*! INT_EN_DI_REQUEST - Data in request interrupt */ +#define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) + +#define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) +#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) +/*! INT_EN_DO_REQUEST - Data out request interrupt */ +#define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define PUF_ISR_INT_BUSY_MASK (0x1U) +#define PUF_ISR_INT_BUSY_SHIFT (0U) +/*! INT_BUSY - Negative edge occurred on Busy */ +#define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) + +#define PUF_ISR_INT_OK_MASK (0x2U) +#define PUF_ISR_INT_OK_SHIFT (1U) +/*! INT_OK - Positive edge occurred on Ok */ +#define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) + +#define PUF_ISR_INT_ERROR_MASK (0x4U) +#define PUF_ISR_INT_ERROR_SHIFT (2U) +/*! INT_ERROR - Positive edge occurred on Error */ +#define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) + +#define PUF_ISR_INT_ZEROIZED_MASK (0x8U) +#define PUF_ISR_INT_ZEROIZED_SHIFT (3U) +/*! INT_ZEROIZED - Positive edge occurred on Zeroized */ +#define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) + +#define PUF_ISR_INT_REJECTED_MASK (0x10U) +#define PUF_ISR_INT_REJECTED_SHIFT (4U) +/*! INT_REJECTED - Positive edge occurred on Rejected */ +#define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) + +#define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) +#define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) +/*! INT_DI_REQUEST - Positive edge occurred on di_request */ +#define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) + +#define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) +#define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) +/*! INT_DO_REQUEST - Positive edge occurred on do_request */ +#define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) +/*! @} */ + +/*! @name DATA_DEST - Data Destination */ +/*! @{ */ + +#define PUF_DATA_DEST_DEST_DOR_MASK (0x1U) +#define PUF_DATA_DEST_DEST_DOR_SHIFT (0U) +/*! DEST_DOR - Key available via the DOR register */ +#define PUF_DATA_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK) + +#define PUF_DATA_DEST_DEST_SO_MASK (0x2U) +#define PUF_DATA_DEST_DEST_SO_SHIFT (1U) +/*! DEST_SO - Key available to ELS */ +#define PUF_DATA_DEST_DEST_SO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK) +/*! @} */ + +/*! @name DATA_SRC - Data Source */ +/*! @{ */ + +#define PUF_DATA_SRC_SRC_DIR_MASK (0x1U) +#define PUF_DATA_SRC_SRC_DIR_SHIFT (0U) +/*! SRC_DIR - Data provided via the DIR register */ +#define PUF_DATA_SRC_SRC_DIR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_DIR_SHIFT)) & PUF_DATA_SRC_SRC_DIR_MASK) + +#define PUF_DATA_SRC_SRC_SI_MASK (0x2U) +#define PUF_DATA_SRC_SRC_SI_SHIFT (1U) +/*! SRC_SI - Data provided via the SI interface */ +#define PUF_DATA_SRC_SRC_SI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_SI_SHIFT)) & PUF_DATA_SRC_SRC_SI_MASK) +/*! @} */ + +/*! @name DIR - Data Input */ +/*! @{ */ + +#define PUF_DIR_DI_MASK (0xFFFFFFFFU) +#define PUF_DIR_DI_SHIFT (0U) +/*! DI - Input data */ +#define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) +/*! @} */ + +/*! @name DOR - Data Output */ +/*! @{ */ + +#define PUF_DOR_DO_MASK (0xFFFFFFFFU) +#define PUF_DOR_DO_SHIFT (0U) +/*! DO - Output data */ +#define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) +/*! @} */ + +/*! @name MISC - Miscellaneous */ +/*! @{ */ + +#define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) +#define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) +/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: + * 0b0..Little endian + * 0b1..Big endian (default) + */ +#define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) +/*! @} */ + +/*! @name IF_SR - Interface Status */ +/*! @{ */ + +#define PUF_IF_SR_APB_ERROR_MASK (0x1U) +#define PUF_IF_SR_APB_ERROR_SHIFT (0U) +/*! APB_ERROR - APB error */ +#define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) +/*! @} */ + +/*! @name PSR - PUF Score */ +/*! @{ */ + +#define PUF_PSR_PUF_SCORE_MASK (0xFU) +#define PUF_PSR_PUF_SCORE_SHIFT (0U) +/*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */ +#define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) +/*! @} */ + +/*! @name HW_RUC0 - Hardware Restrict User Context 0 */ +/*! @{ */ + +#define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) +#define PUF_HW_RUC0_LC_STATE_SHIFT (0U) +/*! LC_STATE - Life cycle state based restrictions + * 0b00000011..OEM Develop + * 0b00000111..OEM Develop 2 + * 0b00001111..OEM In-field + * 0b00011111..OEM Field return + * 0b00111111..NXP Field Return/Failure Analysis + * 0b11001111..In-field Locked + * 0b11111111..Bricked + */ +#define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) + +#define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) +#define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) +/*! BOOT_STATE - Temporal boot state */ +#define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) + +#define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) +#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) +/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up */ +#define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) + +#define PUF_HW_RUC0_COOLFLUX_DEBUG_MASK (0x2000000U) +#define PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT (25U) +/*! COOLFLUX_DEBUG - Disable key access when debugger is attached to COOLFLUX after power-up */ +#define PUF_HW_RUC0_COOLFLUX_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT)) & PUF_HW_RUC0_COOLFLUX_DEBUG_MASK) + +#define PUF_HW_RUC0_dsp_debug_MASK (0x4000000U) +#define PUF_HW_RUC0_dsp_debug_SHIFT (26U) +/*! dsp_debug - DSP debug status. */ +#define PUF_HW_RUC0_dsp_debug(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_dsp_debug_SHIFT)) & PUF_HW_RUC0_dsp_debug_MASK) + +#define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) +#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) +/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level */ +#define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) +/*! @} */ + +/*! @name HW_RUC1 - Hardware Restrict User Context 1 */ +/*! @{ */ + +#define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) +#define PUF_HW_RUC1_APP_CTX_SHIFT (0U) +/*! APP_CTX - Application customizable context */ +#define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) +/*! @} */ + +/*! @name HW_INFO - Hardware Information */ +/*! @{ */ + +#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) +#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) +/*! CONFIG_WRAP - Wrap configuration + * 0b0..Indicates that Wrap is not included + * 0b1..Indicates that Wrap is included + */ +#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) + +#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) +#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) +/*! CONFIG_TYPE - PUF configuration + * 0b0001..Indicates that PUF configuration is Safe. + * 0b0010..Indicates that PUF configuration is Plus. + */ +#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) +/*! @} */ + +/*! @name HW_ID - Hardware Identifier */ +/*! @{ */ + +#define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) +#define PUF_HW_ID_HW_ID_SHIFT (0U) +/*! HW_ID - Provides the hardware identifier */ +#define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) +/*! @} */ + +/*! @name HW_VER - Hardware Version */ +/*! @{ */ + +#define PUF_HW_VER_HW_REV_MASK (0xFFU) +#define PUF_HW_VER_HW_REV_SHIFT (0U) +/*! HW_REV - Provides the hardware version, patch part */ +#define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) + +#define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) +#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) +/*! HW_VERSION_MINOR - Provides the hardware version, minor part */ +#define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) + +#define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) +#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) +/*! HW_VERSION_MAJOR - Provides the hardware version, major part */ +#define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Security level lock */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Security Level + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + +/*! @name SRAM_CFG - SRAM Configuration */ +/*! @{ */ + +#define PUF_SRAM_CFG_ENABLE_MASK (0x1U) +#define PUF_SRAM_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - PUF SRAM Controller activation + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) + +#define PUF_SRAM_CFG_CKGATING_MASK (0x4U) +#define PUF_SRAM_CFG_CKGATING_SHIFT (2U) +/*! CKGATING - PUF SRAM Clock Gating control + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) +/*! @} */ + +/*! @name SRAM_STATUS - Status */ +/*! @{ */ + +#define PUF_SRAM_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_STATUS_READY_SHIFT (0U) +/*! READY - PUF SRAM Controller State */ +#define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status */ +#define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) + +#define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status */ +#define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) +/*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status clear */ +#define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) + +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Clear + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status set */ +#define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) + +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Set + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_1[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ + __IO uint16_t CAPTFILTA; /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */ + __IO uint16_t CAPTFILTB; /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */ + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ + +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +/*! FRACVAL1 - Fractional Value 1 */ +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ + +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +/*! FRACVAL2 - Fractional Value 2 */ +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ + +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +/*! FRACVAL3 - Fractional Value 3 */ +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ + +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +/*! FRACVAL4 - Fractional Value 4 */ +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ + +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +/*! FRACVAL5 - Fractional Value 5 */ +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ + +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) + +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) + +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) + +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +/*! TEST - Test Status Bit */ +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +/*! CFB0 - Capture Flag B0 */ +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) + +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +/*! CFB1 - Capture Flag B1 */ +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) + +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +/*! CFA0 - Capture Flag A0 */ +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) + +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +/*! CFA1 - Capture Flag A1 */ +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) + +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) + +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) + +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1] + * 0b1..Interrupt request enabled for STS[CFA1] + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +/*! CB0DE - Capture B0 FIFO DMA Enable */ +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) + +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +/*! CB1DE - Capture B1 FIFO DMA Enable */ +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) + +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +/*! CA0DE - Capture A0 FIFO DMA Enable */ +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) + +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +/*! CA1DE - Capture A1 FIFO DMA Enable */ +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which + * watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ + +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) + +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) + +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) + +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) + +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) + +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) + +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +/*! CFAWM - Capture A FIFOs Water Mark */ +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) + +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +/*! CA0CNT - Capture A0 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) + +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +/*! CA1CNT - Capture A1 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ + +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +/*! EDGCMPA - Edge Compare A */ +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) + +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +/*! EDGCNTA - Edge Counter A */ +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ + +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) + +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) + +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) + +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) + +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) + +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) + +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +/*! CFBWM - Capture B FIFOs Water Mark */ +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) + +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +/*! CB0CNT - Capture B0 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) + +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +/*! CB1CNT - Capture B1 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ + +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +/*! EDGCMPB - Edge Compare B */ +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) + +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +/*! EDGCNTB - Edge Counter B */ +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ + +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +/*! CAPTVAL2 - Capture Value 2 */ +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +/*! CVAL2CYC - Capture Value 2 Cycle */ +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ + +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +/*! CAPTVAL3 - Capture Value 3 */ +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +/*! CVAL3CYC - Capture Value 3 Cycle */ +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ + +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +/*! CAPTVAL4 - Capture Value 4 */ +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +/*! CVAL4CYC - Capture Value 4 Cycle */ +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ + +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +/*! CAPTVAL5 - Capture Value 5 */ +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +/*! CVAL5CYC - Capture Value 5 Cycle */ +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTA - Capture PWM_A Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) +/*! CAPTA_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) + +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) +/*! CAPTA_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTA */ +#define PWM_CAPTFILTA_COUNT (4U) + +/*! @name CAPTFILTB - Capture PWM_B Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) +/*! CAPTB_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) + +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) +/*! CAPTB_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTB */ +#define PWM_CAPTFILTB_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. + * 0b11..PWM3_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x500D0000u) + /** Peripheral PWM1 base address */ + #define PWM1_BASE_NS (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Peripheral PWM1 base pointer */ + #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer + * @{ + */ + +/** QDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ + __IO uint16_t TST; /**< Test, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ +} QDC_Type; + +/* ---------------------------------------------------------------------------- + -- QDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Register_Masks QDC Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define QDC_CTRL_CMPIE_MASK (0x1U) +#define QDC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) + +#define QDC_CTRL_CMPIRQ_MASK (0x2U) +#define QDC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) + +#define QDC_CTRL_WDE_MASK (0x4U) +#define QDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) + +#define QDC_CTRL_DIE_MASK (0x8U) +#define QDC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) + +#define QDC_CTRL_DIRQ_MASK (0x10U) +#define QDC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) + +#define QDC_CTRL_XNE_MASK (0x20U) +#define QDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive and Negative Edge of INDEX Pulse + * 0b0..Use positive edge + * 0b1..Use negative edge + */ +#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) + +#define QDC_CTRL_XIP_MASK (0x40U) +#define QDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..Does not initialize + * 0b1..Initializes + */ +#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) + +#define QDC_CTRL_XIE_MASK (0x80U) +#define QDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) + +#define QDC_CTRL_XIRQ_MASK (0x100U) +#define QDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) + +#define QDC_CTRL_PH1_MASK (0x200U) +#define QDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. + * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; + * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. + */ +#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) + +#define QDC_CTRL_REV_MASK (0x400U) +#define QDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Counts normally + * 0b1..Counts in the reverse direction + */ +#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) + +#define QDC_CTRL_SWIP_MASK (0x800U) +#define QDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) + +#define QDC_CTRL_HNE_MASK (0x1000U) +#define QDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) + +#define QDC_CTRL_HIP_MASK (0x2000U) +#define QDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) + +#define QDC_CTRL_HIE_MASK (0x4000U) +#define QDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) + +#define QDC_CTRL_HIRQ_MASK (0x8000U) +#define QDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter */ +/*! @{ */ + +#define QDC_FILT_FILT_PER_MASK (0xFFU) +#define QDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) + +#define QDC_FILT_FILT_CNT_MASK (0x700U) +#define QDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) + +#define QDC_FILT_FILT_PRSC_MASK (0xE000U) +#define QDC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ +#define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout */ +/*! @{ */ + +#define QDC_WTR_WDOG_MASK (0xFFFFU) +#define QDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter */ +/*! @{ */ + +#define QDC_POSD_POSD_MASK (0xFFFFU) +#define QDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold */ +/*! @{ */ + +#define QDC_POSDH_POSDH_MASK (0xFFFFU) +#define QDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter */ +/*! @{ */ + +#define QDC_REV_REV_MASK (0xFFFFU) +#define QDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold */ +/*! @{ */ + +#define QDC_REVH_REVH_MASK (0xFFFFU) +#define QDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter */ +/*! @{ */ + +#define QDC_UPOS_POS_MASK (0xFFFFU) +#define QDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter */ +/*! @{ */ + +#define QDC_LPOS_POS_MASK (0xFFFFU) +#define QDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold */ +/*! @{ */ + +#define QDC_UPOSH_POSH_MASK (0xFFFFU) +#define QDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold */ +/*! @{ */ + +#define QDC_LPOSH_POSH_MASK (0xFFFFU) +#define QDC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization */ +/*! @{ */ + +#define QDC_UINIT_INIT_MASK (0xFFFFU) +#define QDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization */ +/*! @{ */ + +#define QDC_LINIT_INIT_MASK (0xFFFFU) +#define QDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor */ +/*! @{ */ + +#define QDC_IMR_HOME_MASK (0x1U) +#define QDC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME */ +#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) + +#define QDC_IMR_INDEX_MASK (0x2U) +#define QDC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX */ +#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) + +#define QDC_IMR_PHB_MASK (0x4U) +#define QDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) + +#define QDC_IMR_PHA_MASK (0x8U) +#define QDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) + +#define QDC_IMR_FHOM_MASK (0x10U) +#define QDC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM */ +#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) + +#define QDC_IMR_FIND_MASK (0x20U) +#define QDC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND */ +#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) + +#define QDC_IMR_FPHB_MASK (0x40U) +#define QDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB */ +#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) + +#define QDC_IMR_FPHA_MASK (0x80U) +#define QDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA */ +#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test */ +/*! @{ */ + +#define QDC_TST_TEST_COUNT_MASK (0xFFU) +#define QDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) + +#define QDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define QDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) + +#define QDC_TST_QDN_MASK (0x2000U) +#define QDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Positive quadrature decoder signal + * 0b1..Negative quadrature decoder signal + */ +#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) + +#define QDC_TST_TCE_MASK (0x4000U) +#define QDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) + +#define QDC_TST_TEN_MASK (0x8000U) +#define QDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define QDC_CTRL2_UPDHLD_MASK (0x1U) +#define QDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) + +#define QDC_CTRL2_UPDPOS_MASK (0x2U) +#define QDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action + * 0b1..Clear + */ +#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) + +#define QDC_CTRL2_MOD_MASK (0x4U) +#define QDC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) + +#define QDC_CTRL2_DIR_MASK (0x8U) +#define QDC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Down direction + * 0b1..Up direction + */ +#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) + +#define QDC_CTRL2_RUIE_MASK (0x10U) +#define QDC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) + +#define QDC_CTRL2_RUIRQ_MASK (0x20U) +#define QDC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) + +#define QDC_CTRL2_ROIE_MASK (0x40U) +#define QDC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) + +#define QDC_CTRL2_ROIRQ_MASK (0x80U) +#define QDC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..Did not occur + * 0b1..Occurred + */ +#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) + +#define QDC_CTRL2_REVMOD_MASK (0x100U) +#define QDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse + * 0b1..Use modulus counting roll-over or roll-under + */ +#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) + +#define QDC_CTRL2_OUTCTL_MASK (0x200U) +#define QDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) + +#define QDC_CTRL2_SABIE_MASK (0x400U) +#define QDC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) + +#define QDC_CTRL2_SABIRQ_MASK (0x800U) +#define QDC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change has occurred + * 0b1..A simultaneous change has occurred + */ +#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) + +#define QDC_CTRL2_INITPOS_MASK (0x1000U) +#define QDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initialize Position Registers + * 0b0..Don't initialize position counter + * 0b1..Initialize position counter + */ +#define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) + +#define QDC_CTRL2_EMIP_MASK (0x2000U) +#define QDC_CTRL2_EMIP_SHIFT (13U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_EMIP_SHIFT)) & QDC_CTRL2_EMIP_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus */ +/*! @{ */ + +#define QDC_UMOD_MOD_MASK (0xFFFFU) +#define QDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus */ +/*! @{ */ + +#define QDC_LMOD_MOD_MASK (0xFFFFU) +#define QDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare */ +/*! @{ */ + +#define QDC_UCOMP_COMP_MASK (0xFFFFU) +#define QDC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare */ +/*! @{ */ + +#define QDC_LCOMP_COMP_MASK (0xFFFFU) +#define QDC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time */ +/*! @{ */ + +#define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold */ +/*! @{ */ + +#define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter */ +/*! @{ */ + +#define QDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define QDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer */ +/*! @{ */ + +#define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold */ +/*! @{ */ + +#define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define QDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 */ +/*! @{ */ + +#define QDC_CTRL3_PMEN_MASK (0x1U) +#define QDC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period Measurement Function Enable + * 0b0..Not used + * 0b1..Used + */ +#define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) + +#define QDC_CTRL3_PRSC_MASK (0xF0U) +#define QDC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler */ +#define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group QDC_Register_Masks */ + + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/*! + * @} + */ /* end of group QDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ + __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ + __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ + __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ + __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ + __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ + __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ + __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ + __IO uint16_t CTRL; /**< Control, offset: 0x10 */ + __IO uint16_t STATUS; /**< Status, offset: 0x12 */ + __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ + __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ + uint8_t RESERVED_0[4]; + __I uint16_t RTC_TEST2; /**< Sub Second Counter, offset: 0x1C */ + uint8_t RESERVED_1[4]; + __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ + __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ + __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ + __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ + uint8_t RESERVED_2[2006]; + __IO uint32_t SUBSECOND_CTRL; /**< Subsecond Control, offset: 0x800 */ + __I uint32_t SUBSECOND_CNT; /**< Subsecond Counter, offset: 0x804 */ + uint8_t RESERVED_3[1016]; + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0xC00 */ + uint8_t RESERVED_4[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC0C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name YEARMON - Year and Month Counters */ +/*! @{ */ + +#define RTC_YEARMON_MON_CNT_MASK (0xFU) +#define RTC_YEARMON_MON_CNT_SHIFT (0U) +/*! MON_CNT - Month Counter + * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value + * 0b0001..January + * 0b0010..February + * 0b0011..March + * 0b0100..April + * 0b0101..May + * 0b0110..June + * 0b0111..July + * 0b1000..August + * 0b1001..September + * 0b1010..October + * 0b1011..November + * 0b1100..December + */ +#define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) + +#define RTC_YEARMON_YROFST_MASK (0xFF00U) +#define RTC_YEARMON_YROFST_SHIFT (8U) +/*! YROFST - Year Offset Count Value */ +#define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) +/*! @} */ + +/*! @name DAYS - Days and Day-of-Week Counters */ +/*! @{ */ + +#define RTC_DAYS_DAY_CNT_MASK (0x1FU) +#define RTC_DAYS_DAY_CNT_SHIFT (0U) +/*! DAY_CNT - Days Counter Value */ +#define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) + +#define RTC_DAYS_DOW_MASK (0x700U) +#define RTC_DAYS_DOW_SHIFT (8U) +/*! DOW - Day of Week Counter Value + * 0b000..Sunday + * 0b001..Monday + * 0b010..Tuesday + * 0b011..Wednesday + * 0b100..Thursday + * 0b101..Friday + * 0b110..Saturday + * 0b111.. + */ +#define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) +/*! @} */ + +/*! @name HOURMIN - Hours and Minutes Counters */ +/*! @{ */ + +#define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) +#define RTC_HOURMIN_MIN_CNT_SHIFT (0U) +/*! MIN_CNT - Minutes Counter Value */ +#define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) + +#define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) +#define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) +/*! HOUR_CNT - Hours Counter Value */ +#define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) +/*! @} */ + +/*! @name SECONDS - Seconds Counters */ +/*! @{ */ + +#define RTC_SECONDS_SEC_CNT_MASK (0x3FU) +#define RTC_SECONDS_SEC_CNT_SHIFT (0U) +/*! SEC_CNT - Seconds Counter Value */ +#define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) +/*! @} */ + +/*! @name ALM_YEARMON - Year and Months Alarm */ +/*! @{ */ + +#define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) +#define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) +/*! ALM_MON - Months Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) + +#define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) +#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) +/*! ALM_YEAR - Year Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) +/*! @} */ + +/*! @name ALM_DAYS - Days Alarm */ +/*! @{ */ + +#define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) +#define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) +/*! ALM_DAY - Days Value for Alarm */ +#define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) +/*! @} */ + +/*! @name ALM_HOURMIN - Hours and Minutes Alarm */ +/*! @{ */ + +#define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) +#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) +/*! ALM_MIN - Minutes Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) + +#define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) +#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) +/*! ALM_HOUR - Hours Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) +/*! @} */ + +/*! @name ALM_SECONDS - Seconds Alarm */ +/*! @{ */ + +#define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) +#define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) +/*! ALM_SEC - Seconds Alarm Value */ +#define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) + +#define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) +#define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) +/*! DEC_SEC - Decrement Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) + +#define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) +#define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) +/*! INC_SEC - Increment Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define RTC_CTRL_FINEEN_MASK (0x1U) +#define RTC_CTRL_FINEEN_SHIFT (0U) +/*! FINEEN - Fine Compensation Enable + * 0b1..Fine compensation is enabled. + * 0b0..Fine compensation is disabled + */ +#define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) + +#define RTC_CTRL_COMP_EN_MASK (0x2U) +#define RTC_CTRL_COMP_EN_SHIFT (1U) +/*! COMP_EN - Compensation Enable + * 0b0..Coarse compensation is disabled. + * 0b1..Coarse compensation is enabled. + */ +#define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) + +#define RTC_CTRL_ALM_MATCH_MASK (0xCU) +#define RTC_CTRL_ALM_MATCH_SHIFT (2U) +/*! ALM_MATCH - Alarm Match + * 0b00..Only seconds, minutes, and hours matched. + * 0b01..Only seconds, minutes, hours, and days matched. + * 0b10..Only seconds, minutes, hours, days, and months matched. + * 0b11..Only seconds, minutes, hours, days, months, and year (offset) matched. + */ +#define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) + +#define RTC_CTRL_DST_EN_MASK (0x40U) +#define RTC_CTRL_DST_EN_SHIFT (6U) +/*! DST_EN - Daylight Saving Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) + +#define RTC_CTRL_SWR_MASK (0x100U) +#define RTC_CTRL_SWR_SHIFT (8U) +/*! SWR - Software Reset + * 0b0..Software Reset cleared + * 0b1..Software Reset asserted + */ +#define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) + +#define RTC_CTRL_CLK_SEL_MASK (0x200U) +#define RTC_CTRL_CLK_SEL_SHIFT (9U) +/*! CLK_SEL - RTC Clock Select + * 0b0..16.384 kHz clock is selected + * 0b1..32.768 kHz clock is selected + */ +#define RTC_CTRL_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLK_SEL_SHIFT)) & RTC_CTRL_CLK_SEL_MASK) + +#define RTC_CTRL_CLKO_DIS_MASK (0x400U) +#define RTC_CTRL_CLKO_DIS_SHIFT (10U) +/*! CLKO_DIS - Clock Output Disable + * 0b0..The selected clock is output to other peripherals. + * 0b1..The selected clock is not output to other peripherals. + */ +#define RTC_CTRL_CLKO_DIS(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK) + +#define RTC_CTRL_CLKOUT_MASK (0x6000U) +#define RTC_CTRL_CLKOUT_SHIFT (13U) +/*! CLKOUT - RTC Clock Output Selection + * 0b00..No output clock + * 0b01..Fine 1 Hz clock with both precise edges + * 0b10..32.768 or 16.384 kHz clock + * 0b11..Coarse 1 Hz clock with both precise edges + */ +#define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define RTC_STATUS_INVAL_BIT_MASK (0x1U) +#define RTC_STATUS_INVAL_BIT_SHIFT (0U) +/*! INVAL_BIT - Invalidate CPU Read/Write Access + * 0b0..Time and date counters can be read or written. Time and date is valid. + * 0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written. + */ +#define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) + +#define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) +#define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) +/*! WRITE_PROT_EN - Write Protect Enable Status + * 0b0..Registers are unlocked and can be accessed. + * 0b1..Registers are locked and in read-only mode. + */ +#define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) + +#define RTC_STATUS_CMP_INT_MASK (0x20U) +#define RTC_STATUS_CMP_INT_SHIFT (5U) +/*! CMP_INT - Compensation Interval */ +#define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) + +#define RTC_STATUS_WE_MASK (0xC0U) +#define RTC_STATUS_WE_SHIFT (6U) +/*! WE - Write Enable + * 0b10..Enable Write Protection - Registers are locked. + */ +#define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) + +#define RTC_STATUS_BUS_ERR_MASK (0x100U) +#define RTC_STATUS_BUS_ERR_SHIFT (8U) +/*! BUS_ERR - Bus Error + * 0b0..Read and write accesses are normal. + * 0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted. + */ +#define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) + +#define RTC_STATUS_CMP_DONE_MASK (0x800U) +#define RTC_STATUS_CMP_DONE_SHIFT (11U) +/*! CMP_DONE - Compensation Done + * 0b0..Compensation busy or not enabled + * 0b1..Compensation completed + */ +#define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define RTC_ISR_ALM_IS_MASK (0x4U) +#define RTC_ISR_ALM_IS_SHIFT (2U) +/*! ALM_IS - Alarm Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) + +#define RTC_ISR_DAY_IS_MASK (0x8U) +#define RTC_ISR_DAY_IS_SHIFT (3U) +/*! DAY_IS - Days Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) + +#define RTC_ISR_HOUR_IS_MASK (0x10U) +#define RTC_ISR_HOUR_IS_SHIFT (4U) +/*! HOUR_IS - Hours Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) + +#define RTC_ISR_MIN_IS_MASK (0x20U) +#define RTC_ISR_MIN_IS_SHIFT (5U) +/*! MIN_IS - Minutes Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) + +#define RTC_ISR_IS_1HZ_MASK (0x40U) +#define RTC_ISR_IS_1HZ_SHIFT (6U) +/*! IS_1HZ - 1 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) + +#define RTC_ISR_IS_2HZ_MASK (0x80U) +#define RTC_ISR_IS_2HZ_SHIFT (7U) +/*! IS_2HZ - 2 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) + +#define RTC_ISR_IS_4HZ_MASK (0x100U) +#define RTC_ISR_IS_4HZ_SHIFT (8U) +/*! IS_4HZ - 4 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) + +#define RTC_ISR_IS_8HZ_MASK (0x200U) +#define RTC_ISR_IS_8HZ_SHIFT (9U) +/*! IS_8HZ - 8 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) + +#define RTC_ISR_IS_16HZ_MASK (0x400U) +#define RTC_ISR_IS_16HZ_SHIFT (10U) +/*! IS_16HZ - 16 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) + +#define RTC_ISR_IS_32HZ_MASK (0x800U) +#define RTC_ISR_IS_32HZ_SHIFT (11U) +/*! IS_32HZ - 32 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) + +#define RTC_ISR_IS_64HZ_MASK (0x1000U) +#define RTC_ISR_IS_64HZ_SHIFT (12U) +/*! IS_64HZ - 64 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) + +#define RTC_ISR_IS_128HZ_MASK (0x2000U) +#define RTC_ISR_IS_128HZ_SHIFT (13U) +/*! IS_128HZ - 128 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) + +#define RTC_ISR_IS_256HZ_MASK (0x4000U) +#define RTC_ISR_IS_256HZ_SHIFT (14U) +/*! IS_256HZ - 256 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) + +#define RTC_ISR_IS_512HZ_MASK (0x8000U) +#define RTC_ISR_IS_512HZ_SHIFT (15U) +/*! IS_512HZ - 512 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_ALM_IE_MASK (0x4U) +#define RTC_IER_ALM_IE_SHIFT (2U) +/*! ALM_IE - Alarm Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) + +#define RTC_IER_DAY_IE_MASK (0x8U) +#define RTC_IER_DAY_IE_SHIFT (3U) +/*! DAY_IE - Days Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) + +#define RTC_IER_HOUR_IE_MASK (0x10U) +#define RTC_IER_HOUR_IE_SHIFT (4U) +/*! HOUR_IE - Hours Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) + +#define RTC_IER_MIN_IE_MASK (0x20U) +#define RTC_IER_MIN_IE_SHIFT (5U) +/*! MIN_IE - Minutes Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) + +#define RTC_IER_IE_1HZ_MASK (0x40U) +#define RTC_IER_IE_1HZ_SHIFT (6U) +/*! IE_1HZ - 1 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) + +#define RTC_IER_IE_2HZ_MASK (0x80U) +#define RTC_IER_IE_2HZ_SHIFT (7U) +/*! IE_2HZ - 2 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) + +#define RTC_IER_IE_4HZ_MASK (0x100U) +#define RTC_IER_IE_4HZ_SHIFT (8U) +/*! IE_4HZ - 4 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) + +#define RTC_IER_IE_8HZ_MASK (0x200U) +#define RTC_IER_IE_8HZ_SHIFT (9U) +/*! IE_8HZ - 8 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) + +#define RTC_IER_IE_16HZ_MASK (0x400U) +#define RTC_IER_IE_16HZ_SHIFT (10U) +/*! IE_16HZ - 16 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) + +#define RTC_IER_IE_32HZ_MASK (0x800U) +#define RTC_IER_IE_32HZ_SHIFT (11U) +/*! IE_32HZ - 32 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) + +#define RTC_IER_IE_64HZ_MASK (0x1000U) +#define RTC_IER_IE_64HZ_SHIFT (12U) +/*! IE_64HZ - 64 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) + +#define RTC_IER_IE_128HZ_MASK (0x2000U) +#define RTC_IER_IE_128HZ_SHIFT (13U) +/*! IE_128HZ - 128 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) + +#define RTC_IER_IE_256HZ_MASK (0x4000U) +#define RTC_IER_IE_256HZ_SHIFT (14U) +/*! IE_256HZ - 256 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) + +#define RTC_IER_IE_512HZ_MASK (0x8000U) +#define RTC_IER_IE_512HZ_SHIFT (15U) +/*! IE_512HZ - 512 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) +/*! @} */ + +/*! @name RTC_TEST2 - Sub Second Counter */ +/*! @{ */ + +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK (0xFFFFU) +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT (0U) +/*! SUB_SECOND_COUNT - Sub Second Counter Value */ +#define RTC_RTC_TEST2_SUB_SECOND_COUNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK) +/*! @} */ + +/*! @name DST_HOUR - Daylight Saving Hour */ +/*! @{ */ + +#define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) +#define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) +/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */ +#define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) + +#define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) +#define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) +/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */ +#define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) +/*! @} */ + +/*! @name DST_MONTH - Daylight Saving Month */ +/*! @{ */ + +#define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) +#define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) +/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */ +#define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) + +#define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) +#define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) +/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */ +#define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) +/*! @} */ + +/*! @name DST_DAY - Daylight Saving Day */ +/*! @{ */ + +#define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) +#define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) +/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */ +#define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) + +#define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) +#define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) +/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */ +#define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) +/*! @} */ + +/*! @name COMPEN - Compensation */ +/*! @{ */ + +#define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) +#define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) +/*! COMPEN_VAL - Compensation Value */ +#define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) +/*! @} */ + +/*! @name SUBSECOND_CTRL - Subsecond Control */ +/*! @{ */ + +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) +/*! SUB_SECOND_CNT_EN - Subsecond Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) +/*! @} */ + +/*! @name SUBSECOND_CNT - Subsecond Counter */ +/*! @{ */ + +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) +/*! SUBSECOND_CNT - Current Subsecond Counter Value */ +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Not timed out + * 0b1..Timed out + */ +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect + * 0b1..Clear the wake timer counter + */ +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +/* Backward compatibility for RTC */ +#define RTC RTC0 + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- S50 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Peripheral_Access_Layer S50 Peripheral Access Layer + * @{ + */ + +/** S50 - Register Layout Typedef */ +typedef struct { + __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ + __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ + __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ + __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ + __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ + __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ + __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ + __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ + __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ + __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ + __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ + __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ + __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ + __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ + __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ + __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ + __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ + __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ + __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ + uint8_t RESERVED_3[4]; + __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ + __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ + __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ + uint8_t RESERVED_4[212]; + __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ + __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ + __I uint32_t ELS_KS2; /**< Status Register, offset: 0x158 */ + __I uint32_t ELS_KS3; /**< Status Register, offset: 0x15C */ + __I uint32_t ELS_KS4; /**< Status Register, offset: 0x160 */ + __I uint32_t ELS_KS5; /**< Status Register, offset: 0x164 */ + __I uint32_t ELS_KS6; /**< Status Register, offset: 0x168 */ + __I uint32_t ELS_KS7; /**< Status Register, offset: 0x16C */ + __I uint32_t ELS_KS8; /**< Status Register, offset: 0x170 */ + __I uint32_t ELS_KS9; /**< Status Register, offset: 0x174 */ + __I uint32_t ELS_KS10; /**< Status Register, offset: 0x178 */ + __I uint32_t ELS_KS11; /**< Status Register, offset: 0x17C */ + __I uint32_t ELS_KS12; /**< Status Register, offset: 0x180 */ + __I uint32_t ELS_KS13; /**< Status Register, offset: 0x184 */ + __I uint32_t ELS_KS14; /**< Status Register, offset: 0x188 */ + __I uint32_t ELS_KS15; /**< Status Register, offset: 0x18C */ + __I uint32_t ELS_KS16; /**< Status Register, offset: 0x190 */ + __I uint32_t ELS_KS17; /**< Status Register, offset: 0x194 */ + __I uint32_t ELS_KS18; /**< Status Register, offset: 0x198 */ + __I uint32_t ELS_KS19; /**< Status Register, offset: 0x19C */ +} S50_Type; + +/* ---------------------------------------------------------------------------- + -- S50 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Register_Masks S50 Register Masks + * @{ + */ + +/*! @name ELS_STATUS - Status Register */ +/*! @{ */ + +#define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) +#define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) +/*! ELS_BUSY + * 0b1..Crypto sequence executing + * 0b0..Crypto sequence not executing + */ +#define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) +#define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) +/*! ELS_IRQ + * 0b1..Active interrupt + * 0b0..No active interrupt + */ +#define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) + +#define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) +#define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) +/*! ELS_ERR + * 0b1..Internal error detected + * 0b0..Internal error not detected + */ +#define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) + +#define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) +#define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) +/*! PRNG_RDY + * 0b0..Internal PRNG not ready + * 0b1..Internal PRNG ready + */ +#define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) + +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) +/*! ECDSA_VFY_STATUS + * 0b11..Invalid, Error + * 0b00..No verify run + * 0b01..Signature verify failed + * 0b10..Signature verify passed + */ +#define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) + +#define S50_ELS_STATUS_PPROT_MASK (0xC0U) +#define S50_ELS_STATUS_PPROT_SHIFT (6U) +/*! PPROT + * 0b10..Non-secure, non-privileged + * 0b11..Non-secure, privileged + * 0b00..Secure, non-privileged + * 0b01..Secure, privileged + */ +#define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) + +#define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) +/*! DRBG_ENT_LVL + * 0b10..HIGH, DRBG generates random numbers of high quality entropy + * 0b01..LOW, DRBG generates random numbers of low quality entropy + * 0b00..NONE + * 0b11..RFU, Reserved for Future Use + */ +#define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) + +#define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) +#define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) +/*! DTRNG_BUSY + * 0b1..Gathering entropy + * 0b0..Not gathering entropy + */ +#define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) +#define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) +/*! ELS_LOCKED + * 0b1..Locked by master + * 0b0..Not locked by master + */ +#define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) +/*! @} */ + +/*! @name ELS_CTRL - Control Register */ +/*! @{ */ + +#define S50_ELS_CTRL_ELS_EN_MASK (0x1U) +#define S50_ELS_CTRL_ELS_EN_SHIFT (0U) +/*! ELS_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) + +#define S50_ELS_CTRL_ELS_START_MASK (0x2U) +#define S50_ELS_CTRL_ELS_START_SHIFT (1U) +#define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) + +#define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) +#define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) +#define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) + +#define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) +#define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) +/*! ELS_CMD - ELS Command ID */ +#define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) + +#define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) +#define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) +/*! BYTE_ORDER + * 0b1..Big endian + * 0b0..Little endian + */ +#define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) +/*! @} */ + +/*! @name ELS_CMDCFG0 - Command Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) +#define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) +/*! @} */ + +/*! @name ELS_CFG - Configuration Register */ +/*! @{ */ + +#define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) +#define S50_ELS_CFG_ADCTRL_SHIFT (16U) +#define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) +/*! @} */ + +/*! @name ELS_KIDX0 - Keystore Index 0 */ +/*! @{ */ + +#define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) +#define S50_ELS_KIDX0_KIDX0_SHIFT (0U) +#define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) +/*! @} */ + +/*! @name ELS_KIDX1 - Keystore Index 1 */ +/*! @{ */ + +#define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) +#define S50_ELS_KIDX1_KIDX1_SHIFT (0U) +#define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) +/*! @} */ + +/*! @name ELS_KPROPIN - Key Properties Request */ +/*! @{ */ + +#define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) +#define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) +#define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0 - DMA Source 0 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) +#define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC1 - DMA Source 1 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) +#define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2 - DMA Source 2 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) +#define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0 - DMA Result 0 */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) +#define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) +/*! @} */ + +/*! @name ELS_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) +#define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN + * 0b0..Disables + * 0b1..Enables + */ +#define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) +#define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS - Error Status */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) +/*! BUS_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) + +#define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) +#define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) +/*! OPN_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) +#define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) +/*! ALG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) +#define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) +/*! ITG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) +#define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) +/*! FLT_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) + +#define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) +#define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) +/*! PRNG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) +#define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) +#define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) + +#define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) +/*! DTRNG_ERR + * 0b0..No error + * 0b1..TRNG error occurred + */ +#define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) +/*! ERR_CLR + * 0b1..Clears ELS error state + * 0b0..Exits ELS error state + */ +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name ELS_VERSION - Version Register */ +/*! @{ */ + +#define S50_ELS_VERSION_Z_MASK (0xFU) +#define S50_ELS_VERSION_Z_SHIFT (0U) +#define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) + +#define S50_ELS_VERSION_Y2_MASK (0xF0U) +#define S50_ELS_VERSION_Y2_SHIFT (4U) +#define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) + +#define S50_ELS_VERSION_Y1_MASK (0xF00U) +#define S50_ELS_VERSION_Y1_SHIFT (8U) +#define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) + +#define S50_ELS_VERSION_X_MASK (0xF000U) +#define S50_ELS_VERSION_X_SHIFT (12U) +#define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) + +#define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) +#define S50_ELS_VERSION_SW_Z_SHIFT (16U) +#define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) + +#define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) +#define S50_ELS_VERSION_SW_Y2_SHIFT (20U) +#define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) + +#define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) +#define S50_ELS_VERSION_SW_Y1_SHIFT (24U) +#define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) + +#define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) +#define S50_ELS_VERSION_SW_X_SHIFT (28U) +#define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) +/*! @} */ + +/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ +/*! @{ */ + +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC_CTRL - CRC Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) +/*! CMDCRC_RST + * 0b1..Resets the CRC command to its default value + * 0b0..No effect + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) +/*! CMDCRC_EN + * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. + * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC - Command CRC Value */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) +#define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) +/*! @} */ + +/*! @name ELS_SESSION_ID - Session ID */ +/*! @{ */ + +#define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) +#define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) +#define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) +/*! @} */ + +/*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ +/*! @{ */ + +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) +/*! @} */ + +/*! @name ELS_MASTER_ID - Master ID */ +/*! @{ */ + +#define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) +#define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) +#define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) +/*! @} */ + +/*! @name ELS_KIDX2 - Keystore Index 2 */ +/*! @{ */ + +#define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) +#define S50_ELS_KIDX2_KIDX2_SHIFT (0U) +#define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) +/*! @} */ + +/*! @name ELS_KS0 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS0_KS0_KSIZE_MASK (0x3U) +#define S50_ELS_KS0_KS0_KSIZE_SHIFT (0U) +/*! KS0_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS0_KS0_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KSIZE_SHIFT)) & S50_ELS_KS0_KS0_KSIZE_MASK) + +#define S50_ELS_KS0_KS0_KACT_MASK (0x20U) +#define S50_ELS_KS0_KS0_KACT_SHIFT (5U) +#define S50_ELS_KS0_KS0_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KACT_SHIFT)) & S50_ELS_KS0_KS0_KACT_MASK) + +#define S50_ELS_KS0_KS0_KBASE_MASK (0x40U) +#define S50_ELS_KS0_KS0_KBASE_SHIFT (6U) +#define S50_ELS_KS0_KS0_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KBASE_SHIFT)) & S50_ELS_KS0_KS0_KBASE_MASK) + +#define S50_ELS_KS0_KS0_FGP_MASK (0x80U) +#define S50_ELS_KS0_KS0_FGP_SHIFT (7U) +#define S50_ELS_KS0_KS0_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FGP_SHIFT)) & S50_ELS_KS0_KS0_FGP_MASK) + +#define S50_ELS_KS0_KS0_FRTN_MASK (0x100U) +#define S50_ELS_KS0_KS0_FRTN_SHIFT (8U) +#define S50_ELS_KS0_KS0_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FRTN_SHIFT)) & S50_ELS_KS0_KS0_FRTN_MASK) + +#define S50_ELS_KS0_KS0_FHWO_MASK (0x200U) +#define S50_ELS_KS0_KS0_FHWO_SHIFT (9U) +#define S50_ELS_KS0_KS0_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FHWO_SHIFT)) & S50_ELS_KS0_KS0_FHWO_MASK) + +#define S50_ELS_KS0_KS0_UKPUK_MASK (0x800U) +#define S50_ELS_KS0_KS0_UKPUK_SHIFT (11U) +#define S50_ELS_KS0_KS0_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKPUK_SHIFT)) & S50_ELS_KS0_KS0_UKPUK_MASK) + +#define S50_ELS_KS0_KS0_UTECDH_MASK (0x1000U) +#define S50_ELS_KS0_KS0_UTECDH_SHIFT (12U) +#define S50_ELS_KS0_KS0_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTECDH_SHIFT)) & S50_ELS_KS0_KS0_UTECDH_MASK) + +#define S50_ELS_KS0_KS0_UCMAC_MASK (0x2000U) +#define S50_ELS_KS0_KS0_UCMAC_SHIFT (13U) +#define S50_ELS_KS0_KS0_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCMAC_SHIFT)) & S50_ELS_KS0_KS0_UCMAC_MASK) + +#define S50_ELS_KS0_KS0_UKSK_MASK (0x4000U) +#define S50_ELS_KS0_KS0_UKSK_SHIFT (14U) +#define S50_ELS_KS0_KS0_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKSK_SHIFT)) & S50_ELS_KS0_KS0_UKSK_MASK) + +#define S50_ELS_KS0_KS0_URTF_MASK (0x8000U) +#define S50_ELS_KS0_KS0_URTF_SHIFT (15U) +#define S50_ELS_KS0_KS0_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_URTF_SHIFT)) & S50_ELS_KS0_KS0_URTF_MASK) + +#define S50_ELS_KS0_KS0_UCKDF_MASK (0x10000U) +#define S50_ELS_KS0_KS0_UCKDF_SHIFT (16U) +#define S50_ELS_KS0_KS0_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCKDF_SHIFT)) & S50_ELS_KS0_KS0_UCKDF_MASK) + +#define S50_ELS_KS0_KS0_UHKDF_MASK (0x20000U) +#define S50_ELS_KS0_KS0_UHKDF_SHIFT (17U) +#define S50_ELS_KS0_KS0_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHKDF_SHIFT)) & S50_ELS_KS0_KS0_UHKDF_MASK) + +#define S50_ELS_KS0_KS0_UECSG_MASK (0x40000U) +#define S50_ELS_KS0_KS0_UECSG_SHIFT (18U) +#define S50_ELS_KS0_KS0_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECSG_SHIFT)) & S50_ELS_KS0_KS0_UECSG_MASK) + +#define S50_ELS_KS0_KS0_UECDH_MASK (0x80000U) +#define S50_ELS_KS0_KS0_UECDH_SHIFT (19U) +#define S50_ELS_KS0_KS0_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECDH_SHIFT)) & S50_ELS_KS0_KS0_UECDH_MASK) + +#define S50_ELS_KS0_KS0_UAES_MASK (0x100000U) +#define S50_ELS_KS0_KS0_UAES_SHIFT (20U) +#define S50_ELS_KS0_KS0_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UAES_SHIFT)) & S50_ELS_KS0_KS0_UAES_MASK) + +#define S50_ELS_KS0_KS0_UHMAC_MASK (0x200000U) +#define S50_ELS_KS0_KS0_UHMAC_SHIFT (21U) +#define S50_ELS_KS0_KS0_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHMAC_SHIFT)) & S50_ELS_KS0_KS0_UHMAC_MASK) + +#define S50_ELS_KS0_KS0_UKWK_MASK (0x400000U) +#define S50_ELS_KS0_KS0_UKWK_SHIFT (22U) +#define S50_ELS_KS0_KS0_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKWK_SHIFT)) & S50_ELS_KS0_KS0_UKWK_MASK) + +#define S50_ELS_KS0_KS0_UKUOK_MASK (0x800000U) +#define S50_ELS_KS0_KS0_UKUOK_SHIFT (23U) +#define S50_ELS_KS0_KS0_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKUOK_SHIFT)) & S50_ELS_KS0_KS0_UKUOK_MASK) + +#define S50_ELS_KS0_KS0_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS0_KS0_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS0_KS0_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSPMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSPMS_MASK) + +#define S50_ELS_KS0_KS0_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS0_KS0_UTLSMS_SHIFT (25U) +#define S50_ELS_KS0_KS0_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSMS_MASK) + +#define S50_ELS_KS0_KS0_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS0_KS0_UKGSRC_SHIFT (26U) +#define S50_ELS_KS0_KS0_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKGSRC_SHIFT)) & S50_ELS_KS0_KS0_UKGSRC_MASK) + +#define S50_ELS_KS0_KS0_UHWO_MASK (0x8000000U) +#define S50_ELS_KS0_KS0_UHWO_SHIFT (27U) +#define S50_ELS_KS0_KS0_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHWO_SHIFT)) & S50_ELS_KS0_KS0_UHWO_MASK) + +#define S50_ELS_KS0_KS0_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS0_KS0_UWRPOK_SHIFT (28U) +#define S50_ELS_KS0_KS0_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UWRPOK_SHIFT)) & S50_ELS_KS0_KS0_UWRPOK_MASK) + +#define S50_ELS_KS0_KS0_UDUK_MASK (0x20000000U) +#define S50_ELS_KS0_KS0_UDUK_SHIFT (29U) +#define S50_ELS_KS0_KS0_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UDUK_SHIFT)) & S50_ELS_KS0_KS0_UDUK_MASK) + +#define S50_ELS_KS0_KS0_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS0_KS0_UPPROT_SHIFT (30U) +#define S50_ELS_KS0_KS0_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UPPROT_SHIFT)) & S50_ELS_KS0_KS0_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS1 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS1_KS1_KSIZE_MASK (0x3U) +#define S50_ELS_KS1_KS1_KSIZE_SHIFT (0U) +/*! KS1_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS1_KS1_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KSIZE_SHIFT)) & S50_ELS_KS1_KS1_KSIZE_MASK) + +#define S50_ELS_KS1_KS1_KACT_MASK (0x20U) +#define S50_ELS_KS1_KS1_KACT_SHIFT (5U) +#define S50_ELS_KS1_KS1_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KACT_SHIFT)) & S50_ELS_KS1_KS1_KACT_MASK) + +#define S50_ELS_KS1_KS1_KBASE_MASK (0x40U) +#define S50_ELS_KS1_KS1_KBASE_SHIFT (6U) +#define S50_ELS_KS1_KS1_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KBASE_SHIFT)) & S50_ELS_KS1_KS1_KBASE_MASK) + +#define S50_ELS_KS1_KS1_FGP_MASK (0x80U) +#define S50_ELS_KS1_KS1_FGP_SHIFT (7U) +#define S50_ELS_KS1_KS1_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FGP_SHIFT)) & S50_ELS_KS1_KS1_FGP_MASK) + +#define S50_ELS_KS1_KS1_FRTN_MASK (0x100U) +#define S50_ELS_KS1_KS1_FRTN_SHIFT (8U) +#define S50_ELS_KS1_KS1_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FRTN_SHIFT)) & S50_ELS_KS1_KS1_FRTN_MASK) + +#define S50_ELS_KS1_KS1_FHWO_MASK (0x200U) +#define S50_ELS_KS1_KS1_FHWO_SHIFT (9U) +#define S50_ELS_KS1_KS1_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FHWO_SHIFT)) & S50_ELS_KS1_KS1_FHWO_MASK) + +#define S50_ELS_KS1_KS1_UKPUK_MASK (0x800U) +#define S50_ELS_KS1_KS1_UKPUK_SHIFT (11U) +#define S50_ELS_KS1_KS1_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKPUK_SHIFT)) & S50_ELS_KS1_KS1_UKPUK_MASK) + +#define S50_ELS_KS1_KS1_UTECDH_MASK (0x1000U) +#define S50_ELS_KS1_KS1_UTECDH_SHIFT (12U) +#define S50_ELS_KS1_KS1_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTECDH_SHIFT)) & S50_ELS_KS1_KS1_UTECDH_MASK) + +#define S50_ELS_KS1_KS1_UCMAC_MASK (0x2000U) +#define S50_ELS_KS1_KS1_UCMAC_SHIFT (13U) +#define S50_ELS_KS1_KS1_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCMAC_SHIFT)) & S50_ELS_KS1_KS1_UCMAC_MASK) + +#define S50_ELS_KS1_KS1_UKSK_MASK (0x4000U) +#define S50_ELS_KS1_KS1_UKSK_SHIFT (14U) +#define S50_ELS_KS1_KS1_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKSK_SHIFT)) & S50_ELS_KS1_KS1_UKSK_MASK) + +#define S50_ELS_KS1_KS1_URTF_MASK (0x8000U) +#define S50_ELS_KS1_KS1_URTF_SHIFT (15U) +#define S50_ELS_KS1_KS1_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_URTF_SHIFT)) & S50_ELS_KS1_KS1_URTF_MASK) + +#define S50_ELS_KS1_KS1_UCKDF_MASK (0x10000U) +#define S50_ELS_KS1_KS1_UCKDF_SHIFT (16U) +#define S50_ELS_KS1_KS1_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCKDF_SHIFT)) & S50_ELS_KS1_KS1_UCKDF_MASK) + +#define S50_ELS_KS1_KS1_UHKDF_MASK (0x20000U) +#define S50_ELS_KS1_KS1_UHKDF_SHIFT (17U) +#define S50_ELS_KS1_KS1_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHKDF_SHIFT)) & S50_ELS_KS1_KS1_UHKDF_MASK) + +#define S50_ELS_KS1_KS1_UECSG_MASK (0x40000U) +#define S50_ELS_KS1_KS1_UECSG_SHIFT (18U) +#define S50_ELS_KS1_KS1_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECSG_SHIFT)) & S50_ELS_KS1_KS1_UECSG_MASK) + +#define S50_ELS_KS1_KS1_UECDH_MASK (0x80000U) +#define S50_ELS_KS1_KS1_UECDH_SHIFT (19U) +#define S50_ELS_KS1_KS1_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECDH_SHIFT)) & S50_ELS_KS1_KS1_UECDH_MASK) + +#define S50_ELS_KS1_KS1_UAES_MASK (0x100000U) +#define S50_ELS_KS1_KS1_UAES_SHIFT (20U) +#define S50_ELS_KS1_KS1_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UAES_SHIFT)) & S50_ELS_KS1_KS1_UAES_MASK) + +#define S50_ELS_KS1_KS1_UHMAC_MASK (0x200000U) +#define S50_ELS_KS1_KS1_UHMAC_SHIFT (21U) +#define S50_ELS_KS1_KS1_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHMAC_SHIFT)) & S50_ELS_KS1_KS1_UHMAC_MASK) + +#define S50_ELS_KS1_KS1_UKWK_MASK (0x400000U) +#define S50_ELS_KS1_KS1_UKWK_SHIFT (22U) +#define S50_ELS_KS1_KS1_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKWK_SHIFT)) & S50_ELS_KS1_KS1_UKWK_MASK) + +#define S50_ELS_KS1_KS1_UKUOK_MASK (0x800000U) +#define S50_ELS_KS1_KS1_UKUOK_SHIFT (23U) +#define S50_ELS_KS1_KS1_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKUOK_SHIFT)) & S50_ELS_KS1_KS1_UKUOK_MASK) + +#define S50_ELS_KS1_KS1_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS1_KS1_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS1_KS1_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSPMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSPMS_MASK) + +#define S50_ELS_KS1_KS1_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS1_KS1_UTLSMS_SHIFT (25U) +#define S50_ELS_KS1_KS1_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSMS_MASK) + +#define S50_ELS_KS1_KS1_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS1_KS1_UKGSRC_SHIFT (26U) +#define S50_ELS_KS1_KS1_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKGSRC_SHIFT)) & S50_ELS_KS1_KS1_UKGSRC_MASK) + +#define S50_ELS_KS1_KS1_UHWO_MASK (0x8000000U) +#define S50_ELS_KS1_KS1_UHWO_SHIFT (27U) +#define S50_ELS_KS1_KS1_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHWO_SHIFT)) & S50_ELS_KS1_KS1_UHWO_MASK) + +#define S50_ELS_KS1_KS1_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS1_KS1_UWRPOK_SHIFT (28U) +#define S50_ELS_KS1_KS1_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UWRPOK_SHIFT)) & S50_ELS_KS1_KS1_UWRPOK_MASK) + +#define S50_ELS_KS1_KS1_UDUK_MASK (0x20000000U) +#define S50_ELS_KS1_KS1_UDUK_SHIFT (29U) +#define S50_ELS_KS1_KS1_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UDUK_SHIFT)) & S50_ELS_KS1_KS1_UDUK_MASK) + +#define S50_ELS_KS1_KS1_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS1_KS1_UPPROT_SHIFT (30U) +#define S50_ELS_KS1_KS1_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UPPROT_SHIFT)) & S50_ELS_KS1_KS1_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS2 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS2_KS2_KSIZE_MASK (0x3U) +#define S50_ELS_KS2_KS2_KSIZE_SHIFT (0U) +/*! KS2_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS2_KS2_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KSIZE_SHIFT)) & S50_ELS_KS2_KS2_KSIZE_MASK) + +#define S50_ELS_KS2_KS2_KACT_MASK (0x20U) +#define S50_ELS_KS2_KS2_KACT_SHIFT (5U) +#define S50_ELS_KS2_KS2_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KACT_SHIFT)) & S50_ELS_KS2_KS2_KACT_MASK) + +#define S50_ELS_KS2_KS2_KBASE_MASK (0x40U) +#define S50_ELS_KS2_KS2_KBASE_SHIFT (6U) +#define S50_ELS_KS2_KS2_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KBASE_SHIFT)) & S50_ELS_KS2_KS2_KBASE_MASK) + +#define S50_ELS_KS2_KS2_FGP_MASK (0x80U) +#define S50_ELS_KS2_KS2_FGP_SHIFT (7U) +#define S50_ELS_KS2_KS2_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FGP_SHIFT)) & S50_ELS_KS2_KS2_FGP_MASK) + +#define S50_ELS_KS2_KS2_FRTN_MASK (0x100U) +#define S50_ELS_KS2_KS2_FRTN_SHIFT (8U) +#define S50_ELS_KS2_KS2_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FRTN_SHIFT)) & S50_ELS_KS2_KS2_FRTN_MASK) + +#define S50_ELS_KS2_KS2_FHWO_MASK (0x200U) +#define S50_ELS_KS2_KS2_FHWO_SHIFT (9U) +#define S50_ELS_KS2_KS2_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FHWO_SHIFT)) & S50_ELS_KS2_KS2_FHWO_MASK) + +#define S50_ELS_KS2_KS2_UKPUK_MASK (0x800U) +#define S50_ELS_KS2_KS2_UKPUK_SHIFT (11U) +#define S50_ELS_KS2_KS2_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKPUK_SHIFT)) & S50_ELS_KS2_KS2_UKPUK_MASK) + +#define S50_ELS_KS2_KS2_UTECDH_MASK (0x1000U) +#define S50_ELS_KS2_KS2_UTECDH_SHIFT (12U) +#define S50_ELS_KS2_KS2_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTECDH_SHIFT)) & S50_ELS_KS2_KS2_UTECDH_MASK) + +#define S50_ELS_KS2_KS2_UCMAC_MASK (0x2000U) +#define S50_ELS_KS2_KS2_UCMAC_SHIFT (13U) +#define S50_ELS_KS2_KS2_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCMAC_SHIFT)) & S50_ELS_KS2_KS2_UCMAC_MASK) + +#define S50_ELS_KS2_KS2_UKSK_MASK (0x4000U) +#define S50_ELS_KS2_KS2_UKSK_SHIFT (14U) +#define S50_ELS_KS2_KS2_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKSK_SHIFT)) & S50_ELS_KS2_KS2_UKSK_MASK) + +#define S50_ELS_KS2_KS2_URTF_MASK (0x8000U) +#define S50_ELS_KS2_KS2_URTF_SHIFT (15U) +#define S50_ELS_KS2_KS2_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_URTF_SHIFT)) & S50_ELS_KS2_KS2_URTF_MASK) + +#define S50_ELS_KS2_KS2_UCKDF_MASK (0x10000U) +#define S50_ELS_KS2_KS2_UCKDF_SHIFT (16U) +#define S50_ELS_KS2_KS2_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCKDF_SHIFT)) & S50_ELS_KS2_KS2_UCKDF_MASK) + +#define S50_ELS_KS2_KS2_UHKDF_MASK (0x20000U) +#define S50_ELS_KS2_KS2_UHKDF_SHIFT (17U) +#define S50_ELS_KS2_KS2_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHKDF_SHIFT)) & S50_ELS_KS2_KS2_UHKDF_MASK) + +#define S50_ELS_KS2_KS2_UECSG_MASK (0x40000U) +#define S50_ELS_KS2_KS2_UECSG_SHIFT (18U) +#define S50_ELS_KS2_KS2_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECSG_SHIFT)) & S50_ELS_KS2_KS2_UECSG_MASK) + +#define S50_ELS_KS2_KS2_UECDH_MASK (0x80000U) +#define S50_ELS_KS2_KS2_UECDH_SHIFT (19U) +#define S50_ELS_KS2_KS2_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECDH_SHIFT)) & S50_ELS_KS2_KS2_UECDH_MASK) + +#define S50_ELS_KS2_KS2_UAES_MASK (0x100000U) +#define S50_ELS_KS2_KS2_UAES_SHIFT (20U) +#define S50_ELS_KS2_KS2_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UAES_SHIFT)) & S50_ELS_KS2_KS2_UAES_MASK) + +#define S50_ELS_KS2_KS2_UHMAC_MASK (0x200000U) +#define S50_ELS_KS2_KS2_UHMAC_SHIFT (21U) +#define S50_ELS_KS2_KS2_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHMAC_SHIFT)) & S50_ELS_KS2_KS2_UHMAC_MASK) + +#define S50_ELS_KS2_KS2_UKWK_MASK (0x400000U) +#define S50_ELS_KS2_KS2_UKWK_SHIFT (22U) +#define S50_ELS_KS2_KS2_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKWK_SHIFT)) & S50_ELS_KS2_KS2_UKWK_MASK) + +#define S50_ELS_KS2_KS2_UKUOK_MASK (0x800000U) +#define S50_ELS_KS2_KS2_UKUOK_SHIFT (23U) +#define S50_ELS_KS2_KS2_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKUOK_SHIFT)) & S50_ELS_KS2_KS2_UKUOK_MASK) + +#define S50_ELS_KS2_KS2_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS2_KS2_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS2_KS2_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSPMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSPMS_MASK) + +#define S50_ELS_KS2_KS2_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS2_KS2_UTLSMS_SHIFT (25U) +#define S50_ELS_KS2_KS2_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSMS_MASK) + +#define S50_ELS_KS2_KS2_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS2_KS2_UKGSRC_SHIFT (26U) +#define S50_ELS_KS2_KS2_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKGSRC_SHIFT)) & S50_ELS_KS2_KS2_UKGSRC_MASK) + +#define S50_ELS_KS2_KS2_UHWO_MASK (0x8000000U) +#define S50_ELS_KS2_KS2_UHWO_SHIFT (27U) +#define S50_ELS_KS2_KS2_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHWO_SHIFT)) & S50_ELS_KS2_KS2_UHWO_MASK) + +#define S50_ELS_KS2_KS2_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS2_KS2_UWRPOK_SHIFT (28U) +#define S50_ELS_KS2_KS2_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UWRPOK_SHIFT)) & S50_ELS_KS2_KS2_UWRPOK_MASK) + +#define S50_ELS_KS2_KS2_UDUK_MASK (0x20000000U) +#define S50_ELS_KS2_KS2_UDUK_SHIFT (29U) +#define S50_ELS_KS2_KS2_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UDUK_SHIFT)) & S50_ELS_KS2_KS2_UDUK_MASK) + +#define S50_ELS_KS2_KS2_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS2_KS2_UPPROT_SHIFT (30U) +#define S50_ELS_KS2_KS2_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UPPROT_SHIFT)) & S50_ELS_KS2_KS2_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS3 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS3_KS3_KSIZE_MASK (0x3U) +#define S50_ELS_KS3_KS3_KSIZE_SHIFT (0U) +/*! KS3_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS3_KS3_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KSIZE_SHIFT)) & S50_ELS_KS3_KS3_KSIZE_MASK) + +#define S50_ELS_KS3_KS3_KACT_MASK (0x20U) +#define S50_ELS_KS3_KS3_KACT_SHIFT (5U) +#define S50_ELS_KS3_KS3_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KACT_SHIFT)) & S50_ELS_KS3_KS3_KACT_MASK) + +#define S50_ELS_KS3_KS3_KBASE_MASK (0x40U) +#define S50_ELS_KS3_KS3_KBASE_SHIFT (6U) +#define S50_ELS_KS3_KS3_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KBASE_SHIFT)) & S50_ELS_KS3_KS3_KBASE_MASK) + +#define S50_ELS_KS3_KS3_FGP_MASK (0x80U) +#define S50_ELS_KS3_KS3_FGP_SHIFT (7U) +#define S50_ELS_KS3_KS3_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FGP_SHIFT)) & S50_ELS_KS3_KS3_FGP_MASK) + +#define S50_ELS_KS3_KS3_FRTN_MASK (0x100U) +#define S50_ELS_KS3_KS3_FRTN_SHIFT (8U) +#define S50_ELS_KS3_KS3_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FRTN_SHIFT)) & S50_ELS_KS3_KS3_FRTN_MASK) + +#define S50_ELS_KS3_KS3_FHWO_MASK (0x200U) +#define S50_ELS_KS3_KS3_FHWO_SHIFT (9U) +#define S50_ELS_KS3_KS3_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FHWO_SHIFT)) & S50_ELS_KS3_KS3_FHWO_MASK) + +#define S50_ELS_KS3_KS3_UKPUK_MASK (0x800U) +#define S50_ELS_KS3_KS3_UKPUK_SHIFT (11U) +#define S50_ELS_KS3_KS3_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKPUK_SHIFT)) & S50_ELS_KS3_KS3_UKPUK_MASK) + +#define S50_ELS_KS3_KS3_UTECDH_MASK (0x1000U) +#define S50_ELS_KS3_KS3_UTECDH_SHIFT (12U) +#define S50_ELS_KS3_KS3_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTECDH_SHIFT)) & S50_ELS_KS3_KS3_UTECDH_MASK) + +#define S50_ELS_KS3_KS3_UCMAC_MASK (0x2000U) +#define S50_ELS_KS3_KS3_UCMAC_SHIFT (13U) +#define S50_ELS_KS3_KS3_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCMAC_SHIFT)) & S50_ELS_KS3_KS3_UCMAC_MASK) + +#define S50_ELS_KS3_KS3_UKSK_MASK (0x4000U) +#define S50_ELS_KS3_KS3_UKSK_SHIFT (14U) +#define S50_ELS_KS3_KS3_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKSK_SHIFT)) & S50_ELS_KS3_KS3_UKSK_MASK) + +#define S50_ELS_KS3_KS3_URTF_MASK (0x8000U) +#define S50_ELS_KS3_KS3_URTF_SHIFT (15U) +#define S50_ELS_KS3_KS3_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_URTF_SHIFT)) & S50_ELS_KS3_KS3_URTF_MASK) + +#define S50_ELS_KS3_KS3_UCKDF_MASK (0x10000U) +#define S50_ELS_KS3_KS3_UCKDF_SHIFT (16U) +#define S50_ELS_KS3_KS3_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCKDF_SHIFT)) & S50_ELS_KS3_KS3_UCKDF_MASK) + +#define S50_ELS_KS3_KS3_UHKDF_MASK (0x20000U) +#define S50_ELS_KS3_KS3_UHKDF_SHIFT (17U) +#define S50_ELS_KS3_KS3_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHKDF_SHIFT)) & S50_ELS_KS3_KS3_UHKDF_MASK) + +#define S50_ELS_KS3_KS3_UECSG_MASK (0x40000U) +#define S50_ELS_KS3_KS3_UECSG_SHIFT (18U) +#define S50_ELS_KS3_KS3_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECSG_SHIFT)) & S50_ELS_KS3_KS3_UECSG_MASK) + +#define S50_ELS_KS3_KS3_UECDH_MASK (0x80000U) +#define S50_ELS_KS3_KS3_UECDH_SHIFT (19U) +#define S50_ELS_KS3_KS3_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECDH_SHIFT)) & S50_ELS_KS3_KS3_UECDH_MASK) + +#define S50_ELS_KS3_KS3_UAES_MASK (0x100000U) +#define S50_ELS_KS3_KS3_UAES_SHIFT (20U) +#define S50_ELS_KS3_KS3_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UAES_SHIFT)) & S50_ELS_KS3_KS3_UAES_MASK) + +#define S50_ELS_KS3_KS3_UHMAC_MASK (0x200000U) +#define S50_ELS_KS3_KS3_UHMAC_SHIFT (21U) +#define S50_ELS_KS3_KS3_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHMAC_SHIFT)) & S50_ELS_KS3_KS3_UHMAC_MASK) + +#define S50_ELS_KS3_KS3_UKWK_MASK (0x400000U) +#define S50_ELS_KS3_KS3_UKWK_SHIFT (22U) +#define S50_ELS_KS3_KS3_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKWK_SHIFT)) & S50_ELS_KS3_KS3_UKWK_MASK) + +#define S50_ELS_KS3_KS3_UKUOK_MASK (0x800000U) +#define S50_ELS_KS3_KS3_UKUOK_SHIFT (23U) +#define S50_ELS_KS3_KS3_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKUOK_SHIFT)) & S50_ELS_KS3_KS3_UKUOK_MASK) + +#define S50_ELS_KS3_KS3_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS3_KS3_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS3_KS3_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSPMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSPMS_MASK) + +#define S50_ELS_KS3_KS3_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS3_KS3_UTLSMS_SHIFT (25U) +#define S50_ELS_KS3_KS3_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSMS_MASK) + +#define S50_ELS_KS3_KS3_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS3_KS3_UKGSRC_SHIFT (26U) +#define S50_ELS_KS3_KS3_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKGSRC_SHIFT)) & S50_ELS_KS3_KS3_UKGSRC_MASK) + +#define S50_ELS_KS3_KS3_UHWO_MASK (0x8000000U) +#define S50_ELS_KS3_KS3_UHWO_SHIFT (27U) +#define S50_ELS_KS3_KS3_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHWO_SHIFT)) & S50_ELS_KS3_KS3_UHWO_MASK) + +#define S50_ELS_KS3_KS3_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS3_KS3_UWRPOK_SHIFT (28U) +#define S50_ELS_KS3_KS3_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UWRPOK_SHIFT)) & S50_ELS_KS3_KS3_UWRPOK_MASK) + +#define S50_ELS_KS3_KS3_UDUK_MASK (0x20000000U) +#define S50_ELS_KS3_KS3_UDUK_SHIFT (29U) +#define S50_ELS_KS3_KS3_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UDUK_SHIFT)) & S50_ELS_KS3_KS3_UDUK_MASK) + +#define S50_ELS_KS3_KS3_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS3_KS3_UPPROT_SHIFT (30U) +#define S50_ELS_KS3_KS3_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UPPROT_SHIFT)) & S50_ELS_KS3_KS3_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS4 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS4_KS4_KSIZE_MASK (0x3U) +#define S50_ELS_KS4_KS4_KSIZE_SHIFT (0U) +/*! KS4_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS4_KS4_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KSIZE_SHIFT)) & S50_ELS_KS4_KS4_KSIZE_MASK) + +#define S50_ELS_KS4_KS4_KACT_MASK (0x20U) +#define S50_ELS_KS4_KS4_KACT_SHIFT (5U) +#define S50_ELS_KS4_KS4_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KACT_SHIFT)) & S50_ELS_KS4_KS4_KACT_MASK) + +#define S50_ELS_KS4_KS4_KBASE_MASK (0x40U) +#define S50_ELS_KS4_KS4_KBASE_SHIFT (6U) +#define S50_ELS_KS4_KS4_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KBASE_SHIFT)) & S50_ELS_KS4_KS4_KBASE_MASK) + +#define S50_ELS_KS4_KS4_FGP_MASK (0x80U) +#define S50_ELS_KS4_KS4_FGP_SHIFT (7U) +#define S50_ELS_KS4_KS4_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FGP_SHIFT)) & S50_ELS_KS4_KS4_FGP_MASK) + +#define S50_ELS_KS4_KS4_FRTN_MASK (0x100U) +#define S50_ELS_KS4_KS4_FRTN_SHIFT (8U) +#define S50_ELS_KS4_KS4_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FRTN_SHIFT)) & S50_ELS_KS4_KS4_FRTN_MASK) + +#define S50_ELS_KS4_KS4_FHWO_MASK (0x200U) +#define S50_ELS_KS4_KS4_FHWO_SHIFT (9U) +#define S50_ELS_KS4_KS4_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FHWO_SHIFT)) & S50_ELS_KS4_KS4_FHWO_MASK) + +#define S50_ELS_KS4_KS4_UKPUK_MASK (0x800U) +#define S50_ELS_KS4_KS4_UKPUK_SHIFT (11U) +#define S50_ELS_KS4_KS4_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKPUK_SHIFT)) & S50_ELS_KS4_KS4_UKPUK_MASK) + +#define S50_ELS_KS4_KS4_UTECDH_MASK (0x1000U) +#define S50_ELS_KS4_KS4_UTECDH_SHIFT (12U) +#define S50_ELS_KS4_KS4_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTECDH_SHIFT)) & S50_ELS_KS4_KS4_UTECDH_MASK) + +#define S50_ELS_KS4_KS4_UCMAC_MASK (0x2000U) +#define S50_ELS_KS4_KS4_UCMAC_SHIFT (13U) +#define S50_ELS_KS4_KS4_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCMAC_SHIFT)) & S50_ELS_KS4_KS4_UCMAC_MASK) + +#define S50_ELS_KS4_KS4_UKSK_MASK (0x4000U) +#define S50_ELS_KS4_KS4_UKSK_SHIFT (14U) +#define S50_ELS_KS4_KS4_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKSK_SHIFT)) & S50_ELS_KS4_KS4_UKSK_MASK) + +#define S50_ELS_KS4_KS4_URTF_MASK (0x8000U) +#define S50_ELS_KS4_KS4_URTF_SHIFT (15U) +#define S50_ELS_KS4_KS4_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_URTF_SHIFT)) & S50_ELS_KS4_KS4_URTF_MASK) + +#define S50_ELS_KS4_KS4_UCKDF_MASK (0x10000U) +#define S50_ELS_KS4_KS4_UCKDF_SHIFT (16U) +#define S50_ELS_KS4_KS4_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCKDF_SHIFT)) & S50_ELS_KS4_KS4_UCKDF_MASK) + +#define S50_ELS_KS4_KS4_UHKDF_MASK (0x20000U) +#define S50_ELS_KS4_KS4_UHKDF_SHIFT (17U) +#define S50_ELS_KS4_KS4_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHKDF_SHIFT)) & S50_ELS_KS4_KS4_UHKDF_MASK) + +#define S50_ELS_KS4_KS4_UECSG_MASK (0x40000U) +#define S50_ELS_KS4_KS4_UECSG_SHIFT (18U) +#define S50_ELS_KS4_KS4_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECSG_SHIFT)) & S50_ELS_KS4_KS4_UECSG_MASK) + +#define S50_ELS_KS4_KS4_UECDH_MASK (0x80000U) +#define S50_ELS_KS4_KS4_UECDH_SHIFT (19U) +#define S50_ELS_KS4_KS4_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECDH_SHIFT)) & S50_ELS_KS4_KS4_UECDH_MASK) + +#define S50_ELS_KS4_KS4_UAES_MASK (0x100000U) +#define S50_ELS_KS4_KS4_UAES_SHIFT (20U) +#define S50_ELS_KS4_KS4_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UAES_SHIFT)) & S50_ELS_KS4_KS4_UAES_MASK) + +#define S50_ELS_KS4_KS4_UHMAC_MASK (0x200000U) +#define S50_ELS_KS4_KS4_UHMAC_SHIFT (21U) +#define S50_ELS_KS4_KS4_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHMAC_SHIFT)) & S50_ELS_KS4_KS4_UHMAC_MASK) + +#define S50_ELS_KS4_KS4_UKWK_MASK (0x400000U) +#define S50_ELS_KS4_KS4_UKWK_SHIFT (22U) +#define S50_ELS_KS4_KS4_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKWK_SHIFT)) & S50_ELS_KS4_KS4_UKWK_MASK) + +#define S50_ELS_KS4_KS4_UKUOK_MASK (0x800000U) +#define S50_ELS_KS4_KS4_UKUOK_SHIFT (23U) +#define S50_ELS_KS4_KS4_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKUOK_SHIFT)) & S50_ELS_KS4_KS4_UKUOK_MASK) + +#define S50_ELS_KS4_KS4_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS4_KS4_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS4_KS4_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSPMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSPMS_MASK) + +#define S50_ELS_KS4_KS4_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS4_KS4_UTLSMS_SHIFT (25U) +#define S50_ELS_KS4_KS4_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSMS_MASK) + +#define S50_ELS_KS4_KS4_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS4_KS4_UKGSRC_SHIFT (26U) +#define S50_ELS_KS4_KS4_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKGSRC_SHIFT)) & S50_ELS_KS4_KS4_UKGSRC_MASK) + +#define S50_ELS_KS4_KS4_UHWO_MASK (0x8000000U) +#define S50_ELS_KS4_KS4_UHWO_SHIFT (27U) +#define S50_ELS_KS4_KS4_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHWO_SHIFT)) & S50_ELS_KS4_KS4_UHWO_MASK) + +#define S50_ELS_KS4_KS4_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS4_KS4_UWRPOK_SHIFT (28U) +#define S50_ELS_KS4_KS4_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UWRPOK_SHIFT)) & S50_ELS_KS4_KS4_UWRPOK_MASK) + +#define S50_ELS_KS4_KS4_UDUK_MASK (0x20000000U) +#define S50_ELS_KS4_KS4_UDUK_SHIFT (29U) +#define S50_ELS_KS4_KS4_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UDUK_SHIFT)) & S50_ELS_KS4_KS4_UDUK_MASK) + +#define S50_ELS_KS4_KS4_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS4_KS4_UPPROT_SHIFT (30U) +#define S50_ELS_KS4_KS4_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UPPROT_SHIFT)) & S50_ELS_KS4_KS4_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS5 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS5_KS5_KSIZE_MASK (0x3U) +#define S50_ELS_KS5_KS5_KSIZE_SHIFT (0U) +/*! KS5_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS5_KS5_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KSIZE_SHIFT)) & S50_ELS_KS5_KS5_KSIZE_MASK) + +#define S50_ELS_KS5_KS5_KACT_MASK (0x20U) +#define S50_ELS_KS5_KS5_KACT_SHIFT (5U) +#define S50_ELS_KS5_KS5_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KACT_SHIFT)) & S50_ELS_KS5_KS5_KACT_MASK) + +#define S50_ELS_KS5_KS5_KBASE_MASK (0x40U) +#define S50_ELS_KS5_KS5_KBASE_SHIFT (6U) +#define S50_ELS_KS5_KS5_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KBASE_SHIFT)) & S50_ELS_KS5_KS5_KBASE_MASK) + +#define S50_ELS_KS5_KS5_FGP_MASK (0x80U) +#define S50_ELS_KS5_KS5_FGP_SHIFT (7U) +#define S50_ELS_KS5_KS5_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FGP_SHIFT)) & S50_ELS_KS5_KS5_FGP_MASK) + +#define S50_ELS_KS5_KS5_FRTN_MASK (0x100U) +#define S50_ELS_KS5_KS5_FRTN_SHIFT (8U) +#define S50_ELS_KS5_KS5_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FRTN_SHIFT)) & S50_ELS_KS5_KS5_FRTN_MASK) + +#define S50_ELS_KS5_KS5_FHWO_MASK (0x200U) +#define S50_ELS_KS5_KS5_FHWO_SHIFT (9U) +#define S50_ELS_KS5_KS5_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FHWO_SHIFT)) & S50_ELS_KS5_KS5_FHWO_MASK) + +#define S50_ELS_KS5_KS5_UKPUK_MASK (0x800U) +#define S50_ELS_KS5_KS5_UKPUK_SHIFT (11U) +#define S50_ELS_KS5_KS5_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKPUK_SHIFT)) & S50_ELS_KS5_KS5_UKPUK_MASK) + +#define S50_ELS_KS5_KS5_UTECDH_MASK (0x1000U) +#define S50_ELS_KS5_KS5_UTECDH_SHIFT (12U) +#define S50_ELS_KS5_KS5_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTECDH_SHIFT)) & S50_ELS_KS5_KS5_UTECDH_MASK) + +#define S50_ELS_KS5_KS5_UCMAC_MASK (0x2000U) +#define S50_ELS_KS5_KS5_UCMAC_SHIFT (13U) +#define S50_ELS_KS5_KS5_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCMAC_SHIFT)) & S50_ELS_KS5_KS5_UCMAC_MASK) + +#define S50_ELS_KS5_KS5_UKSK_MASK (0x4000U) +#define S50_ELS_KS5_KS5_UKSK_SHIFT (14U) +#define S50_ELS_KS5_KS5_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKSK_SHIFT)) & S50_ELS_KS5_KS5_UKSK_MASK) + +#define S50_ELS_KS5_KS5_URTF_MASK (0x8000U) +#define S50_ELS_KS5_KS5_URTF_SHIFT (15U) +#define S50_ELS_KS5_KS5_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_URTF_SHIFT)) & S50_ELS_KS5_KS5_URTF_MASK) + +#define S50_ELS_KS5_KS5_UCKDF_MASK (0x10000U) +#define S50_ELS_KS5_KS5_UCKDF_SHIFT (16U) +#define S50_ELS_KS5_KS5_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCKDF_SHIFT)) & S50_ELS_KS5_KS5_UCKDF_MASK) + +#define S50_ELS_KS5_KS5_UHKDF_MASK (0x20000U) +#define S50_ELS_KS5_KS5_UHKDF_SHIFT (17U) +#define S50_ELS_KS5_KS5_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHKDF_SHIFT)) & S50_ELS_KS5_KS5_UHKDF_MASK) + +#define S50_ELS_KS5_KS5_UECSG_MASK (0x40000U) +#define S50_ELS_KS5_KS5_UECSG_SHIFT (18U) +#define S50_ELS_KS5_KS5_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECSG_SHIFT)) & S50_ELS_KS5_KS5_UECSG_MASK) + +#define S50_ELS_KS5_KS5_UECDH_MASK (0x80000U) +#define S50_ELS_KS5_KS5_UECDH_SHIFT (19U) +#define S50_ELS_KS5_KS5_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECDH_SHIFT)) & S50_ELS_KS5_KS5_UECDH_MASK) + +#define S50_ELS_KS5_KS5_UAES_MASK (0x100000U) +#define S50_ELS_KS5_KS5_UAES_SHIFT (20U) +#define S50_ELS_KS5_KS5_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UAES_SHIFT)) & S50_ELS_KS5_KS5_UAES_MASK) + +#define S50_ELS_KS5_KS5_UHMAC_MASK (0x200000U) +#define S50_ELS_KS5_KS5_UHMAC_SHIFT (21U) +#define S50_ELS_KS5_KS5_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHMAC_SHIFT)) & S50_ELS_KS5_KS5_UHMAC_MASK) + +#define S50_ELS_KS5_KS5_UKWK_MASK (0x400000U) +#define S50_ELS_KS5_KS5_UKWK_SHIFT (22U) +#define S50_ELS_KS5_KS5_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKWK_SHIFT)) & S50_ELS_KS5_KS5_UKWK_MASK) + +#define S50_ELS_KS5_KS5_UKUOK_MASK (0x800000U) +#define S50_ELS_KS5_KS5_UKUOK_SHIFT (23U) +#define S50_ELS_KS5_KS5_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKUOK_SHIFT)) & S50_ELS_KS5_KS5_UKUOK_MASK) + +#define S50_ELS_KS5_KS5_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS5_KS5_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS5_KS5_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSPMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSPMS_MASK) + +#define S50_ELS_KS5_KS5_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS5_KS5_UTLSMS_SHIFT (25U) +#define S50_ELS_KS5_KS5_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSMS_MASK) + +#define S50_ELS_KS5_KS5_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS5_KS5_UKGSRC_SHIFT (26U) +#define S50_ELS_KS5_KS5_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKGSRC_SHIFT)) & S50_ELS_KS5_KS5_UKGSRC_MASK) + +#define S50_ELS_KS5_KS5_UHWO_MASK (0x8000000U) +#define S50_ELS_KS5_KS5_UHWO_SHIFT (27U) +#define S50_ELS_KS5_KS5_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHWO_SHIFT)) & S50_ELS_KS5_KS5_UHWO_MASK) + +#define S50_ELS_KS5_KS5_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS5_KS5_UWRPOK_SHIFT (28U) +#define S50_ELS_KS5_KS5_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UWRPOK_SHIFT)) & S50_ELS_KS5_KS5_UWRPOK_MASK) + +#define S50_ELS_KS5_KS5_UDUK_MASK (0x20000000U) +#define S50_ELS_KS5_KS5_UDUK_SHIFT (29U) +#define S50_ELS_KS5_KS5_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UDUK_SHIFT)) & S50_ELS_KS5_KS5_UDUK_MASK) + +#define S50_ELS_KS5_KS5_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS5_KS5_UPPROT_SHIFT (30U) +#define S50_ELS_KS5_KS5_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UPPROT_SHIFT)) & S50_ELS_KS5_KS5_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS6 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS6_KS6_KSIZE_MASK (0x3U) +#define S50_ELS_KS6_KS6_KSIZE_SHIFT (0U) +/*! KS6_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS6_KS6_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KSIZE_SHIFT)) & S50_ELS_KS6_KS6_KSIZE_MASK) + +#define S50_ELS_KS6_KS6_KACT_MASK (0x20U) +#define S50_ELS_KS6_KS6_KACT_SHIFT (5U) +#define S50_ELS_KS6_KS6_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KACT_SHIFT)) & S50_ELS_KS6_KS6_KACT_MASK) + +#define S50_ELS_KS6_KS6_KBASE_MASK (0x40U) +#define S50_ELS_KS6_KS6_KBASE_SHIFT (6U) +#define S50_ELS_KS6_KS6_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KBASE_SHIFT)) & S50_ELS_KS6_KS6_KBASE_MASK) + +#define S50_ELS_KS6_KS6_FGP_MASK (0x80U) +#define S50_ELS_KS6_KS6_FGP_SHIFT (7U) +#define S50_ELS_KS6_KS6_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FGP_SHIFT)) & S50_ELS_KS6_KS6_FGP_MASK) + +#define S50_ELS_KS6_KS6_FRTN_MASK (0x100U) +#define S50_ELS_KS6_KS6_FRTN_SHIFT (8U) +#define S50_ELS_KS6_KS6_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FRTN_SHIFT)) & S50_ELS_KS6_KS6_FRTN_MASK) + +#define S50_ELS_KS6_KS6_FHWO_MASK (0x200U) +#define S50_ELS_KS6_KS6_FHWO_SHIFT (9U) +#define S50_ELS_KS6_KS6_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FHWO_SHIFT)) & S50_ELS_KS6_KS6_FHWO_MASK) + +#define S50_ELS_KS6_KS6_UKPUK_MASK (0x800U) +#define S50_ELS_KS6_KS6_UKPUK_SHIFT (11U) +#define S50_ELS_KS6_KS6_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKPUK_SHIFT)) & S50_ELS_KS6_KS6_UKPUK_MASK) + +#define S50_ELS_KS6_KS6_UTECDH_MASK (0x1000U) +#define S50_ELS_KS6_KS6_UTECDH_SHIFT (12U) +#define S50_ELS_KS6_KS6_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTECDH_SHIFT)) & S50_ELS_KS6_KS6_UTECDH_MASK) + +#define S50_ELS_KS6_KS6_UCMAC_MASK (0x2000U) +#define S50_ELS_KS6_KS6_UCMAC_SHIFT (13U) +#define S50_ELS_KS6_KS6_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCMAC_SHIFT)) & S50_ELS_KS6_KS6_UCMAC_MASK) + +#define S50_ELS_KS6_KS6_UKSK_MASK (0x4000U) +#define S50_ELS_KS6_KS6_UKSK_SHIFT (14U) +#define S50_ELS_KS6_KS6_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKSK_SHIFT)) & S50_ELS_KS6_KS6_UKSK_MASK) + +#define S50_ELS_KS6_KS6_URTF_MASK (0x8000U) +#define S50_ELS_KS6_KS6_URTF_SHIFT (15U) +#define S50_ELS_KS6_KS6_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_URTF_SHIFT)) & S50_ELS_KS6_KS6_URTF_MASK) + +#define S50_ELS_KS6_KS6_UCKDF_MASK (0x10000U) +#define S50_ELS_KS6_KS6_UCKDF_SHIFT (16U) +#define S50_ELS_KS6_KS6_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCKDF_SHIFT)) & S50_ELS_KS6_KS6_UCKDF_MASK) + +#define S50_ELS_KS6_KS6_UHKDF_MASK (0x20000U) +#define S50_ELS_KS6_KS6_UHKDF_SHIFT (17U) +#define S50_ELS_KS6_KS6_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHKDF_SHIFT)) & S50_ELS_KS6_KS6_UHKDF_MASK) + +#define S50_ELS_KS6_KS6_UECSG_MASK (0x40000U) +#define S50_ELS_KS6_KS6_UECSG_SHIFT (18U) +#define S50_ELS_KS6_KS6_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECSG_SHIFT)) & S50_ELS_KS6_KS6_UECSG_MASK) + +#define S50_ELS_KS6_KS6_UECDH_MASK (0x80000U) +#define S50_ELS_KS6_KS6_UECDH_SHIFT (19U) +#define S50_ELS_KS6_KS6_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECDH_SHIFT)) & S50_ELS_KS6_KS6_UECDH_MASK) + +#define S50_ELS_KS6_KS6_UAES_MASK (0x100000U) +#define S50_ELS_KS6_KS6_UAES_SHIFT (20U) +#define S50_ELS_KS6_KS6_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UAES_SHIFT)) & S50_ELS_KS6_KS6_UAES_MASK) + +#define S50_ELS_KS6_KS6_UHMAC_MASK (0x200000U) +#define S50_ELS_KS6_KS6_UHMAC_SHIFT (21U) +#define S50_ELS_KS6_KS6_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHMAC_SHIFT)) & S50_ELS_KS6_KS6_UHMAC_MASK) + +#define S50_ELS_KS6_KS6_UKWK_MASK (0x400000U) +#define S50_ELS_KS6_KS6_UKWK_SHIFT (22U) +#define S50_ELS_KS6_KS6_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKWK_SHIFT)) & S50_ELS_KS6_KS6_UKWK_MASK) + +#define S50_ELS_KS6_KS6_UKUOK_MASK (0x800000U) +#define S50_ELS_KS6_KS6_UKUOK_SHIFT (23U) +#define S50_ELS_KS6_KS6_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKUOK_SHIFT)) & S50_ELS_KS6_KS6_UKUOK_MASK) + +#define S50_ELS_KS6_KS6_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS6_KS6_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS6_KS6_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSPMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSPMS_MASK) + +#define S50_ELS_KS6_KS6_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS6_KS6_UTLSMS_SHIFT (25U) +#define S50_ELS_KS6_KS6_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSMS_MASK) + +#define S50_ELS_KS6_KS6_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS6_KS6_UKGSRC_SHIFT (26U) +#define S50_ELS_KS6_KS6_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKGSRC_SHIFT)) & S50_ELS_KS6_KS6_UKGSRC_MASK) + +#define S50_ELS_KS6_KS6_UHWO_MASK (0x8000000U) +#define S50_ELS_KS6_KS6_UHWO_SHIFT (27U) +#define S50_ELS_KS6_KS6_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHWO_SHIFT)) & S50_ELS_KS6_KS6_UHWO_MASK) + +#define S50_ELS_KS6_KS6_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS6_KS6_UWRPOK_SHIFT (28U) +#define S50_ELS_KS6_KS6_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UWRPOK_SHIFT)) & S50_ELS_KS6_KS6_UWRPOK_MASK) + +#define S50_ELS_KS6_KS6_UDUK_MASK (0x20000000U) +#define S50_ELS_KS6_KS6_UDUK_SHIFT (29U) +#define S50_ELS_KS6_KS6_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UDUK_SHIFT)) & S50_ELS_KS6_KS6_UDUK_MASK) + +#define S50_ELS_KS6_KS6_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS6_KS6_UPPROT_SHIFT (30U) +#define S50_ELS_KS6_KS6_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UPPROT_SHIFT)) & S50_ELS_KS6_KS6_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS7 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS7_KS7_KSIZE_MASK (0x3U) +#define S50_ELS_KS7_KS7_KSIZE_SHIFT (0U) +/*! KS7_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS7_KS7_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KSIZE_SHIFT)) & S50_ELS_KS7_KS7_KSIZE_MASK) + +#define S50_ELS_KS7_KS7_KACT_MASK (0x20U) +#define S50_ELS_KS7_KS7_KACT_SHIFT (5U) +#define S50_ELS_KS7_KS7_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KACT_SHIFT)) & S50_ELS_KS7_KS7_KACT_MASK) + +#define S50_ELS_KS7_KS7_KBASE_MASK (0x40U) +#define S50_ELS_KS7_KS7_KBASE_SHIFT (6U) +#define S50_ELS_KS7_KS7_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KBASE_SHIFT)) & S50_ELS_KS7_KS7_KBASE_MASK) + +#define S50_ELS_KS7_KS7_FGP_MASK (0x80U) +#define S50_ELS_KS7_KS7_FGP_SHIFT (7U) +#define S50_ELS_KS7_KS7_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FGP_SHIFT)) & S50_ELS_KS7_KS7_FGP_MASK) + +#define S50_ELS_KS7_KS7_FRTN_MASK (0x100U) +#define S50_ELS_KS7_KS7_FRTN_SHIFT (8U) +#define S50_ELS_KS7_KS7_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FRTN_SHIFT)) & S50_ELS_KS7_KS7_FRTN_MASK) + +#define S50_ELS_KS7_KS7_FHWO_MASK (0x200U) +#define S50_ELS_KS7_KS7_FHWO_SHIFT (9U) +#define S50_ELS_KS7_KS7_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FHWO_SHIFT)) & S50_ELS_KS7_KS7_FHWO_MASK) + +#define S50_ELS_KS7_KS7_UKPUK_MASK (0x800U) +#define S50_ELS_KS7_KS7_UKPUK_SHIFT (11U) +#define S50_ELS_KS7_KS7_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKPUK_SHIFT)) & S50_ELS_KS7_KS7_UKPUK_MASK) + +#define S50_ELS_KS7_KS7_UTECDH_MASK (0x1000U) +#define S50_ELS_KS7_KS7_UTECDH_SHIFT (12U) +#define S50_ELS_KS7_KS7_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTECDH_SHIFT)) & S50_ELS_KS7_KS7_UTECDH_MASK) + +#define S50_ELS_KS7_KS7_UCMAC_MASK (0x2000U) +#define S50_ELS_KS7_KS7_UCMAC_SHIFT (13U) +#define S50_ELS_KS7_KS7_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCMAC_SHIFT)) & S50_ELS_KS7_KS7_UCMAC_MASK) + +#define S50_ELS_KS7_KS7_UKSK_MASK (0x4000U) +#define S50_ELS_KS7_KS7_UKSK_SHIFT (14U) +#define S50_ELS_KS7_KS7_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKSK_SHIFT)) & S50_ELS_KS7_KS7_UKSK_MASK) + +#define S50_ELS_KS7_KS7_URTF_MASK (0x8000U) +#define S50_ELS_KS7_KS7_URTF_SHIFT (15U) +#define S50_ELS_KS7_KS7_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_URTF_SHIFT)) & S50_ELS_KS7_KS7_URTF_MASK) + +#define S50_ELS_KS7_KS7_UCKDF_MASK (0x10000U) +#define S50_ELS_KS7_KS7_UCKDF_SHIFT (16U) +#define S50_ELS_KS7_KS7_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCKDF_SHIFT)) & S50_ELS_KS7_KS7_UCKDF_MASK) + +#define S50_ELS_KS7_KS7_UHKDF_MASK (0x20000U) +#define S50_ELS_KS7_KS7_UHKDF_SHIFT (17U) +#define S50_ELS_KS7_KS7_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHKDF_SHIFT)) & S50_ELS_KS7_KS7_UHKDF_MASK) + +#define S50_ELS_KS7_KS7_UECSG_MASK (0x40000U) +#define S50_ELS_KS7_KS7_UECSG_SHIFT (18U) +#define S50_ELS_KS7_KS7_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECSG_SHIFT)) & S50_ELS_KS7_KS7_UECSG_MASK) + +#define S50_ELS_KS7_KS7_UECDH_MASK (0x80000U) +#define S50_ELS_KS7_KS7_UECDH_SHIFT (19U) +#define S50_ELS_KS7_KS7_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECDH_SHIFT)) & S50_ELS_KS7_KS7_UECDH_MASK) + +#define S50_ELS_KS7_KS7_UAES_MASK (0x100000U) +#define S50_ELS_KS7_KS7_UAES_SHIFT (20U) +#define S50_ELS_KS7_KS7_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UAES_SHIFT)) & S50_ELS_KS7_KS7_UAES_MASK) + +#define S50_ELS_KS7_KS7_UHMAC_MASK (0x200000U) +#define S50_ELS_KS7_KS7_UHMAC_SHIFT (21U) +#define S50_ELS_KS7_KS7_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHMAC_SHIFT)) & S50_ELS_KS7_KS7_UHMAC_MASK) + +#define S50_ELS_KS7_KS7_UKWK_MASK (0x400000U) +#define S50_ELS_KS7_KS7_UKWK_SHIFT (22U) +#define S50_ELS_KS7_KS7_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKWK_SHIFT)) & S50_ELS_KS7_KS7_UKWK_MASK) + +#define S50_ELS_KS7_KS7_UKUOK_MASK (0x800000U) +#define S50_ELS_KS7_KS7_UKUOK_SHIFT (23U) +#define S50_ELS_KS7_KS7_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKUOK_SHIFT)) & S50_ELS_KS7_KS7_UKUOK_MASK) + +#define S50_ELS_KS7_KS7_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS7_KS7_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS7_KS7_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSPMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSPMS_MASK) + +#define S50_ELS_KS7_KS7_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS7_KS7_UTLSMS_SHIFT (25U) +#define S50_ELS_KS7_KS7_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSMS_MASK) + +#define S50_ELS_KS7_KS7_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS7_KS7_UKGSRC_SHIFT (26U) +#define S50_ELS_KS7_KS7_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKGSRC_SHIFT)) & S50_ELS_KS7_KS7_UKGSRC_MASK) + +#define S50_ELS_KS7_KS7_UHWO_MASK (0x8000000U) +#define S50_ELS_KS7_KS7_UHWO_SHIFT (27U) +#define S50_ELS_KS7_KS7_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHWO_SHIFT)) & S50_ELS_KS7_KS7_UHWO_MASK) + +#define S50_ELS_KS7_KS7_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS7_KS7_UWRPOK_SHIFT (28U) +#define S50_ELS_KS7_KS7_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UWRPOK_SHIFT)) & S50_ELS_KS7_KS7_UWRPOK_MASK) + +#define S50_ELS_KS7_KS7_UDUK_MASK (0x20000000U) +#define S50_ELS_KS7_KS7_UDUK_SHIFT (29U) +#define S50_ELS_KS7_KS7_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UDUK_SHIFT)) & S50_ELS_KS7_KS7_UDUK_MASK) + +#define S50_ELS_KS7_KS7_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS7_KS7_UPPROT_SHIFT (30U) +#define S50_ELS_KS7_KS7_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UPPROT_SHIFT)) & S50_ELS_KS7_KS7_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS8 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS8_KS8_KSIZE_MASK (0x3U) +#define S50_ELS_KS8_KS8_KSIZE_SHIFT (0U) +/*! KS8_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS8_KS8_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KSIZE_SHIFT)) & S50_ELS_KS8_KS8_KSIZE_MASK) + +#define S50_ELS_KS8_KS8_KACT_MASK (0x20U) +#define S50_ELS_KS8_KS8_KACT_SHIFT (5U) +#define S50_ELS_KS8_KS8_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KACT_SHIFT)) & S50_ELS_KS8_KS8_KACT_MASK) + +#define S50_ELS_KS8_KS8_KBASE_MASK (0x40U) +#define S50_ELS_KS8_KS8_KBASE_SHIFT (6U) +#define S50_ELS_KS8_KS8_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KBASE_SHIFT)) & S50_ELS_KS8_KS8_KBASE_MASK) + +#define S50_ELS_KS8_KS8_FGP_MASK (0x80U) +#define S50_ELS_KS8_KS8_FGP_SHIFT (7U) +#define S50_ELS_KS8_KS8_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FGP_SHIFT)) & S50_ELS_KS8_KS8_FGP_MASK) + +#define S50_ELS_KS8_KS8_FRTN_MASK (0x100U) +#define S50_ELS_KS8_KS8_FRTN_SHIFT (8U) +#define S50_ELS_KS8_KS8_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FRTN_SHIFT)) & S50_ELS_KS8_KS8_FRTN_MASK) + +#define S50_ELS_KS8_KS8_FHWO_MASK (0x200U) +#define S50_ELS_KS8_KS8_FHWO_SHIFT (9U) +#define S50_ELS_KS8_KS8_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FHWO_SHIFT)) & S50_ELS_KS8_KS8_FHWO_MASK) + +#define S50_ELS_KS8_KS8_UKPUK_MASK (0x800U) +#define S50_ELS_KS8_KS8_UKPUK_SHIFT (11U) +#define S50_ELS_KS8_KS8_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKPUK_SHIFT)) & S50_ELS_KS8_KS8_UKPUK_MASK) + +#define S50_ELS_KS8_KS8_UTECDH_MASK (0x1000U) +#define S50_ELS_KS8_KS8_UTECDH_SHIFT (12U) +#define S50_ELS_KS8_KS8_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTECDH_SHIFT)) & S50_ELS_KS8_KS8_UTECDH_MASK) + +#define S50_ELS_KS8_KS8_UCMAC_MASK (0x2000U) +#define S50_ELS_KS8_KS8_UCMAC_SHIFT (13U) +#define S50_ELS_KS8_KS8_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCMAC_SHIFT)) & S50_ELS_KS8_KS8_UCMAC_MASK) + +#define S50_ELS_KS8_KS8_UKSK_MASK (0x4000U) +#define S50_ELS_KS8_KS8_UKSK_SHIFT (14U) +#define S50_ELS_KS8_KS8_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKSK_SHIFT)) & S50_ELS_KS8_KS8_UKSK_MASK) + +#define S50_ELS_KS8_KS8_URTF_MASK (0x8000U) +#define S50_ELS_KS8_KS8_URTF_SHIFT (15U) +#define S50_ELS_KS8_KS8_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_URTF_SHIFT)) & S50_ELS_KS8_KS8_URTF_MASK) + +#define S50_ELS_KS8_KS8_UCKDF_MASK (0x10000U) +#define S50_ELS_KS8_KS8_UCKDF_SHIFT (16U) +#define S50_ELS_KS8_KS8_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCKDF_SHIFT)) & S50_ELS_KS8_KS8_UCKDF_MASK) + +#define S50_ELS_KS8_KS8_UHKDF_MASK (0x20000U) +#define S50_ELS_KS8_KS8_UHKDF_SHIFT (17U) +#define S50_ELS_KS8_KS8_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHKDF_SHIFT)) & S50_ELS_KS8_KS8_UHKDF_MASK) + +#define S50_ELS_KS8_KS8_UECSG_MASK (0x40000U) +#define S50_ELS_KS8_KS8_UECSG_SHIFT (18U) +#define S50_ELS_KS8_KS8_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECSG_SHIFT)) & S50_ELS_KS8_KS8_UECSG_MASK) + +#define S50_ELS_KS8_KS8_UECDH_MASK (0x80000U) +#define S50_ELS_KS8_KS8_UECDH_SHIFT (19U) +#define S50_ELS_KS8_KS8_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECDH_SHIFT)) & S50_ELS_KS8_KS8_UECDH_MASK) + +#define S50_ELS_KS8_KS8_UAES_MASK (0x100000U) +#define S50_ELS_KS8_KS8_UAES_SHIFT (20U) +#define S50_ELS_KS8_KS8_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UAES_SHIFT)) & S50_ELS_KS8_KS8_UAES_MASK) + +#define S50_ELS_KS8_KS8_UHMAC_MASK (0x200000U) +#define S50_ELS_KS8_KS8_UHMAC_SHIFT (21U) +#define S50_ELS_KS8_KS8_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHMAC_SHIFT)) & S50_ELS_KS8_KS8_UHMAC_MASK) + +#define S50_ELS_KS8_KS8_UKWK_MASK (0x400000U) +#define S50_ELS_KS8_KS8_UKWK_SHIFT (22U) +#define S50_ELS_KS8_KS8_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKWK_SHIFT)) & S50_ELS_KS8_KS8_UKWK_MASK) + +#define S50_ELS_KS8_KS8_UKUOK_MASK (0x800000U) +#define S50_ELS_KS8_KS8_UKUOK_SHIFT (23U) +#define S50_ELS_KS8_KS8_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKUOK_SHIFT)) & S50_ELS_KS8_KS8_UKUOK_MASK) + +#define S50_ELS_KS8_KS8_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS8_KS8_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS8_KS8_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSPMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSPMS_MASK) + +#define S50_ELS_KS8_KS8_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS8_KS8_UTLSMS_SHIFT (25U) +#define S50_ELS_KS8_KS8_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSMS_MASK) + +#define S50_ELS_KS8_KS8_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS8_KS8_UKGSRC_SHIFT (26U) +#define S50_ELS_KS8_KS8_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKGSRC_SHIFT)) & S50_ELS_KS8_KS8_UKGSRC_MASK) + +#define S50_ELS_KS8_KS8_UHWO_MASK (0x8000000U) +#define S50_ELS_KS8_KS8_UHWO_SHIFT (27U) +#define S50_ELS_KS8_KS8_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHWO_SHIFT)) & S50_ELS_KS8_KS8_UHWO_MASK) + +#define S50_ELS_KS8_KS8_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS8_KS8_UWRPOK_SHIFT (28U) +#define S50_ELS_KS8_KS8_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UWRPOK_SHIFT)) & S50_ELS_KS8_KS8_UWRPOK_MASK) + +#define S50_ELS_KS8_KS8_UDUK_MASK (0x20000000U) +#define S50_ELS_KS8_KS8_UDUK_SHIFT (29U) +#define S50_ELS_KS8_KS8_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UDUK_SHIFT)) & S50_ELS_KS8_KS8_UDUK_MASK) + +#define S50_ELS_KS8_KS8_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS8_KS8_UPPROT_SHIFT (30U) +#define S50_ELS_KS8_KS8_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UPPROT_SHIFT)) & S50_ELS_KS8_KS8_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS9 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS9_KS9_KSIZE_MASK (0x3U) +#define S50_ELS_KS9_KS9_KSIZE_SHIFT (0U) +/*! KS9_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS9_KS9_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KSIZE_SHIFT)) & S50_ELS_KS9_KS9_KSIZE_MASK) + +#define S50_ELS_KS9_KS9_KACT_MASK (0x20U) +#define S50_ELS_KS9_KS9_KACT_SHIFT (5U) +#define S50_ELS_KS9_KS9_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KACT_SHIFT)) & S50_ELS_KS9_KS9_KACT_MASK) + +#define S50_ELS_KS9_KS9_KBASE_MASK (0x40U) +#define S50_ELS_KS9_KS9_KBASE_SHIFT (6U) +#define S50_ELS_KS9_KS9_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KBASE_SHIFT)) & S50_ELS_KS9_KS9_KBASE_MASK) + +#define S50_ELS_KS9_KS9_FGP_MASK (0x80U) +#define S50_ELS_KS9_KS9_FGP_SHIFT (7U) +#define S50_ELS_KS9_KS9_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FGP_SHIFT)) & S50_ELS_KS9_KS9_FGP_MASK) + +#define S50_ELS_KS9_KS9_FRTN_MASK (0x100U) +#define S50_ELS_KS9_KS9_FRTN_SHIFT (8U) +#define S50_ELS_KS9_KS9_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FRTN_SHIFT)) & S50_ELS_KS9_KS9_FRTN_MASK) + +#define S50_ELS_KS9_KS9_FHWO_MASK (0x200U) +#define S50_ELS_KS9_KS9_FHWO_SHIFT (9U) +#define S50_ELS_KS9_KS9_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FHWO_SHIFT)) & S50_ELS_KS9_KS9_FHWO_MASK) + +#define S50_ELS_KS9_KS9_UKPUK_MASK (0x800U) +#define S50_ELS_KS9_KS9_UKPUK_SHIFT (11U) +#define S50_ELS_KS9_KS9_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKPUK_SHIFT)) & S50_ELS_KS9_KS9_UKPUK_MASK) + +#define S50_ELS_KS9_KS9_UTECDH_MASK (0x1000U) +#define S50_ELS_KS9_KS9_UTECDH_SHIFT (12U) +#define S50_ELS_KS9_KS9_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTECDH_SHIFT)) & S50_ELS_KS9_KS9_UTECDH_MASK) + +#define S50_ELS_KS9_KS9_UCMAC_MASK (0x2000U) +#define S50_ELS_KS9_KS9_UCMAC_SHIFT (13U) +#define S50_ELS_KS9_KS9_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCMAC_SHIFT)) & S50_ELS_KS9_KS9_UCMAC_MASK) + +#define S50_ELS_KS9_KS9_UKSK_MASK (0x4000U) +#define S50_ELS_KS9_KS9_UKSK_SHIFT (14U) +#define S50_ELS_KS9_KS9_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKSK_SHIFT)) & S50_ELS_KS9_KS9_UKSK_MASK) + +#define S50_ELS_KS9_KS9_URTF_MASK (0x8000U) +#define S50_ELS_KS9_KS9_URTF_SHIFT (15U) +#define S50_ELS_KS9_KS9_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_URTF_SHIFT)) & S50_ELS_KS9_KS9_URTF_MASK) + +#define S50_ELS_KS9_KS9_UCKDF_MASK (0x10000U) +#define S50_ELS_KS9_KS9_UCKDF_SHIFT (16U) +#define S50_ELS_KS9_KS9_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCKDF_SHIFT)) & S50_ELS_KS9_KS9_UCKDF_MASK) + +#define S50_ELS_KS9_KS9_UHKDF_MASK (0x20000U) +#define S50_ELS_KS9_KS9_UHKDF_SHIFT (17U) +#define S50_ELS_KS9_KS9_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHKDF_SHIFT)) & S50_ELS_KS9_KS9_UHKDF_MASK) + +#define S50_ELS_KS9_KS9_UECSG_MASK (0x40000U) +#define S50_ELS_KS9_KS9_UECSG_SHIFT (18U) +#define S50_ELS_KS9_KS9_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECSG_SHIFT)) & S50_ELS_KS9_KS9_UECSG_MASK) + +#define S50_ELS_KS9_KS9_UECDH_MASK (0x80000U) +#define S50_ELS_KS9_KS9_UECDH_SHIFT (19U) +#define S50_ELS_KS9_KS9_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECDH_SHIFT)) & S50_ELS_KS9_KS9_UECDH_MASK) + +#define S50_ELS_KS9_KS9_UAES_MASK (0x100000U) +#define S50_ELS_KS9_KS9_UAES_SHIFT (20U) +#define S50_ELS_KS9_KS9_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UAES_SHIFT)) & S50_ELS_KS9_KS9_UAES_MASK) + +#define S50_ELS_KS9_KS9_UHMAC_MASK (0x200000U) +#define S50_ELS_KS9_KS9_UHMAC_SHIFT (21U) +#define S50_ELS_KS9_KS9_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHMAC_SHIFT)) & S50_ELS_KS9_KS9_UHMAC_MASK) + +#define S50_ELS_KS9_KS9_UKWK_MASK (0x400000U) +#define S50_ELS_KS9_KS9_UKWK_SHIFT (22U) +#define S50_ELS_KS9_KS9_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKWK_SHIFT)) & S50_ELS_KS9_KS9_UKWK_MASK) + +#define S50_ELS_KS9_KS9_UKUOK_MASK (0x800000U) +#define S50_ELS_KS9_KS9_UKUOK_SHIFT (23U) +#define S50_ELS_KS9_KS9_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKUOK_SHIFT)) & S50_ELS_KS9_KS9_UKUOK_MASK) + +#define S50_ELS_KS9_KS9_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS9_KS9_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS9_KS9_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSPMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSPMS_MASK) + +#define S50_ELS_KS9_KS9_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS9_KS9_UTLSMS_SHIFT (25U) +#define S50_ELS_KS9_KS9_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSMS_MASK) + +#define S50_ELS_KS9_KS9_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS9_KS9_UKGSRC_SHIFT (26U) +#define S50_ELS_KS9_KS9_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKGSRC_SHIFT)) & S50_ELS_KS9_KS9_UKGSRC_MASK) + +#define S50_ELS_KS9_KS9_UHWO_MASK (0x8000000U) +#define S50_ELS_KS9_KS9_UHWO_SHIFT (27U) +#define S50_ELS_KS9_KS9_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHWO_SHIFT)) & S50_ELS_KS9_KS9_UHWO_MASK) + +#define S50_ELS_KS9_KS9_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS9_KS9_UWRPOK_SHIFT (28U) +#define S50_ELS_KS9_KS9_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UWRPOK_SHIFT)) & S50_ELS_KS9_KS9_UWRPOK_MASK) + +#define S50_ELS_KS9_KS9_UDUK_MASK (0x20000000U) +#define S50_ELS_KS9_KS9_UDUK_SHIFT (29U) +#define S50_ELS_KS9_KS9_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UDUK_SHIFT)) & S50_ELS_KS9_KS9_UDUK_MASK) + +#define S50_ELS_KS9_KS9_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS9_KS9_UPPROT_SHIFT (30U) +#define S50_ELS_KS9_KS9_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UPPROT_SHIFT)) & S50_ELS_KS9_KS9_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS10 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS10_KS10_KSIZE_MASK (0x3U) +#define S50_ELS_KS10_KS10_KSIZE_SHIFT (0U) +/*! KS10_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS10_KS10_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KSIZE_SHIFT)) & S50_ELS_KS10_KS10_KSIZE_MASK) + +#define S50_ELS_KS10_KS10_KACT_MASK (0x20U) +#define S50_ELS_KS10_KS10_KACT_SHIFT (5U) +#define S50_ELS_KS10_KS10_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KACT_SHIFT)) & S50_ELS_KS10_KS10_KACT_MASK) + +#define S50_ELS_KS10_KS10_KBASE_MASK (0x40U) +#define S50_ELS_KS10_KS10_KBASE_SHIFT (6U) +#define S50_ELS_KS10_KS10_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KBASE_SHIFT)) & S50_ELS_KS10_KS10_KBASE_MASK) + +#define S50_ELS_KS10_KS10_FGP_MASK (0x80U) +#define S50_ELS_KS10_KS10_FGP_SHIFT (7U) +#define S50_ELS_KS10_KS10_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FGP_SHIFT)) & S50_ELS_KS10_KS10_FGP_MASK) + +#define S50_ELS_KS10_KS10_FRTN_MASK (0x100U) +#define S50_ELS_KS10_KS10_FRTN_SHIFT (8U) +#define S50_ELS_KS10_KS10_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FRTN_SHIFT)) & S50_ELS_KS10_KS10_FRTN_MASK) + +#define S50_ELS_KS10_KS10_FHWO_MASK (0x200U) +#define S50_ELS_KS10_KS10_FHWO_SHIFT (9U) +#define S50_ELS_KS10_KS10_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FHWO_SHIFT)) & S50_ELS_KS10_KS10_FHWO_MASK) + +#define S50_ELS_KS10_KS10_UKPUK_MASK (0x800U) +#define S50_ELS_KS10_KS10_UKPUK_SHIFT (11U) +#define S50_ELS_KS10_KS10_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKPUK_SHIFT)) & S50_ELS_KS10_KS10_UKPUK_MASK) + +#define S50_ELS_KS10_KS10_UTECDH_MASK (0x1000U) +#define S50_ELS_KS10_KS10_UTECDH_SHIFT (12U) +#define S50_ELS_KS10_KS10_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTECDH_SHIFT)) & S50_ELS_KS10_KS10_UTECDH_MASK) + +#define S50_ELS_KS10_KS10_UCMAC_MASK (0x2000U) +#define S50_ELS_KS10_KS10_UCMAC_SHIFT (13U) +#define S50_ELS_KS10_KS10_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCMAC_SHIFT)) & S50_ELS_KS10_KS10_UCMAC_MASK) + +#define S50_ELS_KS10_KS10_UKSK_MASK (0x4000U) +#define S50_ELS_KS10_KS10_UKSK_SHIFT (14U) +#define S50_ELS_KS10_KS10_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKSK_SHIFT)) & S50_ELS_KS10_KS10_UKSK_MASK) + +#define S50_ELS_KS10_KS10_URTF_MASK (0x8000U) +#define S50_ELS_KS10_KS10_URTF_SHIFT (15U) +#define S50_ELS_KS10_KS10_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_URTF_SHIFT)) & S50_ELS_KS10_KS10_URTF_MASK) + +#define S50_ELS_KS10_KS10_UCKDF_MASK (0x10000U) +#define S50_ELS_KS10_KS10_UCKDF_SHIFT (16U) +#define S50_ELS_KS10_KS10_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCKDF_SHIFT)) & S50_ELS_KS10_KS10_UCKDF_MASK) + +#define S50_ELS_KS10_KS10_UHKDF_MASK (0x20000U) +#define S50_ELS_KS10_KS10_UHKDF_SHIFT (17U) +#define S50_ELS_KS10_KS10_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHKDF_SHIFT)) & S50_ELS_KS10_KS10_UHKDF_MASK) + +#define S50_ELS_KS10_KS10_UECSG_MASK (0x40000U) +#define S50_ELS_KS10_KS10_UECSG_SHIFT (18U) +#define S50_ELS_KS10_KS10_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECSG_SHIFT)) & S50_ELS_KS10_KS10_UECSG_MASK) + +#define S50_ELS_KS10_KS10_UECDH_MASK (0x80000U) +#define S50_ELS_KS10_KS10_UECDH_SHIFT (19U) +#define S50_ELS_KS10_KS10_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECDH_SHIFT)) & S50_ELS_KS10_KS10_UECDH_MASK) + +#define S50_ELS_KS10_KS10_UAES_MASK (0x100000U) +#define S50_ELS_KS10_KS10_UAES_SHIFT (20U) +#define S50_ELS_KS10_KS10_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UAES_SHIFT)) & S50_ELS_KS10_KS10_UAES_MASK) + +#define S50_ELS_KS10_KS10_UHMAC_MASK (0x200000U) +#define S50_ELS_KS10_KS10_UHMAC_SHIFT (21U) +#define S50_ELS_KS10_KS10_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHMAC_SHIFT)) & S50_ELS_KS10_KS10_UHMAC_MASK) + +#define S50_ELS_KS10_KS10_UKWK_MASK (0x400000U) +#define S50_ELS_KS10_KS10_UKWK_SHIFT (22U) +#define S50_ELS_KS10_KS10_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKWK_SHIFT)) & S50_ELS_KS10_KS10_UKWK_MASK) + +#define S50_ELS_KS10_KS10_UKUOK_MASK (0x800000U) +#define S50_ELS_KS10_KS10_UKUOK_SHIFT (23U) +#define S50_ELS_KS10_KS10_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKUOK_SHIFT)) & S50_ELS_KS10_KS10_UKUOK_MASK) + +#define S50_ELS_KS10_KS10_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS10_KS10_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS10_KS10_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSPMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSPMS_MASK) + +#define S50_ELS_KS10_KS10_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS10_KS10_UTLSMS_SHIFT (25U) +#define S50_ELS_KS10_KS10_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSMS_MASK) + +#define S50_ELS_KS10_KS10_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS10_KS10_UKGSRC_SHIFT (26U) +#define S50_ELS_KS10_KS10_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKGSRC_SHIFT)) & S50_ELS_KS10_KS10_UKGSRC_MASK) + +#define S50_ELS_KS10_KS10_UHWO_MASK (0x8000000U) +#define S50_ELS_KS10_KS10_UHWO_SHIFT (27U) +#define S50_ELS_KS10_KS10_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHWO_SHIFT)) & S50_ELS_KS10_KS10_UHWO_MASK) + +#define S50_ELS_KS10_KS10_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS10_KS10_UWRPOK_SHIFT (28U) +#define S50_ELS_KS10_KS10_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UWRPOK_SHIFT)) & S50_ELS_KS10_KS10_UWRPOK_MASK) + +#define S50_ELS_KS10_KS10_UDUK_MASK (0x20000000U) +#define S50_ELS_KS10_KS10_UDUK_SHIFT (29U) +#define S50_ELS_KS10_KS10_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UDUK_SHIFT)) & S50_ELS_KS10_KS10_UDUK_MASK) + +#define S50_ELS_KS10_KS10_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS10_KS10_UPPROT_SHIFT (30U) +#define S50_ELS_KS10_KS10_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UPPROT_SHIFT)) & S50_ELS_KS10_KS10_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS11 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS11_KS11_KSIZE_MASK (0x3U) +#define S50_ELS_KS11_KS11_KSIZE_SHIFT (0U) +/*! KS11_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS11_KS11_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KSIZE_SHIFT)) & S50_ELS_KS11_KS11_KSIZE_MASK) + +#define S50_ELS_KS11_KS11_KACT_MASK (0x20U) +#define S50_ELS_KS11_KS11_KACT_SHIFT (5U) +#define S50_ELS_KS11_KS11_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KACT_SHIFT)) & S50_ELS_KS11_KS11_KACT_MASK) + +#define S50_ELS_KS11_KS11_KBASE_MASK (0x40U) +#define S50_ELS_KS11_KS11_KBASE_SHIFT (6U) +#define S50_ELS_KS11_KS11_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KBASE_SHIFT)) & S50_ELS_KS11_KS11_KBASE_MASK) + +#define S50_ELS_KS11_KS11_FGP_MASK (0x80U) +#define S50_ELS_KS11_KS11_FGP_SHIFT (7U) +#define S50_ELS_KS11_KS11_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FGP_SHIFT)) & S50_ELS_KS11_KS11_FGP_MASK) + +#define S50_ELS_KS11_KS11_FRTN_MASK (0x100U) +#define S50_ELS_KS11_KS11_FRTN_SHIFT (8U) +#define S50_ELS_KS11_KS11_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FRTN_SHIFT)) & S50_ELS_KS11_KS11_FRTN_MASK) + +#define S50_ELS_KS11_KS11_FHWO_MASK (0x200U) +#define S50_ELS_KS11_KS11_FHWO_SHIFT (9U) +#define S50_ELS_KS11_KS11_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FHWO_SHIFT)) & S50_ELS_KS11_KS11_FHWO_MASK) + +#define S50_ELS_KS11_KS11_UKPUK_MASK (0x800U) +#define S50_ELS_KS11_KS11_UKPUK_SHIFT (11U) +#define S50_ELS_KS11_KS11_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKPUK_SHIFT)) & S50_ELS_KS11_KS11_UKPUK_MASK) + +#define S50_ELS_KS11_KS11_UTECDH_MASK (0x1000U) +#define S50_ELS_KS11_KS11_UTECDH_SHIFT (12U) +#define S50_ELS_KS11_KS11_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTECDH_SHIFT)) & S50_ELS_KS11_KS11_UTECDH_MASK) + +#define S50_ELS_KS11_KS11_UCMAC_MASK (0x2000U) +#define S50_ELS_KS11_KS11_UCMAC_SHIFT (13U) +#define S50_ELS_KS11_KS11_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCMAC_SHIFT)) & S50_ELS_KS11_KS11_UCMAC_MASK) + +#define S50_ELS_KS11_KS11_UKSK_MASK (0x4000U) +#define S50_ELS_KS11_KS11_UKSK_SHIFT (14U) +#define S50_ELS_KS11_KS11_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKSK_SHIFT)) & S50_ELS_KS11_KS11_UKSK_MASK) + +#define S50_ELS_KS11_KS11_URTF_MASK (0x8000U) +#define S50_ELS_KS11_KS11_URTF_SHIFT (15U) +#define S50_ELS_KS11_KS11_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_URTF_SHIFT)) & S50_ELS_KS11_KS11_URTF_MASK) + +#define S50_ELS_KS11_KS11_UCKDF_MASK (0x10000U) +#define S50_ELS_KS11_KS11_UCKDF_SHIFT (16U) +#define S50_ELS_KS11_KS11_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCKDF_SHIFT)) & S50_ELS_KS11_KS11_UCKDF_MASK) + +#define S50_ELS_KS11_KS11_UHKDF_MASK (0x20000U) +#define S50_ELS_KS11_KS11_UHKDF_SHIFT (17U) +#define S50_ELS_KS11_KS11_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHKDF_SHIFT)) & S50_ELS_KS11_KS11_UHKDF_MASK) + +#define S50_ELS_KS11_KS11_UECSG_MASK (0x40000U) +#define S50_ELS_KS11_KS11_UECSG_SHIFT (18U) +#define S50_ELS_KS11_KS11_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECSG_SHIFT)) & S50_ELS_KS11_KS11_UECSG_MASK) + +#define S50_ELS_KS11_KS11_UECDH_MASK (0x80000U) +#define S50_ELS_KS11_KS11_UECDH_SHIFT (19U) +#define S50_ELS_KS11_KS11_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECDH_SHIFT)) & S50_ELS_KS11_KS11_UECDH_MASK) + +#define S50_ELS_KS11_KS11_UAES_MASK (0x100000U) +#define S50_ELS_KS11_KS11_UAES_SHIFT (20U) +#define S50_ELS_KS11_KS11_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UAES_SHIFT)) & S50_ELS_KS11_KS11_UAES_MASK) + +#define S50_ELS_KS11_KS11_UHMAC_MASK (0x200000U) +#define S50_ELS_KS11_KS11_UHMAC_SHIFT (21U) +#define S50_ELS_KS11_KS11_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHMAC_SHIFT)) & S50_ELS_KS11_KS11_UHMAC_MASK) + +#define S50_ELS_KS11_KS11_UKWK_MASK (0x400000U) +#define S50_ELS_KS11_KS11_UKWK_SHIFT (22U) +#define S50_ELS_KS11_KS11_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKWK_SHIFT)) & S50_ELS_KS11_KS11_UKWK_MASK) + +#define S50_ELS_KS11_KS11_UKUOK_MASK (0x800000U) +#define S50_ELS_KS11_KS11_UKUOK_SHIFT (23U) +#define S50_ELS_KS11_KS11_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKUOK_SHIFT)) & S50_ELS_KS11_KS11_UKUOK_MASK) + +#define S50_ELS_KS11_KS11_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS11_KS11_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS11_KS11_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSPMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSPMS_MASK) + +#define S50_ELS_KS11_KS11_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS11_KS11_UTLSMS_SHIFT (25U) +#define S50_ELS_KS11_KS11_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSMS_MASK) + +#define S50_ELS_KS11_KS11_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS11_KS11_UKGSRC_SHIFT (26U) +#define S50_ELS_KS11_KS11_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKGSRC_SHIFT)) & S50_ELS_KS11_KS11_UKGSRC_MASK) + +#define S50_ELS_KS11_KS11_UHWO_MASK (0x8000000U) +#define S50_ELS_KS11_KS11_UHWO_SHIFT (27U) +#define S50_ELS_KS11_KS11_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHWO_SHIFT)) & S50_ELS_KS11_KS11_UHWO_MASK) + +#define S50_ELS_KS11_KS11_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS11_KS11_UWRPOK_SHIFT (28U) +#define S50_ELS_KS11_KS11_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UWRPOK_SHIFT)) & S50_ELS_KS11_KS11_UWRPOK_MASK) + +#define S50_ELS_KS11_KS11_UDUK_MASK (0x20000000U) +#define S50_ELS_KS11_KS11_UDUK_SHIFT (29U) +#define S50_ELS_KS11_KS11_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UDUK_SHIFT)) & S50_ELS_KS11_KS11_UDUK_MASK) + +#define S50_ELS_KS11_KS11_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS11_KS11_UPPROT_SHIFT (30U) +#define S50_ELS_KS11_KS11_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UPPROT_SHIFT)) & S50_ELS_KS11_KS11_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS12 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS12_KS12_KSIZE_MASK (0x3U) +#define S50_ELS_KS12_KS12_KSIZE_SHIFT (0U) +/*! KS12_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS12_KS12_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KSIZE_SHIFT)) & S50_ELS_KS12_KS12_KSIZE_MASK) + +#define S50_ELS_KS12_KS12_KACT_MASK (0x20U) +#define S50_ELS_KS12_KS12_KACT_SHIFT (5U) +#define S50_ELS_KS12_KS12_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KACT_SHIFT)) & S50_ELS_KS12_KS12_KACT_MASK) + +#define S50_ELS_KS12_KS12_KBASE_MASK (0x40U) +#define S50_ELS_KS12_KS12_KBASE_SHIFT (6U) +#define S50_ELS_KS12_KS12_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KBASE_SHIFT)) & S50_ELS_KS12_KS12_KBASE_MASK) + +#define S50_ELS_KS12_KS12_FGP_MASK (0x80U) +#define S50_ELS_KS12_KS12_FGP_SHIFT (7U) +#define S50_ELS_KS12_KS12_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FGP_SHIFT)) & S50_ELS_KS12_KS12_FGP_MASK) + +#define S50_ELS_KS12_KS12_FRTN_MASK (0x100U) +#define S50_ELS_KS12_KS12_FRTN_SHIFT (8U) +#define S50_ELS_KS12_KS12_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FRTN_SHIFT)) & S50_ELS_KS12_KS12_FRTN_MASK) + +#define S50_ELS_KS12_KS12_FHWO_MASK (0x200U) +#define S50_ELS_KS12_KS12_FHWO_SHIFT (9U) +#define S50_ELS_KS12_KS12_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FHWO_SHIFT)) & S50_ELS_KS12_KS12_FHWO_MASK) + +#define S50_ELS_KS12_KS12_UKPUK_MASK (0x800U) +#define S50_ELS_KS12_KS12_UKPUK_SHIFT (11U) +#define S50_ELS_KS12_KS12_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKPUK_SHIFT)) & S50_ELS_KS12_KS12_UKPUK_MASK) + +#define S50_ELS_KS12_KS12_UTECDH_MASK (0x1000U) +#define S50_ELS_KS12_KS12_UTECDH_SHIFT (12U) +#define S50_ELS_KS12_KS12_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTECDH_SHIFT)) & S50_ELS_KS12_KS12_UTECDH_MASK) + +#define S50_ELS_KS12_KS12_UCMAC_MASK (0x2000U) +#define S50_ELS_KS12_KS12_UCMAC_SHIFT (13U) +#define S50_ELS_KS12_KS12_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCMAC_SHIFT)) & S50_ELS_KS12_KS12_UCMAC_MASK) + +#define S50_ELS_KS12_KS12_UKSK_MASK (0x4000U) +#define S50_ELS_KS12_KS12_UKSK_SHIFT (14U) +#define S50_ELS_KS12_KS12_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKSK_SHIFT)) & S50_ELS_KS12_KS12_UKSK_MASK) + +#define S50_ELS_KS12_KS12_URTF_MASK (0x8000U) +#define S50_ELS_KS12_KS12_URTF_SHIFT (15U) +#define S50_ELS_KS12_KS12_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_URTF_SHIFT)) & S50_ELS_KS12_KS12_URTF_MASK) + +#define S50_ELS_KS12_KS12_UCKDF_MASK (0x10000U) +#define S50_ELS_KS12_KS12_UCKDF_SHIFT (16U) +#define S50_ELS_KS12_KS12_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCKDF_SHIFT)) & S50_ELS_KS12_KS12_UCKDF_MASK) + +#define S50_ELS_KS12_KS12_UHKDF_MASK (0x20000U) +#define S50_ELS_KS12_KS12_UHKDF_SHIFT (17U) +#define S50_ELS_KS12_KS12_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHKDF_SHIFT)) & S50_ELS_KS12_KS12_UHKDF_MASK) + +#define S50_ELS_KS12_KS12_UECSG_MASK (0x40000U) +#define S50_ELS_KS12_KS12_UECSG_SHIFT (18U) +#define S50_ELS_KS12_KS12_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECSG_SHIFT)) & S50_ELS_KS12_KS12_UECSG_MASK) + +#define S50_ELS_KS12_KS12_UECDH_MASK (0x80000U) +#define S50_ELS_KS12_KS12_UECDH_SHIFT (19U) +#define S50_ELS_KS12_KS12_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECDH_SHIFT)) & S50_ELS_KS12_KS12_UECDH_MASK) + +#define S50_ELS_KS12_KS12_UAES_MASK (0x100000U) +#define S50_ELS_KS12_KS12_UAES_SHIFT (20U) +#define S50_ELS_KS12_KS12_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UAES_SHIFT)) & S50_ELS_KS12_KS12_UAES_MASK) + +#define S50_ELS_KS12_KS12_UHMAC_MASK (0x200000U) +#define S50_ELS_KS12_KS12_UHMAC_SHIFT (21U) +#define S50_ELS_KS12_KS12_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHMAC_SHIFT)) & S50_ELS_KS12_KS12_UHMAC_MASK) + +#define S50_ELS_KS12_KS12_UKWK_MASK (0x400000U) +#define S50_ELS_KS12_KS12_UKWK_SHIFT (22U) +#define S50_ELS_KS12_KS12_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKWK_SHIFT)) & S50_ELS_KS12_KS12_UKWK_MASK) + +#define S50_ELS_KS12_KS12_UKUOK_MASK (0x800000U) +#define S50_ELS_KS12_KS12_UKUOK_SHIFT (23U) +#define S50_ELS_KS12_KS12_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKUOK_SHIFT)) & S50_ELS_KS12_KS12_UKUOK_MASK) + +#define S50_ELS_KS12_KS12_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS12_KS12_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS12_KS12_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSPMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSPMS_MASK) + +#define S50_ELS_KS12_KS12_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS12_KS12_UTLSMS_SHIFT (25U) +#define S50_ELS_KS12_KS12_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSMS_MASK) + +#define S50_ELS_KS12_KS12_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS12_KS12_UKGSRC_SHIFT (26U) +#define S50_ELS_KS12_KS12_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKGSRC_SHIFT)) & S50_ELS_KS12_KS12_UKGSRC_MASK) + +#define S50_ELS_KS12_KS12_UHWO_MASK (0x8000000U) +#define S50_ELS_KS12_KS12_UHWO_SHIFT (27U) +#define S50_ELS_KS12_KS12_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHWO_SHIFT)) & S50_ELS_KS12_KS12_UHWO_MASK) + +#define S50_ELS_KS12_KS12_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS12_KS12_UWRPOK_SHIFT (28U) +#define S50_ELS_KS12_KS12_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UWRPOK_SHIFT)) & S50_ELS_KS12_KS12_UWRPOK_MASK) + +#define S50_ELS_KS12_KS12_UDUK_MASK (0x20000000U) +#define S50_ELS_KS12_KS12_UDUK_SHIFT (29U) +#define S50_ELS_KS12_KS12_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UDUK_SHIFT)) & S50_ELS_KS12_KS12_UDUK_MASK) + +#define S50_ELS_KS12_KS12_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS12_KS12_UPPROT_SHIFT (30U) +#define S50_ELS_KS12_KS12_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UPPROT_SHIFT)) & S50_ELS_KS12_KS12_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS13 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS13_KS13_KSIZE_MASK (0x3U) +#define S50_ELS_KS13_KS13_KSIZE_SHIFT (0U) +/*! KS13_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS13_KS13_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KSIZE_SHIFT)) & S50_ELS_KS13_KS13_KSIZE_MASK) + +#define S50_ELS_KS13_KS13_KACT_MASK (0x20U) +#define S50_ELS_KS13_KS13_KACT_SHIFT (5U) +#define S50_ELS_KS13_KS13_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KACT_SHIFT)) & S50_ELS_KS13_KS13_KACT_MASK) + +#define S50_ELS_KS13_KS13_KBASE_MASK (0x40U) +#define S50_ELS_KS13_KS13_KBASE_SHIFT (6U) +#define S50_ELS_KS13_KS13_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KBASE_SHIFT)) & S50_ELS_KS13_KS13_KBASE_MASK) + +#define S50_ELS_KS13_KS13_FGP_MASK (0x80U) +#define S50_ELS_KS13_KS13_FGP_SHIFT (7U) +#define S50_ELS_KS13_KS13_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FGP_SHIFT)) & S50_ELS_KS13_KS13_FGP_MASK) + +#define S50_ELS_KS13_KS13_FRTN_MASK (0x100U) +#define S50_ELS_KS13_KS13_FRTN_SHIFT (8U) +#define S50_ELS_KS13_KS13_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FRTN_SHIFT)) & S50_ELS_KS13_KS13_FRTN_MASK) + +#define S50_ELS_KS13_KS13_FHWO_MASK (0x200U) +#define S50_ELS_KS13_KS13_FHWO_SHIFT (9U) +#define S50_ELS_KS13_KS13_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FHWO_SHIFT)) & S50_ELS_KS13_KS13_FHWO_MASK) + +#define S50_ELS_KS13_KS13_UKPUK_MASK (0x800U) +#define S50_ELS_KS13_KS13_UKPUK_SHIFT (11U) +#define S50_ELS_KS13_KS13_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKPUK_SHIFT)) & S50_ELS_KS13_KS13_UKPUK_MASK) + +#define S50_ELS_KS13_KS13_UTECDH_MASK (0x1000U) +#define S50_ELS_KS13_KS13_UTECDH_SHIFT (12U) +#define S50_ELS_KS13_KS13_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTECDH_SHIFT)) & S50_ELS_KS13_KS13_UTECDH_MASK) + +#define S50_ELS_KS13_KS13_UCMAC_MASK (0x2000U) +#define S50_ELS_KS13_KS13_UCMAC_SHIFT (13U) +#define S50_ELS_KS13_KS13_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCMAC_SHIFT)) & S50_ELS_KS13_KS13_UCMAC_MASK) + +#define S50_ELS_KS13_KS13_UKSK_MASK (0x4000U) +#define S50_ELS_KS13_KS13_UKSK_SHIFT (14U) +#define S50_ELS_KS13_KS13_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKSK_SHIFT)) & S50_ELS_KS13_KS13_UKSK_MASK) + +#define S50_ELS_KS13_KS13_URTF_MASK (0x8000U) +#define S50_ELS_KS13_KS13_URTF_SHIFT (15U) +#define S50_ELS_KS13_KS13_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_URTF_SHIFT)) & S50_ELS_KS13_KS13_URTF_MASK) + +#define S50_ELS_KS13_KS13_UCKDF_MASK (0x10000U) +#define S50_ELS_KS13_KS13_UCKDF_SHIFT (16U) +#define S50_ELS_KS13_KS13_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCKDF_SHIFT)) & S50_ELS_KS13_KS13_UCKDF_MASK) + +#define S50_ELS_KS13_KS13_UHKDF_MASK (0x20000U) +#define S50_ELS_KS13_KS13_UHKDF_SHIFT (17U) +#define S50_ELS_KS13_KS13_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHKDF_SHIFT)) & S50_ELS_KS13_KS13_UHKDF_MASK) + +#define S50_ELS_KS13_KS13_UECSG_MASK (0x40000U) +#define S50_ELS_KS13_KS13_UECSG_SHIFT (18U) +#define S50_ELS_KS13_KS13_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECSG_SHIFT)) & S50_ELS_KS13_KS13_UECSG_MASK) + +#define S50_ELS_KS13_KS13_UECDH_MASK (0x80000U) +#define S50_ELS_KS13_KS13_UECDH_SHIFT (19U) +#define S50_ELS_KS13_KS13_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECDH_SHIFT)) & S50_ELS_KS13_KS13_UECDH_MASK) + +#define S50_ELS_KS13_KS13_UAES_MASK (0x100000U) +#define S50_ELS_KS13_KS13_UAES_SHIFT (20U) +#define S50_ELS_KS13_KS13_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UAES_SHIFT)) & S50_ELS_KS13_KS13_UAES_MASK) + +#define S50_ELS_KS13_KS13_UHMAC_MASK (0x200000U) +#define S50_ELS_KS13_KS13_UHMAC_SHIFT (21U) +#define S50_ELS_KS13_KS13_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHMAC_SHIFT)) & S50_ELS_KS13_KS13_UHMAC_MASK) + +#define S50_ELS_KS13_KS13_UKWK_MASK (0x400000U) +#define S50_ELS_KS13_KS13_UKWK_SHIFT (22U) +#define S50_ELS_KS13_KS13_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKWK_SHIFT)) & S50_ELS_KS13_KS13_UKWK_MASK) + +#define S50_ELS_KS13_KS13_UKUOK_MASK (0x800000U) +#define S50_ELS_KS13_KS13_UKUOK_SHIFT (23U) +#define S50_ELS_KS13_KS13_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKUOK_SHIFT)) & S50_ELS_KS13_KS13_UKUOK_MASK) + +#define S50_ELS_KS13_KS13_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS13_KS13_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS13_KS13_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSPMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSPMS_MASK) + +#define S50_ELS_KS13_KS13_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS13_KS13_UTLSMS_SHIFT (25U) +#define S50_ELS_KS13_KS13_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSMS_MASK) + +#define S50_ELS_KS13_KS13_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS13_KS13_UKGSRC_SHIFT (26U) +#define S50_ELS_KS13_KS13_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKGSRC_SHIFT)) & S50_ELS_KS13_KS13_UKGSRC_MASK) + +#define S50_ELS_KS13_KS13_UHWO_MASK (0x8000000U) +#define S50_ELS_KS13_KS13_UHWO_SHIFT (27U) +#define S50_ELS_KS13_KS13_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHWO_SHIFT)) & S50_ELS_KS13_KS13_UHWO_MASK) + +#define S50_ELS_KS13_KS13_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS13_KS13_UWRPOK_SHIFT (28U) +#define S50_ELS_KS13_KS13_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UWRPOK_SHIFT)) & S50_ELS_KS13_KS13_UWRPOK_MASK) + +#define S50_ELS_KS13_KS13_UDUK_MASK (0x20000000U) +#define S50_ELS_KS13_KS13_UDUK_SHIFT (29U) +#define S50_ELS_KS13_KS13_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UDUK_SHIFT)) & S50_ELS_KS13_KS13_UDUK_MASK) + +#define S50_ELS_KS13_KS13_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS13_KS13_UPPROT_SHIFT (30U) +#define S50_ELS_KS13_KS13_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UPPROT_SHIFT)) & S50_ELS_KS13_KS13_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS14 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS14_KS14_KSIZE_MASK (0x3U) +#define S50_ELS_KS14_KS14_KSIZE_SHIFT (0U) +/*! KS14_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS14_KS14_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KSIZE_SHIFT)) & S50_ELS_KS14_KS14_KSIZE_MASK) + +#define S50_ELS_KS14_KS14_KACT_MASK (0x20U) +#define S50_ELS_KS14_KS14_KACT_SHIFT (5U) +#define S50_ELS_KS14_KS14_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KACT_SHIFT)) & S50_ELS_KS14_KS14_KACT_MASK) + +#define S50_ELS_KS14_KS14_KBASE_MASK (0x40U) +#define S50_ELS_KS14_KS14_KBASE_SHIFT (6U) +#define S50_ELS_KS14_KS14_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KBASE_SHIFT)) & S50_ELS_KS14_KS14_KBASE_MASK) + +#define S50_ELS_KS14_KS14_FGP_MASK (0x80U) +#define S50_ELS_KS14_KS14_FGP_SHIFT (7U) +#define S50_ELS_KS14_KS14_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FGP_SHIFT)) & S50_ELS_KS14_KS14_FGP_MASK) + +#define S50_ELS_KS14_KS14_FRTN_MASK (0x100U) +#define S50_ELS_KS14_KS14_FRTN_SHIFT (8U) +#define S50_ELS_KS14_KS14_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FRTN_SHIFT)) & S50_ELS_KS14_KS14_FRTN_MASK) + +#define S50_ELS_KS14_KS14_FHWO_MASK (0x200U) +#define S50_ELS_KS14_KS14_FHWO_SHIFT (9U) +#define S50_ELS_KS14_KS14_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FHWO_SHIFT)) & S50_ELS_KS14_KS14_FHWO_MASK) + +#define S50_ELS_KS14_KS14_UKPUK_MASK (0x800U) +#define S50_ELS_KS14_KS14_UKPUK_SHIFT (11U) +#define S50_ELS_KS14_KS14_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKPUK_SHIFT)) & S50_ELS_KS14_KS14_UKPUK_MASK) + +#define S50_ELS_KS14_KS14_UTECDH_MASK (0x1000U) +#define S50_ELS_KS14_KS14_UTECDH_SHIFT (12U) +#define S50_ELS_KS14_KS14_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTECDH_SHIFT)) & S50_ELS_KS14_KS14_UTECDH_MASK) + +#define S50_ELS_KS14_KS14_UCMAC_MASK (0x2000U) +#define S50_ELS_KS14_KS14_UCMAC_SHIFT (13U) +#define S50_ELS_KS14_KS14_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCMAC_SHIFT)) & S50_ELS_KS14_KS14_UCMAC_MASK) + +#define S50_ELS_KS14_KS14_UKSK_MASK (0x4000U) +#define S50_ELS_KS14_KS14_UKSK_SHIFT (14U) +#define S50_ELS_KS14_KS14_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKSK_SHIFT)) & S50_ELS_KS14_KS14_UKSK_MASK) + +#define S50_ELS_KS14_KS14_URTF_MASK (0x8000U) +#define S50_ELS_KS14_KS14_URTF_SHIFT (15U) +#define S50_ELS_KS14_KS14_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_URTF_SHIFT)) & S50_ELS_KS14_KS14_URTF_MASK) + +#define S50_ELS_KS14_KS14_UCKDF_MASK (0x10000U) +#define S50_ELS_KS14_KS14_UCKDF_SHIFT (16U) +#define S50_ELS_KS14_KS14_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCKDF_SHIFT)) & S50_ELS_KS14_KS14_UCKDF_MASK) + +#define S50_ELS_KS14_KS14_UHKDF_MASK (0x20000U) +#define S50_ELS_KS14_KS14_UHKDF_SHIFT (17U) +#define S50_ELS_KS14_KS14_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHKDF_SHIFT)) & S50_ELS_KS14_KS14_UHKDF_MASK) + +#define S50_ELS_KS14_KS14_UECSG_MASK (0x40000U) +#define S50_ELS_KS14_KS14_UECSG_SHIFT (18U) +#define S50_ELS_KS14_KS14_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECSG_SHIFT)) & S50_ELS_KS14_KS14_UECSG_MASK) + +#define S50_ELS_KS14_KS14_UECDH_MASK (0x80000U) +#define S50_ELS_KS14_KS14_UECDH_SHIFT (19U) +#define S50_ELS_KS14_KS14_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECDH_SHIFT)) & S50_ELS_KS14_KS14_UECDH_MASK) + +#define S50_ELS_KS14_KS14_UAES_MASK (0x100000U) +#define S50_ELS_KS14_KS14_UAES_SHIFT (20U) +#define S50_ELS_KS14_KS14_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UAES_SHIFT)) & S50_ELS_KS14_KS14_UAES_MASK) + +#define S50_ELS_KS14_KS14_UHMAC_MASK (0x200000U) +#define S50_ELS_KS14_KS14_UHMAC_SHIFT (21U) +#define S50_ELS_KS14_KS14_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHMAC_SHIFT)) & S50_ELS_KS14_KS14_UHMAC_MASK) + +#define S50_ELS_KS14_KS14_UKWK_MASK (0x400000U) +#define S50_ELS_KS14_KS14_UKWK_SHIFT (22U) +#define S50_ELS_KS14_KS14_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKWK_SHIFT)) & S50_ELS_KS14_KS14_UKWK_MASK) + +#define S50_ELS_KS14_KS14_UKUOK_MASK (0x800000U) +#define S50_ELS_KS14_KS14_UKUOK_SHIFT (23U) +#define S50_ELS_KS14_KS14_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKUOK_SHIFT)) & S50_ELS_KS14_KS14_UKUOK_MASK) + +#define S50_ELS_KS14_KS14_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS14_KS14_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS14_KS14_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSPMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSPMS_MASK) + +#define S50_ELS_KS14_KS14_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS14_KS14_UTLSMS_SHIFT (25U) +#define S50_ELS_KS14_KS14_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSMS_MASK) + +#define S50_ELS_KS14_KS14_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS14_KS14_UKGSRC_SHIFT (26U) +#define S50_ELS_KS14_KS14_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKGSRC_SHIFT)) & S50_ELS_KS14_KS14_UKGSRC_MASK) + +#define S50_ELS_KS14_KS14_UHWO_MASK (0x8000000U) +#define S50_ELS_KS14_KS14_UHWO_SHIFT (27U) +#define S50_ELS_KS14_KS14_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHWO_SHIFT)) & S50_ELS_KS14_KS14_UHWO_MASK) + +#define S50_ELS_KS14_KS14_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS14_KS14_UWRPOK_SHIFT (28U) +#define S50_ELS_KS14_KS14_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UWRPOK_SHIFT)) & S50_ELS_KS14_KS14_UWRPOK_MASK) + +#define S50_ELS_KS14_KS14_UDUK_MASK (0x20000000U) +#define S50_ELS_KS14_KS14_UDUK_SHIFT (29U) +#define S50_ELS_KS14_KS14_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UDUK_SHIFT)) & S50_ELS_KS14_KS14_UDUK_MASK) + +#define S50_ELS_KS14_KS14_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS14_KS14_UPPROT_SHIFT (30U) +#define S50_ELS_KS14_KS14_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UPPROT_SHIFT)) & S50_ELS_KS14_KS14_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS15 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS15_KS15_KSIZE_MASK (0x3U) +#define S50_ELS_KS15_KS15_KSIZE_SHIFT (0U) +/*! KS15_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS15_KS15_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KSIZE_SHIFT)) & S50_ELS_KS15_KS15_KSIZE_MASK) + +#define S50_ELS_KS15_KS15_KACT_MASK (0x20U) +#define S50_ELS_KS15_KS15_KACT_SHIFT (5U) +#define S50_ELS_KS15_KS15_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KACT_SHIFT)) & S50_ELS_KS15_KS15_KACT_MASK) + +#define S50_ELS_KS15_KS15_KBASE_MASK (0x40U) +#define S50_ELS_KS15_KS15_KBASE_SHIFT (6U) +#define S50_ELS_KS15_KS15_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KBASE_SHIFT)) & S50_ELS_KS15_KS15_KBASE_MASK) + +#define S50_ELS_KS15_KS15_FGP_MASK (0x80U) +#define S50_ELS_KS15_KS15_FGP_SHIFT (7U) +#define S50_ELS_KS15_KS15_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FGP_SHIFT)) & S50_ELS_KS15_KS15_FGP_MASK) + +#define S50_ELS_KS15_KS15_FRTN_MASK (0x100U) +#define S50_ELS_KS15_KS15_FRTN_SHIFT (8U) +#define S50_ELS_KS15_KS15_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FRTN_SHIFT)) & S50_ELS_KS15_KS15_FRTN_MASK) + +#define S50_ELS_KS15_KS15_FHWO_MASK (0x200U) +#define S50_ELS_KS15_KS15_FHWO_SHIFT (9U) +#define S50_ELS_KS15_KS15_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FHWO_SHIFT)) & S50_ELS_KS15_KS15_FHWO_MASK) + +#define S50_ELS_KS15_KS15_UKPUK_MASK (0x800U) +#define S50_ELS_KS15_KS15_UKPUK_SHIFT (11U) +#define S50_ELS_KS15_KS15_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKPUK_SHIFT)) & S50_ELS_KS15_KS15_UKPUK_MASK) + +#define S50_ELS_KS15_KS15_UTECDH_MASK (0x1000U) +#define S50_ELS_KS15_KS15_UTECDH_SHIFT (12U) +#define S50_ELS_KS15_KS15_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTECDH_SHIFT)) & S50_ELS_KS15_KS15_UTECDH_MASK) + +#define S50_ELS_KS15_KS15_UCMAC_MASK (0x2000U) +#define S50_ELS_KS15_KS15_UCMAC_SHIFT (13U) +#define S50_ELS_KS15_KS15_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCMAC_SHIFT)) & S50_ELS_KS15_KS15_UCMAC_MASK) + +#define S50_ELS_KS15_KS15_UKSK_MASK (0x4000U) +#define S50_ELS_KS15_KS15_UKSK_SHIFT (14U) +#define S50_ELS_KS15_KS15_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKSK_SHIFT)) & S50_ELS_KS15_KS15_UKSK_MASK) + +#define S50_ELS_KS15_KS15_URTF_MASK (0x8000U) +#define S50_ELS_KS15_KS15_URTF_SHIFT (15U) +#define S50_ELS_KS15_KS15_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_URTF_SHIFT)) & S50_ELS_KS15_KS15_URTF_MASK) + +#define S50_ELS_KS15_KS15_UCKDF_MASK (0x10000U) +#define S50_ELS_KS15_KS15_UCKDF_SHIFT (16U) +#define S50_ELS_KS15_KS15_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCKDF_SHIFT)) & S50_ELS_KS15_KS15_UCKDF_MASK) + +#define S50_ELS_KS15_KS15_UHKDF_MASK (0x20000U) +#define S50_ELS_KS15_KS15_UHKDF_SHIFT (17U) +#define S50_ELS_KS15_KS15_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHKDF_SHIFT)) & S50_ELS_KS15_KS15_UHKDF_MASK) + +#define S50_ELS_KS15_KS15_UECSG_MASK (0x40000U) +#define S50_ELS_KS15_KS15_UECSG_SHIFT (18U) +#define S50_ELS_KS15_KS15_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECSG_SHIFT)) & S50_ELS_KS15_KS15_UECSG_MASK) + +#define S50_ELS_KS15_KS15_UECDH_MASK (0x80000U) +#define S50_ELS_KS15_KS15_UECDH_SHIFT (19U) +#define S50_ELS_KS15_KS15_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECDH_SHIFT)) & S50_ELS_KS15_KS15_UECDH_MASK) + +#define S50_ELS_KS15_KS15_UAES_MASK (0x100000U) +#define S50_ELS_KS15_KS15_UAES_SHIFT (20U) +#define S50_ELS_KS15_KS15_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UAES_SHIFT)) & S50_ELS_KS15_KS15_UAES_MASK) + +#define S50_ELS_KS15_KS15_UHMAC_MASK (0x200000U) +#define S50_ELS_KS15_KS15_UHMAC_SHIFT (21U) +#define S50_ELS_KS15_KS15_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHMAC_SHIFT)) & S50_ELS_KS15_KS15_UHMAC_MASK) + +#define S50_ELS_KS15_KS15_UKWK_MASK (0x400000U) +#define S50_ELS_KS15_KS15_UKWK_SHIFT (22U) +#define S50_ELS_KS15_KS15_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKWK_SHIFT)) & S50_ELS_KS15_KS15_UKWK_MASK) + +#define S50_ELS_KS15_KS15_UKUOK_MASK (0x800000U) +#define S50_ELS_KS15_KS15_UKUOK_SHIFT (23U) +#define S50_ELS_KS15_KS15_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKUOK_SHIFT)) & S50_ELS_KS15_KS15_UKUOK_MASK) + +#define S50_ELS_KS15_KS15_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS15_KS15_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS15_KS15_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSPMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSPMS_MASK) + +#define S50_ELS_KS15_KS15_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS15_KS15_UTLSMS_SHIFT (25U) +#define S50_ELS_KS15_KS15_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSMS_MASK) + +#define S50_ELS_KS15_KS15_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS15_KS15_UKGSRC_SHIFT (26U) +#define S50_ELS_KS15_KS15_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKGSRC_SHIFT)) & S50_ELS_KS15_KS15_UKGSRC_MASK) + +#define S50_ELS_KS15_KS15_UHWO_MASK (0x8000000U) +#define S50_ELS_KS15_KS15_UHWO_SHIFT (27U) +#define S50_ELS_KS15_KS15_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHWO_SHIFT)) & S50_ELS_KS15_KS15_UHWO_MASK) + +#define S50_ELS_KS15_KS15_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS15_KS15_UWRPOK_SHIFT (28U) +#define S50_ELS_KS15_KS15_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UWRPOK_SHIFT)) & S50_ELS_KS15_KS15_UWRPOK_MASK) + +#define S50_ELS_KS15_KS15_UDUK_MASK (0x20000000U) +#define S50_ELS_KS15_KS15_UDUK_SHIFT (29U) +#define S50_ELS_KS15_KS15_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UDUK_SHIFT)) & S50_ELS_KS15_KS15_UDUK_MASK) + +#define S50_ELS_KS15_KS15_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS15_KS15_UPPROT_SHIFT (30U) +#define S50_ELS_KS15_KS15_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UPPROT_SHIFT)) & S50_ELS_KS15_KS15_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS16 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS16_KS16_KSIZE_MASK (0x3U) +#define S50_ELS_KS16_KS16_KSIZE_SHIFT (0U) +/*! KS16_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS16_KS16_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KSIZE_SHIFT)) & S50_ELS_KS16_KS16_KSIZE_MASK) + +#define S50_ELS_KS16_KS16_KACT_MASK (0x20U) +#define S50_ELS_KS16_KS16_KACT_SHIFT (5U) +#define S50_ELS_KS16_KS16_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KACT_SHIFT)) & S50_ELS_KS16_KS16_KACT_MASK) + +#define S50_ELS_KS16_KS16_KBASE_MASK (0x40U) +#define S50_ELS_KS16_KS16_KBASE_SHIFT (6U) +#define S50_ELS_KS16_KS16_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KBASE_SHIFT)) & S50_ELS_KS16_KS16_KBASE_MASK) + +#define S50_ELS_KS16_KS16_FGP_MASK (0x80U) +#define S50_ELS_KS16_KS16_FGP_SHIFT (7U) +#define S50_ELS_KS16_KS16_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FGP_SHIFT)) & S50_ELS_KS16_KS16_FGP_MASK) + +#define S50_ELS_KS16_KS16_FRTN_MASK (0x100U) +#define S50_ELS_KS16_KS16_FRTN_SHIFT (8U) +#define S50_ELS_KS16_KS16_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FRTN_SHIFT)) & S50_ELS_KS16_KS16_FRTN_MASK) + +#define S50_ELS_KS16_KS16_FHWO_MASK (0x200U) +#define S50_ELS_KS16_KS16_FHWO_SHIFT (9U) +#define S50_ELS_KS16_KS16_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FHWO_SHIFT)) & S50_ELS_KS16_KS16_FHWO_MASK) + +#define S50_ELS_KS16_KS16_UKPUK_MASK (0x800U) +#define S50_ELS_KS16_KS16_UKPUK_SHIFT (11U) +#define S50_ELS_KS16_KS16_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKPUK_SHIFT)) & S50_ELS_KS16_KS16_UKPUK_MASK) + +#define S50_ELS_KS16_KS16_UTECDH_MASK (0x1000U) +#define S50_ELS_KS16_KS16_UTECDH_SHIFT (12U) +#define S50_ELS_KS16_KS16_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTECDH_SHIFT)) & S50_ELS_KS16_KS16_UTECDH_MASK) + +#define S50_ELS_KS16_KS16_UCMAC_MASK (0x2000U) +#define S50_ELS_KS16_KS16_UCMAC_SHIFT (13U) +#define S50_ELS_KS16_KS16_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCMAC_SHIFT)) & S50_ELS_KS16_KS16_UCMAC_MASK) + +#define S50_ELS_KS16_KS16_UKSK_MASK (0x4000U) +#define S50_ELS_KS16_KS16_UKSK_SHIFT (14U) +#define S50_ELS_KS16_KS16_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKSK_SHIFT)) & S50_ELS_KS16_KS16_UKSK_MASK) + +#define S50_ELS_KS16_KS16_URTF_MASK (0x8000U) +#define S50_ELS_KS16_KS16_URTF_SHIFT (15U) +#define S50_ELS_KS16_KS16_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_URTF_SHIFT)) & S50_ELS_KS16_KS16_URTF_MASK) + +#define S50_ELS_KS16_KS16_UCKDF_MASK (0x10000U) +#define S50_ELS_KS16_KS16_UCKDF_SHIFT (16U) +#define S50_ELS_KS16_KS16_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCKDF_SHIFT)) & S50_ELS_KS16_KS16_UCKDF_MASK) + +#define S50_ELS_KS16_KS16_UHKDF_MASK (0x20000U) +#define S50_ELS_KS16_KS16_UHKDF_SHIFT (17U) +#define S50_ELS_KS16_KS16_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHKDF_SHIFT)) & S50_ELS_KS16_KS16_UHKDF_MASK) + +#define S50_ELS_KS16_KS16_UECSG_MASK (0x40000U) +#define S50_ELS_KS16_KS16_UECSG_SHIFT (18U) +#define S50_ELS_KS16_KS16_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECSG_SHIFT)) & S50_ELS_KS16_KS16_UECSG_MASK) + +#define S50_ELS_KS16_KS16_UECDH_MASK (0x80000U) +#define S50_ELS_KS16_KS16_UECDH_SHIFT (19U) +#define S50_ELS_KS16_KS16_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECDH_SHIFT)) & S50_ELS_KS16_KS16_UECDH_MASK) + +#define S50_ELS_KS16_KS16_UAES_MASK (0x100000U) +#define S50_ELS_KS16_KS16_UAES_SHIFT (20U) +#define S50_ELS_KS16_KS16_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UAES_SHIFT)) & S50_ELS_KS16_KS16_UAES_MASK) + +#define S50_ELS_KS16_KS16_UHMAC_MASK (0x200000U) +#define S50_ELS_KS16_KS16_UHMAC_SHIFT (21U) +#define S50_ELS_KS16_KS16_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHMAC_SHIFT)) & S50_ELS_KS16_KS16_UHMAC_MASK) + +#define S50_ELS_KS16_KS16_UKWK_MASK (0x400000U) +#define S50_ELS_KS16_KS16_UKWK_SHIFT (22U) +#define S50_ELS_KS16_KS16_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKWK_SHIFT)) & S50_ELS_KS16_KS16_UKWK_MASK) + +#define S50_ELS_KS16_KS16_UKUOK_MASK (0x800000U) +#define S50_ELS_KS16_KS16_UKUOK_SHIFT (23U) +#define S50_ELS_KS16_KS16_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKUOK_SHIFT)) & S50_ELS_KS16_KS16_UKUOK_MASK) + +#define S50_ELS_KS16_KS16_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS16_KS16_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS16_KS16_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSPMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSPMS_MASK) + +#define S50_ELS_KS16_KS16_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS16_KS16_UTLSMS_SHIFT (25U) +#define S50_ELS_KS16_KS16_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSMS_MASK) + +#define S50_ELS_KS16_KS16_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS16_KS16_UKGSRC_SHIFT (26U) +#define S50_ELS_KS16_KS16_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKGSRC_SHIFT)) & S50_ELS_KS16_KS16_UKGSRC_MASK) + +#define S50_ELS_KS16_KS16_UHWO_MASK (0x8000000U) +#define S50_ELS_KS16_KS16_UHWO_SHIFT (27U) +#define S50_ELS_KS16_KS16_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHWO_SHIFT)) & S50_ELS_KS16_KS16_UHWO_MASK) + +#define S50_ELS_KS16_KS16_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS16_KS16_UWRPOK_SHIFT (28U) +#define S50_ELS_KS16_KS16_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UWRPOK_SHIFT)) & S50_ELS_KS16_KS16_UWRPOK_MASK) + +#define S50_ELS_KS16_KS16_UDUK_MASK (0x20000000U) +#define S50_ELS_KS16_KS16_UDUK_SHIFT (29U) +#define S50_ELS_KS16_KS16_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UDUK_SHIFT)) & S50_ELS_KS16_KS16_UDUK_MASK) + +#define S50_ELS_KS16_KS16_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS16_KS16_UPPROT_SHIFT (30U) +#define S50_ELS_KS16_KS16_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UPPROT_SHIFT)) & S50_ELS_KS16_KS16_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS17 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS17_KS17_KSIZE_MASK (0x3U) +#define S50_ELS_KS17_KS17_KSIZE_SHIFT (0U) +/*! KS17_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS17_KS17_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KSIZE_SHIFT)) & S50_ELS_KS17_KS17_KSIZE_MASK) + +#define S50_ELS_KS17_KS17_KACT_MASK (0x20U) +#define S50_ELS_KS17_KS17_KACT_SHIFT (5U) +#define S50_ELS_KS17_KS17_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KACT_SHIFT)) & S50_ELS_KS17_KS17_KACT_MASK) + +#define S50_ELS_KS17_KS17_KBASE_MASK (0x40U) +#define S50_ELS_KS17_KS17_KBASE_SHIFT (6U) +#define S50_ELS_KS17_KS17_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KBASE_SHIFT)) & S50_ELS_KS17_KS17_KBASE_MASK) + +#define S50_ELS_KS17_KS17_FGP_MASK (0x80U) +#define S50_ELS_KS17_KS17_FGP_SHIFT (7U) +#define S50_ELS_KS17_KS17_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FGP_SHIFT)) & S50_ELS_KS17_KS17_FGP_MASK) + +#define S50_ELS_KS17_KS17_FRTN_MASK (0x100U) +#define S50_ELS_KS17_KS17_FRTN_SHIFT (8U) +#define S50_ELS_KS17_KS17_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FRTN_SHIFT)) & S50_ELS_KS17_KS17_FRTN_MASK) + +#define S50_ELS_KS17_KS17_FHWO_MASK (0x200U) +#define S50_ELS_KS17_KS17_FHWO_SHIFT (9U) +#define S50_ELS_KS17_KS17_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FHWO_SHIFT)) & S50_ELS_KS17_KS17_FHWO_MASK) + +#define S50_ELS_KS17_KS17_UKPUK_MASK (0x800U) +#define S50_ELS_KS17_KS17_UKPUK_SHIFT (11U) +#define S50_ELS_KS17_KS17_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKPUK_SHIFT)) & S50_ELS_KS17_KS17_UKPUK_MASK) + +#define S50_ELS_KS17_KS17_UTECDH_MASK (0x1000U) +#define S50_ELS_KS17_KS17_UTECDH_SHIFT (12U) +#define S50_ELS_KS17_KS17_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTECDH_SHIFT)) & S50_ELS_KS17_KS17_UTECDH_MASK) + +#define S50_ELS_KS17_KS17_UCMAC_MASK (0x2000U) +#define S50_ELS_KS17_KS17_UCMAC_SHIFT (13U) +#define S50_ELS_KS17_KS17_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCMAC_SHIFT)) & S50_ELS_KS17_KS17_UCMAC_MASK) + +#define S50_ELS_KS17_KS17_UKSK_MASK (0x4000U) +#define S50_ELS_KS17_KS17_UKSK_SHIFT (14U) +#define S50_ELS_KS17_KS17_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKSK_SHIFT)) & S50_ELS_KS17_KS17_UKSK_MASK) + +#define S50_ELS_KS17_KS17_URTF_MASK (0x8000U) +#define S50_ELS_KS17_KS17_URTF_SHIFT (15U) +#define S50_ELS_KS17_KS17_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_URTF_SHIFT)) & S50_ELS_KS17_KS17_URTF_MASK) + +#define S50_ELS_KS17_KS17_UCKDF_MASK (0x10000U) +#define S50_ELS_KS17_KS17_UCKDF_SHIFT (16U) +#define S50_ELS_KS17_KS17_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCKDF_SHIFT)) & S50_ELS_KS17_KS17_UCKDF_MASK) + +#define S50_ELS_KS17_KS17_UHKDF_MASK (0x20000U) +#define S50_ELS_KS17_KS17_UHKDF_SHIFT (17U) +#define S50_ELS_KS17_KS17_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHKDF_SHIFT)) & S50_ELS_KS17_KS17_UHKDF_MASK) + +#define S50_ELS_KS17_KS17_UECSG_MASK (0x40000U) +#define S50_ELS_KS17_KS17_UECSG_SHIFT (18U) +#define S50_ELS_KS17_KS17_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECSG_SHIFT)) & S50_ELS_KS17_KS17_UECSG_MASK) + +#define S50_ELS_KS17_KS17_UECDH_MASK (0x80000U) +#define S50_ELS_KS17_KS17_UECDH_SHIFT (19U) +#define S50_ELS_KS17_KS17_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECDH_SHIFT)) & S50_ELS_KS17_KS17_UECDH_MASK) + +#define S50_ELS_KS17_KS17_UAES_MASK (0x100000U) +#define S50_ELS_KS17_KS17_UAES_SHIFT (20U) +#define S50_ELS_KS17_KS17_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UAES_SHIFT)) & S50_ELS_KS17_KS17_UAES_MASK) + +#define S50_ELS_KS17_KS17_UHMAC_MASK (0x200000U) +#define S50_ELS_KS17_KS17_UHMAC_SHIFT (21U) +#define S50_ELS_KS17_KS17_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHMAC_SHIFT)) & S50_ELS_KS17_KS17_UHMAC_MASK) + +#define S50_ELS_KS17_KS17_UKWK_MASK (0x400000U) +#define S50_ELS_KS17_KS17_UKWK_SHIFT (22U) +#define S50_ELS_KS17_KS17_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKWK_SHIFT)) & S50_ELS_KS17_KS17_UKWK_MASK) + +#define S50_ELS_KS17_KS17_UKUOK_MASK (0x800000U) +#define S50_ELS_KS17_KS17_UKUOK_SHIFT (23U) +#define S50_ELS_KS17_KS17_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKUOK_SHIFT)) & S50_ELS_KS17_KS17_UKUOK_MASK) + +#define S50_ELS_KS17_KS17_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS17_KS17_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS17_KS17_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSPMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSPMS_MASK) + +#define S50_ELS_KS17_KS17_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS17_KS17_UTLSMS_SHIFT (25U) +#define S50_ELS_KS17_KS17_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSMS_MASK) + +#define S50_ELS_KS17_KS17_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS17_KS17_UKGSRC_SHIFT (26U) +#define S50_ELS_KS17_KS17_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKGSRC_SHIFT)) & S50_ELS_KS17_KS17_UKGSRC_MASK) + +#define S50_ELS_KS17_KS17_UHWO_MASK (0x8000000U) +#define S50_ELS_KS17_KS17_UHWO_SHIFT (27U) +#define S50_ELS_KS17_KS17_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHWO_SHIFT)) & S50_ELS_KS17_KS17_UHWO_MASK) + +#define S50_ELS_KS17_KS17_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS17_KS17_UWRPOK_SHIFT (28U) +#define S50_ELS_KS17_KS17_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UWRPOK_SHIFT)) & S50_ELS_KS17_KS17_UWRPOK_MASK) + +#define S50_ELS_KS17_KS17_UDUK_MASK (0x20000000U) +#define S50_ELS_KS17_KS17_UDUK_SHIFT (29U) +#define S50_ELS_KS17_KS17_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UDUK_SHIFT)) & S50_ELS_KS17_KS17_UDUK_MASK) + +#define S50_ELS_KS17_KS17_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS17_KS17_UPPROT_SHIFT (30U) +#define S50_ELS_KS17_KS17_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UPPROT_SHIFT)) & S50_ELS_KS17_KS17_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS18 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS18_KS18_KSIZE_MASK (0x3U) +#define S50_ELS_KS18_KS18_KSIZE_SHIFT (0U) +/*! KS18_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS18_KS18_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KSIZE_SHIFT)) & S50_ELS_KS18_KS18_KSIZE_MASK) + +#define S50_ELS_KS18_KS18_KACT_MASK (0x20U) +#define S50_ELS_KS18_KS18_KACT_SHIFT (5U) +#define S50_ELS_KS18_KS18_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KACT_SHIFT)) & S50_ELS_KS18_KS18_KACT_MASK) + +#define S50_ELS_KS18_KS18_KBASE_MASK (0x40U) +#define S50_ELS_KS18_KS18_KBASE_SHIFT (6U) +#define S50_ELS_KS18_KS18_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KBASE_SHIFT)) & S50_ELS_KS18_KS18_KBASE_MASK) + +#define S50_ELS_KS18_KS18_FGP_MASK (0x80U) +#define S50_ELS_KS18_KS18_FGP_SHIFT (7U) +#define S50_ELS_KS18_KS18_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FGP_SHIFT)) & S50_ELS_KS18_KS18_FGP_MASK) + +#define S50_ELS_KS18_KS18_FRTN_MASK (0x100U) +#define S50_ELS_KS18_KS18_FRTN_SHIFT (8U) +#define S50_ELS_KS18_KS18_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FRTN_SHIFT)) & S50_ELS_KS18_KS18_FRTN_MASK) + +#define S50_ELS_KS18_KS18_FHWO_MASK (0x200U) +#define S50_ELS_KS18_KS18_FHWO_SHIFT (9U) +#define S50_ELS_KS18_KS18_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FHWO_SHIFT)) & S50_ELS_KS18_KS18_FHWO_MASK) + +#define S50_ELS_KS18_KS18_UKPUK_MASK (0x800U) +#define S50_ELS_KS18_KS18_UKPUK_SHIFT (11U) +#define S50_ELS_KS18_KS18_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKPUK_SHIFT)) & S50_ELS_KS18_KS18_UKPUK_MASK) + +#define S50_ELS_KS18_KS18_UTECDH_MASK (0x1000U) +#define S50_ELS_KS18_KS18_UTECDH_SHIFT (12U) +#define S50_ELS_KS18_KS18_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTECDH_SHIFT)) & S50_ELS_KS18_KS18_UTECDH_MASK) + +#define S50_ELS_KS18_KS18_UCMAC_MASK (0x2000U) +#define S50_ELS_KS18_KS18_UCMAC_SHIFT (13U) +#define S50_ELS_KS18_KS18_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCMAC_SHIFT)) & S50_ELS_KS18_KS18_UCMAC_MASK) + +#define S50_ELS_KS18_KS18_UKSK_MASK (0x4000U) +#define S50_ELS_KS18_KS18_UKSK_SHIFT (14U) +#define S50_ELS_KS18_KS18_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKSK_SHIFT)) & S50_ELS_KS18_KS18_UKSK_MASK) + +#define S50_ELS_KS18_KS18_URTF_MASK (0x8000U) +#define S50_ELS_KS18_KS18_URTF_SHIFT (15U) +#define S50_ELS_KS18_KS18_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_URTF_SHIFT)) & S50_ELS_KS18_KS18_URTF_MASK) + +#define S50_ELS_KS18_KS18_UCKDF_MASK (0x10000U) +#define S50_ELS_KS18_KS18_UCKDF_SHIFT (16U) +#define S50_ELS_KS18_KS18_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCKDF_SHIFT)) & S50_ELS_KS18_KS18_UCKDF_MASK) + +#define S50_ELS_KS18_KS18_UHKDF_MASK (0x20000U) +#define S50_ELS_KS18_KS18_UHKDF_SHIFT (17U) +#define S50_ELS_KS18_KS18_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHKDF_SHIFT)) & S50_ELS_KS18_KS18_UHKDF_MASK) + +#define S50_ELS_KS18_KS18_UECSG_MASK (0x40000U) +#define S50_ELS_KS18_KS18_UECSG_SHIFT (18U) +#define S50_ELS_KS18_KS18_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECSG_SHIFT)) & S50_ELS_KS18_KS18_UECSG_MASK) + +#define S50_ELS_KS18_KS18_UECDH_MASK (0x80000U) +#define S50_ELS_KS18_KS18_UECDH_SHIFT (19U) +#define S50_ELS_KS18_KS18_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECDH_SHIFT)) & S50_ELS_KS18_KS18_UECDH_MASK) + +#define S50_ELS_KS18_KS18_UAES_MASK (0x100000U) +#define S50_ELS_KS18_KS18_UAES_SHIFT (20U) +#define S50_ELS_KS18_KS18_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UAES_SHIFT)) & S50_ELS_KS18_KS18_UAES_MASK) + +#define S50_ELS_KS18_KS18_UHMAC_MASK (0x200000U) +#define S50_ELS_KS18_KS18_UHMAC_SHIFT (21U) +#define S50_ELS_KS18_KS18_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHMAC_SHIFT)) & S50_ELS_KS18_KS18_UHMAC_MASK) + +#define S50_ELS_KS18_KS18_UKWK_MASK (0x400000U) +#define S50_ELS_KS18_KS18_UKWK_SHIFT (22U) +#define S50_ELS_KS18_KS18_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKWK_SHIFT)) & S50_ELS_KS18_KS18_UKWK_MASK) + +#define S50_ELS_KS18_KS18_UKUOK_MASK (0x800000U) +#define S50_ELS_KS18_KS18_UKUOK_SHIFT (23U) +#define S50_ELS_KS18_KS18_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKUOK_SHIFT)) & S50_ELS_KS18_KS18_UKUOK_MASK) + +#define S50_ELS_KS18_KS18_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS18_KS18_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS18_KS18_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSPMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSPMS_MASK) + +#define S50_ELS_KS18_KS18_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS18_KS18_UTLSMS_SHIFT (25U) +#define S50_ELS_KS18_KS18_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSMS_MASK) + +#define S50_ELS_KS18_KS18_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS18_KS18_UKGSRC_SHIFT (26U) +#define S50_ELS_KS18_KS18_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKGSRC_SHIFT)) & S50_ELS_KS18_KS18_UKGSRC_MASK) + +#define S50_ELS_KS18_KS18_UHWO_MASK (0x8000000U) +#define S50_ELS_KS18_KS18_UHWO_SHIFT (27U) +#define S50_ELS_KS18_KS18_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHWO_SHIFT)) & S50_ELS_KS18_KS18_UHWO_MASK) + +#define S50_ELS_KS18_KS18_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS18_KS18_UWRPOK_SHIFT (28U) +#define S50_ELS_KS18_KS18_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UWRPOK_SHIFT)) & S50_ELS_KS18_KS18_UWRPOK_MASK) + +#define S50_ELS_KS18_KS18_UDUK_MASK (0x20000000U) +#define S50_ELS_KS18_KS18_UDUK_SHIFT (29U) +#define S50_ELS_KS18_KS18_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UDUK_SHIFT)) & S50_ELS_KS18_KS18_UDUK_MASK) + +#define S50_ELS_KS18_KS18_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS18_KS18_UPPROT_SHIFT (30U) +#define S50_ELS_KS18_KS18_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UPPROT_SHIFT)) & S50_ELS_KS18_KS18_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS19 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS19_KS19_KSIZE_MASK (0x3U) +#define S50_ELS_KS19_KS19_KSIZE_SHIFT (0U) +/*! KS19_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS19_KS19_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KSIZE_SHIFT)) & S50_ELS_KS19_KS19_KSIZE_MASK) + +#define S50_ELS_KS19_KS19_KACT_MASK (0x20U) +#define S50_ELS_KS19_KS19_KACT_SHIFT (5U) +#define S50_ELS_KS19_KS19_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KACT_SHIFT)) & S50_ELS_KS19_KS19_KACT_MASK) + +#define S50_ELS_KS19_KS19_KBASE_MASK (0x40U) +#define S50_ELS_KS19_KS19_KBASE_SHIFT (6U) +#define S50_ELS_KS19_KS19_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KBASE_SHIFT)) & S50_ELS_KS19_KS19_KBASE_MASK) + +#define S50_ELS_KS19_KS19_FGP_MASK (0x80U) +#define S50_ELS_KS19_KS19_FGP_SHIFT (7U) +#define S50_ELS_KS19_KS19_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FGP_SHIFT)) & S50_ELS_KS19_KS19_FGP_MASK) + +#define S50_ELS_KS19_KS19_FRTN_MASK (0x100U) +#define S50_ELS_KS19_KS19_FRTN_SHIFT (8U) +#define S50_ELS_KS19_KS19_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FRTN_SHIFT)) & S50_ELS_KS19_KS19_FRTN_MASK) + +#define S50_ELS_KS19_KS19_FHWO_MASK (0x200U) +#define S50_ELS_KS19_KS19_FHWO_SHIFT (9U) +#define S50_ELS_KS19_KS19_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FHWO_SHIFT)) & S50_ELS_KS19_KS19_FHWO_MASK) + +#define S50_ELS_KS19_KS19_UKPUK_MASK (0x800U) +#define S50_ELS_KS19_KS19_UKPUK_SHIFT (11U) +#define S50_ELS_KS19_KS19_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKPUK_SHIFT)) & S50_ELS_KS19_KS19_UKPUK_MASK) + +#define S50_ELS_KS19_KS19_UTECDH_MASK (0x1000U) +#define S50_ELS_KS19_KS19_UTECDH_SHIFT (12U) +#define S50_ELS_KS19_KS19_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTECDH_SHIFT)) & S50_ELS_KS19_KS19_UTECDH_MASK) + +#define S50_ELS_KS19_KS19_UCMAC_MASK (0x2000U) +#define S50_ELS_KS19_KS19_UCMAC_SHIFT (13U) +#define S50_ELS_KS19_KS19_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCMAC_SHIFT)) & S50_ELS_KS19_KS19_UCMAC_MASK) + +#define S50_ELS_KS19_KS19_UKSK_MASK (0x4000U) +#define S50_ELS_KS19_KS19_UKSK_SHIFT (14U) +#define S50_ELS_KS19_KS19_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKSK_SHIFT)) & S50_ELS_KS19_KS19_UKSK_MASK) + +#define S50_ELS_KS19_KS19_URTF_MASK (0x8000U) +#define S50_ELS_KS19_KS19_URTF_SHIFT (15U) +#define S50_ELS_KS19_KS19_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_URTF_SHIFT)) & S50_ELS_KS19_KS19_URTF_MASK) + +#define S50_ELS_KS19_KS19_UCKDF_MASK (0x10000U) +#define S50_ELS_KS19_KS19_UCKDF_SHIFT (16U) +#define S50_ELS_KS19_KS19_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCKDF_SHIFT)) & S50_ELS_KS19_KS19_UCKDF_MASK) + +#define S50_ELS_KS19_KS19_UHKDF_MASK (0x20000U) +#define S50_ELS_KS19_KS19_UHKDF_SHIFT (17U) +#define S50_ELS_KS19_KS19_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHKDF_SHIFT)) & S50_ELS_KS19_KS19_UHKDF_MASK) + +#define S50_ELS_KS19_KS19_UECSG_MASK (0x40000U) +#define S50_ELS_KS19_KS19_UECSG_SHIFT (18U) +#define S50_ELS_KS19_KS19_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECSG_SHIFT)) & S50_ELS_KS19_KS19_UECSG_MASK) + +#define S50_ELS_KS19_KS19_UECDH_MASK (0x80000U) +#define S50_ELS_KS19_KS19_UECDH_SHIFT (19U) +#define S50_ELS_KS19_KS19_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECDH_SHIFT)) & S50_ELS_KS19_KS19_UECDH_MASK) + +#define S50_ELS_KS19_KS19_UAES_MASK (0x100000U) +#define S50_ELS_KS19_KS19_UAES_SHIFT (20U) +#define S50_ELS_KS19_KS19_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UAES_SHIFT)) & S50_ELS_KS19_KS19_UAES_MASK) + +#define S50_ELS_KS19_KS19_UHMAC_MASK (0x200000U) +#define S50_ELS_KS19_KS19_UHMAC_SHIFT (21U) +#define S50_ELS_KS19_KS19_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHMAC_SHIFT)) & S50_ELS_KS19_KS19_UHMAC_MASK) + +#define S50_ELS_KS19_KS19_UKWK_MASK (0x400000U) +#define S50_ELS_KS19_KS19_UKWK_SHIFT (22U) +#define S50_ELS_KS19_KS19_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKWK_SHIFT)) & S50_ELS_KS19_KS19_UKWK_MASK) + +#define S50_ELS_KS19_KS19_UKUOK_MASK (0x800000U) +#define S50_ELS_KS19_KS19_UKUOK_SHIFT (23U) +#define S50_ELS_KS19_KS19_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKUOK_SHIFT)) & S50_ELS_KS19_KS19_UKUOK_MASK) + +#define S50_ELS_KS19_KS19_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS19_KS19_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS19_KS19_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSPMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSPMS_MASK) + +#define S50_ELS_KS19_KS19_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS19_KS19_UTLSMS_SHIFT (25U) +#define S50_ELS_KS19_KS19_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSMS_MASK) + +#define S50_ELS_KS19_KS19_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS19_KS19_UKGSRC_SHIFT (26U) +#define S50_ELS_KS19_KS19_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKGSRC_SHIFT)) & S50_ELS_KS19_KS19_UKGSRC_MASK) + +#define S50_ELS_KS19_KS19_UHWO_MASK (0x8000000U) +#define S50_ELS_KS19_KS19_UHWO_SHIFT (27U) +#define S50_ELS_KS19_KS19_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHWO_SHIFT)) & S50_ELS_KS19_KS19_UHWO_MASK) + +#define S50_ELS_KS19_KS19_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS19_KS19_UWRPOK_SHIFT (28U) +#define S50_ELS_KS19_KS19_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UWRPOK_SHIFT)) & S50_ELS_KS19_KS19_UWRPOK_MASK) + +#define S50_ELS_KS19_KS19_UDUK_MASK (0x20000000U) +#define S50_ELS_KS19_KS19_UDUK_SHIFT (29U) +#define S50_ELS_KS19_KS19_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UDUK_SHIFT)) & S50_ELS_KS19_KS19_UDUK_MASK) + +#define S50_ELS_KS19_KS19_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS19_KS19_UPPROT_SHIFT (30U) +#define S50_ELS_KS19_KS19_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UPPROT_SHIFT)) & S50_ELS_KS19_KS19_UPPROT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group S50_Register_Masks */ + + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group S50_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */ + __IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */ + __IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */ + uint8_t RESERVED_9[228]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */ + uint8_t RESERVED_10[252]; + __IO uint32_t APLLCSR; /**< APLL Control Status Register, offset: 0x500 */ + __IO uint32_t APLLCTRL; /**< APLL Control Register, offset: 0x504 */ + __I uint32_t APLLSTAT; /**< APLL Status Register, offset: 0x508 */ + __IO uint32_t APLLNDIV; /**< APLL N Divider Register, offset: 0x50C */ + __IO uint32_t APLLMDIV; /**< APLL M Divider Register, offset: 0x510 */ + __IO uint32_t APLLPDIV; /**< APLL P Divider Register, offset: 0x514 */ + __IO uint32_t APLLLOCK_CNFG; /**< APLL LOCK Configuration Register, offset: 0x518 */ + uint8_t RESERVED_11[4]; + __I uint32_t APLLSSCGSTAT; /**< APLL SSCG Status Register, offset: 0x520 */ + __IO uint32_t APLLSSCG0; /**< APLL Spread Spectrum Control 0 Register, offset: 0x524 */ + __IO uint32_t APLLSSCG1; /**< APLL Spread Spectrum Control 1 Register, offset: 0x528 */ + uint8_t RESERVED_12[200]; + __IO uint32_t APLL_OVRD; /**< APLL Override Register, offset: 0x5F4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SPLLCSR; /**< SPLL Control Status Register, offset: 0x600 */ + __IO uint32_t SPLLCTRL; /**< SPLL Control Register, offset: 0x604 */ + __I uint32_t SPLLSTAT; /**< SPLL Status Register, offset: 0x608 */ + __IO uint32_t SPLLNDIV; /**< SPLL N Divider Register, offset: 0x60C */ + __IO uint32_t SPLLMDIV; /**< SPLL M Divider Register, offset: 0x610 */ + __IO uint32_t SPLLPDIV; /**< SPLL P Divider Register, offset: 0x614 */ + __IO uint32_t SPLLLOCK_CNFG; /**< SPLL LOCK Configuration Register, offset: 0x618 */ + uint8_t RESERVED_14[4]; + __I uint32_t SPLLSSCGSTAT; /**< SPLL SSCG Status Register, offset: 0x620 */ + __IO uint32_t SPLLSSCG0; /**< SPLL Spread Spectrum Control 0 Register, offset: 0x624 */ + __IO uint32_t SPLLSSCG1; /**< SPLL Spread Spectrum Control 1 Register, offset: 0x628 */ + uint8_t RESERVED_15[200]; + __IO uint32_t SPLL_OVRD; /**< SPLL Override Register, offset: 0x6F4 */ + uint8_t RESERVED_16[8]; + __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ + uint8_t RESERVED_17[252]; + __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ + uint8_t RESERVED_18[252]; + __IO uint32_t TROCSR; /**< TRO Control Status Register, offset: 0x900 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b1..SOSC clock source is present + * 0b0..SOSC clock source is not present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b1..SIRC clock source is present + * 0b0..SIRC clock source is not present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b1..FIRC clock source is present + * 0b0..FIRC clock source is not present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b1..ROSC clock source is present + * 0b0..ROSC clock source is not present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) + +#define SCG_PARAM_APLLCLKPRES_MASK (0x20U) +#define SCG_PARAM_APLLCLKPRES_SHIFT (5U) +/*! APLLCLKPRES - APLL Clock Present + * 0b1..APLL clock source is present + * 0b0..APLL clock source is not present + */ +#define SCG_PARAM_APLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_APLLCLKPRES_SHIFT)) & SCG_PARAM_APLLCLKPRES_MASK) + +#define SCG_PARAM_SPLLCLKPRES_MASK (0x40U) +#define SCG_PARAM_SPLLCLKPRES_SHIFT (6U) +/*! SPLLCLKPRES - SPLL Clock Present + * 0b1..SPLL clock source is present + * 0b0..SPLL clock source is not present + */ +#define SCG_PARAM_SPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK) + +#define SCG_PARAM_UPLLCLKPRES_MASK (0x80U) +#define SCG_PARAM_UPLLCLKPRES_SHIFT (7U) +/*! UPLLCLKPRES - UPLL Clock Present + * 0b1..UPLL clock source is present + * 0b0..UPLL clock source is not present + */ +#define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) + +#define SCG_PARAM_TROCLKPRES_MASK (0x100U) +#define SCG_PARAM_TROCLKPRES_SHIFT (8U) +/*! TROCLKPRES - TRO Clock Present + * 0b1..TRO clock source is present + * 0b0..TRO clock source is not present + */ +#define SCG_PARAM_TROCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_TROCLKPRES_SHIFT)) & SCG_PARAM_TROCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock register */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim registers are locked and not writable. + * 0b1..SCG Trim registers are unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status Register */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0xF000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control Register */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0xF000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status Register */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration Register */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. LDO can be disabled in this case. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 16-20 MHz. + * 0b01..Frequency range select of 20-30 MHz. + * 0b10..Frequency range select of 30-50 MHz. + * 0b11..Frequency range select of 50-66 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status Register */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC coarse auto-trim is not bypassed + * 0b1..SIRC coarse auto-trim is bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC (32.768 kHz) + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Predivider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status Register */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable + * 0b0..FIRC 48 MHz to peripherals is disabled + * 0b1..FIRC 48 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FIRC 144 MHz Clock to peripherals Enable + * 0b0..FIRC 144 MHz to peripherals is disabled + * 0b1..FIRC 144 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) +#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) +/*! FIRCTREN - FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1) + * 0b0..Disables trimming FIRC to an external clock source + * 0b1..Enables trimming FIRC to an external clock source + */ +#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) + +#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) +#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) +/*! FIRCTRUP - FIRC Trim Update + * 0b0..Disables FIRC trimming updates + * 0b1..Enables FIRC trimming updates + */ +#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) + +#define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - FIRC TRIM LOCK + * 0b0..FIRC auto trim not locked to target frequency range + * 0b1..FIRC auto trim locked to target frequency range + */ +#define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK) + +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..FIRC coarse auto trim is not bypassed + * 0b1..FIRC coarse auto trim is bypassed + */ +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz + * (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration Register */ +/*! @{ */ + +#define SCG_FIRCCFG_RANGE_MASK (0x1U) +#define SCG_FIRCCFG_RANGE_SHIFT (0U) +/*! RANGE - Frequency Range + * 0b0..48 MHz FIRC clock selected + * 0b1..144 MHz FIRC clock selected + */ +#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) +/*! @} */ + +/*! @name FIRCTCFG - FIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..USB0 Start of Frame (1 kHz). This option does not use TRIMDIV + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC + */ +#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) + +#define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - FIRC Trim Predivider */ +#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim Register */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP_MASK (0x30000U) +#define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) +/*! TRIMTEMP - Trim Temperature */ +#define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name FIRCSTAT - FIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) + +#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status Register */ +/*! @{ */ + +#define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) +#define SCG_ROSCCSR_ROSCCM_SHIFT (16U) +/*! ROSCCM - ROSC Clock Monitor + * 0b0..ROSC clock monitor is disabled + * 0b1..ROSC clock monitor is enabled + */ +#define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) + +#define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) +#define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) +/*! ROSCCMRE - ROSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock Monitor is disabled or has not detected an error + * 0b1..ROSC Clock Monitor is enabled and detected an RTC loss of clock error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + +/*! @name APLLCSR - APLL Control Status Register */ +/*! @{ */ + +#define SCG_APLLCSR_APLLPWREN_MASK (0x1U) +#define SCG_APLLCSR_APLLPWREN_SHIFT (0U) +/*! APLLPWREN - APLL Power Enable + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLLCSR_APLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLPWREN_SHIFT)) & SCG_APLLCSR_APLLPWREN_MASK) + +#define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) +#define SCG_APLLCSR_APLLCLKEN_SHIFT (1U) +/*! APLLCLKEN - APLL Clock Enable + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLLCSR_APLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK) + +#define SCG_APLLCSR_APLLSTEN_MASK (0x4U) +#define SCG_APLLCSR_APLLSTEN_SHIFT (2U) +/*! APLLSTEN - APLL Stop Enable + * 0b0..APLL is disabled in Deep Sleep mode + * 0b1..APLL is enabled in Deep Sleep mode + */ +#define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) + +#define SCG_APLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_APLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_APLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_APLLCSR_APLLCM_MASK (0x10000U) +#define SCG_APLLCSR_APLLCM_SHIFT (16U) +/*! APLLCM - APLL Clock Monitor + * 0b0..APLL Clock Monitor is disabled + * 0b1..APLL Clock Monitor is enabled + */ +#define SCG_APLLCSR_APLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCM_SHIFT)) & SCG_APLLCSR_APLLCM_MASK) + +#define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) +#define SCG_APLLCSR_APLLCMRE_SHIFT (17U) +/*! APLLCMRE - APLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_APLLCSR_APLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK) + +#define SCG_APLLCSR_LK_MASK (0x800000U) +#define SCG_APLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_APLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK) + +#define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) +#define SCG_APLLCSR_APLL_LOCK_SHIFT (24U) +/*! APLL_LOCK - APLL LOCK + * 0b0..APLL is not powered on or not locked + * 0b1..APLL is locked + */ +#define SCG_APLLCSR_APLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK) + +#define SCG_APLLCSR_APLLSEL_MASK (0x2000000U) +#define SCG_APLLCSR_APLLSEL_SHIFT (25U) +/*! APLLSEL - APLL Selected + * 0b0..APLL is not the system clock source + * 0b1..APLL is the system clock source + */ +#define SCG_APLLCSR_APLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK) + +#define SCG_APLLCSR_APLLERR_MASK (0x4000000U) +#define SCG_APLLCSR_APLLERR_SHIFT (26U) +/*! APLLERR - APLL Clock Error + * 0b0..APLL Clock Monitor is disabled or has not detected an error + * 0b1..APLL Clock Monitor is enabled and detected an error + */ +#define SCG_APLLCSR_APLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLERR_SHIFT)) & SCG_APLLCSR_APLLERR_MASK) + +#define SCG_APLLCSR_APLL_LOCK_IE_MASK (0x40000000U) +#define SCG_APLLCSR_APLL_LOCK_IE_SHIFT (30U) +/*! APLL_LOCK_IE - APLL LOCK Interrupt Enable + * 0b0..APLL_LOCK interrupt is not enabled + * 0b1..APLL_LOCK interrupt is enabled + */ +#define SCG_APLLCSR_APLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_IE_SHIFT)) & SCG_APLLCSR_APLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name APLLCTRL - APLL Control Register */ +/*! @{ */ + +#define SCG_APLLCTRL_SELR_MASK (0xFU) +#define SCG_APLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_APLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELR_SHIFT)) & SCG_APLLCTRL_SELR_MASK) + +#define SCG_APLLCTRL_SELI_MASK (0x3F0U) +#define SCG_APLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_APLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELI_SHIFT)) & SCG_APLLCTRL_SELI_MASK) + +#define SCG_APLLCTRL_SELP_MASK (0x7C00U) +#define SCG_APLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_APLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELP_SHIFT)) & SCG_APLLCTRL_SELP_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_APLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_APLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_APLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_LIMUPOFF_SHIFT)) & SCG_APLLCTRL_LIMUPOFF_MASK) + +#define SCG_APLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_APLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_APLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BANDDIRECT_SHIFT)) & SCG_APLLCTRL_BANDDIRECT_MASK) + +#define SCG_APLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_APLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider + * 0b0..Use the predivider. + * 0b1..Bypass of the predivider. + */ +#define SCG_APLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider + * 0b0..Use the postdivider. + * 0b1..Bypass of the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_APLLCTRL_FRM_MASK (0x400000U) +#define SCG_APLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_APLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_FRM_SHIFT)) & SCG_APLLCTRL_FRM_MASK) + +#define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_APLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name APLLSTAT - APLL Status Register */ +/*! @{ */ + +#define SCG_APLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_APLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider(N) ratio change acknowledge. + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL + * 0b1..The predivider (N) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_NDIVACK_SHIFT)) & SCG_APLLSTAT_NDIVACK_MASK) + +#define SCG_APLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_APLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback(M) divider ratio change acknowledge. + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL + * 0b1..The feedback (M) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_MDIVACK_SHIFT)) & SCG_APLLSTAT_MDIVACK_MASK) + +#define SCG_APLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_APLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider(P) ratio change acknowledge. + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) + +#define SCG_APLLSTAT_FRMDET_MASK (0x10U) +#define SCG_APLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_APLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_FRMDET_SHIFT)) & SCG_APLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name APLLNDIV - APLL N Divider Register */ +/*! @{ */ + +#define SCG_APLLNDIV_NDIV_MASK (0xFFU) +#define SCG_APLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_APLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NDIV_SHIFT)) & SCG_APLLNDIV_NDIV_MASK) + +#define SCG_APLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_APLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_APLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NREQ_SHIFT)) & SCG_APLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name APLLMDIV - APLL M Divider Register */ +/*! @{ */ + +#define SCG_APLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_APLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_APLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MDIV_SHIFT)) & SCG_APLLMDIV_MDIV_MASK) + +#define SCG_APLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_APLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_APLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name APLLPDIV - APLL P Divider Register */ +/*! @{ */ + +#define SCG_APLLPDIV_PDIV_MASK (0x1FU) +#define SCG_APLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_APLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PDIV_SHIFT)) & SCG_APLLPDIV_PDIV_MASK) + +#define SCG_APLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_APLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_APLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PREQ_SHIFT)) & SCG_APLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name APLLLOCK_CNFG - APLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked. */ +#define SCG_APLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name APLLSSCGSTAT - APLL SSCG Status Register */ +/*! @{ */ + +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name APLLSSCG0 - APLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV */ +#define SCG_APLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name APLLSSCG1 - APLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_APLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_APLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_APLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_APLLSSCG1_MF_MASK (0x1CU) +#define SCG_APLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_APLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MF_SHIFT)) & SCG_APLLSSCG1_MF_MASK) + +#define SCG_APLLSSCG1_MR_MASK (0xE0U) +#define SCG_APLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_APLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MR_SHIFT)) & SCG_APLLSSCG1_MR_MASK) + +#define SCG_APLLSSCG1_MC_MASK (0x300U) +#define SCG_APLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_APLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MC_SHIFT)) & SCG_APLLSSCG1_MC_MASK) + +#define SCG_APLLSSCG1_DITHER_MASK (0x400U) +#define SCG_APLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_APLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_DITHER_SHIFT)) & SCG_APLLSSCG1_DITHER_MASK) + +#define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_APLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_APLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_APLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_APLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_PD_SHIFT)) & SCG_APLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name APLL_OVRD - APLL Override Register */ +/*! @{ */ + +#define SCG_APLL_OVRD_APLLPWREN_OVRD_MASK (0x1U) +#define SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT (0U) +/*! APLLPWREN_OVRD - APLL Power Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLL_OVRD_APLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLPWREN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK (0x2U) +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT (1U) +/*! APLLCLKEN_OVRD - APLL Clock Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLL_OVRD_APLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLL_OVRD_EN_MASK (0x80000000U) +#define SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT (31U) +/*! APLL_OVRD_EN - APLL Override Enable + * 0b0..APLL override is disabled + * 0b1..APLL override is enabled + */ +#define SCG_APLL_OVRD_APLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT)) & SCG_APLL_OVRD_APLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name SPLLCSR - SPLL Control Status Register */ +/*! @{ */ + +#define SCG_SPLLCSR_SPLLPWREN_MASK (0x1U) +#define SCG_SPLLCSR_SPLLPWREN_SHIFT (0U) +/*! SPLLPWREN - SPLL Power Enable + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLLCSR_SPLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK) + +#define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) +#define SCG_SPLLCSR_SPLLCLKEN_SHIFT (1U) +/*! SPLLCLKEN - SPLL Clock Enable + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLLCSR_SPLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK) + +#define SCG_SPLLCSR_SPLLSTEN_MASK (0x4U) +#define SCG_SPLLCSR_SPLLSTEN_SHIFT (2U) +/*! SPLLSTEN - SPLL Stop Enable + * 0b0..SPLL is disabled in Deep Sleep mode + * 0b1..SPLL is enabled in Deep Sleep mode + */ +#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) + +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) +#define SCG_SPLLCSR_SPLLCM_SHIFT (16U) +/*! SPLLCM - SPLL Clock Monitor + * 0b0..SPLL Clock Monitor is disabled + * 0b1..SPLL Clock Monitor is enabled + */ +#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) + +#define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) +#define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) +/*! SPLLCMRE - SPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) + +#define SCG_SPLLCSR_LK_MASK (0x800000U) +#define SCG_SPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_MASK (0x1000000U) +#define SCG_SPLLCSR_SPLL_LOCK_SHIFT (24U) +/*! SPLL_LOCK - SPLL LOCK + * 0b0..SPLL is not powered on or not locked + * 0b1..SPLL is locked + */ +#define SCG_SPLLCSR_SPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK) + +#define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) +#define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) +/*! SPLLSEL - SPLL Selected + * 0b0..SPLL is not the system clock source + * 0b1..SPLL is the system clock source + */ +#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) + +#define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) +#define SCG_SPLLCSR_SPLLERR_SHIFT (26U) +/*! SPLLERR - SPLL Clock Error + * 0b0..SPLL Clock Monitor is disabled or has not detected an error + * 0b1..SPLL Clock Monitor is enabled and detected an error + */ +#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_IE_MASK (0x40000000U) +#define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT (30U) +/*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable + * 0b0..SPLL_LOCK interrupt is not enabled + * 0b1..SPLL_LOCK interrupt is enabled + */ +#define SCG_SPLLCSR_SPLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name SPLLCTRL - SPLL Control Register */ +/*! @{ */ + +#define SCG_SPLLCTRL_SELR_MASK (0xFU) +#define SCG_SPLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_SPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK) + +#define SCG_SPLLCTRL_SELI_MASK (0x3F0U) +#define SCG_SPLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_SPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK) + +#define SCG_SPLLCTRL_SELP_MASK (0x7C00U) +#define SCG_SPLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_SPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider. + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_SPLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_SPLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter. + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_SPLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK) + +#define SCG_SPLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_SPLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_SPLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK) + +#define SCG_SPLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider. + * 0b0..Use the predivider + * 0b1..Bypass of the predivider + */ +#define SCG_SPLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider. + * 0b0..Use the postdivider + * 0b1..Bypass of the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_SPLLCTRL_FRM_MASK (0x400000U) +#define SCG_SPLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) + +#define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_SPLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name SPLLSTAT - SPLL Status Register */ +/*! @{ */ + +#define SCG_SPLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_SPLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider (N) ratio change acknowledge + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL. + * 0b1..The predivider (N) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK) + +#define SCG_SPLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_SPLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback (M) divider ratio change acknowledge + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL. + * 0b1..The feedback (M) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK) + +#define SCG_SPLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_SPLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider (P) ratio change acknowledge + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) + +#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) +#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name SPLLNDIV - SPLL N Divider Register */ +/*! @{ */ + +#define SCG_SPLLNDIV_NDIV_MASK (0xFFU) +#define SCG_SPLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_SPLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK) + +#define SCG_SPLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_SPLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_SPLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name SPLLMDIV - SPLL M Divider Register */ +/*! @{ */ + +#define SCG_SPLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_SPLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_SPLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK) + +#define SCG_SPLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_SPLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_SPLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name SPLLPDIV - SPLL P Divider Register */ +/*! @{ */ + +#define SCG_SPLLPDIV_PDIV_MASK (0x1FU) +#define SCG_SPLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_SPLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK) + +#define SCG_SPLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_SPLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_SPLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */ +#define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name SPLLSSCGSTAT - SPLL SSCG Status Register */ +/*! @{ */ + +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV[31:0] */ +#define SCG_SPLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_SPLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_SPLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_SPLLSSCG1_MF_MASK (0x1CU) +#define SCG_SPLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_SPLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK) + +#define SCG_SPLLSSCG1_MR_MASK (0xE0U) +#define SCG_SPLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_SPLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK) + +#define SCG_SPLLSSCG1_MC_MASK (0x300U) +#define SCG_SPLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_SPLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK) + +#define SCG_SPLLSSCG1_DITHER_MASK (0x400U) +#define SCG_SPLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_SPLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK) + +#define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_SPLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_SPLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_SPLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_SPLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name SPLL_OVRD - SPLL Override Register */ +/*! @{ */ + +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK (0x1U) +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT (0U) +/*! SPLLPWREN_OVRD - SPLL Power Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK (0x2U) +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT (1U) +/*! SPLLCLKEN_OVRD - SPLL Clock Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK (0x80000000U) +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT (31U) +/*! SPLL_OVRD_EN - SPLL Override Enable + * 0b0..SPLL override is disabled + * 0b1..SPLL override is enabled + */ +#define SCG_SPLL_OVRD_SPLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT)) & SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name UPLLCSR - UPLL Control Status Register */ +/*! @{ */ + +#define SCG_UPLLCSR_UPLLCM_MASK (0x10000U) +#define SCG_UPLLCSR_UPLLCM_SHIFT (16U) +/*! UPLLCM - UPLL Clock Monitor + * 0b0..UPLL Clock Monitor is disabled + * 0b1..UPLL Clock Monitor is enabled + */ +#define SCG_UPLLCSR_UPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCM_SHIFT)) & SCG_UPLLCSR_UPLLCM_MASK) + +#define SCG_UPLLCSR_UPLLCMRE_MASK (0x20000U) +#define SCG_UPLLCSR_UPLLCMRE_SHIFT (17U) +/*! UPLLCMRE - UPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_UPLLCSR_UPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCMRE_SHIFT)) & SCG_UPLLCSR_UPLLCMRE_MASK) + +#define SCG_UPLLCSR_LK_MASK (0x800000U) +#define SCG_UPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_UPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_LK_SHIFT)) & SCG_UPLLCSR_LK_MASK) + +#define SCG_UPLLCSR_UPLLVLD_MASK (0x1000000U) +#define SCG_UPLLCSR_UPLLVLD_SHIFT (24U) +/*! UPLLVLD - UPLL Valid + * 0b0..UPLL is not enabled or clock is not valid + * 0b1..UPLL is enabled and output clock is valid + */ +#define SCG_UPLLCSR_UPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVLD_SHIFT)) & SCG_UPLLCSR_UPLLVLD_MASK) + +#define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) +#define SCG_UPLLCSR_UPLLSEL_SHIFT (25U) +/*! UPLLSEL - UPLL Selected + * 0b0..UPLL is not the system clock source + * 0b1..UPLL is the system clock source + */ +#define SCG_UPLLCSR_UPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK) + +#define SCG_UPLLCSR_UPLLERR_MASK (0x4000000U) +#define SCG_UPLLCSR_UPLLERR_SHIFT (26U) +/*! UPLLERR - UPLL Clock Error + * 0b0..UPLL Clock Monitor is disabled or has not detected an error + * 0b1..UPLL Clock Monitor is enabled and detected an error + */ +#define SCG_UPLLCSR_UPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLERR_SHIFT)) & SCG_UPLLCSR_UPLLERR_MASK) + +#define SCG_UPLLCSR_UPLLVOR_MASK (0x40000000U) +#define SCG_UPLLCSR_UPLLVOR_SHIFT (30U) +/*! UPLLVOR - USB PLL Valid Flag Override Value + * 0b0..Override to 0b + * 0b1..Override to 1b + */ +#define SCG_UPLLCSR_UPLLVOR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVOR_SHIFT)) & SCG_UPLLCSR_UPLLVOR_MASK) + +#define SCG_UPLLCSR_UPLLVORE_MASK (0x80000000U) +#define SCG_UPLLCSR_UPLLVORE_SHIFT (31U) +/*! UPLLVORE - USB PLL Valid Flag Override Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SCG_UPLLCSR_UPLLVORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVORE_SHIFT)) & SCG_UPLLCSR_UPLLVORE_MASK) +/*! @} */ + +/*! @name LDOCSR - LDO Control and Status Register */ +/*! @{ */ + +#define SCG_LDOCSR_LDOEN_MASK (0x1U) +#define SCG_LDOCSR_LDOEN_SHIFT (0U) +/*! LDOEN - LDO Enable + * 0b0..LDO is disabled + * 0b1..LDO is enabled + */ +#define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) + +#define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) +#define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) +/*! VOUT_SEL - LDO output voltage select + * 0b000..VOUT = 1V + * 0b001..VOUT = 1V + * 0b010..VOUT = 1V + * 0b011..VOUT = 1.05V + * 0b100..VOUT = 1.1V + * 0b101..VOUT = 1.15V + * 0b110..VOUT = 1.2V + * 0b111..VOUT = 1.25V + */ +#define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) + +#define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) +#define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) +/*! LDOBYPASS - LDO Bypass + * 0b0..LDO is not bypassed + * 0b1..LDO is bypassed + */ +#define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) + +#define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) +#define SCG_LDOCSR_VOUT_OK_SHIFT (31U) +/*! VOUT_OK - LDO VOUT OK Inform. + * 0b0..LDO output VOUT is not OK + * 0b1..LDO output VOUT is OK + */ +#define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) +/*! @} */ + +/*! @name TROCSR - TRO Control Status Register */ +/*! @{ */ + +#define SCG_TROCSR_TROCM_MASK (0x10000U) +#define SCG_TROCSR_TROCM_SHIFT (16U) +/*! TROCM - TRO Clock Monitor + * 0b0..TRO Clock Monitor is disabled + * 0b1..TRO Clock Monitor is enabled + */ +#define SCG_TROCSR_TROCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCM_SHIFT)) & SCG_TROCSR_TROCM_MASK) + +#define SCG_TROCSR_TROCMRE_MASK (0x20000U) +#define SCG_TROCSR_TROCMRE_SHIFT (17U) +/*! TROCMRE - TRO Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_TROCSR_TROCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCMRE_SHIFT)) & SCG_TROCSR_TROCMRE_MASK) + +#define SCG_TROCSR_TRO_REFCLK_SEL_MASK (0xC0000U) +#define SCG_TROCSR_TRO_REFCLK_SEL_SHIFT (18U) +/*! TRO_REFCLK_SEL - TRO reference clock selection + * 0b00..SOSC + * 0b01..SIRC + * 0b10..FIRC (144 MHz or 48 MHz, based on RANGE selection) + * 0b11..Reserved + */ +#define SCG_TROCSR_TRO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TRO_REFCLK_SEL_SHIFT)) & SCG_TROCSR_TRO_REFCLK_SEL_MASK) + +#define SCG_TROCSR_LK_MASK (0x800000U) +#define SCG_TROCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_TROCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_LK_SHIFT)) & SCG_TROCSR_LK_MASK) + +#define SCG_TROCSR_TROVLD_MASK (0x1000000U) +#define SCG_TROCSR_TROVLD_SHIFT (24U) +/*! TROVLD - TRO Valid + * 0b0..TRO is not enabled or clock is not valid + * 0b1..TRO is enabled and output clock is valid + */ +#define SCG_TROCSR_TROVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROVLD_SHIFT)) & SCG_TROCSR_TROVLD_MASK) + +#define SCG_TROCSR_TROSEL_MASK (0x2000000U) +#define SCG_TROCSR_TROSEL_SHIFT (25U) +/*! TROSEL - TRO Selected + * 0b0..TRO is not the system clock source + * 0b1..TRO is the system clock source + */ +#define SCG_TROCSR_TROSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROSEL_SHIFT)) & SCG_TROCSR_TROSEL_MASK) + +#define SCG_TROCSR_TROERR_MASK (0x4000000U) +#define SCG_TROCSR_TROERR_SHIFT (26U) +/*! TROERR - TRO Clock Error + * 0b0..TRO clock monitor is disabled or has not detected an error + * 0b1..TRO clock monitor is enabled and detected an error + */ +#define SCG_TROCSR_TROERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROERR_SHIFT)) & SCG_TROCSR_TROERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer + * @{ + */ + +/** SMARTDMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ + __IO uint32_t CTRL; /**< Control, offset: 0x24 */ + __I uint32_t PC; /**< Program Counter, offset: 0x28 */ + __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ + __IO uint32_t BREAK_ADDR; /**< Breakpoint Address, offset: 0x30 */ + __IO uint32_t BREAK_VECT; /**< Breakpoint Vector, offset: 0x34 */ + __IO uint32_t EMER_VECT; /**< Emergency Vector, offset: 0x38 */ + __IO uint32_t EMER_SEL; /**< Emergency Select, offset: 0x3C */ + __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ + __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ + __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ +} SMARTDMA_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks + * @{ + */ + +/*! @name BOOTADR - Boot Address */ +/*! @{ */ + +#define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ +#define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define SMARTDMA_CTRL_START_MASK (0x1U) +#define SMARTDMA_CTRL_START_SHIFT (0U) +/*! START - Start Bit Ignition */ +#define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) + +#define SMARTDMA_CTRL_EXF_MASK (0x2U) +#define SMARTDMA_CTRL_EXF_SHIFT (1U) +/*! EXF - External Flag */ +#define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) + +#define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) +#define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) +/*! ERRDIS - Error Disable */ +#define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) + +#define SMARTDMA_CTRL_BUFEN_MASK (0x8U) +#define SMARTDMA_CTRL_BUFEN_SHIFT (3U) +/*! BUFEN - Buffer Enable */ +#define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) + +#define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) +#define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) +/*! SYNCEN - Sync Enable */ +#define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) + +#define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) +#define SMARTDMA_CTRL_WKEY_SHIFT (16U) +/*! WKEY - Write Key */ +#define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) +/*! @} */ + +/*! @name PC - Program Counter */ +/*! @{ */ + +#define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) +#define SMARTDMA_PC_PC_SHIFT (0U) +/*! PC - Program Counter */ +#define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) +/*! @} */ + +/*! @name SP - Stack Pointer */ +/*! @{ */ + +#define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) +#define SMARTDMA_SP_SP_SHIFT (0U) +/*! SP - Stack Pointer */ +#define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) +/*! @} */ + +/*! @name BREAK_ADDR - Breakpoint Address */ +/*! @{ */ + +#define SMARTDMA_BREAK_ADDR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_ADDR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit address to swap to EZHB_BREAK_VECT location */ +#define SMARTDMA_BREAK_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_ADDR_ADDR_SHIFT)) & SMARTDMA_BREAK_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name BREAK_VECT - Breakpoint Vector */ +/*! @{ */ + +#define SMARTDMA_BREAK_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of user debug routine. */ +#define SMARTDMA_BREAK_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_VECT_VEC_SHIFT)) & SMARTDMA_BREAK_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_VECT - Emergency Vector */ +/*! @{ */ + +#define SMARTDMA_EMER_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_EMER_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of emergency code routine */ +#define SMARTDMA_EMER_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_VECT_VEC_SHIFT)) & SMARTDMA_EMER_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_SEL - Emergency Select */ +/*! @{ */ + +#define SMARTDMA_EMER_SEL_EN_MASK (0x100U) +#define SMARTDMA_EMER_SEL_EN_SHIFT (8U) +/*! EN - Emergency code routine */ +#define SMARTDMA_EMER_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_EN_SHIFT)) & SMARTDMA_EMER_SEL_EN_MASK) + +#define SMARTDMA_EMER_SEL_RQ_MASK (0x200U) +#define SMARTDMA_EMER_SEL_RQ_SHIFT (9U) +/*! RQ - Software emergency request */ +#define SMARTDMA_EMER_SEL_RQ(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_RQ_SHIFT)) & SMARTDMA_EMER_SEL_RQ_MASK) +/*! @} */ + +/*! @name ARM2EZH - ARM to EZH Interrupt Control */ +/*! @{ */ + +#define SMARTDMA_ARM2EZH_IE_MASK (0x3U) +#define SMARTDMA_ARM2EZH_IE_SHIFT (0U) +/*! IE - Interrupt Enable */ +#define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) + +#define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) +#define SMARTDMA_ARM2EZH_GP_SHIFT (2U) +/*! GP - General purpose register bits */ +#define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) +/*! @} */ + +/*! @name EZH2ARM - EZH to ARM Trigger */ +/*! @{ */ + +#define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) +#define SMARTDMA_EZH2ARM_GP_SHIFT (0U) +/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ +#define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) +/*! @} */ + +/*! @name PENDTRAP - Pending Trap Control */ +/*! @{ */ + +#define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) +#define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) +/*! STATUS - Status Flag or Pending Trap Request */ +#define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) + +#define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) +#define SMARTDMA_PENDTRAP_POL_SHIFT (8U) +/*! POL - Polarity */ +#define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) + +#define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) +#define SMARTDMA_PENDTRAP_EN_SHIFT (16U) +/*! EN - Enable Pending Trap */ +#define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SMARTDMA_Register_Masks */ + + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/*! + * @} + */ /* end of group SMARTDMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[2]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[188]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + uint8_t RESERVED_5[16]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ + uint8_t RESERVED_7[440]; + __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ + uint8_t RESERVED_8[252]; + __IO uint32_t SYSLDO_CFG; /**< LDO_SYS Configuration, offset: 0x400 */ + uint8_t RESERVED_9[252]; + __IO uint32_t DCDC_CFG; /**< DCDC Configuration, offset: 0x500 */ + __IO uint32_t DCDC_BURST_CFG; /**< DCDC Burst Configuration, offset: 0x504 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + * *.. + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000..Sleep mode with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x30000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name CNTRL - SPC Regulator Control */ +/*! @{ */ + +#define SPC_CNTRL_CORELDO_EN_MASK (0x1U) +#define SPC_CNTRL_CORELDO_EN_SHIFT (0U) +/*! CORELDO_EN - LDO_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) + +#define SPC_CNTRL_SYSLDO_EN_MASK (0x2U) +#define SPC_CNTRL_SYSLDO_EN_SHIFT (1U) +/*! SYSLDO_EN - LDO_SYS Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_SYSLDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK) + +#define SPC_CNTRL_DCDC_EN_MASK (0x4U) +#define SPC_CNTRL_DCDC_EN_SHIFT (2U) +/*! DCDC_EN - DCDC_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_DCDC_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U) +#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U) +/*! PWR_REQ_STATUS - Power Request Status Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000..SLEEP with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/* The count of SPC_PD_STATUS */ +#define SPC_PD_STATUS_COUNT (2U) + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1.0 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Reserved + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK (0x40U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT (6U) +/*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level + * 0b0..Normal voltage (1.8 V) + * 0b1..Overdrive voltage (2.5 V) + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b01..Low + * 0b10..Normal + * *.. + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Reserved + * 0b01..Midvoltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled + */ +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U) +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U) +/*! VDD_VD_DISABLE - VDD Voltage Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_ACTIVE_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK) + +#define SPC_ACTIVE_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_ACTIVE_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Retention voltage + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_LP_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b00..Pulse refresh + * 0b01..Low + * 0b10..Normal + * 0b11.. + */ +#define SPC_LP_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Retention voltage (0.7 V) + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_LP_CFG_COREVDD_IVS_EN_MASK (0x20000U) +#define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT (17U) +/*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_COREVDD_IVS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK) + +#define SPC_LP_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_LP_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_LP_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK) + +#define SPC_LP_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_LP_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) + +#define SPC_LP_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_LP_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_IOVDD_LVDF_MASK (0x4U) +#define SPC_VD_STAT_IOVDD_LVDF_SHIFT (2U) +/*! IOVDD_LVDF - IO VDD LVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK) + +#define SPC_VD_STAT_COREVDD_HVDF_MASK (0x10U) +#define SPC_VD_STAT_COREVDD_HVDF_SHIFT (4U) +/*! COREVDD_HVDF - Core VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) + +#define SPC_VD_STAT_IOVDD_HVDF_MASK (0x40U) +#define SPC_VD_STAT_IOVDD_HVDF_SHIFT (6U) +/*! IOVDD_HVDF - IO VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_CORE_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - Core VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK) + +#define SPC_VD_CORE_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_CORE_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - Core VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_IO_CFG - IO Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_IO_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_IO_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - IO VDD LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK) + +#define SPC_VD_IO_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_IO_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - IO VDD LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK) + +#define SPC_VD_IO_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_IO_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - IO VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK) + +#define SPC_VD_IO_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_IO_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - IO VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK) + +#define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - IO VDD Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) + +#define SPC_VD_IO_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_IO_CFG_LOCK_SHIFT (16U) +/*! LOCK - IO Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_IO_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0x3FU) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0x3F00U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0x3F0000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ +/*! @{ */ + +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +/*! CNT_SELECT - Counter Select + * 0b00..0 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) + +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +/*! TIMEOUT - Timeout */ +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) + +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset + */ +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) + +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt + */ +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) + +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) + +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit + * 0b0..Writes to RE are allowed. + * 0b1..Writes to RE are ignored. + */ +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) +/*! @} */ + +/*! @name CORELDO_CFG - LDO_CORE Configuration */ +/*! @{ */ + +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U) +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U) +/*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable + * 0b0..LDO_CORE pulldown in Deep Power Down not disabled + * 0b1..LDO_CORE pulldown in Deep Power Down disabled + */ +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK) +/*! @} */ + +/*! @name SYSLDO_CFG - LDO_SYS Configuration */ +/*! @{ */ + +#define SPC_SYSLDO_CFG_ISINKEN_MASK (0x1U) +#define SPC_SYSLDO_CFG_ISINKEN_SHIFT (0U) +/*! ISINKEN - Current Sink Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SYSLDO_CFG_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK) +/*! @} */ + +/*! @name DCDC_CFG - DCDC Configuration */ +/*! @{ */ + +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK (0x1U) +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT (0U) +/*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_CFG_FREQ_CNTRL_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK) + +#define SPC_DCDC_CFG_FREQ_CNTRL_MASK (0x3F00U) +#define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT (8U) +/*! FREQ_CNTRL - DCDC Burst Frequency Control */ +#define SPC_DCDC_CFG_FREQ_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK) + +#define SPC_DCDC_CFG_BLEED_EN_MASK (0x80000U) +#define SPC_DCDC_CFG_BLEED_EN_SHIFT (19U) +/*! BLEED_EN - DCDC Bleed Enable + * 0b0..Do not add + * 0b1..Add + */ +#define SPC_DCDC_CFG_BLEED_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_BLEED_EN_SHIFT)) & SPC_DCDC_CFG_BLEED_EN_MASK) +/*! @} */ + +/*! @name DCDC_BURST_CFG - DCDC Burst Configuration */ +/*! @{ */ + +#define SPC_DCDC_BURST_CFG_BURST_REQ_MASK (0x1U) +#define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT (0U) +/*! BURST_REQ - Software Burst Request + * 0b0..Do not generate + * 0b1..Generate + */ +#define SPC_DCDC_BURST_CFG_BURST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK) + +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK (0x2U) +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT (1U) +/*! EXT_BURST_EN - External Burst Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK) + +#define SPC_DCDC_BURST_CFG_BURST_ACK_MASK (0x8U) +#define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT (3U) +/*! BURST_ACK - Burst Acknowledge Flag + * 0b0..Did not complete + * 0b1..Completed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_DCDC_BURST_CFG_BURST_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) + +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U) +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U) +/*! PULSE_REFRESH_CNT - Refresh Count Value */ +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< Secure CPU0 System Tick Calibration, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + __IO uint32_t PRESETCTRL0; /**< Peripheral Reset Control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral Reset Control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral Reset Control 2, offset: 0x108 */ + __IO uint32_t PRESETCTRL3; /**< Peripheral Reset Control 3, offset: 0x10C */ + uint8_t RESERVED_4[16]; + __O uint32_t PRESETCTRLSET[4]; /**< Peripheral Reset Control Set, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral Reset Control Clear, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[176]; + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock Control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock Control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock Control 2, offset: 0x208 */ + __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ + uint8_t RESERVED_7[16]; + __O uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __O uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_9[16]; + __IO uint32_t SYSTICKCLKSEL0; /**< CPU0 System Tick Timer Source Select, offset: 0x260 */ + uint8_t RESERVED_10[4]; + __IO uint32_t TRACECLKSEL; /**< Trace Clock Source Select, offset: 0x268 */ + __IO uint32_t CTIMERCLKSEL[5]; /**< CTIMER Clock Source Select, array offset: 0x26C, array step: 0x4 */ + uint8_t RESERVED_11[8]; + __IO uint32_t CLKOUTSEL; /**< CLKOUT Clock Source Select, offset: 0x288 */ + uint8_t RESERVED_12[24]; + __IO uint32_t ADC0CLKSEL; /**< ADC0 Clock Source Select, offset: 0x2A4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t FCCLKSEL[8]; /**< LP_FLEXCOMM Clock Source Select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_14[48]; + __IO uint32_t SYSTICKCLKDIV[1]; /**< CPU0 System Tick Timer Divider, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_15[4]; + __IO uint32_t TRACECLKDIV; /**< TRACE Clock Divider, offset: 0x308 */ + uint8_t RESERVED_16[108]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + uint8_t RESERVED_17[4]; + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT Clock Divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ + __IO uint32_t WDT0CLKDIV; /**< WDT0 Clock Divider, offset: 0x38C */ + uint8_t RESERVED_18[4]; + __IO uint32_t ADC0CLKDIV; /**< ADC0 Clock Divider, offset: 0x394 */ + uint8_t RESERVED_19[44]; + __IO uint32_t PLLCLKDIV; /**< PLL Clock Divider, offset: 0x3C4 */ + uint8_t RESERVED_20[8]; + __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer Clock Divider, array offset: 0x3D0, array step: 0x4 */ + __IO uint32_t PLL1CLK0DIV; /**< PLL1 Clock 0 Divider, offset: 0x3E4 */ + __IO uint32_t PLL1CLK1DIV; /**< PLL1 Clock 1 Divider, offset: 0x3E8 */ + uint8_t RESERVED_21[4]; + __IO uint32_t UTICKCLKDIV; /**< UTICK Clock Divider, offset: 0x3F0 */ + __IO uint32_t CLKOUT_FRGCTRL; /**< CLKOUT FRG Control, offset: 0x3F4 */ + uint8_t RESERVED_22[4]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + __IO uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */ + uint8_t RESERVED_23[12]; + __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ + uint8_t RESERVED_24[76]; + __IO uint32_t ADC1CLKSEL; /**< ADC1 Clock Source Select, offset: 0x464 */ + __IO uint32_t ADC1CLKDIV; /**< ADC1 Clock Divider, offset: 0x468 */ + uint8_t RESERVED_25[4]; + __IO uint32_t RAM_INTERLEAVE; /**< Control PKC RAM Interleave Access, offset: 0x470 */ + uint8_t RESERVED_26[184]; + __IO uint32_t PLLCLKDIVSEL; /**< PLL Clock Divider Clock Selection, offset: 0x52C */ + __IO uint32_t I3C0FCLKSEL; /**< I3C0 Functional Clock Selection, offset: 0x530 */ + uint8_t RESERVED_27[12]; + __IO uint32_t I3C0FCLKDIV; /**< I3C0 Functional Clock FCLK Divider, offset: 0x540 */ + uint8_t RESERVED_28[4]; + __IO uint32_t MICFILFCLKSEL; /**< MICFIL Clock Selection, offset: 0x548 */ + __IO uint32_t MICFILFCLKDIV; /**< MICFIL Clock Division, offset: 0x54C */ + uint8_t RESERVED_29[16]; + __IO uint32_t FLEXIOCLKSEL; /**< FLEXIO Clock Selection, offset: 0x560 */ + __IO uint32_t FLEXIOCLKDIV; /**< FLEXIO Function Clock Divider, offset: 0x564 */ + uint8_t RESERVED_30[56]; + __IO uint32_t FLEXCAN0CLKSEL; /**< FLEXCAN0 Clock Selection, offset: 0x5A0 */ + __IO uint32_t FLEXCAN0CLKDIV; /**< FLEXCAN0 Function Clock Divider, offset: 0x5A4 */ + __IO uint32_t FLEXCAN1CLKSEL; /**< FLEXCAN1 Clock Selection, offset: 0x5A8 */ + __IO uint32_t FLEXCAN1CLKDIV; /**< FLEXCAN1 Function Clock Divider, offset: 0x5AC */ + uint8_t RESERVED_31[36]; + __IO uint32_t EWM0CLKSEL; /**< EWM0 Clock Selection, offset: 0x5D4 */ + __IO uint32_t WDT1CLKSEL; /**< WDT1 Clock Selection, offset: 0x5D8 */ + __IO uint32_t WDT1CLKDIV; /**< WDT1 Function Clock Divider, offset: 0x5DC */ + __IO uint32_t OSTIMERCLKSEL; /**< OSTIMER Clock Selection, offset: 0x5E0 */ + uint8_t RESERVED_32[12]; + __IO uint32_t CMP0FCLKSEL; /**< CMP0 Function Clock Selection, offset: 0x5F0 */ + __IO uint32_t CMP0FCLKDIV; /**< CMP0 Function Clock Divider, offset: 0x5F4 */ + __IO uint32_t CMP0RRCLKSEL; /**< CMP0 Round Robin Clock Selection, offset: 0x5F8 */ + __IO uint32_t CMP0RRCLKDIV; /**< CMP0 Round Robin Clock Divider, offset: 0x5FC */ + __IO uint32_t CMP1FCLKSEL; /**< CMP1 Function Clock Selection, offset: 0x600 */ + __IO uint32_t CMP1FCLKDIV; /**< CMP1 Function Clock Divider, offset: 0x604 */ + __IO uint32_t CMP1RRCLKSEL; /**< CMP1 Round Robin Clock Source Select, offset: 0x608 */ + __IO uint32_t CMP1RRCLKDIV; /**< CMP1 Round Robin Clock Division, offset: 0x60C */ + uint8_t RESERVED_33[508]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_35[40]; + __IO uint32_t FLEXCOMMCLKDIV[8]; /**< LP_FLEXCOMM Clock Divider, array offset: 0x850, array step: 0x4 */ + uint8_t RESERVED_36[8]; + __IO uint32_t UTICKCLKSEL; /**< UTICK Function Clock Source Select, offset: 0x878 */ + uint8_t RESERVED_37[4]; + __IO uint32_t SAI0CLKSEL; /**< SAI0 Function Clock Source Select, offset: 0x880 */ + __IO uint32_t SAI1CLKSEL; /**< SAI1 Function Clock Source Select, offset: 0x884 */ + __IO uint32_t SAI0CLKDIV; /**< SAI0 Function Clock Division, offset: 0x888 */ + __IO uint32_t SAI1CLKDIV; /**< SAI1 Function Clock Division, offset: 0x88C */ + uint8_t RESERVED_38[192]; + __IO uint32_t KEY_RETAIN_CTRL; /**< Key Retain Control, offset: 0x950 */ + uint8_t RESERVED_39[12]; + __IO uint32_t REF_CLK_CTRL; /**< FRO 48MHz Reference Clock Control, offset: 0x960 */ + __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ + __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ + __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ + __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ + __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ + __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ + __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ + __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ + uint8_t RESERVED_40[64]; + __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ + __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ + __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ + __I uint32_t ELS_AS_CFG3; /**< ELS AS Configuration3, offset: 0x9DC */ + __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ + __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ + __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ + __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ + __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ + __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ + __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ + __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ + uint8_t RESERVED_41[24]; + __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ + uint8_t RESERVED_42[276]; + __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ + uint8_t RESERVED_43[12]; + __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ + uint8_t RESERVED_44[28]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray code_gray[31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_45[660]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ + uint8_t RESERVED_46[36]; + __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ + uint8_t RESERVED_47[8]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ + __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ + uint8_t RESERVED_48[344]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_49[8]; + __IO uint32_t SWD_ACCESS_CPU[1]; /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ + uint8_t RESERVED_50[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_51[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) + +#define SYSCON_AHBMATPRIO_DMA1_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_DMA1_SHIFT (10U) +/*! DMA1 - DMA1 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA1_SHIFT)) & SYSCON_AHBMATPRIO_DMA1_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT (12U) +/*! PRI_PKC_ELS - PKC and ELS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC000000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (26U) +/*! PRI_USB_HS - USB-HS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b1..Enable. + * 0b0..Disable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_FMU_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL0_FMU_RST_SHIFT (9U) +/*! FMU_RST - Flash management unit reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_FMU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMU_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMU_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (12U) +/*! MUX_RST - INPUTMUX reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT0_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_PORT0_RST_SHIFT (13U) +/*! PORT0_RST - PORT0 controller reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT0_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT0_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT1_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_PORT1_RST_SHIFT (14U) +/*! PORT1_RST - PORT1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT1_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT1_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT2_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_PORT2_RST_SHIFT (15U) +/*! PORT2_RST - PORT2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT2_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT2_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT3_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_PORT3_RST_SHIFT (16U) +/*! PORT3_RST - PORT3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT3_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT4_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_PORT4_RST_SHIFT (17U) +/*! PORT4_RST - PORT4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT4_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT4_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (19U) +/*! GPIO0_RST - GPIO0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (20U) +/*! GPIO1_RST - GPIO1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (21U) +/*! GPIO2_RST - GPIO2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (22U) +/*! GPIO3_RST - GPIO3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO4_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT (23U) +/*! GPIO4_RST - GPIO4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO4_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (25U) +/*! PINT_RST - PINT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (26U) +/*! DMA0_RST - DMA0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_CRC_RST_SHIFT (27U) +/*! CRC_RST - CRC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC0_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL1_ADC0_RST_SHIFT (3U) +/*! ADC0_RST - ADC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC1_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL1_ADC1_RST_SHIFT (4U) +/*! ADC1_RST - ADC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_RTC_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_RTC_RST_SHIFT (6U) +/*! RTC_RST - RTC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL1_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - LP_FLEXCOMM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - LP_FLEXCOMM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - LP_FLEXCOMM2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - LP_FLEXCOMM3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - LP_FLEXCOMM4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - LP_FLEXCOMM5 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - LP_FLEXCOMM6 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - LP_FLEXCOMM7 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_MICFIL_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT (21U) +/*! MICFIL_RST - MICFIL reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MICFIL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT)) & SYSCON_PRESETCTRL1_MICFIL_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - CTIMER2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - CTIMER0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - CTIMER1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) + +#define SYSCON_PRESETCTRL1_SmartDMA_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT (31U) +/*! SmartDMA_RST - SmartDMA reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_SmartDMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT)) & SYSCON_PRESETCTRL1_SmartDMA_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral Reset Control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXIO_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT (4U) +/*! FLEXIO_RST - FLEXIO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI0_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_SAI0_RST_SHIFT (5U) +/*! SAI0_RST - SAI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI0_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI0_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI1_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_SAI1_RST_SHIFT (6U) +/*! SAI1_RST - SAI1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI1_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI1_RST_MASK) + +#define SYSCON_PRESETCTRL2_TRO_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_TRO_RST_SHIFT (7U) +/*! TRO_RST - TRO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TRO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRO_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRO_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - FREQME reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT (14U) +/*! FLEXCAN0_RST - CAN0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT (15U) +/*! FLEXCAN1_RST - CAN1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT (16U) +/*! USB_HS_RST - USB HS reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT (17U) +/*! USB_HS_PHY_RST - USB HS PHY reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - CTIMER3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - CTIMER4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) +/*! PKC_RST - PKC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL3 - Peripheral Reset Control 3 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) +/*! I3C0_RST - I3C0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) + +#define SYSCON_PRESETCTRL3_I3C1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL3_I3C1_RST_SHIFT (1U) +/*! I3C1_RST - I3C1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C1_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C1_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) +/*! QDC0_RST - QDC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) +/*! QDC1_RST - QDC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) +/*! PWM0_RST - PWM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (7U) +/*! PWM1_RST - PWM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) + +#define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (8U) +/*! AOI0_RST - AOI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) + +#define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (19U) +/*! VREF_RST - VREF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) + +#define SYSCON_PRESETCTRL3_EWM_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL3_EWM_RST_SHIFT (23U) +/*! EWM_RST - EWM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EWM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EWM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EWM_RST_MASK) + +#define SYSCON_PRESETCTRL3_EIM_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL3_EIM_RST_SHIFT (24U) +/*! EIM_RST - EIM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EIM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EIM_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLSET - Peripheral Reset Control Set */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (4U) + +/*! @name PRESETCTRLCLR - Peripheral Reset Control Clear */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (4U) + +/*! @name AHBCLKCTRL0 - AHB Clock Control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Enables the clock for the RAMB Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Enables the clock for the RAMC Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Enables the clock for the RAMD Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Enables the clock for the RAME Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_FMU_MASK (0x200U) +#define SYSCON_AHBCLKCTRL0_FMU_SHIFT (9U) +/*! FMU - Enables the clock for the Flash Management Unit + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMU_SHIFT)) & SYSCON_AHBCLKCTRL0_FMU_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x400U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (10U) +/*! FMC - Enables the clock for the Flash Memory Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (12U) +/*! MUX - Enables the clock for INPUTMUX + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT0_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_PORT0_SHIFT (13U) +/*! PORT0 - Enables the clock for PORT0 controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT0_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT0_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_PORT1_SHIFT (14U) +/*! PORT1 - Enables the clock for PORT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT1_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT1_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT2_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_PORT2_SHIFT (15U) +/*! PORT2 - Enables the clock for PORT2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT2_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT2_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT3_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_PORT3_SHIFT (16U) +/*! PORT3 - Enables the clock for PORT3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT3_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT3_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT4_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_PORT4_SHIFT (17U) +/*! PORT4 - Enables the clock for PORT4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT4_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT4_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (19U) +/*! GPIO0 - Enables the clock for GPIO0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (20U) +/*! GPIO1 - Enables the clock for GPIO1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (21U) +/*! GPIO2 - Enables the clock for GPIO2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (22U) +/*! GPIO3 - Enables the clock for GPIO3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO4_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_GPIO4_SHIFT (23U) +/*! GPIO4 - Enables the clock for GPIO4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO4_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (25U) +/*! PINT - Enables the clock for PINT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (26U) +/*! DMA0 - Enables the clock for DMA0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_CRC_SHIFT (27U) +/*! CRC - Enables the clock for CRC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRC_SHIFT)) & SYSCON_AHBCLKCTRL0_CRC_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT0_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL0_WWDT0_SHIFT (28U) +/*! WWDT0 - Enables the clock for WWDT0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT0_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT0_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT1_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL0_WWDT1_SHIFT (29U) +/*! WWDT1 - Enables the clock for WWDT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT1_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock Control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for MRT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC0_MASK (0x8U) +#define SYSCON_AHBCLKCTRL1_ADC0_SHIFT (3U) +/*! ADC0 - Enables the clock for ADC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC0_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC1_MASK (0x10U) +#define SYSCON_AHBCLKCTRL1_ADC1_SHIFT (4U) +/*! ADC1 - Enables the clock for ADC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC1_MASK) + +#define SYSCON_AHBCLKCTRL1_RTC_MASK (0x40U) +#define SYSCON_AHBCLKCTRL1_RTC_SHIFT (6U) +/*! RTC - Enables the clock for RTC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_RTC_SHIFT)) & SYSCON_AHBCLKCTRL1_RTC_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for UTICK + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for LP_FLEXCOMM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for LP_FLEXCOMM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for LP_FLEXCOMM2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for LP_FLEXCOMM3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for LP_FLEXCOMM4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for LP_FLEXCOMM5 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for LP_FLEXCOMM6 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for LP_FLEXCOMM7 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_MICFIL_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL1_MICFIL_SHIFT (21U) +/*! MICFIL - Enables the clock for MICFIL + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MICFIL_SHIFT)) & SYSCON_AHBCLKCTRL1_MICFIL_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for CTIMER2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for CTIMER0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for CTIMER1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) + +#define SYSCON_AHBCLKCTRL1_PKC_RAM_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT (29U) +/*! PKC_RAM - Enables the clock for PKC RAM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT)) & SYSCON_AHBCLKCTRL1_PKC_RAM_MASK) + +#define SYSCON_AHBCLKCTRL1_SmartDMA_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT (31U) +/*! SmartDMA - Enables the clock for SmartDMA + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_SmartDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT)) & SYSCON_AHBCLKCTRL1_SmartDMA_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock Control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for DMA1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXIO_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT (4U) +/*! FLEXIO - Enables the clock for Flexio + * 0b1..Enable clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXIO_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI0_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_SAI0_SHIFT (5U) +/*! SAI0 - Enables the clock for SAI0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI0_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI0_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI1_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_SAI1_SHIFT (6U) +/*! SAI1 - Enables the clock for SAI1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI1_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI1_MASK) + +#define SYSCON_AHBCLKCTRL2_TRO_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_TRO_SHIFT (7U) +/*! TRO - Enables the clock for TRO + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRO_SHIFT)) & SYSCON_AHBCLKCTRL2_TRO_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT (14U) +/*! FLEXCAN0 - Enables the clock for FLEXCAN0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT (15U) +/*! FLEXCAN1 - Enables the clock for FLEXCAN1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_SHIFT (16U) +/*! USB_HS - Enables the clock for USB HS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT (17U) +/*! USB_HS_PHY - Enables the clock for USB HS PHY + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_ELS_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_ELS_SHIFT (18U) +/*! ELS - Enables the clock for ELS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ELS_SHIFT)) & SYSCON_AHBCLKCTRL2_ELS_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for CTIMER3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for CTIMER4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for PUF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) +/*! PKC - Enables the clock for PKC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) + +#define SYSCON_AHBCLKCTRL2_SCG_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL2_SCG_SHIFT (26U) +/*! SCG - Enables the clock for SCG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SCG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SCG_SHIFT)) & SYSCON_AHBCLKCTRL2_SCG_MASK) + +#define SYSCON_AHBCLKCTRL2_GDET_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GDET_SHIFT (29U) +/*! GDET - Enables the clock for GDET0 and GDET1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GDET_SHIFT)) & SYSCON_AHBCLKCTRL2_GDET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) +/*! I3C0 - Enables the clock for I3C0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) + +#define SYSCON_AHBCLKCTRL3_I3C1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL3_I3C1_SHIFT (1U) +/*! I3C1 - Enables the clock for I3C1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C1_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C1_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) +/*! QDC0 - Enables the clock for QDC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) +/*! QDC1 - Enables the clock for QDC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) +#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) +/*! PWM0 - Enables the clock for PWM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x80U) +#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (7U) +/*! PWM1 - Enables the clock for PWM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) + +#define SYSCON_AHBCLKCTRL3_EVTG_MASK (0x100U) +#define SYSCON_AHBCLKCTRL3_EVTG_SHIFT (8U) +/*! EVTG - Enables the clock for EVTG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EVTG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EVTG_SHIFT)) & SYSCON_AHBCLKCTRL3_EVTG_MASK) + +#define SYSCON_AHBCLKCTRL3_VREF_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL3_VREF_SHIFT (19U) +/*! VREF - Enables the clock for VREF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) + +#define SYSCON_AHBCLKCTRL3_EWM_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL3_EWM_SHIFT (23U) +/*! EWM - Enables the clock for EWM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EWM_SHIFT)) & SYSCON_AHBCLKCTRL3_EWM_MASK) + +#define SYSCON_AHBCLKCTRL3_EIM_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL3_EIM_SHIFT (24U) +/*! EIM - Enables the clock for EIM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EIM_SHIFT)) & SYSCON_AHBCLKCTRL3_EIM_MASK) + +#define SYSCON_AHBCLKCTRL3_ERM_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL3_ERM_SHIFT (25U) +/*! ERM - Enables the clock for ERM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_ERM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ERM_SHIFT)) & SYSCON_AHBCLKCTRL3_ERM_MASK) + +#define SYSCON_AHBCLKCTRL3_INTM_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL3_INTM_SHIFT (26U) +/*! INTM - Enables the clock for INTM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_INTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_INTM_SHIFT)) & SYSCON_AHBCLKCTRL3_INTM_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLSET - AHB Clock Control Set */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (4U) + +/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (4U) + +/*! @name SYSTICKCLKSEL0 - CPU0 System Tick Timer Source Select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Selects the System Tick Timer for CPU0 source + * 0b000..SYSTICKCLKDIV0 output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name TRACECLKSEL - Trace Clock Source Select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the trace clock source. + * 0b000..TRACECLKDIV output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL - CTIMER Clock Source Select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL_SEL_MASK (0xFU) +#define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CTIMER clock source. + * 0b0000..FRO_1M clock + * 0b0001..PLL0 clock + * 0b0010..PLL1_clk0 clock + * 0b0011..FRO_HF clock + * 0b0100..FRO 12MHz clock + * 0b0101..SAI0 MCLK IN clock + * 0b0110..LP Oscillator clock + * 0b0111..No clock + * 0b1000..SAI1 MCLK IN clock + * 0b1001..SAI0 TX_BCLK clock + * 0b1010..SAI0 RX_BCLK clock + * 0b1011..SAI1 TX_BCLK clock + * 0b1100..SAI1 RX_BCLK clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSEL */ +#define SYSCON_CTIMERCLKSEL_COUNT (5U) + +/*! @name CLKOUTSEL - CLKOUT Clock Source Select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CLKOUT clock source. + * 0b0000..Main clock (main_clk) + * 0b0001..PLL0 clock (pll0_clk) + * 0b0010..CLKIN clock (clk_in) + * 0b0011..FRO_HF clock (fro_hf) + * 0b0100..FRO 12 MHz clock (fro_12m) + * 0b0101..PLL1_clk0 clock (pll1_clk) + * 0b0110..LP Oscillator clock (lp_osc) + * 0b0111..USB PLL clock (usb_pll_clk) + * 0b1000..No clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC0CLKSEL - ADC0 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC0 clock source. + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL - LP_FLEXCOMM Clock Source Select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the LP_FLEXCOMM clock source for Fractional Rate Divider. + * 0b000..No clock + * 0b001..PLL divided clock + * 0b010..FRO 12 MHz clock + * 0b011..fro_hf_div clock + * 0b100..clk_1m clock + * 0b101..USB PLL clock + * 0b110..LP Oscillator clock + * 0b111..No clock + */ +#define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSEL */ +#define SYSCON_FCCLKSEL_COUNT (8U) + +/*! @name SYSTICKCLKDIV - CPU0 System Tick Timer Divider */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset. + * 0b0..Divider is not reset + */ +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKDIV */ +#define SYSCON_SYSTICKCLKDIV_COUNT (1U) + +/*! @name TRACECLKDIV - TRACE Clock Divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT Clock Divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running, this bit is set to 0 when the register is written. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name WDT0CLKDIV - WDT0 Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT0CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_DIV_SHIFT)) & SYSCON_WDT0CLKDIV_DIV_MASK) + +#define SYSCON_WDT0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_RESET_SHIFT)) & SYSCON_WDT0CLKDIV_RESET_MASK) + +#define SYSCON_WDT0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_HALT_SHIFT)) & SYSCON_WDT0CLKDIV_HALT_MASK) + +#define SYSCON_WDT0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name ADC0CLKDIV - ADC0 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) + +#define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) + +#define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) + +#define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLLCLKDIV - PLL Clock Divider */ +/*! @{ */ + +#define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) + +#define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) + +#define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) + +#define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer Clock Divider */ +/*! @{ */ + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock has stopped + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Stable divider clock + * 0b1..Unstable clock frequency + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) + +/*! @name PLL1CLK0DIV - PLL1 Clock 0 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK0DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK0DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK0DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_DIV_SHIFT)) & SYSCON_PLL1CLK0DIV_DIV_MASK) + +#define SYSCON_PLL1CLK0DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK0DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK0DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_RESET_SHIFT)) & SYSCON_PLL1CLK0DIV_RESET_MASK) + +#define SYSCON_PLL1CLK0DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK0DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK0DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_HALT_SHIFT)) & SYSCON_PLL1CLK0DIV_HALT_MASK) + +#define SYSCON_PLL1CLK0DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK0DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK0DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLL1CLK1DIV - PLL1 Clock 1 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK1DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK1DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK1DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_DIV_SHIFT)) & SYSCON_PLL1CLK1DIV_DIV_MASK) + +#define SYSCON_PLL1CLK1DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK1DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK1DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_RESET_SHIFT)) & SYSCON_PLL1CLK1DIV_RESET_MASK) + +#define SYSCON_PLL1CLK1DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK1DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK1DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_HALT_SHIFT)) & SYSCON_PLL1CLK1DIV_HALT_MASK) + +#define SYSCON_PLL1CLK1DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK1DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK1DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name UTICKCLKDIV - UTICK Clock Divider */ +/*! @{ */ + +#define SYSCON_UTICKCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_UTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_UTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_DIV_SHIFT)) & SYSCON_UTICKCLKDIV_DIV_MASK) + +#define SYSCON_UTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_UTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_UTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_RESET_SHIFT)) & SYSCON_UTICKCLKDIV_RESET_MASK) + +#define SYSCON_UTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_UTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_UTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_HALT_SHIFT)) & SYSCON_UTICKCLKDIV_HALT_MASK) + +#define SYSCON_UTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_UTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_UTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_UTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUT_FRGCTRL - CLKOUT FRG Control */ +/*! @{ */ + +#define SYSCON_CLKOUT_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT (0U) +/*! DIV - Divider value */ +#define SYSCON_CLKOUT_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_DIV_MASK) + +#define SYSCON_CLKOUT_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT (8U) +/*! MULT - Numerator value */ +#define SYSCON_CLKOUT_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, xxxDIV, xxxSEL) + * 0b1..Freezes all clock configuration registers update + * 0b0..Updates are allowed to all clock configuration registers + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK (0x4U) +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT (2U) +/*! DIS_FLASH_CACHE - Flash cache control + * 0b0..Enables flash cache + * 0b1..Disables flash cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK (0x8U) +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT (3U) +/*! DIS_FLASH_INST - Flash instruction cache control + * 0b0..Enables flash instruction cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash instruction cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK (0x10U) +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT (4U) +/*! DIS_FLASH_DATA - Flash data cache control + * 0b0..Enables flash data cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash data cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK) + +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK (0x20U) +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT (5U) +/*! CLR_FLASH_CACHE - Clear flash cache control + * 0b0..No clear flash cache + * 0b1..Clears flash cache + */ +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name ROMCR - ROM Wait State */ +/*! @{ */ + +#define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) +#define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) +/*! ROM_WAIT - ROM waiting Arm core and other masters for one cycle + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) +/*! @} */ + +/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ +/*! @{ */ + +#define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) +#define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) +/*! INT0 - SmartDMA hijack NVIC IRQ1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) + +#define SYSCON_SMARTDMAINT_INT1_MASK (0x2U) +#define SYSCON_SMARTDMAINT_INT1_SHIFT (1U) +/*! INT1 - SmartDMA hijack NVIC IRQ17 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK) + +#define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) +#define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) +/*! INT2 - SmartDMA hijack NVIC IRQ18 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) + +#define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) +#define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) +/*! INT3 - SmartDMA hijack NVIC IRQ29 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) + +#define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) +#define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) +/*! INT4 - SmartDMA hijack NVIC IRQ30 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) + +#define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) +#define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) +/*! INT5 - SmartDMA hijack NVIC IRQ31 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) + +#define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) +#define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) +/*! INT6 - SmartDMA hijack NVIC IRQ32 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) + +#define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) +#define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) +/*! INT7 - SmartDMA hijack NVIC IRQ33 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) + +#define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) +#define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) +/*! INT8 - SmartDMA hijack NVIC IRQ34 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) + +#define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) +#define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) +/*! INT9 - SmartDMA hijack NVIC IRQ35 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) + +#define SYSCON_SMARTDMAINT_INT10_MASK (0x400U) +#define SYSCON_SMARTDMAINT_INT10_SHIFT (10U) +/*! INT10 - SmartDMA hijack NVIC IRQ36 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK) + +#define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) +#define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) +/*! INT11 - SmartDMA hijack NVIC IRQ37 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) + +#define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) +#define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) +/*! INT12 - SmartDMA hijack NVIC IRQ38 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) + +#define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) +#define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) +/*! INT13 - SmartDMA hijack NVIC IRQ39 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) + +#define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) +#define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) +/*! INT14 - SmartDMA hijack NVIC IRQ40 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) + +#define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) +#define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) +/*! INT15 - SmartDMA hijack NVIC IRQ41 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) + +#define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) +#define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) +/*! INT16 - SmartDMA hijack NVIC IRQ42 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) + +#define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) +#define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) +/*! INT17 - SmartDMA hijack NVIC IRQ45 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) + +#define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) +#define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) +/*! INT18 - SmartDMA hijack NVIC IRQ47 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) + +#define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) +#define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) +/*! INT19 - SmartDMA hijack NVIC IRQ50 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) + +#define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) +#define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) +/*! INT20 - SmartDMA hijack NVIC IRQ51 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) + +#define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) +#define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) +/*! INT21 - SmartDMA hijack NVIC IRQ66 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) + +#define SYSCON_SMARTDMAINT_INT22_MASK (0x400000U) +#define SYSCON_SMARTDMAINT_INT22_SHIFT (22U) +/*! INT22 - SmartDMA hijack NVIC IRQ67 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT22_SHIFT)) & SYSCON_SMARTDMAINT_INT22_MASK) + +#define SYSCON_SMARTDMAINT_INT23_MASK (0x800000U) +#define SYSCON_SMARTDMAINT_INT23_SHIFT (23U) +/*! INT23 - SmartDMA hijack NVIC IRQ77 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT23_SHIFT)) & SYSCON_SMARTDMAINT_INT23_MASK) +/*! @} */ + +/*! @name ADC1CLKSEL - ADC1 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC1 clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC1CLKDIV - ADC1 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) + +#define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) + +#define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) + +#define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name RAM_INTERLEAVE - Control PKC RAM Interleave Access */ +/*! @{ */ + +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Controls PKC RAM access for PKC RAM 0 and PKC RAM 1 + * 0b1..RAM access to PKC RAM 0 and PKC RAM 1 is interleaved. This setting is need for PKC L0 memory access. + * 0b0..RAM access to PKC RAM 0 and PKC RAM 1 is consecutive. + */ +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) +/*! @} */ + +/*! @name PLLCLKDIVSEL - PLL Clock Divider Clock Selection */ +/*! @{ */ + +#define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) +#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) +/*! SEL - Selects the PLL Clock Divider source clock + * 0b000..PLL0 clock + * 0b001..pll1_clk0 + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKSEL - I3C0 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the I3C0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKDIV - I3C0 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK) + +#define SYSCON_I3C0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKDIV_RESET_MASK) + +#define SYSCON_I3C0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKDIV_HALT_MASK) + +#define SYSCON_I3C0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MICFILFCLKSEL - MICFIL Clock Selection */ +/*! @{ */ + +#define SYSCON_MICFILFCLKSEL_SEL_MASK (0xFU) +#define SYSCON_MICFILFCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the MICFIL clock + * 0b0000..FRO_12M clock + * 0b0001..PLL0 clock + * 0b0010..CLKIN clock + * 0b0011..FRO_HF clock + * 0b0100..PLL1_clk0 clock + * 0b0101..SAI0_MCLK clock + * 0b0110..USB PLL clock + * 0b0111..No clock + * 0b1000..SAI1_MCLK clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_MICFILFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKSEL_SEL_SHIFT)) & SYSCON_MICFILFCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MICFILFCLKDIV - MICFIL Clock Division */ +/*! @{ */ + +#define SYSCON_MICFILFCLKDIV_DIV_MASK (0x7U) +#define SYSCON_MICFILFCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_MICFILFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_DIV_SHIFT)) & SYSCON_MICFILFCLKDIV_DIV_MASK) + +#define SYSCON_MICFILFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MICFILFCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_MICFILFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_RESET_SHIFT)) & SYSCON_MICFILFCLKDIV_RESET_MASK) + +#define SYSCON_MICFILFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MICFILFCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_MICFILFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_HALT_SHIFT)) & SYSCON_MICFILFCLKDIV_HALT_MASK) + +#define SYSCON_MICFILFCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_MICFILFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT)) & SYSCON_MICFILFCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXIOCLKSEL - FLEXIO Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXIO clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..FRO_12M clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKSEL_SEL_SHIFT)) & SYSCON_FLEXIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXIOCLKDIV - FLEXIO Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_DIV_SHIFT)) & SYSCON_FLEXIOCLKDIV_DIV_MASK) + +#define SYSCON_FLEXIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_RESET_SHIFT)) & SYSCON_FLEXIOCLKDIV_RESET_MASK) + +#define SYSCON_FLEXIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_HALT_SHIFT)) & SYSCON_FLEXIOCLKDIV_HALT_MASK) + +#define SYSCON_FLEXIOCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXIOCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXIOCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKSEL - FLEXCAN0 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKDIV - FLEXCAN0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKSEL - FLEXCAN1 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN1 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKDIV - FLEXCAN1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name EWM0CLKSEL - EWM0 Clock Selection */ +/*! @{ */ + +#define SYSCON_EWM0CLKSEL_SEL_MASK (0x1U) +#define SYSCON_EWM0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the EWM0 clock + * 0b0..clk_16k[2] + * 0b1..xtal32k[2] + */ +#define SYSCON_EWM0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EWM0CLKSEL_SEL_SHIFT)) & SYSCON_EWM0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKSEL - WDT1 Clock Selection */ +/*! @{ */ + +#define SYSCON_WDT1CLKSEL_SEL_MASK (0x3U) +#define SYSCON_WDT1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the WDT1 clock + * 0b00..FRO16K clock 2 + * 0b01..fro_hf_div clock + * 0b10..clk_1m clock + * 0b11..clk_1m clock + */ +#define SYSCON_WDT1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKSEL_SEL_SHIFT)) & SYSCON_WDT1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKDIV - WDT1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK) + +#define SYSCON_WDT1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_RESET_SHIFT)) & SYSCON_WDT1CLKDIV_RESET_MASK) + +#define SYSCON_WDT1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_HALT_SHIFT)) & SYSCON_WDT1CLKDIV_HALT_MASK) + +#define SYSCON_WDT1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name OSTIMERCLKSEL - OSTIMER Clock Selection */ +/*! @{ */ + +#define SYSCON_OSTIMERCLKSEL_SEL_MASK (0x3U) +#define SYSCON_OSTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the OS Event Timer clock + * 0b00..clk_16k[2] + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_OSTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OSTIMERCLKSEL_SEL_SHIFT)) & SYSCON_OSTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKSEL - CMP0 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKSEL_SEL_SHIFT)) & SYSCON_CMP0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKDIV - CMP0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_DIV_SHIFT)) & SYSCON_CMP0FCLKDIV_DIV_MASK) + +#define SYSCON_CMP0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_RESET_SHIFT)) & SYSCON_CMP0FCLKDIV_RESET_MASK) + +#define SYSCON_CMP0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_HALT_SHIFT)) & SYSCON_CMP0FCLKDIV_HALT_MASK) + +#define SYSCON_CMP0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP0RRCLKSEL - CMP0 Round Robin Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP0RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0RRCLKDIV - CMP0 Round Robin Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP0RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP0RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP0RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP0RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1FCLKSEL - CMP1 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKSEL_SEL_SHIFT)) & SYSCON_CMP1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1FCLKDIV - CMP1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP1FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_DIV_SHIFT)) & SYSCON_CMP1FCLKDIV_DIV_MASK) + +#define SYSCON_CMP1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_RESET_SHIFT)) & SYSCON_CMP1FCLKDIV_RESET_MASK) + +#define SYSCON_CMP1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_HALT_SHIFT)) & SYSCON_CMP1FCLKDIV_HALT_MASK) + +#define SYSCON_CMP1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1RRCLKSEL - CMP1 Round Robin Clock Source Select */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP1RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1RRCLKDIV - CMP1 Round Robin Clock Division */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP1RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP1RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP1RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP1RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b1..CPU is sleeping + * 0b0..CPU is not sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b1..CPU is in lockup + * 0b0..CPU is not in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) +/*! PARITY_MISS_EN - Enables parity miss. + * 0b0..Disabled + * 0b1..Enables parity, miss on parity error + */ +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b1..Disables write through buffer + * 0b0..Enables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + * 0b0..Write buffer enabled when transaction is bufferable. + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK (0x40U) +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT (6U) +/*! PARITY_FAULT_EN - Enable parity error report. + * 0b1..Enables parity error report + * 0b0..Disables parity error report + */ +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b1..Enabled. + * 0b0..Disabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) +/*! @} */ + +/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - LP_FLEXCOMM Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U) + +/*! @name UTICKCLKSEL - UTICK Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_UTICKCLKSEL_SEL_MASK (0x3U) +#define SYSCON_UTICKCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b00..clk_in + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_UTICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKSEL_SEL_SHIFT)) & SYSCON_UTICKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKSEL - SAI0 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKSEL_SEL_SHIFT)) & SYSCON_SAI0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI1CLKSEL - SAI1 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKSEL_SEL_SHIFT)) & SYSCON_SAI1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKDIV - SAI0 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_DIV_SHIFT)) & SYSCON_SAI0CLKDIV_DIV_MASK) + +#define SYSCON_SAI0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_RESET_SHIFT)) & SYSCON_SAI0CLKDIV_RESET_MASK) + +#define SYSCON_SAI0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_HALT_SHIFT)) & SYSCON_SAI0CLKDIV_HALT_MASK) + +#define SYSCON_SAI0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SAI1CLKDIV - SAI1 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_DIV_SHIFT)) & SYSCON_SAI1CLKDIV_DIV_MASK) + +#define SYSCON_SAI1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_RESET_SHIFT)) & SYSCON_SAI1CLKDIV_RESET_MASK) + +#define SYSCON_SAI1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_HALT_SHIFT)) & SYSCON_SAI1CLKDIV_HALT_MASK) + +#define SYSCON_SAI1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name KEY_RETAIN_CTRL - Key Retain Control */ +/*! @{ */ + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK (0x1U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT (0U) +/*! KEY_RETAIN_VALID - Indicates if the PUF key has been retained in the VBAT domain and has not + * been reset or otherwise invalidated by software. + * 0b0..PUF key is not retained in VBAT domain. + * 0b1..PUF key is retained in VBAT domain. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK (0x2U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT (1U) +/*! KEY_RETAIN_DONE - Indicates the successful completion of the key_save or key_load routine. Once + * set, to clear the key_retain_done flag, both key_save and key_load should be cleared by + * software. + * 0b0..Key save / load sequence has not completed. + * 0b1..Key save / load sequence has completed. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK (0x10000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT (16U) +/*! KEY_SAVE + * 0b0..Key save sequence is disabled. + * 0b1..Key save sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK (0x20000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT (17U) +/*! KEY_LOAD + * 0b0..Key load sequence is disabled. + * 0b1..Key load sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL - FRO 48MHz Reference Clock Control */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) +/*! GDET_REFCLK_EN - GDET reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK) + +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (1U) +/*! TRNG_REFCLK_EN - ELS TRNG reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_SET - FRO 48MHz Reference Clock Control Set */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) +/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) + +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (1U) +/*! TRNG_REFCLK_EN_SET - ELS TRNG reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_CLR - FRO 48MHz Reference Clock Control Clear */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) +/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) + +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (1U) +/*! TRNG_REFCLK_EN_CLR - ELS TRNG reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK) +/*! @} */ + +/*! @name GDETX_CTRL_GDET_CTRL - GDET Control Register */ +/*! @{ */ + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK (0x1U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT (0U) +/*! GDET_EVTCNT_CLR - Controls the GDET clean event counter + * 0b1..Clears event counter + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK (0x2U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT (1U) +/*! GDET_ERR_CLR - Clears GDET error status + * 0b1..Clears error status + * 0b0..Error status not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK (0xCU) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT (2U) +/*! GDET_ISO_SW - GDET isolation control + * 0b10..Isolation is enabled. When both GDET0_CTRL/GDET1_CTRL GDET_ISO_SW are "10", isolation_on is asserted. + * 0b00..Isolation is disabled + * 0b01..Isolation is disabled + * 0b11..Isolation is disabled + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK (0xFF00U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT (8U) +/*! EVENT_CNT - Event count value */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK (0x10000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT (16U) +/*! POS_SYNC - Positive glitch detected + * 0b1..Positive glitch detected + * 0b0..Positive glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK (0x20000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT (17U) +/*! NEG_SYNC - Negative glitch detected + * 0b1..Negative glitch detected + * 0b0..Negative glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK (0x40000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT (18U) +/*! EVENT_CLR_FLAG - Event counter cleared + * 0b1..Event counter cleared + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK) +/*! @} */ + +/* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) + +/*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ +/*! @{ */ + +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) +/*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the + * ELS module. Refer to the ELS chapter in the SRM for more details. + * 0b00..ELS asset is protected + * 0b10..ELS asset is protected + * 0b11..ELS asset is protected + * 0b01..ELS asset is not protected + */ +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL - ELS Lock Control */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - ELS Lock Control */ +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) +/*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name ELS_TEMPORAL_STATE - ELS Temporal State */ +/*! @{ */ + +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) +/*! TEMPORAL_STATE - Temporal state */ +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) +/*! @} */ + +/*! @name ELS_KDF_MASK - Key Derivation Function Mask */ +/*! @{ */ + +#define SYSCON_ELS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT (0U) +/*! KDF_MASK - Key derivation function mask */ +#define SYSCON_ELS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_ELS_KDF_MASK_KDF_MASK_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG0 - ELS AS Configuration */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) +/*! CFG_LC_STATE - LC state configuration bit */ +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK (0x200U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT (9U) +/*! CFG_LVD_CORE_RESET_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK (0x800U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT (11U) +/*! CFG_LVD_CORE_IRQ_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT (12U) +/*! CFG_WDT0_ENABLED - When WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK (0x2000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT (13U) +/*! CFG_CWDT0_ENABLED - When Code WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK (0x4000U) +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT (14U) +/*! CFG_ELS_GDET_ENABLED - When either GDET is enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK (0x8000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT (15U) +/*! CFG_ANA_GDET_RESET_ENABLED - When SPC analog glitch detect reset is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK (0x10000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT (16U) +/*! CFG_ANA_GDET_IRQ_ENABLED - When SPC analog glitch detect IRQ is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) +/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in TDET, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK (0x40000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT (18U) +/*! CFG_LVD_VSYS_RESET_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK (0x80000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT (19U) +/*! CFG_LVD_VDDIO_RESET_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK (0x100000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT (20U) +/*! CFG_LVD_VSYS_IRQ_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK (0x200000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT (21U) +/*! CFG_LVD_VDDIO_IRQ_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK (0x400000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT (22U) +/*! CFG_WDT1_ENABLED - When WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK (0x800000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT (23U) +/*! CFG_CWDT1_ENABLED - When Code WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK (0x1000000U) +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT (24U) +/*! CFG_TEMPTAMPER_DET_ENABLED - When temperature tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK (0x2000000U) +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT (25U) +/*! CFG_VOLTAMPER_DET_ENABLED - When voltage tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT (26U) +/*! CFG_LHTTAMPER_DET_ENABLED - When light tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U) +/*! CFG_CLKTAMPER_DET_ENABLED - When clk tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) +/*! CFG_QK_DISABLE_ENROLL - When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) +/*! CFG_QK_DISABLE_WRAP - When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG1 - ELS AS Configuration1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) +/*! CFG_SEC_DIS_STRICT_MODE - When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE + * bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this + * bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) +/*! CFG_SEC_DIS_VIOL_ABORT - When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) +/*! CFG_SEC_ENA_NS_PRIV_CHK - When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) +/*! CFG_SEC_ENA_S_PRIV_CHK - When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) +/*! CFG_SEC_ENA_SEC_CHK - When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) +/*! CFG_SEC_IDAU_ALLNS - When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB + * secure controller are equal to 01, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) +/*! CFG_SEC_LOCK_NS_MPU - When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) +/*! CFG_SEC_LOCK_NS_VTOR - When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) +/*! CFG_SEC_LOCK_S_MPU - When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) +/*! CFG_SEC_LOCK_S_VTAIRCR - When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure + * controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) +/*! CFG_SEC_LOCK_SAU - When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) + +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK (0x1FE000U) +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT (13U) +/*! METAL_VERSION - metal version */ +#define SYSCON_ELS_AS_CFG1_METAL_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK (0x1E00000U) +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT (21U) +/*! ROM_PATCH_VERSION - ROM patch version */ +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT (26U) +/*! CFG_HVD_CORE_RESET_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT (27U) +/*! CFG_HVD_CORE_IRQ_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT (28U) +/*! CFG_HVD_VSYS_RESET_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT (29U) +/*! CFG_HVD_VDDIO_RESET_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK (0x40000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT (30U) +/*! CFG_HVD_VSYS_IRQ_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK (0x80000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT (31U) +/*! CFG_HVD_VDDIO_IRQ_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG2 - ELS AS Configuration2 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT (0U) +/*! CFG_ELS_CMD_EN - ELS configuration command enable bit */ +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT)) & SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG3 - ELS AS Configuration3 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Device type identification data */ +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT)) & SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name ELS_AS_ST0 - ELS AS State Register */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) +/*! ST_TEMPORAL_STATE - TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register */ +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) +/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) +/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) +/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) +/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) +/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) +/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. */ +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) +/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK (0x10000U) +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT (16U) +/*! ST_XO40M_FAILED - When XO40M oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK (0x20000U) +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT (17U) +/*! ST_IFR_LOAD_FAILED - When IFR load fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK (0x3C0000U) +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT (18U) +/*! ST_GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output. */ +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT)) & SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK) +/*! @} */ + +/*! @name ELS_AS_ST1 - ELS AS State1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) +/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) +/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK) + +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) +/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK (0xC0U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) +/*! ST_DCDC_VOUT - VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK (0x300U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT (8U) +/*! ST_DCDC_DS - DCDC drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) +/*! ST_BOOT_MODE - ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP + * mode during boot, ISP pin should be pull down when out of reset. + */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) +/*! ST_BOOT_RETRY_CNT - BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK (0x30000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT (16U) +/*! ST_LDO_CORE_VOUT - VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK (0xC0000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT (18U) +/*! ST_LDO_CORE_DS - LDO_CORE drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG0 - Boot state captured during boot: Main ROM log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK (0xFU) +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT (0U) +/*! BOOT_IMAGE - Boot image source used during this boot. + * 0b0000..Internal flash image 0 + * 0b0001..Internal flash image 1 + * 0b0010..FlexSPI flash image 0 + * 0b0011..FlexSPI flash image 1 + * 0b0100..Recovery SPI flash image + * 0b0101..Serial boot image (write-memory and execute ISP command used) + * 0b0110..Receive SB3 containing SB_JUMP command is used. + * 0b0111..Customer SBL/recovery image (Bank1 IFR0). + * 0b1000..NXP MAD recovery image (Bank1 IFR0). + * 0b1001..NXP ROM extension (NMPA - Bank0 IFR0). + * 0b1010..Reserved. + * 0b1011..Reserved. + * 0b1100..Reserved. + * 0b1101..Reserved. + * 0b1110..Reserved. + * 0b1111..Reserved. + */ +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK (0x10U) +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT (4U) +/*! CMAC - CMAC verify is used instead of ECDSA verify on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK (0x40U) +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT (6U) +/*! ECDSA - ECDSA P-384 verification is done on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK (0x80U) +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT (7U) +/*! OFF_CHIP - Off-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK (0x100U) +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT (8U) +/*! ON_CHIP - On-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK (0x200U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT (9U) +/*! CDI_CSR - CDI based device keys are derived for CSR harvesting on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK (0x400U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT (10U) +/*! CDI_DICE - CDI per DICE specification is computed on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK (0x800U) +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT (11U) +/*! TRUSTZONE - TrustZone preset data is loaded during this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK (0x1000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT (12U) +/*! DEBUG_AUTH - Debug authentication done in this session prior to boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK (0x2000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT (13U) +/*! ITRC - ITRC zeroize event is handled in this session of boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK (0x4000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT (14U) +/*! DIG_GDET - Digital glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK (0x8000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT (15U) +/*! ANA_GDET - Analog glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK (0x10000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT (16U) +/*! DEEP_PD - Boot from deep-power down state. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK (0xF000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT (24U) +/*! LOW_POWER - Last low-power mode value. ROM copies SPC_LP_MODE field from SPC->SC[7:4]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK (0x80000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT (31U) +/*! ISP - ISP pin state at boot time. ROM copies CMC->MR0[0]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT (0U) +/*! RoTK - RoTK index used for this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK (0x3FCU) +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT (2U) +/*! FIPS - FIPS self-test is executed and PASS during this boot. When a bit is set, means self-test + * is executed and it FAILS. When a bit is clear, means corresponding self-test is executed and + * PASS or it is not executed. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK (0xC00U) +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT (10U) +/*! SB3 - SB3 type (valid after nboot_sb3_load_manifest()). + * 0b00..customer fw load/update file. + * 0b01..NXP Provisioning FW. + * 0b10..ELS signed OEM Provisioning FW. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_SB3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG2 - Boot state captured during boot: Hardware status signals log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK (0x3FU) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT (0U) +/*! CMC_SRS0 - CMC->SRS[5:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK (0xC0U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT (6U) +/*! VBAT_STATUS0 - VBAT->STATUSA[1:0] | ~VBAT->STATUSB[1:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK (0x1FF00U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT (8U) +/*! CMC_SRS1 - CMC->SRS[16:8] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK (0xFC0000U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT (18U) +/*! VBAT_STATUS1 - VBAT->STATUSA[11:6] | ~VBAT->STATUSB[11:6] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK (0xFF000000U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT (24U) +/*! CMC_SRS2 - CMC->SRS[31:24] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG3 - Boot state captured during boot: Security log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK (0xFFU) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT (0U) +/*! ERR_AUTH_FAIL_COUNT - CFPA->ERR_AUTH_FAIL_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK (0xFF00U) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) +/*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) +/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug + * access. The register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK (0x8U) +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT (3U) +/*! EFUSE_ATTACK_DETECT - OTPC can output attack_detect signal when it detects attack when load + * shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status + * can be recorded. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT)) & SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK (0x20U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT (5U) +/*! FLAG_LVD_CORE_OCCURED - This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK (0x100U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT (8U) +/*! FLAG_WDT0_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK (0x200U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT (9U) +/*! FLAG_CWDT0_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK (0x400U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT (10U) +/*! FLAG_WDT0_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK (0x800U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT (11U) +/*! FLAG_CWDT0_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) +/*! FLAG_QK_ERROR - This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK (0x2000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT (13U) +/*! FLAG_ELS_GLITCH_DETECTED - This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) +/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON + * block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) +/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set as 1 when tamper event is flagged from TDET. + * This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is + * cleared by software. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) +/*! FLAG_FLASH_ECC_INVALID - This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) +/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) +/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure code + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) +/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure data + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK (0x100000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT (20U) +/*! FLAG_LVD_VSYS_OCCURED - This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK (0x200000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT (21U) +/*! FLAG_LVD_VDDIO_OCCURED - This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK (0x400000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT (22U) +/*! FLAG_WDT1_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK (0x800000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT (23U) +/*! FLAG_CWDT1_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK (0x1000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT (24U) +/*! FLAG_WDT1_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK (0x2000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT (25U) +/*! FLAG_CWDT1_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U) +/*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when temperature temper IRQ is + * enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK (0x8000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT (27U) +/*! FLAG_VOLTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when voltage temper IRQ is enabled + * and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK (0x10000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT (28U) +/*! FLAG_LHTTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when light temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (29U) +/*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when clock temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG1 - ELS AS Flag1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT (29U) +/*! FLAG_HVD_CORE_OCCURED - This flag bit is set as 1 when HVD from VDD_CORE power domain is triggered. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK (0x40000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT (30U) +/*! FLAG_HVD_VSYS_OCCURED - This flag bit is set as 1 when HVD from VDD_SYS power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK (0x80000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT (31U) +/*! FLAG_HVD_VDDIO_OCCURED - This flag bit is set as 1 when HVD from VDD power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Clock Control */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) +/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT (2U) +/*! FRO1MHZ_ENA - Enables the FRO_1MHz clock for RTC module and for UTICK + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) +/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT (4U) +/*! FRO_HF_ENA - Enables FRO HF clock for the Frequency Measure module + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enables FRO_1MHz clock for clock muxing in clock gen + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +/*! @} */ + +/*! @name I3C1FCLKSEL - I3C1 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - I3C1 clock select + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C1FCLKDIV - I3C1 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C1FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKDIV_DIV_MASK) + +#define SYSCON_I3C1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKDIV_RESET_MASK) + +#define SYSCON_I3C1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKDIV_HALT_MASK) + +#define SYSCON_I3C1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray code_gray[31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray code_gray[41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control Automatic Clock Gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Controls automatic clock gating for the RAMB Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Controls automatic clock gating for the RAMC Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Controls automatic clock gating for the RAMD Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Controls automatic clock gating for the RAMD Controller. + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDEC - Control Automatic Clock Gating C */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK (0x40000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT (30U) +/*! RAMX - Controls automatic clock gating of the RAMX controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK (0x80000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT (31U) +/*! RAMA - Controls automatic clock gating of the RAMA controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM0 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM0 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM0 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM0 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM1 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM1 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM1 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM1 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name ECC_ENABLE_CTRL - RAM ECC Enable Control */ +/*! @{ */ + +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK (0x2U) +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT (1U) +/*! RAMB_RAMX_ECC_ENABLE - RAMB and RAMX ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK (0x4U) +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT (2U) +/*! RAMD_RAMC_ECC_ENABLE - RAMD and RAMC ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b1010..Enables write access to all registers + * 0b0000..Any other value than b1010: disables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) +/*! @} */ + +/* The count of SYSCON_SWD_ACCESS_CPU */ +#define SYSCON_SWD_ACCESS_CPU_COUNT (1U) + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Indicates DEVICE TYPE. */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip Revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) +#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) +/*! MINOR_REVISION - Chip minor revision */ +#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) + +#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) +#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) +/*! MAJOR_REVISION - Chip major revision */ +#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) +/*! MCO_NUM_IN_DIE_ID - Chip number */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif +/* Backward compatibility */ +#define SYSCON SYSCON0 + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer + * @{ + */ + +/** SYSPM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t PMCR; /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x18, array step: index*0x30, index2*0x8 */ + __I uint8_t HI; /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */ + uint8_t RESERVED_0[3]; + __I uint32_t LO; /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */ + } PMECTR[3]; + } PMCR[1]; +} SYSPM_Type; + +/* ---------------------------------------------------------------------------- + -- SYSPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Register_Masks SYSPM Register Masks + * @{ + */ + +/*! @name PMCR - Performance Monitor Control */ +/*! @{ */ + +#define SYSPM_PMCR_MENB_MASK (0x1U) +#define SYSPM_PMCR_MENB_SHIFT (0U) +/*! MENB - Module Is Enabled + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSPM_PMCR_MENB(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK) + +#define SYSPM_PMCR_SSC_MASK (0xEU) +#define SYSPM_PMCR_SSC_SHIFT (1U) +/*! SSC - Start and Stop Control + * 0b000..Idle or no-op + * 0b001..Local stop + * 0b010, 0b011..Local start + * 0b100.. + * 0b101.. + * 0b110, 0b111.. + */ +#define SYSPM_PMCR_SSC(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK) + +#define SYSPM_PMCR_CMODE_MASK (0x30U) +#define SYSPM_PMCR_CMODE_SHIFT (4U) +/*! CMODE - Count Mode + * 0b00..Counted in both User and Privileged modes + * 0b01.. + * 0b10..Counted only in User mode + * 0b11..Counted only in Privileged mode + */ +#define SYSPM_PMCR_CMODE(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK) + +#define SYSPM_PMCR_RECTR1_MASK (0x100U) +#define SYSPM_PMCR_RECTR1_SHIFT (8U) +/*! RECTR1 - Reset Event Counter 1 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK) + +#define SYSPM_PMCR_RECTR2_MASK (0x200U) +#define SYSPM_PMCR_RECTR2_SHIFT (9U) +/*! RECTR2 - Reset Event Counter 2 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK) + +#define SYSPM_PMCR_RECTR3_MASK (0x400U) +#define SYSPM_PMCR_RECTR3_SHIFT (10U) +/*! RECTR3 - Reset Event Counter 3 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK) + +#define SYSPM_PMCR_SELEVT1_MASK (0x3F800U) +#define SYSPM_PMCR_SELEVT1_SHIFT (11U) +/*! SELEVT1 - Select Event 1 */ +#define SYSPM_PMCR_SELEVT1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK) + +#define SYSPM_PMCR_SELEVT2_MASK (0x1FC0000U) +#define SYSPM_PMCR_SELEVT2_SHIFT (18U) +/*! SELEVT2 - Select Event 2 */ +#define SYSPM_PMCR_SELEVT2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK) + +#define SYSPM_PMCR_SELEVT3_MASK (0xFE000000U) +#define SYSPM_PMCR_SELEVT3_SHIFT (25U) +/*! SELEVT3 - Select Event 3 */ +#define SYSPM_PMCR_SELEVT3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR */ +#define SYSPM_PMCR_COUNT (1U) + +/*! @name PMCR_PMECTR_HI - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_HI_ECTR_MASK (0xFFU) +#define SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_HI_ECTR(x) (((uint8_t)(((uint8_t)(x)) << SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_HI_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT2 (3U) + +/*! @name PMCR_PMECTR_LO - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_LO_ECTR_MASK (0xFFFFFFFFU) +#define SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_LO_ECTR(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_LO_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT2 (3U) + + +/*! + * @} + */ /* end of group SYSPM_Register_Masks */ + + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } +#endif + +/*! + * @} + */ /* end of group SYSPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1CC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_0[224]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer + * @{ + */ + +/** USBHS - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USBHS_Type; + +/* ---------------------------------------------------------------------------- + -- USBHS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Register_Masks USBHS Register Masks + * @{ + */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define USBHS_ID_ID_MASK (0x3FU) +#define USBHS_ID_ID_SHIFT (0U) +/*! ID - Configuration Number */ +#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) + +#define USBHS_ID_NID_MASK (0x3F00U) +#define USBHS_ID_NID_SHIFT (8U) +/*! NID - Complement Version of ID */ +#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) + +#define USBHS_ID_REVISION_MASK (0xFF0000U) +#define USBHS_ID_REVISION_SHIFT (16U) +/*! REVISION - Revision Number of the Controller Core */ +#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ + +#define USBHS_HWGENERAL_PHYW_MASK (0x30U) +#define USBHS_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW - Data width of the transceiver connected to the controller core + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) + */ +#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK) + +#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) +#define USBHS_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM - Transceiver Type + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK) + +#define USBHS_HWGENERAL_SM_MASK (0x600U) +#define USBHS_HWGENERAL_SM_SHIFT (9U) +/*! SM - Serial interface mode capability + * 0b00..No Serial Engine, always use parallel signalling + * 0b01..Serial Engine present, always use serial signalling for FS/LS + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWHOST_HC_MASK (0x1U) +#define USBHS_HWHOST_HC_SHIFT (0U) +/*! HC - Host Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK) + +#define USBHS_HWHOST_NPORT_MASK (0xEU) +#define USBHS_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ +#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWDEVICE_DC_MASK (0x1U) +#define USBHS_HWDEVICE_DC_SHIFT (0U) +/*! DC - Device Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK) + +#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) +#define USBHS_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - Device Endpoint Number */ +#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) +#define USBHS_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - Default burst size for memory to TX buffer transfer */ +#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) + +#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ +#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) +#define USBHS_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - Default burst size for memory to RX buffer transfer */ +#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) + +#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) +#define USBHS_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ +#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ + +#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER0CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USBHS_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ + +#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER1CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USBHS_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ + +#define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) +#define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST - AHB master interface Burst configuration + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USBHS_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_SBUSCFG_AHBBRST_SHIFT)) & USBHS_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ + +#define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of + * the Operational Register. Default value is '40h'. + */ +#define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ + +#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - Host Controller Interface Version Number */ +#define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - Number of Downstream Ports */ +#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) + +#define USBHS_HCSPARAMS_PPC_MASK (0x10U) +#define USBHS_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - Port Power Control */ +#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) + +#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - Number of Ports per Companion Controller */ +#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) + +#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) +#define USBHS_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC - Number of Companion Controller + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported + */ +#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) + +#define USBHS_HCSPARAMS_PI_MASK (0x10000U) +#define USBHS_HCSPARAMS_PI_SHIFT (16U) +/*! PI - Port Indicators (P INDICATOR) */ +#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) + +#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - Number of Ports per Transaction Translator */ +#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) + +#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USBHS_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - Number of Transaction Translators */ +#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_HCCPARAMS_ADC_MASK (0x1U) +#define USBHS_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - 64-bit Addressing Capability */ +#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) + +#define USBHS_HCCPARAMS_PFL_MASK (0x2U) +#define USBHS_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - Programmable Frame List Flag */ +#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) + +#define USBHS_HCCPARAMS_ASP_MASK (0x4U) +#define USBHS_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - Asynchronous Schedule Park Capability */ +#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) + +#define USBHS_HCCPARAMS_IST_MASK (0xF0U) +#define USBHS_HCCPARAMS_IST_SHIFT (4U) +/*! IST - Isochronous Scheduling Threshold */ +#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) + +#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) +#define USBHS_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EHCI Extended Capabilities Pointer */ +#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ + +#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - Device Controller Interface Version Number */ +#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_DCCPARAMS_DEN_MASK (0x1FU) +#define USBHS_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - Device Endpoint Number */ +#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) + +#define USBHS_DCCPARAMS_DC_MASK (0x80U) +#define USBHS_DCCPARAMS_DC_SHIFT (7U) +/*! DC - Device Capable */ +#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) + +#define USBHS_DCCPARAMS_HC_MASK (0x100U) +#define USBHS_DCCPARAMS_HC_SHIFT (8U) +/*! HC - Host Capable */ +#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command */ +/*! @{ */ + +#define USBHS_USBCMD_RS_MASK (0x1U) +#define USBHS_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop + * 0b0..Stop + * 0b1..Run + */ +#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) + +#define USBHS_USBCMD_RST_MASK (0x2U) +#define USBHS_USBCMD_RST_SHIFT (1U) +/*! RST - Controller Reset */ +#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) + +#define USBHS_USBCMD_FS_1_MASK (0xCU) +#define USBHS_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - Frame List Size */ +#define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) + +#define USBHS_USBCMD_PSE_MASK (0x10U) +#define USBHS_USBCMD_PSE_SHIFT (4U) +/*! PSE - Periodic Schedule Enable + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule + */ +#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) + +#define USBHS_USBCMD_ASE_MASK (0x20U) +#define USBHS_USBCMD_ASE_SHIFT (5U) +/*! ASE - Asynchronous Schedule Enable + * 0b0..Do not process the Asynchronous Schedule + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule + */ +#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) + +#define USBHS_USBCMD_IAA_MASK (0x40U) +#define USBHS_USBCMD_IAA_SHIFT (6U) +/*! IAA - Interrupt on Async Advance Doorbell */ +#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) + +#define USBHS_USBCMD_ASP_MASK (0x300U) +#define USBHS_USBCMD_ASP_SHIFT (8U) +/*! ASP - Asynchronous Schedule Park Mode Count */ +#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) + +#define USBHS_USBCMD_ASPE_MASK (0x800U) +#define USBHS_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - Asynchronous Schedule Park Mode Enable */ +#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) + +#define USBHS_USBCMD_SUTW_MASK (0x2000U) +#define USBHS_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - Setup TripWire [device mode only] */ +#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) + +#define USBHS_USBCMD_ATDTW_MASK (0x4000U) +#define USBHS_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - Add dTD TripWire[device mode only] */ +#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) + +#define USBHS_USBCMD_FS_2_MASK (0x8000U) +#define USBHS_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 - Frame List Size [host mode only] */ +#define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) + +#define USBHS_USBCMD_ITC_MASK (0xFF0000U) +#define USBHS_USBCMD_ITC_SHIFT (16U) +/*! ITC - Interrupt Threshold Control + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status */ +/*! @{ */ + +#define USBHS_USBSTS_UI_MASK (0x1U) +#define USBHS_USBSTS_UI_SHIFT (0U) +/*! UI - USB Interrupt (USBINT) */ +#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) + +#define USBHS_USBSTS_UEI_MASK (0x2U) +#define USBHS_USBSTS_UEI_SHIFT (1U) +/*! UEI - USB Error Interrupt (USBERRINT) */ +#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) + +#define USBHS_USBSTS_PCI_MASK (0x4U) +#define USBHS_USBSTS_PCI_SHIFT (2U) +/*! PCI - Port Change Detect */ +#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) + +#define USBHS_USBSTS_FRI_MASK (0x8U) +#define USBHS_USBSTS_FRI_SHIFT (3U) +/*! FRI - Frame List Rollover */ +#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) + +#define USBHS_USBSTS_SEI_MASK (0x10U) +#define USBHS_USBSTS_SEI_SHIFT (4U) +/*! SEI - System Error */ +#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) + +#define USBHS_USBSTS_AAI_MASK (0x20U) +#define USBHS_USBSTS_AAI_SHIFT (5U) +/*! AAI - Interrupt on Async Advance */ +#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) + +#define USBHS_USBSTS_URI_MASK (0x40U) +#define USBHS_USBSTS_URI_SHIFT (6U) +/*! URI - USB Reset Received */ +#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) + +#define USBHS_USBSTS_SRI_MASK (0x80U) +#define USBHS_USBSTS_SRI_SHIFT (7U) +/*! SRI - SOF Received */ +#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) + +#define USBHS_USBSTS_SLI_MASK (0x100U) +#define USBHS_USBSTS_SLI_SHIFT (8U) +/*! SLI - DCSuspend */ +#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) + +#define USBHS_USBSTS_ULPII_MASK (0x400U) +#define USBHS_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPI Interrupt */ +#define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) + +#define USBHS_USBSTS_HCH_MASK (0x1000U) +#define USBHS_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCHaIted */ +#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) + +#define USBHS_USBSTS_RCL_MASK (0x2000U) +#define USBHS_USBSTS_RCL_SHIFT (13U) +/*! RCL - Reclamation */ +#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) + +#define USBHS_USBSTS_PS_MASK (0x4000U) +#define USBHS_USBSTS_PS_SHIFT (14U) +/*! PS - Periodic Schedule Status */ +#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) + +#define USBHS_USBSTS_AS_MASK (0x8000U) +#define USBHS_USBSTS_AS_SHIFT (15U) +/*! AS - Asynchronous Schedule Status */ +#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) + +#define USBHS_USBSTS_NAKI_MASK (0x10000U) +#define USBHS_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAK Interrupt Bit */ +#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) + +#define USBHS_USBSTS_TI0_MASK (0x1000000U) +#define USBHS_USBSTS_TI0_SHIFT (24U) +/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ +#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) + +#define USBHS_USBSTS_TI1_MASK (0x2000000U) +#define USBHS_USBSTS_TI1_SHIFT (25U) +/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ +#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable */ +/*! @{ */ + +#define USBHS_USBINTR_UE_MASK (0x1U) +#define USBHS_USBINTR_UE_SHIFT (0U) +/*! UE - USB Interrupt Enable */ +#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) + +#define USBHS_USBINTR_UEE_MASK (0x2U) +#define USBHS_USBINTR_UEE_SHIFT (1U) +/*! UEE - USB Error Interrupt Enable */ +#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) + +#define USBHS_USBINTR_PCE_MASK (0x4U) +#define USBHS_USBINTR_PCE_SHIFT (2U) +/*! PCE - Port Change Detect Interrupt Enable */ +#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) + +#define USBHS_USBINTR_FRE_MASK (0x8U) +#define USBHS_USBINTR_FRE_SHIFT (3U) +/*! FRE - Frame List Rollover Interrupt Enable */ +#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) + +#define USBHS_USBINTR_SEE_MASK (0x10U) +#define USBHS_USBINTR_SEE_SHIFT (4U) +/*! SEE - System Error Interrupt Enable */ +#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) + +#define USBHS_USBINTR_AAE_MASK (0x20U) +#define USBHS_USBINTR_AAE_SHIFT (5U) +/*! AAE - Async Advance Interrupt Enable */ +#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) + +#define USBHS_USBINTR_URE_MASK (0x40U) +#define USBHS_USBINTR_URE_SHIFT (6U) +/*! URE - USB Reset Interrupt Enable */ +#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) + +#define USBHS_USBINTR_SRE_MASK (0x80U) +#define USBHS_USBINTR_SRE_SHIFT (7U) +/*! SRE - SOF Received Interrupt Enable */ +#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) + +#define USBHS_USBINTR_SLE_MASK (0x100U) +#define USBHS_USBINTR_SLE_SHIFT (8U) +/*! SLE - Sleep Interrupt Enable */ +#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) + +#define USBHS_USBINTR_NAKE_MASK (0x10000U) +#define USBHS_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAK Interrupt Enable */ +#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) + +#define USBHS_USBINTR_UAIE_MASK (0x40000U) +#define USBHS_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - USB Host Asynchronous Interrupt Enable */ +#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) + +#define USBHS_USBINTR_UPIE_MASK (0x80000U) +#define USBHS_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - USB Host Periodic Interrupt Enable */ +#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) + +#define USBHS_USBINTR_TIE0_MASK (0x1000000U) +#define USBHS_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - General Purpose Timer #0 Interrupt Enable */ +#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) + +#define USBHS_USBINTR_TIE1_MASK (0x2000000U) +#define USBHS_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - General Purpose Timer #1 Interrupt Enable */ +#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ + +#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USBHS_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX - Frame Index + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ + +#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - Device Address Advance */ +#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) + +#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USBHS_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - Device Address */ +#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ + +#define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - Base Address (Low) */ +#define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ + +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - Link Pointer Low (LPL) */ +#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ + +#define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - Endpoint List Pointer (Low) */ +#define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ + +#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - Programmable RX Burst Size */ +#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) + +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - Programmable TX Burst Size */ +#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ + +#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - Scheduler Overhead */ +#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) + +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - Scheduler Health Counter */ +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) + +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - FIFO Burst Threshold */ +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ + +#define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) +#define USBHS_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - RX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) + +#define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USBHS_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - TX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ + +#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - RX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) + +#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - TX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag */ +/*! @{ */ + +#define USBHS_CONFIGFLAG_CF_MASK (0x1U) +#define USBHS_CONFIGFLAG_CF_SHIFT (0U) +/*! CF - Configure Flag + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller + * 0b1..Port routing control logic default-routes all ports to this host controller + */ +#define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ + +#define USBHS_PORTSC1_CCS_MASK (0x1U) +#define USBHS_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status + * 0b0..In Host mode: No device is present. In Device mode: Not attached + * 0b1..In Host mode: Device is present on port. In Device mode: Attached + */ +#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) + +#define USBHS_PORTSC1_CSC_MASK (0x2U) +#define USBHS_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change + * 0b0..No change + * 0b1..Change in current connect status + */ +#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) + +#define USBHS_PORTSC1_PE_MASK (0x4U) +#define USBHS_PORTSC1_PE_SHIFT (2U) +/*! PE - Port Enabled/Disabled + * 0b0..Disable + * 0b1..Enable + */ +#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) + +#define USBHS_PORTSC1_PEC_MASK (0x8U) +#define USBHS_PORTSC1_PEC_SHIFT (3U) +/*! PEC - Port Enable/Disable Change + * 0b0..No change + * 0b1..Port enabled/disabled status has changed + */ +#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) + +#define USBHS_PORTSC1_OCA_MASK (0x10U) +#define USBHS_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-Current Active + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition + */ +#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) + +#define USBHS_PORTSC1_OCC_MASK (0x20U) +#define USBHS_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current Change */ +#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) + +#define USBHS_PORTSC1_FPR_MASK (0x40U) +#define USBHS_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume + * 0b0..No resume (K-state) detected/driven on port + * 0b1..Resume detected/driven on port + */ +#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) + +#define USBHS_PORTSC1_SUSP_MASK (0x80U) +#define USBHS_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Port not in suspend state + * 0b1..Port in suspend state + */ +#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) + +#define USBHS_PORTSC1_PR_MASK (0x100U) +#define USBHS_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset + * 0b0..Port is not in reset + * 0b1..Port is in reset + */ +#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) + +#define USBHS_PORTSC1_HSP_MASK (0x200U) +#define USBHS_PORTSC1_HSP_SHIFT (9U) +/*! HSP - High-Speed Port */ +#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) + +#define USBHS_PORTSC1_LS_MASK (0xC00U) +#define USBHS_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK) + +#define USBHS_PORTSC1_PP_MASK (0x1000U) +#define USBHS_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power */ +#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) + +#define USBHS_PORTSC1_PO_MASK (0x2000U) +#define USBHS_PORTSC1_PO_SHIFT (13U) +/*! PO - Port Owner */ +#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) + +#define USBHS_PORTSC1_PIC_MASK (0xC000U) +#define USBHS_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK) + +#define USBHS_PORTSC1_PTC_MASK (0xF0000U) +#define USBHS_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved + */ +#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK) + +#define USBHS_PORTSC1_WKCN_MASK (0x100000U) +#define USBHS_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - Wake on Connect Enable (WKCNNT_E) */ +#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) + +#define USBHS_PORTSC1_WKDC_MASK (0x200000U) +#define USBHS_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ +#define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) + +#define USBHS_PORTSC1_WKOC_MASK (0x400000U) +#define USBHS_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - Wake on Over-current Enable (WKOC_E) */ +#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) + +#define USBHS_PORTSC1_PHCD_MASK (0x800000U) +#define USBHS_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK) + +#define USBHS_PORTSC1_PFSC_MASK (0x1000000U) +#define USBHS_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC - Port Force Full Speed Connect + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK) + +#define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) +#define USBHS_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) + +#define USBHS_PORTSC1_PSPD_MASK (0xC000000U) +#define USBHS_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD - Port Speed + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK) + +#define USBHS_PORTSC1_PTW_MASK (0x10000000U) +#define USBHS_PORTSC1_PTW_SHIFT (28U) +/*! PTW - Parallel Transceiver Width - Read/Write + * 0b0..Select the 8-bit UTMI interface [60 MHz] + * 0b1..Select the 16-bit UTMI interface [30 MHz] + */ +#define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) + +#define USBHS_PORTSC1_STS_MASK (0x20000000U) +#define USBHS_PORTSC1_STS_SHIFT (29U) +/*! STS - Serial Transceiver Select + * 0b0..Parallel Interface signals is selected + * 0b1..Serial Interface Engine is selected + */ +#define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) + +#define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USBHS_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & Control */ +/*! @{ */ + +#define USBHS_OTGSC_VD_MASK (0x1U) +#define USBHS_OTGSC_VD_SHIFT (0U) +/*! VD - VBUS Discharge */ +#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) + +#define USBHS_OTGSC_VC_MASK (0x2U) +#define USBHS_OTGSC_VC_SHIFT (1U) +/*! VC - VBUS Charge */ +#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) + +#define USBHS_OTGSC_OT_MASK (0x8U) +#define USBHS_OTGSC_OT_SHIFT (3U) +/*! OT - OTG Termination */ +#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) + +#define USBHS_OTGSC_DP_MASK (0x10U) +#define USBHS_OTGSC_DP_SHIFT (4U) +/*! DP - Data Pulsing */ +#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) + +#define USBHS_OTGSC_IDPU_MASK (0x20U) +#define USBHS_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - ID Pullup + * 0b0..Off + * 0b1..On + */ +#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) + +#define USBHS_OTGSC_ID_MASK (0x100U) +#define USBHS_OTGSC_ID_SHIFT (8U) +/*! ID - USB ID + * 0b0..A device + * 0b1..B device + */ +#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) + +#define USBHS_OTGSC_AVV_MASK (0x200U) +#define USBHS_OTGSC_AVV_SHIFT (9U) +/*! AVV - A VBus Valid */ +#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) + +#define USBHS_OTGSC_ASV_MASK (0x400U) +#define USBHS_OTGSC_ASV_SHIFT (10U) +/*! ASV - A Session Valid */ +#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) + +#define USBHS_OTGSC_BSV_MASK (0x800U) +#define USBHS_OTGSC_BSV_SHIFT (11U) +/*! BSV - B Session Valid */ +#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) + +#define USBHS_OTGSC_BSE_MASK (0x1000U) +#define USBHS_OTGSC_BSE_SHIFT (12U) +/*! BSE - B Session End */ +#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) + +#define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) +#define USBHS_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - 1 Millisecond Timer Toggle */ +#define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) + +#define USBHS_OTGSC_DPS_MASK (0x4000U) +#define USBHS_OTGSC_DPS_SHIFT (14U) +/*! DPS - Data Bus Pulsing Status */ +#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) + +#define USBHS_OTGSC_IDIS_MASK (0x10000U) +#define USBHS_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - USB ID Interrupt Status */ +#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) + +#define USBHS_OTGSC_AVVIS_MASK (0x20000U) +#define USBHS_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - A VBus Valid Interrupt Status */ +#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) + +#define USBHS_OTGSC_ASVIS_MASK (0x40000U) +#define USBHS_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - A Session Valid Interrupt Status */ +#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) + +#define USBHS_OTGSC_BSVIS_MASK (0x80000U) +#define USBHS_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - B Session Valid Interrupt Status */ +#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) + +#define USBHS_OTGSC_BSEIS_MASK (0x100000U) +#define USBHS_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - B Session End Interrupt Status */ +#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) + +#define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ +#define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) + +#define USBHS_OTGSC_DPIS_MASK (0x400000U) +#define USBHS_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - Data Pulse Interrupt Status */ +#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) + +#define USBHS_OTGSC_IDIE_MASK (0x1000000U) +#define USBHS_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - USB ID Interrupt Enable */ +#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) + +#define USBHS_OTGSC_AVVIE_MASK (0x2000000U) +#define USBHS_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - A VBus Valid Interrupt Enable */ +#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) + +#define USBHS_OTGSC_ASVIE_MASK (0x4000000U) +#define USBHS_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - A Session Valid Interrupt Enable */ +#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) + +#define USBHS_OTGSC_BSVIE_MASK (0x8000000U) +#define USBHS_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - B Session Valid Interrupt Enable */ +#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) + +#define USBHS_OTGSC_BSEIE_MASK (0x10000000U) +#define USBHS_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - B Session End Interrupt Enable */ +#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) + +#define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) +#define USBHS_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ +#define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) + +#define USBHS_OTGSC_DPIE_MASK (0x40000000U) +#define USBHS_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - Data Pulse Interrupt Enable */ +#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ + +#define USBHS_USBMODE_CM_MASK (0x3U) +#define USBHS_USBMODE_CM_SHIFT (0U) +/*! CM - Controller Mode + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK) + +#define USBHS_USBMODE_ES_MASK (0x4U) +#define USBHS_USBMODE_ES_SHIFT (2U) +/*! ES - Endian Select + * 0b0..Little Endian + * 0b1..Big Endian + */ +#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) + +#define USBHS_USBMODE_SLOM_MASK (0x8U) +#define USBHS_USBMODE_SLOM_SHIFT (3U) +/*! SLOM - Setup Lockout Mode + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off + */ +#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK) + +#define USBHS_USBMODE_SDIS_MASK (0x10U) +#define USBHS_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - Stream Disable Mode + * 0b0..Inactive + * 0b1..Active + */ +#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ + +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - Setup Endpoint Status */ +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ + +#define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) +#define USBHS_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - Prime Endpoint Receive Buffer */ +#define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) + +#define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USBHS_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - Prime Endpoint Transmit Buffer */ +#define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ + +#define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - Flush Endpoint Receive Buffer */ +#define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) + +#define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - Flush Endpoint Transmit Buffer */ +#define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ + +#define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - Endpoint Receive Buffer Ready */ +#define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) + +#define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - Endpoint Transmit Buffer Ready */ +#define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ + +#define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - Endpoint Receive Complete Event */ +#define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) + +#define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - Endpoint Transmit Complete Event */ +#define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control 0 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) + +#define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) + +#define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) + +#define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) + +#define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) + +#define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) + +#define USBHS_ENDPTCTRL_RXD_MASK (0x2U) +#define USBHS_ENDPTCTRL_RXD_SHIFT (1U) +/*! RXD - RX Endpoint Data Sink + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) + +#define USBHS_ENDPTCTRL_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) + +#define USBHS_ENDPTCTRL_RXI_MASK (0x20U) +#define USBHS_ENDPTCTRL_RXI_SHIFT (5U) +/*! RXI - RX Data Toggle Inhibit + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) + +#define USBHS_ENDPTCTRL_RXR_MASK (0x40U) +#define USBHS_ENDPTCTRL_RXR_SHIFT (6U) +/*! RXR - RX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) + +#define USBHS_ENDPTCTRL_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) + +#define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) + +#define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) +#define USBHS_ENDPTCTRL_TXD_SHIFT (17U) +/*! TXD - TX Endpoint Data Source + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) + +#define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) + +#define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) +#define USBHS_ENDPTCTRL_TXI_SHIFT (21U) +/*! TXI - TX Data Toggle Inhibit + * 0b0..PID sequencing enabled + * 0b1..PID sequencing disabled + */ +#define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) + +#define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) +#define USBHS_ENDPTCTRL_TXR_SHIFT (22U) +/*! TXR - TX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) + +#define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USBHS_ENDPTCTRL */ +#define USBHS_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USBHS_Register_Masks */ + + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USBHS_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USBHS_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USBHS_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USBHS_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USBHS_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USBHS_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USBHS_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USBHS_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USBHS_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USBHS_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USBHS_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USBHS_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USBHS_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USBHS_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USBHS_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USBHS_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USBHS_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USBHS_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USBHS_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USBHS_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USBHS_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USBHS_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USBHS_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USBHS_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USBHS_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USBHS_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USBHS_SBUSCFG_AHBBRST(x) +#define USBHS_USBCMD_FS_MASK USBHS_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USBHS_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USBHS_USBCMD_FS_1(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USBHS_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USBHS_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USBHS_ENDPTLISTADDR_EPBASE(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USBHS_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USBHS_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USBHS_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USBHS_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USBHS_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USBHS_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USBHS_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USBHS_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USBHS_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USBHS_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USBHS_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USBHS_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USBHS_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USBHS_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USBHS_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USBHS_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USBHS_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USBHS_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USBHS_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USBHS_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USBHS_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USBHS_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USBHS_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USBHS_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USBHS_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USBHS_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USBHS_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USBHS_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USBHS_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USBHS_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USBHS_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USBHS_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USBHS_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USBHS_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USBHS_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USBHS_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USBHS_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USBHS_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USBHS_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USBHS_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USBHS_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USBHS_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USBHS_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USBHS_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USBHS_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USBHS_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USBHS_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USBHS_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USBHS_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USBHS_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USBHS_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USBHS_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USBHS_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USBHS_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USBHS_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USBHS_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USBHS_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USBHS_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USBHS_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USBHS_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USBHS_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USBHS_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USBHS_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USBHS_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USBHS_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USBHS_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USBHS_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USBHS_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USBHS_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USBHS_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USBHS_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USBHS_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USBHS_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USBHS_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USBHS_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USBHS_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USBHS_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USBHS_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USBHS_ENDPTCTRL_COUNT +#define USBHS_PORTSC1_WKDS_MASK USBHS_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USBHS_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USBHS_PORTSC1_WKDC(x) +#define USBHS_IRQHandler USB1_HS_IRQHandler + + +/*! + * @} + */ /* end of group USBHS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer + * @{ + */ + +/** USBHSDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock, offset: 0x4 */ + __I uint32_t STATUS; /**< Status, offset: 0x8 */ + __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override, offset: 0xC */ + __IO uint32_t TIMER0; /**< TIMER0, offset: 0x10 */ + __IO uint32_t TIMER1; /**< TIMER1, offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11, offset: 0x18 */ + __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12, offset: 0x18 */ + }; +} USBHSDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks + * @{ + */ + +/*! @name CONTROL - Control */ +/*! @{ */ + +#define USBHSDCD_CONTROL_IACK_MASK (0x1U) +#define USBHSDCD_CONTROL_IACK_SHIFT (0U) +/*! IACK - Interrupt Acknowledge + * 0b0..Do not clear the interrupt. + * 0b1..Clear the IF field (interrupt flag). + */ +#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) + +#define USBHSDCD_CONTROL_IF_MASK (0x100U) +#define USBHSDCD_CONTROL_IF_SHIFT (8U) +/*! IF - Interrupt Flag + * 0b0..No interrupt is pending. + * 0b1..An interrupt is pending. + */ +#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) + +#define USBHSDCD_CONTROL_IE_MASK (0x10000U) +#define USBHSDCD_CONTROL_IE_SHIFT (16U) +/*! IE - Interrupt Enable + * 0b0..Disable interrupts to the system. + * 0b1..Enable interrupts to the system. + */ +#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) + +#define USBHSDCD_CONTROL_BC12_MASK (0x20000U) +#define USBHSDCD_CONTROL_BC12_SHIFT (17U) +/*! BC12 - Battery Charging Revision 1.2 Compatibility + * 0b0..Compatible with BC1.1 + * 0b1..Compatible with BC1.2 (default) + */ +#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) + +#define USBHSDCD_CONTROL_START_MASK (0x1000000U) +#define USBHSDCD_CONTROL_START_SHIFT (24U) +/*! START - Start Change Detection Sequence + * 0b0..Do not start the sequence. Writes of this value have no effect. + * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. + */ +#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) + +#define USBHSDCD_CONTROL_SR_MASK (0x2000000U) +#define USBHSDCD_CONTROL_SR_SHIFT (25U) +/*! SR - Software Reset + * 0b0..Do not perform a software reset. + * 0b1..Perform a software reset. + */ +#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) +/*! @} */ + +/*! @name CLOCK - Clock */ +/*! @{ */ + +#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) +#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed + * 0b0..kHz Speed (between 4 kHz and 1023 kHz) + * 0b1..MHz Speed (between 1 MHz and 1023 MHz) + */ +#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) + +#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) +#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) +/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ +#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) +#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) +/*! SEQ_RES - Charger Detection Sequence Results + * 0b00..No results to report. + * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. + * 0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached + * to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The + * charger type detection has completed.) + * 0b11..Attached to a DCP. + */ +#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) + +#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) +#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) +/*! SEQ_STAT - Charger Detection Sequence Status + * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. + * 0b01..Data pin contact detection is complete. + * 0b10..Charging port detection is complete. + * 0b11..Charger type detection is complete. + */ +#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) + +#define USBHSDCD_STATUS_ERR_MASK (0x100000U) +#define USBHSDCD_STATUS_ERR_SHIFT (20U) +/*! ERR - Error Flag + * 0b0..No sequence errors. + * 0b1..Error in the detection sequence. + */ +#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) + +#define USBHSDCD_STATUS_TO_MASK (0x200000U) +#define USBHSDCD_STATUS_TO_SHIFT (21U) +/*! TO - Timeout Flag + * 0b0..The detection sequence is not running for over 1 s. + * 0b1..It is over 1 s since the data pin contact was detected and debounced. + */ +#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) + +#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) +#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) +/*! ACTIVE - Active Status Indicator + * 0b0..The sequence is not running. + * 0b1..The sequence is running. + */ +#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) +/*! @} */ + +/*! @name SIGNAL_OVERRIDE - Signal Override */ +/*! @{ */ + +#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x7U) +#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) +/*! PS - Phase Selection + * 0b000..No overrides. Field must remain at this value during normal USB data communication to prevent + * unexpected conditions on USB_DP and USB_DM pins. (Default) + * 0b001..Reserved, not for customer use. + * 0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. + * 0b011..Reserved, not for customer use. + * 0b100..Enables VDM_SRC voltage source only. + * 0b101..Reserved, not for customer use. + * 0b110..Reserved, not for customer use. + * 0b111..Reserved, not for customer use. + */ +#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) +/*! @} */ + +/*! @name TIMER0 - TIMER0 */ +/*! @{ */ + +#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) +#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) +/*! TUNITCON - Unit Connection Timer Elapse (in ms) */ +#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) + +#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) +#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) +/*! TSEQ_INIT - Sequence Initiation Time + * 0b0000000000-0b1111111111..0 ms - 1023 ms + */ +#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) +/*! @} */ + +/*! @name TIMER1 - TIMER1 */ +/*! @{ */ + +#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) +/*! TVDPSRC_ON - Time Period Comparator Enabled + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) + +#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) +#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) +/*! TDCD_DBNC - Time Period to Debounce D+ Signal + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) +/*! @} */ + +/*! @name TIMER2_BC11 - TIMER2_BC11 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) +#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) +/*! CHECK_DM - Time Before Check of D- Line + * 0b0001-0b1111..1 ms - 15 ms + */ +#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) + +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) +/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) +/*! @} */ + +/*! @name TIMER2_BC12 - TIMER2_BC12 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) +/*! TVDMSRC_ON - TVDMSRC_ON + * 0b0000000000-0b0000101000..0 ms - 40 ms + */ +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) + +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) +/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSDCD_Register_Masks */ + + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A000u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif +/* Backward compatibility */ +#define USBHSDCD_IRQS { USB1_HS_PHY_IRQn } +#define USB1_HS_PHY_IRQS USBPHY_IRQS + + +/*! + * @} + */ /* end of group USBHSDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name CTRL1 - USB OTG Control 1 */ +/*! @{ */ + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - Disable Overcurrent Detection + * 0b1..Disables + * 0b0..Enables + */ +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - Polarity of Overcurrent + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - Power Polarity + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - Wake-up Interrupt Enable + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - Software Wake-up Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - Software Wake-up + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - Wake-up on ID Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable + * 0b1..DPDM changes wake-up to be enabled, it is for device only + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 + */ +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - Wake-up Interrupt Request + * 0b1..Request received + * 0b0..No request received + */ +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Source Select + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - Low Speed Enable + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI Clock Valid + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_CTRL - USB Host HSIC Control */ +/*! @{ */ + +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) +/*! HSIC_CLK_ON - HSIC Clock ON + * 0b1..Active + * 0b0..Inactive + */ +#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) + +#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) +#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) +/*! HSIC_EN - Host HSIC Enable + * 0b1..Enabled + * 0b0..Disabled + */ +#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) + +#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) +#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) +/*! CLK_VLD - Clock Valid + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif +/* Backward compatibility */ +#define USB_OTGn_CTRL CTRL1 +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) +#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT +#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) +#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT +#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) + + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ + __IO uint32_t TX; /**< TX Control, offset: 0x10 */ + __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ + __IO uint32_t RX; /**< RX Control, offset: 0x20 */ + __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ + __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ + __IO uint32_t STATUS; /**< Status, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ + uint8_t RESERVED_1[32]; + __I uint32_t VERSION; /**< Version, offset: 0x80 */ + uint8_t RESERVED_2[12]; + __IO uint32_t IP; /**< IP Block, offset: 0x90 */ + __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ + __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ + __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ + __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ + uint8_t RESERVED_3[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ + __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ + __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ + __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ + __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ + __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ + __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ + __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ + __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ + uint8_t RESERVED_4[32]; + __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ + __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ + __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ + __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ + __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ + __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ + __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ + __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers + * 0b0..Provide bias to enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - TX Control */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - TX Control */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - TX Control */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - TX Control */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +/*! @} */ + +/*! @name RX - RX Control */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point + * 0b000..0.1000 V + * 0b001..0.1125 V + * 0b010..0.1250 V + * 0b011..0.0875 V + * 0b1xx.. + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point + * 0b000..0.56875 V + * 0b001..0.55000 V + * 0b010..0.58125 V + * 0b011..0.60000 V + * 0b1xx.. + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_SET - RX Control */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_CLR - RX Control */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_TOG - RX Control */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +/*! @} */ + +/*! @name CTRL - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt + * 0b0..Connected + * 0b1..Disconnected + */ +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity + * 0b0..Plugged in + * 0b1..Unplugged + */ +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt + * 0b0..No ID change interrupt + * 0b1..ID change interrupt + */ +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky + * 0b0..During the resume or reset state signaling period + * 0b1..Until you write 0 to it + */ +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt + * 0b0..No resume interrupt + * 0b1..Resume interrupt + */ +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend + * 0b0..Not suspended + * 0b1..Suspended + */ +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate + * 0b0..Run clocks + * 0b1..Gate clocks + */ +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset + * 0b0..Release from reset + * 0b1..Soft-reset + */ +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +/*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status + * 0b0..Not powered + * 0b1..Powered + */ +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS - Host Disconnect Status + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection + * 0b0..No attachment detected + * 0b1..Cable attachment detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +/*! OTGID_STATUS - OTG ID Status + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +/*! RESUME_STATUS - Resume Status */ +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name DEBUG0 - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode + * 0b00..Disconnect + * 0b01..Connect + */ +#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode + * 0b00..Disable + * 0b01..Enable + */ +#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name VERSION - Version */ +/*! @{ */ + +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +/*! STEP - Step */ +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) + +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +/*! MINOR - Minor */ +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) + +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +/*! MAJOR - Major */ +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name IP - IP Block */ +/*! @{ */ + +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_SET - IP Block */ +/*! @{ */ + +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_CLR - IP Block */ +/*! @{ */ + +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_TOG - IP Block */ +/*! @{ */ + +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name PLL_SIC - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control + * 0b0..Power up PLL + * 0b1..Power down PLL + */ +#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control + * 0b0..Power down + * 0b1..Allow powerup + */ +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL + * 0b0..480 MHz output clock + * 0b1..Input reference clock + */ +#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control + * 0b0..PLL_POWER internal state signal + * 0b1..REFBIAS_PWD + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration + * 0b000..Configure for a 32 MHz input clock (divide by 15) + * 0b001..Configure for a 30 MHz input clock (divide by 16) + * 0b010..Configure for a 24 MHz input clock (divide by 20) + * 0b011..Reserved, not usable for USB operation (divide by 22) + * 0b100..Configure for a 20 MHz input clock (divide by 24) + * 0b101..Configure for a 19.2 MHz input clock (divide by 25) + * 0b110..Configure for a 16 MHz input clock (divide by 30) + * 0b111..Configure for a 12 MHz input clock (divide by 40) + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator + * 0b0..Not locked + * 0b1..Locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold + * 0b000..4.0 V + * 0b001..4.1 V + * 0b010..4.2 V + * 0b011..4.3 V + * 0b100..4.4 V + * 0b101..4.5 V + * 0b110..4.6 V + * 0b111..4.7 V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable + * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND + * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection + * 0b0..VBUS_VALID comparator result + * 0b1..VBUS_VALID_3V comparator result + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection + * 0b00..VBUS_VALID comparator result + * 0b01..Session valid comparator result + * 0b10..Session valid comparator result + * 0b11.. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override + * 0b0..Use ID pin detector or external override + * 0b1..Allow local override of ID pin detection status + */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable + * 0b0..Internal detector or local override + * 0b1..External ID signal value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable + * 0b0..Internal detector or local override + * 0b1..External VBUS_VALID value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection + * 0b0..VBUS_VALID comparator + * 0b1..Session valid detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable + * 0bxx0..Disable or power down the VBUS_VALID comparator + * 0bxx1..Enable the VBUS_VALID comparator + * 0bx0x..Disable or power down the session valid detector + * 0bx1x..Enable the session valid detector + * 0b0xx..Disable or power down the VBUS_VALID_3V detector + * 0b1xx..Enable the VBUS_VALID_3V detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator + * 0b0..Above threshold + * 0b1..Below threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection + * 0b0..Fields in USB1_CHRG_DETECT + * 0b1..Fields and state machines in the USBHSDCD module + */ +#define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_SET - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output + * 0b0..SDP detected + * 0b1..Charging port detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage + * 0b0..USB_DM pin voltage is <= 0.8 V + * 0b1..USB_DM pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage + * 0b0..USB_DP pin voltage is <= 0.8 V + * 0b1..USB_DP pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output + * 0b0..CDP detected + * 0b1..DCP detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) +/*! @} */ + +/*! @name ANACTRL - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection + * 0b00..USB1PFDCLK = USB PLL reference clock + * 0b01..USB1PFDCLK = pfd_clk / 4 + * 0b10..USB1PFDCLK frequency = pfd_clk / 2 + * 0b11..USB1PFDCLK = pfd_clk + */ +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value + * 0b0..TRIM_OVERRIDE_EN + * 0b1..PLL_SIC + */ +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_SET - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_CLR - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_TOG - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name PFDA - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal + * 0b0..Not stable + * 0b1..Stable + */ +#define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_SET - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_CLR - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_TOG - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STATUSA; /**< Status A, offset: 0x10 */ + __IO uint32_t STATUSB; /**< Status B, offset: 0x14 */ + __IO uint32_t IRQENA; /**< Interrupt Enable A, offset: 0x18 */ + __IO uint32_t IRQENB; /**< Interrupt Enable B, offset: 0x1C */ + __IO uint32_t WAKENA; /**< Wake-up Enable A, offset: 0x20 */ + __IO uint32_t WAKENB; /**< Wake-up Enable B, offset: 0x24 */ + __IO uint32_t TAMPERA; /**< Tamper Enable A, offset: 0x28 */ + __IO uint32_t TAMPERB; /**< Tamper Enable B, offset: 0x2C */ + __IO uint32_t LOCKA; /**< Lock A, offset: 0x30 */ + __IO uint32_t LOCKB; /**< Lock B, offset: 0x34 */ + __IO uint32_t WAKECFG; /**< Wake-up Configuration, offset: 0x38 */ + uint8_t RESERVED_1[196]; + __IO uint32_t OSCCTLA; /**< Oscillator Control A, offset: 0x100 */ + __IO uint32_t OSCCTLB; /**< Oscillator Control B, offset: 0x104 */ + __IO uint32_t OSCCFGA; /**< Oscillator Configuration A, offset: 0x108 */ + __IO uint32_t OSCCFGB; /**< Oscillator Configuration B, offset: 0x10C */ + uint8_t RESERVED_2[8]; + __IO uint32_t OSCLCKA; /**< Oscillator Lock A, offset: 0x118 */ + __IO uint32_t OSCLCKB; /**< Oscillator Lock B, offset: 0x11C */ + __IO uint32_t OSCCLKE; /**< Oscillator Clock Enable, offset: 0x120 */ + uint8_t RESERVED_3[220]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + __IO uint32_t FROCTLB; /**< FRO16K Control B, offset: 0x204 */ + uint8_t RESERVED_4[16]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + __IO uint32_t FROLCKB; /**< FRO16K Lock B, offset: 0x21C */ + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_5[220]; + __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ + __IO uint32_t LDOCTLB; /**< LDO_RAM Control B, offset: 0x304 */ + uint8_t RESERVED_6[16]; + __IO uint32_t LDOLCKA; /**< LDO_RAM Lock A, offset: 0x318 */ + __IO uint32_t LDOLCKB; /**< LDO_RAM Lock B, offset: 0x31C */ + __IO uint32_t LDORAMC; /**< RAM Control, offset: 0x320 */ + uint8_t RESERVED_7[12]; + __IO uint32_t LDOTIMER0; /**< Bandgap Timer 0, offset: 0x330 */ + uint8_t RESERVED_8[4]; + __IO uint32_t LDOTIMER1; /**< Bandgap Timer 1, offset: 0x338 */ + uint8_t RESERVED_9[196]; + __IO uint32_t MONCTLA; /**< CLKMON Control A, offset: 0x400 */ + __IO uint32_t MONCTLB; /**< CLKMON Control B, offset: 0x404 */ + __IO uint32_t MONCFGA; /**< CLKMON Configuration A, offset: 0x408 */ + __IO uint32_t MONCFGB; /**< CLKMON Configuration B, offset: 0x40C */ + uint8_t RESERVED_10[8]; + __IO uint32_t MONLCKA; /**< CLKMON Lock A, offset: 0x418 */ + __IO uint32_t MONLCKB; /**< CLKMON Lock B, offset: 0x41C */ + uint8_t RESERVED_11[224]; + __IO uint32_t TAMCTLA; /**< TAMPER Control A, offset: 0x500 */ + __IO uint32_t TAMCTLB; /**< TAMPER Control B, offset: 0x504 */ + uint8_t RESERVED_12[16]; + __IO uint32_t TAMLCKA; /**< TAMPER Lock A, offset: 0x518 */ + __IO uint32_t TAMLCKB; /**< TAMPER Lock B, offset: 0x51C */ + uint8_t RESERVED_13[224]; + __IO uint32_t SWICTLA; /**< Switch Control A, offset: 0x600 */ + __IO uint32_t SWICTLB; /**< Switch Control B, offset: 0x604 */ + uint8_t RESERVED_14[16]; + __IO uint32_t SWILCKA; /**< Switch Lock A, offset: 0x618 */ + __IO uint32_t SWILCKB; /**< Switch Lock B, offset: 0x61C */ + uint8_t RESERVED_15[224]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPB; /**< Wakeup 0 Register B, array offset: 0x704, array step: 0x8 */ + } WAKEUP[2]; + uint8_t RESERVED_16[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ + __IO uint32_t WAKLCKB; /**< Wakeup Lock B, offset: 0x7FC */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name STATUSA - Status A */ +/*! @{ */ + +#define VBAT_STATUSA_POR_DET_MASK (0x1U) +#define VBAT_STATUSA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect Flag + * 0b0..Not reset + * 0b1..Reset + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK) + +#define VBAT_STATUSA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_STATUSA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Not asserted + * 0b1..Asserted + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK) + +#define VBAT_STATUSA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_STATUSA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK) + +#define VBAT_STATUSA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_STATUSA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 1 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK) + +#define VBAT_STATUSA_LDO_RDY_MASK (0x10U) +#define VBAT_STATUSA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disabled (not ready) + * 0b1..Enabled (ready) + */ +#define VBAT_STATUSA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK) + +#define VBAT_STATUSA_OSC_RDY_MASK (0x20U) +#define VBAT_STATUSA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disabled (clock not ready) + * 0b1..Enabled (clock ready) + */ +#define VBAT_STATUSA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_OSC_RDY_SHIFT)) & VBAT_STATUSA_OSC_RDY_MASK) + +#define VBAT_STATUSA_CLOCK_DET_MASK (0x40U) +#define VBAT_STATUSA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Clock error not detected + * 0b1..Clock error detected + */ +#define VBAT_STATUSA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CLOCK_DET_SHIFT)) & VBAT_STATUSA_CLOCK_DET_MASK) + +#define VBAT_STATUSA_CONFIG_DET_MASK (0x80U) +#define VBAT_STATUSA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CONFIG_DET_SHIFT)) & VBAT_STATUSA_CONFIG_DET_MASK) + +#define VBAT_STATUSA_VOLT_DET_MASK (0x100U) +#define VBAT_STATUSA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_VOLT_DET_SHIFT)) & VBAT_STATUSA_VOLT_DET_MASK) + +#define VBAT_STATUSA_TEMP_DET_MASK (0x200U) +#define VBAT_STATUSA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Temperature error not detected + * 0b1..Temperature error detected + */ +#define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) + +#define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) +#define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Light error not detected + * 0b1..Light error detected + */ +#define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) + +#define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) +#define VBAT_STATUSA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Security input 0 not detected + * 0b1..Security input 0 detected + */ +#define VBAT_STATUSA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_SEC0_DET_SHIFT)) & VBAT_STATUSA_SEC0_DET_MASK) + +#define VBAT_STATUSA_IRQ0_DET_MASK (0x10000U) +#define VBAT_STATUSA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ0_DET_SHIFT)) & VBAT_STATUSA_IRQ0_DET_MASK) + +#define VBAT_STATUSA_IRQ1_DET_MASK (0x20000U) +#define VBAT_STATUSA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ1_DET_SHIFT)) & VBAT_STATUSA_IRQ1_DET_MASK) + +#define VBAT_STATUSA_IRQ2_DET_MASK (0x40000U) +#define VBAT_STATUSA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ2_DET_SHIFT)) & VBAT_STATUSA_IRQ2_DET_MASK) + +#define VBAT_STATUSA_IRQ3_DET_MASK (0x80000U) +#define VBAT_STATUSA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ3_DET_SHIFT)) & VBAT_STATUSA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name STATUSB - Status B */ +/*! @{ */ + +#define VBAT_STATUSB_INVERSE_MASK (0xFFFFFU) +#define VBAT_STATUSB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_STATUSB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSB_INVERSE_SHIFT)) & VBAT_STATUSB_INVERSE_MASK) +/*! @} */ + +/*! @name IRQENA - Interrupt Enable A */ +/*! @{ */ + +#define VBAT_IRQENA_POR_DET_MASK (0x1U) +#define VBAT_IRQENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK) + +#define VBAT_IRQENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_IRQENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK) + +#define VBAT_IRQENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_IRQENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK) + +#define VBAT_IRQENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_IRQENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK) + +#define VBAT_IRQENA_LDO_RDY_MASK (0x10U) +#define VBAT_IRQENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK) + +#define VBAT_IRQENA_OSC_RDY_MASK (0x20U) +#define VBAT_IRQENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_OSC_RDY_SHIFT)) & VBAT_IRQENA_OSC_RDY_MASK) + +#define VBAT_IRQENA_CLOCK_DET_MASK (0x40U) +#define VBAT_IRQENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CLOCK_DET_SHIFT)) & VBAT_IRQENA_CLOCK_DET_MASK) + +#define VBAT_IRQENA_CONFIG_DET_MASK (0x80U) +#define VBAT_IRQENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CONFIG_DET_SHIFT)) & VBAT_IRQENA_CONFIG_DET_MASK) + +#define VBAT_IRQENA_VOLT_DET_MASK (0x100U) +#define VBAT_IRQENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_VOLT_DET_SHIFT)) & VBAT_IRQENA_VOLT_DET_MASK) + +#define VBAT_IRQENA_TEMP_DET_MASK (0x200U) +#define VBAT_IRQENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) + +#define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) +#define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) + +#define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) +#define VBAT_IRQENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_SEC0_DET_SHIFT)) & VBAT_IRQENA_SEC0_DET_MASK) + +#define VBAT_IRQENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_IRQENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ0_DET_SHIFT)) & VBAT_IRQENA_IRQ0_DET_MASK) + +#define VBAT_IRQENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_IRQENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ1_DET_SHIFT)) & VBAT_IRQENA_IRQ1_DET_MASK) + +#define VBAT_IRQENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_IRQENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ2_DET_SHIFT)) & VBAT_IRQENA_IRQ2_DET_MASK) + +#define VBAT_IRQENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_IRQENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ3_DET_SHIFT)) & VBAT_IRQENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name IRQENB - Interrupt Enable B */ +/*! @{ */ + +#define VBAT_IRQENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_IRQENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_IRQENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENB_INVERSE_SHIFT)) & VBAT_IRQENB_INVERSE_MASK) +/*! @} */ + +/*! @name WAKENA - Wake-up Enable A */ +/*! @{ */ + +#define VBAT_WAKENA_POR_DET_MASK (0x1U) +#define VBAT_WAKENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK) + +#define VBAT_WAKENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_WAKENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wake-up Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK) + +#define VBAT_WAKENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_WAKENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK) + +#define VBAT_WAKENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_WAKENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK) + +#define VBAT_WAKENA_LDO_RDY_MASK (0x10U) +#define VBAT_WAKENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK) + +#define VBAT_WAKENA_OSC_RDY_MASK (0x20U) +#define VBAT_WAKENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32K Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_OSC_RDY_SHIFT)) & VBAT_WAKENA_OSC_RDY_MASK) + +#define VBAT_WAKENA_CLOCK_DET_MASK (0x40U) +#define VBAT_WAKENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CLOCK_DET_SHIFT)) & VBAT_WAKENA_CLOCK_DET_MASK) + +#define VBAT_WAKENA_CONFIG_DET_MASK (0x80U) +#define VBAT_WAKENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CONFIG_DET_SHIFT)) & VBAT_WAKENA_CONFIG_DET_MASK) + +#define VBAT_WAKENA_VOLT_DET_MASK (0x100U) +#define VBAT_WAKENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_VOLT_DET_SHIFT)) & VBAT_WAKENA_VOLT_DET_MASK) + +#define VBAT_WAKENA_TEMP_DET_MASK (0x200U) +#define VBAT_WAKENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) + +#define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) +#define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) + +#define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) +#define VBAT_WAKENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disabled + * 0b1..Enabled + */ +#define VBAT_WAKENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_SEC0_DET_SHIFT)) & VBAT_WAKENA_SEC0_DET_MASK) + +#define VBAT_WAKENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_WAKENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ0_DET_SHIFT)) & VBAT_WAKENA_IRQ0_DET_MASK) + +#define VBAT_WAKENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_WAKENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ1_DET_SHIFT)) & VBAT_WAKENA_IRQ1_DET_MASK) + +#define VBAT_WAKENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_WAKENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ2_DET_SHIFT)) & VBAT_WAKENA_IRQ2_DET_MASK) + +#define VBAT_WAKENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_WAKENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ3_DET_SHIFT)) & VBAT_WAKENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name WAKENB - Wake-up Enable B */ +/*! @{ */ + +#define VBAT_WAKENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_WAKENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_WAKENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENB_INVERSE_SHIFT)) & VBAT_WAKENB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMPERA - Tamper Enable A */ +/*! @{ */ + +#define VBAT_TAMPERA_POR_DET_MASK (0x1U) +#define VBAT_TAMPERA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_POR_DET_SHIFT)) & VBAT_TAMPERA_POR_DET_MASK) + +#define VBAT_TAMPERA_CLOCK_DET_MASK (0x40U) +#define VBAT_TAMPERA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CLOCK_DET_SHIFT)) & VBAT_TAMPERA_CLOCK_DET_MASK) + +#define VBAT_TAMPERA_CONFIG_DET_MASK (0x80U) +#define VBAT_TAMPERA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CONFIG_DET_SHIFT)) & VBAT_TAMPERA_CONFIG_DET_MASK) + +#define VBAT_TAMPERA_VOLT_DET_MASK (0x100U) +#define VBAT_TAMPERA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_VOLT_DET_SHIFT)) & VBAT_TAMPERA_VOLT_DET_MASK) + +#define VBAT_TAMPERA_TEMP_DET_MASK (0x200U) +#define VBAT_TAMPERA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) + +#define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) +#define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) + +#define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) +#define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_SEC0_DET_SHIFT)) & VBAT_TAMPERA_SEC0_DET_MASK) +/*! @} */ + +/*! @name TAMPERB - Tamper Enable B */ +/*! @{ */ + +#define VBAT_TAMPERB_INVERSE_MASK (0xFFFFU) +#define VBAT_TAMPERB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMPERB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERB_INVERSE_SHIFT)) & VBAT_TAMPERB_INVERSE_MASK) +/*! @} */ + +/*! @name LOCKA - Lock A */ +/*! @{ */ + +#define VBAT_LOCKA_LOCK_MASK (0x1U) +#define VBAT_LOCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Disables lock + * 0b1..Enables lock. Cleared by VBAT POR. + */ +#define VBAT_LOCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK) +/*! @} */ + +/*! @name LOCKB - Lock B */ +/*! @{ */ + +#define VBAT_LOCKB_LOCK_MASK (0x1U) +#define VBAT_LOCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Disables lock + * 0b0..Enables lock + */ +#define VBAT_LOCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKB_LOCK_SHIFT)) & VBAT_LOCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKECFG - Wake-up Configuration */ +/*! @{ */ + +#define VBAT_WAKECFG_OUT_MASK (0x1U) +#define VBAT_WAKECFG_OUT_SHIFT (0U) +/*! OUT - Output + * 0b0..Logic zero (asserted) + * 0b1..Logic one + */ +#define VBAT_WAKECFG_OUT(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKECFG_OUT_SHIFT)) & VBAT_WAKECFG_OUT_MASK) +/*! @} */ + +/*! @name OSCCTLA - Oscillator Control A */ +/*! @{ */ + +#define VBAT_OSCCTLA_OSC_EN_MASK (0x1U) +#define VBAT_OSCCTLA_OSC_EN_SHIFT (0U) +/*! OSC_EN - Crystal Oscillator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_EN_SHIFT)) & VBAT_OSCCTLA_OSC_EN_MASK) + +#define VBAT_OSCCTLA_OSC_BYP_EN_MASK (0x2U) +#define VBAT_OSCCTLA_OSC_BYP_EN_SHIFT (1U) +/*! OSC_BYP_EN - Crystal Oscillator Bypass Enable + * 0b0..Does not bypass + * 0b1..Bypass + */ +#define VBAT_OSCCTLA_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_BYP_EN_SHIFT)) & VBAT_OSCCTLA_OSC_BYP_EN_MASK) + +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) +/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external + * crystal ESR values See the device datasheet for the ranges supported by this device + * 0b00..ESR Range 0 + * 0b01..ESR Range 1 + * 0b10..ESR Range 2 + * 0b11..ESR Range 3 + */ +#define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) + +#define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) +#define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) +/*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_CAP_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_CAP_SEL_EN_SHIFT)) & VBAT_OSCCTLA_CAP_SEL_EN_MASK) + +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK (0xF00U) +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT (8U) +/*! EXTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_EXTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) +#define VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT (12U) +/*! XTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_XTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) +#define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) +/*! MODE_EN - Mode Enable + * 0b00..Normal mode + * 0b01..Startup mode + * 0b11..Low power mode + */ +#define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) + +#define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) +#define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) +/*! SUPPLY_DET - Supply Detector Trim + * 0b00..VBAT supply is less than 3V + * 0b01..VBAT supply is greater than 3V + */ +#define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) +/*! @} */ + +/*! @name OSCCTLB - Oscillator Control B */ +/*! @{ */ + +#define VBAT_OSCCTLB_INVERSE_MASK (0xFFFFFU) +#define VBAT_OSCCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLB_INVERSE_SHIFT)) & VBAT_OSCCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCCFGA - Oscillator Configuration A */ +/*! @{ */ + +#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) +#define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) +/*! CMP_TRIM - Comparator Trim + * 0b00..760 mV + * 0b01..770 mV + * 0b11..740 mV + */ +#define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) +#define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) +/*! CAP2_TRIM - CAP2_TRIM */ +#define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) + +#define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) +#define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) +/*! DLY_TRIM - Delay Trim + * 0b0000..P current 9(nA) and N Current 6(nA) + * 0b0001..P current 13(nA) and N Current 6(nA) + * 0b0011..P current 4(nA) and N Current 6(nA) + * 0b0100..P current 9(nA) and N Current 4(nA) + * 0b0101..P current 13(nA) and N Current 4(nA) + * 0b0111..P current 4(nA) and N Current 4(nA) + * 0b1000..P current 9(nA) and N Current 2(nA) + * 0b1001..P current 13(nA) and N Current 2(nA) + * 0b1011..P current 4(nA) and N Current 2(nA) + */ +#define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) +#define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) +/*! CAP_TRIM - Capacitor Trim + * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) + * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) + * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) + * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) + */ +#define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) + +#define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) +#define VBAT_OSCCFGA_INIT_TRIM_SHIFT (9U) +/*! INIT_TRIM - Initialization Trim + * 0b000..8 s + * 0b001..4 s + * 0b010..2 s + * 0b011..1 s + * 0b100..0.5 s + * 0b101..0.25 s + * 0b110..0.125 s + * 0b111..0.5 ms + */ +#define VBAT_OSCCFGA_INIT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_INIT_TRIM_SHIFT)) & VBAT_OSCCFGA_INIT_TRIM_MASK) +/*! @} */ + +/*! @name OSCCFGB - Oscillator Configuration B */ +/*! @{ */ + +#define VBAT_OSCCFGB_INVERSE_MASK (0xFFFU) +#define VBAT_OSCCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGB_INVERSE_SHIFT)) & VBAT_OSCCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCLCKA - Oscillator Lock A */ +/*! @{ */ + +#define VBAT_OSCLCKA_LOCK_MASK (0x1U) +#define VBAT_OSCLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_OSCLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKA_LOCK_SHIFT)) & VBAT_OSCLCKA_LOCK_MASK) +/*! @} */ + +/*! @name OSCLCKB - Oscillator Lock B */ +/*! @{ */ + +#define VBAT_OSCLCKB_LOCK_MASK (0x1U) +#define VBAT_OSCLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_OSCLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKB_LOCK_SHIFT)) & VBAT_OSCLCKB_LOCK_MASK) +/*! @} */ + +/*! @name OSCCLKE - Oscillator Clock Enable */ +/*! @{ */ + +#define VBAT_OSCCLKE_CLKE_MASK (0xFU) +#define VBAT_OSCCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_OSCCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCLKE_CLKE_SHIFT)) & VBAT_OSCCLKE_CLKE_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROCTLB - FRO16K Control B */ +/*! @{ */ + +#define VBAT_FROCTLB_INVERSE_MASK (0x1U) +#define VBAT_FROCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_FROCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLB_INVERSE_SHIFT)) & VBAT_FROCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROLCKB - FRO16K Lock B */ +/*! @{ */ + +#define VBAT_FROLCKB_LOCK_MASK (0x1U) +#define VBAT_FROLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_FROLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKB_LOCK_SHIFT)) & VBAT_FROLCKB_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0xFU) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name LDOCTLA - LDO_RAM Control A */ +/*! @{ */ + +#define VBAT_LDOCTLA_BG_EN_MASK (0x1U) +#define VBAT_LDOCTLA_BG_EN_SHIFT (0U) +/*! BG_EN - Bandgap Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK) + +#define VBAT_LDOCTLA_LDO_EN_MASK (0x2U) +#define VBAT_LDOCTLA_LDO_EN_SHIFT (1U) +/*! LDO_EN - LDO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_LDO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK) + +#define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) +#define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) +/*! REFRESH_EN - Refresh Enable + * 0b0..Refresh mode is disabled + * 0b1..Refresh mode is enabled for low power operation + */ +#define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) +/*! @} */ + +/*! @name LDOCTLB - LDO_RAM Control B */ +/*! @{ */ + +#define VBAT_LDOCTLB_INVERSE_MASK (0x7U) +#define VBAT_LDOCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_LDOCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLB_INVERSE_SHIFT)) & VBAT_LDOCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name LDOLCKA - LDO_RAM Lock A */ +/*! @{ */ + +#define VBAT_LDOLCKA_LOCK_MASK (0x1U) +#define VBAT_LDOLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_LDOLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK) +/*! @} */ + +/*! @name LDOLCKB - LDO_RAM Lock B */ +/*! @{ */ + +#define VBAT_LDOLCKB_LOCK_MASK (0x1U) +#define VBAT_LDOLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_LDOLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKB_LOCK_SHIFT)) & VBAT_LDOLCKB_LOCK_MASK) +/*! @} */ + +/*! @name LDORAMC - RAM Control */ +/*! @{ */ + +#define VBAT_LDORAMC_ISO_MASK (0x1U) +#define VBAT_LDORAMC_ISO_SHIFT (0U) +/*! ISO - Isolate SRAM + * 0b0..State follows the chip power modes + * 0b1..Isolates SRAM and places it in Low-Power Retention mode + */ +#define VBAT_LDORAMC_ISO(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK) + +#define VBAT_LDORAMC_SWI_MASK (0x2U) +#define VBAT_LDORAMC_SWI_SHIFT (1U) +/*! SWI - Switch SRAM + * 0b0..Supply follows the chip power modes + * 0b1..LDO_RAM powers the array + */ +#define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) + +#define VBAT_LDORAMC_RET0_MASK (0x100U) +#define VBAT_LDORAMC_RET0_SHIFT (8U) +/*! RET0 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) + +#define VBAT_LDORAMC_RET1_MASK (0x200U) +#define VBAT_LDORAMC_RET1_SHIFT (9U) +/*! RET1 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) + +#define VBAT_LDORAMC_RET2_MASK (0x400U) +#define VBAT_LDORAMC_RET2_SHIFT (10U) +/*! RET2 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) + +#define VBAT_LDORAMC_RET3_MASK (0x800U) +#define VBAT_LDORAMC_RET3_SHIFT (11U) +/*! RET3 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) +/*! @} */ + +/*! @name LDOTIMER0 - Bandgap Timer 0 */ +/*! @{ */ + +#define VBAT_LDOTIMER0_TIMCFG_MASK (0x7U) +#define VBAT_LDOTIMER0_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration + * 0b111..7.8125 ms + * 0b110..15.625 ms + * 0b101..31.25 ms + * 0b100..62.5 ms + * 0b011..125 ms + * 0b010..250 ms + * 0b001..500 ms + * 0b000..1 s + */ +#define VBAT_LDOTIMER0_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK) + +#define VBAT_LDOTIMER0_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER0_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER0_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK) +/*! @} */ + +/*! @name LDOTIMER1 - Bandgap Timer 1 */ +/*! @{ */ + +#define VBAT_LDOTIMER1_TIMCFG_MASK (0xFFFFFFU) +#define VBAT_LDOTIMER1_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration */ +#define VBAT_LDOTIMER1_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK) + +#define VBAT_LDOTIMER1_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER1_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER1_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK) +/*! @} */ + +/*! @name MONCTLA - CLKMON Control A */ +/*! @{ */ + +#define VBAT_MONCTLA_MON_EN_MASK (0x1U) +#define VBAT_MONCTLA_MON_EN_SHIFT (0U) +/*! MON_EN - CLKMON Enable + * 0b0..CLKMON is disabled + * 0b1..CLKMON is enabled + */ +#define VBAT_MONCTLA_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLA_MON_EN_SHIFT)) & VBAT_MONCTLA_MON_EN_MASK) +/*! @} */ + +/*! @name MONCTLB - CLKMON Control B */ +/*! @{ */ + +#define VBAT_MONCTLB_INVERSE_MASK (0x1U) +#define VBAT_MONCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLB_INVERSE_SHIFT)) & VBAT_MONCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name MONCFGA - CLKMON Configuration A */ +/*! @{ */ + +#define VBAT_MONCFGA_FREQ_TRIM_MASK (0x3U) +#define VBAT_MONCFGA_FREQ_TRIM_SHIFT (0U) +/*! FREQ_TRIM - Frequency Trim + * 0b00..Clock monitor asserts 2 cycle after expected edge + * 0b01..Clock monitor asserts 4 cycles after expected edge + * 0b10..Clock monitor asserts 6 cycles after expected edge + * 0b11..Clock monitor asserts 8 cycles after expected edge + */ +#define VBAT_MONCFGA_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_FREQ_TRIM_SHIFT)) & VBAT_MONCFGA_FREQ_TRIM_MASK) + +#define VBAT_MONCFGA_DIVIDE_TRIM_MASK (0x4U) +#define VBAT_MONCFGA_DIVIDE_TRIM_SHIFT (2U) +/*! DIVIDE_TRIM - Divide Trim + * 0b0..Clock monitor operates at 1 kHz + * 0b1..Clock monitor operates at 64 Hz + */ +#define VBAT_MONCFGA_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_DIVIDE_TRIM_SHIFT)) & VBAT_MONCFGA_DIVIDE_TRIM_MASK) + +#define VBAT_MONCFGA_RSVD_TRIM_MASK (0xF8U) +#define VBAT_MONCFGA_RSVD_TRIM_SHIFT (3U) +/*! RSVD_TRIM - Reserved Trim */ +#define VBAT_MONCFGA_RSVD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_RSVD_TRIM_SHIFT)) & VBAT_MONCFGA_RSVD_TRIM_MASK) +/*! @} */ + +/*! @name MONCFGB - CLKMON Configuration B */ +/*! @{ */ + +#define VBAT_MONCFGB_INVERSE_MASK (0xFFU) +#define VBAT_MONCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGB_INVERSE_SHIFT)) & VBAT_MONCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name MONLCKA - CLKMON Lock A */ +/*! @{ */ + +#define VBAT_MONLCKA_LOCK_MASK (0x1U) +#define VBAT_MONLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_MONLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKA_LOCK_SHIFT)) & VBAT_MONLCKA_LOCK_MASK) +/*! @} */ + +/*! @name MONLCKB - CLKMON Lock B */ +/*! @{ */ + +#define VBAT_MONLCKB_LOCK_MASK (0x1U) +#define VBAT_MONLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_MONLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKB_LOCK_SHIFT)) & VBAT_MONLCKB_LOCK_MASK) +/*! @} */ + +/*! @name TAMCTLA - TAMPER Control A */ +/*! @{ */ + +#define VBAT_TAMCTLA_VOLT_EN_MASK (0x1U) +#define VBAT_TAMCTLA_VOLT_EN_SHIFT (0U) +/*! VOLT_EN - Voltage Detect Enable + * 0b0..Voltage detect is disabled + * 0b1..Voltage detect is enabled + */ +#define VBAT_TAMCTLA_VOLT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_VOLT_EN_SHIFT)) & VBAT_TAMCTLA_VOLT_EN_MASK) + +#define VBAT_TAMCTLA_TEMP_EN_MASK (0x2U) +#define VBAT_TAMCTLA_TEMP_EN_SHIFT (1U) +/*! TEMP_EN - Temperature Detect Enable + * 0b0..Temperature detect is disabled + * 0b1..Temperature detect is enabled + */ +#define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) + +#define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) +#define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) +/*! LIGHT_EN - Light Detect Enable + * 0b0..Light detect is disabled + * 0b1..Light detect is enabled + */ +#define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) +/*! @} */ + +/*! @name TAMCTLB - TAMPER Control B */ +/*! @{ */ + +#define VBAT_TAMCTLB_INVERSE_MASK (0xFU) +#define VBAT_TAMCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLB_INVERSE_SHIFT)) & VBAT_TAMCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMLCKA - TAMPER Lock A */ +/*! @{ */ + +#define VBAT_TAMLCKA_LOCK_MASK (0x1U) +#define VBAT_TAMLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_TAMLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKA_LOCK_SHIFT)) & VBAT_TAMLCKA_LOCK_MASK) +/*! @} */ + +/*! @name TAMLCKB - TAMPER Lock B */ +/*! @{ */ + +#define VBAT_TAMLCKB_LOCK_MASK (0x1U) +#define VBAT_TAMLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_TAMLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKB_LOCK_SHIFT)) & VBAT_TAMLCKB_LOCK_MASK) +/*! @} */ + +/*! @name SWICTLA - Switch Control A */ +/*! @{ */ + +#define VBAT_SWICTLA_SWI_EN_MASK (0x1U) +#define VBAT_SWICTLA_SWI_EN_SHIFT (0U) +/*! SWI_EN - Switch Enable + * 0b0..VDD_BAT + * 0b1..VDD_SYS + */ +#define VBAT_SWICTLA_SWI_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_SWI_EN_SHIFT)) & VBAT_SWICTLA_SWI_EN_MASK) + +#define VBAT_SWICTLA_LP_EN_MASK (0x2U) +#define VBAT_SWICTLA_LP_EN_SHIFT (1U) +/*! LP_EN - Low Power Enable + * 0b0..VDD_BAT always supplies VBAT modules in low-power modes + * 0b1..VDD_SYS always supplies VBAT modules if SWI_EN is also 1 + */ +#define VBAT_SWICTLA_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_LP_EN_SHIFT)) & VBAT_SWICTLA_LP_EN_MASK) +/*! @} */ + +/*! @name SWICTLB - Switch Control B */ +/*! @{ */ + +#define VBAT_SWICTLB_INVERSE_MASK (0x3U) +#define VBAT_SWICTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_SWICTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLB_INVERSE_SHIFT)) & VBAT_SWICTLB_INVERSE_MASK) +/*! @} */ + +/*! @name SWILCKA - Switch Lock A */ +/*! @{ */ + +#define VBAT_SWILCKA_LOCK_MASK (0x1U) +#define VBAT_SWILCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_SWILCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKA_LOCK_SHIFT)) & VBAT_SWILCKA_LOCK_MASK) +/*! @} */ + +/*! @name SWILCKB - Switch Lock B */ +/*! @{ */ + +#define VBAT_SWILCKB_LOCK_MASK (0x1U) +#define VBAT_SWILCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_SWILCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKB_LOCK_SHIFT)) & VBAT_SWILCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKEUP_WAKEUPB - Wakeup 0 Register B */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPB_INVERSE_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_WAKEUP_WAKEUPB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT)) & VBAT_WAKEUP_WAKEUPB_INVERSE_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPB */ +#define VBAT_WAKEUP_WAKEUPB_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + +/*! @name WAKLCKB - Wakeup Lock B */ +/*! @{ */ + +#define VBAT_WAKLCKB_LOCK_MASK (0x1U) +#define VBAT_WAKLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_WAKLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKB_LOCK_SHIFT)) & VBAT_WAKLCKB_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VREF_VERID_FEATURE_MASK (0xFFFFU) +#define VREF_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) + +#define VREF_VERID_MINOR_MASK (0xFF0000U) +#define VREF_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) + +#define VREF_VERID_MAJOR_MASK (0xFF000000U) +#define VREF_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CSR - Control and Status */ +/*! @{ */ + +#define VREF_CSR_HCBGEN_MASK (0x1U) +#define VREF_CSR_HCBGEN_SHIFT (0U) +/*! HCBGEN - HC Bandgap Enabled + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) + +#define VREF_CSR_LPBGEN_MASK (0x2U) +#define VREF_CSR_LPBGEN_SHIFT (1U) +/*! LPBGEN - Low-Power Bandgap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) + +#define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) +#define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) +/*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) + +#define VREF_CSR_CHOPEN_MASK (0x8U) +#define VREF_CSR_CHOPEN_SHIFT (3U) +/*! CHOPEN - Chop Oscillator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) + +#define VREF_CSR_ICOMPEN_MASK (0x10U) +#define VREF_CSR_ICOMPEN_SHIFT (4U) +/*! ICOMPEN - Current Compensation Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) + +#define VREF_CSR_REGEN_MASK (0x20U) +#define VREF_CSR_REGEN_SHIFT (5U) +/*! REGEN - Regulator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) + +#define VREF_CSR_HI_PWR_LV_MASK (0x800U) +#define VREF_CSR_HI_PWR_LV_SHIFT (11U) +/*! HI_PWR_LV - High-Power Level + * 0b0..Low-power + * 0b1..High-power + */ +#define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) + +#define VREF_CSR_BUF21EN_MASK (0x10000U) +#define VREF_CSR_BUF21EN_SHIFT (16U) +/*! BUF21EN - Internal Buffer21 Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) + +#define VREF_CSR_VREFST_MASK (0x80000000U) +#define VREF_CSR_VREFST_SHIFT (31U) +/*! VREFST - Internal HC Voltage Reference Stable + * 0b0..Disabled and unstable + * 0b1..Stable + */ +#define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) +/*! @} */ + +/*! @name UTRIM - User Trim */ +/*! @{ */ + +#define VREF_UTRIM_TRIM2V1_MASK (0xFU) +#define VREF_UTRIM_TRIM2V1_SHIFT (0U) +/*! TRIM2V1 - VREF 2.1 V Trim */ +#define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) + +#define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) +#define VREF_UTRIM_VREFTRIM_SHIFT (8U) +/*! VREFTRIM - VREF Trim */ +#define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + * *.. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_WUPE0_MASK (0x3U) +#define WUU_PE1_WUPE0_SHIFT (0U) +/*! WUPE0 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK) + +#define WUU_PE1_WUPE1_MASK (0xCU) +#define WUU_PE1_WUPE1_SHIFT (2U) +/*! WUPE1 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_WUPE3_MASK (0xC0U) +#define WUU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) + +#define WUU_PE1_WUPE4_MASK (0x300U) +#define WUU_PE1_WUPE4_SHIFT (8U) +/*! WUPE4 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) + +#define WUU_PE1_WUPE5_MASK (0xC00U) +#define WUU_PE1_WUPE5_SHIFT (10U) +/*! WUPE5 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_WUPE13_MASK (0xC000000U) +#define WUU_PE1_WUPE13_SHIFT (26U) +/*! WUPE13 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) + +#define WUU_PE1_WUPE14_MASK (0x30000000U) +#define WUU_PE1_WUPE14_SHIFT (28U) +/*! WUPE14 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK) + +#define WUU_PE1_WUPE15_MASK (0xC0000000U) +#define WUU_PE1_WUPE15_SHIFT (30U) +/*! WUPE15 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_WUPE21_MASK (0xC00U) +#define WUU_PE2_WUPE21_SHIFT (10U) +/*! WUPE21 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_Reserved28_MASK (0x3000000U) +#define WUU_PE2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK) + +#define WUU_PE2_Reserved29_MASK (0xC000000U) +#define WUU_PE2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK) + +#define WUU_PE2_Reserved30_MASK (0x30000000U) +#define WUU_PE2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved30_SHIFT)) & WUU_PE2_Reserved30_MASK) + +#define WUU_PE2_Reserved31_MASK (0xC0000000U) +#define WUU_PE2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved31_SHIFT)) & WUU_PE2_Reserved31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME1_MASK (0x2U) +#define WUU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME3_MASK (0x8U) +#define WUU_ME_WUME3_SHIFT (3U) +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) + +#define WUU_ME_WUME4_MASK (0x10U) +#define WUU_ME_WUME4_SHIFT (4U) +/*! WUME4 - Module Interrupt Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) + +#define WUU_ME_WUME5_MASK (0x20U) +#define WUU_ME_WUME5_SHIFT (5U) +/*! WUME5 - Module Interrupt Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME7_MASK (0x80U) +#define WUU_ME_WUME7_SHIFT (7U) +/*! WUME7 - Module Interrupt Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) + +#define WUU_ME_WUME9_MASK (0x200U) +#define WUU_ME_WUME9_SHIFT (9U) +/*! WUME9 - Module Interrupt Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE0_MASK (0x1U) +#define WUU_DE_WUDE0_SHIFT (0U) +/*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) + +#define WUU_DE_WUDE1_MASK (0x2U) +#define WUU_DE_WUDE1_SHIFT (1U) +/*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) + +#define WUU_DE_WUDE2_MASK (0x4U) +#define WUU_DE_WUDE2_SHIFT (2U) +/*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) + +#define WUU_DE_WUDE3_MASK (0x8U) +#define WUU_DE_WUDE3_SHIFT (3U) +/*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE5_MASK (0x20U) +#define WUU_DE_WUDE5_SHIFT (5U) +/*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE7_MASK (0x80U) +#define WUU_DE_WUDE7_SHIFT (7U) +/*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) + +#define WUU_DE_WUDE9_MASK (0x200U) +#define WUU_DE_WUDE9_SHIFT (9U) +/*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_WUF0_MASK (0x1U) +#define WUU_PF_WUF0_SHIFT (0U) +/*! WUF0 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK) + +#define WUU_PF_WUF1_MASK (0x2U) +#define WUU_PF_WUF1_SHIFT (1U) +/*! WUF1 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_WUF3_MASK (0x8U) +#define WUU_PF_WUF3_SHIFT (3U) +/*! WUF3 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) + +#define WUU_PF_WUF4_MASK (0x10U) +#define WUU_PF_WUF4_SHIFT (4U) +/*! WUF4 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) + +#define WUU_PF_WUF5_MASK (0x20U) +#define WUU_PF_WUF5_SHIFT (5U) +/*! WUF5 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_WUF13_MASK (0x2000U) +#define WUU_PF_WUF13_SHIFT (13U) +/*! WUF13 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) + +#define WUU_PF_WUF14_MASK (0x4000U) +#define WUU_PF_WUF14_SHIFT (14U) +/*! WUF14 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK) + +#define WUU_PF_WUF15_MASK (0x8000U) +#define WUU_PF_WUF15_SHIFT (15U) +/*! WUF15 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_WUF21_MASK (0x200000U) +#define WUU_PF_WUF21_SHIFT (21U) +/*! WUF21 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_Reserved28_MASK (0x10000000U) +#define WUU_PF_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK) + +#define WUU_PF_Reserved29_MASK (0x20000000U) +#define WUU_PF_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK) + +#define WUU_PF_Reserved30_MASK (0x40000000U) +#define WUU_PF_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved30_SHIFT)) & WUU_PF_Reserved30_MASK) + +#define WUU_PF_Reserved31_MASK (0x80000000U) +#define WUU_PF_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved31_SHIFT)) & WUU_PF_Reserved31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_WUPDC0_MASK (0x3U) +#define WUU_PDC1_WUPDC0_SHIFT (0U) +/*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK) + +#define WUU_PDC1_WUPDC1_MASK (0xCU) +#define WUU_PDC1_WUPDC1_SHIFT (2U) +/*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_WUPDC3_MASK (0xC0U) +#define WUU_PDC1_WUPDC3_SHIFT (6U) +/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) + +#define WUU_PDC1_WUPDC4_MASK (0x300U) +#define WUU_PDC1_WUPDC4_SHIFT (8U) +/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) + +#define WUU_PDC1_WUPDC5_MASK (0xC00U) +#define WUU_PDC1_WUPDC5_SHIFT (10U) +/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_WUPDC13_MASK (0xC000000U) +#define WUU_PDC1_WUPDC13_SHIFT (26U) +/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) + +#define WUU_PDC1_WUPDC14_MASK (0x30000000U) +#define WUU_PDC1_WUPDC14_SHIFT (28U) +/*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK) + +#define WUU_PDC1_WUPDC15_MASK (0xC0000000U) +#define WUU_PDC1_WUPDC15_SHIFT (30U) +/*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_WUPDC21_MASK (0xC00U) +#define WUU_PDC2_WUPDC21_SHIFT (10U) +/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_Reserved28_MASK (0x3000000U) +#define WUU_PDC2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK) + +#define WUU_PDC2_Reserved29_MASK (0xC000000U) +#define WUU_PDC2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK) + +#define WUU_PDC2_Reserved30_MASK (0x30000000U) +#define WUU_PDC2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved30_SHIFT)) & WUU_PDC2_Reserved30_MASK) + +#define WUU_PDC2_Reserved31_MASK (0xC0000000U) +#define WUU_PDC2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_WUPMC0_MASK (0x1U) +#define WUU_PMC_WUPMC0_SHIFT (0U) +/*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK) + +#define WUU_PMC_WUPMC1_MASK (0x2U) +#define WUU_PMC_WUPMC1_SHIFT (1U) +/*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_WUPMC3_MASK (0x8U) +#define WUU_PMC_WUPMC3_SHIFT (3U) +/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) + +#define WUU_PMC_WUPMC4_MASK (0x10U) +#define WUU_PMC_WUPMC4_SHIFT (4U) +/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) + +#define WUU_PMC_WUPMC5_MASK (0x20U) +#define WUU_PMC_WUPMC5_SHIFT (5U) +/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_WUPMC13_MASK (0x2000U) +#define WUU_PMC_WUPMC13_SHIFT (13U) +/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) + +#define WUU_PMC_WUPMC14_MASK (0x4000U) +#define WUU_PMC_WUPMC14_SHIFT (14U) +/*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK) + +#define WUU_PMC_WUPMC15_MASK (0x8000U) +#define WUU_PMC_WUPMC15_SHIFT (15U) +/*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_WUPMC21_MASK (0x200000U) +#define WUU_PMC_WUPMC21_SHIFT (21U) +/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_Reserved28_MASK (0x10000000U) +#define WUU_PMC_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK) + +#define WUU_PMC_Reserved29_MASK (0x20000000U) +#define WUU_PMC_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK) + +#define WUU_PMC_Reserved30_MASK (0x40000000U) +#define WUU_PMC_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved30_SHIFT)) & WUU_PMC_Reserved30_MASK) + +#define WUU_PMC_Reserved31_MASK (0x80000000U) +#define WUU_PMC_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved31_SHIFT)) & WUU_PMC_Reserved31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) + +#define WWDT_MOD_DEBUG_EN_MASK (0x40U) +#define WWDT_MOD_DEBUG_EN_SHIFT (6U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN236_H_ */ + diff --git a/devices/MCXN236/MCXN236_features.h b/devices/MCXN236/MCXN236_features.h new file mode 100644 index 000000000..d343f88e8 --- /dev/null +++ b/devices/MCXN236/MCXN236_features.h @@ -0,0 +1,900 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b240407 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN236_FEATURES_H_ +#define _MCXN236_FEATURES_H_ + +/* SOC module features */ + +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) + +/* CDOG module features */ + +/* @brief CDOG Has No Reset */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ + (((x) == DMA0) ? (16) : \ + (((x) == DMA1) ? (8) : (-1))) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _MCXN236_FEATURES_H_ */ + diff --git a/devices/MCXN236/all_lib_device.cmake b/devices/MCXN236/all_lib_device.cmake new file mode 100644 index 000000000..8d161cbe5 --- /dev/null +++ b/devices/MCXN236/all_lib_device.cmake @@ -0,0 +1,1104 @@ +# Copy variable into project config.cmake to use software component +#set.board.frdmmcxn236 +# # description: Board_project_template frdmmcxn236 +# set(CONFIG_USE_BOARD_Project_Template_frdmmcxn236 true) + +#set.device.MCXN236 +# # description: utilitiy for MCXN236 +# set(CONFIG_USE_device_MCXN236_utility_frdmmcxn236 true) + +# # description: Middleware baremetal +# set(CONFIG_USE_middleware_baremetal true) + +# # description: Used to include slave core binary into master core binary. +# set(CONFIG_USE_utility_incbin true) + +# # description: Utilities which is needed for particular toolchain like the SBRK function required to address limitation between HEAP and STACK in GCC toolchain library. +# set(CONFIG_USE_utilities_misc_utilities true) + +# # description: Utilities unity +# set(CONFIG_USE_utilities_unity true) + +# # description: RTT template configuration +# set(CONFIG_USE_driver_rtt_template true) + +# # description: Driver nand_flash-common +# set(CONFIG_USE_driver_nand_flash-common true) + +# # description: Driver nor_flash-common +# set(CONFIG_USE_driver_nor_flash-common true) + +# # description: mflash common +# set(CONFIG_USE_component_mflash_common true) + +# # description: Driver mx25r_flash +# set(CONFIG_USE_driver_mx25r_flash true) + +# # description: Driver pf1550 +# set(CONFIG_USE_driver_pf1550 true) + +# # description: Driver pf3000 +# set(CONFIG_USE_driver_pf3000 true) + +# # description: Driver phy-common +# set(CONFIG_USE_driver_phy-common true) + +# # description: Driver p3t1755 +# set(CONFIG_USE_driver_p3t1755 true) + +# # description: Wi-Fi module Tx power limits +# set(CONFIG_USE_component_wifi_bt_module_tx_pwr_limits true) + +# # description: Wi-Fi and BT module configs +# set(CONFIG_USE_component_wifi_bt_module_config true) + +# # description: Devices_project_template MCXN236 +# set(CONFIG_USE_DEVICES_Project_Template_MCXN236 true) + +# # description: Device MCXN236_startup +# set(CONFIG_USE_device_MCXN236_startup true) + +# # description: Device MCXN236_cmsis +# set(CONFIG_USE_device_MCXN236_CMSIS true) + +# # description: Rte_device +# set(CONFIG_USE_RTE_Device true) + +# # description: Component serial_manager_uart +# set(CONFIG_USE_component_serial_manager_uart true) + +# # description: Clock Driver +# set(CONFIG_USE_driver_clock true) + +# # description: EDMA Driver +# set(CONFIG_USE_driver_edma4 true) + +# # description: EDMA SOC Driver +# set(CONFIG_USE_driver_edma_soc true) + +# # description: FLEXIO MCULCD EDMA Driver +# set(CONFIG_USE_driver_flexio_mculcd_edma true) + +# # description: FLEXIO MCULCD SMARTDMA Driver +# set(CONFIG_USE_driver_flexio_mculcd_smartdma true) + +# # description: SAI EDMA Driver +# set(CONFIG_USE_driver_sai_edma true) + +# # description: LPUART EDMA Driver +# set(CONFIG_USE_driver_lpuart_edma true) + +# # description: LPSPI EDMA Driver +# set(CONFIG_USE_driver_lpspi_edma true) + +# # description: LPI2C EDMA Driver +# set(CONFIG_USE_driver_lpi2c_edma true) + +# # description: LPUART CMSIS Driver +# set(CONFIG_USE_driver_cmsis_lpuart true) + +# # description: LPSPI CMSIS Driver +# set(CONFIG_USE_driver_cmsis_lpspi true) + +# # description: LPI2C CMSIS Driver +# set(CONFIG_USE_driver_cmsis_lpi2c true) + +# # description: FLEXCAN Driver +# set(CONFIG_USE_driver_flexcan_edma true) + +# # description: FLEXIO SPI EDMA Driver +# set(CONFIG_USE_driver_flexio_spi_edma true) + +# # description: FLEXIO UART EDMA Driver +# set(CONFIG_USE_driver_flexio_uart_edma true) + +# # description: PDM EDMA Driver +# set(CONFIG_USE_driver_pdm_edma true) + +# # description: Utility notifier +# set(CONFIG_USE_utility_notifier true) + +# # description: Inputmux_connections Driver +# set(CONFIG_USE_driver_inputmux_connections true) + +# # description: COMMON Driver +# set(CONFIG_USE_driver_common true) + +# # description: Utility assert +# set(CONFIG_USE_utility_assert true) + +# # description: Utility assert_lite +# set(CONFIG_USE_utility_assert_lite true) + +# # description: Utility str +# set(CONFIG_USE_utility_str true) + +# # description: Utility debug_console_lite +# set(CONFIG_USE_utility_debug_console_lite true) + +# # description: Utility debug_console +# set(CONFIG_USE_utility_debug_console true) + +# # description: Device MCXN236_system +# set(CONFIG_USE_device_MCXN236_system true) + +# # description: SEGGER Real Time Transfer(RTT) +# set(CONFIG_USE_driver_rtt true) + +# # description: TDET Driver +# set(CONFIG_USE_driver_tdet true) + +# # description: SYSPM Driver +# set(CONFIG_USE_driver_syspm true) + +# # description: PUFv3 Driver +# set(CONFIG_USE_driver_puf_v3 true) + +# # description: LPCMP Driver +# set(CONFIG_USE_driver_lpcmp true) + +# # description: VREF Driver +# set(CONFIG_USE_driver_vref_1 true) + +# # description: LPADC Driver +# set(CONFIG_USE_driver_lpadc true) + +# # description: itrc Driver +# set(CONFIG_USE_driver_itrc true) + +# # description: INTM Driver +# set(CONFIG_USE_driver_intm true) + +# # description: Driver dbi +# set(CONFIG_USE_driver_dbi true) + +# # description: Driver dbi_flexio_edma +# set(CONFIG_USE_driver_dbi_flexio_edma true) + +# # description: MCX_CMC Driver +# set(CONFIG_USE_driver_mcx_cmc true) + +# # description: EIM Driver +# set(CONFIG_USE_driver_eim true) + +# # description: ERM Driver +# set(CONFIG_USE_driver_erm true) + +# # description: MCX VBAT Driver +# set(CONFIG_USE_driver_mcx_vbat true) + +# # description: MCX SPC Driver +# set(CONFIG_USE_driver_mcx_spc true) + +# # description: CRC Driver +# set(CONFIG_USE_driver_crc true) + +# # description: cdog Driver +# set(CONFIG_USE_driver_cdog true) + +# # description: CACHE Driver +# set(CONFIG_USE_driver_cache_lpcac true) + +# # description: SMARTDMA Driver +# set(CONFIG_USE_driver_lpc_smartdma true) + +# # description: Reset Driver +# set(CONFIG_USE_driver_reset true) + +# # description: Component sai_edma_adapter +# set(CONFIG_USE_component_audio_sai_edma_adapter true) + +# # description: Component button +# set(CONFIG_USE_component_button true) + +# # description: Driver codec +# set(CONFIG_USE_driver_codec true) + +# # description: Component codec adapters for multi codec +# set(CONFIG_USE_component_codec_adapters true) + +# # description: Component wm8904 adapter for single codec +# set(CONFIG_USE_component_wm8904_adapter true) + +# # description: Component wm8960 adapter for single codecs +# set(CONFIG_USE_component_wm8960_adapter true) + +# # description: Component cs42888 adapter for single codec +# set(CONFIG_USE_component_cs42888_adapter true) + +# # description: Component sgtl5000 adapter for single codec +# set(CONFIG_USE_component_sgtl_adapter true) + +# # description: Component da7212 adapter for single codec +# set(CONFIG_USE_component_da7212_adapter true) + +# # description: Component codec_i2c +# set(CONFIG_USE_component_codec_i2c true) + +# # description: Component crc_adapter +# set(CONFIG_USE_component_crc_adapter true) + +# # description: Component software_crc_adapter +# set(CONFIG_USE_component_software_crc_adapter true) + +# # description: Driver cs42888 +# set(CONFIG_USE_driver_cs42888 true) + +# # description: Driver dialog7212 +# set(CONFIG_USE_driver_dialog7212 true) + +# # description: Driver nor_flash-controller-lpspi +# set(CONFIG_USE_driver_nor_flash-controller-lpspi true) + +# # description: Driver gt911 +# set(CONFIG_USE_driver_gt911 true) + +# # description: Driver ft5406_rt +# set(CONFIG_USE_driver_ft5406_rt true) + +# # description: Driver ft5406 +# set(CONFIG_USE_driver_ft5406 true) + +# # description: Driver ft6x06 +# set(CONFIG_USE_driver_ft6x06 true) + +# # description: Driver fxos8700cq +# set(CONFIG_USE_driver_fxos8700cq true) + +# # description: Component gpio_adapter +# set(CONFIG_USE_component_gpio_adapter true) + +# # description: Component lpi2c_adapter +# set(CONFIG_USE_component_lpi2c_adapter true) + +# # description: Component i3c_adapter +# set(CONFIG_USE_component_i3c_adapter true) + +# # description: Component i3c_bus +# set(CONFIG_USE_component_i3c_bus true) + +# # description: Component i3c_bus_adapter +# set(CONFIG_USE_component_i3c_bus_adapter true) + +# # description: Driver ili9341 +# set(CONFIG_USE_driver_ili9341 true) + +# # description: Component led +# set(CONFIG_USE_component_led true) + +# # description: Component lists +# set(CONFIG_USE_component_lists true) + +# # description: Component log +# set(CONFIG_USE_component_log true) + +# # description: Component log backend debug console +# set(CONFIG_USE_component_log_backend_debugconsole true) + +# # description: Component log backend debug console lite +# set(CONFIG_USE_component_log_backend_debugconsole_lite true) + +# # description: Component log backend ring buffer +# set(CONFIG_USE_component_log_backend_ringbuffer true) + +# # description: Component mem_manager +# set(CONFIG_USE_component_mem_manager true) + +# # description: Component mem_manager_light +# set(CONFIG_USE_component_mem_manager_light true) + +# # description: mflash file +# set(CONFIG_USE_component_mflash_file true) + +# # description: dummy file for overwriting mflash when dowloading +# set(CONFIG_USE_component_mflash_dummy true) + +# # description: mflash mcxnx4x +# set(CONFIG_USE_component_mflash_mcxnx4x_onchip true) + +# # description: Driver mma8451q +# set(CONFIG_USE_driver_mma8451q true) + +# # description: Driver mma8652fc +# set(CONFIG_USE_driver_mma8652fc true) + +# # description: Component panic +# set(CONFIG_USE_component_panic true) + +# # description: Driver phy-device-lan8741 +# set(CONFIG_USE_driver_phy-device-lan8741 true) + +# # description: Component pwm_ctimer_adapter +# set(CONFIG_USE_component_pwm_ctimer_adapter true) + +# # description: Component reset_adapter +# set(CONFIG_USE_component_reset_adapter true) + +# # description: Component software_rng_adapter +# set(CONFIG_USE_component_software_rng_adapter true) + +# # description: Component serial_manager +# set(CONFIG_USE_component_serial_manager true) + +# # description: Component serial_manager_spi +# set(CONFIG_USE_component_serial_manager_spi true) + +# # description: Component serial_manager_usb_cdc +# set(CONFIG_USE_component_serial_manager_usb_cdc true) + +# # description: Component serial_manager_virtual +# set(CONFIG_USE_component_serial_manager_virtual true) + +# # description: Component serial_manager_swo +# set(CONFIG_USE_component_serial_manager_swo true) + +# # description: Driver sgtl5000 +# set(CONFIG_USE_driver_sgtl5000 true) + +# # description: Utility shell +# set(CONFIG_USE_utility_shell true) + +# # description: Component lpspi_adapter +# set(CONFIG_USE_component_lpspi_adapter true) + +# # description: Component ctimer_adapter +# set(CONFIG_USE_component_ctimer_adapter true) + +# # description: Component lptmr_adapter +# set(CONFIG_USE_component_lptmr_adapter true) + +# # description: Component mrt_adapter +# set(CONFIG_USE_component_mrt_adapter true) + +# # description: Component ostimer_adapter +# set(CONFIG_USE_component_ostimer_adapter true) + +# # description: Component timer_manager +# set(CONFIG_USE_component_timer_manager true) + +# # description: Component lpuart_adapter +# set(CONFIG_USE_component_lpuart_adapter true) + +# # description: Component lpuart_dma_adapter +# set(CONFIG_USE_component_lpuart_dma_adapter true) + +# # description: Driver wm8904 +# set(CONFIG_USE_driver_wm8904 true) + +# # description: Driver wm8960 +# set(CONFIG_USE_driver_wm8960 true) + +# # description: Driver st7796s +# set(CONFIG_USE_driver_st7796s true) + +# # description: Driver ssd1963 +# set(CONFIG_USE_driver_ssd1963 true) + +# # description: Driver camera-receiver-common +# set(CONFIG_USE_driver_camera-receiver-common true) + +# # description: Driver camera-device-common +# set(CONFIG_USE_driver_camera-device-common true) + +# # description: Driver camera-device-sccb +# set(CONFIG_USE_driver_camera-device-sccb true) + +# # description: Driver camera-device-ov7670 +# set(CONFIG_USE_driver_camera-device-ov7670 true) + +# # description: Driver camera-common +# set(CONFIG_USE_driver_camera-common true) + +# # description: Driver video-common +# set(CONFIG_USE_driver_video-common true) + +# # description: Driver dbi_flexio_smartdma +# set(CONFIG_USE_driver_dbi_flexio_smartdma true) + +# # description: ROMAPI Driver +# set(CONFIG_USE_driver_flashiap true) + +# # description: ROMAPI Driver +# set(CONFIG_USE_driver_mem_interface true) + +# # description: ROMAPI Driver +# set(CONFIG_USE_driver_runbootloader true) + +# # description: WUU Driver +# set(CONFIG_USE_driver_wuu true) + +# # description: INPUTMUX Driver +# set(CONFIG_USE_driver_inputmux true) + +# # description: CTimer Driver +# set(CONFIG_USE_driver_ctimer true) + +# # description: MRT Driver +# set(CONFIG_USE_driver_mrt true) + +# # description: WWDT Driver +# set(CONFIG_USE_driver_wwdt true) + +# # description: UTICK Driver +# set(CONFIG_USE_driver_utick true) + +# # description: OSTimer Driver +# set(CONFIG_USE_driver_ostimer true) + +# # description: EVTG Driver +# set(CONFIG_USE_driver_evtg true) + +# # description: PWM Driver +# set(CONFIG_USE_driver_pwm true) + +# # description: QDC Driver +# set(CONFIG_USE_driver_qdc true) + +# # description: IRTC Driver +# set(CONFIG_USE_driver_irtc true) + +# # description: lpc_freqme Driver +# set(CONFIG_USE_driver_lpc_freqme true) + +# # description: LPTMR Driver +# set(CONFIG_USE_driver_lptmr true) + +# # description: EWM Driver +# set(CONFIG_USE_driver_ewm true) + +# # description: LPFLEXCOMM Driver +# set(CONFIG_USE_driver_lpflexcomm true) + +# # description: LPI2C Driver +# set(CONFIG_USE_driver_lpi2c true) + +# # description: LPI2C Driver +# set(CONFIG_USE_driver_lpflexcomm_lpi2c_freertos true) + +# # description: LPSPI Driver +# set(CONFIG_USE_driver_lpspi true) + +# # description: LPSPI FreeRTOS driver +# set(CONFIG_USE_driver_lpflexcomm_lpspi_freertos true) + +# # description: LPUART Driver +# set(CONFIG_USE_driver_lpuart true) + +# # description: lpflexcomm LPUART driver +# set(CONFIG_USE_driver_lpflexcomm_lpuart_freertos true) + +# # description: SAI Driver +# set(CONFIG_USE_driver_sai true) + +# # description: FLEXCAN Driver +# set(CONFIG_USE_driver_flexcan true) + +# # description: FLEXIO Driver +# set(CONFIG_USE_driver_flexio true) + +# # description: FLEXIO MCULCD Driver +# set(CONFIG_USE_driver_flexio_mculcd true) + +# # description: FLEXIO I2C Driver +# set(CONFIG_USE_driver_flexio_i2c_master true) + +# # description: FLEXIO SPI Driver +# set(CONFIG_USE_driver_flexio_spi true) + +# # description: FLEXIO UART Driver +# set(CONFIG_USE_driver_flexio_uart true) + +# # description: I3C EDMA Driver +# set(CONFIG_USE_driver_i3c_edma true) + +# # description: I3C Driver +# set(CONFIG_USE_driver_i3c true) + +# # description: GPIO Driver +# set(CONFIG_USE_driver_gpio true) + +# # description: PINT Driver +# set(CONFIG_USE_driver_pint true) + +# # description: PORT Driver +# set(CONFIG_USE_driver_port true) + +# # description: PDM Driver +# set(CONFIG_USE_driver_pdm true) + +#set.CMSIS +# # description: CMSIS-CORE for Cortex-M, ARMv8-M, ARMv8.1-M +# set(CONFIG_USE_CMSIS_Include_core_cm true) + +# # description: Access to #include Driver_USART.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_USART true) + +# # description: Access to #include Driver_CAN.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_CAN true) + +# # description: Access to #include Driver_ETH.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_Ethernet true) + +# # description: Access to #include Driver_ETH_MAC.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_Ethernet_MAC true) + +# # description: Access to #include Driver_ETH_PHY.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_Ethernet_PHY true) + +# # description: Access to #include Driver_Flash.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_Flash true) + +# # description: Access to #include Driver_I2C.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_I2C true) + +# # description: Access to #include Driver_MCI.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_MCI true) + +# # description: Access to #include Driver_NAND.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_NAND true) + +# # description: Access to #include Driver_SAI.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_SAI true) + +# # description: Access to #include Driver_SPI.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_SPI true) + +# # description: Access to #include Driver_USBD.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_USB_Device true) + +# # description: Access to #include Driver_USBH.h file for custom implementation +# set(CONFIG_USE_CMSIS_Driver_Include_USB_Host true) + +# # description: Access to #include Driver_WiFi.h file +# set(CONFIG_USE_CMSIS_Driver_Include_WiFi true) + +# # description: Device interrupt controller interface +# set(CONFIG_USE_CMSIS_Device_API_OSTick true) + +# # description: CMSIS-RTOS API for Cortex-M, SC000, and SC300 +# set(CONFIG_USE_CMSIS_Device_API_RTOS2 true) + +# # description: CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library) +# set(CONFIG_USE_CMSIS_RTOS2_Secure true) + +# # description: CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library) +# set(CONFIG_USE_CMSIS_RTOS2_NonSecure true) + +#set.CMSIS_DSP_Lib +# # description: CMSIS-DSP Library Header +# set(CONFIG_USE_CMSIS_DSP_Include true) + +# # description: CMSIS-DSP Library +# set(CONFIG_USE_CMSIS_DSP_Source true) + +# # description: CMSIS-NN Library +# set(CONFIG_USE_CMSIS_NN_Source true) + +#set.middleware.mbedtls +# # description: mbedTLS Template +# set(CONFIG_USE_middleware_mbedtls_template true) + +# # description: els_pkc config +# set(CONFIG_USE_middleware_mbedtls_els_pkc_config true) + +# # description: mbedTLS port library for PKC +# set(CONFIG_USE_middleware_mbedtls_port_els_pkc true) + +# # description: mbedTLS port library for ELS +# set(CONFIG_USE_middleware_mbedtls_port_els true) + +# # description: mbedTLS library +# set(CONFIG_USE_middleware_mbedtls true) + +#set.component.els_pkc +# # description: Component els_pkc.core +# set(CONFIG_USE_component_els_pkc_core true) + +# # description: Component els_pkc.data_integrity +# set(CONFIG_USE_component_els_pkc_data_integrity true) + +# # description: Component els_header_only +# set(CONFIG_USE_component_els_pkc_els_header_only true) + +# # description: Component els_pkc.padding +# set(CONFIG_USE_component_els_pkc_padding true) + +# # description: Component els_pkc.pre_processor +# set(CONFIG_USE_component_els_pkc_pre_processor true) + +# # description: Component els_pkc.secure_counter +# set(CONFIG_USE_component_els_pkc_secure_counter true) + +# # description: Component els_pkc toolchain +# set(CONFIG_USE_component_els_pkc_toolchain true) + +# # description: Component els_pkc.doc.mcxn +# set(CONFIG_USE_component_els_pkc_doc_mcxn true) + +# # description: Component els_pkc static_lib MCXN +# set(CONFIG_USE_component_els_pkc_static_lib_mcxn true) + +# # description: Component els pkc common +# set(CONFIG_USE_component_els_pkc_common true) + +# # description: Component els_pkc.aead +# set(CONFIG_USE_component_els_pkc_aead true) + +# # description: Component els_pkc.aead_modes +# set(CONFIG_USE_component_els_pkc_aead_modes true) + +# # description: Component aes +# set(CONFIG_USE_component_els_pkc_aes true) + +# # description: Component els_pkc.cipher +# set(CONFIG_USE_component_els_pkc_cipher true) + +# # description: Component els_pkc.cipher +# set(CONFIG_USE_component_els_pkc_cipher_modes true) + +# # description: Component els_pkc.ecc +# set(CONFIG_USE_component_els_pkc_ecc true) + +# # description: Component els_pkc els_common +# set(CONFIG_USE_component_els_pkc_els_common true) + +# # description: Component els_pkc standalone_keyManagement +# set(CONFIG_USE_component_els_pkc_standalone_keyManagement true) + +# # description: Component els_pkc standalone_gdet +# set(CONFIG_USE_component_els_pkc_standalone_gdet true) + +# # description: Component els +# set(CONFIG_USE_component_els_pkc_els true) + +# # description: Component els_pkc.hash +# set(CONFIG_USE_component_els_pkc_hash true) + +# # description: Component els_pkc.hashmodes +# set(CONFIG_USE_component_els_pkc_hashmodes true) + +# # description: Component els_pkc.key +# set(CONFIG_USE_component_els_pkc_key true) + +# # description: Component els_pkc.mac +# set(CONFIG_USE_component_els_pkc_mac true) + +# # description: Component els_pkc.hmac +# set(CONFIG_USE_component_els_pkc_hmac true) + +# # description: Component els_pkc.mac_modes +# set(CONFIG_USE_component_els_pkc_mac_modes true) + +# # description: Component els_pkc.math +# set(CONFIG_USE_component_els_pkc_math true) + +# # description: Component els_pkc.memory +# set(CONFIG_USE_component_els_pkc_memory true) + +# # description: Component els_pkc.oscca_pkc +# set(CONFIG_USE_component_els_pkc_oscca_pkc true) + +# # description: Component els_pkc.oscca_sm3 +# set(CONFIG_USE_component_els_pkc_oscca_sm3 true) + +# # description: Component pkc +# set(CONFIG_USE_component_els_pkc_pkc true) + +# # description: Component prng +# set(CONFIG_USE_component_els_pkc_prng true) + +# # description: Component els_pkc.random +# set(CONFIG_USE_component_els_pkc_random true) + +# # description: Component els_pkc.random_modes +# set(CONFIG_USE_component_els_pkc_random_modes true) + +# # description: Component els_pkc.random_modes_ctr +# set(CONFIG_USE_component_els_pkc_random_modes_ctr true) + +# # description: Component els_pkc.rsa +# set(CONFIG_USE_component_els_pkc_rsa true) + +# # description: Component els_pkc.session +# set(CONFIG_USE_component_els_pkc_session true) + +# # description: Component els_pkc.trng +# set(CONFIG_USE_component_els_pkc_trng true) + +# # description: Component els_pkc.trng.type_els +# set(CONFIG_USE_component_els_pkc_trng_type_els true) + +# # description: Component els_pkc.trng.type_rng4 +# set(CONFIG_USE_component_els_pkc_trng_type_rng4 true) + +# # description: Component els_pkc.flow_protection +# set(CONFIG_USE_component_els_pkc_flow_protection true) + +# # description: Component els_pkc.param_integrity +# set(CONFIG_USE_component_els_pkc_param_integrity true) + +# # description: Component els_pkc of Crypto Lib +# set(CONFIG_USE_component_els_pkc true) + +# # description: Component els_pkc_mcxn +# set(CONFIG_USE_component_els_pkc_platform_mcxn true) + +# # description: Component els_pkc_test +# set(CONFIG_USE_component_els_pkc_examples true) + +#set.middleware.fatfs +# # description: FatFs template MMC +# set(CONFIG_USE_middleware_fatfs_template_mmc true) + +# # description: FatFs template NAND +# set(CONFIG_USE_middleware_fatfs_template_nand true) + +# # description: FatFs template RAM +# set(CONFIG_USE_middleware_fatfs_template_ram true) + +# # description: FatFs template SD +# set(CONFIG_USE_middleware_fatfs_template_sd true) + +# # description: FatFs template SDSPI +# set(CONFIG_USE_middleware_fatfs_template_sdspi true) + +# # description: FatFs template USB +# set(CONFIG_USE_middleware_fatfs_template_usb true) + +# # description: FatFs +# set(CONFIG_USE_middleware_fatfs true) + +# # description: FatFs_RAM +# set(CONFIG_USE_middleware_fatfs_ram true) + +# # description: FatFs_USB +# set(CONFIG_USE_middleware_fatfs_usb true) + +#set.middleware.usb +# # description: USB device phydcd config header +# set(CONFIG_USE_middleware_usb_phydcd_config_header true) + +# # description: USB device hsdcd config header +# set(CONFIG_USE_middleware_usb_hsdcd_config_header true) + +# # description: Middleware usb host ehci +# set(CONFIG_USE_middleware_usb_host_ehci true) + +# # description: Middleware usb host audio +# set(CONFIG_USE_middleware_usb_host_audio true) + +# # description: Middleware usb host cdc +# set(CONFIG_USE_middleware_usb_host_cdc true) + +# # description: Middleware usb host cdc_rndis +# set(CONFIG_USE_middleware_usb_host_cdc_rndis true) + +# # description: Middleware usb host hid +# set(CONFIG_USE_middleware_usb_host_hid true) + +# # description: Middleware usb host msd +# set(CONFIG_USE_middleware_usb_host_msd true) + +# # description: Middleware usb host video +# set(CONFIG_USE_middleware_usb_host_video true) + +# # description: Middleware usb host phdc +# set(CONFIG_USE_middleware_usb_host_phdc true) + +# # description: Middleware usb host printer +# set(CONFIG_USE_middleware_usb_host_printer true) + +# # description: Middleware usb host common_header +# set(CONFIG_USE_middleware_usb_host_common_header true) + +# # description: USB host ehci config header +# set(CONFIG_USE_middleware_usb_host_ehci_config_header true) + +# # description: Middleware usb host stack +# set(CONFIG_USE_middleware_usb_host_stack true) + +# # description: USB device ehci config header +# set(CONFIG_USE_middleware_usb_device_ehci_config_header true) + +# # description: Middleware usb common_header +# set(CONFIG_USE_middleware_usb_common_header true) + +# # description: Middleware usb device common_header +# set(CONFIG_USE_middleware_usb_device_common_header true) + +# # description: Middleware usb device ehci +# set(CONFIG_USE_middleware_usb_device_ehci true) + +# # description: Middleware usb phy +# set(CONFIG_USE_middleware_usb_phy true) + +# # description: Middleware usb device stack external +# set(CONFIG_USE_middleware_usb_device_stack_external true) + +# # description: Middleware usb device audio external +# set(CONFIG_USE_middleware_usb_device_audio_external true) + +# # description: Middleware usb device cdc external +# set(CONFIG_USE_middleware_usb_device_cdc_external true) + +# # description: Middleware usb device cdc rndis external +# set(CONFIG_USE_middleware_usb_device_cdc_rndis_external true) + +# # description: Middleware usb device hid external +# set(CONFIG_USE_middleware_usb_device_hid_external true) + +# # description: Middleware usb device dfu external +# set(CONFIG_USE_middleware_usb_device_dfu_external true) + +# # description: Middleware usb device msd external +# set(CONFIG_USE_middleware_usb_device_msd_external true) + +# # description: Middleware usb device phdc external +# set(CONFIG_USE_middleware_usb_device_phdc_external true) + +# # description: Middleware usb device video external +# set(CONFIG_USE_middleware_usb_device_video_external true) + +# # description: Middleware usb device ccid external +# set(CONFIG_USE_middleware_usb_device_ccid_external true) + +# # description: Middleware usb device printer external +# set(CONFIG_USE_middleware_usb_device_printer_external true) + +# # description: Middleware usb HSDCD (Select manually if needed) +# set(CONFIG_USE_middleware_usb_hsdcd true) + +# # description: Middleware usb device controller driver +# set(CONFIG_USE_middleware_usb_device_controller_driver true) + +#set.middleware.littlefs +# # description: littlefs +# set(CONFIG_USE_middleware_littlefs true) + +#set.middleware.freertos-kernel +# # description: FreeRTOS NXP extension +# set(CONFIG_USE_middleware_freertos-kernel_extension true) + +# # description: Template configuration file to be edited by user. Provides also memory allocator (heap_x), change variant if needed. +# set(CONFIG_USE_middleware_freertos-kernel_template true) + +# # description: FreeRTOS kernel +# set(CONFIG_USE_middleware_freertos-kernel true) + +# # description: FreeRTOS cm33 non trustzone port +# set(CONFIG_USE_middleware_freertos-kernel_cm33_non_trustzone true) + +# # description: FreeRTOS cm33 secure port +# set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_non_secure true) + +# # description: FreeRTOS heap 1 +# set(CONFIG_USE_middleware_freertos-kernel_heap_1 true) + +# # description: FreeRTOS heap 2 +# set(CONFIG_USE_middleware_freertos-kernel_heap_2 true) + +# # description: FreeRTOS heap 3 +# set(CONFIG_USE_middleware_freertos-kernel_heap_3 true) + +# # description: FreeRTOS heap 4 +# set(CONFIG_USE_middleware_freertos-kernel_heap_4 true) + +# # description: FreeRTOS heap 5 +# set(CONFIG_USE_middleware_freertos-kernel_heap_5 true) + +# # description: FreeRTOS MPU wrappers +# set(CONFIG_USE_middleware_freertos-kernel_mpu_wrappers true) + +# # description: FreeRTOS cm33 TrustZone secure port +# set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure_context true) + +# # description: FreeRTOS Secure Context +# set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure true) + +#set.middleware.maestro_framework +# # description: maestro_framework template +# set(CONFIG_USE_middleware_maestro_framework_template true) + +# # description: MCU Maestro Audio Framework Doc +# set(CONFIG_USE_middleware_maestro_framework_doc true) + +# # description: MCU Maestro Audio Framework Codecs +# set(CONFIG_USE_middleware_maestro_framework_codecs true) + +# # description: MCU Maestro Audio Framework Streamer Core +# set(CONFIG_USE_middleware_maestro_framework true) + +# # description: MCU Maestro Audio Framework Opus +# set(CONFIG_USE_middleware_maestro_framework_opus true) + +# # description: MCU Maestro Audio Framework Opusfile +# set(CONFIG_USE_middleware_maestro_framework_opusfile true) + +# # description: MCU Maestro Audio Framework Ogg +# set(CONFIG_USE_middleware_maestro_framework_ogg true) + +# # description: MCU Maestro Audio Framework ASRC +# set(CONFIG_USE_middleware_maestro_framework_asrc true) + +#set.middleware.multicore +# # description: Multicore SDK +# set(CONFIG_USE_middleware_multicore true) + +# # description: eRPC +# set(CONFIG_USE_middleware_multicore_erpc_common true) + +# # description: eRPC_arbitrator +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_arbitrator true) + +# # description: eRPC_client +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_client true) + +# # description: eRPC_server +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_server true) + +# # description: eRPC_rpmsg_tty_rtos_remote_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_tty_rtos_remote_c_wrapper true) + +# # description: eRPC_mu_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_mu_c_wrapper true) + +# # description: eRPC_rpmsg_lite_master_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_master_c_wrapper true) + +# # description: eRPC_rpmsg_lite_remote_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_remote_c_wrapper true) + +# # description: eRPC_rpmsg_lite_rtos_master_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_rtos_master_c_wrapper true) + +# # description: eRPC_rpmsg_lite_rtos_remote_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_rtos_remote_c_wrapper true) + +# # description: eRPC_dspi_master_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_dspi_master_c_wrapper true) + +# # description: eRPC_dspi_slave_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_dspi_slave_c_wrapper true) + +# # description: eRPC_spi_master_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_spi_master_c_wrapper true) + +# # description: eRPC_spi_slave_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_spi_slave_c_wrapper true) + +# # description: eRPC_lpspi_slave_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_lpspi_slave_c_wrapper true) + +# # description: eRPC_i2c_slave_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_i2c_slave_c_wrapper true) + +# # description: eRPC_lpi2c_slave_c_wrapper +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_lpi2c_slave_c_wrapper true) + +# # description: eRPC_mu_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_mu_transport true) + +# # description: eRPC_mu_rtos_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_mu_rtos_transport true) + +# # description: eRPC_rpmsg_lite_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_transport true) + +# # description: eRPC_rpmsg_lite_rtos_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_lite_rtos_transport true) + +# # description: eRPC_rpmsg_tty_rtos_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_rpmsg_tty_rtos_transport true) + +# # description: eRPC_uart_cmsis_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_uart_cmsis_transport true) + +# # description: eRPC_dspi_master_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_dspi_master_transport true) + +# # description: eRPC_dspi_slave_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_dspi_slave_transport true) + +# # description: eRPC_spi_master_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_spi_master_transport true) + +# # description: eRPC_spi_slave_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_spi_slave_transport true) + +# # description: eRPC_lpspi_slave_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_lpspi_slave_transport true) + +# # description: eRPC_i2c_slave_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_i2c_slave_transport true) + +# # description: eRPC_lpi2c_slave_transport +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_lpi2c_slave_transport true) + +# # description: eRPC_port_freertos +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_port_freertos true) + +# # description: eRPC_port_stdlib +# set(CONFIG_USE_middleware_multicore_erpc_eRPC_port_stdlib true) + +# # description: erpc_doc +# set(CONFIG_USE_middleware_multicore_erpc_doc true) + +# # description: eRPC +# set(CONFIG_USE_middleware_multicore_erpc true) + +# # description: erpc multiprocessor examples common files +# set(CONFIG_USE_middleware_multicore_erpc_common_multiprocessor true) + +# # description: erpc multiprocessor matrix_multiply_client examples common files +# set(CONFIG_USE_middleware_multicore_erpc_common_multiprocessor_matrix_multiply_client true) + +# # description: erpc multiprocessor matrix_multiply_server examples common files +# set(CONFIG_USE_middleware_multicore_erpc_common_multiprocessor_matrix_multiply_server true) + +#set.component.osa +# # description: Component common_task +# set(CONFIG_USE_component_common_task true) + +# # description: Component osa_bm +# set(CONFIG_USE_component_osa_bm true) + +# # description: Component osa_free_rtos +# set(CONFIG_USE_component_osa_free_rtos true) + +# # description: Component osa +# set(CONFIG_USE_component_osa true) + +# # description: Component osa interface +# set(CONFIG_USE_component_osa_interface true) + +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/. + ${CMAKE_CURRENT_LIST_DIR}/../../components/els_pkc + ${CMAKE_CURRENT_LIST_DIR}/../../components/osa + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/fatfs + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/littlefs + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/maestro + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/mbedtls + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/multicore + ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/usb + ${CMAKE_CURRENT_LIST_DIR}/../../../rtos/freertos/freertos-kernel + ${CMAKE_CURRENT_LIST_DIR}/drivers + ${CMAKE_CURRENT_LIST_DIR}/project_template + ${CMAKE_CURRENT_LIST_DIR}/template + ${CMAKE_CURRENT_LIST_DIR}/../../CMSIS + ${CMAKE_CURRENT_LIST_DIR}/../../boards/frdmmcxn236 +) + +include(set_board_frdmmcxn236 OPTIONAL) +include(set_CMSIS_DSP_Lib OPTIONAL) +include(set_CMSIS OPTIONAL) +include(set_device_MCXN236 OPTIONAL) +include(set_component_osa OPTIONAL) +include(set_component_els_pkc OPTIONAL) +include(set_middleware_fatfs OPTIONAL) +include(set_middleware_freertos-kernel OPTIONAL) +include(set_middleware_littlefs OPTIONAL) +include(set_middleware_maestro_framework OPTIONAL) +include(set_middleware_mbedtls OPTIONAL) +include(set_middleware_multicore OPTIONAL) +include(set_middleware_usb OPTIONAL) diff --git a/devices/MCXN236/drivers/fsl_clock.c b/devices/MCXN236/drivers/fsl_clock.c new file mode 100644 index 000000000..c9c30292d --- /dev/null +++ b/devices/MCXN236/drivers/fsl_clock.c @@ -0,0 +1,2695 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_NDIV_VAL_P (0U) /* NDIV is in bits 7:0 */ +#define PLL_NDIV_VAL_M (0xFFUL << PLL_NDIV_VAL_P) +#define PLL_MDIV_VAL_P (0U) /* MDIV is in bits 15:0 */ +#define PLL_MDIV_VAL_M (0xFFFFULL << PLL_MDIV_VAL_P) +#define PLL_PDIV_VAL_P (0U) /* PDIV is in bits 4:0 */ +#define PLL_PDIV_VAL_M (0x1FUL << PLL_PDIV_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (32000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDIV reg */ +#define PLL_NDIV_VAL_SET(value) (((unsigned long)(value) << PLL_NDIV_VAL_P) & PLL_NDIV_VAL_M) +/* PLL MDIV reg */ +#define PLL_MDIV_VAL_SET(value) (((unsigned long long)(value) << PLL_MDIV_VAL_P) & PLL_MDIV_VAL_M) +/* PLL PDIV reg */ +#define PLL_PDIV_VAL_SET(value) (((unsigned long)(value) << PLL_PDIV_VAL_P) & PLL_PDIV_VAL_M) + +/* PLL SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +#define PLL_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_FRACT_P) & PLL_SSCG_MD_FRACT_M) +#define PLL_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_INT_P) & PLL_SSCG_MD_INT_M) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; +/*! @brief External XTAL32K clock frequency. */ +volatile static uint32_t s_Xtal32_Freq = 32768U; +/*! @brief SAI MCLK clock frequency. */ +volatile static uint32_t s_Sai_Mclk_Freq[2] = {0U}; +/*! @brief SAI TX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Tx_Bclk_Freq[2] = {0U}; +/*! @brief SAI RX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Rx_Bclk_Freq[2] = {0U}; + +/*! @brief external UPLL clock frequency. */ +static uint32_t s_extUpllFreq = 0U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get CLK 48M Clk */ +static uint32_t CLOCK_GetClk48MFreq(void); +/* Get CLK 144M Clk */ +static uint32_t CLOCK_GetClk144MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get OSC 32K Clk */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id); +/* Get Systick Clk */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id); +/* Get CLOCK OUT Clk */ +static uint32_t CLOCK_GetClockOutClkFreq(void); +/* Get LP_OSC Clk */ +static uint32_t CLOCK_GetLposcFreq(void); + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void); +/* Get postdivider (P) from PLL1 PDIV setting */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL0 MDIV and SSCG settings */ +static float findPll0MMult(void); +/* Get multiplier (M) from PLL1 MDIV and SSCG settings */ +static float findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Set PLL0 output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup); +/* Get predivider (N) from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup); +/* Get postdivider (P) from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup); +/* Get multiplier (M) from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_48MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + if ((iFreq != 48000000U) && (iFreq != 144000000U)) + { + return kStatus_Fail; + } + + /* Select 48MHz or 144MHz for FIRC clock */ + SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable FIRC 48 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC 144 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /*Configure SOSC range */ + SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the OSC 32K. + * @param id : OSC 32 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id) +{ + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK | SCG_LDOCSR_VOUT_OK_MASK; + + VBAT0->OSCCTLA = + (VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) | + VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK; + VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E); + /* Wait for STATUSA[OSC_RDY] to set. */ + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + VBAT0->OSCLCKA = VBAT_OSCLCKA_LOCK_MASK; + VBAT0->OSCLCKB &= ~VBAT_OSCLCKA_LOCK_MASK; + + VBAT0->OSCCLKE |= VBAT_OSCCLKE_CLKE(id); + + /* De-initializes the SCG ROSC */ + SCG0->ROSCCSR = SCG_ROSCCSR_ROSCERR_MASK; + + /* Unlock ROSCCSR */ + SCG0->ROSCCSR &= ~SCG_ROSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable ROSC */ + SCG0->ROSCCSR |= SCG_ROSCCSR_ROSCCM_MASK; + + /* Wait for ROSC clock to be valid. */ + while ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) == 0U) + { + } + + s_Xtal32_Freq = 32768U; + + return kStatus_Success; +} + +/** + * @brief Initialize the CLK16K clock. + * @param id : CLK 16 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id) +{ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; + + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + VBAT0->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; + + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(id); + + return kStatus_Success; +} + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config) +{ + SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_FircTrimNonUpdate == config.trimMode) + { + SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); + } + + /* Set trim mode. */ + SCG0->FIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->ROSCCSR; + + reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->ROSCCSR = reg; +} + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode) +{ + uint32_t reg = SCG0->UPLLCSR; + + reg &= ~(SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->UPLLCSR = reg; +} + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode) +{ + uint32_t reg = SCG0->APLLCSR; + + reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->APLLCSR = reg; +} + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SPLLCSR; + + reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SPLLCSR = reg; +} + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ( mode ) + { + case kMD_Mode: + { + if (system_freq_hz > 50000000) + { + return kStatus_Fail; + } + if (system_freq_hz >24000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kSD_Mode: + { + if (system_freq_hz > 100000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kOD_Mode: + { + if (system_freq_hz > 150000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 100000000) + { + num_wait_states_added = 3U; + } + else if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + } + } + + /* additional wait-states are added */ + FMU0 -> FCTRL = (FMU0 -> FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL); + + return kStatus_Success; +} + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config) +{ + uint32_t tmp32; + + if (config->enableCrystalOscillatorBypass == true) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_BYP_EN_MASK; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } + else + { + tmp32 = base->OSCCTLA; + + if (config != NULL) + { + if (config->enableInternalCapBank) + { + tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); + tmp32 |= VBAT_OSCCTLA_EXTAL_CAP_SEL(config->extalCap) | VBAT_OSCCTLA_XTAL_CAP_SEL(config->xtalCap); + tmp32 |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + else + { + /* Disable the internal capacitance bank. */ + tmp32 &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + + tmp32 &= ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK); + tmp32 |= VBAT_OSCCTLA_COARSE_AMP_GAIN(config->coarseAdjustment); + } + base->OSCCTLA = tmp32; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } +} + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint16_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint16_t)GET_ID_ITEM_MUX(item); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_SCGRCCRSCSCLKSEL) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(sel)) + { + } + } + else + { + ((volatile uint32_t *)pClkSel)[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint16_t mux; + uint32_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint16_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_SCGRCCRSCSCLKSEL) + { + actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actualSel = (uint32_t)((volatile uint32_t *)pClkSel)[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + /* halt and reset clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 0x3UL << 29U; + + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } +} + +/* Get IP clock dividers */ +/** + * brief Get peripheral clock dividers. + * param div_name : Clock divider name + * return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name) +{ + uint32_t div; + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + if ((uint32_t)(((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & (0x3UL << 29U)) != 0UL) + { + div = 0U; + } + else + { + div = (uint32_t)((((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & 0xFFU) + 1U); + } + + return div; +} + +/* Halt IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param Halt : Clock divider name + * return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + /* halt clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + + return; +} + +/* enable system clocks */ +/** + * brief system clocks enable controls. + * param mask : system clocks enable value + * return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask) +{ + SYSCON->CLOCK_CTRL |= mask; + + return; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_SystickClk0: + freq = CLOCK_GetSystickClkFreq(0U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Clk1M: + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Clk48M: + freq = CLOCK_GetClk48MFreq(); + break; + case kCLOCK_Clk144M: + freq = CLOCK_GetClk144MFreq(); + break; + case kCLOCK_Clk16K0: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + case kCLOCK_Clk16K1: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVsys); + break; + case kCLOCK_Clk16K2: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case kCLOCK_Clk16K3: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToMain); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Osc32K0: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case kCLOCK_Osc32K1: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVsys); + break; + case kCLOCK_Osc32K2: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case kCLOCK_Osc32K3: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_UsbPllOut: + // freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_LpOsc: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetClk1MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + case 9U: + freq = CLOCK_GetSaiTxBclkFreq(0U); + break; + case 10U: + freq = CLOCK_GetSaiRxBclkFreq(0U); + break; + case 11U: + freq = CLOCK_GetSaiTxBclkFreq(1U); + break; + case 12U: + freq = CLOCK_GetSaiRxBclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->CTIMERCLKDIV[id] & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->ADC0CLKSEL) : (SYSCON->ADC1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->ADC0CLKDIV & SYSCON_ADC0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->ADC1CLKDIV & SYSCON_ADC1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get LPFLEXCOMM Clk */ +/*! brief Return Frequency of LPFLEXCOMM Clock + * return Frequency of LPFLEXCOMM Clock. + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSEL[id]) + { + case 1U: + freq = CLOCK_GetPllClkDivFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + // freq = CLOCK_GetUPllOutFreq(); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXCOMMCLKDIV[id] & 0xffU) + 1U); +} + + +/* Get SYSTEM PLL0 Clk */ +/*! brief Return Frequency of PLL0 + * return Frequency of PLL0 + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + /* If PLL0 is work */ + if (CLOCK_IsPLL0Locked() == true) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get SYSTEM PLL1 Clk */ +/*! brief Return Frequency of PLL1 + * return Frequency of PLL1 + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + /* If PLL1 is work */ + if (CLOCK_IsPLL1Locked() == true) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll1MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get PLLClkDiv Clk */ +/*! brief Return Frequency of PLLClkDiv + * return Frequency of PLLClkDiv + */ +uint32_t CLOCK_GetPllClkDivFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->PLLCLKDIVSEL) + { + case 0U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 1U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); +} + +/*! + * brief Gets the external UPLL frequency. + * + * This function gets the external UPLL frequency in Hz. + * + * return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void) +{ + return s_extUpllFreq; +} + +/*! + * brief Sets the external UPLL frequency. + * + * This function sets the external UPLL frequency in Hz. + * Call this function after the external PLL frequency is changed. + * Otherwise, the APIs, which are used to get the frequency, may return an incorrect value. + * + * param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq) +{ + s_extUpllFreq = freq; +} + +/* Get I3C function Clk */ +/*! brief Return Frequency of I3C function clock + * return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->I3C0FCLKSEL) : (SYSCON->I3C1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->I3C1FCLKDIV & SYSCON_I3C1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get MICFIL Clk */ +/*! brief Return Frequency of MICFIL + * return Frequency of MICFIL + */ +uint32_t CLOCK_GetMicfilClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MICFILFCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->MICFILFCLKDIV & SYSCON_MICFILFCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXIO Clk */ +/*! brief Return Frequency of FLEXIO + * return Frequency of FLEXIO + */ +uint32_t CLOCK_GetFlexioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->FLEXIOCLKSEL) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXIOCLKDIV & SYSCON_FLEXIOCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXCAN Clk */ +/*! brief Return Frequency of FLEXCAN + * return Frequency of FLEXCAN + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->FLEXCAN0CLKSEL) : (SYSCON->FLEXCAN1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->FLEXCAN0CLKDIV & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->FLEXCAN1CLKDIV & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get EWM0 Clk */ +/*! brief Return Frequency of EWM0 + * return Frequency of EWM0 + */ +uint32_t CLOCK_GetEwm0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->EWM0CLKSEL) + { + case 1U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Watchdog Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + if (id == 0U) + { + freq = CLOCK_GetClk1MFreq(); + } + else + { + switch (SYSCON->WDT1CLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + case 3U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + } + + div = ((id == 0U) ? ((SYSCON->WDT0CLKDIV & SYSCON_WDT0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get OSTIMER Clk */ +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->OSTIMERCLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CMP Function Clk */ +/*! brief Return Frequency of CMP Function + * return Frequency of CMP Function + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0FCLKSEL) : (SYSCON->CMP1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0FCLKDIV & SYSCON_CMP0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1FCLKDIV & SYSCON_CMP1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get CMP Round Robin Clk */ +/*! brief Return Frequency of CMP Round Robin + * return Frequency of CMP Round Robin + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0RRCLKSEL) : (SYSCON->CMP1RRCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0RRCLKDIV & SYSCON_CMP0RRCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1RRCLKDIV & SYSCON_CMP1RRCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get UTICK Clk */ +/*! brief Return Frequency of UTICK + * return Frequency of UTICK + */ +uint32_t CLOCK_GetUtickClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t div = ((SYSCON->UTICKCLKDIV & SYSCON_UTICKCLKDIV_DIV_MASK) + 1U); + + switch (SYSCON->UTICKCLKSEL) + { + case 0U: + freq = CLOCK_GetExtClkFreq(); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + return freq / div; +} + +/* Get SAI Clk */ +/*! brief Return Frequency of SAI + * return Frequency of SAI + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->SAI0CLKSEL) : (SYSCON->SAI1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->SAI0CLKDIV & SYSCON_SAI0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->SAI1CLKDIV & SYSCON_SAI1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get SAI MCLK */ +/*! brief Initialize the SAI MCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Mclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI TX BCLK */ +/*! brief Initialize the SAI TX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Tx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI RX BCLK */ +/*! brief Initialize the SAI RX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Rx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI MCLK */ +/*! brief Return Frequency of SAI MCLK + * return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id) +{ + return s_Sai_Mclk_Freq[id]; +} + +/* Get SAI TX BCLK */ +/*! brief Return Frequency of SAI TX BCLK + * return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id) +{ + return s_Sai_Tx_Bclk_Freq[id]; +} + +/* Get SAI RX BCLK */ +/*! brief Return Frequency of SAI RX BCLK + * return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id) +{ + return s_Sai_Rx_Bclk_Freq[id]; +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLLInClockRateFromSetup(pSetup); + + prediv = findPllPreDivFromSetup(pSetup); + postdiv = findPllPostDivFromSetup(pSetup); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPllMMultFromSetup(pSetup); + workRate /= (float)postdiv; + + return (uint32_t)workRate; +} + +/* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Get PLL Input Clock Rate */ + switch (pControl->inputSource) + { + case (uint32_t)kPll_ClkSrcSysOsc: + inRate = CLOCK_GetExtClkFreq(); + break; + case (uint32_t)kPll_ClkSrcFirc: + inRate = CLOCK_GetClk48MFreq(); + break; + case (uint32_t)kPll_ClkSrcRosc: + inRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + inRate = 0U; + break; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useSS); + pSetup->pllctrl |= (uint32_t)pControl->inputSource; + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SCG_APLLSSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL0 and disable PLL0 clock during setup changes */ + SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->APLLCTRL = pSetup->pllctrl; + SCG0->APLLNDIV = pSetup->pllndiv; + SCG0->APLLNDIV = pSetup->pllndiv | (1UL << SCG_APLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->APLLPDIV = pSetup->pllpdiv; + SCG0->APLLPDIV = pSetup->pllpdiv | (1UL << SCG_APLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->APLLMDIV = pSetup->pllmdiv; + SCG0->APLLMDIV = pSetup->pllmdiv | (1UL << SCG_APLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->APLLSSCG0 = pSetup->pllsscg[0]; + SCG0->APLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock APLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500us/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->APLLLOCK_CNFG = SCG_APLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL0 and enable PLL0 clock */ + SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL0Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll0OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL1 and disable PLL1 clock during setup changes */ + SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->SPLLCTRL = pSetup->pllctrl; + SCG0->SPLLNDIV = pSetup->pllndiv; + SCG0->SPLLNDIV = pSetup->pllndiv | (1UL << SCG_SPLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->SPLLPDIV = pSetup->pllpdiv; + SCG0->SPLLPDIV = pSetup->pllpdiv | (1UL << SCG_SPLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->SPLLMDIV = pSetup->pllmdiv; + SCG0->SPLLMDIV = pSetup->pllmdiv | (1UL << SCG_SPLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->SPLLSSCG0 = pSetup->pllsscg[0]; + SCG0->SPLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock SPLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->SPLLLOCK_CNFG = SCG_SPLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL1 and enable PLL1 clock */ + SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL1Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll1OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + // PMC->OSEVENTTIMER |= PMC_OSEVENTTIMER_CLOCKENABLE_MASK; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint32_t freq; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0UL) + { + freq = 0; + } + else if ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) != 0UL) + { + freq = 144000000U; + } + else + { + freq = 48000000U; + } + + return freq; +} + +/* Get CLK 48M Clk */ +/*! brief Return Frequency of CLK 48MHz + * return Frequency of CLK 48MHz + */ +static uint32_t CLOCK_GetClk48MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) ? 48000000U : 0U; +} + +/* Get CLK 144M Clk */ +/*! brief Return Frequency of CLK 144MHz + * return Frequency of CLK 144MHz + */ +static uint32_t CLOCK_GetClk144MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) != 0U) ? 144000000U : 0U; +} + +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? + (((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE(id)) != 0UL) ? 16000U : 0U) : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id) +{ + return ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) != 0UL) ? + (((VBAT0->OSCCLKE & VBAT_OSCCLKE_CLKE(id)) != 0UL) ? s_Xtal32_Freq : 0U) : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 5U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 6U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSEL0) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +static uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get LP_OSC Clk */ +/*! brief Return Frequency of LP_OSC + * return Frequency of LP_OSC + */ +static uint32_t CLOCK_GetLposcFreq(void) +{ + uint32_t freq = 0U; + + switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT) + { + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case 2U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_LIMUPOFF_MASK) == 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum and fractional mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->APLLNDIV & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->SPLLNDIV & SCG_SPLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get postdivider (P) from PLL1 PDIV setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->APLLMDIV & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->APLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->APLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static float findPll1MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->SPLLMDIV & SCG_SPLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->SPLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->SPLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndiv = s_PllSetupCacheStruct[i].pllndiv; + pSetup->pllmdiv = s_PllSetupCacheStruct[i].pllmdiv; + pSetup->pllpdiv = s_PllSetupCacheStruct[i].pllpdiv; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndiv = pSetup->pllndiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllmdiv = pSetup->pllmdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdiv = pSetup->pllpdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndiv", "pllpdiv", "pllmdiv" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllmdiv = (uint32_t)PLL_MDIV_VAL_SET(pllMultiplier); + pSetup->pllsscg[1] &= ~SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) | PLL_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndiv = PLL_NDIV_VAL_SET(pllPreDivider); + pSetup->pllpdiv = PLL_PDIV_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SCG_APLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SCG_APLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SCG_APLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (uplimoff << SCG_APLLCTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SCG_APLLCTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0U; + + switch ((pSetup->pllctrl & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get predivider (N) from from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = pSetup->pllndiv & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t postDiv = 1UL; + + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(pSetup->pllmdiv & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((pSetup->pllsscg[0]) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((pSetup->pllsscg[0]) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool err = false; + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); + if ((480000000UL % freq) != 0UL) + { + return false; + } + multiplier = (uint16_t)(480000000UL / freq); + + switch (multiplier) + { + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 22: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U); + break; + } + case 24: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + err = true; + break; + } + } + + if (err) + { + return false; + } + + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; + + USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD = 0x0U; + + while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void) +{ + USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void) +{ + USBHS1__USBC->USBCMD |= USBHS_USBCMD_RST_MASK; + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (uint32_t i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + return true; +} + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void) +{ + /* System OSC Clock Monitor is disabled */ + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); + + firc_trim_config_t fircAutoTrimConfig = { + .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ + .trimSrc = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */ + .trimDiv = 1U, /* Divided value */ + .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ + .trimFine = 0U, /* Trim value, see Reference Manual for more information */ + }; + CLOCK_FROHFTrimConfig(fircAutoTrimConfig); + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return (status_t)kStatus_Success; +} diff --git a/devices/MCXN236/drivers/fsl_clock.h b/devices/MCXN236/drivers/fsl_clock.h new file mode 100644 index 000000000..649eceb3e --- /dev/null +++ b/devices/MCXN236/drivers/fsl_clock.h @@ -0,0 +1,1726 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4, kCLOCK_Sram5, kCLOCK_Sram6, kCLOCK_Sram7 \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt0, kCLOCK_Wwdt1 \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for LP_FLEXCOMM. */ +#define LP_FLEXCOMM_CLOCKS \ + { \ + kCLOCK_LPFlexComm0, kCLOCK_LPFlexComm1, kCLOCK_LPFlexComm2, kCLOCK_LPFlexComm3, kCLOCK_LPFlexComm4, \ + kCLOCK_LPFlexComm5, kCLOCK_LPFlexComm6, kCLOCK_LPFlexComm7 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_LPUart0, kCLOCK_LPUart1, kCLOCK_LPUart2, kCLOCK_LPUart3, kCLOCK_LPUart4, kCLOCK_LPUart5, \ + kCLOCK_LPUart6, kCLOCK_LPUart7 \ + } +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_LPI2c0, kCLOCK_LPI2c1, kCLOCK_LPI2c2, kCLOCK_LPI2c3, kCLOCK_LPI2c4, kCLOCK_LPI2c5, kCLOCK_LPI2c6, \ + kCLOCK_LPI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LPSpi0, kCLOCK_LPSpi1, kCLOCK_LPSpi2, kCLOCK_LPSpi3, kCLOCK_LPSpi4, kCLOCK_LPSpi5, kCLOCK_LPSpi6, \ + kCLOCK_LPSpi7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \ + { \ + kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \ + } \ + } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ + { \ + kCLOCK_Qdc0, kCLOCK_Qdc1 \ + } +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_Flexio \ + } +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_Flexcan0, kCLOCK_Flexcan1 \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_I3c0, kCLOCK_I3c1 \ + } +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_uSdhc \ + } +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0, kCLOCK_Sai1 \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Micfil \ + } +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS \ + { \ + kCLOCK_Erm \ + } +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS \ + { \ + kCLOCK_Eim \ + } +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } +/*! @brief Clock ip name array for LPCMP. */ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_None, kCLOCK_None, kCLOCK_Cmp2 \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define AHB_CLK_CTRL3 3 +#define REG_PWM0SUBCTL 250 +#define REG_PWM1SUBCTL 251 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_None = 0U, /*!< None clock gate. */ + + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */ + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */ + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */ + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */ + kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */ + kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */ + kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */ + kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */ + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */ + kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */ + kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */ + kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */ + kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */ + kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */ + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */ + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */ + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */ + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */ + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */ + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */ + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */ + kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */ + kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */ + kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */ + kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */ + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */ + kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */ + kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */ + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */ + kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPFlexComm0. */ + kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPFlexComm1. */ + kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPFlexComm2. */ + kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPFlexComm3. */ + kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPFlexComm4. */ + kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPFlexComm5. */ + kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPFlexComm6. */ + kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPFlexComm7. */ + kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */ + kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */ + kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */ + kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */ + kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */ + kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */ + kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */ + kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */ + kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */ + kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */ + kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */ + kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */ + kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */ + kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */ + kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */ + kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */ + kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */ + kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */ + kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */ + kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */ + kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */ + kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */ + kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */ + kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */ + kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */ + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */ + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */ + kCLOCK_Smartdma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */ + + kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */ + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */ + kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */ + kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */ + kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */ + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */ + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */ + kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */ + kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */ + kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */ + kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */ + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */ + kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */ + kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */ + kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */ + + kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */ + kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */ + kCLOCK_Qdc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Qdc0. */ + kCLOCK_Qdc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Qdc1. */ + kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */ + kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */ + kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */ + kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */ + kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */ + kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */ + kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */ + kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */ + + kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */ + kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */ + kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */ + kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */ + + kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */ + kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */ + kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */ + kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */ + +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_SystickClk0, /*!< Systick clock0 */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_FroHf, /*!< FRO48/144 */ + kCLOCK_Clk48M, /*!< CLK48M */ + kCLOCK_Clk144M, /*!< CLK144M */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_Clk16K2, /*!< CLK16K[2] */ + kCLOCK_Clk16K3, /*!< CLK16K[3] */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Osc32K0, /*!< OSC32K[0] */ + kCLOCK_Osc32K1, /*!< OSC32K[1] */ + kCLOCK_Osc32K2, /*!< OSC32K[2] */ + kCLOCK_Osc32K3, /*!< OSC32K[3] */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_UsbPllOut, /*!< USB PLL Output */ + kCLOCK_LpOsc, /*!< lp_osc */ +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U) +#define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_TRACECLKSEL ((0x268 - 0x260) / 4) +#define CM_CTIMERCLKSEL0 ((0x26C - 0x260) / 4) +#define CM_CTIMERCLKSEL1 ((0x270 - 0x260) / 4) +#define CM_CTIMERCLKSEL2 ((0x274 - 0x260) / 4) +#define CM_CTIMERCLKSEL3 ((0x278 - 0x260) / 4) +#define CM_CTIMERCLKSEL4 ((0x27C - 0x260) / 4) +#define CM_CLKOUTCLKSEL ((0x288 - 0x260) / 4) +#define CM_ADC0CLKSEL ((0x2A4 - 0x260) / 4) +#define CM_FCCLKSEL0 ((0x2B0 - 0x260) / 4) +#define CM_FCCLKSEL1 ((0x2B4 - 0x260) / 4) +#define CM_FCCLKSEL2 ((0x2B8 - 0x260) / 4) +#define CM_FCCLKSEL3 ((0x2BC - 0x260) / 4) +#define CM_FCCLKSEL4 ((0x2C0 - 0x260) / 4) +#define CM_FCCLKSEL5 ((0x2C4 - 0x260) / 4) +#define CM_FCCLKSEL6 ((0x2C8 - 0x260) / 4) +#define CM_FCCLKSEL7 ((0x2CC - 0x260) / 4) +#define CM_ADC1CLKSEL ((0x464 - 0x260) / 4) +#define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4) +#define CM_I3C0FCLKSEL ((0x530 - 0x260) / 4) +#define CM_MICFILFCLKSEL ((0x548 - 0x260) / 4) +#define CM_FLEXIOCLKSEL ((0x560 - 0x260) / 4) +#define CM_FLEXCAN0CLKSEL ((0x5A0 - 0x260) / 4) +#define CM_FLEXCAN1CLKSEL ((0x5A8 - 0x260) / 4) +#define CM_EWM0CLKSEL ((0x5D4 - 0x260) / 4) +#define CM_WDT1CLKSEL ((0x5D8 - 0x260) / 4) +#define CM_OSTIMERCLKSEL ((0x5E0 - 0x260) / 4) +#define CM_CMP0FCLKSEL ((0x5F0 - 0x260) / 4) +#define CM_CMP0RRCLKSEL ((0x5F8 - 0x260) / 4) +#define CM_CMP1FCLKSEL ((0x600 - 0x260) / 4) +#define CM_CMP1RRCLKSEL ((0x608 - 0x260) / 4) +#define CM_UTICKCLKSEL ((0x878 - 0x260) / 4) +#define CM_SAI0CLKSEL ((0x880 - 0x260) / 4) +#define CM_SAI1CLKSEL ((0x884 - 0x260) / 4) +#define CM_I3C1FCLKSEL ((0xB30 - 0x260) / 4) + +#define CM_SCGRCCRSCSCLKSEL 0x3FEU + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */ + kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */ + kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */ + kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */ + kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */ + kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */ + kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */ + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */ + kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */ + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */ + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */ + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */ + kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */ + kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */ + kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */ + kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */ + kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */ + kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */ + kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */ + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */ + + kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */ + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */ + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */ + kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */ + kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */ + kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */ + kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */ + kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */ + kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */ + kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */ + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */ + + kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */ + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */ + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */ + kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */ + kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */ + kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */ + kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */ + kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */ + kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */ + kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */ + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */ + + kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */ + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */ + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */ + kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */ + kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */ + kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */ + kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */ + kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */ + kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */ + kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */ + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */ + + kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */ + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */ + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */ + kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */ + kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */ + kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */ + kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */ + kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */ + kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */ + kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */ + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */ + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */ + kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */ + kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */ + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */ + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */ + + kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ + kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ + kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */ + kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */ + kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */ + kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */ + kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ + + kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */ + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */ + kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */ + kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */ + kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */ + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */ + kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */ + kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */ + kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */ + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */ + kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */ + kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */ + kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */ + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */ + kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */ + kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */ + kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */ + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */ + kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */ + kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */ + kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */ + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */ + kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */ + kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */ + kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */ + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */ + kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */ + kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */ + kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */ + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */ + kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */ + kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */ + kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ + kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ + kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */ + kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */ + kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */ + kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */ + kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ + + kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ + kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */ + kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */ + + kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */ + kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */ + kCLK_1M_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLK. */ + kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */ + kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */ + kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */ + + kPLL0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKSTC. */ + kFRO_HF_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKSTC. */ + kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKSTC. */ + kPLL1_CLK0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKSTC. */ + kUSB_PLL_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKSTC. */ + kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */ + + kPLL0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKS. */ + kFRO_HF_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKS. */ + kCLK_1M_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKS. */ + kPLL1_CLK0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKS. */ + kUSB_PLL_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKS. */ + kNONE_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKS. */ + + kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */ + kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */ + kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */ + kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */ + kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */ + kSAI0_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */ + kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */ + kSAI1_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */ + kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */ + + kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */ + kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */ + kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */ + kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */ + kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */ + kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */ + kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */ + + kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */ + kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */ + kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */ + kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */ + kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */ + + kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */ + kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */ + kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */ + kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */ + kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */ + kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */ + + kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */ + kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */ + + kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */ + kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */ + kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */ + kCLK_1M_2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach clk_1m to WDT1. */ + + kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */ + kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */ + kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */ + kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */ + + kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */ + kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */ + kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */ + kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */ + kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */ + kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */ + kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */ + + kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */ + kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */ + kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */ + kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */ + kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */ + kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */ + kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */ + + kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */ + kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */ + kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */ + kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */ + kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */ + kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */ + kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */ + + kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */ + kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */ + kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */ + kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */ + kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */ + kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */ + kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */ + + kCLK_IN_to_UTICK = MUX_A(CM_UTICKCLKSEL, 0), /*!< Attach Clk_in to UTICK. */ + kXTAL32K2_to_UTICK = MUX_A(CM_UTICKCLKSEL, 1), /*!< Attach xtal32k[2] to UTICK. */ + kCLK_1M_to_UTICK = MUX_A(CM_UTICKCLKSEL, 2), /*!< Attach clk_1m to UTICK. */ + kNONE_to_UTICK = MUX_A(CM_UTICKCLKSEL, 3), /*!< Attach NONE to UTICK. */ + + kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */ + kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */ + kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */ + kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */ + kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */ + kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */ + + kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */ + kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */ + kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */ + kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */ + kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */ + kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */ + + kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */ + kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */ + kCLK_1M_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLK. */ + kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */ + kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */ + kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */ + + kPLL0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKSTC. */ + kFRO_HF_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKSTC. */ + kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKSTC. */ + kPLL1_CLK0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKSTC. */ + kUSB_PLL_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKSTC. */ + kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */ + + kPLL0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKS. */ + kFRO_HF_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKS. */ + kCLK_1M_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKS. */ + kPLL1_CLK0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKS. */ + kUSB_PLL_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKS. */ + kNONE_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKS. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + kCLOCK_DivTraceClk = ((0x308 - 0x300) / 4), /*!< Trace Clk Divider. */ + kCLOCK_DivSlowClk = ((0x378 - 0x300) / 4), /*!< SLOW CLK Divider. */ + kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clk Divider. */ + kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< ClkOut Clk Divider. */ + kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Clk Divider. */ + kCLOCK_DivWdt0Clk = ((0x38C - 0x300) / 4), /*!< Wdt0 Clk Divider. */ + kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clk Divider. */ + kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll Clk Divider. */ + kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clk Divider. */ + kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clk Divider. */ + kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clk Divider. */ + kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clk Divider. */ + kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clk Divider. */ + kCLOCK_DivPLL1Clk0 = ((0x3E4 - 0x300) / 4), /*!< PLL1 Clk0 Divider. */ + kCLOCK_DivPLL1Clk1 = ((0x3E8 - 0x300) / 4), /*!< Pll1 Clk1 Divider. */ + kCLOCK_DivUtickClk = ((0x3F0 - 0x300) / 4), /*!< Utick Clk Divider. */ + kCLOCK_DivFrg = ((0x3F4 - 0x300) / 4), /*!< CLKOUT FRG Clk Divider. */ + kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clk Divider. */ + kCLOCK_DivI3c0FClk = ((0x540 - 0x300) / 4), /*!< I3C0 FClk Divider. */ + kCLOCK_DivMicfilFClk = ((0x54C - 0x300) / 4), /*!< MICFILFCLK Divider. */ + kCLOCK_DivFlexioClk = ((0x564 - 0x300) / 4), /*!< Flexio Clk Divider. */ + kCLOCK_DivFlexcan0Clk = ((0x5A4 - 0x300) / 4), /*!< Flexcan0 Clk Divider. */ + kCLOCK_DivFlexcan1Clk = ((0x5AC - 0x300) / 4), /*!< Flexcan1 Clk Divider. */ + kCLOCK_DivWdt1Clk = ((0x5DC - 0x300) / 4), /*!< Wdt1 Clk Divider. */ + kCLOCK_DivCmp0FClk = ((0x5F4 - 0x300) / 4), /*!< Cmp0 FClk Divider. */ + kCLOCK_DivCmp0rrClk = ((0x5FC - 0x300) / 4), /*!< Cmp0rr Clk Divider. */ + kCLOCK_DivCmp1FClk = ((0x604 - 0x300) / 4), /*!< Cmp1 FClk Divider. */ + kCLOCK_DivCmp1rrClk = ((0x60C - 0x300) / 4), /*!< Cmp1rr Clk Divider. */ + kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clk Divider. */ + kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clk Divider. */ + kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clk Divider. */ + kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clk Divider. */ + kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clk Divider. */ + kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clk Divider. */ + kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clk Divider. */ + kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clk Divider. */ + kCLOCK_DivSai0Clk = ((0x888 - 0x300) / 4), /*!< Sai0 Clk Divider. */ + kCLOCK_DivSai1Clk = ((0x88C - 0x300) / 4), /*!< Sai1 Clk Divider. */ + kCLOCK_DivI3c1FClk = ((0xB40 - 0x300) / 4), /*!< I3C1 FClk Divider. */ +} clock_div_name_t; + +/*! @brief OSC32K clock gate */ +typedef enum _osc32k_clk_gate_id +{ + kCLOCK_Osc32kToVbat = 0x1, /*!< OSC32K[0] to VBAT domain. */ + kCLOCK_Osc32kToVsys = 0x2, /*!< OSC32K[1] to VSYS domain. */ + kCLOCK_Osc32kToWake = 0x4, /*!< OSC32K[2] to WAKE domain. */ + kCLOCK_Osc32kToMain = 0x8, /*!< OSC32K[3] to MAIN domain. */ + kCLOCK_Osc32kToAll = 0xF, /*!< OSC32K to VBAT,VSYS,WAKE,MAIN domain. */ +} osc32k_clk_gate_id_t; + +/*! @brief CLK16K clock gate */ +typedef enum _clk16k_clk_gate_id +{ + kCLOCK_Clk16KToVbat = 0x1, /*!< Clk16k[0] to VBAT domain. */ + kCLOCK_Clk16KToVsys = 0x2, /*!< Clk16k[1] to VSYS domain. */ + kCLOCK_Clk16KToWake = 0x4, /*!< Clk16k[2] to WAKE domain. */ + kCLOCK_Clk16KToMain = 0x8, /*!< Clk16k[3] to MAIN domain. */ + kCLOCK_Clk16KToAll = 0xF, /*!< Clk16k to VBAT,VSYS,WAKE,MAIN domain. */ +} clk16k_clk_gate_id_t; + +/*! @brief system clocks enable controls */ +typedef enum _clock_ctrl_enable +{ + kCLOCK_FRO1MHZ_CLK_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */ + kCLOCK_CLKIN_ENA = SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1, + SAI0/1, clkout */ + kCLOCK_FRO_HF_ENA = + SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK, /*!< Enables FRO HF clock for the Frequency Measure module. */ + kCLOCK_FRO12MHZ_ENA = SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK, /*!< Enables the FRO_12MHz clock for the Flash, + LPTIMER0/1, and Frequency Measurement modules. */ + kCLOCK_FRO1MHZ_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */ + kCLOCK_CLKIN_ENA_FM_USBH_LPT = + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK, /*!< Enables the clk_in clock for the Frequency Measurement, USB + HS and LPTIMER0/1 modules. */ +} clock_ctrl_enable_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*! + * @brief SCG status return codes. + */ +enum _scg_status +{ + kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ + kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ +}; + +/*! + * @brief firc trim mode. + */ +typedef enum _firc_trim_mode +{ + kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} firc_trim_mode_t; + +/*! + * @brief firc trim source. + */ +typedef enum _firc_trim_src +{ + kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */ + kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} firc_trim_src_t; + +/*! + * @brief firc trim configuration. + */ +typedef struct _firc_trim_config +{ + firc_trim_mode_t trimMode; /*!< Trim mode. */ + firc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} firc_trim_config_t; + +/*! + * @brief sirc trim mode. + */ +typedef enum _sirc_trim_mode +{ + kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} sirc_trim_mode_t; + +/*! + * @brief sirc trim source. + */ +typedef enum _sirc_trim_src +{ + kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_SircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} sirc_trim_src_t; + +/*! + * @brief sirc trim configuration. + */ +typedef struct _sirc_trim_config +{ + sirc_trim_mode_t trimMode; /*!< Trim mode. */ + sirc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} sirc_trim_config_t; + +/*! + * @brief SCG system OSC monitor mode. + */ +typedef enum _scg_sosc_monitor_mode +{ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ + kSCG_SysOscMonitorReset = + SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ +} scg_sosc_monitor_mode_t; + +/*! + * @brief SCG ROSC monitor mode. + */ +typedef enum _scg_rosc_monitor_mode +{ + kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ + kSCG_RoscMonitorReset = + SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */ +} scg_rosc_monitor_mode_t; + +/*! + * @brief SCG UPLL monitor mode. + */ +typedef enum _scg_upll_monitor_mode +{ + kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */ + kSCG_UpllMonitorReset = + SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK /*!< Reset when the UPLL error is detected. */ +} scg_upll_monitor_mode_t; + +/*! + * @brief SCG PLL0 monitor mode. + */ +typedef enum _scg_pll0_monitor_mode +{ + kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */ + kSCG_Pll0MonitorReset = + SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detected. */ +} scg_pll0_monitor_mode_t; + +/*! + * @brief SCG PLL1 monitor mode. + */ +typedef enum _scg_pll1_monitor_mode +{ + kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ + kSCG_Pll1MonitorReset = + SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */ +} scg_pll1_monitor_mode_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's XTAL pin. + */ +typedef enum _vbat_osc_xtal_cap +{ + kVBAT_OscXtal0pFCap = 0x0U, /*!< The internal capacitance for XTAL pin is 0pF. */ + kVBAT_OscXtal2pFCap = 0x1U, /*!< The internal capacitance for XTAL pin is 2pF. */ + kVBAT_OscXtal4pFCap = 0x2U, /*!< The internal capacitance for XTAL pin is 4pF. */ + kVBAT_OscXtal6pFCap = 0x3U, /*!< The internal capacitance for XTAL pin is 6pF. */ + kVBAT_OscXtal8pFCap = 0x4U, /*!< The internal capacitance for XTAL pin is 8pF. */ + kVBAT_OscXtal10pFCap = 0x5U, /*!< The internal capacitance for XTAL pin is 10pF. */ + kVBAT_OscXtal12pFCap = 0x6U, /*!< The internal capacitance for XTAL pin is 12pF. */ + kVBAT_OscXtal14pFCap = 0x7U, /*!< The internal capacitance for XTAL pin is 14pF. */ + kVBAT_OscXtal16pFCap = 0x8U, /*!< The internal capacitance for XTAL pin is 16pF. */ + kVBAT_OscXtal18pFCap = 0x9U, /*!< The internal capacitance for XTAL pin is 18pF. */ + kVBAT_OscXtal20pFCap = 0xAU, /*!< The internal capacitance for XTAL pin is 20pF. */ + kVBAT_OscXtal22pFCap = 0xBU, /*!< The internal capacitance for XTAL pin is 22pF. */ + kVBAT_OscXtal24pFCap = 0xCU, /*!< The internal capacitance for XTAL pin is 24pF. */ + kVBAT_OscXtal26pFCap = 0xDU, /*!< The internal capacitance for XTAL pin is 26pF. */ + kVBAT_OscXtal28pFCap = 0xEU, /*!< The internal capacitance for XTAL pin is 28pF. */ + kVBAT_OscXtal30pFCap = 0xFU, /*!< The internal capacitance for XTAL pin is 30pF. */ +} vbat_osc_xtal_cap_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's EXTAL pin. + */ +typedef enum _vbat_osc_extal_cap +{ + kVBAT_OscExtal0pFCap = 0x0U, /*!< The internal capacitance for EXTAL pin is 0pF. */ + kVBAT_OscExtal2pFCap = 0x1U, /*!< The internal capacitance for EXTAL pin is 2pF. */ + kVBAT_OscExtal4pFCap = 0x2U, /*!< The internal capacitance for EXTAL pin is 4pF. */ + kVBAT_OscExtal6pFCap = 0x3U, /*!< The internal capacitance for EXTAL pin is 6pF. */ + kVBAT_OscExtal8pFCap = 0x4U, /*!< The internal capacitance for EXTAL pin is 8pF. */ + kVBAT_OscExtal10pFCap = 0x5U, /*!< The internal capacitance for EXTAL pin is 10pF. */ + kVBAT_OscExtal12pFCap = 0x6U, /*!< The internal capacitance for EXTAL pin is 12pF. */ + kVBAT_OscExtal14pFCap = 0x7U, /*!< The internal capacitance for EXTAL pin is 14pF. */ + kVBAT_OscExtal16pFCap = 0x8U, /*!< The internal capacitance for EXTAL pin is 16pF. */ + kVBAT_OscExtal18pFCap = 0x9U, /*!< The internal capacitance for EXTAL pin is 18pF. */ + kVBAT_OscExtal20pFCap = 0xAU, /*!< The internal capacitance for EXTAL pin is 20pF. */ + kVBAT_OscExtal22pFCap = 0xBU, /*!< The internal capacitance for EXTAL pin is 22pF. */ + kVBAT_OscExtal24pFCap = 0xCU, /*!< The internal capacitance for EXTAL pin is 24pF. */ + kVBAT_OscExtal26pFCap = 0xDU, /*!< The internal capacitance for EXTAL pin is 26pF. */ + kVBAT_OscExtal28pFCap = 0xEU, /*!< The internal capacitance for EXTAL pin is 28pF. */ + kVBAT_OscExtal30pFCap = 0xFU, /*!< The internal capacitance for EXTAL pin is 30pF. */ +} vbat_osc_extal_cap_t; + +/*! + * @brief The enumerator of osc amplifier gain fine adjustment. + * Changes the oscillator amplitude by modifying the automatic gain control (AGC). + */ +typedef enum _vbat_osc_fine_adjustment_value +{ + kVBAT_OscCoarseAdjustment05 = 0U, + kVBAT_OscCoarseAdjustment10 = 1U, + kVBAT_OscCoarseAdjustment18 = 2U, + kVBAT_OscCoarseAdjustment33 = 3U, +} vbat_osc_coarse_adjustment_value_t; + +/*! + * @brief The structure of oscillator configuration. + */ +typedef struct _vbat_osc_config +{ + bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */ + + bool enableCrystalOscillatorBypass; /*!< enable/disable the crystal oscillator bypass. */ + + vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank, + only useful when the internal capacitance bank is enabled. */ + vbat_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank, only + useful when the internal capacitance bank is enabled. */ + vbat_osc_coarse_adjustment_value_t + coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */ +} vbat_osc_config_t; + +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Midvoltage (1.0 V). */ + kSD_Mode, /*!< Normal voltage (1.1 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x40U; + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x80U; + } + else + { + SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); + } +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x20U; + } + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x40U; + } + } + else + { + SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); + } +} + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_44MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/** + * @brief Initialize the XTAL32/EXTAL32 input clock to given frequency. + * @param id : OSC 32 kHz output clock to specified modules, it should use osc32k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id); + +/** + * @brief Initialize the FRO16K input clock to given frequency. + * @param id : FRO 16 kHz output clock to specified modules, it should use clk16k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id); + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode); + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode); + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode); + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode); + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config); + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access + * time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + * @return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name); + +/** + * @brief system clocks enable controls. + * @param mask : system clocks enable value, it should use clock_ctrl_enable_t value + * @return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPFlexComm Clock + * @return Frequency of LPFlexComm Clock + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id); + +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); + +/*! @brief Return Frequency of PLLCLKDIV + * @return Frequency of PLLCLKDIV Clock + */ +uint32_t CLOCK_GetPllClkDivFreq(void); + +/*! @brief Return Frequency of I3C function Clock + * @return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id); + +/*! @brief Return Frequency of MICFIL Clock + * @return Frequency of MICFIL. + */ +uint32_t CLOCK_GetMicfilClkFreq(void); + +/*! @brief Return Frequency of FLEXIO + * @return Frequency of FLEXIO Clock + */ +uint32_t CLOCK_GetFlexioClkFreq(void); + +/*! @brief Return Frequency of FLEXCAN + * @return Frequency of FLEXCAN Clock + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id); + +/*! @brief Return Frequency of EWM0 Clock + * @return Frequency of EWM0. + */ +uint32_t CLOCK_GetEwm0ClkFreq(void); + +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of UTICK Clock + * @return Frequency of UTICK Clock. + */ +uint32_t CLOCK_GetUtickClkFreq(void); + +/*! @brief Return Frequency of SAI Clock + * @return Frequency of SAI Clock. + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id); + +/** + * @brief Initialize the SAI MCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI TX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI RX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Return Frequency of SAI MCLK + * @return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI TX BCLK + * @return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI RX BCLK + * @return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Gets the external UPLL frequency. + * @return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void); + +/*! @brief Sets the external UPLL frequency. + * @param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq); + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SCG0->SPLLCSR & SCG_SPLLCSR_SPLL_LOCK_MASK) != 0UL); +} + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! + * @brief PLL clock source. + */ +typedef enum _pll_clk_src +{ + kPll_ClkSrcSysOsc = (0 << 25), /*!< System OSC. */ + kPll_ClkSrcFirc = (1 << 25), /*!< Fast IRC. */ + kPll_ClkSrcRosc = (2 << 25), /*!< RTC OSC. */ +} pll_clk_src_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 2), /*!< Nss = 512 (fm ~= 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 2), /*!< Nss ~= 384 (fm ~= 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 2), /*!< Nss = 256 (fm ~= 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 2), /*!< Nss = 128 (fm ~= 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 2), /*!< Nss = 64 (fm ~= 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 2), /*!< Nss = 32 (fm ~= 62.5 - 125 kHz) */ + kSS_MF_24 = (6 << 2), /*!< Nss ~= 24 (fm ~= 83.3 - 166.6 kHz) */ + kSS_MF_16 = (7 << 2) /*!< Nss = 16 (fm ~= 125 - 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 5), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 5), /*!< k ~= 1 */ + kSS_MR_K1_5 = (2 << 5), /*!< k ~= 1.5 */ + kSS_MR_K2 = (3 << 5), /*!< k ~= 2 */ + kSS_MR_K3 = (4 << 5), /*!< k ~= 3 */ + kSS_MR_K4 = (5 << 5), /*!< k ~= 4 */ + kSS_MR_K6 = (6 << 5), /*!< k ~= 6 */ + kSS_MR_K8 = (7 << 5) /*!< k ~= 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 8), /*!< no compensation */ + kSS_MC_RECC = (2 << 8), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 8), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputSource; /*!< PLL input source */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag + */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL Control register APLLCTRL */ + uint32_t pllndiv; /*!< PLL N Divider register APLLNDIV */ + uint32_t pllpdiv; /*!< PLL P Divider register APLLPDIV */ + uint32_t pllmdiv; /*!< PLL M Divider register APLLMDIV */ + uint32_t pllsscg[2]; /*!< PLL Spread Spectrum Control registers APLLSSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_OutputError = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL output rate error */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 8) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief Return PLL0 output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup); + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void); + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void); + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void); + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/devices/MCXN236/drivers/fsl_edma_soc.c b/devices/MCXN236/drivers/fsl_edma_soc.c new file mode 100644 index 000000000..2706eb37e --- /dev/null +++ b/devices/MCXN236/drivers/fsl_edma_soc.c @@ -0,0 +1,289 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void EDMA_0_CH0_DriverIRQHandler(void); +extern void EDMA_0_CH1_DriverIRQHandler(void); +extern void EDMA_0_CH2_DriverIRQHandler(void); +extern void EDMA_0_CH3_DriverIRQHandler(void); +extern void EDMA_0_CH4_DriverIRQHandler(void); +extern void EDMA_0_CH5_DriverIRQHandler(void); +extern void EDMA_0_CH6_DriverIRQHandler(void); +extern void EDMA_0_CH7_DriverIRQHandler(void); +extern void EDMA_0_CH8_DriverIRQHandler(void); +extern void EDMA_0_CH9_DriverIRQHandler(void); +extern void EDMA_0_CH10_DriverIRQHandler(void); +extern void EDMA_0_CH11_DriverIRQHandler(void); +extern void EDMA_0_CH12_DriverIRQHandler(void); +extern void EDMA_0_CH13_DriverIRQHandler(void); +extern void EDMA_0_CH14_DriverIRQHandler(void); +extern void EDMA_0_CH15_DriverIRQHandler(void); +extern void EDMA_1_CH0_DriverIRQHandler(void); +extern void EDMA_1_CH1_DriverIRQHandler(void); +extern void EDMA_1_CH2_DriverIRQHandler(void); +extern void EDMA_1_CH3_DriverIRQHandler(void); +extern void EDMA_1_CH4_DriverIRQHandler(void); +extern void EDMA_1_CH5_DriverIRQHandler(void); +extern void EDMA_1_CH6_DriverIRQHandler(void); +extern void EDMA_1_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void EDMA_0_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void EDMA_0_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void EDMA_0_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void EDMA_0_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void EDMA_0_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} + +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void EDMA_0_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void EDMA_0_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void EDMA_0_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} + +/*! + * brief DMA instance 0, channel 8 IRQ handler. + * + */ +void EDMA_0_CH8_DriverIRQHandler(void) +{ + /* Instance 0 channel 8 */ + EDMA_DriverIRQHandler(0U, 8U); +} + +/*! + * brief DMA instance 0, channel 9 IRQ handler. + * + */ +void EDMA_0_CH9_DriverIRQHandler(void) +{ + /* Instance 0 channel 9 */ + EDMA_DriverIRQHandler(0U, 9U); +} + +/*! + * brief DMA instance 0, channel 10 IRQ handler. + * + */ +void EDMA_0_CH10_DriverIRQHandler(void) +{ + /* Instance 0 channel 10 */ + EDMA_DriverIRQHandler(0U, 10U); +} + +/*! + * brief DMA instance 0, channel 11 IRQ handler. + * + */ +void EDMA_0_CH11_DriverIRQHandler(void) +{ + /* Instance 0 channel 11 */ + EDMA_DriverIRQHandler(0U, 11U); +} + +/*! + * brief DMA instance 0, channel 12 IRQ handler. + * + */ +void EDMA_0_CH12_DriverIRQHandler(void) +{ + /* Instance 0 channel 12 */ + EDMA_DriverIRQHandler(0U, 12U); +} + +/*! + * brief DMA instance 0, channel 13 IRQ handler. + * + */ +void EDMA_0_CH13_DriverIRQHandler(void) +{ + /* Instance 0 channel 13 */ + EDMA_DriverIRQHandler(0U, 13U); +} + +/*! + * brief DMA instance 0, channel 14 IRQ handler. + * + */ +void EDMA_0_CH14_DriverIRQHandler(void) +{ + /* Instance 0 channel 14 */ + EDMA_DriverIRQHandler(0U, 14U); +} + +/*! + * brief DMA instance 0, channel 15 IRQ handler. + * + */ +void EDMA_0_CH15_DriverIRQHandler(void) +{ + /* Instance 0 channel 15 */ + EDMA_DriverIRQHandler(0U, 15U); +} + +/*! + * brief DMA instance 1, channel 0 IRQ handler. + * + */ +void EDMA_1_CH0_DriverIRQHandler(void) +{ + /* Instance 1 channel 0 */ + EDMA_DriverIRQHandler(1U, 0U); +} + +/*! + * brief DMA instance 1, channel 1 IRQ handler. + * + */ +void EDMA_1_CH1_DriverIRQHandler(void) +{ + /* Instance 1 channel 1 */ + EDMA_DriverIRQHandler(1U, 1U); +} + +/*! + * brief DMA instance 1, channel 2 IRQ handler. + * + */ +void EDMA_1_CH2_DriverIRQHandler(void) +{ + /* Instance 1 channel 2 */ + EDMA_DriverIRQHandler(1U, 2U); +} + +/*! + * brief DMA instance 1, channel 3 IRQ handler. + * + */ +void EDMA_1_CH3_DriverIRQHandler(void) +{ + /* Instance 1 channel 3 */ + EDMA_DriverIRQHandler(1U, 3U); +} + +/*! + * brief DMA instance 1, channel 4 IRQ handler. + * + */ +void EDMA_1_CH4_DriverIRQHandler(void) +{ + /* Instance 1 channel 4 */ + EDMA_DriverIRQHandler(1U, 4U); +} + +/*! + * brief DMA instance 1, channel 5 IRQ handler. + * + */ +void EDMA_1_CH5_DriverIRQHandler(void) +{ + /* Instance 1 channel 5 */ + EDMA_DriverIRQHandler(1U, 5U); +} + +/*! + * brief DMA instance 1, channel 6 IRQ handler. + * + */ +void EDMA_1_CH6_DriverIRQHandler(void) +{ + /* Instance 1 channel 6 */ + EDMA_DriverIRQHandler(1U, 6U); +} + +/*! + * brief DMA instance 1, channel 7 IRQ handler. + * + */ +void EDMA_1_CH7_DriverIRQHandler(void) +{ + /* Instance 1 channel 7 */ + EDMA_DriverIRQHandler(1U, 7U); +} diff --git a/devices/MCXN236/drivers/fsl_edma_soc.h b/devices/MCXN236/drivers/fsl_edma_soc.h new file mode 100644 index 000000000..863542cff --- /dev/null +++ b/devices/MCXN236/drivers/fsl_edma_soc.h @@ -0,0 +1,68 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 1.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS \ + { \ + DMA0, DMA1 \ + } + +#define EDMA_CHN_IRQS \ + { \ + {EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, \ + EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, \ + EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn}, \ + { \ + EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, \ + EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/devices/MCXN236/drivers/fsl_inputmux_connections.h b/devices/MCXN236/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..629a6aa25 --- /dev/null +++ b/devices/MCXN236/drivers/fsl_inputmux_connections.h @@ -0,0 +1,3664 @@ +/* + * Copyright 2022 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 0x20U +#define TIMER0TRIGIN 0x30U +#define TIMER1CAPTSEL0 0x40U +#define TIMER1TRIGIN 0x50U +#define TIMER2CAPTSEL0 0x60U +#define TIMER2TRIGIN 0x70U +#define SMARTDMAARCHB_INMUX0 0xA0U +#define PINTSEL0 0xC0U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TAR_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER3TRIGIN 0x1B0U +#define TIMER4CAPTSEL0 0x1C0U +#define TIMER4TRIGIN 0x1D0U +#define CMP0_TRIG_REG 0x260U +#define ADC0_TRIG0 0x280U +#define ADC1_TRIG0 0x2C0U +#define QDC0_TRIG_REG 0x360U +#define QDC0_HOME_REG 0x364U +#define QDC0_INDEX_REG 0x368U +#define QDC0_PHASEB_REG 0x36CU +#define QDC0_PHASEA_REG 0x370U +#define QDC1_TRIG_REG 0x380U +#define QDC1_HOME_REG 0x384U +#define QDC1_INDEX_REG 0x388U +#define QDC1_PHASEB_REG 0x38CU +#define QDC1_PHASEA_REG 0x390U +#define FlexPWM0_SM0_EXTSYNC_REG 0x3A0U +#define FlexPWM0_SM1_EXTSYNC_REG 0x3A4U +#define FlexPWM0_SM2_EXTSYNC_REG 0x3A8U +#define FlexPWM0_SM3_EXTSYNC_REG 0x3ACU +#define FlexPWM0_SM0_EXTA_REG 0x3B0U +#define FlexPWM0_SM1_EXTA_REG 0x3B4U +#define FlexPWM0_SM2_EXTA_REG 0x3B8U +#define FlexPWM0_SM3_EXTA_REG 0x3BCU +#define FlexPWM0_EXTFORCE_REG 0x3C0U +#define FlexPWM0_FAULT0_REG 0x3C4U +#define FlexPWM0_FAULT1_REG 0x3C8U +#define FlexPWM0_FAULT2_REG 0x3CCU +#define FlexPWM0_FAULT3_REG 0x3D0U +#define FlexPWM1_SM0_EXTSYNC_REG 0x3E0U +#define FlexPWM1_SM1_EXTSYNC_REG 0x3E4U +#define FlexPWM1_SM2_EXTSYNC_REG 0x3E8U +#define FlexPWM1_SM3_EXTSYNC_REG 0x3ECU +#define FlexPWM1_SM0_EXTA_REG 0x3F0U +#define FlexPWM1_SM1_EXTA_REG 0x3F4U +#define FlexPWM1_SM2_EXTA_REG 0x3F8U +#define FlexPWM1_SM3_EXTA_REG 0x3FCU +#define FlexPWM1_EXTFORCE_REG 0x400U +#define FlexPWM1_FAULT0_REG 0x404U +#define FlexPWM1_FAULT1_REG 0x408U +#define FlexPWM1_FAULT2_REG 0x40CU +#define FlexPWM1_FAULT3_REG 0x410U +#define PWM0_EXT_CLK_REG 0x420U +#define PWM1_EXT_CLK_REG 0x424U +#define EVTG_TRIG0_REG 0x440U +#define EXT_TRIG0_REG 0x4C0U +#define CMP1_TRIG_REG 0x4E0U +#define FLEXCOMM0_TRIG_REG 0x5A0U +#define FLEXCOMM1_TRIG_REG 0x5C0U +#define FLEXCOMM2_TRIG_REG 0x5E0U +#define FLEXCOMM3_TRIG_REG 0x600U +#define FLEXCOMM4_TRIG_REG 0x620U +#define FLEXCOMM5_TRIG_REG 0x640U +#define FLEXCOMM6_TRIG_REG 0x660U +#define FLEXCOMM7_TRIG_REG 0x680U +#define FLEXIO_TRIG0_REG 0x6E0U + +#define DMA0_REQ_ENABLE0_REG 0x700U +#define DMA0_REQ_ENABLE1_REG 0x710U +#define DMA0_REQ_ENABLE2_REG 0x720U +#define DMA0_REQ_ENABLE3_REG 0x730U +#define DMA1_REQ_ENABLE0_REG 0x780U +#define DMA1_REQ_ENABLE1_REG 0x790U +#define DMA1_REQ_ENABLE2_REG 0x7A0U +#define DMA1_REQ_ENABLE3_REG 0x7B0U + +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Captsel = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Captsel = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Captsel = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Captsel = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Captsel = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Captsel = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Captsel = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Captsel = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Captsel = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Captsel = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 0U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Trigger = 50U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Trigger = 51U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 0U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Trigger = 50U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Trigger = 51U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 0U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Trigger = 50U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Trigger = 51U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 0U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Trigger = 50U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Trigger = 51U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 0U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Trigger = 50U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Trigger = 51U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< SMARTDMA arch B inputs. */ + kINPUTMUX_GpioPort0Pin0ToSmartDma = 0U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToSmartDma = 1U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToSmartDma = 2U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToSmartDma = 3U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToSmartDma = 4U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToSmartDma = 5U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToSmartDma = 6U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToSmartDma = 7U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToSmartDma = 12U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToSmartDma = 13U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToSmartDma = 14U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToSmartDma = 15U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh0IrqToSmartDma = 20U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh1IrqToSmartDma = 21U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToSmartDma = 22U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToSmartDma = 23U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToSmartDma = 24U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToSmartDma = 25U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToSmartDma = 26U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToSmartDma = 27U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_UtickIrqToSmartDma = 28U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Wdt0IrqToSmartDma = 29U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSmartDma = 30U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0IrqToSmartDma = 31U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm7IrqToSmartDma = 33U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm6IrqToSmartDma = 34U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm5IrqToSmartDma = 35U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm4IrqToSmartDma = 36U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3IrqToSmartDma = 37U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2IrqToSmartDma = 38U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1IrqToSmartDma = 39U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0IrqToSmartDma = 40U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0IrqToSmartDma = 41U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1IrqToSmartDma = 42U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SysIrqToSmartDma = 43U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_RtcComboIrqToSmartDma = 44U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSmartDma = 45U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToSmartDma = 46U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToSmartDma = 49U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameIrqToSmartDma = 50U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameIrqToSmartDma = 51U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OsEventTimerIrqToSmartDma = 52U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSmartDma = 53U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp01IrqToSmartDma = 54U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0IrqToSmartDma = 57U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1IrqToSmartDma = 58U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartDma = 59U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartDma = 60U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToSmartDma = 61U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToSmartDma = 62U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToSmartDma = 65U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig1ToSmartDma = 66U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToSmartDma = 67U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToSmartDma = 68U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToSmartDma = 69U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToSmartDma = 70U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest0ToSmartDma = 71U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest1ToSmartDma = 72U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest2ToSmartDma = 73U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest3ToSmartDma = 74U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest4ToSmartDma = 75U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest5ToSmartDma = 76U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest6ToSmartDma = 77U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest7ToSmartDma = 78U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 0U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasTar = 1u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasTar = 4u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_PinInt0ToCmp0Trigger = 0U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToCmp0Trigger = 1U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp0Trigger = 7U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 35U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp0Trigger = 36U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 37U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp0Trigger = 38U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_PinInt0ToCmp1Trigger = 0U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToCmp1Trigger = 1U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp1Trigger = 7U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 35U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp1Trigger = 36U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 37U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp1Trigger = 38U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + + + /*!< Adc0 Trigger. */ + kINPUTMUX_PinInt0ToAdc0Trigger = 0U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAdc0Trigger = 1U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc0Trigger = 5U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc0Trigger = 6U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc0Trigger = 7U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAdc0Trigger = 8U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAdc0Trigger = 9U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc0Trigger = 10U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc0Trigger = 11U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc0Trigger = 12U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc0Trigger = 13U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc0Trigger = 14U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc0Trigger = 15U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc0Trigger = 16U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 17U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 18U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 19U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 20U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 21U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 22U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc0Trigger = 24U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc0Trigger = 25U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc0Trigger = 26U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc0Trigger = 27U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc0Trigger = 28U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc0Trigger = 29U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc0Trigger = 30U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc0Trigger = 31U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc0Trigger = 32U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc0Trigger = 33U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc0Trigger = 34U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc0Trigger = 35U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc0Trigger = 36U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc0Trigger = 45U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc0Trigger = 46U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc0Trigger = 47U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc0Trigger = 48U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc0Trigger = 49U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 50U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc0Trigger = 51U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 52U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 53U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 54U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 55U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 61U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc0Trigger = 62U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 63U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc0Trigger = 64U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 65U + (ADC0_TRIG0 << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_PinInt0ToAdc1Trigger = 0U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToAdc1Trigger = 1U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc1Trigger = 5U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc1Trigger = 6U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc1Trigger = 7U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAdc1Trigger = 8U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 9U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc1Trigger = 10U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc1Trigger = 11U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc1Trigger = 12U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 13U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 14U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 15U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 16U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc1Trigger = 17U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc1Trigger = 18U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc1Trigger = 19U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc1Trigger = 20U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 21U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 22U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc1Trigger = 24U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc1Trigger = 25U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc1Trigger = 26U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc1Trigger = 27U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc1Trigger = 28U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc1Trigger = 29U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc1Trigger = 30U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc1Trigger = 31U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc1Trigger = 32U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc1Trigger = 33U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc1Trigger = 34U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc1Trigger = 35U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc1Trigger = 36U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc1Trigger = 45U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc1Trigger = 46U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc1Trigger = 47U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc1Trigger = 48U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc1Trigger = 49U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 50U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc1Trigger = 51U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 52U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 53U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 54U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 55U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 61U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc1Trigger = 62U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 63U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc1Trigger = 64U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 65U + (ADC1_TRIG0 << PMUX_SHIFT), + + /*!< QDC0 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Trigger = 0U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Trigger = 15U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 45U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 46U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 47U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 48U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< QDC0 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Home = 0U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Home = 15U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 45U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 46U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 47U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 48U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< QDC0 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Index = 0U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Index = 15U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 45U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 46U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 47U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 48U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< QDC0 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phaseb = 0U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phaseb = 15U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 45U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 46U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 47U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 48U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC0 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phasea = 0U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phasea = 15U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 45U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 46U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 47U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 48U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< QDC1 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Trigger = 0U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Trigger = 15U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 45U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 46U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 47U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 48U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< QDC1 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Home = 0U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Home = 15U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 45U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 46U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 47U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 48U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< QDC1 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Index = 0U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Index = 15U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 45U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 46U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 47U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 48U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< QDC1 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phaseb = 0U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phaseb = 15U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 45U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 46U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 47U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 48U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC1 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phasea = 0U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phasea = 15U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 45U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 46U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 47U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 48U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0ExtSync = 0U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0ExtSync = 1U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0ExtSync = 5U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0ExtSync = 6U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0ExtSync = 7U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0ExtSync = 8U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0ExtSync = 9U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0ExtSync = 11U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0ExtSync = 12U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0ExtSync = 13U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0ExtSync = 14U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0ExtSync = 15U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0ExtSync = 16U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0ExtSync = 17U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0ExtSync = 18U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0ExtSync = 19U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0ExtSync = 20U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0ExtSync = 21U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0ExtSync = 22U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0ExtSync = 24U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0ExtSync = 25U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0ExtSync = 26U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0ExtSync = 27U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0ExtSync = 28U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0ExtSync = 29U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0ExtSync = 30U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0ExtSync = 31U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0ExtSync = 32U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0ExtSync = 33U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0ExtSync = 34U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0ExtSync = 35U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0ExtSync = 36U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0ExtSync = 37U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0ExtSync = 38U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0ExtSync = 39U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0ExtSync = 40U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0ExtSync = 41U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0ExtSync = 42U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0ExtSync = 43U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0ExtSync = 44U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0ExtSync = 45U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0ExtSync = 46U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0ExtSync = 47U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0ExtSync = 48U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0ExtSync = 49U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0ExtSync = 50U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0ExtSync = 51U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0ExtSync = 57U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0ExtSync = 58U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0ExtSync = 59U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0ExtSync = 60U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1ExtSync = 0U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1ExtSync = 1U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1ExtSync = 5U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1ExtSync = 6U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1ExtSync = 7U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1ExtSync = 8U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1ExtSync = 9U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1ExtSync = 11U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1ExtSync = 12U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1ExtSync = 13U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1ExtSync = 14U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1ExtSync = 15U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1ExtSync = 16U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1ExtSync = 17U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1ExtSync = 18U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1ExtSync = 19U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1ExtSync = 20U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1ExtSync = 21U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1ExtSync = 22U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1ExtSync = 24U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1ExtSync = 25U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1ExtSync = 26U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1ExtSync = 27U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1ExtSync = 28U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1ExtSync = 29U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1ExtSync = 30U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1ExtSync = 31U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1ExtSync = 32U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1ExtSync = 33U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1ExtSync = 34U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1ExtSync = 35U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1ExtSync = 36U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1ExtSync = 37U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1ExtSync = 38U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1ExtSync = 39U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1ExtSync = 40U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1ExtSync = 41U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1ExtSync = 42U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1ExtSync = 43U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1ExtSync = 44U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1ExtSync = 45U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1ExtSync = 46U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1ExtSync = 47U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1ExtSync = 48U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1ExtSync = 49U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1ExtSync = 50U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1ExtSync = 51U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1ExtSync = 57U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1ExtSync = 58U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1ExtSync = 59U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1ExtSync = 60U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2ExtSync = 0U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2ExtSync = 1U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2ExtSync = 5U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2ExtSync = 6U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2ExtSync = 7U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2ExtSync = 8U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2ExtSync = 9U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2ExtSync = 11U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2ExtSync = 12U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2ExtSync = 13U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2ExtSync = 14U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2ExtSync = 15U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2ExtSync = 16U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2ExtSync = 17U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2ExtSync = 18U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2ExtSync = 19U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2ExtSync = 20U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2ExtSync = 21U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2ExtSync = 22U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2ExtSync = 24U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2ExtSync = 25U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2ExtSync = 26U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2ExtSync = 27U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2ExtSync = 28U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2ExtSync = 29U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2ExtSync = 30U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2ExtSync = 31U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2ExtSync = 32U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2ExtSync = 33U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2ExtSync = 34U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2ExtSync = 35U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2ExtSync = 36U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2ExtSync = 37U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2ExtSync = 38U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2ExtSync = 39U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2ExtSync = 40U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2ExtSync = 41U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2ExtSync = 42U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2ExtSync = 43U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2ExtSync = 44U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2ExtSync = 45U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2ExtSync = 46U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2ExtSync = 47U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2ExtSync = 48U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2ExtSync = 49U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2ExtSync = 50U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2ExtSync = 51U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2ExtSync = 57U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2ExtSync = 58U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2ExtSync = 59U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2ExtSync = 60U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3ExtSync = 0U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3ExtSync = 1U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3ExtSync = 5U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3ExtSync = 6U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3ExtSync = 7U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3ExtSync = 8U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3ExtSync = 9U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3ExtSync = 11U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3ExtSync = 12U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3ExtSync = 13U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3ExtSync = 14U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3ExtSync = 15U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3ExtSync = 16U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3ExtSync = 17U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3ExtSync = 18U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3ExtSync = 19U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3ExtSync = 20U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3ExtSync = 21U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3ExtSync = 22U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3ExtSync = 24U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3ExtSync = 25U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3ExtSync = 26U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3ExtSync = 27U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3ExtSync = 28U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3ExtSync = 29U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3ExtSync = 30U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3ExtSync = 31U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3ExtSync = 32U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3ExtSync = 33U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3ExtSync = 34U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3ExtSync = 35U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3ExtSync = 36U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3ExtSync = 37U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3ExtSync = 38U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3ExtSync = 39U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3ExtSync = 40U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3ExtSync = 41U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3ExtSync = 42U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3ExtSync = 43U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3ExtSync = 44U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3ExtSync = 45U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3ExtSync = 46U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3ExtSync = 47U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3ExtSync = 48U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3ExtSync = 49U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3ExtSync = 50U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3ExtSync = 51U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3ExtSync = 57U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3ExtSync = 58U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3ExtSync = 59U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3ExtSync = 60U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0Exta = 0U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0Exta = 1U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta = 5U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta = 6U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta = 7U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0Exta = 8U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0Exta = 9U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta = 11U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0Exta = 12U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0Exta = 13U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0Exta = 14U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0Exta = 15U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0Exta = 16U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0Exta = 17U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0Exta = 18U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0Exta = 19U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0Exta = 20U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta = 21U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta = 22U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0Exta = 24U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0Exta = 25U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0Exta = 26U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0Exta = 27U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0Exta = 28U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0Exta = 29U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0Exta = 30U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0Exta = 31U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0Exta = 32U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0Exta = 33U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0Exta = 34U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0Exta = 35U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0Exta = 36U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0Exta = 37U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0Exta = 38U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0Exta = 39U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0Exta = 40U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0Exta = 41U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta = 42U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta = 43U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta = 44U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta = 45U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta = 46U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta = 47U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta = 48U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta = 49U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta = 50U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta = 51U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta = 57U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0Exta = 58U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta = 59U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0Exta = 60U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1Exta = 0U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1Exta = 1U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta = 5U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta = 6U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta = 7U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1Exta = 8U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1Exta = 9U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta = 11U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1Exta = 12U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1Exta = 13U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1Exta = 14U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1Exta = 15U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1Exta = 16U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1Exta = 17U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1Exta = 18U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1Exta = 19U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1Exta = 20U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta = 21U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta = 22U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1Exta = 24U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1Exta = 25U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1Exta = 26U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1Exta = 27U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1Exta = 28U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1Exta = 29U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1Exta = 30U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1Exta = 31U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1Exta = 32U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1Exta = 33U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1Exta = 34U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1Exta = 35U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1Exta = 36U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1Exta = 37U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1Exta = 38U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1Exta = 39U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1Exta = 40U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1Exta = 41U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta = 42U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta = 43U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta = 44U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta = 45U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta = 46U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta = 47U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta = 48U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta = 49U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta = 50U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta = 51U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta = 57U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1Exta = 58U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta = 59U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1Exta = 60U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2Exta = 0U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2Exta = 1U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta = 5U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta = 6U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta = 7U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2Exta = 8U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2Exta = 9U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta = 11U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2Exta = 12U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2Exta = 13U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2Exta = 14U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2Exta = 15U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2Exta = 16U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2Exta = 17U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2Exta = 18U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2Exta = 19U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2Exta = 20U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta = 21U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta = 22U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2Exta = 24U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2Exta = 25U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2Exta = 26U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2Exta = 27U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2Exta = 28U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2Exta = 29U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2Exta = 30U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2Exta = 31U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2Exta = 32U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2Exta = 33U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2Exta = 34U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2Exta = 35U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2Exta = 36U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2Exta = 37U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2Exta = 38U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2Exta = 39U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2Exta = 40U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2Exta = 41U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta = 42U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta = 43U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta = 44U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta = 45U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta = 46U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta = 47U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta = 48U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta = 49U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta = 50U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta = 51U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta = 57U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2Exta = 58U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta = 59U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2Exta = 60U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3Exta = 0U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3Exta = 1U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta = 5U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta = 6U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta = 7U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3Exta = 8U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3Exta = 9U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta = 11U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3Exta = 12U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3Exta = 13U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3Exta = 14U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3Exta = 15U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3Exta = 16U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3Exta = 17U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3Exta = 18U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3Exta = 19U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3Exta = 20U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta = 21U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta = 22U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3Exta = 24U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3Exta = 25U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3Exta = 26U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3Exta = 27U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3Exta = 28U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3Exta = 29U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3Exta = 30U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3Exta = 31U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3Exta = 32U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3Exta = 33U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3Exta = 34U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3Exta = 35U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3Exta = 36U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3Exta = 37U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3Exta = 38U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3Exta = 39U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3Exta = 40U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3Exta = 41U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta = 42U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta = 43U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta = 44U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta = 45U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta = 46U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta = 47U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta = 48U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta = 49U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta = 50U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta = 51U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta = 57U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3Exta = 58U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta = 59U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3Exta = 60U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0ExtForce = 0U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0ExtForce = 1U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0ExtForce = 5U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0ExtForce = 6U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0ExtForce = 7U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0ExtForce = 8U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0ExtForce = 9U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0ExtForce = 11U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0ExtForce = 12U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0ExtForce = 13U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0ExtForce = 14U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0ExtForce = 15U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0ExtForce = 16U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0ExtForce = 17U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0ExtForce = 18U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0ExtForce = 19U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0ExtForce = 20U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0ExtForce = 21U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0ExtForce = 22U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0ExtForce = 24U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0ExtForce = 25U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0ExtForce = 26U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0ExtForce = 27U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0ExtForce = 28U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0ExtForce = 29U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0ExtForce = 30U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0ExtForce = 31U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0ExtForce = 32U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0ExtForce = 33U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0ExtForce = 34U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0ExtForce = 35U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0ExtForce = 36U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0ExtForce = 37U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0ExtForce = 38U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0ExtForce = 39U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0ExtForce = 40U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0ExtForce = 41U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0ExtForce = 42U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0ExtForce = 43U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0ExtForce = 44U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0ExtForce = 45U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0ExtForce = 46U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0ExtForce = 47U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0ExtForce = 48U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0ExtForce = 49U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0ExtForce = 50U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0ExtForce = 51U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0ExtForce = 57U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0ExtForce = 58U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0ExtForce = 59U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0ExtForce = 60U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault0 = 0U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault0 = 1U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault0 = 5U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault0 = 6U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault0 = 7U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault0 = 8U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault0 = 9U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault0 = 11U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault0 = 12U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault0 = 13U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault0 = 14U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault0 = 15U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault0 = 16U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault0 = 17U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault0 = 18U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault0 = 19U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault0 = 20U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault0 = 21U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault0 = 22U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault0 = 24U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault0 = 25U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault0 = 26U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault0 = 27U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault0 = 28U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault0 = 29U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault0 = 30U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault0 = 31U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault0 = 32U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault0 = 33U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault0 = 34U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault0 = 35U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault0 = 36U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault0 = 37U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault0 = 38U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault0 = 39U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault0 = 40U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault0 = 41U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault0 = 42U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault0 = 43U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault0 = 44U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault0 = 45U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault0 = 46U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault0 = 47U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault0 = 48U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault0 = 49U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault0 = 50U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault0 = 51U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault0 = 57U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault0 = 58U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault0 = 59U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault0 = 60U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault1 = 0U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault1 = 1U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault1 = 5U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault1 = 6U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault1 = 7U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault1 = 8U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault1 = 9U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault1 = 11U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault1 = 12U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault1 = 13U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault1 = 14U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault1 = 15U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault1 = 16U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault1 = 17U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault1 = 18U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault1 = 19U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault1 = 20U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault1 = 21U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault1 = 22U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault1 = 24U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault1 = 25U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault1 = 26U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault1 = 27U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault1 = 28U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault1 = 29U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault1 = 30U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault1 = 31U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault1 = 32U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault1 = 33U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault1 = 34U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault1 = 35U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault1 = 36U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault1 = 37U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault1 = 38U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault1 = 39U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault1 = 40U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault1 = 41U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault1 = 42U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault1 = 43U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault1 = 44U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault1 = 45U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault1 = 46U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault1 = 47U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault1 = 48U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault1 = 49U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault1 = 50U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault1 = 51U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault1 = 57U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault1 = 58U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault1 = 59U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault1 = 60U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault2 = 0U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault2 = 1U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault2 = 5U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault2 = 6U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault2 = 7U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault2 = 8U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault2 = 9U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault2 = 11U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault2 = 12U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault2 = 13U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault2 = 14U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault2 = 15U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault2 = 16U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault2 = 17U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault2 = 18U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault2 = 19U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault2 = 20U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault2 = 21U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault2 = 22U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault2 = 24U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault2 = 25U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault2 = 26U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault2 = 27U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault2 = 28U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault2 = 29U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault2 = 30U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault2 = 31U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault2 = 32U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault2 = 33U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault2 = 34U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault2 = 35U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault2 = 36U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault2 = 37U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault2 = 38U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault2 = 39U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault2 = 40U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault2 = 41U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault2 = 42U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault2 = 43U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault2 = 44U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault2 = 45U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault2 = 46U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault2 = 47U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault2 = 48U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault2 = 49U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault2 = 50U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault2 = 51U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault2 = 57U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault2 = 58U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault2 = 59U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault2 = 60U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault3 = 0U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault3 = 1U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault3 = 5U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault3 = 6U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault3 = 7U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault3 = 8U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault3 = 9U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault3 = 11U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault3 = 12U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault3 = 13U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault3 = 14U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault3 = 15U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault3 = 16U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault3 = 17U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault3 = 18U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault3 = 19U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault3 = 20U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault3 = 21U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault3 = 22U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault3 = 24U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault3 = 25U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault3 = 26U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault3 = 27U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault3 = 28U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault3 = 29U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault3 = 30U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault3 = 31U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault3 = 32U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault3 = 33U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault3 = 34U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault3 = 35U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault3 = 36U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault3 = 37U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault3 = 38U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault3 = 39U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault3 = 40U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault3 = 41U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault3 = 42U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault3 = 43U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault3 = 44U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault3 = 45U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault3 = 46U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault3 = 47U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault3 = 48U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault3 = 49U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault3 = 50U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault3 = 51U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault3 = 57U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault3 = 58U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault3 = 59U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault3 = 60U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0ExtSync = 0U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0ExtSync = 1U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0ExtSync = 5U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0ExtSync = 6U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0ExtSync = 7U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0ExtSync = 8U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0ExtSync = 9U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0ExtSync = 11U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0ExtSync = 12U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0ExtSync = 13U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0ExtSync = 14U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0ExtSync = 15U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0ExtSync = 16U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0ExtSync = 17U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0ExtSync = 18U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0ExtSync = 19U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0ExtSync = 20U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0ExtSync = 21U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0ExtSync = 22U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0ExtSync = 24U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0ExtSync = 25U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0ExtSync = 26U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0ExtSync = 27U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0ExtSync = 28U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0ExtSync = 29U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0ExtSync = 30U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0ExtSync = 31U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0ExtSync = 32U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0ExtSync = 33U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0ExtSync = 34U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0ExtSync = 35U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0ExtSync = 36U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0ExtSync = 37U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0ExtSync = 38U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0ExtSync = 39U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0ExtSync = 40U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0ExtSync = 41U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0ExtSync = 42U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0ExtSync = 43U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0ExtSync = 44U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0ExtSync = 45U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0ExtSync = 46U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0ExtSync = 47U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0ExtSync = 48U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0ExtSync = 49U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0ExtSync = 50U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0ExtSync = 51U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0ExtSync = 57U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0ExtSync = 58U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0ExtSync = 59U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0ExtSync = 60U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1ExtSync = 0U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1ExtSync = 1U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1ExtSync = 5U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1ExtSync = 6U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1ExtSync = 7U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1ExtSync = 8U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1ExtSync = 9U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1ExtSync = 11U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1ExtSync = 12U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1ExtSync = 13U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1ExtSync = 14U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1ExtSync = 15U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1ExtSync = 16U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1ExtSync = 17U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1ExtSync = 18U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1ExtSync = 19U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1ExtSync = 20U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1ExtSync = 21U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1ExtSync = 22U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1ExtSync = 24U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1ExtSync = 25U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1ExtSync = 26U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1ExtSync = 27U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1ExtSync = 28U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1ExtSync = 29U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1ExtSync = 30U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1ExtSync = 31U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1ExtSync = 32U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1ExtSync = 33U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1ExtSync = 34U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1ExtSync = 35U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1ExtSync = 36U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1ExtSync = 37U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1ExtSync = 38U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1ExtSync = 39U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1ExtSync = 40U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1ExtSync = 41U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1ExtSync = 42U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1ExtSync = 43U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1ExtSync = 44U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1ExtSync = 45U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1ExtSync = 46U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1ExtSync = 47U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1ExtSync = 48U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1ExtSync = 49U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1ExtSync = 50U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1ExtSync = 51U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1ExtSync = 57U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1ExtSync = 58U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1ExtSync = 59U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1ExtSync = 60U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2ExtSync = 0U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2ExtSync = 1U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2ExtSync = 5U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2ExtSync = 6U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2ExtSync = 7U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2ExtSync = 8U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2ExtSync = 9U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2ExtSync = 11U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2ExtSync = 12U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2ExtSync = 13U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2ExtSync = 14U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2ExtSync = 15U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2ExtSync = 16U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2ExtSync = 17U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2ExtSync = 18U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2ExtSync = 19U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2ExtSync = 20U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2ExtSync = 21U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2ExtSync = 22U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2ExtSync = 24U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2ExtSync = 25U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2ExtSync = 26U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2ExtSync = 27U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2ExtSync = 28U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2ExtSync = 29U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2ExtSync = 30U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2ExtSync = 31U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2ExtSync = 32U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2ExtSync = 33U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2ExtSync = 34U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2ExtSync = 35U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2ExtSync = 36U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2ExtSync = 37U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2ExtSync = 38U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2ExtSync = 39U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2ExtSync = 40U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2ExtSync = 41U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2ExtSync = 42U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2ExtSync = 43U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2ExtSync = 44U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2ExtSync = 45U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2ExtSync = 46U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2ExtSync = 47U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2ExtSync = 48U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2ExtSync = 49U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2ExtSync = 50U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2ExtSync = 51U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2ExtSync = 57U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2ExtSync = 58U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2ExtSync = 59U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2ExtSync = 60U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3ExtSync = 0U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3ExtSync = 1U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3ExtSync = 5U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3ExtSync = 6U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3ExtSync = 7U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3ExtSync = 8U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3ExtSync = 9U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3ExtSync = 11U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3ExtSync = 12U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3ExtSync = 13U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3ExtSync = 14U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3ExtSync = 15U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3ExtSync = 16U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3ExtSync = 17U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3ExtSync = 18U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3ExtSync = 19U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3ExtSync = 20U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3ExtSync = 21U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3ExtSync = 22U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3ExtSync = 24U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3ExtSync = 25U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3ExtSync = 26U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3ExtSync = 27U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3ExtSync = 28U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3ExtSync = 29U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3ExtSync = 30U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3ExtSync = 31U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3ExtSync = 32U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3ExtSync = 33U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3ExtSync = 34U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3ExtSync = 35U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3ExtSync = 36U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3ExtSync = 37U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3ExtSync = 38U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3ExtSync = 39U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3ExtSync = 40U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3ExtSync = 41U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3ExtSync = 42U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3ExtSync = 43U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3ExtSync = 44U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3ExtSync = 45U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3ExtSync = 46U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3ExtSync = 47U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3ExtSync = 48U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3ExtSync = 49U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3ExtSync = 50U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3ExtSync = 51U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3ExtSync = 57U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3ExtSync = 58U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3ExtSync = 59U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3ExtSync = 60U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0Exta = 0U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0Exta = 1U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta = 5U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta = 6U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta = 7U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0Exta = 8U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0Exta = 9U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta = 11U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0Exta = 12U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0Exta = 13U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0Exta = 14U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0Exta = 15U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0Exta = 16U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0Exta = 17U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0Exta = 18U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0Exta = 19U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0Exta = 20U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta = 21U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta = 22U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0Exta = 24U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0Exta = 25U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0Exta = 26U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0Exta = 27U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0Exta = 28U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0Exta = 29U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0Exta = 30U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0Exta = 31U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0Exta = 32U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0Exta = 33U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0Exta = 34U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0Exta = 35U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0Exta = 36U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0Exta = 37U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0Exta = 38U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0Exta = 39U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0Exta = 40U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0Exta = 41U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta = 42U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta = 43U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta = 44U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta = 45U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta = 46U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta = 47U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta = 48U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta = 49U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta = 50U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta = 51U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta = 57U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0Exta = 58U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta = 59U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0Exta = 60U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1Exta = 0U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1Exta = 1U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta = 5U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta = 6U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta = 7U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1Exta = 8U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1Exta = 9U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta = 11U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1Exta = 12U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1Exta = 13U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1Exta = 14U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1Exta = 15U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1Exta = 16U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1Exta = 17U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1Exta = 18U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1Exta = 19U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1Exta = 20U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta = 21U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta = 22U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1Exta = 24U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1Exta = 25U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1Exta = 26U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1Exta = 27U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1Exta = 28U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1Exta = 29U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1Exta = 30U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1Exta = 31U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1Exta = 32U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1Exta = 33U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1Exta = 34U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1Exta = 35U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1Exta = 36U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1Exta = 37U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1Exta = 38U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1Exta = 39U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1Exta = 40U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1Exta = 41U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta = 42U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta = 43U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta = 44U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta = 45U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta = 46U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta = 47U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta = 48U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta = 49U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta = 50U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta = 51U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta = 57U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1Exta = 58U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta = 59U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1Exta = 60U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2Exta = 0U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2Exta = 1U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta = 5U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta = 6U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta = 7U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2Exta = 8U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2Exta = 9U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta = 11U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2Exta = 12U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2Exta = 13U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2Exta = 14U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2Exta = 15U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2Exta = 16U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2Exta = 17U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2Exta = 18U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2Exta = 19U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2Exta = 20U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta = 21U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta = 22U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2Exta = 24U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2Exta = 25U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2Exta = 26U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2Exta = 27U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2Exta = 28U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2Exta = 29U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2Exta = 30U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2Exta = 31U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2Exta = 32U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2Exta = 33U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2Exta = 34U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2Exta = 35U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2Exta = 36U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2Exta = 37U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2Exta = 38U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2Exta = 39U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2Exta = 40U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2Exta = 41U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta = 42U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta = 43U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta = 44U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta = 45U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta = 46U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta = 47U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta = 48U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta = 49U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta = 50U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta = 51U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta = 57U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2Exta = 58U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta = 59U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2Exta = 60U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3Exta = 0U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3Exta = 1U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta = 5U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta = 6U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta = 7U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3Exta = 8U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3Exta = 9U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta = 11U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3Exta = 12U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3Exta = 13U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3Exta = 14U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3Exta = 15U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3Exta = 16U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3Exta = 17U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3Exta = 18U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3Exta = 19U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3Exta = 20U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta = 21U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta = 22U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3Exta = 24U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3Exta = 25U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3Exta = 26U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3Exta = 27U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3Exta = 28U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3Exta = 29U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3Exta = 30U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3Exta = 31U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3Exta = 32U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3Exta = 33U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3Exta = 34U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3Exta = 35U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3Exta = 36U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3Exta = 37U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3Exta = 38U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3Exta = 39U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3Exta = 40U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3Exta = 41U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta = 42U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta = 43U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta = 44U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta = 45U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta = 46U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta = 47U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta = 48U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta = 49U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta = 50U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta = 51U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta = 57U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3Exta = 58U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta = 59U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3Exta = 60U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1ExtForce = 0U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1ExtForce = 1U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1ExtForce = 5U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1ExtForce = 6U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1ExtForce = 7U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1ExtForce = 8U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1ExtForce = 9U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1ExtForce = 11U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1ExtForce = 12U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1ExtForce = 13U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1ExtForce = 14U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1ExtForce = 15U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1ExtForce = 16U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1ExtForce = 17U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1ExtForce = 18U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1ExtForce = 19U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1ExtForce = 20U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1ExtForce = 21U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1ExtForce = 22U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1ExtForce = 24U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1ExtForce = 25U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1ExtForce = 26U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1ExtForce = 27U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1ExtForce = 28U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1ExtForce = 29U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1ExtForce = 30U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1ExtForce = 31U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1ExtForce = 32U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1ExtForce = 33U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1ExtForce = 34U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1ExtForce = 35U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1ExtForce = 36U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1ExtForce = 37U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1ExtForce = 38U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1ExtForce = 39U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1ExtForce = 40U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1ExtForce = 41U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1ExtForce = 42U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1ExtForce = 43U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1ExtForce = 44U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1ExtForce = 45U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1ExtForce = 46U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1ExtForce = 47U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1ExtForce = 48U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1ExtForce = 49U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1ExtForce = 50U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1ExtForce = 51U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1ExtForce = 57U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1ExtForce = 58U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1ExtForce = 59U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1ExtForce = 60U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault0 = 0U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault0 = 1U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault0 = 5U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault0 = 6U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault0 = 7U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault0 = 8U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault0 = 9U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault0 = 11U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault0 = 12U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault0 = 13U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault0 = 14U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault0 = 15U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault0 = 16U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault0 = 17U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault0 = 18U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault0 = 19U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault0 = 20U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault0 = 21U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault0 = 22U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault0 = 24U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault0 = 25U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault0 = 26U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault0 = 27U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault0 = 28U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault0 = 29U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault0 = 30U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault0 = 31U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault0 = 32U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault0 = 33U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault0 = 34U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault0 = 35U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault0 = 36U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault0 = 37U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault0 = 38U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault0 = 39U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault0 = 40U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault0 = 41U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault0 = 42U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault0 = 43U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault0 = 44U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault0 = 45U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault0 = 46U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault0 = 47U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault0 = 48U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault0 = 49U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault0 = 50U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault0 = 51U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault0 = 57U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault0 = 58U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault0 = 59U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault0 = 60U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault1 = 0U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault1 = 1U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault1 = 5U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault1 = 6U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault1 = 7U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault1 = 8U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault1 = 9U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault1 = 11U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault1 = 12U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault1 = 13U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault1 = 14U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault1 = 15U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault1 = 16U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault1 = 17U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault1 = 18U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault1 = 19U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault1 = 20U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault1 = 21U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault1 = 22U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault1 = 24U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault1 = 25U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault1 = 26U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault1 = 27U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault1 = 28U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault1 = 29U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault1 = 30U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault1 = 31U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault1 = 32U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault1 = 33U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault1 = 34U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault1 = 35U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault1 = 36U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault1 = 37U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault1 = 38U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault1 = 39U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault1 = 40U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault1 = 41U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault1 = 42U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault1 = 43U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault1 = 44U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault1 = 45U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault1 = 46U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault1 = 47U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault1 = 48U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault1 = 49U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault1 = 50U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault1 = 51U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault1 = 57U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault1 = 58U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault1 = 59U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault1 = 60U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault2 = 0U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault2 = 1U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault2 = 5U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault2 = 6U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault2 = 7U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault2 = 8U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault2 = 9U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault2 = 11U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault2 = 12U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault2 = 13U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault2 = 14U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault2 = 15U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault2 = 16U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault2 = 17U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault2 = 18U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault2 = 19U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault2 = 20U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault2 = 21U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault2 = 22U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault2 = 24U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault2 = 25U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault2 = 26U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault2 = 27U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault2 = 28U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault2 = 29U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault2 = 30U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault2 = 31U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault2 = 32U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault2 = 33U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault2 = 34U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault2 = 35U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault2 = 36U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault2 = 37U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault2 = 38U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault2 = 39U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault2 = 40U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault2 = 41U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault2 = 42U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault2 = 43U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault2 = 44U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault2 = 45U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault2 = 46U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault2 = 47U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault2 = 48U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault2 = 49U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault2 = 50U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault2 = 51U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault2 = 57U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault2 = 58U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault2 = 59U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault2 = 60U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault3 = 0U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault3 = 1U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault3 = 5U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault3 = 6U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault3 = 7U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault3 = 8U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault3 = 9U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault3 = 11U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault3 = 12U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault3 = 13U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault3 = 14U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault3 = 15U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault3 = 16U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault3 = 17U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault3 = 18U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault3 = 19U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault3 = 20U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault3 = 21U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault3 = 22U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault3 = 24U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault3 = 25U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault3 = 26U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault3 = 27U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault3 = 28U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault3 = 29U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault3 = 30U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault3 = 31U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault3 = 32U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault3 = 33U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault3 = 34U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault3 = 35U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault3 = 36U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault3 = 37U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault3 = 38U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault3 = 39U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault3 = 40U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault3 = 41U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault3 = 42U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault3 = 43U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault3 = 44U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault3 = 45U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault3 = 46U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault3 = 47U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault3 = 48U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault3 = 49U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault3 = 50U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault3 = 51U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault3 = 57U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault3 = 58U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault3 = 59U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault3 = 60U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Fro16KToPwm0ExtClk = 0U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Fro16KToPwm1ExtClk = 0U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< EVTG trigger input connections. */ + kINPUTMUX_PinInt0ToEvtgTrigger = 0U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToEvtgTrigger = 1U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEvtgTrigger = 6U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEvtgTrigger = 7U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEvtgTrigger = 8U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToEvtgTrigger = 9U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToEvtgTrigger = 10U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToEvtgTrigger = 11U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToEvtgTrigger = 13U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToEvtgTrigger = 14U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToEvtgTrigger = 15U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEvtgTrigger = 16U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEvtgTrigger = 17U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEvtgTrigger = 18U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEvtgTrigger = 19U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEvtgTrigger = 20U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEvtgTrigger = 21U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEvtgTrigger = 22U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEvtgTrigger = 23U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToEvtgTrigger = 24U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToEvtgTrigger = 25U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToEvtgTrigger = 27U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToEvtgTrigger = 28U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToEvtgTrigger = 29U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToEvtgTrigger = 30U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToEvtgTrigger = 31U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToEvtgTrigger = 32U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToEvtgTrigger = 33U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToEvtgTrigger = 34U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToEvtgTrigger = 35U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToEvtgTrigger = 36U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToEvtgTrigger = 37U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToEvtgTrigger = 38U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToEvtgTrigger = 39U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToEvtgTrigger = 40U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToEvtgTrigger = 41U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToEvtgTrigger = 42U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToEvtgTrigger = 43U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToEvtgTrigger = 44U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToEvtgTrigger = 45U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToEvtgTrigger = 46U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToEvtgTrigger = 47U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToEvtgTrigger = 48U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToEvtgTrigger = 49U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToEvtgTrigger = 50U + (EVTG_TRIG0_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_PinInt0ToExtTrigger = 0U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToExtTrigger = 1U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToExtTrigger = 8U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToExtTrigger = 20U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToExtTrigger = 21U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToExtTrigger = 22U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToExtTrigger = 23U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToExtTrigger = 26U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToExtTrigger = 27U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig3ToExtTrigger = 34U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig3ToExtTrigger = 35U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig3ToExtTrigger = 36U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToExtTrigger = 37U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm4Trig3ToExtTrigger = 38U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm5Trig3ToExtTrigger = 39U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm6Trig3ToExtTrigger = 40U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm7Trig3ToExtTrigger = 41U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 44U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 45U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< FLEXCOMM0 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm0Trigger = 0U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm0Trigger = 1U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm0Trigger = 2U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm0Trigger = 6U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm0Trigger = 7U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm0Trigger = 8U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm0Trigger = 9U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm0Trigger = 10U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm0Trigger = 11U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm0Trigger = 12U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm0Trigger = 13U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm0Trigger = 14U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm0Trigger = 15U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm0Trigger = 16U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm0Trigger = 18U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm0Trigger = 19U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm0Trigger = 20U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm0Trigger = 21U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm0Trigger = 22U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm0Trigger = 23U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm0Trigger = 24U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm0Trigger = 25U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm0Trigger = 26U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm0Trigger = 27U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm0Trigger = 28U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm0Trigger = 29U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm0Trigger = 30U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm0Trigger = 31U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm0Trigger = 32U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm0Trigger = 33U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm0Trigger = 34U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm0Trigger = 35U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm0Trigger = 36U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm0Trigger = 37U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm0Trigger = 38U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm0Trigger = 39U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm0Trigger = 40U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm0Trigger = 41U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm0Trigger = 42U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM1 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm1Trigger = 0U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm1Trigger = 1U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm1Trigger = 2U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm1Trigger = 6U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm1Trigger = 7U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm1Trigger = 8U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm1Trigger = 9U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm1Trigger = 10U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm1Trigger = 11U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm1Trigger = 12U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm1Trigger = 13U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm1Trigger = 14U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm1Trigger = 15U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm1Trigger = 16U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm1Trigger = 18U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm1Trigger = 19U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm1Trigger = 20U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm1Trigger = 21U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm1Trigger = 22U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm1Trigger = 23U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm1Trigger = 24U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm1Trigger = 25U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm1Trigger = 26U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm1Trigger = 27U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm1Trigger = 28U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm1Trigger = 29U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm1Trigger = 30U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm1Trigger = 31U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm1Trigger = 32U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm1Trigger = 33U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm1Trigger = 34U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm1Trigger = 35U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm1Trigger = 36U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm1Trigger = 37U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm1Trigger = 38U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm1Trigger = 39U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm1Trigger = 40U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm1Trigger = 41U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm1Trigger = 42U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM2 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm2Trigger = 0U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm2Trigger = 1U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm2Trigger = 2U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm2Trigger = 6U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm2Trigger = 7U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm2Trigger = 8U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm2Trigger = 9U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm2Trigger = 10U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm2Trigger = 11U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm2Trigger = 12U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm2Trigger = 13U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm2Trigger = 14U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm2Trigger = 15U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm2Trigger = 16U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm2Trigger = 18U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm2Trigger = 19U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm2Trigger = 20U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm2Trigger = 21U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm2Trigger = 22U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm2Trigger = 23U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm2Trigger = 24U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm2Trigger = 25U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm2Trigger = 26U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm2Trigger = 27U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm2Trigger = 28U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm2Trigger = 29U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm2Trigger = 30U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm2Trigger = 31U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm2Trigger = 32U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm2Trigger = 33U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm2Trigger = 34U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm2Trigger = 35U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm2Trigger = 36U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm2Trigger = 37U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm2Trigger = 38U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm2Trigger = 39U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm2Trigger = 40U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm2Trigger = 41U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm2Trigger = 42U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM3 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm3Trigger = 0U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm3Trigger = 1U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm3Trigger = 2U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm3Trigger = 6U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm3Trigger = 7U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm3Trigger = 8U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm3Trigger = 9U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm3Trigger = 10U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm3Trigger = 11U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm3Trigger = 12U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm3Trigger = 13U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm3Trigger = 14U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm3Trigger = 15U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm3Trigger = 16U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm3Trigger = 18U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm3Trigger = 19U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm3Trigger = 20U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm3Trigger = 21U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm3Trigger = 22U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm3Trigger = 23U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm3Trigger = 24U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm3Trigger = 25U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm3Trigger = 26U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm3Trigger = 27U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm3Trigger = 28U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm3Trigger = 29U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm3Trigger = 30U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm3Trigger = 31U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm3Trigger = 32U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm3Trigger = 33U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm3Trigger = 34U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm3Trigger = 35U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm3Trigger = 36U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm3Trigger = 37U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm3Trigger = 38U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm3Trigger = 39U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm3Trigger = 40U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm3Trigger = 41U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm3Trigger = 42U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM4 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm4Trigger = 0U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm4Trigger = 1U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm4Trigger = 2U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm4Trigger = 6U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm4Trigger = 7U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm4Trigger = 8U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm4Trigger = 9U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm4Trigger = 10U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm4Trigger = 11U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm4Trigger = 12U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm4Trigger = 13U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm4Trigger = 14U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm4Trigger = 15U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm4Trigger = 16U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm4Trigger = 18U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm4Trigger = 19U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm4Trigger = 20U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm4Trigger = 21U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm4Trigger = 22U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm4Trigger = 23U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm4Trigger = 24U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm4Trigger = 25U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm4Trigger = 26U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm4Trigger = 27U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm4Trigger = 28U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm4Trigger = 29U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm4Trigger = 30U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm4Trigger = 31U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm4Trigger = 32U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm4Trigger = 33U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm4Trigger = 34U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm4Trigger = 35U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm4Trigger = 36U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm4Trigger = 37U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm4Trigger = 38U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm4Trigger = 39U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm4Trigger = 40U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm4Trigger = 41U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm4Trigger = 42U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM5 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm5Trigger = 0U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm5Trigger = 1U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm5Trigger = 2U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm5Trigger = 6U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm5Trigger = 7U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm5Trigger = 8U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm5Trigger = 9U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm5Trigger = 10U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm5Trigger = 11U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm5Trigger = 12U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm5Trigger = 13U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm5Trigger = 14U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm5Trigger = 15U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm5Trigger = 16U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm5Trigger = 18U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm5Trigger = 19U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm5Trigger = 20U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm5Trigger = 21U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm5Trigger = 22U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm5Trigger = 23U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm5Trigger = 24U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm5Trigger = 25U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm5Trigger = 26U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm5Trigger = 27U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm5Trigger = 28U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm5Trigger = 29U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm5Trigger = 30U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm5Trigger = 31U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm5Trigger = 32U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm5Trigger = 33U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm5Trigger = 34U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm5Trigger = 35U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm5Trigger = 36U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm5Trigger = 37U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm5Trigger = 38U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm5Trigger = 39U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm5Trigger = 40U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm5Trigger = 41U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm5Trigger = 42U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM6 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm6Trigger = 0U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm6Trigger = 1U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm6Trigger = 2U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm6Trigger = 6U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm6Trigger = 7U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm6Trigger = 8U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm6Trigger = 9U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm6Trigger = 10U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm6Trigger = 11U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm6Trigger = 12U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm6Trigger = 13U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm6Trigger = 14U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm6Trigger = 15U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm6Trigger = 16U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm6Trigger = 18U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm6Trigger = 19U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm6Trigger = 20U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm6Trigger = 21U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm6Trigger = 22U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm6Trigger = 23U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm6Trigger = 24U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm6Trigger = 25U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm6Trigger = 26U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm6Trigger = 27U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm6Trigger = 28U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm6Trigger = 29U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm6Trigger = 30U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm6Trigger = 31U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm6Trigger = 32U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm6Trigger = 33U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm6Trigger = 34U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm6Trigger = 35U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm6Trigger = 36U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm6Trigger = 37U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm6Trigger = 38U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm6Trigger = 39U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm6Trigger = 40U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm6Trigger = 41U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm6Trigger = 42U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM7 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm7Trigger = 0U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm7Trigger = 1U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm7Trigger = 2U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm7Trigger = 6U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm7Trigger = 7U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm7Trigger = 8U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm7Trigger = 9U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm7Trigger = 10U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm7Trigger = 11U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm7Trigger = 12U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm7Trigger = 13U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm7Trigger = 14U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm7Trigger = 15U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm7Trigger = 16U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm7Trigger = 18U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm7Trigger = 19U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm7Trigger = 20U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm7Trigger = 21U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm7Trigger = 22U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm7Trigger = 23U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm7Trigger = 24U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm7Trigger = 25U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm7Trigger = 26U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm7Trigger = 27U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm7Trigger = 28U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm7Trigger = 29U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm7Trigger = 30U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm7Trigger = 31U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm7Trigger = 32U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm7Trigger = 33U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm7Trigger = 34U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm7Trigger = 35U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm7Trigger = 36U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm7Trigger = 37U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm7Trigger = 38U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm7Trigger = 39U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm7Trigger = 40U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm7Trigger = 41U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm7Trigger = 42U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + + /*!< FlexIO trigger input connections. */ + kINPUTMUX_PinInt4ToFlexioTrigger = 0U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 19U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig0ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig1ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig2ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig0ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig1ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig2ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig0ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig1ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig0ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig1ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig2ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 76U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma0Ch3Ena = 3U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma0Ch4Ena = 4U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma0Ch5Ena = 5U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma0Ch6Ena = 6U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0Ch7Ena = 7U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0Ch8Ena = 8U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0Ch9Ena = 9U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0Ch10Ena = 10U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0Ch11Ena = 11U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0Ch12Ena = 12U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0Ch13Ena = 13U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0Ch14Ena = 14U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0Ch15Ena = 15U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0Ch16Ena = 16U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma0Ch17Ena = 17U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma0Ch18Ena = 18U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma0Ch21Ena = 21U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma0Ch22Ena = 22U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma0Ch23Ena = 23U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestoDma0Ch24Ena = 24U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma0Ch28Ena = 28U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma0Ch29Ena = 29U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma0Ch31Ena = 31U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma0Ch32Ena = 0U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma0Ch33Ena = 1U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma0Ch34Ena = 2U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma0Ch35Ena = 3U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma0Ch36Ena = 4U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma0Ch37Ena = 5U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma0Ch38Ena = 6U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma0Ch39Ena = 7U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma0Ch40Ena = 8U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma0Ch41Ena = 9U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma0Ch42Ena = 10U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma0Ch43Ena = 11U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma0Ch44Ena = 12U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma0Ch45Ena = 13U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma0Ch46Ena = 14U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma0Ch47Ena = 15U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma0Ch48Ena = 16U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma0Ch49Ena = 17U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma0Ch50Ena = 18U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma0Ch51Ena = 19U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma0Ch52Ena = 20U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma0Ch53Ena = 21U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma0Ch54Ena = 22U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma0Ch57Ena = 25U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma0Ch58Ena = 26U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma0Ch59Ena = 27U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma0Ch60Ena = 28U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena = 29U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma0Ch62Ena = 30U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma0Ch63Ena = 31U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma0Ch64Ena = 0U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma0Ch65Ena = 1U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma0Ch66Ena = 2U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma0Ch67Ena = 3U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma0Ch68Ena = 4U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma0Ch69Ena = 5U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma0Ch70Ena = 6U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma0Ch71Ena = 7U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma0Ch72Ena = 8U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma0Ch73Ena = 9U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma0Ch74Ena = 10U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma0Ch75Ena = 11U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma0Ch76Ena = 12U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma0Ch77Ena = 13U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma0Ch78Ena = 14U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma0Ch79Ena = 15U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma0Ch80Ena = 16U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma0Ch81Ena = 17U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma0Ch82Ena = 18U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma0Ch83Ena = 19U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma0Ch84Ena = 20U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma0Ch95Ena = 31U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma0Ch96Ena = 0U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma0Ch97Ena = 1U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma0Ch98Ena = 2U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma0Ch99Ena = 3U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma0Ch100Ena = 4U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma0Ch101Ena = 5U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma0Ch102Ena = 6U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma0Ch108Ena = 12U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma0Ch109Ena = 13U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma0Ch110Ena = 14U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma0Ch111Ena = 15U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma0Ch112Ena = 16U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma0Ch113Ena = 17U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma0Ch114Ena = 18U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma0Ch115Ena = 19U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma0Ch116Ena = 20U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma0Ch117Ena = 21U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma0Ch118Ena = 22U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma0Ch119Ena = 23U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma1Ch3Ena = 3U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma1Ch4Ena = 4U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma1Ch5Ena = 5U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma1Ch6Ena = 6U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1Ch7Ena = 7U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1Ch8Ena = 8U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma1Ch9Ena = 9U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma1Ch10Ena = 10U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1Ch11Ena = 11U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma1Ch12Ena = 12U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma1Ch13Ena = 13U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma1Ch14Ena = 14U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1Ch15Ena = 15U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma1Ch16Ena = 16U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma1Ch17Ena = 17U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma1Ch18Ena = 18U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma1Ch21Ena = 21U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma1Ch22Ena = 22U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma1Ch23Ena = 23U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestToDma1Ch24Ena = 24U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma1Ch28Ena = 28U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma1Ch29Ena = 29U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma1Ch31Ena = 31U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma1Ch32Ena = 0U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma1Ch33Ena = 1U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma1Ch34Ena = 2U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma1Ch35Ena = 3U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma1Ch36Ena = 4U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma1Ch37Ena = 5U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma1Ch38Ena = 6U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma1Ch39Ena = 7U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma1Ch40Ena = 8U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma1Ch41Ena = 9U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma1Ch42Ena = 10U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma1Ch43Ena = 11U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma1Ch44Ena = 12U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma1Ch45Ena = 13U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma1Ch46Ena = 14U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma1Ch47Ena = 15U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma1Ch48Ena = 16U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma1Ch49Ena = 17U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma1Ch50Ena = 18U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma1Ch51Ena = 19U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma1Ch52Ena = 20U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma1Ch53Ena = 21U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma1Ch54Ena = 22U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma1Ch57Ena = 25U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma1Ch58Ena = 26U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma1Ch59Ena = 27U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma1Ch60Ena = 28U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma1Ch61Ena = 29U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma1Ch62Ena = 30U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma1Ch63Ena = 31U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma1Ch64Ena = 0U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma1Ch65Ena = 1U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma1Ch66Ena = 2U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma1Ch67Ena = 3U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma1Ch68Ena = 4U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma1Ch69Ena = 5U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma1Ch70Ena = 6U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma1Ch71Ena = 7U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma1Ch72Ena = 8U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma1Ch73Ena = 9U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma1Ch74Ena = 10U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma1Ch75Ena = 11U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma1Ch76Ena = 12U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma1Ch77Ena = 13U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma1Ch78Ena = 14U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma1Ch79Ena = 15U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma1Ch80Ena = 16U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma1Ch81Ena = 17U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma1Ch82Ena = 18U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma1Ch83Ena = 19U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma1Ch84Ena = 20U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch0ToDma1Ch89Ena = 25U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch1ToDma1Ch90Ena = 26U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma1Ch95Ena = 31U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma1Ch96Ena = 0U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma1Ch97Ena = 1U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma1Ch98Ena = 2U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma1Ch99Ena = 3U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma1Ch100Ena = 4U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma1Ch101Ena = 5U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma1Ch102Ena = 6U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma1Ch108Ena = 12U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma1Ch109Ena = 13U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma1Ch110Ena = 14U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma1Ch111Ena = 15U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma1Ch112Ena = 16U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma1Ch113Ena = 17U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma1Ch114Ena = 18U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma1Ch115Ena = 19U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma1Ch116Ena = 20U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma1Ch117Ena = 21U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma1Ch118Ena = 22U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma1Ch119Ena = 23U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/devices/MCXN236/drivers/fsl_reset.c b/devices/MCXN236/drivers/fsl_reset.c new file mode 100644 index 000000000..58c059950 --- /dev/null +++ b/devices/MCXN236/drivers/fsl_reset.c @@ -0,0 +1,102 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (0u == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (bitMask == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/devices/MCXN236/drivers/fsl_reset.h b/devices/MCXN236/drivers/fsl_reset.h new file mode 100644 index 000000000..59922b4fd --- /dev/null +++ b/devices/MCXN236/drivers/fsl_reset.h @@ -0,0 +1,224 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */ + kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */ + kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */ + kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */ + kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */ + kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */ + kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */ + kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */ + kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */ + kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */ + kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */ + kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */ + + kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */ + kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */ + kQDC0_RST_SHIFT_RSTn = 196608 | 4U, /**< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = 196608 | 5U, /**< QDC1 reset control */ + kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */ + kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */ + kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */ + kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */ + kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */ + kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define LP_FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define FLASH_RSTS \ + { \ + kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define TRNG_RSTS \ + { \ + kTRNG_RST_SHIFT_RSTn \ + } /* Reset bits for TRNG peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \ + } /* Reset bits for I3C peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/devices/MCXN236/fsl_device_registers.h b/devices/MCXN236/fsl_device_registers.h new file mode 100644 index 000000000..f270e5a75 --- /dev/null +++ b/devices/MCXN236/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN236VDF) || defined(CPU_MCXN236VNL)) + +#define MCXN236_SERIES + +/* CMSIS-style register definitions */ +#include "MCXN236.h" +/* CPU specific feature definitions */ +#include "MCXN236_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCXN236/gcc/MCXN236_flash.ld b/devices/MCXN236/gcc/MCXN236_flash.ld new file mode 100644 index 000000000..0c3cacbd9 --- /dev/null +++ b/devices/MCXN236/gcc/MCXN236_flash.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compiler: GNU C Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x000FFC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00038000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MCXN236/gcc/MCXN236_ram.ld b/devices/MCXN236/gcc/MCXN236_ram.ld new file mode 100644 index 000000000..343efa2bc --- /dev/null +++ b/devices/MCXN236/gcc/MCXN236_ram.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compiler: GNU C Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x04000400, LENGTH = 0x00017C00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00038000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/devices/MCXN236/gcc/startup_MCXN236.S b/devices/MCXN236/gcc/startup_MCXN236.S new file mode 100644 index 000000000..31c4031a0 --- /dev/null +++ b/devices/MCXN236/gcc/startup_MCXN236.S @@ -0,0 +1,1948 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MCXN236.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* MCXN236 */ +/* @version: 1.0 */ +/* @date: 2023-10-1 */ +/* @build: b240409 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2024 NXP */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long OR_IRQHandler /* OR IRQ*/ + .long EDMA_0_CH0_IRQHandler /* eDMA_0_CH0 error or transfer complete*/ + .long EDMA_0_CH1_IRQHandler /* eDMA_0_CH1 error or transfer complete*/ + .long EDMA_0_CH2_IRQHandler /* eDMA_0_CH2 error or transfer complete*/ + .long EDMA_0_CH3_IRQHandler /* eDMA_0_CH3 error or transfer complete*/ + .long EDMA_0_CH4_IRQHandler /* eDMA_0_CH4 error or transfer complete*/ + .long EDMA_0_CH5_IRQHandler /* eDMA_0_CH5 error or transfer complete*/ + .long EDMA_0_CH6_IRQHandler /* eDMA_0_CH6 error or transfer complete*/ + .long EDMA_0_CH7_IRQHandler /* eDMA_0_CH7 error or transfer complete*/ + .long EDMA_0_CH8_IRQHandler /* eDMA_0_CH8 error or transfer complete*/ + .long EDMA_0_CH9_IRQHandler /* eDMA_0_CH9 error or transfer complete*/ + .long EDMA_0_CH10_IRQHandler /* eDMA_0_CH10 error or transfer complete*/ + .long EDMA_0_CH11_IRQHandler /* eDMA_0_CH11 error or transfer complete*/ + .long EDMA_0_CH12_IRQHandler /* eDMA_0_CH12 error or transfer complete*/ + .long EDMA_0_CH13_IRQHandler /* eDMA_0_CH13 error or transfer complete*/ + .long EDMA_0_CH14_IRQHandler /* eDMA_0_CH14 error or transfer complete*/ + .long EDMA_0_CH15_IRQHandler /* eDMA_0_CH15 error or transfer complete*/ + .long GPIO00_IRQHandler /* GPIO0 interrupt 0*/ + .long GPIO01_IRQHandler /* GPIO0 interrupt 1*/ + .long GPIO10_IRQHandler /* GPIO1 interrupt 0*/ + .long GPIO11_IRQHandler /* GPIO1 interrupt 1*/ + .long GPIO20_IRQHandler /* GPIO2 interrupt 0*/ + .long GPIO21_IRQHandler /* GPIO2 interrupt 1*/ + .long GPIO30_IRQHandler /* GPIO3 interrupt 0*/ + .long GPIO31_IRQHandler /* GPIO3 interrupt 1*/ + .long GPIO40_IRQHandler /* GPIO4 interrupt 0*/ + .long GPIO41_IRQHandler /* GPIO4 interrupt 1*/ + .long GPIO50_IRQHandler /* GPIO5 interrupt 0*/ + .long GPIO51_IRQHandler /* GPIO5 interrupt 1*/ + .long UTICK0_IRQHandler /* Micro-Tick Timer interrupt*/ + .long MRT0_IRQHandler /* Multi-Rate Timer interrupt*/ + .long CTIMER0_IRQHandler /* Standard counter/timer 0 interrupt*/ + .long CTIMER1_IRQHandler /* Standard counter/timer 1 interrupt*/ + .long Reserved49_IRQHandler /* Reserved interrupt*/ + .long CTIMER2_IRQHandler /* Standard counter/timer 2 interrupt*/ + .long LP_FLEXCOMM0_IRQHandler /* LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM1_IRQHandler /* LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM2_IRQHandler /* LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM3_IRQHandler /* LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM4_IRQHandler /* LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM5_IRQHandler /* LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM6_IRQHandler /* LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM7_IRQHandler /* LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long Reserved60_IRQHandler /* Reserved interrupt*/ + .long ADC0_IRQHandler /* Analog-to-Digital Converter 0 - General Purpose interrupt*/ + .long ADC1_IRQHandler /* Analog-to-Digital Converter 1 - General Purpose interrupt*/ + .long PINT0_IRQHandler /* Pin Interrupt Pattern Match Interrupt*/ + .long PDM_EVENT_IRQHandler /* Microphone Interface interrupt */ + .long Reserved65_IRQHandler /* Reserved interrupt*/ + .long Reserved66_IRQHandler /* Reserved interrupt*/ + .long USB0_DCD_IRQHandler /* Universal Serial Bus - Device Charge Detect interrupt*/ + .long RTC_IRQHandler /* RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt)*/ + .long SMARTDMA_IRQHandler /* SmartDMA_IRQ*/ + .long Reserved70_IRQHandler /* Reserved interrupt*/ + .long CTIMER3_IRQHandler /* Standard counter/timer 3 interrupt*/ + .long CTIMER4_IRQHandler /* Standard counter/timer 4 interrupt*/ + .long OS_EVENT_IRQHandler /* OS event timer interrupt*/ + .long Reserved74_IRQHandler /* Reserved interrupt*/ + .long SAI0_IRQHandler /* Serial Audio Interface 0 interrupt*/ + .long SAI1_IRQHandler /* Serial Audio Interface 1 interrupt*/ + .long Reserved77_IRQHandler /* Reserved interrupt*/ + .long CAN0_IRQHandler /* Controller Area Network 0 interrupt*/ + .long CAN1_IRQHandler /* Controller Area Network 1 interrupt*/ + .long Reserved80_IRQHandler /* Reserved interrupt*/ + .long Reserved81_IRQHandler /* Reserved interrupt*/ + .long USB1_HS_PHY_IRQHandler /* USBHS DCD or USBHS Phy interrupt*/ + .long USB1_HS_IRQHandler /* USB High Speed OTG Controller interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* AHB Secure Controller hypervisor call interrupt*/ + .long Reserved85_IRQHandler /* Reserved interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Freqme_IRQHandler /* Frequency Measurement interrupt*/ + .long SEC_VIO_IRQHandler /* Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt)*/ + .long ELS_IRQHandler /* ELS interrupt*/ + .long PKC_IRQHandler /* PKC interrupt*/ + .long PUF_IRQHandler /* Physical Unclonable Function interrupt*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long EDMA_1_CH0_IRQHandler /* eDMA_1_CH0 error or transfer complete*/ + .long EDMA_1_CH1_IRQHandler /* eDMA_1_CH1 error or transfer complete*/ + .long EDMA_1_CH2_IRQHandler /* eDMA_1_CH2 error or transfer complete*/ + .long EDMA_1_CH3_IRQHandler /* eDMA_1_CH3 error or transfer complete*/ + .long EDMA_1_CH4_IRQHandler /* eDMA_1_CH4 error or transfer complete*/ + .long EDMA_1_CH5_IRQHandler /* eDMA_1_CH5 error or transfer complete*/ + .long EDMA_1_CH6_IRQHandler /* eDMA_1_CH6 error or transfer complete*/ + .long EDMA_1_CH7_IRQHandler /* eDMA_1_CH7 error or transfer complete*/ + .long Reserved101_IRQHandler /* Reserved interrupt*/ + .long Reserved102_IRQHandler /* Reserved interrupt*/ + .long Reserved103_IRQHandler /* Reserved interrupt*/ + .long Reserved104_IRQHandler /* Reserved interrupt*/ + .long Reserved105_IRQHandler /* Reserved interrupt*/ + .long Reserved106_IRQHandler /* Reserved interrupt*/ + .long Reserved107_IRQHandler /* Reserved interrupt*/ + .long Reserved108_IRQHandler /* Reserved interrupt*/ + .long CDOG0_IRQHandler /* Code Watchdog Timer 0 interrupt*/ + .long CDOG1_IRQHandler /* Code Watchdog Timer 1 interrupt*/ + .long I3C0_IRQHandler /* Improved Inter Integrated Circuit interrupt 0*/ + .long I3C1_IRQHandler /* Improved Inter Integrated Circuit interrupt 1*/ + .long Reserved113_IRQHandler /* Reserved interrupt*/ + .long GDET_IRQHandler /* Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt*/ + .long VBAT0_IRQHandler /* VBAT interrupt( VBAT interrupt or digital tamper interrupt)*/ + .long EWM0_IRQHandler /* External Watchdog Monitor interrupt*/ + .long Reserved117_IRQHandler /* Reserved interrupt*/ + .long Reserved118_IRQHandler /* Reserved interrupt*/ + .long Reserved119_IRQHandler /* Reserved interrupt*/ + .long Reserved120_IRQHandler /* Reserved interrupt*/ + .long FLEXIO_IRQHandler /* Flexible Input/Output interrupt*/ + .long Reserved122_IRQHandler /* Reserved interrupt*/ + .long Reserved123_IRQHandler /* Reserved interrupt*/ + .long Reserved124_IRQHandler /* Reserved interrupt*/ + .long HSCMP0_IRQHandler /* High-Speed comparator0 interrupt*/ + .long HSCMP1_IRQHandler /* High-Speed comparator1 interrupt*/ + .long Reserved127_IRQHandler /* Reserved interrupt*/ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* FlexPWM0_reload_error interrupt*/ + .long FLEXPWM0_FAULT_IRQHandler /* FlexPWM0_fault interrupt*/ + .long FLEXPWM0_SUBMODULE0_IRQHandler /* FlexPWM0 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE1_IRQHandler /* FlexPWM0 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE2_IRQHandler /* FlexPWM0 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE3_IRQHandler /* FlexPWM0 Submodule 3 capture/compare/reload interrupt*/ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* FlexPWM1_reload_error interrupt*/ + .long FLEXPWM1_FAULT_IRQHandler /* FlexPWM1_fault interrupt*/ + .long FLEXPWM1_SUBMODULE0_IRQHandler /* FlexPWM1 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ + .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ + .long Reserved149_IRQHandler /* Reserved interrupt*/ + .long ELS_ERR_IRQHandler /* ELS error interrupt*/ + .long PKC_ERR_IRQHandler /* PKC error interrupt*/ + .long ERM_SINGLE_BIT_ERROR_IRQHandler /* ERM Single Bit error interrupt*/ + .long ERM_MULTI_BIT_ERROR_IRQHandler /* ERM Multi Bit error interrupt*/ + .long FMU0_IRQHandler /* Flash Management Unit interrupt*/ + .long Reserved155_IRQHandler /* Reserved interrupt*/ + .long Reserved156_IRQHandler /* Reserved interrupt*/ + .long Reserved157_IRQHandler /* Reserved interrupt*/ + .long Reserved158_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* Low Power Timer 0 interrupt*/ + .long LPTMR1_IRQHandler /* Low Power Timer 1 interrupt*/ + .long SCG_IRQHandler /* System Clock Generator interrupt*/ + .long SPC_IRQHandler /* System Power Controller interrupt*/ + .long WUU_IRQHandler /* Wake Up Unit interrupt*/ + .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ + .long Reserved165_IRQHandler /* Reserved interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ + .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ + .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ + .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + + .size __Vectors, . - __Vectors + + .text + .thumb + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 + +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ +#ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else +#define __START _start +#endif +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak OR_IRQHandler + .type OR_IRQHandler, %function +OR_IRQHandler: + ldr r0,=OR_DriverIRQHandler + bx r0 + .size OR_IRQHandler, . - OR_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH0_IRQHandler + .type EDMA_0_CH0_IRQHandler, %function +EDMA_0_CH0_IRQHandler: + ldr r0,=EDMA_0_CH0_DriverIRQHandler + bx r0 + .size EDMA_0_CH0_IRQHandler, . - EDMA_0_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH1_IRQHandler + .type EDMA_0_CH1_IRQHandler, %function +EDMA_0_CH1_IRQHandler: + ldr r0,=EDMA_0_CH1_DriverIRQHandler + bx r0 + .size EDMA_0_CH1_IRQHandler, . - EDMA_0_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH2_IRQHandler + .type EDMA_0_CH2_IRQHandler, %function +EDMA_0_CH2_IRQHandler: + ldr r0,=EDMA_0_CH2_DriverIRQHandler + bx r0 + .size EDMA_0_CH2_IRQHandler, . - EDMA_0_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH3_IRQHandler + .type EDMA_0_CH3_IRQHandler, %function +EDMA_0_CH3_IRQHandler: + ldr r0,=EDMA_0_CH3_DriverIRQHandler + bx r0 + .size EDMA_0_CH3_IRQHandler, . - EDMA_0_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH4_IRQHandler + .type EDMA_0_CH4_IRQHandler, %function +EDMA_0_CH4_IRQHandler: + ldr r0,=EDMA_0_CH4_DriverIRQHandler + bx r0 + .size EDMA_0_CH4_IRQHandler, . - EDMA_0_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH5_IRQHandler + .type EDMA_0_CH5_IRQHandler, %function +EDMA_0_CH5_IRQHandler: + ldr r0,=EDMA_0_CH5_DriverIRQHandler + bx r0 + .size EDMA_0_CH5_IRQHandler, . - EDMA_0_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH6_IRQHandler + .type EDMA_0_CH6_IRQHandler, %function +EDMA_0_CH6_IRQHandler: + ldr r0,=EDMA_0_CH6_DriverIRQHandler + bx r0 + .size EDMA_0_CH6_IRQHandler, . - EDMA_0_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH7_IRQHandler + .type EDMA_0_CH7_IRQHandler, %function +EDMA_0_CH7_IRQHandler: + ldr r0,=EDMA_0_CH7_DriverIRQHandler + bx r0 + .size EDMA_0_CH7_IRQHandler, . - EDMA_0_CH7_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH8_IRQHandler + .type EDMA_0_CH8_IRQHandler, %function +EDMA_0_CH8_IRQHandler: + ldr r0,=EDMA_0_CH8_DriverIRQHandler + bx r0 + .size EDMA_0_CH8_IRQHandler, . - EDMA_0_CH8_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH9_IRQHandler + .type EDMA_0_CH9_IRQHandler, %function +EDMA_0_CH9_IRQHandler: + ldr r0,=EDMA_0_CH9_DriverIRQHandler + bx r0 + .size EDMA_0_CH9_IRQHandler, . - EDMA_0_CH9_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH10_IRQHandler + .type EDMA_0_CH10_IRQHandler, %function +EDMA_0_CH10_IRQHandler: + ldr r0,=EDMA_0_CH10_DriverIRQHandler + bx r0 + .size EDMA_0_CH10_IRQHandler, . - EDMA_0_CH10_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH11_IRQHandler + .type EDMA_0_CH11_IRQHandler, %function +EDMA_0_CH11_IRQHandler: + ldr r0,=EDMA_0_CH11_DriverIRQHandler + bx r0 + .size EDMA_0_CH11_IRQHandler, . - EDMA_0_CH11_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH12_IRQHandler + .type EDMA_0_CH12_IRQHandler, %function +EDMA_0_CH12_IRQHandler: + ldr r0,=EDMA_0_CH12_DriverIRQHandler + bx r0 + .size EDMA_0_CH12_IRQHandler, . - EDMA_0_CH12_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH13_IRQHandler + .type EDMA_0_CH13_IRQHandler, %function +EDMA_0_CH13_IRQHandler: + ldr r0,=EDMA_0_CH13_DriverIRQHandler + bx r0 + .size EDMA_0_CH13_IRQHandler, . - EDMA_0_CH13_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH14_IRQHandler + .type EDMA_0_CH14_IRQHandler, %function +EDMA_0_CH14_IRQHandler: + ldr r0,=EDMA_0_CH14_DriverIRQHandler + bx r0 + .size EDMA_0_CH14_IRQHandler, . - EDMA_0_CH14_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH15_IRQHandler + .type EDMA_0_CH15_IRQHandler, %function +EDMA_0_CH15_IRQHandler: + ldr r0,=EDMA_0_CH15_DriverIRQHandler + bx r0 + .size EDMA_0_CH15_IRQHandler, . - EDMA_0_CH15_IRQHandler + + .align 1 + .thumb_func + .weak GPIO00_IRQHandler + .type GPIO00_IRQHandler, %function +GPIO00_IRQHandler: + ldr r0,=GPIO00_DriverIRQHandler + bx r0 + .size GPIO00_IRQHandler, . - GPIO00_IRQHandler + + .align 1 + .thumb_func + .weak GPIO01_IRQHandler + .type GPIO01_IRQHandler, %function +GPIO01_IRQHandler: + ldr r0,=GPIO01_DriverIRQHandler + bx r0 + .size GPIO01_IRQHandler, . - GPIO01_IRQHandler + + .align 1 + .thumb_func + .weak GPIO10_IRQHandler + .type GPIO10_IRQHandler, %function +GPIO10_IRQHandler: + ldr r0,=GPIO10_DriverIRQHandler + bx r0 + .size GPIO10_IRQHandler, . - GPIO10_IRQHandler + + .align 1 + .thumb_func + .weak GPIO11_IRQHandler + .type GPIO11_IRQHandler, %function +GPIO11_IRQHandler: + ldr r0,=GPIO11_DriverIRQHandler + bx r0 + .size GPIO11_IRQHandler, . - GPIO11_IRQHandler + + .align 1 + .thumb_func + .weak GPIO20_IRQHandler + .type GPIO20_IRQHandler, %function +GPIO20_IRQHandler: + ldr r0,=GPIO20_DriverIRQHandler + bx r0 + .size GPIO20_IRQHandler, . - GPIO20_IRQHandler + + .align 1 + .thumb_func + .weak GPIO21_IRQHandler + .type GPIO21_IRQHandler, %function +GPIO21_IRQHandler: + ldr r0,=GPIO21_DriverIRQHandler + bx r0 + .size GPIO21_IRQHandler, . - GPIO21_IRQHandler + + .align 1 + .thumb_func + .weak GPIO30_IRQHandler + .type GPIO30_IRQHandler, %function +GPIO30_IRQHandler: + ldr r0,=GPIO30_DriverIRQHandler + bx r0 + .size GPIO30_IRQHandler, . - GPIO30_IRQHandler + + .align 1 + .thumb_func + .weak GPIO31_IRQHandler + .type GPIO31_IRQHandler, %function +GPIO31_IRQHandler: + ldr r0,=GPIO31_DriverIRQHandler + bx r0 + .size GPIO31_IRQHandler, . - GPIO31_IRQHandler + + .align 1 + .thumb_func + .weak GPIO40_IRQHandler + .type GPIO40_IRQHandler, %function +GPIO40_IRQHandler: + ldr r0,=GPIO40_DriverIRQHandler + bx r0 + .size GPIO40_IRQHandler, . - GPIO40_IRQHandler + + .align 1 + .thumb_func + .weak GPIO41_IRQHandler + .type GPIO41_IRQHandler, %function +GPIO41_IRQHandler: + ldr r0,=GPIO41_DriverIRQHandler + bx r0 + .size GPIO41_IRQHandler, . - GPIO41_IRQHandler + + .align 1 + .thumb_func + .weak GPIO50_IRQHandler + .type GPIO50_IRQHandler, %function +GPIO50_IRQHandler: + ldr r0,=GPIO50_DriverIRQHandler + bx r0 + .size GPIO50_IRQHandler, . - GPIO50_IRQHandler + + .align 1 + .thumb_func + .weak GPIO51_IRQHandler + .type GPIO51_IRQHandler, %function +GPIO51_IRQHandler: + ldr r0,=GPIO51_DriverIRQHandler + bx r0 + .size GPIO51_IRQHandler, . - GPIO51_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved49_IRQHandler + .type Reserved49_IRQHandler, %function +Reserved49_IRQHandler: + ldr r0,=Reserved49_DriverIRQHandler + bx r0 + .size Reserved49_IRQHandler, . - Reserved49_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM0_IRQHandler + .type LP_FLEXCOMM0_IRQHandler, %function +LP_FLEXCOMM0_IRQHandler: + ldr r0,=LP_FLEXCOMM0_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM0_IRQHandler, . - LP_FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM1_IRQHandler + .type LP_FLEXCOMM1_IRQHandler, %function +LP_FLEXCOMM1_IRQHandler: + ldr r0,=LP_FLEXCOMM1_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM1_IRQHandler, . - LP_FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM2_IRQHandler + .type LP_FLEXCOMM2_IRQHandler, %function +LP_FLEXCOMM2_IRQHandler: + ldr r0,=LP_FLEXCOMM2_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM2_IRQHandler, . - LP_FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM3_IRQHandler + .type LP_FLEXCOMM3_IRQHandler, %function +LP_FLEXCOMM3_IRQHandler: + ldr r0,=LP_FLEXCOMM3_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM3_IRQHandler, . - LP_FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM4_IRQHandler + .type LP_FLEXCOMM4_IRQHandler, %function +LP_FLEXCOMM4_IRQHandler: + ldr r0,=LP_FLEXCOMM4_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM4_IRQHandler, . - LP_FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM5_IRQHandler + .type LP_FLEXCOMM5_IRQHandler, %function +LP_FLEXCOMM5_IRQHandler: + ldr r0,=LP_FLEXCOMM5_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM5_IRQHandler, . - LP_FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM6_IRQHandler + .type LP_FLEXCOMM6_IRQHandler, %function +LP_FLEXCOMM6_IRQHandler: + ldr r0,=LP_FLEXCOMM6_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM6_IRQHandler, . - LP_FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM7_IRQHandler + .type LP_FLEXCOMM7_IRQHandler, %function +LP_FLEXCOMM7_IRQHandler: + ldr r0,=LP_FLEXCOMM7_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM7_IRQHandler, . - LP_FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak PINT0_IRQHandler + .type PINT0_IRQHandler, %function +PINT0_IRQHandler: + ldr r0,=PINT0_DriverIRQHandler + bx r0 + .size PINT0_IRQHandler, . - PINT0_IRQHandler + + .align 1 + .thumb_func + .weak PDM_EVENT_IRQHandler + .type PDM_EVENT_IRQHandler, %function +PDM_EVENT_IRQHandler: + ldr r0,=PDM_EVENT_DriverIRQHandler + bx r0 + .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved65_IRQHandler + .type Reserved65_IRQHandler, %function +Reserved65_IRQHandler: + ldr r0,=Reserved65_DriverIRQHandler + bx r0 + .size Reserved65_IRQHandler, . - Reserved65_IRQHandler + + .align 1 + .thumb_func + .weak Reserved66_IRQHandler + .type Reserved66_IRQHandler, %function +Reserved66_IRQHandler: + ldr r0,=Reserved66_DriverIRQHandler + bx r0 + .size Reserved66_IRQHandler, . - Reserved66_IRQHandler + + .align 1 + .thumb_func + .weak USB0_DCD_IRQHandler + .type USB0_DCD_IRQHandler, %function +USB0_DCD_IRQHandler: + ldr r0,=USB0_DCD_DriverIRQHandler + bx r0 + .size USB0_DCD_IRQHandler, . - USB0_DCD_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak SMARTDMA_IRQHandler + .type SMARTDMA_IRQHandler, %function +SMARTDMA_IRQHandler: + ldr r0,=SMARTDMA_DriverIRQHandler + bx r0 + .size SMARTDMA_IRQHandler, . - SMARTDMA_IRQHandler + + .align 1 + .thumb_func + .weak Reserved70_IRQHandler + .type Reserved70_IRQHandler, %function +Reserved70_IRQHandler: + ldr r0,=Reserved70_DriverIRQHandler + bx r0 + .size Reserved70_IRQHandler, . - Reserved70_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved74_IRQHandler + .type Reserved74_IRQHandler, %function +Reserved74_IRQHandler: + ldr r0,=Reserved74_DriverIRQHandler + bx r0 + .size Reserved74_IRQHandler, . - Reserved74_IRQHandler + + .align 1 + .thumb_func + .weak SAI0_IRQHandler + .type SAI0_IRQHandler, %function +SAI0_IRQHandler: + ldr r0,=SAI0_DriverIRQHandler + bx r0 + .size SAI0_IRQHandler, . - SAI0_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQHandler + .type CAN0_IRQHandler, %function +CAN0_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_IRQHandler, . - CAN0_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQHandler + .type CAN1_IRQHandler, %function +CAN1_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_IRQHandler, . - CAN1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak Reserved81_IRQHandler + .type Reserved81_IRQHandler, %function +Reserved81_IRQHandler: + ldr r0,=Reserved81_DriverIRQHandler + bx r0 + .size Reserved81_IRQHandler, . - Reserved81_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_PHY_IRQHandler + .type USB1_HS_PHY_IRQHandler, %function +USB1_HS_PHY_IRQHandler: + ldr r0,=USB1_HS_PHY_DriverIRQHandler + bx r0 + .size USB1_HS_PHY_IRQHandler, . - USB1_HS_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_IRQHandler + .type USB1_HS_IRQHandler, %function +USB1_HS_IRQHandler: + ldr r0,=USB1_HS_DriverIRQHandler + bx r0 + .size USB1_HS_IRQHandler, . - USB1_HS_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak ELS_IRQHandler + .type ELS_IRQHandler, %function +ELS_IRQHandler: + ldr r0,=ELS_DriverIRQHandler + bx r0 + .size ELS_IRQHandler, . - ELS_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved92_IRQHandler + .type Reserved92_IRQHandler, %function +Reserved92_IRQHandler: + ldr r0,=Reserved92_DriverIRQHandler + bx r0 + .size Reserved92_IRQHandler, . - Reserved92_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH0_IRQHandler + .type EDMA_1_CH0_IRQHandler, %function +EDMA_1_CH0_IRQHandler: + ldr r0,=EDMA_1_CH0_DriverIRQHandler + bx r0 + .size EDMA_1_CH0_IRQHandler, . - EDMA_1_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH1_IRQHandler + .type EDMA_1_CH1_IRQHandler, %function +EDMA_1_CH1_IRQHandler: + ldr r0,=EDMA_1_CH1_DriverIRQHandler + bx r0 + .size EDMA_1_CH1_IRQHandler, . - EDMA_1_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH2_IRQHandler + .type EDMA_1_CH2_IRQHandler, %function +EDMA_1_CH2_IRQHandler: + ldr r0,=EDMA_1_CH2_DriverIRQHandler + bx r0 + .size EDMA_1_CH2_IRQHandler, . - EDMA_1_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH3_IRQHandler + .type EDMA_1_CH3_IRQHandler, %function +EDMA_1_CH3_IRQHandler: + ldr r0,=EDMA_1_CH3_DriverIRQHandler + bx r0 + .size EDMA_1_CH3_IRQHandler, . - EDMA_1_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH4_IRQHandler + .type EDMA_1_CH4_IRQHandler, %function +EDMA_1_CH4_IRQHandler: + ldr r0,=EDMA_1_CH4_DriverIRQHandler + bx r0 + .size EDMA_1_CH4_IRQHandler, . - EDMA_1_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH5_IRQHandler + .type EDMA_1_CH5_IRQHandler, %function +EDMA_1_CH5_IRQHandler: + ldr r0,=EDMA_1_CH5_DriverIRQHandler + bx r0 + .size EDMA_1_CH5_IRQHandler, . - EDMA_1_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH6_IRQHandler + .type EDMA_1_CH6_IRQHandler, %function +EDMA_1_CH6_IRQHandler: + ldr r0,=EDMA_1_CH6_DriverIRQHandler + bx r0 + .size EDMA_1_CH6_IRQHandler, . - EDMA_1_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH7_IRQHandler + .type EDMA_1_CH7_IRQHandler, %function +EDMA_1_CH7_IRQHandler: + ldr r0,=EDMA_1_CH7_DriverIRQHandler + bx r0 + .size EDMA_1_CH7_IRQHandler, . - EDMA_1_CH7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved101_IRQHandler + .type Reserved101_IRQHandler, %function +Reserved101_IRQHandler: + ldr r0,=Reserved101_DriverIRQHandler + bx r0 + .size Reserved101_IRQHandler, . - Reserved101_IRQHandler + + .align 1 + .thumb_func + .weak Reserved102_IRQHandler + .type Reserved102_IRQHandler, %function +Reserved102_IRQHandler: + ldr r0,=Reserved102_DriverIRQHandler + bx r0 + .size Reserved102_IRQHandler, . - Reserved102_IRQHandler + + .align 1 + .thumb_func + .weak Reserved103_IRQHandler + .type Reserved103_IRQHandler, %function +Reserved103_IRQHandler: + ldr r0,=Reserved103_DriverIRQHandler + bx r0 + .size Reserved103_IRQHandler, . - Reserved103_IRQHandler + + .align 1 + .thumb_func + .weak Reserved104_IRQHandler + .type Reserved104_IRQHandler, %function +Reserved104_IRQHandler: + ldr r0,=Reserved104_DriverIRQHandler + bx r0 + .size Reserved104_IRQHandler, . - Reserved104_IRQHandler + + .align 1 + .thumb_func + .weak Reserved105_IRQHandler + .type Reserved105_IRQHandler, %function +Reserved105_IRQHandler: + ldr r0,=Reserved105_DriverIRQHandler + bx r0 + .size Reserved105_IRQHandler, . - Reserved105_IRQHandler + + .align 1 + .thumb_func + .weak Reserved106_IRQHandler + .type Reserved106_IRQHandler, %function +Reserved106_IRQHandler: + ldr r0,=Reserved106_DriverIRQHandler + bx r0 + .size Reserved106_IRQHandler, . - Reserved106_IRQHandler + + .align 1 + .thumb_func + .weak Reserved107_IRQHandler + .type Reserved107_IRQHandler, %function +Reserved107_IRQHandler: + ldr r0,=Reserved107_DriverIRQHandler + bx r0 + .size Reserved107_IRQHandler, . - Reserved107_IRQHandler + + .align 1 + .thumb_func + .weak Reserved108_IRQHandler + .type Reserved108_IRQHandler, %function +Reserved108_IRQHandler: + ldr r0,=Reserved108_DriverIRQHandler + bx r0 + .size Reserved108_IRQHandler, . - Reserved108_IRQHandler + + .align 1 + .thumb_func + .weak CDOG0_IRQHandler + .type CDOG0_IRQHandler, %function +CDOG0_IRQHandler: + ldr r0,=CDOG0_DriverIRQHandler + bx r0 + .size CDOG0_IRQHandler, . - CDOG0_IRQHandler + + .align 1 + .thumb_func + .weak CDOG1_IRQHandler + .type CDOG1_IRQHandler, %function +CDOG1_IRQHandler: + ldr r0,=CDOG1_DriverIRQHandler + bx r0 + .size CDOG1_IRQHandler, . - CDOG1_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak I3C1_IRQHandler + .type I3C1_IRQHandler, %function +I3C1_IRQHandler: + ldr r0,=I3C1_DriverIRQHandler + bx r0 + .size I3C1_IRQHandler, . - I3C1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved113_IRQHandler + .type Reserved113_IRQHandler, %function +Reserved113_IRQHandler: + ldr r0,=Reserved113_DriverIRQHandler + bx r0 + .size Reserved113_IRQHandler, . - Reserved113_IRQHandler + + .align 1 + .thumb_func + .weak GDET_IRQHandler + .type GDET_IRQHandler, %function +GDET_IRQHandler: + ldr r0,=GDET_DriverIRQHandler + bx r0 + .size GDET_IRQHandler, . - GDET_IRQHandler + + .align 1 + .thumb_func + .weak VBAT0_IRQHandler + .type VBAT0_IRQHandler, %function +VBAT0_IRQHandler: + ldr r0,=VBAT0_DriverIRQHandler + bx r0 + .size VBAT0_IRQHandler, . - VBAT0_IRQHandler + + .align 1 + .thumb_func + .weak EWM0_IRQHandler + .type EWM0_IRQHandler, %function +EWM0_IRQHandler: + ldr r0,=EWM0_DriverIRQHandler + bx r0 + .size EWM0_IRQHandler, . - EWM0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved117_IRQHandler + .type Reserved117_IRQHandler, %function +Reserved117_IRQHandler: + ldr r0,=Reserved117_DriverIRQHandler + bx r0 + .size Reserved117_IRQHandler, . - Reserved117_IRQHandler + + .align 1 + .thumb_func + .weak Reserved118_IRQHandler + .type Reserved118_IRQHandler, %function +Reserved118_IRQHandler: + ldr r0,=Reserved118_DriverIRQHandler + bx r0 + .size Reserved118_IRQHandler, . - Reserved118_IRQHandler + + .align 1 + .thumb_func + .weak Reserved119_IRQHandler + .type Reserved119_IRQHandler, %function +Reserved119_IRQHandler: + ldr r0,=Reserved119_DriverIRQHandler + bx r0 + .size Reserved119_IRQHandler, . - Reserved119_IRQHandler + + .align 1 + .thumb_func + .weak Reserved120_IRQHandler + .type Reserved120_IRQHandler, %function +Reserved120_IRQHandler: + ldr r0,=Reserved120_DriverIRQHandler + bx r0 + .size Reserved120_IRQHandler, . - Reserved120_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO_IRQHandler + .type FLEXIO_IRQHandler, %function +FLEXIO_IRQHandler: + ldr r0,=FLEXIO_DriverIRQHandler + bx r0 + .size FLEXIO_IRQHandler, . - FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved122_IRQHandler + .type Reserved122_IRQHandler, %function +Reserved122_IRQHandler: + ldr r0,=Reserved122_DriverIRQHandler + bx r0 + .size Reserved122_IRQHandler, . - Reserved122_IRQHandler + + .align 1 + .thumb_func + .weak Reserved123_IRQHandler + .type Reserved123_IRQHandler, %function +Reserved123_IRQHandler: + ldr r0,=Reserved123_DriverIRQHandler + bx r0 + .size Reserved123_IRQHandler, . - Reserved123_IRQHandler + + .align 1 + .thumb_func + .weak Reserved124_IRQHandler + .type Reserved124_IRQHandler, %function +Reserved124_IRQHandler: + ldr r0,=Reserved124_DriverIRQHandler + bx r0 + .size Reserved124_IRQHandler, . - Reserved124_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE0_IRQHandler + .type FLEXPWM0_SUBMODULE0_IRQHandler, %function +FLEXPWM0_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE0_IRQHandler, . - FLEXPWM0_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE1_IRQHandler + .type FLEXPWM0_SUBMODULE1_IRQHandler, %function +FLEXPWM0_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE1_IRQHandler, . - FLEXPWM0_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE2_IRQHandler + .type FLEXPWM0_SUBMODULE2_IRQHandler, %function +FLEXPWM0_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE2_IRQHandler, . - FLEXPWM0_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE3_IRQHandler + .type FLEXPWM0_SUBMODULE3_IRQHandler, %function +FLEXPWM0_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE3_IRQHandler, . - FLEXPWM0_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE0_IRQHandler + .type FLEXPWM1_SUBMODULE0_IRQHandler, %function +FLEXPWM1_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE0_IRQHandler, . - FLEXPWM1_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE1_IRQHandler + .type FLEXPWM1_SUBMODULE1_IRQHandler, %function +FLEXPWM1_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE1_IRQHandler, . - FLEXPWM1_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE2_IRQHandler + .type FLEXPWM1_SUBMODULE2_IRQHandler, %function +FLEXPWM1_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE2_IRQHandler, . - FLEXPWM1_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE3_IRQHandler + .type FLEXPWM1_SUBMODULE3_IRQHandler, %function +FLEXPWM1_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE3_IRQHandler, . - FLEXPWM1_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler + bx r0 + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler + bx r0 + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler + bx r0 + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler + bx r0 + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler + bx r0 + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler + bx r0 + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved149_IRQHandler + .type Reserved149_IRQHandler, %function +Reserved149_IRQHandler: + ldr r0,=Reserved149_DriverIRQHandler + bx r0 + .size Reserved149_IRQHandler, . - Reserved149_IRQHandler + + .align 1 + .thumb_func + .weak ELS_ERR_IRQHandler + .type ELS_ERR_IRQHandler, %function +ELS_ERR_IRQHandler: + ldr r0,=ELS_ERR_DriverIRQHandler + bx r0 + .size ELS_ERR_IRQHandler, . - ELS_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_SINGLE_BIT_ERROR_IRQHandler + .type ERM_SINGLE_BIT_ERROR_IRQHandler, %function +ERM_SINGLE_BIT_ERROR_IRQHandler: + ldr r0,=ERM_SINGLE_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_SINGLE_BIT_ERROR_IRQHandler, . - ERM_SINGLE_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_MULTI_BIT_ERROR_IRQHandler + .type ERM_MULTI_BIT_ERROR_IRQHandler, %function +ERM_MULTI_BIT_ERROR_IRQHandler: + ldr r0,=ERM_MULTI_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_MULTI_BIT_ERROR_IRQHandler, . - ERM_MULTI_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FMU0_IRQHandler + .type FMU0_IRQHandler, %function +FMU0_IRQHandler: + ldr r0,=FMU0_DriverIRQHandler + bx r0 + .size FMU0_IRQHandler, . - FMU0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved155_IRQHandler + .type Reserved155_IRQHandler, %function +Reserved155_IRQHandler: + ldr r0,=Reserved155_DriverIRQHandler + bx r0 + .size Reserved155_IRQHandler, . - Reserved155_IRQHandler + + .align 1 + .thumb_func + .weak Reserved156_IRQHandler + .type Reserved156_IRQHandler, %function +Reserved156_IRQHandler: + ldr r0,=Reserved156_DriverIRQHandler + bx r0 + .size Reserved156_IRQHandler, . - Reserved156_IRQHandler + + .align 1 + .thumb_func + .weak Reserved157_IRQHandler + .type Reserved157_IRQHandler, %function +Reserved157_IRQHandler: + ldr r0,=Reserved157_DriverIRQHandler + bx r0 + .size Reserved157_IRQHandler, . - Reserved157_IRQHandler + + .align 1 + .thumb_func + .weak Reserved158_IRQHandler + .type Reserved158_IRQHandler, %function +Reserved158_IRQHandler: + ldr r0,=Reserved158_DriverIRQHandler + bx r0 + .size Reserved158_IRQHandler, . - Reserved158_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR0_IRQHandler + .type LPTMR0_IRQHandler, %function +LPTMR0_IRQHandler: + ldr r0,=LPTMR0_DriverIRQHandler + bx r0 + .size LPTMR0_IRQHandler, . - LPTMR0_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR1_IRQHandler + .type LPTMR1_IRQHandler, %function +LPTMR1_IRQHandler: + ldr r0,=LPTMR1_DriverIRQHandler + bx r0 + .size LPTMR1_IRQHandler, . - LPTMR1_IRQHandler + + .align 1 + .thumb_func + .weak SCG_IRQHandler + .type SCG_IRQHandler, %function +SCG_IRQHandler: + ldr r0,=SCG_DriverIRQHandler + bx r0 + .size SCG_IRQHandler, . - SCG_IRQHandler + + .align 1 + .thumb_func + .weak SPC_IRQHandler + .type SPC_IRQHandler, %function +SPC_IRQHandler: + ldr r0,=SPC_DriverIRQHandler + bx r0 + .size SPC_IRQHandler, . - SPC_IRQHandler + + .align 1 + .thumb_func + .weak WUU_IRQHandler + .type WUU_IRQHandler, %function +WUU_IRQHandler: + ldr r0,=WUU_DriverIRQHandler + bx r0 + .size WUU_IRQHandler, . - WUU_IRQHandler + + .align 1 + .thumb_func + .weak PORT_EFT_IRQHandler + .type PORT_EFT_IRQHandler, %function +PORT_EFT_IRQHandler: + ldr r0,=PORT_EFT_DriverIRQHandler + bx r0 + .size PORT_EFT_IRQHandler, . - PORT_EFT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved165_IRQHandler + .type Reserved165_IRQHandler, %function +Reserved165_IRQHandler: + ldr r0,=Reserved165_DriverIRQHandler + bx r0 + .size Reserved165_IRQHandler, . - Reserved165_IRQHandler + + .align 1 + .thumb_func + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler + bx r0 + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler + + .align 1 + .thumb_func + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler + bx r0 + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler + + .align 1 + .thumb_func + .weak WWDT0_IRQHandler + .type WWDT0_IRQHandler, %function +WWDT0_IRQHandler: + ldr r0,=WWDT0_DriverIRQHandler + bx r0 + .size WWDT0_IRQHandler, . - WWDT0_IRQHandler + + .align 1 + .thumb_func + .weak WWDT1_IRQHandler + .type WWDT1_IRQHandler, %function +WWDT1_IRQHandler: + ldr r0,=WWDT1_DriverIRQHandler + bx r0 + .size WWDT1_IRQHandler, . - WWDT1_IRQHandler + + .align 1 + .thumb_func + .weak CMC0_IRQHandler + .type CMC0_IRQHandler, %function +CMC0_IRQHandler: + ldr r0,=CMC0_DriverIRQHandler + bx r0 + .size CMC0_IRQHandler, . - CMC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved171_IRQHandler + .type Reserved171_IRQHandler, %function +Reserved171_IRQHandler: + ldr r0,=Reserved171_DriverIRQHandler + bx r0 + .size Reserved171_IRQHandler, . - Reserved171_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler OR_DriverIRQHandler + def_irq_handler EDMA_0_CH0_DriverIRQHandler + def_irq_handler EDMA_0_CH1_DriverIRQHandler + def_irq_handler EDMA_0_CH2_DriverIRQHandler + def_irq_handler EDMA_0_CH3_DriverIRQHandler + def_irq_handler EDMA_0_CH4_DriverIRQHandler + def_irq_handler EDMA_0_CH5_DriverIRQHandler + def_irq_handler EDMA_0_CH6_DriverIRQHandler + def_irq_handler EDMA_0_CH7_DriverIRQHandler + def_irq_handler EDMA_0_CH8_DriverIRQHandler + def_irq_handler EDMA_0_CH9_DriverIRQHandler + def_irq_handler EDMA_0_CH10_DriverIRQHandler + def_irq_handler EDMA_0_CH11_DriverIRQHandler + def_irq_handler EDMA_0_CH12_DriverIRQHandler + def_irq_handler EDMA_0_CH13_DriverIRQHandler + def_irq_handler EDMA_0_CH14_DriverIRQHandler + def_irq_handler EDMA_0_CH15_DriverIRQHandler + def_irq_handler GPIO00_DriverIRQHandler + def_irq_handler GPIO01_DriverIRQHandler + def_irq_handler GPIO10_DriverIRQHandler + def_irq_handler GPIO11_DriverIRQHandler + def_irq_handler GPIO20_DriverIRQHandler + def_irq_handler GPIO21_DriverIRQHandler + def_irq_handler GPIO30_DriverIRQHandler + def_irq_handler GPIO31_DriverIRQHandler + def_irq_handler GPIO40_DriverIRQHandler + def_irq_handler GPIO41_DriverIRQHandler + def_irq_handler GPIO50_DriverIRQHandler + def_irq_handler GPIO51_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler Reserved49_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM0_DriverIRQHandler + def_irq_handler LP_FLEXCOMM1_DriverIRQHandler + def_irq_handler LP_FLEXCOMM2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM3_DriverIRQHandler + def_irq_handler LP_FLEXCOMM4_DriverIRQHandler + def_irq_handler LP_FLEXCOMM5_DriverIRQHandler + def_irq_handler LP_FLEXCOMM6_DriverIRQHandler + def_irq_handler LP_FLEXCOMM7_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler PINT0_DriverIRQHandler + def_irq_handler PDM_EVENT_DriverIRQHandler + def_irq_handler Reserved65_DriverIRQHandler + def_irq_handler Reserved66_DriverIRQHandler + def_irq_handler USB0_DCD_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler SMARTDMA_DriverIRQHandler + def_irq_handler Reserved70_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved74_DriverIRQHandler + def_irq_handler SAI0_DriverIRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler Reserved80_DriverIRQHandler + def_irq_handler Reserved81_DriverIRQHandler + def_irq_handler USB1_HS_PHY_DriverIRQHandler + def_irq_handler USB1_HS_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler Freqme_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler ELS_DriverIRQHandler + def_irq_handler PKC_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler Reserved92_DriverIRQHandler + def_irq_handler EDMA_1_CH0_DriverIRQHandler + def_irq_handler EDMA_1_CH1_DriverIRQHandler + def_irq_handler EDMA_1_CH2_DriverIRQHandler + def_irq_handler EDMA_1_CH3_DriverIRQHandler + def_irq_handler EDMA_1_CH4_DriverIRQHandler + def_irq_handler EDMA_1_CH5_DriverIRQHandler + def_irq_handler EDMA_1_CH6_DriverIRQHandler + def_irq_handler EDMA_1_CH7_DriverIRQHandler + def_irq_handler Reserved101_DriverIRQHandler + def_irq_handler Reserved102_DriverIRQHandler + def_irq_handler Reserved103_DriverIRQHandler + def_irq_handler Reserved104_DriverIRQHandler + def_irq_handler Reserved105_DriverIRQHandler + def_irq_handler Reserved106_DriverIRQHandler + def_irq_handler Reserved107_DriverIRQHandler + def_irq_handler Reserved108_DriverIRQHandler + def_irq_handler CDOG0_DriverIRQHandler + def_irq_handler CDOG1_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler I3C1_DriverIRQHandler + def_irq_handler Reserved113_DriverIRQHandler + def_irq_handler GDET_DriverIRQHandler + def_irq_handler VBAT0_DriverIRQHandler + def_irq_handler EWM0_DriverIRQHandler + def_irq_handler Reserved117_DriverIRQHandler + def_irq_handler Reserved118_DriverIRQHandler + def_irq_handler Reserved119_DriverIRQHandler + def_irq_handler Reserved120_DriverIRQHandler + def_irq_handler FLEXIO_DriverIRQHandler + def_irq_handler Reserved122_DriverIRQHandler + def_irq_handler Reserved123_DriverIRQHandler + def_irq_handler Reserved124_DriverIRQHandler + def_irq_handler HSCMP0_DriverIRQHandler + def_irq_handler HSCMP1_DriverIRQHandler + def_irq_handler Reserved127_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE3_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler + def_irq_handler ITRC0_DriverIRQHandler + def_irq_handler Reserved149_DriverIRQHandler + def_irq_handler ELS_ERR_DriverIRQHandler + def_irq_handler PKC_ERR_DriverIRQHandler + def_irq_handler ERM_SINGLE_BIT_ERROR_DriverIRQHandler + def_irq_handler ERM_MULTI_BIT_ERROR_DriverIRQHandler + def_irq_handler FMU0_DriverIRQHandler + def_irq_handler Reserved155_DriverIRQHandler + def_irq_handler Reserved156_DriverIRQHandler + def_irq_handler Reserved157_DriverIRQHandler + def_irq_handler Reserved158_DriverIRQHandler + def_irq_handler LPTMR0_DriverIRQHandler + def_irq_handler LPTMR1_DriverIRQHandler + def_irq_handler SCG_DriverIRQHandler + def_irq_handler SPC_DriverIRQHandler + def_irq_handler WUU_DriverIRQHandler + def_irq_handler PORT_EFT_DriverIRQHandler + def_irq_handler Reserved165_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler + def_irq_handler WWDT0_DriverIRQHandler + def_irq_handler WWDT1_DriverIRQHandler + def_irq_handler CMC0_DriverIRQHandler + def_irq_handler Reserved171_DriverIRQHandler + + .end diff --git a/devices/MCXN236/mcuxpresso/startup_mcxn236.c b/devices/MCXN236/mcuxpresso/startup_mcxn236.c new file mode 100644 index 000000000..35873bb15 --- /dev/null +++ b/devices/MCXN236/mcuxpresso/startup_mcxn236.c @@ -0,0 +1,1409 @@ +//***************************************************************************** +// MCXN236 startup code for use with MCUXpresso IDE +// +// Version : 090424 +//***************************************************************************** +// +// Copyright 2016-2024 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void OR_IRQHandler(void); +WEAK void EDMA_0_CH0_IRQHandler(void); +WEAK void EDMA_0_CH1_IRQHandler(void); +WEAK void EDMA_0_CH2_IRQHandler(void); +WEAK void EDMA_0_CH3_IRQHandler(void); +WEAK void EDMA_0_CH4_IRQHandler(void); +WEAK void EDMA_0_CH5_IRQHandler(void); +WEAK void EDMA_0_CH6_IRQHandler(void); +WEAK void EDMA_0_CH7_IRQHandler(void); +WEAK void EDMA_0_CH8_IRQHandler(void); +WEAK void EDMA_0_CH9_IRQHandler(void); +WEAK void EDMA_0_CH10_IRQHandler(void); +WEAK void EDMA_0_CH11_IRQHandler(void); +WEAK void EDMA_0_CH12_IRQHandler(void); +WEAK void EDMA_0_CH13_IRQHandler(void); +WEAK void EDMA_0_CH14_IRQHandler(void); +WEAK void EDMA_0_CH15_IRQHandler(void); +WEAK void GPIO00_IRQHandler(void); +WEAK void GPIO01_IRQHandler(void); +WEAK void GPIO10_IRQHandler(void); +WEAK void GPIO11_IRQHandler(void); +WEAK void GPIO20_IRQHandler(void); +WEAK void GPIO21_IRQHandler(void); +WEAK void GPIO30_IRQHandler(void); +WEAK void GPIO31_IRQHandler(void); +WEAK void GPIO40_IRQHandler(void); +WEAK void GPIO41_IRQHandler(void); +WEAK void GPIO50_IRQHandler(void); +WEAK void GPIO51_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void Reserved49_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void LP_FLEXCOMM0_IRQHandler(void); +WEAK void LP_FLEXCOMM1_IRQHandler(void); +WEAK void LP_FLEXCOMM2_IRQHandler(void); +WEAK void LP_FLEXCOMM3_IRQHandler(void); +WEAK void LP_FLEXCOMM4_IRQHandler(void); +WEAK void LP_FLEXCOMM5_IRQHandler(void); +WEAK void LP_FLEXCOMM6_IRQHandler(void); +WEAK void LP_FLEXCOMM7_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void PINT0_IRQHandler(void); +WEAK void PDM_EVENT_IRQHandler(void); +WEAK void Reserved65_IRQHandler(void); +WEAK void Reserved66_IRQHandler(void); +WEAK void USB0_DCD_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved70_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved74_IRQHandler(void); +WEAK void SAI0_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved80_IRQHandler(void); +WEAK void Reserved81_IRQHandler(void); +WEAK void USB1_HS_PHY_IRQHandler(void); +WEAK void USB1_HS_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Freqme_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void ELS_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void EDMA_1_CH0_IRQHandler(void); +WEAK void EDMA_1_CH1_IRQHandler(void); +WEAK void EDMA_1_CH2_IRQHandler(void); +WEAK void EDMA_1_CH3_IRQHandler(void); +WEAK void EDMA_1_CH4_IRQHandler(void); +WEAK void EDMA_1_CH5_IRQHandler(void); +WEAK void EDMA_1_CH6_IRQHandler(void); +WEAK void EDMA_1_CH7_IRQHandler(void); +WEAK void Reserved101_IRQHandler(void); +WEAK void Reserved102_IRQHandler(void); +WEAK void Reserved103_IRQHandler(void); +WEAK void Reserved104_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void I3C1_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void GDET_IRQHandler(void); +WEAK void VBAT0_IRQHandler(void); +WEAK void EWM0_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void Reserved124_IRQHandler(void); +WEAK void HSCMP0_IRQHandler(void); +WEAK void HSCMP1_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void QDC0_COMPARE_IRQHandler(void); +WEAK void QDC0_HOME_IRQHandler(void); +WEAK void QDC0_WDG_SAB_IRQHandler(void); +WEAK void QDC0_IDX_IRQHandler(void); +WEAK void QDC1_COMPARE_IRQHandler(void); +WEAK void QDC1_HOME_IRQHandler(void); +WEAK void QDC1_WDG_SAB_IRQHandler(void); +WEAK void QDC1_IDX_IRQHandler(void); +WEAK void ITRC0_IRQHandler(void); +WEAK void Reserved149_IRQHandler(void); +WEAK void ELS_ERR_IRQHandler(void); +WEAK void PKC_ERR_IRQHandler(void); +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void); +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void Reserved155_IRQHandler(void); +WEAK void Reserved156_IRQHandler(void); +WEAK void Reserved157_IRQHandler(void); +WEAK void Reserved158_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void LPTMR1_IRQHandler(void); +WEAK void SCG_IRQHandler(void); +WEAK void SPC_IRQHandler(void); +WEAK void WUU_IRQHandler(void); +WEAK void PORT_EFT_IRQHandler(void); +WEAK void Reserved165_IRQHandler(void); +WEAK void Reserved166_IRQHandler(void); +WEAK void Reserved167_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void WWDT1_IRQHandler(void); +WEAK void CMC0_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void OR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH12_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH13_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH14_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO00_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO01_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO40_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO50_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO51_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved49_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PDM_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SMARTDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved77_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved80_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved81_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved85_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Freqme_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved92_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved101_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved102_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved103_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved104_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved105_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved106_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved107_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved108_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved113_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GDET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void VBAT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved117_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved118_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved119_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved120_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved122_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved124_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved127_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ITRC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved149_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_SINGLE_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_MULTI_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FMU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved155_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved156_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved157_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved158_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WUU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PORT_EFT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved165_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved166_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved167_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +extern void _vStackBase(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** + +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXN236 + OR_IRQHandler, // 16 : OR IRQ + EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete + EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete + EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete + EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete + EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete + EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete + EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete + EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete + EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete + EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete + EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete + EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete + EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete + EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete + EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete + EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete + GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 + GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 + GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 + GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 + GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 + GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 + GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 + GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 + GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 + GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 + GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 + GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 + UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt + MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt + CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt + Reserved49_IRQHandler, // 49 : Reserved interrupt + CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt + LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose interrupt + ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose interrupt + PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt + PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt + Reserved65_IRQHandler, // 65 : Reserved interrupt + Reserved66_IRQHandler, // 66 : Reserved interrupt + USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect interrupt + RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) + SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ + Reserved70_IRQHandler, // 70 : Reserved interrupt + CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + Reserved74_IRQHandler, // 74 : Reserved interrupt + SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt + SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 79 : Controller Area Network 1 interrupt + Reserved80_IRQHandler, // 80 : Reserved interrupt + Reserved81_IRQHandler, // 81 : Reserved interrupt + USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt + USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt + SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor call interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Freqme_IRQHandler, // 87 : Frequency Measurement interrupt + SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) + ELS_IRQHandler, // 89 : ELS interrupt + PKC_IRQHandler, // 90 : PKC interrupt + PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt + Reserved92_IRQHandler, // 92 : Reserved interrupt + EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete + EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete + EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete + EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete + EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete + EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete + EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete + EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete + Reserved101_IRQHandler, // 101: Reserved interrupt + Reserved102_IRQHandler, // 102: Reserved interrupt + Reserved103_IRQHandler, // 103: Reserved interrupt + Reserved104_IRQHandler, // 104: Reserved interrupt + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt + CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt + I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 + I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 + Reserved113_IRQHandler, // 113: Reserved interrupt + GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt + VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper interrupt) + EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + Reserved124_IRQHandler, // 124: Reserved interrupt + HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt + HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 capture/compare/reload interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 134: FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 135: FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 136: FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 137: FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 138: FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 139: FlexPWM1 Submodule 3 capture/compare/reload interrupt + QDC0_COMPARE_IRQHandler, // 140: QDC0_Compare interrupt + QDC0_HOME_IRQHandler, // 141: QDC0_Home interrupt + QDC0_WDG_SAB_IRQHandler, // 142: QDC0_WDG_IRQ/SAB interrupt + QDC0_IDX_IRQHandler, // 143: QDC0_IDX interrupt + QDC1_COMPARE_IRQHandler, // 144: QDC1_Compare interrupt + QDC1_HOME_IRQHandler, // 145: QDC1_Home interrupt + QDC1_WDG_SAB_IRQHandler, // 146: QDC1_WDG_IRQ/SAB interrupt + QDC1_IDX_IRQHandler, // 147: QDC1_IDX interrupt + ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller interrupt + Reserved149_IRQHandler, // 149: Reserved interrupt + ELS_ERR_IRQHandler, // 150: ELS error interrupt + PKC_ERR_IRQHandler, // 151: PKC error interrupt + ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt + ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt + FMU0_IRQHandler, // 154: Flash Management Unit interrupt + Reserved155_IRQHandler, // 155: Reserved interrupt + Reserved156_IRQHandler, // 156: Reserved interrupt + Reserved157_IRQHandler, // 157: Reserved interrupt + Reserved158_IRQHandler, // 158: Reserved interrupt + LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt + LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt + SCG_IRQHandler, // 161: System Clock Generator interrupt + SPC_IRQHandler, // 162: System Power Controller interrupt + WUU_IRQHandler, // 163: Wake Up Unit interrupt + PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt + Reserved165_IRQHandler, // 165: Reserved interrupt + Reserved166_IRQHandler, // 166: Reserved interrupt + Reserved167_IRQHandler, // 167: Reserved interrupt + WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt + WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt + CMC0_IRQHandler, // 170: Core Mode Controller interrupt +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((naked, section(".after_vectors.reset"))) +void ResetISR(void) { + // Disable interrupts + __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void OR_IRQHandler(void) +{ OR_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH0_IRQHandler(void) +{ EDMA_0_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH1_IRQHandler(void) +{ EDMA_0_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH2_IRQHandler(void) +{ EDMA_0_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH3_IRQHandler(void) +{ EDMA_0_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH4_IRQHandler(void) +{ EDMA_0_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH5_IRQHandler(void) +{ EDMA_0_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH6_IRQHandler(void) +{ EDMA_0_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH7_IRQHandler(void) +{ EDMA_0_CH7_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH8_IRQHandler(void) +{ EDMA_0_CH8_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH9_IRQHandler(void) +{ EDMA_0_CH9_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH10_IRQHandler(void) +{ EDMA_0_CH10_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH11_IRQHandler(void) +{ EDMA_0_CH11_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH12_IRQHandler(void) +{ EDMA_0_CH12_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH13_IRQHandler(void) +{ EDMA_0_CH13_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH14_IRQHandler(void) +{ EDMA_0_CH14_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH15_IRQHandler(void) +{ EDMA_0_CH15_DriverIRQHandler(); +} + +WEAK void GPIO00_IRQHandler(void) +{ GPIO00_DriverIRQHandler(); +} + +WEAK void GPIO01_IRQHandler(void) +{ GPIO01_DriverIRQHandler(); +} + +WEAK void GPIO10_IRQHandler(void) +{ GPIO10_DriverIRQHandler(); +} + +WEAK void GPIO11_IRQHandler(void) +{ GPIO11_DriverIRQHandler(); +} + +WEAK void GPIO20_IRQHandler(void) +{ GPIO20_DriverIRQHandler(); +} + +WEAK void GPIO21_IRQHandler(void) +{ GPIO21_DriverIRQHandler(); +} + +WEAK void GPIO30_IRQHandler(void) +{ GPIO30_DriverIRQHandler(); +} + +WEAK void GPIO31_IRQHandler(void) +{ GPIO31_DriverIRQHandler(); +} + +WEAK void GPIO40_IRQHandler(void) +{ GPIO40_DriverIRQHandler(); +} + +WEAK void GPIO41_IRQHandler(void) +{ GPIO41_DriverIRQHandler(); +} + +WEAK void GPIO50_IRQHandler(void) +{ GPIO50_DriverIRQHandler(); +} + +WEAK void GPIO51_IRQHandler(void) +{ GPIO51_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void Reserved49_IRQHandler(void) +{ Reserved49_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM0_IRQHandler(void) +{ LP_FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM1_IRQHandler(void) +{ LP_FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM2_IRQHandler(void) +{ LP_FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM3_IRQHandler(void) +{ LP_FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM4_IRQHandler(void) +{ LP_FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM5_IRQHandler(void) +{ LP_FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM6_IRQHandler(void) +{ LP_FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM7_IRQHandler(void) +{ LP_FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void PINT0_IRQHandler(void) +{ PINT0_DriverIRQHandler(); +} + +WEAK void PDM_EVENT_IRQHandler(void) +{ PDM_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved65_IRQHandler(void) +{ Reserved65_DriverIRQHandler(); +} + +WEAK void Reserved66_IRQHandler(void) +{ Reserved66_DriverIRQHandler(); +} + +WEAK void USB0_DCD_IRQHandler(void) +{ USB0_DCD_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved70_IRQHandler(void) +{ Reserved70_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved74_IRQHandler(void) +{ Reserved74_DriverIRQHandler(); +} + +WEAK void SAI0_IRQHandler(void) +{ SAI0_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ Reserved77_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void Reserved80_IRQHandler(void) +{ Reserved80_DriverIRQHandler(); +} + +WEAK void Reserved81_IRQHandler(void) +{ Reserved81_DriverIRQHandler(); +} + +WEAK void USB1_HS_PHY_IRQHandler(void) +{ USB1_HS_PHY_DriverIRQHandler(); +} + +WEAK void USB1_HS_IRQHandler(void) +{ USB1_HS_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Freqme_IRQHandler(void) +{ Freqme_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void ELS_IRQHandler(void) +{ ELS_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ PKC_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ Reserved92_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH0_IRQHandler(void) +{ EDMA_1_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH1_IRQHandler(void) +{ EDMA_1_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH2_IRQHandler(void) +{ EDMA_1_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH3_IRQHandler(void) +{ EDMA_1_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH4_IRQHandler(void) +{ EDMA_1_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH5_IRQHandler(void) +{ EDMA_1_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH6_IRQHandler(void) +{ EDMA_1_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH7_IRQHandler(void) +{ EDMA_1_CH7_DriverIRQHandler(); +} + +WEAK void Reserved101_IRQHandler(void) +{ Reserved101_DriverIRQHandler(); +} + +WEAK void Reserved102_IRQHandler(void) +{ Reserved102_DriverIRQHandler(); +} + +WEAK void Reserved103_IRQHandler(void) +{ Reserved103_DriverIRQHandler(); +} + +WEAK void Reserved104_IRQHandler(void) +{ Reserved104_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ Reserved108_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ CDOG0_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ CDOG1_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ I3C0_DriverIRQHandler(); +} + +WEAK void I3C1_IRQHandler(void) +{ I3C1_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ Reserved113_DriverIRQHandler(); +} + +WEAK void GDET_IRQHandler(void) +{ GDET_DriverIRQHandler(); +} + +WEAK void VBAT0_IRQHandler(void) +{ VBAT0_DriverIRQHandler(); +} + +WEAK void EWM0_IRQHandler(void) +{ EWM0_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ Reserved120_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ FLEXIO_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ Reserved122_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void Reserved124_IRQHandler(void) +{ Reserved124_DriverIRQHandler(); +} + +WEAK void HSCMP0_IRQHandler(void) +{ HSCMP0_DriverIRQHandler(); +} + +WEAK void HSCMP1_IRQHandler(void) +{ HSCMP1_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ Reserved127_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void QDC0_COMPARE_IRQHandler(void) +{ QDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC0_HOME_IRQHandler(void) +{ QDC0_HOME_DriverIRQHandler(); +} + +WEAK void QDC0_WDG_SAB_IRQHandler(void) +{ QDC0_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC0_IDX_IRQHandler(void) +{ QDC0_IDX_DriverIRQHandler(); +} + +WEAK void QDC1_COMPARE_IRQHandler(void) +{ QDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC1_HOME_IRQHandler(void) +{ QDC1_HOME_DriverIRQHandler(); +} + +WEAK void QDC1_WDG_SAB_IRQHandler(void) +{ QDC1_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC1_IDX_IRQHandler(void) +{ QDC1_IDX_DriverIRQHandler(); +} + +WEAK void ITRC0_IRQHandler(void) +{ ITRC0_DriverIRQHandler(); +} + +WEAK void Reserved149_IRQHandler(void) +{ Reserved149_DriverIRQHandler(); +} + +WEAK void ELS_ERR_IRQHandler(void) +{ ELS_ERR_DriverIRQHandler(); +} + +WEAK void PKC_ERR_IRQHandler(void) +{ PKC_ERR_DriverIRQHandler(); +} + +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void) +{ ERM_SINGLE_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void) +{ ERM_MULTI_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ FMU0_DriverIRQHandler(); +} + +WEAK void Reserved155_IRQHandler(void) +{ Reserved155_DriverIRQHandler(); +} + +WEAK void Reserved156_IRQHandler(void) +{ Reserved156_DriverIRQHandler(); +} + +WEAK void Reserved157_IRQHandler(void) +{ Reserved157_DriverIRQHandler(); +} + +WEAK void Reserved158_IRQHandler(void) +{ Reserved158_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ LPTMR0_DriverIRQHandler(); +} + +WEAK void LPTMR1_IRQHandler(void) +{ LPTMR1_DriverIRQHandler(); +} + +WEAK void SCG_IRQHandler(void) +{ SCG_DriverIRQHandler(); +} + +WEAK void SPC_IRQHandler(void) +{ SPC_DriverIRQHandler(); +} + +WEAK void WUU_IRQHandler(void) +{ WUU_DriverIRQHandler(); +} + +WEAK void PORT_EFT_IRQHandler(void) +{ PORT_EFT_DriverIRQHandler(); +} + +WEAK void Reserved165_IRQHandler(void) +{ Reserved165_DriverIRQHandler(); +} + +WEAK void Reserved166_IRQHandler(void) +{ Reserved166_DriverIRQHandler(); +} + +WEAK void Reserved167_IRQHandler(void) +{ Reserved167_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ WWDT0_DriverIRQHandler(); +} + +WEAK void WWDT1_IRQHandler(void) +{ WWDT1_DriverIRQHandler(); +} + +WEAK void CMC0_IRQHandler(void) +{ CMC0_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/devices/MCXN236/mcuxpresso/startup_mcxn236.cpp b/devices/MCXN236/mcuxpresso/startup_mcxn236.cpp new file mode 100644 index 000000000..35873bb15 --- /dev/null +++ b/devices/MCXN236/mcuxpresso/startup_mcxn236.cpp @@ -0,0 +1,1409 @@ +//***************************************************************************** +// MCXN236 startup code for use with MCUXpresso IDE +// +// Version : 090424 +//***************************************************************************** +// +// Copyright 2016-2024 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void OR_IRQHandler(void); +WEAK void EDMA_0_CH0_IRQHandler(void); +WEAK void EDMA_0_CH1_IRQHandler(void); +WEAK void EDMA_0_CH2_IRQHandler(void); +WEAK void EDMA_0_CH3_IRQHandler(void); +WEAK void EDMA_0_CH4_IRQHandler(void); +WEAK void EDMA_0_CH5_IRQHandler(void); +WEAK void EDMA_0_CH6_IRQHandler(void); +WEAK void EDMA_0_CH7_IRQHandler(void); +WEAK void EDMA_0_CH8_IRQHandler(void); +WEAK void EDMA_0_CH9_IRQHandler(void); +WEAK void EDMA_0_CH10_IRQHandler(void); +WEAK void EDMA_0_CH11_IRQHandler(void); +WEAK void EDMA_0_CH12_IRQHandler(void); +WEAK void EDMA_0_CH13_IRQHandler(void); +WEAK void EDMA_0_CH14_IRQHandler(void); +WEAK void EDMA_0_CH15_IRQHandler(void); +WEAK void GPIO00_IRQHandler(void); +WEAK void GPIO01_IRQHandler(void); +WEAK void GPIO10_IRQHandler(void); +WEAK void GPIO11_IRQHandler(void); +WEAK void GPIO20_IRQHandler(void); +WEAK void GPIO21_IRQHandler(void); +WEAK void GPIO30_IRQHandler(void); +WEAK void GPIO31_IRQHandler(void); +WEAK void GPIO40_IRQHandler(void); +WEAK void GPIO41_IRQHandler(void); +WEAK void GPIO50_IRQHandler(void); +WEAK void GPIO51_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void Reserved49_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void LP_FLEXCOMM0_IRQHandler(void); +WEAK void LP_FLEXCOMM1_IRQHandler(void); +WEAK void LP_FLEXCOMM2_IRQHandler(void); +WEAK void LP_FLEXCOMM3_IRQHandler(void); +WEAK void LP_FLEXCOMM4_IRQHandler(void); +WEAK void LP_FLEXCOMM5_IRQHandler(void); +WEAK void LP_FLEXCOMM6_IRQHandler(void); +WEAK void LP_FLEXCOMM7_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void PINT0_IRQHandler(void); +WEAK void PDM_EVENT_IRQHandler(void); +WEAK void Reserved65_IRQHandler(void); +WEAK void Reserved66_IRQHandler(void); +WEAK void USB0_DCD_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void SMARTDMA_IRQHandler(void); +WEAK void Reserved70_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved74_IRQHandler(void); +WEAK void SAI0_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void Reserved77_IRQHandler(void); +WEAK void CAN0_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void Reserved80_IRQHandler(void); +WEAK void Reserved81_IRQHandler(void); +WEAK void USB1_HS_PHY_IRQHandler(void); +WEAK void USB1_HS_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void Reserved85_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Freqme_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void ELS_IRQHandler(void); +WEAK void PKC_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void Reserved92_IRQHandler(void); +WEAK void EDMA_1_CH0_IRQHandler(void); +WEAK void EDMA_1_CH1_IRQHandler(void); +WEAK void EDMA_1_CH2_IRQHandler(void); +WEAK void EDMA_1_CH3_IRQHandler(void); +WEAK void EDMA_1_CH4_IRQHandler(void); +WEAK void EDMA_1_CH5_IRQHandler(void); +WEAK void EDMA_1_CH6_IRQHandler(void); +WEAK void EDMA_1_CH7_IRQHandler(void); +WEAK void Reserved101_IRQHandler(void); +WEAK void Reserved102_IRQHandler(void); +WEAK void Reserved103_IRQHandler(void); +WEAK void Reserved104_IRQHandler(void); +WEAK void Reserved105_IRQHandler(void); +WEAK void Reserved106_IRQHandler(void); +WEAK void Reserved107_IRQHandler(void); +WEAK void Reserved108_IRQHandler(void); +WEAK void CDOG0_IRQHandler(void); +WEAK void CDOG1_IRQHandler(void); +WEAK void I3C0_IRQHandler(void); +WEAK void I3C1_IRQHandler(void); +WEAK void Reserved113_IRQHandler(void); +WEAK void GDET_IRQHandler(void); +WEAK void VBAT0_IRQHandler(void); +WEAK void EWM0_IRQHandler(void); +WEAK void Reserved117_IRQHandler(void); +WEAK void Reserved118_IRQHandler(void); +WEAK void Reserved119_IRQHandler(void); +WEAK void Reserved120_IRQHandler(void); +WEAK void FLEXIO_IRQHandler(void); +WEAK void Reserved122_IRQHandler(void); +WEAK void Reserved123_IRQHandler(void); +WEAK void Reserved124_IRQHandler(void); +WEAK void HSCMP0_IRQHandler(void); +WEAK void HSCMP1_IRQHandler(void); +WEAK void Reserved127_IRQHandler(void); +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM0_FAULT_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void); +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); +WEAK void FLEXPWM1_FAULT_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void); +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void); +WEAK void QDC0_COMPARE_IRQHandler(void); +WEAK void QDC0_HOME_IRQHandler(void); +WEAK void QDC0_WDG_SAB_IRQHandler(void); +WEAK void QDC0_IDX_IRQHandler(void); +WEAK void QDC1_COMPARE_IRQHandler(void); +WEAK void QDC1_HOME_IRQHandler(void); +WEAK void QDC1_WDG_SAB_IRQHandler(void); +WEAK void QDC1_IDX_IRQHandler(void); +WEAK void ITRC0_IRQHandler(void); +WEAK void Reserved149_IRQHandler(void); +WEAK void ELS_ERR_IRQHandler(void); +WEAK void PKC_ERR_IRQHandler(void); +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void); +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void); +WEAK void FMU0_IRQHandler(void); +WEAK void Reserved155_IRQHandler(void); +WEAK void Reserved156_IRQHandler(void); +WEAK void Reserved157_IRQHandler(void); +WEAK void Reserved158_IRQHandler(void); +WEAK void LPTMR0_IRQHandler(void); +WEAK void LPTMR1_IRQHandler(void); +WEAK void SCG_IRQHandler(void); +WEAK void SPC_IRQHandler(void); +WEAK void WUU_IRQHandler(void); +WEAK void PORT_EFT_IRQHandler(void); +WEAK void Reserved165_IRQHandler(void); +WEAK void Reserved166_IRQHandler(void); +WEAK void Reserved167_IRQHandler(void); +WEAK void WWDT0_IRQHandler(void); +WEAK void WWDT1_IRQHandler(void); +WEAK void CMC0_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void OR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH12_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH13_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH14_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_0_CH15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO00_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO01_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO11_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO40_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO50_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO51_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved49_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LP_FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PDM_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SMARTDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved77_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved80_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved81_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_HS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved85_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Freqme_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved92_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EDMA_1_CH7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved101_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved102_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved103_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved104_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved105_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved106_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved107_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved108_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void I3C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved113_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GDET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void VBAT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved117_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved118_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved119_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved120_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved122_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved123_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved124_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HSCMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved127_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM0_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXPWM1_SUBMODULE3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC0_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_COMPARE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_HOME_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_WDG_SAB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void QDC1_IDX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ITRC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved149_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ELS_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PKC_ERR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_SINGLE_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ERM_MULTI_BIT_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FMU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved155_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved156_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved157_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved158_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WUU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PORT_EFT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved165_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved166_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved167_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WWDT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +extern void _vStackBase(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** + +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + SecureFault_Handler, // Secure Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler + + // Chip Level - MCXN236 + OR_IRQHandler, // 16 : OR IRQ + EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete + EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete + EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete + EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete + EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete + EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete + EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete + EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete + EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete + EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete + EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete + EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete + EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete + EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete + EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete + EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete + GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 + GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 + GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 + GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 + GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 + GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 + GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 + GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 + GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 + GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 + GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 + GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 + UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt + MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt + CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt + CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt + Reserved49_IRQHandler, // 49 : Reserved interrupt + CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt + LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose interrupt + ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose interrupt + PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt + PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt + Reserved65_IRQHandler, // 65 : Reserved interrupt + Reserved66_IRQHandler, // 66 : Reserved interrupt + USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect interrupt + RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) + SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ + Reserved70_IRQHandler, // 70 : Reserved interrupt + CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt + CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt + OS_EVENT_IRQHandler, // 73 : OS event timer interrupt + Reserved74_IRQHandler, // 74 : Reserved interrupt + SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt + SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt + Reserved77_IRQHandler, // 77 : Reserved interrupt + CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt + CAN1_IRQHandler, // 79 : Controller Area Network 1 interrupt + Reserved80_IRQHandler, // 80 : Reserved interrupt + Reserved81_IRQHandler, // 81 : Reserved interrupt + USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt + USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt + SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor call interrupt + Reserved85_IRQHandler, // 85 : Reserved interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Freqme_IRQHandler, // 87 : Frequency Measurement interrupt + SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) + ELS_IRQHandler, // 89 : ELS interrupt + PKC_IRQHandler, // 90 : PKC interrupt + PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt + Reserved92_IRQHandler, // 92 : Reserved interrupt + EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete + EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete + EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete + EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete + EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete + EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete + EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete + EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete + Reserved101_IRQHandler, // 101: Reserved interrupt + Reserved102_IRQHandler, // 102: Reserved interrupt + Reserved103_IRQHandler, // 103: Reserved interrupt + Reserved104_IRQHandler, // 104: Reserved interrupt + Reserved105_IRQHandler, // 105: Reserved interrupt + Reserved106_IRQHandler, // 106: Reserved interrupt + Reserved107_IRQHandler, // 107: Reserved interrupt + Reserved108_IRQHandler, // 108: Reserved interrupt + CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt + CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt + I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 + I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 + Reserved113_IRQHandler, // 113: Reserved interrupt + GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt + VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper interrupt) + EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt + Reserved117_IRQHandler, // 117: Reserved interrupt + Reserved118_IRQHandler, // 118: Reserved interrupt + Reserved119_IRQHandler, // 119: Reserved interrupt + Reserved120_IRQHandler, // 120: Reserved interrupt + FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt + Reserved122_IRQHandler, // 122: Reserved interrupt + Reserved123_IRQHandler, // 123: Reserved interrupt + Reserved124_IRQHandler, // 124: Reserved interrupt + HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt + HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt + Reserved127_IRQHandler, // 127: Reserved interrupt + FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt + FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt + FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 capture/compare/reload interrupt + FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 capture/compare/reload interrupt + FLEXPWM1_RELOAD_ERROR_IRQHandler, // 134: FlexPWM1_reload_error interrupt + FLEXPWM1_FAULT_IRQHandler, // 135: FlexPWM1_fault interrupt + FLEXPWM1_SUBMODULE0_IRQHandler, // 136: FlexPWM1 Submodule 0 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE1_IRQHandler, // 137: FlexPWM1 Submodule 1 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE2_IRQHandler, // 138: FlexPWM1 Submodule 2 capture/compare/reload interrupt + FLEXPWM1_SUBMODULE3_IRQHandler, // 139: FlexPWM1 Submodule 3 capture/compare/reload interrupt + QDC0_COMPARE_IRQHandler, // 140: QDC0_Compare interrupt + QDC0_HOME_IRQHandler, // 141: QDC0_Home interrupt + QDC0_WDG_SAB_IRQHandler, // 142: QDC0_WDG_IRQ/SAB interrupt + QDC0_IDX_IRQHandler, // 143: QDC0_IDX interrupt + QDC1_COMPARE_IRQHandler, // 144: QDC1_Compare interrupt + QDC1_HOME_IRQHandler, // 145: QDC1_Home interrupt + QDC1_WDG_SAB_IRQHandler, // 146: QDC1_WDG_IRQ/SAB interrupt + QDC1_IDX_IRQHandler, // 147: QDC1_IDX interrupt + ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller interrupt + Reserved149_IRQHandler, // 149: Reserved interrupt + ELS_ERR_IRQHandler, // 150: ELS error interrupt + PKC_ERR_IRQHandler, // 151: PKC error interrupt + ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt + ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt + FMU0_IRQHandler, // 154: Flash Management Unit interrupt + Reserved155_IRQHandler, // 155: Reserved interrupt + Reserved156_IRQHandler, // 156: Reserved interrupt + Reserved157_IRQHandler, // 157: Reserved interrupt + Reserved158_IRQHandler, // 158: Reserved interrupt + LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt + LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt + SCG_IRQHandler, // 161: System Clock Generator interrupt + SPC_IRQHandler, // 162: System Power Controller interrupt + WUU_IRQHandler, // 163: Wake Up Unit interrupt + PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt + Reserved165_IRQHandler, // 165: Reserved interrupt + Reserved166_IRQHandler, // 166: Reserved interrupt + Reserved167_IRQHandler, // 167: Reserved interrupt + WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt + WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt + CMC0_IRQHandler, // 170: Core Mode Controller interrupt +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((naked, section(".after_vectors.reset"))) +void ResetISR(void) { + // Disable interrupts + __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void OR_IRQHandler(void) +{ OR_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH0_IRQHandler(void) +{ EDMA_0_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH1_IRQHandler(void) +{ EDMA_0_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH2_IRQHandler(void) +{ EDMA_0_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH3_IRQHandler(void) +{ EDMA_0_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH4_IRQHandler(void) +{ EDMA_0_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH5_IRQHandler(void) +{ EDMA_0_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH6_IRQHandler(void) +{ EDMA_0_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH7_IRQHandler(void) +{ EDMA_0_CH7_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH8_IRQHandler(void) +{ EDMA_0_CH8_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH9_IRQHandler(void) +{ EDMA_0_CH9_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH10_IRQHandler(void) +{ EDMA_0_CH10_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH11_IRQHandler(void) +{ EDMA_0_CH11_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH12_IRQHandler(void) +{ EDMA_0_CH12_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH13_IRQHandler(void) +{ EDMA_0_CH13_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH14_IRQHandler(void) +{ EDMA_0_CH14_DriverIRQHandler(); +} + +WEAK void EDMA_0_CH15_IRQHandler(void) +{ EDMA_0_CH15_DriverIRQHandler(); +} + +WEAK void GPIO00_IRQHandler(void) +{ GPIO00_DriverIRQHandler(); +} + +WEAK void GPIO01_IRQHandler(void) +{ GPIO01_DriverIRQHandler(); +} + +WEAK void GPIO10_IRQHandler(void) +{ GPIO10_DriverIRQHandler(); +} + +WEAK void GPIO11_IRQHandler(void) +{ GPIO11_DriverIRQHandler(); +} + +WEAK void GPIO20_IRQHandler(void) +{ GPIO20_DriverIRQHandler(); +} + +WEAK void GPIO21_IRQHandler(void) +{ GPIO21_DriverIRQHandler(); +} + +WEAK void GPIO30_IRQHandler(void) +{ GPIO30_DriverIRQHandler(); +} + +WEAK void GPIO31_IRQHandler(void) +{ GPIO31_DriverIRQHandler(); +} + +WEAK void GPIO40_IRQHandler(void) +{ GPIO40_DriverIRQHandler(); +} + +WEAK void GPIO41_IRQHandler(void) +{ GPIO41_DriverIRQHandler(); +} + +WEAK void GPIO50_IRQHandler(void) +{ GPIO50_DriverIRQHandler(); +} + +WEAK void GPIO51_IRQHandler(void) +{ GPIO51_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void Reserved49_IRQHandler(void) +{ Reserved49_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM0_IRQHandler(void) +{ LP_FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM1_IRQHandler(void) +{ LP_FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM2_IRQHandler(void) +{ LP_FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM3_IRQHandler(void) +{ LP_FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM4_IRQHandler(void) +{ LP_FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM5_IRQHandler(void) +{ LP_FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM6_IRQHandler(void) +{ LP_FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void LP_FLEXCOMM7_IRQHandler(void) +{ LP_FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void PINT0_IRQHandler(void) +{ PINT0_DriverIRQHandler(); +} + +WEAK void PDM_EVENT_IRQHandler(void) +{ PDM_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved65_IRQHandler(void) +{ Reserved65_DriverIRQHandler(); +} + +WEAK void Reserved66_IRQHandler(void) +{ Reserved66_DriverIRQHandler(); +} + +WEAK void USB0_DCD_IRQHandler(void) +{ USB0_DCD_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void SMARTDMA_IRQHandler(void) +{ SMARTDMA_DriverIRQHandler(); +} + +WEAK void Reserved70_IRQHandler(void) +{ Reserved70_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved74_IRQHandler(void) +{ Reserved74_DriverIRQHandler(); +} + +WEAK void SAI0_IRQHandler(void) +{ SAI0_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void Reserved77_IRQHandler(void) +{ Reserved77_DriverIRQHandler(); +} + +WEAK void CAN0_IRQHandler(void) +{ CAN0_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void Reserved80_IRQHandler(void) +{ Reserved80_DriverIRQHandler(); +} + +WEAK void Reserved81_IRQHandler(void) +{ Reserved81_DriverIRQHandler(); +} + +WEAK void USB1_HS_PHY_IRQHandler(void) +{ USB1_HS_PHY_DriverIRQHandler(); +} + +WEAK void USB1_HS_IRQHandler(void) +{ USB1_HS_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void Reserved85_IRQHandler(void) +{ Reserved85_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Freqme_IRQHandler(void) +{ Freqme_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void ELS_IRQHandler(void) +{ ELS_DriverIRQHandler(); +} + +WEAK void PKC_IRQHandler(void) +{ PKC_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void Reserved92_IRQHandler(void) +{ Reserved92_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH0_IRQHandler(void) +{ EDMA_1_CH0_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH1_IRQHandler(void) +{ EDMA_1_CH1_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH2_IRQHandler(void) +{ EDMA_1_CH2_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH3_IRQHandler(void) +{ EDMA_1_CH3_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH4_IRQHandler(void) +{ EDMA_1_CH4_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH5_IRQHandler(void) +{ EDMA_1_CH5_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH6_IRQHandler(void) +{ EDMA_1_CH6_DriverIRQHandler(); +} + +WEAK void EDMA_1_CH7_IRQHandler(void) +{ EDMA_1_CH7_DriverIRQHandler(); +} + +WEAK void Reserved101_IRQHandler(void) +{ Reserved101_DriverIRQHandler(); +} + +WEAK void Reserved102_IRQHandler(void) +{ Reserved102_DriverIRQHandler(); +} + +WEAK void Reserved103_IRQHandler(void) +{ Reserved103_DriverIRQHandler(); +} + +WEAK void Reserved104_IRQHandler(void) +{ Reserved104_DriverIRQHandler(); +} + +WEAK void Reserved105_IRQHandler(void) +{ Reserved105_DriverIRQHandler(); +} + +WEAK void Reserved106_IRQHandler(void) +{ Reserved106_DriverIRQHandler(); +} + +WEAK void Reserved107_IRQHandler(void) +{ Reserved107_DriverIRQHandler(); +} + +WEAK void Reserved108_IRQHandler(void) +{ Reserved108_DriverIRQHandler(); +} + +WEAK void CDOG0_IRQHandler(void) +{ CDOG0_DriverIRQHandler(); +} + +WEAK void CDOG1_IRQHandler(void) +{ CDOG1_DriverIRQHandler(); +} + +WEAK void I3C0_IRQHandler(void) +{ I3C0_DriverIRQHandler(); +} + +WEAK void I3C1_IRQHandler(void) +{ I3C1_DriverIRQHandler(); +} + +WEAK void Reserved113_IRQHandler(void) +{ Reserved113_DriverIRQHandler(); +} + +WEAK void GDET_IRQHandler(void) +{ GDET_DriverIRQHandler(); +} + +WEAK void VBAT0_IRQHandler(void) +{ VBAT0_DriverIRQHandler(); +} + +WEAK void EWM0_IRQHandler(void) +{ EWM0_DriverIRQHandler(); +} + +WEAK void Reserved117_IRQHandler(void) +{ Reserved117_DriverIRQHandler(); +} + +WEAK void Reserved118_IRQHandler(void) +{ Reserved118_DriverIRQHandler(); +} + +WEAK void Reserved119_IRQHandler(void) +{ Reserved119_DriverIRQHandler(); +} + +WEAK void Reserved120_IRQHandler(void) +{ Reserved120_DriverIRQHandler(); +} + +WEAK void FLEXIO_IRQHandler(void) +{ FLEXIO_DriverIRQHandler(); +} + +WEAK void Reserved122_IRQHandler(void) +{ Reserved122_DriverIRQHandler(); +} + +WEAK void Reserved123_IRQHandler(void) +{ Reserved123_DriverIRQHandler(); +} + +WEAK void Reserved124_IRQHandler(void) +{ Reserved124_DriverIRQHandler(); +} + +WEAK void HSCMP0_IRQHandler(void) +{ HSCMP0_DriverIRQHandler(); +} + +WEAK void HSCMP1_IRQHandler(void) +{ HSCMP1_DriverIRQHandler(); +} + +WEAK void Reserved127_IRQHandler(void) +{ Reserved127_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM0_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_FAULT_IRQHandler(void) +{ FLEXPWM0_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE0_IRQHandler(void) +{ FLEXPWM0_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE1_IRQHandler(void) +{ FLEXPWM0_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE2_IRQHandler(void) +{ FLEXPWM0_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM0_SUBMODULE3_IRQHandler(void) +{ FLEXPWM0_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_RELOAD_ERROR_IRQHandler(void) +{ FLEXPWM1_RELOAD_ERROR_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_FAULT_IRQHandler(void) +{ FLEXPWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE0_IRQHandler(void) +{ FLEXPWM1_SUBMODULE0_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE1_IRQHandler(void) +{ FLEXPWM1_SUBMODULE1_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE2_IRQHandler(void) +{ FLEXPWM1_SUBMODULE2_DriverIRQHandler(); +} + +WEAK void FLEXPWM1_SUBMODULE3_IRQHandler(void) +{ FLEXPWM1_SUBMODULE3_DriverIRQHandler(); +} + +WEAK void QDC0_COMPARE_IRQHandler(void) +{ QDC0_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC0_HOME_IRQHandler(void) +{ QDC0_HOME_DriverIRQHandler(); +} + +WEAK void QDC0_WDG_SAB_IRQHandler(void) +{ QDC0_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC0_IDX_IRQHandler(void) +{ QDC0_IDX_DriverIRQHandler(); +} + +WEAK void QDC1_COMPARE_IRQHandler(void) +{ QDC1_COMPARE_DriverIRQHandler(); +} + +WEAK void QDC1_HOME_IRQHandler(void) +{ QDC1_HOME_DriverIRQHandler(); +} + +WEAK void QDC1_WDG_SAB_IRQHandler(void) +{ QDC1_WDG_SAB_DriverIRQHandler(); +} + +WEAK void QDC1_IDX_IRQHandler(void) +{ QDC1_IDX_DriverIRQHandler(); +} + +WEAK void ITRC0_IRQHandler(void) +{ ITRC0_DriverIRQHandler(); +} + +WEAK void Reserved149_IRQHandler(void) +{ Reserved149_DriverIRQHandler(); +} + +WEAK void ELS_ERR_IRQHandler(void) +{ ELS_ERR_DriverIRQHandler(); +} + +WEAK void PKC_ERR_IRQHandler(void) +{ PKC_ERR_DriverIRQHandler(); +} + +WEAK void ERM_SINGLE_BIT_ERROR_IRQHandler(void) +{ ERM_SINGLE_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void ERM_MULTI_BIT_ERROR_IRQHandler(void) +{ ERM_MULTI_BIT_ERROR_DriverIRQHandler(); +} + +WEAK void FMU0_IRQHandler(void) +{ FMU0_DriverIRQHandler(); +} + +WEAK void Reserved155_IRQHandler(void) +{ Reserved155_DriverIRQHandler(); +} + +WEAK void Reserved156_IRQHandler(void) +{ Reserved156_DriverIRQHandler(); +} + +WEAK void Reserved157_IRQHandler(void) +{ Reserved157_DriverIRQHandler(); +} + +WEAK void Reserved158_IRQHandler(void) +{ Reserved158_DriverIRQHandler(); +} + +WEAK void LPTMR0_IRQHandler(void) +{ LPTMR0_DriverIRQHandler(); +} + +WEAK void LPTMR1_IRQHandler(void) +{ LPTMR1_DriverIRQHandler(); +} + +WEAK void SCG_IRQHandler(void) +{ SCG_DriverIRQHandler(); +} + +WEAK void SPC_IRQHandler(void) +{ SPC_DriverIRQHandler(); +} + +WEAK void WUU_IRQHandler(void) +{ WUU_DriverIRQHandler(); +} + +WEAK void PORT_EFT_IRQHandler(void) +{ PORT_EFT_DriverIRQHandler(); +} + +WEAK void Reserved165_IRQHandler(void) +{ Reserved165_DriverIRQHandler(); +} + +WEAK void Reserved166_IRQHandler(void) +{ Reserved166_DriverIRQHandler(); +} + +WEAK void Reserved167_IRQHandler(void) +{ Reserved167_DriverIRQHandler(); +} + +WEAK void WWDT0_IRQHandler(void) +{ WWDT0_DriverIRQHandler(); +} + +WEAK void WWDT1_IRQHandler(void) +{ WWDT1_DriverIRQHandler(); +} + +WEAK void CMC0_IRQHandler(void) +{ CMC0_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/devices/MCXN236/project_template/board.c b/devices/MCXN236/project_template/board.c new file mode 100644 index 000000000..b5848545c --- /dev/null +++ b/devices/MCXN236/project_template/board.c @@ -0,0 +1,59 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER +#include "fsl_lpflexcomm.h" +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ +#include "fsl_spc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* attach 12 MHz clock to FLEXCOMM4 (debug console) */ + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); + CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); + + RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST); + + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + +#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER + LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART); +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +/* Update Active mode voltage for OverDrive mode. */ +void BOARD_PowerMode_OD(void) +{ + spc_active_mode_dcdc_option_t opt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); + + spc_sram_voltage_config_t cfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &cfg); +} diff --git a/devices/MCXN236/project_template/board.h b/devices/MCXN236/project_template/board.h new file mode 100644 index 000000000..f1cf86278 --- /dev/null +++ b/devices/MCXN236/project_template/board.h @@ -0,0 +1,148 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "FRDM-MCXN236" + +/*! @brief The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART4 +#define BOARD_DEBUG_UART_INSTANCE 4U +#define BOARD_DEBUG_UART_CLK_FREQ 12000000U +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4 +#define BOARD_DEBUG_UART_RST kFC4_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC kCLOCK_FlexComm4 +#define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM4_IRQHandler +#define BOARD_UART_IRQ LP_FLEXCOMM4_IRQn + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#endif + +#define BOARD_CODEC_I2C_BASEADDR LPI2C2 +#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000 +#define BOARD_CODEC_I2C_INSTANCE 2 + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO4 +#endif +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 18U +#endif + +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO4 +#endif +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 17U +#endif + +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO4 +#endif +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 19U +#endif + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO0 +#endif +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 20U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW2_IRQ GPIO00_IRQn +#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO0 +#endif +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 6U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ GPIO00_IRQn +#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED_RED_INIT(output) \ + GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ + BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ +#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ +#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ +#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ + +#define LED_BLUE_INIT(output) \ + GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ + BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ +#define LED_BLUE_ON() GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ +#define LED_BLUE_OFF() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ +#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ + BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ +#define LED_GREEN_ON() GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ +#define LED_GREEN_OFF() GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ +#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ + + +/* ERPC LPSPI configuration */ +#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1) +#define ERPC_BOARD_LPSPI_BASEADDR LPSPI3 +#define ERPC_BOARD_LPSPI_BAUDRATE 500000U +#define ERPC_BOARD_LPSPI_CLKSRC kCLOCK_Flexcomm3 +#define ERPC_BOARD_LPSPI_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(1) +#define ERPC_BOARD_LPSPI_INT_GPIO GPIO0 +#define ERPC_BOARD_LPSPI_INT_PIN 16U +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ PIN_INT0_IRQn +#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER PIN_INT0_IRQHandler + +/* ERPC LPI2C configuration */ +#define ERPC_BOARD_LPI2C_BASEADDR LPI2C0_BASE +#define ERPC_BOARD_LPI2C_BAUDRATE 100000U +#define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm0 +#define ERPC_BOARD_LPI2C_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(2) +#define ERPC_BOARD_LPI2C_INT_GPIO GPIO1 +#define ERPC_BOARD_LPI2C_INT_PIN 0U +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ PIN_INT1_IRQn +#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +void BOARD_PowerMode_OD(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/devices/MCXN236/project_template/clock_config.c b/devices/MCXN236/project_template/clock_config.c new file mode 100644 index 000000000..1f8c09954 --- /dev/null +++ b/devices/MCXN236/project_template/clock_config.c @@ -0,0 +1,447 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v12.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 12000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + /*!< Set up clock selectors */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Set the DCDC VDD regulator to 1.0 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_MidVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Configure Flash wait-states to support 1V voltage level and 48000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P0V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF144M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 144 MHz} +- {id: MAIN_clock.outFreq, value: 144 MHz} +- {id: Slow_clock.outFreq, value: 36 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: RunPowerMode, value: OD} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.FIRC.outFreq, value: 144 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF144M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 144000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */ + /*!< Set up clock selectors */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 150 MHz} +- {id: PLL0_CLK_clock.outFreq, value: 150 MHz} +- {id: Slow_clock.outFreq, value: 37.5 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: RunPowerMode, value: OD} +- {id: SCGMode, value: PLL0} +- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true} +- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M} +- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + /*!< Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: CLK_144M_clock.outFreq, value: 144 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CLK_IN_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 100 MHz} +- {id: PLL1_CLK_clock.outFreq, value: 100 MHz} +- {id: Slow_clock.outFreq, value: 25 MHz} +- {id: System_clock.outFreq, value: 100 MHz} +- {id: gdet_clock.outFreq, value: 48 MHz} +- {id: trng_clock.outFreq, value: 48 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: RunPowerMode, value: SD} +- {id: SCGMode, value: PLL1} +- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true} +- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true} +- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} +- {id: SCG_SOSCCSR_ERFES_SEL, value: CryOsc} +- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled} +- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a} +- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a} +sources: +- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ + CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */ + + /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */ + + /* Set the DCDC VDD regulator to 1.1 V voltage level */ + spc_active_mode_dcdc_option_t dcdcOpt = { + .DCDCVoltage = kSPC_DCDC_NormalVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt); + /* Set the LDO_CORE VDD regulator to 1.1 V voltage level */ + spc_active_mode_core_ldo_option_t ldoOpt = { + .CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt); + /* Configure Flash wait-states to support 1.1V voltage level and 100000000Hz frequency */; + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the 1.1V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t sramCfg = { + .operateVoltage = kSPC_sramOperateAt1P1V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &sramCfg); + + CLOCK_SetupExtClocking(24000000U); + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + /*!< Set up PLL1 */ + const pll_setup_t pll1Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U), + .pllndiv = SCG_SPLLNDIV_NDIV(6U), + .pllpdiv = SCG_SPLLPDIV_PDIV(2U), + .pllmdiv = SCG_SPLLMDIV_MDIV(100U), + .pllRate = 100000000U + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */ + + /*!< Set up clock selectors */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +} + diff --git a/devices/MCXN236/project_template/clock_config.h b/devices/MCXN236/project_template/clock_config.h new file mode 100644 index 000000000..eb259a85c --- /dev/null +++ b/devices/MCXN236/project_template/clock_config.h @@ -0,0 +1,177 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ +#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ +#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF144M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ +#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ +#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/devices/MCXN236/project_template/peripherals.c b/devices/MCXN236/project_template/peripherals.c new file mode 100644 index 000000000..75d5ffba1 --- /dev/null +++ b/devices/MCXN236/project_template/peripherals.c @@ -0,0 +1,99 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v13.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.5 +functionalGroups: +- name: BOARD_InitPeripherals + UUID: fbea44e1-da40-4200-8454-ce9165488681 + called_from_default_init: true + selectedCore: cm33_core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ + /* Initialize components */ +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/devices/MCXN236/project_template/peripherals.h b/devices/MCXN236/project_template/peripherals.h new file mode 100644 index 000000000..ead2693b4 --- /dev/null +++ b/devices/MCXN236/project_template/peripherals.h @@ -0,0 +1,39 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/devices/MCXN236/project_template/pin_mux.c b/devices/MCXN236/project_template/pin_mux.c new file mode 100644 index 000000000..3eb84f1be --- /dev/null +++ b/devices/MCXN236/project_template/pin_mux.c @@ -0,0 +1,61 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v14.0 +processor: MCXN236 +package_id: MCXN236VDF +mcu_data: ksdk2_0 +processor_version: 0.14.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/devices/MCXN236/project_template/pin_mux.h b/devices/MCXN236/project_template/pin_mux.h new file mode 100644 index 000000000..4cf27932b --- /dev/null +++ b/devices/MCXN236/project_template/pin_mux.h @@ -0,0 +1,52 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/devices/MCXN236/set_device_MCXN236.cmake b/devices/MCXN236/set_device_MCXN236.cmake new file mode 100644 index 000000000..39def3207 --- /dev/null +++ b/devices/MCXN236/set_device_MCXN236.cmake @@ -0,0 +1,4239 @@ +include_guard(GLOBAL) + + +if (CONFIG_USE_device_MCXN236_utility_frdmmcxn236) +# Add set(CONFIG_USE_device_MCXN236_utility_frdmmcxn236 true) in config.cmake to use this component + +message("device_MCXN236_utility_frdmmcxn236 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/utilities/. +) + + +endif() + + +if (CONFIG_USE_middleware_baremetal) +# Add set(CONFIG_USE_middleware_baremetal true) in config.cmake to use this component + +message("middleware_baremetal component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_OS_BAREMETAL + ) + +endif() + + +endif() + + +if (CONFIG_USE_utility_incbin) +# Add set(CONFIG_USE_utility_incbin true) in config.cmake to use this component + +message("utility_incbin component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_TOOLCHAIN STREQUAL armgcc) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities/fsl_incbin.S + ) +endif() + + +endif() + + +if (CONFIG_USE_utilities_misc_utilities) +# Add set(CONFIG_USE_utilities_misc_utilities true) in config.cmake to use this component + +message("utilities_misc_utilities component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_TOOLCHAIN STREQUAL armgcc) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities/fsl_sbrk.c + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities/fsl_syscall_stub.c + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND CONFIG_CORE STREQUAL cm33) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities/fsl_memcpy.S + ) +endif() + + +endif() + + +if (CONFIG_USE_utilities_unity) +# Add set(CONFIG_USE_utilities_unity true) in config.cmake to use this component + +message("utilities_unity component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_TOOLCHAIN STREQUAL mcux) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/unity/linkscripts/main_text.ldt + ) +endif() + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/unity/unity.c + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/unity/gcov_support.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/unity/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + if(CONFIG_TOOLCHAIN STREQUAL mcux) + target_compile_options(${MCUX_SDK_PROJECT_NAME} PUBLIC + ) + endif() + +endif() + + +endif() + + +if (CONFIG_USE_driver_rtt_template) +# Add set(CONFIG_USE_driver_rtt_template true) in config.cmake to use this component + +message("driver_rtt_template component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +add_config_file(${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/template/SEGGER_RTT_Conf.h ${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/template driver_rtt_template.MCXN236) + + +endif() + + +if (CONFIG_USE_driver_nand_flash-common) +# Add set(CONFIG_USE_driver_nand_flash-common true) in config.cmake to use this component + +message("driver_nand_flash-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/nand/. +) + + +endif() + + +if (CONFIG_USE_driver_nor_flash-common) +# Add set(CONFIG_USE_driver_nor_flash-common true) in config.cmake to use this component + +message("driver_nor_flash-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/nor/. +) + + +endif() + + +if (CONFIG_USE_component_mflash_common) +# Add set(CONFIG_USE_component_mflash_common true) in config.cmake to use this component + +message("component_mflash_common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/. +) + + +endif() + + +if (CONFIG_USE_driver_mx25r_flash) +# Add set(CONFIG_USE_driver_mx25r_flash true) in config.cmake to use this component + +message("driver_mx25r_flash component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/mx25r_flash/mx25r_flash.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/mx25r_flash/. +) + + +endif() + + +if (CONFIG_USE_driver_pf1550) +# Add set(CONFIG_USE_driver_pf1550 true) in config.cmake to use this component + +message("driver_pf1550 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/pf1550/fsl_pf1550.c + ${CMAKE_CURRENT_LIST_DIR}/../../components/pf1550/fsl_pf1550_charger.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/pf1550/. +) + + +endif() + + +if (CONFIG_USE_driver_pf3000) +# Add set(CONFIG_USE_driver_pf3000 true) in config.cmake to use this component + +message("driver_pf3000 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/pf3000/fsl_pf3000.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/pf3000/. +) + + +endif() + + +if (CONFIG_USE_driver_phy-common) +# Add set(CONFIG_USE_driver_phy-common true) in config.cmake to use this component + +message("driver_phy-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/. +) + + +endif() + + +if (CONFIG_USE_driver_p3t1755) +# Add set(CONFIG_USE_driver_p3t1755 true) in config.cmake to use this component + +message("driver_p3t1755 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/p3t1755/fsl_p3t1755.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/p3t1755/. +) + + +endif() + + +if (CONFIG_USE_component_wifi_bt_module_tx_pwr_limits) +# Add set(CONFIG_USE_component_wifi_bt_module_tx_pwr_limits true) in config.cmake to use this component + +message("component_wifi_bt_module_tx_pwr_limits component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/wifi_bt_module/AzureWave/tx_pwr_limits + ${CMAKE_CURRENT_LIST_DIR}/../../components/wifi_bt_module/Murata/tx_pwr_limits + ${CMAKE_CURRENT_LIST_DIR}/../../components/wifi_bt_module/u-blox/tx_pwr_limits +) + + +endif() + + +if (CONFIG_USE_component_wifi_bt_module_config) +# Add set(CONFIG_USE_component_wifi_bt_module_config true) in config.cmake to use this component + +message("component_wifi_bt_module_config component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/wifi_bt_module/incl +) + + +endif() + + +if (CONFIG_USE_DEVICES_Project_Template_MCXN236) +# Add set(CONFIG_USE_DEVICES_Project_Template_MCXN236 true) in config.cmake to use this component + +message("DEVICES_Project_Template_MCXN236 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_lpuart_adapter AND CONFIG_USE_driver_lpuart AND CONFIG_USE_driver_gpio AND CONFIG_USE_driver_port AND CONFIG_USE_driver_reset AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_device_MCXN236_startup AND CONFIG_USE_driver_common AND CONFIG_USE_driver_clock AND ((CONFIG_USE_component_serial_manager AND CONFIG_USE_driver_lpflexcomm AND CONFIG_USE_utility_debug_console AND CONFIG_USE_utility_assert) OR (CONFIG_USE_utility_debug_console_lite AND CONFIG_USE_utility_assert_lite))) + +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.h "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/board.c "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.h "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/clock_config.c "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.h "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/pin_mux.c "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.h "" DEVICES_Project_Template_MCXN236.MCXN236) +add_config_file(${CMAKE_CURRENT_LIST_DIR}/project_template/peripherals.c "" DEVICES_Project_Template_MCXN236.MCXN236) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/project_template/. +) + +else() + +message(SEND_ERROR "DEVICES_Project_Template_MCXN236.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_device_MCXN236_startup) +# Add set(CONFIG_USE_device_MCXN236_startup true) in config.cmake to use this component + +message("device_MCXN236_startup component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_device_MCXN236_system) + +if(CONFIG_TOOLCHAIN STREQUAL armgcc) + add_config_file(${CMAKE_CURRENT_LIST_DIR}/./gcc/startup_MCXN236.S "" device_MCXN236_startup.MCXN236) +endif() + +if(CONFIG_TOOLCHAIN STREQUAL mcux) + add_config_file(${CMAKE_CURRENT_LIST_DIR}/./mcuxpresso/startup_mcxn236.c "" device_MCXN236_startup.MCXN236) + add_config_file(${CMAKE_CURRENT_LIST_DIR}/./mcuxpresso/startup_mcxn236.cpp "" device_MCXN236_startup.MCXN236) +endif() + +else() + +message(SEND_ERROR "device_MCXN236_startup.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_device_MCXN236_CMSIS) +# Add set(CONFIG_USE_device_MCXN236_CMSIS true) in config.cmake to use this component + +message("device_MCXN236_CMSIS component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_CMSIS_Include_core_cm) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "device_MCXN236_CMSIS.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_RTE_Device) +# Add set(CONFIG_USE_RTE_Device true) in config.cmake to use this component + +message("RTE_Device component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236)) + +add_config_file(${CMAKE_CURRENT_LIST_DIR}/template/RTE_Device.h "" RTE_Device.MCXN236) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/template/. +) + +else() + +message(SEND_ERROR "RTE_Device.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager_uart) +# Add set(CONFIG_USE_component_serial_manager_uart true) in config.cmake to use this component + +message("component_serial_manager_uart component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_lpuart_adapter AND CONFIG_USE_component_serial_manager AND (CONFIG_USE_driver_lpuart)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_port_uart.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSERIAL_PORT_TYPE_UART=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_serial_manager_uart.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_clock) +# Add set(CONFIG_USE_driver_clock true) in config.cmake to use this component + +message("driver_clock component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_mcx_spc AND CONFIG_USE_driver_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/drivers/fsl_clock.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/drivers/. +) + +else() + +message(SEND_ERROR "driver_clock.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_edma4) +# Add set(CONFIG_USE_driver_edma4 true) in config.cmake to use this component + +message("driver_edma4 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma_soc AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/edma4/fsl_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/edma4/. +) + +else() + +message(SEND_ERROR "driver_edma4.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_edma_soc) +# Add set(CONFIG_USE_driver_edma_soc true) in config.cmake to use this component + +message("driver_edma_soc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/drivers/fsl_edma_soc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/drivers/. +) + +else() + +message(SEND_ERROR "driver_edma_soc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_mculcd_edma) +# Add set(CONFIG_USE_driver_flexio_mculcd_edma true) in config.cmake to use this component + +message("driver_flexio_mculcd_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_flexio_mculcd AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/. +) + +else() + +message(SEND_ERROR "driver_flexio_mculcd_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_mculcd_smartdma) +# Add set(CONFIG_USE_driver_flexio_mculcd_smartdma true) in config.cmake to use this component + +message("driver_flexio_mculcd_smartdma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_lpc_smartdma AND CONFIG_USE_driver_flexio_mculcd) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/. +) + +else() + +message(SEND_ERROR "driver_flexio_mculcd_smartdma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_sai_edma) +# Add set(CONFIG_USE_driver_sai_edma true) in config.cmake to use this component + +message("driver_sai_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_sai AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai/fsl_sai_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai/. +) + +else() + +message(SEND_ERROR "driver_sai_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpuart_edma) +# Add set(CONFIG_USE_driver_lpuart_edma true) in config.cmake to use this component + +message("driver_lpuart_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpuart/. +) + +else() + +message(SEND_ERROR "driver_lpuart_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpspi_edma) +# Add set(CONFIG_USE_driver_lpspi_edma true) in config.cmake to use this component + +message("driver_lpspi_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_lpspi AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpspi/. +) + +else() + +message(SEND_ERROR "driver_lpspi_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpi2c_edma) +# Add set(CONFIG_USE_driver_lpi2c_edma true) in config.cmake to use this component + +message("driver_lpi2c_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_lpi2c AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpi2c/. +) + +else() + +message(SEND_ERROR "driver_lpi2c_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cmsis_lpuart) +# Add set(CONFIG_USE_driver_cmsis_lpuart true) in config.cmake to use this component + +message("driver_cmsis_lpuart component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_lpuart_edma AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_lpuart AND CONFIG_USE_CMSIS_Driver_Include_USART AND CONFIG_USE_RTE_Device) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpuart/fsl_lpuart_cmsis.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpuart/. +) + +else() + +message(SEND_ERROR "driver_cmsis_lpuart.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cmsis_lpspi) +# Add set(CONFIG_USE_driver_cmsis_lpspi true) in config.cmake to use this component + +message("driver_cmsis_lpspi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_lpspi_edma AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_lpspi AND CONFIG_USE_CMSIS_Driver_Include_SPI AND CONFIG_USE_RTE_Device) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpspi/fsl_lpspi_cmsis.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpspi/. +) + +else() + +message(SEND_ERROR "driver_cmsis_lpspi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cmsis_lpi2c) +# Add set(CONFIG_USE_driver_cmsis_lpi2c true) in config.cmake to use this component + +message("driver_cmsis_lpi2c component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_lpi2c_edma AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_lpi2c AND CONFIG_USE_CMSIS_Driver_Include_I2C AND CONFIG_USE_RTE_Device) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpi2c/fsl_lpi2c_cmsis.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../cmsis_drivers/lpi2c/. +) + +else() + +message(SEND_ERROR "driver_cmsis_lpi2c.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexcan_edma) +# Add set(CONFIG_USE_driver_flexcan_edma true) in config.cmake to use this component + +message("driver_flexcan_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_flexcan AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan/fsl_flexcan_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan/. +) + +else() + +message(SEND_ERROR "driver_flexcan_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_spi_edma) +# Add set(CONFIG_USE_driver_flexio_spi_edma true) in config.cmake to use this component + +message("driver_flexio_spi_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_flexio_spi AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/spi/fsl_flexio_spi_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/spi/. +) + +else() + +message(SEND_ERROR "driver_flexio_spi_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_uart_edma) +# Add set(CONFIG_USE_driver_flexio_uart_edma true) in config.cmake to use this component + +message("driver_flexio_uart_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_flexio_uart AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/uart/fsl_flexio_uart_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/uart/. +) + +else() + +message(SEND_ERROR "driver_flexio_uart_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_pdm_edma) +# Add set(CONFIG_USE_driver_pdm_edma true) in config.cmake to use this component + +message("driver_pdm_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_edma4 AND CONFIG_USE_driver_pdm AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pdm/fsl_pdm_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pdm/. +) + +else() + +message(SEND_ERROR "driver_pdm_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_notifier) +# Add set(CONFIG_USE_utility_notifier true) in config.cmake to use this component + +message("utility_notifier component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/notifier/fsl_notifier.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/notifier/. +) + +else() + +message(SEND_ERROR "utility_notifier.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_inputmux_connections) +# Add set(CONFIG_USE_driver_inputmux_connections true) in config.cmake to use this component + +message("driver_inputmux_connections component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/drivers/. +) + +else() + +message(SEND_ERROR "driver_inputmux_connections.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_common) +# Add set(CONFIG_USE_driver_common true) in config.cmake to use this component + +message("driver_common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_reset AND CONFIG_USE_driver_clock AND CONFIG_USE_device_MCXN236_CMSIS) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common/fsl_common.c +) + +if(CONFIG_CORE STREQUAL cm33) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common/fsl_common_arm.c + ) +endif() + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common/. +) + +else() + +message(SEND_ERROR "driver_common.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_assert) +# Add set(CONFIG_USE_utility_assert true) in config.cmake to use this component + +message("utility_assert component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_utility_debug_console AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/assert/fsl_assert.c +) + +else() + +message(SEND_ERROR "utility_assert.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_assert_lite) +# Add set(CONFIG_USE_utility_assert_lite true) in config.cmake to use this component + +message("utility_assert_lite component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_utility_debug_console_lite AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/assert/fsl_assert.c +) + +else() + +message(SEND_ERROR "utility_assert_lite.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_str) +# Add set(CONFIG_USE_utility_str true) in config.cmake to use this component + +message("utility_str component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str/fsl_str.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str +) + +else() + +message(SEND_ERROR "utility_str.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_debug_console_lite) +# Add set(CONFIG_USE_utility_debug_console_lite true) in config.cmake to use this component + +message("utility_debug_console_lite component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str/fsl_str.c + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/debug_console_lite/fsl_debug_console.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/debug_console_lite +) + +else() + +message(SEND_ERROR "utility_debug_console_lite.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_debug_console) +# Add set(CONFIG_USE_utility_debug_console true) in config.cmake to use this component + +message("utility_debug_console component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_serial_manager AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str/fsl_str.c + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/debug_console/fsl_debug_console.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/str + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/debug_console +) + +else() + +message(SEND_ERROR "utility_debug_console.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_device_MCXN236_system) +# Add set(CONFIG_USE_device_MCXN236_system true) in config.cmake to use this component + +message("device_MCXN236_system component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_device_MCXN236_CMSIS) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./system_MCXN236.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./. +) + +else() + +message(SEND_ERROR "device_MCXN236_system.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_rtt) +# Add set(CONFIG_USE_driver_rtt true) in config.cmake to use this component + +message("driver_rtt component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_rtt_template) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/RTT/SEGGER_RTT.c + ${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/RTT/SEGGER_RTT_printf.c +) + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/Syscalls/SEGGER_RTT_Syscalls_GCC.c + ) +endif() + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/rtt/RTT +) + +else() + +message(SEND_ERROR "driver_rtt.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_tdet) +# Add set(CONFIG_USE_driver_tdet true) in config.cmake to use this component + +message("driver_tdet component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/tdet/fsl_tdet.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/tdet/. +) + +else() + +message(SEND_ERROR "driver_tdet.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_syspm) +# Add set(CONFIG_USE_driver_syspm true) in config.cmake to use this component + +message("driver_syspm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/syspm/fsl_syspm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/syspm/. +) + +else() + +message(SEND_ERROR "driver_syspm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_puf_v3) +# Add set(CONFIG_USE_driver_puf_v3 true) in config.cmake to use this component + +message("driver_puf_v3 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/puf_v3/fsl_puf_v3.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/puf_v3/. +) + +else() + +message(SEND_ERROR "driver_puf_v3.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpcmp) +# Add set(CONFIG_USE_driver_lpcmp true) in config.cmake to use this component + +message("driver_lpcmp component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpcmp/fsl_lpcmp.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpcmp/. +) + +else() + +message(SEND_ERROR "driver_lpcmp.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_vref_1) +# Add set(CONFIG_USE_driver_vref_1 true) in config.cmake to use this component + +message("driver_vref_1 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/vref_1/fsl_vref.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/vref_1/. +) + +else() + +message(SEND_ERROR "driver_vref_1.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpadc) +# Add set(CONFIG_USE_driver_lpadc true) in config.cmake to use this component + +message("driver_lpadc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpadc/fsl_lpadc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpadc/. +) + +else() + +message(SEND_ERROR "driver_lpadc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_itrc) +# Add set(CONFIG_USE_driver_itrc true) in config.cmake to use this component + +message("driver_itrc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/itrc/fsl_itrc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/itrc/. +) + +else() + +message(SEND_ERROR "driver_itrc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_intm) +# Add set(CONFIG_USE_driver_intm true) in config.cmake to use this component + +message("driver_intm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/intm/fsl_intm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/intm/. +) + +else() + +message(SEND_ERROR "driver_intm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_dbi) +# Add set(CONFIG_USE_driver_dbi true) in config.cmake to use this component + +message("driver_dbi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/display/dbi/. +) + +else() + +message(SEND_ERROR "driver_dbi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_dbi_flexio_edma) +# Add set(CONFIG_USE_driver_dbi_flexio_edma true) in config.cmake to use this component + +message("driver_dbi_flexio_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_dbi AND CONFIG_USE_driver_flexio_mculcd AND CONFIG_USE_driver_flexio_mculcd_edma) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/display/dbi/flexio/fsl_dbi_flexio_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/display/dbi/flexio/. +) + +else() + +message(SEND_ERROR "driver_dbi_flexio_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mcx_cmc) +# Add set(CONFIG_USE_driver_mcx_cmc true) in config.cmake to use this component + +message("driver_mcx_cmc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_cmc/fsl_cmc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_cmc/. +) + +else() + +message(SEND_ERROR "driver_mcx_cmc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_eim) +# Add set(CONFIG_USE_driver_eim true) in config.cmake to use this component + +message("driver_eim component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/eim/fsl_eim.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/eim/. +) + +else() + +message(SEND_ERROR "driver_eim.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_erm) +# Add set(CONFIG_USE_driver_erm true) in config.cmake to use this component + +message("driver_erm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/erm/fsl_erm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/erm/. +) + +else() + +message(SEND_ERROR "driver_erm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mcx_vbat) +# Add set(CONFIG_USE_driver_mcx_vbat true) in config.cmake to use this component + +message("driver_mcx_vbat component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_vbat/fsl_vbat.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_vbat/. +) + +else() + +message(SEND_ERROR "driver_mcx_vbat.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mcx_spc) +# Add set(CONFIG_USE_driver_mcx_spc true) in config.cmake to use this component + +message("driver_mcx_spc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_spc/fsl_spc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_spc/. +) + +else() + +message(SEND_ERROR "driver_mcx_spc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_crc) +# Add set(CONFIG_USE_driver_crc true) in config.cmake to use this component + +message("driver_crc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/crc/fsl_crc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/crc/. +) + +else() + +message(SEND_ERROR "driver_crc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cdog) +# Add set(CONFIG_USE_driver_cdog true) in config.cmake to use this component + +message("driver_cdog component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cdog/fsl_cdog.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cdog/. +) + +else() + +message(SEND_ERROR "driver_cdog.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cache_lpcac) +# Add set(CONFIG_USE_driver_cache_lpcac true) in config.cmake to use this component + +message("driver_cache_lpcac component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cache/lpcac_n4a_mcxn/. +) + +else() + +message(SEND_ERROR "driver_cache_lpcac.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpc_smartdma) +# Add set(CONFIG_USE_driver_lpc_smartdma true) in config.cmake to use this component + +message("driver_lpc_smartdma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/smartdma/fsl_smartdma.c + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/smartdma/fsl_smartdma_rt500.c + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/smartdma/fsl_smartdma_mcxn.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/smartdma/. +) + +else() + +message(SEND_ERROR "driver_lpc_smartdma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_reset) +# Add set(CONFIG_USE_driver_reset true) in config.cmake to use this component + +message("driver_reset component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/drivers/fsl_reset.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/drivers/. +) + +else() + +message(SEND_ERROR "driver_reset.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_audio_sai_edma_adapter) +# Add set(CONFIG_USE_component_audio_sai_edma_adapter true) in config.cmake to use this component + +message("component_audio_sai_edma_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_sai_edma) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/audio/fsl_adapter_sai.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/audio/. +) + +else() + +message(SEND_ERROR "component_audio_sai_edma_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_button) +# Add set(CONFIG_USE_component_button true) in config.cmake to use this component + +message("component_button component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_timer_manager AND (CONFIG_USE_component_gpio_adapter)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/button/fsl_component_button.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/button/. +) + +else() + +message(SEND_ERROR "component_button.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_codec) +# Add set(CONFIG_USE_driver_codec true) in config.cmake to use this component + +message("driver_codec component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_USE_component_wm8904_adapter OR CONFIG_USE_component_wm8960_adapter OR CONFIG_USE_component_sgtl_adapter OR CONFIG_USE_component_da7212_adapter OR CONFIG_USE_component_cs42888_adapter OR CONFIG_USE_component_codec_adapters)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/fsl_codec_common.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + ) + +endif() + +else() + +message(SEND_ERROR "driver_codec.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_codec_adapters) +# Add set(CONFIG_USE_component_codec_adapters true) in config.cmake to use this component + +message("component_codec_adapters component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_USE_driver_codec AND CONFIG_USE_component_wm8904_adapter) OR (CONFIG_USE_driver_codec AND CONFIG_USE_component_wm8960_adapter) OR (CONFIG_USE_driver_codec AND CONFIG_USE_component_sgtl_adapter) OR (CONFIG_USE_driver_codec AND CONFIG_USE_component_da7212_adapter) OR (CONFIG_USE_driver_codec AND CONFIG_USE_component_cs42888_adapter)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/fsl_codec_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DCODEC_MULTI_ADAPTERS=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_codec_adapters.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_wm8904_adapter) +# Add set(CONFIG_USE_component_wm8904_adapter true) in config.cmake to use this component + +message("component_wm8904_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_wm8904 AND CONFIG_USE_driver_codec) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/wm8904/fsl_codec_wm8904_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/wm8904 + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +else() + +message(SEND_ERROR "component_wm8904_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_wm8960_adapter) +# Add set(CONFIG_USE_component_wm8960_adapter true) in config.cmake to use this component + +message("component_wm8960_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_wm8960 AND CONFIG_USE_driver_codec) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/wm8960/fsl_codec_wm8960_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/wm8960 + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +else() + +message(SEND_ERROR "component_wm8960_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_cs42888_adapter) +# Add set(CONFIG_USE_component_cs42888_adapter true) in config.cmake to use this component + +message("component_cs42888_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_cs42888 AND CONFIG_USE_driver_codec) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/cs42888/fsl_codec_cs42888_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/cs42888 + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +else() + +message(SEND_ERROR "component_cs42888_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_sgtl_adapter) +# Add set(CONFIG_USE_component_sgtl_adapter true) in config.cmake to use this component + +message("component_sgtl_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_sgtl5000 AND CONFIG_USE_driver_codec) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/sgtl5000/fsl_codec_sgtl_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/sgtl5000 + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +else() + +message(SEND_ERROR "component_sgtl_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_da7212_adapter) +# Add set(CONFIG_USE_component_da7212_adapter true) in config.cmake to use this component + +message("component_da7212_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_dialog7212 AND CONFIG_USE_driver_codec) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/da7212/fsl_codec_da7212_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port/da7212 + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/port +) + +else() + +message(SEND_ERROR "component_da7212_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_codec_i2c) +# Add set(CONFIG_USE_component_codec_i2c true) in config.cmake to use this component + +message("component_codec_i2c component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_USE_component_lpi2c_adapter OR CONFIG_USE_component_i3c_adapter)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/i2c/fsl_codec_i2c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/i2c/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_codec_i2c.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_crc_adapter) +# Add set(CONFIG_USE_component_crc_adapter true) in config.cmake to use this component + +message("component_crc_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_crc) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/crc/fsl_adapter_crc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/crc/. +) + +else() + +message(SEND_ERROR "component_crc_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_software_crc_adapter) +# Add set(CONFIG_USE_component_software_crc_adapter true) in config.cmake to use this component + +message("component_software_crc_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/crc/fsl_adapter_software_crc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/crc/. +) + +else() + +message(SEND_ERROR "component_software_crc_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_cs42888) +# Add set(CONFIG_USE_driver_cs42888 true) in config.cmake to use this component + +message("driver_cs42888 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_codec_i2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/cs42888/fsl_cs42888.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/cs42888/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + -DCODEC_CS42888_ENABLE + ) + +endif() + +else() + +message(SEND_ERROR "driver_cs42888.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_dialog7212) +# Add set(CONFIG_USE_driver_dialog7212 true) in config.cmake to use this component + +message("driver_dialog7212 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_codec_i2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/da7212/fsl_dialog7212.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/da7212/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + -DBOARD_USE_CODEC=1 + -DCODEC_DA7212_ENABLE + ) + +endif() + +else() + +message(SEND_ERROR "driver_dialog7212.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_nor_flash-controller-lpspi) +# Add set(CONFIG_USE_driver_nor_flash-controller-lpspi true) in config.cmake to use this component + +message("driver_nor_flash-controller-lpspi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_nor_flash-common AND CONFIG_USE_driver_lpspi) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/nor/lpspi/fsl_lpspi_nor_flash.c + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/nor/lpspi/fsl_lpspi_mem_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/nor/lpspi/. +) + +else() + +message(SEND_ERROR "driver_nor_flash-controller-lpspi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_gt911) +# Add set(CONFIG_USE_driver_gt911 true) in config.cmake to use this component + +message("driver_gt911 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/gt911/fsl_gt911.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/gt911/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + ) + +endif() + +else() + +message(SEND_ERROR "driver_gt911.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ft5406_rt) +# Add set(CONFIG_USE_driver_ft5406_rt true) in config.cmake to use this component + +message("driver_ft5406_rt component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_lpi2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft5406_rt/fsl_ft5406_rt.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft5406_rt/. +) + +else() + +message(SEND_ERROR "driver_ft5406_rt.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ft5406) +# Add set(CONFIG_USE_driver_ft5406 true) in config.cmake to use this component + +message("driver_ft5406 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft5406/fsl_ft5406.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft5406/. +) + +else() + +message(SEND_ERROR "driver_ft5406.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ft6x06) +# Add set(CONFIG_USE_driver_ft6x06 true) in config.cmake to use this component + +message("driver_ft6x06 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_CMSIS_Driver_Include_I2C) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft6x06/fsl_ft6x06.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/ft6x06/. +) + +else() + +message(SEND_ERROR "driver_ft6x06.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_fxos8700cq) +# Add set(CONFIG_USE_driver_fxos8700cq true) in config.cmake to use this component + +message("driver_fxos8700cq component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/fxos8700cq/fsl_fxos.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/fxos8700cq/. +) + +else() + +message(SEND_ERROR "driver_fxos8700cq.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_gpio_adapter) +# Add set(CONFIG_USE_component_gpio_adapter true) in config.cmake to use this component + +message("component_gpio_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_gpio AND (CONFIG_USE_driver_port)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/gpio/fsl_adapter_gpio.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/gpio/. +) + +else() + +message(SEND_ERROR "component_gpio_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lpi2c_adapter) +# Add set(CONFIG_USE_component_lpi2c_adapter true) in config.cmake to use this component + +message("component_lpi2c_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpi2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c/fsl_adapter_lpi2c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c/. +) + +else() + +message(SEND_ERROR "component_lpi2c_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_i3c_adapter) +# Add set(CONFIG_USE_component_i3c_adapter true) in config.cmake to use this component + +message("component_i3c_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_i3c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c/fsl_adapter_i3c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I3C_BASED_COMPONENT_USED=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_i3c_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_i3c_bus) +# Add set(CONFIG_USE_component_i3c_bus true) in config.cmake to use this component + +message("component_i3c_bus component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/i3c_bus/fsl_component_i3c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/i3c_bus/. +) + +else() + +message(SEND_ERROR "component_i3c_bus.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_i3c_bus_adapter) +# Add set(CONFIG_USE_component_i3c_bus_adapter true) in config.cmake to use this component + +message("component_i3c_bus_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_i3c AND CONFIG_USE_component_i3c_bus) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/i3c_bus/fsl_component_i3c_adapter.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/i3c_bus/. +) + +else() + +message(SEND_ERROR "component_i3c_bus_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ili9341) +# Add set(CONFIG_USE_driver_ili9341 true) in config.cmake to use this component + +message("driver_ili9341 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/ili9341/fsl_ili9341.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/ili9341/. +) + +else() + +message(SEND_ERROR "driver_ili9341.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_led) +# Add set(CONFIG_USE_component_led true) in config.cmake to use this component + +message("component_led component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_timer_manager AND (CONFIG_USE_component_gpio_adapter)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/led/fsl_component_led.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/led/. +) + +else() + +message(SEND_ERROR "component_led.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lists) +# Add set(CONFIG_USE_component_lists true) in config.cmake to use this component + +message("component_lists component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/lists/fsl_component_generic_list.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/lists/. +) + +else() + +message(SEND_ERROR "component_lists.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_log) +# Add set(CONFIG_USE_component_log true) in config.cmake to use this component + +message("component_log component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_utility_str) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/fsl_component_log.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/. +) + +else() + +message(SEND_ERROR "component_log.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_log_backend_debugconsole) +# Add set(CONFIG_USE_component_log_backend_debugconsole true) in config.cmake to use this component + +message("component_log_backend_debugconsole component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_log AND CONFIG_USE_utility_debug_console) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/fsl_component_log_backend_debugconsole.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/. +) + +else() + +message(SEND_ERROR "component_log_backend_debugconsole.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_log_backend_debugconsole_lite) +# Add set(CONFIG_USE_component_log_backend_debugconsole_lite true) in config.cmake to use this component + +message("component_log_backend_debugconsole_lite component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_log AND CONFIG_USE_utility_debug_console_lite) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/fsl_component_log_backend_debugconsole.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/. +) + +else() + +message(SEND_ERROR "component_log_backend_debugconsole_lite.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_log_backend_ringbuffer) +# Add set(CONFIG_USE_component_log_backend_ringbuffer true) in config.cmake to use this component + +message("component_log_backend_ringbuffer component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_log) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/fsl_component_log_backend_ringbuffer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/log/. +) + +else() + +message(SEND_ERROR "component_log_backend_ringbuffer.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mem_manager) +# Add set(CONFIG_USE_component_mem_manager true) in config.cmake to use this component + +message("component_mem_manager component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/mem_manager/fsl_component_mem_manager.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/mem_manager/. +) + +else() + +message(SEND_ERROR "component_mem_manager.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mem_manager_light) +# Add set(CONFIG_USE_component_mem_manager_light true) in config.cmake to use this component + +message("component_mem_manager_light component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/mem_manager/fsl_component_mem_manager_light.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/mem_manager/. +) + +else() + +message(SEND_ERROR "component_mem_manager_light.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mflash_file) +# Add set(CONFIG_USE_component_mflash_file true) in config.cmake to use this component + +message("component_mflash_file component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_mflash_mcxnx4x_onchip) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/mflash_file.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/. +) + +else() + +message(SEND_ERROR "component_mflash_file.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mflash_dummy) +# Add set(CONFIG_USE_component_mflash_dummy true) in config.cmake to use this component + +message("component_mflash_dummy component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_mflash_file) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/mflash_dummy.c +) + +else() + +message(SEND_ERROR "component_mflash_dummy.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mflash_mcxnx4x_onchip) +# Add set(CONFIG_USE_component_mflash_mcxnx4x_onchip true) in config.cmake to use this component + +message("component_mflash_mcxnx4x_onchip component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_mflash_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_flashiap) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/mcxnx4x/mflash_drv.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/mcxnx4x/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DMFLASH_FILE_BASEADDR=131072 + ) + +endif() + +else() + +message(SEND_ERROR "component_mflash_mcxnx4x_onchip.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mma8451q) +# Add set(CONFIG_USE_driver_mma8451q true) in config.cmake to use this component + +message("driver_mma8451q component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/mma8451q/fsl_mma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/mma8451q/. +) + +else() + +message(SEND_ERROR "driver_mma8451q.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mma8652fc) +# Add set(CONFIG_USE_driver_mma8652fc true) in config.cmake to use this component + +message("driver_mma8652fc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/mma8652fc/fsl_mma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/mma8652fc/. +) + +else() + +message(SEND_ERROR "driver_mma8652fc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_panic) +# Add set(CONFIG_USE_component_panic true) in config.cmake to use this component + +message("component_panic component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/panic/fsl_component_panic.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/panic/. +) + +else() + +message(SEND_ERROR "component_panic.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_phy-device-lan8741) +# Add set(CONFIG_USE_driver_phy-device-lan8741 true) in config.cmake to use this component + +message("driver_phy-device-lan8741 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_phy-common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/device/phylan8741/fsl_phylan8741.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/device/phylan8741/. +) + +else() + +message(SEND_ERROR "driver_phy-device-lan8741.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_pwm_ctimer_adapter) +# Add set(CONFIG_USE_component_pwm_ctimer_adapter true) in config.cmake to use this component + +message("component_pwm_ctimer_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_ctimer) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/pwm/fsl_adapter_pwm_ctimer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/pwm/. +) + +else() + +message(SEND_ERROR "component_pwm_ctimer_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_reset_adapter) +# Add set(CONFIG_USE_component_reset_adapter true) in config.cmake to use this component + +message("component_reset_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/reset/fsl_adapter_reset.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/reset/. +) + +else() + +message(SEND_ERROR "component_reset_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_software_rng_adapter) +# Add set(CONFIG_USE_component_software_rng_adapter true) in config.cmake to use this component + +message("component_software_rng_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/rng/fsl_adapter_software_rng.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/rng/. +) + +else() + +message(SEND_ERROR "component_software_rng_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager) +# Add set(CONFIG_USE_component_serial_manager true) in config.cmake to use this component + +message("component_serial_manager component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists AND (CONFIG_USE_component_serial_manager_uart OR CONFIG_USE_component_serial_manager_usb_cdc OR CONFIG_USE_component_serial_manager_virtual OR CONFIG_USE_component_serial_manager_swo OR CONFIG_USE_component_serial_manager_spi)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_manager.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. +) + +else() + +message(SEND_ERROR "component_serial_manager.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager_spi) +# Add set(CONFIG_USE_component_serial_manager_spi true) in config.cmake to use this component + +message("component_serial_manager_spi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_serial_manager AND ((CONFIG_USE_driver_lpspi AND CONFIG_USE_component_lpspi_adapter))) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_port_spi.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSERIAL_PORT_TYPE_SPI=1 + -DSERIAL_PORT_TYPE_SPI_MASTER=1 + -DSERIAL_PORT_TYPE_SPI_SLAVE=1 + -DSERIAL_MANAGER_NON_BLOCKING_MODE=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_serial_manager_spi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager_usb_cdc) +# Add set(CONFIG_USE_component_serial_manager_usb_cdc true) in config.cmake to use this component + +message("component_serial_manager_usb_cdc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_serial_manager AND CONFIG_USE_middleware_usb_device_cdc_external AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_port_usb.c + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/usb_cdc_adapter/usb_device_descriptor.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/usb_cdc_adapter +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSERIAL_PORT_TYPE_USBCDC=1 + -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING + -DUSB_DEVICE_CONFIG_CDC_ACM=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_serial_manager_usb_cdc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager_virtual) +# Add set(CONFIG_USE_component_serial_manager_virtual true) in config.cmake to use this component + +message("component_serial_manager_virtual component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_serial_manager AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_port_virtual.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSERIAL_PORT_TYPE_VIRTUAL=1 + -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING + ) + +endif() + +else() + +message(SEND_ERROR "component_serial_manager_virtual.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_serial_manager_swo) +# Add set(CONFIG_USE_component_serial_manager_swo true) in config.cmake to use this component + +message("component_serial_manager_swo component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_CORE STREQUAL cm33) AND CONFIG_USE_driver_common AND CONFIG_USE_component_serial_manager) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/fsl_component_serial_port_swo.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSERIAL_PORT_TYPE_SWO=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_serial_manager_swo.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_sgtl5000) +# Add set(CONFIG_USE_driver_sgtl5000 true) in config.cmake to use this component + +message("driver_sgtl5000 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_codec_i2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/sgtl5000/fsl_sgtl5000.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/sgtl5000/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + -DBOARD_USE_CODEC=1 + -DCODEC_SGTL5000_ENABLE + ) + +endif() + +else() + +message(SEND_ERROR "driver_sgtl5000.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_utility_shell) +# Add set(CONFIG_USE_utility_shell true) in config.cmake to use this component + +message("utility_shell component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_utility_str AND CONFIG_USE_component_lists AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/shell/fsl_shell.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/shell/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DDEBUG_CONSOLE_RX_ENABLE=0 + ) + +endif() + +else() + +message(SEND_ERROR "utility_shell.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lpspi_adapter) +# Add set(CONFIG_USE_component_lpspi_adapter true) in config.cmake to use this component + +message("component_lpspi_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpspi) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/spi/fsl_adapter_lpspi.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/spi/. +) + +else() + +message(SEND_ERROR "component_lpspi_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_ctimer_adapter) +# Add set(CONFIG_USE_component_ctimer_adapter true) in config.cmake to use this component + +message("component_ctimer_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_ctimer) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/fsl_adapter_ctimer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/. +) + +else() + +message(SEND_ERROR "component_ctimer_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lptmr_adapter) +# Add set(CONFIG_USE_component_lptmr_adapter true) in config.cmake to use this component + +message("component_lptmr_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lptmr) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/fsl_adapter_lptmr.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/. +) + +else() + +message(SEND_ERROR "component_lptmr_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_mrt_adapter) +# Add set(CONFIG_USE_component_mrt_adapter true) in config.cmake to use this component + +message("component_mrt_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_mrt) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/fsl_adapter_mrt.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/. +) + +else() + +message(SEND_ERROR "component_mrt_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_ostimer_adapter) +# Add set(CONFIG_USE_component_ostimer_adapter true) in config.cmake to use this component + +message("component_ostimer_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_ostimer) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/fsl_adapter_ostimer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer/. +) + +else() + +message(SEND_ERROR "component_ostimer_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_timer_manager) +# Add set(CONFIG_USE_component_timer_manager true) in config.cmake to use this component + +message("component_timer_manager component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_lists AND (CONFIG_USE_component_ctimer_adapter OR CONFIG_USE_component_lptmr_adapter OR CONFIG_USE_component_mrt_adapter OR CONFIG_USE_component_ostimer_adapter)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer_manager/fsl_component_timer_manager.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/timer_manager/. +) + +else() + +message(SEND_ERROR "component_timer_manager.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lpuart_adapter) +# Add set(CONFIG_USE_component_lpuart_adapter true) in config.cmake to use this component + +message("component_lpuart_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpuart) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart/fsl_adapter_lpuart.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart/. +) + +else() + +message(SEND_ERROR "component_lpuart_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_component_lpuart_dma_adapter) +# Add set(CONFIG_USE_component_lpuart_dma_adapter true) in config.cmake to use this component + +message("component_lpuart_dma_adapter component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_component_lpuart_adapter AND CONFIG_USE_component_timer_manager AND (CONFIG_USE_driver_lpuart_edma)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart/fsl_adapter_lpuart.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DHAL_UART_DMA_ENABLE=1 + ) + +endif() + +else() + +message(SEND_ERROR "component_lpuart_dma_adapter.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_wm8904) +# Add set(CONFIG_USE_driver_wm8904 true) in config.cmake to use this component + +message("driver_wm8904 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_codec_i2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/wm8904/fsl_wm8904.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/wm8904/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + -DBOARD_USE_CODEC=1 + -DCODEC_WM8904_ENABLE + ) + +endif() + +else() + +message(SEND_ERROR "driver_wm8904.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_wm8960) +# Add set(CONFIG_USE_driver_wm8960 true) in config.cmake to use this component + +message("driver_wm8960 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_component_codec_i2c) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/wm8960/fsl_wm8960.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/codec/wm8960/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + -DBOARD_USE_CODEC=1 + -DCODEC_WM8960_ENABLE + ) + +endif() + +else() + +message(SEND_ERROR "driver_wm8960.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_st7796s) +# Add set(CONFIG_USE_driver_st7796s true) in config.cmake to use this component + +message("driver_st7796s component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_dbi) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/st7796s/fsl_st7796s.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/st7796s/. +) + +else() + +message(SEND_ERROR "driver_st7796s.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ssd1963) +# Add set(CONFIG_USE_driver_ssd1963 true) in config.cmake to use this component + +message("driver_ssd1963 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_dbi) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/ssd1963/fsl_ssd1963.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/ssd1963/. +) + +else() + +message(SEND_ERROR "driver_ssd1963.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_camera-receiver-common) +# Add set(CONFIG_USE_driver_camera-receiver-common true) in config.cmake to use this component + +message("driver_camera-receiver-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_video-common AND CONFIG_USE_driver_camera-common) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/receiver/. +) + +else() + +message(SEND_ERROR "driver_camera-receiver-common.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_camera-device-common) +# Add set(CONFIG_USE_driver_camera-device-common true) in config.cmake to use this component + +message("driver_camera-device-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_camera-common AND CONFIG_USE_driver_common) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/device/. +) + +else() + +message(SEND_ERROR "driver_camera-device-common.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_camera-device-sccb) +# Add set(CONFIG_USE_driver_camera-device-sccb true) in config.cmake to use this component + +message("driver_camera-device-sccb component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_USE_driver_lpi2c)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/device/sccb/fsl_sccb.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/device/sccb/. +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_I2C_BASED_COMPONENT_USED=1 + ) + +endif() + +else() + +message(SEND_ERROR "driver_camera-device-sccb.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_camera-device-ov7670) +# Add set(CONFIG_USE_driver_camera-device-ov7670 true) in config.cmake to use this component + +message("driver_camera-device-ov7670 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_video-common AND CONFIG_USE_driver_camera-common AND CONFIG_USE_driver_camera-device-common AND CONFIG_USE_driver_camera-device-sccb) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/device/ov7670/fsl_ov7670.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/device/ov7670/. +) + +else() + +message(SEND_ERROR "driver_camera-device-ov7670.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_camera-common) +# Add set(CONFIG_USE_driver_camera-common true) in config.cmake to use this component + +message("driver_camera-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_video-common) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/camera/. +) + +else() + +message(SEND_ERROR "driver_camera-common.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_video-common) +# Add set(CONFIG_USE_driver_video-common true) in config.cmake to use this component + +message("driver_video-common component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/fsl_video_common.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/. +) + +else() + +message(SEND_ERROR "driver_video-common.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_dbi_flexio_smartdma) +# Add set(CONFIG_USE_driver_dbi_flexio_smartdma true) in config.cmake to use this component + +message("driver_dbi_flexio_smartdma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_dbi AND CONFIG_USE_driver_flexio_mculcd AND CONFIG_USE_driver_flexio_mculcd_smartdma) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/display/dbi/flexio/fsl_dbi_flexio_smartdma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../components/video/display/dbi/flexio/. +) + +else() + +message(SEND_ERROR "driver_dbi_flexio_smartdma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flashiap) +# Add set(CONFIG_USE_driver_flashiap true) in config.cmake to use this component + +message("driver_flashiap component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/flash/src/fsl_flash.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/flash +) + +else() + +message(SEND_ERROR "driver_flashiap.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mem_interface) +# Add set(CONFIG_USE_driver_mem_interface true) in config.cmake to use this component + +message("driver_mem_interface component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/mem_interface/src/fsl_mem_interface.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/mem_interface + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/flash + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/nboot +) + +else() + +message(SEND_ERROR "driver_mem_interface.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_runbootloader) +# Add set(CONFIG_USE_driver_runbootloader true) in config.cmake to use this component + +message("driver_runbootloader component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/nboot/src/fsl_nboot.c + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/runbootloader/src/fsl_runbootloader.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/mem_interface + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/flash + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/nboot + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mcx_romapi/runbootloader +) + +else() + +message(SEND_ERROR "driver_runbootloader.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_wuu) +# Add set(CONFIG_USE_driver_wuu true) in config.cmake to use this component + +message("driver_wuu component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/wuu/fsl_wuu.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/wuu/. +) + +else() + +message(SEND_ERROR "driver_wuu.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_inputmux) +# Add set(CONFIG_USE_driver_inputmux true) in config.cmake to use this component + +message("driver_inputmux component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_inputmux_connections) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/inputmux/fsl_inputmux.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/inputmux/. +) + +else() + +message(SEND_ERROR "driver_inputmux.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ctimer) +# Add set(CONFIG_USE_driver_ctimer true) in config.cmake to use this component + +message("driver_ctimer component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ctimer/fsl_ctimer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ctimer/. +) + +else() + +message(SEND_ERROR "driver_ctimer.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_mrt) +# Add set(CONFIG_USE_driver_mrt true) in config.cmake to use this component + +message("driver_mrt component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mrt/fsl_mrt.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mrt/. +) + +else() + +message(SEND_ERROR "driver_mrt.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_wwdt) +# Add set(CONFIG_USE_driver_wwdt true) in config.cmake to use this component + +message("driver_wwdt component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/wwdt/fsl_wwdt.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/wwdt/. +) + +else() + +message(SEND_ERROR "driver_wwdt.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_utick) +# Add set(CONFIG_USE_driver_utick true) in config.cmake to use this component + +message("driver_utick component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/utick/fsl_utick.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/utick/. +) + +else() + +message(SEND_ERROR "driver_utick.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ostimer) +# Add set(CONFIG_USE_driver_ostimer true) in config.cmake to use this component + +message("driver_ostimer component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ostimer/fsl_ostimer.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ostimer/. +) + +else() + +message(SEND_ERROR "driver_ostimer.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_evtg) +# Add set(CONFIG_USE_driver_evtg true) in config.cmake to use this component + +message("driver_evtg component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/evtg/fsl_evtg.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/evtg/. +) + +else() + +message(SEND_ERROR "driver_evtg.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_pwm) +# Add set(CONFIG_USE_driver_pwm true) in config.cmake to use this component + +message("driver_pwm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pwm/fsl_pwm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pwm/. +) + +else() + +message(SEND_ERROR "driver_pwm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_qdc) +# Add set(CONFIG_USE_driver_qdc true) in config.cmake to use this component + +message("driver_qdc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/qdc/fsl_qdc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/qdc/. +) + +else() + +message(SEND_ERROR "driver_qdc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_irtc) +# Add set(CONFIG_USE_driver_irtc true) in config.cmake to use this component + +message("driver_irtc component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/irtc/fsl_irtc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/irtc/. +) + +else() + +message(SEND_ERROR "driver_irtc.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpc_freqme) +# Add set(CONFIG_USE_driver_lpc_freqme true) in config.cmake to use this component + +message("driver_lpc_freqme component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpc_freqme/fsl_freqme.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpc_freqme/. +) + +else() + +message(SEND_ERROR "driver_lpc_freqme.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lptmr) +# Add set(CONFIG_USE_driver_lptmr true) in config.cmake to use this component + +message("driver_lptmr component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lptmr/fsl_lptmr.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lptmr/. +) + +else() + +message(SEND_ERROR "driver_lptmr.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_ewm) +# Add set(CONFIG_USE_driver_ewm true) in config.cmake to use this component + +message("driver_ewm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ewm/fsl_ewm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/ewm/. +) + +else() + +message(SEND_ERROR "driver_ewm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpflexcomm) +# Add set(CONFIG_USE_driver_lpflexcomm true) in config.cmake to use this component + +message("driver_lpflexcomm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/fsl_lpflexcomm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/. +) + +else() + +message(SEND_ERROR "driver_lpflexcomm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpi2c) +# Add set(CONFIG_USE_driver_lpi2c true) in config.cmake to use this component + +message("driver_lpi2c component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpi2c/fsl_lpi2c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpi2c/. +) + +else() + +message(SEND_ERROR "driver_lpi2c.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpflexcomm_lpi2c_freertos) +# Add set(CONFIG_USE_driver_lpflexcomm_lpi2c_freertos true) in config.cmake to use this component + +message("driver_lpflexcomm_lpi2c_freertos component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm AND CONFIG_USE_driver_lpi2c AND CONFIG_USE_middleware_freertos-kernel) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/fsl_lpi2c_freertos.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/. +) + +else() + +message(SEND_ERROR "driver_lpflexcomm_lpi2c_freertos.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpspi) +# Add set(CONFIG_USE_driver_lpspi true) in config.cmake to use this component + +message("driver_lpspi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpspi/fsl_lpspi.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpspi/. +) + +else() + +message(SEND_ERROR "driver_lpspi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpflexcomm_lpspi_freertos) +# Add set(CONFIG_USE_driver_lpflexcomm_lpspi_freertos true) in config.cmake to use this component + +message("driver_lpflexcomm_lpspi_freertos component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm AND CONFIG_USE_driver_lpspi AND CONFIG_USE_middleware_freertos-kernel) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/fsl_lpspi_freertos.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/. +) + +else() + +message(SEND_ERROR "driver_lpflexcomm_lpspi_freertos.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpuart) +# Add set(CONFIG_USE_driver_lpuart true) in config.cmake to use this component + +message("driver_lpuart component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpuart/fsl_lpuart.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/lpuart/. +) + +else() + +message(SEND_ERROR "driver_lpuart.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_lpflexcomm_lpuart_freertos) +# Add set(CONFIG_USE_driver_lpflexcomm_lpuart_freertos true) in config.cmake to use this component + +message("driver_lpflexcomm_lpuart_freertos component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND CONFIG_USE_driver_lpflexcomm AND CONFIG_USE_driver_lpuart AND CONFIG_USE_middleware_freertos-kernel) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/fsl_lpuart_freertos.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpflexcomm/. +) + +else() + +message(SEND_ERROR "driver_lpflexcomm_lpuart_freertos.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_sai) +# Add set(CONFIG_USE_driver_sai true) in config.cmake to use this component + +message("driver_sai component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai/fsl_sai.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai/. +) + +else() + +message(SEND_ERROR "driver_sai.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexcan) +# Add set(CONFIG_USE_driver_flexcan true) in config.cmake to use this component + +message("driver_flexcan component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan/fsl_flexcan.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan/. +) + +else() + +message(SEND_ERROR "driver_flexcan.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio) +# Add set(CONFIG_USE_driver_flexio true) in config.cmake to use this component + +message("driver_flexio component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/fsl_flexio.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/. +) + +else() + +message(SEND_ERROR "driver_flexio.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_mculcd) +# Add set(CONFIG_USE_driver_flexio_mculcd true) in config.cmake to use this component + +message("driver_flexio_mculcd component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_flexio AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/fsl_flexio_mculcd.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/mculcd/. +) + +else() + +message(SEND_ERROR "driver_flexio_mculcd.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_i2c_master) +# Add set(CONFIG_USE_driver_flexio_i2c_master true) in config.cmake to use this component + +message("driver_flexio_i2c_master component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_flexio) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/i2c/fsl_flexio_i2c_master.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/i2c/. +) + +else() + +message(SEND_ERROR "driver_flexio_i2c_master.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_spi) +# Add set(CONFIG_USE_driver_flexio_spi true) in config.cmake to use this component + +message("driver_flexio_spi component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_flexio) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/spi/fsl_flexio_spi.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/spi/. +) + +else() + +message(SEND_ERROR "driver_flexio_spi.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_flexio_uart) +# Add set(CONFIG_USE_driver_flexio_uart true) in config.cmake to use this component + +message("driver_flexio_uart component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_flexio) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/uart/fsl_flexio_uart.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexio/uart/. +) + +else() + +message(SEND_ERROR "driver_flexio_uart.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_i3c_edma) +# Add set(CONFIG_USE_driver_i3c_edma true) in config.cmake to use this component + +message("driver_i3c_edma component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_i3c AND CONFIG_USE_driver_edma4) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/i3c/fsl_i3c_edma.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/i3c/. +) + +else() + +message(SEND_ERROR "driver_i3c_edma.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_i3c) +# Add set(CONFIG_USE_driver_i3c true) in config.cmake to use this component + +message("driver_i3c component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_driver_common AND (CONFIG_DEVICE_ID STREQUAL MCXN236)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/i3c/fsl_i3c.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/i3c/. +) + +else() + +message(SEND_ERROR "driver_i3c.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_gpio) +# Add set(CONFIG_USE_driver_gpio true) in config.cmake to use this component + +message("driver_gpio component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/gpio/fsl_gpio.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/gpio/. +) + +else() + +message(SEND_ERROR "driver_gpio.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_pint) +# Add set(CONFIG_USE_driver_pint true) in config.cmake to use this component + +message("driver_pint component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pint/fsl_pint.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pint/. +) + +else() + +message(SEND_ERROR "driver_pint.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_port) +# Add set(CONFIG_USE_driver_port true) in config.cmake to use this component + +message("driver_port component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/port/. +) + +else() + +message(SEND_ERROR "driver_port.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_driver_pdm) +# Add set(CONFIG_USE_driver_pdm true) in config.cmake to use this component + +message("driver_pdm component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_DEVICE_ID STREQUAL MCXN236) AND CONFIG_USE_driver_common) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pdm/fsl_pdm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/pdm/. +) + +else() + +message(SEND_ERROR "driver_pdm.MCXN236 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + diff --git a/devices/MCXN236/system_MCXN236.c b/devices/MCXN236/system_MCXN236.c new file mode 100644 index 000000000..11c0ff20f --- /dev/null +++ b/devices/MCXN236/system_MCXN236.c @@ -0,0 +1,128 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN236 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/devices/MCXN236/system_MCXN236.h b/devices/MCXN236/system_MCXN236.h new file mode 100644 index 000000000..2406a9790 --- /dev/null +++ b/devices/MCXN236/system_MCXN236.h @@ -0,0 +1,106 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN236 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN236_H_ +#define _SYSTEM_MCXN236_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN236_H_ */ diff --git a/devices/MCXN236/template/RTE_Device.h b/devices/MCXN236/template/RTE_Device.h new file mode 100644 index 000000000..7313b556b --- /dev/null +++ b/devices/MCXN236/template/RTE_Device.h @@ -0,0 +1,230 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +#include "pin_mux.h" + +/* UART Select, UART0-UART7. */ +/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART + * instance. */ +#define RTE_USART0 0 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 +#define RTE_USART6 0 +#define RTE_USART6_DMA_EN 0 +#define RTE_USART7 0 +#define RTE_USART7_DMA_EN 0 + +/* USART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 +#define USART6_RX_BUFFER_ENABLE 0 +#define USART7_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_PIN_INIT USART0_InitPins +#define RTE_USART0_PIN_DEINIT USART0_DeinitPins +#define RTE_USART0_DMA_TX_CH 5 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 4 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_PIN_INIT USART1_InitPins +#define RTE_USART1_PIN_DEINIT USART1_DeinitPins +#define RTE_USART1_DMA_TX_CH 7 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 6 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_PIN_INIT USART2_InitPins +#define RTE_USART2_PIN_DEINIT USART2_DeinitPins +#define RTE_USART2_DMA_TX_CH 8 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 9 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_PIN_INIT USART3_InitPins +#define RTE_USART3_PIN_DEINIT USART3_DeinitPins +#define RTE_USART3_DMA_TX_CH 10 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 11 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_PIN_INIT USART4_InitPins +#define RTE_USART4_PIN_DEINIT USART4_DeinitPins +#define RTE_USART4_DMA_TX_CH 13 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 12 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_PIN_INIT USART5_InitPins +#define RTE_USART5_PIN_DEINIT USART5_DeinitPins +#define RTE_USART5_DMA_TX_CH 15 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 14 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART6_PIN_INIT USART6_InitPins +#define RTE_USART6_PIN_DEINIT USART6_DeinitPins +#define RTE_USART6_DMA_TX_CH 17 +#define RTE_USART6_DMA_TX_DMA_BASE DMA0 +#define RTE_USART6_DMA_RX_CH 16 +#define RTE_USART6_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART7_PIN_INIT USART7_InitPins +#define RTE_USART7_PIN_DEINIT USART7_DeinitPins +#define RTE_USART7_DMA_TX_CH 19 +#define RTE_USART7_DMA_TX_DMA_BASE DMA0 +#define RTE_USART7_DMA_RX_CH 18 +#define RTE_USART7_DMA_RX_DMA_BASE DMA0 + +/* I2C Select, I2C0 -I2C7*/ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 +#define RTE_I2C5 0 +#define RTE_I2C5_DMA_EN 0 +#define RTE_I2C6 0 +#define RTE_I2C6_DMA_EN 0 +#define RTE_I2C7 0 +#define RTE_I2C7_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 1 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 3 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 5 + +#define RTE_I2C3_Master_DMA_BASE DMA0 +#define RTE_I2C3_Master_DMA_CH 7 + +#define RTE_I2C4_Master_DMA_BASE DMA0 +#define RTE_I2C4_Master_DMA_CH 9 + +#define RTE_I2C5_Master_DMA_BASE DMA0 +#define RTE_I2C5_Master_DMA_CH 11 + +#define RTE_I2C6_Master_DMA_BASE DMA0 +#define RTE_I2C6_Master_DMA_CH 13 + +#define RTE_I2C7_Master_DMA_BASE DMA0 +#define RTE_I2C7_Master_DMA_CH 15 + +/* SPI select, SPI0 - SPI7.*/ +/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. + */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 +#define RTE_SPI3 0 +#define RTE_SPI3_DMA_EN 0 +#define RTE_SPI4 0 +#define RTE_SPI4_DMA_EN 0 +#define RTE_SPI5 0 +#define RTE_SPI5_DMA_EN 0 +#define RTE_SPI6 0 +#define RTE_SPI6_DMA_EN 0 +#define RTE_SPI7 0 +#define RTE_SPI7_DMA_EN 0 + +/* SPI configuration. */ +#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI0_PIN_INIT SPI0_InitPins +#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins +#define RTE_SPI0_DMA_TX_CH 1 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI1_PIN_INIT SPI1_InitPins +#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins +#define RTE_SPI1_DMA_TX_CH 3 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 2 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI2_PIN_INIT SPI2_InitPins +#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins +#define RTE_SPI2_DMA_TX_CH 5 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 4 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI3_PIN_INIT SPI3_InitPins +#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins +#define RTE_SPI3_DMA_TX_CH 7 +#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI3_DMA_RX_CH 6 +#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI4_PIN_INIT SPI4_InitPins +#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins +#define RTE_SPI4_DMA_TX_CH 9 +#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI4_DMA_RX_CH 8 +#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI5_PIN_INIT SPI5_InitPins +#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins +#define RTE_SPI5_DMA_TX_CH 11 +#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI5_DMA_RX_CH 10 +#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI6_PIN_INIT SPI6_InitPins +#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins +#define RTE_SPI6_DMA_TX_CH 13 +#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI6_DMA_RX_CH 12 +#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI7_PIN_INIT SPI7_InitPins +#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins +#define RTE_SPI7_DMA_TX_CH 15 +#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI7_DMA_RX_CH 14 +#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 + +#endif /* _RTE_DEVICE_H */ diff --git a/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c b/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c new file mode 100644 index 000000000..31b4415e1 --- /dev/null +++ b/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.c @@ -0,0 +1,20 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache_lpcac.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ diff --git a/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.h b/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.h new file mode 100644 index 000000000..54dd1fd84 --- /dev/null +++ b/drivers/cache/lpcac_n4a_mcxn/fsl_cache_lpcac.h @@ -0,0 +1,184 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CACHE_LPCAC_H_ +#define FSL_CACHE_LPCAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_lpcac + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version */ +#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name cache control for the L1 low power cache controller + *@{ + */ + +/*! + * @brief Enables the processor code bus cache. + * + */ +static inline void L1CACHE_EnableCodeCache(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Disables the processor code bus cache. + * + */ +static inline void L1CACHE_DisableCodeCache(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Clears cache. + * + */ +static inline void L1CACHE_InvalidateCodeCache(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; +} + +/*! + * @brief Enables allocation. + * + */ +static inline void L1CACHE_EnableAllocation(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Disables allocation. + * + */ +static inline void L1CACHE_DisableAllocation(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Enables parity. + * + */ +static inline void L1CACHE_EnableParity(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +/*! + * @brief Disable parity. + * + */ +static inline void L1CACHE_DisableParity(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +#if defined(FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL) && FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL +/*! + * @brief Enables write through buffer. + * + */ +static inline void L1CACHE_EnableWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK; +} + +/*! + * @brief Disables write through buffer. + * + */ +static inline void L1CACHE_DisableWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK; +} + +/*! + * @brief Limits write through buffer. + * + */ +static inline void L1CACHE_LimitWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK; +} + +/*! + * @brief Unlimits write through buffer. + * + */ +static inline void L1CACHE_UnlimitParity(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK; +} + +/*! + * @brief Enables parity error report. + * + */ +static inline void L1CACHE_EnableParityErrorReport(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK; +} + +/*! + * @brief Disables parity error report. + * + */ +static inline void L1CACHE_DisableParityErrorReport(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK; +} + +/*! + * @brief Enables XOM(eXecute-Only-Memory) control. + * + */ +static inline void L1CACHE_EnableXOMControl(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK; +} + +/*! + * @brief Disables XOM(eXecute-Only-Memory) control. + * + */ +static inline void L1CACHE_DisableXOMControl(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK; +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CACHE_LPCAC_H_*/ diff --git a/drivers/cdog/fsl_cdog.c b/drivers/cdog/fsl_cdog.c index 02aac54c8..301dd0907 100644 --- a/drivers/cdog/fsl_cdog.c +++ b/drivers/cdog/fsl_cdog.c @@ -322,6 +322,25 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) } else { +/* load default values for CDOG->CONTROL before flags clear */ +#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0) + cdog_config_t default_conf; + + /* Initialize CDOG */ + CDOG_GetDefaultConfig(&default_conf); + + /* Write default value to CDOG->CONTROL*/ + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ +#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */ + base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | CDOG_FLAGS_POR_FLAG(0U); diff --git a/drivers/cdog/fsl_cdog.h b/drivers/cdog/fsl_cdog.h index 33a66e47d..924ac5684 100644 --- a/drivers/cdog/fsl_cdog.h +++ b/drivers/cdog/fsl_cdog.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CDOG_H_ -#define _FSL_CDOG_H_ +#ifndef FSL_CDOG_H_ +#define FSL_CDOG_H_ #include "fsl_common.h" @@ -334,4 +334,4 @@ uint32_t CDOG_ReadPersistent(CDOG_Type *base); /*! @}*/ /* end of group cdog */ -#endif /* _FSL_CDOG_H_ */ +#endif /* FSL_CDOG_H_ */ diff --git a/drivers/common/fsl_common.h b/drivers/common/fsl_common.h index 8b9790db3..6a0603737 100644 --- a/drivers/common/fsl_common.h +++ b/drivers/common/fsl_common.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ #include #include @@ -189,7 +189,7 @@ enum _status_groups kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ @@ -199,6 +199,7 @@ enum _status_groups kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ }; /*! \public @@ -317,4 +318,4 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); #include "fsl_common_arm.h" #endif -#endif /* _FSL_COMMON_H_ */ +#endif /* FSL_COMMON_H_ */ diff --git a/drivers/common/fsl_common_arm.c b/drivers/common/fsl_common_arm.c index 241005e92..45c7bb379 100644 --- a/drivers/common/fsl_common_arm.c +++ b/drivers/common/fsl_common_arm.c @@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base #define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) #elif defined(__ICCARM__) extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; extern uint32_t __VECTOR_TABLE[]; diff --git a/drivers/common/fsl_common_arm.h b/drivers/common/fsl_common_arm.h index 453e1f00d..e5004d703 100644 --- a/drivers/common/fsl_common_arm.h +++ b/drivers/common/fsl_common_arm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ /* * For CMSIS pack RTE. @@ -261,7 +261,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) += (val); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_SUB(addr, val) \ do \ @@ -270,7 +270,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) -= (val); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_SET(addr, bits) \ do \ @@ -279,7 +279,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) |= (bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ do \ @@ -288,7 +288,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) &= ~(bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ do \ @@ -297,7 +297,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) ^= (bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ do \ @@ -306,7 +306,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #endif /* @} */ @@ -839,4 +839,4 @@ uint32_t MSDK_GetCpuCycleCount(void); /*! @} */ -#endif /* _FSL_COMMON_ARM_H_ */ +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/drivers/crc/fsl_crc.c b/drivers/crc/fsl_crc.c index 037dd4168..f4e303be9 100644 --- a/drivers/crc/fsl_crc.c +++ b/drivers/crc/fsl_crc.c @@ -40,6 +40,10 @@ /*< Default is resutl type is final checksum */ #endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ +#if defined(CRC_RSTS) +#define CRC_RESETS_ARRAY CRC_RSTS +#endif + /*! @brief CRC type of transpose of read write data */ typedef enum _crc_transpose_type { @@ -65,9 +69,49 @@ typedef struct _crc_module_config crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ } crc_module_config_t; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +/*! + * @brief Get instance number for CRC module. + * + * @param base CRC peripheral base address + */ +static uint32_t CRC_GetInstance(CRC_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static uint32_t CRC_GetInstance(CRC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++) + { + if (s_crcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_crcBases)); + + return instance; +} +#endif /*! * @brief Returns transpose type for CRC protocol reflect in parameter. @@ -191,6 +235,11 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) /* ungate clock */ CLOCK_EnableClock(kCLOCK_Crc0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(CRC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]); +#endif + /* configure CRC module and write the seed */ if (config->crcResult == kCrcFinalChecksum) { diff --git a/drivers/crc/fsl_crc.h b/drivers/crc/fsl_crc.h index 04270b83d..8e1c29c6d 100644 --- a/drivers/crc/fsl_crc.h +++ b/drivers/crc/fsl_crc.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ +#ifndef FSL_CRC_H_ +#define FSL_CRC_H_ #include "fsl_common.h" @@ -22,12 +22,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CRC driver version. Version 2.0.3. +/*! @brief CRC driver version. Version 2.0.4. * - * Current version: 2.0.3 + * Current version: 2.0.4 * * Change log: * + * - Version 2.0.4 + * - Release peripheral from reset if necessary in init function. + * * - Version 2.0.3 * - Fix MISRA issues * @@ -37,7 +40,7 @@ * - Version 2.0.1 * - move DATA and DATALL macro definition from header file to source file */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ #ifndef CRC_DRIVER_CUSTOM_DEFAULTS @@ -175,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base); *@} */ -#endif /* _FSL_CRC_H_ */ +#endif /* FSL_CRC_H_ */ diff --git a/drivers/ctimer/fsl_ctimer.h b/drivers/ctimer/fsl_ctimer.h index 27b6906f0..713c15a77 100644 --- a/drivers/ctimer/fsl_ctimer.h +++ b/drivers/ctimer/fsl_ctimer.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ #include "fsl_common.h" @@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match /*! @}*/ -#endif /* _FSL_CTIMER_H_ */ +#endif /* FSL_CTIMER_H_ */ diff --git a/drivers/edma4/fsl_edma.c b/drivers/edma4/fsl_edma.c new file mode 100644 index 000000000..ae3132c14 --- /dev/null +++ b/drivers/edma4/fsl_edma.c @@ -0,0 +1,2224 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma.h" +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma4" +#endif +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#define CONVERT_TO_DMA_ADDRESS(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_Local2DMA)) +#else +#define CONVERT_TO_DMA_ADDRESS(addr) ((uint32_t)(addr)) +#endif +#if defined(DMA_RSTS_N) +#define EDMA_RESETS_ARRAY DMA_RSTS_N +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Map transfer width. + * + * @param width transfer width. + */ +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width); + +/*! + * @brief validate edma errata. + * + * @param base edma base address. + * @param tcd edma transfer content descriptor. + */ +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, const edma_tcd_t *tcd); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map EDMA instance number to base pointer. */ +static EDMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_edmaResets[] = EDMA_RESETS_ARRAY; +#endif + +/*! @brief Array to map EDMA instance number to IRQ number. */ +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each EDMA channel. */ +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_SOC_EDMA_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL]; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EDMA_GetInstance(EDMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) + { + if (s_edmaBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_edmaBases)); + + return instance; +} + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, const edma_tcd_t *tcd) +{ + status_t status = kStatus_Success; + /* errata 51327: to use scatter gather feature, NBYTES must be multiple of 8 */ + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(base) == 1U) + { + if ((tcd->NBYTES % 8U) != 0U) + { + assert(false); + status = kStatus_InvalidArgument; + } + } + + return status; +} +#endif + +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, const edma_tcd_t *tcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + edma_tcd_t *tcdRegs = EDMA_TCD_BASE(base, channel); + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if ((tcd->DLAST_SGA != 0U) && ((tcd->CSR & (uint16_t)DMA_CSR_ESG_MASK) != 0U) && + (EDMA_CheckErrata(base, tcd) != kStatus_Success)) + { + assert(false); + } +#endif + + /* Clear DONE bit first, otherwise ESG cannot be set */ + DMA_CLEAR_DONE_STATUS(base, channel); + + /* Push tcd into hardware TCD register */ + tcdRegs->SADDR = tcd->SADDR; + tcdRegs->SOFF = tcd->SOFF; + tcdRegs->ATTR = tcd->ATTR; + tcdRegs->NBYTES = tcd->NBYTES; + tcdRegs->SLAST = (uint32_t)tcd->SLAST; + tcdRegs->DADDR = tcd->DADDR; + tcdRegs->DOFF = tcd->DOFF; + tcdRegs->CITER = tcd->CITER; + tcdRegs->DLAST_SGA = (uint32_t)tcd->DLAST_SGA; + tcdRegs->CSR = tcd->CSR; + tcdRegs->BITER = tcd->BITER; +} + +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + + uint32_t tmpreg, i = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA peripheral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_edmaResets[EDMA_GetInstance(base)]); +#endif + +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + EDMA_BASE(base)->ERQ = 0U; + EDMA_BASE(base)->INT = 0xFFFFFFFFU; + EDMA_BASE(base)->ERR = 0xFFFFFFFFU; + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = EDMA_BASE(base)->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U)); + EDMA_BASE(base)->CR = tmpreg; +#else + tmpreg = EDMA_MP_BASE(base)->MP_CSR; +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_GMRC_MASK | DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_GMRC(config->enableMasterIdReplication) | DMA_MP_CSR_HAE(config->enableHaltOnError) | + DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | DMA_MP_CSR_EDBG(config->enableDebugMode) | + DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#else + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_HAE(config->enableHaltOnError) | DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | + DMA_MP_CSR_EDBG(config->enableDebugMode) | DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#endif + EDMA_MP_BASE(base)->MP_CSR = tmpreg; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + /* channel transfer configuration */ + for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) + { + if (config->channelConfig[i] != NULL) + { + EDMA_InitChannel(base, i, config->channelConfig[i]); + } + } +#endif +#endif +} + +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA peripheral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * brief EDMA Channel initialization + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param channelConfig pointer to user's eDMA channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig) +{ + assert(channelConfig != NULL); + + EDMA_SetChannelPreemptionConfig(base, channel, &channelConfig->channelPreemptionConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + EDMA_SetChannelSwapSize(base, channel, channelConfig->channelSwapSize); +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + EDMA_SetChannelMemoryAttribute(base, channel, channelConfig->channelWriteMemoryAttribute, + channelConfig->channelReadMemoryAttribute); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION + EDMA_SetChannelSignExtension(base, channel, channelConfig->channelDataSignExtensionBitPosition); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + EDMA_SetChannelAccessType(base, channel, channelConfig->channelAccessType); +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + if (0U != (uint32_t)channelConfig->channelRequestSource) + { + /* dma request source */ + EDMA_SetChannelMux(base, channel, (int32_t)channelConfig->channelRequestSource); + } +#endif + + /* master ID replication */ + EDMA_EnableChannelMasterIDReplication(base, channel, channelConfig->enableMasterIDReplication); +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + /* dma transfer security level */ + EDMA_SetChannelSecurityLevel(base, channel, channelConfig->securityLevel); +#endif + /* dma transfer protection level */ + EDMA_SetChannelProtectionLevel(base, channel, channelConfig->protectionLevel); +} +#endif + +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableRoundRobinArbitration = false; + + config->enableHaltOnError = true; + +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + config->enableContinuousLinkMode = false; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + config->enableMasterIdReplication = false; +#endif + + config->enableDebugMode = false; + + config->enableGlobalChannelLink = true; +} + +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* reset channel CSR */ + EDMA_ClearChannelStatusFlags(base, channel, (uint32_t)kEDMA_DoneFlag | (uint32_t)kEDMA_ErrorFlag); + /* reset channel TCD */ + EDMA_TcdReset(EDMA_TCD_BASE(base, channel)); +} + +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); + + EDMA_TcdSetTransferConfig(EDMA_TCD_BASE(base, channel), config, (edma_tcd_t *)CONVERT_TO_DMA_ADDRESS(nextTcd)); +} + +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_BASE(base, channel)->NBYTES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_BASE(base, channel)->NBYTES = tmpreg; +} + +/*! + * brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param base eDMA peripheral base address. + * param channel edma channel number. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_BASE(base, channel)->SLAST = (uint32_t)sourceOffset; + EDMA_TCD_BASE(base, channel)->DLAST_SGA = (uint32_t)destOffset; +} + +/*! + * brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number + * param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + bool tmpEnablePreemptAbility = config->enablePreemptAbility; + bool tmpEnablchannelPreemption = config->enableChannelPreemption; + uint8_t tmpChannelPriority = config->channelPriority; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + + volatile uint8_t *tmpReg = &EDMA_BASE(base)->DCHPRI3; + + ((volatile uint8_t *)tmpReg)[DMA_DCHPRI_INDEX(channel)] = + (DMA_DCHPRI0_DPA((true == tmpEnablePreemptAbility ? 0U : 1U)) | + DMA_DCHPRI0_ECP((true == tmpEnablchannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority)); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_PRI = DMA_CH_PRI_ECP(tmpEnablchannelPreemption) | + DMA_CH_PRI_DPA(tmpEnablePreemptAbility) | + DMA_CH_PRI_APL(tmpChannelPriority); +#endif +} + +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TcdSetChannelLink(EDMA_TCD_BASE(base, channel), type, linkedChannel); +} + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_BASE(base, channel)->CSR = + (uint16_t)((EDMA_TCD_BASE(base, channel)->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint16_t tmpreg = EDMA_TCD_BASE(base, channel)->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_BASE(base, channel)->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(1U); + tcd->BITER = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(config != NULL); + + EDMA_ConfigChannelSoftwareTCD(tcd, config); + + if (nextTcd != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Sets TCD fields according to the user's channel transfer configuration structure, see + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * param tcd Pointer to the TCD structure. + * param transfer channel transfer configuration pointer. + * + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer) +{ + assert(transfer != NULL); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert(((uint32_t)transfer->srcOffset % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert(((uint32_t)transfer->destOffset % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcAddrModulo))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->dstAddrModulo))) == 0U); + + uint16_t tmpreg; + + tcd->SADDR = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); + /* destination address */ + tcd->DADDR = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + + /* Source address signed offset */ + tcd->SOFF = (uint16_t)(transfer->srcOffset); + /* Destination address signed offset */ + tcd->DOFF = (uint16_t)(transfer->destOffset); + + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + tcd->NBYTES = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + } + else + { + tcd->NBYTES = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + } + + /* Current major iteration count */ + tcd->CITER = (uint16_t)(transfer->majorLoopCounts); + /* Starting major iteration count */ + tcd->BITER = (uint16_t)(transfer->majorLoopCounts); + /* reset CSR firstly */ + tcd->CSR = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (transfer->linkTCD != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + else + { + tcd->CSR &= ~(uint16_t)DMA_CSR_ESG_MASK; + tcd->DLAST_SGA = (uint32_t)transfer->dstMajorLoopOffset; + } + + /* configure interrupt/auto disable channel request */ + tcd->CSR |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + + /* Minor link config */ + if (transfer->enableChannelMinorLoopLink) + { + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + tcd->BITER = tmpreg; + } + /* Major link config */ + if (transfer->enableChannelMajorLoopLink) + { + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + } + + /* clear link relate field if no channel link enabled */ + if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) + { + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } + + /* major loop offset */ + tcd->SLAST = (uint32_t)transfer->srcMajorLoopOffset; + /* modulo feature */ + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +/*! + * brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param tcd A point to the TCD structure. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->SLAST = (uint32_t)sourceOffset; + tcd->DLAST_SGA = (uint32_t)destOffset; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint16_t tmpreg; + + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t remainingCount = 0; + + if (0U != DMA_GET_DONE_STATUS(base, channel)) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (0U != (EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_ELINK_MASK)) + { + remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT); + } + else + { + remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_CITER_MASK) >> + DMA_CITER_ELINKNO_CITER_SHIFT); + } + } + + return remainingCount; +} + +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Enable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_ENABLE_ERROR_INT(base, channel); + } + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_ENABLE_MAJOR_INT(base, channel); + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_ENABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Disable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_DISABLE_ERROR_INT(base, channel); + } + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_DISABLE_MAJOR_INT(base, channel); + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_DISABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= DMA_GET_DONE_STATUS(base, channel); + /* Get ERROR bit flag */ + retval |= (DMA_GET_ERROR_STATUS(base, channel) << 1U); + /* Get INT bit flag */ + retval |= (DMA_GET_INT_STATUS(base, channel) << 2U); + + return retval; +} + +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Clear DONE bit flag */ + if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) + { + DMA_CLEAR_DONE_STATUS(base, channel); + } + /* Clear ERROR bit flag */ + if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) + { + DMA_CLEAR_ERROR_STATUS(base, channel); + } + /* Clear INT bit flag */ + if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) + { + DMA_CLEAR_INT_STATUS(base, channel); + } +} + +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t edmaInstance; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->channel = channel; + + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + s_EDMAHandle[edmaInstance][channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + handle->tcdBase = EDMA_TCD_BASE(base, channel); + handle->channelBase = EDMA_CHANNEL_BASE(base, channel); + handle->base = base; + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = handle->tcdBase; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0U); + + /* Initialize tcd queue attribute. */ + /* header should initial as 1, since that it is used to point to the next TCD to be loaded into TCD memory, + * In EDMA driver IRQ handler, header will be used to calculate how many tcd has done, for example, + * If application submit 4 transfer request, A->B->C->D, + * when A finshed, the header is 0, C is the next TCD to be load, since B is already loaded, + * according to EDMA driver IRQ handler, tcdDone = C - A - header = 2 - header = 2, but actually only 1 TCD done, + * so the issue will be the wrong TCD done count will pass to application in first TCD interrupt. + * During first submit, the header should be assigned to 1, since 0 is current one and 1 is next TCD to be loaded, + * but software cannot know which submission is the first one, so assign 1 to header here. + */ + handle->header = 1; + handle->tcdUsed = 0; + handle->tcdSize = (int8_t)tcdSize; + handle->tcdPool = tcdPool; +} + +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width) +{ + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + + /* map width to register value */ + switch (width) + { + /* width 8bit */ + case 1U: + transferSize = kEDMA_TransferSize1Bytes; + break; + /* width 16bit */ + case 2U: + transferSize = kEDMA_TransferSize2Bytes; + break; + /* width 32bit */ + case 4U: + transferSize = kEDMA_TransferSize4Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + /* width 64bit */ + case 8U: + transferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + /* width 128bit */ + case 16U: + transferSize = kEDMA_TransferSize16Bytes; + break; +#endif + /* width 256bit */ + case 32U: + transferSize = kEDMA_TransferSize32Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + /* width 512bit */ + case 64U: + transferSize = kEDMA_TransferSize64Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + /* width 1024bit */ + case 128U: + transferSize = kEDMA_TransferSize128Bytes; + break; +#endif + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + return transferSize; +} + +/*! + * brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint8_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint8_t *)destAddr) % destWidth) == 0U); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->destAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)destAddr); + config->srcAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)srcAddr); + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + config->srcTransferSize = EDMA_TransferWidthMapping(srcWidth); + config->destTransferSize = EDMA_TransferWidthMapping(destWidth); + config->destOffset = destOffset; + config->srcOffset = srcOffset; + /* enable major interrupt by default */ + config->enabledInterruptMask = (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + + int16_t srcOffset = 0, destOffset = 0; + + switch (type) + { + case kEDMA_MemoryToMemory: + destOffset = (int16_t)destWidth; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_MemoryToPeripheral: + destOffset = 0; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_PeripheralToMemory: + destOffset = (int16_t)destWidth; + srcOffset = 0; + break; + case kEDMA_PeripheralToPeripheral: + destOffset = 0; + srcOffset = 0; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + EDMA_PrepareTransferConfig(config, srcAddr, srcWidth, srcOffset, destAddr, destWidth, destOffset, bytesEachRequest, + transferBytes); +} + +/*! + * brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param nextTcd eDMA transfer linked TCD address. + * + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint32_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint32_t *)destAddr) % destWidth) == 0U); + + edma_transfer_size_t srcTransferSize = EDMA_TransferWidthMapping(srcWidth), + destTransferSize = EDMA_TransferWidthMapping(srcWidth); + + /* Initializes the configure structure to zero. */ + EDMA_TcdReset(tcd); + + assert((bytesEachRequest % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert((bytesEachRequest % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)srcOffset % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)destOffset % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)srcAddr % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)destAddr % (1UL << ((uint32_t)destTransferSize))) == 0U); + + tcd->SADDR = CONVERT_TO_DMA_ADDRESS((uint32_t *)srcAddr); + /* destination address */ + tcd->DADDR = CONVERT_TO_DMA_ADDRESS((uint32_t *)destAddr); + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize); + + /* Source address signed offset */ + tcd->SOFF = (uint16_t)(srcOffset); + /* Destination address signed offset */ + tcd->DOFF = (uint16_t)(destOffset); + + tcd->NBYTES = DMA_NBYTES_MLOFFNO_NBYTES(bytesEachRequest); + + /* Current major iteration count */ + tcd->CITER = (uint16_t)(transferBytes / bytesEachRequest); + /* Starting major iteration count */ + tcd->BITER = (uint16_t)(transferBytes / bytesEachRequest); + /* reset CSR firstly */ + tcd->CSR = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + + /* configure interrupt/auto disable channel request, enable major interrupt by default */ + tcd->CSR |= (tcd->CSR & (~(uint16_t)kEDMA_ErrorInterruptEnable)) | (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 2. submit static link transfer, + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * 3. submit dynamic link transfer + * code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 4. submit loop transfer + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, const edma_tcd_t *tcd) +{ + assert(handle != NULL); + assert(handle->tcdBase != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((tcdRegs->CITER & DMA_CITER_ELINKNO_CITER_MASK) != (tcdRegs->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_InstallTCD(handle->base, handle->channel, tcd); + /* Enable auto disable request feature */ + EDMA_EnableAutoStopRequest(handle->base, handle->channel, true); + /* Enable major interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, kEDMA_MajorInterruptEnable); + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + (void)memcpy(&handle->tcdPool[currentTcd], tcd, sizeof(edma_tcd_t)); + + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + + if ((tcd->DLAST_SGA == 0U) || ((tcd->CSR & DMA_CSR_ESG_MASK) == 0U)) + { + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + } + + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(handle->tcdBase != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert(((config->srcTransferSize != kEDMA_TransferSize128Bytes) && + (config->destTransferSize != kEDMA_TransferSize128Bytes)) || + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#endif + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((tcdRegs->CITER & DMA_CITER_ELINKNO_CITER_MASK) != (tcdRegs->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_TcdSetTransferConfig(tcdRegs, config, NULL); + /* Enable auto disable request feature */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + tcdRegs->CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(handle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * note Application should check the return value of this function to avoid transfer request + * submit failed + * + * param handle eDMA handle pointer + * param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * retval #kStatus_Success It means submit transfer request succeed + * retval #kStatus_EDMA_Busy channel is in busy status + * retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount) +{ + assert(transfer != NULL); + assert(handle != NULL); + assert(handle->tcdPool != NULL); + + uint32_t i = 0U; + + if (handle->tcdSize < (int8_t)transferLoopCount) + { + return kStatus_InvalidArgument; + } + + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel service doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((handle->tcdBase->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((handle->tcdBase->CITER & DMA_CITER_ELINKNO_CITER_MASK) != + (handle->tcdBase->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + + (void)memset(handle->tcdPool, 0, (uint32_t)handle->tcdSize * sizeof(edma_tcd_t)); + for (i = 0U; i < transferLoopCount - 1UL; i++) + { + transfer[i].linkTCD = &handle->tcdPool[i + 1UL]; + EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &(handle->tcdPool[i])) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + } + + /* prepare last one in the ring and link it to the HEAD of the ring */ + transfer[i].linkTCD = &handle->tcdPool[0]; + EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_EnableMinorLoopMapping(handle->psBase, true); + } +#endif + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[0U]); + + /* enable interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, + ((uint32_t)transfer->enabledInterruptMask & ~((uint32_t)kEDMA_ErrorInterruptEnable))); + + return kStatus_Success; +} + +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + tmpCSR = tcdRegs->CSR; + if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK))) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +#else +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && handle->channelBase->CH_MUX == 0U) + { + tcdRegs->CSR |= DMA_CSR_START_MASK; + } + else +#endif + if (handle->tcdPool == NULL) + { + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + else + { + /* Check if channel request is actually disable. */ + if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) + { + /* Check if transfer is paused. */ + if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || + ((tcdRegs->CSR & DMA_CSR_ESG_MASK) != 0U)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + } + } +#endif +} + +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +#else + handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); +#endif +} + +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + EDMA_StopTransfer(handle); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + EDMA_TcdReset(handle->tcdBase); + + /* Handle the tcd */ + if (handle->tcdPool != NULL) + { + handle->header = 1; + handle->tail = 0; + handle->tcdUsed = 0; + } +} + +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + bool transfer_done; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + /* Check if transfer is already finished. */ + transfer_done = ((handle->tcdBase->CSR & DMA_CSR_DONE_MASK) != 0U); +#else + transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); +#endif + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((handle->base->INT >> channel) != 0U) + { + handle->base->CINT = channel; + } +#else + if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; + } +#endif + + if (handle->tcdPool == NULL) + { + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, transfer_done, 0); + } + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = (uint32_t)((edma_tcd_t *)(handle->tcdBase))->DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool esg = ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U); + + /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga -= CONVERT_TO_DMA_ADDRESS((uint32_t)handle->tcdPool); + /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = (uint8_t)sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == (uint8_t)handle->header) + { + int8_t tmpTcdUsed = handle->tcdUsed; + int8_t tmpTcdSize = handle->tcdSize; + + /* check esg here for the case that application submit only one request, once the request complete: + * new_header(1) = handle->header(1) + * tcdUsed(1) != tcdSize(>1) + * As the application submit only once, so scatter gather must not enabled, then tcds_done should be 1 + */ + if ((tmpTcdUsed == tmpTcdSize) || (!esg)) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = (int32_t)new_header - (int32_t)handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + /* + * While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware + * so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD + * overwritten. + */ + if (transfer_done) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = (int8_t)new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= (int8_t)tcds_done; + /* Invoke callback function. */ + if (NULL != handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + + /* + * 1.clear the DONE bit here is meaningful for below cases: + * A new TCD has been loaded to EDMA already: + * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten + * if peripheral request isn't coming before next transfer request. + * 2. Don't clear DONE bit for below case, + * for the case that transfer request submitted in the privious edma callback, this is a case that doesn't + * need scatter gather, so keep DONE bit during the next transfer request submission will re-install the TCD and + * the DONE bit will be cleared together with TCD re-installation. + */ + if (transfer_done) + { + if ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + } +} + +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((s_edmaBases[instance]->INT >> channel) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#else + if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#endif + SDK_ISR_EXIT_BARRIER; +} diff --git a/drivers/edma4/fsl_edma.h b/drivers/edma4/fsl_edma.h new file mode 100644 index 000000000..4cee503c8 --- /dev/null +++ b/drivers/edma4/fsl_edma.h @@ -0,0 +1,1593 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EDMA_H_ +#define FSL_EDMA_H_ + +#include "fsl_common.h" +#include "fsl_edma_core.h" +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 0)) /*!< Version 2.9.0. */ +/*@}*/ + +/*!@brief Macro used for allocate edma TCD */ +#define EDMA_ALLOCATE_TCD(name, number) AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t name[number], EDMA_TCD_ALIGN_SIZE) + +/*! @brief _edma_transfer_status eDMA transfer status */ +enum +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U))) + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ +#endif + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + kEDMA_TransferSize64Bytes = 0x6U, /*!< Source/Destination data transfer size is 64 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + kEDMA_TransferSize128Bytes = 0x7U, /*!< Source/Destination data transfer size is 128 bytes every time */ +#endif +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; +#endif + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief _edma_channel_status_flags eDMA channel status flags. */ +enum +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief _edma_error_status_flags eDMA channel error status flags. */ +enum +{ + kEDMA_DestinationBusErrorFlag = DMA_ERR_DBE_FLAG, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ERR_SBE_FLAG, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ERR_SGE_FLAG, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ERR_NCE_FLAG, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ERR_DOE_FLAG, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ERR_DAE_FLAG, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ERR_SOE_FLAG, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ERR_SAE_FLAG, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ERR_ERRCHAN_FLAG, /*!< Error channel number of the cancelled channel number */ +#if defined(FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR) && (FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR > 1) + kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG, /*!< Channel priority is not unique. */ +#endif + kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) + kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = (int)DMA_ERR_FLAG, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief _edma_interrupt_enable eDMA interrupt source */ +enum +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +}; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ + kEDMA_PeripheralToPeripheral, /*!< Transfer from Peripheral to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! @brief eDMA channel memory attribute */ +typedef enum edma_channel_memory_attribute +{ + kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer = + 0x0U, /*!< No write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteNoReadNoCacheBufferable, /*!< No write allocate, no read allocate, non-cacheable, bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableNoBuffer, /*!< No write allocate, no read allocate, cacheable, non-bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableBufferable, /*!< No write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheNoBuffer, /*!< No write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheBufferable, /*!< No write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadCacheableNoBuffer, /*!< No write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadCacheableBufferable, /*!< No write allocate, read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheNoBuffer, /*!< write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheBufferable, /*!< write allocate, no read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadCacheableNoBuffer, /*!< write allocate, no read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadCacheableBufferable, /*!< write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteReadNoCacheNoBuffer, /*!< write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadNoCacheBufferable, /*!< write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteReadCacheableNoBuffer, /*!< write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadCacheableBufferable, /*!< write allocate, read allocate, cacheable, bufferable. */ +} edma_channel_memory_attribute_t; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! @brief eDMA4 channel swap size */ +typedef enum _edma_channel_swap_size +{ + kEDMA_ChannelSwapDisabled = 0x0U, /*!< Swap is disabled. */ + kEDMA_ChannelReadWith8bitSwap = 0x1U, /*!< Swap occurs with respect to the read 8bit. */ + kEDMA_ChannelReadWith16bitSwap = 0x2U, /*!< Swap occurs with respect to the read 16bit. */ + kEDMA_ChannelReadWith32bitSwap = 0x3U, /*!< Swap occurs with respect to the read 32bit. */ + kEDMA_ChannelWriteWith8bitSwap = 0x9U, /*!< Swap occurs with respect to the write 8bit. */ + kEDMA_ChannelWriteWith16bitSwap = 0x10U, /*!< Swap occurs with respect to the write 16bit. */ + kEDMA_ChannelWriteWith32bitSwap = 0x11U, /*!< Swap occurs with respect to the write 32bit. */ +} edma_channel_swap_size_t; +#endif + +/*! @brief eDMA channel system bus information, _edma_channel_sys_bus_info*/ +enum +{ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) + kEDMA_AttributeOutput = DMA_CH_SBR_ATTR_MASK, /*!< DMA's AHB system bus attribute output value. */ +#endif + + kEDMA_PrivilegedAccessLevel = DMA_CH_SBR_PAL_MASK, /*!< Privileged Access Level for DMA transfers. 0b - User + protection level; 1b - Privileged protection level. */ + kEDMA_MasterId = + DMA_CH_SBR_MID_MASK, /*!< DMA's master ID when channel is active and master ID replication is enabled. */ +}; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! @brief eDMA4 channel access type */ +typedef enum _edma_channel_access_type +{ + kEDMA_ChannelDataAccess = 0x0U, /*!< Data access for eDMA4 transfers. */ + kEDMA_ChannelInstructionAccess = 0x1U, /*!< Instruction access for eDMA4 transfers. */ +} edma_channel_access_type_t; +#endif + +/*! @brief eDMA4 channel protection level */ +typedef enum _edma_channel_protection_level +{ + kEDMA_ChannelProtectionLevelUser = 0x0U, /*!< user protection level for eDMA transfers. */ + kEDMA_ChannelProtectionLevelPrivileged = 0x1U, /*!< Privileged protection level eDMA transfers. */ +} edma_channel_protection_level_t; + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + +/*! @brief eDMA4 channel security level */ +typedef enum _edma_channel_security_level +{ + kEDMA_ChannelSecurityLevelNonSecure = 0x0U, /*!< non secure level for eDMA transfers. */ + kEDMA_ChannelSecurityLevelSecure = 0x1U, /*!< secure level for eDMA transfers. */ +} edma_channel_security_level_t; +#endif + +/*! @brief eDMA4 channel configuration*/ +typedef struct _edma_channel_config +{ + edma_channel_Preemption_config_t channelPreemptionConfig; /*!< channel preemption configuration */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + edma_channel_memory_attribute_t channelReadMemoryAttribute; /*!< channel memory read attribute configuration */ + edma_channel_memory_attribute_t channelWriteMemoryAttribute; /*!< channel memory write attribute configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + edma_channel_swap_size_t channelSwapSize; /*!< channel swap size configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + edma_channel_access_type_t channelAccessType; /*!< channel access type configuration */ +#endif + + uint8_t channelDataSignExtensionBitPosition; /*!< channel data sign extension bit psition configuration */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + int channelRequestSource; /*!< hardware service request source for the channel */ +#endif + + bool enableMasterIDReplication; /*!< enable master ID replication */ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + edma_channel_security_level_t securityLevel; /*!< security level */ +#endif + edma_channel_protection_level_t protectionLevel; /*!< protection level */ + +} edma_channel_config_t; +#endif + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef edma_core_tcd_t edma_tcd_t; + +/*! @brief edma4 channel transfer configuration + * + * The transfer configuration structure support full feature configuration of the transfer control descriptor. + * + * @note User should pay attention to the transfer size alignment limitation + * 1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer + * that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0 + * 2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width + * 3. the totalBytes should align with the bytesEachRequest + * 4. the srcAddr should align with the srcWidthOfEachTransfer + * 5. the dstAddr should align with the dstWidthOfEachTransfer + * 6. the srcAddr should align with srcAddrModulo if modulo feature is enabled + * 7. the dstAddr should align with dstAddrModulo if modulo feature is enabled + * If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error. + * + * 1.To perform a simple transfer, below members should be initialized at least + * .srcAddr - source address + * .dstAddr - destination address + * .srcWidthOfEachTransfer - data width of source address + * .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as + * srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total + * bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as + * each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination + * address as each destination write is completed enablchannelRequest - channel request can be enabled together with + * transfer configure submission + * + * 2.The transfer configuration structure also support advance feature: + * Programmable source/destination address range(MODULO) + * Programmable minor loop offset + * Programmable major loop offset + * Programmable channel chain feature + * Programmable channel transfer control descriptor link feature + * + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset value in byte unit applied to the current source + address to form the next-state value as each source read is completed */ + int16_t destOffset; /*!< Sign-extended offset value in byte unit applied to the current destination + address to form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< bytes in each minor loop or each request + * range: 1 - (2^30 -1) when minor loop mapping is enabled + * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor + * loop offset is enabled + * range: 1 - (2^32 - 1) when minor loop mapping is disabled + */ + uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each + * transfer range: (0 - (2^15 - 1)) when minor loop channel link is + * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled + * total bytes in a transfer = minorLoopCountsEachMajorLoop * + * bytesEachMinorLoop + */ + + uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of _edma_interrupt_enable */ + + edma_modulo_t srcAddrModulo; /*!< source circular data queue range */ + int32_t srcMajorLoopOffset; /*!< source major loop offset */ + + edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */ + int32_t dstMajorLoopOffset; /*!< destination major loop offset */ + + bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */ + bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */ + int32_t minorLoopOffset; /*!< burst offset, the offset will be applied after minor loop update */ + + bool enableChannelMajorLoopLink; /*!< channel link when major loop complete */ + uint32_t majorLoopLinkChannel; /*!< major loop link channel number */ + + bool enableChannelMinorLoopLink; /*!< channel link when minor loop complete */ + uint32_t minorLoopLinkChannel; /*!< minor loop link channel number */ + + edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */ +} edma_transfer_config_t; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + bool enableMasterIdReplication; /*!< Enable (true) master ID replication. If Master ID replication is disabled, the + privileged protection level (supervisor mode) for eDMA4 transfers is used. */ +#endif + + bool enableGlobalChannelLink; /*!< Enable(true) channel linking is available and controlled by each channel's link + settings. */ + + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + + bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of + a new channel. Executing channels are allowed to complete. */ + + bool enableRoundRobinArbitration; /*!< Enable(true) channel linking is available and controlled by each channel's + link settings. */ +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + edma_channel_config_t *channelConfig[FSL_FEATURE_EDMA_MODULE_CHANNEL]; /*!< channel preemption configuration */ +#endif +} edma_config_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + EDMA_ChannelType *channelBase; /*!< eDMA peripheral channel base address. */ +#endif + EDMA_Type *base; /*!< eDMA peripheral base address*/ + EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */ + + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint32_t channel; /*!< eDMA channel number. */ + + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ +} edma_handle_t; +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base); + +/*! + * @brief Push content of TCD structure into hardware TCD register. + * + * @param base EDMA peripheral base address. + * @param channel EDMA channel number. + * @param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, const edma_tcd_t *tcd); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +#if defined(FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK) && FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK +/*! + * @brief Enable/Disable continuous channel link mode. + * + * @note Do not use continuous link mode with a channel linking to itself if there is only one minor loop + * iteration per service request, for example, if the channel's NBYTES value is the same as either + * the source or destination size. The same data transfer profile can be achieved by simply + * increasing the NBYTES value, which provides more efficient, faster processing. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableContinuousChannelLinkMode(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_CLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_CLM_MASK; + } +} +#endif + +#if defined(FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING) && FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING +/*! + * @brief Enable/Disable minor loop mapping. + * + * The TCDn.word2 is redefined to include individual enable fields, an offset field, and the + * NBYTES field. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_EMLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_EMLM_MASK; + } +} +#endif + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * @brief EDMA Channel initialization + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelConfig pointer to user's eDMA4 channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! + * @brief Set channel memory attribute. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param writeAttribute Attributes associated with a write transaction. + * @param readAttribute Attributes associated with a read transaction. + */ +static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, + uint32_t channel, + edma_channel_memory_attribute_t writeAttribute, + edma_channel_memory_attribute_t readAttribute) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION +/*! + * @brief Set channel sign extension. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param position A non-zero value specifing the sign extend bit position. + * If 0, sign extension is disabled. + */ +static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | + ((uint32_t)position << DMA_CH_CSR_SIGNEXT_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! + * @brief Set channel swap size. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param swapSize Swap occurs with respect to the specified transfer size. + * If 0, swap is disabled. + */ +static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | + ((uint32_t)swapSize << DMA_CH_CSR_SWAP_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! + * @brief Set channel access type. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelAccessType eDMA4's transactions type on the system bus when the channel is active. + */ +static inline void EDMA_SetChannelAccessType(EDMA_Type *base, + uint32_t channel, + edma_channel_access_type_t channelAccessType) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR = + (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX +/*! + * @brief Set channel request source. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param channelRequestSource eDMA hardware service request source for the channel. User need to use + * the dma_request_source_t type as the input parameter. Note that devices + * may use other enum type to express dma request source and User can fined it in + * SOC header or fsl_edma_soc.h. + */ +static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, int32_t channelRequestSource) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(base) == 1U) + { + EDMA_CHANNEL_BASE(base, channel)->CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource); + } +} +#endif + +/*! + * @brief Gets the channel identification and attribute information on the system bus interface. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of the channel system bus information. Users need to use the + * _edma_channel_sys_bus_info type to decode the return variables. + */ +static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + return EDMA_CHANNEL_BASE(base, channel)->CH_SBR; +} + +/*! + * @brief Set channel master ID replication. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK; + } +} + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channel, edma_channel_security_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK; + } +} +#endif + +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, + uint32_t channel, + edma_channel_protection_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK; + } +} + +#endif +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->EARS &= ~((uint32_t)1U << channel); + EDMA_BASE(base)->EARS |= ((uint32_t)(true == enable ? 1U : 0U) << channel); +#else + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EARQ_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EARQ_MASK; + } +#endif +} +#endif + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (enable) + { + EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param base eDMA peripheral base address. + * @param channel edma channel number. + * @param sourceOffset source address offset will be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ +/*! + * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * @param tcd Pointer to the TCD structure. + * @param transfer channel transfer configuration pointer. + * + * @note This function enables the auto stop request feature. + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer); + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param tcd A point to the TCD structure. + * @param sourceOffset source address offset wiil be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SERQ = DMA_SERQ_SERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->CERQ = DMA_CERQ_CERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SSRT = DMA_SSRT_SSRT(channel); +#else + EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_START_MASK; +#endif +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + return EDMA_BASE(base)->ES; +#else + return EDMA_MP_BASE(base)->MP_ES; +#endif +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param nextTcd eDMA transfer linked TCD address. + * + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd); + +/*! + * @brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * @code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 2. submit static link transfer, + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * 3. submit dynamic link transfer + * @code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 4. submit loop transfer + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, const edma_tcd_t *tcd); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * @note Application should check the return value of this function to avoid transfer request + * submit failed + * + * @param handle eDMA handle pointer + * @param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * @param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * @retval #kStatus_Success It means submit transfer request succeed + * @retval #kStatus_EDMA_Busy channel is in busy status + * @retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief Get unused TCD slot number. + * + * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. + * + * @param handle DMA handle pointer. + * @return The unused tcd slot number. + */ +static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) +{ + int8_t tmpTcdSize = handle->tcdSize; + int8_t tmpTcdUsed = handle->tcdUsed; + return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed); +} + +/*! + * @brief Get the next tcd address. + * + * This function gets the next tcd address. If this is last TCD, return 0. + * + * @param handle DMA handle pointer. + * @return The next TCD address. + */ +static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) +{ + return (uint32_t)(handle->tcdBase->DLAST_SGA); +} + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*FSL_EDMA_H_*/ diff --git a/drivers/edma4/fsl_edma_core.h b/drivers/edma4/fsl_edma_core.h new file mode 100644 index 000000000..e76840e4e --- /dev/null +++ b/drivers/edma4/fsl_edma_core.h @@ -0,0 +1,299 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_EDMA_CORE_H_ +#define FSL_EDMA_CORE_H_ + +#include "fsl_edma_soc.h" + +/*! + * @addtogroup edma_core + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4 +#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA_TCD_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA_TCD_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK +#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) +#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) +#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) +#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK +#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT +#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK +#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT +#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK +#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT +#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) +#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \ + (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4)) +#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA_TCD_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA_TCD_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) +#define DMA_CH_MUX_SOURCE(x) DMA_CH_MUX_SRC(x) +#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \ + (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3)) +#define DMA_CSR_INTMAJOR_MASK DMA4_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA4_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA4_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA4_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA4_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA4_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA4_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA4_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA4_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA4_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA4_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA4_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA4_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA4_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA4_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA4_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA4_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA4_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_ATTR_DMOD(x) DMA4_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA4_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA4_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA4_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA4_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA4_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA4_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA4_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA4_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA4_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA4_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA4_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA4_CSR_MAJORLINKCH(x) +#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) +#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) +#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK +#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT +#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK +#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT +#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK +#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT +#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) +#define DMA_CH_CSR_DONE_MASK DMA4_CH_CSR_DONE_MASK +#define DMA_CH_CSR_ERQ_MASK DMA4_CH_CSR_ERQ_MASK +#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +/*! intentional empty */ +#endif + +/*! @brief DMA error flag */ +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +#define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK +#define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK +#define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) +#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK +#endif +#define DMA_ERR_FLAG DMA_ES_VLD_MASK + +/*! @brief get/clear DONE status*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT) +/*! @brief enable/disable error interrupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel)) +#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel))) +/*! @brief get/clear error status*/ +#define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) +#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel) +/*! @brief get/clear int status*/ +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U)) +#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel) + +#else + +#define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK +#define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK +#define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK + +/*! @brief get/clear DONE bit*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT) +/*! @brief enable/disable error interupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK) +#define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK) +/*! @brief get/clear error status*/ +#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK) +#define DMA_GET_ERROR_STATUS(base, channel) \ + (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) +/*! @brief get/clear INT status*/ +#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK) +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U)) +#endif /*FSL_EDMA_SOC_IP_EDMA*/ + +/*! @brief enable/dsiable MAJOR/HALF INT*/ +#define DMA_ENABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK) +#define DMA_ENABLE_HALF_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK) +#define DMA_DISABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK) +#define DMA_DISABLE_HALF_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK) + +/*!@brief EDMA tcd align size */ +#define EDMA_TCD_ALIGN_SIZE (32U) + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_mp +{ + __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ +} edma_core_mp_t; + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_channel +{ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ +} edma_core_channel_t; + +/*!@brief edma core TCD struture definition */ +typedef struct _edma_core_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_core_tcd_t; + +/*!@brief EDMA typedef */ +typedef edma_core_channel_t EDMA_ChannelType; +typedef edma_core_tcd_t EDMA_TCDType; +typedef void EDMA_Type; + +/*!@brief EDMA base address convert macro */ +#define EDMA_BASE(base) +#define EDMA_CHANNEL_BASE(base, channel) \ + ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base))) +#define EDMA_TCD_BASE(base, channel) \ + ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) +#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base))) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* FSL_EDMA_CORE_H_ */ diff --git a/drivers/eim/fsl_eim.c b/drivers/eim/fsl_eim.c new file mode 100644 index 000000000..bae11683f --- /dev/null +++ b/drivers/eim/fsl_eim.c @@ -0,0 +1,312 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_eim.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.eim" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EIM bases for each instance. */ +static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EIM clocks for each instance. */ +static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EIM_GetInstance(EIM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++) + { + if (s_eimBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_eimBases)); + + return instance; +} + +/*! + * brief EIM module initialization function. + * + * param base EIM base address. + */ +void EIM_Init(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->EIMCR = 0x00U; + base->EICHEN = 0x00U; +} + +/*! + * brief Deinitializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask); + break; +#endif + +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask); + break; +#endif + default: + assert(NULL); + break; + } +} + +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint8_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} + +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD1 = mask; + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case kEIM_MemoryChannelRAMC: + base->EICHD3_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case kEIM_MemoryChannelRAMD: + base->EICHD4_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case kEIM_MemoryChannelRAME: + base->EICHD5_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case kEIM_MemoryChannelRAMF: + base->EICHD6_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case kEIM_MemoryChannelLPCACRAM: + base->EICHD7_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case kEIM_MemoryChannelPKCRAM: + base->EICHD8_WORD1 = mask; + break; +#endif + default: + assert(NULL); + break; + } +} + +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint32_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; + break; + +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} diff --git a/drivers/eim/fsl_eim.h b/drivers/eim/fsl_eim.h new file mode 100644 index 000000000..4594136c1 --- /dev/null +++ b/drivers/eim/fsl_eim.h @@ -0,0 +1,144 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EIM_H_ +#define FSL_EIM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup eim + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief EIM module initialization function. + * + * @param base EIM base address. + */ +void EIM_Init(EIM_Type *base); + +/*! + * @brief De-initializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base); + +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief EIM module enable global error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. + */ +static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable) +{ + if (enable) + { + base->EIMCR = EIM_EIMCR_GEIEN_MASK; + } + else + { + base->EIMCR = ~EIM_EIMCR_GEIEN_MASK; + } +} + +/*! + * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error + * injection channel. The Global Error Injection Enable function must also be called to enable error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN |= mask; +} + +/*! + * @brief EIM module disable error injection for memory channel n. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN &= ~mask; +} + +/*! + * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get checkbit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! + * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get databit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/drivers/erm/fsl_erm.c b/drivers/erm/fsl_erm.c new file mode 100644 index 000000000..cdd35b56b --- /dev/null +++ b/drivers/erm/fsl_erm.c @@ -0,0 +1,317 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_erm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.erm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ERM bases for each instance. */ +static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ERM clocks for each instance. */ +static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ERM_GetInstance(ERM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ermBases); instance++) + { + if (s_ermBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ermBases)); + + return instance; +} + +/*! + * brief ERM module initialization function. + * + * param base ERM base address. + */ +void ERM_Init(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CR0 = 0x00U; +#ifdef ERM_CR1_ENCIE8_MASK + base->CR1 = 0x00U; +#endif + base->SR0 = 0xFFFFFFFFU; +#ifdef ERM_SR1_SBC8_MASK + base->SR1 = 0xFFFFFFFFU; +#endif +} + +/*! + * brief Deinitializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_DisableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t absoluteErrorAddress = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + absoluteErrorAddress = base->EAR0; + break; +#ifdef ERM_EAR1_EAR_MASK + case 1U: + absoluteErrorAddress = base->EAR1; + break; +#endif +#ifdef ERM_EAR2_EAR_MASK + case 2U: + absoluteErrorAddress = base->EAR2; + break; +#endif +#ifdef ERM_EAR3_EAR_MASK + case 3U: + absoluteErrorAddress = base->EAR3; + break; +#endif +#ifdef ERM_EAR4_EAR_MASK + case 4U: + absoluteErrorAddress = base->EAR4; + break; +#endif +#ifdef ERM_EAR5_EAR_MASK + case 5U: + absoluteErrorAddress = base->EAR5; + break; +#endif +#ifdef ERM_EAR6_EAR_MASK + case 6U: + absoluteErrorAddress = base->EAR6; + break; +#endif + default: + assert(NULL); + break; + } + + return absoluteErrorAddress; +} + +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t syndrome = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT; + break; +#ifdef ERM_SYN1_SYNDROME_MASK + case 1U: + syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN2_SYNDROME_MASK + case 2U: + syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN3_SYNDROME_MASK + case 3U: + syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN4_SYNDROME_MASK + case 4U: + syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN5_SYNDROME_MASK + case 5U: + syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN6_SYNDROME_MASK + case 6U: + syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN7_SYNDROME_MASK + case 7U: + syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN8_SYNDROME_MASK + case 8U: + syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN9_SYNDROME_MASK + case 8U: + syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return syndrome; +} + +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t count = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT; + break; +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK + case 7U: + count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return count; +} + +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + switch ((uint8_t)channel) + { + case 0U: + base->CORR_ERR_CNT0 = 0x00U; + break; + +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + base->CORR_ERR_CNT1 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + base->CORR_ERR_CNT2 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + base->CORR_ERR_CNT3 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + base->CORR_ERR_CNT4 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + base->CORR_ERR_CNT5 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + base->CORR_ERR_CNT6 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 7U: + base->CORR_ERR_CNT7 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + base->CORR_ERR_CNT8 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + base->CORR_ERR_CNT9 = 0x00U; + break; +#endif + default: + assert(NULL); + break; + } +} diff --git a/drivers/erm/fsl_erm.h b/drivers/erm/fsl_erm.h new file mode 100644 index 000000000..c199e74b0 --- /dev/null +++ b/drivers/erm/fsl_erm.h @@ -0,0 +1,235 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_ERM_H_ +#define FSL_ERM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup erm + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +/*! + * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable. + * + * This structure contains the settings for all of the ERM interrupt configurations. + */ +enum +{ + kERM_SingleCorrectionIntEnable = 0x08U, /*!< Single Correction Interrupt Notification enable.*/ + kERM_NonCorrectableIntEnable = 0x04U, /*!< Non-Correction Interrupt Notification enable.*/ + + kERM_AllInterruptsEnable = 0xFFFFFFFFUL, /*!< All Interrupts enable */ +}; + +/*! + * @brief ERM interrupt status, _erm_interrupt_flag. + * + * This provides constants for the ERM event status for use in the ERM functions. + */ +enum +{ + kERM_SingleBitCorrectionIntFlag = 0x08U, /*!< Single-Bit Correction Event.*/ + kERM_NonCorrectableErrorIntFlag = 0x04U, /*!< Non-Correctable Error Event.*/ + + kERM_AllIntsFlag = 0xFFFFFFFFUL, /*!< All Events. */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief ERM module initialization function. + * + * @param base ERM base address. + */ +void ERM_Init(ERM_Type *base); + +/*! + * @brief De-initializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base); + +/* @} */ + +/*! + * @name Interrupt + * @{ + */ +/*! + * @brief ERM enable interrupts. + * + * @param base ERM peripheral base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + uint32_t temp = 0x00U; + if ((uint32_t)channel <= 0x07U) + { + temp = base->CR0; + base->CR0 = + (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + temp = base->CR1; + base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) | + (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief ERM module disable interrupts. + * + * @param base ERM base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief Gets ERM interrupt flags. + * + * @param base ERM peripheral base address. + * @return ERM event flags. + */ +static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel) +{ + if ((uint32_t)channel <= 0x07U) + { + return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#else + { + return 0; + } +#endif +} + +/*! + * @brief ERM module clear interrupt status flag. + * + * @param base ERM base address. + * @param mask event flag to clear. Refer to "_erm_interrupt_flag" enumeration. + */ +static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U); + } +#endif +} + +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval memory error absolute address. + */ + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a + * non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic + * information on non-correctable, multi-bit inversions. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval syndrome value. + */ +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get error count, which records the count value of the number of correctable ECC error events for Memory + * n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count + * non-correctable errors. Only correctable errors are counted. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval error count. + */ +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM reset error count. + * + * @param base ERM base address. + * @param channel memory channel. + */ +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/drivers/evtg/fsl_evtg.c b/drivers/evtg/fsl_evtg.c new file mode 100644 index 000000000..7402c428d --- /dev/null +++ b/drivers/evtg/fsl_evtg.c @@ -0,0 +1,418 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_evtg.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.evtg" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize EVTG with a user configuration structure. + * + * param base EVTG base address. + * param evtgIndex EVTG instance index. + * param psConfig EVTG initial configuration structure pointer. + */ +void EVTG_Init(EVTG_Type *base, evtg_index_t evtgIndex, evtg_config_t *psConfig) +{ + /* Configure Flip-Flop as expected mode. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL = EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL((uint16_t)psConfig->flipflopMode); + + if (kEVTG_FFModeJKFF == psConfig->flipflopMode) + { + /* When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace one of the four + * inputs.*/ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= + EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD((uint16_t)psConfig->outfdbkOverideinput); + } + + if (psConfig->enableFlipflopInitOutput == true) + { + EVTG_ForceFlipflopInitOutput(base, evtgIndex, psConfig->flipflopInitOutputValue); + } + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS( + ((uint16_t)psConfig->enableForceBypassFlipFlopAOI1 << 1U) | (uint16_t)psConfig->enableForceBypassFlipFlopAOI0); +#endif + + /* Configure EVTG input sync. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL( + (((uint16_t)psConfig->enableInputDSync << 3U) | ((uint16_t)psConfig->enableInputCSync << 2U) | + ((uint16_t)psConfig->enableInputBSync << 1U) | ((uint16_t)psConfig->enableInputASync))); + + /* Configure AOI0. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 = + (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psConfig->aoi0Config.productTerm0.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psConfig->aoi0Config.productTerm0.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psConfig->aoi0Config.productTerm0.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psConfig->aoi0Config.productTerm0.dInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psConfig->aoi0Config.productTerm1.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psConfig->aoi0Config.productTerm1.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psConfig->aoi0Config.productTerm1.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psConfig->aoi0Config.productTerm1.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 = + (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psConfig->aoi0Config.productTerm2.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psConfig->aoi0Config.productTerm2.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psConfig->aoi0Config.productTerm2.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psConfig->aoi0Config.productTerm2.dInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psConfig->aoi0Config.productTerm3.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psConfig->aoi0Config.productTerm3.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psConfig->aoi0Config.productTerm3.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psConfig->aoi0Config.productTerm3.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_FILT |= + (EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT((uint16_t)psConfig->aoi0Config.aoiOutFilterConfig.sampleCount) | + EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod)); + + /* Configure AOI1. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 = + (EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC((uint8_t)psConfig->aoi1Config.productTerm0.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC((uint8_t)psConfig->aoi1Config.productTerm0.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC((uint8_t)psConfig->aoi1Config.productTerm0.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC((uint8_t)psConfig->aoi1Config.productTerm0.dInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC((uint8_t)psConfig->aoi1Config.productTerm1.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC((uint8_t)psConfig->aoi1Config.productTerm1.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC((uint8_t)psConfig->aoi1Config.productTerm1.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC((uint8_t)psConfig->aoi1Config.productTerm1.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 = + (EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC((uint8_t)psConfig->aoi1Config.productTerm2.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC((uint8_t)psConfig->aoi1Config.productTerm2.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC((uint8_t)psConfig->aoi1Config.productTerm2.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC((uint8_t)psConfig->aoi1Config.productTerm2.dInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC((uint8_t)psConfig->aoi1Config.productTerm3.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC((uint8_t)psConfig->aoi1Config.productTerm3.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC((uint8_t)psConfig->aoi1Config.productTerm3.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC((uint8_t)psConfig->aoi1Config.productTerm3.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_FILT |= + (EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT((uint16_t)psConfig->aoi1Config.aoiOutFilterConfig.sampleCount) | + EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod)); +} + +/*! + * brief Configure AOI product term by initializing the product term + * configuration structure. + * + * param base EVTG base address. + * param evtgIndex EVTG instance index. + * param aoiIndex EVTG AOI index. see enum ref evtg_aoi_index_t + * param productTerm EVTG AOI product term index. + * param psProductTermConfig Pointer to EVTG product term configuration structure. + * see ref _evtg_product_term_config + */ +void EVTG_ConfigAOIProductTerm(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_aoi_product_term_config_t *psProductTermConfig) +{ + volatile uint16_t *pu16AOIPT01Config; + volatile uint16_t *pu16AOIPT23Config; + + if (kEVTG_AOI0 == aoiIndex) + { + pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01; + pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23; + } + else + { + pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01; + pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23; + } + + if (kEVTG_ProductTerm0 == productTerm) + { + *pu16AOIPT01Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK); + *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psProductTermConfig->dInput)); + } + else if (kEVTG_ProductTerm1 == productTerm) + { + *pu16AOIPT01Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK); + *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psProductTermConfig->dInput)); + } + else if (kEVTG_ProductTerm2 == productTerm) + { + *pu16AOIPT23Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK); + *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psProductTermConfig->dInput)); + } + else + { + *pu16AOIPT23Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK); + *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psProductTermConfig->dInput)); + } +} + +/*! + * @brief Loads default values to the EVTG configuration structure. + * + * The purpose of this API is to initialize the configuration structure to default value for @ref EVTG_Init() + * to use. + * The Flip-Flop can be configured as Bypass mode, RS trigger mode, T-FF mode, D-FF mode, JK-FF mode, Latch mode. + * Please check RM INTC chapter for more details. + * + * @param psConfig EVTG initial configuration structure pointer. + * @param flipflopMode EVTG flip flop mode. see @ ref _evtg_flipflop_mode + */ +void EVTG_GetDefaultConfig(evtg_config_t *psConfig, evtg_flipflop_mode_t flipflopMode) +{ + /* Initializes the configure structure to zero. */ + (void)memset(psConfig, 0, sizeof(evtg_config_t)); + + switch (flipflopMode) + { + case kEVTG_FFModeBypass: + + /* + * In this mode, filp-flop will be passed, The two AOI expressions "AOI_0" and "AOI_1" + * will be directly assigned to EVTG outputs(EVTG_OUTA and EVTG_OUTB). + * + * In this mode, user can choose to enable or disable input sync logic and filter function. + * Here disable both input sync logic and filter function. + */ + psConfig->flipflopMode = kEVTG_FFModeBypass; + + psConfig->enableInputASync = false; + psConfig->enableInputBSync = false; + psConfig->enableInputCSync = false; + psConfig->enableInputDSync = false; + + break; + + case kEVTG_FFModeRSTrigger: + + /* + * In this mode, AOI_0 expression is Reset port, and AOI_1 is Set port. Both are active + * high. When "R"(Reset) is high, whatever "S"(Set) is, EVTG_OUTA will be "0". When "R" is + * low and "S" is high, EVTG_OUTA will be "1". If both "R" and "S" are low, EVTG output + * will be kept. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, user can choose to enable or disable input sync logic and filter function. + * Here disable both input sync logic and filter function. + */ + psConfig->flipflopMode = kEVTG_FFModeRSTrigger; + + psConfig->enableInputASync = false; + psConfig->enableInputBSync = false; + psConfig->enableInputCSync = false; + psConfig->enableInputDSync = false; + + break; + + case kEVTG_FFModeTFF: + + /* + * In this mode, AOI_0 expression is T port of T-FF, AOI_1 is CLK port. When T assert, + * the Q port (EVTG_OUTA) will turnover at the rising edge of "CLK". When T dis-assert, + * Q(EVTG_OUTA) will be kept. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + */ + psConfig->flipflopMode = kEVTG_FFModeTFF; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + case kEVTG_FFModeJKFF: + + /* + * In general, JK Flip-Flop have four input ports: J, K , Q and CLK(Q is output of Flip-Flop). + * And the logical expression is J&~Q | ~K&Q; Here we implement the logic expression by AOI + * so that we can reuse the D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port, + * "Cn" as "K" port, "Dn" as "CLK" port, and "Q" port of FF feed back and override "Bn". + * According to the JK logic expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", + * AOI_1 expression will be "Dn". + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + * + * When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace + * one of the four inputs. Here input Bn is replaced, represents which EVTG input(EVTG_OUTA) + * is replaced by FF output. + */ + psConfig->flipflopMode = kEVTG_FFModeJKFF; + psConfig->outfdbkOverideinput = kEVTG_OutputOverrideInputB; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + case kEVTG_FFModeLatch: + + /* + * In this mode, AOI_0 expression is D port, AOI_1 is CLK port. Different from D-FF + * mode, in Latch mode, D port will be passed only when CLK is high, and output will be + * kept when CLK is low. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + */ + psConfig->flipflopMode = kEVTG_FFModeLatch; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + default: + assert(false); + break; + } + /* User could choose to enable or disable Flip-flop initial output value. */ + psConfig->enableFlipflopInitOutput = false; + psConfig->flipflopInitOutputValue = kEVTG_FFInitOut0; + + /* User could choose to override this fields to enable filter function. */ + psConfig->aoi0Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3; + psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod = 0U; + + psConfig->aoi1Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3; + psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod = 0U; + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + psConfig->enableForceBypassFlipFlopAOI0 = false; + psConfig->enableForceBypassFlipFlopAOI1 = false; +#endif + + /* + * For JK-FF Mode, Here we implement the logic expression by AOI so that we can reuse the + * D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port, "Cn" as "K" port, "Dn" + * as "CLK" port, and "Q" port of FF feed back and override "Bn". According to the JK logic + * expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", AOI_1 expression will be "Dn". + * + * For other FF Mode, the default input here is logical 0. User can configure to produce a logical 0 + * or 1 or pass the true or complement of the selected event input according to their requirement. + */ + if (kEVTG_FFModeJKFF == flipflopMode) + { + psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputDirectPass; + psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputComplement; + psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicOne; + psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicOne; + + psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicOne; + psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputDirectPass; + psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputComplement; + psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicOne; + + psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputDirectPass; + + psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero; + } + else + { + psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero; + } +} diff --git a/drivers/evtg/fsl_evtg.h b/drivers/evtg/fsl_evtg.h new file mode 100644 index 000000000..42a2a746e --- /dev/null +++ b/drivers/evtg/fsl_evtg.h @@ -0,0 +1,355 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EVTG_H_ +#define FSL_EVTG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup evtg + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EVTG driver version. */ +#define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +/*! @brief EVTG instance index. */ +typedef enum _evtg_index +{ + kEVTG_Index0 = 0x0U, /*!< EVTG instance index 0. */ + kEVTG_Index1, /*!< EVTG instance index 1. */ + kEVTG_Index2, /*!< EVTG instance index 2. */ + kEVTG_Index3, /*!< EVTG instance index 3. */ +} evtg_index_t; + +/*! @brief EVTG input index. */ +typedef enum _evtg_input_index +{ + kEVTG_InputA = 0x0U, /*!< EVTG input A. */ + kEVTG_InputB, /*!< EVTG input B. */ + kEVTG_InputC, /*!< EVTG input C. */ + kEVTG_InputD, /*!< EVTG input D. */ +} evtg_input_index_t; + +/*! @brief EVTG AOI index. */ +typedef enum _evtg_aoi_index +{ + kEVTG_AOI0 = 0x0U, /*!< EVTG AOI index 0. */ + kEVTG_AOI1 = 0x1U, /*!< EVTG AOI index 1. */ +} evtg_aoi_index_t; + +/*! @brief EVTG AOI product term index. */ +typedef enum _evtg_aoi_product_term +{ + kEVTG_ProductTerm0 = 0x0U, /*!< EVTG AOI product term index 0. */ + kEVTG_ProductTerm1, /*!< EVTG AOI product term index 1. */ + kEVTG_ProductTerm2, /*!< EVTG AOI product term index 2. */ + kEVTG_ProductTerm3, /*!< EVTG AOI product term index 3. */ +} evtg_aoi_product_term_t; + +/*! @brief EVTG input configuration. */ +typedef enum _evtg_aoi_input_config +{ + kEVTG_InputLogicZero = 0x0U, /*!< Force input in product term to a logical zero. */ + kEVTG_InputDirectPass, /*!< Pass input in product term. */ + kEVTG_InputComplement, /*!< Complement input in product term. */ + kEVTG_InputLogicOne, /*!< Force input in product term to a logical one. */ +} evtg_aoi_input_config_t; + +/*! @brief EVTG AOI Output Filter Sample Count. */ +typedef enum _evtg_aoi_outfilter_count +{ + kEVTG_AOIOutFilterSampleCount3 = 0x0U, /*!< EVTG AOI output filter sample count is 3. */ + kEVTG_AOIOutFilterSampleCount4, /*!< EVTG AOI output filter sample count is 4. */ + kEVTG_AOIOutFilterSampleCount5, /*!< EVTG AOI output filter sample count is 5. */ + kEVTG_AOIOutFilterSampleCount6, /*!< EVTG AOI output filter sample count is 6. */ + kEVTG_AOIOutFilterSampleCount7, /*!< EVTG AOI output filter sample count is 7. */ + kEVTG_AOIOutFilterSampleCount8, /*!< EVTG AOI output filter sample count is 8. */ + kEVTG_AOIOutFilterSampleCount9, /*!< EVTG AOI output filter sample count is 9. */ + kEVTG_AOIOutFilterSampleCount10, /*!< EVTG AOI output filter sample count is 10. */ +} evtg_aoi_outfilter_count_t; + +/*! + * @brief EVTG output feedback override control mode. When FF is configured as JK-FF mode, + * need EVTG_OUTA feedback to EVTG input and replace one of the four inputs. + */ +typedef enum _evtg_outfdbk_override_input +{ + kEVTG_OutputOverrideInputA = 0x0U, /*!< Replace input A. */ + kEVTG_OutputOverrideInputB, /*!< Replace input B. */ + kEVTG_OutputOverrideInputC, /*!< Replace input C. */ + kEVTG_OutputOverrideInputD, /*!< Replace input D. */ +} evtg_outfdbk_override_input_t; + +/*! @brief EVTG flip flop mode configuration. */ +typedef enum _evtg_flipflop_mode +{ + kEVTG_FFModeBypass = 0x0U, /*!< Bypass mode (default).In this mode, user can choose to enable + or disable input sync logic and filter function. */ + kEVTG_FFModeRSTrigger, /*!< RS trigger mode. In this mode, user can choose to enable + or disable input sync logic and filter function. */ + kEVTG_FFModeTFF, /*!< T-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeDFF, /*!< D-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeJKFF, /*!< JK-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeLatch, /*!< Latch mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ +} evtg_flipflop_mode_t; + +/*! @brief EVTG flip-flop initial value. */ +typedef enum _evtg_flipflop_init_output +{ + kEVTG_FFInitOut0 = 0x0U, /*!< Configure the positive output of flip-flop as 0. */ + kEVTG_FFInitOut1 = 0x1U, /*!< Configure the positive output of flip-flop as 1. */ +} evtg_flipflop_init_output_t; + +/*! @brief The structure for configuring an AOI output filter sample. + * + * AOI output filter sample count represent the number of consecutive samples that must agree prior to the AOI output + * filter accepting an transition. + * AOI output filter sample period represent the sampling period (in IP bus clock cycles) of the AOI output signals. + * Each AOI output is sampled multiple times at the rate specified by this period. + * + * For the modes with Filter function enabled, filter delay is "(FILT_CNT + 3) x FILT_PER + 2". + * + */ +typedef struct _evtg_aoi_outfilter_config +{ + evtg_aoi_outfilter_count_t sampleCount; /*!< EVTG AOI output filter sample count. + refer to @ref evtg_aoi_outfilter_count_t. */ + uint8_t samplePeriod; /*!< EVTG AOI output filter sample period, within 0~255. If sample period + value is 0x00 (default), then the input filter is bypassed. */ +} evtg_aoi_outfilter_config_t; + +/*! @brief The structure for configuring an AOI product term. */ +typedef struct _evtg_aoi_product_term_config +{ + evtg_aoi_input_config_t aInput; /*!< Input A configuration. */ + evtg_aoi_input_config_t bInput; /*!< Input B configuration. */ + evtg_aoi_input_config_t cInput; /*!< Input C configuration. */ + evtg_aoi_input_config_t dInput; /*!< Input D configuration. */ +} evtg_aoi_product_term_config_t; + +/*! @brief EVTG AOI configuration structure. */ +typedef struct _evtg_aoi_config +{ + /* AOI Output Filter configuration. */ + evtg_aoi_outfilter_config_t aoiOutFilterConfig; /*!< EVTG AOI output filter sample + configuration structure. */ + + /* Product term configuration. */ + evtg_aoi_product_term_config_t productTerm0; /*!< Configure AOI product term0. */ + evtg_aoi_product_term_config_t productTerm1; /*!< Configure AOI product term1. */ + evtg_aoi_product_term_config_t productTerm2; /*!< Configure AOI product term2. */ + evtg_aoi_product_term_config_t productTerm3; /*!< Configure AOI product term3. */ +} evtg_aoi_config_t; + +/*! @brief EVTG configuration covering all configurable fields. */ +typedef struct _evtg_config +{ + /* Input configuration. */ + bool enableInputASync; /*!< Enable/Disable EVTG A input synchronous with bus clk. */ + bool enableInputBSync; /*!< Enable/Disable EVTG B input synchronous with bus clk. */ + bool enableInputCSync; /*!< Enable/Disable EVTG C input synchronous with bus clk. */ + bool enableInputDSync; /*!< Enable/Disable EVTG D input synchronous with bus clk. */ + evtg_outfdbk_override_input_t outfdbkOverideinput; /*!< EVTG output feedback to EVTG input + and replace one of the four inputs. */ + + /* Flip-flop configuration. */ + evtg_flipflop_mode_t flipflopMode; /*!< Flip-Flop can be configured as one of Bypass mode, RS trigger mode, + T-FF mode, D-FF mode, JK-FF mode, Latch mode. */ + bool enableFlipflopInitOutput; /*!< Flip-flop initial output value enable/disable. */ + evtg_flipflop_init_output_t flipflopInitOutputValue; /*!< Flip-flop initial output value configuration. */ + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + bool enableForceBypassFlipFlopAOI0; /*!< Enable/Disable force bypass Flip-Flop and route the AOI_0(Filter_0) + value directly to EVTG_OUTA */ + bool enableForceBypassFlipFlopAOI1; /*!< Enable/Disable force bypass Flip-Flop and route the AOI_1(Filter_1) + value directly to EVTG_OUTB */ +#endif + + /* AOI configuration. */ + evtg_aoi_config_t aoi0Config; /*!< Configure EVTG AOI0. */ + evtg_aoi_config_t aoi1Config; /*!< Configure EVTG AOI1. */ +} evtg_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup evtg_driver + * @{ + */ + +/*! + * @name Initialization Interfaces + * @{ + */ + +/*! + * @brief Initialize EVTG with a user configuration structure. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param psConfig EVTG initial configuration structure pointer. + */ +void EVTG_Init(EVTG_Type *base, evtg_index_t evtgIndex, evtg_config_t *psConfig); + +/*! + * @brief Loads default values to the EVTG configuration structure. + * + * The purpose of this API is to initialize the configuration structure to default value for @ref EVTG_Init() + * to use. + * The Flip-Flop can be configured as Bypass mode, RS trigger mode, T-FF mode, D-FF mode, JK-FF mode, Latch mode. + * Please check RM INTC chapter for more details. + * + * @param psConfig EVTG initial configuration structure pointer. + * @param flipflopMode EVTG flip flop mode. see @ ref _evtg_flipflop_mode + */ +void EVTG_GetDefaultConfig(evtg_config_t *psConfig, evtg_flipflop_mode_t flipflopMode); +/*! @} */ + +/*! + * @name Force Init Flipflop Interfaces + * @{ + */ + +/*! + * @brief Force Flip-flop initial output value to be presented on flip-flop positive output. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param flipflopInitOutputValue EVTG flip-flop initial output control. + * see @ref evtg_flipflop_init_output_t + */ +static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_flipflop_init_output_t flipflopInitOutputValue) +{ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= + EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue); + /* INIT_EN bit should be set after FF_INIT is set. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK; +} +/*! @} */ + +/*! + * @name Input Interfaces + * @{ + */ +/*! + * @brief Configure each input value of AOI product term. Each selected input term in + * each product term can be configured to produce a logical 0 or 1 or pass the + * true or complement of the selected event input. Adapt to some simple aoi + * expressions. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param aoiIndex EVTG AOI index. see enum ref evtg_aoi_index_t + * @param productTerm EVTG product term index. + * @param inputIndex EVTG input index. + * @param input EVTG input configuration with enum @ref evtg_aoi_input_config_t. + */ +static inline void EVTG_SetProductTermInput(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_input_index_t inputIndex, + evtg_aoi_input_config_t input) +{ + if (kEVTG_AOI0 == aoiIndex) + { + if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + else + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + } + else if (kEVTG_AOI1 == aoiIndex) + { + if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + else + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + } + else + { + ; /* No action*/ + } +} + +/*! + * @brief Configure AOI product term by initializing the product term + * configuration structure. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param aoiIndex EVTG AOI index. see enum @ref evtg_aoi_index_t + * @param productTerm EVTG AOI product term index. + * @param psProductTermConfig Pointer to EVTG product term configuration structure. + * see ref _evtg_aoi_product_term_config + */ +void EVTG_ConfigAOIProductTerm(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_aoi_product_term_config_t *psProductTermConfig); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_EVTG_H_ */ diff --git a/drivers/ewm/fsl_ewm.h b/drivers/ewm/fsl_ewm.h index dbef1b3d0..ee3face3f 100644 --- a/drivers/ewm/fsl_ewm.h +++ b/drivers/ewm/fsl_ewm.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EWM_H_ -#define _FSL_EWM_H_ +#ifndef FSL_EWM_H_ +#define FSL_EWM_H_ #include "fsl_common.h" @@ -215,4 +215,4 @@ void EWM_Refresh(EWM_Type *base); /*! @}*/ -#endif /* _FSL_EWM_H_ */ +#endif /* FSL_EWM_H_ */ diff --git a/drivers/flexcan/fsl_flexcan.c b/drivers/flexcan/fsl_flexcan.c index bf3446158..c3a989f3f 100644 --- a/drivers/flexcan/fsl_flexcan.c +++ b/drivers/flexcan/fsl_flexcan.c @@ -98,7 +98,11 @@ #define MIN_TIME_SEGMENT2 (2U) /* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ +#if (defined(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#define MAX_CANFD_BITRATE ((uint32_t)(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#else #define MAX_CANFD_BITRATE (8000000U) +#endif #define MAX_CAN_BITRATE (1000000U) #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) @@ -121,6 +125,12 @@ #endif /* CAN_CLOCK_CHECK_NO_AFFECTS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RSTS) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS +#elif defined(FLEXCAN_RSTS_N) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS_N +#endif + /*! @brief FlexCAN Internal State. */ enum _flexcan_state { @@ -320,6 +330,11 @@ static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexcanResets[] = FLEXCAN_RESETS_ARRAY; +#endif + /* FlexCAN ISR for transactional APIs. */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR; @@ -889,6 +904,10 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sour #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexcanResets[FLEXCAN_GetInstance(base)]); +#endif + #if defined(CAN_CTRL1_CLKSRC_MASK) #if (defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) && FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) @@ -1041,7 +1060,7 @@ void FLEXCAN_FDInit( uint16_t maxDivider; /* Check bit rate value. */ - assert((pConfig->bitRateFD <= 8000000U) && (tqFre <= sourceClock_Hz)); + assert((pConfig->bitRateFD <= MAX_CANFD_BITRATE) && (tqFre <= sourceClock_Hz)); #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) assert((tqFre * MAX_EDPRESDIV) >= sourceClock_Hz); maxDivider = MAX_EDPRESDIV; @@ -4388,22 +4407,30 @@ static status_t FLEXCAN_SubHandlerForMB(CAN_Type *base, flexcan_handle_t *handle if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) { status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); - if (kStatus_Success == status) + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) { /* Align the current index of RX MB timestamp to the timestamp array by handle. */ handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; - status = kStatus_FLEXCAN_RxIdle; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } } } else #endif { status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); - if (kStatus_Success == status) + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) { /* Align the current index of RX MB timestamp to the timestamp array by handle. */ handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; - status = kStatus_FLEXCAN_RxIdle; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } } } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) diff --git a/drivers/flexcan/fsl_flexcan.h b/drivers/flexcan/fsl_flexcan.h index fe4643a7b..553e4613c 100644 --- a/drivers/flexcan/fsl_flexcan.h +++ b/drivers/flexcan/fsl_flexcan.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXCAN_H_ -#define _FSL_FLEXCAN_H_ +#ifndef FSL_FLEXCAN_H_ +#define FSL_FLEXCAN_H_ #include "fsl_common.h" @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexCAN driver version. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 1)) +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 4)) /*@}*/ #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) @@ -231,7 +231,7 @@ #endif /*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) -#define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U) +#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U) #else #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U) #endif @@ -2357,4 +2357,4 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); /*! @}*/ -#endif /* _FSL_FLEXCAN_H_ */ +#endif /* FSL_FLEXCAN_H_ */ diff --git a/drivers/flexcan/fsl_flexcan_edma.c b/drivers/flexcan/fsl_flexcan_edma.c index f5da4e18c..a5f68487f 100644 --- a/drivers/flexcan/fsl_flexcan_edma.c +++ b/drivers/flexcan/fsl_flexcan_edma.c @@ -324,6 +324,7 @@ status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, assert(NULL != pFifoXfer->framefd); edma_transfer_config_t dmaXferConfig; + edma_minor_offset_config_t dmaMinorOffsetConfig; status_t status; flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base); uint32_t perReadWords = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U; @@ -355,13 +356,16 @@ status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, kEDMA_MemoryToMemory); /* Submit configuration. */ (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig); - handle->rxFifoEdmaHandle->base->CH[handle->rxFifoEdmaHandle->channel].TCD_NBYTES_MLOFFYES &= - ~DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK; - handle->rxFifoEdmaHandle->base->CH[handle->rxFifoEdmaHandle->channel].TCD_NBYTES_MLOFFYES |= - DMA_TCD_NBYTES_MLOFFYES_MLOFF(128U - sizeof(uint32_t) * perReadWords) | DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK; - handle->rxFifoEdmaHandle->base->CH[handle->rxFifoEdmaHandle->channel].TCD_ATTR &= - ~(uint16_t)DMA_TCD_ATTR_SMOD_MASK; - handle->rxFifoEdmaHandle->base->CH[handle->rxFifoEdmaHandle->channel].TCD_ATTR |= DMA_TCD_ATTR_SMOD(7U); + + dmaMinorOffsetConfig.enableDestMinorOffset = false; + dmaMinorOffsetConfig.enableSrcMinorOffset = true; + dmaMinorOffsetConfig.minorOffset = 128U - sizeof(uint32_t) * perReadWords; + EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, + &dmaMinorOffsetConfig); + + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes, + kEDMA_ModuloDisable); + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; /* Enable FlexCAN Rx FIFO EDMA. */ diff --git a/drivers/flexcan/fsl_flexcan_edma.h b/drivers/flexcan/fsl_flexcan_edma.h index 31bea4c29..98f1f803b 100644 --- a/drivers/flexcan/fsl_flexcan_edma.h +++ b/drivers/flexcan/fsl_flexcan_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXCAN_EDMA_H_ -#define _FSL_FLEXCAN_EDMA_H_ +#ifndef FSL_FLEXCAN_EDMA_H_ +#define FSL_FLEXCAN_EDMA_H_ #include "fsl_flexcan.h" #include "fsl_edma.h" @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexCAN EDMA driver version. */ -#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 0)) +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3)) /*@}*/ /* Forward declaration of the handle typedef. */ @@ -185,4 +185,4 @@ static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type /*! @}*/ -#endif /* _FSL_FLEXCAN_EDMA_H_ */ +#endif /* FSL_FLEXCAN_EDMA_H_ */ diff --git a/drivers/flexio/fsl_flexio.c b/drivers/flexio/fsl_flexio.c index 16491862b..52741f2a4 100644 --- a/drivers/flexio/fsl_flexio.c +++ b/drivers/flexio/fsl_flexio.c @@ -20,6 +20,12 @@ /*< @brief user configurable flexio handle count. */ #define FLEXIO_HANDLE_COUNT 2 +#if defined(FLEXIO_RSTS) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS +#elif defined(FLEXIO_RSTS_N) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -43,6 +49,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; /* FlexIO common IRQ Handler. */ static void FLEXIO_CommonIRQHandler(void); +#if defined(FLEXIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY; +#endif + /******************************************************************************* * Codes ******************************************************************************/ @@ -96,6 +107,10 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]); +#endif + FLEXIO_Reset(base); ctrlReg = base->CTRL; diff --git a/drivers/flexio/fsl_flexio.h b/drivers/flexio/fsl_flexio.h index a250272c1..86f655357 100644 --- a/drivers/flexio/fsl_flexio.h +++ b/drivers/flexio/fsl_flexio.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_H_ -#define _FSL_FLEXIO_H_ +#ifndef FSL_FLEXIO_H_ +#define FSL_FLEXIO_H_ #include "fsl_common.h" @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexIO driver version. */ -#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*@}*/ /*! @brief Calculate FlexIO timer trigger.*/ @@ -522,6 +522,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_ * @brief This function set the value of the prescaler on flexio channels * * @param base Pointer to the FlexIO simulated peripheral type. + * @param index Timer index * @param clocksource Set clock value */ static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource) @@ -913,4 +914,4 @@ static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask) #endif /*_cplusplus*/ /*@}*/ -#endif /*_FSL_FLEXIO_H_*/ +#endif /*FSL_FLEXIO_H_*/ diff --git a/drivers/flexio/i2c/fsl_flexio_i2c_master.h b/drivers/flexio/i2c/fsl_flexio_i2c_master.h index 8bf4707c8..02dd10a48 100644 --- a/drivers/flexio/i2c/fsl_flexio_i2c_master.h +++ b/drivers/flexio/i2c/fsl_flexio_i2c_master.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_I2C_MASTER_H_ -#define _FSL_FLEXIO_I2C_MASTER_H_ +#ifndef FSL_FLEXIO_I2C_MASTER_H_ +#define FSL_FLEXIO_I2C_MASTER_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -482,4 +482,4 @@ void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); #endif /*_cplusplus*/ /*@}*/ -#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ +#endif /*FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd.c b/drivers/flexio/mculcd/fsl_flexio_mculcd.c index 809e9f7b6..217b6595a 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd.c +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd.c @@ -992,7 +992,10 @@ void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_tran { FLEXIO_MCULCD_StartTransfer(base); - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + if (!xfer->dataOnly) + { + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } if (xfer->dataSize > 0U) { @@ -1093,8 +1096,11 @@ status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, /* Assert the nCS. */ FLEXIO_MCULCD_StartTransfer(base); - /* Send the command. */ - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } /* If transfer count is 0 (only to send command), return directly. */ if (0U == xfer->dataSize) diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd.h b/drivers/flexio/mculcd/fsl_flexio_mculcd.h index db146d39c..d998b1d39 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd.h +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_MCULCD_H_ -#define _FSL_FLEXIO_MCULCD_H_ +#ifndef FSL_FLEXIO_MCULCD_H_ +#define FSL_FLEXIO_MCULCD_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexIO MCULCD driver version. */ -#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 8)) +#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ #ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME @@ -144,11 +144,12 @@ typedef enum _flexio_mculcd_transfer_mode typedef struct _flexio_mculcd_transfer { uint32_t command; /*!< Command to send. */ - flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, this is the value to send. When writing or reading array, this is the address of the data array. */ size_t dataSize; /*!< How many bytes to transfer. */ + flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ + bool dataOnly; /*!< Send data only when tx without the command. */ } flexio_mculcd_transfer_t; /*! @brief typedef for flexio_mculcd_handle_t in advance. */ @@ -682,4 +683,4 @@ void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle); #endif /*_cplusplus*/ /*@}*/ -#endif /*_FSL_FLEXIO_MCULCD_H_*/ +#endif /*FSL_FLEXIO_MCULCD_H_*/ diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c b/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c index 458ad8e72..0c52c4e8c 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -460,8 +460,12 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, /* Setup DMA to transfer data. */ /* Assert the nCS. */ FLEXIO_MCULCD_StartTransfer(base); - /* Send the command. */ - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } /* Setup the DMA configuration. */ FLEXIO_MCULCD_EDMAConfig(base, handle); diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.h b/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.h index 200440baa..eb2a4ce42 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.h +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd_edma.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_ -#define _FSL_FLEXIO_MCULCD_EDMA_H_ +#ifndef FSL_FLEXIO_MCULCD_EDMA_H_ +#define FSL_FLEXIO_MCULCD_EDMA_H_ #include "fsl_edma.h" #include "fsl_flexio_mculcd.h" @@ -23,7 +23,7 @@ /*@{*/ /*! @brief FlexIO MCULCD EDMA driver version. */ -#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*@}*/ /*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */ @@ -150,4 +150,4 @@ status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, /*! * @} */ -#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */ +#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */ diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c b/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c index 4159ba20a..3ca531505 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2021 NXP + * Copyright 2019-2021,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -195,6 +195,10 @@ status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, /* The shifter interrupt is used by the SMARTDMA. */ FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, (1UL << FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER)); +#if (defined(SMARTDMA_USE_FLEXIO_SHIFTER_DMA) && SMARTDMA_USE_FLEXIO_SHIFTER_DMA) + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL, true); +#endif + return kStatus_Success; } @@ -245,8 +249,12 @@ status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base, /* Assert the nCS. */ FLEXIO_MCULCD_StartTransfer(base); - /* Send the command. */ - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } if (part1Len > 0U) { diff --git a/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h b/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h index bbc8d4fa5..3500aaaed 100644 --- a/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h +++ b/drivers/flexio/mculcd/fsl_flexio_mculcd_smartdma.h @@ -1,12 +1,12 @@ /* - * Copyright 2019, 2021 NXP + * Copyright 2019,2021,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_MCULCD_SMARTDMA_H_ -#define _FSL_FLEXIO_MCULCD_SMARTDMA_H_ +#ifndef FSL_FLEXIO_MCULCD_SMARTDMA_H_ +#define FSL_FLEXIO_MCULCD_SMARTDMA_H_ #include "fsl_smartdma.h" #include "fsl_flexio_mculcd.h" @@ -22,7 +22,7 @@ /*@{*/ /*! @brief FlexIO MCULCD SMARTDMA driver version. */ -#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ /*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */ @@ -155,4 +155,4 @@ status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base, /*! * @} */ -#endif /* _FSL_FLEXIO_MCULCD_SMARTDMA_H_ */ +#endif /* FSL_FLEXIO_MCULCD_SMARTDMA_H_ */ diff --git a/drivers/flexio/spi/fsl_flexio_spi.c b/drivers/flexio/spi/fsl_flexio_spi.c index 53cf2030b..96c9a7c0a 100644 --- a/drivers/flexio/spi/fsl_flexio_spi.c +++ b/drivers/flexio/spi/fsl_flexio_spi.c @@ -1229,7 +1229,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, /* Enable transmit and receive interrupt to handle rx. */ FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); - + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } + return kStatus_Success; } @@ -1310,6 +1315,7 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) /* Receive interrupt. */ if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U) { + FLEXIO_SPI_TransferSendTransaction(base, handle); return; } diff --git a/drivers/flexio/spi/fsl_flexio_spi.h b/drivers/flexio/spi/fsl_flexio_spi.h index f90853e5f..338cf43ab 100644 --- a/drivers/flexio/spi/fsl_flexio_spi.h +++ b/drivers/flexio/spi/fsl_flexio_spi.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_SPI_H_ -#define _FSL_FLEXIO_SPI_H_ +#ifndef FSL_FLEXIO_SPI_H_ +#define FSL_FLEXIO_SPI_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexIO SPI driver version. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*@}*/ #ifndef FLEXIO_SPI_DUMMYDATA @@ -716,4 +716,4 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); #endif /*_cplusplus*/ /*@}*/ -#endif /*_FSL_FLEXIO_SPI_H_*/ +#endif /*FSL_FLEXIO_SPI_H_*/ diff --git a/drivers/flexio/spi/fsl_flexio_spi_edma.h b/drivers/flexio/spi/fsl_flexio_spi_edma.h index c71a1b1fd..670054898 100644 --- a/drivers/flexio/spi/fsl_flexio_spi_edma.h +++ b/drivers/flexio/spi/fsl_flexio_spi_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_SPI_EDMA_H_ -#define _FSL_FLEXIO_SPI_EDMA_H_ +#ifndef FSL_FLEXIO_SPI_EDMA_H_ +#define FSL_FLEXIO_SPI_EDMA_H_ #include "fsl_flexio_spi.h" #include "fsl_edma.h" diff --git a/drivers/flexio/uart/fsl_flexio_uart.c b/drivers/flexio/uart/fsl_flexio_uart.c index 0d308b16a..13890caee 100644 --- a/drivers/flexio/uart/fsl_flexio_uart.c +++ b/drivers/flexio/uart/fsl_flexio_uart.c @@ -1007,3 +1007,17 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) } } } + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/drivers/flexio/uart/fsl_flexio_uart.h b/drivers/flexio/uart/fsl_flexio_uart.h index 783c31885..bc82a0aee 100644 --- a/drivers/flexio/uart/fsl_flexio_uart.h +++ b/drivers/flexio/uart/fsl_flexio_uart.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_UART_H_ -#define _FSL_FLEXIO_UART_H_ +#ifndef FSL_FLEXIO_UART_H_ +#define FSL_FLEXIO_UART_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexIO UART driver version. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) /*@}*/ /*! @brief Retry times for waiting flag. */ @@ -571,6 +571,13 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart */ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base); + /*@}*/ #if defined(__cplusplus) @@ -578,4 +585,4 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); #endif /*_cplusplus*/ /*@}*/ -#endif /*_FSL_FLEXIO_UART_H_*/ +#endif /*FSL_FLEXIO_UART_H_*/ diff --git a/drivers/flexio/uart/fsl_flexio_uart_edma.h b/drivers/flexio/uart/fsl_flexio_uart_edma.h index 3f145ea6a..3809ad98a 100644 --- a/drivers/flexio/uart/fsl_flexio_uart_edma.h +++ b/drivers/flexio/uart/fsl_flexio_uart_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_UART_EDMA_H_ -#define _FSL_FLEXIO_UART_EDMA_H_ +#ifndef FSL_FLEXIO_UART_EDMA_H_ +#define FSL_FLEXIO_UART_EDMA_H_ #include "fsl_flexio_uart.h" #include "fsl_edma.h" @@ -175,4 +175,4 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, /*! @}*/ -#endif /* _FSL_UART_EDMA_H_ */ +#endif /* FSL_UART_EDMA_H_ */ diff --git a/drivers/gpio/fsl_gpio.c b/drivers/gpio/fsl_gpio.c index a9868a863..0f3b4020c 100644 --- a/drivers/gpio/fsl_gpio.c +++ b/drivers/gpio/fsl_gpio.c @@ -8,11 +8,18 @@ #include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.gpio" #endif +#if defined(GPIO_RSTS) +#define GPIO_RESETS_ARRAY GPIO_RSTS +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -36,6 +43,11 @@ static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ +#if defined(GPIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY; +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -53,7 +65,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base); * Code ******************************************************************************/ #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ - defined(FSL_FEATURE_SOC_PORT_COUNT) + defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY) static uint32_t GPIO_GetInstance(GPIO_Type *base) { uint32_t instance; @@ -102,6 +114,10 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config { assert(NULL != config); +#if defined(GPIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]); +#endif + if (config->pinDirection == kGPIO_DigitalInput) { base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); diff --git a/drivers/gpio/fsl_gpio.h b/drivers/gpio/fsl_gpio.h index b7f3bee80..ce943c5b6 100644 --- a/drivers/gpio/fsl_gpio.h +++ b/drivers/gpio/fsl_gpio.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ +#ifndef FSL_GPIO_H_ +#define FSL_GPIO_H_ #include "fsl_common.h" @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 2)) +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3)) /*@}*/ #if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) @@ -796,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib * @} */ -#endif /* _FSL_GPIO_H_*/ +#endif /* FSL_GPIO_H_*/ diff --git a/drivers/i3c/fsl_i3c.c b/drivers/i3c/fsl_i3c.c index 2f50aca54..5862a142a 100644 --- a/drivers/i3c/fsl_i3c.c +++ b/drivers/i3c/fsl_i3c.c @@ -431,7 +431,7 @@ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status) return result; } -static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) { status_t result = kStatus_Success; uint32_t status, errStatus; @@ -1391,6 +1391,7 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) { I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); } else { @@ -1409,9 +1410,12 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t { *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); rxSize--; - if ((!isRxAutoTerm) && (rxSize == 1U)) + if ((flags & (uint32_t)kI3C_TransferDisableRxTermFlag) == 0UL) { - base->MCTRL |= I3C_MCTRL_RDTERM(1U); + if ((!isRxAutoTerm) && (rxSize == 1U)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } } } } @@ -1506,6 +1510,7 @@ status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint3 if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) { I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); } else { @@ -1746,7 +1751,7 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans i3c_direction_t direction = transfer->direction; i3c_master_state_t masterState = I3C_MasterGetState(base); bool checkDdrState = false; - bool isRxAutoTerm; + i3c_rx_term_ops_t rxTermOps; /* Return an error if the bus is already in use not by us. */ checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; @@ -1770,11 +1775,48 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans } /* True: Set Rx termination bytes at start point, False: Set Rx termination one bytes in advance. */ - isRxAutoTerm = (transfer->dataSize <= 255U) ? true : false; + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + rxTermOps = kI3C_RxAutoTerm; + } + else + { + rxTermOps = kI3C_RxTermLastByte; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) { - if ((direction == kI3C_Read) && isRxAutoTerm) + if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm)) { result = I3C_MasterStartWithRxSize(base, transfer->busType, transfer->slaveAddress, direction, (uint8_t)transfer->dataSize); @@ -1783,6 +1825,16 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans { result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); } + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } if (true == I3C_MasterTransferNoStartFlag(base, transfer)) { @@ -1791,10 +1843,10 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans } else { - if (direction == kI3C_Read) + if ((direction == kI3C_Read) && (rxTermOps != kI3C_RxTermDisable)) { /* Can't set Rx termination more than one bytes in advance without START. */ - isRxAutoTerm = false; + rxTermOps = kI3C_RxTermLastByte; } } @@ -1831,7 +1883,7 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans /* Need to send repeated start if switching directions to read. */ if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) { - if (isRxAutoTerm) + if (rxTermOps == kI3C_RxAutoTerm) { result = I3C_MasterRepeatedStartWithRxSize(base, transfer->busType, transfer->slaveAddress, kI3C_Read, (uint8_t)transfer->dataSize); @@ -1846,10 +1898,16 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans I3C_MasterClearFlagsAndEnableIRQ(base); return result; } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } } } - if (isRxAutoTerm) + if (rxTermOps == kI3C_RxAutoTerm) { transfer->flags |= (uint32_t)kI3C_TransferRxAutoTermFlag; } @@ -2015,14 +2073,21 @@ static void I3C_TransferStateMachineSendCommandState(I3C_Type *base, { base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); - if (0UL == handle->transfer.dataSize) + if (handle->transfer.busType != kI3C_TypeI3CDdr) { - handle->state = (uint8_t)kWaitForCompletionState; + if (0UL == handle->transfer.dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } } else { - /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ - handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + handle->state = (uint8_t)kTransferDataState; } } else @@ -2051,7 +2116,7 @@ static void I3C_TransferStateMachineWaitRepeatedStartCompleteState(I3C_Type *bas if (handle->remainingBytes < 256U) { - handle->isRxAutoTerm = true; + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; stateParams->result = I3C_MasterRepeatedStartWithRxSize(base, handle->transfer.busType, handle->transfer.slaveAddress, kI3C_Read, (uint8_t)handle->remainingBytes); @@ -2120,11 +2185,10 @@ static void I3C_TransferStateMachineTransferDataState(I3C_Type *base, /* Move to stop when the transfer is done. */ if (--handle->remainingBytes == 0UL) { - handle->isRxAutoTerm = false; - handle->state = (uint8_t)kWaitForCompletionState; + handle->state = (uint8_t)kWaitForCompletionState; } - if (!handle->isRxAutoTerm && (handle->remainingBytes == 1UL)) + if ((handle->rxTermOps == kI3C_RxTermLastByte) && (handle->remainingBytes == 1UL)) { base->MCTRL |= I3C_MCTRL_RDTERM(1UL); } @@ -2281,6 +2345,32 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; } + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + /* Handle no start option. */ if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) { @@ -2326,7 +2416,7 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) { - handle->isRxAutoTerm = true; + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); } @@ -2381,6 +2471,19 @@ status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *hand /* Reset fifos. These flags clear automatically. */ base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + handle->rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + handle->rxTermOps = kI3C_RxAutoTerm; + } + else + { + handle->rxTermOps = kI3C_RxTermLastByte; + } + /* Generate commands to send. */ (void)I3C_InitTransferStateMachine(base, handle); @@ -3146,7 +3249,7 @@ static void I3C_SlaveTransferHandleBusStop(I3C_Type *base, I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; - if (handle->isBusy == true) + if (handle->isBusy) { handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; handle->transfer.completionStatus = kStatus_Success; @@ -3197,6 +3300,7 @@ static void I3C_SlaveTransferHandleTxReady(I3C_Type *base, if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) { handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; } if (NULL != handle->callback) { @@ -3243,6 +3347,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base, if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) { handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; } if (NULL != handle->callback) { diff --git a/drivers/i3c/fsl_i3c.h b/drivers/i3c/fsl_i3c.h index 33c2e83c5..f6a2d7fc4 100644 --- a/drivers/i3c/fsl_i3c.h +++ b/drivers/i3c/fsl_i3c.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_I3C_H_ -#define _FSL_I3C_H_ +#ifndef FSL_I3C_H_ +#define FSL_I3C_H_ #include "fsl_common.h" @@ -20,7 +20,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief I3C driver version */ -#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 10, 3)) +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 10, 6)) /*@}*/ /*! @brief Timeout times for waiting flag. */ @@ -254,6 +254,14 @@ typedef enum _i3c_rx_trigger_level kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ } i3c_rx_trigger_level_t; +/*! @brief I3C master read termination operations. */ +typedef enum _i3c_rx_term_ops +{ + kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */ + kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */ + kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */ +} i3c_rx_term_ops_t; + /*! @brief Structure with setting master IBI rules and slave registry. */ typedef struct _i3c_register_ibi_addr { @@ -326,8 +334,10 @@ enum _i3c_master_transfer_flags kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ + kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */ kI3C_TransferRxAutoTermFlag = - 0x10U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size except in I3C_MasterReceive. */ + 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */ + kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */ }; /*! @@ -357,7 +367,7 @@ struct _i3c_master_handle { uint8_t state; /*!< Transfer state machine current state. */ uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - bool isRxAutoTerm; /*!< Is read auto-termination configured. */ + i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */ i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ uint8_t ibiAddress; /*!< Slave address which request IBI. */ uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ @@ -776,6 +786,9 @@ void I3C_MasterDeinit(I3C_Type *base); /* Not static so it can be used from fsl_i3c_dma.c. */ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle); + /* Not static so it can be used from fsl_i3c_dma.c. */ status_t I3C_CheckForBusyBus(I3C_Type *base); @@ -1860,4 +1873,4 @@ void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t data } #endif -#endif /* _FSL_I3C_H_ */ +#endif /* FSL_I3C_H_ */ diff --git a/drivers/i3c/fsl_i3c_edma.c b/drivers/i3c/fsl_i3c_edma.c new file mode 100644 index 000000000..7601d3c7c --- /dev/null +++ b/drivers/i3c/fsl_i3c_edma.c @@ -0,0 +1,1055 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c_edma" +#endif + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_edma_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransmitDataState, + kReceiveDataState, + kStopState, + kWaitForCompletionState, + kAddressMatchState, +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_edma_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterDMAIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveDMAIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | + kI3C_SlaveBusStopFlag | /*kI3C_SlaveRxReadyFlag |*/ + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map I3C instance number to base pointer. */ +static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; + +/*! @brief Array to store the END byte of I3C teransfer. */ +static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + + if (transferDone) + { + /* Terminate following data if present. */ + i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.dataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) = + (uint8_t)i3cHandle->base->MRDATAB; + } +#endif + + /* Disable I3C Rx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK; + } +} + +static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + uint32_t instance; + + if (transferDone) + { + /* Disable I3C Tx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK; + + if (i3cHandle->transferCount != 1U) + { + instance = I3C_GetInstance(i3cHandle->base); + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U) + { + } + i3cHandle->base->MWDATABE = i3cEndByte[instance]; + } + } +} +/*! + * brief Prepares the transfer state machine and fills in the command buffer. + * param handle Master nonblocking driver handle. + */ +static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + /* Calculate command count and put into command buffer. */ + handle->subaddressCount = 0U; + if (xfer->subaddressSize != 0U) + { + for (uint32_t i = xfer->subaddressSize; i > 0U; i--) + { + handle->subaddressBuffer[handle->subaddressCount++] = (uint8_t)((xfer->subaddress) >> (8U * (i - 1U))); + } + } + + /* Start condition shall be ommited, switch directly to next phase */ + if (xfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransmitDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + } + else + { + if (xfer->subaddressSize != 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI3C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI3C_Read) + { + handle->state = (uint8_t)kReceiveDataState; + } + else + { + return kStatus_InvalidArgument; + } + } + + if (handle->transfer.direction == kI3C_Read) + { + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read); + } + + if (handle->state != (uint8_t)kStopState) + { + /* If repeated start is requested, send repeated start. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + } + } + + I3C_MasterTransferEDMAHandleIRQ(base, handle); + return result; +} + +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction) +{ + bool isEnableTxDMA = false; + bool isEnableRxDMA = false; + edma_transfer_config_t xferConfig; + uint32_t instance; + uint32_t address; + uint32_t width; + + handle->transferCount = dataSize; + + switch (direction) + { + case kI3C_Write: + if (dataSize != 1U) + { + address = (uint32_t)&base->MWDATAB1; + /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */ + instance = I3C_GetInstance(base); + i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U); + dataSize--; + } + else + { + address = (uint32_t)&base->MWDATABE; + } + EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize, + kEDMA_MemoryToPeripheral); + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txDmaHandle); + isEnableTxDMA = true; + width = 1U; + break; + + case kI3C_Read: +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + address = (uint32_t)&base->MRDATAB; + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxDmaHandle); + isEnableRxDMA = true; + width = 1U; + break; + + default: + /* This should never happen */ + assert(false); + break; + } + + I3C_MasterEnableDMA(base, isEnableTxDMA, isEnableRxDMA, width); +} + +static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t errStatus; + status_t result = kStatus_Success; + i3c_master_transfer_t *xfer; + size_t rxCount = 0; + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, status); + + i3c_master_state_t masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return result; + } + + if (handle->state == (uint8_t)kIBIWonState) + { + /* Get fifo counts and compute room in tx fifo. */ + rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + state_complete = true; + break; + + case (uint8_t)kIBIWonState: + if (masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + rxCount--; + break; + } + else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + state_complete = true; + result = kStatus_I3C_IBIWon; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kSendCommandState: + I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write); + + if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) + { + if (0UL == xfer->dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransmitDataState; + } + + state_complete = true; + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kReceiveDataState; + /* Send repeated start and slave address. */ + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); + } + + state_complete = true; + break; + + case (uint8_t)kTransmitDataState: + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Write); + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kReceiveDataState: + /* Do DMA read. */ + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kWaitForCompletionState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + if (xfer->busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + } + } + *isDone = true; + state_complete = true; + break; + + default: + assert(false); + break; + } + } + return result; +} + +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_MasterTransferEDMACallbackRx, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_MasterTransferEDMACallbackTx, handle); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterDMAIrqFlags); +} + +/*! + * brief Performs a non-blocking DMA transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts( + base, ((uint32_t)kMasterDMAIrqFlags | (uint32_t)kI3C_MasterRxReadyFlag | (uint32_t)kI3C_MasterTxReadyFlag)); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Generate commands to send. */ + (void)I3C_MasterInitTransferStateMachineEDMA(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)(kMasterDMAIrqFlags)); + + if (transfer->busType == kI3C_TypeI2C) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterSlaveStartFlag); + } + + return kStatus_Success; +} + +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + i3c_master_edma_handle_t *handle = (i3c_master_edma_handle_t *)i3cHandle; + + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_MasterRunTransferStateMachineEDMA(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + } + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + i3c_direction_t dir = handle->transfer.direction; + + if (dir == kI3C_Read) + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + + return kStatus_Success; +} + +/*! + * brief Abort a master edma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_MasterEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_slave_edma_handle_t *i3cHandle = (i3c_slave_edma_handle_t *)param; + + if (transferDone) + { + /* Simply disable dma enablement */ + if (i3cHandle->txDmaHandle == dmaHandle) + { + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMATB_MASK; + + if (i3cHandle->transfer.txDataSize > 1U) + { + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U) + { + } + /* Send the last byte. */ + i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U); + } + } + else + { +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.rxDataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) = + (uint8_t)i3cHandle->base->SRDATAB; + } +#endif + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK; + } + } +} + +/*! + * brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + * param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_SlaveTransferEDMACallback, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_SlaveTransferEDMACallback, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Enable IRQ. */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); +} + +static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + edma_transfer_config_t txConfig; + uint32_t *txFifoBase; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + + if (xfer->txDataSize == 1U) + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATABE; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize, + kEDMA_MemoryToPeripheral); + } + else + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U, + kEDMA_MemoryToPeripheral); + } + + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &txConfig); + EDMA_StartTransfer(handle->txDmaHandle); +} + +static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + uint32_t *rxFifoBase = (uint32_t *)(uintptr_t)&base->SRDATAB; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + size_t dataSize = xfer->rxDataSize; + edma_transfer_config_t rxConfig; + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + + EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig); + EDMA_StartTransfer(handle->rxDmaHandle); +} + +/*! + * brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param transfer The pointer to the transfer descriptor. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask) +{ + assert(NULL != handle); + assert(NULL != transfer); + + bool txDmaEn = false, rxDmaEn = false; + uint32_t width; + + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + /* Clear all flags. */ + I3C_SlaveClearErrorStatusFlags(base, (uint32_t)kSlaveErrorFlags); + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + + handle->transfer = *transfer; + + /* Set up event mask. */ + handle->eventMask = eventMask; + + if ((transfer->txData != NULL) && (transfer->txDataSize != 0U)) + { + I3C_SlavePrepareTxEDMA(base, handle); + txDmaEn = true; + width = 1U; + } + + if ((transfer->rxData != NULL) && (transfer->rxDataSize != 0U)) + { + I3C_SlavePrepareRxEDMA(base, handle); + rxDmaEn = true; + width = 1U; + } + + if (txDmaEn || rxDmaEn) + { + I3C_SlaveEnableDMA(base, txDmaEn, rxDmaEn, width); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + uint32_t flags; + uint32_t errFlags; + i3c_slave_edma_transfer_t *xfer; + + i3c_slave_edma_handle_t *handle = (i3c_slave_edma_handle_t *)i3cHandle; + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, flags); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + if (handle->isBusy == true) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + I3C_SlaveTransferAbortEDMA(base, handle); + } + else + { + return; + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } +} + +/*! + * brief Abort a slave dma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + if (handle->isBusy != false) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_SlaveEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } +} \ No newline at end of file diff --git a/drivers/i3c/fsl_i3c_edma.h b/drivers/i3c/fsl_i3c_edma.h new file mode 100644 index 000000000..1e896e8de --- /dev/null +++ b/drivers/i3c/fsl_i3c_edma.h @@ -0,0 +1,279 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_EDMA_H_ +#define FSL_I3C_EDMA_H_ + +#include "fsl_i3c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I3C EDMA driver version. */ +#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 8)) +/*@}*/ + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_edma_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} i3c_master_edma_callback_t; +/*! + * @brief Driver handle for master EDMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint8_t subaddressBuffer[4]; /*!< Saving subaddress command. */ + uint8_t subaddressCount; /*!< Saving command count. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i3c_master_edma_callback_t callback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ +}; + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t; + +/*! @brief I3C slave transfer structure */ +typedef struct _i3c_slave_edma_transfer +{ + uint32_t event; /*!< Reason the callback is being invoked. */ + uint8_t *txData; /*!< Transfer buffer */ + size_t txDataSize; /*!< Transfer size */ + uint8_t *rxData; /*!< Transfer buffer */ + size_t rxDataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI3C_SlaveCompletionEvent. */ +} i3c_slave_edma_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave DMA transfer API. + * + * @param base Base address for the I3C instance on which the event occurred. + * @param handle Pointer to slave DMA transfer handle. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData); +/*! + * @brief I3C slave edma handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_slave_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + i3c_slave_edma_transfer_t transfer; /*!< I3C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i3c_slave_edma_callback_t callback; /*!< Callback function called at transfer event. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; +/*! @} */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the I3C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I3C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * DMA peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master DMA driver handle. + */ +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ + +/*! @name Slave DMA */ +/*@{*/ +/*! + * @brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param transfer The pointer to the transfer descriptor. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * @retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask); +/*! + * @brief Abort a slave edma non-blocking transfer in a early time + * + * @param base I3C peripheral base address + * @param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave DMA driver handle. + */ +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*@}*/ + +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_EDMA_H_ */ \ No newline at end of file diff --git a/drivers/inputmux/fsl_inputmux.c b/drivers/inputmux/fsl_inputmux.c index 2f632ebf5..1f2ce0bcd 100644 --- a/drivers/inputmux/fsl_inputmux.c +++ b/drivers/inputmux/fsl_inputmux.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,9 +17,54 @@ #define FSL_COMPONENT_ID "platform.drivers.inputmux" #endif +#if defined(INPUTMUX_RSTS) +#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! + * @brief Get instance number for INPUTMUX module. + * + * @param base INPUTMUX peripheral base address + */ +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! @brief Pointers to INPUTMUX bases for each instance. */ +static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++) + { + if (s_inputmuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_inputmuxBases)); + + return instance; +} +#endif /*! * brief Initialize INPUTMUX peripheral. @@ -42,16 +87,26 @@ void INPUTMUX_Init(INPUTMUX_Type *base) CLOCK_EnableClock(kCLOCK_InputMux); #endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(INPUTMUX_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]); +#endif } /*! * brief Attaches a signal * - * This function gates the INPUTPMUX clock. + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter p index specified as 2, this function configures register PINT_SEL2. * * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. + * param index The serial number of destination register in the group of INPUTMUX registers with same name. + * param connection Applies signal from source signals collection to target signal. * * retval None. */ diff --git a/drivers/inputmux/fsl_inputmux.h b/drivers/inputmux/fsl_inputmux.h index 7be58c3ad..c3cf9ccdd 100644 --- a/drivers/inputmux/fsl_inputmux.h +++ b/drivers/inputmux/fsl_inputmux.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ +#ifndef FSL_INPUTMUX_H_ +#define FSL_INPUTMUX_H_ #include "fsl_inputmux_connections.h" #include "fsl_common.h" @@ -27,7 +27,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) /*@}*/ /******************************************************************************* @@ -52,11 +52,17 @@ void INPUTMUX_Init(INPUTMUX_Type *base); /*! * @brief Attaches a signal * - * This function gates the INPUTPMUX clock. + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * @code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * @endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter @p index specified as 2, this function configures register PINT_SEL2. * * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. + * @param index The serial number of destination register in the group of INPUTMUX registers with same name. + * @param connection Applies signal from source signals collection to target signal. * * @retval None. */ @@ -94,4 +100,4 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base); /*@}*/ -#endif /* _FSL_INPUTMUX_H_ */ +#endif /* FSL_INPUTMUX_H_ */ diff --git a/drivers/intm/fsl_intm.c b/drivers/intm/fsl_intm.c new file mode 100644 index 000000000..b62eb585b --- /dev/null +++ b/drivers/intm/fsl_intm.c @@ -0,0 +1,86 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_intm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.intm" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Fill in the INTM config struct with the default settings + * + * The default values are: + * code + * config[0].irqnumber = NotAvail_IRQn; + * config[0].maxtimer = 1000U; + * config[1].irqnumber = NotAvail_IRQn; + * config[1].maxtimer = 1000U; + * config[2].irqnumber = NotAvail_IRQn; + * config[2].maxtimer = 1000U; + * config[3].irqnumber = NotAvail_IRQn; + * config[3].maxtimer = 1000U; + * config->enable = false; + * endcode + * param config Pointer to user's INTM config structure. + */ +void INTM_GetDefaultConfig(intm_config_t *config) +{ + assert(config); + + for (uint32_t i = 0; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++) + { + config->intm[i].irqnumber = NotAvail_IRQn; + config->intm[i].maxtimer = 1000U; + } + + /* INTM cycle count timer mode disable*/ + config->enable = false; +} + +/*! + * brief Ungates the INTM clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the INTM driver. + * + * param base INTM peripheral base address + * param config Pointer to user's INTM config structure. + */ +void INTM_Init(INTM_Type *base, const intm_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Intm); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++) + { + base->MON[i].INTM_IRQSEL = INTM_MON_INTM_IRQSEL_IRQ(config->intm[i].irqnumber); + base->MON[i].INTM_LATENCY = INTM_MON_INTM_LATENCY_LAT(config->intm[i].maxtimer); + } + + INTM_EnableCycleCount(base, config->enable); +} + +/*! + * brief Disables the INTM module. + * + * param base INTM peripheral base address + */ +void INTM_Deinit(INTM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the INTM clock*/ + CLOCK_DisableClock(kCLOCK_Intm); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/drivers/intm/fsl_intm.h b/drivers/intm/fsl_intm.h new file mode 100644 index 000000000..7e0410b3c --- /dev/null +++ b/drivers/intm/fsl_intm.h @@ -0,0 +1,207 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_INTM_H_ +#define FSL_INTM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup intm + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief INTM driver version. */ +#define FSL_INTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Interrupt monitors. */ +typedef enum _intm_monitor +{ + kINTM_Monitor1 = 0U, + kINTM_Monitor2, + kINTM_Monitor3, + kINTM_Monitor4 +} intm_monitor_t; + +/*! @brief INTM interrupt source configuration structure. */ +typedef struct _intm_monitor_config +{ + uint32_t maxtimer; /*!< Set the maximum timer */ + IRQn_Type irqnumber; /*!< Select the interrupt request number to monitor. */ +} intm_monitor_config_t; + +/*! @brief INTM configuration structure. */ +typedef struct _intm_config +{ + intm_monitor_config_t intm[FSL_FEATURE_INTM_MONITOR_COUNT]; /*! Interrupt source monitor config.*/ + bool enable; /*!< enables the cycle count timer on a monitored interrupt request for comparison to the latency + register. */ +} intm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Fill in the INTM config struct with the default settings + * + * The default values are: + * @code + * config[0].irqnumber = NotAvail_IRQn; + * config[0].maxtimer = 1000U; + * config[1].irqnumber = NotAvail_IRQn; + * config[1].maxtimer = 1000U; + * config[2].irqnumber = NotAvail_IRQn; + * config[2].maxtimer = 1000U; + * config[3].irqnumber = NotAvail_IRQn; + * config[3].maxtimer = 1000U; + * config->enable = false; + * @endcode + * @param config Pointer to user's INTM config structure. + */ +void INTM_GetDefaultConfig(intm_config_t *config); + +/*! + * @brief Ungates the INTM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the INTM driver. + * + * @param base INTM peripheral base address + * @param config Pointer to user's INTM config structure. + */ +void INTM_Init(INTM_Type *base, const intm_config_t *config); + +/*! + * @brief Disables the INTM module. + * + * @param base INTM peripheral base address + */ +void INTM_Deinit(INTM_Type *base); + +/*! + * @brief Enable the cycle count timer mode. + * + * Monitor mode enables the cycle count timer on a monitored interrupt request for comparison to the latency register. + * + * @param base INTM peripheral base address. + * @param enable Enable the cycle count or not. + */ +static inline void INTM_EnableCycleCount(INTM_Type *base, bool enable) +{ + if (enable) + { + base->INTM_MM |= INTM_INTM_MM_MM_MASK; + } + else + { + base->INTM_MM &= ~INTM_INTM_MM_MM_MASK; + } +} + +/*! + * @brief Interrupt Acknowledge. + * + * Call this function in ISR to acknowledge interrupt. + * + * @param base INTM peripheral base address. + * @param irq Handle interrupt number. + */ +static inline void INTM_AckIrq(INTM_Type *base, IRQn_Type irq) +{ + assert(((uint32_t)irq) < (uint32_t)NUMBER_OF_INT_VECTORS); + + base->INTM_IACK = (uint32_t)irq; +} + +/*! + * @brief Interrupt Request Select. + * + * This function is used to set the interrupt request number to monitor or check. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * @param irq Interrupt request number to monitor. + * + * @return Select the interrupt request number to monitor. + */ +static inline void INTM_SetInterruptRequestNumber(INTM_Type *base, intm_monitor_t intms, IRQn_Type irq) +{ + assert(((uint32_t)irq) < (uint32_t)NUMBER_OF_INT_VECTORS); + + base->MON[intms].INTM_IRQSEL = INTM_MON_INTM_IRQSEL_IRQ(irq); +} + +/*! + * @brief Set the maximum count time. + * + * This function is to set the maximum time from interrupt generation to confirmation. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * @param count Timer maximum count. + */ +static inline void INTM_SetMaxTime(INTM_Type *base, intm_monitor_t intms, uint32_t count) +{ + assert((count < 0xFFFFFDU) && (count > 0U)); + + base->MON[intms].INTM_LATENCY = INTM_MON_INTM_LATENCY_LAT(count); +} + +/*! + * @brief Clear the timer period in units of count. + * + * This function is used to clear the INTM_TIMERa register. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + */ +static inline void INTM_ClearTimeCount(INTM_Type *base, intm_monitor_t intms) +{ + base->MON[intms].INTM_TIMER &= ~INTM_MON_INTM_TIMER_TIMER_MASK; +} + +/*! + * @brief Gets the timer period in units of count. + * + * This function is used to get the number of INTM clock cycles from interrupt request to confirmation interrupt + * processing. If this number exceeds the set maximum time, will be an error signal. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + */ +static inline uint32_t INTM_GetTimeCount(INTM_Type *base, intm_monitor_t intms) +{ + return base->MON[intms].INTM_TIMER; +} + +/*! + * @brief Interrupt monitor status. + * + * This function indicates whether the INTM_TIMERa value has exceeded the INTM_LATENCYa value. + * If any interrupt source in INTM_TIMERa exceeds the programmed delay value, the monitor state + * can be cleared by calling the INTM_ClearTimeCount() API to clear the corresponding INTM_TIMERa register. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * + * @return Whether INTM_TIMER value has exceeded INTM_LATENCY value. + * false:INTM_TIMER value has not exceeded the INTM_LATENCY value; + * true:INTM_TIMER value has exceeded the INTM_LATENCY value. + */ +static inline bool INTM_GetStatusFlags(INTM_Type *base, intm_monitor_t intms) +{ + return ((base->MON[intms].INTM_STATUS & INTM_MON_INTM_STATUS_STATUS_MASK) != 0U); +} + +/*! @} */ +#endif /* FSL_INTM_H_*/ diff --git a/drivers/irtc/fsl_irtc.h b/drivers/irtc/fsl_irtc.h index c1c092b2e..98f78be18 100644 --- a/drivers/irtc/fsl_irtc.h +++ b/drivers/irtc/fsl_irtc.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2022 NXP + * Copyright 2016-2019, 2022-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_IRTC_H_ -#define _FSL_IRTC_H_ +#ifndef FSL_IRTC_H_ +#define FSL_IRTC_H_ #include "fsl_common.h" @@ -21,7 +21,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version. */ +#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version. */ /*@}*/ #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT @@ -346,7 +346,7 @@ static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask) #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) { base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; } @@ -367,14 +367,14 @@ static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask) #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM if (0U != (mask & (uint32_t)kIRTC_WakeTimerInterruptEnable)) { - base->WAKE_TIMER_CTRL &= ~RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + base->WAKE_TIMER_CTRL &= ~(uint16_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; } #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) { - base->TAMPER_QSCR &= ~RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + base->TAMPER_QSCR &= ~(uint16_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; } #endif #endif @@ -392,11 +392,11 @@ static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base) { uint32_t intsEnabled = base->IER; #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - intsEnabled |= (base->WAKE_TIMER_CTRL & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; + intsEnabled |= (base->WAKE_TIMER_CTRL & (uint32_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - intsEnabled |= (base->TAMPER_QSCR & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; + intsEnabled |= (base->TAMPER_QSCR & (uint32_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; #endif #endif @@ -849,4 +849,4 @@ static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base) /*! @}*/ -#endif /* _FSL_IRTC_H_ */ +#endif /* FSL_IRTC_H_ */ diff --git a/drivers/itrc/fsl_itrc.c b/drivers/itrc/fsl_itrc.c index af31f6c18..27120e076 100644 --- a/drivers/itrc/fsl_itrc.c +++ b/drivers/itrc/fsl_itrc.c @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -16,10 +16,14 @@ #define FSL_COMPONENT_ID "platform.drivers.itrc" #endif -#define b11 0x3u +#define b11 0x3UL #define b10 0x2u #define b01 0x1u +#define OUT_SEL_0_COUNT (16u) +#define OUT_SEL_1_COUNT (32u) +#define OUT_SEL_2_COUNT (48u) + /* Value used to trigger SW Events */ #define SW_EVENT_VAL 0x5AA55AA5u @@ -54,7 +58,7 @@ __WEAK void ITRC0_DriverIRQHandler(void) status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word) { /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ - if ((word & ~(IN_EVENTS_MASK | OUT_ACTIONS_MASK)) != 0u) + if ((word & ~(IN_0_15_EVENTS_MASK | OUT_ACTIONS_MASK)) != 0u) { return kStatus_InvalidArgument; } @@ -64,17 +68,72 @@ status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word) return kStatus_Success; } +/*! + * brief Get ITRC Status + * + * This function returns ITRC STATUS1 register value. + * + * param base ITRC peripheral base address + * return Value of ITRC STATUS register + */ +uint32_t ITRC_GetStatus(ITRC_Type *base) +{ + return base->STATUS; +} + +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) +/*! + * brief Clear ITRC status 1 + * + * This function clears corresponding ITRC event or action in STATUS1 register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS1 register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus1(ITRC_Type *base, uint32_t word) +{ + /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ + if ((word & ~(IN_16_47_EVENTS_MASK)) != 0u) + { + return kStatus_InvalidArgument; + } + + base->STATUS1 |= word; + + return kStatus_Success; +} + +/*! + * brief Get ITRC Status 1 + * + * This function returns ITRC STATUS1 register value. + * + * param base ITRC peripheral base address + * return Value of ITRC STATUS1 register + */ +uint32_t ITRC_GetStatus1(ITRC_Type *base) +{ + return base->STATUS1; +} + +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ + /*! * brief Clear all ITRC status * - * This clears all event and action status. + * This clears all event and action in STATUS and STATUS1 registers. * * param base ITRC peripheral base address - * return Status of the ITRC + * return kStatus_Success */ status_t ITRC_ClearAllStatus(ITRC_Type *base) { - base->STATUS |= (IN_EVENTS_MASK | OUT_ACTIONS_MASK); + base->STATUS |= (IN_0_15_EVENTS_MASK | OUT_ACTIONS_MASK); +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) + base->STATUS1 |= (IN_16_47_EVENTS_MASK); +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ return kStatus_Success; } @@ -147,67 +206,65 @@ status_t ITRC_SetActionToEvent( } /* Compute index for INx_SEL0/1 bit-field within OUTy_SEL0/1 registers */ - index = 2u * in; - /* Prepare AND mask to set INx_SEL0 accordingly */ - select_AND_mask = ~(b11 << index); - - /* Last possible index in OUTx_SELy registers is 30 */ - if (index > 30u) + if ((uint32_t)in < OUT_SEL_0_COUNT) + { + index = 2u * (uint32_t)in; + } + else if (OUT_SEL_0_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_1_COUNT) + { + index = 2u * ((uint32_t)in - OUT_SEL_0_COUNT); + } + else if (OUT_SEL_1_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_2_COUNT) + { + index = 2u * ((uint32_t)in - OUT_SEL_1_COUNT); + } + else { return kStatus_InvalidArgument; } - switch (out) + /* Prepare AND mask to set INx_SEL0 accordingly */ + select_AND_mask = ~(uint32_t)(b11 << index); + + /* Configure OUT action for IN event */ + for (uint8_t i = (uint8_t)kITRC_Irq; i < ITRC_OUT_COUNT; i++) { - case kITRC_Irq: - base->OUT0_SEL0 = (base->OUT0_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT0_SEL1 |= sel1 << index; - break; - case kITRC_CssReset: - base->OUT1_SEL0 = (base->OUT1_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT1_SEL1 |= sel1 << index; - break; - - case kITRC_PufZeroize: - base->OUT2_SEL0 = (base->OUT2_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT2_SEL1 |= sel1 << index; - break; - - case kITRC_RamZeroize: - base->OUT3_SEL0 = (base->OUT3_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT3_SEL1 |= sel1 << index; - break; - - case kITRC_ChipReset: - base->OUT4_SEL0 = (base->OUT4_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT4_SEL1 |= sel1 << index; - break; - - case kITRC_TamperOut: - base->OUT5_SEL0 = (base->OUT5_SEL0 & select_AND_mask) | (sel0 << index); - base->OUT5_SEL1 |= sel1 << index; - break; - default: - /* This case shouldn't be reached. */ - return kStatus_InvalidArgument; + /* Loop over all OUT actions, set only requested one */ + if (i == (uint8_t)out) + { + if ((uint32_t)in < OUT_SEL_0_COUNT) + { + base->OUT_SEL[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL[i][1] |= sel1 << index; + break; + } +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT) + else if (OUT_SEL_0_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_1_COUNT) + { + base->OUT_SEL_1[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL_1[i][1] |= sel1 << index; + break; + } +#endif /* defined(OUT_SEL_1) */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT) + else if (OUT_SEL_1_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_2_COUNT) + { + base->OUT_SEL_2[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL_2[i][1] |= sel1 << index; + break; + } + else + { + /* All the cases have been listed above, this branch should not be reached. */ + return kStatus_InvalidArgument; + } +#endif /* defined(OUT_SEL_2) */ + } } return kStatus_Success; } -/*! - * brief Get ITRC Status - * - * This function returns ITRC register status. - * - * param base ITRC peripheral base address - * return Value of ITRC STATUS register - */ -status_t ITRC_GetStatus(ITRC_Type *base) -{ - return base->STATUS; -} - /*! * brief Initialize ITRC * diff --git a/drivers/itrc/fsl_itrc.h b/drivers/itrc/fsl_itrc.h index 877134aa4..6e0817da6 100644 --- a/drivers/itrc/fsl_itrc.h +++ b/drivers/itrc/fsl_itrc.h @@ -1,11 +1,11 @@ /* - * Copyright 2021 NXP + * Copyright 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_ITRC_H_ -#define _FSL_ITRC_H_ +#ifndef FSL_ITRC_H_ +#define FSL_ITRC_H_ #include "fsl_common.h" @@ -22,34 +22,103 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Defines ITRC driver version 2.1.0. +/*! @brief Defines ITRC driver version 2.3.0. * * Change log: + * - Version 2.3.0 + * - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM + * - Version 2.2.0 + * - Update driver to new version and input events * - Version 2.1.0 * - Make SYSCON glitch platform dependent * - Version 2.0.0 * - initial version */ -#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ typedef enum _itrc_input_signals { - kITRC_CssGlitch = 0U, - kITRC_RtcTamper = 1U, - kITRC_Cdog = 2U, - kITRC_BodVbat = 3u, - kITRC_BodVdd = 4u, - kITRC_Watchdog = 5u, - kITRC_FlashEcc = 6u, - kITRC_Ahb = 7u, - kITRC_CssErr = 8u, + kITRC_Glitch = 0U, + kITRC_Tamper = 1U, + kITRC_Cdog = 2U, + kITRC_BodVbat = 3u, + kITRC_BodVdd = 4u, + kITRC_Watchdog = 5u, + kITRC_FlashEcc = 6u, + kITRC_Ahb = 7u, + kITRC_ElsErr = 8u, #if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) kITRC_SysconGlitch = 9u, #endif - kITRC_Pkc = 10u, - kITRC_SwEvent1 = 14u, - kITRC_SwEvent2 = 15u + kITRC_Pkc = 10u, +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) + kITRC_Cdog1 = 11u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) + kITRC_Watchdog1 = 12u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK*/ +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) + kITRC_Freqme = 13u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */ + kITRC_SwEvent0 = 14u, + kITRC_SwEvent1 = 15u, +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) + kITRC_VddSysLow = 16u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) + kITRC_VddIoLow = 17u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) + kITRC_VddTemp = 19u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) + kITRC_VddClock = 20u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) + kITRC_INTM0 = 21u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) + kITRC_INTM1 = 22u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) + kITRC_INTM2 = 23u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) + kITRC_INTM3 = 24u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) && \ + defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) + kITRC_SoCTrim0 = 25u, + kITRC_SoCTrim1 = 26u, + kITRC_SoCTrim2 = 27u, + kITRC_SoCTrim3 = 28u, + kITRC_SoCTrim4 = 29u, + kITRC_SoCTrim5 = 30u, + kITRC_SoCTrim6 = 31u, + kITRC_SoCTrim7 = 32u, +#endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) + kITRC_GdetSfr = 33u, +#endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) + kITRC_VddCore = 34u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) + kITRC_VddSys = 35u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) + kITRC_VddIo = 36u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) + kITRC_FlexspiGcm = 37u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) + kITRC_Sm3Err = 46u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) + kITRC_TrngErr = 47u, +#endif /* */ } itrc_input_signals_t; typedef enum _itrc_lock @@ -66,33 +135,54 @@ typedef enum _itrc_enable typedef enum _itrc_out_signals { - kITRC_Irq = 16U, - kITRC_CssReset = 17U, - kITRC_PufZeroize = 18U, - kITRC_RamZeroize = 19u, - kITRC_ChipReset = 20u, - kITRC_TamperOut = 21u, + kITRC_Irq = 0U, + kITRC_ElsReset = 1U, + kITRC_PufZeroize = 2U, + kITRC_RamZeroize = 3u, + kITRC_ChipReset = 4u, + kITRC_TamperOut = 5u, + kITRC_TamperOut1 = 6u, } itrc_out_signals_t; +/* Inputs 0 to 15 events mask */ #if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) -#define IN_EVENTS_MASK \ +#define IN_0_15_EVENTS_MASK \ (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ ITRC_STATUS_IN9_STATUS_MASK | ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | \ ITRC_STATUS_IN15_STATUS_MASK) #else -#define IN_EVENTS_MASK \ +#define IN_0_15_EVENTS_MASK \ (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | ITRC_STATUS_IN15_STATUS_MASK) #endif /* FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH */ +/* Inputs 15 to 47 events mask */ +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) && defined(ITRC_STATUS1_IN47_STATUS) +#define IN_16_47_EVENTS_MASK \ + (ITRC_STATUS1_IN16_STATUS_MASK | ITRC_STATUS1_IN17_STATUS_MASK | ITRC_STATUS1_IN18_STATUS_MASK | \ + ITRC_STATUS1_IN19_STATUS_MASK | ITRC_STATUS1_IN20_STATUS_MASK | ITRC_STATUS1_IN24_21_STATUS_MASK | \ + ITRC_STATUS1_IN24_21_STATUS_MASK | ITRC_STATUS1_IN32_25_STATUS_MASK | ITRC_STATUS1_IN33_STATUS_MASK | \ + ITRC_STATUS1_IN34_STATUS_MASK | ITRC_STATUS1_IN35_STATUS_MASK | ITRC_STATUS1_IN36_STATUS_MASK | \ + ITRC_STATUS1_IN37_STATUS_MASK | ITRC_STATUS1_IN46_STATUS_MASK | ITRC_STATUS1_IN47_STATUS_MASK) +#endif /* ITRC_STATUS1_IN16_STATUS_MASK && ITRC_STATUS1_IN47_STATUS */ + +/* Output actions mask */ +#if defined(ITRC_STATUS_OUT6_STATUS) +#define OUT_ACTIONS_MASK \ + (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ + ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK | \ + ITRC_STATUS_OUT6_STATUS_MASK) +#else #define OUT_ACTIONS_MASK \ (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK) +#endif /* ITRC_STATUS_OUT6_STATUS */ +#define ITRC_OUT_COUNT (7u) #ifndef ITRC #define ITRC ITRC0 #endif @@ -153,7 +243,7 @@ void ITRC_SetSWEvent1(ITRC_Type *base); * @param base ITRC peripheral base address * @return Value of ITRC STATUS register */ -status_t ITRC_GetStatus(ITRC_Type *base); +uint32_t ITRC_GetStatus(ITRC_Type *base); /*! * @brief Clear ITRC status @@ -167,6 +257,30 @@ status_t ITRC_GetStatus(ITRC_Type *base); */ status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word); +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) +/*! + * @brief Get ITRC Status 1 + * + * This function returns ITRC STATUS1 register value. + * + * @param base ITRC peripheral base address + * @return Value of ITRC STATUS1 register + */ +uint32_t ITRC_GetStatus1(ITRC_Type *base); + +/*! + * brief Clear ITRC status 1 + * + * This function clears corresponding ITRC event or action in STATUS1 register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS1 register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus1(ITRC_Type *base, uint32_t word); +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ + /*! * @brief Clear All ITRC status * @@ -205,4 +319,4 @@ void ITRC_Deinit(ITRC_Type *base); /*! @}*/ /* end of group itrc */ -#endif /* _FSL_ITRC_H_ */ +#endif /* FSL_ITRC_H_ */ diff --git a/drivers/lpadc/fsl_lpadc.c b/drivers/lpadc/fsl_lpadc.c index ec56b8545..a2f09027d 100644 --- a/drivers/lpadc/fsl_lpadc.c +++ b/drivers/lpadc/fsl_lpadc.c @@ -1,845 +1,977 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE -/*! - * @brief Get gain conversion result . - * - * @param gainAdjustment gain adjustment value. - */ -static uint32_t LPADC_GetGainConvResult(float gainAdjustment); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - /* - * $Branch Coverage Justification$ - * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base - * address is always valid and checked by assert. - */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - /* - * $Branch Coverage Justification$ - * (s_lpadcBases[instance] != base) not covered. The peripheral base - * address is always valid and checked by assert. - */ - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE -/*! - * brief Get gain conversion Result . - * - * param gainAdjustment gain adjustment value. - */ -static uint32_t LPADC_GetGainConvResult(float gainAdjustment) -{ - uint16_t i = 0U; - uint32_t tmp32 = 0U; - uint32_t GCRa[17] = {0}; - uint32_t GCALR = 0U; - - for (i = 0x11U; i > 0U; i--) - { - tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))); - GCRa[i - 1U] = tmp32; - gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))); - } - /* Get GCALR value calculated */ - for (i = 0x11U; i > 0U; i--) - { - GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL))); - } - - - /* to return GCALR value calculated */ - return GCALR; -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - -#if !(defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 0)) - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; -#if !(defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 0)) - config->powerLevelMode = kLPADC_PowerLevelAlt1; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ - config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - while (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - /* while loop until FIFO is not empty */ - tmp32 = base->RESFIFO[index]; - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0U; - - while (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - /* while loop until FIFO is not empty */ - tmp32 = base->RESFIFO; - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) -#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) - | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH - tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */ -#endif -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE - tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN - /* Enable alternate channel B.*/ - if (config->enableChannelB) - { - tmp32 |= ADC_CMDL_ALTBEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ - - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelBScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config ->alternateChannelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * config->enableChannelB = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE - config->channelBScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH - config->channelBNumber = 0U; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN - config->enableChannelB = false; /* Enable alternate channel B.*/ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - LPADC_PrepareAutoCalibration(base); - LPADC_FinishAutoCalibration(base); -} - -/*! - * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. - * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. - * - * param base LPADC peripheral base address. - */ -void LPADC_PrepareAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; -} - -/*! - * brief Finish auto calibration start with LPADC_PrepareAutoCalibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_FinishAutoCalibration(ADC_Type *base) -{ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE - int32_t GCCa; - int32_t GCCb; - float GCRa; - float GCRb; -#else - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ - - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE - /* Calculate gain offset. */ - GCCa = (int32_t)((base->GCC[0] & ADC_GCC_GAIN_CAL_MASK)); - GCCb = (int32_t)((base->GCC[1] & ADC_GCC_GAIN_CAL_MASK)); - - if (0U != ((base->GCC[0]) & 0x8000U)) - { - GCCa = GCCa - 0x10000; - GCRa = (float)((131072.0) / - (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ - base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ - } - - if (0U != ((base->GCC[1]) & 0x8000U)) - { - GCCb = GCCb - 0x10000; - GCRb = (float)((131072.0) / - (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ - base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ - } -#else - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ - -/*! - * brief Get calibration value into the memory which is defined by invoker. - * - * note Please note the ADC will be disabled temporary. - * note This function should be used after finish calibration. - * - * param base LPADC peripheral base address. - * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered - * on even in low power modes. - */ -void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue) -{ - assert(ptrCalibrationValue != NULL); - - bool adcEnabled = false; - - /* Check if ADC is enabled. */ - if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) - { - LPADC_Enable(base, false); - adcEnabled = true; - } - -#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) - uint32_t i; - for (i = 0UL; i < 33UL; i++) - { -#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) - ptrCalibrationValue->generalCalibrationValueA[i] = - (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU); - ptrCalibrationValue->generalCalibrationValueB[i] = - (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU); -#else - ptrCalibrationValue->generalCalibrationValueA[i] = - (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU); - ptrCalibrationValue->generalCalibrationValueB[i] = - (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU); - -#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ - - ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); - ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); - - if (adcEnabled) - { - LPADC_Enable(base, true); - } -} - -/*! - * brief Set calibration value into ADC calibration registers. - * - * note Please note the ADC will be disabled temporary. - * - * param base LPADC peripheral base address. - * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value. - */ -void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue) -{ - assert(ptrCalibrationValue != NULL); - - bool adcEnabled = false; - - /* Check if ADC is enabled. */ - if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) - { - LPADC_Enable(base, false); - adcEnabled = true; - } - -#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) - for (uint32_t i = 0UL; i < 33UL; i++) - { -#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) - *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; - *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; -#else - *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; - *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; -#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ - - base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; - base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; - /* - * $Branch Coverage Justification$ - * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible, - * the calibration ready state is too short not to catch. - */ - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } - - if (adcEnabled) - { - LPADC_Enable(base, true); - } -} - -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +#ifndef ADC_VERID_DIFFEN_MASK +#define ADC_VERID_DIFFEN_MASK (0x2U) +#endif /* ADC_VERID_DIFFEN_MASK */ + +#ifndef ADC_VERID_NUM_SEC_MASK +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#endif /* ADC_VERID_NUM_SEC_MASK */ + +#define ADC_CMDL_CHANNEL_MODE_MASK (0x60U) +#define ADC_CMDL_CHANNEL_MODE_SHIFT (5U) +#define ADC_CMDL_CHANNEL_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK) + +#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U) + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES +#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES +#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI +#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + +#if defined(LPADC_RSTS) +#define LPADC_RESETS_ARRAY LPADC_RSTS +#elif defined(ADC_RSTS) +#define LPADC_RESETS_ARRAY ADC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * @brief Get gain conversion result . + * + * @param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(LPADC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpadcResets[] = LPADC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_lpadcBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) +/*! + * brief Get gain conversion Result . + * + * param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment) +{ + uint16_t i = 0U; + uint32_t tmp32 = 0U; + uint32_t GCRa[17] = {0}; + uint32_t GCALR = 0U; + + for (i = 0x11U; i > 0U; i--) + { + tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))); + GCRa[i - 1U] = tmp32; + gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))); + } + /* Get GCALR value calculated */ + for (i = 0x11U; i > 0U; i--) + { + GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL))); + } + + /* to return GCALR value calculated */ + return GCALR; +} +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPADC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]); +#endif + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + ); + + tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy)); + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES) + tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) + tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) + tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + config->powerLevelMode = kLPADC_PowerLevelAlt1; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * brief Get the result in conversion FIFOn using blocking method. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO[index]; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0 to 3. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */ +#endif +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + assert(((config->sampleChannelMode == kLPADC_SampleChannelDiffBothSide) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) && + (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + + tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + /* Enable alternate channel B.*/ + if (config->enableChannelB) + { + tmp32 |= ADC_CMDL_ALTBEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ + + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be + * made before setting the CV register. + */ + + if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT)) + { + /* Set CV register. */ + base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelBScaleMode = kLPADC_SampleFullScale; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * config->enableChannelB = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + config->channelBScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + config->channelBNumber = 0U; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + config->enableChannelB = false; /* Enable alternate channel B.*/ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + LPADC_PrepareAutoCalibration(base); + LPADC_FinishAutoCalibration(base); +} + +/*! + * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base) +{ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + assert((0U == LPADC_GetConvResultCount(base, 0)) && (0U == LPADC_GetConvResultCount(base, 1))); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ + assert(LPADC_GetConvResultCount(base) == 0U); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; +} + +/*! + * brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base) +{ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + int32_t GCCa; + int32_t GCCb; + float GCRa; + float GCRb; +#else + uint32_t GCCa; + float GCRa; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + uint32_t GCCb; + float GCRb; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + || (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + ) + { + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + if (0U != ((base->GCC[0]) & 0x8000U)) + { + GCCa = GCCa - 0x10000; + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + } + + if (0U != ((base->GCC[1]) & 0x8000U)) + { + GCCb = GCCb - 0x10000; + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ + } +#else + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] |= ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Get calibration value into the memory which is defined by invoker. + * + * note Please note the ADC will be disabled temporary. + * note This function should be used after finish calibration. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered + * on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + uint32_t i; + for (i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#else + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +/*! + * brief Set calibration value into ADC calibration registers. + * + * note Please note the ADC will be disabled temporary. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + for (uint32_t i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#else + *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + /* + * $Branch Coverage Justification$ + * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible, + * the calibration ready state is too short not to catch. + */ + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ diff --git a/drivers/lpadc/fsl_lpadc.h b/drivers/lpadc/fsl_lpadc.h index 4fa559a9a..5da001968 100644 --- a/drivers/lpadc/fsl_lpadc.h +++ b/drivers/lpadc/fsl_lpadc.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ +#ifndef FSL_LPADC_H_ +#define FSL_LPADC_H_ #include "fsl_common.h" @@ -22,10 +22,21 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.6.2. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 6, 2)) -/*@}*/ +/*! @{ */ +/*! @brief LPADC driver version 2.8.4. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) +/*! @} */ + +#if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1)) +#define ADC_OFSTRIM_OFSTRIM_MAX (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_SIGN ((ADC_OFSTRIM_OFSTRIM_MAX + 1U) >> 1U) + +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2)) +#define ADC_OFSTRIM_OFSTRIM_A_MAX (ADC_OFSTRIM_OFSTRIM_A_MASK >> ADC_OFSTRIM_OFSTRIM_A_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_B_MAX (ADC_OFSTRIM_OFSTRIM_B_MASK >> ADC_OFSTRIM_OFSTRIM_B_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_A_SIGN ((ADC_OFSTRIM_OFSTRIM_A_MAX + 1U) >> 1U) +#define ADC_OFSTRIM_OFSTRIM_B_SIGN ((ADC_OFSTRIM_OFSTRIM_B_MAX + 1U) >> 1U) +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ /*! * @brief Define the MACRO function to get command status from status value. @@ -41,7 +52,39 @@ */ #define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/* Map macros to the unified name. */ +#if !defined(ADC_STAT_FOF0_MASK) +#ifdef ADC_STAT_FOF_MASK +#define ADC_STAT_FOF0_MASK ADC_STAT_FOF_MASK +#else +#error "ADC_STAT_FOF0_MASK not defined" +#endif /* ifdef(ADC_STAT_FOF_MASK) */ +#endif /* !defined(ADC_STAT_FOF0_MASK) */ + +#if !defined(ADC_STAT_RDY0_MASK) +#ifdef ADC_STAT_RDY_MASK +#define ADC_STAT_RDY0_MASK ADC_STAT_RDY_MASK +#else +#error "ADC_STAT_RDY0_MASK not defined" +#endif /* ifdef ADC_STAT_RDY_MASK */ +#endif /* !defined(ADC_STAT_RDY0_MASK) */ + +#if !defined(ADC_IE_FOFIE0_MASK) +#ifdef ADC_IE_FOFIE_MASK +#define ADC_IE_FOFIE0_MASK ADC_IE_FOFIE_MASK +#else +#error "ADC_IE_FOFIE0_MASK not defined" +#endif /* ifdef ADC_IE_FOFIE_MASK */ +#endif /* !defined(ADC_IE_FOFIE0_MASK) */ + +#if !defined(ADC_IE_FWMIE0_MASK) +#ifdef ADC_IE_FWMIE_MASK +#define ADC_IE_FWMIE0_MASK ADC_IE_FWMIE_MASK +#else +#error "ADC_IE_FWMIE0_MASK not defined" +#endif /* ifdef ADC_IE_FWMIE_MASK */ +#endif /* !defined(ADC_IE_FWMIE0_MASK) */ + /*! * @brief Define hardware flags of the module. */ @@ -51,14 +94,45 @@ enum _lpadc_status_flags FIFO 0 than it can hold. */ kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result FIFO 1 than it can hold. */ kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result FIFO 1 is greater than the setting watermark level. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) + kLPADC_TriggerExceptionFlag = ADC_STAT_TEXC_INT_MASK, /*!< Indicates that a trigger exception event has occurred. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) + kLPADC_TriggerCompletionFlag = ADC_STAT_TCOMP_INT_MASK, /*!< Indicates that a trigger completion event has occurred. + */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) + kLPADC_CalibrationReadyFlag = ADC_STAT_CAL_RDY_MASK, /*!< Indicates that the calibration process is done. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) + kLPADC_ActiveFlag = ADC_STAT_ADC_ACTIVE_MASK, /*!< Indicates that the ADC is in active state. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) */ + + kLPADC_ResultFIFOOverflowFlag = kLPADC_ResultFIFO0OverflowFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0OverflowFlag as instead. */ + + kLPADC_ResultFIFOReadyFlag = kLPADC_ResultFIFO0ReadyFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0ReadyFlag as instead. */ }; /*! * @brief Define interrupt switchers of the module. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. */ enum _lpadc_interrupt_enable { @@ -66,13 +140,30 @@ enum _lpadc_interrupt_enable requests when FOF0 flag is asserted. */ kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFOOverflowInterruptEnable = kLPADC_ResultFIFO0OverflowInterruptEnable, /*!< To compilitable with old + version, do not recommend using this, + please use + #kLPADC_ResultFIFO0OverflowInterruptEnable + as instead. */ + kLPADC_FIFOWatermarkInterruptEnable = kLPADC_FIFO0WatermarkInterruptEnable, /*!< To compilitable with old version, + do not recommend using this, please + use + #kLPADC_FIFO0WatermarkInterruptEnable + as instead. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt requests when FOF1 flag is asserted. */ kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception interrupt. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt when trigger 0 completion. */ kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt @@ -105,35 +196,15 @@ enum _lpadc_interrupt_enable when trigger 14 completion. */ kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ }; -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) /*! * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. */ enum _lpadc_trigger_status_flags { @@ -154,40 +225,40 @@ enum _lpadc_trigger_status_flags kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ }; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) */ /*! * @brief Define enumeration of sample scale mode. @@ -199,8 +270,8 @@ enum _lpadc_trigger_status_flags */ typedef enum _lpadc_sample_scale_mode { - kLPADC_SamplePartScale = - 0U, /*!< Use divided input voltage signal. (For scale select,please refer to the reference manual). */ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. + (For scale select,please refer to the reference manual). */ kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ } lpadc_sample_scale_mode_t; @@ -211,16 +282,19 @@ typedef enum _lpadc_sample_scale_mode */ typedef enum _lpadc_sample_channel_mode { - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ + kLPADC_SampleChannelSingleEndSideA = 0x0U, /*!< Single-end mode, only A-side channel is converted. */ +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + kLPADC_SampleChannelSingleEndSideB = 0x1U, /*!< Single-end mode, only B-side channel is converted. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif + kLPADC_SampleChannelDiffBothSideAB = 0x2U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side + channels are converted independently. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ } lpadc_sample_channel_mode_t; /*! @@ -228,6 +302,9 @@ typedef enum _lpadc_sample_channel_mode * * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to * capture temporary results while the averaging iterations are executed. + * + * @note Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH + * register. */ typedef enum _lpadc_hardware_average_mode { @@ -240,11 +317,12 @@ typedef enum _lpadc_hardware_average_mode kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ - (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */ kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */ kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */ -#endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ } lpadc_hardware_average_mode_t; /*! @@ -294,13 +372,15 @@ typedef enum _lpadc_conversion_resolution_mode kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. */ } lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS /*! * @brief Define enumeration of conversion averages mode. * * Configure the converion average number for auto-calibration. + * @note Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL + * register. */ typedef enum _lpadc_conversion_average_mode { @@ -313,13 +393,14 @@ typedef enum _lpadc_conversion_average_mode kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ - (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */ kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */ kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */ -#endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ } lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ /*! * @brief Define enumeration of reference voltage source. @@ -357,29 +438,111 @@ typedef enum _lpadc_offset_calibration_mode kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */ kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */ } lpadc_offset_calibration_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ /*! * @brief Define enumeration of trigger priority policy. * * This selection controls how higher priority triggers are handled. + * @note \b kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of + * TPRICTRL field in CFG register. */ typedef enum _lpadc_trigger_priority_policy { - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + kLPADC_ConvPreemptImmediatelyNotAutoResumed = 0x0U, /*!< If a higher priority trigger is detected during command processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion is not + automatically resumed or restarted. */ + kLPADC_ConvPreemptSoftlyNotAutoResumed = 0x1U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion is not + resumed or restarted. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptImmediatelyAutoRestarted = 0x4U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be restarted. */ + kLPADC_ConvPreemptSoftlyAutoRestarted = 0x5U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + automatically be restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptImmediatelyAutoResumed = 0xCU, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be resumed. */ + kLPADC_ConvPreemptSoftlyAutoResumed = 0xDU, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + be automatically be resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptImmediately = + kLPADC_ConvPreemptImmediatelyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ + kLPADC_TriggerPriorityPreemptSoftly = + kLPADC_ConvPreemptSoftlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures compatibility + with older versions. */ + +#if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) + kLPADC_ConvPreemptSubsequentlyNotAutoResumed = 0x2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + not automatically be restarted or resumed. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptSubsequentlyAutoRestarted = 0x6U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptSubsequentlyAutoResumed = 0xEU, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptSubsequently = + kLPADC_ConvPreemptSubsequentlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI + kLPADC_TriggerPriorityExceptionDisabled = 0x10U, /*!< High priority trigger exception disabled. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ } lpadc_trigger_priority_policy_t; +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Define enumeration of tune value. + */ +typedef enum _lpadc_tune_value +{ + kLPADC_TuneValue0 = 0U, /*!< Tune value 0. */ + kLPADC_TuneValue1 = 1U, /*!< Tune value 1. */ + kLPADC_TuneValue2 = 2U, /*!< Tune value 2. */ + kLPADC_TuneValue3 = 3U, /*!< Tune value 3. */ +} lpadc_tune_value_t; +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + /*! * @brief LPADC global configuration. * @@ -388,9 +551,9 @@ typedef enum _lpadc_trigger_priority_policy typedef struct { #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ #if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". If voltage reference option1 input is above 1.8V, it should be "false". */ @@ -412,9 +575,9 @@ typedef struct lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for conversions.*/ -#if !(defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 0)) - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t. */ bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during @@ -437,7 +600,10 @@ typedef struct uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) + +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ } lpadc_config_t; /*! @@ -446,15 +612,15 @@ typedef struct typedef struct { #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */ #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH - uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ + uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ #endif uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command. */ @@ -479,8 +645,8 @@ typedef struct executing this command. */ #endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN - bool enableChannelB; /*! Enable alternate Channel B */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ + bool enableChannelB; /*! Enable alternate Channel B */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ } lpadc_conv_command_config_t; /*! @@ -524,14 +690,17 @@ typedef struct _lpadc_calibration_value { /* gain calibration result. */ uint16_t gainCalibrationResultA; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) uint16_t gainCalibrationResultB; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ #if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) /* general calibration value. */ uint16_t generalCalibrationValueA[33U]; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) uint16_t generalCalibrationValueB[33U]; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ } lpadc_calibration_value_t; - #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ #if defined(__cplusplus) @@ -619,6 +788,10 @@ static inline void LPADC_DoResetFIFO1(ADC_Type *base) base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; } #else + +#if defined(ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#endif /* defined(ADC_CTRL_RSTFIFO0_MASK) */ /*! * @brief Do reset the conversion FIFO. * @@ -696,9 +869,12 @@ static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) */ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) { + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert(((mask & 0xFFFFU) == (mask & ADC_TSTAT_TEXC_NUM_MASK)) && + ((mask & 0xFFFF0000U) == (mask & ADC_TSTAT_TCOMP_FLAG_MASK))); base->TSTAT = mask; } -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */ /* @} */ @@ -715,6 +891,10 @@ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) */ static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ base->IE |= mask; } @@ -726,6 +906,10 @@ static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) */ static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ base->IE &= ~mask; } @@ -771,6 +955,9 @@ static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) } } #else +#if defined(ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#endif /* defined(ADC_DE_FWMDE0_MASK) */ /*! * @brief Switch on/off the DMA trigger for FIFO watermark event. * @@ -788,8 +975,8 @@ static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) base->DE &= ~ADC_DE_FWMDE_MASK; } } -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ +/* @} */ /*! * @name Trigger and conversion with FIFO. @@ -810,16 +997,25 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) } /*! - * brief Get the result in conversion FIFOn. + * @brief Get the result in conversion FIFOn. * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. * - * return Status whether FIFOn entry is valid. + * @return Status whether FIFOn entry is valid. */ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else + +/*! + * @brief Get the result in conversion FIFOn using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ /*! * @brief Get the count of result kept in conversion FIFO. * @@ -840,7 +1036,15 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) * @return Status whether FIFO entry is valid. */ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ /*! * @brief Configure the conversion trigger source. @@ -858,10 +1062,12 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_ * * This function initializes the trigger's configuration structure with an available settings. The default values are: * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; * @endcode * @param config Pointer to configuration structure. */ @@ -901,10 +1107,13 @@ static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, u base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK; } } -#endif /* FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ +#endif /* defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ /*! * @brief Configure conversion command. + + * @note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. * * @param base LPADC peripheral base address. * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. @@ -920,9 +1129,10 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * @code * config->sampleScaleMode = kLPADC_SampleFullScale; * config->channelBScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; * config->enableAutoChannelIncrement = false; * config->loopCount = 0U; * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; @@ -978,11 +1188,48 @@ static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) * @param base LPADC peripheral base address. */ void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +#if defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1U) +/*! + * @brief Set trim value for offset. + * + * @note For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5 + * LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to + * 15.96875 LSB. + * + * @param base LPADC peripheral base address. + * @param value Offset trim value, is a 10-bit signed value between -512 and 511. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValue Pointer to the variable in type of int16_t to store offset value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue) +{ + assert(pValue != NULL); + + uint16_t ofstrim = (uint16_t)((base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_MASK)) >> ADC_OFSTRIM_OFSTRIM_SHIFT); + + if ((ofstrim & ADC_OFSTRIM_OFSTRIM_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrim |= (uint16_t)(~ADC_OFSTRIM_OFSTRIM_MAX); + } + + *pValue = (int16_t)ofstrim; +} +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2U)) /*! * @brief Set proper offset value to trim ADC. * @@ -993,11 +1240,42 @@ void LPADC_DoAutoCalibration(ADC_Type *base); * @param valueB Setting offset value B. * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB) { base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); } -#else + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValueA Pointer to the variable in type of int32_t to store offset A value. + * @param pValueB Pointer to the variable in type of int32_t to store offset B value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int32_t *pValueA, int32_t *pValueB) +{ + assert(pValueA != NULL); + assert(pValueB != NULL); + + uint32_t ofstrimA = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_A_MASK)) >> ADC_OFSTRIM_OFSTRIM_A_SHIFT; + uint32_t ofstrimB = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_B_MASK)) >> ADC_OFSTRIM_OFSTRIM_B_SHIFT; + + if ((ofstrimA & ADC_OFSTRIM_OFSTRIM_A_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimA |= (~ADC_OFSTRIM_OFSTRIM_A_MAX); + } + if ((ofstrimB & ADC_OFSTRIM_OFSTRIM_B_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimB |= (~ADC_OFSTRIM_OFSTRIM_B_MAX); + } + + *pValueA = (int32_t)ofstrimA; + *pValueB = (int32_t)ofstrimB; +} +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ +#else /* !(defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM) */ /*! * @brief Set proper offset value to trim 12 bit ADC conversion. * @@ -1058,7 +1336,7 @@ static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_c base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode); } -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ /*! * @brief Do offset calibration. @@ -1090,30 +1368,155 @@ void LPADC_PrepareAutoCalibration(ADC_Type *base); */ void LPADC_FinishAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ /*! * @brief Get calibration value into the memory which is defined by invoker. - * + * * @note Please note the ADC will be disabled temporary. * @note This function should be used after finish calibration. - * + * * @param base LPADC peripheral base address. - * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always powered on even in low power modes. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always + * powered on even in low power modes. */ void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue); /*! * @brief Set calibration value into ADC calibration registers. - * + * * @note Please note the ADC will be disabled temporary. - * + * * @param base LPADC peripheral base address. - * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration value. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration + * value. */ void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Request high speed mode trim calculation. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_CALHS_MASK; +} + +/*! + * @brief Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15. + * + * @note The high speed mode trim value is used to minimize offset for high speed conversion. + * + * @param base LPADC peripheral base address. + * @return The calculated high speed mode trim value. + */ +static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base) +{ + return (int8_t)(base->HSTRIM); +} + +/*! + * @brief Set high speed mode trim value. + * + * @note If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim. + * + * @param base LPADC peripheral base address. + * @param trimValue The trim value to be set. + */ +static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue) +{ + base->HSTRIM = ADC_HSTRIM_HSTRIM(trimValue); +} + +/*! + * @brief Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared + * to conversion cycle counts when high speed mode is disabled. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable high speed conversion mode: + * - \b true Enable high speed conversion mode; + * - \b false Disable high speed conversion mode. + */ +static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HS_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HS_MASK; + } +} + +/*! + * @brief Enable/disable an additional ADCK cycle to conversion. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable an additional ADCK cycle to conversion: + * - \b true Enable an additional ADCK cycle to conversion; + * - \b false Disable an additional ADCK cycle to conversion. + */ +static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HSEXTRA_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HSEXTRA_MASK; + } +} + +/*! + * @brief Set tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @param tuneValue The tune value to be set, please refer to @ref lpadc_tune_value_t. + */ +static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue) +{ + base->CFG2 = (base->CFG2 & ~ADC_CFG2_TUNE_MASK) | ADC_CFG2_TUNE(tuneValue); +} + +/*! + * @brief Get tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @return The tune value, please refer to @ref lpadc_tune_value_t. + */ +static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base) +{ + return (lpadc_tune_value_t)((base->CFG2 & ADC_CFG2_TUNE_MASK) >> ADC_CFG2_TUNE_SHIFT); +} +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) +/*! + * @brief Enable/disable left-justify format in 12-bit single-end mode. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable left-justify format in 12-bit single-end mode: + * - \b true Enable left-justify format in 12-bit single-end mode; + * - \b false Disable left-justify format in 12-bit single-end mode. + */ +static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_JLEFT_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_JLEFT_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */ /* @} */ @@ -1123,4 +1526,4 @@ void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t * /*! * @} */ -#endif /* _FSL_LPADC_H_ */ +#endif /* FSL_LPADC_H_ */ diff --git a/drivers/lpc_freqme/fsl_freqme.c b/drivers/lpc_freqme/fsl_freqme.c index 709bc80f2..459bbb6f3 100644 --- a/drivers/lpc_freqme/fsl_freqme.c +++ b/drivers/lpc_freqme/fsl_freqme.c @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2021-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,10 @@ #define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" #endif +#if defined(FREQME_RSTS_N) +#define FREQME_RESETS_ARRAY FREQME_RSTS_N +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -31,6 +35,10 @@ static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FREQME_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY; +#endif /******************************************************************************* * Code ******************************************************************************/ @@ -69,22 +77,26 @@ void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FREQME_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]); +#endif + if (config->startMeasurement) { - tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; } - tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | - FREQME_FREQMECTRL_W_PULSE_MODE(config->operateMode); + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | + FREQME_CTRL_W_PULSE_MODE(config->operateMode); if (config->operateMode == kFREQME_FreqMeasurementMode) { - tmp32 |= FREQME_FREQMECTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); + tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); } else { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); + tmp32 |= FREQME_CTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); } - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @@ -124,19 +136,19 @@ void FREQME_GetDefaultConfig(freq_measure_config_t *config) */ uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency) { - uint64_t measureResult = 0ULL; - uint32_t targetFreq = 0ULL; + uint32_t measureResult = 0UL; + uint32_t targetFreq = 0UL; uint64_t tmp64 = 0ULL; - while ((base->FREQMECTRL_R & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) + while ((base->CTRL_R & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) { } if (!FREQME_CheckOperateMode(base)) { - measureResult = (uint64_t)(base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK); - tmp64 = (measureResult - 2ULL) * (uint64_t)refClkFrequency; - targetFreq = (uint32_t)(tmp64 / (1UL << (uint32_t)FREQME_GetReferenceClkScaleValue(base))); + measureResult = base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; + tmp64 = ((uint64_t)measureResult - 2ULL) * (uint64_t)refClkFrequency; + targetFreq = (uint32_t)(tmp64 / (1ULL << (uint64_t)FREQME_GetReferenceClkScaleValue(base))); } return targetFreq; diff --git a/drivers/lpc_freqme/fsl_freqme.h b/drivers/lpc_freqme/fsl_freqme.h index dae1c2b81..72e281051 100644 --- a/drivers/lpc_freqme/fsl_freqme.h +++ b/drivers/lpc_freqme/fsl_freqme.h @@ -1,11 +1,11 @@ /* - * Copyright 2021 NXP + * Copyright 2021-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FREQME_ -#define _FSL_FREQME_ +#ifndef FSL_FREQME_H_ +#define FSL_FREQME_H_ #include "fsl_common.h" @@ -20,8 +20,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FREQME driver version 2.0.0. */ -#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief FREQME driver version 2.1.2. */ +#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ /*! @@ -30,17 +30,17 @@ */ enum _freqme_interrupt_status_flags { - kFREQME_UnderflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is + kFREQME_UnderflowInterruptStatusFlag = FREQME_CTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is just done and the result is less than minimun value. */ - kFREQME_OverflowInterruptStatusFlag = FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is + kFREQME_OverflowInterruptStatusFlag = FREQME_CTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is just done and the result is greater than maximum value. */ - kFREQME_ReadyInterruptStatusFlag = FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is + kFREQME_ReadyInterruptStatusFlag = FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is just done and the result is ready to read. */ - kFREQME_AllInterruptStatusFlags = FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt + kFREQME_AllInterruptStatusFlags = FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt status flags. */ }; @@ -51,11 +51,11 @@ enum _freqme_interrupt_status_flags */ enum _freqme_interrupt_enable { - kFREQME_UnderflowInterruptEnable = FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is + kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is less than minimum value. */ - kFREQME_OverflowInterruptEnable = FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is + kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is greater than maximum value. */ - kFREQME_ReadyInterruptEnable = FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a + kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a measurement completes and the result is ready. */ }; @@ -154,11 +154,11 @@ static inline void FREQME_StartMeasurementCycle(FREQME_Type *base) { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - tmp32 |= FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK; - base->FREQMECTRL_W = tmp32; + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; + base->CTRL_W = tmp32; } /*! @@ -171,10 +171,10 @@ static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base) { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); - base->FREQMECTRL_W = tmp32; + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + base->CTRL_W = tmp32; } /*! @@ -189,15 +189,15 @@ static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); if (enable) { - tmp32 |= FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK; + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK; } - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @@ -209,7 +209,7 @@ static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) */ static inline bool FREQME_CheckContinuousMode(FREQME_Type *base) { - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); } /*! @@ -222,15 +222,15 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_ { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); if (operateMode == kFREOME_PulseWidthMeasurementMode) { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_MODE_MASK; + tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK; } - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @@ -242,7 +242,8 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_ */ static inline bool FREQME_CheckOperateMode(FREQME_Type *base) { - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK) != 0UL); + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL); + } /*! @@ -253,7 +254,7 @@ static inline bool FREQME_CheckOperateMode(FREQME_Type *base) */ static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue) { - base->FREQMEMIN = minValue; + base->MIN = minValue; } /*! @@ -264,7 +265,7 @@ static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minVal */ static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue) { - base->FREQMEMAX = maxValue; + base->MAX = maxValue; } /*! @} */ @@ -296,7 +297,7 @@ uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequen */ static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base) { - return (uint8_t)(base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK); + return (uint8_t)(base->CTRLSTAT & FREQME_CTRLSTAT_REF_SCALE_MASK); } /*! @} */ @@ -316,16 +317,16 @@ static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polar { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_PULSE_POL_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); if (pulsePolarity != kFREQME_PulseHighPeriod) { - tmp32 |= FREQME_FREQMECTRL_W_PULSE_POL_MASK; + tmp32 |= FREQME_CTRL_W_PULSE_POL_MASK; } - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @@ -337,7 +338,7 @@ static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polar */ static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) { - return (bool)((base->FREQMECTRLSTAT & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK) != 0UL); + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_POL_MASK) != 0UL); } /*! @@ -351,7 +352,7 @@ static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) */ static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) { - return base->FREQMECTRL_R & FREQME_FREQMECTRL_R_RESULT_MASK; + return base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; } /*! @} */ @@ -370,7 +371,7 @@ static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) */ static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) { - return (base->FREQMECTRLSTAT & kFREQME_AllInterruptStatusFlags); + return (base->CTRLSTAT & (uint32_t)kFREQME_AllInterruptStatusFlags); } /*! @@ -382,7 +383,7 @@ static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) */ static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags) { - base->FREQMECTRLSTAT |= statusFlags; + base->CTRLSTAT |= statusFlags; } /*! @} */ @@ -402,13 +403,13 @@ static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks) { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK | - FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK | + FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); tmp32 |= masks; - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @@ -421,11 +422,11 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) { uint32_t tmp32; - tmp32 = base->FREQMECTRLSTAT; - tmp32 &= ~(FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK | FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK | - FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK | masks); + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK | masks); - base->FREQMECTRL_W = tmp32; + base->CTRL_W = tmp32; } /*! @} */ @@ -437,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) /*! * @} */ -#endif /* __FSL_FREQME_H__ */ +#endif /* FSL_FREQME_H_ */ diff --git a/drivers/lpcmp/fsl_lpcmp.c b/drivers/lpcmp/fsl_lpcmp.c index 0ec528d43..23b2da790 100644 --- a/drivers/lpcmp/fsl_lpcmp.c +++ b/drivers/lpcmp/fsl_lpcmp.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2022 NXP + * Copyright 2016-2019, 2023 NXP * All rights reserved. * * @@ -9,11 +9,18 @@ #include "fsl_lpcmp.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.lpcmp" #endif +#if defined(LPCMP_RSTS) +#define LPCMP_RESETS_ARRAY LPCMP_RSTS +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -39,6 +46,11 @@ static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* LPCMP_CLOCKS */ +#if defined(LPCMP_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpcmpResets[] = LPCMP_RESETS_ARRAY; +#endif + /******************************************************************************* * Codes ******************************************************************************/ @@ -98,8 +110,14 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* LPCMP_CLOCKS */ +#if defined(LPCMP_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpcmpResets[LPCMP_GetInstance(base)]); +#endif + /* Configure. */ LPCMP_Enable(base, false); + +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) /* CCR0 register. */ if (config->enableStopMode) { @@ -109,8 +127,15 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) { base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; } +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + /* CCR1 register. */ - tmp32 = base->CCR1 & ~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK); + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + | LPCMP_CCR1_FUNC_CLK_SEL_MASK +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + ))); + if (config->enableOutputPin) { tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; @@ -123,6 +148,9 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) { tmp32 |= LPCMP_CCR1_COUT_INV_MASK; } +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock); +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ base->CCR1 = tmp32; /* CCR2 register. */ tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK); @@ -169,6 +197,7 @@ void LPCMP_Deinit(LPCMP_Type *base) * config->enableInvertOutput = false; * config->hysteresisMode = kLPCMP_HysteresisLevel0; * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; * endcode * param config Pointer to "lpcmp_config_t" structure. */ @@ -176,13 +205,17 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config) { /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); - - config->enableStopMode = false; +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + config->enableStopMode = false; +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ config->enableOutputPin = false; config->useUnfilteredOutput = false; config->enableInvertOutput = false; config->hysteresisMode = kLPCMP_HysteresisLevel0; config->powerMode = kLPCMP_LowSpeedPowerMode; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + config->functionalSourceClock = kLPCMP_FunctionalClockSource0; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ } /*! @@ -190,8 +223,8 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config) * is selected for the negative and positive mux. * * param base LPCMP peripheral base address. - * param positiveChannel Positive side input channel number. Available range is 0-7. - * param negativeChannel Negative side input channel number. Available range is 0-7. + * param positiveChannel Positive side input channel number. + * param negativeChannel Negative side input channel number. */ void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) { @@ -247,3 +280,88 @@ void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config) } base->DCR = tmp32; } + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUTA_CFG_MASK | LPCMP_CCR1_EVT_SEL_CFG_MASK | LPCMP_CCR1_WINDOW_INV_MASK))); + + if (config->enableInvertWindowSignal) + { + tmp32 |= LPCMP_CCR1_WINDOW_INV_MASK; + } + + /* Set COUT event, which can close the active window in window mode. */ + tmp32 |= LPCMP_CCR1_EVT_SEL_CFG(config->closeWindowEvent); + + /* Set the COUTA signal value when the window is closed. */ + tmp32 |= LPCMP_CCR1_COUTA_CFG(config->COUTASignal); + + base->CCR1 = tmp32; +} +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + /* LPCMPx_RRCR0 register, Configuration options for the round-robin operation. */ + tmp32 = (base->RRCR0 & + (~(LPCMP_RRCR0_RR_TRG_SEL_MASK | LPCMP_RRCR0_RR_NSAM_MASK | LPCMP_RRCR0_RR_CLK_SEL_MASK | + LPCMP_RRCR0_RR_INITMOD_MASK | LPCMP_RRCR0_RR_SAMPLE_CNT_MASK | LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK))); + + tmp32 |= + (LPCMP_RRCR0_RR_TRG_SEL(config->roundrobinTriggerSource) | LPCMP_RRCR0_RR_NSAM(config->sampleClockNumbers) | + LPCMP_RRCR0_RR_CLK_SEL(config->roundrobinClockSource) | LPCMP_RRCR0_RR_INITMOD(config->initDelayModules) | + LPCMP_RRCR0_RR_SAMPLE_CNT(config->channelSampleNumbers) | + LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(config->sampleTimeThreshhold)); + + base->RRCR0 = tmp32; + + /* LPCMPx_RRCR1 register, Configure the fix port, fix channel and checker channel. */ + tmp32 = + (base->RRCR1 & (~(LPCMP_RRCR1_FIXP_MASK | LPCMP_RRCR1_FIXCH_MASK | (0xFFUL << LPCMP_RRCR1_RR_CH0EN_SHIFT)))); + tmp32 |= (LPCMP_RRCR1_FIXP(config->fixedMuxPort) | LPCMP_RRCR1_FIXCH(config->fixedChannel) | + ((uint32_t)(config->checkerChannelMask) << LPCMP_RRCR1_RR_CH0EN_SHIFT)); + + base->RRCR1 = tmp32; +} + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value) +{ + uint32_t tmp32 = 0UL; + + tmp32 = (base->RRCR2 & (~LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)); + tmp32 |= LPCMP_RRCR2_RR_TIMER_RELOAD(value); + + base->RRCR2 = tmp32; +} + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ diff --git a/drivers/lpcmp/fsl_lpcmp.h b/drivers/lpcmp/fsl_lpcmp.h index e4ef16218..737738acd 100644 --- a/drivers/lpcmp/fsl_lpcmp.h +++ b/drivers/lpcmp/fsl_lpcmp.h @@ -1,14 +1,14 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2023 NXP * All rights reserved. * * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPCMP_H_ -#define _FSL_LPCMP_H_ +#ifndef FSL_LPCMP_H_ +#define FSL_LPCMP_H_ #include "fsl_common.h" @@ -20,22 +20,35 @@ /******************************************************************************* * Definitions ******************************************************************************/ - /*! @name Driver version */ -/*@{*/ -/*! @brief LPCMP driver version 2.0.3. */ -#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ +/*! @{ */ +/*! @brief LPCMP driver version 2.1.2. */ +#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ + +#define LPCMP_CCR1_COUTA_CFG_MASK (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK) +#define LPCMP_CCR1_COUTA_CFG_SHIFT LPCMP_CCR1_COUTA_OWEN_SHIFT +#define LPCMP_CCR1_COUTA_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_CFG_SHIFT)) & LPCMP_CCR1_COUTA_CFG_MASK) + +#define LPCMP_CCR1_EVT_SEL_CFG_MASK (LPCMP_CCR1_EVT_SEL_MASK | LPCMP_CCR1_WINDOW_CLS_MASK) +#define LPCMP_CCR1_EVT_SEL_CFG_SHIFT LPCMP_CCR1_WINDOW_CLS_SHIFT +#define LPCMP_CCR1_EVT_SEL_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_CFG_SHIFT)) & LPCMP_CCR1_EVT_SEL_CFG_MASK) /*! * @brief LPCMP status falgs mask. */ enum _lpcmp_status_flags { - kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. - The flag does not support W1C. */ + kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CSR_RRF) && FSL_FEATURE_LPCMP_HAS_CSR_RRF + kLPCMP_OutputRoundRobinEventFlag = LPCMP_CSR_RRF_MASK, /*!< Detects when any channel's last comparison result is + different from the pre-set value in trigger mode. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CSR_RRF */ + kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. + The flag does not support W1C. */ }; /*! @@ -45,7 +58,12 @@ enum _lpcmp_interrupt_enable { kLPCMP_OutputRisingInterruptEnable = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ +#if defined(FSL_FEATURE_LPCMP_HAS_IER_RRF_IE) && FSL_FEATURE_LPCMP_HAS_IER_RRF_IE + kLPCMP_RoundRobinInterruptEnable = LPCMP_IER_RRF_IE_MASK, /*!< Comparator round robin mode interrupt + occurred when the comparison result changes for a given channel. */ +#endif /* FSL_FEATURE_LPCMP_HAS_IER_RRF_IE */ }; + /*! * @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis * value with each level @@ -77,6 +95,79 @@ typedef enum _lpcmp_dac_reference_voltage_source kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ } lpcmp_dac_reference_voltage_source_t; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL +/*! + * @brief LPCMP functional mode clock source selection. + * + * Note: In different devices, the functional mode clock source selection is different, + * please refer to specific device Reference Manual for details. + */ +typedef enum _lpcmp_functional_source_clock +{ + kLPCMP_FunctionalClockSource0 = 0U, /*!< Select functional mode clock source0. */ + kLPCMP_FunctionalClockSource1 = 1U, /*!< Select functional mode clock source1. */ + kLPCMP_FunctionalClockSource2 = 2U, /*!< Select functional mode clock source2. */ + kLPCMP_FunctionalClockSource3 = 3U, /*!< Select functional mode clock source3. */ +} lpcmp_functional_source_clock_t; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Set the COUTA signal value when the window is closed. + */ +typedef enum _lpcmp_couta_signal +{ + kLPCMP_COUTASignalNoSet = 0U, /*!< NO set the COUTA signal value when the window is closed. */ + kLPCMP_COUTASignalLow = 1U, /*!< Set COUTA signal low(0) when the window is closed. */ + kLPCMP_COUTASignalHigh = 3U, /*!< Set COUTA signal high(1) when the window is closed. */ +} lpcmp_couta_signal_t; + +/*! + * @brief Set COUT event, which can close the active window in window mode. + */ +typedef enum _lpcmp_close_window_event +{ + kLPCMP_CLoseWindowEventNoSet = 0U, /*!< No Set COUT event, which can close the active window in window mode. */ + kLPCMP_CloseWindowEventRisingEdge = 1U, /*!< Set rising edge COUT signal as COUT event. */ + kLPCMP_CloseWindowEventFallingEdge = 3U, /*!< Set falling edge COUT signal as COUT event. */ + kLPCMP_CLoseWindowEventBothEdge = 5U, /*!< Set both rising and falling edge COUT signal as COUT event. */ +} lpcmp_close_window_event_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief LPCMP round robin mode fixed mux port. + */ +typedef enum _lpcmp_roundrobin_fixedmuxport +{ + kLPCMP_FixedPlusMuxPort = 0U, /*!< Fixed plus mux port. */ + kLPCMP_FixedMinusMuxPort = 1U, /*!< Fixed minus mux port. */ +} lpcmp_roundrobin_fixedmuxport_t; + +/*! + * @brief LPCMP round robin mode clock source selection. + * + * Note: In different devices,the round robin mode clock source selection is different, + * please refer to the specific device Reference Manual for details. + */ +typedef enum _lpcmp_roundrobin_clock_source +{ + kLPCMP_RoundRobinClockSource0 = 0U, /*!< Select roundrobin mode clock source0. */ + kLPCMP_RoundRobinClockSource1 = 1U, /*!< Select roundrobin mode clock source1. */ + kLPCMP_RoundRobinClockSource2 = 2U, /*!< Select roundrobin mode clock source2. */ + kLPCMP_RoundRobinClockSource3 = 3U, /*!< Select roundrobin mode clock source3. */ +} lpcmp_roundrobin_clock_source_t; + +/*! + * @brief LPCMP round robin mode trigger source. + */ +typedef enum _lpcmp_roundrobin_trigger_source +{ + kLPCMP_TriggerSourceExternally = 0U, /*!< Select external trigger source. */ + kLPCMP_TriggerSourceInternally = 1U, /*!< Select internal trigger source. */ +} lpcmp_roundrobin_trigger_source_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + /*! * @brief Configure the filter. */ @@ -85,8 +176,8 @@ typedef struct _lpcmp_filter_config bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The - sampling clock must be at least 4 times slower than the system clock to the comparator. - So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ + sampling clock must be at least 4 times slower than the system clock to the comparator. + So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ } lpcmp_filter_config_t; /*! @@ -96,7 +187,8 @@ typedef struct _lpcmp_dac_config { bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Different devices has different available range, + for specific values, please refer to the reference manual.*/ } lpcmp_dac_config_t; /*! @@ -104,19 +196,71 @@ typedef struct _lpcmp_dac_config */ typedef struct _lpcmp_config { - bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ - lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ - lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ + lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ + lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + lpcmp_functional_source_clock_t functionalSourceClock; /*!< Select LPCMP functional mode clock source. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ } lpcmp_config_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window mode control. + */ +typedef struct _lpcmp_window_control_config +{ + bool enableInvertWindowSignal; /*!< True: enable invert window signal, False: disable invert window signal. */ + lpcmp_couta_signal_t COUTASignal; /*!< Decide whether to define the COUTA signal value when the window is closed. */ + lpcmp_close_window_event_t closeWindowEvent; /*!< Decide whether to select COUT event signal edge defines + a COUT event to close window. */ +} lpcmp_window_control_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the round robin mode. + */ +typedef struct _lpcmp_roundrobin_config +{ + uint8_t initDelayModules; /*!< Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet + for specific value. */ + uint8_t sampleClockNumbers; /*!< Specify the number of the round robin clock cycles(0~3) to wait after scanning the + active channel before sampling the channel's comparison result. */ + uint8_t channelSampleNumbers; /*!< Specify the number of samples for one channel, note that channelSampleNumbers + must not smaller than sampleTimeThreshhold. */ + uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are + "1",the final result is "1", otherwise the final result is "0", note that the + sampleTimeThreshhold must not be larger than channelSampleNumbers. */ + lpcmp_roundrobin_clock_source_t roundrobinClockSource; /*!< Decide which clock source to + choose in round robin mode. */ + lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to + choose in round robin mode. */ + lpcmp_roundrobin_fixedmuxport_t fixedMuxPort; /*!< Decide which mux port to choose as + fixed channel in round robin mode. */ + uint8_t fixedChannel; /*!< Indicate which channel of the fixed mux port is used in round robin mode. */ + uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in + round robin mode, for example, if checkerChannelMask set to 0x11U means select + channel 0 and channel 4 as checker channel.*/ +} lpcmp_roundrobin_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + /******************************************************************************* * API ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + /*! - * @name Initialization + * @name Initialization and configuration * @{ */ @@ -161,6 +305,7 @@ void LPCMP_Deinit(LPCMP_Type *base); * config->enableInvertOutput = false; * config->hysteresisMode = kLPCMP_HysteresisLevel0; * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; * @endcode * @param config Pointer to "lpcmp_config_t" structure. */ @@ -215,27 +360,6 @@ static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable) } } -/*! - * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by - * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. - * The optionally inverted comparator output COUT_RAW is sampled on every bus clock - * when WINDOW=1 to generate COUTA. - * - * @param base LPCMP peripheral base address. - * @param enable "true" means enable window mode, and "false" means disable window mode. - */ -static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; - } - else - { - base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; - } -} - /*! * @brief Configures the filter. * @@ -297,8 +421,165 @@ static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) base->CSR = mask; } -/*@}*/ +/*! @} */ + +/*! + * @name Window mode + * @{ + */ + +/*! + * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by + * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. + * The optionally inverted comparator output COUT_RAW is sampled on every bus clock + * when WINDOW=1 to generate COUTA. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable window mode, and "false" means disable window mode. + */ +static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; + } +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config); +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +/*! @} */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @name RoundRobin mode + * @{ + */ + +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config); + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value); + +/*! + * @brief Enable/Disable roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin mode, and "false" means disable roundrobin mode. + */ +static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK; + } + else + { + base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK; + } +} + +/*! + * @brief Enable/Disable roundrobin internal timer, note that this function is only valid + * when using the internal trigger source. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin internal timer, and "false" means disable roundrobin internal timer. + */ +static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR2 |= LPCMP_RRCR2_RR_TIMER_EN_MASK; + } + else + { + base->RRCR2 &= ~LPCMP_RRCR2_RR_TIMER_EN_MASK; + } +} + +/*! + * @brief Set preset value for all channels, users can set all channels' preset vaule through this API, + * for example, if the mask set to 0x03U means channel0 and channel2's preset value set to 1U and other + * channels' preset value set to 0U. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask) +{ + base->RRCSR = (uint32_t)mask; +} + +/*! + * @brief Get comparison results for all channels, users can get all channels' comparison + * results through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' comparison result. + */ +static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base) +{ + return (uint8_t)base->RRCSR; +} + +/*! + * @brief Clear input changed flags for single channel or multiple channels, users can clear + * input changed flag of a single channel or multiple channels through this API, for example, + * if the mask set to 0x03U means clear channel0 and channel2's input changed flags. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask) +{ + base->RRSR = (uint32_t)mask; +} + +/*! + * @brief Get input changed flags for all channels, Users can get all channels' input changed + * flags through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' changed flag. + */ +static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base) +{ + return (uint8_t)base->RRSR; +} + +/*! @} */ + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +#if defined(__cplusplus) +} +#endif -/*@}*/ +/*! @} */ -#endif /* _FSL_LPCMP_H_ */ +#endif /* FSL_LPCMP_H_ */ diff --git a/drivers/lpflexcomm/fsl_lpflexcomm.c b/drivers/lpflexcomm/fsl_lpflexcomm.c new file mode 100644 index 000000000..b494aa8d9 --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpflexcomm.c @@ -0,0 +1,380 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm" +#endif + +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief check whether lpflexcomm supports peripheral type */ +static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph); + +/*! @brief Changes LP_FLEXCOMM mode. */ +static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief Common LPFLEXCOMM IRQhandle. */ +static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LP_FLEXCOMM instance number to base address. */ +static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS; + +/*! @brief Array to map LP_FLEXCOMM instance PTRS. */ +static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)]; + +/*! @brief Array to map LP_FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = LP_FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each LP_FLEXCOMM module */ +static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether lpflexcomm supports peripheral type */ +static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph) +{ + if (periph == LP_FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= LP_FLEXCOMM_PERIPH_LPI2C) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == LP_FLEXCOMM_PERIPH_LPI2CAndLPUART) + { + return true; + } + else + { + return false; + } +} + +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance) +{ + if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)) + { + return s_lpflexcommBaseAddrs[instance]; + } + return 0U; +} + +/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ +uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance) +{ + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; + return base->ISTAT; +} + +/* Get the index corresponding to the LP_FLEXCOMM */ +/*! brief Returns instance number for LP_FLEXCOMM module with given base address. */ +uint32_t LP_FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; + + for (i = 0U; i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs); i++) + { + if (BaseAddr.u32 == s_lpflexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); + return i; +} + +/* Changes LP_FLEXCOMM mode */ +static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock) +{ + assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; + + /* Check whether peripheral type is present */ + if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & LP_FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & LP_FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | LP_FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_lpflexcommClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) + /* Reset the LP_FLEXCOMM module before configuring it.*/ + RESET_ClearPeripheralReset(s_lpflexcommResets[instance]); +#endif + /* Set the LP_FLEXCOMM to given peripheral */ + return LP_FLEXCOMM_SetPeriph(instance, periph, 0); +} + +/*! brief Deinitializes LP_FLEXCOMM. */ +void LP_FLEXCOMM_Deinit(uint32_t instance) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_lpflexcommClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_SetPeripheralReset(s_lpflexcommResets[instance]); +} + +/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to + * LP_FLEXCOMM mode */ +void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, + lpflexcomm_irq_handler_t handler, + void *lpflexcommHandle, + LP_FLEXCOMM_PERIPH_T periph) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_lpflexcommIrqHandler[periph][instance] = NULL; + s_lpflexcommHandle[periph][instance] = lpflexcommHandle; + s_lpflexcommIrqHandler[periph][instance] = handler; +} + +static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance) +{ + uint32_t interruptStat; + + interruptStat = LP_FLEXCOMM_GetInterruptStatus(instance); + if ((interruptStat & + ((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C][instance]); + } + } + if ((interruptStat & ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPUART][instance]); + } + } + if (((interruptStat & (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPSPI][instance]); + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(LP_FLEXCOMM0) +void LP_FLEXCOMM0_DriverIRQHandler(void); +void LP_FLEXCOMM0_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(0U); +} +#endif + +#if defined(LP_FLEXCOMM1) +void LP_FLEXCOMM1_DriverIRQHandler(void); +void LP_FLEXCOMM1_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(1U); +} +#endif + +#if defined(LP_FLEXCOMM2) +void LP_FLEXCOMM2_DriverIRQHandler(void); +void LP_FLEXCOMM2_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(2U); +} +#endif + +#if defined(LP_FLEXCOMM3) +void LP_FLEXCOMM3_DriverIRQHandler(void); +void LP_FLEXCOMM3_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(3U); +} +#endif + +#if defined(LP_FLEXCOMM4) +void LP_FLEXCOMM4_DriverIRQHandler(void); +void LP_FLEXCOMM4_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(4U); +} +#endif + +#if defined(LP_FLEXCOMM5) +void LP_FLEXCOMM5_DriverIRQHandler(void); +void LP_FLEXCOMM5_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(5U); +} +#endif + +#if defined(LP_FLEXCOMM6) +void LP_FLEXCOMM6_DriverIRQHandler(void); +void LP_FLEXCOMM6_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(6U); +} +#endif + +#if defined(LP_FLEXCOMM7) +void LP_FLEXCOMM7_DriverIRQHandler(void); +void LP_FLEXCOMM7_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(7U); +} +#endif + +#if defined(LP_FLEXCOMM8) +void LP_FLEXCOMM8_DriverIRQHandler(void); +void LP_FLEXCOMM8_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(8U); +} +#endif + +#if defined(LP_FLEXCOMM9) +void LP_FLEXCOMM9_DriverIRQHandler(void); +void LP_FLEXCOMM9_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(9U); +} +#endif + +#if defined(LP_FLEXCOMM10) +void LP_FLEXCOMM10_DriverIRQHandler(void); +void LP_FLEXCOMM10_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(10U); +} +#endif + +#if defined(LP_FLEXCOMM11) +void LP_FLEXCOMM11_DriverIRQHandler(void); +void LP_FLEXCOMM11_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(11U); +} +#endif + +#if defined(LP_FLEXCOMM12) +void LP_FLEXCOMM12_DriverIRQHandler(void); +void LP_FLEXCOMM12_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(12U); +} +#endif + +#if defined(LP_FLEXCOMM13) +void LP_FLEXCOMM13_DriverIRQHandler(void); +void LP_FLEXCOMM13_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(13U); +} +#endif + +#if defined(LP_FLEXCOMM17) +void LP_FLEXCOMM17_DriverIRQHandler(void); +void LP_FLEXCOMM17_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(17U); +} +#endif + +#if defined(LP_FLEXCOMM18) +void LP_FLEXCOMM18_DriverIRQHandler(void); +void LP_FLEXCOMM18_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(18U); +} +#endif + +#if defined(LP_FLEXCOMM19) +void LP_FLEXCOMM19_DriverIRQHandler(void); +void LP_FLEXCOMM19_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(19U); +} +#endif + +#if defined(LP_FLEXCOMM20) +void LP_FLEXCOMM20_DriverIRQHandler(void); +void LP_FLEXCOMM20_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(20U); +} +#endif diff --git a/drivers/lpflexcomm/fsl_lpflexcomm.h b/drivers/lpflexcomm/fsl_lpflexcomm.h new file mode 100644 index 000000000..3dc449b65 --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpflexcomm.h @@ -0,0 +1,88 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LP_FLEXCOMM_H_ +#define FSL_LP_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpflexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version. */ +#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! @brief LP_FLEXCOMM peripheral modes. */ +typedef enum +{ + LP_FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + LP_FLEXCOMM_PERIPH_LPUART, /*!< LPUART peripheral */ + LP_FLEXCOMM_PERIPH_LPSPI, /*!< LPSPI Peripheral */ + LP_FLEXCOMM_PERIPH_LPI2C, /*!< LPI2C Peripheral */ + LP_FLEXCOMM_PERIPH_LPI2CAndLPUART = 7, /*!< LPI2C and LPUART Peripheral */ +} LP_FLEXCOMM_PERIPH_T; + +/*! @brief LP_FLEXCOMM interrupt source flags. */ +enum _lpflexcomm_interrupt_flag +{ + kLPFLEXCOMM_I2cSlaveInterruptFlag = LP_FLEXCOMM_ISTAT_I2CS_MASK, /* LPI2C slave interrupt. */ + kLPFLEXCOMM_I2cMasterInterruptFlag = LP_FLEXCOMM_ISTAT_I2CM_MASK, /* LPI2C master interrupt. */ + kLPFLEXCOMM_SpiInterruptFlag = LP_FLEXCOMM_ISTAT_SPI_MASK, /* LPSPI interrupt. */ + kLPFLEXCOMM_UartRxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTRX_MASK, /* LPUART RX interrupt. */ + kLPFLEXCOMM_UartTxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTTX_MASK, /* LPUART TX interrupt. */ + + kLPFLEXCOMM_AllInterruptFlag = kLPFLEXCOMM_I2cSlaveInterruptFlag | kLPFLEXCOMM_I2cMasterInterruptFlag | + kLPFLEXCOMM_SpiInterruptFlag | kLPFLEXCOMM_UartRxInterruptFlag | + kLPFLEXCOMM_UartTxInterruptFlag, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*lpflexcomm_irq_handler_t)(uint32_t instance, void *handle); + +/*! @brief Array with IRQ number for each LP_FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */ +uint32_t LP_FLEXCOMM_GetInstance(void *base); + +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance); + +/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ +uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance); + +/*! @brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph); + +/*! @brief Deinitializes LP_FLEXCOMM. */ +void LP_FLEXCOMM_Deinit(uint32_t instance); + +/*! @brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to + * LP_FLEXCOMM mode */ +void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, + lpflexcomm_irq_handler_t handler, + void *lpflexcommHandle, + LP_FLEXCOMM_PERIPH_T periph); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* FSL_LP_FLEXCOMM_H_*/ diff --git a/drivers/lpflexcomm/fsl_lpi2c_freertos.c b/drivers/lpflexcomm/fsl_lpi2c_freertos.c new file mode 100644 index 000000000..818c23801 --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpi2c_freertos.c @@ -0,0 +1,122 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c_freertos" +#endif + +static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData) +{ + lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData; + BaseType_t reschedule = pdFALSE; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPI2C. + * + * This function initializes the LPI2C module and the related RTOS context. + * + * param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPI2C instance to initialize. + * param masterConfig Configuration structure to set-up LPI2C in master mode. + * param srcClock_Hz Frequency of input clock of the LPI2C module. + * return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpi2c_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->semaphore = xSemaphoreCreateBinary(); + if (handle->semaphore == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + LPI2C_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPI2C_MasterTransferCreateHandle(base, &handle->drv_handle, LPI2C_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and the related RTOS context. + * + * param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle) +{ + LPI2C_MasterDeinit(handle->base); + vSemaphoreDelete(handle->semaphore); + vSemaphoreDelete(handle->mutex); + return kStatus_Success; +} + +/*! + * brief Performs LPI2C transfer. + * + * This function performs an LPI2C transfer according to data given in the transfer structure. + * + * param handle The RTOS LPI2C handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPI2C_Busy; + } + + status = LPI2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/drivers/lpflexcomm/fsl_lpi2c_freertos.h b/drivers/lpflexcomm/fsl_lpi2c_freertos.h new file mode 100644 index 000000000..ea4e77d3c --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpi2c_freertos.h @@ -0,0 +1,107 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPI2C_FREERTOS_H__ +#define FSL_LPI2C_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_lpi2c.h" + +/*! + * @addtogroup lpi2c_freertos_driver LPI2C FreeRTOS Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C FreeRTOS driver version 2.0.0. */ +#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPI2C FreeRTOS handle */ +typedef struct _lpi2c_rtos_handle +{ + LPI2C_Type *base; /*!< LPI2C base address */ + lpi2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; /*!< Transactional state of the underlying driver */ + SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ + SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ + StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ +#endif +} lpi2c_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPI2C RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPI2C. + * + * This function initializes the LPI2C module and the related RTOS context. + * + * @param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPI2C instance to initialize. + * @param masterConfig Configuration structure to set-up LPI2C in master mode. + * @param srcClock_Hz Frequency of input clock of the LPI2C module. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and the related RTOS context. + * + * @param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle); + +/*! + * @brief Performs LPI2C transfer. + * + * This function performs an LPI2C transfer according to data given in the transfer structure. + * + * @param handle The RTOS LPI2C handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_LPI2C_FREERTOS_H__ */ diff --git a/drivers/lpflexcomm/fsl_lpspi_freertos.c b/drivers/lpflexcomm/fsl_lpspi_freertos.c new file mode 100644 index 000000000..a5e2ef0a5 --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpspi_freertos.c @@ -0,0 +1,135 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpspi_freertos" +#endif + +static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData) +{ + lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData; + BaseType_t reschedule = pdFALSE; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPSPI instance to initialize. + * param masterConfig Configuration structure to set-up LPSPI in master mode. + * param srcClock_Hz Frequency of input clock of the LPSPI module. + * return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpspi_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->event = xSemaphoreCreateBinary(); + if (handle->event == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + (void)LPSPI_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, LPSPI_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle) +{ + LPSPI_Deinit(handle->base); + vSemaphoreDelete(handle->event); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs LPSPI transfer. + * + * This function performs an LPSPI transfer according to data given in the transfer structure. + * + * param handle The RTOS LPSPI handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Busy; + } + + /* Initiate transfer */ + status = LPSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Error; + } + + /* Retrieve status before releasing mutex */ + status = handle->async_status; + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Translate status of underlying driver */ + if (status == kStatus_LPSPI_Idle) + { + status = kStatus_Success; + } + + return status; +} diff --git a/drivers/lpflexcomm/fsl_lpspi_freertos.h b/drivers/lpflexcomm/fsl_lpspi_freertos.h new file mode 100644 index 000000000..98fe4b16f --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpspi_freertos.h @@ -0,0 +1,103 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_FREERTOS_H__ +#define FSL_LPSPI_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" +#include "fsl_lpspi.h" + +/*! + * @addtogroup lpspi_freertos_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI FreeRTOS driver version 2.0.0. */ +#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPSPI FreeRTOS handle */ +typedef struct _lpspi_rtos_handle +{ + LPSPI_Type *base; /*!< LPSPI base address */ + lpspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ +} lpspi_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPSPI RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPSPI instance to initialize. + * @param masterConfig Configuration structure to set-up LPSPI in master mode. + * @param srcClock_Hz Frequency of input clock of the LPSPI module. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle); + +/*! + * @brief Performs LPSPI transfer. + * + * This function performs an LPSPI transfer according to data given in the transfer structure. + * + * @param handle The RTOS LPSPI handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_LPSPI_FREERTOS_H__ */ diff --git a/drivers/lpflexcomm/fsl_lpuart_freertos.c b/drivers/lpflexcomm/fsl_lpuart_freertos.c new file mode 100644 index 000000000..f78a4dc9f --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpuart_freertos.c @@ -0,0 +1,489 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_freertos.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpuart_freertos" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void LPUART_RTOS_Callback(LPUART_Type *base, lpuart_handle_t *state, status_t status, void *param) +{ + lpuart_rtos_handle_t *handle = (lpuart_rtos_handle_t *)param; + BaseType_t xHigherPriorityTaskWoken, xResult; + + xHigherPriorityTaskWoken = pdFALSE; + xResult = pdFAIL; + + if (status == kStatus_LPUART_RxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_TxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_LPUART_TX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxRingBufferOverrun) + { + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxHardwareOverrun) + { + /* Clear Overrun flag (OR) in LPUART STAT register */ + (void)LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag); + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else + { + xResult = pdFAIL; + } + + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Init + * Description : Initializes the LPUART instance for application + * + *END**************************************************************************/ +/*! + * brief Initializes an LPUART instance for operation in RTOS. + * + * param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * param t_handle The pointer to an allocated space to store the transactional layer internal state. + * param cfg The pointer to the parameters required to configure the LPUART after initialization. + * return kStatus_Success, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg) +{ + status_t status; + lpuart_config_t defcfg; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + if (NULL == t_handle) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg->base) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->srcclk) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->baudrate) + { + return kStatus_InvalidArgument; + } + + handle->base = cfg->base; + handle->t_state = t_handle; + handle->rx_timeout_constant_ms = cfg->rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = cfg->rx_timeout_multiplier_ms; + handle->tx_timeout_constant_ms = cfg->tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = cfg->tx_timeout_multiplier_ms; + +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer); +#else + handle->txSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->txSemaphore) + { + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer); +#else + handle->rxSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->rxSemaphore) + { + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer); +#else + handle->txEvent = xEventGroupCreate(); +#endif + if (NULL == handle->txEvent) + { + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer); +#else + handle->rxEvent = xEventGroupCreate(); +#endif + if (NULL == handle->rxEvent) + { + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + + LPUART_GetDefaultConfig(&defcfg); + + defcfg.baudRate_Bps = cfg->baudrate; + defcfg.parityMode = cfg->parity; + defcfg.stopBitCount = cfg->stopbits; +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + defcfg.enableRxRTS = cfg->enableRxRTS; + defcfg.enableTxCTS = cfg->enableTxCTS; + defcfg.txCtsSource = cfg->txCtsSource; + defcfg.txCtsConfig = cfg->txCtsConfig; +#endif + status = LPUART_Init(handle->base, &defcfg, cfg->srcclk); + if (status != kStatus_Success) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + LPUART_TransferCreateHandle(handle->base, handle->t_state, LPUART_RTOS_Callback, handle); + LPUART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); + + LPUART_EnableTx(handle->base, true); + LPUART_EnableRx(handle->base, true); + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Deinit + * Description : Deinitializes the LPUART instance and frees resources + * + *END**************************************************************************/ +/*! + * brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle) +{ + LPUART_Deinit(handle->base); + + vEventGroupDelete(handle->txEvent); + vEventGroupDelete(handle->rxEvent); + + /* Give the semaphore. This is for functional safety */ + (void)xSemaphoreGive(handle->txSemaphore); + (void)xSemaphoreGive(handle->rxSemaphore); + + vSemaphoreDelete(handle->txSemaphore); + vSemaphoreDelete(handle->rxSemaphore); + + /* Invalidate the handle */ + handle->base = NULL; + handle->t_state = NULL; + + return 0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Send + * Description : Send chars over LPUART + * + *END**************************************************************************/ +/*! + * brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer to send. + * param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) +{ + EventBits_t ev; + int retval = kStatus_Fail; + status_t status; + const TickType_t txTickTimeout = + (length * handle->tx_timeout_multiplier_ms + handle->tx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0u)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->txTransfer.data = (uint8_t *)buffer; + handle->txTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->txSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE, pdTRUE, pdFALSE, + (txTickTimeout > 0u) ? txTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_TX_COMPLETE) != 0u) + { + retval = kStatus_Success; + } + else /* timeout expired or unknown error*/ + { + if (txTickTimeout > 0u) + { + LPUART_TransferAbortSend(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_Fail; + } + } + + if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Receive + * Description : Receives chars from LPUART + * + *END**************************************************************************/ +/*! + * brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer where to write received data. + * param length The number of bytes to receive. + * param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) +{ + EventBits_t ev; + size_t n = 0u; + int retval = kStatus_Fail; + uint32_t local_received = 0u; + status_t status; + const TickType_t rxTickTimeout = + (length * handle->rx_timeout_multiplier_ms + handle->rx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + if (received != NULL) + { + *received = n; + } + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + /* New transfer can be performed only after current one is finished */ + if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->rxTransfer.data = buffer; + handle->rxTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->rxSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits( + handle->rxEvent, + RTOS_LPUART_RX_COMPLETE | RTOS_LPUART_RING_BUFFER_OVERRUN | RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, pdTRUE, + pdFALSE, (rxTickTimeout > 0u) ? rxTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_HARDWARE_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxHardwareOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RING_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxRingBufferOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RX_COMPLETE) != 0u) + { + retval = kStatus_Success; + local_received = length; + } + else /* timeout expired or unknown error*/ + { + if (rxTickTimeout > 0u) + { + (void)LPUART_TransferGetReceiveCount(handle->base, handle->t_state, &local_received); + LPUART_TransferAbortReceive(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_LPUART_Error; + local_received = 0u; + } + } + + /* Prevent repetitive NULL check */ + if (received != NULL) + { + *received = (size_t)local_received; + } + + /* Enable next transfer. Current one is finished */ + if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetRxTimeout + * Description : Modify receive timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->rx_timeout_constant_ms = rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = rx_timeout_multiplier_ms; + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetTxTimeout + * Description : Modify send timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->tx_timeout_constant_ms = tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = tx_timeout_multiplier_ms; + return kStatus_Success; +} diff --git a/drivers/lpflexcomm/fsl_lpuart_freertos.h b/drivers/lpflexcomm/fsl_lpuart_freertos.h new file mode 100644 index 000000000..57d453da1 --- /dev/null +++ b/drivers/lpflexcomm/fsl_lpuart_freertos.h @@ -0,0 +1,192 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPUART_FREERTOS_H__ +#define FSL_LPUART_FREERTOS_H__ + +#include "fsl_lpuart.h" +#include "FreeRTOS.h" +#include "event_groups.h" +#include "semphr.h" + +/*! + * @addtogroup lpuart_freertos_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART FreeRTOS driver version 2.0.0. */ +#define FSL_LPUART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPUART RTOS configuration structure. */ +typedef struct _lpuart_rtos_config +{ + LPUART_Type *base; /*!< UART base address */ + uint32_t srcclk; /*!< UART source clock in Hz*/ + uint32_t baudrate; /*!< Desired communication speed */ + lpuart_parity_mode_t parity; /*!< Parity setting */ + lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ + uint8_t *buffer; /*!< Buffer for background reception */ + uint32_t buffer_size; /*!< Size of buffer for background reception */ + /* Zero in constant and multiplier is interpreted as infinit timeout. */ + uint32_t rx_timeout_constant_ms; /*!< RX timeout applied per receive */ + uint32_t rx_timeout_multiplier_ms; /*!< RX timeout added for each byte of the receive. */ + uint32_t tx_timeout_constant_ms; /*!< TX timeout applied per transmition */ + uint32_t tx_timeout_multiplier_ms; /*!< TX timeout added for each byte of the transmition. */ +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif +} lpuart_rtos_config_t; + +/*! + * @cond RTOS_PRIVATE + * @name LPUART event flags + * + * This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t). + */ +/*@{*/ +/*! @brief Event flag - uart transmit complete. */ +#define RTOS_LPUART_TX_COMPLETE 0x1U +/*! @brief Event flag - uart receive complete. */ +#define RTOS_LPUART_RX_COMPLETE 0x2U +/*! @brief Event flag - ring buffer overrun. */ +#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x4U +/*! @brief Event flag - hardware buffer overrun. */ +#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x8U +/*@}*/ + +/*! @brief LPUART FreeRTOS transfer structure. */ +typedef struct _lpuart_rtos_handle +{ + LPUART_Type *base; /*!< UART base address */ + lpuart_transfer_t txTransfer; /*!< TX transfer structure */ + lpuart_transfer_t rxTransfer; /*!< RX transfer structure */ + SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ + SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ + EventGroupHandle_t rxEvent; /*!< RX completion event */ + EventGroupHandle_t txEvent; /*!< TX completion event */ + uint32_t rx_timeout_constant_ms; /*!< RX Timeout applied per transfer */ + uint32_t rx_timeout_multiplier_ms; /*!< RX Timeout added for each byte of the transfer. */ + uint32_t tx_timeout_constant_ms; /*!< TX Timeout applied per transfer */ + uint32_t tx_timeout_multiplier_ms; /*!< TX Timeout added for each byte of the transfer. */ + void *t_state; /*!< Transactional state of the underlying driver */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */ + StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */ + StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */ + StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */ +#endif +} lpuart_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPUART RTOS Operation + * @{ + */ + +/*! + * @brief Initializes an LPUART instance for operation in RTOS. + * + * @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * @param t_handle The pointer to an allocated space to store the transactional layer internal state. + * @param cfg The pointer to the parameters required to configure the LPUART after initialization. + * @return 0 succeed, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg); + +/*! + * @brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * @param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle); + +/*! + * @name LPUART transactional Operation + * @{ + */ + +/*! + * @brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer to send. + * @param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); + +/*! + * @brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer where to write received data. + * @param length The number of bytes to receive. + * @param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); + +/*! + * @brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms); + +/*! + * @brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_FREERTOS_H__ */ diff --git a/drivers/lpflexcomm/lpi2c/fsl_lpi2c.c b/drivers/lpflexcomm/lpi2c/fsl_lpi2c.c new file mode 100644 index 000000000..43e081a0f --- /dev/null +++ b/drivers/lpflexcomm/lpi2c/fsl_lpi2c.c @@ -0,0 +1,2423 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c" +#endif + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(uint32_t instance, void *handle); + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t` + */ +typedef union lpi2c_to_lpflexcomm +{ + lpi2c_master_isr_t lpi2c_master_handler; + lpi2c_slave_isr_t lpi2c_slave_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpi2c_to_lpflexcomm_t; + +/* ! @brief LPI2C master fifo commands. */ +enum +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler); + +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); + +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +void *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The LPI2C peripheral base address. + * return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base) +{ + uint32_t instance; + for (instance = 0U; instance < ARRAY_SIZE(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(kLpi2cBases)); + return instance; +} + +/*! + * @brief Computes a cycle count for a given time in nanoseconds. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param width_ns Desired with in nanoseconds. + * @param minCycles Minimum cycle count. + * @param maxCycles Maximum cycle count. + * @param prescaler LPI2C prescaler setting. If the cycle period is not affected by the prescaler value, set it to 0. + */ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler) +{ + assert(sourceClock_Hz > 0U); + + uint32_t divider = 1U; + + while (prescaler != 0U) + { + divider *= 2U; + prescaler--; + } + + uint32_t busCycle_ns = 1000000U / (sourceClock_Hz / divider / 1000U); + /* Calculate the cycle count, round up the calculated value. */ + uint32_t cycles = (width_ns * 10U / busCycle_ns + 5U) / 10U; + + /* If the calculated value is smaller than the minimum value, use the minimum value */ + if (cycles < minCycles) + { + cycles = minCycles; + } + /* If the calculated value is larger than the maximum value, use the maxmum value */ + if (cycles > maxCycles) + { + cycles = maxCycles; + } + + return cycles; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kLPI2C_MasterErrorFlags; + if (0U != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * @brief Wait until there is room in the tx fifo. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + size_t txCount; + size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (kStatus_Success != result) + { + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == txCount) && (0U != waitTimes)); + + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == txCount); +#endif + + return result; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Busy + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) +{ + status_t ret = kStatus_Success; + + uint32_t status = LPI2C_MasterGetStatusFlags(base); + if ((0U != (status & (uint32_t)kLPI2C_MasterBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_MasterBusyFlag))) + { + ret = kStatus_LPI2C_Busy; + } + + return ret; +} + +/*! + * brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0U; + * masterConfig->pinLowTimeout_ns = 0U; + * masterConfig->sdaGlitchFilterWidth_ns = 0U; + * masterConfig->sclGlitchFilterWidth_ns = 0U; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->pinLowTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +/*! + * brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The LPI2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + uint32_t value; + uint32_t instance = LPI2C_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Reset peripheral before configuring it. */ + LPI2C_MasterReset(base); + + /* Doze bit: 0 is enable, 1 is disable */ + base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); + + /* host request */ + value = base->MCFGR0; + value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); + value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | + LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | + LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); + base->MCFGR0 = value; + + /* pin config and ignore ack */ + value = base->MCFGR1; + value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); + value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); + base->MCFGR1 = value; + + LPI2C_MasterSetWatermarks(base, (size_t)kDefaultTxWatermark, (size_t)kDefaultRxWatermark); + + /* Configure glitch filters. */ + cfgr2 = base->MCFGR2; + if (0U != (masterConfig->sdaGlitchFilterWidth_ns)) + { + /* Calculate SDA filter width. The width is equal to FILTSDA cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); + } + if (0U != masterConfig->sclGlitchFilterWidth_ns) + { + /* Calculate SDL filter width. The width is equal to FILTSCL cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); + } + base->MCFGR2 = cfgr2; + + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + + /* Configure bus idle and pin low timeouts after baudrate setting, + since the timeout calculation needs prescaler as parameter. */ + prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; + + if (0U != (masterConfig->busIdleTimeout_ns)) + { + /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by + prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; + cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); + } + base->MCFGR2 = cfgr2; + if (0U != masterConfig->pinLowTimeout_ns) + { + /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by + prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); + } + + LPI2C_MasterEnable(base, masterConfig->enableMaster); +} + +/*! + * brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base) +{ + uint32_t instance = LPI2C_GetInstance(base); + + /* Restore to reset state. */ + LPI2C_MasterReset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); +#endif +} + +/*! + * brief Configures LPI2C master data match feature. + * + * param base The LPI2C peripheral base address. + * param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig) +{ + /* Disable master mode. */ + bool wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(matchConfig->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(matchConfig->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(matchConfig->match0) | LPI2C_MDMR_MATCH1(matchConfig->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * param base The LPI2C peripheral base address. + * param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + bool wasEnabled; + uint8_t filtScl = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSCL_MASK) >> LPI2C_MCFGR2_FILTSCL_SHIFT); + + uint8_t divider = 1U; + uint8_t bestDivider = 1U; + uint8_t prescale = 0U; + uint8_t bestPre = 0U; + + uint8_t clkCycle; + uint8_t bestclkCycle = 0U; + + uint32_t absError = 0U; + uint32_t bestError = 0xffffffffu; + uint32_t computedRate; + + uint32_t tmpReg = 0U; + + /* Disable master mode. */ + wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + /* Baud rate = (sourceClock_Hz / 2 ^ prescale) / (CLKLO + 1 + CLKHI + 1 + SCL_LATENCY) + * SCL_LATENCY = ROUNDDOWN((2 + FILTSCL) / (2 ^ prescale)) + */ + for (prescale = 0U; prescale <= 7U; prescale++) + { + /* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */ + clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U); + /* According to register description, The max value for CLKLO and CLKHI is 63. + however to meet the I2C specification of tBUF, CLKHI should be less than + clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U. Refer to the comment of the tmpHigh's + calculation for details. So we have: + CLKHI < clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U, + clkCycle = CLKHI + CLKLO and + sourceClock_Hz / baudRate_Hz / divider = clkCycle + 2 + ROUNDDOWN((2 + FILTSCL) / divider), + we can come up with: CLKHI < 0.92 x CLKLO - ROUNDDOWN(2 + FILTSCL) / divider + so the max boundary of CLKHI should be 0.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider, + and the max boundary of clkCycle is 1.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider. */ + if (clkCycle > (120U - (2U + filtScl) / divider)) + { + divider *= 2U; + continue; + } + /* Calculate the computed baudrate and compare it with the desired baudrate */ + computedRate = (sourceClock_Hz / (uint32_t)divider) / + ((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider); + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + if (absError < bestError) + { + bestPre = prescale; + bestDivider = divider; + bestclkCycle = clkCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) + { + break; + } + } + divider *= 2U; + } + + /* SCL low time tLO should be larger than or equal to SCL high time tHI: + tLO = ((CLKLO + 1) x (2 ^ PRESCALE)) >= tHI = ((CLKHI + 1 + SCL_LATENCY) x (2 ^ PRESCALE)), + which is CLKLO >= CLKHI + (2U + filtScl) / bestDivider. + Also since bestclkCycle = CLKLO + CLKHI, bestDivider = 2 ^ PRESCALE + which makes CLKHI <= (bestclkCycle - (2U + filtScl) / bestDivider) / 2U. + + The max tBUF should be at least 0.52 times of the SCL clock cycle: + tBUF = ((CLKLO + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.52 / baudRate_Hz), + plus bestDivider = 2 ^ PRESCALE, bestclkCycle = CLKLO + CLKHI we can come up with + CLKHI <= (bestclkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / bestDivider + 1U). + In this case to get a safe CLKHI calculation, we can assume: + */ + uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U; + while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U)) + { + tmpHigh = tmpHigh - 1U; + } + + /* Calculate DATAVD and SETHOLD. + To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */ + /* The min tHD:STA/tSU:STA/tSU:STO should be at least 0.4 times of the SCL clock cycle, use 0.5 to be safe: + tHD:STA = ((SETHOLD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.5 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U; + + /* The max tVD:DAT/tVD:ACK/tHD:DAT should be at most 0.345 times of the SCL clock cycle, use 0.25 to be safe: + tVD:DAT = ((DATAVD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) < (0.25 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U; + + /* The min tSU:DAT should be at least 0.05 times of the SCL clock cycle: + tSU:DAT = ((2 + FILTSDA + 2 ^ PRESCALE) / sourceClock_Hz) >= (0.05 / baud), + plus bestDivider = 2 ^ PRESCALE, we can come up with: + FILTSDA >= (0.05 x sourceClock_Hz / baudRate_Hz - bestDivider - 2) */ + if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U)) + { + /* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */ + uint8_t filtSda = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSDA_MASK) >> LPI2C_MCFGR2_FILTSDA_SHIFT); + if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U)) + { + filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U; + } + base->MCFGR2 = (base->MCFGR2 & ~LPI2C_MCFGR2_FILTSDA_MASK) | LPI2C_MCFGR2_FILTSDA(filtSda); + } + + /* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */ + tmpReg = LPI2C_MCCR0_CLKHI((uint32_t)tmpHigh) | + LPI2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) | + LPI2C_MCCR0_SETHOLD((uint32_t)tmpHold) | LPI2C_MCCR0_DATAVD((uint32_t)tmpDataVd); + base->MCCR0 = tmpReg; + + /* Set PRESCALE value. */ + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The LPI2C peripheral base address. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + /* Return an error if the bus is already in use not by us. */ + status_t result = LPI2C_CheckForBusyBus(base); + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Wait until there is room in the fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue start command. */ + base->MTDR = (uint32_t)kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); + } + } + + return result; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Send the STOP signal */ + base->MTDR = (uint32_t)kStopCmd; + + /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ + /* Also check for errors while waiting. */ +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + +#if I2C_RETRY_TIMES != 0U + while ((result == kStatus_Success) && (0U != waitTimes)) + { + waitTimes--; +#else + while (result == kStatus_Success) + { +#endif + uint32_t status = LPI2C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(base, status); + + /* Check if the stop was sent successfully. */ + if ((0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) && + (0U != (status & (uint32_t)kLPI2C_MasterTxReadyFlag))) + { + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if I2C_RETRY_TIMES != 0U + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#endif + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) +{ + assert(NULL != rxBuff); + + status_t result = kStatus_Success; + uint8_t *buf; + size_t tmpRxSize = rxSize; +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes; +#endif + + /* Check transfer data size. */ + if (rxSize > (256UL * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base))) + { + return kStatus_InvalidArgument; + } + + /* Handle empty read. */ + if (rxSize != 0U) + { + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue command to receive data. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data + at most, so when the rxSize is larger than 0x100U, push multiple read commands to MTDR until rxSize is + reached. */ + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0U != (rxSize--)) + { +#if I2C_RETRY_TIMES != 0U + waitTimes = I2C_RETRY_TIMES; +#endif + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value = 0U; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); + if (kStatus_Success != result) + { + break; + } + + value = base->MRDR; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U != (value & LPI2C_MRDR_RXEMPTY_MASK)); +#endif + if ((status_t)kStatus_Success != result) + { + break; + } + + *buf++ = (uint8_t)(value & LPI2C_MRDR_DATA_MASK); + } + } + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0U != (txSize--)) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = *buf++; + } + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The LPI2C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + status_t ret = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0U; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > (256UL * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + lpi2c_direction_t direction = (0U != transfer->subaddressSize) ? kLPI2C_Write : transfer->direction; + if (0U == (transfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != transfer->dataSize) && (transfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Send command buffer */ + uint32_t index = 0U; + while (0U != cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = commandBuffer[index]; + index++; + } + + if (kStatus_Success == result) + { + /* Transmit data. */ + if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0U)) + { + /* Send Data. */ + result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0U)) + { + result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); + } + + if (kStatus_Success == result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + result = LPI2C_MasterStop(base); + } + } + } + /* Transmit fail */ + if (kStatus_Success != result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + ret = LPI2C_MasterStop(base); + if(kStatus_Success != ret) + { + result = ret; + } + } + } + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + } + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + status_t result = kStatus_Success; + lpi2c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + bool state_complete = false; + uint16_t sendval; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = LPI2C_MasterGetStatusFlags(base); + + /* Get fifo counts. */ + LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* For the last byte, nack flag is expected. + Do not check and clear kLPI2C_MasterNackDetectFlag for the last byte, + in case FIFO is emptied when stop command has not been sent. */ + if (handle->remainingBytes == 0U) + { + /* When data size is not zero which means it is not only one byte of address is sent, and */ + /* when the txfifo is empty, or have one byte which is the stop command, then the nack status can be ignored. */ + if ((xfer->dataSize != 0U) && + ((txCount == 0U) || ((txCount == 1U) && (handle->state == (uint8_t)kWaitForCompletionState) && + ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)))) + { + status &= ~(uint32_t)kLPI2C_MasterNackDetectFlag; + } + } + + result = LPI2C_MasterCheckAndClearError(base, status); + + if (kStatus_Success == result) + { + /* Compute room in tx fifo */ + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSendCommandState: + /* Make sure there is room in the tx fifo for the next command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + sendval = ((uint16_t)handle->buf[0]) | (((uint16_t)handle->buf[1]) << 8U); + base->MTDR = sendval; + handle->buf++; + handle->buf++; + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0U) + { + /* Choose next state and set up buffer pointer and count. */ + if (0U != xfer->dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = (uint8_t)kTransferDataState; + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + /* Issue command to receive data. A single write to MTDR can issue read operation of + 0xFFU + 1 byte of data at most, so when the dataSize is larger than 0x100U, push + multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + while (txFifoSize == txCount) + { + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + } + + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = (uint8_t)kStopState; + } + } + break; + + case (uint8_t)kIssueReadCommandState: + /* Make sure there is room in the tx fifo for the read command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + base->MTDR = (uint32_t)kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1U); + + /* Move to transfer state. */ + handle->state = (uint8_t)kTransferDataState; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + } + break; + + case (uint8_t)kTransferDataState: + if (xfer->direction == kLPI2C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + /* Put byte to send in fifo. */ + base->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (0U == rxCount--) + { + state_complete = true; + break; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = (uint8_t)(base->MRDR & LPI2C_MRDR_DATA_MASK); + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0U) + { + if (xfer->direction == kLPI2C_Write) + { + state_complete = true; + } + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + base->MTDR = (uint32_t)kStopCmd; + } + else + { + /* If all data is read and no stop flag is required to send, we are done. */ + if (xfer->direction == kLPI2C_Read) + { + *isDone = true; + } + state_complete = true; + } + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* We stay in this state until the stop state is detected. */ + if (0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) + { + *isDone = true; + } + } + else + { + /* If all data is pushed to FIFO and no stop flag is required to send, we need to make sure they + are all send out to bus. */ + if ((xfer->direction == kLPI2C_Write) && ((base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) == 0U)) + { + /* We stay in this state until the data is sent out to bus. */ + *isDone = true; + } + } + state_complete = true; + break; + default: + assert(false); + break; + } + } + } + return result; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + handle->state = (uint8_t)kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = (uint8_t)kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0U; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + lpi2c_direction_t direction = (0U != xfer->subaddressSize) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (0U != xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != (subaddressRemaining--)) + { + uint8_t subaddressByte = (uint8_t)((xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Set up state machine for transferring the commands. */ + handle->state = (uint8_t)kSendCommandState; + handle->remainingBytes = (uint16_t)cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > (256U * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_LPI2C_Busy; + } + else + { + result = LPI2C_CheckForBusyBus(base); + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset FIFO in case there are data. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + } + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + if (NULL == count) + { + result = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + result = kStatus_NoTransferInProgress; + } + else + { + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); + LPI2C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + case (uint8_t) + kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + } + + return result; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & ((uint32_t)kLPI2C_MasterStopDetectFlag | + (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param instance The LPI2C instance. + * param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle) +{ + assert(lpi2cMasterHandle != NULL); + assert(instance < ARRAY_SIZE(kLpi2cBases)); + LPI2C_Type *base = kLpi2cBases[instance]; + lpi2c_master_handle_t *handle = (lpi2c_master_handle_t *)lpi2cMasterHandle; + bool isDone = false; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL != handle) + { + if (handle->state != (uint8_t)kIdleState) + { + result = LPI2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Handle error, terminate xfer */ + if (result != kStatus_Success) + { + LPI2C_MasterTransferAbort(base, handle); + } + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke callback. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } + } + } +} + +/*! + * brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a + * address0 member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; + slaveConfig->enableReceivedAddressRead = false; + slaveConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->dataValidDelay_ns = 0U; + /* When enabling the slave tx SCL stall, set the default clock hold time to 250ns according + to I2C spec for standard mode baudrate(100k). User can manually change it to 100ns or 50ns + for fast-mode(400k) or fast-mode+(1m). */ + slaveConfig->clockHoldTime_ns = 250U; +} + +/*! + * brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * param base The LPI2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) +{ + uint32_t tmpReg; + uint32_t tmpCycle; + uint32_t instance = LPI2C_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Restore to reset conditions. */ + LPI2C_SlaveReset(base); + + /* Configure peripheral. */ + base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); + + base->SCFGR1 = + LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | + LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | + LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | + LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | + LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); + + /* Calculate SDA filter width. The width is equal to FILTSDA+3 cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 4. */ + tmpReg = LPI2C_SCFGR2_FILTSDA( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT) + 3U, 0U) - + 3U); + + /* Calculate SDL filter width. The width is equal to FILTSCL+3 cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 4. */ + tmpCycle = LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT) + 3U, 0U); + tmpReg |= LPI2C_SCFGR2_FILTSCL(tmpCycle - 3U); + + /* Calculate data valid time. The time is equal to FILTSCL+DATAVD+3 cycles of functional clock. + So the min value is FILTSCL+3. */ + tmpReg |= LPI2C_SCFGR2_DATAVD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, tmpCycle, + tmpCycle + (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 0U) - + tmpCycle); + + /* Calculate clock hold time. The time is equal to CLKHOLD+3 cycles of functional clock. + So the min value is 3. */ + base->SCFGR2 = + tmpReg | LPI2C_SCFGR2_CLKHOLD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, 3U, + (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT) + 3U, 0U) - + 3U); + + /* Save SCR to last so we don't enable slave until it is configured */ + base->SCR = LPI2C_SCR_FILTDZ(!slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | + LPI2C_SCR_SEN(slaveConfig->enableSlave); +} + +/*! + * brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base) +{ + uint32_t instance = LPI2C_GetInstance(base); + + /* Restore to reset state. */ + LPI2C_SlaveReset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); +#endif +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_BitError + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= (uint32_t)kLPI2C_SlaveErrorFlags; + if (0U != flags) + { + if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag)) + { + result = kStatus_LPI2C_BitError; + } + else if (0U != (flags & (uint32_t)kLPI2C_SlaveFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the errors. */ + LPI2C_SlaveClearStatusFlags(base, flags); + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param[out] actualTxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + size_t remaining = txSize; + + assert(NULL != txBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if (kStatus_Success != result) + { + break; + } + + /* Send a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + base->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart in transfer*/ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param[out] actualRxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert(NULL != rxBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if ((status_t)kStatus_Success != result) + { + break; + } + + /* Receive a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + *buf++ = (uint8_t)(base->SRDR & LPI2C_SRDR_DATA_MASK); + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + } + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + result = kStatus_LPI2C_Busy; + } + else + { + /* Return an error if the bus is already in use not by us. */ + uint32_t status = LPI2C_SlaveGetStatusFlags(base); + if ((0U != (status & (uint32_t)kLPI2C_SlaveBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_SlaveBusyFlag))) + { + result = kStatus_LPI2C_Busy; + } + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kLPI2C_SlaveTransmitEvent | (uint32_t)kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + base->STAR = 0U; + + /* Clear all flags. */ + LPI2C_SlaveClearStatusFlags(base, (uint32_t)kLPI2C_SlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + } + + return result; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The LPI2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) +{ + status_t status = kStatus_Success; + + assert(NULL != handle); + + if (count == NULL) + { + status = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (!handle->isBusy) + { + *count = 0; + status = kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + else + { + *count = handle->transferredCount; + } + + return status; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param instance The LPI2C instance. + * param lpi2cSlaveHandle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle) +{ + assert(instance < ARRAY_SIZE(kLpi2cBases)); + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + LPI2C_Type *base = kLpi2cBases[instance]; + lpi2c_slave_handle_t *handle = (lpi2c_slave_handle_t *)lpi2cSlaveHandle; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL != handle) + { + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(base); + + if (0U != (flags & ((uint32_t)kLPI2C_SlaveBitErrFlag | (uint32_t)kLPI2C_SlaveFifoErrFlag))) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + if (0U != + (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag)))) + { + xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ? + kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0U; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = false; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + /* Clear the flag. */ + LPI2C_SlaveClearStatusFlags(base, flags & ((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag | + (uint32_t)kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + base->STAR = 0U; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (0U != (flags & (uint32_t)kLPI2C_SlaveStopDetectFlag)) + { + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveAddressValidFlag)) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = (uint8_t)(base->SASR & LPI2C_SASR_RADDR_MASK); + + /* Update handle status to busy because slave is addressed. */ + handle->isBusy = true; + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveTransmitAckFlag)) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + else + { + LPI2C_SlaveTransmitAck(base, true); + } + } + + /* Handle transmit and receive. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Transmit a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + base->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Receive a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + *xfer->data++ = (uint8_t)base->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) + { + if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) || + (NULL == handle->callback))) + { + LPI2C_SlaveTransmitAck(base, true); + } + } + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) + { + if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) || + (NULL == handle->callback))) + { + LPI2C_SlaveTransmitAck(base, false); + } + } + } + } + } + } +} + +#if !(defined(FSL_FEATURE_I2C_HAS_NO_IRQ) && FSL_FEATURE_I2C_HAS_NO_IRQ) +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((0U != (base->MCR & LPI2C_MCR_MEN_MASK)) && (NULL != s_lpi2cMasterIsr)) + { + /* Master mode. */ + s_lpi2cMasterIsr(instance, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((0U != (base->SCR & LPI2C_SCR_SEN_MASK)) && (NULL != s_lpi2cSlaveIsr)) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(instance, s_lpi2cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(LPI2C15) +/* Implementation of LPI2C15 handler named in startup code. */ +void LPI2C15_DriverIRQHandler(void); +void LPI2C15_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C15, 15U); +} +#endif diff --git a/drivers/lpflexcomm/lpi2c/fsl_lpi2c.h b/drivers/lpflexcomm/lpi2c/fsl_lpi2c.h new file mode 100644 index 000000000..cd7cba033 --- /dev/null +++ b/drivers/lpflexcomm/lpi2c/fsl_lpi2c.h @@ -0,0 +1,1342 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPI2C_H_ +#define FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C driver version. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout polling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK, /*!< Bus busy flag */ + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_MasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag | kLPI2C_MasterDataMatchFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_MasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + /*! Errors to check for. */ + kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | + kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[6]; /*!< LPI2C command sequence. When all 6 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs. + */ +typedef void (*lpi2c_master_isr_t)(uint32_t instance, void *handle); + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_SlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_SlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + /*! Errors to check for. */ + kLPI2C_SlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to + disable. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to + disable. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. + When this event is set, the driver will no longer decide to reply to ack/nack. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern IRQn_Type const kLpi2cIrqs[]; + +/*! Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern void *s_lpi2cMasterHandle[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The LPI2C peripheral base address. + * @return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base); + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of _lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return ((base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param instance The LPI2C instance. + * @param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*@}*/ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return ((base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Enables or disables ACKSTALL. + * + * When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to + * a byte from the master. + * + * @param base The LPI2C peripheral base address. + * @param enable True will enable ACKSTALL,false will disable ACKSTALL. + */ +static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable) +{ + if (enable) + { + base->SCFGR1 |= LPI2C_SCFGR1_ACKSTALL_MASK; + } + else + { + base->SCFGR1 &= ~LPI2C_SCFGR1_ACKSTALL_MASK; + } +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param instance The LPI2C instance. + * @param lpi2cSlaveHandle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_LPI2C_H_ */ diff --git a/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c b/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c new file mode 100644 index 000000000..a49cf9fb1 --- /dev/null +++ b/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.c @@ -0,0 +1,636 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_edma.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c_edma" +#endif + +/* @brief Mask to align an address to 32 bytes. */ +#define ALIGN_32_MASK (0x1fU) + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t` + */ +typedef union lpi2c_to_lpflexcomm_edma +{ + lpi2c_master_isr_t lpi2c_master_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpi2c_to_lpflexcomm_edma_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. + * @param handle Master DMA driver handle. + * @return Number of command words. + */ +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); + +/*! + * @brief DMA completion callback. + * @param dmaHandle DMA channel handle for the channel that completed. + * @param userData User data associated with the channel handle. For this callback, the user data is the + * LPI2C DMA driver handle. + * @param isTransferDone Whether the DMA transfer has completed. + * @param tcds Number of TCDs that completed. + */ +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); + +/*! + * @brief LPI2C master edma transfer IRQ handle routine. + * + * This API handles the LPI2C bus error status and invoke callback if needed. + * + * @param base The LPI2C peripheral base address. + * @param lpi2cMasterEdmaHandle Pointer to the LPI2C master edma handle. + */ +static void LPI2C_MasterTransferEdmaHandleIRQ(uint32_t instance, void *lpi2cMasterEdmaHandle); +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t lpi2c_edma_RecSetting = 0x02; + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + assert(rxDmaHandle != NULL); + assert(txDmaHandle != NULL); + + /* Look up instance number */ + uint32_t instance = LPI2C_GetInstance(base); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ + /* in order to make the transfer API code simpler. */ + handle->base = base; + handle->completionCallback = callback; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_edma_t handler; + handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ; + + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */ + s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ; + } + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Set DMA channel completion callbacks. */ + EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); + } +} + +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Handle no start option. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag) != 0U) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(xfer->dataSize - 1U); + } + } + else + { + /* + * Initial direction depends on whether a subaddress was provided, and of course the actual + * data transfer direction. + */ + lpi2c_direction_t direction = (xfer->subaddressSize != 0U) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize != 0U) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)(xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ + if ((xfer->dataSize != 0U) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when + the dataSize is larger than 0x100U, push multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + + return cmdCount; +} + +/*! + * brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the a handle was created is invoked when the transaction has + * completed. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle != NULL); + assert(transfer != NULL); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Check transfer data size in read operation. */ + /* A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when the dataSize is larger + than 0x100U, push multiple read commands to MTDR until dataSize is reached. LPI2C edma transfer uses linked + descriptor to transfer command and data, the command buffer is stored in handle. Allocate 4 command words to + carry read command which can cover nearly all use cases. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > (256U * 4U))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result != kStatus_Success) + { + return result; + } + + /* We're now busy. */ + handle->isBusy = true; + + /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + LPI2C_MasterEnableDMA(base, false, false); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + uint32_t commandCount = LPI2C_GenerateCommands(handle); + + /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ + if ((0U == commandCount) && (transfer->dataSize == 0U)) + { + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + return kStatus_Success; + } + + /* Reset DMA channels. */ + EDMA_ResetChannel(handle->rx->base, handle->rx->channel); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_ResetChannel(handle->tx->base, handle->tx->channel); + } + + /* Get a 32-byte aligned TCD pointer. */ + edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); + + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize != 0U); + bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize != 0U); + + edma_transfer_config_t transferConfig = {0}; + edma_tcd_t *linkTcd = NULL; + + /* Set up data transmit. */ + if (hasSendData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + transferConfig.srcAddr = (uint32_t)srcAddr; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if (commandCount != 0U) + { + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + else + { + /* User is only transmitting data with no required commands, so this transfer can stand alone. */ + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + } + else if (hasReceiveData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + /* Set up data receive. */ + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)srcAddr; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if ((FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) || (0U == commandCount)) + { + /* We can put this receive transfer on its own DMA channel. */ + EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + else + { + /* For shared rx/tx DMA requests, when there are commands, create a software TCD of + enabling rx dma and disabling tx dma, which will be chained onto the commands transfer, + and create another software TCD of transfering data and chain it onto the last TCD. + Notice that in this situation assume tx/rx uses same channel */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); + + transferConfig.srcAddr = (uint32_t)&lpi2c_edma_RecSetting; + transferConfig.destAddr = (uint32_t) & (base->MDER); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); + transferConfig.majorLoopCounts = 1; + + edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK)); + + EDMA_TcdReset(tcdSetRxClearTxDMA); + EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd); + linkTcd = tcdSetRxClearTxDMA; + } + } + else + { + /* No data to send */ + } + + if (hasSendData) + { + } + + /* Set up commands transfer. */ + if (commandCount != 0U) + { + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; + + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); + } + + /* Start DMA transfer. */ + if (hasReceiveData || (0 == FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base))) + { + EDMA_StartTransfer(handle->rx); + } + + if ((hasSendData || (commandCount != 0U)) && (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0)) + { + EDMA_StartTransfer(handle->tx); + } + + /* Enable DMA in both directions. This actually kicks of the transfer. */ + LPI2C_MasterEnableDMA(base, true, true); + + /* Enable all LPI2C master interrupts */ + LPI2C_MasterEnableInterrupts(base, + (uint32_t)kLPI2C_MasterArbitrationLostFlag | (uint32_t)kLPI2C_MasterNackDetectFlag | + (uint32_t)kLPI2C_MasterPinLowTimeoutFlag | (uint32_t)kLPI2C_MasterFifoErrFlag); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint32_t remaining = handle->transfer.dataSize; + + /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ + /* we do nothing and return the number of transferred bytes as zero. */ + if (EDMA_GetNextTCDAddress(handle->tx) == 0U) + { + if (handle->transfer.direction == kLPI2C_Write) + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); + } + else + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); + } + } + + *count = handle->transfer.dataSize - remaining; + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) +{ + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + return kStatus_LPI2C_Idle; + } + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & + ((uint32_t)kLPI2C_MasterStopDetectFlag | (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->isBusy = false; + + return kStatus_Success; +} + +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) +{ + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; + + if (NULL == handle) + { + return; + } + + /* Check for errors. */ + status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); + + /* Done with this transaction. */ + handle->isBusy = false; + + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(handle->base, handle, result, handle->userData); + } +} + +static void LPI2C_MasterTransferEdmaHandleIRQ(uint32_t instance, void *lpi2cMasterEdmaHandle) +{ + assert(lpi2cMasterEdmaHandle != NULL); + assert(instance < ARRAY_SIZE(kLpi2cBases)); + LPI2C_Type *base = kLpi2cBases[instance]; + + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)lpi2cMasterEdmaHandle; + uint32_t status = LPI2C_MasterGetStatusFlags(base); + status_t result = kStatus_Success; + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Done with this transaction. */ + handle->isBusy = false; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Check error status */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear error status. */ + (void)LPI2C_MasterCheckAndClearError(base, status); + + /* Send stop flag if needed */ + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + status = LPI2C_MasterGetStatusFlags(base); + /* If bus is still busy and the master has not generate stop flag */ + if ((status & ((uint32_t)kLPI2C_MasterBusBusyFlag | (uint32_t)kLPI2C_MasterStopDetectFlag)) == + (uint32_t)kLPI2C_MasterBusBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } +} \ No newline at end of file diff --git a/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.h b/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.h new file mode 100644 index 000000000..e17be7799 --- /dev/null +++ b/drivers/lpflexcomm/lpi2c/fsl_lpi2c_edma.h @@ -0,0 +1,158 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPI2C_EDMA_H_ +#define FSL_LPI2C_EDMA_H_ + +#include "fsl_lpi2c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C EDMA driver version. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; + +/*! + * @brief Master DMA completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterCreateEDMAHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Handle associated with the completed transfer. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Driver handle for master DMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_edma_handle +{ + LPI2C_Type *base; /*!< LPI2C base pointer. */ + bool isBusy; /*!< Transfer state machine current state. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint16_t commandBuffer[10]; /*!< LPI2C command sequence. When all 10 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rx; /*!< Handle for receive DMA channel. */ + edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ + edma_tcd_t tcds[3]; /*!< Software TCD. Three are allocated to provide enough room to align to 32-bytes. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_LPI2C_EDMA_H_ */ diff --git a/drivers/lpflexcomm/lpspi/fsl_lpspi.c b/drivers/lpflexcomm/lpspi/fsl_lpspi.c new file mode 100644 index 000000000..09ef87cba --- /dev/null +++ b/drivers/lpflexcomm/lpspi/fsl_lpspi.c @@ -0,0 +1,2297 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpspi" +#endif + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpspi_default_watermarks +{ + kLpspiDefaultTxWatermark = 0, + kLpspiDefaultRxWatermark = 0, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpspi_master_isr_t)(uint32_t instance, lpspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpspi_slave_isr_t)(uint32_t instance, lpspi_slave_handle_t *handle); + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpuart_irq_handler_t` + */ +typedef union lpspi_to_lpflexcomm +{ + lpspi_master_isr_t lpspi_master_handler; + lpspi_slave_isr_t lpspi_slave_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpspi_to_lpflexcomm_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Configures the LPSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base LPSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type lpspi_pcs_polarity_config_t. + */ +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Combine the write data for 1 byte to 4 bytes. + * This is not a public API. + */ +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap); + +/*! + * @brief Separate the read data for 1 byte to 4 bytes. + * This is not a public API. + */ +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap); + +/*! + * @brief Wait for tx FIFO to be empty. + * This is not a public API. + * @param base LPSPI peripheral address. + * @return true for the tx FIFO is ready, false is not. + */ +static bool LPSPI_TxFifoReady(LPSPI_Type *base); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; + +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi IRQ number for each instance. */ +static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to lpspi clocks for each instance. */ +static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; + +#if defined(LPSPI_PERIPH_CLOCKS) +static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to lpspi handles for each instance. */ +static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)]; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpspi_master_isr_t s_lpspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpspi_slave_isr_t s_lpspiSlaveIsr; + +/********************************************************************************************************************** + * Code + *********************************************************************************************************************/ + +/*! + * brief Get the LPSPI instance from peripheral base address. + * + * param base LPSPI peripheral base address. + * return LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base) +{ + uint8_t instance = 0; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) + { + if (s_lpspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpspiBases)); + + return instance; +} + +/*! + * brief Set up the dummy data. + * + * param base LPSPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = LPSPI_GetInstance(base); + g_lpspiDummyData[instance] = dummyData; +} + +/*! + * brief Initializes the LPSPI master. + * + * param base LPSPI peripheral address. + * param masterConfig Pointer to structure lpspi_master_config_t. + * param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig != NULL); + + uint32_t tcrPrescaleValue = 0; + uint32_t instance = LPSPI_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPSPI mode */ + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Disable LPSPI first */ + LPSPI_Enable(base, false); + + /* Set LPSPI to master */ + LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); + + /* Set specific PCS to active high or low */ + LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + /* Set Configuration Register 1 related setting.*/ + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK | + LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK )) | + LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay )| + LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc); + + /* Set baudrate and delay times*/ + (void)LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); + + /* Set default watermarks */ + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + /* Set Transmit Command Register*/ + base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | + LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1U) | + LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); + + LPSPI_Enable(base, true); + + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, + srcClock_Hz); + + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); +} + +/*! + * brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->baudRate = 500000; + masterConfig->bitsPerFrame = 8; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; + + masterConfig->pcsToSckDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->lastSckToPcsDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->betweenTransferDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + + masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + masterConfig->pcsFunc = kLPSPI_PcsAsCs; + + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->dataOutConfig = kLpspiDataOutRetained; + + masterConfig->enableInputDelay = false; +} + +/*! + * brief LPSPI slave configuration. + * + * param base LPSPI peripheral address. + * param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + uint32_t instance = LPSPI_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPSPI mode */ + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); + + LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); + + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); + + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | + LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1U); + + /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); + + LPSPI_Enable(base, true); +} + +/*! + * brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ + + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->dataOutConfig = kLpspiDataOutRetained; +} + +/*! + * brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base) +{ + /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ + base->CR |= LPSPI_CR_RST_MASK; + + /* Software reset doesn't reset the CR, so manual reset the FIFOs */ + base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + + /* Master logic is not reset and module is disabled.*/ + base->CR = 0x00U; +} + +/*! + * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base) +{ + + uint32_t instance = LPSPI_GetInstance(base); + + /* Reset to default value */ + LPSPI_Reset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable LPSPI clock */ + (void)CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPSPI_GetInstance(base)); +#endif +} + +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t cfgr1Value = 0; + /* Clear the PCS polarity bit */ + cfgr1Value = base->CFGR1 & ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); + + /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ + base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); +} + +/*! + * brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param baudRate_Bps The desired baud rate in bits per second. + * param srcClock_Hz Module source input clock in Hertz. + * param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue) +{ + assert(tcrPrescaleValue != NULL); + + /* For master mode configuration only, if slave mode detected, return 0. + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ + if ((!LPSPI_IsMaster(base)) || ((base->CR & LPSPI_CR_MEN_MASK) != 0U)) + { + return 0U; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t desiredBaudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + + /* Set to maximum divisor value bit settings so that if baud rate passed in is less + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ + bestPrescaler = 7; + bestScaler = 255; + + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0U; prescaler < 8U; prescaler++) + { + if (min_diff == 0U) + { + break; + } + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); + + /* calculate the baud rate difference based on the conditional statement + * that states that the calculated baud rate must not exceed the desired baud rate + */ + if (desiredBaudrate >= realBaudrate) + { + diff = desiredBaudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + } + } + } + } + + /* Write the best baud rate scalar to the CCR. + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + base->CCR = base->CCR | LPSPI_CCR_DBT((base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT) | + LPSPI_CCR_SCKDIV(bestScaler); +#else + base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + + /* return the best prescaler value for user to use later */ + *tcrPrescaleValue = bestPrescaler; + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +/*! + * brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param scaler The 8-bit delay value 0x00 to 0xFF (255). + * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) +{ + /*These settings are only relevant in master mode */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + uint32_t dbt = (base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT; + uint32_t sckdiv = (base->CCR1 & LPSPI_CCR1_SCKHLD_MASK) >> LPSPI_CCR1_SCKHLD_SHIFT; + sckdiv += (base->CCR1 & LPSPI_CCR1_SCKSET_MASK) >> LPSPI_CCR1_SCKSET_SHIFT; + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = base->CCR | LPSPI_CCR_DBT(scaler) | LPSPI_CCR_SCKDIV(sckdiv); +#else + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + break; + default: + assert(false); + break; + } +} + +/*! + * brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * param base LPSPI peripheral address. + * param delayTimeInNanoSec The desired delay value in nano-seconds. + * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * param srcClock_Hz Module source input clock in Hertz. + * return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz) +{ + uint64_t realDelay, bestDelay; + uint32_t scaler, bestScaler; + uint32_t diff, min_diff; + uint64_t initialDelayNanoSec; + uint32_t clockDividedPrescaler; + + /* For delay between transfer, an additional scaler value is needed */ + uint32_t additionalScaler = 0; + + /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between + * transfers.*/ + clockDividedPrescaler = + srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; + + /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ + min_diff = 0xFFFFFFFFU; + + /* Initialize scaler to max value to generate the max delay */ + bestScaler = 0xFFU; + + /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as + * the delay divisors are slightly different based on which delay we are configuring. + */ + if (whichDelay == kLPSPI_BetweenTransfer) + { + /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of + calculated values (uint64_t), we need to break up the calculation into several steps to ensure + accurate calculated results + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec *= 2U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated + values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated + results. + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 0U; + } + + /* If the initial, default delay is already greater than the desired delay, then + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + LPSPI_MasterSetDelayScaler(base, 0, whichDelay); + return (uint32_t)initialDelayNanoSec; + } + + /* If min_diff = 0, the exit for loop */ + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + /* Calculate the real delay value as we cycle through the scaler values. + Due to large size of calculated values (uint64_t), we need to break up the + calculation into several steps to ensure accurate calculated results + */ + realDelay = 1000000000U; + realDelay *= ((uint64_t)scaler + 1UL + (uint64_t)additionalScaler); + realDelay /= clockDividedPrescaler; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = (uint32_t)(realDelay - (uint64_t)delayTimeInNanoSec); + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + + /* write the best scaler value for the delay */ + LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + + /* return the actual calculated delay value (in ns) */ + return (uint32_t)bestDelay; +} + +/*Transactional APIs -- Master*/ + +/*! + * brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_master_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance = LPSPI_GetInstance(base); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + } +} + +/*! + * brief Check the argument for transfer . + * + * param base LPSPI peripheral address. + * param transfer the transfer struct to be used. + * param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma) +{ + assert(transfer != NULL); + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; + uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0U) + { + return false; + } + + /* If both send buffer and receive buffer is null */ + if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) + { + return false; + } + + /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . + *For bytesPerFrame greater than 4 situation: + *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , + *otherwise , the transfer data size can be integer multiples of bytesPerFrame. + */ + if (bytesPerFrame <= 4U) + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + else + { + if ((bytesPerFrame % 4U) != 0U) + { + if (transfer->dataSize != bytesPerFrame) + { + return false; + } + } + else + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + } + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + /* The 3-wire mode can't send and receive data at the same time. */ + if ((transfer->txData != NULL) && (transfer->rxData != NULL)) + { + return false; + } + if (NULL == transfer->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + } + + if (isEdma && ((bytesPerFrame % 4U) == 3U)) + { + return false; + } + + return true; +} + +/*! + * brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) +{ + assert(transfer != NULL); + + /* Check that LPSPI is not busy.*/ + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + + /* Variables */ + bool isTxMask = false; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint8_t bytesEachWrite; + uint8_t bytesEachRead; + uint8_t *txData = transfer->txData; + uint8_t *rxData = transfer->rxData; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t readData = 0U; + uint32_t txRemainingByteCount = transfer->dataSize; + uint32_t rxRemainingByteCount = transfer->dataSize; + uint32_t wordToSend = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + uint32_t fifoSize = LPSPI_GetRxFifoSize(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + bool isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (bytesPerFrame < transfer->dataSize)); + uint32_t rxFifoMaxBytes = MIN(bytesPerFrame, 4U) * fifoSize; + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t width = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* Mask tx data in half duplex mode */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (txData == NULL)) + { + isTxMask = true; + } + + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs) | LPSPI_TCR_WIDTH(width); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(NULL == rxData); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (bytesPerFrame <= 4U) + { + bytesEachWrite = (uint8_t)bytesPerFrame; + bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + bytesEachWrite = 4U; + bytesEachRead = 4U; + } + + /*Write the TX data until txRemainingByteCount is equal to 0 */ + while (txRemainingByteCount > 0U) + { + if (txRemainingByteCount < bytesEachWrite) + { + bytesEachWrite = (uint8_t)txRemainingByteCount; + } + + /*Wait until TX FIFO is not full*/ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == fifoSize) && (--waitTimes != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == fifoSize) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + + /* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */ + if (((NULL == rxData) || (rxRemainingByteCount - txRemainingByteCount) < rxFifoMaxBytes)) + { + if (isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared + by hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if (isPcsContinuous && (txRemainingByteCount == bytesPerFrame)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + txRemainingByteCount -= bytesPerFrame; + } + else + { + if (txData != NULL) + { + wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); + txData += bytesEachWrite; + } + /* Otherwise push data to tx FIFO to initiate transfer */ + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= bytesEachWrite; + } + } + + /* Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun. */ + if ((rxData != NULL) && (rxRemainingByteCount != 0U)) + { + /* To ensure parallel execution in 3-wire mode, after writting 1 to TXMSK to generate clock of + bytesPerFrame's data wait until bytesPerFrame's data is received. */ + while (isTxMask && (LPSPI_GetRxFifoCount(base) == 0U)) + { + } +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = (uint8_t)rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + } + } + + if (isPcsContinuous && !isTxMask) + { + /* In PCS continous mode(TCR[CONT]), after write all the data in TX FIFO, TCR[CONTC] and TCR[CONT] should be + cleared to de-assert the PCS. Note that TCR register also use the TX FIFO. Also CONTC should be cleared when + tx is not masked, otherwise written to TCR register with TXMSK bit wet will initiate a new transfer. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == fifoSize) && (--waitTimes != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == fifoSize) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK)); + } + + /*Read out the RX data in FIFO*/ + if (rxData != NULL) + { + while (rxRemainingByteCount > 0U) + { +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = (uint8_t)rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + } + } + + /* Wait for transfer complete flag, that is the PCS is re-asserted. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) && (--waitTimes != 0U)) +#else + while ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the interrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + handle->isTxMask = false; + uint8_t txWatermark; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t tmpTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeTcrInIsr = false; + handle->bytesPerFrame = (uint16_t)((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + bool isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (transfer->dataSize > handle->bytesPerFrame)); + handle->writeRegRemainingTimes = + (transfer->dataSize / (uint32_t)handle->bytesPerFrame) * (((uint32_t)handle->bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (handle->bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)handle->bytesPerFrame; + handle->bytesEachRead = (uint8_t)handle->bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize - 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + /* Mask tx data in half duplex mode since the tx/rx share the same pin, so that the data received from slave is not + * interfered. */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (handle->txData == NULL)) + { + handle->isTxMask = true; + } + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(isRxMask); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. In this case TCR[TXMSK] should be set to + initiate each transfer. */ + + base->TCR |= LPSPI_TCR_TXMSK_MASK; + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + } + else + { + /* Fill up the TX data in FIFO to initiate transfer */ + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + if (handle->isTxMask) + { + /* if tx data is masked, transfer is initiated by writing 1 to TCR[TXMSK] and TCR[FRMESZ] bits of data is + read. If rx water mark is set larger than TCR[FRMESZ], rx interrupt will not be generated. Lower the rx + water mark setting */ + if ((handle->bytesPerFrame / 4U) < (uint16_t)handle->rxWatermark) + { + handle->rxWatermark = + (uint8_t)(handle->bytesPerFrame / 4U) > 0U ? (uint8_t)(handle->bytesPerFrame / 4U - 1U) : 0U; + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->rxWatermark); + } + } + else + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise + *there is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + tmpTimes = handle->readRegRemainingTimes; + if (tmpTimes <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(tmpTimes - 1U); + } + } + + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0; + uint8_t fifoSize = handle->fifoSize; + uint32_t writeRegRemainingTimes = handle->writeRegRemainingTimes; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + size_t txRemainingByteCount = handle->txRemainingByteCount; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ + while ((LPSPI_GetTxFifoCount(base) < fifoSize) && + (((readRegRemainingTimes - writeRegRemainingTimes) < (uint32_t)fifoSize) || (handle->rxData == NULL))) + { + if (txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + if (handle->txData != NULL) + { + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + } + else + { + wordToSend = handle->txBuffIfNull; + } + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + /*Decrease the write TX register times.*/ + --handle->writeRegRemainingTimes; + writeRegRemainingTimes = handle->writeRegRemainingTimes; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + txRemainingByteCount = handle->txRemainingByteCount; + + if (handle->txRemainingByteCount == 0U) + { + /* If PCS is continuous, update TCR to de-assert PCS */ + if (handle->isPcsContinuous) + { + /* Only write to the TCR if the FIFO has room */ + if (LPSPI_GetTxFifoCount(base) < fifoSize) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + /* Else, set a global flag to tell the ISR to do write to the TCR */ + else + { + handle->writeTcrInIsr = true; + } + } + break; + } + } +} + +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_Success, handle->userData); + } +} + +/*! + * brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +/*! + * brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * param instance LPSPI instance. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(uint32_t instance, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + assert(instance < ARRAY_SIZE(s_lpspiBases)); + LPSPI_Type *base = s_lpspiBases[instance]; + uint32_t readData; + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount != 0U) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + + while ((LPSPI_GetRxFifoCount(base) != 0U) && (handle->rxRemainingByteCount != 0U)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)(handle->rxRemainingByteCount); + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (handle->rxRemainingByteCount != 0U) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + + if (handle->txRemainingByteCount != 0U) + { + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if ((handle->txRemainingByteCount == (uint32_t)handle->bytesPerFrame) && (handle->isPcsContinuous)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + } + else + { + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + } + else + { + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + if ((handle->isPcsContinuous) && (handle->writeTcrInIsr) && (!handle->isTxMask)) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + } + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U) && (!handle->writeTcrInIsr)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + if (handle->rxData == NULL) + { + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) != 0U) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransferCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransferCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + } +} + +/*Transactional APIs -- Slave*/ +/*! + * brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_slave_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* Get instance from peripheral base address. */ + uint32_t instance = LPSPI_GetInstance(base); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + } +} + +/*! + * brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the inerrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + bool isTxMask = false; + uint8_t txWatermark; + uint32_t readRegRemainingTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_SlaveByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + /* Set proper RX and TX watermarks to reduce the ISR response times. */ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize - 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0U; + } + /* If there is no txData, mask the transmit data so that no data is loaded from transmit FIFO and output pin + * is tristated. */ + if (handle->txData == NULL) + { + isTxMask = true; + handle->txRemainingByteCount = 0U; + } + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* Fill up the TX data in FIFO */ + if (handle->txData != NULL) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(readRegRemainingTimes - 1U); + } + + /* RX request and FIFO overflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable | (uint32_t)kLPSPI_ReceiveErrorInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + if (handle->txData != NULL) + { + /* TX FIFO underflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransmitErrorInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0U; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) + { + if (handle->txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)handle->txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + if (handle->txRemainingByteCount == 0U) + { + break; + } + } +} + +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + if (handle->state == (uint8_t)kLPSPI_Error) + { + status = kStatus_LPSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, status, handle->userData); + } +} + +/*! + * brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0U; + handle->rxRemainingByteCount = 0U; +} + +/*! + * brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * param instance LPSPI instance index. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + assert(instance < ARRAY_SIZE(s_lpspiBases)); + LPSPI_Type *base = s_lpspiBases[instance]; + uint32_t readData; /* variable to store word read from RX FIFO */ + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount > 0U) + { + while (LPSPI_GetRxFifoCount(base) != 0U) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)handle->rxRemainingByteCount; + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + + if ((handle->txRemainingByteCount > 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if (handle->rxRemainingByteCount == 0U) + { + break; + } + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + if ((handle->rxData == NULL) && (handle->txRemainingByteCount != 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ + if (handle->rxData == NULL) + { + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_FrameCompleteFlag) != 0U) && + (LPSPI_GetTxFifoCount(base) == 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + else + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_FrameCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransmitErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_TEIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransmitErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + /* ERR051588: Clear FIFO after underrun occurs */ + LPSPI_FlushFifo(base, true, false); + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_REIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_ReceiveErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + } +} + +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap) +{ + assert(txData != NULL); + + uint32_t wordToSend = 0U; + + switch (bytesEachWrite) + { + case 1: + wordToSend = *txData; + ++txData; + break; + + case 2: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + + break; + + case 3: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + case 4: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 24U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 24U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + default: + assert(false); + break; + } + return wordToSend; +} + +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + switch (bytesEachRead) + { + case 1: + *rxData = (uint8_t)readData; + ++rxData; + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 3: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 4: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + default: + assert(false); + break; + } +} + +static bool LPSPI_TxFifoReady(LPSPI_Type *base) +{ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while (((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while ((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + return true; +} + +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance); +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance) +{ + assert(s_lpspiHandle[instance] != NULL); + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(instance, (lpspi_master_handle_t *)s_lpspiHandle[instance]); + } + else + { + s_lpspiSlaveIsr(instance, (lpspi_slave_handle_t *)s_lpspiHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(LPSPI14) +void LPSPI14_DriverIRQHandler(void); +void LPSPI14_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI14, 14); +} +#endif + +#if defined(LPSPI16) +void LPSPI16_DriverIRQHandler(void); +void LPSPI16_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI16, 16); +} +#endif diff --git a/drivers/lpflexcomm/lpspi/fsl_lpspi.h b/drivers/lpflexcomm/lpspi/fsl_lpspi.h new file mode 100644 index 000000000..2b016e983 --- /dev/null +++ b/drivers/lpflexcomm/lpspi/fsl_lpspi.h @@ -0,0 +1,1175 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_H_ +#define FSL_LPSPI_H_ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/*! + * @addtogroup lpspi_driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI driver version. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*@}*/ + +#ifndef LPSPI_DUMMY_DATA +/*! @brief LPSPI dummy data if no Tx data.*/ +#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + +/*! @brief Status for the LPSPI driver.*/ +enum +{ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */ + kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */ +}; + +/*! @brief LPSPI status flags in SPIx_SR register.*/ +enum _lpspi_flags +{ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | + LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ +}; + +/*! @brief LPSPI interrupt source.*/ +enum _lpspi_interrupt_enable +{ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_AllInterruptEnable = + (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | + LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ +}; + +/*! @brief LPSPI DMA source.*/ +enum _lpspi_dma_enable +{ + kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ + kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ +}; + +/*! @brief LPSPI master or slave mode configuration.*/ +typedef enum _lpspi_master_slave_mode +{ + kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ +} lpspi_master_slave_mode_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ +typedef enum _lpspi_which_pcs_config +{ + kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ + kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ + kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ + kLPSPI_Pcs3 = 3U /*!< PCS[3] */ +} lpspi_which_pcs_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _lpspi_pcs_polarity_config +{ + kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ +} lpspi_pcs_polarity_config_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ +enum _lpspi_pcs_polarity +{ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief LPSPI clock polarity configuration.*/ +typedef enum _lpspi_clock_polarity +{ + kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ +} lpspi_clock_polarity_t; + +/*! @brief LPSPI clock phase configuration.*/ +typedef enum _lpspi_clock_phase +{ + kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} lpspi_clock_phase_t; + +/*! @brief LPSPI data shifter direction options.*/ +typedef enum _lpspi_shift_direction +{ + kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} lpspi_shift_direction_t; + +/*! @brief LPSPI Host Request select configuration. */ +typedef enum _lpspi_host_request_select +{ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ +} lpspi_host_request_select_t; + +/*! @brief LPSPI Match configuration options. */ +typedef enum _lpspi_match_config +{ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ +} lpspi_match_config_t; + +/*! @brief LPSPI pin (SDO and SDI) configuration. */ +typedef enum _lpspi_pin_config +{ + kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ + kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ + kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ + kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ +} lpspi_pin_config_t; + +/*! @brief LPSPI data output configuration. */ +typedef enum _lpspi_data_out_config +{ + kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ + kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ +} lpspi_data_out_config_t; + +/*! @brief LPSPI cs function configuration. */ +typedef enum _lpspi_pcs_function_config +{ + kLPSPI_PcsAsCs = 0U, /*!< PCS pin select as cs function */ + kLPSPI_PcsAsData = 1U, /*!< PCS pin select as date function */ +} lpspi_pcs_function_config_t; + +/*! @brief LPSPI transfer width configuration. */ +typedef enum _lpspi_transfer_width +{ + kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} lpspi_transfer_width_t; + +/*! @brief LPSPI delay type selection.*/ +typedef enum _lpspi_delay_type +{ + kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ + kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ + kLPSPI_BetweenTransfer /*!< Delay between transfers. */ +} lpspi_delay_type_t; + +#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ +#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ + +#define LPSPI_MASTER_WIDTH_SHIFT (16U) /*!< LPSPI master width shift macro, internal used */ +#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift mask, internal used */ + +/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_master +{ + kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ + kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ + kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ + kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ + + kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */ + kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */ + kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */ + + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ + + kLPSPI_MasterByteSwap = + 1U << 22 /*!< Is master swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ +}; + +#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ +#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_slave +{ + kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ + kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ + kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ + kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ + + kLPSPI_SlaveByteSwap = + 1U << 22 /*!< Is slave swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ +}; + +/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ +enum _lpspi_transfer_state +{ + kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kLPSPI_Busy, /*!< Transfer queue is not finished. */ + kLPSPI_Error /*!< Transfer error. */ +}; + +/*! @brief LPSPI master configuration structure.*/ +typedef struct _lpspi_master_config +{ + uint32_t baudRate; /*!< Baud Rate for LPSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. + It sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the + minimum delay. It sets the boundary value if out of range.*/ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ + bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave + setup time. Refer to device data sheet for specific time length. */ +} lpspi_master_config_t; + +/*! @brief LPSPI slave configuration structure.*/ +typedef struct _lpspi_slave_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_slave_config_t; + +/*! + * @brief Forward declaration of the _lpspi_master_handle typedefs. + */ +typedef struct _lpspi_master_handle lpspi_master_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_handle typedefs. + */ +typedef struct _lpspi_slave_handle lpspi_slave_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Slave completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master/slave transfer structure.*/ +typedef struct _lpspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if + the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the + transfer is used for slave.*/ +} lpspi_transfer_t; + +/*! @brief LPSPI master transfer handle structure used for transactional API. */ +struct _lpspi_master_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */ + volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief LPSPI slave transfer handle structure used for transactional API. */ +struct _lpspi_slave_handle +{ + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the LPSPI master. + * + * @param base LPSPI peripheral address. + * @param masterConfig Pointer to structure lpspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * @code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); + +/*! + * @brief LPSPI slave configuration. + * + * @param base LPSPI peripheral address. + * @param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * @code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * @param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base); + +/*! + * @brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * @param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base); + +/*! + * @brief Get the LPSPI instance from peripheral base address. + * + * @param base LPSPI peripheral base address. + * @return LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! + * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. + * + * @param base LPSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) +{ + if (enable) + { + base->CR |= LPSPI_CR_MEN_MASK; + } + else + { + base->CR &= ~LPSPI_CR_MEN_MASK; + } +} + +/*! + *@} + */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPSPI status flag state. + * @param base LPSPI peripheral address. + * @return The LPSPI status(in SR register). + */ +static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Gets the LPSPI Tx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Tx FIFO size. + */ +static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Rx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Rx FIFO size. + */ +static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Tx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the transmit FIFO. + */ +static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); +} + +/*! + * @brief Gets the LPSPI Rx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the receive FIFO. + */ +static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); +} + +/*! + * @brief Clears the LPSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. + * Example usage: + * @code + * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); + * @endcode + * + * @param base LPSPI peripheral address. + * @param statusFlags The status flag used from type _lpspi_flags. + */ +static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} + */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPSPI interrupts. + * + * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. + * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. + * + * @code + * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the LPSPI interrupts. + * + * @code + * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + *@} + */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER |= mask; +} + +/*! + * @brief Disables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER &= ~mask; +} + +/*! + * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. + * + * This function gets the LPSPI Transmit Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Transmit Data Register address. + */ +static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->TDR); +} + +/*! + * @brief Gets the LPSPI Receive Data Register address for a DMA operation. + * + * This function gets the LPSPI Receive Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Receive Data Register address. + */ +static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->RDR); +} + +/*! + *@} + */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Check the argument for transfer . + * + * @param base LPSPI peripheral address. + * @param transfer the transfer struct to be used. + * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * @return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma); + +/*! + * @brief Configures the LPSPI for either master or slave. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * @param base LPSPI peripheral address. + * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. + */ +static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) +{ + base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); +} + +/*! + * @brief Configures the peripheral chip select used for the transfer. + * + * @param base LPSPI peripheral address. + * @param select LPSPI Peripheral Chip Select (PCS) configuration. + */ +static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select) +{ + base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); +} + +/*! + * @brief Set the PCS signal to continuous or uncontinuous mode. + * + * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command + * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. + * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after + * that the LPSPI will transmit received data back (assuming a 32-bit shift register). + * + * @param base LPSPI peripheral address. + * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. + */ +static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous) +{ + if (IsContinous) + { + base->TCR |= LPSPI_TCR_CONT_MASK; + } + else + { + base->TCR &= ~LPSPI_TCR_CONT_MASK; + } +} + +/*! + * @brief Returns whether the LPSPI module is in master mode. + * + * @param base LPSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool LPSPI_IsMaster(LPSPI_Type *base) +{ + return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); +} + +/*! + * @brief Flushes the LPSPI FIFOs. + * + * @param base LPSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. + */ +static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); +} + +/*! + * @brief Sets the transmit and receive FIFO watermark values. + * + * This function allows the user to set the receive and transmit FIFO watermarks. The function + * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be + * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. + * + * @param base LPSPI peripheral address. + * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + */ +static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) +{ + base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); +} + +/*! + * @brief Configures all LPSPI peripheral chip select polarities simultaneously. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of + * PCS is device-specific. + * @code + * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. + */ +static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) +{ + base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); +} + +/*! + * @brief Configures the frame size. + * + * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal + * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word + * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not + * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. + * + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command + * register + * should only be changed if the LPSPI is idle. + * + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * means the TCR register should be written to when the Tx FIFO is not full. + * + * @param base LPSPI peripheral address. + * @param frameSize The frame size in number of bits. + */ +static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) +{ + base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); +} + +/*! + * @brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param baudRate_Bps The desired baud rate in bits per second. + * @param srcClock_Hz Module source input clock in Hertz. + * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * @return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue); + +/*! + * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param scaler The 8-bit delay value 0x00 to 0xFF (255). + * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * @param base LPSPI peripheral address. + * @param delayTimeInNanoSec The desired delay value in nano-seconds. + * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * @param srcClock_Hz Module source input clock in Hertz. + * @return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz); + +/*! + * @brief Writes data into the transmit data buffer. + * + * This function writes data passed in by the user to the Transmit Data Register (TDR). + * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, + * the user has to manage sending the data one 32-bit word at a time. + * Any writes to the TDR result in an immediate push to the transmit FIFO. + * This function can be used for either master or slave modes. + * + * @param base LPSPI peripheral address. + * @param data The data word to be sent. + */ +static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) +{ + base->TDR = data; +} + +/*! + * @brief Reads data from the data buffer. + * + * This function reads the data from the Receive Data Register (RDR). + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The data read from the data buffer. + */ +static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) +{ + return (base->RDR); +} + +/*! + * @brief Set up the dummy data. + * + * @param base LPSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); + +/*! + *@} + */ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_master_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); + +/*! + * @brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * @param instance LPSPI instance. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(uint32_t instance, lpspi_master_handle_t *handle); + +/*! + * @brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_slave_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * @param instance LPSPI instance index. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle); + +/*! + *@} + */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /*FSL_LPSPI_H_*/ diff --git a/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c b/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c new file mode 100644 index 000000000..bfba766d3 --- /dev/null +++ b/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.c @@ -0,0 +1,1118 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_edma.h" + +/*********************************************************************************************************************** + * Definitions + ***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpspi_edma" +#endif + +/*! + * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_master_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ +} lpspi_master_edma_private_handle_t; + +/*! + * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_slave_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ +} lpspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** + * Prototypes + ***********************************************************************************************************************/ + +/*! + * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! + * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*********************************************************************************************************************** + * Variables + ***********************************************************************************************************************/ +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi edma handles for each instance. */ +static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; +static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; + +/*********************************************************************************************************************** + * Code + ***********************************************************************************************************************/ +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + switch (bytesEachRead) + { + case 1: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 4: + + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Initializes the LPSPI master eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * request source. + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_master_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + lpspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base) +{ + /* Flush FIFO, clear status, disable all the inerrupts and DMA requests. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); +} + +/*! + * brief LPSPI master config transfer parameter using eDMA. + * + * This function is preparing to transfers data using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param configFlags transfer configuration flags. ref _lpspi_transfer_config_flag_for_master. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + */ +status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags) +{ + assert(handle != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Disable module before configuration */ + LPSPI_Enable(base, false); + + LPSPI_PrepareTransferEDMA(base); + + bool isByteSwap = ((configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + bool isPcsContinuous = ((configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U); + uint32_t instance = LPSPI_GetInstance(base); + uint8_t dummyData = g_lpspiDummyData[instance]; + /*Used for byte swap*/ + uint32_t whichPcs = (configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + } + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA without configs. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * This API is only for transfer through DMA without configuration. + * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure, config field is not working. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + * retval kStatus_InvalidArgument The transfer structure is invalid. + */ +status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + /* Variables */ + bool isThereExtraTxBytes = false; + uint8_t bytesLastWrite = 0; + uint32_t instance = LPSPI_GetInstance(base); + /*Used for byte swap*/ + uint32_t addrOffset = 0; + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame > 4U) + { + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + + --handle->writeRegRemainingTimes; + + --handle->readRegRemainingTimes; + handle->isThereExtraRxBytes = true; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, + &s_lpspiMasterEdmaPrivateHandle[instance]); + + /* Configure rx EDMA transfer */ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + + /* Configure tx EDMA transfer */ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + } + + if (handle->isPcsContinuous) + { + handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); + + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcOffset = 0; + + transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); + } + + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0U; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else if (handle->isPcsContinuous) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + LPSPI_EnableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status = kStatus_Fail; + status = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags); + if(kStatus_Success != status) + { + return status; + } + return LPSPI_MasterTransferEDMALite(base,handle,transfer); +} + +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + + lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaPrivateHandle->handle->bytesLastRead; + bool isByteSwap = lpspiEdmaPrivateHandle->handle->isByteSwap; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), + readData, bytesLastRead, isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the master eDMA transfer remaining bytes. + * + * This function gets the master eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the EDMA transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief Initializes the LPSPI slave eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request + * source. + * + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle . + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + lpspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +/*! + * brief LPSPI slave transfers data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + /* Disable module before configuration. */ + LPSPI_Enable(base, false); + /* Check arguements, also dma transfer can not support 3 bytes */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + LPSPI_PrepareTransferEDMA(base); + + /* Variables */ + bool isThereExtraTxBytes = false; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint8_t bytesLastWrite = 0; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t mask = (uint32_t)kLPSPI_RxDmaEnable; + + /* Used for byte swap */ + uint32_t addrOffset = 0; + uint32_t instance = LPSPI_GetInstance(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /* Because DMA is fast enough, set the RX and TX watermarks to 0. */ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer, mask the transmit data if the tx data is null, for rx the receive data should not be masked at + any time since we use rx dma transfer finish cllback to indicate transfer finish. */ + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) | + LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + --handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = true; + --handle->readRegRemainingTimes; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, + &s_lpspiSlaveEdmaPrivateHandle[instance]); + + /*Rx*/ + if (handle->readRegRemainingTimes > 0U) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + } + + /*Tx*/ + if (handle->txData != NULL) + { + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + if (isThereExtraTxBytes) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + mask |= (uint32_t)kLPSPI_TxDmaEnable; + } + + LPSPI_EnableDMA(base, mask); + + return kStatus_Success; +} + +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + + lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaPrivateHandle->handle->bytesLastRead; + bool isByteSwap = lpspiEdmaPrivateHandle->handle->isByteSwap; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), + readData, bytesLastRead, isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the slave eDMA transfer remaining bytes. + * + * This function gets the slave eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the eDMA transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} diff --git a/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.h b/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.h new file mode 100644 index 000000000..d5ed08989 --- /dev/null +++ b/drivers/lpflexcomm/lpspi/fsl_lpspi_edma.h @@ -0,0 +1,339 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPSPI_EDMA_H_ +#define FSL_LPSPI_EDMA_H_ + +#include "fsl_lpspi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI EDMA driver version. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. + */ +typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. + */ +typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ +struct _lpspi_master_edma_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ + volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + + uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPUART mode */ + status = LP_FLEXCOMM_Init(LPUART_GetInstance(base), LP_FLEXCOMM_PERIPH_LPUART); + if (kStatus_Success != status) + { + return status; + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout configuration. */ + base->REIR = (uint32_t)config->timeoutConfig.rxExtendedTimeoutValue; + base->TEIR = (uint32_t)config->timeoutConfig.txExtendedTimeoutValue; + base->TOCR |= (uint32_t)config->timeoutConfig.rxCounter0.enableCounter | + ((uint32_t)config->timeoutConfig.rxCounter1.enableCounter << 1U) | + ((uint32_t)config->timeoutConfig.txCounter0.enableCounter << 2U) | + ((uint32_t)config->timeoutConfig.txCounter1.enableCounter << 3U); + base->TIMEOUT[0] = ((uint32_t)config->timeoutConfig.rxCounter0.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.rxCounter0.timeoutValue; + base->TIMEOUT[1] = ((uint32_t)config->timeoutConfig.rxCounter1.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.rxCounter1.timeoutValue; + base->TIMEOUT[2] = ((uint32_t)config->timeoutConfig.txCounter0.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.txCounter0.timeoutValue; + base->TIMEOUT[3] = ((uint32_t)config->timeoutConfig.txCounter1.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.txCounter1.timeoutValue; +#endif + + /* Siglewire configuration. */ +#if defined(FSL_FEATURE_LPUART_HAS_HDCR) && FSL_FEATURE_LPUART_HAS_HDCR + base->HDCR = (uint32_t)config->rtsDelay << 8U; + if (config->enableSingleWire) + { + base->HDCR |= 0xFUL; + } +#endif + } + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPUART_GetInstance(base)); +#endif +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } + + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem control interrupt enables */ + base->MCR |= (mask & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout interrupt enables. */ + base->TOSR |= ((mask >> 2U) & 0xF00UL); +#endif + /* Check int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Check int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem control interrupts. */ + base->MCR &= ~(mask & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout interrupt enables. */ + base->TOSR &= ~((mask >> 2U) & 0xF00UL); +#endif + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + /* Check int enable bits in base->CTRL */ + uint32_t temp = (uint32_t)(base->CTRL & 0xFF0C000UL); + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Check modem control interrupts. */ + temp |= (base->MCR & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Check timeout control interrupts. */ + temp |= ((base->TOCR & 0xF00UL) << 2U); +#endif + + /* Check int enable bits in base->BAUD */ + temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + temp = + (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) | + (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + + temp = (base->STAT & 0xC1FFC000UL); +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + temp |= ((base->MSR & 0xFUL) << 2U); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + temp |= ((base->TOSR & 0xF00UL) << 2U); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + /* Only keeps the status bits */ + temp &= (uint32_t)kLPUART_AllFlags; + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; + + /* Only deal with the clearable flags */ + mask &= (uint32_t)kLPUART_AllClearFlags; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem status */ + base->MSR = ((mask >> 2U) & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout status */ + base->TOSR = ((mask >> 2U) & 0xF00UL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Status bits in FIFO register */ + if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U) + { + /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case + they are written 1 accidentally. */ + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)( + ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; + } +#endif + /* Status bits in STAT register */ + /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit + * that is to be W1C */ + temp = (base->STAT & 0x3E000000UL) | mask; + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + status = kStatus_LPUART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + /* Get instance from peripheral base address. */ + uint32_t instance = LPUART_GetInstance(base); + + lpuart_to_lpflexcomm_t handler; + handler.lpuart_handler = LPUART_TransferHandleIRQ; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(LPUART_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_lpuartIRQ[instance]); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable the interrupt to accept the data when user need the ring buffer. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->txData); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable transmitter interrupt. */ + base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK; + EnableGlobalIRQ(irqMask); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK); + EnableGlobalIRQ(irqMask); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->rxData); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + uint32_t irqMask; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable LPUART RX IRQ, protect ring buffer. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Re-enable LPUART RX IRQ. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Enable RX interrupt. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Disable RX interrupt. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param instance LPUART instance. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) +{ + assert(NULL != irqHandle); + assert(instance < ARRAY_SIZE(s_lpuartBases)); + LPUART_Type *base = s_lpuartBases[instance]; + uint8_t count; + uint8_t tempCount; + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + uint32_t irqMask; + lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, (uint16_t *)handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount * 2u]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, invoke rx idle callback.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK); + + /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/ + if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + /* Invoke callback if callback is not NULL and rxDataSize is not 0. */ + else if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + else + { + /* Avoid MISRA 15.7 */ + } + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, (uint16_t *)handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount * 2]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } +#else + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK); + EnableGlobalIRQ(irqMask); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, (const uint16_t *)handle->txData, tempCount); + handle->txData = &handle->txData[tempCount * 2u]; + } + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable TX register empty interrupt and enable transmission completion interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + } + } + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + irqMask = DisableGlobalIRQ(); + /* Disable transmission complete interrupt. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle) +{ + /* To be implemented by User. */ +} diff --git a/drivers/lpflexcomm/lpuart/fsl_lpuart.h b/drivers/lpflexcomm/lpuart/fsl_lpuart.h new file mode 100644 index 000000000..072c22aa1 --- /dev/null +++ b/drivers/lpflexcomm/lpuart/fsl_lpuart.h @@ -0,0 +1,1175 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK, /*!< Change of state on CTS_B pin. bit 0 */ + kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK, /*!< Change of state on DSR_B pin. bit 1 */ + kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK, /*!< Change of state on RIN_B pin. bit 2 */ + kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK, /*!< Change of state on DCD_B pin. bit 3 */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ +#endif + kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch2InterruptEnable = + (LPUART_CTRL_MA2IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ + kLPUART_DataMatch1InterruptEnable = + (LPUART_CTRL_MA1IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ +#endif + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. bit 21 */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. bit 23 */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */ + kLPUART_AllInterruptEnable = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeInterruptEnable | kLPUART_DsrStateChangeInterruptEnable | + kLPUART_RinStateChangeInterruptEnable | kLPUART_DcdStateChangeInterruptEnable | +#endif + kLPUART_RxActiveEdgeInterruptEnable | kLPUART_IdleLineInterruptEnable | kLPUART_RxDataRegFullInterruptEnable | + kLPUART_TransmissionCompleteInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable | + kLPUART_ParityErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable | kLPUART_NoiseErrorInterruptEnable | + kLPUART_RxOverrunInterruptEnable +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_RxFifoUnderflowInterruptEnable | kLPUART_TxFifoOverflowInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2InterruptEnable | kLPUART_DataMatch1InterruptEnable +#endif + , +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + kLPUART_RxFifoEmptyFlag = + (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ + kLPUART_TxFifoEmptyFlag = + (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */ +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag = LPUART_MCR_CTS_MASK << 2U, /*!< Change of state on CTS_B pin. bit 2 */ + kLPUART_DsrStateChangeFlag = LPUART_MCR_DSR_MASK << 2U, /*!< Change of state on DSR_B pin. bit 3 */ + kLPUART_RinStateChangeFlag = LPUART_MCR_RIN_MASK << 2U, /*!< Change of state on RIN_B pin. bit 4 */ + kLPUART_DcdStateChangeFlag = LPUART_MCR_DCD_MASK << 2U, /*!< Change of state on DCD_B pin. bit 5 */ +#endif + kLPUART_RxCounter0TimeoutFlag = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutFlag = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutFlag = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutFlag = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch2Flag = + LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ + kLPUART_DataMatch1Flag = + LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ +#endif + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any + of these samples differ, noise flag sets. bit 18 */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before + data is read from receive register. bit 19 */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */ + kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the + receive data buffer is full. bit 21 */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ + kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets + when active edge detected. bit 30 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ +#endif + + kLPUART_AllClearFlags = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag | kLPUART_DsrStateChangeFlag | kLPUART_RinStateChangeFlag | + kLPUART_DcdStateChangeFlag | +#endif + kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag | kLPUART_RxOverrunFlag | + kLPUART_IdleLineFlag | kLPUART_RxActiveEdgeFlag +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2Flag | kLPUART_DataMatch1Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , + + kLPUART_AllFlags = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag | kLPUART_DsrStateChangeFlag | kLPUART_RinStateChangeFlag | + kLPUART_DcdStateChangeFlag | +#endif + kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag | kLPUART_RxOverrunFlag | + kLPUART_IdleLineFlag | kLPUART_RxDataRegFullFlag | kLPUART_TransmissionCompleteFlag | + kLPUART_TxDataRegEmptyFlag | kLPUART_RxActiveFlag | kLPUART_RxActiveEdgeFlag +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2Flag | kLPUART_DataMatch1Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , +}; + +/*! @brief LPUART timeout condition. + * This structure defines the conditions when the counter timeout occur. + */ +typedef enum _lpuart_timeout_condition +{ + kLPUART_TimeoutAfterCharacters = + 0U, /*!< Timeout occurs when the number of characters specified by timeoutValue are received. */ + kLPUART_TimeoutAfterIdle = 1U, /*!< Timeout occurs when rx/tx remains idle for timeoutValue of bit clocks after idle + condition is detected. */ + kLPUART_TimeoutAfterNext = 2U, /*!< Timeout occurs when rx/tx remains idle for timeoutValue of bit clocks after next + character is received/transmitted. */ + kLPUART_TimeoutAfterIdleBeforeExtended = 3U, /*!< Timeout occurs when tx/rx is idle for larger than timeoutValue of + bit clocks and smaller than tx/rx extended timeout value. */ +} lpuart_timeout_condition_t; + +/*! @brief LPUART timeout counter configuration structure. */ +typedef struct _lpuart_timeout_counter_config +{ + bool enableCounter; /*!< Eneble the timeout counter. */ + lpuart_timeout_condition_t timeoutCondition; /*!< Timeout condition. */ + uint16_t timeoutValue; /*!< Timeout value. */ +} lpuart_timeout_counter_config_t; + +/*! @brief LPUART timeout configuration structure. */ +typedef struct _lpuart_timeout_config +{ + uint16_t rxExtendedTimeoutValue; /*!< The number of bits since the last stop bit that is required for an + idle condition to be detected. Enable this will disable rxIdleType and rxIdleConfig. Set to 0 to disable. */ + uint16_t txExtendedTimeoutValue; /*!< The transmitter idle time in number of bits (baud rate) whenever an + idle character is queued through the transmit FIFO. */ + lpuart_timeout_counter_config_t rxCounter0; /*!< Rx counter 0 configuration. */ + lpuart_timeout_counter_config_t rxCounter1; /*!< Rx counter 1 configuration. */ + lpuart_timeout_counter_config_t txCounter0; /*!< Tx counter 0 configuration. */ + lpuart_timeout_counter_config_t txCounter1; /*!< Tx counter 1 configuration. */ +} lpuart_timeout_config_t; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + lpuart_timeout_config_t timeoutConfig; /*!< Timeout configuration. */ + bool enableSingleWire; /*!< Use TXD pin as the source for the receiver. When enabled the TXD pin should be + configured as open drain. */ + uint8_t rtsDelay; /*!< Delay the negation of RTS by the configured number of bit clocks. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_irq_handler_t)(uint32_t instance, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART IRQ number. */ +extern const IRQn_Type s_lpuartIRQ[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle,bool enable) +{ + handle->is16bitData = enable; +} + +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); +/* @} */ + +/*! + * @name Module configuration + * @{ + */ +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); +} +#endif +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); +/* @} */ + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @name DMA Configuration + * @{ + */ +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Gets the rx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +} +#endif + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param instance LPUART instance. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_H_ */ diff --git a/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c b/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c new file mode 100644 index 000000000..653496565 --- /dev/null +++ b/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.c @@ -0,0 +1,510 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpuart_edma" +#endif + +/*base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + lpuart_to_lpflexcomm_edma_t handler; + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + handler.lpuart_handler = LPUART_TransferEdmaHandleIRQ; + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART); + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param instance LPUART peripheral index. + * param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(uint32_t instance, void *lpuartEdmaHandle) +{ + assert(lpuartEdmaHandle != NULL); + assert(instance < ARRAY_SIZE(s_lpuartBases)); + LPUART_Type *base = s_lpuartBases[instance]; + + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_edma_handle_t *handle = (lpuart_edma_handle_t *)lpuartEdmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.h b/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.h new file mode 100644 index 000000000..2d25416da --- /dev/null +++ b/drivers/lpflexcomm/lpuart/fsl_lpuart_edma.h @@ -0,0 +1,189 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPUART_EDMA_H_ +#define FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART EDMA driver version. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param instance LPUART peripheral index. + * @param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(uint32_t instance, void *lpuartEdmaHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_EDMA_H_ */ diff --git a/drivers/lptmr/fsl_lptmr.h b/drivers/lptmr/fsl_lptmr.h index dcff41f34..ba94fe177 100644 --- a/drivers/lptmr/fsl_lptmr.h +++ b/drivers/lptmr/fsl_lptmr.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPTMR_H_ -#define _FSL_LPTMR_H_ +#ifndef FSL_LPTMR_H_ +#define FSL_LPTMR_H_ #include "fsl_common.h" @@ -371,4 +371,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base) /*! @}*/ -#endif /* _FSL_LPTMR_H_ */ +#endif /* FSL_LPTMR_H_ */ diff --git a/drivers/mcx_cmc/fsl_cmc.c b/drivers/mcx_cmc/fsl_cmc.c new file mode 100644 index 000000000..f2b7e064a --- /dev/null +++ b/drivers/mcx_cmc/fsl_cmc.c @@ -0,0 +1,315 @@ +/* + * Copyright 2022 ~ 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_cmc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_cmc" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +#define CMC_SRAMDIS_RESERVED_MASK \ + (~(kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | kCMC_RAMD1 | \ + kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | \ + kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI)) + +#define CMC_SRAMRET_RESERVED_MASK (CMC_SRAMDIS_RESERVED_MASK) +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t g_savedPrimask; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * param base CMC peripheral base address. + * param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode) +{ + uint32_t reg; + + reg = base->CKCTRL; + reg &= ~CMC_CKCTRL_CKMODE_MASK; + reg |= CMC_CKCTRL_CKMODE((mode)); + base->CKCTRL = reg; +} + +/*! + * brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before setting the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * param base CMC peripheral base address. + * param allowedModes Bitmaps of the allowed power modes. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes) +{ + uint32_t reg; + + reg = base->PMPROT; + reg &= ~0xFUL; + reg |= allowedModes; + + base->PMPROT = reg; +} + +/*! + * brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * param base CMC peripheral base address. + * param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = base->RPC; + + if (config->lowpowerFilterEnable) + { + reg |= CMC_RPC_LPFEN_MASK; + } + else + { + reg &= ~CMC_RPC_LPFEN_MASK; + } + if (config->resetFilterEnable) + { + reg |= (CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG(config->resetFilterWidth)); + } + else + { + reg &= ~(CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG_MASK); + } + base->RPC = reg; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * brief Power off the selected system SRAM always. + * + * This function powers off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be powered off all modes. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMDIS[0]; + + reg &= ~(CMC_SRAMDIS_DIS_MASK | CMC_SRAMDIS_RESERVED_MASK); + reg |= CMC_SRAMDIS_DIS(mask); + base->SRAMDIS[0] = reg; +} + +/*! + * brief Power off the selected system SRAm during low power mode only. + * + * This function powers off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be power off during low power mode only. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMRET[0]; + + reg &= ~(CMC_SRAMRET_RET_MASK | CMC_SRAMRET_RESERVED_MASK); + reg |= CMC_SRAMRET_RET(mask); + base->SRAMRET[0] = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param doze true: Flash is disabled while core is sleeping + * false: No effect. + * param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)); + base->FLASHCR = reg; +} +#else +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function config the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param wake + * true - Flash will exit low power state during the flash memory accesses. + * false - No effect. + * param doze + * true - Flash is disabled while core is sleeping + * false - No effect. + * param disable + * true - Flash memory is placed in low power state. + * false - No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)) | + (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U)); + base->FLASHCR = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ + +/*! + * brief Prepares to enter stop modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after waking up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * param base CMC peripheral base address. + * param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + /* Note: unlock the CKCTRL register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetGlobalPowerMode(base, lowPowerMode); + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->GPMCTRL; + /* Set the core into DeepSleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +} + +/*! + * brief Configs the entry into different low power modes for each of the power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * param base CMC peripheral base address. + * param base config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config) +{ + assert(config != NULL); + +#if (CMC_PMCTRL_COUNT > 1U) + /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */ + assert(config->wake_domain <= config->main_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode) + { + /* In This case the power domain doesn't need to be placed in low power state. */ + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, config->clock_mode); + + CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->CKCTRL; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + } + else + { + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetMAINPowerMode(base, config->main_domain); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, config->wake_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before execute WFI instruction read back the last register to + * ensure all registers writes have completed. */ +#if (CMC_PMCTRL_COUNT > 1U) + if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain)) + { +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +#if (CMC_PMCTRL_COUNT > 1U) + } +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + } +} diff --git a/drivers/mcx_cmc/fsl_cmc.h b/drivers/mcx_cmc/fsl_cmc.h new file mode 100644 index 000000000..979c5dfa0 --- /dev/null +++ b/drivers/mcx_cmc/fsl_cmc.h @@ -0,0 +1,911 @@ +/* + * Copyright 2022 ~ 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CMC_H_ +#define FSL_CMC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_cmc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief CMC driver version 2.2.0. */ +#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/* @} */ + +/*! + * @brief CMC power mode Protection enumeration. + */ +enum _cmc_power_mode_protection +{ + kCMC_AllowDeepSleepMode = 0x1UL, /*!< Allow Deep Sleep mode. */ + kCMC_AllowPowerDownMode = 0x2UL, /*!< Allow Power Down mode. */ + kCMC_AllowDeepPowerDownMode = 0x8UL, /*!< Allow Deep Power Down mode. */ + kCMC_AllowAllLowPowerModes = 0xFUL, /*!< Allow Deep Sleep, Power Down, Deep Power Down modes. */ +}; + +/*! + * @brief Wake up sources from the previous low power mode entry. + * + * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family. + */ +enum _cmc_wakeup_sources +{ + kCMC_WakeupFromResetInterruptOrPowerDown = + CMC_CKSTAT_WAKEUP(1U << 0U), /*!< Wakeup source is reset interrupt, or wake up from Deep Power Down. */ + kCMC_WakeupFromDebugReuqest = CMC_CKSTAT_WAKEUP(1U << 1U), /*!< Wakeup source is debug request. */ + kCMC_WakeupFromInterrupt = CMC_CKSTAT_WAKEUP(1U << 2U), /*!< Wakeup source is interrupt. */ + kCMC_WakeupFromDMAWakeup = CMC_CKSTAT_WAKEUP(1U << 3U), /*!< Wakeup source is DMA Wakeup. */ + kCMC_WakeupFromWUURequest = CMC_CKSTAT_WAKEUP(1U << 4U), /*!< Wakeup source is WUU request. */ + kCMC_WakeupFromUsbFs = CMC_CKSTAT_WAKEUP(1U << 5U), /*!< Wakeup source is USBFS(USB0). */ + kCMC_WakeupFromITRC = CMC_CKSTAT_WAKEUP(1U << 6U), /*!< Wakeup source is ITRC. */ + kCMC_WakeupFromCpu1 = CMC_CKSTAT_WAKEUP(1U << 7U), /*!< Wakeup source is CPU1. */ +}; + +/*! + * @brief System Reset Interrupt enable enumeration. + */ +enum _cmc_system_reset_interrupt_enable +{ + kCMC_PinResetInterruptEnable = CMC_SRIE_PIN_MASK, /*!< Pin Reset interrupt enable. */ + kCMC_DAPResetInterruptEnable = CMC_SRIE_DAP_MASK, /*!< DAP Reset interrupt enable. */ + kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable = CMC_SRIE_LPACK_MASK, /*!< Low Power Acknowledge Timeout + Reset interrupt enable. */ + kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset + interrupt enable. */ + kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ + kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ +#if defined(CMC_SRIE_CPU1_MASK) + kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */ +#endif /* CMC_SRIE_CPU1_MASK */ +#if defined(CMC_SRIE_VBAT_MASK) + kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */ +#endif /* CMC_SRIE_VBAT_MASK */ +#if defined(CMC_SRIE_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset + interrupt enable. */ +#endif /* CMC_SRIE_WWDT1_MASK */ + kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */ +#if defined(CMC_SRIE_CDOG1_MASK) + kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */ +#endif /* CMC_SRIE_CDOG1_MASK */ +}; + +/*! + * @brief CMC System Reset Interrupt Status flag. + */ +enum _cmc_system_reset_interrupt_flag +{ + kCMC_PinResetInterruptFlag = CMC_SRIF_PIN_MASK, /*!< Pin Reset interrupt flag. */ + kCMC_DAPResetInterruptFlag = CMC_SRIF_DAP_MASK, /*!< DAP Reset interrupt flag. */ + kCMC_LowPowerAcknowledgeTimeoutResetFlag = CMC_SRIF_LPACK_MASK, /*!< Low Power Acknowledge + Timeout Reset interrupt flag. */ + kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */ + kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */ + kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */ +#if defined(CMC_SRIF_CPU1_MASK) + kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */ +#endif /* CMC_SRIF_CPU1_MASK */ +#if defined(CMC_SRIF_VBAT_MASK) + kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */ +#endif /* CMC_SRIF_VBAT_MASK */ +#if defined(CMC_SRIF_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */ +#endif /* CMC_SRIF_WWDT1_MASK */ + kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */ +#if defined(CMC_SRIF_CDOG1_MASK) + kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */ +#endif /* CMC_SRIF_CDOG1_MASK */ +}; + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @brief CMC System SRAM arrays low power mode enable enumeration. + */ +enum _cmc_system_sram_arrays +{ + kCMC_RAMX0 = 1UL << 0UL, /*!< Used to control RAMX0. */ + kCMC_RAMX1 = 1UL << 1UL, /*!< Used to control RAMX1. */ + kCMC_RAMX2 = 1UL << 2UL, /*!< Used to control RAMX2. */ + kCMC_RAMB = 1UL << 3UL, /*!< Used to control RAMB. */ + kCMC_RAMC0 = 1UL << 4UL, /*!< Used to control RAMC0. */ + kCMC_RAMC1 = 1UL << 5UL, /*!< Used to control RAMC1. */ + kCMC_RAMD0 = 1UL << 6UL, /*!< Used to control RAMD0. */ + kCMC_RAMD1 = 1UL << 7UL, /*!< Used to control RAMD1. */ + kCMC_RAME0 = 1UL << 8UL, /*!< Used to control RAME0. */ + kCMC_RAME1 = 1UL << 9UL, /*!< Used to control RAME1. */ + kCMC_RAMF0 = 1UL << 10UL, /*!< Used to control RAMF0. */ + kCMC_RAMF1 = 1UL << 11UL, /*!< Used to control RAMF1. */ + kCMC_RAMG0_RAMG1 = 1UL << 12UL, /*!< Used to control RAMG0 and RAMG1. */ + kCMC_RAMG2_RAMG3 = 1UL << 13UL, /*!< Used to control RAMG2 and RAMG3. */ + kCMC_RAMH0_RAMH1 = 1UL << 14UL, /*!< Used to control RAMH0 and RAMH1. */ + kCMC_LPCAC = 1UL << 24UL, /*!< Used to control LPCAC. */ + kCMC_DMA0_DMA1_PKC = 1UL << 25UL, /*!< Used to control DMA0, DMA1 and PKC. */ + kCMC_USB0 = 1UL << 26UL, /*!< Used to control USB0. */ + kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */ + kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */ + kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */ +}; +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @brief System reset sources enumeration. + */ +enum _cmc_system_reset_sources +{ + kCMC_WakeUpReset = CMC_SRS_WAKEUP_MASK, /*!< The reset caused by a wakeup from Power Down or + Deep Power Down mode. */ + kCMC_PORReset = CMC_SRS_POR_MASK, /*!< The reset caused by power on reset detection logic. */ + kCMC_VDReset = CMC_SRS_VD_MASK, /*!< The reset caused by an LVD or HVD. */ + kCMC_WarmReset = CMC_SRS_WARM_MASK, /*!< The last reset source is a warm reset source. */ + kCMC_FatalReset = CMC_SRS_FATAL_MASK, /*!< The last reset source is a fatal reset source. */ + kCMC_PinReset = CMC_SRS_PIN_MASK, /*!< The reset caused by the RESET_b pin. */ + kCMC_DAPReset = CMC_SRS_DAP_MASK, /*!< The reset caused by a reset request from the Debug Access port. */ + kCMC_ResetTimeout = CMC_SRS_RSTACK_MASK, /*!< The reset caused by a timeout or other error condition in the system + reset generation. */ + kCMC_LowPowerAcknowledgeTimeoutReset = CMC_SRS_LPACK_MASK, /*!< The reset caused by a timeout in + low power mode entry logic. */ + kCMC_SCGReset = CMC_SRS_SCG_MASK, /*!< The reset caused by a loss of clock or loss of lock event in the SCG. */ + kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */ + kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */ + kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */ +#if defined(CMC_SRS_CPU1_MASK) + kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */ +#endif /* CMC_SRS_CPU1_MASK */ +#if defined(CMC_SRS_VBAT_MASK) + kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */ +#endif /* CMC_SRS_VBAT_MASK */ +#if defined(CMC_SRS_WWDT1_MASK) + kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */ +#endif /* CMC_SRS_WWDT1_MASK */ + kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */ +#if defined(CMC_SRS_CDOG1_MASK) + kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */ +#endif /* CMC_SRS_CDOG1_MASK */ + kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ +#if defined(CMC_SRS_SECVIO_MASK) + kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */ +#endif /* CMC_SRS_SECVIO_MASK */ +#if defined(CMC_SRS_TAMPER_MASK) + kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */ +#endif /* CMC_SRS_TAMPER_MASK */ +}; + +/*! + * @brief Indicate the core clock was gated. + */ +typedef enum _cmc_core_clock_gate_status +{ + kCMC_CoreClockNotGated = 0U, /*!< Core clock not gated. */ + kCMC_CoreClockGated = 1U /*!< Core clock was gated due to low power mode entry. */ +} cmc_core_clock_gate_status_t; + +/*! + * @brief CMC clock mode enumeration. + */ +typedef enum _cmc_clock_mode +{ + kCMC_GateNoneClock = 0x00U, /*!< No clock gating. */ + kCMC_GateCoreClock = 0x01U, /*!< Gate Core clock. */ + kCMC_GateCorePlatformClock = 0x03U, /*!< Gate Core clock and platform clock. */ + kCMC_GateAllSystemClocks = 0x07U, /*!< Gate all System clocks, without getting core entering into low power mode. */ + kCMC_GateAllSystemClocksEnterLowPowerMode = 0x0FU /*!< Gate all System clocks, with core + entering into low power mode. */ +} cmc_clock_mode_t; + +/*! + * @brief CMC power mode enumeration. + */ +typedef enum _cmc_low_power_mode +{ + kCMC_ActiveOrSleepMode = 0x0U, /*!< Select Active/Sleep mode. */ + kCMC_DeepSleepMode = 0x1U, /*!< Select Deep Sleep mode when a core executes WFI or WFE instruction. */ + kCMC_PowerDownMode = 0x3U, /*!< Select Power Down mode when a core executes WFI or WFE instruction. */ + kCMC_DeepPowerDown = 0xFU, /*!< Select Deep Power Down mode when a core executes WFI or WFE instruction. */ +} cmc_low_power_mode_t; + +/*! + * @brief CMC reset pin configuration. + */ +typedef struct _cmc_reset_pin_config +{ + bool lowpowerFilterEnable; /*!< Low Power Filter enable. */ + bool resetFilterEnable; /*!< Reset Filter enable. */ + uint8_t resetFilterWidth; /*!< Width of the Reset Filter. */ +} cmc_reset_pin_config_t; + +/*! + * @brief power mode configuration for each power domain. + */ +typedef struct _cmc_power_domain_config +{ + cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */ + cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */ +#if (CMC_PMCTRL_COUNT > 1U) + cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */ +#endif /* (CMC_PMCTRL_COUNT > 1U) */ +} cmc_power_domain_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CLOCK mode configuration. + * @{ + */ + +/*! + * @brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * @param base CMC peripheral base address. + * @param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode); + +/*! + * @brief Locks the clock mode setting. + * + * After invoking this function, any clock mode setting will be blocked. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockClockModeSetting(CMC_Type *base) +{ + base->CKCTRL |= CMC_CKCTRL_LOCK_MASK; +} + +/* @} */ + +/*! + * @name Gets/Clears the Clock Mode, the wake up source, the Reset source. + * @{ + */ + +/*! + * @brief Gets the core clock gated status. + * + * This function get the status to indicate whether the core clock is gated. + * The core clock gated status can be cleared by software. + * + * @param base CMC peripheral base address. + * @return The status to indicate whether the core clock is gated. + */ +static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base) +{ + return (cmc_core_clock_gate_status_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_VALID_MASK) >> CMC_CKSTAT_VALID_SHIFT); +} + +/*! + * @brief Clears the core clock gated status. + * + * This function clear clock status flag by software. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base) +{ + base->CKSTAT |= CMC_CKSTAT_VALID_MASK; +} + +/*! + * @brief Gets the Wakeup Source. + * + * This function gets the Wakeup sources from the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Wakeup sources from the previous low power mode entry. See @ref _cmc_wakeup_sources for details. + */ +static inline uint8_t CMC_GetWakeupSource(CMC_Type *base) +{ + return ((uint8_t)((base->CKSTAT & CMC_CKSTAT_WAKEUP_MASK) >> CMC_CKSTAT_WAKEUP_SHIFT)); +} + +/*! + * @brief Gets the Clock mode. + * + * This function gets the clock mode of the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Low Power status. + */ +static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base) +{ + return (cmc_clock_mode_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_CKMODE_MASK) >> CMC_CKSTAT_CKMODE_SHIFT); +} + +/*! + * @brief Gets the System reset status. + * + * This function returns the system reset status. Those status + * updates on every MAIN Warm Reset to indicate the type/source + * of the most recent reset. + * + * @param base CMC peripheral base address. + * @return The most recent system reset status. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base) +{ + return base->SRS; +} + +/*! + * @brief Gets the sticky system reset status since the last WAKE Cold Reset. + * + * This function gets all source of system reset that have generated a + * system reset since the last WAKE Cold Reset, and that have not been + * cleared by software. + * + * @param base CMC peripheral base address. + * @return System reset status that have not been cleared by software. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base) +{ + return base->SSRS; +} + +/*! + * @brief Clears the sticky system reset status flags. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the sticky system reset status to be cleared. + */ +static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask) +{ + base->SSRS = mask; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) +/*! + * @brief Gets the number of reset sequences completed since the last Cold Reset. + * + * @param base CMC peripheral base address. + * @return The number of reset sequences. + */ +static inline uint8_t CMC_GetResetCount(CMC_Type *base) +{ + return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */ + +/* @} */ + +/*! + * @name Power mode configuration. + * @{ + */ + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before set the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * @param base CMC peripheral base address. + * @param allowedModes Bitmaps of the allowed power modes. See @ref _cmc_power_mode_protection for details. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes); + +/*! + * @brief Locks the power mode protection. + * + * This function locks the power mode protection. After invoking this function, + * any power mode protection setting will be ignored. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base) +{ + base->PMPROT |= CMC_PMPROT_LOCK_MASK; +} + +/*! + * @brief Config the same lowPower mode for all power domain. + * + * This function configures the same low power mode for MAIN power domian and WAKE power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + */ +static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Configures entry into low power mode for the MAIN Power domain. + * + * This function configures the low power mode for the MAIN power domian, + * when the core executes WFI/WFE instruction. The available lowPower modes + * are defined in the @ref cmc_low_power_mode_t. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[0] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the MAIN Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of MAIN Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK); +} + +#if (CMC_PMCTRL_COUNT > 1U) +/*! + * @brief Configure entry into low power mode for the WAKE Power domain. + * + * This function configures the low power mode for the WAKE power domian, + * when the core executes WFI/WFE instruction. The available lowPower mode + * are defined in the @ref cmc_low_power_mode_t. + * + * @note The lowPower Mode for the WAKE domain must not be configured to a + * lower power mode than any other power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetWAKEPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[1] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the WAKE Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of WAKE Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK); +} +#endif /* CMC_PMCTRL_COUNT > 1U */ + +/* @} */ + +/*! + * @name Reset Pin configuration. + * @{ + */ + +/*! + * @brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * @param base CMC peripheral base address. + * @param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config); + +/* @} */ + +/*! + * @name System Reset Interrupts. + * @{ + */ + +/*! + * @brief Enable system reset interrupts. + * + * This function enables the system reset interrupts. The assertion of + * non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock + * while an enabled interrupt is generated. Then Software can perform a graceful + * shutdown or abort the non-fatal warm reset provided the pending reset source is cleared + * by resetting the reset source and then clearing the pending flag. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + * + */ +static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE |= mask; +} + +/*! + * @brief Disable system reset interrupts. + * + * This function disables the system reset interrupts. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + */ +static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE &= (uint32_t)(~mask); +} + +/*! + * @brief Gets System Reset interrupt flags. + * + * This function returns the System reset interrupt flags. + * + * @param base CMC peripheral base address. + * @return System reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + */ +static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base) +{ + return base->SRIF; +} + +/*! + * @brief Clears System Reset interrupt flags. + * + * This function clears system reset interrupt flags. The pending reset source + * can be cleared by resetting the source of the reset and then clearing the pending + * flags. + * + * @param base CMC peripheral base address. + * @param mask System Reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + * + */ +static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask) +{ + base->SRIF = mask; +} + +/* @} */ + +/*! + * @name Non Maskable Pin interrupt. + * @{ + */ + +/*! + * @brief Enable/Disable Non maskable Pin interrupt. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Non maskable pin interrupt. + * true - enable Non-maskable pin interrupt. + * false - disable Non-maskable pin interupt. + */ +static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable) +{ + if (enable) + { + base->CORECTL |= CMC_CORECTL_NPIE_MASK; + } + else + { + base->CORECTL &= ~CMC_CORECTL_NPIE_MASK; + } +} + +/* @} */ + +/*! + * @name Boot Configuration. + * @{ + */ + +/*! + * @brief Gets the logic state of the ISPMODE_n pin. + * + * This function returns the logic state of the ISPMODE_n pin + * on the last negation of RESET_b pin. + * + * @param base CMC peripheral base address. + * @return The logic state of the ISPMODE_n pin on the last negation of RESET_b pin. + */ +static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base) +{ + return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT); +} + +/*! + * @brief Clears ISPMODE_n pin state. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base) +{ + base->MR[0] = CMC_MR_ISPMODE_n_MASK; +} + +/*! + * @brief Set the logic state of the BOOT_CONFIGn pin. + * + * This function force the logic state of the Boot_Confign pin to assert + * on next system reset. + * + * @param base CMC peripheral base address. + * @param assert Assert the corresponding pin or not. + * true - Assert corresponding pin on next system reset. + * false - No effect. + */ +static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert) +{ + if (assert) + { + base->FM[0] |= CMC_FM_FORCECFG_MASK; + } + else + { + base->FM[0] &= ~CMC_FM_FORCECFG_MASK; + } +} + +/* @} */ + +/*! + * @name BootROM Status. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG) +/*! + * @brief Gets the status information written by the BootROM. + * + * @param base CMC peripheral base address. + * @return The status information written by the BootROM. + */ +static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base) +{ + return base->BSR; +} + +/*! + * @brief Sets the bootROM status value. + * + * @note This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true. + * + * @param base CMC peripheral base address. + * @param stat The state value to set. + */ +static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue) +{ + base->BSR = CMC_BSR_STAT(statValue); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG) +/*! + * @brief Check if BootROM status and lock registers is writtable. + * + * @param base CMC peripheral base address. + * @return The result of whether BootROM status and lock register is writtable. + * - \b true BootROM status and lock registers are writtable; + * - \b false BootROM status and lock registers are not writtable. + */ +static inline bool CMC_CheckBootRomRegisterWrittable(CMC_Type *base) +{ + return (base->BLR == 0x2UL); +} + +/*! + * @brief After invoking this function, BootROM status and lock registers cannot be written. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x5U); +} + +/*! + * @brief After invoking this function, BootROM status and lock register can be written.s + * + * @param base + */ +static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x2U); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */ + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @name System SRAM Configuration. + * @{ + */ + +/*! + * @brief Power off the selected system SRAM always. + * + * This function power off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered off all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on SRAM during all mode. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered on all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + base->SRAMDIS[0] &= CMC_SRAMDIS_DIS((uint32_t)(~mask)); +} + +/*! + * @brief Power off the selected system SRAM during low power modes only. + * + * This function power off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power off during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on the selected system SRAM during low power modes only. + * + * This function power on the selected system SRAM. The SRAM arrray contents are + * retained in low power modes. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power on during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + base->SRAMRET[0] &= CMC_SRAMRET_RET((uint32_t)(~mask)); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @name Flash Low Power Mode configuration. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable); +#else +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param wake true: Flash will exit low power state during the flash memory accesses. + * false: No effect. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable); +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ +/* @} */ + +/*! + * @name Debug Configuration. + */ + +/*! + * @brief Enables/Disables debug Operation when the core sleep. + * + * This function configs what happens to debug when core sleeps. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Debug when Core is sleeping. + * true - Debug remains enabled when the core is sleeping. + * false - Debug is disabled when the core is sleeping. + */ +static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable) +{ + if (enable) + { + base->DBGCTL &= ~CMC_DBGCTL_SOD_MASK; + } + else + { + base->DBGCTL |= CMC_DBGCTL_SOD_MASK; + } +} + +/* @} */ + +/*! + * @name Low Power modes enter. + * @{ + */ +/*! + * @brief Prepares to enter low power modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void); + +/*! + * @brief Recovers after wake up from low power modes. + * + * This function should be called after wake up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void); + +/*! + * @brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode); + +/*! + * @brief Configs the entry into different low power modes for each power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * @param base CMC peripheral base address. + * @param config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ +#endif /* FSL_CMC_H_ */ diff --git a/drivers/mcx_romapi/flash/fsl_efuse.h b/drivers/mcx_romapi/flash/fsl_efuse.h new file mode 100644 index 000000000..aad5bf341 --- /dev/null +++ b/drivers/mcx_romapi/flash/fsl_efuse.h @@ -0,0 +1,112 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_EFUSE_H_ +#define FSL_EFUSE_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup efuse_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EFUSE APIs + * @{ + */ + +/*! + * @brief Initialize EFUSE controller. + * + * This function enables EFUSE Controller clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Init(void); + +/*! + * @brief De-Initialize EFUSE controller. + * + * This functin disables EFUSE Controller Clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Deinit(void); + +/*! + * @brief Read Fuse value from eFuse word. + * + * This function read fuse data from eFuse word to specified data buffer. + * + * @param addr Fuse address + * @param data Buffer to hold the data read from eFuse word + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data); + +/*! + * @brief Program value to eFuse block. + * + * This function program data to specified eFuse address. + * + * @param addr Fuse address + * @param data data to be programmed into eFuse Fuse block + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! FSL_EFUSE_H_ */ diff --git a/drivers/mcx_romapi/flash/fsl_flash.h b/drivers/mcx_romapi/flash/fsl_flash.h new file mode 100644 index 000000000..ccdf3ff90 --- /dev/null +++ b/drivers/mcx_romapi/flash/fsl_flash.h @@ -0,0 +1,591 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_H_ +#define FSL_FLASH_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) /*!< Version 1.0.0. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 1, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash driver support feature + * @{ + */ +#define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U + +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_CfpaScratchPageInvalid = + MAKE_STATUS(kStatusGroupFlashDriver, 0x30), /*!< CFPA Scratch Page is invalid*/ + kStatus_FLASH_CfpaVersionRollbackDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x31), /*!< CFPA version rollback is not allowed */ + kStatus_FLASH_ReadHidingAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x32), /*!< Flash hiding read is not allowed */ + kStatus_FLASH_ModifyProtectedAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x33), /*!< Flash firewall page locked erase and program are not allowed */ + kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( + kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4U, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512U, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4U,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16U /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0U, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1U /*! ECC is off */ +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0U, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1U, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2U, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3U /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0U, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1U /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0U, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1U, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2U, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3U /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; + uint32_t *nbootCtx; + bool useAhbRead; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + * The flash_deinit API should be called after all the other FLASH APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_Deinit(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need to be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name CustKeyStore + * @{ + */ + +/*! + * @brief Get the customer key store data from the customer key store region . + * + * @param config Pointer to flash_config_t data structure in memory to store driver runtime state. + * @param pData Pointer to the customer key store data buffer, which got from the customer key store region. + * @param offset Point to the offset value based on the customer key store address(0x3e400) of the device. + * @param len Point to the length of the expected get customer key store data, and the offset + len <= 512B. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*@}*/ + +/*! + * @name flash status + * @{ + */ +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + * + * @param config A pointer to the storage for the driver runtime state. + * @param startAddress The start address of the desired flash memory to be verified. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +#endif + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FLASH_FLASH_H_ */ diff --git a/drivers/mcx_romapi/flash/fsl_flash_ffr.h b/drivers/mcx_romapi/flash/fsl_flash_ffr.h new file mode 100644 index 000000000..29a764f81 --- /dev/null +++ b/drivers/mcx_romapi/flash/fsl_flash_ffr.h @@ -0,0 +1,591 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_FFR_H_ +#define FSL_FLASH_FFR_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup flash_ffr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_CUST_ADDRESS (0x200U) +#define FLASH_FFR_CUST_PAGE_NUMBER (15u) + +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) +#define FLASH_FFR_KETBLOB_OFFSET (0x160u) +#define FLASH_FFR_KETBLOB_SIZE (0x30u) +#define CFPA_HEADER_MARKER (0x9635u) +#define CMPA_HEADER_MARKER (0x5963u) +#define FLASH_FFR_UUID_SIZE (16u) +enum flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_CfgPing = 0, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 1, /*!< Same as CFPA page (Pong page)*/ + kFfrPageOffset_CMPA_Cfg = 2, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Cfg = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_SBL_Cfg = 4, /*!< SBL recovery programmed area*/ + kFfrPageOffset_B0_IFR1_Visible = 128, /*!< Trim programmed area*/ + +}; + +enum flash_ffr_page_num +{ + kFfrSectorNum_CFPA = 2, /*!< Customer In-Field programmed area*/ + kFfrSectorNum_CMPA = 1, /*!< Customer Manufacturing programmed area*/ + kFfrSectorNum_NMPA = 1, /*!< NXP Manufacturing programmed area*/ + kFfrSectorNum_SBL = 4, /*!< SBL Cus programmed area*/ + kFfrSectorNum_Total = (kFfrSectorNum_CFPA + kFfrSectorNum_CMPA + kFfrSectorNum_NMPA + kFfrSectorNum_SBL), +}; + +enum flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1000u, +}; + +enum cfpa_cfg_cmpa_prog_status +{ + kFfrCmpaProgStatus_Idle = 0x0u, + kFfrCmpaProgStatus_InProgress = 0x5CC55AA5u, +}; + +typedef enum +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct +{ + struct + { + uint32_t cfpa_lc_state : 8; + uint32_t cfpa_lc_state_inv : 8; + uint32_t header_marker : 16; + } header; //!< [0x000-0x003] + + struct //!< [0x004-0x007] + { + uint32_t version : 24; //!< cfpa version + uint32_t img_upd : 2; //!< image cmac update + uint32_t reserved0 : 1; + uint32_t cmpa_update : 3; //!< CFPA page updated through SB command. + uint32_t reserved1 : 1; + uint32_t dice_en : 1; //!< Update DICE certificate during next boot + } cfpa_page_version; + + uint32_t secureFwVersion; //!< [0x008-0x00b] + uint32_t nsFwVersion; //!< [0x00c-0x00f] + uint32_t recFwVersion; //!< [0x010-0x013] + uint32_t secBootFlags; //!< [0x014-0x01f] + uint32_t imageKeyRevoke; //!< [0x018-0x01b] + uint32_t lpVectorAddr; //!< [0x01c-0x01f] + uint32_t vendorUsage; //!< [0x020-0x02f] + uint32_t dcfgNsPin; //!< [0x024-0x027] + uint32_t dcfgNsDflt; //!< [0x028-0x02b] + uint32_t reserved0; //!< [0x02c-0x02f] + uint32_t ivPrince[4]; //!< [0x030-0x03f] + uint32_t ivIped[8]; //!< [0x040-0x05f] + + uint32_t errCnt[8]; //!< [0x060-0x07f] + + uint32_t custCtr[8]; //!< [0x080-0x09f] + uint32_t mflagCtr[8]; //!< [0x0a0-0x0bf] + uint32_t flashAcl[8]; //!< [0x0C0-0x0Df] + uint32_t sblImg0Cmac[4]; //!< [0x0E0-0x0Ef] + uint32_t img1Cmac[4]; //!< [0x0F0-0x0Ff] + uint32_t diceCert[36]; //!< [0x100-0x18f] + uint32_t reserved2[23]; //!< [0x190-0x1eb] + uint32_t cfpaCrc; //!< [0x1ec-0x1ef] + uint32_t cfpaCmac[4]; //!< [0x1f0-0x1ff] +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_USBSPEED_SHIFT (9U) +#define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) +#define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) +#define FFR_BOOTCFG_USBSPEED_FS (0x1U) +#define FFR_BOOTCFG_USBSPEED_HS (0x2U) +#define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +#define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1) +#define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2) + +#define FFR_IFR1_PUF_AC_CODE_ADDR (0x01100200UL) +#define FFR_IFR1_PUF_AC_CODE_LEN (1024UL) + +#define FFR_IFR1_NXP_CERT_ADDR (0x01100600UL) +#define FFR_IFR1_NXP_CERT_LEN (1448UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY0_ADDR (0x01101900UL) +#define FFR_IFR1_ROM_PATCH_ARRAY0_LEN (1792UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY1_ADDR (0x01102000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY1_LEN (3584UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY2_ADDR (0x01103000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY2_LEN (2048UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY3_ADDR (0x01103800UL) +#define FFR_IFR1_ROM_PATCH_ARRAY3_LEN (2048UL) + +#define FFR_IFR1_NXP_WRITEABLE_REGION0_START (FFR_IFR1_PUF_AC_CODE_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION0_END \ + (FFR_IFR1_PUF_AC_CODE_ADDR + FFR_IFR1_PUF_AC_CODE_LEN + FFR_IFR1_NXP_CERT_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_START (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_END \ + (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR + FFR_IFR1_ROM_PATCH_ARRAY0_LEN + FFR_IFR1_ROM_PATCH_ARRAY1_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_START (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_END \ + (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR + FFR_IFR1_ROM_PATCH_ARRAY2_LEN + FFR_IFR1_ROM_PATCH_ARRAY3_LEN) + +typedef struct +{ + struct + { + uint32_t boot_src : 2; + uint32_t rsv0 : 2; + uint32_t isp_boot_if : 3; + uint32_t rsv1 : 1; + uint32_t rec_boot_src : 2; + uint32_t rsv2 : 2; + uint32_t boot_speed : 2; + uint32_t rsv3 : 2; + uint32_t header_marker : 16; + } bootCfg; //!< [0x000-0x003] + + struct + { + uint32_t flash_remap_size : 5; + uint32_t bank1_ifr0_usage : 3; + uint32_t reserved : 24; + } FlashCfg; //!< [0x004-0x007] + + struct + { + uint8_t recLed; + uint8_t ispLed; + uint8_t bootFailLed; + uint8_t resv0; + } bootLedStatus; //!< [0x008-0x00b] + + struct + { + uint16_t powerDnTimeout; + uint16_t wdogTimeout; + } bootTimers; //!< [0x00c-0x00f] + + uint32_t resv2; //!< [0x010-0x013] + uint32_t resv3; //!< [0x014-0x017] + + uint32_t recSpiFlashCfg0; //!< [0x018-0x01b] + uint32_t recSpiFlashCfg1; //!< [0x01c-0x01f] + + uint32_t isp_uart_cfg; //!< [0x020-0x023] + uint32_t isp_i2c_cfg; //!< [0x024-0x027] + uint32_t isp_can_cfg; //!< [0x028-0x02b] + uint32_t isp_spi_cfg0; //!< [0x02c-0x02f] + uint32_t isp_spi_cfg1; //!< [0x030-0x034] + + struct + { + uint16_t vid; + uint16_t pid; + } usbId; //!< [0x034-0x037] + + uint32_t isp_usb_cfg; //!< [0x038-0x038] + uint32_t isp_misc_cfg; //!< [0x03c-0x03f] + uint32_t dcfgPin; //!< [0x040-0x043] + uint32_t dcfgDflt; //!< [0x044-0x047] + uint32_t dapVendorUsage; //!< [0x048-0x04b] + uint32_t resv1; //!< [0x04c-0x04f] + uint32_t secureBootCfg; //!< [0x050-0x053] + uint32_t rokthUsage; //!< [0x054-0x057] + uint32_t resv4; //!< [0x058-0x05b] + uint32_t resv5; //!< [0x05c-0x05f] + uint32_t rotkh[12]; //!< [0x060-0x08f] + + struct + { + uint32_t npx_w0; + uint32_t npx_w1; + } princeSr[4]; //!< [0x090-0x0af] + + struct + { + uint32_t ipedStartAddr; + uint32_t ipedEndAddr; + } ipedRegions[8]; //!< [0x0b0-0x11f] + + uint32_t rec_img_exit0; + uint32_t rec_img_exit1; + + uint32_t resv6[10]; + + struct + { + uint32_t set0; + uint32_t clr0; + } quickSetGpio[6]; //!< [0x120-0x14f] + + uint32_t resv7[4]; //!< [0x150-0x15f] + uint32_t cust_key_blob[12]; //!< [0x160-0x18f] + + uint32_t resv8[23]; //!< [0x190-0x1eb] + uint32_t cmpaCrc; //!< [0x1ec-0x1ef] + uint32_t cmpaCmac[4]; //!< [0x1f0-0x1ff] + +} cmpa_cfg_info_t; + +typedef struct +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_USBCFG_USBSPEED_HS (0x0U) +#define FFR_USBCFG_USBSPEED_FS (0x1U) +#define FFR_USBCFG_USBSPEED_NO (0x2U) + +#define FFR_MCAN_BAUDRATE_MASK (0xF0000U) +#define FFR_MCAN_BAUDRATE_SHIFT (16U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +#define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) +#define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) +#define FFR_PUF_SRAM_VALID_MASK (0x1U) +#define FFR_PUF_SRAM_VALID_SHIFT (0U) +#define FFR_PUF_SRAM_MODE_MASK (0x2U) +#define FFR_PUF_SRAM_MODE_SHIFT (1U) +#define FFR_PUF_SRAM_CKGATING_MASK (0x4U) +#define FFR_PUF_SRAM_CKGATING_SHIFT (2) +#define FFR_PUF_SRAM_SMB_MASK (0x300U) +#define FFR_PUF_SRAM_SMB_SHIFT (8U) +#define FFR_PUF_SRAM_RM_MASK (0x1C00U) +#define FFR_PUF_SRAM_RM_SHIFT (10U) +#define FFR_PUF_SRAM_WM_MASK (0xE000U) +#define FFR_PUF_SRAM_WM_SHIFT (13U) +#define FFR_PUF_SRAM_WRME_MASK (0x10000U) +#define FFR_PUF_SRAM_WRME_SHIFT (16U) +#define FFR_PUF_SRAM_RAEN_MASK (0x20000U) +#define FFR_PUF_SRAM_RAEN_SHIFT (17U) +#define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) +#define FFR_PUF_SRAM_RAM_SHIFT (18U) +#define FFR_PUF_SRAM_WAEN_MASK (0x400000U) +#define FFR_PUF_SRAM_WAEN_SHIFT (22U) +#define FFR_PUF_SRAM_WAM_MASK (0x1800000U) +#define FFR_PUF_SRAM_WAM_SHIFT (23U) +#define FFR_PUF_SRAM_STBP_MASK (0x2000000U) +#define FFR_PUF_SRAM_STBP_SHIFT (25U) + +typedef struct +{ + uint32_t fro32kCfg; //!< [0x000-0x003] + uint32_t puf_cfg; //!< [0x004-0x007] + uint32_t bod; //!< [0x008-0x00b] + uint32_t trim; //!< [0x00c-0x00f] + uint32_t deviceID; //!< [0x010-0x03f] + uint32_t peripheralCfg; //!< [0x014-0x017] + uint32_t dcdPowerProFileLOW[2]; //!< [0x018-0x01f] + uint32_t deviceType; //!< [0x020-0x023] + uint32_t ldo_ao; //!< [0x024-0x027] + uint32_t gdetDelayCfg; //!< [0x028-0x02b] + uint32_t gdetMargin; //!< [0x02c-0x02f] + uint32_t gdetTrim1; //!< [0x030-0x033] + uint32_t gdetEanble1; //!< [0x034-0x037] + uint32_t gdetCtrl1; //!< [0x038-0x03b] + uint32_t gdetUpdateTimer; //!< [0x03c-0x03f] + uint32_t GpoDataChecksum[4]; //!< [0x040-0x04f] + uint32_t finalTestBatchId[4]; //!< [0x050-0x05f] + uint32_t ecidBackup[4]; //!< [0x060-0x06f] + uint32_t uuid[4]; //!< [0x070-0x07f] + uint32_t reserved1[7]; //!< [0x080-0x09b] + struct + { + uint8_t xo32mReadyTimeoutInMs; + uint8_t usbSpeed; + uint8_t reserved[2]; + } usbCfg; //!< [0x09c-0x09f] + uint32_t reserved2[80]; //!< [0x0a0-0x1df] + uint8_t cmac[16]; //!< [0x1e0-0x1ef] + uint32_t pageChecksum[4]; //!< [0x1f0-0x1ff] +} nmpa_cfg_info_t; + +typedef struct +{ + uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum +{ + kFFR_BankTypeBank0_CFPA0 = 0x00u, + kFFR_BankTypeBank0_CFPA1 = 0x01u, + kFFR_BankTypeBank0_CMPA = 0x02U, + kFFR_BankTypeBank0_NMPA = 0x03U, + kFFR_BankTypeBank0_SBL = 0x04U, + +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + */ +status_t FFR_Lock(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_SizeError Error size + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_Fail Generic status for Fail. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A pointer to the source buffer of data that is to be programmed + * into the "Key store". + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. + * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/drivers/mcx_romapi/flash/fsl_flexspi_nor_flash.h b/drivers/mcx_romapi/flash/fsl_flexspi_nor_flash.h new file mode 100644 index 000000000..2adabba33 --- /dev/null +++ b/drivers/mcx_romapi/flash/fsl_flexspi_nor_flash.h @@ -0,0 +1,721 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLEXSPI_NOR_FLASH_H__ +#define FSL_FLEXSPI_NOR_FLASH_H__ + +#include "fsl_common.h" +/*! + * @addtogroup flexspi_nor_flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 0 /*!< FLEXSPI Feature related definitions */ + +#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +#define CMD_SDR 0x01U +#define CMD_DDR 0x21U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x22U +#define CADDR_SDR 0x03U +#define CADDR_DDR 0x23U +#define MODE1_SDR 0x04U +#define MODE1_DDR 0x24U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x25U +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x26U +#define MODE8_SDR 0x07U +#define MODE8_DDR 0x27U +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x28U +#define READ_SDR 0x09U +#define READ_DDR 0x29U +#define LEARN_SDR 0x0AU +#define LEARN_DDR 0x2AU +#define DATSZ_SDR 0x0BU +#define DATSZ_DDR 0x2BU +#define DUMMY_SDR 0x0CU +#define DUMMY_DDR 0x2CU +#define DUMMY_RWDS_SDR 0x0DU +#define DUMMY_RWDS_DDR 0x2DU +#define JMP_ON_CS 0x1FU +#define FLEXSPI_STOP 0U + +#define FLEXSPI_1PAD 0U +#define FLEXSPI_2PAD 1U +#define FLEXSPI_4PAD 2U +#define FLEXSPI_8PAD 3U + +/*! + * @brief NOR LUT sequence index used for default LUT assignment + * NOTE: + * The will take effect if the lut sequences are not customized. + */ +#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READID 7U +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ + +/*! @brief FLEXSPI status group numbers. */ +enum _flexspi_status_groups +{ + kStatusROMGroup_FLEXSPI = 60, /*!< Group number for ROM FLEXSPI status codes. */ + kStatusROMGroup_FLEXSPINOR = 201, /*!< ROM FLEXSPI NOR status group number.*/ +}; + +/*! @brief FLEXSPI NOR status */ +enum _flexspi_nor_status +{ + kStatus_FLEXSPINOR_ProgramFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 0), /*!< Status for Page programming failure */ + kStatus_FLEXSPINOR_EraseSectorFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 1), /*!< Status for Sector Erase failure */ + kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 2), /*!< Status for Chip Erase failure */ + kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 3), /*!< Status for timeout */ + kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 4), // Status for PageSize overflow */ + kStatus_FlexSPINOR_WriteAlignmentError = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 5), /*!< Status for Alignement error */ + kStatus_FlexSPINOR_CommandFailure = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 6), /*!< Status for Erase/Program Verify Error */ + kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ + kStatus_FLEXSPINOR_Unsupported_SFDP_Version = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 8), /*!< Status for Unrecognized SFDP version */ + kStatus_FLEXSPINOR_Flash_NotFound = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ + kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ + + kStatus_FLEXSPI_SequenceExecutionTimeout = + MAKE_STATUS(kStatusROMGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ + kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ + kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 2), /*!< Status for Device timeout */ + +}; + +/*! @brief Configure the device_type of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorCfgOption_Tag = 0x0cU, + kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0U, + kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1U, + kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2U, + kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3U, + kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4U, + kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5U, + kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6U, + kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7U, + kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8U, + kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9U, +}; + +/*! @brief Configure the quad_mode_setting of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorQuadMode_NotConfig = 0U, + kSerialNorQuadMode_StatusReg1_Bit6 = 1U, + kSerialNorQuadMode_StatusReg2_Bit1 = 2U, + kSerialNorQuadMode_StatusReg2_Bit7 = 3U, + kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4U, +}; + +/*! @brief FLEXSPI NOR Octal mode */ +enum +{ + kSerialNorOctaldMode_NoOctalEnableBit = 0U, + kSerialNorOctaldMode_HasOctalEnableBit = 1U, +}; + +/*! @brief miscellaneous mode */ +enum +{ + kSerialNorEnhanceMode_Disabled = 0U, + kSerialNorEnhanceMode_0_4_4_Mode = 1U, + kSerialNorEnhanceMode_0_8_8_Mode = 2U, + kSerialNorEnhanceMode_DataOrderSwapped = 3U, + kSerialNorEnhanceMode_2ndPinMux = 4U, + kSerialNorEnhanceMode_InternalLoopback = 5U, + kSerialNorEnhanceMode_SpiMode = 6U, + kSerialNorEnhanceMode_ExtDqs = 8U, +}; + +/*! @brief FLEXSPI NOR reset logic options */ +enum +{ + kFlashResetLogic_Disabled = 0U, + kFlashResetLogic_ResetPin = 1U, + kFlashResetLogic_JedecHwReset = 2U, +}; + +/*! @brief Configure the flash_connection of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorConnection_SinglePortA, + kSerialNorConnection_Parallel, + kSerialNorConnection_SinglePortB, + kSerialNorConnection_BothPorts +}; + +/*! @brief + * FLEXSPI ROOT clock soruce related definitions + */ +enum +{ + kFLEXSPIClkSrc_MainClk = 0U, + kFLEXSPIClkSrc_Pll0 = 1U, + kFLEXSPIClkSrc_FroHf = 3U, + kFLEXSPIClkSrc_Pll1 = 5U, +}; + +/*! @brief Restore sequence options + * Configure the restore_sequence of "flash_run_context_t" structure + */ +enum +{ + kRestoreSequence_None = 0U, + kRestoreSequence_HW_Reset = 1U, + kRestoreSequence_QPI_4_0xFFs = 2U, + kRestoreSequence_QPI_Mode_0x00 = 3U, + kRestoreSequence_8QPI_FF = 4U, + kRestoreSequence_Send_F0 = 5U, + kRestoreSequence_Send_66_99 = 6U, + kRestoreSequence_Send_6699_9966 = 7U, + kRestoreSequence_Send_06_FF = 8U, /*!< Adesto EcoXIP */ + kRestoreSequence_QPI_5_0xFFs = 9U, + kRestoreSequence_Send_QPI_8_0xFFs = 10U, + kRestoreSequence_Wakeup_0xAB = 11U, + kRestoreSequence_Wakeup_0xAB_54 = 12U, +}; + +/*! @brief Port mode options*/ +enum +{ + kFlashInstMode_ExtendedSpi = 0x00U, + kFlashInstMode_0_4_4_SDR = 0x01U, + kFlashInstMode_0_4_4_DDR = 0x02U, + kFlashInstMode_DPI_SDR = 0x21U, + kFlashInstMode_DPI_DDR = 0x22U, + kFlashInstMode_QPI_SDR = 0x41U, + kFlashInstMode_QPI_DDR = 0x42U, + kFlashInstMode_OPI_SDR = 0x81U, + kFlashInstMode_OPI_DDR = 0x82U, +}; + +/*! + * @name Support for init FLEXSPI NOR configuration + * @{ + */ +/*! @brief Flash Pad Definitions */ +enum +{ + kSerialFlash_1Pad = 1U, + kSerialFlash_2Pads = 2U, + kSerialFlash_4Pads = 4U, + kSerialFlash_8Pads = 8U, +}; + +/*! @brief FLEXSPI clock configuration type */ +enum +{ + kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ + kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ +}; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +enum _flexspi_read_sample_clk +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, +}; + +/*! @brief Flash Type Definition */ +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +/*! @brief Flash Configuration Command Type */ +enum +{ + kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ + kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /*!< Reset device command */ +}; + +/*! @brief Defintions for FLEXSPI Serial Clock Frequency */ +enum _flexspi_serial_clk_freq +{ + kFLEXSPISerialClk_NoChange = 0U, + kFLEXSPISerialClk_30MHz = 1U, + kFLEXSPISerialClk_50MHz = 2U, + kFLEXSPISerialClk_60MHz = 3U, + kFLEXSPISerialClk_75MHz = 4U, + kFLEXSPISerialClk_100MHz = 5U, +}; + +/*! @brief Misc feature bit definitions */ +enum +{ + kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ + kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ + kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ + kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ + kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ + kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ + kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ + kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ +}; + +/*@}*/ + +/*! @brief Manufacturer ID */ +enum +{ + kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ + kSerialFlash_Adesto_ManufacturerID = 0x1FU, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ + kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ + kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ +}; + +/*! @brief + * Serial NOR configuration option + */ +typedef struct _serial_nor_config_option +{ + union + { + struct + { + uint32_t max_freq : 4; /*!< Maximum supported Frequency */ + uint32_t misc_mode : 4; /*!< miscellaneous mode */ + uint32_t quad_mode_setting : 4; /*!< Quad mode setting */ + uint32_t cmd_pads : 4; /*!< Command pads */ + uint32_t query_pads : 4; /*!< SFDP read pads */ + uint32_t device_type : 4; /*!< Device type */ + uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ + uint32_t tag : 4; /*!< Tag, must be 0x0E */ + } B; + uint32_t U; + } option0; + + union + { + struct + { + uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */ + uint32_t status_override : 8; /*!< Override status register value during device mode configuration */ + uint32_t pinmux_group : 4; /*!< The pinmux group selection */ + uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */ + uint32_t drive_strength : 4; /*!< The Drive Strength of FLEXSPI Pads */ + uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */ + /*!< Parallel mode, 2 - Single Flash connected to Port B */ + } B; + uint32_t U; + } option1; + +} serial_nor_config_option_t; + +typedef union +{ + struct + { + uint8_t por_mode; + uint8_t current_mode; + uint8_t exit_no_cmd_sequence; + uint8_t restore_sequence; + } B; + uint32_t U; +} flash_run_context_t; + +/*! @brief + * FLEXSPI LUT Sequence structure + */ +typedef struct _lut_sequence +{ + uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +typedef struct +{ + uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/*! @brief + * FLEXSPI Memory Configuration Block + */ +typedef struct _FlexSPIConfig +{ + uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ + uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ + uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ + uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + flexspi_lut_seq_t + configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ + uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + details */ + uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ + uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ + uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + Chapter for more details */ + uint8_t lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ + uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t dll0CrVal; //!> [0x1b0-0x1b3] Customizable DLL0CR setting */ + uint32_t dll1CrVal; //!> [0x1b4-0x1b7] Customizable DLL1CR setting */ + uint32_t reserved4[2]; /*!< [0x1b8-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; + +/*! @brief + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ + uint32_t pageSize; /*!< Page size of Serial NOR */ + uint32_t sectorSize; /*!< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /*!< Reserved for future use */ + uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ + uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ + uint32_t blockSize; /*!< Block size */ + uint32_t flashStateCtx; /*!< Flash State Context */ + uint32_t reserve2[10]; /*!< Reserved for future use */ +} flexspi_nor_config_t; + +typedef enum _flexspi_operation +{ + kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ + kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ + kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ + kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPIOperation_End = kFLEXSPIOperation_Read, +} flexspi_operation_t; + +/*! @brief FLEXSPI Transfer Context */ +typedef struct _flexspi_xfer +{ + flexspi_operation_t operation; /*!< FLEXSPI operation */ + uint32_t baseAddress; /*!< FLEXSPI operation base address */ + uint32_t seqId; /*!< Sequence Id */ + uint32_t seqNum; /*!< Sequence Number */ + bool isParallelModeEnable; /*!< Is a parallel transfer */ + uint32_t *txBuffer; /*!< Tx buffer */ + uint32_t txSize; /*!< Tx size in bytes */ + uint32_t *rxBuffer; /*!< Rx buffer */ + uint32_t rxSize; /*!< Rx size in bytes */ +} flexspi_xfer_t; + +/*! @brief + * FLEXSPI Clock Type + */ +typedef enum +{ + kFlexSpiClock_CoreClock, /*!< ARM Core Clock */ + kFlexSpiClock_AhbClock, /*!< AHB clock */ + kFlexSpiClock_SerialRootClock, /*!< Serial Root Clock */ + kFlexSpiClock_IpgClock, /*!< IPG clock */ +} flexspi_clock_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t FLEXSPI_NorFlash_GetVersion(void); +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * This function programs the NOR flash memory with the dest address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst_addr A pointer to the desired flash memory to be programmed. + * NOTE: + * It is recommended that use page aligned access; + * If the dst_addr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src); + +/*! + * @brief Erase all the Serial NOR devices connected on FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Erase one sector specified by address + * + * This function erases one of NOR flash sectors based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param address The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,The driver automatically + * aligns address down with the sector address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Erase one block specified by address + * + * This function erases one block of NOR flash based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use block-aligned access nor device; + * If dstAddr is not aligned with the block,The driver automatically + * aligns address down with the block address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Get FLEXSPI NOR Configuration Block based on specified option. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param option A pointer to the storage Serial NOR Configuration Option Context. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, + flexspi_nor_config_t *config, + serial_nor_config_option_t *option); + +/*! + * @brief Erase Flash Region specified by address and length + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,the driver automatically + * aligns address down with the sector address. + * @param length The length, given in bytes to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If length is not aligned with the sector,the driver automatically + * aligns up with the sector. + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + +/*! + * @brief Read data from Serial NOR via FLEXSPI. + * + * This function read the NOR flash memory with the start address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. + * NOTE: + * It is recommended that use page aligned access; + * If the dstAddr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param start The start address of the desired NOR flash memory to be read. + * @param lengthInBytes The length, given in bytes to be read. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + +/*! + * @brief FLEXSPI command + * + * This function is used to perform the command write sequence to the NOR device. + * + * @param instance storage the index of FLEXSPI. + * @param xfer A pointer to the storage FLEXSPI Transfer Context. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); + +/*! + * @brief Configure FLEXSPI Lookup table + * + * @param instance storage the index of FLEXSPI. + * @param seqIndex storage the sequence Id. + * @param lutBase A pointer to the look-up-table for command sequences. + * @param seqNumber storage sequence number. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber); + +/*! + * @brief Set the clock source for FLEXSPI NOR + * + * @param clockSource Clock source for FLEXSPI NOR. See to "_flexspi_nor_clock_source". + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource); + +/*! + * @brief Configure the FlexSPI clock. + * + *The API is used for configuring the FlexSPI clock. + * + * @param instance storage the index of FLEXSPI. + * @param freqOption storage FlexSPIFlexSPI flash serial clock frequency. + * @param sampleClkMode storage the FlexSPI clock configuration type. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + */ +void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); + +#ifdef __cplusplus +} +#endif + +#endif /*! FSL_FLEXSPI_NOR_FLASH_H__ */ diff --git a/drivers/mcx_romapi/flash/src/fsl_flash.c b/drivers/mcx_romapi/flash/src/fsl_flash.c new file mode 100644 index 000000000..d2a2edead --- /dev/null +++ b/drivers/mcx_romapi/flash/src/fsl_flash.c @@ -0,0 +1,567 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flashiap" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! + * @name flash, ffr, flexspi nor flash Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); + status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +} function_command_option_t; + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number. */ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + const uint32_t reserved0[3]; + + /*!< Flash FFR driver */ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t reserved1; + status_t reserved2; + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + const uint32_t reserved3; + status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_deinit)(flash_config_t *config); +} flash_driver_interface_t; + +/*! @brief FLEXSPI Flash driver API Interface */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); + status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); + status_t (*set_clock_source)(uint32_t clockSrc); + void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); + status_t (*partial_program)( + uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src, uint32_t length); +} flexspi_nor_flash_driver_t; + +/* !@brief EFUSE driver API Interface */ +typedef struct +{ + standard_version_t version; + status_t (*init)(void); + status_t (*deinit)(void); + status_t (*read)(uint32_t addr, uint32_t *data); + status_t (*program)(uint32_t addr, uint32_t data); +} efuse_driver_t; + +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const efuse_driver_t *efuseDriver; /*!< eFuse driver API */ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************** + * Internal Flash driver API + *******************************************************************************/ +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_init(config); +} + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + */ +status_t FLASH_Deinit(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_deinit(config); +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program(config, start, src, lengthInBytes); +} + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_read(config, start, dest, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program(config, start, lengthInBytes, expectedData, + failedAddress, failedData); +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); +} + +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +#if defined(BL_FEATURE_HAS_BUS_CRYPTO_ENGINE) && BL_FEATURE_HAS_BUS_CRYPTO_ENGINE +status_t FLASH_ErasePrologue(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_with_checker(config, start, lengthInBytes, key); +} + +status_t FLASH_ProgramPrologue(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program_with_checker(config, start, src, lengthInBytes); +} + +status_t FLASH_VerifyProgramPrologue(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program_with_checker( + config, start, lengthInBytes, expectedData, failedAddress, failedData); +} + +#endif // BL_FEATURE_HAS_BUS_CRYPTO_ENGINE + +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) +{ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x130366f9u; + return runCmdFuncOption.isFlashAreaReadable(config, startAddress, lengthInBytes); +} +#endif + +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! + * @brief Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_init(config); +} + +/*! + * @brief Enable firewall for all flash banks. + */ +status_t FFR_Lock(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_lock(config); +} + +/*! + * @brief APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_factory_page_write(config, page_data, seal_part); +} + +/*! + * @brief See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_uuid(config, uuid); +} + +/*! + * @brief APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_data(config, pData, offset, len); +} + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_keystore_write(config, pKeyStore); +} + +/*! + * @brief APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_infield_page_write(config, page_data, valid_len); +} + +/*! + * @brief APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_infield_data(config, pData, offset, len); +} + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +/******************************************************************************** + * FlexSPI NOR FLASH Driver API + *******************************************************************************/ +/*! + * @brief Initialize Serial NOR devices via FLEXSPI. + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->init(instance, config); +} + +/*! + * @brief Program data to Serial NOR via FlexSPI + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->page_program(instance, config, dstAddr, src); +} + +/*! + * @brief Erase all the Serial NOR devices connected on FlexSPI + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_all(instance, config); +} + +/*! + * @brief Erase Flash Region specified by address and length + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase(instance, config, start, length); +} + +/*! + * @brief Erase one sector specified by address + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_sector(instance, config, address); +} + +/*! + * @brief Erase one block specified by address + */ +status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_block(instance, config, address); +} + +/*! + * @brief Get FlexSPI NOR driver version + */ +uint32_t FLEXSPI_NorFlash_GetVersion(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->version; +} + +/*! + * @brief Get FlexSPI NOR Configuration Block based on specified option + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->get_config(instance, config, option); +} + +/*! + * @brief Read data from Serial NOR + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->read(instance, config, dst, start, bytes); +} + +/*! + * @brief Perform FlexSPI command + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->xfer(instance, xfer); +} + +/*! + * @brief Configure FlexSPI Lookup table + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); +} + +/*! + * @brief Set flexspi clock source + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->set_clock_source(clockSource); +} + +/*! + * @brief config flexspi clock + */ +void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->config_clock(instance, freqOption, sampleClkMode); +} + +/******************************************************************************** + * EFUSE driver API + *******************************************************************************/ + +/*! + * @brief Initialize EFUSE controller. + */ +status_t EFUSE_Init(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->init(); +} + +/*! + * @brief De-Initialize EFUSE controller. + */ +status_t EFUSE_Deinit(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->deinit(); +} + +/*! + * @brief Read Fuse value from eFuse word. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->read(addr, data); +} + +/*! + * @brief Program value to eFuse block. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + status_t status; + bool is_hvd_enabled = false; + + /* Disable SYS_HVD */ + if (0 != (SPC0->ACTIVE_CFG & SPC_ACTIVE_CFG_SYS_HVDE_MASK)) + { + is_hvd_enabled = true; + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + /* Call ROM API to program efuse */ + status = BOOTLOADER_API_TREE_POINTER->efuseDriver->program(addr, data); + + /* Bring VDD_SYS back to 1.8v */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK; + + /* Wait for voltage to settle */ + SDK_DelayAtLeastUs(5000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable SYS_HVD back */ + if (is_hvd_enabled) + { + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} diff --git a/drivers/mcx_romapi/mem_interface/fsl_mem_interface.h b/drivers/mcx_romapi/mem_interface/fsl_mem_interface.h new file mode 100644 index 000000000..98147b6ba --- /dev/null +++ b/drivers/mcx_romapi/mem_interface/fsl_mem_interface.h @@ -0,0 +1,379 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_MEM_INTERFACE_H_ +#define FSL_MEM_INTERFACE_H_ + +#include "fsl_sbloader.h" +#include "fsl_common.h" + +/*! + * @addtogroup memory_interface + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Bit mask for device ID. */ +#define DEVICE_ID_MASK (0xffU) +/*! @brief Bit position of device ID. */ +#define DEVICE_ID_SHIFT 0U +/*! @brief Bit mask for group ID. */ +#define GROUP_ID_MASK (0xf00U) +/*! @brief Bit position of group ID. */ +#define GROUP_ID_SHIFT 8U + +/*! @brief Construct a memory ID from a given group ID and device ID. */ +#define MAKE_MEMORYID(group, device) \ + ((((group) << GROUP_ID_SHIFT) & GROUP_ID_MASK) | (((device) << DEVICE_ID_SHIFT) & DEVICE_ID_MASK)) +/*! @brief Get group ID from a given memory ID. */ +#define GROUPID(memoryId) (((memoryId)&GROUP_ID_MASK) >> GROUP_ID_SHIFT) + +/*! @brief Get device ID from a given memory ID. */ +#define DEVICEID(memoryId) (((memoryId)&DEVICE_ID_MASK) >> DEVICE_ID_SHIFT) + +/*! @brief Memory group definition. */ +enum +{ + kMemoryGroup_Internal = 0U, /*!< Memory belongs internal 4G memory region. */ + kMemoryGroup_External = 1U, /*!< Memory belongs external memory region. */ +}; + +/*! @brief Memory device ID definition. */ +enum +{ + /* Memory ID bitfiled definition. + | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | Reserved | INT/EXT | Type | Sub-Type | + | | 0: INT | INT: | | + | | 1: EXT | 0: NorFlash0 | 0: Internal Flash(FTFX) | + | | | | 1: QSPI | + | | | | 4: IFR | + | | | | 5: LPC FFR | + | | | | 8: SEMC | + | | | | 9: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: ExecuteOnlyRegion | 0: Internal Flash(FTFX) | + | | | | others: Unused | + | | | | | + | | | others: Unused | | + | | | | | + | | | EXT: | | + | | | 0: NandFlash | 0: SEMC | + | | | | 1: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: NorFlash/EEPROM | 0: LPSPI | + | | | | 1: LPI2C | + | | | | others: Unused | + | | | | | + | | | 2: SD/SDHC/SDXC/MMC/eMMC | 0: uSDHC SD | + | | | | 1: uSDHC MMC | + | | | | others: Unused | + | | | others: Unused | | + + INT : Internal 4G memory, including internal memory modules, and XIP external memory modules. + EXT : Non-XIP external memory modules. + */ + kMemoryInternal = MAKE_MEMORYID(kMemoryGroup_Internal, 0U), /*!< Internal memory (include all on chip memory) */ + kMemoryQuadSpi0 = MAKE_MEMORYID(kMemoryGroup_Internal, 1U), /*!< Qsuad SPI memory 0 */ + kMemoryIFR0 = + MAKE_MEMORYID(kMemoryGroup_Internal, 4U), /*!< Nonvolatile information register 0. Only used by SB loader. */ + kMemoryFFR = MAKE_MEMORYID(kMemoryGroup_Internal, 5U), /*!< LPCc040hd flash FFR region. */ + kMemorySemcNor = MAKE_MEMORYID(kMemoryGroup_Internal, 8U), /*!< SEMC Nor memory */ + kMemoryFlexSpiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 9U), /*!< Flex SPI Nor memory */ + kMemorySpifiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 0xAU), /*!< SPIFI Nor memory */ + kMemoryFlashExecuteOnly = MAKE_MEMORYID(kMemoryGroup_Internal, 0x10U), /*!< Execute-only region on internal Flash */ + + kMemorySemcNand = MAKE_MEMORYID(kMemoryGroup_External, 0U), /*!< SEMC NAND memory */ + kMemorySpiNand = MAKE_MEMORYID(kMemoryGroup_External, 1U), /*!< SPI NAND memory */ + kMemorySpiNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x10U), /*!< SPI NOR/EEPROM memory */ + kMemoryI2cNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x11U), /*!< I2C NOR/EEPROM memory */ + kMemorySDCard = MAKE_MEMORYID(kMemoryGroup_External, 0x20U), /*!< eSD, SD, SDHC, SDXC memory Card */ + kMemoryMMCCard = MAKE_MEMORYID(kMemoryGroup_External, 0x21U), /*!< MMC, eMMC memory Card */ +}; + +/*! @brief Bootloader status group numbers. + * + * @ingroup bl_core + */ +enum +{ + kStatusGroup_Bootloader = 100, /*!< Bootloader status group number (100). */ + kStatusGroup_MemoryInterface = 102, /*!< Memory interface status group number (102). */ +}; + +/*! @brief Memory interface status codes. */ +enum +{ + kStatusMemoryRangeInvalid = MAKE_STATUS(kStatusGroup_MemoryInterface, 0), + kStatusMemoryReadFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 1), + kStatusMemoryWriteFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 2), + kStatusMemoryCumulativeWrite = MAKE_STATUS(kStatusGroup_MemoryInterface, 3), + kStatusMemoryAppOverlapWithExecuteOnlyRegion = MAKE_STATUS(kStatusGroup_MemoryInterface, 4), + kStatusMemoryNotConfigured = MAKE_STATUS(kStatusGroup_MemoryInterface, 5), + kStatusMemoryAlignmentError = MAKE_STATUS(kStatusGroup_MemoryInterface, 6), + kStatusMemoryVerifyFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 7), + kStatusMemoryWriteProtected = MAKE_STATUS(kStatusGroup_MemoryInterface, 8), + kStatusMemoryAddressError = MAKE_STATUS(kStatusGroup_MemoryInterface, 9), + kStatusMemoryBlankCheckFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 10), + kStatusMemoryBlankPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 11), + kStatusMemoryProtectedPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 12), + kStatusMemoryFfrSpecRegionWriteBroken = MAKE_STATUS(kStatusGroup_MemoryInterface, 13), + kStatusMemoryUnsupportedCommand = MAKE_STATUS(kStatusGroup_MemoryInterface, 14), +}; + +/*! @brief Bootloader status codes. */ +enum +{ + kStatus_UnknownCommand = MAKE_STATUS(kStatusGroup_Bootloader, 0), + kStatus_SecurityViolation = MAKE_STATUS(kStatusGroup_Bootloader, 1), + kStatus_AbortDataPhase = MAKE_STATUS(kStatusGroup_Bootloader, 2), + kStatus_Ping = MAKE_STATUS(kStatusGroup_Bootloader, 3), + kStatus_NoResponse = MAKE_STATUS(kStatusGroup_Bootloader, 4), + kStatus_NoResponseExpected = MAKE_STATUS(kStatusGroup_Bootloader, 5), + kStatus_CommandUnsupported = MAKE_STATUS(kStatusGroup_Bootloader, 6), +}; + +/*! + * @brief Interface to memory operations. + * + * This is the main abstract interface to all memory operations. + */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer, uint32_t memoryId); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer, uint32_t memoryId); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*finalize)(void); + status_t (*erase)(uint32_t address, uint32_t length, uint32_t memoryId); +} memory_interface_t; + +/*! @brief Interface to memory operations for one region of memory. */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +//! @brief Structure of a memory map entry. +typedef struct +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +/*! @brief Structure of version property. */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief API initialization data structure */ +typedef struct kb_api_parameter_struct +{ + uint32_t allocStart; + uint32_t allocSize; +} kp_api_init_param_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void); + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx); + +/*! + * @brief Initialize memory interface. + * + * @retval #kStatus_Fail + * @retval #kStatus_Success + */ +status_t MEM_Init(api_core_context_t *coreCtx); + +/*! + * @brief Configure memory interface + * + * @param config A pointer to the storage for the driver runtime state. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport +*/ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId); + +/*! + * @brief Write memory. + * + * @param address The start address of the desired flash memory to be programmed. + For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param buffer A pointer to the source buffer of data that is to be programmed into the flash. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatus_FLASH_CompareError + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId); + +/*! + * @brief Fill memory with a word pattern. + * + * @param address The start address of the desired flash memory to be programmed. + * For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param pattern The data to be written into the specified memory area. + * + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_Success + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId); + +/*! + * @brief Flush memory. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Flush(api_core_context_t *coreCtx); + +/*! + * @brief Erase memory. + * + * @param address The start address of the desired flash memory to be erased. + * @param length Number of bytes to be read. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatusMemoryAddressError + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + + */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId); + +/*! + * @brief Erase entire memory based on memoryId + * + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + * @retval #kStatusMemoryNotConfigured + * @retval #kStatus_InvalidArgument + */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_MEM_INTERFACE_H_ */ diff --git a/drivers/mcx_romapi/mem_interface/fsl_sbloader.h b/drivers/mcx_romapi/mem_interface/fsl_sbloader.h new file mode 100644 index 000000000..c2862e73d --- /dev/null +++ b/drivers/mcx_romapi/mem_interface/fsl_sbloader.h @@ -0,0 +1,373 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SBLOADER_H_ +#define FSL_SBLOADER_H_ + +#include "fsl_flash.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_sbloader_v3.h" +#include "fsl_common.h" +/*! + * @addtogroup sbloader + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Determines the version of SB loader implementation (1: sb1.0; 2: sb2.0; 3.1: sb3.1) */ +#define SB_FILE_MAJOR_VERSION (3) +#define SB_FILE_MINOR_VERSION (1) + +/*! @brief Bootloader status group numbers */ +#define kStatusGroup_SBLoader (101U) + +/*! @brief Contiguous RAM region count */ +#define RAM_REGION_COUNT (2U) + +/*! @brief Contiguous FLASH region count */ +#define FLASH_REGION_COUNT (1U) + +/*! @brief Contiguous FFR region count */ +#define FFR_REGION_COUNT (1U) + +/*! @brief Memory Interface count */ +#define MEM_INTERFACE_COUNT (4U) + +/*! @brief Contiguous FLEXSPINOR meomry count */ +#define FLEXSPINOR_REGION_COUNT (1U) + +/*! @brief SB loader status codes.*/ +enum +{ + kStatusRomLdrSectionOverrun = MAKE_STATUS(kStatusGroup_SBLoader, 0), + kStatusRomLdrSignature = MAKE_STATUS(kStatusGroup_SBLoader, 1), + kStatusRomLdrSectionLength = MAKE_STATUS(kStatusGroup_SBLoader, 2), + kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3), + kStatusRomLdrEOFReached = MAKE_STATUS(kStatusGroup_SBLoader, 4), + kStatusRomLdrChecksum = MAKE_STATUS(kStatusGroup_SBLoader, 5), + kStatusRomLdrCrc32Error = MAKE_STATUS(kStatusGroup_SBLoader, 6), + kStatusRomLdrUnknownCommand = MAKE_STATUS(kStatusGroup_SBLoader, 7), + kStatusRomLdrIdNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 8), + kStatusRomLdrDataUnderrun = MAKE_STATUS(kStatusGroup_SBLoader, 9), + kStatusRomLdrJumpReturned = MAKE_STATUS(kStatusGroup_SBLoader, 10), + kStatusRomLdrCallFailed = MAKE_STATUS(kStatusGroup_SBLoader, 11), + kStatusRomLdrKeyNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 12), + kStatusRomLdrSecureOnly = MAKE_STATUS(kStatusGroup_SBLoader, 13), + kStatusRomLdrResetReturned = MAKE_STATUS(kStatusGroup_SBLoader, 14), + + kStatusRomLdrRollbackBlocked = MAKE_STATUS(kStatusGroup_SBLoader, 15), + kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16), + kStatusRomLdrUnexpectedCommand = MAKE_STATUS(kStatusGroup_SBLoader, 17), + kStatusRomLdrBadSBKEK = MAKE_STATUS(kStatusGroup_SBLoader, 18), + kStatusRomLdrPendingJumpCommand = MAKE_STATUS(kStatusGroup_SBLoader, 19), +}; + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define BYTES_PER_CHUNK 16 + +#define SB_SECTION_COUNT_MAX 8 + +/*! @brief Boot image signature in 32-bit little-endian format "PMTS" */ +#define BOOT_SIGNATURE 0x504d5453 + +/*! @brief Boot image signature in 32-bit little-endian format "ltgs" */ +#define BOOT_SIGNATURE2 0x6c746773 + +/*! @brief These define file header flags */ +#define FFLG_DISPLAY_PROGRESS 0x0001 + +/*! @brief These define section header flags */ +#define SFLG_SECTION_BOOTABLE 0x0001 + +/*! @brief These define boot command flags */ +#define CFLG_LAST_TAG 0x01 + +/*! @brief ROM_ERASE_CMD flags */ +#define ROM_ERASE_ALL_MASK 0x01 +#define ROM_ERASE_ALL_UNSECURE_MASK 0x02 + +/*! @brief ROM_JUMP_CMD flags */ +#define ROM_JUMP_SP_MASK 0x02 + +/*! @brief Memory device id shift at sb command flags */ +#define ROM_MEM_DEVICE_ID_SHIFT 0x8 + +/*! @brief Memory device id mask */ +#define ROM_MEM_DEVICE_ID_MASK 0xff00 + +/*! @brief Memory group id shift at sb command flags */ +#define ROM_MEM_GROUP_ID_SHIFT 0x4 + +/*! @brief Memory group id flags mask */ +#define ROM_MEM_GROUP_ID_MASK 0xf0 + +/*! @brief ROM_PROG_CMD flags */ +#define ROM_PROG_8BYTE_MASK 0x01 + +/*! @brief These define the boot command tags */ +#define ROM_NOP_CMD 0x00 +#define ROM_TAG_CMD 0x01 +#define ROM_LOAD_CMD 0x02 +#define ROM_FILL_CMD 0x03 +#define ROM_JUMP_CMD 0x04 +#define ROM_CALL_CMD 0x05 +#define ROM_MODE_CMD 0x06 +#define ROM_ERASE_CMD 0x07 +#define ROM_RESET_CMD 0x08 +#define ROM_MEM_ENABLE_CMD 0x09 +#define ROM_PROG_CMD 0x0a +#define ROM_FW_VER_CHK 0x0b + +#if SB_FILE_MAJOR_VERSION == 2 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V2_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V2_CMD_SET_IN_REC_MODE) +#elif SB_FILE_MAJOR_VERSION == 3 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V3_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V3_CMD_SET_IN_REC_MODE) +#endif + +/*! @brief Plugin return codes */ +#define ROM_BOOT_SECTION_ID 1 +#define ROM_BOOT_IMAGE_ID 2 + +enum _fw_version_check_option +{ + kRomLdr_FwCheckOption_SecureVersion = 0x0U, + kRomLdr_FwCheckOption_NonSecureVersion = 0x1U, +}; + +typedef uint8_t chunk_t[BYTES_PER_CHUNK]; + +/*! @brief Boot command definition */ +typedef struct _boot_cmd +{ + uint8_t checksum; /*!< 8-bit checksum over command chunk */ + uint8_t tag; /*!< command tag (identifier) */ + uint16_t flags; /*!< command flags (modifier) */ + uint32_t address; /*!< address argument */ + uint32_t count; /*!< count argument */ + uint32_t data; /*!< data argument */ +} boot_cmd_t; + +/*! @brief Definition for boot image file header chunk 1 */ +typedef struct _boot_hdr1 +{ + uint32_t hash; /*!< last 32-bits of SHA-1 hash */ + uint32_t signature; /*!< must equal "STMP" */ + uint8_t major; /*!< major file format version */ + uint8_t minor; /*!< minor file format version */ + uint16_t fileFlags; /*!< global file flags */ + uint32_t fileChunks; /*!< total chunks in the file */ +} boot_hdr1_t; + +/*! @brief Definition for boot image file header chunk 2 */ +typedef struct _boot_hdr2 +{ + uint32_t bootOffset; /*!< chunk offset to the first boot section */ + uint32_t bootSectID; /*!< section ID of the first boot section */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint16_t keyOffset; /*!< chunk offset to the key dictionary */ + uint16_t hdrChunks; /*!< number of chunks in the header */ + uint16_t sectCount; /*!< number of sections in the image */ +} boot_hdr2_t; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context ldr_Context_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_t)(ldr_Context_t *context); + +/*! @brief Jump command function pointer definition. */ +typedef status_t (*pJumpFnc_t)(uint32_t parameter); + +/*! @brief Call command function pointer definition. */ +typedef status_t (*pCallFnc_t)(uint32_t parameter, uint32_t *func); + +/*! @brief State information for the CRC32 algorithm. */ +typedef struct Crc32Data +{ + uint32_t currentCrc; /*!< Current CRC value. */ + uint32_t byteCountCrc; /*!< Number of bytes processed. */ +} crc32_data_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context +{ + pLdrFnc_t Action; /*!< pointer to loader action function */ + uint32_t fileChunks; /*!< chunks remaining in file */ + uint32_t sectChunks; /*!< chunks remaining in section */ + uint32_t bootSectChunks; /*!< number of chunks we need to complete the boot section */ + uint32_t receivedChunks; /*!< number of chunks we need to complete the boot section */ + uint16_t fileFlags; /*!< file header flags */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint32_t objectID; /*!< ID of the current boot section or image */ + crc32_data_t crc32; /*!< crc calculated over load command payload */ + uint8_t *src; /*!< source buffer address */ + chunk_t initVector; /*!< decryption initialization vector */ + chunk_t dek; /*!< chunk size DEK if the image is encrypted */ + chunk_t scratchPad; /*!< chunk size scratch pad area */ + boot_cmd_t bootCmd; /*!< current boot command */ + uint32_t skipCount; /*!< Number of chunks to skip */ + bool skipToEnd; /*!< true if skipping to end of file */ + + // extended for SB 2.0 + uint32_t nonce[4]; + uint32_t keyBlobBlock; + uint32_t keyBlobBlockCount; + uint8_t *keyBlobBuffer; + uint32_t offsetSignatureBytes; /*!< offset to signagure block header in bytesn */ + uint8_t *headerBuffer; +}; + +typedef struct soc_memory_map_struct +{ + struct + { + uint32_t start; + uint32_t end; + } ramRegions[RAM_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flashRegions[FLASH_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } ffrRegions[FFR_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flexspiNorRegions[FLEXSPINOR_REGION_COUNT]; +} soc_mem_regions_t; + +typedef struct arena_context +{ + uint32_t start; + uint32_t end; + uint32_t nextAddr; +} arena_context_t; + +/*! @brief Memory region information table */ +typedef struct mem_region +{ + uint32_t start; + uint32_t end; +} mem_region_t; + +/*! @brief Memory Attribute Structure */ +typedef struct memory_attribute_struct +{ + uint32_t memId; + uint32_t regionCount; + mem_region_t *memRegions; + void *context; +} mem_attribute_t; + +/*! @brief Memory context structure */ +typedef struct memory_context_struct +{ + status_t (*flush)(mem_attribute_t *attr); + mem_attribute_t *attr; +} mem_context_t; + +/*! @brief Memory region interface structure */ +typedef struct api_memory_region_interface +{ + status_t (*init)(mem_attribute_t *attr); +#if ROM_API_HAS_FEATURE_MEM_READ + status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); +#endif + status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); + status_t (*fill)(mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern); + status_t (*flush)(mem_attribute_t *attr); + status_t (*erase)(mem_attribute_t *attr, uint32_t addr, uint32_t len); + status_t (*config)(mem_attribute_t *attr, uint32_t *buf); + status_t (*erase_all)(mem_attribute_t *attr); + status_t (*alloc_ctx)(arena_context_t *ctx, mem_attribute_t *attr, void *miscParams); +} api_memory_region_interface_t; + +/*! @brief Memory entry data structure */ +typedef struct memory_map_entry +{ + mem_attribute_t *memoryAttribute; + const api_memory_region_interface_t *memoryInterface; +} api_memory_map_entry_t; + +/*! @brief The API context structure */ +typedef struct api_core_context +{ + soc_mem_regions_t memRegions; + arena_context_t arenaCtx; + flash_config_t flashConfig; + flexspi_nor_config_t flexspinorCfg; + mem_context_t memCtx; + ldr_Context_v3_t *sbloaderCtx; + nboot_context_t *nbootCtx; + uint8_t *sharedBuf; + api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT]; +} api_core_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Perform the Sbloader runtime environment initialization + * This API is used for initializing the sbloader state machine before calling + * the api_sbloader_pump. This API should be called after the iap_api_init API. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Init(api_core_context_t *ctx); + +/*! + * @brief Handle the SB data stream + * This API is used for handling the secure binary(SB3.1 format) data stream, + * which is used for image update, lifecycle advancing, etc. + * This API should be called after the iap_api_init and api_sbloader_init APIs. + + * @param ctx Pointer to IAP API core context structure. + * @param data Pointer to source data that is the sb file buffer data. + * @param length The size of the process buffer data. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_Fail API execution failed. + */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length); + +/*! + * @brief Finish the sbloader handling + * The API is used for finalizing the sbloader operations. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Finalize(api_core_context_t *ctx); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_SBLOADER_H_ */ diff --git a/drivers/mcx_romapi/mem_interface/fsl_sbloader_v3.h b/drivers/mcx_romapi/mem_interface/fsl_sbloader_v3.h new file mode 100644 index 000000000..795d8f19e --- /dev/null +++ b/drivers/mcx_romapi/mem_interface/fsl_sbloader_v3.h @@ -0,0 +1,271 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SBLOADER_V3_H_ +#define FSL_SBLOADER_V3_H_ + +#include + +#include "fsl_nboot_hal.h" + +/*! @addtogroup sbloader */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define SB3_BYTES_PER_CHUNK 16 + +typedef uint8_t chunk_v3_t[SB3_BYTES_PER_CHUNK]; + +typedef struct _ldr_buf ldr_buf_t; + +struct _ldr_buf +{ + chunk_v3_t data; + uint32_t fillPosition; +}; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context_v3 ldr_Context_v3_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_v3_t)(ldr_Context_v3_t *content); + +/*! @brief sb3 section definitions */ +/*! @brief section type */ +typedef enum _sectionType +{ + kSectionNone = 0, /*!< end or invalid */ + kSectionDataRange = 1, + kSectionDiffUpdate = 2, + kSectionDDRConfig = 3, + kSectionRegister = 4, +} section_type_t; + +#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) /*!< bit 0 */ +#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK (0x2u) /*!< bit 1 */ + +/*! @brief section data range structure */ +typedef struct range_header +{ + uint32_t tag; + uint32_t startAddress; + uint32_t length; + uint32_t cmd; +} sb3_data_range_header_t; + +typedef struct range_header_expansion +{ + uint32_t memoryId; + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_data_range_expansion_t; + +typedef struct copy_memory_expansion +{ + uint32_t destAddr; + uint32_t memoryIdFrom; + uint32_t memoryIdTo; + uint32_t pad; +} sb3_copy_memory_expansion_t; + +typedef struct copy +{ + sb3_data_range_header_t header; + sb3_copy_memory_expansion_t expansion; +} sb3_copy_memory_t; + +typedef struct load_keyblob +{ + uint32_t tag; + uint16_t offset; + uint16_t keyWrapId; + uint32_t length; + uint32_t cmd; +} sb3_load_keyblob_t; + +typedef struct fill_memory_expansion +{ + uint32_t pattern; /*!< word to be used as pattern */ + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_fill_memory_expansion_t; + +typedef struct fill_memory +{ + sb3_data_range_header_t header; + sb3_fill_memory_expansion_t arg; +} sb3_fill_memory_t; + +typedef struct config_memory +{ + uint32_t tag; + uint32_t memoryId; + uint32_t address; /*!< address of config blob */ + uint32_t cmd; +} sb3_config_memory_t; + +enum +{ + kFwVerChk_Id_none = 0, + kFwVerChk_Id_nonsecure = 1, + kFwVerChk_Id_secure = 2, +}; + +typedef struct fw_ver_check +{ + uint32_t tag; + uint32_t version; + uint32_t id; + uint32_t cmd; +} sb3_fw_ver_check_t; + +/*! @brief sb3 DATA section header format */ +typedef struct section_header +{ + uint32_t sectionUid; + uint32_t sectionType; + uint32_t length; + uint32_t _pad; +} sb3_section_header_t; + +/*! @brief loader command enum */ +typedef enum _loader_command_sb3 +{ + kSB3_CmdInvalid = 0, + kSB3_CmdErase = 1, + kSB3_CmdLoad = 2, + kSB3_CmdExecute = 3, + kSB3_CmdCall = 4, + kSB3_CmdProgramFuse = 5, + kSB3_CmdProgramIFR = 6, + kSB3_CmdLoadCmac = 7, + kSB3_CmdCopy = 8, + kSB3_CmdLoadHashLocking = 9, + kSB3_CmdLoadKeyBlob = 10, + kSB3_CmdConfigMem = 11, + kSB3_CmdFillMem = 12, + kSB3_CmdFwVerCheck = 13, +} sb3_cmd_t; + +/*! @brief The all of the allowed command */ +#define SBLOADER_V3_CMD_SET_ALL \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdCall) | \ + (1u << kSB3_CmdProgramFuse) | (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | \ + (1u << kSB3_CmdConfigMem) | (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in ISP mode */ +#define SBLOADER_V3_CMD_SET_IN_ISP_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in recovery mode */ +#define SBLOADER_V3_CMD_SET_IN_REC_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) + +#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX)) + +/*! @brief Memory region definition. */ +typedef struct +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image. */ + kRomLoadImage = 2, /*!< Load SB file. */ + kRomOperationCount = 3, +} kb_operation_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct +{ + uint32_t version; /*!< Should be set to #kKbootApiVersion. */ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot. */ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*!< Settings for #kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*!< Settings for #kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context_v3 +{ + pLdrFnc_v3_t Action; /*!< pointer to loader action function */ + uint32_t block_size; /*!< size of each block in bytes */ + uint32_t block_data_size; /*!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES) */ + uint32_t block_data_total; /*!< data max size in bytes (block_size * data_size */ + uint32_t block_buffer_size; /*!< block0 and block size */ + uint32_t block_buffer_position; + uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES, + NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; /*! will be used for both block0 and blockx */ + uint32_t processedBlocks; + + uint8_t data_block_offset; /*! data block offset in a block. */ + bool in_data_block; /*!< in progress of handling a data block within a block */ + uint8_t *data_block; + uint32_t data_block_position; + + bool in_data_section; /*!< in progress of handling a data section within a data block */ + uint32_t data_section_handled; + sb3_section_header_t data_section_header; + + bool in_data_range; /*!< in progress of handling a data range within a data section */ + uint32_t data_range_handled; + uint32_t data_range_gap; + sb3_data_range_header_t data_range_header; + bool has_data_range_expansion; + sb3_data_range_expansion_t data_range_expansion; + + uint32_t commandSet; /*!< support command set during sb file handling */ + + uint32_t data_position; + uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; /*!< temporary data buffer */ + + kb_options_t fromAPI; /*!< options from ROM API */ +}; + +/*! @} */ + +#endif /* FSL_SBLOADER_V3_H_ */ diff --git a/drivers/mcx_romapi/mem_interface/src/fsl_mem_interface.c b/drivers/mcx_romapi/mem_interface/src/fsl_mem_interface.c new file mode 100644 index 000000000..b95b82c8a --- /dev/null +++ b/drivers/mcx_romapi/mem_interface/src/fsl_mem_interface.c @@ -0,0 +1,154 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_mem_interface.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.memInterface" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! @brief IAP API Interface structure */ +typedef struct iap_api_interface_struct +{ + standard_version_t version; /*!< IAP API version number. */ + status_t (*api_init)(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + status_t (*api_deinit)(api_core_context_t *coreCtx); + status_t (*mem_init)(api_core_context_t *ctx); + status_t (*mem_read)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint8_t *buf, uint32_t memoryId); + status_t (*mem_write)(api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId); + status_t (*mem_fill)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId); + status_t (*mem_flush)(api_core_context_t *ctx); + status_t (*mem_erase)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId); + status_t (*mem_config)(api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId); + status_t (*mem_erase_all)(api_core_context_t *ctx, uint32_t memoryId); + status_t (*sbloader_init)(api_core_context_t *ctx); + status_t (*sbloader_pump)(api_core_context_t *ctx, uint8_t *data, uint32_t length); + status_t (*sbloader_finalize)(api_core_context_t *ctx); +} iap_api_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const iap_api_interface_t *iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->version; +} + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_init(coreCtx, param); +} + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_deinit(coreCtx); +} + +/*! @brief Intialize the memory interface of the IAP API */ +status_t MEM_Init(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_init(coreCtx); +} + +/*! @brief Perform the memory write operation */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_write(coreCtx, start, lengthInBytes, buf, memoryId); +} + +/*! @brief Perform the Fill operation */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_fill(coreCtx, start, lengthInBytes, pattern, memoryId); +} + +/*! @brief Perform the Memory erase operation */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase(coreCtx, start, lengthInBytes, memoryId); +} +/*! @brief Perform the full Memory erase operation */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase_all(coreCtx, memoryId); +} + +/*! @brief Perform the Memory configuration operation */ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_config(coreCtx, config, memoryId); +} + +/*! @brief Perform the Memory Flush operation */ +status_t MEM_Flush(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_flush(coreCtx); +} + +/*! @brief Perform the Sbloader runtime environment initialization */ +status_t Sbloader_Init(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_init(ctx); +} + +/*! @brief Handle the SB data stream */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_pump(ctx, data, length); +} +/*! @brief Finish the sbloader handling */ +status_t Sbloader_Finalize(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_finalize(ctx); +} diff --git a/drivers/mcx_romapi/nboot/fsl_nboot.h b/drivers/mcx_romapi/nboot/fsl_nboot.h new file mode 100644 index 000000000..f1cca4da1 --- /dev/null +++ b/drivers/mcx_romapi/nboot/fsl_nboot.h @@ -0,0 +1,346 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_NBOOT_H_ +#define FSL_NBOOT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup nboot + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** @def NXPCLHASH_WA_SIZE_MAX + * @brief Define the max workarea size required for this component + */ +#define NXPCLHASH_WA_SIZE_MAX (128U + 64U) +#define NBOOT_ROOT_CERT_COUNT (4U) +#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL ((size_t)32U) ///< Size of RTF appendix to hash output buffer, in bytes + +#define NBOOT_KEYINFO_WORDLEN (23U) +#define NBOOT_CONTEXT_BYTELEN (192U + NXPCLHASH_WA_SIZE_MAX) +#define NBOOT_CONTEXT_WORDLEN (NBOOT_CONTEXT_BYTELEN / sizeof(uint32_t)) +typedef int romapi_status_t; + +/*! + * @brief NBOOT type for the root key usage + * + * This type defines the NBOOT root key usage; + * any other value means the root key is not valid (treat as if revoked). + */ +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0U) +#define kNBOOT_RootKeyUsage_DebugCA (0x1U) +#define kNBOOT_RootKeyUsage_ImageCA_FwCA (0x2U) +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA (0x3U) +#define kNBOOT_RootKeyUsage_ImageKey_FwKey (0x4U) +#define kNBOOT_RootKeyUsage_ImageKey (0x5U) +#define kNBOOT_RootKeyUsage_FwKey (0x6U) +#define kNBOOT_RootKeyUsage_Unused (0x7U) +typedef uint32_t nboot_root_key_usage_t; + +/*! + * @brief NBOOT type for the root key revocation + * + * This type defines the NBOOT root key revocation; + * any other value means the root key is revoked. + */ +#define kNBOOT_RootKey_Enabled (0xAAU) +#define kNBOOT_RootKey_Revoked (0xBBU) +typedef uint32_t nboot_root_key_revocation_t; + +/*! + * @brief NBOOT type specifying the elliptic curve to be used + * + * This type defines the elliptic curve type and length + */ +#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01U) +#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02U) +typedef uint32_t nboot_root_key_type_and_length_t; + +/*! @brief Enumeration for SoC Lifecycle. */ +#define nboot_lc_nxpBlank (0xFFFF0000U) +#define nboot_lc_nxpFab (0xFFFE0001U) +#define nboot_lc_nxpDev (0xFF0300FCU) +#define nboot_lc_nxpProvisioned (0xFFFC0003U) +#define nboot_lc_oemOpen (0xFFFC0003U) +#define nboot_lc_oemSecureWorld (0xFFF80007U) +#define nboot_lc_oemClosed (0xFFF0000FU) +#define nboot_lc_oemLocked (0xFF3000CFU) +#define nboot_lc_oemFieldReturn (0xFFE0001FU) +#define nboot_lc_nxpFieldReturn (0xFF80007FU) +#define nboot_lc_shredded (0xFF0000FFU) +typedef uint32_t nboot_soc_lifecycle_t; + +/*! @brief Type for nboot status codes */ +typedef uint32_t nboot_status_t; + +/*! @brief Type for nboot protected status codes */ +typedef uint64_t nboot_status_protected_t; + +/*! + * @brief nboot status codes. + */ +enum +{ + kStatus_NBOOT_Success = 0x5A5A5A5AU, /*!< Operation completed successfully. */ + kStatus_NBOOT_Fail = 0x5A5AA5A5U, /*!< Operation failed. */ + kStatus_NBOOT_InvalidArgument = 0x5A5AA5F0U, /*!< Invalid argument passed to the function. */ + kStatus_NBOOT_RequestTimeout = 0x5A5AA5E1U, /*!< Operation timed out. */ + kStatus_NBOOT_KeyNotLoaded = 0x5A5AA5E2U, /*!< The requested key is not loaded. */ + kStatus_NBOOT_AuthFail = 0x5A5AA5E4U, /*!< Authentication failed. */ + kStatus_NBOOT_OperationNotAvaialable = 0x5A5AA5E5U, /*!< Operation not available on this HW. */ + kStatus_NBOOT_KeyNotAvailable = 0x5A5AA5E6U, /*!< Key is not avaialble. */ + kStatus_NBOOT_IvCounterOverflow = 0x5A5AA5E7U, /*!< Overflow of IV counter (PRINCE/IPED). */ + kStatus_NBOOT_SelftestFail = 0x5A5AA5E8U, /*!< FIPS self-test failure. */ + kStatus_NBOOT_InvalidDataFormat = 0x5A5AA5E9U, /*!< Invalid data format for example antipole */ + kStatus_NBOOT_IskCertUserDataTooBig = + 0x5A5AA5EAU, /*!< Size of User data in ISK certificate is greater than 96 bytes */ + kStatus_NBOOT_IskCertSignatureOffsetTooSmall = + 0x5A5AA5EBU, /*!< Signature offset in ISK certificate is smaller than expected */ + kStatus_NBOOT_MemcpyFail = 0x5A5A845AU, /*!< Unexpected error detected during nboot_memcpy() */ +}; + +/*! @brief Data structure holding secure counter value used by nboot library */ +typedef struct _nboot_secure_counter +{ + uint32_t sc; + uint32_t scAp; +} nboot_secure_counter_t; + +/*! + * @brief NBOOT context type + * + * This type defines the NBOOT context + * + */ +typedef struct _nboot_context +{ + uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */ + uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header(). + SB3 related flag set by NBOOT in case the nboot_sb3_load_block() + provides plain data to output buffer (for processing by ROM SB3 loader */ + uint32_t timeout; /*!< timeout value for css operation. In case it is 0, infinite wait is performed */ + uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */ + uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */ + uint32_t uuid[4]; /*!< holds UUID value from NMPA */ + uint32_t prngReadyFlag; /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to + generate rnd number */ + uint32_t multipartMacBuffer[1024 / sizeof(uint32_t)]; + uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by + nboot_tp_isp_gen_oem_master_share() */ + uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */ + nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */ + uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL / sizeof(uint32_t)]; + uint32_t imageHash[48 / sizeof(uint32_t)]; + uint32_t authStatus; +} nboot_context_t; + +/*! + * @brief NBOOT type for the root of trust parameters + * + * This type defines the NBOOT root of trust parameters + * + */ +typedef struct _nboot_rot_auth_parms +{ + /* trusted information originated from CFPA */ + nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM + information in CFPA: ROTKH_REVOKE */ + uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */ + + /* trusted information originated from CMPA */ + uint32_t soc_rkh[12]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash of hashes) */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */ + + uint32_t soc_numberOfRootKeys; /*!< unsigned int, between minimum = 1 and maximum = 4; */ + nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /*!< CMPA */ + nboot_root_key_type_and_length_t + soc_rootKeyTypeAndLength; /*!< static selection between ECDSA P-256 or ECDSA P-384 based root keys */ + + /* trusted information originated from OTP fuses */ + nboot_soc_lifecycle_t soc_lifecycle; +} nboot_rot_auth_parms_t; + +/*! + * @brief manifest loading parameters + * + * This type defines the NBOOT SB3.1 manifest loading parameters + * + */ +typedef struct _nboot_sb3_load_manifest_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ + uint8_t pckBlob[48]; +} nboot_sb3_load_manifest_parms_t; + +/*! + * @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. + * Shall be read from SoC trusted NVM or SoC fuses. + */ +typedef struct _nboot_img_auth_ecdsa_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ +} nboot_img_auth_ecdsa_parms_t; + +/*! @brief Data structure holding input arguments for CMAC authentication */ +typedef struct _nboot_cmac_authenticate_parms +{ + uint32_t expectedMAC[4]; /*!< expected MAC result */ +} nboot_img_authenticate_cmac_parms_t; + +/*! + * @brief Boolean type for the NBOOT functions + * + * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks + */ +typedef enum _nboot_bool +{ + kNBOOT_TRUE = 0x3C5AC33CU, /*!< Value for TRUE. */ + kNBOOT_TRUE256 = 0x3C5AC35AU, /*!< Value for TRUE when P256 was used to sign the image. */ + kNBOOT_TRUE384 = 0x3C5AC3A5U, /*!< Value for TRUE when P384 was used to sign the image. */ + kNBOOT_FALSE = 0x5AA55AA5U, /*!< Value for FALSE. */ + kNBOOT_OperationAllowed = 0x3c5a33ccU, + kNBOOT_OperationDisallowed = 0x5aa5cc33U, +} nboot_bool_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief This API function is used to generate random number with specified length. + * + * @param output Pointer to random number buffer + * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> + * + * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen); + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextInit(nboot_context_t *context); + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context); + +/*! + * @brief Verify NBOOT SB3.1 manifest (header message) + * + * This function verifies the NBOOT SB3.1 manifest (header message), initializes + * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block + * function. The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. Please note that this API is intended to be used only by users who needs to split + * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. + * For regular SB3.1 processing, please use API described in chapter ��SBloader APIs��. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * @param manifest Pointer to the input manifest buffer + * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms); + +/*! + * @brief Verify NBOOT SB3.1 block + * + * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * Please note that this API is intended to be used only by users who needs to split FW update process + * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, + * please use API described in chapter ��SBloader APIs��. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the input SB3.1 data block + * + * @retval #kStatus_NBOOT_Success successfully finished + * @retval #kStatus_NBOOT_Fail occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block); + +/*! + * @brief This function authenticates image with asymmetric cryptography. + * The NBOOT context has to be initialized by the function nboot_context_init + * before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + * After the function returns, the value will be set to kNBOOT_TRUE when the image is + * authentic. Any other value means the authentication does not pass. + * + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, + * it could also mean transient error caused by short time environmental conditions. + */ +nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms); + +/*! + * @brief This function calculates the CMAC over the given image and compares it to the expected value. + * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. + * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + After the function returns, the value will be set to + * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. + The data structure shall be correctly filled before the function call. + * + * @retval kStatus_NBOOT_Success + * @retval kStatus_NBOOT_Fail + */ +nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_NBOOT_H_ */ diff --git a/drivers/mcx_romapi/nboot/fsl_nboot_hal.h b/drivers/mcx_romapi/nboot/fsl_nboot_hal.h new file mode 100644 index 000000000..79e0dd490 --- /dev/null +++ b/drivers/mcx_romapi/nboot/fsl_nboot_hal.h @@ -0,0 +1,231 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_NBOOT_HAL_H_ +#define FSL_NBOOT_HAL_H_ + +#include "fsl_nboot.h" + +/*! @addtogroup nbot_hal */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The size of the UUID. */ +#define NBOOT_UUID_SIZE_IN_WORD (4) +#define NBOOT_UUID_SIZE_IN_BYTE (NBOOT_UUID_SIZE_IN_WORD * 4) + +/*! @brief The size of the PUF activation code. */ +#define NBOOT_PUF_AC_SIZE_IN_BYTE (996) +/*! @brief The size of the PUF key code. */ +#define NBOOT_PUF_KC_SIZE_IN_BYTE (84) + +/*! @brief The size of the key store. */ +#define NBOOT_KEY_STORE_SIZE_IN_BYTE (NBOOT_PUF_AC_SIZE_IN_BYTE + 8) + +/*! @brief The size of the root of trust key table hash. */ +#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12) +#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4) + +/*! @brief The size of the blob with Key Blob. */ +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384) + +/*! @brief The mask of the value of the debug state . */ +#define NBOOT_DBG_AUTH_DBG_STATE_MASK (0x0000FFFFu) +/*! @brief The shift inverted value of the debug state. */ +#define NBOOT_DBG_AUTH_DBG_STATE_SHIFT (16) +/*! @brief The value with all debug feature disabled. */ +#define NBOOT_DBG_AUTH_DBG_STATE_ALL_DISABLED (0xFFFF0000u) + +#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u) + +#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES (48u) +#define NBOOT_EC_COORDINATE_MAX_SIZE NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES + +/* SB3.1 */ +#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES (256u) +#define NBOOT_SB3_BLOCK_HASH256_SIZE_IN_BYTES (32u) +#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES (48u) + +/*! + * @brief NBOOT type for a timestamp + * + * This type defines the NBOOT timestamp + * + */ +typedef uint32_t nboot_timestamp_t[2]; + +/*! + * @brief NBOOT SB3.1 header type + * + * This type defines the header used in the SB3.1 manifest + * + */ +typedef struct _nboot_sb3_header +{ + uint32_t magic; /*!< offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */ + uint32_t formatVersion; /*!< offset 0x04: (major = 3, minor = 1); The format version determines the manifest + (block0) size. */ + uint32_t flags; /*!< offset 0x08: not defined yet, keep zero for future compatibility */ + uint32_t blockCount; /*!< offset 0x0C: Number of blocks not including the manifest (block0). */ + uint32_t + blockSize; /*!< offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */ + nboot_timestamp_t timeStamp; /*!< offset 0x14: 64-bit value used as key derivation data. */ + uint32_t firmwareVersion; /*!< offset 0x1c: Version number of the included firmware */ + uint32_t imageTotalLength; /*!< offset 0x20: Total manifest length in bytes, including signatures etc. */ + uint32_t imageType; /*!< offset 0x24: image type and flags */ + uint32_t certificateBlockOffset; /*!< offset 0x28: Offset from start of header block to the certificate block. */ + uint8_t description[16]; /*!< offset 0x32: This field provides description of the file. It is an arbitrary + string injected by the signing tool, which helps to identify the file. */ +} nboot_sb3_header_t; + +/*! + * @brief NBOOT type for the header of the certificate block + * + * This type defines the NBOOT header of the certificate block, it is part of the nboot_certificate_block_t + * + */ +typedef struct _nboot_certificate_header_block +{ + uint32_t magic; /*!< magic number. */ + uint32_t formatMajorMinorVersion; /*!< format major minor version */ + uint32_t certBlockSize; /*!< Size of the full certificate block */ +} nboot_certificate_header_block_t; + +typedef uint8_t nboot_ctrk_hash_t[NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES]; + +/*! + * @brief NBOOT type for the hash table + * + * This type defines the NBOOT hash table + * + */ +typedef struct _nboot_ctrk_hash_table +{ + nboot_ctrk_hash_t ctrkHashTable[NBOOT_ROOT_CERT_COUNT]; +} nboot_ctrk_hash_table_t; + +/*! + * @brief NBOOT type for an ECC coordinate + * + * This type defines the NBOOT ECC coordinate type + * + */ +typedef uint8_t + nboot_ecc_coordinate_t[NBOOT_EC_COORDINATE_MAX_SIZE]; /*!< ECC point coordinate, up to 384-bits. big endian. */ + +/*! + * @brief NBOOT type for an ECC point + * + * This type defines the NBOOT ECC point type + */ +typedef struct +{ + nboot_ecc_coordinate_t x; /*!< x portion of the ECDSA public key, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t y; /*!< y portion of the ECDSA public key, up to 384-bits. big endian. */ +} nboot_ecdsa_public_key_t; + +/*! + * @brief NBOOT type for the root certificate block + * + * This type defines the NBOOT root certificate block, it is part of the nboot_certificate_block_t + */ +typedef struct _nboot_root_certificate_block +{ + uint32_t flags; /*!< root certificate flags */ + nboot_ctrk_hash_table_t ctrkHashTable; /*!< hash table */ + nboot_ecdsa_public_key_t rootPublicKey; /*!< root public key */ +} nboot_root_certificate_block_t; + +/*! + * @brief NBOOT type for an ECC signature + * + * This type defines the NBOOT ECC signature type + */ +typedef struct +{ + nboot_ecc_coordinate_t r; /*!< r portion of the ECDSA signature, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t s; /*!< s portion of the ECDSA signature, up to 384-bits. big endian. */ +} nboot_ecdsa_signature_t; + +/*! + * @brief NBOOT type for the isk block + * + * This type defines the constant length part of an NBOOT isk block + */ +typedef struct +{ + uint32_t signatureOffset; /*!< Offset of signature in ISK block. */ + uint32_t constraints; /*!< Version number of signing certificate. */ + uint32_t iskFlags; /*!< Reserved for definiton of ISK certificate flags. */ + nboot_ecdsa_public_key_t + iskPubKey; /*!< Public key of signing certificate. Variable length; only used to determine start address*/ + nboot_ecdsa_public_key_t userData; /*!< Space for at lest one addition public key*/ + nboot_ecdsa_signature_t iskSign; /*!< ISK signature*/ +} nboot_isk_block_t; + +/*! + * @brief NBOOT type for the certificate block + * + * This type defines the constant length part of an NBOOT certificate block + */ +typedef struct _nboot_certificate_block +{ + nboot_certificate_header_block_t header; + nboot_root_certificate_block_t rootCertBlock; /*! Details of selected root certificate (root certificate which will + be used for ISK signing/SB3 header signing) */ + nboot_isk_block_t iskBlock; +} nboot_certificate_block_t; + +#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES \ + (sizeof(nboot_sb3_header_t) + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + sizeof(nboot_certificate_block_t) + \ + NBOOT_EC_COORDINATE_MAX_SIZE * 2) +#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES \ + (4 /* blockNumber */ + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + NBOOT_SB3_CHUNK_SIZE_IN_BYTES) + +/*! @brief The size of the DICE certificate. */ +#define NBOOT_DICE_CSR_SIZE_IN_WORD (36) +#define NBOOT_DICE_CSR_SIZE_IN_BYTES (NBOOT_DICE_CSR_SIZE_IN_WORD * 4) + +/*! @brief The physical address to put the DICE certificate. */ +#define NBOOT_DICE_CSR_ADDRESS (0x30000000u) + +/*! @brief The offset for the PRCINE/IPED erase region return by nboot mem checker. */ +#define NBOOT_IPED_IV_OFFSET (3U) + +#define NBOOT_IMAGE_CMAC_UPDATE_NONE (0u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX0 (1u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX1 (2u) +#define NBOOT_IMAGE_CMAC_UPDATE_BOTH (3u) +#define NBOOT_IMAGE_CMAC_UPDATE_MASK (3u) + +#define NBOOT_CMPA_CMAC_UPDATE_MASK (0x1Cu) +#define NBOOT_CMPA_CMAC_UPDATE_SHIFT (0x2u) + +#define NBOOT_CMPA_UPDATE_CMAC_PFR (0x2u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_SECURE (0x3u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_CLOSE (0x5u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_LOCKED (0x6u) + +/*! @brief Algorithm used for nboot HASH operation */ +typedef enum _nboot_hash_algo_t +{ + kHASH_Sha1 = 1, /*!< SHA_1 */ + kHASH_Sha256 = 2, /*!< SHA_256 */ + kHASH_Sha512 = 3, /*!< SHA_512 */ + kHASH_Aes = 4, /*!< AES */ + kHASH_AesIcb = 5, /*!< AES_ICB */ +} nboot_hash_algo_t; + +/*! @} */ + +#endif /*FSL_NBOOT_HAL_H_ */ diff --git a/drivers/mcx_romapi/nboot/src/fsl_nboot.c b/drivers/mcx_romapi/nboot/src/fsl_nboot.c new file mode 100644 index 000000000..909be4ae3 --- /dev/null +++ b/drivers/mcx_romapi/nboot/src/fsl_nboot.c @@ -0,0 +1,212 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_nboot.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nboot" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/** + * @brief Image authentication operations. + * + * These abstract interface are used for image verification operations. + */ +typedef struct +{ + romapi_status_t (*romapi_rng_generate_random)(uint8_t *output, size_t outputByteLen); + nboot_status_t (*nboot_context_init)(nboot_context_t *context); + nboot_status_t (*nboot_context_deinit)(nboot_context_t *context); + nboot_status_protected_t (*nboot_sb3_load_manifest)(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms); + nboot_status_protected_t (*nboot_sb3_load_block)(nboot_context_t *context, uint32_t *block); + nboot_status_protected_t (*nboot_img_authenticate_ecdsa)(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms); + nboot_status_protected_t (*nboot_img_authenticate_cmac)(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms); +} nboot_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const nboot_interface_t *nbootDriver; /*!< nBoot driver API */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const uint32_t iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief This API function is used to generate random number with specified length. + * + * @param output Pointer to random number buffer + * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> + * + * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->romapi_rng_generate_random(output, outputByteLen); +} + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextInit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_init(context); +} + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_deinit(context); +} +/*! + * @brief Verify NBOOT SB3.1 manifest (header message) + * + * This function verifies the NBOOT SB3.1 manifest (header message), initializes + * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block + * function. The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. Please note that this API is intended to be used only by users who needs to split + * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. + * For regular SB3.1 processing, please use API described in chapter SBloader APIs. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * @param manifest Pointer to the input manifest buffer + * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb3_load_manifest(context, manifest, parms); +} + +/*! + * @brief Verify NBOOT SB3.1 block + * + * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * Please note that this API is intended to be used only by users who needs to split FW update process + * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, + * please use API described in chapter SBloader APIs. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the input SB3.1 data block + * + * @retval #kStatus_NBOOT_Success successfully finished + * @retval #kStatus_NBOOT_Fail occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb3_load_block(context, block); +} + +/*! + * @brief This function authenticates image with asymmetric cryptography. + * The NBOOT context has to be initialized by the function nboot_context_init + * before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + * After the function returns, the value will be set to kNBOOT_TRUE when the image is + * authentic. Any other value means the authentication does not pass. + * + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, + * it could also mean transient error caused by short time environmental conditions. + */ +nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_img_authenticate_ecdsa(context, imageStartAddress, + isSignatureVerified, parms); +} + +/*! + * @brief This function calculates the CMAC over the given image and compares it to the expected value. + * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. + * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + After the function returns, the value will be set to + * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. + The data structure shall be correctly filled before the function call. + * + * @retval kStatus_NBOOT_Success + * @retval kStatus_NBOOT_Fail + */ +nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_img_authenticate_cmac(context, imageStartAddress, + isSignatureVerified, parms); +} diff --git a/drivers/mcx_romapi/runbootloader/fsl_runbootloader.h b/drivers/mcx_romapi/runbootloader/fsl_runbootloader.h new file mode 100644 index 000000000..de0ed4a9c --- /dev/null +++ b/drivers/mcx_romapi/runbootloader/fsl_runbootloader.h @@ -0,0 +1,72 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_RUN_BOOTLOADER_H_ +#define FSL_RUN_BOOTLOADER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup runbootloader + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | + | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ + +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void bootloader_user_entry(void *arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_RUN_BOOTLOADER_H_ */ diff --git a/drivers/mcx_romapi/runbootloader/src/fsl_runbootloader.c b/drivers/mcx_romapi/runbootloader/src/fsl_runbootloader.c new file mode 100644 index 000000000..ebfe866f1 --- /dev/null +++ b/drivers/mcx_romapi/runbootloader/src/fsl_runbootloader.c @@ -0,0 +1,52 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_runbootloader.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.runBootloader" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t reserved2; /*!< reserved*/ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +void bootloader_user_entry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} diff --git a/drivers/mcx_spc/fsl_spc.c b/drivers/mcx_spc/fsl_spc.c new file mode 100644 index 000000000..fa09ae1f4 --- /dev/null +++ b/drivers/mcx_spc/fsl_spc.c @@ -0,0 +1,1753 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_spc" +#endif + +/* + * $Coverage Justification Reference$ + * + * $Justification spc_c_ref_1$ + * The SPC busy status flag is too short to get coverage data. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets selected power domain's requested low power mode. + * + * param base SPC peripheral base address. + * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t. + * + * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + + uint32_t val; + + val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); + return (spc_power_domain_low_power_mode_t)val; +} + +/*! + * brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * param base SPC peripheral base address. + * return Current isolation status for each power domains. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base) +{ + uint32_t reg; + + reg = base->SC; + return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); +} + +/*! + * brief Configs Low power request output pin. + * + * This function configs the low power request output pin + * + * param base SPC peripheral base address. + * param config Pointer the spc_LowPower_Request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = base->LPREQ_CFG; + reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); + + if (config->enable) + { + reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | + SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override)); + } + else + { + reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; + } + + base->LPREQ_CFG = reg; +} + +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} + +/*! + * brief Set SRAM operate voltage. + * + * param base SPC peripheral base address. + * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= SPC_SRAMCTL_VSM(config->operateVoltage); + + base->SRAMCTL = reg; + + if (config->requestVoltageUpdate) + { + base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK; + while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL) + { + /* Wait until acknowledged */ + ; + } + base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK; + } +} + +/*! + * brief Configs Bandgap mode in Active mode. + * + * note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * disable Bandgap in active mode + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * retval kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->ACTIVE_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = SPC_GetActiveModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + } + + reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK; + reg |= SPC_ACTIVE_CFG_BGMODE(mode); + + base->ACTIVE_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs Bandgap mode in Low Power mode. + * + * This function configs Bandgap mode in Low Power mode. + * IF user wants to disable Bandgap while keeping any of the Regulator in Normal Driver Strength + * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode + * will be set as Bandgap Enabled with Buffer Disabled. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->LP_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == + SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + reg &= ~SPC_LP_CFG_BGMODE_MASK; + reg |= SPC_LP_CFG_BGMODE(mode); + base->LP_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs CORE voltage detect options. + * + * This function configs CORE voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); + + base->VD_CORE_CFG = reg; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * brief Enables the Core High Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * retval kStatus_Success Enable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + + return status; +} + + +/*! + * brief Enables the Core High Voltage Detector in Low Power mode. + * + * note If the CORE_LDO high voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each regulator + * must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core Low Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core Low Voltage Detector in Low Power mode. + * + * note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_SYS_CFG; + /* Before changing voltage level, must disable low voltage detect interrupt and reset. */ + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); + reg |= SPC_VD_SYS_CFG_LVSEL(level); + + base->VD_SYS_CFG = reg; +} + +/*! + * brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U); + + base->VD_SYS_CFG = reg; + + /* Set trip voltage level. */ + SPC_SetSystemVDDLowVoltageLevel(base, config->level); +} + +/*! + * brief Enables the System High Voltage Detector in Active mode. + * + * note If the System_LDO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of + * each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * retval kStatus_Success Enable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System Low Voltage Detector in Active mode. + * + * note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * retval kStatus_Success Enable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System High Voltage Detector in Low Power mode. + * + * note If the System_LDO high voltage detect is enabled in low power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System Low Voltage Detector in Low Power mode. + * + * note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK; + } + + return status; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_IO_CFG; + + base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK); + reg |= SPC_VD_IO_CFG_LVSEL(level); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_IO_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + /* Set trip voltage level. */ + SPC_SetIOVDDLowVoltageLevel(base, config->level); + + reg = base->VD_IO_CFG; + reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK); + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Enables the IO High Voltage Detector in Active mode. + * + * note If the IO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * retval kStatus_Success Enable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO Low Voltage Detector in Active mode. + * + * note If the IO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO High Voltage Detector in Low Power mode. + * + * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO Low Voltage Detector in Low Power mode. + * + * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * param base SPC peripheral base address. + * param lowPowerIsoMask The mask of external domains isolate enable during low power mode. + * param IsoMask The mask of external domains isolate. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask) +{ + uint32_t reg = 0UL; + + reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask); + base->EVD_CFG = reg; +} + +/*! + * brief Configs Core LDO VDD Regulator in Active mode. + * + * note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + * note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. + * + * retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not + * set to low. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (SPC_GetActiveModeCoreLDODriveStrength(base) == kSPC_CoreLDO_LowDriveStrength) && (option->CoreLDOVoltage != SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* In active mode, CORE_LDO voltage level should only be changed when the CORE_LDO is in Normal strength. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (SPC_GetActiveModeCoreLDODriveStrength(base) == kSPC_CoreLDO_NormalDriveStrength)) + { + /* Change Voltage level firstly. */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + /* Then change drive strength. */ + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + } + + if (option->CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* Change drive strength firstly. */ + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + /* Then change Voltage level. */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } +#else /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | + SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | + SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength is set as Normal. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. + * retval kStatus_Success Config Core LDO regulator in power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in low powermode is wrong. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) +{ + status_t status = kStatus_Success; + spc_core_ldo_drive_strength_t activeCoreLdoDS = kSPC_CoreLDO_NormalDriveStrength; + + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + activeCoreLdoDS = SPC_GetActiveModeCoreLDODriveStrength(base); +#endif /* (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) */ + + if ((option->CoreLDODriveStrength == activeCoreLdoDS) && (option->CoreLDOVoltage != SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* If attemp to set to same drive strength as active mode, voltage level must same in active mode and low power mode. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (option->CoreLDOVoltage != SPC_GetLowPowerCoreLDOVDDVoltageLevel(base))) + { + /* Can change core VDD levels for the LDO_CORE low power regulator only when the LDO_CORE is work as normal drive strength. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) + { + status = SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((SPC_GetLowPowerCoreLDOVDDDriveStrength(base) == kSPC_CoreLDO_NormalDriveStrength) && ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* If LDO_CORE VDD Drive strength is set as normal, the voltage level in active mode and low power mode must be same. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((SPC_GetLowPowerCoreLDOVDDDriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) && ((uint8_t)SPC_GetLowPowerCoreLDOVDDVoltageLevel(base) != (uint8_t)voltageLevel)) + { + /* Voltage level for the LDO_CORE low power regulatorcan only be changed when core LDO work as normal drive strength. */ + return kStatus_SPC_CORELDOVoltageSetFail; + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | + SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enable the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option) +{ + assert(option != NULL); + + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + if (status == kStatus_Success) + { + status = SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + } + + base->ACTIVE_CFG = (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * param base SPC peripheral base address. + * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + else + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * brief Configs DCDC VDD Regulator in Active mode. + * + * Before switching DCDC drive strength from low to normal, the DCDC voltage level should be configured back to + * what it was before switching to low drive strength. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * retval kStatus_Success Config DCDC regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) +{ + assert(option != NULL); + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) + { + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_LowDriveStrength) + { + /*If enabled LVDs or HVDs, and attempt to specify low drive strength, + SPC will ignore the attempt. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_DCDCLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs DCDC VDD Regulator in Low power modes. + * + * This function configs DCDC VDD Regulator in Low Power modes. + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode + * will be ignored. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * retval kStatus_Success Config DCDC regulator in low power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + if (status == kStatus_Success) + { + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_LowDriveStrength) + { + /*If enabled LVDs or HVDs, and attempt to specify low drive strength, + SPC will ignore the attempt. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_DCDCLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Config DCDC Burst options + * + * param base SPC peripheral base address. + * param config Pointer to spc_DCDC_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) +{ + assert(config != NULL); + uint32_t reg; + reg = base->DCDC_CFG; + reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); + reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); + base->DCDC_CFG = reg; + + /* Clear DCDC burst acknowledge flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->sofwareBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0U) + { + } + /* DCDC burst request has completed and acknowledged, need to clear this flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + } +} + +/*! + * brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * param base SPC peripheral base address. + * param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) +{ + uint32_t reg; + + reg = base->DCDC_BURST_CFG; + reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK; + reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count); + + base->DCDC_BURST_CFG = reg; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + +/*! + * brief Configs regulators in Active mode. + * + * This function provides the method to config all on-chip regulators in active mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_active_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Active power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config) +{ + assert(config != NULL); + + status_t status; + bool bandgapConfigured = false; + spc_bandgap_mode_t curBandgapMode = SPC_GetActiveModeBandgapMode(base); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (((config->DCDCOption.DCDCDriveStrength) == kSPC_DCDC_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (((config->CoreLDOOption.CoreLDODriveStrength) == kSPC_CoreLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if (((config->SysLDOOption.SysLDODriveStrength) == kSPC_SysLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + /* Must specify the same level for both DCDC and CORE LDO, even if LDO_CORE is off. */ + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if (SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) < (config->CoreLDOOption.CoreLDOVoltage)) + { + /* If want to switch to higher voltage level. */ + + /* Set DCDC configuration previously. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + if (status == kStatus_Success) + { + /* Configure CORE LDO after DCDC is configured successfully. */ + status = SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + } + else + { + return status; + } + } + else + { + /* If want to switch to lower/same voltage level. */ + + /* Set LDO configuration previously. */ + status = SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (status == kStatus_Success) + { + /* Configure DCDC after CORE_LDO is configured successfully. */ + status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); + } + else + { + return status; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + } + + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + status = SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + if (status == kStatus_Success) + { + if (bandgapConfigured == false) + { + status = SPC_SetActiveModeBandgapModeConfig(base, config->bandgapMode); + } +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + if (status == kStatus_Success) + { + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + } + } + return status; +} + +/*! + * brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Low power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + bool bandgapConfigured = false; + spc_bandgap_mode_t curBandgapMode = SPC_GetActiveModeBandgapMode(base); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (((config->DCDCOption.DCDCDriveStrength) == kSPC_DCDC_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if (((config->CoreLDOOption.CoreLDODriveStrength) == kSPC_CoreLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if (((config->SysLDOOption.SysLDODriveStrength) == kSPC_SysLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + /* Must specify the same level for both DCDC and CORE LDO, even if LDO_CORE is off. */ + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + status = SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + status = SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + status = SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + if (status == kStatus_Success) + { + if (bandgapConfigured == false) + { + status = SPC_SetLowPowerModeBandgapmodeConfig(base, config->bandgapMode); + } + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBufferMode(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + } + } + } + } + + return status; +} diff --git a/drivers/mcx_spc/fsl_spc.h b/drivers/mcx_spc/fsl_spc.h new file mode 100644 index 000000000..356283850 --- /dev/null +++ b/drivers/mcx_spc/fsl_spc.h @@ -0,0 +1,2223 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_spc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPC driver version 2.2.1. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +#define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL +#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL +#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL + +#define SPC_EVD_CFG_REG_EVDISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) + +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif + +/*! + * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. + */ +enum +{ + kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any + type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be + ignored for LVD/HVD enabled. */ + kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive + strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive + voltage failed for SYS LDO HVD must be disabled. */ + kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ + kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ + kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set fail. */ + kStatus_SPC_BandgapModeWrong = MAKE_STATUS(kStatusGroup_SPC, 6U), /*!< Selected Bandgap Mode wrong. */ +}; + +/*! + * @brief Voltage Detect Status Flags. + */ +enum _spc_voltage_detect_flags +{ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +}; + +/*! + * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. + */ +enum _spc_power_domains +{ + kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */ + kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */ +}; + +/*! + * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes. + * @anchor spc_analog_module_control + */ +enum _spc_analog_module_control +{ + kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ + kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ + kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ + kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ + kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ + kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ + kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ + kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ + kSPC_controlCmp2 = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */ + kSPC_controlCmp0Dac = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */ + kSPC_controlCmp1Dac = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */ + kSPC_controlCmp2Dac = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */ + kSPC_controlAllModules = 0x770773UL, /*!< Enable/disable all modules in active or low-power modes. */ +}; + +/*! + * @brief The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip's RM + * for details. + */ +typedef enum _spc_power_domain_id +{ + kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */ + kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */ +} spc_power_domain_id_t; + +/*! + * @brief The enumeration of Power domain's low power mode. + */ +typedef enum _spc_power_domain_low_power_mode +{ + kSPC_SleepWithSYSClockRunning = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */ + kSPC_DeepSleepWithSysClockOff = 1U, /*!< Power domain request deep sleep mode with system clock off. */ + kSPC_PowerDownWithSysClockOff = 2U, /*!< Power domain request power down mode with system clock off. */ + kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */ +} spc_power_domain_low_power_mode_t; + +/*! + * @brief SPC low power request output pin polarity. + */ +typedef enum _spc_lowPower_request_pin_polarity +{ + kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Reqest Pin. */ + kSPC_LowTruePolarity = 0x1U, /*!< Control the Low Polarity of the Low Power Reqest Pin. */ +} spc_lowpower_request_pin_polarity_t; + +/*! + * @brief SPC low power request output override. + */ +typedef enum _spc_lowPower_request_output_override +{ + kSPC_LowPowerRequestNotForced = 0x0U, /*!< Not Forced. */ + kSPC_LowPowerRequestReserved = 0x1U, /*!< Reserved. */ + kSPC_LowPowerRequestForcedLow = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */ + kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */ +} spc_lowpower_request_output_override_t; + +/*! + * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_bandgap_mode +{ + kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ + kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ + kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ +} spc_bandgap_mode_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + */ +typedef enum _spc_dcdc_voltage_level +{ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC VDD Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Safe-Mode Voltage(1.2V). */ +} spc_dcdc_voltage_level_t; + +/*! + * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + */ +typedef enum _spc_dcdc_drive_strength +{ + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC VDD Regulator Drive Strength set to Pulse Refresh Mode, + * This enum member is only useful for Low Power Mode config, please + * note that pluse refresh mode is invalid in SLEEP mode. + */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC VDD regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC VDD regulator Drive Strength set to Normal. */ +} spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief SYS LDO regulator voltage level enumeration in Active mode. + */ +typedef enum _spc_sys_ldo_voltage_level +{ + kSPC_SysLDO_NormalVoltage = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */ + kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */ +} spc_sys_ldo_voltage_level_t; + +/*! + * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_sys_ldo_drive_strength +{ + kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ + kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ +} spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +/*! + * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_core_ldo_voltage_level +{ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to Under Drive Voltage, please note that + underDrive voltage only useful in low power modes. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ +} spc_core_ldo_voltage_level_t; + +/*! + * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode. + */ +typedef enum _spc_core_ldo_drive_strength +{ + kSPC_CoreLDO_LowDriveStrength = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */ + kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */ +} spc_core_ldo_drive_strength_t; + +/*! + * @brief System/IO VDD Low-Voltage Level Select. + */ +typedef enum _spc_low_voltage_level_select +{ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< Trip point set to Normal level. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< Trip point set to Safe level. */ +} spc_low_voltage_level_select_t; + +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; + +/*! + * @brief The list of the operating voltage for the SRAM's read/write timing margin. + */ +typedef enum _spc_sram_operate_voltage +{ + kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */ + kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */ + kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ +} spc_sram_operate_voltage_t; + +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; + +typedef struct _spc_sram_voltage_config +{ + spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's + read/write timing margin. */ + bool requestVoltageUpdate; /*!< Used to control whether request an SRAM trim value change. */ +} spc_sram_voltage_config_t; + +/*! + * @brief Low Power Request output pin configuration. + */ +typedef struct _spc_lowpower_request_config +{ + bool enable; /*!< Low Power Request Output enable. */ + spc_lowpower_request_pin_polarity_t polarity; /*!< Low Power Request Output pin polarity select. */ + spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */ +} spc_lowpower_request_config_t; + +/*! + * @brief Core LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +} spc_active_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_sys_ldo_option +{ + spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Active mode. */ +} spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Active mode. + */ +typedef struct _spc_active_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Active mode. */ +} spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief Core LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Low Power mode */ +} spc_lowpower_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_sys_ldo_option +{ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Low Power mode. */ +} spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Low Power mode. */ +} spc_lowpower_mode_dcdc_option_t; + +/*! + * @brief DCDC Burst configuration. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief CORE/SYS/IO VDD Voltage Detect options. + */ +typedef struct _spc_voltage_detect_option +{ + bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */ + bool HVDResetEnable; /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */ + bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */ + bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ +} spc_voltage_detect_option_t; + +/*! + * @brief Core Voltage Detect configuration. + */ +typedef struct _spc_core_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */ +} spc_core_voltage_detect_config_t; + +/*! + * @brief System Voltage Detect Configuration. + */ +typedef struct _spc_system_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< System VDD low-voltage selection. */ +} spc_system_voltage_detect_config_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @brief IO Voltage Detect Configuration. + */ +typedef struct _spc_io_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ +} spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @brief Active mode configuration. + */ +typedef struct _spc_active_mode_regulators_config +{ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ +} spc_active_mode_regulators_config_t; + +/*! + * @brief Low Power Mode configuration. + */ +typedef struct _spc_lowpower_mode_regulators_config +{ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ +} spc_lowpower_mode_regulators_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SPC Status + * @{ + */ +/*! + * @brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * @param base SPC peripheral base address. + * @return Current isolation status for each power domains. See @ref _spc_power_domains for details. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base); + +/*! + * @brief Clears peripherals and I/O pads isolation flags for each power domains. + * + * This function clears peripherals and I/O pads isolation flags for each power domains. + * After recovering from the POWERDOWN mode, user must invoke this function to release the + * I/O pads and certain peripherals to their normal run mode state. Before invoking this + * function, user must restore chip configuration in particular pin configuration for enabled + * WUU wakeup pins. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) +{ + base->SC |= SPC_SC_ISO_CLR_MASK; +} + +/*! + * @brief Gets SPC busy status flag. + * + * This function gets SPC busy status flag. When SPC executing any type of power mode + * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set + * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level + * in ACTIVE mode, the SPC busy status flag is set and this function return true. + * + * @param base SPC peripheral base address. + * @return Ack busy flag. + * true - SPC is busy. + * false - SPC is not busy. + */ +static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) +{ + return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); +} + +/*! + * @brief Checks system low power request. + * + * @note Only when all power domains request low power mode entry, the result of this function is true. That means when + * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register. + * + * @param base SPC peripheral base address. + * @return The system low power request check result. + * - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode + * configuration are based on the LP_CFG configuration register. + * - \b false SPC in active mode and ACTIVE_CFG register control system power supply. + */ +static inline bool SPC_CheckLowPowerReqest(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK); +} + +/*! + * @brief Clears system low power request, set SPC in active mode. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearLowPowerRequest(SPC_Type *base) +{ + base->SC |= SPC_SC_SPC_LP_REQ_MASK; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + +/*! + * @brief Gets selected power domain's requested low power mode. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * + * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId); + +/*! + * @brief Checks power domain's low power request. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * @return The result of power domain's low power request. + * - \b true The selected power domain requests low power mode entry. + * - \b false The selected power domain does not request low power mode entry. + */ +static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == + SPC_PD_STATUS_PWR_REQ_STATUS_MASK); +} + +/*! + * @brief Clears selected power domain's low power request flag. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + */ +static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; +} + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ + +/*! + * @name Low Power Request configuration + * @{ + */ +/*! + * @brief Configs Low power request output pin. + * + * This function config the low power request output pin + * + * @param base SPC peripheral base address. + * @param config Pointer the @ref spc_lowpower_request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/* @} */ + +/*! + * @name SRAM Control APIs + * @{ + */ + +/*! + * @brief Set SRAM operate voltage. + * + * @param base SPC peripheral base address. + * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); + +/* @} */ + +/*! + * @name Active Mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Active mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >> + SPC_ACTIVE_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets all voltage detectors status in Active mode. + * + * @param base SPC peripheral base address. + * @return All voltage detectors status in Active mode. + */ +static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->ACTIVE_CFG & + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK \ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Configs Bandgap mode in Active mode. + * + * @note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * disable Bandgap in active mode + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * @retval #kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference voltage to CMP. + * false - Disable Buffer Stored Reference voltage to CMP. + */ +static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +/*! + * @brief Sets the delay when the regulators change voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles. + */ +static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay) +{ + base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay); +} + +/*! + * @brief Configs regulators in Active mode. + * + * This function provides the method to config all on-chip regulators in active mode. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_active_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Active power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); + +/*! + * @brief Disables/Enables VDD Core Glitch Detect in Active mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Enables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in active mode. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in active mode. + */ +static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) +{ + return base->ACTIVE_CFG1; +} + +/* @} */ + +/*! + * @name Low Power mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Low Power mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets the status of all voltage detectors in Low Power mode. + * + * @param base SPC peripheral base address. + * @return The status of all voltage detectors in low power mode. + */ +static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK \ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Enables/Disables Low Power IREF in low power modes. + * + * This function enables/disables Low Power IREF. Low Power IREF can only get + * disabled in Deep power down mode. In other low power modes, the Low Power IREF + * is always enabled. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Low Power IREF. + * true - Enable Low Power IREF for Low Power modes. + * false - Disable Low Power IREF for Deep Power Down mode. + */ +static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK; + } +} + +/*! + * @brief Configs Bandgap mode in Low Power mode. + * + * This function configs Bandgap mode in Low Power mode. + * IF user want to disable Bandgap while keeping any of the Regulator in Normal Driver Strength + * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode + * will be set as Bandgap Enabled with Buffer Disabled. + * + * @note This API shall be invoked following set HVDs/LVDs and regulators' driver strength. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) +/*! + * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. + * + * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the + * external input CORE VDD to a lower voltage level to reduce internal leakage. + * IVS is invalid in Sleep or Deep power down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IVS. + * true - enable CORE VDD IVS in Power Down mode. + * false - disable CORE VDD IVS in Power Down mode. + */ +static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +/*! + * @brief Sets the delay when exit the low power modes. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes. + */ +static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) +{ + base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay); +} + +/*! + * @brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); + +/*! + * @brief Disable/Enable VDD Core Glitch Detect in low power mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Enables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in low power modes. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in low power modes. + */ +static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) +{ + return base->LP_CFG1; +} + +/* @} */ + +/*! + * @name Voltage Detect Status + * @{ + */ +/*! + * @brief Get Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +{ + return (uint8_t)(base->VD_STAT); +} + +/*! + * @brief Clear Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask) +{ + base->VD_STAT |= mask; +} + +/* @} */ + +/*! + * @name Voltage Detect configuration for Core voltage domain. + * @{ + */ + +/*! + * @brief Configs CORE voltage detect options. + * + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config); + +/*! + * @brief Locks Core voltage detect reset setting. + * + * This function locks core voltage detect reset setting. After invoking this function + * any configuration of Core voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Unlocks Core voltage detect reset setting. + * + * This function unlocks core voltage detect reset setting. If locks the Core + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Active mode. + * + * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. + * + * This function enables/disables the Core Low Voltage Detector. + * If enabled the Core Low Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/* @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain + * @{ + */ +/*! + * @brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level System VDD Low-Voltage level selection. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config); + +/*! + * @brief Lock System voltage detect reset setting. + * + * This function locks system voltage detect reset setting. After invoking this function + * any configuration of System Voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock System voltage detect reset setting. + * + * This function unlocks system voltage detect reset setting. If locks the System + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the System High Voltage Detector in Active mode. + * + * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disable the System Low Voltage Detector in Active mode. + * + * @note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System High Voltage Detector in Low Power mode. + * + * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note + * that the bandgap must be enabled and the drive strength of each regulator must + * not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System Low Voltage Detector in Low Power mode. + * + * @note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @name Voltage detect configuration for IO voltage domain + * @{ + */ +/*! + * @brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config); + +/*! + * @brief Lock IO Voltage detect reset setting. + * + * This function locks IO voltage detect reset setting. After invoking this function + * any configuration of system voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock IO voltage detect reset setting. + * + * This function unlocks IO voltage detect reset setting. If locks the IO + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Active mode. + * + * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Active mode. + * + * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Low Power mode. + * + * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode. + * + * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/* @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @name External Voltage domains configuration + * @{ + */ +/*! + * @brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * @param base SPC peripheral base address. + * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference + * Manual for the Bitmap. + * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask); + +/*! + * @brief Gets External Domains status. + * + * This function configs external voltage domains status. + * + * @param base SPC peripheral base address. + * @return The status of each external domain. + */ +static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) +{ + return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); +} + +/* @} */ + +/*! + * @name Set CORE LDO Regulator + * @{ + */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) +/*! + * @brief Enable/Disable Core LDO regulator. + * + * @note The CORE LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CORE LDO Regulator. + * true - Enable CORE LDO Regulator. + * false - Disable CORE LDO Regulator. + */ +static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If CORE_LDO is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) +/*! + * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. + * + * @note This function only useful when enabled the CORE LDO Regulator. + * + * @param base SPC peripheral base address. + * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode. + * true - CORE LDO Regulator will discharge in Deep Power Down mode. + * false - CORE LDO Regulator will not discharge in Deep Power Down mode. + */ +static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) +{ + if (pulldown) + { + base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } + else + { + base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ + +/*! + * @brief Configs Core LDO VDD Regulator in Active mode. + * + * @note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + * + * @note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not + * set to low. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO VDD Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + +/*! + * @brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength set as Normal. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Set System LDO Regulator. + * @{ + */ + +/*! + * @brief Enable/Disable System LDO regulator. + * + * @note The SYSTEM LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LDO Regulator. + * true - Enable System LDO Regulator. + * false - Disable System LDO Regulator. + */ +static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If SYSTEM_LDO is disabled, may cause some unexpected issues. + */ + base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK; + } +} + +/*! + * @brief Enable/Disable current sink feature of System LDO Regulator. + * + * @param base SPC peripheral base address. + * @param sink Enable/Disable current sink feature. + * true - Enable current sink feature of System LDO Regulator. + * false - Disable current sink feature of System LDO Regulator. + */ +static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) +{ + if (sink) + { + base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK; + } + else + { + base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK; + } +} + +/*! + * @brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enables the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + +/*! + * @brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * @param base SPC peripheral base address. + * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Set DCDC Regulator. + * @{ + */ + +/*! + * @brief Enable/Disable DCDC Regulator. + * + * @note The DCDC enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable DCDC Regulator. + * true - Enable DCDC Regulator. + * false - Disable DCDC Regulator. + */ +static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If DCDC is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK; + } +} + +/*! + * @brief Config DCDC Burst options + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_dcdc_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); + +/*! + * @brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * @param base SPC peripheral base address. + * @param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); + +/*! + * @brief Configs DCDC VDD Regulator in Active mode. + * + * @note Before switching DCDC drive strength from low to normal, the DCDC voltage level should be configured back to + * what it was before switching to low drive strength. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC VDD Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC VDD Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT); +} + +/*! + * @brief Set DCDC VDD Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC VDD Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT); +} + +/*! + * @brief Configs DCDC VDD Regulator in Low power modes. + * + * This function configs DCDC VDD Regulator in Low Power modes. + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode + * will be ignored. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC VDD Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC VDD Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT); +} + +/*! + * @brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC VDD Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> SPC_LP_CFG_DCDC_VDD_DS_SHIFT); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* FSL_SPC_H_ */ diff --git a/drivers/mcx_vbat/fsl_vbat.c b/drivers/mcx_vbat/fsl_vbat.c new file mode 100644 index 000000000..676adcdf5 --- /dev/null +++ b/drivers/mcx_vbat/fsl_vbat.c @@ -0,0 +1,498 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_vbat.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_vbat" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config) +{ + assert(config != NULL); + + VBAT_EnableFRO16k(base, config->enableFRO16k); + VBAT_UngateFRO16k(base, config->enabledConnectionsMask); +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * param base VBAT peripheral base address. + * param operateMode Specify the crystal oscillator mode, please refer to vbat_osc32k_operate_mode_t. + * param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap) +{ + if (operateMode == kVBAT_Osc32kEnabledToTransconductanceMode) + { + if (((uint8_t)extalCap & 0x1U) == 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerSwitchedMode) + { + if ((extalCap != kVBAT_Osc32kCrystalLoadCap0pF) && (xtalCap != kVBAT_Osc32kCrystalLoadCap0pF)) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode) + { + if ((extalCap & 0x1U) != 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if ((xtalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled) && (extalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled)) + { + base->OSCCTLA |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + VBAT_OSCCTLA_XTAL_CAP_SEL(~xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~extalCap)); + } + + base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode)); + base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN((uint8_t)~operateMode)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * brief Enable/disable Bandgap. + * + * note The FRO16K must be enabled before enableing the bandgap. + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * retval kStatus_Success Success to enable/disable the bandgap. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_BG_EN_MASK; + } + else + { + /* FRO16K must be enabled before enabling the Bandgap. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_BG_EN_MASK; + } + + return status; +} + +/*! + * brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_LDO_EN_MASK; + /* Polling until LDO is enabled. */ + while ((base->STATUSA & VBAT_STATUSA_LDO_RDY_MASK) == 0UL) + { + } + } + else + { + /* The bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16k must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_LDO_EN_MASK; + } + + return status; +} + +/*! + * brief Switch the SRAM to be powered by VBAT. + * + * param base VBAT peripheral base address. + * + * retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base) +{ + status_t status = kStatus_Success; + + status = VBAT_EnableBandgap(base, true); + + if (status == kStatus_Success) + { + VBAT_EnableBandgapRefreshMode(base, true); + (void)VBAT_EnableBackupSRAMRegulator(base, true); + + /* Isolate the SRAM array */ + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + /* Switch the supply to VBAT LDO. */ + base->LDORAMC |= VBAT_LDORAMC_SWI_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * brief Enable/disable Bandgap timer. + * + * note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap timer. + * param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of vbat_bandgap_timer_id_t. + * + * retval kStatus_Success Success to enable/disable selected bandgap timer. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not + * enabled previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } + } + else + { + /* Bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16K must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + } + + return status; +} + +/*! + * brief Set bandgap timer0 timeout value. + * + * param base VBAT peripheral base address. + * param timeoutPeriod Bandgap timer timeout value, please refer to vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER0 & VBAT_LDOTIMER0_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + base->LDOTIMER0 = ((base->LDOTIMER0 & (~VBAT_LDOTIMER0_TIMCFG_MASK)) | VBAT_LDOTIMER0_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } +} + +/*! + * brief Set bandgap timer1 timeout value. + * + * note The timeout value can only be changed when the timer is disabled. + * + * param base VBAT peripheral base address. + * param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER1 & VBAT_LDOTIMER1_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + + base->LDOTIMER1 = ((base->LDOTIMER1 & (~VBAT_LDOTIMER1_TIMCFG_MASK)) | VBAT_LDOTIMER1_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * brief Initializes the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_clock_monitor_config_t structure. + * + * retval kStatus_Success Clock monitor is initialized successfully. + * retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if ((VBAT_GetStatusFlags(base) & kVBAT_StatusFlagOsc32kReady) != 0UL) + { + if (VBAT_CheckClockMonitorControlLocked(base)) + { + status = kStatus_VBAT_ClockMonitorLocked; + } + else + { + /* Disable clock monitor before configuring clock monitor. */ + VBAT_EnableClockMonitor(base, false); + /* Set clock monitor divide trim value. */ + VBAT_SetClockMonitorDivideTrim(base, config->divideTrim); + /* Set clock monitor frequency trim value. */ + VBAT_SetClockMonitorFrequencyTrim(base, config->freqTrim); + /* Enable clock monitor. */ + VBAT_EnableClockMonitor(base, true); + + if (config->lock) + { + VBAT_LockClockMonitorControl(base); + } + } + } + else + { + status = kStatus_VBAT_OSC32KNotReady; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief Deinitialize the VBAT clock monitor. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Clock monitor is de-initialized successfully. + * retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base) +{ + if (VBAT_CheckClockMonitorControlLocked(base)) + { + return kStatus_VBAT_ClockMonitorLocked; + } + + VBAT_EnableClockMonitor(base, false); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * brief Initialize tamper control. + * + * note Both FRO16K and bandgap should be enabled before calling this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_tamper_config_t structure. + * + * retval kStatus_Success Tamper is initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + * retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + else + { + base->TAMCTLA = ((base->TAMCTLA & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN(config->enableVoltageDetect) | + VBAT_TAMCTLA_TEMP_EN(config->enableTemperatureDetect)); + base->TAMCTLB = ((base->TAMCTLB & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN((config->enableVoltageDetect) ? 0U : 1U) | + VBAT_TAMCTLA_TEMP_EN((config->enableTemperatureDetect) ? 0U : 1U)); + + if (config->lock) + { + VBAT_LockTamperControl(base); + } + } + } + else + { + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief De-initialize tamper control. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Tamper is de-initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base) +{ + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + + base->TAMCTLA &= ~(VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + base->TAMCTLB |= (VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ diff --git a/drivers/mcx_vbat/fsl_vbat.h b/drivers/mcx_vbat/fsl_vbat.h new file mode 100644 index 000000000..72290b49f --- /dev/null +++ b/drivers/mcx_vbat/fsl_vbat.h @@ -0,0 +1,1386 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_VBAT_H_ +#define FSL_VBAT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mcx_vbat + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief VBAT driver version 2.3.0. */ +#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +#if !defined(VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET_MASK (0xF00U) +#define VBAT_LDORAMC_RET_SHIFT (8U) +#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#endif + +/*! + * @brief The enumeration of VBAT module status. + */ +enum +{ + kStatus_VBAT_Fro16kNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 0), /*!< Internal 16kHz free running + oscillator not enabled. */ + kStatus_VBAT_BandgapNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 1), /*!< Bandgap not enabled. */ + kStatus_VBAT_WrongCapacitanceValue = MAKE_STATUS(kStatusGroup_VBAT, 2), /*!< Wrong capacitance for + selected oscillator mode. */ + kStatus_VBAT_ClockMonitorLocked = MAKE_STATUS(kStatusGroup_VBAT, 3), /*!< Clock monitor locked. */ + kStatus_VBAT_OSC32KNotReady = MAKE_STATUS(kStatusGroup_VBAT, 4), /*!< OSC32K not ready. */ + kStatus_VBAT_LDONotReady = MAKE_STATUS(kStatusGroup_VBAT, 5), /*!< LDO not ready. */ + kStatus_VBAT_TamperLocked = MAKE_STATUS(kStatusGroup_VBAT, 6), /*!< Tamper locked. */ +}; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! + * @brief The enumeration of VBAT status flags. + * + * @anchor vbat_status_flag_t + */ +enum _vbat_status_flag +{ + kVBAT_StatusFlagPORDetect = VBAT_STATUSA_POR_DET_MASK, /*!< VBAT domain has been reset */ + kVBAT_StatusFlagWakeupPin = VBAT_STATUSA_WAKEUP_FLAG_MASK, /*!< A falling edge is detected on the wakeup pin. */ + kVBAT_StatusFlagBandgapTimer0 = VBAT_STATUSA_TIMER0_FLAG_MASK, /*!< Bandgap Timer0 period reached. */ + kVBAT_StatusFlagBandgapTimer1 = VBAT_STATUSA_TIMER1_FLAG_MASK, /*!< Bandgap Timer1 period reached. */ + kVBAT_StatusFlagLdoReady = VBAT_STATUSA_LDO_RDY_MASK, /*!< LDO is enabled and ready. */ + kVBAT_StatusFlagOsc32kReady = VBAT_STATUSA_OSC_RDY_MASK, /*!< OSC32k is enabled and clock is ready. */ +#if defined(VBAT_STATUSA_CLOCK_DET_MASK) + kVBAT_StatusFlagClockDetect = VBAT_STATUSA_CLOCK_DET_MASK, /*!< The clock monitor has detected an error. */ +#endif /* VBAT_STATUSA_CLOCK_DET_MASK */ + kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */ +#if defined(VBAT_STATUSA_VOLT_DET_MASK) + kVBAT_StatusFlagVoltageDetect = VBAT_STATUSA_VOLT_DET_MASK, /*!< Voltage monitor has detected + an error with VBAT supply. */ +#endif /* VBAT_STATUSA_VOLT_DET_MASK */ +#if defined(VBAT_STATUSA_TEMP_DET_MASK) + kVBAT_StatusFlagTemperatureDetect = VBAT_STATUSA_TEMP_DET_MASK, /*!< Temperature monitor has detected an error. */ +#endif /* VBAT_STATUSA_TEMP_DET_MASK */ +#if defined(VBAT_STATUSA_SEC0_DET_MASK) + kVBAT_StatusFlagSec0Detect = VBAT_STATUSA_SEC0_DET_MASK, /*!< Security input 0 has detected an error. */ +#endif /* VBAT_STATUSA_SEC0_DET_MASK */ + kVBAT_StatusFlagInterrupt0Detect = VBAT_STATUSA_IRQ0_DET_MASK, /*!< Interrupt 0 asserted. */ + kVBAT_StatusFlagInterrupt1Detect = VBAT_STATUSA_IRQ1_DET_MASK, /*!< Interrupt 1 asserted. */ + kVBAT_StatusFlagInterrupt2Detect = VBAT_STATUSA_IRQ2_DET_MASK, /*!< Interrupt 2 asserted. */ + kVBAT_StatusFlagInterrupt3Detect = VBAT_STATUSA_IRQ3_DET_MASK, /*!< Interrupt 2 asserted. */ +}; + +/*! + * @brief The enumeration of VBAT interrupt enable. + * + * @anchor vbat_interrupt_enable_t + */ +enum _vbat_interrupt_enable +{ + kVBAT_InterruptEnablePORDetect = VBAT_IRQENA_POR_DET_MASK, /*!< Enable POR detect interrupt. */ + kVBAT_InterruptEnableWakeupPin = VBAT_IRQENA_WAKEUP_FLAG_MASK, /*!< Enable the interrupt when a falling edge is + detected on the wakeup pin. */ + kVBAT_InterruptEnableBandgapTimer0 = VBAT_IRQENA_TIMER0_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer0 period reached. */ + kVBAT_InterruptEnableBandgapTimer1 = VBAT_IRQENA_TIMER1_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer1 period reached. */ + kVBAT_InterruptEnableLdoReady = VBAT_IRQENA_LDO_RDY_MASK, /*!< Enable LDO ready interrupt. */ + kVBAT_InterruptEnableOsc32kReady = VBAT_IRQENA_OSC_RDY_MASK, /*!< Enable OSC32K ready interrupt. */ +#if defined(VBAT_IRQENA_CLOCK_DET_MASK) + kVBAT_InterruptEnableClockDetect = VBAT_IRQENA_CLOCK_DET_MASK, /*!< Enable clock monitor detect interrupt. */ +#endif /* VBAT_IRQENA_CLOCK_DET_MASK */ + kVBAT_InterruptEnableConfigDetect = + VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */ +#if defined(VBAT_IRQENA_VOLT_DET_MASK) + kVBAT_InterruptEnableVoltageDetect = VBAT_IRQENA_VOLT_DET_MASK, /*!< Enable voltage monitor detect interrupt. */ +#endif /* VBAT_IRQENA_VOLT_DET_MASK */ +#if defined(VBAT_IRQENA_TEMP_DET_MASK) + kVBAT_InterruptEnableTemperatureDetect = VBAT_IRQENA_TEMP_DET_MASK, /*!< Enable temperature monitor detect + interrupt. */ +#endif /* VBAT_IRQENA_TEMP_DET_MASK */ +#if defined(VBAT_IRQENA_SEC0_DET_MASK) + kVBAT_InterruptEnableSec0Detect = VBAT_IRQENA_SEC0_DET_MASK, /*!< Enable security input 0 detect interrupt. */ +#endif /* VBAT_IRQENA_SEC0_DET_MASK */ + kVBAT_InterruptEnableInterrupt0 = VBAT_IRQENA_IRQ0_DET_MASK, /*!< Enable the interrupt0. */ + kVBAT_InterruptEnableInterrupt1 = VBAT_IRQENA_IRQ1_DET_MASK, /*!< Enable the interrupt1. */ + kVBAT_InterruptEnableInterrupt2 = VBAT_IRQENA_IRQ2_DET_MASK, /*!< Enable the interrupt2. */ + kVBAT_InterruptEnableInterrupt3 = VBAT_IRQENA_IRQ3_DET_MASK, /*!< Enable the interrupt3. */ + + kVBAT_AllInterruptsEnable = + (VBAT_IRQENA_POR_DET_MASK | VBAT_IRQENA_WAKEUP_FLAG_MASK | VBAT_IRQENA_TIMER0_FLAG_MASK | + VBAT_IRQENA_TIMER1_FLAG_MASK | VBAT_IRQENA_LDO_RDY_MASK | VBAT_IRQENA_OSC_RDY_MASK | + VBAT_IRQENA_CONFIG_DET_MASK | VBAT_IRQENA_IRQ0_DET_MASK | VBAT_IRQENA_IRQ1_DET_MASK | + VBAT_IRQENA_IRQ2_DET_MASK | VBAT_IRQENA_IRQ3_DET_MASK), /*!< Enable all interrupts. */ +}; + +/*! + * @brief The enumeration of VBAT wakeup enable. + * + * @anchor vbat_wakeup_enable_t + */ +enum _vbat_wakeup_enable +{ + kVBAT_WakeupEnablePORDetect = VBAT_WAKENA_POR_DET_MASK, /*!< Enable POR detect wakeup. */ + kVBAT_WakeupEnableWakeupPin = VBAT_WAKENA_WAKEUP_FLAG_MASK, /*!< Enable wakeup feature when a falling edge is + detected on the wakeup pin. */ + kVBAT_WakeupEnableBandgapTimer0 = VBAT_WAKENA_TIMER0_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer0 period reached. */ + kVBAT_WakeupEnableBandgapTimer1 = VBAT_WAKENA_TIMER1_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer1 period reached. */ + kVBAT_WakeupEnableLdoReady = VBAT_WAKENA_LDO_RDY_MASK, /*!< Enable wakeup when LDO ready. */ + kVBAT_WakeupEnableOsc32kReady = VBAT_WAKENA_OSC_RDY_MASK, /*!< Enable wakeup when OSC32k ready. */ +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + kVBAT_WakeupEnableClockDetect = + VBAT_WAKENA_CLOCK_DET_MASK, /*!< Enable wakeup when clock monitor detect an error. */ +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ + kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when + configuration error detected. */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + kVBAT_WakeupEnableVoltageDetect = VBAT_WAKENA_VOLT_DET_MASK, /*!< Enable wakeup when voltage monitor detect an + error. */ +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + kVBAT_WakeupEnableTemperatureDetect = VBAT_WAKENA_TEMP_DET_MASK, /*!< Enable wakeup when temperature monitor + detect an error. */ +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + kVBAT_WakeupEnableSec0Detect = VBAT_WAKENA_SEC0_DET_MASK, /*!< Enable wakeup when security input 0 detect an + error. */ +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + kVBAT_WakeupEnableInterrupt0 = VBAT_WAKENA_IRQ0_DET_MASK, /*!< Enable wakeup when interrupt0 asserted. */ + kVBAT_WakeupEnableInterrupt1 = VBAT_WAKENA_IRQ1_DET_MASK, /*!< Enable wakeup when interrupt1 asserted. */ + kVBAT_WakeupEnableInterrupt2 = VBAT_WAKENA_IRQ2_DET_MASK, /*!< Enable wakeup when interrupt2 asserted. */ + kVBAT_WakeupEnableInterrupt3 = VBAT_WAKENA_IRQ3_DET_MASK, /*!< Enable wakeup when interrupt3 asserted. */ + + kVBAT_AllWakeupsEnable = (VBAT_WAKENA_POR_DET_MASK | VBAT_WAKENA_WAKEUP_FLAG_MASK | VBAT_WAKENA_TIMER0_FLAG_MASK | + VBAT_WAKENA_TIMER1_FLAG_MASK | VBAT_WAKENA_LDO_RDY_MASK | VBAT_WAKENA_OSC_RDY_MASK | + VBAT_WAKENA_CONFIG_DET_MASK | VBAT_WAKENA_IRQ0_DET_MASK | VBAT_WAKENA_IRQ1_DET_MASK | + VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK + +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + | VBAT_WAKENA_CLOCK_DET_MASK + +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + | VBAT_WAKENA_VOLT_DET_MASK + +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + | VBAT_WAKENA_TEMP_DET_MASK + +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + | VBAT_WAKENA_SEC0_DET_MASK + +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + ), /*!< Enable all wakeup. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The enumeration of VBAT tamper enable. + */ +enum _vbat_tamper_enable +{ + kVBAT_TamperEnablePOR = VBAT_TAMPERA_POR_DET_MASK, /*!< Enable tamper if POR asserted in STATUS register. */ + kVBAT_TamperEnableClockDetect = VBAT_TAMPERA_CLOCK_DET_MASK, /*!< Enable tamper if clock monitor detect an error. */ + kVBAT_TamperEnableConfigDetect = + VBAT_TAMPERA_CONFIG_DET_MASK, /*!< Enable tamper if configuration error detected. */ + kVBAT_TamperEnableVoltageDetect = VBAT_TAMPERA_VOLT_DET_MASK, /*!< Enable tamper if voltage monitor detect an + error. */ + kVBAT_TamperEnableTemperatureDetect = VBAT_TAMPERA_TEMP_DET_MASK, /*!< Enable tamper if temperature monitor + detect an error. */ + kVBAT_TamperEnableSec0Detect = VBAT_TAMPERA_SEC0_DET_MASK, /*!< Enable tamper if security input 0 detect an + error. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer id, VBAT support two bandgap timers. + * + * @anchor vbat_bandgap_timer_id_t + */ +enum _vbat_bandgap_timer_id +{ + kVBAT_BandgapTimer0 = 1U << 0U, /*!< Bandgap Timer0. */ + kVBAT_BandgapTimer1 = 1U << 1U, /*!< Bandgap Timer1. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +/*! + * @brief The enumeration of connections for OSC32K/FRO32K output clock to other modules. + * + * @anchor vbat_clock_enable_t + */ +enum _vbat_clock_enable +{ + kVBAT_EnableClockToDomain0 = 1U << 0U, /*!< Enable clock to power domain0. */ + kVBAT_EnableClockToDomain1 = 1U << 1U, /*!< Enable clock to power domain1. */ + kVBAT_EnableClockToDomain2 = 1U << 2U, /*!< Enable clock to power domain2. */ + kVBAT_EnableClockToDomain3 = 1U << 3U, /*!< Enable clock to power domain3. */ +}; +#define kVBAT_EnableClockToVddBat kVBAT_EnableClockToDomain0 +#define kVBAT_EnableClockToVddSys kVBAT_EnableClockToDomain1 +#define kVBAT_EnableClockToVddWake kVBAT_EnableClockToDomain2 +#define kVBAT_EnableClockToVddMain kVBAT_EnableClockToDomain3 + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @brief The enumeration of SRAM arrays that controlled by VBAT. + * @anchor vbat_ram_array_t + */ +enum _vbat_ram_array +{ + kVBAT_SramArray0 = 1U << 0U, /*!< Specify SRAM array0 that controlled by VBAT. */ + kVBAT_SramArray1 = 1U << 1U, /*!< Specify SRAM array1 that controlled by VBAT. */ + kVBAT_SramArray2 = 1U << 2U, /*!< Specify SRAM array2 that controlled by VBAT. */ + kVBAT_SramArray3 = 1U << 3U, /*!< Specify SRAM array3 that controlled by VBAT. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +/*! + * @brief The enumeration of bandgap refresh period. + */ +typedef enum _vbat_bandgap_refresh_period +{ + kVBAT_BandgapRefresh7P8125ms = 0U, /*!< Bandgap refresh every 7.8125ms. */ + kVBAT_BandgapRefresh15P625ms = 1U, /*!< Bandgap refresh every 15.625ms. */ + kVBAT_BandgapRefresh31P25ms = 2U, /*!< Bandgap refresh every 31.25ms. */ + kVBAT_BandgapRefresh62P5ms = 3U, /*!< Bandgap refresh every 62.5ms. */ +} vbat_bandgap_refresh_period_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer0 timeout period. + */ +typedef enum _vbat_bandgap_timer0_timeout_period +{ + kVBAT_BangapTimer0Timeout1s = 0U, /*!< Bandgap timer0 timerout every 1s. */ + kVBAT_BangapTimer0Timeout500ms = 1U, /*!< Bandgap timer0 timerout every 500ms. */ + kVBAT_BangapTimer0Timeout250ms = 2U, /*!< Bandgap timer0 timerout every 250ms. */ + kVBAT_BangapTimer0Timeout125ms = 3U, /*!< Bandgap timer0 timerout every 125ms. */ + kVBAT_BangapTimer0Timeout62P5ms = 4U, /*!< Bandgap timer0 timerout every 62.5ms. */ + kVBAT_BangapTimer0Timeout31P25ms = 5U, /*!< Bandgap timer0 timerout every 31.25ms. */ +} vbat_bandgap_timer0_timeout_period_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @brief The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on. + */ +typedef enum _vbat_osc32k_operate_mode +{ + kVBAT_Osc32kEnabledToTransconductanceMode = 0U, /*!< Set to transconductance mode. */ + kVBAT_Osc32kEnabledToLowPowerBackupMode = 1U, /*!< Set to low power backup mode. */ + kVBAT_Osc32kEnabledToLowPowerSwitchedMode = 2U, /*!< Set to low power switched mode. */ +} vbat_osc32k_operate_mode_t; + +/*! + * @brief The enumeration of OSC32K load capacitance. + */ +typedef enum _vbat_osc32k_load_capacitance_select +{ + kVBAT_Osc32kCrystalLoadCap0pF = + 0U, /*!< Internal capacitance bank is enabled, set the internal capacitance to 0 pF. */ + kVBAT_Osc32kCrystalLoadCap2pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 2 pF. */ + kVBAT_Osc32kCrystalLoadCap4pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 4 pF. */ + kVBAT_Osc32kCrystalLoadCap6pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 6 pF. */ + kVBAT_Osc32kCrystalLoadCap8pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 8 pF. */ + kVBAT_Osc32kCrystalLoadCap10pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 10 pF. */ + kVBAT_Osc32kCrystalLoadCap12pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 12 pF. */ + kVBAT_Osc32kCrystalLoadCap14pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 14 pF. */ + kVBAT_Osc32kCrystalLoadCap16pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 16 pF. */ + kVBAT_Osc32kCrystalLoadCap18pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 18 pF. */ + kVBAT_Osc32kCrystalLoadCap20pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 20 pF. */ + kVBAT_Osc32kCrystalLoadCap22pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 22 pF. */ + kVBAT_Osc32kCrystalLoadCap24pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 24 pF. */ + kVBAT_Osc32kCrystalLoadCap26pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 26 pF. */ + kVBAT_Osc32kCrystalLoadCap28pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 28 pF. */ + kVBAT_Osc32kCrystalLoadCap30pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 30 pF. */ + kVBAT_Osc32kCrystalLoadCapBankDisabled = 0xF0U, /*!< Internal capacitance bank is disabled. */ +} vbat_osc32k_load_capacitance_select_t; + +/*! + * @brief The enumeration of start-up time of the oscillator. + */ +typedef enum _vbat_osc32k_start_up_time +{ + kVBAT_Osc32kStartUpTime8Sec = 0U, /*!< Configure the start-up time as 8 seconds. */ + kVBAT_Osc32kStartUpTime4Sec, /*!< Configure the start-up time as 4 seconds. */ + kVBAT_Osc32kStartUpTime2Sec, /*!< Configure the start-up time as 2 seconds. */ + kVBAT_Osc32kStartUpTime1Sec, /*!< Configure the start-up time as 1 seconds. */ + kVBAT_Osc32kStartUpTime0P5Sec, /*!< Configure the start-up time as 0.5 seconds. */ + kVBAT_Osc32kStartUpTime0P25Sec, /*!< Configure the start-up time as 0.25 seconds. */ + kVBAT_Osc32kStartUpTime0P125Sec, /*!< Configure the start-up time as 0.125 seconds. */ + kVBAT_Osc32kStartUpTime0P5MSec, /*!< Configure the start-up time as 0.5 milliseconds. */ +} vbat_osc32k_start_up_time_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! + * @brief The enumeration of VBAT module supplies. + */ +typedef enum _vbat_internal_module_supply +{ + kVBAT_ModuleSuppliedByVddBat = 0U, /*!< VDD_BAT supplies VBAT modules. */ + kVBAT_ModuleSuppliedByVddSys = 1U, /*!< VDD_SYS supplies VBAT modules. */ +} vbat_internal_module_supply_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The enumeration of VBAT clock monitor divide trim value + */ +typedef enum _vbat_clock_monitor_divide_trim +{ + kVBAT_ClockMonitorOperateAt1kHz = 0U, /*!< Clock monitor operates at 1 kHz. */ + kVBAT_ClockMonitorOperateAt64Hz = 1U, /*!< Clock monitor operates at 64 Hz. */ +} vbat_clock_monitor_divide_trim_t; + +/*! + * @brief The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert. + */ +typedef enum _vbat_clock_monitor_freq_trim +{ + kVBAT_ClockMonitorAssert2Cycle = 0U, /*!< Clock monitor assert 2 cycles after expected edge. */ + kVBAT_ClockMonitorAssert4Cycle = 1U, /*!< Clock monitor assert 4 cycles after expected edge. */ + kVBAT_ClockMonitorAssert6Cycle = 2U, /*!< Clock monitor assert 8 cycles after expected edge. */ + kVBAT_ClockMonitorAssert8Cycle = 3U, /*!< Clock monitor assert 8 cycles after expected edge. */ +} vbat_clock_monitor_freq_trim_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +/*! + * @brief The structure of internal 16kHz free running oscillator attributes. + */ +typedef struct _vbat_fro16k_config +{ + bool enableFRO16k; /*!< Enable/disable internal 16kHz free running oscillator. */ + uint8_t enabledConnectionsMask; /*!< The mask of connected modules to enable FRO16k clock output. */ +} vbat_fro16k_config_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The structure of internal clock monitor, including divide trim and frequency trim. + */ +typedef struct _vbat_clock_monitor_config +{ + vbat_clock_monitor_divide_trim_t divideTrim : 1U; /* !< Divide trim value, please + refer to @ref vbat_clock_monitor_divide_trim_t */ + vbat_clock_monitor_freq_trim_t freqTrim : 2U; /*!< Frequency trim value used to adjust the clock monitor + assert, please refer to @ref vbat_clock_monitor_freq_trim_t. */ + bool lock : 1U; /*!< Lock the clock monitor control after enabled. */ +} vbat_clock_monitor_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The structure of Tamper configuration. + */ +typedef struct _vbat_tamper_config +{ + bool enableVoltageDetect : 1U; /*!< Enable/disable voltage detection. */ + bool enableTemperatureDetect : 1U; /*!< Enable/disable temperature detection. */ + bool lock : 1U; /*!< Lock the tamper control after enabled. */ +} vbat_tamper_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FRO16K Control Interfaces + * @{ + */ + +/*! + * @brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config); + +/*! + * @brief Enable/disable internal 16kHz free running oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 16kHz FRO. + * - \b true Enable internal 16kHz free running oscillator. + * - \b false Disable internal 16kHz free running oscillator. + */ +static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } + else + { + base->FROCTLA &= ~VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB |= VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } +} + +/*! + * @brief Check if internal 16kHz free running oscillator is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The internal 16kHz Free running oscillator is enabled. + * @retval false The internal 16kHz Free running oscillator is enabled. + */ +static inline bool VBAT_CheckFRO16kEnabled(VBAT_Type *base) +{ + return (bool)((base->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) == VBAT_FROCTLA_FRO_EN_MASK); +} + +/*! + * @brief Enable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The mask of modules that FRO16k is connected, should be the OR'ed + * value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE |= VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE &= ~VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Lock settings of internal 16kHz free running oscillator, please note that if locked 16kHz FRO's settings can + * not be updated until the next POR. + * + * @note Please note that the operation to ungate/gate FRO 16kHz output clock can not be locked by this function. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockFRO16kSettings(VBAT_Type *base) +{ + base->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; +#if (defined(VBAT_FROLCKB_LOCK_MASK)) + base->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; +#endif /* VBAT_FROLCKB_LOCK_MASK */ +} + +/*! + * @brief Check if FRO16K settings are locked. + * + * @param base VBAT peripheral base address. + * + * @return @c true in case of FRO16k settings are locked, @c false in case of FRO16k settings are not locked. + */ +static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base) +{ + return ((base->FROLCKA & VBAT_FROLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @name OSC32K Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable 32K Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 32k Crystal Oscillator: + * - \b true Enable crystal oscillator and polling status register to check clock is ready. + * - \b false Disable crystal oscillator. + */ +static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_OSC_EN_MASK; + + /* Polling status register to check clock is ready. */ + while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL) + ; + } + else + { + base->OSCCTLA &= ~VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB |= VBAT_OSCCTLA_OSC_EN_MASK; + } +} + +/*! + * @brief Bypass 32k crystal oscillator, the clock is still output by oscillator but this clock is the same as clock + * provided on EXTAL pin. + * + * @note In bypass mode, oscillator must be enabled; To exit bypass mode, oscillator must be disabled. + * + * @param base VBAT peripheral base address. + * @param enableBypass Used to enter/exit bypass mode: + * - \b true Enter into bypass mode; + * - \b false Exit bypass mode. + */ +static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass) +{ + if (enableBypass) + { + base->OSCCTLA |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } + else + { + base->OSCCTLA &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + * @param fine Specify amplifier fine trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse, uint8_t fine) +{ + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(fine))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine))); +} +#else +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse) +{ + base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse)); + base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse)); +} + +#endif /* */ + +/*! + * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * @param base VBAT peripheral base address. + * @param operateMode Specify the crystal oscillator mode, please refer to @ref vbat_osc32k_operate_mode_t. + * @param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * @param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * @retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * @retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap); + +/*! + * @brief Trim 32k crystal oscillator startup time. + * + * @param base VBAT peripheral base address. + * @param startupTime Specify the startup time of the oscillator. + */ +static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime) +{ + base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime)); + base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime))); +} + +/*! + * @brief Set crystal oscillator comparator trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param comparatorTrimValue Comparator trim value, ranges from 0 to 7. + */ +static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue))); +} + +/*! + * @brief Set crystal oscillator delay trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param delayTrimValue Delay trim value, ranges from 0 to 15. + */ +static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue))); +} + +/*! + * @brief Set crystal oscillator capacitor trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param capacitorTrimValue Capacitor value to trim, ranges from 0 to 3. + */ +static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue))); +} + +/*! + * @brief Lock Osc32k settings, after locked all writes to the Oscillator registers are blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LookOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA |= VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB &= ~VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Unlock Osc32k settings. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA &= ~VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB |= VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Check if osc32k settings are locked. + * + * @param base VBAT peripheral base address. + * @return \c true in case of osc32k settings are locked, \c false in case of osc32k settings are not locked. + */ +static inline bool VBAT_CheckOsc32kSettingsLocked(VBAT_Type *base) +{ + return ((base->OSCLCKA & VBAT_OSCLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Enable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE |= VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE &= ~VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @name RAM_LDO Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap. + * + * @note The FRO16K must be enabled before enabling the bandgap. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * @retval kStatus_Success Success to enable/disable the bandgap. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable); + +/*! + * @brief Check if bandgap is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The bandgap is enabled. + * @retval false The bandgap is disabled. + */ +static inline bool VBAT_CheckBandgapEnabled(VBAT_Type *base) +{ + return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK); +} + +/*! + * @brief Enable/disable bandgap low power refresh mode. + * + * @note For lowest power consumption, refresh mode must be enabled. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enableRefreshMode Used to enable/disable bandgap low power refresh mode. + * - \b true Enable bandgap low power refresh mode. + * - \b false Disable bandgap low power refresh mode. + */ +static inline void VBAT_EnableBandgapRefreshMode(VBAT_Type *base, bool enableRefreshMode) +{ + if (enableRefreshMode) + { + base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_REFRESH_EN_MASK; + } +} + +/*! + * @brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * @retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable); + +/*! + * @brief Lock settings of RAM_LDO, please note that if locked then RAM_LDO's settings + * can not be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockRamLdoSettings(VBAT_Type *base) +{ + base->LDOLCKA |= VBAT_LDOLCKA_LOCK_MASK; + base->LDOLCKB &= ~VBAT_LDOLCKA_LOCK_MASK; +} + +/*! + * @brief Check if RAM_LDO settings is locked. + * + * @param base VBAT peripheral base address. + * @return @c true in case of RAM_LDO settings are locked, @c false in case of RAM_LDO settings are unlocked. + */ +static inline bool VBAT_CheckRamLdoSettingsLocked(VBAT_Type *base) +{ + return ((base->LDOLCKA & VBAT_LDOLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Switch the SRAM to be powered by LDO_RAM. + * + * @note This function can be used to switch the SRAM to the VBAT retention supply at any time, but please note that the + * SRAM must not be accessed during this time. + * @note Invoke this function to switch power supply before switching off external power. + * @note RAM_LDO must be enabled before invoking this function. + * @note To access the SRAM arrays retained by the LDO_RAM, please invoke VBAT_SwitchSRAMPowerBySocSupply(), after + * external power is switched back on. + * + * @param base VBAT peripheral base address. + * + * @retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base); + +/*! + * @brief Switch the RAM to be powered by Soc Supply in software mode. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base) +{ + base->LDORAMC &= ~VBAT_LDORAMC_SWI_MASK; + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; +} + +/*! + * @brief Power off selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to power off, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Retain selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to retain, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Enable/disable SRAM isolation. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable SRAM violation. + * - \b true SRAM will be isolated. + * - \b false SRAM state follows the SoC power modes. + */ +static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + } + else + { + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_RAM_LDO */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! @name Bandgap Timer Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap timer. + * + * @note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap timer. + * @param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of @ref vbat_bandgap_timer_id_t. + * + * @retval kStatus_Success Success to enable/disable selected bandgap timer. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not enabled + * previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask); + +/*! + * @brief Set bandgap timer0 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod Bandgap timer timeout value, please refer to @ref vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod); + +/*! + * @brief Set bandgap timer1 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod); + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! @name Switch Control Interfaces + * @{ + */ + +/*! + * @brief Control the VBAT internal switch in active mode, VBAT modules can be suppiled by VDD_BAT and VDD_SYS. + * + * @param base VBAT peripheral base address. + * @param supply Used to control the VBAT internal switch. + */ +static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_SWI_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + } +} + +/*! + * @brief Get VBAT module supply in active mode. + * + * @param base VBAT peripheral base address. + * @return VDD_SYS supplies VBAT modules or VDD_BAT supplies VBAT modules, in type of @ref + * vbat_internal_module_supply_t. + */ +static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base) +{ + return (vbat_internal_module_supply_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK); +} + +/*! + * @brief Control the VBAT internal switch in low power modes. + * + * @note If VBAT modules are supplied by VDD_SYS in low power modes, VBAT module will also supplied by VDD_SYS in active + * mode. + * + * @param base VBAT peripheral base address. + * @param supply Used to specify which voltage input supply VBAT modules in low power mode. + */ +static inline void VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_LP_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLA |= VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_LP_EN_MASK; + } +} + +/*! + * @brief Lock switch control, if locked all writes to the switch registers will be blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA |= VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB &= ~VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Unlock switch control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA &= ~VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB |= VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Check if switch control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false switch control is not locked. + * @retval true switch control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base) +{ + return ((base->SWILCKA & VBAT_SWILCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @name Clock Monitor Interfaces + * @{ + */ + +/*! + * @brief Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * @note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_clock_monitor_config_t structure. + * + * @retval kStatus_Success Clock monitor is initialized successfully. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * @retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * @retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config); + +/*! + * @brief Deinitialize the VBAT clock monitor. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Clock monitor is de-initialized successfully. + * @retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base); + +/*! + * @brief Enable/disable clock monitor. + * + * @param base VBAT peripheral base address. + * @param enable Switcher to enable/disable clock monitor: + * - true: enable clock monitor; + * - false: disable clock monitor. + */ +static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->MONCTLA |= VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB &= ~VBAT_MONCTLA_MON_EN_MASK; + } + else + { + base->MONCTLA &= ~VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB |= VBAT_MONCTLA_MON_EN_MASK; + } +} + +/*! + * @brief Set clock monitor's divide trim, avaiable value is #kVBAT_ClockMonitorOperateAt1kHz and + * #kVBAT_ClockMonitorOperateAt64Hz + * + * @param base VBAT peripheral base address. + * @param divideTrim Specify divide trim value, please refer to @ref vbat_clock_monitor_divide_trim_t. + */ +static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(divideTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(~divideTrim); +} + +/*! + * @brief Set clock monitor's frequency trim, avaiable value is #kVBAT_ClockMonitorAssert2Cycle, + * #kVBAT_ClockMonitorAssert4Cycle, #kVBAT_ClockMonitorAssert6Cycle and #kVBAT_ClockMonitorAssert8Cycle. + * + * @param base VBAT peripheral base address. + * @param freqTrim Specify frequency trim value, please refer to @ref vbat_clock_monitor_freq_trim_t. + */ +static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(freqTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(~freqTrim); +} + +/*! + * @brief Lock clock monitor enable/disable control. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA |= VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB &= ~VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock clock monitor enable/disable control. + * + * @param base VBTA peripheral base address. + */ +static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA &= ~VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB |= VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Check if clock monitor enable/disable control is locked. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + * + * @retval false clock monitor enable/disable control is not locked. + * @retval true clock monitor enable/disable control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base) +{ + return ((base->MONLCKA & VBAT_MONLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_CLOCK_MONITOR */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! @name Tamper Control Interfaces + * + */ + +/*! + * @brief Initialize tamper control. + * + * @note Both FRO16K and bandgap should be enabled before calling this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_tamper_config_t structure. + * + * @retval kStatus_Success Tamper is initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + * @retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config); + +/*! + * @brief De-initialize tamper control. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Tamper is de-initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base); + +/*! + * @brief Enable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be enabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA |= tamperEnableMask; + base->TAMPERB &= ~tamperEnableMask; +} + +/*! + * @brief Disable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be disabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA &= ~tamperEnableMask; + base->TAMPERB |= tamperEnableMask; +} + +/*! + * @brief Get tamper enable information. + * + * @param base VBAT peripheral base address. + * + * @return Mask of tamper enable information, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base) +{ + return base->TAMPERA; +} + +/*! + * @brief Lock tamper control, if locked, it is not allowed to change tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA |= VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB &= ~VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA &= ~VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB |= VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Check if tamper control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false Tamper control is not locked. + * @retval true Tamper control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base) +{ + return ((base->TAMLCKA & VBAT_TAMLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_TAMPER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! @name Status, Interrupt, Wakeup Control Interfaces + * @{ + */ + +/*! + * @brief Get VBAT status flags + * + * @param base VBAT peripheral base address. + * @return The asserted status flags, should be the OR'ed value of @ref vbat_status_flag_t. + */ +static inline uint32_t VBAT_GetStatusFlags(VBAT_Type *base) +{ + return (uint32_t)(base->STATUSA); +} + +/*! + * @brief Clear VBAT status flags. + * + * @param base VBAT peripheral base address. + * @param mask The mask of status flags to be cleared, should be the OR'ed value of @ref vbat_status_flag_t except + * @ref kVBAT_StatusFlagLdoReady, @ref kVBAT_StatusFlagOsc32kReady, @ref kVBAT_StatusFlagInterrupt0Detect, + * @ref kVBAT_StatusFlagInterrupt1Detect, @ref kVBAT_StatusFlagInterrupt2Detect, + * @ref kVBAT_StatusFlagInterrupt3Detect. + */ +static inline void VBAT_ClearStatusFlags(VBAT_Type *base, uint32_t mask) +{ + base->STATUSA = mask; + base->STATUSB = ~mask; +} + +/*! + * @brief Enable interrupts for the VBAT module, such as POR detect interrupt, Wakeup Pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be enabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_EnableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA |= mask; + base->IRQENB &= (uint32_t)~mask; +} + +/*! + * @brief Disable interrupts for the VBAT module, such as POR detect interrupt, wakeup pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be disabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_DisableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA &= ~mask; + base->IRQENB |= mask; +} + +/*! + * @brief Enable wakeup for the VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_EnableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA |= mask; + base->WAKENB &= ~mask; +} + +/*! + * @brief Disable wakeup for VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_DisableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA &= ~mask; + base->WAKENB |= mask; +} + +/*! + * @brief Lock VBAT interrupt and wakeup settings, please note that if locked the interrupt and wakeup settings can not + * be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockInterruptWakeupSettings(VBAT_Type *base) +{ + base->LOCKA |= VBAT_LOCKA_LOCK_MASK; +} + +/*! + * @brief Set the default state of the WAKEUP_b pin output when no enabled wakeup source is asserted. + * + * @param base VBAT peripheral base address. + * @param assert Used to set default state of the WAKEUP_b pin output: + * - \b true WAKEUP_b output state is logic one; + * - \b false WAKEUP_b output state is logic zero. + */ +static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert) +{ + if (assert) + { + base->WAKECFG |= VBAT_WAKECFG_OUT_MASK; + } + else + { + base->WAKECFG &= ~VBAT_WAKECFG_OUT_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_VBAT_H__ */ diff --git a/drivers/mrt/fsl_mrt.h b/drivers/mrt/fsl_mrt.h index 7829d984e..3d398a0f9 100644 --- a/drivers/mrt/fsl_mrt.h +++ b/drivers/mrt/fsl_mrt.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ +#ifndef FSL_MRT_H_ +#define FSL_MRT_H_ #include "fsl_common.h" @@ -363,4 +363,4 @@ static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) /*! @}*/ -#endif /* _FSL_MRT_H_ */ +#endif /* FSL_MRT_H_ */ diff --git a/drivers/ostimer/fsl_ostimer.c b/drivers/ostimer/fsl_ostimer.c index c3acfb0e4..42feaf04a 100644 --- a/drivers/ostimer/fsl_ostimer.c +++ b/drivers/ostimer/fsl_ostimer.c @@ -16,6 +16,10 @@ #define FSL_COMPONENT_ID "platform.drivers.ostimer" #endif +#if defined(OSTIMER_RSTS) +#define OSTIMER_RESETS_ARRAY OSTIMER_RSTS +#endif + /* Typedef for interrupt handler. */ typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); @@ -62,6 +66,11 @@ static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; static ostimer_isr_t s_ostimerIsr; #endif +#if defined(OSTIMER_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_ostimerResets[] = OSTIMER_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -177,6 +186,10 @@ void OSTIMER_Init(OSTIMER_Type *base) CLOCK_EnableClock(kCLOCK_Sysctl); #endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OSTIMER_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_ostimerResets[OSTIMER_GetInstance(base)]); +#endif } /*! diff --git a/drivers/ostimer/fsl_ostimer.h b/drivers/ostimer/fsl_ostimer.h index c74a79313..0cd991ef4 100644 --- a/drivers/ostimer/fsl_ostimer.h +++ b/drivers/ostimer/fsl_ostimer.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ +#ifndef FSL_OSTIMER_H_ +#define FSL_OSTIMER_H_ #include "fsl_common.h" @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*@}*/ /*! @@ -270,4 +270,4 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); /*! @}*/ -#endif /* _FSL_OSTIMER_H_ */ +#endif /* FSL_OSTIMER_H_ */ diff --git a/drivers/pdm/fsl_pdm.c b/drivers/pdm/fsl_pdm.c index bfdc89384..2132ed2a1 100644 --- a/drivers/pdm/fsl_pdm.c +++ b/drivers/pdm/fsl_pdm.c @@ -227,7 +227,7 @@ status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32 uint32_t regDiv = 0U; /* get divider */ - osr = 16U - osr; + osr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - osr; pdmClockRate = sampleRate_HZ * osr * 8U; regDiv = sourceClock_HZ / pdmClockRate; @@ -262,7 +262,8 @@ status_t PDM_SetSampleRate( PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv) { #if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) - uint8_t realOsr = 16U - (osr & (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT)); + uint8_t realOsr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - + (osr & (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT)); #endif uint32_t regDiv = clkDiv >> 1U; @@ -336,11 +337,15 @@ void PDM_Init(PDM_Type *base, const pdm_config_t *config) base->CTRL_1 |= PDM_CTRL_1_SRES_MASK; /* Set the configure settings */ - base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_DOZEN_MASK)) | PDM_CTRL_1_DOZEN(config->enableDoze); - +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) + PDM_EnableDoze(base, config->enableDoze); +#endif base->CTRL_2 = (base->CTRL_2 & (~(PDM_CTRL_2_CICOSR_MASK | PDM_CTRL_2_QSEL_MASK))) | PDM_CTRL_2_CICOSR(config->cicOverSampleRate) | PDM_CTRL_2_QSEL(config->qualityMode); +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + base->CTRL_2 = (base->CTRL_2 & ~PDM_CTRL_2_DEC_BYPASS_MASK) | PDM_CTRL_2_DEC_BYPASS(config->enableFilterBypass); +#endif /* Set the watermark */ base->FIFO_CTRL = PDM_FIFO_CTRL_FIFOWMK(config->fifoWatermark); } @@ -356,6 +361,7 @@ void PDM_Init(PDM_Type *base, const pdm_config_t *config) void PDM_Deinit(PDM_Type *base) { /* disable PDM interface */ + PDM_DisableInterrupts(base, (uint32_t)kPDM_FIFOInterruptEnable | (uint32_t)kPDM_ErrorInterruptEnable); PDM_Enable(base, false); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) diff --git a/drivers/pdm/fsl_pdm.h b/drivers/pdm/fsl_pdm.h index f7c263a18..e8c402df0 100644 --- a/drivers/pdm/fsl_pdm.h +++ b/drivers/pdm/fsl_pdm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PDM_H_ -#define _FSL_PDM_H_ +#ifndef FSL_PDM_H_ +#define FSL_PDM_H_ #include "fsl_common.h" @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 8, 0)) /*!< Version 2.8.0 */ +#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) /*!< Version 2.9.1 */ /*@}*/ /*! @brief PDM XFER QUEUE SIZE */ @@ -31,9 +31,9 @@ /*! @brief PDM return status*/ enum { - kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), /*!< PDM is busy. */ + kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), /*!< PDM is busy. */ #if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) - kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), /*!< PDM clock frequency low */ + kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), /*!< PDM clock frequency low */ #endif kStatus_PDM_FIFO_ERROR = MAKE_STATUS(kStatusGroup_PDM, 2), /*!< PDM FIFO underrun or overflow */ kStatus_PDM_QueueFull = MAKE_STATUS(kStatusGroup_PDM, 3), /*!< PDM FIFO underrun or overflow */ @@ -41,8 +41,8 @@ enum kStatus_PDM_Output_ERROR = MAKE_STATUS(kStatusGroup_PDM, 5), /*!< PDM is output error */ kStatus_PDM_ChannelConfig_Failed = MAKE_STATUS(kStatusGroup_PDM, 6), /*!< PDM channel config failed */ #if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) - kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), /*!< PDM hwvad voice detected */ - kStatus_PDM_HWVAD_Error = MAKE_STATUS(kStatusGroup_PDM, 8), /*!< PDM hwvad error */ + kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), /*!< PDM hwvad voice detected */ + kStatus_PDM_HWVAD_Error = MAKE_STATUS(kStatusGroup_PDM, 8), /*!< PDM hwvad error */ #endif }; @@ -58,10 +58,10 @@ enum _pdm_internal_status { kPDM_StatusDfBusyFlag = (int)PDM_STAT_BSY_FIL_MASK, /*!< Decimation filter is busy processing data */ #if !(defined(FSL_FEATURE_PDM_HAS_NO_FIR_RDY) && FSL_FEATURE_PDM_HAS_NO_FIR_RDY) - kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, /*!< FIR filter data is ready */ + kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, /*!< FIR filter data is ready */ #endif #if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) - kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, /*!< Mic app clock frequency not high enough */ + kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, /*!< Mic app clock frequency not high enough */ #endif kPDM_StatusCh0FifoDataAvaliable = PDM_STAT_CH0F_MASK, /*!< channel 0 fifo data reached watermark level */ kPDM_StatusCh1FifoDataAvaliable = PDM_STAT_CH1F_MASK, /*!< channel 1 fifo data reached watermark level */ @@ -135,15 +135,15 @@ enum _pdm_range_status kPDM_RangeStatusUnderFlowCh6 = PDM_RANGE_STAT_RANGEUNF6_MASK, /*!< channel6 range status underflow */ kPDM_RangeStatusUnderFlowCh7 = PDM_RANGE_STAT_RANGEUNF7_MASK, /*!< channel7 range status underflow */ #endif - kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, /*!< channel0 range status overflow */ - kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, /*!< channel1 range status overflow */ - kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, /*!< channel2 range status overflow */ - kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, /*!< channel3 range status overflow */ + kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, /*!< channel0 range status overflow */ + kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, /*!< channel1 range status overflow */ + kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, /*!< channel2 range status overflow */ + kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, /*!< channel3 range status overflow */ #if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) - kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, /*!< channel4 range status overflow */ - kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, /*!< channel5 range status overflow */ - kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, /*!< channel6 range status overflow */ - kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, /*!< channel7 range status overflow */ + kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, /*!< channel4 range status overflow */ + kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, /*!< channel5 range status overflow */ + kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, /*!< channel6 range status overflow */ + kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, /*!< channel7 range status overflow */ #endif }; #else @@ -160,15 +160,15 @@ enum _pdm_output_status kPDM_OutputStatusUnderFlowCh6 = PDM_OUT_STAT_OUTUNF6_MASK, /*!< channel6 output status underflow */ kPDM_OutputStatusUnderFlowCh7 = PDM_OUT_STAT_OUTUNF7_MASK, /*!< channel7 output status underflow */ #endif - kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK, /*!< channel0 output status overflow */ - kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK, /*!< channel1 output status overflow */ - kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK, /*!< channel2 output status overflow */ - kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK, /*!< channel3 output status overflow */ + kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK, /*!< channel0 output status overflow */ + kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK, /*!< channel1 output status overflow */ + kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK, /*!< channel2 output status overflow */ + kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK, /*!< channel3 output status overflow */ #if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) - kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK, /*!< channel4 output status overflow */ - kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK, /*!< channel5 output status overflow */ - kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK, /*!< channel6 output status overflow */ - kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK, /*!< channel7 output status overflow */ + kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK, /*!< channel4 output status overflow */ + kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK, /*!< channel5 output status overflow */ + kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK, /*!< channel6 output status overflow */ + kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK, /*!< channel7 output status overflow */ #endif }; #endif @@ -186,10 +186,10 @@ typedef enum _pdm_dc_remover /*! @brief PDM DC remover configurations */ typedef enum _pdm_dc_remover { - kPDM_DcRemoverCutOff21Hz = 0U, /*!< DC remover cut off 21HZ */ - kPDM_DcRemoverCutOff83Hz = 1U, /*!< DC remover cut off 83HZ */ + kPDM_DcRemoverCutOff21Hz = 0U, /*!< DC remover cut off 21HZ */ + kPDM_DcRemoverCutOff83Hz = 1U, /*!< DC remover cut off 83HZ */ kPDM_DcRemoverCutOff152Hz = 2U, /*!< DC remover cut off 152HZ */ - kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ + kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ } pdm_dc_remover_t; #endif @@ -241,7 +241,7 @@ enum _pdm_data_width kPDM_DataWwidth24 = 3U, /*!< PDM data width 24bit */ kPDM_DataWwidth32 = 4U, /*!< PDM data width 32bit */ #else - kPDM_DataWdith16 = 2U, /*!< PDM data width 16bit */ + kPDM_DataWdith16 = 2U, /*!< PDM data width 16bit */ #endif }; @@ -264,6 +264,9 @@ typedef struct _pdm_config { bool enableDoze; /*!< This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted */ +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + bool enableFilterBypass; /*!< Switchable bypass path for the decimation filter */ +#endif uint8_t fifoWatermark; /*!< Watermark value for FIFO */ pdm_df_quality_mode_t qualityMode; /*!< Quality mode */ uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ @@ -303,9 +306,9 @@ typedef enum _pdm_hwvad_filter_status /*! @brief PDM voice activity detector user configuration structure */ typedef struct _pdm_hwvad_config { - uint8_t channel; /*!< Which channel uses voice activity detector */ - uint8_t initializeTime; /*!< Number of frames or samples to initialize voice activity detector. */ - uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ + uint8_t channel; /*!< Which channel uses voice activity detector */ + uint8_t initializeTime; /*!< Number of frames or samples to initialize voice activity detector. */ + uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ uint8_t inputGain; /*!< Voice activity detector input gain */ uint32_t frameTime; /*!< Voice activity frame time */ @@ -371,19 +374,19 @@ typedef struct _pdm_hwvad_notification /*! @brief PDM handle structure */ struct _pdm_handle { - uint32_t state; /*!< Transfer status */ - pdm_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ + uint32_t state; /*!< Transfer status */ + pdm_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ pdm_transfer_t pdmQueue[PDM_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ size_t transferSize[PDM_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ volatile uint8_t queueUser; /*!< Index for user to queue transfer */ volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ - uint32_t format; /*!< data format */ - uint8_t watermark; /*!< Watermark value */ - uint8_t startChannel; /*!< end channel */ - uint8_t channelNums; /*!< Enabled channel number */ + uint32_t format; /*!< data format */ + uint8_t watermark; /*!< Watermark value */ + uint8_t startChannel; /*!< end channel */ + uint8_t channelNums; /*!< Enabled channel number */ }; /******************************************************************************* @@ -453,6 +456,7 @@ static inline void PDM_Enable(PDM_Type *base, bool enable) } } +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) /*! * @brief Enables/disables DOZE. * @@ -471,7 +475,7 @@ static inline void PDM_EnableDoze(PDM_Type *base, bool enable) base->CTRL_1 &= ~PDM_CTRL_1_DOZEN_MASK; } } - +#endif /*! * @brief Enables/disables debug mode for PDM. * The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode. @@ -1210,4 +1214,4 @@ void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle); /*! @} */ -#endif /* _FSL_PDM_H_ */ +#endif /* FSL_PDM_H_ */ diff --git a/drivers/pdm/fsl_pdm_edma.h b/drivers/pdm/fsl_pdm_edma.h index 4da78192f..a1ca0442f 100644 --- a/drivers/pdm/fsl_pdm_edma.h +++ b/drivers/pdm/fsl_pdm_edma.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PDM_EDMA_H_ -#define _FSL_PDM_EDMA_H_ +#ifndef FSL_PDM_EDMA_H_ +#define FSL_PDM_EDMA_H_ #include "fsl_edma.h" #include "fsl_pdm.h" diff --git a/drivers/pint/fsl_pint.c b/drivers/pint/fsl_pint.c index 6a03d4e2c..28745b270 100644 --- a/drivers/pint/fsl_pint.c +++ b/drivers/pint/fsl_pint.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2023 NXP - * All rights reserved. + * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,8 +24,14 @@ static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + /*! @brief Callback function array for SECPINT(s). */ static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; #else + +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[1] = PINT_IRQS; +#else /*! @brief Irq number array */ static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_PINT_INTERRUPT_COMBINE */ #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /*! @brief Callback function array for PINT(s). */ @@ -561,7 +566,7 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) /* Get the right security pint irq index in array */ - if (base == SECPINT) + if ((base == SECPINT) && ((uint32_t)pintIdx < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)) { pintIdx = (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); diff --git a/drivers/pint/fsl_pint.h b/drivers/pint/fsl_pint.h index 5148b53aa..41dae8c45 100644 --- a/drivers/pint/fsl_pint.h +++ b/drivers/pint/fsl_pint.h @@ -1,13 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2023 NXP - * All rights reserved. + * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ +#ifndef FSL_PINT_H_ +#define FSL_PINT_H_ #include "fsl_common.h" @@ -24,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 11)) +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 13)) /*@}*/ /* Number of interrupt line supported by PINT */ @@ -578,4 +577,4 @@ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); /*@}*/ -#endif /* _FSL_PINT_H_ */ +#endif /* FSL_PINT_H_ */ diff --git a/drivers/port/fsl_port.h b/drivers/port/fsl_port.h index d7cfafe81..ded800567 100644 --- a/drivers/port/fsl_port.h +++ b/drivers/port/fsl_port.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PORT_H_ -#define _FSL_PORT_H_ +#ifndef FSL_PORT_H_ +#define FSL_PORT_H_ #include "fsl_common.h" @@ -676,4 +676,4 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base) /*! @}*/ -#endif /* _FSL_PORT_H_ */ +#endif /* FSL_PORT_H_ */ diff --git a/drivers/puf_v3/fsl_puf_v3.c b/drivers/puf_v3/fsl_puf_v3.c index d5c457a55..de5ff296b 100644 --- a/drivers/puf_v3/fsl_puf_v3.c +++ b/drivers/puf_v3/fsl_puf_v3.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 NXP + * Copyright 2020,2023 NXP * All rights reserved. * * @@ -33,7 +33,7 @@ #define kPUF_Zeroize (0x2fu) typedef uint32_t puf_last_operation_t; -#define PUF_KEY_OPERATION_CONTEXT_TYPE (0x10 << 16) +#define PUF_KEY_OPERATION_CONTEXT_TYPE (0x10UL << 16UL) #define PUF_CONTEXT_GENERIC_KEY_TYPE (0x0u) #define PUF_CONTEXT_KEY_LEN_MASK (0x1fffu) @@ -56,7 +56,7 @@ static status_t puf_waitForInit(PUF_Type *base) } /* return status */ - if (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK)) + if (0U != (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK))) { status = kStatus_Success; } @@ -99,7 +99,7 @@ static status_t puf_makeStatus(PUF_Type *base, puf_last_operation_t operation) } else { - status = MAKE_STATUS(kStatusGroup_PUF, result); + status = MAKE_STATUS((int32_t)kStatusGroup_PUF, (int32_t)result); } } @@ -134,8 +134,14 @@ status_t PUF_Init(PUF_Type *base, puf_config_t *conf) /* Enable PUF clock */ CLOCK_EnableClock(kCLOCK_Puf); + + /* Clear the PUF peripheral reset */ + RESET_ClearPeripheralReset(kPUF_RST_SHIFT_RSTn); + /* Reset PUF */ +#if defined(FSL_FEATURE_PUF_HAS_RESET) && FSL_FEATURE_PUF_HAS_RESET RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_RESET */ /* Set configuration from SRAM */ base->SRAM_CFG |= PUF_SRAM_CFG_CKGATING(conf->CKGATING); @@ -150,7 +156,7 @@ status_t PUF_Init(PUF_Type *base, puf_config_t *conf) if ((status != kStatus_Success) || ((PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK) != (base->AR & (PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK)))) { - puf_powerCycle(base, conf); + (void)puf_powerCycle(base, conf); status = puf_waitForInit(base); } @@ -178,7 +184,7 @@ void PUF_Deinit(PUF_Type *base, puf_config_t *conf) { base->SRAM_CFG = 0x0u; - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); CLOCK_DisableClock(kCLOCK_Puf); } @@ -191,7 +197,7 @@ void PUF_Deinit(PUF_Type *base, puf_config_t *conf) * * @param base PUF peripheral base address * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the enroll operation. * @return Status of enroll operation. */ @@ -201,14 +207,14 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo uint32_t *activationCodeAligned = NULL; register uint32_t temp32 = 0; - /* check that activation code buffer size is at least 996 bytes */ + /* check that activation code buffer size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) { return kStatus_InvalidArgument; } /* only work with aligned and valid activationCode */ - if ((0x3u & (uintptr_t)activationCode) || (activationCode == NULL)) + if ((0U != (0x3u & (uintptr_t)activationCode)) || (activationCode == NULL)) { return kStatus_InvalidArgument; } @@ -265,7 +271,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo * * @param base PUF peripheral base address * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the start operation. * return Status of start operation. */ @@ -275,17 +281,17 @@ status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activat const uint32_t *activationCodeAligned = NULL; register uint32_t temp32 = 0; - /* check that activation code size is at least 996 bytes */ + /* check that activation code size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) { return kStatus_InvalidArgument; } - /* Set activationCodeSize to 996 bytes */ + /* Set activationCodeSize to FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ activationCodeSize = PUF_ACTIVATION_CODE_SIZE; /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) + if ((0U != (0x3u & (uintptr_t)activationCode)) || (activationCode == NULL)) { return kStatus_InvalidArgument; } @@ -418,18 +424,18 @@ status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDes /* check for valid key size. */ /* must be 8byte multiple */ - if (keySize & 0x7u) + if (0U != (keySize & 0x7u)) { return kStatus_InvalidArgument; } /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) { return kStatus_InvalidArgument; } /* only work with aligned key */ - if (0x3u & (uintptr_t)key) + if (0U != (0x3u & (uintptr_t)key)) { return kStatus_InvalidArgument; } @@ -443,7 +449,7 @@ status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDes context[3] = keyCtx->userCtx1; /* set key destination */ - base->KEY_DEST = keyDest; + base->DATA_DEST = keyDest; /* begin */ base->CR = PUF_CR_GET_KEY_MASK; @@ -454,15 +460,15 @@ status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDes } /* send context and read output data while busy */ - while (0 != (base->SR & PUF_SR_BUSY_MASK)) + while (0U != (base->SR & PUF_SR_BUSY_MASK)) { - if ((0 != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) + if ((0U != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) { base->DIR = context[idx]; idx++; } - if ((0 != (PUF_SR_DO_REQUEST_MASK & base->SR)) && (kPUF_KeyDestRegister == keyDest)) + if ((0U != (PUF_SR_DO_REQUEST_MASK & base->SR)) && (kPUF_KeyDestRegister == keyDest)) { if (keySize >= sizeof(uint32_t)) { @@ -513,12 +519,12 @@ status_t PUF_WrapGeneratedRandom( /* check for valid key size. */ /* must be 8byte multiple */ - if (keySize & 0x7u) + if (0U != (keySize & 0x7u)) { return kStatus_InvalidArgument; } /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) { return kStatus_InvalidArgument; } @@ -530,7 +536,7 @@ status_t PUF_WrapGeneratedRandom( } /* only work with aligned key code */ - if (0x3u & (uintptr_t)keyCode) + if (0U != (0x3u & (uintptr_t)keyCode)) { return kStatus_InvalidArgument; } @@ -538,7 +544,7 @@ status_t PUF_WrapGeneratedRandom( keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; /* fill in key context */ - context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & 0x1FFF); + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & 0x1FFFu); context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; context[2] = keyCtx->userCtx0; context[3] = keyCtx->userCtx1; @@ -613,12 +619,12 @@ status_t PUF_Wrap( /* check for valid userKey size. */ /* must be 8byte multiple */ - if (userKeySize & 0x7u) + if (0U != (userKeySize & 0x7u)) { return kStatus_InvalidArgument; } /* if userKeySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((userKeySize > 128u) && !((userKeySize == 256u) || (userKeySize == 384u) || (userKeySize == 512u))) + if ((userKeySize > 128u) && !((userKeySize == 256u) || (userKeySize == 384u) || (userKeySize == 512u))) { return kStatus_InvalidArgument; } @@ -630,7 +636,7 @@ status_t PUF_Wrap( } /* only work with aligned userKey and key code */ - if ((0x3u & (uintptr_t)userKey) || (0x3u & (uintptr_t)keyCode)) + if (0U != ((0x3u & (uintptr_t)userKey)) || (0U != (0x3u & (uintptr_t)keyCode))) { return kStatus_InvalidArgument; } @@ -639,7 +645,7 @@ status_t PUF_Wrap( keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; /* fill in key context */ - context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((userKeySize * 8u) & 0x1FFF); + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((userKeySize * 8u) & 0x1FFFu); context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; context[2] = keyCtx->userCtx0; context[3] = keyCtx->userCtx1; @@ -721,7 +727,7 @@ status_t PUF_Unwrap( } /* only work with aligned key and key code */ - if ((0x3u & (uintptr_t)key) || (0x3u & (uintptr_t)keyCode)) + if ((0U != (0x3u & (uintptr_t)key)) || (0U != (0x3u & (uintptr_t)keyCode)) || (keyCode == NULL)) { return kStatus_InvalidArgument; } @@ -730,7 +736,7 @@ status_t PUF_Unwrap( keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; /* set key destination */ - base->KEY_DEST = keyDest; + base->DATA_DEST = keyDest; /* begin */ base->CR = PUF_CR_UNWRAP_MASK; @@ -799,18 +805,18 @@ status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size) /* check for valid size. */ /* must be 8byte multiple */ - if (size & 0x7u) + if (0U != (size & 0x7u)) { return kStatus_InvalidArgument; } /* if size > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ - else if ((size > 128u) && !((size == 256u) || (size == 384u) || (size == 512u))) + if ((size > 128u) && !((size == 256u) || (size == 384u) || (size == 512u))) { return kStatus_InvalidArgument; } /* only work with aligned data buffer */ - if (0x3u & (uintptr_t)data) + if (0U != (0x3u & (uintptr_t)data)) { return kStatus_InvalidArgument; } @@ -821,6 +827,8 @@ status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size) dataAligned = (uint32_t *)(uintptr_t)data; /* begin */ + base->DATA_DEST = PUF_DATA_DEST_DEST_DOR_MASK; + base->CR = PUF_CR_GENERATE_RANDOM_MASK; /* wait till command is accepted */ @@ -927,3 +935,66 @@ status_t PUF_Test(PUF_Type *base, uint8_t *score) return status; } + +/*! + * brief Set lock of PUF operation + * + * Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. + * Note: Only secure-privilege code can change the security level. + * + * @param base PUF peripheral base address + * @param securityLevel Security level of PUF block. + * @return Status of the test operation. + */ +status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel) +{ + uint32_t sec_lock_option = 0u; + + if ((securityLevel != kPUF_NonsecureUser) && (securityLevel != kPUF_NonsecurePrivilege) && + (securityLevel != kPUF_SecureUser) && (securityLevel != kPUF_SecurePrivilege)) + { + return kStatus_InvalidArgument; + } + + /* Wait until PUF is in IDLE */ + while ((base->SR & PUF_SR_BUSY_MASK) != 0u) + { + } + + /* Prepare SEC_LOCK option word */ + /* [1:0] - Security level */ + /* [3:2] - anti-pole of security level [1:0] */ + /* [15:4] - PATTERN: This field must be written as 0xAC5 */ + sec_lock_option = SEC_LOCK_PATTERN | securityLevel; + + /* Apply setings */ + base->SEC_LOCK = sec_lock_option; + + /* Check if the security level is same as the level written */ + if (securityLevel != base->SEC_LOCK) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief Set App Context mask + * + * This function sets Application defined context mask used in conjunction with key user context 2. + * Whenever bit in this register is 1, corresponding bit in user context 2 provided + * during key code creation should be zero only. + * + * This register is only modifiable by task running at secure-privilege level. + * + * @param base PUF peripheral base address + * @param appCtxMask Value of the Application defined context mask. + * @return Status of the test operation. + */ +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask) +{ + base->APP_CTX_MASK = appCtxMask; + + return kStatus_Success; +} diff --git a/drivers/puf_v3/fsl_puf_v3.h b/drivers/puf_v3/fsl_puf_v3.h index f360447f4..1acf08484 100644 --- a/drivers/puf_v3/fsl_puf_v3.h +++ b/drivers/puf_v3/fsl_puf_v3.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018,2023 NXP * All rights reserved. * * @@ -23,15 +23,19 @@ */ /*! @name Driver version */ /*@{*/ -/*! @brief PUFv3 driver version. Version 2.0.0. +/*! @brief PUFv3 driver version. Version 2.0.2. * - * Current version: 2.0.0 + * Current version: 2.0.2 * * Change log: + * - 2.0.2 + * - Fix MISRA issue in driver. + * - 2.0.1 + * - Fix PUF initialization issue and update driver to reflect SoC header changes. * - 2.0.0 * - Initial version. */ -#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ #define kPUF_EndianLittle (0x0u) @@ -61,6 +65,12 @@ typedef uint32_t puf_key_scope_t; #define kPUF_Failure (0xFFu) typedef uint32_t puf_result_code_t; +#define kPUF_NonsecureUser (0xCu) /* b1100 */ +#define kPUF_NonsecurePrivilege (0x9u) /* b1001 */ +#define kPUF_SecureUser (0x6u) /* b0110 */ +#define kPUF_SecurePrivilege (0x3u) /* b0011 */ +typedef uint32_t puf_sec_level_t; + typedef struct { puf_endianness_t dataEndianness; @@ -75,10 +85,11 @@ typedef struct uint32_t userCtx1; } puf_key_ctx_t; -#define PUF_ACTIVATION_CODE_SIZE 996 -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + x) + 0x10u * (x / 0x32u)) +#define PUF_ACTIVATION_CODE_SIZE (size_t)(FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE) +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + (x)) + 0x10u * ((x) / 0x32u)) +#define SEC_LOCK_PATTERN 0xAC50u -enum _puf_status +enum { kStatus_PUF_OperationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 0xA5), kStatus_PUF_AcNotForThisProductPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase1), @@ -138,7 +149,7 @@ void PUF_Deinit(PUF_Type *base, puf_config_t *conf); * * @param base PUF peripheral base address * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the enroll operation. * @return Status of enroll operation. */ @@ -153,7 +164,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo * * @param base PUF peripheral base address * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the start operation. * return Status of start operation. */ @@ -271,7 +282,7 @@ status_t PUF_Test(PUF_Type *base, uint8_t *score); * This function blocks PUF commands specified by mask parameter. * * @param base PUF peripheral base address - * @param score Value of the PUF Score that was obtained during the enroll operation. + * @param mask Mask of parameters which should be blocked until power-cycle. * @return Status of the test operation. */ static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) @@ -279,6 +290,34 @@ static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) base->CONFIG |= mask; } +/*! + * brief Set lock of PUF operation + * + * Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. + * Note: Only security level defined in SEC_LOCK register can use PUFv3 or change its security level. + * Default setting after leaving ROM is Secure-Privilege + * + * @param base PUF peripheral base address + * @param securityLevel Security level of PUF block. + * @return Status of the test operation. + */ +status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel); + +/*! + * brief Set App Context mask + * + * This function sets Application defined context mask used in conjunction with key user context 2. + * Whenever bit in this register is 1, corresponding bit in user context 2 provided + * during key code creation should be zero only. + * + * This register is only modifiable by task running at secure-privilege level. + * + * @param base PUF peripheral base address + * @param appCtxMask Value of the Application defined context mask. + * @return Status of the test operation. + */ +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/drivers/pwm/fsl_pwm.c b/drivers/pwm/fsl_pwm.c index f84e6c2bd..f227249ef 100644 --- a/drivers/pwm/fsl_pwm.c +++ b/drivers/pwm/fsl_pwm.c @@ -25,6 +25,14 @@ */ static uint32_t PWM_GetInstance(PWM_Type *base); +#if defined(PWM_RSTS) +#define PWM_RESETS_ARRAY PWM_RSTS +#elif defined(FLEXPWM_RSTS) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS +#elif defined(FLEXPWM_RSTS_N) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS_N +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -36,6 +44,11 @@ static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(PWM_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_pwmResets[] = PWM_RESETS_ARRAY; +#endif + /*! @brief Temporary PWM duty cycle. */ static uint8_t s_pwmGetPwmDutyCycle[FSL_FEATURE_PWM_SUBMODULE_COUNT][PWM_SUBMODULE_CHANNEL] = {{0}}; @@ -80,6 +93,165 @@ static uint32_t PWM_GetInstance(PWM_Type *base) return instance; } +/*! + * brief Set register about period on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + */ +static void PWM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Set register about dutycycle on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + */ +static void PWM_SetDutycycleRegister(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t mode, + uint16_t pulseCnt, + uint16_t pwmHighPulse) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM dutycycle for a signed center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_CenterAligned: + /* Setup the PWM dutycycle for an unsigned center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_SignedEdgeAligned: + modulo = (pulseCnt >> 1U); + + /* Setup the PWM dutycycle for a signed edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM dutycycle for a unsigned edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + default: + assert(false); + break; + } +} + /*! * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. * @@ -114,6 +286,10 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(PWM_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pwmResets[PWM_GetInstance(base)]); +#endif + /* Clear the fault status flags */ base->FSTS |= PWM_FSTS_FFLAG_MASK; @@ -184,7 +360,12 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t base->SM[subModule].CTRL = reg; /* Set PWM output normal */ +#if defined(PWM_MASK_UPDATE_MASK) + base->MASK &= (uint16_t)(~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | + PWM_MASK_MASKB_MASK | PWM_MASK_UPDATE_MASK_MASK)); +#else base->MASK &= ~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK); +#endif base->DTSRCSEL = 0U; @@ -280,7 +461,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config) * Array size should not be more than 2 as each submodule has 2 pins to output PWM * param mode PWM operation mode, options available in enumeration ::pwm_mode_t * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz PWM main counter clock in Hz. + * param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. * * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise */ @@ -299,7 +482,6 @@ status_t PWM_SetupPwm(PWM_Type *base, uint32_t pwmClock; uint16_t pulseCnt = 0, pwmHighPulse = 0; - uint16_t modulo = 0; uint8_t i, polarityShift = 0, outputEnableShift = 0; for (i = 0; i < numOfChnls; i++) @@ -322,114 +504,15 @@ status_t PWM_SetupPwm(PWM_Type *base, pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; /* Setup the different match registers to generate the PWM signal */ - switch (mode) + if (i == 0U) { - case kPWM_SignedCenterAligned: - /* Setup the PWM period for a signed center aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - break; - case kPWM_CenterAligned: - /* Setup the PWM period for an unsigned center aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - break; - case kPWM_SignedEdgeAligned: - /* Setup the PWM period for a signed edge aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - break; - case kPWM_EdgeAligned: - /* Setup the PWM period for a unsigned edge aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - assert(false); - break; + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, mode, pulseCnt); } + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, chnlParams->pwmChannel, mode, pulseCnt, pwmHighPulse); + /* Setup register shift values based on the channel being configured. * Also setup the deadtime value */ @@ -636,98 +719,96 @@ void PWM_UpdatePwmDutycycleHighAccuracy( pulseCnt = modulo * 2U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - else - { - assert(false); - } break; case kPWM_CenterAligned: pulseCnt = base->SM[subModule].VAL1 + 1U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - assert(false); - } break; case kPWM_SignedEdgeAligned: modulo = base->SM[subModule].VAL1 + 1U; pulseCnt = modulo * 2U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - assert(false); - } break; case kPWM_EdgeAligned: pulseCnt = base->SM[subModule].VAL1 + 1U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - else - { - assert(false); - } break; default: assert(false); break; } + + /* Update register about dutycycle */ + if (kPWM_PwmA == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmA, currPwmMode, pulseCnt, pwmHighPulse); + } + else if (kPWM_PwmB == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmB, currPwmMode, pulseCnt, pwmHighPulse); + } + else + { + ; /* Intentional empty */ + } + if (kPWM_PwmX != pwmSignal) { /* Get the pwm duty cycle */ - s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle / 65535U); + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle * 100U / 65535U); } } +/*! + * brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original dutycycle or update new dutycycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle) +{ + uint16_t pwmHighPulse = 0; + + assert(pwmSignal != kPWM_PwmX); + + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, currPwmMode, pulseCnt); + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, pwmSignal, currPwmMode, pulseCnt, pwmHighPulse); + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)((dutyCycle * 100U) / 65535U); +} + /*! * brief Sets up the PWM input capture * @@ -747,6 +828,7 @@ void PWM_SetupInputCapture(PWM_Type *base, uint16_t reg = 0; switch (pwmChannel) { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA case kPWM_PwmA: /* Setup the capture paramters for PWM A pin */ reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | @@ -768,6 +850,8 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM A pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB case kPWM_PwmB: /* Setup the capture paramters for PWM B pin */ reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | @@ -789,6 +873,8 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM B pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX case kPWM_PwmX: reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | @@ -809,6 +895,7 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM X pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ default: assert(false); break; @@ -1213,7 +1300,9 @@ void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_presc */ void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero) { +#if !defined(PWM_MASK_UPDATE_MASK) uint16_t reg = base->SM[subModule].CTRL2; +#endif uint16_t mask; if (kPWM_PwmA == pwmChannel) @@ -1240,12 +1329,17 @@ void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_ base->MASK &= ~mask; } +#if defined(PWM_MASK_UPDATE_MASK) + /* Update output mask bits immediately with UPDATE_MASK bit */ + base->MASK |= PWM_MASK_UPDATE_MASK(0x01UL << (uint8_t)subModule); +#else /* Select local force signal */ base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; /* Issue a local Force trigger event */ base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; /* Restore the source of FORCE OUTPUT signal */ base->SM[subModule].CTRL2 = reg; +#endif } /*! @@ -1341,6 +1435,7 @@ void PWM_SetChannelOutput(PWM_Type *base, */ status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles) { + assert(subModule != kPWM_Module_0); uint16_t reg = base->SM[subModule].CTRL2; /* Clear LDOK bit if it is set */ diff --git a/drivers/pwm/fsl_pwm.h b/drivers/pwm/fsl_pwm.h index 3786f6473..0de61c1c0 100644 --- a/drivers/pwm/fsl_pwm.h +++ b/drivers/pwm/fsl_pwm.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PWM_H_ -#define _FSL_PWM_H_ +#ifndef FSL_PWM_H_ +#define FSL_PWM_H_ #include "fsl_common.h" @@ -20,7 +20,7 @@ ******************************************************************************/ /*! @name Driver version */ /*@{*/ -#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) /*!< Version 2.6.1 */ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 3)) /*!< Version 2.8.3 */ /*@}*/ /*! Number of bits per submodule for software output control */ @@ -34,7 +34,9 @@ typedef enum _pwm_submodule kPWM_Module_0 = 0U, /*!< Submodule 0 */ kPWM_Module_1, /*!< Submodule 1 */ kPWM_Module_2, /*!< Submodule 2 */ +#if defined(FSL_FEATURE_PWM_SUBMODULE_COUNT) && (FSL_FEATURE_PWM_SUBMODULE_COUNT > 3U) kPWM_Module_3 /*!< Submodule 3 */ +#endif /* FSL_FEATURE_PWM_SUBMODULE_COUNT */ } pwm_submodule_t; /*! @brief List of PWM channels in each module */ @@ -220,12 +222,18 @@ typedef enum _pwm_interrupt_enable kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ @@ -243,12 +251,18 @@ typedef enum _pwm_status_flags kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ @@ -261,12 +275,18 @@ typedef enum _pwm_status_flags /*! @brief List of PWM DMA options */ typedef enum _pwm_dma_enable { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ } pwm_dma_enable_t; /*! @brief List of PWM capture DMA enable source select */ @@ -488,7 +508,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config); * Array size should not be more than 2 as each submodule has 2 pins to output PWM * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz PWM main counter clock in Hz. + * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. * * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise */ @@ -561,6 +583,36 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base, void PWM_UpdatePwmDutycycleHighAccuracy( PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); +/*! + * @brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * @param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * @param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original duty cycle or update new duty cycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle); + /*! @}*/ /*! @@ -1247,18 +1299,24 @@ static inline void PWM_SetFilterSampleCount(PWM_Type *base, { switch(pwmChannel) { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA case kPWM_PwmA: base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK); base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_CNT(filterSampleCount); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB case kPWM_PwmB: base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK); base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_CNT(filterSampleCount); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX case kPWM_PwmX: base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK); base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_CNT(filterSampleCount); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ default: assert(false); break; @@ -1280,18 +1338,24 @@ static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, { switch(pwmChannel) { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA case kPWM_PwmA: base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_PER_MASK); base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_PER(filterSamplePeriod); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB case kPWM_PwmB: base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_PER_MASK); base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_PER(filterSamplePeriod); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX case kPWM_PwmX: base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_PER_MASK); base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_PER(filterSamplePeriod); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ default: assert(false); break; @@ -1305,4 +1369,4 @@ static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, /*! @}*/ -#endif /* _FSL_PWM_H_ */ +#endif /* FSL_PWM_H_ */ diff --git a/drivers/qdc/fsl_qdc.c b/drivers/qdc/fsl_qdc.c new file mode 100644 index 000000000..75158b976 --- /dev/null +++ b/drivers/qdc/fsl_qdc.c @@ -0,0 +1,645 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_qdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qdc" +#endif + +#define QDC_CTRL_W1C_FLAGS (QDC_CTRL_HIRQ_MASK | QDC_CTRL_XIRQ_MASK | QDC_CTRL_DIRQ_MASK | QDC_CTRL_CMPIRQ_MASK) +#if (defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#else +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_SABIRQ_MASK | QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#endif + +#if defined(QDC_RSTS) +#define QDC_RESETS_ARRAY QDC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for QDC module. + * + * @param base QDC peripheral base address + */ +static uint32_t QDC_GetInstance(QDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to QDC bases for each instance. */ +static QDC_Type *const s_qdcBases[] = QDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to QDC clocks for each instance. */ +static const clock_ip_name_t s_qdcClocks[] = QDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_qdcResets[] = QDC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t QDC_GetInstance(QDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qdcBases); instance++) + { + if (s_qdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qdcBases)); + + return instance; +} + +/*! + * brief Initialization for the QDC module. + * + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_config_t". + */ +void QDC_Init(QDC_Type *base, const qdc_config_t *config) +{ + assert(NULL != config); + + uint16_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_qdcResets[QDC_GetInstance(base)]); +#endif + + /* QDC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_HIP_MASK | QDC_CTRL_HNE_MASK | QDC_CTRL_REV_MASK | + QDC_CTRL_PH1_MASK | QDC_CTRL_XIP_MASK | QDC_CTRL_XNE_MASK | QDC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kQDC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HIP_MASK; + if (kQDC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= QDC_CTRL_REV_MASK; + } + if (kQDC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= QDC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kQDC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XIP_MASK; + if (kQDC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= QDC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* QDC_FILT. */ + base->FILT = QDC_FILT_FILT_CNT(config->filterCount) | QDC_FILT_FILT_PER(config->filterSamplePeriod) +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + | QDC_FILT_FILT_PRSC(config->filterPrescaler) +#endif + ; + + /* QDC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(QDC_CTRL2_W1C_FLAGS | QDC_CTRL2_OUTCTL_MASK | QDC_CTRL2_REVMOD_MASK | + QDC_CTRL2_MOD_MASK | QDC_CTRL2_UPDPOS_MASK | QDC_CTRL2_UPDHLD_MASK)); + if (kQDC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= QDC_CTRL2_OUTCTL_MASK; + } + if (kQDC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= QDC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= QDC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + /* QDC_CTRL3. */ + tmp16 = base->CTRL3 & (uint16_t)(~(QDC_CTRL3_PMEN_MASK | QDC_CTRL3_PRSC_MASK)); + if (config->enablePeriodMeasurementFunction) + { + tmp16 |= QDC_CTRL3_PMEN_MASK; + /* Set prescaler value. */ + tmp16 |= ((uint16_t)config->prescalerValue << QDC_CTRL3_PRSC_SHIFT); + } + base->CTRL3 = tmp16; +#endif + + /* QDC_UCOMP & QDC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* QDC_UINIT & QDC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +/*! + * brief De-initialization for the QDC module. + * + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with + * the operations like: + * - Disable the clock for QDC module. + * + * param base QDC peripheral base address. + */ +void QDC_Deinit(QDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get an available pre-defined settings for QDC's configuration. + * + * This function initializes the QDC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * config->prescalerValue = kQDC_ClockDiv1; + * config->enablePeriodMeasurementFunction = true; + * endcode + * param config Pointer to a variable of configuration structure. See to "qdc_config_t". + */ +void QDC_GetDefaultConfig(qdc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableReverseDirection = false; + config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + config->prescalerValue = kQDC_ClockDiv1; + config->enablePeriodMeasurementFunction = true; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + config->filterPrescaler = kQDC_FilterPrescalerDiv1; +#endif +} + +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base QDC peripheral base address. + */ +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS); + + tmp16 |= QDC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. + */ +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + tmp16 = 0U; + } + else + { + tmp16 = QDC_TST_TEN_MASK | QDC_TST_TCE_MASK | QDC_TST_TEST_PERIOD(config->signalPeriod) | + QDC_TST_TEST_COUNT(config->signalCount); + if (kQDC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= QDC_TST_QDN_MASK; + } + } + + base->TST = tmp16; +} + +/*! + * brief Enable watchdog for QDC module. + * + * param base QDC peripheral base address + * param enable Enables or disables the watchdog + */ +void QDC_EnableWatchdog(QDC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= QDC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +/*! + * brief Get the status flags. + * + * param base QDC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_qdc_status_flags". + */ +uint32_t QDC_GetStatusFlags(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionFlag; + } + if (0U != (QDC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseFlag; + } + if (0U != (QDC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutFlag; + } + if (0U != (QDC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareFlag; + } + + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeFlag; + } +#endif + if (0U != (QDC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverFlag; + } + if (0U != (QDC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderFlag; + } + if (0U != (QDC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_LastCountDirectionFlag; + } + + return ret32; +} + +/*! + * brief Clear the status flags. + * + * param base QDC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". + */ +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionFlag & mask)) + { + tmp16 |= QDC_CTRL_HIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseFlag & mask)) + { + tmp16 |= QDC_CTRL_XIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= QDC_CTRL_DIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareFlag & mask)) + { + tmp16 |= QDC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= QDC_CTRL2_SABIRQ_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverFlag & mask)) + { + tmp16 |= QDC_CTRL2_ROIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderFlag & mask)) + { + tmp16 |= QDC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Enable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Disable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~QDC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +/*! + * brief Get the enabled interrupts' flags. + * + * param base QDC peripheral base address. + * + * return Mask value of enabled interrupts. + */ +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionInterruptEnable; + } + if (0U != (QDC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseInterruptEnable; + } + if (0U != (QDC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutInterruptEnable; + } + if (0U != (QDC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareInerruptEnable; + } + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable; + } +#endif + if (0U != (QDC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverInterruptEnable; + } + if (0U != (QDC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +/*! + * brief Set initial position value for QDC module. + * + * param base QDC peripheral base address + * param value Positive initial value + */ +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +/*! + * brief Get the current position counter's value. + * + * param base QDC peripheral base address. + * + * return Current position counter's value. + */ +uint32_t QDC_GetPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base QDC peripheral base address. + * + * return Hold position counter's value. + */ +uint32_t QDC_GetHoldPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/drivers/qdc/fsl_qdc.h b/drivers/qdc/fsl_qdc.h new file mode 100644 index 000000000..5a79f3de1 --- /dev/null +++ b/drivers/qdc/fsl_qdc.h @@ -0,0 +1,585 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_QDC_H_ +#define FSL_QDC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup qdc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_QDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _qdc_interrupt_enable +{ + kQDC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kQDC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kQDC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kQDC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeInterruptEnable = + (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ +#endif + kQDC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kQDC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ +}; + +/*! + * @brief Status flag mask. + * + * These flags indicate the counter's events. + */ +enum _qdc_status_flags +{ + kQDC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kQDC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kQDC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kQDC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ +#endif + kQDC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kQDC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kQDC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ +}; + +/*! + * @brief Signal status flag mask. + * + * These flags indicate the counter's signal. + */ +enum _qdc_signal_status_flags +{ + kQDC_RawHOMEStatusFlag = QDC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kQDC_RawINDEXStatusFlag = QDC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kQDC_RawPHBStatusFlag = QDC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kQDC_RawPHAEXStatusFlag = QDC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kQDC_FilteredHOMEStatusFlag = QDC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kQDC_FilteredINDEXStatusFlag = QDC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kQDC_FilteredPHBStatusFlag = QDC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kQDC_FilteredPHAStatusFlag = QDC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ +}; + +/*! + * @brief Define HOME signal's trigger mode. + * + * The QDC would count the trigger from HOME signal line. + */ +typedef enum _qdc_home_trigger_mode +{ + kQDC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kQDC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_home_trigger_mode_t; + +/*! + * @brief Define INDEX signal's trigger mode. + * + * The QDC would count the trigger from INDEX signal line. + */ +typedef enum _qdc_index_trigger_mode +{ + kQDC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kQDC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_index_trigger_mode_t; + +/*! + * @brief Define type for decoder work mode. + * + * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, + * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction + * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 + * means counting down. Otherwise, the direction is reversed. + */ +typedef enum _qdc_decoder_work_mode +{ + kQDC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kQDC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + direction. */ +} qdc_decoder_work_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _qdc_position_match_mode +{ + kQDC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + position counters (POS) and the compare value (COMP). */ + kQDC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} qdc_position_match_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _qdc_revolution_count_condition +{ + kQDC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kQDC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} qdc_revolution_count_condition_t; + +/*! + * @brief Define type for direction of self test generated signal. + */ +typedef enum _qdc_self_test_direction +{ + kQDC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kQDC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} qdc_self_test_direction_t; + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) +/*! + * @brief Define prescaler value for clock in CTRL3. + * + * The clock is prescaled by a value of 2^PRSC which means that the prescaler logic + * can divide the clock by a minimum of 1 and a maximum of 32,768. + */ +typedef enum _qdc_prescaler +{ + kQDC_ClockDiv1 = 0, + kQDC_ClockDiv2 = 1, + kQDC_ClockDiv4 = 2, + kQDC_ClockDiv8 = 3, + kQDC_ClockDiv16 = 4, + kQDC_ClockDiv32 = 5, + kQDC_ClockDiv64 = 6, + kQDC_ClockDiv128 = 7, + kQDC_ClockDiv256 = 8, + kQDC_ClockDiv512 = 9, + kQDC_ClockDiv1024 = 10, + kQDC_ClockDiv2048 = 11, + kQDC_ClockDiv4096 = 12, + kQDC_ClockDiv8192 = 13, + kQDC_ClockDiv16384 = 14, + kQDC_ClockDiv32768 = 15, +} qdc_prescaler_t; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) +/*! + * @brief Define input filter prescaler value. + * + * The input filter prescaler value is to prescale the IPBus clock. + * (Frequency of FILT clock) = (Frequency of IPBus clock) / 2^FILT_PRSC. + */ +typedef enum _qdc_filter_prescaler +{ + kQDC_FilterPrescalerDiv1 = 0U, /*!< Input filter prescaler is 1. */ + kQDC_FilterPrescalerDiv2 = 1U, /*!< Input filter prescaler is 2. */ + kQDC_FilterPrescalerDiv4 = 2U, /*!< Input filter prescaler is 4. */ + kQDC_FilterPrescalerDiv8 = 3U, /*!< Input filter prescaler is 8. */ + kQDC_FilterPrescalerDiv16 = 4U, /*!< Input filter prescaler is 16. */ + kQDC_FilterPrescalerDiv32 = 5U, /*!< Input filter prescaler is 32. */ + kQDC_FilterPrescalerDiv64 = 6U, /*!< Input filter prescaler is 64. */ + kQDC_FilterPrescalerDiv128 = 7U, /*!< Input filter prescaler is 128. */ +} qdc_filter_prescaler_t; +#endif + +/*! + * @brief Define user configuration structure for QDC module. + */ +typedef struct _qdc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + qdc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + + /* Signal detection. */ + qdc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + qdc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ + bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. + */ + + /* Watchdog. */ + bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ + uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature + decoder module watchdog timer. This field is only available when + "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + qdc_filter_prescaler_t filterPrescaler; /*!< Input filter prescaler. */ +#endif + + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ + uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of + noisy samples causing an incorrect transition to be recognized. The value represent the + number of consecutive samples that must agree prior to the input filter accepting an + input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 + samples. The Available range is 0 - 7.*/ + uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period + is larger than the period of the expected noise. This value represents the + sampling period (in IPBus clock cycles) of the decoder input signals. + The available range is 0 - 255. */ + + /* Position compare. */ + qdc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ + + /* Modulus counting. */ + qdc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + bool enableModuloCountMode; /*!< Enable Modulo Counting. */ + uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when + "enableModuloCountMode" = true. The available value is a 32-bit number. */ + uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + /* Prescaler. */ + bool enablePeriodMeasurementFunction; /*!< Enable period measurement function. */ + qdc_prescaler_t prescalerValue; /*!< The value of prescaler. */ +#endif +} qdc_config_t; + +/*! + * @brief Define configuration structure for self test module. + * + * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. + * This is a factory test feature. It is also useful to customers' software development and testing. + */ +typedef struct _qdc_self_test_config +{ + qdc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ + uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. + The available range is 0 - 31. */ +} qdc_self_test_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initialization for the QDC module. + * + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. + * + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_config_t". + */ +void QDC_Init(QDC_Type *base, const qdc_config_t *config); + +/*! + * @brief De-initialization for the QDC module. + * + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with + * the operations like: + * - Disable the clock for QDC module. + * + * @param base QDC peripheral base address. + */ +void QDC_Deinit(QDC_Type *base); + +/*! + * @brief Get an available pre-defined settings for QDC's configuration. + * + * This function initializes the QDC configuration structure with an available settings, the default value are: + * @code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * config->prescalerValue = kQDC_ClockDiv1; + * config->enablePeriodMeasurementFunction = true; + * @endcode + * @param config Pointer to a variable of configuration structure. See to "qdc_config_t". + */ +void QDC_GetDefaultConfig(qdc_config_t *config); + +/*! + * @brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * @param base QDC peripheral base address. + */ +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base); + +/*! + * @brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. + */ +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config); + +/*! + * @brief Enable watchdog for QDC module. + * + * @param base QDC peripheral base address + * @param enable Enables or disables the watchdog + */ +void QDC_EnableWatchdog(QDC_Type *base, bool enable); + +/*! + * @brief Set initial position value for QDC module. + * + * @param base QDC peripheral base address + * @param value Positive initial value + */ +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value); + +/*! @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base QDC peripheral base address. + * + * @return Mask value of status flags. For available mask, see to "_qdc_status_flags". + */ +uint32_t QDC_GetStatusFlags(QDC_Type *base); + +/*! + * @brief Clear the status flags. + * + * @param base QDC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". + */ +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask); + +/*! + * @brief Get the signals' real-time status. + * + * @param base QDC peripheral base address. + * + * @return Mask value of signals' real-time status. For available mask, see to "_qdc_signal_status_flags" + */ +static inline uint16_t QDC_GetSignalStatusFlags(QDC_Type *base) +{ + return base->IMR; +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask); + +/*! + * @brief Disable the interrupts. + * + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask); + +/*! + * @brief Get the enabled interrupts' flags. + * + * @param base QDC peripheral base address. + * + * @return Mask value of enabled interrupts. + */ +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base); + +/*! @} */ + +/*! + * @name Value Operation + * @{ + */ + +/*! + * @brief Get the current position counter's value. + * + * @param base QDC peripheral base address. + * + * @return Current position counter's value. + */ +uint32_t QDC_GetPositionValue(QDC_Type *base); + +/*! + * @brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position counter's value. + */ +uint32_t QDC_GetHoldPositionValue(QDC_Type *base); + +/*! + * @brief Get the position difference counter's value. + * + * @param base QDC peripheral base address. + * + * @return The position difference counter's value. + */ +static inline uint16_t QDC_GetPositionDifferenceValue(QDC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position difference counter's value. + */ +static inline uint16_t QDC_GetHoldPositionDifferenceValue(QDC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the position revolution counter's value. + * + * @param base QDC peripheral base address. + * + * @return The position revolution counter's value. + */ +static inline uint16_t QDC_GetRevolutionValue(QDC_Type *base) +{ + return base->REV; +} + +/*! + * @brief Get the hold position revolution counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position revolution counter's value. + */ +static inline uint16_t QDC_GetHoldRevolutionValue(QDC_Type *base) +{ + return base->REVH; +} + +#if (defined(FSL_FEATURE_QDC_HAS_LASTEDGE) && FSL_FEATURE_QDC_HAS_LASTEDGE) +/*! + * @brief Get the last edge time value. + * + * @param base QDC peripheral base address. + * + * @return The last edge time hold value. + */ +static inline uint16_t QDC_GetLastEdgeTimeValue(QDC_Type *base) +{ + return base->LASTEDGE; +} + +/*! + * @brief Get the last edge time hold value. + * + * @param base QDC peripheral base address. + * + * @return The last edge time hold value. + */ +static inline uint16_t QDC_GetHoldLastEdgeTimeValue(QDC_Type *base) +{ + return base->LASTEDGEH; +} +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_POSDPER) && FSL_FEATURE_QDC_HAS_POSDPER) +/*! + * @brief Get the position difference period value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetPositionDifferencePeriodValue(QDC_Type *base) +{ + return base->POSDPER; +} + +/*! + * @brief Get the position difference period buffer value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetPositionDifferencePeriodBufferValue(QDC_Type *base) +{ + return base->POSDPERBFR; +} + +/*! + * @brief Get the position difference period hold value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetHoldPositionDifferencePeriodValue(QDC_Type *base) +{ + return base->POSDPERH; +} +#endif +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_QDC_H_ */ diff --git a/drivers/sai/fsl_sai.c b/drivers/sai/fsl_sai.c index 32d36a047..6d69f5efb 100644 --- a/drivers/sai/fsl_sai.c +++ b/drivers/sai/fsl_sai.c @@ -32,6 +32,10 @@ typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); /*! @brief check flag avalibility */ #define IS_SAI_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) + +#if defined(SAI_RSTS) +#define SAI_RESETS_ARRAY SAI_RSTS +#endif /******************************************************************************* * Prototypes ******************************************************************************/ @@ -145,6 +149,10 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config, ******************************************************************************/ /* Base pointer array */ static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +#if defined(SAI_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_saiReset[] = SAI_RESETS_ARRAY; +#endif /*!@brief SAI handle pointer */ static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; /* IRQ number array */ @@ -385,254 +393,6 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config, #endif } -/*! - * brief Initializes the SAI Tx peripheral. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * param base SAI base pointer - * param config SAI configuration structure. - */ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); -#endif - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_TxReset(base); - - /* Configure audio protocol */ - if (config->protocol == kSAI_BusLeftJustified) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusRightJustified) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusI2S) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusPCMA) - { - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->TCR2 |= I2S_TCR2_BCD_MASK; - base->TCR4 |= I2S_TCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); - base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCD_MASK; - base->TCR4 &= ~I2S_TCR4_FSD_MASK; - } - - /* Set Sync mode */ - if (config->syncMode == kSAI_ModeAsync) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - } - if (config->syncMode == kSAI_ModeSync) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(1U)); - /* If sync with Rx, should set Rx to async mode */ - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - } -#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) - if (config->syncMode == kSAI_ModeSyncWithOtherTx) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(2U)); - } - if (config->syncMode == kSAI_ModeSyncWithOtherRx) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(3U)); - } -#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_TxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - -/*! - * brief Initializes the SAI Rx peripheral. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * param base SAI base pointer - * param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SAI clock first. */ - (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); -#endif - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_RxReset(base); - - /* Configure audio protocol */ - if (config->protocol == kSAI_BusLeftJustified) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusRightJustified) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusI2S) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusPCMA) - { - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->RCR2 |= I2S_RCR2_BCD_MASK; - base->RCR4 |= I2S_RCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); - base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCD_MASK; - base->RCR4 &= ~I2S_RCR4_FSD_MASK; - } - - /* Set Sync mode */ - if (config->syncMode == kSAI_ModeAsync) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - } - if (config->syncMode == kSAI_ModeSync) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(1U)); - /* If sync with Tx, should set Tx to async mode */ - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - } -#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) - if (config->syncMode == kSAI_ModeSyncWithOtherTx) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(2U)); - } - if (config->syncMode == kSAI_ModeSyncWithOtherRx) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(3U)); - } -#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_RxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - /*! * brief Initializes the SAI peripheral. * @@ -647,6 +407,10 @@ void SAI_Init(I2S_Type *base) (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(SAI_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_saiReset[SAI_GetInstance(base)]); +#endif + #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) /* disable interrupt and DMA request*/ base->TCSR &= @@ -677,74 +441,6 @@ void SAI_Deinit(I2S_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } -/*! - * brief Sets the SAI Tx configuration structure to default values. - * - * deprecated Do not use this function. It has been superceded by @ref - * SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig, SAI_GetDSPConfig,SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * This is an example. - code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - endcode - * - * param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - config->mclkSource = kSAI_MclkSourceSysclk; -#endif -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeAsync; -} - -/*! - * brief Sets the SAI Rx configuration structure to default values. - * - * deprecated Do not use this function. It has been superceded by @ref - * SAI_GetClassicI2SConfig,SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig,SAI_GetDSPConfig,SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * This is an example. - code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - endcode - * - * param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - config->mclkSource = kSAI_MclkSourceSysclk; -#endif -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeSync; -} - /*! * brief Resets the SAI Tx. * @@ -1533,7 +1229,7 @@ void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv assert(config != NULL); assert(config->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); - handle->bitWidth = config->frameSync.frameSyncWidth; + handle->bitWidth = config->serialData.dataWordNLength; #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) if ((config->fifo.fifoWatermark == 0U) || (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) @@ -1667,7 +1363,7 @@ void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv assert(handle != NULL); assert(config != NULL); - handle->bitWidth = config->frameSync.frameSyncWidth; + handle->bitWidth = config->serialData.dataWordNLength; #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) if ((config->fifo.fifoWatermark == 0U) || (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) @@ -1832,293 +1528,6 @@ void SAI_GetTDMConfig(sai_transceiver_t *config, config->serialData.dataWordNum = (uint8_t)dataWordNum; } -/*! - * brief Configures the SAI Tx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); - - uint32_t bclk = 0; - uint32_t val = 0; - uint8_t i = 0U, channelNums = 0U; - uint32_t divider = 0U; - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); - val |= I2S_TCR4_SYWD(format->bitWidth - 1U); - base->TCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled, then set master clock divider */ - if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (IS_SAI_FLAG_SET(base->TCR2, I2S_TCR2_BCD_MASK)) - { - base->TCR2 &= ~I2S_TCR2_DIV_MASK; - /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ - divider = bclkSourceClockHz / bclk; - /* for the condition where the source clock is smaller than target bclk */ - if (divider == 0U) - { - divider++; - } - /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ - if ((bclkSourceClockHz / divider) > bclk) - { - divider++; - } - -#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) - /* if bclk same with MCLK, bypass the divider */ - if (divider == 1U) - { - base->TCR2 |= I2S_TCR2_BYP_MASK; - } - else -#endif - { - base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); - } - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); - } - else - { - if (IS_SAI_FLAG_SET(base->TCR4, I2S_TCR4_MF_MASK)) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1UL); - } - else - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); - } - } - - /* Set mono or stereo */ - base->TMR = (uint32_t)format->stereo; - - /* if channel mask is not set, then format->channel must be set, - use it to get channel mask value */ - if (format->channelMask == 0U) - { - format->channelMask = 1U << format->channel; - } - - /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - channelNums++; - format->endChannel = i; - } - } - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - format->channel = i; - break; - } - } - - format->channelNums = channelNums; -#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) - /* make sure combine mode disabled while multipe channel is used */ - if (format->channelNums > 1U) - { - base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; - } -#endif - - /* Set data channel */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(format->channelMask); - -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - /* Set watermark */ - base->TCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); - - uint32_t bclk = 0; - uint32_t val = 0; - uint8_t i = 0U, channelNums = 0U; - uint32_t divider = 0U; - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); - val |= I2S_RCR4_SYWD(format->bitWidth - 1U); - base->RCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled */ - if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (IS_SAI_FLAG_SET(base->RCR2, I2S_RCR2_BCD_MASK)) - { - base->RCR2 &= ~I2S_RCR2_DIV_MASK; - /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ - divider = bclkSourceClockHz / bclk; - /* for the condition where the source clock is smaller than target bclk */ - if (divider == 0U) - { - divider++; - } - /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ - if ((bclkSourceClockHz / divider) > bclk) - { - divider++; - } -#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) - /* if bclk same with MCLK, bypass the divider */ - if (divider == 1U) - { - base->RCR2 |= I2S_RCR2_BYP_MASK; - } - else -#endif - { - base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); - } - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); - } - else - { - if (IS_SAI_FLAG_SET(base->RCR4, I2S_RCR4_MF_MASK)) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1UL); - } - else - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0UL); - } - } - - /* Set mono or stereo */ - base->RMR = (uint32_t)format->stereo; - - /* if channel mask is not set, then format->channel must be set, - use it to get channel mask value */ - if (format->channelMask == 0U) - { - format->channelMask = 1U << format->channel; - } - - /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - channelNums++; - format->endChannel = i; - } - } - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - format->channel = i; - break; - } - } - - format->channelNums = channelNums; - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) - /* make sure combine mode disabled while multipe channel is used */ - if (format->channelNums > 1U) - { - base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; - } -#endif - - /* Set data channel */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - /* enable all the channel */ - base->RCR3 |= I2S_RCR3_RCE(format->channelMask); - -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - /* Set watermark */ - base->RCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - /*! * brief Sends data using a blocking method. * @@ -2353,106 +1762,6 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf (void)EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } -/*! - * brief Configures the SAI Tx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param handle SAI handle pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * return Status of this function. Return value is the status_t. - */ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle != NULL); - - if ((bclkSourceClockHz < format->sampleRate_Hz) -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - || (mclkSourceClockHz < format->sampleRate_Hz) -#endif - ) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = (uint8_t)format->bitWidth; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->watermark = format->watermark; -#endif - - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - handle->channel = format->channel; - /* used for multi channel */ - handle->channelMask = format->channelMask; - handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; - - return kStatus_Success; -} - -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param handle SAI handle pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * return Status of this function. Return value is one of status_t. - */ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle != NULL); - - if ((bclkSourceClockHz < format->sampleRate_Hz) -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - || (mclkSourceClockHz < format->sampleRate_Hz) -#endif - ) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = (uint8_t)format->bitWidth; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->watermark = format->watermark; -#endif - - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - handle->channel = format->channel; - /* used for multi channel */ - handle->channelMask = format->channelMask; - handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; - - return kStatus_Success; -} - /*! * brief Performs an interrupt non-blocking send transfer on SAI. * diff --git a/drivers/sai/fsl_sai.h b/drivers/sai/fsl_sai.h index a303edf29..d00f81e98 100644 --- a/drivers/sai/fsl_sai.h +++ b/drivers/sai/fsl_sai.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SAI_H_ -#define _FSL_SAI_H_ +#ifndef FSL_SAI_H_ +#define FSL_SAI_H_ #include "fsl_common.h" @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 8)) /*!< Version 2.3.8 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2 */ /*@}*/ /*! @brief _sai_status_t, SAI return status.*/ @@ -466,78 +466,6 @@ extern "C" { * @{ */ -/*! - * @brief Initializes the SAI Tx peripheral. - * @deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Initializes the SAI Rx peripheral. - * @deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Sets the SAI Tx configuration structure to default values. - * @deprecated Do not use this function. It has been superceded by - * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref - SAI_GetDSPConfig, @ref SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief Sets the SAI Rx configuration structure to default values. - * @deprecated Do not use this function. It has been superceded by - * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref - SAI_GetDSPConfig, @ref SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config); - /*! * @brief Initializes the SAI peripheral. * @@ -1244,42 +1172,6 @@ static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t ch * @{ */ -/*! - * @brief Configures the SAI Tx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - /*! * @brief Sends data using a blocking method. * @@ -1417,47 +1309,6 @@ void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv */ void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); -/*! - * @brief Configures the SAI Tx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is the status_t. - */ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is one of status_t. - */ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); /*! * @brief Performs an interrupt non-blocking send transfer on SAI. @@ -1583,4 +1434,4 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); /*! @} */ -#endif /* _FSL_SAI_H_ */ +#endif /* FSL_SAI_H_ */ diff --git a/drivers/sai/fsl_sai_edma.c b/drivers/sai/fsl_sai_edma.c index d32503e24..64ea0711a 100644 --- a/drivers/sai/fsl_sai_edma.c +++ b/drivers/sai/fsl_sai_edma.c @@ -192,9 +192,10 @@ void SAI_TransferTxCreateHandleEDMA( (void)memset(handle, 0, sizeof(*handle)); /* Set sai base to handle */ - handle->dmaHandle = txDmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->dmaHandle = txDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; /* Set SAI state to idle */ handle->state = (uint32_t)kSAI_Idle; @@ -233,9 +234,10 @@ void SAI_TransferRxCreateHandleEDMA( (void)memset(handle, 0, sizeof(*handle)); /* Set sai base to handle */ - handle->dmaHandle = rxDmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->dmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; /* Set SAI state to idle */ handle->state = (uint32_t)kSAI_Idle; @@ -251,53 +253,18 @@ void SAI_TransferRxCreateHandleEDMA( } /*! - * brief Configures the SAI Tx audio format. + * brief Initializes the SAI interleave type. * - * deprecated Do not use this function. It has been superceded by ref SAI_TransferTxSetConfigEDMA + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. + * param interleaveType SAI interleave type. */ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType) { - assert((handle != NULL) && (format != NULL)); - - /* Configure the audio format to SAI registers */ - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the transfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = (uint8_t)(format->bitWidth / 8U); - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits until do a send/receive */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->count = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - format->watermark); -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + handle->interleaveType = interleaveType; } /*! @@ -357,56 +324,6 @@ void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ #endif /* FSL_FEATURE_SAI_HAS_FIFO */ } -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by ref SAI_TransferRxSetConfigEDMA - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. - */ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert((handle != NULL) && (format != NULL)); - - /* Configure the audio format to SAI registers */ - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the transfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = (uint8_t)(format->bitWidth / 8U); - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits until do a send/receive */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->count = format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - /*! * brief Configures the SAI Rx. * @@ -470,6 +387,18 @@ void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ * note This interface returns immediately after the transfer initiates. Call * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. * + * In classic I2S mode configuration. + * 1. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * * This function support multi channel transfer, * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation * on channel numbers @@ -487,9 +416,14 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra { assert((handle != NULL) && (xfer != NULL)); - edma_transfer_config_t config = {0}; - uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); - uint32_t destOffset = 0U; + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + uint32_t destOffset = 0U; + uint32_t srcOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = {.enableSrcMinorOffset = true, + .enableDestMinorOffset = false, + .minorOffset = 0xFFFFFU - 2U * srcOffset + 1U + handle->bytesPerFrame}; /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -518,11 +452,24 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra } #endif - /* Prepare edma configure */ - EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, - (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, - (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); - + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ handle->nbytes = handle->count * handle->bytesPerFrame; @@ -564,6 +511,18 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra * note This interface returns immediately after the transfer initiates. Call * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. * + * In classic I2S mode configuration. + * 1. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * * This function support multi channel transfer, * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation * on channel numbers @@ -581,9 +540,15 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ { assert((handle != NULL) && (xfer != NULL)); - edma_transfer_config_t config = {0}; - uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); - uint32_t srcOffset = 0U; + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + uint32_t srcOffset = 0U; + uint32_t destOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = { + .enableSrcMinorOffset = false, + .enableDestMinorOffset = true, + .minorOffset = 0xFFFFFU - 2U * destOffset + 1U + (uint32_t)handle->bytesPerFrame}; /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -612,10 +577,25 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ } #endif - /* Prepare edma configure */ - EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, - xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, - (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ handle->nbytes = handle->count * handle->bytesPerFrame; diff --git a/drivers/sai/fsl_sai_edma.h b/drivers/sai/fsl_sai_edma.h index 5cae5d83a..82d7fb0f2 100644 --- a/drivers/sai/fsl_sai_edma.h +++ b/drivers/sai/fsl_sai_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SAI_EDMA_H_ -#define _FSL_SAI_EDMA_H_ +#ifndef FSL_SAI_EDMA_H_ +#define FSL_SAI_EDMA_H_ #include "fsl_edma.h" #include "fsl_sai.h" @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*!< Version 2.5.1 */ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) /*!< Version 2.7.0 */ /*@}*/ typedef struct sai_edma_handle sai_edma_handle_t; @@ -31,6 +31,23 @@ typedef struct sai_edma_handle sai_edma_handle_t; /*! @brief SAI eDMA transfer callback function for finish and error */ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); +/*!@brief sai interleave type */ +typedef enum _sai_edma_interleave +{ + kSAI_EDMAInterleavePerChannelSample = + 0U, /*!< SAI data interleave per channel sample + * --------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ....| + * --------------------------------------------------------------------------------------------------- + */ + kSAI_EDMAInterleavePerChannelBlock = + 1U, /*!< SAI data interleave per channel block + * -------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ... | RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------------- + */ +} sai_edma_interleave_t; + /*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ struct sai_edma_handle { @@ -47,6 +64,7 @@ struct sai_edma_handle uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + sai_edma_interleave_t interleaveType; /*!< Transfer interleave type */ volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ }; @@ -102,50 +120,16 @@ void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, edma_handle_t *rxDmaHandle); /*! - * @brief Configures the SAI Tx audio format. - * - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfigEDMA - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - */ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. + * @brief Initializes the SAI interleave type. * - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfigEDMA + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. + * @param interleaveType Multi channel interleave type. */ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType); /*! * @brief Configures the SAI Tx. diff --git a/drivers/smartdma/fsl_smartdma.c b/drivers/smartdma/fsl_smartdma.c index 79b7c8a93..d1560d46b 100644 --- a/drivers/smartdma/fsl_smartdma.c +++ b/drivers/smartdma/fsl_smartdma.c @@ -5,7 +5,7 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_smartdma_prv.h" + #include "fsl_smartdma.h" /* Component ID definition, used by tools. */ @@ -19,23 +19,15 @@ typedef void (*smartdma_func_t)(void); -typedef struct -{ - __IO uint32_t SMARTDMA_BOOT; /* 0x20 */ - __IO uint32_t SMARTDMA_CTRL; /* 0x24 */ - __I uint32_t SMARTDMA_PC; /* 0x28 */ - __I uint32_t SMARTDMA_SP; /* 0x2C */ - __IO uint32_t SMARTDMA_BREAK_ADDR; /* 0x30 */ - __IO uint32_t SMARTDMA_BREAK_VECT; /* 0x34 */ - __IO uint32_t SMARTDMA_EMER_VECT; /* 0x38 */ - __IO uint32_t SMARTDMA_EMER_SEL; /* 0x3C */ - __IO uint32_t SMARTDMA_ARM2SMARTDMA; /* 0x40 */ - __IO uint32_t SMARTDMA_SMARTDMA2ARM; /* 0x44 */ - __IO uint32_t SMARTDMA_PENDTRAP; /* 0x48 */ -} SMARTDMA_Type; +#define SMARTDMA_HANDSHAKE_EVENT 0U +#define SMARTDMA_HANDSHAKE_ENABLE 1U +#define SMARTDMA_MASK_RESP 2U +#define SMARTDMA_ENABLE_AHBBUF 3U +#define SMARTDMA_ENABLE_GPISYNCH 4U -#define SMARTDMA_BASE 0x40027020 -#define SMARTDMA ((volatile SMARTDMA_Type *)SMARTDMA_BASE) +#if defined(SMARTDMA0) && !(defined(SMARTDMA)) +#define SMARTDMA SMARTDMA0 +#endif /******************************************************************************* * Variables @@ -43,771 +35,7 @@ typedef struct static smartdma_func_t *s_smartdmaApiTable; static smartdma_callback_t s_smartdmaCallback; static void *s_smartdmaCallbackParam; - -const uint8_t s_smartdmaDisplayFirmware[] = { - 0x54U, 0x00U, 0x10U, 0x24U, 0x34U, 0x01U, 0x10U, 0x24U, 0xBCU, 0x02U, 0x10U, 0x24U, 0xF8U, 0x01U, 0x10U, 0x24U, 0x5CU, 0x03U, 0x10U, - 0x24U, 0x8CU, 0x08U, 0x10U, 0x24U, 0xDCU, 0x0DU, 0x10U, 0x24U, 0xF0U, 0x0FU, 0x10U, 0x24U, 0x64U, 0x12U, 0x10U, 0x24U, 0xDCU, 0x14U, - 0x10U, 0x24U, 0xA0U, 0x25U, 0x10U, 0x24U, 0x48U, 0x16U, 0x10U, 0x24U, 0xC0U, 0x27U, 0x10U, 0x24U, 0x0CU, 0x19U, 0x10U, 0x24U, 0x70U, - 0x2BU, 0x10U, 0x24U, 0xD8U, 0x1BU, 0x10U, 0x24U, 0x48U, 0x1DU, 0x10U, 0x24U, 0x18U, 0x20U, 0x10U, 0x24U, 0xD0U, 0x2EU, 0x10U, 0x24U, - 0x5CU, 0x33U, 0x10U, 0x24U, 0xECU, 0x22U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, - 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, - 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, - 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, - 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x04U, 0x22U, - 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, 0x11U, 0x08U, - 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, - 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, - 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x14U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, - 0x10U, 0x05U, 0x18U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x1CU, - 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, - 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x15U, 0x2AU, 0x02U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, - 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, - 0x14U, 0x00U, 0x06U, 0x48U, 0x07U, 0x07U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, - 0xECU, 0x02U, 0x20U, 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, - 0x01U, 0x14U, 0x1CU, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x04U, 0x32U, - 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, - 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0x08U, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, - 0x10U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, - 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, - 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, - 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xB2U, 0x03U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, - 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, - 0x06U, 0x18U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, 0x1AU, 0x80U, 0x10U, - 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, - 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, - 0x0CU, 0x30U, 0x00U, 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, - 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, - 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, - 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, - 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x3AU, 0x05U, 0x20U, 0x12U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, - 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, - 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, - 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, - 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, 0x05U, - 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, - 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x15U, 0x7AU, 0x06U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x04U, 0x18U, 0x04U, 0x27U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, - 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0xA4U, 0x05U, 0x01U, 0x01U, 0x84U, 0x05U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x03U, 0x10U, - 0x04U, 0x14U, 0x06U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, - 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, - 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, - 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, - 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, - 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, - 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, - 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, - 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, - 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, - 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, - 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, - 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, - 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, - 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, - 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, - 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, - 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, - 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, - 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, - 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, - 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, - 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, - 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, - 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, - 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, - 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, - 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, - 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, - 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, - 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, - 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, - 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, - 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, - 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, - 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, - 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, - 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, - 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, - 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, - 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, - 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, - 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, - 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, - 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, - 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, - 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, - 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, - 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, - 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, - 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, - 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, - 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, - 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, - 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, - 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, - 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, - 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, - 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, - 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, - 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, - 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x08U, 0x46U, 0x14U, - 0x00U, 0x55U, 0x02U, 0x07U, 0x20U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, - 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, - 0xDAU, 0x10U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, - 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, - 0x02U, 0x10U, 0x04U, 0x14U, 0x06U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, - 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, - 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, - 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, - 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, - 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, - 0xCCU, 0x70U, 0x55U, 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, - 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, - 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x08U, 0x32U, 0x32U, 0x01U, 0x08U, - 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, - 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, - 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, - 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, - 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, - 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, - 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, - 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x14U, - 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, - 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, - 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, - 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, - 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, - 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, - 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, - 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x00U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, - 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, - 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, - 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, - 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, - 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, - 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, - 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, - 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x01U, - 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, - 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, - 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, - 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, - 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, - 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, - 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, - 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, - 0x18U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, - 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, - 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, - 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, - 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, - 0x55U, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, - 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, - 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x04U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, - 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, - 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, - 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, - 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, - 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, - 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x10U, 0x32U, 0x32U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, - 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, - 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, - 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, - 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, - 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, - 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, - 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, - 0x05U, 0x1CU, 0x32U, 0x32U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x11U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, - 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x1BU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, - 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, - 0x1BU, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, - 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, - 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, - 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, - 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, - 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, - 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, - 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, - 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, - 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, - 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, - 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, - 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, - 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, - 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, - 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, - 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, - 0x04U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, - 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, - 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, - 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, - 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, - 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, - 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x1FU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, - 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, - 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, - 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, - 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, - 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, - 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, - 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, - 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, - 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, - 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, - 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, - 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, - 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, - 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, - 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, - 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, - 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, - 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, - 0x18U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, - 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, - 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, - 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, 0x04U, 0x42U, 0x32U, 0x01U, - 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, - 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, - 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, - 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, - 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, - 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, - 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, - 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x24U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, - 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x06U, 0x00U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x07U, 0x08U, 0x44U, - 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, - 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, - 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, - 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, - 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, - 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, - 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, - 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, - 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, - 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, - 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, 0x05U, 0x1CU, 0x32U, - 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, - 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, - 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, - 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, - 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, - 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, - 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, - 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, - 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, - 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, - 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, - 0x05U, 0x04U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, - 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, - 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, - 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, - 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, - 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, - 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, - 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, - 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x29U, - 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, - 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, - 0xDEU, 0x01U, 0x00U, 0x35U, 0x1AU, 0x2AU, 0x20U, 0x15U, 0x42U, 0x2BU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, - 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, - 0x04U, 0x35U, 0x42U, 0x2AU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x10U, 0x4CU, 0x10U, 0x10U, 0xDCU, - 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0x42U, 0x2AU, 0x20U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x9AU, 0x2AU, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, - 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, - 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, - 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x1AU, 0x2AU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, - 0x00U, 0x00U, 0x00U, 0x15U, 0x52U, 0x2CU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, - 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x6AU, 0x2BU, - 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, - 0x15U, 0x00U, 0x55U, 0x6AU, 0x2BU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xB2U, 0x2BU, 0x20U, 0x0DU, - 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, - 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, - 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x42U, - 0x2BU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, - 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x15U, 0x52U, 0x2CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, - 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, - 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xF2U, 0x2CU, 0x20U, 0x15U, 0xAAU, 0x2FU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, - 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x12U, 0x2EU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, - 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x1AU, 0x2DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, - 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, - 0xF5U, 0x0FU, 0x10U, 0x0CU, 0x31U, 0x48U, 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, - 0x14U, 0x50U, 0x00U, 0x10U, 0x14U, 0x50U, 0x10U, 0x11U, 0x1CU, 0x60U, 0x00U, 0x10U, 0x1CU, 0x70U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xF6U, 0x0FU, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x1AU, 0x2DU, - 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xEAU, 0x2DU, 0x20U, 0x05U, 0x80U, - 0x32U, 0x31U, 0x15U, 0x2AU, 0x2FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x12U, 0x2EU, 0x20U, 0x01U, - 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x2AU, 0x2FU, 0x20U, 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, - 0x0FU, 0x10U, 0x0CU, 0x31U, 0x48U, 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, - 0x34U, 0x00U, 0x35U, 0x2AU, 0x2FU, 0x20U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x14U, 0x50U, 0x10U, 0x11U, 0x1CU, 0x60U, 0x00U, 0x10U, - 0x1CU, 0x70U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x2AU, 0x2FU, 0x20U, - 0x00U, 0x0CU, 0xF6U, 0x0FU, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x12U, 0x2EU, 0x20U, 0x04U, 0x1CU, 0x29U, - 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x2FU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, - 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, - 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, - 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xF2U, 0x2CU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xDAU, 0x31U, - 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x8AU, 0x30U, 0x20U, 0x00U, 0x24U, - 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xD2U, 0x2FU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, - 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x18U, - 0x10U, 0x1CU, 0x51U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x14U, 0x58U, 0x18U, 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x10U, 0x0CU, 0x68U, 0x18U, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xD2U, 0x2FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, - 0x05U, 0x04U, 0x35U, 0x5AU, 0x30U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x62U, 0x31U, 0x20U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x8AU, 0x30U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, - 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x62U, 0x31U, - 0x20U, 0x10U, 0x10U, 0x48U, 0x18U, 0x10U, 0x1CU, 0x51U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x62U, - 0x31U, 0x20U, 0x10U, 0x14U, 0x58U, 0x18U, 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, - 0x62U, 0x31U, 0x20U, 0x10U, 0x0CU, 0x68U, 0x18U, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x8AU, 0x30U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, - 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x42U, 0x31U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, - 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, - 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, - 0x46U, 0x00U, 0x00U, 0xB5U, 0xAAU, 0x2FU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, - 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, - 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xDAU, 0x31U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, - 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, - 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0x24U, 0xF4U, 0x0FU, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x82U, 0x32U, 0x20U, - 0x15U, 0x02U, 0x35U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x82U, 0x33U, - 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xAAU, 0x32U, 0x20U, 0x01U, 0x10U, - 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, - 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0xAAU, 0x32U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, - 0x05U, 0x04U, 0x35U, 0x52U, 0x33U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x7AU, 0x34U, 0x20U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x82U, 0x33U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, - 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, - 0x00U, 0x35U, 0x7AU, 0x34U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, - 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x7AU, 0x34U, 0x20U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, - 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x7AU, 0x34U, 0x20U, - 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0x82U, 0x33U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, - 0x04U, 0x35U, 0x5AU, 0x34U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, - 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, - 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, - 0x00U, 0x0CU, 0xC4U, 0x03U, 0xB5U, 0x82U, 0x32U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x72U, 0x37U, - 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xFAU, 0x35U, 0x20U, 0x00U, 0x20U, - 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x2AU, 0x35U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, - 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x1CU, 0x01U, - 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, - 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x22U, - 0x16U, 0x00U, 0x55U, 0x2AU, 0x35U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xCAU, 0x35U, 0x20U, 0x08U, - 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xEAU, 0x36U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, - 0x75U, 0xFAU, 0x35U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, - 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xEAU, 0x36U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x14U, - 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, - 0xEAU, 0x36U, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, - 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xEAU, 0x36U, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0xFAU, 0x35U, - 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xCAU, 0x36U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, - 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, - 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, - 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x02U, 0x35U, - 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, - 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, - 0x72U, 0x37U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, - 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, - 0x02U, 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x1AU, 0x38U, 0x20U, 0x15U, 0x3AU, 0x39U, 0x20U, 0x08U, 0x4AU, - 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x42U, 0x38U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x10U, 0x48U, 0x00U, - 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0x42U, 0x38U, - 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x92U, 0x38U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, - 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, - 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, - 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x1AU, 0x38U, 0x20U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x52U, 0x3AU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, - 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, - 0x62U, 0x39U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x10U, 0x4CU, 0x10U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, - 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0x62U, 0x39U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, - 0x04U, 0x35U, 0xB2U, 0x39U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, - 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, - 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, - 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x3AU, 0x39U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, - 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, - 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x52U, 0x3AU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, - 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, - 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xFAU, 0x3AU, - 0x20U, 0x15U, 0x62U, 0x3DU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xF2U, - 0x3BU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x22U, 0x3BU, 0x20U, 0x01U, - 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x00U, 0x10U, 0xDCU, 0x70U, 0x48U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x58U, 0x00U, 0x10U, 0x1CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x8CU, - 0xF5U, 0x0FU, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x22U, 0x3BU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, - 0xDEU, 0x05U, 0x04U, 0x35U, 0xCAU, 0x3BU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xE2U, 0x3CU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, - 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x12U, 0x2EU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, - 0xFFU, 0x11U, 0x1CU, 0x40U, 0x00U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xE2U, - 0x3CU, 0x20U, 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x58U, 0x00U, 0x10U, 0x1CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, - 0x46U, 0x34U, 0x00U, 0x35U, 0xE2U, 0x3CU, 0x20U, 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, 0x10U, 0x5CU, 0x71U, 0x48U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xE2U, 0x3CU, 0x20U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x08U, 0x46U, 0x34U, - 0x00U, 0xB5U, 0xF2U, 0x3BU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xC2U, 0x3CU, 0x20U, 0x05U, 0x80U, - 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, - 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, - 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xFAU, 0x3AU, 0x20U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xF2U, 0x3FU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, - 0x00U, 0x00U, 0x95U, 0x72U, 0x3EU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, - 0x8AU, 0x3DU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0x1CU, 0x48U, 0x08U, - 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x10U, 0x1CU, 0x68U, 0x18U, 0x10U, 0x1CU, 0x70U, - 0x18U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x14U, 0x50U, 0x10U, 0x10U, 0x1CU, - 0x60U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, 0x0DU, 0xCCU, 0xF4U, 0x0FU, 0x08U, - 0x66U, 0x16U, 0x00U, 0x55U, 0x8AU, 0x3DU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x5AU, 0x30U, 0x20U, - 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x7AU, 0x3FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, - 0x03U, 0x75U, 0x72U, 0x3EU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0x1CU, - 0x48U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x7AU, 0x3FU, 0x20U, 0x0DU, - 0x10U, 0xF5U, 0x0FU, 0x10U, 0x1CU, 0x68U, 0x18U, 0x10U, 0x1CU, 0x70U, 0x18U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x10U, 0xDCU, 0x41U, 0x50U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x7AU, 0x3FU, 0x20U, 0x10U, 0x14U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x60U, - 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x7AU, 0x3FU, 0x20U, 0x10U, 0x0CU, - 0x68U, 0x10U, 0x0DU, 0xCCU, 0xF4U, 0x0FU, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x72U, 0x3EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, - 0xDEU, 0x05U, 0x04U, 0x35U, 0x5AU, 0x3FU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, - 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, - 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, - 0x00U, 0x00U, 0xB5U, 0x62U, 0x3DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, - 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, - 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xF2U, 0x3FU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, - 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, - 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0x24U, 0xF4U, 0x0FU, 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, - 0xA2U, 0x40U, 0x20U, 0x15U, 0x2AU, 0x43U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, - 0x95U, 0xA2U, 0x41U, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xCAU, 0x40U, - 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, - 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, - 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0xCAU, 0x40U, 0x20U, 0x04U, 0x1CU, 0x29U, - 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x72U, 0x41U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x9AU, - 0x42U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xA2U, 0x41U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, - 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, - 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x9AU, 0x42U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, - 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x9AU, 0x42U, 0x20U, 0x11U, 0x18U, - 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, - 0x9AU, 0x42U, 0x20U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0xA2U, 0x41U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, - 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x7AU, 0x42U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, - 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, - 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, - 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xA2U, 0x40U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x9AU, 0x45U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, - 0x00U, 0x95U, 0x22U, 0x44U, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x52U, - 0x43U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, - 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0x52U, 0x43U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, - 0x05U, 0x04U, 0x35U, 0xF2U, 0x43U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x12U, 0x45U, 0x20U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x22U, 0x44U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, - 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x12U, 0x45U, - 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x12U, 0x45U, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, - 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x12U, 0x45U, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, - 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0x22U, 0x44U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x44U, - 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, - 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, - 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, - 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x2AU, 0x43U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, - 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, - 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x9AU, 0x45U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, - 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x8CU, 0x05U, 0x02U, - 0x01U, 0xB0U, 0x05U, 0x03U, 0x10U, 0x04U, 0x14U, 0x02U, 0x0DU, 0x50U, 0x14U, 0x00U, 0x10U, 0x04U, 0x14U, 0x01U, 0x08U, 0x44U, 0x14U, - 0x00U, 0x00U, 0xCEU, 0x00U, 0x00U, 0x35U, 0xC2U, 0x46U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x4AU, 0x47U, 0x20U, 0x08U, 0xCEU, - 0x14U, 0x00U, 0x35U, 0xD2U, 0x47U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x5AU, 0x48U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, - 0xE2U, 0x48U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x6AU, 0x49U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0xF2U, 0x49U, 0x20U, - 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x7AU, 0x4AU, 0x20U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, - 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, - 0x02U, 0x20U, 0x05U, 0x00U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, - 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x00U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, - 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, - 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x22U, 0x32U, 0x1CU, 0xB4U, - 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, - 0xB4U, 0x00U, 0x00U, 0x45U, 0x04U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, - 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, - 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x08U, 0x22U, 0x32U, 0x14U, - 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x22U, - 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, - 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x0CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, - 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, - 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x10U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, - 0x20U, 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x10U, - 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, - 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, - 0x05U, 0x14U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, - 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x14U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, - 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, - 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, - 0x00U, 0x45U, 0x18U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, - 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, - 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x32U, 0x32U, - 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x1CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, - 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, - 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x02U, 0x4BU, 0x20U, 0x12U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, - 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, - 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x08U, - 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xD2U, 0x4BU, 0x20U, 0x15U, 0x8AU, 0x4DU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, - 0x14U, 0x18U, 0x01U, 0x10U, 0x5CU, 0x41U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x46U, 0x24U, 0x00U, 0x55U, 0x4AU, 0x4CU, 0x20U, - 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, - 0x00U, 0x55U, 0x4AU, 0x4CU, 0x20U, 0x26U, 0x98U, 0x25U, 0x00U, 0x20U, 0xC8U, 0x01U, 0x00U, 0x35U, 0xCAU, 0x4CU, 0x20U, 0x01U, 0x08U, - 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x08U, 0x44U, 0x24U, 0x00U, 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, - 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xCAU, 0x4CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xD2U, 0x4BU, 0x20U, - 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, - 0x00U, 0x55U, 0xD2U, 0x4BU, 0x20U, 0x05U, 0x80U, 0x22U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x06U, 0xDCU, - 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, - 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x00U, 0x18U, 0x04U, 0x00U, - 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xD2U, 0x4BU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, - 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xD2U, 0x4BU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, - 0x00U, 0x00U, 0x15U, 0x42U, 0x4FU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x10U, 0x1CU, 0x51U, 0x48U, 0x10U, - 0x9CU, 0x70U, 0x48U, 0x08U, 0x46U, 0x24U, 0x00U, 0x55U, 0x02U, 0x4EU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, - 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x02U, 0x4EU, 0x20U, 0x26U, 0x98U, 0x25U, - 0x00U, 0x20U, 0xC8U, 0x01U, 0x00U, 0x35U, 0x82U, 0x4EU, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, - 0x24U, 0x00U, 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, - 0x82U, 0x4EU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x8AU, 0x4DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, - 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x8AU, 0x4DU, 0x20U, 0x05U, 0x80U, 0x22U, - 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, - 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, - 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x8AU, 0x4DU, 0x20U, - 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, - 0x00U, 0x55U, 0x8AU, 0x4DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x42U, 0x4FU, 0x20U, 0x00U, 0x28U, - 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, - 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x42U, 0x4FU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, - 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, - 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, - 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, - 0x12U, 0x50U, 0x20U, 0x15U, 0x5AU, 0x53U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, - 0x10U, 0xD4U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x41U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x44U, 0x34U, 0x00U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xA2U, 0x52U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xB2U, - 0x50U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, - 0xCCU, 0x14U, 0x00U, 0x55U, 0xB2U, 0x50U, 0x20U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, - 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0xD4U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x41U, 0x50U, 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, 0x32U, 0x51U, - 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, - 0x14U, 0x00U, 0x55U, 0x32U, 0x51U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x01U, - 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x91U, 0x58U, - 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x5CU, 0x41U, 0x48U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x72U, - 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xEAU, 0x51U, 0x20U, 0x20U, 0xCEU, - 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, - 0xEAU, 0x51U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x01U, 0x08U, 0x18U, 0x01U, - 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x10U, 0xDCU, 0x51U, - 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, - 0x15U, 0x00U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x12U, 0x50U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, - 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x12U, 0x50U, 0x20U, - 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0xA2U, 0x52U, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, - 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, - 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, - 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x12U, 0x50U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, - 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x12U, 0x50U, 0x20U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x56U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, - 0x18U, 0x01U, 0x10U, 0x14U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x71U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x44U, 0x34U, 0x00U, 0x05U, - 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xEAU, 0x55U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, - 0x55U, 0xFAU, 0x53U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, - 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xFAU, 0x53U, 0x20U, 0x35U, 0xEAU, 0x55U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, - 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0x14U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x71U, 0x50U, 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, - 0x7AU, 0x54U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, - 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x7AU, 0x54U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xEAU, 0x55U, - 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, - 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x5CU, 0x91U, 0x48U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, - 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xEAU, 0x55U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x32U, 0x55U, 0x20U, - 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, - 0x00U, 0x55U, 0x32U, 0x55U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xEAU, 0x55U, 0x20U, 0x01U, 0x10U, - 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x10U, - 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, - 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0xEAU, 0x55U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x5AU, 0x53U, 0x20U, 0x20U, 0xCEU, 0x00U, - 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x5AU, - 0x53U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0xEAU, 0x55U, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, - 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, - 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, - 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x5AU, 0x53U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, - 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x5AU, 0x53U, 0x20U, 0x1CU, - 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x56U, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, - 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x15U, 0xA2U, 0x56U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, - 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, - 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, - 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x14U, 0xFEU, 0x8FU, 0x00U, 0xDEU, 0x01U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, 0x35U, 0x7AU, 0x57U, - 0x20U, 0x15U, 0x82U, 0x5AU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x9CU, - 0x40U, 0x48U, 0x08U, 0x44U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, - 0xCAU, 0x59U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x0AU, 0x58U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, - 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x0AU, 0x58U, 0x20U, 0x35U, 0xCAU, 0x59U, - 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x1CU, 0x40U, 0x08U, 0x11U, 0x1CU, 0x78U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0x55U, 0x7AU, - 0x58U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, - 0xCCU, 0x14U, 0x00U, 0x55U, 0x7AU, 0x58U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xCAU, 0x59U, 0x20U, - 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, 0x08U, 0x46U, 0x44U, - 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, 0x08U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xCAU, - 0x59U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x22U, 0x59U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, - 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x22U, 0x59U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, - 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xCAU, 0x59U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, - 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x08U, 0x48U, 0x10U, 0x06U, 0x98U, - 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xCAU, 0x59U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x7AU, 0x57U, 0x20U, 0x20U, - 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, - 0x55U, 0x7AU, 0x57U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xCAU, 0x59U, 0x20U, 0x00U, 0x9CU, 0x9CU, - 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, - 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, - 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x7AU, 0x57U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, - 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x7AU, 0x57U, - 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x62U, 0x5DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x9CU, - 0x40U, 0x48U, 0x08U, 0x44U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, - 0xAAU, 0x5CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x02U, 0x5BU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, - 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x02U, 0x5BU, 0x20U, 0x35U, 0xAAU, 0x5CU, - 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x0DU, 0x1CU, 0x51U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0x55U, 0x6AU, 0x5BU, 0x20U, 0x20U, 0xCEU, - 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, - 0x6AU, 0x5BU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xAAU, 0x5CU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, - 0x0DU, 0x10U, 0x51U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, - 0x08U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xAAU, 0x5CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x0AU, - 0x5CU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, - 0xCCU, 0x14U, 0x00U, 0x55U, 0x0AU, 0x5CU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xAAU, 0x5CU, 0x20U, - 0x01U, 0x10U, 0x1CU, 0x01U, 0x0DU, 0x10U, 0x51U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x10U, 0x08U, 0x48U, 0x10U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xAAU, 0x5CU, 0x20U, 0x00U, 0x46U, - 0x00U, 0x00U, 0x55U, 0x82U, 0x5AU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, - 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x82U, 0x5AU, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, - 0x35U, 0xAAU, 0x5CU, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, - 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, - 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, - 0x82U, 0x5AU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, - 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x82U, 0x5AU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x62U, 0x5DU, - 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, - 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x62U, 0x5DU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, - 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x02U, 0x5EU, - 0x20U, 0x15U, 0x42U, 0x62U, 0x20U, 0x08U, 0x4AU, 0x84U, 0x0AU, 0x60U, 0x08U, 0x84U, 0x0AU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xE2U, - 0x5FU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x2AU, 0x5EU, 0x20U, 0x01U, - 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, - 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, - 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, - 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, - 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, - 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, - 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x10U, - 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, - 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x0CU, 0xF5U, 0x01U, - 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x2AU, 0x5EU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, - 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xBAU, 0x5FU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xBAU, 0x61U, 0x20U, 0x04U, 0x1CU, - 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xE2U, 0x5FU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, - 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, - 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, - 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xBAU, 0x61U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, - 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, - 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, - 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xBAU, 0x61U, - 0x20U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, - 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, - 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, - 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xBAU, 0x61U, 0x20U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, - 0x03U, 0x08U, 0x46U, 0x24U, 0x00U, 0xB5U, 0xE2U, 0x5FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x9AU, - 0x61U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x88U, 0x28U, 0x81U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, - 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, - 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, - 0x00U, 0xB5U, 0x02U, 0x5EU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x66U, 0x20U, 0x08U, 0x4AU, - 0x84U, 0x0AU, 0x60U, 0x08U, 0x84U, 0x0AU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x22U, 0x64U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x6AU, 0x62U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, - 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, - 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, - 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, - 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, - 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, - 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, - 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, - 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x66U, 0x16U, - 0x00U, 0x55U, 0x6AU, 0x62U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x63U, 0x20U, 0x08U, 0x46U, - 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xFAU, 0x65U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, - 0x22U, 0x64U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, - 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, - 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xFAU, - 0x65U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, - 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, - 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, - 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xFAU, 0x65U, 0x20U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, - 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, - 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, - 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, - 0x00U, 0x35U, 0xFAU, 0x65U, 0x20U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x46U, 0x24U, 0x00U, 0xB5U, 0x22U, - 0x64U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xDAU, 0x65U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, - 0x9CU, 0x9CU, 0x07U, 0x10U, 0x88U, 0x28U, 0x81U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, - 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x42U, 0x62U, 0x20U, 0x1CU, 0xB4U, - 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, - 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x66U, 0x20U, - 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, - 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0xA0U, 0x05U, 0x03U, 0x01U, 0x90U, 0x05U, 0x04U, 0x01U, 0xB0U, - 0x05U, 0x05U, 0x01U, 0xBCU, 0x05U, 0x06U, 0x01U, 0x9CU, 0x05U, 0x07U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x02U, - 0x00U, 0xF7U, 0x02U, 0x02U, 0x00U, 0x47U, 0x03U, 0x02U, 0x00U, 0x77U, 0x0EU, 0x0DU, 0x1EU, 0x15U, 0x00U, 0x40U, 0x1CU, 0x14U, 0x00U, - 0x20U, 0x1CU, 0x04U, 0x00U, 0x02U, 0x00U, 0x77U, 0x04U, 0x02U, 0x00U, 0x77U, 0x05U, 0x08U, 0x1EU, 0x15U, 0x00U, 0x26U, 0x00U, 0x44U, - 0x00U, 0x00U, 0x24U, 0xFCU, 0x0FU, 0x00U, 0x10U, 0xF6U, 0x0FU, 0x0CU, 0x64U, 0x42U, 0x00U, 0x00U, 0x10U, 0xF4U, 0x0FU, 0x0CU, 0x64U, - 0x42U, 0x00U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x01U, 0x08U, 0x07U, 0x00U, 0x08U, 0x88U, 0x14U, 0x00U, 0x02U, 0x00U, 0x27U, 0x00U, 0x01U, - 0x04U, 0x07U, 0x01U, 0x08U, 0x4AU, 0x44U, 0x05U, 0x60U, 0x08U, 0x44U, 0x05U, 0x80U, 0x48U, 0x00U, 0x00U, 0x02U, 0x00U, 0x27U, 0x07U, - 0x95U, 0x22U, 0x6AU, 0x20U, 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0x0AU, 0x68U, 0x20U, 0x15U, 0x2AU, 0x68U, 0x20U, 0x01U, 0x10U, 0x07U, - 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xF2U, 0x68U, 0x20U, 0x55U, 0x92U, 0x69U, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, - 0x15U, 0x00U, 0x35U, 0x72U, 0x68U, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0x92U, 0x68U, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, - 0xB2U, 0x68U, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0xD2U, 0x68U, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, - 0x55U, 0x92U, 0x69U, 0x20U, 0x35U, 0xFAU, 0x6DU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xF2U, 0x68U, - 0x20U, 0x55U, 0xFAU, 0x6DU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x92U, 0x69U, 0x20U, 0x55U, 0xFAU, - 0x6DU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0xF2U, 0x68U, 0x20U, 0x35U, 0xFAU, 0x6DU, 0x20U, 0x04U, - 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xF2U, 0x68U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x01U, 0x18U, 0x1CU, 0x02U, - 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, - 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x60U, 0x18U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, - 0x68U, 0x08U, 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x0CU, 0x04U, 0x00U, 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0xF2U, 0x68U, 0x20U, 0x15U, - 0xDAU, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x92U, 0x69U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, - 0x01U, 0x18U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, - 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x05U, 0x80U, 0x32U, 0x31U, 0x05U, 0x80U, 0x42U, 0x31U, 0x10U, 0x1CU, 0x60U, 0x10U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0x92U, 0x69U, 0x20U, 0x15U, 0xDAU, 0x6EU, 0x20U, 0x0DU, - 0x1EU, 0x16U, 0x00U, 0x55U, 0x3AU, 0x6AU, 0x20U, 0x15U, 0x5AU, 0x6AU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, - 0x35U, 0x22U, 0x6BU, 0x20U, 0x55U, 0xFAU, 0x6BU, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, 0x00U, 0x35U, 0xA2U, 0x6AU, - 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0xC2U, 0x6AU, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0xE2U, 0x6AU, 0x20U, 0x08U, 0x1EU, - 0x45U, 0x00U, 0x35U, 0x02U, 0x6BU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0xFAU, 0x6BU, 0x20U, 0x35U, - 0xD2U, 0x6CU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x22U, 0x6BU, 0x20U, 0x55U, 0xD2U, 0x6CU, 0x20U, - 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xFAU, 0x6BU, 0x20U, 0x55U, 0xD2U, 0x6CU, 0x20U, 0x01U, 0x10U, 0x07U, - 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0x22U, 0x6BU, 0x20U, 0x35U, 0xD2U, 0x6CU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, - 0xE5U, 0x03U, 0x75U, 0x22U, 0x6BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, - 0x10U, 0x40U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, - 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x1CU, 0x40U, - 0x18U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, 0x10U, 0x1CU, 0x48U, 0x08U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, 0x00U, 0x0CU, 0x04U, 0x00U, 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, - 0x22U, 0x6BU, 0x20U, 0x15U, 0xDAU, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xFAU, 0x6BU, 0x20U, - 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x00U, 0xDCU, 0x00U, - 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, 0x00U, 0x1CU, 0x01U, 0x00U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, - 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x1CU, 0x40U, 0x10U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, - 0x35U, 0xFAU, 0x6EU, 0x20U, 0x10U, 0x0CU, 0x48U, 0x10U, 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0xFAU, 0x6BU, 0x20U, 0x15U, 0xDAU, 0x6EU, - 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xD2U, 0x6CU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, - 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, - 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, - 0x31U, 0x10U, 0x40U, 0x08U, 0x00U, 0x18U, 0x01U, 0x00U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, - 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, - 0x6EU, 0x20U, 0x10U, 0x18U, 0x48U, 0x08U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, - 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x6EU, 0x20U, - 0x10U, 0x0CU, 0x48U, 0x10U, 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0xD2U, 0x6CU, 0x20U, 0x15U, 0xDAU, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, - 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xFAU, 0x6DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x00U, 0xFEU, - 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x10U, - 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x94U, 0x01U, 0x00U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, - 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, - 0x08U, 0x10U, 0x5CU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x08U, 0x10U, 0x1CU, 0x61U, 0x50U, 0x05U, 0x80U, - 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0xFAU, 0x6DU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, - 0xDEU, 0x05U, 0x04U, 0x35U, 0xDAU, 0x6EU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x01U, 0x08U, 0x07U, 0x07U, - 0x10U, 0x0CU, 0x20U, 0x01U, 0x06U, 0x8CU, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x31U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, - 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, - 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xCAU, 0x67U, 0x20U, 0x0DU, - 0x1EU, 0x16U, 0x00U, 0x55U, 0x92U, 0x6FU, 0x20U, 0x35U, 0xBAU, 0x6FU, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, - 0x28U, 0x00U, 0x44U, 0x00U, 0x46U, 0x00U, 0x44U, 0x00U, 0x15U, 0x4AU, 0x70U, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, - 0x00U, 0x35U, 0x02U, 0x70U, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0x4AU, 0x70U, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0x2AU, - 0x70U, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0x4AU, 0x70U, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, 0x28U, - 0x00U, 0x44U, 0x00U, 0x46U, 0x00U, 0x44U, 0x00U, 0x15U, 0x4AU, 0x70U, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, - 0x26U, 0x00U, 0x44U, 0x00U, 0x48U, 0x00U, 0x44U, 0x00U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, 0x20U, 0x1CU, 0x04U, - 0x00U, 0x40U, 0x1CU, 0x14U, 0x00U, 0x02U, 0x00U, 0x77U, 0x04U, 0x01U, 0x08U, 0x07U, 0x00U, 0x00U, 0x8AU, 0x00U, 0x00U, 0xB5U, 0xAAU, - 0x67U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, - 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, - 0x15U, 0x9AU, 0x70U, 0x20U}; - -const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); +static smartdma_param_t s_smartdmaParam; /******************************************************************************* * Prototypes @@ -853,8 +81,8 @@ void SMARTDMA_InitWithoutFirmware(void) void SMARTDMA_InstallFirmware(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte) { (void)memcpy((void *)(uint8_t *)apiMemAddr, firmware, firmwareSizeByte); - SMARTDMA->SMARTDMA_CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); - s_smartdmaApiTable = (smartdma_func_t *)apiMemAddr; + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); + s_smartdmaApiTable = (smartdma_func_t *)apiMemAddr; } /*! @@ -872,22 +100,41 @@ void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param) * brief Boot the SMARTDMA to run program. * * param apiIndex Index of the API to call. - * param pParam Pointer to the parameter. + * param pParam Pointer to the parameter allocated by caller. * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. */ void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask) { - SMARTDMA->SMARTDMA_ARM2SMARTDMA = (uint32_t)(uint8_t *)pParam | (uint32_t)mask; - SMARTDMA->SMARTDMA_BOOT = (uint32_t)(s_smartdmaApiTable[apiIndex]); - SMARTDMA->SMARTDMA_CTRL = 0xC0DE0011U | (0U << SMARTDMA_MASK_RESP) | (0U << SMARTDMA_ENABLE_AHBBUF); /* BOOT */ + SMARTDMA->ARM2EZH = (uint32_t)(uint8_t *)pParam | (uint32_t)mask; + SMARTDMA->BOOTADR = (uint32_t)(s_smartdmaApiTable[apiIndex]); + SMARTDMA->CTRL = 0xC0DE0011U | (0U << SMARTDMA_MASK_RESP) | (0U << SMARTDMA_ENABLE_AHBBUF); /* BOOT */ }; +/* + * brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * param apiIndex Index of the API to call. + * param pParam Pointer to the parameter. + * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + * note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask) +{ + (void)memcpy(&s_smartdmaParam, pParam, sizeof(smartdma_param_t)); + SMARTDMA_Boot(apiIndex, &s_smartdmaParam, mask); +} + /*! * brief Deinitialize the SMARTDMA. */ void SMARTDMA_Deinit(void) { - SMARTDMA->SMARTDMA_CTRL = 0xC0DE0000U; + SMARTDMA->CTRL = 0xC0DE0000U; CLOCK_DisableClock(kCLOCK_Smartdma); } @@ -897,7 +144,7 @@ void SMARTDMA_Deinit(void) void SMARTDMA_Reset(void) { RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); - SMARTDMA->SMARTDMA_CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); } /*! @@ -910,9 +157,3 @@ void SMARTDMA_HandleIRQ(void) s_smartdmaCallback(s_smartdmaCallbackParam); } } - -void SDMA_IRQHandler(void); -void SDMA_IRQHandler(void) -{ - SMARTDMA_HandleIRQ(); -} diff --git a/drivers/smartdma/fsl_smartdma.h b/drivers/smartdma/fsl_smartdma.h index 17d0ce4af..8741711c9 100644 --- a/drivers/smartdma/fsl_smartdma.h +++ b/drivers/smartdma/fsl_smartdma.h @@ -2,15 +2,25 @@ * Copyright 2019-2023 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SMARTDMA_H_ -#define _FSL_SMARTDMA_H_ +#ifndef FSL_SMARTDMA_H_ +#define FSL_SMARTDMA_H_ #include "fsl_common.h" +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) +#include "fsl_smartdma_rt500.h" +#elif defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || \ + defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ + defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#include "fsl_smartdma_mcxn.h" +#else +#error "Device not supported" +#endif + /*! * @addtogroup smartdma * @{ @@ -23,187 +33,9 @@ /*! @name Driver version */ /*@{*/ /*! @brief SMARTDMA driver version */ -#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) +#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) /*@}*/ -/*! @brief The firmware used for display. */ -extern const uint8_t s_smartdmaDisplayFirmware[]; - -/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ -#define SMARTDMA_DISPLAY_MEM_ADDR 0x24100000 - -/*! @brief Size of s_smartdmaDisplayFirmware */ -#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) - -/*! @brief Size of s_smartdmaDisplayFirmware */ -extern const uint32_t s_smartdmaDisplayFirmwareSize; - -/*! @brief Compatibility redefinition. */ -#define s_smartdmaFlexioMcuLcdFirmware s_smartdmaDisplayFirmware -#define SMARTDMA_FLEXIO_MCULCD_MEM_ADDR SMARTDMA_DISPLAY_MEM_ADDR -#define SMARTDMA_FLEXIO_MCULCD_FIRMWARE_SIZE SMARTDMA_DISPLAY_FIRMWARE_SIZE -#define s_smartdmaFlexioMcuLcdFirmwareSize s_smartdmaDisplayFirmwareSize - -/*! - * @brief The API index when using s_smartdmaFlexioMcuLcdFirmware. - */ -enum _smartdma_flexio_mculcd_api -{ - kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, - kSMARTDMA_FlexIO_DMA_Reverse32, - kSMARTDMA_FlexIO_DMA, - kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ - kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter - smartdma_rgb565_rgb888_param_t. */ - kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter - smartdma_flexio_mculcd_param_t. */ - kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter - smartdma_flexio_mculcd_param_t. */ - kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use - parameter smartdma_flexio_mculcd_param_t. */ - kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send - to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ - kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ - kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. */ - kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ - kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. */ - kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ - kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. */ - kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter smartdma_dsi_param_t. - */ - kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter smartdma_dsi_param_t. - */ - kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter - smartdma_dsi_param_t */ - kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ - kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, use parameter - smartdma_dsi_checkerboard_param_t. */ - kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ -}; - -/*! - * @brief Parameter for FlexIO MCULCD except kSMARTDMA_FlexIO_DMA_ONELANE - */ -typedef struct _smartdma_flexio_mculcd_param -{ - uint32_t *p_buffer; - uint32_t buffersize; - uint32_t *smartdma_stack; -} smartdma_flexio_mculcd_param_t; - -/*! - * @brief Parameter for kSMARTDMA_FlexIO_DMA_ONELANE - */ -typedef struct _smartdma_flexio_onelane_mculcd_param -{ - uint32_t *p_buffer; - uint32_t buffersize; - uint32_t offset; - uint32_t *smartdma_stack; -} smartdma_flexio_onelane_mculcd_param_t; - -/*! - * @brief Parameter for MIPI DSI - */ -typedef struct _smartdma_dsi_param -{ - /*! Pointer to the buffer to send. */ - const uint8_t *p_buffer; - /*! Buffer size in byte. */ - uint32_t buffersize; - /*! Stack used by SMARTDMA. */ - uint32_t *smartdma_stack; - /*! - * If set to 1, the pixels are filled to MIPI DSI FIFO directly. - * If set to 0, the pixel bytes are swapped then filled to - * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel - * format is RGB565: - * LSB MSB - * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 - * Then the pixel filled to DSI FIFO is: - * LSB MSB - * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 - */ - uint32_t disablePixelByteSwap; -} smartdma_dsi_param_t; - -/*! - * @brief Parameter for kSMARTDMA_MIPI_RGB565_DMA2D, kSMARTDMA_MIPI_RGB888_DMA2D - * and kSMARTDMA_MIPI_XRGB2RGB_DMA2D. - */ -typedef struct _smartdma_dsi_2d_param -{ - /*! Pointer to the buffer to send. */ - const uint8_t *p_buffer; - /*! SRC data transfer in a minor loop */ - uint32_t minorLoop; - /*! SRC data offset added after a minor loop */ - uint32_t minorLoopOffset; - /*! SRC data transfer in a major loop */ - uint32_t majorLoop; - /*! Stack used by SMARTDMA. */ - uint32_t *smartdma_stack; - /*! - * If set to 1, the pixels are filled to MIPI DSI FIFO directly. - * If set to 0, the pixel bytes are swapped then filled to - * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel - * format is RGB565: - * LSB MSB - * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 - * Then the pixel filled to DSI FIFO is: - * LSB MSB - * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 - */ - uint32_t disablePixelByteSwap; -} smartdma_dsi_2d_param_t; - -/*! - * @brief Parameter for kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA - */ -typedef struct _smartdma_dsi_checkerboard_param -{ - /*! Pointer to the buffer to send, pixel format is ARGB8888. */ - const uint8_t *p_buffer; - uint32_t height; /*! Height resolution in pixel. */ - uint32_t width; /*! Width resolution in pixel. */ - /*! Cube block type. - * cbType=1 : 1/2 pixel mask cases - * cbType=2 : 1/4 pixel mask cases - */ - uint32_t cbType; - /*! which pixel is turned off in each type - * cbType=2: indexOff= 1,2,3,4 - * cbType=1: indexOff= 0,1 - */ - uint32_t indexOff; - /*! Stack used by SMARTDMA. */ - uint32_t *smartdma_stack; - /*! - * If set to 1, the pixels are filled to MIPI DSI FIFO directly. - * If set to 0, the pixel bytes are swapped then filled to - * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel - * for example - * format is RGB888: - * LSB MSB - * B0 B1 B2 B3 B4 B5 B6 B7 | G0 G1 G2 G3 G4 G5 G6 G7 | R0 R1 R2 R3 R4 R5 R6 R7 - * Then the pixel filled to DSI FIFO is: - * LSB MSB - * R0 R1 R2 R3 R4 R5 R6 R7 | G0 G1 G2 G3 G4 G5 G6 G7 | B0 B1 B2 B3 B4 B5 B6 B7 - */ - uint32_t disablePixelByteSwap; -} smartdma_dsi_checkerboard_param_t; - -/*! - * @brief Parameter for RGB565To888 - */ -typedef struct _smartdma_rgb565_rgb888_param -{ - uint32_t *inBuf; - uint32_t *outBuf; - uint32_t buffersize; - uint32_t *smartdma_stack; -} smartdma_rgb565_rgb888_param_t; - /*! @brief Callback function prototype for the smartdma driver. */ typedef void (*smartdma_callback_t)(void *param); @@ -221,7 +53,7 @@ extern "C" { * @param apiMemAddr The address firmware will be copied to. * @param firmware The firmware to use. * @param firmwareSizeByte Size of firmware. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + * @deprecated Do not use this function. It has been superceded by * @ref SMARTDMA_InitWithoutFirmware and @ref SMARTDMA_InstallFirmware. */ void SMARTDMA_Init(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte); @@ -258,11 +90,27 @@ void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param); * @brief Boot the SMARTDMA to run program. * * @param apiIndex Index of the API to call. + * @param pParam Pointer to the parameter allocated by caller. + * @param mask Value set to register SMARTDMA->ARM2EZH[0:1]. + * @note Only call this function when SMARTDMA is not busy. + * @note The memory *pParam shall not be freed before the SMARTDMA function finished. + */ +void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask); + +/*! + * @brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with @ref SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * @param apiIndex Index of the API to call. * @param pParam Pointer to the parameter. * @param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. * @note Only call this function when SMARTDMA is not busy. */ -void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask); +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask); /*! * @brief Deinitialize the SMARTDMA. @@ -285,4 +133,4 @@ void SMARTDMA_HandleIRQ(void); /* @} */ -#endif /* _FSL_SMARTDMA_H_ */ +#endif /* FSL_SMARTDMA_H_ */ diff --git a/drivers/smartdma/fsl_smartdma_mcxn.c b/drivers/smartdma/fsl_smartdma_mcxn.c new file mode 100644 index 000000000..887901879 --- /dev/null +++ b/drivers/smartdma/fsl_smartdma_mcxn.c @@ -0,0 +1,445 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \ + defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ + defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN236_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x24U, 0x00U, 0x00U, 0x04U, 0x18U, 0x01U, 0x00U, 0x04U, 0xC8U, 0x02U, 0x00U, 0x04U, 0xF0U, 0x01U, 0x00U, 0x04U, + 0x7CU, 0x03U, 0x00U, 0x04U, 0xACU, 0x08U, 0x00U, 0x04U, 0x10U, 0x0EU, 0x00U, 0x04U, 0x38U, 0x10U, 0x00U, 0x04U, + 0xC0U, 0x12U, 0x00U, 0x04U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x01U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x02U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x03U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x04U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x05U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x06U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xF2U, 0x01U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, + 0x0CU, 0x88U, 0x30U, 0x00U, 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0x07U, 0x07U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, + 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x02U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x03U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, + 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0x08U, 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x04U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x06U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x03U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x06U, 0x18U, 0x10U, 0x00U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, 0xFFU, + 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x00U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x02U, 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x03U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, 0xFFU, + 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x04U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x05U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x06U, 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x52U, 0x05U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, + 0x0CU, 0x88U, 0x30U, 0x00U, 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x02U, 0xC0U, 0x25U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, 0x02U, 0xC0U, 0x45U, 0x02U, + 0x02U, 0xC0U, 0x55U, 0x03U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x02U, 0xC0U, 0x25U, 0x04U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x02U, 0xC0U, 0x45U, 0x06U, + 0x02U, 0xC0U, 0x55U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xBAU, 0x06U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0xA4U, 0x05U, 0x01U, 0x01U, 0x84U, 0x05U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x03U, 0x10U, 0x04U, 0x14U, 0x06U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, + 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, + 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, + 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, + 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, + 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, + 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x42U, 0x07U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x11U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x06U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, + 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, + 0x02U, 0xC0U, 0x35U, 0x00U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x90U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x55U, 0x02U, 0xC0U, 0x35U, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x38U, 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x02U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, + 0x10U, 0xCCU, 0x40U, 0x45U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x03U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x90U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, + 0x10U, 0xCCU, 0x40U, 0x55U, 0x02U, 0xC0U, 0x35U, 0x04U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, + 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x06U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x90U, 0x40U, 0x00U, + 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x55U, + 0x02U, 0xC0U, 0x35U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x38U, 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, + 0x10U, 0xCCU, 0x40U, 0x45U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x90U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, + 0x10U, 0xCCU, 0x40U, 0x55U, 0x02U, 0xC0U, 0x35U, 0x02U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x03U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, + 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x04U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x90U, 0x40U, 0x00U, + 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x55U, + 0x02U, 0xC0U, 0x35U, 0x05U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, 0x10U, 0xCCU, 0x48U, 0x40U, + 0x02U, 0xC0U, 0x35U, 0x06U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, + 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x90U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, + 0x10U, 0xCCU, 0x40U, 0x55U, 0x02U, 0xC0U, 0x35U, 0x00U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, + 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x02U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x90U, 0x40U, 0x00U, + 0x10U, 0xCCU, 0x40U, 0x53U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x55U, + 0x02U, 0xC0U, 0x35U, 0x03U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x10U, 0x90U, 0x40U, 0x30U, 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0xCCU, 0x48U, 0x43U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, 0x10U, 0xCCU, 0x48U, 0x40U, + 0x02U, 0xC0U, 0x35U, 0x04U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x45U, 0x00U, 0x10U, 0x84U, 0x0FU, + 0x10U, 0x90U, 0x40U, 0x28U, 0x10U, 0xCCU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, + 0x10U, 0xCCU, 0x40U, 0x4BU, 0x02U, 0xC0U, 0x35U, 0x05U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x48U, 0x50U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x0DU, 0x90U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x53U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x24U, 0x10U, 0xCCU, 0x40U, 0x55U, 0x02U, 0xC0U, 0x35U, 0x06U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x10U, 0x90U, 0x40U, 0x30U, + 0x10U, 0xCCU, 0x48U, 0x45U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0xCCU, 0x48U, 0x43U, + 0x00U, 0x10U, 0x84U, 0x0FU, 0x10U, 0x90U, 0x40U, 0x38U, 0x10U, 0xCCU, 0x48U, 0x40U, 0x02U, 0xC0U, 0x35U, 0x07U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xD2U, 0x11U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xE2U, 0x1BU, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, + 0x00U, 0x18U, 0xFEU, 0x8FU, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x1BU, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, + 0x02U, 0xC0U, 0x45U, 0x02U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x03U, + 0x02U, 0xC0U, 0x35U, 0x04U, 0x02U, 0xC0U, 0x45U, 0x05U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x06U, 0x02U, 0xC0U, 0x35U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x01U, + 0x02U, 0xC0U, 0x35U, 0x02U, 0x02U, 0xC0U, 0x45U, 0x03U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x04U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x02U, 0xC0U, 0x45U, 0x06U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x02U, 0xC0U, 0x35U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x02U, 0x02U, 0xC0U, 0x35U, 0x03U, 0x02U, 0xC0U, 0x45U, 0x04U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x05U, 0x02U, 0xC0U, 0x35U, 0x06U, 0x02U, 0xC0U, 0x45U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x32U, 0x20U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x00U, 0x08U, 0x26U, 0x05U, + 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x02U, 0xC0U, 0x35U, 0x01U, 0x02U, 0xC0U, 0x45U, 0x02U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x03U, + 0x02U, 0xC0U, 0x35U, 0x04U, 0x02U, 0xC0U, 0x45U, 0x05U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x06U, + 0x02U, 0xC0U, 0x35U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x02U, 0xC0U, 0x45U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x01U, 0x02U, 0xC0U, 0x35U, 0x02U, 0x02U, 0xC0U, 0x45U, 0x03U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x04U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x02U, 0xC0U, 0x45U, 0x06U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x02U, 0xC0U, 0x35U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x02U, + 0x02U, 0xC0U, 0x35U, 0x03U, 0x02U, 0xC0U, 0x45U, 0x04U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x05U, + 0x02U, 0xC0U, 0x35U, 0x06U, 0x02U, 0xC0U, 0x45U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x42U, 0x25U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x00U, 0x18U, 0xFEU, 0x8FU, + 0x06U, 0x00U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, + 0x0CU, 0x88U, 0x30U, 0x00U, 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, + 0x02U, 0xC0U, 0x45U, 0x02U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x03U, 0x02U, 0xC0U, 0x35U, 0x04U, + 0x02U, 0xC0U, 0x45U, 0x05U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x06U, 0x02U, 0xC0U, 0x35U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x02U, 0xC0U, 0x45U, 0x00U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x01U, 0x02U, 0xC0U, 0x35U, 0x02U, 0x02U, 0xC0U, 0x45U, 0x03U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x04U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x02U, 0xC0U, 0x45U, 0x06U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x02U, 0xC0U, 0x35U, 0x00U, + 0x02U, 0xC0U, 0x45U, 0x01U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x02U, 0x02U, 0xC0U, 0x35U, 0x03U, + 0x02U, 0xC0U, 0x45U, 0x04U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x05U, 0x02U, 0xC0U, 0x35U, 0x06U, + 0x02U, 0xC0U, 0x45U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x2AU, 0x00U}; + +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +const uint8_t s_smartdmaCameraFirmware[] = { + 0x21U, 0x00U, 0x00U, 0x04U, 0xE1U, 0x00U, 0x00U, 0x04U, 0xE1U, 0x02U, 0x00U, 0x04U, 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0FU, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x9FU, 0x00U, 0x00U, 0x04U, + 0xBBU, 0x00U, 0x00U, 0x04U, 0x02U, 0xC4U, 0x08U, 0x01U, 0x83U, 0x00U, 0x00U, 0x04U, 0x18U, 0xECU, 0x02U, 0xC0U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x01U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x05U, 0x44U, 0x00U, 0x33U, 0x83U, 0x00U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20U, 0x18U, 0xCCU, 0x00U, 0x21U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x18U, 0x20U, 0x02U, 0xF2U, 0x83U, 0x00U, 0x00U, 0x04U, + 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x08U, 0x14U, 0x00U, + 0x00U, 0x14U, 0x04U, 0x00U, 0x1CU, 0x36U, 0xD0U, 0x04U, 0x0DU, 0x80U, 0xF7U, 0x0FU, 0x18U, 0xECU, 0x02U, 0xC2U, + 0x67U, 0x01U, 0x00U, 0x04U, 0x87U, 0x01U, 0x00U, 0x04U, 0x08U, 0x76U, 0xC7U, 0x01U, 0x02U, 0xC4U, 0x08U, 0x01U, + 0x18U, 0x20U, 0x02U, 0xF2U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x00U, 0x08U, 0x14U, 0x00U, 0x00U, 0x14U, 0x04U, 0x00U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x47U, 0x01U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20U, 0x18U, 0xCCU, 0x00U, 0x21U, 0x00U, 0x14U, 0x04U, 0x00U, + 0x0DU, 0x88U, 0xF4U, 0x1FU, 0x01U, 0x90U, 0x05U, 0x02U, 0x0EU, 0x82U, 0xF4U, 0x00U, 0x20U, 0x04U, 0x04U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xE4U, 0x01U, 0x20U, 0x04U, 0x14U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xD4U, 0x02U, + 0x20U, 0x04U, 0x24U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xC4U, 0x03U, + 0x20U, 0x04U, 0x34U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0xB4U, 0x04U, 0x20U, 0x04U, 0x44U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0xA4U, 0x05U, 0x20U, 0x04U, 0x54U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x94U, 0x06U, 0x20U, 0x04U, 0x64U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x84U, 0x07U, 0x20U, 0x04U, 0x74U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x74U, 0x08U, 0x20U, 0x04U, 0x84U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x64U, 0x09U, 0x20U, 0x04U, 0x94U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x54U, 0x0AU, + 0x20U, 0x04U, 0xA4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x44U, 0x0BU, + 0x20U, 0x04U, 0xB4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0x34U, 0x0CU, 0x20U, 0x04U, 0xC4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0x24U, 0x0DU, 0x20U, 0x04U, 0xD4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x14U, 0x0EU, 0x20U, 0x04U, 0xE4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x0EU, 0x82U, 0x04U, 0x0FU, + 0x20U, 0x04U, 0xF4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x38U, 0xECU, 0x02U, 0x21U, 0x38U, 0xECU, 0x02U, 0x22U, 0x06U, 0x88U, 0x14U, 0x00U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x47U, 0x01U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0FU, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x6BU, 0x03U, 0x00U, 0x04U, + 0x8BU, 0x03U, 0x00U, 0x04U, 0x08U, 0xBEU, 0x04U, 0x3CU, 0x82U, 0xC4U, 0x08U, 0x01U, 0x08U, 0x76U, 0x47U, 0x02U, + 0x98U, 0x20U, 0x02U, 0xF2U, 0x06U, 0x88U, 0x14U, 0x00U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x18U, 0xECU, 0x02U, 0xC1U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x00U, 0x08U, 0x04U, 0x00U, 0x00U, 0x10U, 0x04U, 0x00U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x05U, 0x44U, 0x00U, 0x33U, 0x43U, 0x03U, 0x00U, 0x04U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x06U, 0x10U, 0x15U, 0x00U, + 0x08U, 0x3EU, 0x05U, 0x05U, 0xB8U, 0xECU, 0x02U, 0xC2U, 0x08U, 0x3EU, 0x05U, 0x19U, 0xB8U, 0xECU, 0x02U, 0x22U, + 0x00U, 0x08U, 0x04U, 0x00U, 0x43U, 0x03U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0x00, +}; + +const uint32_t s_smartdmaCameraFirmwareSize = sizeof(s_smartdmaCameraFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SMARTDMA_IRQHandler(void); +void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/drivers/smartdma/fsl_smartdma_mcxn.h b/drivers/smartdma/fsl_smartdma_mcxn.h new file mode 100644 index 000000000..ceadc8841 --- /dev/null +++ b/drivers/smartdma/fsl_smartdma_mcxn.h @@ -0,0 +1,136 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_MCXN_H_ +#define FSL_SMARTDMA_MCXN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_mcxn MCXN SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#define SMARTDMA_USE_FLEXIO_SHIFTER_DMA 1 +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +/*! @brief The firmware used for camera. */ +extern const uint8_t s_smartdmaCameraFirmware[]; + +/*! @brief The s_smartdmaCameraFirmware firmware memory address. */ +#define SMARTDMA_CAMERA_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmacameraFirmware */ +#define SMARTDMA_CAMERA_FIRMWARE_SIZE (s_smartdmaCameraFirmwareSize) + +/*! @brief Size of s_smartdmacameraFirmware */ +extern const uint32_t s_smartdmaCameraFirmwareSize; + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ +}; + +/*! + * @brief Parameter for FlexIO MCULCD + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief The API index when using s_smartdmaCameraFirmware + */ +enum _smartdma_camera_api +{ + /*! Save whole camera frame to buffer, only supports QVGA(320x240), QQVGA(160x120). */ + kSMARTDMA_FlexIO_CameraWholeFrame = 0U, + /*! Save only first 1/16 of camera frame to buffer, only supports QVGA(320x240). */ + kSMARTDMA_FlexIO_CameraDiv16Frame = 1U, +}; + +/*! + * @brief Parameter for camera + */ +typedef struct _smartdma_camera_param +{ + uint32_t *smartdma_stack; /*!< Stack used by SMARTDMA, shall be at least 64 bytes. */ + uint32_t *p_buffer; /*!< Buffer to store the received camera data. */ +} smartdma_camera_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; /*!< Parameter for flexio MCULCD. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; /*!< Parameter for RGB565_RGB888 convertion. */ + smartdma_camera_param_t cameraParam; /*!< Parameter for camera. */ +} smartdma_param_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_MCXN_H_ */ diff --git a/drivers/smartdma/fsl_smartdma_prv.h b/drivers/smartdma/fsl_smartdma_prv.h index 9c5305f9a..f297aa068 100644 --- a/drivers/smartdma/fsl_smartdma_prv.h +++ b/drivers/smartdma/fsl_smartdma_prv.h @@ -29,8 +29,8 @@ * this code. */ -#ifndef _FSL_SMARTDMA_PRV_H_ -#define _FSL_SMARTDMA_PRV_H_ +#ifndef FSL_SMARTDMA_PRV_H_ +#define FSL_SMARTDMA_PRV_H_ #include "fsl_common.h" diff --git a/drivers/smartdma/fsl_smartdma_rt500.c b/drivers/smartdma/fsl_smartdma_rt500.c new file mode 100644 index 000000000..f8952e16e --- /dev/null +++ b/drivers/smartdma/fsl_smartdma_rt500.c @@ -0,0 +1,2518 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x60U, 0x00U, 0x10U, 0x24U, 0x40U, 0x01U, 0x10U, 0x24U, 0xC8U, 0x02U, 0x10U, 0x24U, + 0x04U, 0x02U, 0x10U, 0x24U, 0x68U, 0x03U, 0x10U, 0x24U, 0x98U, 0x08U, 0x10U, 0x24U, + 0xE8U, 0x0DU, 0x10U, 0x24U, 0xFCU, 0x0FU, 0x10U, 0x24U, 0x70U, 0x12U, 0x10U, 0x24U, + 0xE8U, 0x14U, 0x10U, 0x24U, 0xACU, 0x25U, 0x10U, 0x24U, 0x54U, 0x16U, 0x10U, 0x24U, + 0xCCU, 0x27U, 0x10U, 0x24U, 0x18U, 0x19U, 0x10U, 0x24U, 0x7CU, 0x2BU, 0x10U, 0x24U, + 0xE4U, 0x1BU, 0x10U, 0x24U, 0x54U, 0x1DU, 0x10U, 0x24U, 0x24U, 0x20U, 0x10U, 0x24U, + 0xDCU, 0x2EU, 0x10U, 0x24U, 0x68U, 0x33U, 0x10U, 0x24U, 0x70U, 0x38U, 0x10U, 0x24U, + 0x8CU, 0x3BU, 0x10U, 0x24U, 0xF8U, 0x22U, 0x10U, 0x24U, 0x44U, 0x3EU, 0x10U, 0x24U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x08U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x04U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x14U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x42U, 0x02U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0x07U, 0x07U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, + 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0xFFU, + 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0xFFU, + 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0x08U, + 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xCAU, 0x03U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x06U, 0x18U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x05U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, + 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, + 0x05U, 0x08U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 0x32U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, + 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, + 0x05U, 0x18U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x52U, 0x05U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, + 0x05U, 0x08U, 0x42U, 0x32U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x92U, 0x06U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0xA4U, 0x05U, 0x01U, 0x01U, 0x84U, 0x05U, 0x02U, + 0x01U, 0xB0U, 0x05U, 0x03U, 0x10U, 0x04U, 0x14U, 0x06U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x02U, 0x44U, 0x3EU, 0x01U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x02U, 0x44U, 0x3EU, 0x01U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x1AU, 0x07U, 0x20U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xF2U, 0x10U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x06U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, + 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x05U, 0x08U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, + 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x00U, 0x32U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, + 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, + 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x08U, 0x32U, 0x32U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x0CU, 0x32U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, + 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, + 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x14U, 0x32U, 0x32U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x18U, 0x32U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x04U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x08U, 0x32U, 0x32U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x10U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x14U, 0x32U, 0x32U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x82U, 0x11U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x92U, 0x1BU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x1BU, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, 0x04U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, 0x32U, 0x32U, + 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, + 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xBAU, 0x1FU, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, + 0x05U, 0x08U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x05U, 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x18U, 0x22U, 0x32U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, + 0x05U, 0x18U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, + 0x05U, 0x04U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, + 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xA2U, 0x24U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x00U, 0x18U, 0xFEU, 0x8FU, + 0x06U, 0x00U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x07U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, 0x04U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, 0x32U, 0x32U, + 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, + 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x92U, 0x29U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, + 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x32U, 0x2AU, 0x20U, 0x15U, 0x5AU, 0x2BU, 0x20U, + 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, + 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x5AU, 0x2AU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x10U, 0x4CU, 0x10U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, + 0x55U, 0x5AU, 0x2AU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xB2U, 0x2AU, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0x32U, 0x2AU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x6AU, 0x2CU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x82U, 0x2BU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0x82U, 0x2BU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xCAU, 0x2BU, 0x20U, + 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x5AU, 0x2BU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x6AU, 0x2CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x0AU, 0x2DU, 0x20U, + 0x15U, 0xC2U, 0x2FU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x2AU, 0x2EU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x32U, 0x2DU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x10U, 0x0CU, 0x31U, 0x48U, + 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x14U, 0x50U, 0x10U, 0x11U, 0x1CU, 0x60U, 0x00U, + 0x10U, 0x1CU, 0x70U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xF6U, 0x0FU, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x08U, 0x66U, 0x16U, 0x00U, + 0x55U, 0x32U, 0x2DU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x02U, 0x2EU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0x42U, 0x2FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x2AU, 0x2EU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x42U, 0x2FU, 0x20U, + 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x10U, 0x0CU, 0x31U, 0x48U, + 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x42U, 0x2FU, 0x20U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x14U, 0x50U, 0x10U, 0x11U, 0x1CU, 0x60U, 0x00U, 0x10U, 0x1CU, 0x70U, 0x10U, + 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x42U, 0x2FU, 0x20U, 0x00U, 0x0CU, 0xF6U, 0x0FU, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x2AU, 0x2EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x22U, 0x2FU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, + 0xB5U, 0x0AU, 0x2DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0xF2U, 0x31U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xA2U, 0x30U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xEAU, 0x2FU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x18U, + 0x10U, 0x1CU, 0x51U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x14U, 0x58U, 0x18U, + 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x18U, + 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xEAU, 0x2FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x72U, 0x30U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x7AU, 0x31U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xA2U, 0x30U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x7AU, 0x31U, 0x20U, + 0x10U, 0x10U, 0x48U, 0x18U, 0x10U, 0x1CU, 0x51U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x7AU, 0x31U, 0x20U, 0x10U, 0x14U, 0x58U, 0x18U, + 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x7AU, 0x31U, 0x20U, 0x10U, 0x0CU, 0x68U, 0x18U, 0x08U, 0x46U, 0x34U, 0x00U, + 0xB5U, 0xA2U, 0x30U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x5AU, 0x31U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xC2U, 0x2FU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xF2U, 0x31U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0x24U, 0xF4U, 0x0FU, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0x9AU, 0x32U, 0x20U, 0x15U, 0x1AU, 0x35U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, + 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x9AU, 0x33U, 0x20U, + 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xC2U, 0x32U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x22U, 0x16U, 0x00U, + 0x55U, 0xC2U, 0x32U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x6AU, 0x33U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0x92U, 0x34U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x9AU, 0x33U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x92U, 0x34U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, + 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x92U, 0x34U, 0x20U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x92U, 0x34U, 0x20U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, + 0xB5U, 0x9AU, 0x33U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x72U, 0x34U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0xB5U, 0x9AU, 0x32U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x8AU, 0x37U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x12U, 0x36U, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x42U, 0x35U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, + 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x4CU, 0x4AU, 0x30U, + 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0x42U, 0x35U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xE2U, 0x35U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x02U, 0x37U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x12U, 0x36U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x02U, 0x37U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, + 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x02U, 0x37U, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, + 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x02U, 0x37U, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x46U, 0x44U, 0x00U, + 0xB5U, 0x12U, 0x36U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xE2U, 0x36U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x1AU, 0x35U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x37U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, + 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x32U, 0x38U, 0x20U, + 0x15U, 0x52U, 0x39U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x5AU, 0x38U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, + 0x55U, 0x5AU, 0x38U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xAAU, 0x38U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0x32U, 0x38U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x6AU, 0x3AU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x7AU, 0x39U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x10U, 0x4CU, 0x10U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, + 0x55U, 0x7AU, 0x39U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xCAU, 0x39U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0x52U, 0x39U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x6AU, 0x3AU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x06U, 0x00U, 0x10U, 0x00U, + 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x12U, 0x3BU, 0x20U, 0x15U, 0x7AU, 0x3DU, 0x20U, + 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, + 0x95U, 0x0AU, 0x3CU, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x3AU, 0x3BU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x00U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x10U, 0xF5U, 0x0FU, + 0x11U, 0x1CU, 0x58U, 0x00U, 0x10U, 0x1CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, 0x10U, 0x5CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x08U, 0x66U, 0x16U, 0x00U, + 0x55U, 0x3AU, 0x3BU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xE2U, 0x3BU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0xFAU, 0x3CU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x2AU, 0x2EU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x00U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xFAU, 0x3CU, 0x20U, + 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x58U, 0x00U, 0x10U, 0x1CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xFAU, 0x3CU, 0x20U, + 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, 0x10U, 0x5CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xFAU, 0x3CU, 0x20U, + 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x0AU, 0x3CU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xDAU, 0x3CU, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x12U, 0x3BU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x0AU, 0x40U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x8AU, 0x3EU, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xA2U, 0x3DU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0x1CU, 0x48U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x10U, 0x1CU, 0x68U, 0x18U, + 0x10U, 0x1CU, 0x70U, 0x18U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x10U, 0xDCU, 0x41U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x14U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x60U, 0x10U, + 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, + 0x0DU, 0xCCU, 0xF4U, 0x0FU, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xA2U, 0x3DU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x72U, 0x30U, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x92U, 0x3FU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x8AU, 0x3EU, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x10U, 0x1CU, 0x48U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x92U, 0x3FU, 0x20U, 0x0DU, 0x10U, 0xF5U, 0x0FU, + 0x10U, 0x1CU, 0x68U, 0x18U, 0x10U, 0x1CU, 0x70U, 0x18U, 0x10U, 0xDCU, 0x59U, 0x50U, + 0x10U, 0xDCU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x92U, 0x3FU, 0x20U, 0x10U, 0x14U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x60U, 0x10U, + 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x92U, 0x3FU, 0x20U, 0x10U, 0x0CU, 0x68U, 0x10U, 0x0DU, 0xCCU, 0xF4U, 0x0FU, + 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x8AU, 0x3EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x72U, 0x3FU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, + 0xB5U, 0x7AU, 0x3DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x0AU, 0x40U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0x24U, 0xF4U, 0x0FU, + 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xBAU, 0x40U, 0x20U, + 0x15U, 0x42U, 0x43U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xBAU, 0x41U, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xE2U, 0x40U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, + 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, 0x18U, 0x60U, 0x10U, + 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0xE2U, 0x40U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x8AU, 0x41U, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xB2U, 0x42U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xBAU, 0x41U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xB2U, 0x42U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xB2U, 0x42U, 0x20U, + 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xB2U, 0x42U, 0x20U, + 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0xBAU, 0x41U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x92U, 0x42U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, + 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, + 0xB5U, 0xBAU, 0x40U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0xB2U, 0x45U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x3AU, 0x44U, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x6AU, 0x43U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, + 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x4CU, 0x4AU, 0x30U, + 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0x6AU, 0x43U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x44U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x2AU, 0x45U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x3AU, 0x44U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x2AU, 0x45U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, + 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x2AU, 0x45U, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, 0x10U, 0x18U, 0x68U, 0x10U, + 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x2AU, 0x45U, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x46U, 0x44U, 0x00U, + 0xB5U, 0x3AU, 0x44U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x0AU, 0x45U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x42U, 0x43U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xB2U, 0x45U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0x8CU, 0x05U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x03U, 0x10U, 0x04U, 0x14U, 0x02U, + 0x0DU, 0x50U, 0x14U, 0x00U, 0x10U, 0x04U, 0x14U, 0x01U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x00U, 0xCEU, 0x00U, 0x00U, 0x35U, 0xDAU, 0x46U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, + 0x35U, 0x62U, 0x47U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0xEAU, 0x47U, 0x20U, + 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x72U, 0x48U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, + 0x35U, 0xFAU, 0x48U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x82U, 0x49U, 0x20U, + 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x0AU, 0x4AU, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, + 0x35U, 0x92U, 0x4AU, 0x20U, 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x00U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x04U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x08U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x0CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x0CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x10U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x14U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x18U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x18U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x1AU, 0x4BU, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x1CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x1AU, 0x4BU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, + 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0xEAU, 0x4BU, 0x20U, 0x15U, 0xA2U, 0x4DU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x10U, 0x5CU, 0x41U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x48U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x55U, 0x62U, 0x4CU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x62U, 0x4CU, 0x20U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x20U, 0xC8U, 0x01U, 0x00U, 0x35U, 0xE2U, 0x4CU, 0x20U, 0x01U, 0x08U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x08U, 0x44U, 0x24U, 0x00U, 0x10U, 0xDCU, 0x51U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0xE2U, 0x4CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xEAU, 0x4BU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xEAU, 0x4BU, 0x20U, + 0x05U, 0x80U, 0x22U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xEAU, 0x4BU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xEAU, 0x4BU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x4FU, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x10U, 0x1CU, 0x51U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x46U, 0x24U, 0x00U, 0x55U, 0x1AU, 0x4EU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4EU, 0x20U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x20U, 0xC8U, 0x01U, 0x00U, 0x35U, 0x9AU, 0x4EU, 0x20U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, 0x24U, 0x00U, + 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x9AU, 0x4EU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0xA2U, 0x4DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0xA2U, 0x4DU, 0x20U, 0x05U, 0x80U, 0x22U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x0CU, 0xDCU, 0x61U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x08U, 0xC4U, 0x03U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0xA2U, 0x4DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0xA2U, 0x4DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x5AU, 0x4FU, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x4FU, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, + 0x01U, 0x9CU, 0x05U, 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, + 0x08U, 0xCCU, 0x14U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, + 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x2AU, 0x50U, 0x20U, 0x15U, 0x72U, 0x53U, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, + 0x10U, 0xD4U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x41U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, + 0x08U, 0x44U, 0x34U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xBAU, 0x52U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0xCAU, 0x50U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0xCAU, 0x50U, 0x20U, 0x35U, 0xBAU, 0x52U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0xD4U, 0x51U, 0x48U, + 0x10U, 0x5CU, 0x41U, 0x50U, 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, 0x4AU, 0x51U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x4AU, 0x51U, 0x20U, + 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xBAU, 0x52U, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, + 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x91U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x5CU, 0x41U, 0x48U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xBAU, 0x52U, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x02U, 0x52U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x02U, 0x52U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xBAU, 0x52U, 0x20U, 0x01U, 0x08U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x10U, 0xDCU, 0x41U, 0x50U, 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, + 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0xBAU, 0x52U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x2AU, 0x50U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x2AU, 0x50U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, + 0x35U, 0xBAU, 0x52U, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x2AU, 0x50U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x2AU, 0x50U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xBAU, 0x56U, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, + 0x10U, 0x14U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x71U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, + 0x08U, 0x44U, 0x34U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x02U, 0x56U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x12U, 0x54U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x12U, 0x54U, 0x20U, 0x35U, 0x02U, 0x56U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0x14U, 0x51U, 0x48U, + 0x10U, 0x5CU, 0x71U, 0x50U, 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, 0x92U, 0x54U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x92U, 0x54U, 0x20U, + 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0x02U, 0x56U, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, + 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x5CU, 0x91U, 0x48U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0x02U, 0x56U, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x4AU, 0x55U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x4AU, 0x55U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0x02U, 0x56U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x10U, 0xDCU, 0x41U, 0x50U, 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, + 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0x02U, 0x56U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x72U, 0x53U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x72U, 0x53U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, + 0x35U, 0x02U, 0x56U, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x72U, 0x53U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x72U, 0x53U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xBAU, 0x56U, 0x20U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xBAU, 0x56U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, + 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x14U, 0xFEU, 0x8FU, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x00U, 0x08U, 0xC4U, 0x02U, 0x35U, 0x92U, 0x57U, 0x20U, 0x15U, 0x9AU, 0x5AU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, + 0x10U, 0x9CU, 0x40U, 0x48U, 0x08U, 0x44U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xE2U, 0x59U, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x22U, 0x58U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x22U, 0x58U, 0x20U, 0x35U, 0xE2U, 0x59U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x1CU, 0x40U, 0x08U, 0x11U, 0x1CU, 0x78U, 0x00U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x55U, 0x92U, 0x58U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x92U, 0x58U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xE2U, 0x59U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, 0x08U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xE2U, 0x59U, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x3AU, 0x59U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x3AU, 0x59U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xE2U, 0x59U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x08U, 0x48U, 0x10U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xE2U, 0x59U, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x92U, 0x57U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x92U, 0x57U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xE2U, 0x59U, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, + 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x92U, 0x57U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x92U, 0x57U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x7AU, 0x5DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x9CU, 0x40U, 0x48U, + 0x08U, 0x44U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xC2U, 0x5CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x1AU, 0x5BU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x1AU, 0x5BU, 0x20U, 0x35U, 0xC2U, 0x5CU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x0DU, 0x1CU, 0x51U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, 0x55U, 0x82U, 0x5BU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x82U, 0x5BU, 0x20U, + 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xC2U, 0x5CU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x0DU, 0x10U, 0x51U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, 0x08U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xC2U, 0x5CU, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x22U, 0x5CU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x22U, 0x5CU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xC2U, 0x5CU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x0DU, 0x10U, 0x51U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x08U, 0x48U, 0x10U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xC2U, 0x5CU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x9AU, 0x5AU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x9AU, 0x5AU, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0xC2U, 0x5CU, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x9AU, 0x5AU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x9AU, 0x5AU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x5DU, 0x20U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x5DU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0x1AU, 0x5EU, 0x20U, 0x15U, 0x5AU, 0x62U, 0x20U, 0x08U, 0x4AU, 0x84U, 0x0AU, + 0x60U, 0x08U, 0x84U, 0x0AU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xFAU, 0x5FU, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x42U, 0x5EU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, + 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, + 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x42U, 0x5EU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xD2U, 0x5FU, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xD2U, 0x61U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xFAU, 0x5FU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, + 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, + 0x35U, 0xD2U, 0x61U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xD2U, 0x61U, 0x20U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0xD2U, 0x61U, 0x20U, 0x0DU, 0x0CU, 0xF5U, 0x01U, + 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x46U, 0x24U, 0x00U, 0xB5U, 0xFAU, 0x5FU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xB2U, 0x61U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x88U, 0x28U, 0x81U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x1AU, 0x5EU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x92U, 0x66U, 0x20U, + 0x08U, 0x4AU, 0x84U, 0x0AU, 0x60U, 0x08U, 0x84U, 0x0AU, 0x80U, 0x48U, 0x00U, 0x00U, + 0x95U, 0x3AU, 0x64U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x82U, 0x62U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, + 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, + 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x0CU, 0xF5U, 0x01U, + 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x82U, 0x62U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x64U, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x12U, 0x66U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x3AU, 0x64U, 0x20U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, + 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x12U, 0x66U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, + 0x35U, 0x12U, 0x66U, 0x20U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, + 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x12U, 0x66U, 0x20U, + 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x46U, 0x24U, 0x00U, + 0xB5U, 0x3AU, 0x64U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xF2U, 0x65U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x10U, 0x88U, 0x28U, 0x81U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, + 0xB5U, 0x5AU, 0x62U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x92U, 0x66U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, + 0x01U, 0xA0U, 0x05U, 0x03U, 0x01U, 0x90U, 0x05U, 0x04U, 0x01U, 0xB0U, 0x05U, 0x05U, + 0x01U, 0xBCU, 0x05U, 0x06U, 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, + 0x02U, 0x00U, 0xF7U, 0x02U, 0x02U, 0x00U, 0x47U, 0x03U, 0x0DU, 0x1EU, 0x15U, 0x00U, + 0x40U, 0x1CU, 0x14U, 0x00U, 0x20U, 0x1CU, 0x04U, 0x00U, 0x02U, 0x00U, 0x77U, 0x04U, + 0x02U, 0x00U, 0x77U, 0x05U, 0x08U, 0x1EU, 0x15U, 0x00U, 0x26U, 0x00U, 0x44U, 0x00U, + 0x00U, 0x24U, 0xFCU, 0x0FU, 0x00U, 0x10U, 0xF6U, 0x0FU, 0x0CU, 0x64U, 0x42U, 0x00U, + 0x00U, 0x10U, 0xF4U, 0x0FU, 0x0CU, 0x64U, 0x42U, 0x00U, 0x00U, 0x0CU, 0xC4U, 0x02U, + 0x01U, 0x08U, 0x07U, 0x00U, 0x08U, 0x88U, 0x14U, 0x00U, 0x02U, 0x00U, 0x27U, 0x00U, + 0x01U, 0x04U, 0x07U, 0x01U, 0x08U, 0x4AU, 0x44U, 0x05U, 0x60U, 0x08U, 0x44U, 0x05U, + 0x80U, 0x48U, 0x00U, 0x00U, 0x02U, 0x00U, 0x27U, 0x07U, 0x95U, 0x2AU, 0x6AU, 0x20U, + 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0x12U, 0x68U, 0x20U, 0x15U, 0x32U, 0x68U, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xFAU, 0x68U, 0x20U, + 0x55U, 0x9AU, 0x69U, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, 0x00U, + 0x35U, 0x7AU, 0x68U, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0x9AU, 0x68U, 0x20U, + 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0xBAU, 0x68U, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, + 0x35U, 0xDAU, 0x68U, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x55U, 0x9AU, 0x69U, 0x20U, 0x35U, 0x02U, 0x6EU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xFAU, 0x68U, 0x20U, 0x55U, 0x02U, 0x6EU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x9AU, 0x69U, 0x20U, + 0x55U, 0x02U, 0x6EU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x55U, 0xFAU, 0x68U, 0x20U, 0x35U, 0x02U, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xFAU, 0x68U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, + 0x01U, 0x18U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x60U, 0x18U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x68U, 0x08U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0x04U, 0x00U, 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0xFAU, 0x68U, 0x20U, + 0x15U, 0xE2U, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x9AU, 0x69U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x01U, 0x18U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x05U, 0x80U, 0x42U, 0x31U, 0x10U, 0x1CU, 0x60U, 0x10U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x0CU, 0x68U, 0x10U, 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0x9AU, 0x69U, 0x20U, + 0x15U, 0xE2U, 0x6EU, 0x20U, 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0x42U, 0x6AU, 0x20U, + 0x15U, 0x62U, 0x6AU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x35U, 0x2AU, 0x6BU, 0x20U, 0x55U, 0x02U, 0x6CU, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, + 0x08U, 0x1EU, 0x15U, 0x00U, 0x35U, 0xAAU, 0x6AU, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, + 0x35U, 0xCAU, 0x6AU, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0xEAU, 0x6AU, 0x20U, + 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0x0AU, 0x6BU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0x02U, 0x6CU, 0x20U, 0x35U, 0xDAU, 0x6CU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x2AU, 0x6BU, 0x20U, + 0x55U, 0xDAU, 0x6CU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x35U, 0x02U, 0x6CU, 0x20U, 0x55U, 0xDAU, 0x6CU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0x2AU, 0x6BU, 0x20U, 0x35U, 0xDAU, 0x6CU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x2AU, 0x6BU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x10U, 0x1CU, 0x40U, 0x18U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x02U, 0x6FU, 0x20U, 0x10U, 0x1CU, 0x48U, 0x08U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, 0x00U, 0x0CU, 0x04U, 0x00U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0x2AU, 0x6BU, 0x20U, 0x15U, 0xE2U, 0x6EU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x02U, 0x6CU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x00U, 0xDCU, 0x00U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, 0x00U, 0x1CU, 0x01U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x1CU, 0x40U, 0x10U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, 0x10U, 0x0CU, 0x48U, 0x10U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0x02U, 0x6CU, 0x20U, 0x15U, 0xE2U, 0x6EU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xDAU, 0x6CU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x00U, 0x18U, 0x01U, 0x00U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, + 0x10U, 0x18U, 0x48U, 0x08U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x02U, 0x6FU, 0x20U, + 0x10U, 0x0CU, 0x48U, 0x10U, 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0xDAU, 0x6CU, 0x20U, + 0x15U, 0xE2U, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x02U, 0x6EU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x94U, 0x01U, 0x00U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, + 0x10U, 0x5CU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x08U, + 0x10U, 0x1CU, 0x61U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, + 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0x02U, 0x6EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xE2U, 0x6EU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x01U, 0x08U, 0x07U, 0x07U, 0x10U, 0x0CU, 0x20U, 0x01U, + 0x06U, 0x8CU, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x31U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0xD2U, 0x67U, 0x20U, 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0x9AU, 0x6FU, 0x20U, + 0x35U, 0xC2U, 0x6FU, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, + 0x28U, 0x00U, 0x44U, 0x00U, 0x46U, 0x00U, 0x44U, 0x00U, 0x15U, 0x52U, 0x70U, 0x20U, + 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, 0x00U, 0x35U, 0x0AU, 0x70U, 0x20U, + 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0x52U, 0x70U, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, + 0x35U, 0x32U, 0x70U, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0x52U, 0x70U, 0x20U, + 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, 0x28U, 0x00U, 0x44U, 0x00U, + 0x46U, 0x00U, 0x44U, 0x00U, 0x15U, 0x52U, 0x70U, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, + 0x08U, 0xDEU, 0x15U, 0x00U, 0x26U, 0x00U, 0x44U, 0x00U, 0x48U, 0x00U, 0x44U, 0x00U, + 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, 0x20U, 0x1CU, 0x04U, 0x00U, + 0x40U, 0x1CU, 0x14U, 0x00U, 0x02U, 0x00U, 0x77U, 0x04U, 0x01U, 0x08U, 0x07U, 0x00U, + 0x00U, 0x8AU, 0x00U, 0x00U, 0xB5U, 0xB2U, 0x67U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x70U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0xB0U, 0x05U, 0x00U, 0x00U, 0x00U, 0x14U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x44U, 0x00U, 0x27U, 0x04U, 0x84U, 0x01U, 0x01U, + 0x00U, 0x80U, 0x1FU, 0x00U, 0x0CU, 0x00U, 0x10U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x18U, 0x00U, 0x01U, 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, + 0x00U, 0x08U, 0x06U, 0x06U, 0x0CU, 0x1CU, 0x10U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x00U, 0x00U, 0x2EU, 0x00U, 0x00U, 0x04U, 0x6CU, 0x04U, 0x00U, 0x08U, 0xA6U, 0x08U, + 0x00U, 0x0CU, 0xE4U, 0x0CU, 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, + 0x0CU, 0x54U, 0x31U, 0x00U, 0x00U, 0x00U, 0x3EU, 0x01U, 0x00U, 0x04U, 0x7CU, 0x05U, + 0x00U, 0x08U, 0xB6U, 0x09U, 0x00U, 0x0CU, 0xF4U, 0x0DU, 0x0CU, 0x18U, 0x10U, 0x00U, + 0x0CU, 0x98U, 0x21U, 0x00U, 0x0CU, 0x98U, 0x31U, 0x00U, 0x02U, 0x04U, 0x5FU, 0x01U, + 0x02U, 0x04U, 0x6FU, 0x01U, 0x02U, 0x04U, 0x7FU, 0x01U, 0x02U, 0xC0U, 0x55U, 0x00U, + 0x02U, 0xC0U, 0x65U, 0x00U, 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x18U, 0xB4U, 0x00U, 0x02U, 0x04U, 0x6FU, 0x01U, + 0x05U, 0x24U, 0x6FU, 0x02U, 0x00U, 0x04U, 0x04U, 0x02U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x42U, 0x72U, 0x20U, 0x00U, 0x00U, 0xF4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x00U, 0xD4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x92U, 0x72U, 0x20U, + 0x00U, 0x00U, 0xC4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xCAU, 0x72U, 0x20U, 0x00U, 0x00U, 0xE4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x02U, 0x73U, 0x20U, 0x00U, 0x00U, 0xC4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x73U, 0x20U, + 0x00U, 0x00U, 0x24U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x72U, 0x73U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x73U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xE2U, 0x73U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x1AU, 0x74U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x52U, 0x74U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x74U, 0x20U, + 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xC2U, 0x74U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x74U, 0x20U, 0x00U, 0x00U, 0x14U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x32U, 0x75U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x75U, 0x20U, 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xA2U, 0x75U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x75U, 0x20U, + 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x12U, 0x76U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x76U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x82U, 0x76U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x76U, 0x20U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xDAU, 0x76U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x44U, 0x00U, 0x27U, + 0x00U, 0x00U, 0xD4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x02U, 0x04U, 0x4FU, 0x01U, 0x02U, 0xC0U, 0x45U, 0x00U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x77U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xAAU, 0x77U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x77U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x77U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x0AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x78U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x78U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xCAU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x2AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x8AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xEAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x4AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xAAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x0AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x7BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x7BU, 0x20U, + 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x02U, 0x80U, 0x45U, 0x00U, 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, + 0x00U, 0x08U, 0x06U, 0x06U, 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x4AU, 0x7CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, 0x04U, 0x4CU, 0x20U, 0x32U, + 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, + 0x04U, 0x1CU, 0x21U, 0x32U, 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, + 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, 0x02U, 0x04U, 0x3CU, 0x01U, + 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x7DU, 0x20U +}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x28U, 0x00U, 0x10U, 0x24U, 0x08U, 0x01U, 0x10U, 0x24U, 0x90U, 0x02U, 0x10U, 0x24U, 0xCCU, 0x01U, 0x10U, 0x24U, + 0x30U, 0x03U, 0x10U, 0x24U, 0x80U, 0x08U, 0x10U, 0x24U, 0x94U, 0x0AU, 0x10U, 0x24U, 0x08U, 0x0DU, 0x10U, 0x24U, + 0x80U, 0x0FU, 0x10U, 0x24U, 0x34U, 0x12U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x14U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xD2U, 0x01U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0x07U, 0x07U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, + 0x01U, 0x14U, 0x1CU, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, + 0x01U, 0x14U, 0x1CU, 0x08U, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x03U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x06U, 0x18U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x05U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, + 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, + 0x01U, 0x90U, 0x15U, 0xFFU, 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xE2U, 0x04U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, + 0x05U, 0x08U, 0x42U, 0x32U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, + 0x05U, 0x18U, 0x42U, 0x32U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x22U, 0x06U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x06U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, + 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, + 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, + 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, + 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x08U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x0CU, 0x32U, 0x32U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x14U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x10U, 0x86U, 0x0FU, + 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, + 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, + 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x00U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, + 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, + 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x04U, 0x32U, 0x32U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x10U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x05U, 0x18U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, + 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, + 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x00U, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, + 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, + 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, + 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x04U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, + 0x00U, 0x14U, 0xE4U, 0x07U, 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, + 0x10U, 0x94U, 0x50U, 0x24U, 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, + 0x10U, 0x9CU, 0x70U, 0x30U, 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, + 0x00U, 0x14U, 0x84U, 0x0FU, 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, + 0x10U, 0x0CU, 0x48U, 0x13U, 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, + 0x0DU, 0x98U, 0x60U, 0x00U, 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, + 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, + 0x00U, 0x1CU, 0x84U, 0x0FU, 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, + 0x10U, 0x98U, 0x60U, 0x34U, 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, + 0x05U, 0x10U, 0x32U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x00U, 0x10U, 0xF4U, 0x01U, 0x00U, 0x14U, 0xE4U, 0x07U, + 0x00U, 0x18U, 0x84U, 0x0FU, 0x00U, 0x1CU, 0xF4U, 0x01U, 0x0DU, 0x8CU, 0x40U, 0x03U, 0x10U, 0x94U, 0x50U, 0x24U, + 0x10U, 0xCCU, 0x50U, 0x45U, 0x10U, 0x98U, 0x60U, 0x28U, 0x10U, 0xCCU, 0x60U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x30U, + 0x10U, 0xCCU, 0x70U, 0x4BU, 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x10U, 0xE4U, 0x07U, 0x00U, 0x14U, 0x84U, 0x0FU, + 0x00U, 0x18U, 0xF4U, 0x01U, 0x00U, 0x1CU, 0xE4U, 0x07U, 0x10U, 0x90U, 0x40U, 0x34U, 0x10U, 0x0CU, 0x48U, 0x13U, + 0x10U, 0x94U, 0x50U, 0x38U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x10U, 0xCCU, 0x58U, 0x50U, 0x0DU, 0x98U, 0x60U, 0x00U, + 0x10U, 0xCCU, 0x60U, 0x53U, 0x10U, 0x9CU, 0x70U, 0x24U, 0x10U, 0xCCU, 0x70U, 0x55U, 0x05U, 0x18U, 0x32U, 0x32U, + 0x00U, 0x10U, 0x86U, 0x0FU, 0x00U, 0x14U, 0xF4U, 0x01U, 0x00U, 0x18U, 0xE4U, 0x07U, 0x00U, 0x1CU, 0x84U, 0x0FU, + 0x0DU, 0x8CU, 0x40U, 0x48U, 0x10U, 0x94U, 0x50U, 0x30U, 0x10U, 0xCCU, 0x58U, 0x45U, 0x10U, 0x98U, 0x60U, 0x34U, + 0x10U, 0xCCU, 0x68U, 0x43U, 0x10U, 0x9CU, 0x70U, 0x38U, 0x10U, 0xCCU, 0x78U, 0x40U, 0x05U, 0x1CU, 0x32U, 0x32U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xB2U, 0x06U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xC2U, 0x10U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x07U, + 0x00U, 0x18U, 0xFEU, 0x8FU, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x1BU, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, 0x32U, + 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, + 0x05U, 0x04U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, + 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x0DU, 0x88U, 0x60U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xEAU, 0x14U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x07U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x21U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, 0x22U, 0x32U, 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, 0x05U, 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, 0x04U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x11U, 0x88U, 0x21U, 0x20U, 0x11U, 0x0CU, 0x30U, 0x00U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x00U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x00U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xD2U, 0x19U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x00U, 0x18U, 0xFEU, 0x8FU, 0x06U, 0x00U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x07U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x21U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x05U, 0x08U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x05U, 0x10U, 0x32U, 0x32U, 0x05U, 0x14U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x05U, 0x1CU, 0x32U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x04U, 0x22U, 0x32U, 0x05U, 0x08U, 0x32U, 0x32U, 0x05U, 0x0CU, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x10U, 0x22U, 0x32U, 0x05U, 0x14U, 0x32U, 0x32U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x32U, 0x32U, 0x05U, 0x04U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x08U, 0x22U, 0x32U, + 0x05U, 0x0CU, 0x32U, 0x32U, 0x05U, 0x10U, 0x42U, 0x32U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, + 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, + 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x05U, 0x14U, 0x22U, 0x32U, + 0x05U, 0x18U, 0x32U, 0x32U, 0x05U, 0x1CU, 0x42U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xC2U, 0x1EU, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x8CU, 0x05U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x03U, + 0x10U, 0x04U, 0x14U, 0x02U, 0x0DU, 0x50U, 0x14U, 0x00U, 0x10U, 0x04U, 0x14U, 0x01U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x00U, 0xCEU, 0x00U, 0x00U, 0x35U, 0xEAU, 0x1FU, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x72U, 0x20U, 0x20U, + 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0xFAU, 0x20U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x82U, 0x21U, 0x20U, + 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x0AU, 0x22U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x92U, 0x22U, 0x20U, + 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0x1AU, 0x23U, 0x20U, 0x08U, 0xCEU, 0x14U, 0x00U, 0x35U, 0xA2U, 0x23U, 0x20U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x00U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x00U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x04U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x08U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x0CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x10U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x14U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x18U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x1CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, + 0x04U, 0x4CU, 0x20U, 0x32U, 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x04U, 0x1CU, 0x21U, 0x32U, + 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x82U, 0x25U, 0x20U}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x34U, 0x00U, 0x10U, 0x24U, 0x44U, 0x0EU, 0x10U, 0x24U, 0xA0U, 0x01U, 0x10U, 0x24U, + 0x64U, 0x10U, 0x10U, 0x24U, 0x64U, 0x04U, 0x10U, 0x24U, 0x14U, 0x14U, 0x10U, 0x24U, + 0x30U, 0x07U, 0x10U, 0x24U, 0xA0U, 0x08U, 0x10U, 0x24U, 0x70U, 0x0BU, 0x10U, 0x24U, + 0x74U, 0x17U, 0x10U, 0x24U, 0x00U, 0x1CU, 0x10U, 0x24U, 0x08U, 0x21U, 0x10U, 0x24U, + 0x24U, 0x24U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xCAU, 0x00U, 0x20U, + 0x15U, 0xF2U, 0x01U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x00U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x10U, 0x4CU, 0x10U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, + 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0xF2U, 0x00U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x4AU, 0x01U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, + 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xCAU, 0x00U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x03U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, + 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x1AU, 0x02U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, + 0x55U, 0x1AU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x62U, 0x02U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0xF2U, 0x01U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x02U, 0x03U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0xA2U, 0x03U, 0x20U, 0x15U, 0x5AU, 0x06U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xC2U, 0x04U, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xCAU, 0x03U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, + 0x10U, 0x0CU, 0x31U, 0x48U, 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x14U, 0x50U, 0x10U, + 0x11U, 0x1CU, 0x60U, 0x00U, 0x10U, 0x1CU, 0x70U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xF6U, 0x0FU, 0x0DU, 0xCCU, 0x60U, 0x48U, + 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xCAU, 0x03U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x9AU, 0x04U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xDAU, 0x05U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xC2U, 0x04U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0xDAU, 0x05U, 0x20U, 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, + 0x10U, 0x0CU, 0x31U, 0x48U, 0x11U, 0x10U, 0x50U, 0x10U, 0x10U, 0x1CU, 0x31U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xDAU, 0x05U, 0x20U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x10U, 0x14U, 0x50U, 0x10U, 0x11U, 0x1CU, 0x60U, 0x00U, + 0x10U, 0x1CU, 0x70U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0xDAU, 0x05U, 0x20U, 0x00U, 0x0CU, 0xF6U, 0x0FU, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0xC2U, 0x04U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xBAU, 0x05U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xA2U, 0x03U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x08U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x3AU, 0x07U, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x82U, 0x06U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x10U, 0x48U, 0x18U, 0x10U, 0x1CU, 0x51U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x14U, 0x58U, 0x18U, 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x0CU, 0x68U, 0x18U, 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0x82U, 0x06U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x07U, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x12U, 0x08U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x3AU, 0x07U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x12U, 0x08U, 0x20U, 0x10U, 0x10U, 0x48U, 0x18U, 0x10U, 0x1CU, 0x51U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x12U, 0x08U, 0x20U, + 0x10U, 0x14U, 0x58U, 0x18U, 0x10U, 0x5CU, 0x61U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x12U, 0x08U, 0x20U, 0x10U, 0x0CU, 0x68U, 0x18U, + 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x3AU, 0x07U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x07U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, + 0xB5U, 0x5AU, 0x06U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x08U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0x24U, 0xF4U, 0x0FU, + 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x32U, 0x09U, 0x20U, 0x15U, 0xB2U, 0x0BU, 0x20U, + 0x08U, 0x4AU, 0x04U, 0x15U, 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, + 0x95U, 0x32U, 0x0AU, 0x20U, 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x5AU, 0x09U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x4CU, 0x42U, 0x00U, + 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0x5AU, 0x09U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x02U, 0x0AU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x2AU, 0x0BU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x32U, 0x0AU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x2AU, 0x0BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x2AU, 0x0BU, 0x20U, 0x11U, 0x18U, 0x60U, 0x10U, + 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x2AU, 0x0BU, 0x20U, 0x0DU, 0x4CU, 0x42U, 0x00U, + 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0x32U, 0x0AU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x0BU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0xB5U, 0x32U, 0x09U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x22U, 0x0EU, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, + 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xAAU, 0x0CU, 0x20U, + 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xDAU, 0x0BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, + 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, 0x08U, + 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0xDAU, 0x0BU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x7AU, 0x0CU, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x9AU, 0x0DU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xAAU, 0x0CU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x9AU, 0x0DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x9AU, 0x0DU, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, + 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x9AU, 0x0DU, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, + 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0xAAU, 0x0CU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x7AU, 0x0DU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xB2U, 0x0BU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x22U, 0x0EU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0xCAU, 0x0EU, 0x20U, 0x15U, 0xEAU, 0x0FU, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, + 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0xF2U, 0x0EU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x10U, 0x48U, 0x00U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, + 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0xF2U, 0x0EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x42U, 0x0FU, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, + 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xCAU, 0x0EU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x11U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, + 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x12U, 0x10U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x10U, 0x4CU, 0x10U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, + 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0x12U, 0x10U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x62U, 0x10U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, + 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xEAU, 0x0FU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x02U, 0x11U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, + 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xAAU, 0x11U, 0x20U, + 0x15U, 0x12U, 0x14U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xA2U, 0x12U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xD2U, 0x11U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x11U, 0x1CU, 0x40U, 0x00U, 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x58U, 0x00U, 0x10U, 0x1CU, 0x71U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, + 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, + 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xD2U, 0x11U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x7AU, 0x12U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x92U, 0x13U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xC2U, 0x04U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x00U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x92U, 0x13U, 0x20U, 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x58U, 0x00U, + 0x10U, 0x1CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x92U, 0x13U, 0x20U, 0x0DU, 0x54U, 0xF5U, 0x0FU, 0x11U, 0x1CU, 0x68U, 0x00U, + 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, + 0x35U, 0x92U, 0x13U, 0x20U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, 0x08U, 0x46U, 0x34U, 0x00U, + 0xB5U, 0xA2U, 0x12U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x72U, 0x13U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xAAU, 0x11U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x16U, 0x20U, + 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, + 0x95U, 0x22U, 0x15U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x3AU, 0x14U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0x1CU, 0x48U, 0x08U, + 0x10U, 0xDCU, 0x70U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x10U, 0xF5U, 0x0FU, + 0x10U, 0x1CU, 0x68U, 0x18U, 0x10U, 0x1CU, 0x70U, 0x18U, 0x10U, 0xDCU, 0x59U, 0x50U, + 0x10U, 0xDCU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x14U, 0x50U, 0x10U, + 0x10U, 0x1CU, 0x60U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x0CU, 0x68U, 0x10U, 0x0DU, 0xCCU, 0xF4U, 0x0FU, 0x08U, 0x66U, 0x16U, 0x00U, + 0x55U, 0x3AU, 0x14U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x0AU, 0x07U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0x2AU, 0x16U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x22U, 0x15U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0x1CU, 0x48U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x2AU, 0x16U, 0x20U, + 0x0DU, 0x10U, 0xF5U, 0x0FU, 0x10U, 0x1CU, 0x68U, 0x18U, 0x10U, 0x1CU, 0x70U, 0x18U, + 0x10U, 0xDCU, 0x59U, 0x50U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x2AU, 0x16U, 0x20U, 0x10U, 0x14U, 0x50U, 0x10U, + 0x10U, 0x1CU, 0x60U, 0x10U, 0x10U, 0xDCU, 0x59U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x35U, 0x2AU, 0x16U, 0x20U, 0x10U, 0x0CU, 0x68U, 0x10U, + 0x0DU, 0xCCU, 0xF4U, 0x0FU, 0x08U, 0x46U, 0x34U, 0x00U, 0xB5U, 0x22U, 0x15U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x0AU, 0x16U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x12U, 0x14U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x16U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, + 0x00U, 0x24U, 0xF4U, 0x0FU, 0x06U, 0x00U, 0x10U, 0x00U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0x52U, 0x17U, 0x20U, 0x15U, 0xDAU, 0x19U, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, + 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x52U, 0x18U, 0x20U, + 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x7AU, 0x17U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x9CU, 0x91U, 0x30U, 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0x9CU, 0x71U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x22U, 0x16U, 0x00U, + 0x55U, 0x7AU, 0x17U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x22U, 0x18U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0x4AU, 0x19U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x52U, 0x18U, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0x4AU, 0x19U, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x9CU, 0x91U, 0x30U, + 0x10U, 0x5CU, 0x71U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x4AU, 0x19U, 0x20U, 0x11U, 0x18U, 0x60U, 0x10U, 0x11U, 0x1CU, 0x40U, 0x08U, + 0x10U, 0x9CU, 0x71U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0x4AU, 0x19U, 0x20U, 0x0DU, 0x4CU, 0x42U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, + 0xB5U, 0x52U, 0x18U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x2AU, 0x19U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x52U, 0x17U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x4AU, 0x1CU, 0x20U, 0x08U, 0x4AU, 0x04U, 0x15U, + 0x60U, 0x08U, 0x04U, 0x15U, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xD2U, 0x1AU, 0x20U, + 0x00U, 0x20U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x02U, 0x1AU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, + 0x01U, 0x18U, 0x14U, 0xFFU, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x14U, 0x50U, 0x08U, 0x10U, 0x14U, 0x58U, 0x08U, + 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x18U, 0x60U, 0x08U, + 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x4CU, 0x4AU, 0x30U, 0x08U, 0x22U, 0x16U, 0x00U, 0x55U, 0x02U, 0x1AU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xA2U, 0x1AU, 0x20U, + 0x08U, 0x46U, 0x20U, 0x00U, 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0xC2U, 0x1BU, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xD2U, 0x1AU, 0x20U, + 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x01U, 0x18U, 0x14U, 0xFFU, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x35U, 0xC2U, 0x1BU, 0x20U, 0x01U, 0x10U, 0x14U, 0xFFU, 0x10U, 0x14U, 0x50U, 0x08U, + 0x10U, 0x14U, 0x58U, 0x08U, 0x10U, 0x5CU, 0x61U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xC2U, 0x1BU, 0x20U, 0x10U, 0x18U, 0x60U, 0x08U, + 0x10U, 0x18U, 0x68U, 0x10U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x35U, 0xC2U, 0x1BU, 0x20U, 0x10U, 0x4CU, 0x4AU, 0x30U, + 0x08U, 0x46U, 0x44U, 0x00U, 0xB5U, 0xD2U, 0x1AU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xA2U, 0x1BU, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x0CU, 0x28U, 0x02U, 0x08U, 0x88U, 0x30U, 0x00U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0xDAU, 0x19U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x4AU, 0x1CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, + 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, + 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x08U, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x1AU, 0x1DU, 0x20U, + 0x15U, 0xD2U, 0x1EU, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x10U, 0x5CU, 0x41U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x46U, 0x24U, 0x00U, + 0x55U, 0x92U, 0x1DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x92U, 0x1DU, 0x20U, 0x26U, 0x98U, 0x25U, 0x00U, 0x20U, 0xC8U, 0x01U, 0x00U, + 0x35U, 0x12U, 0x1EU, 0x20U, 0x01U, 0x08U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x08U, 0x44U, 0x24U, 0x00U, 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x12U, 0x1EU, 0x20U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x1AU, 0x1DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x1AU, 0x1DU, 0x20U, 0x05U, 0x80U, 0x22U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x1AU, 0x1DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x1AU, 0x1DU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x20U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x10U, 0x1CU, 0x51U, 0x48U, 0x10U, 0x9CU, 0x70U, 0x48U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x55U, 0x4AU, 0x1FU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x4AU, 0x1FU, 0x20U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x20U, 0xC8U, 0x01U, 0x00U, 0x35U, 0xCAU, 0x1FU, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, 0x24U, 0x00U, 0x10U, 0xDCU, 0x51U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0xCAU, 0x1FU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xD2U, 0x1EU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xD2U, 0x1EU, 0x20U, + 0x05U, 0x80U, 0x22U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xD2U, 0x1EU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xD2U, 0x1EU, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x20U, 0x20U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x8AU, 0x20U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, + 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0x5AU, 0x21U, 0x20U, 0x15U, 0xA2U, 0x24U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0xD4U, 0x51U, 0x48U, + 0x10U, 0x5CU, 0x41U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0xEAU, 0x23U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xFAU, 0x21U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xFAU, 0x21U, 0x20U, + 0x35U, 0xEAU, 0x23U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0xD4U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x41U, 0x50U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, 0x7AU, 0x22U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x7AU, 0x22U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xEAU, 0x23U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x10U, 0xDCU, 0x91U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x5CU, 0x41U, 0x48U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xEAU, 0x23U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x32U, 0x23U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x32U, 0x23U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0xEAU, 0x23U, 0x20U, 0x01U, 0x08U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, + 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, + 0x35U, 0xEAU, 0x23U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x5AU, 0x21U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x5AU, 0x21U, 0x20U, + 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0xEAU, 0x23U, 0x20U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x5AU, 0x21U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x5AU, 0x21U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xEAU, 0x27U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0x14U, 0x51U, 0x48U, + 0x10U, 0x5CU, 0x71U, 0x50U, 0x10U, 0x9CU, 0x70U, 0x48U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0x32U, 0x27U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x42U, 0x25U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x42U, 0x25U, 0x20U, + 0x35U, 0x32U, 0x27U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x1CU, 0x18U, 0x01U, 0x10U, 0x14U, 0x51U, 0x48U, 0x10U, 0x5CU, 0x71U, 0x50U, + 0x08U, 0x46U, 0x34U, 0x00U, 0x55U, 0xC2U, 0x25U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xC2U, 0x25U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0x32U, 0x27U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x24U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, + 0x10U, 0xDCU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x5CU, 0x91U, 0x48U, + 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0x32U, 0x27U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x7AU, 0x26U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x7AU, 0x26U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0x32U, 0x27U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x08U, 0x18U, 0x01U, 0x08U, 0x44U, 0x34U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, + 0x10U, 0xDCU, 0x51U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, + 0x35U, 0x32U, 0x27U, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xA2U, 0x24U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xA2U, 0x24U, 0x20U, + 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x15U, 0x00U, 0x35U, 0x32U, 0x27U, 0x20U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xA2U, 0x24U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xA2U, 0x24U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xEAU, 0x27U, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xEAU, 0x27U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0x8CU, 0x05U, 0x03U, + 0x01U, 0xB0U, 0x05U, 0x04U, 0x01U, 0x9CU, 0x05U, 0x05U, 0x02U, 0x00U, 0x17U, 0x00U, + 0x02U, 0x00U, 0x27U, 0x01U, 0x08U, 0xCCU, 0x14U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x14U, 0xFEU, 0x8FU, 0x00U, 0xDEU, 0x01U, 0x00U, 0x00U, 0x08U, 0xC4U, 0x02U, + 0x35U, 0xC2U, 0x28U, 0x20U, 0x15U, 0xCAU, 0x2BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x10U, 0x10U, 0x40U, 0x08U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x9CU, 0x40U, 0x48U, + 0x08U, 0x44U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x12U, 0x2BU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x52U, 0x29U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x52U, 0x29U, 0x20U, 0x35U, 0x12U, 0x2BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x10U, 0x1CU, 0x40U, 0x08U, 0x11U, 0x1CU, 0x78U, 0x00U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x55U, 0xC2U, 0x29U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0xC2U, 0x29U, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x35U, 0x00U, + 0x35U, 0x12U, 0x2BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, + 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, 0x08U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x12U, 0x2BU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x6AU, 0x2AU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x2AU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0x12U, 0x2BU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x10U, 0x40U, 0x08U, + 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x50U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x08U, 0x48U, 0x10U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0x12U, 0x2BU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0xC2U, 0x28U, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0xC2U, 0x28U, 0x20U, 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0x12U, 0x2BU, 0x20U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, + 0x00U, 0x18U, 0x04U, 0x00U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xC2U, 0x28U, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xC2U, 0x28U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xAAU, 0x2EU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0x9CU, 0x40U, 0x48U, 0x08U, 0x44U, 0x44U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0xF2U, 0x2DU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0x4AU, 0x2CU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0x4AU, 0x2CU, 0x20U, + 0x35U, 0xF2U, 0x2DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x0DU, 0x1CU, 0x51U, 0x00U, + 0x08U, 0x46U, 0x44U, 0x00U, 0x55U, 0xB2U, 0x2CU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xB2U, 0x2CU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, + 0x26U, 0x98U, 0x35U, 0x00U, 0x35U, 0xF2U, 0x2DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x0DU, 0x10U, 0x51U, 0x00U, 0x10U, 0xDCU, 0x41U, 0x58U, 0x08U, 0x46U, 0x44U, 0x00U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x48U, 0x08U, 0x06U, 0x98U, 0x45U, 0x00U, + 0x08U, 0x92U, 0xC5U, 0x07U, 0x75U, 0xF2U, 0x2DU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, + 0x55U, 0x52U, 0x2DU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, + 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, + 0x55U, 0x52U, 0x2DU, 0x20U, 0x25U, 0x80U, 0x72U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, + 0x35U, 0xF2U, 0x2DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x0DU, 0x10U, 0x51U, 0x00U, + 0x10U, 0xDCU, 0x41U, 0x50U, 0x08U, 0x46U, 0x44U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x08U, 0x48U, 0x10U, 0x06U, 0x98U, 0x45U, 0x00U, 0x08U, 0x92U, 0xC5U, 0x07U, + 0x75U, 0xF2U, 0x2DU, 0x20U, 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xCAU, 0x2BU, 0x20U, + 0x20U, 0xCEU, 0x00U, 0x00U, 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, + 0x46U, 0x00U, 0x40U, 0x00U, 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xCAU, 0x2BU, 0x20U, + 0x25U, 0x80U, 0x22U, 0x31U, 0x26U, 0x98U, 0x25U, 0x00U, 0x35U, 0xF2U, 0x2DU, 0x20U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x61U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x08U, 0xC4U, 0x03U, 0x08U, 0x98U, 0x15U, 0x00U, 0x00U, 0x18U, 0x04U, 0x00U, + 0x00U, 0x46U, 0x00U, 0x00U, 0x55U, 0xCAU, 0x2BU, 0x20U, 0x20U, 0xCEU, 0x00U, 0x00U, + 0x41U, 0x04U, 0x07U, 0x00U, 0x41U, 0x10U, 0x07U, 0x01U, 0x46U, 0x00U, 0x40U, 0x00U, + 0x48U, 0xCCU, 0x14U, 0x00U, 0x55U, 0xCAU, 0x2BU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xAAU, 0x2EU, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xAAU, 0x2EU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0x4AU, 0x2FU, 0x20U, + 0x15U, 0x8AU, 0x33U, 0x20U, 0x08U, 0x4AU, 0x84U, 0x0AU, 0x60U, 0x08U, 0x84U, 0x0AU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x2AU, 0x31U, 0x20U, 0x00U, 0x24U, 0x54U, 0x01U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x72U, 0x2FU, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, + 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, + 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, + 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x66U, 0x16U, 0x00U, + 0x55U, 0x72U, 0x2FU, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x02U, 0x31U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x15U, 0x02U, 0x33U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x2AU, 0x31U, 0x20U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x02U, 0x33U, 0x20U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, + 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x45U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x10U, 0x18U, 0x01U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x02U, 0x33U, 0x20U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, + 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x10U, 0x18U, 0x01U, + 0x01U, 0x14U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, + 0x35U, 0x02U, 0x33U, 0x20U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, + 0x08U, 0x46U, 0x24U, 0x00U, 0xB5U, 0x2AU, 0x31U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xE2U, 0x32U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x88U, 0x28U, 0x81U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x4AU, 0x2FU, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0xC2U, 0x37U, 0x20U, 0x08U, 0x4AU, 0x84U, 0x0AU, + 0x60U, 0x08U, 0x84U, 0x0AU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0x6AU, 0x35U, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xB2U, 0x33U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, 0x10U, 0xDCU, 0x60U, 0x40U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, + 0x10U, 0x9CU, 0x71U, 0x4BU, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, + 0x05U, 0x80U, 0x72U, 0x31U, 0x0DU, 0x0CU, 0xF5U, 0x01U, 0x10U, 0x0CU, 0x30U, 0x03U, + 0x08U, 0x66U, 0x16U, 0x00U, 0x55U, 0xB2U, 0x33U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x3AU, 0x35U, 0x20U, 0x08U, 0x46U, 0x20U, 0x00U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x15U, 0x42U, 0x37U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x6AU, 0x35U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x1BU, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x4DU, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x55U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x48U, + 0x10U, 0xDCU, 0x60U, 0x40U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, + 0x35U, 0x42U, 0x37U, 0x20U, 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, + 0x0DU, 0x18U, 0xF5U, 0x01U, 0x10U, 0x18U, 0x60U, 0x13U, 0x0DU, 0x1CU, 0x05U, 0x0EU, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x98U, 0x71U, 0x4DU, + 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x98U, 0x71U, 0x40U, 0x01U, 0x14U, 0x18U, 0x01U, + 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, 0x10U, 0x9CU, 0x71U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x42U, 0x37U, 0x20U, + 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x18U, 0x78U, 0x03U, 0x0DU, 0x5CU, 0x75U, 0x00U, + 0x10U, 0x98U, 0x71U, 0x45U, 0x0DU, 0x1CU, 0xF5U, 0x01U, 0x10U, 0x9CU, 0x71U, 0x4BU, + 0x01U, 0x14U, 0x18U, 0x01U, 0x01U, 0x10U, 0x18U, 0x01U, 0x0DU, 0x5CU, 0x85U, 0x0FU, + 0x10U, 0x98U, 0x71U, 0x50U, 0x0DU, 0x1CU, 0x05U, 0x0EU, 0x10U, 0x98U, 0x71U, 0x55U, + 0x0DU, 0x5CU, 0x75U, 0x00U, 0x10U, 0x9CU, 0x71U, 0x5DU, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x46U, 0x24U, 0x00U, 0x35U, 0x42U, 0x37U, 0x20U, 0x0DU, 0x0CU, 0xF5U, 0x01U, + 0x10U, 0x0CU, 0x30U, 0x03U, 0x08U, 0x46U, 0x24U, 0x00U, 0xB5U, 0x6AU, 0x35U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x22U, 0x37U, 0x20U, + 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x10U, 0x88U, 0x28U, 0x81U, + 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x00U, 0x46U, 0x00U, 0x00U, 0xB5U, 0x8AU, 0x33U, 0x20U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xC2U, 0x37U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0x88U, 0x05U, 0x02U, 0x01U, 0xA0U, 0x05U, 0x03U, + 0x01U, 0x90U, 0x05U, 0x04U, 0x01U, 0xB0U, 0x05U, 0x05U, 0x01U, 0xBCU, 0x05U, 0x06U, + 0x02U, 0x00U, 0x17U, 0x00U, 0x02U, 0x00U, 0x27U, 0x01U, 0x02U, 0x00U, 0xF7U, 0x02U, + 0x02U, 0x00U, 0x47U, 0x03U, 0x0DU, 0x1EU, 0x15U, 0x00U, 0x40U, 0x1CU, 0x14U, 0x00U, + 0x20U, 0x1CU, 0x04U, 0x00U, 0x02U, 0x00U, 0x77U, 0x04U, 0x02U, 0x00U, 0x77U, 0x05U, + 0x08U, 0x1EU, 0x15U, 0x00U, 0x26U, 0x00U, 0x44U, 0x00U, 0x00U, 0x24U, 0xFCU, 0x0FU, + 0x00U, 0x10U, 0xF6U, 0x0FU, 0x0CU, 0x64U, 0x42U, 0x00U, 0x00U, 0x10U, 0xF4U, 0x0FU, + 0x0CU, 0x64U, 0x42U, 0x00U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x01U, 0x08U, 0x07U, 0x00U, + 0x08U, 0x88U, 0x14U, 0x00U, 0x02U, 0x00U, 0x27U, 0x00U, 0x01U, 0x04U, 0x07U, 0x01U, + 0x08U, 0x4AU, 0x44U, 0x05U, 0x60U, 0x08U, 0x44U, 0x05U, 0x80U, 0x48U, 0x00U, 0x00U, + 0x02U, 0x00U, 0x27U, 0x07U, 0x95U, 0x5AU, 0x3BU, 0x20U, 0x0DU, 0x1EU, 0x16U, 0x00U, + 0x55U, 0x42U, 0x39U, 0x20U, 0x15U, 0x62U, 0x39U, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x2AU, 0x3AU, 0x20U, 0x55U, 0xCAU, 0x3AU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, 0x00U, 0x35U, 0xAAU, 0x39U, 0x20U, + 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0xCAU, 0x39U, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, + 0x35U, 0xEAU, 0x39U, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0x0AU, 0x3AU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0xCAU, 0x3AU, 0x20U, + 0x35U, 0x32U, 0x3FU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x35U, 0x2AU, 0x3AU, 0x20U, 0x55U, 0x32U, 0x3FU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0xCAU, 0x3AU, 0x20U, 0x55U, 0x32U, 0x3FU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x55U, 0x2AU, 0x3AU, 0x20U, + 0x35U, 0x32U, 0x3FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0x2AU, 0x3AU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x01U, 0x18U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x1CU, 0x60U, 0x18U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x10U, 0x1CU, 0x68U, 0x08U, 0x05U, 0x80U, 0x72U, 0x31U, 0x00U, 0x0CU, 0x04U, 0x00U, + 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0x2AU, 0x3AU, 0x20U, 0x15U, 0x12U, 0x40U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0xCAU, 0x3AU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x02U, 0x01U, 0x18U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x31U, 0x18U, 0x60U, 0x08U, 0x05U, 0x80U, 0x32U, 0x31U, 0x05U, 0x80U, 0x42U, 0x31U, + 0x10U, 0x1CU, 0x60U, 0x10U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, + 0x08U, 0x8AU, 0x44U, 0x00U, 0xB5U, 0xCAU, 0x3AU, 0x20U, 0x15U, 0x12U, 0x40U, 0x20U, + 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0x72U, 0x3BU, 0x20U, 0x15U, 0x92U, 0x3BU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x5AU, 0x3CU, 0x20U, + 0x55U, 0x32U, 0x3DU, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, 0x08U, 0x1EU, 0x15U, 0x00U, + 0x35U, 0xDAU, 0x3BU, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, 0x35U, 0xFAU, 0x3BU, 0x20U, + 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0x1AU, 0x3CU, 0x20U, 0x08U, 0x1EU, 0x45U, 0x00U, + 0x35U, 0x3AU, 0x3CU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x55U, 0x32U, 0x3DU, 0x20U, 0x35U, 0x0AU, 0x3EU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x5AU, 0x3CU, 0x20U, 0x55U, 0x0AU, 0x3EU, 0x20U, + 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, 0x35U, 0x32U, 0x3DU, 0x20U, + 0x55U, 0x0AU, 0x3EU, 0x20U, 0x01U, 0x10U, 0x07U, 0x04U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x55U, 0x5AU, 0x3CU, 0x20U, 0x35U, 0x0AU, 0x3EU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x5AU, 0x3CU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x32U, 0x40U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x1CU, 0x40U, 0x18U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x32U, 0x40U, 0x20U, + 0x10U, 0x1CU, 0x48U, 0x08U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x32U, 0x40U, 0x20U, 0x00U, 0x0CU, 0x04U, 0x00U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0xB5U, 0x5AU, 0x3CU, 0x20U, 0x15U, 0x12U, 0x40U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x32U, 0x3DU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x00U, 0xDCU, 0x00U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x32U, 0x40U, 0x20U, 0x00U, 0x1CU, 0x01U, 0x00U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x32U, 0x40U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x02U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x10U, 0x1CU, 0x40U, 0x10U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x32U, 0x40U, 0x20U, 0x10U, 0x0CU, 0x48U, 0x10U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0xB5U, 0x32U, 0x3DU, 0x20U, 0x15U, 0x12U, 0x40U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x0AU, 0x3EU, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x08U, 0x8AU, 0x14U, 0x00U, + 0x35U, 0x32U, 0x40U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, 0x00U, 0x18U, 0x01U, 0x00U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x58U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x32U, 0x40U, 0x20U, 0x10U, 0x18U, 0x48U, 0x08U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x10U, 0x9CU, 0x41U, 0x50U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0x35U, 0x32U, 0x40U, 0x20U, 0x10U, 0x0CU, 0x48U, 0x10U, + 0x08U, 0x8AU, 0x14U, 0x00U, 0xB5U, 0x0AU, 0x3EU, 0x20U, 0x15U, 0x12U, 0x40U, 0x20U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, 0x75U, 0x32U, 0x3FU, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, 0x00U, 0xFEU, 0x03U, 0x00U, + 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, 0x31U, 0x10U, 0x40U, 0x08U, + 0x31U, 0x18U, 0x60U, 0x08U, 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, + 0x00U, 0x94U, 0x01U, 0x00U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x18U, 0x1CU, 0x01U, + 0x00U, 0xFEU, 0x03U, 0x00U, 0x0DU, 0x10U, 0x91U, 0x00U, 0x0DU, 0x98U, 0x91U, 0x00U, + 0x31U, 0x10U, 0x40U, 0x08U, 0x31U, 0x18U, 0x60U, 0x08U, 0x10U, 0x5CU, 0x41U, 0x58U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x08U, 0x10U, 0x1CU, 0x61U, 0x50U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x68U, 0x10U, 0x08U, 0x8AU, 0x44U, 0x00U, + 0xB5U, 0x32U, 0x3FU, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x12U, 0x40U, 0x20U, 0x05U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, + 0x01U, 0x08U, 0x07U, 0x07U, 0x10U, 0x0CU, 0x20U, 0x01U, 0x06U, 0x8CU, 0x30U, 0x00U, + 0x0CU, 0xDCU, 0x31U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, + 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, + 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0x02U, 0x39U, 0x20U, + 0x0DU, 0x1EU, 0x16U, 0x00U, 0x55U, 0xCAU, 0x40U, 0x20U, 0x35U, 0xF2U, 0x40U, 0x20U, + 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, 0x28U, 0x00U, 0x44U, 0x00U, + 0x46U, 0x00U, 0x44U, 0x00U, 0x15U, 0x82U, 0x41U, 0x20U, 0x01U, 0x10U, 0x07U, 0x03U, + 0x08U, 0x1EU, 0x15U, 0x00U, 0x35U, 0x3AU, 0x41U, 0x20U, 0x08U, 0x1EU, 0x25U, 0x00U, + 0x35U, 0x82U, 0x41U, 0x20U, 0x08U, 0x1EU, 0x35U, 0x00U, 0x35U, 0x62U, 0x41U, 0x20U, + 0x08U, 0x1EU, 0x45U, 0x00U, 0x35U, 0x82U, 0x41U, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, + 0x08U, 0xDEU, 0x15U, 0x00U, 0x28U, 0x00U, 0x44U, 0x00U, 0x46U, 0x00U, 0x44U, 0x00U, + 0x15U, 0x82U, 0x41U, 0x20U, 0x01U, 0x1CU, 0x07U, 0x04U, 0x08U, 0xDEU, 0x15U, 0x00U, + 0x26U, 0x00U, 0x44U, 0x00U, 0x48U, 0x00U, 0x44U, 0x00U, 0x01U, 0x1CU, 0x07U, 0x04U, + 0x08U, 0xDEU, 0x15U, 0x00U, 0x20U, 0x1CU, 0x04U, 0x00U, 0x40U, 0x1CU, 0x14U, 0x00U, + 0x02U, 0x00U, 0x77U, 0x04U, 0x01U, 0x08U, 0x07U, 0x00U, 0x00U, 0x8AU, 0x00U, 0x00U, + 0xB5U, 0xE2U, 0x38U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xD2U, 0x41U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0xB0U, 0x05U, 0x00U, 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x44U, 0x00U, 0x27U, 0x04U, 0x84U, 0x01U, 0x01U, 0x00U, 0x80U, 0x1FU, 0x00U, + 0x0CU, 0x00U, 0x10U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x18U, 0x00U, 0x01U, + 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, 0x00U, 0x08U, 0x06U, 0x06U, + 0x0CU, 0x1CU, 0x10U, 0x00U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x00U, 0x00U, 0x2EU, 0x00U, + 0x00U, 0x04U, 0x6CU, 0x04U, 0x00U, 0x08U, 0xA6U, 0x08U, 0x00U, 0x0CU, 0xE4U, 0x0CU, + 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, 0x0CU, 0x54U, 0x31U, 0x00U, + 0x00U, 0x00U, 0x3EU, 0x01U, 0x00U, 0x04U, 0x7CU, 0x05U, 0x00U, 0x08U, 0xB6U, 0x09U, + 0x00U, 0x0CU, 0xF4U, 0x0DU, 0x0CU, 0x18U, 0x10U, 0x00U, 0x0CU, 0x98U, 0x21U, 0x00U, + 0x0CU, 0x98U, 0x31U, 0x00U, 0x02U, 0x04U, 0x5FU, 0x01U, 0x02U, 0x04U, 0x6FU, 0x01U, + 0x02U, 0x04U, 0x7FU, 0x01U, 0x02U, 0xC0U, 0x55U, 0x00U, 0x02U, 0xC0U, 0x65U, 0x00U, + 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x18U, 0xB4U, 0x00U, 0x02U, 0x04U, 0x6FU, 0x01U, 0x05U, 0x24U, 0x6FU, 0x02U, + 0x00U, 0x04U, 0x04U, 0x02U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x72U, 0x43U, 0x20U, 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x00U, 0xD4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xC2U, 0x43U, 0x20U, 0x00U, 0x00U, 0xC4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x43U, 0x20U, + 0x00U, 0x00U, 0xE4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x32U, 0x44U, 0x20U, 0x00U, 0x00U, 0xC4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x44U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xA2U, 0x44U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xDAU, 0x44U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x12U, 0x45U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x45U, 0x20U, + 0x00U, 0x00U, 0x24U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x82U, 0x45U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x45U, 0x20U, 0x00U, 0x00U, 0x14U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xF2U, 0x45U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x2AU, 0x46U, 0x20U, 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x62U, 0x46U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x46U, 0x20U, + 0x00U, 0x00U, 0x14U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xD2U, 0x46U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x47U, 0x20U, 0x00U, 0x00U, 0x14U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x42U, 0x47U, 0x20U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x7AU, 0x47U, 0x20U, 0x00U, 0x00U, 0x24U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, + 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xB2U, 0x47U, 0x20U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x00U, 0x04U, 0x24U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x47U, 0x20U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x0AU, 0x48U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0xB0U, 0x05U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x44U, 0x00U, 0x27U, 0x00U, 0x00U, 0xD4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x02U, 0x04U, 0x4FU, 0x01U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x48U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x48U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xFAU, 0x48U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x5AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x1AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x5AU, 0x4AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x7AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xDAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x3AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x5AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x9AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xFAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x5AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4CU, 0x20U, 0x00U, 0x00U, 0xF4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x02U, 0x80U, 0x45U, 0x00U, + 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, 0x00U, 0x08U, 0x06U, 0x06U, + 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, 0x02U, 0xC0U, 0x45U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x4DU, 0x20U +}; +#endif +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SDMA_IRQHandler(void); +void SDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/drivers/smartdma/fsl_smartdma_rt500.h b/drivers/smartdma/fsl_smartdma_rt500.h new file mode 100644 index 000000000..fe2c47f8b --- /dev/null +++ b/drivers/smartdma/fsl_smartdma_rt500.h @@ -0,0 +1,321 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_RT500_H_ +#define FSL_SMARTDMA_RT500_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_rt500 RT500 SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SMARTDMA_DISPLAY_MIPI_AND_FLEXIO 0 +#define SMARTDMA_DISPLAY_MIPI_ONLY 1 +#define SMARTDMA_DISPLAY_FLEXIO_ONLY 2 + +/* Select firmware for MIPI and FLEXIO by default. */ +#ifndef SMARTDMA_DISPLAY_FIRMWARE_SELECT +#define SMARTDMA_DISPLAY_FIRMWARE_SELECT SMARTDMA_DISPLAY_MIPI_AND_FLEXIO +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x24100000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to + FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; +#endif + +/*! + * @brief Parameter for FlexIO MCULCD except kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_onelane_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t offset; + uint32_t *smartdma_stack; +} smartdma_flexio_onelane_mculcd_param_t; + +/*! + * @brief Parameter for MIPI DSI + */ +typedef struct _smartdma_dsi_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! Buffer size in byte. */ + uint32_t buffersize; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB565_DMA2D, kSMARTDMA_MIPI_RGB888_DMA2D + * and kSMARTDMA_MIPI_XRGB2RGB_DMA2D. + */ +typedef struct _smartdma_dsi_2d_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! SRC data transfer in a minor loop */ + uint32_t minorLoop; + /*! SRC data offset added after a minor loop */ + uint32_t minorLoopOffset; + /*! SRC data transfer in a major loop */ + uint32_t majorLoop; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_2d_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA + */ +typedef struct _smartdma_dsi_checkerboard_param +{ + /*! Pointer to the buffer to send, pixel format is ARGB8888. */ + const uint8_t *p_buffer; + uint32_t height; /*! Height resolution in pixel. */ + uint32_t width; /*! Width resolution in pixel. */ + /*! Cube block type. + * cbType=1 : 1/2 pixel mask cases + * cbType=2 : 1/4 pixel mask cases + */ + uint32_t cbType; + /*! which pixel is turned off in each type + * cbType=2: indexOff= 1,2,3,4 + * cbType=1: indexOff= 0,1 + */ + uint32_t indexOff; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * for example + * format is RGB888: + * LSB MSB + * B0 B1 B2 B3 B4 B5 B6 B7 | G0 G1 G2 G3 G4 G5 G6 G7 | R0 R1 R2 R3 R4 R5 R6 R7 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * R0 R1 R2 R3 R4 R5 R6 R7 | G0 G1 G2 G3 G4 G5 G6 G7 | B0 B1 B2 B3 B4 B5 B6 B7 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_checkerboard_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + /*! Parameter for flexio MCULCD. */ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; + /*! Parameter for flexio MCULCD with one shift buffer. */ + smartdma_flexio_onelane_mculcd_param_t flexioOneLineMcuLcdParam; + /*! Parameter for MIPI DSI functions. */ + smartdma_dsi_param_t dsiParam; + /*! Parameter for MIPI DSI 2D functions. */ + smartdma_dsi_2d_param_t dsi2DParam; + /*! Parameter for MIPI DSI checker board functions. */ + smartdma_dsi_checkerboard_param_t dsiCheckerBoardParam; + /*! Parameter for RGB565_RGB888 convertion. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; +} smartdma_param_t; + +typedef struct +{ + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /* 0x20 */ + __IO uint32_t CTRL; /* 0x24 */ + __I uint32_t PC; /* 0x28 */ + __I uint32_t SP; /* 0x2C */ + __IO uint32_t BREAK_ADDR; /* 0x30 */ + __IO uint32_t BREAK_VECT; /* 0x34 */ + __IO uint32_t EMER_VECT; /* 0x38 */ + __IO uint32_t EMER_SEL; /* 0x3C */ + __IO uint32_t ARM2EZH; /* 0x40 */ + __IO uint32_t EZH2ARM; /* 0x44 */ + __IO uint32_t PENDTRAP; /* 0x48 */ +} SMARTDMA_Type; + +#define SMARTDMA_BASE 0x40027000 +#define SMARTDMA ((volatile SMARTDMA_Type *)SMARTDMA_BASE) + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_RT500_H_ */ diff --git a/drivers/syspm/fsl_syspm.c b/drivers/syspm/fsl_syspm.c new file mode 100644 index 000000000..2fecd525b --- /dev/null +++ b/drivers/syspm/fsl_syspm.c @@ -0,0 +1,215 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_syspm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.syspm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +/*! + * @brief Get instance number for ESYSPM. + * + * @param base ESYSPM peripheral base address. + */ +static uint32_t SYSPM_GetInstance(SYSPM_Type *base); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +/*! @brief Array to map SYSPM instance number to base pointer. */ +static SYSPM_Type *const s_syspmBases[] = SYSPM_BASE_PTRS; + +/*! @brief Array to map SYSPM instance number to clock name. */ +static const clock_ip_name_t s_syspmClockName[] = SYSPM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +static uint32_t SYSPM_GetInstance(SYSPM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_syspmBases); instance++) + { + if (s_syspmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_syspmBases)); + + return instance; +} +#endif + +/* + * brief Initializes the SYSPM + * + * This function enables the SYSPM clock. + * + * param base SYSPM peripheral base address. + */ +void SYSPM_Init(SYSPM_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) + CLOCK_EnableClock(s_syspmClockName[SYSPM_GetInstance(base)]); +#endif +} + +/* + * brief Deinitializes the SYSPM + * + * This function disables the SYSPM clock. + * + * param base SYSPM peripheral base address. + */ +void SYSPM_Deinit(SYSPM_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) + CLOCK_DisableClock(s_syspmClockName[SYSPM_GetInstance(base)]); +#endif +} + +/*! + * @brief Select event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @param eventCode select which event to be counted in PMECTRx., see to table Events. + */ +void SYSPM_SelectEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event, uint8_t eventCode) +{ + uint32_t pmcr; + uint8_t shift; + + shift = 7U * (uint8_t)event; + + pmcr = base->PMCR[(uint8_t)monitor].PMCR; + pmcr &= ~(SYSPM_PMCR_SELEVT1_MASK << shift); + pmcr |= SYSPM_PMCR_SELEVT1(eventCode) << shift; + + base->PMCR[(uint8_t)monitor].PMCR = pmcr; +} + +/*! + * @brief Reset event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event) +{ + base->PMCR[(uint8_t)monitor].PMCR |= ((uint32_t)SYSPM_PMCR_RECTR1_MASK << (uint8_t)event); +} + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_RICTR) && (FSL_FEATURE_SYSPM_HAS_PMCR_RICTR == 0U))) +/*! + * @brief Reset Instruction Counter + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetInstructionEvent(SYSPM_Type *base, syspm_monitor_t monitor) +{ + base->PMCR[(uint8_t)monitor].PMCR |= SYSPM_PMCR_RICTR_MASK; +} +#endif /* FSL_FEATURE_SYSPM_HAS_PMCR_RICTR */ + +/*! + * @brief Set count mode + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param mode syspm select counter mode, see to #syspm_mode_t. + */ +void SYSPM_SetCountMode(SYSPM_Type *base, syspm_monitor_t monitor, syspm_mode_t mode) +{ + base->PMCR[(uint8_t)monitor].PMCR = + (base->PMCR[(uint8_t)monitor].PMCR & ~SYSPM_PMCR_CMODE_MASK) | SYSPM_PMCR_CMODE(mode); +} + +/*! + * @brief Set Start/Stop Control + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param ssc This 3-bit field provides a three-phase mechanism to start/stop the counters. It includes a + * prioritized scheme with local start > local stop > global start > global stop > conditional + * TSTART > TSTOP. The global and conditional start/stop affect all configured PM/PSAM module concurrently so counters + * are "coherent". see to #syspm_startstop_control_t + */ +void SYSPM_SetStartStopControl(SYSPM_Type *base, syspm_monitor_t monitor, syspm_startstop_control_t ssc) +{ + base->PMCR[(uint8_t)monitor].PMCR = + (base->PMCR[(uint8_t)monitor].PMCR & ~SYSPM_PMCR_SSC_MASK) | SYSPM_PMCR_SSC(ssc); +} + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH)) && (FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH == 0U)) +/*! + * @brief Disable Counters if Stopped or Halted + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_DisableCounter(SYSPM_Type *base, syspm_monitor_t monitor) +{ + base->PMCR[(uint8_t)monitor].PMCR |= SYSPM_PMCR_DCIFSH_MASK; +} +#endif /* FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH */ + +/*! + * @brief This is the the 40-bits of eventx counter. + The value in this register increments each time the event + selected in PMCRx[SELEVTx] occurs. + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @return get the the 40 bits of eventx counter. + */ +uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event) +{ + uint32_t highOld; + uint32_t high; + uint32_t low; + + highOld = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].HI; + while (true) + { + low = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].LO; + high = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].HI; + if (high == highOld) + { + break; + } + else + { + highOld = high; + } + } + + return ((uint64_t)high << 32U) + low; +} diff --git a/drivers/syspm/fsl_syspm.h b/drivers/syspm/fsl_syspm.h new file mode 100644 index 000000000..397b1f9ae --- /dev/null +++ b/drivers/syspm/fsl_syspm.h @@ -0,0 +1,165 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SYSPM_H_ +#define FSL_SYSPM_H_ + +#include "fsl_common.h" + +/*! @addtogroup syspm */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SYSPM driver version */ +#define FSL_SYSPM_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) + +/*@}*/ +/*! @brief syspm select control monitor */ +typedef enum _syspm_monitor +{ + kSYSPM_Monitor0 = 0U, /*!< Monitor 0 */ +#if (SYSPM_PMCR_COUNT > 1U) + kSYSPM_Monitor1 = 1U, /*!< Monitor 1 */ +#endif +} syspm_monitor_t; + +/*! @brief syspm select event */ +typedef enum _syspm_event +{ + kSYSPM_Event1 = 0U, /*!< Event 1 */ + kSYSPM_Event2 = 1U, /*!< Event 2 */ + kSYSPM_Event3 = 2U, /*!< Event 3 */ +} syspm_event_t; + +/*! @brief syspm set count mode */ +typedef enum _syspm_mode +{ + kSYSPM_BothMode = 0x00, /*!< count in both modes */ + kSYSPM_UserMode = 0x02, /*!< count only in user mode */ + kSYSPM_PrivilegedMode = 0x03, /*!< count only in privileged mode */ +} syspm_mode_t; + +/*! @brief syspm start/stop control */ +typedef enum _syspm_startstop_control +{ + kSYSPM_Idle = 0x00, /*!< idle >*/ + kSYSPM_LocalStop = 0x01, /*!< local stop */ + kSYSPM_LocalStart = 0x02, /*!< local start */ + KSYSPM_EnableTraceControl = 0x04, /*!< enable global TSTART/TSTOP */ + kSYSPM_GlobalStart = 0x05, /*!< global stop */ + kSYSPM_GlobalStop = 0x06, /*!< global start */ +} syspm_startstop_control_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @brief Initializes the SYSPM + * + * This function enables the SYSPM clock. + * + * @param base SYSPM peripheral base address. + */ +void SYSPM_Init(SYSPM_Type *base); + +/*! + * @brief Deinitializes the SYSPM + * + * This function disables the SYSPM clock. + * + * @param base SYSPM peripheral base address. + */ +void SYSPM_Deinit(SYSPM_Type *base); + +/*! + * @brief Select event counters + * + * @param base SYSPM peripheral base address. + * @param event syspm select event, see to #syspm_event_t. + * @param eventCode select which event to be counted in PMECTRx., see to table Events. + */ +void SYSPM_SelectEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event, uint8_t eventCode); + +/*! + * @brief Reset event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event); + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_RICTR) && (FSL_FEATURE_SYSPM_HAS_PMCR_RICTR == 0U))) +/*! + * @brief Reset Instruction Counter + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetInstructionEvent(SYSPM_Type *base, syspm_monitor_t monitor); +#endif + +/*! + * @brief Set count mode + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param mode syspm select counter mode, see to #syspm_mode_t. + */ +void SYSPM_SetCountMode(SYSPM_Type *base, syspm_monitor_t monitor, syspm_mode_t mode); + +/*! + * @brief Set Start/Stop Control + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param ssc This 3-bit field provides a three-phase mechanism to start/stop the counters. It includes a + * prioritized scheme with local start > local stop > global start > global stop > conditional + * TSTART > TSTOP. The global and conditional start/stop affect all configured PM/PSAM module concurrently so counters + * are "coherent". see to #syspm_startstop_control_t + */ +void SYSPM_SetStartStopControl(SYSPM_Type *base, syspm_monitor_t monitor, syspm_startstop_control_t ssc); + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH)) && (FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH == 0U)) +/*! + * @brief Disable Counters if Stopped or Halted + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_DisableCounter(SYSPM_Type *base, syspm_monitor_t monitor); +#endif + +/*! + * @brief This is the the 40-bits of eventx counter. + The value in this register increments each time the event + selected in PMCRx[SELEVTx] occurs. + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @return get the the 40 bits of eventx counter. + */ +uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* FSL_SYSPM_H_*/ diff --git a/drivers/tdet/fsl_tdet.c b/drivers/tdet/fsl_tdet.c new file mode 100644 index 000000000..4caa262a5 --- /dev/null +++ b/drivers/tdet/fsl_tdet.c @@ -0,0 +1,656 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tdet.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tdet" +#endif + +/* all bits defined in the LOCK Register. */ +#define TDET_ALL_LC_MASK 0x00FF3FF0u + +/* all bits defined in the Interrupt Enable Register. */ +#define TDET_ALL_IER_MASK 0x00FF03FDu + +/* all bits defined in the Tamper Enable Register. */ +#define TDET_ALL_TER_MASK 0x00FF0FFCu + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * Weak implementation of TDET IRQ, should be re-defined by user when using TDET IRQ + */ +__WEAK void VBAT0_DriverIRQHandler(void) +{ + /* TDET generates IRQ until corresponding bit in STATUS is cleared by calling + * TDET_ClearStatusFlags(TDET0,kTDET_StatusAll); + * which clear all bits or kTDET_StatusXXX to clear only one bit + */ +} + +static bool tdet_IsRegisterWriteAllowed(DIGTMP_Type *base, uint32_t mask) +{ + bool retval; + + retval = false; + mask = mask & TDET_ALL_LC_MASK; + + /* specified LR bit(s) must be set */ + if (mask == (mask & base->LR)) + { + retval = true; + } + return retval; +} + +static status_t tdet_PinConfigure(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pin) +{ + uint32_t temp; + uint32_t mask; + status_t status; + + if ((tdet_IsRegisterWriteAllowed( + base, DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | (((uint32_t)1u << DIGTMP_LR_GFL0_SHIFT) << pin))) && + (pinConfig != NULL)) + { + /* pin 0 to 7 selects bit0 to bit7 */ + mask = ((uint32_t)1u << pin); + + /* Pin Direction Register */ + temp = base->PDR; + temp &= ~mask; /* clear the bit */ + if (kTDET_TamperPinDirectionOut == pinConfig->pinDirection) + { + temp |= mask; /* set the bit, if configured */ + } + base->PDR = temp; + + /* Pin Polarity Register */ + temp = base->PPR; + temp &= ~mask; /* clear the bit */ + if (kTDET_TamperPinPolarityExpectInverted == pinConfig->pinPolarity) + { + temp |= mask; /* set the bit, if configured */ + } + base->PPR = temp; + + /* compute and set the configured value to the glitch filter register */ + temp = 0; + temp |= DIGTMP_PGFR_GFW(pinConfig->glitchFilterWidth); + temp |= DIGTMP_PGFR_GFP(pinConfig->glitchFilterPrescaler); + temp |= DIGTMP_PGFR_TPSW(pinConfig->tamperPinSampleWidth); + temp |= DIGTMP_PGFR_TPSF(pinConfig->tamperPinSampleFrequency); + temp |= DIGTMP_PGFR_TPEX(pinConfig->tamperPinExpected); + temp |= DIGTMP_PGFR_TPE(pinConfig->tamperPullEnable); + temp |= DIGTMP_PGFR_TPS(pinConfig->tamperPullSelect); + /* make sure the glitch filter is disabled when we configure glitch filter width */ + base->PGFR[pin] = temp; + /* add glitch filter enabled */ + if (pinConfig->glitchFilterEnable) + { + temp |= DIGTMP_PGFR_GFE(1u); + base->PGFR[pin] = temp; + } + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +static status_t tdet_ActiveTamperConfigure(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegister) +{ + uint32_t temp; + status_t status; + + /* check if writing to active tamper register is allowed */ + if ((tdet_IsRegisterWriteAllowed(base, ((uint32_t)1u << DIGTMP_LR_ATL0_SHIFT) << activeTamperRegister)) && + (activeTamperConfig != NULL)) + { + /* compute and set the configured value to the active tamper register */ + temp = 0; + temp |= DIGTMP_ATR_ATSR(activeTamperConfig->activeTamperShift); + temp |= DIGTMP_ATR_ATP(activeTamperConfig->activeTamperPolynomial); + base->ATR[activeTamperRegister] = temp; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Initialize TDET + * + * This function initializes TDET. + * + * param base TDET peripheral base address + * return Status of the init operation + */ +status_t TDET_Init(DIGTMP_Type *base) +{ + return kStatus_Success; +} + +/*! + * brief Deinitialize TDET + * + * This function disables glitch filters and active tampers + * This function disables the TDET clock and prescaler in TDET Control Register. + * param base TDET peripheral base address + */ +void TDET_Deinit(DIGTMP_Type *base) +{ + uint32_t i, j, k; + j = ARRAY_SIZE(base->PGFR); + k = ARRAY_SIZE(base->ATR); + /* disable all glitch filters and active tampers */ + for (i = 0; i < j; i++) + { + base->PGFR[i] = 0; + } + for (i = 0; i < k; i++) + { + base->ATR[i] = 0; + } + + /* disable inner TDET clock and prescaler */ + base->CR &= ~DIGTMP_CR_DEN_MASK; +} + +/*! + * brief Gets default values for the TDET Control Register. + * + * This function fills the given structure with default values for the TDET Control Register. + * The default values are: + * code + * defaultConfig->innerClockAndPrescalerEnable = true + * defaultConfig->tamperForceSystemResetEnable = false + * defaultConfig->updateMode = kTDET_StatusLockWithTamper + * defaultConfig->clockSourceActiveTamper0 = kTDET_ClockType1Hz + * defaultConfig->clockSourceActiveTamper1 = kTDET_ClockType1Hz + * defaultConfig->disablePrescalerAfterTamper = false + * defaultConfig->prescaler = 0 + * endcode + * param base TDET peripheral base address + * param[out] defaultConfig Pointer to structure to be filled with default parameters + */ +void TDET_GetDefaultConfig(DIGTMP_Type *base, tdet_config_t *defaultConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(defaultConfig, 0, sizeof(*defaultConfig)); + + struct _tdet_config myDefaultConfig = { + true, /* innerClockAndPrescalerEnable */ + false, /* tamperForceSystemResetEnable */ + kTDET_StatusLockWithTamper, /* updateMode */ + kTDET_ClockType1Hz, /* clockSourceActiveTamper0 */ + kTDET_ClockType1Hz, /* clockSourceActiveTamper1 */ + false, /* disable prescaler on tamper event */ + 0, /* prescaler */ + }; + + *defaultConfig = myDefaultConfig; +} + +/*! + * brief Writes to the TDET Control Register. + * + * This function writes the given structure to the TDET Control Register. + * param base TDET peripheral base address + * param config Pointer to structure with TDET peripheral configuration parameters + * return kStatus_Fail when writing to TDET Control Register is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_SetConfig(DIGTMP_Type *base, const tdet_config_t *config) +{ + uint32_t tmpCR; + + status_t retval = kStatus_Fail; + + /* check if writing to CR is allowed */ + if ((tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_CRL_MASK)) && (config != NULL)) + { + /* compute CR value */ + tmpCR = 0; + tmpCR |= DIGTMP_CR_TFSR(config->tamperForceSystemResetEnable); + tmpCR |= DIGTMP_CR_UM(config->updateMode); + tmpCR |= DIGTMP_CR_ATCS0(config->clockSourceActiveTamper0); + tmpCR |= DIGTMP_CR_ATCS1(config->clockSourceActiveTamper1); + tmpCR |= DIGTMP_CR_DISTAM(config->disablePrescalerAfterTamper); + tmpCR |= DIGTMP_CR_DPR(config->prescaler); + /* write the computed value to the CR register */ + base->CR = tmpCR; + /* after the prescaler is written to CR register, enable the inner TDET clock and prescaler */ + if (config->innerClockAndPrescalerEnable) + { + base->CR = tmpCR | DIGTMP_CR_DEN_MASK; + } + retval = kStatus_Success; + } + else + { + retval = kStatus_Fail; + } + + return retval; +} + +/*! + * brief Software reset. + * + * This function resets all TDET registers. The CR[SWR] itself is not affected; + * it is reset by VBAT POR only. + * + * param base TDET peripheral base address + * return kStatus_Fail when writing to TDET Control Register is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_SoftwareReset(DIGTMP_Type *base) +{ + status_t retval = kStatus_Fail; + + /* check if writing to CR is allowed */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_CRL_MASK)) + { + /* set the CR[SWR] */ + base->CR = DIGTMP_CR_SWR_MASK; + retval = kStatus_Success; + } + else + { + retval = kStatus_Fail; + } + + return retval; +} + +/*! + * brief Writes to the active tamper register(s). + * + * This function writes per active tamper register parameters to active tamper register(s). + * + * param base TDET peripheral base address + * param activeTamperConfig Pointer to structure with active tamper register parameters + * param activeTamperRegisterSelect Bit mask for active tamper registers to be configured. The passed value is + * combination of tdet_active_tamper_register_t values (OR'ed). + * return kStatus_Fail when writing to TDET Active Tamper Register(s) is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_ActiveTamperSetConfig(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegisterSelect) +{ + uint32_t mask; + status_t status; + uint32_t i, j; + + mask = 1u; + status = kStatus_Success; + j = ARRAY_SIZE(base->ATR); + /* configure active tamper register by active tamper register, by moving through all active tamper registers */ + for (i = 0; i < j; i++) + { + if ((activeTamperRegisterSelect & mask) != 0U) + { + /* configure this active tamper register */ + status = tdet_ActiveTamperConfigure(base, activeTamperConfig, i); + if (status != kStatus_Success) + { + break; + } + } + mask = mask << 1u; + } + + return status; +} + +/*! + * brief Gets default values for tamper pin configuration. + * + * This function fills the give structure with default values for the tamper pin and glitch filter configuration. + * The default values are: + * code + * pinConfig->pinPolarity = kTDET_TamperPinPolarityExpectNormal; + * pinConfig->pinDirection = kTDET_TamperPinDirectionIn; + * pinConfig->tamperPullEnable = false; + * pinConfig->tamperPinSampleFrequency = kTDET_GlitchFilterSamplingEveryCycle8; + * pinConfig->tamperPinSampleWidth = kTDET_GlitchFilterSampleDisable; + * pinConfig->glitchFilterEnable = false; + * pinConfig->glitchFilterPrescaler = kTDET_GlitchFilterClock512Hz; + * pinConfig->glitchFilterWidth = 0; + * pinConfig->tamperPinExpected = kTDET_GlitchFilterExpectedLogicZero; + * pinConfig->tamperPullSelect = kTDET_GlitchFilterPullTypeAssert; + * endcode + * + * param base TDET peripheral base address + * param[out] pinConfig Pointer to structure to be filled with tamper pins default parameters + */ +void TDET_PinGetDefaultConfig(DIGTMP_Type *base, tdet_pin_config_t *pinConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(pinConfig, 0, sizeof(*pinConfig)); + + struct _tdet_pin_config myPinDefaultConfig = { + kTDET_TamperPinPolarityExpectNormal, /* pinPolarity */ + kTDET_TamperPinDirectionIn, /* pinDirection */ + false, /* tamperPullEnable */ + kTDET_GlitchFilterSamplingEveryCycle8, /* tamperPinSampleFrequency */ + kTDET_GlitchFilterSampleDisable, /* tamperPinSampleWidth */ + false, /* glitchFilterEnable */ + kTDET_GlitchFilterClock512Hz, /* glitchFilterPrescaler */ + 0, /* glitchFilterWidth */ + kTDET_GlitchFilterExpectedLogicZero, /* tamperPinExpected */ + kTDET_GlitchFilterPullTypeAssert, /* tamperPullSelect */ + }; + + *pinConfig = myPinDefaultConfig; +} + +/*! + * brief Writes the tamper pin configuration. + * + * This function writes per pin parameters to tamper pin and glitch filter configuration registers. + * + * param base TDET peripheral base address + * param pinConfig Pointer to structure with tamper pin and glitch filter configuration parameters + * param pinSelect Bit mask for tamper pins to be configured. The passed value is combination of + * enum _tdet_external_tamper_pin (tdet_external_tamper_pin_t) values (OR'ed). + * return kStatus_Fail when writing to TDET Pin Direction, Pin Polarity or Glitch Filter Register(s) is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_PinSetConfig(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pinSelect) +{ + uint32_t mask; + status_t status; + uint32_t i, j; + + mask = 1u; + status = kStatus_Success; + j = ARRAY_SIZE(base->PGFR); + /* configure pin by pin, by moving through all selected pins */ + for (i = 0; i < j; i++) + { + if ((pinSelect & mask) != 0U) + { + /* clear this pin from pinSelect */ + pinSelect &= ~mask; + + /* configure this pin */ + status = tdet_PinConfigure(base, pinConfig, i); + + /* if pinSelect is zero, we have configured all pins selected by pinSelect, so skip */ + if ((status != kStatus_Success) || (0U == pinSelect)) + { + break; + } + } + mask = mask << 1u; + } + + return status; +} + +/*! + * brief Reads the Status Register. + * + * This function reads flag bits from TDET Status Register. + * + * param base TDET peripheral base address + * param[out] result Pointer to uint32_t where to write Status Register read value. Use tdet_status_flag_t to decode + * individual flags. + * return kStatus_Fail when Status Register reading is not allowed + * return kStatus_Success when result is written with the Status Register read value + */ +status_t TDET_GetStatusFlags(DIGTMP_Type *base, uint32_t *result) +{ + status_t status; + + if (result != NULL) + { + *result = base->SR; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Status Register. + * + * This function clears specified flag bits in TDET Status Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the flag bits to be cleared. Use tdet_status_flag_t to encode flags. + * return kStatus_Fail when Status Register writing is not allowed + * return kStatus_Success when mask is written to the Status Register + */ +status_t TDET_ClearStatusFlags(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_SRL_MASK)) + { + base->SR = mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Interrupt Enable Register. + * + * This function sets specified interrupt enable bits in TDET Interrupt Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the interrupt enable bits to be set. + * return kStatus_Fail when Interrupt Enable Register writing is not allowed + * return kStatus_Success when mask is written to the Interrupt Enable Register + */ +status_t TDET_EnableInterrupts(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_IER_MASK; /* only set the bits documented in Reference Manual. */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_IEL_MASK)) + { + base->IER |= mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Interrupt Enable Register. + * + * This function clears specified interrupt enable bits in TDET Interrupt Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the interrupt enable bits to be cleared. + * return kStatus_Fail when Interrupt Enable Register writing is not allowed + * return kStatus_Success when specified bits are cleared in the Interrupt Enable Register + */ +status_t TDET_DisableInterrupts(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_IER_MASK; /* only clear the bits documented in Reference Manual. */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_IEL_MASK)) + { + base->IER &= ~mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Enable Register. + * + * This function sets specified tamper enable bits in TDET Tamper Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the tamper enable bits to be set. + * return kStatus_Fail when Tamper Enable Register writing is not allowed + * return kStatus_Success when mask is written to the Tamper Enable Register + */ +status_t TDET_EnableTampers(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_TER_MASK; /* only set the bits documented in Reference Manual */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TEL_MASK)) + { + base->TER |= mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Enable Register. + * + * This function clears specified tamper enable bits in TDET Tamper Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the tamper enable bits to be cleared. + * return kStatus_Fail when Tamper Enable Register writing is not allowed + * return kStatus_Success when specified bits are cleared in the Tamper Enable Register + */ +status_t TDET_DisableTampers(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_TER_MASK; /* only clear the bits documented in Reference Manual */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TEL_MASK)) + { + base->TER &= ~mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Seconds Register. + * + * This function writes to TDET Tamper Seconds Register. This causes Status Register DTF flag to be set (TDET + * tampering detected). + * + * param base TDET peripheral base address + * return kStatus_Fail when Tamper Seconds Register writing is not allowed + * return kStatus_Success when Tamper Seconds Register is written + */ +status_t TDET_ForceTamper(DIGTMP_Type *base) +{ + status_t status; + + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TSL_MASK)) + { + base->TSR = 0; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Reads the Tamper Seconds Register. + * + * This function reads TDET Tamper Seconds Register. The read value returns the time in seconds at which the Status + * Register DTF flag was set. + * + * param base TDET peripheral base address + * param tamperTimeSeconds Time in seconds at which the tamper detection SR[DTF] flag was set. + * return kStatus_Fail when Tamper Seconds Register reading is not allowed + * return kStatus_Success when Tamper Seconds Register is read + */ +status_t TDET_GetTamperTimeSeconds(DIGTMP_Type *base, uint32_t *tamperTimeSeconds) +{ + status_t status; + + if (tamperTimeSeconds != NULL) + { + *tamperTimeSeconds = base->TSR; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the TDET Lock Register. + * + * This function clears specified lock bits in the TDET Lock Register. + * When a lock bit is clear, a write to corresponding TDET Register is ignored. + * Once cleared, these bits can only be set by VBAT POR or software reset. + * + * param base TDET peripheral base address + * param mask Bit mask for the lock bits to be cleared. Use tdet_register_t values to encode (OR'ed) which TDET + * Registers shall be locked. + */ +void TDET_LockRegisters(DIGTMP_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kTDET_AllRegisters; /* make sure only documented registers are selected by the mask */ + base->LR &= ~mask; /* clear the selected bits */ +} diff --git a/drivers/tdet/fsl_tdet.h b/drivers/tdet/fsl_tdet.h new file mode 100644 index 000000000..e56234933 --- /dev/null +++ b/drivers/tdet/fsl_tdet.h @@ -0,0 +1,601 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_TDET_H_ +#define FSL_TDET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup TDET + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines TDET driver version 2.1.0. + * + * Change log: + * - Version 2.1.0 + * - Added setting of disabling prescaler on tamper event into TDET_SetConfig() and TDET_GetDefaultConfig functions. + * - Version 2.0.0 + * - Initial version + */ +#define FSL_TDET_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief TDET Update Mode. + * + * These constants allow TDET interrupts to be cleared if no tampering has been detected, while still preventing + * the TDET Tamper Flag (SR[DTF]) from being cleared once it is set. + */ +typedef enum _tdet_update_mode +{ + kTDET_StatusLockNormal = 0U, /*!< TDET Status Register cannot be written when the Status Register Lock bit + within the Lock Register (LR[SRL]) is clear */ + kTDET_StatusLockWithTamper = 1U, /*!< TDET Status Register cannot be written when the Status Register Lock bit + within the Lock Register (LR[SRL]) is clear and TDET Tamper Flag (SR[DTF]) + is set*/ +} tdet_update_mode_t; + +/*! + * @brief TDET Active Tamper Clock Source. + * + * These constants define the clock source for Active Tamper Shift Register to configure in a TDET base. + */ +typedef enum _tdet_active_tamper_clock +{ + kTDET_ClockType1Hz = 0U, /*!< clocked by 1 Hz prescaler clock */ + kTDET_ClockType64Hz = 1U, /*!< clocked by 614 Hz prescaler clock */ +} tdet_active_tamper_clock_t; + +/*! + * @brief TDET Control Register. + * + * This structure defines values for TDET Control Register. + */ +typedef struct _tdet_config +{ + bool innerClockAndPrescalerEnable; /*!< Enable/disable 32768 Hz clock within TDET and the TDET prescaler that + generates 512 Hz, 64Hz and 1 Hz prescaler clocks */ + bool tamperForceSystemResetEnable; /*!< Enable/disable assertion of chip reset when tampering is detected */ + enum _tdet_update_mode updateMode; /*!< Selects update mode for TDET Status Register */ + enum _tdet_active_tamper_clock + clockSourceActiveTamper0; /*!< Selects clock source for Active Tamper Shift Register 0 */ + enum _tdet_active_tamper_clock + clockSourceActiveTamper1; /*!< Selects clock source for Active Tamper Shift Register 1 */ + bool disablePrescalerAfterTamper; /*!< Allows the 32-KHz clock and prescaler to be automatically disabled after + tamper detection and until the system acknowledges the tamper. Disabling the + prescaler after detecting a tamper event conserves power and freezes the state + of the active tamper outputs and glitch filters. To ensure a clean transition, + the prescaler is disabled at the end of a 1 Hz period. */ + uint32_t prescaler; /*!< Initial value for the TDET prescaler 15-bit value. */ +} tdet_config_t; + +/*! + * @brief TDET Tamper Pin Polarity. + * + * These constants define tamper pin polarity to configure in a TDET base. + */ +typedef enum _tdet_pin_polarity +{ + kTDET_TamperPinPolarityExpectNormal = 0U, /*!< Tamper pin expected value is not inverted */ + kTDET_TamperPinPolarityExpectInverted = 1U, /*!< Tamper pin expected value is inverted */ +} tdet_pin_polarity_t; + +/*! + * @brief TDET Tamper Pin Direction. + * + * These constants define tamper pin direction to configure in a TDET base. + */ +typedef enum _tdet_pin_direction +{ + kTDET_TamperPinDirectionIn = 0U, /*!< Tamper pins configured as input */ + kTDET_TamperPinDirectionOut = 1U, /*!< Tamper pins configured as output, drives inverse of expected value */ +} tdet_pin_direction_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Sample Frequency. + * + * These constants define tamper pin glitch filter sample frequency to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_sample_freq +{ + kTDET_GlitchFilterSamplingEveryCycle8 = 0U, /*!< Sample once every 8 cycles */ + kTDET_GlitchFilterSamplingEveryCycle32 = 1U, /*!< Sample once every 32 cycles */ + kTDET_GlitchFilterSamplingEveryCycle128 = 2U, /*!< Sample once every 128 cycles */ + kTDET_GlitchFilterSamplingEveryCycle512 = 3U, /*!< Sample once every 512 cycles */ +} tdet_glitch_filter_sample_freq_t; +/*! + * @brief TDET Glitch Filter Tamper Pin Sample Width. + * + * These constants define tamper pin glitch filter sample width to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_sample_width +{ + kTDET_GlitchFilterSampleDisable = 0U, /*!< Sampling disabled */ + kTDET_GlitchFilterSampleCycle2 = 1U, /*!< Sample width pull enable/input buffer enable=2 cycles/1 cycle */ + kTDET_GlitchFilterSampleCycle4 = 2U, /*!< Sample width pull enable/input buffer enable=4 cycles/2 cycles */ + kTDET_GlitchFilterSampleCycle8 = 3U, /*!< Sample width pull enable/input buffer enable=8 cycles/4 cycles */ +} tdet_glitch_filter_sample_width_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Clock Source. + * + * These constants define tamper pin glitch filter clock source to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_prescaler +{ + kTDET_GlitchFilterClock512Hz = 0U, /*!< Glitch Filter on tamper pin is clocked by the 512 Hz prescaler clock */ + kTDET_GlitchFilterClock32768Hz = 1U, /*!< Glitch Filter on tamper pin is clocked by the 32768 Hz prescaler clock */ +} tdet_glitch_filter_prescaler_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Expected Value. + * + * These constants define tamper pin glitch filter expected value to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_expected +{ + kTDET_GlitchFilterExpectedLogicZero = 0U, /*!< Expected value is logic zero */ + kTDET_GlitchFilterExpectedActTamperOut0 = 1U, /*!< Expected value is active tamper 0 output */ + kTDET_GlitchFilterExpectedActTamperOut1 = 2U, /*!< Expected value is active tamper 1 output */ + kTDET_GlitchFilterExpectedActTamperOutXOR = + 3U, /*!< Expected value is active tamper 0 output XORed with active tamper 1 output */ +} tdet_glitch_filter_expected_t; + +/*! + * @brief TDET Glitch Filter Tamper Pull Select. + * + * These constants define tamper pin glitch filter pull direction to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_pull +{ + kTDET_GlitchFilterPullTypeAssert = 0U, /*!< Tamper pin pull direction always asserts the tamper pin. */ + kTDET_GlitchFilterPullTypeNegate = 1U, /*!< Tamper pin pull direction always negates the tamper pin. */ +} tdet_glitch_filter_pull_t; + +/*! + * @brief TDET Tamper Pin configuration registers. + * + * This structure defines values for TDET Pin Direction, Pin Polarity, and Glitch Filter registers. + */ +typedef struct _tdet_pin_config +{ + enum _tdet_pin_polarity pinPolarity; /*!< Selects tamper pin expected value */ + enum _tdet_pin_direction pinDirection; /*!< Selects tamper pin direction */ + bool tamperPullEnable; /*!< Enable/disable pull resistor on the tamper pin */ + enum _tdet_glitch_filter_sample_freq tamperPinSampleFrequency; /*!< Selects tamper pin sample frequency */ + enum _tdet_glitch_filter_sample_width tamperPinSampleWidth; /*!< Selects tamper pin sample width */ + bool glitchFilterEnable; /*!< Enable/disable glitch filter on the tamper pin */ + enum _tdet_glitch_filter_prescaler + glitchFilterPrescaler; /*!< Selects the prescaler for the glitch filter on tamper pin */ + + uint8_t glitchFilterWidth; /*!< 6-bit value to configure number of clock edges the input must remain stable for to + be passed through the glitch filter for the tamper pin */ + + enum _tdet_glitch_filter_expected tamperPinExpected; /*!< Selects tamper pin expected value */ + enum _tdet_glitch_filter_pull tamperPullSelect; /*!< Selects the direction of the tamper pin pull resistor */ +} tdet_pin_config_t; + +/*! @brief List of TDET external tampers */ +typedef enum _tdet_external_tamper_pin +{ + kTDET_ExternalTamper0 = 1U << 0, + kTDET_ExternalTamper1 = 1U << 1, + kTDET_ExternalTamper2 = 1U << 2, + kTDET_ExternalTamper3 = 1U << 3, + kTDET_ExternalTamper4 = 1U << 4, + kTDET_ExternalTamper5 = 1U << 5, + kTDET_ExternalTamper6 = 1U << 6, + kTDET_ExternalTamper7 = 1U << 7 +} tdet_external_tamper_pin_t; + +/*! + * @brief TDET Active Tamper Register Select. + * + * These constants are used to define activeTamperRegisterSelect argument to be used with + * TDET_ActiveTamperConfigure(). + */ +typedef enum _tdet_active_tamper_register +{ + kTDET_ActiveTamperRegister0 = 1u << 0, + kTDET_ActiveTamperRegister1 = 1u << 1, +} tdet_active_tamper_register_t; + +/*! + * @brief TDET Active Tamper registers. + * + * This structure defines values for TDET Active Tamper Registers. + */ +typedef struct _tdet_active_tamper_config +{ + uint32_t activeTamperShift; /*!< Active tamper shift register. initialize to non-zero value. */ + uint32_t activeTamperPolynomial; /*!< Polynomial of the active tamper shift register. */ +} tdet_active_tamper_config_t; + +/*! + * @brief TDET Status Register flags. + * + * This provides constants for the TDET Status Register. + */ +typedef enum _tdet_status_flag +{ + kTDET_StatusTamperFlag = 1U << DIGTMP_SR_DTF_SHIFT, /*!< TDET Digital Tamper Flag */ + kTDET_StatusTamperAcknowledgeFlag = 1U << DIGTMP_SR_TAF_SHIFT, /*!< TDET Tamper Acknowledge Flag */ + kTDET_StatusClockTamper = 1U << DIGTMP_IER_TIIE0_SHIFT, /*!< TDET Clock Tamper detected */ + kTDET_StatusConfigurationTamper = 1U << DIGTMP_IER_TIIE1_SHIFT, /*!< TDET Configuration Tamper detected */ + kTDET_StatusVoltageTamper = 1U << DIGTMP_IER_TIIE2_SHIFT, /*!< TDET Voltage Tamper detected */ + kTDET_StatusTemperatureTamper = 1U << DIGTMP_IER_TIIE3_SHIFT, /*!< TDET Temperature Tamper detected */ + kTDET_StatusRamZeroizeTamper = 1U << DIGTMP_IER_TIIE6_SHIFT, /*!< TDET RAM Zeroize Tamper detected */ + kTDET_StatusTamperPinTamper0 = 1U << DIGTMP_IER_TPIE0_SHIFT, /*!< TDET Tamper Pin 0 Tamper detected */ + kTDET_StatusTamperPinTamper1 = 1U << DIGTMP_IER_TPIE1_SHIFT, /*!< TDET Tamper Pin 1 Tamper detected */ + kTDET_StatusTamperPinTamper2 = 1U << DIGTMP_IER_TPIE2_SHIFT, /*!< TDET Tamper Pin 2 Tamper detected */ + kTDET_StatusTamperPinTamper3 = 1U << DIGTMP_IER_TPIE3_SHIFT, /*!< TDET Tamper Pin 3 Tamper detected */ + kTDET_StatusTamperPinTamper4 = 1U << DIGTMP_IER_TPIE4_SHIFT, /*!< TDET Tamper Pin 4 Tamper detected */ + kTDET_StatusTamperPinTamper5 = 1U << DIGTMP_IER_TPIE5_SHIFT, /*!< TDET Tamper Pin 5 Tamper detected */ + kTDET_StatusTamperPinTamper6 = 1U << DIGTMP_IER_TPIE6_SHIFT, /*!< TDET Tamper Pin 6 Tamper detected */ + kTDET_StatusTamperPinTamper7 = 1U << DIGTMP_IER_TPIE7_SHIFT, /*!< TDET Tamper Pin 7 Tamper detected */ + kTDET_StatusAll = DIGTMP_SR_DTF_MASK | DIGTMP_SR_TAF_MASK | DIGTMP_IER_TIIE0_MASK | DIGTMP_IER_TIIE1_MASK | + DIGTMP_IER_TIIE2_MASK | DIGTMP_IER_TIIE3_MASK | DIGTMP_IER_TIIE6_MASK | DIGTMP_IER_TPIE0_MASK | + DIGTMP_IER_TPIE1_MASK | DIGTMP_IER_TPIE2_MASK | DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | + DIGTMP_IER_TPIE5_MASK | DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< Mask for all of the TDET Status Register bits */ +} tdet_status_flag_t; + +/*! + * @brief TDET Interrupt Enable Register. + * + * This provides constants for the TDET Interrupt Enable Register. + */ +typedef enum _tdet_interrupt +{ + kTDET_InterruptTamper = 1U << DIGTMP_IER_DTIE_SHIFT, /*!< TDET Digital Tamper Interrupt */ + kTDET_InterruptClockTamper = 1U << DIGTMP_IER_TIIE0_SHIFT, /*!< TDET Clock Tamper Interrupt */ + kTDET_InterruptConfigurationTamper = 1U << DIGTMP_IER_TIIE1_SHIFT, /*!< TDET Configuration error */ + kTDET_InterruptVoltageTamper = 1U << DIGTMP_IER_TIIE2_SHIFT, /*!< TDET Voltage Tamper */ + kTDET_InterruptTemperatureTamper = 1U << DIGTMP_IER_TIIE3_SHIFT, /*!< TDET Temperature Tamper Interrupt */ + kTDET_InterruptRamZeroizeTamper = 1U << DIGTMP_IER_TIIE6_SHIFT, /*!< TDET RAM Zeroize Tamper Interrupt */ + kTDET_InterruptTamperPinTamper0 = 1U << DIGTMP_IER_TPIE0_SHIFT, /*!< TDET Tamper Pin Tamper 0 Interrupt */ + kTDET_InterruptTamperPinTamper1 = 1U << DIGTMP_IER_TPIE1_SHIFT, /*!< TDET Tamper Pin Tamper 1 Interrupt */ + kTDET_InterruptTamperPinTamper2 = 1U << DIGTMP_IER_TPIE2_SHIFT, /*!< TDET Tamper Pin Tamper 2 Interrupt */ + kTDET_InterruptTamperPinTamper3 = 1U << DIGTMP_IER_TPIE3_SHIFT, /*!< TDET Tamper Pin Tamper 3 Interrupt */ + kTDET_InterruptTamperPinTamper4 = 1U << DIGTMP_IER_TPIE4_SHIFT, /*!< TDET Tamper Pin Tamper 4 Interrupt */ + kTDET_InterruptTamperPinTamper5 = 1U << DIGTMP_IER_TPIE5_SHIFT, /*!< TDET Tamper Pin Tamper 5 Interrupt */ + kTDET_InterruptTamperPinTamper6 = 1U << DIGTMP_IER_TPIE6_SHIFT, /*!< TDET Tamper Pin Tamper 6 Interrupt */ + kTDET_InterruptTamperPinTamper7 = 1U << DIGTMP_IER_TPIE7_SHIFT, /*!< TDET Tamper Pin Tamper 7 Interrupt */ + kTDET_InterruptTamperPinTamper_All = DIGTMP_IER_TPIE0_MASK | DIGTMP_IER_TPIE1_MASK | DIGTMP_IER_TPIE2_MASK | + DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | DIGTMP_IER_TPIE5_MASK | + DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< TDET All Tamper Pins Interrupt */ + kTDET_InterruptAll = DIGTMP_IER_DTIE_MASK | DIGTMP_IER_TIIE0_MASK | DIGTMP_IER_TIIE1_MASK | DIGTMP_IER_TIIE2_MASK | + DIGTMP_IER_TIIE3_MASK | DIGTMP_IER_TIIE6_MASK | DIGTMP_IER_TPIE0_MASK | DIGTMP_IER_TPIE1_MASK | + DIGTMP_IER_TPIE2_MASK | DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | DIGTMP_IER_TPIE5_MASK | + DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< Mask to select all TDET Interrupt Enable Register bits */ +} tdet_interrupt_t; + +/*! + * @brief TDET Tamper Enable Register. + * + * This provides constants for the TDET Tamper Enable Register. + */ +typedef enum _tdet_tamper +{ + kTDET_TamperClock = 1U << DIGTMP_TER_TIE0_SHIFT, /*!< Clock Tamper Enable */ + kTDET_TamperConfiguration = 1U << DIGTMP_TER_TIE1_SHIFT, /*!< Configuration error Tamper Enable */ + kTDET_TamperVoltage = 1U << DIGTMP_TER_TIE2_SHIFT, /*!< Voltage Tamper Enable */ + kTDET_TamperTemperature = 1U << DIGTMP_TER_TIE3_SHIFT, /*!< Temperature Tamper Enable */ + kTDET_TamperRamZeroize = 1U << DIGTMP_TER_TIE6_SHIFT, /*!< RAM Zeroize Tamper Enable */ + kTDET_TamperTamperPin0 = 1U << DIGTMP_TER_TPE0_SHIFT, /*!< Tamper Pin 0 Tamper Enable */ + kTDET_TamperTamperPin1 = 1U << DIGTMP_TER_TPE1_SHIFT, /*!< Tamper Pin 1 Tamper Enable */ + kTDET_TamperTamperPin2 = 1U << DIGTMP_TER_TPE2_SHIFT, /*!< Tamper Pin 2 Tamper Enable */ + kTDET_TamperTamperPin3 = 1U << DIGTMP_TER_TPE3_SHIFT, /*!< Tamper Pin 3 Tamper Enable */ + kTDET_TamperTamperPin4 = 1U << DIGTMP_TER_TPE4_SHIFT, /*!< Tamper Pin 4 Tamper Enable */ + kTDET_TamperTamperPin5 = 1U << DIGTMP_TER_TPE5_SHIFT, /*!< Tamper Pin 5 Tamper Enable */ + kTDET_TamperTamperPin6 = 1U << DIGTMP_TER_TPE6_SHIFT, /*!< Tamper Pin 6 Tamper Enable */ + kTDET_TamperTamperPin7 = 1U << DIGTMP_TER_TPE7_SHIFT, /*!< Tamper Pin 7 Tamper Enable */ + kTDET_TamperTamperPinAll = DIGTMP_TER_TPE0_MASK | DIGTMP_TER_TPE1_MASK | DIGTMP_TER_TPE2_MASK | + DIGTMP_TER_TPE3_MASK | DIGTMP_TER_TPE4_MASK | DIGTMP_TER_TPE5_MASK | + DIGTMP_TER_TPE6_MASK | DIGTMP_TER_TPE7_MASK, /*!< All Tamper Pin Tamper Enable */ + kTDET_TamperAll = DIGTMP_TER_TIE0_MASK | DIGTMP_TER_TIE1_MASK | DIGTMP_TER_TIE2_MASK | DIGTMP_TER_TIE3_MASK | + DIGTMP_TER_TIE6_MASK | DIGTMP_TER_TPE0_MASK | DIGTMP_TER_TPE1_MASK | DIGTMP_TER_TPE2_MASK | + DIGTMP_TER_TPE3_MASK | DIGTMP_TER_TPE4_MASK | DIGTMP_TER_TPE5_MASK | DIGTMP_TER_TPE6_MASK | + DIGTMP_TER_TPE7_MASK, /*!< Mask to select all Tamper Enable Register bits */ +} tdet_tamper_t; + +/*! + * @brief TDET Registers. + * + * This provides constants to encode a mask for the TDET Registers. + */ +typedef enum _tdet_register +{ + kTDET_NoRegister = 0U, /*!< No Register */ + kTDET_Control = 1U << DIGTMP_LR_CRL_SHIFT, /*!< Control Register */ + kTDET_Status = 1U << DIGTMP_LR_SRL_SHIFT, /*!< Status Register */ + kTDET_Lock = 1U << DIGTMP_LR_LRL_SHIFT, /*!< Lock Register */ + kTDET_InterruptEnable = 1U << DIGTMP_LR_IEL_SHIFT, /*!< Interrupt Enable Register */ + kTDET_TamperSeconds = 1U << DIGTMP_LR_TSL_SHIFT, /*!< Tamper Seconds Register */ + kTDET_TamperEnable = 1U << DIGTMP_LR_TEL_SHIFT, /*!< Tamper Enable Register */ + kTDET_PinDirection = 1U << DIGTMP_LR_PDL_SHIFT, /*!< Pin Direction Register */ + kTDET_PinPolarity = 1U << DIGTMP_LR_PPL_SHIFT, /*!< Pin Polarity Register */ + kTDET_ActiveTamper0 = 1U << DIGTMP_LR_ATL0_SHIFT, /*!< Active Tamper Register 0 */ + kTDET_ActiveTamper1 = 1U << DIGTMP_LR_ATL1_SHIFT, /*!< Active Tamper Register 1 */ + kTDET_GlitchFilter0 = 1U << DIGTMP_LR_GFL0_SHIFT, /*!< Glitch Filter Register 0 */ + kTDET_GlitchFilter1 = 1U << DIGTMP_LR_GFL1_SHIFT, /*!< Glitch Filter Register 1 */ + kTDET_GlitchFilter2 = 1U << DIGTMP_LR_GFL2_SHIFT, /*!< Glitch Filter Register 2 */ + kTDET_GlitchFilter3 = 1U << DIGTMP_LR_GFL3_SHIFT, /*!< Glitch Filter Register 3 */ + kTDET_GlitchFilter4 = 1U << DIGTMP_LR_GFL4_SHIFT, /*!< Glitch Filter Register 4 */ + kTDET_GlitchFilter5 = 1U << DIGTMP_LR_GFL5_SHIFT, /*!< Glitch Filter Register 5 */ + kTDET_GlitchFilter6 = 1U << DIGTMP_LR_GFL6_SHIFT, /*!< Glitch Filter Register 6 */ + kTDET_GlitchFilter7 = 1U << DIGTMP_LR_GFL7_SHIFT, /*!< Glitch Filter Register 7 */ + kTDET_PinConfigurationRegisters = + DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | DIGTMP_LR_ATL0_MASK | DIGTMP_LR_ATL1_MASK | DIGTMP_LR_GFL0_MASK | + DIGTMP_LR_GFL1_MASK | DIGTMP_LR_GFL2_MASK | DIGTMP_LR_GFL3_MASK | DIGTMP_LR_GFL4_MASK | DIGTMP_LR_GFL5_MASK | + DIGTMP_LR_GFL6_MASK | DIGTMP_LR_GFL7_MASK, /*!< Mask to select all TDET Pin Configuration Registers */ + kTDET_AllRegisters = DIGTMP_LR_CRL_MASK | DIGTMP_LR_SRL_MASK | DIGTMP_LR_LRL_MASK | DIGTMP_LR_IEL_MASK | + DIGTMP_LR_TSL_MASK | DIGTMP_LR_TEL_MASK | DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | + DIGTMP_LR_ATL0_MASK | DIGTMP_LR_ATL1_MASK | DIGTMP_LR_GFL0_MASK | DIGTMP_LR_GFL1_MASK | + DIGTMP_LR_GFL2_MASK | DIGTMP_LR_GFL3_MASK | DIGTMP_LR_GFL4_MASK | DIGTMP_LR_GFL5_MASK | + DIGTMP_LR_GFL6_MASK | DIGTMP_LR_GFL7_MASK, /*!< Mask to select all TDET Registers */ +} tdet_register_t; + +/******************************************************************************* + * API + *******************************************************************************/ +extern void VBAT0_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name TDET Functional Operation + * @{ + */ + +/*! + * @brief Initialize TDET + * + * This function initializes TDET. + * + * @param base TDET peripheral base address + * @return Status of the init operation + */ +status_t TDET_Init(DIGTMP_Type *base); + +/*! + * @brief Deinitialize TDET + * + * This function disables glitch filters and active tampers + * This function disables the TDET clock and prescaler in TDET Control Register. + * @param base TDET peripheral base address + */ +void TDET_Deinit(DIGTMP_Type *base); + +/*! + * @brief Gets default values for the TDET Control Register. + * + * This function fills the given structure with default values for the TDET Control Register. + * The default values are: + * @code + * defaultConfig->innerClockAndPrescalerEnable = true + * defaultConfig->tamperForceSystemResetEnable = false + * defaultConfig->updateMode = kTDET_StatusLockWithTamper + * defaultConfig->clockSourceActiveTamper0 = kTDET_ClockType1Hz + * defaultConfig->clockSourceActiveTamper1 = kTDET_ClockType1Hz + * defaultConfig->prescaler = 0 + * @endcode + * @param base TDET peripheral base address + * @param[out] defaultConfig Pointer to structure to be filled with default parameters + */ +void TDET_GetDefaultConfig(DIGTMP_Type *base, tdet_config_t *defaultConfig); + +/*! + * @brief Writes to the TDET Control Register. + * + * This function writes the given structure to the TDET Control Register. + * @param base TDET peripheral base address + * @param config Pointer to structure with TDET peripheral configuration parameters + * @return kStatus_Fail when writing to TDET Control Register is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_SetConfig(DIGTMP_Type *base, const tdet_config_t *config); + +/*! + * @brief Software reset. + * + * This function resets all TDET registers. The CR[SWR] itself is not affected; + * it is reset by VBAT POR only. + * + * @param base TDET peripheral base address + * @return kStatus_Fail when writing to TDET Control Register is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_SoftwareReset(DIGTMP_Type *base); + +/*! + * @brief Writes to the active tamper register(s). + * + * This function writes per active tamper register parameters to active tamper register(s). + * + * @param base TDET peripheral base address + * @param activeTamperConfig Pointer to structure with active tamper register parameters + * @param activeTamperRegisterSelect Bit mask for active tamper registers to be configured. The passed value is + * combination of tdet_active_tamper_register_t values (OR'ed). + * @return kStatus_Fail when writing to TDET Active Tamper Register(s) is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_ActiveTamperSetConfig(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegisterSelect); + +/*! + * @brief Gets default values for tamper pin configuration. + * + * This function fills the give structure with default values for the tamper pin and glitch filter configuration. + * The default values are: + * code + * pinConfig->pinPolarity = kTDET_TamperPinPolarityExpectNormal; + * pinConfig->pinDirection = kTDET_TamperPinDirectionIn; + * pinConfig->tamperPullEnable = false; + * pinConfig->tamperPinSampleFrequency = kTDET_GlitchFilterSamplingEveryCycle8; + * pinConfig->tamperPinSampleWidth = kTDET_GlitchFilterSampleDisable; + * pinConfig->glitchFilterEnable = false; + * pinConfig->glitchFilterPrescaler = kTDET_GlitchFilterClock512Hz; + * pinConfig->glitchFilterWidth = 0; + * pinConfig->tamperPinExpected = kTDET_GlitchFilterExpectedLogicZero; + * pinConfig->tamperPullSelect = kTDET_GlitchFilterPullTypeAssert; + * endcode + * + * @param base TDET peripheral base address + * @param[out] pinConfig Pointer to structure to be filled with tamper pins default parameters + */ + +void TDET_PinGetDefaultConfig(DIGTMP_Type *base, tdet_pin_config_t *pinConfig); + +/*! + * @brief Writes the tamper pin configuration. + * + * This function writes per pin parameters to tamper pin and glitch filter configuration registers. + * + * @param base TDET peripheral base address + * @param pinConfig Pointer to structure with tamper pin and glitch filter configuration parameters + * @param pinSelect Bit mask for tamper pins to be configured. The passed value is combination of + * enum _tdet_tamper_pin (tdet_tamper_pin_t) values (OR'ed). + * @return kStatus_Fail when writing to TDET Pin Direction, Pin Polarity or Glitch Filter Register(s) is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_PinSetConfig(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pinSelect); + +/*! + * @brief Reads the Status Register. + * + * This function reads flag bits from TDET Status Register. + * + * @param base TDET peripheral base address + * @param[out] result Pointer to uint32_t where to write Status Register read value. Use tdet_status_flag_t to decode + * individual flags. + * @return kStatus_Fail when Status Register reading is not allowed + * @return kStatus_Success when result is written with the Status Register read value + */ +status_t TDET_GetStatusFlags(DIGTMP_Type *base, uint32_t *result); + +/*! + * @brief Writes to the Status Register. + * + * This function clears specified flag bits in TDET Status Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the flag bits to be cleared. Use tdet_status_flag_t to encode flags. + * @return kStatus_Fail when Status Register writing is not allowed + * @return kStatus_Success when mask is written to the Status Register + */ +status_t TDET_ClearStatusFlags(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Interrupt Enable Register. + * + * This function sets specified interrupt enable bits in TDET Interrupt Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the interrupt enable bits to be set. + * @return kStatus_Fail when Interrupt Enable Register writing is not allowed + * @return kStatus_Success when mask is written to the Interrupt Enable Register + */ +status_t TDET_EnableInterrupts(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Interrupt Enable Register. + * + * This function clears specified interrupt enable bits in TDET Interrupt Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the interrupt enable bits to be cleared. + * @return kStatus_Fail when Interrupt Enable Register writing is not allowed + * @return kStatus_Success when specified bits are cleared in the Interrupt Enable Register + */ +status_t TDET_DisableInterrupts(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Enable Register. + * + * This function sets specified tamper enable bits in TDET Tamper Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the tamper enable bits to be set. + * @return kStatus_Fail when Tamper Enable Register writing is not allowed + * @return kStatus_Success when mask is written to the Tamper Enable Register + */ +status_t TDET_EnableTampers(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Enable Register. + * + * This function clears specified tamper enable bits in TDET Tamper Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the tamper enable bits to be cleared. + * @return kStatus_Fail when Tamper Enable Register writing is not allowed + * @return kStatus_Success when specified bits are cleared in the Tamper Enable Register + */ +status_t TDET_DisableTampers(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Seconds Register. + * + * This function writes to TDET Tamper Seconds Register. This causes Status Register DTF flag to be set (TDET + * tampering detected). + * + * @param base TDET peripheral base address + * @return kStatus_Fail when Tamper Seconds Register writing is not allowed + * @return kStatus_Success when Tamper Seconds Register is written + */ +status_t TDET_ForceTamper(DIGTMP_Type *base); + +/*! + * @brief Reads the Tamper Seconds Register. + * + * This function reads TDET Tamper Seconds Register. The read value returns the time in seconds at which the Status + * Register DTF flag was set. + * + * @param base TDET peripheral base address + * @param tamperTimeSeconds Time in seconds at which the tamper detection SR[DTF] flag was set. + * @return kStatus_Fail when Tamper Seconds Register reading is not allowed + * @return kStatus_Success when Tamper Seconds Register is read + */ +status_t TDET_GetTamperTimeSeconds(DIGTMP_Type *base, uint32_t *tamperTimeSeconds); + +/*! + * @brief Writes to the TDET Lock Register. + * + * This function clears specified lock bits in the TDET Lock Register. + * When a lock bit is clear, a write to corresponding TDET Register is ignored. + * Once cleared, these bits can only be set by VBAT POR or software reset. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the lock bits to be cleared. Use tdet_register_t values to encode (OR'ed) which TDET + * Registers shall be locked. + */ +void TDET_LockRegisters(DIGTMP_Type *base, uint32_t mask); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group tdet */ + +#endif /* FSL_TDET_H_ */ diff --git a/drivers/utick/fsl_utick.h b/drivers/utick/fsl_utick.h index 48c7d6b86..836b518f4 100644 --- a/drivers/utick/fsl_utick.h +++ b/drivers/utick/fsl_utick.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ +#ifndef FSL_UTICK_H_ +#define FSL_UTICK_H_ #include "fsl_common.h" /*! @@ -115,4 +115,4 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); /*! @}*/ -#endif /* _FSL_UTICK_H_ */ +#endif /* FSL_UTICK_H_ */ diff --git a/drivers/vref_1/fsl_vref.c b/drivers/vref_1/fsl_vref.c index d0ab8ebf3..fd8ee68ae 100644 --- a/drivers/vref_1/fsl_vref.c +++ b/drivers/vref_1/fsl_vref.c @@ -46,8 +46,18 @@ static uint32_t VREF_GetInstance(VREF_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_vrefBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) { + /* + * $Branch Coverage Justification$ + * (s_vrefBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ if (s_vrefBases[instance] == base) { break; @@ -86,57 +96,50 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config) CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Enable low power bandgap at first. */ - tmp32 = VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK | VREF_CSR_VRSEL(config->vrefSel); + base->CSR |= VREF_CSR_LPBGEN_MASK; + /* After enabling low power bandgap, delay 20 us. */ + SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Configure buffer mode. */ - switch (config->bufferMode) + /* Provides bias current for other peripherals. */ + if (config->enableLowPowerBuff) { - case kVREF_ModeBandgapOnly: - break; - case kVREF_ModeLowPowerBuffer: - tmp32 |= VREF_CSR_BUF21EN_MASK; - break; - case kVREF_ModeHighPowerBuffer: - tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); - break; - default: - assert(false); - break; + base->CSR |= VREF_CSR_LPBG_BUF_EN_MASK; } - /* Enable internal voltage regulator */ - if (config->enableInternalVoltageRegulator) + if (config->bufferMode != kVREF_ModeBandgapOnly) { - /* Enable internal voltage regulator to provide the optimum VREF performance. */ - tmp32 |= VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK | VREF_CSR_ICOMPEN_MASK; - base->CSR = tmp32; - /* After enabling low power bandgap, delay 20 us. */ - SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Enable high accurancy bandgap for vref output. */ - if (config->enableVrefOut) + if (config->enableHCBandgap) { - base->CSR |= VREF_CSR_HCBGEN_MASK; + tmp32 |= VREF_CSR_HCBGEN_MASK; } - /* After enabling high accurancy bandgap, delay 400 us. */ - SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - } - else - { - /* Enable high accurancy bandgap for vref output. */ - if (config->enableVrefOut) + + if (config->enableInternalVoltageRegulator) { - tmp32 |= VREF_CSR_HCBGEN_MASK; - base->CSR = tmp32; - /* Wait until internal voltage stable */ - while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) - { - } + tmp32 |= VREF_CSR_REGEN_MASK; + } + + if (config->enableChopOscillator) + { + tmp32 |= (VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK); + } + + if (config->enableCurvatureCompensation) + { + tmp32 |= VREF_CSR_ICOMPEN_MASK; + } + + if (config->bufferMode == kVREF_ModeLowPowerBuffer) + { + tmp32 |= VREF_CSR_BUF21EN_MASK; } else { - base->CSR = tmp32; + tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); } + + base->CSR |= tmp32; + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); } } @@ -171,8 +174,10 @@ void VREF_Deinit(VREF_Type *base) * code * config->bufferMode = kVREF_ModeHighPowerBuffer; * config->enableInternalVoltageRegulator = true; - * config->enableVrefOut = true; - * config->vrefSel = kVREF_InternalBandgap; + * config->enableChopOscillator = true; + * config->enableHCBandgap = true; + * config->enableCurvatureCompensation = true; + * config->enableLowPowerBuff = true; * endcode * * param config Pointer to the initialization structure. @@ -186,8 +191,10 @@ void VREF_GetDefaultConfig(vref_config_t *config) config->bufferMode = kVREF_ModeHighPowerBuffer; config->enableInternalVoltageRegulator = true; - config->enableVrefOut = true; - config->vrefSel = kVREF_InternalBandgap; + config->enableChopOscillator = true; + config->enableHCBandgap = true; + config->enableCurvatureCompensation = true; + config->enableLowPowerBuff = true; } /*! @@ -214,6 +221,12 @@ void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) } else { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) { } @@ -230,17 +243,14 @@ void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. * * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + * param trim21Value Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). */ void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) { uint32_t tmp32 = base->UTRIM; - if (VREF_CSR_BUF21EN_MASK == (base->CSR & VREF_CSR_BUF21EN_MASK)) - { - tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK); - tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value); - } + tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK); + tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value); base->UTRIM = tmp32; @@ -251,6 +261,12 @@ void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) } else { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) { } @@ -258,7 +274,7 @@ void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) } /*! - * brief Reads the VREF trim value.. + * brief Reads the VREF trim value. * * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) * @@ -275,7 +291,7 @@ uint8_t VREF_GetVrefTrimVal(VREF_Type *base) } /*! - * brief Reads the VREF 2.1V trim value.. + * brief Reads the VREF 2.1V trim value. * * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), * diff --git a/drivers/vref_1/fsl_vref.h b/drivers/vref_1/fsl_vref.h index 51ff4bb92..99689610c 100644 --- a/drivers/vref_1/fsl_vref.h +++ b/drivers/vref_1/fsl_vref.h @@ -1,12 +1,12 @@ /* - * Copyright 2019-2022 NXP + * Copyright 2019-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_VREF_H_ -#define _FSL_VREF_H_ +#ifndef FSL_VREF_H_ +#define FSL_VREF_H_ #include "fsl_common.h" @@ -21,32 +21,27 @@ /*! @name Driver version */ /*@{*/ -#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2. */ /*@}*/ /*! @brief VREF buffer modes. */ typedef enum _vref_buffer_mode { kVREF_ModeBandgapOnly = 0U, /*!< Bandgap enabled/standby. */ - kVREF_ModeLowPowerBuffer = 1U, /*!< High-power buffer mode enabled */ - kVREF_ModeHighPowerBuffer = 2U /*!< Low-power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 1U, /*!< Low-power buffer mode enabled */ + kVREF_ModeHighPowerBuffer = 2U, /*!< High-power buffer mode enabled */ } vref_buffer_mode_t; -/*! @brief Voltage reference selection. */ -typedef enum _vref_voltage_reference_sel -{ - kVREF_InternalBandgap = 0U, /*!< Internal bandgap. */ - kVREF_LowPowerBuffed1v = 1U, /*!< Low power buffered 1v. */ - kVREF_LowPowerBufferMode = 2U, /*!< Low-power buffer mode enabled. */ -} vref_voltage_reference_sel_t; - /*! @brief The description structure for the VREF module. */ typedef struct _vref_config { - vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ - bool enableInternalVoltageRegulator; /*!< Provide additional supply noise rejection. */ - bool enableVrefOut; /*!< Enable the VREF supply voltage on VREF_OUT. */ - vref_voltage_reference_sel_t vrefSel; /*!< Control voltage reference selection */ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ + bool enableInternalVoltageRegulator; /*!< Provide additional supply noise rejection. */ + bool enableChopOscillator; /*!< Enable Chop oscillator.*/ + bool enableHCBandgap; /*!< Enable High-Accurate bandgap.*/ + bool enableCurvatureCompensation; /*!< Enable second order curvature compensation. */ + bool enableLowPowerBuff; /*!< Provides bias current for other peripherals.*/ + } vref_config_t; /****************************************************************************** @@ -105,8 +100,10 @@ void VREF_Deinit(VREF_Type *base); * @code * config->bufferMode = kVREF_ModeHighPowerBuffer; * config->enableInternalVoltageRegulator = true; - * config->enableVrefOut = true; - * config->vrefSel = kVREF_InternalBandgap; + * config->enableChopOscillator = true; + * config->enableHCBandgap = true; + * config->enableCurvatureCompensation = true; + * config->enableLowPowerBuff = true; * @endcode * * @param config Pointer to the initialization structure. @@ -121,46 +118,46 @@ void VREF_GetDefaultConfig(vref_config_t *config); */ /*! - * brief Sets a TRIM value for the accurate 1.0V bandgap output. + * @brief Sets a TRIM value for the accurate 1.0V bandgap output. * * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). */ void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue); /*! - * brief Sets a TRIM value for the accurate buffered VREF output. + * @brief Sets a TRIM value for the accurate buffered VREF output. * * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. * - * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the + * @note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. * - * param base VREF peripheral address. - * param trimValue Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + * @param base VREF peripheral address. + * @param trim21Value Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). */ void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value); /*! - * brief Reads the VREF trim value.. + * @brief Reads the trim value. * * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) * - * param base VREF peripheral address. - * return 6-bit value of trim setting. + * @param base VREF peripheral address. + * @return 6-bit value of trim setting. */ uint8_t VREF_GetVrefTrimVal(VREF_Type *base); /*! - * brief Reads the VREF 2.1V trim value.. + * @brief Reads the VREF 2.1V trim value. * * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), * - * param base VREF peripheral address. - * return 4-bit value of trim setting. + * @param base VREF peripheral address. + * @return 4-bit value of trim setting. */ uint8_t VREF_GetTrim21Val(VREF_Type *base); @@ -172,4 +169,4 @@ uint8_t VREF_GetTrim21Val(VREF_Type *base); /*! @}*/ -#endif /* _FSL_VREF_H_ */ +#endif /* FSL_VREF_H_ */ diff --git a/drivers/wuu/fsl_wuu.c b/drivers/wuu/fsl_wuu.c new file mode 100644 index 000000000..453907ba4 --- /dev/null +++ b/drivers/wuu/fsl_wuu.c @@ -0,0 +1,292 @@ +/* + * Copyright 2019-2023 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wuu.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wuu" +#endif + +#define WUU_PE_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PDC_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PMC_REG_BIT_FIELD_MASK 0x01UL + +#define WUU_ME_REG_WUME_FIELD_MASK 0x01UL +#define WUU_DE_REG_WUME_FIELD_MASK 0x01UL + +#define WUU_FILT_REG_FILTE_FIELD_MASK 0x60U +#define WUU_FILT_REG_FILTSET_FIELD_MASK 0x1FU +#define WUU_FDC_REG_FILTC_FIELD_MASK 0x3U +#define WUU_FMC_REG_FILTM_FIELD_MASK 0x1U + +#define WUU_FILT_REG_FILTSET_FIELD(x) (((uint32_t)(x) << 5UL) & WUU_FILT_REG_FILTE_FIELD_MASK) +#define WUU_CLEAR_BIT_FIELD_IN_REG(mask, offset) (~((uint32_t)(mask) << (offset))) +#define WUU_SET_BIT_FIELD_IN_REG(val, offset) ((uint32_t)(val) << (offset)) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * param base MUU peripheral base address. + * param pinIndex The index of the external input pin. See Reference Manual for the details. + * param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config) +{ + assert(config != NULL); + + volatile uint32_t *edgeRegBase = NULL; + volatile uint32_t *eventRegBase = NULL; + uint32_t edgeReg; + uint32_t eventReg; + uint32_t modeReg; + uint8_t offset; + + /* Calculate offset. */ + offset = 2U * (pinIndex & 0xFU); + + if (config->edge != kWUU_ExternalPinDisable) + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + eventRegBase = &base->PDC2; + } + else + { + edgeRegBase = &base->PE1; + eventRegBase = &base->PDC1; + } + + /* Enable and config the edge detection. */ + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + edgeReg |= WUU_SET_BIT_FIELD_IN_REG(config->edge, offset); + *edgeRegBase = edgeReg; + + /* Config the wakeup event. */ + eventReg = *eventRegBase; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PDC_REG_BIT_FIELD_MASK, offset); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, offset); + *eventRegBase = eventReg; + + /* Config operate mode. */ + modeReg = base->PMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PMC_REG_BIT_FIELD_MASK, pinIndex); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, pinIndex); + + base->PMC = modeReg; + } + else + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + } + else + { + edgeRegBase = &base->PE1; + } + + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + *edgeRegBase = edgeReg; + } +} + +/*! + * brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch (event) + { + case kWUU_InternalModuleInterrupt: + base->ME |= WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE |= WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Disable an on-chip internal modules' event as the wakeup sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch(event) + { + case kWUU_InternalModuleInterrupt: + base->ME &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * param base WUU peripheral base address. + * param filterIndex The index of the pin filer. + * param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config) +{ + assert(config != NULL); + + uint8_t shift; + uint32_t filterReg; + uint32_t eventReg; + uint32_t modeReg; + + shift = (filterIndex - 1U) * 8U; + filterReg = base->FILT; + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTE_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD(config->edge), shift); + + if (config->edge != kWUU_FilterDisabled) + { + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(config->pinIndex, shift); + + /* Config wake up event. */ + shift = (filterIndex - 1U) * 2U; + eventReg = base->FDC; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FDC_REG_FILTC_FIELD_MASK, shift); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, shift); + base->FDC = eventReg; + + /* Config operate mode. */ + shift = (filterIndex - 1U) * 1U; + modeReg = base->FMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FMC_REG_FILTM_FIELD_MASK, shift); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, shift); + base->FMC = modeReg; + } + + base->FILT = filterReg; +} + +/*! + * brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index, which starts from 1. + * return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + bool ret = false; + + switch (filterIndex) + { + case 1: + ret = ((base->FILT & WUU_FILT_FILTF1_MASK) != 0U); + break; + case 2: + ret = ((base->FILT & WUU_FILT_FILTF2_MASK) != 0U); + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + uint32_t reg; + + reg = base->FILT; + /* Clean the W1C bits, in case the flags are cleared by mistake. */ + reg &= ~(WUU_FILT_FILTF1_MASK | WUU_FILT_FILTF2_MASK); + + reg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_FILTF1_MASK, ((filterIndex - 1U) * 8U)); + + base->FILT = reg; +} + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + return (0U != (base->PF & (1UL << pinIndex))); +} + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + base->PF = (1UL << pinIndex); +} diff --git a/drivers/wuu/fsl_wuu.h b/drivers/wuu/fsl_wuu.h new file mode 100644 index 000000000..87a2ae13f --- /dev/null +++ b/drivers/wuu/fsl_wuu.h @@ -0,0 +1,286 @@ +/* + * Copyright 2019-2023 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WUU_H_ +#define FSL_WUU_H_ + +#include "fsl_common.h" + +/*! @addtogroup wuu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WUU driver version 2.3.0. */ +#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! + * @brief External WakeUp pin edge detection enumeration. + */ +typedef enum _wuu_external_pin_edge_detection +{ + kWUU_ExternalPinDisable = 0x0U, /*!< External input Pin disabled as wake up input. */ + kWUU_ExternalPinRisingEdge = 0x1U, /*!< External input Pin enabled with the rising edge detection. */ + kWUU_ExternalPinFallingEdge = 0x2U, /*!< External input Pin enabled with the falling edge detection. */ + kWUU_ExternalPinAnyEdge = 0x3U, /*!< External input Pin enabled with any change detection. */ +} wuu_external_pin_edge_detection_t; + +/*! + * @brief External input wake up pin event enumeration. + */ +typedef enum _wuu_external_wakeup_pin_event +{ + kWUU_ExternalPinInterrupt = 0x0U, /*!< External input Pin configured as interrupt. */ + kWUU_ExternalPinDMARequest = 0x1U, /*!< External input Pin configured as DMA request. */ + kWUU_ExternalPinTriggerEvent = 0x2U, /*!< External input Pin configured as Trigger event. */ +} wuu_external_wakeup_pin_event_t; + +/*! + * @brief External input wake up pin mode enumeration. + */ +typedef enum _wuu_external_wakeup_pin_mode +{ + kWUU_ExternalPinActiveDSPD = 0x0U, /*!< External input Pin is active only during Deep Sleep/Power Down Mode. */ + kWUU_ExternalPinActiveAlways = 0x1U, /*!< External input Pin is active during all power modes. */ +} wuu_external_wakeup_pin_mode_t; + +/*! + * @brief Internal module wake up event enumeration. + */ +typedef enum _wuu_internal_wakeup_module_event +{ + kWUU_InternalModuleInterrupt = 0x0U, /*!< Internal modules' interrupt as a wakeup source. */ + kWUU_InternalModuleDMATrigger = 0x1U, /*!< Internal modules' DMA/Trigger as a wakeup source. */ +} wuu_internal_wakeup_module_event_t; + +/*! + * @brief Pin filter edge enumeration. + */ +typedef enum _wuu_filter_edge +{ + kWUU_FilterDisabled = 0x0U, /*!< Filter disabled. */ + kWUU_FilterPosedgeEnable = 0x1U, /*!< Filter posedge detect enabled. */ + kWUU_FilterNegedgeEnable = 0x2U, /*!< Filter negedge detect enabled. */ + kWUU_FilterAnyEdge = 0x3U, /*!< Filter any edge detect enabled. */ +} wuu_filter_edge_t; + +/*! + * @brief Pin Filter event enumeration. + */ +typedef enum _wuu_filter_event +{ + kWUU_FilterInterrupt = 0x0U, /*!< Filter output configured as interrupt. */ + kWUU_FilterDMARequest = 0x1U, /*!< Filter output configured as DMA request. */ + kWUU_FilterTriggerEvent = 0x2U, /*!< Filter output configured as Trigger event. */ +} wuu_filter_event_t; + +/*! + * @brief Pin filter mode enumeration. + */ +typedef enum _wuu_filter_mode +{ + kWUU_FilterActiveDSPD = 0x0U, /*!< External input pin filter is active only during Deep Sleep/Power Down Mode. */ + kWUU_FilterActiveAlways = 0x1U, /*!< External input Pin filter is active during all power modes. */ +} wuu_filter_mode_t; + +/*! + * @brief External WakeUp pin configuration + */ +typedef struct _wuu_external_wakeup_pin_config +{ + wuu_external_pin_edge_detection_t edge; /*!< External Input pin edge detection. */ + wuu_external_wakeup_pin_event_t event; /*!< External Input wakeup Pin event */ + wuu_external_wakeup_pin_mode_t mode; /*!< External Input wakeup Pin operate mode. */ +} wuu_external_wakeup_pin_config_t; + +/*! + * @brief Pin Filter configuration. + */ +typedef struct _wuu_pin_filter_config +{ + uint32_t pinIndex; /*!< The index of wakeup pin to be muxxed into filter. */ + wuu_filter_edge_t edge; /*!< The edge of the pin digital filter. */ + wuu_filter_event_t event; /*!< The event of the filter output. */ + wuu_filter_mode_t mode; /*!< The mode of the filter operate. */ +} wuu_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name External Wake up Pins Control APIs. + * @{ + */ +/*! + * @brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * @param base MUU peripheral base address. + * @param pinIndex The index of the external input pin. See Reference Manual for the details. + * @param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config); + +/*! + * @brief Gets External Wakeup pin flags. + * + * This function return the external wakeup pin flags. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all external wakeup pins. + */ +static inline uint32_t WUU_GetExternalWakeUpPinsFlag(WUU_Type *base) +{ + return base->PF; +} + +/*! + * @brief Clears External WakeUp Pin flags. + * + * This function clears external wakeup pins flags based on the mask. + * + * @param base WUU peripheral base address. + * @param mask The mask of Wakeup pin index to be cleared. + */ +static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask) +{ + base->PF = mask; +} +/* @} */ + +/*! + * @name Internal Wakeup Module control APIs. + * @{ + */ + +/*! + * @brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +/*! + * @brief Disable an on-chip internal modules' event as the wakeup sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +#if (defined(FSL_FEATURE_WUU_HAS_MF) && FSL_FEATURE_WUU_HAS_MF) +/*! + * @brief Get wakeup flags for internal wakeup modules. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all internal wakeup modules. + */ +static inline uint32_t WUU_GetModuleInterruptFlag(WUU_Type *base) +{ + return base->MF; +} + +/*! + * @brief Gets the internal module wakeup source flag. + * + * This function checks the flag to detect whether the system is + * woken up by specific on-chip module interrupt. + * + * @param base WWU peripheral base address. + * @param moduleIndex A module index, which starts from 0. + * @return True if the specific pin is a wake up source. + */ +static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t moduleIndex) +{ + return ((1UL << moduleIndex) == (WUU_GetModuleInterruptFlag(base) & (1UL << moduleIndex))); +} +#endif /* FSL_FEATURE_WUU_HAS_MF */ + +/* @} */ + +/*! + * @name Pin Filter Control APIs + * @{ + */ +/*! + * @brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * @param base WUU peripheral base address. + * @param filterIndex The index of the pin filer. + * @param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index, which starts from 1. + * @return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * @brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*FSL_WUU_H_*/ diff --git a/drivers/wwdt/fsl_wwdt.h b/drivers/wwdt/fsl_wwdt.h index 254625349..e1ee183dd 100644 --- a/drivers/wwdt/fsl_wwdt.h +++ b/drivers/wwdt/fsl_wwdt.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ +#ifndef FSL_WWDT_H_ +#define FSL_WWDT_H_ #include "fsl_common.h" @@ -273,4 +273,4 @@ void WWDT_Refresh(WWDT_Type *base); /*! @}*/ -#endif /* _FSL_WWDT_H_ */ +#endif /* FSL_WWDT_H_ */ diff --git a/manifests/FRDM-MCXN236_manifest_v3_13.xml b/manifests/FRDM-MCXN236_manifest_v3_13.xml new file mode 100644 index 000000000..115a5ea81 --- /dev/null +++ b/manifests/FRDM-MCXN236_manifest_v3_13.xml @@ -0,0 +1,9307 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FRDM-MCXN236 + + + + + + + + 150 MHz Arm® Cortex-M33 TrustZone® microcontroller for Industrial and Consumer IoT Applications. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/cmake_toolchain_files/mcux_config.cmake b/tools/cmake_toolchain_files/mcux_config.cmake index 05e0a92b5..d76844273 100644 --- a/tools/cmake_toolchain_files/mcux_config.cmake +++ b/tools/cmake_toolchain_files/mcux_config.cmake @@ -2,6 +2,7 @@ function(set_library LIBRARY_TYPE LANGUAGE) set(EXTRADEFINES " -fstack-usage ") if(${LIBRARY_TYPE} STREQUAL "REDLIB") + set(SPECS "-specs=redlib.specs" PARENT_SCOPE) set(EXTRADEFINES "${EXTRADEFINES} -D__REDLIB__") set(TARGET_LINK_SYSTEM_LIBRARIES "-lcr_c -lcr_eabihelpers -lgcc" PARENT_SCOPE) elseif(${LIBRARY_TYPE} STREQUAL "NEWLIB") @@ -12,6 +13,7 @@ elseif(${LIBRARY_TYPE} STREQUAL "NEWLIB") set(TARGET_LINK_SYSTEM_LIBRARIES "-lgcc -lc -lm" PARENT_SCOPE) endif() elseif(${LIBRARY_TYPE} STREQUAL "NEWLIB_NANO") + set(SPECS "--specs=nano.specs" PARENT_SCOPE) set(EXTRADEFINES "${EXTRADEFINES} -D__NEWLIB__") if(${LANGUAGE} STREQUAL "CPP") set(TARGET_LINK_SYSTEM_LIBRARIES "-lstdc++_nano crti.o crtn.o crtbegin.o crtend.o" PARENT_SCOPE) @@ -44,9 +46,8 @@ endfunction() function(set_debug_console DEBUG_CONSOLE LIBRARY_TYPE) if(${DEBUG_CONSOLE} MATCHES "SEMIHOST") - set(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=0" PARENT_SCOPE) + set(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=0 -DSDK_USE_SYSCALL_STUB=0" PARENT_SCOPE) else() - set(SPECS "--specs=nano.specs --specs=nosys.specs" PARENT_SCOPE) set(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1" PARENT_SCOPE) endif() diff --git a/utilities/debug_console/fsl_debug_console.c b/utilities/debug_console/fsl_debug_console.c index d5730edf7..4782b99e1 100644 --- a/utilities/debug_console/fsl_debug_console.c +++ b/utilities/debug_console/fsl_debug_console.c @@ -1002,8 +1002,8 @@ status_t DbgConsole_Deinit(void) } #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ -#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE > DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN))) || \ - ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))) || \ + ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) { diff --git a/utilities/debug_console_lite/fsl_debug_console.c b/utilities/debug_console_lite/fsl_debug_console.c index 6489bf760..88efbe200 100644 --- a/utilities/debug_console_lite/fsl_debug_console.c +++ b/utilities/debug_console_lite/fsl_debug_console.c @@ -124,23 +124,23 @@ status_t DbgConsole_Deinit(void) /* See fsl_debug_console.h for documentation of this function. */ status_t DbgConsole_EnterLowpower(void) { - hal_uart_status_t status = kStatus_HAL_UartError; + hal_uart_status_t DbgConsoleUartStatus = kStatus_HAL_UartError; if (kSerialPort_Uart == s_debugConsole.serial_port_type) { - status = HAL_UartEnterLowpower((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); + DbgConsoleUartStatus = HAL_UartEnterLowpower((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); } - return (status_t)status; + return (status_t)DbgConsoleUartStatus; } /* See fsl_debug_console.h for documentation of this function. */ status_t DbgConsole_ExitLowpower(void) { - hal_uart_status_t status = kStatus_HAL_UartError; + hal_uart_status_t DbgConsoleUartStatus = kStatus_HAL_UartError; if (kSerialPort_Uart == s_debugConsole.serial_port_type) { - status = HAL_UartExitLowpower((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); + DbgConsoleUartStatus = HAL_UartExitLowpower((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); } - return (status_t)status; + return (status_t)DbgConsoleUartStatus; } #endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */ diff --git a/utilities/str/fsl_str.c b/utilities/str/fsl_str.c index fde141375..bffbcda04 100644 --- a/utilities/str/fsl_str.c +++ b/utilities/str/fsl_str.c @@ -542,12 +542,12 @@ static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int ne uc = 0ULL; uc_param = 0ULL; #else - a = 0; - b = 0; - c = 0; - ua = 0U; - ub = 0U; - uc = 0U; + a = 0; + b = 0; + c = 0; + ua = 0U; + ub = 0U; + uc = 0U; uc_param = 0U; #endif /* PRINTF_ADVANCED_ENABLE */ @@ -1300,71 +1300,71 @@ static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t else #endif /* SCANF_FLOAT_ENABLE */ if (((*c) >= '0') && ((*c) <= '9')) - { { - char *p; - errno = 0; - (*field_width) = strtoul(c, &p, 10); - if (0 != errno) { - *field_width = 0U; + char *p; + errno = 0; + (*field_width) = strtoul(c, &p, 10); + if (0 != errno) + { + *field_width = 0U; + } + c = p - 1; } - c = p - 1; } - } - else if ('d' == (*c)) - { - (*base) = 10U; - (*flag) |= (uint32_t)kSCANF_TypeSinged; - (*flag) |= (uint32_t)kSCANF_DestInt; - } - else if ('u' == (*c)) - { - (*base) = 10U; - (*flag) |= (uint32_t)kSCANF_DestInt; - } - else if ('o' == (*c)) - { - (*base) = 8U; - (*flag) |= (uint32_t)kSCANF_DestInt; - } - else if (('x' == (*c))) - { - (*base) = 16U; - (*flag) |= (uint32_t)kSCANF_DestInt; - } - else if ('X' == (*c)) - { - (*base) = 16U; - (*flag) |= (uint32_t)kSCANF_DestInt; - } - else if ('i' == (*c)) - { - (*base) = 0U; - (*flag) |= (uint32_t)kSCANF_DestInt; - } + else if ('d' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_TypeSinged; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('u' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('o' == (*c)) + { + (*base) = 8U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if (('x' == (*c))) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('X' == (*c)) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('i' == (*c)) + { + (*base) = 0U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } #if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U)) - else if (1U == StrFormatScanIsFloat(c)) - { - (*flag) |= (uint32_t)kSCANF_DestFloat; - } + else if (1U == StrFormatScanIsFloat(c)) + { + (*flag) |= (uint32_t)kSCANF_DestFloat; + } #endif /* SCANF_FLOAT_ENABLE */ - else if ('c' == (*c)) - { - (*flag) |= (uint32_t)kSCANF_DestChar; - if (MAX_FIELD_WIDTH == (*field_width)) + else if ('c' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestChar; + if (MAX_FIELD_WIDTH == (*field_width)) + { + (*field_width) = 1; + } + } + else if ('s' == (*c)) { - (*field_width) = 1; + (*flag) |= (uint32_t)kSCANF_DestString; + } + else + { + exitPending = 1U; } - } - else if ('s' == (*c)) - { - (*flag) |= (uint32_t)kSCANF_DestString; - } - else - { - exitPending = 1U; - } if (1U == exitPending) { @@ -1408,7 +1408,7 @@ int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) int32_t val; - uint8_t added; + uint8_t added = 0U; uint8_t exitPending = 0; @@ -1462,7 +1462,6 @@ int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) flag = 0; field_width = MAX_FIELD_WIDTH; base = 0; - added = 0U; exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base); @@ -1568,7 +1567,6 @@ int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) else { char *tempEnd; - val = 0; errno = 0; val = (int32_t)strtoul(p, &tempEnd, (int)base); if (0 != errno) @@ -1587,7 +1585,6 @@ int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat) { n_decode += ScanIgnoreWhiteSpace(&p); - fnum = 0.0; errno = 0; fnum = strtod(p, (char **)&s_temp); diff --git a/utilities/unity/gcov_support.c b/utilities/unity/gcov_support.c index 9ccbbfd0b..b9bfb740f 100644 --- a/utilities/unity/gcov_support.c +++ b/utilities/unity/gcov_support.c @@ -65,7 +65,7 @@ void gcov_write(void) { #if GCOV_USE_TCOV tcov_print_all(); /* print coverage information */ -#elif GCOV_USE_GCOV_EMBEDDED +#elif 0 && GCOV_USE_GCOV_EMBEDDED void gcov_exit(void); gcov_exit(); diff --git a/utilities/unity/linkscripts/main_text.ldt b/utilities/unity/linkscripts/main_text.ldt index c32a33ebe..cb8670fb4 100644 --- a/utilities/unity/linkscripts/main_text.ldt +++ b/utilities/unity/linkscripts/main_text.ldt @@ -1,13 +1,13 @@ - /************************************************ - * start of main_text.ldt: * - ************************************************/ - *(.text*) - /* added in template for gcov: */ - . = ALIGN(8); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - /************************************************ - * end of main_text.ldt * - ************************************************/ + /************************************************ + * start of main_text.ldt: * + ************************************************/ + *(.text*) + /* added in template for gcov: */ + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + /************************************************ + * end of main_text.ldt * + ************************************************/ diff --git a/utilities/unity/unity.c b/utilities/unity/unity.c index 092da3aa2..d74cd9a19 100644 --- a/utilities/unity/unity.c +++ b/utilities/unity/unity.c @@ -12,6 +12,117 @@ #include "gcov_support.h" #endif +/* This is SquishCoco code coverage tool related code */ +#ifdef __COVERAGESCANNER__ + +extern void __coveragescanner_set_custom_io(char *(*csfgets)(char *s, int size, void *stream), + int (*csfputs)(const char *s, void *stream), + void *(*csfopenappend)(const char *path), + void *(*csfopenread)(const char *path), + void *(*csfopenwrite)(const char *path), + int (*csfclose)(void *fp), + int (*csremove)(const char *filename)); +extern void __coveragescanner_save(void); +extern void __coveragescanner_testname(const char *name); +extern void __coveragescanner_teststate(const char *state); + +/* Use preprocessor macro from the following list to chose the way results are stored: + SQUISHCOCO_RESULT_DATA_SAVE_TO_FILE + SQUISHCOCO_RESULT_DATA_SAVE_TO_MEMORY + SQUISHCOCO_RESULT_DATA_SAVE_TO_CONSOLE +*/ +#if ((!defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_FILE)) && (!defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_MEMORY)) && \ + (!defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_CONSOLE)) && (!defined(SQUISHCOCO_RESULT_DATA_SAVE_CUSTOM))) +#define SQUISHCOCO_RESULT_DATA_SAVE_TO_CONSOLE + +/* Squish Coco I/O functions set implementation */ +int csfputs(const char *s, void *stream); +void *csfopenappend(const char *path); +int csfclose(void *fp); +void *csfopenwrite(const char *path); + +#else + +/* Squish Coco I/O functions implemented externally */ +extern int csfputs(const char *s, void *stream); +extern void *csfopenappend(const char *path); +extern int csfclose(void *fp); +extern void *csfopenwrite(const char *path); + +#endif + +#if defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_FILE) +void *csfopenwrite(const char *path) +{ + return (void *)fopen("../measurements.csexe", "w"); +} + +int csfputs(const char *s, void *stream) +{ + return fputs(s, (FILE *)stream); +} + +void *csfopenappend(const char *path) +{ + return (void *)fopen(path, "a+"); +} + +int csfclose(void *fp) +{ + return fclose((FILE *)fp); +} +#elif defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_MEMORY) +uint32_t mem_offset = 0x10U; +#define SH_MEM_TOTAL_SIZE (6144U) +#if defined(__ICCARM__) /* IAR Workbench */ +#pragma location = "rpmsg_sh_mem_section" +static uint8_t mem_to_store_coverage_results[SH_MEM_TOTAL_SIZE]; +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /* Keil MDK */ +static char mem_to_store_coverage_results[SH_MEM_TOTAL_SIZE] __attribute__((section("rpmsg_sh_mem_section"))); +#elif defined(__GNUC__) +static char mem_to_store_coverage_results[SH_MEM_TOTAL_SIZE] __attribute__((section(".noinit.$rpmsg_sh_mem"))); +#endif +int csfputs(const char *s, void *stream) +{ + int return_value = 0; + uint32_t len = strlen(s); + memcpy((void *)(char *)(mem_to_store_coverage_results + mem_offset), s, len); + mem_offset += len; + return return_value; +} + +static uint32_t stream = 0; +void *csfopenappend(const char *path) +{ + return &stream; +} + +int csfclose(void *fp) +{ + return 0; +} +#elif defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_CONSOLE) +int csfputs(const char *s, void *stream) +{ + int return_value = 0; + uint16_t len = strlen(s); + uint16_t status = PRINTF("%s", (char *)s); + return return_value; +} + +static uint32_t stream = 0; +void *csfopenappend(const char *path) +{ + return &stream; +} + +int csfclose(void *fp) +{ + return 0; +} +#endif /* SQUISHCOCO_RESULT_DATA_SAVE_TO_x */ +#endif /*__COVERAGESCANNER__*/ + #ifdef UNITY_DUMP_RESULT #if defined(UNITY_DUMP_RESULT_ARRAY_SMALL) #define DUMP_RESULT_ARRAY_SIZE 20U @@ -1432,6 +1543,15 @@ void UnityBegin(void) Unity.CurrentTestFailed = 0; Unity.CurrentTestIgnored = 0; +#ifdef __COVERAGESCANNER__ + /* Define the Squish Coco set of I/O functions */ +#ifdef SQUISHCOCO_RESULT_DATA_SAVE_TO_FILE + __coveragescanner_set_custom_io(NULL, csfputs, csfopenappend, NULL, csfopenwrite, csfclose, NULL); +#else + __coveragescanner_set_custom_io(NULL, csfputs, csfopenappend, NULL, NULL, csfclose, NULL); +#endif /* SQUISHCOCO_RESULT_DATA_SAVE_TO_FILE */ +#endif /*__COVERAGESCANNER__*/ + #if GCOV_DO_COVERAGE /* Currently, only MCUXPresso support this function. */ #if (defined(__GNUC__) && defined(__MCUXPRESSO)) @@ -1463,10 +1583,18 @@ int UnityEnd(void) if (Unity.TestFailures == 0U) { UnityPrintOk(); +#ifdef __COVERAGESCANNER__ + /* Set the state of the current test */ + __coveragescanner_teststate("PASSED"); +#endif /*__COVERAGESCANNER__*/ } else { UnityPrintFail(); +#ifdef __COVERAGESCANNER__ + /* Set the state of the current test */ + __coveragescanner_teststate("FAILED"); +#endif /*__COVERAGESCANNER__*/ } UNITY_PRINT_EOL; @@ -1496,6 +1624,16 @@ int UnityEnd(void) #ifdef UNITY_DUMP_RESULT UnityMemDumpEntry(); #endif + +#ifdef __COVERAGESCANNER__ + //__coveragescanner_testname(Unity.CurrentTestName); + /* Save the execution report and reset the status of all instrumentations */ + __coveragescanner_save(); +#if defined(SQUISHCOCO_RESULT_DATA_SAVE_TO_MEMORY) + ((uint32_t *)mem_to_store_coverage_results)[0] = mem_offset - 0x10; +#endif +#endif /*__COVERAGESCANNER__*/ + /*do not return for MCU*/ // while(1); return Unity.TestFailures; diff --git a/utilities/unity/unity.h b/utilities/unity/unity.h index 728402cfd..936c9eaf5 100644 --- a/utilities/unity/unity.h +++ b/utilities/unity/unity.h @@ -179,6 +179,16 @@ enum _unity_module k_unity_dsp = 164, k_unity_common = 165, k_unity_dcic = 166, + k_unity_imu = 167, + k_unity_maestro = 168, + k_unity_clock = 169, + k_unity_spc = 170, + k_unity_cmc = 171, + k_unity_ccm32k = 172, + k_unity_wuu = 173, + k_unity_sfa = 174, + k_unity_pm = 175, + k_unity_dac14 = 176, }; #define MAKE_UNITY_NUM(unity_module, caseID) (((uint32_t)(unity_module)*10000) + (uint32_t)(caseID)) @@ -226,16 +236,13 @@ enum _unity_module //------------------------------------------------------- // Test Running Macros //------------------------------------------------------- -#ifndef TEST_PROTECT_NOT_IMPLEMENTED + #define TEST_PROTECT() (setjmp(Unity.AbortFrame) == 0) #define TEST_ABORT() \ { \ longjmp(Unity.AbortFrame, 1); \ } -#else -#define TEST_PROTECT() (1) -#endif #ifndef RUN_EXAMPLE #ifdef UNITY_SHOW_TEST_FILE_PATH diff --git a/west.yml b/west.yml index 8ed0a2cb7..a6138143b 100644 --- a/west.yml +++ b/west.yml @@ -10,17 +10,17 @@ manifest: remote: nxp-mcuxpresso projects: - name: mcux-sdk-examples - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x path: examples - name: FreeRTOS-Kernel - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x path: rtos/freertos/freertos-kernel - name: mcux-sdk-middleware-sdmmc revision: MCUX_2.14.0 path: middleware/sdmmc - name: mcux-sdk-middleware-multicore path: middleware/multicore - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: rpmsg-lite path: middleware/multicore/rpmsg_lite url: https://github.com/nxp-mcuxpresso/rpmsg-lite @@ -28,13 +28,13 @@ manifest: - name: erpc path: middleware/multicore/erpc url: https://github.com/EmbeddedRPC/erpc - revision: 1.11.0 + revision: 09af912f9776b4f386d26d77435864ea61fb41d5 - name: mcux-soc-svd - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x path: svd - name: fatfs path: middleware/fatfs - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: mcux-sdk-middleware-eiq revision: MCUX_2.14.0 path: middleware/eiq @@ -49,7 +49,7 @@ manifest: path: middleware/eiq/tensorflow-lite - name: mcux-sdk-middleware-usb path: middleware/usb - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: mcux-sdk-middleware-edgefast-bluetooth path: middleware/edgefast_bluetooth revision: MCUX_2.14.0 @@ -87,7 +87,7 @@ manifest: remote: nxp - name: mbedtls path: middleware/mbedtls - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: wifi_nxp path: middleware/wifi_nxp revision: MCUX_2.14.0 @@ -97,10 +97,10 @@ manifest: revision: MCUX_2.14.0 - name: littlefs path: middleware/littlefs - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: maestro path: middleware/maestro - revision: MCUX_2.14.0 + revision: MCUX_2.14.0_MCXN23x - name: mcuboot path: middleware/mcuboot_opensource revision: MCUX_2.14.0